1 //===-- X86ISelLowering.cpp - X86 DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that X86 uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "x86-isel"
16 #include "X86ISelLowering.h"
18 #include "X86InstrBuilder.h"
19 #include "X86TargetMachine.h"
20 #include "X86TargetObjectFile.h"
21 #include "Utils/X86ShuffleDecode.h"
22 #include "llvm/CallingConv.h"
23 #include "llvm/Constants.h"
24 #include "llvm/DerivedTypes.h"
25 #include "llvm/GlobalAlias.h"
26 #include "llvm/GlobalVariable.h"
27 #include "llvm/Function.h"
28 #include "llvm/Instructions.h"
29 #include "llvm/Intrinsics.h"
30 #include "llvm/LLVMContext.h"
31 #include "llvm/CodeGen/IntrinsicLowering.h"
32 #include "llvm/CodeGen/MachineFrameInfo.h"
33 #include "llvm/CodeGen/MachineFunction.h"
34 #include "llvm/CodeGen/MachineInstrBuilder.h"
35 #include "llvm/CodeGen/MachineJumpTableInfo.h"
36 #include "llvm/CodeGen/MachineModuleInfo.h"
37 #include "llvm/CodeGen/MachineRegisterInfo.h"
38 #include "llvm/MC/MCAsmInfo.h"
39 #include "llvm/MC/MCContext.h"
40 #include "llvm/MC/MCExpr.h"
41 #include "llvm/MC/MCSymbol.h"
42 #include "llvm/ADT/SmallSet.h"
43 #include "llvm/ADT/Statistic.h"
44 #include "llvm/ADT/StringExtras.h"
45 #include "llvm/ADT/VariadicFunction.h"
46 #include "llvm/Support/CallSite.h"
47 #include "llvm/Support/Debug.h"
48 #include "llvm/Support/ErrorHandling.h"
49 #include "llvm/Support/MathExtras.h"
50 #include "llvm/Target/TargetOptions.h"
54 STATISTIC(NumTailCalls, "Number of tail calls");
56 // Forward declarations.
57 static SDValue getMOVL(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1,
60 /// Generate a DAG to grab 128-bits from a vector > 128 bits. This
61 /// sets things up to match to an AVX VEXTRACTF128 instruction or a
62 /// simple subregister reference. Idx is an index in the 128 bits we
63 /// want. It need not be aligned to a 128-bit bounday. That makes
64 /// lowering EXTRACT_VECTOR_ELT operations easier.
65 static SDValue Extract128BitVector(SDValue Vec, unsigned IdxVal,
66 SelectionDAG &DAG, DebugLoc dl) {
67 EVT VT = Vec.getValueType();
68 assert(VT.getSizeInBits() == 256 && "Unexpected vector size!");
69 EVT ElVT = VT.getVectorElementType();
70 int Factor = VT.getSizeInBits()/128;
71 EVT ResultVT = EVT::getVectorVT(*DAG.getContext(), ElVT,
72 VT.getVectorNumElements()/Factor);
74 // Extract from UNDEF is UNDEF.
75 if (Vec.getOpcode() == ISD::UNDEF)
76 return DAG.getUNDEF(ResultVT);
78 // Extract the relevant 128 bits. Generate an EXTRACT_SUBVECTOR
79 // we can match to VEXTRACTF128.
80 unsigned ElemsPerChunk = 128 / ElVT.getSizeInBits();
82 // This is the index of the first element of the 128-bit chunk
84 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits()) / 128)
87 SDValue VecIdx = DAG.getConstant(NormalizedIdxVal, MVT::i32);
88 SDValue Result = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, ResultVT, Vec,
94 /// Generate a DAG to put 128-bits into a vector > 128 bits. This
95 /// sets things up to match to an AVX VINSERTF128 instruction or a
96 /// simple superregister reference. Idx is an index in the 128 bits
97 /// we want. It need not be aligned to a 128-bit bounday. That makes
98 /// lowering INSERT_VECTOR_ELT operations easier.
99 static SDValue Insert128BitVector(SDValue Result, SDValue Vec,
100 unsigned IdxVal, SelectionDAG &DAG,
102 EVT VT = Vec.getValueType();
103 assert(VT.getSizeInBits() == 128 && "Unexpected vector size!");
105 EVT ElVT = VT.getVectorElementType();
106 EVT ResultVT = Result.getValueType();
108 // Insert the relevant 128 bits.
109 unsigned ElemsPerChunk = 128/ElVT.getSizeInBits();
111 // This is the index of the first element of the 128-bit chunk
113 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits())/128)
116 SDValue VecIdx = DAG.getConstant(NormalizedIdxVal, MVT::i32);
117 Result = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResultVT, Result, Vec,
122 /// Concat two 128-bit vectors into a 256 bit vector using VINSERTF128
123 /// instructions. This is used because creating CONCAT_VECTOR nodes of
124 /// BUILD_VECTORS returns a larger BUILD_VECTOR while we're trying to lower
125 /// large BUILD_VECTORS.
126 static SDValue Concat128BitVectors(SDValue V1, SDValue V2, EVT VT,
127 unsigned NumElems, SelectionDAG &DAG,
129 SDValue V = Insert128BitVector(DAG.getUNDEF(VT), V1, 0, DAG, dl);
130 return Insert128BitVector(V, V2, NumElems/2, DAG, dl);
133 static TargetLoweringObjectFile *createTLOF(X86TargetMachine &TM) {
134 const X86Subtarget *Subtarget = &TM.getSubtarget<X86Subtarget>();
135 bool is64Bit = Subtarget->is64Bit();
137 if (Subtarget->isTargetEnvMacho()) {
139 return new X8664_MachoTargetObjectFile();
140 return new TargetLoweringObjectFileMachO();
143 if (Subtarget->isTargetELF())
144 return new TargetLoweringObjectFileELF();
145 if (Subtarget->isTargetCOFF() && !Subtarget->isTargetEnvMacho())
146 return new TargetLoweringObjectFileCOFF();
147 llvm_unreachable("unknown subtarget type");
150 X86TargetLowering::X86TargetLowering(X86TargetMachine &TM)
151 : TargetLowering(TM, createTLOF(TM)) {
152 Subtarget = &TM.getSubtarget<X86Subtarget>();
153 X86ScalarSSEf64 = Subtarget->hasSSE2();
154 X86ScalarSSEf32 = Subtarget->hasSSE1();
155 X86StackPtr = Subtarget->is64Bit() ? X86::RSP : X86::ESP;
157 RegInfo = TM.getRegisterInfo();
158 TD = getTargetData();
160 // Set up the TargetLowering object.
161 static const MVT IntVTs[] = { MVT::i8, MVT::i16, MVT::i32, MVT::i64 };
163 // X86 is weird, it always uses i8 for shift amounts and setcc results.
164 setBooleanContents(ZeroOrOneBooleanContent);
165 // X86-SSE is even stranger. It uses -1 or 0 for vector masks.
166 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
168 // For 64-bit since we have so many registers use the ILP scheduler, for
169 // 32-bit code use the register pressure specific scheduling.
170 // For 32 bit Atom, use Hybrid (register pressure + latency) scheduling.
171 if (Subtarget->is64Bit())
172 setSchedulingPreference(Sched::ILP);
173 else if (Subtarget->isAtom())
174 setSchedulingPreference(Sched::Hybrid);
176 setSchedulingPreference(Sched::RegPressure);
177 setStackPointerRegisterToSaveRestore(X86StackPtr);
179 if (Subtarget->isTargetWindows() && !Subtarget->isTargetCygMing()) {
180 // Setup Windows compiler runtime calls.
181 setLibcallName(RTLIB::SDIV_I64, "_alldiv");
182 setLibcallName(RTLIB::UDIV_I64, "_aulldiv");
183 setLibcallName(RTLIB::SREM_I64, "_allrem");
184 setLibcallName(RTLIB::UREM_I64, "_aullrem");
185 setLibcallName(RTLIB::MUL_I64, "_allmul");
186 setLibcallCallingConv(RTLIB::SDIV_I64, CallingConv::X86_StdCall);
187 setLibcallCallingConv(RTLIB::UDIV_I64, CallingConv::X86_StdCall);
188 setLibcallCallingConv(RTLIB::SREM_I64, CallingConv::X86_StdCall);
189 setLibcallCallingConv(RTLIB::UREM_I64, CallingConv::X86_StdCall);
190 setLibcallCallingConv(RTLIB::MUL_I64, CallingConv::X86_StdCall);
192 // The _ftol2 runtime function has an unusual calling conv, which
193 // is modeled by a special pseudo-instruction.
194 setLibcallName(RTLIB::FPTOUINT_F64_I64, 0);
195 setLibcallName(RTLIB::FPTOUINT_F32_I64, 0);
196 setLibcallName(RTLIB::FPTOUINT_F64_I32, 0);
197 setLibcallName(RTLIB::FPTOUINT_F32_I32, 0);
200 if (Subtarget->isTargetDarwin()) {
201 // Darwin should use _setjmp/_longjmp instead of setjmp/longjmp.
202 setUseUnderscoreSetJmp(false);
203 setUseUnderscoreLongJmp(false);
204 } else if (Subtarget->isTargetMingw()) {
205 // MS runtime is weird: it exports _setjmp, but longjmp!
206 setUseUnderscoreSetJmp(true);
207 setUseUnderscoreLongJmp(false);
209 setUseUnderscoreSetJmp(true);
210 setUseUnderscoreLongJmp(true);
213 // Set up the register classes.
214 addRegisterClass(MVT::i8, &X86::GR8RegClass);
215 addRegisterClass(MVT::i16, &X86::GR16RegClass);
216 addRegisterClass(MVT::i32, &X86::GR32RegClass);
217 if (Subtarget->is64Bit())
218 addRegisterClass(MVT::i64, &X86::GR64RegClass);
220 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
222 // We don't accept any truncstore of integer registers.
223 setTruncStoreAction(MVT::i64, MVT::i32, Expand);
224 setTruncStoreAction(MVT::i64, MVT::i16, Expand);
225 setTruncStoreAction(MVT::i64, MVT::i8 , Expand);
226 setTruncStoreAction(MVT::i32, MVT::i16, Expand);
227 setTruncStoreAction(MVT::i32, MVT::i8 , Expand);
228 setTruncStoreAction(MVT::i16, MVT::i8, Expand);
230 // SETOEQ and SETUNE require checking two conditions.
231 setCondCodeAction(ISD::SETOEQ, MVT::f32, Expand);
232 setCondCodeAction(ISD::SETOEQ, MVT::f64, Expand);
233 setCondCodeAction(ISD::SETOEQ, MVT::f80, Expand);
234 setCondCodeAction(ISD::SETUNE, MVT::f32, Expand);
235 setCondCodeAction(ISD::SETUNE, MVT::f64, Expand);
236 setCondCodeAction(ISD::SETUNE, MVT::f80, Expand);
238 // Promote all UINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have this
240 setOperationAction(ISD::UINT_TO_FP , MVT::i1 , Promote);
241 setOperationAction(ISD::UINT_TO_FP , MVT::i8 , Promote);
242 setOperationAction(ISD::UINT_TO_FP , MVT::i16 , Promote);
244 if (Subtarget->is64Bit()) {
245 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote);
246 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
247 } else if (!TM.Options.UseSoftFloat) {
248 // We have an algorithm for SSE2->double, and we turn this into a
249 // 64-bit FILD followed by conditional FADD for other targets.
250 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
251 // We have an algorithm for SSE2, and we turn this into a 64-bit
252 // FILD for other targets.
253 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Custom);
256 // Promote i1/i8 SINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have
258 setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote);
259 setOperationAction(ISD::SINT_TO_FP , MVT::i8 , Promote);
261 if (!TM.Options.UseSoftFloat) {
262 // SSE has no i16 to fp conversion, only i32
263 if (X86ScalarSSEf32) {
264 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
265 // f32 and f64 cases are Legal, f80 case is not
266 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
268 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Custom);
269 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
272 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
273 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Promote);
276 // In 32-bit mode these are custom lowered. In 64-bit mode F32 and F64
277 // are Legal, f80 is custom lowered.
278 setOperationAction(ISD::FP_TO_SINT , MVT::i64 , Custom);
279 setOperationAction(ISD::SINT_TO_FP , MVT::i64 , Custom);
281 // Promote i1/i8 FP_TO_SINT to larger FP_TO_SINTS's, as X86 doesn't have
283 setOperationAction(ISD::FP_TO_SINT , MVT::i1 , Promote);
284 setOperationAction(ISD::FP_TO_SINT , MVT::i8 , Promote);
286 if (X86ScalarSSEf32) {
287 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Promote);
288 // f32 and f64 cases are Legal, f80 case is not
289 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
291 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Custom);
292 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
295 // Handle FP_TO_UINT by promoting the destination to a larger signed
297 setOperationAction(ISD::FP_TO_UINT , MVT::i1 , Promote);
298 setOperationAction(ISD::FP_TO_UINT , MVT::i8 , Promote);
299 setOperationAction(ISD::FP_TO_UINT , MVT::i16 , Promote);
301 if (Subtarget->is64Bit()) {
302 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Expand);
303 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote);
304 } else if (!TM.Options.UseSoftFloat) {
305 // Since AVX is a superset of SSE3, only check for SSE here.
306 if (Subtarget->hasSSE1() && !Subtarget->hasSSE3())
307 // Expand FP_TO_UINT into a select.
308 // FIXME: We would like to use a Custom expander here eventually to do
309 // the optimal thing for SSE vs. the default expansion in the legalizer.
310 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Expand);
312 // With SSE3 we can use fisttpll to convert to a signed i64; without
313 // SSE, we're stuck with a fistpll.
314 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Custom);
317 if (isTargetFTOL()) {
318 // Use the _ftol2 runtime function, which has a pseudo-instruction
319 // to handle its weird calling convention.
320 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Custom);
323 // TODO: when we have SSE, these could be more efficient, by using movd/movq.
324 if (!X86ScalarSSEf64) {
325 setOperationAction(ISD::BITCAST , MVT::f32 , Expand);
326 setOperationAction(ISD::BITCAST , MVT::i32 , Expand);
327 if (Subtarget->is64Bit()) {
328 setOperationAction(ISD::BITCAST , MVT::f64 , Expand);
329 // Without SSE, i64->f64 goes through memory.
330 setOperationAction(ISD::BITCAST , MVT::i64 , Expand);
334 // Scalar integer divide and remainder are lowered to use operations that
335 // produce two results, to match the available instructions. This exposes
336 // the two-result form to trivial CSE, which is able to combine x/y and x%y
337 // into a single instruction.
339 // Scalar integer multiply-high is also lowered to use two-result
340 // operations, to match the available instructions. However, plain multiply
341 // (low) operations are left as Legal, as there are single-result
342 // instructions for this in x86. Using the two-result multiply instructions
343 // when both high and low results are needed must be arranged by dagcombine.
344 for (unsigned i = 0; i != array_lengthof(IntVTs); ++i) {
346 setOperationAction(ISD::MULHS, VT, Expand);
347 setOperationAction(ISD::MULHU, VT, Expand);
348 setOperationAction(ISD::SDIV, VT, Expand);
349 setOperationAction(ISD::UDIV, VT, Expand);
350 setOperationAction(ISD::SREM, VT, Expand);
351 setOperationAction(ISD::UREM, VT, Expand);
353 // Add/Sub overflow ops with MVT::Glues are lowered to EFLAGS dependences.
354 setOperationAction(ISD::ADDC, VT, Custom);
355 setOperationAction(ISD::ADDE, VT, Custom);
356 setOperationAction(ISD::SUBC, VT, Custom);
357 setOperationAction(ISD::SUBE, VT, Custom);
360 setOperationAction(ISD::BR_JT , MVT::Other, Expand);
361 setOperationAction(ISD::BRCOND , MVT::Other, Custom);
362 setOperationAction(ISD::BR_CC , MVT::Other, Expand);
363 setOperationAction(ISD::SELECT_CC , MVT::Other, Expand);
364 if (Subtarget->is64Bit())
365 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal);
366 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Legal);
367 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Legal);
368 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
369 setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand);
370 setOperationAction(ISD::FREM , MVT::f32 , Expand);
371 setOperationAction(ISD::FREM , MVT::f64 , Expand);
372 setOperationAction(ISD::FREM , MVT::f80 , Expand);
373 setOperationAction(ISD::FLT_ROUNDS_ , MVT::i32 , Custom);
375 // Promote the i8 variants and force them on up to i32 which has a shorter
377 setOperationAction(ISD::CTTZ , MVT::i8 , Promote);
378 AddPromotedToType (ISD::CTTZ , MVT::i8 , MVT::i32);
379 setOperationAction(ISD::CTTZ_ZERO_UNDEF , MVT::i8 , Promote);
380 AddPromotedToType (ISD::CTTZ_ZERO_UNDEF , MVT::i8 , MVT::i32);
381 if (Subtarget->hasBMI()) {
382 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i16 , Expand);
383 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32 , Expand);
384 if (Subtarget->is64Bit())
385 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand);
387 setOperationAction(ISD::CTTZ , MVT::i16 , Custom);
388 setOperationAction(ISD::CTTZ , MVT::i32 , Custom);
389 if (Subtarget->is64Bit())
390 setOperationAction(ISD::CTTZ , MVT::i64 , Custom);
393 if (Subtarget->hasLZCNT()) {
394 // When promoting the i8 variants, force them to i32 for a shorter
396 setOperationAction(ISD::CTLZ , MVT::i8 , Promote);
397 AddPromotedToType (ISD::CTLZ , MVT::i8 , MVT::i32);
398 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Promote);
399 AddPromotedToType (ISD::CTLZ_ZERO_UNDEF, MVT::i8 , MVT::i32);
400 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Expand);
401 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Expand);
402 if (Subtarget->is64Bit())
403 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Expand);
405 setOperationAction(ISD::CTLZ , MVT::i8 , Custom);
406 setOperationAction(ISD::CTLZ , MVT::i16 , Custom);
407 setOperationAction(ISD::CTLZ , MVT::i32 , Custom);
408 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Custom);
409 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Custom);
410 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Custom);
411 if (Subtarget->is64Bit()) {
412 setOperationAction(ISD::CTLZ , MVT::i64 , Custom);
413 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Custom);
417 if (Subtarget->hasPOPCNT()) {
418 setOperationAction(ISD::CTPOP , MVT::i8 , Promote);
420 setOperationAction(ISD::CTPOP , MVT::i8 , Expand);
421 setOperationAction(ISD::CTPOP , MVT::i16 , Expand);
422 setOperationAction(ISD::CTPOP , MVT::i32 , Expand);
423 if (Subtarget->is64Bit())
424 setOperationAction(ISD::CTPOP , MVT::i64 , Expand);
427 setOperationAction(ISD::READCYCLECOUNTER , MVT::i64 , Custom);
428 setOperationAction(ISD::BSWAP , MVT::i16 , Expand);
430 // These should be promoted to a larger select which is supported.
431 setOperationAction(ISD::SELECT , MVT::i1 , Promote);
432 // X86 wants to expand cmov itself.
433 setOperationAction(ISD::SELECT , MVT::i8 , Custom);
434 setOperationAction(ISD::SELECT , MVT::i16 , Custom);
435 setOperationAction(ISD::SELECT , MVT::i32 , Custom);
436 setOperationAction(ISD::SELECT , MVT::f32 , Custom);
437 setOperationAction(ISD::SELECT , MVT::f64 , Custom);
438 setOperationAction(ISD::SELECT , MVT::f80 , Custom);
439 setOperationAction(ISD::SETCC , MVT::i8 , Custom);
440 setOperationAction(ISD::SETCC , MVT::i16 , Custom);
441 setOperationAction(ISD::SETCC , MVT::i32 , Custom);
442 setOperationAction(ISD::SETCC , MVT::f32 , Custom);
443 setOperationAction(ISD::SETCC , MVT::f64 , Custom);
444 setOperationAction(ISD::SETCC , MVT::f80 , Custom);
445 if (Subtarget->is64Bit()) {
446 setOperationAction(ISD::SELECT , MVT::i64 , Custom);
447 setOperationAction(ISD::SETCC , MVT::i64 , Custom);
449 setOperationAction(ISD::EH_RETURN , MVT::Other, Custom);
452 setOperationAction(ISD::ConstantPool , MVT::i32 , Custom);
453 setOperationAction(ISD::JumpTable , MVT::i32 , Custom);
454 setOperationAction(ISD::GlobalAddress , MVT::i32 , Custom);
455 setOperationAction(ISD::GlobalTLSAddress, MVT::i32 , Custom);
456 if (Subtarget->is64Bit())
457 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
458 setOperationAction(ISD::ExternalSymbol , MVT::i32 , Custom);
459 setOperationAction(ISD::BlockAddress , MVT::i32 , Custom);
460 if (Subtarget->is64Bit()) {
461 setOperationAction(ISD::ConstantPool , MVT::i64 , Custom);
462 setOperationAction(ISD::JumpTable , MVT::i64 , Custom);
463 setOperationAction(ISD::GlobalAddress , MVT::i64 , Custom);
464 setOperationAction(ISD::ExternalSymbol, MVT::i64 , Custom);
465 setOperationAction(ISD::BlockAddress , MVT::i64 , Custom);
467 // 64-bit addm sub, shl, sra, srl (iff 32-bit x86)
468 setOperationAction(ISD::SHL_PARTS , MVT::i32 , Custom);
469 setOperationAction(ISD::SRA_PARTS , MVT::i32 , Custom);
470 setOperationAction(ISD::SRL_PARTS , MVT::i32 , Custom);
471 if (Subtarget->is64Bit()) {
472 setOperationAction(ISD::SHL_PARTS , MVT::i64 , Custom);
473 setOperationAction(ISD::SRA_PARTS , MVT::i64 , Custom);
474 setOperationAction(ISD::SRL_PARTS , MVT::i64 , Custom);
477 if (Subtarget->hasSSE1())
478 setOperationAction(ISD::PREFETCH , MVT::Other, Legal);
480 setOperationAction(ISD::MEMBARRIER , MVT::Other, Custom);
481 setOperationAction(ISD::ATOMIC_FENCE , MVT::Other, Custom);
483 // On X86 and X86-64, atomic operations are lowered to locked instructions.
484 // Locked instructions, in turn, have implicit fence semantics (all memory
485 // operations are flushed before issuing the locked instruction, and they
486 // are not buffered), so we can fold away the common pattern of
487 // fence-atomic-fence.
488 setShouldFoldAtomicFences(true);
490 // Expand certain atomics
491 for (unsigned i = 0; i != array_lengthof(IntVTs); ++i) {
493 setOperationAction(ISD::ATOMIC_CMP_SWAP, VT, Custom);
494 setOperationAction(ISD::ATOMIC_LOAD_SUB, VT, Custom);
495 setOperationAction(ISD::ATOMIC_STORE, VT, Custom);
498 if (!Subtarget->is64Bit()) {
499 setOperationAction(ISD::ATOMIC_LOAD, MVT::i64, Custom);
500 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i64, Custom);
501 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i64, Custom);
502 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i64, Custom);
503 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i64, Custom);
504 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i64, Custom);
505 setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i64, Custom);
506 setOperationAction(ISD::ATOMIC_SWAP, MVT::i64, Custom);
509 if (Subtarget->hasCmpxchg16b()) {
510 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i128, Custom);
513 // FIXME - use subtarget debug flags
514 if (!Subtarget->isTargetDarwin() &&
515 !Subtarget->isTargetELF() &&
516 !Subtarget->isTargetCygMing()) {
517 setOperationAction(ISD::EH_LABEL, MVT::Other, Expand);
520 setOperationAction(ISD::EXCEPTIONADDR, MVT::i64, Expand);
521 setOperationAction(ISD::EHSELECTION, MVT::i64, Expand);
522 setOperationAction(ISD::EXCEPTIONADDR, MVT::i32, Expand);
523 setOperationAction(ISD::EHSELECTION, MVT::i32, Expand);
524 if (Subtarget->is64Bit()) {
525 setExceptionPointerRegister(X86::RAX);
526 setExceptionSelectorRegister(X86::RDX);
528 setExceptionPointerRegister(X86::EAX);
529 setExceptionSelectorRegister(X86::EDX);
531 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i32, Custom);
532 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i64, Custom);
534 setOperationAction(ISD::INIT_TRAMPOLINE, MVT::Other, Custom);
535 setOperationAction(ISD::ADJUST_TRAMPOLINE, MVT::Other, Custom);
537 setOperationAction(ISD::TRAP, MVT::Other, Legal);
539 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
540 setOperationAction(ISD::VASTART , MVT::Other, Custom);
541 setOperationAction(ISD::VAEND , MVT::Other, Expand);
542 if (Subtarget->is64Bit()) {
543 setOperationAction(ISD::VAARG , MVT::Other, Custom);
544 setOperationAction(ISD::VACOPY , MVT::Other, Custom);
546 setOperationAction(ISD::VAARG , MVT::Other, Expand);
547 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
550 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
551 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
553 if (Subtarget->isTargetCOFF() && !Subtarget->isTargetEnvMacho())
554 setOperationAction(ISD::DYNAMIC_STACKALLOC, Subtarget->is64Bit() ?
555 MVT::i64 : MVT::i32, Custom);
556 else if (TM.Options.EnableSegmentedStacks)
557 setOperationAction(ISD::DYNAMIC_STACKALLOC, Subtarget->is64Bit() ?
558 MVT::i64 : MVT::i32, Custom);
560 setOperationAction(ISD::DYNAMIC_STACKALLOC, Subtarget->is64Bit() ?
561 MVT::i64 : MVT::i32, Expand);
563 if (!TM.Options.UseSoftFloat && X86ScalarSSEf64) {
564 // f32 and f64 use SSE.
565 // Set up the FP register classes.
566 addRegisterClass(MVT::f32, &X86::FR32RegClass);
567 addRegisterClass(MVT::f64, &X86::FR64RegClass);
569 // Use ANDPD to simulate FABS.
570 setOperationAction(ISD::FABS , MVT::f64, Custom);
571 setOperationAction(ISD::FABS , MVT::f32, Custom);
573 // Use XORP to simulate FNEG.
574 setOperationAction(ISD::FNEG , MVT::f64, Custom);
575 setOperationAction(ISD::FNEG , MVT::f32, Custom);
577 // Use ANDPD and ORPD to simulate FCOPYSIGN.
578 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
579 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
581 // Lower this to FGETSIGNx86 plus an AND.
582 setOperationAction(ISD::FGETSIGN, MVT::i64, Custom);
583 setOperationAction(ISD::FGETSIGN, MVT::i32, Custom);
585 // We don't support sin/cos/fmod
586 setOperationAction(ISD::FSIN , MVT::f64, Expand);
587 setOperationAction(ISD::FCOS , MVT::f64, Expand);
588 setOperationAction(ISD::FSIN , MVT::f32, Expand);
589 setOperationAction(ISD::FCOS , MVT::f32, Expand);
591 // Expand FP immediates into loads from the stack, except for the special
593 addLegalFPImmediate(APFloat(+0.0)); // xorpd
594 addLegalFPImmediate(APFloat(+0.0f)); // xorps
595 } else if (!TM.Options.UseSoftFloat && X86ScalarSSEf32) {
596 // Use SSE for f32, x87 for f64.
597 // Set up the FP register classes.
598 addRegisterClass(MVT::f32, &X86::FR32RegClass);
599 addRegisterClass(MVT::f64, &X86::RFP64RegClass);
601 // Use ANDPS to simulate FABS.
602 setOperationAction(ISD::FABS , MVT::f32, Custom);
604 // Use XORP to simulate FNEG.
605 setOperationAction(ISD::FNEG , MVT::f32, Custom);
607 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
609 // Use ANDPS and ORPS to simulate FCOPYSIGN.
610 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
611 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
613 // We don't support sin/cos/fmod
614 setOperationAction(ISD::FSIN , MVT::f32, Expand);
615 setOperationAction(ISD::FCOS , MVT::f32, Expand);
617 // Special cases we handle for FP constants.
618 addLegalFPImmediate(APFloat(+0.0f)); // xorps
619 addLegalFPImmediate(APFloat(+0.0)); // FLD0
620 addLegalFPImmediate(APFloat(+1.0)); // FLD1
621 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
622 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
624 if (!TM.Options.UnsafeFPMath) {
625 setOperationAction(ISD::FSIN , MVT::f64 , Expand);
626 setOperationAction(ISD::FCOS , MVT::f64 , Expand);
628 } else if (!TM.Options.UseSoftFloat) {
629 // f32 and f64 in x87.
630 // Set up the FP register classes.
631 addRegisterClass(MVT::f64, &X86::RFP64RegClass);
632 addRegisterClass(MVT::f32, &X86::RFP32RegClass);
634 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
635 setOperationAction(ISD::UNDEF, MVT::f32, Expand);
636 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
637 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
639 if (!TM.Options.UnsafeFPMath) {
640 setOperationAction(ISD::FSIN , MVT::f64 , Expand);
641 setOperationAction(ISD::FCOS , MVT::f64 , Expand);
643 addLegalFPImmediate(APFloat(+0.0)); // FLD0
644 addLegalFPImmediate(APFloat(+1.0)); // FLD1
645 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
646 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
647 addLegalFPImmediate(APFloat(+0.0f)); // FLD0
648 addLegalFPImmediate(APFloat(+1.0f)); // FLD1
649 addLegalFPImmediate(APFloat(-0.0f)); // FLD0/FCHS
650 addLegalFPImmediate(APFloat(-1.0f)); // FLD1/FCHS
653 // We don't support FMA.
654 setOperationAction(ISD::FMA, MVT::f64, Expand);
655 setOperationAction(ISD::FMA, MVT::f32, Expand);
657 // Long double always uses X87.
658 if (!TM.Options.UseSoftFloat) {
659 addRegisterClass(MVT::f80, &X86::RFP80RegClass);
660 setOperationAction(ISD::UNDEF, MVT::f80, Expand);
661 setOperationAction(ISD::FCOPYSIGN, MVT::f80, Expand);
663 APFloat TmpFlt = APFloat::getZero(APFloat::x87DoubleExtended);
664 addLegalFPImmediate(TmpFlt); // FLD0
666 addLegalFPImmediate(TmpFlt); // FLD0/FCHS
669 APFloat TmpFlt2(+1.0);
670 TmpFlt2.convert(APFloat::x87DoubleExtended, APFloat::rmNearestTiesToEven,
672 addLegalFPImmediate(TmpFlt2); // FLD1
673 TmpFlt2.changeSign();
674 addLegalFPImmediate(TmpFlt2); // FLD1/FCHS
677 if (!TM.Options.UnsafeFPMath) {
678 setOperationAction(ISD::FSIN , MVT::f80 , Expand);
679 setOperationAction(ISD::FCOS , MVT::f80 , Expand);
682 setOperationAction(ISD::FFLOOR, MVT::f80, Expand);
683 setOperationAction(ISD::FCEIL, MVT::f80, Expand);
684 setOperationAction(ISD::FTRUNC, MVT::f80, Expand);
685 setOperationAction(ISD::FRINT, MVT::f80, Expand);
686 setOperationAction(ISD::FNEARBYINT, MVT::f80, Expand);
687 setOperationAction(ISD::FMA, MVT::f80, Expand);
690 // Always use a library call for pow.
691 setOperationAction(ISD::FPOW , MVT::f32 , Expand);
692 setOperationAction(ISD::FPOW , MVT::f64 , Expand);
693 setOperationAction(ISD::FPOW , MVT::f80 , Expand);
695 setOperationAction(ISD::FLOG, MVT::f80, Expand);
696 setOperationAction(ISD::FLOG2, MVT::f80, Expand);
697 setOperationAction(ISD::FLOG10, MVT::f80, Expand);
698 setOperationAction(ISD::FEXP, MVT::f80, Expand);
699 setOperationAction(ISD::FEXP2, MVT::f80, Expand);
701 // First set operation action for all vector types to either promote
702 // (for widening) or expand (for scalarization). Then we will selectively
703 // turn on ones that can be effectively codegen'd.
704 for (unsigned VT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
705 VT <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++VT) {
706 setOperationAction(ISD::ADD , (MVT::SimpleValueType)VT, Expand);
707 setOperationAction(ISD::SUB , (MVT::SimpleValueType)VT, Expand);
708 setOperationAction(ISD::FADD, (MVT::SimpleValueType)VT, Expand);
709 setOperationAction(ISD::FNEG, (MVT::SimpleValueType)VT, Expand);
710 setOperationAction(ISD::FSUB, (MVT::SimpleValueType)VT, Expand);
711 setOperationAction(ISD::MUL , (MVT::SimpleValueType)VT, Expand);
712 setOperationAction(ISD::FMUL, (MVT::SimpleValueType)VT, Expand);
713 setOperationAction(ISD::SDIV, (MVT::SimpleValueType)VT, Expand);
714 setOperationAction(ISD::UDIV, (MVT::SimpleValueType)VT, Expand);
715 setOperationAction(ISD::FDIV, (MVT::SimpleValueType)VT, Expand);
716 setOperationAction(ISD::SREM, (MVT::SimpleValueType)VT, Expand);
717 setOperationAction(ISD::UREM, (MVT::SimpleValueType)VT, Expand);
718 setOperationAction(ISD::LOAD, (MVT::SimpleValueType)VT, Expand);
719 setOperationAction(ISD::VECTOR_SHUFFLE, (MVT::SimpleValueType)VT, Expand);
720 setOperationAction(ISD::EXTRACT_VECTOR_ELT,(MVT::SimpleValueType)VT,Expand);
721 setOperationAction(ISD::INSERT_VECTOR_ELT,(MVT::SimpleValueType)VT, Expand);
722 setOperationAction(ISD::EXTRACT_SUBVECTOR,(MVT::SimpleValueType)VT,Expand);
723 setOperationAction(ISD::INSERT_SUBVECTOR,(MVT::SimpleValueType)VT,Expand);
724 setOperationAction(ISD::FABS, (MVT::SimpleValueType)VT, Expand);
725 setOperationAction(ISD::FSIN, (MVT::SimpleValueType)VT, Expand);
726 setOperationAction(ISD::FCOS, (MVT::SimpleValueType)VT, Expand);
727 setOperationAction(ISD::FREM, (MVT::SimpleValueType)VT, Expand);
728 setOperationAction(ISD::FPOWI, (MVT::SimpleValueType)VT, Expand);
729 setOperationAction(ISD::FSQRT, (MVT::SimpleValueType)VT, Expand);
730 setOperationAction(ISD::FCOPYSIGN, (MVT::SimpleValueType)VT, Expand);
731 setOperationAction(ISD::SMUL_LOHI, (MVT::SimpleValueType)VT, Expand);
732 setOperationAction(ISD::UMUL_LOHI, (MVT::SimpleValueType)VT, Expand);
733 setOperationAction(ISD::SDIVREM, (MVT::SimpleValueType)VT, Expand);
734 setOperationAction(ISD::UDIVREM, (MVT::SimpleValueType)VT, Expand);
735 setOperationAction(ISD::FPOW, (MVT::SimpleValueType)VT, Expand);
736 setOperationAction(ISD::CTPOP, (MVT::SimpleValueType)VT, Expand);
737 setOperationAction(ISD::CTTZ, (MVT::SimpleValueType)VT, Expand);
738 setOperationAction(ISD::CTTZ_ZERO_UNDEF, (MVT::SimpleValueType)VT, Expand);
739 setOperationAction(ISD::CTLZ, (MVT::SimpleValueType)VT, Expand);
740 setOperationAction(ISD::CTLZ_ZERO_UNDEF, (MVT::SimpleValueType)VT, Expand);
741 setOperationAction(ISD::SHL, (MVT::SimpleValueType)VT, Expand);
742 setOperationAction(ISD::SRA, (MVT::SimpleValueType)VT, Expand);
743 setOperationAction(ISD::SRL, (MVT::SimpleValueType)VT, Expand);
744 setOperationAction(ISD::ROTL, (MVT::SimpleValueType)VT, Expand);
745 setOperationAction(ISD::ROTR, (MVT::SimpleValueType)VT, Expand);
746 setOperationAction(ISD::BSWAP, (MVT::SimpleValueType)VT, Expand);
747 setOperationAction(ISD::SETCC, (MVT::SimpleValueType)VT, Expand);
748 setOperationAction(ISD::FLOG, (MVT::SimpleValueType)VT, Expand);
749 setOperationAction(ISD::FLOG2, (MVT::SimpleValueType)VT, Expand);
750 setOperationAction(ISD::FLOG10, (MVT::SimpleValueType)VT, Expand);
751 setOperationAction(ISD::FEXP, (MVT::SimpleValueType)VT, Expand);
752 setOperationAction(ISD::FEXP2, (MVT::SimpleValueType)VT, Expand);
753 setOperationAction(ISD::FP_TO_UINT, (MVT::SimpleValueType)VT, Expand);
754 setOperationAction(ISD::FP_TO_SINT, (MVT::SimpleValueType)VT, Expand);
755 setOperationAction(ISD::UINT_TO_FP, (MVT::SimpleValueType)VT, Expand);
756 setOperationAction(ISD::SINT_TO_FP, (MVT::SimpleValueType)VT, Expand);
757 setOperationAction(ISD::SIGN_EXTEND_INREG, (MVT::SimpleValueType)VT,Expand);
758 setOperationAction(ISD::TRUNCATE, (MVT::SimpleValueType)VT, Expand);
759 setOperationAction(ISD::SIGN_EXTEND, (MVT::SimpleValueType)VT, Expand);
760 setOperationAction(ISD::ZERO_EXTEND, (MVT::SimpleValueType)VT, Expand);
761 setOperationAction(ISD::ANY_EXTEND, (MVT::SimpleValueType)VT, Expand);
762 setOperationAction(ISD::VSELECT, (MVT::SimpleValueType)VT, Expand);
763 for (unsigned InnerVT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
764 InnerVT <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++InnerVT)
765 setTruncStoreAction((MVT::SimpleValueType)VT,
766 (MVT::SimpleValueType)InnerVT, Expand);
767 setLoadExtAction(ISD::SEXTLOAD, (MVT::SimpleValueType)VT, Expand);
768 setLoadExtAction(ISD::ZEXTLOAD, (MVT::SimpleValueType)VT, Expand);
769 setLoadExtAction(ISD::EXTLOAD, (MVT::SimpleValueType)VT, Expand);
772 // FIXME: In order to prevent SSE instructions being expanded to MMX ones
773 // with -msoft-float, disable use of MMX as well.
774 if (!TM.Options.UseSoftFloat && Subtarget->hasMMX()) {
775 addRegisterClass(MVT::x86mmx, &X86::VR64RegClass);
776 // No operations on x86mmx supported, everything uses intrinsics.
779 // MMX-sized vectors (other than x86mmx) are expected to be expanded
780 // into smaller operations.
781 setOperationAction(ISD::MULHS, MVT::v8i8, Expand);
782 setOperationAction(ISD::MULHS, MVT::v4i16, Expand);
783 setOperationAction(ISD::MULHS, MVT::v2i32, Expand);
784 setOperationAction(ISD::MULHS, MVT::v1i64, Expand);
785 setOperationAction(ISD::AND, MVT::v8i8, Expand);
786 setOperationAction(ISD::AND, MVT::v4i16, Expand);
787 setOperationAction(ISD::AND, MVT::v2i32, Expand);
788 setOperationAction(ISD::AND, MVT::v1i64, Expand);
789 setOperationAction(ISD::OR, MVT::v8i8, Expand);
790 setOperationAction(ISD::OR, MVT::v4i16, Expand);
791 setOperationAction(ISD::OR, MVT::v2i32, Expand);
792 setOperationAction(ISD::OR, MVT::v1i64, Expand);
793 setOperationAction(ISD::XOR, MVT::v8i8, Expand);
794 setOperationAction(ISD::XOR, MVT::v4i16, Expand);
795 setOperationAction(ISD::XOR, MVT::v2i32, Expand);
796 setOperationAction(ISD::XOR, MVT::v1i64, Expand);
797 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i8, Expand);
798 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i16, Expand);
799 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2i32, Expand);
800 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v1i64, Expand);
801 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v1i64, Expand);
802 setOperationAction(ISD::SELECT, MVT::v8i8, Expand);
803 setOperationAction(ISD::SELECT, MVT::v4i16, Expand);
804 setOperationAction(ISD::SELECT, MVT::v2i32, Expand);
805 setOperationAction(ISD::SELECT, MVT::v1i64, Expand);
806 setOperationAction(ISD::BITCAST, MVT::v8i8, Expand);
807 setOperationAction(ISD::BITCAST, MVT::v4i16, Expand);
808 setOperationAction(ISD::BITCAST, MVT::v2i32, Expand);
809 setOperationAction(ISD::BITCAST, MVT::v1i64, Expand);
811 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE1()) {
812 addRegisterClass(MVT::v4f32, &X86::VR128RegClass);
814 setOperationAction(ISD::FADD, MVT::v4f32, Legal);
815 setOperationAction(ISD::FSUB, MVT::v4f32, Legal);
816 setOperationAction(ISD::FMUL, MVT::v4f32, Legal);
817 setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
818 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal);
819 setOperationAction(ISD::FNEG, MVT::v4f32, Custom);
820 setOperationAction(ISD::LOAD, MVT::v4f32, Legal);
821 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
822 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f32, Custom);
823 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
824 setOperationAction(ISD::SELECT, MVT::v4f32, Custom);
825 setOperationAction(ISD::SETCC, MVT::v4f32, Custom);
828 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE2()) {
829 addRegisterClass(MVT::v2f64, &X86::VR128RegClass);
831 // FIXME: Unfortunately -soft-float and -no-implicit-float means XMM
832 // registers cannot be used even for integer operations.
833 addRegisterClass(MVT::v16i8, &X86::VR128RegClass);
834 addRegisterClass(MVT::v8i16, &X86::VR128RegClass);
835 addRegisterClass(MVT::v4i32, &X86::VR128RegClass);
836 addRegisterClass(MVT::v2i64, &X86::VR128RegClass);
838 setOperationAction(ISD::ADD, MVT::v16i8, Legal);
839 setOperationAction(ISD::ADD, MVT::v8i16, Legal);
840 setOperationAction(ISD::ADD, MVT::v4i32, Legal);
841 setOperationAction(ISD::ADD, MVT::v2i64, Legal);
842 setOperationAction(ISD::MUL, MVT::v2i64, Custom);
843 setOperationAction(ISD::SUB, MVT::v16i8, Legal);
844 setOperationAction(ISD::SUB, MVT::v8i16, Legal);
845 setOperationAction(ISD::SUB, MVT::v4i32, Legal);
846 setOperationAction(ISD::SUB, MVT::v2i64, Legal);
847 setOperationAction(ISD::MUL, MVT::v8i16, Legal);
848 setOperationAction(ISD::FADD, MVT::v2f64, Legal);
849 setOperationAction(ISD::FSUB, MVT::v2f64, Legal);
850 setOperationAction(ISD::FMUL, MVT::v2f64, Legal);
851 setOperationAction(ISD::FDIV, MVT::v2f64, Legal);
852 setOperationAction(ISD::FSQRT, MVT::v2f64, Legal);
853 setOperationAction(ISD::FNEG, MVT::v2f64, Custom);
855 setOperationAction(ISD::SETCC, MVT::v2i64, Custom);
856 setOperationAction(ISD::SETCC, MVT::v16i8, Custom);
857 setOperationAction(ISD::SETCC, MVT::v8i16, Custom);
858 setOperationAction(ISD::SETCC, MVT::v4i32, Custom);
860 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Custom);
861 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Custom);
862 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
863 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
864 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
866 setOperationAction(ISD::CONCAT_VECTORS, MVT::v2f64, Custom);
867 setOperationAction(ISD::CONCAT_VECTORS, MVT::v2i64, Custom);
868 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i8, Custom);
869 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i16, Custom);
870 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4i32, Custom);
872 // Custom lower build_vector, vector_shuffle, and extract_vector_elt.
873 for (unsigned i = (unsigned)MVT::v16i8; i != (unsigned)MVT::v2i64; ++i) {
874 EVT VT = (MVT::SimpleValueType)i;
875 // Do not attempt to custom lower non-power-of-2 vectors
876 if (!isPowerOf2_32(VT.getVectorNumElements()))
878 // Do not attempt to custom lower non-128-bit vectors
879 if (!VT.is128BitVector())
881 setOperationAction(ISD::BUILD_VECTOR,
882 VT.getSimpleVT().SimpleTy, Custom);
883 setOperationAction(ISD::VECTOR_SHUFFLE,
884 VT.getSimpleVT().SimpleTy, Custom);
885 setOperationAction(ISD::EXTRACT_VECTOR_ELT,
886 VT.getSimpleVT().SimpleTy, Custom);
889 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f64, Custom);
890 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i64, Custom);
891 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Custom);
892 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Custom);
893 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f64, Custom);
894 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Custom);
896 if (Subtarget->is64Bit()) {
897 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
898 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
901 // Promote v16i8, v8i16, v4i32 load, select, and, or, xor to v2i64.
902 for (unsigned i = (unsigned)MVT::v16i8; i != (unsigned)MVT::v2i64; i++) {
903 MVT::SimpleValueType SVT = (MVT::SimpleValueType)i;
906 // Do not attempt to promote non-128-bit vectors
907 if (!VT.is128BitVector())
910 setOperationAction(ISD::AND, SVT, Promote);
911 AddPromotedToType (ISD::AND, SVT, MVT::v2i64);
912 setOperationAction(ISD::OR, SVT, Promote);
913 AddPromotedToType (ISD::OR, SVT, MVT::v2i64);
914 setOperationAction(ISD::XOR, SVT, Promote);
915 AddPromotedToType (ISD::XOR, SVT, MVT::v2i64);
916 setOperationAction(ISD::LOAD, SVT, Promote);
917 AddPromotedToType (ISD::LOAD, SVT, MVT::v2i64);
918 setOperationAction(ISD::SELECT, SVT, Promote);
919 AddPromotedToType (ISD::SELECT, SVT, MVT::v2i64);
922 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
924 // Custom lower v2i64 and v2f64 selects.
925 setOperationAction(ISD::LOAD, MVT::v2f64, Legal);
926 setOperationAction(ISD::LOAD, MVT::v2i64, Legal);
927 setOperationAction(ISD::SELECT, MVT::v2f64, Custom);
928 setOperationAction(ISD::SELECT, MVT::v2i64, Custom);
930 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal);
931 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal);
934 if (Subtarget->hasSSE41()) {
935 setOperationAction(ISD::FFLOOR, MVT::f32, Legal);
936 setOperationAction(ISD::FCEIL, MVT::f32, Legal);
937 setOperationAction(ISD::FTRUNC, MVT::f32, Legal);
938 setOperationAction(ISD::FRINT, MVT::f32, Legal);
939 setOperationAction(ISD::FNEARBYINT, MVT::f32, Legal);
940 setOperationAction(ISD::FFLOOR, MVT::f64, Legal);
941 setOperationAction(ISD::FCEIL, MVT::f64, Legal);
942 setOperationAction(ISD::FTRUNC, MVT::f64, Legal);
943 setOperationAction(ISD::FRINT, MVT::f64, Legal);
944 setOperationAction(ISD::FNEARBYINT, MVT::f64, Legal);
946 // FIXME: Do we need to handle scalar-to-vector here?
947 setOperationAction(ISD::MUL, MVT::v4i32, Legal);
949 setOperationAction(ISD::VSELECT, MVT::v2f64, Legal);
950 setOperationAction(ISD::VSELECT, MVT::v2i64, Legal);
951 setOperationAction(ISD::VSELECT, MVT::v16i8, Legal);
952 setOperationAction(ISD::VSELECT, MVT::v4i32, Legal);
953 setOperationAction(ISD::VSELECT, MVT::v4f32, Legal);
955 // i8 and i16 vectors are custom , because the source register and source
956 // source memory operand types are not the same width. f32 vectors are
957 // custom since the immediate controlling the insert encodes additional
959 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i8, Custom);
960 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
961 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
962 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
964 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i8, Custom);
965 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i16, Custom);
966 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i32, Custom);
967 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
969 // FIXME: these should be Legal but thats only for the case where
970 // the index is constant. For now custom expand to deal with that.
971 if (Subtarget->is64Bit()) {
972 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
973 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
977 if (Subtarget->hasSSE2()) {
978 setOperationAction(ISD::SRL, MVT::v8i16, Custom);
979 setOperationAction(ISD::SRL, MVT::v16i8, Custom);
981 setOperationAction(ISD::SHL, MVT::v8i16, Custom);
982 setOperationAction(ISD::SHL, MVT::v16i8, Custom);
984 setOperationAction(ISD::SRA, MVT::v8i16, Custom);
985 setOperationAction(ISD::SRA, MVT::v16i8, Custom);
987 if (Subtarget->hasAVX2()) {
988 setOperationAction(ISD::SRL, MVT::v2i64, Legal);
989 setOperationAction(ISD::SRL, MVT::v4i32, Legal);
991 setOperationAction(ISD::SHL, MVT::v2i64, Legal);
992 setOperationAction(ISD::SHL, MVT::v4i32, Legal);
994 setOperationAction(ISD::SRA, MVT::v4i32, Legal);
996 setOperationAction(ISD::SRL, MVT::v2i64, Custom);
997 setOperationAction(ISD::SRL, MVT::v4i32, Custom);
999 setOperationAction(ISD::SHL, MVT::v2i64, Custom);
1000 setOperationAction(ISD::SHL, MVT::v4i32, Custom);
1002 setOperationAction(ISD::SRA, MVT::v4i32, Custom);
1006 if (Subtarget->hasSSE42())
1007 setOperationAction(ISD::SETCC, MVT::v2i64, Custom);
1009 if (!TM.Options.UseSoftFloat && Subtarget->hasAVX()) {
1010 addRegisterClass(MVT::v32i8, &X86::VR256RegClass);
1011 addRegisterClass(MVT::v16i16, &X86::VR256RegClass);
1012 addRegisterClass(MVT::v8i32, &X86::VR256RegClass);
1013 addRegisterClass(MVT::v8f32, &X86::VR256RegClass);
1014 addRegisterClass(MVT::v4i64, &X86::VR256RegClass);
1015 addRegisterClass(MVT::v4f64, &X86::VR256RegClass);
1017 setOperationAction(ISD::LOAD, MVT::v8f32, Legal);
1018 setOperationAction(ISD::LOAD, MVT::v4f64, Legal);
1019 setOperationAction(ISD::LOAD, MVT::v4i64, Legal);
1021 setOperationAction(ISD::FADD, MVT::v8f32, Legal);
1022 setOperationAction(ISD::FSUB, MVT::v8f32, Legal);
1023 setOperationAction(ISD::FMUL, MVT::v8f32, Legal);
1024 setOperationAction(ISD::FDIV, MVT::v8f32, Legal);
1025 setOperationAction(ISD::FSQRT, MVT::v8f32, Legal);
1026 setOperationAction(ISD::FNEG, MVT::v8f32, Custom);
1028 setOperationAction(ISD::FADD, MVT::v4f64, Legal);
1029 setOperationAction(ISD::FSUB, MVT::v4f64, Legal);
1030 setOperationAction(ISD::FMUL, MVT::v4f64, Legal);
1031 setOperationAction(ISD::FDIV, MVT::v4f64, Legal);
1032 setOperationAction(ISD::FSQRT, MVT::v4f64, Legal);
1033 setOperationAction(ISD::FNEG, MVT::v4f64, Custom);
1035 setOperationAction(ISD::FP_TO_SINT, MVT::v8i32, Legal);
1036 setOperationAction(ISD::SINT_TO_FP, MVT::v8i32, Legal);
1037 setOperationAction(ISD::FP_ROUND, MVT::v4f32, Legal);
1039 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4f64, Custom);
1040 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4i64, Custom);
1041 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8f32, Custom);
1042 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i32, Custom);
1043 setOperationAction(ISD::CONCAT_VECTORS, MVT::v32i8, Custom);
1044 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i16, Custom);
1046 setOperationAction(ISD::SRL, MVT::v16i16, Custom);
1047 setOperationAction(ISD::SRL, MVT::v32i8, Custom);
1049 setOperationAction(ISD::SHL, MVT::v16i16, Custom);
1050 setOperationAction(ISD::SHL, MVT::v32i8, Custom);
1052 setOperationAction(ISD::SRA, MVT::v16i16, Custom);
1053 setOperationAction(ISD::SRA, MVT::v32i8, Custom);
1055 setOperationAction(ISD::SETCC, MVT::v32i8, Custom);
1056 setOperationAction(ISD::SETCC, MVT::v16i16, Custom);
1057 setOperationAction(ISD::SETCC, MVT::v8i32, Custom);
1058 setOperationAction(ISD::SETCC, MVT::v4i64, Custom);
1060 setOperationAction(ISD::SELECT, MVT::v4f64, Custom);
1061 setOperationAction(ISD::SELECT, MVT::v4i64, Custom);
1062 setOperationAction(ISD::SELECT, MVT::v8f32, Custom);
1064 setOperationAction(ISD::VSELECT, MVT::v4f64, Legal);
1065 setOperationAction(ISD::VSELECT, MVT::v4i64, Legal);
1066 setOperationAction(ISD::VSELECT, MVT::v8i32, Legal);
1067 setOperationAction(ISD::VSELECT, MVT::v8f32, Legal);
1069 if (Subtarget->hasAVX2()) {
1070 setOperationAction(ISD::ADD, MVT::v4i64, Legal);
1071 setOperationAction(ISD::ADD, MVT::v8i32, Legal);
1072 setOperationAction(ISD::ADD, MVT::v16i16, Legal);
1073 setOperationAction(ISD::ADD, MVT::v32i8, Legal);
1075 setOperationAction(ISD::SUB, MVT::v4i64, Legal);
1076 setOperationAction(ISD::SUB, MVT::v8i32, Legal);
1077 setOperationAction(ISD::SUB, MVT::v16i16, Legal);
1078 setOperationAction(ISD::SUB, MVT::v32i8, Legal);
1080 setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1081 setOperationAction(ISD::MUL, MVT::v8i32, Legal);
1082 setOperationAction(ISD::MUL, MVT::v16i16, Legal);
1083 // Don't lower v32i8 because there is no 128-bit byte mul
1085 setOperationAction(ISD::VSELECT, MVT::v32i8, Legal);
1087 setOperationAction(ISD::SRL, MVT::v4i64, Legal);
1088 setOperationAction(ISD::SRL, MVT::v8i32, Legal);
1090 setOperationAction(ISD::SHL, MVT::v4i64, Legal);
1091 setOperationAction(ISD::SHL, MVT::v8i32, Legal);
1093 setOperationAction(ISD::SRA, MVT::v8i32, Legal);
1095 setOperationAction(ISD::ADD, MVT::v4i64, Custom);
1096 setOperationAction(ISD::ADD, MVT::v8i32, Custom);
1097 setOperationAction(ISD::ADD, MVT::v16i16, Custom);
1098 setOperationAction(ISD::ADD, MVT::v32i8, Custom);
1100 setOperationAction(ISD::SUB, MVT::v4i64, Custom);
1101 setOperationAction(ISD::SUB, MVT::v8i32, Custom);
1102 setOperationAction(ISD::SUB, MVT::v16i16, Custom);
1103 setOperationAction(ISD::SUB, MVT::v32i8, Custom);
1105 setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1106 setOperationAction(ISD::MUL, MVT::v8i32, Custom);
1107 setOperationAction(ISD::MUL, MVT::v16i16, Custom);
1108 // Don't lower v32i8 because there is no 128-bit byte mul
1110 setOperationAction(ISD::SRL, MVT::v4i64, Custom);
1111 setOperationAction(ISD::SRL, MVT::v8i32, Custom);
1113 setOperationAction(ISD::SHL, MVT::v4i64, Custom);
1114 setOperationAction(ISD::SHL, MVT::v8i32, Custom);
1116 setOperationAction(ISD::SRA, MVT::v8i32, Custom);
1119 // Custom lower several nodes for 256-bit types.
1120 for (unsigned i = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
1121 i <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++i) {
1122 MVT::SimpleValueType SVT = (MVT::SimpleValueType)i;
1125 // Extract subvector is special because the value type
1126 // (result) is 128-bit but the source is 256-bit wide.
1127 if (VT.is128BitVector())
1128 setOperationAction(ISD::EXTRACT_SUBVECTOR, SVT, Custom);
1130 // Do not attempt to custom lower other non-256-bit vectors
1131 if (!VT.is256BitVector())
1134 setOperationAction(ISD::BUILD_VECTOR, SVT, Custom);
1135 setOperationAction(ISD::VECTOR_SHUFFLE, SVT, Custom);
1136 setOperationAction(ISD::INSERT_VECTOR_ELT, SVT, Custom);
1137 setOperationAction(ISD::EXTRACT_VECTOR_ELT, SVT, Custom);
1138 setOperationAction(ISD::SCALAR_TO_VECTOR, SVT, Custom);
1139 setOperationAction(ISD::INSERT_SUBVECTOR, SVT, Custom);
1142 // Promote v32i8, v16i16, v8i32 select, and, or, xor to v4i64.
1143 for (unsigned i = (unsigned)MVT::v32i8; i != (unsigned)MVT::v4i64; ++i) {
1144 MVT::SimpleValueType SVT = (MVT::SimpleValueType)i;
1147 // Do not attempt to promote non-256-bit vectors
1148 if (!VT.is256BitVector())
1151 setOperationAction(ISD::AND, SVT, Promote);
1152 AddPromotedToType (ISD::AND, SVT, MVT::v4i64);
1153 setOperationAction(ISD::OR, SVT, Promote);
1154 AddPromotedToType (ISD::OR, SVT, MVT::v4i64);
1155 setOperationAction(ISD::XOR, SVT, Promote);
1156 AddPromotedToType (ISD::XOR, SVT, MVT::v4i64);
1157 setOperationAction(ISD::LOAD, SVT, Promote);
1158 AddPromotedToType (ISD::LOAD, SVT, MVT::v4i64);
1159 setOperationAction(ISD::SELECT, SVT, Promote);
1160 AddPromotedToType (ISD::SELECT, SVT, MVT::v4i64);
1164 // SIGN_EXTEND_INREGs are evaluated by the extend type. Handle the expansion
1165 // of this type with custom code.
1166 for (unsigned VT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
1167 VT != (unsigned)MVT::LAST_VECTOR_VALUETYPE; VT++) {
1168 setOperationAction(ISD::SIGN_EXTEND_INREG, (MVT::SimpleValueType)VT,
1172 // We want to custom lower some of our intrinsics.
1173 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
1176 // Only custom-lower 64-bit SADDO and friends on 64-bit because we don't
1177 // handle type legalization for these operations here.
1179 // FIXME: We really should do custom legalization for addition and
1180 // subtraction on x86-32 once PR3203 is fixed. We really can't do much better
1181 // than generic legalization for 64-bit multiplication-with-overflow, though.
1182 for (unsigned i = 0, e = 3+Subtarget->is64Bit(); i != e; ++i) {
1183 // Add/Sub/Mul with overflow operations are custom lowered.
1185 setOperationAction(ISD::SADDO, VT, Custom);
1186 setOperationAction(ISD::UADDO, VT, Custom);
1187 setOperationAction(ISD::SSUBO, VT, Custom);
1188 setOperationAction(ISD::USUBO, VT, Custom);
1189 setOperationAction(ISD::SMULO, VT, Custom);
1190 setOperationAction(ISD::UMULO, VT, Custom);
1193 // There are no 8-bit 3-address imul/mul instructions
1194 setOperationAction(ISD::SMULO, MVT::i8, Expand);
1195 setOperationAction(ISD::UMULO, MVT::i8, Expand);
1197 if (!Subtarget->is64Bit()) {
1198 // These libcalls are not available in 32-bit.
1199 setLibcallName(RTLIB::SHL_I128, 0);
1200 setLibcallName(RTLIB::SRL_I128, 0);
1201 setLibcallName(RTLIB::SRA_I128, 0);
1204 // We have target-specific dag combine patterns for the following nodes:
1205 setTargetDAGCombine(ISD::VECTOR_SHUFFLE);
1206 setTargetDAGCombine(ISD::EXTRACT_VECTOR_ELT);
1207 setTargetDAGCombine(ISD::VSELECT);
1208 setTargetDAGCombine(ISD::SELECT);
1209 setTargetDAGCombine(ISD::SHL);
1210 setTargetDAGCombine(ISD::SRA);
1211 setTargetDAGCombine(ISD::SRL);
1212 setTargetDAGCombine(ISD::OR);
1213 setTargetDAGCombine(ISD::AND);
1214 setTargetDAGCombine(ISD::ADD);
1215 setTargetDAGCombine(ISD::FADD);
1216 setTargetDAGCombine(ISD::FSUB);
1217 setTargetDAGCombine(ISD::SUB);
1218 setTargetDAGCombine(ISD::LOAD);
1219 setTargetDAGCombine(ISD::STORE);
1220 setTargetDAGCombine(ISD::ZERO_EXTEND);
1221 setTargetDAGCombine(ISD::ANY_EXTEND);
1222 setTargetDAGCombine(ISD::SIGN_EXTEND);
1223 setTargetDAGCombine(ISD::TRUNCATE);
1224 setTargetDAGCombine(ISD::UINT_TO_FP);
1225 setTargetDAGCombine(ISD::SINT_TO_FP);
1226 setTargetDAGCombine(ISD::FP_TO_SINT);
1227 if (Subtarget->is64Bit())
1228 setTargetDAGCombine(ISD::MUL);
1229 if (Subtarget->hasBMI())
1230 setTargetDAGCombine(ISD::XOR);
1232 computeRegisterProperties();
1234 // On Darwin, -Os means optimize for size without hurting performance,
1235 // do not reduce the limit.
1236 maxStoresPerMemset = 16; // For @llvm.memset -> sequence of stores
1237 maxStoresPerMemsetOptSize = Subtarget->isTargetDarwin() ? 16 : 8;
1238 maxStoresPerMemcpy = 8; // For @llvm.memcpy -> sequence of stores
1239 maxStoresPerMemcpyOptSize = Subtarget->isTargetDarwin() ? 8 : 4;
1240 maxStoresPerMemmove = 8; // For @llvm.memmove -> sequence of stores
1241 maxStoresPerMemmoveOptSize = Subtarget->isTargetDarwin() ? 8 : 4;
1242 setPrefLoopAlignment(4); // 2^4 bytes.
1243 benefitFromCodePlacementOpt = true;
1245 setPrefFunctionAlignment(4); // 2^4 bytes.
1249 EVT X86TargetLowering::getSetCCResultType(EVT VT) const {
1250 if (!VT.isVector()) return MVT::i8;
1251 return VT.changeVectorElementTypeToInteger();
1255 /// getMaxByValAlign - Helper for getByValTypeAlignment to determine
1256 /// the desired ByVal argument alignment.
1257 static void getMaxByValAlign(Type *Ty, unsigned &MaxAlign) {
1260 if (VectorType *VTy = dyn_cast<VectorType>(Ty)) {
1261 if (VTy->getBitWidth() == 128)
1263 } else if (ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
1264 unsigned EltAlign = 0;
1265 getMaxByValAlign(ATy->getElementType(), EltAlign);
1266 if (EltAlign > MaxAlign)
1267 MaxAlign = EltAlign;
1268 } else if (StructType *STy = dyn_cast<StructType>(Ty)) {
1269 for (unsigned i = 0, e = STy->getNumElements(); i != e; ++i) {
1270 unsigned EltAlign = 0;
1271 getMaxByValAlign(STy->getElementType(i), EltAlign);
1272 if (EltAlign > MaxAlign)
1273 MaxAlign = EltAlign;
1280 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
1281 /// function arguments in the caller parameter area. For X86, aggregates
1282 /// that contain SSE vectors are placed at 16-byte boundaries while the rest
1283 /// are at 4-byte boundaries.
1284 unsigned X86TargetLowering::getByValTypeAlignment(Type *Ty) const {
1285 if (Subtarget->is64Bit()) {
1286 // Max of 8 and alignment of type.
1287 unsigned TyAlign = TD->getABITypeAlignment(Ty);
1294 if (Subtarget->hasSSE1())
1295 getMaxByValAlign(Ty, Align);
1299 /// getOptimalMemOpType - Returns the target specific optimal type for load
1300 /// and store operations as a result of memset, memcpy, and memmove
1301 /// lowering. If DstAlign is zero that means it's safe to destination
1302 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
1303 /// means there isn't a need to check it against alignment requirement,
1304 /// probably because the source does not need to be loaded. If
1305 /// 'IsZeroVal' is true, that means it's safe to return a
1306 /// non-scalar-integer type, e.g. empty string source, constant, or loaded
1307 /// from memory. 'MemcpyStrSrc' indicates whether the memcpy source is
1308 /// constant so it does not need to be loaded.
1309 /// It returns EVT::Other if the type should be determined using generic
1310 /// target-independent logic.
1312 X86TargetLowering::getOptimalMemOpType(uint64_t Size,
1313 unsigned DstAlign, unsigned SrcAlign,
1316 MachineFunction &MF) const {
1317 // FIXME: This turns off use of xmm stores for memset/memcpy on targets like
1318 // linux. This is because the stack realignment code can't handle certain
1319 // cases like PR2962. This should be removed when PR2962 is fixed.
1320 const Function *F = MF.getFunction();
1322 !F->hasFnAttr(Attribute::NoImplicitFloat)) {
1324 (Subtarget->isUnalignedMemAccessFast() ||
1325 ((DstAlign == 0 || DstAlign >= 16) &&
1326 (SrcAlign == 0 || SrcAlign >= 16))) &&
1327 Subtarget->getStackAlignment() >= 16) {
1328 if (Subtarget->getStackAlignment() >= 32) {
1329 if (Subtarget->hasAVX2())
1331 if (Subtarget->hasAVX())
1334 if (Subtarget->hasSSE2())
1336 if (Subtarget->hasSSE1())
1338 } else if (!MemcpyStrSrc && Size >= 8 &&
1339 !Subtarget->is64Bit() &&
1340 Subtarget->getStackAlignment() >= 8 &&
1341 Subtarget->hasSSE2()) {
1342 // Do not use f64 to lower memcpy if source is string constant. It's
1343 // better to use i32 to avoid the loads.
1347 if (Subtarget->is64Bit() && Size >= 8)
1352 /// getJumpTableEncoding - Return the entry encoding for a jump table in the
1353 /// current function. The returned value is a member of the
1354 /// MachineJumpTableInfo::JTEntryKind enum.
1355 unsigned X86TargetLowering::getJumpTableEncoding() const {
1356 // In GOT pic mode, each entry in the jump table is emitted as a @GOTOFF
1358 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1359 Subtarget->isPICStyleGOT())
1360 return MachineJumpTableInfo::EK_Custom32;
1362 // Otherwise, use the normal jump table encoding heuristics.
1363 return TargetLowering::getJumpTableEncoding();
1367 X86TargetLowering::LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI,
1368 const MachineBasicBlock *MBB,
1369 unsigned uid,MCContext &Ctx) const{
1370 assert(getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1371 Subtarget->isPICStyleGOT());
1372 // In 32-bit ELF systems, our jump table entries are formed with @GOTOFF
1374 return MCSymbolRefExpr::Create(MBB->getSymbol(),
1375 MCSymbolRefExpr::VK_GOTOFF, Ctx);
1378 /// getPICJumpTableRelocaBase - Returns relocation base for the given PIC
1380 SDValue X86TargetLowering::getPICJumpTableRelocBase(SDValue Table,
1381 SelectionDAG &DAG) const {
1382 if (!Subtarget->is64Bit())
1383 // This doesn't have DebugLoc associated with it, but is not really the
1384 // same as a Register.
1385 return DAG.getNode(X86ISD::GlobalBaseReg, DebugLoc(), getPointerTy());
1389 /// getPICJumpTableRelocBaseExpr - This returns the relocation base for the
1390 /// given PIC jumptable, the same as getPICJumpTableRelocBase, but as an
1392 const MCExpr *X86TargetLowering::
1393 getPICJumpTableRelocBaseExpr(const MachineFunction *MF, unsigned JTI,
1394 MCContext &Ctx) const {
1395 // X86-64 uses RIP relative addressing based on the jump table label.
1396 if (Subtarget->isPICStyleRIPRel())
1397 return TargetLowering::getPICJumpTableRelocBaseExpr(MF, JTI, Ctx);
1399 // Otherwise, the reference is relative to the PIC base.
1400 return MCSymbolRefExpr::Create(MF->getPICBaseSymbol(), Ctx);
1403 // FIXME: Why this routine is here? Move to RegInfo!
1404 std::pair<const TargetRegisterClass*, uint8_t>
1405 X86TargetLowering::findRepresentativeClass(EVT VT) const{
1406 const TargetRegisterClass *RRC = 0;
1408 switch (VT.getSimpleVT().SimpleTy) {
1410 return TargetLowering::findRepresentativeClass(VT);
1411 case MVT::i8: case MVT::i16: case MVT::i32: case MVT::i64:
1412 RRC = Subtarget->is64Bit() ?
1413 (const TargetRegisterClass*)&X86::GR64RegClass :
1414 (const TargetRegisterClass*)&X86::GR32RegClass;
1417 RRC = &X86::VR64RegClass;
1419 case MVT::f32: case MVT::f64:
1420 case MVT::v16i8: case MVT::v8i16: case MVT::v4i32: case MVT::v2i64:
1421 case MVT::v4f32: case MVT::v2f64:
1422 case MVT::v32i8: case MVT::v8i32: case MVT::v4i64: case MVT::v8f32:
1424 RRC = &X86::VR128RegClass;
1427 return std::make_pair(RRC, Cost);
1430 bool X86TargetLowering::getStackCookieLocation(unsigned &AddressSpace,
1431 unsigned &Offset) const {
1432 if (!Subtarget->isTargetLinux())
1435 if (Subtarget->is64Bit()) {
1436 // %fs:0x28, unless we're using a Kernel code model, in which case it's %gs:
1438 if (getTargetMachine().getCodeModel() == CodeModel::Kernel)
1451 //===----------------------------------------------------------------------===//
1452 // Return Value Calling Convention Implementation
1453 //===----------------------------------------------------------------------===//
1455 #include "X86GenCallingConv.inc"
1458 X86TargetLowering::CanLowerReturn(CallingConv::ID CallConv,
1459 MachineFunction &MF, bool isVarArg,
1460 const SmallVectorImpl<ISD::OutputArg> &Outs,
1461 LLVMContext &Context) const {
1462 SmallVector<CCValAssign, 16> RVLocs;
1463 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(),
1465 return CCInfo.CheckReturn(Outs, RetCC_X86);
1469 X86TargetLowering::LowerReturn(SDValue Chain,
1470 CallingConv::ID CallConv, bool isVarArg,
1471 const SmallVectorImpl<ISD::OutputArg> &Outs,
1472 const SmallVectorImpl<SDValue> &OutVals,
1473 DebugLoc dl, SelectionDAG &DAG) const {
1474 MachineFunction &MF = DAG.getMachineFunction();
1475 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1477 SmallVector<CCValAssign, 16> RVLocs;
1478 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(),
1479 RVLocs, *DAG.getContext());
1480 CCInfo.AnalyzeReturn(Outs, RetCC_X86);
1482 // Add the regs to the liveout set for the function.
1483 MachineRegisterInfo &MRI = DAG.getMachineFunction().getRegInfo();
1484 for (unsigned i = 0; i != RVLocs.size(); ++i)
1485 if (RVLocs[i].isRegLoc() && !MRI.isLiveOut(RVLocs[i].getLocReg()))
1486 MRI.addLiveOut(RVLocs[i].getLocReg());
1490 SmallVector<SDValue, 6> RetOps;
1491 RetOps.push_back(Chain); // Operand #0 = Chain (updated below)
1492 // Operand #1 = Bytes To Pop
1493 RetOps.push_back(DAG.getTargetConstant(FuncInfo->getBytesToPopOnReturn(),
1496 // Copy the result values into the output registers.
1497 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1498 CCValAssign &VA = RVLocs[i];
1499 assert(VA.isRegLoc() && "Can only return in registers!");
1500 SDValue ValToCopy = OutVals[i];
1501 EVT ValVT = ValToCopy.getValueType();
1503 // If this is x86-64, and we disabled SSE, we can't return FP values,
1504 // or SSE or MMX vectors.
1505 if ((ValVT == MVT::f32 || ValVT == MVT::f64 ||
1506 VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) &&
1507 (Subtarget->is64Bit() && !Subtarget->hasSSE1())) {
1508 report_fatal_error("SSE register return with SSE disabled");
1510 // Likewise we can't return F64 values with SSE1 only. gcc does so, but
1511 // llvm-gcc has never done it right and no one has noticed, so this
1512 // should be OK for now.
1513 if (ValVT == MVT::f64 &&
1514 (Subtarget->is64Bit() && !Subtarget->hasSSE2()))
1515 report_fatal_error("SSE2 register return with SSE2 disabled");
1517 // Returns in ST0/ST1 are handled specially: these are pushed as operands to
1518 // the RET instruction and handled by the FP Stackifier.
1519 if (VA.getLocReg() == X86::ST0 ||
1520 VA.getLocReg() == X86::ST1) {
1521 // If this is a copy from an xmm register to ST(0), use an FPExtend to
1522 // change the value to the FP stack register class.
1523 if (isScalarFPTypeInSSEReg(VA.getValVT()))
1524 ValToCopy = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f80, ValToCopy);
1525 RetOps.push_back(ValToCopy);
1526 // Don't emit a copytoreg.
1530 // 64-bit vector (MMX) values are returned in XMM0 / XMM1 except for v1i64
1531 // which is returned in RAX / RDX.
1532 if (Subtarget->is64Bit()) {
1533 if (ValVT == MVT::x86mmx) {
1534 if (VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) {
1535 ValToCopy = DAG.getNode(ISD::BITCAST, dl, MVT::i64, ValToCopy);
1536 ValToCopy = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
1538 // If we don't have SSE2 available, convert to v4f32 so the generated
1539 // register is legal.
1540 if (!Subtarget->hasSSE2())
1541 ValToCopy = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32,ValToCopy);
1546 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), ValToCopy, Flag);
1547 Flag = Chain.getValue(1);
1550 // The x86-64 ABI for returning structs by value requires that we copy
1551 // the sret argument into %rax for the return. We saved the argument into
1552 // a virtual register in the entry block, so now we copy the value out
1554 if (Subtarget->is64Bit() &&
1555 DAG.getMachineFunction().getFunction()->hasStructRetAttr()) {
1556 MachineFunction &MF = DAG.getMachineFunction();
1557 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1558 unsigned Reg = FuncInfo->getSRetReturnReg();
1560 "SRetReturnReg should have been set in LowerFormalArguments().");
1561 SDValue Val = DAG.getCopyFromReg(Chain, dl, Reg, getPointerTy());
1563 Chain = DAG.getCopyToReg(Chain, dl, X86::RAX, Val, Flag);
1564 Flag = Chain.getValue(1);
1566 // RAX now acts like a return value.
1567 MRI.addLiveOut(X86::RAX);
1570 RetOps[0] = Chain; // Update chain.
1572 // Add the flag if we have it.
1574 RetOps.push_back(Flag);
1576 return DAG.getNode(X86ISD::RET_FLAG, dl,
1577 MVT::Other, &RetOps[0], RetOps.size());
1580 bool X86TargetLowering::isUsedByReturnOnly(SDNode *N, SDValue &Chain) const {
1581 if (N->getNumValues() != 1)
1583 if (!N->hasNUsesOfValue(1, 0))
1586 SDValue TCChain = Chain;
1587 SDNode *Copy = *N->use_begin();
1588 if (Copy->getOpcode() == ISD::CopyToReg) {
1589 // If the copy has a glue operand, we conservatively assume it isn't safe to
1590 // perform a tail call.
1591 if (Copy->getOperand(Copy->getNumOperands()-1).getValueType() == MVT::Glue)
1593 TCChain = Copy->getOperand(0);
1594 } else if (Copy->getOpcode() != ISD::FP_EXTEND)
1597 bool HasRet = false;
1598 for (SDNode::use_iterator UI = Copy->use_begin(), UE = Copy->use_end();
1600 if (UI->getOpcode() != X86ISD::RET_FLAG)
1613 X86TargetLowering::getTypeForExtArgOrReturn(LLVMContext &Context, EVT VT,
1614 ISD::NodeType ExtendKind) const {
1616 // TODO: Is this also valid on 32-bit?
1617 if (Subtarget->is64Bit() && VT == MVT::i1 && ExtendKind == ISD::ZERO_EXTEND)
1618 ReturnMVT = MVT::i8;
1620 ReturnMVT = MVT::i32;
1622 EVT MinVT = getRegisterType(Context, ReturnMVT);
1623 return VT.bitsLT(MinVT) ? MinVT : VT;
1626 /// LowerCallResult - Lower the result values of a call into the
1627 /// appropriate copies out of appropriate physical registers.
1630 X86TargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
1631 CallingConv::ID CallConv, bool isVarArg,
1632 const SmallVectorImpl<ISD::InputArg> &Ins,
1633 DebugLoc dl, SelectionDAG &DAG,
1634 SmallVectorImpl<SDValue> &InVals) const {
1636 // Assign locations to each value returned by this call.
1637 SmallVector<CCValAssign, 16> RVLocs;
1638 bool Is64Bit = Subtarget->is64Bit();
1639 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
1640 getTargetMachine(), RVLocs, *DAG.getContext());
1641 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
1643 // Copy all of the result registers out of their specified physreg.
1644 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1645 CCValAssign &VA = RVLocs[i];
1646 EVT CopyVT = VA.getValVT();
1648 // If this is x86-64, and we disabled SSE, we can't return FP values
1649 if ((CopyVT == MVT::f32 || CopyVT == MVT::f64) &&
1650 ((Is64Bit || Ins[i].Flags.isInReg()) && !Subtarget->hasSSE1())) {
1651 report_fatal_error("SSE register return with SSE disabled");
1656 // If this is a call to a function that returns an fp value on the floating
1657 // point stack, we must guarantee the the value is popped from the stack, so
1658 // a CopyFromReg is not good enough - the copy instruction may be eliminated
1659 // if the return value is not used. We use the FpPOP_RETVAL instruction
1661 if (VA.getLocReg() == X86::ST0 || VA.getLocReg() == X86::ST1) {
1662 // If we prefer to use the value in xmm registers, copy it out as f80 and
1663 // use a truncate to move it from fp stack reg to xmm reg.
1664 if (isScalarFPTypeInSSEReg(VA.getValVT())) CopyVT = MVT::f80;
1665 SDValue Ops[] = { Chain, InFlag };
1666 Chain = SDValue(DAG.getMachineNode(X86::FpPOP_RETVAL, dl, CopyVT,
1667 MVT::Other, MVT::Glue, Ops, 2), 1);
1668 Val = Chain.getValue(0);
1670 // Round the f80 to the right size, which also moves it to the appropriate
1672 if (CopyVT != VA.getValVT())
1673 Val = DAG.getNode(ISD::FP_ROUND, dl, VA.getValVT(), Val,
1674 // This truncation won't change the value.
1675 DAG.getIntPtrConstant(1));
1677 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(),
1678 CopyVT, InFlag).getValue(1);
1679 Val = Chain.getValue(0);
1681 InFlag = Chain.getValue(2);
1682 InVals.push_back(Val);
1689 //===----------------------------------------------------------------------===//
1690 // C & StdCall & Fast Calling Convention implementation
1691 //===----------------------------------------------------------------------===//
1692 // StdCall calling convention seems to be standard for many Windows' API
1693 // routines and around. It differs from C calling convention just a little:
1694 // callee should clean up the stack, not caller. Symbols should be also
1695 // decorated in some fancy way :) It doesn't support any vector arguments.
1696 // For info on fast calling convention see Fast Calling Convention (tail call)
1697 // implementation LowerX86_32FastCCCallTo.
1699 /// CallIsStructReturn - Determines whether a call uses struct return
1701 static bool CallIsStructReturn(const SmallVectorImpl<ISD::OutputArg> &Outs) {
1705 return Outs[0].Flags.isSRet();
1708 /// ArgsAreStructReturn - Determines whether a function uses struct
1709 /// return semantics.
1711 ArgsAreStructReturn(const SmallVectorImpl<ISD::InputArg> &Ins) {
1715 return Ins[0].Flags.isSRet();
1718 /// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified
1719 /// by "Src" to address "Dst" with size and alignment information specified by
1720 /// the specific parameter attribute. The copy will be passed as a byval
1721 /// function parameter.
1723 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
1724 ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
1726 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32);
1728 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
1729 /*isVolatile*/false, /*AlwaysInline=*/true,
1730 MachinePointerInfo(), MachinePointerInfo());
1733 /// IsTailCallConvention - Return true if the calling convention is one that
1734 /// supports tail call optimization.
1735 static bool IsTailCallConvention(CallingConv::ID CC) {
1736 return (CC == CallingConv::Fast || CC == CallingConv::GHC);
1739 bool X86TargetLowering::mayBeEmittedAsTailCall(CallInst *CI) const {
1740 if (!CI->isTailCall() || getTargetMachine().Options.DisableTailCalls)
1744 CallingConv::ID CalleeCC = CS.getCallingConv();
1745 if (!IsTailCallConvention(CalleeCC) && CalleeCC != CallingConv::C)
1751 /// FuncIsMadeTailCallSafe - Return true if the function is being made into
1752 /// a tailcall target by changing its ABI.
1753 static bool FuncIsMadeTailCallSafe(CallingConv::ID CC,
1754 bool GuaranteedTailCallOpt) {
1755 return GuaranteedTailCallOpt && IsTailCallConvention(CC);
1759 X86TargetLowering::LowerMemArgument(SDValue Chain,
1760 CallingConv::ID CallConv,
1761 const SmallVectorImpl<ISD::InputArg> &Ins,
1762 DebugLoc dl, SelectionDAG &DAG,
1763 const CCValAssign &VA,
1764 MachineFrameInfo *MFI,
1766 // Create the nodes corresponding to a load from this parameter slot.
1767 ISD::ArgFlagsTy Flags = Ins[i].Flags;
1768 bool AlwaysUseMutable = FuncIsMadeTailCallSafe(CallConv,
1769 getTargetMachine().Options.GuaranteedTailCallOpt);
1770 bool isImmutable = !AlwaysUseMutable && !Flags.isByVal();
1773 // If value is passed by pointer we have address passed instead of the value
1775 if (VA.getLocInfo() == CCValAssign::Indirect)
1776 ValVT = VA.getLocVT();
1778 ValVT = VA.getValVT();
1780 // FIXME: For now, all byval parameter objects are marked mutable. This can be
1781 // changed with more analysis.
1782 // In case of tail call optimization mark all arguments mutable. Since they
1783 // could be overwritten by lowering of arguments in case of a tail call.
1784 if (Flags.isByVal()) {
1785 unsigned Bytes = Flags.getByValSize();
1786 if (Bytes == 0) Bytes = 1; // Don't create zero-sized stack objects.
1787 int FI = MFI->CreateFixedObject(Bytes, VA.getLocMemOffset(), isImmutable);
1788 return DAG.getFrameIndex(FI, getPointerTy());
1790 int FI = MFI->CreateFixedObject(ValVT.getSizeInBits()/8,
1791 VA.getLocMemOffset(), isImmutable);
1792 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
1793 return DAG.getLoad(ValVT, dl, Chain, FIN,
1794 MachinePointerInfo::getFixedStack(FI),
1795 false, false, false, 0);
1800 X86TargetLowering::LowerFormalArguments(SDValue Chain,
1801 CallingConv::ID CallConv,
1803 const SmallVectorImpl<ISD::InputArg> &Ins,
1806 SmallVectorImpl<SDValue> &InVals)
1808 MachineFunction &MF = DAG.getMachineFunction();
1809 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1811 const Function* Fn = MF.getFunction();
1812 if (Fn->hasExternalLinkage() &&
1813 Subtarget->isTargetCygMing() &&
1814 Fn->getName() == "main")
1815 FuncInfo->setForceFramePointer(true);
1817 MachineFrameInfo *MFI = MF.getFrameInfo();
1818 bool Is64Bit = Subtarget->is64Bit();
1819 bool IsWindows = Subtarget->isTargetWindows();
1820 bool IsWin64 = Subtarget->isTargetWin64();
1822 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
1823 "Var args not supported with calling convention fastcc or ghc");
1825 // Assign locations to all of the incoming arguments.
1826 SmallVector<CCValAssign, 16> ArgLocs;
1827 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(),
1828 ArgLocs, *DAG.getContext());
1830 // Allocate shadow area for Win64
1832 CCInfo.AllocateStack(32, 8);
1835 CCInfo.AnalyzeFormalArguments(Ins, CC_X86);
1837 unsigned LastVal = ~0U;
1839 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1840 CCValAssign &VA = ArgLocs[i];
1841 // TODO: If an arg is passed in two places (e.g. reg and stack), skip later
1843 assert(VA.getValNo() != LastVal &&
1844 "Don't support value assigned to multiple locs yet");
1846 LastVal = VA.getValNo();
1848 if (VA.isRegLoc()) {
1849 EVT RegVT = VA.getLocVT();
1850 const TargetRegisterClass *RC;
1851 if (RegVT == MVT::i32)
1852 RC = &X86::GR32RegClass;
1853 else if (Is64Bit && RegVT == MVT::i64)
1854 RC = &X86::GR64RegClass;
1855 else if (RegVT == MVT::f32)
1856 RC = &X86::FR32RegClass;
1857 else if (RegVT == MVT::f64)
1858 RC = &X86::FR64RegClass;
1859 else if (RegVT.isVector() && RegVT.getSizeInBits() == 256)
1860 RC = &X86::VR256RegClass;
1861 else if (RegVT.isVector() && RegVT.getSizeInBits() == 128)
1862 RC = &X86::VR128RegClass;
1863 else if (RegVT == MVT::x86mmx)
1864 RC = &X86::VR64RegClass;
1866 llvm_unreachable("Unknown argument type!");
1868 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
1869 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
1871 // If this is an 8 or 16-bit value, it is really passed promoted to 32
1872 // bits. Insert an assert[sz]ext to capture this, then truncate to the
1874 if (VA.getLocInfo() == CCValAssign::SExt)
1875 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
1876 DAG.getValueType(VA.getValVT()));
1877 else if (VA.getLocInfo() == CCValAssign::ZExt)
1878 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
1879 DAG.getValueType(VA.getValVT()));
1880 else if (VA.getLocInfo() == CCValAssign::BCvt)
1881 ArgValue = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), ArgValue);
1883 if (VA.isExtInLoc()) {
1884 // Handle MMX values passed in XMM regs.
1885 if (RegVT.isVector()) {
1886 ArgValue = DAG.getNode(X86ISD::MOVDQ2Q, dl, VA.getValVT(),
1889 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
1892 assert(VA.isMemLoc());
1893 ArgValue = LowerMemArgument(Chain, CallConv, Ins, dl, DAG, VA, MFI, i);
1896 // If value is passed via pointer - do a load.
1897 if (VA.getLocInfo() == CCValAssign::Indirect)
1898 ArgValue = DAG.getLoad(VA.getValVT(), dl, Chain, ArgValue,
1899 MachinePointerInfo(), false, false, false, 0);
1901 InVals.push_back(ArgValue);
1904 // The x86-64 ABI for returning structs by value requires that we copy
1905 // the sret argument into %rax for the return. Save the argument into
1906 // a virtual register so that we can access it from the return points.
1907 if (Is64Bit && MF.getFunction()->hasStructRetAttr()) {
1908 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1909 unsigned Reg = FuncInfo->getSRetReturnReg();
1911 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(MVT::i64));
1912 FuncInfo->setSRetReturnReg(Reg);
1914 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, InVals[0]);
1915 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain);
1918 unsigned StackSize = CCInfo.getNextStackOffset();
1919 // Align stack specially for tail calls.
1920 if (FuncIsMadeTailCallSafe(CallConv,
1921 MF.getTarget().Options.GuaranteedTailCallOpt))
1922 StackSize = GetAlignedArgumentStackSize(StackSize, DAG);
1924 // If the function takes variable number of arguments, make a frame index for
1925 // the start of the first vararg value... for expansion of llvm.va_start.
1927 if (Is64Bit || (CallConv != CallingConv::X86_FastCall &&
1928 CallConv != CallingConv::X86_ThisCall)) {
1929 FuncInfo->setVarArgsFrameIndex(MFI->CreateFixedObject(1, StackSize,true));
1932 unsigned TotalNumIntRegs = 0, TotalNumXMMRegs = 0;
1934 // FIXME: We should really autogenerate these arrays
1935 static const uint16_t GPR64ArgRegsWin64[] = {
1936 X86::RCX, X86::RDX, X86::R8, X86::R9
1938 static const uint16_t GPR64ArgRegs64Bit[] = {
1939 X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9
1941 static const uint16_t XMMArgRegs64Bit[] = {
1942 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
1943 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
1945 const uint16_t *GPR64ArgRegs;
1946 unsigned NumXMMRegs = 0;
1949 // The XMM registers which might contain var arg parameters are shadowed
1950 // in their paired GPR. So we only need to save the GPR to their home
1952 TotalNumIntRegs = 4;
1953 GPR64ArgRegs = GPR64ArgRegsWin64;
1955 TotalNumIntRegs = 6; TotalNumXMMRegs = 8;
1956 GPR64ArgRegs = GPR64ArgRegs64Bit;
1958 NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs64Bit,
1961 unsigned NumIntRegs = CCInfo.getFirstUnallocated(GPR64ArgRegs,
1964 bool NoImplicitFloatOps = Fn->hasFnAttr(Attribute::NoImplicitFloat);
1965 assert(!(NumXMMRegs && !Subtarget->hasSSE1()) &&
1966 "SSE register cannot be used when SSE is disabled!");
1967 assert(!(NumXMMRegs && MF.getTarget().Options.UseSoftFloat &&
1968 NoImplicitFloatOps) &&
1969 "SSE register cannot be used when SSE is disabled!");
1970 if (MF.getTarget().Options.UseSoftFloat || NoImplicitFloatOps ||
1971 !Subtarget->hasSSE1())
1972 // Kernel mode asks for SSE to be disabled, so don't push them
1974 TotalNumXMMRegs = 0;
1977 const TargetFrameLowering &TFI = *getTargetMachine().getFrameLowering();
1978 // Get to the caller-allocated home save location. Add 8 to account
1979 // for the return address.
1980 int HomeOffset = TFI.getOffsetOfLocalArea() + 8;
1981 FuncInfo->setRegSaveFrameIndex(
1982 MFI->CreateFixedObject(1, NumIntRegs * 8 + HomeOffset, false));
1983 // Fixup to set vararg frame on shadow area (4 x i64).
1985 FuncInfo->setVarArgsFrameIndex(FuncInfo->getRegSaveFrameIndex());
1987 // For X86-64, if there are vararg parameters that are passed via
1988 // registers, then we must store them to their spots on the stack so
1989 // they may be loaded by deferencing the result of va_next.
1990 FuncInfo->setVarArgsGPOffset(NumIntRegs * 8);
1991 FuncInfo->setVarArgsFPOffset(TotalNumIntRegs * 8 + NumXMMRegs * 16);
1992 FuncInfo->setRegSaveFrameIndex(
1993 MFI->CreateStackObject(TotalNumIntRegs * 8 + TotalNumXMMRegs * 16, 16,
1997 // Store the integer parameter registers.
1998 SmallVector<SDValue, 8> MemOps;
1999 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
2001 unsigned Offset = FuncInfo->getVarArgsGPOffset();
2002 for (; NumIntRegs != TotalNumIntRegs; ++NumIntRegs) {
2003 SDValue FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), RSFIN,
2004 DAG.getIntPtrConstant(Offset));
2005 unsigned VReg = MF.addLiveIn(GPR64ArgRegs[NumIntRegs],
2006 &X86::GR64RegClass);
2007 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64);
2009 DAG.getStore(Val.getValue(1), dl, Val, FIN,
2010 MachinePointerInfo::getFixedStack(
2011 FuncInfo->getRegSaveFrameIndex(), Offset),
2013 MemOps.push_back(Store);
2017 if (TotalNumXMMRegs != 0 && NumXMMRegs != TotalNumXMMRegs) {
2018 // Now store the XMM (fp + vector) parameter registers.
2019 SmallVector<SDValue, 11> SaveXMMOps;
2020 SaveXMMOps.push_back(Chain);
2022 unsigned AL = MF.addLiveIn(X86::AL, &X86::GR8RegClass);
2023 SDValue ALVal = DAG.getCopyFromReg(DAG.getEntryNode(), dl, AL, MVT::i8);
2024 SaveXMMOps.push_back(ALVal);
2026 SaveXMMOps.push_back(DAG.getIntPtrConstant(
2027 FuncInfo->getRegSaveFrameIndex()));
2028 SaveXMMOps.push_back(DAG.getIntPtrConstant(
2029 FuncInfo->getVarArgsFPOffset()));
2031 for (; NumXMMRegs != TotalNumXMMRegs; ++NumXMMRegs) {
2032 unsigned VReg = MF.addLiveIn(XMMArgRegs64Bit[NumXMMRegs],
2033 &X86::VR128RegClass);
2034 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::v4f32);
2035 SaveXMMOps.push_back(Val);
2037 MemOps.push_back(DAG.getNode(X86ISD::VASTART_SAVE_XMM_REGS, dl,
2039 &SaveXMMOps[0], SaveXMMOps.size()));
2042 if (!MemOps.empty())
2043 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
2044 &MemOps[0], MemOps.size());
2048 // Some CCs need callee pop.
2049 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg,
2050 MF.getTarget().Options.GuaranteedTailCallOpt)) {
2051 FuncInfo->setBytesToPopOnReturn(StackSize); // Callee pops everything.
2053 FuncInfo->setBytesToPopOnReturn(0); // Callee pops nothing.
2054 // If this is an sret function, the return should pop the hidden pointer.
2055 if (!Is64Bit && !IsTailCallConvention(CallConv) && !IsWindows &&
2056 ArgsAreStructReturn(Ins))
2057 FuncInfo->setBytesToPopOnReturn(4);
2061 // RegSaveFrameIndex is X86-64 only.
2062 FuncInfo->setRegSaveFrameIndex(0xAAAAAAA);
2063 if (CallConv == CallingConv::X86_FastCall ||
2064 CallConv == CallingConv::X86_ThisCall)
2065 // fastcc functions can't have varargs.
2066 FuncInfo->setVarArgsFrameIndex(0xAAAAAAA);
2069 FuncInfo->setArgumentStackSize(StackSize);
2075 X86TargetLowering::LowerMemOpCallTo(SDValue Chain,
2076 SDValue StackPtr, SDValue Arg,
2077 DebugLoc dl, SelectionDAG &DAG,
2078 const CCValAssign &VA,
2079 ISD::ArgFlagsTy Flags) const {
2080 unsigned LocMemOffset = VA.getLocMemOffset();
2081 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
2082 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
2083 if (Flags.isByVal())
2084 return CreateCopyOfByValArgument(Arg, PtrOff, Chain, Flags, DAG, dl);
2086 return DAG.getStore(Chain, dl, Arg, PtrOff,
2087 MachinePointerInfo::getStack(LocMemOffset),
2091 /// EmitTailCallLoadRetAddr - Emit a load of return address if tail call
2092 /// optimization is performed and it is required.
2094 X86TargetLowering::EmitTailCallLoadRetAddr(SelectionDAG &DAG,
2095 SDValue &OutRetAddr, SDValue Chain,
2096 bool IsTailCall, bool Is64Bit,
2097 int FPDiff, DebugLoc dl) const {
2098 // Adjust the Return address stack slot.
2099 EVT VT = getPointerTy();
2100 OutRetAddr = getReturnAddressFrameIndex(DAG);
2102 // Load the "old" Return address.
2103 OutRetAddr = DAG.getLoad(VT, dl, Chain, OutRetAddr, MachinePointerInfo(),
2104 false, false, false, 0);
2105 return SDValue(OutRetAddr.getNode(), 1);
2108 /// EmitTailCallStoreRetAddr - Emit a store of the return address if tail call
2109 /// optimization is performed and it is required (FPDiff!=0).
2111 EmitTailCallStoreRetAddr(SelectionDAG & DAG, MachineFunction &MF,
2112 SDValue Chain, SDValue RetAddrFrIdx,
2113 bool Is64Bit, int FPDiff, DebugLoc dl) {
2114 // Store the return address to the appropriate stack slot.
2115 if (!FPDiff) return Chain;
2116 // Calculate the new stack slot for the return address.
2117 int SlotSize = Is64Bit ? 8 : 4;
2118 int NewReturnAddrFI =
2119 MF.getFrameInfo()->CreateFixedObject(SlotSize, FPDiff-SlotSize, false);
2120 EVT VT = Is64Bit ? MVT::i64 : MVT::i32;
2121 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewReturnAddrFI, VT);
2122 Chain = DAG.getStore(Chain, dl, RetAddrFrIdx, NewRetAddrFrIdx,
2123 MachinePointerInfo::getFixedStack(NewReturnAddrFI),
2129 X86TargetLowering::LowerCall(SDValue Chain, SDValue Callee,
2130 CallingConv::ID CallConv, bool isVarArg,
2131 bool doesNotRet, bool &isTailCall,
2132 const SmallVectorImpl<ISD::OutputArg> &Outs,
2133 const SmallVectorImpl<SDValue> &OutVals,
2134 const SmallVectorImpl<ISD::InputArg> &Ins,
2135 DebugLoc dl, SelectionDAG &DAG,
2136 SmallVectorImpl<SDValue> &InVals) const {
2137 MachineFunction &MF = DAG.getMachineFunction();
2138 bool Is64Bit = Subtarget->is64Bit();
2139 bool IsWin64 = Subtarget->isTargetWin64();
2140 bool IsWindows = Subtarget->isTargetWindows();
2141 bool IsStructRet = CallIsStructReturn(Outs);
2142 bool IsSibcall = false;
2144 if (MF.getTarget().Options.DisableTailCalls)
2148 // Check if it's really possible to do a tail call.
2149 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv,
2150 isVarArg, IsStructRet, MF.getFunction()->hasStructRetAttr(),
2151 Outs, OutVals, Ins, DAG);
2153 // Sibcalls are automatically detected tailcalls which do not require
2155 if (!MF.getTarget().Options.GuaranteedTailCallOpt && isTailCall)
2162 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
2163 "Var args not supported with calling convention fastcc or ghc");
2165 // Analyze operands of the call, assigning locations to each operand.
2166 SmallVector<CCValAssign, 16> ArgLocs;
2167 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(),
2168 ArgLocs, *DAG.getContext());
2170 // Allocate shadow area for Win64
2172 CCInfo.AllocateStack(32, 8);
2175 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
2177 // Get a count of how many bytes are to be pushed on the stack.
2178 unsigned NumBytes = CCInfo.getNextStackOffset();
2180 // This is a sibcall. The memory operands are available in caller's
2181 // own caller's stack.
2183 else if (getTargetMachine().Options.GuaranteedTailCallOpt &&
2184 IsTailCallConvention(CallConv))
2185 NumBytes = GetAlignedArgumentStackSize(NumBytes, DAG);
2188 if (isTailCall && !IsSibcall) {
2189 // Lower arguments at fp - stackoffset + fpdiff.
2190 unsigned NumBytesCallerPushed =
2191 MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn();
2192 FPDiff = NumBytesCallerPushed - NumBytes;
2194 // Set the delta of movement of the returnaddr stackslot.
2195 // But only set if delta is greater than previous delta.
2196 if (FPDiff < (MF.getInfo<X86MachineFunctionInfo>()->getTCReturnAddrDelta()))
2197 MF.getInfo<X86MachineFunctionInfo>()->setTCReturnAddrDelta(FPDiff);
2201 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true));
2203 SDValue RetAddrFrIdx;
2204 // Load return address for tail calls.
2205 if (isTailCall && FPDiff)
2206 Chain = EmitTailCallLoadRetAddr(DAG, RetAddrFrIdx, Chain, isTailCall,
2207 Is64Bit, FPDiff, dl);
2209 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
2210 SmallVector<SDValue, 8> MemOpChains;
2213 // Walk the register/memloc assignments, inserting copies/loads. In the case
2214 // of tail call optimization arguments are handle later.
2215 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2216 CCValAssign &VA = ArgLocs[i];
2217 EVT RegVT = VA.getLocVT();
2218 SDValue Arg = OutVals[i];
2219 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2220 bool isByVal = Flags.isByVal();
2222 // Promote the value if needed.
2223 switch (VA.getLocInfo()) {
2224 default: llvm_unreachable("Unknown loc info!");
2225 case CCValAssign::Full: break;
2226 case CCValAssign::SExt:
2227 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, RegVT, Arg);
2229 case CCValAssign::ZExt:
2230 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, RegVT, Arg);
2232 case CCValAssign::AExt:
2233 if (RegVT.isVector() && RegVT.getSizeInBits() == 128) {
2234 // Special case: passing MMX values in XMM registers.
2235 Arg = DAG.getNode(ISD::BITCAST, dl, MVT::i64, Arg);
2236 Arg = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, Arg);
2237 Arg = getMOVL(DAG, dl, MVT::v2i64, DAG.getUNDEF(MVT::v2i64), Arg);
2239 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, RegVT, Arg);
2241 case CCValAssign::BCvt:
2242 Arg = DAG.getNode(ISD::BITCAST, dl, RegVT, Arg);
2244 case CCValAssign::Indirect: {
2245 // Store the argument.
2246 SDValue SpillSlot = DAG.CreateStackTemporary(VA.getValVT());
2247 int FI = cast<FrameIndexSDNode>(SpillSlot)->getIndex();
2248 Chain = DAG.getStore(Chain, dl, Arg, SpillSlot,
2249 MachinePointerInfo::getFixedStack(FI),
2256 if (VA.isRegLoc()) {
2257 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
2258 if (isVarArg && IsWin64) {
2259 // Win64 ABI requires argument XMM reg to be copied to the corresponding
2260 // shadow reg if callee is a varargs function.
2261 unsigned ShadowReg = 0;
2262 switch (VA.getLocReg()) {
2263 case X86::XMM0: ShadowReg = X86::RCX; break;
2264 case X86::XMM1: ShadowReg = X86::RDX; break;
2265 case X86::XMM2: ShadowReg = X86::R8; break;
2266 case X86::XMM3: ShadowReg = X86::R9; break;
2269 RegsToPass.push_back(std::make_pair(ShadowReg, Arg));
2271 } else if (!IsSibcall && (!isTailCall || isByVal)) {
2272 assert(VA.isMemLoc());
2273 if (StackPtr.getNode() == 0)
2274 StackPtr = DAG.getCopyFromReg(Chain, dl, X86StackPtr, getPointerTy());
2275 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Arg,
2276 dl, DAG, VA, Flags));
2280 if (!MemOpChains.empty())
2281 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
2282 &MemOpChains[0], MemOpChains.size());
2284 // Build a sequence of copy-to-reg nodes chained together with token chain
2285 // and flag operands which copy the outgoing args into registers.
2287 // Tail call byval lowering might overwrite argument registers so in case of
2288 // tail call optimization the copies to registers are lowered later.
2290 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
2291 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
2292 RegsToPass[i].second, InFlag);
2293 InFlag = Chain.getValue(1);
2296 if (Subtarget->isPICStyleGOT()) {
2297 // ELF / PIC requires GOT in the EBX register before function calls via PLT
2300 Chain = DAG.getCopyToReg(Chain, dl, X86::EBX,
2301 DAG.getNode(X86ISD::GlobalBaseReg,
2302 DebugLoc(), getPointerTy()),
2304 InFlag = Chain.getValue(1);
2306 // If we are tail calling and generating PIC/GOT style code load the
2307 // address of the callee into ECX. The value in ecx is used as target of
2308 // the tail jump. This is done to circumvent the ebx/callee-saved problem
2309 // for tail calls on PIC/GOT architectures. Normally we would just put the
2310 // address of GOT into ebx and then call target@PLT. But for tail calls
2311 // ebx would be restored (since ebx is callee saved) before jumping to the
2314 // Note: The actual moving to ECX is done further down.
2315 GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee);
2316 if (G && !G->getGlobal()->hasHiddenVisibility() &&
2317 !G->getGlobal()->hasProtectedVisibility())
2318 Callee = LowerGlobalAddress(Callee, DAG);
2319 else if (isa<ExternalSymbolSDNode>(Callee))
2320 Callee = LowerExternalSymbol(Callee, DAG);
2324 if (Is64Bit && isVarArg && !IsWin64) {
2325 // From AMD64 ABI document:
2326 // For calls that may call functions that use varargs or stdargs
2327 // (prototype-less calls or calls to functions containing ellipsis (...) in
2328 // the declaration) %al is used as hidden argument to specify the number
2329 // of SSE registers used. The contents of %al do not need to match exactly
2330 // the number of registers, but must be an ubound on the number of SSE
2331 // registers used and is in the range 0 - 8 inclusive.
2333 // Count the number of XMM registers allocated.
2334 static const uint16_t XMMArgRegs[] = {
2335 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
2336 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
2338 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs, 8);
2339 assert((Subtarget->hasSSE1() || !NumXMMRegs)
2340 && "SSE registers cannot be used when SSE is disabled");
2342 Chain = DAG.getCopyToReg(Chain, dl, X86::AL,
2343 DAG.getConstant(NumXMMRegs, MVT::i8), InFlag);
2344 InFlag = Chain.getValue(1);
2348 // For tail calls lower the arguments to the 'real' stack slot.
2350 // Force all the incoming stack arguments to be loaded from the stack
2351 // before any new outgoing arguments are stored to the stack, because the
2352 // outgoing stack slots may alias the incoming argument stack slots, and
2353 // the alias isn't otherwise explicit. This is slightly more conservative
2354 // than necessary, because it means that each store effectively depends
2355 // on every argument instead of just those arguments it would clobber.
2356 SDValue ArgChain = DAG.getStackArgumentTokenFactor(Chain);
2358 SmallVector<SDValue, 8> MemOpChains2;
2361 // Do not flag preceding copytoreg stuff together with the following stuff.
2363 if (getTargetMachine().Options.GuaranteedTailCallOpt) {
2364 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2365 CCValAssign &VA = ArgLocs[i];
2368 assert(VA.isMemLoc());
2369 SDValue Arg = OutVals[i];
2370 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2371 // Create frame index.
2372 int32_t Offset = VA.getLocMemOffset()+FPDiff;
2373 uint32_t OpSize = (VA.getLocVT().getSizeInBits()+7)/8;
2374 FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true);
2375 FIN = DAG.getFrameIndex(FI, getPointerTy());
2377 if (Flags.isByVal()) {
2378 // Copy relative to framepointer.
2379 SDValue Source = DAG.getIntPtrConstant(VA.getLocMemOffset());
2380 if (StackPtr.getNode() == 0)
2381 StackPtr = DAG.getCopyFromReg(Chain, dl, X86StackPtr,
2383 Source = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, Source);
2385 MemOpChains2.push_back(CreateCopyOfByValArgument(Source, FIN,
2389 // Store relative to framepointer.
2390 MemOpChains2.push_back(
2391 DAG.getStore(ArgChain, dl, Arg, FIN,
2392 MachinePointerInfo::getFixedStack(FI),
2398 if (!MemOpChains2.empty())
2399 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
2400 &MemOpChains2[0], MemOpChains2.size());
2402 // Copy arguments to their registers.
2403 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
2404 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
2405 RegsToPass[i].second, InFlag);
2406 InFlag = Chain.getValue(1);
2410 // Store the return address to the appropriate stack slot.
2411 Chain = EmitTailCallStoreRetAddr(DAG, MF, Chain, RetAddrFrIdx, Is64Bit,
2415 if (getTargetMachine().getCodeModel() == CodeModel::Large) {
2416 assert(Is64Bit && "Large code model is only legal in 64-bit mode.");
2417 // In the 64-bit large code model, we have to make all calls
2418 // through a register, since the call instruction's 32-bit
2419 // pc-relative offset may not be large enough to hold the whole
2421 } else if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
2422 // If the callee is a GlobalAddress node (quite common, every direct call
2423 // is) turn it into a TargetGlobalAddress node so that legalize doesn't hack
2426 // We should use extra load for direct calls to dllimported functions in
2428 const GlobalValue *GV = G->getGlobal();
2429 if (!GV->hasDLLImportLinkage()) {
2430 unsigned char OpFlags = 0;
2431 bool ExtraLoad = false;
2432 unsigned WrapperKind = ISD::DELETED_NODE;
2434 // On ELF targets, in both X86-64 and X86-32 mode, direct calls to
2435 // external symbols most go through the PLT in PIC mode. If the symbol
2436 // has hidden or protected visibility, or if it is static or local, then
2437 // we don't need to use the PLT - we can directly call it.
2438 if (Subtarget->isTargetELF() &&
2439 getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
2440 GV->hasDefaultVisibility() && !GV->hasLocalLinkage()) {
2441 OpFlags = X86II::MO_PLT;
2442 } else if (Subtarget->isPICStyleStubAny() &&
2443 (GV->isDeclaration() || GV->isWeakForLinker()) &&
2444 (!Subtarget->getTargetTriple().isMacOSX() ||
2445 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
2446 // PC-relative references to external symbols should go through $stub,
2447 // unless we're building with the leopard linker or later, which
2448 // automatically synthesizes these stubs.
2449 OpFlags = X86II::MO_DARWIN_STUB;
2450 } else if (Subtarget->isPICStyleRIPRel() &&
2451 isa<Function>(GV) &&
2452 cast<Function>(GV)->hasFnAttr(Attribute::NonLazyBind)) {
2453 // If the function is marked as non-lazy, generate an indirect call
2454 // which loads from the GOT directly. This avoids runtime overhead
2455 // at the cost of eager binding (and one extra byte of encoding).
2456 OpFlags = X86II::MO_GOTPCREL;
2457 WrapperKind = X86ISD::WrapperRIP;
2461 Callee = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(),
2462 G->getOffset(), OpFlags);
2464 // Add a wrapper if needed.
2465 if (WrapperKind != ISD::DELETED_NODE)
2466 Callee = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Callee);
2467 // Add extra indirection if needed.
2469 Callee = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Callee,
2470 MachinePointerInfo::getGOT(),
2471 false, false, false, 0);
2473 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
2474 unsigned char OpFlags = 0;
2476 // On ELF targets, in either X86-64 or X86-32 mode, direct calls to
2477 // external symbols should go through the PLT.
2478 if (Subtarget->isTargetELF() &&
2479 getTargetMachine().getRelocationModel() == Reloc::PIC_) {
2480 OpFlags = X86II::MO_PLT;
2481 } else if (Subtarget->isPICStyleStubAny() &&
2482 (!Subtarget->getTargetTriple().isMacOSX() ||
2483 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
2484 // PC-relative references to external symbols should go through $stub,
2485 // unless we're building with the leopard linker or later, which
2486 // automatically synthesizes these stubs.
2487 OpFlags = X86II::MO_DARWIN_STUB;
2490 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy(),
2494 // Returns a chain & a flag for retval copy to use.
2495 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
2496 SmallVector<SDValue, 8> Ops;
2498 if (!IsSibcall && isTailCall) {
2499 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
2500 DAG.getIntPtrConstant(0, true), InFlag);
2501 InFlag = Chain.getValue(1);
2504 Ops.push_back(Chain);
2505 Ops.push_back(Callee);
2508 Ops.push_back(DAG.getConstant(FPDiff, MVT::i32));
2510 // Add argument registers to the end of the list so that they are known live
2512 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
2513 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
2514 RegsToPass[i].second.getValueType()));
2516 // Add an implicit use GOT pointer in EBX.
2517 if (!isTailCall && Subtarget->isPICStyleGOT())
2518 Ops.push_back(DAG.getRegister(X86::EBX, getPointerTy()));
2520 // Add an implicit use of AL for non-Windows x86 64-bit vararg functions.
2521 if (Is64Bit && isVarArg && !IsWin64)
2522 Ops.push_back(DAG.getRegister(X86::AL, MVT::i8));
2524 // Add a register mask operand representing the call-preserved registers.
2525 const TargetRegisterInfo *TRI = getTargetMachine().getRegisterInfo();
2526 const uint32_t *Mask = TRI->getCallPreservedMask(CallConv);
2527 assert(Mask && "Missing call preserved mask for calling convention");
2528 Ops.push_back(DAG.getRegisterMask(Mask));
2530 if (InFlag.getNode())
2531 Ops.push_back(InFlag);
2535 //// If this is the first return lowered for this function, add the regs
2536 //// to the liveout set for the function.
2537 // This isn't right, although it's probably harmless on x86; liveouts
2538 // should be computed from returns not tail calls. Consider a void
2539 // function making a tail call to a function returning int.
2540 return DAG.getNode(X86ISD::TC_RETURN, dl,
2541 NodeTys, &Ops[0], Ops.size());
2544 Chain = DAG.getNode(X86ISD::CALL, dl, NodeTys, &Ops[0], Ops.size());
2545 InFlag = Chain.getValue(1);
2547 // Create the CALLSEQ_END node.
2548 unsigned NumBytesForCalleeToPush;
2549 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg,
2550 getTargetMachine().Options.GuaranteedTailCallOpt))
2551 NumBytesForCalleeToPush = NumBytes; // Callee pops everything
2552 else if (!Is64Bit && !IsTailCallConvention(CallConv) && !IsWindows &&
2554 // If this is a call to a struct-return function, the callee
2555 // pops the hidden struct pointer, so we have to push it back.
2556 // This is common for Darwin/X86, Linux & Mingw32 targets.
2557 // For MSVC Win32 targets, the caller pops the hidden struct pointer.
2558 NumBytesForCalleeToPush = 4;
2560 NumBytesForCalleeToPush = 0; // Callee pops nothing.
2562 // Returns a flag for retval copy to use.
2564 Chain = DAG.getCALLSEQ_END(Chain,
2565 DAG.getIntPtrConstant(NumBytes, true),
2566 DAG.getIntPtrConstant(NumBytesForCalleeToPush,
2569 InFlag = Chain.getValue(1);
2572 // Handle result values, copying them out of physregs into vregs that we
2574 return LowerCallResult(Chain, InFlag, CallConv, isVarArg,
2575 Ins, dl, DAG, InVals);
2579 //===----------------------------------------------------------------------===//
2580 // Fast Calling Convention (tail call) implementation
2581 //===----------------------------------------------------------------------===//
2583 // Like std call, callee cleans arguments, convention except that ECX is
2584 // reserved for storing the tail called function address. Only 2 registers are
2585 // free for argument passing (inreg). Tail call optimization is performed
2587 // * tailcallopt is enabled
2588 // * caller/callee are fastcc
2589 // On X86_64 architecture with GOT-style position independent code only local
2590 // (within module) calls are supported at the moment.
2591 // To keep the stack aligned according to platform abi the function
2592 // GetAlignedArgumentStackSize ensures that argument delta is always multiples
2593 // of stack alignment. (Dynamic linkers need this - darwin's dyld for example)
2594 // If a tail called function callee has more arguments than the caller the
2595 // caller needs to make sure that there is room to move the RETADDR to. This is
2596 // achieved by reserving an area the size of the argument delta right after the
2597 // original REtADDR, but before the saved framepointer or the spilled registers
2598 // e.g. caller(arg1, arg2) calls callee(arg1, arg2,arg3,arg4)
2610 /// GetAlignedArgumentStackSize - Make the stack size align e.g 16n + 12 aligned
2611 /// for a 16 byte align requirement.
2613 X86TargetLowering::GetAlignedArgumentStackSize(unsigned StackSize,
2614 SelectionDAG& DAG) const {
2615 MachineFunction &MF = DAG.getMachineFunction();
2616 const TargetMachine &TM = MF.getTarget();
2617 const TargetFrameLowering &TFI = *TM.getFrameLowering();
2618 unsigned StackAlignment = TFI.getStackAlignment();
2619 uint64_t AlignMask = StackAlignment - 1;
2620 int64_t Offset = StackSize;
2621 uint64_t SlotSize = TD->getPointerSize();
2622 if ( (Offset & AlignMask) <= (StackAlignment - SlotSize) ) {
2623 // Number smaller than 12 so just add the difference.
2624 Offset += ((StackAlignment - SlotSize) - (Offset & AlignMask));
2626 // Mask out lower bits, add stackalignment once plus the 12 bytes.
2627 Offset = ((~AlignMask) & Offset) + StackAlignment +
2628 (StackAlignment-SlotSize);
2633 /// MatchingStackOffset - Return true if the given stack call argument is
2634 /// already available in the same position (relatively) of the caller's
2635 /// incoming argument stack.
2637 bool MatchingStackOffset(SDValue Arg, unsigned Offset, ISD::ArgFlagsTy Flags,
2638 MachineFrameInfo *MFI, const MachineRegisterInfo *MRI,
2639 const X86InstrInfo *TII) {
2640 unsigned Bytes = Arg.getValueType().getSizeInBits() / 8;
2642 if (Arg.getOpcode() == ISD::CopyFromReg) {
2643 unsigned VR = cast<RegisterSDNode>(Arg.getOperand(1))->getReg();
2644 if (!TargetRegisterInfo::isVirtualRegister(VR))
2646 MachineInstr *Def = MRI->getVRegDef(VR);
2649 if (!Flags.isByVal()) {
2650 if (!TII->isLoadFromStackSlot(Def, FI))
2653 unsigned Opcode = Def->getOpcode();
2654 if ((Opcode == X86::LEA32r || Opcode == X86::LEA64r) &&
2655 Def->getOperand(1).isFI()) {
2656 FI = Def->getOperand(1).getIndex();
2657 Bytes = Flags.getByValSize();
2661 } else if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Arg)) {
2662 if (Flags.isByVal())
2663 // ByVal argument is passed in as a pointer but it's now being
2664 // dereferenced. e.g.
2665 // define @foo(%struct.X* %A) {
2666 // tail call @bar(%struct.X* byval %A)
2669 SDValue Ptr = Ld->getBasePtr();
2670 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr);
2673 FI = FINode->getIndex();
2674 } else if (Arg.getOpcode() == ISD::FrameIndex && Flags.isByVal()) {
2675 FrameIndexSDNode *FINode = cast<FrameIndexSDNode>(Arg);
2676 FI = FINode->getIndex();
2677 Bytes = Flags.getByValSize();
2681 assert(FI != INT_MAX);
2682 if (!MFI->isFixedObjectIndex(FI))
2684 return Offset == MFI->getObjectOffset(FI) && Bytes == MFI->getObjectSize(FI);
2687 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
2688 /// for tail call optimization. Targets which want to do tail call
2689 /// optimization should implement this function.
2691 X86TargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
2692 CallingConv::ID CalleeCC,
2694 bool isCalleeStructRet,
2695 bool isCallerStructRet,
2696 const SmallVectorImpl<ISD::OutputArg> &Outs,
2697 const SmallVectorImpl<SDValue> &OutVals,
2698 const SmallVectorImpl<ISD::InputArg> &Ins,
2699 SelectionDAG& DAG) const {
2700 if (!IsTailCallConvention(CalleeCC) &&
2701 CalleeCC != CallingConv::C)
2704 // If -tailcallopt is specified, make fastcc functions tail-callable.
2705 const MachineFunction &MF = DAG.getMachineFunction();
2706 const Function *CallerF = DAG.getMachineFunction().getFunction();
2707 CallingConv::ID CallerCC = CallerF->getCallingConv();
2708 bool CCMatch = CallerCC == CalleeCC;
2710 if (getTargetMachine().Options.GuaranteedTailCallOpt) {
2711 if (IsTailCallConvention(CalleeCC) && CCMatch)
2716 // Look for obvious safe cases to perform tail call optimization that do not
2717 // require ABI changes. This is what gcc calls sibcall.
2719 // Can't do sibcall if stack needs to be dynamically re-aligned. PEI needs to
2720 // emit a special epilogue.
2721 if (RegInfo->needsStackRealignment(MF))
2724 // Also avoid sibcall optimization if either caller or callee uses struct
2725 // return semantics.
2726 if (isCalleeStructRet || isCallerStructRet)
2729 // An stdcall caller is expected to clean up its arguments; the callee
2730 // isn't going to do that.
2731 if (!CCMatch && CallerCC==CallingConv::X86_StdCall)
2734 // Do not sibcall optimize vararg calls unless all arguments are passed via
2736 if (isVarArg && !Outs.empty()) {
2738 // Optimizing for varargs on Win64 is unlikely to be safe without
2739 // additional testing.
2740 if (Subtarget->isTargetWin64())
2743 SmallVector<CCValAssign, 16> ArgLocs;
2744 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(),
2745 getTargetMachine(), ArgLocs, *DAG.getContext());
2747 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
2748 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i)
2749 if (!ArgLocs[i].isRegLoc())
2753 // If the call result is in ST0 / ST1, it needs to be popped off the x87
2754 // stack. Therefore, if it's not used by the call it is not safe to optimize
2755 // this into a sibcall.
2756 bool Unused = false;
2757 for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
2764 SmallVector<CCValAssign, 16> RVLocs;
2765 CCState CCInfo(CalleeCC, false, DAG.getMachineFunction(),
2766 getTargetMachine(), RVLocs, *DAG.getContext());
2767 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
2768 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
2769 CCValAssign &VA = RVLocs[i];
2770 if (VA.getLocReg() == X86::ST0 || VA.getLocReg() == X86::ST1)
2775 // If the calling conventions do not match, then we'd better make sure the
2776 // results are returned in the same way as what the caller expects.
2778 SmallVector<CCValAssign, 16> RVLocs1;
2779 CCState CCInfo1(CalleeCC, false, DAG.getMachineFunction(),
2780 getTargetMachine(), RVLocs1, *DAG.getContext());
2781 CCInfo1.AnalyzeCallResult(Ins, RetCC_X86);
2783 SmallVector<CCValAssign, 16> RVLocs2;
2784 CCState CCInfo2(CallerCC, false, DAG.getMachineFunction(),
2785 getTargetMachine(), RVLocs2, *DAG.getContext());
2786 CCInfo2.AnalyzeCallResult(Ins, RetCC_X86);
2788 if (RVLocs1.size() != RVLocs2.size())
2790 for (unsigned i = 0, e = RVLocs1.size(); i != e; ++i) {
2791 if (RVLocs1[i].isRegLoc() != RVLocs2[i].isRegLoc())
2793 if (RVLocs1[i].getLocInfo() != RVLocs2[i].getLocInfo())
2795 if (RVLocs1[i].isRegLoc()) {
2796 if (RVLocs1[i].getLocReg() != RVLocs2[i].getLocReg())
2799 if (RVLocs1[i].getLocMemOffset() != RVLocs2[i].getLocMemOffset())
2805 // If the callee takes no arguments then go on to check the results of the
2807 if (!Outs.empty()) {
2808 // Check if stack adjustment is needed. For now, do not do this if any
2809 // argument is passed on the stack.
2810 SmallVector<CCValAssign, 16> ArgLocs;
2811 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(),
2812 getTargetMachine(), ArgLocs, *DAG.getContext());
2814 // Allocate shadow area for Win64
2815 if (Subtarget->isTargetWin64()) {
2816 CCInfo.AllocateStack(32, 8);
2819 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
2820 if (CCInfo.getNextStackOffset()) {
2821 MachineFunction &MF = DAG.getMachineFunction();
2822 if (MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn())
2825 // Check if the arguments are already laid out in the right way as
2826 // the caller's fixed stack objects.
2827 MachineFrameInfo *MFI = MF.getFrameInfo();
2828 const MachineRegisterInfo *MRI = &MF.getRegInfo();
2829 const X86InstrInfo *TII =
2830 ((X86TargetMachine&)getTargetMachine()).getInstrInfo();
2831 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2832 CCValAssign &VA = ArgLocs[i];
2833 SDValue Arg = OutVals[i];
2834 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2835 if (VA.getLocInfo() == CCValAssign::Indirect)
2837 if (!VA.isRegLoc()) {
2838 if (!MatchingStackOffset(Arg, VA.getLocMemOffset(), Flags,
2845 // If the tailcall address may be in a register, then make sure it's
2846 // possible to register allocate for it. In 32-bit, the call address can
2847 // only target EAX, EDX, or ECX since the tail call must be scheduled after
2848 // callee-saved registers are restored. These happen to be the same
2849 // registers used to pass 'inreg' arguments so watch out for those.
2850 if (!Subtarget->is64Bit() &&
2851 !isa<GlobalAddressSDNode>(Callee) &&
2852 !isa<ExternalSymbolSDNode>(Callee)) {
2853 unsigned NumInRegs = 0;
2854 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2855 CCValAssign &VA = ArgLocs[i];
2858 unsigned Reg = VA.getLocReg();
2861 case X86::EAX: case X86::EDX: case X86::ECX:
2862 if (++NumInRegs == 3)
2874 X86TargetLowering::createFastISel(FunctionLoweringInfo &funcInfo) const {
2875 return X86::createFastISel(funcInfo);
2879 //===----------------------------------------------------------------------===//
2880 // Other Lowering Hooks
2881 //===----------------------------------------------------------------------===//
2883 static bool MayFoldLoad(SDValue Op) {
2884 return Op.hasOneUse() && ISD::isNormalLoad(Op.getNode());
2887 static bool MayFoldIntoStore(SDValue Op) {
2888 return Op.hasOneUse() && ISD::isNormalStore(*Op.getNode()->use_begin());
2891 static bool isTargetShuffle(unsigned Opcode) {
2893 default: return false;
2894 case X86ISD::PSHUFD:
2895 case X86ISD::PSHUFHW:
2896 case X86ISD::PSHUFLW:
2898 case X86ISD::PALIGN:
2899 case X86ISD::MOVLHPS:
2900 case X86ISD::MOVLHPD:
2901 case X86ISD::MOVHLPS:
2902 case X86ISD::MOVLPS:
2903 case X86ISD::MOVLPD:
2904 case X86ISD::MOVSHDUP:
2905 case X86ISD::MOVSLDUP:
2906 case X86ISD::MOVDDUP:
2909 case X86ISD::UNPCKL:
2910 case X86ISD::UNPCKH:
2911 case X86ISD::VPERMILP:
2912 case X86ISD::VPERM2X128:
2917 static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT,
2918 SDValue V1, SelectionDAG &DAG) {
2920 default: llvm_unreachable("Unknown x86 shuffle node");
2921 case X86ISD::MOVSHDUP:
2922 case X86ISD::MOVSLDUP:
2923 case X86ISD::MOVDDUP:
2924 return DAG.getNode(Opc, dl, VT, V1);
2928 static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT,
2929 SDValue V1, unsigned TargetMask,
2930 SelectionDAG &DAG) {
2932 default: llvm_unreachable("Unknown x86 shuffle node");
2933 case X86ISD::PSHUFD:
2934 case X86ISD::PSHUFHW:
2935 case X86ISD::PSHUFLW:
2936 case X86ISD::VPERMILP:
2937 case X86ISD::VPERMI:
2938 return DAG.getNode(Opc, dl, VT, V1, DAG.getConstant(TargetMask, MVT::i8));
2942 static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT,
2943 SDValue V1, SDValue V2, unsigned TargetMask,
2944 SelectionDAG &DAG) {
2946 default: llvm_unreachable("Unknown x86 shuffle node");
2947 case X86ISD::PALIGN:
2949 case X86ISD::VPERM2X128:
2950 return DAG.getNode(Opc, dl, VT, V1, V2,
2951 DAG.getConstant(TargetMask, MVT::i8));
2955 static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT,
2956 SDValue V1, SDValue V2, SelectionDAG &DAG) {
2958 default: llvm_unreachable("Unknown x86 shuffle node");
2959 case X86ISD::MOVLHPS:
2960 case X86ISD::MOVLHPD:
2961 case X86ISD::MOVHLPS:
2962 case X86ISD::MOVLPS:
2963 case X86ISD::MOVLPD:
2966 case X86ISD::UNPCKL:
2967 case X86ISD::UNPCKH:
2968 return DAG.getNode(Opc, dl, VT, V1, V2);
2972 SDValue X86TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) const {
2973 MachineFunction &MF = DAG.getMachineFunction();
2974 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
2975 int ReturnAddrIndex = FuncInfo->getRAIndex();
2977 if (ReturnAddrIndex == 0) {
2978 // Set up a frame object for the return address.
2979 uint64_t SlotSize = TD->getPointerSize();
2980 ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(SlotSize, -SlotSize,
2982 FuncInfo->setRAIndex(ReturnAddrIndex);
2985 return DAG.getFrameIndex(ReturnAddrIndex, getPointerTy());
2989 bool X86::isOffsetSuitableForCodeModel(int64_t Offset, CodeModel::Model M,
2990 bool hasSymbolicDisplacement) {
2991 // Offset should fit into 32 bit immediate field.
2992 if (!isInt<32>(Offset))
2995 // If we don't have a symbolic displacement - we don't have any extra
2997 if (!hasSymbolicDisplacement)
3000 // FIXME: Some tweaks might be needed for medium code model.
3001 if (M != CodeModel::Small && M != CodeModel::Kernel)
3004 // For small code model we assume that latest object is 16MB before end of 31
3005 // bits boundary. We may also accept pretty large negative constants knowing
3006 // that all objects are in the positive half of address space.
3007 if (M == CodeModel::Small && Offset < 16*1024*1024)
3010 // For kernel code model we know that all object resist in the negative half
3011 // of 32bits address space. We may not accept negative offsets, since they may
3012 // be just off and we may accept pretty large positive ones.
3013 if (M == CodeModel::Kernel && Offset > 0)
3019 /// isCalleePop - Determines whether the callee is required to pop its
3020 /// own arguments. Callee pop is necessary to support tail calls.
3021 bool X86::isCalleePop(CallingConv::ID CallingConv,
3022 bool is64Bit, bool IsVarArg, bool TailCallOpt) {
3026 switch (CallingConv) {
3029 case CallingConv::X86_StdCall:
3031 case CallingConv::X86_FastCall:
3033 case CallingConv::X86_ThisCall:
3035 case CallingConv::Fast:
3037 case CallingConv::GHC:
3042 /// TranslateX86CC - do a one to one translation of a ISD::CondCode to the X86
3043 /// specific condition code, returning the condition code and the LHS/RHS of the
3044 /// comparison to make.
3045 static unsigned TranslateX86CC(ISD::CondCode SetCCOpcode, bool isFP,
3046 SDValue &LHS, SDValue &RHS, SelectionDAG &DAG) {
3048 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
3049 if (SetCCOpcode == ISD::SETGT && RHSC->isAllOnesValue()) {
3050 // X > -1 -> X == 0, jump !sign.
3051 RHS = DAG.getConstant(0, RHS.getValueType());
3052 return X86::COND_NS;
3054 if (SetCCOpcode == ISD::SETLT && RHSC->isNullValue()) {
3055 // X < 0 -> X == 0, jump on sign.
3058 if (SetCCOpcode == ISD::SETLT && RHSC->getZExtValue() == 1) {
3060 RHS = DAG.getConstant(0, RHS.getValueType());
3061 return X86::COND_LE;
3065 switch (SetCCOpcode) {
3066 default: llvm_unreachable("Invalid integer condition!");
3067 case ISD::SETEQ: return X86::COND_E;
3068 case ISD::SETGT: return X86::COND_G;
3069 case ISD::SETGE: return X86::COND_GE;
3070 case ISD::SETLT: return X86::COND_L;
3071 case ISD::SETLE: return X86::COND_LE;
3072 case ISD::SETNE: return X86::COND_NE;
3073 case ISD::SETULT: return X86::COND_B;
3074 case ISD::SETUGT: return X86::COND_A;
3075 case ISD::SETULE: return X86::COND_BE;
3076 case ISD::SETUGE: return X86::COND_AE;
3080 // First determine if it is required or is profitable to flip the operands.
3082 // If LHS is a foldable load, but RHS is not, flip the condition.
3083 if (ISD::isNON_EXTLoad(LHS.getNode()) &&
3084 !ISD::isNON_EXTLoad(RHS.getNode())) {
3085 SetCCOpcode = getSetCCSwappedOperands(SetCCOpcode);
3086 std::swap(LHS, RHS);
3089 switch (SetCCOpcode) {
3095 std::swap(LHS, RHS);
3099 // On a floating point condition, the flags are set as follows:
3101 // 0 | 0 | 0 | X > Y
3102 // 0 | 0 | 1 | X < Y
3103 // 1 | 0 | 0 | X == Y
3104 // 1 | 1 | 1 | unordered
3105 switch (SetCCOpcode) {
3106 default: llvm_unreachable("Condcode should be pre-legalized away");
3108 case ISD::SETEQ: return X86::COND_E;
3109 case ISD::SETOLT: // flipped
3111 case ISD::SETGT: return X86::COND_A;
3112 case ISD::SETOLE: // flipped
3114 case ISD::SETGE: return X86::COND_AE;
3115 case ISD::SETUGT: // flipped
3117 case ISD::SETLT: return X86::COND_B;
3118 case ISD::SETUGE: // flipped
3120 case ISD::SETLE: return X86::COND_BE;
3122 case ISD::SETNE: return X86::COND_NE;
3123 case ISD::SETUO: return X86::COND_P;
3124 case ISD::SETO: return X86::COND_NP;
3126 case ISD::SETUNE: return X86::COND_INVALID;
3130 /// hasFPCMov - is there a floating point cmov for the specific X86 condition
3131 /// code. Current x86 isa includes the following FP cmov instructions:
3132 /// fcmovb, fcomvbe, fcomve, fcmovu, fcmovae, fcmova, fcmovne, fcmovnu.
3133 static bool hasFPCMov(unsigned X86CC) {
3149 /// isFPImmLegal - Returns true if the target can instruction select the
3150 /// specified FP immediate natively. If false, the legalizer will
3151 /// materialize the FP immediate as a load from a constant pool.
3152 bool X86TargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
3153 for (unsigned i = 0, e = LegalFPImmediates.size(); i != e; ++i) {
3154 if (Imm.bitwiseIsEqual(LegalFPImmediates[i]))
3160 /// isUndefOrInRange - Return true if Val is undef or if its value falls within
3161 /// the specified range (L, H].
3162 static bool isUndefOrInRange(int Val, int Low, int Hi) {
3163 return (Val < 0) || (Val >= Low && Val < Hi);
3166 /// isUndefOrEqual - Val is either less than zero (undef) or equal to the
3167 /// specified value.
3168 static bool isUndefOrEqual(int Val, int CmpVal) {
3169 if (Val < 0 || Val == CmpVal)
3174 /// isSequentialOrUndefInRange - Return true if every element in Mask, begining
3175 /// from position Pos and ending in Pos+Size, falls within the specified
3176 /// sequential range (L, L+Pos]. or is undef.
3177 static bool isSequentialOrUndefInRange(ArrayRef<int> Mask,
3178 int Pos, int Size, int Low) {
3179 for (int i = Pos, e = Pos+Size; i != e; ++i, ++Low)
3180 if (!isUndefOrEqual(Mask[i], Low))
3185 /// isPSHUFDMask - Return true if the node specifies a shuffle of elements that
3186 /// is suitable for input to PSHUFD or PSHUFW. That is, it doesn't reference
3187 /// the second operand.
3188 static bool isPSHUFDMask(ArrayRef<int> Mask, EVT VT) {
3189 if (VT == MVT::v4f32 || VT == MVT::v4i32 )
3190 return (Mask[0] < 4 && Mask[1] < 4 && Mask[2] < 4 && Mask[3] < 4);
3191 if (VT == MVT::v2f64 || VT == MVT::v2i64)
3192 return (Mask[0] < 2 && Mask[1] < 2);
3196 /// isPSHUFHWMask - Return true if the node specifies a shuffle of elements that
3197 /// is suitable for input to PSHUFHW.
3198 static bool isPSHUFHWMask(ArrayRef<int> Mask, EVT VT) {
3199 if (VT != MVT::v8i16)
3202 // Lower quadword copied in order or undef.
3203 if (!isSequentialOrUndefInRange(Mask, 0, 4, 0))
3206 // Upper quadword shuffled.
3207 for (unsigned i = 4; i != 8; ++i)
3208 if (Mask[i] >= 0 && (Mask[i] < 4 || Mask[i] > 7))
3214 /// isPSHUFLWMask - Return true if the node specifies a shuffle of elements that
3215 /// is suitable for input to PSHUFLW.
3216 static bool isPSHUFLWMask(ArrayRef<int> Mask, EVT VT) {
3217 if (VT != MVT::v8i16)
3220 // Upper quadword copied in order.
3221 if (!isSequentialOrUndefInRange(Mask, 4, 4, 4))
3224 // Lower quadword shuffled.
3225 for (unsigned i = 0; i != 4; ++i)
3232 /// isPALIGNRMask - Return true if the node specifies a shuffle of elements that
3233 /// is suitable for input to PALIGNR.
3234 static bool isPALIGNRMask(ArrayRef<int> Mask, EVT VT,
3235 const X86Subtarget *Subtarget) {
3236 if ((VT.getSizeInBits() == 128 && !Subtarget->hasSSSE3()) ||
3237 (VT.getSizeInBits() == 256 && !Subtarget->hasAVX2()))
3240 unsigned NumElts = VT.getVectorNumElements();
3241 unsigned NumLanes = VT.getSizeInBits()/128;
3242 unsigned NumLaneElts = NumElts/NumLanes;
3244 // Do not handle 64-bit element shuffles with palignr.
3245 if (NumLaneElts == 2)
3248 for (unsigned l = 0; l != NumElts; l+=NumLaneElts) {
3250 for (i = 0; i != NumLaneElts; ++i) {
3255 // Lane is all undef, go to next lane
3256 if (i == NumLaneElts)
3259 int Start = Mask[i+l];
3261 // Make sure its in this lane in one of the sources
3262 if (!isUndefOrInRange(Start, l, l+NumLaneElts) &&
3263 !isUndefOrInRange(Start, l+NumElts, l+NumElts+NumLaneElts))
3266 // If not lane 0, then we must match lane 0
3267 if (l != 0 && Mask[i] >= 0 && !isUndefOrEqual(Start, Mask[i]+l))
3270 // Correct second source to be contiguous with first source
3271 if (Start >= (int)NumElts)
3272 Start -= NumElts - NumLaneElts;
3274 // Make sure we're shifting in the right direction.
3275 if (Start <= (int)(i+l))
3280 // Check the rest of the elements to see if they are consecutive.
3281 for (++i; i != NumLaneElts; ++i) {
3282 int Idx = Mask[i+l];
3284 // Make sure its in this lane
3285 if (!isUndefOrInRange(Idx, l, l+NumLaneElts) &&
3286 !isUndefOrInRange(Idx, l+NumElts, l+NumElts+NumLaneElts))
3289 // If not lane 0, then we must match lane 0
3290 if (l != 0 && Mask[i] >= 0 && !isUndefOrEqual(Idx, Mask[i]+l))
3293 if (Idx >= (int)NumElts)
3294 Idx -= NumElts - NumLaneElts;
3296 if (!isUndefOrEqual(Idx, Start+i))
3305 /// CommuteVectorShuffleMask - Change values in a shuffle permute mask assuming
3306 /// the two vector operands have swapped position.
3307 static void CommuteVectorShuffleMask(SmallVectorImpl<int> &Mask,
3308 unsigned NumElems) {
3309 for (unsigned i = 0; i != NumElems; ++i) {
3313 else if (idx < (int)NumElems)
3314 Mask[i] = idx + NumElems;
3316 Mask[i] = idx - NumElems;
3320 /// isSHUFPMask - Return true if the specified VECTOR_SHUFFLE operand
3321 /// specifies a shuffle of elements that is suitable for input to 128/256-bit
3322 /// SHUFPS and SHUFPD. If Commuted is true, then it checks for sources to be
3323 /// reverse of what x86 shuffles want.
3324 static bool isSHUFPMask(ArrayRef<int> Mask, EVT VT, bool HasAVX,
3325 bool Commuted = false) {
3326 if (!HasAVX && VT.getSizeInBits() == 256)
3329 unsigned NumElems = VT.getVectorNumElements();
3330 unsigned NumLanes = VT.getSizeInBits()/128;
3331 unsigned NumLaneElems = NumElems/NumLanes;
3333 if (NumLaneElems != 2 && NumLaneElems != 4)
3336 // VSHUFPSY divides the resulting vector into 4 chunks.
3337 // The sources are also splitted into 4 chunks, and each destination
3338 // chunk must come from a different source chunk.
3340 // SRC1 => X7 X6 X5 X4 X3 X2 X1 X0
3341 // SRC2 => Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y9
3343 // DST => Y7..Y4, Y7..Y4, X7..X4, X7..X4,
3344 // Y3..Y0, Y3..Y0, X3..X0, X3..X0
3346 // VSHUFPDY divides the resulting vector into 4 chunks.
3347 // The sources are also splitted into 4 chunks, and each destination
3348 // chunk must come from a different source chunk.
3350 // SRC1 => X3 X2 X1 X0
3351 // SRC2 => Y3 Y2 Y1 Y0
3353 // DST => Y3..Y2, X3..X2, Y1..Y0, X1..X0
3355 unsigned HalfLaneElems = NumLaneElems/2;
3356 for (unsigned l = 0; l != NumElems; l += NumLaneElems) {
3357 for (unsigned i = 0; i != NumLaneElems; ++i) {
3358 int Idx = Mask[i+l];
3359 unsigned RngStart = l + ((Commuted == (i<HalfLaneElems)) ? NumElems : 0);
3360 if (!isUndefOrInRange(Idx, RngStart, RngStart+NumLaneElems))
3362 // For VSHUFPSY, the mask of the second half must be the same as the
3363 // first but with the appropriate offsets. This works in the same way as
3364 // VPERMILPS works with masks.
3365 if (NumElems != 8 || l == 0 || Mask[i] < 0)
3367 if (!isUndefOrEqual(Idx, Mask[i]+l))
3375 /// isMOVHLPSMask - Return true if the specified VECTOR_SHUFFLE operand
3376 /// specifies a shuffle of elements that is suitable for input to MOVHLPS.
3377 static bool isMOVHLPSMask(ArrayRef<int> Mask, EVT VT) {
3378 unsigned NumElems = VT.getVectorNumElements();
3380 if (VT.getSizeInBits() != 128)
3386 // Expect bit0 == 6, bit1 == 7, bit2 == 2, bit3 == 3
3387 return isUndefOrEqual(Mask[0], 6) &&
3388 isUndefOrEqual(Mask[1], 7) &&
3389 isUndefOrEqual(Mask[2], 2) &&
3390 isUndefOrEqual(Mask[3], 3);
3393 /// isMOVHLPS_v_undef_Mask - Special case of isMOVHLPSMask for canonical form
3394 /// of vector_shuffle v, v, <2, 3, 2, 3>, i.e. vector_shuffle v, undef,
3396 static bool isMOVHLPS_v_undef_Mask(ArrayRef<int> Mask, EVT VT) {
3397 unsigned NumElems = VT.getVectorNumElements();
3399 if (VT.getSizeInBits() != 128)
3405 return isUndefOrEqual(Mask[0], 2) &&
3406 isUndefOrEqual(Mask[1], 3) &&
3407 isUndefOrEqual(Mask[2], 2) &&
3408 isUndefOrEqual(Mask[3], 3);
3411 /// isMOVLPMask - Return true if the specified VECTOR_SHUFFLE operand
3412 /// specifies a shuffle of elements that is suitable for input to MOVLP{S|D}.
3413 static bool isMOVLPMask(ArrayRef<int> Mask, EVT VT) {
3414 if (VT.getSizeInBits() != 128)
3417 unsigned NumElems = VT.getVectorNumElements();
3419 if (NumElems != 2 && NumElems != 4)
3422 for (unsigned i = 0; i != NumElems/2; ++i)
3423 if (!isUndefOrEqual(Mask[i], i + NumElems))
3426 for (unsigned i = NumElems/2; i != NumElems; ++i)
3427 if (!isUndefOrEqual(Mask[i], i))
3433 /// isMOVLHPSMask - Return true if the specified VECTOR_SHUFFLE operand
3434 /// specifies a shuffle of elements that is suitable for input to MOVLHPS.
3435 static bool isMOVLHPSMask(ArrayRef<int> Mask, EVT VT) {
3436 unsigned NumElems = VT.getVectorNumElements();
3438 if ((NumElems != 2 && NumElems != 4)
3439 || VT.getSizeInBits() > 128)
3442 for (unsigned i = 0; i != NumElems/2; ++i)
3443 if (!isUndefOrEqual(Mask[i], i))
3446 for (unsigned i = 0; i != NumElems/2; ++i)
3447 if (!isUndefOrEqual(Mask[i + NumElems/2], i + NumElems))
3453 /// isUNPCKLMask - Return true if the specified VECTOR_SHUFFLE operand
3454 /// specifies a shuffle of elements that is suitable for input to UNPCKL.
3455 static bool isUNPCKLMask(ArrayRef<int> Mask, EVT VT,
3456 bool HasAVX2, bool V2IsSplat = false) {
3457 unsigned NumElts = VT.getVectorNumElements();
3459 assert((VT.is128BitVector() || VT.is256BitVector()) &&
3460 "Unsupported vector type for unpckh");
3462 if (VT.getSizeInBits() == 256 && NumElts != 4 && NumElts != 8 &&
3463 (!HasAVX2 || (NumElts != 16 && NumElts != 32)))
3466 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
3467 // independently on 128-bit lanes.
3468 unsigned NumLanes = VT.getSizeInBits()/128;
3469 unsigned NumLaneElts = NumElts/NumLanes;
3471 for (unsigned l = 0; l != NumLanes; ++l) {
3472 for (unsigned i = l*NumLaneElts, j = l*NumLaneElts;
3473 i != (l+1)*NumLaneElts;
3476 int BitI1 = Mask[i+1];
3477 if (!isUndefOrEqual(BitI, j))
3480 if (!isUndefOrEqual(BitI1, NumElts))
3483 if (!isUndefOrEqual(BitI1, j + NumElts))
3492 /// isUNPCKHMask - Return true if the specified VECTOR_SHUFFLE operand
3493 /// specifies a shuffle of elements that is suitable for input to UNPCKH.
3494 static bool isUNPCKHMask(ArrayRef<int> Mask, EVT VT,
3495 bool HasAVX2, bool V2IsSplat = false) {
3496 unsigned NumElts = VT.getVectorNumElements();
3498 assert((VT.is128BitVector() || VT.is256BitVector()) &&
3499 "Unsupported vector type for unpckh");
3501 if (VT.getSizeInBits() == 256 && NumElts != 4 && NumElts != 8 &&
3502 (!HasAVX2 || (NumElts != 16 && NumElts != 32)))
3505 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
3506 // independently on 128-bit lanes.
3507 unsigned NumLanes = VT.getSizeInBits()/128;
3508 unsigned NumLaneElts = NumElts/NumLanes;
3510 for (unsigned l = 0; l != NumLanes; ++l) {
3511 for (unsigned i = l*NumLaneElts, j = (l*NumLaneElts)+NumLaneElts/2;
3512 i != (l+1)*NumLaneElts; i += 2, ++j) {
3514 int BitI1 = Mask[i+1];
3515 if (!isUndefOrEqual(BitI, j))
3518 if (isUndefOrEqual(BitI1, NumElts))
3521 if (!isUndefOrEqual(BitI1, j+NumElts))
3529 /// isUNPCKL_v_undef_Mask - Special case of isUNPCKLMask for canonical form
3530 /// of vector_shuffle v, v, <0, 4, 1, 5>, i.e. vector_shuffle v, undef,
3532 static bool isUNPCKL_v_undef_Mask(ArrayRef<int> Mask, EVT VT,
3534 unsigned NumElts = VT.getVectorNumElements();
3536 assert((VT.is128BitVector() || VT.is256BitVector()) &&
3537 "Unsupported vector type for unpckh");
3539 if (VT.getSizeInBits() == 256 && NumElts != 4 && NumElts != 8 &&
3540 (!HasAVX2 || (NumElts != 16 && NumElts != 32)))
3543 // For 256-bit i64/f64, use MOVDDUPY instead, so reject the matching pattern
3544 // FIXME: Need a better way to get rid of this, there's no latency difference
3545 // between UNPCKLPD and MOVDDUP, the later should always be checked first and
3546 // the former later. We should also remove the "_undef" special mask.
3547 if (NumElts == 4 && VT.getSizeInBits() == 256)
3550 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
3551 // independently on 128-bit lanes.
3552 unsigned NumLanes = VT.getSizeInBits()/128;
3553 unsigned NumLaneElts = NumElts/NumLanes;
3555 for (unsigned l = 0; l != NumLanes; ++l) {
3556 for (unsigned i = l*NumLaneElts, j = l*NumLaneElts;
3557 i != (l+1)*NumLaneElts;
3560 int BitI1 = Mask[i+1];
3562 if (!isUndefOrEqual(BitI, j))
3564 if (!isUndefOrEqual(BitI1, j))
3572 /// isUNPCKH_v_undef_Mask - Special case of isUNPCKHMask for canonical form
3573 /// of vector_shuffle v, v, <2, 6, 3, 7>, i.e. vector_shuffle v, undef,
3575 static bool isUNPCKH_v_undef_Mask(ArrayRef<int> Mask, EVT VT, bool HasAVX2) {
3576 unsigned NumElts = VT.getVectorNumElements();
3578 assert((VT.is128BitVector() || VT.is256BitVector()) &&
3579 "Unsupported vector type for unpckh");
3581 if (VT.getSizeInBits() == 256 && NumElts != 4 && NumElts != 8 &&
3582 (!HasAVX2 || (NumElts != 16 && NumElts != 32)))
3585 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
3586 // independently on 128-bit lanes.
3587 unsigned NumLanes = VT.getSizeInBits()/128;
3588 unsigned NumLaneElts = NumElts/NumLanes;
3590 for (unsigned l = 0; l != NumLanes; ++l) {
3591 for (unsigned i = l*NumLaneElts, j = (l*NumLaneElts)+NumLaneElts/2;
3592 i != (l+1)*NumLaneElts; i += 2, ++j) {
3594 int BitI1 = Mask[i+1];
3595 if (!isUndefOrEqual(BitI, j))
3597 if (!isUndefOrEqual(BitI1, j))
3604 /// isMOVLMask - Return true if the specified VECTOR_SHUFFLE operand
3605 /// specifies a shuffle of elements that is suitable for input to MOVSS,
3606 /// MOVSD, and MOVD, i.e. setting the lowest element.
3607 static bool isMOVLMask(ArrayRef<int> Mask, EVT VT) {
3608 if (VT.getVectorElementType().getSizeInBits() < 32)
3610 if (VT.getSizeInBits() == 256)
3613 unsigned NumElts = VT.getVectorNumElements();
3615 if (!isUndefOrEqual(Mask[0], NumElts))
3618 for (unsigned i = 1; i != NumElts; ++i)
3619 if (!isUndefOrEqual(Mask[i], i))
3625 /// isVPERM2X128Mask - Match 256-bit shuffles where the elements are considered
3626 /// as permutations between 128-bit chunks or halves. As an example: this
3628 /// vector_shuffle <4, 5, 6, 7, 12, 13, 14, 15>
3629 /// The first half comes from the second half of V1 and the second half from the
3630 /// the second half of V2.
3631 static bool isVPERM2X128Mask(ArrayRef<int> Mask, EVT VT, bool HasAVX) {
3632 if (!HasAVX || VT.getSizeInBits() != 256)
3635 // The shuffle result is divided into half A and half B. In total the two
3636 // sources have 4 halves, namely: C, D, E, F. The final values of A and
3637 // B must come from C, D, E or F.
3638 unsigned HalfSize = VT.getVectorNumElements()/2;
3639 bool MatchA = false, MatchB = false;
3641 // Check if A comes from one of C, D, E, F.
3642 for (unsigned Half = 0; Half != 4; ++Half) {
3643 if (isSequentialOrUndefInRange(Mask, 0, HalfSize, Half*HalfSize)) {
3649 // Check if B comes from one of C, D, E, F.
3650 for (unsigned Half = 0; Half != 4; ++Half) {
3651 if (isSequentialOrUndefInRange(Mask, HalfSize, HalfSize, Half*HalfSize)) {
3657 return MatchA && MatchB;
3660 /// getShuffleVPERM2X128Immediate - Return the appropriate immediate to shuffle
3661 /// the specified VECTOR_MASK mask with VPERM2F128/VPERM2I128 instructions.
3662 static unsigned getShuffleVPERM2X128Immediate(ShuffleVectorSDNode *SVOp) {
3663 EVT VT = SVOp->getValueType(0);
3665 unsigned HalfSize = VT.getVectorNumElements()/2;
3667 unsigned FstHalf = 0, SndHalf = 0;
3668 for (unsigned i = 0; i < HalfSize; ++i) {
3669 if (SVOp->getMaskElt(i) > 0) {
3670 FstHalf = SVOp->getMaskElt(i)/HalfSize;
3674 for (unsigned i = HalfSize; i < HalfSize*2; ++i) {
3675 if (SVOp->getMaskElt(i) > 0) {
3676 SndHalf = SVOp->getMaskElt(i)/HalfSize;
3681 return (FstHalf | (SndHalf << 4));
3684 /// isVPERMILPMask - Return true if the specified VECTOR_SHUFFLE operand
3685 /// specifies a shuffle of elements that is suitable for input to VPERMILPD*.
3686 /// Note that VPERMIL mask matching is different depending whether theunderlying
3687 /// type is 32 or 64. In the VPERMILPS the high half of the mask should point
3688 /// to the same elements of the low, but to the higher half of the source.
3689 /// In VPERMILPD the two lanes could be shuffled independently of each other
3690 /// with the same restriction that lanes can't be crossed. Also handles PSHUFDY.
3691 static bool isVPERMILPMask(ArrayRef<int> Mask, EVT VT, bool HasAVX) {
3695 unsigned NumElts = VT.getVectorNumElements();
3696 // Only match 256-bit with 32/64-bit types
3697 if (VT.getSizeInBits() != 256 || (NumElts != 4 && NumElts != 8))
3700 unsigned NumLanes = VT.getSizeInBits()/128;
3701 unsigned LaneSize = NumElts/NumLanes;
3702 for (unsigned l = 0; l != NumElts; l += LaneSize) {
3703 for (unsigned i = 0; i != LaneSize; ++i) {
3704 if (!isUndefOrInRange(Mask[i+l], l, l+LaneSize))
3706 if (NumElts != 8 || l == 0)
3708 // VPERMILPS handling
3711 if (!isUndefOrEqual(Mask[i+l], Mask[i]+l))
3719 /// isCommutedMOVLMask - Returns true if the shuffle mask is except the reverse
3720 /// of what x86 movss want. X86 movs requires the lowest element to be lowest
3721 /// element of vector 2 and the other elements to come from vector 1 in order.
3722 static bool isCommutedMOVLMask(ArrayRef<int> Mask, EVT VT,
3723 bool V2IsSplat = false, bool V2IsUndef = false) {
3724 unsigned NumOps = VT.getVectorNumElements();
3725 if (VT.getSizeInBits() == 256)
3727 if (NumOps != 2 && NumOps != 4 && NumOps != 8 && NumOps != 16)
3730 if (!isUndefOrEqual(Mask[0], 0))
3733 for (unsigned i = 1; i != NumOps; ++i)
3734 if (!(isUndefOrEqual(Mask[i], i+NumOps) ||
3735 (V2IsUndef && isUndefOrInRange(Mask[i], NumOps, NumOps*2)) ||
3736 (V2IsSplat && isUndefOrEqual(Mask[i], NumOps))))
3742 /// isMOVSHDUPMask - Return true if the specified VECTOR_SHUFFLE operand
3743 /// specifies a shuffle of elements that is suitable for input to MOVSHDUP.
3744 /// Masks to match: <1, 1, 3, 3> or <1, 1, 3, 3, 5, 5, 7, 7>
3745 static bool isMOVSHDUPMask(ArrayRef<int> Mask, EVT VT,
3746 const X86Subtarget *Subtarget) {
3747 if (!Subtarget->hasSSE3())
3750 unsigned NumElems = VT.getVectorNumElements();
3752 if ((VT.getSizeInBits() == 128 && NumElems != 4) ||
3753 (VT.getSizeInBits() == 256 && NumElems != 8))
3756 // "i+1" is the value the indexed mask element must have
3757 for (unsigned i = 0; i != NumElems; i += 2)
3758 if (!isUndefOrEqual(Mask[i], i+1) ||
3759 !isUndefOrEqual(Mask[i+1], i+1))
3765 /// isMOVSLDUPMask - Return true if the specified VECTOR_SHUFFLE operand
3766 /// specifies a shuffle of elements that is suitable for input to MOVSLDUP.
3767 /// Masks to match: <0, 0, 2, 2> or <0, 0, 2, 2, 4, 4, 6, 6>
3768 static bool isMOVSLDUPMask(ArrayRef<int> Mask, EVT VT,
3769 const X86Subtarget *Subtarget) {
3770 if (!Subtarget->hasSSE3())
3773 unsigned NumElems = VT.getVectorNumElements();
3775 if ((VT.getSizeInBits() == 128 && NumElems != 4) ||
3776 (VT.getSizeInBits() == 256 && NumElems != 8))
3779 // "i" is the value the indexed mask element must have
3780 for (unsigned i = 0; i != NumElems; i += 2)
3781 if (!isUndefOrEqual(Mask[i], i) ||
3782 !isUndefOrEqual(Mask[i+1], i))
3788 /// isMOVDDUPYMask - Return true if the specified VECTOR_SHUFFLE operand
3789 /// specifies a shuffle of elements that is suitable for input to 256-bit
3790 /// version of MOVDDUP.
3791 static bool isMOVDDUPYMask(ArrayRef<int> Mask, EVT VT, bool HasAVX) {
3792 unsigned NumElts = VT.getVectorNumElements();
3794 if (!HasAVX || VT.getSizeInBits() != 256 || NumElts != 4)
3797 for (unsigned i = 0; i != NumElts/2; ++i)
3798 if (!isUndefOrEqual(Mask[i], 0))
3800 for (unsigned i = NumElts/2; i != NumElts; ++i)
3801 if (!isUndefOrEqual(Mask[i], NumElts/2))
3806 /// isMOVDDUPMask - Return true if the specified VECTOR_SHUFFLE operand
3807 /// specifies a shuffle of elements that is suitable for input to 128-bit
3808 /// version of MOVDDUP.
3809 static bool isMOVDDUPMask(ArrayRef<int> Mask, EVT VT) {
3810 if (VT.getSizeInBits() != 128)
3813 unsigned e = VT.getVectorNumElements() / 2;
3814 for (unsigned i = 0; i != e; ++i)
3815 if (!isUndefOrEqual(Mask[i], i))
3817 for (unsigned i = 0; i != e; ++i)
3818 if (!isUndefOrEqual(Mask[e+i], i))
3823 /// isVEXTRACTF128Index - Return true if the specified
3824 /// EXTRACT_SUBVECTOR operand specifies a vector extract that is
3825 /// suitable for input to VEXTRACTF128.
3826 bool X86::isVEXTRACTF128Index(SDNode *N) {
3827 if (!isa<ConstantSDNode>(N->getOperand(1).getNode()))
3830 // The index should be aligned on a 128-bit boundary.
3832 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
3834 unsigned VL = N->getValueType(0).getVectorNumElements();
3835 unsigned VBits = N->getValueType(0).getSizeInBits();
3836 unsigned ElSize = VBits / VL;
3837 bool Result = (Index * ElSize) % 128 == 0;
3842 /// isVINSERTF128Index - Return true if the specified INSERT_SUBVECTOR
3843 /// operand specifies a subvector insert that is suitable for input to
3845 bool X86::isVINSERTF128Index(SDNode *N) {
3846 if (!isa<ConstantSDNode>(N->getOperand(2).getNode()))
3849 // The index should be aligned on a 128-bit boundary.
3851 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
3853 unsigned VL = N->getValueType(0).getVectorNumElements();
3854 unsigned VBits = N->getValueType(0).getSizeInBits();
3855 unsigned ElSize = VBits / VL;
3856 bool Result = (Index * ElSize) % 128 == 0;
3861 /// getShuffleSHUFImmediate - Return the appropriate immediate to shuffle
3862 /// the specified VECTOR_SHUFFLE mask with PSHUF* and SHUFP* instructions.
3863 /// Handles 128-bit and 256-bit.
3864 static unsigned getShuffleSHUFImmediate(ShuffleVectorSDNode *N) {
3865 EVT VT = N->getValueType(0);
3867 assert((VT.is128BitVector() || VT.is256BitVector()) &&
3868 "Unsupported vector type for PSHUF/SHUFP");
3870 // Handle 128 and 256-bit vector lengths. AVX defines PSHUF/SHUFP to operate
3871 // independently on 128-bit lanes.
3872 unsigned NumElts = VT.getVectorNumElements();
3873 unsigned NumLanes = VT.getSizeInBits()/128;
3874 unsigned NumLaneElts = NumElts/NumLanes;
3876 assert((NumLaneElts == 2 || NumLaneElts == 4) &&
3877 "Only supports 2 or 4 elements per lane");
3879 unsigned Shift = (NumLaneElts == 4) ? 1 : 0;
3881 for (unsigned i = 0; i != NumElts; ++i) {
3882 int Elt = N->getMaskElt(i);
3883 if (Elt < 0) continue;
3885 unsigned ShAmt = i << Shift;
3886 if (ShAmt >= 8) ShAmt -= 8;
3887 Mask |= Elt << ShAmt;
3893 /// getShufflePSHUFHWImmediate - Return the appropriate immediate to shuffle
3894 /// the specified VECTOR_SHUFFLE mask with the PSHUFHW instruction.
3895 static unsigned getShufflePSHUFHWImmediate(ShuffleVectorSDNode *N) {
3897 // 8 nodes, but we only care about the last 4.
3898 for (unsigned i = 7; i >= 4; --i) {
3899 int Val = N->getMaskElt(i);
3908 /// getShufflePSHUFLWImmediate - Return the appropriate immediate to shuffle
3909 /// the specified VECTOR_SHUFFLE mask with the PSHUFLW instruction.
3910 static unsigned getShufflePSHUFLWImmediate(ShuffleVectorSDNode *N) {
3912 // 8 nodes, but we only care about the first 4.
3913 for (int i = 3; i >= 0; --i) {
3914 int Val = N->getMaskElt(i);
3923 /// getShufflePALIGNRImmediate - Return the appropriate immediate to shuffle
3924 /// the specified VECTOR_SHUFFLE mask with the PALIGNR instruction.
3925 static unsigned getShufflePALIGNRImmediate(ShuffleVectorSDNode *SVOp) {
3926 EVT VT = SVOp->getValueType(0);
3927 unsigned EltSize = VT.getVectorElementType().getSizeInBits() >> 3;
3929 unsigned NumElts = VT.getVectorNumElements();
3930 unsigned NumLanes = VT.getSizeInBits()/128;
3931 unsigned NumLaneElts = NumElts/NumLanes;
3935 for (i = 0; i != NumElts; ++i) {
3936 Val = SVOp->getMaskElt(i);
3940 if (Val >= (int)NumElts)
3941 Val -= NumElts - NumLaneElts;
3943 assert(Val - i > 0 && "PALIGNR imm should be positive");
3944 return (Val - i) * EltSize;
3947 /// getExtractVEXTRACTF128Immediate - Return the appropriate immediate
3948 /// to extract the specified EXTRACT_SUBVECTOR index with VEXTRACTF128
3950 unsigned X86::getExtractVEXTRACTF128Immediate(SDNode *N) {
3951 if (!isa<ConstantSDNode>(N->getOperand(1).getNode()))
3952 llvm_unreachable("Illegal extract subvector for VEXTRACTF128");
3955 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
3957 EVT VecVT = N->getOperand(0).getValueType();
3958 EVT ElVT = VecVT.getVectorElementType();
3960 unsigned NumElemsPerChunk = 128 / ElVT.getSizeInBits();
3961 return Index / NumElemsPerChunk;
3964 /// getInsertVINSERTF128Immediate - Return the appropriate immediate
3965 /// to insert at the specified INSERT_SUBVECTOR index with VINSERTF128
3967 unsigned X86::getInsertVINSERTF128Immediate(SDNode *N) {
3968 if (!isa<ConstantSDNode>(N->getOperand(2).getNode()))
3969 llvm_unreachable("Illegal insert subvector for VINSERTF128");
3972 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
3974 EVT VecVT = N->getValueType(0);
3975 EVT ElVT = VecVT.getVectorElementType();
3977 unsigned NumElemsPerChunk = 128 / ElVT.getSizeInBits();
3978 return Index / NumElemsPerChunk;
3981 /// getShuffleCLImmediate - Return the appropriate immediate to shuffle
3982 /// the specified VECTOR_SHUFFLE mask with VPERMQ and VPERMPD instructions.
3983 /// Handles 256-bit.
3984 static unsigned getShuffleCLImmediate(ShuffleVectorSDNode *N) {
3985 EVT VT = N->getValueType(0);
3987 unsigned NumElts = VT.getVectorNumElements();
3989 assert((VT.is256BitVector() && NumElts == 4) &&
3990 "Unsupported vector type for VPERMQ/VPERMPD");
3993 for (unsigned i = 0; i != NumElts; ++i) {
3994 int Elt = N->getMaskElt(i);
3997 Mask |= Elt << (i*2);
4002 /// isZeroNode - Returns true if Elt is a constant zero or a floating point
4004 bool X86::isZeroNode(SDValue Elt) {
4005 return ((isa<ConstantSDNode>(Elt) &&
4006 cast<ConstantSDNode>(Elt)->isNullValue()) ||
4007 (isa<ConstantFPSDNode>(Elt) &&
4008 cast<ConstantFPSDNode>(Elt)->getValueAPF().isPosZero()));
4011 /// CommuteVectorShuffle - Swap vector_shuffle operands as well as values in
4012 /// their permute mask.
4013 static SDValue CommuteVectorShuffle(ShuffleVectorSDNode *SVOp,
4014 SelectionDAG &DAG) {
4015 EVT VT = SVOp->getValueType(0);
4016 unsigned NumElems = VT.getVectorNumElements();
4017 SmallVector<int, 8> MaskVec;
4019 for (unsigned i = 0; i != NumElems; ++i) {
4020 int idx = SVOp->getMaskElt(i);
4022 MaskVec.push_back(idx);
4023 else if (idx < (int)NumElems)
4024 MaskVec.push_back(idx + NumElems);
4026 MaskVec.push_back(idx - NumElems);
4028 return DAG.getVectorShuffle(VT, SVOp->getDebugLoc(), SVOp->getOperand(1),
4029 SVOp->getOperand(0), &MaskVec[0]);
4032 /// ShouldXformToMOVHLPS - Return true if the node should be transformed to
4033 /// match movhlps. The lower half elements should come from upper half of
4034 /// V1 (and in order), and the upper half elements should come from the upper
4035 /// half of V2 (and in order).
4036 static bool ShouldXformToMOVHLPS(ArrayRef<int> Mask, EVT VT) {
4037 if (VT.getSizeInBits() != 128)
4039 if (VT.getVectorNumElements() != 4)
4041 for (unsigned i = 0, e = 2; i != e; ++i)
4042 if (!isUndefOrEqual(Mask[i], i+2))
4044 for (unsigned i = 2; i != 4; ++i)
4045 if (!isUndefOrEqual(Mask[i], i+4))
4050 /// isScalarLoadToVector - Returns true if the node is a scalar load that
4051 /// is promoted to a vector. It also returns the LoadSDNode by reference if
4053 static bool isScalarLoadToVector(SDNode *N, LoadSDNode **LD = NULL) {
4054 if (N->getOpcode() != ISD::SCALAR_TO_VECTOR)
4056 N = N->getOperand(0).getNode();
4057 if (!ISD::isNON_EXTLoad(N))
4060 *LD = cast<LoadSDNode>(N);
4064 // Test whether the given value is a vector value which will be legalized
4066 static bool WillBeConstantPoolLoad(SDNode *N) {
4067 if (N->getOpcode() != ISD::BUILD_VECTOR)
4070 // Check for any non-constant elements.
4071 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
4072 switch (N->getOperand(i).getNode()->getOpcode()) {
4074 case ISD::ConstantFP:
4081 // Vectors of all-zeros and all-ones are materialized with special
4082 // instructions rather than being loaded.
4083 return !ISD::isBuildVectorAllZeros(N) &&
4084 !ISD::isBuildVectorAllOnes(N);
4087 /// ShouldXformToMOVLP{S|D} - Return true if the node should be transformed to
4088 /// match movlp{s|d}. The lower half elements should come from lower half of
4089 /// V1 (and in order), and the upper half elements should come from the upper
4090 /// half of V2 (and in order). And since V1 will become the source of the
4091 /// MOVLP, it must be either a vector load or a scalar load to vector.
4092 static bool ShouldXformToMOVLP(SDNode *V1, SDNode *V2,
4093 ArrayRef<int> Mask, EVT VT) {
4094 if (VT.getSizeInBits() != 128)
4097 if (!ISD::isNON_EXTLoad(V1) && !isScalarLoadToVector(V1))
4099 // Is V2 is a vector load, don't do this transformation. We will try to use
4100 // load folding shufps op.
4101 if (ISD::isNON_EXTLoad(V2) || WillBeConstantPoolLoad(V2))
4104 unsigned NumElems = VT.getVectorNumElements();
4106 if (NumElems != 2 && NumElems != 4)
4108 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
4109 if (!isUndefOrEqual(Mask[i], i))
4111 for (unsigned i = NumElems/2; i != NumElems; ++i)
4112 if (!isUndefOrEqual(Mask[i], i+NumElems))
4117 /// isSplatVector - Returns true if N is a BUILD_VECTOR node whose elements are
4119 static bool isSplatVector(SDNode *N) {
4120 if (N->getOpcode() != ISD::BUILD_VECTOR)
4123 SDValue SplatValue = N->getOperand(0);
4124 for (unsigned i = 1, e = N->getNumOperands(); i != e; ++i)
4125 if (N->getOperand(i) != SplatValue)
4130 /// isZeroShuffle - Returns true if N is a VECTOR_SHUFFLE that can be resolved
4131 /// to an zero vector.
4132 /// FIXME: move to dag combiner / method on ShuffleVectorSDNode
4133 static bool isZeroShuffle(ShuffleVectorSDNode *N) {
4134 SDValue V1 = N->getOperand(0);
4135 SDValue V2 = N->getOperand(1);
4136 unsigned NumElems = N->getValueType(0).getVectorNumElements();
4137 for (unsigned i = 0; i != NumElems; ++i) {
4138 int Idx = N->getMaskElt(i);
4139 if (Idx >= (int)NumElems) {
4140 unsigned Opc = V2.getOpcode();
4141 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V2.getNode()))
4143 if (Opc != ISD::BUILD_VECTOR ||
4144 !X86::isZeroNode(V2.getOperand(Idx-NumElems)))
4146 } else if (Idx >= 0) {
4147 unsigned Opc = V1.getOpcode();
4148 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V1.getNode()))
4150 if (Opc != ISD::BUILD_VECTOR ||
4151 !X86::isZeroNode(V1.getOperand(Idx)))
4158 /// getZeroVector - Returns a vector of specified type with all zero elements.
4160 static SDValue getZeroVector(EVT VT, const X86Subtarget *Subtarget,
4161 SelectionDAG &DAG, DebugLoc dl) {
4162 assert(VT.isVector() && "Expected a vector type");
4163 unsigned Size = VT.getSizeInBits();
4165 // Always build SSE zero vectors as <4 x i32> bitcasted
4166 // to their dest type. This ensures they get CSE'd.
4168 if (Size == 128) { // SSE
4169 if (Subtarget->hasSSE2()) { // SSE2
4170 SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
4171 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4173 SDValue Cst = DAG.getTargetConstantFP(+0.0, MVT::f32);
4174 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4f32, Cst, Cst, Cst, Cst);
4176 } else if (Size == 256) { // AVX
4177 if (Subtarget->hasAVX2()) { // AVX2
4178 SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
4179 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4180 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops, 8);
4182 // 256-bit logic and arithmetic instructions in AVX are all
4183 // floating-point, no support for integer ops. Emit fp zeroed vectors.
4184 SDValue Cst = DAG.getTargetConstantFP(+0.0, MVT::f32);
4185 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4186 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8f32, Ops, 8);
4189 llvm_unreachable("Unexpected vector type");
4191 return DAG.getNode(ISD::BITCAST, dl, VT, Vec);
4194 /// getOnesVector - Returns a vector of specified type with all bits set.
4195 /// Always build ones vectors as <4 x i32> or <8 x i32>. For 256-bit types with
4196 /// no AVX2 supprt, use two <4 x i32> inserted in a <8 x i32> appropriately.
4197 /// Then bitcast to their original type, ensuring they get CSE'd.
4198 static SDValue getOnesVector(EVT VT, bool HasAVX2, SelectionDAG &DAG,
4200 assert(VT.isVector() && "Expected a vector type");
4201 unsigned Size = VT.getSizeInBits();
4203 SDValue Cst = DAG.getTargetConstant(~0U, MVT::i32);
4206 if (HasAVX2) { // AVX2
4207 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4208 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops, 8);
4210 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4211 Vec = Concat128BitVectors(Vec, Vec, MVT::v8i32, 8, DAG, dl);
4213 } else if (Size == 128) {
4214 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4216 llvm_unreachable("Unexpected vector type");
4218 return DAG.getNode(ISD::BITCAST, dl, VT, Vec);
4221 /// NormalizeMask - V2 is a splat, modify the mask (if needed) so all elements
4222 /// that point to V2 points to its first element.
4223 static void NormalizeMask(SmallVectorImpl<int> &Mask, unsigned NumElems) {
4224 for (unsigned i = 0; i != NumElems; ++i) {
4225 if (Mask[i] > (int)NumElems) {
4231 /// getMOVLMask - Returns a vector_shuffle mask for an movs{s|d}, movd
4232 /// operation of specified width.
4233 static SDValue getMOVL(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1,
4235 unsigned NumElems = VT.getVectorNumElements();
4236 SmallVector<int, 8> Mask;
4237 Mask.push_back(NumElems);
4238 for (unsigned i = 1; i != NumElems; ++i)
4240 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
4243 /// getUnpackl - Returns a vector_shuffle node for an unpackl operation.
4244 static SDValue getUnpackl(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1,
4246 unsigned NumElems = VT.getVectorNumElements();
4247 SmallVector<int, 8> Mask;
4248 for (unsigned i = 0, e = NumElems/2; i != e; ++i) {
4250 Mask.push_back(i + NumElems);
4252 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
4255 /// getUnpackh - Returns a vector_shuffle node for an unpackh operation.
4256 static SDValue getUnpackh(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1,
4258 unsigned NumElems = VT.getVectorNumElements();
4259 unsigned Half = NumElems/2;
4260 SmallVector<int, 8> Mask;
4261 for (unsigned i = 0; i != Half; ++i) {
4262 Mask.push_back(i + Half);
4263 Mask.push_back(i + NumElems + Half);
4265 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
4268 // PromoteSplati8i16 - All i16 and i8 vector types can't be used directly by
4269 // a generic shuffle instruction because the target has no such instructions.
4270 // Generate shuffles which repeat i16 and i8 several times until they can be
4271 // represented by v4f32 and then be manipulated by target suported shuffles.
4272 static SDValue PromoteSplati8i16(SDValue V, SelectionDAG &DAG, int &EltNo) {
4273 EVT VT = V.getValueType();
4274 int NumElems = VT.getVectorNumElements();
4275 DebugLoc dl = V.getDebugLoc();
4277 while (NumElems > 4) {
4278 if (EltNo < NumElems/2) {
4279 V = getUnpackl(DAG, dl, VT, V, V);
4281 V = getUnpackh(DAG, dl, VT, V, V);
4282 EltNo -= NumElems/2;
4289 /// getLegalSplat - Generate a legal splat with supported x86 shuffles
4290 static SDValue getLegalSplat(SelectionDAG &DAG, SDValue V, int EltNo) {
4291 EVT VT = V.getValueType();
4292 DebugLoc dl = V.getDebugLoc();
4293 unsigned Size = VT.getSizeInBits();
4296 V = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V);
4297 int SplatMask[4] = { EltNo, EltNo, EltNo, EltNo };
4298 V = DAG.getVectorShuffle(MVT::v4f32, dl, V, DAG.getUNDEF(MVT::v4f32),
4300 } else if (Size == 256) {
4301 // To use VPERMILPS to splat scalars, the second half of indicies must
4302 // refer to the higher part, which is a duplication of the lower one,
4303 // because VPERMILPS can only handle in-lane permutations.
4304 int SplatMask[8] = { EltNo, EltNo, EltNo, EltNo,
4305 EltNo+4, EltNo+4, EltNo+4, EltNo+4 };
4307 V = DAG.getNode(ISD::BITCAST, dl, MVT::v8f32, V);
4308 V = DAG.getVectorShuffle(MVT::v8f32, dl, V, DAG.getUNDEF(MVT::v8f32),
4311 llvm_unreachable("Vector size not supported");
4313 return DAG.getNode(ISD::BITCAST, dl, VT, V);
4316 /// PromoteSplat - Splat is promoted to target supported vector shuffles.
4317 static SDValue PromoteSplat(ShuffleVectorSDNode *SV, SelectionDAG &DAG) {
4318 EVT SrcVT = SV->getValueType(0);
4319 SDValue V1 = SV->getOperand(0);
4320 DebugLoc dl = SV->getDebugLoc();
4322 int EltNo = SV->getSplatIndex();
4323 int NumElems = SrcVT.getVectorNumElements();
4324 unsigned Size = SrcVT.getSizeInBits();
4326 assert(((Size == 128 && NumElems > 4) || Size == 256) &&
4327 "Unknown how to promote splat for type");
4329 // Extract the 128-bit part containing the splat element and update
4330 // the splat element index when it refers to the higher register.
4332 unsigned Idx = (EltNo >= NumElems/2) ? NumElems/2 : 0;
4333 V1 = Extract128BitVector(V1, Idx, DAG, dl);
4335 EltNo -= NumElems/2;
4338 // All i16 and i8 vector types can't be used directly by a generic shuffle
4339 // instruction because the target has no such instruction. Generate shuffles
4340 // which repeat i16 and i8 several times until they fit in i32, and then can
4341 // be manipulated by target suported shuffles.
4342 EVT EltVT = SrcVT.getVectorElementType();
4343 if (EltVT == MVT::i8 || EltVT == MVT::i16)
4344 V1 = PromoteSplati8i16(V1, DAG, EltNo);
4346 // Recreate the 256-bit vector and place the same 128-bit vector
4347 // into the low and high part. This is necessary because we want
4348 // to use VPERM* to shuffle the vectors
4350 V1 = DAG.getNode(ISD::CONCAT_VECTORS, dl, SrcVT, V1, V1);
4353 return getLegalSplat(DAG, V1, EltNo);
4356 /// getShuffleVectorZeroOrUndef - Return a vector_shuffle of the specified
4357 /// vector of zero or undef vector. This produces a shuffle where the low
4358 /// element of V2 is swizzled into the zero/undef vector, landing at element
4359 /// Idx. This produces a shuffle mask like 4,1,2,3 (idx=0) or 0,1,2,4 (idx=3).
4360 static SDValue getShuffleVectorZeroOrUndef(SDValue V2, unsigned Idx,
4362 const X86Subtarget *Subtarget,
4363 SelectionDAG &DAG) {
4364 EVT VT = V2.getValueType();
4366 ? getZeroVector(VT, Subtarget, DAG, V2.getDebugLoc()) : DAG.getUNDEF(VT);
4367 unsigned NumElems = VT.getVectorNumElements();
4368 SmallVector<int, 16> MaskVec;
4369 for (unsigned i = 0; i != NumElems; ++i)
4370 // If this is the insertion idx, put the low elt of V2 here.
4371 MaskVec.push_back(i == Idx ? NumElems : i);
4372 return DAG.getVectorShuffle(VT, V2.getDebugLoc(), V1, V2, &MaskVec[0]);
4375 /// getTargetShuffleMask - Calculates the shuffle mask corresponding to the
4376 /// target specific opcode. Returns true if the Mask could be calculated.
4377 /// Sets IsUnary to true if only uses one source.
4378 static bool getTargetShuffleMask(SDNode *N, EVT VT,
4379 SmallVectorImpl<int> &Mask, bool &IsUnary) {
4380 unsigned NumElems = VT.getVectorNumElements();
4384 switch(N->getOpcode()) {
4386 ImmN = N->getOperand(N->getNumOperands()-1);
4387 DecodeSHUFPMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4389 case X86ISD::UNPCKH:
4390 DecodeUNPCKHMask(VT, Mask);
4392 case X86ISD::UNPCKL:
4393 DecodeUNPCKLMask(VT, Mask);
4395 case X86ISD::MOVHLPS:
4396 DecodeMOVHLPSMask(NumElems, Mask);
4398 case X86ISD::MOVLHPS:
4399 DecodeMOVLHPSMask(NumElems, Mask);
4401 case X86ISD::PSHUFD:
4402 case X86ISD::VPERMILP:
4403 ImmN = N->getOperand(N->getNumOperands()-1);
4404 DecodePSHUFMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4407 case X86ISD::PSHUFHW:
4408 ImmN = N->getOperand(N->getNumOperands()-1);
4409 DecodePSHUFHWMask(cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4412 case X86ISD::PSHUFLW:
4413 ImmN = N->getOperand(N->getNumOperands()-1);
4414 DecodePSHUFLWMask(cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4418 case X86ISD::MOVSD: {
4419 // The index 0 always comes from the first element of the second source,
4420 // this is why MOVSS and MOVSD are used in the first place. The other
4421 // elements come from the other positions of the first source vector
4422 Mask.push_back(NumElems);
4423 for (unsigned i = 1; i != NumElems; ++i) {
4428 case X86ISD::VPERM2X128:
4429 ImmN = N->getOperand(N->getNumOperands()-1);
4430 DecodeVPERM2X128Mask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4431 if (Mask.empty()) return false;
4433 case X86ISD::MOVDDUP:
4434 case X86ISD::MOVLHPD:
4435 case X86ISD::MOVLPD:
4436 case X86ISD::MOVLPS:
4437 case X86ISD::MOVSHDUP:
4438 case X86ISD::MOVSLDUP:
4439 case X86ISD::PALIGN:
4440 // Not yet implemented
4442 default: llvm_unreachable("unknown target shuffle node");
4448 /// getShuffleScalarElt - Returns the scalar element that will make up the ith
4449 /// element of the result of the vector shuffle.
4450 static SDValue getShuffleScalarElt(SDNode *N, unsigned Index, SelectionDAG &DAG,
4453 return SDValue(); // Limit search depth.
4455 SDValue V = SDValue(N, 0);
4456 EVT VT = V.getValueType();
4457 unsigned Opcode = V.getOpcode();
4459 // Recurse into ISD::VECTOR_SHUFFLE node to find scalars.
4460 if (const ShuffleVectorSDNode *SV = dyn_cast<ShuffleVectorSDNode>(N)) {
4461 int Elt = SV->getMaskElt(Index);
4464 return DAG.getUNDEF(VT.getVectorElementType());
4466 unsigned NumElems = VT.getVectorNumElements();
4467 SDValue NewV = (Elt < (int)NumElems) ? SV->getOperand(0)
4468 : SV->getOperand(1);
4469 return getShuffleScalarElt(NewV.getNode(), Elt % NumElems, DAG, Depth+1);
4472 // Recurse into target specific vector shuffles to find scalars.
4473 if (isTargetShuffle(Opcode)) {
4474 unsigned NumElems = VT.getVectorNumElements();
4475 SmallVector<int, 16> ShuffleMask;
4479 if (!getTargetShuffleMask(N, VT, ShuffleMask, IsUnary))
4482 int Elt = ShuffleMask[Index];
4484 return DAG.getUNDEF(VT.getVectorElementType());
4486 SDValue NewV = (Elt < (int)NumElems) ? N->getOperand(0)
4488 return getShuffleScalarElt(NewV.getNode(), Elt % NumElems, DAG,
4492 // Actual nodes that may contain scalar elements
4493 if (Opcode == ISD::BITCAST) {
4494 V = V.getOperand(0);
4495 EVT SrcVT = V.getValueType();
4496 unsigned NumElems = VT.getVectorNumElements();
4498 if (!SrcVT.isVector() || SrcVT.getVectorNumElements() != NumElems)
4502 if (V.getOpcode() == ISD::SCALAR_TO_VECTOR)
4503 return (Index == 0) ? V.getOperand(0)
4504 : DAG.getUNDEF(VT.getVectorElementType());
4506 if (V.getOpcode() == ISD::BUILD_VECTOR)
4507 return V.getOperand(Index);
4512 /// getNumOfConsecutiveZeros - Return the number of elements of a vector
4513 /// shuffle operation which come from a consecutively from a zero. The
4514 /// search can start in two different directions, from left or right.
4516 unsigned getNumOfConsecutiveZeros(ShuffleVectorSDNode *SVOp, unsigned NumElems,
4517 bool ZerosFromLeft, SelectionDAG &DAG) {
4519 for (i = 0; i != NumElems; ++i) {
4520 unsigned Index = ZerosFromLeft ? i : NumElems-i-1;
4521 SDValue Elt = getShuffleScalarElt(SVOp, Index, DAG, 0);
4522 if (!(Elt.getNode() &&
4523 (Elt.getOpcode() == ISD::UNDEF || X86::isZeroNode(Elt))))
4530 /// isShuffleMaskConsecutive - Check if the shuffle mask indicies [MaskI, MaskE)
4531 /// correspond consecutively to elements from one of the vector operands,
4532 /// starting from its index OpIdx. Also tell OpNum which source vector operand.
4534 bool isShuffleMaskConsecutive(ShuffleVectorSDNode *SVOp,
4535 unsigned MaskI, unsigned MaskE, unsigned OpIdx,
4536 unsigned NumElems, unsigned &OpNum) {
4537 bool SeenV1 = false;
4538 bool SeenV2 = false;
4540 for (unsigned i = MaskI; i != MaskE; ++i, ++OpIdx) {
4541 int Idx = SVOp->getMaskElt(i);
4542 // Ignore undef indicies
4546 if (Idx < (int)NumElems)
4551 // Only accept consecutive elements from the same vector
4552 if ((Idx % NumElems != OpIdx) || (SeenV1 && SeenV2))
4556 OpNum = SeenV1 ? 0 : 1;
4560 /// isVectorShiftRight - Returns true if the shuffle can be implemented as a
4561 /// logical left shift of a vector.
4562 static bool isVectorShiftRight(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
4563 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
4564 unsigned NumElems = SVOp->getValueType(0).getVectorNumElements();
4565 unsigned NumZeros = getNumOfConsecutiveZeros(SVOp, NumElems,
4566 false /* check zeros from right */, DAG);
4572 // Considering the elements in the mask that are not consecutive zeros,
4573 // check if they consecutively come from only one of the source vectors.
4575 // V1 = {X, A, B, C} 0
4577 // vector_shuffle V1, V2 <1, 2, 3, X>
4579 if (!isShuffleMaskConsecutive(SVOp,
4580 0, // Mask Start Index
4581 NumElems-NumZeros, // Mask End Index(exclusive)
4582 NumZeros, // Where to start looking in the src vector
4583 NumElems, // Number of elements in vector
4584 OpSrc)) // Which source operand ?
4589 ShVal = SVOp->getOperand(OpSrc);
4593 /// isVectorShiftLeft - Returns true if the shuffle can be implemented as a
4594 /// logical left shift of a vector.
4595 static bool isVectorShiftLeft(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
4596 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
4597 unsigned NumElems = SVOp->getValueType(0).getVectorNumElements();
4598 unsigned NumZeros = getNumOfConsecutiveZeros(SVOp, NumElems,
4599 true /* check zeros from left */, DAG);
4605 // Considering the elements in the mask that are not consecutive zeros,
4606 // check if they consecutively come from only one of the source vectors.
4608 // 0 { A, B, X, X } = V2
4610 // vector_shuffle V1, V2 <X, X, 4, 5>
4612 if (!isShuffleMaskConsecutive(SVOp,
4613 NumZeros, // Mask Start Index
4614 NumElems, // Mask End Index(exclusive)
4615 0, // Where to start looking in the src vector
4616 NumElems, // Number of elements in vector
4617 OpSrc)) // Which source operand ?
4622 ShVal = SVOp->getOperand(OpSrc);
4626 /// isVectorShift - Returns true if the shuffle can be implemented as a
4627 /// logical left or right shift of a vector.
4628 static bool isVectorShift(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
4629 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
4630 // Although the logic below support any bitwidth size, there are no
4631 // shift instructions which handle more than 128-bit vectors.
4632 if (SVOp->getValueType(0).getSizeInBits() > 128)
4635 if (isVectorShiftLeft(SVOp, DAG, isLeft, ShVal, ShAmt) ||
4636 isVectorShiftRight(SVOp, DAG, isLeft, ShVal, ShAmt))
4642 /// LowerBuildVectorv16i8 - Custom lower build_vector of v16i8.
4644 static SDValue LowerBuildVectorv16i8(SDValue Op, unsigned NonZeros,
4645 unsigned NumNonZero, unsigned NumZero,
4647 const X86Subtarget* Subtarget,
4648 const TargetLowering &TLI) {
4652 DebugLoc dl = Op.getDebugLoc();
4655 for (unsigned i = 0; i < 16; ++i) {
4656 bool ThisIsNonZero = (NonZeros & (1 << i)) != 0;
4657 if (ThisIsNonZero && First) {
4659 V = getZeroVector(MVT::v8i16, Subtarget, DAG, dl);
4661 V = DAG.getUNDEF(MVT::v8i16);
4666 SDValue ThisElt(0, 0), LastElt(0, 0);
4667 bool LastIsNonZero = (NonZeros & (1 << (i-1))) != 0;
4668 if (LastIsNonZero) {
4669 LastElt = DAG.getNode(ISD::ZERO_EXTEND, dl,
4670 MVT::i16, Op.getOperand(i-1));
4672 if (ThisIsNonZero) {
4673 ThisElt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, Op.getOperand(i));
4674 ThisElt = DAG.getNode(ISD::SHL, dl, MVT::i16,
4675 ThisElt, DAG.getConstant(8, MVT::i8));
4677 ThisElt = DAG.getNode(ISD::OR, dl, MVT::i16, ThisElt, LastElt);
4681 if (ThisElt.getNode())
4682 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, V, ThisElt,
4683 DAG.getIntPtrConstant(i/2));
4687 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V);
4690 /// LowerBuildVectorv8i16 - Custom lower build_vector of v8i16.
4692 static SDValue LowerBuildVectorv8i16(SDValue Op, unsigned NonZeros,
4693 unsigned NumNonZero, unsigned NumZero,
4695 const X86Subtarget* Subtarget,
4696 const TargetLowering &TLI) {
4700 DebugLoc dl = Op.getDebugLoc();
4703 for (unsigned i = 0; i < 8; ++i) {
4704 bool isNonZero = (NonZeros & (1 << i)) != 0;
4708 V = getZeroVector(MVT::v8i16, Subtarget, DAG, dl);
4710 V = DAG.getUNDEF(MVT::v8i16);
4713 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl,
4714 MVT::v8i16, V, Op.getOperand(i),
4715 DAG.getIntPtrConstant(i));
4722 /// getVShift - Return a vector logical shift node.
4724 static SDValue getVShift(bool isLeft, EVT VT, SDValue SrcOp,
4725 unsigned NumBits, SelectionDAG &DAG,
4726 const TargetLowering &TLI, DebugLoc dl) {
4727 assert(VT.getSizeInBits() == 128 && "Unknown type for VShift");
4728 EVT ShVT = MVT::v2i64;
4729 unsigned Opc = isLeft ? X86ISD::VSHLDQ : X86ISD::VSRLDQ;
4730 SrcOp = DAG.getNode(ISD::BITCAST, dl, ShVT, SrcOp);
4731 return DAG.getNode(ISD::BITCAST, dl, VT,
4732 DAG.getNode(Opc, dl, ShVT, SrcOp,
4733 DAG.getConstant(NumBits,
4734 TLI.getShiftAmountTy(SrcOp.getValueType()))));
4738 X86TargetLowering::LowerAsSplatVectorLoad(SDValue SrcOp, EVT VT, DebugLoc dl,
4739 SelectionDAG &DAG) const {
4741 // Check if the scalar load can be widened into a vector load. And if
4742 // the address is "base + cst" see if the cst can be "absorbed" into
4743 // the shuffle mask.
4744 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(SrcOp)) {
4745 SDValue Ptr = LD->getBasePtr();
4746 if (!ISD::isNormalLoad(LD) || LD->isVolatile())
4748 EVT PVT = LD->getValueType(0);
4749 if (PVT != MVT::i32 && PVT != MVT::f32)
4754 if (FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr)) {
4755 FI = FINode->getIndex();
4757 } else if (DAG.isBaseWithConstantOffset(Ptr) &&
4758 isa<FrameIndexSDNode>(Ptr.getOperand(0))) {
4759 FI = cast<FrameIndexSDNode>(Ptr.getOperand(0))->getIndex();
4760 Offset = Ptr.getConstantOperandVal(1);
4761 Ptr = Ptr.getOperand(0);
4766 // FIXME: 256-bit vector instructions don't require a strict alignment,
4767 // improve this code to support it better.
4768 unsigned RequiredAlign = VT.getSizeInBits()/8;
4769 SDValue Chain = LD->getChain();
4770 // Make sure the stack object alignment is at least 16 or 32.
4771 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
4772 if (DAG.InferPtrAlignment(Ptr) < RequiredAlign) {
4773 if (MFI->isFixedObjectIndex(FI)) {
4774 // Can't change the alignment. FIXME: It's possible to compute
4775 // the exact stack offset and reference FI + adjust offset instead.
4776 // If someone *really* cares about this. That's the way to implement it.
4779 MFI->setObjectAlignment(FI, RequiredAlign);
4783 // (Offset % 16 or 32) must be multiple of 4. Then address is then
4784 // Ptr + (Offset & ~15).
4787 if ((Offset % RequiredAlign) & 3)
4789 int64_t StartOffset = Offset & ~(RequiredAlign-1);
4791 Ptr = DAG.getNode(ISD::ADD, Ptr.getDebugLoc(), Ptr.getValueType(),
4792 Ptr,DAG.getConstant(StartOffset, Ptr.getValueType()));
4794 int EltNo = (Offset - StartOffset) >> 2;
4795 int NumElems = VT.getVectorNumElements();
4797 EVT NVT = EVT::getVectorVT(*DAG.getContext(), PVT, NumElems);
4798 SDValue V1 = DAG.getLoad(NVT, dl, Chain, Ptr,
4799 LD->getPointerInfo().getWithOffset(StartOffset),
4800 false, false, false, 0);
4802 SmallVector<int, 8> Mask;
4803 for (int i = 0; i < NumElems; ++i)
4804 Mask.push_back(EltNo);
4806 return DAG.getVectorShuffle(NVT, dl, V1, DAG.getUNDEF(NVT), &Mask[0]);
4812 /// EltsFromConsecutiveLoads - Given the initializing elements 'Elts' of a
4813 /// vector of type 'VT', see if the elements can be replaced by a single large
4814 /// load which has the same value as a build_vector whose operands are 'elts'.
4816 /// Example: <load i32 *a, load i32 *a+4, undef, undef> -> zextload a
4818 /// FIXME: we'd also like to handle the case where the last elements are zero
4819 /// rather than undef via VZEXT_LOAD, but we do not detect that case today.
4820 /// There's even a handy isZeroNode for that purpose.
4821 static SDValue EltsFromConsecutiveLoads(EVT VT, SmallVectorImpl<SDValue> &Elts,
4822 DebugLoc &DL, SelectionDAG &DAG) {
4823 EVT EltVT = VT.getVectorElementType();
4824 unsigned NumElems = Elts.size();
4826 LoadSDNode *LDBase = NULL;
4827 unsigned LastLoadedElt = -1U;
4829 // For each element in the initializer, see if we've found a load or an undef.
4830 // If we don't find an initial load element, or later load elements are
4831 // non-consecutive, bail out.
4832 for (unsigned i = 0; i < NumElems; ++i) {
4833 SDValue Elt = Elts[i];
4835 if (!Elt.getNode() ||
4836 (Elt.getOpcode() != ISD::UNDEF && !ISD::isNON_EXTLoad(Elt.getNode())))
4839 if (Elt.getNode()->getOpcode() == ISD::UNDEF)
4841 LDBase = cast<LoadSDNode>(Elt.getNode());
4845 if (Elt.getOpcode() == ISD::UNDEF)
4848 LoadSDNode *LD = cast<LoadSDNode>(Elt);
4849 if (!DAG.isConsecutiveLoad(LD, LDBase, EltVT.getSizeInBits()/8, i))
4854 // If we have found an entire vector of loads and undefs, then return a large
4855 // load of the entire vector width starting at the base pointer. If we found
4856 // consecutive loads for the low half, generate a vzext_load node.
4857 if (LastLoadedElt == NumElems - 1) {
4858 if (DAG.InferPtrAlignment(LDBase->getBasePtr()) >= 16)
4859 return DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(),
4860 LDBase->getPointerInfo(),
4861 LDBase->isVolatile(), LDBase->isNonTemporal(),
4862 LDBase->isInvariant(), 0);
4863 return DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(),
4864 LDBase->getPointerInfo(),
4865 LDBase->isVolatile(), LDBase->isNonTemporal(),
4866 LDBase->isInvariant(), LDBase->getAlignment());
4868 if (NumElems == 4 && LastLoadedElt == 1 &&
4869 DAG.getTargetLoweringInfo().isTypeLegal(MVT::v2i64)) {
4870 SDVTList Tys = DAG.getVTList(MVT::v2i64, MVT::Other);
4871 SDValue Ops[] = { LDBase->getChain(), LDBase->getBasePtr() };
4873 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, DL, Tys, Ops, 2, MVT::i64,
4874 LDBase->getPointerInfo(),
4875 LDBase->getAlignment(),
4876 false/*isVolatile*/, true/*ReadMem*/,
4878 return DAG.getNode(ISD::BITCAST, DL, VT, ResNode);
4883 /// LowerVectorBroadcast - Attempt to use the vbroadcast instruction
4884 /// to generate a splat value for the following cases:
4885 /// 1. A splat BUILD_VECTOR which uses a single scalar load, or a constant.
4886 /// 2. A splat shuffle which uses a scalar_to_vector node which comes from
4887 /// a scalar load, or a constant.
4888 /// The VBROADCAST node is returned when a pattern is found,
4889 /// or SDValue() otherwise.
4891 X86TargetLowering::LowerVectorBroadcast(SDValue &Op, SelectionDAG &DAG) const {
4892 if (!Subtarget->hasAVX())
4895 EVT VT = Op.getValueType();
4896 DebugLoc dl = Op.getDebugLoc();
4901 switch (Op.getOpcode()) {
4903 // Unknown pattern found.
4906 case ISD::BUILD_VECTOR: {
4907 // The BUILD_VECTOR node must be a splat.
4908 if (!isSplatVector(Op.getNode()))
4911 Ld = Op.getOperand(0);
4912 ConstSplatVal = (Ld.getOpcode() == ISD::Constant ||
4913 Ld.getOpcode() == ISD::ConstantFP);
4915 // The suspected load node has several users. Make sure that all
4916 // of its users are from the BUILD_VECTOR node.
4917 // Constants may have multiple users.
4918 if (!ConstSplatVal && !Ld->hasNUsesOfValue(VT.getVectorNumElements(), 0))
4923 case ISD::VECTOR_SHUFFLE: {
4924 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
4926 // Shuffles must have a splat mask where the first element is
4928 if ((!SVOp->isSplat()) || SVOp->getMaskElt(0) != 0)
4931 SDValue Sc = Op.getOperand(0);
4932 if (Sc.getOpcode() != ISD::SCALAR_TO_VECTOR)
4935 Ld = Sc.getOperand(0);
4936 ConstSplatVal = (Ld.getOpcode() == ISD::Constant ||
4937 Ld.getOpcode() == ISD::ConstantFP);
4939 // The scalar_to_vector node and the suspected
4940 // load node must have exactly one user.
4941 // Constants may have multiple users.
4942 if (!ConstSplatVal && (!Sc.hasOneUse() || !Ld.hasOneUse()))
4948 bool Is256 = VT.getSizeInBits() == 256;
4949 bool Is128 = VT.getSizeInBits() == 128;
4951 // Handle the broadcasting a single constant scalar from the constant pool
4952 // into a vector. On Sandybridge it is still better to load a constant vector
4953 // from the constant pool and not to broadcast it from a scalar.
4954 if (ConstSplatVal && Subtarget->hasAVX2()) {
4955 EVT CVT = Ld.getValueType();
4956 assert(!CVT.isVector() && "Must not broadcast a vector type");
4957 unsigned ScalarSize = CVT.getSizeInBits();
4959 if ((Is256 && (ScalarSize == 32 || ScalarSize == 64)) ||
4960 (Is128 && (ScalarSize == 32))) {
4962 const Constant *C = 0;
4963 if (ConstantSDNode *CI = dyn_cast<ConstantSDNode>(Ld))
4964 C = CI->getConstantIntValue();
4965 else if (ConstantFPSDNode *CF = dyn_cast<ConstantFPSDNode>(Ld))
4966 C = CF->getConstantFPValue();
4968 assert(C && "Invalid constant type");
4970 SDValue CP = DAG.getConstantPool(C, getPointerTy());
4971 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
4972 Ld = DAG.getLoad(CVT, dl, DAG.getEntryNode(), CP,
4973 MachinePointerInfo::getConstantPool(),
4974 false, false, false, Alignment);
4976 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
4980 // The scalar source must be a normal load.
4981 if (!ISD::isNormalLoad(Ld.getNode()))
4984 // Reject loads that have uses of the chain result
4985 if (Ld->hasAnyUseOfValue(1))
4988 unsigned ScalarSize = Ld.getValueType().getSizeInBits();
4990 // VBroadcast to YMM
4991 if (Is256 && (ScalarSize == 32 || ScalarSize == 64))
4992 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
4994 // VBroadcast to XMM
4995 if (Is128 && (ScalarSize == 32))
4996 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
4998 // The integer check is needed for the 64-bit into 128-bit so it doesn't match
4999 // double since there is vbroadcastsd xmm
5000 if (Subtarget->hasAVX2() && Ld.getValueType().isInteger()) {
5001 // VBroadcast to YMM
5002 if (Is256 && (ScalarSize == 8 || ScalarSize == 16))
5003 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5005 // VBroadcast to XMM
5006 if (Is128 && (ScalarSize == 8 || ScalarSize == 16 || ScalarSize == 64))
5007 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5010 // Unsupported broadcast.
5015 X86TargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const {
5016 DebugLoc dl = Op.getDebugLoc();
5018 EVT VT = Op.getValueType();
5019 EVT ExtVT = VT.getVectorElementType();
5020 unsigned NumElems = Op.getNumOperands();
5022 // Vectors containing all zeros can be matched by pxor and xorps later
5023 if (ISD::isBuildVectorAllZeros(Op.getNode())) {
5024 // Canonicalize this to <4 x i32> to 1) ensure the zero vectors are CSE'd
5025 // and 2) ensure that i64 scalars are eliminated on x86-32 hosts.
5026 if (VT == MVT::v4i32 || VT == MVT::v8i32)
5029 return getZeroVector(VT, Subtarget, DAG, dl);
5032 // Vectors containing all ones can be matched by pcmpeqd on 128-bit width
5033 // vectors or broken into v4i32 operations on 256-bit vectors. AVX2 can use
5034 // vpcmpeqd on 256-bit vectors.
5035 if (ISD::isBuildVectorAllOnes(Op.getNode())) {
5036 if (VT == MVT::v4i32 || (VT == MVT::v8i32 && Subtarget->hasAVX2()))
5039 return getOnesVector(VT, Subtarget->hasAVX2(), DAG, dl);
5042 SDValue Broadcast = LowerVectorBroadcast(Op, DAG);
5043 if (Broadcast.getNode())
5046 unsigned EVTBits = ExtVT.getSizeInBits();
5048 unsigned NumZero = 0;
5049 unsigned NumNonZero = 0;
5050 unsigned NonZeros = 0;
5051 bool IsAllConstants = true;
5052 SmallSet<SDValue, 8> Values;
5053 for (unsigned i = 0; i < NumElems; ++i) {
5054 SDValue Elt = Op.getOperand(i);
5055 if (Elt.getOpcode() == ISD::UNDEF)
5058 if (Elt.getOpcode() != ISD::Constant &&
5059 Elt.getOpcode() != ISD::ConstantFP)
5060 IsAllConstants = false;
5061 if (X86::isZeroNode(Elt))
5064 NonZeros |= (1 << i);
5069 // All undef vector. Return an UNDEF. All zero vectors were handled above.
5070 if (NumNonZero == 0)
5071 return DAG.getUNDEF(VT);
5073 // Special case for single non-zero, non-undef, element.
5074 if (NumNonZero == 1) {
5075 unsigned Idx = CountTrailingZeros_32(NonZeros);
5076 SDValue Item = Op.getOperand(Idx);
5078 // If this is an insertion of an i64 value on x86-32, and if the top bits of
5079 // the value are obviously zero, truncate the value to i32 and do the
5080 // insertion that way. Only do this if the value is non-constant or if the
5081 // value is a constant being inserted into element 0. It is cheaper to do
5082 // a constant pool load than it is to do a movd + shuffle.
5083 if (ExtVT == MVT::i64 && !Subtarget->is64Bit() &&
5084 (!IsAllConstants || Idx == 0)) {
5085 if (DAG.MaskedValueIsZero(Item, APInt::getBitsSet(64, 32, 64))) {
5087 assert(VT == MVT::v2i64 && "Expected an SSE value type!");
5088 EVT VecVT = MVT::v4i32;
5089 unsigned VecElts = 4;
5091 // Truncate the value (which may itself be a constant) to i32, and
5092 // convert it to a vector with movd (S2V+shuffle to zero extend).
5093 Item = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Item);
5094 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Item);
5095 Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
5097 // Now we have our 32-bit value zero extended in the low element of
5098 // a vector. If Idx != 0, swizzle it into place.
5100 SmallVector<int, 4> Mask;
5101 Mask.push_back(Idx);
5102 for (unsigned i = 1; i != VecElts; ++i)
5104 Item = DAG.getVectorShuffle(VecVT, dl, Item, DAG.getUNDEF(VecVT),
5107 return DAG.getNode(ISD::BITCAST, dl, VT, Item);
5111 // If we have a constant or non-constant insertion into the low element of
5112 // a vector, we can do this with SCALAR_TO_VECTOR + shuffle of zero into
5113 // the rest of the elements. This will be matched as movd/movq/movss/movsd
5114 // depending on what the source datatype is.
5117 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
5119 if (ExtVT == MVT::i32 || ExtVT == MVT::f32 || ExtVT == MVT::f64 ||
5120 (ExtVT == MVT::i64 && Subtarget->is64Bit())) {
5121 if (VT.getSizeInBits() == 256) {
5122 SDValue ZeroVec = getZeroVector(VT, Subtarget, DAG, dl);
5123 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, ZeroVec,
5124 Item, DAG.getIntPtrConstant(0));
5126 assert(VT.getSizeInBits() == 128 && "Expected an SSE value type!");
5127 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
5128 // Turn it into a MOVL (i.e. movss, movsd, or movd) to a zero vector.
5129 return getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
5132 if (ExtVT == MVT::i16 || ExtVT == MVT::i8) {
5133 Item = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Item);
5134 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, Item);
5135 if (VT.getSizeInBits() == 256) {
5136 SDValue ZeroVec = getZeroVector(MVT::v8i32, Subtarget, DAG, dl);
5137 Item = Insert128BitVector(ZeroVec, Item, 0, DAG, dl);
5139 assert(VT.getSizeInBits() == 128 && "Expected an SSE value type!");
5140 Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
5142 return DAG.getNode(ISD::BITCAST, dl, VT, Item);
5146 // Is it a vector logical left shift?
5147 if (NumElems == 2 && Idx == 1 &&
5148 X86::isZeroNode(Op.getOperand(0)) &&
5149 !X86::isZeroNode(Op.getOperand(1))) {
5150 unsigned NumBits = VT.getSizeInBits();
5151 return getVShift(true, VT,
5152 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
5153 VT, Op.getOperand(1)),
5154 NumBits/2, DAG, *this, dl);
5157 if (IsAllConstants) // Otherwise, it's better to do a constpool load.
5160 // Otherwise, if this is a vector with i32 or f32 elements, and the element
5161 // is a non-constant being inserted into an element other than the low one,
5162 // we can't use a constant pool load. Instead, use SCALAR_TO_VECTOR (aka
5163 // movd/movss) to move this into the low element, then shuffle it into
5165 if (EVTBits == 32) {
5166 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
5168 // Turn it into a shuffle of zero and zero-extended scalar to vector.
5169 Item = getShuffleVectorZeroOrUndef(Item, 0, NumZero > 0, Subtarget, DAG);
5170 SmallVector<int, 8> MaskVec;
5171 for (unsigned i = 0; i < NumElems; i++)
5172 MaskVec.push_back(i == Idx ? 0 : 1);
5173 return DAG.getVectorShuffle(VT, dl, Item, DAG.getUNDEF(VT), &MaskVec[0]);
5177 // Splat is obviously ok. Let legalizer expand it to a shuffle.
5178 if (Values.size() == 1) {
5179 if (EVTBits == 32) {
5180 // Instead of a shuffle like this:
5181 // shuffle (scalar_to_vector (load (ptr + 4))), undef, <0, 0, 0, 0>
5182 // Check if it's possible to issue this instead.
5183 // shuffle (vload ptr)), undef, <1, 1, 1, 1>
5184 unsigned Idx = CountTrailingZeros_32(NonZeros);
5185 SDValue Item = Op.getOperand(Idx);
5186 if (Op.getNode()->isOnlyUserOf(Item.getNode()))
5187 return LowerAsSplatVectorLoad(Item, VT, dl, DAG);
5192 // A vector full of immediates; various special cases are already
5193 // handled, so this is best done with a single constant-pool load.
5197 // For AVX-length vectors, build the individual 128-bit pieces and use
5198 // shuffles to put them in place.
5199 if (VT.getSizeInBits() == 256) {
5200 SmallVector<SDValue, 32> V;
5201 for (unsigned i = 0; i != NumElems; ++i)
5202 V.push_back(Op.getOperand(i));
5204 EVT HVT = EVT::getVectorVT(*DAG.getContext(), ExtVT, NumElems/2);
5206 // Build both the lower and upper subvector.
5207 SDValue Lower = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT, &V[0], NumElems/2);
5208 SDValue Upper = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT, &V[NumElems / 2],
5211 // Recreate the wider vector with the lower and upper part.
5212 return Concat128BitVectors(Lower, Upper, VT, NumElems, DAG, dl);
5215 // Let legalizer expand 2-wide build_vectors.
5216 if (EVTBits == 64) {
5217 if (NumNonZero == 1) {
5218 // One half is zero or undef.
5219 unsigned Idx = CountTrailingZeros_32(NonZeros);
5220 SDValue V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT,
5221 Op.getOperand(Idx));
5222 return getShuffleVectorZeroOrUndef(V2, Idx, true, Subtarget, DAG);
5227 // If element VT is < 32 bits, convert it to inserts into a zero vector.
5228 if (EVTBits == 8 && NumElems == 16) {
5229 SDValue V = LowerBuildVectorv16i8(Op, NonZeros,NumNonZero,NumZero, DAG,
5231 if (V.getNode()) return V;
5234 if (EVTBits == 16 && NumElems == 8) {
5235 SDValue V = LowerBuildVectorv8i16(Op, NonZeros,NumNonZero,NumZero, DAG,
5237 if (V.getNode()) return V;
5240 // If element VT is == 32 bits, turn it into a number of shuffles.
5241 SmallVector<SDValue, 8> V(NumElems);
5242 if (NumElems == 4 && NumZero > 0) {
5243 for (unsigned i = 0; i < 4; ++i) {
5244 bool isZero = !(NonZeros & (1 << i));
5246 V[i] = getZeroVector(VT, Subtarget, DAG, dl);
5248 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
5251 for (unsigned i = 0; i < 2; ++i) {
5252 switch ((NonZeros & (0x3 << i*2)) >> (i*2)) {
5255 V[i] = V[i*2]; // Must be a zero vector.
5258 V[i] = getMOVL(DAG, dl, VT, V[i*2+1], V[i*2]);
5261 V[i] = getMOVL(DAG, dl, VT, V[i*2], V[i*2+1]);
5264 V[i] = getUnpackl(DAG, dl, VT, V[i*2], V[i*2+1]);
5269 bool Reverse1 = (NonZeros & 0x3) == 2;
5270 bool Reverse2 = ((NonZeros & (0x3 << 2)) >> 2) == 2;
5274 static_cast<int>(Reverse2 ? NumElems+1 : NumElems),
5275 static_cast<int>(Reverse2 ? NumElems : NumElems+1)
5277 return DAG.getVectorShuffle(VT, dl, V[0], V[1], &MaskVec[0]);
5280 if (Values.size() > 1 && VT.getSizeInBits() == 128) {
5281 // Check for a build vector of consecutive loads.
5282 for (unsigned i = 0; i < NumElems; ++i)
5283 V[i] = Op.getOperand(i);
5285 // Check for elements which are consecutive loads.
5286 SDValue LD = EltsFromConsecutiveLoads(VT, V, dl, DAG);
5290 // For SSE 4.1, use insertps to put the high elements into the low element.
5291 if (getSubtarget()->hasSSE41()) {
5293 if (Op.getOperand(0).getOpcode() != ISD::UNDEF)
5294 Result = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(0));
5296 Result = DAG.getUNDEF(VT);
5298 for (unsigned i = 1; i < NumElems; ++i) {
5299 if (Op.getOperand(i).getOpcode() == ISD::UNDEF) continue;
5300 Result = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Result,
5301 Op.getOperand(i), DAG.getIntPtrConstant(i));
5306 // Otherwise, expand into a number of unpckl*, start by extending each of
5307 // our (non-undef) elements to the full vector width with the element in the
5308 // bottom slot of the vector (which generates no code for SSE).
5309 for (unsigned i = 0; i < NumElems; ++i) {
5310 if (Op.getOperand(i).getOpcode() != ISD::UNDEF)
5311 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
5313 V[i] = DAG.getUNDEF(VT);
5316 // Next, we iteratively mix elements, e.g. for v4f32:
5317 // Step 1: unpcklps 0, 2 ==> X: <?, ?, 2, 0>
5318 // : unpcklps 1, 3 ==> Y: <?, ?, 3, 1>
5319 // Step 2: unpcklps X, Y ==> <3, 2, 1, 0>
5320 unsigned EltStride = NumElems >> 1;
5321 while (EltStride != 0) {
5322 for (unsigned i = 0; i < EltStride; ++i) {
5323 // If V[i+EltStride] is undef and this is the first round of mixing,
5324 // then it is safe to just drop this shuffle: V[i] is already in the
5325 // right place, the one element (since it's the first round) being
5326 // inserted as undef can be dropped. This isn't safe for successive
5327 // rounds because they will permute elements within both vectors.
5328 if (V[i+EltStride].getOpcode() == ISD::UNDEF &&
5329 EltStride == NumElems/2)
5332 V[i] = getUnpackl(DAG, dl, VT, V[i], V[i + EltStride]);
5341 // LowerMMXCONCAT_VECTORS - We support concatenate two MMX registers and place
5342 // them in a MMX register. This is better than doing a stack convert.
5343 static SDValue LowerMMXCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
5344 DebugLoc dl = Op.getDebugLoc();
5345 EVT ResVT = Op.getValueType();
5347 assert(ResVT == MVT::v2i64 || ResVT == MVT::v4i32 ||
5348 ResVT == MVT::v8i16 || ResVT == MVT::v16i8);
5350 SDValue InVec = DAG.getNode(ISD::BITCAST,dl, MVT::v1i64, Op.getOperand(0));
5351 SDValue VecOp = DAG.getNode(X86ISD::MOVQ2DQ, dl, MVT::v2i64, InVec);
5352 InVec = Op.getOperand(1);
5353 if (InVec.getOpcode() == ISD::SCALAR_TO_VECTOR) {
5354 unsigned NumElts = ResVT.getVectorNumElements();
5355 VecOp = DAG.getNode(ISD::BITCAST, dl, ResVT, VecOp);
5356 VecOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, ResVT, VecOp,
5357 InVec.getOperand(0), DAG.getIntPtrConstant(NumElts/2+1));
5359 InVec = DAG.getNode(ISD::BITCAST, dl, MVT::v1i64, InVec);
5360 SDValue VecOp2 = DAG.getNode(X86ISD::MOVQ2DQ, dl, MVT::v2i64, InVec);
5361 Mask[0] = 0; Mask[1] = 2;
5362 VecOp = DAG.getVectorShuffle(MVT::v2i64, dl, VecOp, VecOp2, Mask);
5364 return DAG.getNode(ISD::BITCAST, dl, ResVT, VecOp);
5367 // LowerAVXCONCAT_VECTORS - 256-bit AVX can use the vinsertf128 instruction
5368 // to create 256-bit vectors from two other 128-bit ones.
5369 static SDValue LowerAVXCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
5370 DebugLoc dl = Op.getDebugLoc();
5371 EVT ResVT = Op.getValueType();
5373 assert(ResVT.getSizeInBits() == 256 && "Value type must be 256-bit wide");
5375 SDValue V1 = Op.getOperand(0);
5376 SDValue V2 = Op.getOperand(1);
5377 unsigned NumElems = ResVT.getVectorNumElements();
5379 return Concat128BitVectors(V1, V2, ResVT, NumElems, DAG, dl);
5383 X86TargetLowering::LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) const {
5384 EVT ResVT = Op.getValueType();
5386 assert(Op.getNumOperands() == 2);
5387 assert((ResVT.getSizeInBits() == 128 || ResVT.getSizeInBits() == 256) &&
5388 "Unsupported CONCAT_VECTORS for value type");
5390 // We support concatenate two MMX registers and place them in a MMX register.
5391 // This is better than doing a stack convert.
5392 if (ResVT.is128BitVector())
5393 return LowerMMXCONCAT_VECTORS(Op, DAG);
5395 // 256-bit AVX can use the vinsertf128 instruction to create 256-bit vectors
5396 // from two other 128-bit ones.
5397 return LowerAVXCONCAT_VECTORS(Op, DAG);
5400 // Try to lower a shuffle node into a simple blend instruction.
5401 static SDValue LowerVECTOR_SHUFFLEtoBlend(ShuffleVectorSDNode *SVOp,
5402 const X86Subtarget *Subtarget,
5403 SelectionDAG &DAG) {
5404 SDValue V1 = SVOp->getOperand(0);
5405 SDValue V2 = SVOp->getOperand(1);
5406 DebugLoc dl = SVOp->getDebugLoc();
5407 MVT VT = SVOp->getValueType(0).getSimpleVT();
5408 unsigned NumElems = VT.getVectorNumElements();
5410 if (!Subtarget->hasSSE41())
5416 switch (VT.SimpleTy) {
5417 default: return SDValue();
5419 ISDNo = X86ISD::BLENDPW;
5424 ISDNo = X86ISD::BLENDPS;
5429 ISDNo = X86ISD::BLENDPD;
5434 if (!Subtarget->hasAVX())
5436 ISDNo = X86ISD::BLENDPS;
5441 if (!Subtarget->hasAVX())
5443 ISDNo = X86ISD::BLENDPD;
5447 assert(ISDNo && "Invalid Op Number");
5449 unsigned MaskVals = 0;
5451 for (unsigned i = 0; i != NumElems; ++i) {
5452 int EltIdx = SVOp->getMaskElt(i);
5453 if (EltIdx == (int)i || EltIdx < 0)
5455 else if (EltIdx == (int)(i + NumElems))
5456 continue; // Bit is set to zero;
5461 V1 = DAG.getNode(ISD::BITCAST, dl, OpTy, V1);
5462 V2 = DAG.getNode(ISD::BITCAST, dl, OpTy, V2);
5463 SDValue Ret = DAG.getNode(ISDNo, dl, OpTy, V1, V2,
5464 DAG.getConstant(MaskVals, MVT::i32));
5465 return DAG.getNode(ISD::BITCAST, dl, VT, Ret);
5468 // v8i16 shuffles - Prefer shuffles in the following order:
5469 // 1. [all] pshuflw, pshufhw, optional move
5470 // 2. [ssse3] 1 x pshufb
5471 // 3. [ssse3] 2 x pshufb + 1 x por
5472 // 4. [all] mov + pshuflw + pshufhw + N x (pextrw + pinsrw)
5474 X86TargetLowering::LowerVECTOR_SHUFFLEv8i16(SDValue Op,
5475 SelectionDAG &DAG) const {
5476 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
5477 SDValue V1 = SVOp->getOperand(0);
5478 SDValue V2 = SVOp->getOperand(1);
5479 DebugLoc dl = SVOp->getDebugLoc();
5480 SmallVector<int, 8> MaskVals;
5482 // Determine if more than 1 of the words in each of the low and high quadwords
5483 // of the result come from the same quadword of one of the two inputs. Undef
5484 // mask values count as coming from any quadword, for better codegen.
5485 unsigned LoQuad[] = { 0, 0, 0, 0 };
5486 unsigned HiQuad[] = { 0, 0, 0, 0 };
5487 std::bitset<4> InputQuads;
5488 for (unsigned i = 0; i < 8; ++i) {
5489 unsigned *Quad = i < 4 ? LoQuad : HiQuad;
5490 int EltIdx = SVOp->getMaskElt(i);
5491 MaskVals.push_back(EltIdx);
5500 InputQuads.set(EltIdx / 4);
5503 int BestLoQuad = -1;
5504 unsigned MaxQuad = 1;
5505 for (unsigned i = 0; i < 4; ++i) {
5506 if (LoQuad[i] > MaxQuad) {
5508 MaxQuad = LoQuad[i];
5512 int BestHiQuad = -1;
5514 for (unsigned i = 0; i < 4; ++i) {
5515 if (HiQuad[i] > MaxQuad) {
5517 MaxQuad = HiQuad[i];
5521 // For SSSE3, If all 8 words of the result come from only 1 quadword of each
5522 // of the two input vectors, shuffle them into one input vector so only a
5523 // single pshufb instruction is necessary. If There are more than 2 input
5524 // quads, disable the next transformation since it does not help SSSE3.
5525 bool V1Used = InputQuads[0] || InputQuads[1];
5526 bool V2Used = InputQuads[2] || InputQuads[3];
5527 if (Subtarget->hasSSSE3()) {
5528 if (InputQuads.count() == 2 && V1Used && V2Used) {
5529 BestLoQuad = InputQuads[0] ? 0 : 1;
5530 BestHiQuad = InputQuads[2] ? 2 : 3;
5532 if (InputQuads.count() > 2) {
5538 // If BestLoQuad or BestHiQuad are set, shuffle the quads together and update
5539 // the shuffle mask. If a quad is scored as -1, that means that it contains
5540 // words from all 4 input quadwords.
5542 if (BestLoQuad >= 0 || BestHiQuad >= 0) {
5544 BestLoQuad < 0 ? 0 : BestLoQuad,
5545 BestHiQuad < 0 ? 1 : BestHiQuad
5547 NewV = DAG.getVectorShuffle(MVT::v2i64, dl,
5548 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, V1),
5549 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, V2), &MaskV[0]);
5550 NewV = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, NewV);
5552 // Rewrite the MaskVals and assign NewV to V1 if NewV now contains all the
5553 // source words for the shuffle, to aid later transformations.
5554 bool AllWordsInNewV = true;
5555 bool InOrder[2] = { true, true };
5556 for (unsigned i = 0; i != 8; ++i) {
5557 int idx = MaskVals[i];
5559 InOrder[i/4] = false;
5560 if (idx < 0 || (idx/4) == BestLoQuad || (idx/4) == BestHiQuad)
5562 AllWordsInNewV = false;
5566 bool pshuflw = AllWordsInNewV, pshufhw = AllWordsInNewV;
5567 if (AllWordsInNewV) {
5568 for (int i = 0; i != 8; ++i) {
5569 int idx = MaskVals[i];
5572 idx = MaskVals[i] = (idx / 4) == BestLoQuad ? (idx & 3) : (idx & 3) + 4;
5573 if ((idx != i) && idx < 4)
5575 if ((idx != i) && idx > 3)
5584 // If we've eliminated the use of V2, and the new mask is a pshuflw or
5585 // pshufhw, that's as cheap as it gets. Return the new shuffle.
5586 if ((pshufhw && InOrder[0]) || (pshuflw && InOrder[1])) {
5587 unsigned Opc = pshufhw ? X86ISD::PSHUFHW : X86ISD::PSHUFLW;
5588 unsigned TargetMask = 0;
5589 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV,
5590 DAG.getUNDEF(MVT::v8i16), &MaskVals[0]);
5591 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode());
5592 TargetMask = pshufhw ? getShufflePSHUFHWImmediate(SVOp):
5593 getShufflePSHUFLWImmediate(SVOp);
5594 V1 = NewV.getOperand(0);
5595 return getTargetShuffleNode(Opc, dl, MVT::v8i16, V1, TargetMask, DAG);
5599 // If we have SSSE3, and all words of the result are from 1 input vector,
5600 // case 2 is generated, otherwise case 3 is generated. If no SSSE3
5601 // is present, fall back to case 4.
5602 if (Subtarget->hasSSSE3()) {
5603 SmallVector<SDValue,16> pshufbMask;
5605 // If we have elements from both input vectors, set the high bit of the
5606 // shuffle mask element to zero out elements that come from V2 in the V1
5607 // mask, and elements that come from V1 in the V2 mask, so that the two
5608 // results can be OR'd together.
5609 bool TwoInputs = V1Used && V2Used;
5610 for (unsigned i = 0; i != 8; ++i) {
5611 int EltIdx = MaskVals[i] * 2;
5612 if (TwoInputs && (EltIdx >= 16)) {
5613 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
5614 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
5617 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
5618 pshufbMask.push_back(DAG.getConstant(EltIdx+1, MVT::i8));
5620 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V1);
5621 V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1,
5622 DAG.getNode(ISD::BUILD_VECTOR, dl,
5623 MVT::v16i8, &pshufbMask[0], 16));
5625 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
5627 // Calculate the shuffle mask for the second input, shuffle it, and
5628 // OR it with the first shuffled input.
5630 for (unsigned i = 0; i != 8; ++i) {
5631 int EltIdx = MaskVals[i] * 2;
5633 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
5634 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
5637 pshufbMask.push_back(DAG.getConstant(EltIdx - 16, MVT::i8));
5638 pshufbMask.push_back(DAG.getConstant(EltIdx - 15, MVT::i8));
5640 V2 = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V2);
5641 V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2,
5642 DAG.getNode(ISD::BUILD_VECTOR, dl,
5643 MVT::v16i8, &pshufbMask[0], 16));
5644 V1 = DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
5645 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
5648 // If BestLoQuad >= 0, generate a pshuflw to put the low elements in order,
5649 // and update MaskVals with new element order.
5650 std::bitset<8> InOrder;
5651 if (BestLoQuad >= 0) {
5652 int MaskV[] = { -1, -1, -1, -1, 4, 5, 6, 7 };
5653 for (int i = 0; i != 4; ++i) {
5654 int idx = MaskVals[i];
5657 } else if ((idx / 4) == BestLoQuad) {
5662 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16),
5665 if (NewV.getOpcode() == ISD::VECTOR_SHUFFLE && Subtarget->hasSSSE3()) {
5666 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode());
5667 NewV = getTargetShuffleNode(X86ISD::PSHUFLW, dl, MVT::v8i16,
5669 getShufflePSHUFLWImmediate(SVOp), DAG);
5673 // If BestHi >= 0, generate a pshufhw to put the high elements in order,
5674 // and update MaskVals with the new element order.
5675 if (BestHiQuad >= 0) {
5676 int MaskV[] = { 0, 1, 2, 3, -1, -1, -1, -1 };
5677 for (unsigned i = 4; i != 8; ++i) {
5678 int idx = MaskVals[i];
5681 } else if ((idx / 4) == BestHiQuad) {
5682 MaskV[i] = (idx & 3) + 4;
5686 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16),
5689 if (NewV.getOpcode() == ISD::VECTOR_SHUFFLE && Subtarget->hasSSSE3()) {
5690 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode());
5691 NewV = getTargetShuffleNode(X86ISD::PSHUFHW, dl, MVT::v8i16,
5693 getShufflePSHUFHWImmediate(SVOp), DAG);
5697 // In case BestHi & BestLo were both -1, which means each quadword has a word
5698 // from each of the four input quadwords, calculate the InOrder bitvector now
5699 // before falling through to the insert/extract cleanup.
5700 if (BestLoQuad == -1 && BestHiQuad == -1) {
5702 for (int i = 0; i != 8; ++i)
5703 if (MaskVals[i] < 0 || MaskVals[i] == i)
5707 // The other elements are put in the right place using pextrw and pinsrw.
5708 for (unsigned i = 0; i != 8; ++i) {
5711 int EltIdx = MaskVals[i];
5714 SDValue ExtOp = (EltIdx < 8)
5715 ? DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V1,
5716 DAG.getIntPtrConstant(EltIdx))
5717 : DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V2,
5718 DAG.getIntPtrConstant(EltIdx - 8));
5719 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, ExtOp,
5720 DAG.getIntPtrConstant(i));
5725 // v16i8 shuffles - Prefer shuffles in the following order:
5726 // 1. [ssse3] 1 x pshufb
5727 // 2. [ssse3] 2 x pshufb + 1 x por
5728 // 3. [all] v8i16 shuffle + N x pextrw + rotate + pinsrw
5730 SDValue LowerVECTOR_SHUFFLEv16i8(ShuffleVectorSDNode *SVOp,
5732 const X86TargetLowering &TLI) {
5733 SDValue V1 = SVOp->getOperand(0);
5734 SDValue V2 = SVOp->getOperand(1);
5735 DebugLoc dl = SVOp->getDebugLoc();
5736 ArrayRef<int> MaskVals = SVOp->getMask();
5738 // If we have SSSE3, case 1 is generated when all result bytes come from
5739 // one of the inputs. Otherwise, case 2 is generated. If no SSSE3 is
5740 // present, fall back to case 3.
5741 // FIXME: kill V2Only once shuffles are canonizalized by getNode.
5744 for (unsigned i = 0; i < 16; ++i) {
5745 int EltIdx = MaskVals[i];
5754 // If SSSE3, use 1 pshufb instruction per vector with elements in the result.
5755 if (TLI.getSubtarget()->hasSSSE3()) {
5756 SmallVector<SDValue,16> pshufbMask;
5758 // If all result elements are from one input vector, then only translate
5759 // undef mask values to 0x80 (zero out result) in the pshufb mask.
5761 // Otherwise, we have elements from both input vectors, and must zero out
5762 // elements that come from V2 in the first mask, and V1 in the second mask
5763 // so that we can OR them together.
5764 bool TwoInputs = !(V1Only || V2Only);
5765 for (unsigned i = 0; i != 16; ++i) {
5766 int EltIdx = MaskVals[i];
5767 if (EltIdx < 0 || (TwoInputs && EltIdx >= 16)) {
5768 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
5771 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
5773 // If all the elements are from V2, assign it to V1 and return after
5774 // building the first pshufb.
5777 V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1,
5778 DAG.getNode(ISD::BUILD_VECTOR, dl,
5779 MVT::v16i8, &pshufbMask[0], 16));
5783 // Calculate the shuffle mask for the second input, shuffle it, and
5784 // OR it with the first shuffled input.
5786 for (unsigned i = 0; i != 16; ++i) {
5787 int EltIdx = MaskVals[i];
5789 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
5792 pshufbMask.push_back(DAG.getConstant(EltIdx - 16, MVT::i8));
5794 V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2,
5795 DAG.getNode(ISD::BUILD_VECTOR, dl,
5796 MVT::v16i8, &pshufbMask[0], 16));
5797 return DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
5800 // No SSSE3 - Calculate in place words and then fix all out of place words
5801 // With 0-16 extracts & inserts. Worst case is 16 bytes out of order from
5802 // the 16 different words that comprise the two doublequadword input vectors.
5803 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
5804 V2 = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V2);
5805 SDValue NewV = V2Only ? V2 : V1;
5806 for (int i = 0; i != 8; ++i) {
5807 int Elt0 = MaskVals[i*2];
5808 int Elt1 = MaskVals[i*2+1];
5810 // This word of the result is all undef, skip it.
5811 if (Elt0 < 0 && Elt1 < 0)
5814 // This word of the result is already in the correct place, skip it.
5815 if (V1Only && (Elt0 == i*2) && (Elt1 == i*2+1))
5817 if (V2Only && (Elt0 == i*2+16) && (Elt1 == i*2+17))
5820 SDValue Elt0Src = Elt0 < 16 ? V1 : V2;
5821 SDValue Elt1Src = Elt1 < 16 ? V1 : V2;
5824 // If Elt0 and Elt1 are defined, are consecutive, and can be load
5825 // using a single extract together, load it and store it.
5826 if ((Elt0 >= 0) && ((Elt0 + 1) == Elt1) && ((Elt0 & 1) == 0)) {
5827 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src,
5828 DAG.getIntPtrConstant(Elt1 / 2));
5829 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt,
5830 DAG.getIntPtrConstant(i));
5834 // If Elt1 is defined, extract it from the appropriate source. If the
5835 // source byte is not also odd, shift the extracted word left 8 bits
5836 // otherwise clear the bottom 8 bits if we need to do an or.
5838 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src,
5839 DAG.getIntPtrConstant(Elt1 / 2));
5840 if ((Elt1 & 1) == 0)
5841 InsElt = DAG.getNode(ISD::SHL, dl, MVT::i16, InsElt,
5843 TLI.getShiftAmountTy(InsElt.getValueType())));
5845 InsElt = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt,
5846 DAG.getConstant(0xFF00, MVT::i16));
5848 // If Elt0 is defined, extract it from the appropriate source. If the
5849 // source byte is not also even, shift the extracted word right 8 bits. If
5850 // Elt1 was also defined, OR the extracted values together before
5851 // inserting them in the result.
5853 SDValue InsElt0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16,
5854 Elt0Src, DAG.getIntPtrConstant(Elt0 / 2));
5855 if ((Elt0 & 1) != 0)
5856 InsElt0 = DAG.getNode(ISD::SRL, dl, MVT::i16, InsElt0,
5858 TLI.getShiftAmountTy(InsElt0.getValueType())));
5860 InsElt0 = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt0,
5861 DAG.getConstant(0x00FF, MVT::i16));
5862 InsElt = Elt1 >= 0 ? DAG.getNode(ISD::OR, dl, MVT::i16, InsElt, InsElt0)
5865 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt,
5866 DAG.getIntPtrConstant(i));
5868 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, NewV);
5871 /// RewriteAsNarrowerShuffle - Try rewriting v8i16 and v16i8 shuffles as 4 wide
5872 /// ones, or rewriting v4i32 / v4f32 as 2 wide ones if possible. This can be
5873 /// done when every pair / quad of shuffle mask elements point to elements in
5874 /// the right sequence. e.g.
5875 /// vector_shuffle X, Y, <2, 3, | 10, 11, | 0, 1, | 14, 15>
5877 SDValue RewriteAsNarrowerShuffle(ShuffleVectorSDNode *SVOp,
5878 SelectionDAG &DAG, DebugLoc dl) {
5879 EVT VT = SVOp->getValueType(0);
5880 SDValue V1 = SVOp->getOperand(0);
5881 SDValue V2 = SVOp->getOperand(1);
5882 unsigned NumElems = VT.getVectorNumElements();
5883 unsigned NewWidth = (NumElems == 4) ? 2 : 4;
5885 switch (VT.getSimpleVT().SimpleTy) {
5886 default: llvm_unreachable("Unexpected!");
5887 case MVT::v4f32: NewVT = MVT::v2f64; break;
5888 case MVT::v4i32: NewVT = MVT::v2i64; break;
5889 case MVT::v8i16: NewVT = MVT::v4i32; break;
5890 case MVT::v16i8: NewVT = MVT::v4i32; break;
5893 int Scale = NumElems / NewWidth;
5894 SmallVector<int, 8> MaskVec;
5895 for (unsigned i = 0; i < NumElems; i += Scale) {
5897 for (int j = 0; j < Scale; ++j) {
5898 int EltIdx = SVOp->getMaskElt(i+j);
5902 StartIdx = EltIdx - (EltIdx % Scale);
5903 if (EltIdx != StartIdx + j)
5907 MaskVec.push_back(-1);
5909 MaskVec.push_back(StartIdx / Scale);
5912 V1 = DAG.getNode(ISD::BITCAST, dl, NewVT, V1);
5913 V2 = DAG.getNode(ISD::BITCAST, dl, NewVT, V2);
5914 return DAG.getVectorShuffle(NewVT, dl, V1, V2, &MaskVec[0]);
5917 /// getVZextMovL - Return a zero-extending vector move low node.
5919 static SDValue getVZextMovL(EVT VT, EVT OpVT,
5920 SDValue SrcOp, SelectionDAG &DAG,
5921 const X86Subtarget *Subtarget, DebugLoc dl) {
5922 if (VT == MVT::v2f64 || VT == MVT::v4f32) {
5923 LoadSDNode *LD = NULL;
5924 if (!isScalarLoadToVector(SrcOp.getNode(), &LD))
5925 LD = dyn_cast<LoadSDNode>(SrcOp);
5927 // movssrr and movsdrr do not clear top bits. Try to use movd, movq
5929 MVT ExtVT = (OpVT == MVT::v2f64) ? MVT::i64 : MVT::i32;
5930 if ((ExtVT != MVT::i64 || Subtarget->is64Bit()) &&
5931 SrcOp.getOpcode() == ISD::SCALAR_TO_VECTOR &&
5932 SrcOp.getOperand(0).getOpcode() == ISD::BITCAST &&
5933 SrcOp.getOperand(0).getOperand(0).getValueType() == ExtVT) {
5935 OpVT = (OpVT == MVT::v2f64) ? MVT::v2i64 : MVT::v4i32;
5936 return DAG.getNode(ISD::BITCAST, dl, VT,
5937 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT,
5938 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
5946 return DAG.getNode(ISD::BITCAST, dl, VT,
5947 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT,
5948 DAG.getNode(ISD::BITCAST, dl,
5952 /// LowerVECTOR_SHUFFLE_256 - Handle all 256-bit wide vectors shuffles
5953 /// which could not be matched by any known target speficic shuffle
5955 LowerVECTOR_SHUFFLE_256(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
5956 EVT VT = SVOp->getValueType(0);
5958 unsigned NumElems = VT.getVectorNumElements();
5959 unsigned NumLaneElems = NumElems / 2;
5961 DebugLoc dl = SVOp->getDebugLoc();
5962 MVT EltVT = VT.getVectorElementType().getSimpleVT();
5963 EVT NVT = MVT::getVectorVT(EltVT, NumLaneElems);
5966 SmallVector<int, 16> Mask;
5967 for (unsigned l = 0; l < 2; ++l) {
5968 // Build a shuffle mask for the output, discovering on the fly which
5969 // input vectors to use as shuffle operands (recorded in InputUsed).
5970 // If building a suitable shuffle vector proves too hard, then bail
5971 // out with useBuildVector set.
5972 int InputUsed[2] = { -1, -1 }; // Not yet discovered.
5973 unsigned LaneStart = l * NumLaneElems;
5974 for (unsigned i = 0; i != NumLaneElems; ++i) {
5975 // The mask element. This indexes into the input.
5976 int Idx = SVOp->getMaskElt(i+LaneStart);
5978 // the mask element does not index into any input vector.
5983 // The input vector this mask element indexes into.
5984 int Input = Idx / NumLaneElems;
5986 // Turn the index into an offset from the start of the input vector.
5987 Idx -= Input * NumLaneElems;
5989 // Find or create a shuffle vector operand to hold this input.
5991 for (OpNo = 0; OpNo < array_lengthof(InputUsed); ++OpNo) {
5992 if (InputUsed[OpNo] == Input)
5993 // This input vector is already an operand.
5995 if (InputUsed[OpNo] < 0) {
5996 // Create a new operand for this input vector.
5997 InputUsed[OpNo] = Input;
6002 if (OpNo >= array_lengthof(InputUsed)) {
6003 // More than two input vectors used! Give up.
6007 // Add the mask index for the new shuffle vector.
6008 Mask.push_back(Idx + OpNo * NumLaneElems);
6011 if (InputUsed[0] < 0) {
6012 // No input vectors were used! The result is undefined.
6013 Shufs[l] = DAG.getUNDEF(NVT);
6015 SDValue Op0 = Extract128BitVector(SVOp->getOperand(InputUsed[0] / 2),
6016 (InputUsed[0] % 2) * NumLaneElems,
6018 // If only one input was used, use an undefined vector for the other.
6019 SDValue Op1 = (InputUsed[1] < 0) ? DAG.getUNDEF(NVT) :
6020 Extract128BitVector(SVOp->getOperand(InputUsed[1] / 2),
6021 (InputUsed[1] % 2) * NumLaneElems, DAG, dl);
6022 // At least one input vector was used. Create a new shuffle vector.
6023 Shufs[l] = DAG.getVectorShuffle(NVT, dl, Op0, Op1, &Mask[0]);
6029 // Concatenate the result back
6030 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, Shufs[0], Shufs[1]);
6033 /// LowerVECTOR_SHUFFLE_128v4 - Handle all 128-bit wide vectors with
6034 /// 4 elements, and match them with several different shuffle types.
6036 LowerVECTOR_SHUFFLE_128v4(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
6037 SDValue V1 = SVOp->getOperand(0);
6038 SDValue V2 = SVOp->getOperand(1);
6039 DebugLoc dl = SVOp->getDebugLoc();
6040 EVT VT = SVOp->getValueType(0);
6042 assert(VT.getSizeInBits() == 128 && "Unsupported vector size");
6044 std::pair<int, int> Locs[4];
6045 int Mask1[] = { -1, -1, -1, -1 };
6046 SmallVector<int, 8> PermMask(SVOp->getMask().begin(), SVOp->getMask().end());
6050 for (unsigned i = 0; i != 4; ++i) {
6051 int Idx = PermMask[i];
6053 Locs[i] = std::make_pair(-1, -1);
6055 assert(Idx < 8 && "Invalid VECTOR_SHUFFLE index!");
6057 Locs[i] = std::make_pair(0, NumLo);
6061 Locs[i] = std::make_pair(1, NumHi);
6063 Mask1[2+NumHi] = Idx;
6069 if (NumLo <= 2 && NumHi <= 2) {
6070 // If no more than two elements come from either vector. This can be
6071 // implemented with two shuffles. First shuffle gather the elements.
6072 // The second shuffle, which takes the first shuffle as both of its
6073 // vector operands, put the elements into the right order.
6074 V1 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
6076 int Mask2[] = { -1, -1, -1, -1 };
6078 for (unsigned i = 0; i != 4; ++i)
6079 if (Locs[i].first != -1) {
6080 unsigned Idx = (i < 2) ? 0 : 4;
6081 Idx += Locs[i].first * 2 + Locs[i].second;
6085 return DAG.getVectorShuffle(VT, dl, V1, V1, &Mask2[0]);
6088 if (NumLo == 3 || NumHi == 3) {
6089 // Otherwise, we must have three elements from one vector, call it X, and
6090 // one element from the other, call it Y. First, use a shufps to build an
6091 // intermediate vector with the one element from Y and the element from X
6092 // that will be in the same half in the final destination (the indexes don't
6093 // matter). Then, use a shufps to build the final vector, taking the half
6094 // containing the element from Y from the intermediate, and the other half
6097 // Normalize it so the 3 elements come from V1.
6098 CommuteVectorShuffleMask(PermMask, 4);
6102 // Find the element from V2.
6104 for (HiIndex = 0; HiIndex < 3; ++HiIndex) {
6105 int Val = PermMask[HiIndex];
6112 Mask1[0] = PermMask[HiIndex];
6114 Mask1[2] = PermMask[HiIndex^1];
6116 V2 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
6119 Mask1[0] = PermMask[0];
6120 Mask1[1] = PermMask[1];
6121 Mask1[2] = HiIndex & 1 ? 6 : 4;
6122 Mask1[3] = HiIndex & 1 ? 4 : 6;
6123 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
6126 Mask1[0] = HiIndex & 1 ? 2 : 0;
6127 Mask1[1] = HiIndex & 1 ? 0 : 2;
6128 Mask1[2] = PermMask[2];
6129 Mask1[3] = PermMask[3];
6134 return DAG.getVectorShuffle(VT, dl, V2, V1, &Mask1[0]);
6137 // Break it into (shuffle shuffle_hi, shuffle_lo).
6138 int LoMask[] = { -1, -1, -1, -1 };
6139 int HiMask[] = { -1, -1, -1, -1 };
6141 int *MaskPtr = LoMask;
6142 unsigned MaskIdx = 0;
6145 for (unsigned i = 0; i != 4; ++i) {
6152 int Idx = PermMask[i];
6154 Locs[i] = std::make_pair(-1, -1);
6155 } else if (Idx < 4) {
6156 Locs[i] = std::make_pair(MaskIdx, LoIdx);
6157 MaskPtr[LoIdx] = Idx;
6160 Locs[i] = std::make_pair(MaskIdx, HiIdx);
6161 MaskPtr[HiIdx] = Idx;
6166 SDValue LoShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &LoMask[0]);
6167 SDValue HiShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &HiMask[0]);
6168 int MaskOps[] = { -1, -1, -1, -1 };
6169 for (unsigned i = 0; i != 4; ++i)
6170 if (Locs[i].first != -1)
6171 MaskOps[i] = Locs[i].first * 4 + Locs[i].second;
6172 return DAG.getVectorShuffle(VT, dl, LoShuffle, HiShuffle, &MaskOps[0]);
6175 static bool MayFoldVectorLoad(SDValue V) {
6176 if (V.hasOneUse() && V.getOpcode() == ISD::BITCAST)
6177 V = V.getOperand(0);
6178 if (V.hasOneUse() && V.getOpcode() == ISD::SCALAR_TO_VECTOR)
6179 V = V.getOperand(0);
6180 if (V.hasOneUse() && V.getOpcode() == ISD::BUILD_VECTOR &&
6181 V.getNumOperands() == 2 && V.getOperand(1).getOpcode() == ISD::UNDEF)
6182 // BUILD_VECTOR (load), undef
6183 V = V.getOperand(0);
6189 // FIXME: the version above should always be used. Since there's
6190 // a bug where several vector shuffles can't be folded because the
6191 // DAG is not updated during lowering and a node claims to have two
6192 // uses while it only has one, use this version, and let isel match
6193 // another instruction if the load really happens to have more than
6194 // one use. Remove this version after this bug get fixed.
6195 // rdar://8434668, PR8156
6196 static bool RelaxedMayFoldVectorLoad(SDValue V) {
6197 if (V.hasOneUse() && V.getOpcode() == ISD::BITCAST)
6198 V = V.getOperand(0);
6199 if (V.hasOneUse() && V.getOpcode() == ISD::SCALAR_TO_VECTOR)
6200 V = V.getOperand(0);
6201 if (ISD::isNormalLoad(V.getNode()))
6207 SDValue getMOVDDup(SDValue &Op, DebugLoc &dl, SDValue V1, SelectionDAG &DAG) {
6208 EVT VT = Op.getValueType();
6210 // Canonizalize to v2f64.
6211 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, V1);
6212 return DAG.getNode(ISD::BITCAST, dl, VT,
6213 getTargetShuffleNode(X86ISD::MOVDDUP, dl, MVT::v2f64,
6218 SDValue getMOVLowToHigh(SDValue &Op, DebugLoc &dl, SelectionDAG &DAG,
6220 SDValue V1 = Op.getOperand(0);
6221 SDValue V2 = Op.getOperand(1);
6222 EVT VT = Op.getValueType();
6224 assert(VT != MVT::v2i64 && "unsupported shuffle type");
6226 if (HasSSE2 && VT == MVT::v2f64)
6227 return getTargetShuffleNode(X86ISD::MOVLHPD, dl, VT, V1, V2, DAG);
6229 // v4f32 or v4i32: canonizalized to v4f32 (which is legal for SSE1)
6230 return DAG.getNode(ISD::BITCAST, dl, VT,
6231 getTargetShuffleNode(X86ISD::MOVLHPS, dl, MVT::v4f32,
6232 DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V1),
6233 DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V2), DAG));
6237 SDValue getMOVHighToLow(SDValue &Op, DebugLoc &dl, SelectionDAG &DAG) {
6238 SDValue V1 = Op.getOperand(0);
6239 SDValue V2 = Op.getOperand(1);
6240 EVT VT = Op.getValueType();
6242 assert((VT == MVT::v4i32 || VT == MVT::v4f32) &&
6243 "unsupported shuffle type");
6245 if (V2.getOpcode() == ISD::UNDEF)
6249 return getTargetShuffleNode(X86ISD::MOVHLPS, dl, VT, V1, V2, DAG);
6253 SDValue getMOVLP(SDValue &Op, DebugLoc &dl, SelectionDAG &DAG, bool HasSSE2) {
6254 SDValue V1 = Op.getOperand(0);
6255 SDValue V2 = Op.getOperand(1);
6256 EVT VT = Op.getValueType();
6257 unsigned NumElems = VT.getVectorNumElements();
6259 // Use MOVLPS and MOVLPD in case V1 or V2 are loads. During isel, the second
6260 // operand of these instructions is only memory, so check if there's a
6261 // potencial load folding here, otherwise use SHUFPS or MOVSD to match the
6263 bool CanFoldLoad = false;
6265 // Trivial case, when V2 comes from a load.
6266 if (MayFoldVectorLoad(V2))
6269 // When V1 is a load, it can be folded later into a store in isel, example:
6270 // (store (v4f32 (X86Movlps (load addr:$src1), VR128:$src2)), addr:$src1)
6272 // (MOVLPSmr addr:$src1, VR128:$src2)
6273 // So, recognize this potential and also use MOVLPS or MOVLPD
6274 else if (MayFoldVectorLoad(V1) && MayFoldIntoStore(Op))
6277 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
6279 if (HasSSE2 && NumElems == 2)
6280 return getTargetShuffleNode(X86ISD::MOVLPD, dl, VT, V1, V2, DAG);
6283 // If we don't care about the second element, procede to use movss.
6284 if (SVOp->getMaskElt(1) != -1)
6285 return getTargetShuffleNode(X86ISD::MOVLPS, dl, VT, V1, V2, DAG);
6288 // movl and movlp will both match v2i64, but v2i64 is never matched by
6289 // movl earlier because we make it strict to avoid messing with the movlp load
6290 // folding logic (see the code above getMOVLP call). Match it here then,
6291 // this is horrible, but will stay like this until we move all shuffle
6292 // matching to x86 specific nodes. Note that for the 1st condition all
6293 // types are matched with movsd.
6295 // FIXME: isMOVLMask should be checked and matched before getMOVLP,
6296 // as to remove this logic from here, as much as possible
6297 if (NumElems == 2 || !isMOVLMask(SVOp->getMask(), VT))
6298 return getTargetShuffleNode(X86ISD::MOVSD, dl, VT, V1, V2, DAG);
6299 return getTargetShuffleNode(X86ISD::MOVSS, dl, VT, V1, V2, DAG);
6302 assert(VT != MVT::v4i32 && "unsupported shuffle type");
6304 // Invert the operand order and use SHUFPS to match it.
6305 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V2, V1,
6306 getShuffleSHUFImmediate(SVOp), DAG);
6310 X86TargetLowering::NormalizeVectorShuffle(SDValue Op, SelectionDAG &DAG) const {
6311 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
6312 EVT VT = Op.getValueType();
6313 DebugLoc dl = Op.getDebugLoc();
6314 SDValue V1 = Op.getOperand(0);
6315 SDValue V2 = Op.getOperand(1);
6317 if (isZeroShuffle(SVOp))
6318 return getZeroVector(VT, Subtarget, DAG, dl);
6320 // Handle splat operations
6321 if (SVOp->isSplat()) {
6322 unsigned NumElem = VT.getVectorNumElements();
6323 int Size = VT.getSizeInBits();
6325 // Use vbroadcast whenever the splat comes from a foldable load
6326 SDValue Broadcast = LowerVectorBroadcast(Op, DAG);
6327 if (Broadcast.getNode())
6330 // Handle splats by matching through known shuffle masks
6331 if ((Size == 128 && NumElem <= 4) ||
6332 (Size == 256 && NumElem < 8))
6335 // All remaning splats are promoted to target supported vector shuffles.
6336 return PromoteSplat(SVOp, DAG);
6339 // If the shuffle can be profitably rewritten as a narrower shuffle, then
6341 if (VT == MVT::v8i16 || VT == MVT::v16i8) {
6342 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG, dl);
6343 if (NewOp.getNode())
6344 return DAG.getNode(ISD::BITCAST, dl, VT, NewOp);
6345 } else if ((VT == MVT::v4i32 ||
6346 (VT == MVT::v4f32 && Subtarget->hasSSE2()))) {
6347 // FIXME: Figure out a cleaner way to do this.
6348 // Try to make use of movq to zero out the top part.
6349 if (ISD::isBuildVectorAllZeros(V2.getNode())) {
6350 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG, dl);
6351 if (NewOp.getNode()) {
6352 EVT NewVT = NewOp.getValueType();
6353 if (isCommutedMOVLMask(cast<ShuffleVectorSDNode>(NewOp)->getMask(),
6354 NewVT, true, false))
6355 return getVZextMovL(VT, NewVT, NewOp.getOperand(0),
6356 DAG, Subtarget, dl);
6358 } else if (ISD::isBuildVectorAllZeros(V1.getNode())) {
6359 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG, dl);
6360 if (NewOp.getNode()) {
6361 EVT NewVT = NewOp.getValueType();
6362 if (isMOVLMask(cast<ShuffleVectorSDNode>(NewOp)->getMask(), NewVT))
6363 return getVZextMovL(VT, NewVT, NewOp.getOperand(1),
6364 DAG, Subtarget, dl);
6372 X86TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const {
6373 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
6374 SDValue V1 = Op.getOperand(0);
6375 SDValue V2 = Op.getOperand(1);
6376 EVT VT = Op.getValueType();
6377 DebugLoc dl = Op.getDebugLoc();
6378 unsigned NumElems = VT.getVectorNumElements();
6379 bool V1IsUndef = V1.getOpcode() == ISD::UNDEF;
6380 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
6381 bool V1IsSplat = false;
6382 bool V2IsSplat = false;
6383 bool HasSSE2 = Subtarget->hasSSE2();
6384 bool HasAVX = Subtarget->hasAVX();
6385 bool HasAVX2 = Subtarget->hasAVX2();
6386 MachineFunction &MF = DAG.getMachineFunction();
6387 bool OptForSize = MF.getFunction()->hasFnAttr(Attribute::OptimizeForSize);
6389 assert(VT.getSizeInBits() != 64 && "Can't lower MMX shuffles");
6391 if (V1IsUndef && V2IsUndef)
6392 return DAG.getUNDEF(VT);
6394 assert(!V1IsUndef && "Op 1 of shuffle should not be undef");
6396 // Vector shuffle lowering takes 3 steps:
6398 // 1) Normalize the input vectors. Here splats, zeroed vectors, profitable
6399 // narrowing and commutation of operands should be handled.
6400 // 2) Matching of shuffles with known shuffle masks to x86 target specific
6402 // 3) Rewriting of unmatched masks into new generic shuffle operations,
6403 // so the shuffle can be broken into other shuffles and the legalizer can
6404 // try the lowering again.
6406 // The general idea is that no vector_shuffle operation should be left to
6407 // be matched during isel, all of them must be converted to a target specific
6410 // Normalize the input vectors. Here splats, zeroed vectors, profitable
6411 // narrowing and commutation of operands should be handled. The actual code
6412 // doesn't include all of those, work in progress...
6413 SDValue NewOp = NormalizeVectorShuffle(Op, DAG);
6414 if (NewOp.getNode())
6417 SmallVector<int, 8> M(SVOp->getMask().begin(), SVOp->getMask().end());
6419 // NOTE: isPSHUFDMask can also match both masks below (unpckl_undef and
6420 // unpckh_undef). Only use pshufd if speed is more important than size.
6421 if (OptForSize && isUNPCKL_v_undef_Mask(M, VT, HasAVX2))
6422 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
6423 if (OptForSize && isUNPCKH_v_undef_Mask(M, VT, HasAVX2))
6424 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
6426 if (isMOVDDUPMask(M, VT) && Subtarget->hasSSE3() &&
6427 V2IsUndef && RelaxedMayFoldVectorLoad(V1))
6428 return getMOVDDup(Op, dl, V1, DAG);
6430 if (isMOVHLPS_v_undef_Mask(M, VT))
6431 return getMOVHighToLow(Op, dl, DAG);
6433 // Use to match splats
6434 if (HasSSE2 && isUNPCKHMask(M, VT, HasAVX2) && V2IsUndef &&
6435 (VT == MVT::v2f64 || VT == MVT::v2i64))
6436 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
6438 if (isPSHUFDMask(M, VT)) {
6439 // The actual implementation will match the mask in the if above and then
6440 // during isel it can match several different instructions, not only pshufd
6441 // as its name says, sad but true, emulate the behavior for now...
6442 if (isMOVDDUPMask(M, VT) && ((VT == MVT::v4f32 || VT == MVT::v2i64)))
6443 return getTargetShuffleNode(X86ISD::MOVLHPS, dl, VT, V1, V1, DAG);
6445 unsigned TargetMask = getShuffleSHUFImmediate(SVOp);
6447 if (HasAVX && (VT == MVT::v4f32 || VT == MVT::v2f64))
6448 return getTargetShuffleNode(X86ISD::VPERMILP, dl, VT, V1, TargetMask, DAG);
6450 if (HasSSE2 && (VT == MVT::v4f32 || VT == MVT::v4i32))
6451 return getTargetShuffleNode(X86ISD::PSHUFD, dl, VT, V1, TargetMask, DAG);
6453 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V1, V1,
6457 // Check if this can be converted into a logical shift.
6458 bool isLeft = false;
6461 bool isShift = HasSSE2 && isVectorShift(SVOp, DAG, isLeft, ShVal, ShAmt);
6462 if (isShift && ShVal.hasOneUse()) {
6463 // If the shifted value has multiple uses, it may be cheaper to use
6464 // v_set0 + movlhps or movhlps, etc.
6465 EVT EltVT = VT.getVectorElementType();
6466 ShAmt *= EltVT.getSizeInBits();
6467 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl);
6470 if (isMOVLMask(M, VT)) {
6471 if (ISD::isBuildVectorAllZeros(V1.getNode()))
6472 return getVZextMovL(VT, VT, V2, DAG, Subtarget, dl);
6473 if (!isMOVLPMask(M, VT)) {
6474 if (HasSSE2 && (VT == MVT::v2i64 || VT == MVT::v2f64))
6475 return getTargetShuffleNode(X86ISD::MOVSD, dl, VT, V1, V2, DAG);
6477 if (VT == MVT::v4i32 || VT == MVT::v4f32)
6478 return getTargetShuffleNode(X86ISD::MOVSS, dl, VT, V1, V2, DAG);
6482 // FIXME: fold these into legal mask.
6483 if (isMOVLHPSMask(M, VT) && !isUNPCKLMask(M, VT, HasAVX2))
6484 return getMOVLowToHigh(Op, dl, DAG, HasSSE2);
6486 if (isMOVHLPSMask(M, VT))
6487 return getMOVHighToLow(Op, dl, DAG);
6489 if (V2IsUndef && isMOVSHDUPMask(M, VT, Subtarget))
6490 return getTargetShuffleNode(X86ISD::MOVSHDUP, dl, VT, V1, DAG);
6492 if (V2IsUndef && isMOVSLDUPMask(M, VT, Subtarget))
6493 return getTargetShuffleNode(X86ISD::MOVSLDUP, dl, VT, V1, DAG);
6495 if (isMOVLPMask(M, VT))
6496 return getMOVLP(Op, dl, DAG, HasSSE2);
6498 if (ShouldXformToMOVHLPS(M, VT) ||
6499 ShouldXformToMOVLP(V1.getNode(), V2.getNode(), M, VT))
6500 return CommuteVectorShuffle(SVOp, DAG);
6503 // No better options. Use a vshldq / vsrldq.
6504 EVT EltVT = VT.getVectorElementType();
6505 ShAmt *= EltVT.getSizeInBits();
6506 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl);
6509 bool Commuted = false;
6510 // FIXME: This should also accept a bitcast of a splat? Be careful, not
6511 // 1,1,1,1 -> v8i16 though.
6512 V1IsSplat = isSplatVector(V1.getNode());
6513 V2IsSplat = isSplatVector(V2.getNode());
6515 // Canonicalize the splat or undef, if present, to be on the RHS.
6516 if (!V2IsUndef && V1IsSplat && !V2IsSplat) {
6517 CommuteVectorShuffleMask(M, NumElems);
6519 std::swap(V1IsSplat, V2IsSplat);
6523 if (isCommutedMOVLMask(M, VT, V2IsSplat, V2IsUndef)) {
6524 // Shuffling low element of v1 into undef, just return v1.
6527 // If V2 is a splat, the mask may be malformed such as <4,3,3,3>, which
6528 // the instruction selector will not match, so get a canonical MOVL with
6529 // swapped operands to undo the commute.
6530 return getMOVL(DAG, dl, VT, V2, V1);
6533 if (isUNPCKLMask(M, VT, HasAVX2))
6534 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG);
6536 if (isUNPCKHMask(M, VT, HasAVX2))
6537 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG);
6540 // Normalize mask so all entries that point to V2 points to its first
6541 // element then try to match unpck{h|l} again. If match, return a
6542 // new vector_shuffle with the corrected mask.p
6543 SmallVector<int, 8> NewMask(M.begin(), M.end());
6544 NormalizeMask(NewMask, NumElems);
6545 if (isUNPCKLMask(NewMask, VT, HasAVX2, true))
6546 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG);
6547 if (isUNPCKHMask(NewMask, VT, HasAVX2, true))
6548 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG);
6552 // Commute is back and try unpck* again.
6553 // FIXME: this seems wrong.
6554 CommuteVectorShuffleMask(M, NumElems);
6556 std::swap(V1IsSplat, V2IsSplat);
6559 if (isUNPCKLMask(M, VT, HasAVX2))
6560 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG);
6562 if (isUNPCKHMask(M, VT, HasAVX2))
6563 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG);
6566 // Normalize the node to match x86 shuffle ops if needed
6567 if (!V2IsUndef && (isSHUFPMask(M, VT, HasAVX, /* Commuted */ true)))
6568 return CommuteVectorShuffle(SVOp, DAG);
6570 // The checks below are all present in isShuffleMaskLegal, but they are
6571 // inlined here right now to enable us to directly emit target specific
6572 // nodes, and remove one by one until they don't return Op anymore.
6574 if (isPALIGNRMask(M, VT, Subtarget))
6575 return getTargetShuffleNode(X86ISD::PALIGN, dl, VT, V1, V2,
6576 getShufflePALIGNRImmediate(SVOp),
6579 if (ShuffleVectorSDNode::isSplatMask(&M[0], VT) &&
6580 SVOp->getSplatIndex() == 0 && V2IsUndef) {
6581 if (VT == MVT::v2f64 || VT == MVT::v2i64)
6582 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
6585 if (isPSHUFHWMask(M, VT))
6586 return getTargetShuffleNode(X86ISD::PSHUFHW, dl, VT, V1,
6587 getShufflePSHUFHWImmediate(SVOp),
6590 if (isPSHUFLWMask(M, VT))
6591 return getTargetShuffleNode(X86ISD::PSHUFLW, dl, VT, V1,
6592 getShufflePSHUFLWImmediate(SVOp),
6595 if (isSHUFPMask(M, VT, HasAVX))
6596 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V1, V2,
6597 getShuffleSHUFImmediate(SVOp), DAG);
6599 if (isUNPCKL_v_undef_Mask(M, VT, HasAVX2))
6600 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
6601 if (isUNPCKH_v_undef_Mask(M, VT, HasAVX2))
6602 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
6604 //===--------------------------------------------------------------------===//
6605 // Generate target specific nodes for 128 or 256-bit shuffles only
6606 // supported in the AVX instruction set.
6609 // Handle VMOVDDUPY permutations
6610 if (V2IsUndef && isMOVDDUPYMask(M, VT, HasAVX))
6611 return getTargetShuffleNode(X86ISD::MOVDDUP, dl, VT, V1, DAG);
6613 // Handle VPERMILPS/D* permutations
6614 if (isVPERMILPMask(M, VT, HasAVX)) {
6615 if (HasAVX2 && VT == MVT::v8i32)
6616 return getTargetShuffleNode(X86ISD::PSHUFD, dl, VT, V1,
6617 getShuffleSHUFImmediate(SVOp), DAG);
6618 return getTargetShuffleNode(X86ISD::VPERMILP, dl, VT, V1,
6619 getShuffleSHUFImmediate(SVOp), DAG);
6622 // Handle VPERM2F128/VPERM2I128 permutations
6623 if (isVPERM2X128Mask(M, VT, HasAVX))
6624 return getTargetShuffleNode(X86ISD::VPERM2X128, dl, VT, V1,
6625 V2, getShuffleVPERM2X128Immediate(SVOp), DAG);
6627 SDValue BlendOp = LowerVECTOR_SHUFFLEtoBlend(SVOp, Subtarget, DAG);
6628 if (BlendOp.getNode())
6631 if (V2IsUndef && HasAVX2 && (VT == MVT::v8i32 || VT == MVT::v8f32)) {
6632 SmallVector<SDValue, 8> permclMask;
6633 for (unsigned i = 0; i != 8; ++i) {
6634 permclMask.push_back(DAG.getConstant((M[i]>=0) ? M[i] : 0, MVT::i32));
6636 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32,
6638 // Bitcast is for VPERMPS since mask is v8i32 but node takes v8f32
6639 return DAG.getNode(X86ISD::VPERMV, dl, VT,
6640 DAG.getNode(ISD::BITCAST, dl, VT, Mask), V1);
6643 if (V2IsUndef && HasAVX2 && (VT == MVT::v4i64 || VT == MVT::v4f64))
6644 return getTargetShuffleNode(X86ISD::VPERMI, dl, VT, V1,
6645 getShuffleCLImmediate(SVOp), DAG);
6648 //===--------------------------------------------------------------------===//
6649 // Since no target specific shuffle was selected for this generic one,
6650 // lower it into other known shuffles. FIXME: this isn't true yet, but
6651 // this is the plan.
6654 // Handle v8i16 specifically since SSE can do byte extraction and insertion.
6655 if (VT == MVT::v8i16) {
6656 SDValue NewOp = LowerVECTOR_SHUFFLEv8i16(Op, DAG);
6657 if (NewOp.getNode())
6661 if (VT == MVT::v16i8) {
6662 SDValue NewOp = LowerVECTOR_SHUFFLEv16i8(SVOp, DAG, *this);
6663 if (NewOp.getNode())
6667 // Handle all 128-bit wide vectors with 4 elements, and match them with
6668 // several different shuffle types.
6669 if (NumElems == 4 && VT.getSizeInBits() == 128)
6670 return LowerVECTOR_SHUFFLE_128v4(SVOp, DAG);
6672 // Handle general 256-bit shuffles
6673 if (VT.is256BitVector())
6674 return LowerVECTOR_SHUFFLE_256(SVOp, DAG);
6680 X86TargetLowering::LowerEXTRACT_VECTOR_ELT_SSE4(SDValue Op,
6681 SelectionDAG &DAG) const {
6682 EVT VT = Op.getValueType();
6683 DebugLoc dl = Op.getDebugLoc();
6685 if (Op.getOperand(0).getValueType().getSizeInBits() != 128)
6688 if (VT.getSizeInBits() == 8) {
6689 SDValue Extract = DAG.getNode(X86ISD::PEXTRB, dl, MVT::i32,
6690 Op.getOperand(0), Op.getOperand(1));
6691 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
6692 DAG.getValueType(VT));
6693 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
6696 if (VT.getSizeInBits() == 16) {
6697 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
6698 // If Idx is 0, it's cheaper to do a move instead of a pextrw.
6700 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
6701 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
6702 DAG.getNode(ISD::BITCAST, dl,
6706 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, MVT::i32,
6707 Op.getOperand(0), Op.getOperand(1));
6708 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
6709 DAG.getValueType(VT));
6710 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
6713 if (VT == MVT::f32) {
6714 // EXTRACTPS outputs to a GPR32 register which will require a movd to copy
6715 // the result back to FR32 register. It's only worth matching if the
6716 // result has a single use which is a store or a bitcast to i32. And in
6717 // the case of a store, it's not worth it if the index is a constant 0,
6718 // because a MOVSSmr can be used instead, which is smaller and faster.
6719 if (!Op.hasOneUse())
6721 SDNode *User = *Op.getNode()->use_begin();
6722 if ((User->getOpcode() != ISD::STORE ||
6723 (isa<ConstantSDNode>(Op.getOperand(1)) &&
6724 cast<ConstantSDNode>(Op.getOperand(1))->isNullValue())) &&
6725 (User->getOpcode() != ISD::BITCAST ||
6726 User->getValueType(0) != MVT::i32))
6728 SDValue Extract = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
6729 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32,
6732 return DAG.getNode(ISD::BITCAST, dl, MVT::f32, Extract);
6735 if (VT == MVT::i32 || VT == MVT::i64) {
6736 // ExtractPS/pextrq works with constant index.
6737 if (isa<ConstantSDNode>(Op.getOperand(1)))
6745 X86TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op,
6746 SelectionDAG &DAG) const {
6747 if (!isa<ConstantSDNode>(Op.getOperand(1)))
6750 SDValue Vec = Op.getOperand(0);
6751 EVT VecVT = Vec.getValueType();
6753 // If this is a 256-bit vector result, first extract the 128-bit vector and
6754 // then extract the element from the 128-bit vector.
6755 if (VecVT.getSizeInBits() == 256) {
6756 DebugLoc dl = Op.getNode()->getDebugLoc();
6757 unsigned NumElems = VecVT.getVectorNumElements();
6758 SDValue Idx = Op.getOperand(1);
6759 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
6761 // Get the 128-bit vector.
6762 bool Upper = IdxVal >= NumElems/2;
6763 Vec = Extract128BitVector(Vec, Upper ? NumElems/2 : 0, DAG, dl);
6765 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, Op.getValueType(), Vec,
6766 Upper ? DAG.getConstant(IdxVal-NumElems/2, MVT::i32) : Idx);
6769 assert(Vec.getValueSizeInBits() <= 128 && "Unexpected vector length");
6771 if (Subtarget->hasSSE41()) {
6772 SDValue Res = LowerEXTRACT_VECTOR_ELT_SSE4(Op, DAG);
6777 EVT VT = Op.getValueType();
6778 DebugLoc dl = Op.getDebugLoc();
6779 // TODO: handle v16i8.
6780 if (VT.getSizeInBits() == 16) {
6781 SDValue Vec = Op.getOperand(0);
6782 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
6784 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
6785 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
6786 DAG.getNode(ISD::BITCAST, dl,
6789 // Transform it so it match pextrw which produces a 32-bit result.
6790 EVT EltVT = MVT::i32;
6791 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, EltVT,
6792 Op.getOperand(0), Op.getOperand(1));
6793 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, EltVT, Extract,
6794 DAG.getValueType(VT));
6795 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
6798 if (VT.getSizeInBits() == 32) {
6799 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
6803 // SHUFPS the element to the lowest double word, then movss.
6804 int Mask[4] = { static_cast<int>(Idx), -1, -1, -1 };
6805 EVT VVT = Op.getOperand(0).getValueType();
6806 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
6807 DAG.getUNDEF(VVT), Mask);
6808 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
6809 DAG.getIntPtrConstant(0));
6812 if (VT.getSizeInBits() == 64) {
6813 // FIXME: .td only matches this for <2 x f64>, not <2 x i64> on 32b
6814 // FIXME: seems like this should be unnecessary if mov{h,l}pd were taught
6815 // to match extract_elt for f64.
6816 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
6820 // UNPCKHPD the element to the lowest double word, then movsd.
6821 // Note if the lower 64 bits of the result of the UNPCKHPD is then stored
6822 // to a f64mem, the whole operation is folded into a single MOVHPDmr.
6823 int Mask[2] = { 1, -1 };
6824 EVT VVT = Op.getOperand(0).getValueType();
6825 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
6826 DAG.getUNDEF(VVT), Mask);
6827 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
6828 DAG.getIntPtrConstant(0));
6835 X86TargetLowering::LowerINSERT_VECTOR_ELT_SSE4(SDValue Op,
6836 SelectionDAG &DAG) const {
6837 EVT VT = Op.getValueType();
6838 EVT EltVT = VT.getVectorElementType();
6839 DebugLoc dl = Op.getDebugLoc();
6841 SDValue N0 = Op.getOperand(0);
6842 SDValue N1 = Op.getOperand(1);
6843 SDValue N2 = Op.getOperand(2);
6845 if (VT.getSizeInBits() == 256)
6848 if ((EltVT.getSizeInBits() == 8 || EltVT.getSizeInBits() == 16) &&
6849 isa<ConstantSDNode>(N2)) {
6851 if (VT == MVT::v8i16)
6852 Opc = X86ISD::PINSRW;
6853 else if (VT == MVT::v16i8)
6854 Opc = X86ISD::PINSRB;
6856 Opc = X86ISD::PINSRB;
6858 // Transform it so it match pinsr{b,w} which expects a GR32 as its second
6860 if (N1.getValueType() != MVT::i32)
6861 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
6862 if (N2.getValueType() != MVT::i32)
6863 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue());
6864 return DAG.getNode(Opc, dl, VT, N0, N1, N2);
6867 if (EltVT == MVT::f32 && isa<ConstantSDNode>(N2)) {
6868 // Bits [7:6] of the constant are the source select. This will always be
6869 // zero here. The DAG Combiner may combine an extract_elt index into these
6870 // bits. For example (insert (extract, 3), 2) could be matched by putting
6871 // the '3' into bits [7:6] of X86ISD::INSERTPS.
6872 // Bits [5:4] of the constant are the destination select. This is the
6873 // value of the incoming immediate.
6874 // Bits [3:0] of the constant are the zero mask. The DAG Combiner may
6875 // combine either bitwise AND or insert of float 0.0 to set these bits.
6876 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue() << 4);
6877 // Create this as a scalar to vector..
6878 N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4f32, N1);
6879 return DAG.getNode(X86ISD::INSERTPS, dl, VT, N0, N1, N2);
6882 if ((EltVT == MVT::i32 || EltVT == MVT::i64) && isa<ConstantSDNode>(N2)) {
6883 // PINSR* works with constant index.
6890 X86TargetLowering::LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const {
6891 EVT VT = Op.getValueType();
6892 EVT EltVT = VT.getVectorElementType();
6894 DebugLoc dl = Op.getDebugLoc();
6895 SDValue N0 = Op.getOperand(0);
6896 SDValue N1 = Op.getOperand(1);
6897 SDValue N2 = Op.getOperand(2);
6899 // If this is a 256-bit vector result, first extract the 128-bit vector,
6900 // insert the element into the extracted half and then place it back.
6901 if (VT.getSizeInBits() == 256) {
6902 if (!isa<ConstantSDNode>(N2))
6905 // Get the desired 128-bit vector half.
6906 unsigned NumElems = VT.getVectorNumElements();
6907 unsigned IdxVal = cast<ConstantSDNode>(N2)->getZExtValue();
6908 bool Upper = IdxVal >= NumElems/2;
6909 unsigned Ins128Idx = Upper ? NumElems/2 : 0;
6910 SDValue V = Extract128BitVector(N0, Ins128Idx, DAG, dl);
6912 // Insert the element into the desired half.
6913 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, V.getValueType(), V,
6914 N1, Upper ? DAG.getConstant(IdxVal-NumElems/2, MVT::i32) : N2);
6916 // Insert the changed part back to the 256-bit vector
6917 return Insert128BitVector(N0, V, Ins128Idx, DAG, dl);
6920 if (Subtarget->hasSSE41())
6921 return LowerINSERT_VECTOR_ELT_SSE4(Op, DAG);
6923 if (EltVT == MVT::i8)
6926 if (EltVT.getSizeInBits() == 16 && isa<ConstantSDNode>(N2)) {
6927 // Transform it so it match pinsrw which expects a 16-bit value in a GR32
6928 // as its second argument.
6929 if (N1.getValueType() != MVT::i32)
6930 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
6931 if (N2.getValueType() != MVT::i32)
6932 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue());
6933 return DAG.getNode(X86ISD::PINSRW, dl, VT, N0, N1, N2);
6939 X86TargetLowering::LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) const {
6940 LLVMContext *Context = DAG.getContext();
6941 DebugLoc dl = Op.getDebugLoc();
6942 EVT OpVT = Op.getValueType();
6944 // If this is a 256-bit vector result, first insert into a 128-bit
6945 // vector and then insert into the 256-bit vector.
6946 if (OpVT.getSizeInBits() > 128) {
6947 // Insert into a 128-bit vector.
6948 EVT VT128 = EVT::getVectorVT(*Context,
6949 OpVT.getVectorElementType(),
6950 OpVT.getVectorNumElements() / 2);
6952 Op = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT128, Op.getOperand(0));
6954 // Insert the 128-bit vector.
6955 return Insert128BitVector(DAG.getUNDEF(OpVT), Op, 0, DAG, dl);
6958 if (Op.getValueType() == MVT::v1i64 &&
6959 Op.getOperand(0).getValueType() == MVT::i64)
6960 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v1i64, Op.getOperand(0));
6962 SDValue AnyExt = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, Op.getOperand(0));
6963 assert(Op.getValueType().getSimpleVT().getSizeInBits() == 128 &&
6964 "Expected an SSE type!");
6965 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(),
6966 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,AnyExt));
6969 // Lower a node with an EXTRACT_SUBVECTOR opcode. This may result in
6970 // a simple subregister reference or explicit instructions to grab
6971 // upper bits of a vector.
6973 X86TargetLowering::LowerEXTRACT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const {
6974 if (Subtarget->hasAVX()) {
6975 DebugLoc dl = Op.getNode()->getDebugLoc();
6976 SDValue Vec = Op.getNode()->getOperand(0);
6977 SDValue Idx = Op.getNode()->getOperand(1);
6979 if (Op.getNode()->getValueType(0).getSizeInBits() == 128 &&
6980 Vec.getNode()->getValueType(0).getSizeInBits() == 256 &&
6981 isa<ConstantSDNode>(Idx)) {
6982 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
6983 return Extract128BitVector(Vec, IdxVal, DAG, dl);
6989 // Lower a node with an INSERT_SUBVECTOR opcode. This may result in a
6990 // simple superregister reference or explicit instructions to insert
6991 // the upper bits of a vector.
6993 X86TargetLowering::LowerINSERT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const {
6994 if (Subtarget->hasAVX()) {
6995 DebugLoc dl = Op.getNode()->getDebugLoc();
6996 SDValue Vec = Op.getNode()->getOperand(0);
6997 SDValue SubVec = Op.getNode()->getOperand(1);
6998 SDValue Idx = Op.getNode()->getOperand(2);
7000 if (Op.getNode()->getValueType(0).getSizeInBits() == 256 &&
7001 SubVec.getNode()->getValueType(0).getSizeInBits() == 128 &&
7002 isa<ConstantSDNode>(Idx)) {
7003 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
7004 return Insert128BitVector(Vec, SubVec, IdxVal, DAG, dl);
7010 // ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as
7011 // their target countpart wrapped in the X86ISD::Wrapper node. Suppose N is
7012 // one of the above mentioned nodes. It has to be wrapped because otherwise
7013 // Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only
7014 // be used to form addressing mode. These wrapped nodes will be selected
7017 X86TargetLowering::LowerConstantPool(SDValue Op, SelectionDAG &DAG) const {
7018 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
7020 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
7022 unsigned char OpFlag = 0;
7023 unsigned WrapperKind = X86ISD::Wrapper;
7024 CodeModel::Model M = getTargetMachine().getCodeModel();
7026 if (Subtarget->isPICStyleRIPRel() &&
7027 (M == CodeModel::Small || M == CodeModel::Kernel))
7028 WrapperKind = X86ISD::WrapperRIP;
7029 else if (Subtarget->isPICStyleGOT())
7030 OpFlag = X86II::MO_GOTOFF;
7031 else if (Subtarget->isPICStyleStubPIC())
7032 OpFlag = X86II::MO_PIC_BASE_OFFSET;
7034 SDValue Result = DAG.getTargetConstantPool(CP->getConstVal(), getPointerTy(),
7036 CP->getOffset(), OpFlag);
7037 DebugLoc DL = CP->getDebugLoc();
7038 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
7039 // With PIC, the address is actually $g + Offset.
7041 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
7042 DAG.getNode(X86ISD::GlobalBaseReg,
7043 DebugLoc(), getPointerTy()),
7050 SDValue X86TargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) const {
7051 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
7053 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
7055 unsigned char OpFlag = 0;
7056 unsigned WrapperKind = X86ISD::Wrapper;
7057 CodeModel::Model M = getTargetMachine().getCodeModel();
7059 if (Subtarget->isPICStyleRIPRel() &&
7060 (M == CodeModel::Small || M == CodeModel::Kernel))
7061 WrapperKind = X86ISD::WrapperRIP;
7062 else if (Subtarget->isPICStyleGOT())
7063 OpFlag = X86II::MO_GOTOFF;
7064 else if (Subtarget->isPICStyleStubPIC())
7065 OpFlag = X86II::MO_PIC_BASE_OFFSET;
7067 SDValue Result = DAG.getTargetJumpTable(JT->getIndex(), getPointerTy(),
7069 DebugLoc DL = JT->getDebugLoc();
7070 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
7072 // With PIC, the address is actually $g + Offset.
7074 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
7075 DAG.getNode(X86ISD::GlobalBaseReg,
7076 DebugLoc(), getPointerTy()),
7083 X86TargetLowering::LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) const {
7084 const char *Sym = cast<ExternalSymbolSDNode>(Op)->getSymbol();
7086 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
7088 unsigned char OpFlag = 0;
7089 unsigned WrapperKind = X86ISD::Wrapper;
7090 CodeModel::Model M = getTargetMachine().getCodeModel();
7092 if (Subtarget->isPICStyleRIPRel() &&
7093 (M == CodeModel::Small || M == CodeModel::Kernel)) {
7094 if (Subtarget->isTargetDarwin() || Subtarget->isTargetELF())
7095 OpFlag = X86II::MO_GOTPCREL;
7096 WrapperKind = X86ISD::WrapperRIP;
7097 } else if (Subtarget->isPICStyleGOT()) {
7098 OpFlag = X86II::MO_GOT;
7099 } else if (Subtarget->isPICStyleStubPIC()) {
7100 OpFlag = X86II::MO_DARWIN_NONLAZY_PIC_BASE;
7101 } else if (Subtarget->isPICStyleStubNoDynamic()) {
7102 OpFlag = X86II::MO_DARWIN_NONLAZY;
7105 SDValue Result = DAG.getTargetExternalSymbol(Sym, getPointerTy(), OpFlag);
7107 DebugLoc DL = Op.getDebugLoc();
7108 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
7111 // With PIC, the address is actually $g + Offset.
7112 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
7113 !Subtarget->is64Bit()) {
7114 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
7115 DAG.getNode(X86ISD::GlobalBaseReg,
7116 DebugLoc(), getPointerTy()),
7120 // For symbols that require a load from a stub to get the address, emit the
7122 if (isGlobalStubReference(OpFlag))
7123 Result = DAG.getLoad(getPointerTy(), DL, DAG.getEntryNode(), Result,
7124 MachinePointerInfo::getGOT(), false, false, false, 0);
7130 X86TargetLowering::LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const {
7131 // Create the TargetBlockAddressAddress node.
7132 unsigned char OpFlags =
7133 Subtarget->ClassifyBlockAddressReference();
7134 CodeModel::Model M = getTargetMachine().getCodeModel();
7135 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
7136 DebugLoc dl = Op.getDebugLoc();
7137 SDValue Result = DAG.getBlockAddress(BA, getPointerTy(),
7138 /*isTarget=*/true, OpFlags);
7140 if (Subtarget->isPICStyleRIPRel() &&
7141 (M == CodeModel::Small || M == CodeModel::Kernel))
7142 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
7144 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
7146 // With PIC, the address is actually $g + Offset.
7147 if (isGlobalRelativeToPICBase(OpFlags)) {
7148 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
7149 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
7157 X86TargetLowering::LowerGlobalAddress(const GlobalValue *GV, DebugLoc dl,
7159 SelectionDAG &DAG) const {
7160 // Create the TargetGlobalAddress node, folding in the constant
7161 // offset if it is legal.
7162 unsigned char OpFlags =
7163 Subtarget->ClassifyGlobalReference(GV, getTargetMachine());
7164 CodeModel::Model M = getTargetMachine().getCodeModel();
7166 if (OpFlags == X86II::MO_NO_FLAG &&
7167 X86::isOffsetSuitableForCodeModel(Offset, M)) {
7168 // A direct static reference to a global.
7169 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), Offset);
7172 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), 0, OpFlags);
7175 if (Subtarget->isPICStyleRIPRel() &&
7176 (M == CodeModel::Small || M == CodeModel::Kernel))
7177 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
7179 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
7181 // With PIC, the address is actually $g + Offset.
7182 if (isGlobalRelativeToPICBase(OpFlags)) {
7183 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
7184 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
7188 // For globals that require a load from a stub to get the address, emit the
7190 if (isGlobalStubReference(OpFlags))
7191 Result = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Result,
7192 MachinePointerInfo::getGOT(), false, false, false, 0);
7194 // If there was a non-zero offset that we didn't fold, create an explicit
7197 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(), Result,
7198 DAG.getConstant(Offset, getPointerTy()));
7204 X86TargetLowering::LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const {
7205 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
7206 int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset();
7207 return LowerGlobalAddress(GV, Op.getDebugLoc(), Offset, DAG);
7211 GetTLSADDR(SelectionDAG &DAG, SDValue Chain, GlobalAddressSDNode *GA,
7212 SDValue *InFlag, const EVT PtrVT, unsigned ReturnReg,
7213 unsigned char OperandFlags) {
7214 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
7215 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
7216 DebugLoc dl = GA->getDebugLoc();
7217 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
7218 GA->getValueType(0),
7222 SDValue Ops[] = { Chain, TGA, *InFlag };
7223 Chain = DAG.getNode(X86ISD::TLSADDR, dl, NodeTys, Ops, 3);
7225 SDValue Ops[] = { Chain, TGA };
7226 Chain = DAG.getNode(X86ISD::TLSADDR, dl, NodeTys, Ops, 2);
7229 // TLSADDR will be codegen'ed as call. Inform MFI that function has calls.
7230 MFI->setAdjustsStack(true);
7232 SDValue Flag = Chain.getValue(1);
7233 return DAG.getCopyFromReg(Chain, dl, ReturnReg, PtrVT, Flag);
7236 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 32 bit
7238 LowerToTLSGeneralDynamicModel32(GlobalAddressSDNode *GA, SelectionDAG &DAG,
7241 DebugLoc dl = GA->getDebugLoc(); // ? function entry point might be better
7242 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
7243 DAG.getNode(X86ISD::GlobalBaseReg,
7244 DebugLoc(), PtrVT), InFlag);
7245 InFlag = Chain.getValue(1);
7247 return GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX, X86II::MO_TLSGD);
7250 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 64 bit
7252 LowerToTLSGeneralDynamicModel64(GlobalAddressSDNode *GA, SelectionDAG &DAG,
7254 return GetTLSADDR(DAG, DAG.getEntryNode(), GA, NULL, PtrVT,
7255 X86::RAX, X86II::MO_TLSGD);
7258 // Lower ISD::GlobalTLSAddress using the "initial exec" (for no-pic) or
7259 // "local exec" model.
7260 static SDValue LowerToTLSExecModel(GlobalAddressSDNode *GA, SelectionDAG &DAG,
7261 const EVT PtrVT, TLSModel::Model model,
7263 DebugLoc dl = GA->getDebugLoc();
7265 // Get the Thread Pointer, which is %gs:0 (32-bit) or %fs:0 (64-bit).
7266 Value *Ptr = Constant::getNullValue(Type::getInt8PtrTy(*DAG.getContext(),
7267 is64Bit ? 257 : 256));
7269 SDValue ThreadPointer = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
7270 DAG.getIntPtrConstant(0),
7271 MachinePointerInfo(Ptr),
7272 false, false, false, 0);
7274 unsigned char OperandFlags = 0;
7275 // Most TLS accesses are not RIP relative, even on x86-64. One exception is
7277 unsigned WrapperKind = X86ISD::Wrapper;
7278 if (model == TLSModel::LocalExec) {
7279 OperandFlags = is64Bit ? X86II::MO_TPOFF : X86II::MO_NTPOFF;
7280 } else if (is64Bit) {
7281 assert(model == TLSModel::InitialExec);
7282 OperandFlags = X86II::MO_GOTTPOFF;
7283 WrapperKind = X86ISD::WrapperRIP;
7285 assert(model == TLSModel::InitialExec);
7286 OperandFlags = X86II::MO_INDNTPOFF;
7289 // emit "addl x@ntpoff,%eax" (local exec) or "addl x@indntpoff,%eax" (initial
7291 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
7292 GA->getValueType(0),
7293 GA->getOffset(), OperandFlags);
7294 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
7296 if (model == TLSModel::InitialExec)
7297 Offset = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Offset,
7298 MachinePointerInfo::getGOT(), false, false, false, 0);
7300 // The address of the thread local variable is the add of the thread
7301 // pointer with the offset of the variable.
7302 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset);
7306 X86TargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const {
7308 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
7309 const GlobalValue *GV = GA->getGlobal();
7311 if (Subtarget->isTargetELF()) {
7312 // TODO: implement the "local dynamic" model
7313 // TODO: implement the "initial exec"model for pic executables
7315 // If GV is an alias then use the aliasee for determining
7316 // thread-localness.
7317 if (const GlobalAlias *GA = dyn_cast<GlobalAlias>(GV))
7318 GV = GA->resolveAliasedGlobal(false);
7320 TLSModel::Model model = getTargetMachine().getTLSModel(GV);
7323 case TLSModel::GeneralDynamic:
7324 case TLSModel::LocalDynamic: // not implemented
7325 if (Subtarget->is64Bit())
7326 return LowerToTLSGeneralDynamicModel64(GA, DAG, getPointerTy());
7327 return LowerToTLSGeneralDynamicModel32(GA, DAG, getPointerTy());
7329 case TLSModel::InitialExec:
7330 case TLSModel::LocalExec:
7331 return LowerToTLSExecModel(GA, DAG, getPointerTy(), model,
7332 Subtarget->is64Bit());
7334 llvm_unreachable("Unknown TLS model.");
7337 if (Subtarget->isTargetDarwin()) {
7338 // Darwin only has one model of TLS. Lower to that.
7339 unsigned char OpFlag = 0;
7340 unsigned WrapperKind = Subtarget->isPICStyleRIPRel() ?
7341 X86ISD::WrapperRIP : X86ISD::Wrapper;
7343 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
7345 bool PIC32 = (getTargetMachine().getRelocationModel() == Reloc::PIC_) &&
7346 !Subtarget->is64Bit();
7348 OpFlag = X86II::MO_TLVP_PIC_BASE;
7350 OpFlag = X86II::MO_TLVP;
7351 DebugLoc DL = Op.getDebugLoc();
7352 SDValue Result = DAG.getTargetGlobalAddress(GA->getGlobal(), DL,
7353 GA->getValueType(0),
7354 GA->getOffset(), OpFlag);
7355 SDValue Offset = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
7357 // With PIC32, the address is actually $g + Offset.
7359 Offset = DAG.getNode(ISD::ADD, DL, getPointerTy(),
7360 DAG.getNode(X86ISD::GlobalBaseReg,
7361 DebugLoc(), getPointerTy()),
7364 // Lowering the machine isd will make sure everything is in the right
7366 SDValue Chain = DAG.getEntryNode();
7367 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
7368 SDValue Args[] = { Chain, Offset };
7369 Chain = DAG.getNode(X86ISD::TLSCALL, DL, NodeTys, Args, 2);
7371 // TLSCALL will be codegen'ed as call. Inform MFI that function has calls.
7372 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
7373 MFI->setAdjustsStack(true);
7375 // And our return value (tls address) is in the standard call return value
7377 unsigned Reg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
7378 return DAG.getCopyFromReg(Chain, DL, Reg, getPointerTy(),
7382 if (Subtarget->isTargetWindows()) {
7383 // Just use the implicit TLS architecture
7384 // Need to generate someting similar to:
7385 // mov rdx, qword [gs:abs 58H]; Load pointer to ThreadLocalStorage
7387 // mov ecx, dword [rel _tls_index]: Load index (from C runtime)
7388 // mov rcx, qword [rdx+rcx*8]
7389 // mov eax, .tls$:tlsvar
7390 // [rax+rcx] contains the address
7391 // Windows 64bit: gs:0x58
7392 // Windows 32bit: fs:__tls_array
7394 // If GV is an alias then use the aliasee for determining
7395 // thread-localness.
7396 if (const GlobalAlias *GA = dyn_cast<GlobalAlias>(GV))
7397 GV = GA->resolveAliasedGlobal(false);
7398 DebugLoc dl = GA->getDebugLoc();
7399 SDValue Chain = DAG.getEntryNode();
7401 // Get the Thread Pointer, which is %fs:__tls_array (32-bit) or
7402 // %gs:0x58 (64-bit).
7403 Value *Ptr = Constant::getNullValue(Subtarget->is64Bit()
7404 ? Type::getInt8PtrTy(*DAG.getContext(),
7406 : Type::getInt32PtrTy(*DAG.getContext(),
7409 SDValue ThreadPointer = DAG.getLoad(getPointerTy(), dl, Chain,
7410 Subtarget->is64Bit()
7411 ? DAG.getIntPtrConstant(0x58)
7412 : DAG.getExternalSymbol("_tls_array",
7414 MachinePointerInfo(Ptr),
7415 false, false, false, 0);
7417 // Load the _tls_index variable
7418 SDValue IDX = DAG.getExternalSymbol("_tls_index", getPointerTy());
7419 if (Subtarget->is64Bit())
7420 IDX = DAG.getExtLoad(ISD::ZEXTLOAD, dl, getPointerTy(), Chain,
7421 IDX, MachinePointerInfo(), MVT::i32,
7424 IDX = DAG.getLoad(getPointerTy(), dl, Chain, IDX, MachinePointerInfo(),
7425 false, false, false, 0);
7427 SDValue Scale = DAG.getConstant(Log2_64_Ceil(TD->getPointerSize()),
7429 IDX = DAG.getNode(ISD::SHL, dl, getPointerTy(), IDX, Scale);
7431 SDValue res = DAG.getNode(ISD::ADD, dl, getPointerTy(), ThreadPointer, IDX);
7432 res = DAG.getLoad(getPointerTy(), dl, Chain, res, MachinePointerInfo(),
7433 false, false, false, 0);
7435 // Get the offset of start of .tls section
7436 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
7437 GA->getValueType(0),
7438 GA->getOffset(), X86II::MO_SECREL);
7439 SDValue Offset = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), TGA);
7441 // The address of the thread local variable is the add of the thread
7442 // pointer with the offset of the variable.
7443 return DAG.getNode(ISD::ADD, dl, getPointerTy(), res, Offset);
7446 llvm_unreachable("TLS not implemented for this target.");
7450 /// LowerShiftParts - Lower SRA_PARTS and friends, which return two i32 values
7451 /// and take a 2 x i32 value to shift plus a shift amount.
7452 SDValue X86TargetLowering::LowerShiftParts(SDValue Op, SelectionDAG &DAG) const{
7453 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
7454 EVT VT = Op.getValueType();
7455 unsigned VTBits = VT.getSizeInBits();
7456 DebugLoc dl = Op.getDebugLoc();
7457 bool isSRA = Op.getOpcode() == ISD::SRA_PARTS;
7458 SDValue ShOpLo = Op.getOperand(0);
7459 SDValue ShOpHi = Op.getOperand(1);
7460 SDValue ShAmt = Op.getOperand(2);
7461 SDValue Tmp1 = isSRA ? DAG.getNode(ISD::SRA, dl, VT, ShOpHi,
7462 DAG.getConstant(VTBits - 1, MVT::i8))
7463 : DAG.getConstant(0, VT);
7466 if (Op.getOpcode() == ISD::SHL_PARTS) {
7467 Tmp2 = DAG.getNode(X86ISD::SHLD, dl, VT, ShOpHi, ShOpLo, ShAmt);
7468 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ShAmt);
7470 Tmp2 = DAG.getNode(X86ISD::SHRD, dl, VT, ShOpLo, ShOpHi, ShAmt);
7471 Tmp3 = DAG.getNode(isSRA ? ISD::SRA : ISD::SRL, dl, VT, ShOpHi, ShAmt);
7474 SDValue AndNode = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt,
7475 DAG.getConstant(VTBits, MVT::i8));
7476 SDValue Cond = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
7477 AndNode, DAG.getConstant(0, MVT::i8));
7480 SDValue CC = DAG.getConstant(X86::COND_NE, MVT::i8);
7481 SDValue Ops0[4] = { Tmp2, Tmp3, CC, Cond };
7482 SDValue Ops1[4] = { Tmp3, Tmp1, CC, Cond };
7484 if (Op.getOpcode() == ISD::SHL_PARTS) {
7485 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0, 4);
7486 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1, 4);
7488 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0, 4);
7489 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1, 4);
7492 SDValue Ops[2] = { Lo, Hi };
7493 return DAG.getMergeValues(Ops, 2, dl);
7496 SDValue X86TargetLowering::LowerSINT_TO_FP(SDValue Op,
7497 SelectionDAG &DAG) const {
7498 EVT SrcVT = Op.getOperand(0).getValueType();
7500 if (SrcVT.isVector())
7503 assert(SrcVT.getSimpleVT() <= MVT::i64 && SrcVT.getSimpleVT() >= MVT::i16 &&
7504 "Unknown SINT_TO_FP to lower!");
7506 // These are really Legal; return the operand so the caller accepts it as
7508 if (SrcVT == MVT::i32 && isScalarFPTypeInSSEReg(Op.getValueType()))
7510 if (SrcVT == MVT::i64 && isScalarFPTypeInSSEReg(Op.getValueType()) &&
7511 Subtarget->is64Bit()) {
7515 DebugLoc dl = Op.getDebugLoc();
7516 unsigned Size = SrcVT.getSizeInBits()/8;
7517 MachineFunction &MF = DAG.getMachineFunction();
7518 int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size, false);
7519 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
7520 SDValue Chain = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
7522 MachinePointerInfo::getFixedStack(SSFI),
7524 return BuildFILD(Op, SrcVT, Chain, StackSlot, DAG);
7527 SDValue X86TargetLowering::BuildFILD(SDValue Op, EVT SrcVT, SDValue Chain,
7529 SelectionDAG &DAG) const {
7531 DebugLoc DL = Op.getDebugLoc();
7533 bool useSSE = isScalarFPTypeInSSEReg(Op.getValueType());
7535 Tys = DAG.getVTList(MVT::f64, MVT::Other, MVT::Glue);
7537 Tys = DAG.getVTList(Op.getValueType(), MVT::Other);
7539 unsigned ByteSize = SrcVT.getSizeInBits()/8;
7541 FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(StackSlot);
7542 MachineMemOperand *MMO;
7544 int SSFI = FI->getIndex();
7546 DAG.getMachineFunction()
7547 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
7548 MachineMemOperand::MOLoad, ByteSize, ByteSize);
7550 MMO = cast<LoadSDNode>(StackSlot)->getMemOperand();
7551 StackSlot = StackSlot.getOperand(1);
7553 SDValue Ops[] = { Chain, StackSlot, DAG.getValueType(SrcVT) };
7554 SDValue Result = DAG.getMemIntrinsicNode(useSSE ? X86ISD::FILD_FLAG :
7556 Tys, Ops, array_lengthof(Ops),
7560 Chain = Result.getValue(1);
7561 SDValue InFlag = Result.getValue(2);
7563 // FIXME: Currently the FST is flagged to the FILD_FLAG. This
7564 // shouldn't be necessary except that RFP cannot be live across
7565 // multiple blocks. When stackifier is fixed, they can be uncoupled.
7566 MachineFunction &MF = DAG.getMachineFunction();
7567 unsigned SSFISize = Op.getValueType().getSizeInBits()/8;
7568 int SSFI = MF.getFrameInfo()->CreateStackObject(SSFISize, SSFISize, false);
7569 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
7570 Tys = DAG.getVTList(MVT::Other);
7572 Chain, Result, StackSlot, DAG.getValueType(Op.getValueType()), InFlag
7574 MachineMemOperand *MMO =
7575 DAG.getMachineFunction()
7576 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
7577 MachineMemOperand::MOStore, SSFISize, SSFISize);
7579 Chain = DAG.getMemIntrinsicNode(X86ISD::FST, DL, Tys,
7580 Ops, array_lengthof(Ops),
7581 Op.getValueType(), MMO);
7582 Result = DAG.getLoad(Op.getValueType(), DL, Chain, StackSlot,
7583 MachinePointerInfo::getFixedStack(SSFI),
7584 false, false, false, 0);
7590 // LowerUINT_TO_FP_i64 - 64-bit unsigned integer to double expansion.
7591 SDValue X86TargetLowering::LowerUINT_TO_FP_i64(SDValue Op,
7592 SelectionDAG &DAG) const {
7593 // This algorithm is not obvious. Here it is what we're trying to output:
7596 punpckldq (c0), %xmm0 // c0: (uint4){ 0x43300000U, 0x45300000U, 0U, 0U }
7597 subpd (c1), %xmm0 // c1: (double2){ 0x1.0p52, 0x1.0p52 * 0x1.0p32 }
7601 pshufd $0x4e, %xmm0, %xmm1
7606 DebugLoc dl = Op.getDebugLoc();
7607 LLVMContext *Context = DAG.getContext();
7609 // Build some magic constants.
7610 const uint32_t CV0[] = { 0x43300000, 0x45300000, 0, 0 };
7611 Constant *C0 = ConstantDataVector::get(*Context, CV0);
7612 SDValue CPIdx0 = DAG.getConstantPool(C0, getPointerTy(), 16);
7614 SmallVector<Constant*,2> CV1;
7616 ConstantFP::get(*Context, APFloat(APInt(64, 0x4330000000000000ULL))));
7618 ConstantFP::get(*Context, APFloat(APInt(64, 0x4530000000000000ULL))));
7619 Constant *C1 = ConstantVector::get(CV1);
7620 SDValue CPIdx1 = DAG.getConstantPool(C1, getPointerTy(), 16);
7622 // Load the 64-bit value into an XMM register.
7623 SDValue XR1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
7625 SDValue CLod0 = DAG.getLoad(MVT::v4i32, dl, DAG.getEntryNode(), CPIdx0,
7626 MachinePointerInfo::getConstantPool(),
7627 false, false, false, 16);
7628 SDValue Unpck1 = getUnpackl(DAG, dl, MVT::v4i32,
7629 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, XR1),
7632 SDValue CLod1 = DAG.getLoad(MVT::v2f64, dl, CLod0.getValue(1), CPIdx1,
7633 MachinePointerInfo::getConstantPool(),
7634 false, false, false, 16);
7635 SDValue XR2F = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Unpck1);
7636 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, XR2F, CLod1);
7639 if (Subtarget->hasSSE3()) {
7640 // FIXME: The 'haddpd' instruction may be slower than 'movhlps + addsd'.
7641 Result = DAG.getNode(X86ISD::FHADD, dl, MVT::v2f64, Sub, Sub);
7643 SDValue S2F = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Sub);
7644 SDValue Shuffle = getTargetShuffleNode(X86ISD::PSHUFD, dl, MVT::v4i32,
7646 Result = DAG.getNode(ISD::FADD, dl, MVT::v2f64,
7647 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Shuffle),
7651 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Result,
7652 DAG.getIntPtrConstant(0));
7655 // LowerUINT_TO_FP_i32 - 32-bit unsigned integer to float expansion.
7656 SDValue X86TargetLowering::LowerUINT_TO_FP_i32(SDValue Op,
7657 SelectionDAG &DAG) const {
7658 DebugLoc dl = Op.getDebugLoc();
7659 // FP constant to bias correct the final result.
7660 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL),
7663 // Load the 32-bit value into an XMM register.
7664 SDValue Load = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,
7667 // Zero out the upper parts of the register.
7668 Load = getShuffleVectorZeroOrUndef(Load, 0, true, Subtarget, DAG);
7670 Load = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
7671 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Load),
7672 DAG.getIntPtrConstant(0));
7674 // Or the load with the bias.
7675 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64,
7676 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
7677 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
7679 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
7680 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
7681 MVT::v2f64, Bias)));
7682 Or = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
7683 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Or),
7684 DAG.getIntPtrConstant(0));
7686 // Subtract the bias.
7687 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Or, Bias);
7689 // Handle final rounding.
7690 EVT DestVT = Op.getValueType();
7692 if (DestVT.bitsLT(MVT::f64))
7693 return DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub,
7694 DAG.getIntPtrConstant(0));
7695 if (DestVT.bitsGT(MVT::f64))
7696 return DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub);
7698 // Handle final rounding.
7702 SDValue X86TargetLowering::LowerUINT_TO_FP(SDValue Op,
7703 SelectionDAG &DAG) const {
7704 SDValue N0 = Op.getOperand(0);
7705 DebugLoc dl = Op.getDebugLoc();
7707 // Since UINT_TO_FP is legal (it's marked custom), dag combiner won't
7708 // optimize it to a SINT_TO_FP when the sign bit is known zero. Perform
7709 // the optimization here.
7710 if (DAG.SignBitIsZero(N0))
7711 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(), N0);
7713 EVT SrcVT = N0.getValueType();
7714 EVT DstVT = Op.getValueType();
7715 if (SrcVT == MVT::i64 && DstVT == MVT::f64 && X86ScalarSSEf64)
7716 return LowerUINT_TO_FP_i64(Op, DAG);
7717 if (SrcVT == MVT::i32 && X86ScalarSSEf64)
7718 return LowerUINT_TO_FP_i32(Op, DAG);
7719 if (Subtarget->is64Bit() && SrcVT == MVT::i64 && DstVT == MVT::f32)
7722 // Make a 64-bit buffer, and use it to build an FILD.
7723 SDValue StackSlot = DAG.CreateStackTemporary(MVT::i64);
7724 if (SrcVT == MVT::i32) {
7725 SDValue WordOff = DAG.getConstant(4, getPointerTy());
7726 SDValue OffsetSlot = DAG.getNode(ISD::ADD, dl,
7727 getPointerTy(), StackSlot, WordOff);
7728 SDValue Store1 = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
7729 StackSlot, MachinePointerInfo(),
7731 SDValue Store2 = DAG.getStore(Store1, dl, DAG.getConstant(0, MVT::i32),
7732 OffsetSlot, MachinePointerInfo(),
7734 SDValue Fild = BuildFILD(Op, MVT::i64, Store2, StackSlot, DAG);
7738 assert(SrcVT == MVT::i64 && "Unexpected type in UINT_TO_FP");
7739 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
7740 StackSlot, MachinePointerInfo(),
7742 // For i64 source, we need to add the appropriate power of 2 if the input
7743 // was negative. This is the same as the optimization in
7744 // DAGTypeLegalizer::ExpandIntOp_UNIT_TO_FP, and for it to be safe here,
7745 // we must be careful to do the computation in x87 extended precision, not
7746 // in SSE. (The generic code can't know it's OK to do this, or how to.)
7747 int SSFI = cast<FrameIndexSDNode>(StackSlot)->getIndex();
7748 MachineMemOperand *MMO =
7749 DAG.getMachineFunction()
7750 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
7751 MachineMemOperand::MOLoad, 8, 8);
7753 SDVTList Tys = DAG.getVTList(MVT::f80, MVT::Other);
7754 SDValue Ops[] = { Store, StackSlot, DAG.getValueType(MVT::i64) };
7755 SDValue Fild = DAG.getMemIntrinsicNode(X86ISD::FILD, dl, Tys, Ops, 3,
7758 APInt FF(32, 0x5F800000ULL);
7760 // Check whether the sign bit is set.
7761 SDValue SignSet = DAG.getSetCC(dl, getSetCCResultType(MVT::i64),
7762 Op.getOperand(0), DAG.getConstant(0, MVT::i64),
7765 // Build a 64 bit pair (0, FF) in the constant pool, with FF in the lo bits.
7766 SDValue FudgePtr = DAG.getConstantPool(
7767 ConstantInt::get(*DAG.getContext(), FF.zext(64)),
7770 // Get a pointer to FF if the sign bit was set, or to 0 otherwise.
7771 SDValue Zero = DAG.getIntPtrConstant(0);
7772 SDValue Four = DAG.getIntPtrConstant(4);
7773 SDValue Offset = DAG.getNode(ISD::SELECT, dl, Zero.getValueType(), SignSet,
7775 FudgePtr = DAG.getNode(ISD::ADD, dl, getPointerTy(), FudgePtr, Offset);
7777 // Load the value out, extending it from f32 to f80.
7778 // FIXME: Avoid the extend by constructing the right constant pool?
7779 SDValue Fudge = DAG.getExtLoad(ISD::EXTLOAD, dl, MVT::f80, DAG.getEntryNode(),
7780 FudgePtr, MachinePointerInfo::getConstantPool(),
7781 MVT::f32, false, false, 4);
7782 // Extend everything to 80 bits to force it to be done on x87.
7783 SDValue Add = DAG.getNode(ISD::FADD, dl, MVT::f80, Fild, Fudge);
7784 return DAG.getNode(ISD::FP_ROUND, dl, DstVT, Add, DAG.getIntPtrConstant(0));
7787 std::pair<SDValue,SDValue> X86TargetLowering::
7788 FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG, bool IsSigned, bool IsReplace) const {
7789 DebugLoc DL = Op.getDebugLoc();
7791 EVT DstTy = Op.getValueType();
7793 if (!IsSigned && !isIntegerTypeFTOL(DstTy)) {
7794 assert(DstTy == MVT::i32 && "Unexpected FP_TO_UINT");
7798 assert(DstTy.getSimpleVT() <= MVT::i64 &&
7799 DstTy.getSimpleVT() >= MVT::i16 &&
7800 "Unknown FP_TO_INT to lower!");
7802 // These are really Legal.
7803 if (DstTy == MVT::i32 &&
7804 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
7805 return std::make_pair(SDValue(), SDValue());
7806 if (Subtarget->is64Bit() &&
7807 DstTy == MVT::i64 &&
7808 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
7809 return std::make_pair(SDValue(), SDValue());
7811 // We lower FP->int64 either into FISTP64 followed by a load from a temporary
7812 // stack slot, or into the FTOL runtime function.
7813 MachineFunction &MF = DAG.getMachineFunction();
7814 unsigned MemSize = DstTy.getSizeInBits()/8;
7815 int SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
7816 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
7819 if (!IsSigned && isIntegerTypeFTOL(DstTy))
7820 Opc = X86ISD::WIN_FTOL;
7822 switch (DstTy.getSimpleVT().SimpleTy) {
7823 default: llvm_unreachable("Invalid FP_TO_SINT to lower!");
7824 case MVT::i16: Opc = X86ISD::FP_TO_INT16_IN_MEM; break;
7825 case MVT::i32: Opc = X86ISD::FP_TO_INT32_IN_MEM; break;
7826 case MVT::i64: Opc = X86ISD::FP_TO_INT64_IN_MEM; break;
7829 SDValue Chain = DAG.getEntryNode();
7830 SDValue Value = Op.getOperand(0);
7831 EVT TheVT = Op.getOperand(0).getValueType();
7832 // FIXME This causes a redundant load/store if the SSE-class value is already
7833 // in memory, such as if it is on the callstack.
7834 if (isScalarFPTypeInSSEReg(TheVT)) {
7835 assert(DstTy == MVT::i64 && "Invalid FP_TO_SINT to lower!");
7836 Chain = DAG.getStore(Chain, DL, Value, StackSlot,
7837 MachinePointerInfo::getFixedStack(SSFI),
7839 SDVTList Tys = DAG.getVTList(Op.getOperand(0).getValueType(), MVT::Other);
7841 Chain, StackSlot, DAG.getValueType(TheVT)
7844 MachineMemOperand *MMO =
7845 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
7846 MachineMemOperand::MOLoad, MemSize, MemSize);
7847 Value = DAG.getMemIntrinsicNode(X86ISD::FLD, DL, Tys, Ops, 3,
7849 Chain = Value.getValue(1);
7850 SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
7851 StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
7854 MachineMemOperand *MMO =
7855 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
7856 MachineMemOperand::MOStore, MemSize, MemSize);
7858 if (Opc != X86ISD::WIN_FTOL) {
7859 // Build the FP_TO_INT*_IN_MEM
7860 SDValue Ops[] = { Chain, Value, StackSlot };
7861 SDValue FIST = DAG.getMemIntrinsicNode(Opc, DL, DAG.getVTList(MVT::Other),
7862 Ops, 3, DstTy, MMO);
7863 return std::make_pair(FIST, StackSlot);
7865 SDValue ftol = DAG.getNode(X86ISD::WIN_FTOL, DL,
7866 DAG.getVTList(MVT::Other, MVT::Glue),
7868 SDValue eax = DAG.getCopyFromReg(ftol, DL, X86::EAX,
7869 MVT::i32, ftol.getValue(1));
7870 SDValue edx = DAG.getCopyFromReg(eax.getValue(1), DL, X86::EDX,
7871 MVT::i32, eax.getValue(2));
7872 SDValue Ops[] = { eax, edx };
7873 SDValue pair = IsReplace
7874 ? DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops, 2)
7875 : DAG.getMergeValues(Ops, 2, DL);
7876 return std::make_pair(pair, SDValue());
7880 SDValue X86TargetLowering::LowerFP_TO_SINT(SDValue Op,
7881 SelectionDAG &DAG) const {
7882 if (Op.getValueType().isVector())
7885 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG,
7886 /*IsSigned=*/ true, /*IsReplace=*/ false);
7887 SDValue FIST = Vals.first, StackSlot = Vals.second;
7888 // If FP_TO_INTHelper failed, the node is actually supposed to be Legal.
7889 if (FIST.getNode() == 0) return Op;
7891 if (StackSlot.getNode())
7893 return DAG.getLoad(Op.getValueType(), Op.getDebugLoc(),
7894 FIST, StackSlot, MachinePointerInfo(),
7895 false, false, false, 0);
7897 // The node is the result.
7901 SDValue X86TargetLowering::LowerFP_TO_UINT(SDValue Op,
7902 SelectionDAG &DAG) const {
7903 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG,
7904 /*IsSigned=*/ false, /*IsReplace=*/ false);
7905 SDValue FIST = Vals.first, StackSlot = Vals.second;
7906 assert(FIST.getNode() && "Unexpected failure");
7908 if (StackSlot.getNode())
7910 return DAG.getLoad(Op.getValueType(), Op.getDebugLoc(),
7911 FIST, StackSlot, MachinePointerInfo(),
7912 false, false, false, 0);
7914 // The node is the result.
7918 SDValue X86TargetLowering::LowerFABS(SDValue Op,
7919 SelectionDAG &DAG) const {
7920 LLVMContext *Context = DAG.getContext();
7921 DebugLoc dl = Op.getDebugLoc();
7922 EVT VT = Op.getValueType();
7925 EltVT = VT.getVectorElementType();
7927 if (EltVT == MVT::f64) {
7928 C = ConstantVector::getSplat(2,
7929 ConstantFP::get(*Context, APFloat(APInt(64, ~(1ULL << 63)))));
7931 C = ConstantVector::getSplat(4,
7932 ConstantFP::get(*Context, APFloat(APInt(32, ~(1U << 31)))));
7934 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
7935 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
7936 MachinePointerInfo::getConstantPool(),
7937 false, false, false, 16);
7938 return DAG.getNode(X86ISD::FAND, dl, VT, Op.getOperand(0), Mask);
7941 SDValue X86TargetLowering::LowerFNEG(SDValue Op, SelectionDAG &DAG) const {
7942 LLVMContext *Context = DAG.getContext();
7943 DebugLoc dl = Op.getDebugLoc();
7944 EVT VT = Op.getValueType();
7946 unsigned NumElts = VT == MVT::f64 ? 2 : 4;
7947 if (VT.isVector()) {
7948 EltVT = VT.getVectorElementType();
7949 NumElts = VT.getVectorNumElements();
7952 if (EltVT == MVT::f64)
7953 C = ConstantFP::get(*Context, APFloat(APInt(64, 1ULL << 63)));
7955 C = ConstantFP::get(*Context, APFloat(APInt(32, 1U << 31)));
7956 C = ConstantVector::getSplat(NumElts, C);
7957 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
7958 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
7959 MachinePointerInfo::getConstantPool(),
7960 false, false, false, 16);
7961 if (VT.isVector()) {
7962 MVT XORVT = VT.getSizeInBits() == 128 ? MVT::v2i64 : MVT::v4i64;
7963 return DAG.getNode(ISD::BITCAST, dl, VT,
7964 DAG.getNode(ISD::XOR, dl, XORVT,
7965 DAG.getNode(ISD::BITCAST, dl, XORVT,
7967 DAG.getNode(ISD::BITCAST, dl, XORVT, Mask)));
7970 return DAG.getNode(X86ISD::FXOR, dl, VT, Op.getOperand(0), Mask);
7973 SDValue X86TargetLowering::LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const {
7974 LLVMContext *Context = DAG.getContext();
7975 SDValue Op0 = Op.getOperand(0);
7976 SDValue Op1 = Op.getOperand(1);
7977 DebugLoc dl = Op.getDebugLoc();
7978 EVT VT = Op.getValueType();
7979 EVT SrcVT = Op1.getValueType();
7981 // If second operand is smaller, extend it first.
7982 if (SrcVT.bitsLT(VT)) {
7983 Op1 = DAG.getNode(ISD::FP_EXTEND, dl, VT, Op1);
7986 // And if it is bigger, shrink it first.
7987 if (SrcVT.bitsGT(VT)) {
7988 Op1 = DAG.getNode(ISD::FP_ROUND, dl, VT, Op1, DAG.getIntPtrConstant(1));
7992 // At this point the operands and the result should have the same
7993 // type, and that won't be f80 since that is not custom lowered.
7995 // First get the sign bit of second operand.
7996 SmallVector<Constant*,4> CV;
7997 if (SrcVT == MVT::f64) {
7998 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, 1ULL << 63))));
7999 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, 0))));
8001 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 1U << 31))));
8002 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
8003 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
8004 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
8006 Constant *C = ConstantVector::get(CV);
8007 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
8008 SDValue Mask1 = DAG.getLoad(SrcVT, dl, DAG.getEntryNode(), CPIdx,
8009 MachinePointerInfo::getConstantPool(),
8010 false, false, false, 16);
8011 SDValue SignBit = DAG.getNode(X86ISD::FAND, dl, SrcVT, Op1, Mask1);
8013 // Shift sign bit right or left if the two operands have different types.
8014 if (SrcVT.bitsGT(VT)) {
8015 // Op0 is MVT::f32, Op1 is MVT::f64.
8016 SignBit = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f64, SignBit);
8017 SignBit = DAG.getNode(X86ISD::FSRL, dl, MVT::v2f64, SignBit,
8018 DAG.getConstant(32, MVT::i32));
8019 SignBit = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, SignBit);
8020 SignBit = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f32, SignBit,
8021 DAG.getIntPtrConstant(0));
8024 // Clear first operand sign bit.
8026 if (VT == MVT::f64) {
8027 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, ~(1ULL << 63)))));
8028 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, 0))));
8030 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, ~(1U << 31)))));
8031 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
8032 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
8033 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
8035 C = ConstantVector::get(CV);
8036 CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
8037 SDValue Mask2 = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
8038 MachinePointerInfo::getConstantPool(),
8039 false, false, false, 16);
8040 SDValue Val = DAG.getNode(X86ISD::FAND, dl, VT, Op0, Mask2);
8042 // Or the value with the sign bit.
8043 return DAG.getNode(X86ISD::FOR, dl, VT, Val, SignBit);
8046 SDValue X86TargetLowering::LowerFGETSIGN(SDValue Op, SelectionDAG &DAG) const {
8047 SDValue N0 = Op.getOperand(0);
8048 DebugLoc dl = Op.getDebugLoc();
8049 EVT VT = Op.getValueType();
8051 // Lower ISD::FGETSIGN to (AND (X86ISD::FGETSIGNx86 ...) 1).
8052 SDValue xFGETSIGN = DAG.getNode(X86ISD::FGETSIGNx86, dl, VT, N0,
8053 DAG.getConstant(1, VT));
8054 return DAG.getNode(ISD::AND, dl, VT, xFGETSIGN, DAG.getConstant(1, VT));
8057 /// Emit nodes that will be selected as "test Op0,Op0", or something
8059 SDValue X86TargetLowering::EmitTest(SDValue Op, unsigned X86CC,
8060 SelectionDAG &DAG) const {
8061 DebugLoc dl = Op.getDebugLoc();
8063 // CF and OF aren't always set the way we want. Determine which
8064 // of these we need.
8065 bool NeedCF = false;
8066 bool NeedOF = false;
8069 case X86::COND_A: case X86::COND_AE:
8070 case X86::COND_B: case X86::COND_BE:
8073 case X86::COND_G: case X86::COND_GE:
8074 case X86::COND_L: case X86::COND_LE:
8075 case X86::COND_O: case X86::COND_NO:
8080 // See if we can use the EFLAGS value from the operand instead of
8081 // doing a separate TEST. TEST always sets OF and CF to 0, so unless
8082 // we prove that the arithmetic won't overflow, we can't use OF or CF.
8083 if (Op.getResNo() != 0 || NeedOF || NeedCF)
8084 // Emit a CMP with 0, which is the TEST pattern.
8085 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
8086 DAG.getConstant(0, Op.getValueType()));
8088 unsigned Opcode = 0;
8089 unsigned NumOperands = 0;
8090 switch (Op.getNode()->getOpcode()) {
8092 // Due to an isel shortcoming, be conservative if this add is likely to be
8093 // selected as part of a load-modify-store instruction. When the root node
8094 // in a match is a store, isel doesn't know how to remap non-chain non-flag
8095 // uses of other nodes in the match, such as the ADD in this case. This
8096 // leads to the ADD being left around and reselected, with the result being
8097 // two adds in the output. Alas, even if none our users are stores, that
8098 // doesn't prove we're O.K. Ergo, if we have any parents that aren't
8099 // CopyToReg or SETCC, eschew INC/DEC. A better fix seems to require
8100 // climbing the DAG back to the root, and it doesn't seem to be worth the
8102 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
8103 UE = Op.getNode()->use_end(); UI != UE; ++UI)
8104 if (UI->getOpcode() != ISD::CopyToReg &&
8105 UI->getOpcode() != ISD::SETCC &&
8106 UI->getOpcode() != ISD::STORE)
8109 if (ConstantSDNode *C =
8110 dyn_cast<ConstantSDNode>(Op.getNode()->getOperand(1))) {
8111 // An add of one will be selected as an INC.
8112 if (C->getAPIntValue() == 1) {
8113 Opcode = X86ISD::INC;
8118 // An add of negative one (subtract of one) will be selected as a DEC.
8119 if (C->getAPIntValue().isAllOnesValue()) {
8120 Opcode = X86ISD::DEC;
8126 // Otherwise use a regular EFLAGS-setting add.
8127 Opcode = X86ISD::ADD;
8131 // If the primary and result isn't used, don't bother using X86ISD::AND,
8132 // because a TEST instruction will be better.
8133 bool NonFlagUse = false;
8134 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
8135 UE = Op.getNode()->use_end(); UI != UE; ++UI) {
8137 unsigned UOpNo = UI.getOperandNo();
8138 if (User->getOpcode() == ISD::TRUNCATE && User->hasOneUse()) {
8139 // Look pass truncate.
8140 UOpNo = User->use_begin().getOperandNo();
8141 User = *User->use_begin();
8144 if (User->getOpcode() != ISD::BRCOND &&
8145 User->getOpcode() != ISD::SETCC &&
8146 (User->getOpcode() != ISD::SELECT || UOpNo != 0)) {
8159 // Due to the ISEL shortcoming noted above, be conservative if this op is
8160 // likely to be selected as part of a load-modify-store instruction.
8161 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
8162 UE = Op.getNode()->use_end(); UI != UE; ++UI)
8163 if (UI->getOpcode() == ISD::STORE)
8166 // Otherwise use a regular EFLAGS-setting instruction.
8167 switch (Op.getNode()->getOpcode()) {
8168 default: llvm_unreachable("unexpected operator!");
8169 case ISD::SUB: Opcode = X86ISD::SUB; break;
8170 case ISD::OR: Opcode = X86ISD::OR; break;
8171 case ISD::XOR: Opcode = X86ISD::XOR; break;
8172 case ISD::AND: Opcode = X86ISD::AND; break;
8184 return SDValue(Op.getNode(), 1);
8191 // Emit a CMP with 0, which is the TEST pattern.
8192 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
8193 DAG.getConstant(0, Op.getValueType()));
8195 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
8196 SmallVector<SDValue, 4> Ops;
8197 for (unsigned i = 0; i != NumOperands; ++i)
8198 Ops.push_back(Op.getOperand(i));
8200 SDValue New = DAG.getNode(Opcode, dl, VTs, &Ops[0], NumOperands);
8201 DAG.ReplaceAllUsesWith(Op, New);
8202 return SDValue(New.getNode(), 1);
8205 /// Emit nodes that will be selected as "cmp Op0,Op1", or something
8207 SDValue X86TargetLowering::EmitCmp(SDValue Op0, SDValue Op1, unsigned X86CC,
8208 SelectionDAG &DAG) const {
8209 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op1))
8210 if (C->getAPIntValue() == 0)
8211 return EmitTest(Op0, X86CC, DAG);
8213 DebugLoc dl = Op0.getDebugLoc();
8214 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op0, Op1);
8217 /// LowerToBT - Result of 'and' is compared against zero. Turn it into a BT node
8218 /// if it's possible.
8219 SDValue X86TargetLowering::LowerToBT(SDValue And, ISD::CondCode CC,
8220 DebugLoc dl, SelectionDAG &DAG) const {
8221 SDValue Op0 = And.getOperand(0);
8222 SDValue Op1 = And.getOperand(1);
8223 if (Op0.getOpcode() == ISD::TRUNCATE)
8224 Op0 = Op0.getOperand(0);
8225 if (Op1.getOpcode() == ISD::TRUNCATE)
8226 Op1 = Op1.getOperand(0);
8229 if (Op1.getOpcode() == ISD::SHL)
8230 std::swap(Op0, Op1);
8231 if (Op0.getOpcode() == ISD::SHL) {
8232 if (ConstantSDNode *And00C = dyn_cast<ConstantSDNode>(Op0.getOperand(0)))
8233 if (And00C->getZExtValue() == 1) {
8234 // If we looked past a truncate, check that it's only truncating away
8236 unsigned BitWidth = Op0.getValueSizeInBits();
8237 unsigned AndBitWidth = And.getValueSizeInBits();
8238 if (BitWidth > AndBitWidth) {
8240 DAG.ComputeMaskedBits(Op0, Zeros, Ones);
8241 if (Zeros.countLeadingOnes() < BitWidth - AndBitWidth)
8245 RHS = Op0.getOperand(1);
8247 } else if (Op1.getOpcode() == ISD::Constant) {
8248 ConstantSDNode *AndRHS = cast<ConstantSDNode>(Op1);
8249 uint64_t AndRHSVal = AndRHS->getZExtValue();
8250 SDValue AndLHS = Op0;
8252 if (AndRHSVal == 1 && AndLHS.getOpcode() == ISD::SRL) {
8253 LHS = AndLHS.getOperand(0);
8254 RHS = AndLHS.getOperand(1);
8257 // Use BT if the immediate can't be encoded in a TEST instruction.
8258 if (!isUInt<32>(AndRHSVal) && isPowerOf2_64(AndRHSVal)) {
8260 RHS = DAG.getConstant(Log2_64_Ceil(AndRHSVal), LHS.getValueType());
8264 if (LHS.getNode()) {
8265 // If LHS is i8, promote it to i32 with any_extend. There is no i8 BT
8266 // instruction. Since the shift amount is in-range-or-undefined, we know
8267 // that doing a bittest on the i32 value is ok. We extend to i32 because
8268 // the encoding for the i16 version is larger than the i32 version.
8269 // Also promote i16 to i32 for performance / code size reason.
8270 if (LHS.getValueType() == MVT::i8 ||
8271 LHS.getValueType() == MVT::i16)
8272 LHS = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, LHS);
8274 // If the operand types disagree, extend the shift amount to match. Since
8275 // BT ignores high bits (like shifts) we can use anyextend.
8276 if (LHS.getValueType() != RHS.getValueType())
8277 RHS = DAG.getNode(ISD::ANY_EXTEND, dl, LHS.getValueType(), RHS);
8279 SDValue BT = DAG.getNode(X86ISD::BT, dl, MVT::i32, LHS, RHS);
8280 unsigned Cond = CC == ISD::SETEQ ? X86::COND_AE : X86::COND_B;
8281 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
8282 DAG.getConstant(Cond, MVT::i8), BT);
8288 SDValue X86TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
8290 if (Op.getValueType().isVector()) return LowerVSETCC(Op, DAG);
8292 assert(Op.getValueType() == MVT::i8 && "SetCC type must be 8-bit integer");
8293 SDValue Op0 = Op.getOperand(0);
8294 SDValue Op1 = Op.getOperand(1);
8295 DebugLoc dl = Op.getDebugLoc();
8296 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
8298 // Optimize to BT if possible.
8299 // Lower (X & (1 << N)) == 0 to BT(X, N).
8300 // Lower ((X >>u N) & 1) != 0 to BT(X, N).
8301 // Lower ((X >>s N) & 1) != 0 to BT(X, N).
8302 if (Op0.getOpcode() == ISD::AND && Op0.hasOneUse() &&
8303 Op1.getOpcode() == ISD::Constant &&
8304 cast<ConstantSDNode>(Op1)->isNullValue() &&
8305 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
8306 SDValue NewSetCC = LowerToBT(Op0, CC, dl, DAG);
8307 if (NewSetCC.getNode())
8311 // Look for X == 0, X == 1, X != 0, or X != 1. We can simplify some forms of
8313 if (Op1.getOpcode() == ISD::Constant &&
8314 (cast<ConstantSDNode>(Op1)->getZExtValue() == 1 ||
8315 cast<ConstantSDNode>(Op1)->isNullValue()) &&
8316 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
8318 // If the input is a setcc, then reuse the input setcc or use a new one with
8319 // the inverted condition.
8320 if (Op0.getOpcode() == X86ISD::SETCC) {
8321 X86::CondCode CCode = (X86::CondCode)Op0.getConstantOperandVal(0);
8322 bool Invert = (CC == ISD::SETNE) ^
8323 cast<ConstantSDNode>(Op1)->isNullValue();
8324 if (!Invert) return Op0;
8326 CCode = X86::GetOppositeBranchCondition(CCode);
8327 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
8328 DAG.getConstant(CCode, MVT::i8), Op0.getOperand(1));
8332 bool isFP = Op1.getValueType().isFloatingPoint();
8333 unsigned X86CC = TranslateX86CC(CC, isFP, Op0, Op1, DAG);
8334 if (X86CC == X86::COND_INVALID)
8337 SDValue EFLAGS = EmitCmp(Op0, Op1, X86CC, DAG);
8338 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
8339 DAG.getConstant(X86CC, MVT::i8), EFLAGS);
8342 // Lower256IntVSETCC - Break a VSETCC 256-bit integer VSETCC into two new 128
8343 // ones, and then concatenate the result back.
8344 static SDValue Lower256IntVSETCC(SDValue Op, SelectionDAG &DAG) {
8345 EVT VT = Op.getValueType();
8347 assert(VT.getSizeInBits() == 256 && Op.getOpcode() == ISD::SETCC &&
8348 "Unsupported value type for operation");
8350 int NumElems = VT.getVectorNumElements();
8351 DebugLoc dl = Op.getDebugLoc();
8352 SDValue CC = Op.getOperand(2);
8354 // Extract the LHS vectors
8355 SDValue LHS = Op.getOperand(0);
8356 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
8357 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
8359 // Extract the RHS vectors
8360 SDValue RHS = Op.getOperand(1);
8361 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, dl);
8362 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, dl);
8364 // Issue the operation on the smaller types and concatenate the result back
8365 MVT EltVT = VT.getVectorElementType().getSimpleVT();
8366 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
8367 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
8368 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1, CC),
8369 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2, CC));
8373 SDValue X86TargetLowering::LowerVSETCC(SDValue Op, SelectionDAG &DAG) const {
8375 SDValue Op0 = Op.getOperand(0);
8376 SDValue Op1 = Op.getOperand(1);
8377 SDValue CC = Op.getOperand(2);
8378 EVT VT = Op.getValueType();
8379 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
8380 bool isFP = Op.getOperand(1).getValueType().isFloatingPoint();
8381 DebugLoc dl = Op.getDebugLoc();
8385 EVT EltVT = Op0.getValueType().getVectorElementType();
8386 assert(EltVT == MVT::f32 || EltVT == MVT::f64); (void)EltVT;
8390 // SSE Condition code mapping:
8399 switch (SetCCOpcode) {
8402 case ISD::SETEQ: SSECC = 0; break;
8404 case ISD::SETGT: Swap = true; // Fallthrough
8406 case ISD::SETOLT: SSECC = 1; break;
8408 case ISD::SETGE: Swap = true; // Fallthrough
8410 case ISD::SETOLE: SSECC = 2; break;
8411 case ISD::SETUO: SSECC = 3; break;
8413 case ISD::SETNE: SSECC = 4; break;
8414 case ISD::SETULE: Swap = true;
8415 case ISD::SETUGE: SSECC = 5; break;
8416 case ISD::SETULT: Swap = true;
8417 case ISD::SETUGT: SSECC = 6; break;
8418 case ISD::SETO: SSECC = 7; break;
8421 std::swap(Op0, Op1);
8423 // In the two special cases we can't handle, emit two comparisons.
8425 if (SetCCOpcode == ISD::SETUEQ) {
8427 UNORD = DAG.getNode(X86ISD::CMPP, dl, VT, Op0, Op1,
8428 DAG.getConstant(3, MVT::i8));
8429 EQ = DAG.getNode(X86ISD::CMPP, dl, VT, Op0, Op1,
8430 DAG.getConstant(0, MVT::i8));
8431 return DAG.getNode(ISD::OR, dl, VT, UNORD, EQ);
8433 if (SetCCOpcode == ISD::SETONE) {
8435 ORD = DAG.getNode(X86ISD::CMPP, dl, VT, Op0, Op1,
8436 DAG.getConstant(7, MVT::i8));
8437 NEQ = DAG.getNode(X86ISD::CMPP, dl, VT, Op0, Op1,
8438 DAG.getConstant(4, MVT::i8));
8439 return DAG.getNode(ISD::AND, dl, VT, ORD, NEQ);
8441 llvm_unreachable("Illegal FP comparison");
8443 // Handle all other FP comparisons here.
8444 return DAG.getNode(X86ISD::CMPP, dl, VT, Op0, Op1,
8445 DAG.getConstant(SSECC, MVT::i8));
8448 // Break 256-bit integer vector compare into smaller ones.
8449 if (VT.getSizeInBits() == 256 && !Subtarget->hasAVX2())
8450 return Lower256IntVSETCC(Op, DAG);
8452 // We are handling one of the integer comparisons here. Since SSE only has
8453 // GT and EQ comparisons for integer, swapping operands and multiple
8454 // operations may be required for some comparisons.
8456 bool Swap = false, Invert = false, FlipSigns = false;
8458 switch (SetCCOpcode) {
8460 case ISD::SETNE: Invert = true;
8461 case ISD::SETEQ: Opc = X86ISD::PCMPEQ; break;
8462 case ISD::SETLT: Swap = true;
8463 case ISD::SETGT: Opc = X86ISD::PCMPGT; break;
8464 case ISD::SETGE: Swap = true;
8465 case ISD::SETLE: Opc = X86ISD::PCMPGT; Invert = true; break;
8466 case ISD::SETULT: Swap = true;
8467 case ISD::SETUGT: Opc = X86ISD::PCMPGT; FlipSigns = true; break;
8468 case ISD::SETUGE: Swap = true;
8469 case ISD::SETULE: Opc = X86ISD::PCMPGT; FlipSigns = true; Invert = true; break;
8472 std::swap(Op0, Op1);
8474 // Check that the operation in question is available (most are plain SSE2,
8475 // but PCMPGTQ and PCMPEQQ have different requirements).
8476 if (Opc == X86ISD::PCMPGT && VT == MVT::v2i64 && !Subtarget->hasSSE42())
8478 if (Opc == X86ISD::PCMPEQ && VT == MVT::v2i64 && !Subtarget->hasSSE41())
8481 // Since SSE has no unsigned integer comparisons, we need to flip the sign
8482 // bits of the inputs before performing those operations.
8484 EVT EltVT = VT.getVectorElementType();
8485 SDValue SignBit = DAG.getConstant(APInt::getSignBit(EltVT.getSizeInBits()),
8487 std::vector<SDValue> SignBits(VT.getVectorNumElements(), SignBit);
8488 SDValue SignVec = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &SignBits[0],
8490 Op0 = DAG.getNode(ISD::XOR, dl, VT, Op0, SignVec);
8491 Op1 = DAG.getNode(ISD::XOR, dl, VT, Op1, SignVec);
8494 SDValue Result = DAG.getNode(Opc, dl, VT, Op0, Op1);
8496 // If the logical-not of the result is required, perform that now.
8498 Result = DAG.getNOT(dl, Result, VT);
8503 // isX86LogicalCmp - Return true if opcode is a X86 logical comparison.
8504 static bool isX86LogicalCmp(SDValue Op) {
8505 unsigned Opc = Op.getNode()->getOpcode();
8506 if (Opc == X86ISD::CMP || Opc == X86ISD::COMI || Opc == X86ISD::UCOMI)
8508 if (Op.getResNo() == 1 &&
8509 (Opc == X86ISD::ADD ||
8510 Opc == X86ISD::SUB ||
8511 Opc == X86ISD::ADC ||
8512 Opc == X86ISD::SBB ||
8513 Opc == X86ISD::SMUL ||
8514 Opc == X86ISD::UMUL ||
8515 Opc == X86ISD::INC ||
8516 Opc == X86ISD::DEC ||
8517 Opc == X86ISD::OR ||
8518 Opc == X86ISD::XOR ||
8519 Opc == X86ISD::AND))
8522 if (Op.getResNo() == 2 && Opc == X86ISD::UMUL)
8528 static bool isZero(SDValue V) {
8529 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V);
8530 return C && C->isNullValue();
8533 static bool isAllOnes(SDValue V) {
8534 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V);
8535 return C && C->isAllOnesValue();
8538 SDValue X86TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {
8539 bool addTest = true;
8540 SDValue Cond = Op.getOperand(0);
8541 SDValue Op1 = Op.getOperand(1);
8542 SDValue Op2 = Op.getOperand(2);
8543 DebugLoc DL = Op.getDebugLoc();
8546 if (Cond.getOpcode() == ISD::SETCC) {
8547 SDValue NewCond = LowerSETCC(Cond, DAG);
8548 if (NewCond.getNode())
8552 // (select (x == 0), -1, y) -> (sign_bit (x - 1)) | y
8553 // (select (x == 0), y, -1) -> ~(sign_bit (x - 1)) | y
8554 // (select (x != 0), y, -1) -> (sign_bit (x - 1)) | y
8555 // (select (x != 0), -1, y) -> ~(sign_bit (x - 1)) | y
8556 if (Cond.getOpcode() == X86ISD::SETCC &&
8557 Cond.getOperand(1).getOpcode() == X86ISD::CMP &&
8558 isZero(Cond.getOperand(1).getOperand(1))) {
8559 SDValue Cmp = Cond.getOperand(1);
8561 unsigned CondCode =cast<ConstantSDNode>(Cond.getOperand(0))->getZExtValue();
8563 if ((isAllOnes(Op1) || isAllOnes(Op2)) &&
8564 (CondCode == X86::COND_E || CondCode == X86::COND_NE)) {
8565 SDValue Y = isAllOnes(Op2) ? Op1 : Op2;
8567 SDValue CmpOp0 = Cmp.getOperand(0);
8568 Cmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32,
8569 CmpOp0, DAG.getConstant(1, CmpOp0.getValueType()));
8571 SDValue Res = // Res = 0 or -1.
8572 DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
8573 DAG.getConstant(X86::COND_B, MVT::i8), Cmp);
8575 if (isAllOnes(Op1) != (CondCode == X86::COND_E))
8576 Res = DAG.getNOT(DL, Res, Res.getValueType());
8578 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(Op2);
8579 if (N2C == 0 || !N2C->isNullValue())
8580 Res = DAG.getNode(ISD::OR, DL, Res.getValueType(), Res, Y);
8585 // Look past (and (setcc_carry (cmp ...)), 1).
8586 if (Cond.getOpcode() == ISD::AND &&
8587 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
8588 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
8589 if (C && C->getAPIntValue() == 1)
8590 Cond = Cond.getOperand(0);
8593 // If condition flag is set by a X86ISD::CMP, then use it as the condition
8594 // setting operand in place of the X86ISD::SETCC.
8595 unsigned CondOpcode = Cond.getOpcode();
8596 if (CondOpcode == X86ISD::SETCC ||
8597 CondOpcode == X86ISD::SETCC_CARRY) {
8598 CC = Cond.getOperand(0);
8600 SDValue Cmp = Cond.getOperand(1);
8601 unsigned Opc = Cmp.getOpcode();
8602 EVT VT = Op.getValueType();
8604 bool IllegalFPCMov = false;
8605 if (VT.isFloatingPoint() && !VT.isVector() &&
8606 !isScalarFPTypeInSSEReg(VT)) // FPStack?
8607 IllegalFPCMov = !hasFPCMov(cast<ConstantSDNode>(CC)->getSExtValue());
8609 if ((isX86LogicalCmp(Cmp) && !IllegalFPCMov) ||
8610 Opc == X86ISD::BT) { // FIXME
8614 } else if (CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO ||
8615 CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO ||
8616 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) &&
8617 Cond.getOperand(0).getValueType() != MVT::i8)) {
8618 SDValue LHS = Cond.getOperand(0);
8619 SDValue RHS = Cond.getOperand(1);
8623 switch (CondOpcode) {
8624 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break;
8625 case ISD::SADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break;
8626 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break;
8627 case ISD::SSUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break;
8628 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break;
8629 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break;
8630 default: llvm_unreachable("unexpected overflowing operator");
8632 if (CondOpcode == ISD::UMULO)
8633 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(),
8636 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
8638 SDValue X86Op = DAG.getNode(X86Opcode, DL, VTs, LHS, RHS);
8640 if (CondOpcode == ISD::UMULO)
8641 Cond = X86Op.getValue(2);
8643 Cond = X86Op.getValue(1);
8645 CC = DAG.getConstant(X86Cond, MVT::i8);
8650 // Look pass the truncate.
8651 if (Cond.getOpcode() == ISD::TRUNCATE)
8652 Cond = Cond.getOperand(0);
8654 // We know the result of AND is compared against zero. Try to match
8656 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
8657 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, DL, DAG);
8658 if (NewSetCC.getNode()) {
8659 CC = NewSetCC.getOperand(0);
8660 Cond = NewSetCC.getOperand(1);
8667 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
8668 Cond = EmitTest(Cond, X86::COND_NE, DAG);
8671 // a < b ? -1 : 0 -> RES = ~setcc_carry
8672 // a < b ? 0 : -1 -> RES = setcc_carry
8673 // a >= b ? -1 : 0 -> RES = setcc_carry
8674 // a >= b ? 0 : -1 -> RES = ~setcc_carry
8675 if (Cond.getOpcode() == X86ISD::CMP) {
8676 unsigned CondCode = cast<ConstantSDNode>(CC)->getZExtValue();
8678 if ((CondCode == X86::COND_AE || CondCode == X86::COND_B) &&
8679 (isAllOnes(Op1) || isAllOnes(Op2)) && (isZero(Op1) || isZero(Op2))) {
8680 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
8681 DAG.getConstant(X86::COND_B, MVT::i8), Cond);
8682 if (isAllOnes(Op1) != (CondCode == X86::COND_B))
8683 return DAG.getNOT(DL, Res, Res.getValueType());
8688 // X86ISD::CMOV means set the result (which is operand 1) to the RHS if
8689 // condition is true.
8690 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue);
8691 SDValue Ops[] = { Op2, Op1, CC, Cond };
8692 return DAG.getNode(X86ISD::CMOV, DL, VTs, Ops, array_lengthof(Ops));
8695 // isAndOrOfSingleUseSetCCs - Return true if node is an ISD::AND or
8696 // ISD::OR of two X86ISD::SETCC nodes each of which has no other use apart
8697 // from the AND / OR.
8698 static bool isAndOrOfSetCCs(SDValue Op, unsigned &Opc) {
8699 Opc = Op.getOpcode();
8700 if (Opc != ISD::OR && Opc != ISD::AND)
8702 return (Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
8703 Op.getOperand(0).hasOneUse() &&
8704 Op.getOperand(1).getOpcode() == X86ISD::SETCC &&
8705 Op.getOperand(1).hasOneUse());
8708 // isXor1OfSetCC - Return true if node is an ISD::XOR of a X86ISD::SETCC and
8709 // 1 and that the SETCC node has a single use.
8710 static bool isXor1OfSetCC(SDValue Op) {
8711 if (Op.getOpcode() != ISD::XOR)
8713 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
8714 if (N1C && N1C->getAPIntValue() == 1) {
8715 return Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
8716 Op.getOperand(0).hasOneUse();
8721 SDValue X86TargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) const {
8722 bool addTest = true;
8723 SDValue Chain = Op.getOperand(0);
8724 SDValue Cond = Op.getOperand(1);
8725 SDValue Dest = Op.getOperand(2);
8726 DebugLoc dl = Op.getDebugLoc();
8728 bool Inverted = false;
8730 if (Cond.getOpcode() == ISD::SETCC) {
8731 // Check for setcc([su]{add,sub,mul}o == 0).
8732 if (cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETEQ &&
8733 isa<ConstantSDNode>(Cond.getOperand(1)) &&
8734 cast<ConstantSDNode>(Cond.getOperand(1))->isNullValue() &&
8735 Cond.getOperand(0).getResNo() == 1 &&
8736 (Cond.getOperand(0).getOpcode() == ISD::SADDO ||
8737 Cond.getOperand(0).getOpcode() == ISD::UADDO ||
8738 Cond.getOperand(0).getOpcode() == ISD::SSUBO ||
8739 Cond.getOperand(0).getOpcode() == ISD::USUBO ||
8740 Cond.getOperand(0).getOpcode() == ISD::SMULO ||
8741 Cond.getOperand(0).getOpcode() == ISD::UMULO)) {
8743 Cond = Cond.getOperand(0);
8745 SDValue NewCond = LowerSETCC(Cond, DAG);
8746 if (NewCond.getNode())
8751 // FIXME: LowerXALUO doesn't handle these!!
8752 else if (Cond.getOpcode() == X86ISD::ADD ||
8753 Cond.getOpcode() == X86ISD::SUB ||
8754 Cond.getOpcode() == X86ISD::SMUL ||
8755 Cond.getOpcode() == X86ISD::UMUL)
8756 Cond = LowerXALUO(Cond, DAG);
8759 // Look pass (and (setcc_carry (cmp ...)), 1).
8760 if (Cond.getOpcode() == ISD::AND &&
8761 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
8762 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
8763 if (C && C->getAPIntValue() == 1)
8764 Cond = Cond.getOperand(0);
8767 // If condition flag is set by a X86ISD::CMP, then use it as the condition
8768 // setting operand in place of the X86ISD::SETCC.
8769 unsigned CondOpcode = Cond.getOpcode();
8770 if (CondOpcode == X86ISD::SETCC ||
8771 CondOpcode == X86ISD::SETCC_CARRY) {
8772 CC = Cond.getOperand(0);
8774 SDValue Cmp = Cond.getOperand(1);
8775 unsigned Opc = Cmp.getOpcode();
8776 // FIXME: WHY THE SPECIAL CASING OF LogicalCmp??
8777 if (isX86LogicalCmp(Cmp) || Opc == X86ISD::BT) {
8781 switch (cast<ConstantSDNode>(CC)->getZExtValue()) {
8785 // These can only come from an arithmetic instruction with overflow,
8786 // e.g. SADDO, UADDO.
8787 Cond = Cond.getNode()->getOperand(1);
8793 CondOpcode = Cond.getOpcode();
8794 if (CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO ||
8795 CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO ||
8796 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) &&
8797 Cond.getOperand(0).getValueType() != MVT::i8)) {
8798 SDValue LHS = Cond.getOperand(0);
8799 SDValue RHS = Cond.getOperand(1);
8803 switch (CondOpcode) {
8804 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break;
8805 case ISD::SADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break;
8806 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break;
8807 case ISD::SSUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break;
8808 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break;
8809 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break;
8810 default: llvm_unreachable("unexpected overflowing operator");
8813 X86Cond = X86::GetOppositeBranchCondition((X86::CondCode)X86Cond);
8814 if (CondOpcode == ISD::UMULO)
8815 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(),
8818 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
8820 SDValue X86Op = DAG.getNode(X86Opcode, dl, VTs, LHS, RHS);
8822 if (CondOpcode == ISD::UMULO)
8823 Cond = X86Op.getValue(2);
8825 Cond = X86Op.getValue(1);
8827 CC = DAG.getConstant(X86Cond, MVT::i8);
8831 if (Cond.hasOneUse() && isAndOrOfSetCCs(Cond, CondOpc)) {
8832 SDValue Cmp = Cond.getOperand(0).getOperand(1);
8833 if (CondOpc == ISD::OR) {
8834 // Also, recognize the pattern generated by an FCMP_UNE. We can emit
8835 // two branches instead of an explicit OR instruction with a
8837 if (Cmp == Cond.getOperand(1).getOperand(1) &&
8838 isX86LogicalCmp(Cmp)) {
8839 CC = Cond.getOperand(0).getOperand(0);
8840 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
8841 Chain, Dest, CC, Cmp);
8842 CC = Cond.getOperand(1).getOperand(0);
8846 } else { // ISD::AND
8847 // Also, recognize the pattern generated by an FCMP_OEQ. We can emit
8848 // two branches instead of an explicit AND instruction with a
8849 // separate test. However, we only do this if this block doesn't
8850 // have a fall-through edge, because this requires an explicit
8851 // jmp when the condition is false.
8852 if (Cmp == Cond.getOperand(1).getOperand(1) &&
8853 isX86LogicalCmp(Cmp) &&
8854 Op.getNode()->hasOneUse()) {
8855 X86::CondCode CCode =
8856 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
8857 CCode = X86::GetOppositeBranchCondition(CCode);
8858 CC = DAG.getConstant(CCode, MVT::i8);
8859 SDNode *User = *Op.getNode()->use_begin();
8860 // Look for an unconditional branch following this conditional branch.
8861 // We need this because we need to reverse the successors in order
8862 // to implement FCMP_OEQ.
8863 if (User->getOpcode() == ISD::BR) {
8864 SDValue FalseBB = User->getOperand(1);
8866 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
8867 assert(NewBR == User);
8871 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
8872 Chain, Dest, CC, Cmp);
8873 X86::CondCode CCode =
8874 (X86::CondCode)Cond.getOperand(1).getConstantOperandVal(0);
8875 CCode = X86::GetOppositeBranchCondition(CCode);
8876 CC = DAG.getConstant(CCode, MVT::i8);
8882 } else if (Cond.hasOneUse() && isXor1OfSetCC(Cond)) {
8883 // Recognize for xorb (setcc), 1 patterns. The xor inverts the condition.
8884 // It should be transformed during dag combiner except when the condition
8885 // is set by a arithmetics with overflow node.
8886 X86::CondCode CCode =
8887 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
8888 CCode = X86::GetOppositeBranchCondition(CCode);
8889 CC = DAG.getConstant(CCode, MVT::i8);
8890 Cond = Cond.getOperand(0).getOperand(1);
8892 } else if (Cond.getOpcode() == ISD::SETCC &&
8893 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETOEQ) {
8894 // For FCMP_OEQ, we can emit
8895 // two branches instead of an explicit AND instruction with a
8896 // separate test. However, we only do this if this block doesn't
8897 // have a fall-through edge, because this requires an explicit
8898 // jmp when the condition is false.
8899 if (Op.getNode()->hasOneUse()) {
8900 SDNode *User = *Op.getNode()->use_begin();
8901 // Look for an unconditional branch following this conditional branch.
8902 // We need this because we need to reverse the successors in order
8903 // to implement FCMP_OEQ.
8904 if (User->getOpcode() == ISD::BR) {
8905 SDValue FalseBB = User->getOperand(1);
8907 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
8908 assert(NewBR == User);
8912 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
8913 Cond.getOperand(0), Cond.getOperand(1));
8914 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
8915 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
8916 Chain, Dest, CC, Cmp);
8917 CC = DAG.getConstant(X86::COND_P, MVT::i8);
8922 } else if (Cond.getOpcode() == ISD::SETCC &&
8923 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETUNE) {
8924 // For FCMP_UNE, we can emit
8925 // two branches instead of an explicit AND instruction with a
8926 // separate test. However, we only do this if this block doesn't
8927 // have a fall-through edge, because this requires an explicit
8928 // jmp when the condition is false.
8929 if (Op.getNode()->hasOneUse()) {
8930 SDNode *User = *Op.getNode()->use_begin();
8931 // Look for an unconditional branch following this conditional branch.
8932 // We need this because we need to reverse the successors in order
8933 // to implement FCMP_UNE.
8934 if (User->getOpcode() == ISD::BR) {
8935 SDValue FalseBB = User->getOperand(1);
8937 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
8938 assert(NewBR == User);
8941 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
8942 Cond.getOperand(0), Cond.getOperand(1));
8943 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
8944 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
8945 Chain, Dest, CC, Cmp);
8946 CC = DAG.getConstant(X86::COND_NP, MVT::i8);
8956 // Look pass the truncate.
8957 if (Cond.getOpcode() == ISD::TRUNCATE)
8958 Cond = Cond.getOperand(0);
8960 // We know the result of AND is compared against zero. Try to match
8962 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
8963 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, dl, DAG);
8964 if (NewSetCC.getNode()) {
8965 CC = NewSetCC.getOperand(0);
8966 Cond = NewSetCC.getOperand(1);
8973 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
8974 Cond = EmitTest(Cond, X86::COND_NE, DAG);
8976 return DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
8977 Chain, Dest, CC, Cond);
8981 // Lower dynamic stack allocation to _alloca call for Cygwin/Mingw targets.
8982 // Calls to _alloca is needed to probe the stack when allocating more than 4k
8983 // bytes in one go. Touching the stack at 4K increments is necessary to ensure
8984 // that the guard pages used by the OS virtual memory manager are allocated in
8985 // correct sequence.
8987 X86TargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
8988 SelectionDAG &DAG) const {
8989 assert((Subtarget->isTargetCygMing() || Subtarget->isTargetWindows() ||
8990 getTargetMachine().Options.EnableSegmentedStacks) &&
8991 "This should be used only on Windows targets or when segmented stacks "
8993 assert(!Subtarget->isTargetEnvMacho() && "Not implemented");
8994 DebugLoc dl = Op.getDebugLoc();
8997 SDValue Chain = Op.getOperand(0);
8998 SDValue Size = Op.getOperand(1);
8999 // FIXME: Ensure alignment here
9001 bool Is64Bit = Subtarget->is64Bit();
9002 EVT SPTy = Is64Bit ? MVT::i64 : MVT::i32;
9004 if (getTargetMachine().Options.EnableSegmentedStacks) {
9005 MachineFunction &MF = DAG.getMachineFunction();
9006 MachineRegisterInfo &MRI = MF.getRegInfo();
9009 // The 64 bit implementation of segmented stacks needs to clobber both r10
9010 // r11. This makes it impossible to use it along with nested parameters.
9011 const Function *F = MF.getFunction();
9013 for (Function::const_arg_iterator I = F->arg_begin(), E = F->arg_end();
9015 if (I->hasNestAttr())
9016 report_fatal_error("Cannot use segmented stacks with functions that "
9017 "have nested arguments.");
9020 const TargetRegisterClass *AddrRegClass =
9021 getRegClassFor(Subtarget->is64Bit() ? MVT::i64:MVT::i32);
9022 unsigned Vreg = MRI.createVirtualRegister(AddrRegClass);
9023 Chain = DAG.getCopyToReg(Chain, dl, Vreg, Size);
9024 SDValue Value = DAG.getNode(X86ISD::SEG_ALLOCA, dl, SPTy, Chain,
9025 DAG.getRegister(Vreg, SPTy));
9026 SDValue Ops1[2] = { Value, Chain };
9027 return DAG.getMergeValues(Ops1, 2, dl);
9030 unsigned Reg = (Subtarget->is64Bit() ? X86::RAX : X86::EAX);
9032 Chain = DAG.getCopyToReg(Chain, dl, Reg, Size, Flag);
9033 Flag = Chain.getValue(1);
9034 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
9036 Chain = DAG.getNode(X86ISD::WIN_ALLOCA, dl, NodeTys, Chain, Flag);
9037 Flag = Chain.getValue(1);
9039 Chain = DAG.getCopyFromReg(Chain, dl, X86StackPtr, SPTy).getValue(1);
9041 SDValue Ops1[2] = { Chain.getValue(0), Chain };
9042 return DAG.getMergeValues(Ops1, 2, dl);
9046 SDValue X86TargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const {
9047 MachineFunction &MF = DAG.getMachineFunction();
9048 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
9050 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
9051 DebugLoc DL = Op.getDebugLoc();
9053 if (!Subtarget->is64Bit() || Subtarget->isTargetWin64()) {
9054 // vastart just stores the address of the VarArgsFrameIndex slot into the
9055 // memory location argument.
9056 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
9058 return DAG.getStore(Op.getOperand(0), DL, FR, Op.getOperand(1),
9059 MachinePointerInfo(SV), false, false, 0);
9063 // gp_offset (0 - 6 * 8)
9064 // fp_offset (48 - 48 + 8 * 16)
9065 // overflow_arg_area (point to parameters coming in memory).
9067 SmallVector<SDValue, 8> MemOps;
9068 SDValue FIN = Op.getOperand(1);
9070 SDValue Store = DAG.getStore(Op.getOperand(0), DL,
9071 DAG.getConstant(FuncInfo->getVarArgsGPOffset(),
9073 FIN, MachinePointerInfo(SV), false, false, 0);
9074 MemOps.push_back(Store);
9077 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
9078 FIN, DAG.getIntPtrConstant(4));
9079 Store = DAG.getStore(Op.getOperand(0), DL,
9080 DAG.getConstant(FuncInfo->getVarArgsFPOffset(),
9082 FIN, MachinePointerInfo(SV, 4), false, false, 0);
9083 MemOps.push_back(Store);
9085 // Store ptr to overflow_arg_area
9086 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
9087 FIN, DAG.getIntPtrConstant(4));
9088 SDValue OVFIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
9090 Store = DAG.getStore(Op.getOperand(0), DL, OVFIN, FIN,
9091 MachinePointerInfo(SV, 8),
9093 MemOps.push_back(Store);
9095 // Store ptr to reg_save_area.
9096 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
9097 FIN, DAG.getIntPtrConstant(8));
9098 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
9100 Store = DAG.getStore(Op.getOperand(0), DL, RSFIN, FIN,
9101 MachinePointerInfo(SV, 16), false, false, 0);
9102 MemOps.push_back(Store);
9103 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
9104 &MemOps[0], MemOps.size());
9107 SDValue X86TargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG) const {
9108 assert(Subtarget->is64Bit() &&
9109 "LowerVAARG only handles 64-bit va_arg!");
9110 assert((Subtarget->isTargetLinux() ||
9111 Subtarget->isTargetDarwin()) &&
9112 "Unhandled target in LowerVAARG");
9113 assert(Op.getNode()->getNumOperands() == 4);
9114 SDValue Chain = Op.getOperand(0);
9115 SDValue SrcPtr = Op.getOperand(1);
9116 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
9117 unsigned Align = Op.getConstantOperandVal(3);
9118 DebugLoc dl = Op.getDebugLoc();
9120 EVT ArgVT = Op.getNode()->getValueType(0);
9121 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
9122 uint32_t ArgSize = getTargetData()->getTypeAllocSize(ArgTy);
9125 // Decide which area this value should be read from.
9126 // TODO: Implement the AMD64 ABI in its entirety. This simple
9127 // selection mechanism works only for the basic types.
9128 if (ArgVT == MVT::f80) {
9129 llvm_unreachable("va_arg for f80 not yet implemented");
9130 } else if (ArgVT.isFloatingPoint() && ArgSize <= 16 /*bytes*/) {
9131 ArgMode = 2; // Argument passed in XMM register. Use fp_offset.
9132 } else if (ArgVT.isInteger() && ArgSize <= 32 /*bytes*/) {
9133 ArgMode = 1; // Argument passed in GPR64 register(s). Use gp_offset.
9135 llvm_unreachable("Unhandled argument type in LowerVAARG");
9139 // Sanity Check: Make sure using fp_offset makes sense.
9140 assert(!getTargetMachine().Options.UseSoftFloat &&
9141 !(DAG.getMachineFunction()
9142 .getFunction()->hasFnAttr(Attribute::NoImplicitFloat)) &&
9143 Subtarget->hasSSE1());
9146 // Insert VAARG_64 node into the DAG
9147 // VAARG_64 returns two values: Variable Argument Address, Chain
9148 SmallVector<SDValue, 11> InstOps;
9149 InstOps.push_back(Chain);
9150 InstOps.push_back(SrcPtr);
9151 InstOps.push_back(DAG.getConstant(ArgSize, MVT::i32));
9152 InstOps.push_back(DAG.getConstant(ArgMode, MVT::i8));
9153 InstOps.push_back(DAG.getConstant(Align, MVT::i32));
9154 SDVTList VTs = DAG.getVTList(getPointerTy(), MVT::Other);
9155 SDValue VAARG = DAG.getMemIntrinsicNode(X86ISD::VAARG_64, dl,
9156 VTs, &InstOps[0], InstOps.size(),
9158 MachinePointerInfo(SV),
9163 Chain = VAARG.getValue(1);
9165 // Load the next argument and return it
9166 return DAG.getLoad(ArgVT, dl,
9169 MachinePointerInfo(),
9170 false, false, false, 0);
9173 SDValue X86TargetLowering::LowerVACOPY(SDValue Op, SelectionDAG &DAG) const {
9174 // X86-64 va_list is a struct { i32, i32, i8*, i8* }.
9175 assert(Subtarget->is64Bit() && "This code only handles 64-bit va_copy!");
9176 SDValue Chain = Op.getOperand(0);
9177 SDValue DstPtr = Op.getOperand(1);
9178 SDValue SrcPtr = Op.getOperand(2);
9179 const Value *DstSV = cast<SrcValueSDNode>(Op.getOperand(3))->getValue();
9180 const Value *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
9181 DebugLoc DL = Op.getDebugLoc();
9183 return DAG.getMemcpy(Chain, DL, DstPtr, SrcPtr,
9184 DAG.getIntPtrConstant(24), 8, /*isVolatile*/false,
9186 MachinePointerInfo(DstSV), MachinePointerInfo(SrcSV));
9189 // getTargetVShiftNOde - Handle vector element shifts where the shift amount
9190 // may or may not be a constant. Takes immediate version of shift as input.
9191 static SDValue getTargetVShiftNode(unsigned Opc, DebugLoc dl, EVT VT,
9192 SDValue SrcOp, SDValue ShAmt,
9193 SelectionDAG &DAG) {
9194 assert(ShAmt.getValueType() == MVT::i32 && "ShAmt is not i32");
9196 if (isa<ConstantSDNode>(ShAmt)) {
9198 default: llvm_unreachable("Unknown target vector shift node");
9202 return DAG.getNode(Opc, dl, VT, SrcOp, ShAmt);
9206 // Change opcode to non-immediate version
9208 default: llvm_unreachable("Unknown target vector shift node");
9209 case X86ISD::VSHLI: Opc = X86ISD::VSHL; break;
9210 case X86ISD::VSRLI: Opc = X86ISD::VSRL; break;
9211 case X86ISD::VSRAI: Opc = X86ISD::VSRA; break;
9214 // Need to build a vector containing shift amount
9215 // Shift amount is 32-bits, but SSE instructions read 64-bit, so fill with 0
9218 ShOps[1] = DAG.getConstant(0, MVT::i32);
9219 ShOps[2] = DAG.getUNDEF(MVT::i32);
9220 ShOps[3] = DAG.getUNDEF(MVT::i32);
9221 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, &ShOps[0], 4);
9222 ShAmt = DAG.getNode(ISD::BITCAST, dl, VT, ShAmt);
9223 return DAG.getNode(Opc, dl, VT, SrcOp, ShAmt);
9227 X86TargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const {
9228 DebugLoc dl = Op.getDebugLoc();
9229 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
9231 default: return SDValue(); // Don't custom lower most intrinsics.
9232 // Comparison intrinsics.
9233 case Intrinsic::x86_sse_comieq_ss:
9234 case Intrinsic::x86_sse_comilt_ss:
9235 case Intrinsic::x86_sse_comile_ss:
9236 case Intrinsic::x86_sse_comigt_ss:
9237 case Intrinsic::x86_sse_comige_ss:
9238 case Intrinsic::x86_sse_comineq_ss:
9239 case Intrinsic::x86_sse_ucomieq_ss:
9240 case Intrinsic::x86_sse_ucomilt_ss:
9241 case Intrinsic::x86_sse_ucomile_ss:
9242 case Intrinsic::x86_sse_ucomigt_ss:
9243 case Intrinsic::x86_sse_ucomige_ss:
9244 case Intrinsic::x86_sse_ucomineq_ss:
9245 case Intrinsic::x86_sse2_comieq_sd:
9246 case Intrinsic::x86_sse2_comilt_sd:
9247 case Intrinsic::x86_sse2_comile_sd:
9248 case Intrinsic::x86_sse2_comigt_sd:
9249 case Intrinsic::x86_sse2_comige_sd:
9250 case Intrinsic::x86_sse2_comineq_sd:
9251 case Intrinsic::x86_sse2_ucomieq_sd:
9252 case Intrinsic::x86_sse2_ucomilt_sd:
9253 case Intrinsic::x86_sse2_ucomile_sd:
9254 case Intrinsic::x86_sse2_ucomigt_sd:
9255 case Intrinsic::x86_sse2_ucomige_sd:
9256 case Intrinsic::x86_sse2_ucomineq_sd: {
9258 ISD::CondCode CC = ISD::SETCC_INVALID;
9260 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
9261 case Intrinsic::x86_sse_comieq_ss:
9262 case Intrinsic::x86_sse2_comieq_sd:
9266 case Intrinsic::x86_sse_comilt_ss:
9267 case Intrinsic::x86_sse2_comilt_sd:
9271 case Intrinsic::x86_sse_comile_ss:
9272 case Intrinsic::x86_sse2_comile_sd:
9276 case Intrinsic::x86_sse_comigt_ss:
9277 case Intrinsic::x86_sse2_comigt_sd:
9281 case Intrinsic::x86_sse_comige_ss:
9282 case Intrinsic::x86_sse2_comige_sd:
9286 case Intrinsic::x86_sse_comineq_ss:
9287 case Intrinsic::x86_sse2_comineq_sd:
9291 case Intrinsic::x86_sse_ucomieq_ss:
9292 case Intrinsic::x86_sse2_ucomieq_sd:
9293 Opc = X86ISD::UCOMI;
9296 case Intrinsic::x86_sse_ucomilt_ss:
9297 case Intrinsic::x86_sse2_ucomilt_sd:
9298 Opc = X86ISD::UCOMI;
9301 case Intrinsic::x86_sse_ucomile_ss:
9302 case Intrinsic::x86_sse2_ucomile_sd:
9303 Opc = X86ISD::UCOMI;
9306 case Intrinsic::x86_sse_ucomigt_ss:
9307 case Intrinsic::x86_sse2_ucomigt_sd:
9308 Opc = X86ISD::UCOMI;
9311 case Intrinsic::x86_sse_ucomige_ss:
9312 case Intrinsic::x86_sse2_ucomige_sd:
9313 Opc = X86ISD::UCOMI;
9316 case Intrinsic::x86_sse_ucomineq_ss:
9317 case Intrinsic::x86_sse2_ucomineq_sd:
9318 Opc = X86ISD::UCOMI;
9323 SDValue LHS = Op.getOperand(1);
9324 SDValue RHS = Op.getOperand(2);
9325 unsigned X86CC = TranslateX86CC(CC, true, LHS, RHS, DAG);
9326 assert(X86CC != X86::COND_INVALID && "Unexpected illegal condition!");
9327 SDValue Cond = DAG.getNode(Opc, dl, MVT::i32, LHS, RHS);
9328 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
9329 DAG.getConstant(X86CC, MVT::i8), Cond);
9330 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
9332 // XOP comparison intrinsics
9333 case Intrinsic::x86_xop_vpcomltb:
9334 case Intrinsic::x86_xop_vpcomltw:
9335 case Intrinsic::x86_xop_vpcomltd:
9336 case Intrinsic::x86_xop_vpcomltq:
9337 case Intrinsic::x86_xop_vpcomltub:
9338 case Intrinsic::x86_xop_vpcomltuw:
9339 case Intrinsic::x86_xop_vpcomltud:
9340 case Intrinsic::x86_xop_vpcomltuq:
9341 case Intrinsic::x86_xop_vpcomleb:
9342 case Intrinsic::x86_xop_vpcomlew:
9343 case Intrinsic::x86_xop_vpcomled:
9344 case Intrinsic::x86_xop_vpcomleq:
9345 case Intrinsic::x86_xop_vpcomleub:
9346 case Intrinsic::x86_xop_vpcomleuw:
9347 case Intrinsic::x86_xop_vpcomleud:
9348 case Intrinsic::x86_xop_vpcomleuq:
9349 case Intrinsic::x86_xop_vpcomgtb:
9350 case Intrinsic::x86_xop_vpcomgtw:
9351 case Intrinsic::x86_xop_vpcomgtd:
9352 case Intrinsic::x86_xop_vpcomgtq:
9353 case Intrinsic::x86_xop_vpcomgtub:
9354 case Intrinsic::x86_xop_vpcomgtuw:
9355 case Intrinsic::x86_xop_vpcomgtud:
9356 case Intrinsic::x86_xop_vpcomgtuq:
9357 case Intrinsic::x86_xop_vpcomgeb:
9358 case Intrinsic::x86_xop_vpcomgew:
9359 case Intrinsic::x86_xop_vpcomged:
9360 case Intrinsic::x86_xop_vpcomgeq:
9361 case Intrinsic::x86_xop_vpcomgeub:
9362 case Intrinsic::x86_xop_vpcomgeuw:
9363 case Intrinsic::x86_xop_vpcomgeud:
9364 case Intrinsic::x86_xop_vpcomgeuq:
9365 case Intrinsic::x86_xop_vpcomeqb:
9366 case Intrinsic::x86_xop_vpcomeqw:
9367 case Intrinsic::x86_xop_vpcomeqd:
9368 case Intrinsic::x86_xop_vpcomeqq:
9369 case Intrinsic::x86_xop_vpcomequb:
9370 case Intrinsic::x86_xop_vpcomequw:
9371 case Intrinsic::x86_xop_vpcomequd:
9372 case Intrinsic::x86_xop_vpcomequq:
9373 case Intrinsic::x86_xop_vpcomneb:
9374 case Intrinsic::x86_xop_vpcomnew:
9375 case Intrinsic::x86_xop_vpcomned:
9376 case Intrinsic::x86_xop_vpcomneq:
9377 case Intrinsic::x86_xop_vpcomneub:
9378 case Intrinsic::x86_xop_vpcomneuw:
9379 case Intrinsic::x86_xop_vpcomneud:
9380 case Intrinsic::x86_xop_vpcomneuq:
9381 case Intrinsic::x86_xop_vpcomfalseb:
9382 case Intrinsic::x86_xop_vpcomfalsew:
9383 case Intrinsic::x86_xop_vpcomfalsed:
9384 case Intrinsic::x86_xop_vpcomfalseq:
9385 case Intrinsic::x86_xop_vpcomfalseub:
9386 case Intrinsic::x86_xop_vpcomfalseuw:
9387 case Intrinsic::x86_xop_vpcomfalseud:
9388 case Intrinsic::x86_xop_vpcomfalseuq:
9389 case Intrinsic::x86_xop_vpcomtrueb:
9390 case Intrinsic::x86_xop_vpcomtruew:
9391 case Intrinsic::x86_xop_vpcomtrued:
9392 case Intrinsic::x86_xop_vpcomtrueq:
9393 case Intrinsic::x86_xop_vpcomtrueub:
9394 case Intrinsic::x86_xop_vpcomtrueuw:
9395 case Intrinsic::x86_xop_vpcomtrueud:
9396 case Intrinsic::x86_xop_vpcomtrueuq: {
9401 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
9402 case Intrinsic::x86_xop_vpcomltb:
9403 case Intrinsic::x86_xop_vpcomltw:
9404 case Intrinsic::x86_xop_vpcomltd:
9405 case Intrinsic::x86_xop_vpcomltq:
9407 Opc = X86ISD::VPCOM;
9409 case Intrinsic::x86_xop_vpcomltub:
9410 case Intrinsic::x86_xop_vpcomltuw:
9411 case Intrinsic::x86_xop_vpcomltud:
9412 case Intrinsic::x86_xop_vpcomltuq:
9414 Opc = X86ISD::VPCOMU;
9416 case Intrinsic::x86_xop_vpcomleb:
9417 case Intrinsic::x86_xop_vpcomlew:
9418 case Intrinsic::x86_xop_vpcomled:
9419 case Intrinsic::x86_xop_vpcomleq:
9421 Opc = X86ISD::VPCOM;
9423 case Intrinsic::x86_xop_vpcomleub:
9424 case Intrinsic::x86_xop_vpcomleuw:
9425 case Intrinsic::x86_xop_vpcomleud:
9426 case Intrinsic::x86_xop_vpcomleuq:
9428 Opc = X86ISD::VPCOMU;
9430 case Intrinsic::x86_xop_vpcomgtb:
9431 case Intrinsic::x86_xop_vpcomgtw:
9432 case Intrinsic::x86_xop_vpcomgtd:
9433 case Intrinsic::x86_xop_vpcomgtq:
9435 Opc = X86ISD::VPCOM;
9437 case Intrinsic::x86_xop_vpcomgtub:
9438 case Intrinsic::x86_xop_vpcomgtuw:
9439 case Intrinsic::x86_xop_vpcomgtud:
9440 case Intrinsic::x86_xop_vpcomgtuq:
9442 Opc = X86ISD::VPCOMU;
9444 case Intrinsic::x86_xop_vpcomgeb:
9445 case Intrinsic::x86_xop_vpcomgew:
9446 case Intrinsic::x86_xop_vpcomged:
9447 case Intrinsic::x86_xop_vpcomgeq:
9449 Opc = X86ISD::VPCOM;
9451 case Intrinsic::x86_xop_vpcomgeub:
9452 case Intrinsic::x86_xop_vpcomgeuw:
9453 case Intrinsic::x86_xop_vpcomgeud:
9454 case Intrinsic::x86_xop_vpcomgeuq:
9456 Opc = X86ISD::VPCOMU;
9458 case Intrinsic::x86_xop_vpcomeqb:
9459 case Intrinsic::x86_xop_vpcomeqw:
9460 case Intrinsic::x86_xop_vpcomeqd:
9461 case Intrinsic::x86_xop_vpcomeqq:
9463 Opc = X86ISD::VPCOM;
9465 case Intrinsic::x86_xop_vpcomequb:
9466 case Intrinsic::x86_xop_vpcomequw:
9467 case Intrinsic::x86_xop_vpcomequd:
9468 case Intrinsic::x86_xop_vpcomequq:
9470 Opc = X86ISD::VPCOMU;
9472 case Intrinsic::x86_xop_vpcomneb:
9473 case Intrinsic::x86_xop_vpcomnew:
9474 case Intrinsic::x86_xop_vpcomned:
9475 case Intrinsic::x86_xop_vpcomneq:
9477 Opc = X86ISD::VPCOM;
9479 case Intrinsic::x86_xop_vpcomneub:
9480 case Intrinsic::x86_xop_vpcomneuw:
9481 case Intrinsic::x86_xop_vpcomneud:
9482 case Intrinsic::x86_xop_vpcomneuq:
9484 Opc = X86ISD::VPCOMU;
9486 case Intrinsic::x86_xop_vpcomfalseb:
9487 case Intrinsic::x86_xop_vpcomfalsew:
9488 case Intrinsic::x86_xop_vpcomfalsed:
9489 case Intrinsic::x86_xop_vpcomfalseq:
9491 Opc = X86ISD::VPCOM;
9493 case Intrinsic::x86_xop_vpcomfalseub:
9494 case Intrinsic::x86_xop_vpcomfalseuw:
9495 case Intrinsic::x86_xop_vpcomfalseud:
9496 case Intrinsic::x86_xop_vpcomfalseuq:
9498 Opc = X86ISD::VPCOMU;
9500 case Intrinsic::x86_xop_vpcomtrueb:
9501 case Intrinsic::x86_xop_vpcomtruew:
9502 case Intrinsic::x86_xop_vpcomtrued:
9503 case Intrinsic::x86_xop_vpcomtrueq:
9505 Opc = X86ISD::VPCOM;
9507 case Intrinsic::x86_xop_vpcomtrueub:
9508 case Intrinsic::x86_xop_vpcomtrueuw:
9509 case Intrinsic::x86_xop_vpcomtrueud:
9510 case Intrinsic::x86_xop_vpcomtrueuq:
9512 Opc = X86ISD::VPCOMU;
9516 SDValue LHS = Op.getOperand(1);
9517 SDValue RHS = Op.getOperand(2);
9518 return DAG.getNode(Opc, dl, Op.getValueType(), LHS, RHS,
9519 DAG.getConstant(CC, MVT::i8));
9522 // Arithmetic intrinsics.
9523 case Intrinsic::x86_sse2_pmulu_dq:
9524 case Intrinsic::x86_avx2_pmulu_dq:
9525 return DAG.getNode(X86ISD::PMULUDQ, dl, Op.getValueType(),
9526 Op.getOperand(1), Op.getOperand(2));
9527 case Intrinsic::x86_sse3_hadd_ps:
9528 case Intrinsic::x86_sse3_hadd_pd:
9529 case Intrinsic::x86_avx_hadd_ps_256:
9530 case Intrinsic::x86_avx_hadd_pd_256:
9531 return DAG.getNode(X86ISD::FHADD, dl, Op.getValueType(),
9532 Op.getOperand(1), Op.getOperand(2));
9533 case Intrinsic::x86_sse3_hsub_ps:
9534 case Intrinsic::x86_sse3_hsub_pd:
9535 case Intrinsic::x86_avx_hsub_ps_256:
9536 case Intrinsic::x86_avx_hsub_pd_256:
9537 return DAG.getNode(X86ISD::FHSUB, dl, Op.getValueType(),
9538 Op.getOperand(1), Op.getOperand(2));
9539 case Intrinsic::x86_ssse3_phadd_w_128:
9540 case Intrinsic::x86_ssse3_phadd_d_128:
9541 case Intrinsic::x86_avx2_phadd_w:
9542 case Intrinsic::x86_avx2_phadd_d:
9543 return DAG.getNode(X86ISD::HADD, dl, Op.getValueType(),
9544 Op.getOperand(1), Op.getOperand(2));
9545 case Intrinsic::x86_ssse3_phsub_w_128:
9546 case Intrinsic::x86_ssse3_phsub_d_128:
9547 case Intrinsic::x86_avx2_phsub_w:
9548 case Intrinsic::x86_avx2_phsub_d:
9549 return DAG.getNode(X86ISD::HSUB, dl, Op.getValueType(),
9550 Op.getOperand(1), Op.getOperand(2));
9551 case Intrinsic::x86_avx2_psllv_d:
9552 case Intrinsic::x86_avx2_psllv_q:
9553 case Intrinsic::x86_avx2_psllv_d_256:
9554 case Intrinsic::x86_avx2_psllv_q_256:
9555 return DAG.getNode(ISD::SHL, dl, Op.getValueType(),
9556 Op.getOperand(1), Op.getOperand(2));
9557 case Intrinsic::x86_avx2_psrlv_d:
9558 case Intrinsic::x86_avx2_psrlv_q:
9559 case Intrinsic::x86_avx2_psrlv_d_256:
9560 case Intrinsic::x86_avx2_psrlv_q_256:
9561 return DAG.getNode(ISD::SRL, dl, Op.getValueType(),
9562 Op.getOperand(1), Op.getOperand(2));
9563 case Intrinsic::x86_avx2_psrav_d:
9564 case Intrinsic::x86_avx2_psrav_d_256:
9565 return DAG.getNode(ISD::SRA, dl, Op.getValueType(),
9566 Op.getOperand(1), Op.getOperand(2));
9567 case Intrinsic::x86_ssse3_pshuf_b_128:
9568 case Intrinsic::x86_avx2_pshuf_b:
9569 return DAG.getNode(X86ISD::PSHUFB, dl, Op.getValueType(),
9570 Op.getOperand(1), Op.getOperand(2));
9571 case Intrinsic::x86_ssse3_psign_b_128:
9572 case Intrinsic::x86_ssse3_psign_w_128:
9573 case Intrinsic::x86_ssse3_psign_d_128:
9574 case Intrinsic::x86_avx2_psign_b:
9575 case Intrinsic::x86_avx2_psign_w:
9576 case Intrinsic::x86_avx2_psign_d:
9577 return DAG.getNode(X86ISD::PSIGN, dl, Op.getValueType(),
9578 Op.getOperand(1), Op.getOperand(2));
9579 case Intrinsic::x86_sse41_insertps:
9580 return DAG.getNode(X86ISD::INSERTPS, dl, Op.getValueType(),
9581 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
9582 case Intrinsic::x86_avx_vperm2f128_ps_256:
9583 case Intrinsic::x86_avx_vperm2f128_pd_256:
9584 case Intrinsic::x86_avx_vperm2f128_si_256:
9585 case Intrinsic::x86_avx2_vperm2i128:
9586 return DAG.getNode(X86ISD::VPERM2X128, dl, Op.getValueType(),
9587 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
9588 case Intrinsic::x86_avx2_permd:
9589 case Intrinsic::x86_avx2_permps:
9590 // Operands intentionally swapped. Mask is last operand to intrinsic,
9591 // but second operand for node/intruction.
9592 return DAG.getNode(X86ISD::VPERMV, dl, Op.getValueType(),
9593 Op.getOperand(2), Op.getOperand(1));
9595 // ptest and testp intrinsics. The intrinsic these come from are designed to
9596 // return an integer value, not just an instruction so lower it to the ptest
9597 // or testp pattern and a setcc for the result.
9598 case Intrinsic::x86_sse41_ptestz:
9599 case Intrinsic::x86_sse41_ptestc:
9600 case Intrinsic::x86_sse41_ptestnzc:
9601 case Intrinsic::x86_avx_ptestz_256:
9602 case Intrinsic::x86_avx_ptestc_256:
9603 case Intrinsic::x86_avx_ptestnzc_256:
9604 case Intrinsic::x86_avx_vtestz_ps:
9605 case Intrinsic::x86_avx_vtestc_ps:
9606 case Intrinsic::x86_avx_vtestnzc_ps:
9607 case Intrinsic::x86_avx_vtestz_pd:
9608 case Intrinsic::x86_avx_vtestc_pd:
9609 case Intrinsic::x86_avx_vtestnzc_pd:
9610 case Intrinsic::x86_avx_vtestz_ps_256:
9611 case Intrinsic::x86_avx_vtestc_ps_256:
9612 case Intrinsic::x86_avx_vtestnzc_ps_256:
9613 case Intrinsic::x86_avx_vtestz_pd_256:
9614 case Intrinsic::x86_avx_vtestc_pd_256:
9615 case Intrinsic::x86_avx_vtestnzc_pd_256: {
9616 bool IsTestPacked = false;
9619 default: llvm_unreachable("Bad fallthrough in Intrinsic lowering.");
9620 case Intrinsic::x86_avx_vtestz_ps:
9621 case Intrinsic::x86_avx_vtestz_pd:
9622 case Intrinsic::x86_avx_vtestz_ps_256:
9623 case Intrinsic::x86_avx_vtestz_pd_256:
9624 IsTestPacked = true; // Fallthrough
9625 case Intrinsic::x86_sse41_ptestz:
9626 case Intrinsic::x86_avx_ptestz_256:
9628 X86CC = X86::COND_E;
9630 case Intrinsic::x86_avx_vtestc_ps:
9631 case Intrinsic::x86_avx_vtestc_pd:
9632 case Intrinsic::x86_avx_vtestc_ps_256:
9633 case Intrinsic::x86_avx_vtestc_pd_256:
9634 IsTestPacked = true; // Fallthrough
9635 case Intrinsic::x86_sse41_ptestc:
9636 case Intrinsic::x86_avx_ptestc_256:
9638 X86CC = X86::COND_B;
9640 case Intrinsic::x86_avx_vtestnzc_ps:
9641 case Intrinsic::x86_avx_vtestnzc_pd:
9642 case Intrinsic::x86_avx_vtestnzc_ps_256:
9643 case Intrinsic::x86_avx_vtestnzc_pd_256:
9644 IsTestPacked = true; // Fallthrough
9645 case Intrinsic::x86_sse41_ptestnzc:
9646 case Intrinsic::x86_avx_ptestnzc_256:
9648 X86CC = X86::COND_A;
9652 SDValue LHS = Op.getOperand(1);
9653 SDValue RHS = Op.getOperand(2);
9654 unsigned TestOpc = IsTestPacked ? X86ISD::TESTP : X86ISD::PTEST;
9655 SDValue Test = DAG.getNode(TestOpc, dl, MVT::i32, LHS, RHS);
9656 SDValue CC = DAG.getConstant(X86CC, MVT::i8);
9657 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8, CC, Test);
9658 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
9661 // SSE/AVX shift intrinsics
9662 case Intrinsic::x86_sse2_psll_w:
9663 case Intrinsic::x86_sse2_psll_d:
9664 case Intrinsic::x86_sse2_psll_q:
9665 case Intrinsic::x86_avx2_psll_w:
9666 case Intrinsic::x86_avx2_psll_d:
9667 case Intrinsic::x86_avx2_psll_q:
9668 return DAG.getNode(X86ISD::VSHL, dl, Op.getValueType(),
9669 Op.getOperand(1), Op.getOperand(2));
9670 case Intrinsic::x86_sse2_psrl_w:
9671 case Intrinsic::x86_sse2_psrl_d:
9672 case Intrinsic::x86_sse2_psrl_q:
9673 case Intrinsic::x86_avx2_psrl_w:
9674 case Intrinsic::x86_avx2_psrl_d:
9675 case Intrinsic::x86_avx2_psrl_q:
9676 return DAG.getNode(X86ISD::VSRL, dl, Op.getValueType(),
9677 Op.getOperand(1), Op.getOperand(2));
9678 case Intrinsic::x86_sse2_psra_w:
9679 case Intrinsic::x86_sse2_psra_d:
9680 case Intrinsic::x86_avx2_psra_w:
9681 case Intrinsic::x86_avx2_psra_d:
9682 return DAG.getNode(X86ISD::VSRA, dl, Op.getValueType(),
9683 Op.getOperand(1), Op.getOperand(2));
9684 case Intrinsic::x86_sse2_pslli_w:
9685 case Intrinsic::x86_sse2_pslli_d:
9686 case Intrinsic::x86_sse2_pslli_q:
9687 case Intrinsic::x86_avx2_pslli_w:
9688 case Intrinsic::x86_avx2_pslli_d:
9689 case Intrinsic::x86_avx2_pslli_q:
9690 return getTargetVShiftNode(X86ISD::VSHLI, dl, Op.getValueType(),
9691 Op.getOperand(1), Op.getOperand(2), DAG);
9692 case Intrinsic::x86_sse2_psrli_w:
9693 case Intrinsic::x86_sse2_psrli_d:
9694 case Intrinsic::x86_sse2_psrli_q:
9695 case Intrinsic::x86_avx2_psrli_w:
9696 case Intrinsic::x86_avx2_psrli_d:
9697 case Intrinsic::x86_avx2_psrli_q:
9698 return getTargetVShiftNode(X86ISD::VSRLI, dl, Op.getValueType(),
9699 Op.getOperand(1), Op.getOperand(2), DAG);
9700 case Intrinsic::x86_sse2_psrai_w:
9701 case Intrinsic::x86_sse2_psrai_d:
9702 case Intrinsic::x86_avx2_psrai_w:
9703 case Intrinsic::x86_avx2_psrai_d:
9704 return getTargetVShiftNode(X86ISD::VSRAI, dl, Op.getValueType(),
9705 Op.getOperand(1), Op.getOperand(2), DAG);
9706 // Fix vector shift instructions where the last operand is a non-immediate
9708 case Intrinsic::x86_mmx_pslli_w:
9709 case Intrinsic::x86_mmx_pslli_d:
9710 case Intrinsic::x86_mmx_pslli_q:
9711 case Intrinsic::x86_mmx_psrli_w:
9712 case Intrinsic::x86_mmx_psrli_d:
9713 case Intrinsic::x86_mmx_psrli_q:
9714 case Intrinsic::x86_mmx_psrai_w:
9715 case Intrinsic::x86_mmx_psrai_d: {
9716 SDValue ShAmt = Op.getOperand(2);
9717 if (isa<ConstantSDNode>(ShAmt))
9720 unsigned NewIntNo = 0;
9722 case Intrinsic::x86_mmx_pslli_w:
9723 NewIntNo = Intrinsic::x86_mmx_psll_w;
9725 case Intrinsic::x86_mmx_pslli_d:
9726 NewIntNo = Intrinsic::x86_mmx_psll_d;
9728 case Intrinsic::x86_mmx_pslli_q:
9729 NewIntNo = Intrinsic::x86_mmx_psll_q;
9731 case Intrinsic::x86_mmx_psrli_w:
9732 NewIntNo = Intrinsic::x86_mmx_psrl_w;
9734 case Intrinsic::x86_mmx_psrli_d:
9735 NewIntNo = Intrinsic::x86_mmx_psrl_d;
9737 case Intrinsic::x86_mmx_psrli_q:
9738 NewIntNo = Intrinsic::x86_mmx_psrl_q;
9740 case Intrinsic::x86_mmx_psrai_w:
9741 NewIntNo = Intrinsic::x86_mmx_psra_w;
9743 case Intrinsic::x86_mmx_psrai_d:
9744 NewIntNo = Intrinsic::x86_mmx_psra_d;
9746 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
9749 // The vector shift intrinsics with scalars uses 32b shift amounts but
9750 // the sse2/mmx shift instructions reads 64 bits. Set the upper 32 bits
9752 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2i32, ShAmt,
9753 DAG.getConstant(0, MVT::i32));
9754 // FIXME this must be lowered to get rid of the invalid type.
9756 EVT VT = Op.getValueType();
9757 ShAmt = DAG.getNode(ISD::BITCAST, dl, VT, ShAmt);
9758 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
9759 DAG.getConstant(NewIntNo, MVT::i32),
9760 Op.getOperand(1), ShAmt);
9765 SDValue X86TargetLowering::LowerRETURNADDR(SDValue Op,
9766 SelectionDAG &DAG) const {
9767 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
9768 MFI->setReturnAddressIsTaken(true);
9770 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
9771 DebugLoc dl = Op.getDebugLoc();
9774 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
9776 DAG.getConstant(TD->getPointerSize(),
9777 Subtarget->is64Bit() ? MVT::i64 : MVT::i32);
9778 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(),
9779 DAG.getNode(ISD::ADD, dl, getPointerTy(),
9781 MachinePointerInfo(), false, false, false, 0);
9784 // Just load the return address.
9785 SDValue RetAddrFI = getReturnAddressFrameIndex(DAG);
9786 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(),
9787 RetAddrFI, MachinePointerInfo(), false, false, false, 0);
9790 SDValue X86TargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {
9791 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
9792 MFI->setFrameAddressIsTaken(true);
9794 EVT VT = Op.getValueType();
9795 DebugLoc dl = Op.getDebugLoc(); // FIXME probably not meaningful
9796 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
9797 unsigned FrameReg = Subtarget->is64Bit() ? X86::RBP : X86::EBP;
9798 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT);
9800 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr,
9801 MachinePointerInfo(),
9802 false, false, false, 0);
9806 SDValue X86TargetLowering::LowerFRAME_TO_ARGS_OFFSET(SDValue Op,
9807 SelectionDAG &DAG) const {
9808 return DAG.getIntPtrConstant(2*TD->getPointerSize());
9811 SDValue X86TargetLowering::LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const {
9812 MachineFunction &MF = DAG.getMachineFunction();
9813 SDValue Chain = Op.getOperand(0);
9814 SDValue Offset = Op.getOperand(1);
9815 SDValue Handler = Op.getOperand(2);
9816 DebugLoc dl = Op.getDebugLoc();
9818 SDValue Frame = DAG.getCopyFromReg(DAG.getEntryNode(), dl,
9819 Subtarget->is64Bit() ? X86::RBP : X86::EBP,
9821 unsigned StoreAddrReg = (Subtarget->is64Bit() ? X86::RCX : X86::ECX);
9823 SDValue StoreAddr = DAG.getNode(ISD::ADD, dl, getPointerTy(), Frame,
9824 DAG.getIntPtrConstant(TD->getPointerSize()));
9825 StoreAddr = DAG.getNode(ISD::ADD, dl, getPointerTy(), StoreAddr, Offset);
9826 Chain = DAG.getStore(Chain, dl, Handler, StoreAddr, MachinePointerInfo(),
9828 Chain = DAG.getCopyToReg(Chain, dl, StoreAddrReg, StoreAddr);
9829 MF.getRegInfo().addLiveOut(StoreAddrReg);
9831 return DAG.getNode(X86ISD::EH_RETURN, dl,
9833 Chain, DAG.getRegister(StoreAddrReg, getPointerTy()));
9836 SDValue X86TargetLowering::LowerADJUST_TRAMPOLINE(SDValue Op,
9837 SelectionDAG &DAG) const {
9838 return Op.getOperand(0);
9841 SDValue X86TargetLowering::LowerINIT_TRAMPOLINE(SDValue Op,
9842 SelectionDAG &DAG) const {
9843 SDValue Root = Op.getOperand(0);
9844 SDValue Trmp = Op.getOperand(1); // trampoline
9845 SDValue FPtr = Op.getOperand(2); // nested function
9846 SDValue Nest = Op.getOperand(3); // 'nest' parameter value
9847 DebugLoc dl = Op.getDebugLoc();
9849 const Value *TrmpAddr = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
9851 if (Subtarget->is64Bit()) {
9852 SDValue OutChains[6];
9854 // Large code-model.
9855 const unsigned char JMP64r = 0xFF; // 64-bit jmp through register opcode.
9856 const unsigned char MOV64ri = 0xB8; // X86::MOV64ri opcode.
9858 const unsigned char N86R10 = X86_MC::getX86RegNum(X86::R10);
9859 const unsigned char N86R11 = X86_MC::getX86RegNum(X86::R11);
9861 const unsigned char REX_WB = 0x40 | 0x08 | 0x01; // REX prefix
9863 // Load the pointer to the nested function into R11.
9864 unsigned OpCode = ((MOV64ri | N86R11) << 8) | REX_WB; // movabsq r11
9865 SDValue Addr = Trmp;
9866 OutChains[0] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
9867 Addr, MachinePointerInfo(TrmpAddr),
9870 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
9871 DAG.getConstant(2, MVT::i64));
9872 OutChains[1] = DAG.getStore(Root, dl, FPtr, Addr,
9873 MachinePointerInfo(TrmpAddr, 2),
9876 // Load the 'nest' parameter value into R10.
9877 // R10 is specified in X86CallingConv.td
9878 OpCode = ((MOV64ri | N86R10) << 8) | REX_WB; // movabsq r10
9879 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
9880 DAG.getConstant(10, MVT::i64));
9881 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
9882 Addr, MachinePointerInfo(TrmpAddr, 10),
9885 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
9886 DAG.getConstant(12, MVT::i64));
9887 OutChains[3] = DAG.getStore(Root, dl, Nest, Addr,
9888 MachinePointerInfo(TrmpAddr, 12),
9891 // Jump to the nested function.
9892 OpCode = (JMP64r << 8) | REX_WB; // jmpq *...
9893 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
9894 DAG.getConstant(20, MVT::i64));
9895 OutChains[4] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
9896 Addr, MachinePointerInfo(TrmpAddr, 20),
9899 unsigned char ModRM = N86R11 | (4 << 3) | (3 << 6); // ...r11
9900 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
9901 DAG.getConstant(22, MVT::i64));
9902 OutChains[5] = DAG.getStore(Root, dl, DAG.getConstant(ModRM, MVT::i8), Addr,
9903 MachinePointerInfo(TrmpAddr, 22),
9906 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains, 6);
9908 const Function *Func =
9909 cast<Function>(cast<SrcValueSDNode>(Op.getOperand(5))->getValue());
9910 CallingConv::ID CC = Func->getCallingConv();
9915 llvm_unreachable("Unsupported calling convention");
9916 case CallingConv::C:
9917 case CallingConv::X86_StdCall: {
9918 // Pass 'nest' parameter in ECX.
9919 // Must be kept in sync with X86CallingConv.td
9922 // Check that ECX wasn't needed by an 'inreg' parameter.
9923 FunctionType *FTy = Func->getFunctionType();
9924 const AttrListPtr &Attrs = Func->getAttributes();
9926 if (!Attrs.isEmpty() && !Func->isVarArg()) {
9927 unsigned InRegCount = 0;
9930 for (FunctionType::param_iterator I = FTy->param_begin(),
9931 E = FTy->param_end(); I != E; ++I, ++Idx)
9932 if (Attrs.paramHasAttr(Idx, Attribute::InReg))
9933 // FIXME: should only count parameters that are lowered to integers.
9934 InRegCount += (TD->getTypeSizeInBits(*I) + 31) / 32;
9936 if (InRegCount > 2) {
9937 report_fatal_error("Nest register in use - reduce number of inreg"
9943 case CallingConv::X86_FastCall:
9944 case CallingConv::X86_ThisCall:
9945 case CallingConv::Fast:
9946 // Pass 'nest' parameter in EAX.
9947 // Must be kept in sync with X86CallingConv.td
9952 SDValue OutChains[4];
9955 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
9956 DAG.getConstant(10, MVT::i32));
9957 Disp = DAG.getNode(ISD::SUB, dl, MVT::i32, FPtr, Addr);
9959 // This is storing the opcode for MOV32ri.
9960 const unsigned char MOV32ri = 0xB8; // X86::MOV32ri's opcode byte.
9961 const unsigned char N86Reg = X86_MC::getX86RegNum(NestReg);
9962 OutChains[0] = DAG.getStore(Root, dl,
9963 DAG.getConstant(MOV32ri|N86Reg, MVT::i8),
9964 Trmp, MachinePointerInfo(TrmpAddr),
9967 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
9968 DAG.getConstant(1, MVT::i32));
9969 OutChains[1] = DAG.getStore(Root, dl, Nest, Addr,
9970 MachinePointerInfo(TrmpAddr, 1),
9973 const unsigned char JMP = 0xE9; // jmp <32bit dst> opcode.
9974 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
9975 DAG.getConstant(5, MVT::i32));
9976 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(JMP, MVT::i8), Addr,
9977 MachinePointerInfo(TrmpAddr, 5),
9980 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
9981 DAG.getConstant(6, MVT::i32));
9982 OutChains[3] = DAG.getStore(Root, dl, Disp, Addr,
9983 MachinePointerInfo(TrmpAddr, 6),
9986 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains, 4);
9990 SDValue X86TargetLowering::LowerFLT_ROUNDS_(SDValue Op,
9991 SelectionDAG &DAG) const {
9993 The rounding mode is in bits 11:10 of FPSR, and has the following
10000 FLT_ROUNDS, on the other hand, expects the following:
10007 To perform the conversion, we do:
10008 (((((FPSR & 0x800) >> 11) | ((FPSR & 0x400) >> 9)) + 1) & 3)
10011 MachineFunction &MF = DAG.getMachineFunction();
10012 const TargetMachine &TM = MF.getTarget();
10013 const TargetFrameLowering &TFI = *TM.getFrameLowering();
10014 unsigned StackAlignment = TFI.getStackAlignment();
10015 EVT VT = Op.getValueType();
10016 DebugLoc DL = Op.getDebugLoc();
10018 // Save FP Control Word to stack slot
10019 int SSFI = MF.getFrameInfo()->CreateStackObject(2, StackAlignment, false);
10020 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
10023 MachineMemOperand *MMO =
10024 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
10025 MachineMemOperand::MOStore, 2, 2);
10027 SDValue Ops[] = { DAG.getEntryNode(), StackSlot };
10028 SDValue Chain = DAG.getMemIntrinsicNode(X86ISD::FNSTCW16m, DL,
10029 DAG.getVTList(MVT::Other),
10030 Ops, 2, MVT::i16, MMO);
10032 // Load FP Control Word from stack slot
10033 SDValue CWD = DAG.getLoad(MVT::i16, DL, Chain, StackSlot,
10034 MachinePointerInfo(), false, false, false, 0);
10036 // Transform as necessary
10038 DAG.getNode(ISD::SRL, DL, MVT::i16,
10039 DAG.getNode(ISD::AND, DL, MVT::i16,
10040 CWD, DAG.getConstant(0x800, MVT::i16)),
10041 DAG.getConstant(11, MVT::i8));
10043 DAG.getNode(ISD::SRL, DL, MVT::i16,
10044 DAG.getNode(ISD::AND, DL, MVT::i16,
10045 CWD, DAG.getConstant(0x400, MVT::i16)),
10046 DAG.getConstant(9, MVT::i8));
10049 DAG.getNode(ISD::AND, DL, MVT::i16,
10050 DAG.getNode(ISD::ADD, DL, MVT::i16,
10051 DAG.getNode(ISD::OR, DL, MVT::i16, CWD1, CWD2),
10052 DAG.getConstant(1, MVT::i16)),
10053 DAG.getConstant(3, MVT::i16));
10056 return DAG.getNode((VT.getSizeInBits() < 16 ?
10057 ISD::TRUNCATE : ISD::ZERO_EXTEND), DL, VT, RetVal);
10060 SDValue X86TargetLowering::LowerCTLZ(SDValue Op, SelectionDAG &DAG) const {
10061 EVT VT = Op.getValueType();
10063 unsigned NumBits = VT.getSizeInBits();
10064 DebugLoc dl = Op.getDebugLoc();
10066 Op = Op.getOperand(0);
10067 if (VT == MVT::i8) {
10068 // Zero extend to i32 since there is not an i8 bsr.
10070 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
10073 // Issue a bsr (scan bits in reverse) which also sets EFLAGS.
10074 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
10075 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
10077 // If src is zero (i.e. bsr sets ZF), returns NumBits.
10080 DAG.getConstant(NumBits+NumBits-1, OpVT),
10081 DAG.getConstant(X86::COND_E, MVT::i8),
10084 Op = DAG.getNode(X86ISD::CMOV, dl, OpVT, Ops, array_lengthof(Ops));
10086 // Finally xor with NumBits-1.
10087 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT));
10090 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
10094 SDValue X86TargetLowering::LowerCTLZ_ZERO_UNDEF(SDValue Op,
10095 SelectionDAG &DAG) const {
10096 EVT VT = Op.getValueType();
10098 unsigned NumBits = VT.getSizeInBits();
10099 DebugLoc dl = Op.getDebugLoc();
10101 Op = Op.getOperand(0);
10102 if (VT == MVT::i8) {
10103 // Zero extend to i32 since there is not an i8 bsr.
10105 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
10108 // Issue a bsr (scan bits in reverse).
10109 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
10110 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
10112 // And xor with NumBits-1.
10113 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT));
10116 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
10120 SDValue X86TargetLowering::LowerCTTZ(SDValue Op, SelectionDAG &DAG) const {
10121 EVT VT = Op.getValueType();
10122 unsigned NumBits = VT.getSizeInBits();
10123 DebugLoc dl = Op.getDebugLoc();
10124 Op = Op.getOperand(0);
10126 // Issue a bsf (scan bits forward) which also sets EFLAGS.
10127 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
10128 Op = DAG.getNode(X86ISD::BSF, dl, VTs, Op);
10130 // If src is zero (i.e. bsf sets ZF), returns NumBits.
10133 DAG.getConstant(NumBits, VT),
10134 DAG.getConstant(X86::COND_E, MVT::i8),
10137 return DAG.getNode(X86ISD::CMOV, dl, VT, Ops, array_lengthof(Ops));
10140 // Lower256IntArith - Break a 256-bit integer operation into two new 128-bit
10141 // ones, and then concatenate the result back.
10142 static SDValue Lower256IntArith(SDValue Op, SelectionDAG &DAG) {
10143 EVT VT = Op.getValueType();
10145 assert(VT.getSizeInBits() == 256 && VT.isInteger() &&
10146 "Unsupported value type for operation");
10148 int NumElems = VT.getVectorNumElements();
10149 DebugLoc dl = Op.getDebugLoc();
10151 // Extract the LHS vectors
10152 SDValue LHS = Op.getOperand(0);
10153 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
10154 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
10156 // Extract the RHS vectors
10157 SDValue RHS = Op.getOperand(1);
10158 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, dl);
10159 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, dl);
10161 MVT EltVT = VT.getVectorElementType().getSimpleVT();
10162 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
10164 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
10165 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1),
10166 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2));
10169 SDValue X86TargetLowering::LowerADD(SDValue Op, SelectionDAG &DAG) const {
10170 assert(Op.getValueType().getSizeInBits() == 256 &&
10171 Op.getValueType().isInteger() &&
10172 "Only handle AVX 256-bit vector integer operation");
10173 return Lower256IntArith(Op, DAG);
10176 SDValue X86TargetLowering::LowerSUB(SDValue Op, SelectionDAG &DAG) const {
10177 assert(Op.getValueType().getSizeInBits() == 256 &&
10178 Op.getValueType().isInteger() &&
10179 "Only handle AVX 256-bit vector integer operation");
10180 return Lower256IntArith(Op, DAG);
10183 SDValue X86TargetLowering::LowerMUL(SDValue Op, SelectionDAG &DAG) const {
10184 EVT VT = Op.getValueType();
10186 // Decompose 256-bit ops into smaller 128-bit ops.
10187 if (VT.getSizeInBits() == 256 && !Subtarget->hasAVX2())
10188 return Lower256IntArith(Op, DAG);
10190 assert((VT == MVT::v2i64 || VT == MVT::v4i64) &&
10191 "Only know how to lower V2I64/V4I64 multiply");
10193 DebugLoc dl = Op.getDebugLoc();
10195 // Ahi = psrlqi(a, 32);
10196 // Bhi = psrlqi(b, 32);
10198 // AloBlo = pmuludq(a, b);
10199 // AloBhi = pmuludq(a, Bhi);
10200 // AhiBlo = pmuludq(Ahi, b);
10202 // AloBhi = psllqi(AloBhi, 32);
10203 // AhiBlo = psllqi(AhiBlo, 32);
10204 // return AloBlo + AloBhi + AhiBlo;
10206 SDValue A = Op.getOperand(0);
10207 SDValue B = Op.getOperand(1);
10209 SDValue ShAmt = DAG.getConstant(32, MVT::i32);
10211 SDValue Ahi = DAG.getNode(X86ISD::VSRLI, dl, VT, A, ShAmt);
10212 SDValue Bhi = DAG.getNode(X86ISD::VSRLI, dl, VT, B, ShAmt);
10214 // Bit cast to 32-bit vectors for MULUDQ
10215 EVT MulVT = (VT == MVT::v2i64) ? MVT::v4i32 : MVT::v8i32;
10216 A = DAG.getNode(ISD::BITCAST, dl, MulVT, A);
10217 B = DAG.getNode(ISD::BITCAST, dl, MulVT, B);
10218 Ahi = DAG.getNode(ISD::BITCAST, dl, MulVT, Ahi);
10219 Bhi = DAG.getNode(ISD::BITCAST, dl, MulVT, Bhi);
10221 SDValue AloBlo = DAG.getNode(X86ISD::PMULUDQ, dl, VT, A, B);
10222 SDValue AloBhi = DAG.getNode(X86ISD::PMULUDQ, dl, VT, A, Bhi);
10223 SDValue AhiBlo = DAG.getNode(X86ISD::PMULUDQ, dl, VT, Ahi, B);
10225 AloBhi = DAG.getNode(X86ISD::VSHLI, dl, VT, AloBhi, ShAmt);
10226 AhiBlo = DAG.getNode(X86ISD::VSHLI, dl, VT, AhiBlo, ShAmt);
10228 SDValue Res = DAG.getNode(ISD::ADD, dl, VT, AloBlo, AloBhi);
10229 return DAG.getNode(ISD::ADD, dl, VT, Res, AhiBlo);
10232 SDValue X86TargetLowering::LowerShift(SDValue Op, SelectionDAG &DAG) const {
10234 EVT VT = Op.getValueType();
10235 DebugLoc dl = Op.getDebugLoc();
10236 SDValue R = Op.getOperand(0);
10237 SDValue Amt = Op.getOperand(1);
10238 LLVMContext *Context = DAG.getContext();
10240 if (!Subtarget->hasSSE2())
10243 // Optimize shl/srl/sra with constant shift amount.
10244 if (isSplatVector(Amt.getNode())) {
10245 SDValue SclrAmt = Amt->getOperand(0);
10246 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(SclrAmt)) {
10247 uint64_t ShiftAmt = C->getZExtValue();
10249 if (VT == MVT::v2i64 || VT == MVT::v4i32 || VT == MVT::v8i16 ||
10250 (Subtarget->hasAVX2() &&
10251 (VT == MVT::v4i64 || VT == MVT::v8i32 || VT == MVT::v16i16))) {
10252 if (Op.getOpcode() == ISD::SHL)
10253 return DAG.getNode(X86ISD::VSHLI, dl, VT, R,
10254 DAG.getConstant(ShiftAmt, MVT::i32));
10255 if (Op.getOpcode() == ISD::SRL)
10256 return DAG.getNode(X86ISD::VSRLI, dl, VT, R,
10257 DAG.getConstant(ShiftAmt, MVT::i32));
10258 if (Op.getOpcode() == ISD::SRA && VT != MVT::v2i64 && VT != MVT::v4i64)
10259 return DAG.getNode(X86ISD::VSRAI, dl, VT, R,
10260 DAG.getConstant(ShiftAmt, MVT::i32));
10263 if (VT == MVT::v16i8) {
10264 if (Op.getOpcode() == ISD::SHL) {
10265 // Make a large shift.
10266 SDValue SHL = DAG.getNode(X86ISD::VSHLI, dl, MVT::v8i16, R,
10267 DAG.getConstant(ShiftAmt, MVT::i32));
10268 SHL = DAG.getNode(ISD::BITCAST, dl, VT, SHL);
10269 // Zero out the rightmost bits.
10270 SmallVector<SDValue, 16> V(16,
10271 DAG.getConstant(uint8_t(-1U << ShiftAmt),
10273 return DAG.getNode(ISD::AND, dl, VT, SHL,
10274 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 16));
10276 if (Op.getOpcode() == ISD::SRL) {
10277 // Make a large shift.
10278 SDValue SRL = DAG.getNode(X86ISD::VSRLI, dl, MVT::v8i16, R,
10279 DAG.getConstant(ShiftAmt, MVT::i32));
10280 SRL = DAG.getNode(ISD::BITCAST, dl, VT, SRL);
10281 // Zero out the leftmost bits.
10282 SmallVector<SDValue, 16> V(16,
10283 DAG.getConstant(uint8_t(-1U) >> ShiftAmt,
10285 return DAG.getNode(ISD::AND, dl, VT, SRL,
10286 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 16));
10288 if (Op.getOpcode() == ISD::SRA) {
10289 if (ShiftAmt == 7) {
10290 // R s>> 7 === R s< 0
10291 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
10292 return DAG.getNode(X86ISD::PCMPGT, dl, VT, Zeros, R);
10295 // R s>> a === ((R u>> a) ^ m) - m
10296 SDValue Res = DAG.getNode(ISD::SRL, dl, VT, R, Amt);
10297 SmallVector<SDValue, 16> V(16, DAG.getConstant(128 >> ShiftAmt,
10299 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 16);
10300 Res = DAG.getNode(ISD::XOR, dl, VT, Res, Mask);
10301 Res = DAG.getNode(ISD::SUB, dl, VT, Res, Mask);
10304 llvm_unreachable("Unknown shift opcode.");
10307 if (Subtarget->hasAVX2() && VT == MVT::v32i8) {
10308 if (Op.getOpcode() == ISD::SHL) {
10309 // Make a large shift.
10310 SDValue SHL = DAG.getNode(X86ISD::VSHLI, dl, MVT::v16i16, R,
10311 DAG.getConstant(ShiftAmt, MVT::i32));
10312 SHL = DAG.getNode(ISD::BITCAST, dl, VT, SHL);
10313 // Zero out the rightmost bits.
10314 SmallVector<SDValue, 32> V(32,
10315 DAG.getConstant(uint8_t(-1U << ShiftAmt),
10317 return DAG.getNode(ISD::AND, dl, VT, SHL,
10318 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 32));
10320 if (Op.getOpcode() == ISD::SRL) {
10321 // Make a large shift.
10322 SDValue SRL = DAG.getNode(X86ISD::VSRLI, dl, MVT::v16i16, R,
10323 DAG.getConstant(ShiftAmt, MVT::i32));
10324 SRL = DAG.getNode(ISD::BITCAST, dl, VT, SRL);
10325 // Zero out the leftmost bits.
10326 SmallVector<SDValue, 32> V(32,
10327 DAG.getConstant(uint8_t(-1U) >> ShiftAmt,
10329 return DAG.getNode(ISD::AND, dl, VT, SRL,
10330 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 32));
10332 if (Op.getOpcode() == ISD::SRA) {
10333 if (ShiftAmt == 7) {
10334 // R s>> 7 === R s< 0
10335 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
10336 return DAG.getNode(X86ISD::PCMPGT, dl, VT, Zeros, R);
10339 // R s>> a === ((R u>> a) ^ m) - m
10340 SDValue Res = DAG.getNode(ISD::SRL, dl, VT, R, Amt);
10341 SmallVector<SDValue, 32> V(32, DAG.getConstant(128 >> ShiftAmt,
10343 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 32);
10344 Res = DAG.getNode(ISD::XOR, dl, VT, Res, Mask);
10345 Res = DAG.getNode(ISD::SUB, dl, VT, Res, Mask);
10348 llvm_unreachable("Unknown shift opcode.");
10353 // Lower SHL with variable shift amount.
10354 if (VT == MVT::v4i32 && Op->getOpcode() == ISD::SHL) {
10355 Op = DAG.getNode(X86ISD::VSHLI, dl, VT, Op.getOperand(1),
10356 DAG.getConstant(23, MVT::i32));
10358 const uint32_t CV[] = { 0x3f800000U, 0x3f800000U, 0x3f800000U, 0x3f800000U};
10359 Constant *C = ConstantDataVector::get(*Context, CV);
10360 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
10361 SDValue Addend = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
10362 MachinePointerInfo::getConstantPool(),
10363 false, false, false, 16);
10365 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Addend);
10366 Op = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, Op);
10367 Op = DAG.getNode(ISD::FP_TO_SINT, dl, VT, Op);
10368 return DAG.getNode(ISD::MUL, dl, VT, Op, R);
10370 if (VT == MVT::v16i8 && Op->getOpcode() == ISD::SHL) {
10371 assert(Subtarget->hasSSE2() && "Need SSE2 for pslli/pcmpeq.");
10374 Op = DAG.getNode(X86ISD::VSHLI, dl, MVT::v8i16, Op.getOperand(1),
10375 DAG.getConstant(5, MVT::i32));
10376 Op = DAG.getNode(ISD::BITCAST, dl, VT, Op);
10378 // Turn 'a' into a mask suitable for VSELECT
10379 SDValue VSelM = DAG.getConstant(0x80, VT);
10380 SDValue OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
10381 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
10383 SDValue CM1 = DAG.getConstant(0x0f, VT);
10384 SDValue CM2 = DAG.getConstant(0x3f, VT);
10386 // r = VSELECT(r, psllw(r & (char16)15, 4), a);
10387 SDValue M = DAG.getNode(ISD::AND, dl, VT, R, CM1);
10388 M = getTargetVShiftNode(X86ISD::VSHLI, dl, MVT::v8i16, M,
10389 DAG.getConstant(4, MVT::i32), DAG);
10390 M = DAG.getNode(ISD::BITCAST, dl, VT, M);
10391 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel, M, R);
10394 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op);
10395 OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
10396 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
10398 // r = VSELECT(r, psllw(r & (char16)63, 2), a);
10399 M = DAG.getNode(ISD::AND, dl, VT, R, CM2);
10400 M = getTargetVShiftNode(X86ISD::VSHLI, dl, MVT::v8i16, M,
10401 DAG.getConstant(2, MVT::i32), DAG);
10402 M = DAG.getNode(ISD::BITCAST, dl, VT, M);
10403 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel, M, R);
10406 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op);
10407 OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
10408 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
10410 // return VSELECT(r, r+r, a);
10411 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel,
10412 DAG.getNode(ISD::ADD, dl, VT, R, R), R);
10416 // Decompose 256-bit shifts into smaller 128-bit shifts.
10417 if (VT.getSizeInBits() == 256) {
10418 unsigned NumElems = VT.getVectorNumElements();
10419 MVT EltVT = VT.getVectorElementType().getSimpleVT();
10420 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
10422 // Extract the two vectors
10423 SDValue V1 = Extract128BitVector(R, 0, DAG, dl);
10424 SDValue V2 = Extract128BitVector(R, NumElems/2, DAG, dl);
10426 // Recreate the shift amount vectors
10427 SDValue Amt1, Amt2;
10428 if (Amt.getOpcode() == ISD::BUILD_VECTOR) {
10429 // Constant shift amount
10430 SmallVector<SDValue, 4> Amt1Csts;
10431 SmallVector<SDValue, 4> Amt2Csts;
10432 for (unsigned i = 0; i != NumElems/2; ++i)
10433 Amt1Csts.push_back(Amt->getOperand(i));
10434 for (unsigned i = NumElems/2; i != NumElems; ++i)
10435 Amt2Csts.push_back(Amt->getOperand(i));
10437 Amt1 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT,
10438 &Amt1Csts[0], NumElems/2);
10439 Amt2 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT,
10440 &Amt2Csts[0], NumElems/2);
10442 // Variable shift amount
10443 Amt1 = Extract128BitVector(Amt, 0, DAG, dl);
10444 Amt2 = Extract128BitVector(Amt, NumElems/2, DAG, dl);
10447 // Issue new vector shifts for the smaller types
10448 V1 = DAG.getNode(Op.getOpcode(), dl, NewVT, V1, Amt1);
10449 V2 = DAG.getNode(Op.getOpcode(), dl, NewVT, V2, Amt2);
10451 // Concatenate the result back
10452 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, V1, V2);
10458 SDValue X86TargetLowering::LowerXALUO(SDValue Op, SelectionDAG &DAG) const {
10459 // Lower the "add/sub/mul with overflow" instruction into a regular ins plus
10460 // a "setcc" instruction that checks the overflow flag. The "brcond" lowering
10461 // looks for this combo and may remove the "setcc" instruction if the "setcc"
10462 // has only one use.
10463 SDNode *N = Op.getNode();
10464 SDValue LHS = N->getOperand(0);
10465 SDValue RHS = N->getOperand(1);
10466 unsigned BaseOp = 0;
10468 DebugLoc DL = Op.getDebugLoc();
10469 switch (Op.getOpcode()) {
10470 default: llvm_unreachable("Unknown ovf instruction!");
10472 // A subtract of one will be selected as a INC. Note that INC doesn't
10473 // set CF, so we can't do this for UADDO.
10474 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
10476 BaseOp = X86ISD::INC;
10477 Cond = X86::COND_O;
10480 BaseOp = X86ISD::ADD;
10481 Cond = X86::COND_O;
10484 BaseOp = X86ISD::ADD;
10485 Cond = X86::COND_B;
10488 // A subtract of one will be selected as a DEC. Note that DEC doesn't
10489 // set CF, so we can't do this for USUBO.
10490 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
10492 BaseOp = X86ISD::DEC;
10493 Cond = X86::COND_O;
10496 BaseOp = X86ISD::SUB;
10497 Cond = X86::COND_O;
10500 BaseOp = X86ISD::SUB;
10501 Cond = X86::COND_B;
10504 BaseOp = X86ISD::SMUL;
10505 Cond = X86::COND_O;
10507 case ISD::UMULO: { // i64, i8 = umulo lhs, rhs --> i64, i64, i32 umul lhs,rhs
10508 SDVTList VTs = DAG.getVTList(N->getValueType(0), N->getValueType(0),
10510 SDValue Sum = DAG.getNode(X86ISD::UMUL, DL, VTs, LHS, RHS);
10513 DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
10514 DAG.getConstant(X86::COND_O, MVT::i32),
10515 SDValue(Sum.getNode(), 2));
10517 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
10521 // Also sets EFLAGS.
10522 SDVTList VTs = DAG.getVTList(N->getValueType(0), MVT::i32);
10523 SDValue Sum = DAG.getNode(BaseOp, DL, VTs, LHS, RHS);
10526 DAG.getNode(X86ISD::SETCC, DL, N->getValueType(1),
10527 DAG.getConstant(Cond, MVT::i32),
10528 SDValue(Sum.getNode(), 1));
10530 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
10533 SDValue X86TargetLowering::LowerSIGN_EXTEND_INREG(SDValue Op,
10534 SelectionDAG &DAG) const {
10535 DebugLoc dl = Op.getDebugLoc();
10536 EVT ExtraVT = cast<VTSDNode>(Op.getOperand(1))->getVT();
10537 EVT VT = Op.getValueType();
10539 if (!Subtarget->hasSSE2() || !VT.isVector())
10542 unsigned BitsDiff = VT.getScalarType().getSizeInBits() -
10543 ExtraVT.getScalarType().getSizeInBits();
10544 SDValue ShAmt = DAG.getConstant(BitsDiff, MVT::i32);
10546 switch (VT.getSimpleVT().SimpleTy) {
10547 default: return SDValue();
10550 if (!Subtarget->hasAVX())
10552 if (!Subtarget->hasAVX2()) {
10553 // needs to be split
10554 int NumElems = VT.getVectorNumElements();
10556 // Extract the LHS vectors
10557 SDValue LHS = Op.getOperand(0);
10558 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
10559 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
10561 MVT EltVT = VT.getVectorElementType().getSimpleVT();
10562 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
10564 EVT ExtraEltVT = ExtraVT.getVectorElementType();
10565 int ExtraNumElems = ExtraVT.getVectorNumElements();
10566 ExtraVT = EVT::getVectorVT(*DAG.getContext(), ExtraEltVT,
10568 SDValue Extra = DAG.getValueType(ExtraVT);
10570 LHS1 = DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, Extra);
10571 LHS2 = DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, Extra);
10573 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, LHS1, LHS2);;
10578 SDValue Tmp1 = getTargetVShiftNode(X86ISD::VSHLI, dl, VT,
10579 Op.getOperand(0), ShAmt, DAG);
10580 return getTargetVShiftNode(X86ISD::VSRAI, dl, VT, Tmp1, ShAmt, DAG);
10586 SDValue X86TargetLowering::LowerMEMBARRIER(SDValue Op, SelectionDAG &DAG) const{
10587 DebugLoc dl = Op.getDebugLoc();
10589 // Go ahead and emit the fence on x86-64 even if we asked for no-sse2.
10590 // There isn't any reason to disable it if the target processor supports it.
10591 if (!Subtarget->hasSSE2() && !Subtarget->is64Bit()) {
10592 SDValue Chain = Op.getOperand(0);
10593 SDValue Zero = DAG.getConstant(0, MVT::i32);
10595 DAG.getRegister(X86::ESP, MVT::i32), // Base
10596 DAG.getTargetConstant(1, MVT::i8), // Scale
10597 DAG.getRegister(0, MVT::i32), // Index
10598 DAG.getTargetConstant(0, MVT::i32), // Disp
10599 DAG.getRegister(0, MVT::i32), // Segment.
10604 DAG.getMachineNode(X86::OR32mrLocked, dl, MVT::Other, Ops,
10605 array_lengthof(Ops));
10606 return SDValue(Res, 0);
10609 unsigned isDev = cast<ConstantSDNode>(Op.getOperand(5))->getZExtValue();
10611 return DAG.getNode(X86ISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0));
10613 unsigned Op1 = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
10614 unsigned Op2 = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue();
10615 unsigned Op3 = cast<ConstantSDNode>(Op.getOperand(3))->getZExtValue();
10616 unsigned Op4 = cast<ConstantSDNode>(Op.getOperand(4))->getZExtValue();
10618 // def : Pat<(membarrier (i8 0), (i8 0), (i8 0), (i8 1), (i8 1)), (SFENCE)>;
10619 if (!Op1 && !Op2 && !Op3 && Op4)
10620 return DAG.getNode(X86ISD::SFENCE, dl, MVT::Other, Op.getOperand(0));
10622 // def : Pat<(membarrier (i8 1), (i8 0), (i8 0), (i8 0), (i8 1)), (LFENCE)>;
10623 if (Op1 && !Op2 && !Op3 && !Op4)
10624 return DAG.getNode(X86ISD::LFENCE, dl, MVT::Other, Op.getOperand(0));
10626 // def : Pat<(membarrier (i8 imm), (i8 imm), (i8 imm), (i8 imm), (i8 1)),
10628 return DAG.getNode(X86ISD::MFENCE, dl, MVT::Other, Op.getOperand(0));
10631 SDValue X86TargetLowering::LowerATOMIC_FENCE(SDValue Op,
10632 SelectionDAG &DAG) const {
10633 DebugLoc dl = Op.getDebugLoc();
10634 AtomicOrdering FenceOrdering = static_cast<AtomicOrdering>(
10635 cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue());
10636 SynchronizationScope FenceScope = static_cast<SynchronizationScope>(
10637 cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue());
10639 // The only fence that needs an instruction is a sequentially-consistent
10640 // cross-thread fence.
10641 if (FenceOrdering == SequentiallyConsistent && FenceScope == CrossThread) {
10642 // Use mfence if we have SSE2 or we're on x86-64 (even if we asked for
10643 // no-sse2). There isn't any reason to disable it if the target processor
10645 if (Subtarget->hasSSE2() || Subtarget->is64Bit())
10646 return DAG.getNode(X86ISD::MFENCE, dl, MVT::Other, Op.getOperand(0));
10648 SDValue Chain = Op.getOperand(0);
10649 SDValue Zero = DAG.getConstant(0, MVT::i32);
10651 DAG.getRegister(X86::ESP, MVT::i32), // Base
10652 DAG.getTargetConstant(1, MVT::i8), // Scale
10653 DAG.getRegister(0, MVT::i32), // Index
10654 DAG.getTargetConstant(0, MVT::i32), // Disp
10655 DAG.getRegister(0, MVT::i32), // Segment.
10660 DAG.getMachineNode(X86::OR32mrLocked, dl, MVT::Other, Ops,
10661 array_lengthof(Ops));
10662 return SDValue(Res, 0);
10665 // MEMBARRIER is a compiler barrier; it codegens to a no-op.
10666 return DAG.getNode(X86ISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0));
10670 SDValue X86TargetLowering::LowerCMP_SWAP(SDValue Op, SelectionDAG &DAG) const {
10671 EVT T = Op.getValueType();
10672 DebugLoc DL = Op.getDebugLoc();
10675 switch(T.getSimpleVT().SimpleTy) {
10676 default: llvm_unreachable("Invalid value type!");
10677 case MVT::i8: Reg = X86::AL; size = 1; break;
10678 case MVT::i16: Reg = X86::AX; size = 2; break;
10679 case MVT::i32: Reg = X86::EAX; size = 4; break;
10681 assert(Subtarget->is64Bit() && "Node not type legal!");
10682 Reg = X86::RAX; size = 8;
10685 SDValue cpIn = DAG.getCopyToReg(Op.getOperand(0), DL, Reg,
10686 Op.getOperand(2), SDValue());
10687 SDValue Ops[] = { cpIn.getValue(0),
10690 DAG.getTargetConstant(size, MVT::i8),
10691 cpIn.getValue(1) };
10692 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
10693 MachineMemOperand *MMO = cast<AtomicSDNode>(Op)->getMemOperand();
10694 SDValue Result = DAG.getMemIntrinsicNode(X86ISD::LCMPXCHG_DAG, DL, Tys,
10697 DAG.getCopyFromReg(Result.getValue(0), DL, Reg, T, Result.getValue(1));
10701 SDValue X86TargetLowering::LowerREADCYCLECOUNTER(SDValue Op,
10702 SelectionDAG &DAG) const {
10703 assert(Subtarget->is64Bit() && "Result not type legalized?");
10704 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
10705 SDValue TheChain = Op.getOperand(0);
10706 DebugLoc dl = Op.getDebugLoc();
10707 SDValue rd = DAG.getNode(X86ISD::RDTSC_DAG, dl, Tys, &TheChain, 1);
10708 SDValue rax = DAG.getCopyFromReg(rd, dl, X86::RAX, MVT::i64, rd.getValue(1));
10709 SDValue rdx = DAG.getCopyFromReg(rax.getValue(1), dl, X86::RDX, MVT::i64,
10711 SDValue Tmp = DAG.getNode(ISD::SHL, dl, MVT::i64, rdx,
10712 DAG.getConstant(32, MVT::i8));
10714 DAG.getNode(ISD::OR, dl, MVT::i64, rax, Tmp),
10717 return DAG.getMergeValues(Ops, 2, dl);
10720 SDValue X86TargetLowering::LowerBITCAST(SDValue Op,
10721 SelectionDAG &DAG) const {
10722 EVT SrcVT = Op.getOperand(0).getValueType();
10723 EVT DstVT = Op.getValueType();
10724 assert(Subtarget->is64Bit() && !Subtarget->hasSSE2() &&
10725 Subtarget->hasMMX() && "Unexpected custom BITCAST");
10726 assert((DstVT == MVT::i64 ||
10727 (DstVT.isVector() && DstVT.getSizeInBits()==64)) &&
10728 "Unexpected custom BITCAST");
10729 // i64 <=> MMX conversions are Legal.
10730 if (SrcVT==MVT::i64 && DstVT.isVector())
10732 if (DstVT==MVT::i64 && SrcVT.isVector())
10734 // MMX <=> MMX conversions are Legal.
10735 if (SrcVT.isVector() && DstVT.isVector())
10737 // All other conversions need to be expanded.
10741 SDValue X86TargetLowering::LowerLOAD_SUB(SDValue Op, SelectionDAG &DAG) const {
10742 SDNode *Node = Op.getNode();
10743 DebugLoc dl = Node->getDebugLoc();
10744 EVT T = Node->getValueType(0);
10745 SDValue negOp = DAG.getNode(ISD::SUB, dl, T,
10746 DAG.getConstant(0, T), Node->getOperand(2));
10747 return DAG.getAtomic(ISD::ATOMIC_LOAD_ADD, dl,
10748 cast<AtomicSDNode>(Node)->getMemoryVT(),
10749 Node->getOperand(0),
10750 Node->getOperand(1), negOp,
10751 cast<AtomicSDNode>(Node)->getSrcValue(),
10752 cast<AtomicSDNode>(Node)->getAlignment(),
10753 cast<AtomicSDNode>(Node)->getOrdering(),
10754 cast<AtomicSDNode>(Node)->getSynchScope());
10757 static SDValue LowerATOMIC_STORE(SDValue Op, SelectionDAG &DAG) {
10758 SDNode *Node = Op.getNode();
10759 DebugLoc dl = Node->getDebugLoc();
10760 EVT VT = cast<AtomicSDNode>(Node)->getMemoryVT();
10762 // Convert seq_cst store -> xchg
10763 // Convert wide store -> swap (-> cmpxchg8b/cmpxchg16b)
10764 // FIXME: On 32-bit, store -> fist or movq would be more efficient
10765 // (The only way to get a 16-byte store is cmpxchg16b)
10766 // FIXME: 16-byte ATOMIC_SWAP isn't actually hooked up at the moment.
10767 if (cast<AtomicSDNode>(Node)->getOrdering() == SequentiallyConsistent ||
10768 !DAG.getTargetLoweringInfo().isTypeLegal(VT)) {
10769 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_SWAP, dl,
10770 cast<AtomicSDNode>(Node)->getMemoryVT(),
10771 Node->getOperand(0),
10772 Node->getOperand(1), Node->getOperand(2),
10773 cast<AtomicSDNode>(Node)->getMemOperand(),
10774 cast<AtomicSDNode>(Node)->getOrdering(),
10775 cast<AtomicSDNode>(Node)->getSynchScope());
10776 return Swap.getValue(1);
10778 // Other atomic stores have a simple pattern.
10782 static SDValue LowerADDC_ADDE_SUBC_SUBE(SDValue Op, SelectionDAG &DAG) {
10783 EVT VT = Op.getNode()->getValueType(0);
10785 // Let legalize expand this if it isn't a legal type yet.
10786 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
10789 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
10792 bool ExtraOp = false;
10793 switch (Op.getOpcode()) {
10794 default: llvm_unreachable("Invalid code");
10795 case ISD::ADDC: Opc = X86ISD::ADD; break;
10796 case ISD::ADDE: Opc = X86ISD::ADC; ExtraOp = true; break;
10797 case ISD::SUBC: Opc = X86ISD::SUB; break;
10798 case ISD::SUBE: Opc = X86ISD::SBB; ExtraOp = true; break;
10802 return DAG.getNode(Opc, Op->getDebugLoc(), VTs, Op.getOperand(0),
10804 return DAG.getNode(Opc, Op->getDebugLoc(), VTs, Op.getOperand(0),
10805 Op.getOperand(1), Op.getOperand(2));
10808 /// LowerOperation - Provide custom lowering hooks for some operations.
10810 SDValue X86TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
10811 switch (Op.getOpcode()) {
10812 default: llvm_unreachable("Should not custom lower this!");
10813 case ISD::SIGN_EXTEND_INREG: return LowerSIGN_EXTEND_INREG(Op,DAG);
10814 case ISD::MEMBARRIER: return LowerMEMBARRIER(Op,DAG);
10815 case ISD::ATOMIC_FENCE: return LowerATOMIC_FENCE(Op,DAG);
10816 case ISD::ATOMIC_CMP_SWAP: return LowerCMP_SWAP(Op,DAG);
10817 case ISD::ATOMIC_LOAD_SUB: return LowerLOAD_SUB(Op,DAG);
10818 case ISD::ATOMIC_STORE: return LowerATOMIC_STORE(Op,DAG);
10819 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
10820 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG);
10821 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
10822 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
10823 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG);
10824 case ISD::EXTRACT_SUBVECTOR: return LowerEXTRACT_SUBVECTOR(Op, DAG);
10825 case ISD::INSERT_SUBVECTOR: return LowerINSERT_SUBVECTOR(Op, DAG);
10826 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
10827 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
10828 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
10829 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
10830 case ISD::ExternalSymbol: return LowerExternalSymbol(Op, DAG);
10831 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
10832 case ISD::SHL_PARTS:
10833 case ISD::SRA_PARTS:
10834 case ISD::SRL_PARTS: return LowerShiftParts(Op, DAG);
10835 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG);
10836 case ISD::UINT_TO_FP: return LowerUINT_TO_FP(Op, DAG);
10837 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG);
10838 case ISD::FP_TO_UINT: return LowerFP_TO_UINT(Op, DAG);
10839 case ISD::FABS: return LowerFABS(Op, DAG);
10840 case ISD::FNEG: return LowerFNEG(Op, DAG);
10841 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG);
10842 case ISD::FGETSIGN: return LowerFGETSIGN(Op, DAG);
10843 case ISD::SETCC: return LowerSETCC(Op, DAG);
10844 case ISD::SELECT: return LowerSELECT(Op, DAG);
10845 case ISD::BRCOND: return LowerBRCOND(Op, DAG);
10846 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
10847 case ISD::VASTART: return LowerVASTART(Op, DAG);
10848 case ISD::VAARG: return LowerVAARG(Op, DAG);
10849 case ISD::VACOPY: return LowerVACOPY(Op, DAG);
10850 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
10851 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
10852 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
10853 case ISD::FRAME_TO_ARGS_OFFSET:
10854 return LowerFRAME_TO_ARGS_OFFSET(Op, DAG);
10855 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
10856 case ISD::EH_RETURN: return LowerEH_RETURN(Op, DAG);
10857 case ISD::INIT_TRAMPOLINE: return LowerINIT_TRAMPOLINE(Op, DAG);
10858 case ISD::ADJUST_TRAMPOLINE: return LowerADJUST_TRAMPOLINE(Op, DAG);
10859 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
10860 case ISD::CTLZ: return LowerCTLZ(Op, DAG);
10861 case ISD::CTLZ_ZERO_UNDEF: return LowerCTLZ_ZERO_UNDEF(Op, DAG);
10862 case ISD::CTTZ: return LowerCTTZ(Op, DAG);
10863 case ISD::MUL: return LowerMUL(Op, DAG);
10866 case ISD::SHL: return LowerShift(Op, DAG);
10872 case ISD::UMULO: return LowerXALUO(Op, DAG);
10873 case ISD::READCYCLECOUNTER: return LowerREADCYCLECOUNTER(Op, DAG);
10874 case ISD::BITCAST: return LowerBITCAST(Op, DAG);
10878 case ISD::SUBE: return LowerADDC_ADDE_SUBC_SUBE(Op, DAG);
10879 case ISD::ADD: return LowerADD(Op, DAG);
10880 case ISD::SUB: return LowerSUB(Op, DAG);
10884 static void ReplaceATOMIC_LOAD(SDNode *Node,
10885 SmallVectorImpl<SDValue> &Results,
10886 SelectionDAG &DAG) {
10887 DebugLoc dl = Node->getDebugLoc();
10888 EVT VT = cast<AtomicSDNode>(Node)->getMemoryVT();
10890 // Convert wide load -> cmpxchg8b/cmpxchg16b
10891 // FIXME: On 32-bit, load -> fild or movq would be more efficient
10892 // (The only way to get a 16-byte load is cmpxchg16b)
10893 // FIXME: 16-byte ATOMIC_CMP_SWAP isn't actually hooked up at the moment.
10894 SDValue Zero = DAG.getConstant(0, VT);
10895 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_CMP_SWAP, dl, VT,
10896 Node->getOperand(0),
10897 Node->getOperand(1), Zero, Zero,
10898 cast<AtomicSDNode>(Node)->getMemOperand(),
10899 cast<AtomicSDNode>(Node)->getOrdering(),
10900 cast<AtomicSDNode>(Node)->getSynchScope());
10901 Results.push_back(Swap.getValue(0));
10902 Results.push_back(Swap.getValue(1));
10905 void X86TargetLowering::
10906 ReplaceATOMIC_BINARY_64(SDNode *Node, SmallVectorImpl<SDValue>&Results,
10907 SelectionDAG &DAG, unsigned NewOp) const {
10908 DebugLoc dl = Node->getDebugLoc();
10909 assert (Node->getValueType(0) == MVT::i64 &&
10910 "Only know how to expand i64 atomics");
10912 SDValue Chain = Node->getOperand(0);
10913 SDValue In1 = Node->getOperand(1);
10914 SDValue In2L = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
10915 Node->getOperand(2), DAG.getIntPtrConstant(0));
10916 SDValue In2H = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
10917 Node->getOperand(2), DAG.getIntPtrConstant(1));
10918 SDValue Ops[] = { Chain, In1, In2L, In2H };
10919 SDVTList Tys = DAG.getVTList(MVT::i32, MVT::i32, MVT::Other);
10921 DAG.getMemIntrinsicNode(NewOp, dl, Tys, Ops, 4, MVT::i64,
10922 cast<MemSDNode>(Node)->getMemOperand());
10923 SDValue OpsF[] = { Result.getValue(0), Result.getValue(1)};
10924 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, OpsF, 2));
10925 Results.push_back(Result.getValue(2));
10928 /// ReplaceNodeResults - Replace a node with an illegal result type
10929 /// with a new node built out of custom code.
10930 void X86TargetLowering::ReplaceNodeResults(SDNode *N,
10931 SmallVectorImpl<SDValue>&Results,
10932 SelectionDAG &DAG) const {
10933 DebugLoc dl = N->getDebugLoc();
10934 switch (N->getOpcode()) {
10936 llvm_unreachable("Do not know how to custom type legalize this operation!");
10937 case ISD::SIGN_EXTEND_INREG:
10942 // We don't want to expand or promote these.
10944 case ISD::FP_TO_SINT:
10945 case ISD::FP_TO_UINT: {
10946 bool IsSigned = N->getOpcode() == ISD::FP_TO_SINT;
10948 if (!IsSigned && !isIntegerTypeFTOL(SDValue(N, 0).getValueType()))
10951 std::pair<SDValue,SDValue> Vals =
10952 FP_TO_INTHelper(SDValue(N, 0), DAG, IsSigned, /*IsReplace=*/ true);
10953 SDValue FIST = Vals.first, StackSlot = Vals.second;
10954 if (FIST.getNode() != 0) {
10955 EVT VT = N->getValueType(0);
10956 // Return a load from the stack slot.
10957 if (StackSlot.getNode() != 0)
10958 Results.push_back(DAG.getLoad(VT, dl, FIST, StackSlot,
10959 MachinePointerInfo(),
10960 false, false, false, 0));
10962 Results.push_back(FIST);
10966 case ISD::READCYCLECOUNTER: {
10967 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
10968 SDValue TheChain = N->getOperand(0);
10969 SDValue rd = DAG.getNode(X86ISD::RDTSC_DAG, dl, Tys, &TheChain, 1);
10970 SDValue eax = DAG.getCopyFromReg(rd, dl, X86::EAX, MVT::i32,
10972 SDValue edx = DAG.getCopyFromReg(eax.getValue(1), dl, X86::EDX, MVT::i32,
10974 // Use a buildpair to merge the two 32-bit values into a 64-bit one.
10975 SDValue Ops[] = { eax, edx };
10976 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Ops, 2));
10977 Results.push_back(edx.getValue(1));
10980 case ISD::ATOMIC_CMP_SWAP: {
10981 EVT T = N->getValueType(0);
10982 assert((T == MVT::i64 || T == MVT::i128) && "can only expand cmpxchg pair");
10983 bool Regs64bit = T == MVT::i128;
10984 EVT HalfT = Regs64bit ? MVT::i64 : MVT::i32;
10985 SDValue cpInL, cpInH;
10986 cpInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2),
10987 DAG.getConstant(0, HalfT));
10988 cpInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2),
10989 DAG.getConstant(1, HalfT));
10990 cpInL = DAG.getCopyToReg(N->getOperand(0), dl,
10991 Regs64bit ? X86::RAX : X86::EAX,
10993 cpInH = DAG.getCopyToReg(cpInL.getValue(0), dl,
10994 Regs64bit ? X86::RDX : X86::EDX,
10995 cpInH, cpInL.getValue(1));
10996 SDValue swapInL, swapInH;
10997 swapInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3),
10998 DAG.getConstant(0, HalfT));
10999 swapInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3),
11000 DAG.getConstant(1, HalfT));
11001 swapInL = DAG.getCopyToReg(cpInH.getValue(0), dl,
11002 Regs64bit ? X86::RBX : X86::EBX,
11003 swapInL, cpInH.getValue(1));
11004 swapInH = DAG.getCopyToReg(swapInL.getValue(0), dl,
11005 Regs64bit ? X86::RCX : X86::ECX,
11006 swapInH, swapInL.getValue(1));
11007 SDValue Ops[] = { swapInH.getValue(0),
11009 swapInH.getValue(1) };
11010 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
11011 MachineMemOperand *MMO = cast<AtomicSDNode>(N)->getMemOperand();
11012 unsigned Opcode = Regs64bit ? X86ISD::LCMPXCHG16_DAG :
11013 X86ISD::LCMPXCHG8_DAG;
11014 SDValue Result = DAG.getMemIntrinsicNode(Opcode, dl, Tys,
11016 SDValue cpOutL = DAG.getCopyFromReg(Result.getValue(0), dl,
11017 Regs64bit ? X86::RAX : X86::EAX,
11018 HalfT, Result.getValue(1));
11019 SDValue cpOutH = DAG.getCopyFromReg(cpOutL.getValue(1), dl,
11020 Regs64bit ? X86::RDX : X86::EDX,
11021 HalfT, cpOutL.getValue(2));
11022 SDValue OpsF[] = { cpOutL.getValue(0), cpOutH.getValue(0)};
11023 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, T, OpsF, 2));
11024 Results.push_back(cpOutH.getValue(1));
11027 case ISD::ATOMIC_LOAD_ADD:
11028 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMADD64_DAG);
11030 case ISD::ATOMIC_LOAD_AND:
11031 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMAND64_DAG);
11033 case ISD::ATOMIC_LOAD_NAND:
11034 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMNAND64_DAG);
11036 case ISD::ATOMIC_LOAD_OR:
11037 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMOR64_DAG);
11039 case ISD::ATOMIC_LOAD_SUB:
11040 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMSUB64_DAG);
11042 case ISD::ATOMIC_LOAD_XOR:
11043 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMXOR64_DAG);
11045 case ISD::ATOMIC_SWAP:
11046 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMSWAP64_DAG);
11048 case ISD::ATOMIC_LOAD:
11049 ReplaceATOMIC_LOAD(N, Results, DAG);
11053 const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
11055 default: return NULL;
11056 case X86ISD::BSF: return "X86ISD::BSF";
11057 case X86ISD::BSR: return "X86ISD::BSR";
11058 case X86ISD::SHLD: return "X86ISD::SHLD";
11059 case X86ISD::SHRD: return "X86ISD::SHRD";
11060 case X86ISD::FAND: return "X86ISD::FAND";
11061 case X86ISD::FOR: return "X86ISD::FOR";
11062 case X86ISD::FXOR: return "X86ISD::FXOR";
11063 case X86ISD::FSRL: return "X86ISD::FSRL";
11064 case X86ISD::FILD: return "X86ISD::FILD";
11065 case X86ISD::FILD_FLAG: return "X86ISD::FILD_FLAG";
11066 case X86ISD::FP_TO_INT16_IN_MEM: return "X86ISD::FP_TO_INT16_IN_MEM";
11067 case X86ISD::FP_TO_INT32_IN_MEM: return "X86ISD::FP_TO_INT32_IN_MEM";
11068 case X86ISD::FP_TO_INT64_IN_MEM: return "X86ISD::FP_TO_INT64_IN_MEM";
11069 case X86ISD::FLD: return "X86ISD::FLD";
11070 case X86ISD::FST: return "X86ISD::FST";
11071 case X86ISD::CALL: return "X86ISD::CALL";
11072 case X86ISD::RDTSC_DAG: return "X86ISD::RDTSC_DAG";
11073 case X86ISD::BT: return "X86ISD::BT";
11074 case X86ISD::CMP: return "X86ISD::CMP";
11075 case X86ISD::COMI: return "X86ISD::COMI";
11076 case X86ISD::UCOMI: return "X86ISD::UCOMI";
11077 case X86ISD::SETCC: return "X86ISD::SETCC";
11078 case X86ISD::SETCC_CARRY: return "X86ISD::SETCC_CARRY";
11079 case X86ISD::FSETCCsd: return "X86ISD::FSETCCsd";
11080 case X86ISD::FSETCCss: return "X86ISD::FSETCCss";
11081 case X86ISD::CMOV: return "X86ISD::CMOV";
11082 case X86ISD::BRCOND: return "X86ISD::BRCOND";
11083 case X86ISD::RET_FLAG: return "X86ISD::RET_FLAG";
11084 case X86ISD::REP_STOS: return "X86ISD::REP_STOS";
11085 case X86ISD::REP_MOVS: return "X86ISD::REP_MOVS";
11086 case X86ISD::GlobalBaseReg: return "X86ISD::GlobalBaseReg";
11087 case X86ISD::Wrapper: return "X86ISD::Wrapper";
11088 case X86ISD::WrapperRIP: return "X86ISD::WrapperRIP";
11089 case X86ISD::PEXTRB: return "X86ISD::PEXTRB";
11090 case X86ISD::PEXTRW: return "X86ISD::PEXTRW";
11091 case X86ISD::INSERTPS: return "X86ISD::INSERTPS";
11092 case X86ISD::PINSRB: return "X86ISD::PINSRB";
11093 case X86ISD::PINSRW: return "X86ISD::PINSRW";
11094 case X86ISD::PSHUFB: return "X86ISD::PSHUFB";
11095 case X86ISD::ANDNP: return "X86ISD::ANDNP";
11096 case X86ISD::PSIGN: return "X86ISD::PSIGN";
11097 case X86ISD::BLENDV: return "X86ISD::BLENDV";
11098 case X86ISD::BLENDPW: return "X86ISD::BLENDPW";
11099 case X86ISD::BLENDPS: return "X86ISD::BLENDPS";
11100 case X86ISD::BLENDPD: return "X86ISD::BLENDPD";
11101 case X86ISD::HADD: return "X86ISD::HADD";
11102 case X86ISD::HSUB: return "X86ISD::HSUB";
11103 case X86ISD::FHADD: return "X86ISD::FHADD";
11104 case X86ISD::FHSUB: return "X86ISD::FHSUB";
11105 case X86ISD::FMAX: return "X86ISD::FMAX";
11106 case X86ISD::FMIN: return "X86ISD::FMIN";
11107 case X86ISD::FRSQRT: return "X86ISD::FRSQRT";
11108 case X86ISD::FRCP: return "X86ISD::FRCP";
11109 case X86ISD::TLSADDR: return "X86ISD::TLSADDR";
11110 case X86ISD::TLSCALL: return "X86ISD::TLSCALL";
11111 case X86ISD::EH_RETURN: return "X86ISD::EH_RETURN";
11112 case X86ISD::TC_RETURN: return "X86ISD::TC_RETURN";
11113 case X86ISD::FNSTCW16m: return "X86ISD::FNSTCW16m";
11114 case X86ISD::LCMPXCHG_DAG: return "X86ISD::LCMPXCHG_DAG";
11115 case X86ISD::LCMPXCHG8_DAG: return "X86ISD::LCMPXCHG8_DAG";
11116 case X86ISD::ATOMADD64_DAG: return "X86ISD::ATOMADD64_DAG";
11117 case X86ISD::ATOMSUB64_DAG: return "X86ISD::ATOMSUB64_DAG";
11118 case X86ISD::ATOMOR64_DAG: return "X86ISD::ATOMOR64_DAG";
11119 case X86ISD::ATOMXOR64_DAG: return "X86ISD::ATOMXOR64_DAG";
11120 case X86ISD::ATOMAND64_DAG: return "X86ISD::ATOMAND64_DAG";
11121 case X86ISD::ATOMNAND64_DAG: return "X86ISD::ATOMNAND64_DAG";
11122 case X86ISD::VZEXT_MOVL: return "X86ISD::VZEXT_MOVL";
11123 case X86ISD::VZEXT_LOAD: return "X86ISD::VZEXT_LOAD";
11124 case X86ISD::VSHLDQ: return "X86ISD::VSHLDQ";
11125 case X86ISD::VSRLDQ: return "X86ISD::VSRLDQ";
11126 case X86ISD::VSHL: return "X86ISD::VSHL";
11127 case X86ISD::VSRL: return "X86ISD::VSRL";
11128 case X86ISD::VSRA: return "X86ISD::VSRA";
11129 case X86ISD::VSHLI: return "X86ISD::VSHLI";
11130 case X86ISD::VSRLI: return "X86ISD::VSRLI";
11131 case X86ISD::VSRAI: return "X86ISD::VSRAI";
11132 case X86ISD::CMPP: return "X86ISD::CMPP";
11133 case X86ISD::PCMPEQ: return "X86ISD::PCMPEQ";
11134 case X86ISD::PCMPGT: return "X86ISD::PCMPGT";
11135 case X86ISD::ADD: return "X86ISD::ADD";
11136 case X86ISD::SUB: return "X86ISD::SUB";
11137 case X86ISD::ADC: return "X86ISD::ADC";
11138 case X86ISD::SBB: return "X86ISD::SBB";
11139 case X86ISD::SMUL: return "X86ISD::SMUL";
11140 case X86ISD::UMUL: return "X86ISD::UMUL";
11141 case X86ISD::INC: return "X86ISD::INC";
11142 case X86ISD::DEC: return "X86ISD::DEC";
11143 case X86ISD::OR: return "X86ISD::OR";
11144 case X86ISD::XOR: return "X86ISD::XOR";
11145 case X86ISD::AND: return "X86ISD::AND";
11146 case X86ISD::ANDN: return "X86ISD::ANDN";
11147 case X86ISD::BLSI: return "X86ISD::BLSI";
11148 case X86ISD::BLSMSK: return "X86ISD::BLSMSK";
11149 case X86ISD::BLSR: return "X86ISD::BLSR";
11150 case X86ISD::MUL_IMM: return "X86ISD::MUL_IMM";
11151 case X86ISD::PTEST: return "X86ISD::PTEST";
11152 case X86ISD::TESTP: return "X86ISD::TESTP";
11153 case X86ISD::PALIGN: return "X86ISD::PALIGN";
11154 case X86ISD::PSHUFD: return "X86ISD::PSHUFD";
11155 case X86ISD::PSHUFHW: return "X86ISD::PSHUFHW";
11156 case X86ISD::PSHUFLW: return "X86ISD::PSHUFLW";
11157 case X86ISD::SHUFP: return "X86ISD::SHUFP";
11158 case X86ISD::MOVLHPS: return "X86ISD::MOVLHPS";
11159 case X86ISD::MOVLHPD: return "X86ISD::MOVLHPD";
11160 case X86ISD::MOVHLPS: return "X86ISD::MOVHLPS";
11161 case X86ISD::MOVLPS: return "X86ISD::MOVLPS";
11162 case X86ISD::MOVLPD: return "X86ISD::MOVLPD";
11163 case X86ISD::MOVDDUP: return "X86ISD::MOVDDUP";
11164 case X86ISD::MOVSHDUP: return "X86ISD::MOVSHDUP";
11165 case X86ISD::MOVSLDUP: return "X86ISD::MOVSLDUP";
11166 case X86ISD::MOVSD: return "X86ISD::MOVSD";
11167 case X86ISD::MOVSS: return "X86ISD::MOVSS";
11168 case X86ISD::UNPCKL: return "X86ISD::UNPCKL";
11169 case X86ISD::UNPCKH: return "X86ISD::UNPCKH";
11170 case X86ISD::VBROADCAST: return "X86ISD::VBROADCAST";
11171 case X86ISD::VPERMILP: return "X86ISD::VPERMILP";
11172 case X86ISD::VPERM2X128: return "X86ISD::VPERM2X128";
11173 case X86ISD::VPERMV: return "X86ISD::VPERMV";
11174 case X86ISD::VPERMI: return "X86ISD::VPERMI";
11175 case X86ISD::PMULUDQ: return "X86ISD::PMULUDQ";
11176 case X86ISD::VASTART_SAVE_XMM_REGS: return "X86ISD::VASTART_SAVE_XMM_REGS";
11177 case X86ISD::VAARG_64: return "X86ISD::VAARG_64";
11178 case X86ISD::WIN_ALLOCA: return "X86ISD::WIN_ALLOCA";
11179 case X86ISD::MEMBARRIER: return "X86ISD::MEMBARRIER";
11180 case X86ISD::SEG_ALLOCA: return "X86ISD::SEG_ALLOCA";
11181 case X86ISD::WIN_FTOL: return "X86ISD::WIN_FTOL";
11185 // isLegalAddressingMode - Return true if the addressing mode represented
11186 // by AM is legal for this target, for a load/store of the specified type.
11187 bool X86TargetLowering::isLegalAddressingMode(const AddrMode &AM,
11189 // X86 supports extremely general addressing modes.
11190 CodeModel::Model M = getTargetMachine().getCodeModel();
11191 Reloc::Model R = getTargetMachine().getRelocationModel();
11193 // X86 allows a sign-extended 32-bit immediate field as a displacement.
11194 if (!X86::isOffsetSuitableForCodeModel(AM.BaseOffs, M, AM.BaseGV != NULL))
11199 Subtarget->ClassifyGlobalReference(AM.BaseGV, getTargetMachine());
11201 // If a reference to this global requires an extra load, we can't fold it.
11202 if (isGlobalStubReference(GVFlags))
11205 // If BaseGV requires a register for the PIC base, we cannot also have a
11206 // BaseReg specified.
11207 if (AM.HasBaseReg && isGlobalRelativeToPICBase(GVFlags))
11210 // If lower 4G is not available, then we must use rip-relative addressing.
11211 if ((M != CodeModel::Small || R != Reloc::Static) &&
11212 Subtarget->is64Bit() && (AM.BaseOffs || AM.Scale > 1))
11216 switch (AM.Scale) {
11222 // These scales always work.
11227 // These scales are formed with basereg+scalereg. Only accept if there is
11232 default: // Other stuff never works.
11240 bool X86TargetLowering::isTruncateFree(Type *Ty1, Type *Ty2) const {
11241 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
11243 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits();
11244 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits();
11245 if (NumBits1 <= NumBits2)
11250 bool X86TargetLowering::isTruncateFree(EVT VT1, EVT VT2) const {
11251 if (!VT1.isInteger() || !VT2.isInteger())
11253 unsigned NumBits1 = VT1.getSizeInBits();
11254 unsigned NumBits2 = VT2.getSizeInBits();
11255 if (NumBits1 <= NumBits2)
11260 bool X86TargetLowering::isZExtFree(Type *Ty1, Type *Ty2) const {
11261 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
11262 return Ty1->isIntegerTy(32) && Ty2->isIntegerTy(64) && Subtarget->is64Bit();
11265 bool X86TargetLowering::isZExtFree(EVT VT1, EVT VT2) const {
11266 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
11267 return VT1 == MVT::i32 && VT2 == MVT::i64 && Subtarget->is64Bit();
11270 bool X86TargetLowering::isNarrowingProfitable(EVT VT1, EVT VT2) const {
11271 // i16 instructions are longer (0x66 prefix) and potentially slower.
11272 return !(VT1 == MVT::i32 && VT2 == MVT::i16);
11275 /// isShuffleMaskLegal - Targets can use this to indicate that they only
11276 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
11277 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
11278 /// are assumed to be legal.
11280 X86TargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M,
11282 // Very little shuffling can be done for 64-bit vectors right now.
11283 if (VT.getSizeInBits() == 64)
11286 // FIXME: pshufb, blends, shifts.
11287 return (VT.getVectorNumElements() == 2 ||
11288 ShuffleVectorSDNode::isSplatMask(&M[0], VT) ||
11289 isMOVLMask(M, VT) ||
11290 isSHUFPMask(M, VT, Subtarget->hasAVX()) ||
11291 isPSHUFDMask(M, VT) ||
11292 isPSHUFHWMask(M, VT) ||
11293 isPSHUFLWMask(M, VT) ||
11294 isPALIGNRMask(M, VT, Subtarget) ||
11295 isUNPCKLMask(M, VT, Subtarget->hasAVX2()) ||
11296 isUNPCKHMask(M, VT, Subtarget->hasAVX2()) ||
11297 isUNPCKL_v_undef_Mask(M, VT, Subtarget->hasAVX2()) ||
11298 isUNPCKH_v_undef_Mask(M, VT, Subtarget->hasAVX2()));
11302 X86TargetLowering::isVectorClearMaskLegal(const SmallVectorImpl<int> &Mask,
11304 unsigned NumElts = VT.getVectorNumElements();
11305 // FIXME: This collection of masks seems suspect.
11308 if (NumElts == 4 && VT.getSizeInBits() == 128) {
11309 return (isMOVLMask(Mask, VT) ||
11310 isCommutedMOVLMask(Mask, VT, true) ||
11311 isSHUFPMask(Mask, VT, Subtarget->hasAVX()) ||
11312 isSHUFPMask(Mask, VT, Subtarget->hasAVX(), /* Commuted */ true));
11317 //===----------------------------------------------------------------------===//
11318 // X86 Scheduler Hooks
11319 //===----------------------------------------------------------------------===//
11321 // private utility function
11322 MachineBasicBlock *
11323 X86TargetLowering::EmitAtomicBitwiseWithCustomInserter(MachineInstr *bInstr,
11324 MachineBasicBlock *MBB,
11331 const TargetRegisterClass *RC,
11332 bool Invert) const {
11333 // For the atomic bitwise operator, we generate
11336 // ld t1 = [bitinstr.addr]
11337 // op t2 = t1, [bitinstr.val]
11338 // not t3 = t2 (if Invert)
11340 // lcs dest = [bitinstr.addr], t3 [EAX is implicit]
11342 // fallthrough -->nextMBB
11343 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
11344 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
11345 MachineFunction::iterator MBBIter = MBB;
11348 /// First build the CFG
11349 MachineFunction *F = MBB->getParent();
11350 MachineBasicBlock *thisMBB = MBB;
11351 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB);
11352 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB);
11353 F->insert(MBBIter, newMBB);
11354 F->insert(MBBIter, nextMBB);
11356 // Transfer the remainder of thisMBB and its successor edges to nextMBB.
11357 nextMBB->splice(nextMBB->begin(), thisMBB,
11358 llvm::next(MachineBasicBlock::iterator(bInstr)),
11360 nextMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
11362 // Update thisMBB to fall through to newMBB
11363 thisMBB->addSuccessor(newMBB);
11365 // newMBB jumps to itself and fall through to nextMBB
11366 newMBB->addSuccessor(nextMBB);
11367 newMBB->addSuccessor(newMBB);
11369 // Insert instructions into newMBB based on incoming instruction
11370 assert(bInstr->getNumOperands() < X86::AddrNumOperands + 4 &&
11371 "unexpected number of operands");
11372 DebugLoc dl = bInstr->getDebugLoc();
11373 MachineOperand& destOper = bInstr->getOperand(0);
11374 MachineOperand* argOpers[2 + X86::AddrNumOperands];
11375 int numArgs = bInstr->getNumOperands() - 1;
11376 for (int i=0; i < numArgs; ++i)
11377 argOpers[i] = &bInstr->getOperand(i+1);
11379 // x86 address has 4 operands: base, index, scale, and displacement
11380 int lastAddrIndx = X86::AddrNumOperands - 1; // [0,3]
11381 int valArgIndx = lastAddrIndx + 1;
11383 unsigned t1 = F->getRegInfo().createVirtualRegister(RC);
11384 MachineInstrBuilder MIB = BuildMI(newMBB, dl, TII->get(LoadOpc), t1);
11385 for (int i=0; i <= lastAddrIndx; ++i)
11386 (*MIB).addOperand(*argOpers[i]);
11388 unsigned t2 = F->getRegInfo().createVirtualRegister(RC);
11389 assert((argOpers[valArgIndx]->isReg() ||
11390 argOpers[valArgIndx]->isImm()) &&
11391 "invalid operand");
11392 if (argOpers[valArgIndx]->isReg())
11393 MIB = BuildMI(newMBB, dl, TII->get(regOpc), t2);
11395 MIB = BuildMI(newMBB, dl, TII->get(immOpc), t2);
11397 (*MIB).addOperand(*argOpers[valArgIndx]);
11399 unsigned t3 = F->getRegInfo().createVirtualRegister(RC);
11401 MIB = BuildMI(newMBB, dl, TII->get(notOpc), t3).addReg(t2);
11406 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), EAXreg);
11409 MIB = BuildMI(newMBB, dl, TII->get(CXchgOpc));
11410 for (int i=0; i <= lastAddrIndx; ++i)
11411 (*MIB).addOperand(*argOpers[i]);
11413 assert(bInstr->hasOneMemOperand() && "Unexpected number of memoperand");
11414 (*MIB).setMemRefs(bInstr->memoperands_begin(),
11415 bInstr->memoperands_end());
11417 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), destOper.getReg());
11418 MIB.addReg(EAXreg);
11421 BuildMI(newMBB, dl, TII->get(X86::JNE_4)).addMBB(newMBB);
11423 bInstr->eraseFromParent(); // The pseudo instruction is gone now.
11427 // private utility function: 64 bit atomics on 32 bit host.
11428 MachineBasicBlock *
11429 X86TargetLowering::EmitAtomicBit6432WithCustomInserter(MachineInstr *bInstr,
11430 MachineBasicBlock *MBB,
11435 bool Invert) const {
11436 // For the atomic bitwise operator, we generate
11437 // thisMBB (instructions are in pairs, except cmpxchg8b)
11438 // ld t1,t2 = [bitinstr.addr]
11440 // out1, out2 = phi (thisMBB, t1/t2) (newMBB, t3/t4)
11441 // op t5, t6 <- out1, out2, [bitinstr.val]
11442 // (for SWAP, substitute: mov t5, t6 <- [bitinstr.val])
11443 // neg t7, t8 < t5, t6 (if Invert)
11444 // mov ECX, EBX <- t5, t6
11445 // mov EAX, EDX <- t1, t2
11446 // cmpxchg8b [bitinstr.addr] [EAX, EDX, EBX, ECX implicit]
11447 // mov t3, t4 <- EAX, EDX
11449 // result in out1, out2
11450 // fallthrough -->nextMBB
11452 const TargetRegisterClass *RC = &X86::GR32RegClass;
11453 const unsigned LoadOpc = X86::MOV32rm;
11454 const unsigned NotOpc = X86::NOT32r;
11455 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
11456 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
11457 MachineFunction::iterator MBBIter = MBB;
11460 /// First build the CFG
11461 MachineFunction *F = MBB->getParent();
11462 MachineBasicBlock *thisMBB = MBB;
11463 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB);
11464 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB);
11465 F->insert(MBBIter, newMBB);
11466 F->insert(MBBIter, nextMBB);
11468 // Transfer the remainder of thisMBB and its successor edges to nextMBB.
11469 nextMBB->splice(nextMBB->begin(), thisMBB,
11470 llvm::next(MachineBasicBlock::iterator(bInstr)),
11472 nextMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
11474 // Update thisMBB to fall through to newMBB
11475 thisMBB->addSuccessor(newMBB);
11477 // newMBB jumps to itself and fall through to nextMBB
11478 newMBB->addSuccessor(nextMBB);
11479 newMBB->addSuccessor(newMBB);
11481 DebugLoc dl = bInstr->getDebugLoc();
11482 // Insert instructions into newMBB based on incoming instruction
11483 // There are 8 "real" operands plus 9 implicit def/uses, ignored here.
11484 assert(bInstr->getNumOperands() < X86::AddrNumOperands + 14 &&
11485 "unexpected number of operands");
11486 MachineOperand& dest1Oper = bInstr->getOperand(0);
11487 MachineOperand& dest2Oper = bInstr->getOperand(1);
11488 MachineOperand* argOpers[2 + X86::AddrNumOperands];
11489 for (int i=0; i < 2 + X86::AddrNumOperands; ++i) {
11490 argOpers[i] = &bInstr->getOperand(i+2);
11492 // We use some of the operands multiple times, so conservatively just
11493 // clear any kill flags that might be present.
11494 if (argOpers[i]->isReg() && argOpers[i]->isUse())
11495 argOpers[i]->setIsKill(false);
11498 // x86 address has 5 operands: base, index, scale, displacement, and segment.
11499 int lastAddrIndx = X86::AddrNumOperands - 1; // [0,3]
11501 unsigned t1 = F->getRegInfo().createVirtualRegister(RC);
11502 MachineInstrBuilder MIB = BuildMI(thisMBB, dl, TII->get(LoadOpc), t1);
11503 for (int i=0; i <= lastAddrIndx; ++i)
11504 (*MIB).addOperand(*argOpers[i]);
11505 unsigned t2 = F->getRegInfo().createVirtualRegister(RC);
11506 MIB = BuildMI(thisMBB, dl, TII->get(LoadOpc), t2);
11507 // add 4 to displacement.
11508 for (int i=0; i <= lastAddrIndx-2; ++i)
11509 (*MIB).addOperand(*argOpers[i]);
11510 MachineOperand newOp3 = *(argOpers[3]);
11511 if (newOp3.isImm())
11512 newOp3.setImm(newOp3.getImm()+4);
11514 newOp3.setOffset(newOp3.getOffset()+4);
11515 (*MIB).addOperand(newOp3);
11516 (*MIB).addOperand(*argOpers[lastAddrIndx]);
11518 // t3/4 are defined later, at the bottom of the loop
11519 unsigned t3 = F->getRegInfo().createVirtualRegister(RC);
11520 unsigned t4 = F->getRegInfo().createVirtualRegister(RC);
11521 BuildMI(newMBB, dl, TII->get(X86::PHI), dest1Oper.getReg())
11522 .addReg(t1).addMBB(thisMBB).addReg(t3).addMBB(newMBB);
11523 BuildMI(newMBB, dl, TII->get(X86::PHI), dest2Oper.getReg())
11524 .addReg(t2).addMBB(thisMBB).addReg(t4).addMBB(newMBB);
11526 // The subsequent operations should be using the destination registers of
11527 // the PHI instructions.
11528 t1 = dest1Oper.getReg();
11529 t2 = dest2Oper.getReg();
11531 int valArgIndx = lastAddrIndx + 1;
11532 assert((argOpers[valArgIndx]->isReg() ||
11533 argOpers[valArgIndx]->isImm()) &&
11534 "invalid operand");
11535 unsigned t5 = F->getRegInfo().createVirtualRegister(RC);
11536 unsigned t6 = F->getRegInfo().createVirtualRegister(RC);
11537 if (argOpers[valArgIndx]->isReg())
11538 MIB = BuildMI(newMBB, dl, TII->get(regOpcL), t5);
11540 MIB = BuildMI(newMBB, dl, TII->get(immOpcL), t5);
11541 if (regOpcL != X86::MOV32rr)
11543 (*MIB).addOperand(*argOpers[valArgIndx]);
11544 assert(argOpers[valArgIndx + 1]->isReg() ==
11545 argOpers[valArgIndx]->isReg());
11546 assert(argOpers[valArgIndx + 1]->isImm() ==
11547 argOpers[valArgIndx]->isImm());
11548 if (argOpers[valArgIndx + 1]->isReg())
11549 MIB = BuildMI(newMBB, dl, TII->get(regOpcH), t6);
11551 MIB = BuildMI(newMBB, dl, TII->get(immOpcH), t6);
11552 if (regOpcH != X86::MOV32rr)
11554 (*MIB).addOperand(*argOpers[valArgIndx + 1]);
11558 t7 = F->getRegInfo().createVirtualRegister(RC);
11559 t8 = F->getRegInfo().createVirtualRegister(RC);
11560 MIB = BuildMI(newMBB, dl, TII->get(NotOpc), t7).addReg(t5);
11561 MIB = BuildMI(newMBB, dl, TII->get(NotOpc), t8).addReg(t6);
11567 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::EAX);
11569 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::EDX);
11572 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::EBX);
11574 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::ECX);
11577 MIB = BuildMI(newMBB, dl, TII->get(X86::LCMPXCHG8B));
11578 for (int i=0; i <= lastAddrIndx; ++i)
11579 (*MIB).addOperand(*argOpers[i]);
11581 assert(bInstr->hasOneMemOperand() && "Unexpected number of memoperand");
11582 (*MIB).setMemRefs(bInstr->memoperands_begin(),
11583 bInstr->memoperands_end());
11585 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), t3);
11586 MIB.addReg(X86::EAX);
11587 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), t4);
11588 MIB.addReg(X86::EDX);
11591 BuildMI(newMBB, dl, TII->get(X86::JNE_4)).addMBB(newMBB);
11593 bInstr->eraseFromParent(); // The pseudo instruction is gone now.
11597 // private utility function
11598 MachineBasicBlock *
11599 X86TargetLowering::EmitAtomicMinMaxWithCustomInserter(MachineInstr *mInstr,
11600 MachineBasicBlock *MBB,
11601 unsigned cmovOpc) const {
11602 // For the atomic min/max operator, we generate
11605 // ld t1 = [min/max.addr]
11606 // mov t2 = [min/max.val]
11608 // cmov[cond] t2 = t1
11610 // lcs dest = [bitinstr.addr], t2 [EAX is implicit]
11612 // fallthrough -->nextMBB
11614 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
11615 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
11616 MachineFunction::iterator MBBIter = MBB;
11619 /// First build the CFG
11620 MachineFunction *F = MBB->getParent();
11621 MachineBasicBlock *thisMBB = MBB;
11622 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB);
11623 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB);
11624 F->insert(MBBIter, newMBB);
11625 F->insert(MBBIter, nextMBB);
11627 // Transfer the remainder of thisMBB and its successor edges to nextMBB.
11628 nextMBB->splice(nextMBB->begin(), thisMBB,
11629 llvm::next(MachineBasicBlock::iterator(mInstr)),
11631 nextMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
11633 // Update thisMBB to fall through to newMBB
11634 thisMBB->addSuccessor(newMBB);
11636 // newMBB jumps to newMBB and fall through to nextMBB
11637 newMBB->addSuccessor(nextMBB);
11638 newMBB->addSuccessor(newMBB);
11640 DebugLoc dl = mInstr->getDebugLoc();
11641 // Insert instructions into newMBB based on incoming instruction
11642 assert(mInstr->getNumOperands() < X86::AddrNumOperands + 4 &&
11643 "unexpected number of operands");
11644 MachineOperand& destOper = mInstr->getOperand(0);
11645 MachineOperand* argOpers[2 + X86::AddrNumOperands];
11646 int numArgs = mInstr->getNumOperands() - 1;
11647 for (int i=0; i < numArgs; ++i)
11648 argOpers[i] = &mInstr->getOperand(i+1);
11650 // x86 address has 4 operands: base, index, scale, and displacement
11651 int lastAddrIndx = X86::AddrNumOperands - 1; // [0,3]
11652 int valArgIndx = lastAddrIndx + 1;
11654 unsigned t1 = F->getRegInfo().createVirtualRegister(&X86::GR32RegClass);
11655 MachineInstrBuilder MIB = BuildMI(newMBB, dl, TII->get(X86::MOV32rm), t1);
11656 for (int i=0; i <= lastAddrIndx; ++i)
11657 (*MIB).addOperand(*argOpers[i]);
11659 // We only support register and immediate values
11660 assert((argOpers[valArgIndx]->isReg() ||
11661 argOpers[valArgIndx]->isImm()) &&
11662 "invalid operand");
11664 unsigned t2 = F->getRegInfo().createVirtualRegister(&X86::GR32RegClass);
11665 if (argOpers[valArgIndx]->isReg())
11666 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), t2);
11668 MIB = BuildMI(newMBB, dl, TII->get(X86::MOV32rr), t2);
11669 (*MIB).addOperand(*argOpers[valArgIndx]);
11671 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::EAX);
11674 MIB = BuildMI(newMBB, dl, TII->get(X86::CMP32rr));
11679 unsigned t3 = F->getRegInfo().createVirtualRegister(&X86::GR32RegClass);
11680 MIB = BuildMI(newMBB, dl, TII->get(cmovOpc),t3);
11684 // Cmp and exchange if none has modified the memory location
11685 MIB = BuildMI(newMBB, dl, TII->get(X86::LCMPXCHG32));
11686 for (int i=0; i <= lastAddrIndx; ++i)
11687 (*MIB).addOperand(*argOpers[i]);
11689 assert(mInstr->hasOneMemOperand() && "Unexpected number of memoperand");
11690 (*MIB).setMemRefs(mInstr->memoperands_begin(),
11691 mInstr->memoperands_end());
11693 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), destOper.getReg());
11694 MIB.addReg(X86::EAX);
11697 BuildMI(newMBB, dl, TII->get(X86::JNE_4)).addMBB(newMBB);
11699 mInstr->eraseFromParent(); // The pseudo instruction is gone now.
11703 // FIXME: When we get size specific XMM0 registers, i.e. XMM0_V16I8
11704 // or XMM0_V32I8 in AVX all of this code can be replaced with that
11705 // in the .td file.
11706 MachineBasicBlock *
11707 X86TargetLowering::EmitPCMP(MachineInstr *MI, MachineBasicBlock *BB,
11708 unsigned numArgs, bool memArg) const {
11709 assert(Subtarget->hasSSE42() &&
11710 "Target must have SSE4.2 or AVX features enabled");
11712 DebugLoc dl = MI->getDebugLoc();
11713 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
11715 if (!Subtarget->hasAVX()) {
11717 Opc = numArgs == 3 ? X86::PCMPISTRM128rm : X86::PCMPESTRM128rm;
11719 Opc = numArgs == 3 ? X86::PCMPISTRM128rr : X86::PCMPESTRM128rr;
11722 Opc = numArgs == 3 ? X86::VPCMPISTRM128rm : X86::VPCMPESTRM128rm;
11724 Opc = numArgs == 3 ? X86::VPCMPISTRM128rr : X86::VPCMPESTRM128rr;
11727 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(Opc));
11728 for (unsigned i = 0; i < numArgs; ++i) {
11729 MachineOperand &Op = MI->getOperand(i+1);
11730 if (!(Op.isReg() && Op.isImplicit()))
11731 MIB.addOperand(Op);
11733 BuildMI(*BB, MI, dl,
11734 TII->get(Subtarget->hasAVX() ? X86::VMOVAPSrr : X86::MOVAPSrr),
11735 MI->getOperand(0).getReg())
11736 .addReg(X86::XMM0);
11738 MI->eraseFromParent();
11742 MachineBasicBlock *
11743 X86TargetLowering::EmitMonitor(MachineInstr *MI, MachineBasicBlock *BB) const {
11744 DebugLoc dl = MI->getDebugLoc();
11745 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
11747 // Address into RAX/EAX, other two args into ECX, EDX.
11748 unsigned MemOpc = Subtarget->is64Bit() ? X86::LEA64r : X86::LEA32r;
11749 unsigned MemReg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
11750 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(MemOpc), MemReg);
11751 for (int i = 0; i < X86::AddrNumOperands; ++i)
11752 MIB.addOperand(MI->getOperand(i));
11754 unsigned ValOps = X86::AddrNumOperands;
11755 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::ECX)
11756 .addReg(MI->getOperand(ValOps).getReg());
11757 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::EDX)
11758 .addReg(MI->getOperand(ValOps+1).getReg());
11760 // The instruction doesn't actually take any operands though.
11761 BuildMI(*BB, MI, dl, TII->get(X86::MONITORrrr));
11763 MI->eraseFromParent(); // The pseudo is gone now.
11767 MachineBasicBlock *
11768 X86TargetLowering::EmitMwait(MachineInstr *MI, MachineBasicBlock *BB) const {
11769 DebugLoc dl = MI->getDebugLoc();
11770 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
11772 // First arg in ECX, the second in EAX.
11773 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::ECX)
11774 .addReg(MI->getOperand(0).getReg());
11775 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::EAX)
11776 .addReg(MI->getOperand(1).getReg());
11778 // The instruction doesn't actually take any operands though.
11779 BuildMI(*BB, MI, dl, TII->get(X86::MWAITrr));
11781 MI->eraseFromParent(); // The pseudo is gone now.
11785 MachineBasicBlock *
11786 X86TargetLowering::EmitVAARG64WithCustomInserter(
11788 MachineBasicBlock *MBB) const {
11789 // Emit va_arg instruction on X86-64.
11791 // Operands to this pseudo-instruction:
11792 // 0 ) Output : destination address (reg)
11793 // 1-5) Input : va_list address (addr, i64mem)
11794 // 6 ) ArgSize : Size (in bytes) of vararg type
11795 // 7 ) ArgMode : 0=overflow only, 1=use gp_offset, 2=use fp_offset
11796 // 8 ) Align : Alignment of type
11797 // 9 ) EFLAGS (implicit-def)
11799 assert(MI->getNumOperands() == 10 && "VAARG_64 should have 10 operands!");
11800 assert(X86::AddrNumOperands == 5 && "VAARG_64 assumes 5 address operands");
11802 unsigned DestReg = MI->getOperand(0).getReg();
11803 MachineOperand &Base = MI->getOperand(1);
11804 MachineOperand &Scale = MI->getOperand(2);
11805 MachineOperand &Index = MI->getOperand(3);
11806 MachineOperand &Disp = MI->getOperand(4);
11807 MachineOperand &Segment = MI->getOperand(5);
11808 unsigned ArgSize = MI->getOperand(6).getImm();
11809 unsigned ArgMode = MI->getOperand(7).getImm();
11810 unsigned Align = MI->getOperand(8).getImm();
11812 // Memory Reference
11813 assert(MI->hasOneMemOperand() && "Expected VAARG_64 to have one memoperand");
11814 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
11815 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
11817 // Machine Information
11818 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
11819 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
11820 const TargetRegisterClass *AddrRegClass = getRegClassFor(MVT::i64);
11821 const TargetRegisterClass *OffsetRegClass = getRegClassFor(MVT::i32);
11822 DebugLoc DL = MI->getDebugLoc();
11824 // struct va_list {
11827 // i64 overflow_area (address)
11828 // i64 reg_save_area (address)
11830 // sizeof(va_list) = 24
11831 // alignment(va_list) = 8
11833 unsigned TotalNumIntRegs = 6;
11834 unsigned TotalNumXMMRegs = 8;
11835 bool UseGPOffset = (ArgMode == 1);
11836 bool UseFPOffset = (ArgMode == 2);
11837 unsigned MaxOffset = TotalNumIntRegs * 8 +
11838 (UseFPOffset ? TotalNumXMMRegs * 16 : 0);
11840 /* Align ArgSize to a multiple of 8 */
11841 unsigned ArgSizeA8 = (ArgSize + 7) & ~7;
11842 bool NeedsAlign = (Align > 8);
11844 MachineBasicBlock *thisMBB = MBB;
11845 MachineBasicBlock *overflowMBB;
11846 MachineBasicBlock *offsetMBB;
11847 MachineBasicBlock *endMBB;
11849 unsigned OffsetDestReg = 0; // Argument address computed by offsetMBB
11850 unsigned OverflowDestReg = 0; // Argument address computed by overflowMBB
11851 unsigned OffsetReg = 0;
11853 if (!UseGPOffset && !UseFPOffset) {
11854 // If we only pull from the overflow region, we don't create a branch.
11855 // We don't need to alter control flow.
11856 OffsetDestReg = 0; // unused
11857 OverflowDestReg = DestReg;
11860 overflowMBB = thisMBB;
11863 // First emit code to check if gp_offset (or fp_offset) is below the bound.
11864 // If so, pull the argument from reg_save_area. (branch to offsetMBB)
11865 // If not, pull from overflow_area. (branch to overflowMBB)
11870 // offsetMBB overflowMBB
11875 // Registers for the PHI in endMBB
11876 OffsetDestReg = MRI.createVirtualRegister(AddrRegClass);
11877 OverflowDestReg = MRI.createVirtualRegister(AddrRegClass);
11879 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
11880 MachineFunction *MF = MBB->getParent();
11881 overflowMBB = MF->CreateMachineBasicBlock(LLVM_BB);
11882 offsetMBB = MF->CreateMachineBasicBlock(LLVM_BB);
11883 endMBB = MF->CreateMachineBasicBlock(LLVM_BB);
11885 MachineFunction::iterator MBBIter = MBB;
11888 // Insert the new basic blocks
11889 MF->insert(MBBIter, offsetMBB);
11890 MF->insert(MBBIter, overflowMBB);
11891 MF->insert(MBBIter, endMBB);
11893 // Transfer the remainder of MBB and its successor edges to endMBB.
11894 endMBB->splice(endMBB->begin(), thisMBB,
11895 llvm::next(MachineBasicBlock::iterator(MI)),
11897 endMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
11899 // Make offsetMBB and overflowMBB successors of thisMBB
11900 thisMBB->addSuccessor(offsetMBB);
11901 thisMBB->addSuccessor(overflowMBB);
11903 // endMBB is a successor of both offsetMBB and overflowMBB
11904 offsetMBB->addSuccessor(endMBB);
11905 overflowMBB->addSuccessor(endMBB);
11907 // Load the offset value into a register
11908 OffsetReg = MRI.createVirtualRegister(OffsetRegClass);
11909 BuildMI(thisMBB, DL, TII->get(X86::MOV32rm), OffsetReg)
11913 .addDisp(Disp, UseFPOffset ? 4 : 0)
11914 .addOperand(Segment)
11915 .setMemRefs(MMOBegin, MMOEnd);
11917 // Check if there is enough room left to pull this argument.
11918 BuildMI(thisMBB, DL, TII->get(X86::CMP32ri))
11920 .addImm(MaxOffset + 8 - ArgSizeA8);
11922 // Branch to "overflowMBB" if offset >= max
11923 // Fall through to "offsetMBB" otherwise
11924 BuildMI(thisMBB, DL, TII->get(X86::GetCondBranchFromCond(X86::COND_AE)))
11925 .addMBB(overflowMBB);
11928 // In offsetMBB, emit code to use the reg_save_area.
11930 assert(OffsetReg != 0);
11932 // Read the reg_save_area address.
11933 unsigned RegSaveReg = MRI.createVirtualRegister(AddrRegClass);
11934 BuildMI(offsetMBB, DL, TII->get(X86::MOV64rm), RegSaveReg)
11939 .addOperand(Segment)
11940 .setMemRefs(MMOBegin, MMOEnd);
11942 // Zero-extend the offset
11943 unsigned OffsetReg64 = MRI.createVirtualRegister(AddrRegClass);
11944 BuildMI(offsetMBB, DL, TII->get(X86::SUBREG_TO_REG), OffsetReg64)
11947 .addImm(X86::sub_32bit);
11949 // Add the offset to the reg_save_area to get the final address.
11950 BuildMI(offsetMBB, DL, TII->get(X86::ADD64rr), OffsetDestReg)
11951 .addReg(OffsetReg64)
11952 .addReg(RegSaveReg);
11954 // Compute the offset for the next argument
11955 unsigned NextOffsetReg = MRI.createVirtualRegister(OffsetRegClass);
11956 BuildMI(offsetMBB, DL, TII->get(X86::ADD32ri), NextOffsetReg)
11958 .addImm(UseFPOffset ? 16 : 8);
11960 // Store it back into the va_list.
11961 BuildMI(offsetMBB, DL, TII->get(X86::MOV32mr))
11965 .addDisp(Disp, UseFPOffset ? 4 : 0)
11966 .addOperand(Segment)
11967 .addReg(NextOffsetReg)
11968 .setMemRefs(MMOBegin, MMOEnd);
11971 BuildMI(offsetMBB, DL, TII->get(X86::JMP_4))
11976 // Emit code to use overflow area
11979 // Load the overflow_area address into a register.
11980 unsigned OverflowAddrReg = MRI.createVirtualRegister(AddrRegClass);
11981 BuildMI(overflowMBB, DL, TII->get(X86::MOV64rm), OverflowAddrReg)
11986 .addOperand(Segment)
11987 .setMemRefs(MMOBegin, MMOEnd);
11989 // If we need to align it, do so. Otherwise, just copy the address
11990 // to OverflowDestReg.
11992 // Align the overflow address
11993 assert((Align & (Align-1)) == 0 && "Alignment must be a power of 2");
11994 unsigned TmpReg = MRI.createVirtualRegister(AddrRegClass);
11996 // aligned_addr = (addr + (align-1)) & ~(align-1)
11997 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), TmpReg)
11998 .addReg(OverflowAddrReg)
12001 BuildMI(overflowMBB, DL, TII->get(X86::AND64ri32), OverflowDestReg)
12003 .addImm(~(uint64_t)(Align-1));
12005 BuildMI(overflowMBB, DL, TII->get(TargetOpcode::COPY), OverflowDestReg)
12006 .addReg(OverflowAddrReg);
12009 // Compute the next overflow address after this argument.
12010 // (the overflow address should be kept 8-byte aligned)
12011 unsigned NextAddrReg = MRI.createVirtualRegister(AddrRegClass);
12012 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), NextAddrReg)
12013 .addReg(OverflowDestReg)
12014 .addImm(ArgSizeA8);
12016 // Store the new overflow address.
12017 BuildMI(overflowMBB, DL, TII->get(X86::MOV64mr))
12022 .addOperand(Segment)
12023 .addReg(NextAddrReg)
12024 .setMemRefs(MMOBegin, MMOEnd);
12026 // If we branched, emit the PHI to the front of endMBB.
12028 BuildMI(*endMBB, endMBB->begin(), DL,
12029 TII->get(X86::PHI), DestReg)
12030 .addReg(OffsetDestReg).addMBB(offsetMBB)
12031 .addReg(OverflowDestReg).addMBB(overflowMBB);
12034 // Erase the pseudo instruction
12035 MI->eraseFromParent();
12040 MachineBasicBlock *
12041 X86TargetLowering::EmitVAStartSaveXMMRegsWithCustomInserter(
12043 MachineBasicBlock *MBB) const {
12044 // Emit code to save XMM registers to the stack. The ABI says that the
12045 // number of registers to save is given in %al, so it's theoretically
12046 // possible to do an indirect jump trick to avoid saving all of them,
12047 // however this code takes a simpler approach and just executes all
12048 // of the stores if %al is non-zero. It's less code, and it's probably
12049 // easier on the hardware branch predictor, and stores aren't all that
12050 // expensive anyway.
12052 // Create the new basic blocks. One block contains all the XMM stores,
12053 // and one block is the final destination regardless of whether any
12054 // stores were performed.
12055 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
12056 MachineFunction *F = MBB->getParent();
12057 MachineFunction::iterator MBBIter = MBB;
12059 MachineBasicBlock *XMMSaveMBB = F->CreateMachineBasicBlock(LLVM_BB);
12060 MachineBasicBlock *EndMBB = F->CreateMachineBasicBlock(LLVM_BB);
12061 F->insert(MBBIter, XMMSaveMBB);
12062 F->insert(MBBIter, EndMBB);
12064 // Transfer the remainder of MBB and its successor edges to EndMBB.
12065 EndMBB->splice(EndMBB->begin(), MBB,
12066 llvm::next(MachineBasicBlock::iterator(MI)),
12068 EndMBB->transferSuccessorsAndUpdatePHIs(MBB);
12070 // The original block will now fall through to the XMM save block.
12071 MBB->addSuccessor(XMMSaveMBB);
12072 // The XMMSaveMBB will fall through to the end block.
12073 XMMSaveMBB->addSuccessor(EndMBB);
12075 // Now add the instructions.
12076 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
12077 DebugLoc DL = MI->getDebugLoc();
12079 unsigned CountReg = MI->getOperand(0).getReg();
12080 int64_t RegSaveFrameIndex = MI->getOperand(1).getImm();
12081 int64_t VarArgsFPOffset = MI->getOperand(2).getImm();
12083 if (!Subtarget->isTargetWin64()) {
12084 // If %al is 0, branch around the XMM save block.
12085 BuildMI(MBB, DL, TII->get(X86::TEST8rr)).addReg(CountReg).addReg(CountReg);
12086 BuildMI(MBB, DL, TII->get(X86::JE_4)).addMBB(EndMBB);
12087 MBB->addSuccessor(EndMBB);
12090 unsigned MOVOpc = Subtarget->hasAVX() ? X86::VMOVAPSmr : X86::MOVAPSmr;
12091 // In the XMM save block, save all the XMM argument registers.
12092 for (int i = 3, e = MI->getNumOperands(); i != e; ++i) {
12093 int64_t Offset = (i - 3) * 16 + VarArgsFPOffset;
12094 MachineMemOperand *MMO =
12095 F->getMachineMemOperand(
12096 MachinePointerInfo::getFixedStack(RegSaveFrameIndex, Offset),
12097 MachineMemOperand::MOStore,
12098 /*Size=*/16, /*Align=*/16);
12099 BuildMI(XMMSaveMBB, DL, TII->get(MOVOpc))
12100 .addFrameIndex(RegSaveFrameIndex)
12101 .addImm(/*Scale=*/1)
12102 .addReg(/*IndexReg=*/0)
12103 .addImm(/*Disp=*/Offset)
12104 .addReg(/*Segment=*/0)
12105 .addReg(MI->getOperand(i).getReg())
12106 .addMemOperand(MMO);
12109 MI->eraseFromParent(); // The pseudo instruction is gone now.
12114 // The EFLAGS operand of SelectItr might be missing a kill marker
12115 // because there were multiple uses of EFLAGS, and ISel didn't know
12116 // which to mark. Figure out whether SelectItr should have had a
12117 // kill marker, and set it if it should. Returns the correct kill
12119 static bool checkAndUpdateEFLAGSKill(MachineBasicBlock::iterator SelectItr,
12120 MachineBasicBlock* BB,
12121 const TargetRegisterInfo* TRI) {
12122 // Scan forward through BB for a use/def of EFLAGS.
12123 MachineBasicBlock::iterator miI(llvm::next(SelectItr));
12124 for (MachineBasicBlock::iterator miE = BB->end(); miI != miE; ++miI) {
12125 const MachineInstr& mi = *miI;
12126 if (mi.readsRegister(X86::EFLAGS))
12128 if (mi.definesRegister(X86::EFLAGS))
12129 break; // Should have kill-flag - update below.
12132 // If we hit the end of the block, check whether EFLAGS is live into a
12134 if (miI == BB->end()) {
12135 for (MachineBasicBlock::succ_iterator sItr = BB->succ_begin(),
12136 sEnd = BB->succ_end();
12137 sItr != sEnd; ++sItr) {
12138 MachineBasicBlock* succ = *sItr;
12139 if (succ->isLiveIn(X86::EFLAGS))
12144 // We found a def, or hit the end of the basic block and EFLAGS wasn't live
12145 // out. SelectMI should have a kill flag on EFLAGS.
12146 SelectItr->addRegisterKilled(X86::EFLAGS, TRI);
12150 MachineBasicBlock *
12151 X86TargetLowering::EmitLoweredSelect(MachineInstr *MI,
12152 MachineBasicBlock *BB) const {
12153 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
12154 DebugLoc DL = MI->getDebugLoc();
12156 // To "insert" a SELECT_CC instruction, we actually have to insert the
12157 // diamond control-flow pattern. The incoming instruction knows the
12158 // destination vreg to set, the condition code register to branch on, the
12159 // true/false values to select between, and a branch opcode to use.
12160 const BasicBlock *LLVM_BB = BB->getBasicBlock();
12161 MachineFunction::iterator It = BB;
12167 // cmpTY ccX, r1, r2
12169 // fallthrough --> copy0MBB
12170 MachineBasicBlock *thisMBB = BB;
12171 MachineFunction *F = BB->getParent();
12172 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
12173 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
12174 F->insert(It, copy0MBB);
12175 F->insert(It, sinkMBB);
12177 // If the EFLAGS register isn't dead in the terminator, then claim that it's
12178 // live into the sink and copy blocks.
12179 const TargetRegisterInfo* TRI = getTargetMachine().getRegisterInfo();
12180 if (!MI->killsRegister(X86::EFLAGS) &&
12181 !checkAndUpdateEFLAGSKill(MI, BB, TRI)) {
12182 copy0MBB->addLiveIn(X86::EFLAGS);
12183 sinkMBB->addLiveIn(X86::EFLAGS);
12186 // Transfer the remainder of BB and its successor edges to sinkMBB.
12187 sinkMBB->splice(sinkMBB->begin(), BB,
12188 llvm::next(MachineBasicBlock::iterator(MI)),
12190 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
12192 // Add the true and fallthrough blocks as its successors.
12193 BB->addSuccessor(copy0MBB);
12194 BB->addSuccessor(sinkMBB);
12196 // Create the conditional branch instruction.
12198 X86::GetCondBranchFromCond((X86::CondCode)MI->getOperand(3).getImm());
12199 BuildMI(BB, DL, TII->get(Opc)).addMBB(sinkMBB);
12202 // %FalseValue = ...
12203 // # fallthrough to sinkMBB
12204 copy0MBB->addSuccessor(sinkMBB);
12207 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
12209 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
12210 TII->get(X86::PHI), MI->getOperand(0).getReg())
12211 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB)
12212 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
12214 MI->eraseFromParent(); // The pseudo instruction is gone now.
12218 MachineBasicBlock *
12219 X86TargetLowering::EmitLoweredSegAlloca(MachineInstr *MI, MachineBasicBlock *BB,
12220 bool Is64Bit) const {
12221 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
12222 DebugLoc DL = MI->getDebugLoc();
12223 MachineFunction *MF = BB->getParent();
12224 const BasicBlock *LLVM_BB = BB->getBasicBlock();
12226 assert(getTargetMachine().Options.EnableSegmentedStacks);
12228 unsigned TlsReg = Is64Bit ? X86::FS : X86::GS;
12229 unsigned TlsOffset = Is64Bit ? 0x70 : 0x30;
12232 // ... [Till the alloca]
12233 // If stacklet is not large enough, jump to mallocMBB
12236 // Allocate by subtracting from RSP
12237 // Jump to continueMBB
12240 // Allocate by call to runtime
12244 // [rest of original BB]
12247 MachineBasicBlock *mallocMBB = MF->CreateMachineBasicBlock(LLVM_BB);
12248 MachineBasicBlock *bumpMBB = MF->CreateMachineBasicBlock(LLVM_BB);
12249 MachineBasicBlock *continueMBB = MF->CreateMachineBasicBlock(LLVM_BB);
12251 MachineRegisterInfo &MRI = MF->getRegInfo();
12252 const TargetRegisterClass *AddrRegClass =
12253 getRegClassFor(Is64Bit ? MVT::i64:MVT::i32);
12255 unsigned mallocPtrVReg = MRI.createVirtualRegister(AddrRegClass),
12256 bumpSPPtrVReg = MRI.createVirtualRegister(AddrRegClass),
12257 tmpSPVReg = MRI.createVirtualRegister(AddrRegClass),
12258 SPLimitVReg = MRI.createVirtualRegister(AddrRegClass),
12259 sizeVReg = MI->getOperand(1).getReg(),
12260 physSPReg = Is64Bit ? X86::RSP : X86::ESP;
12262 MachineFunction::iterator MBBIter = BB;
12265 MF->insert(MBBIter, bumpMBB);
12266 MF->insert(MBBIter, mallocMBB);
12267 MF->insert(MBBIter, continueMBB);
12269 continueMBB->splice(continueMBB->begin(), BB, llvm::next
12270 (MachineBasicBlock::iterator(MI)), BB->end());
12271 continueMBB->transferSuccessorsAndUpdatePHIs(BB);
12273 // Add code to the main basic block to check if the stack limit has been hit,
12274 // and if so, jump to mallocMBB otherwise to bumpMBB.
12275 BuildMI(BB, DL, TII->get(TargetOpcode::COPY), tmpSPVReg).addReg(physSPReg);
12276 BuildMI(BB, DL, TII->get(Is64Bit ? X86::SUB64rr:X86::SUB32rr), SPLimitVReg)
12277 .addReg(tmpSPVReg).addReg(sizeVReg);
12278 BuildMI(BB, DL, TII->get(Is64Bit ? X86::CMP64mr:X86::CMP32mr))
12279 .addReg(0).addImm(1).addReg(0).addImm(TlsOffset).addReg(TlsReg)
12280 .addReg(SPLimitVReg);
12281 BuildMI(BB, DL, TII->get(X86::JG_4)).addMBB(mallocMBB);
12283 // bumpMBB simply decreases the stack pointer, since we know the current
12284 // stacklet has enough space.
12285 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), physSPReg)
12286 .addReg(SPLimitVReg);
12287 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), bumpSPPtrVReg)
12288 .addReg(SPLimitVReg);
12289 BuildMI(bumpMBB, DL, TII->get(X86::JMP_4)).addMBB(continueMBB);
12291 // Calls into a routine in libgcc to allocate more space from the heap.
12292 const uint32_t *RegMask =
12293 getTargetMachine().getRegisterInfo()->getCallPreservedMask(CallingConv::C);
12295 BuildMI(mallocMBB, DL, TII->get(X86::MOV64rr), X86::RDI)
12297 BuildMI(mallocMBB, DL, TII->get(X86::CALL64pcrel32))
12298 .addExternalSymbol("__morestack_allocate_stack_space").addReg(X86::RDI)
12299 .addRegMask(RegMask)
12300 .addReg(X86::RAX, RegState::ImplicitDefine);
12302 BuildMI(mallocMBB, DL, TII->get(X86::SUB32ri), physSPReg).addReg(physSPReg)
12304 BuildMI(mallocMBB, DL, TII->get(X86::PUSH32r)).addReg(sizeVReg);
12305 BuildMI(mallocMBB, DL, TII->get(X86::CALLpcrel32))
12306 .addExternalSymbol("__morestack_allocate_stack_space")
12307 .addRegMask(RegMask)
12308 .addReg(X86::EAX, RegState::ImplicitDefine);
12312 BuildMI(mallocMBB, DL, TII->get(X86::ADD32ri), physSPReg).addReg(physSPReg)
12315 BuildMI(mallocMBB, DL, TII->get(TargetOpcode::COPY), mallocPtrVReg)
12316 .addReg(Is64Bit ? X86::RAX : X86::EAX);
12317 BuildMI(mallocMBB, DL, TII->get(X86::JMP_4)).addMBB(continueMBB);
12319 // Set up the CFG correctly.
12320 BB->addSuccessor(bumpMBB);
12321 BB->addSuccessor(mallocMBB);
12322 mallocMBB->addSuccessor(continueMBB);
12323 bumpMBB->addSuccessor(continueMBB);
12325 // Take care of the PHI nodes.
12326 BuildMI(*continueMBB, continueMBB->begin(), DL, TII->get(X86::PHI),
12327 MI->getOperand(0).getReg())
12328 .addReg(mallocPtrVReg).addMBB(mallocMBB)
12329 .addReg(bumpSPPtrVReg).addMBB(bumpMBB);
12331 // Delete the original pseudo instruction.
12332 MI->eraseFromParent();
12335 return continueMBB;
12338 MachineBasicBlock *
12339 X86TargetLowering::EmitLoweredWinAlloca(MachineInstr *MI,
12340 MachineBasicBlock *BB) const {
12341 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
12342 DebugLoc DL = MI->getDebugLoc();
12344 assert(!Subtarget->isTargetEnvMacho());
12346 // The lowering is pretty easy: we're just emitting the call to _alloca. The
12347 // non-trivial part is impdef of ESP.
12349 if (Subtarget->isTargetWin64()) {
12350 if (Subtarget->isTargetCygMing()) {
12351 // ___chkstk(Mingw64):
12352 // Clobbers R10, R11, RAX and EFLAGS.
12354 BuildMI(*BB, MI, DL, TII->get(X86::W64ALLOCA))
12355 .addExternalSymbol("___chkstk")
12356 .addReg(X86::RAX, RegState::Implicit)
12357 .addReg(X86::RSP, RegState::Implicit)
12358 .addReg(X86::RAX, RegState::Define | RegState::Implicit)
12359 .addReg(X86::RSP, RegState::Define | RegState::Implicit)
12360 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
12362 // __chkstk(MSVCRT): does not update stack pointer.
12363 // Clobbers R10, R11 and EFLAGS.
12364 // FIXME: RAX(allocated size) might be reused and not killed.
12365 BuildMI(*BB, MI, DL, TII->get(X86::W64ALLOCA))
12366 .addExternalSymbol("__chkstk")
12367 .addReg(X86::RAX, RegState::Implicit)
12368 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
12369 // RAX has the offset to subtracted from RSP.
12370 BuildMI(*BB, MI, DL, TII->get(X86::SUB64rr), X86::RSP)
12375 const char *StackProbeSymbol =
12376 Subtarget->isTargetWindows() ? "_chkstk" : "_alloca";
12378 BuildMI(*BB, MI, DL, TII->get(X86::CALLpcrel32))
12379 .addExternalSymbol(StackProbeSymbol)
12380 .addReg(X86::EAX, RegState::Implicit)
12381 .addReg(X86::ESP, RegState::Implicit)
12382 .addReg(X86::EAX, RegState::Define | RegState::Implicit)
12383 .addReg(X86::ESP, RegState::Define | RegState::Implicit)
12384 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
12387 MI->eraseFromParent(); // The pseudo instruction is gone now.
12391 MachineBasicBlock *
12392 X86TargetLowering::EmitLoweredTLSCall(MachineInstr *MI,
12393 MachineBasicBlock *BB) const {
12394 // This is pretty easy. We're taking the value that we received from
12395 // our load from the relocation, sticking it in either RDI (x86-64)
12396 // or EAX and doing an indirect call. The return value will then
12397 // be in the normal return register.
12398 const X86InstrInfo *TII
12399 = static_cast<const X86InstrInfo*>(getTargetMachine().getInstrInfo());
12400 DebugLoc DL = MI->getDebugLoc();
12401 MachineFunction *F = BB->getParent();
12403 assert(Subtarget->isTargetDarwin() && "Darwin only instr emitted?");
12404 assert(MI->getOperand(3).isGlobal() && "This should be a global");
12406 // Get a register mask for the lowered call.
12407 // FIXME: The 32-bit calls have non-standard calling conventions. Use a
12408 // proper register mask.
12409 const uint32_t *RegMask =
12410 getTargetMachine().getRegisterInfo()->getCallPreservedMask(CallingConv::C);
12411 if (Subtarget->is64Bit()) {
12412 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
12413 TII->get(X86::MOV64rm), X86::RDI)
12415 .addImm(0).addReg(0)
12416 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
12417 MI->getOperand(3).getTargetFlags())
12419 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL64m));
12420 addDirectMem(MIB, X86::RDI);
12421 MIB.addReg(X86::RAX, RegState::ImplicitDefine).addRegMask(RegMask);
12422 } else if (getTargetMachine().getRelocationModel() != Reloc::PIC_) {
12423 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
12424 TII->get(X86::MOV32rm), X86::EAX)
12426 .addImm(0).addReg(0)
12427 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
12428 MI->getOperand(3).getTargetFlags())
12430 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
12431 addDirectMem(MIB, X86::EAX);
12432 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask);
12434 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
12435 TII->get(X86::MOV32rm), X86::EAX)
12436 .addReg(TII->getGlobalBaseReg(F))
12437 .addImm(0).addReg(0)
12438 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
12439 MI->getOperand(3).getTargetFlags())
12441 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
12442 addDirectMem(MIB, X86::EAX);
12443 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask);
12446 MI->eraseFromParent(); // The pseudo instruction is gone now.
12450 MachineBasicBlock *
12451 X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
12452 MachineBasicBlock *BB) const {
12453 switch (MI->getOpcode()) {
12454 default: llvm_unreachable("Unexpected instr type to insert");
12455 case X86::TAILJMPd64:
12456 case X86::TAILJMPr64:
12457 case X86::TAILJMPm64:
12458 llvm_unreachable("TAILJMP64 would not be touched here.");
12459 case X86::TCRETURNdi64:
12460 case X86::TCRETURNri64:
12461 case X86::TCRETURNmi64:
12463 case X86::WIN_ALLOCA:
12464 return EmitLoweredWinAlloca(MI, BB);
12465 case X86::SEG_ALLOCA_32:
12466 return EmitLoweredSegAlloca(MI, BB, false);
12467 case X86::SEG_ALLOCA_64:
12468 return EmitLoweredSegAlloca(MI, BB, true);
12469 case X86::TLSCall_32:
12470 case X86::TLSCall_64:
12471 return EmitLoweredTLSCall(MI, BB);
12472 case X86::CMOV_GR8:
12473 case X86::CMOV_FR32:
12474 case X86::CMOV_FR64:
12475 case X86::CMOV_V4F32:
12476 case X86::CMOV_V2F64:
12477 case X86::CMOV_V2I64:
12478 case X86::CMOV_V8F32:
12479 case X86::CMOV_V4F64:
12480 case X86::CMOV_V4I64:
12481 case X86::CMOV_GR16:
12482 case X86::CMOV_GR32:
12483 case X86::CMOV_RFP32:
12484 case X86::CMOV_RFP64:
12485 case X86::CMOV_RFP80:
12486 return EmitLoweredSelect(MI, BB);
12488 case X86::FP32_TO_INT16_IN_MEM:
12489 case X86::FP32_TO_INT32_IN_MEM:
12490 case X86::FP32_TO_INT64_IN_MEM:
12491 case X86::FP64_TO_INT16_IN_MEM:
12492 case X86::FP64_TO_INT32_IN_MEM:
12493 case X86::FP64_TO_INT64_IN_MEM:
12494 case X86::FP80_TO_INT16_IN_MEM:
12495 case X86::FP80_TO_INT32_IN_MEM:
12496 case X86::FP80_TO_INT64_IN_MEM: {
12497 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
12498 DebugLoc DL = MI->getDebugLoc();
12500 // Change the floating point control register to use "round towards zero"
12501 // mode when truncating to an integer value.
12502 MachineFunction *F = BB->getParent();
12503 int CWFrameIdx = F->getFrameInfo()->CreateStackObject(2, 2, false);
12504 addFrameReference(BuildMI(*BB, MI, DL,
12505 TII->get(X86::FNSTCW16m)), CWFrameIdx);
12507 // Load the old value of the high byte of the control word...
12509 F->getRegInfo().createVirtualRegister(&X86::GR16RegClass);
12510 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16rm), OldCW),
12513 // Set the high part to be round to zero...
12514 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mi)), CWFrameIdx)
12517 // Reload the modified control word now...
12518 addFrameReference(BuildMI(*BB, MI, DL,
12519 TII->get(X86::FLDCW16m)), CWFrameIdx);
12521 // Restore the memory image of control word to original value
12522 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mr)), CWFrameIdx)
12525 // Get the X86 opcode to use.
12527 switch (MI->getOpcode()) {
12528 default: llvm_unreachable("illegal opcode!");
12529 case X86::FP32_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m32; break;
12530 case X86::FP32_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m32; break;
12531 case X86::FP32_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m32; break;
12532 case X86::FP64_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m64; break;
12533 case X86::FP64_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m64; break;
12534 case X86::FP64_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m64; break;
12535 case X86::FP80_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m80; break;
12536 case X86::FP80_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m80; break;
12537 case X86::FP80_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m80; break;
12541 MachineOperand &Op = MI->getOperand(0);
12543 AM.BaseType = X86AddressMode::RegBase;
12544 AM.Base.Reg = Op.getReg();
12546 AM.BaseType = X86AddressMode::FrameIndexBase;
12547 AM.Base.FrameIndex = Op.getIndex();
12549 Op = MI->getOperand(1);
12551 AM.Scale = Op.getImm();
12552 Op = MI->getOperand(2);
12554 AM.IndexReg = Op.getImm();
12555 Op = MI->getOperand(3);
12556 if (Op.isGlobal()) {
12557 AM.GV = Op.getGlobal();
12559 AM.Disp = Op.getImm();
12561 addFullAddress(BuildMI(*BB, MI, DL, TII->get(Opc)), AM)
12562 .addReg(MI->getOperand(X86::AddrNumOperands).getReg());
12564 // Reload the original control word now.
12565 addFrameReference(BuildMI(*BB, MI, DL,
12566 TII->get(X86::FLDCW16m)), CWFrameIdx);
12568 MI->eraseFromParent(); // The pseudo instruction is gone now.
12571 // String/text processing lowering.
12572 case X86::PCMPISTRM128REG:
12573 case X86::VPCMPISTRM128REG:
12574 return EmitPCMP(MI, BB, 3, false /* in-mem */);
12575 case X86::PCMPISTRM128MEM:
12576 case X86::VPCMPISTRM128MEM:
12577 return EmitPCMP(MI, BB, 3, true /* in-mem */);
12578 case X86::PCMPESTRM128REG:
12579 case X86::VPCMPESTRM128REG:
12580 return EmitPCMP(MI, BB, 5, false /* in mem */);
12581 case X86::PCMPESTRM128MEM:
12582 case X86::VPCMPESTRM128MEM:
12583 return EmitPCMP(MI, BB, 5, true /* in mem */);
12585 // Thread synchronization.
12587 return EmitMonitor(MI, BB);
12589 return EmitMwait(MI, BB);
12591 // Atomic Lowering.
12592 case X86::ATOMAND32:
12593 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND32rr,
12594 X86::AND32ri, X86::MOV32rm,
12596 X86::NOT32r, X86::EAX,
12597 &X86::GR32RegClass);
12598 case X86::ATOMOR32:
12599 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR32rr,
12600 X86::OR32ri, X86::MOV32rm,
12602 X86::NOT32r, X86::EAX,
12603 &X86::GR32RegClass);
12604 case X86::ATOMXOR32:
12605 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR32rr,
12606 X86::XOR32ri, X86::MOV32rm,
12608 X86::NOT32r, X86::EAX,
12609 &X86::GR32RegClass);
12610 case X86::ATOMNAND32:
12611 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND32rr,
12612 X86::AND32ri, X86::MOV32rm,
12614 X86::NOT32r, X86::EAX,
12615 &X86::GR32RegClass, true);
12616 case X86::ATOMMIN32:
12617 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL32rr);
12618 case X86::ATOMMAX32:
12619 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG32rr);
12620 case X86::ATOMUMIN32:
12621 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB32rr);
12622 case X86::ATOMUMAX32:
12623 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA32rr);
12625 case X86::ATOMAND16:
12626 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND16rr,
12627 X86::AND16ri, X86::MOV16rm,
12629 X86::NOT16r, X86::AX,
12630 &X86::GR16RegClass);
12631 case X86::ATOMOR16:
12632 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR16rr,
12633 X86::OR16ri, X86::MOV16rm,
12635 X86::NOT16r, X86::AX,
12636 &X86::GR16RegClass);
12637 case X86::ATOMXOR16:
12638 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR16rr,
12639 X86::XOR16ri, X86::MOV16rm,
12641 X86::NOT16r, X86::AX,
12642 &X86::GR16RegClass);
12643 case X86::ATOMNAND16:
12644 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND16rr,
12645 X86::AND16ri, X86::MOV16rm,
12647 X86::NOT16r, X86::AX,
12648 &X86::GR16RegClass, true);
12649 case X86::ATOMMIN16:
12650 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL16rr);
12651 case X86::ATOMMAX16:
12652 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG16rr);
12653 case X86::ATOMUMIN16:
12654 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB16rr);
12655 case X86::ATOMUMAX16:
12656 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA16rr);
12658 case X86::ATOMAND8:
12659 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND8rr,
12660 X86::AND8ri, X86::MOV8rm,
12662 X86::NOT8r, X86::AL,
12663 &X86::GR8RegClass);
12665 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR8rr,
12666 X86::OR8ri, X86::MOV8rm,
12668 X86::NOT8r, X86::AL,
12669 &X86::GR8RegClass);
12670 case X86::ATOMXOR8:
12671 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR8rr,
12672 X86::XOR8ri, X86::MOV8rm,
12674 X86::NOT8r, X86::AL,
12675 &X86::GR8RegClass);
12676 case X86::ATOMNAND8:
12677 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND8rr,
12678 X86::AND8ri, X86::MOV8rm,
12680 X86::NOT8r, X86::AL,
12681 &X86::GR8RegClass, true);
12682 // FIXME: There are no CMOV8 instructions; MIN/MAX need some other way.
12683 // This group is for 64-bit host.
12684 case X86::ATOMAND64:
12685 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND64rr,
12686 X86::AND64ri32, X86::MOV64rm,
12688 X86::NOT64r, X86::RAX,
12689 &X86::GR64RegClass);
12690 case X86::ATOMOR64:
12691 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR64rr,
12692 X86::OR64ri32, X86::MOV64rm,
12694 X86::NOT64r, X86::RAX,
12695 &X86::GR64RegClass);
12696 case X86::ATOMXOR64:
12697 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR64rr,
12698 X86::XOR64ri32, X86::MOV64rm,
12700 X86::NOT64r, X86::RAX,
12701 &X86::GR64RegClass);
12702 case X86::ATOMNAND64:
12703 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND64rr,
12704 X86::AND64ri32, X86::MOV64rm,
12706 X86::NOT64r, X86::RAX,
12707 &X86::GR64RegClass, true);
12708 case X86::ATOMMIN64:
12709 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL64rr);
12710 case X86::ATOMMAX64:
12711 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG64rr);
12712 case X86::ATOMUMIN64:
12713 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB64rr);
12714 case X86::ATOMUMAX64:
12715 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA64rr);
12717 // This group does 64-bit operations on a 32-bit host.
12718 case X86::ATOMAND6432:
12719 return EmitAtomicBit6432WithCustomInserter(MI, BB,
12720 X86::AND32rr, X86::AND32rr,
12721 X86::AND32ri, X86::AND32ri,
12723 case X86::ATOMOR6432:
12724 return EmitAtomicBit6432WithCustomInserter(MI, BB,
12725 X86::OR32rr, X86::OR32rr,
12726 X86::OR32ri, X86::OR32ri,
12728 case X86::ATOMXOR6432:
12729 return EmitAtomicBit6432WithCustomInserter(MI, BB,
12730 X86::XOR32rr, X86::XOR32rr,
12731 X86::XOR32ri, X86::XOR32ri,
12733 case X86::ATOMNAND6432:
12734 return EmitAtomicBit6432WithCustomInserter(MI, BB,
12735 X86::AND32rr, X86::AND32rr,
12736 X86::AND32ri, X86::AND32ri,
12738 case X86::ATOMADD6432:
12739 return EmitAtomicBit6432WithCustomInserter(MI, BB,
12740 X86::ADD32rr, X86::ADC32rr,
12741 X86::ADD32ri, X86::ADC32ri,
12743 case X86::ATOMSUB6432:
12744 return EmitAtomicBit6432WithCustomInserter(MI, BB,
12745 X86::SUB32rr, X86::SBB32rr,
12746 X86::SUB32ri, X86::SBB32ri,
12748 case X86::ATOMSWAP6432:
12749 return EmitAtomicBit6432WithCustomInserter(MI, BB,
12750 X86::MOV32rr, X86::MOV32rr,
12751 X86::MOV32ri, X86::MOV32ri,
12753 case X86::VASTART_SAVE_XMM_REGS:
12754 return EmitVAStartSaveXMMRegsWithCustomInserter(MI, BB);
12756 case X86::VAARG_64:
12757 return EmitVAARG64WithCustomInserter(MI, BB);
12761 //===----------------------------------------------------------------------===//
12762 // X86 Optimization Hooks
12763 //===----------------------------------------------------------------------===//
12765 void X86TargetLowering::computeMaskedBitsForTargetNode(const SDValue Op,
12768 const SelectionDAG &DAG,
12769 unsigned Depth) const {
12770 unsigned BitWidth = KnownZero.getBitWidth();
12771 unsigned Opc = Op.getOpcode();
12772 assert((Opc >= ISD::BUILTIN_OP_END ||
12773 Opc == ISD::INTRINSIC_WO_CHAIN ||
12774 Opc == ISD::INTRINSIC_W_CHAIN ||
12775 Opc == ISD::INTRINSIC_VOID) &&
12776 "Should use MaskedValueIsZero if you don't know whether Op"
12777 " is a target node!");
12779 KnownZero = KnownOne = APInt(BitWidth, 0); // Don't know anything.
12793 // These nodes' second result is a boolean.
12794 if (Op.getResNo() == 0)
12797 case X86ISD::SETCC:
12798 KnownZero |= APInt::getHighBitsSet(BitWidth, BitWidth - 1);
12800 case ISD::INTRINSIC_WO_CHAIN: {
12801 unsigned IntId = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
12802 unsigned NumLoBits = 0;
12805 case Intrinsic::x86_sse_movmsk_ps:
12806 case Intrinsic::x86_avx_movmsk_ps_256:
12807 case Intrinsic::x86_sse2_movmsk_pd:
12808 case Intrinsic::x86_avx_movmsk_pd_256:
12809 case Intrinsic::x86_mmx_pmovmskb:
12810 case Intrinsic::x86_sse2_pmovmskb_128:
12811 case Intrinsic::x86_avx2_pmovmskb: {
12812 // High bits of movmskp{s|d}, pmovmskb are known zero.
12814 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
12815 case Intrinsic::x86_sse_movmsk_ps: NumLoBits = 4; break;
12816 case Intrinsic::x86_avx_movmsk_ps_256: NumLoBits = 8; break;
12817 case Intrinsic::x86_sse2_movmsk_pd: NumLoBits = 2; break;
12818 case Intrinsic::x86_avx_movmsk_pd_256: NumLoBits = 4; break;
12819 case Intrinsic::x86_mmx_pmovmskb: NumLoBits = 8; break;
12820 case Intrinsic::x86_sse2_pmovmskb_128: NumLoBits = 16; break;
12821 case Intrinsic::x86_avx2_pmovmskb: NumLoBits = 32; break;
12823 KnownZero = APInt::getHighBitsSet(BitWidth, BitWidth - NumLoBits);
12832 unsigned X86TargetLowering::ComputeNumSignBitsForTargetNode(SDValue Op,
12833 unsigned Depth) const {
12834 // SETCC_CARRY sets the dest to ~0 for true or 0 for false.
12835 if (Op.getOpcode() == X86ISD::SETCC_CARRY)
12836 return Op.getValueType().getScalarType().getSizeInBits();
12842 /// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the
12843 /// node is a GlobalAddress + offset.
12844 bool X86TargetLowering::isGAPlusOffset(SDNode *N,
12845 const GlobalValue* &GA,
12846 int64_t &Offset) const {
12847 if (N->getOpcode() == X86ISD::Wrapper) {
12848 if (isa<GlobalAddressSDNode>(N->getOperand(0))) {
12849 GA = cast<GlobalAddressSDNode>(N->getOperand(0))->getGlobal();
12850 Offset = cast<GlobalAddressSDNode>(N->getOperand(0))->getOffset();
12854 return TargetLowering::isGAPlusOffset(N, GA, Offset);
12857 /// isShuffleHigh128VectorInsertLow - Checks whether the shuffle node is the
12858 /// same as extracting the high 128-bit part of 256-bit vector and then
12859 /// inserting the result into the low part of a new 256-bit vector
12860 static bool isShuffleHigh128VectorInsertLow(ShuffleVectorSDNode *SVOp) {
12861 EVT VT = SVOp->getValueType(0);
12862 int NumElems = VT.getVectorNumElements();
12864 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
12865 for (int i = 0, j = NumElems/2; i < NumElems/2; ++i, ++j)
12866 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) ||
12867 SVOp->getMaskElt(j) >= 0)
12873 /// isShuffleLow128VectorInsertHigh - Checks whether the shuffle node is the
12874 /// same as extracting the low 128-bit part of 256-bit vector and then
12875 /// inserting the result into the high part of a new 256-bit vector
12876 static bool isShuffleLow128VectorInsertHigh(ShuffleVectorSDNode *SVOp) {
12877 EVT VT = SVOp->getValueType(0);
12878 int NumElems = VT.getVectorNumElements();
12880 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
12881 for (int i = NumElems/2, j = 0; i < NumElems; ++i, ++j)
12882 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) ||
12883 SVOp->getMaskElt(j) >= 0)
12889 /// PerformShuffleCombine256 - Performs shuffle combines for 256-bit vectors.
12890 static SDValue PerformShuffleCombine256(SDNode *N, SelectionDAG &DAG,
12891 TargetLowering::DAGCombinerInfo &DCI,
12892 const X86Subtarget* Subtarget) {
12893 DebugLoc dl = N->getDebugLoc();
12894 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
12895 SDValue V1 = SVOp->getOperand(0);
12896 SDValue V2 = SVOp->getOperand(1);
12897 EVT VT = SVOp->getValueType(0);
12898 int NumElems = VT.getVectorNumElements();
12900 if (V1.getOpcode() == ISD::CONCAT_VECTORS &&
12901 V2.getOpcode() == ISD::CONCAT_VECTORS) {
12905 // V UNDEF BUILD_VECTOR UNDEF
12907 // CONCAT_VECTOR CONCAT_VECTOR
12910 // RESULT: V + zero extended
12912 if (V2.getOperand(0).getOpcode() != ISD::BUILD_VECTOR ||
12913 V2.getOperand(1).getOpcode() != ISD::UNDEF ||
12914 V1.getOperand(1).getOpcode() != ISD::UNDEF)
12917 if (!ISD::isBuildVectorAllZeros(V2.getOperand(0).getNode()))
12920 // To match the shuffle mask, the first half of the mask should
12921 // be exactly the first vector, and all the rest a splat with the
12922 // first element of the second one.
12923 for (int i = 0; i < NumElems/2; ++i)
12924 if (!isUndefOrEqual(SVOp->getMaskElt(i), i) ||
12925 !isUndefOrEqual(SVOp->getMaskElt(i+NumElems/2), NumElems))
12928 // If V1 is coming from a vector load then just fold to a VZEXT_LOAD.
12929 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(V1.getOperand(0))) {
12930 SDVTList Tys = DAG.getVTList(MVT::v4i64, MVT::Other);
12931 SDValue Ops[] = { Ld->getChain(), Ld->getBasePtr() };
12933 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, dl, Tys, Ops, 2,
12935 Ld->getPointerInfo(),
12936 Ld->getAlignment(),
12937 false/*isVolatile*/, true/*ReadMem*/,
12938 false/*WriteMem*/);
12939 return DAG.getNode(ISD::BITCAST, dl, VT, ResNode);
12942 // Emit a zeroed vector and insert the desired subvector on its
12944 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
12945 SDValue InsV = Insert128BitVector(Zeros, V1.getOperand(0), 0, DAG, dl);
12946 return DCI.CombineTo(N, InsV);
12949 //===--------------------------------------------------------------------===//
12950 // Combine some shuffles into subvector extracts and inserts:
12953 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
12954 if (isShuffleHigh128VectorInsertLow(SVOp)) {
12955 SDValue V = Extract128BitVector(V1, NumElems/2, DAG, dl);
12956 SDValue InsV = Insert128BitVector(DAG.getUNDEF(VT), V, 0, DAG, dl);
12957 return DCI.CombineTo(N, InsV);
12960 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
12961 if (isShuffleLow128VectorInsertHigh(SVOp)) {
12962 SDValue V = Extract128BitVector(V1, 0, DAG, dl);
12963 SDValue InsV = Insert128BitVector(DAG.getUNDEF(VT), V, NumElems/2, DAG, dl);
12964 return DCI.CombineTo(N, InsV);
12970 /// PerformShuffleCombine - Performs several different shuffle combines.
12971 static SDValue PerformShuffleCombine(SDNode *N, SelectionDAG &DAG,
12972 TargetLowering::DAGCombinerInfo &DCI,
12973 const X86Subtarget *Subtarget) {
12974 DebugLoc dl = N->getDebugLoc();
12975 EVT VT = N->getValueType(0);
12977 // Don't create instructions with illegal types after legalize types has run.
12978 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
12979 if (!DCI.isBeforeLegalize() && !TLI.isTypeLegal(VT.getVectorElementType()))
12982 // Combine 256-bit vector shuffles. This is only profitable when in AVX mode
12983 if (Subtarget->hasAVX() && VT.getSizeInBits() == 256 &&
12984 N->getOpcode() == ISD::VECTOR_SHUFFLE)
12985 return PerformShuffleCombine256(N, DAG, DCI, Subtarget);
12987 // Only handle 128 wide vector from here on.
12988 if (VT.getSizeInBits() != 128)
12991 // Combine a vector_shuffle that is equal to build_vector load1, load2, load3,
12992 // load4, <0, 1, 2, 3> into a 128-bit load if the load addresses are
12993 // consecutive, non-overlapping, and in the right order.
12994 SmallVector<SDValue, 16> Elts;
12995 for (unsigned i = 0, e = VT.getVectorNumElements(); i != e; ++i)
12996 Elts.push_back(getShuffleScalarElt(N, i, DAG, 0));
12998 return EltsFromConsecutiveLoads(VT, Elts, dl, DAG);
13002 /// PerformTruncateCombine - Converts truncate operation to
13003 /// a sequence of vector shuffle operations.
13004 /// It is possible when we truncate 256-bit vector to 128-bit vector
13006 SDValue X86TargetLowering::PerformTruncateCombine(SDNode *N, SelectionDAG &DAG,
13007 DAGCombinerInfo &DCI) const {
13008 if (!DCI.isBeforeLegalizeOps())
13011 if (!Subtarget->hasAVX())
13014 EVT VT = N->getValueType(0);
13015 SDValue Op = N->getOperand(0);
13016 EVT OpVT = Op.getValueType();
13017 DebugLoc dl = N->getDebugLoc();
13019 if ((VT == MVT::v4i32) && (OpVT == MVT::v4i64)) {
13021 if (Subtarget->hasAVX2()) {
13022 // AVX2: v4i64 -> v4i32
13025 static const int ShufMask[] = {0, 2, 4, 6, -1, -1, -1, -1};
13027 Op = DAG.getNode(ISD::BITCAST, dl, MVT::v8i32, Op);
13028 Op = DAG.getVectorShuffle(MVT::v8i32, dl, Op, DAG.getUNDEF(MVT::v8i32),
13031 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, Op,
13032 DAG.getIntPtrConstant(0));
13035 // AVX: v4i64 -> v4i32
13036 SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v2i64, Op,
13037 DAG.getIntPtrConstant(0));
13039 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v2i64, Op,
13040 DAG.getIntPtrConstant(2));
13042 OpLo = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, OpLo);
13043 OpHi = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, OpHi);
13046 static const int ShufMask1[] = {0, 2, 0, 0};
13048 OpLo = DAG.getVectorShuffle(VT, dl, OpLo, DAG.getUNDEF(VT), ShufMask1);
13049 OpHi = DAG.getVectorShuffle(VT, dl, OpHi, DAG.getUNDEF(VT), ShufMask1);
13052 static const int ShufMask2[] = {0, 1, 4, 5};
13054 return DAG.getVectorShuffle(VT, dl, OpLo, OpHi, ShufMask2);
13057 if ((VT == MVT::v8i16) && (OpVT == MVT::v8i32)) {
13059 if (Subtarget->hasAVX2()) {
13060 // AVX2: v8i32 -> v8i16
13062 Op = DAG.getNode(ISD::BITCAST, dl, MVT::v32i8, Op);
13065 SmallVector<SDValue,32> pshufbMask;
13066 for (unsigned i = 0; i < 2; ++i) {
13067 pshufbMask.push_back(DAG.getConstant(0x0, MVT::i8));
13068 pshufbMask.push_back(DAG.getConstant(0x1, MVT::i8));
13069 pshufbMask.push_back(DAG.getConstant(0x4, MVT::i8));
13070 pshufbMask.push_back(DAG.getConstant(0x5, MVT::i8));
13071 pshufbMask.push_back(DAG.getConstant(0x8, MVT::i8));
13072 pshufbMask.push_back(DAG.getConstant(0x9, MVT::i8));
13073 pshufbMask.push_back(DAG.getConstant(0xc, MVT::i8));
13074 pshufbMask.push_back(DAG.getConstant(0xd, MVT::i8));
13075 for (unsigned j = 0; j < 8; ++j)
13076 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
13078 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v32i8,
13079 &pshufbMask[0], 32);
13080 Op = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v32i8, Op, BV);
13082 Op = DAG.getNode(ISD::BITCAST, dl, MVT::v4i64, Op);
13084 static const int ShufMask[] = {0, 2, -1, -1};
13085 Op = DAG.getVectorShuffle(MVT::v4i64, dl, Op, DAG.getUNDEF(MVT::v4i64),
13088 Op = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v2i64, Op,
13089 DAG.getIntPtrConstant(0));
13091 return DAG.getNode(ISD::BITCAST, dl, VT, Op);
13094 SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i32, Op,
13095 DAG.getIntPtrConstant(0));
13097 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i32, Op,
13098 DAG.getIntPtrConstant(4));
13100 OpLo = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, OpLo);
13101 OpHi = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, OpHi);
13104 static const int ShufMask1[] = {0, 1, 4, 5, 8, 9, 12, 13,
13105 -1, -1, -1, -1, -1, -1, -1, -1};
13107 OpLo = DAG.getVectorShuffle(MVT::v16i8, dl, OpLo, DAG.getUNDEF(MVT::v16i8),
13109 OpHi = DAG.getVectorShuffle(MVT::v16i8, dl, OpHi, DAG.getUNDEF(MVT::v16i8),
13112 OpLo = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, OpLo);
13113 OpHi = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, OpHi);
13116 static const int ShufMask2[] = {0, 1, 4, 5};
13118 SDValue res = DAG.getVectorShuffle(MVT::v4i32, dl, OpLo, OpHi, ShufMask2);
13119 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, res);
13125 /// XFormVExtractWithShuffleIntoLoad - Check if a vector extract from a target
13126 /// specific shuffle of a load can be folded into a single element load.
13127 /// Similar handling for VECTOR_SHUFFLE is performed by DAGCombiner, but
13128 /// shuffles have been customed lowered so we need to handle those here.
13129 static SDValue XFormVExtractWithShuffleIntoLoad(SDNode *N, SelectionDAG &DAG,
13130 TargetLowering::DAGCombinerInfo &DCI) {
13131 if (DCI.isBeforeLegalizeOps())
13134 SDValue InVec = N->getOperand(0);
13135 SDValue EltNo = N->getOperand(1);
13137 if (!isa<ConstantSDNode>(EltNo))
13140 EVT VT = InVec.getValueType();
13142 bool HasShuffleIntoBitcast = false;
13143 if (InVec.getOpcode() == ISD::BITCAST) {
13144 // Don't duplicate a load with other uses.
13145 if (!InVec.hasOneUse())
13147 EVT BCVT = InVec.getOperand(0).getValueType();
13148 if (BCVT.getVectorNumElements() != VT.getVectorNumElements())
13150 InVec = InVec.getOperand(0);
13151 HasShuffleIntoBitcast = true;
13154 if (!isTargetShuffle(InVec.getOpcode()))
13157 // Don't duplicate a load with other uses.
13158 if (!InVec.hasOneUse())
13161 SmallVector<int, 16> ShuffleMask;
13163 if (!getTargetShuffleMask(InVec.getNode(), VT, ShuffleMask, UnaryShuffle))
13166 // Select the input vector, guarding against out of range extract vector.
13167 unsigned NumElems = VT.getVectorNumElements();
13168 int Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();
13169 int Idx = (Elt > (int)NumElems) ? -1 : ShuffleMask[Elt];
13170 SDValue LdNode = (Idx < (int)NumElems) ? InVec.getOperand(0)
13171 : InVec.getOperand(1);
13173 // If inputs to shuffle are the same for both ops, then allow 2 uses
13174 unsigned AllowedUses = InVec.getOperand(0) == InVec.getOperand(1) ? 2 : 1;
13176 if (LdNode.getOpcode() == ISD::BITCAST) {
13177 // Don't duplicate a load with other uses.
13178 if (!LdNode.getNode()->hasNUsesOfValue(AllowedUses, 0))
13181 AllowedUses = 1; // only allow 1 load use if we have a bitcast
13182 LdNode = LdNode.getOperand(0);
13185 if (!ISD::isNormalLoad(LdNode.getNode()))
13188 LoadSDNode *LN0 = cast<LoadSDNode>(LdNode);
13190 if (!LN0 ||!LN0->hasNUsesOfValue(AllowedUses, 0) || LN0->isVolatile())
13193 if (HasShuffleIntoBitcast) {
13194 // If there's a bitcast before the shuffle, check if the load type and
13195 // alignment is valid.
13196 unsigned Align = LN0->getAlignment();
13197 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
13198 unsigned NewAlign = TLI.getTargetData()->
13199 getABITypeAlignment(VT.getTypeForEVT(*DAG.getContext()));
13201 if (NewAlign > Align || !TLI.isOperationLegalOrCustom(ISD::LOAD, VT))
13205 // All checks match so transform back to vector_shuffle so that DAG combiner
13206 // can finish the job
13207 DebugLoc dl = N->getDebugLoc();
13209 // Create shuffle node taking into account the case that its a unary shuffle
13210 SDValue Shuffle = (UnaryShuffle) ? DAG.getUNDEF(VT) : InVec.getOperand(1);
13211 Shuffle = DAG.getVectorShuffle(InVec.getValueType(), dl,
13212 InVec.getOperand(0), Shuffle,
13214 Shuffle = DAG.getNode(ISD::BITCAST, dl, VT, Shuffle);
13215 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, N->getValueType(0), Shuffle,
13219 /// PerformEXTRACT_VECTOR_ELTCombine - Detect vector gather/scatter index
13220 /// generation and convert it from being a bunch of shuffles and extracts
13221 /// to a simple store and scalar loads to extract the elements.
13222 static SDValue PerformEXTRACT_VECTOR_ELTCombine(SDNode *N, SelectionDAG &DAG,
13223 TargetLowering::DAGCombinerInfo &DCI) {
13224 SDValue NewOp = XFormVExtractWithShuffleIntoLoad(N, DAG, DCI);
13225 if (NewOp.getNode())
13228 SDValue InputVector = N->getOperand(0);
13230 // Only operate on vectors of 4 elements, where the alternative shuffling
13231 // gets to be more expensive.
13232 if (InputVector.getValueType() != MVT::v4i32)
13235 // Check whether every use of InputVector is an EXTRACT_VECTOR_ELT with a
13236 // single use which is a sign-extend or zero-extend, and all elements are
13238 SmallVector<SDNode *, 4> Uses;
13239 unsigned ExtractedElements = 0;
13240 for (SDNode::use_iterator UI = InputVector.getNode()->use_begin(),
13241 UE = InputVector.getNode()->use_end(); UI != UE; ++UI) {
13242 if (UI.getUse().getResNo() != InputVector.getResNo())
13245 SDNode *Extract = *UI;
13246 if (Extract->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
13249 if (Extract->getValueType(0) != MVT::i32)
13251 if (!Extract->hasOneUse())
13253 if (Extract->use_begin()->getOpcode() != ISD::SIGN_EXTEND &&
13254 Extract->use_begin()->getOpcode() != ISD::ZERO_EXTEND)
13256 if (!isa<ConstantSDNode>(Extract->getOperand(1)))
13259 // Record which element was extracted.
13260 ExtractedElements |=
13261 1 << cast<ConstantSDNode>(Extract->getOperand(1))->getZExtValue();
13263 Uses.push_back(Extract);
13266 // If not all the elements were used, this may not be worthwhile.
13267 if (ExtractedElements != 15)
13270 // Ok, we've now decided to do the transformation.
13271 DebugLoc dl = InputVector.getDebugLoc();
13273 // Store the value to a temporary stack slot.
13274 SDValue StackPtr = DAG.CreateStackTemporary(InputVector.getValueType());
13275 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, InputVector, StackPtr,
13276 MachinePointerInfo(), false, false, 0);
13278 // Replace each use (extract) with a load of the appropriate element.
13279 for (SmallVectorImpl<SDNode *>::iterator UI = Uses.begin(),
13280 UE = Uses.end(); UI != UE; ++UI) {
13281 SDNode *Extract = *UI;
13283 // cOMpute the element's address.
13284 SDValue Idx = Extract->getOperand(1);
13286 InputVector.getValueType().getVectorElementType().getSizeInBits()/8;
13287 uint64_t Offset = EltSize * cast<ConstantSDNode>(Idx)->getZExtValue();
13288 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
13289 SDValue OffsetVal = DAG.getConstant(Offset, TLI.getPointerTy());
13291 SDValue ScalarAddr = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(),
13292 StackPtr, OffsetVal);
13294 // Load the scalar.
13295 SDValue LoadScalar = DAG.getLoad(Extract->getValueType(0), dl, Ch,
13296 ScalarAddr, MachinePointerInfo(),
13297 false, false, false, 0);
13299 // Replace the exact with the load.
13300 DAG.ReplaceAllUsesOfValueWith(SDValue(Extract, 0), LoadScalar);
13303 // The replacement was made in place; don't return anything.
13307 /// PerformSELECTCombine - Do target-specific dag combines on SELECT and VSELECT
13309 static SDValue PerformSELECTCombine(SDNode *N, SelectionDAG &DAG,
13310 TargetLowering::DAGCombinerInfo &DCI,
13311 const X86Subtarget *Subtarget) {
13314 DebugLoc DL = N->getDebugLoc();
13315 SDValue Cond = N->getOperand(0);
13316 // Get the LHS/RHS of the select.
13317 SDValue LHS = N->getOperand(1);
13318 SDValue RHS = N->getOperand(2);
13319 EVT VT = LHS.getValueType();
13321 // If we have SSE[12] support, try to form min/max nodes. SSE min/max
13322 // instructions match the semantics of the common C idiom x<y?x:y but not
13323 // x<=y?x:y, because of how they handle negative zero (which can be
13324 // ignored in unsafe-math mode).
13325 if (Cond.getOpcode() == ISD::SETCC && VT.isFloatingPoint() &&
13326 VT != MVT::f80 && DAG.getTargetLoweringInfo().isTypeLegal(VT) &&
13327 (Subtarget->hasSSE2() ||
13328 (Subtarget->hasSSE1() && VT.getScalarType() == MVT::f32))) {
13329 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
13331 unsigned Opcode = 0;
13332 // Check for x CC y ? x : y.
13333 if (DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
13334 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
13338 // Converting this to a min would handle NaNs incorrectly, and swapping
13339 // the operands would cause it to handle comparisons between positive
13340 // and negative zero incorrectly.
13341 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
13342 if (!DAG.getTarget().Options.UnsafeFPMath &&
13343 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
13345 std::swap(LHS, RHS);
13347 Opcode = X86ISD::FMIN;
13350 // Converting this to a min would handle comparisons between positive
13351 // and negative zero incorrectly.
13352 if (!DAG.getTarget().Options.UnsafeFPMath &&
13353 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
13355 Opcode = X86ISD::FMIN;
13358 // Converting this to a min would handle both negative zeros and NaNs
13359 // incorrectly, but we can swap the operands to fix both.
13360 std::swap(LHS, RHS);
13364 Opcode = X86ISD::FMIN;
13368 // Converting this to a max would handle comparisons between positive
13369 // and negative zero incorrectly.
13370 if (!DAG.getTarget().Options.UnsafeFPMath &&
13371 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
13373 Opcode = X86ISD::FMAX;
13376 // Converting this to a max would handle NaNs incorrectly, and swapping
13377 // the operands would cause it to handle comparisons between positive
13378 // and negative zero incorrectly.
13379 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
13380 if (!DAG.getTarget().Options.UnsafeFPMath &&
13381 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
13383 std::swap(LHS, RHS);
13385 Opcode = X86ISD::FMAX;
13388 // Converting this to a max would handle both negative zeros and NaNs
13389 // incorrectly, but we can swap the operands to fix both.
13390 std::swap(LHS, RHS);
13394 Opcode = X86ISD::FMAX;
13397 // Check for x CC y ? y : x -- a min/max with reversed arms.
13398 } else if (DAG.isEqualTo(LHS, Cond.getOperand(1)) &&
13399 DAG.isEqualTo(RHS, Cond.getOperand(0))) {
13403 // Converting this to a min would handle comparisons between positive
13404 // and negative zero incorrectly, and swapping the operands would
13405 // cause it to handle NaNs incorrectly.
13406 if (!DAG.getTarget().Options.UnsafeFPMath &&
13407 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS))) {
13408 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
13410 std::swap(LHS, RHS);
13412 Opcode = X86ISD::FMIN;
13415 // Converting this to a min would handle NaNs incorrectly.
13416 if (!DAG.getTarget().Options.UnsafeFPMath &&
13417 (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)))
13419 Opcode = X86ISD::FMIN;
13422 // Converting this to a min would handle both negative zeros and NaNs
13423 // incorrectly, but we can swap the operands to fix both.
13424 std::swap(LHS, RHS);
13428 Opcode = X86ISD::FMIN;
13432 // Converting this to a max would handle NaNs incorrectly.
13433 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
13435 Opcode = X86ISD::FMAX;
13438 // Converting this to a max would handle comparisons between positive
13439 // and negative zero incorrectly, and swapping the operands would
13440 // cause it to handle NaNs incorrectly.
13441 if (!DAG.getTarget().Options.UnsafeFPMath &&
13442 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS)) {
13443 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
13445 std::swap(LHS, RHS);
13447 Opcode = X86ISD::FMAX;
13450 // Converting this to a max would handle both negative zeros and NaNs
13451 // incorrectly, but we can swap the operands to fix both.
13452 std::swap(LHS, RHS);
13456 Opcode = X86ISD::FMAX;
13462 return DAG.getNode(Opcode, DL, N->getValueType(0), LHS, RHS);
13465 // If this is a select between two integer constants, try to do some
13467 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(LHS)) {
13468 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(RHS))
13469 // Don't do this for crazy integer types.
13470 if (DAG.getTargetLoweringInfo().isTypeLegal(LHS.getValueType())) {
13471 // If this is efficiently invertible, canonicalize the LHSC/RHSC values
13472 // so that TrueC (the true value) is larger than FalseC.
13473 bool NeedsCondInvert = false;
13475 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue()) &&
13476 // Efficiently invertible.
13477 (Cond.getOpcode() == ISD::SETCC || // setcc -> invertible.
13478 (Cond.getOpcode() == ISD::XOR && // xor(X, C) -> invertible.
13479 isa<ConstantSDNode>(Cond.getOperand(1))))) {
13480 NeedsCondInvert = true;
13481 std::swap(TrueC, FalseC);
13484 // Optimize C ? 8 : 0 -> zext(C) << 3. Likewise for any pow2/0.
13485 if (FalseC->getAPIntValue() == 0 &&
13486 TrueC->getAPIntValue().isPowerOf2()) {
13487 if (NeedsCondInvert) // Invert the condition if needed.
13488 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
13489 DAG.getConstant(1, Cond.getValueType()));
13491 // Zero extend the condition if needed.
13492 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, LHS.getValueType(), Cond);
13494 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
13495 return DAG.getNode(ISD::SHL, DL, LHS.getValueType(), Cond,
13496 DAG.getConstant(ShAmt, MVT::i8));
13499 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst.
13500 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
13501 if (NeedsCondInvert) // Invert the condition if needed.
13502 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
13503 DAG.getConstant(1, Cond.getValueType()));
13505 // Zero extend the condition if needed.
13506 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
13507 FalseC->getValueType(0), Cond);
13508 return DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
13509 SDValue(FalseC, 0));
13512 // Optimize cases that will turn into an LEA instruction. This requires
13513 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
13514 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
13515 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
13516 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
13518 bool isFastMultiplier = false;
13520 switch ((unsigned char)Diff) {
13522 case 1: // result = add base, cond
13523 case 2: // result = lea base( , cond*2)
13524 case 3: // result = lea base(cond, cond*2)
13525 case 4: // result = lea base( , cond*4)
13526 case 5: // result = lea base(cond, cond*4)
13527 case 8: // result = lea base( , cond*8)
13528 case 9: // result = lea base(cond, cond*8)
13529 isFastMultiplier = true;
13534 if (isFastMultiplier) {
13535 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
13536 if (NeedsCondInvert) // Invert the condition if needed.
13537 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
13538 DAG.getConstant(1, Cond.getValueType()));
13540 // Zero extend the condition if needed.
13541 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
13543 // Scale the condition by the difference.
13545 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
13546 DAG.getConstant(Diff, Cond.getValueType()));
13548 // Add the base if non-zero.
13549 if (FalseC->getAPIntValue() != 0)
13550 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
13551 SDValue(FalseC, 0));
13558 // Canonicalize max and min:
13559 // (x > y) ? x : y -> (x >= y) ? x : y
13560 // (x < y) ? x : y -> (x <= y) ? x : y
13561 // This allows use of COND_S / COND_NS (see TranslateX86CC) which eliminates
13562 // the need for an extra compare
13563 // against zero. e.g.
13564 // (x - y) > 0 : (x - y) ? 0 -> (x - y) >= 0 : (x - y) ? 0
13566 // testl %edi, %edi
13568 // cmovgl %edi, %eax
13572 // cmovsl %eax, %edi
13573 if (N->getOpcode() == ISD::SELECT && Cond.getOpcode() == ISD::SETCC &&
13574 DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
13575 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
13576 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
13581 ISD::CondCode NewCC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGE;
13582 Cond = DAG.getSetCC(Cond.getDebugLoc(), Cond.getValueType(),
13583 Cond.getOperand(0), Cond.getOperand(1), NewCC);
13584 return DAG.getNode(ISD::SELECT, DL, VT, Cond, LHS, RHS);
13589 // If we know that this node is legal then we know that it is going to be
13590 // matched by one of the SSE/AVX BLEND instructions. These instructions only
13591 // depend on the highest bit in each word. Try to use SimplifyDemandedBits
13592 // to simplify previous instructions.
13593 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
13594 if (N->getOpcode() == ISD::VSELECT && DCI.isBeforeLegalizeOps() &&
13595 !DCI.isBeforeLegalize() &&
13596 TLI.isOperationLegal(ISD::VSELECT, VT)) {
13597 unsigned BitWidth = Cond.getValueType().getScalarType().getSizeInBits();
13598 assert(BitWidth >= 8 && BitWidth <= 64 && "Invalid mask size");
13599 APInt DemandedMask = APInt::getHighBitsSet(BitWidth, 1);
13601 APInt KnownZero, KnownOne;
13602 TargetLowering::TargetLoweringOpt TLO(DAG, DCI.isBeforeLegalize(),
13603 DCI.isBeforeLegalizeOps());
13604 if (TLO.ShrinkDemandedConstant(Cond, DemandedMask) ||
13605 TLI.SimplifyDemandedBits(Cond, DemandedMask, KnownZero, KnownOne, TLO))
13606 DCI.CommitTargetLoweringOpt(TLO);
13612 /// Optimize X86ISD::CMOV [LHS, RHS, CONDCODE (e.g. X86::COND_NE), CONDVAL]
13613 static SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG,
13614 TargetLowering::DAGCombinerInfo &DCI) {
13615 DebugLoc DL = N->getDebugLoc();
13617 // If the flag operand isn't dead, don't touch this CMOV.
13618 if (N->getNumValues() == 2 && !SDValue(N, 1).use_empty())
13621 SDValue FalseOp = N->getOperand(0);
13622 SDValue TrueOp = N->getOperand(1);
13623 X86::CondCode CC = (X86::CondCode)N->getConstantOperandVal(2);
13624 SDValue Cond = N->getOperand(3);
13625 if (CC == X86::COND_E || CC == X86::COND_NE) {
13626 switch (Cond.getOpcode()) {
13630 // If operand of BSR / BSF are proven never zero, then ZF cannot be set.
13631 if (DAG.isKnownNeverZero(Cond.getOperand(0)))
13632 return (CC == X86::COND_E) ? FalseOp : TrueOp;
13636 // If this is a select between two integer constants, try to do some
13637 // optimizations. Note that the operands are ordered the opposite of SELECT
13639 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(TrueOp)) {
13640 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(FalseOp)) {
13641 // Canonicalize the TrueC/FalseC values so that TrueC (the true value) is
13642 // larger than FalseC (the false value).
13643 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue())) {
13644 CC = X86::GetOppositeBranchCondition(CC);
13645 std::swap(TrueC, FalseC);
13648 // Optimize C ? 8 : 0 -> zext(setcc(C)) << 3. Likewise for any pow2/0.
13649 // This is efficient for any integer data type (including i8/i16) and
13651 if (FalseC->getAPIntValue() == 0 && TrueC->getAPIntValue().isPowerOf2()) {
13652 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
13653 DAG.getConstant(CC, MVT::i8), Cond);
13655 // Zero extend the condition if needed.
13656 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, TrueC->getValueType(0), Cond);
13658 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
13659 Cond = DAG.getNode(ISD::SHL, DL, Cond.getValueType(), Cond,
13660 DAG.getConstant(ShAmt, MVT::i8));
13661 if (N->getNumValues() == 2) // Dead flag value?
13662 return DCI.CombineTo(N, Cond, SDValue());
13666 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst. This is efficient
13667 // for any integer data type, including i8/i16.
13668 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
13669 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
13670 DAG.getConstant(CC, MVT::i8), Cond);
13672 // Zero extend the condition if needed.
13673 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
13674 FalseC->getValueType(0), Cond);
13675 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
13676 SDValue(FalseC, 0));
13678 if (N->getNumValues() == 2) // Dead flag value?
13679 return DCI.CombineTo(N, Cond, SDValue());
13683 // Optimize cases that will turn into an LEA instruction. This requires
13684 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
13685 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
13686 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
13687 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
13689 bool isFastMultiplier = false;
13691 switch ((unsigned char)Diff) {
13693 case 1: // result = add base, cond
13694 case 2: // result = lea base( , cond*2)
13695 case 3: // result = lea base(cond, cond*2)
13696 case 4: // result = lea base( , cond*4)
13697 case 5: // result = lea base(cond, cond*4)
13698 case 8: // result = lea base( , cond*8)
13699 case 9: // result = lea base(cond, cond*8)
13700 isFastMultiplier = true;
13705 if (isFastMultiplier) {
13706 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
13707 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
13708 DAG.getConstant(CC, MVT::i8), Cond);
13709 // Zero extend the condition if needed.
13710 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
13712 // Scale the condition by the difference.
13714 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
13715 DAG.getConstant(Diff, Cond.getValueType()));
13717 // Add the base if non-zero.
13718 if (FalseC->getAPIntValue() != 0)
13719 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
13720 SDValue(FalseC, 0));
13721 if (N->getNumValues() == 2) // Dead flag value?
13722 return DCI.CombineTo(N, Cond, SDValue());
13732 /// PerformMulCombine - Optimize a single multiply with constant into two
13733 /// in order to implement it with two cheaper instructions, e.g.
13734 /// LEA + SHL, LEA + LEA.
13735 static SDValue PerformMulCombine(SDNode *N, SelectionDAG &DAG,
13736 TargetLowering::DAGCombinerInfo &DCI) {
13737 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer())
13740 EVT VT = N->getValueType(0);
13741 if (VT != MVT::i64)
13744 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
13747 uint64_t MulAmt = C->getZExtValue();
13748 if (isPowerOf2_64(MulAmt) || MulAmt == 3 || MulAmt == 5 || MulAmt == 9)
13751 uint64_t MulAmt1 = 0;
13752 uint64_t MulAmt2 = 0;
13753 if ((MulAmt % 9) == 0) {
13755 MulAmt2 = MulAmt / 9;
13756 } else if ((MulAmt % 5) == 0) {
13758 MulAmt2 = MulAmt / 5;
13759 } else if ((MulAmt % 3) == 0) {
13761 MulAmt2 = MulAmt / 3;
13764 (isPowerOf2_64(MulAmt2) || MulAmt2 == 3 || MulAmt2 == 5 || MulAmt2 == 9)){
13765 DebugLoc DL = N->getDebugLoc();
13767 if (isPowerOf2_64(MulAmt2) &&
13768 !(N->hasOneUse() && N->use_begin()->getOpcode() == ISD::ADD))
13769 // If second multiplifer is pow2, issue it first. We want the multiply by
13770 // 3, 5, or 9 to be folded into the addressing mode unless the lone use
13772 std::swap(MulAmt1, MulAmt2);
13775 if (isPowerOf2_64(MulAmt1))
13776 NewMul = DAG.getNode(ISD::SHL, DL, VT, N->getOperand(0),
13777 DAG.getConstant(Log2_64(MulAmt1), MVT::i8));
13779 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, N->getOperand(0),
13780 DAG.getConstant(MulAmt1, VT));
13782 if (isPowerOf2_64(MulAmt2))
13783 NewMul = DAG.getNode(ISD::SHL, DL, VT, NewMul,
13784 DAG.getConstant(Log2_64(MulAmt2), MVT::i8));
13786 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, NewMul,
13787 DAG.getConstant(MulAmt2, VT));
13789 // Do not add new nodes to DAG combiner worklist.
13790 DCI.CombineTo(N, NewMul, false);
13795 static SDValue PerformSHLCombine(SDNode *N, SelectionDAG &DAG) {
13796 SDValue N0 = N->getOperand(0);
13797 SDValue N1 = N->getOperand(1);
13798 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
13799 EVT VT = N0.getValueType();
13801 // fold (shl (and (setcc_c), c1), c2) -> (and setcc_c, (c1 << c2))
13802 // since the result of setcc_c is all zero's or all ones.
13803 if (VT.isInteger() && !VT.isVector() &&
13804 N1C && N0.getOpcode() == ISD::AND &&
13805 N0.getOperand(1).getOpcode() == ISD::Constant) {
13806 SDValue N00 = N0.getOperand(0);
13807 if (N00.getOpcode() == X86ISD::SETCC_CARRY ||
13808 ((N00.getOpcode() == ISD::ANY_EXTEND ||
13809 N00.getOpcode() == ISD::ZERO_EXTEND) &&
13810 N00.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY)) {
13811 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
13812 APInt ShAmt = N1C->getAPIntValue();
13813 Mask = Mask.shl(ShAmt);
13815 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT,
13816 N00, DAG.getConstant(Mask, VT));
13821 // Hardware support for vector shifts is sparse which makes us scalarize the
13822 // vector operations in many cases. Also, on sandybridge ADD is faster than
13824 // (shl V, 1) -> add V,V
13825 if (isSplatVector(N1.getNode())) {
13826 assert(N0.getValueType().isVector() && "Invalid vector shift type");
13827 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1->getOperand(0));
13828 // We shift all of the values by one. In many cases we do not have
13829 // hardware support for this operation. This is better expressed as an ADD
13831 if (N1C && (1 == N1C->getZExtValue())) {
13832 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N0, N0);
13839 /// PerformShiftCombine - Transforms vector shift nodes to use vector shifts
13841 static SDValue PerformShiftCombine(SDNode* N, SelectionDAG &DAG,
13842 TargetLowering::DAGCombinerInfo &DCI,
13843 const X86Subtarget *Subtarget) {
13844 EVT VT = N->getValueType(0);
13845 if (N->getOpcode() == ISD::SHL) {
13846 SDValue V = PerformSHLCombine(N, DAG);
13847 if (V.getNode()) return V;
13850 // On X86 with SSE2 support, we can transform this to a vector shift if
13851 // all elements are shifted by the same amount. We can't do this in legalize
13852 // because the a constant vector is typically transformed to a constant pool
13853 // so we have no knowledge of the shift amount.
13854 if (!Subtarget->hasSSE2())
13857 if (VT != MVT::v2i64 && VT != MVT::v4i32 && VT != MVT::v8i16 &&
13858 (!Subtarget->hasAVX2() ||
13859 (VT != MVT::v4i64 && VT != MVT::v8i32 && VT != MVT::v16i16)))
13862 SDValue ShAmtOp = N->getOperand(1);
13863 EVT EltVT = VT.getVectorElementType();
13864 DebugLoc DL = N->getDebugLoc();
13865 SDValue BaseShAmt = SDValue();
13866 if (ShAmtOp.getOpcode() == ISD::BUILD_VECTOR) {
13867 unsigned NumElts = VT.getVectorNumElements();
13869 for (; i != NumElts; ++i) {
13870 SDValue Arg = ShAmtOp.getOperand(i);
13871 if (Arg.getOpcode() == ISD::UNDEF) continue;
13875 // Handle the case where the build_vector is all undef
13876 // FIXME: Should DAG allow this?
13880 for (; i != NumElts; ++i) {
13881 SDValue Arg = ShAmtOp.getOperand(i);
13882 if (Arg.getOpcode() == ISD::UNDEF) continue;
13883 if (Arg != BaseShAmt) {
13887 } else if (ShAmtOp.getOpcode() == ISD::VECTOR_SHUFFLE &&
13888 cast<ShuffleVectorSDNode>(ShAmtOp)->isSplat()) {
13889 SDValue InVec = ShAmtOp.getOperand(0);
13890 if (InVec.getOpcode() == ISD::BUILD_VECTOR) {
13891 unsigned NumElts = InVec.getValueType().getVectorNumElements();
13893 for (; i != NumElts; ++i) {
13894 SDValue Arg = InVec.getOperand(i);
13895 if (Arg.getOpcode() == ISD::UNDEF) continue;
13899 } else if (InVec.getOpcode() == ISD::INSERT_VECTOR_ELT) {
13900 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(InVec.getOperand(2))) {
13901 unsigned SplatIdx= cast<ShuffleVectorSDNode>(ShAmtOp)->getSplatIndex();
13902 if (C->getZExtValue() == SplatIdx)
13903 BaseShAmt = InVec.getOperand(1);
13906 if (BaseShAmt.getNode() == 0) {
13907 // Don't create instructions with illegal types after legalize
13909 if (!DAG.getTargetLoweringInfo().isTypeLegal(EltVT) &&
13910 !DCI.isBeforeLegalize())
13913 BaseShAmt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, EltVT, ShAmtOp,
13914 DAG.getIntPtrConstant(0));
13919 // The shift amount is an i32.
13920 if (EltVT.bitsGT(MVT::i32))
13921 BaseShAmt = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, BaseShAmt);
13922 else if (EltVT.bitsLT(MVT::i32))
13923 BaseShAmt = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i32, BaseShAmt);
13925 // The shift amount is identical so we can do a vector shift.
13926 SDValue ValOp = N->getOperand(0);
13927 switch (N->getOpcode()) {
13929 llvm_unreachable("Unknown shift opcode!");
13931 switch (VT.getSimpleVT().SimpleTy) {
13932 default: return SDValue();
13939 return getTargetVShiftNode(X86ISD::VSHLI, DL, VT, ValOp, BaseShAmt, DAG);
13942 switch (VT.getSimpleVT().SimpleTy) {
13943 default: return SDValue();
13948 return getTargetVShiftNode(X86ISD::VSRAI, DL, VT, ValOp, BaseShAmt, DAG);
13951 switch (VT.getSimpleVT().SimpleTy) {
13952 default: return SDValue();
13959 return getTargetVShiftNode(X86ISD::VSRLI, DL, VT, ValOp, BaseShAmt, DAG);
13965 // CMPEQCombine - Recognize the distinctive (AND (setcc ...) (setcc ..))
13966 // where both setccs reference the same FP CMP, and rewrite for CMPEQSS
13967 // and friends. Likewise for OR -> CMPNEQSS.
13968 static SDValue CMPEQCombine(SDNode *N, SelectionDAG &DAG,
13969 TargetLowering::DAGCombinerInfo &DCI,
13970 const X86Subtarget *Subtarget) {
13973 // SSE1 supports CMP{eq|ne}SS, and SSE2 added CMP{eq|ne}SD, but
13974 // we're requiring SSE2 for both.
13975 if (Subtarget->hasSSE2() && isAndOrOfSetCCs(SDValue(N, 0U), opcode)) {
13976 SDValue N0 = N->getOperand(0);
13977 SDValue N1 = N->getOperand(1);
13978 SDValue CMP0 = N0->getOperand(1);
13979 SDValue CMP1 = N1->getOperand(1);
13980 DebugLoc DL = N->getDebugLoc();
13982 // The SETCCs should both refer to the same CMP.
13983 if (CMP0.getOpcode() != X86ISD::CMP || CMP0 != CMP1)
13986 SDValue CMP00 = CMP0->getOperand(0);
13987 SDValue CMP01 = CMP0->getOperand(1);
13988 EVT VT = CMP00.getValueType();
13990 if (VT == MVT::f32 || VT == MVT::f64) {
13991 bool ExpectingFlags = false;
13992 // Check for any users that want flags:
13993 for (SDNode::use_iterator UI = N->use_begin(),
13995 !ExpectingFlags && UI != UE; ++UI)
13996 switch (UI->getOpcode()) {
14001 ExpectingFlags = true;
14003 case ISD::CopyToReg:
14004 case ISD::SIGN_EXTEND:
14005 case ISD::ZERO_EXTEND:
14006 case ISD::ANY_EXTEND:
14010 if (!ExpectingFlags) {
14011 enum X86::CondCode cc0 = (enum X86::CondCode)N0.getConstantOperandVal(0);
14012 enum X86::CondCode cc1 = (enum X86::CondCode)N1.getConstantOperandVal(0);
14014 if (cc1 == X86::COND_E || cc1 == X86::COND_NE) {
14015 X86::CondCode tmp = cc0;
14020 if ((cc0 == X86::COND_E && cc1 == X86::COND_NP) ||
14021 (cc0 == X86::COND_NE && cc1 == X86::COND_P)) {
14022 bool is64BitFP = (CMP00.getValueType() == MVT::f64);
14023 X86ISD::NodeType NTOperator = is64BitFP ?
14024 X86ISD::FSETCCsd : X86ISD::FSETCCss;
14025 // FIXME: need symbolic constants for these magic numbers.
14026 // See X86ATTInstPrinter.cpp:printSSECC().
14027 unsigned x86cc = (cc0 == X86::COND_E) ? 0 : 4;
14028 SDValue OnesOrZeroesF = DAG.getNode(NTOperator, DL, MVT::f32, CMP00, CMP01,
14029 DAG.getConstant(x86cc, MVT::i8));
14030 SDValue OnesOrZeroesI = DAG.getNode(ISD::BITCAST, DL, MVT::i32,
14032 SDValue ANDed = DAG.getNode(ISD::AND, DL, MVT::i32, OnesOrZeroesI,
14033 DAG.getConstant(1, MVT::i32));
14034 SDValue OneBitOfTruth = DAG.getNode(ISD::TRUNCATE, DL, MVT::i8, ANDed);
14035 return OneBitOfTruth;
14043 /// CanFoldXORWithAllOnes - Test whether the XOR operand is a AllOnes vector
14044 /// so it can be folded inside ANDNP.
14045 static bool CanFoldXORWithAllOnes(const SDNode *N) {
14046 EVT VT = N->getValueType(0);
14048 // Match direct AllOnes for 128 and 256-bit vectors
14049 if (ISD::isBuildVectorAllOnes(N))
14052 // Look through a bit convert.
14053 if (N->getOpcode() == ISD::BITCAST)
14054 N = N->getOperand(0).getNode();
14056 // Sometimes the operand may come from a insert_subvector building a 256-bit
14058 if (VT.getSizeInBits() == 256 &&
14059 N->getOpcode() == ISD::INSERT_SUBVECTOR) {
14060 SDValue V1 = N->getOperand(0);
14061 SDValue V2 = N->getOperand(1);
14063 if (V1.getOpcode() == ISD::INSERT_SUBVECTOR &&
14064 V1.getOperand(0).getOpcode() == ISD::UNDEF &&
14065 ISD::isBuildVectorAllOnes(V1.getOperand(1).getNode()) &&
14066 ISD::isBuildVectorAllOnes(V2.getNode()))
14073 static SDValue PerformAndCombine(SDNode *N, SelectionDAG &DAG,
14074 TargetLowering::DAGCombinerInfo &DCI,
14075 const X86Subtarget *Subtarget) {
14076 if (DCI.isBeforeLegalizeOps())
14079 SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget);
14083 EVT VT = N->getValueType(0);
14085 // Create ANDN, BLSI, and BLSR instructions
14086 // BLSI is X & (-X)
14087 // BLSR is X & (X-1)
14088 if (Subtarget->hasBMI() && (VT == MVT::i32 || VT == MVT::i64)) {
14089 SDValue N0 = N->getOperand(0);
14090 SDValue N1 = N->getOperand(1);
14091 DebugLoc DL = N->getDebugLoc();
14093 // Check LHS for not
14094 if (N0.getOpcode() == ISD::XOR && isAllOnes(N0.getOperand(1)))
14095 return DAG.getNode(X86ISD::ANDN, DL, VT, N0.getOperand(0), N1);
14096 // Check RHS for not
14097 if (N1.getOpcode() == ISD::XOR && isAllOnes(N1.getOperand(1)))
14098 return DAG.getNode(X86ISD::ANDN, DL, VT, N1.getOperand(0), N0);
14100 // Check LHS for neg
14101 if (N0.getOpcode() == ISD::SUB && N0.getOperand(1) == N1 &&
14102 isZero(N0.getOperand(0)))
14103 return DAG.getNode(X86ISD::BLSI, DL, VT, N1);
14105 // Check RHS for neg
14106 if (N1.getOpcode() == ISD::SUB && N1.getOperand(1) == N0 &&
14107 isZero(N1.getOperand(0)))
14108 return DAG.getNode(X86ISD::BLSI, DL, VT, N0);
14110 // Check LHS for X-1
14111 if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1 &&
14112 isAllOnes(N0.getOperand(1)))
14113 return DAG.getNode(X86ISD::BLSR, DL, VT, N1);
14115 // Check RHS for X-1
14116 if (N1.getOpcode() == ISD::ADD && N1.getOperand(0) == N0 &&
14117 isAllOnes(N1.getOperand(1)))
14118 return DAG.getNode(X86ISD::BLSR, DL, VT, N0);
14123 // Want to form ANDNP nodes:
14124 // 1) In the hopes of then easily combining them with OR and AND nodes
14125 // to form PBLEND/PSIGN.
14126 // 2) To match ANDN packed intrinsics
14127 if (VT != MVT::v2i64 && VT != MVT::v4i64)
14130 SDValue N0 = N->getOperand(0);
14131 SDValue N1 = N->getOperand(1);
14132 DebugLoc DL = N->getDebugLoc();
14134 // Check LHS for vnot
14135 if (N0.getOpcode() == ISD::XOR &&
14136 //ISD::isBuildVectorAllOnes(N0.getOperand(1).getNode()))
14137 CanFoldXORWithAllOnes(N0.getOperand(1).getNode()))
14138 return DAG.getNode(X86ISD::ANDNP, DL, VT, N0.getOperand(0), N1);
14140 // Check RHS for vnot
14141 if (N1.getOpcode() == ISD::XOR &&
14142 //ISD::isBuildVectorAllOnes(N1.getOperand(1).getNode()))
14143 CanFoldXORWithAllOnes(N1.getOperand(1).getNode()))
14144 return DAG.getNode(X86ISD::ANDNP, DL, VT, N1.getOperand(0), N0);
14149 static SDValue PerformOrCombine(SDNode *N, SelectionDAG &DAG,
14150 TargetLowering::DAGCombinerInfo &DCI,
14151 const X86Subtarget *Subtarget) {
14152 if (DCI.isBeforeLegalizeOps())
14155 SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget);
14159 EVT VT = N->getValueType(0);
14161 SDValue N0 = N->getOperand(0);
14162 SDValue N1 = N->getOperand(1);
14164 // look for psign/blend
14165 if (VT == MVT::v2i64 || VT == MVT::v4i64) {
14166 if (!Subtarget->hasSSSE3() ||
14167 (VT == MVT::v4i64 && !Subtarget->hasAVX2()))
14170 // Canonicalize pandn to RHS
14171 if (N0.getOpcode() == X86ISD::ANDNP)
14173 // or (and (m, y), (pandn m, x))
14174 if (N0.getOpcode() == ISD::AND && N1.getOpcode() == X86ISD::ANDNP) {
14175 SDValue Mask = N1.getOperand(0);
14176 SDValue X = N1.getOperand(1);
14178 if (N0.getOperand(0) == Mask)
14179 Y = N0.getOperand(1);
14180 if (N0.getOperand(1) == Mask)
14181 Y = N0.getOperand(0);
14183 // Check to see if the mask appeared in both the AND and ANDNP and
14187 // Validate that X, Y, and Mask are BIT_CONVERTS, and see through them.
14188 // Look through mask bitcast.
14189 if (Mask.getOpcode() == ISD::BITCAST)
14190 Mask = Mask.getOperand(0);
14191 if (X.getOpcode() == ISD::BITCAST)
14192 X = X.getOperand(0);
14193 if (Y.getOpcode() == ISD::BITCAST)
14194 Y = Y.getOperand(0);
14196 EVT MaskVT = Mask.getValueType();
14198 // Validate that the Mask operand is a vector sra node.
14199 // FIXME: what to do for bytes, since there is a psignb/pblendvb, but
14200 // there is no psrai.b
14201 if (Mask.getOpcode() != X86ISD::VSRAI)
14204 // Check that the SRA is all signbits.
14205 SDValue SraC = Mask.getOperand(1);
14206 unsigned SraAmt = cast<ConstantSDNode>(SraC)->getZExtValue();
14207 unsigned EltBits = MaskVT.getVectorElementType().getSizeInBits();
14208 if ((SraAmt + 1) != EltBits)
14211 DebugLoc DL = N->getDebugLoc();
14213 // Now we know we at least have a plendvb with the mask val. See if
14214 // we can form a psignb/w/d.
14215 // psign = x.type == y.type == mask.type && y = sub(0, x);
14216 if (Y.getOpcode() == ISD::SUB && Y.getOperand(1) == X &&
14217 ISD::isBuildVectorAllZeros(Y.getOperand(0).getNode()) &&
14218 X.getValueType() == MaskVT && Y.getValueType() == MaskVT) {
14219 assert((EltBits == 8 || EltBits == 16 || EltBits == 32) &&
14220 "Unsupported VT for PSIGN");
14221 Mask = DAG.getNode(X86ISD::PSIGN, DL, MaskVT, X, Mask.getOperand(0));
14222 return DAG.getNode(ISD::BITCAST, DL, VT, Mask);
14224 // PBLENDVB only available on SSE 4.1
14225 if (!Subtarget->hasSSE41())
14228 EVT BlendVT = (VT == MVT::v4i64) ? MVT::v32i8 : MVT::v16i8;
14230 X = DAG.getNode(ISD::BITCAST, DL, BlendVT, X);
14231 Y = DAG.getNode(ISD::BITCAST, DL, BlendVT, Y);
14232 Mask = DAG.getNode(ISD::BITCAST, DL, BlendVT, Mask);
14233 Mask = DAG.getNode(ISD::VSELECT, DL, BlendVT, Mask, Y, X);
14234 return DAG.getNode(ISD::BITCAST, DL, VT, Mask);
14238 if (VT != MVT::i16 && VT != MVT::i32 && VT != MVT::i64)
14241 // fold (or (x << c) | (y >> (64 - c))) ==> (shld64 x, y, c)
14242 if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL)
14244 if (N0.getOpcode() != ISD::SHL || N1.getOpcode() != ISD::SRL)
14246 if (!N0.hasOneUse() || !N1.hasOneUse())
14249 SDValue ShAmt0 = N0.getOperand(1);
14250 if (ShAmt0.getValueType() != MVT::i8)
14252 SDValue ShAmt1 = N1.getOperand(1);
14253 if (ShAmt1.getValueType() != MVT::i8)
14255 if (ShAmt0.getOpcode() == ISD::TRUNCATE)
14256 ShAmt0 = ShAmt0.getOperand(0);
14257 if (ShAmt1.getOpcode() == ISD::TRUNCATE)
14258 ShAmt1 = ShAmt1.getOperand(0);
14260 DebugLoc DL = N->getDebugLoc();
14261 unsigned Opc = X86ISD::SHLD;
14262 SDValue Op0 = N0.getOperand(0);
14263 SDValue Op1 = N1.getOperand(0);
14264 if (ShAmt0.getOpcode() == ISD::SUB) {
14265 Opc = X86ISD::SHRD;
14266 std::swap(Op0, Op1);
14267 std::swap(ShAmt0, ShAmt1);
14270 unsigned Bits = VT.getSizeInBits();
14271 if (ShAmt1.getOpcode() == ISD::SUB) {
14272 SDValue Sum = ShAmt1.getOperand(0);
14273 if (ConstantSDNode *SumC = dyn_cast<ConstantSDNode>(Sum)) {
14274 SDValue ShAmt1Op1 = ShAmt1.getOperand(1);
14275 if (ShAmt1Op1.getNode()->getOpcode() == ISD::TRUNCATE)
14276 ShAmt1Op1 = ShAmt1Op1.getOperand(0);
14277 if (SumC->getSExtValue() == Bits && ShAmt1Op1 == ShAmt0)
14278 return DAG.getNode(Opc, DL, VT,
14280 DAG.getNode(ISD::TRUNCATE, DL,
14283 } else if (ConstantSDNode *ShAmt1C = dyn_cast<ConstantSDNode>(ShAmt1)) {
14284 ConstantSDNode *ShAmt0C = dyn_cast<ConstantSDNode>(ShAmt0);
14286 ShAmt0C->getSExtValue() + ShAmt1C->getSExtValue() == Bits)
14287 return DAG.getNode(Opc, DL, VT,
14288 N0.getOperand(0), N1.getOperand(0),
14289 DAG.getNode(ISD::TRUNCATE, DL,
14296 // PerformXorCombine - Attempts to turn XOR nodes into BLSMSK nodes
14297 static SDValue PerformXorCombine(SDNode *N, SelectionDAG &DAG,
14298 TargetLowering::DAGCombinerInfo &DCI,
14299 const X86Subtarget *Subtarget) {
14300 if (DCI.isBeforeLegalizeOps())
14303 EVT VT = N->getValueType(0);
14305 if (VT != MVT::i32 && VT != MVT::i64)
14308 assert(Subtarget->hasBMI() && "Creating BLSMSK requires BMI instructions");
14310 // Create BLSMSK instructions by finding X ^ (X-1)
14311 SDValue N0 = N->getOperand(0);
14312 SDValue N1 = N->getOperand(1);
14313 DebugLoc DL = N->getDebugLoc();
14315 if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1 &&
14316 isAllOnes(N0.getOperand(1)))
14317 return DAG.getNode(X86ISD::BLSMSK, DL, VT, N1);
14319 if (N1.getOpcode() == ISD::ADD && N1.getOperand(0) == N0 &&
14320 isAllOnes(N1.getOperand(1)))
14321 return DAG.getNode(X86ISD::BLSMSK, DL, VT, N0);
14326 /// PerformLOADCombine - Do target-specific dag combines on LOAD nodes.
14327 static SDValue PerformLOADCombine(SDNode *N, SelectionDAG &DAG,
14328 const X86Subtarget *Subtarget) {
14329 LoadSDNode *Ld = cast<LoadSDNode>(N);
14330 EVT RegVT = Ld->getValueType(0);
14331 EVT MemVT = Ld->getMemoryVT();
14332 DebugLoc dl = Ld->getDebugLoc();
14333 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
14335 ISD::LoadExtType Ext = Ld->getExtensionType();
14337 // If this is a vector EXT Load then attempt to optimize it using a
14338 // shuffle. We need SSE4 for the shuffles.
14339 // TODO: It is possible to support ZExt by zeroing the undef values
14340 // during the shuffle phase or after the shuffle.
14341 if (RegVT.isVector() && RegVT.isInteger() &&
14342 Ext == ISD::EXTLOAD && Subtarget->hasSSE41()) {
14343 assert(MemVT != RegVT && "Cannot extend to the same type");
14344 assert(MemVT.isVector() && "Must load a vector from memory");
14346 unsigned NumElems = RegVT.getVectorNumElements();
14347 unsigned RegSz = RegVT.getSizeInBits();
14348 unsigned MemSz = MemVT.getSizeInBits();
14349 assert(RegSz > MemSz && "Register size must be greater than the mem size");
14350 // All sizes must be a power of two
14351 if (!isPowerOf2_32(RegSz * MemSz * NumElems)) return SDValue();
14353 // Attempt to load the original value using a single load op.
14354 // Find a scalar type which is equal to the loaded word size.
14355 MVT SclrLoadTy = MVT::i8;
14356 for (unsigned tp = MVT::FIRST_INTEGER_VALUETYPE;
14357 tp < MVT::LAST_INTEGER_VALUETYPE; ++tp) {
14358 MVT Tp = (MVT::SimpleValueType)tp;
14359 if (TLI.isTypeLegal(Tp) && Tp.getSizeInBits() == MemSz) {
14365 // Proceed if a load word is found.
14366 if (SclrLoadTy.getSizeInBits() != MemSz) return SDValue();
14368 EVT LoadUnitVecVT = EVT::getVectorVT(*DAG.getContext(), SclrLoadTy,
14369 RegSz/SclrLoadTy.getSizeInBits());
14371 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(), MemVT.getScalarType(),
14372 RegSz/MemVT.getScalarType().getSizeInBits());
14373 // Can't shuffle using an illegal type.
14374 if (!TLI.isTypeLegal(WideVecVT)) return SDValue();
14376 // Perform a single load.
14377 SDValue ScalarLoad = DAG.getLoad(SclrLoadTy, dl, Ld->getChain(),
14379 Ld->getPointerInfo(), Ld->isVolatile(),
14380 Ld->isNonTemporal(), Ld->isInvariant(),
14381 Ld->getAlignment());
14383 // Insert the word loaded into a vector.
14384 SDValue ScalarInVector = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
14385 LoadUnitVecVT, ScalarLoad);
14387 // Bitcast the loaded value to a vector of the original element type, in
14388 // the size of the target vector type.
14389 SDValue SlicedVec = DAG.getNode(ISD::BITCAST, dl, WideVecVT,
14391 unsigned SizeRatio = RegSz/MemSz;
14393 // Redistribute the loaded elements into the different locations.
14394 SmallVector<int, 8> ShuffleVec(NumElems * SizeRatio, -1);
14395 for (unsigned i = 0; i < NumElems; i++) ShuffleVec[i*SizeRatio] = i;
14397 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, SlicedVec,
14398 DAG.getUNDEF(WideVecVT),
14401 // Bitcast to the requested type.
14402 Shuff = DAG.getNode(ISD::BITCAST, dl, RegVT, Shuff);
14403 // Replace the original load with the new sequence
14404 // and return the new chain.
14405 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Shuff);
14406 return SDValue(ScalarLoad.getNode(), 1);
14412 /// PerformSTORECombine - Do target-specific dag combines on STORE nodes.
14413 static SDValue PerformSTORECombine(SDNode *N, SelectionDAG &DAG,
14414 const X86Subtarget *Subtarget) {
14415 StoreSDNode *St = cast<StoreSDNode>(N);
14416 EVT VT = St->getValue().getValueType();
14417 EVT StVT = St->getMemoryVT();
14418 DebugLoc dl = St->getDebugLoc();
14419 SDValue StoredVal = St->getOperand(1);
14420 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
14422 // If we are saving a concatenation of two XMM registers, perform two stores.
14423 // This is better in Sandy Bridge cause one 256-bit mem op is done via two
14424 // 128-bit ones. If in the future the cost becomes only one memory access the
14425 // first version would be better.
14426 if (VT.getSizeInBits() == 256 &&
14427 StoredVal.getNode()->getOpcode() == ISD::CONCAT_VECTORS &&
14428 StoredVal.getNumOperands() == 2) {
14430 SDValue Value0 = StoredVal.getOperand(0);
14431 SDValue Value1 = StoredVal.getOperand(1);
14433 SDValue Stride = DAG.getConstant(16, TLI.getPointerTy());
14434 SDValue Ptr0 = St->getBasePtr();
14435 SDValue Ptr1 = DAG.getNode(ISD::ADD, dl, Ptr0.getValueType(), Ptr0, Stride);
14437 SDValue Ch0 = DAG.getStore(St->getChain(), dl, Value0, Ptr0,
14438 St->getPointerInfo(), St->isVolatile(),
14439 St->isNonTemporal(), St->getAlignment());
14440 SDValue Ch1 = DAG.getStore(St->getChain(), dl, Value1, Ptr1,
14441 St->getPointerInfo(), St->isVolatile(),
14442 St->isNonTemporal(), St->getAlignment());
14443 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Ch0, Ch1);
14446 // Optimize trunc store (of multiple scalars) to shuffle and store.
14447 // First, pack all of the elements in one place. Next, store to memory
14448 // in fewer chunks.
14449 if (St->isTruncatingStore() && VT.isVector()) {
14450 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
14451 unsigned NumElems = VT.getVectorNumElements();
14452 assert(StVT != VT && "Cannot truncate to the same type");
14453 unsigned FromSz = VT.getVectorElementType().getSizeInBits();
14454 unsigned ToSz = StVT.getVectorElementType().getSizeInBits();
14456 // From, To sizes and ElemCount must be pow of two
14457 if (!isPowerOf2_32(NumElems * FromSz * ToSz)) return SDValue();
14458 // We are going to use the original vector elt for storing.
14459 // Accumulated smaller vector elements must be a multiple of the store size.
14460 if (0 != (NumElems * FromSz) % ToSz) return SDValue();
14462 unsigned SizeRatio = FromSz / ToSz;
14464 assert(SizeRatio * NumElems * ToSz == VT.getSizeInBits());
14466 // Create a type on which we perform the shuffle
14467 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(),
14468 StVT.getScalarType(), NumElems*SizeRatio);
14470 assert(WideVecVT.getSizeInBits() == VT.getSizeInBits());
14472 SDValue WideVec = DAG.getNode(ISD::BITCAST, dl, WideVecVT, St->getValue());
14473 SmallVector<int, 8> ShuffleVec(NumElems * SizeRatio, -1);
14474 for (unsigned i = 0; i < NumElems; i++ ) ShuffleVec[i] = i * SizeRatio;
14476 // Can't shuffle using an illegal type
14477 if (!TLI.isTypeLegal(WideVecVT)) return SDValue();
14479 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, WideVec,
14480 DAG.getUNDEF(WideVecVT),
14482 // At this point all of the data is stored at the bottom of the
14483 // register. We now need to save it to mem.
14485 // Find the largest store unit
14486 MVT StoreType = MVT::i8;
14487 for (unsigned tp = MVT::FIRST_INTEGER_VALUETYPE;
14488 tp < MVT::LAST_INTEGER_VALUETYPE; ++tp) {
14489 MVT Tp = (MVT::SimpleValueType)tp;
14490 if (TLI.isTypeLegal(Tp) && StoreType.getSizeInBits() < NumElems * ToSz)
14494 // Bitcast the original vector into a vector of store-size units
14495 EVT StoreVecVT = EVT::getVectorVT(*DAG.getContext(),
14496 StoreType, VT.getSizeInBits()/EVT(StoreType).getSizeInBits());
14497 assert(StoreVecVT.getSizeInBits() == VT.getSizeInBits());
14498 SDValue ShuffWide = DAG.getNode(ISD::BITCAST, dl, StoreVecVT, Shuff);
14499 SmallVector<SDValue, 8> Chains;
14500 SDValue Increment = DAG.getConstant(StoreType.getSizeInBits()/8,
14501 TLI.getPointerTy());
14502 SDValue Ptr = St->getBasePtr();
14504 // Perform one or more big stores into memory.
14505 for (unsigned i = 0; i < (ToSz*NumElems)/StoreType.getSizeInBits() ; i++) {
14506 SDValue SubVec = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
14507 StoreType, ShuffWide,
14508 DAG.getIntPtrConstant(i));
14509 SDValue Ch = DAG.getStore(St->getChain(), dl, SubVec, Ptr,
14510 St->getPointerInfo(), St->isVolatile(),
14511 St->isNonTemporal(), St->getAlignment());
14512 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
14513 Chains.push_back(Ch);
14516 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Chains[0],
14521 // Turn load->store of MMX types into GPR load/stores. This avoids clobbering
14522 // the FP state in cases where an emms may be missing.
14523 // A preferable solution to the general problem is to figure out the right
14524 // places to insert EMMS. This qualifies as a quick hack.
14526 // Similarly, turn load->store of i64 into double load/stores in 32-bit mode.
14527 if (VT.getSizeInBits() != 64)
14530 const Function *F = DAG.getMachineFunction().getFunction();
14531 bool NoImplicitFloatOps = F->hasFnAttr(Attribute::NoImplicitFloat);
14532 bool F64IsLegal = !DAG.getTarget().Options.UseSoftFloat && !NoImplicitFloatOps
14533 && Subtarget->hasSSE2();
14534 if ((VT.isVector() ||
14535 (VT == MVT::i64 && F64IsLegal && !Subtarget->is64Bit())) &&
14536 isa<LoadSDNode>(St->getValue()) &&
14537 !cast<LoadSDNode>(St->getValue())->isVolatile() &&
14538 St->getChain().hasOneUse() && !St->isVolatile()) {
14539 SDNode* LdVal = St->getValue().getNode();
14540 LoadSDNode *Ld = 0;
14541 int TokenFactorIndex = -1;
14542 SmallVector<SDValue, 8> Ops;
14543 SDNode* ChainVal = St->getChain().getNode();
14544 // Must be a store of a load. We currently handle two cases: the load
14545 // is a direct child, and it's under an intervening TokenFactor. It is
14546 // possible to dig deeper under nested TokenFactors.
14547 if (ChainVal == LdVal)
14548 Ld = cast<LoadSDNode>(St->getChain());
14549 else if (St->getValue().hasOneUse() &&
14550 ChainVal->getOpcode() == ISD::TokenFactor) {
14551 for (unsigned i = 0, e = ChainVal->getNumOperands(); i != e; ++i) {
14552 if (ChainVal->getOperand(i).getNode() == LdVal) {
14553 TokenFactorIndex = i;
14554 Ld = cast<LoadSDNode>(St->getValue());
14556 Ops.push_back(ChainVal->getOperand(i));
14560 if (!Ld || !ISD::isNormalLoad(Ld))
14563 // If this is not the MMX case, i.e. we are just turning i64 load/store
14564 // into f64 load/store, avoid the transformation if there are multiple
14565 // uses of the loaded value.
14566 if (!VT.isVector() && !Ld->hasNUsesOfValue(1, 0))
14569 DebugLoc LdDL = Ld->getDebugLoc();
14570 DebugLoc StDL = N->getDebugLoc();
14571 // If we are a 64-bit capable x86, lower to a single movq load/store pair.
14572 // Otherwise, if it's legal to use f64 SSE instructions, use f64 load/store
14574 if (Subtarget->is64Bit() || F64IsLegal) {
14575 EVT LdVT = Subtarget->is64Bit() ? MVT::i64 : MVT::f64;
14576 SDValue NewLd = DAG.getLoad(LdVT, LdDL, Ld->getChain(), Ld->getBasePtr(),
14577 Ld->getPointerInfo(), Ld->isVolatile(),
14578 Ld->isNonTemporal(), Ld->isInvariant(),
14579 Ld->getAlignment());
14580 SDValue NewChain = NewLd.getValue(1);
14581 if (TokenFactorIndex != -1) {
14582 Ops.push_back(NewChain);
14583 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, &Ops[0],
14586 return DAG.getStore(NewChain, StDL, NewLd, St->getBasePtr(),
14587 St->getPointerInfo(),
14588 St->isVolatile(), St->isNonTemporal(),
14589 St->getAlignment());
14592 // Otherwise, lower to two pairs of 32-bit loads / stores.
14593 SDValue LoAddr = Ld->getBasePtr();
14594 SDValue HiAddr = DAG.getNode(ISD::ADD, LdDL, MVT::i32, LoAddr,
14595 DAG.getConstant(4, MVT::i32));
14597 SDValue LoLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), LoAddr,
14598 Ld->getPointerInfo(),
14599 Ld->isVolatile(), Ld->isNonTemporal(),
14600 Ld->isInvariant(), Ld->getAlignment());
14601 SDValue HiLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), HiAddr,
14602 Ld->getPointerInfo().getWithOffset(4),
14603 Ld->isVolatile(), Ld->isNonTemporal(),
14605 MinAlign(Ld->getAlignment(), 4));
14607 SDValue NewChain = LoLd.getValue(1);
14608 if (TokenFactorIndex != -1) {
14609 Ops.push_back(LoLd);
14610 Ops.push_back(HiLd);
14611 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, &Ops[0],
14615 LoAddr = St->getBasePtr();
14616 HiAddr = DAG.getNode(ISD::ADD, StDL, MVT::i32, LoAddr,
14617 DAG.getConstant(4, MVT::i32));
14619 SDValue LoSt = DAG.getStore(NewChain, StDL, LoLd, LoAddr,
14620 St->getPointerInfo(),
14621 St->isVolatile(), St->isNonTemporal(),
14622 St->getAlignment());
14623 SDValue HiSt = DAG.getStore(NewChain, StDL, HiLd, HiAddr,
14624 St->getPointerInfo().getWithOffset(4),
14626 St->isNonTemporal(),
14627 MinAlign(St->getAlignment(), 4));
14628 return DAG.getNode(ISD::TokenFactor, StDL, MVT::Other, LoSt, HiSt);
14633 /// isHorizontalBinOp - Return 'true' if this vector operation is "horizontal"
14634 /// and return the operands for the horizontal operation in LHS and RHS. A
14635 /// horizontal operation performs the binary operation on successive elements
14636 /// of its first operand, then on successive elements of its second operand,
14637 /// returning the resulting values in a vector. For example, if
14638 /// A = < float a0, float a1, float a2, float a3 >
14640 /// B = < float b0, float b1, float b2, float b3 >
14641 /// then the result of doing a horizontal operation on A and B is
14642 /// A horizontal-op B = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >.
14643 /// In short, LHS and RHS are inspected to see if LHS op RHS is of the form
14644 /// A horizontal-op B, for some already available A and B, and if so then LHS is
14645 /// set to A, RHS to B, and the routine returns 'true'.
14646 /// Note that the binary operation should have the property that if one of the
14647 /// operands is UNDEF then the result is UNDEF.
14648 static bool isHorizontalBinOp(SDValue &LHS, SDValue &RHS, bool IsCommutative) {
14649 // Look for the following pattern: if
14650 // A = < float a0, float a1, float a2, float a3 >
14651 // B = < float b0, float b1, float b2, float b3 >
14653 // LHS = VECTOR_SHUFFLE A, B, <0, 2, 4, 6>
14654 // RHS = VECTOR_SHUFFLE A, B, <1, 3, 5, 7>
14655 // then LHS op RHS = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >
14656 // which is A horizontal-op B.
14658 // At least one of the operands should be a vector shuffle.
14659 if (LHS.getOpcode() != ISD::VECTOR_SHUFFLE &&
14660 RHS.getOpcode() != ISD::VECTOR_SHUFFLE)
14663 EVT VT = LHS.getValueType();
14665 assert((VT.is128BitVector() || VT.is256BitVector()) &&
14666 "Unsupported vector type for horizontal add/sub");
14668 // Handle 128 and 256-bit vector lengths. AVX defines horizontal add/sub to
14669 // operate independently on 128-bit lanes.
14670 unsigned NumElts = VT.getVectorNumElements();
14671 unsigned NumLanes = VT.getSizeInBits()/128;
14672 unsigned NumLaneElts = NumElts / NumLanes;
14673 assert((NumLaneElts % 2 == 0) &&
14674 "Vector type should have an even number of elements in each lane");
14675 unsigned HalfLaneElts = NumLaneElts/2;
14677 // View LHS in the form
14678 // LHS = VECTOR_SHUFFLE A, B, LMask
14679 // If LHS is not a shuffle then pretend it is the shuffle
14680 // LHS = VECTOR_SHUFFLE LHS, undef, <0, 1, ..., N-1>
14681 // NOTE: in what follows a default initialized SDValue represents an UNDEF of
14684 SmallVector<int, 16> LMask(NumElts);
14685 if (LHS.getOpcode() == ISD::VECTOR_SHUFFLE) {
14686 if (LHS.getOperand(0).getOpcode() != ISD::UNDEF)
14687 A = LHS.getOperand(0);
14688 if (LHS.getOperand(1).getOpcode() != ISD::UNDEF)
14689 B = LHS.getOperand(1);
14690 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(LHS.getNode())->getMask();
14691 std::copy(Mask.begin(), Mask.end(), LMask.begin());
14693 if (LHS.getOpcode() != ISD::UNDEF)
14695 for (unsigned i = 0; i != NumElts; ++i)
14699 // Likewise, view RHS in the form
14700 // RHS = VECTOR_SHUFFLE C, D, RMask
14702 SmallVector<int, 16> RMask(NumElts);
14703 if (RHS.getOpcode() == ISD::VECTOR_SHUFFLE) {
14704 if (RHS.getOperand(0).getOpcode() != ISD::UNDEF)
14705 C = RHS.getOperand(0);
14706 if (RHS.getOperand(1).getOpcode() != ISD::UNDEF)
14707 D = RHS.getOperand(1);
14708 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(RHS.getNode())->getMask();
14709 std::copy(Mask.begin(), Mask.end(), RMask.begin());
14711 if (RHS.getOpcode() != ISD::UNDEF)
14713 for (unsigned i = 0; i != NumElts; ++i)
14717 // Check that the shuffles are both shuffling the same vectors.
14718 if (!(A == C && B == D) && !(A == D && B == C))
14721 // If everything is UNDEF then bail out: it would be better to fold to UNDEF.
14722 if (!A.getNode() && !B.getNode())
14725 // If A and B occur in reverse order in RHS, then "swap" them (which means
14726 // rewriting the mask).
14728 CommuteVectorShuffleMask(RMask, NumElts);
14730 // At this point LHS and RHS are equivalent to
14731 // LHS = VECTOR_SHUFFLE A, B, LMask
14732 // RHS = VECTOR_SHUFFLE A, B, RMask
14733 // Check that the masks correspond to performing a horizontal operation.
14734 for (unsigned i = 0; i != NumElts; ++i) {
14735 int LIdx = LMask[i], RIdx = RMask[i];
14737 // Ignore any UNDEF components.
14738 if (LIdx < 0 || RIdx < 0 ||
14739 (!A.getNode() && (LIdx < (int)NumElts || RIdx < (int)NumElts)) ||
14740 (!B.getNode() && (LIdx >= (int)NumElts || RIdx >= (int)NumElts)))
14743 // Check that successive elements are being operated on. If not, this is
14744 // not a horizontal operation.
14745 unsigned Src = (i/HalfLaneElts) % 2; // each lane is split between srcs
14746 unsigned LaneStart = (i/NumLaneElts) * NumLaneElts;
14747 int Index = 2*(i%HalfLaneElts) + NumElts*Src + LaneStart;
14748 if (!(LIdx == Index && RIdx == Index + 1) &&
14749 !(IsCommutative && LIdx == Index + 1 && RIdx == Index))
14753 LHS = A.getNode() ? A : B; // If A is 'UNDEF', use B for it.
14754 RHS = B.getNode() ? B : A; // If B is 'UNDEF', use A for it.
14758 /// PerformFADDCombine - Do target-specific dag combines on floating point adds.
14759 static SDValue PerformFADDCombine(SDNode *N, SelectionDAG &DAG,
14760 const X86Subtarget *Subtarget) {
14761 EVT VT = N->getValueType(0);
14762 SDValue LHS = N->getOperand(0);
14763 SDValue RHS = N->getOperand(1);
14765 // Try to synthesize horizontal adds from adds of shuffles.
14766 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
14767 (Subtarget->hasAVX() && (VT == MVT::v8f32 || VT == MVT::v4f64))) &&
14768 isHorizontalBinOp(LHS, RHS, true))
14769 return DAG.getNode(X86ISD::FHADD, N->getDebugLoc(), VT, LHS, RHS);
14773 /// PerformFSUBCombine - Do target-specific dag combines on floating point subs.
14774 static SDValue PerformFSUBCombine(SDNode *N, SelectionDAG &DAG,
14775 const X86Subtarget *Subtarget) {
14776 EVT VT = N->getValueType(0);
14777 SDValue LHS = N->getOperand(0);
14778 SDValue RHS = N->getOperand(1);
14780 // Try to synthesize horizontal subs from subs of shuffles.
14781 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
14782 (Subtarget->hasAVX() && (VT == MVT::v8f32 || VT == MVT::v4f64))) &&
14783 isHorizontalBinOp(LHS, RHS, false))
14784 return DAG.getNode(X86ISD::FHSUB, N->getDebugLoc(), VT, LHS, RHS);
14788 /// PerformFORCombine - Do target-specific dag combines on X86ISD::FOR and
14789 /// X86ISD::FXOR nodes.
14790 static SDValue PerformFORCombine(SDNode *N, SelectionDAG &DAG) {
14791 assert(N->getOpcode() == X86ISD::FOR || N->getOpcode() == X86ISD::FXOR);
14792 // F[X]OR(0.0, x) -> x
14793 // F[X]OR(x, 0.0) -> x
14794 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
14795 if (C->getValueAPF().isPosZero())
14796 return N->getOperand(1);
14797 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
14798 if (C->getValueAPF().isPosZero())
14799 return N->getOperand(0);
14803 /// PerformFANDCombine - Do target-specific dag combines on X86ISD::FAND nodes.
14804 static SDValue PerformFANDCombine(SDNode *N, SelectionDAG &DAG) {
14805 // FAND(0.0, x) -> 0.0
14806 // FAND(x, 0.0) -> 0.0
14807 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
14808 if (C->getValueAPF().isPosZero())
14809 return N->getOperand(0);
14810 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
14811 if (C->getValueAPF().isPosZero())
14812 return N->getOperand(1);
14816 static SDValue PerformBTCombine(SDNode *N,
14818 TargetLowering::DAGCombinerInfo &DCI) {
14819 // BT ignores high bits in the bit index operand.
14820 SDValue Op1 = N->getOperand(1);
14821 if (Op1.hasOneUse()) {
14822 unsigned BitWidth = Op1.getValueSizeInBits();
14823 APInt DemandedMask = APInt::getLowBitsSet(BitWidth, Log2_32(BitWidth));
14824 APInt KnownZero, KnownOne;
14825 TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(),
14826 !DCI.isBeforeLegalizeOps());
14827 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
14828 if (TLO.ShrinkDemandedConstant(Op1, DemandedMask) ||
14829 TLI.SimplifyDemandedBits(Op1, DemandedMask, KnownZero, KnownOne, TLO))
14830 DCI.CommitTargetLoweringOpt(TLO);
14835 static SDValue PerformVZEXT_MOVLCombine(SDNode *N, SelectionDAG &DAG) {
14836 SDValue Op = N->getOperand(0);
14837 if (Op.getOpcode() == ISD::BITCAST)
14838 Op = Op.getOperand(0);
14839 EVT VT = N->getValueType(0), OpVT = Op.getValueType();
14840 if (Op.getOpcode() == X86ISD::VZEXT_LOAD &&
14841 VT.getVectorElementType().getSizeInBits() ==
14842 OpVT.getVectorElementType().getSizeInBits()) {
14843 return DAG.getNode(ISD::BITCAST, N->getDebugLoc(), VT, Op);
14848 static SDValue PerformSExtCombine(SDNode *N, SelectionDAG &DAG,
14849 TargetLowering::DAGCombinerInfo &DCI,
14850 const X86Subtarget *Subtarget) {
14851 if (!DCI.isBeforeLegalizeOps())
14854 if (!Subtarget->hasAVX())
14857 EVT VT = N->getValueType(0);
14858 SDValue Op = N->getOperand(0);
14859 EVT OpVT = Op.getValueType();
14860 DebugLoc dl = N->getDebugLoc();
14862 if ((VT == MVT::v4i64 && OpVT == MVT::v4i32) ||
14863 (VT == MVT::v8i32 && OpVT == MVT::v8i16)) {
14865 if (Subtarget->hasAVX2())
14866 return DAG.getNode(X86ISD::VSEXT_MOVL, dl, VT, Op);
14868 // Optimize vectors in AVX mode
14869 // Sign extend v8i16 to v8i32 and
14872 // Divide input vector into two parts
14873 // for v4i32 the shuffle mask will be { 0, 1, -1, -1} {2, 3, -1, -1}
14874 // use vpmovsx instruction to extend v4i32 -> v2i64; v8i16 -> v4i32
14875 // concat the vectors to original VT
14877 unsigned NumElems = OpVT.getVectorNumElements();
14878 SmallVector<int,8> ShufMask1(NumElems, -1);
14879 for (unsigned i = 0; i != NumElems/2; ++i)
14882 SDValue OpLo = DAG.getVectorShuffle(OpVT, dl, Op, DAG.getUNDEF(OpVT),
14885 SmallVector<int,8> ShufMask2(NumElems, -1);
14886 for (unsigned i = 0; i != NumElems/2; ++i)
14887 ShufMask2[i] = i + NumElems/2;
14889 SDValue OpHi = DAG.getVectorShuffle(OpVT, dl, Op, DAG.getUNDEF(OpVT),
14892 EVT HalfVT = EVT::getVectorVT(*DAG.getContext(), VT.getScalarType(),
14893 VT.getVectorNumElements()/2);
14895 OpLo = DAG.getNode(X86ISD::VSEXT_MOVL, dl, HalfVT, OpLo);
14896 OpHi = DAG.getNode(X86ISD::VSEXT_MOVL, dl, HalfVT, OpHi);
14898 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi);
14903 static SDValue PerformZExtCombine(SDNode *N, SelectionDAG &DAG,
14904 const X86Subtarget *Subtarget) {
14905 // (i32 zext (and (i8 x86isd::setcc_carry), 1)) ->
14906 // (and (i32 x86isd::setcc_carry), 1)
14907 // This eliminates the zext. This transformation is necessary because
14908 // ISD::SETCC is always legalized to i8.
14909 DebugLoc dl = N->getDebugLoc();
14910 SDValue N0 = N->getOperand(0);
14911 EVT VT = N->getValueType(0);
14912 EVT OpVT = N0.getValueType();
14914 if (N0.getOpcode() == ISD::AND &&
14916 N0.getOperand(0).hasOneUse()) {
14917 SDValue N00 = N0.getOperand(0);
14918 if (N00.getOpcode() != X86ISD::SETCC_CARRY)
14920 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
14921 if (!C || C->getZExtValue() != 1)
14923 return DAG.getNode(ISD::AND, dl, VT,
14924 DAG.getNode(X86ISD::SETCC_CARRY, dl, VT,
14925 N00.getOperand(0), N00.getOperand(1)),
14926 DAG.getConstant(1, VT));
14929 // Optimize vectors in AVX mode:
14932 // Use vpunpcklwd for 4 lower elements v8i16 -> v4i32.
14933 // Use vpunpckhwd for 4 upper elements v8i16 -> v4i32.
14934 // Concat upper and lower parts.
14937 // Use vpunpckldq for 4 lower elements v4i32 -> v2i64.
14938 // Use vpunpckhdq for 4 upper elements v4i32 -> v2i64.
14939 // Concat upper and lower parts.
14941 if (Subtarget->hasAVX()) {
14943 if (((VT == MVT::v8i32) && (OpVT == MVT::v8i16)) ||
14944 ((VT == MVT::v4i64) && (OpVT == MVT::v4i32))) {
14946 if (Subtarget->hasAVX2())
14947 return DAG.getNode(X86ISD::VZEXT_MOVL, dl, VT, N0);
14949 SDValue ZeroVec = getZeroVector(OpVT, Subtarget, DAG, dl);
14950 SDValue OpLo = getTargetShuffleNode(X86ISD::UNPCKL, dl, OpVT, N0, ZeroVec,
14952 SDValue OpHi = getTargetShuffleNode(X86ISD::UNPCKH, dl, OpVT, N0, ZeroVec,
14955 EVT HVT = EVT::getVectorVT(*DAG.getContext(), VT.getVectorElementType(),
14956 VT.getVectorNumElements()/2);
14958 OpLo = DAG.getNode(ISD::BITCAST, dl, HVT, OpLo);
14959 OpHi = DAG.getNode(ISD::BITCAST, dl, HVT, OpHi);
14961 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi);
14968 // Optimize RES = X86ISD::SETCC CONDCODE, EFLAG_INPUT
14969 static SDValue PerformSETCCCombine(SDNode *N, SelectionDAG &DAG) {
14970 unsigned X86CC = N->getConstantOperandVal(0);
14971 SDValue EFLAG = N->getOperand(1);
14972 DebugLoc DL = N->getDebugLoc();
14974 // Materialize "setb reg" as "sbb reg,reg", since it can be extended without
14975 // a zext and produces an all-ones bit which is more useful than 0/1 in some
14977 if (X86CC == X86::COND_B)
14978 return DAG.getNode(ISD::AND, DL, MVT::i8,
14979 DAG.getNode(X86ISD::SETCC_CARRY, DL, MVT::i8,
14980 DAG.getConstant(X86CC, MVT::i8), EFLAG),
14981 DAG.getConstant(1, MVT::i8));
14986 static SDValue PerformUINT_TO_FPCombine(SDNode *N, SelectionDAG &DAG) {
14987 SDValue Op0 = N->getOperand(0);
14988 EVT InVT = Op0->getValueType(0);
14990 // UINT_TO_FP(v4i8) -> SINT_TO_FP(ZEXT(v4i8 to v4i32))
14991 if (InVT == MVT::v8i8 || InVT == MVT::v4i8) {
14992 DebugLoc dl = N->getDebugLoc();
14993 MVT DstVT = InVT == MVT::v4i8 ? MVT::v4i32 : MVT::v8i32;
14994 SDValue P = DAG.getNode(ISD::ZERO_EXTEND, dl, DstVT, Op0);
14995 // Notice that we use SINT_TO_FP because we know that the high bits
14996 // are zero and SINT_TO_FP is better supported by the hardware.
14997 return DAG.getNode(ISD::SINT_TO_FP, dl, N->getValueType(0), P);
15003 static SDValue PerformSINT_TO_FPCombine(SDNode *N, SelectionDAG &DAG,
15004 const X86TargetLowering *XTLI) {
15005 SDValue Op0 = N->getOperand(0);
15006 EVT InVT = Op0->getValueType(0);
15008 // SINT_TO_FP(v4i8) -> SINT_TO_FP(SEXT(v4i8 to v4i32))
15009 if (InVT == MVT::v8i8 || InVT == MVT::v4i8) {
15010 DebugLoc dl = N->getDebugLoc();
15011 MVT DstVT = InVT == MVT::v4i8 ? MVT::v4i32 : MVT::v8i32;
15012 SDValue P = DAG.getNode(ISD::SIGN_EXTEND, dl, DstVT, Op0);
15013 return DAG.getNode(ISD::SINT_TO_FP, dl, N->getValueType(0), P);
15016 // Transform (SINT_TO_FP (i64 ...)) into an x87 operation if we have
15017 // a 32-bit target where SSE doesn't support i64->FP operations.
15018 if (Op0.getOpcode() == ISD::LOAD) {
15019 LoadSDNode *Ld = cast<LoadSDNode>(Op0.getNode());
15020 EVT VT = Ld->getValueType(0);
15021 if (!Ld->isVolatile() && !N->getValueType(0).isVector() &&
15022 ISD::isNON_EXTLoad(Op0.getNode()) && Op0.hasOneUse() &&
15023 !XTLI->getSubtarget()->is64Bit() &&
15024 !DAG.getTargetLoweringInfo().isTypeLegal(VT)) {
15025 SDValue FILDChain = XTLI->BuildFILD(SDValue(N, 0), Ld->getValueType(0),
15026 Ld->getChain(), Op0, DAG);
15027 DAG.ReplaceAllUsesOfValueWith(Op0.getValue(1), FILDChain.getValue(1));
15034 static SDValue PerformFP_TO_SINTCombine(SDNode *N, SelectionDAG &DAG) {
15035 EVT VT = N->getValueType(0);
15037 // v4i8 = FP_TO_SINT() -> v4i8 = TRUNCATE (V4i32 = FP_TO_SINT()
15038 if (VT == MVT::v8i8 || VT == MVT::v4i8) {
15039 DebugLoc dl = N->getDebugLoc();
15040 MVT DstVT = VT == MVT::v4i8 ? MVT::v4i32 : MVT::v8i32;
15041 SDValue I = DAG.getNode(ISD::FP_TO_SINT, dl, DstVT, N->getOperand(0));
15042 return DAG.getNode(ISD::TRUNCATE, dl, VT, I);
15048 // Optimize RES, EFLAGS = X86ISD::ADC LHS, RHS, EFLAGS
15049 static SDValue PerformADCCombine(SDNode *N, SelectionDAG &DAG,
15050 X86TargetLowering::DAGCombinerInfo &DCI) {
15051 // If the LHS and RHS of the ADC node are zero, then it can't overflow and
15052 // the result is either zero or one (depending on the input carry bit).
15053 // Strength reduce this down to a "set on carry" aka SETCC_CARRY&1.
15054 if (X86::isZeroNode(N->getOperand(0)) &&
15055 X86::isZeroNode(N->getOperand(1)) &&
15056 // We don't have a good way to replace an EFLAGS use, so only do this when
15058 SDValue(N, 1).use_empty()) {
15059 DebugLoc DL = N->getDebugLoc();
15060 EVT VT = N->getValueType(0);
15061 SDValue CarryOut = DAG.getConstant(0, N->getValueType(1));
15062 SDValue Res1 = DAG.getNode(ISD::AND, DL, VT,
15063 DAG.getNode(X86ISD::SETCC_CARRY, DL, VT,
15064 DAG.getConstant(X86::COND_B,MVT::i8),
15066 DAG.getConstant(1, VT));
15067 return DCI.CombineTo(N, Res1, CarryOut);
15073 // fold (add Y, (sete X, 0)) -> adc 0, Y
15074 // (add Y, (setne X, 0)) -> sbb -1, Y
15075 // (sub (sete X, 0), Y) -> sbb 0, Y
15076 // (sub (setne X, 0), Y) -> adc -1, Y
15077 static SDValue OptimizeConditionalInDecrement(SDNode *N, SelectionDAG &DAG) {
15078 DebugLoc DL = N->getDebugLoc();
15080 // Look through ZExts.
15081 SDValue Ext = N->getOperand(N->getOpcode() == ISD::SUB ? 1 : 0);
15082 if (Ext.getOpcode() != ISD::ZERO_EXTEND || !Ext.hasOneUse())
15085 SDValue SetCC = Ext.getOperand(0);
15086 if (SetCC.getOpcode() != X86ISD::SETCC || !SetCC.hasOneUse())
15089 X86::CondCode CC = (X86::CondCode)SetCC.getConstantOperandVal(0);
15090 if (CC != X86::COND_E && CC != X86::COND_NE)
15093 SDValue Cmp = SetCC.getOperand(1);
15094 if (Cmp.getOpcode() != X86ISD::CMP || !Cmp.hasOneUse() ||
15095 !X86::isZeroNode(Cmp.getOperand(1)) ||
15096 !Cmp.getOperand(0).getValueType().isInteger())
15099 SDValue CmpOp0 = Cmp.getOperand(0);
15100 SDValue NewCmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32, CmpOp0,
15101 DAG.getConstant(1, CmpOp0.getValueType()));
15103 SDValue OtherVal = N->getOperand(N->getOpcode() == ISD::SUB ? 0 : 1);
15104 if (CC == X86::COND_NE)
15105 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::ADC : X86ISD::SBB,
15106 DL, OtherVal.getValueType(), OtherVal,
15107 DAG.getConstant(-1ULL, OtherVal.getValueType()), NewCmp);
15108 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::SBB : X86ISD::ADC,
15109 DL, OtherVal.getValueType(), OtherVal,
15110 DAG.getConstant(0, OtherVal.getValueType()), NewCmp);
15113 /// PerformADDCombine - Do target-specific dag combines on integer adds.
15114 static SDValue PerformAddCombine(SDNode *N, SelectionDAG &DAG,
15115 const X86Subtarget *Subtarget) {
15116 EVT VT = N->getValueType(0);
15117 SDValue Op0 = N->getOperand(0);
15118 SDValue Op1 = N->getOperand(1);
15120 // Try to synthesize horizontal adds from adds of shuffles.
15121 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) ||
15122 (Subtarget->hasAVX2() && (VT == MVT::v16i16 || VT == MVT::v8i32))) &&
15123 isHorizontalBinOp(Op0, Op1, true))
15124 return DAG.getNode(X86ISD::HADD, N->getDebugLoc(), VT, Op0, Op1);
15126 return OptimizeConditionalInDecrement(N, DAG);
15129 static SDValue PerformSubCombine(SDNode *N, SelectionDAG &DAG,
15130 const X86Subtarget *Subtarget) {
15131 SDValue Op0 = N->getOperand(0);
15132 SDValue Op1 = N->getOperand(1);
15134 // X86 can't encode an immediate LHS of a sub. See if we can push the
15135 // negation into a preceding instruction.
15136 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op0)) {
15137 // If the RHS of the sub is a XOR with one use and a constant, invert the
15138 // immediate. Then add one to the LHS of the sub so we can turn
15139 // X-Y -> X+~Y+1, saving one register.
15140 if (Op1->hasOneUse() && Op1.getOpcode() == ISD::XOR &&
15141 isa<ConstantSDNode>(Op1.getOperand(1))) {
15142 APInt XorC = cast<ConstantSDNode>(Op1.getOperand(1))->getAPIntValue();
15143 EVT VT = Op0.getValueType();
15144 SDValue NewXor = DAG.getNode(ISD::XOR, Op1.getDebugLoc(), VT,
15146 DAG.getConstant(~XorC, VT));
15147 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, NewXor,
15148 DAG.getConstant(C->getAPIntValue()+1, VT));
15152 // Try to synthesize horizontal adds from adds of shuffles.
15153 EVT VT = N->getValueType(0);
15154 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) ||
15155 (Subtarget->hasAVX2() && (VT == MVT::v16i16 || VT == MVT::v8i32))) &&
15156 isHorizontalBinOp(Op0, Op1, true))
15157 return DAG.getNode(X86ISD::HSUB, N->getDebugLoc(), VT, Op0, Op1);
15159 return OptimizeConditionalInDecrement(N, DAG);
15162 SDValue X86TargetLowering::PerformDAGCombine(SDNode *N,
15163 DAGCombinerInfo &DCI) const {
15164 SelectionDAG &DAG = DCI.DAG;
15165 switch (N->getOpcode()) {
15167 case ISD::EXTRACT_VECTOR_ELT:
15168 return PerformEXTRACT_VECTOR_ELTCombine(N, DAG, DCI);
15170 case ISD::SELECT: return PerformSELECTCombine(N, DAG, DCI, Subtarget);
15171 case X86ISD::CMOV: return PerformCMOVCombine(N, DAG, DCI);
15172 case ISD::ADD: return PerformAddCombine(N, DAG, Subtarget);
15173 case ISD::SUB: return PerformSubCombine(N, DAG, Subtarget);
15174 case X86ISD::ADC: return PerformADCCombine(N, DAG, DCI);
15175 case ISD::MUL: return PerformMulCombine(N, DAG, DCI);
15178 case ISD::SRL: return PerformShiftCombine(N, DAG, DCI, Subtarget);
15179 case ISD::AND: return PerformAndCombine(N, DAG, DCI, Subtarget);
15180 case ISD::OR: return PerformOrCombine(N, DAG, DCI, Subtarget);
15181 case ISD::XOR: return PerformXorCombine(N, DAG, DCI, Subtarget);
15182 case ISD::LOAD: return PerformLOADCombine(N, DAG, Subtarget);
15183 case ISD::STORE: return PerformSTORECombine(N, DAG, Subtarget);
15184 case ISD::UINT_TO_FP: return PerformUINT_TO_FPCombine(N, DAG);
15185 case ISD::SINT_TO_FP: return PerformSINT_TO_FPCombine(N, DAG, this);
15186 case ISD::FP_TO_SINT: return PerformFP_TO_SINTCombine(N, DAG);
15187 case ISD::FADD: return PerformFADDCombine(N, DAG, Subtarget);
15188 case ISD::FSUB: return PerformFSUBCombine(N, DAG, Subtarget);
15190 case X86ISD::FOR: return PerformFORCombine(N, DAG);
15191 case X86ISD::FAND: return PerformFANDCombine(N, DAG);
15192 case X86ISD::BT: return PerformBTCombine(N, DAG, DCI);
15193 case X86ISD::VZEXT_MOVL: return PerformVZEXT_MOVLCombine(N, DAG);
15194 case ISD::ANY_EXTEND:
15195 case ISD::ZERO_EXTEND: return PerformZExtCombine(N, DAG, Subtarget);
15196 case ISD::SIGN_EXTEND: return PerformSExtCombine(N, DAG, DCI, Subtarget);
15197 case ISD::TRUNCATE: return PerformTruncateCombine(N, DAG, DCI);
15198 case X86ISD::SETCC: return PerformSETCCCombine(N, DAG);
15199 case X86ISD::SHUFP: // Handle all target specific shuffles
15200 case X86ISD::PALIGN:
15201 case X86ISD::UNPCKH:
15202 case X86ISD::UNPCKL:
15203 case X86ISD::MOVHLPS:
15204 case X86ISD::MOVLHPS:
15205 case X86ISD::PSHUFD:
15206 case X86ISD::PSHUFHW:
15207 case X86ISD::PSHUFLW:
15208 case X86ISD::MOVSS:
15209 case X86ISD::MOVSD:
15210 case X86ISD::VPERMILP:
15211 case X86ISD::VPERM2X128:
15212 case ISD::VECTOR_SHUFFLE: return PerformShuffleCombine(N, DAG, DCI,Subtarget);
15218 /// isTypeDesirableForOp - Return true if the target has native support for
15219 /// the specified value type and it is 'desirable' to use the type for the
15220 /// given node type. e.g. On x86 i16 is legal, but undesirable since i16
15221 /// instruction encodings are longer and some i16 instructions are slow.
15222 bool X86TargetLowering::isTypeDesirableForOp(unsigned Opc, EVT VT) const {
15223 if (!isTypeLegal(VT))
15225 if (VT != MVT::i16)
15232 case ISD::SIGN_EXTEND:
15233 case ISD::ZERO_EXTEND:
15234 case ISD::ANY_EXTEND:
15247 /// IsDesirableToPromoteOp - This method query the target whether it is
15248 /// beneficial for dag combiner to promote the specified node. If true, it
15249 /// should return the desired promotion type by reference.
15250 bool X86TargetLowering::IsDesirableToPromoteOp(SDValue Op, EVT &PVT) const {
15251 EVT VT = Op.getValueType();
15252 if (VT != MVT::i16)
15255 bool Promote = false;
15256 bool Commute = false;
15257 switch (Op.getOpcode()) {
15260 LoadSDNode *LD = cast<LoadSDNode>(Op);
15261 // If the non-extending load has a single use and it's not live out, then it
15262 // might be folded.
15263 if (LD->getExtensionType() == ISD::NON_EXTLOAD /*&&
15264 Op.hasOneUse()*/) {
15265 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
15266 UE = Op.getNode()->use_end(); UI != UE; ++UI) {
15267 // The only case where we'd want to promote LOAD (rather then it being
15268 // promoted as an operand is when it's only use is liveout.
15269 if (UI->getOpcode() != ISD::CopyToReg)
15276 case ISD::SIGN_EXTEND:
15277 case ISD::ZERO_EXTEND:
15278 case ISD::ANY_EXTEND:
15283 SDValue N0 = Op.getOperand(0);
15284 // Look out for (store (shl (load), x)).
15285 if (MayFoldLoad(N0) && MayFoldIntoStore(Op))
15298 SDValue N0 = Op.getOperand(0);
15299 SDValue N1 = Op.getOperand(1);
15300 if (!Commute && MayFoldLoad(N1))
15302 // Avoid disabling potential load folding opportunities.
15303 if (MayFoldLoad(N0) && (!isa<ConstantSDNode>(N1) || MayFoldIntoStore(Op)))
15305 if (MayFoldLoad(N1) && (!isa<ConstantSDNode>(N0) || MayFoldIntoStore(Op)))
15315 //===----------------------------------------------------------------------===//
15316 // X86 Inline Assembly Support
15317 //===----------------------------------------------------------------------===//
15320 // Helper to match a string separated by whitespace.
15321 bool matchAsmImpl(StringRef s, ArrayRef<const StringRef *> args) {
15322 s = s.substr(s.find_first_not_of(" \t")); // Skip leading whitespace.
15324 for (unsigned i = 0, e = args.size(); i != e; ++i) {
15325 StringRef piece(*args[i]);
15326 if (!s.startswith(piece)) // Check if the piece matches.
15329 s = s.substr(piece.size());
15330 StringRef::size_type pos = s.find_first_not_of(" \t");
15331 if (pos == 0) // We matched a prefix.
15339 const VariadicFunction1<bool, StringRef, StringRef, matchAsmImpl> matchAsm={};
15342 bool X86TargetLowering::ExpandInlineAsm(CallInst *CI) const {
15343 InlineAsm *IA = cast<InlineAsm>(CI->getCalledValue());
15345 std::string AsmStr = IA->getAsmString();
15347 IntegerType *Ty = dyn_cast<IntegerType>(CI->getType());
15348 if (!Ty || Ty->getBitWidth() % 16 != 0)
15351 // TODO: should remove alternatives from the asmstring: "foo {a|b}" -> "foo a"
15352 SmallVector<StringRef, 4> AsmPieces;
15353 SplitString(AsmStr, AsmPieces, ";\n");
15355 switch (AsmPieces.size()) {
15356 default: return false;
15358 // FIXME: this should verify that we are targeting a 486 or better. If not,
15359 // we will turn this bswap into something that will be lowered to logical
15360 // ops instead of emitting the bswap asm. For now, we don't support 486 or
15361 // lower so don't worry about this.
15363 if (matchAsm(AsmPieces[0], "bswap", "$0") ||
15364 matchAsm(AsmPieces[0], "bswapl", "$0") ||
15365 matchAsm(AsmPieces[0], "bswapq", "$0") ||
15366 matchAsm(AsmPieces[0], "bswap", "${0:q}") ||
15367 matchAsm(AsmPieces[0], "bswapl", "${0:q}") ||
15368 matchAsm(AsmPieces[0], "bswapq", "${0:q}")) {
15369 // No need to check constraints, nothing other than the equivalent of
15370 // "=r,0" would be valid here.
15371 return IntrinsicLowering::LowerToByteSwap(CI);
15374 // rorw $$8, ${0:w} --> llvm.bswap.i16
15375 if (CI->getType()->isIntegerTy(16) &&
15376 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 &&
15377 (matchAsm(AsmPieces[0], "rorw", "$$8,", "${0:w}") ||
15378 matchAsm(AsmPieces[0], "rolw", "$$8,", "${0:w}"))) {
15380 const std::string &ConstraintsStr = IA->getConstraintString();
15381 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
15382 std::sort(AsmPieces.begin(), AsmPieces.end());
15383 if (AsmPieces.size() == 4 &&
15384 AsmPieces[0] == "~{cc}" &&
15385 AsmPieces[1] == "~{dirflag}" &&
15386 AsmPieces[2] == "~{flags}" &&
15387 AsmPieces[3] == "~{fpsr}")
15388 return IntrinsicLowering::LowerToByteSwap(CI);
15392 if (CI->getType()->isIntegerTy(32) &&
15393 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 &&
15394 matchAsm(AsmPieces[0], "rorw", "$$8,", "${0:w}") &&
15395 matchAsm(AsmPieces[1], "rorl", "$$16,", "$0") &&
15396 matchAsm(AsmPieces[2], "rorw", "$$8,", "${0:w}")) {
15398 const std::string &ConstraintsStr = IA->getConstraintString();
15399 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
15400 std::sort(AsmPieces.begin(), AsmPieces.end());
15401 if (AsmPieces.size() == 4 &&
15402 AsmPieces[0] == "~{cc}" &&
15403 AsmPieces[1] == "~{dirflag}" &&
15404 AsmPieces[2] == "~{flags}" &&
15405 AsmPieces[3] == "~{fpsr}")
15406 return IntrinsicLowering::LowerToByteSwap(CI);
15409 if (CI->getType()->isIntegerTy(64)) {
15410 InlineAsm::ConstraintInfoVector Constraints = IA->ParseConstraints();
15411 if (Constraints.size() >= 2 &&
15412 Constraints[0].Codes.size() == 1 && Constraints[0].Codes[0] == "A" &&
15413 Constraints[1].Codes.size() == 1 && Constraints[1].Codes[0] == "0") {
15414 // bswap %eax / bswap %edx / xchgl %eax, %edx -> llvm.bswap.i64
15415 if (matchAsm(AsmPieces[0], "bswap", "%eax") &&
15416 matchAsm(AsmPieces[1], "bswap", "%edx") &&
15417 matchAsm(AsmPieces[2], "xchgl", "%eax,", "%edx"))
15418 return IntrinsicLowering::LowerToByteSwap(CI);
15428 /// getConstraintType - Given a constraint letter, return the type of
15429 /// constraint it is for this target.
15430 X86TargetLowering::ConstraintType
15431 X86TargetLowering::getConstraintType(const std::string &Constraint) const {
15432 if (Constraint.size() == 1) {
15433 switch (Constraint[0]) {
15444 return C_RegisterClass;
15468 return TargetLowering::getConstraintType(Constraint);
15471 /// Examine constraint type and operand type and determine a weight value.
15472 /// This object must already have been set up with the operand type
15473 /// and the current alternative constraint selected.
15474 TargetLowering::ConstraintWeight
15475 X86TargetLowering::getSingleConstraintMatchWeight(
15476 AsmOperandInfo &info, const char *constraint) const {
15477 ConstraintWeight weight = CW_Invalid;
15478 Value *CallOperandVal = info.CallOperandVal;
15479 // If we don't have a value, we can't do a match,
15480 // but allow it at the lowest weight.
15481 if (CallOperandVal == NULL)
15483 Type *type = CallOperandVal->getType();
15484 // Look at the constraint type.
15485 switch (*constraint) {
15487 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
15498 if (CallOperandVal->getType()->isIntegerTy())
15499 weight = CW_SpecificReg;
15504 if (type->isFloatingPointTy())
15505 weight = CW_SpecificReg;
15508 if (type->isX86_MMXTy() && Subtarget->hasMMX())
15509 weight = CW_SpecificReg;
15513 if (((type->getPrimitiveSizeInBits() == 128) && Subtarget->hasSSE1()) ||
15514 ((type->getPrimitiveSizeInBits() == 256) && Subtarget->hasAVX()))
15515 weight = CW_Register;
15518 if (ConstantInt *C = dyn_cast<ConstantInt>(info.CallOperandVal)) {
15519 if (C->getZExtValue() <= 31)
15520 weight = CW_Constant;
15524 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
15525 if (C->getZExtValue() <= 63)
15526 weight = CW_Constant;
15530 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
15531 if ((C->getSExtValue() >= -0x80) && (C->getSExtValue() <= 0x7f))
15532 weight = CW_Constant;
15536 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
15537 if ((C->getZExtValue() == 0xff) || (C->getZExtValue() == 0xffff))
15538 weight = CW_Constant;
15542 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
15543 if (C->getZExtValue() <= 3)
15544 weight = CW_Constant;
15548 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
15549 if (C->getZExtValue() <= 0xff)
15550 weight = CW_Constant;
15555 if (dyn_cast<ConstantFP>(CallOperandVal)) {
15556 weight = CW_Constant;
15560 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
15561 if ((C->getSExtValue() >= -0x80000000LL) &&
15562 (C->getSExtValue() <= 0x7fffffffLL))
15563 weight = CW_Constant;
15567 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
15568 if (C->getZExtValue() <= 0xffffffff)
15569 weight = CW_Constant;
15576 /// LowerXConstraint - try to replace an X constraint, which matches anything,
15577 /// with another that has more specific requirements based on the type of the
15578 /// corresponding operand.
15579 const char *X86TargetLowering::
15580 LowerXConstraint(EVT ConstraintVT) const {
15581 // FP X constraints get lowered to SSE1/2 registers if available, otherwise
15582 // 'f' like normal targets.
15583 if (ConstraintVT.isFloatingPoint()) {
15584 if (Subtarget->hasSSE2())
15586 if (Subtarget->hasSSE1())
15590 return TargetLowering::LowerXConstraint(ConstraintVT);
15593 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
15594 /// vector. If it is invalid, don't add anything to Ops.
15595 void X86TargetLowering::LowerAsmOperandForConstraint(SDValue Op,
15596 std::string &Constraint,
15597 std::vector<SDValue>&Ops,
15598 SelectionDAG &DAG) const {
15599 SDValue Result(0, 0);
15601 // Only support length 1 constraints for now.
15602 if (Constraint.length() > 1) return;
15604 char ConstraintLetter = Constraint[0];
15605 switch (ConstraintLetter) {
15608 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
15609 if (C->getZExtValue() <= 31) {
15610 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
15616 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
15617 if (C->getZExtValue() <= 63) {
15618 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
15624 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
15625 if ((int8_t)C->getSExtValue() == C->getSExtValue()) {
15626 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
15632 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
15633 if (C->getZExtValue() <= 255) {
15634 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
15640 // 32-bit signed value
15641 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
15642 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
15643 C->getSExtValue())) {
15644 // Widen to 64 bits here to get it sign extended.
15645 Result = DAG.getTargetConstant(C->getSExtValue(), MVT::i64);
15648 // FIXME gcc accepts some relocatable values here too, but only in certain
15649 // memory models; it's complicated.
15654 // 32-bit unsigned value
15655 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
15656 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
15657 C->getZExtValue())) {
15658 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
15662 // FIXME gcc accepts some relocatable values here too, but only in certain
15663 // memory models; it's complicated.
15667 // Literal immediates are always ok.
15668 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op)) {
15669 // Widen to 64 bits here to get it sign extended.
15670 Result = DAG.getTargetConstant(CST->getSExtValue(), MVT::i64);
15674 // In any sort of PIC mode addresses need to be computed at runtime by
15675 // adding in a register or some sort of table lookup. These can't
15676 // be used as immediates.
15677 if (Subtarget->isPICStyleGOT() || Subtarget->isPICStyleStubPIC())
15680 // If we are in non-pic codegen mode, we allow the address of a global (with
15681 // an optional displacement) to be used with 'i'.
15682 GlobalAddressSDNode *GA = 0;
15683 int64_t Offset = 0;
15685 // Match either (GA), (GA+C), (GA+C1+C2), etc.
15687 if ((GA = dyn_cast<GlobalAddressSDNode>(Op))) {
15688 Offset += GA->getOffset();
15690 } else if (Op.getOpcode() == ISD::ADD) {
15691 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
15692 Offset += C->getZExtValue();
15693 Op = Op.getOperand(0);
15696 } else if (Op.getOpcode() == ISD::SUB) {
15697 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
15698 Offset += -C->getZExtValue();
15699 Op = Op.getOperand(0);
15704 // Otherwise, this isn't something we can handle, reject it.
15708 const GlobalValue *GV = GA->getGlobal();
15709 // If we require an extra load to get this address, as in PIC mode, we
15710 // can't accept it.
15711 if (isGlobalStubReference(Subtarget->ClassifyGlobalReference(GV,
15712 getTargetMachine())))
15715 Result = DAG.getTargetGlobalAddress(GV, Op.getDebugLoc(),
15716 GA->getValueType(0), Offset);
15721 if (Result.getNode()) {
15722 Ops.push_back(Result);
15725 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
15728 std::pair<unsigned, const TargetRegisterClass*>
15729 X86TargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
15731 // First, see if this is a constraint that directly corresponds to an LLVM
15733 if (Constraint.size() == 1) {
15734 // GCC Constraint Letters
15735 switch (Constraint[0]) {
15737 // TODO: Slight differences here in allocation order and leaving
15738 // RIP in the class. Do they matter any more here than they do
15739 // in the normal allocation?
15740 case 'q': // GENERAL_REGS in 64-bit mode, Q_REGS in 32-bit mode.
15741 if (Subtarget->is64Bit()) {
15742 if (VT == MVT::i32 || VT == MVT::f32)
15743 return std::make_pair(0U, &X86::GR32RegClass);
15744 if (VT == MVT::i16)
15745 return std::make_pair(0U, &X86::GR16RegClass);
15746 if (VT == MVT::i8 || VT == MVT::i1)
15747 return std::make_pair(0U, &X86::GR8RegClass);
15748 if (VT == MVT::i64 || VT == MVT::f64)
15749 return std::make_pair(0U, &X86::GR64RegClass);
15752 // 32-bit fallthrough
15753 case 'Q': // Q_REGS
15754 if (VT == MVT::i32 || VT == MVT::f32)
15755 return std::make_pair(0U, &X86::GR32_ABCDRegClass);
15756 if (VT == MVT::i16)
15757 return std::make_pair(0U, &X86::GR16_ABCDRegClass);
15758 if (VT == MVT::i8 || VT == MVT::i1)
15759 return std::make_pair(0U, &X86::GR8_ABCD_LRegClass);
15760 if (VT == MVT::i64)
15761 return std::make_pair(0U, &X86::GR64_ABCDRegClass);
15763 case 'r': // GENERAL_REGS
15764 case 'l': // INDEX_REGS
15765 if (VT == MVT::i8 || VT == MVT::i1)
15766 return std::make_pair(0U, &X86::GR8RegClass);
15767 if (VT == MVT::i16)
15768 return std::make_pair(0U, &X86::GR16RegClass);
15769 if (VT == MVT::i32 || VT == MVT::f32 || !Subtarget->is64Bit())
15770 return std::make_pair(0U, &X86::GR32RegClass);
15771 return std::make_pair(0U, &X86::GR64RegClass);
15772 case 'R': // LEGACY_REGS
15773 if (VT == MVT::i8 || VT == MVT::i1)
15774 return std::make_pair(0U, &X86::GR8_NOREXRegClass);
15775 if (VT == MVT::i16)
15776 return std::make_pair(0U, &X86::GR16_NOREXRegClass);
15777 if (VT == MVT::i32 || !Subtarget->is64Bit())
15778 return std::make_pair(0U, &X86::GR32_NOREXRegClass);
15779 return std::make_pair(0U, &X86::GR64_NOREXRegClass);
15780 case 'f': // FP Stack registers.
15781 // If SSE is enabled for this VT, use f80 to ensure the isel moves the
15782 // value to the correct fpstack register class.
15783 if (VT == MVT::f32 && !isScalarFPTypeInSSEReg(VT))
15784 return std::make_pair(0U, &X86::RFP32RegClass);
15785 if (VT == MVT::f64 && !isScalarFPTypeInSSEReg(VT))
15786 return std::make_pair(0U, &X86::RFP64RegClass);
15787 return std::make_pair(0U, &X86::RFP80RegClass);
15788 case 'y': // MMX_REGS if MMX allowed.
15789 if (!Subtarget->hasMMX()) break;
15790 return std::make_pair(0U, &X86::VR64RegClass);
15791 case 'Y': // SSE_REGS if SSE2 allowed
15792 if (!Subtarget->hasSSE2()) break;
15794 case 'x': // SSE_REGS if SSE1 allowed or AVX_REGS if AVX allowed
15795 if (!Subtarget->hasSSE1()) break;
15797 switch (VT.getSimpleVT().SimpleTy) {
15799 // Scalar SSE types.
15802 return std::make_pair(0U, &X86::FR32RegClass);
15805 return std::make_pair(0U, &X86::FR64RegClass);
15813 return std::make_pair(0U, &X86::VR128RegClass);
15821 return std::make_pair(0U, &X86::VR256RegClass);
15827 // Use the default implementation in TargetLowering to convert the register
15828 // constraint into a member of a register class.
15829 std::pair<unsigned, const TargetRegisterClass*> Res;
15830 Res = TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
15832 // Not found as a standard register?
15833 if (Res.second == 0) {
15834 // Map st(0) -> st(7) -> ST0
15835 if (Constraint.size() == 7 && Constraint[0] == '{' &&
15836 tolower(Constraint[1]) == 's' &&
15837 tolower(Constraint[2]) == 't' &&
15838 Constraint[3] == '(' &&
15839 (Constraint[4] >= '0' && Constraint[4] <= '7') &&
15840 Constraint[5] == ')' &&
15841 Constraint[6] == '}') {
15843 Res.first = X86::ST0+Constraint[4]-'0';
15844 Res.second = &X86::RFP80RegClass;
15848 // GCC allows "st(0)" to be called just plain "st".
15849 if (StringRef("{st}").equals_lower(Constraint)) {
15850 Res.first = X86::ST0;
15851 Res.second = &X86::RFP80RegClass;
15856 if (StringRef("{flags}").equals_lower(Constraint)) {
15857 Res.first = X86::EFLAGS;
15858 Res.second = &X86::CCRRegClass;
15862 // 'A' means EAX + EDX.
15863 if (Constraint == "A") {
15864 Res.first = X86::EAX;
15865 Res.second = &X86::GR32_ADRegClass;
15871 // Otherwise, check to see if this is a register class of the wrong value
15872 // type. For example, we want to map "{ax},i32" -> {eax}, we don't want it to
15873 // turn into {ax},{dx}.
15874 if (Res.second->hasType(VT))
15875 return Res; // Correct type already, nothing to do.
15877 // All of the single-register GCC register classes map their values onto
15878 // 16-bit register pieces "ax","dx","cx","bx","si","di","bp","sp". If we
15879 // really want an 8-bit or 32-bit register, map to the appropriate register
15880 // class and return the appropriate register.
15881 if (Res.second == &X86::GR16RegClass) {
15882 if (VT == MVT::i8) {
15883 unsigned DestReg = 0;
15884 switch (Res.first) {
15886 case X86::AX: DestReg = X86::AL; break;
15887 case X86::DX: DestReg = X86::DL; break;
15888 case X86::CX: DestReg = X86::CL; break;
15889 case X86::BX: DestReg = X86::BL; break;
15892 Res.first = DestReg;
15893 Res.second = &X86::GR8RegClass;
15895 } else if (VT == MVT::i32) {
15896 unsigned DestReg = 0;
15897 switch (Res.first) {
15899 case X86::AX: DestReg = X86::EAX; break;
15900 case X86::DX: DestReg = X86::EDX; break;
15901 case X86::CX: DestReg = X86::ECX; break;
15902 case X86::BX: DestReg = X86::EBX; break;
15903 case X86::SI: DestReg = X86::ESI; break;
15904 case X86::DI: DestReg = X86::EDI; break;
15905 case X86::BP: DestReg = X86::EBP; break;
15906 case X86::SP: DestReg = X86::ESP; break;
15909 Res.first = DestReg;
15910 Res.second = &X86::GR32RegClass;
15912 } else if (VT == MVT::i64) {
15913 unsigned DestReg = 0;
15914 switch (Res.first) {
15916 case X86::AX: DestReg = X86::RAX; break;
15917 case X86::DX: DestReg = X86::RDX; break;
15918 case X86::CX: DestReg = X86::RCX; break;
15919 case X86::BX: DestReg = X86::RBX; break;
15920 case X86::SI: DestReg = X86::RSI; break;
15921 case X86::DI: DestReg = X86::RDI; break;
15922 case X86::BP: DestReg = X86::RBP; break;
15923 case X86::SP: DestReg = X86::RSP; break;
15926 Res.first = DestReg;
15927 Res.second = &X86::GR64RegClass;
15930 } else if (Res.second == &X86::FR32RegClass ||
15931 Res.second == &X86::FR64RegClass ||
15932 Res.second == &X86::VR128RegClass) {
15933 // Handle references to XMM physical registers that got mapped into the
15934 // wrong class. This can happen with constraints like {xmm0} where the
15935 // target independent register mapper will just pick the first match it can
15936 // find, ignoring the required type.
15937 if (VT == MVT::f32)
15938 Res.second = &X86::FR32RegClass;
15939 else if (VT == MVT::f64)
15940 Res.second = &X86::FR64RegClass;
15941 else if (X86::VR128RegClass.hasType(VT))
15942 Res.second = &X86::VR128RegClass;