1 //===-- X86ISelLowering.cpp - X86 DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that X86 uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "x86-isel"
16 #include "X86ISelLowering.h"
18 #include "X86InstrBuilder.h"
19 #include "X86TargetMachine.h"
20 #include "X86TargetObjectFile.h"
21 #include "Utils/X86ShuffleDecode.h"
22 #include "llvm/CallingConv.h"
23 #include "llvm/Constants.h"
24 #include "llvm/DerivedTypes.h"
25 #include "llvm/GlobalAlias.h"
26 #include "llvm/GlobalVariable.h"
27 #include "llvm/Function.h"
28 #include "llvm/Instructions.h"
29 #include "llvm/Intrinsics.h"
30 #include "llvm/LLVMContext.h"
31 #include "llvm/CodeGen/IntrinsicLowering.h"
32 #include "llvm/CodeGen/MachineFrameInfo.h"
33 #include "llvm/CodeGen/MachineFunction.h"
34 #include "llvm/CodeGen/MachineInstrBuilder.h"
35 #include "llvm/CodeGen/MachineJumpTableInfo.h"
36 #include "llvm/CodeGen/MachineModuleInfo.h"
37 #include "llvm/CodeGen/MachineRegisterInfo.h"
38 #include "llvm/MC/MCAsmInfo.h"
39 #include "llvm/MC/MCContext.h"
40 #include "llvm/MC/MCExpr.h"
41 #include "llvm/MC/MCSymbol.h"
42 #include "llvm/ADT/SmallSet.h"
43 #include "llvm/ADT/Statistic.h"
44 #include "llvm/ADT/StringExtras.h"
45 #include "llvm/ADT/VariadicFunction.h"
46 #include "llvm/Support/CallSite.h"
47 #include "llvm/Support/Debug.h"
48 #include "llvm/Support/ErrorHandling.h"
49 #include "llvm/Support/MathExtras.h"
50 #include "llvm/Target/TargetOptions.h"
55 STATISTIC(NumTailCalls, "Number of tail calls");
57 // Forward declarations.
58 static SDValue getMOVL(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1,
61 /// Generate a DAG to grab 128-bits from a vector > 128 bits. This
62 /// sets things up to match to an AVX VEXTRACTF128 instruction or a
63 /// simple subregister reference. Idx is an index in the 128 bits we
64 /// want. It need not be aligned to a 128-bit bounday. That makes
65 /// lowering EXTRACT_VECTOR_ELT operations easier.
66 static SDValue Extract128BitVector(SDValue Vec, unsigned IdxVal,
67 SelectionDAG &DAG, DebugLoc dl) {
68 EVT VT = Vec.getValueType();
69 assert(VT.is256BitVector() && "Unexpected vector size!");
70 EVT ElVT = VT.getVectorElementType();
71 unsigned Factor = VT.getSizeInBits()/128;
72 EVT ResultVT = EVT::getVectorVT(*DAG.getContext(), ElVT,
73 VT.getVectorNumElements()/Factor);
75 // Extract from UNDEF is UNDEF.
76 if (Vec.getOpcode() == ISD::UNDEF)
77 return DAG.getUNDEF(ResultVT);
79 // Extract the relevant 128 bits. Generate an EXTRACT_SUBVECTOR
80 // we can match to VEXTRACTF128.
81 unsigned ElemsPerChunk = 128 / ElVT.getSizeInBits();
83 // This is the index of the first element of the 128-bit chunk
85 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits()) / 128)
88 SDValue VecIdx = DAG.getConstant(NormalizedIdxVal, MVT::i32);
89 SDValue Result = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, ResultVT, Vec,
95 /// Generate a DAG to put 128-bits into a vector > 128 bits. This
96 /// sets things up to match to an AVX VINSERTF128 instruction or a
97 /// simple superregister reference. Idx is an index in the 128 bits
98 /// we want. It need not be aligned to a 128-bit bounday. That makes
99 /// lowering INSERT_VECTOR_ELT operations easier.
100 static SDValue Insert128BitVector(SDValue Result, SDValue Vec,
101 unsigned IdxVal, SelectionDAG &DAG,
103 // Inserting UNDEF is Result
104 if (Vec.getOpcode() == ISD::UNDEF)
107 EVT VT = Vec.getValueType();
108 assert(VT.is128BitVector() && "Unexpected vector size!");
110 EVT ElVT = VT.getVectorElementType();
111 EVT ResultVT = Result.getValueType();
113 // Insert the relevant 128 bits.
114 unsigned ElemsPerChunk = 128/ElVT.getSizeInBits();
116 // This is the index of the first element of the 128-bit chunk
118 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits())/128)
121 SDValue VecIdx = DAG.getConstant(NormalizedIdxVal, MVT::i32);
122 return DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResultVT, Result, Vec,
126 /// Concat two 128-bit vectors into a 256 bit vector using VINSERTF128
127 /// instructions. This is used because creating CONCAT_VECTOR nodes of
128 /// BUILD_VECTORS returns a larger BUILD_VECTOR while we're trying to lower
129 /// large BUILD_VECTORS.
130 static SDValue Concat128BitVectors(SDValue V1, SDValue V2, EVT VT,
131 unsigned NumElems, SelectionDAG &DAG,
133 SDValue V = Insert128BitVector(DAG.getUNDEF(VT), V1, 0, DAG, dl);
134 return Insert128BitVector(V, V2, NumElems/2, DAG, dl);
137 static TargetLoweringObjectFile *createTLOF(X86TargetMachine &TM) {
138 const X86Subtarget *Subtarget = &TM.getSubtarget<X86Subtarget>();
139 bool is64Bit = Subtarget->is64Bit();
141 if (Subtarget->isTargetEnvMacho()) {
143 return new X86_64MachoTargetObjectFile();
144 return new TargetLoweringObjectFileMachO();
147 if (Subtarget->isTargetLinux())
148 return new X86LinuxTargetObjectFile();
149 if (Subtarget->isTargetELF())
150 return new TargetLoweringObjectFileELF();
151 if (Subtarget->isTargetCOFF() && !Subtarget->isTargetEnvMacho())
152 return new TargetLoweringObjectFileCOFF();
153 llvm_unreachable("unknown subtarget type");
156 X86TargetLowering::X86TargetLowering(X86TargetMachine &TM)
157 : TargetLowering(TM, createTLOF(TM)) {
158 Subtarget = &TM.getSubtarget<X86Subtarget>();
159 X86ScalarSSEf64 = Subtarget->hasSSE2();
160 X86ScalarSSEf32 = Subtarget->hasSSE1();
161 X86StackPtr = Subtarget->is64Bit() ? X86::RSP : X86::ESP;
163 RegInfo = TM.getRegisterInfo();
164 TD = getTargetData();
166 // Set up the TargetLowering object.
167 static const MVT IntVTs[] = { MVT::i8, MVT::i16, MVT::i32, MVT::i64 };
169 // X86 is weird, it always uses i8 for shift amounts and setcc results.
170 setBooleanContents(ZeroOrOneBooleanContent);
171 // X86-SSE is even stranger. It uses -1 or 0 for vector masks.
172 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
174 // For 64-bit since we have so many registers use the ILP scheduler, for
175 // 32-bit code use the register pressure specific scheduling.
176 // For Atom, always use ILP scheduling.
177 if (Subtarget->isAtom())
178 setSchedulingPreference(Sched::ILP);
179 else if (Subtarget->is64Bit())
180 setSchedulingPreference(Sched::ILP);
182 setSchedulingPreference(Sched::RegPressure);
183 setStackPointerRegisterToSaveRestore(X86StackPtr);
185 if (Subtarget->isTargetWindows() && !Subtarget->isTargetCygMing()) {
186 // Setup Windows compiler runtime calls.
187 setLibcallName(RTLIB::SDIV_I64, "_alldiv");
188 setLibcallName(RTLIB::UDIV_I64, "_aulldiv");
189 setLibcallName(RTLIB::SREM_I64, "_allrem");
190 setLibcallName(RTLIB::UREM_I64, "_aullrem");
191 setLibcallName(RTLIB::MUL_I64, "_allmul");
192 setLibcallCallingConv(RTLIB::SDIV_I64, CallingConv::X86_StdCall);
193 setLibcallCallingConv(RTLIB::UDIV_I64, CallingConv::X86_StdCall);
194 setLibcallCallingConv(RTLIB::SREM_I64, CallingConv::X86_StdCall);
195 setLibcallCallingConv(RTLIB::UREM_I64, CallingConv::X86_StdCall);
196 setLibcallCallingConv(RTLIB::MUL_I64, CallingConv::X86_StdCall);
198 // The _ftol2 runtime function has an unusual calling conv, which
199 // is modeled by a special pseudo-instruction.
200 setLibcallName(RTLIB::FPTOUINT_F64_I64, 0);
201 setLibcallName(RTLIB::FPTOUINT_F32_I64, 0);
202 setLibcallName(RTLIB::FPTOUINT_F64_I32, 0);
203 setLibcallName(RTLIB::FPTOUINT_F32_I32, 0);
206 if (Subtarget->isTargetDarwin()) {
207 // Darwin should use _setjmp/_longjmp instead of setjmp/longjmp.
208 setUseUnderscoreSetJmp(false);
209 setUseUnderscoreLongJmp(false);
210 } else if (Subtarget->isTargetMingw()) {
211 // MS runtime is weird: it exports _setjmp, but longjmp!
212 setUseUnderscoreSetJmp(true);
213 setUseUnderscoreLongJmp(false);
215 setUseUnderscoreSetJmp(true);
216 setUseUnderscoreLongJmp(true);
219 // Set up the register classes.
220 addRegisterClass(MVT::i8, &X86::GR8RegClass);
221 addRegisterClass(MVT::i16, &X86::GR16RegClass);
222 addRegisterClass(MVT::i32, &X86::GR32RegClass);
223 if (Subtarget->is64Bit())
224 addRegisterClass(MVT::i64, &X86::GR64RegClass);
226 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
228 // We don't accept any truncstore of integer registers.
229 setTruncStoreAction(MVT::i64, MVT::i32, Expand);
230 setTruncStoreAction(MVT::i64, MVT::i16, Expand);
231 setTruncStoreAction(MVT::i64, MVT::i8 , Expand);
232 setTruncStoreAction(MVT::i32, MVT::i16, Expand);
233 setTruncStoreAction(MVT::i32, MVT::i8 , Expand);
234 setTruncStoreAction(MVT::i16, MVT::i8, Expand);
236 // SETOEQ and SETUNE require checking two conditions.
237 setCondCodeAction(ISD::SETOEQ, MVT::f32, Expand);
238 setCondCodeAction(ISD::SETOEQ, MVT::f64, Expand);
239 setCondCodeAction(ISD::SETOEQ, MVT::f80, Expand);
240 setCondCodeAction(ISD::SETUNE, MVT::f32, Expand);
241 setCondCodeAction(ISD::SETUNE, MVT::f64, Expand);
242 setCondCodeAction(ISD::SETUNE, MVT::f80, Expand);
244 // Promote all UINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have this
246 setOperationAction(ISD::UINT_TO_FP , MVT::i1 , Promote);
247 setOperationAction(ISD::UINT_TO_FP , MVT::i8 , Promote);
248 setOperationAction(ISD::UINT_TO_FP , MVT::i16 , Promote);
250 if (Subtarget->is64Bit()) {
251 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote);
252 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
253 } else if (!TM.Options.UseSoftFloat) {
254 // We have an algorithm for SSE2->double, and we turn this into a
255 // 64-bit FILD followed by conditional FADD for other targets.
256 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
257 // We have an algorithm for SSE2, and we turn this into a 64-bit
258 // FILD for other targets.
259 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Custom);
262 // Promote i1/i8 SINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have
264 setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote);
265 setOperationAction(ISD::SINT_TO_FP , MVT::i8 , Promote);
267 if (!TM.Options.UseSoftFloat) {
268 // SSE has no i16 to fp conversion, only i32
269 if (X86ScalarSSEf32) {
270 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
271 // f32 and f64 cases are Legal, f80 case is not
272 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
274 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Custom);
275 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
278 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
279 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Promote);
282 // In 32-bit mode these are custom lowered. In 64-bit mode F32 and F64
283 // are Legal, f80 is custom lowered.
284 setOperationAction(ISD::FP_TO_SINT , MVT::i64 , Custom);
285 setOperationAction(ISD::SINT_TO_FP , MVT::i64 , Custom);
287 // Promote i1/i8 FP_TO_SINT to larger FP_TO_SINTS's, as X86 doesn't have
289 setOperationAction(ISD::FP_TO_SINT , MVT::i1 , Promote);
290 setOperationAction(ISD::FP_TO_SINT , MVT::i8 , Promote);
292 if (X86ScalarSSEf32) {
293 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Promote);
294 // f32 and f64 cases are Legal, f80 case is not
295 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
297 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Custom);
298 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
301 // Handle FP_TO_UINT by promoting the destination to a larger signed
303 setOperationAction(ISD::FP_TO_UINT , MVT::i1 , Promote);
304 setOperationAction(ISD::FP_TO_UINT , MVT::i8 , Promote);
305 setOperationAction(ISD::FP_TO_UINT , MVT::i16 , Promote);
307 if (Subtarget->is64Bit()) {
308 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Expand);
309 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote);
310 } else if (!TM.Options.UseSoftFloat) {
311 // Since AVX is a superset of SSE3, only check for SSE here.
312 if (Subtarget->hasSSE1() && !Subtarget->hasSSE3())
313 // Expand FP_TO_UINT into a select.
314 // FIXME: We would like to use a Custom expander here eventually to do
315 // the optimal thing for SSE vs. the default expansion in the legalizer.
316 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Expand);
318 // With SSE3 we can use fisttpll to convert to a signed i64; without
319 // SSE, we're stuck with a fistpll.
320 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Custom);
323 if (isTargetFTOL()) {
324 // Use the _ftol2 runtime function, which has a pseudo-instruction
325 // to handle its weird calling convention.
326 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Custom);
329 // TODO: when we have SSE, these could be more efficient, by using movd/movq.
330 if (!X86ScalarSSEf64) {
331 setOperationAction(ISD::BITCAST , MVT::f32 , Expand);
332 setOperationAction(ISD::BITCAST , MVT::i32 , Expand);
333 if (Subtarget->is64Bit()) {
334 setOperationAction(ISD::BITCAST , MVT::f64 , Expand);
335 // Without SSE, i64->f64 goes through memory.
336 setOperationAction(ISD::BITCAST , MVT::i64 , Expand);
340 // Scalar integer divide and remainder are lowered to use operations that
341 // produce two results, to match the available instructions. This exposes
342 // the two-result form to trivial CSE, which is able to combine x/y and x%y
343 // into a single instruction.
345 // Scalar integer multiply-high is also lowered to use two-result
346 // operations, to match the available instructions. However, plain multiply
347 // (low) operations are left as Legal, as there are single-result
348 // instructions for this in x86. Using the two-result multiply instructions
349 // when both high and low results are needed must be arranged by dagcombine.
350 for (unsigned i = 0; i != array_lengthof(IntVTs); ++i) {
352 setOperationAction(ISD::MULHS, VT, Expand);
353 setOperationAction(ISD::MULHU, VT, Expand);
354 setOperationAction(ISD::SDIV, VT, Expand);
355 setOperationAction(ISD::UDIV, VT, Expand);
356 setOperationAction(ISD::SREM, VT, Expand);
357 setOperationAction(ISD::UREM, VT, Expand);
359 // Add/Sub overflow ops with MVT::Glues are lowered to EFLAGS dependences.
360 setOperationAction(ISD::ADDC, VT, Custom);
361 setOperationAction(ISD::ADDE, VT, Custom);
362 setOperationAction(ISD::SUBC, VT, Custom);
363 setOperationAction(ISD::SUBE, VT, Custom);
366 setOperationAction(ISD::BR_JT , MVT::Other, Expand);
367 setOperationAction(ISD::BRCOND , MVT::Other, Custom);
368 setOperationAction(ISD::BR_CC , MVT::Other, Expand);
369 setOperationAction(ISD::SELECT_CC , MVT::Other, Expand);
370 if (Subtarget->is64Bit())
371 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal);
372 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Legal);
373 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Legal);
374 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
375 setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand);
376 setOperationAction(ISD::FREM , MVT::f32 , Expand);
377 setOperationAction(ISD::FREM , MVT::f64 , Expand);
378 setOperationAction(ISD::FREM , MVT::f80 , Expand);
379 setOperationAction(ISD::FLT_ROUNDS_ , MVT::i32 , Custom);
381 // Promote the i8 variants and force them on up to i32 which has a shorter
383 setOperationAction(ISD::CTTZ , MVT::i8 , Promote);
384 AddPromotedToType (ISD::CTTZ , MVT::i8 , MVT::i32);
385 setOperationAction(ISD::CTTZ_ZERO_UNDEF , MVT::i8 , Promote);
386 AddPromotedToType (ISD::CTTZ_ZERO_UNDEF , MVT::i8 , MVT::i32);
387 if (Subtarget->hasBMI()) {
388 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i16 , Expand);
389 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32 , Expand);
390 if (Subtarget->is64Bit())
391 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand);
393 setOperationAction(ISD::CTTZ , MVT::i16 , Custom);
394 setOperationAction(ISD::CTTZ , MVT::i32 , Custom);
395 if (Subtarget->is64Bit())
396 setOperationAction(ISD::CTTZ , MVT::i64 , Custom);
399 if (Subtarget->hasLZCNT()) {
400 // When promoting the i8 variants, force them to i32 for a shorter
402 setOperationAction(ISD::CTLZ , MVT::i8 , Promote);
403 AddPromotedToType (ISD::CTLZ , MVT::i8 , MVT::i32);
404 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Promote);
405 AddPromotedToType (ISD::CTLZ_ZERO_UNDEF, MVT::i8 , MVT::i32);
406 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Expand);
407 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Expand);
408 if (Subtarget->is64Bit())
409 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Expand);
411 setOperationAction(ISD::CTLZ , MVT::i8 , Custom);
412 setOperationAction(ISD::CTLZ , MVT::i16 , Custom);
413 setOperationAction(ISD::CTLZ , MVT::i32 , Custom);
414 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Custom);
415 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Custom);
416 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Custom);
417 if (Subtarget->is64Bit()) {
418 setOperationAction(ISD::CTLZ , MVT::i64 , Custom);
419 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Custom);
423 if (Subtarget->hasPOPCNT()) {
424 setOperationAction(ISD::CTPOP , MVT::i8 , Promote);
426 setOperationAction(ISD::CTPOP , MVT::i8 , Expand);
427 setOperationAction(ISD::CTPOP , MVT::i16 , Expand);
428 setOperationAction(ISD::CTPOP , MVT::i32 , Expand);
429 if (Subtarget->is64Bit())
430 setOperationAction(ISD::CTPOP , MVT::i64 , Expand);
433 setOperationAction(ISD::READCYCLECOUNTER , MVT::i64 , Custom);
434 setOperationAction(ISD::BSWAP , MVT::i16 , Expand);
436 // These should be promoted to a larger select which is supported.
437 setOperationAction(ISD::SELECT , MVT::i1 , Promote);
438 // X86 wants to expand cmov itself.
439 setOperationAction(ISD::SELECT , MVT::i8 , Custom);
440 setOperationAction(ISD::SELECT , MVT::i16 , Custom);
441 setOperationAction(ISD::SELECT , MVT::i32 , Custom);
442 setOperationAction(ISD::SELECT , MVT::f32 , Custom);
443 setOperationAction(ISD::SELECT , MVT::f64 , Custom);
444 setOperationAction(ISD::SELECT , MVT::f80 , Custom);
445 setOperationAction(ISD::SETCC , MVT::i8 , Custom);
446 setOperationAction(ISD::SETCC , MVT::i16 , Custom);
447 setOperationAction(ISD::SETCC , MVT::i32 , Custom);
448 setOperationAction(ISD::SETCC , MVT::f32 , Custom);
449 setOperationAction(ISD::SETCC , MVT::f64 , Custom);
450 setOperationAction(ISD::SETCC , MVT::f80 , Custom);
451 if (Subtarget->is64Bit()) {
452 setOperationAction(ISD::SELECT , MVT::i64 , Custom);
453 setOperationAction(ISD::SETCC , MVT::i64 , Custom);
455 setOperationAction(ISD::EH_RETURN , MVT::Other, Custom);
458 setOperationAction(ISD::ConstantPool , MVT::i32 , Custom);
459 setOperationAction(ISD::JumpTable , MVT::i32 , Custom);
460 setOperationAction(ISD::GlobalAddress , MVT::i32 , Custom);
461 setOperationAction(ISD::GlobalTLSAddress, MVT::i32 , Custom);
462 if (Subtarget->is64Bit())
463 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
464 setOperationAction(ISD::ExternalSymbol , MVT::i32 , Custom);
465 setOperationAction(ISD::BlockAddress , MVT::i32 , Custom);
466 if (Subtarget->is64Bit()) {
467 setOperationAction(ISD::ConstantPool , MVT::i64 , Custom);
468 setOperationAction(ISD::JumpTable , MVT::i64 , Custom);
469 setOperationAction(ISD::GlobalAddress , MVT::i64 , Custom);
470 setOperationAction(ISD::ExternalSymbol, MVT::i64 , Custom);
471 setOperationAction(ISD::BlockAddress , MVT::i64 , Custom);
473 // 64-bit addm sub, shl, sra, srl (iff 32-bit x86)
474 setOperationAction(ISD::SHL_PARTS , MVT::i32 , Custom);
475 setOperationAction(ISD::SRA_PARTS , MVT::i32 , Custom);
476 setOperationAction(ISD::SRL_PARTS , MVT::i32 , Custom);
477 if (Subtarget->is64Bit()) {
478 setOperationAction(ISD::SHL_PARTS , MVT::i64 , Custom);
479 setOperationAction(ISD::SRA_PARTS , MVT::i64 , Custom);
480 setOperationAction(ISD::SRL_PARTS , MVT::i64 , Custom);
483 if (Subtarget->hasSSE1())
484 setOperationAction(ISD::PREFETCH , MVT::Other, Legal);
486 setOperationAction(ISD::MEMBARRIER , MVT::Other, Custom);
487 setOperationAction(ISD::ATOMIC_FENCE , MVT::Other, Custom);
489 // On X86 and X86-64, atomic operations are lowered to locked instructions.
490 // Locked instructions, in turn, have implicit fence semantics (all memory
491 // operations are flushed before issuing the locked instruction, and they
492 // are not buffered), so we can fold away the common pattern of
493 // fence-atomic-fence.
494 setShouldFoldAtomicFences(true);
496 // Expand certain atomics
497 for (unsigned i = 0; i != array_lengthof(IntVTs); ++i) {
499 setOperationAction(ISD::ATOMIC_CMP_SWAP, VT, Custom);
500 setOperationAction(ISD::ATOMIC_LOAD_SUB, VT, Custom);
501 setOperationAction(ISD::ATOMIC_STORE, VT, Custom);
504 if (!Subtarget->is64Bit()) {
505 setOperationAction(ISD::ATOMIC_LOAD, MVT::i64, Custom);
506 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i64, Custom);
507 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i64, Custom);
508 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i64, Custom);
509 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i64, Custom);
510 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i64, Custom);
511 setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i64, Custom);
512 setOperationAction(ISD::ATOMIC_SWAP, MVT::i64, Custom);
515 if (Subtarget->hasCmpxchg16b()) {
516 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i128, Custom);
519 // FIXME - use subtarget debug flags
520 if (!Subtarget->isTargetDarwin() &&
521 !Subtarget->isTargetELF() &&
522 !Subtarget->isTargetCygMing()) {
523 setOperationAction(ISD::EH_LABEL, MVT::Other, Expand);
526 setOperationAction(ISD::EXCEPTIONADDR, MVT::i64, Expand);
527 setOperationAction(ISD::EHSELECTION, MVT::i64, Expand);
528 setOperationAction(ISD::EXCEPTIONADDR, MVT::i32, Expand);
529 setOperationAction(ISD::EHSELECTION, MVT::i32, Expand);
530 if (Subtarget->is64Bit()) {
531 setExceptionPointerRegister(X86::RAX);
532 setExceptionSelectorRegister(X86::RDX);
534 setExceptionPointerRegister(X86::EAX);
535 setExceptionSelectorRegister(X86::EDX);
537 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i32, Custom);
538 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i64, Custom);
540 setOperationAction(ISD::INIT_TRAMPOLINE, MVT::Other, Custom);
541 setOperationAction(ISD::ADJUST_TRAMPOLINE, MVT::Other, Custom);
543 setOperationAction(ISD::TRAP, MVT::Other, Legal);
545 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
546 setOperationAction(ISD::VASTART , MVT::Other, Custom);
547 setOperationAction(ISD::VAEND , MVT::Other, Expand);
548 if (Subtarget->is64Bit()) {
549 setOperationAction(ISD::VAARG , MVT::Other, Custom);
550 setOperationAction(ISD::VACOPY , MVT::Other, Custom);
552 setOperationAction(ISD::VAARG , MVT::Other, Expand);
553 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
556 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
557 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
559 if (Subtarget->isTargetCOFF() && !Subtarget->isTargetEnvMacho())
560 setOperationAction(ISD::DYNAMIC_STACKALLOC, Subtarget->is64Bit() ?
561 MVT::i64 : MVT::i32, Custom);
562 else if (TM.Options.EnableSegmentedStacks)
563 setOperationAction(ISD::DYNAMIC_STACKALLOC, Subtarget->is64Bit() ?
564 MVT::i64 : MVT::i32, Custom);
566 setOperationAction(ISD::DYNAMIC_STACKALLOC, Subtarget->is64Bit() ?
567 MVT::i64 : MVT::i32, Expand);
569 if (!TM.Options.UseSoftFloat && X86ScalarSSEf64) {
570 // f32 and f64 use SSE.
571 // Set up the FP register classes.
572 addRegisterClass(MVT::f32, &X86::FR32RegClass);
573 addRegisterClass(MVT::f64, &X86::FR64RegClass);
575 // Use ANDPD to simulate FABS.
576 setOperationAction(ISD::FABS , MVT::f64, Custom);
577 setOperationAction(ISD::FABS , MVT::f32, Custom);
579 // Use XORP to simulate FNEG.
580 setOperationAction(ISD::FNEG , MVT::f64, Custom);
581 setOperationAction(ISD::FNEG , MVT::f32, Custom);
583 // Use ANDPD and ORPD to simulate FCOPYSIGN.
584 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
585 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
587 // Lower this to FGETSIGNx86 plus an AND.
588 setOperationAction(ISD::FGETSIGN, MVT::i64, Custom);
589 setOperationAction(ISD::FGETSIGN, MVT::i32, Custom);
591 // We don't support sin/cos/fmod
592 setOperationAction(ISD::FSIN , MVT::f64, Expand);
593 setOperationAction(ISD::FCOS , MVT::f64, Expand);
594 setOperationAction(ISD::FSIN , MVT::f32, Expand);
595 setOperationAction(ISD::FCOS , MVT::f32, Expand);
597 // Expand FP immediates into loads from the stack, except for the special
599 addLegalFPImmediate(APFloat(+0.0)); // xorpd
600 addLegalFPImmediate(APFloat(+0.0f)); // xorps
601 } else if (!TM.Options.UseSoftFloat && X86ScalarSSEf32) {
602 // Use SSE for f32, x87 for f64.
603 // Set up the FP register classes.
604 addRegisterClass(MVT::f32, &X86::FR32RegClass);
605 addRegisterClass(MVT::f64, &X86::RFP64RegClass);
607 // Use ANDPS to simulate FABS.
608 setOperationAction(ISD::FABS , MVT::f32, Custom);
610 // Use XORP to simulate FNEG.
611 setOperationAction(ISD::FNEG , MVT::f32, Custom);
613 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
615 // Use ANDPS and ORPS to simulate FCOPYSIGN.
616 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
617 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
619 // We don't support sin/cos/fmod
620 setOperationAction(ISD::FSIN , MVT::f32, Expand);
621 setOperationAction(ISD::FCOS , MVT::f32, Expand);
623 // Special cases we handle for FP constants.
624 addLegalFPImmediate(APFloat(+0.0f)); // xorps
625 addLegalFPImmediate(APFloat(+0.0)); // FLD0
626 addLegalFPImmediate(APFloat(+1.0)); // FLD1
627 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
628 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
630 if (!TM.Options.UnsafeFPMath) {
631 setOperationAction(ISD::FSIN , MVT::f64 , Expand);
632 setOperationAction(ISD::FCOS , MVT::f64 , Expand);
634 } else if (!TM.Options.UseSoftFloat) {
635 // f32 and f64 in x87.
636 // Set up the FP register classes.
637 addRegisterClass(MVT::f64, &X86::RFP64RegClass);
638 addRegisterClass(MVT::f32, &X86::RFP32RegClass);
640 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
641 setOperationAction(ISD::UNDEF, MVT::f32, Expand);
642 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
643 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
645 if (!TM.Options.UnsafeFPMath) {
646 setOperationAction(ISD::FSIN , MVT::f64 , Expand);
647 setOperationAction(ISD::FCOS , MVT::f64 , Expand);
649 addLegalFPImmediate(APFloat(+0.0)); // FLD0
650 addLegalFPImmediate(APFloat(+1.0)); // FLD1
651 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
652 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
653 addLegalFPImmediate(APFloat(+0.0f)); // FLD0
654 addLegalFPImmediate(APFloat(+1.0f)); // FLD1
655 addLegalFPImmediate(APFloat(-0.0f)); // FLD0/FCHS
656 addLegalFPImmediate(APFloat(-1.0f)); // FLD1/FCHS
659 // We don't support FMA.
660 setOperationAction(ISD::FMA, MVT::f64, Expand);
661 setOperationAction(ISD::FMA, MVT::f32, Expand);
663 // Long double always uses X87.
664 if (!TM.Options.UseSoftFloat) {
665 addRegisterClass(MVT::f80, &X86::RFP80RegClass);
666 setOperationAction(ISD::UNDEF, MVT::f80, Expand);
667 setOperationAction(ISD::FCOPYSIGN, MVT::f80, Expand);
669 APFloat TmpFlt = APFloat::getZero(APFloat::x87DoubleExtended);
670 addLegalFPImmediate(TmpFlt); // FLD0
672 addLegalFPImmediate(TmpFlt); // FLD0/FCHS
675 APFloat TmpFlt2(+1.0);
676 TmpFlt2.convert(APFloat::x87DoubleExtended, APFloat::rmNearestTiesToEven,
678 addLegalFPImmediate(TmpFlt2); // FLD1
679 TmpFlt2.changeSign();
680 addLegalFPImmediate(TmpFlt2); // FLD1/FCHS
683 if (!TM.Options.UnsafeFPMath) {
684 setOperationAction(ISD::FSIN , MVT::f80 , Expand);
685 setOperationAction(ISD::FCOS , MVT::f80 , Expand);
688 setOperationAction(ISD::FFLOOR, MVT::f80, Expand);
689 setOperationAction(ISD::FCEIL, MVT::f80, Expand);
690 setOperationAction(ISD::FTRUNC, MVT::f80, Expand);
691 setOperationAction(ISD::FRINT, MVT::f80, Expand);
692 setOperationAction(ISD::FNEARBYINT, MVT::f80, Expand);
693 setOperationAction(ISD::FMA, MVT::f80, Expand);
696 // Always use a library call for pow.
697 setOperationAction(ISD::FPOW , MVT::f32 , Expand);
698 setOperationAction(ISD::FPOW , MVT::f64 , Expand);
699 setOperationAction(ISD::FPOW , MVT::f80 , Expand);
701 setOperationAction(ISD::FLOG, MVT::f80, Expand);
702 setOperationAction(ISD::FLOG2, MVT::f80, Expand);
703 setOperationAction(ISD::FLOG10, MVT::f80, Expand);
704 setOperationAction(ISD::FEXP, MVT::f80, Expand);
705 setOperationAction(ISD::FEXP2, MVT::f80, Expand);
707 // First set operation action for all vector types to either promote
708 // (for widening) or expand (for scalarization). Then we will selectively
709 // turn on ones that can be effectively codegen'd.
710 for (int VT = MVT::FIRST_VECTOR_VALUETYPE;
711 VT <= MVT::LAST_VECTOR_VALUETYPE; ++VT) {
712 setOperationAction(ISD::ADD , (MVT::SimpleValueType)VT, Expand);
713 setOperationAction(ISD::SUB , (MVT::SimpleValueType)VT, Expand);
714 setOperationAction(ISD::FADD, (MVT::SimpleValueType)VT, Expand);
715 setOperationAction(ISD::FNEG, (MVT::SimpleValueType)VT, Expand);
716 setOperationAction(ISD::FSUB, (MVT::SimpleValueType)VT, Expand);
717 setOperationAction(ISD::MUL , (MVT::SimpleValueType)VT, Expand);
718 setOperationAction(ISD::FMUL, (MVT::SimpleValueType)VT, Expand);
719 setOperationAction(ISD::SDIV, (MVT::SimpleValueType)VT, Expand);
720 setOperationAction(ISD::UDIV, (MVT::SimpleValueType)VT, Expand);
721 setOperationAction(ISD::FDIV, (MVT::SimpleValueType)VT, Expand);
722 setOperationAction(ISD::SREM, (MVT::SimpleValueType)VT, Expand);
723 setOperationAction(ISD::UREM, (MVT::SimpleValueType)VT, Expand);
724 setOperationAction(ISD::LOAD, (MVT::SimpleValueType)VT, Expand);
725 setOperationAction(ISD::VECTOR_SHUFFLE, (MVT::SimpleValueType)VT, Expand);
726 setOperationAction(ISD::EXTRACT_VECTOR_ELT,(MVT::SimpleValueType)VT,Expand);
727 setOperationAction(ISD::INSERT_VECTOR_ELT,(MVT::SimpleValueType)VT, Expand);
728 setOperationAction(ISD::EXTRACT_SUBVECTOR,(MVT::SimpleValueType)VT,Expand);
729 setOperationAction(ISD::INSERT_SUBVECTOR,(MVT::SimpleValueType)VT,Expand);
730 setOperationAction(ISD::FABS, (MVT::SimpleValueType)VT, Expand);
731 setOperationAction(ISD::FSIN, (MVT::SimpleValueType)VT, Expand);
732 setOperationAction(ISD::FCOS, (MVT::SimpleValueType)VT, Expand);
733 setOperationAction(ISD::FREM, (MVT::SimpleValueType)VT, Expand);
734 setOperationAction(ISD::FMA, (MVT::SimpleValueType)VT, Expand);
735 setOperationAction(ISD::FPOWI, (MVT::SimpleValueType)VT, Expand);
736 setOperationAction(ISD::FSQRT, (MVT::SimpleValueType)VT, Expand);
737 setOperationAction(ISD::FCOPYSIGN, (MVT::SimpleValueType)VT, Expand);
738 setOperationAction(ISD::SMUL_LOHI, (MVT::SimpleValueType)VT, Expand);
739 setOperationAction(ISD::UMUL_LOHI, (MVT::SimpleValueType)VT, Expand);
740 setOperationAction(ISD::SDIVREM, (MVT::SimpleValueType)VT, Expand);
741 setOperationAction(ISD::UDIVREM, (MVT::SimpleValueType)VT, Expand);
742 setOperationAction(ISD::FPOW, (MVT::SimpleValueType)VT, Expand);
743 setOperationAction(ISD::CTPOP, (MVT::SimpleValueType)VT, Expand);
744 setOperationAction(ISD::CTTZ, (MVT::SimpleValueType)VT, Expand);
745 setOperationAction(ISD::CTTZ_ZERO_UNDEF, (MVT::SimpleValueType)VT, Expand);
746 setOperationAction(ISD::CTLZ, (MVT::SimpleValueType)VT, Expand);
747 setOperationAction(ISD::CTLZ_ZERO_UNDEF, (MVT::SimpleValueType)VT, Expand);
748 setOperationAction(ISD::SHL, (MVT::SimpleValueType)VT, Expand);
749 setOperationAction(ISD::SRA, (MVT::SimpleValueType)VT, Expand);
750 setOperationAction(ISD::SRL, (MVT::SimpleValueType)VT, Expand);
751 setOperationAction(ISD::ROTL, (MVT::SimpleValueType)VT, Expand);
752 setOperationAction(ISD::ROTR, (MVT::SimpleValueType)VT, Expand);
753 setOperationAction(ISD::BSWAP, (MVT::SimpleValueType)VT, Expand);
754 setOperationAction(ISD::SETCC, (MVT::SimpleValueType)VT, Expand);
755 setOperationAction(ISD::FLOG, (MVT::SimpleValueType)VT, Expand);
756 setOperationAction(ISD::FLOG2, (MVT::SimpleValueType)VT, Expand);
757 setOperationAction(ISD::FLOG10, (MVT::SimpleValueType)VT, Expand);
758 setOperationAction(ISD::FEXP, (MVT::SimpleValueType)VT, Expand);
759 setOperationAction(ISD::FEXP2, (MVT::SimpleValueType)VT, Expand);
760 setOperationAction(ISD::FP_TO_UINT, (MVT::SimpleValueType)VT, Expand);
761 setOperationAction(ISD::FP_TO_SINT, (MVT::SimpleValueType)VT, Expand);
762 setOperationAction(ISD::UINT_TO_FP, (MVT::SimpleValueType)VT, Expand);
763 setOperationAction(ISD::SINT_TO_FP, (MVT::SimpleValueType)VT, Expand);
764 setOperationAction(ISD::SIGN_EXTEND_INREG, (MVT::SimpleValueType)VT,Expand);
765 setOperationAction(ISD::TRUNCATE, (MVT::SimpleValueType)VT, Expand);
766 setOperationAction(ISD::SIGN_EXTEND, (MVT::SimpleValueType)VT, Expand);
767 setOperationAction(ISD::ZERO_EXTEND, (MVT::SimpleValueType)VT, Expand);
768 setOperationAction(ISD::ANY_EXTEND, (MVT::SimpleValueType)VT, Expand);
769 setOperationAction(ISD::VSELECT, (MVT::SimpleValueType)VT, Expand);
770 for (int InnerVT = MVT::FIRST_VECTOR_VALUETYPE;
771 InnerVT <= MVT::LAST_VECTOR_VALUETYPE; ++InnerVT)
772 setTruncStoreAction((MVT::SimpleValueType)VT,
773 (MVT::SimpleValueType)InnerVT, Expand);
774 setLoadExtAction(ISD::SEXTLOAD, (MVT::SimpleValueType)VT, Expand);
775 setLoadExtAction(ISD::ZEXTLOAD, (MVT::SimpleValueType)VT, Expand);
776 setLoadExtAction(ISD::EXTLOAD, (MVT::SimpleValueType)VT, Expand);
779 // FIXME: In order to prevent SSE instructions being expanded to MMX ones
780 // with -msoft-float, disable use of MMX as well.
781 if (!TM.Options.UseSoftFloat && Subtarget->hasMMX()) {
782 addRegisterClass(MVT::x86mmx, &X86::VR64RegClass);
783 // No operations on x86mmx supported, everything uses intrinsics.
786 // MMX-sized vectors (other than x86mmx) are expected to be expanded
787 // into smaller operations.
788 setOperationAction(ISD::MULHS, MVT::v8i8, Expand);
789 setOperationAction(ISD::MULHS, MVT::v4i16, Expand);
790 setOperationAction(ISD::MULHS, MVT::v2i32, Expand);
791 setOperationAction(ISD::MULHS, MVT::v1i64, Expand);
792 setOperationAction(ISD::AND, MVT::v8i8, Expand);
793 setOperationAction(ISD::AND, MVT::v4i16, Expand);
794 setOperationAction(ISD::AND, MVT::v2i32, Expand);
795 setOperationAction(ISD::AND, MVT::v1i64, Expand);
796 setOperationAction(ISD::OR, MVT::v8i8, Expand);
797 setOperationAction(ISD::OR, MVT::v4i16, Expand);
798 setOperationAction(ISD::OR, MVT::v2i32, Expand);
799 setOperationAction(ISD::OR, MVT::v1i64, Expand);
800 setOperationAction(ISD::XOR, MVT::v8i8, Expand);
801 setOperationAction(ISD::XOR, MVT::v4i16, Expand);
802 setOperationAction(ISD::XOR, MVT::v2i32, Expand);
803 setOperationAction(ISD::XOR, MVT::v1i64, Expand);
804 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i8, Expand);
805 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i16, Expand);
806 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2i32, Expand);
807 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v1i64, Expand);
808 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v1i64, Expand);
809 setOperationAction(ISD::SELECT, MVT::v8i8, Expand);
810 setOperationAction(ISD::SELECT, MVT::v4i16, Expand);
811 setOperationAction(ISD::SELECT, MVT::v2i32, Expand);
812 setOperationAction(ISD::SELECT, MVT::v1i64, Expand);
813 setOperationAction(ISD::BITCAST, MVT::v8i8, Expand);
814 setOperationAction(ISD::BITCAST, MVT::v4i16, Expand);
815 setOperationAction(ISD::BITCAST, MVT::v2i32, Expand);
816 setOperationAction(ISD::BITCAST, MVT::v1i64, Expand);
818 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE1()) {
819 addRegisterClass(MVT::v4f32, &X86::VR128RegClass);
821 setOperationAction(ISD::FADD, MVT::v4f32, Legal);
822 setOperationAction(ISD::FSUB, MVT::v4f32, Legal);
823 setOperationAction(ISD::FMUL, MVT::v4f32, Legal);
824 setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
825 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal);
826 setOperationAction(ISD::FNEG, MVT::v4f32, Custom);
827 setOperationAction(ISD::LOAD, MVT::v4f32, Legal);
828 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
829 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f32, Custom);
830 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
831 setOperationAction(ISD::SELECT, MVT::v4f32, Custom);
834 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE2()) {
835 addRegisterClass(MVT::v2f64, &X86::VR128RegClass);
837 // FIXME: Unfortunately -soft-float and -no-implicit-float means XMM
838 // registers cannot be used even for integer operations.
839 addRegisterClass(MVT::v16i8, &X86::VR128RegClass);
840 addRegisterClass(MVT::v8i16, &X86::VR128RegClass);
841 addRegisterClass(MVT::v4i32, &X86::VR128RegClass);
842 addRegisterClass(MVT::v2i64, &X86::VR128RegClass);
844 setOperationAction(ISD::ADD, MVT::v16i8, Legal);
845 setOperationAction(ISD::ADD, MVT::v8i16, Legal);
846 setOperationAction(ISD::ADD, MVT::v4i32, Legal);
847 setOperationAction(ISD::ADD, MVT::v2i64, Legal);
848 setOperationAction(ISD::MUL, MVT::v2i64, Custom);
849 setOperationAction(ISD::SUB, MVT::v16i8, Legal);
850 setOperationAction(ISD::SUB, MVT::v8i16, Legal);
851 setOperationAction(ISD::SUB, MVT::v4i32, Legal);
852 setOperationAction(ISD::SUB, MVT::v2i64, Legal);
853 setOperationAction(ISD::MUL, MVT::v8i16, Legal);
854 setOperationAction(ISD::FADD, MVT::v2f64, Legal);
855 setOperationAction(ISD::FSUB, MVT::v2f64, Legal);
856 setOperationAction(ISD::FMUL, MVT::v2f64, Legal);
857 setOperationAction(ISD::FDIV, MVT::v2f64, Legal);
858 setOperationAction(ISD::FSQRT, MVT::v2f64, Legal);
859 setOperationAction(ISD::FNEG, MVT::v2f64, Custom);
861 setOperationAction(ISD::SETCC, MVT::v2i64, Custom);
862 setOperationAction(ISD::SETCC, MVT::v16i8, Custom);
863 setOperationAction(ISD::SETCC, MVT::v8i16, Custom);
864 setOperationAction(ISD::SETCC, MVT::v4i32, Custom);
866 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Custom);
867 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Custom);
868 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
869 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
870 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
872 // Custom lower build_vector, vector_shuffle, and extract_vector_elt.
873 for (int i = MVT::v16i8; i != MVT::v2i64; ++i) {
874 MVT VT = (MVT::SimpleValueType)i;
875 // Do not attempt to custom lower non-power-of-2 vectors
876 if (!isPowerOf2_32(VT.getVectorNumElements()))
878 // Do not attempt to custom lower non-128-bit vectors
879 if (!VT.is128BitVector())
881 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
882 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
883 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
886 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f64, Custom);
887 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i64, Custom);
888 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Custom);
889 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Custom);
890 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f64, Custom);
891 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Custom);
893 if (Subtarget->is64Bit()) {
894 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
895 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
898 // Promote v16i8, v8i16, v4i32 load, select, and, or, xor to v2i64.
899 for (int i = MVT::v16i8; i != MVT::v2i64; ++i) {
900 MVT VT = (MVT::SimpleValueType)i;
902 // Do not attempt to promote non-128-bit vectors
903 if (!VT.is128BitVector())
906 setOperationAction(ISD::AND, VT, Promote);
907 AddPromotedToType (ISD::AND, VT, MVT::v2i64);
908 setOperationAction(ISD::OR, VT, Promote);
909 AddPromotedToType (ISD::OR, VT, MVT::v2i64);
910 setOperationAction(ISD::XOR, VT, Promote);
911 AddPromotedToType (ISD::XOR, VT, MVT::v2i64);
912 setOperationAction(ISD::LOAD, VT, Promote);
913 AddPromotedToType (ISD::LOAD, VT, MVT::v2i64);
914 setOperationAction(ISD::SELECT, VT, Promote);
915 AddPromotedToType (ISD::SELECT, VT, MVT::v2i64);
918 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
920 // Custom lower v2i64 and v2f64 selects.
921 setOperationAction(ISD::LOAD, MVT::v2f64, Legal);
922 setOperationAction(ISD::LOAD, MVT::v2i64, Legal);
923 setOperationAction(ISD::SELECT, MVT::v2f64, Custom);
924 setOperationAction(ISD::SELECT, MVT::v2i64, Custom);
926 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal);
927 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal);
930 if (Subtarget->hasSSE41()) {
931 setOperationAction(ISD::FFLOOR, MVT::f32, Legal);
932 setOperationAction(ISD::FCEIL, MVT::f32, Legal);
933 setOperationAction(ISD::FTRUNC, MVT::f32, Legal);
934 setOperationAction(ISD::FRINT, MVT::f32, Legal);
935 setOperationAction(ISD::FNEARBYINT, MVT::f32, Legal);
936 setOperationAction(ISD::FFLOOR, MVT::f64, Legal);
937 setOperationAction(ISD::FCEIL, MVT::f64, Legal);
938 setOperationAction(ISD::FTRUNC, MVT::f64, Legal);
939 setOperationAction(ISD::FRINT, MVT::f64, Legal);
940 setOperationAction(ISD::FNEARBYINT, MVT::f64, Legal);
942 // FIXME: Do we need to handle scalar-to-vector here?
943 setOperationAction(ISD::MUL, MVT::v4i32, Legal);
945 setOperationAction(ISD::VSELECT, MVT::v2f64, Legal);
946 setOperationAction(ISD::VSELECT, MVT::v2i64, Legal);
947 setOperationAction(ISD::VSELECT, MVT::v16i8, Legal);
948 setOperationAction(ISD::VSELECT, MVT::v4i32, Legal);
949 setOperationAction(ISD::VSELECT, MVT::v4f32, Legal);
951 // i8 and i16 vectors are custom , because the source register and source
952 // source memory operand types are not the same width. f32 vectors are
953 // custom since the immediate controlling the insert encodes additional
955 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i8, Custom);
956 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
957 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
958 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
960 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i8, Custom);
961 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i16, Custom);
962 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i32, Custom);
963 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
965 // FIXME: these should be Legal but thats only for the case where
966 // the index is constant. For now custom expand to deal with that.
967 if (Subtarget->is64Bit()) {
968 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
969 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
973 if (Subtarget->hasSSE2()) {
974 setOperationAction(ISD::SRL, MVT::v8i16, Custom);
975 setOperationAction(ISD::SRL, MVT::v16i8, Custom);
977 setOperationAction(ISD::SHL, MVT::v8i16, Custom);
978 setOperationAction(ISD::SHL, MVT::v16i8, Custom);
980 setOperationAction(ISD::SRA, MVT::v8i16, Custom);
981 setOperationAction(ISD::SRA, MVT::v16i8, Custom);
983 if (Subtarget->hasAVX2()) {
984 setOperationAction(ISD::SRL, MVT::v2i64, Legal);
985 setOperationAction(ISD::SRL, MVT::v4i32, Legal);
987 setOperationAction(ISD::SHL, MVT::v2i64, Legal);
988 setOperationAction(ISD::SHL, MVT::v4i32, Legal);
990 setOperationAction(ISD::SRA, MVT::v4i32, Legal);
992 setOperationAction(ISD::SRL, MVT::v2i64, Custom);
993 setOperationAction(ISD::SRL, MVT::v4i32, Custom);
995 setOperationAction(ISD::SHL, MVT::v2i64, Custom);
996 setOperationAction(ISD::SHL, MVT::v4i32, Custom);
998 setOperationAction(ISD::SRA, MVT::v4i32, Custom);
1002 if (!TM.Options.UseSoftFloat && Subtarget->hasAVX()) {
1003 addRegisterClass(MVT::v32i8, &X86::VR256RegClass);
1004 addRegisterClass(MVT::v16i16, &X86::VR256RegClass);
1005 addRegisterClass(MVT::v8i32, &X86::VR256RegClass);
1006 addRegisterClass(MVT::v8f32, &X86::VR256RegClass);
1007 addRegisterClass(MVT::v4i64, &X86::VR256RegClass);
1008 addRegisterClass(MVT::v4f64, &X86::VR256RegClass);
1010 setOperationAction(ISD::LOAD, MVT::v8f32, Legal);
1011 setOperationAction(ISD::LOAD, MVT::v4f64, Legal);
1012 setOperationAction(ISD::LOAD, MVT::v4i64, Legal);
1014 setOperationAction(ISD::FADD, MVT::v8f32, Legal);
1015 setOperationAction(ISD::FSUB, MVT::v8f32, Legal);
1016 setOperationAction(ISD::FMUL, MVT::v8f32, Legal);
1017 setOperationAction(ISD::FDIV, MVT::v8f32, Legal);
1018 setOperationAction(ISD::FSQRT, MVT::v8f32, Legal);
1019 setOperationAction(ISD::FNEG, MVT::v8f32, Custom);
1021 setOperationAction(ISD::FADD, MVT::v4f64, Legal);
1022 setOperationAction(ISD::FSUB, MVT::v4f64, Legal);
1023 setOperationAction(ISD::FMUL, MVT::v4f64, Legal);
1024 setOperationAction(ISD::FDIV, MVT::v4f64, Legal);
1025 setOperationAction(ISD::FSQRT, MVT::v4f64, Legal);
1026 setOperationAction(ISD::FNEG, MVT::v4f64, Custom);
1028 setOperationAction(ISD::FP_TO_SINT, MVT::v8i32, Legal);
1029 setOperationAction(ISD::SINT_TO_FP, MVT::v8i32, Legal);
1030 setOperationAction(ISD::FP_ROUND, MVT::v4f32, Legal);
1032 setOperationAction(ISD::SRL, MVT::v16i16, Custom);
1033 setOperationAction(ISD::SRL, MVT::v32i8, Custom);
1035 setOperationAction(ISD::SHL, MVT::v16i16, Custom);
1036 setOperationAction(ISD::SHL, MVT::v32i8, Custom);
1038 setOperationAction(ISD::SRA, MVT::v16i16, Custom);
1039 setOperationAction(ISD::SRA, MVT::v32i8, Custom);
1041 setOperationAction(ISD::SETCC, MVT::v32i8, Custom);
1042 setOperationAction(ISD::SETCC, MVT::v16i16, Custom);
1043 setOperationAction(ISD::SETCC, MVT::v8i32, Custom);
1044 setOperationAction(ISD::SETCC, MVT::v4i64, Custom);
1046 setOperationAction(ISD::SELECT, MVT::v4f64, Custom);
1047 setOperationAction(ISD::SELECT, MVT::v4i64, Custom);
1048 setOperationAction(ISD::SELECT, MVT::v8f32, Custom);
1050 setOperationAction(ISD::VSELECT, MVT::v4f64, Legal);
1051 setOperationAction(ISD::VSELECT, MVT::v4i64, Legal);
1052 setOperationAction(ISD::VSELECT, MVT::v8i32, Legal);
1053 setOperationAction(ISD::VSELECT, MVT::v8f32, Legal);
1055 if (Subtarget->hasFMA()) {
1056 setOperationAction(ISD::FMA, MVT::v8f32, Custom);
1057 setOperationAction(ISD::FMA, MVT::v4f64, Custom);
1058 setOperationAction(ISD::FMA, MVT::v4f32, Custom);
1059 setOperationAction(ISD::FMA, MVT::v2f64, Custom);
1060 setOperationAction(ISD::FMA, MVT::f32, Custom);
1061 setOperationAction(ISD::FMA, MVT::f64, Custom);
1064 if (Subtarget->hasAVX2()) {
1065 setOperationAction(ISD::ADD, MVT::v4i64, Legal);
1066 setOperationAction(ISD::ADD, MVT::v8i32, Legal);
1067 setOperationAction(ISD::ADD, MVT::v16i16, Legal);
1068 setOperationAction(ISD::ADD, MVT::v32i8, Legal);
1070 setOperationAction(ISD::SUB, MVT::v4i64, Legal);
1071 setOperationAction(ISD::SUB, MVT::v8i32, Legal);
1072 setOperationAction(ISD::SUB, MVT::v16i16, Legal);
1073 setOperationAction(ISD::SUB, MVT::v32i8, Legal);
1075 setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1076 setOperationAction(ISD::MUL, MVT::v8i32, Legal);
1077 setOperationAction(ISD::MUL, MVT::v16i16, Legal);
1078 // Don't lower v32i8 because there is no 128-bit byte mul
1080 setOperationAction(ISD::VSELECT, MVT::v32i8, Legal);
1082 setOperationAction(ISD::SRL, MVT::v4i64, Legal);
1083 setOperationAction(ISD::SRL, MVT::v8i32, Legal);
1085 setOperationAction(ISD::SHL, MVT::v4i64, Legal);
1086 setOperationAction(ISD::SHL, MVT::v8i32, Legal);
1088 setOperationAction(ISD::SRA, MVT::v8i32, Legal);
1090 setOperationAction(ISD::ADD, MVT::v4i64, Custom);
1091 setOperationAction(ISD::ADD, MVT::v8i32, Custom);
1092 setOperationAction(ISD::ADD, MVT::v16i16, Custom);
1093 setOperationAction(ISD::ADD, MVT::v32i8, Custom);
1095 setOperationAction(ISD::SUB, MVT::v4i64, Custom);
1096 setOperationAction(ISD::SUB, MVT::v8i32, Custom);
1097 setOperationAction(ISD::SUB, MVT::v16i16, Custom);
1098 setOperationAction(ISD::SUB, MVT::v32i8, Custom);
1100 setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1101 setOperationAction(ISD::MUL, MVT::v8i32, Custom);
1102 setOperationAction(ISD::MUL, MVT::v16i16, Custom);
1103 // Don't lower v32i8 because there is no 128-bit byte mul
1105 setOperationAction(ISD::SRL, MVT::v4i64, Custom);
1106 setOperationAction(ISD::SRL, MVT::v8i32, Custom);
1108 setOperationAction(ISD::SHL, MVT::v4i64, Custom);
1109 setOperationAction(ISD::SHL, MVT::v8i32, Custom);
1111 setOperationAction(ISD::SRA, MVT::v8i32, Custom);
1114 // Custom lower several nodes for 256-bit types.
1115 for (int i = MVT::FIRST_VECTOR_VALUETYPE;
1116 i <= MVT::LAST_VECTOR_VALUETYPE; ++i) {
1117 MVT VT = (MVT::SimpleValueType)i;
1119 // Extract subvector is special because the value type
1120 // (result) is 128-bit but the source is 256-bit wide.
1121 if (VT.is128BitVector())
1122 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom);
1124 // Do not attempt to custom lower other non-256-bit vectors
1125 if (!VT.is256BitVector())
1128 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1129 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1130 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
1131 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1132 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom);
1133 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom);
1134 setOperationAction(ISD::CONCAT_VECTORS, VT, Custom);
1137 // Promote v32i8, v16i16, v8i32 select, and, or, xor to v4i64.
1138 for (int i = MVT::v32i8; i != MVT::v4i64; ++i) {
1139 MVT VT = (MVT::SimpleValueType)i;
1141 // Do not attempt to promote non-256-bit vectors
1142 if (!VT.is256BitVector())
1145 setOperationAction(ISD::AND, VT, Promote);
1146 AddPromotedToType (ISD::AND, VT, MVT::v4i64);
1147 setOperationAction(ISD::OR, VT, Promote);
1148 AddPromotedToType (ISD::OR, VT, MVT::v4i64);
1149 setOperationAction(ISD::XOR, VT, Promote);
1150 AddPromotedToType (ISD::XOR, VT, MVT::v4i64);
1151 setOperationAction(ISD::LOAD, VT, Promote);
1152 AddPromotedToType (ISD::LOAD, VT, MVT::v4i64);
1153 setOperationAction(ISD::SELECT, VT, Promote);
1154 AddPromotedToType (ISD::SELECT, VT, MVT::v4i64);
1158 // SIGN_EXTEND_INREGs are evaluated by the extend type. Handle the expansion
1159 // of this type with custom code.
1160 for (int VT = MVT::FIRST_VECTOR_VALUETYPE;
1161 VT != MVT::LAST_VECTOR_VALUETYPE; VT++) {
1162 setOperationAction(ISD::SIGN_EXTEND_INREG, (MVT::SimpleValueType)VT,
1166 // We want to custom lower some of our intrinsics.
1167 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
1168 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::Other, Custom);
1171 // Only custom-lower 64-bit SADDO and friends on 64-bit because we don't
1172 // handle type legalization for these operations here.
1174 // FIXME: We really should do custom legalization for addition and
1175 // subtraction on x86-32 once PR3203 is fixed. We really can't do much better
1176 // than generic legalization for 64-bit multiplication-with-overflow, though.
1177 for (unsigned i = 0, e = 3+Subtarget->is64Bit(); i != e; ++i) {
1178 // Add/Sub/Mul with overflow operations are custom lowered.
1180 setOperationAction(ISD::SADDO, VT, Custom);
1181 setOperationAction(ISD::UADDO, VT, Custom);
1182 setOperationAction(ISD::SSUBO, VT, Custom);
1183 setOperationAction(ISD::USUBO, VT, Custom);
1184 setOperationAction(ISD::SMULO, VT, Custom);
1185 setOperationAction(ISD::UMULO, VT, Custom);
1188 // There are no 8-bit 3-address imul/mul instructions
1189 setOperationAction(ISD::SMULO, MVT::i8, Expand);
1190 setOperationAction(ISD::UMULO, MVT::i8, Expand);
1192 if (!Subtarget->is64Bit()) {
1193 // These libcalls are not available in 32-bit.
1194 setLibcallName(RTLIB::SHL_I128, 0);
1195 setLibcallName(RTLIB::SRL_I128, 0);
1196 setLibcallName(RTLIB::SRA_I128, 0);
1199 // We have target-specific dag combine patterns for the following nodes:
1200 setTargetDAGCombine(ISD::VECTOR_SHUFFLE);
1201 setTargetDAGCombine(ISD::EXTRACT_VECTOR_ELT);
1202 setTargetDAGCombine(ISD::VSELECT);
1203 setTargetDAGCombine(ISD::SELECT);
1204 setTargetDAGCombine(ISD::SHL);
1205 setTargetDAGCombine(ISD::SRA);
1206 setTargetDAGCombine(ISD::SRL);
1207 setTargetDAGCombine(ISD::OR);
1208 setTargetDAGCombine(ISD::AND);
1209 setTargetDAGCombine(ISD::ADD);
1210 setTargetDAGCombine(ISD::FADD);
1211 setTargetDAGCombine(ISD::FSUB);
1212 setTargetDAGCombine(ISD::FMA);
1213 setTargetDAGCombine(ISD::SUB);
1214 setTargetDAGCombine(ISD::LOAD);
1215 setTargetDAGCombine(ISD::STORE);
1216 setTargetDAGCombine(ISD::ZERO_EXTEND);
1217 setTargetDAGCombine(ISD::ANY_EXTEND);
1218 setTargetDAGCombine(ISD::SIGN_EXTEND);
1219 setTargetDAGCombine(ISD::TRUNCATE);
1220 setTargetDAGCombine(ISD::UINT_TO_FP);
1221 setTargetDAGCombine(ISD::SINT_TO_FP);
1222 setTargetDAGCombine(ISD::SETCC);
1223 setTargetDAGCombine(ISD::FP_TO_SINT);
1224 if (Subtarget->is64Bit())
1225 setTargetDAGCombine(ISD::MUL);
1226 setTargetDAGCombine(ISD::XOR);
1228 computeRegisterProperties();
1230 // On Darwin, -Os means optimize for size without hurting performance,
1231 // do not reduce the limit.
1232 maxStoresPerMemset = 16; // For @llvm.memset -> sequence of stores
1233 maxStoresPerMemsetOptSize = Subtarget->isTargetDarwin() ? 16 : 8;
1234 maxStoresPerMemcpy = 8; // For @llvm.memcpy -> sequence of stores
1235 maxStoresPerMemcpyOptSize = Subtarget->isTargetDarwin() ? 8 : 4;
1236 maxStoresPerMemmove = 8; // For @llvm.memmove -> sequence of stores
1237 maxStoresPerMemmoveOptSize = Subtarget->isTargetDarwin() ? 8 : 4;
1238 setPrefLoopAlignment(4); // 2^4 bytes.
1239 benefitFromCodePlacementOpt = true;
1241 // Predictable cmov don't hurt on atom because it's in-order.
1242 predictableSelectIsExpensive = !Subtarget->isAtom();
1244 setPrefFunctionAlignment(4); // 2^4 bytes.
1248 EVT X86TargetLowering::getSetCCResultType(EVT VT) const {
1249 if (!VT.isVector()) return MVT::i8;
1250 return VT.changeVectorElementTypeToInteger();
1254 /// getMaxByValAlign - Helper for getByValTypeAlignment to determine
1255 /// the desired ByVal argument alignment.
1256 static void getMaxByValAlign(Type *Ty, unsigned &MaxAlign) {
1259 if (VectorType *VTy = dyn_cast<VectorType>(Ty)) {
1260 if (VTy->getBitWidth() == 128)
1262 } else if (ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
1263 unsigned EltAlign = 0;
1264 getMaxByValAlign(ATy->getElementType(), EltAlign);
1265 if (EltAlign > MaxAlign)
1266 MaxAlign = EltAlign;
1267 } else if (StructType *STy = dyn_cast<StructType>(Ty)) {
1268 for (unsigned i = 0, e = STy->getNumElements(); i != e; ++i) {
1269 unsigned EltAlign = 0;
1270 getMaxByValAlign(STy->getElementType(i), EltAlign);
1271 if (EltAlign > MaxAlign)
1272 MaxAlign = EltAlign;
1279 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
1280 /// function arguments in the caller parameter area. For X86, aggregates
1281 /// that contain SSE vectors are placed at 16-byte boundaries while the rest
1282 /// are at 4-byte boundaries.
1283 unsigned X86TargetLowering::getByValTypeAlignment(Type *Ty) const {
1284 if (Subtarget->is64Bit()) {
1285 // Max of 8 and alignment of type.
1286 unsigned TyAlign = TD->getABITypeAlignment(Ty);
1293 if (Subtarget->hasSSE1())
1294 getMaxByValAlign(Ty, Align);
1298 /// getOptimalMemOpType - Returns the target specific optimal type for load
1299 /// and store operations as a result of memset, memcpy, and memmove
1300 /// lowering. If DstAlign is zero that means it's safe to destination
1301 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
1302 /// means there isn't a need to check it against alignment requirement,
1303 /// probably because the source does not need to be loaded. If
1304 /// 'IsZeroVal' is true, that means it's safe to return a
1305 /// non-scalar-integer type, e.g. empty string source, constant, or loaded
1306 /// from memory. 'MemcpyStrSrc' indicates whether the memcpy source is
1307 /// constant so it does not need to be loaded.
1308 /// It returns EVT::Other if the type should be determined using generic
1309 /// target-independent logic.
1311 X86TargetLowering::getOptimalMemOpType(uint64_t Size,
1312 unsigned DstAlign, unsigned SrcAlign,
1315 MachineFunction &MF) const {
1316 // FIXME: This turns off use of xmm stores for memset/memcpy on targets like
1317 // linux. This is because the stack realignment code can't handle certain
1318 // cases like PR2962. This should be removed when PR2962 is fixed.
1319 const Function *F = MF.getFunction();
1321 !F->hasFnAttr(Attribute::NoImplicitFloat)) {
1323 (Subtarget->isUnalignedMemAccessFast() ||
1324 ((DstAlign == 0 || DstAlign >= 16) &&
1325 (SrcAlign == 0 || SrcAlign >= 16))) &&
1326 Subtarget->getStackAlignment() >= 16) {
1327 if (Subtarget->getStackAlignment() >= 32) {
1328 if (Subtarget->hasAVX2())
1330 if (Subtarget->hasAVX())
1333 if (Subtarget->hasSSE2())
1335 if (Subtarget->hasSSE1())
1337 } else if (!MemcpyStrSrc && Size >= 8 &&
1338 !Subtarget->is64Bit() &&
1339 Subtarget->getStackAlignment() >= 8 &&
1340 Subtarget->hasSSE2()) {
1341 // Do not use f64 to lower memcpy if source is string constant. It's
1342 // better to use i32 to avoid the loads.
1346 if (Subtarget->is64Bit() && Size >= 8)
1351 /// getJumpTableEncoding - Return the entry encoding for a jump table in the
1352 /// current function. The returned value is a member of the
1353 /// MachineJumpTableInfo::JTEntryKind enum.
1354 unsigned X86TargetLowering::getJumpTableEncoding() const {
1355 // In GOT pic mode, each entry in the jump table is emitted as a @GOTOFF
1357 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1358 Subtarget->isPICStyleGOT())
1359 return MachineJumpTableInfo::EK_Custom32;
1361 // Otherwise, use the normal jump table encoding heuristics.
1362 return TargetLowering::getJumpTableEncoding();
1366 X86TargetLowering::LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI,
1367 const MachineBasicBlock *MBB,
1368 unsigned uid,MCContext &Ctx) const{
1369 assert(getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1370 Subtarget->isPICStyleGOT());
1371 // In 32-bit ELF systems, our jump table entries are formed with @GOTOFF
1373 return MCSymbolRefExpr::Create(MBB->getSymbol(),
1374 MCSymbolRefExpr::VK_GOTOFF, Ctx);
1377 /// getPICJumpTableRelocaBase - Returns relocation base for the given PIC
1379 SDValue X86TargetLowering::getPICJumpTableRelocBase(SDValue Table,
1380 SelectionDAG &DAG) const {
1381 if (!Subtarget->is64Bit())
1382 // This doesn't have DebugLoc associated with it, but is not really the
1383 // same as a Register.
1384 return DAG.getNode(X86ISD::GlobalBaseReg, DebugLoc(), getPointerTy());
1388 /// getPICJumpTableRelocBaseExpr - This returns the relocation base for the
1389 /// given PIC jumptable, the same as getPICJumpTableRelocBase, but as an
1391 const MCExpr *X86TargetLowering::
1392 getPICJumpTableRelocBaseExpr(const MachineFunction *MF, unsigned JTI,
1393 MCContext &Ctx) const {
1394 // X86-64 uses RIP relative addressing based on the jump table label.
1395 if (Subtarget->isPICStyleRIPRel())
1396 return TargetLowering::getPICJumpTableRelocBaseExpr(MF, JTI, Ctx);
1398 // Otherwise, the reference is relative to the PIC base.
1399 return MCSymbolRefExpr::Create(MF->getPICBaseSymbol(), Ctx);
1402 // FIXME: Why this routine is here? Move to RegInfo!
1403 std::pair<const TargetRegisterClass*, uint8_t>
1404 X86TargetLowering::findRepresentativeClass(EVT VT) const{
1405 const TargetRegisterClass *RRC = 0;
1407 switch (VT.getSimpleVT().SimpleTy) {
1409 return TargetLowering::findRepresentativeClass(VT);
1410 case MVT::i8: case MVT::i16: case MVT::i32: case MVT::i64:
1411 RRC = Subtarget->is64Bit() ?
1412 (const TargetRegisterClass*)&X86::GR64RegClass :
1413 (const TargetRegisterClass*)&X86::GR32RegClass;
1416 RRC = &X86::VR64RegClass;
1418 case MVT::f32: case MVT::f64:
1419 case MVT::v16i8: case MVT::v8i16: case MVT::v4i32: case MVT::v2i64:
1420 case MVT::v4f32: case MVT::v2f64:
1421 case MVT::v32i8: case MVT::v8i32: case MVT::v4i64: case MVT::v8f32:
1423 RRC = &X86::VR128RegClass;
1426 return std::make_pair(RRC, Cost);
1429 bool X86TargetLowering::getStackCookieLocation(unsigned &AddressSpace,
1430 unsigned &Offset) const {
1431 if (!Subtarget->isTargetLinux())
1434 if (Subtarget->is64Bit()) {
1435 // %fs:0x28, unless we're using a Kernel code model, in which case it's %gs:
1437 if (getTargetMachine().getCodeModel() == CodeModel::Kernel)
1450 //===----------------------------------------------------------------------===//
1451 // Return Value Calling Convention Implementation
1452 //===----------------------------------------------------------------------===//
1454 #include "X86GenCallingConv.inc"
1457 X86TargetLowering::CanLowerReturn(CallingConv::ID CallConv,
1458 MachineFunction &MF, bool isVarArg,
1459 const SmallVectorImpl<ISD::OutputArg> &Outs,
1460 LLVMContext &Context) const {
1461 SmallVector<CCValAssign, 16> RVLocs;
1462 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(),
1464 return CCInfo.CheckReturn(Outs, RetCC_X86);
1468 X86TargetLowering::LowerReturn(SDValue Chain,
1469 CallingConv::ID CallConv, bool isVarArg,
1470 const SmallVectorImpl<ISD::OutputArg> &Outs,
1471 const SmallVectorImpl<SDValue> &OutVals,
1472 DebugLoc dl, SelectionDAG &DAG) const {
1473 MachineFunction &MF = DAG.getMachineFunction();
1474 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1476 SmallVector<CCValAssign, 16> RVLocs;
1477 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(),
1478 RVLocs, *DAG.getContext());
1479 CCInfo.AnalyzeReturn(Outs, RetCC_X86);
1481 // Add the regs to the liveout set for the function.
1482 MachineRegisterInfo &MRI = DAG.getMachineFunction().getRegInfo();
1483 for (unsigned i = 0; i != RVLocs.size(); ++i)
1484 if (RVLocs[i].isRegLoc() && !MRI.isLiveOut(RVLocs[i].getLocReg()))
1485 MRI.addLiveOut(RVLocs[i].getLocReg());
1489 SmallVector<SDValue, 6> RetOps;
1490 RetOps.push_back(Chain); // Operand #0 = Chain (updated below)
1491 // Operand #1 = Bytes To Pop
1492 RetOps.push_back(DAG.getTargetConstant(FuncInfo->getBytesToPopOnReturn(),
1495 // Copy the result values into the output registers.
1496 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1497 CCValAssign &VA = RVLocs[i];
1498 assert(VA.isRegLoc() && "Can only return in registers!");
1499 SDValue ValToCopy = OutVals[i];
1500 EVT ValVT = ValToCopy.getValueType();
1502 // Promote values to the appropriate types
1503 if (VA.getLocInfo() == CCValAssign::SExt)
1504 ValToCopy = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), ValToCopy);
1505 else if (VA.getLocInfo() == CCValAssign::ZExt)
1506 ValToCopy = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), ValToCopy);
1507 else if (VA.getLocInfo() == CCValAssign::AExt)
1508 ValToCopy = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), ValToCopy);
1509 else if (VA.getLocInfo() == CCValAssign::BCvt)
1510 ValToCopy = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), ValToCopy);
1512 // If this is x86-64, and we disabled SSE, we can't return FP values,
1513 // or SSE or MMX vectors.
1514 if ((ValVT == MVT::f32 || ValVT == MVT::f64 ||
1515 VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) &&
1516 (Subtarget->is64Bit() && !Subtarget->hasSSE1())) {
1517 report_fatal_error("SSE register return with SSE disabled");
1519 // Likewise we can't return F64 values with SSE1 only. gcc does so, but
1520 // llvm-gcc has never done it right and no one has noticed, so this
1521 // should be OK for now.
1522 if (ValVT == MVT::f64 &&
1523 (Subtarget->is64Bit() && !Subtarget->hasSSE2()))
1524 report_fatal_error("SSE2 register return with SSE2 disabled");
1526 // Returns in ST0/ST1 are handled specially: these are pushed as operands to
1527 // the RET instruction and handled by the FP Stackifier.
1528 if (VA.getLocReg() == X86::ST0 ||
1529 VA.getLocReg() == X86::ST1) {
1530 // If this is a copy from an xmm register to ST(0), use an FPExtend to
1531 // change the value to the FP stack register class.
1532 if (isScalarFPTypeInSSEReg(VA.getValVT()))
1533 ValToCopy = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f80, ValToCopy);
1534 RetOps.push_back(ValToCopy);
1535 // Don't emit a copytoreg.
1539 // 64-bit vector (MMX) values are returned in XMM0 / XMM1 except for v1i64
1540 // which is returned in RAX / RDX.
1541 if (Subtarget->is64Bit()) {
1542 if (ValVT == MVT::x86mmx) {
1543 if (VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) {
1544 ValToCopy = DAG.getNode(ISD::BITCAST, dl, MVT::i64, ValToCopy);
1545 ValToCopy = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
1547 // If we don't have SSE2 available, convert to v4f32 so the generated
1548 // register is legal.
1549 if (!Subtarget->hasSSE2())
1550 ValToCopy = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32,ValToCopy);
1555 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), ValToCopy, Flag);
1556 Flag = Chain.getValue(1);
1559 // The x86-64 ABI for returning structs by value requires that we copy
1560 // the sret argument into %rax for the return. We saved the argument into
1561 // a virtual register in the entry block, so now we copy the value out
1563 if (Subtarget->is64Bit() &&
1564 DAG.getMachineFunction().getFunction()->hasStructRetAttr()) {
1565 MachineFunction &MF = DAG.getMachineFunction();
1566 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1567 unsigned Reg = FuncInfo->getSRetReturnReg();
1569 "SRetReturnReg should have been set in LowerFormalArguments().");
1570 SDValue Val = DAG.getCopyFromReg(Chain, dl, Reg, getPointerTy());
1572 Chain = DAG.getCopyToReg(Chain, dl, X86::RAX, Val, Flag);
1573 Flag = Chain.getValue(1);
1575 // RAX now acts like a return value.
1576 MRI.addLiveOut(X86::RAX);
1579 RetOps[0] = Chain; // Update chain.
1581 // Add the flag if we have it.
1583 RetOps.push_back(Flag);
1585 return DAG.getNode(X86ISD::RET_FLAG, dl,
1586 MVT::Other, &RetOps[0], RetOps.size());
1589 bool X86TargetLowering::isUsedByReturnOnly(SDNode *N, SDValue &Chain) const {
1590 if (N->getNumValues() != 1)
1592 if (!N->hasNUsesOfValue(1, 0))
1595 SDValue TCChain = Chain;
1596 SDNode *Copy = *N->use_begin();
1597 if (Copy->getOpcode() == ISD::CopyToReg) {
1598 // If the copy has a glue operand, we conservatively assume it isn't safe to
1599 // perform a tail call.
1600 if (Copy->getOperand(Copy->getNumOperands()-1).getValueType() == MVT::Glue)
1602 TCChain = Copy->getOperand(0);
1603 } else if (Copy->getOpcode() != ISD::FP_EXTEND)
1606 bool HasRet = false;
1607 for (SDNode::use_iterator UI = Copy->use_begin(), UE = Copy->use_end();
1609 if (UI->getOpcode() != X86ISD::RET_FLAG)
1622 X86TargetLowering::getTypeForExtArgOrReturn(LLVMContext &Context, EVT VT,
1623 ISD::NodeType ExtendKind) const {
1625 // TODO: Is this also valid on 32-bit?
1626 if (Subtarget->is64Bit() && VT == MVT::i1 && ExtendKind == ISD::ZERO_EXTEND)
1627 ReturnMVT = MVT::i8;
1629 ReturnMVT = MVT::i32;
1631 EVT MinVT = getRegisterType(Context, ReturnMVT);
1632 return VT.bitsLT(MinVT) ? MinVT : VT;
1635 /// LowerCallResult - Lower the result values of a call into the
1636 /// appropriate copies out of appropriate physical registers.
1639 X86TargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
1640 CallingConv::ID CallConv, bool isVarArg,
1641 const SmallVectorImpl<ISD::InputArg> &Ins,
1642 DebugLoc dl, SelectionDAG &DAG,
1643 SmallVectorImpl<SDValue> &InVals) const {
1645 // Assign locations to each value returned by this call.
1646 SmallVector<CCValAssign, 16> RVLocs;
1647 bool Is64Bit = Subtarget->is64Bit();
1648 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
1649 getTargetMachine(), RVLocs, *DAG.getContext());
1650 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
1652 // Copy all of the result registers out of their specified physreg.
1653 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1654 CCValAssign &VA = RVLocs[i];
1655 EVT CopyVT = VA.getValVT();
1657 // If this is x86-64, and we disabled SSE, we can't return FP values
1658 if ((CopyVT == MVT::f32 || CopyVT == MVT::f64) &&
1659 ((Is64Bit || Ins[i].Flags.isInReg()) && !Subtarget->hasSSE1())) {
1660 report_fatal_error("SSE register return with SSE disabled");
1665 // If this is a call to a function that returns an fp value on the floating
1666 // point stack, we must guarantee the value is popped from the stack, so
1667 // a CopyFromReg is not good enough - the copy instruction may be eliminated
1668 // if the return value is not used. We use the FpPOP_RETVAL instruction
1670 if (VA.getLocReg() == X86::ST0 || VA.getLocReg() == X86::ST1) {
1671 // If we prefer to use the value in xmm registers, copy it out as f80 and
1672 // use a truncate to move it from fp stack reg to xmm reg.
1673 if (isScalarFPTypeInSSEReg(VA.getValVT())) CopyVT = MVT::f80;
1674 SDValue Ops[] = { Chain, InFlag };
1675 Chain = SDValue(DAG.getMachineNode(X86::FpPOP_RETVAL, dl, CopyVT,
1676 MVT::Other, MVT::Glue, Ops, 2), 1);
1677 Val = Chain.getValue(0);
1679 // Round the f80 to the right size, which also moves it to the appropriate
1681 if (CopyVT != VA.getValVT())
1682 Val = DAG.getNode(ISD::FP_ROUND, dl, VA.getValVT(), Val,
1683 // This truncation won't change the value.
1684 DAG.getIntPtrConstant(1));
1686 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(),
1687 CopyVT, InFlag).getValue(1);
1688 Val = Chain.getValue(0);
1690 InFlag = Chain.getValue(2);
1691 InVals.push_back(Val);
1698 //===----------------------------------------------------------------------===//
1699 // C & StdCall & Fast Calling Convention implementation
1700 //===----------------------------------------------------------------------===//
1701 // StdCall calling convention seems to be standard for many Windows' API
1702 // routines and around. It differs from C calling convention just a little:
1703 // callee should clean up the stack, not caller. Symbols should be also
1704 // decorated in some fancy way :) It doesn't support any vector arguments.
1705 // For info on fast calling convention see Fast Calling Convention (tail call)
1706 // implementation LowerX86_32FastCCCallTo.
1708 /// CallIsStructReturn - Determines whether a call uses struct return
1710 enum StructReturnType {
1715 static StructReturnType
1716 callIsStructReturn(const SmallVectorImpl<ISD::OutputArg> &Outs) {
1718 return NotStructReturn;
1720 const ISD::ArgFlagsTy &Flags = Outs[0].Flags;
1721 if (!Flags.isSRet())
1722 return NotStructReturn;
1723 if (Flags.isInReg())
1724 return RegStructReturn;
1725 return StackStructReturn;
1728 /// ArgsAreStructReturn - Determines whether a function uses struct
1729 /// return semantics.
1730 static StructReturnType
1731 argsAreStructReturn(const SmallVectorImpl<ISD::InputArg> &Ins) {
1733 return NotStructReturn;
1735 const ISD::ArgFlagsTy &Flags = Ins[0].Flags;
1736 if (!Flags.isSRet())
1737 return NotStructReturn;
1738 if (Flags.isInReg())
1739 return RegStructReturn;
1740 return StackStructReturn;
1743 /// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified
1744 /// by "Src" to address "Dst" with size and alignment information specified by
1745 /// the specific parameter attribute. The copy will be passed as a byval
1746 /// function parameter.
1748 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
1749 ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
1751 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32);
1753 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
1754 /*isVolatile*/false, /*AlwaysInline=*/true,
1755 MachinePointerInfo(), MachinePointerInfo());
1758 /// IsTailCallConvention - Return true if the calling convention is one that
1759 /// supports tail call optimization.
1760 static bool IsTailCallConvention(CallingConv::ID CC) {
1761 return (CC == CallingConv::Fast || CC == CallingConv::GHC);
1764 bool X86TargetLowering::mayBeEmittedAsTailCall(CallInst *CI) const {
1765 if (!CI->isTailCall() || getTargetMachine().Options.DisableTailCalls)
1769 CallingConv::ID CalleeCC = CS.getCallingConv();
1770 if (!IsTailCallConvention(CalleeCC) && CalleeCC != CallingConv::C)
1776 /// FuncIsMadeTailCallSafe - Return true if the function is being made into
1777 /// a tailcall target by changing its ABI.
1778 static bool FuncIsMadeTailCallSafe(CallingConv::ID CC,
1779 bool GuaranteedTailCallOpt) {
1780 return GuaranteedTailCallOpt && IsTailCallConvention(CC);
1784 X86TargetLowering::LowerMemArgument(SDValue Chain,
1785 CallingConv::ID CallConv,
1786 const SmallVectorImpl<ISD::InputArg> &Ins,
1787 DebugLoc dl, SelectionDAG &DAG,
1788 const CCValAssign &VA,
1789 MachineFrameInfo *MFI,
1791 // Create the nodes corresponding to a load from this parameter slot.
1792 ISD::ArgFlagsTy Flags = Ins[i].Flags;
1793 bool AlwaysUseMutable = FuncIsMadeTailCallSafe(CallConv,
1794 getTargetMachine().Options.GuaranteedTailCallOpt);
1795 bool isImmutable = !AlwaysUseMutable && !Flags.isByVal();
1798 // If value is passed by pointer we have address passed instead of the value
1800 if (VA.getLocInfo() == CCValAssign::Indirect)
1801 ValVT = VA.getLocVT();
1803 ValVT = VA.getValVT();
1805 // FIXME: For now, all byval parameter objects are marked mutable. This can be
1806 // changed with more analysis.
1807 // In case of tail call optimization mark all arguments mutable. Since they
1808 // could be overwritten by lowering of arguments in case of a tail call.
1809 if (Flags.isByVal()) {
1810 unsigned Bytes = Flags.getByValSize();
1811 if (Bytes == 0) Bytes = 1; // Don't create zero-sized stack objects.
1812 int FI = MFI->CreateFixedObject(Bytes, VA.getLocMemOffset(), isImmutable);
1813 return DAG.getFrameIndex(FI, getPointerTy());
1815 int FI = MFI->CreateFixedObject(ValVT.getSizeInBits()/8,
1816 VA.getLocMemOffset(), isImmutable);
1817 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
1818 return DAG.getLoad(ValVT, dl, Chain, FIN,
1819 MachinePointerInfo::getFixedStack(FI),
1820 false, false, false, 0);
1825 X86TargetLowering::LowerFormalArguments(SDValue Chain,
1826 CallingConv::ID CallConv,
1828 const SmallVectorImpl<ISD::InputArg> &Ins,
1831 SmallVectorImpl<SDValue> &InVals)
1833 MachineFunction &MF = DAG.getMachineFunction();
1834 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1836 const Function* Fn = MF.getFunction();
1837 if (Fn->hasExternalLinkage() &&
1838 Subtarget->isTargetCygMing() &&
1839 Fn->getName() == "main")
1840 FuncInfo->setForceFramePointer(true);
1842 MachineFrameInfo *MFI = MF.getFrameInfo();
1843 bool Is64Bit = Subtarget->is64Bit();
1844 bool IsWindows = Subtarget->isTargetWindows();
1845 bool IsWin64 = Subtarget->isTargetWin64();
1847 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
1848 "Var args not supported with calling convention fastcc or ghc");
1850 // Assign locations to all of the incoming arguments.
1851 SmallVector<CCValAssign, 16> ArgLocs;
1852 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(),
1853 ArgLocs, *DAG.getContext());
1855 // Allocate shadow area for Win64
1857 CCInfo.AllocateStack(32, 8);
1860 CCInfo.AnalyzeFormalArguments(Ins, CC_X86);
1862 unsigned LastVal = ~0U;
1864 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1865 CCValAssign &VA = ArgLocs[i];
1866 // TODO: If an arg is passed in two places (e.g. reg and stack), skip later
1868 assert(VA.getValNo() != LastVal &&
1869 "Don't support value assigned to multiple locs yet");
1871 LastVal = VA.getValNo();
1873 if (VA.isRegLoc()) {
1874 EVT RegVT = VA.getLocVT();
1875 const TargetRegisterClass *RC;
1876 if (RegVT == MVT::i32)
1877 RC = &X86::GR32RegClass;
1878 else if (Is64Bit && RegVT == MVT::i64)
1879 RC = &X86::GR64RegClass;
1880 else if (RegVT == MVT::f32)
1881 RC = &X86::FR32RegClass;
1882 else if (RegVT == MVT::f64)
1883 RC = &X86::FR64RegClass;
1884 else if (RegVT.is256BitVector())
1885 RC = &X86::VR256RegClass;
1886 else if (RegVT.is128BitVector())
1887 RC = &X86::VR128RegClass;
1888 else if (RegVT == MVT::x86mmx)
1889 RC = &X86::VR64RegClass;
1891 llvm_unreachable("Unknown argument type!");
1893 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
1894 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
1896 // If this is an 8 or 16-bit value, it is really passed promoted to 32
1897 // bits. Insert an assert[sz]ext to capture this, then truncate to the
1899 if (VA.getLocInfo() == CCValAssign::SExt)
1900 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
1901 DAG.getValueType(VA.getValVT()));
1902 else if (VA.getLocInfo() == CCValAssign::ZExt)
1903 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
1904 DAG.getValueType(VA.getValVT()));
1905 else if (VA.getLocInfo() == CCValAssign::BCvt)
1906 ArgValue = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), ArgValue);
1908 if (VA.isExtInLoc()) {
1909 // Handle MMX values passed in XMM regs.
1910 if (RegVT.isVector()) {
1911 ArgValue = DAG.getNode(X86ISD::MOVDQ2Q, dl, VA.getValVT(),
1914 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
1917 assert(VA.isMemLoc());
1918 ArgValue = LowerMemArgument(Chain, CallConv, Ins, dl, DAG, VA, MFI, i);
1921 // If value is passed via pointer - do a load.
1922 if (VA.getLocInfo() == CCValAssign::Indirect)
1923 ArgValue = DAG.getLoad(VA.getValVT(), dl, Chain, ArgValue,
1924 MachinePointerInfo(), false, false, false, 0);
1926 InVals.push_back(ArgValue);
1929 // The x86-64 ABI for returning structs by value requires that we copy
1930 // the sret argument into %rax for the return. Save the argument into
1931 // a virtual register so that we can access it from the return points.
1932 if (Is64Bit && MF.getFunction()->hasStructRetAttr()) {
1933 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1934 unsigned Reg = FuncInfo->getSRetReturnReg();
1936 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(MVT::i64));
1937 FuncInfo->setSRetReturnReg(Reg);
1939 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, InVals[0]);
1940 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain);
1943 unsigned StackSize = CCInfo.getNextStackOffset();
1944 // Align stack specially for tail calls.
1945 if (FuncIsMadeTailCallSafe(CallConv,
1946 MF.getTarget().Options.GuaranteedTailCallOpt))
1947 StackSize = GetAlignedArgumentStackSize(StackSize, DAG);
1949 // If the function takes variable number of arguments, make a frame index for
1950 // the start of the first vararg value... for expansion of llvm.va_start.
1952 if (Is64Bit || (CallConv != CallingConv::X86_FastCall &&
1953 CallConv != CallingConv::X86_ThisCall)) {
1954 FuncInfo->setVarArgsFrameIndex(MFI->CreateFixedObject(1, StackSize,true));
1957 unsigned TotalNumIntRegs = 0, TotalNumXMMRegs = 0;
1959 // FIXME: We should really autogenerate these arrays
1960 static const uint16_t GPR64ArgRegsWin64[] = {
1961 X86::RCX, X86::RDX, X86::R8, X86::R9
1963 static const uint16_t GPR64ArgRegs64Bit[] = {
1964 X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9
1966 static const uint16_t XMMArgRegs64Bit[] = {
1967 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
1968 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
1970 const uint16_t *GPR64ArgRegs;
1971 unsigned NumXMMRegs = 0;
1974 // The XMM registers which might contain var arg parameters are shadowed
1975 // in their paired GPR. So we only need to save the GPR to their home
1977 TotalNumIntRegs = 4;
1978 GPR64ArgRegs = GPR64ArgRegsWin64;
1980 TotalNumIntRegs = 6; TotalNumXMMRegs = 8;
1981 GPR64ArgRegs = GPR64ArgRegs64Bit;
1983 NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs64Bit,
1986 unsigned NumIntRegs = CCInfo.getFirstUnallocated(GPR64ArgRegs,
1989 bool NoImplicitFloatOps = Fn->hasFnAttr(Attribute::NoImplicitFloat);
1990 assert(!(NumXMMRegs && !Subtarget->hasSSE1()) &&
1991 "SSE register cannot be used when SSE is disabled!");
1992 assert(!(NumXMMRegs && MF.getTarget().Options.UseSoftFloat &&
1993 NoImplicitFloatOps) &&
1994 "SSE register cannot be used when SSE is disabled!");
1995 if (MF.getTarget().Options.UseSoftFloat || NoImplicitFloatOps ||
1996 !Subtarget->hasSSE1())
1997 // Kernel mode asks for SSE to be disabled, so don't push them
1999 TotalNumXMMRegs = 0;
2002 const TargetFrameLowering &TFI = *getTargetMachine().getFrameLowering();
2003 // Get to the caller-allocated home save location. Add 8 to account
2004 // for the return address.
2005 int HomeOffset = TFI.getOffsetOfLocalArea() + 8;
2006 FuncInfo->setRegSaveFrameIndex(
2007 MFI->CreateFixedObject(1, NumIntRegs * 8 + HomeOffset, false));
2008 // Fixup to set vararg frame on shadow area (4 x i64).
2010 FuncInfo->setVarArgsFrameIndex(FuncInfo->getRegSaveFrameIndex());
2012 // For X86-64, if there are vararg parameters that are passed via
2013 // registers, then we must store them to their spots on the stack so
2014 // they may be loaded by deferencing the result of va_next.
2015 FuncInfo->setVarArgsGPOffset(NumIntRegs * 8);
2016 FuncInfo->setVarArgsFPOffset(TotalNumIntRegs * 8 + NumXMMRegs * 16);
2017 FuncInfo->setRegSaveFrameIndex(
2018 MFI->CreateStackObject(TotalNumIntRegs * 8 + TotalNumXMMRegs * 16, 16,
2022 // Store the integer parameter registers.
2023 SmallVector<SDValue, 8> MemOps;
2024 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
2026 unsigned Offset = FuncInfo->getVarArgsGPOffset();
2027 for (; NumIntRegs != TotalNumIntRegs; ++NumIntRegs) {
2028 SDValue FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), RSFIN,
2029 DAG.getIntPtrConstant(Offset));
2030 unsigned VReg = MF.addLiveIn(GPR64ArgRegs[NumIntRegs],
2031 &X86::GR64RegClass);
2032 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64);
2034 DAG.getStore(Val.getValue(1), dl, Val, FIN,
2035 MachinePointerInfo::getFixedStack(
2036 FuncInfo->getRegSaveFrameIndex(), Offset),
2038 MemOps.push_back(Store);
2042 if (TotalNumXMMRegs != 0 && NumXMMRegs != TotalNumXMMRegs) {
2043 // Now store the XMM (fp + vector) parameter registers.
2044 SmallVector<SDValue, 11> SaveXMMOps;
2045 SaveXMMOps.push_back(Chain);
2047 unsigned AL = MF.addLiveIn(X86::AL, &X86::GR8RegClass);
2048 SDValue ALVal = DAG.getCopyFromReg(DAG.getEntryNode(), dl, AL, MVT::i8);
2049 SaveXMMOps.push_back(ALVal);
2051 SaveXMMOps.push_back(DAG.getIntPtrConstant(
2052 FuncInfo->getRegSaveFrameIndex()));
2053 SaveXMMOps.push_back(DAG.getIntPtrConstant(
2054 FuncInfo->getVarArgsFPOffset()));
2056 for (; NumXMMRegs != TotalNumXMMRegs; ++NumXMMRegs) {
2057 unsigned VReg = MF.addLiveIn(XMMArgRegs64Bit[NumXMMRegs],
2058 &X86::VR128RegClass);
2059 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::v4f32);
2060 SaveXMMOps.push_back(Val);
2062 MemOps.push_back(DAG.getNode(X86ISD::VASTART_SAVE_XMM_REGS, dl,
2064 &SaveXMMOps[0], SaveXMMOps.size()));
2067 if (!MemOps.empty())
2068 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
2069 &MemOps[0], MemOps.size());
2073 // Some CCs need callee pop.
2074 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg,
2075 MF.getTarget().Options.GuaranteedTailCallOpt)) {
2076 FuncInfo->setBytesToPopOnReturn(StackSize); // Callee pops everything.
2078 FuncInfo->setBytesToPopOnReturn(0); // Callee pops nothing.
2079 // If this is an sret function, the return should pop the hidden pointer.
2080 if (!Is64Bit && !IsTailCallConvention(CallConv) && !IsWindows &&
2081 argsAreStructReturn(Ins) == StackStructReturn)
2082 FuncInfo->setBytesToPopOnReturn(4);
2086 // RegSaveFrameIndex is X86-64 only.
2087 FuncInfo->setRegSaveFrameIndex(0xAAAAAAA);
2088 if (CallConv == CallingConv::X86_FastCall ||
2089 CallConv == CallingConv::X86_ThisCall)
2090 // fastcc functions can't have varargs.
2091 FuncInfo->setVarArgsFrameIndex(0xAAAAAAA);
2094 FuncInfo->setArgumentStackSize(StackSize);
2100 X86TargetLowering::LowerMemOpCallTo(SDValue Chain,
2101 SDValue StackPtr, SDValue Arg,
2102 DebugLoc dl, SelectionDAG &DAG,
2103 const CCValAssign &VA,
2104 ISD::ArgFlagsTy Flags) const {
2105 unsigned LocMemOffset = VA.getLocMemOffset();
2106 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
2107 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
2108 if (Flags.isByVal())
2109 return CreateCopyOfByValArgument(Arg, PtrOff, Chain, Flags, DAG, dl);
2111 return DAG.getStore(Chain, dl, Arg, PtrOff,
2112 MachinePointerInfo::getStack(LocMemOffset),
2116 /// EmitTailCallLoadRetAddr - Emit a load of return address if tail call
2117 /// optimization is performed and it is required.
2119 X86TargetLowering::EmitTailCallLoadRetAddr(SelectionDAG &DAG,
2120 SDValue &OutRetAddr, SDValue Chain,
2121 bool IsTailCall, bool Is64Bit,
2122 int FPDiff, DebugLoc dl) const {
2123 // Adjust the Return address stack slot.
2124 EVT VT = getPointerTy();
2125 OutRetAddr = getReturnAddressFrameIndex(DAG);
2127 // Load the "old" Return address.
2128 OutRetAddr = DAG.getLoad(VT, dl, Chain, OutRetAddr, MachinePointerInfo(),
2129 false, false, false, 0);
2130 return SDValue(OutRetAddr.getNode(), 1);
2133 /// EmitTailCallStoreRetAddr - Emit a store of the return address if tail call
2134 /// optimization is performed and it is required (FPDiff!=0).
2136 EmitTailCallStoreRetAddr(SelectionDAG & DAG, MachineFunction &MF,
2137 SDValue Chain, SDValue RetAddrFrIdx,
2138 bool Is64Bit, int FPDiff, DebugLoc dl) {
2139 // Store the return address to the appropriate stack slot.
2140 if (!FPDiff) return Chain;
2141 // Calculate the new stack slot for the return address.
2142 int SlotSize = Is64Bit ? 8 : 4;
2143 int NewReturnAddrFI =
2144 MF.getFrameInfo()->CreateFixedObject(SlotSize, FPDiff-SlotSize, false);
2145 EVT VT = Is64Bit ? MVT::i64 : MVT::i32;
2146 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewReturnAddrFI, VT);
2147 Chain = DAG.getStore(Chain, dl, RetAddrFrIdx, NewRetAddrFrIdx,
2148 MachinePointerInfo::getFixedStack(NewReturnAddrFI),
2154 X86TargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
2155 SmallVectorImpl<SDValue> &InVals) const {
2156 SelectionDAG &DAG = CLI.DAG;
2157 DebugLoc &dl = CLI.DL;
2158 SmallVector<ISD::OutputArg, 32> &Outs = CLI.Outs;
2159 SmallVector<SDValue, 32> &OutVals = CLI.OutVals;
2160 SmallVector<ISD::InputArg, 32> &Ins = CLI.Ins;
2161 SDValue Chain = CLI.Chain;
2162 SDValue Callee = CLI.Callee;
2163 CallingConv::ID CallConv = CLI.CallConv;
2164 bool &isTailCall = CLI.IsTailCall;
2165 bool isVarArg = CLI.IsVarArg;
2167 MachineFunction &MF = DAG.getMachineFunction();
2168 bool Is64Bit = Subtarget->is64Bit();
2169 bool IsWin64 = Subtarget->isTargetWin64();
2170 bool IsWindows = Subtarget->isTargetWindows();
2171 StructReturnType SR = callIsStructReturn(Outs);
2172 bool IsSibcall = false;
2174 if (MF.getTarget().Options.DisableTailCalls)
2178 // Check if it's really possible to do a tail call.
2179 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv,
2180 isVarArg, SR != NotStructReturn,
2181 MF.getFunction()->hasStructRetAttr(),
2182 Outs, OutVals, Ins, DAG);
2184 // Sibcalls are automatically detected tailcalls which do not require
2186 if (!MF.getTarget().Options.GuaranteedTailCallOpt && isTailCall)
2193 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
2194 "Var args not supported with calling convention fastcc or ghc");
2196 // Analyze operands of the call, assigning locations to each operand.
2197 SmallVector<CCValAssign, 16> ArgLocs;
2198 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(),
2199 ArgLocs, *DAG.getContext());
2201 // Allocate shadow area for Win64
2203 CCInfo.AllocateStack(32, 8);
2206 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
2208 // Get a count of how many bytes are to be pushed on the stack.
2209 unsigned NumBytes = CCInfo.getNextStackOffset();
2211 // This is a sibcall. The memory operands are available in caller's
2212 // own caller's stack.
2214 else if (getTargetMachine().Options.GuaranteedTailCallOpt &&
2215 IsTailCallConvention(CallConv))
2216 NumBytes = GetAlignedArgumentStackSize(NumBytes, DAG);
2219 if (isTailCall && !IsSibcall) {
2220 // Lower arguments at fp - stackoffset + fpdiff.
2221 unsigned NumBytesCallerPushed =
2222 MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn();
2223 FPDiff = NumBytesCallerPushed - NumBytes;
2225 // Set the delta of movement of the returnaddr stackslot.
2226 // But only set if delta is greater than previous delta.
2227 if (FPDiff < (MF.getInfo<X86MachineFunctionInfo>()->getTCReturnAddrDelta()))
2228 MF.getInfo<X86MachineFunctionInfo>()->setTCReturnAddrDelta(FPDiff);
2232 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true));
2234 SDValue RetAddrFrIdx;
2235 // Load return address for tail calls.
2236 if (isTailCall && FPDiff)
2237 Chain = EmitTailCallLoadRetAddr(DAG, RetAddrFrIdx, Chain, isTailCall,
2238 Is64Bit, FPDiff, dl);
2240 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
2241 SmallVector<SDValue, 8> MemOpChains;
2244 // Walk the register/memloc assignments, inserting copies/loads. In the case
2245 // of tail call optimization arguments are handle later.
2246 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2247 CCValAssign &VA = ArgLocs[i];
2248 EVT RegVT = VA.getLocVT();
2249 SDValue Arg = OutVals[i];
2250 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2251 bool isByVal = Flags.isByVal();
2253 // Promote the value if needed.
2254 switch (VA.getLocInfo()) {
2255 default: llvm_unreachable("Unknown loc info!");
2256 case CCValAssign::Full: break;
2257 case CCValAssign::SExt:
2258 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, RegVT, Arg);
2260 case CCValAssign::ZExt:
2261 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, RegVT, Arg);
2263 case CCValAssign::AExt:
2264 if (RegVT.is128BitVector()) {
2265 // Special case: passing MMX values in XMM registers.
2266 Arg = DAG.getNode(ISD::BITCAST, dl, MVT::i64, Arg);
2267 Arg = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, Arg);
2268 Arg = getMOVL(DAG, dl, MVT::v2i64, DAG.getUNDEF(MVT::v2i64), Arg);
2270 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, RegVT, Arg);
2272 case CCValAssign::BCvt:
2273 Arg = DAG.getNode(ISD::BITCAST, dl, RegVT, Arg);
2275 case CCValAssign::Indirect: {
2276 // Store the argument.
2277 SDValue SpillSlot = DAG.CreateStackTemporary(VA.getValVT());
2278 int FI = cast<FrameIndexSDNode>(SpillSlot)->getIndex();
2279 Chain = DAG.getStore(Chain, dl, Arg, SpillSlot,
2280 MachinePointerInfo::getFixedStack(FI),
2287 if (VA.isRegLoc()) {
2288 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
2289 if (isVarArg && IsWin64) {
2290 // Win64 ABI requires argument XMM reg to be copied to the corresponding
2291 // shadow reg if callee is a varargs function.
2292 unsigned ShadowReg = 0;
2293 switch (VA.getLocReg()) {
2294 case X86::XMM0: ShadowReg = X86::RCX; break;
2295 case X86::XMM1: ShadowReg = X86::RDX; break;
2296 case X86::XMM2: ShadowReg = X86::R8; break;
2297 case X86::XMM3: ShadowReg = X86::R9; break;
2300 RegsToPass.push_back(std::make_pair(ShadowReg, Arg));
2302 } else if (!IsSibcall && (!isTailCall || isByVal)) {
2303 assert(VA.isMemLoc());
2304 if (StackPtr.getNode() == 0)
2305 StackPtr = DAG.getCopyFromReg(Chain, dl, X86StackPtr, getPointerTy());
2306 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Arg,
2307 dl, DAG, VA, Flags));
2311 if (!MemOpChains.empty())
2312 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
2313 &MemOpChains[0], MemOpChains.size());
2315 if (Subtarget->isPICStyleGOT()) {
2316 // ELF / PIC requires GOT in the EBX register before function calls via PLT
2319 RegsToPass.push_back(std::make_pair(unsigned(X86::EBX),
2320 DAG.getNode(X86ISD::GlobalBaseReg, DebugLoc(), getPointerTy())));
2322 // If we are tail calling and generating PIC/GOT style code load the
2323 // address of the callee into ECX. The value in ecx is used as target of
2324 // the tail jump. This is done to circumvent the ebx/callee-saved problem
2325 // for tail calls on PIC/GOT architectures. Normally we would just put the
2326 // address of GOT into ebx and then call target@PLT. But for tail calls
2327 // ebx would be restored (since ebx is callee saved) before jumping to the
2330 // Note: The actual moving to ECX is done further down.
2331 GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee);
2332 if (G && !G->getGlobal()->hasHiddenVisibility() &&
2333 !G->getGlobal()->hasProtectedVisibility())
2334 Callee = LowerGlobalAddress(Callee, DAG);
2335 else if (isa<ExternalSymbolSDNode>(Callee))
2336 Callee = LowerExternalSymbol(Callee, DAG);
2340 if (Is64Bit && isVarArg && !IsWin64) {
2341 // From AMD64 ABI document:
2342 // For calls that may call functions that use varargs or stdargs
2343 // (prototype-less calls or calls to functions containing ellipsis (...) in
2344 // the declaration) %al is used as hidden argument to specify the number
2345 // of SSE registers used. The contents of %al do not need to match exactly
2346 // the number of registers, but must be an ubound on the number of SSE
2347 // registers used and is in the range 0 - 8 inclusive.
2349 // Count the number of XMM registers allocated.
2350 static const uint16_t XMMArgRegs[] = {
2351 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
2352 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
2354 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs, 8);
2355 assert((Subtarget->hasSSE1() || !NumXMMRegs)
2356 && "SSE registers cannot be used when SSE is disabled");
2358 RegsToPass.push_back(std::make_pair(unsigned(X86::AL),
2359 DAG.getConstant(NumXMMRegs, MVT::i8)));
2362 // For tail calls lower the arguments to the 'real' stack slot.
2364 // Force all the incoming stack arguments to be loaded from the stack
2365 // before any new outgoing arguments are stored to the stack, because the
2366 // outgoing stack slots may alias the incoming argument stack slots, and
2367 // the alias isn't otherwise explicit. This is slightly more conservative
2368 // than necessary, because it means that each store effectively depends
2369 // on every argument instead of just those arguments it would clobber.
2370 SDValue ArgChain = DAG.getStackArgumentTokenFactor(Chain);
2372 SmallVector<SDValue, 8> MemOpChains2;
2375 if (getTargetMachine().Options.GuaranteedTailCallOpt) {
2376 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2377 CCValAssign &VA = ArgLocs[i];
2380 assert(VA.isMemLoc());
2381 SDValue Arg = OutVals[i];
2382 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2383 // Create frame index.
2384 int32_t Offset = VA.getLocMemOffset()+FPDiff;
2385 uint32_t OpSize = (VA.getLocVT().getSizeInBits()+7)/8;
2386 FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true);
2387 FIN = DAG.getFrameIndex(FI, getPointerTy());
2389 if (Flags.isByVal()) {
2390 // Copy relative to framepointer.
2391 SDValue Source = DAG.getIntPtrConstant(VA.getLocMemOffset());
2392 if (StackPtr.getNode() == 0)
2393 StackPtr = DAG.getCopyFromReg(Chain, dl, X86StackPtr,
2395 Source = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, Source);
2397 MemOpChains2.push_back(CreateCopyOfByValArgument(Source, FIN,
2401 // Store relative to framepointer.
2402 MemOpChains2.push_back(
2403 DAG.getStore(ArgChain, dl, Arg, FIN,
2404 MachinePointerInfo::getFixedStack(FI),
2410 if (!MemOpChains2.empty())
2411 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
2412 &MemOpChains2[0], MemOpChains2.size());
2414 // Store the return address to the appropriate stack slot.
2415 Chain = EmitTailCallStoreRetAddr(DAG, MF, Chain, RetAddrFrIdx, Is64Bit,
2419 // Build a sequence of copy-to-reg nodes chained together with token chain
2420 // and flag operands which copy the outgoing args into registers.
2422 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
2423 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
2424 RegsToPass[i].second, InFlag);
2425 InFlag = Chain.getValue(1);
2428 if (getTargetMachine().getCodeModel() == CodeModel::Large) {
2429 assert(Is64Bit && "Large code model is only legal in 64-bit mode.");
2430 // In the 64-bit large code model, we have to make all calls
2431 // through a register, since the call instruction's 32-bit
2432 // pc-relative offset may not be large enough to hold the whole
2434 } else if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
2435 // If the callee is a GlobalAddress node (quite common, every direct call
2436 // is) turn it into a TargetGlobalAddress node so that legalize doesn't hack
2439 // We should use extra load for direct calls to dllimported functions in
2441 const GlobalValue *GV = G->getGlobal();
2442 if (!GV->hasDLLImportLinkage()) {
2443 unsigned char OpFlags = 0;
2444 bool ExtraLoad = false;
2445 unsigned WrapperKind = ISD::DELETED_NODE;
2447 // On ELF targets, in both X86-64 and X86-32 mode, direct calls to
2448 // external symbols most go through the PLT in PIC mode. If the symbol
2449 // has hidden or protected visibility, or if it is static or local, then
2450 // we don't need to use the PLT - we can directly call it.
2451 if (Subtarget->isTargetELF() &&
2452 getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
2453 GV->hasDefaultVisibility() && !GV->hasLocalLinkage()) {
2454 OpFlags = X86II::MO_PLT;
2455 } else if (Subtarget->isPICStyleStubAny() &&
2456 (GV->isDeclaration() || GV->isWeakForLinker()) &&
2457 (!Subtarget->getTargetTriple().isMacOSX() ||
2458 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
2459 // PC-relative references to external symbols should go through $stub,
2460 // unless we're building with the leopard linker or later, which
2461 // automatically synthesizes these stubs.
2462 OpFlags = X86II::MO_DARWIN_STUB;
2463 } else if (Subtarget->isPICStyleRIPRel() &&
2464 isa<Function>(GV) &&
2465 cast<Function>(GV)->hasFnAttr(Attribute::NonLazyBind)) {
2466 // If the function is marked as non-lazy, generate an indirect call
2467 // which loads from the GOT directly. This avoids runtime overhead
2468 // at the cost of eager binding (and one extra byte of encoding).
2469 OpFlags = X86II::MO_GOTPCREL;
2470 WrapperKind = X86ISD::WrapperRIP;
2474 Callee = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(),
2475 G->getOffset(), OpFlags);
2477 // Add a wrapper if needed.
2478 if (WrapperKind != ISD::DELETED_NODE)
2479 Callee = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Callee);
2480 // Add extra indirection if needed.
2482 Callee = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Callee,
2483 MachinePointerInfo::getGOT(),
2484 false, false, false, 0);
2486 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
2487 unsigned char OpFlags = 0;
2489 // On ELF targets, in either X86-64 or X86-32 mode, direct calls to
2490 // external symbols should go through the PLT.
2491 if (Subtarget->isTargetELF() &&
2492 getTargetMachine().getRelocationModel() == Reloc::PIC_) {
2493 OpFlags = X86II::MO_PLT;
2494 } else if (Subtarget->isPICStyleStubAny() &&
2495 (!Subtarget->getTargetTriple().isMacOSX() ||
2496 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
2497 // PC-relative references to external symbols should go through $stub,
2498 // unless we're building with the leopard linker or later, which
2499 // automatically synthesizes these stubs.
2500 OpFlags = X86II::MO_DARWIN_STUB;
2503 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy(),
2507 // Returns a chain & a flag for retval copy to use.
2508 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
2509 SmallVector<SDValue, 8> Ops;
2511 if (!IsSibcall && isTailCall) {
2512 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
2513 DAG.getIntPtrConstant(0, true), InFlag);
2514 InFlag = Chain.getValue(1);
2517 Ops.push_back(Chain);
2518 Ops.push_back(Callee);
2521 Ops.push_back(DAG.getConstant(FPDiff, MVT::i32));
2523 // Add argument registers to the end of the list so that they are known live
2525 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
2526 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
2527 RegsToPass[i].second.getValueType()));
2529 // Add a register mask operand representing the call-preserved registers.
2530 const TargetRegisterInfo *TRI = getTargetMachine().getRegisterInfo();
2531 const uint32_t *Mask = TRI->getCallPreservedMask(CallConv);
2532 assert(Mask && "Missing call preserved mask for calling convention");
2533 Ops.push_back(DAG.getRegisterMask(Mask));
2535 if (InFlag.getNode())
2536 Ops.push_back(InFlag);
2540 //// If this is the first return lowered for this function, add the regs
2541 //// to the liveout set for the function.
2542 // This isn't right, although it's probably harmless on x86; liveouts
2543 // should be computed from returns not tail calls. Consider a void
2544 // function making a tail call to a function returning int.
2545 return DAG.getNode(X86ISD::TC_RETURN, dl,
2546 NodeTys, &Ops[0], Ops.size());
2549 Chain = DAG.getNode(X86ISD::CALL, dl, NodeTys, &Ops[0], Ops.size());
2550 InFlag = Chain.getValue(1);
2552 // Create the CALLSEQ_END node.
2553 unsigned NumBytesForCalleeToPush;
2554 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg,
2555 getTargetMachine().Options.GuaranteedTailCallOpt))
2556 NumBytesForCalleeToPush = NumBytes; // Callee pops everything
2557 else if (!Is64Bit && !IsTailCallConvention(CallConv) && !IsWindows &&
2558 SR == StackStructReturn)
2559 // If this is a call to a struct-return function, the callee
2560 // pops the hidden struct pointer, so we have to push it back.
2561 // This is common for Darwin/X86, Linux & Mingw32 targets.
2562 // For MSVC Win32 targets, the caller pops the hidden struct pointer.
2563 NumBytesForCalleeToPush = 4;
2565 NumBytesForCalleeToPush = 0; // Callee pops nothing.
2567 // Returns a flag for retval copy to use.
2569 Chain = DAG.getCALLSEQ_END(Chain,
2570 DAG.getIntPtrConstant(NumBytes, true),
2571 DAG.getIntPtrConstant(NumBytesForCalleeToPush,
2574 InFlag = Chain.getValue(1);
2577 // Handle result values, copying them out of physregs into vregs that we
2579 return LowerCallResult(Chain, InFlag, CallConv, isVarArg,
2580 Ins, dl, DAG, InVals);
2584 //===----------------------------------------------------------------------===//
2585 // Fast Calling Convention (tail call) implementation
2586 //===----------------------------------------------------------------------===//
2588 // Like std call, callee cleans arguments, convention except that ECX is
2589 // reserved for storing the tail called function address. Only 2 registers are
2590 // free for argument passing (inreg). Tail call optimization is performed
2592 // * tailcallopt is enabled
2593 // * caller/callee are fastcc
2594 // On X86_64 architecture with GOT-style position independent code only local
2595 // (within module) calls are supported at the moment.
2596 // To keep the stack aligned according to platform abi the function
2597 // GetAlignedArgumentStackSize ensures that argument delta is always multiples
2598 // of stack alignment. (Dynamic linkers need this - darwin's dyld for example)
2599 // If a tail called function callee has more arguments than the caller the
2600 // caller needs to make sure that there is room to move the RETADDR to. This is
2601 // achieved by reserving an area the size of the argument delta right after the
2602 // original REtADDR, but before the saved framepointer or the spilled registers
2603 // e.g. caller(arg1, arg2) calls callee(arg1, arg2,arg3,arg4)
2615 /// GetAlignedArgumentStackSize - Make the stack size align e.g 16n + 12 aligned
2616 /// for a 16 byte align requirement.
2618 X86TargetLowering::GetAlignedArgumentStackSize(unsigned StackSize,
2619 SelectionDAG& DAG) const {
2620 MachineFunction &MF = DAG.getMachineFunction();
2621 const TargetMachine &TM = MF.getTarget();
2622 const TargetFrameLowering &TFI = *TM.getFrameLowering();
2623 unsigned StackAlignment = TFI.getStackAlignment();
2624 uint64_t AlignMask = StackAlignment - 1;
2625 int64_t Offset = StackSize;
2626 uint64_t SlotSize = TD->getPointerSize();
2627 if ( (Offset & AlignMask) <= (StackAlignment - SlotSize) ) {
2628 // Number smaller than 12 so just add the difference.
2629 Offset += ((StackAlignment - SlotSize) - (Offset & AlignMask));
2631 // Mask out lower bits, add stackalignment once plus the 12 bytes.
2632 Offset = ((~AlignMask) & Offset) + StackAlignment +
2633 (StackAlignment-SlotSize);
2638 /// MatchingStackOffset - Return true if the given stack call argument is
2639 /// already available in the same position (relatively) of the caller's
2640 /// incoming argument stack.
2642 bool MatchingStackOffset(SDValue Arg, unsigned Offset, ISD::ArgFlagsTy Flags,
2643 MachineFrameInfo *MFI, const MachineRegisterInfo *MRI,
2644 const X86InstrInfo *TII) {
2645 unsigned Bytes = Arg.getValueType().getSizeInBits() / 8;
2647 if (Arg.getOpcode() == ISD::CopyFromReg) {
2648 unsigned VR = cast<RegisterSDNode>(Arg.getOperand(1))->getReg();
2649 if (!TargetRegisterInfo::isVirtualRegister(VR))
2651 MachineInstr *Def = MRI->getVRegDef(VR);
2654 if (!Flags.isByVal()) {
2655 if (!TII->isLoadFromStackSlot(Def, FI))
2658 unsigned Opcode = Def->getOpcode();
2659 if ((Opcode == X86::LEA32r || Opcode == X86::LEA64r) &&
2660 Def->getOperand(1).isFI()) {
2661 FI = Def->getOperand(1).getIndex();
2662 Bytes = Flags.getByValSize();
2666 } else if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Arg)) {
2667 if (Flags.isByVal())
2668 // ByVal argument is passed in as a pointer but it's now being
2669 // dereferenced. e.g.
2670 // define @foo(%struct.X* %A) {
2671 // tail call @bar(%struct.X* byval %A)
2674 SDValue Ptr = Ld->getBasePtr();
2675 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr);
2678 FI = FINode->getIndex();
2679 } else if (Arg.getOpcode() == ISD::FrameIndex && Flags.isByVal()) {
2680 FrameIndexSDNode *FINode = cast<FrameIndexSDNode>(Arg);
2681 FI = FINode->getIndex();
2682 Bytes = Flags.getByValSize();
2686 assert(FI != INT_MAX);
2687 if (!MFI->isFixedObjectIndex(FI))
2689 return Offset == MFI->getObjectOffset(FI) && Bytes == MFI->getObjectSize(FI);
2692 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
2693 /// for tail call optimization. Targets which want to do tail call
2694 /// optimization should implement this function.
2696 X86TargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
2697 CallingConv::ID CalleeCC,
2699 bool isCalleeStructRet,
2700 bool isCallerStructRet,
2701 const SmallVectorImpl<ISD::OutputArg> &Outs,
2702 const SmallVectorImpl<SDValue> &OutVals,
2703 const SmallVectorImpl<ISD::InputArg> &Ins,
2704 SelectionDAG& DAG) const {
2705 if (!IsTailCallConvention(CalleeCC) &&
2706 CalleeCC != CallingConv::C)
2709 // If -tailcallopt is specified, make fastcc functions tail-callable.
2710 const MachineFunction &MF = DAG.getMachineFunction();
2711 const Function *CallerF = DAG.getMachineFunction().getFunction();
2712 CallingConv::ID CallerCC = CallerF->getCallingConv();
2713 bool CCMatch = CallerCC == CalleeCC;
2715 if (getTargetMachine().Options.GuaranteedTailCallOpt) {
2716 if (IsTailCallConvention(CalleeCC) && CCMatch)
2721 // Look for obvious safe cases to perform tail call optimization that do not
2722 // require ABI changes. This is what gcc calls sibcall.
2724 // Can't do sibcall if stack needs to be dynamically re-aligned. PEI needs to
2725 // emit a special epilogue.
2726 if (RegInfo->needsStackRealignment(MF))
2729 // Also avoid sibcall optimization if either caller or callee uses struct
2730 // return semantics.
2731 if (isCalleeStructRet || isCallerStructRet)
2734 // An stdcall caller is expected to clean up its arguments; the callee
2735 // isn't going to do that.
2736 if (!CCMatch && CallerCC==CallingConv::X86_StdCall)
2739 // Do not sibcall optimize vararg calls unless all arguments are passed via
2741 if (isVarArg && !Outs.empty()) {
2743 // Optimizing for varargs on Win64 is unlikely to be safe without
2744 // additional testing.
2745 if (Subtarget->isTargetWin64())
2748 SmallVector<CCValAssign, 16> ArgLocs;
2749 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(),
2750 getTargetMachine(), ArgLocs, *DAG.getContext());
2752 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
2753 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i)
2754 if (!ArgLocs[i].isRegLoc())
2758 // If the call result is in ST0 / ST1, it needs to be popped off the x87
2759 // stack. Therefore, if it's not used by the call it is not safe to optimize
2760 // this into a sibcall.
2761 bool Unused = false;
2762 for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
2769 SmallVector<CCValAssign, 16> RVLocs;
2770 CCState CCInfo(CalleeCC, false, DAG.getMachineFunction(),
2771 getTargetMachine(), RVLocs, *DAG.getContext());
2772 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
2773 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
2774 CCValAssign &VA = RVLocs[i];
2775 if (VA.getLocReg() == X86::ST0 || VA.getLocReg() == X86::ST1)
2780 // If the calling conventions do not match, then we'd better make sure the
2781 // results are returned in the same way as what the caller expects.
2783 SmallVector<CCValAssign, 16> RVLocs1;
2784 CCState CCInfo1(CalleeCC, false, DAG.getMachineFunction(),
2785 getTargetMachine(), RVLocs1, *DAG.getContext());
2786 CCInfo1.AnalyzeCallResult(Ins, RetCC_X86);
2788 SmallVector<CCValAssign, 16> RVLocs2;
2789 CCState CCInfo2(CallerCC, false, DAG.getMachineFunction(),
2790 getTargetMachine(), RVLocs2, *DAG.getContext());
2791 CCInfo2.AnalyzeCallResult(Ins, RetCC_X86);
2793 if (RVLocs1.size() != RVLocs2.size())
2795 for (unsigned i = 0, e = RVLocs1.size(); i != e; ++i) {
2796 if (RVLocs1[i].isRegLoc() != RVLocs2[i].isRegLoc())
2798 if (RVLocs1[i].getLocInfo() != RVLocs2[i].getLocInfo())
2800 if (RVLocs1[i].isRegLoc()) {
2801 if (RVLocs1[i].getLocReg() != RVLocs2[i].getLocReg())
2804 if (RVLocs1[i].getLocMemOffset() != RVLocs2[i].getLocMemOffset())
2810 // If the callee takes no arguments then go on to check the results of the
2812 if (!Outs.empty()) {
2813 // Check if stack adjustment is needed. For now, do not do this if any
2814 // argument is passed on the stack.
2815 SmallVector<CCValAssign, 16> ArgLocs;
2816 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(),
2817 getTargetMachine(), ArgLocs, *DAG.getContext());
2819 // Allocate shadow area for Win64
2820 if (Subtarget->isTargetWin64()) {
2821 CCInfo.AllocateStack(32, 8);
2824 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
2825 if (CCInfo.getNextStackOffset()) {
2826 MachineFunction &MF = DAG.getMachineFunction();
2827 if (MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn())
2830 // Check if the arguments are already laid out in the right way as
2831 // the caller's fixed stack objects.
2832 MachineFrameInfo *MFI = MF.getFrameInfo();
2833 const MachineRegisterInfo *MRI = &MF.getRegInfo();
2834 const X86InstrInfo *TII =
2835 ((X86TargetMachine&)getTargetMachine()).getInstrInfo();
2836 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2837 CCValAssign &VA = ArgLocs[i];
2838 SDValue Arg = OutVals[i];
2839 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2840 if (VA.getLocInfo() == CCValAssign::Indirect)
2842 if (!VA.isRegLoc()) {
2843 if (!MatchingStackOffset(Arg, VA.getLocMemOffset(), Flags,
2850 // If the tailcall address may be in a register, then make sure it's
2851 // possible to register allocate for it. In 32-bit, the call address can
2852 // only target EAX, EDX, or ECX since the tail call must be scheduled after
2853 // callee-saved registers are restored. These happen to be the same
2854 // registers used to pass 'inreg' arguments so watch out for those.
2855 if (!Subtarget->is64Bit() &&
2856 !isa<GlobalAddressSDNode>(Callee) &&
2857 !isa<ExternalSymbolSDNode>(Callee)) {
2858 unsigned NumInRegs = 0;
2859 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2860 CCValAssign &VA = ArgLocs[i];
2863 unsigned Reg = VA.getLocReg();
2866 case X86::EAX: case X86::EDX: case X86::ECX:
2867 if (++NumInRegs == 3)
2879 X86TargetLowering::createFastISel(FunctionLoweringInfo &funcInfo,
2880 const TargetLibraryInfo *libInfo) const {
2881 return X86::createFastISel(funcInfo, libInfo);
2885 //===----------------------------------------------------------------------===//
2886 // Other Lowering Hooks
2887 //===----------------------------------------------------------------------===//
2889 static bool MayFoldLoad(SDValue Op) {
2890 return Op.hasOneUse() && ISD::isNormalLoad(Op.getNode());
2893 static bool MayFoldIntoStore(SDValue Op) {
2894 return Op.hasOneUse() && ISD::isNormalStore(*Op.getNode()->use_begin());
2897 static bool isTargetShuffle(unsigned Opcode) {
2899 default: return false;
2900 case X86ISD::PSHUFD:
2901 case X86ISD::PSHUFHW:
2902 case X86ISD::PSHUFLW:
2904 case X86ISD::PALIGN:
2905 case X86ISD::MOVLHPS:
2906 case X86ISD::MOVLHPD:
2907 case X86ISD::MOVHLPS:
2908 case X86ISD::MOVLPS:
2909 case X86ISD::MOVLPD:
2910 case X86ISD::MOVSHDUP:
2911 case X86ISD::MOVSLDUP:
2912 case X86ISD::MOVDDUP:
2915 case X86ISD::UNPCKL:
2916 case X86ISD::UNPCKH:
2917 case X86ISD::VPERMILP:
2918 case X86ISD::VPERM2X128:
2919 case X86ISD::VPERMI:
2924 static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT,
2925 SDValue V1, SelectionDAG &DAG) {
2927 default: llvm_unreachable("Unknown x86 shuffle node");
2928 case X86ISD::MOVSHDUP:
2929 case X86ISD::MOVSLDUP:
2930 case X86ISD::MOVDDUP:
2931 return DAG.getNode(Opc, dl, VT, V1);
2935 static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT,
2936 SDValue V1, unsigned TargetMask,
2937 SelectionDAG &DAG) {
2939 default: llvm_unreachable("Unknown x86 shuffle node");
2940 case X86ISD::PSHUFD:
2941 case X86ISD::PSHUFHW:
2942 case X86ISD::PSHUFLW:
2943 case X86ISD::VPERMILP:
2944 case X86ISD::VPERMI:
2945 return DAG.getNode(Opc, dl, VT, V1, DAG.getConstant(TargetMask, MVT::i8));
2949 static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT,
2950 SDValue V1, SDValue V2, unsigned TargetMask,
2951 SelectionDAG &DAG) {
2953 default: llvm_unreachable("Unknown x86 shuffle node");
2954 case X86ISD::PALIGN:
2956 case X86ISD::VPERM2X128:
2957 return DAG.getNode(Opc, dl, VT, V1, V2,
2958 DAG.getConstant(TargetMask, MVT::i8));
2962 static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT,
2963 SDValue V1, SDValue V2, SelectionDAG &DAG) {
2965 default: llvm_unreachable("Unknown x86 shuffle node");
2966 case X86ISD::MOVLHPS:
2967 case X86ISD::MOVLHPD:
2968 case X86ISD::MOVHLPS:
2969 case X86ISD::MOVLPS:
2970 case X86ISD::MOVLPD:
2973 case X86ISD::UNPCKL:
2974 case X86ISD::UNPCKH:
2975 return DAG.getNode(Opc, dl, VT, V1, V2);
2979 SDValue X86TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) const {
2980 MachineFunction &MF = DAG.getMachineFunction();
2981 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
2982 int ReturnAddrIndex = FuncInfo->getRAIndex();
2984 if (ReturnAddrIndex == 0) {
2985 // Set up a frame object for the return address.
2986 uint64_t SlotSize = TD->getPointerSize();
2987 ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(SlotSize, -SlotSize,
2989 FuncInfo->setRAIndex(ReturnAddrIndex);
2992 return DAG.getFrameIndex(ReturnAddrIndex, getPointerTy());
2996 bool X86::isOffsetSuitableForCodeModel(int64_t Offset, CodeModel::Model M,
2997 bool hasSymbolicDisplacement) {
2998 // Offset should fit into 32 bit immediate field.
2999 if (!isInt<32>(Offset))
3002 // If we don't have a symbolic displacement - we don't have any extra
3004 if (!hasSymbolicDisplacement)
3007 // FIXME: Some tweaks might be needed for medium code model.
3008 if (M != CodeModel::Small && M != CodeModel::Kernel)
3011 // For small code model we assume that latest object is 16MB before end of 31
3012 // bits boundary. We may also accept pretty large negative constants knowing
3013 // that all objects are in the positive half of address space.
3014 if (M == CodeModel::Small && Offset < 16*1024*1024)
3017 // For kernel code model we know that all object resist in the negative half
3018 // of 32bits address space. We may not accept negative offsets, since they may
3019 // be just off and we may accept pretty large positive ones.
3020 if (M == CodeModel::Kernel && Offset > 0)
3026 /// isCalleePop - Determines whether the callee is required to pop its
3027 /// own arguments. Callee pop is necessary to support tail calls.
3028 bool X86::isCalleePop(CallingConv::ID CallingConv,
3029 bool is64Bit, bool IsVarArg, bool TailCallOpt) {
3033 switch (CallingConv) {
3036 case CallingConv::X86_StdCall:
3038 case CallingConv::X86_FastCall:
3040 case CallingConv::X86_ThisCall:
3042 case CallingConv::Fast:
3044 case CallingConv::GHC:
3049 /// TranslateX86CC - do a one to one translation of a ISD::CondCode to the X86
3050 /// specific condition code, returning the condition code and the LHS/RHS of the
3051 /// comparison to make.
3052 static unsigned TranslateX86CC(ISD::CondCode SetCCOpcode, bool isFP,
3053 SDValue &LHS, SDValue &RHS, SelectionDAG &DAG) {
3055 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
3056 if (SetCCOpcode == ISD::SETGT && RHSC->isAllOnesValue()) {
3057 // X > -1 -> X == 0, jump !sign.
3058 RHS = DAG.getConstant(0, RHS.getValueType());
3059 return X86::COND_NS;
3061 if (SetCCOpcode == ISD::SETLT && RHSC->isNullValue()) {
3062 // X < 0 -> X == 0, jump on sign.
3065 if (SetCCOpcode == ISD::SETLT && RHSC->getZExtValue() == 1) {
3067 RHS = DAG.getConstant(0, RHS.getValueType());
3068 return X86::COND_LE;
3072 switch (SetCCOpcode) {
3073 default: llvm_unreachable("Invalid integer condition!");
3074 case ISD::SETEQ: return X86::COND_E;
3075 case ISD::SETGT: return X86::COND_G;
3076 case ISD::SETGE: return X86::COND_GE;
3077 case ISD::SETLT: return X86::COND_L;
3078 case ISD::SETLE: return X86::COND_LE;
3079 case ISD::SETNE: return X86::COND_NE;
3080 case ISD::SETULT: return X86::COND_B;
3081 case ISD::SETUGT: return X86::COND_A;
3082 case ISD::SETULE: return X86::COND_BE;
3083 case ISD::SETUGE: return X86::COND_AE;
3087 // First determine if it is required or is profitable to flip the operands.
3089 // If LHS is a foldable load, but RHS is not, flip the condition.
3090 if (ISD::isNON_EXTLoad(LHS.getNode()) &&
3091 !ISD::isNON_EXTLoad(RHS.getNode())) {
3092 SetCCOpcode = getSetCCSwappedOperands(SetCCOpcode);
3093 std::swap(LHS, RHS);
3096 switch (SetCCOpcode) {
3102 std::swap(LHS, RHS);
3106 // On a floating point condition, the flags are set as follows:
3108 // 0 | 0 | 0 | X > Y
3109 // 0 | 0 | 1 | X < Y
3110 // 1 | 0 | 0 | X == Y
3111 // 1 | 1 | 1 | unordered
3112 switch (SetCCOpcode) {
3113 default: llvm_unreachable("Condcode should be pre-legalized away");
3115 case ISD::SETEQ: return X86::COND_E;
3116 case ISD::SETOLT: // flipped
3118 case ISD::SETGT: return X86::COND_A;
3119 case ISD::SETOLE: // flipped
3121 case ISD::SETGE: return X86::COND_AE;
3122 case ISD::SETUGT: // flipped
3124 case ISD::SETLT: return X86::COND_B;
3125 case ISD::SETUGE: // flipped
3127 case ISD::SETLE: return X86::COND_BE;
3129 case ISD::SETNE: return X86::COND_NE;
3130 case ISD::SETUO: return X86::COND_P;
3131 case ISD::SETO: return X86::COND_NP;
3133 case ISD::SETUNE: return X86::COND_INVALID;
3137 /// hasFPCMov - is there a floating point cmov for the specific X86 condition
3138 /// code. Current x86 isa includes the following FP cmov instructions:
3139 /// fcmovb, fcomvbe, fcomve, fcmovu, fcmovae, fcmova, fcmovne, fcmovnu.
3140 static bool hasFPCMov(unsigned X86CC) {
3156 /// isFPImmLegal - Returns true if the target can instruction select the
3157 /// specified FP immediate natively. If false, the legalizer will
3158 /// materialize the FP immediate as a load from a constant pool.
3159 bool X86TargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
3160 for (unsigned i = 0, e = LegalFPImmediates.size(); i != e; ++i) {
3161 if (Imm.bitwiseIsEqual(LegalFPImmediates[i]))
3167 /// isUndefOrInRange - Return true if Val is undef or if its value falls within
3168 /// the specified range (L, H].
3169 static bool isUndefOrInRange(int Val, int Low, int Hi) {
3170 return (Val < 0) || (Val >= Low && Val < Hi);
3173 /// isUndefOrEqual - Val is either less than zero (undef) or equal to the
3174 /// specified value.
3175 static bool isUndefOrEqual(int Val, int CmpVal) {
3176 if (Val < 0 || Val == CmpVal)
3181 /// isSequentialOrUndefInRange - Return true if every element in Mask, beginning
3182 /// from position Pos and ending in Pos+Size, falls within the specified
3183 /// sequential range (L, L+Pos]. or is undef.
3184 static bool isSequentialOrUndefInRange(ArrayRef<int> Mask,
3185 unsigned Pos, unsigned Size, int Low) {
3186 for (unsigned i = Pos, e = Pos+Size; i != e; ++i, ++Low)
3187 if (!isUndefOrEqual(Mask[i], Low))
3192 /// isPSHUFDMask - Return true if the node specifies a shuffle of elements that
3193 /// is suitable for input to PSHUFD or PSHUFW. That is, it doesn't reference
3194 /// the second operand.
3195 static bool isPSHUFDMask(ArrayRef<int> Mask, EVT VT) {
3196 if (VT == MVT::v4f32 || VT == MVT::v4i32 )
3197 return (Mask[0] < 4 && Mask[1] < 4 && Mask[2] < 4 && Mask[3] < 4);
3198 if (VT == MVT::v2f64 || VT == MVT::v2i64)
3199 return (Mask[0] < 2 && Mask[1] < 2);
3203 /// isPSHUFHWMask - Return true if the node specifies a shuffle of elements that
3204 /// is suitable for input to PSHUFHW.
3205 static bool isPSHUFHWMask(ArrayRef<int> Mask, EVT VT, bool HasAVX2) {
3206 if (VT != MVT::v8i16 && (!HasAVX2 || VT != MVT::v16i16))
3209 // Lower quadword copied in order or undef.
3210 if (!isSequentialOrUndefInRange(Mask, 0, 4, 0))
3213 // Upper quadword shuffled.
3214 for (unsigned i = 4; i != 8; ++i)
3215 if (!isUndefOrInRange(Mask[i], 4, 8))
3218 if (VT == MVT::v16i16) {
3219 // Lower quadword copied in order or undef.
3220 if (!isSequentialOrUndefInRange(Mask, 8, 4, 8))
3223 // Upper quadword shuffled.
3224 for (unsigned i = 12; i != 16; ++i)
3225 if (!isUndefOrInRange(Mask[i], 12, 16))
3232 /// isPSHUFLWMask - Return true if the node specifies a shuffle of elements that
3233 /// is suitable for input to PSHUFLW.
3234 static bool isPSHUFLWMask(ArrayRef<int> Mask, EVT VT, bool HasAVX2) {
3235 if (VT != MVT::v8i16 && (!HasAVX2 || VT != MVT::v16i16))
3238 // Upper quadword copied in order.
3239 if (!isSequentialOrUndefInRange(Mask, 4, 4, 4))
3242 // Lower quadword shuffled.
3243 for (unsigned i = 0; i != 4; ++i)
3244 if (!isUndefOrInRange(Mask[i], 0, 4))
3247 if (VT == MVT::v16i16) {
3248 // Upper quadword copied in order.
3249 if (!isSequentialOrUndefInRange(Mask, 12, 4, 12))
3252 // Lower quadword shuffled.
3253 for (unsigned i = 8; i != 12; ++i)
3254 if (!isUndefOrInRange(Mask[i], 8, 12))
3261 /// isPALIGNRMask - Return true if the node specifies a shuffle of elements that
3262 /// is suitable for input to PALIGNR.
3263 static bool isPALIGNRMask(ArrayRef<int> Mask, EVT VT,
3264 const X86Subtarget *Subtarget) {
3265 if ((VT.getSizeInBits() == 128 && !Subtarget->hasSSSE3()) ||
3266 (VT.getSizeInBits() == 256 && !Subtarget->hasAVX2()))
3269 unsigned NumElts = VT.getVectorNumElements();
3270 unsigned NumLanes = VT.getSizeInBits()/128;
3271 unsigned NumLaneElts = NumElts/NumLanes;
3273 // Do not handle 64-bit element shuffles with palignr.
3274 if (NumLaneElts == 2)
3277 for (unsigned l = 0; l != NumElts; l+=NumLaneElts) {
3279 for (i = 0; i != NumLaneElts; ++i) {
3284 // Lane is all undef, go to next lane
3285 if (i == NumLaneElts)
3288 int Start = Mask[i+l];
3290 // Make sure its in this lane in one of the sources
3291 if (!isUndefOrInRange(Start, l, l+NumLaneElts) &&
3292 !isUndefOrInRange(Start, l+NumElts, l+NumElts+NumLaneElts))
3295 // If not lane 0, then we must match lane 0
3296 if (l != 0 && Mask[i] >= 0 && !isUndefOrEqual(Start, Mask[i]+l))
3299 // Correct second source to be contiguous with first source
3300 if (Start >= (int)NumElts)
3301 Start -= NumElts - NumLaneElts;
3303 // Make sure we're shifting in the right direction.
3304 if (Start <= (int)(i+l))
3309 // Check the rest of the elements to see if they are consecutive.
3310 for (++i; i != NumLaneElts; ++i) {
3311 int Idx = Mask[i+l];
3313 // Make sure its in this lane
3314 if (!isUndefOrInRange(Idx, l, l+NumLaneElts) &&
3315 !isUndefOrInRange(Idx, l+NumElts, l+NumElts+NumLaneElts))
3318 // If not lane 0, then we must match lane 0
3319 if (l != 0 && Mask[i] >= 0 && !isUndefOrEqual(Idx, Mask[i]+l))
3322 if (Idx >= (int)NumElts)
3323 Idx -= NumElts - NumLaneElts;
3325 if (!isUndefOrEqual(Idx, Start+i))
3334 /// CommuteVectorShuffleMask - Change values in a shuffle permute mask assuming
3335 /// the two vector operands have swapped position.
3336 static void CommuteVectorShuffleMask(SmallVectorImpl<int> &Mask,
3337 unsigned NumElems) {
3338 for (unsigned i = 0; i != NumElems; ++i) {
3342 else if (idx < (int)NumElems)
3343 Mask[i] = idx + NumElems;
3345 Mask[i] = idx - NumElems;
3349 /// isSHUFPMask - Return true if the specified VECTOR_SHUFFLE operand
3350 /// specifies a shuffle of elements that is suitable for input to 128/256-bit
3351 /// SHUFPS and SHUFPD. If Commuted is true, then it checks for sources to be
3352 /// reverse of what x86 shuffles want.
3353 static bool isSHUFPMask(ArrayRef<int> Mask, EVT VT, bool HasAVX,
3354 bool Commuted = false) {
3355 if (!HasAVX && VT.getSizeInBits() == 256)
3358 unsigned NumElems = VT.getVectorNumElements();
3359 unsigned NumLanes = VT.getSizeInBits()/128;
3360 unsigned NumLaneElems = NumElems/NumLanes;
3362 if (NumLaneElems != 2 && NumLaneElems != 4)
3365 // VSHUFPSY divides the resulting vector into 4 chunks.
3366 // The sources are also splitted into 4 chunks, and each destination
3367 // chunk must come from a different source chunk.
3369 // SRC1 => X7 X6 X5 X4 X3 X2 X1 X0
3370 // SRC2 => Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y9
3372 // DST => Y7..Y4, Y7..Y4, X7..X4, X7..X4,
3373 // Y3..Y0, Y3..Y0, X3..X0, X3..X0
3375 // VSHUFPDY divides the resulting vector into 4 chunks.
3376 // The sources are also splitted into 4 chunks, and each destination
3377 // chunk must come from a different source chunk.
3379 // SRC1 => X3 X2 X1 X0
3380 // SRC2 => Y3 Y2 Y1 Y0
3382 // DST => Y3..Y2, X3..X2, Y1..Y0, X1..X0
3384 unsigned HalfLaneElems = NumLaneElems/2;
3385 for (unsigned l = 0; l != NumElems; l += NumLaneElems) {
3386 for (unsigned i = 0; i != NumLaneElems; ++i) {
3387 int Idx = Mask[i+l];
3388 unsigned RngStart = l + ((Commuted == (i<HalfLaneElems)) ? NumElems : 0);
3389 if (!isUndefOrInRange(Idx, RngStart, RngStart+NumLaneElems))
3391 // For VSHUFPSY, the mask of the second half must be the same as the
3392 // first but with the appropriate offsets. This works in the same way as
3393 // VPERMILPS works with masks.
3394 if (NumElems != 8 || l == 0 || Mask[i] < 0)
3396 if (!isUndefOrEqual(Idx, Mask[i]+l))
3404 /// isMOVHLPSMask - Return true if the specified VECTOR_SHUFFLE operand
3405 /// specifies a shuffle of elements that is suitable for input to MOVHLPS.
3406 static bool isMOVHLPSMask(ArrayRef<int> Mask, EVT VT) {
3407 if (!VT.is128BitVector())
3410 unsigned NumElems = VT.getVectorNumElements();
3415 // Expect bit0 == 6, bit1 == 7, bit2 == 2, bit3 == 3
3416 return isUndefOrEqual(Mask[0], 6) &&
3417 isUndefOrEqual(Mask[1], 7) &&
3418 isUndefOrEqual(Mask[2], 2) &&
3419 isUndefOrEqual(Mask[3], 3);
3422 /// isMOVHLPS_v_undef_Mask - Special case of isMOVHLPSMask for canonical form
3423 /// of vector_shuffle v, v, <2, 3, 2, 3>, i.e. vector_shuffle v, undef,
3425 static bool isMOVHLPS_v_undef_Mask(ArrayRef<int> Mask, EVT VT) {
3426 if (!VT.is128BitVector())
3429 unsigned NumElems = VT.getVectorNumElements();
3434 return isUndefOrEqual(Mask[0], 2) &&
3435 isUndefOrEqual(Mask[1], 3) &&
3436 isUndefOrEqual(Mask[2], 2) &&
3437 isUndefOrEqual(Mask[3], 3);
3440 /// isMOVLPMask - Return true if the specified VECTOR_SHUFFLE operand
3441 /// specifies a shuffle of elements that is suitable for input to MOVLP{S|D}.
3442 static bool isMOVLPMask(ArrayRef<int> Mask, EVT VT) {
3443 if (!VT.is128BitVector())
3446 unsigned NumElems = VT.getVectorNumElements();
3448 if (NumElems != 2 && NumElems != 4)
3451 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
3452 if (!isUndefOrEqual(Mask[i], i + NumElems))
3455 for (unsigned i = NumElems/2, e = NumElems; i != e; ++i)
3456 if (!isUndefOrEqual(Mask[i], i))
3462 /// isMOVLHPSMask - Return true if the specified VECTOR_SHUFFLE operand
3463 /// specifies a shuffle of elements that is suitable for input to MOVLHPS.
3464 static bool isMOVLHPSMask(ArrayRef<int> Mask, EVT VT) {
3465 if (!VT.is128BitVector())
3468 unsigned NumElems = VT.getVectorNumElements();
3470 if (NumElems != 2 && NumElems != 4)
3473 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
3474 if (!isUndefOrEqual(Mask[i], i))
3477 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
3478 if (!isUndefOrEqual(Mask[i + e], i + NumElems))
3485 // Some special combinations that can be optimized.
3488 SDValue Compact8x32ShuffleNode(ShuffleVectorSDNode *SVOp,
3489 SelectionDAG &DAG) {
3490 EVT VT = SVOp->getValueType(0);
3491 DebugLoc dl = SVOp->getDebugLoc();
3493 if (VT != MVT::v8i32 && VT != MVT::v8f32)
3496 ArrayRef<int> Mask = SVOp->getMask();
3498 // These are the special masks that may be optimized.
3499 static const int MaskToOptimizeEven[] = {0, 8, 2, 10, 4, 12, 6, 14};
3500 static const int MaskToOptimizeOdd[] = {1, 9, 3, 11, 5, 13, 7, 15};
3501 bool MatchEvenMask = true;
3502 bool MatchOddMask = true;
3503 for (int i=0; i<8; ++i) {
3504 if (!isUndefOrEqual(Mask[i], MaskToOptimizeEven[i]))
3505 MatchEvenMask = false;
3506 if (!isUndefOrEqual(Mask[i], MaskToOptimizeOdd[i]))
3507 MatchOddMask = false;
3509 static const int CompactionMaskEven[] = {0, 2, -1, -1, 4, 6, -1, -1};
3510 static const int CompactionMaskOdd [] = {1, 3, -1, -1, 5, 7, -1, -1};
3512 const int *CompactionMask;
3514 CompactionMask = CompactionMaskEven;
3515 else if (MatchOddMask)
3516 CompactionMask = CompactionMaskOdd;
3520 SDValue UndefNode = DAG.getNode(ISD::UNDEF, dl, VT);
3522 SDValue Op0 = DAG.getVectorShuffle(VT, dl, SVOp->getOperand(0),
3523 UndefNode, CompactionMask);
3524 SDValue Op1 = DAG.getVectorShuffle(VT, dl, SVOp->getOperand(1),
3525 UndefNode, CompactionMask);
3526 static const int UnpackMask[] = {0, 8, 1, 9, 4, 12, 5, 13};
3527 return DAG.getVectorShuffle(VT, dl, Op0, Op1, UnpackMask);
3530 /// isUNPCKLMask - Return true if the specified VECTOR_SHUFFLE operand
3531 /// specifies a shuffle of elements that is suitable for input to UNPCKL.
3532 static bool isUNPCKLMask(ArrayRef<int> Mask, EVT VT,
3533 bool HasAVX2, bool V2IsSplat = false) {
3534 unsigned NumElts = VT.getVectorNumElements();
3536 assert((VT.is128BitVector() || VT.is256BitVector()) &&
3537 "Unsupported vector type for unpckh");
3539 if (VT.getSizeInBits() == 256 && NumElts != 4 && NumElts != 8 &&
3540 (!HasAVX2 || (NumElts != 16 && NumElts != 32)))
3543 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
3544 // independently on 128-bit lanes.
3545 unsigned NumLanes = VT.getSizeInBits()/128;
3546 unsigned NumLaneElts = NumElts/NumLanes;
3548 for (unsigned l = 0; l != NumLanes; ++l) {
3549 for (unsigned i = l*NumLaneElts, j = l*NumLaneElts;
3550 i != (l+1)*NumLaneElts;
3553 int BitI1 = Mask[i+1];
3554 if (!isUndefOrEqual(BitI, j))
3557 if (!isUndefOrEqual(BitI1, NumElts))
3560 if (!isUndefOrEqual(BitI1, j + NumElts))
3569 /// isUNPCKHMask - Return true if the specified VECTOR_SHUFFLE operand
3570 /// specifies a shuffle of elements that is suitable for input to UNPCKH.
3571 static bool isUNPCKHMask(ArrayRef<int> Mask, EVT VT,
3572 bool HasAVX2, bool V2IsSplat = false) {
3573 unsigned NumElts = VT.getVectorNumElements();
3575 assert((VT.is128BitVector() || VT.is256BitVector()) &&
3576 "Unsupported vector type for unpckh");
3578 if (VT.getSizeInBits() == 256 && NumElts != 4 && NumElts != 8 &&
3579 (!HasAVX2 || (NumElts != 16 && NumElts != 32)))
3582 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
3583 // independently on 128-bit lanes.
3584 unsigned NumLanes = VT.getSizeInBits()/128;
3585 unsigned NumLaneElts = NumElts/NumLanes;
3587 for (unsigned l = 0; l != NumLanes; ++l) {
3588 for (unsigned i = l*NumLaneElts, j = (l*NumLaneElts)+NumLaneElts/2;
3589 i != (l+1)*NumLaneElts; i += 2, ++j) {
3591 int BitI1 = Mask[i+1];
3592 if (!isUndefOrEqual(BitI, j))
3595 if (isUndefOrEqual(BitI1, NumElts))
3598 if (!isUndefOrEqual(BitI1, j+NumElts))
3606 /// isUNPCKL_v_undef_Mask - Special case of isUNPCKLMask for canonical form
3607 /// of vector_shuffle v, v, <0, 4, 1, 5>, i.e. vector_shuffle v, undef,
3609 static bool isUNPCKL_v_undef_Mask(ArrayRef<int> Mask, EVT VT,
3611 unsigned NumElts = VT.getVectorNumElements();
3613 assert((VT.is128BitVector() || VT.is256BitVector()) &&
3614 "Unsupported vector type for unpckh");
3616 if (VT.getSizeInBits() == 256 && NumElts != 4 && NumElts != 8 &&
3617 (!HasAVX2 || (NumElts != 16 && NumElts != 32)))
3620 // For 256-bit i64/f64, use MOVDDUPY instead, so reject the matching pattern
3621 // FIXME: Need a better way to get rid of this, there's no latency difference
3622 // between UNPCKLPD and MOVDDUP, the later should always be checked first and
3623 // the former later. We should also remove the "_undef" special mask.
3624 if (NumElts == 4 && VT.getSizeInBits() == 256)
3627 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
3628 // independently on 128-bit lanes.
3629 unsigned NumLanes = VT.getSizeInBits()/128;
3630 unsigned NumLaneElts = NumElts/NumLanes;
3632 for (unsigned l = 0; l != NumLanes; ++l) {
3633 for (unsigned i = l*NumLaneElts, j = l*NumLaneElts;
3634 i != (l+1)*NumLaneElts;
3637 int BitI1 = Mask[i+1];
3639 if (!isUndefOrEqual(BitI, j))
3641 if (!isUndefOrEqual(BitI1, j))
3649 /// isUNPCKH_v_undef_Mask - Special case of isUNPCKHMask for canonical form
3650 /// of vector_shuffle v, v, <2, 6, 3, 7>, i.e. vector_shuffle v, undef,
3652 static bool isUNPCKH_v_undef_Mask(ArrayRef<int> Mask, EVT VT, bool HasAVX2) {
3653 unsigned NumElts = VT.getVectorNumElements();
3655 assert((VT.is128BitVector() || VT.is256BitVector()) &&
3656 "Unsupported vector type for unpckh");
3658 if (VT.getSizeInBits() == 256 && NumElts != 4 && NumElts != 8 &&
3659 (!HasAVX2 || (NumElts != 16 && NumElts != 32)))
3662 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
3663 // independently on 128-bit lanes.
3664 unsigned NumLanes = VT.getSizeInBits()/128;
3665 unsigned NumLaneElts = NumElts/NumLanes;
3667 for (unsigned l = 0; l != NumLanes; ++l) {
3668 for (unsigned i = l*NumLaneElts, j = (l*NumLaneElts)+NumLaneElts/2;
3669 i != (l+1)*NumLaneElts; i += 2, ++j) {
3671 int BitI1 = Mask[i+1];
3672 if (!isUndefOrEqual(BitI, j))
3674 if (!isUndefOrEqual(BitI1, j))
3681 /// isMOVLMask - Return true if the specified VECTOR_SHUFFLE operand
3682 /// specifies a shuffle of elements that is suitable for input to MOVSS,
3683 /// MOVSD, and MOVD, i.e. setting the lowest element.
3684 static bool isMOVLMask(ArrayRef<int> Mask, EVT VT) {
3685 if (VT.getVectorElementType().getSizeInBits() < 32)
3687 if (!VT.is128BitVector())
3690 unsigned NumElts = VT.getVectorNumElements();
3692 if (!isUndefOrEqual(Mask[0], NumElts))
3695 for (unsigned i = 1; i != NumElts; ++i)
3696 if (!isUndefOrEqual(Mask[i], i))
3702 /// isVPERM2X128Mask - Match 256-bit shuffles where the elements are considered
3703 /// as permutations between 128-bit chunks or halves. As an example: this
3705 /// vector_shuffle <4, 5, 6, 7, 12, 13, 14, 15>
3706 /// The first half comes from the second half of V1 and the second half from the
3707 /// the second half of V2.
3708 static bool isVPERM2X128Mask(ArrayRef<int> Mask, EVT VT, bool HasAVX) {
3709 if (!HasAVX || !VT.is256BitVector())
3712 // The shuffle result is divided into half A and half B. In total the two
3713 // sources have 4 halves, namely: C, D, E, F. The final values of A and
3714 // B must come from C, D, E or F.
3715 unsigned HalfSize = VT.getVectorNumElements()/2;
3716 bool MatchA = false, MatchB = false;
3718 // Check if A comes from one of C, D, E, F.
3719 for (unsigned Half = 0; Half != 4; ++Half) {
3720 if (isSequentialOrUndefInRange(Mask, 0, HalfSize, Half*HalfSize)) {
3726 // Check if B comes from one of C, D, E, F.
3727 for (unsigned Half = 0; Half != 4; ++Half) {
3728 if (isSequentialOrUndefInRange(Mask, HalfSize, HalfSize, Half*HalfSize)) {
3734 return MatchA && MatchB;
3737 /// getShuffleVPERM2X128Immediate - Return the appropriate immediate to shuffle
3738 /// the specified VECTOR_MASK mask with VPERM2F128/VPERM2I128 instructions.
3739 static unsigned getShuffleVPERM2X128Immediate(ShuffleVectorSDNode *SVOp) {
3740 EVT VT = SVOp->getValueType(0);
3742 unsigned HalfSize = VT.getVectorNumElements()/2;
3744 unsigned FstHalf = 0, SndHalf = 0;
3745 for (unsigned i = 0; i < HalfSize; ++i) {
3746 if (SVOp->getMaskElt(i) > 0) {
3747 FstHalf = SVOp->getMaskElt(i)/HalfSize;
3751 for (unsigned i = HalfSize; i < HalfSize*2; ++i) {
3752 if (SVOp->getMaskElt(i) > 0) {
3753 SndHalf = SVOp->getMaskElt(i)/HalfSize;
3758 return (FstHalf | (SndHalf << 4));
3761 /// isVPERMILPMask - Return true if the specified VECTOR_SHUFFLE operand
3762 /// specifies a shuffle of elements that is suitable for input to VPERMILPD*.
3763 /// Note that VPERMIL mask matching is different depending whether theunderlying
3764 /// type is 32 or 64. In the VPERMILPS the high half of the mask should point
3765 /// to the same elements of the low, but to the higher half of the source.
3766 /// In VPERMILPD the two lanes could be shuffled independently of each other
3767 /// with the same restriction that lanes can't be crossed. Also handles PSHUFDY.
3768 static bool isVPERMILPMask(ArrayRef<int> Mask, EVT VT, bool HasAVX) {
3772 unsigned NumElts = VT.getVectorNumElements();
3773 // Only match 256-bit with 32/64-bit types
3774 if (VT.getSizeInBits() != 256 || (NumElts != 4 && NumElts != 8))
3777 unsigned NumLanes = VT.getSizeInBits()/128;
3778 unsigned LaneSize = NumElts/NumLanes;
3779 for (unsigned l = 0; l != NumElts; l += LaneSize) {
3780 for (unsigned i = 0; i != LaneSize; ++i) {
3781 if (!isUndefOrInRange(Mask[i+l], l, l+LaneSize))
3783 if (NumElts != 8 || l == 0)
3785 // VPERMILPS handling
3788 if (!isUndefOrEqual(Mask[i+l], Mask[i]+l))
3796 /// isCommutedMOVLMask - Returns true if the shuffle mask is except the reverse
3797 /// of what x86 movss want. X86 movs requires the lowest element to be lowest
3798 /// element of vector 2 and the other elements to come from vector 1 in order.
3799 static bool isCommutedMOVLMask(ArrayRef<int> Mask, EVT VT,
3800 bool V2IsSplat = false, bool V2IsUndef = false) {
3801 if (!VT.is128BitVector())
3804 unsigned NumOps = VT.getVectorNumElements();
3805 if (NumOps != 2 && NumOps != 4 && NumOps != 8 && NumOps != 16)
3808 if (!isUndefOrEqual(Mask[0], 0))
3811 for (unsigned i = 1; i != NumOps; ++i)
3812 if (!(isUndefOrEqual(Mask[i], i+NumOps) ||
3813 (V2IsUndef && isUndefOrInRange(Mask[i], NumOps, NumOps*2)) ||
3814 (V2IsSplat && isUndefOrEqual(Mask[i], NumOps))))
3820 /// isMOVSHDUPMask - Return true if the specified VECTOR_SHUFFLE operand
3821 /// specifies a shuffle of elements that is suitable for input to MOVSHDUP.
3822 /// Masks to match: <1, 1, 3, 3> or <1, 1, 3, 3, 5, 5, 7, 7>
3823 static bool isMOVSHDUPMask(ArrayRef<int> Mask, EVT VT,
3824 const X86Subtarget *Subtarget) {
3825 if (!Subtarget->hasSSE3())
3828 unsigned NumElems = VT.getVectorNumElements();
3830 if ((VT.getSizeInBits() == 128 && NumElems != 4) ||
3831 (VT.getSizeInBits() == 256 && NumElems != 8))
3834 // "i+1" is the value the indexed mask element must have
3835 for (unsigned i = 0; i != NumElems; i += 2)
3836 if (!isUndefOrEqual(Mask[i], i+1) ||
3837 !isUndefOrEqual(Mask[i+1], i+1))
3843 /// isMOVSLDUPMask - Return true if the specified VECTOR_SHUFFLE operand
3844 /// specifies a shuffle of elements that is suitable for input to MOVSLDUP.
3845 /// Masks to match: <0, 0, 2, 2> or <0, 0, 2, 2, 4, 4, 6, 6>
3846 static bool isMOVSLDUPMask(ArrayRef<int> Mask, EVT VT,
3847 const X86Subtarget *Subtarget) {
3848 if (!Subtarget->hasSSE3())
3851 unsigned NumElems = VT.getVectorNumElements();
3853 if ((VT.getSizeInBits() == 128 && NumElems != 4) ||
3854 (VT.getSizeInBits() == 256 && NumElems != 8))
3857 // "i" is the value the indexed mask element must have
3858 for (unsigned i = 0; i != NumElems; i += 2)
3859 if (!isUndefOrEqual(Mask[i], i) ||
3860 !isUndefOrEqual(Mask[i+1], i))
3866 /// isMOVDDUPYMask - Return true if the specified VECTOR_SHUFFLE operand
3867 /// specifies a shuffle of elements that is suitable for input to 256-bit
3868 /// version of MOVDDUP.
3869 static bool isMOVDDUPYMask(ArrayRef<int> Mask, EVT VT, bool HasAVX) {
3870 if (!HasAVX || !VT.is256BitVector())
3873 unsigned NumElts = VT.getVectorNumElements();
3877 for (unsigned i = 0; i != NumElts/2; ++i)
3878 if (!isUndefOrEqual(Mask[i], 0))
3880 for (unsigned i = NumElts/2; i != NumElts; ++i)
3881 if (!isUndefOrEqual(Mask[i], NumElts/2))
3886 /// isMOVDDUPMask - Return true if the specified VECTOR_SHUFFLE operand
3887 /// specifies a shuffle of elements that is suitable for input to 128-bit
3888 /// version of MOVDDUP.
3889 static bool isMOVDDUPMask(ArrayRef<int> Mask, EVT VT) {
3890 if (!VT.is128BitVector())
3893 unsigned e = VT.getVectorNumElements() / 2;
3894 for (unsigned i = 0; i != e; ++i)
3895 if (!isUndefOrEqual(Mask[i], i))
3897 for (unsigned i = 0; i != e; ++i)
3898 if (!isUndefOrEqual(Mask[e+i], i))
3903 /// isVEXTRACTF128Index - Return true if the specified
3904 /// EXTRACT_SUBVECTOR operand specifies a vector extract that is
3905 /// suitable for input to VEXTRACTF128.
3906 bool X86::isVEXTRACTF128Index(SDNode *N) {
3907 if (!isa<ConstantSDNode>(N->getOperand(1).getNode()))
3910 // The index should be aligned on a 128-bit boundary.
3912 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
3914 unsigned VL = N->getValueType(0).getVectorNumElements();
3915 unsigned VBits = N->getValueType(0).getSizeInBits();
3916 unsigned ElSize = VBits / VL;
3917 bool Result = (Index * ElSize) % 128 == 0;
3922 /// isVINSERTF128Index - Return true if the specified INSERT_SUBVECTOR
3923 /// operand specifies a subvector insert that is suitable for input to
3925 bool X86::isVINSERTF128Index(SDNode *N) {
3926 if (!isa<ConstantSDNode>(N->getOperand(2).getNode()))
3929 // The index should be aligned on a 128-bit boundary.
3931 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
3933 unsigned VL = N->getValueType(0).getVectorNumElements();
3934 unsigned VBits = N->getValueType(0).getSizeInBits();
3935 unsigned ElSize = VBits / VL;
3936 bool Result = (Index * ElSize) % 128 == 0;
3941 /// getShuffleSHUFImmediate - Return the appropriate immediate to shuffle
3942 /// the specified VECTOR_SHUFFLE mask with PSHUF* and SHUFP* instructions.
3943 /// Handles 128-bit and 256-bit.
3944 static unsigned getShuffleSHUFImmediate(ShuffleVectorSDNode *N) {
3945 EVT VT = N->getValueType(0);
3947 assert((VT.is128BitVector() || VT.is256BitVector()) &&
3948 "Unsupported vector type for PSHUF/SHUFP");
3950 // Handle 128 and 256-bit vector lengths. AVX defines PSHUF/SHUFP to operate
3951 // independently on 128-bit lanes.
3952 unsigned NumElts = VT.getVectorNumElements();
3953 unsigned NumLanes = VT.getSizeInBits()/128;
3954 unsigned NumLaneElts = NumElts/NumLanes;
3956 assert((NumLaneElts == 2 || NumLaneElts == 4) &&
3957 "Only supports 2 or 4 elements per lane");
3959 unsigned Shift = (NumLaneElts == 4) ? 1 : 0;
3961 for (unsigned i = 0; i != NumElts; ++i) {
3962 int Elt = N->getMaskElt(i);
3963 if (Elt < 0) continue;
3964 Elt &= NumLaneElts - 1;
3965 unsigned ShAmt = (i << Shift) % 8;
3966 Mask |= Elt << ShAmt;
3972 /// getShufflePSHUFHWImmediate - Return the appropriate immediate to shuffle
3973 /// the specified VECTOR_SHUFFLE mask with the PSHUFHW instruction.
3974 static unsigned getShufflePSHUFHWImmediate(ShuffleVectorSDNode *N) {
3975 EVT VT = N->getValueType(0);
3977 assert((VT == MVT::v8i16 || VT == MVT::v16i16) &&
3978 "Unsupported vector type for PSHUFHW");
3980 unsigned NumElts = VT.getVectorNumElements();
3983 for (unsigned l = 0; l != NumElts; l += 8) {
3984 // 8 nodes per lane, but we only care about the last 4.
3985 for (unsigned i = 0; i < 4; ++i) {
3986 int Elt = N->getMaskElt(l+i+4);
3987 if (Elt < 0) continue;
3988 Elt &= 0x3; // only 2-bits.
3989 Mask |= Elt << (i * 2);
3996 /// getShufflePSHUFLWImmediate - Return the appropriate immediate to shuffle
3997 /// the specified VECTOR_SHUFFLE mask with the PSHUFLW instruction.
3998 static unsigned getShufflePSHUFLWImmediate(ShuffleVectorSDNode *N) {
3999 EVT VT = N->getValueType(0);
4001 assert((VT == MVT::v8i16 || VT == MVT::v16i16) &&
4002 "Unsupported vector type for PSHUFHW");
4004 unsigned NumElts = VT.getVectorNumElements();
4007 for (unsigned l = 0; l != NumElts; l += 8) {
4008 // 8 nodes per lane, but we only care about the first 4.
4009 for (unsigned i = 0; i < 4; ++i) {
4010 int Elt = N->getMaskElt(l+i);
4011 if (Elt < 0) continue;
4012 Elt &= 0x3; // only 2-bits
4013 Mask |= Elt << (i * 2);
4020 /// getShufflePALIGNRImmediate - Return the appropriate immediate to shuffle
4021 /// the specified VECTOR_SHUFFLE mask with the PALIGNR instruction.
4022 static unsigned getShufflePALIGNRImmediate(ShuffleVectorSDNode *SVOp) {
4023 EVT VT = SVOp->getValueType(0);
4024 unsigned EltSize = VT.getVectorElementType().getSizeInBits() >> 3;
4026 unsigned NumElts = VT.getVectorNumElements();
4027 unsigned NumLanes = VT.getSizeInBits()/128;
4028 unsigned NumLaneElts = NumElts/NumLanes;
4032 for (i = 0; i != NumElts; ++i) {
4033 Val = SVOp->getMaskElt(i);
4037 if (Val >= (int)NumElts)
4038 Val -= NumElts - NumLaneElts;
4040 assert(Val - i > 0 && "PALIGNR imm should be positive");
4041 return (Val - i) * EltSize;
4044 /// getExtractVEXTRACTF128Immediate - Return the appropriate immediate
4045 /// to extract the specified EXTRACT_SUBVECTOR index with VEXTRACTF128
4047 unsigned X86::getExtractVEXTRACTF128Immediate(SDNode *N) {
4048 if (!isa<ConstantSDNode>(N->getOperand(1).getNode()))
4049 llvm_unreachable("Illegal extract subvector for VEXTRACTF128");
4052 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
4054 EVT VecVT = N->getOperand(0).getValueType();
4055 EVT ElVT = VecVT.getVectorElementType();
4057 unsigned NumElemsPerChunk = 128 / ElVT.getSizeInBits();
4058 return Index / NumElemsPerChunk;
4061 /// getInsertVINSERTF128Immediate - Return the appropriate immediate
4062 /// to insert at the specified INSERT_SUBVECTOR index with VINSERTF128
4064 unsigned X86::getInsertVINSERTF128Immediate(SDNode *N) {
4065 if (!isa<ConstantSDNode>(N->getOperand(2).getNode()))
4066 llvm_unreachable("Illegal insert subvector for VINSERTF128");
4069 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
4071 EVT VecVT = N->getValueType(0);
4072 EVT ElVT = VecVT.getVectorElementType();
4074 unsigned NumElemsPerChunk = 128 / ElVT.getSizeInBits();
4075 return Index / NumElemsPerChunk;
4078 /// getShuffleCLImmediate - Return the appropriate immediate to shuffle
4079 /// the specified VECTOR_SHUFFLE mask with VPERMQ and VPERMPD instructions.
4080 /// Handles 256-bit.
4081 static unsigned getShuffleCLImmediate(ShuffleVectorSDNode *N) {
4082 EVT VT = N->getValueType(0);
4084 unsigned NumElts = VT.getVectorNumElements();
4086 assert((VT.is256BitVector() && NumElts == 4) &&
4087 "Unsupported vector type for VPERMQ/VPERMPD");
4090 for (unsigned i = 0; i != NumElts; ++i) {
4091 int Elt = N->getMaskElt(i);
4094 Mask |= Elt << (i*2);
4099 /// isZeroNode - Returns true if Elt is a constant zero or a floating point
4101 bool X86::isZeroNode(SDValue Elt) {
4102 return ((isa<ConstantSDNode>(Elt) &&
4103 cast<ConstantSDNode>(Elt)->isNullValue()) ||
4104 (isa<ConstantFPSDNode>(Elt) &&
4105 cast<ConstantFPSDNode>(Elt)->getValueAPF().isPosZero()));
4108 /// CommuteVectorShuffle - Swap vector_shuffle operands as well as values in
4109 /// their permute mask.
4110 static SDValue CommuteVectorShuffle(ShuffleVectorSDNode *SVOp,
4111 SelectionDAG &DAG) {
4112 EVT VT = SVOp->getValueType(0);
4113 unsigned NumElems = VT.getVectorNumElements();
4114 SmallVector<int, 8> MaskVec;
4116 for (unsigned i = 0; i != NumElems; ++i) {
4117 int Idx = SVOp->getMaskElt(i);
4119 if (Idx < (int)NumElems)
4124 MaskVec.push_back(Idx);
4126 return DAG.getVectorShuffle(VT, SVOp->getDebugLoc(), SVOp->getOperand(1),
4127 SVOp->getOperand(0), &MaskVec[0]);
4130 /// ShouldXformToMOVHLPS - Return true if the node should be transformed to
4131 /// match movhlps. The lower half elements should come from upper half of
4132 /// V1 (and in order), and the upper half elements should come from the upper
4133 /// half of V2 (and in order).
4134 static bool ShouldXformToMOVHLPS(ArrayRef<int> Mask, EVT VT) {
4135 if (!VT.is128BitVector())
4137 if (VT.getVectorNumElements() != 4)
4139 for (unsigned i = 0, e = 2; i != e; ++i)
4140 if (!isUndefOrEqual(Mask[i], i+2))
4142 for (unsigned i = 2; i != 4; ++i)
4143 if (!isUndefOrEqual(Mask[i], i+4))
4148 /// isScalarLoadToVector - Returns true if the node is a scalar load that
4149 /// is promoted to a vector. It also returns the LoadSDNode by reference if
4151 static bool isScalarLoadToVector(SDNode *N, LoadSDNode **LD = NULL) {
4152 if (N->getOpcode() != ISD::SCALAR_TO_VECTOR)
4154 N = N->getOperand(0).getNode();
4155 if (!ISD::isNON_EXTLoad(N))
4158 *LD = cast<LoadSDNode>(N);
4162 // Test whether the given value is a vector value which will be legalized
4164 static bool WillBeConstantPoolLoad(SDNode *N) {
4165 if (N->getOpcode() != ISD::BUILD_VECTOR)
4168 // Check for any non-constant elements.
4169 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
4170 switch (N->getOperand(i).getNode()->getOpcode()) {
4172 case ISD::ConstantFP:
4179 // Vectors of all-zeros and all-ones are materialized with special
4180 // instructions rather than being loaded.
4181 return !ISD::isBuildVectorAllZeros(N) &&
4182 !ISD::isBuildVectorAllOnes(N);
4185 /// ShouldXformToMOVLP{S|D} - Return true if the node should be transformed to
4186 /// match movlp{s|d}. The lower half elements should come from lower half of
4187 /// V1 (and in order), and the upper half elements should come from the upper
4188 /// half of V2 (and in order). And since V1 will become the source of the
4189 /// MOVLP, it must be either a vector load or a scalar load to vector.
4190 static bool ShouldXformToMOVLP(SDNode *V1, SDNode *V2,
4191 ArrayRef<int> Mask, EVT VT) {
4192 if (!VT.is128BitVector())
4195 if (!ISD::isNON_EXTLoad(V1) && !isScalarLoadToVector(V1))
4197 // Is V2 is a vector load, don't do this transformation. We will try to use
4198 // load folding shufps op.
4199 if (ISD::isNON_EXTLoad(V2) || WillBeConstantPoolLoad(V2))
4202 unsigned NumElems = VT.getVectorNumElements();
4204 if (NumElems != 2 && NumElems != 4)
4206 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
4207 if (!isUndefOrEqual(Mask[i], i))
4209 for (unsigned i = NumElems/2, e = NumElems; i != e; ++i)
4210 if (!isUndefOrEqual(Mask[i], i+NumElems))
4215 /// isSplatVector - Returns true if N is a BUILD_VECTOR node whose elements are
4217 static bool isSplatVector(SDNode *N) {
4218 if (N->getOpcode() != ISD::BUILD_VECTOR)
4221 SDValue SplatValue = N->getOperand(0);
4222 for (unsigned i = 1, e = N->getNumOperands(); i != e; ++i)
4223 if (N->getOperand(i) != SplatValue)
4228 /// isZeroShuffle - Returns true if N is a VECTOR_SHUFFLE that can be resolved
4229 /// to an zero vector.
4230 /// FIXME: move to dag combiner / method on ShuffleVectorSDNode
4231 static bool isZeroShuffle(ShuffleVectorSDNode *N) {
4232 SDValue V1 = N->getOperand(0);
4233 SDValue V2 = N->getOperand(1);
4234 unsigned NumElems = N->getValueType(0).getVectorNumElements();
4235 for (unsigned i = 0; i != NumElems; ++i) {
4236 int Idx = N->getMaskElt(i);
4237 if (Idx >= (int)NumElems) {
4238 unsigned Opc = V2.getOpcode();
4239 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V2.getNode()))
4241 if (Opc != ISD::BUILD_VECTOR ||
4242 !X86::isZeroNode(V2.getOperand(Idx-NumElems)))
4244 } else if (Idx >= 0) {
4245 unsigned Opc = V1.getOpcode();
4246 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V1.getNode()))
4248 if (Opc != ISD::BUILD_VECTOR ||
4249 !X86::isZeroNode(V1.getOperand(Idx)))
4256 /// getZeroVector - Returns a vector of specified type with all zero elements.
4258 static SDValue getZeroVector(EVT VT, const X86Subtarget *Subtarget,
4259 SelectionDAG &DAG, DebugLoc dl) {
4260 assert(VT.isVector() && "Expected a vector type");
4261 unsigned Size = VT.getSizeInBits();
4263 // Always build SSE zero vectors as <4 x i32> bitcasted
4264 // to their dest type. This ensures they get CSE'd.
4266 if (Size == 128) { // SSE
4267 if (Subtarget->hasSSE2()) { // SSE2
4268 SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
4269 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4271 SDValue Cst = DAG.getTargetConstantFP(+0.0, MVT::f32);
4272 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4f32, Cst, Cst, Cst, Cst);
4274 } else if (Size == 256) { // AVX
4275 if (Subtarget->hasAVX2()) { // AVX2
4276 SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
4277 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4278 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops, 8);
4280 // 256-bit logic and arithmetic instructions in AVX are all
4281 // floating-point, no support for integer ops. Emit fp zeroed vectors.
4282 SDValue Cst = DAG.getTargetConstantFP(+0.0, MVT::f32);
4283 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4284 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8f32, Ops, 8);
4287 llvm_unreachable("Unexpected vector type");
4289 return DAG.getNode(ISD::BITCAST, dl, VT, Vec);
4292 /// getOnesVector - Returns a vector of specified type with all bits set.
4293 /// Always build ones vectors as <4 x i32> or <8 x i32>. For 256-bit types with
4294 /// no AVX2 supprt, use two <4 x i32> inserted in a <8 x i32> appropriately.
4295 /// Then bitcast to their original type, ensuring they get CSE'd.
4296 static SDValue getOnesVector(EVT VT, bool HasAVX2, SelectionDAG &DAG,
4298 assert(VT.isVector() && "Expected a vector type");
4299 unsigned Size = VT.getSizeInBits();
4301 SDValue Cst = DAG.getTargetConstant(~0U, MVT::i32);
4304 if (HasAVX2) { // AVX2
4305 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4306 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops, 8);
4308 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4309 Vec = Concat128BitVectors(Vec, Vec, MVT::v8i32, 8, DAG, dl);
4311 } else if (Size == 128) {
4312 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4314 llvm_unreachable("Unexpected vector type");
4316 return DAG.getNode(ISD::BITCAST, dl, VT, Vec);
4319 /// NormalizeMask - V2 is a splat, modify the mask (if needed) so all elements
4320 /// that point to V2 points to its first element.
4321 static void NormalizeMask(SmallVectorImpl<int> &Mask, unsigned NumElems) {
4322 for (unsigned i = 0; i != NumElems; ++i) {
4323 if (Mask[i] > (int)NumElems) {
4329 /// getMOVLMask - Returns a vector_shuffle mask for an movs{s|d}, movd
4330 /// operation of specified width.
4331 static SDValue getMOVL(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1,
4333 unsigned NumElems = VT.getVectorNumElements();
4334 SmallVector<int, 8> Mask;
4335 Mask.push_back(NumElems);
4336 for (unsigned i = 1; i != NumElems; ++i)
4338 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
4341 /// getUnpackl - Returns a vector_shuffle node for an unpackl operation.
4342 static SDValue getUnpackl(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1,
4344 unsigned NumElems = VT.getVectorNumElements();
4345 SmallVector<int, 8> Mask;
4346 for (unsigned i = 0, e = NumElems/2; i != e; ++i) {
4348 Mask.push_back(i + NumElems);
4350 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
4353 /// getUnpackh - Returns a vector_shuffle node for an unpackh operation.
4354 static SDValue getUnpackh(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1,
4356 unsigned NumElems = VT.getVectorNumElements();
4357 SmallVector<int, 8> Mask;
4358 for (unsigned i = 0, Half = NumElems/2; i != Half; ++i) {
4359 Mask.push_back(i + Half);
4360 Mask.push_back(i + NumElems + Half);
4362 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
4365 // PromoteSplati8i16 - All i16 and i8 vector types can't be used directly by
4366 // a generic shuffle instruction because the target has no such instructions.
4367 // Generate shuffles which repeat i16 and i8 several times until they can be
4368 // represented by v4f32 and then be manipulated by target suported shuffles.
4369 static SDValue PromoteSplati8i16(SDValue V, SelectionDAG &DAG, int &EltNo) {
4370 EVT VT = V.getValueType();
4371 int NumElems = VT.getVectorNumElements();
4372 DebugLoc dl = V.getDebugLoc();
4374 while (NumElems > 4) {
4375 if (EltNo < NumElems/2) {
4376 V = getUnpackl(DAG, dl, VT, V, V);
4378 V = getUnpackh(DAG, dl, VT, V, V);
4379 EltNo -= NumElems/2;
4386 /// getLegalSplat - Generate a legal splat with supported x86 shuffles
4387 static SDValue getLegalSplat(SelectionDAG &DAG, SDValue V, int EltNo) {
4388 EVT VT = V.getValueType();
4389 DebugLoc dl = V.getDebugLoc();
4390 unsigned Size = VT.getSizeInBits();
4393 V = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V);
4394 int SplatMask[4] = { EltNo, EltNo, EltNo, EltNo };
4395 V = DAG.getVectorShuffle(MVT::v4f32, dl, V, DAG.getUNDEF(MVT::v4f32),
4397 } else if (Size == 256) {
4398 // To use VPERMILPS to splat scalars, the second half of indicies must
4399 // refer to the higher part, which is a duplication of the lower one,
4400 // because VPERMILPS can only handle in-lane permutations.
4401 int SplatMask[8] = { EltNo, EltNo, EltNo, EltNo,
4402 EltNo+4, EltNo+4, EltNo+4, EltNo+4 };
4404 V = DAG.getNode(ISD::BITCAST, dl, MVT::v8f32, V);
4405 V = DAG.getVectorShuffle(MVT::v8f32, dl, V, DAG.getUNDEF(MVT::v8f32),
4408 llvm_unreachable("Vector size not supported");
4410 return DAG.getNode(ISD::BITCAST, dl, VT, V);
4413 /// PromoteSplat - Splat is promoted to target supported vector shuffles.
4414 static SDValue PromoteSplat(ShuffleVectorSDNode *SV, SelectionDAG &DAG) {
4415 EVT SrcVT = SV->getValueType(0);
4416 SDValue V1 = SV->getOperand(0);
4417 DebugLoc dl = SV->getDebugLoc();
4419 int EltNo = SV->getSplatIndex();
4420 int NumElems = SrcVT.getVectorNumElements();
4421 unsigned Size = SrcVT.getSizeInBits();
4423 assert(((Size == 128 && NumElems > 4) || Size == 256) &&
4424 "Unknown how to promote splat for type");
4426 // Extract the 128-bit part containing the splat element and update
4427 // the splat element index when it refers to the higher register.
4429 V1 = Extract128BitVector(V1, EltNo, DAG, dl);
4430 if (EltNo >= NumElems/2)
4431 EltNo -= NumElems/2;
4434 // All i16 and i8 vector types can't be used directly by a generic shuffle
4435 // instruction because the target has no such instruction. Generate shuffles
4436 // which repeat i16 and i8 several times until they fit in i32, and then can
4437 // be manipulated by target suported shuffles.
4438 EVT EltVT = SrcVT.getVectorElementType();
4439 if (EltVT == MVT::i8 || EltVT == MVT::i16)
4440 V1 = PromoteSplati8i16(V1, DAG, EltNo);
4442 // Recreate the 256-bit vector and place the same 128-bit vector
4443 // into the low and high part. This is necessary because we want
4444 // to use VPERM* to shuffle the vectors
4446 V1 = DAG.getNode(ISD::CONCAT_VECTORS, dl, SrcVT, V1, V1);
4449 return getLegalSplat(DAG, V1, EltNo);
4452 /// getShuffleVectorZeroOrUndef - Return a vector_shuffle of the specified
4453 /// vector of zero or undef vector. This produces a shuffle where the low
4454 /// element of V2 is swizzled into the zero/undef vector, landing at element
4455 /// Idx. This produces a shuffle mask like 4,1,2,3 (idx=0) or 0,1,2,4 (idx=3).
4456 static SDValue getShuffleVectorZeroOrUndef(SDValue V2, unsigned Idx,
4458 const X86Subtarget *Subtarget,
4459 SelectionDAG &DAG) {
4460 EVT VT = V2.getValueType();
4462 ? getZeroVector(VT, Subtarget, DAG, V2.getDebugLoc()) : DAG.getUNDEF(VT);
4463 unsigned NumElems = VT.getVectorNumElements();
4464 SmallVector<int, 16> MaskVec;
4465 for (unsigned i = 0; i != NumElems; ++i)
4466 // If this is the insertion idx, put the low elt of V2 here.
4467 MaskVec.push_back(i == Idx ? NumElems : i);
4468 return DAG.getVectorShuffle(VT, V2.getDebugLoc(), V1, V2, &MaskVec[0]);
4471 /// getTargetShuffleMask - Calculates the shuffle mask corresponding to the
4472 /// target specific opcode. Returns true if the Mask could be calculated.
4473 /// Sets IsUnary to true if only uses one source.
4474 static bool getTargetShuffleMask(SDNode *N, MVT VT,
4475 SmallVectorImpl<int> &Mask, bool &IsUnary) {
4476 unsigned NumElems = VT.getVectorNumElements();
4480 switch(N->getOpcode()) {
4482 ImmN = N->getOperand(N->getNumOperands()-1);
4483 DecodeSHUFPMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4485 case X86ISD::UNPCKH:
4486 DecodeUNPCKHMask(VT, Mask);
4488 case X86ISD::UNPCKL:
4489 DecodeUNPCKLMask(VT, Mask);
4491 case X86ISD::MOVHLPS:
4492 DecodeMOVHLPSMask(NumElems, Mask);
4494 case X86ISD::MOVLHPS:
4495 DecodeMOVLHPSMask(NumElems, Mask);
4497 case X86ISD::PSHUFD:
4498 case X86ISD::VPERMILP:
4499 ImmN = N->getOperand(N->getNumOperands()-1);
4500 DecodePSHUFMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4503 case X86ISD::PSHUFHW:
4504 ImmN = N->getOperand(N->getNumOperands()-1);
4505 DecodePSHUFHWMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4508 case X86ISD::PSHUFLW:
4509 ImmN = N->getOperand(N->getNumOperands()-1);
4510 DecodePSHUFLWMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4513 case X86ISD::VPERMI:
4514 ImmN = N->getOperand(N->getNumOperands()-1);
4515 DecodeVPERMMask(cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4519 case X86ISD::MOVSD: {
4520 // The index 0 always comes from the first element of the second source,
4521 // this is why MOVSS and MOVSD are used in the first place. The other
4522 // elements come from the other positions of the first source vector
4523 Mask.push_back(NumElems);
4524 for (unsigned i = 1; i != NumElems; ++i) {
4529 case X86ISD::VPERM2X128:
4530 ImmN = N->getOperand(N->getNumOperands()-1);
4531 DecodeVPERM2X128Mask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4532 if (Mask.empty()) return false;
4534 case X86ISD::MOVDDUP:
4535 case X86ISD::MOVLHPD:
4536 case X86ISD::MOVLPD:
4537 case X86ISD::MOVLPS:
4538 case X86ISD::MOVSHDUP:
4539 case X86ISD::MOVSLDUP:
4540 case X86ISD::PALIGN:
4541 // Not yet implemented
4543 default: llvm_unreachable("unknown target shuffle node");
4549 /// getShuffleScalarElt - Returns the scalar element that will make up the ith
4550 /// element of the result of the vector shuffle.
4551 static SDValue getShuffleScalarElt(SDNode *N, unsigned Index, SelectionDAG &DAG,
4554 return SDValue(); // Limit search depth.
4556 SDValue V = SDValue(N, 0);
4557 EVT VT = V.getValueType();
4558 unsigned Opcode = V.getOpcode();
4560 // Recurse into ISD::VECTOR_SHUFFLE node to find scalars.
4561 if (const ShuffleVectorSDNode *SV = dyn_cast<ShuffleVectorSDNode>(N)) {
4562 int Elt = SV->getMaskElt(Index);
4565 return DAG.getUNDEF(VT.getVectorElementType());
4567 unsigned NumElems = VT.getVectorNumElements();
4568 SDValue NewV = (Elt < (int)NumElems) ? SV->getOperand(0)
4569 : SV->getOperand(1);
4570 return getShuffleScalarElt(NewV.getNode(), Elt % NumElems, DAG, Depth+1);
4573 // Recurse into target specific vector shuffles to find scalars.
4574 if (isTargetShuffle(Opcode)) {
4575 MVT ShufVT = V.getValueType().getSimpleVT();
4576 unsigned NumElems = ShufVT.getVectorNumElements();
4577 SmallVector<int, 16> ShuffleMask;
4581 if (!getTargetShuffleMask(N, ShufVT, ShuffleMask, IsUnary))
4584 int Elt = ShuffleMask[Index];
4586 return DAG.getUNDEF(ShufVT.getVectorElementType());
4588 SDValue NewV = (Elt < (int)NumElems) ? N->getOperand(0)
4590 return getShuffleScalarElt(NewV.getNode(), Elt % NumElems, DAG,
4594 // Actual nodes that may contain scalar elements
4595 if (Opcode == ISD::BITCAST) {
4596 V = V.getOperand(0);
4597 EVT SrcVT = V.getValueType();
4598 unsigned NumElems = VT.getVectorNumElements();
4600 if (!SrcVT.isVector() || SrcVT.getVectorNumElements() != NumElems)
4604 if (V.getOpcode() == ISD::SCALAR_TO_VECTOR)
4605 return (Index == 0) ? V.getOperand(0)
4606 : DAG.getUNDEF(VT.getVectorElementType());
4608 if (V.getOpcode() == ISD::BUILD_VECTOR)
4609 return V.getOperand(Index);
4614 /// getNumOfConsecutiveZeros - Return the number of elements of a vector
4615 /// shuffle operation which come from a consecutively from a zero. The
4616 /// search can start in two different directions, from left or right.
4618 unsigned getNumOfConsecutiveZeros(ShuffleVectorSDNode *SVOp, unsigned NumElems,
4619 bool ZerosFromLeft, SelectionDAG &DAG) {
4621 for (i = 0; i != NumElems; ++i) {
4622 unsigned Index = ZerosFromLeft ? i : NumElems-i-1;
4623 SDValue Elt = getShuffleScalarElt(SVOp, Index, DAG, 0);
4624 if (!(Elt.getNode() &&
4625 (Elt.getOpcode() == ISD::UNDEF || X86::isZeroNode(Elt))))
4632 /// isShuffleMaskConsecutive - Check if the shuffle mask indicies [MaskI, MaskE)
4633 /// correspond consecutively to elements from one of the vector operands,
4634 /// starting from its index OpIdx. Also tell OpNum which source vector operand.
4636 bool isShuffleMaskConsecutive(ShuffleVectorSDNode *SVOp,
4637 unsigned MaskI, unsigned MaskE, unsigned OpIdx,
4638 unsigned NumElems, unsigned &OpNum) {
4639 bool SeenV1 = false;
4640 bool SeenV2 = false;
4642 for (unsigned i = MaskI; i != MaskE; ++i, ++OpIdx) {
4643 int Idx = SVOp->getMaskElt(i);
4644 // Ignore undef indicies
4648 if (Idx < (int)NumElems)
4653 // Only accept consecutive elements from the same vector
4654 if ((Idx % NumElems != OpIdx) || (SeenV1 && SeenV2))
4658 OpNum = SeenV1 ? 0 : 1;
4662 /// isVectorShiftRight - Returns true if the shuffle can be implemented as a
4663 /// logical left shift of a vector.
4664 static bool isVectorShiftRight(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
4665 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
4666 unsigned NumElems = SVOp->getValueType(0).getVectorNumElements();
4667 unsigned NumZeros = getNumOfConsecutiveZeros(SVOp, NumElems,
4668 false /* check zeros from right */, DAG);
4674 // Considering the elements in the mask that are not consecutive zeros,
4675 // check if they consecutively come from only one of the source vectors.
4677 // V1 = {X, A, B, C} 0
4679 // vector_shuffle V1, V2 <1, 2, 3, X>
4681 if (!isShuffleMaskConsecutive(SVOp,
4682 0, // Mask Start Index
4683 NumElems-NumZeros, // Mask End Index(exclusive)
4684 NumZeros, // Where to start looking in the src vector
4685 NumElems, // Number of elements in vector
4686 OpSrc)) // Which source operand ?
4691 ShVal = SVOp->getOperand(OpSrc);
4695 /// isVectorShiftLeft - Returns true if the shuffle can be implemented as a
4696 /// logical left shift of a vector.
4697 static bool isVectorShiftLeft(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
4698 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
4699 unsigned NumElems = SVOp->getValueType(0).getVectorNumElements();
4700 unsigned NumZeros = getNumOfConsecutiveZeros(SVOp, NumElems,
4701 true /* check zeros from left */, DAG);
4707 // Considering the elements in the mask that are not consecutive zeros,
4708 // check if they consecutively come from only one of the source vectors.
4710 // 0 { A, B, X, X } = V2
4712 // vector_shuffle V1, V2 <X, X, 4, 5>
4714 if (!isShuffleMaskConsecutive(SVOp,
4715 NumZeros, // Mask Start Index
4716 NumElems, // Mask End Index(exclusive)
4717 0, // Where to start looking in the src vector
4718 NumElems, // Number of elements in vector
4719 OpSrc)) // Which source operand ?
4724 ShVal = SVOp->getOperand(OpSrc);
4728 /// isVectorShift - Returns true if the shuffle can be implemented as a
4729 /// logical left or right shift of a vector.
4730 static bool isVectorShift(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
4731 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
4732 // Although the logic below support any bitwidth size, there are no
4733 // shift instructions which handle more than 128-bit vectors.
4734 if (!SVOp->getValueType(0).is128BitVector())
4737 if (isVectorShiftLeft(SVOp, DAG, isLeft, ShVal, ShAmt) ||
4738 isVectorShiftRight(SVOp, DAG, isLeft, ShVal, ShAmt))
4744 /// LowerBuildVectorv16i8 - Custom lower build_vector of v16i8.
4746 static SDValue LowerBuildVectorv16i8(SDValue Op, unsigned NonZeros,
4747 unsigned NumNonZero, unsigned NumZero,
4749 const X86Subtarget* Subtarget,
4750 const TargetLowering &TLI) {
4754 DebugLoc dl = Op.getDebugLoc();
4757 for (unsigned i = 0; i < 16; ++i) {
4758 bool ThisIsNonZero = (NonZeros & (1 << i)) != 0;
4759 if (ThisIsNonZero && First) {
4761 V = getZeroVector(MVT::v8i16, Subtarget, DAG, dl);
4763 V = DAG.getUNDEF(MVT::v8i16);
4768 SDValue ThisElt(0, 0), LastElt(0, 0);
4769 bool LastIsNonZero = (NonZeros & (1 << (i-1))) != 0;
4770 if (LastIsNonZero) {
4771 LastElt = DAG.getNode(ISD::ZERO_EXTEND, dl,
4772 MVT::i16, Op.getOperand(i-1));
4774 if (ThisIsNonZero) {
4775 ThisElt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, Op.getOperand(i));
4776 ThisElt = DAG.getNode(ISD::SHL, dl, MVT::i16,
4777 ThisElt, DAG.getConstant(8, MVT::i8));
4779 ThisElt = DAG.getNode(ISD::OR, dl, MVT::i16, ThisElt, LastElt);
4783 if (ThisElt.getNode())
4784 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, V, ThisElt,
4785 DAG.getIntPtrConstant(i/2));
4789 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V);
4792 /// LowerBuildVectorv8i16 - Custom lower build_vector of v8i16.
4794 static SDValue LowerBuildVectorv8i16(SDValue Op, unsigned NonZeros,
4795 unsigned NumNonZero, unsigned NumZero,
4797 const X86Subtarget* Subtarget,
4798 const TargetLowering &TLI) {
4802 DebugLoc dl = Op.getDebugLoc();
4805 for (unsigned i = 0; i < 8; ++i) {
4806 bool isNonZero = (NonZeros & (1 << i)) != 0;
4810 V = getZeroVector(MVT::v8i16, Subtarget, DAG, dl);
4812 V = DAG.getUNDEF(MVT::v8i16);
4815 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl,
4816 MVT::v8i16, V, Op.getOperand(i),
4817 DAG.getIntPtrConstant(i));
4824 /// getVShift - Return a vector logical shift node.
4826 static SDValue getVShift(bool isLeft, EVT VT, SDValue SrcOp,
4827 unsigned NumBits, SelectionDAG &DAG,
4828 const TargetLowering &TLI, DebugLoc dl) {
4829 assert(VT.is128BitVector() && "Unknown type for VShift");
4830 EVT ShVT = MVT::v2i64;
4831 unsigned Opc = isLeft ? X86ISD::VSHLDQ : X86ISD::VSRLDQ;
4832 SrcOp = DAG.getNode(ISD::BITCAST, dl, ShVT, SrcOp);
4833 return DAG.getNode(ISD::BITCAST, dl, VT,
4834 DAG.getNode(Opc, dl, ShVT, SrcOp,
4835 DAG.getConstant(NumBits,
4836 TLI.getShiftAmountTy(SrcOp.getValueType()))));
4840 X86TargetLowering::LowerAsSplatVectorLoad(SDValue SrcOp, EVT VT, DebugLoc dl,
4841 SelectionDAG &DAG) const {
4843 // Check if the scalar load can be widened into a vector load. And if
4844 // the address is "base + cst" see if the cst can be "absorbed" into
4845 // the shuffle mask.
4846 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(SrcOp)) {
4847 SDValue Ptr = LD->getBasePtr();
4848 if (!ISD::isNormalLoad(LD) || LD->isVolatile())
4850 EVT PVT = LD->getValueType(0);
4851 if (PVT != MVT::i32 && PVT != MVT::f32)
4856 if (FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr)) {
4857 FI = FINode->getIndex();
4859 } else if (DAG.isBaseWithConstantOffset(Ptr) &&
4860 isa<FrameIndexSDNode>(Ptr.getOperand(0))) {
4861 FI = cast<FrameIndexSDNode>(Ptr.getOperand(0))->getIndex();
4862 Offset = Ptr.getConstantOperandVal(1);
4863 Ptr = Ptr.getOperand(0);
4868 // FIXME: 256-bit vector instructions don't require a strict alignment,
4869 // improve this code to support it better.
4870 unsigned RequiredAlign = VT.getSizeInBits()/8;
4871 SDValue Chain = LD->getChain();
4872 // Make sure the stack object alignment is at least 16 or 32.
4873 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
4874 if (DAG.InferPtrAlignment(Ptr) < RequiredAlign) {
4875 if (MFI->isFixedObjectIndex(FI)) {
4876 // Can't change the alignment. FIXME: It's possible to compute
4877 // the exact stack offset and reference FI + adjust offset instead.
4878 // If someone *really* cares about this. That's the way to implement it.
4881 MFI->setObjectAlignment(FI, RequiredAlign);
4885 // (Offset % 16 or 32) must be multiple of 4. Then address is then
4886 // Ptr + (Offset & ~15).
4889 if ((Offset % RequiredAlign) & 3)
4891 int64_t StartOffset = Offset & ~(RequiredAlign-1);
4893 Ptr = DAG.getNode(ISD::ADD, Ptr.getDebugLoc(), Ptr.getValueType(),
4894 Ptr,DAG.getConstant(StartOffset, Ptr.getValueType()));
4896 int EltNo = (Offset - StartOffset) >> 2;
4897 unsigned NumElems = VT.getVectorNumElements();
4899 EVT NVT = EVT::getVectorVT(*DAG.getContext(), PVT, NumElems);
4900 SDValue V1 = DAG.getLoad(NVT, dl, Chain, Ptr,
4901 LD->getPointerInfo().getWithOffset(StartOffset),
4902 false, false, false, 0);
4904 SmallVector<int, 8> Mask;
4905 for (unsigned i = 0; i != NumElems; ++i)
4906 Mask.push_back(EltNo);
4908 return DAG.getVectorShuffle(NVT, dl, V1, DAG.getUNDEF(NVT), &Mask[0]);
4914 /// EltsFromConsecutiveLoads - Given the initializing elements 'Elts' of a
4915 /// vector of type 'VT', see if the elements can be replaced by a single large
4916 /// load which has the same value as a build_vector whose operands are 'elts'.
4918 /// Example: <load i32 *a, load i32 *a+4, undef, undef> -> zextload a
4920 /// FIXME: we'd also like to handle the case where the last elements are zero
4921 /// rather than undef via VZEXT_LOAD, but we do not detect that case today.
4922 /// There's even a handy isZeroNode for that purpose.
4923 static SDValue EltsFromConsecutiveLoads(EVT VT, SmallVectorImpl<SDValue> &Elts,
4924 DebugLoc &DL, SelectionDAG &DAG) {
4925 EVT EltVT = VT.getVectorElementType();
4926 unsigned NumElems = Elts.size();
4928 LoadSDNode *LDBase = NULL;
4929 unsigned LastLoadedElt = -1U;
4931 // For each element in the initializer, see if we've found a load or an undef.
4932 // If we don't find an initial load element, or later load elements are
4933 // non-consecutive, bail out.
4934 for (unsigned i = 0; i < NumElems; ++i) {
4935 SDValue Elt = Elts[i];
4937 if (!Elt.getNode() ||
4938 (Elt.getOpcode() != ISD::UNDEF && !ISD::isNON_EXTLoad(Elt.getNode())))
4941 if (Elt.getNode()->getOpcode() == ISD::UNDEF)
4943 LDBase = cast<LoadSDNode>(Elt.getNode());
4947 if (Elt.getOpcode() == ISD::UNDEF)
4950 LoadSDNode *LD = cast<LoadSDNode>(Elt);
4951 if (!DAG.isConsecutiveLoad(LD, LDBase, EltVT.getSizeInBits()/8, i))
4956 // If we have found an entire vector of loads and undefs, then return a large
4957 // load of the entire vector width starting at the base pointer. If we found
4958 // consecutive loads for the low half, generate a vzext_load node.
4959 if (LastLoadedElt == NumElems - 1) {
4960 if (DAG.InferPtrAlignment(LDBase->getBasePtr()) >= 16)
4961 return DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(),
4962 LDBase->getPointerInfo(),
4963 LDBase->isVolatile(), LDBase->isNonTemporal(),
4964 LDBase->isInvariant(), 0);
4965 return DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(),
4966 LDBase->getPointerInfo(),
4967 LDBase->isVolatile(), LDBase->isNonTemporal(),
4968 LDBase->isInvariant(), LDBase->getAlignment());
4970 if (NumElems == 4 && LastLoadedElt == 1 &&
4971 DAG.getTargetLoweringInfo().isTypeLegal(MVT::v2i64)) {
4972 SDVTList Tys = DAG.getVTList(MVT::v2i64, MVT::Other);
4973 SDValue Ops[] = { LDBase->getChain(), LDBase->getBasePtr() };
4975 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, DL, Tys, Ops, 2, MVT::i64,
4976 LDBase->getPointerInfo(),
4977 LDBase->getAlignment(),
4978 false/*isVolatile*/, true/*ReadMem*/,
4980 return DAG.getNode(ISD::BITCAST, DL, VT, ResNode);
4985 /// LowerVectorBroadcast - Attempt to use the vbroadcast instruction
4986 /// to generate a splat value for the following cases:
4987 /// 1. A splat BUILD_VECTOR which uses a single scalar load, or a constant.
4988 /// 2. A splat shuffle which uses a scalar_to_vector node which comes from
4989 /// a scalar load, or a constant.
4990 /// The VBROADCAST node is returned when a pattern is found,
4991 /// or SDValue() otherwise.
4993 X86TargetLowering::LowerVectorBroadcast(SDValue &Op, SelectionDAG &DAG) const {
4994 if (!Subtarget->hasAVX())
4997 EVT VT = Op.getValueType();
4998 DebugLoc dl = Op.getDebugLoc();
5000 assert((VT.is128BitVector() || VT.is256BitVector()) &&
5001 "Unsupported vector type for broadcast.");
5006 switch (Op.getOpcode()) {
5008 // Unknown pattern found.
5011 case ISD::BUILD_VECTOR: {
5012 // The BUILD_VECTOR node must be a splat.
5013 if (!isSplatVector(Op.getNode()))
5016 Ld = Op.getOperand(0);
5017 ConstSplatVal = (Ld.getOpcode() == ISD::Constant ||
5018 Ld.getOpcode() == ISD::ConstantFP);
5020 // The suspected load node has several users. Make sure that all
5021 // of its users are from the BUILD_VECTOR node.
5022 // Constants may have multiple users.
5023 if (!ConstSplatVal && !Ld->hasNUsesOfValue(VT.getVectorNumElements(), 0))
5028 case ISD::VECTOR_SHUFFLE: {
5029 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
5031 // Shuffles must have a splat mask where the first element is
5033 if ((!SVOp->isSplat()) || SVOp->getMaskElt(0) != 0)
5036 SDValue Sc = Op.getOperand(0);
5037 if (Sc.getOpcode() != ISD::SCALAR_TO_VECTOR &&
5038 Sc.getOpcode() != ISD::BUILD_VECTOR) {
5040 if (!Subtarget->hasAVX2())
5043 // Use the register form of the broadcast instruction available on AVX2.
5044 if (VT.is256BitVector())
5045 Sc = Extract128BitVector(Sc, 0, DAG, dl);
5046 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Sc);
5049 Ld = Sc.getOperand(0);
5050 ConstSplatVal = (Ld.getOpcode() == ISD::Constant ||
5051 Ld.getOpcode() == ISD::ConstantFP);
5053 // The scalar_to_vector node and the suspected
5054 // load node must have exactly one user.
5055 // Constants may have multiple users.
5056 if (!ConstSplatVal && (!Sc.hasOneUse() || !Ld.hasOneUse()))
5062 bool Is256 = VT.is256BitVector();
5064 // Handle the broadcasting a single constant scalar from the constant pool
5065 // into a vector. On Sandybridge it is still better to load a constant vector
5066 // from the constant pool and not to broadcast it from a scalar.
5067 if (ConstSplatVal && Subtarget->hasAVX2()) {
5068 EVT CVT = Ld.getValueType();
5069 assert(!CVT.isVector() && "Must not broadcast a vector type");
5070 unsigned ScalarSize = CVT.getSizeInBits();
5072 if (ScalarSize == 32 || (Is256 && ScalarSize == 64)) {
5073 const Constant *C = 0;
5074 if (ConstantSDNode *CI = dyn_cast<ConstantSDNode>(Ld))
5075 C = CI->getConstantIntValue();
5076 else if (ConstantFPSDNode *CF = dyn_cast<ConstantFPSDNode>(Ld))
5077 C = CF->getConstantFPValue();
5079 assert(C && "Invalid constant type");
5081 SDValue CP = DAG.getConstantPool(C, getPointerTy());
5082 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
5083 Ld = DAG.getLoad(CVT, dl, DAG.getEntryNode(), CP,
5084 MachinePointerInfo::getConstantPool(),
5085 false, false, false, Alignment);
5087 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5091 bool IsLoad = ISD::isNormalLoad(Ld.getNode());
5092 unsigned ScalarSize = Ld.getValueType().getSizeInBits();
5094 // Handle AVX2 in-register broadcasts.
5095 if (!IsLoad && Subtarget->hasAVX2() &&
5096 (ScalarSize == 32 || (Is256 && ScalarSize == 64)))
5097 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5099 // The scalar source must be a normal load.
5103 if (ScalarSize == 32 || (Is256 && ScalarSize == 64))
5104 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5106 // The integer check is needed for the 64-bit into 128-bit so it doesn't match
5107 // double since there is no vbroadcastsd xmm
5108 if (Subtarget->hasAVX2() && Ld.getValueType().isInteger()) {
5109 if (ScalarSize == 8 || ScalarSize == 16 || ScalarSize == 64)
5110 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5113 // Unsupported broadcast.
5118 X86TargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const {
5119 DebugLoc dl = Op.getDebugLoc();
5121 EVT VT = Op.getValueType();
5122 EVT ExtVT = VT.getVectorElementType();
5123 unsigned NumElems = Op.getNumOperands();
5125 // Vectors containing all zeros can be matched by pxor and xorps later
5126 if (ISD::isBuildVectorAllZeros(Op.getNode())) {
5127 // Canonicalize this to <4 x i32> to 1) ensure the zero vectors are CSE'd
5128 // and 2) ensure that i64 scalars are eliminated on x86-32 hosts.
5129 if (VT == MVT::v4i32 || VT == MVT::v8i32)
5132 return getZeroVector(VT, Subtarget, DAG, dl);
5135 // Vectors containing all ones can be matched by pcmpeqd on 128-bit width
5136 // vectors or broken into v4i32 operations on 256-bit vectors. AVX2 can use
5137 // vpcmpeqd on 256-bit vectors.
5138 if (ISD::isBuildVectorAllOnes(Op.getNode())) {
5139 if (VT == MVT::v4i32 || (VT == MVT::v8i32 && Subtarget->hasAVX2()))
5142 return getOnesVector(VT, Subtarget->hasAVX2(), DAG, dl);
5145 SDValue Broadcast = LowerVectorBroadcast(Op, DAG);
5146 if (Broadcast.getNode())
5149 unsigned EVTBits = ExtVT.getSizeInBits();
5151 unsigned NumZero = 0;
5152 unsigned NumNonZero = 0;
5153 unsigned NonZeros = 0;
5154 bool IsAllConstants = true;
5155 SmallSet<SDValue, 8> Values;
5156 for (unsigned i = 0; i < NumElems; ++i) {
5157 SDValue Elt = Op.getOperand(i);
5158 if (Elt.getOpcode() == ISD::UNDEF)
5161 if (Elt.getOpcode() != ISD::Constant &&
5162 Elt.getOpcode() != ISD::ConstantFP)
5163 IsAllConstants = false;
5164 if (X86::isZeroNode(Elt))
5167 NonZeros |= (1 << i);
5172 // All undef vector. Return an UNDEF. All zero vectors were handled above.
5173 if (NumNonZero == 0)
5174 return DAG.getUNDEF(VT);
5176 // Special case for single non-zero, non-undef, element.
5177 if (NumNonZero == 1) {
5178 unsigned Idx = CountTrailingZeros_32(NonZeros);
5179 SDValue Item = Op.getOperand(Idx);
5181 // If this is an insertion of an i64 value on x86-32, and if the top bits of
5182 // the value are obviously zero, truncate the value to i32 and do the
5183 // insertion that way. Only do this if the value is non-constant or if the
5184 // value is a constant being inserted into element 0. It is cheaper to do
5185 // a constant pool load than it is to do a movd + shuffle.
5186 if (ExtVT == MVT::i64 && !Subtarget->is64Bit() &&
5187 (!IsAllConstants || Idx == 0)) {
5188 if (DAG.MaskedValueIsZero(Item, APInt::getBitsSet(64, 32, 64))) {
5190 assert(VT == MVT::v2i64 && "Expected an SSE value type!");
5191 EVT VecVT = MVT::v4i32;
5192 unsigned VecElts = 4;
5194 // Truncate the value (which may itself be a constant) to i32, and
5195 // convert it to a vector with movd (S2V+shuffle to zero extend).
5196 Item = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Item);
5197 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Item);
5198 Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
5200 // Now we have our 32-bit value zero extended in the low element of
5201 // a vector. If Idx != 0, swizzle it into place.
5203 SmallVector<int, 4> Mask;
5204 Mask.push_back(Idx);
5205 for (unsigned i = 1; i != VecElts; ++i)
5207 Item = DAG.getVectorShuffle(VecVT, dl, Item, DAG.getUNDEF(VecVT),
5210 return DAG.getNode(ISD::BITCAST, dl, VT, Item);
5214 // If we have a constant or non-constant insertion into the low element of
5215 // a vector, we can do this with SCALAR_TO_VECTOR + shuffle of zero into
5216 // the rest of the elements. This will be matched as movd/movq/movss/movsd
5217 // depending on what the source datatype is.
5220 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
5222 if (ExtVT == MVT::i32 || ExtVT == MVT::f32 || ExtVT == MVT::f64 ||
5223 (ExtVT == MVT::i64 && Subtarget->is64Bit())) {
5224 if (VT.is256BitVector()) {
5225 SDValue ZeroVec = getZeroVector(VT, Subtarget, DAG, dl);
5226 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, ZeroVec,
5227 Item, DAG.getIntPtrConstant(0));
5229 assert(VT.is128BitVector() && "Expected an SSE value type!");
5230 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
5231 // Turn it into a MOVL (i.e. movss, movsd, or movd) to a zero vector.
5232 return getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
5235 if (ExtVT == MVT::i16 || ExtVT == MVT::i8) {
5236 Item = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Item);
5237 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, Item);
5238 if (VT.is256BitVector()) {
5239 SDValue ZeroVec = getZeroVector(MVT::v8i32, Subtarget, DAG, dl);
5240 Item = Insert128BitVector(ZeroVec, Item, 0, DAG, dl);
5242 assert(VT.is128BitVector() && "Expected an SSE value type!");
5243 Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
5245 return DAG.getNode(ISD::BITCAST, dl, VT, Item);
5249 // Is it a vector logical left shift?
5250 if (NumElems == 2 && Idx == 1 &&
5251 X86::isZeroNode(Op.getOperand(0)) &&
5252 !X86::isZeroNode(Op.getOperand(1))) {
5253 unsigned NumBits = VT.getSizeInBits();
5254 return getVShift(true, VT,
5255 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
5256 VT, Op.getOperand(1)),
5257 NumBits/2, DAG, *this, dl);
5260 if (IsAllConstants) // Otherwise, it's better to do a constpool load.
5263 // Otherwise, if this is a vector with i32 or f32 elements, and the element
5264 // is a non-constant being inserted into an element other than the low one,
5265 // we can't use a constant pool load. Instead, use SCALAR_TO_VECTOR (aka
5266 // movd/movss) to move this into the low element, then shuffle it into
5268 if (EVTBits == 32) {
5269 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
5271 // Turn it into a shuffle of zero and zero-extended scalar to vector.
5272 Item = getShuffleVectorZeroOrUndef(Item, 0, NumZero > 0, Subtarget, DAG);
5273 SmallVector<int, 8> MaskVec;
5274 for (unsigned i = 0; i != NumElems; ++i)
5275 MaskVec.push_back(i == Idx ? 0 : 1);
5276 return DAG.getVectorShuffle(VT, dl, Item, DAG.getUNDEF(VT), &MaskVec[0]);
5280 // Splat is obviously ok. Let legalizer expand it to a shuffle.
5281 if (Values.size() == 1) {
5282 if (EVTBits == 32) {
5283 // Instead of a shuffle like this:
5284 // shuffle (scalar_to_vector (load (ptr + 4))), undef, <0, 0, 0, 0>
5285 // Check if it's possible to issue this instead.
5286 // shuffle (vload ptr)), undef, <1, 1, 1, 1>
5287 unsigned Idx = CountTrailingZeros_32(NonZeros);
5288 SDValue Item = Op.getOperand(Idx);
5289 if (Op.getNode()->isOnlyUserOf(Item.getNode()))
5290 return LowerAsSplatVectorLoad(Item, VT, dl, DAG);
5295 // A vector full of immediates; various special cases are already
5296 // handled, so this is best done with a single constant-pool load.
5300 // For AVX-length vectors, build the individual 128-bit pieces and use
5301 // shuffles to put them in place.
5302 if (VT.is256BitVector()) {
5303 SmallVector<SDValue, 32> V;
5304 for (unsigned i = 0; i != NumElems; ++i)
5305 V.push_back(Op.getOperand(i));
5307 EVT HVT = EVT::getVectorVT(*DAG.getContext(), ExtVT, NumElems/2);
5309 // Build both the lower and upper subvector.
5310 SDValue Lower = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT, &V[0], NumElems/2);
5311 SDValue Upper = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT, &V[NumElems / 2],
5314 // Recreate the wider vector with the lower and upper part.
5315 return Concat128BitVectors(Lower, Upper, VT, NumElems, DAG, dl);
5318 // Let legalizer expand 2-wide build_vectors.
5319 if (EVTBits == 64) {
5320 if (NumNonZero == 1) {
5321 // One half is zero or undef.
5322 unsigned Idx = CountTrailingZeros_32(NonZeros);
5323 SDValue V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT,
5324 Op.getOperand(Idx));
5325 return getShuffleVectorZeroOrUndef(V2, Idx, true, Subtarget, DAG);
5330 // If element VT is < 32 bits, convert it to inserts into a zero vector.
5331 if (EVTBits == 8 && NumElems == 16) {
5332 SDValue V = LowerBuildVectorv16i8(Op, NonZeros,NumNonZero,NumZero, DAG,
5334 if (V.getNode()) return V;
5337 if (EVTBits == 16 && NumElems == 8) {
5338 SDValue V = LowerBuildVectorv8i16(Op, NonZeros,NumNonZero,NumZero, DAG,
5340 if (V.getNode()) return V;
5343 // If element VT is == 32 bits, turn it into a number of shuffles.
5344 SmallVector<SDValue, 8> V(NumElems);
5345 if (NumElems == 4 && NumZero > 0) {
5346 for (unsigned i = 0; i < 4; ++i) {
5347 bool isZero = !(NonZeros & (1 << i));
5349 V[i] = getZeroVector(VT, Subtarget, DAG, dl);
5351 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
5354 for (unsigned i = 0; i < 2; ++i) {
5355 switch ((NonZeros & (0x3 << i*2)) >> (i*2)) {
5358 V[i] = V[i*2]; // Must be a zero vector.
5361 V[i] = getMOVL(DAG, dl, VT, V[i*2+1], V[i*2]);
5364 V[i] = getMOVL(DAG, dl, VT, V[i*2], V[i*2+1]);
5367 V[i] = getUnpackl(DAG, dl, VT, V[i*2], V[i*2+1]);
5372 bool Reverse1 = (NonZeros & 0x3) == 2;
5373 bool Reverse2 = ((NonZeros & (0x3 << 2)) >> 2) == 2;
5377 static_cast<int>(Reverse2 ? NumElems+1 : NumElems),
5378 static_cast<int>(Reverse2 ? NumElems : NumElems+1)
5380 return DAG.getVectorShuffle(VT, dl, V[0], V[1], &MaskVec[0]);
5383 if (Values.size() > 1 && VT.is128BitVector()) {
5384 // Check for a build vector of consecutive loads.
5385 for (unsigned i = 0; i < NumElems; ++i)
5386 V[i] = Op.getOperand(i);
5388 // Check for elements which are consecutive loads.
5389 SDValue LD = EltsFromConsecutiveLoads(VT, V, dl, DAG);
5393 // For SSE 4.1, use insertps to put the high elements into the low element.
5394 if (getSubtarget()->hasSSE41()) {
5396 if (Op.getOperand(0).getOpcode() != ISD::UNDEF)
5397 Result = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(0));
5399 Result = DAG.getUNDEF(VT);
5401 for (unsigned i = 1; i < NumElems; ++i) {
5402 if (Op.getOperand(i).getOpcode() == ISD::UNDEF) continue;
5403 Result = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Result,
5404 Op.getOperand(i), DAG.getIntPtrConstant(i));
5409 // Otherwise, expand into a number of unpckl*, start by extending each of
5410 // our (non-undef) elements to the full vector width with the element in the
5411 // bottom slot of the vector (which generates no code for SSE).
5412 for (unsigned i = 0; i < NumElems; ++i) {
5413 if (Op.getOperand(i).getOpcode() != ISD::UNDEF)
5414 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
5416 V[i] = DAG.getUNDEF(VT);
5419 // Next, we iteratively mix elements, e.g. for v4f32:
5420 // Step 1: unpcklps 0, 2 ==> X: <?, ?, 2, 0>
5421 // : unpcklps 1, 3 ==> Y: <?, ?, 3, 1>
5422 // Step 2: unpcklps X, Y ==> <3, 2, 1, 0>
5423 unsigned EltStride = NumElems >> 1;
5424 while (EltStride != 0) {
5425 for (unsigned i = 0; i < EltStride; ++i) {
5426 // If V[i+EltStride] is undef and this is the first round of mixing,
5427 // then it is safe to just drop this shuffle: V[i] is already in the
5428 // right place, the one element (since it's the first round) being
5429 // inserted as undef can be dropped. This isn't safe for successive
5430 // rounds because they will permute elements within both vectors.
5431 if (V[i+EltStride].getOpcode() == ISD::UNDEF &&
5432 EltStride == NumElems/2)
5435 V[i] = getUnpackl(DAG, dl, VT, V[i], V[i + EltStride]);
5444 // LowerAVXCONCAT_VECTORS - 256-bit AVX can use the vinsertf128 instruction
5445 // to create 256-bit vectors from two other 128-bit ones.
5446 static SDValue LowerAVXCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
5447 DebugLoc dl = Op.getDebugLoc();
5448 EVT ResVT = Op.getValueType();
5450 assert(ResVT.is256BitVector() && "Value type must be 256-bit wide");
5452 SDValue V1 = Op.getOperand(0);
5453 SDValue V2 = Op.getOperand(1);
5454 unsigned NumElems = ResVT.getVectorNumElements();
5456 return Concat128BitVectors(V1, V2, ResVT, NumElems, DAG, dl);
5460 X86TargetLowering::LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) const {
5461 assert(Op.getNumOperands() == 2);
5463 // 256-bit AVX can use the vinsertf128 instruction to create 256-bit vectors
5464 // from two other 128-bit ones.
5465 return LowerAVXCONCAT_VECTORS(Op, DAG);
5468 // Try to lower a shuffle node into a simple blend instruction.
5469 static SDValue LowerVECTOR_SHUFFLEtoBlend(ShuffleVectorSDNode *SVOp,
5470 const X86Subtarget *Subtarget,
5471 SelectionDAG &DAG) {
5472 SDValue V1 = SVOp->getOperand(0);
5473 SDValue V2 = SVOp->getOperand(1);
5474 DebugLoc dl = SVOp->getDebugLoc();
5475 MVT VT = SVOp->getValueType(0).getSimpleVT();
5476 unsigned NumElems = VT.getVectorNumElements();
5478 if (!Subtarget->hasSSE41())
5484 switch (VT.SimpleTy) {
5485 default: return SDValue();
5487 ISDNo = X86ISD::BLENDPW;
5492 ISDNo = X86ISD::BLENDPS;
5497 ISDNo = X86ISD::BLENDPD;
5502 if (!Subtarget->hasAVX())
5504 ISDNo = X86ISD::BLENDPS;
5509 if (!Subtarget->hasAVX())
5511 ISDNo = X86ISD::BLENDPD;
5515 assert(ISDNo && "Invalid Op Number");
5517 unsigned MaskVals = 0;
5519 for (unsigned i = 0; i != NumElems; ++i) {
5520 int EltIdx = SVOp->getMaskElt(i);
5521 if (EltIdx == (int)i || EltIdx < 0)
5523 else if (EltIdx == (int)(i + NumElems))
5524 continue; // Bit is set to zero;
5529 V1 = DAG.getNode(ISD::BITCAST, dl, OpTy, V1);
5530 V2 = DAG.getNode(ISD::BITCAST, dl, OpTy, V2);
5531 SDValue Ret = DAG.getNode(ISDNo, dl, OpTy, V1, V2,
5532 DAG.getConstant(MaskVals, MVT::i32));
5533 return DAG.getNode(ISD::BITCAST, dl, VT, Ret);
5536 // v8i16 shuffles - Prefer shuffles in the following order:
5537 // 1. [all] pshuflw, pshufhw, optional move
5538 // 2. [ssse3] 1 x pshufb
5539 // 3. [ssse3] 2 x pshufb + 1 x por
5540 // 4. [all] mov + pshuflw + pshufhw + N x (pextrw + pinsrw)
5542 X86TargetLowering::LowerVECTOR_SHUFFLEv8i16(SDValue Op,
5543 SelectionDAG &DAG) const {
5544 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
5545 SDValue V1 = SVOp->getOperand(0);
5546 SDValue V2 = SVOp->getOperand(1);
5547 DebugLoc dl = SVOp->getDebugLoc();
5548 SmallVector<int, 8> MaskVals;
5550 // Determine if more than 1 of the words in each of the low and high quadwords
5551 // of the result come from the same quadword of one of the two inputs. Undef
5552 // mask values count as coming from any quadword, for better codegen.
5553 unsigned LoQuad[] = { 0, 0, 0, 0 };
5554 unsigned HiQuad[] = { 0, 0, 0, 0 };
5555 std::bitset<4> InputQuads;
5556 for (unsigned i = 0; i < 8; ++i) {
5557 unsigned *Quad = i < 4 ? LoQuad : HiQuad;
5558 int EltIdx = SVOp->getMaskElt(i);
5559 MaskVals.push_back(EltIdx);
5568 InputQuads.set(EltIdx / 4);
5571 int BestLoQuad = -1;
5572 unsigned MaxQuad = 1;
5573 for (unsigned i = 0; i < 4; ++i) {
5574 if (LoQuad[i] > MaxQuad) {
5576 MaxQuad = LoQuad[i];
5580 int BestHiQuad = -1;
5582 for (unsigned i = 0; i < 4; ++i) {
5583 if (HiQuad[i] > MaxQuad) {
5585 MaxQuad = HiQuad[i];
5589 // For SSSE3, If all 8 words of the result come from only 1 quadword of each
5590 // of the two input vectors, shuffle them into one input vector so only a
5591 // single pshufb instruction is necessary. If There are more than 2 input
5592 // quads, disable the next transformation since it does not help SSSE3.
5593 bool V1Used = InputQuads[0] || InputQuads[1];
5594 bool V2Used = InputQuads[2] || InputQuads[3];
5595 if (Subtarget->hasSSSE3()) {
5596 if (InputQuads.count() == 2 && V1Used && V2Used) {
5597 BestLoQuad = InputQuads[0] ? 0 : 1;
5598 BestHiQuad = InputQuads[2] ? 2 : 3;
5600 if (InputQuads.count() > 2) {
5606 // If BestLoQuad or BestHiQuad are set, shuffle the quads together and update
5607 // the shuffle mask. If a quad is scored as -1, that means that it contains
5608 // words from all 4 input quadwords.
5610 if (BestLoQuad >= 0 || BestHiQuad >= 0) {
5612 BestLoQuad < 0 ? 0 : BestLoQuad,
5613 BestHiQuad < 0 ? 1 : BestHiQuad
5615 NewV = DAG.getVectorShuffle(MVT::v2i64, dl,
5616 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, V1),
5617 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, V2), &MaskV[0]);
5618 NewV = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, NewV);
5620 // Rewrite the MaskVals and assign NewV to V1 if NewV now contains all the
5621 // source words for the shuffle, to aid later transformations.
5622 bool AllWordsInNewV = true;
5623 bool InOrder[2] = { true, true };
5624 for (unsigned i = 0; i != 8; ++i) {
5625 int idx = MaskVals[i];
5627 InOrder[i/4] = false;
5628 if (idx < 0 || (idx/4) == BestLoQuad || (idx/4) == BestHiQuad)
5630 AllWordsInNewV = false;
5634 bool pshuflw = AllWordsInNewV, pshufhw = AllWordsInNewV;
5635 if (AllWordsInNewV) {
5636 for (int i = 0; i != 8; ++i) {
5637 int idx = MaskVals[i];
5640 idx = MaskVals[i] = (idx / 4) == BestLoQuad ? (idx & 3) : (idx & 3) + 4;
5641 if ((idx != i) && idx < 4)
5643 if ((idx != i) && idx > 3)
5652 // If we've eliminated the use of V2, and the new mask is a pshuflw or
5653 // pshufhw, that's as cheap as it gets. Return the new shuffle.
5654 if ((pshufhw && InOrder[0]) || (pshuflw && InOrder[1])) {
5655 unsigned Opc = pshufhw ? X86ISD::PSHUFHW : X86ISD::PSHUFLW;
5656 unsigned TargetMask = 0;
5657 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV,
5658 DAG.getUNDEF(MVT::v8i16), &MaskVals[0]);
5659 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode());
5660 TargetMask = pshufhw ? getShufflePSHUFHWImmediate(SVOp):
5661 getShufflePSHUFLWImmediate(SVOp);
5662 V1 = NewV.getOperand(0);
5663 return getTargetShuffleNode(Opc, dl, MVT::v8i16, V1, TargetMask, DAG);
5667 // If we have SSSE3, and all words of the result are from 1 input vector,
5668 // case 2 is generated, otherwise case 3 is generated. If no SSSE3
5669 // is present, fall back to case 4.
5670 if (Subtarget->hasSSSE3()) {
5671 SmallVector<SDValue,16> pshufbMask;
5673 // If we have elements from both input vectors, set the high bit of the
5674 // shuffle mask element to zero out elements that come from V2 in the V1
5675 // mask, and elements that come from V1 in the V2 mask, so that the two
5676 // results can be OR'd together.
5677 bool TwoInputs = V1Used && V2Used;
5678 for (unsigned i = 0; i != 8; ++i) {
5679 int EltIdx = MaskVals[i] * 2;
5680 int Idx0 = (TwoInputs && (EltIdx >= 16)) ? 0x80 : EltIdx;
5681 int Idx1 = (TwoInputs && (EltIdx >= 16)) ? 0x80 : EltIdx+1;
5682 pshufbMask.push_back(DAG.getConstant(Idx0, MVT::i8));
5683 pshufbMask.push_back(DAG.getConstant(Idx1, MVT::i8));
5685 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V1);
5686 V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1,
5687 DAG.getNode(ISD::BUILD_VECTOR, dl,
5688 MVT::v16i8, &pshufbMask[0], 16));
5690 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
5692 // Calculate the shuffle mask for the second input, shuffle it, and
5693 // OR it with the first shuffled input.
5695 for (unsigned i = 0; i != 8; ++i) {
5696 int EltIdx = MaskVals[i] * 2;
5697 int Idx0 = (EltIdx < 16) ? 0x80 : EltIdx - 16;
5698 int Idx1 = (EltIdx < 16) ? 0x80 : EltIdx - 15;
5699 pshufbMask.push_back(DAG.getConstant(Idx0, MVT::i8));
5700 pshufbMask.push_back(DAG.getConstant(Idx1, MVT::i8));
5702 V2 = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V2);
5703 V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2,
5704 DAG.getNode(ISD::BUILD_VECTOR, dl,
5705 MVT::v16i8, &pshufbMask[0], 16));
5706 V1 = DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
5707 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
5710 // If BestLoQuad >= 0, generate a pshuflw to put the low elements in order,
5711 // and update MaskVals with new element order.
5712 std::bitset<8> InOrder;
5713 if (BestLoQuad >= 0) {
5714 int MaskV[] = { -1, -1, -1, -1, 4, 5, 6, 7 };
5715 for (int i = 0; i != 4; ++i) {
5716 int idx = MaskVals[i];
5719 } else if ((idx / 4) == BestLoQuad) {
5724 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16),
5727 if (NewV.getOpcode() == ISD::VECTOR_SHUFFLE && Subtarget->hasSSSE3()) {
5728 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode());
5729 NewV = getTargetShuffleNode(X86ISD::PSHUFLW, dl, MVT::v8i16,
5731 getShufflePSHUFLWImmediate(SVOp), DAG);
5735 // If BestHi >= 0, generate a pshufhw to put the high elements in order,
5736 // and update MaskVals with the new element order.
5737 if (BestHiQuad >= 0) {
5738 int MaskV[] = { 0, 1, 2, 3, -1, -1, -1, -1 };
5739 for (unsigned i = 4; i != 8; ++i) {
5740 int idx = MaskVals[i];
5743 } else if ((idx / 4) == BestHiQuad) {
5744 MaskV[i] = (idx & 3) + 4;
5748 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16),
5751 if (NewV.getOpcode() == ISD::VECTOR_SHUFFLE && Subtarget->hasSSSE3()) {
5752 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode());
5753 NewV = getTargetShuffleNode(X86ISD::PSHUFHW, dl, MVT::v8i16,
5755 getShufflePSHUFHWImmediate(SVOp), DAG);
5759 // In case BestHi & BestLo were both -1, which means each quadword has a word
5760 // from each of the four input quadwords, calculate the InOrder bitvector now
5761 // before falling through to the insert/extract cleanup.
5762 if (BestLoQuad == -1 && BestHiQuad == -1) {
5764 for (int i = 0; i != 8; ++i)
5765 if (MaskVals[i] < 0 || MaskVals[i] == i)
5769 // The other elements are put in the right place using pextrw and pinsrw.
5770 for (unsigned i = 0; i != 8; ++i) {
5773 int EltIdx = MaskVals[i];
5776 SDValue ExtOp = (EltIdx < 8) ?
5777 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V1,
5778 DAG.getIntPtrConstant(EltIdx)) :
5779 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V2,
5780 DAG.getIntPtrConstant(EltIdx - 8));
5781 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, ExtOp,
5782 DAG.getIntPtrConstant(i));
5787 // v16i8 shuffles - Prefer shuffles in the following order:
5788 // 1. [ssse3] 1 x pshufb
5789 // 2. [ssse3] 2 x pshufb + 1 x por
5790 // 3. [all] v8i16 shuffle + N x pextrw + rotate + pinsrw
5792 SDValue LowerVECTOR_SHUFFLEv16i8(ShuffleVectorSDNode *SVOp,
5794 const X86TargetLowering &TLI) {
5795 SDValue V1 = SVOp->getOperand(0);
5796 SDValue V2 = SVOp->getOperand(1);
5797 DebugLoc dl = SVOp->getDebugLoc();
5798 ArrayRef<int> MaskVals = SVOp->getMask();
5800 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
5802 // If we have SSSE3, case 1 is generated when all result bytes come from
5803 // one of the inputs. Otherwise, case 2 is generated. If no SSSE3 is
5804 // present, fall back to case 3.
5806 // If SSSE3, use 1 pshufb instruction per vector with elements in the result.
5807 if (TLI.getSubtarget()->hasSSSE3()) {
5808 SmallVector<SDValue,16> pshufbMask;
5810 // If all result elements are from one input vector, then only translate
5811 // undef mask values to 0x80 (zero out result) in the pshufb mask.
5813 // Otherwise, we have elements from both input vectors, and must zero out
5814 // elements that come from V2 in the first mask, and V1 in the second mask
5815 // so that we can OR them together.
5816 for (unsigned i = 0; i != 16; ++i) {
5817 int EltIdx = MaskVals[i];
5818 if (EltIdx < 0 || EltIdx >= 16)
5820 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
5822 V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1,
5823 DAG.getNode(ISD::BUILD_VECTOR, dl,
5824 MVT::v16i8, &pshufbMask[0], 16));
5828 // Calculate the shuffle mask for the second input, shuffle it, and
5829 // OR it with the first shuffled input.
5831 for (unsigned i = 0; i != 16; ++i) {
5832 int EltIdx = MaskVals[i];
5833 EltIdx = (EltIdx < 16) ? 0x80 : EltIdx - 16;
5834 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
5836 V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2,
5837 DAG.getNode(ISD::BUILD_VECTOR, dl,
5838 MVT::v16i8, &pshufbMask[0], 16));
5839 return DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
5842 // No SSSE3 - Calculate in place words and then fix all out of place words
5843 // With 0-16 extracts & inserts. Worst case is 16 bytes out of order from
5844 // the 16 different words that comprise the two doublequadword input vectors.
5845 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
5846 V2 = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V2);
5848 for (int i = 0; i != 8; ++i) {
5849 int Elt0 = MaskVals[i*2];
5850 int Elt1 = MaskVals[i*2+1];
5852 // This word of the result is all undef, skip it.
5853 if (Elt0 < 0 && Elt1 < 0)
5856 // This word of the result is already in the correct place, skip it.
5857 if ((Elt0 == i*2) && (Elt1 == i*2+1))
5860 SDValue Elt0Src = Elt0 < 16 ? V1 : V2;
5861 SDValue Elt1Src = Elt1 < 16 ? V1 : V2;
5864 // If Elt0 and Elt1 are defined, are consecutive, and can be load
5865 // using a single extract together, load it and store it.
5866 if ((Elt0 >= 0) && ((Elt0 + 1) == Elt1) && ((Elt0 & 1) == 0)) {
5867 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src,
5868 DAG.getIntPtrConstant(Elt1 / 2));
5869 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt,
5870 DAG.getIntPtrConstant(i));
5874 // If Elt1 is defined, extract it from the appropriate source. If the
5875 // source byte is not also odd, shift the extracted word left 8 bits
5876 // otherwise clear the bottom 8 bits if we need to do an or.
5878 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src,
5879 DAG.getIntPtrConstant(Elt1 / 2));
5880 if ((Elt1 & 1) == 0)
5881 InsElt = DAG.getNode(ISD::SHL, dl, MVT::i16, InsElt,
5883 TLI.getShiftAmountTy(InsElt.getValueType())));
5885 InsElt = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt,
5886 DAG.getConstant(0xFF00, MVT::i16));
5888 // If Elt0 is defined, extract it from the appropriate source. If the
5889 // source byte is not also even, shift the extracted word right 8 bits. If
5890 // Elt1 was also defined, OR the extracted values together before
5891 // inserting them in the result.
5893 SDValue InsElt0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16,
5894 Elt0Src, DAG.getIntPtrConstant(Elt0 / 2));
5895 if ((Elt0 & 1) != 0)
5896 InsElt0 = DAG.getNode(ISD::SRL, dl, MVT::i16, InsElt0,
5898 TLI.getShiftAmountTy(InsElt0.getValueType())));
5900 InsElt0 = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt0,
5901 DAG.getConstant(0x00FF, MVT::i16));
5902 InsElt = Elt1 >= 0 ? DAG.getNode(ISD::OR, dl, MVT::i16, InsElt, InsElt0)
5905 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt,
5906 DAG.getIntPtrConstant(i));
5908 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, NewV);
5911 /// RewriteAsNarrowerShuffle - Try rewriting v8i16 and v16i8 shuffles as 4 wide
5912 /// ones, or rewriting v4i32 / v4f32 as 2 wide ones if possible. This can be
5913 /// done when every pair / quad of shuffle mask elements point to elements in
5914 /// the right sequence. e.g.
5915 /// vector_shuffle X, Y, <2, 3, | 10, 11, | 0, 1, | 14, 15>
5917 SDValue RewriteAsNarrowerShuffle(ShuffleVectorSDNode *SVOp,
5918 SelectionDAG &DAG, DebugLoc dl) {
5919 MVT VT = SVOp->getValueType(0).getSimpleVT();
5920 unsigned NumElems = VT.getVectorNumElements();
5923 switch (VT.SimpleTy) {
5924 default: llvm_unreachable("Unexpected!");
5925 case MVT::v4f32: NewVT = MVT::v2f64; Scale = 2; break;
5926 case MVT::v4i32: NewVT = MVT::v2i64; Scale = 2; break;
5927 case MVT::v8i16: NewVT = MVT::v4i32; Scale = 2; break;
5928 case MVT::v16i8: NewVT = MVT::v4i32; Scale = 4; break;
5929 case MVT::v16i16: NewVT = MVT::v8i32; Scale = 2; break;
5930 case MVT::v32i8: NewVT = MVT::v8i32; Scale = 4; break;
5933 SmallVector<int, 8> MaskVec;
5934 for (unsigned i = 0; i != NumElems; i += Scale) {
5936 for (unsigned j = 0; j != Scale; ++j) {
5937 int EltIdx = SVOp->getMaskElt(i+j);
5941 StartIdx = (EltIdx / Scale);
5942 if (EltIdx != (int)(StartIdx*Scale + j))
5945 MaskVec.push_back(StartIdx);
5948 SDValue V1 = DAG.getNode(ISD::BITCAST, dl, NewVT, SVOp->getOperand(0));
5949 SDValue V2 = DAG.getNode(ISD::BITCAST, dl, NewVT, SVOp->getOperand(1));
5950 return DAG.getVectorShuffle(NewVT, dl, V1, V2, &MaskVec[0]);
5953 /// getVZextMovL - Return a zero-extending vector move low node.
5955 static SDValue getVZextMovL(EVT VT, EVT OpVT,
5956 SDValue SrcOp, SelectionDAG &DAG,
5957 const X86Subtarget *Subtarget, DebugLoc dl) {
5958 if (VT == MVT::v2f64 || VT == MVT::v4f32) {
5959 LoadSDNode *LD = NULL;
5960 if (!isScalarLoadToVector(SrcOp.getNode(), &LD))
5961 LD = dyn_cast<LoadSDNode>(SrcOp);
5963 // movssrr and movsdrr do not clear top bits. Try to use movd, movq
5965 MVT ExtVT = (OpVT == MVT::v2f64) ? MVT::i64 : MVT::i32;
5966 if ((ExtVT != MVT::i64 || Subtarget->is64Bit()) &&
5967 SrcOp.getOpcode() == ISD::SCALAR_TO_VECTOR &&
5968 SrcOp.getOperand(0).getOpcode() == ISD::BITCAST &&
5969 SrcOp.getOperand(0).getOperand(0).getValueType() == ExtVT) {
5971 OpVT = (OpVT == MVT::v2f64) ? MVT::v2i64 : MVT::v4i32;
5972 return DAG.getNode(ISD::BITCAST, dl, VT,
5973 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT,
5974 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
5982 return DAG.getNode(ISD::BITCAST, dl, VT,
5983 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT,
5984 DAG.getNode(ISD::BITCAST, dl,
5988 /// LowerVECTOR_SHUFFLE_256 - Handle all 256-bit wide vectors shuffles
5989 /// which could not be matched by any known target speficic shuffle
5991 LowerVECTOR_SHUFFLE_256(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
5993 SDValue NewOp = Compact8x32ShuffleNode(SVOp, DAG);
5994 if (NewOp.getNode())
5997 EVT VT = SVOp->getValueType(0);
5999 unsigned NumElems = VT.getVectorNumElements();
6000 unsigned NumLaneElems = NumElems / 2;
6002 DebugLoc dl = SVOp->getDebugLoc();
6003 MVT EltVT = VT.getVectorElementType().getSimpleVT();
6004 EVT NVT = MVT::getVectorVT(EltVT, NumLaneElems);
6007 SmallVector<int, 16> Mask;
6008 for (unsigned l = 0; l < 2; ++l) {
6009 // Build a shuffle mask for the output, discovering on the fly which
6010 // input vectors to use as shuffle operands (recorded in InputUsed).
6011 // If building a suitable shuffle vector proves too hard, then bail
6012 // out with UseBuildVector set.
6013 bool UseBuildVector = false;
6014 int InputUsed[2] = { -1, -1 }; // Not yet discovered.
6015 unsigned LaneStart = l * NumLaneElems;
6016 for (unsigned i = 0; i != NumLaneElems; ++i) {
6017 // The mask element. This indexes into the input.
6018 int Idx = SVOp->getMaskElt(i+LaneStart);
6020 // the mask element does not index into any input vector.
6025 // The input vector this mask element indexes into.
6026 int Input = Idx / NumLaneElems;
6028 // Turn the index into an offset from the start of the input vector.
6029 Idx -= Input * NumLaneElems;
6031 // Find or create a shuffle vector operand to hold this input.
6033 for (OpNo = 0; OpNo < array_lengthof(InputUsed); ++OpNo) {
6034 if (InputUsed[OpNo] == Input)
6035 // This input vector is already an operand.
6037 if (InputUsed[OpNo] < 0) {
6038 // Create a new operand for this input vector.
6039 InputUsed[OpNo] = Input;
6044 if (OpNo >= array_lengthof(InputUsed)) {
6045 // More than two input vectors used! Give up on trying to create a
6046 // shuffle vector. Insert all elements into a BUILD_VECTOR instead.
6047 UseBuildVector = true;
6051 // Add the mask index for the new shuffle vector.
6052 Mask.push_back(Idx + OpNo * NumLaneElems);
6055 if (UseBuildVector) {
6056 SmallVector<SDValue, 16> SVOps;
6057 for (unsigned i = 0; i != NumLaneElems; ++i) {
6058 // The mask element. This indexes into the input.
6059 int Idx = SVOp->getMaskElt(i+LaneStart);
6061 SVOps.push_back(DAG.getUNDEF(EltVT));
6065 // The input vector this mask element indexes into.
6066 int Input = Idx / NumElems;
6068 // Turn the index into an offset from the start of the input vector.
6069 Idx -= Input * NumElems;
6071 // Extract the vector element by hand.
6072 SVOps.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT,
6073 SVOp->getOperand(Input),
6074 DAG.getIntPtrConstant(Idx)));
6077 // Construct the output using a BUILD_VECTOR.
6078 Output[l] = DAG.getNode(ISD::BUILD_VECTOR, dl, NVT, &SVOps[0],
6080 } else if (InputUsed[0] < 0) {
6081 // No input vectors were used! The result is undefined.
6082 Output[l] = DAG.getUNDEF(NVT);
6084 SDValue Op0 = Extract128BitVector(SVOp->getOperand(InputUsed[0] / 2),
6085 (InputUsed[0] % 2) * NumLaneElems,
6087 // If only one input was used, use an undefined vector for the other.
6088 SDValue Op1 = (InputUsed[1] < 0) ? DAG.getUNDEF(NVT) :
6089 Extract128BitVector(SVOp->getOperand(InputUsed[1] / 2),
6090 (InputUsed[1] % 2) * NumLaneElems, DAG, dl);
6091 // At least one input vector was used. Create a new shuffle vector.
6092 Output[l] = DAG.getVectorShuffle(NVT, dl, Op0, Op1, &Mask[0]);
6098 // Concatenate the result back
6099 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, Output[0], Output[1]);
6102 /// LowerVECTOR_SHUFFLE_128v4 - Handle all 128-bit wide vectors with
6103 /// 4 elements, and match them with several different shuffle types.
6105 LowerVECTOR_SHUFFLE_128v4(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
6106 SDValue V1 = SVOp->getOperand(0);
6107 SDValue V2 = SVOp->getOperand(1);
6108 DebugLoc dl = SVOp->getDebugLoc();
6109 EVT VT = SVOp->getValueType(0);
6111 assert(VT.is128BitVector() && "Unsupported vector size");
6113 std::pair<int, int> Locs[4];
6114 int Mask1[] = { -1, -1, -1, -1 };
6115 SmallVector<int, 8> PermMask(SVOp->getMask().begin(), SVOp->getMask().end());
6119 for (unsigned i = 0; i != 4; ++i) {
6120 int Idx = PermMask[i];
6122 Locs[i] = std::make_pair(-1, -1);
6124 assert(Idx < 8 && "Invalid VECTOR_SHUFFLE index!");
6126 Locs[i] = std::make_pair(0, NumLo);
6130 Locs[i] = std::make_pair(1, NumHi);
6132 Mask1[2+NumHi] = Idx;
6138 if (NumLo <= 2 && NumHi <= 2) {
6139 // If no more than two elements come from either vector. This can be
6140 // implemented with two shuffles. First shuffle gather the elements.
6141 // The second shuffle, which takes the first shuffle as both of its
6142 // vector operands, put the elements into the right order.
6143 V1 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
6145 int Mask2[] = { -1, -1, -1, -1 };
6147 for (unsigned i = 0; i != 4; ++i)
6148 if (Locs[i].first != -1) {
6149 unsigned Idx = (i < 2) ? 0 : 4;
6150 Idx += Locs[i].first * 2 + Locs[i].second;
6154 return DAG.getVectorShuffle(VT, dl, V1, V1, &Mask2[0]);
6157 if (NumLo == 3 || NumHi == 3) {
6158 // Otherwise, we must have three elements from one vector, call it X, and
6159 // one element from the other, call it Y. First, use a shufps to build an
6160 // intermediate vector with the one element from Y and the element from X
6161 // that will be in the same half in the final destination (the indexes don't
6162 // matter). Then, use a shufps to build the final vector, taking the half
6163 // containing the element from Y from the intermediate, and the other half
6166 // Normalize it so the 3 elements come from V1.
6167 CommuteVectorShuffleMask(PermMask, 4);
6171 // Find the element from V2.
6173 for (HiIndex = 0; HiIndex < 3; ++HiIndex) {
6174 int Val = PermMask[HiIndex];
6181 Mask1[0] = PermMask[HiIndex];
6183 Mask1[2] = PermMask[HiIndex^1];
6185 V2 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
6188 Mask1[0] = PermMask[0];
6189 Mask1[1] = PermMask[1];
6190 Mask1[2] = HiIndex & 1 ? 6 : 4;
6191 Mask1[3] = HiIndex & 1 ? 4 : 6;
6192 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
6195 Mask1[0] = HiIndex & 1 ? 2 : 0;
6196 Mask1[1] = HiIndex & 1 ? 0 : 2;
6197 Mask1[2] = PermMask[2];
6198 Mask1[3] = PermMask[3];
6203 return DAG.getVectorShuffle(VT, dl, V2, V1, &Mask1[0]);
6206 // Break it into (shuffle shuffle_hi, shuffle_lo).
6207 int LoMask[] = { -1, -1, -1, -1 };
6208 int HiMask[] = { -1, -1, -1, -1 };
6210 int *MaskPtr = LoMask;
6211 unsigned MaskIdx = 0;
6214 for (unsigned i = 0; i != 4; ++i) {
6221 int Idx = PermMask[i];
6223 Locs[i] = std::make_pair(-1, -1);
6224 } else if (Idx < 4) {
6225 Locs[i] = std::make_pair(MaskIdx, LoIdx);
6226 MaskPtr[LoIdx] = Idx;
6229 Locs[i] = std::make_pair(MaskIdx, HiIdx);
6230 MaskPtr[HiIdx] = Idx;
6235 SDValue LoShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &LoMask[0]);
6236 SDValue HiShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &HiMask[0]);
6237 int MaskOps[] = { -1, -1, -1, -1 };
6238 for (unsigned i = 0; i != 4; ++i)
6239 if (Locs[i].first != -1)
6240 MaskOps[i] = Locs[i].first * 4 + Locs[i].second;
6241 return DAG.getVectorShuffle(VT, dl, LoShuffle, HiShuffle, &MaskOps[0]);
6244 static bool MayFoldVectorLoad(SDValue V) {
6245 if (V.hasOneUse() && V.getOpcode() == ISD::BITCAST)
6246 V = V.getOperand(0);
6247 if (V.hasOneUse() && V.getOpcode() == ISD::SCALAR_TO_VECTOR)
6248 V = V.getOperand(0);
6249 if (V.hasOneUse() && V.getOpcode() == ISD::BUILD_VECTOR &&
6250 V.getNumOperands() == 2 && V.getOperand(1).getOpcode() == ISD::UNDEF)
6251 // BUILD_VECTOR (load), undef
6252 V = V.getOperand(0);
6258 // FIXME: the version above should always be used. Since there's
6259 // a bug where several vector shuffles can't be folded because the
6260 // DAG is not updated during lowering and a node claims to have two
6261 // uses while it only has one, use this version, and let isel match
6262 // another instruction if the load really happens to have more than
6263 // one use. Remove this version after this bug get fixed.
6264 // rdar://8434668, PR8156
6265 static bool RelaxedMayFoldVectorLoad(SDValue V) {
6266 if (V.hasOneUse() && V.getOpcode() == ISD::BITCAST)
6267 V = V.getOperand(0);
6268 if (V.hasOneUse() && V.getOpcode() == ISD::SCALAR_TO_VECTOR)
6269 V = V.getOperand(0);
6270 if (ISD::isNormalLoad(V.getNode()))
6276 SDValue getMOVDDup(SDValue &Op, DebugLoc &dl, SDValue V1, SelectionDAG &DAG) {
6277 EVT VT = Op.getValueType();
6279 // Canonizalize to v2f64.
6280 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, V1);
6281 return DAG.getNode(ISD::BITCAST, dl, VT,
6282 getTargetShuffleNode(X86ISD::MOVDDUP, dl, MVT::v2f64,
6287 SDValue getMOVLowToHigh(SDValue &Op, DebugLoc &dl, SelectionDAG &DAG,
6289 SDValue V1 = Op.getOperand(0);
6290 SDValue V2 = Op.getOperand(1);
6291 EVT VT = Op.getValueType();
6293 assert(VT != MVT::v2i64 && "unsupported shuffle type");
6295 if (HasSSE2 && VT == MVT::v2f64)
6296 return getTargetShuffleNode(X86ISD::MOVLHPD, dl, VT, V1, V2, DAG);
6298 // v4f32 or v4i32: canonizalized to v4f32 (which is legal for SSE1)
6299 return DAG.getNode(ISD::BITCAST, dl, VT,
6300 getTargetShuffleNode(X86ISD::MOVLHPS, dl, MVT::v4f32,
6301 DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V1),
6302 DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V2), DAG));
6306 SDValue getMOVHighToLow(SDValue &Op, DebugLoc &dl, SelectionDAG &DAG) {
6307 SDValue V1 = Op.getOperand(0);
6308 SDValue V2 = Op.getOperand(1);
6309 EVT VT = Op.getValueType();
6311 assert((VT == MVT::v4i32 || VT == MVT::v4f32) &&
6312 "unsupported shuffle type");
6314 if (V2.getOpcode() == ISD::UNDEF)
6318 return getTargetShuffleNode(X86ISD::MOVHLPS, dl, VT, V1, V2, DAG);
6322 SDValue getMOVLP(SDValue &Op, DebugLoc &dl, SelectionDAG &DAG, bool HasSSE2) {
6323 SDValue V1 = Op.getOperand(0);
6324 SDValue V2 = Op.getOperand(1);
6325 EVT VT = Op.getValueType();
6326 unsigned NumElems = VT.getVectorNumElements();
6328 // Use MOVLPS and MOVLPD in case V1 or V2 are loads. During isel, the second
6329 // operand of these instructions is only memory, so check if there's a
6330 // potencial load folding here, otherwise use SHUFPS or MOVSD to match the
6332 bool CanFoldLoad = false;
6334 // Trivial case, when V2 comes from a load.
6335 if (MayFoldVectorLoad(V2))
6338 // When V1 is a load, it can be folded later into a store in isel, example:
6339 // (store (v4f32 (X86Movlps (load addr:$src1), VR128:$src2)), addr:$src1)
6341 // (MOVLPSmr addr:$src1, VR128:$src2)
6342 // So, recognize this potential and also use MOVLPS or MOVLPD
6343 else if (MayFoldVectorLoad(V1) && MayFoldIntoStore(Op))
6346 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
6348 if (HasSSE2 && NumElems == 2)
6349 return getTargetShuffleNode(X86ISD::MOVLPD, dl, VT, V1, V2, DAG);
6352 // If we don't care about the second element, proceed to use movss.
6353 if (SVOp->getMaskElt(1) != -1)
6354 return getTargetShuffleNode(X86ISD::MOVLPS, dl, VT, V1, V2, DAG);
6357 // movl and movlp will both match v2i64, but v2i64 is never matched by
6358 // movl earlier because we make it strict to avoid messing with the movlp load
6359 // folding logic (see the code above getMOVLP call). Match it here then,
6360 // this is horrible, but will stay like this until we move all shuffle
6361 // matching to x86 specific nodes. Note that for the 1st condition all
6362 // types are matched with movsd.
6364 // FIXME: isMOVLMask should be checked and matched before getMOVLP,
6365 // as to remove this logic from here, as much as possible
6366 if (NumElems == 2 || !isMOVLMask(SVOp->getMask(), VT))
6367 return getTargetShuffleNode(X86ISD::MOVSD, dl, VT, V1, V2, DAG);
6368 return getTargetShuffleNode(X86ISD::MOVSS, dl, VT, V1, V2, DAG);
6371 assert(VT != MVT::v4i32 && "unsupported shuffle type");
6373 // Invert the operand order and use SHUFPS to match it.
6374 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V2, V1,
6375 getShuffleSHUFImmediate(SVOp), DAG);
6379 X86TargetLowering::NormalizeVectorShuffle(SDValue Op, SelectionDAG &DAG) const {
6380 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
6381 EVT VT = Op.getValueType();
6382 DebugLoc dl = Op.getDebugLoc();
6383 SDValue V1 = Op.getOperand(0);
6384 SDValue V2 = Op.getOperand(1);
6386 if (isZeroShuffle(SVOp))
6387 return getZeroVector(VT, Subtarget, DAG, dl);
6389 // Handle splat operations
6390 if (SVOp->isSplat()) {
6391 unsigned NumElem = VT.getVectorNumElements();
6392 int Size = VT.getSizeInBits();
6394 // Use vbroadcast whenever the splat comes from a foldable load
6395 SDValue Broadcast = LowerVectorBroadcast(Op, DAG);
6396 if (Broadcast.getNode())
6399 // Handle splats by matching through known shuffle masks
6400 if ((Size == 128 && NumElem <= 4) ||
6401 (Size == 256 && NumElem < 8))
6404 // All remaning splats are promoted to target supported vector shuffles.
6405 return PromoteSplat(SVOp, DAG);
6408 // If the shuffle can be profitably rewritten as a narrower shuffle, then
6410 if (VT == MVT::v8i16 || VT == MVT::v16i8 ||
6411 VT == MVT::v16i16 || VT == MVT::v32i8) {
6412 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG, dl);
6413 if (NewOp.getNode())
6414 return DAG.getNode(ISD::BITCAST, dl, VT, NewOp);
6415 } else if ((VT == MVT::v4i32 ||
6416 (VT == MVT::v4f32 && Subtarget->hasSSE2()))) {
6417 // FIXME: Figure out a cleaner way to do this.
6418 // Try to make use of movq to zero out the top part.
6419 if (ISD::isBuildVectorAllZeros(V2.getNode())) {
6420 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG, dl);
6421 if (NewOp.getNode()) {
6422 EVT NewVT = NewOp.getValueType();
6423 if (isCommutedMOVLMask(cast<ShuffleVectorSDNode>(NewOp)->getMask(),
6424 NewVT, true, false))
6425 return getVZextMovL(VT, NewVT, NewOp.getOperand(0),
6426 DAG, Subtarget, dl);
6428 } else if (ISD::isBuildVectorAllZeros(V1.getNode())) {
6429 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG, dl);
6430 if (NewOp.getNode()) {
6431 EVT NewVT = NewOp.getValueType();
6432 if (isMOVLMask(cast<ShuffleVectorSDNode>(NewOp)->getMask(), NewVT))
6433 return getVZextMovL(VT, NewVT, NewOp.getOperand(1),
6434 DAG, Subtarget, dl);
6442 X86TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const {
6443 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
6444 SDValue V1 = Op.getOperand(0);
6445 SDValue V2 = Op.getOperand(1);
6446 EVT VT = Op.getValueType();
6447 DebugLoc dl = Op.getDebugLoc();
6448 unsigned NumElems = VT.getVectorNumElements();
6449 bool V1IsUndef = V1.getOpcode() == ISD::UNDEF;
6450 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
6451 bool V1IsSplat = false;
6452 bool V2IsSplat = false;
6453 bool HasSSE2 = Subtarget->hasSSE2();
6454 bool HasAVX = Subtarget->hasAVX();
6455 bool HasAVX2 = Subtarget->hasAVX2();
6456 MachineFunction &MF = DAG.getMachineFunction();
6457 bool OptForSize = MF.getFunction()->hasFnAttr(Attribute::OptimizeForSize);
6459 assert(VT.getSizeInBits() != 64 && "Can't lower MMX shuffles");
6461 if (V1IsUndef && V2IsUndef)
6462 return DAG.getUNDEF(VT);
6464 assert(!V1IsUndef && "Op 1 of shuffle should not be undef");
6466 // Vector shuffle lowering takes 3 steps:
6468 // 1) Normalize the input vectors. Here splats, zeroed vectors, profitable
6469 // narrowing and commutation of operands should be handled.
6470 // 2) Matching of shuffles with known shuffle masks to x86 target specific
6472 // 3) Rewriting of unmatched masks into new generic shuffle operations,
6473 // so the shuffle can be broken into other shuffles and the legalizer can
6474 // try the lowering again.
6476 // The general idea is that no vector_shuffle operation should be left to
6477 // be matched during isel, all of them must be converted to a target specific
6480 // Normalize the input vectors. Here splats, zeroed vectors, profitable
6481 // narrowing and commutation of operands should be handled. The actual code
6482 // doesn't include all of those, work in progress...
6483 SDValue NewOp = NormalizeVectorShuffle(Op, DAG);
6484 if (NewOp.getNode())
6487 SmallVector<int, 8> M(SVOp->getMask().begin(), SVOp->getMask().end());
6489 // NOTE: isPSHUFDMask can also match both masks below (unpckl_undef and
6490 // unpckh_undef). Only use pshufd if speed is more important than size.
6491 if (OptForSize && isUNPCKL_v_undef_Mask(M, VT, HasAVX2))
6492 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
6493 if (OptForSize && isUNPCKH_v_undef_Mask(M, VT, HasAVX2))
6494 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
6496 if (isMOVDDUPMask(M, VT) && Subtarget->hasSSE3() &&
6497 V2IsUndef && RelaxedMayFoldVectorLoad(V1))
6498 return getMOVDDup(Op, dl, V1, DAG);
6500 if (isMOVHLPS_v_undef_Mask(M, VT))
6501 return getMOVHighToLow(Op, dl, DAG);
6503 // Use to match splats
6504 if (HasSSE2 && isUNPCKHMask(M, VT, HasAVX2) && V2IsUndef &&
6505 (VT == MVT::v2f64 || VT == MVT::v2i64))
6506 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
6508 if (isPSHUFDMask(M, VT)) {
6509 // The actual implementation will match the mask in the if above and then
6510 // during isel it can match several different instructions, not only pshufd
6511 // as its name says, sad but true, emulate the behavior for now...
6512 if (isMOVDDUPMask(M, VT) && ((VT == MVT::v4f32 || VT == MVT::v2i64)))
6513 return getTargetShuffleNode(X86ISD::MOVLHPS, dl, VT, V1, V1, DAG);
6515 unsigned TargetMask = getShuffleSHUFImmediate(SVOp);
6517 if (HasAVX && (VT == MVT::v4f32 || VT == MVT::v2f64))
6518 return getTargetShuffleNode(X86ISD::VPERMILP, dl, VT, V1, TargetMask, DAG);
6520 if (HasSSE2 && (VT == MVT::v4f32 || VT == MVT::v4i32))
6521 return getTargetShuffleNode(X86ISD::PSHUFD, dl, VT, V1, TargetMask, DAG);
6523 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V1, V1,
6527 // Check if this can be converted into a logical shift.
6528 bool isLeft = false;
6531 bool isShift = HasSSE2 && isVectorShift(SVOp, DAG, isLeft, ShVal, ShAmt);
6532 if (isShift && ShVal.hasOneUse()) {
6533 // If the shifted value has multiple uses, it may be cheaper to use
6534 // v_set0 + movlhps or movhlps, etc.
6535 EVT EltVT = VT.getVectorElementType();
6536 ShAmt *= EltVT.getSizeInBits();
6537 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl);
6540 if (isMOVLMask(M, VT)) {
6541 if (ISD::isBuildVectorAllZeros(V1.getNode()))
6542 return getVZextMovL(VT, VT, V2, DAG, Subtarget, dl);
6543 if (!isMOVLPMask(M, VT)) {
6544 if (HasSSE2 && (VT == MVT::v2i64 || VT == MVT::v2f64))
6545 return getTargetShuffleNode(X86ISD::MOVSD, dl, VT, V1, V2, DAG);
6547 if (VT == MVT::v4i32 || VT == MVT::v4f32)
6548 return getTargetShuffleNode(X86ISD::MOVSS, dl, VT, V1, V2, DAG);
6552 // FIXME: fold these into legal mask.
6553 if (isMOVLHPSMask(M, VT) && !isUNPCKLMask(M, VT, HasAVX2))
6554 return getMOVLowToHigh(Op, dl, DAG, HasSSE2);
6556 if (isMOVHLPSMask(M, VT))
6557 return getMOVHighToLow(Op, dl, DAG);
6559 if (V2IsUndef && isMOVSHDUPMask(M, VT, Subtarget))
6560 return getTargetShuffleNode(X86ISD::MOVSHDUP, dl, VT, V1, DAG);
6562 if (V2IsUndef && isMOVSLDUPMask(M, VT, Subtarget))
6563 return getTargetShuffleNode(X86ISD::MOVSLDUP, dl, VT, V1, DAG);
6565 if (isMOVLPMask(M, VT))
6566 return getMOVLP(Op, dl, DAG, HasSSE2);
6568 if (ShouldXformToMOVHLPS(M, VT) ||
6569 ShouldXformToMOVLP(V1.getNode(), V2.getNode(), M, VT))
6570 return CommuteVectorShuffle(SVOp, DAG);
6573 // No better options. Use a vshldq / vsrldq.
6574 EVT EltVT = VT.getVectorElementType();
6575 ShAmt *= EltVT.getSizeInBits();
6576 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl);
6579 bool Commuted = false;
6580 // FIXME: This should also accept a bitcast of a splat? Be careful, not
6581 // 1,1,1,1 -> v8i16 though.
6582 V1IsSplat = isSplatVector(V1.getNode());
6583 V2IsSplat = isSplatVector(V2.getNode());
6585 // Canonicalize the splat or undef, if present, to be on the RHS.
6586 if (!V2IsUndef && V1IsSplat && !V2IsSplat) {
6587 CommuteVectorShuffleMask(M, NumElems);
6589 std::swap(V1IsSplat, V2IsSplat);
6593 if (isCommutedMOVLMask(M, VT, V2IsSplat, V2IsUndef)) {
6594 // Shuffling low element of v1 into undef, just return v1.
6597 // If V2 is a splat, the mask may be malformed such as <4,3,3,3>, which
6598 // the instruction selector will not match, so get a canonical MOVL with
6599 // swapped operands to undo the commute.
6600 return getMOVL(DAG, dl, VT, V2, V1);
6603 if (isUNPCKLMask(M, VT, HasAVX2))
6604 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG);
6606 if (isUNPCKHMask(M, VT, HasAVX2))
6607 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG);
6610 // Normalize mask so all entries that point to V2 points to its first
6611 // element then try to match unpck{h|l} again. If match, return a
6612 // new vector_shuffle with the corrected mask.p
6613 SmallVector<int, 8> NewMask(M.begin(), M.end());
6614 NormalizeMask(NewMask, NumElems);
6615 if (isUNPCKLMask(NewMask, VT, HasAVX2, true))
6616 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG);
6617 if (isUNPCKHMask(NewMask, VT, HasAVX2, true))
6618 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG);
6622 // Commute is back and try unpck* again.
6623 // FIXME: this seems wrong.
6624 CommuteVectorShuffleMask(M, NumElems);
6626 std::swap(V1IsSplat, V2IsSplat);
6629 if (isUNPCKLMask(M, VT, HasAVX2))
6630 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG);
6632 if (isUNPCKHMask(M, VT, HasAVX2))
6633 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG);
6636 // Normalize the node to match x86 shuffle ops if needed
6637 if (!V2IsUndef && (isSHUFPMask(M, VT, HasAVX, /* Commuted */ true)))
6638 return CommuteVectorShuffle(SVOp, DAG);
6640 // The checks below are all present in isShuffleMaskLegal, but they are
6641 // inlined here right now to enable us to directly emit target specific
6642 // nodes, and remove one by one until they don't return Op anymore.
6644 if (isPALIGNRMask(M, VT, Subtarget))
6645 return getTargetShuffleNode(X86ISD::PALIGN, dl, VT, V1, V2,
6646 getShufflePALIGNRImmediate(SVOp),
6649 if (ShuffleVectorSDNode::isSplatMask(&M[0], VT) &&
6650 SVOp->getSplatIndex() == 0 && V2IsUndef) {
6651 if (VT == MVT::v2f64 || VT == MVT::v2i64)
6652 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
6655 if (isPSHUFHWMask(M, VT, HasAVX2))
6656 return getTargetShuffleNode(X86ISD::PSHUFHW, dl, VT, V1,
6657 getShufflePSHUFHWImmediate(SVOp),
6660 if (isPSHUFLWMask(M, VT, HasAVX2))
6661 return getTargetShuffleNode(X86ISD::PSHUFLW, dl, VT, V1,
6662 getShufflePSHUFLWImmediate(SVOp),
6665 if (isSHUFPMask(M, VT, HasAVX))
6666 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V1, V2,
6667 getShuffleSHUFImmediate(SVOp), DAG);
6669 if (isUNPCKL_v_undef_Mask(M, VT, HasAVX2))
6670 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
6671 if (isUNPCKH_v_undef_Mask(M, VT, HasAVX2))
6672 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
6674 //===--------------------------------------------------------------------===//
6675 // Generate target specific nodes for 128 or 256-bit shuffles only
6676 // supported in the AVX instruction set.
6679 // Handle VMOVDDUPY permutations
6680 if (V2IsUndef && isMOVDDUPYMask(M, VT, HasAVX))
6681 return getTargetShuffleNode(X86ISD::MOVDDUP, dl, VT, V1, DAG);
6683 // Handle VPERMILPS/D* permutations
6684 if (isVPERMILPMask(M, VT, HasAVX)) {
6685 if (HasAVX2 && VT == MVT::v8i32)
6686 return getTargetShuffleNode(X86ISD::PSHUFD, dl, VT, V1,
6687 getShuffleSHUFImmediate(SVOp), DAG);
6688 return getTargetShuffleNode(X86ISD::VPERMILP, dl, VT, V1,
6689 getShuffleSHUFImmediate(SVOp), DAG);
6692 // Handle VPERM2F128/VPERM2I128 permutations
6693 if (isVPERM2X128Mask(M, VT, HasAVX))
6694 return getTargetShuffleNode(X86ISD::VPERM2X128, dl, VT, V1,
6695 V2, getShuffleVPERM2X128Immediate(SVOp), DAG);
6697 SDValue BlendOp = LowerVECTOR_SHUFFLEtoBlend(SVOp, Subtarget, DAG);
6698 if (BlendOp.getNode())
6701 if (V2IsUndef && HasAVX2 && (VT == MVT::v8i32 || VT == MVT::v8f32)) {
6702 SmallVector<SDValue, 8> permclMask;
6703 for (unsigned i = 0; i != 8; ++i) {
6704 permclMask.push_back(DAG.getConstant((M[i]>=0) ? M[i] : 0, MVT::i32));
6706 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32,
6708 // Bitcast is for VPERMPS since mask is v8i32 but node takes v8f32
6709 return DAG.getNode(X86ISD::VPERMV, dl, VT,
6710 DAG.getNode(ISD::BITCAST, dl, VT, Mask), V1);
6713 if (V2IsUndef && HasAVX2 && (VT == MVT::v4i64 || VT == MVT::v4f64))
6714 return getTargetShuffleNode(X86ISD::VPERMI, dl, VT, V1,
6715 getShuffleCLImmediate(SVOp), DAG);
6718 //===--------------------------------------------------------------------===//
6719 // Since no target specific shuffle was selected for this generic one,
6720 // lower it into other known shuffles. FIXME: this isn't true yet, but
6721 // this is the plan.
6724 // Handle v8i16 specifically since SSE can do byte extraction and insertion.
6725 if (VT == MVT::v8i16) {
6726 SDValue NewOp = LowerVECTOR_SHUFFLEv8i16(Op, DAG);
6727 if (NewOp.getNode())
6731 if (VT == MVT::v16i8) {
6732 SDValue NewOp = LowerVECTOR_SHUFFLEv16i8(SVOp, DAG, *this);
6733 if (NewOp.getNode())
6737 // Handle all 128-bit wide vectors with 4 elements, and match them with
6738 // several different shuffle types.
6739 if (NumElems == 4 && VT.is128BitVector())
6740 return LowerVECTOR_SHUFFLE_128v4(SVOp, DAG);
6742 // Handle general 256-bit shuffles
6743 if (VT.is256BitVector())
6744 return LowerVECTOR_SHUFFLE_256(SVOp, DAG);
6750 X86TargetLowering::LowerEXTRACT_VECTOR_ELT_SSE4(SDValue Op,
6751 SelectionDAG &DAG) const {
6752 EVT VT = Op.getValueType();
6753 DebugLoc dl = Op.getDebugLoc();
6755 if (!Op.getOperand(0).getValueType().is128BitVector())
6758 if (VT.getSizeInBits() == 8) {
6759 SDValue Extract = DAG.getNode(X86ISD::PEXTRB, dl, MVT::i32,
6760 Op.getOperand(0), Op.getOperand(1));
6761 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
6762 DAG.getValueType(VT));
6763 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
6766 if (VT.getSizeInBits() == 16) {
6767 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
6768 // If Idx is 0, it's cheaper to do a move instead of a pextrw.
6770 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
6771 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
6772 DAG.getNode(ISD::BITCAST, dl,
6776 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, MVT::i32,
6777 Op.getOperand(0), Op.getOperand(1));
6778 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
6779 DAG.getValueType(VT));
6780 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
6783 if (VT == MVT::f32) {
6784 // EXTRACTPS outputs to a GPR32 register which will require a movd to copy
6785 // the result back to FR32 register. It's only worth matching if the
6786 // result has a single use which is a store or a bitcast to i32. And in
6787 // the case of a store, it's not worth it if the index is a constant 0,
6788 // because a MOVSSmr can be used instead, which is smaller and faster.
6789 if (!Op.hasOneUse())
6791 SDNode *User = *Op.getNode()->use_begin();
6792 if ((User->getOpcode() != ISD::STORE ||
6793 (isa<ConstantSDNode>(Op.getOperand(1)) &&
6794 cast<ConstantSDNode>(Op.getOperand(1))->isNullValue())) &&
6795 (User->getOpcode() != ISD::BITCAST ||
6796 User->getValueType(0) != MVT::i32))
6798 SDValue Extract = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
6799 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32,
6802 return DAG.getNode(ISD::BITCAST, dl, MVT::f32, Extract);
6805 if (VT == MVT::i32 || VT == MVT::i64) {
6806 // ExtractPS/pextrq works with constant index.
6807 if (isa<ConstantSDNode>(Op.getOperand(1)))
6815 X86TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op,
6816 SelectionDAG &DAG) const {
6817 if (!isa<ConstantSDNode>(Op.getOperand(1)))
6820 SDValue Vec = Op.getOperand(0);
6821 EVT VecVT = Vec.getValueType();
6823 // If this is a 256-bit vector result, first extract the 128-bit vector and
6824 // then extract the element from the 128-bit vector.
6825 if (VecVT.is256BitVector()) {
6826 DebugLoc dl = Op.getNode()->getDebugLoc();
6827 unsigned NumElems = VecVT.getVectorNumElements();
6828 SDValue Idx = Op.getOperand(1);
6829 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
6831 // Get the 128-bit vector.
6832 Vec = Extract128BitVector(Vec, IdxVal, DAG, dl);
6834 if (IdxVal >= NumElems/2)
6835 IdxVal -= NumElems/2;
6836 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, Op.getValueType(), Vec,
6837 DAG.getConstant(IdxVal, MVT::i32));
6840 assert(VecVT.is128BitVector() && "Unexpected vector length");
6842 if (Subtarget->hasSSE41()) {
6843 SDValue Res = LowerEXTRACT_VECTOR_ELT_SSE4(Op, DAG);
6848 EVT VT = Op.getValueType();
6849 DebugLoc dl = Op.getDebugLoc();
6850 // TODO: handle v16i8.
6851 if (VT.getSizeInBits() == 16) {
6852 SDValue Vec = Op.getOperand(0);
6853 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
6855 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
6856 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
6857 DAG.getNode(ISD::BITCAST, dl,
6860 // Transform it so it match pextrw which produces a 32-bit result.
6861 EVT EltVT = MVT::i32;
6862 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, EltVT,
6863 Op.getOperand(0), Op.getOperand(1));
6864 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, EltVT, Extract,
6865 DAG.getValueType(VT));
6866 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
6869 if (VT.getSizeInBits() == 32) {
6870 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
6874 // SHUFPS the element to the lowest double word, then movss.
6875 int Mask[4] = { static_cast<int>(Idx), -1, -1, -1 };
6876 EVT VVT = Op.getOperand(0).getValueType();
6877 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
6878 DAG.getUNDEF(VVT), Mask);
6879 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
6880 DAG.getIntPtrConstant(0));
6883 if (VT.getSizeInBits() == 64) {
6884 // FIXME: .td only matches this for <2 x f64>, not <2 x i64> on 32b
6885 // FIXME: seems like this should be unnecessary if mov{h,l}pd were taught
6886 // to match extract_elt for f64.
6887 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
6891 // UNPCKHPD the element to the lowest double word, then movsd.
6892 // Note if the lower 64 bits of the result of the UNPCKHPD is then stored
6893 // to a f64mem, the whole operation is folded into a single MOVHPDmr.
6894 int Mask[2] = { 1, -1 };
6895 EVT VVT = Op.getOperand(0).getValueType();
6896 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
6897 DAG.getUNDEF(VVT), Mask);
6898 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
6899 DAG.getIntPtrConstant(0));
6906 X86TargetLowering::LowerINSERT_VECTOR_ELT_SSE4(SDValue Op,
6907 SelectionDAG &DAG) const {
6908 EVT VT = Op.getValueType();
6909 EVT EltVT = VT.getVectorElementType();
6910 DebugLoc dl = Op.getDebugLoc();
6912 SDValue N0 = Op.getOperand(0);
6913 SDValue N1 = Op.getOperand(1);
6914 SDValue N2 = Op.getOperand(2);
6916 if (!VT.is128BitVector())
6919 if ((EltVT.getSizeInBits() == 8 || EltVT.getSizeInBits() == 16) &&
6920 isa<ConstantSDNode>(N2)) {
6922 if (VT == MVT::v8i16)
6923 Opc = X86ISD::PINSRW;
6924 else if (VT == MVT::v16i8)
6925 Opc = X86ISD::PINSRB;
6927 Opc = X86ISD::PINSRB;
6929 // Transform it so it match pinsr{b,w} which expects a GR32 as its second
6931 if (N1.getValueType() != MVT::i32)
6932 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
6933 if (N2.getValueType() != MVT::i32)
6934 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue());
6935 return DAG.getNode(Opc, dl, VT, N0, N1, N2);
6938 if (EltVT == MVT::f32 && isa<ConstantSDNode>(N2)) {
6939 // Bits [7:6] of the constant are the source select. This will always be
6940 // zero here. The DAG Combiner may combine an extract_elt index into these
6941 // bits. For example (insert (extract, 3), 2) could be matched by putting
6942 // the '3' into bits [7:6] of X86ISD::INSERTPS.
6943 // Bits [5:4] of the constant are the destination select. This is the
6944 // value of the incoming immediate.
6945 // Bits [3:0] of the constant are the zero mask. The DAG Combiner may
6946 // combine either bitwise AND or insert of float 0.0 to set these bits.
6947 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue() << 4);
6948 // Create this as a scalar to vector..
6949 N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4f32, N1);
6950 return DAG.getNode(X86ISD::INSERTPS, dl, VT, N0, N1, N2);
6953 if ((EltVT == MVT::i32 || EltVT == MVT::i64) && isa<ConstantSDNode>(N2)) {
6954 // PINSR* works with constant index.
6961 X86TargetLowering::LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const {
6962 EVT VT = Op.getValueType();
6963 EVT EltVT = VT.getVectorElementType();
6965 DebugLoc dl = Op.getDebugLoc();
6966 SDValue N0 = Op.getOperand(0);
6967 SDValue N1 = Op.getOperand(1);
6968 SDValue N2 = Op.getOperand(2);
6970 // If this is a 256-bit vector result, first extract the 128-bit vector,
6971 // insert the element into the extracted half and then place it back.
6972 if (VT.is256BitVector()) {
6973 if (!isa<ConstantSDNode>(N2))
6976 // Get the desired 128-bit vector half.
6977 unsigned NumElems = VT.getVectorNumElements();
6978 unsigned IdxVal = cast<ConstantSDNode>(N2)->getZExtValue();
6979 SDValue V = Extract128BitVector(N0, IdxVal, DAG, dl);
6981 // Insert the element into the desired half.
6982 bool Upper = IdxVal >= NumElems/2;
6983 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, V.getValueType(), V, N1,
6984 DAG.getConstant(Upper ? IdxVal-NumElems/2 : IdxVal, MVT::i32));
6986 // Insert the changed part back to the 256-bit vector
6987 return Insert128BitVector(N0, V, IdxVal, DAG, dl);
6990 if (Subtarget->hasSSE41())
6991 return LowerINSERT_VECTOR_ELT_SSE4(Op, DAG);
6993 if (EltVT == MVT::i8)
6996 if (EltVT.getSizeInBits() == 16 && isa<ConstantSDNode>(N2)) {
6997 // Transform it so it match pinsrw which expects a 16-bit value in a GR32
6998 // as its second argument.
6999 if (N1.getValueType() != MVT::i32)
7000 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
7001 if (N2.getValueType() != MVT::i32)
7002 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue());
7003 return DAG.getNode(X86ISD::PINSRW, dl, VT, N0, N1, N2);
7009 X86TargetLowering::LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) const {
7010 LLVMContext *Context = DAG.getContext();
7011 DebugLoc dl = Op.getDebugLoc();
7012 EVT OpVT = Op.getValueType();
7014 // If this is a 256-bit vector result, first insert into a 128-bit
7015 // vector and then insert into the 256-bit vector.
7016 if (!OpVT.is128BitVector()) {
7017 // Insert into a 128-bit vector.
7018 EVT VT128 = EVT::getVectorVT(*Context,
7019 OpVT.getVectorElementType(),
7020 OpVT.getVectorNumElements() / 2);
7022 Op = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT128, Op.getOperand(0));
7024 // Insert the 128-bit vector.
7025 return Insert128BitVector(DAG.getUNDEF(OpVT), Op, 0, DAG, dl);
7028 if (OpVT == MVT::v1i64 &&
7029 Op.getOperand(0).getValueType() == MVT::i64)
7030 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v1i64, Op.getOperand(0));
7032 SDValue AnyExt = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, Op.getOperand(0));
7033 assert(OpVT.is128BitVector() && "Expected an SSE type!");
7034 return DAG.getNode(ISD::BITCAST, dl, OpVT,
7035 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,AnyExt));
7038 // Lower a node with an EXTRACT_SUBVECTOR opcode. This may result in
7039 // a simple subregister reference or explicit instructions to grab
7040 // upper bits of a vector.
7042 X86TargetLowering::LowerEXTRACT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const {
7043 if (Subtarget->hasAVX()) {
7044 DebugLoc dl = Op.getNode()->getDebugLoc();
7045 SDValue Vec = Op.getNode()->getOperand(0);
7046 SDValue Idx = Op.getNode()->getOperand(1);
7048 if (Op.getNode()->getValueType(0).is128BitVector() &&
7049 Vec.getNode()->getValueType(0).is256BitVector() &&
7050 isa<ConstantSDNode>(Idx)) {
7051 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
7052 return Extract128BitVector(Vec, IdxVal, DAG, dl);
7058 // Lower a node with an INSERT_SUBVECTOR opcode. This may result in a
7059 // simple superregister reference or explicit instructions to insert
7060 // the upper bits of a vector.
7062 X86TargetLowering::LowerINSERT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const {
7063 if (Subtarget->hasAVX()) {
7064 DebugLoc dl = Op.getNode()->getDebugLoc();
7065 SDValue Vec = Op.getNode()->getOperand(0);
7066 SDValue SubVec = Op.getNode()->getOperand(1);
7067 SDValue Idx = Op.getNode()->getOperand(2);
7069 if (Op.getNode()->getValueType(0).is256BitVector() &&
7070 SubVec.getNode()->getValueType(0).is128BitVector() &&
7071 isa<ConstantSDNode>(Idx)) {
7072 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
7073 return Insert128BitVector(Vec, SubVec, IdxVal, DAG, dl);
7079 // ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as
7080 // their target countpart wrapped in the X86ISD::Wrapper node. Suppose N is
7081 // one of the above mentioned nodes. It has to be wrapped because otherwise
7082 // Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only
7083 // be used to form addressing mode. These wrapped nodes will be selected
7086 X86TargetLowering::LowerConstantPool(SDValue Op, SelectionDAG &DAG) const {
7087 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
7089 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
7091 unsigned char OpFlag = 0;
7092 unsigned WrapperKind = X86ISD::Wrapper;
7093 CodeModel::Model M = getTargetMachine().getCodeModel();
7095 if (Subtarget->isPICStyleRIPRel() &&
7096 (M == CodeModel::Small || M == CodeModel::Kernel))
7097 WrapperKind = X86ISD::WrapperRIP;
7098 else if (Subtarget->isPICStyleGOT())
7099 OpFlag = X86II::MO_GOTOFF;
7100 else if (Subtarget->isPICStyleStubPIC())
7101 OpFlag = X86II::MO_PIC_BASE_OFFSET;
7103 SDValue Result = DAG.getTargetConstantPool(CP->getConstVal(), getPointerTy(),
7105 CP->getOffset(), OpFlag);
7106 DebugLoc DL = CP->getDebugLoc();
7107 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
7108 // With PIC, the address is actually $g + Offset.
7110 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
7111 DAG.getNode(X86ISD::GlobalBaseReg,
7112 DebugLoc(), getPointerTy()),
7119 SDValue X86TargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) const {
7120 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
7122 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
7124 unsigned char OpFlag = 0;
7125 unsigned WrapperKind = X86ISD::Wrapper;
7126 CodeModel::Model M = getTargetMachine().getCodeModel();
7128 if (Subtarget->isPICStyleRIPRel() &&
7129 (M == CodeModel::Small || M == CodeModel::Kernel))
7130 WrapperKind = X86ISD::WrapperRIP;
7131 else if (Subtarget->isPICStyleGOT())
7132 OpFlag = X86II::MO_GOTOFF;
7133 else if (Subtarget->isPICStyleStubPIC())
7134 OpFlag = X86II::MO_PIC_BASE_OFFSET;
7136 SDValue Result = DAG.getTargetJumpTable(JT->getIndex(), getPointerTy(),
7138 DebugLoc DL = JT->getDebugLoc();
7139 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
7141 // With PIC, the address is actually $g + Offset.
7143 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
7144 DAG.getNode(X86ISD::GlobalBaseReg,
7145 DebugLoc(), getPointerTy()),
7152 X86TargetLowering::LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) const {
7153 const char *Sym = cast<ExternalSymbolSDNode>(Op)->getSymbol();
7155 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
7157 unsigned char OpFlag = 0;
7158 unsigned WrapperKind = X86ISD::Wrapper;
7159 CodeModel::Model M = getTargetMachine().getCodeModel();
7161 if (Subtarget->isPICStyleRIPRel() &&
7162 (M == CodeModel::Small || M == CodeModel::Kernel)) {
7163 if (Subtarget->isTargetDarwin() || Subtarget->isTargetELF())
7164 OpFlag = X86II::MO_GOTPCREL;
7165 WrapperKind = X86ISD::WrapperRIP;
7166 } else if (Subtarget->isPICStyleGOT()) {
7167 OpFlag = X86II::MO_GOT;
7168 } else if (Subtarget->isPICStyleStubPIC()) {
7169 OpFlag = X86II::MO_DARWIN_NONLAZY_PIC_BASE;
7170 } else if (Subtarget->isPICStyleStubNoDynamic()) {
7171 OpFlag = X86II::MO_DARWIN_NONLAZY;
7174 SDValue Result = DAG.getTargetExternalSymbol(Sym, getPointerTy(), OpFlag);
7176 DebugLoc DL = Op.getDebugLoc();
7177 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
7180 // With PIC, the address is actually $g + Offset.
7181 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
7182 !Subtarget->is64Bit()) {
7183 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
7184 DAG.getNode(X86ISD::GlobalBaseReg,
7185 DebugLoc(), getPointerTy()),
7189 // For symbols that require a load from a stub to get the address, emit the
7191 if (isGlobalStubReference(OpFlag))
7192 Result = DAG.getLoad(getPointerTy(), DL, DAG.getEntryNode(), Result,
7193 MachinePointerInfo::getGOT(), false, false, false, 0);
7199 X86TargetLowering::LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const {
7200 // Create the TargetBlockAddressAddress node.
7201 unsigned char OpFlags =
7202 Subtarget->ClassifyBlockAddressReference();
7203 CodeModel::Model M = getTargetMachine().getCodeModel();
7204 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
7205 DebugLoc dl = Op.getDebugLoc();
7206 SDValue Result = DAG.getBlockAddress(BA, getPointerTy(),
7207 /*isTarget=*/true, OpFlags);
7209 if (Subtarget->isPICStyleRIPRel() &&
7210 (M == CodeModel::Small || M == CodeModel::Kernel))
7211 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
7213 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
7215 // With PIC, the address is actually $g + Offset.
7216 if (isGlobalRelativeToPICBase(OpFlags)) {
7217 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
7218 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
7226 X86TargetLowering::LowerGlobalAddress(const GlobalValue *GV, DebugLoc dl,
7228 SelectionDAG &DAG) const {
7229 // Create the TargetGlobalAddress node, folding in the constant
7230 // offset if it is legal.
7231 unsigned char OpFlags =
7232 Subtarget->ClassifyGlobalReference(GV, getTargetMachine());
7233 CodeModel::Model M = getTargetMachine().getCodeModel();
7235 if (OpFlags == X86II::MO_NO_FLAG &&
7236 X86::isOffsetSuitableForCodeModel(Offset, M)) {
7237 // A direct static reference to a global.
7238 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), Offset);
7241 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), 0, OpFlags);
7244 if (Subtarget->isPICStyleRIPRel() &&
7245 (M == CodeModel::Small || M == CodeModel::Kernel))
7246 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
7248 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
7250 // With PIC, the address is actually $g + Offset.
7251 if (isGlobalRelativeToPICBase(OpFlags)) {
7252 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
7253 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
7257 // For globals that require a load from a stub to get the address, emit the
7259 if (isGlobalStubReference(OpFlags))
7260 Result = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Result,
7261 MachinePointerInfo::getGOT(), false, false, false, 0);
7263 // If there was a non-zero offset that we didn't fold, create an explicit
7266 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(), Result,
7267 DAG.getConstant(Offset, getPointerTy()));
7273 X86TargetLowering::LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const {
7274 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
7275 int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset();
7276 return LowerGlobalAddress(GV, Op.getDebugLoc(), Offset, DAG);
7280 GetTLSADDR(SelectionDAG &DAG, SDValue Chain, GlobalAddressSDNode *GA,
7281 SDValue *InFlag, const EVT PtrVT, unsigned ReturnReg,
7282 unsigned char OperandFlags, bool LocalDynamic = false) {
7283 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
7284 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
7285 DebugLoc dl = GA->getDebugLoc();
7286 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
7287 GA->getValueType(0),
7291 X86ISD::NodeType CallType = LocalDynamic ? X86ISD::TLSBASEADDR
7295 SDValue Ops[] = { Chain, TGA, *InFlag };
7296 Chain = DAG.getNode(CallType, dl, NodeTys, Ops, 3);
7298 SDValue Ops[] = { Chain, TGA };
7299 Chain = DAG.getNode(CallType, dl, NodeTys, Ops, 2);
7302 // TLSADDR will be codegen'ed as call. Inform MFI that function has calls.
7303 MFI->setAdjustsStack(true);
7305 SDValue Flag = Chain.getValue(1);
7306 return DAG.getCopyFromReg(Chain, dl, ReturnReg, PtrVT, Flag);
7309 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 32 bit
7311 LowerToTLSGeneralDynamicModel32(GlobalAddressSDNode *GA, SelectionDAG &DAG,
7314 DebugLoc dl = GA->getDebugLoc(); // ? function entry point might be better
7315 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
7316 DAG.getNode(X86ISD::GlobalBaseReg,
7317 DebugLoc(), PtrVT), InFlag);
7318 InFlag = Chain.getValue(1);
7320 return GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX, X86II::MO_TLSGD);
7323 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 64 bit
7325 LowerToTLSGeneralDynamicModel64(GlobalAddressSDNode *GA, SelectionDAG &DAG,
7327 return GetTLSADDR(DAG, DAG.getEntryNode(), GA, NULL, PtrVT,
7328 X86::RAX, X86II::MO_TLSGD);
7331 static SDValue LowerToTLSLocalDynamicModel(GlobalAddressSDNode *GA,
7335 DebugLoc dl = GA->getDebugLoc();
7337 // Get the start address of the TLS block for this module.
7338 X86MachineFunctionInfo* MFI = DAG.getMachineFunction()
7339 .getInfo<X86MachineFunctionInfo>();
7340 MFI->incNumLocalDynamicTLSAccesses();
7344 Base = GetTLSADDR(DAG, DAG.getEntryNode(), GA, NULL, PtrVT, X86::RAX,
7345 X86II::MO_TLSLD, /*LocalDynamic=*/true);
7348 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
7349 DAG.getNode(X86ISD::GlobalBaseReg, DebugLoc(), PtrVT), InFlag);
7350 InFlag = Chain.getValue(1);
7351 Base = GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX,
7352 X86II::MO_TLSLDM, /*LocalDynamic=*/true);
7355 // Note: the CleanupLocalDynamicTLSPass will remove redundant computations
7359 unsigned char OperandFlags = X86II::MO_DTPOFF;
7360 unsigned WrapperKind = X86ISD::Wrapper;
7361 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
7362 GA->getValueType(0),
7363 GA->getOffset(), OperandFlags);
7364 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
7366 // Add x@dtpoff with the base.
7367 return DAG.getNode(ISD::ADD, dl, PtrVT, Offset, Base);
7370 // Lower ISD::GlobalTLSAddress using the "initial exec" or "local exec" model.
7371 static SDValue LowerToTLSExecModel(GlobalAddressSDNode *GA, SelectionDAG &DAG,
7372 const EVT PtrVT, TLSModel::Model model,
7373 bool is64Bit, bool isPIC) {
7374 DebugLoc dl = GA->getDebugLoc();
7376 // Get the Thread Pointer, which is %gs:0 (32-bit) or %fs:0 (64-bit).
7377 Value *Ptr = Constant::getNullValue(Type::getInt8PtrTy(*DAG.getContext(),
7378 is64Bit ? 257 : 256));
7380 SDValue ThreadPointer = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
7381 DAG.getIntPtrConstant(0),
7382 MachinePointerInfo(Ptr),
7383 false, false, false, 0);
7385 unsigned char OperandFlags = 0;
7386 // Most TLS accesses are not RIP relative, even on x86-64. One exception is
7388 unsigned WrapperKind = X86ISD::Wrapper;
7389 if (model == TLSModel::LocalExec) {
7390 OperandFlags = is64Bit ? X86II::MO_TPOFF : X86II::MO_NTPOFF;
7391 } else if (model == TLSModel::InitialExec) {
7393 OperandFlags = X86II::MO_GOTTPOFF;
7394 WrapperKind = X86ISD::WrapperRIP;
7396 OperandFlags = isPIC ? X86II::MO_GOTNTPOFF : X86II::MO_INDNTPOFF;
7399 llvm_unreachable("Unexpected model");
7402 // emit "addl x@ntpoff,%eax" (local exec)
7403 // or "addl x@indntpoff,%eax" (initial exec)
7404 // or "addl x@gotntpoff(%ebx) ,%eax" (initial exec, 32-bit pic)
7405 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
7406 GA->getValueType(0),
7407 GA->getOffset(), OperandFlags);
7408 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
7410 if (model == TLSModel::InitialExec) {
7411 if (isPIC && !is64Bit) {
7412 Offset = DAG.getNode(ISD::ADD, dl, PtrVT,
7413 DAG.getNode(X86ISD::GlobalBaseReg, DebugLoc(), PtrVT),
7417 Offset = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Offset,
7418 MachinePointerInfo::getGOT(), false, false, false,
7422 // The address of the thread local variable is the add of the thread
7423 // pointer with the offset of the variable.
7424 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset);
7428 X86TargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const {
7430 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
7431 const GlobalValue *GV = GA->getGlobal();
7433 if (Subtarget->isTargetELF()) {
7434 TLSModel::Model model = getTargetMachine().getTLSModel(GV);
7437 case TLSModel::GeneralDynamic:
7438 if (Subtarget->is64Bit())
7439 return LowerToTLSGeneralDynamicModel64(GA, DAG, getPointerTy());
7440 return LowerToTLSGeneralDynamicModel32(GA, DAG, getPointerTy());
7441 case TLSModel::LocalDynamic:
7442 return LowerToTLSLocalDynamicModel(GA, DAG, getPointerTy(),
7443 Subtarget->is64Bit());
7444 case TLSModel::InitialExec:
7445 case TLSModel::LocalExec:
7446 return LowerToTLSExecModel(GA, DAG, getPointerTy(), model,
7447 Subtarget->is64Bit(),
7448 getTargetMachine().getRelocationModel() == Reloc::PIC_);
7450 llvm_unreachable("Unknown TLS model.");
7453 if (Subtarget->isTargetDarwin()) {
7454 // Darwin only has one model of TLS. Lower to that.
7455 unsigned char OpFlag = 0;
7456 unsigned WrapperKind = Subtarget->isPICStyleRIPRel() ?
7457 X86ISD::WrapperRIP : X86ISD::Wrapper;
7459 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
7461 bool PIC32 = (getTargetMachine().getRelocationModel() == Reloc::PIC_) &&
7462 !Subtarget->is64Bit();
7464 OpFlag = X86II::MO_TLVP_PIC_BASE;
7466 OpFlag = X86II::MO_TLVP;
7467 DebugLoc DL = Op.getDebugLoc();
7468 SDValue Result = DAG.getTargetGlobalAddress(GA->getGlobal(), DL,
7469 GA->getValueType(0),
7470 GA->getOffset(), OpFlag);
7471 SDValue Offset = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
7473 // With PIC32, the address is actually $g + Offset.
7475 Offset = DAG.getNode(ISD::ADD, DL, getPointerTy(),
7476 DAG.getNode(X86ISD::GlobalBaseReg,
7477 DebugLoc(), getPointerTy()),
7480 // Lowering the machine isd will make sure everything is in the right
7482 SDValue Chain = DAG.getEntryNode();
7483 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
7484 SDValue Args[] = { Chain, Offset };
7485 Chain = DAG.getNode(X86ISD::TLSCALL, DL, NodeTys, Args, 2);
7487 // TLSCALL will be codegen'ed as call. Inform MFI that function has calls.
7488 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
7489 MFI->setAdjustsStack(true);
7491 // And our return value (tls address) is in the standard call return value
7493 unsigned Reg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
7494 return DAG.getCopyFromReg(Chain, DL, Reg, getPointerTy(),
7498 if (Subtarget->isTargetWindows()) {
7499 // Just use the implicit TLS architecture
7500 // Need to generate someting similar to:
7501 // mov rdx, qword [gs:abs 58H]; Load pointer to ThreadLocalStorage
7503 // mov ecx, dword [rel _tls_index]: Load index (from C runtime)
7504 // mov rcx, qword [rdx+rcx*8]
7505 // mov eax, .tls$:tlsvar
7506 // [rax+rcx] contains the address
7507 // Windows 64bit: gs:0x58
7508 // Windows 32bit: fs:__tls_array
7510 // If GV is an alias then use the aliasee for determining
7511 // thread-localness.
7512 if (const GlobalAlias *GA = dyn_cast<GlobalAlias>(GV))
7513 GV = GA->resolveAliasedGlobal(false);
7514 DebugLoc dl = GA->getDebugLoc();
7515 SDValue Chain = DAG.getEntryNode();
7517 // Get the Thread Pointer, which is %fs:__tls_array (32-bit) or
7518 // %gs:0x58 (64-bit).
7519 Value *Ptr = Constant::getNullValue(Subtarget->is64Bit()
7520 ? Type::getInt8PtrTy(*DAG.getContext(),
7522 : Type::getInt32PtrTy(*DAG.getContext(),
7525 SDValue ThreadPointer = DAG.getLoad(getPointerTy(), dl, Chain,
7526 Subtarget->is64Bit()
7527 ? DAG.getIntPtrConstant(0x58)
7528 : DAG.getExternalSymbol("_tls_array",
7530 MachinePointerInfo(Ptr),
7531 false, false, false, 0);
7533 // Load the _tls_index variable
7534 SDValue IDX = DAG.getExternalSymbol("_tls_index", getPointerTy());
7535 if (Subtarget->is64Bit())
7536 IDX = DAG.getExtLoad(ISD::ZEXTLOAD, dl, getPointerTy(), Chain,
7537 IDX, MachinePointerInfo(), MVT::i32,
7540 IDX = DAG.getLoad(getPointerTy(), dl, Chain, IDX, MachinePointerInfo(),
7541 false, false, false, 0);
7543 SDValue Scale = DAG.getConstant(Log2_64_Ceil(TD->getPointerSize()),
7545 IDX = DAG.getNode(ISD::SHL, dl, getPointerTy(), IDX, Scale);
7547 SDValue res = DAG.getNode(ISD::ADD, dl, getPointerTy(), ThreadPointer, IDX);
7548 res = DAG.getLoad(getPointerTy(), dl, Chain, res, MachinePointerInfo(),
7549 false, false, false, 0);
7551 // Get the offset of start of .tls section
7552 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
7553 GA->getValueType(0),
7554 GA->getOffset(), X86II::MO_SECREL);
7555 SDValue Offset = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), TGA);
7557 // The address of the thread local variable is the add of the thread
7558 // pointer with the offset of the variable.
7559 return DAG.getNode(ISD::ADD, dl, getPointerTy(), res, Offset);
7562 llvm_unreachable("TLS not implemented for this target.");
7566 /// LowerShiftParts - Lower SRA_PARTS and friends, which return two i32 values
7567 /// and take a 2 x i32 value to shift plus a shift amount.
7568 SDValue X86TargetLowering::LowerShiftParts(SDValue Op, SelectionDAG &DAG) const{
7569 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
7570 EVT VT = Op.getValueType();
7571 unsigned VTBits = VT.getSizeInBits();
7572 DebugLoc dl = Op.getDebugLoc();
7573 bool isSRA = Op.getOpcode() == ISD::SRA_PARTS;
7574 SDValue ShOpLo = Op.getOperand(0);
7575 SDValue ShOpHi = Op.getOperand(1);
7576 SDValue ShAmt = Op.getOperand(2);
7577 SDValue Tmp1 = isSRA ? DAG.getNode(ISD::SRA, dl, VT, ShOpHi,
7578 DAG.getConstant(VTBits - 1, MVT::i8))
7579 : DAG.getConstant(0, VT);
7582 if (Op.getOpcode() == ISD::SHL_PARTS) {
7583 Tmp2 = DAG.getNode(X86ISD::SHLD, dl, VT, ShOpHi, ShOpLo, ShAmt);
7584 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ShAmt);
7586 Tmp2 = DAG.getNode(X86ISD::SHRD, dl, VT, ShOpLo, ShOpHi, ShAmt);
7587 Tmp3 = DAG.getNode(isSRA ? ISD::SRA : ISD::SRL, dl, VT, ShOpHi, ShAmt);
7590 SDValue AndNode = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt,
7591 DAG.getConstant(VTBits, MVT::i8));
7592 SDValue Cond = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
7593 AndNode, DAG.getConstant(0, MVT::i8));
7596 SDValue CC = DAG.getConstant(X86::COND_NE, MVT::i8);
7597 SDValue Ops0[4] = { Tmp2, Tmp3, CC, Cond };
7598 SDValue Ops1[4] = { Tmp3, Tmp1, CC, Cond };
7600 if (Op.getOpcode() == ISD::SHL_PARTS) {
7601 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0, 4);
7602 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1, 4);
7604 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0, 4);
7605 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1, 4);
7608 SDValue Ops[2] = { Lo, Hi };
7609 return DAG.getMergeValues(Ops, 2, dl);
7612 SDValue X86TargetLowering::LowerSINT_TO_FP(SDValue Op,
7613 SelectionDAG &DAG) const {
7614 EVT SrcVT = Op.getOperand(0).getValueType();
7616 if (SrcVT.isVector())
7619 assert(SrcVT.getSimpleVT() <= MVT::i64 && SrcVT.getSimpleVT() >= MVT::i16 &&
7620 "Unknown SINT_TO_FP to lower!");
7622 // These are really Legal; return the operand so the caller accepts it as
7624 if (SrcVT == MVT::i32 && isScalarFPTypeInSSEReg(Op.getValueType()))
7626 if (SrcVT == MVT::i64 && isScalarFPTypeInSSEReg(Op.getValueType()) &&
7627 Subtarget->is64Bit()) {
7631 DebugLoc dl = Op.getDebugLoc();
7632 unsigned Size = SrcVT.getSizeInBits()/8;
7633 MachineFunction &MF = DAG.getMachineFunction();
7634 int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size, false);
7635 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
7636 SDValue Chain = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
7638 MachinePointerInfo::getFixedStack(SSFI),
7640 return BuildFILD(Op, SrcVT, Chain, StackSlot, DAG);
7643 SDValue X86TargetLowering::BuildFILD(SDValue Op, EVT SrcVT, SDValue Chain,
7645 SelectionDAG &DAG) const {
7647 DebugLoc DL = Op.getDebugLoc();
7649 bool useSSE = isScalarFPTypeInSSEReg(Op.getValueType());
7651 Tys = DAG.getVTList(MVT::f64, MVT::Other, MVT::Glue);
7653 Tys = DAG.getVTList(Op.getValueType(), MVT::Other);
7655 unsigned ByteSize = SrcVT.getSizeInBits()/8;
7657 FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(StackSlot);
7658 MachineMemOperand *MMO;
7660 int SSFI = FI->getIndex();
7662 DAG.getMachineFunction()
7663 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
7664 MachineMemOperand::MOLoad, ByteSize, ByteSize);
7666 MMO = cast<LoadSDNode>(StackSlot)->getMemOperand();
7667 StackSlot = StackSlot.getOperand(1);
7669 SDValue Ops[] = { Chain, StackSlot, DAG.getValueType(SrcVT) };
7670 SDValue Result = DAG.getMemIntrinsicNode(useSSE ? X86ISD::FILD_FLAG :
7672 Tys, Ops, array_lengthof(Ops),
7676 Chain = Result.getValue(1);
7677 SDValue InFlag = Result.getValue(2);
7679 // FIXME: Currently the FST is flagged to the FILD_FLAG. This
7680 // shouldn't be necessary except that RFP cannot be live across
7681 // multiple blocks. When stackifier is fixed, they can be uncoupled.
7682 MachineFunction &MF = DAG.getMachineFunction();
7683 unsigned SSFISize = Op.getValueType().getSizeInBits()/8;
7684 int SSFI = MF.getFrameInfo()->CreateStackObject(SSFISize, SSFISize, false);
7685 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
7686 Tys = DAG.getVTList(MVT::Other);
7688 Chain, Result, StackSlot, DAG.getValueType(Op.getValueType()), InFlag
7690 MachineMemOperand *MMO =
7691 DAG.getMachineFunction()
7692 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
7693 MachineMemOperand::MOStore, SSFISize, SSFISize);
7695 Chain = DAG.getMemIntrinsicNode(X86ISD::FST, DL, Tys,
7696 Ops, array_lengthof(Ops),
7697 Op.getValueType(), MMO);
7698 Result = DAG.getLoad(Op.getValueType(), DL, Chain, StackSlot,
7699 MachinePointerInfo::getFixedStack(SSFI),
7700 false, false, false, 0);
7706 // LowerUINT_TO_FP_i64 - 64-bit unsigned integer to double expansion.
7707 SDValue X86TargetLowering::LowerUINT_TO_FP_i64(SDValue Op,
7708 SelectionDAG &DAG) const {
7709 // This algorithm is not obvious. Here it is what we're trying to output:
7712 punpckldq (c0), %xmm0 // c0: (uint4){ 0x43300000U, 0x45300000U, 0U, 0U }
7713 subpd (c1), %xmm0 // c1: (double2){ 0x1.0p52, 0x1.0p52 * 0x1.0p32 }
7717 pshufd $0x4e, %xmm0, %xmm1
7722 DebugLoc dl = Op.getDebugLoc();
7723 LLVMContext *Context = DAG.getContext();
7725 // Build some magic constants.
7726 const uint32_t CV0[] = { 0x43300000, 0x45300000, 0, 0 };
7727 Constant *C0 = ConstantDataVector::get(*Context, CV0);
7728 SDValue CPIdx0 = DAG.getConstantPool(C0, getPointerTy(), 16);
7730 SmallVector<Constant*,2> CV1;
7732 ConstantFP::get(*Context, APFloat(APInt(64, 0x4330000000000000ULL))));
7734 ConstantFP::get(*Context, APFloat(APInt(64, 0x4530000000000000ULL))));
7735 Constant *C1 = ConstantVector::get(CV1);
7736 SDValue CPIdx1 = DAG.getConstantPool(C1, getPointerTy(), 16);
7738 // Load the 64-bit value into an XMM register.
7739 SDValue XR1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
7741 SDValue CLod0 = DAG.getLoad(MVT::v4i32, dl, DAG.getEntryNode(), CPIdx0,
7742 MachinePointerInfo::getConstantPool(),
7743 false, false, false, 16);
7744 SDValue Unpck1 = getUnpackl(DAG, dl, MVT::v4i32,
7745 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, XR1),
7748 SDValue CLod1 = DAG.getLoad(MVT::v2f64, dl, CLod0.getValue(1), CPIdx1,
7749 MachinePointerInfo::getConstantPool(),
7750 false, false, false, 16);
7751 SDValue XR2F = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Unpck1);
7752 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, XR2F, CLod1);
7755 if (Subtarget->hasSSE3()) {
7756 // FIXME: The 'haddpd' instruction may be slower than 'movhlps + addsd'.
7757 Result = DAG.getNode(X86ISD::FHADD, dl, MVT::v2f64, Sub, Sub);
7759 SDValue S2F = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Sub);
7760 SDValue Shuffle = getTargetShuffleNode(X86ISD::PSHUFD, dl, MVT::v4i32,
7762 Result = DAG.getNode(ISD::FADD, dl, MVT::v2f64,
7763 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Shuffle),
7767 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Result,
7768 DAG.getIntPtrConstant(0));
7771 // LowerUINT_TO_FP_i32 - 32-bit unsigned integer to float expansion.
7772 SDValue X86TargetLowering::LowerUINT_TO_FP_i32(SDValue Op,
7773 SelectionDAG &DAG) const {
7774 DebugLoc dl = Op.getDebugLoc();
7775 // FP constant to bias correct the final result.
7776 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL),
7779 // Load the 32-bit value into an XMM register.
7780 SDValue Load = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,
7783 // Zero out the upper parts of the register.
7784 Load = getShuffleVectorZeroOrUndef(Load, 0, true, Subtarget, DAG);
7786 Load = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
7787 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Load),
7788 DAG.getIntPtrConstant(0));
7790 // Or the load with the bias.
7791 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64,
7792 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
7793 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
7795 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
7796 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
7797 MVT::v2f64, Bias)));
7798 Or = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
7799 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Or),
7800 DAG.getIntPtrConstant(0));
7802 // Subtract the bias.
7803 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Or, Bias);
7805 // Handle final rounding.
7806 EVT DestVT = Op.getValueType();
7808 if (DestVT.bitsLT(MVT::f64))
7809 return DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub,
7810 DAG.getIntPtrConstant(0));
7811 if (DestVT.bitsGT(MVT::f64))
7812 return DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub);
7814 // Handle final rounding.
7818 SDValue X86TargetLowering::LowerUINT_TO_FP(SDValue Op,
7819 SelectionDAG &DAG) const {
7820 SDValue N0 = Op.getOperand(0);
7821 DebugLoc dl = Op.getDebugLoc();
7823 // Since UINT_TO_FP is legal (it's marked custom), dag combiner won't
7824 // optimize it to a SINT_TO_FP when the sign bit is known zero. Perform
7825 // the optimization here.
7826 if (DAG.SignBitIsZero(N0))
7827 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(), N0);
7829 EVT SrcVT = N0.getValueType();
7830 EVT DstVT = Op.getValueType();
7831 if (SrcVT == MVT::i64 && DstVT == MVT::f64 && X86ScalarSSEf64)
7832 return LowerUINT_TO_FP_i64(Op, DAG);
7833 if (SrcVT == MVT::i32 && X86ScalarSSEf64)
7834 return LowerUINT_TO_FP_i32(Op, DAG);
7835 if (Subtarget->is64Bit() && SrcVT == MVT::i64 && DstVT == MVT::f32)
7838 // Make a 64-bit buffer, and use it to build an FILD.
7839 SDValue StackSlot = DAG.CreateStackTemporary(MVT::i64);
7840 if (SrcVT == MVT::i32) {
7841 SDValue WordOff = DAG.getConstant(4, getPointerTy());
7842 SDValue OffsetSlot = DAG.getNode(ISD::ADD, dl,
7843 getPointerTy(), StackSlot, WordOff);
7844 SDValue Store1 = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
7845 StackSlot, MachinePointerInfo(),
7847 SDValue Store2 = DAG.getStore(Store1, dl, DAG.getConstant(0, MVT::i32),
7848 OffsetSlot, MachinePointerInfo(),
7850 SDValue Fild = BuildFILD(Op, MVT::i64, Store2, StackSlot, DAG);
7854 assert(SrcVT == MVT::i64 && "Unexpected type in UINT_TO_FP");
7855 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
7856 StackSlot, MachinePointerInfo(),
7858 // For i64 source, we need to add the appropriate power of 2 if the input
7859 // was negative. This is the same as the optimization in
7860 // DAGTypeLegalizer::ExpandIntOp_UNIT_TO_FP, and for it to be safe here,
7861 // we must be careful to do the computation in x87 extended precision, not
7862 // in SSE. (The generic code can't know it's OK to do this, or how to.)
7863 int SSFI = cast<FrameIndexSDNode>(StackSlot)->getIndex();
7864 MachineMemOperand *MMO =
7865 DAG.getMachineFunction()
7866 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
7867 MachineMemOperand::MOLoad, 8, 8);
7869 SDVTList Tys = DAG.getVTList(MVT::f80, MVT::Other);
7870 SDValue Ops[] = { Store, StackSlot, DAG.getValueType(MVT::i64) };
7871 SDValue Fild = DAG.getMemIntrinsicNode(X86ISD::FILD, dl, Tys, Ops, 3,
7874 APInt FF(32, 0x5F800000ULL);
7876 // Check whether the sign bit is set.
7877 SDValue SignSet = DAG.getSetCC(dl, getSetCCResultType(MVT::i64),
7878 Op.getOperand(0), DAG.getConstant(0, MVT::i64),
7881 // Build a 64 bit pair (0, FF) in the constant pool, with FF in the lo bits.
7882 SDValue FudgePtr = DAG.getConstantPool(
7883 ConstantInt::get(*DAG.getContext(), FF.zext(64)),
7886 // Get a pointer to FF if the sign bit was set, or to 0 otherwise.
7887 SDValue Zero = DAG.getIntPtrConstant(0);
7888 SDValue Four = DAG.getIntPtrConstant(4);
7889 SDValue Offset = DAG.getNode(ISD::SELECT, dl, Zero.getValueType(), SignSet,
7891 FudgePtr = DAG.getNode(ISD::ADD, dl, getPointerTy(), FudgePtr, Offset);
7893 // Load the value out, extending it from f32 to f80.
7894 // FIXME: Avoid the extend by constructing the right constant pool?
7895 SDValue Fudge = DAG.getExtLoad(ISD::EXTLOAD, dl, MVT::f80, DAG.getEntryNode(),
7896 FudgePtr, MachinePointerInfo::getConstantPool(),
7897 MVT::f32, false, false, 4);
7898 // Extend everything to 80 bits to force it to be done on x87.
7899 SDValue Add = DAG.getNode(ISD::FADD, dl, MVT::f80, Fild, Fudge);
7900 return DAG.getNode(ISD::FP_ROUND, dl, DstVT, Add, DAG.getIntPtrConstant(0));
7903 std::pair<SDValue,SDValue> X86TargetLowering::
7904 FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG, bool IsSigned, bool IsReplace) const {
7905 DebugLoc DL = Op.getDebugLoc();
7907 EVT DstTy = Op.getValueType();
7909 if (!IsSigned && !isIntegerTypeFTOL(DstTy)) {
7910 assert(DstTy == MVT::i32 && "Unexpected FP_TO_UINT");
7914 assert(DstTy.getSimpleVT() <= MVT::i64 &&
7915 DstTy.getSimpleVT() >= MVT::i16 &&
7916 "Unknown FP_TO_INT to lower!");
7918 // These are really Legal.
7919 if (DstTy == MVT::i32 &&
7920 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
7921 return std::make_pair(SDValue(), SDValue());
7922 if (Subtarget->is64Bit() &&
7923 DstTy == MVT::i64 &&
7924 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
7925 return std::make_pair(SDValue(), SDValue());
7927 // We lower FP->int64 either into FISTP64 followed by a load from a temporary
7928 // stack slot, or into the FTOL runtime function.
7929 MachineFunction &MF = DAG.getMachineFunction();
7930 unsigned MemSize = DstTy.getSizeInBits()/8;
7931 int SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
7932 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
7935 if (!IsSigned && isIntegerTypeFTOL(DstTy))
7936 Opc = X86ISD::WIN_FTOL;
7938 switch (DstTy.getSimpleVT().SimpleTy) {
7939 default: llvm_unreachable("Invalid FP_TO_SINT to lower!");
7940 case MVT::i16: Opc = X86ISD::FP_TO_INT16_IN_MEM; break;
7941 case MVT::i32: Opc = X86ISD::FP_TO_INT32_IN_MEM; break;
7942 case MVT::i64: Opc = X86ISD::FP_TO_INT64_IN_MEM; break;
7945 SDValue Chain = DAG.getEntryNode();
7946 SDValue Value = Op.getOperand(0);
7947 EVT TheVT = Op.getOperand(0).getValueType();
7948 // FIXME This causes a redundant load/store if the SSE-class value is already
7949 // in memory, such as if it is on the callstack.
7950 if (isScalarFPTypeInSSEReg(TheVT)) {
7951 assert(DstTy == MVT::i64 && "Invalid FP_TO_SINT to lower!");
7952 Chain = DAG.getStore(Chain, DL, Value, StackSlot,
7953 MachinePointerInfo::getFixedStack(SSFI),
7955 SDVTList Tys = DAG.getVTList(Op.getOperand(0).getValueType(), MVT::Other);
7957 Chain, StackSlot, DAG.getValueType(TheVT)
7960 MachineMemOperand *MMO =
7961 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
7962 MachineMemOperand::MOLoad, MemSize, MemSize);
7963 Value = DAG.getMemIntrinsicNode(X86ISD::FLD, DL, Tys, Ops, 3,
7965 Chain = Value.getValue(1);
7966 SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
7967 StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
7970 MachineMemOperand *MMO =
7971 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
7972 MachineMemOperand::MOStore, MemSize, MemSize);
7974 if (Opc != X86ISD::WIN_FTOL) {
7975 // Build the FP_TO_INT*_IN_MEM
7976 SDValue Ops[] = { Chain, Value, StackSlot };
7977 SDValue FIST = DAG.getMemIntrinsicNode(Opc, DL, DAG.getVTList(MVT::Other),
7978 Ops, 3, DstTy, MMO);
7979 return std::make_pair(FIST, StackSlot);
7981 SDValue ftol = DAG.getNode(X86ISD::WIN_FTOL, DL,
7982 DAG.getVTList(MVT::Other, MVT::Glue),
7984 SDValue eax = DAG.getCopyFromReg(ftol, DL, X86::EAX,
7985 MVT::i32, ftol.getValue(1));
7986 SDValue edx = DAG.getCopyFromReg(eax.getValue(1), DL, X86::EDX,
7987 MVT::i32, eax.getValue(2));
7988 SDValue Ops[] = { eax, edx };
7989 SDValue pair = IsReplace
7990 ? DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops, 2)
7991 : DAG.getMergeValues(Ops, 2, DL);
7992 return std::make_pair(pair, SDValue());
7996 SDValue X86TargetLowering::LowerFP_TO_SINT(SDValue Op,
7997 SelectionDAG &DAG) const {
7998 if (Op.getValueType().isVector())
8001 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG,
8002 /*IsSigned=*/ true, /*IsReplace=*/ false);
8003 SDValue FIST = Vals.first, StackSlot = Vals.second;
8004 // If FP_TO_INTHelper failed, the node is actually supposed to be Legal.
8005 if (FIST.getNode() == 0) return Op;
8007 if (StackSlot.getNode())
8009 return DAG.getLoad(Op.getValueType(), Op.getDebugLoc(),
8010 FIST, StackSlot, MachinePointerInfo(),
8011 false, false, false, 0);
8013 // The node is the result.
8017 SDValue X86TargetLowering::LowerFP_TO_UINT(SDValue Op,
8018 SelectionDAG &DAG) const {
8019 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG,
8020 /*IsSigned=*/ false, /*IsReplace=*/ false);
8021 SDValue FIST = Vals.first, StackSlot = Vals.second;
8022 assert(FIST.getNode() && "Unexpected failure");
8024 if (StackSlot.getNode())
8026 return DAG.getLoad(Op.getValueType(), Op.getDebugLoc(),
8027 FIST, StackSlot, MachinePointerInfo(),
8028 false, false, false, 0);
8030 // The node is the result.
8034 SDValue X86TargetLowering::LowerFABS(SDValue Op,
8035 SelectionDAG &DAG) const {
8036 LLVMContext *Context = DAG.getContext();
8037 DebugLoc dl = Op.getDebugLoc();
8038 EVT VT = Op.getValueType();
8041 EltVT = VT.getVectorElementType();
8043 if (EltVT == MVT::f64) {
8044 C = ConstantVector::getSplat(2,
8045 ConstantFP::get(*Context, APFloat(APInt(64, ~(1ULL << 63)))));
8047 C = ConstantVector::getSplat(4,
8048 ConstantFP::get(*Context, APFloat(APInt(32, ~(1U << 31)))));
8050 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
8051 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
8052 MachinePointerInfo::getConstantPool(),
8053 false, false, false, 16);
8054 return DAG.getNode(X86ISD::FAND, dl, VT, Op.getOperand(0), Mask);
8057 SDValue X86TargetLowering::LowerFNEG(SDValue Op, SelectionDAG &DAG) const {
8058 LLVMContext *Context = DAG.getContext();
8059 DebugLoc dl = Op.getDebugLoc();
8060 EVT VT = Op.getValueType();
8062 unsigned NumElts = VT == MVT::f64 ? 2 : 4;
8063 if (VT.isVector()) {
8064 EltVT = VT.getVectorElementType();
8065 NumElts = VT.getVectorNumElements();
8068 if (EltVT == MVT::f64)
8069 C = ConstantFP::get(*Context, APFloat(APInt(64, 1ULL << 63)));
8071 C = ConstantFP::get(*Context, APFloat(APInt(32, 1U << 31)));
8072 C = ConstantVector::getSplat(NumElts, C);
8073 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
8074 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
8075 MachinePointerInfo::getConstantPool(),
8076 false, false, false, 16);
8077 if (VT.isVector()) {
8078 MVT XORVT = VT.is128BitVector() ? MVT::v2i64 : MVT::v4i64;
8079 return DAG.getNode(ISD::BITCAST, dl, VT,
8080 DAG.getNode(ISD::XOR, dl, XORVT,
8081 DAG.getNode(ISD::BITCAST, dl, XORVT,
8083 DAG.getNode(ISD::BITCAST, dl, XORVT, Mask)));
8086 return DAG.getNode(X86ISD::FXOR, dl, VT, Op.getOperand(0), Mask);
8089 SDValue X86TargetLowering::LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const {
8090 LLVMContext *Context = DAG.getContext();
8091 SDValue Op0 = Op.getOperand(0);
8092 SDValue Op1 = Op.getOperand(1);
8093 DebugLoc dl = Op.getDebugLoc();
8094 EVT VT = Op.getValueType();
8095 EVT SrcVT = Op1.getValueType();
8097 // If second operand is smaller, extend it first.
8098 if (SrcVT.bitsLT(VT)) {
8099 Op1 = DAG.getNode(ISD::FP_EXTEND, dl, VT, Op1);
8102 // And if it is bigger, shrink it first.
8103 if (SrcVT.bitsGT(VT)) {
8104 Op1 = DAG.getNode(ISD::FP_ROUND, dl, VT, Op1, DAG.getIntPtrConstant(1));
8108 // At this point the operands and the result should have the same
8109 // type, and that won't be f80 since that is not custom lowered.
8111 // First get the sign bit of second operand.
8112 SmallVector<Constant*,4> CV;
8113 if (SrcVT == MVT::f64) {
8114 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, 1ULL << 63))));
8115 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, 0))));
8117 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 1U << 31))));
8118 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
8119 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
8120 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
8122 Constant *C = ConstantVector::get(CV);
8123 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
8124 SDValue Mask1 = DAG.getLoad(SrcVT, dl, DAG.getEntryNode(), CPIdx,
8125 MachinePointerInfo::getConstantPool(),
8126 false, false, false, 16);
8127 SDValue SignBit = DAG.getNode(X86ISD::FAND, dl, SrcVT, Op1, Mask1);
8129 // Shift sign bit right or left if the two operands have different types.
8130 if (SrcVT.bitsGT(VT)) {
8131 // Op0 is MVT::f32, Op1 is MVT::f64.
8132 SignBit = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f64, SignBit);
8133 SignBit = DAG.getNode(X86ISD::FSRL, dl, MVT::v2f64, SignBit,
8134 DAG.getConstant(32, MVT::i32));
8135 SignBit = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, SignBit);
8136 SignBit = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f32, SignBit,
8137 DAG.getIntPtrConstant(0));
8140 // Clear first operand sign bit.
8142 if (VT == MVT::f64) {
8143 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, ~(1ULL << 63)))));
8144 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, 0))));
8146 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, ~(1U << 31)))));
8147 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
8148 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
8149 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
8151 C = ConstantVector::get(CV);
8152 CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
8153 SDValue Mask2 = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
8154 MachinePointerInfo::getConstantPool(),
8155 false, false, false, 16);
8156 SDValue Val = DAG.getNode(X86ISD::FAND, dl, VT, Op0, Mask2);
8158 // Or the value with the sign bit.
8159 return DAG.getNode(X86ISD::FOR, dl, VT, Val, SignBit);
8162 SDValue X86TargetLowering::LowerFGETSIGN(SDValue Op, SelectionDAG &DAG) const {
8163 SDValue N0 = Op.getOperand(0);
8164 DebugLoc dl = Op.getDebugLoc();
8165 EVT VT = Op.getValueType();
8167 // Lower ISD::FGETSIGN to (AND (X86ISD::FGETSIGNx86 ...) 1).
8168 SDValue xFGETSIGN = DAG.getNode(X86ISD::FGETSIGNx86, dl, VT, N0,
8169 DAG.getConstant(1, VT));
8170 return DAG.getNode(ISD::AND, dl, VT, xFGETSIGN, DAG.getConstant(1, VT));
8173 /// Emit nodes that will be selected as "test Op0,Op0", or something
8175 SDValue X86TargetLowering::EmitTest(SDValue Op, unsigned X86CC,
8176 SelectionDAG &DAG) const {
8177 DebugLoc dl = Op.getDebugLoc();
8179 // CF and OF aren't always set the way we want. Determine which
8180 // of these we need.
8181 bool NeedCF = false;
8182 bool NeedOF = false;
8185 case X86::COND_A: case X86::COND_AE:
8186 case X86::COND_B: case X86::COND_BE:
8189 case X86::COND_G: case X86::COND_GE:
8190 case X86::COND_L: case X86::COND_LE:
8191 case X86::COND_O: case X86::COND_NO:
8196 // See if we can use the EFLAGS value from the operand instead of
8197 // doing a separate TEST. TEST always sets OF and CF to 0, so unless
8198 // we prove that the arithmetic won't overflow, we can't use OF or CF.
8199 if (Op.getResNo() != 0 || NeedOF || NeedCF)
8200 // Emit a CMP with 0, which is the TEST pattern.
8201 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
8202 DAG.getConstant(0, Op.getValueType()));
8204 unsigned Opcode = 0;
8205 unsigned NumOperands = 0;
8206 switch (Op.getNode()->getOpcode()) {
8208 // Due to an isel shortcoming, be conservative if this add is likely to be
8209 // selected as part of a load-modify-store instruction. When the root node
8210 // in a match is a store, isel doesn't know how to remap non-chain non-flag
8211 // uses of other nodes in the match, such as the ADD in this case. This
8212 // leads to the ADD being left around and reselected, with the result being
8213 // two adds in the output. Alas, even if none our users are stores, that
8214 // doesn't prove we're O.K. Ergo, if we have any parents that aren't
8215 // CopyToReg or SETCC, eschew INC/DEC. A better fix seems to require
8216 // climbing the DAG back to the root, and it doesn't seem to be worth the
8218 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
8219 UE = Op.getNode()->use_end(); UI != UE; ++UI)
8220 if (UI->getOpcode() != ISD::CopyToReg &&
8221 UI->getOpcode() != ISD::SETCC &&
8222 UI->getOpcode() != ISD::STORE)
8225 if (ConstantSDNode *C =
8226 dyn_cast<ConstantSDNode>(Op.getNode()->getOperand(1))) {
8227 // An add of one will be selected as an INC.
8228 if (C->getAPIntValue() == 1) {
8229 Opcode = X86ISD::INC;
8234 // An add of negative one (subtract of one) will be selected as a DEC.
8235 if (C->getAPIntValue().isAllOnesValue()) {
8236 Opcode = X86ISD::DEC;
8242 // Otherwise use a regular EFLAGS-setting add.
8243 Opcode = X86ISD::ADD;
8247 // If the primary and result isn't used, don't bother using X86ISD::AND,
8248 // because a TEST instruction will be better.
8249 bool NonFlagUse = false;
8250 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
8251 UE = Op.getNode()->use_end(); UI != UE; ++UI) {
8253 unsigned UOpNo = UI.getOperandNo();
8254 if (User->getOpcode() == ISD::TRUNCATE && User->hasOneUse()) {
8255 // Look pass truncate.
8256 UOpNo = User->use_begin().getOperandNo();
8257 User = *User->use_begin();
8260 if (User->getOpcode() != ISD::BRCOND &&
8261 User->getOpcode() != ISD::SETCC &&
8262 (User->getOpcode() != ISD::SELECT || UOpNo != 0)) {
8275 // Due to the ISEL shortcoming noted above, be conservative if this op is
8276 // likely to be selected as part of a load-modify-store instruction.
8277 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
8278 UE = Op.getNode()->use_end(); UI != UE; ++UI)
8279 if (UI->getOpcode() == ISD::STORE)
8282 // Otherwise use a regular EFLAGS-setting instruction.
8283 switch (Op.getNode()->getOpcode()) {
8284 default: llvm_unreachable("unexpected operator!");
8286 Opcode = X86ISD::SUB;
8288 case ISD::OR: Opcode = X86ISD::OR; break;
8289 case ISD::XOR: Opcode = X86ISD::XOR; break;
8290 case ISD::AND: Opcode = X86ISD::AND; break;
8302 return SDValue(Op.getNode(), 1);
8309 // Emit a CMP with 0, which is the TEST pattern.
8310 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
8311 DAG.getConstant(0, Op.getValueType()));
8313 if (Opcode == X86ISD::CMP) {
8314 SDValue New = DAG.getNode(Opcode, dl, MVT::i32, Op.getOperand(0),
8316 // We can't replace usage of SUB with CMP.
8317 // The SUB node will be removed later because there is no use of it.
8318 return SDValue(New.getNode(), 0);
8321 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
8322 SmallVector<SDValue, 4> Ops;
8323 for (unsigned i = 0; i != NumOperands; ++i)
8324 Ops.push_back(Op.getOperand(i));
8326 SDValue New = DAG.getNode(Opcode, dl, VTs, &Ops[0], NumOperands);
8327 DAG.ReplaceAllUsesWith(Op, New);
8328 return SDValue(New.getNode(), 1);
8331 /// Emit nodes that will be selected as "cmp Op0,Op1", or something
8333 SDValue X86TargetLowering::EmitCmp(SDValue Op0, SDValue Op1, unsigned X86CC,
8334 SelectionDAG &DAG) const {
8335 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op1))
8336 if (C->getAPIntValue() == 0)
8337 return EmitTest(Op0, X86CC, DAG);
8339 DebugLoc dl = Op0.getDebugLoc();
8340 if ((Op0.getValueType() == MVT::i8 || Op0.getValueType() == MVT::i16 ||
8341 Op0.getValueType() == MVT::i32 || Op0.getValueType() == MVT::i64)) {
8342 // Use SUB instead of CMP to enable CSE between SUB and CMP.
8343 SDVTList VTs = DAG.getVTList(Op0.getValueType(), MVT::i32);
8344 SDValue Sub = DAG.getNode(X86ISD::SUB, dl, VTs,
8346 return SDValue(Sub.getNode(), 1);
8348 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op0, Op1);
8351 /// Convert a comparison if required by the subtarget.
8352 SDValue X86TargetLowering::ConvertCmpIfNecessary(SDValue Cmp,
8353 SelectionDAG &DAG) const {
8354 // If the subtarget does not support the FUCOMI instruction, floating-point
8355 // comparisons have to be converted.
8356 if (Subtarget->hasCMov() ||
8357 Cmp.getOpcode() != X86ISD::CMP ||
8358 !Cmp.getOperand(0).getValueType().isFloatingPoint() ||
8359 !Cmp.getOperand(1).getValueType().isFloatingPoint())
8362 // The instruction selector will select an FUCOM instruction instead of
8363 // FUCOMI, which writes the comparison result to FPSW instead of EFLAGS. Hence
8364 // build an SDNode sequence that transfers the result from FPSW into EFLAGS:
8365 // (X86sahf (trunc (srl (X86fp_stsw (trunc (X86cmp ...)), 8))))
8366 DebugLoc dl = Cmp.getDebugLoc();
8367 SDValue TruncFPSW = DAG.getNode(ISD::TRUNCATE, dl, MVT::i16, Cmp);
8368 SDValue FNStSW = DAG.getNode(X86ISD::FNSTSW16r, dl, MVT::i16, TruncFPSW);
8369 SDValue Srl = DAG.getNode(ISD::SRL, dl, MVT::i16, FNStSW,
8370 DAG.getConstant(8, MVT::i8));
8371 SDValue TruncSrl = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Srl);
8372 return DAG.getNode(X86ISD::SAHF, dl, MVT::i32, TruncSrl);
8375 /// LowerToBT - Result of 'and' is compared against zero. Turn it into a BT node
8376 /// if it's possible.
8377 SDValue X86TargetLowering::LowerToBT(SDValue And, ISD::CondCode CC,
8378 DebugLoc dl, SelectionDAG &DAG) const {
8379 SDValue Op0 = And.getOperand(0);
8380 SDValue Op1 = And.getOperand(1);
8381 if (Op0.getOpcode() == ISD::TRUNCATE)
8382 Op0 = Op0.getOperand(0);
8383 if (Op1.getOpcode() == ISD::TRUNCATE)
8384 Op1 = Op1.getOperand(0);
8387 if (Op1.getOpcode() == ISD::SHL)
8388 std::swap(Op0, Op1);
8389 if (Op0.getOpcode() == ISD::SHL) {
8390 if (ConstantSDNode *And00C = dyn_cast<ConstantSDNode>(Op0.getOperand(0)))
8391 if (And00C->getZExtValue() == 1) {
8392 // If we looked past a truncate, check that it's only truncating away
8394 unsigned BitWidth = Op0.getValueSizeInBits();
8395 unsigned AndBitWidth = And.getValueSizeInBits();
8396 if (BitWidth > AndBitWidth) {
8398 DAG.ComputeMaskedBits(Op0, Zeros, Ones);
8399 if (Zeros.countLeadingOnes() < BitWidth - AndBitWidth)
8403 RHS = Op0.getOperand(1);
8405 } else if (Op1.getOpcode() == ISD::Constant) {
8406 ConstantSDNode *AndRHS = cast<ConstantSDNode>(Op1);
8407 uint64_t AndRHSVal = AndRHS->getZExtValue();
8408 SDValue AndLHS = Op0;
8410 if (AndRHSVal == 1 && AndLHS.getOpcode() == ISD::SRL) {
8411 LHS = AndLHS.getOperand(0);
8412 RHS = AndLHS.getOperand(1);
8415 // Use BT if the immediate can't be encoded in a TEST instruction.
8416 if (!isUInt<32>(AndRHSVal) && isPowerOf2_64(AndRHSVal)) {
8418 RHS = DAG.getConstant(Log2_64_Ceil(AndRHSVal), LHS.getValueType());
8422 if (LHS.getNode()) {
8423 // If LHS is i8, promote it to i32 with any_extend. There is no i8 BT
8424 // instruction. Since the shift amount is in-range-or-undefined, we know
8425 // that doing a bittest on the i32 value is ok. We extend to i32 because
8426 // the encoding for the i16 version is larger than the i32 version.
8427 // Also promote i16 to i32 for performance / code size reason.
8428 if (LHS.getValueType() == MVT::i8 ||
8429 LHS.getValueType() == MVT::i16)
8430 LHS = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, LHS);
8432 // If the operand types disagree, extend the shift amount to match. Since
8433 // BT ignores high bits (like shifts) we can use anyextend.
8434 if (LHS.getValueType() != RHS.getValueType())
8435 RHS = DAG.getNode(ISD::ANY_EXTEND, dl, LHS.getValueType(), RHS);
8437 SDValue BT = DAG.getNode(X86ISD::BT, dl, MVT::i32, LHS, RHS);
8438 unsigned Cond = CC == ISD::SETEQ ? X86::COND_AE : X86::COND_B;
8439 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
8440 DAG.getConstant(Cond, MVT::i8), BT);
8446 SDValue X86TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
8448 if (Op.getValueType().isVector()) return LowerVSETCC(Op, DAG);
8450 assert(Op.getValueType() == MVT::i8 && "SetCC type must be 8-bit integer");
8451 SDValue Op0 = Op.getOperand(0);
8452 SDValue Op1 = Op.getOperand(1);
8453 DebugLoc dl = Op.getDebugLoc();
8454 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
8456 // Optimize to BT if possible.
8457 // Lower (X & (1 << N)) == 0 to BT(X, N).
8458 // Lower ((X >>u N) & 1) != 0 to BT(X, N).
8459 // Lower ((X >>s N) & 1) != 0 to BT(X, N).
8460 if (Op0.getOpcode() == ISD::AND && Op0.hasOneUse() &&
8461 Op1.getOpcode() == ISD::Constant &&
8462 cast<ConstantSDNode>(Op1)->isNullValue() &&
8463 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
8464 SDValue NewSetCC = LowerToBT(Op0, CC, dl, DAG);
8465 if (NewSetCC.getNode())
8469 // Look for X == 0, X == 1, X != 0, or X != 1. We can simplify some forms of
8471 if (Op1.getOpcode() == ISD::Constant &&
8472 (cast<ConstantSDNode>(Op1)->getZExtValue() == 1 ||
8473 cast<ConstantSDNode>(Op1)->isNullValue()) &&
8474 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
8476 // If the input is a setcc, then reuse the input setcc or use a new one with
8477 // the inverted condition.
8478 if (Op0.getOpcode() == X86ISD::SETCC) {
8479 X86::CondCode CCode = (X86::CondCode)Op0.getConstantOperandVal(0);
8480 bool Invert = (CC == ISD::SETNE) ^
8481 cast<ConstantSDNode>(Op1)->isNullValue();
8482 if (!Invert) return Op0;
8484 CCode = X86::GetOppositeBranchCondition(CCode);
8485 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
8486 DAG.getConstant(CCode, MVT::i8), Op0.getOperand(1));
8490 bool isFP = Op1.getValueType().isFloatingPoint();
8491 unsigned X86CC = TranslateX86CC(CC, isFP, Op0, Op1, DAG);
8492 if (X86CC == X86::COND_INVALID)
8495 SDValue EFLAGS = EmitCmp(Op0, Op1, X86CC, DAG);
8496 EFLAGS = ConvertCmpIfNecessary(EFLAGS, DAG);
8497 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
8498 DAG.getConstant(X86CC, MVT::i8), EFLAGS);
8501 // Lower256IntVSETCC - Break a VSETCC 256-bit integer VSETCC into two new 128
8502 // ones, and then concatenate the result back.
8503 static SDValue Lower256IntVSETCC(SDValue Op, SelectionDAG &DAG) {
8504 EVT VT = Op.getValueType();
8506 assert(VT.is256BitVector() && Op.getOpcode() == ISD::SETCC &&
8507 "Unsupported value type for operation");
8509 unsigned NumElems = VT.getVectorNumElements();
8510 DebugLoc dl = Op.getDebugLoc();
8511 SDValue CC = Op.getOperand(2);
8513 // Extract the LHS vectors
8514 SDValue LHS = Op.getOperand(0);
8515 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
8516 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
8518 // Extract the RHS vectors
8519 SDValue RHS = Op.getOperand(1);
8520 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, dl);
8521 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, dl);
8523 // Issue the operation on the smaller types and concatenate the result back
8524 MVT EltVT = VT.getVectorElementType().getSimpleVT();
8525 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
8526 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
8527 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1, CC),
8528 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2, CC));
8532 SDValue X86TargetLowering::LowerVSETCC(SDValue Op, SelectionDAG &DAG) const {
8534 SDValue Op0 = Op.getOperand(0);
8535 SDValue Op1 = Op.getOperand(1);
8536 SDValue CC = Op.getOperand(2);
8537 EVT VT = Op.getValueType();
8538 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
8539 bool isFP = Op.getOperand(1).getValueType().isFloatingPoint();
8540 DebugLoc dl = Op.getDebugLoc();
8544 EVT EltVT = Op0.getValueType().getVectorElementType();
8545 assert(EltVT == MVT::f32 || EltVT == MVT::f64);
8551 // SSE Condition code mapping:
8560 switch (SetCCOpcode) {
8561 default: llvm_unreachable("Unexpected SETCC condition");
8563 case ISD::SETEQ: SSECC = 0; break;
8565 case ISD::SETGT: Swap = true; // Fallthrough
8567 case ISD::SETOLT: SSECC = 1; break;
8569 case ISD::SETGE: Swap = true; // Fallthrough
8571 case ISD::SETOLE: SSECC = 2; break;
8572 case ISD::SETUO: SSECC = 3; break;
8574 case ISD::SETNE: SSECC = 4; break;
8575 case ISD::SETULE: Swap = true; // Fallthrough
8576 case ISD::SETUGE: SSECC = 5; break;
8577 case ISD::SETULT: Swap = true; // Fallthrough
8578 case ISD::SETUGT: SSECC = 6; break;
8579 case ISD::SETO: SSECC = 7; break;
8581 case ISD::SETONE: SSECC = 8; break;
8584 std::swap(Op0, Op1);
8586 // In the two special cases we can't handle, emit two comparisons.
8589 unsigned CombineOpc;
8590 if (SetCCOpcode == ISD::SETUEQ) {
8591 CC0 = 3; CC1 = 0; CombineOpc = ISD::OR;
8593 assert(SetCCOpcode == ISD::SETONE);
8594 CC0 = 7; CC1 = 4; CombineOpc = ISD::AND;
8597 SDValue Cmp0 = DAG.getNode(X86ISD::CMPP, dl, VT, Op0, Op1,
8598 DAG.getConstant(CC0, MVT::i8));
8599 SDValue Cmp1 = DAG.getNode(X86ISD::CMPP, dl, VT, Op0, Op1,
8600 DAG.getConstant(CC1, MVT::i8));
8601 return DAG.getNode(CombineOpc, dl, VT, Cmp0, Cmp1);
8603 // Handle all other FP comparisons here.
8604 return DAG.getNode(X86ISD::CMPP, dl, VT, Op0, Op1,
8605 DAG.getConstant(SSECC, MVT::i8));
8608 // Break 256-bit integer vector compare into smaller ones.
8609 if (VT.is256BitVector() && !Subtarget->hasAVX2())
8610 return Lower256IntVSETCC(Op, DAG);
8612 // We are handling one of the integer comparisons here. Since SSE only has
8613 // GT and EQ comparisons for integer, swapping operands and multiple
8614 // operations may be required for some comparisons.
8616 bool Swap = false, Invert = false, FlipSigns = false;
8618 switch (SetCCOpcode) {
8619 default: llvm_unreachable("Unexpected SETCC condition");
8620 case ISD::SETNE: Invert = true;
8621 case ISD::SETEQ: Opc = X86ISD::PCMPEQ; break;
8622 case ISD::SETLT: Swap = true;
8623 case ISD::SETGT: Opc = X86ISD::PCMPGT; break;
8624 case ISD::SETGE: Swap = true;
8625 case ISD::SETLE: Opc = X86ISD::PCMPGT; Invert = true; break;
8626 case ISD::SETULT: Swap = true;
8627 case ISD::SETUGT: Opc = X86ISD::PCMPGT; FlipSigns = true; break;
8628 case ISD::SETUGE: Swap = true;
8629 case ISD::SETULE: Opc = X86ISD::PCMPGT; FlipSigns = true; Invert = true; break;
8632 std::swap(Op0, Op1);
8634 // Check that the operation in question is available (most are plain SSE2,
8635 // but PCMPGTQ and PCMPEQQ have different requirements).
8636 if (VT == MVT::v2i64) {
8637 if (Opc == X86ISD::PCMPGT && !Subtarget->hasSSE42())
8639 if (Opc == X86ISD::PCMPEQ && !Subtarget->hasSSE41())
8643 // Since SSE has no unsigned integer comparisons, we need to flip the sign
8644 // bits of the inputs before performing those operations.
8646 EVT EltVT = VT.getVectorElementType();
8647 SDValue SignBit = DAG.getConstant(APInt::getSignBit(EltVT.getSizeInBits()),
8649 std::vector<SDValue> SignBits(VT.getVectorNumElements(), SignBit);
8650 SDValue SignVec = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &SignBits[0],
8652 Op0 = DAG.getNode(ISD::XOR, dl, VT, Op0, SignVec);
8653 Op1 = DAG.getNode(ISD::XOR, dl, VT, Op1, SignVec);
8656 SDValue Result = DAG.getNode(Opc, dl, VT, Op0, Op1);
8658 // If the logical-not of the result is required, perform that now.
8660 Result = DAG.getNOT(dl, Result, VT);
8665 // isX86LogicalCmp - Return true if opcode is a X86 logical comparison.
8666 static bool isX86LogicalCmp(SDValue Op) {
8667 unsigned Opc = Op.getNode()->getOpcode();
8668 if (Opc == X86ISD::CMP || Opc == X86ISD::COMI || Opc == X86ISD::UCOMI ||
8669 Opc == X86ISD::SAHF)
8671 if (Op.getResNo() == 1 &&
8672 (Opc == X86ISD::ADD ||
8673 Opc == X86ISD::SUB ||
8674 Opc == X86ISD::ADC ||
8675 Opc == X86ISD::SBB ||
8676 Opc == X86ISD::SMUL ||
8677 Opc == X86ISD::UMUL ||
8678 Opc == X86ISD::INC ||
8679 Opc == X86ISD::DEC ||
8680 Opc == X86ISD::OR ||
8681 Opc == X86ISD::XOR ||
8682 Opc == X86ISD::AND))
8685 if (Op.getResNo() == 2 && Opc == X86ISD::UMUL)
8691 static bool isZero(SDValue V) {
8692 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V);
8693 return C && C->isNullValue();
8696 static bool isAllOnes(SDValue V) {
8697 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V);
8698 return C && C->isAllOnesValue();
8701 static bool isTruncWithZeroHighBitsInput(SDValue V, SelectionDAG &DAG) {
8702 if (V.getOpcode() != ISD::TRUNCATE)
8705 SDValue VOp0 = V.getOperand(0);
8706 unsigned InBits = VOp0.getValueSizeInBits();
8707 unsigned Bits = V.getValueSizeInBits();
8708 return DAG.MaskedValueIsZero(VOp0, APInt::getHighBitsSet(InBits,InBits-Bits));
8711 SDValue X86TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {
8712 bool addTest = true;
8713 SDValue Cond = Op.getOperand(0);
8714 SDValue Op1 = Op.getOperand(1);
8715 SDValue Op2 = Op.getOperand(2);
8716 DebugLoc DL = Op.getDebugLoc();
8719 if (Cond.getOpcode() == ISD::SETCC) {
8720 SDValue NewCond = LowerSETCC(Cond, DAG);
8721 if (NewCond.getNode())
8725 // (select (x == 0), -1, y) -> (sign_bit (x - 1)) | y
8726 // (select (x == 0), y, -1) -> ~(sign_bit (x - 1)) | y
8727 // (select (x != 0), y, -1) -> (sign_bit (x - 1)) | y
8728 // (select (x != 0), -1, y) -> ~(sign_bit (x - 1)) | y
8729 if (Cond.getOpcode() == X86ISD::SETCC &&
8730 Cond.getOperand(1).getOpcode() == X86ISD::CMP &&
8731 isZero(Cond.getOperand(1).getOperand(1))) {
8732 SDValue Cmp = Cond.getOperand(1);
8734 unsigned CondCode =cast<ConstantSDNode>(Cond.getOperand(0))->getZExtValue();
8736 if ((isAllOnes(Op1) || isAllOnes(Op2)) &&
8737 (CondCode == X86::COND_E || CondCode == X86::COND_NE)) {
8738 SDValue Y = isAllOnes(Op2) ? Op1 : Op2;
8740 SDValue CmpOp0 = Cmp.getOperand(0);
8741 // Apply further optimizations for special cases
8742 // (select (x != 0), -1, 0) -> neg & sbb
8743 // (select (x == 0), 0, -1) -> neg & sbb
8744 if (ConstantSDNode *YC = dyn_cast<ConstantSDNode>(Y))
8745 if (YC->isNullValue() &&
8746 (isAllOnes(Op1) == (CondCode == X86::COND_NE))) {
8747 SDVTList VTs = DAG.getVTList(CmpOp0.getValueType(), MVT::i32);
8748 SDValue Neg = DAG.getNode(X86ISD::SUB, DL, VTs,
8749 DAG.getConstant(0, CmpOp0.getValueType()),
8751 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
8752 DAG.getConstant(X86::COND_B, MVT::i8),
8753 SDValue(Neg.getNode(), 1));
8757 Cmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32,
8758 CmpOp0, DAG.getConstant(1, CmpOp0.getValueType()));
8759 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
8761 SDValue Res = // Res = 0 or -1.
8762 DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
8763 DAG.getConstant(X86::COND_B, MVT::i8), Cmp);
8765 if (isAllOnes(Op1) != (CondCode == X86::COND_E))
8766 Res = DAG.getNOT(DL, Res, Res.getValueType());
8768 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(Op2);
8769 if (N2C == 0 || !N2C->isNullValue())
8770 Res = DAG.getNode(ISD::OR, DL, Res.getValueType(), Res, Y);
8775 // Look past (and (setcc_carry (cmp ...)), 1).
8776 if (Cond.getOpcode() == ISD::AND &&
8777 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
8778 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
8779 if (C && C->getAPIntValue() == 1)
8780 Cond = Cond.getOperand(0);
8783 // If condition flag is set by a X86ISD::CMP, then use it as the condition
8784 // setting operand in place of the X86ISD::SETCC.
8785 unsigned CondOpcode = Cond.getOpcode();
8786 if (CondOpcode == X86ISD::SETCC ||
8787 CondOpcode == X86ISD::SETCC_CARRY) {
8788 CC = Cond.getOperand(0);
8790 SDValue Cmp = Cond.getOperand(1);
8791 unsigned Opc = Cmp.getOpcode();
8792 EVT VT = Op.getValueType();
8794 bool IllegalFPCMov = false;
8795 if (VT.isFloatingPoint() && !VT.isVector() &&
8796 !isScalarFPTypeInSSEReg(VT)) // FPStack?
8797 IllegalFPCMov = !hasFPCMov(cast<ConstantSDNode>(CC)->getSExtValue());
8799 if ((isX86LogicalCmp(Cmp) && !IllegalFPCMov) ||
8800 Opc == X86ISD::BT) { // FIXME
8804 } else if (CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO ||
8805 CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO ||
8806 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) &&
8807 Cond.getOperand(0).getValueType() != MVT::i8)) {
8808 SDValue LHS = Cond.getOperand(0);
8809 SDValue RHS = Cond.getOperand(1);
8813 switch (CondOpcode) {
8814 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break;
8815 case ISD::SADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break;
8816 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break;
8817 case ISD::SSUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break;
8818 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break;
8819 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break;
8820 default: llvm_unreachable("unexpected overflowing operator");
8822 if (CondOpcode == ISD::UMULO)
8823 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(),
8826 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
8828 SDValue X86Op = DAG.getNode(X86Opcode, DL, VTs, LHS, RHS);
8830 if (CondOpcode == ISD::UMULO)
8831 Cond = X86Op.getValue(2);
8833 Cond = X86Op.getValue(1);
8835 CC = DAG.getConstant(X86Cond, MVT::i8);
8840 // Look pass the truncate if the high bits are known zero.
8841 if (isTruncWithZeroHighBitsInput(Cond, DAG))
8842 Cond = Cond.getOperand(0);
8844 // We know the result of AND is compared against zero. Try to match
8846 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
8847 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, DL, DAG);
8848 if (NewSetCC.getNode()) {
8849 CC = NewSetCC.getOperand(0);
8850 Cond = NewSetCC.getOperand(1);
8857 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
8858 Cond = EmitTest(Cond, X86::COND_NE, DAG);
8861 // a < b ? -1 : 0 -> RES = ~setcc_carry
8862 // a < b ? 0 : -1 -> RES = setcc_carry
8863 // a >= b ? -1 : 0 -> RES = setcc_carry
8864 // a >= b ? 0 : -1 -> RES = ~setcc_carry
8865 if (Cond.getOpcode() == X86ISD::SUB) {
8866 Cond = ConvertCmpIfNecessary(Cond, DAG);
8867 unsigned CondCode = cast<ConstantSDNode>(CC)->getZExtValue();
8869 if ((CondCode == X86::COND_AE || CondCode == X86::COND_B) &&
8870 (isAllOnes(Op1) || isAllOnes(Op2)) && (isZero(Op1) || isZero(Op2))) {
8871 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
8872 DAG.getConstant(X86::COND_B, MVT::i8), Cond);
8873 if (isAllOnes(Op1) != (CondCode == X86::COND_B))
8874 return DAG.getNOT(DL, Res, Res.getValueType());
8879 // X86ISD::CMOV means set the result (which is operand 1) to the RHS if
8880 // condition is true.
8881 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue);
8882 SDValue Ops[] = { Op2, Op1, CC, Cond };
8883 return DAG.getNode(X86ISD::CMOV, DL, VTs, Ops, array_lengthof(Ops));
8886 // isAndOrOfSingleUseSetCCs - Return true if node is an ISD::AND or
8887 // ISD::OR of two X86ISD::SETCC nodes each of which has no other use apart
8888 // from the AND / OR.
8889 static bool isAndOrOfSetCCs(SDValue Op, unsigned &Opc) {
8890 Opc = Op.getOpcode();
8891 if (Opc != ISD::OR && Opc != ISD::AND)
8893 return (Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
8894 Op.getOperand(0).hasOneUse() &&
8895 Op.getOperand(1).getOpcode() == X86ISD::SETCC &&
8896 Op.getOperand(1).hasOneUse());
8899 // isXor1OfSetCC - Return true if node is an ISD::XOR of a X86ISD::SETCC and
8900 // 1 and that the SETCC node has a single use.
8901 static bool isXor1OfSetCC(SDValue Op) {
8902 if (Op.getOpcode() != ISD::XOR)
8904 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
8905 if (N1C && N1C->getAPIntValue() == 1) {
8906 return Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
8907 Op.getOperand(0).hasOneUse();
8912 SDValue X86TargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) const {
8913 bool addTest = true;
8914 SDValue Chain = Op.getOperand(0);
8915 SDValue Cond = Op.getOperand(1);
8916 SDValue Dest = Op.getOperand(2);
8917 DebugLoc dl = Op.getDebugLoc();
8919 bool Inverted = false;
8921 if (Cond.getOpcode() == ISD::SETCC) {
8922 // Check for setcc([su]{add,sub,mul}o == 0).
8923 if (cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETEQ &&
8924 isa<ConstantSDNode>(Cond.getOperand(1)) &&
8925 cast<ConstantSDNode>(Cond.getOperand(1))->isNullValue() &&
8926 Cond.getOperand(0).getResNo() == 1 &&
8927 (Cond.getOperand(0).getOpcode() == ISD::SADDO ||
8928 Cond.getOperand(0).getOpcode() == ISD::UADDO ||
8929 Cond.getOperand(0).getOpcode() == ISD::SSUBO ||
8930 Cond.getOperand(0).getOpcode() == ISD::USUBO ||
8931 Cond.getOperand(0).getOpcode() == ISD::SMULO ||
8932 Cond.getOperand(0).getOpcode() == ISD::UMULO)) {
8934 Cond = Cond.getOperand(0);
8936 SDValue NewCond = LowerSETCC(Cond, DAG);
8937 if (NewCond.getNode())
8942 // FIXME: LowerXALUO doesn't handle these!!
8943 else if (Cond.getOpcode() == X86ISD::ADD ||
8944 Cond.getOpcode() == X86ISD::SUB ||
8945 Cond.getOpcode() == X86ISD::SMUL ||
8946 Cond.getOpcode() == X86ISD::UMUL)
8947 Cond = LowerXALUO(Cond, DAG);
8950 // Look pass (and (setcc_carry (cmp ...)), 1).
8951 if (Cond.getOpcode() == ISD::AND &&
8952 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
8953 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
8954 if (C && C->getAPIntValue() == 1)
8955 Cond = Cond.getOperand(0);
8958 // If condition flag is set by a X86ISD::CMP, then use it as the condition
8959 // setting operand in place of the X86ISD::SETCC.
8960 unsigned CondOpcode = Cond.getOpcode();
8961 if (CondOpcode == X86ISD::SETCC ||
8962 CondOpcode == X86ISD::SETCC_CARRY) {
8963 CC = Cond.getOperand(0);
8965 SDValue Cmp = Cond.getOperand(1);
8966 unsigned Opc = Cmp.getOpcode();
8967 // FIXME: WHY THE SPECIAL CASING OF LogicalCmp??
8968 if (isX86LogicalCmp(Cmp) || Opc == X86ISD::BT) {
8972 switch (cast<ConstantSDNode>(CC)->getZExtValue()) {
8976 // These can only come from an arithmetic instruction with overflow,
8977 // e.g. SADDO, UADDO.
8978 Cond = Cond.getNode()->getOperand(1);
8984 CondOpcode = Cond.getOpcode();
8985 if (CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO ||
8986 CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO ||
8987 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) &&
8988 Cond.getOperand(0).getValueType() != MVT::i8)) {
8989 SDValue LHS = Cond.getOperand(0);
8990 SDValue RHS = Cond.getOperand(1);
8994 switch (CondOpcode) {
8995 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break;
8996 case ISD::SADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break;
8997 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break;
8998 case ISD::SSUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break;
8999 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break;
9000 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break;
9001 default: llvm_unreachable("unexpected overflowing operator");
9004 X86Cond = X86::GetOppositeBranchCondition((X86::CondCode)X86Cond);
9005 if (CondOpcode == ISD::UMULO)
9006 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(),
9009 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
9011 SDValue X86Op = DAG.getNode(X86Opcode, dl, VTs, LHS, RHS);
9013 if (CondOpcode == ISD::UMULO)
9014 Cond = X86Op.getValue(2);
9016 Cond = X86Op.getValue(1);
9018 CC = DAG.getConstant(X86Cond, MVT::i8);
9022 if (Cond.hasOneUse() && isAndOrOfSetCCs(Cond, CondOpc)) {
9023 SDValue Cmp = Cond.getOperand(0).getOperand(1);
9024 if (CondOpc == ISD::OR) {
9025 // Also, recognize the pattern generated by an FCMP_UNE. We can emit
9026 // two branches instead of an explicit OR instruction with a
9028 if (Cmp == Cond.getOperand(1).getOperand(1) &&
9029 isX86LogicalCmp(Cmp)) {
9030 CC = Cond.getOperand(0).getOperand(0);
9031 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
9032 Chain, Dest, CC, Cmp);
9033 CC = Cond.getOperand(1).getOperand(0);
9037 } else { // ISD::AND
9038 // Also, recognize the pattern generated by an FCMP_OEQ. We can emit
9039 // two branches instead of an explicit AND instruction with a
9040 // separate test. However, we only do this if this block doesn't
9041 // have a fall-through edge, because this requires an explicit
9042 // jmp when the condition is false.
9043 if (Cmp == Cond.getOperand(1).getOperand(1) &&
9044 isX86LogicalCmp(Cmp) &&
9045 Op.getNode()->hasOneUse()) {
9046 X86::CondCode CCode =
9047 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
9048 CCode = X86::GetOppositeBranchCondition(CCode);
9049 CC = DAG.getConstant(CCode, MVT::i8);
9050 SDNode *User = *Op.getNode()->use_begin();
9051 // Look for an unconditional branch following this conditional branch.
9052 // We need this because we need to reverse the successors in order
9053 // to implement FCMP_OEQ.
9054 if (User->getOpcode() == ISD::BR) {
9055 SDValue FalseBB = User->getOperand(1);
9057 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
9058 assert(NewBR == User);
9062 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
9063 Chain, Dest, CC, Cmp);
9064 X86::CondCode CCode =
9065 (X86::CondCode)Cond.getOperand(1).getConstantOperandVal(0);
9066 CCode = X86::GetOppositeBranchCondition(CCode);
9067 CC = DAG.getConstant(CCode, MVT::i8);
9073 } else if (Cond.hasOneUse() && isXor1OfSetCC(Cond)) {
9074 // Recognize for xorb (setcc), 1 patterns. The xor inverts the condition.
9075 // It should be transformed during dag combiner except when the condition
9076 // is set by a arithmetics with overflow node.
9077 X86::CondCode CCode =
9078 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
9079 CCode = X86::GetOppositeBranchCondition(CCode);
9080 CC = DAG.getConstant(CCode, MVT::i8);
9081 Cond = Cond.getOperand(0).getOperand(1);
9083 } else if (Cond.getOpcode() == ISD::SETCC &&
9084 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETOEQ) {
9085 // For FCMP_OEQ, we can emit
9086 // two branches instead of an explicit AND instruction with a
9087 // separate test. However, we only do this if this block doesn't
9088 // have a fall-through edge, because this requires an explicit
9089 // jmp when the condition is false.
9090 if (Op.getNode()->hasOneUse()) {
9091 SDNode *User = *Op.getNode()->use_begin();
9092 // Look for an unconditional branch following this conditional branch.
9093 // We need this because we need to reverse the successors in order
9094 // to implement FCMP_OEQ.
9095 if (User->getOpcode() == ISD::BR) {
9096 SDValue FalseBB = User->getOperand(1);
9098 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
9099 assert(NewBR == User);
9103 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
9104 Cond.getOperand(0), Cond.getOperand(1));
9105 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
9106 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
9107 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
9108 Chain, Dest, CC, Cmp);
9109 CC = DAG.getConstant(X86::COND_P, MVT::i8);
9114 } else if (Cond.getOpcode() == ISD::SETCC &&
9115 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETUNE) {
9116 // For FCMP_UNE, we can emit
9117 // two branches instead of an explicit AND instruction with a
9118 // separate test. However, we only do this if this block doesn't
9119 // have a fall-through edge, because this requires an explicit
9120 // jmp when the condition is false.
9121 if (Op.getNode()->hasOneUse()) {
9122 SDNode *User = *Op.getNode()->use_begin();
9123 // Look for an unconditional branch following this conditional branch.
9124 // We need this because we need to reverse the successors in order
9125 // to implement FCMP_UNE.
9126 if (User->getOpcode() == ISD::BR) {
9127 SDValue FalseBB = User->getOperand(1);
9129 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
9130 assert(NewBR == User);
9133 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
9134 Cond.getOperand(0), Cond.getOperand(1));
9135 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
9136 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
9137 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
9138 Chain, Dest, CC, Cmp);
9139 CC = DAG.getConstant(X86::COND_NP, MVT::i8);
9149 // Look pass the truncate if the high bits are known zero.
9150 if (isTruncWithZeroHighBitsInput(Cond, DAG))
9151 Cond = Cond.getOperand(0);
9153 // We know the result of AND is compared against zero. Try to match
9155 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
9156 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, dl, DAG);
9157 if (NewSetCC.getNode()) {
9158 CC = NewSetCC.getOperand(0);
9159 Cond = NewSetCC.getOperand(1);
9166 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
9167 Cond = EmitTest(Cond, X86::COND_NE, DAG);
9169 Cond = ConvertCmpIfNecessary(Cond, DAG);
9170 return DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
9171 Chain, Dest, CC, Cond);
9175 // Lower dynamic stack allocation to _alloca call for Cygwin/Mingw targets.
9176 // Calls to _alloca is needed to probe the stack when allocating more than 4k
9177 // bytes in one go. Touching the stack at 4K increments is necessary to ensure
9178 // that the guard pages used by the OS virtual memory manager are allocated in
9179 // correct sequence.
9181 X86TargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
9182 SelectionDAG &DAG) const {
9183 assert((Subtarget->isTargetCygMing() || Subtarget->isTargetWindows() ||
9184 getTargetMachine().Options.EnableSegmentedStacks) &&
9185 "This should be used only on Windows targets or when segmented stacks "
9187 assert(!Subtarget->isTargetEnvMacho() && "Not implemented");
9188 DebugLoc dl = Op.getDebugLoc();
9191 SDValue Chain = Op.getOperand(0);
9192 SDValue Size = Op.getOperand(1);
9193 // FIXME: Ensure alignment here
9195 bool Is64Bit = Subtarget->is64Bit();
9196 EVT SPTy = Is64Bit ? MVT::i64 : MVT::i32;
9198 if (getTargetMachine().Options.EnableSegmentedStacks) {
9199 MachineFunction &MF = DAG.getMachineFunction();
9200 MachineRegisterInfo &MRI = MF.getRegInfo();
9203 // The 64 bit implementation of segmented stacks needs to clobber both r10
9204 // r11. This makes it impossible to use it along with nested parameters.
9205 const Function *F = MF.getFunction();
9207 for (Function::const_arg_iterator I = F->arg_begin(), E = F->arg_end();
9209 if (I->hasNestAttr())
9210 report_fatal_error("Cannot use segmented stacks with functions that "
9211 "have nested arguments.");
9214 const TargetRegisterClass *AddrRegClass =
9215 getRegClassFor(Subtarget->is64Bit() ? MVT::i64:MVT::i32);
9216 unsigned Vreg = MRI.createVirtualRegister(AddrRegClass);
9217 Chain = DAG.getCopyToReg(Chain, dl, Vreg, Size);
9218 SDValue Value = DAG.getNode(X86ISD::SEG_ALLOCA, dl, SPTy, Chain,
9219 DAG.getRegister(Vreg, SPTy));
9220 SDValue Ops1[2] = { Value, Chain };
9221 return DAG.getMergeValues(Ops1, 2, dl);
9224 unsigned Reg = (Subtarget->is64Bit() ? X86::RAX : X86::EAX);
9226 Chain = DAG.getCopyToReg(Chain, dl, Reg, Size, Flag);
9227 Flag = Chain.getValue(1);
9228 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
9230 Chain = DAG.getNode(X86ISD::WIN_ALLOCA, dl, NodeTys, Chain, Flag);
9231 Flag = Chain.getValue(1);
9233 Chain = DAG.getCopyFromReg(Chain, dl, X86StackPtr, SPTy).getValue(1);
9235 SDValue Ops1[2] = { Chain.getValue(0), Chain };
9236 return DAG.getMergeValues(Ops1, 2, dl);
9240 SDValue X86TargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const {
9241 MachineFunction &MF = DAG.getMachineFunction();
9242 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
9244 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
9245 DebugLoc DL = Op.getDebugLoc();
9247 if (!Subtarget->is64Bit() || Subtarget->isTargetWin64()) {
9248 // vastart just stores the address of the VarArgsFrameIndex slot into the
9249 // memory location argument.
9250 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
9252 return DAG.getStore(Op.getOperand(0), DL, FR, Op.getOperand(1),
9253 MachinePointerInfo(SV), false, false, 0);
9257 // gp_offset (0 - 6 * 8)
9258 // fp_offset (48 - 48 + 8 * 16)
9259 // overflow_arg_area (point to parameters coming in memory).
9261 SmallVector<SDValue, 8> MemOps;
9262 SDValue FIN = Op.getOperand(1);
9264 SDValue Store = DAG.getStore(Op.getOperand(0), DL,
9265 DAG.getConstant(FuncInfo->getVarArgsGPOffset(),
9267 FIN, MachinePointerInfo(SV), false, false, 0);
9268 MemOps.push_back(Store);
9271 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
9272 FIN, DAG.getIntPtrConstant(4));
9273 Store = DAG.getStore(Op.getOperand(0), DL,
9274 DAG.getConstant(FuncInfo->getVarArgsFPOffset(),
9276 FIN, MachinePointerInfo(SV, 4), false, false, 0);
9277 MemOps.push_back(Store);
9279 // Store ptr to overflow_arg_area
9280 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
9281 FIN, DAG.getIntPtrConstant(4));
9282 SDValue OVFIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
9284 Store = DAG.getStore(Op.getOperand(0), DL, OVFIN, FIN,
9285 MachinePointerInfo(SV, 8),
9287 MemOps.push_back(Store);
9289 // Store ptr to reg_save_area.
9290 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
9291 FIN, DAG.getIntPtrConstant(8));
9292 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
9294 Store = DAG.getStore(Op.getOperand(0), DL, RSFIN, FIN,
9295 MachinePointerInfo(SV, 16), false, false, 0);
9296 MemOps.push_back(Store);
9297 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
9298 &MemOps[0], MemOps.size());
9301 SDValue X86TargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG) const {
9302 assert(Subtarget->is64Bit() &&
9303 "LowerVAARG only handles 64-bit va_arg!");
9304 assert((Subtarget->isTargetLinux() ||
9305 Subtarget->isTargetDarwin()) &&
9306 "Unhandled target in LowerVAARG");
9307 assert(Op.getNode()->getNumOperands() == 4);
9308 SDValue Chain = Op.getOperand(0);
9309 SDValue SrcPtr = Op.getOperand(1);
9310 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
9311 unsigned Align = Op.getConstantOperandVal(3);
9312 DebugLoc dl = Op.getDebugLoc();
9314 EVT ArgVT = Op.getNode()->getValueType(0);
9315 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
9316 uint32_t ArgSize = getTargetData()->getTypeAllocSize(ArgTy);
9319 // Decide which area this value should be read from.
9320 // TODO: Implement the AMD64 ABI in its entirety. This simple
9321 // selection mechanism works only for the basic types.
9322 if (ArgVT == MVT::f80) {
9323 llvm_unreachable("va_arg for f80 not yet implemented");
9324 } else if (ArgVT.isFloatingPoint() && ArgSize <= 16 /*bytes*/) {
9325 ArgMode = 2; // Argument passed in XMM register. Use fp_offset.
9326 } else if (ArgVT.isInteger() && ArgSize <= 32 /*bytes*/) {
9327 ArgMode = 1; // Argument passed in GPR64 register(s). Use gp_offset.
9329 llvm_unreachable("Unhandled argument type in LowerVAARG");
9333 // Sanity Check: Make sure using fp_offset makes sense.
9334 assert(!getTargetMachine().Options.UseSoftFloat &&
9335 !(DAG.getMachineFunction()
9336 .getFunction()->hasFnAttr(Attribute::NoImplicitFloat)) &&
9337 Subtarget->hasSSE1());
9340 // Insert VAARG_64 node into the DAG
9341 // VAARG_64 returns two values: Variable Argument Address, Chain
9342 SmallVector<SDValue, 11> InstOps;
9343 InstOps.push_back(Chain);
9344 InstOps.push_back(SrcPtr);
9345 InstOps.push_back(DAG.getConstant(ArgSize, MVT::i32));
9346 InstOps.push_back(DAG.getConstant(ArgMode, MVT::i8));
9347 InstOps.push_back(DAG.getConstant(Align, MVT::i32));
9348 SDVTList VTs = DAG.getVTList(getPointerTy(), MVT::Other);
9349 SDValue VAARG = DAG.getMemIntrinsicNode(X86ISD::VAARG_64, dl,
9350 VTs, &InstOps[0], InstOps.size(),
9352 MachinePointerInfo(SV),
9357 Chain = VAARG.getValue(1);
9359 // Load the next argument and return it
9360 return DAG.getLoad(ArgVT, dl,
9363 MachinePointerInfo(),
9364 false, false, false, 0);
9367 SDValue X86TargetLowering::LowerVACOPY(SDValue Op, SelectionDAG &DAG) const {
9368 // X86-64 va_list is a struct { i32, i32, i8*, i8* }.
9369 assert(Subtarget->is64Bit() && "This code only handles 64-bit va_copy!");
9370 SDValue Chain = Op.getOperand(0);
9371 SDValue DstPtr = Op.getOperand(1);
9372 SDValue SrcPtr = Op.getOperand(2);
9373 const Value *DstSV = cast<SrcValueSDNode>(Op.getOperand(3))->getValue();
9374 const Value *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
9375 DebugLoc DL = Op.getDebugLoc();
9377 return DAG.getMemcpy(Chain, DL, DstPtr, SrcPtr,
9378 DAG.getIntPtrConstant(24), 8, /*isVolatile*/false,
9380 MachinePointerInfo(DstSV), MachinePointerInfo(SrcSV));
9383 // getTargetVShiftNOde - Handle vector element shifts where the shift amount
9384 // may or may not be a constant. Takes immediate version of shift as input.
9385 static SDValue getTargetVShiftNode(unsigned Opc, DebugLoc dl, EVT VT,
9386 SDValue SrcOp, SDValue ShAmt,
9387 SelectionDAG &DAG) {
9388 assert(ShAmt.getValueType() == MVT::i32 && "ShAmt is not i32");
9390 if (isa<ConstantSDNode>(ShAmt)) {
9391 // Constant may be a TargetConstant. Use a regular constant.
9392 uint32_t ShiftAmt = cast<ConstantSDNode>(ShAmt)->getZExtValue();
9394 default: llvm_unreachable("Unknown target vector shift node");
9398 return DAG.getNode(Opc, dl, VT, SrcOp,
9399 DAG.getConstant(ShiftAmt, MVT::i32));
9403 // Change opcode to non-immediate version
9405 default: llvm_unreachable("Unknown target vector shift node");
9406 case X86ISD::VSHLI: Opc = X86ISD::VSHL; break;
9407 case X86ISD::VSRLI: Opc = X86ISD::VSRL; break;
9408 case X86ISD::VSRAI: Opc = X86ISD::VSRA; break;
9411 // Need to build a vector containing shift amount
9412 // Shift amount is 32-bits, but SSE instructions read 64-bit, so fill with 0
9415 ShOps[1] = DAG.getConstant(0, MVT::i32);
9416 ShOps[2] = DAG.getUNDEF(MVT::i32);
9417 ShOps[3] = DAG.getUNDEF(MVT::i32);
9418 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, &ShOps[0], 4);
9420 // The return type has to be a 128-bit type with the same element
9421 // type as the input type.
9422 MVT EltVT = VT.getVectorElementType().getSimpleVT();
9423 EVT ShVT = MVT::getVectorVT(EltVT, 128/EltVT.getSizeInBits());
9425 ShAmt = DAG.getNode(ISD::BITCAST, dl, ShVT, ShAmt);
9426 return DAG.getNode(Opc, dl, VT, SrcOp, ShAmt);
9430 X86TargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const {
9431 DebugLoc dl = Op.getDebugLoc();
9432 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
9434 default: return SDValue(); // Don't custom lower most intrinsics.
9435 // Comparison intrinsics.
9436 case Intrinsic::x86_sse_comieq_ss:
9437 case Intrinsic::x86_sse_comilt_ss:
9438 case Intrinsic::x86_sse_comile_ss:
9439 case Intrinsic::x86_sse_comigt_ss:
9440 case Intrinsic::x86_sse_comige_ss:
9441 case Intrinsic::x86_sse_comineq_ss:
9442 case Intrinsic::x86_sse_ucomieq_ss:
9443 case Intrinsic::x86_sse_ucomilt_ss:
9444 case Intrinsic::x86_sse_ucomile_ss:
9445 case Intrinsic::x86_sse_ucomigt_ss:
9446 case Intrinsic::x86_sse_ucomige_ss:
9447 case Intrinsic::x86_sse_ucomineq_ss:
9448 case Intrinsic::x86_sse2_comieq_sd:
9449 case Intrinsic::x86_sse2_comilt_sd:
9450 case Intrinsic::x86_sse2_comile_sd:
9451 case Intrinsic::x86_sse2_comigt_sd:
9452 case Intrinsic::x86_sse2_comige_sd:
9453 case Intrinsic::x86_sse2_comineq_sd:
9454 case Intrinsic::x86_sse2_ucomieq_sd:
9455 case Intrinsic::x86_sse2_ucomilt_sd:
9456 case Intrinsic::x86_sse2_ucomile_sd:
9457 case Intrinsic::x86_sse2_ucomigt_sd:
9458 case Intrinsic::x86_sse2_ucomige_sd:
9459 case Intrinsic::x86_sse2_ucomineq_sd: {
9461 ISD::CondCode CC = ISD::SETCC_INVALID;
9463 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
9464 case Intrinsic::x86_sse_comieq_ss:
9465 case Intrinsic::x86_sse2_comieq_sd:
9469 case Intrinsic::x86_sse_comilt_ss:
9470 case Intrinsic::x86_sse2_comilt_sd:
9474 case Intrinsic::x86_sse_comile_ss:
9475 case Intrinsic::x86_sse2_comile_sd:
9479 case Intrinsic::x86_sse_comigt_ss:
9480 case Intrinsic::x86_sse2_comigt_sd:
9484 case Intrinsic::x86_sse_comige_ss:
9485 case Intrinsic::x86_sse2_comige_sd:
9489 case Intrinsic::x86_sse_comineq_ss:
9490 case Intrinsic::x86_sse2_comineq_sd:
9494 case Intrinsic::x86_sse_ucomieq_ss:
9495 case Intrinsic::x86_sse2_ucomieq_sd:
9496 Opc = X86ISD::UCOMI;
9499 case Intrinsic::x86_sse_ucomilt_ss:
9500 case Intrinsic::x86_sse2_ucomilt_sd:
9501 Opc = X86ISD::UCOMI;
9504 case Intrinsic::x86_sse_ucomile_ss:
9505 case Intrinsic::x86_sse2_ucomile_sd:
9506 Opc = X86ISD::UCOMI;
9509 case Intrinsic::x86_sse_ucomigt_ss:
9510 case Intrinsic::x86_sse2_ucomigt_sd:
9511 Opc = X86ISD::UCOMI;
9514 case Intrinsic::x86_sse_ucomige_ss:
9515 case Intrinsic::x86_sse2_ucomige_sd:
9516 Opc = X86ISD::UCOMI;
9519 case Intrinsic::x86_sse_ucomineq_ss:
9520 case Intrinsic::x86_sse2_ucomineq_sd:
9521 Opc = X86ISD::UCOMI;
9526 SDValue LHS = Op.getOperand(1);
9527 SDValue RHS = Op.getOperand(2);
9528 unsigned X86CC = TranslateX86CC(CC, true, LHS, RHS, DAG);
9529 assert(X86CC != X86::COND_INVALID && "Unexpected illegal condition!");
9530 SDValue Cond = DAG.getNode(Opc, dl, MVT::i32, LHS, RHS);
9531 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
9532 DAG.getConstant(X86CC, MVT::i8), Cond);
9533 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
9535 // Arithmetic intrinsics.
9536 case Intrinsic::x86_sse2_pmulu_dq:
9537 case Intrinsic::x86_avx2_pmulu_dq:
9538 return DAG.getNode(X86ISD::PMULUDQ, dl, Op.getValueType(),
9539 Op.getOperand(1), Op.getOperand(2));
9540 case Intrinsic::x86_sse3_hadd_ps:
9541 case Intrinsic::x86_sse3_hadd_pd:
9542 case Intrinsic::x86_avx_hadd_ps_256:
9543 case Intrinsic::x86_avx_hadd_pd_256:
9544 return DAG.getNode(X86ISD::FHADD, dl, Op.getValueType(),
9545 Op.getOperand(1), Op.getOperand(2));
9546 case Intrinsic::x86_sse3_hsub_ps:
9547 case Intrinsic::x86_sse3_hsub_pd:
9548 case Intrinsic::x86_avx_hsub_ps_256:
9549 case Intrinsic::x86_avx_hsub_pd_256:
9550 return DAG.getNode(X86ISD::FHSUB, dl, Op.getValueType(),
9551 Op.getOperand(1), Op.getOperand(2));
9552 case Intrinsic::x86_ssse3_phadd_w_128:
9553 case Intrinsic::x86_ssse3_phadd_d_128:
9554 case Intrinsic::x86_avx2_phadd_w:
9555 case Intrinsic::x86_avx2_phadd_d:
9556 return DAG.getNode(X86ISD::HADD, dl, Op.getValueType(),
9557 Op.getOperand(1), Op.getOperand(2));
9558 case Intrinsic::x86_ssse3_phsub_w_128:
9559 case Intrinsic::x86_ssse3_phsub_d_128:
9560 case Intrinsic::x86_avx2_phsub_w:
9561 case Intrinsic::x86_avx2_phsub_d:
9562 return DAG.getNode(X86ISD::HSUB, dl, Op.getValueType(),
9563 Op.getOperand(1), Op.getOperand(2));
9564 case Intrinsic::x86_avx2_psllv_d:
9565 case Intrinsic::x86_avx2_psllv_q:
9566 case Intrinsic::x86_avx2_psllv_d_256:
9567 case Intrinsic::x86_avx2_psllv_q_256:
9568 return DAG.getNode(ISD::SHL, dl, Op.getValueType(),
9569 Op.getOperand(1), Op.getOperand(2));
9570 case Intrinsic::x86_avx2_psrlv_d:
9571 case Intrinsic::x86_avx2_psrlv_q:
9572 case Intrinsic::x86_avx2_psrlv_d_256:
9573 case Intrinsic::x86_avx2_psrlv_q_256:
9574 return DAG.getNode(ISD::SRL, dl, Op.getValueType(),
9575 Op.getOperand(1), Op.getOperand(2));
9576 case Intrinsic::x86_avx2_psrav_d:
9577 case Intrinsic::x86_avx2_psrav_d_256:
9578 return DAG.getNode(ISD::SRA, dl, Op.getValueType(),
9579 Op.getOperand(1), Op.getOperand(2));
9580 case Intrinsic::x86_ssse3_pshuf_b_128:
9581 case Intrinsic::x86_avx2_pshuf_b:
9582 return DAG.getNode(X86ISD::PSHUFB, dl, Op.getValueType(),
9583 Op.getOperand(1), Op.getOperand(2));
9584 case Intrinsic::x86_ssse3_psign_b_128:
9585 case Intrinsic::x86_ssse3_psign_w_128:
9586 case Intrinsic::x86_ssse3_psign_d_128:
9587 case Intrinsic::x86_avx2_psign_b:
9588 case Intrinsic::x86_avx2_psign_w:
9589 case Intrinsic::x86_avx2_psign_d:
9590 return DAG.getNode(X86ISD::PSIGN, dl, Op.getValueType(),
9591 Op.getOperand(1), Op.getOperand(2));
9592 case Intrinsic::x86_sse41_insertps:
9593 return DAG.getNode(X86ISD::INSERTPS, dl, Op.getValueType(),
9594 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
9595 case Intrinsic::x86_avx_vperm2f128_ps_256:
9596 case Intrinsic::x86_avx_vperm2f128_pd_256:
9597 case Intrinsic::x86_avx_vperm2f128_si_256:
9598 case Intrinsic::x86_avx2_vperm2i128:
9599 return DAG.getNode(X86ISD::VPERM2X128, dl, Op.getValueType(),
9600 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
9601 case Intrinsic::x86_avx2_permd:
9602 case Intrinsic::x86_avx2_permps:
9603 // Operands intentionally swapped. Mask is last operand to intrinsic,
9604 // but second operand for node/intruction.
9605 return DAG.getNode(X86ISD::VPERMV, dl, Op.getValueType(),
9606 Op.getOperand(2), Op.getOperand(1));
9608 // ptest and testp intrinsics. The intrinsic these come from are designed to
9609 // return an integer value, not just an instruction so lower it to the ptest
9610 // or testp pattern and a setcc for the result.
9611 case Intrinsic::x86_sse41_ptestz:
9612 case Intrinsic::x86_sse41_ptestc:
9613 case Intrinsic::x86_sse41_ptestnzc:
9614 case Intrinsic::x86_avx_ptestz_256:
9615 case Intrinsic::x86_avx_ptestc_256:
9616 case Intrinsic::x86_avx_ptestnzc_256:
9617 case Intrinsic::x86_avx_vtestz_ps:
9618 case Intrinsic::x86_avx_vtestc_ps:
9619 case Intrinsic::x86_avx_vtestnzc_ps:
9620 case Intrinsic::x86_avx_vtestz_pd:
9621 case Intrinsic::x86_avx_vtestc_pd:
9622 case Intrinsic::x86_avx_vtestnzc_pd:
9623 case Intrinsic::x86_avx_vtestz_ps_256:
9624 case Intrinsic::x86_avx_vtestc_ps_256:
9625 case Intrinsic::x86_avx_vtestnzc_ps_256:
9626 case Intrinsic::x86_avx_vtestz_pd_256:
9627 case Intrinsic::x86_avx_vtestc_pd_256:
9628 case Intrinsic::x86_avx_vtestnzc_pd_256: {
9629 bool IsTestPacked = false;
9632 default: llvm_unreachable("Bad fallthrough in Intrinsic lowering.");
9633 case Intrinsic::x86_avx_vtestz_ps:
9634 case Intrinsic::x86_avx_vtestz_pd:
9635 case Intrinsic::x86_avx_vtestz_ps_256:
9636 case Intrinsic::x86_avx_vtestz_pd_256:
9637 IsTestPacked = true; // Fallthrough
9638 case Intrinsic::x86_sse41_ptestz:
9639 case Intrinsic::x86_avx_ptestz_256:
9641 X86CC = X86::COND_E;
9643 case Intrinsic::x86_avx_vtestc_ps:
9644 case Intrinsic::x86_avx_vtestc_pd:
9645 case Intrinsic::x86_avx_vtestc_ps_256:
9646 case Intrinsic::x86_avx_vtestc_pd_256:
9647 IsTestPacked = true; // Fallthrough
9648 case Intrinsic::x86_sse41_ptestc:
9649 case Intrinsic::x86_avx_ptestc_256:
9651 X86CC = X86::COND_B;
9653 case Intrinsic::x86_avx_vtestnzc_ps:
9654 case Intrinsic::x86_avx_vtestnzc_pd:
9655 case Intrinsic::x86_avx_vtestnzc_ps_256:
9656 case Intrinsic::x86_avx_vtestnzc_pd_256:
9657 IsTestPacked = true; // Fallthrough
9658 case Intrinsic::x86_sse41_ptestnzc:
9659 case Intrinsic::x86_avx_ptestnzc_256:
9661 X86CC = X86::COND_A;
9665 SDValue LHS = Op.getOperand(1);
9666 SDValue RHS = Op.getOperand(2);
9667 unsigned TestOpc = IsTestPacked ? X86ISD::TESTP : X86ISD::PTEST;
9668 SDValue Test = DAG.getNode(TestOpc, dl, MVT::i32, LHS, RHS);
9669 SDValue CC = DAG.getConstant(X86CC, MVT::i8);
9670 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8, CC, Test);
9671 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
9674 // SSE/AVX shift intrinsics
9675 case Intrinsic::x86_sse2_psll_w:
9676 case Intrinsic::x86_sse2_psll_d:
9677 case Intrinsic::x86_sse2_psll_q:
9678 case Intrinsic::x86_avx2_psll_w:
9679 case Intrinsic::x86_avx2_psll_d:
9680 case Intrinsic::x86_avx2_psll_q:
9681 return DAG.getNode(X86ISD::VSHL, dl, Op.getValueType(),
9682 Op.getOperand(1), Op.getOperand(2));
9683 case Intrinsic::x86_sse2_psrl_w:
9684 case Intrinsic::x86_sse2_psrl_d:
9685 case Intrinsic::x86_sse2_psrl_q:
9686 case Intrinsic::x86_avx2_psrl_w:
9687 case Intrinsic::x86_avx2_psrl_d:
9688 case Intrinsic::x86_avx2_psrl_q:
9689 return DAG.getNode(X86ISD::VSRL, dl, Op.getValueType(),
9690 Op.getOperand(1), Op.getOperand(2));
9691 case Intrinsic::x86_sse2_psra_w:
9692 case Intrinsic::x86_sse2_psra_d:
9693 case Intrinsic::x86_avx2_psra_w:
9694 case Intrinsic::x86_avx2_psra_d:
9695 return DAG.getNode(X86ISD::VSRA, dl, Op.getValueType(),
9696 Op.getOperand(1), Op.getOperand(2));
9697 case Intrinsic::x86_sse2_pslli_w:
9698 case Intrinsic::x86_sse2_pslli_d:
9699 case Intrinsic::x86_sse2_pslli_q:
9700 case Intrinsic::x86_avx2_pslli_w:
9701 case Intrinsic::x86_avx2_pslli_d:
9702 case Intrinsic::x86_avx2_pslli_q:
9703 return getTargetVShiftNode(X86ISD::VSHLI, dl, Op.getValueType(),
9704 Op.getOperand(1), Op.getOperand(2), DAG);
9705 case Intrinsic::x86_sse2_psrli_w:
9706 case Intrinsic::x86_sse2_psrli_d:
9707 case Intrinsic::x86_sse2_psrli_q:
9708 case Intrinsic::x86_avx2_psrli_w:
9709 case Intrinsic::x86_avx2_psrli_d:
9710 case Intrinsic::x86_avx2_psrli_q:
9711 return getTargetVShiftNode(X86ISD::VSRLI, dl, Op.getValueType(),
9712 Op.getOperand(1), Op.getOperand(2), DAG);
9713 case Intrinsic::x86_sse2_psrai_w:
9714 case Intrinsic::x86_sse2_psrai_d:
9715 case Intrinsic::x86_avx2_psrai_w:
9716 case Intrinsic::x86_avx2_psrai_d:
9717 return getTargetVShiftNode(X86ISD::VSRAI, dl, Op.getValueType(),
9718 Op.getOperand(1), Op.getOperand(2), DAG);
9719 // Fix vector shift instructions where the last operand is a non-immediate
9721 case Intrinsic::x86_mmx_pslli_w:
9722 case Intrinsic::x86_mmx_pslli_d:
9723 case Intrinsic::x86_mmx_pslli_q:
9724 case Intrinsic::x86_mmx_psrli_w:
9725 case Intrinsic::x86_mmx_psrli_d:
9726 case Intrinsic::x86_mmx_psrli_q:
9727 case Intrinsic::x86_mmx_psrai_w:
9728 case Intrinsic::x86_mmx_psrai_d: {
9729 SDValue ShAmt = Op.getOperand(2);
9730 if (isa<ConstantSDNode>(ShAmt))
9733 unsigned NewIntNo = 0;
9735 case Intrinsic::x86_mmx_pslli_w:
9736 NewIntNo = Intrinsic::x86_mmx_psll_w;
9738 case Intrinsic::x86_mmx_pslli_d:
9739 NewIntNo = Intrinsic::x86_mmx_psll_d;
9741 case Intrinsic::x86_mmx_pslli_q:
9742 NewIntNo = Intrinsic::x86_mmx_psll_q;
9744 case Intrinsic::x86_mmx_psrli_w:
9745 NewIntNo = Intrinsic::x86_mmx_psrl_w;
9747 case Intrinsic::x86_mmx_psrli_d:
9748 NewIntNo = Intrinsic::x86_mmx_psrl_d;
9750 case Intrinsic::x86_mmx_psrli_q:
9751 NewIntNo = Intrinsic::x86_mmx_psrl_q;
9753 case Intrinsic::x86_mmx_psrai_w:
9754 NewIntNo = Intrinsic::x86_mmx_psra_w;
9756 case Intrinsic::x86_mmx_psrai_d:
9757 NewIntNo = Intrinsic::x86_mmx_psra_d;
9759 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
9762 // The vector shift intrinsics with scalars uses 32b shift amounts but
9763 // the sse2/mmx shift instructions reads 64 bits. Set the upper 32 bits
9765 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2i32, ShAmt,
9766 DAG.getConstant(0, MVT::i32));
9767 // FIXME this must be lowered to get rid of the invalid type.
9769 EVT VT = Op.getValueType();
9770 ShAmt = DAG.getNode(ISD::BITCAST, dl, VT, ShAmt);
9771 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
9772 DAG.getConstant(NewIntNo, MVT::i32),
9773 Op.getOperand(1), ShAmt);
9775 case Intrinsic::x86_sse42_pcmpistria128:
9776 case Intrinsic::x86_sse42_pcmpestria128:
9777 case Intrinsic::x86_sse42_pcmpistric128:
9778 case Intrinsic::x86_sse42_pcmpestric128:
9779 case Intrinsic::x86_sse42_pcmpistrio128:
9780 case Intrinsic::x86_sse42_pcmpestrio128:
9781 case Intrinsic::x86_sse42_pcmpistris128:
9782 case Intrinsic::x86_sse42_pcmpestris128:
9783 case Intrinsic::x86_sse42_pcmpistriz128:
9784 case Intrinsic::x86_sse42_pcmpestriz128: {
9788 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
9789 case Intrinsic::x86_sse42_pcmpistria128:
9790 Opcode = X86ISD::PCMPISTRI;
9791 X86CC = X86::COND_A;
9793 case Intrinsic::x86_sse42_pcmpestria128:
9794 Opcode = X86ISD::PCMPESTRI;
9795 X86CC = X86::COND_A;
9797 case Intrinsic::x86_sse42_pcmpistric128:
9798 Opcode = X86ISD::PCMPISTRI;
9799 X86CC = X86::COND_B;
9801 case Intrinsic::x86_sse42_pcmpestric128:
9802 Opcode = X86ISD::PCMPESTRI;
9803 X86CC = X86::COND_B;
9805 case Intrinsic::x86_sse42_pcmpistrio128:
9806 Opcode = X86ISD::PCMPISTRI;
9807 X86CC = X86::COND_O;
9809 case Intrinsic::x86_sse42_pcmpestrio128:
9810 Opcode = X86ISD::PCMPESTRI;
9811 X86CC = X86::COND_O;
9813 case Intrinsic::x86_sse42_pcmpistris128:
9814 Opcode = X86ISD::PCMPISTRI;
9815 X86CC = X86::COND_S;
9817 case Intrinsic::x86_sse42_pcmpestris128:
9818 Opcode = X86ISD::PCMPESTRI;
9819 X86CC = X86::COND_S;
9821 case Intrinsic::x86_sse42_pcmpistriz128:
9822 Opcode = X86ISD::PCMPISTRI;
9823 X86CC = X86::COND_E;
9825 case Intrinsic::x86_sse42_pcmpestriz128:
9826 Opcode = X86ISD::PCMPESTRI;
9827 X86CC = X86::COND_E;
9830 SmallVector<SDValue, 5> NewOps;
9831 NewOps.append(Op->op_begin()+1, Op->op_end());
9832 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
9833 SDValue PCMP = DAG.getNode(Opcode, dl, VTs, NewOps.data(), NewOps.size());
9834 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
9835 DAG.getConstant(X86CC, MVT::i8),
9836 SDValue(PCMP.getNode(), 1));
9837 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
9839 case Intrinsic::x86_sse42_pcmpistri128:
9840 case Intrinsic::x86_sse42_pcmpestri128: {
9842 if (IntNo == Intrinsic::x86_sse42_pcmpistri128)
9843 Opcode = X86ISD::PCMPISTRI;
9845 Opcode = X86ISD::PCMPESTRI;
9847 SmallVector<SDValue, 5> NewOps;
9848 NewOps.append(Op->op_begin()+1, Op->op_end());
9849 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
9850 return DAG.getNode(Opcode, dl, VTs, NewOps.data(), NewOps.size());
9856 X86TargetLowering::LowerINTRINSIC_W_CHAIN(SDValue Op, SelectionDAG &DAG) const {
9857 DebugLoc dl = Op.getDebugLoc();
9858 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
9860 default: return SDValue(); // Don't custom lower most intrinsics.
9862 // RDRAND intrinsics.
9863 case Intrinsic::x86_rdrand_16:
9864 case Intrinsic::x86_rdrand_32:
9865 case Intrinsic::x86_rdrand_64: {
9866 // Emit the node with the right value type.
9867 SDVTList VTs = DAG.getVTList(Op->getValueType(0), MVT::Glue, MVT::Other);
9868 SDValue Result = DAG.getNode(X86ISD::RDRAND, dl, VTs, Op.getOperand(0));
9870 // If the value returned by RDRAND was valid (CF=1), return 1. Otherwise
9871 // return the value from Rand, which is always 0, casted to i32.
9872 SDValue Ops[] = { DAG.getZExtOrTrunc(Result, dl, Op->getValueType(1)),
9873 DAG.getConstant(1, Op->getValueType(1)),
9874 DAG.getConstant(X86::COND_B, MVT::i32),
9875 SDValue(Result.getNode(), 1) };
9876 SDValue isValid = DAG.getNode(X86ISD::CMOV, dl,
9877 DAG.getVTList(Op->getValueType(1), MVT::Glue),
9880 // Return { result, isValid, chain }.
9881 return DAG.getNode(ISD::MERGE_VALUES, dl, Op->getVTList(), Result, isValid,
9882 SDValue(Result.getNode(), 2));
9887 SDValue X86TargetLowering::LowerRETURNADDR(SDValue Op,
9888 SelectionDAG &DAG) const {
9889 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
9890 MFI->setReturnAddressIsTaken(true);
9892 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
9893 DebugLoc dl = Op.getDebugLoc();
9896 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
9898 DAG.getConstant(TD->getPointerSize(),
9899 Subtarget->is64Bit() ? MVT::i64 : MVT::i32);
9900 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(),
9901 DAG.getNode(ISD::ADD, dl, getPointerTy(),
9903 MachinePointerInfo(), false, false, false, 0);
9906 // Just load the return address.
9907 SDValue RetAddrFI = getReturnAddressFrameIndex(DAG);
9908 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(),
9909 RetAddrFI, MachinePointerInfo(), false, false, false, 0);
9912 SDValue X86TargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {
9913 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
9914 MFI->setFrameAddressIsTaken(true);
9916 EVT VT = Op.getValueType();
9917 DebugLoc dl = Op.getDebugLoc(); // FIXME probably not meaningful
9918 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
9919 unsigned FrameReg = Subtarget->is64Bit() ? X86::RBP : X86::EBP;
9920 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT);
9922 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr,
9923 MachinePointerInfo(),
9924 false, false, false, 0);
9928 SDValue X86TargetLowering::LowerFRAME_TO_ARGS_OFFSET(SDValue Op,
9929 SelectionDAG &DAG) const {
9930 return DAG.getIntPtrConstant(2*TD->getPointerSize());
9933 SDValue X86TargetLowering::LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const {
9934 SDValue Chain = Op.getOperand(0);
9935 SDValue Offset = Op.getOperand(1);
9936 SDValue Handler = Op.getOperand(2);
9937 DebugLoc dl = Op.getDebugLoc();
9939 SDValue Frame = DAG.getCopyFromReg(DAG.getEntryNode(), dl,
9940 Subtarget->is64Bit() ? X86::RBP : X86::EBP,
9942 unsigned StoreAddrReg = (Subtarget->is64Bit() ? X86::RCX : X86::ECX);
9944 SDValue StoreAddr = DAG.getNode(ISD::ADD, dl, getPointerTy(), Frame,
9945 DAG.getIntPtrConstant(TD->getPointerSize()));
9946 StoreAddr = DAG.getNode(ISD::ADD, dl, getPointerTy(), StoreAddr, Offset);
9947 Chain = DAG.getStore(Chain, dl, Handler, StoreAddr, MachinePointerInfo(),
9949 Chain = DAG.getCopyToReg(Chain, dl, StoreAddrReg, StoreAddr);
9951 return DAG.getNode(X86ISD::EH_RETURN, dl,
9953 Chain, DAG.getRegister(StoreAddrReg, getPointerTy()));
9956 SDValue X86TargetLowering::LowerADJUST_TRAMPOLINE(SDValue Op,
9957 SelectionDAG &DAG) const {
9958 return Op.getOperand(0);
9961 SDValue X86TargetLowering::LowerINIT_TRAMPOLINE(SDValue Op,
9962 SelectionDAG &DAG) const {
9963 SDValue Root = Op.getOperand(0);
9964 SDValue Trmp = Op.getOperand(1); // trampoline
9965 SDValue FPtr = Op.getOperand(2); // nested function
9966 SDValue Nest = Op.getOperand(3); // 'nest' parameter value
9967 DebugLoc dl = Op.getDebugLoc();
9969 const Value *TrmpAddr = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
9971 if (Subtarget->is64Bit()) {
9972 SDValue OutChains[6];
9974 // Large code-model.
9975 const unsigned char JMP64r = 0xFF; // 64-bit jmp through register opcode.
9976 const unsigned char MOV64ri = 0xB8; // X86::MOV64ri opcode.
9978 const unsigned char N86R10 = X86_MC::getX86RegNum(X86::R10);
9979 const unsigned char N86R11 = X86_MC::getX86RegNum(X86::R11);
9981 const unsigned char REX_WB = 0x40 | 0x08 | 0x01; // REX prefix
9983 // Load the pointer to the nested function into R11.
9984 unsigned OpCode = ((MOV64ri | N86R11) << 8) | REX_WB; // movabsq r11
9985 SDValue Addr = Trmp;
9986 OutChains[0] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
9987 Addr, MachinePointerInfo(TrmpAddr),
9990 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
9991 DAG.getConstant(2, MVT::i64));
9992 OutChains[1] = DAG.getStore(Root, dl, FPtr, Addr,
9993 MachinePointerInfo(TrmpAddr, 2),
9996 // Load the 'nest' parameter value into R10.
9997 // R10 is specified in X86CallingConv.td
9998 OpCode = ((MOV64ri | N86R10) << 8) | REX_WB; // movabsq r10
9999 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
10000 DAG.getConstant(10, MVT::i64));
10001 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
10002 Addr, MachinePointerInfo(TrmpAddr, 10),
10005 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
10006 DAG.getConstant(12, MVT::i64));
10007 OutChains[3] = DAG.getStore(Root, dl, Nest, Addr,
10008 MachinePointerInfo(TrmpAddr, 12),
10011 // Jump to the nested function.
10012 OpCode = (JMP64r << 8) | REX_WB; // jmpq *...
10013 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
10014 DAG.getConstant(20, MVT::i64));
10015 OutChains[4] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
10016 Addr, MachinePointerInfo(TrmpAddr, 20),
10019 unsigned char ModRM = N86R11 | (4 << 3) | (3 << 6); // ...r11
10020 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
10021 DAG.getConstant(22, MVT::i64));
10022 OutChains[5] = DAG.getStore(Root, dl, DAG.getConstant(ModRM, MVT::i8), Addr,
10023 MachinePointerInfo(TrmpAddr, 22),
10026 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains, 6);
10028 const Function *Func =
10029 cast<Function>(cast<SrcValueSDNode>(Op.getOperand(5))->getValue());
10030 CallingConv::ID CC = Func->getCallingConv();
10035 llvm_unreachable("Unsupported calling convention");
10036 case CallingConv::C:
10037 case CallingConv::X86_StdCall: {
10038 // Pass 'nest' parameter in ECX.
10039 // Must be kept in sync with X86CallingConv.td
10040 NestReg = X86::ECX;
10042 // Check that ECX wasn't needed by an 'inreg' parameter.
10043 FunctionType *FTy = Func->getFunctionType();
10044 const AttrListPtr &Attrs = Func->getAttributes();
10046 if (!Attrs.isEmpty() && !Func->isVarArg()) {
10047 unsigned InRegCount = 0;
10050 for (FunctionType::param_iterator I = FTy->param_begin(),
10051 E = FTy->param_end(); I != E; ++I, ++Idx)
10052 if (Attrs.paramHasAttr(Idx, Attribute::InReg))
10053 // FIXME: should only count parameters that are lowered to integers.
10054 InRegCount += (TD->getTypeSizeInBits(*I) + 31) / 32;
10056 if (InRegCount > 2) {
10057 report_fatal_error("Nest register in use - reduce number of inreg"
10063 case CallingConv::X86_FastCall:
10064 case CallingConv::X86_ThisCall:
10065 case CallingConv::Fast:
10066 // Pass 'nest' parameter in EAX.
10067 // Must be kept in sync with X86CallingConv.td
10068 NestReg = X86::EAX;
10072 SDValue OutChains[4];
10073 SDValue Addr, Disp;
10075 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
10076 DAG.getConstant(10, MVT::i32));
10077 Disp = DAG.getNode(ISD::SUB, dl, MVT::i32, FPtr, Addr);
10079 // This is storing the opcode for MOV32ri.
10080 const unsigned char MOV32ri = 0xB8; // X86::MOV32ri's opcode byte.
10081 const unsigned char N86Reg = X86_MC::getX86RegNum(NestReg);
10082 OutChains[0] = DAG.getStore(Root, dl,
10083 DAG.getConstant(MOV32ri|N86Reg, MVT::i8),
10084 Trmp, MachinePointerInfo(TrmpAddr),
10087 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
10088 DAG.getConstant(1, MVT::i32));
10089 OutChains[1] = DAG.getStore(Root, dl, Nest, Addr,
10090 MachinePointerInfo(TrmpAddr, 1),
10093 const unsigned char JMP = 0xE9; // jmp <32bit dst> opcode.
10094 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
10095 DAG.getConstant(5, MVT::i32));
10096 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(JMP, MVT::i8), Addr,
10097 MachinePointerInfo(TrmpAddr, 5),
10100 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
10101 DAG.getConstant(6, MVT::i32));
10102 OutChains[3] = DAG.getStore(Root, dl, Disp, Addr,
10103 MachinePointerInfo(TrmpAddr, 6),
10106 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains, 4);
10110 SDValue X86TargetLowering::LowerFLT_ROUNDS_(SDValue Op,
10111 SelectionDAG &DAG) const {
10113 The rounding mode is in bits 11:10 of FPSR, and has the following
10115 00 Round to nearest
10120 FLT_ROUNDS, on the other hand, expects the following:
10127 To perform the conversion, we do:
10128 (((((FPSR & 0x800) >> 11) | ((FPSR & 0x400) >> 9)) + 1) & 3)
10131 MachineFunction &MF = DAG.getMachineFunction();
10132 const TargetMachine &TM = MF.getTarget();
10133 const TargetFrameLowering &TFI = *TM.getFrameLowering();
10134 unsigned StackAlignment = TFI.getStackAlignment();
10135 EVT VT = Op.getValueType();
10136 DebugLoc DL = Op.getDebugLoc();
10138 // Save FP Control Word to stack slot
10139 int SSFI = MF.getFrameInfo()->CreateStackObject(2, StackAlignment, false);
10140 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
10143 MachineMemOperand *MMO =
10144 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
10145 MachineMemOperand::MOStore, 2, 2);
10147 SDValue Ops[] = { DAG.getEntryNode(), StackSlot };
10148 SDValue Chain = DAG.getMemIntrinsicNode(X86ISD::FNSTCW16m, DL,
10149 DAG.getVTList(MVT::Other),
10150 Ops, 2, MVT::i16, MMO);
10152 // Load FP Control Word from stack slot
10153 SDValue CWD = DAG.getLoad(MVT::i16, DL, Chain, StackSlot,
10154 MachinePointerInfo(), false, false, false, 0);
10156 // Transform as necessary
10158 DAG.getNode(ISD::SRL, DL, MVT::i16,
10159 DAG.getNode(ISD::AND, DL, MVT::i16,
10160 CWD, DAG.getConstant(0x800, MVT::i16)),
10161 DAG.getConstant(11, MVT::i8));
10163 DAG.getNode(ISD::SRL, DL, MVT::i16,
10164 DAG.getNode(ISD::AND, DL, MVT::i16,
10165 CWD, DAG.getConstant(0x400, MVT::i16)),
10166 DAG.getConstant(9, MVT::i8));
10169 DAG.getNode(ISD::AND, DL, MVT::i16,
10170 DAG.getNode(ISD::ADD, DL, MVT::i16,
10171 DAG.getNode(ISD::OR, DL, MVT::i16, CWD1, CWD2),
10172 DAG.getConstant(1, MVT::i16)),
10173 DAG.getConstant(3, MVT::i16));
10176 return DAG.getNode((VT.getSizeInBits() < 16 ?
10177 ISD::TRUNCATE : ISD::ZERO_EXTEND), DL, VT, RetVal);
10180 SDValue X86TargetLowering::LowerCTLZ(SDValue Op, SelectionDAG &DAG) const {
10181 EVT VT = Op.getValueType();
10183 unsigned NumBits = VT.getSizeInBits();
10184 DebugLoc dl = Op.getDebugLoc();
10186 Op = Op.getOperand(0);
10187 if (VT == MVT::i8) {
10188 // Zero extend to i32 since there is not an i8 bsr.
10190 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
10193 // Issue a bsr (scan bits in reverse) which also sets EFLAGS.
10194 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
10195 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
10197 // If src is zero (i.e. bsr sets ZF), returns NumBits.
10200 DAG.getConstant(NumBits+NumBits-1, OpVT),
10201 DAG.getConstant(X86::COND_E, MVT::i8),
10204 Op = DAG.getNode(X86ISD::CMOV, dl, OpVT, Ops, array_lengthof(Ops));
10206 // Finally xor with NumBits-1.
10207 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT));
10210 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
10214 SDValue X86TargetLowering::LowerCTLZ_ZERO_UNDEF(SDValue Op,
10215 SelectionDAG &DAG) const {
10216 EVT VT = Op.getValueType();
10218 unsigned NumBits = VT.getSizeInBits();
10219 DebugLoc dl = Op.getDebugLoc();
10221 Op = Op.getOperand(0);
10222 if (VT == MVT::i8) {
10223 // Zero extend to i32 since there is not an i8 bsr.
10225 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
10228 // Issue a bsr (scan bits in reverse).
10229 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
10230 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
10232 // And xor with NumBits-1.
10233 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT));
10236 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
10240 SDValue X86TargetLowering::LowerCTTZ(SDValue Op, SelectionDAG &DAG) const {
10241 EVT VT = Op.getValueType();
10242 unsigned NumBits = VT.getSizeInBits();
10243 DebugLoc dl = Op.getDebugLoc();
10244 Op = Op.getOperand(0);
10246 // Issue a bsf (scan bits forward) which also sets EFLAGS.
10247 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
10248 Op = DAG.getNode(X86ISD::BSF, dl, VTs, Op);
10250 // If src is zero (i.e. bsf sets ZF), returns NumBits.
10253 DAG.getConstant(NumBits, VT),
10254 DAG.getConstant(X86::COND_E, MVT::i8),
10257 return DAG.getNode(X86ISD::CMOV, dl, VT, Ops, array_lengthof(Ops));
10260 // Lower256IntArith - Break a 256-bit integer operation into two new 128-bit
10261 // ones, and then concatenate the result back.
10262 static SDValue Lower256IntArith(SDValue Op, SelectionDAG &DAG) {
10263 EVT VT = Op.getValueType();
10265 assert(VT.is256BitVector() && VT.isInteger() &&
10266 "Unsupported value type for operation");
10268 unsigned NumElems = VT.getVectorNumElements();
10269 DebugLoc dl = Op.getDebugLoc();
10271 // Extract the LHS vectors
10272 SDValue LHS = Op.getOperand(0);
10273 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
10274 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
10276 // Extract the RHS vectors
10277 SDValue RHS = Op.getOperand(1);
10278 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, dl);
10279 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, dl);
10281 MVT EltVT = VT.getVectorElementType().getSimpleVT();
10282 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
10284 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
10285 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1),
10286 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2));
10289 SDValue X86TargetLowering::LowerADD(SDValue Op, SelectionDAG &DAG) const {
10290 assert(Op.getValueType().is256BitVector() &&
10291 Op.getValueType().isInteger() &&
10292 "Only handle AVX 256-bit vector integer operation");
10293 return Lower256IntArith(Op, DAG);
10296 SDValue X86TargetLowering::LowerSUB(SDValue Op, SelectionDAG &DAG) const {
10297 assert(Op.getValueType().is256BitVector() &&
10298 Op.getValueType().isInteger() &&
10299 "Only handle AVX 256-bit vector integer operation");
10300 return Lower256IntArith(Op, DAG);
10303 SDValue X86TargetLowering::LowerMUL(SDValue Op, SelectionDAG &DAG) const {
10304 EVT VT = Op.getValueType();
10306 // Decompose 256-bit ops into smaller 128-bit ops.
10307 if (VT.is256BitVector() && !Subtarget->hasAVX2())
10308 return Lower256IntArith(Op, DAG);
10310 assert((VT == MVT::v2i64 || VT == MVT::v4i64) &&
10311 "Only know how to lower V2I64/V4I64 multiply");
10313 DebugLoc dl = Op.getDebugLoc();
10315 // Ahi = psrlqi(a, 32);
10316 // Bhi = psrlqi(b, 32);
10318 // AloBlo = pmuludq(a, b);
10319 // AloBhi = pmuludq(a, Bhi);
10320 // AhiBlo = pmuludq(Ahi, b);
10322 // AloBhi = psllqi(AloBhi, 32);
10323 // AhiBlo = psllqi(AhiBlo, 32);
10324 // return AloBlo + AloBhi + AhiBlo;
10326 SDValue A = Op.getOperand(0);
10327 SDValue B = Op.getOperand(1);
10329 SDValue ShAmt = DAG.getConstant(32, MVT::i32);
10331 SDValue Ahi = DAG.getNode(X86ISD::VSRLI, dl, VT, A, ShAmt);
10332 SDValue Bhi = DAG.getNode(X86ISD::VSRLI, dl, VT, B, ShAmt);
10334 // Bit cast to 32-bit vectors for MULUDQ
10335 EVT MulVT = (VT == MVT::v2i64) ? MVT::v4i32 : MVT::v8i32;
10336 A = DAG.getNode(ISD::BITCAST, dl, MulVT, A);
10337 B = DAG.getNode(ISD::BITCAST, dl, MulVT, B);
10338 Ahi = DAG.getNode(ISD::BITCAST, dl, MulVT, Ahi);
10339 Bhi = DAG.getNode(ISD::BITCAST, dl, MulVT, Bhi);
10341 SDValue AloBlo = DAG.getNode(X86ISD::PMULUDQ, dl, VT, A, B);
10342 SDValue AloBhi = DAG.getNode(X86ISD::PMULUDQ, dl, VT, A, Bhi);
10343 SDValue AhiBlo = DAG.getNode(X86ISD::PMULUDQ, dl, VT, Ahi, B);
10345 AloBhi = DAG.getNode(X86ISD::VSHLI, dl, VT, AloBhi, ShAmt);
10346 AhiBlo = DAG.getNode(X86ISD::VSHLI, dl, VT, AhiBlo, ShAmt);
10348 SDValue Res = DAG.getNode(ISD::ADD, dl, VT, AloBlo, AloBhi);
10349 return DAG.getNode(ISD::ADD, dl, VT, Res, AhiBlo);
10352 SDValue X86TargetLowering::LowerShift(SDValue Op, SelectionDAG &DAG) const {
10354 EVT VT = Op.getValueType();
10355 DebugLoc dl = Op.getDebugLoc();
10356 SDValue R = Op.getOperand(0);
10357 SDValue Amt = Op.getOperand(1);
10358 LLVMContext *Context = DAG.getContext();
10360 if (!Subtarget->hasSSE2())
10363 // Optimize shl/srl/sra with constant shift amount.
10364 if (isSplatVector(Amt.getNode())) {
10365 SDValue SclrAmt = Amt->getOperand(0);
10366 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(SclrAmt)) {
10367 uint64_t ShiftAmt = C->getZExtValue();
10369 if (VT == MVT::v2i64 || VT == MVT::v4i32 || VT == MVT::v8i16 ||
10370 (Subtarget->hasAVX2() &&
10371 (VT == MVT::v4i64 || VT == MVT::v8i32 || VT == MVT::v16i16))) {
10372 if (Op.getOpcode() == ISD::SHL)
10373 return DAG.getNode(X86ISD::VSHLI, dl, VT, R,
10374 DAG.getConstant(ShiftAmt, MVT::i32));
10375 if (Op.getOpcode() == ISD::SRL)
10376 return DAG.getNode(X86ISD::VSRLI, dl, VT, R,
10377 DAG.getConstant(ShiftAmt, MVT::i32));
10378 if (Op.getOpcode() == ISD::SRA && VT != MVT::v2i64 && VT != MVT::v4i64)
10379 return DAG.getNode(X86ISD::VSRAI, dl, VT, R,
10380 DAG.getConstant(ShiftAmt, MVT::i32));
10383 if (VT == MVT::v16i8) {
10384 if (Op.getOpcode() == ISD::SHL) {
10385 // Make a large shift.
10386 SDValue SHL = DAG.getNode(X86ISD::VSHLI, dl, MVT::v8i16, R,
10387 DAG.getConstant(ShiftAmt, MVT::i32));
10388 SHL = DAG.getNode(ISD::BITCAST, dl, VT, SHL);
10389 // Zero out the rightmost bits.
10390 SmallVector<SDValue, 16> V(16,
10391 DAG.getConstant(uint8_t(-1U << ShiftAmt),
10393 return DAG.getNode(ISD::AND, dl, VT, SHL,
10394 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 16));
10396 if (Op.getOpcode() == ISD::SRL) {
10397 // Make a large shift.
10398 SDValue SRL = DAG.getNode(X86ISD::VSRLI, dl, MVT::v8i16, R,
10399 DAG.getConstant(ShiftAmt, MVT::i32));
10400 SRL = DAG.getNode(ISD::BITCAST, dl, VT, SRL);
10401 // Zero out the leftmost bits.
10402 SmallVector<SDValue, 16> V(16,
10403 DAG.getConstant(uint8_t(-1U) >> ShiftAmt,
10405 return DAG.getNode(ISD::AND, dl, VT, SRL,
10406 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 16));
10408 if (Op.getOpcode() == ISD::SRA) {
10409 if (ShiftAmt == 7) {
10410 // R s>> 7 === R s< 0
10411 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
10412 return DAG.getNode(X86ISD::PCMPGT, dl, VT, Zeros, R);
10415 // R s>> a === ((R u>> a) ^ m) - m
10416 SDValue Res = DAG.getNode(ISD::SRL, dl, VT, R, Amt);
10417 SmallVector<SDValue, 16> V(16, DAG.getConstant(128 >> ShiftAmt,
10419 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 16);
10420 Res = DAG.getNode(ISD::XOR, dl, VT, Res, Mask);
10421 Res = DAG.getNode(ISD::SUB, dl, VT, Res, Mask);
10424 llvm_unreachable("Unknown shift opcode.");
10427 if (Subtarget->hasAVX2() && VT == MVT::v32i8) {
10428 if (Op.getOpcode() == ISD::SHL) {
10429 // Make a large shift.
10430 SDValue SHL = DAG.getNode(X86ISD::VSHLI, dl, MVT::v16i16, R,
10431 DAG.getConstant(ShiftAmt, MVT::i32));
10432 SHL = DAG.getNode(ISD::BITCAST, dl, VT, SHL);
10433 // Zero out the rightmost bits.
10434 SmallVector<SDValue, 32> V(32,
10435 DAG.getConstant(uint8_t(-1U << ShiftAmt),
10437 return DAG.getNode(ISD::AND, dl, VT, SHL,
10438 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 32));
10440 if (Op.getOpcode() == ISD::SRL) {
10441 // Make a large shift.
10442 SDValue SRL = DAG.getNode(X86ISD::VSRLI, dl, MVT::v16i16, R,
10443 DAG.getConstant(ShiftAmt, MVT::i32));
10444 SRL = DAG.getNode(ISD::BITCAST, dl, VT, SRL);
10445 // Zero out the leftmost bits.
10446 SmallVector<SDValue, 32> V(32,
10447 DAG.getConstant(uint8_t(-1U) >> ShiftAmt,
10449 return DAG.getNode(ISD::AND, dl, VT, SRL,
10450 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 32));
10452 if (Op.getOpcode() == ISD::SRA) {
10453 if (ShiftAmt == 7) {
10454 // R s>> 7 === R s< 0
10455 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
10456 return DAG.getNode(X86ISD::PCMPGT, dl, VT, Zeros, R);
10459 // R s>> a === ((R u>> a) ^ m) - m
10460 SDValue Res = DAG.getNode(ISD::SRL, dl, VT, R, Amt);
10461 SmallVector<SDValue, 32> V(32, DAG.getConstant(128 >> ShiftAmt,
10463 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 32);
10464 Res = DAG.getNode(ISD::XOR, dl, VT, Res, Mask);
10465 Res = DAG.getNode(ISD::SUB, dl, VT, Res, Mask);
10468 llvm_unreachable("Unknown shift opcode.");
10473 // Lower SHL with variable shift amount.
10474 if (VT == MVT::v4i32 && Op->getOpcode() == ISD::SHL) {
10475 Op = DAG.getNode(X86ISD::VSHLI, dl, VT, Op.getOperand(1),
10476 DAG.getConstant(23, MVT::i32));
10478 const uint32_t CV[] = { 0x3f800000U, 0x3f800000U, 0x3f800000U, 0x3f800000U};
10479 Constant *C = ConstantDataVector::get(*Context, CV);
10480 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
10481 SDValue Addend = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
10482 MachinePointerInfo::getConstantPool(),
10483 false, false, false, 16);
10485 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Addend);
10486 Op = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, Op);
10487 Op = DAG.getNode(ISD::FP_TO_SINT, dl, VT, Op);
10488 return DAG.getNode(ISD::MUL, dl, VT, Op, R);
10490 if (VT == MVT::v16i8 && Op->getOpcode() == ISD::SHL) {
10491 assert(Subtarget->hasSSE2() && "Need SSE2 for pslli/pcmpeq.");
10494 Op = DAG.getNode(X86ISD::VSHLI, dl, MVT::v8i16, Op.getOperand(1),
10495 DAG.getConstant(5, MVT::i32));
10496 Op = DAG.getNode(ISD::BITCAST, dl, VT, Op);
10498 // Turn 'a' into a mask suitable for VSELECT
10499 SDValue VSelM = DAG.getConstant(0x80, VT);
10500 SDValue OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
10501 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
10503 SDValue CM1 = DAG.getConstant(0x0f, VT);
10504 SDValue CM2 = DAG.getConstant(0x3f, VT);
10506 // r = VSELECT(r, psllw(r & (char16)15, 4), a);
10507 SDValue M = DAG.getNode(ISD::AND, dl, VT, R, CM1);
10508 M = getTargetVShiftNode(X86ISD::VSHLI, dl, MVT::v8i16, M,
10509 DAG.getConstant(4, MVT::i32), DAG);
10510 M = DAG.getNode(ISD::BITCAST, dl, VT, M);
10511 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel, M, R);
10514 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op);
10515 OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
10516 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
10518 // r = VSELECT(r, psllw(r & (char16)63, 2), a);
10519 M = DAG.getNode(ISD::AND, dl, VT, R, CM2);
10520 M = getTargetVShiftNode(X86ISD::VSHLI, dl, MVT::v8i16, M,
10521 DAG.getConstant(2, MVT::i32), DAG);
10522 M = DAG.getNode(ISD::BITCAST, dl, VT, M);
10523 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel, M, R);
10526 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op);
10527 OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
10528 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
10530 // return VSELECT(r, r+r, a);
10531 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel,
10532 DAG.getNode(ISD::ADD, dl, VT, R, R), R);
10536 // Decompose 256-bit shifts into smaller 128-bit shifts.
10537 if (VT.is256BitVector()) {
10538 unsigned NumElems = VT.getVectorNumElements();
10539 MVT EltVT = VT.getVectorElementType().getSimpleVT();
10540 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
10542 // Extract the two vectors
10543 SDValue V1 = Extract128BitVector(R, 0, DAG, dl);
10544 SDValue V2 = Extract128BitVector(R, NumElems/2, DAG, dl);
10546 // Recreate the shift amount vectors
10547 SDValue Amt1, Amt2;
10548 if (Amt.getOpcode() == ISD::BUILD_VECTOR) {
10549 // Constant shift amount
10550 SmallVector<SDValue, 4> Amt1Csts;
10551 SmallVector<SDValue, 4> Amt2Csts;
10552 for (unsigned i = 0; i != NumElems/2; ++i)
10553 Amt1Csts.push_back(Amt->getOperand(i));
10554 for (unsigned i = NumElems/2; i != NumElems; ++i)
10555 Amt2Csts.push_back(Amt->getOperand(i));
10557 Amt1 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT,
10558 &Amt1Csts[0], NumElems/2);
10559 Amt2 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT,
10560 &Amt2Csts[0], NumElems/2);
10562 // Variable shift amount
10563 Amt1 = Extract128BitVector(Amt, 0, DAG, dl);
10564 Amt2 = Extract128BitVector(Amt, NumElems/2, DAG, dl);
10567 // Issue new vector shifts for the smaller types
10568 V1 = DAG.getNode(Op.getOpcode(), dl, NewVT, V1, Amt1);
10569 V2 = DAG.getNode(Op.getOpcode(), dl, NewVT, V2, Amt2);
10571 // Concatenate the result back
10572 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, V1, V2);
10578 SDValue X86TargetLowering::LowerXALUO(SDValue Op, SelectionDAG &DAG) const {
10579 // Lower the "add/sub/mul with overflow" instruction into a regular ins plus
10580 // a "setcc" instruction that checks the overflow flag. The "brcond" lowering
10581 // looks for this combo and may remove the "setcc" instruction if the "setcc"
10582 // has only one use.
10583 SDNode *N = Op.getNode();
10584 SDValue LHS = N->getOperand(0);
10585 SDValue RHS = N->getOperand(1);
10586 unsigned BaseOp = 0;
10588 DebugLoc DL = Op.getDebugLoc();
10589 switch (Op.getOpcode()) {
10590 default: llvm_unreachable("Unknown ovf instruction!");
10592 // A subtract of one will be selected as a INC. Note that INC doesn't
10593 // set CF, so we can't do this for UADDO.
10594 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
10596 BaseOp = X86ISD::INC;
10597 Cond = X86::COND_O;
10600 BaseOp = X86ISD::ADD;
10601 Cond = X86::COND_O;
10604 BaseOp = X86ISD::ADD;
10605 Cond = X86::COND_B;
10608 // A subtract of one will be selected as a DEC. Note that DEC doesn't
10609 // set CF, so we can't do this for USUBO.
10610 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
10612 BaseOp = X86ISD::DEC;
10613 Cond = X86::COND_O;
10616 BaseOp = X86ISD::SUB;
10617 Cond = X86::COND_O;
10620 BaseOp = X86ISD::SUB;
10621 Cond = X86::COND_B;
10624 BaseOp = X86ISD::SMUL;
10625 Cond = X86::COND_O;
10627 case ISD::UMULO: { // i64, i8 = umulo lhs, rhs --> i64, i64, i32 umul lhs,rhs
10628 SDVTList VTs = DAG.getVTList(N->getValueType(0), N->getValueType(0),
10630 SDValue Sum = DAG.getNode(X86ISD::UMUL, DL, VTs, LHS, RHS);
10633 DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
10634 DAG.getConstant(X86::COND_O, MVT::i32),
10635 SDValue(Sum.getNode(), 2));
10637 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
10641 // Also sets EFLAGS.
10642 SDVTList VTs = DAG.getVTList(N->getValueType(0), MVT::i32);
10643 SDValue Sum = DAG.getNode(BaseOp, DL, VTs, LHS, RHS);
10646 DAG.getNode(X86ISD::SETCC, DL, N->getValueType(1),
10647 DAG.getConstant(Cond, MVT::i32),
10648 SDValue(Sum.getNode(), 1));
10650 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
10653 SDValue X86TargetLowering::LowerSIGN_EXTEND_INREG(SDValue Op,
10654 SelectionDAG &DAG) const {
10655 DebugLoc dl = Op.getDebugLoc();
10656 EVT ExtraVT = cast<VTSDNode>(Op.getOperand(1))->getVT();
10657 EVT VT = Op.getValueType();
10659 if (!Subtarget->hasSSE2() || !VT.isVector())
10662 unsigned BitsDiff = VT.getScalarType().getSizeInBits() -
10663 ExtraVT.getScalarType().getSizeInBits();
10664 SDValue ShAmt = DAG.getConstant(BitsDiff, MVT::i32);
10666 switch (VT.getSimpleVT().SimpleTy) {
10667 default: return SDValue();
10670 if (!Subtarget->hasAVX())
10672 if (!Subtarget->hasAVX2()) {
10673 // needs to be split
10674 unsigned NumElems = VT.getVectorNumElements();
10676 // Extract the LHS vectors
10677 SDValue LHS = Op.getOperand(0);
10678 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
10679 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
10681 MVT EltVT = VT.getVectorElementType().getSimpleVT();
10682 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
10684 EVT ExtraEltVT = ExtraVT.getVectorElementType();
10685 unsigned ExtraNumElems = ExtraVT.getVectorNumElements();
10686 ExtraVT = EVT::getVectorVT(*DAG.getContext(), ExtraEltVT,
10688 SDValue Extra = DAG.getValueType(ExtraVT);
10690 LHS1 = DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, Extra);
10691 LHS2 = DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, Extra);
10693 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, LHS1, LHS2);;
10698 SDValue Tmp1 = getTargetVShiftNode(X86ISD::VSHLI, dl, VT,
10699 Op.getOperand(0), ShAmt, DAG);
10700 return getTargetVShiftNode(X86ISD::VSRAI, dl, VT, Tmp1, ShAmt, DAG);
10706 SDValue X86TargetLowering::LowerMEMBARRIER(SDValue Op, SelectionDAG &DAG) const{
10707 DebugLoc dl = Op.getDebugLoc();
10709 // Go ahead and emit the fence on x86-64 even if we asked for no-sse2.
10710 // There isn't any reason to disable it if the target processor supports it.
10711 if (!Subtarget->hasSSE2() && !Subtarget->is64Bit()) {
10712 SDValue Chain = Op.getOperand(0);
10713 SDValue Zero = DAG.getConstant(0, MVT::i32);
10715 DAG.getRegister(X86::ESP, MVT::i32), // Base
10716 DAG.getTargetConstant(1, MVT::i8), // Scale
10717 DAG.getRegister(0, MVT::i32), // Index
10718 DAG.getTargetConstant(0, MVT::i32), // Disp
10719 DAG.getRegister(0, MVT::i32), // Segment.
10724 DAG.getMachineNode(X86::OR32mrLocked, dl, MVT::Other, Ops,
10725 array_lengthof(Ops));
10726 return SDValue(Res, 0);
10729 unsigned isDev = cast<ConstantSDNode>(Op.getOperand(5))->getZExtValue();
10731 return DAG.getNode(X86ISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0));
10733 unsigned Op1 = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
10734 unsigned Op2 = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue();
10735 unsigned Op3 = cast<ConstantSDNode>(Op.getOperand(3))->getZExtValue();
10736 unsigned Op4 = cast<ConstantSDNode>(Op.getOperand(4))->getZExtValue();
10738 // def : Pat<(membarrier (i8 0), (i8 0), (i8 0), (i8 1), (i8 1)), (SFENCE)>;
10739 if (!Op1 && !Op2 && !Op3 && Op4)
10740 return DAG.getNode(X86ISD::SFENCE, dl, MVT::Other, Op.getOperand(0));
10742 // def : Pat<(membarrier (i8 1), (i8 0), (i8 0), (i8 0), (i8 1)), (LFENCE)>;
10743 if (Op1 && !Op2 && !Op3 && !Op4)
10744 return DAG.getNode(X86ISD::LFENCE, dl, MVT::Other, Op.getOperand(0));
10746 // def : Pat<(membarrier (i8 imm), (i8 imm), (i8 imm), (i8 imm), (i8 1)),
10748 return DAG.getNode(X86ISD::MFENCE, dl, MVT::Other, Op.getOperand(0));
10751 SDValue X86TargetLowering::LowerATOMIC_FENCE(SDValue Op,
10752 SelectionDAG &DAG) const {
10753 DebugLoc dl = Op.getDebugLoc();
10754 AtomicOrdering FenceOrdering = static_cast<AtomicOrdering>(
10755 cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue());
10756 SynchronizationScope FenceScope = static_cast<SynchronizationScope>(
10757 cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue());
10759 // The only fence that needs an instruction is a sequentially-consistent
10760 // cross-thread fence.
10761 if (FenceOrdering == SequentiallyConsistent && FenceScope == CrossThread) {
10762 // Use mfence if we have SSE2 or we're on x86-64 (even if we asked for
10763 // no-sse2). There isn't any reason to disable it if the target processor
10765 if (Subtarget->hasSSE2() || Subtarget->is64Bit())
10766 return DAG.getNode(X86ISD::MFENCE, dl, MVT::Other, Op.getOperand(0));
10768 SDValue Chain = Op.getOperand(0);
10769 SDValue Zero = DAG.getConstant(0, MVT::i32);
10771 DAG.getRegister(X86::ESP, MVT::i32), // Base
10772 DAG.getTargetConstant(1, MVT::i8), // Scale
10773 DAG.getRegister(0, MVT::i32), // Index
10774 DAG.getTargetConstant(0, MVT::i32), // Disp
10775 DAG.getRegister(0, MVT::i32), // Segment.
10780 DAG.getMachineNode(X86::OR32mrLocked, dl, MVT::Other, Ops,
10781 array_lengthof(Ops));
10782 return SDValue(Res, 0);
10785 // MEMBARRIER is a compiler barrier; it codegens to a no-op.
10786 return DAG.getNode(X86ISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0));
10790 SDValue X86TargetLowering::LowerCMP_SWAP(SDValue Op, SelectionDAG &DAG) const {
10791 EVT T = Op.getValueType();
10792 DebugLoc DL = Op.getDebugLoc();
10795 switch(T.getSimpleVT().SimpleTy) {
10796 default: llvm_unreachable("Invalid value type!");
10797 case MVT::i8: Reg = X86::AL; size = 1; break;
10798 case MVT::i16: Reg = X86::AX; size = 2; break;
10799 case MVT::i32: Reg = X86::EAX; size = 4; break;
10801 assert(Subtarget->is64Bit() && "Node not type legal!");
10802 Reg = X86::RAX; size = 8;
10805 SDValue cpIn = DAG.getCopyToReg(Op.getOperand(0), DL, Reg,
10806 Op.getOperand(2), SDValue());
10807 SDValue Ops[] = { cpIn.getValue(0),
10810 DAG.getTargetConstant(size, MVT::i8),
10811 cpIn.getValue(1) };
10812 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
10813 MachineMemOperand *MMO = cast<AtomicSDNode>(Op)->getMemOperand();
10814 SDValue Result = DAG.getMemIntrinsicNode(X86ISD::LCMPXCHG_DAG, DL, Tys,
10817 DAG.getCopyFromReg(Result.getValue(0), DL, Reg, T, Result.getValue(1));
10821 SDValue X86TargetLowering::LowerREADCYCLECOUNTER(SDValue Op,
10822 SelectionDAG &DAG) const {
10823 assert(Subtarget->is64Bit() && "Result not type legalized?");
10824 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
10825 SDValue TheChain = Op.getOperand(0);
10826 DebugLoc dl = Op.getDebugLoc();
10827 SDValue rd = DAG.getNode(X86ISD::RDTSC_DAG, dl, Tys, &TheChain, 1);
10828 SDValue rax = DAG.getCopyFromReg(rd, dl, X86::RAX, MVT::i64, rd.getValue(1));
10829 SDValue rdx = DAG.getCopyFromReg(rax.getValue(1), dl, X86::RDX, MVT::i64,
10831 SDValue Tmp = DAG.getNode(ISD::SHL, dl, MVT::i64, rdx,
10832 DAG.getConstant(32, MVT::i8));
10834 DAG.getNode(ISD::OR, dl, MVT::i64, rax, Tmp),
10837 return DAG.getMergeValues(Ops, 2, dl);
10840 SDValue X86TargetLowering::LowerBITCAST(SDValue Op,
10841 SelectionDAG &DAG) const {
10842 EVT SrcVT = Op.getOperand(0).getValueType();
10843 EVT DstVT = Op.getValueType();
10844 assert(Subtarget->is64Bit() && !Subtarget->hasSSE2() &&
10845 Subtarget->hasMMX() && "Unexpected custom BITCAST");
10846 assert((DstVT == MVT::i64 ||
10847 (DstVT.isVector() && DstVT.getSizeInBits()==64)) &&
10848 "Unexpected custom BITCAST");
10849 // i64 <=> MMX conversions are Legal.
10850 if (SrcVT==MVT::i64 && DstVT.isVector())
10852 if (DstVT==MVT::i64 && SrcVT.isVector())
10854 // MMX <=> MMX conversions are Legal.
10855 if (SrcVT.isVector() && DstVT.isVector())
10857 // All other conversions need to be expanded.
10861 SDValue X86TargetLowering::LowerLOAD_SUB(SDValue Op, SelectionDAG &DAG) const {
10862 SDNode *Node = Op.getNode();
10863 DebugLoc dl = Node->getDebugLoc();
10864 EVT T = Node->getValueType(0);
10865 SDValue negOp = DAG.getNode(ISD::SUB, dl, T,
10866 DAG.getConstant(0, T), Node->getOperand(2));
10867 return DAG.getAtomic(ISD::ATOMIC_LOAD_ADD, dl,
10868 cast<AtomicSDNode>(Node)->getMemoryVT(),
10869 Node->getOperand(0),
10870 Node->getOperand(1), negOp,
10871 cast<AtomicSDNode>(Node)->getSrcValue(),
10872 cast<AtomicSDNode>(Node)->getAlignment(),
10873 cast<AtomicSDNode>(Node)->getOrdering(),
10874 cast<AtomicSDNode>(Node)->getSynchScope());
10877 static SDValue LowerATOMIC_STORE(SDValue Op, SelectionDAG &DAG) {
10878 SDNode *Node = Op.getNode();
10879 DebugLoc dl = Node->getDebugLoc();
10880 EVT VT = cast<AtomicSDNode>(Node)->getMemoryVT();
10882 // Convert seq_cst store -> xchg
10883 // Convert wide store -> swap (-> cmpxchg8b/cmpxchg16b)
10884 // FIXME: On 32-bit, store -> fist or movq would be more efficient
10885 // (The only way to get a 16-byte store is cmpxchg16b)
10886 // FIXME: 16-byte ATOMIC_SWAP isn't actually hooked up at the moment.
10887 if (cast<AtomicSDNode>(Node)->getOrdering() == SequentiallyConsistent ||
10888 !DAG.getTargetLoweringInfo().isTypeLegal(VT)) {
10889 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_SWAP, dl,
10890 cast<AtomicSDNode>(Node)->getMemoryVT(),
10891 Node->getOperand(0),
10892 Node->getOperand(1), Node->getOperand(2),
10893 cast<AtomicSDNode>(Node)->getMemOperand(),
10894 cast<AtomicSDNode>(Node)->getOrdering(),
10895 cast<AtomicSDNode>(Node)->getSynchScope());
10896 return Swap.getValue(1);
10898 // Other atomic stores have a simple pattern.
10902 static SDValue LowerADDC_ADDE_SUBC_SUBE(SDValue Op, SelectionDAG &DAG) {
10903 EVT VT = Op.getNode()->getValueType(0);
10905 // Let legalize expand this if it isn't a legal type yet.
10906 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
10909 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
10912 bool ExtraOp = false;
10913 switch (Op.getOpcode()) {
10914 default: llvm_unreachable("Invalid code");
10915 case ISD::ADDC: Opc = X86ISD::ADD; break;
10916 case ISD::ADDE: Opc = X86ISD::ADC; ExtraOp = true; break;
10917 case ISD::SUBC: Opc = X86ISD::SUB; break;
10918 case ISD::SUBE: Opc = X86ISD::SBB; ExtraOp = true; break;
10922 return DAG.getNode(Opc, Op->getDebugLoc(), VTs, Op.getOperand(0),
10924 return DAG.getNode(Opc, Op->getDebugLoc(), VTs, Op.getOperand(0),
10925 Op.getOperand(1), Op.getOperand(2));
10928 /// LowerOperation - Provide custom lowering hooks for some operations.
10930 SDValue X86TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
10931 switch (Op.getOpcode()) {
10932 default: llvm_unreachable("Should not custom lower this!");
10933 case ISD::SIGN_EXTEND_INREG: return LowerSIGN_EXTEND_INREG(Op,DAG);
10934 case ISD::MEMBARRIER: return LowerMEMBARRIER(Op,DAG);
10935 case ISD::ATOMIC_FENCE: return LowerATOMIC_FENCE(Op,DAG);
10936 case ISD::ATOMIC_CMP_SWAP: return LowerCMP_SWAP(Op,DAG);
10937 case ISD::ATOMIC_LOAD_SUB: return LowerLOAD_SUB(Op,DAG);
10938 case ISD::ATOMIC_STORE: return LowerATOMIC_STORE(Op,DAG);
10939 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
10940 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG);
10941 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
10942 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
10943 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG);
10944 case ISD::EXTRACT_SUBVECTOR: return LowerEXTRACT_SUBVECTOR(Op, DAG);
10945 case ISD::INSERT_SUBVECTOR: return LowerINSERT_SUBVECTOR(Op, DAG);
10946 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
10947 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
10948 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
10949 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
10950 case ISD::ExternalSymbol: return LowerExternalSymbol(Op, DAG);
10951 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
10952 case ISD::SHL_PARTS:
10953 case ISD::SRA_PARTS:
10954 case ISD::SRL_PARTS: return LowerShiftParts(Op, DAG);
10955 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG);
10956 case ISD::UINT_TO_FP: return LowerUINT_TO_FP(Op, DAG);
10957 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG);
10958 case ISD::FP_TO_UINT: return LowerFP_TO_UINT(Op, DAG);
10959 case ISD::FABS: return LowerFABS(Op, DAG);
10960 case ISD::FNEG: return LowerFNEG(Op, DAG);
10961 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG);
10962 case ISD::FGETSIGN: return LowerFGETSIGN(Op, DAG);
10963 case ISD::SETCC: return LowerSETCC(Op, DAG);
10964 case ISD::SELECT: return LowerSELECT(Op, DAG);
10965 case ISD::BRCOND: return LowerBRCOND(Op, DAG);
10966 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
10967 case ISD::VASTART: return LowerVASTART(Op, DAG);
10968 case ISD::VAARG: return LowerVAARG(Op, DAG);
10969 case ISD::VACOPY: return LowerVACOPY(Op, DAG);
10970 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
10971 case ISD::INTRINSIC_W_CHAIN: return LowerINTRINSIC_W_CHAIN(Op, DAG);
10972 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
10973 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
10974 case ISD::FRAME_TO_ARGS_OFFSET:
10975 return LowerFRAME_TO_ARGS_OFFSET(Op, DAG);
10976 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
10977 case ISD::EH_RETURN: return LowerEH_RETURN(Op, DAG);
10978 case ISD::INIT_TRAMPOLINE: return LowerINIT_TRAMPOLINE(Op, DAG);
10979 case ISD::ADJUST_TRAMPOLINE: return LowerADJUST_TRAMPOLINE(Op, DAG);
10980 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
10981 case ISD::CTLZ: return LowerCTLZ(Op, DAG);
10982 case ISD::CTLZ_ZERO_UNDEF: return LowerCTLZ_ZERO_UNDEF(Op, DAG);
10983 case ISD::CTTZ: return LowerCTTZ(Op, DAG);
10984 case ISD::MUL: return LowerMUL(Op, DAG);
10987 case ISD::SHL: return LowerShift(Op, DAG);
10993 case ISD::UMULO: return LowerXALUO(Op, DAG);
10994 case ISD::READCYCLECOUNTER: return LowerREADCYCLECOUNTER(Op, DAG);
10995 case ISD::BITCAST: return LowerBITCAST(Op, DAG);
10999 case ISD::SUBE: return LowerADDC_ADDE_SUBC_SUBE(Op, DAG);
11000 case ISD::ADD: return LowerADD(Op, DAG);
11001 case ISD::SUB: return LowerSUB(Op, DAG);
11005 static void ReplaceATOMIC_LOAD(SDNode *Node,
11006 SmallVectorImpl<SDValue> &Results,
11007 SelectionDAG &DAG) {
11008 DebugLoc dl = Node->getDebugLoc();
11009 EVT VT = cast<AtomicSDNode>(Node)->getMemoryVT();
11011 // Convert wide load -> cmpxchg8b/cmpxchg16b
11012 // FIXME: On 32-bit, load -> fild or movq would be more efficient
11013 // (The only way to get a 16-byte load is cmpxchg16b)
11014 // FIXME: 16-byte ATOMIC_CMP_SWAP isn't actually hooked up at the moment.
11015 SDValue Zero = DAG.getConstant(0, VT);
11016 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_CMP_SWAP, dl, VT,
11017 Node->getOperand(0),
11018 Node->getOperand(1), Zero, Zero,
11019 cast<AtomicSDNode>(Node)->getMemOperand(),
11020 cast<AtomicSDNode>(Node)->getOrdering(),
11021 cast<AtomicSDNode>(Node)->getSynchScope());
11022 Results.push_back(Swap.getValue(0));
11023 Results.push_back(Swap.getValue(1));
11026 void X86TargetLowering::
11027 ReplaceATOMIC_BINARY_64(SDNode *Node, SmallVectorImpl<SDValue>&Results,
11028 SelectionDAG &DAG, unsigned NewOp) const {
11029 DebugLoc dl = Node->getDebugLoc();
11030 assert (Node->getValueType(0) == MVT::i64 &&
11031 "Only know how to expand i64 atomics");
11033 SDValue Chain = Node->getOperand(0);
11034 SDValue In1 = Node->getOperand(1);
11035 SDValue In2L = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
11036 Node->getOperand(2), DAG.getIntPtrConstant(0));
11037 SDValue In2H = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
11038 Node->getOperand(2), DAG.getIntPtrConstant(1));
11039 SDValue Ops[] = { Chain, In1, In2L, In2H };
11040 SDVTList Tys = DAG.getVTList(MVT::i32, MVT::i32, MVT::Other);
11042 DAG.getMemIntrinsicNode(NewOp, dl, Tys, Ops, 4, MVT::i64,
11043 cast<MemSDNode>(Node)->getMemOperand());
11044 SDValue OpsF[] = { Result.getValue(0), Result.getValue(1)};
11045 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, OpsF, 2));
11046 Results.push_back(Result.getValue(2));
11049 /// ReplaceNodeResults - Replace a node with an illegal result type
11050 /// with a new node built out of custom code.
11051 void X86TargetLowering::ReplaceNodeResults(SDNode *N,
11052 SmallVectorImpl<SDValue>&Results,
11053 SelectionDAG &DAG) const {
11054 DebugLoc dl = N->getDebugLoc();
11055 switch (N->getOpcode()) {
11057 llvm_unreachable("Do not know how to custom type legalize this operation!");
11058 case ISD::SIGN_EXTEND_INREG:
11063 // We don't want to expand or promote these.
11065 case ISD::FP_TO_SINT:
11066 case ISD::FP_TO_UINT: {
11067 bool IsSigned = N->getOpcode() == ISD::FP_TO_SINT;
11069 if (!IsSigned && !isIntegerTypeFTOL(SDValue(N, 0).getValueType()))
11072 std::pair<SDValue,SDValue> Vals =
11073 FP_TO_INTHelper(SDValue(N, 0), DAG, IsSigned, /*IsReplace=*/ true);
11074 SDValue FIST = Vals.first, StackSlot = Vals.second;
11075 if (FIST.getNode() != 0) {
11076 EVT VT = N->getValueType(0);
11077 // Return a load from the stack slot.
11078 if (StackSlot.getNode() != 0)
11079 Results.push_back(DAG.getLoad(VT, dl, FIST, StackSlot,
11080 MachinePointerInfo(),
11081 false, false, false, 0));
11083 Results.push_back(FIST);
11087 case ISD::READCYCLECOUNTER: {
11088 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
11089 SDValue TheChain = N->getOperand(0);
11090 SDValue rd = DAG.getNode(X86ISD::RDTSC_DAG, dl, Tys, &TheChain, 1);
11091 SDValue eax = DAG.getCopyFromReg(rd, dl, X86::EAX, MVT::i32,
11093 SDValue edx = DAG.getCopyFromReg(eax.getValue(1), dl, X86::EDX, MVT::i32,
11095 // Use a buildpair to merge the two 32-bit values into a 64-bit one.
11096 SDValue Ops[] = { eax, edx };
11097 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Ops, 2));
11098 Results.push_back(edx.getValue(1));
11101 case ISD::ATOMIC_CMP_SWAP: {
11102 EVT T = N->getValueType(0);
11103 assert((T == MVT::i64 || T == MVT::i128) && "can only expand cmpxchg pair");
11104 bool Regs64bit = T == MVT::i128;
11105 EVT HalfT = Regs64bit ? MVT::i64 : MVT::i32;
11106 SDValue cpInL, cpInH;
11107 cpInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2),
11108 DAG.getConstant(0, HalfT));
11109 cpInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2),
11110 DAG.getConstant(1, HalfT));
11111 cpInL = DAG.getCopyToReg(N->getOperand(0), dl,
11112 Regs64bit ? X86::RAX : X86::EAX,
11114 cpInH = DAG.getCopyToReg(cpInL.getValue(0), dl,
11115 Regs64bit ? X86::RDX : X86::EDX,
11116 cpInH, cpInL.getValue(1));
11117 SDValue swapInL, swapInH;
11118 swapInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3),
11119 DAG.getConstant(0, HalfT));
11120 swapInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3),
11121 DAG.getConstant(1, HalfT));
11122 swapInL = DAG.getCopyToReg(cpInH.getValue(0), dl,
11123 Regs64bit ? X86::RBX : X86::EBX,
11124 swapInL, cpInH.getValue(1));
11125 swapInH = DAG.getCopyToReg(swapInL.getValue(0), dl,
11126 Regs64bit ? X86::RCX : X86::ECX,
11127 swapInH, swapInL.getValue(1));
11128 SDValue Ops[] = { swapInH.getValue(0),
11130 swapInH.getValue(1) };
11131 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
11132 MachineMemOperand *MMO = cast<AtomicSDNode>(N)->getMemOperand();
11133 unsigned Opcode = Regs64bit ? X86ISD::LCMPXCHG16_DAG :
11134 X86ISD::LCMPXCHG8_DAG;
11135 SDValue Result = DAG.getMemIntrinsicNode(Opcode, dl, Tys,
11137 SDValue cpOutL = DAG.getCopyFromReg(Result.getValue(0), dl,
11138 Regs64bit ? X86::RAX : X86::EAX,
11139 HalfT, Result.getValue(1));
11140 SDValue cpOutH = DAG.getCopyFromReg(cpOutL.getValue(1), dl,
11141 Regs64bit ? X86::RDX : X86::EDX,
11142 HalfT, cpOutL.getValue(2));
11143 SDValue OpsF[] = { cpOutL.getValue(0), cpOutH.getValue(0)};
11144 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, T, OpsF, 2));
11145 Results.push_back(cpOutH.getValue(1));
11148 case ISD::ATOMIC_LOAD_ADD:
11149 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMADD64_DAG);
11151 case ISD::ATOMIC_LOAD_AND:
11152 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMAND64_DAG);
11154 case ISD::ATOMIC_LOAD_NAND:
11155 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMNAND64_DAG);
11157 case ISD::ATOMIC_LOAD_OR:
11158 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMOR64_DAG);
11160 case ISD::ATOMIC_LOAD_SUB:
11161 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMSUB64_DAG);
11163 case ISD::ATOMIC_LOAD_XOR:
11164 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMXOR64_DAG);
11166 case ISD::ATOMIC_SWAP:
11167 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMSWAP64_DAG);
11169 case ISD::ATOMIC_LOAD:
11170 ReplaceATOMIC_LOAD(N, Results, DAG);
11174 const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
11176 default: return NULL;
11177 case X86ISD::BSF: return "X86ISD::BSF";
11178 case X86ISD::BSR: return "X86ISD::BSR";
11179 case X86ISD::SHLD: return "X86ISD::SHLD";
11180 case X86ISD::SHRD: return "X86ISD::SHRD";
11181 case X86ISD::FAND: return "X86ISD::FAND";
11182 case X86ISD::FOR: return "X86ISD::FOR";
11183 case X86ISD::FXOR: return "X86ISD::FXOR";
11184 case X86ISD::FSRL: return "X86ISD::FSRL";
11185 case X86ISD::FILD: return "X86ISD::FILD";
11186 case X86ISD::FILD_FLAG: return "X86ISD::FILD_FLAG";
11187 case X86ISD::FP_TO_INT16_IN_MEM: return "X86ISD::FP_TO_INT16_IN_MEM";
11188 case X86ISD::FP_TO_INT32_IN_MEM: return "X86ISD::FP_TO_INT32_IN_MEM";
11189 case X86ISD::FP_TO_INT64_IN_MEM: return "X86ISD::FP_TO_INT64_IN_MEM";
11190 case X86ISD::FLD: return "X86ISD::FLD";
11191 case X86ISD::FST: return "X86ISD::FST";
11192 case X86ISD::CALL: return "X86ISD::CALL";
11193 case X86ISD::RDTSC_DAG: return "X86ISD::RDTSC_DAG";
11194 case X86ISD::BT: return "X86ISD::BT";
11195 case X86ISD::CMP: return "X86ISD::CMP";
11196 case X86ISD::COMI: return "X86ISD::COMI";
11197 case X86ISD::UCOMI: return "X86ISD::UCOMI";
11198 case X86ISD::SETCC: return "X86ISD::SETCC";
11199 case X86ISD::SETCC_CARRY: return "X86ISD::SETCC_CARRY";
11200 case X86ISD::FSETCCsd: return "X86ISD::FSETCCsd";
11201 case X86ISD::FSETCCss: return "X86ISD::FSETCCss";
11202 case X86ISD::CMOV: return "X86ISD::CMOV";
11203 case X86ISD::BRCOND: return "X86ISD::BRCOND";
11204 case X86ISD::RET_FLAG: return "X86ISD::RET_FLAG";
11205 case X86ISD::REP_STOS: return "X86ISD::REP_STOS";
11206 case X86ISD::REP_MOVS: return "X86ISD::REP_MOVS";
11207 case X86ISD::GlobalBaseReg: return "X86ISD::GlobalBaseReg";
11208 case X86ISD::Wrapper: return "X86ISD::Wrapper";
11209 case X86ISD::WrapperRIP: return "X86ISD::WrapperRIP";
11210 case X86ISD::PEXTRB: return "X86ISD::PEXTRB";
11211 case X86ISD::PEXTRW: return "X86ISD::PEXTRW";
11212 case X86ISD::INSERTPS: return "X86ISD::INSERTPS";
11213 case X86ISD::PINSRB: return "X86ISD::PINSRB";
11214 case X86ISD::PINSRW: return "X86ISD::PINSRW";
11215 case X86ISD::PSHUFB: return "X86ISD::PSHUFB";
11216 case X86ISD::ANDNP: return "X86ISD::ANDNP";
11217 case X86ISD::PSIGN: return "X86ISD::PSIGN";
11218 case X86ISD::BLENDV: return "X86ISD::BLENDV";
11219 case X86ISD::BLENDPW: return "X86ISD::BLENDPW";
11220 case X86ISD::BLENDPS: return "X86ISD::BLENDPS";
11221 case X86ISD::BLENDPD: return "X86ISD::BLENDPD";
11222 case X86ISD::HADD: return "X86ISD::HADD";
11223 case X86ISD::HSUB: return "X86ISD::HSUB";
11224 case X86ISD::FHADD: return "X86ISD::FHADD";
11225 case X86ISD::FHSUB: return "X86ISD::FHSUB";
11226 case X86ISD::FMAX: return "X86ISD::FMAX";
11227 case X86ISD::FMIN: return "X86ISD::FMIN";
11228 case X86ISD::FRSQRT: return "X86ISD::FRSQRT";
11229 case X86ISD::FRCP: return "X86ISD::FRCP";
11230 case X86ISD::TLSADDR: return "X86ISD::TLSADDR";
11231 case X86ISD::TLSBASEADDR: return "X86ISD::TLSBASEADDR";
11232 case X86ISD::TLSCALL: return "X86ISD::TLSCALL";
11233 case X86ISD::EH_RETURN: return "X86ISD::EH_RETURN";
11234 case X86ISD::TC_RETURN: return "X86ISD::TC_RETURN";
11235 case X86ISD::FNSTCW16m: return "X86ISD::FNSTCW16m";
11236 case X86ISD::FNSTSW16r: return "X86ISD::FNSTSW16r";
11237 case X86ISD::LCMPXCHG_DAG: return "X86ISD::LCMPXCHG_DAG";
11238 case X86ISD::LCMPXCHG8_DAG: return "X86ISD::LCMPXCHG8_DAG";
11239 case X86ISD::ATOMADD64_DAG: return "X86ISD::ATOMADD64_DAG";
11240 case X86ISD::ATOMSUB64_DAG: return "X86ISD::ATOMSUB64_DAG";
11241 case X86ISD::ATOMOR64_DAG: return "X86ISD::ATOMOR64_DAG";
11242 case X86ISD::ATOMXOR64_DAG: return "X86ISD::ATOMXOR64_DAG";
11243 case X86ISD::ATOMAND64_DAG: return "X86ISD::ATOMAND64_DAG";
11244 case X86ISD::ATOMNAND64_DAG: return "X86ISD::ATOMNAND64_DAG";
11245 case X86ISD::VZEXT_MOVL: return "X86ISD::VZEXT_MOVL";
11246 case X86ISD::VZEXT_LOAD: return "X86ISD::VZEXT_LOAD";
11247 case X86ISD::VSHLDQ: return "X86ISD::VSHLDQ";
11248 case X86ISD::VSRLDQ: return "X86ISD::VSRLDQ";
11249 case X86ISD::VSHL: return "X86ISD::VSHL";
11250 case X86ISD::VSRL: return "X86ISD::VSRL";
11251 case X86ISD::VSRA: return "X86ISD::VSRA";
11252 case X86ISD::VSHLI: return "X86ISD::VSHLI";
11253 case X86ISD::VSRLI: return "X86ISD::VSRLI";
11254 case X86ISD::VSRAI: return "X86ISD::VSRAI";
11255 case X86ISD::CMPP: return "X86ISD::CMPP";
11256 case X86ISD::PCMPEQ: return "X86ISD::PCMPEQ";
11257 case X86ISD::PCMPGT: return "X86ISD::PCMPGT";
11258 case X86ISD::ADD: return "X86ISD::ADD";
11259 case X86ISD::SUB: return "X86ISD::SUB";
11260 case X86ISD::ADC: return "X86ISD::ADC";
11261 case X86ISD::SBB: return "X86ISD::SBB";
11262 case X86ISD::SMUL: return "X86ISD::SMUL";
11263 case X86ISD::UMUL: return "X86ISD::UMUL";
11264 case X86ISD::INC: return "X86ISD::INC";
11265 case X86ISD::DEC: return "X86ISD::DEC";
11266 case X86ISD::OR: return "X86ISD::OR";
11267 case X86ISD::XOR: return "X86ISD::XOR";
11268 case X86ISD::AND: return "X86ISD::AND";
11269 case X86ISD::ANDN: return "X86ISD::ANDN";
11270 case X86ISD::BLSI: return "X86ISD::BLSI";
11271 case X86ISD::BLSMSK: return "X86ISD::BLSMSK";
11272 case X86ISD::BLSR: return "X86ISD::BLSR";
11273 case X86ISD::MUL_IMM: return "X86ISD::MUL_IMM";
11274 case X86ISD::PTEST: return "X86ISD::PTEST";
11275 case X86ISD::TESTP: return "X86ISD::TESTP";
11276 case X86ISD::PALIGN: return "X86ISD::PALIGN";
11277 case X86ISD::PSHUFD: return "X86ISD::PSHUFD";
11278 case X86ISD::PSHUFHW: return "X86ISD::PSHUFHW";
11279 case X86ISD::PSHUFLW: return "X86ISD::PSHUFLW";
11280 case X86ISD::SHUFP: return "X86ISD::SHUFP";
11281 case X86ISD::MOVLHPS: return "X86ISD::MOVLHPS";
11282 case X86ISD::MOVLHPD: return "X86ISD::MOVLHPD";
11283 case X86ISD::MOVHLPS: return "X86ISD::MOVHLPS";
11284 case X86ISD::MOVLPS: return "X86ISD::MOVLPS";
11285 case X86ISD::MOVLPD: return "X86ISD::MOVLPD";
11286 case X86ISD::MOVDDUP: return "X86ISD::MOVDDUP";
11287 case X86ISD::MOVSHDUP: return "X86ISD::MOVSHDUP";
11288 case X86ISD::MOVSLDUP: return "X86ISD::MOVSLDUP";
11289 case X86ISD::MOVSD: return "X86ISD::MOVSD";
11290 case X86ISD::MOVSS: return "X86ISD::MOVSS";
11291 case X86ISD::UNPCKL: return "X86ISD::UNPCKL";
11292 case X86ISD::UNPCKH: return "X86ISD::UNPCKH";
11293 case X86ISD::VBROADCAST: return "X86ISD::VBROADCAST";
11294 case X86ISD::VPERMILP: return "X86ISD::VPERMILP";
11295 case X86ISD::VPERM2X128: return "X86ISD::VPERM2X128";
11296 case X86ISD::VPERMV: return "X86ISD::VPERMV";
11297 case X86ISD::VPERMI: return "X86ISD::VPERMI";
11298 case X86ISD::PMULUDQ: return "X86ISD::PMULUDQ";
11299 case X86ISD::VASTART_SAVE_XMM_REGS: return "X86ISD::VASTART_SAVE_XMM_REGS";
11300 case X86ISD::VAARG_64: return "X86ISD::VAARG_64";
11301 case X86ISD::WIN_ALLOCA: return "X86ISD::WIN_ALLOCA";
11302 case X86ISD::MEMBARRIER: return "X86ISD::MEMBARRIER";
11303 case X86ISD::SEG_ALLOCA: return "X86ISD::SEG_ALLOCA";
11304 case X86ISD::WIN_FTOL: return "X86ISD::WIN_FTOL";
11305 case X86ISD::SAHF: return "X86ISD::SAHF";
11306 case X86ISD::RDRAND: return "X86ISD::RDRAND";
11307 case X86ISD::FMADD: return "X86ISD::FMADD";
11308 case X86ISD::FMSUB: return "X86ISD::FMSUB";
11309 case X86ISD::FNMADD: return "X86ISD::FNMADD";
11310 case X86ISD::FNMSUB: return "X86ISD::FNMSUB";
11311 case X86ISD::FMADDSUB: return "X86ISD::FMADDSUB";
11312 case X86ISD::FMSUBADD: return "X86ISD::FMSUBADD";
11316 // isLegalAddressingMode - Return true if the addressing mode represented
11317 // by AM is legal for this target, for a load/store of the specified type.
11318 bool X86TargetLowering::isLegalAddressingMode(const AddrMode &AM,
11320 // X86 supports extremely general addressing modes.
11321 CodeModel::Model M = getTargetMachine().getCodeModel();
11322 Reloc::Model R = getTargetMachine().getRelocationModel();
11324 // X86 allows a sign-extended 32-bit immediate field as a displacement.
11325 if (!X86::isOffsetSuitableForCodeModel(AM.BaseOffs, M, AM.BaseGV != NULL))
11330 Subtarget->ClassifyGlobalReference(AM.BaseGV, getTargetMachine());
11332 // If a reference to this global requires an extra load, we can't fold it.
11333 if (isGlobalStubReference(GVFlags))
11336 // If BaseGV requires a register for the PIC base, we cannot also have a
11337 // BaseReg specified.
11338 if (AM.HasBaseReg && isGlobalRelativeToPICBase(GVFlags))
11341 // If lower 4G is not available, then we must use rip-relative addressing.
11342 if ((M != CodeModel::Small || R != Reloc::Static) &&
11343 Subtarget->is64Bit() && (AM.BaseOffs || AM.Scale > 1))
11347 switch (AM.Scale) {
11353 // These scales always work.
11358 // These scales are formed with basereg+scalereg. Only accept if there is
11363 default: // Other stuff never works.
11371 bool X86TargetLowering::isTruncateFree(Type *Ty1, Type *Ty2) const {
11372 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
11374 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits();
11375 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits();
11376 if (NumBits1 <= NumBits2)
11381 bool X86TargetLowering::isLegalICmpImmediate(int64_t Imm) const {
11382 return Imm == (int32_t)Imm;
11385 bool X86TargetLowering::isLegalAddImmediate(int64_t Imm) const {
11386 // Can also use sub to handle negated immediates.
11387 return Imm == (int32_t)Imm;
11390 bool X86TargetLowering::isTruncateFree(EVT VT1, EVT VT2) const {
11391 if (!VT1.isInteger() || !VT2.isInteger())
11393 unsigned NumBits1 = VT1.getSizeInBits();
11394 unsigned NumBits2 = VT2.getSizeInBits();
11395 if (NumBits1 <= NumBits2)
11400 bool X86TargetLowering::isZExtFree(Type *Ty1, Type *Ty2) const {
11401 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
11402 return Ty1->isIntegerTy(32) && Ty2->isIntegerTy(64) && Subtarget->is64Bit();
11405 bool X86TargetLowering::isZExtFree(EVT VT1, EVT VT2) const {
11406 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
11407 return VT1 == MVT::i32 && VT2 == MVT::i64 && Subtarget->is64Bit();
11410 bool X86TargetLowering::isNarrowingProfitable(EVT VT1, EVT VT2) const {
11411 // i16 instructions are longer (0x66 prefix) and potentially slower.
11412 return !(VT1 == MVT::i32 && VT2 == MVT::i16);
11415 /// isShuffleMaskLegal - Targets can use this to indicate that they only
11416 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
11417 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
11418 /// are assumed to be legal.
11420 X86TargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M,
11422 // Very little shuffling can be done for 64-bit vectors right now.
11423 if (VT.getSizeInBits() == 64)
11426 // FIXME: pshufb, blends, shifts.
11427 return (VT.getVectorNumElements() == 2 ||
11428 ShuffleVectorSDNode::isSplatMask(&M[0], VT) ||
11429 isMOVLMask(M, VT) ||
11430 isSHUFPMask(M, VT, Subtarget->hasAVX()) ||
11431 isPSHUFDMask(M, VT) ||
11432 isPSHUFHWMask(M, VT, Subtarget->hasAVX2()) ||
11433 isPSHUFLWMask(M, VT, Subtarget->hasAVX2()) ||
11434 isPALIGNRMask(M, VT, Subtarget) ||
11435 isUNPCKLMask(M, VT, Subtarget->hasAVX2()) ||
11436 isUNPCKHMask(M, VT, Subtarget->hasAVX2()) ||
11437 isUNPCKL_v_undef_Mask(M, VT, Subtarget->hasAVX2()) ||
11438 isUNPCKH_v_undef_Mask(M, VT, Subtarget->hasAVX2()));
11442 X86TargetLowering::isVectorClearMaskLegal(const SmallVectorImpl<int> &Mask,
11444 unsigned NumElts = VT.getVectorNumElements();
11445 // FIXME: This collection of masks seems suspect.
11448 if (NumElts == 4 && VT.is128BitVector()) {
11449 return (isMOVLMask(Mask, VT) ||
11450 isCommutedMOVLMask(Mask, VT, true) ||
11451 isSHUFPMask(Mask, VT, Subtarget->hasAVX()) ||
11452 isSHUFPMask(Mask, VT, Subtarget->hasAVX(), /* Commuted */ true));
11457 //===----------------------------------------------------------------------===//
11458 // X86 Scheduler Hooks
11459 //===----------------------------------------------------------------------===//
11461 // private utility function
11462 MachineBasicBlock *
11463 X86TargetLowering::EmitAtomicBitwiseWithCustomInserter(MachineInstr *bInstr,
11464 MachineBasicBlock *MBB,
11471 const TargetRegisterClass *RC,
11472 bool Invert) const {
11473 // For the atomic bitwise operator, we generate
11476 // ld t1 = [bitinstr.addr]
11477 // op t2 = t1, [bitinstr.val]
11478 // not t3 = t2 (if Invert)
11480 // lcs dest = [bitinstr.addr], t3 [EAX is implicit]
11482 // fallthrough -->nextMBB
11483 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
11484 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
11485 MachineFunction::iterator MBBIter = MBB;
11488 /// First build the CFG
11489 MachineFunction *F = MBB->getParent();
11490 MachineBasicBlock *thisMBB = MBB;
11491 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB);
11492 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB);
11493 F->insert(MBBIter, newMBB);
11494 F->insert(MBBIter, nextMBB);
11496 // Transfer the remainder of thisMBB and its successor edges to nextMBB.
11497 nextMBB->splice(nextMBB->begin(), thisMBB,
11498 llvm::next(MachineBasicBlock::iterator(bInstr)),
11500 nextMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
11502 // Update thisMBB to fall through to newMBB
11503 thisMBB->addSuccessor(newMBB);
11505 // newMBB jumps to itself and fall through to nextMBB
11506 newMBB->addSuccessor(nextMBB);
11507 newMBB->addSuccessor(newMBB);
11509 // Insert instructions into newMBB based on incoming instruction
11510 assert(bInstr->getNumOperands() < X86::AddrNumOperands + 4 &&
11511 "unexpected number of operands");
11512 DebugLoc dl = bInstr->getDebugLoc();
11513 MachineOperand& destOper = bInstr->getOperand(0);
11514 MachineOperand* argOpers[2 + X86::AddrNumOperands];
11515 int numArgs = bInstr->getNumOperands() - 1;
11516 for (int i=0; i < numArgs; ++i)
11517 argOpers[i] = &bInstr->getOperand(i+1);
11519 // x86 address has 4 operands: base, index, scale, and displacement
11520 int lastAddrIndx = X86::AddrNumOperands - 1; // [0,3]
11521 int valArgIndx = lastAddrIndx + 1;
11523 unsigned t1 = F->getRegInfo().createVirtualRegister(RC);
11524 MachineInstrBuilder MIB = BuildMI(newMBB, dl, TII->get(LoadOpc), t1);
11525 for (int i=0; i <= lastAddrIndx; ++i)
11526 (*MIB).addOperand(*argOpers[i]);
11528 unsigned t2 = F->getRegInfo().createVirtualRegister(RC);
11529 assert((argOpers[valArgIndx]->isReg() ||
11530 argOpers[valArgIndx]->isImm()) &&
11531 "invalid operand");
11532 if (argOpers[valArgIndx]->isReg())
11533 MIB = BuildMI(newMBB, dl, TII->get(regOpc), t2);
11535 MIB = BuildMI(newMBB, dl, TII->get(immOpc), t2);
11537 (*MIB).addOperand(*argOpers[valArgIndx]);
11539 unsigned t3 = F->getRegInfo().createVirtualRegister(RC);
11541 MIB = BuildMI(newMBB, dl, TII->get(notOpc), t3).addReg(t2);
11546 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), EAXreg);
11549 MIB = BuildMI(newMBB, dl, TII->get(CXchgOpc));
11550 for (int i=0; i <= lastAddrIndx; ++i)
11551 (*MIB).addOperand(*argOpers[i]);
11553 assert(bInstr->hasOneMemOperand() && "Unexpected number of memoperand");
11554 (*MIB).setMemRefs(bInstr->memoperands_begin(),
11555 bInstr->memoperands_end());
11557 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), destOper.getReg());
11558 MIB.addReg(EAXreg);
11561 BuildMI(newMBB, dl, TII->get(X86::JNE_4)).addMBB(newMBB);
11563 bInstr->eraseFromParent(); // The pseudo instruction is gone now.
11567 // private utility function: 64 bit atomics on 32 bit host.
11568 MachineBasicBlock *
11569 X86TargetLowering::EmitAtomicBit6432WithCustomInserter(MachineInstr *bInstr,
11570 MachineBasicBlock *MBB,
11575 bool Invert) const {
11576 // For the atomic bitwise operator, we generate
11577 // thisMBB (instructions are in pairs, except cmpxchg8b)
11578 // ld t1,t2 = [bitinstr.addr]
11580 // out1, out2 = phi (thisMBB, t1/t2) (newMBB, t3/t4)
11581 // op t5, t6 <- out1, out2, [bitinstr.val]
11582 // (for SWAP, substitute: mov t5, t6 <- [bitinstr.val])
11583 // neg t7, t8 < t5, t6 (if Invert)
11584 // mov ECX, EBX <- t5, t6
11585 // mov EAX, EDX <- t1, t2
11586 // cmpxchg8b [bitinstr.addr] [EAX, EDX, EBX, ECX implicit]
11587 // mov t3, t4 <- EAX, EDX
11589 // result in out1, out2
11590 // fallthrough -->nextMBB
11592 const TargetRegisterClass *RC = &X86::GR32RegClass;
11593 const unsigned LoadOpc = X86::MOV32rm;
11594 const unsigned NotOpc = X86::NOT32r;
11595 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
11596 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
11597 MachineFunction::iterator MBBIter = MBB;
11600 /// First build the CFG
11601 MachineFunction *F = MBB->getParent();
11602 MachineBasicBlock *thisMBB = MBB;
11603 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB);
11604 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB);
11605 F->insert(MBBIter, newMBB);
11606 F->insert(MBBIter, nextMBB);
11608 // Transfer the remainder of thisMBB and its successor edges to nextMBB.
11609 nextMBB->splice(nextMBB->begin(), thisMBB,
11610 llvm::next(MachineBasicBlock::iterator(bInstr)),
11612 nextMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
11614 // Update thisMBB to fall through to newMBB
11615 thisMBB->addSuccessor(newMBB);
11617 // newMBB jumps to itself and fall through to nextMBB
11618 newMBB->addSuccessor(nextMBB);
11619 newMBB->addSuccessor(newMBB);
11621 DebugLoc dl = bInstr->getDebugLoc();
11622 // Insert instructions into newMBB based on incoming instruction
11623 // There are 8 "real" operands plus 9 implicit def/uses, ignored here.
11624 assert(bInstr->getNumOperands() < X86::AddrNumOperands + 14 &&
11625 "unexpected number of operands");
11626 MachineOperand& dest1Oper = bInstr->getOperand(0);
11627 MachineOperand& dest2Oper = bInstr->getOperand(1);
11628 MachineOperand* argOpers[2 + X86::AddrNumOperands];
11629 for (int i=0; i < 2 + X86::AddrNumOperands; ++i) {
11630 argOpers[i] = &bInstr->getOperand(i+2);
11632 // We use some of the operands multiple times, so conservatively just
11633 // clear any kill flags that might be present.
11634 if (argOpers[i]->isReg() && argOpers[i]->isUse())
11635 argOpers[i]->setIsKill(false);
11638 // x86 address has 5 operands: base, index, scale, displacement, and segment.
11639 int lastAddrIndx = X86::AddrNumOperands - 1; // [0,3]
11641 unsigned t1 = F->getRegInfo().createVirtualRegister(RC);
11642 MachineInstrBuilder MIB = BuildMI(thisMBB, dl, TII->get(LoadOpc), t1);
11643 for (int i=0; i <= lastAddrIndx; ++i)
11644 (*MIB).addOperand(*argOpers[i]);
11645 unsigned t2 = F->getRegInfo().createVirtualRegister(RC);
11646 MIB = BuildMI(thisMBB, dl, TII->get(LoadOpc), t2);
11647 // add 4 to displacement.
11648 for (int i=0; i <= lastAddrIndx-2; ++i)
11649 (*MIB).addOperand(*argOpers[i]);
11650 MachineOperand newOp3 = *(argOpers[3]);
11651 if (newOp3.isImm())
11652 newOp3.setImm(newOp3.getImm()+4);
11654 newOp3.setOffset(newOp3.getOffset()+4);
11655 (*MIB).addOperand(newOp3);
11656 (*MIB).addOperand(*argOpers[lastAddrIndx]);
11658 // t3/4 are defined later, at the bottom of the loop
11659 unsigned t3 = F->getRegInfo().createVirtualRegister(RC);
11660 unsigned t4 = F->getRegInfo().createVirtualRegister(RC);
11661 BuildMI(newMBB, dl, TII->get(X86::PHI), dest1Oper.getReg())
11662 .addReg(t1).addMBB(thisMBB).addReg(t3).addMBB(newMBB);
11663 BuildMI(newMBB, dl, TII->get(X86::PHI), dest2Oper.getReg())
11664 .addReg(t2).addMBB(thisMBB).addReg(t4).addMBB(newMBB);
11666 // The subsequent operations should be using the destination registers of
11667 // the PHI instructions.
11668 t1 = dest1Oper.getReg();
11669 t2 = dest2Oper.getReg();
11671 int valArgIndx = lastAddrIndx + 1;
11672 assert((argOpers[valArgIndx]->isReg() ||
11673 argOpers[valArgIndx]->isImm()) &&
11674 "invalid operand");
11675 unsigned t5 = F->getRegInfo().createVirtualRegister(RC);
11676 unsigned t6 = F->getRegInfo().createVirtualRegister(RC);
11677 if (argOpers[valArgIndx]->isReg())
11678 MIB = BuildMI(newMBB, dl, TII->get(regOpcL), t5);
11680 MIB = BuildMI(newMBB, dl, TII->get(immOpcL), t5);
11681 if (regOpcL != X86::MOV32rr)
11683 (*MIB).addOperand(*argOpers[valArgIndx]);
11684 assert(argOpers[valArgIndx + 1]->isReg() ==
11685 argOpers[valArgIndx]->isReg());
11686 assert(argOpers[valArgIndx + 1]->isImm() ==
11687 argOpers[valArgIndx]->isImm());
11688 if (argOpers[valArgIndx + 1]->isReg())
11689 MIB = BuildMI(newMBB, dl, TII->get(regOpcH), t6);
11691 MIB = BuildMI(newMBB, dl, TII->get(immOpcH), t6);
11692 if (regOpcH != X86::MOV32rr)
11694 (*MIB).addOperand(*argOpers[valArgIndx + 1]);
11698 t7 = F->getRegInfo().createVirtualRegister(RC);
11699 t8 = F->getRegInfo().createVirtualRegister(RC);
11700 MIB = BuildMI(newMBB, dl, TII->get(NotOpc), t7).addReg(t5);
11701 MIB = BuildMI(newMBB, dl, TII->get(NotOpc), t8).addReg(t6);
11707 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::EAX);
11709 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::EDX);
11712 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::EBX);
11714 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::ECX);
11717 MIB = BuildMI(newMBB, dl, TII->get(X86::LCMPXCHG8B));
11718 for (int i=0; i <= lastAddrIndx; ++i)
11719 (*MIB).addOperand(*argOpers[i]);
11721 assert(bInstr->hasOneMemOperand() && "Unexpected number of memoperand");
11722 (*MIB).setMemRefs(bInstr->memoperands_begin(),
11723 bInstr->memoperands_end());
11725 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), t3);
11726 MIB.addReg(X86::EAX);
11727 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), t4);
11728 MIB.addReg(X86::EDX);
11731 BuildMI(newMBB, dl, TII->get(X86::JNE_4)).addMBB(newMBB);
11733 bInstr->eraseFromParent(); // The pseudo instruction is gone now.
11737 // private utility function
11738 MachineBasicBlock *
11739 X86TargetLowering::EmitAtomicMinMaxWithCustomInserter(MachineInstr *mInstr,
11740 MachineBasicBlock *MBB,
11741 unsigned cmovOpc) const {
11742 // For the atomic min/max operator, we generate
11745 // ld t1 = [min/max.addr]
11746 // mov t2 = [min/max.val]
11748 // cmov[cond] t2 = t1
11750 // lcs dest = [bitinstr.addr], t2 [EAX is implicit]
11752 // fallthrough -->nextMBB
11754 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
11755 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
11756 MachineFunction::iterator MBBIter = MBB;
11759 /// First build the CFG
11760 MachineFunction *F = MBB->getParent();
11761 MachineBasicBlock *thisMBB = MBB;
11762 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB);
11763 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB);
11764 F->insert(MBBIter, newMBB);
11765 F->insert(MBBIter, nextMBB);
11767 // Transfer the remainder of thisMBB and its successor edges to nextMBB.
11768 nextMBB->splice(nextMBB->begin(), thisMBB,
11769 llvm::next(MachineBasicBlock::iterator(mInstr)),
11771 nextMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
11773 // Update thisMBB to fall through to newMBB
11774 thisMBB->addSuccessor(newMBB);
11776 // newMBB jumps to newMBB and fall through to nextMBB
11777 newMBB->addSuccessor(nextMBB);
11778 newMBB->addSuccessor(newMBB);
11780 DebugLoc dl = mInstr->getDebugLoc();
11781 // Insert instructions into newMBB based on incoming instruction
11782 assert(mInstr->getNumOperands() < X86::AddrNumOperands + 4 &&
11783 "unexpected number of operands");
11784 MachineOperand& destOper = mInstr->getOperand(0);
11785 MachineOperand* argOpers[2 + X86::AddrNumOperands];
11786 int numArgs = mInstr->getNumOperands() - 1;
11787 for (int i=0; i < numArgs; ++i)
11788 argOpers[i] = &mInstr->getOperand(i+1);
11790 // x86 address has 4 operands: base, index, scale, and displacement
11791 int lastAddrIndx = X86::AddrNumOperands - 1; // [0,3]
11792 int valArgIndx = lastAddrIndx + 1;
11794 unsigned t1 = F->getRegInfo().createVirtualRegister(&X86::GR32RegClass);
11795 MachineInstrBuilder MIB = BuildMI(newMBB, dl, TII->get(X86::MOV32rm), t1);
11796 for (int i=0; i <= lastAddrIndx; ++i)
11797 (*MIB).addOperand(*argOpers[i]);
11799 // We only support register and immediate values
11800 assert((argOpers[valArgIndx]->isReg() ||
11801 argOpers[valArgIndx]->isImm()) &&
11802 "invalid operand");
11804 unsigned t2 = F->getRegInfo().createVirtualRegister(&X86::GR32RegClass);
11805 if (argOpers[valArgIndx]->isReg())
11806 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), t2);
11808 MIB = BuildMI(newMBB, dl, TII->get(X86::MOV32rr), t2);
11809 (*MIB).addOperand(*argOpers[valArgIndx]);
11811 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::EAX);
11814 MIB = BuildMI(newMBB, dl, TII->get(X86::CMP32rr));
11819 unsigned t3 = F->getRegInfo().createVirtualRegister(&X86::GR32RegClass);
11820 MIB = BuildMI(newMBB, dl, TII->get(cmovOpc),t3);
11824 // Cmp and exchange if none has modified the memory location
11825 MIB = BuildMI(newMBB, dl, TII->get(X86::LCMPXCHG32));
11826 for (int i=0; i <= lastAddrIndx; ++i)
11827 (*MIB).addOperand(*argOpers[i]);
11829 assert(mInstr->hasOneMemOperand() && "Unexpected number of memoperand");
11830 (*MIB).setMemRefs(mInstr->memoperands_begin(),
11831 mInstr->memoperands_end());
11833 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), destOper.getReg());
11834 MIB.addReg(X86::EAX);
11837 BuildMI(newMBB, dl, TII->get(X86::JNE_4)).addMBB(newMBB);
11839 mInstr->eraseFromParent(); // The pseudo instruction is gone now.
11843 // FIXME: When we get size specific XMM0 registers, i.e. XMM0_V16I8
11844 // or XMM0_V32I8 in AVX all of this code can be replaced with that
11845 // in the .td file.
11846 MachineBasicBlock *
11847 X86TargetLowering::EmitPCMP(MachineInstr *MI, MachineBasicBlock *BB,
11848 unsigned numArgs, bool memArg) const {
11849 assert(Subtarget->hasSSE42() &&
11850 "Target must have SSE4.2 or AVX features enabled");
11852 DebugLoc dl = MI->getDebugLoc();
11853 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
11855 if (!Subtarget->hasAVX()) {
11857 Opc = numArgs == 3 ? X86::PCMPISTRM128rm : X86::PCMPESTRM128rm;
11859 Opc = numArgs == 3 ? X86::PCMPISTRM128rr : X86::PCMPESTRM128rr;
11862 Opc = numArgs == 3 ? X86::VPCMPISTRM128rm : X86::VPCMPESTRM128rm;
11864 Opc = numArgs == 3 ? X86::VPCMPISTRM128rr : X86::VPCMPESTRM128rr;
11867 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(Opc));
11868 for (unsigned i = 0; i < numArgs; ++i) {
11869 MachineOperand &Op = MI->getOperand(i+1);
11870 if (!(Op.isReg() && Op.isImplicit()))
11871 MIB.addOperand(Op);
11873 BuildMI(*BB, MI, dl,
11874 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
11875 .addReg(X86::XMM0);
11877 MI->eraseFromParent();
11881 MachineBasicBlock *
11882 X86TargetLowering::EmitMonitor(MachineInstr *MI, MachineBasicBlock *BB) const {
11883 DebugLoc dl = MI->getDebugLoc();
11884 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
11886 // Address into RAX/EAX, other two args into ECX, EDX.
11887 unsigned MemOpc = Subtarget->is64Bit() ? X86::LEA64r : X86::LEA32r;
11888 unsigned MemReg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
11889 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(MemOpc), MemReg);
11890 for (int i = 0; i < X86::AddrNumOperands; ++i)
11891 MIB.addOperand(MI->getOperand(i));
11893 unsigned ValOps = X86::AddrNumOperands;
11894 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::ECX)
11895 .addReg(MI->getOperand(ValOps).getReg());
11896 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::EDX)
11897 .addReg(MI->getOperand(ValOps+1).getReg());
11899 // The instruction doesn't actually take any operands though.
11900 BuildMI(*BB, MI, dl, TII->get(X86::MONITORrrr));
11902 MI->eraseFromParent(); // The pseudo is gone now.
11906 MachineBasicBlock *
11907 X86TargetLowering::EmitVAARG64WithCustomInserter(
11909 MachineBasicBlock *MBB) const {
11910 // Emit va_arg instruction on X86-64.
11912 // Operands to this pseudo-instruction:
11913 // 0 ) Output : destination address (reg)
11914 // 1-5) Input : va_list address (addr, i64mem)
11915 // 6 ) ArgSize : Size (in bytes) of vararg type
11916 // 7 ) ArgMode : 0=overflow only, 1=use gp_offset, 2=use fp_offset
11917 // 8 ) Align : Alignment of type
11918 // 9 ) EFLAGS (implicit-def)
11920 assert(MI->getNumOperands() == 10 && "VAARG_64 should have 10 operands!");
11921 assert(X86::AddrNumOperands == 5 && "VAARG_64 assumes 5 address operands");
11923 unsigned DestReg = MI->getOperand(0).getReg();
11924 MachineOperand &Base = MI->getOperand(1);
11925 MachineOperand &Scale = MI->getOperand(2);
11926 MachineOperand &Index = MI->getOperand(3);
11927 MachineOperand &Disp = MI->getOperand(4);
11928 MachineOperand &Segment = MI->getOperand(5);
11929 unsigned ArgSize = MI->getOperand(6).getImm();
11930 unsigned ArgMode = MI->getOperand(7).getImm();
11931 unsigned Align = MI->getOperand(8).getImm();
11933 // Memory Reference
11934 assert(MI->hasOneMemOperand() && "Expected VAARG_64 to have one memoperand");
11935 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
11936 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
11938 // Machine Information
11939 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
11940 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
11941 const TargetRegisterClass *AddrRegClass = getRegClassFor(MVT::i64);
11942 const TargetRegisterClass *OffsetRegClass = getRegClassFor(MVT::i32);
11943 DebugLoc DL = MI->getDebugLoc();
11945 // struct va_list {
11948 // i64 overflow_area (address)
11949 // i64 reg_save_area (address)
11951 // sizeof(va_list) = 24
11952 // alignment(va_list) = 8
11954 unsigned TotalNumIntRegs = 6;
11955 unsigned TotalNumXMMRegs = 8;
11956 bool UseGPOffset = (ArgMode == 1);
11957 bool UseFPOffset = (ArgMode == 2);
11958 unsigned MaxOffset = TotalNumIntRegs * 8 +
11959 (UseFPOffset ? TotalNumXMMRegs * 16 : 0);
11961 /* Align ArgSize to a multiple of 8 */
11962 unsigned ArgSizeA8 = (ArgSize + 7) & ~7;
11963 bool NeedsAlign = (Align > 8);
11965 MachineBasicBlock *thisMBB = MBB;
11966 MachineBasicBlock *overflowMBB;
11967 MachineBasicBlock *offsetMBB;
11968 MachineBasicBlock *endMBB;
11970 unsigned OffsetDestReg = 0; // Argument address computed by offsetMBB
11971 unsigned OverflowDestReg = 0; // Argument address computed by overflowMBB
11972 unsigned OffsetReg = 0;
11974 if (!UseGPOffset && !UseFPOffset) {
11975 // If we only pull from the overflow region, we don't create a branch.
11976 // We don't need to alter control flow.
11977 OffsetDestReg = 0; // unused
11978 OverflowDestReg = DestReg;
11981 overflowMBB = thisMBB;
11984 // First emit code to check if gp_offset (or fp_offset) is below the bound.
11985 // If so, pull the argument from reg_save_area. (branch to offsetMBB)
11986 // If not, pull from overflow_area. (branch to overflowMBB)
11991 // offsetMBB overflowMBB
11996 // Registers for the PHI in endMBB
11997 OffsetDestReg = MRI.createVirtualRegister(AddrRegClass);
11998 OverflowDestReg = MRI.createVirtualRegister(AddrRegClass);
12000 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
12001 MachineFunction *MF = MBB->getParent();
12002 overflowMBB = MF->CreateMachineBasicBlock(LLVM_BB);
12003 offsetMBB = MF->CreateMachineBasicBlock(LLVM_BB);
12004 endMBB = MF->CreateMachineBasicBlock(LLVM_BB);
12006 MachineFunction::iterator MBBIter = MBB;
12009 // Insert the new basic blocks
12010 MF->insert(MBBIter, offsetMBB);
12011 MF->insert(MBBIter, overflowMBB);
12012 MF->insert(MBBIter, endMBB);
12014 // Transfer the remainder of MBB and its successor edges to endMBB.
12015 endMBB->splice(endMBB->begin(), thisMBB,
12016 llvm::next(MachineBasicBlock::iterator(MI)),
12018 endMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
12020 // Make offsetMBB and overflowMBB successors of thisMBB
12021 thisMBB->addSuccessor(offsetMBB);
12022 thisMBB->addSuccessor(overflowMBB);
12024 // endMBB is a successor of both offsetMBB and overflowMBB
12025 offsetMBB->addSuccessor(endMBB);
12026 overflowMBB->addSuccessor(endMBB);
12028 // Load the offset value into a register
12029 OffsetReg = MRI.createVirtualRegister(OffsetRegClass);
12030 BuildMI(thisMBB, DL, TII->get(X86::MOV32rm), OffsetReg)
12034 .addDisp(Disp, UseFPOffset ? 4 : 0)
12035 .addOperand(Segment)
12036 .setMemRefs(MMOBegin, MMOEnd);
12038 // Check if there is enough room left to pull this argument.
12039 BuildMI(thisMBB, DL, TII->get(X86::CMP32ri))
12041 .addImm(MaxOffset + 8 - ArgSizeA8);
12043 // Branch to "overflowMBB" if offset >= max
12044 // Fall through to "offsetMBB" otherwise
12045 BuildMI(thisMBB, DL, TII->get(X86::GetCondBranchFromCond(X86::COND_AE)))
12046 .addMBB(overflowMBB);
12049 // In offsetMBB, emit code to use the reg_save_area.
12051 assert(OffsetReg != 0);
12053 // Read the reg_save_area address.
12054 unsigned RegSaveReg = MRI.createVirtualRegister(AddrRegClass);
12055 BuildMI(offsetMBB, DL, TII->get(X86::MOV64rm), RegSaveReg)
12060 .addOperand(Segment)
12061 .setMemRefs(MMOBegin, MMOEnd);
12063 // Zero-extend the offset
12064 unsigned OffsetReg64 = MRI.createVirtualRegister(AddrRegClass);
12065 BuildMI(offsetMBB, DL, TII->get(X86::SUBREG_TO_REG), OffsetReg64)
12068 .addImm(X86::sub_32bit);
12070 // Add the offset to the reg_save_area to get the final address.
12071 BuildMI(offsetMBB, DL, TII->get(X86::ADD64rr), OffsetDestReg)
12072 .addReg(OffsetReg64)
12073 .addReg(RegSaveReg);
12075 // Compute the offset for the next argument
12076 unsigned NextOffsetReg = MRI.createVirtualRegister(OffsetRegClass);
12077 BuildMI(offsetMBB, DL, TII->get(X86::ADD32ri), NextOffsetReg)
12079 .addImm(UseFPOffset ? 16 : 8);
12081 // Store it back into the va_list.
12082 BuildMI(offsetMBB, DL, TII->get(X86::MOV32mr))
12086 .addDisp(Disp, UseFPOffset ? 4 : 0)
12087 .addOperand(Segment)
12088 .addReg(NextOffsetReg)
12089 .setMemRefs(MMOBegin, MMOEnd);
12092 BuildMI(offsetMBB, DL, TII->get(X86::JMP_4))
12097 // Emit code to use overflow area
12100 // Load the overflow_area address into a register.
12101 unsigned OverflowAddrReg = MRI.createVirtualRegister(AddrRegClass);
12102 BuildMI(overflowMBB, DL, TII->get(X86::MOV64rm), OverflowAddrReg)
12107 .addOperand(Segment)
12108 .setMemRefs(MMOBegin, MMOEnd);
12110 // If we need to align it, do so. Otherwise, just copy the address
12111 // to OverflowDestReg.
12113 // Align the overflow address
12114 assert((Align & (Align-1)) == 0 && "Alignment must be a power of 2");
12115 unsigned TmpReg = MRI.createVirtualRegister(AddrRegClass);
12117 // aligned_addr = (addr + (align-1)) & ~(align-1)
12118 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), TmpReg)
12119 .addReg(OverflowAddrReg)
12122 BuildMI(overflowMBB, DL, TII->get(X86::AND64ri32), OverflowDestReg)
12124 .addImm(~(uint64_t)(Align-1));
12126 BuildMI(overflowMBB, DL, TII->get(TargetOpcode::COPY), OverflowDestReg)
12127 .addReg(OverflowAddrReg);
12130 // Compute the next overflow address after this argument.
12131 // (the overflow address should be kept 8-byte aligned)
12132 unsigned NextAddrReg = MRI.createVirtualRegister(AddrRegClass);
12133 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), NextAddrReg)
12134 .addReg(OverflowDestReg)
12135 .addImm(ArgSizeA8);
12137 // Store the new overflow address.
12138 BuildMI(overflowMBB, DL, TII->get(X86::MOV64mr))
12143 .addOperand(Segment)
12144 .addReg(NextAddrReg)
12145 .setMemRefs(MMOBegin, MMOEnd);
12147 // If we branched, emit the PHI to the front of endMBB.
12149 BuildMI(*endMBB, endMBB->begin(), DL,
12150 TII->get(X86::PHI), DestReg)
12151 .addReg(OffsetDestReg).addMBB(offsetMBB)
12152 .addReg(OverflowDestReg).addMBB(overflowMBB);
12155 // Erase the pseudo instruction
12156 MI->eraseFromParent();
12161 MachineBasicBlock *
12162 X86TargetLowering::EmitVAStartSaveXMMRegsWithCustomInserter(
12164 MachineBasicBlock *MBB) const {
12165 // Emit code to save XMM registers to the stack. The ABI says that the
12166 // number of registers to save is given in %al, so it's theoretically
12167 // possible to do an indirect jump trick to avoid saving all of them,
12168 // however this code takes a simpler approach and just executes all
12169 // of the stores if %al is non-zero. It's less code, and it's probably
12170 // easier on the hardware branch predictor, and stores aren't all that
12171 // expensive anyway.
12173 // Create the new basic blocks. One block contains all the XMM stores,
12174 // and one block is the final destination regardless of whether any
12175 // stores were performed.
12176 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
12177 MachineFunction *F = MBB->getParent();
12178 MachineFunction::iterator MBBIter = MBB;
12180 MachineBasicBlock *XMMSaveMBB = F->CreateMachineBasicBlock(LLVM_BB);
12181 MachineBasicBlock *EndMBB = F->CreateMachineBasicBlock(LLVM_BB);
12182 F->insert(MBBIter, XMMSaveMBB);
12183 F->insert(MBBIter, EndMBB);
12185 // Transfer the remainder of MBB and its successor edges to EndMBB.
12186 EndMBB->splice(EndMBB->begin(), MBB,
12187 llvm::next(MachineBasicBlock::iterator(MI)),
12189 EndMBB->transferSuccessorsAndUpdatePHIs(MBB);
12191 // The original block will now fall through to the XMM save block.
12192 MBB->addSuccessor(XMMSaveMBB);
12193 // The XMMSaveMBB will fall through to the end block.
12194 XMMSaveMBB->addSuccessor(EndMBB);
12196 // Now add the instructions.
12197 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
12198 DebugLoc DL = MI->getDebugLoc();
12200 unsigned CountReg = MI->getOperand(0).getReg();
12201 int64_t RegSaveFrameIndex = MI->getOperand(1).getImm();
12202 int64_t VarArgsFPOffset = MI->getOperand(2).getImm();
12204 if (!Subtarget->isTargetWin64()) {
12205 // If %al is 0, branch around the XMM save block.
12206 BuildMI(MBB, DL, TII->get(X86::TEST8rr)).addReg(CountReg).addReg(CountReg);
12207 BuildMI(MBB, DL, TII->get(X86::JE_4)).addMBB(EndMBB);
12208 MBB->addSuccessor(EndMBB);
12211 unsigned MOVOpc = Subtarget->hasAVX() ? X86::VMOVAPSmr : X86::MOVAPSmr;
12212 // In the XMM save block, save all the XMM argument registers.
12213 for (int i = 3, e = MI->getNumOperands(); i != e; ++i) {
12214 int64_t Offset = (i - 3) * 16 + VarArgsFPOffset;
12215 MachineMemOperand *MMO =
12216 F->getMachineMemOperand(
12217 MachinePointerInfo::getFixedStack(RegSaveFrameIndex, Offset),
12218 MachineMemOperand::MOStore,
12219 /*Size=*/16, /*Align=*/16);
12220 BuildMI(XMMSaveMBB, DL, TII->get(MOVOpc))
12221 .addFrameIndex(RegSaveFrameIndex)
12222 .addImm(/*Scale=*/1)
12223 .addReg(/*IndexReg=*/0)
12224 .addImm(/*Disp=*/Offset)
12225 .addReg(/*Segment=*/0)
12226 .addReg(MI->getOperand(i).getReg())
12227 .addMemOperand(MMO);
12230 MI->eraseFromParent(); // The pseudo instruction is gone now.
12235 // The EFLAGS operand of SelectItr might be missing a kill marker
12236 // because there were multiple uses of EFLAGS, and ISel didn't know
12237 // which to mark. Figure out whether SelectItr should have had a
12238 // kill marker, and set it if it should. Returns the correct kill
12240 static bool checkAndUpdateEFLAGSKill(MachineBasicBlock::iterator SelectItr,
12241 MachineBasicBlock* BB,
12242 const TargetRegisterInfo* TRI) {
12243 // Scan forward through BB for a use/def of EFLAGS.
12244 MachineBasicBlock::iterator miI(llvm::next(SelectItr));
12245 for (MachineBasicBlock::iterator miE = BB->end(); miI != miE; ++miI) {
12246 const MachineInstr& mi = *miI;
12247 if (mi.readsRegister(X86::EFLAGS))
12249 if (mi.definesRegister(X86::EFLAGS))
12250 break; // Should have kill-flag - update below.
12253 // If we hit the end of the block, check whether EFLAGS is live into a
12255 if (miI == BB->end()) {
12256 for (MachineBasicBlock::succ_iterator sItr = BB->succ_begin(),
12257 sEnd = BB->succ_end();
12258 sItr != sEnd; ++sItr) {
12259 MachineBasicBlock* succ = *sItr;
12260 if (succ->isLiveIn(X86::EFLAGS))
12265 // We found a def, or hit the end of the basic block and EFLAGS wasn't live
12266 // out. SelectMI should have a kill flag on EFLAGS.
12267 SelectItr->addRegisterKilled(X86::EFLAGS, TRI);
12271 MachineBasicBlock *
12272 X86TargetLowering::EmitLoweredSelect(MachineInstr *MI,
12273 MachineBasicBlock *BB) const {
12274 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
12275 DebugLoc DL = MI->getDebugLoc();
12277 // To "insert" a SELECT_CC instruction, we actually have to insert the
12278 // diamond control-flow pattern. The incoming instruction knows the
12279 // destination vreg to set, the condition code register to branch on, the
12280 // true/false values to select between, and a branch opcode to use.
12281 const BasicBlock *LLVM_BB = BB->getBasicBlock();
12282 MachineFunction::iterator It = BB;
12288 // cmpTY ccX, r1, r2
12290 // fallthrough --> copy0MBB
12291 MachineBasicBlock *thisMBB = BB;
12292 MachineFunction *F = BB->getParent();
12293 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
12294 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
12295 F->insert(It, copy0MBB);
12296 F->insert(It, sinkMBB);
12298 // If the EFLAGS register isn't dead in the terminator, then claim that it's
12299 // live into the sink and copy blocks.
12300 const TargetRegisterInfo* TRI = getTargetMachine().getRegisterInfo();
12301 if (!MI->killsRegister(X86::EFLAGS) &&
12302 !checkAndUpdateEFLAGSKill(MI, BB, TRI)) {
12303 copy0MBB->addLiveIn(X86::EFLAGS);
12304 sinkMBB->addLiveIn(X86::EFLAGS);
12307 // Transfer the remainder of BB and its successor edges to sinkMBB.
12308 sinkMBB->splice(sinkMBB->begin(), BB,
12309 llvm::next(MachineBasicBlock::iterator(MI)),
12311 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
12313 // Add the true and fallthrough blocks as its successors.
12314 BB->addSuccessor(copy0MBB);
12315 BB->addSuccessor(sinkMBB);
12317 // Create the conditional branch instruction.
12319 X86::GetCondBranchFromCond((X86::CondCode)MI->getOperand(3).getImm());
12320 BuildMI(BB, DL, TII->get(Opc)).addMBB(sinkMBB);
12323 // %FalseValue = ...
12324 // # fallthrough to sinkMBB
12325 copy0MBB->addSuccessor(sinkMBB);
12328 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
12330 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
12331 TII->get(X86::PHI), MI->getOperand(0).getReg())
12332 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB)
12333 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
12335 MI->eraseFromParent(); // The pseudo instruction is gone now.
12339 MachineBasicBlock *
12340 X86TargetLowering::EmitLoweredSegAlloca(MachineInstr *MI, MachineBasicBlock *BB,
12341 bool Is64Bit) const {
12342 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
12343 DebugLoc DL = MI->getDebugLoc();
12344 MachineFunction *MF = BB->getParent();
12345 const BasicBlock *LLVM_BB = BB->getBasicBlock();
12347 assert(getTargetMachine().Options.EnableSegmentedStacks);
12349 unsigned TlsReg = Is64Bit ? X86::FS : X86::GS;
12350 unsigned TlsOffset = Is64Bit ? 0x70 : 0x30;
12353 // ... [Till the alloca]
12354 // If stacklet is not large enough, jump to mallocMBB
12357 // Allocate by subtracting from RSP
12358 // Jump to continueMBB
12361 // Allocate by call to runtime
12365 // [rest of original BB]
12368 MachineBasicBlock *mallocMBB = MF->CreateMachineBasicBlock(LLVM_BB);
12369 MachineBasicBlock *bumpMBB = MF->CreateMachineBasicBlock(LLVM_BB);
12370 MachineBasicBlock *continueMBB = MF->CreateMachineBasicBlock(LLVM_BB);
12372 MachineRegisterInfo &MRI = MF->getRegInfo();
12373 const TargetRegisterClass *AddrRegClass =
12374 getRegClassFor(Is64Bit ? MVT::i64:MVT::i32);
12376 unsigned mallocPtrVReg = MRI.createVirtualRegister(AddrRegClass),
12377 bumpSPPtrVReg = MRI.createVirtualRegister(AddrRegClass),
12378 tmpSPVReg = MRI.createVirtualRegister(AddrRegClass),
12379 SPLimitVReg = MRI.createVirtualRegister(AddrRegClass),
12380 sizeVReg = MI->getOperand(1).getReg(),
12381 physSPReg = Is64Bit ? X86::RSP : X86::ESP;
12383 MachineFunction::iterator MBBIter = BB;
12386 MF->insert(MBBIter, bumpMBB);
12387 MF->insert(MBBIter, mallocMBB);
12388 MF->insert(MBBIter, continueMBB);
12390 continueMBB->splice(continueMBB->begin(), BB, llvm::next
12391 (MachineBasicBlock::iterator(MI)), BB->end());
12392 continueMBB->transferSuccessorsAndUpdatePHIs(BB);
12394 // Add code to the main basic block to check if the stack limit has been hit,
12395 // and if so, jump to mallocMBB otherwise to bumpMBB.
12396 BuildMI(BB, DL, TII->get(TargetOpcode::COPY), tmpSPVReg).addReg(physSPReg);
12397 BuildMI(BB, DL, TII->get(Is64Bit ? X86::SUB64rr:X86::SUB32rr), SPLimitVReg)
12398 .addReg(tmpSPVReg).addReg(sizeVReg);
12399 BuildMI(BB, DL, TII->get(Is64Bit ? X86::CMP64mr:X86::CMP32mr))
12400 .addReg(0).addImm(1).addReg(0).addImm(TlsOffset).addReg(TlsReg)
12401 .addReg(SPLimitVReg);
12402 BuildMI(BB, DL, TII->get(X86::JG_4)).addMBB(mallocMBB);
12404 // bumpMBB simply decreases the stack pointer, since we know the current
12405 // stacklet has enough space.
12406 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), physSPReg)
12407 .addReg(SPLimitVReg);
12408 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), bumpSPPtrVReg)
12409 .addReg(SPLimitVReg);
12410 BuildMI(bumpMBB, DL, TII->get(X86::JMP_4)).addMBB(continueMBB);
12412 // Calls into a routine in libgcc to allocate more space from the heap.
12413 const uint32_t *RegMask =
12414 getTargetMachine().getRegisterInfo()->getCallPreservedMask(CallingConv::C);
12416 BuildMI(mallocMBB, DL, TII->get(X86::MOV64rr), X86::RDI)
12418 BuildMI(mallocMBB, DL, TII->get(X86::CALL64pcrel32))
12419 .addExternalSymbol("__morestack_allocate_stack_space")
12420 .addRegMask(RegMask)
12421 .addReg(X86::RDI, RegState::Implicit)
12422 .addReg(X86::RAX, RegState::ImplicitDefine);
12424 BuildMI(mallocMBB, DL, TII->get(X86::SUB32ri), physSPReg).addReg(physSPReg)
12426 BuildMI(mallocMBB, DL, TII->get(X86::PUSH32r)).addReg(sizeVReg);
12427 BuildMI(mallocMBB, DL, TII->get(X86::CALLpcrel32))
12428 .addExternalSymbol("__morestack_allocate_stack_space")
12429 .addRegMask(RegMask)
12430 .addReg(X86::EAX, RegState::ImplicitDefine);
12434 BuildMI(mallocMBB, DL, TII->get(X86::ADD32ri), physSPReg).addReg(physSPReg)
12437 BuildMI(mallocMBB, DL, TII->get(TargetOpcode::COPY), mallocPtrVReg)
12438 .addReg(Is64Bit ? X86::RAX : X86::EAX);
12439 BuildMI(mallocMBB, DL, TII->get(X86::JMP_4)).addMBB(continueMBB);
12441 // Set up the CFG correctly.
12442 BB->addSuccessor(bumpMBB);
12443 BB->addSuccessor(mallocMBB);
12444 mallocMBB->addSuccessor(continueMBB);
12445 bumpMBB->addSuccessor(continueMBB);
12447 // Take care of the PHI nodes.
12448 BuildMI(*continueMBB, continueMBB->begin(), DL, TII->get(X86::PHI),
12449 MI->getOperand(0).getReg())
12450 .addReg(mallocPtrVReg).addMBB(mallocMBB)
12451 .addReg(bumpSPPtrVReg).addMBB(bumpMBB);
12453 // Delete the original pseudo instruction.
12454 MI->eraseFromParent();
12457 return continueMBB;
12460 MachineBasicBlock *
12461 X86TargetLowering::EmitLoweredWinAlloca(MachineInstr *MI,
12462 MachineBasicBlock *BB) const {
12463 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
12464 DebugLoc DL = MI->getDebugLoc();
12466 assert(!Subtarget->isTargetEnvMacho());
12468 // The lowering is pretty easy: we're just emitting the call to _alloca. The
12469 // non-trivial part is impdef of ESP.
12471 if (Subtarget->isTargetWin64()) {
12472 if (Subtarget->isTargetCygMing()) {
12473 // ___chkstk(Mingw64):
12474 // Clobbers R10, R11, RAX and EFLAGS.
12476 BuildMI(*BB, MI, DL, TII->get(X86::W64ALLOCA))
12477 .addExternalSymbol("___chkstk")
12478 .addReg(X86::RAX, RegState::Implicit)
12479 .addReg(X86::RSP, RegState::Implicit)
12480 .addReg(X86::RAX, RegState::Define | RegState::Implicit)
12481 .addReg(X86::RSP, RegState::Define | RegState::Implicit)
12482 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
12484 // __chkstk(MSVCRT): does not update stack pointer.
12485 // Clobbers R10, R11 and EFLAGS.
12486 // FIXME: RAX(allocated size) might be reused and not killed.
12487 BuildMI(*BB, MI, DL, TII->get(X86::W64ALLOCA))
12488 .addExternalSymbol("__chkstk")
12489 .addReg(X86::RAX, RegState::Implicit)
12490 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
12491 // RAX has the offset to subtracted from RSP.
12492 BuildMI(*BB, MI, DL, TII->get(X86::SUB64rr), X86::RSP)
12497 const char *StackProbeSymbol =
12498 Subtarget->isTargetWindows() ? "_chkstk" : "_alloca";
12500 BuildMI(*BB, MI, DL, TII->get(X86::CALLpcrel32))
12501 .addExternalSymbol(StackProbeSymbol)
12502 .addReg(X86::EAX, RegState::Implicit)
12503 .addReg(X86::ESP, RegState::Implicit)
12504 .addReg(X86::EAX, RegState::Define | RegState::Implicit)
12505 .addReg(X86::ESP, RegState::Define | RegState::Implicit)
12506 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
12509 MI->eraseFromParent(); // The pseudo instruction is gone now.
12513 MachineBasicBlock *
12514 X86TargetLowering::EmitLoweredTLSCall(MachineInstr *MI,
12515 MachineBasicBlock *BB) const {
12516 // This is pretty easy. We're taking the value that we received from
12517 // our load from the relocation, sticking it in either RDI (x86-64)
12518 // or EAX and doing an indirect call. The return value will then
12519 // be in the normal return register.
12520 const X86InstrInfo *TII
12521 = static_cast<const X86InstrInfo*>(getTargetMachine().getInstrInfo());
12522 DebugLoc DL = MI->getDebugLoc();
12523 MachineFunction *F = BB->getParent();
12525 assert(Subtarget->isTargetDarwin() && "Darwin only instr emitted?");
12526 assert(MI->getOperand(3).isGlobal() && "This should be a global");
12528 // Get a register mask for the lowered call.
12529 // FIXME: The 32-bit calls have non-standard calling conventions. Use a
12530 // proper register mask.
12531 const uint32_t *RegMask =
12532 getTargetMachine().getRegisterInfo()->getCallPreservedMask(CallingConv::C);
12533 if (Subtarget->is64Bit()) {
12534 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
12535 TII->get(X86::MOV64rm), X86::RDI)
12537 .addImm(0).addReg(0)
12538 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
12539 MI->getOperand(3).getTargetFlags())
12541 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL64m));
12542 addDirectMem(MIB, X86::RDI);
12543 MIB.addReg(X86::RAX, RegState::ImplicitDefine).addRegMask(RegMask);
12544 } else if (getTargetMachine().getRelocationModel() != Reloc::PIC_) {
12545 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
12546 TII->get(X86::MOV32rm), X86::EAX)
12548 .addImm(0).addReg(0)
12549 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
12550 MI->getOperand(3).getTargetFlags())
12552 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
12553 addDirectMem(MIB, X86::EAX);
12554 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask);
12556 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
12557 TII->get(X86::MOV32rm), X86::EAX)
12558 .addReg(TII->getGlobalBaseReg(F))
12559 .addImm(0).addReg(0)
12560 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
12561 MI->getOperand(3).getTargetFlags())
12563 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
12564 addDirectMem(MIB, X86::EAX);
12565 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask);
12568 MI->eraseFromParent(); // The pseudo instruction is gone now.
12572 MachineBasicBlock *
12573 X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
12574 MachineBasicBlock *BB) const {
12575 switch (MI->getOpcode()) {
12576 default: llvm_unreachable("Unexpected instr type to insert");
12577 case X86::TAILJMPd64:
12578 case X86::TAILJMPr64:
12579 case X86::TAILJMPm64:
12580 llvm_unreachable("TAILJMP64 would not be touched here.");
12581 case X86::TCRETURNdi64:
12582 case X86::TCRETURNri64:
12583 case X86::TCRETURNmi64:
12585 case X86::WIN_ALLOCA:
12586 return EmitLoweredWinAlloca(MI, BB);
12587 case X86::SEG_ALLOCA_32:
12588 return EmitLoweredSegAlloca(MI, BB, false);
12589 case X86::SEG_ALLOCA_64:
12590 return EmitLoweredSegAlloca(MI, BB, true);
12591 case X86::TLSCall_32:
12592 case X86::TLSCall_64:
12593 return EmitLoweredTLSCall(MI, BB);
12594 case X86::CMOV_GR8:
12595 case X86::CMOV_FR32:
12596 case X86::CMOV_FR64:
12597 case X86::CMOV_V4F32:
12598 case X86::CMOV_V2F64:
12599 case X86::CMOV_V2I64:
12600 case X86::CMOV_V8F32:
12601 case X86::CMOV_V4F64:
12602 case X86::CMOV_V4I64:
12603 case X86::CMOV_GR16:
12604 case X86::CMOV_GR32:
12605 case X86::CMOV_RFP32:
12606 case X86::CMOV_RFP64:
12607 case X86::CMOV_RFP80:
12608 return EmitLoweredSelect(MI, BB);
12610 case X86::FP32_TO_INT16_IN_MEM:
12611 case X86::FP32_TO_INT32_IN_MEM:
12612 case X86::FP32_TO_INT64_IN_MEM:
12613 case X86::FP64_TO_INT16_IN_MEM:
12614 case X86::FP64_TO_INT32_IN_MEM:
12615 case X86::FP64_TO_INT64_IN_MEM:
12616 case X86::FP80_TO_INT16_IN_MEM:
12617 case X86::FP80_TO_INT32_IN_MEM:
12618 case X86::FP80_TO_INT64_IN_MEM: {
12619 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
12620 DebugLoc DL = MI->getDebugLoc();
12622 // Change the floating point control register to use "round towards zero"
12623 // mode when truncating to an integer value.
12624 MachineFunction *F = BB->getParent();
12625 int CWFrameIdx = F->getFrameInfo()->CreateStackObject(2, 2, false);
12626 addFrameReference(BuildMI(*BB, MI, DL,
12627 TII->get(X86::FNSTCW16m)), CWFrameIdx);
12629 // Load the old value of the high byte of the control word...
12631 F->getRegInfo().createVirtualRegister(&X86::GR16RegClass);
12632 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16rm), OldCW),
12635 // Set the high part to be round to zero...
12636 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mi)), CWFrameIdx)
12639 // Reload the modified control word now...
12640 addFrameReference(BuildMI(*BB, MI, DL,
12641 TII->get(X86::FLDCW16m)), CWFrameIdx);
12643 // Restore the memory image of control word to original value
12644 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mr)), CWFrameIdx)
12647 // Get the X86 opcode to use.
12649 switch (MI->getOpcode()) {
12650 default: llvm_unreachable("illegal opcode!");
12651 case X86::FP32_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m32; break;
12652 case X86::FP32_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m32; break;
12653 case X86::FP32_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m32; break;
12654 case X86::FP64_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m64; break;
12655 case X86::FP64_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m64; break;
12656 case X86::FP64_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m64; break;
12657 case X86::FP80_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m80; break;
12658 case X86::FP80_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m80; break;
12659 case X86::FP80_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m80; break;
12663 MachineOperand &Op = MI->getOperand(0);
12665 AM.BaseType = X86AddressMode::RegBase;
12666 AM.Base.Reg = Op.getReg();
12668 AM.BaseType = X86AddressMode::FrameIndexBase;
12669 AM.Base.FrameIndex = Op.getIndex();
12671 Op = MI->getOperand(1);
12673 AM.Scale = Op.getImm();
12674 Op = MI->getOperand(2);
12676 AM.IndexReg = Op.getImm();
12677 Op = MI->getOperand(3);
12678 if (Op.isGlobal()) {
12679 AM.GV = Op.getGlobal();
12681 AM.Disp = Op.getImm();
12683 addFullAddress(BuildMI(*BB, MI, DL, TII->get(Opc)), AM)
12684 .addReg(MI->getOperand(X86::AddrNumOperands).getReg());
12686 // Reload the original control word now.
12687 addFrameReference(BuildMI(*BB, MI, DL,
12688 TII->get(X86::FLDCW16m)), CWFrameIdx);
12690 MI->eraseFromParent(); // The pseudo instruction is gone now.
12693 // String/text processing lowering.
12694 case X86::PCMPISTRM128REG:
12695 case X86::VPCMPISTRM128REG:
12696 return EmitPCMP(MI, BB, 3, false /* in-mem */);
12697 case X86::PCMPISTRM128MEM:
12698 case X86::VPCMPISTRM128MEM:
12699 return EmitPCMP(MI, BB, 3, true /* in-mem */);
12700 case X86::PCMPESTRM128REG:
12701 case X86::VPCMPESTRM128REG:
12702 return EmitPCMP(MI, BB, 5, false /* in mem */);
12703 case X86::PCMPESTRM128MEM:
12704 case X86::VPCMPESTRM128MEM:
12705 return EmitPCMP(MI, BB, 5, true /* in mem */);
12707 // Thread synchronization.
12709 return EmitMonitor(MI, BB);
12711 // Atomic Lowering.
12712 case X86::ATOMAND32:
12713 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND32rr,
12714 X86::AND32ri, X86::MOV32rm,
12716 X86::NOT32r, X86::EAX,
12717 &X86::GR32RegClass);
12718 case X86::ATOMOR32:
12719 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR32rr,
12720 X86::OR32ri, X86::MOV32rm,
12722 X86::NOT32r, X86::EAX,
12723 &X86::GR32RegClass);
12724 case X86::ATOMXOR32:
12725 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR32rr,
12726 X86::XOR32ri, X86::MOV32rm,
12728 X86::NOT32r, X86::EAX,
12729 &X86::GR32RegClass);
12730 case X86::ATOMNAND32:
12731 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND32rr,
12732 X86::AND32ri, X86::MOV32rm,
12734 X86::NOT32r, X86::EAX,
12735 &X86::GR32RegClass, true);
12736 case X86::ATOMMIN32:
12737 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL32rr);
12738 case X86::ATOMMAX32:
12739 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG32rr);
12740 case X86::ATOMUMIN32:
12741 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB32rr);
12742 case X86::ATOMUMAX32:
12743 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA32rr);
12745 case X86::ATOMAND16:
12746 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND16rr,
12747 X86::AND16ri, X86::MOV16rm,
12749 X86::NOT16r, X86::AX,
12750 &X86::GR16RegClass);
12751 case X86::ATOMOR16:
12752 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR16rr,
12753 X86::OR16ri, X86::MOV16rm,
12755 X86::NOT16r, X86::AX,
12756 &X86::GR16RegClass);
12757 case X86::ATOMXOR16:
12758 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR16rr,
12759 X86::XOR16ri, X86::MOV16rm,
12761 X86::NOT16r, X86::AX,
12762 &X86::GR16RegClass);
12763 case X86::ATOMNAND16:
12764 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND16rr,
12765 X86::AND16ri, X86::MOV16rm,
12767 X86::NOT16r, X86::AX,
12768 &X86::GR16RegClass, true);
12769 case X86::ATOMMIN16:
12770 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL16rr);
12771 case X86::ATOMMAX16:
12772 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG16rr);
12773 case X86::ATOMUMIN16:
12774 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB16rr);
12775 case X86::ATOMUMAX16:
12776 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA16rr);
12778 case X86::ATOMAND8:
12779 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND8rr,
12780 X86::AND8ri, X86::MOV8rm,
12782 X86::NOT8r, X86::AL,
12783 &X86::GR8RegClass);
12785 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR8rr,
12786 X86::OR8ri, X86::MOV8rm,
12788 X86::NOT8r, X86::AL,
12789 &X86::GR8RegClass);
12790 case X86::ATOMXOR8:
12791 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR8rr,
12792 X86::XOR8ri, X86::MOV8rm,
12794 X86::NOT8r, X86::AL,
12795 &X86::GR8RegClass);
12796 case X86::ATOMNAND8:
12797 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND8rr,
12798 X86::AND8ri, X86::MOV8rm,
12800 X86::NOT8r, X86::AL,
12801 &X86::GR8RegClass, true);
12802 // FIXME: There are no CMOV8 instructions; MIN/MAX need some other way.
12803 // This group is for 64-bit host.
12804 case X86::ATOMAND64:
12805 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND64rr,
12806 X86::AND64ri32, X86::MOV64rm,
12808 X86::NOT64r, X86::RAX,
12809 &X86::GR64RegClass);
12810 case X86::ATOMOR64:
12811 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR64rr,
12812 X86::OR64ri32, X86::MOV64rm,
12814 X86::NOT64r, X86::RAX,
12815 &X86::GR64RegClass);
12816 case X86::ATOMXOR64:
12817 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR64rr,
12818 X86::XOR64ri32, X86::MOV64rm,
12820 X86::NOT64r, X86::RAX,
12821 &X86::GR64RegClass);
12822 case X86::ATOMNAND64:
12823 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND64rr,
12824 X86::AND64ri32, X86::MOV64rm,
12826 X86::NOT64r, X86::RAX,
12827 &X86::GR64RegClass, true);
12828 case X86::ATOMMIN64:
12829 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL64rr);
12830 case X86::ATOMMAX64:
12831 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG64rr);
12832 case X86::ATOMUMIN64:
12833 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB64rr);
12834 case X86::ATOMUMAX64:
12835 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA64rr);
12837 // This group does 64-bit operations on a 32-bit host.
12838 case X86::ATOMAND6432:
12839 return EmitAtomicBit6432WithCustomInserter(MI, BB,
12840 X86::AND32rr, X86::AND32rr,
12841 X86::AND32ri, X86::AND32ri,
12843 case X86::ATOMOR6432:
12844 return EmitAtomicBit6432WithCustomInserter(MI, BB,
12845 X86::OR32rr, X86::OR32rr,
12846 X86::OR32ri, X86::OR32ri,
12848 case X86::ATOMXOR6432:
12849 return EmitAtomicBit6432WithCustomInserter(MI, BB,
12850 X86::XOR32rr, X86::XOR32rr,
12851 X86::XOR32ri, X86::XOR32ri,
12853 case X86::ATOMNAND6432:
12854 return EmitAtomicBit6432WithCustomInserter(MI, BB,
12855 X86::AND32rr, X86::AND32rr,
12856 X86::AND32ri, X86::AND32ri,
12858 case X86::ATOMADD6432:
12859 return EmitAtomicBit6432WithCustomInserter(MI, BB,
12860 X86::ADD32rr, X86::ADC32rr,
12861 X86::ADD32ri, X86::ADC32ri,
12863 case X86::ATOMSUB6432:
12864 return EmitAtomicBit6432WithCustomInserter(MI, BB,
12865 X86::SUB32rr, X86::SBB32rr,
12866 X86::SUB32ri, X86::SBB32ri,
12868 case X86::ATOMSWAP6432:
12869 return EmitAtomicBit6432WithCustomInserter(MI, BB,
12870 X86::MOV32rr, X86::MOV32rr,
12871 X86::MOV32ri, X86::MOV32ri,
12873 case X86::VASTART_SAVE_XMM_REGS:
12874 return EmitVAStartSaveXMMRegsWithCustomInserter(MI, BB);
12876 case X86::VAARG_64:
12877 return EmitVAARG64WithCustomInserter(MI, BB);
12881 //===----------------------------------------------------------------------===//
12882 // X86 Optimization Hooks
12883 //===----------------------------------------------------------------------===//
12885 void X86TargetLowering::computeMaskedBitsForTargetNode(const SDValue Op,
12888 const SelectionDAG &DAG,
12889 unsigned Depth) const {
12890 unsigned BitWidth = KnownZero.getBitWidth();
12891 unsigned Opc = Op.getOpcode();
12892 assert((Opc >= ISD::BUILTIN_OP_END ||
12893 Opc == ISD::INTRINSIC_WO_CHAIN ||
12894 Opc == ISD::INTRINSIC_W_CHAIN ||
12895 Opc == ISD::INTRINSIC_VOID) &&
12896 "Should use MaskedValueIsZero if you don't know whether Op"
12897 " is a target node!");
12899 KnownZero = KnownOne = APInt(BitWidth, 0); // Don't know anything.
12913 // These nodes' second result is a boolean.
12914 if (Op.getResNo() == 0)
12917 case X86ISD::SETCC:
12918 KnownZero |= APInt::getHighBitsSet(BitWidth, BitWidth - 1);
12920 case ISD::INTRINSIC_WO_CHAIN: {
12921 unsigned IntId = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
12922 unsigned NumLoBits = 0;
12925 case Intrinsic::x86_sse_movmsk_ps:
12926 case Intrinsic::x86_avx_movmsk_ps_256:
12927 case Intrinsic::x86_sse2_movmsk_pd:
12928 case Intrinsic::x86_avx_movmsk_pd_256:
12929 case Intrinsic::x86_mmx_pmovmskb:
12930 case Intrinsic::x86_sse2_pmovmskb_128:
12931 case Intrinsic::x86_avx2_pmovmskb: {
12932 // High bits of movmskp{s|d}, pmovmskb are known zero.
12934 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
12935 case Intrinsic::x86_sse_movmsk_ps: NumLoBits = 4; break;
12936 case Intrinsic::x86_avx_movmsk_ps_256: NumLoBits = 8; break;
12937 case Intrinsic::x86_sse2_movmsk_pd: NumLoBits = 2; break;
12938 case Intrinsic::x86_avx_movmsk_pd_256: NumLoBits = 4; break;
12939 case Intrinsic::x86_mmx_pmovmskb: NumLoBits = 8; break;
12940 case Intrinsic::x86_sse2_pmovmskb_128: NumLoBits = 16; break;
12941 case Intrinsic::x86_avx2_pmovmskb: NumLoBits = 32; break;
12943 KnownZero = APInt::getHighBitsSet(BitWidth, BitWidth - NumLoBits);
12952 unsigned X86TargetLowering::ComputeNumSignBitsForTargetNode(SDValue Op,
12953 unsigned Depth) const {
12954 // SETCC_CARRY sets the dest to ~0 for true or 0 for false.
12955 if (Op.getOpcode() == X86ISD::SETCC_CARRY)
12956 return Op.getValueType().getScalarType().getSizeInBits();
12962 /// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the
12963 /// node is a GlobalAddress + offset.
12964 bool X86TargetLowering::isGAPlusOffset(SDNode *N,
12965 const GlobalValue* &GA,
12966 int64_t &Offset) const {
12967 if (N->getOpcode() == X86ISD::Wrapper) {
12968 if (isa<GlobalAddressSDNode>(N->getOperand(0))) {
12969 GA = cast<GlobalAddressSDNode>(N->getOperand(0))->getGlobal();
12970 Offset = cast<GlobalAddressSDNode>(N->getOperand(0))->getOffset();
12974 return TargetLowering::isGAPlusOffset(N, GA, Offset);
12977 /// isShuffleHigh128VectorInsertLow - Checks whether the shuffle node is the
12978 /// same as extracting the high 128-bit part of 256-bit vector and then
12979 /// inserting the result into the low part of a new 256-bit vector
12980 static bool isShuffleHigh128VectorInsertLow(ShuffleVectorSDNode *SVOp) {
12981 EVT VT = SVOp->getValueType(0);
12982 unsigned NumElems = VT.getVectorNumElements();
12984 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
12985 for (unsigned i = 0, j = NumElems/2; i != NumElems/2; ++i, ++j)
12986 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) ||
12987 SVOp->getMaskElt(j) >= 0)
12993 /// isShuffleLow128VectorInsertHigh - Checks whether the shuffle node is the
12994 /// same as extracting the low 128-bit part of 256-bit vector and then
12995 /// inserting the result into the high part of a new 256-bit vector
12996 static bool isShuffleLow128VectorInsertHigh(ShuffleVectorSDNode *SVOp) {
12997 EVT VT = SVOp->getValueType(0);
12998 unsigned NumElems = VT.getVectorNumElements();
13000 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
13001 for (unsigned i = NumElems/2, j = 0; i != NumElems; ++i, ++j)
13002 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) ||
13003 SVOp->getMaskElt(j) >= 0)
13009 /// PerformShuffleCombine256 - Performs shuffle combines for 256-bit vectors.
13010 static SDValue PerformShuffleCombine256(SDNode *N, SelectionDAG &DAG,
13011 TargetLowering::DAGCombinerInfo &DCI,
13012 const X86Subtarget* Subtarget) {
13013 DebugLoc dl = N->getDebugLoc();
13014 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
13015 SDValue V1 = SVOp->getOperand(0);
13016 SDValue V2 = SVOp->getOperand(1);
13017 EVT VT = SVOp->getValueType(0);
13018 unsigned NumElems = VT.getVectorNumElements();
13020 if (V1.getOpcode() == ISD::CONCAT_VECTORS &&
13021 V2.getOpcode() == ISD::CONCAT_VECTORS) {
13025 // V UNDEF BUILD_VECTOR UNDEF
13027 // CONCAT_VECTOR CONCAT_VECTOR
13030 // RESULT: V + zero extended
13032 if (V2.getOperand(0).getOpcode() != ISD::BUILD_VECTOR ||
13033 V2.getOperand(1).getOpcode() != ISD::UNDEF ||
13034 V1.getOperand(1).getOpcode() != ISD::UNDEF)
13037 if (!ISD::isBuildVectorAllZeros(V2.getOperand(0).getNode()))
13040 // To match the shuffle mask, the first half of the mask should
13041 // be exactly the first vector, and all the rest a splat with the
13042 // first element of the second one.
13043 for (unsigned i = 0; i != NumElems/2; ++i)
13044 if (!isUndefOrEqual(SVOp->getMaskElt(i), i) ||
13045 !isUndefOrEqual(SVOp->getMaskElt(i+NumElems/2), NumElems))
13048 // If V1 is coming from a vector load then just fold to a VZEXT_LOAD.
13049 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(V1.getOperand(0))) {
13050 if (Ld->hasNUsesOfValue(1, 0)) {
13051 SDVTList Tys = DAG.getVTList(MVT::v4i64, MVT::Other);
13052 SDValue Ops[] = { Ld->getChain(), Ld->getBasePtr() };
13054 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, dl, Tys, Ops, 2,
13056 Ld->getPointerInfo(),
13057 Ld->getAlignment(),
13058 false/*isVolatile*/, true/*ReadMem*/,
13059 false/*WriteMem*/);
13060 return DAG.getNode(ISD::BITCAST, dl, VT, ResNode);
13064 // Emit a zeroed vector and insert the desired subvector on its
13066 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
13067 SDValue InsV = Insert128BitVector(Zeros, V1.getOperand(0), 0, DAG, dl);
13068 return DCI.CombineTo(N, InsV);
13071 //===--------------------------------------------------------------------===//
13072 // Combine some shuffles into subvector extracts and inserts:
13075 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
13076 if (isShuffleHigh128VectorInsertLow(SVOp)) {
13077 SDValue V = Extract128BitVector(V1, NumElems/2, DAG, dl);
13078 SDValue InsV = Insert128BitVector(DAG.getUNDEF(VT), V, 0, DAG, dl);
13079 return DCI.CombineTo(N, InsV);
13082 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
13083 if (isShuffleLow128VectorInsertHigh(SVOp)) {
13084 SDValue V = Extract128BitVector(V1, 0, DAG, dl);
13085 SDValue InsV = Insert128BitVector(DAG.getUNDEF(VT), V, NumElems/2, DAG, dl);
13086 return DCI.CombineTo(N, InsV);
13092 /// PerformShuffleCombine - Performs several different shuffle combines.
13093 static SDValue PerformShuffleCombine(SDNode *N, SelectionDAG &DAG,
13094 TargetLowering::DAGCombinerInfo &DCI,
13095 const X86Subtarget *Subtarget) {
13096 DebugLoc dl = N->getDebugLoc();
13097 EVT VT = N->getValueType(0);
13099 // Don't create instructions with illegal types after legalize types has run.
13100 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
13101 if (!DCI.isBeforeLegalize() && !TLI.isTypeLegal(VT.getVectorElementType()))
13104 // Combine 256-bit vector shuffles. This is only profitable when in AVX mode
13105 if (Subtarget->hasAVX() && VT.is256BitVector() &&
13106 N->getOpcode() == ISD::VECTOR_SHUFFLE)
13107 return PerformShuffleCombine256(N, DAG, DCI, Subtarget);
13109 // Only handle 128 wide vector from here on.
13110 if (!VT.is128BitVector())
13113 // Combine a vector_shuffle that is equal to build_vector load1, load2, load3,
13114 // load4, <0, 1, 2, 3> into a 128-bit load if the load addresses are
13115 // consecutive, non-overlapping, and in the right order.
13116 SmallVector<SDValue, 16> Elts;
13117 for (unsigned i = 0, e = VT.getVectorNumElements(); i != e; ++i)
13118 Elts.push_back(getShuffleScalarElt(N, i, DAG, 0));
13120 return EltsFromConsecutiveLoads(VT, Elts, dl, DAG);
13124 /// DCI, PerformTruncateCombine - Converts truncate operation to
13125 /// a sequence of vector shuffle operations.
13126 /// It is possible when we truncate 256-bit vector to 128-bit vector
13128 SDValue X86TargetLowering::PerformTruncateCombine(SDNode *N, SelectionDAG &DAG,
13129 DAGCombinerInfo &DCI) const {
13130 if (!DCI.isBeforeLegalizeOps())
13133 if (!Subtarget->hasAVX())
13136 EVT VT = N->getValueType(0);
13137 SDValue Op = N->getOperand(0);
13138 EVT OpVT = Op.getValueType();
13139 DebugLoc dl = N->getDebugLoc();
13141 if ((VT == MVT::v4i32) && (OpVT == MVT::v4i64)) {
13143 if (Subtarget->hasAVX2()) {
13144 // AVX2: v4i64 -> v4i32
13147 static const int ShufMask[] = {0, 2, 4, 6, -1, -1, -1, -1};
13149 Op = DAG.getNode(ISD::BITCAST, dl, MVT::v8i32, Op);
13150 Op = DAG.getVectorShuffle(MVT::v8i32, dl, Op, DAG.getUNDEF(MVT::v8i32),
13153 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, Op,
13154 DAG.getIntPtrConstant(0));
13157 // AVX: v4i64 -> v4i32
13158 SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v2i64, Op,
13159 DAG.getIntPtrConstant(0));
13161 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v2i64, Op,
13162 DAG.getIntPtrConstant(2));
13164 OpLo = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, OpLo);
13165 OpHi = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, OpHi);
13168 static const int ShufMask1[] = {0, 2, 0, 0};
13170 OpLo = DAG.getVectorShuffle(VT, dl, OpLo, DAG.getUNDEF(VT), ShufMask1);
13171 OpHi = DAG.getVectorShuffle(VT, dl, OpHi, DAG.getUNDEF(VT), ShufMask1);
13174 static const int ShufMask2[] = {0, 1, 4, 5};
13176 return DAG.getVectorShuffle(VT, dl, OpLo, OpHi, ShufMask2);
13179 if ((VT == MVT::v8i16) && (OpVT == MVT::v8i32)) {
13181 if (Subtarget->hasAVX2()) {
13182 // AVX2: v8i32 -> v8i16
13184 Op = DAG.getNode(ISD::BITCAST, dl, MVT::v32i8, Op);
13187 SmallVector<SDValue,32> pshufbMask;
13188 for (unsigned i = 0; i < 2; ++i) {
13189 pshufbMask.push_back(DAG.getConstant(0x0, MVT::i8));
13190 pshufbMask.push_back(DAG.getConstant(0x1, MVT::i8));
13191 pshufbMask.push_back(DAG.getConstant(0x4, MVT::i8));
13192 pshufbMask.push_back(DAG.getConstant(0x5, MVT::i8));
13193 pshufbMask.push_back(DAG.getConstant(0x8, MVT::i8));
13194 pshufbMask.push_back(DAG.getConstant(0x9, MVT::i8));
13195 pshufbMask.push_back(DAG.getConstant(0xc, MVT::i8));
13196 pshufbMask.push_back(DAG.getConstant(0xd, MVT::i8));
13197 for (unsigned j = 0; j < 8; ++j)
13198 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
13200 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v32i8,
13201 &pshufbMask[0], 32);
13202 Op = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v32i8, Op, BV);
13204 Op = DAG.getNode(ISD::BITCAST, dl, MVT::v4i64, Op);
13206 static const int ShufMask[] = {0, 2, -1, -1};
13207 Op = DAG.getVectorShuffle(MVT::v4i64, dl, Op, DAG.getUNDEF(MVT::v4i64),
13210 Op = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v2i64, Op,
13211 DAG.getIntPtrConstant(0));
13213 return DAG.getNode(ISD::BITCAST, dl, VT, Op);
13216 SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i32, Op,
13217 DAG.getIntPtrConstant(0));
13219 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i32, Op,
13220 DAG.getIntPtrConstant(4));
13222 OpLo = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, OpLo);
13223 OpHi = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, OpHi);
13226 static const int ShufMask1[] = {0, 1, 4, 5, 8, 9, 12, 13,
13227 -1, -1, -1, -1, -1, -1, -1, -1};
13229 OpLo = DAG.getVectorShuffle(MVT::v16i8, dl, OpLo, DAG.getUNDEF(MVT::v16i8),
13231 OpHi = DAG.getVectorShuffle(MVT::v16i8, dl, OpHi, DAG.getUNDEF(MVT::v16i8),
13234 OpLo = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, OpLo);
13235 OpHi = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, OpHi);
13238 static const int ShufMask2[] = {0, 1, 4, 5};
13240 SDValue res = DAG.getVectorShuffle(MVT::v4i32, dl, OpLo, OpHi, ShufMask2);
13241 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, res);
13247 /// XFormVExtractWithShuffleIntoLoad - Check if a vector extract from a target
13248 /// specific shuffle of a load can be folded into a single element load.
13249 /// Similar handling for VECTOR_SHUFFLE is performed by DAGCombiner, but
13250 /// shuffles have been customed lowered so we need to handle those here.
13251 static SDValue XFormVExtractWithShuffleIntoLoad(SDNode *N, SelectionDAG &DAG,
13252 TargetLowering::DAGCombinerInfo &DCI) {
13253 if (DCI.isBeforeLegalizeOps())
13256 SDValue InVec = N->getOperand(0);
13257 SDValue EltNo = N->getOperand(1);
13259 if (!isa<ConstantSDNode>(EltNo))
13262 EVT VT = InVec.getValueType();
13264 bool HasShuffleIntoBitcast = false;
13265 if (InVec.getOpcode() == ISD::BITCAST) {
13266 // Don't duplicate a load with other uses.
13267 if (!InVec.hasOneUse())
13269 EVT BCVT = InVec.getOperand(0).getValueType();
13270 if (BCVT.getVectorNumElements() != VT.getVectorNumElements())
13272 InVec = InVec.getOperand(0);
13273 HasShuffleIntoBitcast = true;
13276 if (!isTargetShuffle(InVec.getOpcode()))
13279 // Don't duplicate a load with other uses.
13280 if (!InVec.hasOneUse())
13283 SmallVector<int, 16> ShuffleMask;
13285 if (!getTargetShuffleMask(InVec.getNode(), VT.getSimpleVT(), ShuffleMask,
13289 // Select the input vector, guarding against out of range extract vector.
13290 unsigned NumElems = VT.getVectorNumElements();
13291 int Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();
13292 int Idx = (Elt > (int)NumElems) ? -1 : ShuffleMask[Elt];
13293 SDValue LdNode = (Idx < (int)NumElems) ? InVec.getOperand(0)
13294 : InVec.getOperand(1);
13296 // If inputs to shuffle are the same for both ops, then allow 2 uses
13297 unsigned AllowedUses = InVec.getOperand(0) == InVec.getOperand(1) ? 2 : 1;
13299 if (LdNode.getOpcode() == ISD::BITCAST) {
13300 // Don't duplicate a load with other uses.
13301 if (!LdNode.getNode()->hasNUsesOfValue(AllowedUses, 0))
13304 AllowedUses = 1; // only allow 1 load use if we have a bitcast
13305 LdNode = LdNode.getOperand(0);
13308 if (!ISD::isNormalLoad(LdNode.getNode()))
13311 LoadSDNode *LN0 = cast<LoadSDNode>(LdNode);
13313 if (!LN0 ||!LN0->hasNUsesOfValue(AllowedUses, 0) || LN0->isVolatile())
13316 if (HasShuffleIntoBitcast) {
13317 // If there's a bitcast before the shuffle, check if the load type and
13318 // alignment is valid.
13319 unsigned Align = LN0->getAlignment();
13320 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
13321 unsigned NewAlign = TLI.getTargetData()->
13322 getABITypeAlignment(VT.getTypeForEVT(*DAG.getContext()));
13324 if (NewAlign > Align || !TLI.isOperationLegalOrCustom(ISD::LOAD, VT))
13328 // All checks match so transform back to vector_shuffle so that DAG combiner
13329 // can finish the job
13330 DebugLoc dl = N->getDebugLoc();
13332 // Create shuffle node taking into account the case that its a unary shuffle
13333 SDValue Shuffle = (UnaryShuffle) ? DAG.getUNDEF(VT) : InVec.getOperand(1);
13334 Shuffle = DAG.getVectorShuffle(InVec.getValueType(), dl,
13335 InVec.getOperand(0), Shuffle,
13337 Shuffle = DAG.getNode(ISD::BITCAST, dl, VT, Shuffle);
13338 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, N->getValueType(0), Shuffle,
13342 /// PerformEXTRACT_VECTOR_ELTCombine - Detect vector gather/scatter index
13343 /// generation and convert it from being a bunch of shuffles and extracts
13344 /// to a simple store and scalar loads to extract the elements.
13345 static SDValue PerformEXTRACT_VECTOR_ELTCombine(SDNode *N, SelectionDAG &DAG,
13346 TargetLowering::DAGCombinerInfo &DCI) {
13347 SDValue NewOp = XFormVExtractWithShuffleIntoLoad(N, DAG, DCI);
13348 if (NewOp.getNode())
13351 SDValue InputVector = N->getOperand(0);
13353 // Only operate on vectors of 4 elements, where the alternative shuffling
13354 // gets to be more expensive.
13355 if (InputVector.getValueType() != MVT::v4i32)
13358 // Check whether every use of InputVector is an EXTRACT_VECTOR_ELT with a
13359 // single use which is a sign-extend or zero-extend, and all elements are
13361 SmallVector<SDNode *, 4> Uses;
13362 unsigned ExtractedElements = 0;
13363 for (SDNode::use_iterator UI = InputVector.getNode()->use_begin(),
13364 UE = InputVector.getNode()->use_end(); UI != UE; ++UI) {
13365 if (UI.getUse().getResNo() != InputVector.getResNo())
13368 SDNode *Extract = *UI;
13369 if (Extract->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
13372 if (Extract->getValueType(0) != MVT::i32)
13374 if (!Extract->hasOneUse())
13376 if (Extract->use_begin()->getOpcode() != ISD::SIGN_EXTEND &&
13377 Extract->use_begin()->getOpcode() != ISD::ZERO_EXTEND)
13379 if (!isa<ConstantSDNode>(Extract->getOperand(1)))
13382 // Record which element was extracted.
13383 ExtractedElements |=
13384 1 << cast<ConstantSDNode>(Extract->getOperand(1))->getZExtValue();
13386 Uses.push_back(Extract);
13389 // If not all the elements were used, this may not be worthwhile.
13390 if (ExtractedElements != 15)
13393 // Ok, we've now decided to do the transformation.
13394 DebugLoc dl = InputVector.getDebugLoc();
13396 // Store the value to a temporary stack slot.
13397 SDValue StackPtr = DAG.CreateStackTemporary(InputVector.getValueType());
13398 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, InputVector, StackPtr,
13399 MachinePointerInfo(), false, false, 0);
13401 // Replace each use (extract) with a load of the appropriate element.
13402 for (SmallVectorImpl<SDNode *>::iterator UI = Uses.begin(),
13403 UE = Uses.end(); UI != UE; ++UI) {
13404 SDNode *Extract = *UI;
13406 // cOMpute the element's address.
13407 SDValue Idx = Extract->getOperand(1);
13409 InputVector.getValueType().getVectorElementType().getSizeInBits()/8;
13410 uint64_t Offset = EltSize * cast<ConstantSDNode>(Idx)->getZExtValue();
13411 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
13412 SDValue OffsetVal = DAG.getConstant(Offset, TLI.getPointerTy());
13414 SDValue ScalarAddr = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(),
13415 StackPtr, OffsetVal);
13417 // Load the scalar.
13418 SDValue LoadScalar = DAG.getLoad(Extract->getValueType(0), dl, Ch,
13419 ScalarAddr, MachinePointerInfo(),
13420 false, false, false, 0);
13422 // Replace the exact with the load.
13423 DAG.ReplaceAllUsesOfValueWith(SDValue(Extract, 0), LoadScalar);
13426 // The replacement was made in place; don't return anything.
13430 /// PerformSELECTCombine - Do target-specific dag combines on SELECT and VSELECT
13432 static SDValue PerformSELECTCombine(SDNode *N, SelectionDAG &DAG,
13433 TargetLowering::DAGCombinerInfo &DCI,
13434 const X86Subtarget *Subtarget) {
13435 DebugLoc DL = N->getDebugLoc();
13436 SDValue Cond = N->getOperand(0);
13437 // Get the LHS/RHS of the select.
13438 SDValue LHS = N->getOperand(1);
13439 SDValue RHS = N->getOperand(2);
13440 EVT VT = LHS.getValueType();
13442 // If we have SSE[12] support, try to form min/max nodes. SSE min/max
13443 // instructions match the semantics of the common C idiom x<y?x:y but not
13444 // x<=y?x:y, because of how they handle negative zero (which can be
13445 // ignored in unsafe-math mode).
13446 if (Cond.getOpcode() == ISD::SETCC && VT.isFloatingPoint() &&
13447 VT != MVT::f80 && DAG.getTargetLoweringInfo().isTypeLegal(VT) &&
13448 (Subtarget->hasSSE2() ||
13449 (Subtarget->hasSSE1() && VT.getScalarType() == MVT::f32))) {
13450 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
13452 unsigned Opcode = 0;
13453 // Check for x CC y ? x : y.
13454 if (DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
13455 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
13459 // Converting this to a min would handle NaNs incorrectly, and swapping
13460 // the operands would cause it to handle comparisons between positive
13461 // and negative zero incorrectly.
13462 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
13463 if (!DAG.getTarget().Options.UnsafeFPMath &&
13464 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
13466 std::swap(LHS, RHS);
13468 Opcode = X86ISD::FMIN;
13471 // Converting this to a min would handle comparisons between positive
13472 // and negative zero incorrectly.
13473 if (!DAG.getTarget().Options.UnsafeFPMath &&
13474 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
13476 Opcode = X86ISD::FMIN;
13479 // Converting this to a min would handle both negative zeros and NaNs
13480 // incorrectly, but we can swap the operands to fix both.
13481 std::swap(LHS, RHS);
13485 Opcode = X86ISD::FMIN;
13489 // Converting this to a max would handle comparisons between positive
13490 // and negative zero incorrectly.
13491 if (!DAG.getTarget().Options.UnsafeFPMath &&
13492 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
13494 Opcode = X86ISD::FMAX;
13497 // Converting this to a max would handle NaNs incorrectly, and swapping
13498 // the operands would cause it to handle comparisons between positive
13499 // and negative zero incorrectly.
13500 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
13501 if (!DAG.getTarget().Options.UnsafeFPMath &&
13502 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
13504 std::swap(LHS, RHS);
13506 Opcode = X86ISD::FMAX;
13509 // Converting this to a max would handle both negative zeros and NaNs
13510 // incorrectly, but we can swap the operands to fix both.
13511 std::swap(LHS, RHS);
13515 Opcode = X86ISD::FMAX;
13518 // Check for x CC y ? y : x -- a min/max with reversed arms.
13519 } else if (DAG.isEqualTo(LHS, Cond.getOperand(1)) &&
13520 DAG.isEqualTo(RHS, Cond.getOperand(0))) {
13524 // Converting this to a min would handle comparisons between positive
13525 // and negative zero incorrectly, and swapping the operands would
13526 // cause it to handle NaNs incorrectly.
13527 if (!DAG.getTarget().Options.UnsafeFPMath &&
13528 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS))) {
13529 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
13531 std::swap(LHS, RHS);
13533 Opcode = X86ISD::FMIN;
13536 // Converting this to a min would handle NaNs incorrectly.
13537 if (!DAG.getTarget().Options.UnsafeFPMath &&
13538 (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)))
13540 Opcode = X86ISD::FMIN;
13543 // Converting this to a min would handle both negative zeros and NaNs
13544 // incorrectly, but we can swap the operands to fix both.
13545 std::swap(LHS, RHS);
13549 Opcode = X86ISD::FMIN;
13553 // Converting this to a max would handle NaNs incorrectly.
13554 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
13556 Opcode = X86ISD::FMAX;
13559 // Converting this to a max would handle comparisons between positive
13560 // and negative zero incorrectly, and swapping the operands would
13561 // cause it to handle NaNs incorrectly.
13562 if (!DAG.getTarget().Options.UnsafeFPMath &&
13563 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS)) {
13564 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
13566 std::swap(LHS, RHS);
13568 Opcode = X86ISD::FMAX;
13571 // Converting this to a max would handle both negative zeros and NaNs
13572 // incorrectly, but we can swap the operands to fix both.
13573 std::swap(LHS, RHS);
13577 Opcode = X86ISD::FMAX;
13583 return DAG.getNode(Opcode, DL, N->getValueType(0), LHS, RHS);
13586 // If this is a select between two integer constants, try to do some
13588 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(LHS)) {
13589 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(RHS))
13590 // Don't do this for crazy integer types.
13591 if (DAG.getTargetLoweringInfo().isTypeLegal(LHS.getValueType())) {
13592 // If this is efficiently invertible, canonicalize the LHSC/RHSC values
13593 // so that TrueC (the true value) is larger than FalseC.
13594 bool NeedsCondInvert = false;
13596 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue()) &&
13597 // Efficiently invertible.
13598 (Cond.getOpcode() == ISD::SETCC || // setcc -> invertible.
13599 (Cond.getOpcode() == ISD::XOR && // xor(X, C) -> invertible.
13600 isa<ConstantSDNode>(Cond.getOperand(1))))) {
13601 NeedsCondInvert = true;
13602 std::swap(TrueC, FalseC);
13605 // Optimize C ? 8 : 0 -> zext(C) << 3. Likewise for any pow2/0.
13606 if (FalseC->getAPIntValue() == 0 &&
13607 TrueC->getAPIntValue().isPowerOf2()) {
13608 if (NeedsCondInvert) // Invert the condition if needed.
13609 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
13610 DAG.getConstant(1, Cond.getValueType()));
13612 // Zero extend the condition if needed.
13613 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, LHS.getValueType(), Cond);
13615 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
13616 return DAG.getNode(ISD::SHL, DL, LHS.getValueType(), Cond,
13617 DAG.getConstant(ShAmt, MVT::i8));
13620 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst.
13621 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
13622 if (NeedsCondInvert) // Invert the condition if needed.
13623 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
13624 DAG.getConstant(1, Cond.getValueType()));
13626 // Zero extend the condition if needed.
13627 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
13628 FalseC->getValueType(0), Cond);
13629 return DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
13630 SDValue(FalseC, 0));
13633 // Optimize cases that will turn into an LEA instruction. This requires
13634 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
13635 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
13636 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
13637 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
13639 bool isFastMultiplier = false;
13641 switch ((unsigned char)Diff) {
13643 case 1: // result = add base, cond
13644 case 2: // result = lea base( , cond*2)
13645 case 3: // result = lea base(cond, cond*2)
13646 case 4: // result = lea base( , cond*4)
13647 case 5: // result = lea base(cond, cond*4)
13648 case 8: // result = lea base( , cond*8)
13649 case 9: // result = lea base(cond, cond*8)
13650 isFastMultiplier = true;
13655 if (isFastMultiplier) {
13656 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
13657 if (NeedsCondInvert) // Invert the condition if needed.
13658 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
13659 DAG.getConstant(1, Cond.getValueType()));
13661 // Zero extend the condition if needed.
13662 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
13664 // Scale the condition by the difference.
13666 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
13667 DAG.getConstant(Diff, Cond.getValueType()));
13669 // Add the base if non-zero.
13670 if (FalseC->getAPIntValue() != 0)
13671 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
13672 SDValue(FalseC, 0));
13679 // Canonicalize max and min:
13680 // (x > y) ? x : y -> (x >= y) ? x : y
13681 // (x < y) ? x : y -> (x <= y) ? x : y
13682 // This allows use of COND_S / COND_NS (see TranslateX86CC) which eliminates
13683 // the need for an extra compare
13684 // against zero. e.g.
13685 // (x - y) > 0 : (x - y) ? 0 -> (x - y) >= 0 : (x - y) ? 0
13687 // testl %edi, %edi
13689 // cmovgl %edi, %eax
13693 // cmovsl %eax, %edi
13694 if (N->getOpcode() == ISD::SELECT && Cond.getOpcode() == ISD::SETCC &&
13695 DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
13696 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
13697 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
13702 ISD::CondCode NewCC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGE;
13703 Cond = DAG.getSetCC(Cond.getDebugLoc(), Cond.getValueType(),
13704 Cond.getOperand(0), Cond.getOperand(1), NewCC);
13705 return DAG.getNode(ISD::SELECT, DL, VT, Cond, LHS, RHS);
13710 // If we know that this node is legal then we know that it is going to be
13711 // matched by one of the SSE/AVX BLEND instructions. These instructions only
13712 // depend on the highest bit in each word. Try to use SimplifyDemandedBits
13713 // to simplify previous instructions.
13714 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
13715 if (N->getOpcode() == ISD::VSELECT && DCI.isBeforeLegalizeOps() &&
13716 !DCI.isBeforeLegalize() && TLI.isOperationLegal(ISD::VSELECT, VT)) {
13717 unsigned BitWidth = Cond.getValueType().getScalarType().getSizeInBits();
13719 // Don't optimize vector selects that map to mask-registers.
13723 assert(BitWidth >= 8 && BitWidth <= 64 && "Invalid mask size");
13724 APInt DemandedMask = APInt::getHighBitsSet(BitWidth, 1);
13726 APInt KnownZero, KnownOne;
13727 TargetLowering::TargetLoweringOpt TLO(DAG, DCI.isBeforeLegalize(),
13728 DCI.isBeforeLegalizeOps());
13729 if (TLO.ShrinkDemandedConstant(Cond, DemandedMask) ||
13730 TLI.SimplifyDemandedBits(Cond, DemandedMask, KnownZero, KnownOne, TLO))
13731 DCI.CommitTargetLoweringOpt(TLO);
13737 // Check whether a boolean test is testing a boolean value generated by
13738 // X86ISD::SETCC. If so, return the operand of that SETCC and proper condition
13741 // Simplify the following patterns:
13742 // (Op (CMP (SETCC Cond EFLAGS) 1) EQ) or
13743 // (Op (CMP (SETCC Cond EFLAGS) 0) NEQ)
13744 // to (Op EFLAGS Cond)
13746 // (Op (CMP (SETCC Cond EFLAGS) 0) EQ) or
13747 // (Op (CMP (SETCC Cond EFLAGS) 1) NEQ)
13748 // to (Op EFLAGS !Cond)
13750 // where Op could be BRCOND or CMOV.
13752 static SDValue BoolTestSetCCCombine(SDValue Cmp, X86::CondCode &CC) {
13753 // Quit if not CMP and SUB with its value result used.
13754 if (Cmp.getOpcode() != X86ISD::CMP &&
13755 (Cmp.getOpcode() != X86ISD::SUB || Cmp.getNode()->hasAnyUseOfValue(0)))
13758 // Quit if not used as a boolean value.
13759 if (CC != X86::COND_E && CC != X86::COND_NE)
13762 // Check CMP operands. One of them should be 0 or 1 and the other should be
13763 // an SetCC or extended from it.
13764 SDValue Op1 = Cmp.getOperand(0);
13765 SDValue Op2 = Cmp.getOperand(1);
13768 const ConstantSDNode* C = 0;
13769 bool needOppositeCond = (CC == X86::COND_E);
13771 if ((C = dyn_cast<ConstantSDNode>(Op1)))
13773 else if ((C = dyn_cast<ConstantSDNode>(Op2)))
13775 else // Quit if all operands are not constants.
13778 if (C->getZExtValue() == 1)
13779 needOppositeCond = !needOppositeCond;
13780 else if (C->getZExtValue() != 0)
13781 // Quit if the constant is neither 0 or 1.
13784 // Skip 'zext' node.
13785 if (SetCC.getOpcode() == ISD::ZERO_EXTEND)
13786 SetCC = SetCC.getOperand(0);
13788 // Quit if not SETCC.
13789 // FIXME: So far we only handle the boolean value generated from SETCC. If
13790 // there is other ways to generate boolean values, we need handle them here
13792 if (SetCC.getOpcode() != X86ISD::SETCC)
13795 // Set the condition code or opposite one if necessary.
13796 CC = X86::CondCode(SetCC.getConstantOperandVal(0));
13797 if (needOppositeCond)
13798 CC = X86::GetOppositeBranchCondition(CC);
13800 return SetCC.getOperand(1);
13803 static bool IsValidFCMOVCondition(X86::CondCode CC) {
13819 /// Optimize X86ISD::CMOV [LHS, RHS, CONDCODE (e.g. X86::COND_NE), CONDVAL]
13820 static SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG,
13821 TargetLowering::DAGCombinerInfo &DCI) {
13822 DebugLoc DL = N->getDebugLoc();
13824 // If the flag operand isn't dead, don't touch this CMOV.
13825 if (N->getNumValues() == 2 && !SDValue(N, 1).use_empty())
13828 SDValue FalseOp = N->getOperand(0);
13829 SDValue TrueOp = N->getOperand(1);
13830 X86::CondCode CC = (X86::CondCode)N->getConstantOperandVal(2);
13831 SDValue Cond = N->getOperand(3);
13833 if (CC == X86::COND_E || CC == X86::COND_NE) {
13834 switch (Cond.getOpcode()) {
13838 // If operand of BSR / BSF are proven never zero, then ZF cannot be set.
13839 if (DAG.isKnownNeverZero(Cond.getOperand(0)))
13840 return (CC == X86::COND_E) ? FalseOp : TrueOp;
13846 Flags = BoolTestSetCCCombine(Cond, CC);
13847 if (Flags.getNode() &&
13848 // Extra check as FCMOV only supports a subset of X86 cond.
13849 (FalseOp.getValueType() != MVT::f80 || IsValidFCMOVCondition(CC))) {
13850 SDValue Ops[] = { FalseOp, TrueOp,
13851 DAG.getConstant(CC, MVT::i8), Flags };
13852 return DAG.getNode(X86ISD::CMOV, DL, N->getVTList(),
13853 Ops, array_lengthof(Ops));
13856 // If this is a select between two integer constants, try to do some
13857 // optimizations. Note that the operands are ordered the opposite of SELECT
13859 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(TrueOp)) {
13860 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(FalseOp)) {
13861 // Canonicalize the TrueC/FalseC values so that TrueC (the true value) is
13862 // larger than FalseC (the false value).
13863 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue())) {
13864 CC = X86::GetOppositeBranchCondition(CC);
13865 std::swap(TrueC, FalseC);
13868 // Optimize C ? 8 : 0 -> zext(setcc(C)) << 3. Likewise for any pow2/0.
13869 // This is efficient for any integer data type (including i8/i16) and
13871 if (FalseC->getAPIntValue() == 0 && TrueC->getAPIntValue().isPowerOf2()) {
13872 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
13873 DAG.getConstant(CC, MVT::i8), Cond);
13875 // Zero extend the condition if needed.
13876 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, TrueC->getValueType(0), Cond);
13878 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
13879 Cond = DAG.getNode(ISD::SHL, DL, Cond.getValueType(), Cond,
13880 DAG.getConstant(ShAmt, MVT::i8));
13881 if (N->getNumValues() == 2) // Dead flag value?
13882 return DCI.CombineTo(N, Cond, SDValue());
13886 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst. This is efficient
13887 // for any integer data type, including i8/i16.
13888 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
13889 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
13890 DAG.getConstant(CC, MVT::i8), Cond);
13892 // Zero extend the condition if needed.
13893 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
13894 FalseC->getValueType(0), Cond);
13895 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
13896 SDValue(FalseC, 0));
13898 if (N->getNumValues() == 2) // Dead flag value?
13899 return DCI.CombineTo(N, Cond, SDValue());
13903 // Optimize cases that will turn into an LEA instruction. This requires
13904 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
13905 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
13906 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
13907 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
13909 bool isFastMultiplier = false;
13911 switch ((unsigned char)Diff) {
13913 case 1: // result = add base, cond
13914 case 2: // result = lea base( , cond*2)
13915 case 3: // result = lea base(cond, cond*2)
13916 case 4: // result = lea base( , cond*4)
13917 case 5: // result = lea base(cond, cond*4)
13918 case 8: // result = lea base( , cond*8)
13919 case 9: // result = lea base(cond, cond*8)
13920 isFastMultiplier = true;
13925 if (isFastMultiplier) {
13926 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
13927 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
13928 DAG.getConstant(CC, MVT::i8), Cond);
13929 // Zero extend the condition if needed.
13930 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
13932 // Scale the condition by the difference.
13934 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
13935 DAG.getConstant(Diff, Cond.getValueType()));
13937 // Add the base if non-zero.
13938 if (FalseC->getAPIntValue() != 0)
13939 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
13940 SDValue(FalseC, 0));
13941 if (N->getNumValues() == 2) // Dead flag value?
13942 return DCI.CombineTo(N, Cond, SDValue());
13952 /// PerformMulCombine - Optimize a single multiply with constant into two
13953 /// in order to implement it with two cheaper instructions, e.g.
13954 /// LEA + SHL, LEA + LEA.
13955 static SDValue PerformMulCombine(SDNode *N, SelectionDAG &DAG,
13956 TargetLowering::DAGCombinerInfo &DCI) {
13957 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer())
13960 EVT VT = N->getValueType(0);
13961 if (VT != MVT::i64)
13964 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
13967 uint64_t MulAmt = C->getZExtValue();
13968 if (isPowerOf2_64(MulAmt) || MulAmt == 3 || MulAmt == 5 || MulAmt == 9)
13971 uint64_t MulAmt1 = 0;
13972 uint64_t MulAmt2 = 0;
13973 if ((MulAmt % 9) == 0) {
13975 MulAmt2 = MulAmt / 9;
13976 } else if ((MulAmt % 5) == 0) {
13978 MulAmt2 = MulAmt / 5;
13979 } else if ((MulAmt % 3) == 0) {
13981 MulAmt2 = MulAmt / 3;
13984 (isPowerOf2_64(MulAmt2) || MulAmt2 == 3 || MulAmt2 == 5 || MulAmt2 == 9)){
13985 DebugLoc DL = N->getDebugLoc();
13987 if (isPowerOf2_64(MulAmt2) &&
13988 !(N->hasOneUse() && N->use_begin()->getOpcode() == ISD::ADD))
13989 // If second multiplifer is pow2, issue it first. We want the multiply by
13990 // 3, 5, or 9 to be folded into the addressing mode unless the lone use
13992 std::swap(MulAmt1, MulAmt2);
13995 if (isPowerOf2_64(MulAmt1))
13996 NewMul = DAG.getNode(ISD::SHL, DL, VT, N->getOperand(0),
13997 DAG.getConstant(Log2_64(MulAmt1), MVT::i8));
13999 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, N->getOperand(0),
14000 DAG.getConstant(MulAmt1, VT));
14002 if (isPowerOf2_64(MulAmt2))
14003 NewMul = DAG.getNode(ISD::SHL, DL, VT, NewMul,
14004 DAG.getConstant(Log2_64(MulAmt2), MVT::i8));
14006 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, NewMul,
14007 DAG.getConstant(MulAmt2, VT));
14009 // Do not add new nodes to DAG combiner worklist.
14010 DCI.CombineTo(N, NewMul, false);
14015 static SDValue PerformSHLCombine(SDNode *N, SelectionDAG &DAG) {
14016 SDValue N0 = N->getOperand(0);
14017 SDValue N1 = N->getOperand(1);
14018 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
14019 EVT VT = N0.getValueType();
14021 // fold (shl (and (setcc_c), c1), c2) -> (and setcc_c, (c1 << c2))
14022 // since the result of setcc_c is all zero's or all ones.
14023 if (VT.isInteger() && !VT.isVector() &&
14024 N1C && N0.getOpcode() == ISD::AND &&
14025 N0.getOperand(1).getOpcode() == ISD::Constant) {
14026 SDValue N00 = N0.getOperand(0);
14027 if (N00.getOpcode() == X86ISD::SETCC_CARRY ||
14028 ((N00.getOpcode() == ISD::ANY_EXTEND ||
14029 N00.getOpcode() == ISD::ZERO_EXTEND) &&
14030 N00.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY)) {
14031 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
14032 APInt ShAmt = N1C->getAPIntValue();
14033 Mask = Mask.shl(ShAmt);
14035 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT,
14036 N00, DAG.getConstant(Mask, VT));
14041 // Hardware support for vector shifts is sparse which makes us scalarize the
14042 // vector operations in many cases. Also, on sandybridge ADD is faster than
14044 // (shl V, 1) -> add V,V
14045 if (isSplatVector(N1.getNode())) {
14046 assert(N0.getValueType().isVector() && "Invalid vector shift type");
14047 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1->getOperand(0));
14048 // We shift all of the values by one. In many cases we do not have
14049 // hardware support for this operation. This is better expressed as an ADD
14051 if (N1C && (1 == N1C->getZExtValue())) {
14052 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N0, N0);
14059 /// PerformShiftCombine - Transforms vector shift nodes to use vector shifts
14061 static SDValue PerformShiftCombine(SDNode* N, SelectionDAG &DAG,
14062 TargetLowering::DAGCombinerInfo &DCI,
14063 const X86Subtarget *Subtarget) {
14064 EVT VT = N->getValueType(0);
14065 if (N->getOpcode() == ISD::SHL) {
14066 SDValue V = PerformSHLCombine(N, DAG);
14067 if (V.getNode()) return V;
14070 // On X86 with SSE2 support, we can transform this to a vector shift if
14071 // all elements are shifted by the same amount. We can't do this in legalize
14072 // because the a constant vector is typically transformed to a constant pool
14073 // so we have no knowledge of the shift amount.
14074 if (!Subtarget->hasSSE2())
14077 if (VT != MVT::v2i64 && VT != MVT::v4i32 && VT != MVT::v8i16 &&
14078 (!Subtarget->hasAVX2() ||
14079 (VT != MVT::v4i64 && VT != MVT::v8i32 && VT != MVT::v16i16)))
14082 SDValue ShAmtOp = N->getOperand(1);
14083 EVT EltVT = VT.getVectorElementType();
14084 DebugLoc DL = N->getDebugLoc();
14085 SDValue BaseShAmt = SDValue();
14086 if (ShAmtOp.getOpcode() == ISD::BUILD_VECTOR) {
14087 unsigned NumElts = VT.getVectorNumElements();
14089 for (; i != NumElts; ++i) {
14090 SDValue Arg = ShAmtOp.getOperand(i);
14091 if (Arg.getOpcode() == ISD::UNDEF) continue;
14095 // Handle the case where the build_vector is all undef
14096 // FIXME: Should DAG allow this?
14100 for (; i != NumElts; ++i) {
14101 SDValue Arg = ShAmtOp.getOperand(i);
14102 if (Arg.getOpcode() == ISD::UNDEF) continue;
14103 if (Arg != BaseShAmt) {
14107 } else if (ShAmtOp.getOpcode() == ISD::VECTOR_SHUFFLE &&
14108 cast<ShuffleVectorSDNode>(ShAmtOp)->isSplat()) {
14109 SDValue InVec = ShAmtOp.getOperand(0);
14110 if (InVec.getOpcode() == ISD::BUILD_VECTOR) {
14111 unsigned NumElts = InVec.getValueType().getVectorNumElements();
14113 for (; i != NumElts; ++i) {
14114 SDValue Arg = InVec.getOperand(i);
14115 if (Arg.getOpcode() == ISD::UNDEF) continue;
14119 } else if (InVec.getOpcode() == ISD::INSERT_VECTOR_ELT) {
14120 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(InVec.getOperand(2))) {
14121 unsigned SplatIdx= cast<ShuffleVectorSDNode>(ShAmtOp)->getSplatIndex();
14122 if (C->getZExtValue() == SplatIdx)
14123 BaseShAmt = InVec.getOperand(1);
14126 if (BaseShAmt.getNode() == 0) {
14127 // Don't create instructions with illegal types after legalize
14129 if (!DAG.getTargetLoweringInfo().isTypeLegal(EltVT) &&
14130 !DCI.isBeforeLegalize())
14133 BaseShAmt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, EltVT, ShAmtOp,
14134 DAG.getIntPtrConstant(0));
14139 // The shift amount is an i32.
14140 if (EltVT.bitsGT(MVT::i32))
14141 BaseShAmt = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, BaseShAmt);
14142 else if (EltVT.bitsLT(MVT::i32))
14143 BaseShAmt = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i32, BaseShAmt);
14145 // The shift amount is identical so we can do a vector shift.
14146 SDValue ValOp = N->getOperand(0);
14147 switch (N->getOpcode()) {
14149 llvm_unreachable("Unknown shift opcode!");
14151 switch (VT.getSimpleVT().SimpleTy) {
14152 default: return SDValue();
14159 return getTargetVShiftNode(X86ISD::VSHLI, DL, VT, ValOp, BaseShAmt, DAG);
14162 switch (VT.getSimpleVT().SimpleTy) {
14163 default: return SDValue();
14168 return getTargetVShiftNode(X86ISD::VSRAI, DL, VT, ValOp, BaseShAmt, DAG);
14171 switch (VT.getSimpleVT().SimpleTy) {
14172 default: return SDValue();
14179 return getTargetVShiftNode(X86ISD::VSRLI, DL, VT, ValOp, BaseShAmt, DAG);
14185 // CMPEQCombine - Recognize the distinctive (AND (setcc ...) (setcc ..))
14186 // where both setccs reference the same FP CMP, and rewrite for CMPEQSS
14187 // and friends. Likewise for OR -> CMPNEQSS.
14188 static SDValue CMPEQCombine(SDNode *N, SelectionDAG &DAG,
14189 TargetLowering::DAGCombinerInfo &DCI,
14190 const X86Subtarget *Subtarget) {
14193 // SSE1 supports CMP{eq|ne}SS, and SSE2 added CMP{eq|ne}SD, but
14194 // we're requiring SSE2 for both.
14195 if (Subtarget->hasSSE2() && isAndOrOfSetCCs(SDValue(N, 0U), opcode)) {
14196 SDValue N0 = N->getOperand(0);
14197 SDValue N1 = N->getOperand(1);
14198 SDValue CMP0 = N0->getOperand(1);
14199 SDValue CMP1 = N1->getOperand(1);
14200 DebugLoc DL = N->getDebugLoc();
14202 // The SETCCs should both refer to the same CMP.
14203 if (CMP0.getOpcode() != X86ISD::CMP || CMP0 != CMP1)
14206 SDValue CMP00 = CMP0->getOperand(0);
14207 SDValue CMP01 = CMP0->getOperand(1);
14208 EVT VT = CMP00.getValueType();
14210 if (VT == MVT::f32 || VT == MVT::f64) {
14211 bool ExpectingFlags = false;
14212 // Check for any users that want flags:
14213 for (SDNode::use_iterator UI = N->use_begin(),
14215 !ExpectingFlags && UI != UE; ++UI)
14216 switch (UI->getOpcode()) {
14221 ExpectingFlags = true;
14223 case ISD::CopyToReg:
14224 case ISD::SIGN_EXTEND:
14225 case ISD::ZERO_EXTEND:
14226 case ISD::ANY_EXTEND:
14230 if (!ExpectingFlags) {
14231 enum X86::CondCode cc0 = (enum X86::CondCode)N0.getConstantOperandVal(0);
14232 enum X86::CondCode cc1 = (enum X86::CondCode)N1.getConstantOperandVal(0);
14234 if (cc1 == X86::COND_E || cc1 == X86::COND_NE) {
14235 X86::CondCode tmp = cc0;
14240 if ((cc0 == X86::COND_E && cc1 == X86::COND_NP) ||
14241 (cc0 == X86::COND_NE && cc1 == X86::COND_P)) {
14242 bool is64BitFP = (CMP00.getValueType() == MVT::f64);
14243 X86ISD::NodeType NTOperator = is64BitFP ?
14244 X86ISD::FSETCCsd : X86ISD::FSETCCss;
14245 // FIXME: need symbolic constants for these magic numbers.
14246 // See X86ATTInstPrinter.cpp:printSSECC().
14247 unsigned x86cc = (cc0 == X86::COND_E) ? 0 : 4;
14248 SDValue OnesOrZeroesF = DAG.getNode(NTOperator, DL, MVT::f32, CMP00, CMP01,
14249 DAG.getConstant(x86cc, MVT::i8));
14250 SDValue OnesOrZeroesI = DAG.getNode(ISD::BITCAST, DL, MVT::i32,
14252 SDValue ANDed = DAG.getNode(ISD::AND, DL, MVT::i32, OnesOrZeroesI,
14253 DAG.getConstant(1, MVT::i32));
14254 SDValue OneBitOfTruth = DAG.getNode(ISD::TRUNCATE, DL, MVT::i8, ANDed);
14255 return OneBitOfTruth;
14263 /// CanFoldXORWithAllOnes - Test whether the XOR operand is a AllOnes vector
14264 /// so it can be folded inside ANDNP.
14265 static bool CanFoldXORWithAllOnes(const SDNode *N) {
14266 EVT VT = N->getValueType(0);
14268 // Match direct AllOnes for 128 and 256-bit vectors
14269 if (ISD::isBuildVectorAllOnes(N))
14272 // Look through a bit convert.
14273 if (N->getOpcode() == ISD::BITCAST)
14274 N = N->getOperand(0).getNode();
14276 // Sometimes the operand may come from a insert_subvector building a 256-bit
14278 if (VT.is256BitVector() &&
14279 N->getOpcode() == ISD::INSERT_SUBVECTOR) {
14280 SDValue V1 = N->getOperand(0);
14281 SDValue V2 = N->getOperand(1);
14283 if (V1.getOpcode() == ISD::INSERT_SUBVECTOR &&
14284 V1.getOperand(0).getOpcode() == ISD::UNDEF &&
14285 ISD::isBuildVectorAllOnes(V1.getOperand(1).getNode()) &&
14286 ISD::isBuildVectorAllOnes(V2.getNode()))
14293 static SDValue PerformAndCombine(SDNode *N, SelectionDAG &DAG,
14294 TargetLowering::DAGCombinerInfo &DCI,
14295 const X86Subtarget *Subtarget) {
14296 if (DCI.isBeforeLegalizeOps())
14299 SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget);
14303 EVT VT = N->getValueType(0);
14305 // Create ANDN, BLSI, and BLSR instructions
14306 // BLSI is X & (-X)
14307 // BLSR is X & (X-1)
14308 if (Subtarget->hasBMI() && (VT == MVT::i32 || VT == MVT::i64)) {
14309 SDValue N0 = N->getOperand(0);
14310 SDValue N1 = N->getOperand(1);
14311 DebugLoc DL = N->getDebugLoc();
14313 // Check LHS for not
14314 if (N0.getOpcode() == ISD::XOR && isAllOnes(N0.getOperand(1)))
14315 return DAG.getNode(X86ISD::ANDN, DL, VT, N0.getOperand(0), N1);
14316 // Check RHS for not
14317 if (N1.getOpcode() == ISD::XOR && isAllOnes(N1.getOperand(1)))
14318 return DAG.getNode(X86ISD::ANDN, DL, VT, N1.getOperand(0), N0);
14320 // Check LHS for neg
14321 if (N0.getOpcode() == ISD::SUB && N0.getOperand(1) == N1 &&
14322 isZero(N0.getOperand(0)))
14323 return DAG.getNode(X86ISD::BLSI, DL, VT, N1);
14325 // Check RHS for neg
14326 if (N1.getOpcode() == ISD::SUB && N1.getOperand(1) == N0 &&
14327 isZero(N1.getOperand(0)))
14328 return DAG.getNode(X86ISD::BLSI, DL, VT, N0);
14330 // Check LHS for X-1
14331 if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1 &&
14332 isAllOnes(N0.getOperand(1)))
14333 return DAG.getNode(X86ISD::BLSR, DL, VT, N1);
14335 // Check RHS for X-1
14336 if (N1.getOpcode() == ISD::ADD && N1.getOperand(0) == N0 &&
14337 isAllOnes(N1.getOperand(1)))
14338 return DAG.getNode(X86ISD::BLSR, DL, VT, N0);
14343 // Want to form ANDNP nodes:
14344 // 1) In the hopes of then easily combining them with OR and AND nodes
14345 // to form PBLEND/PSIGN.
14346 // 2) To match ANDN packed intrinsics
14347 if (VT != MVT::v2i64 && VT != MVT::v4i64)
14350 SDValue N0 = N->getOperand(0);
14351 SDValue N1 = N->getOperand(1);
14352 DebugLoc DL = N->getDebugLoc();
14354 // Check LHS for vnot
14355 if (N0.getOpcode() == ISD::XOR &&
14356 //ISD::isBuildVectorAllOnes(N0.getOperand(1).getNode()))
14357 CanFoldXORWithAllOnes(N0.getOperand(1).getNode()))
14358 return DAG.getNode(X86ISD::ANDNP, DL, VT, N0.getOperand(0), N1);
14360 // Check RHS for vnot
14361 if (N1.getOpcode() == ISD::XOR &&
14362 //ISD::isBuildVectorAllOnes(N1.getOperand(1).getNode()))
14363 CanFoldXORWithAllOnes(N1.getOperand(1).getNode()))
14364 return DAG.getNode(X86ISD::ANDNP, DL, VT, N1.getOperand(0), N0);
14369 static SDValue PerformOrCombine(SDNode *N, SelectionDAG &DAG,
14370 TargetLowering::DAGCombinerInfo &DCI,
14371 const X86Subtarget *Subtarget) {
14372 if (DCI.isBeforeLegalizeOps())
14375 SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget);
14379 EVT VT = N->getValueType(0);
14381 SDValue N0 = N->getOperand(0);
14382 SDValue N1 = N->getOperand(1);
14384 // look for psign/blend
14385 if (VT == MVT::v2i64 || VT == MVT::v4i64) {
14386 if (!Subtarget->hasSSSE3() ||
14387 (VT == MVT::v4i64 && !Subtarget->hasAVX2()))
14390 // Canonicalize pandn to RHS
14391 if (N0.getOpcode() == X86ISD::ANDNP)
14393 // or (and (m, y), (pandn m, x))
14394 if (N0.getOpcode() == ISD::AND && N1.getOpcode() == X86ISD::ANDNP) {
14395 SDValue Mask = N1.getOperand(0);
14396 SDValue X = N1.getOperand(1);
14398 if (N0.getOperand(0) == Mask)
14399 Y = N0.getOperand(1);
14400 if (N0.getOperand(1) == Mask)
14401 Y = N0.getOperand(0);
14403 // Check to see if the mask appeared in both the AND and ANDNP and
14407 // Validate that X, Y, and Mask are BIT_CONVERTS, and see through them.
14408 // Look through mask bitcast.
14409 if (Mask.getOpcode() == ISD::BITCAST)
14410 Mask = Mask.getOperand(0);
14411 if (X.getOpcode() == ISD::BITCAST)
14412 X = X.getOperand(0);
14413 if (Y.getOpcode() == ISD::BITCAST)
14414 Y = Y.getOperand(0);
14416 EVT MaskVT = Mask.getValueType();
14418 // Validate that the Mask operand is a vector sra node.
14419 // FIXME: what to do for bytes, since there is a psignb/pblendvb, but
14420 // there is no psrai.b
14421 if (Mask.getOpcode() != X86ISD::VSRAI)
14424 // Check that the SRA is all signbits.
14425 SDValue SraC = Mask.getOperand(1);
14426 unsigned SraAmt = cast<ConstantSDNode>(SraC)->getZExtValue();
14427 unsigned EltBits = MaskVT.getVectorElementType().getSizeInBits();
14428 if ((SraAmt + 1) != EltBits)
14431 DebugLoc DL = N->getDebugLoc();
14433 // Now we know we at least have a plendvb with the mask val. See if
14434 // we can form a psignb/w/d.
14435 // psign = x.type == y.type == mask.type && y = sub(0, x);
14436 if (Y.getOpcode() == ISD::SUB && Y.getOperand(1) == X &&
14437 ISD::isBuildVectorAllZeros(Y.getOperand(0).getNode()) &&
14438 X.getValueType() == MaskVT && Y.getValueType() == MaskVT) {
14439 assert((EltBits == 8 || EltBits == 16 || EltBits == 32) &&
14440 "Unsupported VT for PSIGN");
14441 Mask = DAG.getNode(X86ISD::PSIGN, DL, MaskVT, X, Mask.getOperand(0));
14442 return DAG.getNode(ISD::BITCAST, DL, VT, Mask);
14444 // PBLENDVB only available on SSE 4.1
14445 if (!Subtarget->hasSSE41())
14448 EVT BlendVT = (VT == MVT::v4i64) ? MVT::v32i8 : MVT::v16i8;
14450 X = DAG.getNode(ISD::BITCAST, DL, BlendVT, X);
14451 Y = DAG.getNode(ISD::BITCAST, DL, BlendVT, Y);
14452 Mask = DAG.getNode(ISD::BITCAST, DL, BlendVT, Mask);
14453 Mask = DAG.getNode(ISD::VSELECT, DL, BlendVT, Mask, Y, X);
14454 return DAG.getNode(ISD::BITCAST, DL, VT, Mask);
14458 if (VT != MVT::i16 && VT != MVT::i32 && VT != MVT::i64)
14461 // fold (or (x << c) | (y >> (64 - c))) ==> (shld64 x, y, c)
14462 if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL)
14464 if (N0.getOpcode() != ISD::SHL || N1.getOpcode() != ISD::SRL)
14466 if (!N0.hasOneUse() || !N1.hasOneUse())
14469 SDValue ShAmt0 = N0.getOperand(1);
14470 if (ShAmt0.getValueType() != MVT::i8)
14472 SDValue ShAmt1 = N1.getOperand(1);
14473 if (ShAmt1.getValueType() != MVT::i8)
14475 if (ShAmt0.getOpcode() == ISD::TRUNCATE)
14476 ShAmt0 = ShAmt0.getOperand(0);
14477 if (ShAmt1.getOpcode() == ISD::TRUNCATE)
14478 ShAmt1 = ShAmt1.getOperand(0);
14480 DebugLoc DL = N->getDebugLoc();
14481 unsigned Opc = X86ISD::SHLD;
14482 SDValue Op0 = N0.getOperand(0);
14483 SDValue Op1 = N1.getOperand(0);
14484 if (ShAmt0.getOpcode() == ISD::SUB) {
14485 Opc = X86ISD::SHRD;
14486 std::swap(Op0, Op1);
14487 std::swap(ShAmt0, ShAmt1);
14490 unsigned Bits = VT.getSizeInBits();
14491 if (ShAmt1.getOpcode() == ISD::SUB) {
14492 SDValue Sum = ShAmt1.getOperand(0);
14493 if (ConstantSDNode *SumC = dyn_cast<ConstantSDNode>(Sum)) {
14494 SDValue ShAmt1Op1 = ShAmt1.getOperand(1);
14495 if (ShAmt1Op1.getNode()->getOpcode() == ISD::TRUNCATE)
14496 ShAmt1Op1 = ShAmt1Op1.getOperand(0);
14497 if (SumC->getSExtValue() == Bits && ShAmt1Op1 == ShAmt0)
14498 return DAG.getNode(Opc, DL, VT,
14500 DAG.getNode(ISD::TRUNCATE, DL,
14503 } else if (ConstantSDNode *ShAmt1C = dyn_cast<ConstantSDNode>(ShAmt1)) {
14504 ConstantSDNode *ShAmt0C = dyn_cast<ConstantSDNode>(ShAmt0);
14506 ShAmt0C->getSExtValue() + ShAmt1C->getSExtValue() == Bits)
14507 return DAG.getNode(Opc, DL, VT,
14508 N0.getOperand(0), N1.getOperand(0),
14509 DAG.getNode(ISD::TRUNCATE, DL,
14516 // Generate NEG and CMOV for integer abs.
14517 static SDValue performIntegerAbsCombine(SDNode *N, SelectionDAG &DAG) {
14518 EVT VT = N->getValueType(0);
14520 // Since X86 does not have CMOV for 8-bit integer, we don't convert
14521 // 8-bit integer abs to NEG and CMOV.
14522 if (VT.isInteger() && VT.getSizeInBits() == 8)
14525 SDValue N0 = N->getOperand(0);
14526 SDValue N1 = N->getOperand(1);
14527 DebugLoc DL = N->getDebugLoc();
14529 // Check pattern of XOR(ADD(X,Y), Y) where Y is SRA(X, size(X)-1)
14530 // and change it to SUB and CMOV.
14531 if (VT.isInteger() && N->getOpcode() == ISD::XOR &&
14532 N0.getOpcode() == ISD::ADD &&
14533 N0.getOperand(1) == N1 &&
14534 N1.getOpcode() == ISD::SRA &&
14535 N1.getOperand(0) == N0.getOperand(0))
14536 if (ConstantSDNode *Y1C = dyn_cast<ConstantSDNode>(N1.getOperand(1)))
14537 if (Y1C->getAPIntValue() == VT.getSizeInBits()-1) {
14538 // Generate SUB & CMOV.
14539 SDValue Neg = DAG.getNode(X86ISD::SUB, DL, DAG.getVTList(VT, MVT::i32),
14540 DAG.getConstant(0, VT), N0.getOperand(0));
14542 SDValue Ops[] = { N0.getOperand(0), Neg,
14543 DAG.getConstant(X86::COND_GE, MVT::i8),
14544 SDValue(Neg.getNode(), 1) };
14545 return DAG.getNode(X86ISD::CMOV, DL, DAG.getVTList(VT, MVT::Glue),
14546 Ops, array_lengthof(Ops));
14551 // PerformXorCombine - Attempts to turn XOR nodes into BLSMSK nodes
14552 static SDValue PerformXorCombine(SDNode *N, SelectionDAG &DAG,
14553 TargetLowering::DAGCombinerInfo &DCI,
14554 const X86Subtarget *Subtarget) {
14555 if (DCI.isBeforeLegalizeOps())
14558 if (Subtarget->hasCMov()) {
14559 SDValue RV = performIntegerAbsCombine(N, DAG);
14564 // Try forming BMI if it is available.
14565 if (!Subtarget->hasBMI())
14568 EVT VT = N->getValueType(0);
14570 if (VT != MVT::i32 && VT != MVT::i64)
14573 assert(Subtarget->hasBMI() && "Creating BLSMSK requires BMI instructions");
14575 // Create BLSMSK instructions by finding X ^ (X-1)
14576 SDValue N0 = N->getOperand(0);
14577 SDValue N1 = N->getOperand(1);
14578 DebugLoc DL = N->getDebugLoc();
14580 if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1 &&
14581 isAllOnes(N0.getOperand(1)))
14582 return DAG.getNode(X86ISD::BLSMSK, DL, VT, N1);
14584 if (N1.getOpcode() == ISD::ADD && N1.getOperand(0) == N0 &&
14585 isAllOnes(N1.getOperand(1)))
14586 return DAG.getNode(X86ISD::BLSMSK, DL, VT, N0);
14591 /// PerformLOADCombine - Do target-specific dag combines on LOAD nodes.
14592 static SDValue PerformLOADCombine(SDNode *N, SelectionDAG &DAG,
14593 TargetLowering::DAGCombinerInfo &DCI,
14594 const X86Subtarget *Subtarget) {
14595 LoadSDNode *Ld = cast<LoadSDNode>(N);
14596 EVT RegVT = Ld->getValueType(0);
14597 EVT MemVT = Ld->getMemoryVT();
14598 DebugLoc dl = Ld->getDebugLoc();
14599 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
14601 ISD::LoadExtType Ext = Ld->getExtensionType();
14603 // If this is a vector EXT Load then attempt to optimize it using a
14604 // shuffle. We need SSE4 for the shuffles.
14605 // TODO: It is possible to support ZExt by zeroing the undef values
14606 // during the shuffle phase or after the shuffle.
14607 if (RegVT.isVector() && RegVT.isInteger() &&
14608 Ext == ISD::EXTLOAD && Subtarget->hasSSE41()) {
14609 assert(MemVT != RegVT && "Cannot extend to the same type");
14610 assert(MemVT.isVector() && "Must load a vector from memory");
14612 unsigned NumElems = RegVT.getVectorNumElements();
14613 unsigned RegSz = RegVT.getSizeInBits();
14614 unsigned MemSz = MemVT.getSizeInBits();
14615 assert(RegSz > MemSz && "Register size must be greater than the mem size");
14617 // All sizes must be a power of two.
14618 if (!isPowerOf2_32(RegSz * MemSz * NumElems))
14621 // Attempt to load the original value using scalar loads.
14622 // Find the largest scalar type that divides the total loaded size.
14623 MVT SclrLoadTy = MVT::i8;
14624 for (unsigned tp = MVT::FIRST_INTEGER_VALUETYPE;
14625 tp < MVT::LAST_INTEGER_VALUETYPE; ++tp) {
14626 MVT Tp = (MVT::SimpleValueType)tp;
14627 if (TLI.isTypeLegal(Tp) && ((MemSz % Tp.getSizeInBits()) == 0)) {
14632 // On 32bit systems, we can't save 64bit integers. Try bitcasting to F64.
14633 if (TLI.isTypeLegal(MVT::f64) && SclrLoadTy.getSizeInBits() < 64 &&
14635 SclrLoadTy = MVT::f64;
14637 // Calculate the number of scalar loads that we need to perform
14638 // in order to load our vector from memory.
14639 unsigned NumLoads = MemSz / SclrLoadTy.getSizeInBits();
14641 // Represent our vector as a sequence of elements which are the
14642 // largest scalar that we can load.
14643 EVT LoadUnitVecVT = EVT::getVectorVT(*DAG.getContext(), SclrLoadTy,
14644 RegSz/SclrLoadTy.getSizeInBits());
14646 // Represent the data using the same element type that is stored in
14647 // memory. In practice, we ''widen'' MemVT.
14648 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(), MemVT.getScalarType(),
14649 RegSz/MemVT.getScalarType().getSizeInBits());
14651 assert(WideVecVT.getSizeInBits() == LoadUnitVecVT.getSizeInBits() &&
14652 "Invalid vector type");
14654 // We can't shuffle using an illegal type.
14655 if (!TLI.isTypeLegal(WideVecVT))
14658 SmallVector<SDValue, 8> Chains;
14659 SDValue Ptr = Ld->getBasePtr();
14660 SDValue Increment = DAG.getConstant(SclrLoadTy.getSizeInBits()/8,
14661 TLI.getPointerTy());
14662 SDValue Res = DAG.getUNDEF(LoadUnitVecVT);
14664 for (unsigned i = 0; i < NumLoads; ++i) {
14665 // Perform a single load.
14666 SDValue ScalarLoad = DAG.getLoad(SclrLoadTy, dl, Ld->getChain(),
14667 Ptr, Ld->getPointerInfo(),
14668 Ld->isVolatile(), Ld->isNonTemporal(),
14669 Ld->isInvariant(), Ld->getAlignment());
14670 Chains.push_back(ScalarLoad.getValue(1));
14671 // Create the first element type using SCALAR_TO_VECTOR in order to avoid
14672 // another round of DAGCombining.
14674 Res = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, LoadUnitVecVT, ScalarLoad);
14676 Res = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, LoadUnitVecVT, Res,
14677 ScalarLoad, DAG.getIntPtrConstant(i));
14679 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
14682 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Chains[0],
14685 // Bitcast the loaded value to a vector of the original element type, in
14686 // the size of the target vector type.
14687 SDValue SlicedVec = DAG.getNode(ISD::BITCAST, dl, WideVecVT, Res);
14688 unsigned SizeRatio = RegSz/MemSz;
14690 // Redistribute the loaded elements into the different locations.
14691 SmallVector<int, 8> ShuffleVec(NumElems * SizeRatio, -1);
14692 for (unsigned i = 0; i != NumElems; ++i)
14693 ShuffleVec[i*SizeRatio] = i;
14695 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, SlicedVec,
14696 DAG.getUNDEF(WideVecVT),
14699 // Bitcast to the requested type.
14700 Shuff = DAG.getNode(ISD::BITCAST, dl, RegVT, Shuff);
14701 // Replace the original load with the new sequence
14702 // and return the new chain.
14703 return DCI.CombineTo(N, Shuff, TF, true);
14709 /// PerformSTORECombine - Do target-specific dag combines on STORE nodes.
14710 static SDValue PerformSTORECombine(SDNode *N, SelectionDAG &DAG,
14711 const X86Subtarget *Subtarget) {
14712 StoreSDNode *St = cast<StoreSDNode>(N);
14713 EVT VT = St->getValue().getValueType();
14714 EVT StVT = St->getMemoryVT();
14715 DebugLoc dl = St->getDebugLoc();
14716 SDValue StoredVal = St->getOperand(1);
14717 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
14719 // If we are saving a concatenation of two XMM registers, perform two stores.
14720 // On Sandy Bridge, 256-bit memory operations are executed by two
14721 // 128-bit ports. However, on Haswell it is better to issue a single 256-bit
14722 // memory operation.
14723 if (VT.is256BitVector() && !Subtarget->hasAVX2() &&
14724 StoredVal.getNode()->getOpcode() == ISD::CONCAT_VECTORS &&
14725 StoredVal.getNumOperands() == 2) {
14726 SDValue Value0 = StoredVal.getOperand(0);
14727 SDValue Value1 = StoredVal.getOperand(1);
14729 SDValue Stride = DAG.getConstant(16, TLI.getPointerTy());
14730 SDValue Ptr0 = St->getBasePtr();
14731 SDValue Ptr1 = DAG.getNode(ISD::ADD, dl, Ptr0.getValueType(), Ptr0, Stride);
14733 SDValue Ch0 = DAG.getStore(St->getChain(), dl, Value0, Ptr0,
14734 St->getPointerInfo(), St->isVolatile(),
14735 St->isNonTemporal(), St->getAlignment());
14736 SDValue Ch1 = DAG.getStore(St->getChain(), dl, Value1, Ptr1,
14737 St->getPointerInfo(), St->isVolatile(),
14738 St->isNonTemporal(), St->getAlignment());
14739 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Ch0, Ch1);
14742 // Optimize trunc store (of multiple scalars) to shuffle and store.
14743 // First, pack all of the elements in one place. Next, store to memory
14744 // in fewer chunks.
14745 if (St->isTruncatingStore() && VT.isVector()) {
14746 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
14747 unsigned NumElems = VT.getVectorNumElements();
14748 assert(StVT != VT && "Cannot truncate to the same type");
14749 unsigned FromSz = VT.getVectorElementType().getSizeInBits();
14750 unsigned ToSz = StVT.getVectorElementType().getSizeInBits();
14752 // From, To sizes and ElemCount must be pow of two
14753 if (!isPowerOf2_32(NumElems * FromSz * ToSz)) return SDValue();
14754 // We are going to use the original vector elt for storing.
14755 // Accumulated smaller vector elements must be a multiple of the store size.
14756 if (0 != (NumElems * FromSz) % ToSz) return SDValue();
14758 unsigned SizeRatio = FromSz / ToSz;
14760 assert(SizeRatio * NumElems * ToSz == VT.getSizeInBits());
14762 // Create a type on which we perform the shuffle
14763 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(),
14764 StVT.getScalarType(), NumElems*SizeRatio);
14766 assert(WideVecVT.getSizeInBits() == VT.getSizeInBits());
14768 SDValue WideVec = DAG.getNode(ISD::BITCAST, dl, WideVecVT, St->getValue());
14769 SmallVector<int, 8> ShuffleVec(NumElems * SizeRatio, -1);
14770 for (unsigned i = 0; i != NumElems; ++i)
14771 ShuffleVec[i] = i * SizeRatio;
14773 // Can't shuffle using an illegal type.
14774 if (!TLI.isTypeLegal(WideVecVT))
14777 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, WideVec,
14778 DAG.getUNDEF(WideVecVT),
14780 // At this point all of the data is stored at the bottom of the
14781 // register. We now need to save it to mem.
14783 // Find the largest store unit
14784 MVT StoreType = MVT::i8;
14785 for (unsigned tp = MVT::FIRST_INTEGER_VALUETYPE;
14786 tp < MVT::LAST_INTEGER_VALUETYPE; ++tp) {
14787 MVT Tp = (MVT::SimpleValueType)tp;
14788 if (TLI.isTypeLegal(Tp) && Tp.getSizeInBits() <= NumElems * ToSz)
14792 // On 32bit systems, we can't save 64bit integers. Try bitcasting to F64.
14793 if (TLI.isTypeLegal(MVT::f64) && StoreType.getSizeInBits() < 64 &&
14794 (64 <= NumElems * ToSz))
14795 StoreType = MVT::f64;
14797 // Bitcast the original vector into a vector of store-size units
14798 EVT StoreVecVT = EVT::getVectorVT(*DAG.getContext(),
14799 StoreType, VT.getSizeInBits()/StoreType.getSizeInBits());
14800 assert(StoreVecVT.getSizeInBits() == VT.getSizeInBits());
14801 SDValue ShuffWide = DAG.getNode(ISD::BITCAST, dl, StoreVecVT, Shuff);
14802 SmallVector<SDValue, 8> Chains;
14803 SDValue Increment = DAG.getConstant(StoreType.getSizeInBits()/8,
14804 TLI.getPointerTy());
14805 SDValue Ptr = St->getBasePtr();
14807 // Perform one or more big stores into memory.
14808 for (unsigned i=0, e=(ToSz*NumElems)/StoreType.getSizeInBits(); i!=e; ++i) {
14809 SDValue SubVec = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
14810 StoreType, ShuffWide,
14811 DAG.getIntPtrConstant(i));
14812 SDValue Ch = DAG.getStore(St->getChain(), dl, SubVec, Ptr,
14813 St->getPointerInfo(), St->isVolatile(),
14814 St->isNonTemporal(), St->getAlignment());
14815 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
14816 Chains.push_back(Ch);
14819 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Chains[0],
14824 // Turn load->store of MMX types into GPR load/stores. This avoids clobbering
14825 // the FP state in cases where an emms may be missing.
14826 // A preferable solution to the general problem is to figure out the right
14827 // places to insert EMMS. This qualifies as a quick hack.
14829 // Similarly, turn load->store of i64 into double load/stores in 32-bit mode.
14830 if (VT.getSizeInBits() != 64)
14833 const Function *F = DAG.getMachineFunction().getFunction();
14834 bool NoImplicitFloatOps = F->hasFnAttr(Attribute::NoImplicitFloat);
14835 bool F64IsLegal = !DAG.getTarget().Options.UseSoftFloat && !NoImplicitFloatOps
14836 && Subtarget->hasSSE2();
14837 if ((VT.isVector() ||
14838 (VT == MVT::i64 && F64IsLegal && !Subtarget->is64Bit())) &&
14839 isa<LoadSDNode>(St->getValue()) &&
14840 !cast<LoadSDNode>(St->getValue())->isVolatile() &&
14841 St->getChain().hasOneUse() && !St->isVolatile()) {
14842 SDNode* LdVal = St->getValue().getNode();
14843 LoadSDNode *Ld = 0;
14844 int TokenFactorIndex = -1;
14845 SmallVector<SDValue, 8> Ops;
14846 SDNode* ChainVal = St->getChain().getNode();
14847 // Must be a store of a load. We currently handle two cases: the load
14848 // is a direct child, and it's under an intervening TokenFactor. It is
14849 // possible to dig deeper under nested TokenFactors.
14850 if (ChainVal == LdVal)
14851 Ld = cast<LoadSDNode>(St->getChain());
14852 else if (St->getValue().hasOneUse() &&
14853 ChainVal->getOpcode() == ISD::TokenFactor) {
14854 for (unsigned i = 0, e = ChainVal->getNumOperands(); i != e; ++i) {
14855 if (ChainVal->getOperand(i).getNode() == LdVal) {
14856 TokenFactorIndex = i;
14857 Ld = cast<LoadSDNode>(St->getValue());
14859 Ops.push_back(ChainVal->getOperand(i));
14863 if (!Ld || !ISD::isNormalLoad(Ld))
14866 // If this is not the MMX case, i.e. we are just turning i64 load/store
14867 // into f64 load/store, avoid the transformation if there are multiple
14868 // uses of the loaded value.
14869 if (!VT.isVector() && !Ld->hasNUsesOfValue(1, 0))
14872 DebugLoc LdDL = Ld->getDebugLoc();
14873 DebugLoc StDL = N->getDebugLoc();
14874 // If we are a 64-bit capable x86, lower to a single movq load/store pair.
14875 // Otherwise, if it's legal to use f64 SSE instructions, use f64 load/store
14877 if (Subtarget->is64Bit() || F64IsLegal) {
14878 EVT LdVT = Subtarget->is64Bit() ? MVT::i64 : MVT::f64;
14879 SDValue NewLd = DAG.getLoad(LdVT, LdDL, Ld->getChain(), Ld->getBasePtr(),
14880 Ld->getPointerInfo(), Ld->isVolatile(),
14881 Ld->isNonTemporal(), Ld->isInvariant(),
14882 Ld->getAlignment());
14883 SDValue NewChain = NewLd.getValue(1);
14884 if (TokenFactorIndex != -1) {
14885 Ops.push_back(NewChain);
14886 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, &Ops[0],
14889 return DAG.getStore(NewChain, StDL, NewLd, St->getBasePtr(),
14890 St->getPointerInfo(),
14891 St->isVolatile(), St->isNonTemporal(),
14892 St->getAlignment());
14895 // Otherwise, lower to two pairs of 32-bit loads / stores.
14896 SDValue LoAddr = Ld->getBasePtr();
14897 SDValue HiAddr = DAG.getNode(ISD::ADD, LdDL, MVT::i32, LoAddr,
14898 DAG.getConstant(4, MVT::i32));
14900 SDValue LoLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), LoAddr,
14901 Ld->getPointerInfo(),
14902 Ld->isVolatile(), Ld->isNonTemporal(),
14903 Ld->isInvariant(), Ld->getAlignment());
14904 SDValue HiLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), HiAddr,
14905 Ld->getPointerInfo().getWithOffset(4),
14906 Ld->isVolatile(), Ld->isNonTemporal(),
14908 MinAlign(Ld->getAlignment(), 4));
14910 SDValue NewChain = LoLd.getValue(1);
14911 if (TokenFactorIndex != -1) {
14912 Ops.push_back(LoLd);
14913 Ops.push_back(HiLd);
14914 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, &Ops[0],
14918 LoAddr = St->getBasePtr();
14919 HiAddr = DAG.getNode(ISD::ADD, StDL, MVT::i32, LoAddr,
14920 DAG.getConstant(4, MVT::i32));
14922 SDValue LoSt = DAG.getStore(NewChain, StDL, LoLd, LoAddr,
14923 St->getPointerInfo(),
14924 St->isVolatile(), St->isNonTemporal(),
14925 St->getAlignment());
14926 SDValue HiSt = DAG.getStore(NewChain, StDL, HiLd, HiAddr,
14927 St->getPointerInfo().getWithOffset(4),
14929 St->isNonTemporal(),
14930 MinAlign(St->getAlignment(), 4));
14931 return DAG.getNode(ISD::TokenFactor, StDL, MVT::Other, LoSt, HiSt);
14936 /// isHorizontalBinOp - Return 'true' if this vector operation is "horizontal"
14937 /// and return the operands for the horizontal operation in LHS and RHS. A
14938 /// horizontal operation performs the binary operation on successive elements
14939 /// of its first operand, then on successive elements of its second operand,
14940 /// returning the resulting values in a vector. For example, if
14941 /// A = < float a0, float a1, float a2, float a3 >
14943 /// B = < float b0, float b1, float b2, float b3 >
14944 /// then the result of doing a horizontal operation on A and B is
14945 /// A horizontal-op B = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >.
14946 /// In short, LHS and RHS are inspected to see if LHS op RHS is of the form
14947 /// A horizontal-op B, for some already available A and B, and if so then LHS is
14948 /// set to A, RHS to B, and the routine returns 'true'.
14949 /// Note that the binary operation should have the property that if one of the
14950 /// operands is UNDEF then the result is UNDEF.
14951 static bool isHorizontalBinOp(SDValue &LHS, SDValue &RHS, bool IsCommutative) {
14952 // Look for the following pattern: if
14953 // A = < float a0, float a1, float a2, float a3 >
14954 // B = < float b0, float b1, float b2, float b3 >
14956 // LHS = VECTOR_SHUFFLE A, B, <0, 2, 4, 6>
14957 // RHS = VECTOR_SHUFFLE A, B, <1, 3, 5, 7>
14958 // then LHS op RHS = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >
14959 // which is A horizontal-op B.
14961 // At least one of the operands should be a vector shuffle.
14962 if (LHS.getOpcode() != ISD::VECTOR_SHUFFLE &&
14963 RHS.getOpcode() != ISD::VECTOR_SHUFFLE)
14966 EVT VT = LHS.getValueType();
14968 assert((VT.is128BitVector() || VT.is256BitVector()) &&
14969 "Unsupported vector type for horizontal add/sub");
14971 // Handle 128 and 256-bit vector lengths. AVX defines horizontal add/sub to
14972 // operate independently on 128-bit lanes.
14973 unsigned NumElts = VT.getVectorNumElements();
14974 unsigned NumLanes = VT.getSizeInBits()/128;
14975 unsigned NumLaneElts = NumElts / NumLanes;
14976 assert((NumLaneElts % 2 == 0) &&
14977 "Vector type should have an even number of elements in each lane");
14978 unsigned HalfLaneElts = NumLaneElts/2;
14980 // View LHS in the form
14981 // LHS = VECTOR_SHUFFLE A, B, LMask
14982 // If LHS is not a shuffle then pretend it is the shuffle
14983 // LHS = VECTOR_SHUFFLE LHS, undef, <0, 1, ..., N-1>
14984 // NOTE: in what follows a default initialized SDValue represents an UNDEF of
14987 SmallVector<int, 16> LMask(NumElts);
14988 if (LHS.getOpcode() == ISD::VECTOR_SHUFFLE) {
14989 if (LHS.getOperand(0).getOpcode() != ISD::UNDEF)
14990 A = LHS.getOperand(0);
14991 if (LHS.getOperand(1).getOpcode() != ISD::UNDEF)
14992 B = LHS.getOperand(1);
14993 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(LHS.getNode())->getMask();
14994 std::copy(Mask.begin(), Mask.end(), LMask.begin());
14996 if (LHS.getOpcode() != ISD::UNDEF)
14998 for (unsigned i = 0; i != NumElts; ++i)
15002 // Likewise, view RHS in the form
15003 // RHS = VECTOR_SHUFFLE C, D, RMask
15005 SmallVector<int, 16> RMask(NumElts);
15006 if (RHS.getOpcode() == ISD::VECTOR_SHUFFLE) {
15007 if (RHS.getOperand(0).getOpcode() != ISD::UNDEF)
15008 C = RHS.getOperand(0);
15009 if (RHS.getOperand(1).getOpcode() != ISD::UNDEF)
15010 D = RHS.getOperand(1);
15011 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(RHS.getNode())->getMask();
15012 std::copy(Mask.begin(), Mask.end(), RMask.begin());
15014 if (RHS.getOpcode() != ISD::UNDEF)
15016 for (unsigned i = 0; i != NumElts; ++i)
15020 // Check that the shuffles are both shuffling the same vectors.
15021 if (!(A == C && B == D) && !(A == D && B == C))
15024 // If everything is UNDEF then bail out: it would be better to fold to UNDEF.
15025 if (!A.getNode() && !B.getNode())
15028 // If A and B occur in reverse order in RHS, then "swap" them (which means
15029 // rewriting the mask).
15031 CommuteVectorShuffleMask(RMask, NumElts);
15033 // At this point LHS and RHS are equivalent to
15034 // LHS = VECTOR_SHUFFLE A, B, LMask
15035 // RHS = VECTOR_SHUFFLE A, B, RMask
15036 // Check that the masks correspond to performing a horizontal operation.
15037 for (unsigned i = 0; i != NumElts; ++i) {
15038 int LIdx = LMask[i], RIdx = RMask[i];
15040 // Ignore any UNDEF components.
15041 if (LIdx < 0 || RIdx < 0 ||
15042 (!A.getNode() && (LIdx < (int)NumElts || RIdx < (int)NumElts)) ||
15043 (!B.getNode() && (LIdx >= (int)NumElts || RIdx >= (int)NumElts)))
15046 // Check that successive elements are being operated on. If not, this is
15047 // not a horizontal operation.
15048 unsigned Src = (i/HalfLaneElts) % 2; // each lane is split between srcs
15049 unsigned LaneStart = (i/NumLaneElts) * NumLaneElts;
15050 int Index = 2*(i%HalfLaneElts) + NumElts*Src + LaneStart;
15051 if (!(LIdx == Index && RIdx == Index + 1) &&
15052 !(IsCommutative && LIdx == Index + 1 && RIdx == Index))
15056 LHS = A.getNode() ? A : B; // If A is 'UNDEF', use B for it.
15057 RHS = B.getNode() ? B : A; // If B is 'UNDEF', use A for it.
15061 /// PerformFADDCombine - Do target-specific dag combines on floating point adds.
15062 static SDValue PerformFADDCombine(SDNode *N, SelectionDAG &DAG,
15063 const X86Subtarget *Subtarget) {
15064 EVT VT = N->getValueType(0);
15065 SDValue LHS = N->getOperand(0);
15066 SDValue RHS = N->getOperand(1);
15068 // Try to synthesize horizontal adds from adds of shuffles.
15069 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
15070 (Subtarget->hasAVX() && (VT == MVT::v8f32 || VT == MVT::v4f64))) &&
15071 isHorizontalBinOp(LHS, RHS, true))
15072 return DAG.getNode(X86ISD::FHADD, N->getDebugLoc(), VT, LHS, RHS);
15076 /// PerformFSUBCombine - Do target-specific dag combines on floating point subs.
15077 static SDValue PerformFSUBCombine(SDNode *N, SelectionDAG &DAG,
15078 const X86Subtarget *Subtarget) {
15079 EVT VT = N->getValueType(0);
15080 SDValue LHS = N->getOperand(0);
15081 SDValue RHS = N->getOperand(1);
15083 // Try to synthesize horizontal subs from subs of shuffles.
15084 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
15085 (Subtarget->hasAVX() && (VT == MVT::v8f32 || VT == MVT::v4f64))) &&
15086 isHorizontalBinOp(LHS, RHS, false))
15087 return DAG.getNode(X86ISD::FHSUB, N->getDebugLoc(), VT, LHS, RHS);
15091 /// PerformFORCombine - Do target-specific dag combines on X86ISD::FOR and
15092 /// X86ISD::FXOR nodes.
15093 static SDValue PerformFORCombine(SDNode *N, SelectionDAG &DAG) {
15094 assert(N->getOpcode() == X86ISD::FOR || N->getOpcode() == X86ISD::FXOR);
15095 // F[X]OR(0.0, x) -> x
15096 // F[X]OR(x, 0.0) -> x
15097 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
15098 if (C->getValueAPF().isPosZero())
15099 return N->getOperand(1);
15100 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
15101 if (C->getValueAPF().isPosZero())
15102 return N->getOperand(0);
15106 /// PerformFANDCombine - Do target-specific dag combines on X86ISD::FAND nodes.
15107 static SDValue PerformFANDCombine(SDNode *N, SelectionDAG &DAG) {
15108 // FAND(0.0, x) -> 0.0
15109 // FAND(x, 0.0) -> 0.0
15110 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
15111 if (C->getValueAPF().isPosZero())
15112 return N->getOperand(0);
15113 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
15114 if (C->getValueAPF().isPosZero())
15115 return N->getOperand(1);
15119 static SDValue PerformBTCombine(SDNode *N,
15121 TargetLowering::DAGCombinerInfo &DCI) {
15122 // BT ignores high bits in the bit index operand.
15123 SDValue Op1 = N->getOperand(1);
15124 if (Op1.hasOneUse()) {
15125 unsigned BitWidth = Op1.getValueSizeInBits();
15126 APInt DemandedMask = APInt::getLowBitsSet(BitWidth, Log2_32(BitWidth));
15127 APInt KnownZero, KnownOne;
15128 TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(),
15129 !DCI.isBeforeLegalizeOps());
15130 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
15131 if (TLO.ShrinkDemandedConstant(Op1, DemandedMask) ||
15132 TLI.SimplifyDemandedBits(Op1, DemandedMask, KnownZero, KnownOne, TLO))
15133 DCI.CommitTargetLoweringOpt(TLO);
15138 static SDValue PerformVZEXT_MOVLCombine(SDNode *N, SelectionDAG &DAG) {
15139 SDValue Op = N->getOperand(0);
15140 if (Op.getOpcode() == ISD::BITCAST)
15141 Op = Op.getOperand(0);
15142 EVT VT = N->getValueType(0), OpVT = Op.getValueType();
15143 if (Op.getOpcode() == X86ISD::VZEXT_LOAD &&
15144 VT.getVectorElementType().getSizeInBits() ==
15145 OpVT.getVectorElementType().getSizeInBits()) {
15146 return DAG.getNode(ISD::BITCAST, N->getDebugLoc(), VT, Op);
15151 static SDValue PerformSExtCombine(SDNode *N, SelectionDAG &DAG,
15152 TargetLowering::DAGCombinerInfo &DCI,
15153 const X86Subtarget *Subtarget) {
15154 if (!DCI.isBeforeLegalizeOps())
15157 if (!Subtarget->hasAVX())
15160 EVT VT = N->getValueType(0);
15161 SDValue Op = N->getOperand(0);
15162 EVT OpVT = Op.getValueType();
15163 DebugLoc dl = N->getDebugLoc();
15165 if ((VT == MVT::v4i64 && OpVT == MVT::v4i32) ||
15166 (VT == MVT::v8i32 && OpVT == MVT::v8i16)) {
15168 if (Subtarget->hasAVX2())
15169 return DAG.getNode(X86ISD::VSEXT_MOVL, dl, VT, Op);
15171 // Optimize vectors in AVX mode
15172 // Sign extend v8i16 to v8i32 and
15175 // Divide input vector into two parts
15176 // for v4i32 the shuffle mask will be { 0, 1, -1, -1} {2, 3, -1, -1}
15177 // use vpmovsx instruction to extend v4i32 -> v2i64; v8i16 -> v4i32
15178 // concat the vectors to original VT
15180 unsigned NumElems = OpVT.getVectorNumElements();
15181 SmallVector<int,8> ShufMask1(NumElems, -1);
15182 for (unsigned i = 0; i != NumElems/2; ++i)
15185 SDValue OpLo = DAG.getVectorShuffle(OpVT, dl, Op, DAG.getUNDEF(OpVT),
15188 SmallVector<int,8> ShufMask2(NumElems, -1);
15189 for (unsigned i = 0; i != NumElems/2; ++i)
15190 ShufMask2[i] = i + NumElems/2;
15192 SDValue OpHi = DAG.getVectorShuffle(OpVT, dl, Op, DAG.getUNDEF(OpVT),
15195 EVT HalfVT = EVT::getVectorVT(*DAG.getContext(), VT.getScalarType(),
15196 VT.getVectorNumElements()/2);
15198 OpLo = DAG.getNode(X86ISD::VSEXT_MOVL, dl, HalfVT, OpLo);
15199 OpHi = DAG.getNode(X86ISD::VSEXT_MOVL, dl, HalfVT, OpHi);
15201 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi);
15206 static SDValue PerformFMACombine(SDNode *N, SelectionDAG &DAG,
15207 const X86Subtarget* Subtarget) {
15208 DebugLoc dl = N->getDebugLoc();
15209 EVT VT = N->getValueType(0);
15211 EVT ScalarVT = VT.getScalarType();
15212 if ((ScalarVT != MVT::f32 && ScalarVT != MVT::f64) || !Subtarget->hasFMA())
15215 SDValue A = N->getOperand(0);
15216 SDValue B = N->getOperand(1);
15217 SDValue C = N->getOperand(2);
15219 bool NegA = (A.getOpcode() == ISD::FNEG);
15220 bool NegB = (B.getOpcode() == ISD::FNEG);
15221 bool NegC = (C.getOpcode() == ISD::FNEG);
15223 // Negative multiplication when NegA xor NegB
15224 bool NegMul = (NegA != NegB);
15226 A = A.getOperand(0);
15228 B = B.getOperand(0);
15230 C = C.getOperand(0);
15234 Opcode = (!NegC)? X86ISD::FMADD : X86ISD::FMSUB;
15236 Opcode = (!NegC)? X86ISD::FNMADD : X86ISD::FNMSUB;
15237 return DAG.getNode(Opcode, dl, VT, A, B, C);
15240 static SDValue PerformZExtCombine(SDNode *N, SelectionDAG &DAG,
15241 TargetLowering::DAGCombinerInfo &DCI,
15242 const X86Subtarget *Subtarget) {
15243 // (i32 zext (and (i8 x86isd::setcc_carry), 1)) ->
15244 // (and (i32 x86isd::setcc_carry), 1)
15245 // This eliminates the zext. This transformation is necessary because
15246 // ISD::SETCC is always legalized to i8.
15247 DebugLoc dl = N->getDebugLoc();
15248 SDValue N0 = N->getOperand(0);
15249 EVT VT = N->getValueType(0);
15250 EVT OpVT = N0.getValueType();
15252 if (N0.getOpcode() == ISD::AND &&
15254 N0.getOperand(0).hasOneUse()) {
15255 SDValue N00 = N0.getOperand(0);
15256 if (N00.getOpcode() != X86ISD::SETCC_CARRY)
15258 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
15259 if (!C || C->getZExtValue() != 1)
15261 return DAG.getNode(ISD::AND, dl, VT,
15262 DAG.getNode(X86ISD::SETCC_CARRY, dl, VT,
15263 N00.getOperand(0), N00.getOperand(1)),
15264 DAG.getConstant(1, VT));
15267 // Optimize vectors in AVX mode:
15270 // Use vpunpcklwd for 4 lower elements v8i16 -> v4i32.
15271 // Use vpunpckhwd for 4 upper elements v8i16 -> v4i32.
15272 // Concat upper and lower parts.
15275 // Use vpunpckldq for 4 lower elements v4i32 -> v2i64.
15276 // Use vpunpckhdq for 4 upper elements v4i32 -> v2i64.
15277 // Concat upper and lower parts.
15279 if (!DCI.isBeforeLegalizeOps())
15282 if (!Subtarget->hasAVX())
15285 if (((VT == MVT::v8i32) && (OpVT == MVT::v8i16)) ||
15286 ((VT == MVT::v4i64) && (OpVT == MVT::v4i32))) {
15288 if (Subtarget->hasAVX2())
15289 return DAG.getNode(X86ISD::VZEXT_MOVL, dl, VT, N0);
15291 SDValue ZeroVec = getZeroVector(OpVT, Subtarget, DAG, dl);
15292 SDValue OpLo = getUnpackl(DAG, dl, OpVT, N0, ZeroVec);
15293 SDValue OpHi = getUnpackh(DAG, dl, OpVT, N0, ZeroVec);
15295 EVT HVT = EVT::getVectorVT(*DAG.getContext(), VT.getVectorElementType(),
15296 VT.getVectorNumElements()/2);
15298 OpLo = DAG.getNode(ISD::BITCAST, dl, HVT, OpLo);
15299 OpHi = DAG.getNode(ISD::BITCAST, dl, HVT, OpHi);
15301 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi);
15307 // Optimize x == -y --> x+y == 0
15308 // x != -y --> x+y != 0
15309 static SDValue PerformISDSETCCCombine(SDNode *N, SelectionDAG &DAG) {
15310 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(2))->get();
15311 SDValue LHS = N->getOperand(0);
15312 SDValue RHS = N->getOperand(1);
15314 if ((CC == ISD::SETNE || CC == ISD::SETEQ) && LHS.getOpcode() == ISD::SUB)
15315 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(LHS.getOperand(0)))
15316 if (C->getAPIntValue() == 0 && LHS.hasOneUse()) {
15317 SDValue addV = DAG.getNode(ISD::ADD, N->getDebugLoc(),
15318 LHS.getValueType(), RHS, LHS.getOperand(1));
15319 return DAG.getSetCC(N->getDebugLoc(), N->getValueType(0),
15320 addV, DAG.getConstant(0, addV.getValueType()), CC);
15322 if ((CC == ISD::SETNE || CC == ISD::SETEQ) && RHS.getOpcode() == ISD::SUB)
15323 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS.getOperand(0)))
15324 if (C->getAPIntValue() == 0 && RHS.hasOneUse()) {
15325 SDValue addV = DAG.getNode(ISD::ADD, N->getDebugLoc(),
15326 RHS.getValueType(), LHS, RHS.getOperand(1));
15327 return DAG.getSetCC(N->getDebugLoc(), N->getValueType(0),
15328 addV, DAG.getConstant(0, addV.getValueType()), CC);
15333 // Optimize RES = X86ISD::SETCC CONDCODE, EFLAG_INPUT
15334 static SDValue PerformSETCCCombine(SDNode *N, SelectionDAG &DAG) {
15335 DebugLoc DL = N->getDebugLoc();
15336 X86::CondCode CC = X86::CondCode(N->getConstantOperandVal(0));
15337 SDValue EFLAGS = N->getOperand(1);
15339 // Materialize "setb reg" as "sbb reg,reg", since it can be extended without
15340 // a zext and produces an all-ones bit which is more useful than 0/1 in some
15342 if (CC == X86::COND_B)
15343 return DAG.getNode(ISD::AND, DL, MVT::i8,
15344 DAG.getNode(X86ISD::SETCC_CARRY, DL, MVT::i8,
15345 DAG.getConstant(CC, MVT::i8), EFLAGS),
15346 DAG.getConstant(1, MVT::i8));
15350 Flags = BoolTestSetCCCombine(EFLAGS, CC);
15351 if (Flags.getNode()) {
15352 SDValue Cond = DAG.getConstant(CC, MVT::i8);
15353 return DAG.getNode(X86ISD::SETCC, DL, N->getVTList(), Cond, Flags);
15359 // Optimize branch condition evaluation.
15361 static SDValue PerformBrCondCombine(SDNode *N, SelectionDAG &DAG,
15362 TargetLowering::DAGCombinerInfo &DCI,
15363 const X86Subtarget *Subtarget) {
15364 DebugLoc DL = N->getDebugLoc();
15365 SDValue Chain = N->getOperand(0);
15366 SDValue Dest = N->getOperand(1);
15367 SDValue EFLAGS = N->getOperand(3);
15368 X86::CondCode CC = X86::CondCode(N->getConstantOperandVal(2));
15372 Flags = BoolTestSetCCCombine(EFLAGS, CC);
15373 if (Flags.getNode()) {
15374 SDValue Cond = DAG.getConstant(CC, MVT::i8);
15375 return DAG.getNode(X86ISD::BRCOND, DL, N->getVTList(), Chain, Dest, Cond,
15382 static SDValue PerformUINT_TO_FPCombine(SDNode *N, SelectionDAG &DAG) {
15383 SDValue Op0 = N->getOperand(0);
15384 EVT InVT = Op0->getValueType(0);
15386 // UINT_TO_FP(v4i8) -> SINT_TO_FP(ZEXT(v4i8 to v4i32))
15387 if (InVT == MVT::v8i8 || InVT == MVT::v4i8) {
15388 DebugLoc dl = N->getDebugLoc();
15389 MVT DstVT = InVT == MVT::v4i8 ? MVT::v4i32 : MVT::v8i32;
15390 SDValue P = DAG.getNode(ISD::ZERO_EXTEND, dl, DstVT, Op0);
15391 // Notice that we use SINT_TO_FP because we know that the high bits
15392 // are zero and SINT_TO_FP is better supported by the hardware.
15393 return DAG.getNode(ISD::SINT_TO_FP, dl, N->getValueType(0), P);
15399 static SDValue PerformSINT_TO_FPCombine(SDNode *N, SelectionDAG &DAG,
15400 const X86TargetLowering *XTLI) {
15401 SDValue Op0 = N->getOperand(0);
15402 EVT InVT = Op0->getValueType(0);
15404 // SINT_TO_FP(v4i8) -> SINT_TO_FP(SEXT(v4i8 to v4i32))
15405 if (InVT == MVT::v8i8 || InVT == MVT::v4i8) {
15406 DebugLoc dl = N->getDebugLoc();
15407 MVT DstVT = InVT == MVT::v4i8 ? MVT::v4i32 : MVT::v8i32;
15408 SDValue P = DAG.getNode(ISD::SIGN_EXTEND, dl, DstVT, Op0);
15409 return DAG.getNode(ISD::SINT_TO_FP, dl, N->getValueType(0), P);
15412 // Transform (SINT_TO_FP (i64 ...)) into an x87 operation if we have
15413 // a 32-bit target where SSE doesn't support i64->FP operations.
15414 if (Op0.getOpcode() == ISD::LOAD) {
15415 LoadSDNode *Ld = cast<LoadSDNode>(Op0.getNode());
15416 EVT VT = Ld->getValueType(0);
15417 if (!Ld->isVolatile() && !N->getValueType(0).isVector() &&
15418 ISD::isNON_EXTLoad(Op0.getNode()) && Op0.hasOneUse() &&
15419 !XTLI->getSubtarget()->is64Bit() &&
15420 !DAG.getTargetLoweringInfo().isTypeLegal(VT)) {
15421 SDValue FILDChain = XTLI->BuildFILD(SDValue(N, 0), Ld->getValueType(0),
15422 Ld->getChain(), Op0, DAG);
15423 DAG.ReplaceAllUsesOfValueWith(Op0.getValue(1), FILDChain.getValue(1));
15430 static SDValue PerformFP_TO_SINTCombine(SDNode *N, SelectionDAG &DAG) {
15431 EVT VT = N->getValueType(0);
15433 // v4i8 = FP_TO_SINT() -> v4i8 = TRUNCATE (V4i32 = FP_TO_SINT()
15434 if (VT == MVT::v8i8 || VT == MVT::v4i8) {
15435 DebugLoc dl = N->getDebugLoc();
15436 MVT DstVT = VT == MVT::v4i8 ? MVT::v4i32 : MVT::v8i32;
15437 SDValue I = DAG.getNode(ISD::FP_TO_SINT, dl, DstVT, N->getOperand(0));
15438 return DAG.getNode(ISD::TRUNCATE, dl, VT, I);
15444 // Optimize RES, EFLAGS = X86ISD::ADC LHS, RHS, EFLAGS
15445 static SDValue PerformADCCombine(SDNode *N, SelectionDAG &DAG,
15446 X86TargetLowering::DAGCombinerInfo &DCI) {
15447 // If the LHS and RHS of the ADC node are zero, then it can't overflow and
15448 // the result is either zero or one (depending on the input carry bit).
15449 // Strength reduce this down to a "set on carry" aka SETCC_CARRY&1.
15450 if (X86::isZeroNode(N->getOperand(0)) &&
15451 X86::isZeroNode(N->getOperand(1)) &&
15452 // We don't have a good way to replace an EFLAGS use, so only do this when
15454 SDValue(N, 1).use_empty()) {
15455 DebugLoc DL = N->getDebugLoc();
15456 EVT VT = N->getValueType(0);
15457 SDValue CarryOut = DAG.getConstant(0, N->getValueType(1));
15458 SDValue Res1 = DAG.getNode(ISD::AND, DL, VT,
15459 DAG.getNode(X86ISD::SETCC_CARRY, DL, VT,
15460 DAG.getConstant(X86::COND_B,MVT::i8),
15462 DAG.getConstant(1, VT));
15463 return DCI.CombineTo(N, Res1, CarryOut);
15469 // fold (add Y, (sete X, 0)) -> adc 0, Y
15470 // (add Y, (setne X, 0)) -> sbb -1, Y
15471 // (sub (sete X, 0), Y) -> sbb 0, Y
15472 // (sub (setne X, 0), Y) -> adc -1, Y
15473 static SDValue OptimizeConditionalInDecrement(SDNode *N, SelectionDAG &DAG) {
15474 DebugLoc DL = N->getDebugLoc();
15476 // Look through ZExts.
15477 SDValue Ext = N->getOperand(N->getOpcode() == ISD::SUB ? 1 : 0);
15478 if (Ext.getOpcode() != ISD::ZERO_EXTEND || !Ext.hasOneUse())
15481 SDValue SetCC = Ext.getOperand(0);
15482 if (SetCC.getOpcode() != X86ISD::SETCC || !SetCC.hasOneUse())
15485 X86::CondCode CC = (X86::CondCode)SetCC.getConstantOperandVal(0);
15486 if (CC != X86::COND_E && CC != X86::COND_NE)
15489 SDValue Cmp = SetCC.getOperand(1);
15490 if (Cmp.getOpcode() != X86ISD::CMP || !Cmp.hasOneUse() ||
15491 !X86::isZeroNode(Cmp.getOperand(1)) ||
15492 !Cmp.getOperand(0).getValueType().isInteger())
15495 SDValue CmpOp0 = Cmp.getOperand(0);
15496 SDValue NewCmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32, CmpOp0,
15497 DAG.getConstant(1, CmpOp0.getValueType()));
15499 SDValue OtherVal = N->getOperand(N->getOpcode() == ISD::SUB ? 0 : 1);
15500 if (CC == X86::COND_NE)
15501 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::ADC : X86ISD::SBB,
15502 DL, OtherVal.getValueType(), OtherVal,
15503 DAG.getConstant(-1ULL, OtherVal.getValueType()), NewCmp);
15504 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::SBB : X86ISD::ADC,
15505 DL, OtherVal.getValueType(), OtherVal,
15506 DAG.getConstant(0, OtherVal.getValueType()), NewCmp);
15509 /// PerformADDCombine - Do target-specific dag combines on integer adds.
15510 static SDValue PerformAddCombine(SDNode *N, SelectionDAG &DAG,
15511 const X86Subtarget *Subtarget) {
15512 EVT VT = N->getValueType(0);
15513 SDValue Op0 = N->getOperand(0);
15514 SDValue Op1 = N->getOperand(1);
15516 // Try to synthesize horizontal adds from adds of shuffles.
15517 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) ||
15518 (Subtarget->hasAVX2() && (VT == MVT::v16i16 || VT == MVT::v8i32))) &&
15519 isHorizontalBinOp(Op0, Op1, true))
15520 return DAG.getNode(X86ISD::HADD, N->getDebugLoc(), VT, Op0, Op1);
15522 return OptimizeConditionalInDecrement(N, DAG);
15525 static SDValue PerformSubCombine(SDNode *N, SelectionDAG &DAG,
15526 const X86Subtarget *Subtarget) {
15527 SDValue Op0 = N->getOperand(0);
15528 SDValue Op1 = N->getOperand(1);
15530 // X86 can't encode an immediate LHS of a sub. See if we can push the
15531 // negation into a preceding instruction.
15532 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op0)) {
15533 // If the RHS of the sub is a XOR with one use and a constant, invert the
15534 // immediate. Then add one to the LHS of the sub so we can turn
15535 // X-Y -> X+~Y+1, saving one register.
15536 if (Op1->hasOneUse() && Op1.getOpcode() == ISD::XOR &&
15537 isa<ConstantSDNode>(Op1.getOperand(1))) {
15538 APInt XorC = cast<ConstantSDNode>(Op1.getOperand(1))->getAPIntValue();
15539 EVT VT = Op0.getValueType();
15540 SDValue NewXor = DAG.getNode(ISD::XOR, Op1.getDebugLoc(), VT,
15542 DAG.getConstant(~XorC, VT));
15543 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, NewXor,
15544 DAG.getConstant(C->getAPIntValue()+1, VT));
15548 // Try to synthesize horizontal adds from adds of shuffles.
15549 EVT VT = N->getValueType(0);
15550 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) ||
15551 (Subtarget->hasAVX2() && (VT == MVT::v16i16 || VT == MVT::v8i32))) &&
15552 isHorizontalBinOp(Op0, Op1, true))
15553 return DAG.getNode(X86ISD::HSUB, N->getDebugLoc(), VT, Op0, Op1);
15555 return OptimizeConditionalInDecrement(N, DAG);
15558 SDValue X86TargetLowering::PerformDAGCombine(SDNode *N,
15559 DAGCombinerInfo &DCI) const {
15560 SelectionDAG &DAG = DCI.DAG;
15561 switch (N->getOpcode()) {
15563 case ISD::EXTRACT_VECTOR_ELT:
15564 return PerformEXTRACT_VECTOR_ELTCombine(N, DAG, DCI);
15566 case ISD::SELECT: return PerformSELECTCombine(N, DAG, DCI, Subtarget);
15567 case X86ISD::CMOV: return PerformCMOVCombine(N, DAG, DCI);
15568 case ISD::ADD: return PerformAddCombine(N, DAG, Subtarget);
15569 case ISD::SUB: return PerformSubCombine(N, DAG, Subtarget);
15570 case X86ISD::ADC: return PerformADCCombine(N, DAG, DCI);
15571 case ISD::MUL: return PerformMulCombine(N, DAG, DCI);
15574 case ISD::SRL: return PerformShiftCombine(N, DAG, DCI, Subtarget);
15575 case ISD::AND: return PerformAndCombine(N, DAG, DCI, Subtarget);
15576 case ISD::OR: return PerformOrCombine(N, DAG, DCI, Subtarget);
15577 case ISD::XOR: return PerformXorCombine(N, DAG, DCI, Subtarget);
15578 case ISD::LOAD: return PerformLOADCombine(N, DAG, DCI, Subtarget);
15579 case ISD::STORE: return PerformSTORECombine(N, DAG, Subtarget);
15580 case ISD::UINT_TO_FP: return PerformUINT_TO_FPCombine(N, DAG);
15581 case ISD::SINT_TO_FP: return PerformSINT_TO_FPCombine(N, DAG, this);
15582 case ISD::FP_TO_SINT: return PerformFP_TO_SINTCombine(N, DAG);
15583 case ISD::FADD: return PerformFADDCombine(N, DAG, Subtarget);
15584 case ISD::FSUB: return PerformFSUBCombine(N, DAG, Subtarget);
15586 case X86ISD::FOR: return PerformFORCombine(N, DAG);
15587 case X86ISD::FAND: return PerformFANDCombine(N, DAG);
15588 case X86ISD::BT: return PerformBTCombine(N, DAG, DCI);
15589 case X86ISD::VZEXT_MOVL: return PerformVZEXT_MOVLCombine(N, DAG);
15590 case ISD::ANY_EXTEND:
15591 case ISD::ZERO_EXTEND: return PerformZExtCombine(N, DAG, DCI, Subtarget);
15592 case ISD::SIGN_EXTEND: return PerformSExtCombine(N, DAG, DCI, Subtarget);
15593 case ISD::TRUNCATE: return PerformTruncateCombine(N, DAG, DCI);
15594 case ISD::SETCC: return PerformISDSETCCCombine(N, DAG);
15595 case X86ISD::SETCC: return PerformSETCCCombine(N, DAG);
15596 case X86ISD::BRCOND: return PerformBrCondCombine(N, DAG, DCI, Subtarget);
15597 case X86ISD::SHUFP: // Handle all target specific shuffles
15598 case X86ISD::PALIGN:
15599 case X86ISD::UNPCKH:
15600 case X86ISD::UNPCKL:
15601 case X86ISD::MOVHLPS:
15602 case X86ISD::MOVLHPS:
15603 case X86ISD::PSHUFD:
15604 case X86ISD::PSHUFHW:
15605 case X86ISD::PSHUFLW:
15606 case X86ISD::MOVSS:
15607 case X86ISD::MOVSD:
15608 case X86ISD::VPERMILP:
15609 case X86ISD::VPERM2X128:
15610 case ISD::VECTOR_SHUFFLE: return PerformShuffleCombine(N, DAG, DCI,Subtarget);
15611 case ISD::FMA: return PerformFMACombine(N, DAG, Subtarget);
15617 /// isTypeDesirableForOp - Return true if the target has native support for
15618 /// the specified value type and it is 'desirable' to use the type for the
15619 /// given node type. e.g. On x86 i16 is legal, but undesirable since i16
15620 /// instruction encodings are longer and some i16 instructions are slow.
15621 bool X86TargetLowering::isTypeDesirableForOp(unsigned Opc, EVT VT) const {
15622 if (!isTypeLegal(VT))
15624 if (VT != MVT::i16)
15631 case ISD::SIGN_EXTEND:
15632 case ISD::ZERO_EXTEND:
15633 case ISD::ANY_EXTEND:
15646 /// IsDesirableToPromoteOp - This method query the target whether it is
15647 /// beneficial for dag combiner to promote the specified node. If true, it
15648 /// should return the desired promotion type by reference.
15649 bool X86TargetLowering::IsDesirableToPromoteOp(SDValue Op, EVT &PVT) const {
15650 EVT VT = Op.getValueType();
15651 if (VT != MVT::i16)
15654 bool Promote = false;
15655 bool Commute = false;
15656 switch (Op.getOpcode()) {
15659 LoadSDNode *LD = cast<LoadSDNode>(Op);
15660 // If the non-extending load has a single use and it's not live out, then it
15661 // might be folded.
15662 if (LD->getExtensionType() == ISD::NON_EXTLOAD /*&&
15663 Op.hasOneUse()*/) {
15664 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
15665 UE = Op.getNode()->use_end(); UI != UE; ++UI) {
15666 // The only case where we'd want to promote LOAD (rather then it being
15667 // promoted as an operand is when it's only use is liveout.
15668 if (UI->getOpcode() != ISD::CopyToReg)
15675 case ISD::SIGN_EXTEND:
15676 case ISD::ZERO_EXTEND:
15677 case ISD::ANY_EXTEND:
15682 SDValue N0 = Op.getOperand(0);
15683 // Look out for (store (shl (load), x)).
15684 if (MayFoldLoad(N0) && MayFoldIntoStore(Op))
15697 SDValue N0 = Op.getOperand(0);
15698 SDValue N1 = Op.getOperand(1);
15699 if (!Commute && MayFoldLoad(N1))
15701 // Avoid disabling potential load folding opportunities.
15702 if (MayFoldLoad(N0) && (!isa<ConstantSDNode>(N1) || MayFoldIntoStore(Op)))
15704 if (MayFoldLoad(N1) && (!isa<ConstantSDNode>(N0) || MayFoldIntoStore(Op)))
15714 //===----------------------------------------------------------------------===//
15715 // X86 Inline Assembly Support
15716 //===----------------------------------------------------------------------===//
15719 // Helper to match a string separated by whitespace.
15720 bool matchAsmImpl(StringRef s, ArrayRef<const StringRef *> args) {
15721 s = s.substr(s.find_first_not_of(" \t")); // Skip leading whitespace.
15723 for (unsigned i = 0, e = args.size(); i != e; ++i) {
15724 StringRef piece(*args[i]);
15725 if (!s.startswith(piece)) // Check if the piece matches.
15728 s = s.substr(piece.size());
15729 StringRef::size_type pos = s.find_first_not_of(" \t");
15730 if (pos == 0) // We matched a prefix.
15738 const VariadicFunction1<bool, StringRef, StringRef, matchAsmImpl> matchAsm={};
15741 bool X86TargetLowering::ExpandInlineAsm(CallInst *CI) const {
15742 InlineAsm *IA = cast<InlineAsm>(CI->getCalledValue());
15744 std::string AsmStr = IA->getAsmString();
15746 IntegerType *Ty = dyn_cast<IntegerType>(CI->getType());
15747 if (!Ty || Ty->getBitWidth() % 16 != 0)
15750 // TODO: should remove alternatives from the asmstring: "foo {a|b}" -> "foo a"
15751 SmallVector<StringRef, 4> AsmPieces;
15752 SplitString(AsmStr, AsmPieces, ";\n");
15754 switch (AsmPieces.size()) {
15755 default: return false;
15757 // FIXME: this should verify that we are targeting a 486 or better. If not,
15758 // we will turn this bswap into something that will be lowered to logical
15759 // ops instead of emitting the bswap asm. For now, we don't support 486 or
15760 // lower so don't worry about this.
15762 if (matchAsm(AsmPieces[0], "bswap", "$0") ||
15763 matchAsm(AsmPieces[0], "bswapl", "$0") ||
15764 matchAsm(AsmPieces[0], "bswapq", "$0") ||
15765 matchAsm(AsmPieces[0], "bswap", "${0:q}") ||
15766 matchAsm(AsmPieces[0], "bswapl", "${0:q}") ||
15767 matchAsm(AsmPieces[0], "bswapq", "${0:q}")) {
15768 // No need to check constraints, nothing other than the equivalent of
15769 // "=r,0" would be valid here.
15770 return IntrinsicLowering::LowerToByteSwap(CI);
15773 // rorw $$8, ${0:w} --> llvm.bswap.i16
15774 if (CI->getType()->isIntegerTy(16) &&
15775 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 &&
15776 (matchAsm(AsmPieces[0], "rorw", "$$8,", "${0:w}") ||
15777 matchAsm(AsmPieces[0], "rolw", "$$8,", "${0:w}"))) {
15779 const std::string &ConstraintsStr = IA->getConstraintString();
15780 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
15781 std::sort(AsmPieces.begin(), AsmPieces.end());
15782 if (AsmPieces.size() == 4 &&
15783 AsmPieces[0] == "~{cc}" &&
15784 AsmPieces[1] == "~{dirflag}" &&
15785 AsmPieces[2] == "~{flags}" &&
15786 AsmPieces[3] == "~{fpsr}")
15787 return IntrinsicLowering::LowerToByteSwap(CI);
15791 if (CI->getType()->isIntegerTy(32) &&
15792 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 &&
15793 matchAsm(AsmPieces[0], "rorw", "$$8,", "${0:w}") &&
15794 matchAsm(AsmPieces[1], "rorl", "$$16,", "$0") &&
15795 matchAsm(AsmPieces[2], "rorw", "$$8,", "${0:w}")) {
15797 const std::string &ConstraintsStr = IA->getConstraintString();
15798 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
15799 std::sort(AsmPieces.begin(), AsmPieces.end());
15800 if (AsmPieces.size() == 4 &&
15801 AsmPieces[0] == "~{cc}" &&
15802 AsmPieces[1] == "~{dirflag}" &&
15803 AsmPieces[2] == "~{flags}" &&
15804 AsmPieces[3] == "~{fpsr}")
15805 return IntrinsicLowering::LowerToByteSwap(CI);
15808 if (CI->getType()->isIntegerTy(64)) {
15809 InlineAsm::ConstraintInfoVector Constraints = IA->ParseConstraints();
15810 if (Constraints.size() >= 2 &&
15811 Constraints[0].Codes.size() == 1 && Constraints[0].Codes[0] == "A" &&
15812 Constraints[1].Codes.size() == 1 && Constraints[1].Codes[0] == "0") {
15813 // bswap %eax / bswap %edx / xchgl %eax, %edx -> llvm.bswap.i64
15814 if (matchAsm(AsmPieces[0], "bswap", "%eax") &&
15815 matchAsm(AsmPieces[1], "bswap", "%edx") &&
15816 matchAsm(AsmPieces[2], "xchgl", "%eax,", "%edx"))
15817 return IntrinsicLowering::LowerToByteSwap(CI);
15827 /// getConstraintType - Given a constraint letter, return the type of
15828 /// constraint it is for this target.
15829 X86TargetLowering::ConstraintType
15830 X86TargetLowering::getConstraintType(const std::string &Constraint) const {
15831 if (Constraint.size() == 1) {
15832 switch (Constraint[0]) {
15843 return C_RegisterClass;
15867 return TargetLowering::getConstraintType(Constraint);
15870 /// Examine constraint type and operand type and determine a weight value.
15871 /// This object must already have been set up with the operand type
15872 /// and the current alternative constraint selected.
15873 TargetLowering::ConstraintWeight
15874 X86TargetLowering::getSingleConstraintMatchWeight(
15875 AsmOperandInfo &info, const char *constraint) const {
15876 ConstraintWeight weight = CW_Invalid;
15877 Value *CallOperandVal = info.CallOperandVal;
15878 // If we don't have a value, we can't do a match,
15879 // but allow it at the lowest weight.
15880 if (CallOperandVal == NULL)
15882 Type *type = CallOperandVal->getType();
15883 // Look at the constraint type.
15884 switch (*constraint) {
15886 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
15897 if (CallOperandVal->getType()->isIntegerTy())
15898 weight = CW_SpecificReg;
15903 if (type->isFloatingPointTy())
15904 weight = CW_SpecificReg;
15907 if (type->isX86_MMXTy() && Subtarget->hasMMX())
15908 weight = CW_SpecificReg;
15912 if (((type->getPrimitiveSizeInBits() == 128) && Subtarget->hasSSE1()) ||
15913 ((type->getPrimitiveSizeInBits() == 256) && Subtarget->hasAVX()))
15914 weight = CW_Register;
15917 if (ConstantInt *C = dyn_cast<ConstantInt>(info.CallOperandVal)) {
15918 if (C->getZExtValue() <= 31)
15919 weight = CW_Constant;
15923 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
15924 if (C->getZExtValue() <= 63)
15925 weight = CW_Constant;
15929 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
15930 if ((C->getSExtValue() >= -0x80) && (C->getSExtValue() <= 0x7f))
15931 weight = CW_Constant;
15935 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
15936 if ((C->getZExtValue() == 0xff) || (C->getZExtValue() == 0xffff))
15937 weight = CW_Constant;
15941 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
15942 if (C->getZExtValue() <= 3)
15943 weight = CW_Constant;
15947 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
15948 if (C->getZExtValue() <= 0xff)
15949 weight = CW_Constant;
15954 if (dyn_cast<ConstantFP>(CallOperandVal)) {
15955 weight = CW_Constant;
15959 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
15960 if ((C->getSExtValue() >= -0x80000000LL) &&
15961 (C->getSExtValue() <= 0x7fffffffLL))
15962 weight = CW_Constant;
15966 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
15967 if (C->getZExtValue() <= 0xffffffff)
15968 weight = CW_Constant;
15975 /// LowerXConstraint - try to replace an X constraint, which matches anything,
15976 /// with another that has more specific requirements based on the type of the
15977 /// corresponding operand.
15978 const char *X86TargetLowering::
15979 LowerXConstraint(EVT ConstraintVT) const {
15980 // FP X constraints get lowered to SSE1/2 registers if available, otherwise
15981 // 'f' like normal targets.
15982 if (ConstraintVT.isFloatingPoint()) {
15983 if (Subtarget->hasSSE2())
15985 if (Subtarget->hasSSE1())
15989 return TargetLowering::LowerXConstraint(ConstraintVT);
15992 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
15993 /// vector. If it is invalid, don't add anything to Ops.
15994 void X86TargetLowering::LowerAsmOperandForConstraint(SDValue Op,
15995 std::string &Constraint,
15996 std::vector<SDValue>&Ops,
15997 SelectionDAG &DAG) const {
15998 SDValue Result(0, 0);
16000 // Only support length 1 constraints for now.
16001 if (Constraint.length() > 1) return;
16003 char ConstraintLetter = Constraint[0];
16004 switch (ConstraintLetter) {
16007 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
16008 if (C->getZExtValue() <= 31) {
16009 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
16015 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
16016 if (C->getZExtValue() <= 63) {
16017 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
16023 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
16024 if ((int8_t)C->getSExtValue() == C->getSExtValue()) {
16025 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
16031 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
16032 if (C->getZExtValue() <= 255) {
16033 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
16039 // 32-bit signed value
16040 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
16041 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
16042 C->getSExtValue())) {
16043 // Widen to 64 bits here to get it sign extended.
16044 Result = DAG.getTargetConstant(C->getSExtValue(), MVT::i64);
16047 // FIXME gcc accepts some relocatable values here too, but only in certain
16048 // memory models; it's complicated.
16053 // 32-bit unsigned value
16054 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
16055 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
16056 C->getZExtValue())) {
16057 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
16061 // FIXME gcc accepts some relocatable values here too, but only in certain
16062 // memory models; it's complicated.
16066 // Literal immediates are always ok.
16067 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op)) {
16068 // Widen to 64 bits here to get it sign extended.
16069 Result = DAG.getTargetConstant(CST->getSExtValue(), MVT::i64);
16073 // In any sort of PIC mode addresses need to be computed at runtime by
16074 // adding in a register or some sort of table lookup. These can't
16075 // be used as immediates.
16076 if (Subtarget->isPICStyleGOT() || Subtarget->isPICStyleStubPIC())
16079 // If we are in non-pic codegen mode, we allow the address of a global (with
16080 // an optional displacement) to be used with 'i'.
16081 GlobalAddressSDNode *GA = 0;
16082 int64_t Offset = 0;
16084 // Match either (GA), (GA+C), (GA+C1+C2), etc.
16086 if ((GA = dyn_cast<GlobalAddressSDNode>(Op))) {
16087 Offset += GA->getOffset();
16089 } else if (Op.getOpcode() == ISD::ADD) {
16090 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
16091 Offset += C->getZExtValue();
16092 Op = Op.getOperand(0);
16095 } else if (Op.getOpcode() == ISD::SUB) {
16096 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
16097 Offset += -C->getZExtValue();
16098 Op = Op.getOperand(0);
16103 // Otherwise, this isn't something we can handle, reject it.
16107 const GlobalValue *GV = GA->getGlobal();
16108 // If we require an extra load to get this address, as in PIC mode, we
16109 // can't accept it.
16110 if (isGlobalStubReference(Subtarget->ClassifyGlobalReference(GV,
16111 getTargetMachine())))
16114 Result = DAG.getTargetGlobalAddress(GV, Op.getDebugLoc(),
16115 GA->getValueType(0), Offset);
16120 if (Result.getNode()) {
16121 Ops.push_back(Result);
16124 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
16127 std::pair<unsigned, const TargetRegisterClass*>
16128 X86TargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
16130 // First, see if this is a constraint that directly corresponds to an LLVM
16132 if (Constraint.size() == 1) {
16133 // GCC Constraint Letters
16134 switch (Constraint[0]) {
16136 // TODO: Slight differences here in allocation order and leaving
16137 // RIP in the class. Do they matter any more here than they do
16138 // in the normal allocation?
16139 case 'q': // GENERAL_REGS in 64-bit mode, Q_REGS in 32-bit mode.
16140 if (Subtarget->is64Bit()) {
16141 if (VT == MVT::i32 || VT == MVT::f32)
16142 return std::make_pair(0U, &X86::GR32RegClass);
16143 if (VT == MVT::i16)
16144 return std::make_pair(0U, &X86::GR16RegClass);
16145 if (VT == MVT::i8 || VT == MVT::i1)
16146 return std::make_pair(0U, &X86::GR8RegClass);
16147 if (VT == MVT::i64 || VT == MVT::f64)
16148 return std::make_pair(0U, &X86::GR64RegClass);
16151 // 32-bit fallthrough
16152 case 'Q': // Q_REGS
16153 if (VT == MVT::i32 || VT == MVT::f32)
16154 return std::make_pair(0U, &X86::GR32_ABCDRegClass);
16155 if (VT == MVT::i16)
16156 return std::make_pair(0U, &X86::GR16_ABCDRegClass);
16157 if (VT == MVT::i8 || VT == MVT::i1)
16158 return std::make_pair(0U, &X86::GR8_ABCD_LRegClass);
16159 if (VT == MVT::i64)
16160 return std::make_pair(0U, &X86::GR64_ABCDRegClass);
16162 case 'r': // GENERAL_REGS
16163 case 'l': // INDEX_REGS
16164 if (VT == MVT::i8 || VT == MVT::i1)
16165 return std::make_pair(0U, &X86::GR8RegClass);
16166 if (VT == MVT::i16)
16167 return std::make_pair(0U, &X86::GR16RegClass);
16168 if (VT == MVT::i32 || VT == MVT::f32 || !Subtarget->is64Bit())
16169 return std::make_pair(0U, &X86::GR32RegClass);
16170 return std::make_pair(0U, &X86::GR64RegClass);
16171 case 'R': // LEGACY_REGS
16172 if (VT == MVT::i8 || VT == MVT::i1)
16173 return std::make_pair(0U, &X86::GR8_NOREXRegClass);
16174 if (VT == MVT::i16)
16175 return std::make_pair(0U, &X86::GR16_NOREXRegClass);
16176 if (VT == MVT::i32 || !Subtarget->is64Bit())
16177 return std::make_pair(0U, &X86::GR32_NOREXRegClass);
16178 return std::make_pair(0U, &X86::GR64_NOREXRegClass);
16179 case 'f': // FP Stack registers.
16180 // If SSE is enabled for this VT, use f80 to ensure the isel moves the
16181 // value to the correct fpstack register class.
16182 if (VT == MVT::f32 && !isScalarFPTypeInSSEReg(VT))
16183 return std::make_pair(0U, &X86::RFP32RegClass);
16184 if (VT == MVT::f64 && !isScalarFPTypeInSSEReg(VT))
16185 return std::make_pair(0U, &X86::RFP64RegClass);
16186 return std::make_pair(0U, &X86::RFP80RegClass);
16187 case 'y': // MMX_REGS if MMX allowed.
16188 if (!Subtarget->hasMMX()) break;
16189 return std::make_pair(0U, &X86::VR64RegClass);
16190 case 'Y': // SSE_REGS if SSE2 allowed
16191 if (!Subtarget->hasSSE2()) break;
16193 case 'x': // SSE_REGS if SSE1 allowed or AVX_REGS if AVX allowed
16194 if (!Subtarget->hasSSE1()) break;
16196 switch (VT.getSimpleVT().SimpleTy) {
16198 // Scalar SSE types.
16201 return std::make_pair(0U, &X86::FR32RegClass);
16204 return std::make_pair(0U, &X86::FR64RegClass);
16212 return std::make_pair(0U, &X86::VR128RegClass);
16220 return std::make_pair(0U, &X86::VR256RegClass);
16226 // Use the default implementation in TargetLowering to convert the register
16227 // constraint into a member of a register class.
16228 std::pair<unsigned, const TargetRegisterClass*> Res;
16229 Res = TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
16231 // Not found as a standard register?
16232 if (Res.second == 0) {
16233 // Map st(0) -> st(7) -> ST0
16234 if (Constraint.size() == 7 && Constraint[0] == '{' &&
16235 tolower(Constraint[1]) == 's' &&
16236 tolower(Constraint[2]) == 't' &&
16237 Constraint[3] == '(' &&
16238 (Constraint[4] >= '0' && Constraint[4] <= '7') &&
16239 Constraint[5] == ')' &&
16240 Constraint[6] == '}') {
16242 Res.first = X86::ST0+Constraint[4]-'0';
16243 Res.second = &X86::RFP80RegClass;
16247 // GCC allows "st(0)" to be called just plain "st".
16248 if (StringRef("{st}").equals_lower(Constraint)) {
16249 Res.first = X86::ST0;
16250 Res.second = &X86::RFP80RegClass;
16255 if (StringRef("{flags}").equals_lower(Constraint)) {
16256 Res.first = X86::EFLAGS;
16257 Res.second = &X86::CCRRegClass;
16261 // 'A' means EAX + EDX.
16262 if (Constraint == "A") {
16263 Res.first = X86::EAX;
16264 Res.second = &X86::GR32_ADRegClass;
16270 // Otherwise, check to see if this is a register class of the wrong value
16271 // type. For example, we want to map "{ax},i32" -> {eax}, we don't want it to
16272 // turn into {ax},{dx}.
16273 if (Res.second->hasType(VT))
16274 return Res; // Correct type already, nothing to do.
16276 // All of the single-register GCC register classes map their values onto
16277 // 16-bit register pieces "ax","dx","cx","bx","si","di","bp","sp". If we
16278 // really want an 8-bit or 32-bit register, map to the appropriate register
16279 // class and return the appropriate register.
16280 if (Res.second == &X86::GR16RegClass) {
16281 if (VT == MVT::i8) {
16282 unsigned DestReg = 0;
16283 switch (Res.first) {
16285 case X86::AX: DestReg = X86::AL; break;
16286 case X86::DX: DestReg = X86::DL; break;
16287 case X86::CX: DestReg = X86::CL; break;
16288 case X86::BX: DestReg = X86::BL; break;
16291 Res.first = DestReg;
16292 Res.second = &X86::GR8RegClass;
16294 } else if (VT == MVT::i32) {
16295 unsigned DestReg = 0;
16296 switch (Res.first) {
16298 case X86::AX: DestReg = X86::EAX; break;
16299 case X86::DX: DestReg = X86::EDX; break;
16300 case X86::CX: DestReg = X86::ECX; break;
16301 case X86::BX: DestReg = X86::EBX; break;
16302 case X86::SI: DestReg = X86::ESI; break;
16303 case X86::DI: DestReg = X86::EDI; break;
16304 case X86::BP: DestReg = X86::EBP; break;
16305 case X86::SP: DestReg = X86::ESP; break;
16308 Res.first = DestReg;
16309 Res.second = &X86::GR32RegClass;
16311 } else if (VT == MVT::i64) {
16312 unsigned DestReg = 0;
16313 switch (Res.first) {
16315 case X86::AX: DestReg = X86::RAX; break;
16316 case X86::DX: DestReg = X86::RDX; break;
16317 case X86::CX: DestReg = X86::RCX; break;
16318 case X86::BX: DestReg = X86::RBX; break;
16319 case X86::SI: DestReg = X86::RSI; break;
16320 case X86::DI: DestReg = X86::RDI; break;
16321 case X86::BP: DestReg = X86::RBP; break;
16322 case X86::SP: DestReg = X86::RSP; break;
16325 Res.first = DestReg;
16326 Res.second = &X86::GR64RegClass;
16329 } else if (Res.second == &X86::FR32RegClass ||
16330 Res.second == &X86::FR64RegClass ||
16331 Res.second == &X86::VR128RegClass) {
16332 // Handle references to XMM physical registers that got mapped into the
16333 // wrong class. This can happen with constraints like {xmm0} where the
16334 // target independent register mapper will just pick the first match it can
16335 // find, ignoring the required type.
16337 if (VT == MVT::f32 || VT == MVT::i32)
16338 Res.second = &X86::FR32RegClass;
16339 else if (VT == MVT::f64 || VT == MVT::i64)
16340 Res.second = &X86::FR64RegClass;
16341 else if (X86::VR128RegClass.hasType(VT))
16342 Res.second = &X86::VR128RegClass;
16343 else if (X86::VR256RegClass.hasType(VT))
16344 Res.second = &X86::VR256RegClass;