1 //===-- X86ISelLowering.cpp - X86 DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that X86 uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #include "X86ISelLowering.h"
16 #include "Utils/X86ShuffleDecode.h"
17 #include "X86CallingConv.h"
18 #include "X86InstrBuilder.h"
19 #include "X86MachineFunctionInfo.h"
20 #include "X86TargetMachine.h"
21 #include "X86TargetObjectFile.h"
22 #include "llvm/ADT/SmallSet.h"
23 #include "llvm/ADT/Statistic.h"
24 #include "llvm/ADT/StringExtras.h"
25 #include "llvm/ADT/StringSwitch.h"
26 #include "llvm/ADT/VariadicFunction.h"
27 #include "llvm/CodeGen/IntrinsicLowering.h"
28 #include "llvm/CodeGen/MachineFrameInfo.h"
29 #include "llvm/CodeGen/MachineFunction.h"
30 #include "llvm/CodeGen/MachineInstrBuilder.h"
31 #include "llvm/CodeGen/MachineJumpTableInfo.h"
32 #include "llvm/CodeGen/MachineModuleInfo.h"
33 #include "llvm/CodeGen/MachineRegisterInfo.h"
34 #include "llvm/IR/CallSite.h"
35 #include "llvm/IR/CallingConv.h"
36 #include "llvm/IR/Constants.h"
37 #include "llvm/IR/DerivedTypes.h"
38 #include "llvm/IR/Function.h"
39 #include "llvm/IR/GlobalAlias.h"
40 #include "llvm/IR/GlobalVariable.h"
41 #include "llvm/IR/Instructions.h"
42 #include "llvm/IR/Intrinsics.h"
43 #include "llvm/MC/MCAsmInfo.h"
44 #include "llvm/MC/MCContext.h"
45 #include "llvm/MC/MCExpr.h"
46 #include "llvm/MC/MCSymbol.h"
47 #include "llvm/Support/Debug.h"
48 #include "llvm/Support/ErrorHandling.h"
49 #include "llvm/Support/MathExtras.h"
50 #include "llvm/Target/TargetOptions.h"
55 #define DEBUG_TYPE "x86-isel"
57 STATISTIC(NumTailCalls, "Number of tail calls");
59 // Forward declarations.
60 static SDValue getMOVL(SelectionDAG &DAG, SDLoc dl, EVT VT, SDValue V1,
63 static SDValue ExtractSubVector(SDValue Vec, unsigned IdxVal,
64 SelectionDAG &DAG, SDLoc dl,
65 unsigned vectorWidth) {
66 assert((vectorWidth == 128 || vectorWidth == 256) &&
67 "Unsupported vector width");
68 EVT VT = Vec.getValueType();
69 EVT ElVT = VT.getVectorElementType();
70 unsigned Factor = VT.getSizeInBits()/vectorWidth;
71 EVT ResultVT = EVT::getVectorVT(*DAG.getContext(), ElVT,
72 VT.getVectorNumElements()/Factor);
74 // Extract from UNDEF is UNDEF.
75 if (Vec.getOpcode() == ISD::UNDEF)
76 return DAG.getUNDEF(ResultVT);
78 // Extract the relevant vectorWidth bits. Generate an EXTRACT_SUBVECTOR
79 unsigned ElemsPerChunk = vectorWidth / ElVT.getSizeInBits();
81 // This is the index of the first element of the vectorWidth-bit chunk
83 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits()) / vectorWidth)
86 // If the input is a buildvector just emit a smaller one.
87 if (Vec.getOpcode() == ISD::BUILD_VECTOR)
88 return DAG.getNode(ISD::BUILD_VECTOR, dl, ResultVT,
89 makeArrayRef(Vec->op_begin()+NormalizedIdxVal,
92 SDValue VecIdx = DAG.getIntPtrConstant(NormalizedIdxVal);
93 SDValue Result = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, ResultVT, Vec,
99 /// Generate a DAG to grab 128-bits from a vector > 128 bits. This
100 /// sets things up to match to an AVX VEXTRACTF128 / VEXTRACTI128
101 /// or AVX-512 VEXTRACTF32x4 / VEXTRACTI32x4
102 /// instructions or a simple subregister reference. Idx is an index in the
103 /// 128 bits we want. It need not be aligned to a 128-bit bounday. That makes
104 /// lowering EXTRACT_VECTOR_ELT operations easier.
105 static SDValue Extract128BitVector(SDValue Vec, unsigned IdxVal,
106 SelectionDAG &DAG, SDLoc dl) {
107 assert((Vec.getValueType().is256BitVector() ||
108 Vec.getValueType().is512BitVector()) && "Unexpected vector size!");
109 return ExtractSubVector(Vec, IdxVal, DAG, dl, 128);
112 /// Generate a DAG to grab 256-bits from a 512-bit vector.
113 static SDValue Extract256BitVector(SDValue Vec, unsigned IdxVal,
114 SelectionDAG &DAG, SDLoc dl) {
115 assert(Vec.getValueType().is512BitVector() && "Unexpected vector size!");
116 return ExtractSubVector(Vec, IdxVal, DAG, dl, 256);
119 static SDValue InsertSubVector(SDValue Result, SDValue Vec,
120 unsigned IdxVal, SelectionDAG &DAG,
121 SDLoc dl, unsigned vectorWidth) {
122 assert((vectorWidth == 128 || vectorWidth == 256) &&
123 "Unsupported vector width");
124 // Inserting UNDEF is Result
125 if (Vec.getOpcode() == ISD::UNDEF)
127 EVT VT = Vec.getValueType();
128 EVT ElVT = VT.getVectorElementType();
129 EVT ResultVT = Result.getValueType();
131 // Insert the relevant vectorWidth bits.
132 unsigned ElemsPerChunk = vectorWidth/ElVT.getSizeInBits();
134 // This is the index of the first element of the vectorWidth-bit chunk
136 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits())/vectorWidth)
139 SDValue VecIdx = DAG.getIntPtrConstant(NormalizedIdxVal);
140 return DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResultVT, Result, Vec,
143 /// Generate a DAG to put 128-bits into a vector > 128 bits. This
144 /// sets things up to match to an AVX VINSERTF128/VINSERTI128 or
145 /// AVX-512 VINSERTF32x4/VINSERTI32x4 instructions or a
146 /// simple superregister reference. Idx is an index in the 128 bits
147 /// we want. It need not be aligned to a 128-bit bounday. That makes
148 /// lowering INSERT_VECTOR_ELT operations easier.
149 static SDValue Insert128BitVector(SDValue Result, SDValue Vec,
150 unsigned IdxVal, SelectionDAG &DAG,
152 assert(Vec.getValueType().is128BitVector() && "Unexpected vector size!");
153 return InsertSubVector(Result, Vec, IdxVal, DAG, dl, 128);
156 static SDValue Insert256BitVector(SDValue Result, SDValue Vec,
157 unsigned IdxVal, SelectionDAG &DAG,
159 assert(Vec.getValueType().is256BitVector() && "Unexpected vector size!");
160 return InsertSubVector(Result, Vec, IdxVal, DAG, dl, 256);
163 /// Concat two 128-bit vectors into a 256 bit vector using VINSERTF128
164 /// instructions. This is used because creating CONCAT_VECTOR nodes of
165 /// BUILD_VECTORS returns a larger BUILD_VECTOR while we're trying to lower
166 /// large BUILD_VECTORS.
167 static SDValue Concat128BitVectors(SDValue V1, SDValue V2, EVT VT,
168 unsigned NumElems, SelectionDAG &DAG,
170 SDValue V = Insert128BitVector(DAG.getUNDEF(VT), V1, 0, DAG, dl);
171 return Insert128BitVector(V, V2, NumElems/2, DAG, dl);
174 static SDValue Concat256BitVectors(SDValue V1, SDValue V2, EVT VT,
175 unsigned NumElems, SelectionDAG &DAG,
177 SDValue V = Insert256BitVector(DAG.getUNDEF(VT), V1, 0, DAG, dl);
178 return Insert256BitVector(V, V2, NumElems/2, DAG, dl);
181 static TargetLoweringObjectFile *createTLOF(X86TargetMachine &TM) {
182 const X86Subtarget *Subtarget = &TM.getSubtarget<X86Subtarget>();
183 bool is64Bit = Subtarget->is64Bit();
185 if (Subtarget->isTargetMacho()) {
187 return new X86_64MachoTargetObjectFile();
188 return new TargetLoweringObjectFileMachO();
191 if (Subtarget->isTargetLinux())
192 return new X86LinuxTargetObjectFile();
193 if (Subtarget->isTargetELF())
194 return new TargetLoweringObjectFileELF();
195 if (Subtarget->isTargetKnownWindowsMSVC())
196 return new X86WindowsTargetObjectFile();
197 if (Subtarget->isTargetCOFF())
198 return new TargetLoweringObjectFileCOFF();
199 llvm_unreachable("unknown subtarget type");
202 X86TargetLowering::X86TargetLowering(X86TargetMachine &TM)
203 : TargetLowering(TM, createTLOF(TM)) {
204 Subtarget = &TM.getSubtarget<X86Subtarget>();
205 X86ScalarSSEf64 = Subtarget->hasSSE2();
206 X86ScalarSSEf32 = Subtarget->hasSSE1();
207 TD = getDataLayout();
209 resetOperationActions();
212 void X86TargetLowering::resetOperationActions() {
213 const TargetMachine &TM = getTargetMachine();
214 static bool FirstTimeThrough = true;
216 // If none of the target options have changed, then we don't need to reset the
217 // operation actions.
218 if (!FirstTimeThrough && TO == TM.Options) return;
220 if (!FirstTimeThrough) {
221 // Reinitialize the actions.
223 FirstTimeThrough = false;
228 // Set up the TargetLowering object.
229 static const MVT IntVTs[] = { MVT::i8, MVT::i16, MVT::i32, MVT::i64 };
231 // X86 is weird, it always uses i8 for shift amounts and setcc results.
232 setBooleanContents(ZeroOrOneBooleanContent);
233 // X86-SSE is even stranger. It uses -1 or 0 for vector masks.
234 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
236 // For 64-bit since we have so many registers use the ILP scheduler, for
237 // 32-bit code use the register pressure specific scheduling.
238 // For Atom, always use ILP scheduling.
239 if (Subtarget->isAtom())
240 setSchedulingPreference(Sched::ILP);
241 else if (Subtarget->is64Bit())
242 setSchedulingPreference(Sched::ILP);
244 setSchedulingPreference(Sched::RegPressure);
245 const X86RegisterInfo *RegInfo =
246 static_cast<const X86RegisterInfo*>(TM.getRegisterInfo());
247 setStackPointerRegisterToSaveRestore(RegInfo->getStackRegister());
249 // Bypass expensive divides on Atom when compiling with O2
250 if (Subtarget->hasSlowDivide() && TM.getOptLevel() >= CodeGenOpt::Default) {
251 addBypassSlowDiv(32, 8);
252 if (Subtarget->is64Bit())
253 addBypassSlowDiv(64, 16);
256 if (Subtarget->isTargetKnownWindowsMSVC()) {
257 // Setup Windows compiler runtime calls.
258 setLibcallName(RTLIB::SDIV_I64, "_alldiv");
259 setLibcallName(RTLIB::UDIV_I64, "_aulldiv");
260 setLibcallName(RTLIB::SREM_I64, "_allrem");
261 setLibcallName(RTLIB::UREM_I64, "_aullrem");
262 setLibcallName(RTLIB::MUL_I64, "_allmul");
263 setLibcallCallingConv(RTLIB::SDIV_I64, CallingConv::X86_StdCall);
264 setLibcallCallingConv(RTLIB::UDIV_I64, CallingConv::X86_StdCall);
265 setLibcallCallingConv(RTLIB::SREM_I64, CallingConv::X86_StdCall);
266 setLibcallCallingConv(RTLIB::UREM_I64, CallingConv::X86_StdCall);
267 setLibcallCallingConv(RTLIB::MUL_I64, CallingConv::X86_StdCall);
269 // The _ftol2 runtime function has an unusual calling conv, which
270 // is modeled by a special pseudo-instruction.
271 setLibcallName(RTLIB::FPTOUINT_F64_I64, nullptr);
272 setLibcallName(RTLIB::FPTOUINT_F32_I64, nullptr);
273 setLibcallName(RTLIB::FPTOUINT_F64_I32, nullptr);
274 setLibcallName(RTLIB::FPTOUINT_F32_I32, nullptr);
277 if (Subtarget->isTargetDarwin()) {
278 // Darwin should use _setjmp/_longjmp instead of setjmp/longjmp.
279 setUseUnderscoreSetJmp(false);
280 setUseUnderscoreLongJmp(false);
281 } else if (Subtarget->isTargetWindowsGNU()) {
282 // MS runtime is weird: it exports _setjmp, but longjmp!
283 setUseUnderscoreSetJmp(true);
284 setUseUnderscoreLongJmp(false);
286 setUseUnderscoreSetJmp(true);
287 setUseUnderscoreLongJmp(true);
290 // Set up the register classes.
291 addRegisterClass(MVT::i8, &X86::GR8RegClass);
292 addRegisterClass(MVT::i16, &X86::GR16RegClass);
293 addRegisterClass(MVT::i32, &X86::GR32RegClass);
294 if (Subtarget->is64Bit())
295 addRegisterClass(MVT::i64, &X86::GR64RegClass);
297 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
299 // We don't accept any truncstore of integer registers.
300 setTruncStoreAction(MVT::i64, MVT::i32, Expand);
301 setTruncStoreAction(MVT::i64, MVT::i16, Expand);
302 setTruncStoreAction(MVT::i64, MVT::i8 , Expand);
303 setTruncStoreAction(MVT::i32, MVT::i16, Expand);
304 setTruncStoreAction(MVT::i32, MVT::i8 , Expand);
305 setTruncStoreAction(MVT::i16, MVT::i8, Expand);
307 // SETOEQ and SETUNE require checking two conditions.
308 setCondCodeAction(ISD::SETOEQ, MVT::f32, Expand);
309 setCondCodeAction(ISD::SETOEQ, MVT::f64, Expand);
310 setCondCodeAction(ISD::SETOEQ, MVT::f80, Expand);
311 setCondCodeAction(ISD::SETUNE, MVT::f32, Expand);
312 setCondCodeAction(ISD::SETUNE, MVT::f64, Expand);
313 setCondCodeAction(ISD::SETUNE, MVT::f80, Expand);
315 // Promote all UINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have this
317 setOperationAction(ISD::UINT_TO_FP , MVT::i1 , Promote);
318 setOperationAction(ISD::UINT_TO_FP , MVT::i8 , Promote);
319 setOperationAction(ISD::UINT_TO_FP , MVT::i16 , Promote);
321 if (Subtarget->is64Bit()) {
322 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote);
323 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
324 } else if (!TM.Options.UseSoftFloat) {
325 // We have an algorithm for SSE2->double, and we turn this into a
326 // 64-bit FILD followed by conditional FADD for other targets.
327 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
328 // We have an algorithm for SSE2, and we turn this into a 64-bit
329 // FILD for other targets.
330 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Custom);
333 // Promote i1/i8 SINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have
335 setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote);
336 setOperationAction(ISD::SINT_TO_FP , MVT::i8 , Promote);
338 if (!TM.Options.UseSoftFloat) {
339 // SSE has no i16 to fp conversion, only i32
340 if (X86ScalarSSEf32) {
341 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
342 // f32 and f64 cases are Legal, f80 case is not
343 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
345 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Custom);
346 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
349 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
350 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Promote);
353 // In 32-bit mode these are custom lowered. In 64-bit mode F32 and F64
354 // are Legal, f80 is custom lowered.
355 setOperationAction(ISD::FP_TO_SINT , MVT::i64 , Custom);
356 setOperationAction(ISD::SINT_TO_FP , MVT::i64 , Custom);
358 // Promote i1/i8 FP_TO_SINT to larger FP_TO_SINTS's, as X86 doesn't have
360 setOperationAction(ISD::FP_TO_SINT , MVT::i1 , Promote);
361 setOperationAction(ISD::FP_TO_SINT , MVT::i8 , Promote);
363 if (X86ScalarSSEf32) {
364 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Promote);
365 // f32 and f64 cases are Legal, f80 case is not
366 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
368 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Custom);
369 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
372 // Handle FP_TO_UINT by promoting the destination to a larger signed
374 setOperationAction(ISD::FP_TO_UINT , MVT::i1 , Promote);
375 setOperationAction(ISD::FP_TO_UINT , MVT::i8 , Promote);
376 setOperationAction(ISD::FP_TO_UINT , MVT::i16 , Promote);
378 if (Subtarget->is64Bit()) {
379 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Expand);
380 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote);
381 } else if (!TM.Options.UseSoftFloat) {
382 // Since AVX is a superset of SSE3, only check for SSE here.
383 if (Subtarget->hasSSE1() && !Subtarget->hasSSE3())
384 // Expand FP_TO_UINT into a select.
385 // FIXME: We would like to use a Custom expander here eventually to do
386 // the optimal thing for SSE vs. the default expansion in the legalizer.
387 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Expand);
389 // With SSE3 we can use fisttpll to convert to a signed i64; without
390 // SSE, we're stuck with a fistpll.
391 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Custom);
394 if (isTargetFTOL()) {
395 // Use the _ftol2 runtime function, which has a pseudo-instruction
396 // to handle its weird calling convention.
397 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Custom);
400 // TODO: when we have SSE, these could be more efficient, by using movd/movq.
401 if (!X86ScalarSSEf64) {
402 setOperationAction(ISD::BITCAST , MVT::f32 , Expand);
403 setOperationAction(ISD::BITCAST , MVT::i32 , Expand);
404 if (Subtarget->is64Bit()) {
405 setOperationAction(ISD::BITCAST , MVT::f64 , Expand);
406 // Without SSE, i64->f64 goes through memory.
407 setOperationAction(ISD::BITCAST , MVT::i64 , Expand);
411 // Scalar integer divide and remainder are lowered to use operations that
412 // produce two results, to match the available instructions. This exposes
413 // the two-result form to trivial CSE, which is able to combine x/y and x%y
414 // into a single instruction.
416 // Scalar integer multiply-high is also lowered to use two-result
417 // operations, to match the available instructions. However, plain multiply
418 // (low) operations are left as Legal, as there are single-result
419 // instructions for this in x86. Using the two-result multiply instructions
420 // when both high and low results are needed must be arranged by dagcombine.
421 for (unsigned i = 0; i != array_lengthof(IntVTs); ++i) {
423 setOperationAction(ISD::MULHS, VT, Expand);
424 setOperationAction(ISD::MULHU, VT, Expand);
425 setOperationAction(ISD::SDIV, VT, Expand);
426 setOperationAction(ISD::UDIV, VT, Expand);
427 setOperationAction(ISD::SREM, VT, Expand);
428 setOperationAction(ISD::UREM, VT, Expand);
430 // Add/Sub overflow ops with MVT::Glues are lowered to EFLAGS dependences.
431 setOperationAction(ISD::ADDC, VT, Custom);
432 setOperationAction(ISD::ADDE, VT, Custom);
433 setOperationAction(ISD::SUBC, VT, Custom);
434 setOperationAction(ISD::SUBE, VT, Custom);
437 setOperationAction(ISD::BR_JT , MVT::Other, Expand);
438 setOperationAction(ISD::BRCOND , MVT::Other, Custom);
439 setOperationAction(ISD::BR_CC , MVT::f32, Expand);
440 setOperationAction(ISD::BR_CC , MVT::f64, Expand);
441 setOperationAction(ISD::BR_CC , MVT::f80, Expand);
442 setOperationAction(ISD::BR_CC , MVT::i8, Expand);
443 setOperationAction(ISD::BR_CC , MVT::i16, Expand);
444 setOperationAction(ISD::BR_CC , MVT::i32, Expand);
445 setOperationAction(ISD::BR_CC , MVT::i64, Expand);
446 setOperationAction(ISD::SELECT_CC , MVT::Other, Expand);
447 if (Subtarget->is64Bit())
448 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal);
449 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Legal);
450 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Legal);
451 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
452 setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand);
453 setOperationAction(ISD::FREM , MVT::f32 , Expand);
454 setOperationAction(ISD::FREM , MVT::f64 , Expand);
455 setOperationAction(ISD::FREM , MVT::f80 , Expand);
456 setOperationAction(ISD::FLT_ROUNDS_ , MVT::i32 , Custom);
458 // Promote the i8 variants and force them on up to i32 which has a shorter
460 setOperationAction(ISD::CTTZ , MVT::i8 , Promote);
461 AddPromotedToType (ISD::CTTZ , MVT::i8 , MVT::i32);
462 setOperationAction(ISD::CTTZ_ZERO_UNDEF , MVT::i8 , Promote);
463 AddPromotedToType (ISD::CTTZ_ZERO_UNDEF , MVT::i8 , MVT::i32);
464 if (Subtarget->hasBMI()) {
465 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i16 , Expand);
466 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32 , Expand);
467 if (Subtarget->is64Bit())
468 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand);
470 setOperationAction(ISD::CTTZ , MVT::i16 , Custom);
471 setOperationAction(ISD::CTTZ , MVT::i32 , Custom);
472 if (Subtarget->is64Bit())
473 setOperationAction(ISD::CTTZ , MVT::i64 , Custom);
476 if (Subtarget->hasLZCNT()) {
477 // When promoting the i8 variants, force them to i32 for a shorter
479 setOperationAction(ISD::CTLZ , MVT::i8 , Promote);
480 AddPromotedToType (ISD::CTLZ , MVT::i8 , MVT::i32);
481 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Promote);
482 AddPromotedToType (ISD::CTLZ_ZERO_UNDEF, MVT::i8 , MVT::i32);
483 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Expand);
484 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Expand);
485 if (Subtarget->is64Bit())
486 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Expand);
488 setOperationAction(ISD::CTLZ , MVT::i8 , Custom);
489 setOperationAction(ISD::CTLZ , MVT::i16 , Custom);
490 setOperationAction(ISD::CTLZ , MVT::i32 , Custom);
491 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Custom);
492 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Custom);
493 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Custom);
494 if (Subtarget->is64Bit()) {
495 setOperationAction(ISD::CTLZ , MVT::i64 , Custom);
496 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Custom);
500 if (Subtarget->hasPOPCNT()) {
501 setOperationAction(ISD::CTPOP , MVT::i8 , Promote);
503 setOperationAction(ISD::CTPOP , MVT::i8 , Expand);
504 setOperationAction(ISD::CTPOP , MVT::i16 , Expand);
505 setOperationAction(ISD::CTPOP , MVT::i32 , Expand);
506 if (Subtarget->is64Bit())
507 setOperationAction(ISD::CTPOP , MVT::i64 , Expand);
510 setOperationAction(ISD::READCYCLECOUNTER , MVT::i64 , Custom);
512 if (!Subtarget->hasMOVBE())
513 setOperationAction(ISD::BSWAP , MVT::i16 , Expand);
515 // These should be promoted to a larger select which is supported.
516 setOperationAction(ISD::SELECT , MVT::i1 , Promote);
517 // X86 wants to expand cmov itself.
518 setOperationAction(ISD::SELECT , MVT::i8 , Custom);
519 setOperationAction(ISD::SELECT , MVT::i16 , Custom);
520 setOperationAction(ISD::SELECT , MVT::i32 , Custom);
521 setOperationAction(ISD::SELECT , MVT::f32 , Custom);
522 setOperationAction(ISD::SELECT , MVT::f64 , Custom);
523 setOperationAction(ISD::SELECT , MVT::f80 , Custom);
524 setOperationAction(ISD::SETCC , MVT::i8 , Custom);
525 setOperationAction(ISD::SETCC , MVT::i16 , Custom);
526 setOperationAction(ISD::SETCC , MVT::i32 , Custom);
527 setOperationAction(ISD::SETCC , MVT::f32 , Custom);
528 setOperationAction(ISD::SETCC , MVT::f64 , Custom);
529 setOperationAction(ISD::SETCC , MVT::f80 , Custom);
530 if (Subtarget->is64Bit()) {
531 setOperationAction(ISD::SELECT , MVT::i64 , Custom);
532 setOperationAction(ISD::SETCC , MVT::i64 , Custom);
534 setOperationAction(ISD::EH_RETURN , MVT::Other, Custom);
535 // NOTE: EH_SJLJ_SETJMP/_LONGJMP supported here is NOT intended to support
536 // SjLj exception handling but a light-weight setjmp/longjmp replacement to
537 // support continuation, user-level threading, and etc.. As a result, no
538 // other SjLj exception interfaces are implemented and please don't build
539 // your own exception handling based on them.
540 // LLVM/Clang supports zero-cost DWARF exception handling.
541 setOperationAction(ISD::EH_SJLJ_SETJMP, MVT::i32, Custom);
542 setOperationAction(ISD::EH_SJLJ_LONGJMP, MVT::Other, Custom);
545 setOperationAction(ISD::ConstantPool , MVT::i32 , Custom);
546 setOperationAction(ISD::JumpTable , MVT::i32 , Custom);
547 setOperationAction(ISD::GlobalAddress , MVT::i32 , Custom);
548 setOperationAction(ISD::GlobalTLSAddress, MVT::i32 , Custom);
549 if (Subtarget->is64Bit())
550 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
551 setOperationAction(ISD::ExternalSymbol , MVT::i32 , Custom);
552 setOperationAction(ISD::BlockAddress , MVT::i32 , Custom);
553 if (Subtarget->is64Bit()) {
554 setOperationAction(ISD::ConstantPool , MVT::i64 , Custom);
555 setOperationAction(ISD::JumpTable , MVT::i64 , Custom);
556 setOperationAction(ISD::GlobalAddress , MVT::i64 , Custom);
557 setOperationAction(ISD::ExternalSymbol, MVT::i64 , Custom);
558 setOperationAction(ISD::BlockAddress , MVT::i64 , Custom);
560 // 64-bit addm sub, shl, sra, srl (iff 32-bit x86)
561 setOperationAction(ISD::SHL_PARTS , MVT::i32 , Custom);
562 setOperationAction(ISD::SRA_PARTS , MVT::i32 , Custom);
563 setOperationAction(ISD::SRL_PARTS , MVT::i32 , Custom);
564 if (Subtarget->is64Bit()) {
565 setOperationAction(ISD::SHL_PARTS , MVT::i64 , Custom);
566 setOperationAction(ISD::SRA_PARTS , MVT::i64 , Custom);
567 setOperationAction(ISD::SRL_PARTS , MVT::i64 , Custom);
570 if (Subtarget->hasSSE1())
571 setOperationAction(ISD::PREFETCH , MVT::Other, Legal);
573 setOperationAction(ISD::ATOMIC_FENCE , MVT::Other, Custom);
575 // Expand certain atomics
576 for (unsigned i = 0; i != array_lengthof(IntVTs); ++i) {
578 setOperationAction(ISD::ATOMIC_CMP_SWAP, VT, Custom);
579 setOperationAction(ISD::ATOMIC_LOAD_SUB, VT, Custom);
580 setOperationAction(ISD::ATOMIC_STORE, VT, Custom);
583 if (!Subtarget->is64Bit()) {
584 setOperationAction(ISD::ATOMIC_LOAD, MVT::i64, Custom);
585 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i64, Custom);
586 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i64, Custom);
587 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i64, Custom);
588 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i64, Custom);
589 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i64, Custom);
590 setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i64, Custom);
591 setOperationAction(ISD::ATOMIC_SWAP, MVT::i64, Custom);
592 setOperationAction(ISD::ATOMIC_LOAD_MAX, MVT::i64, Custom);
593 setOperationAction(ISD::ATOMIC_LOAD_MIN, MVT::i64, Custom);
594 setOperationAction(ISD::ATOMIC_LOAD_UMAX, MVT::i64, Custom);
595 setOperationAction(ISD::ATOMIC_LOAD_UMIN, MVT::i64, Custom);
598 if (Subtarget->hasCmpxchg16b()) {
599 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i128, Custom);
602 // FIXME - use subtarget debug flags
603 if (!Subtarget->isTargetDarwin() &&
604 !Subtarget->isTargetELF() &&
605 !Subtarget->isTargetCygMing()) {
606 setOperationAction(ISD::EH_LABEL, MVT::Other, Expand);
609 if (Subtarget->is64Bit()) {
610 setExceptionPointerRegister(X86::RAX);
611 setExceptionSelectorRegister(X86::RDX);
613 setExceptionPointerRegister(X86::EAX);
614 setExceptionSelectorRegister(X86::EDX);
616 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i32, Custom);
617 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i64, Custom);
619 setOperationAction(ISD::INIT_TRAMPOLINE, MVT::Other, Custom);
620 setOperationAction(ISD::ADJUST_TRAMPOLINE, MVT::Other, Custom);
622 setOperationAction(ISD::TRAP, MVT::Other, Legal);
623 setOperationAction(ISD::DEBUGTRAP, MVT::Other, Legal);
625 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
626 setOperationAction(ISD::VASTART , MVT::Other, Custom);
627 setOperationAction(ISD::VAEND , MVT::Other, Expand);
628 if (Subtarget->is64Bit() && !Subtarget->isTargetWin64()) {
629 // TargetInfo::X86_64ABIBuiltinVaList
630 setOperationAction(ISD::VAARG , MVT::Other, Custom);
631 setOperationAction(ISD::VACOPY , MVT::Other, Custom);
633 // TargetInfo::CharPtrBuiltinVaList
634 setOperationAction(ISD::VAARG , MVT::Other, Expand);
635 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
638 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
639 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
641 setOperationAction(ISD::DYNAMIC_STACKALLOC, Subtarget->is64Bit() ?
642 MVT::i64 : MVT::i32, Custom);
644 if (!TM.Options.UseSoftFloat && X86ScalarSSEf64) {
645 // f32 and f64 use SSE.
646 // Set up the FP register classes.
647 addRegisterClass(MVT::f32, &X86::FR32RegClass);
648 addRegisterClass(MVT::f64, &X86::FR64RegClass);
650 // Use ANDPD to simulate FABS.
651 setOperationAction(ISD::FABS , MVT::f64, Custom);
652 setOperationAction(ISD::FABS , MVT::f32, Custom);
654 // Use XORP to simulate FNEG.
655 setOperationAction(ISD::FNEG , MVT::f64, Custom);
656 setOperationAction(ISD::FNEG , MVT::f32, Custom);
658 // Use ANDPD and ORPD to simulate FCOPYSIGN.
659 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
660 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
662 // Lower this to FGETSIGNx86 plus an AND.
663 setOperationAction(ISD::FGETSIGN, MVT::i64, Custom);
664 setOperationAction(ISD::FGETSIGN, MVT::i32, Custom);
666 // We don't support sin/cos/fmod
667 setOperationAction(ISD::FSIN , MVT::f64, Expand);
668 setOperationAction(ISD::FCOS , MVT::f64, Expand);
669 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
670 setOperationAction(ISD::FSIN , MVT::f32, Expand);
671 setOperationAction(ISD::FCOS , MVT::f32, Expand);
672 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
674 // Expand FP immediates into loads from the stack, except for the special
676 addLegalFPImmediate(APFloat(+0.0)); // xorpd
677 addLegalFPImmediate(APFloat(+0.0f)); // xorps
678 } else if (!TM.Options.UseSoftFloat && X86ScalarSSEf32) {
679 // Use SSE for f32, x87 for f64.
680 // Set up the FP register classes.
681 addRegisterClass(MVT::f32, &X86::FR32RegClass);
682 addRegisterClass(MVT::f64, &X86::RFP64RegClass);
684 // Use ANDPS to simulate FABS.
685 setOperationAction(ISD::FABS , MVT::f32, Custom);
687 // Use XORP to simulate FNEG.
688 setOperationAction(ISD::FNEG , MVT::f32, Custom);
690 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
692 // Use ANDPS and ORPS to simulate FCOPYSIGN.
693 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
694 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
696 // We don't support sin/cos/fmod
697 setOperationAction(ISD::FSIN , MVT::f32, Expand);
698 setOperationAction(ISD::FCOS , MVT::f32, Expand);
699 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
701 // Special cases we handle for FP constants.
702 addLegalFPImmediate(APFloat(+0.0f)); // xorps
703 addLegalFPImmediate(APFloat(+0.0)); // FLD0
704 addLegalFPImmediate(APFloat(+1.0)); // FLD1
705 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
706 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
708 if (!TM.Options.UnsafeFPMath) {
709 setOperationAction(ISD::FSIN , MVT::f64, Expand);
710 setOperationAction(ISD::FCOS , MVT::f64, Expand);
711 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
713 } else if (!TM.Options.UseSoftFloat) {
714 // f32 and f64 in x87.
715 // Set up the FP register classes.
716 addRegisterClass(MVT::f64, &X86::RFP64RegClass);
717 addRegisterClass(MVT::f32, &X86::RFP32RegClass);
719 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
720 setOperationAction(ISD::UNDEF, MVT::f32, Expand);
721 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
722 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
724 if (!TM.Options.UnsafeFPMath) {
725 setOperationAction(ISD::FSIN , MVT::f64, Expand);
726 setOperationAction(ISD::FSIN , MVT::f32, Expand);
727 setOperationAction(ISD::FCOS , MVT::f64, Expand);
728 setOperationAction(ISD::FCOS , MVT::f32, Expand);
729 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
730 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
732 addLegalFPImmediate(APFloat(+0.0)); // FLD0
733 addLegalFPImmediate(APFloat(+1.0)); // FLD1
734 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
735 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
736 addLegalFPImmediate(APFloat(+0.0f)); // FLD0
737 addLegalFPImmediate(APFloat(+1.0f)); // FLD1
738 addLegalFPImmediate(APFloat(-0.0f)); // FLD0/FCHS
739 addLegalFPImmediate(APFloat(-1.0f)); // FLD1/FCHS
742 // We don't support FMA.
743 setOperationAction(ISD::FMA, MVT::f64, Expand);
744 setOperationAction(ISD::FMA, MVT::f32, Expand);
746 // Long double always uses X87.
747 if (!TM.Options.UseSoftFloat) {
748 addRegisterClass(MVT::f80, &X86::RFP80RegClass);
749 setOperationAction(ISD::UNDEF, MVT::f80, Expand);
750 setOperationAction(ISD::FCOPYSIGN, MVT::f80, Expand);
752 APFloat TmpFlt = APFloat::getZero(APFloat::x87DoubleExtended);
753 addLegalFPImmediate(TmpFlt); // FLD0
755 addLegalFPImmediate(TmpFlt); // FLD0/FCHS
758 APFloat TmpFlt2(+1.0);
759 TmpFlt2.convert(APFloat::x87DoubleExtended, APFloat::rmNearestTiesToEven,
761 addLegalFPImmediate(TmpFlt2); // FLD1
762 TmpFlt2.changeSign();
763 addLegalFPImmediate(TmpFlt2); // FLD1/FCHS
766 if (!TM.Options.UnsafeFPMath) {
767 setOperationAction(ISD::FSIN , MVT::f80, Expand);
768 setOperationAction(ISD::FCOS , MVT::f80, Expand);
769 setOperationAction(ISD::FSINCOS, MVT::f80, Expand);
772 setOperationAction(ISD::FFLOOR, MVT::f80, Expand);
773 setOperationAction(ISD::FCEIL, MVT::f80, Expand);
774 setOperationAction(ISD::FTRUNC, MVT::f80, Expand);
775 setOperationAction(ISD::FRINT, MVT::f80, Expand);
776 setOperationAction(ISD::FNEARBYINT, MVT::f80, Expand);
777 setOperationAction(ISD::FMA, MVT::f80, Expand);
780 // Always use a library call for pow.
781 setOperationAction(ISD::FPOW , MVT::f32 , Expand);
782 setOperationAction(ISD::FPOW , MVT::f64 , Expand);
783 setOperationAction(ISD::FPOW , MVT::f80 , Expand);
785 setOperationAction(ISD::FLOG, MVT::f80, Expand);
786 setOperationAction(ISD::FLOG2, MVT::f80, Expand);
787 setOperationAction(ISD::FLOG10, MVT::f80, Expand);
788 setOperationAction(ISD::FEXP, MVT::f80, Expand);
789 setOperationAction(ISD::FEXP2, MVT::f80, Expand);
791 // First set operation action for all vector types to either promote
792 // (for widening) or expand (for scalarization). Then we will selectively
793 // turn on ones that can be effectively codegen'd.
794 for (int i = MVT::FIRST_VECTOR_VALUETYPE;
795 i <= MVT::LAST_VECTOR_VALUETYPE; ++i) {
796 MVT VT = (MVT::SimpleValueType)i;
797 setOperationAction(ISD::ADD , VT, Expand);
798 setOperationAction(ISD::SUB , VT, Expand);
799 setOperationAction(ISD::FADD, VT, Expand);
800 setOperationAction(ISD::FNEG, VT, Expand);
801 setOperationAction(ISD::FSUB, VT, Expand);
802 setOperationAction(ISD::MUL , VT, Expand);
803 setOperationAction(ISD::FMUL, VT, Expand);
804 setOperationAction(ISD::SDIV, VT, Expand);
805 setOperationAction(ISD::UDIV, VT, Expand);
806 setOperationAction(ISD::FDIV, VT, Expand);
807 setOperationAction(ISD::SREM, VT, Expand);
808 setOperationAction(ISD::UREM, VT, Expand);
809 setOperationAction(ISD::LOAD, VT, Expand);
810 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Expand);
811 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT,Expand);
812 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Expand);
813 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT,Expand);
814 setOperationAction(ISD::INSERT_SUBVECTOR, VT,Expand);
815 setOperationAction(ISD::FABS, VT, Expand);
816 setOperationAction(ISD::FSIN, VT, Expand);
817 setOperationAction(ISD::FSINCOS, VT, Expand);
818 setOperationAction(ISD::FCOS, VT, Expand);
819 setOperationAction(ISD::FSINCOS, VT, Expand);
820 setOperationAction(ISD::FREM, VT, Expand);
821 setOperationAction(ISD::FMA, VT, Expand);
822 setOperationAction(ISD::FPOWI, VT, Expand);
823 setOperationAction(ISD::FSQRT, VT, Expand);
824 setOperationAction(ISD::FCOPYSIGN, VT, Expand);
825 setOperationAction(ISD::FFLOOR, VT, Expand);
826 setOperationAction(ISD::FCEIL, VT, Expand);
827 setOperationAction(ISD::FTRUNC, VT, Expand);
828 setOperationAction(ISD::FRINT, VT, Expand);
829 setOperationAction(ISD::FNEARBYINT, VT, Expand);
830 setOperationAction(ISD::SMUL_LOHI, VT, Expand);
831 setOperationAction(ISD::MULHS, VT, Expand);
832 setOperationAction(ISD::UMUL_LOHI, VT, Expand);
833 setOperationAction(ISD::MULHU, VT, Expand);
834 setOperationAction(ISD::SDIVREM, VT, Expand);
835 setOperationAction(ISD::UDIVREM, VT, Expand);
836 setOperationAction(ISD::FPOW, VT, Expand);
837 setOperationAction(ISD::CTPOP, VT, Expand);
838 setOperationAction(ISD::CTTZ, VT, Expand);
839 setOperationAction(ISD::CTTZ_ZERO_UNDEF, VT, Expand);
840 setOperationAction(ISD::CTLZ, VT, Expand);
841 setOperationAction(ISD::CTLZ_ZERO_UNDEF, VT, Expand);
842 setOperationAction(ISD::SHL, VT, Expand);
843 setOperationAction(ISD::SRA, VT, Expand);
844 setOperationAction(ISD::SRL, VT, Expand);
845 setOperationAction(ISD::ROTL, VT, Expand);
846 setOperationAction(ISD::ROTR, VT, Expand);
847 setOperationAction(ISD::BSWAP, VT, Expand);
848 setOperationAction(ISD::SETCC, VT, Expand);
849 setOperationAction(ISD::FLOG, VT, Expand);
850 setOperationAction(ISD::FLOG2, VT, Expand);
851 setOperationAction(ISD::FLOG10, VT, Expand);
852 setOperationAction(ISD::FEXP, VT, Expand);
853 setOperationAction(ISD::FEXP2, VT, Expand);
854 setOperationAction(ISD::FP_TO_UINT, VT, Expand);
855 setOperationAction(ISD::FP_TO_SINT, VT, Expand);
856 setOperationAction(ISD::UINT_TO_FP, VT, Expand);
857 setOperationAction(ISD::SINT_TO_FP, VT, Expand);
858 setOperationAction(ISD::SIGN_EXTEND_INREG, VT,Expand);
859 setOperationAction(ISD::TRUNCATE, VT, Expand);
860 setOperationAction(ISD::SIGN_EXTEND, VT, Expand);
861 setOperationAction(ISD::ZERO_EXTEND, VT, Expand);
862 setOperationAction(ISD::ANY_EXTEND, VT, Expand);
863 setOperationAction(ISD::VSELECT, VT, Expand);
864 for (int InnerVT = MVT::FIRST_VECTOR_VALUETYPE;
865 InnerVT <= MVT::LAST_VECTOR_VALUETYPE; ++InnerVT)
866 setTruncStoreAction(VT,
867 (MVT::SimpleValueType)InnerVT, Expand);
868 setLoadExtAction(ISD::SEXTLOAD, VT, Expand);
869 setLoadExtAction(ISD::ZEXTLOAD, VT, Expand);
870 setLoadExtAction(ISD::EXTLOAD, VT, Expand);
873 // FIXME: In order to prevent SSE instructions being expanded to MMX ones
874 // with -msoft-float, disable use of MMX as well.
875 if (!TM.Options.UseSoftFloat && Subtarget->hasMMX()) {
876 addRegisterClass(MVT::x86mmx, &X86::VR64RegClass);
877 // No operations on x86mmx supported, everything uses intrinsics.
880 // MMX-sized vectors (other than x86mmx) are expected to be expanded
881 // into smaller operations.
882 setOperationAction(ISD::MULHS, MVT::v8i8, Expand);
883 setOperationAction(ISD::MULHS, MVT::v4i16, Expand);
884 setOperationAction(ISD::MULHS, MVT::v2i32, Expand);
885 setOperationAction(ISD::MULHS, MVT::v1i64, Expand);
886 setOperationAction(ISD::AND, MVT::v8i8, Expand);
887 setOperationAction(ISD::AND, MVT::v4i16, Expand);
888 setOperationAction(ISD::AND, MVT::v2i32, Expand);
889 setOperationAction(ISD::AND, MVT::v1i64, Expand);
890 setOperationAction(ISD::OR, MVT::v8i8, Expand);
891 setOperationAction(ISD::OR, MVT::v4i16, Expand);
892 setOperationAction(ISD::OR, MVT::v2i32, Expand);
893 setOperationAction(ISD::OR, MVT::v1i64, Expand);
894 setOperationAction(ISD::XOR, MVT::v8i8, Expand);
895 setOperationAction(ISD::XOR, MVT::v4i16, Expand);
896 setOperationAction(ISD::XOR, MVT::v2i32, Expand);
897 setOperationAction(ISD::XOR, MVT::v1i64, Expand);
898 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i8, Expand);
899 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i16, Expand);
900 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2i32, Expand);
901 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v1i64, Expand);
902 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v1i64, Expand);
903 setOperationAction(ISD::SELECT, MVT::v8i8, Expand);
904 setOperationAction(ISD::SELECT, MVT::v4i16, Expand);
905 setOperationAction(ISD::SELECT, MVT::v2i32, Expand);
906 setOperationAction(ISD::SELECT, MVT::v1i64, Expand);
907 setOperationAction(ISD::BITCAST, MVT::v8i8, Expand);
908 setOperationAction(ISD::BITCAST, MVT::v4i16, Expand);
909 setOperationAction(ISD::BITCAST, MVT::v2i32, Expand);
910 setOperationAction(ISD::BITCAST, MVT::v1i64, Expand);
912 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE1()) {
913 addRegisterClass(MVT::v4f32, &X86::VR128RegClass);
915 setOperationAction(ISD::FADD, MVT::v4f32, Legal);
916 setOperationAction(ISD::FSUB, MVT::v4f32, Legal);
917 setOperationAction(ISD::FMUL, MVT::v4f32, Legal);
918 setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
919 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal);
920 setOperationAction(ISD::FNEG, MVT::v4f32, Custom);
921 setOperationAction(ISD::FABS, MVT::v4f32, Custom);
922 setOperationAction(ISD::LOAD, MVT::v4f32, Legal);
923 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
924 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f32, Custom);
925 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
926 setOperationAction(ISD::SELECT, MVT::v4f32, Custom);
929 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE2()) {
930 addRegisterClass(MVT::v2f64, &X86::VR128RegClass);
932 // FIXME: Unfortunately -soft-float and -no-implicit-float means XMM
933 // registers cannot be used even for integer operations.
934 addRegisterClass(MVT::v16i8, &X86::VR128RegClass);
935 addRegisterClass(MVT::v8i16, &X86::VR128RegClass);
936 addRegisterClass(MVT::v4i32, &X86::VR128RegClass);
937 addRegisterClass(MVT::v2i64, &X86::VR128RegClass);
939 setOperationAction(ISD::ADD, MVT::v16i8, Legal);
940 setOperationAction(ISD::ADD, MVT::v8i16, Legal);
941 setOperationAction(ISD::ADD, MVT::v4i32, Legal);
942 setOperationAction(ISD::ADD, MVT::v2i64, Legal);
943 setOperationAction(ISD::MUL, MVT::v4i32, Custom);
944 setOperationAction(ISD::MUL, MVT::v2i64, Custom);
945 setOperationAction(ISD::UMUL_LOHI, MVT::v4i32, Custom);
946 setOperationAction(ISD::SMUL_LOHI, MVT::v4i32, Custom);
947 setOperationAction(ISD::MULHU, MVT::v8i16, Legal);
948 setOperationAction(ISD::MULHS, MVT::v8i16, Legal);
949 setOperationAction(ISD::SUB, MVT::v16i8, Legal);
950 setOperationAction(ISD::SUB, MVT::v8i16, Legal);
951 setOperationAction(ISD::SUB, MVT::v4i32, Legal);
952 setOperationAction(ISD::SUB, MVT::v2i64, Legal);
953 setOperationAction(ISD::MUL, MVT::v8i16, Legal);
954 setOperationAction(ISD::FADD, MVT::v2f64, Legal);
955 setOperationAction(ISD::FSUB, MVT::v2f64, Legal);
956 setOperationAction(ISD::FMUL, MVT::v2f64, Legal);
957 setOperationAction(ISD::FDIV, MVT::v2f64, Legal);
958 setOperationAction(ISD::FSQRT, MVT::v2f64, Legal);
959 setOperationAction(ISD::FNEG, MVT::v2f64, Custom);
960 setOperationAction(ISD::FABS, MVT::v2f64, Custom);
962 setOperationAction(ISD::SETCC, MVT::v2i64, Custom);
963 setOperationAction(ISD::SETCC, MVT::v16i8, Custom);
964 setOperationAction(ISD::SETCC, MVT::v8i16, Custom);
965 setOperationAction(ISD::SETCC, MVT::v4i32, Custom);
967 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Custom);
968 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Custom);
969 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
970 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
971 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
973 // Custom lower build_vector, vector_shuffle, and extract_vector_elt.
974 for (int i = MVT::v16i8; i != MVT::v2i64; ++i) {
975 MVT VT = (MVT::SimpleValueType)i;
976 // Do not attempt to custom lower non-power-of-2 vectors
977 if (!isPowerOf2_32(VT.getVectorNumElements()))
979 // Do not attempt to custom lower non-128-bit vectors
980 if (!VT.is128BitVector())
982 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
983 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
984 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
987 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f64, Custom);
988 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i64, Custom);
989 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Custom);
990 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Custom);
991 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f64, Custom);
992 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Custom);
994 if (Subtarget->is64Bit()) {
995 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
996 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
999 // Promote v16i8, v8i16, v4i32 load, select, and, or, xor to v2i64.
1000 for (int i = MVT::v16i8; i != MVT::v2i64; ++i) {
1001 MVT VT = (MVT::SimpleValueType)i;
1003 // Do not attempt to promote non-128-bit vectors
1004 if (!VT.is128BitVector())
1007 setOperationAction(ISD::AND, VT, Promote);
1008 AddPromotedToType (ISD::AND, VT, MVT::v2i64);
1009 setOperationAction(ISD::OR, VT, Promote);
1010 AddPromotedToType (ISD::OR, VT, MVT::v2i64);
1011 setOperationAction(ISD::XOR, VT, Promote);
1012 AddPromotedToType (ISD::XOR, VT, MVT::v2i64);
1013 setOperationAction(ISD::LOAD, VT, Promote);
1014 AddPromotedToType (ISD::LOAD, VT, MVT::v2i64);
1015 setOperationAction(ISD::SELECT, VT, Promote);
1016 AddPromotedToType (ISD::SELECT, VT, MVT::v2i64);
1019 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
1021 // Custom lower v2i64 and v2f64 selects.
1022 setOperationAction(ISD::LOAD, MVT::v2f64, Legal);
1023 setOperationAction(ISD::LOAD, MVT::v2i64, Legal);
1024 setOperationAction(ISD::SELECT, MVT::v2f64, Custom);
1025 setOperationAction(ISD::SELECT, MVT::v2i64, Custom);
1027 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal);
1028 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal);
1030 setOperationAction(ISD::UINT_TO_FP, MVT::v4i8, Custom);
1031 setOperationAction(ISD::UINT_TO_FP, MVT::v4i16, Custom);
1032 // As there is no 64-bit GPR available, we need build a special custom
1033 // sequence to convert from v2i32 to v2f32.
1034 if (!Subtarget->is64Bit())
1035 setOperationAction(ISD::UINT_TO_FP, MVT::v2f32, Custom);
1037 setOperationAction(ISD::FP_EXTEND, MVT::v2f32, Custom);
1038 setOperationAction(ISD::FP_ROUND, MVT::v2f32, Custom);
1040 setLoadExtAction(ISD::EXTLOAD, MVT::v2f32, Legal);
1042 setOperationAction(ISD::BITCAST, MVT::v2i32, Custom);
1045 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE41()) {
1046 setOperationAction(ISD::FFLOOR, MVT::f32, Legal);
1047 setOperationAction(ISD::FCEIL, MVT::f32, Legal);
1048 setOperationAction(ISD::FTRUNC, MVT::f32, Legal);
1049 setOperationAction(ISD::FRINT, MVT::f32, Legal);
1050 setOperationAction(ISD::FNEARBYINT, MVT::f32, Legal);
1051 setOperationAction(ISD::FFLOOR, MVT::f64, Legal);
1052 setOperationAction(ISD::FCEIL, MVT::f64, Legal);
1053 setOperationAction(ISD::FTRUNC, MVT::f64, Legal);
1054 setOperationAction(ISD::FRINT, MVT::f64, Legal);
1055 setOperationAction(ISD::FNEARBYINT, MVT::f64, Legal);
1057 setOperationAction(ISD::FFLOOR, MVT::v4f32, Legal);
1058 setOperationAction(ISD::FCEIL, MVT::v4f32, Legal);
1059 setOperationAction(ISD::FTRUNC, MVT::v4f32, Legal);
1060 setOperationAction(ISD::FRINT, MVT::v4f32, Legal);
1061 setOperationAction(ISD::FNEARBYINT, MVT::v4f32, Legal);
1062 setOperationAction(ISD::FFLOOR, MVT::v2f64, Legal);
1063 setOperationAction(ISD::FCEIL, MVT::v2f64, Legal);
1064 setOperationAction(ISD::FTRUNC, MVT::v2f64, Legal);
1065 setOperationAction(ISD::FRINT, MVT::v2f64, Legal);
1066 setOperationAction(ISD::FNEARBYINT, MVT::v2f64, Legal);
1068 // FIXME: Do we need to handle scalar-to-vector here?
1069 setOperationAction(ISD::MUL, MVT::v4i32, Legal);
1071 setOperationAction(ISD::VSELECT, MVT::v2f64, Custom);
1072 setOperationAction(ISD::VSELECT, MVT::v2i64, Custom);
1073 setOperationAction(ISD::VSELECT, MVT::v4i32, Custom);
1074 setOperationAction(ISD::VSELECT, MVT::v4f32, Custom);
1075 setOperationAction(ISD::VSELECT, MVT::v8i16, Custom);
1076 // There is no BLENDI for byte vectors. We don't need to custom lower
1077 // some vselects for now.
1078 setOperationAction(ISD::VSELECT, MVT::v16i8, Legal);
1080 // i8 and i16 vectors are custom , because the source register and source
1081 // source memory operand types are not the same width. f32 vectors are
1082 // custom since the immediate controlling the insert encodes additional
1084 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i8, Custom);
1085 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
1086 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
1087 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
1089 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i8, Custom);
1090 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i16, Custom);
1091 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i32, Custom);
1092 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
1094 // FIXME: these should be Legal but thats only for the case where
1095 // the index is constant. For now custom expand to deal with that.
1096 if (Subtarget->is64Bit()) {
1097 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
1098 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
1102 if (Subtarget->hasSSE2()) {
1103 setOperationAction(ISD::SRL, MVT::v8i16, Custom);
1104 setOperationAction(ISD::SRL, MVT::v16i8, Custom);
1106 setOperationAction(ISD::SHL, MVT::v8i16, Custom);
1107 setOperationAction(ISD::SHL, MVT::v16i8, Custom);
1109 setOperationAction(ISD::SRA, MVT::v8i16, Custom);
1110 setOperationAction(ISD::SRA, MVT::v16i8, Custom);
1112 // In the customized shift lowering, the legal cases in AVX2 will be
1114 setOperationAction(ISD::SRL, MVT::v2i64, Custom);
1115 setOperationAction(ISD::SRL, MVT::v4i32, Custom);
1117 setOperationAction(ISD::SHL, MVT::v2i64, Custom);
1118 setOperationAction(ISD::SHL, MVT::v4i32, Custom);
1120 setOperationAction(ISD::SRA, MVT::v4i32, Custom);
1123 if (!TM.Options.UseSoftFloat && Subtarget->hasFp256()) {
1124 addRegisterClass(MVT::v32i8, &X86::VR256RegClass);
1125 addRegisterClass(MVT::v16i16, &X86::VR256RegClass);
1126 addRegisterClass(MVT::v8i32, &X86::VR256RegClass);
1127 addRegisterClass(MVT::v8f32, &X86::VR256RegClass);
1128 addRegisterClass(MVT::v4i64, &X86::VR256RegClass);
1129 addRegisterClass(MVT::v4f64, &X86::VR256RegClass);
1131 setOperationAction(ISD::LOAD, MVT::v8f32, Legal);
1132 setOperationAction(ISD::LOAD, MVT::v4f64, Legal);
1133 setOperationAction(ISD::LOAD, MVT::v4i64, Legal);
1135 setOperationAction(ISD::FADD, MVT::v8f32, Legal);
1136 setOperationAction(ISD::FSUB, MVT::v8f32, Legal);
1137 setOperationAction(ISD::FMUL, MVT::v8f32, Legal);
1138 setOperationAction(ISD::FDIV, MVT::v8f32, Legal);
1139 setOperationAction(ISD::FSQRT, MVT::v8f32, Legal);
1140 setOperationAction(ISD::FFLOOR, MVT::v8f32, Legal);
1141 setOperationAction(ISD::FCEIL, MVT::v8f32, Legal);
1142 setOperationAction(ISD::FTRUNC, MVT::v8f32, Legal);
1143 setOperationAction(ISD::FRINT, MVT::v8f32, Legal);
1144 setOperationAction(ISD::FNEARBYINT, MVT::v8f32, Legal);
1145 setOperationAction(ISD::FNEG, MVT::v8f32, Custom);
1146 setOperationAction(ISD::FABS, MVT::v8f32, Custom);
1148 setOperationAction(ISD::FADD, MVT::v4f64, Legal);
1149 setOperationAction(ISD::FSUB, MVT::v4f64, Legal);
1150 setOperationAction(ISD::FMUL, MVT::v4f64, Legal);
1151 setOperationAction(ISD::FDIV, MVT::v4f64, Legal);
1152 setOperationAction(ISD::FSQRT, MVT::v4f64, Legal);
1153 setOperationAction(ISD::FFLOOR, MVT::v4f64, Legal);
1154 setOperationAction(ISD::FCEIL, MVT::v4f64, Legal);
1155 setOperationAction(ISD::FTRUNC, MVT::v4f64, Legal);
1156 setOperationAction(ISD::FRINT, MVT::v4f64, Legal);
1157 setOperationAction(ISD::FNEARBYINT, MVT::v4f64, Legal);
1158 setOperationAction(ISD::FNEG, MVT::v4f64, Custom);
1159 setOperationAction(ISD::FABS, MVT::v4f64, Custom);
1161 // (fp_to_int:v8i16 (v8f32 ..)) requires the result type to be promoted
1162 // even though v8i16 is a legal type.
1163 setOperationAction(ISD::FP_TO_SINT, MVT::v8i16, Promote);
1164 setOperationAction(ISD::FP_TO_UINT, MVT::v8i16, Promote);
1165 setOperationAction(ISD::FP_TO_SINT, MVT::v8i32, Legal);
1167 setOperationAction(ISD::SINT_TO_FP, MVT::v8i16, Promote);
1168 setOperationAction(ISD::SINT_TO_FP, MVT::v8i32, Legal);
1169 setOperationAction(ISD::FP_ROUND, MVT::v4f32, Legal);
1171 setOperationAction(ISD::UINT_TO_FP, MVT::v8i8, Custom);
1172 setOperationAction(ISD::UINT_TO_FP, MVT::v8i16, Custom);
1174 setLoadExtAction(ISD::EXTLOAD, MVT::v4f32, Legal);
1176 setOperationAction(ISD::SRL, MVT::v16i16, Custom);
1177 setOperationAction(ISD::SRL, MVT::v32i8, Custom);
1179 setOperationAction(ISD::SHL, MVT::v16i16, Custom);
1180 setOperationAction(ISD::SHL, MVT::v32i8, Custom);
1182 setOperationAction(ISD::SRA, MVT::v16i16, Custom);
1183 setOperationAction(ISD::SRA, MVT::v32i8, Custom);
1185 setOperationAction(ISD::SETCC, MVT::v32i8, Custom);
1186 setOperationAction(ISD::SETCC, MVT::v16i16, Custom);
1187 setOperationAction(ISD::SETCC, MVT::v8i32, Custom);
1188 setOperationAction(ISD::SETCC, MVT::v4i64, Custom);
1190 setOperationAction(ISD::SELECT, MVT::v4f64, Custom);
1191 setOperationAction(ISD::SELECT, MVT::v4i64, Custom);
1192 setOperationAction(ISD::SELECT, MVT::v8f32, Custom);
1194 setOperationAction(ISD::VSELECT, MVT::v4f64, Custom);
1195 setOperationAction(ISD::VSELECT, MVT::v4i64, Custom);
1196 setOperationAction(ISD::VSELECT, MVT::v8i32, Custom);
1197 setOperationAction(ISD::VSELECT, MVT::v8f32, Custom);
1199 setOperationAction(ISD::SIGN_EXTEND, MVT::v4i64, Custom);
1200 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i32, Custom);
1201 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i16, Custom);
1202 setOperationAction(ISD::ZERO_EXTEND, MVT::v4i64, Custom);
1203 setOperationAction(ISD::ZERO_EXTEND, MVT::v8i32, Custom);
1204 setOperationAction(ISD::ZERO_EXTEND, MVT::v16i16, Custom);
1205 setOperationAction(ISD::ANY_EXTEND, MVT::v4i64, Custom);
1206 setOperationAction(ISD::ANY_EXTEND, MVT::v8i32, Custom);
1207 setOperationAction(ISD::ANY_EXTEND, MVT::v16i16, Custom);
1208 setOperationAction(ISD::TRUNCATE, MVT::v16i8, Custom);
1209 setOperationAction(ISD::TRUNCATE, MVT::v8i16, Custom);
1210 setOperationAction(ISD::TRUNCATE, MVT::v4i32, Custom);
1212 if (Subtarget->hasFMA() || Subtarget->hasFMA4()) {
1213 setOperationAction(ISD::FMA, MVT::v8f32, Legal);
1214 setOperationAction(ISD::FMA, MVT::v4f64, Legal);
1215 setOperationAction(ISD::FMA, MVT::v4f32, Legal);
1216 setOperationAction(ISD::FMA, MVT::v2f64, Legal);
1217 setOperationAction(ISD::FMA, MVT::f32, Legal);
1218 setOperationAction(ISD::FMA, MVT::f64, Legal);
1221 if (Subtarget->hasInt256()) {
1222 setOperationAction(ISD::ADD, MVT::v4i64, Legal);
1223 setOperationAction(ISD::ADD, MVT::v8i32, Legal);
1224 setOperationAction(ISD::ADD, MVT::v16i16, Legal);
1225 setOperationAction(ISD::ADD, MVT::v32i8, Legal);
1227 setOperationAction(ISD::SUB, MVT::v4i64, Legal);
1228 setOperationAction(ISD::SUB, MVT::v8i32, Legal);
1229 setOperationAction(ISD::SUB, MVT::v16i16, Legal);
1230 setOperationAction(ISD::SUB, MVT::v32i8, Legal);
1232 setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1233 setOperationAction(ISD::MUL, MVT::v8i32, Legal);
1234 setOperationAction(ISD::MUL, MVT::v16i16, Legal);
1235 // Don't lower v32i8 because there is no 128-bit byte mul
1237 setOperationAction(ISD::UMUL_LOHI, MVT::v8i32, Custom);
1238 setOperationAction(ISD::SMUL_LOHI, MVT::v8i32, Custom);
1239 setOperationAction(ISD::MULHU, MVT::v16i16, Legal);
1240 setOperationAction(ISD::MULHS, MVT::v16i16, Legal);
1242 setOperationAction(ISD::VSELECT, MVT::v16i16, Custom);
1243 setOperationAction(ISD::VSELECT, MVT::v32i8, Legal);
1245 setOperationAction(ISD::ADD, MVT::v4i64, Custom);
1246 setOperationAction(ISD::ADD, MVT::v8i32, Custom);
1247 setOperationAction(ISD::ADD, MVT::v16i16, Custom);
1248 setOperationAction(ISD::ADD, MVT::v32i8, Custom);
1250 setOperationAction(ISD::SUB, MVT::v4i64, Custom);
1251 setOperationAction(ISD::SUB, MVT::v8i32, Custom);
1252 setOperationAction(ISD::SUB, MVT::v16i16, Custom);
1253 setOperationAction(ISD::SUB, MVT::v32i8, Custom);
1255 setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1256 setOperationAction(ISD::MUL, MVT::v8i32, Custom);
1257 setOperationAction(ISD::MUL, MVT::v16i16, Custom);
1258 // Don't lower v32i8 because there is no 128-bit byte mul
1261 // In the customized shift lowering, the legal cases in AVX2 will be
1263 setOperationAction(ISD::SRL, MVT::v4i64, Custom);
1264 setOperationAction(ISD::SRL, MVT::v8i32, Custom);
1266 setOperationAction(ISD::SHL, MVT::v4i64, Custom);
1267 setOperationAction(ISD::SHL, MVT::v8i32, Custom);
1269 setOperationAction(ISD::SRA, MVT::v8i32, Custom);
1271 // Custom lower several nodes for 256-bit types.
1272 for (int i = MVT::FIRST_VECTOR_VALUETYPE;
1273 i <= MVT::LAST_VECTOR_VALUETYPE; ++i) {
1274 MVT VT = (MVT::SimpleValueType)i;
1276 // Extract subvector is special because the value type
1277 // (result) is 128-bit but the source is 256-bit wide.
1278 if (VT.is128BitVector())
1279 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom);
1281 // Do not attempt to custom lower other non-256-bit vectors
1282 if (!VT.is256BitVector())
1285 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1286 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1287 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
1288 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1289 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom);
1290 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom);
1291 setOperationAction(ISD::CONCAT_VECTORS, VT, Custom);
1294 // Promote v32i8, v16i16, v8i32 select, and, or, xor to v4i64.
1295 for (int i = MVT::v32i8; i != MVT::v4i64; ++i) {
1296 MVT VT = (MVT::SimpleValueType)i;
1298 // Do not attempt to promote non-256-bit vectors
1299 if (!VT.is256BitVector())
1302 setOperationAction(ISD::AND, VT, Promote);
1303 AddPromotedToType (ISD::AND, VT, MVT::v4i64);
1304 setOperationAction(ISD::OR, VT, Promote);
1305 AddPromotedToType (ISD::OR, VT, MVT::v4i64);
1306 setOperationAction(ISD::XOR, VT, Promote);
1307 AddPromotedToType (ISD::XOR, VT, MVT::v4i64);
1308 setOperationAction(ISD::LOAD, VT, Promote);
1309 AddPromotedToType (ISD::LOAD, VT, MVT::v4i64);
1310 setOperationAction(ISD::SELECT, VT, Promote);
1311 AddPromotedToType (ISD::SELECT, VT, MVT::v4i64);
1315 if (!TM.Options.UseSoftFloat && Subtarget->hasAVX512()) {
1316 addRegisterClass(MVT::v16i32, &X86::VR512RegClass);
1317 addRegisterClass(MVT::v16f32, &X86::VR512RegClass);
1318 addRegisterClass(MVT::v8i64, &X86::VR512RegClass);
1319 addRegisterClass(MVT::v8f64, &X86::VR512RegClass);
1321 addRegisterClass(MVT::i1, &X86::VK1RegClass);
1322 addRegisterClass(MVT::v8i1, &X86::VK8RegClass);
1323 addRegisterClass(MVT::v16i1, &X86::VK16RegClass);
1325 setOperationAction(ISD::BR_CC, MVT::i1, Expand);
1326 setOperationAction(ISD::SETCC, MVT::i1, Custom);
1327 setOperationAction(ISD::XOR, MVT::i1, Legal);
1328 setOperationAction(ISD::OR, MVT::i1, Legal);
1329 setOperationAction(ISD::AND, MVT::i1, Legal);
1330 setLoadExtAction(ISD::EXTLOAD, MVT::v8f32, Legal);
1331 setOperationAction(ISD::LOAD, MVT::v16f32, Legal);
1332 setOperationAction(ISD::LOAD, MVT::v8f64, Legal);
1333 setOperationAction(ISD::LOAD, MVT::v8i64, Legal);
1334 setOperationAction(ISD::LOAD, MVT::v16i32, Legal);
1335 setOperationAction(ISD::LOAD, MVT::v16i1, Legal);
1337 setOperationAction(ISD::FADD, MVT::v16f32, Legal);
1338 setOperationAction(ISD::FSUB, MVT::v16f32, Legal);
1339 setOperationAction(ISD::FMUL, MVT::v16f32, Legal);
1340 setOperationAction(ISD::FDIV, MVT::v16f32, Legal);
1341 setOperationAction(ISD::FSQRT, MVT::v16f32, Legal);
1342 setOperationAction(ISD::FNEG, MVT::v16f32, Custom);
1344 setOperationAction(ISD::FADD, MVT::v8f64, Legal);
1345 setOperationAction(ISD::FSUB, MVT::v8f64, Legal);
1346 setOperationAction(ISD::FMUL, MVT::v8f64, Legal);
1347 setOperationAction(ISD::FDIV, MVT::v8f64, Legal);
1348 setOperationAction(ISD::FSQRT, MVT::v8f64, Legal);
1349 setOperationAction(ISD::FNEG, MVT::v8f64, Custom);
1350 setOperationAction(ISD::FMA, MVT::v8f64, Legal);
1351 setOperationAction(ISD::FMA, MVT::v16f32, Legal);
1353 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Legal);
1354 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Legal);
1355 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Legal);
1356 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Legal);
1357 if (Subtarget->is64Bit()) {
1358 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Legal);
1359 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Legal);
1360 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Legal);
1361 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Legal);
1363 setOperationAction(ISD::FP_TO_SINT, MVT::v16i32, Legal);
1364 setOperationAction(ISD::FP_TO_UINT, MVT::v16i32, Legal);
1365 setOperationAction(ISD::FP_TO_UINT, MVT::v8i32, Legal);
1366 setOperationAction(ISD::FP_TO_UINT, MVT::v4i32, Legal);
1367 setOperationAction(ISD::SINT_TO_FP, MVT::v16i32, Legal);
1368 setOperationAction(ISD::UINT_TO_FP, MVT::v16i32, Legal);
1369 setOperationAction(ISD::UINT_TO_FP, MVT::v8i32, Legal);
1370 setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Legal);
1371 setOperationAction(ISD::FP_ROUND, MVT::v8f32, Legal);
1372 setOperationAction(ISD::FP_EXTEND, MVT::v8f32, Legal);
1374 setOperationAction(ISD::TRUNCATE, MVT::i1, Custom);
1375 setOperationAction(ISD::TRUNCATE, MVT::v16i8, Custom);
1376 setOperationAction(ISD::TRUNCATE, MVT::v8i32, Custom);
1377 setOperationAction(ISD::TRUNCATE, MVT::v8i1, Custom);
1378 setOperationAction(ISD::TRUNCATE, MVT::v16i1, Custom);
1379 setOperationAction(ISD::TRUNCATE, MVT::v16i16, Custom);
1380 setOperationAction(ISD::ZERO_EXTEND, MVT::v16i32, Custom);
1381 setOperationAction(ISD::ZERO_EXTEND, MVT::v8i64, Custom);
1382 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i32, Custom);
1383 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i64, Custom);
1384 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i8, Custom);
1385 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i16, Custom);
1386 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i16, Custom);
1388 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8f64, Custom);
1389 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i64, Custom);
1390 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16f32, Custom);
1391 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i32, Custom);
1392 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i1, Custom);
1393 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i1, Legal);
1395 setOperationAction(ISD::SETCC, MVT::v16i1, Custom);
1396 setOperationAction(ISD::SETCC, MVT::v8i1, Custom);
1398 setOperationAction(ISD::MUL, MVT::v8i64, Custom);
1400 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i1, Custom);
1401 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i1, Custom);
1402 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i1, Custom);
1403 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i1, Custom);
1404 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i1, Custom);
1405 setOperationAction(ISD::BUILD_VECTOR, MVT::v16i1, Custom);
1406 setOperationAction(ISD::SELECT, MVT::v8f64, Custom);
1407 setOperationAction(ISD::SELECT, MVT::v8i64, Custom);
1408 setOperationAction(ISD::SELECT, MVT::v16f32, Custom);
1410 setOperationAction(ISD::ADD, MVT::v8i64, Legal);
1411 setOperationAction(ISD::ADD, MVT::v16i32, Legal);
1413 setOperationAction(ISD::SUB, MVT::v8i64, Legal);
1414 setOperationAction(ISD::SUB, MVT::v16i32, Legal);
1416 setOperationAction(ISD::MUL, MVT::v16i32, Legal);
1418 setOperationAction(ISD::SRL, MVT::v8i64, Custom);
1419 setOperationAction(ISD::SRL, MVT::v16i32, Custom);
1421 setOperationAction(ISD::SHL, MVT::v8i64, Custom);
1422 setOperationAction(ISD::SHL, MVT::v16i32, Custom);
1424 setOperationAction(ISD::SRA, MVT::v8i64, Custom);
1425 setOperationAction(ISD::SRA, MVT::v16i32, Custom);
1427 setOperationAction(ISD::AND, MVT::v8i64, Legal);
1428 setOperationAction(ISD::OR, MVT::v8i64, Legal);
1429 setOperationAction(ISD::XOR, MVT::v8i64, Legal);
1430 setOperationAction(ISD::AND, MVT::v16i32, Legal);
1431 setOperationAction(ISD::OR, MVT::v16i32, Legal);
1432 setOperationAction(ISD::XOR, MVT::v16i32, Legal);
1434 // Custom lower several nodes.
1435 for (int i = MVT::FIRST_VECTOR_VALUETYPE;
1436 i <= MVT::LAST_VECTOR_VALUETYPE; ++i) {
1437 MVT VT = (MVT::SimpleValueType)i;
1439 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
1440 // Extract subvector is special because the value type
1441 // (result) is 256/128-bit but the source is 512-bit wide.
1442 if (VT.is128BitVector() || VT.is256BitVector())
1443 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom);
1445 if (VT.getVectorElementType() == MVT::i1)
1446 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Legal);
1448 // Do not attempt to custom lower other non-512-bit vectors
1449 if (!VT.is512BitVector())
1452 if ( EltSize >= 32) {
1453 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1454 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
1455 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1456 setOperationAction(ISD::VSELECT, VT, Legal);
1457 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1458 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom);
1459 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom);
1462 for (int i = MVT::v32i8; i != MVT::v8i64; ++i) {
1463 MVT VT = (MVT::SimpleValueType)i;
1465 // Do not attempt to promote non-256-bit vectors
1466 if (!VT.is512BitVector())
1469 setOperationAction(ISD::SELECT, VT, Promote);
1470 AddPromotedToType (ISD::SELECT, VT, MVT::v8i64);
1474 // SIGN_EXTEND_INREGs are evaluated by the extend type. Handle the expansion
1475 // of this type with custom code.
1476 for (int VT = MVT::FIRST_VECTOR_VALUETYPE;
1477 VT != MVT::LAST_VECTOR_VALUETYPE; VT++) {
1478 setOperationAction(ISD::SIGN_EXTEND_INREG, (MVT::SimpleValueType)VT,
1482 // We want to custom lower some of our intrinsics.
1483 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
1484 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::Other, Custom);
1485 setOperationAction(ISD::INTRINSIC_VOID, MVT::Other, Custom);
1486 if (!Subtarget->is64Bit())
1487 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::i64, Custom);
1489 // Only custom-lower 64-bit SADDO and friends on 64-bit because we don't
1490 // handle type legalization for these operations here.
1492 // FIXME: We really should do custom legalization for addition and
1493 // subtraction on x86-32 once PR3203 is fixed. We really can't do much better
1494 // than generic legalization for 64-bit multiplication-with-overflow, though.
1495 for (unsigned i = 0, e = 3+Subtarget->is64Bit(); i != e; ++i) {
1496 // Add/Sub/Mul with overflow operations are custom lowered.
1498 setOperationAction(ISD::SADDO, VT, Custom);
1499 setOperationAction(ISD::UADDO, VT, Custom);
1500 setOperationAction(ISD::SSUBO, VT, Custom);
1501 setOperationAction(ISD::USUBO, VT, Custom);
1502 setOperationAction(ISD::SMULO, VT, Custom);
1503 setOperationAction(ISD::UMULO, VT, Custom);
1506 // There are no 8-bit 3-address imul/mul instructions
1507 setOperationAction(ISD::SMULO, MVT::i8, Expand);
1508 setOperationAction(ISD::UMULO, MVT::i8, Expand);
1510 if (!Subtarget->is64Bit()) {
1511 // These libcalls are not available in 32-bit.
1512 setLibcallName(RTLIB::SHL_I128, nullptr);
1513 setLibcallName(RTLIB::SRL_I128, nullptr);
1514 setLibcallName(RTLIB::SRA_I128, nullptr);
1517 // Combine sin / cos into one node or libcall if possible.
1518 if (Subtarget->hasSinCos()) {
1519 setLibcallName(RTLIB::SINCOS_F32, "sincosf");
1520 setLibcallName(RTLIB::SINCOS_F64, "sincos");
1521 if (Subtarget->isTargetDarwin()) {
1522 // For MacOSX, we don't want to the normal expansion of a libcall to
1523 // sincos. We want to issue a libcall to __sincos_stret to avoid memory
1525 setOperationAction(ISD::FSINCOS, MVT::f64, Custom);
1526 setOperationAction(ISD::FSINCOS, MVT::f32, Custom);
1530 if (Subtarget->isTargetWin64()) {
1531 setOperationAction(ISD::SDIV, MVT::i128, Custom);
1532 setOperationAction(ISD::UDIV, MVT::i128, Custom);
1533 setOperationAction(ISD::SREM, MVT::i128, Custom);
1534 setOperationAction(ISD::UREM, MVT::i128, Custom);
1535 setOperationAction(ISD::SDIVREM, MVT::i128, Custom);
1536 setOperationAction(ISD::UDIVREM, MVT::i128, Custom);
1539 // We have target-specific dag combine patterns for the following nodes:
1540 setTargetDAGCombine(ISD::VECTOR_SHUFFLE);
1541 setTargetDAGCombine(ISD::EXTRACT_VECTOR_ELT);
1542 setTargetDAGCombine(ISD::VSELECT);
1543 setTargetDAGCombine(ISD::SELECT);
1544 setTargetDAGCombine(ISD::SHL);
1545 setTargetDAGCombine(ISD::SRA);
1546 setTargetDAGCombine(ISD::SRL);
1547 setTargetDAGCombine(ISD::OR);
1548 setTargetDAGCombine(ISD::AND);
1549 setTargetDAGCombine(ISD::ADD);
1550 setTargetDAGCombine(ISD::FADD);
1551 setTargetDAGCombine(ISD::FSUB);
1552 setTargetDAGCombine(ISD::FMA);
1553 setTargetDAGCombine(ISD::SUB);
1554 setTargetDAGCombine(ISD::LOAD);
1555 setTargetDAGCombine(ISD::STORE);
1556 setTargetDAGCombine(ISD::ZERO_EXTEND);
1557 setTargetDAGCombine(ISD::ANY_EXTEND);
1558 setTargetDAGCombine(ISD::SIGN_EXTEND);
1559 setTargetDAGCombine(ISD::SIGN_EXTEND_INREG);
1560 setTargetDAGCombine(ISD::TRUNCATE);
1561 setTargetDAGCombine(ISD::SINT_TO_FP);
1562 setTargetDAGCombine(ISD::SETCC);
1563 setTargetDAGCombine(ISD::INTRINSIC_WO_CHAIN);
1564 if (Subtarget->is64Bit())
1565 setTargetDAGCombine(ISD::MUL);
1566 setTargetDAGCombine(ISD::XOR);
1568 computeRegisterProperties();
1570 // On Darwin, -Os means optimize for size without hurting performance,
1571 // do not reduce the limit.
1572 MaxStoresPerMemset = 16; // For @llvm.memset -> sequence of stores
1573 MaxStoresPerMemsetOptSize = Subtarget->isTargetDarwin() ? 16 : 8;
1574 MaxStoresPerMemcpy = 8; // For @llvm.memcpy -> sequence of stores
1575 MaxStoresPerMemcpyOptSize = Subtarget->isTargetDarwin() ? 8 : 4;
1576 MaxStoresPerMemmove = 8; // For @llvm.memmove -> sequence of stores
1577 MaxStoresPerMemmoveOptSize = Subtarget->isTargetDarwin() ? 8 : 4;
1578 setPrefLoopAlignment(4); // 2^4 bytes.
1580 // Predictable cmov don't hurt on atom because it's in-order.
1581 PredictableSelectIsExpensive = !Subtarget->isAtom();
1583 setPrefFunctionAlignment(4); // 2^4 bytes.
1586 EVT X86TargetLowering::getSetCCResultType(LLVMContext &, EVT VT) const {
1588 return Subtarget->hasAVX512() ? MVT::i1: MVT::i8;
1590 if (Subtarget->hasAVX512())
1591 switch(VT.getVectorNumElements()) {
1592 case 8: return MVT::v8i1;
1593 case 16: return MVT::v16i1;
1596 return VT.changeVectorElementTypeToInteger();
1599 /// getMaxByValAlign - Helper for getByValTypeAlignment to determine
1600 /// the desired ByVal argument alignment.
1601 static void getMaxByValAlign(Type *Ty, unsigned &MaxAlign) {
1604 if (VectorType *VTy = dyn_cast<VectorType>(Ty)) {
1605 if (VTy->getBitWidth() == 128)
1607 } else if (ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
1608 unsigned EltAlign = 0;
1609 getMaxByValAlign(ATy->getElementType(), EltAlign);
1610 if (EltAlign > MaxAlign)
1611 MaxAlign = EltAlign;
1612 } else if (StructType *STy = dyn_cast<StructType>(Ty)) {
1613 for (unsigned i = 0, e = STy->getNumElements(); i != e; ++i) {
1614 unsigned EltAlign = 0;
1615 getMaxByValAlign(STy->getElementType(i), EltAlign);
1616 if (EltAlign > MaxAlign)
1617 MaxAlign = EltAlign;
1624 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
1625 /// function arguments in the caller parameter area. For X86, aggregates
1626 /// that contain SSE vectors are placed at 16-byte boundaries while the rest
1627 /// are at 4-byte boundaries.
1628 unsigned X86TargetLowering::getByValTypeAlignment(Type *Ty) const {
1629 if (Subtarget->is64Bit()) {
1630 // Max of 8 and alignment of type.
1631 unsigned TyAlign = TD->getABITypeAlignment(Ty);
1638 if (Subtarget->hasSSE1())
1639 getMaxByValAlign(Ty, Align);
1643 /// getOptimalMemOpType - Returns the target specific optimal type for load
1644 /// and store operations as a result of memset, memcpy, and memmove
1645 /// lowering. If DstAlign is zero that means it's safe to destination
1646 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
1647 /// means there isn't a need to check it against alignment requirement,
1648 /// probably because the source does not need to be loaded. If 'IsMemset' is
1649 /// true, that means it's expanding a memset. If 'ZeroMemset' is true, that
1650 /// means it's a memset of zero. 'MemcpyStrSrc' indicates whether the memcpy
1651 /// source is constant so it does not need to be loaded.
1652 /// It returns EVT::Other if the type should be determined using generic
1653 /// target-independent logic.
1655 X86TargetLowering::getOptimalMemOpType(uint64_t Size,
1656 unsigned DstAlign, unsigned SrcAlign,
1657 bool IsMemset, bool ZeroMemset,
1659 MachineFunction &MF) const {
1660 const Function *F = MF.getFunction();
1661 if ((!IsMemset || ZeroMemset) &&
1662 !F->getAttributes().hasAttribute(AttributeSet::FunctionIndex,
1663 Attribute::NoImplicitFloat)) {
1665 (Subtarget->isUnalignedMemAccessFast() ||
1666 ((DstAlign == 0 || DstAlign >= 16) &&
1667 (SrcAlign == 0 || SrcAlign >= 16)))) {
1669 if (Subtarget->hasInt256())
1671 if (Subtarget->hasFp256())
1674 if (Subtarget->hasSSE2())
1676 if (Subtarget->hasSSE1())
1678 } else if (!MemcpyStrSrc && Size >= 8 &&
1679 !Subtarget->is64Bit() &&
1680 Subtarget->hasSSE2()) {
1681 // Do not use f64 to lower memcpy if source is string constant. It's
1682 // better to use i32 to avoid the loads.
1686 if (Subtarget->is64Bit() && Size >= 8)
1691 bool X86TargetLowering::isSafeMemOpType(MVT VT) const {
1693 return X86ScalarSSEf32;
1694 else if (VT == MVT::f64)
1695 return X86ScalarSSEf64;
1700 X86TargetLowering::allowsUnalignedMemoryAccesses(EVT VT,
1704 *Fast = Subtarget->isUnalignedMemAccessFast();
1708 /// getJumpTableEncoding - Return the entry encoding for a jump table in the
1709 /// current function. The returned value is a member of the
1710 /// MachineJumpTableInfo::JTEntryKind enum.
1711 unsigned X86TargetLowering::getJumpTableEncoding() const {
1712 // In GOT pic mode, each entry in the jump table is emitted as a @GOTOFF
1714 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1715 Subtarget->isPICStyleGOT())
1716 return MachineJumpTableInfo::EK_Custom32;
1718 // Otherwise, use the normal jump table encoding heuristics.
1719 return TargetLowering::getJumpTableEncoding();
1723 X86TargetLowering::LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI,
1724 const MachineBasicBlock *MBB,
1725 unsigned uid,MCContext &Ctx) const{
1726 assert(getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1727 Subtarget->isPICStyleGOT());
1728 // In 32-bit ELF systems, our jump table entries are formed with @GOTOFF
1730 return MCSymbolRefExpr::Create(MBB->getSymbol(),
1731 MCSymbolRefExpr::VK_GOTOFF, Ctx);
1734 /// getPICJumpTableRelocaBase - Returns relocation base for the given PIC
1736 SDValue X86TargetLowering::getPICJumpTableRelocBase(SDValue Table,
1737 SelectionDAG &DAG) const {
1738 if (!Subtarget->is64Bit())
1739 // This doesn't have SDLoc associated with it, but is not really the
1740 // same as a Register.
1741 return DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), getPointerTy());
1745 /// getPICJumpTableRelocBaseExpr - This returns the relocation base for the
1746 /// given PIC jumptable, the same as getPICJumpTableRelocBase, but as an
1748 const MCExpr *X86TargetLowering::
1749 getPICJumpTableRelocBaseExpr(const MachineFunction *MF, unsigned JTI,
1750 MCContext &Ctx) const {
1751 // X86-64 uses RIP relative addressing based on the jump table label.
1752 if (Subtarget->isPICStyleRIPRel())
1753 return TargetLowering::getPICJumpTableRelocBaseExpr(MF, JTI, Ctx);
1755 // Otherwise, the reference is relative to the PIC base.
1756 return MCSymbolRefExpr::Create(MF->getPICBaseSymbol(), Ctx);
1759 // FIXME: Why this routine is here? Move to RegInfo!
1760 std::pair<const TargetRegisterClass*, uint8_t>
1761 X86TargetLowering::findRepresentativeClass(MVT VT) const{
1762 const TargetRegisterClass *RRC = nullptr;
1764 switch (VT.SimpleTy) {
1766 return TargetLowering::findRepresentativeClass(VT);
1767 case MVT::i8: case MVT::i16: case MVT::i32: case MVT::i64:
1768 RRC = Subtarget->is64Bit() ?
1769 (const TargetRegisterClass*)&X86::GR64RegClass :
1770 (const TargetRegisterClass*)&X86::GR32RegClass;
1773 RRC = &X86::VR64RegClass;
1775 case MVT::f32: case MVT::f64:
1776 case MVT::v16i8: case MVT::v8i16: case MVT::v4i32: case MVT::v2i64:
1777 case MVT::v4f32: case MVT::v2f64:
1778 case MVT::v32i8: case MVT::v8i32: case MVT::v4i64: case MVT::v8f32:
1780 RRC = &X86::VR128RegClass;
1783 return std::make_pair(RRC, Cost);
1786 bool X86TargetLowering::getStackCookieLocation(unsigned &AddressSpace,
1787 unsigned &Offset) const {
1788 if (!Subtarget->isTargetLinux())
1791 if (Subtarget->is64Bit()) {
1792 // %fs:0x28, unless we're using a Kernel code model, in which case it's %gs:
1794 if (getTargetMachine().getCodeModel() == CodeModel::Kernel)
1806 bool X86TargetLowering::isNoopAddrSpaceCast(unsigned SrcAS,
1807 unsigned DestAS) const {
1808 assert(SrcAS != DestAS && "Expected different address spaces!");
1810 return SrcAS < 256 && DestAS < 256;
1813 //===----------------------------------------------------------------------===//
1814 // Return Value Calling Convention Implementation
1815 //===----------------------------------------------------------------------===//
1817 #include "X86GenCallingConv.inc"
1820 X86TargetLowering::CanLowerReturn(CallingConv::ID CallConv,
1821 MachineFunction &MF, bool isVarArg,
1822 const SmallVectorImpl<ISD::OutputArg> &Outs,
1823 LLVMContext &Context) const {
1824 SmallVector<CCValAssign, 16> RVLocs;
1825 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(),
1827 return CCInfo.CheckReturn(Outs, RetCC_X86);
1830 const MCPhysReg *X86TargetLowering::getScratchRegisters(CallingConv::ID) const {
1831 static const MCPhysReg ScratchRegs[] = { X86::R11, 0 };
1836 X86TargetLowering::LowerReturn(SDValue Chain,
1837 CallingConv::ID CallConv, bool isVarArg,
1838 const SmallVectorImpl<ISD::OutputArg> &Outs,
1839 const SmallVectorImpl<SDValue> &OutVals,
1840 SDLoc dl, SelectionDAG &DAG) const {
1841 MachineFunction &MF = DAG.getMachineFunction();
1842 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1844 SmallVector<CCValAssign, 16> RVLocs;
1845 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(),
1846 RVLocs, *DAG.getContext());
1847 CCInfo.AnalyzeReturn(Outs, RetCC_X86);
1850 SmallVector<SDValue, 6> RetOps;
1851 RetOps.push_back(Chain); // Operand #0 = Chain (updated below)
1852 // Operand #1 = Bytes To Pop
1853 RetOps.push_back(DAG.getTargetConstant(FuncInfo->getBytesToPopOnReturn(),
1856 // Copy the result values into the output registers.
1857 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1858 CCValAssign &VA = RVLocs[i];
1859 assert(VA.isRegLoc() && "Can only return in registers!");
1860 SDValue ValToCopy = OutVals[i];
1861 EVT ValVT = ValToCopy.getValueType();
1863 // Promote values to the appropriate types
1864 if (VA.getLocInfo() == CCValAssign::SExt)
1865 ValToCopy = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), ValToCopy);
1866 else if (VA.getLocInfo() == CCValAssign::ZExt)
1867 ValToCopy = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), ValToCopy);
1868 else if (VA.getLocInfo() == CCValAssign::AExt)
1869 ValToCopy = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), ValToCopy);
1870 else if (VA.getLocInfo() == CCValAssign::BCvt)
1871 ValToCopy = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), ValToCopy);
1873 assert(VA.getLocInfo() != CCValAssign::FPExt &&
1874 "Unexpected FP-extend for return value.");
1876 // If this is x86-64, and we disabled SSE, we can't return FP values,
1877 // or SSE or MMX vectors.
1878 if ((ValVT == MVT::f32 || ValVT == MVT::f64 ||
1879 VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) &&
1880 (Subtarget->is64Bit() && !Subtarget->hasSSE1())) {
1881 report_fatal_error("SSE register return with SSE disabled");
1883 // Likewise we can't return F64 values with SSE1 only. gcc does so, but
1884 // llvm-gcc has never done it right and no one has noticed, so this
1885 // should be OK for now.
1886 if (ValVT == MVT::f64 &&
1887 (Subtarget->is64Bit() && !Subtarget->hasSSE2()))
1888 report_fatal_error("SSE2 register return with SSE2 disabled");
1890 // Returns in ST0/ST1 are handled specially: these are pushed as operands to
1891 // the RET instruction and handled by the FP Stackifier.
1892 if (VA.getLocReg() == X86::ST0 ||
1893 VA.getLocReg() == X86::ST1) {
1894 // If this is a copy from an xmm register to ST(0), use an FPExtend to
1895 // change the value to the FP stack register class.
1896 if (isScalarFPTypeInSSEReg(VA.getValVT()))
1897 ValToCopy = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f80, ValToCopy);
1898 RetOps.push_back(ValToCopy);
1899 // Don't emit a copytoreg.
1903 // 64-bit vector (MMX) values are returned in XMM0 / XMM1 except for v1i64
1904 // which is returned in RAX / RDX.
1905 if (Subtarget->is64Bit()) {
1906 if (ValVT == MVT::x86mmx) {
1907 if (VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) {
1908 ValToCopy = DAG.getNode(ISD::BITCAST, dl, MVT::i64, ValToCopy);
1909 ValToCopy = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
1911 // If we don't have SSE2 available, convert to v4f32 so the generated
1912 // register is legal.
1913 if (!Subtarget->hasSSE2())
1914 ValToCopy = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32,ValToCopy);
1919 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), ValToCopy, Flag);
1920 Flag = Chain.getValue(1);
1921 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
1924 // The x86-64 ABIs require that for returning structs by value we copy
1925 // the sret argument into %rax/%eax (depending on ABI) for the return.
1926 // Win32 requires us to put the sret argument to %eax as well.
1927 // We saved the argument into a virtual register in the entry block,
1928 // so now we copy the value out and into %rax/%eax.
1929 if (DAG.getMachineFunction().getFunction()->hasStructRetAttr() &&
1930 (Subtarget->is64Bit() || Subtarget->isTargetKnownWindowsMSVC())) {
1931 MachineFunction &MF = DAG.getMachineFunction();
1932 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1933 unsigned Reg = FuncInfo->getSRetReturnReg();
1935 "SRetReturnReg should have been set in LowerFormalArguments().");
1936 SDValue Val = DAG.getCopyFromReg(Chain, dl, Reg, getPointerTy());
1939 = (Subtarget->is64Bit() && !Subtarget->isTarget64BitILP32()) ?
1940 X86::RAX : X86::EAX;
1941 Chain = DAG.getCopyToReg(Chain, dl, RetValReg, Val, Flag);
1942 Flag = Chain.getValue(1);
1944 // RAX/EAX now acts like a return value.
1945 RetOps.push_back(DAG.getRegister(RetValReg, getPointerTy()));
1948 RetOps[0] = Chain; // Update chain.
1950 // Add the flag if we have it.
1952 RetOps.push_back(Flag);
1954 return DAG.getNode(X86ISD::RET_FLAG, dl, MVT::Other, RetOps);
1957 bool X86TargetLowering::isUsedByReturnOnly(SDNode *N, SDValue &Chain) const {
1958 if (N->getNumValues() != 1)
1960 if (!N->hasNUsesOfValue(1, 0))
1963 SDValue TCChain = Chain;
1964 SDNode *Copy = *N->use_begin();
1965 if (Copy->getOpcode() == ISD::CopyToReg) {
1966 // If the copy has a glue operand, we conservatively assume it isn't safe to
1967 // perform a tail call.
1968 if (Copy->getOperand(Copy->getNumOperands()-1).getValueType() == MVT::Glue)
1970 TCChain = Copy->getOperand(0);
1971 } else if (Copy->getOpcode() != ISD::FP_EXTEND)
1974 bool HasRet = false;
1975 for (SDNode::use_iterator UI = Copy->use_begin(), UE = Copy->use_end();
1977 if (UI->getOpcode() != X86ISD::RET_FLAG)
1990 X86TargetLowering::getTypeForExtArgOrReturn(MVT VT,
1991 ISD::NodeType ExtendKind) const {
1993 // TODO: Is this also valid on 32-bit?
1994 if (Subtarget->is64Bit() && VT == MVT::i1 && ExtendKind == ISD::ZERO_EXTEND)
1995 ReturnMVT = MVT::i8;
1997 ReturnMVT = MVT::i32;
1999 MVT MinVT = getRegisterType(ReturnMVT);
2000 return VT.bitsLT(MinVT) ? MinVT : VT;
2003 /// LowerCallResult - Lower the result values of a call into the
2004 /// appropriate copies out of appropriate physical registers.
2007 X86TargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
2008 CallingConv::ID CallConv, bool isVarArg,
2009 const SmallVectorImpl<ISD::InputArg> &Ins,
2010 SDLoc dl, SelectionDAG &DAG,
2011 SmallVectorImpl<SDValue> &InVals) const {
2013 // Assign locations to each value returned by this call.
2014 SmallVector<CCValAssign, 16> RVLocs;
2015 bool Is64Bit = Subtarget->is64Bit();
2016 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
2017 getTargetMachine(), RVLocs, *DAG.getContext());
2018 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
2020 // Copy all of the result registers out of their specified physreg.
2021 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
2022 CCValAssign &VA = RVLocs[i];
2023 EVT CopyVT = VA.getValVT();
2025 // If this is x86-64, and we disabled SSE, we can't return FP values
2026 if ((CopyVT == MVT::f32 || CopyVT == MVT::f64) &&
2027 ((Is64Bit || Ins[i].Flags.isInReg()) && !Subtarget->hasSSE1())) {
2028 report_fatal_error("SSE register return with SSE disabled");
2033 // If this is a call to a function that returns an fp value on the floating
2034 // point stack, we must guarantee the value is popped from the stack, so
2035 // a CopyFromReg is not good enough - the copy instruction may be eliminated
2036 // if the return value is not used. We use the FpPOP_RETVAL instruction
2038 if (VA.getLocReg() == X86::ST0 || VA.getLocReg() == X86::ST1) {
2039 // If we prefer to use the value in xmm registers, copy it out as f80 and
2040 // use a truncate to move it from fp stack reg to xmm reg.
2041 if (isScalarFPTypeInSSEReg(VA.getValVT())) CopyVT = MVT::f80;
2042 SDValue Ops[] = { Chain, InFlag };
2043 Chain = SDValue(DAG.getMachineNode(X86::FpPOP_RETVAL, dl, CopyVT,
2044 MVT::Other, MVT::Glue, Ops), 1);
2045 Val = Chain.getValue(0);
2047 // Round the f80 to the right size, which also moves it to the appropriate
2049 if (CopyVT != VA.getValVT())
2050 Val = DAG.getNode(ISD::FP_ROUND, dl, VA.getValVT(), Val,
2051 // This truncation won't change the value.
2052 DAG.getIntPtrConstant(1));
2054 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(),
2055 CopyVT, InFlag).getValue(1);
2056 Val = Chain.getValue(0);
2058 InFlag = Chain.getValue(2);
2059 InVals.push_back(Val);
2065 //===----------------------------------------------------------------------===//
2066 // C & StdCall & Fast Calling Convention implementation
2067 //===----------------------------------------------------------------------===//
2068 // StdCall calling convention seems to be standard for many Windows' API
2069 // routines and around. It differs from C calling convention just a little:
2070 // callee should clean up the stack, not caller. Symbols should be also
2071 // decorated in some fancy way :) It doesn't support any vector arguments.
2072 // For info on fast calling convention see Fast Calling Convention (tail call)
2073 // implementation LowerX86_32FastCCCallTo.
2075 /// CallIsStructReturn - Determines whether a call uses struct return
2077 enum StructReturnType {
2082 static StructReturnType
2083 callIsStructReturn(const SmallVectorImpl<ISD::OutputArg> &Outs) {
2085 return NotStructReturn;
2087 const ISD::ArgFlagsTy &Flags = Outs[0].Flags;
2088 if (!Flags.isSRet())
2089 return NotStructReturn;
2090 if (Flags.isInReg())
2091 return RegStructReturn;
2092 return StackStructReturn;
2095 /// ArgsAreStructReturn - Determines whether a function uses struct
2096 /// return semantics.
2097 static StructReturnType
2098 argsAreStructReturn(const SmallVectorImpl<ISD::InputArg> &Ins) {
2100 return NotStructReturn;
2102 const ISD::ArgFlagsTy &Flags = Ins[0].Flags;
2103 if (!Flags.isSRet())
2104 return NotStructReturn;
2105 if (Flags.isInReg())
2106 return RegStructReturn;
2107 return StackStructReturn;
2110 /// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified
2111 /// by "Src" to address "Dst" with size and alignment information specified by
2112 /// the specific parameter attribute. The copy will be passed as a byval
2113 /// function parameter.
2115 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
2116 ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
2118 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32);
2120 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
2121 /*isVolatile*/false, /*AlwaysInline=*/true,
2122 MachinePointerInfo(), MachinePointerInfo());
2125 /// IsTailCallConvention - Return true if the calling convention is one that
2126 /// supports tail call optimization.
2127 static bool IsTailCallConvention(CallingConv::ID CC) {
2128 return (CC == CallingConv::Fast || CC == CallingConv::GHC ||
2129 CC == CallingConv::HiPE);
2132 /// \brief Return true if the calling convention is a C calling convention.
2133 static bool IsCCallConvention(CallingConv::ID CC) {
2134 return (CC == CallingConv::C || CC == CallingConv::X86_64_Win64 ||
2135 CC == CallingConv::X86_64_SysV);
2138 bool X86TargetLowering::mayBeEmittedAsTailCall(CallInst *CI) const {
2139 if (!CI->isTailCall() || getTargetMachine().Options.DisableTailCalls)
2143 CallingConv::ID CalleeCC = CS.getCallingConv();
2144 if (!IsTailCallConvention(CalleeCC) && !IsCCallConvention(CalleeCC))
2150 /// FuncIsMadeTailCallSafe - Return true if the function is being made into
2151 /// a tailcall target by changing its ABI.
2152 static bool FuncIsMadeTailCallSafe(CallingConv::ID CC,
2153 bool GuaranteedTailCallOpt) {
2154 return GuaranteedTailCallOpt && IsTailCallConvention(CC);
2158 X86TargetLowering::LowerMemArgument(SDValue Chain,
2159 CallingConv::ID CallConv,
2160 const SmallVectorImpl<ISD::InputArg> &Ins,
2161 SDLoc dl, SelectionDAG &DAG,
2162 const CCValAssign &VA,
2163 MachineFrameInfo *MFI,
2165 // Create the nodes corresponding to a load from this parameter slot.
2166 ISD::ArgFlagsTy Flags = Ins[i].Flags;
2167 bool AlwaysUseMutable = FuncIsMadeTailCallSafe(CallConv,
2168 getTargetMachine().Options.GuaranteedTailCallOpt);
2169 bool isImmutable = !AlwaysUseMutable && !Flags.isByVal();
2172 // If value is passed by pointer we have address passed instead of the value
2174 if (VA.getLocInfo() == CCValAssign::Indirect)
2175 ValVT = VA.getLocVT();
2177 ValVT = VA.getValVT();
2179 // FIXME: For now, all byval parameter objects are marked mutable. This can be
2180 // changed with more analysis.
2181 // In case of tail call optimization mark all arguments mutable. Since they
2182 // could be overwritten by lowering of arguments in case of a tail call.
2183 if (Flags.isByVal()) {
2184 unsigned Bytes = Flags.getByValSize();
2185 if (Bytes == 0) Bytes = 1; // Don't create zero-sized stack objects.
2186 int FI = MFI->CreateFixedObject(Bytes, VA.getLocMemOffset(), isImmutable);
2187 return DAG.getFrameIndex(FI, getPointerTy());
2189 int FI = MFI->CreateFixedObject(ValVT.getSizeInBits()/8,
2190 VA.getLocMemOffset(), isImmutable);
2191 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
2192 return DAG.getLoad(ValVT, dl, Chain, FIN,
2193 MachinePointerInfo::getFixedStack(FI),
2194 false, false, false, 0);
2199 X86TargetLowering::LowerFormalArguments(SDValue Chain,
2200 CallingConv::ID CallConv,
2202 const SmallVectorImpl<ISD::InputArg> &Ins,
2205 SmallVectorImpl<SDValue> &InVals)
2207 MachineFunction &MF = DAG.getMachineFunction();
2208 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
2210 const Function* Fn = MF.getFunction();
2211 if (Fn->hasExternalLinkage() &&
2212 Subtarget->isTargetCygMing() &&
2213 Fn->getName() == "main")
2214 FuncInfo->setForceFramePointer(true);
2216 MachineFrameInfo *MFI = MF.getFrameInfo();
2217 bool Is64Bit = Subtarget->is64Bit();
2218 bool IsWin64 = Subtarget->isCallingConvWin64(CallConv);
2220 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
2221 "Var args not supported with calling convention fastcc, ghc or hipe");
2223 // Assign locations to all of the incoming arguments.
2224 SmallVector<CCValAssign, 16> ArgLocs;
2225 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(),
2226 ArgLocs, *DAG.getContext());
2228 // Allocate shadow area for Win64
2230 CCInfo.AllocateStack(32, 8);
2232 CCInfo.AnalyzeFormalArguments(Ins, CC_X86);
2234 unsigned LastVal = ~0U;
2236 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2237 CCValAssign &VA = ArgLocs[i];
2238 // TODO: If an arg is passed in two places (e.g. reg and stack), skip later
2240 assert(VA.getValNo() != LastVal &&
2241 "Don't support value assigned to multiple locs yet");
2243 LastVal = VA.getValNo();
2245 if (VA.isRegLoc()) {
2246 EVT RegVT = VA.getLocVT();
2247 const TargetRegisterClass *RC;
2248 if (RegVT == MVT::i32)
2249 RC = &X86::GR32RegClass;
2250 else if (Is64Bit && RegVT == MVT::i64)
2251 RC = &X86::GR64RegClass;
2252 else if (RegVT == MVT::f32)
2253 RC = &X86::FR32RegClass;
2254 else if (RegVT == MVT::f64)
2255 RC = &X86::FR64RegClass;
2256 else if (RegVT.is512BitVector())
2257 RC = &X86::VR512RegClass;
2258 else if (RegVT.is256BitVector())
2259 RC = &X86::VR256RegClass;
2260 else if (RegVT.is128BitVector())
2261 RC = &X86::VR128RegClass;
2262 else if (RegVT == MVT::x86mmx)
2263 RC = &X86::VR64RegClass;
2264 else if (RegVT == MVT::i1)
2265 RC = &X86::VK1RegClass;
2266 else if (RegVT == MVT::v8i1)
2267 RC = &X86::VK8RegClass;
2268 else if (RegVT == MVT::v16i1)
2269 RC = &X86::VK16RegClass;
2271 llvm_unreachable("Unknown argument type!");
2273 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
2274 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
2276 // If this is an 8 or 16-bit value, it is really passed promoted to 32
2277 // bits. Insert an assert[sz]ext to capture this, then truncate to the
2279 if (VA.getLocInfo() == CCValAssign::SExt)
2280 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
2281 DAG.getValueType(VA.getValVT()));
2282 else if (VA.getLocInfo() == CCValAssign::ZExt)
2283 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
2284 DAG.getValueType(VA.getValVT()));
2285 else if (VA.getLocInfo() == CCValAssign::BCvt)
2286 ArgValue = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), ArgValue);
2288 if (VA.isExtInLoc()) {
2289 // Handle MMX values passed in XMM regs.
2290 if (RegVT.isVector())
2291 ArgValue = DAG.getNode(X86ISD::MOVDQ2Q, dl, VA.getValVT(), ArgValue);
2293 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
2296 assert(VA.isMemLoc());
2297 ArgValue = LowerMemArgument(Chain, CallConv, Ins, dl, DAG, VA, MFI, i);
2300 // If value is passed via pointer - do a load.
2301 if (VA.getLocInfo() == CCValAssign::Indirect)
2302 ArgValue = DAG.getLoad(VA.getValVT(), dl, Chain, ArgValue,
2303 MachinePointerInfo(), false, false, false, 0);
2305 InVals.push_back(ArgValue);
2308 if (Subtarget->is64Bit() || Subtarget->isTargetKnownWindowsMSVC()) {
2309 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2310 // The x86-64 ABIs require that for returning structs by value we copy
2311 // the sret argument into %rax/%eax (depending on ABI) for the return.
2312 // Win32 requires us to put the sret argument to %eax as well.
2313 // Save the argument into a virtual register so that we can access it
2314 // from the return points.
2315 if (Ins[i].Flags.isSRet()) {
2316 unsigned Reg = FuncInfo->getSRetReturnReg();
2318 MVT PtrTy = getPointerTy();
2319 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(PtrTy));
2320 FuncInfo->setSRetReturnReg(Reg);
2322 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, InVals[i]);
2323 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain);
2329 unsigned StackSize = CCInfo.getNextStackOffset();
2330 // Align stack specially for tail calls.
2331 if (FuncIsMadeTailCallSafe(CallConv,
2332 MF.getTarget().Options.GuaranteedTailCallOpt))
2333 StackSize = GetAlignedArgumentStackSize(StackSize, DAG);
2335 // If the function takes variable number of arguments, make a frame index for
2336 // the start of the first vararg value... for expansion of llvm.va_start.
2338 if (Is64Bit || (CallConv != CallingConv::X86_FastCall &&
2339 CallConv != CallingConv::X86_ThisCall)) {
2340 FuncInfo->setVarArgsFrameIndex(MFI->CreateFixedObject(1, StackSize,true));
2343 unsigned TotalNumIntRegs = 0, TotalNumXMMRegs = 0;
2345 // FIXME: We should really autogenerate these arrays
2346 static const MCPhysReg GPR64ArgRegsWin64[] = {
2347 X86::RCX, X86::RDX, X86::R8, X86::R9
2349 static const MCPhysReg GPR64ArgRegs64Bit[] = {
2350 X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9
2352 static const MCPhysReg XMMArgRegs64Bit[] = {
2353 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
2354 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
2356 const MCPhysReg *GPR64ArgRegs;
2357 unsigned NumXMMRegs = 0;
2360 // The XMM registers which might contain var arg parameters are shadowed
2361 // in their paired GPR. So we only need to save the GPR to their home
2363 TotalNumIntRegs = 4;
2364 GPR64ArgRegs = GPR64ArgRegsWin64;
2366 TotalNumIntRegs = 6; TotalNumXMMRegs = 8;
2367 GPR64ArgRegs = GPR64ArgRegs64Bit;
2369 NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs64Bit,
2372 unsigned NumIntRegs = CCInfo.getFirstUnallocated(GPR64ArgRegs,
2375 bool NoImplicitFloatOps = Fn->getAttributes().
2376 hasAttribute(AttributeSet::FunctionIndex, Attribute::NoImplicitFloat);
2377 assert(!(NumXMMRegs && !Subtarget->hasSSE1()) &&
2378 "SSE register cannot be used when SSE is disabled!");
2379 assert(!(NumXMMRegs && MF.getTarget().Options.UseSoftFloat &&
2380 NoImplicitFloatOps) &&
2381 "SSE register cannot be used when SSE is disabled!");
2382 if (MF.getTarget().Options.UseSoftFloat || NoImplicitFloatOps ||
2383 !Subtarget->hasSSE1())
2384 // Kernel mode asks for SSE to be disabled, so don't push them
2386 TotalNumXMMRegs = 0;
2389 const TargetFrameLowering &TFI = *getTargetMachine().getFrameLowering();
2390 // Get to the caller-allocated home save location. Add 8 to account
2391 // for the return address.
2392 int HomeOffset = TFI.getOffsetOfLocalArea() + 8;
2393 FuncInfo->setRegSaveFrameIndex(
2394 MFI->CreateFixedObject(1, NumIntRegs * 8 + HomeOffset, false));
2395 // Fixup to set vararg frame on shadow area (4 x i64).
2397 FuncInfo->setVarArgsFrameIndex(FuncInfo->getRegSaveFrameIndex());
2399 // For X86-64, if there are vararg parameters that are passed via
2400 // registers, then we must store them to their spots on the stack so
2401 // they may be loaded by deferencing the result of va_next.
2402 FuncInfo->setVarArgsGPOffset(NumIntRegs * 8);
2403 FuncInfo->setVarArgsFPOffset(TotalNumIntRegs * 8 + NumXMMRegs * 16);
2404 FuncInfo->setRegSaveFrameIndex(
2405 MFI->CreateStackObject(TotalNumIntRegs * 8 + TotalNumXMMRegs * 16, 16,
2409 // Store the integer parameter registers.
2410 SmallVector<SDValue, 8> MemOps;
2411 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
2413 unsigned Offset = FuncInfo->getVarArgsGPOffset();
2414 for (; NumIntRegs != TotalNumIntRegs; ++NumIntRegs) {
2415 SDValue FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), RSFIN,
2416 DAG.getIntPtrConstant(Offset));
2417 unsigned VReg = MF.addLiveIn(GPR64ArgRegs[NumIntRegs],
2418 &X86::GR64RegClass);
2419 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64);
2421 DAG.getStore(Val.getValue(1), dl, Val, FIN,
2422 MachinePointerInfo::getFixedStack(
2423 FuncInfo->getRegSaveFrameIndex(), Offset),
2425 MemOps.push_back(Store);
2429 if (TotalNumXMMRegs != 0 && NumXMMRegs != TotalNumXMMRegs) {
2430 // Now store the XMM (fp + vector) parameter registers.
2431 SmallVector<SDValue, 11> SaveXMMOps;
2432 SaveXMMOps.push_back(Chain);
2434 unsigned AL = MF.addLiveIn(X86::AL, &X86::GR8RegClass);
2435 SDValue ALVal = DAG.getCopyFromReg(DAG.getEntryNode(), dl, AL, MVT::i8);
2436 SaveXMMOps.push_back(ALVal);
2438 SaveXMMOps.push_back(DAG.getIntPtrConstant(
2439 FuncInfo->getRegSaveFrameIndex()));
2440 SaveXMMOps.push_back(DAG.getIntPtrConstant(
2441 FuncInfo->getVarArgsFPOffset()));
2443 for (; NumXMMRegs != TotalNumXMMRegs; ++NumXMMRegs) {
2444 unsigned VReg = MF.addLiveIn(XMMArgRegs64Bit[NumXMMRegs],
2445 &X86::VR128RegClass);
2446 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::v4f32);
2447 SaveXMMOps.push_back(Val);
2449 MemOps.push_back(DAG.getNode(X86ISD::VASTART_SAVE_XMM_REGS, dl,
2450 MVT::Other, SaveXMMOps));
2453 if (!MemOps.empty())
2454 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps);
2458 // Some CCs need callee pop.
2459 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg,
2460 MF.getTarget().Options.GuaranteedTailCallOpt)) {
2461 FuncInfo->setBytesToPopOnReturn(StackSize); // Callee pops everything.
2463 FuncInfo->setBytesToPopOnReturn(0); // Callee pops nothing.
2464 // If this is an sret function, the return should pop the hidden pointer.
2465 if (!Is64Bit && !IsTailCallConvention(CallConv) &&
2466 !Subtarget->getTargetTriple().isOSMSVCRT() &&
2467 argsAreStructReturn(Ins) == StackStructReturn)
2468 FuncInfo->setBytesToPopOnReturn(4);
2472 // RegSaveFrameIndex is X86-64 only.
2473 FuncInfo->setRegSaveFrameIndex(0xAAAAAAA);
2474 if (CallConv == CallingConv::X86_FastCall ||
2475 CallConv == CallingConv::X86_ThisCall)
2476 // fastcc functions can't have varargs.
2477 FuncInfo->setVarArgsFrameIndex(0xAAAAAAA);
2480 FuncInfo->setArgumentStackSize(StackSize);
2486 X86TargetLowering::LowerMemOpCallTo(SDValue Chain,
2487 SDValue StackPtr, SDValue Arg,
2488 SDLoc dl, SelectionDAG &DAG,
2489 const CCValAssign &VA,
2490 ISD::ArgFlagsTy Flags) const {
2491 unsigned LocMemOffset = VA.getLocMemOffset();
2492 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
2493 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
2494 if (Flags.isByVal())
2495 return CreateCopyOfByValArgument(Arg, PtrOff, Chain, Flags, DAG, dl);
2497 return DAG.getStore(Chain, dl, Arg, PtrOff,
2498 MachinePointerInfo::getStack(LocMemOffset),
2502 /// EmitTailCallLoadRetAddr - Emit a load of return address if tail call
2503 /// optimization is performed and it is required.
2505 X86TargetLowering::EmitTailCallLoadRetAddr(SelectionDAG &DAG,
2506 SDValue &OutRetAddr, SDValue Chain,
2507 bool IsTailCall, bool Is64Bit,
2508 int FPDiff, SDLoc dl) const {
2509 // Adjust the Return address stack slot.
2510 EVT VT = getPointerTy();
2511 OutRetAddr = getReturnAddressFrameIndex(DAG);
2513 // Load the "old" Return address.
2514 OutRetAddr = DAG.getLoad(VT, dl, Chain, OutRetAddr, MachinePointerInfo(),
2515 false, false, false, 0);
2516 return SDValue(OutRetAddr.getNode(), 1);
2519 /// EmitTailCallStoreRetAddr - Emit a store of the return address if tail call
2520 /// optimization is performed and it is required (FPDiff!=0).
2521 static SDValue EmitTailCallStoreRetAddr(SelectionDAG &DAG, MachineFunction &MF,
2522 SDValue Chain, SDValue RetAddrFrIdx,
2523 EVT PtrVT, unsigned SlotSize,
2524 int FPDiff, SDLoc dl) {
2525 // Store the return address to the appropriate stack slot.
2526 if (!FPDiff) return Chain;
2527 // Calculate the new stack slot for the return address.
2528 int NewReturnAddrFI =
2529 MF.getFrameInfo()->CreateFixedObject(SlotSize, (int64_t)FPDiff - SlotSize,
2531 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewReturnAddrFI, PtrVT);
2532 Chain = DAG.getStore(Chain, dl, RetAddrFrIdx, NewRetAddrFrIdx,
2533 MachinePointerInfo::getFixedStack(NewReturnAddrFI),
2539 X86TargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
2540 SmallVectorImpl<SDValue> &InVals) const {
2541 SelectionDAG &DAG = CLI.DAG;
2543 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
2544 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
2545 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
2546 SDValue Chain = CLI.Chain;
2547 SDValue Callee = CLI.Callee;
2548 CallingConv::ID CallConv = CLI.CallConv;
2549 bool &isTailCall = CLI.IsTailCall;
2550 bool isVarArg = CLI.IsVarArg;
2552 MachineFunction &MF = DAG.getMachineFunction();
2553 bool Is64Bit = Subtarget->is64Bit();
2554 bool IsWin64 = Subtarget->isCallingConvWin64(CallConv);
2555 StructReturnType SR = callIsStructReturn(Outs);
2556 bool IsSibcall = false;
2558 if (MF.getTarget().Options.DisableTailCalls)
2561 bool IsMustTail = CLI.CS && CLI.CS->isMustTailCall();
2563 // Force this to be a tail call. The verifier rules are enough to ensure
2564 // that we can lower this successfully without moving the return address
2567 } else if (isTailCall) {
2568 // Check if it's really possible to do a tail call.
2569 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv,
2570 isVarArg, SR != NotStructReturn,
2571 MF.getFunction()->hasStructRetAttr(), CLI.RetTy,
2572 Outs, OutVals, Ins, DAG);
2574 // Sibcalls are automatically detected tailcalls which do not require
2576 if (!MF.getTarget().Options.GuaranteedTailCallOpt && isTailCall)
2583 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
2584 "Var args not supported with calling convention fastcc, ghc or hipe");
2586 // Analyze operands of the call, assigning locations to each operand.
2587 SmallVector<CCValAssign, 16> ArgLocs;
2588 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(),
2589 ArgLocs, *DAG.getContext());
2591 // Allocate shadow area for Win64
2593 CCInfo.AllocateStack(32, 8);
2595 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
2597 // Get a count of how many bytes are to be pushed on the stack.
2598 unsigned NumBytes = CCInfo.getNextStackOffset();
2600 // This is a sibcall. The memory operands are available in caller's
2601 // own caller's stack.
2603 else if (getTargetMachine().Options.GuaranteedTailCallOpt &&
2604 IsTailCallConvention(CallConv))
2605 NumBytes = GetAlignedArgumentStackSize(NumBytes, DAG);
2608 if (isTailCall && !IsSibcall && !IsMustTail) {
2609 // Lower arguments at fp - stackoffset + fpdiff.
2610 X86MachineFunctionInfo *X86Info = MF.getInfo<X86MachineFunctionInfo>();
2611 unsigned NumBytesCallerPushed = X86Info->getBytesToPopOnReturn();
2613 FPDiff = NumBytesCallerPushed - NumBytes;
2615 // Set the delta of movement of the returnaddr stackslot.
2616 // But only set if delta is greater than previous delta.
2617 if (FPDiff < X86Info->getTCReturnAddrDelta())
2618 X86Info->setTCReturnAddrDelta(FPDiff);
2621 unsigned NumBytesToPush = NumBytes;
2622 unsigned NumBytesToPop = NumBytes;
2624 // If we have an inalloca argument, all stack space has already been allocated
2625 // for us and be right at the top of the stack. We don't support multiple
2626 // arguments passed in memory when using inalloca.
2627 if (!Outs.empty() && Outs.back().Flags.isInAlloca()) {
2629 assert(ArgLocs.back().getLocMemOffset() == 0 &&
2630 "an inalloca argument must be the only memory argument");
2634 Chain = DAG.getCALLSEQ_START(
2635 Chain, DAG.getIntPtrConstant(NumBytesToPush, true), dl);
2637 SDValue RetAddrFrIdx;
2638 // Load return address for tail calls.
2639 if (isTailCall && FPDiff)
2640 Chain = EmitTailCallLoadRetAddr(DAG, RetAddrFrIdx, Chain, isTailCall,
2641 Is64Bit, FPDiff, dl);
2643 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
2644 SmallVector<SDValue, 8> MemOpChains;
2647 // Walk the register/memloc assignments, inserting copies/loads. In the case
2648 // of tail call optimization arguments are handle later.
2649 const X86RegisterInfo *RegInfo =
2650 static_cast<const X86RegisterInfo*>(getTargetMachine().getRegisterInfo());
2651 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2652 // Skip inalloca arguments, they have already been written.
2653 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2654 if (Flags.isInAlloca())
2657 CCValAssign &VA = ArgLocs[i];
2658 EVT RegVT = VA.getLocVT();
2659 SDValue Arg = OutVals[i];
2660 bool isByVal = Flags.isByVal();
2662 // Promote the value if needed.
2663 switch (VA.getLocInfo()) {
2664 default: llvm_unreachable("Unknown loc info!");
2665 case CCValAssign::Full: break;
2666 case CCValAssign::SExt:
2667 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, RegVT, Arg);
2669 case CCValAssign::ZExt:
2670 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, RegVT, Arg);
2672 case CCValAssign::AExt:
2673 if (RegVT.is128BitVector()) {
2674 // Special case: passing MMX values in XMM registers.
2675 Arg = DAG.getNode(ISD::BITCAST, dl, MVT::i64, Arg);
2676 Arg = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, Arg);
2677 Arg = getMOVL(DAG, dl, MVT::v2i64, DAG.getUNDEF(MVT::v2i64), Arg);
2679 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, RegVT, Arg);
2681 case CCValAssign::BCvt:
2682 Arg = DAG.getNode(ISD::BITCAST, dl, RegVT, Arg);
2684 case CCValAssign::Indirect: {
2685 // Store the argument.
2686 SDValue SpillSlot = DAG.CreateStackTemporary(VA.getValVT());
2687 int FI = cast<FrameIndexSDNode>(SpillSlot)->getIndex();
2688 Chain = DAG.getStore(Chain, dl, Arg, SpillSlot,
2689 MachinePointerInfo::getFixedStack(FI),
2696 if (VA.isRegLoc()) {
2697 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
2698 if (isVarArg && IsWin64) {
2699 // Win64 ABI requires argument XMM reg to be copied to the corresponding
2700 // shadow reg if callee is a varargs function.
2701 unsigned ShadowReg = 0;
2702 switch (VA.getLocReg()) {
2703 case X86::XMM0: ShadowReg = X86::RCX; break;
2704 case X86::XMM1: ShadowReg = X86::RDX; break;
2705 case X86::XMM2: ShadowReg = X86::R8; break;
2706 case X86::XMM3: ShadowReg = X86::R9; break;
2709 RegsToPass.push_back(std::make_pair(ShadowReg, Arg));
2711 } else if (!IsSibcall && (!isTailCall || isByVal)) {
2712 assert(VA.isMemLoc());
2713 if (!StackPtr.getNode())
2714 StackPtr = DAG.getCopyFromReg(Chain, dl, RegInfo->getStackRegister(),
2716 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Arg,
2717 dl, DAG, VA, Flags));
2721 if (!MemOpChains.empty())
2722 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains);
2724 if (Subtarget->isPICStyleGOT()) {
2725 // ELF / PIC requires GOT in the EBX register before function calls via PLT
2728 RegsToPass.push_back(std::make_pair(unsigned(X86::EBX),
2729 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), getPointerTy())));
2731 // If we are tail calling and generating PIC/GOT style code load the
2732 // address of the callee into ECX. The value in ecx is used as target of
2733 // the tail jump. This is done to circumvent the ebx/callee-saved problem
2734 // for tail calls on PIC/GOT architectures. Normally we would just put the
2735 // address of GOT into ebx and then call target@PLT. But for tail calls
2736 // ebx would be restored (since ebx is callee saved) before jumping to the
2739 // Note: The actual moving to ECX is done further down.
2740 GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee);
2741 if (G && !G->getGlobal()->hasHiddenVisibility() &&
2742 !G->getGlobal()->hasProtectedVisibility())
2743 Callee = LowerGlobalAddress(Callee, DAG);
2744 else if (isa<ExternalSymbolSDNode>(Callee))
2745 Callee = LowerExternalSymbol(Callee, DAG);
2749 if (Is64Bit && isVarArg && !IsWin64) {
2750 // From AMD64 ABI document:
2751 // For calls that may call functions that use varargs or stdargs
2752 // (prototype-less calls or calls to functions containing ellipsis (...) in
2753 // the declaration) %al is used as hidden argument to specify the number
2754 // of SSE registers used. The contents of %al do not need to match exactly
2755 // the number of registers, but must be an ubound on the number of SSE
2756 // registers used and is in the range 0 - 8 inclusive.
2758 // Count the number of XMM registers allocated.
2759 static const MCPhysReg XMMArgRegs[] = {
2760 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
2761 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
2763 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs, 8);
2764 assert((Subtarget->hasSSE1() || !NumXMMRegs)
2765 && "SSE registers cannot be used when SSE is disabled");
2767 RegsToPass.push_back(std::make_pair(unsigned(X86::AL),
2768 DAG.getConstant(NumXMMRegs, MVT::i8)));
2771 // For tail calls lower the arguments to the 'real' stack slots. Sibcalls
2772 // don't need this because the eligibility check rejects calls that require
2773 // shuffling arguments passed in memory.
2774 if (!IsSibcall && isTailCall) {
2775 // Force all the incoming stack arguments to be loaded from the stack
2776 // before any new outgoing arguments are stored to the stack, because the
2777 // outgoing stack slots may alias the incoming argument stack slots, and
2778 // the alias isn't otherwise explicit. This is slightly more conservative
2779 // than necessary, because it means that each store effectively depends
2780 // on every argument instead of just those arguments it would clobber.
2781 SDValue ArgChain = DAG.getStackArgumentTokenFactor(Chain);
2783 SmallVector<SDValue, 8> MemOpChains2;
2786 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2787 CCValAssign &VA = ArgLocs[i];
2790 assert(VA.isMemLoc());
2791 SDValue Arg = OutVals[i];
2792 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2793 // Skip inalloca arguments. They don't require any work.
2794 if (Flags.isInAlloca())
2796 // Create frame index.
2797 int32_t Offset = VA.getLocMemOffset()+FPDiff;
2798 uint32_t OpSize = (VA.getLocVT().getSizeInBits()+7)/8;
2799 FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true);
2800 FIN = DAG.getFrameIndex(FI, getPointerTy());
2802 if (Flags.isByVal()) {
2803 // Copy relative to framepointer.
2804 SDValue Source = DAG.getIntPtrConstant(VA.getLocMemOffset());
2805 if (!StackPtr.getNode())
2806 StackPtr = DAG.getCopyFromReg(Chain, dl,
2807 RegInfo->getStackRegister(),
2809 Source = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, Source);
2811 MemOpChains2.push_back(CreateCopyOfByValArgument(Source, FIN,
2815 // Store relative to framepointer.
2816 MemOpChains2.push_back(
2817 DAG.getStore(ArgChain, dl, Arg, FIN,
2818 MachinePointerInfo::getFixedStack(FI),
2823 if (!MemOpChains2.empty())
2824 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains2);
2826 // Store the return address to the appropriate stack slot.
2827 Chain = EmitTailCallStoreRetAddr(DAG, MF, Chain, RetAddrFrIdx,
2828 getPointerTy(), RegInfo->getSlotSize(),
2832 // Build a sequence of copy-to-reg nodes chained together with token chain
2833 // and flag operands which copy the outgoing args into registers.
2835 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
2836 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
2837 RegsToPass[i].second, InFlag);
2838 InFlag = Chain.getValue(1);
2841 if (getTargetMachine().getCodeModel() == CodeModel::Large) {
2842 assert(Is64Bit && "Large code model is only legal in 64-bit mode.");
2843 // In the 64-bit large code model, we have to make all calls
2844 // through a register, since the call instruction's 32-bit
2845 // pc-relative offset may not be large enough to hold the whole
2847 } else if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
2848 // If the callee is a GlobalAddress node (quite common, every direct call
2849 // is) turn it into a TargetGlobalAddress node so that legalize doesn't hack
2852 // We should use extra load for direct calls to dllimported functions in
2854 const GlobalValue *GV = G->getGlobal();
2855 if (!GV->hasDLLImportStorageClass()) {
2856 unsigned char OpFlags = 0;
2857 bool ExtraLoad = false;
2858 unsigned WrapperKind = ISD::DELETED_NODE;
2860 // On ELF targets, in both X86-64 and X86-32 mode, direct calls to
2861 // external symbols most go through the PLT in PIC mode. If the symbol
2862 // has hidden or protected visibility, or if it is static or local, then
2863 // we don't need to use the PLT - we can directly call it.
2864 if (Subtarget->isTargetELF() &&
2865 getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
2866 GV->hasDefaultVisibility() && !GV->hasLocalLinkage()) {
2867 OpFlags = X86II::MO_PLT;
2868 } else if (Subtarget->isPICStyleStubAny() &&
2869 (GV->isDeclaration() || GV->isWeakForLinker()) &&
2870 (!Subtarget->getTargetTriple().isMacOSX() ||
2871 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
2872 // PC-relative references to external symbols should go through $stub,
2873 // unless we're building with the leopard linker or later, which
2874 // automatically synthesizes these stubs.
2875 OpFlags = X86II::MO_DARWIN_STUB;
2876 } else if (Subtarget->isPICStyleRIPRel() &&
2877 isa<Function>(GV) &&
2878 cast<Function>(GV)->getAttributes().
2879 hasAttribute(AttributeSet::FunctionIndex,
2880 Attribute::NonLazyBind)) {
2881 // If the function is marked as non-lazy, generate an indirect call
2882 // which loads from the GOT directly. This avoids runtime overhead
2883 // at the cost of eager binding (and one extra byte of encoding).
2884 OpFlags = X86II::MO_GOTPCREL;
2885 WrapperKind = X86ISD::WrapperRIP;
2889 Callee = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(),
2890 G->getOffset(), OpFlags);
2892 // Add a wrapper if needed.
2893 if (WrapperKind != ISD::DELETED_NODE)
2894 Callee = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Callee);
2895 // Add extra indirection if needed.
2897 Callee = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Callee,
2898 MachinePointerInfo::getGOT(),
2899 false, false, false, 0);
2901 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
2902 unsigned char OpFlags = 0;
2904 // On ELF targets, in either X86-64 or X86-32 mode, direct calls to
2905 // external symbols should go through the PLT.
2906 if (Subtarget->isTargetELF() &&
2907 getTargetMachine().getRelocationModel() == Reloc::PIC_) {
2908 OpFlags = X86II::MO_PLT;
2909 } else if (Subtarget->isPICStyleStubAny() &&
2910 (!Subtarget->getTargetTriple().isMacOSX() ||
2911 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
2912 // PC-relative references to external symbols should go through $stub,
2913 // unless we're building with the leopard linker or later, which
2914 // automatically synthesizes these stubs.
2915 OpFlags = X86II::MO_DARWIN_STUB;
2918 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy(),
2922 // Returns a chain & a flag for retval copy to use.
2923 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
2924 SmallVector<SDValue, 8> Ops;
2926 if (!IsSibcall && isTailCall) {
2927 Chain = DAG.getCALLSEQ_END(Chain,
2928 DAG.getIntPtrConstant(NumBytesToPop, true),
2929 DAG.getIntPtrConstant(0, true), InFlag, dl);
2930 InFlag = Chain.getValue(1);
2933 Ops.push_back(Chain);
2934 Ops.push_back(Callee);
2937 Ops.push_back(DAG.getConstant(FPDiff, MVT::i32));
2939 // Add argument registers to the end of the list so that they are known live
2941 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
2942 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
2943 RegsToPass[i].second.getValueType()));
2945 // Add a register mask operand representing the call-preserved registers.
2946 const TargetRegisterInfo *TRI = getTargetMachine().getRegisterInfo();
2947 const uint32_t *Mask = TRI->getCallPreservedMask(CallConv);
2948 assert(Mask && "Missing call preserved mask for calling convention");
2949 Ops.push_back(DAG.getRegisterMask(Mask));
2951 if (InFlag.getNode())
2952 Ops.push_back(InFlag);
2956 //// If this is the first return lowered for this function, add the regs
2957 //// to the liveout set for the function.
2958 // This isn't right, although it's probably harmless on x86; liveouts
2959 // should be computed from returns not tail calls. Consider a void
2960 // function making a tail call to a function returning int.
2961 return DAG.getNode(X86ISD::TC_RETURN, dl, NodeTys, Ops);
2964 Chain = DAG.getNode(X86ISD::CALL, dl, NodeTys, Ops);
2965 InFlag = Chain.getValue(1);
2967 // Create the CALLSEQ_END node.
2968 unsigned NumBytesForCalleeToPop;
2969 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg,
2970 getTargetMachine().Options.GuaranteedTailCallOpt))
2971 NumBytesForCalleeToPop = NumBytes; // Callee pops everything
2972 else if (!Is64Bit && !IsTailCallConvention(CallConv) &&
2973 !Subtarget->getTargetTriple().isOSMSVCRT() &&
2974 SR == StackStructReturn)
2975 // If this is a call to a struct-return function, the callee
2976 // pops the hidden struct pointer, so we have to push it back.
2977 // This is common for Darwin/X86, Linux & Mingw32 targets.
2978 // For MSVC Win32 targets, the caller pops the hidden struct pointer.
2979 NumBytesForCalleeToPop = 4;
2981 NumBytesForCalleeToPop = 0; // Callee pops nothing.
2983 // Returns a flag for retval copy to use.
2985 Chain = DAG.getCALLSEQ_END(Chain,
2986 DAG.getIntPtrConstant(NumBytesToPop, true),
2987 DAG.getIntPtrConstant(NumBytesForCalleeToPop,
2990 InFlag = Chain.getValue(1);
2993 // Handle result values, copying them out of physregs into vregs that we
2995 return LowerCallResult(Chain, InFlag, CallConv, isVarArg,
2996 Ins, dl, DAG, InVals);
2999 //===----------------------------------------------------------------------===//
3000 // Fast Calling Convention (tail call) implementation
3001 //===----------------------------------------------------------------------===//
3003 // Like std call, callee cleans arguments, convention except that ECX is
3004 // reserved for storing the tail called function address. Only 2 registers are
3005 // free for argument passing (inreg). Tail call optimization is performed
3007 // * tailcallopt is enabled
3008 // * caller/callee are fastcc
3009 // On X86_64 architecture with GOT-style position independent code only local
3010 // (within module) calls are supported at the moment.
3011 // To keep the stack aligned according to platform abi the function
3012 // GetAlignedArgumentStackSize ensures that argument delta is always multiples
3013 // of stack alignment. (Dynamic linkers need this - darwin's dyld for example)
3014 // If a tail called function callee has more arguments than the caller the
3015 // caller needs to make sure that there is room to move the RETADDR to. This is
3016 // achieved by reserving an area the size of the argument delta right after the
3017 // original REtADDR, but before the saved framepointer or the spilled registers
3018 // e.g. caller(arg1, arg2) calls callee(arg1, arg2,arg3,arg4)
3030 /// GetAlignedArgumentStackSize - Make the stack size align e.g 16n + 12 aligned
3031 /// for a 16 byte align requirement.
3033 X86TargetLowering::GetAlignedArgumentStackSize(unsigned StackSize,
3034 SelectionDAG& DAG) const {
3035 MachineFunction &MF = DAG.getMachineFunction();
3036 const TargetMachine &TM = MF.getTarget();
3037 const X86RegisterInfo *RegInfo =
3038 static_cast<const X86RegisterInfo*>(TM.getRegisterInfo());
3039 const TargetFrameLowering &TFI = *TM.getFrameLowering();
3040 unsigned StackAlignment = TFI.getStackAlignment();
3041 uint64_t AlignMask = StackAlignment - 1;
3042 int64_t Offset = StackSize;
3043 unsigned SlotSize = RegInfo->getSlotSize();
3044 if ( (Offset & AlignMask) <= (StackAlignment - SlotSize) ) {
3045 // Number smaller than 12 so just add the difference.
3046 Offset += ((StackAlignment - SlotSize) - (Offset & AlignMask));
3048 // Mask out lower bits, add stackalignment once plus the 12 bytes.
3049 Offset = ((~AlignMask) & Offset) + StackAlignment +
3050 (StackAlignment-SlotSize);
3055 /// MatchingStackOffset - Return true if the given stack call argument is
3056 /// already available in the same position (relatively) of the caller's
3057 /// incoming argument stack.
3059 bool MatchingStackOffset(SDValue Arg, unsigned Offset, ISD::ArgFlagsTy Flags,
3060 MachineFrameInfo *MFI, const MachineRegisterInfo *MRI,
3061 const X86InstrInfo *TII) {
3062 unsigned Bytes = Arg.getValueType().getSizeInBits() / 8;
3064 if (Arg.getOpcode() == ISD::CopyFromReg) {
3065 unsigned VR = cast<RegisterSDNode>(Arg.getOperand(1))->getReg();
3066 if (!TargetRegisterInfo::isVirtualRegister(VR))
3068 MachineInstr *Def = MRI->getVRegDef(VR);
3071 if (!Flags.isByVal()) {
3072 if (!TII->isLoadFromStackSlot(Def, FI))
3075 unsigned Opcode = Def->getOpcode();
3076 if ((Opcode == X86::LEA32r || Opcode == X86::LEA64r) &&
3077 Def->getOperand(1).isFI()) {
3078 FI = Def->getOperand(1).getIndex();
3079 Bytes = Flags.getByValSize();
3083 } else if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Arg)) {
3084 if (Flags.isByVal())
3085 // ByVal argument is passed in as a pointer but it's now being
3086 // dereferenced. e.g.
3087 // define @foo(%struct.X* %A) {
3088 // tail call @bar(%struct.X* byval %A)
3091 SDValue Ptr = Ld->getBasePtr();
3092 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr);
3095 FI = FINode->getIndex();
3096 } else if (Arg.getOpcode() == ISD::FrameIndex && Flags.isByVal()) {
3097 FrameIndexSDNode *FINode = cast<FrameIndexSDNode>(Arg);
3098 FI = FINode->getIndex();
3099 Bytes = Flags.getByValSize();
3103 assert(FI != INT_MAX);
3104 if (!MFI->isFixedObjectIndex(FI))
3106 return Offset == MFI->getObjectOffset(FI) && Bytes == MFI->getObjectSize(FI);
3109 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
3110 /// for tail call optimization. Targets which want to do tail call
3111 /// optimization should implement this function.
3113 X86TargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
3114 CallingConv::ID CalleeCC,
3116 bool isCalleeStructRet,
3117 bool isCallerStructRet,
3119 const SmallVectorImpl<ISD::OutputArg> &Outs,
3120 const SmallVectorImpl<SDValue> &OutVals,
3121 const SmallVectorImpl<ISD::InputArg> &Ins,
3122 SelectionDAG &DAG) const {
3123 if (!IsTailCallConvention(CalleeCC) && !IsCCallConvention(CalleeCC))
3126 // If -tailcallopt is specified, make fastcc functions tail-callable.
3127 const MachineFunction &MF = DAG.getMachineFunction();
3128 const Function *CallerF = MF.getFunction();
3130 // If the function return type is x86_fp80 and the callee return type is not,
3131 // then the FP_EXTEND of the call result is not a nop. It's not safe to
3132 // perform a tailcall optimization here.
3133 if (CallerF->getReturnType()->isX86_FP80Ty() && !RetTy->isX86_FP80Ty())
3136 CallingConv::ID CallerCC = CallerF->getCallingConv();
3137 bool CCMatch = CallerCC == CalleeCC;
3138 bool IsCalleeWin64 = Subtarget->isCallingConvWin64(CalleeCC);
3139 bool IsCallerWin64 = Subtarget->isCallingConvWin64(CallerCC);
3141 if (getTargetMachine().Options.GuaranteedTailCallOpt) {
3142 if (IsTailCallConvention(CalleeCC) && CCMatch)
3147 // Look for obvious safe cases to perform tail call optimization that do not
3148 // require ABI changes. This is what gcc calls sibcall.
3150 // Can't do sibcall if stack needs to be dynamically re-aligned. PEI needs to
3151 // emit a special epilogue.
3152 const X86RegisterInfo *RegInfo =
3153 static_cast<const X86RegisterInfo*>(getTargetMachine().getRegisterInfo());
3154 if (RegInfo->needsStackRealignment(MF))
3157 // Also avoid sibcall optimization if either caller or callee uses struct
3158 // return semantics.
3159 if (isCalleeStructRet || isCallerStructRet)
3162 // An stdcall/thiscall caller is expected to clean up its arguments; the
3163 // callee isn't going to do that.
3164 // FIXME: this is more restrictive than needed. We could produce a tailcall
3165 // when the stack adjustment matches. For example, with a thiscall that takes
3166 // only one argument.
3167 if (!CCMatch && (CallerCC == CallingConv::X86_StdCall ||
3168 CallerCC == CallingConv::X86_ThisCall))
3171 // Do not sibcall optimize vararg calls unless all arguments are passed via
3173 if (isVarArg && !Outs.empty()) {
3175 // Optimizing for varargs on Win64 is unlikely to be safe without
3176 // additional testing.
3177 if (IsCalleeWin64 || IsCallerWin64)
3180 SmallVector<CCValAssign, 16> ArgLocs;
3181 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(),
3182 getTargetMachine(), ArgLocs, *DAG.getContext());
3184 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
3185 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i)
3186 if (!ArgLocs[i].isRegLoc())
3190 // If the call result is in ST0 / ST1, it needs to be popped off the x87
3191 // stack. Therefore, if it's not used by the call it is not safe to optimize
3192 // this into a sibcall.
3193 bool Unused = false;
3194 for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
3201 SmallVector<CCValAssign, 16> RVLocs;
3202 CCState CCInfo(CalleeCC, false, DAG.getMachineFunction(),
3203 getTargetMachine(), RVLocs, *DAG.getContext());
3204 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
3205 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
3206 CCValAssign &VA = RVLocs[i];
3207 if (VA.getLocReg() == X86::ST0 || VA.getLocReg() == X86::ST1)
3212 // If the calling conventions do not match, then we'd better make sure the
3213 // results are returned in the same way as what the caller expects.
3215 SmallVector<CCValAssign, 16> RVLocs1;
3216 CCState CCInfo1(CalleeCC, false, DAG.getMachineFunction(),
3217 getTargetMachine(), RVLocs1, *DAG.getContext());
3218 CCInfo1.AnalyzeCallResult(Ins, RetCC_X86);
3220 SmallVector<CCValAssign, 16> RVLocs2;
3221 CCState CCInfo2(CallerCC, false, DAG.getMachineFunction(),
3222 getTargetMachine(), RVLocs2, *DAG.getContext());
3223 CCInfo2.AnalyzeCallResult(Ins, RetCC_X86);
3225 if (RVLocs1.size() != RVLocs2.size())
3227 for (unsigned i = 0, e = RVLocs1.size(); i != e; ++i) {
3228 if (RVLocs1[i].isRegLoc() != RVLocs2[i].isRegLoc())
3230 if (RVLocs1[i].getLocInfo() != RVLocs2[i].getLocInfo())
3232 if (RVLocs1[i].isRegLoc()) {
3233 if (RVLocs1[i].getLocReg() != RVLocs2[i].getLocReg())
3236 if (RVLocs1[i].getLocMemOffset() != RVLocs2[i].getLocMemOffset())
3242 // If the callee takes no arguments then go on to check the results of the
3244 if (!Outs.empty()) {
3245 // Check if stack adjustment is needed. For now, do not do this if any
3246 // argument is passed on the stack.
3247 SmallVector<CCValAssign, 16> ArgLocs;
3248 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(),
3249 getTargetMachine(), ArgLocs, *DAG.getContext());
3251 // Allocate shadow area for Win64
3253 CCInfo.AllocateStack(32, 8);
3255 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
3256 if (CCInfo.getNextStackOffset()) {
3257 MachineFunction &MF = DAG.getMachineFunction();
3258 if (MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn())
3261 // Check if the arguments are already laid out in the right way as
3262 // the caller's fixed stack objects.
3263 MachineFrameInfo *MFI = MF.getFrameInfo();
3264 const MachineRegisterInfo *MRI = &MF.getRegInfo();
3265 const X86InstrInfo *TII =
3266 ((const X86TargetMachine&)getTargetMachine()).getInstrInfo();
3267 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3268 CCValAssign &VA = ArgLocs[i];
3269 SDValue Arg = OutVals[i];
3270 ISD::ArgFlagsTy Flags = Outs[i].Flags;
3271 if (VA.getLocInfo() == CCValAssign::Indirect)
3273 if (!VA.isRegLoc()) {
3274 if (!MatchingStackOffset(Arg, VA.getLocMemOffset(), Flags,
3281 // If the tailcall address may be in a register, then make sure it's
3282 // possible to register allocate for it. In 32-bit, the call address can
3283 // only target EAX, EDX, or ECX since the tail call must be scheduled after
3284 // callee-saved registers are restored. These happen to be the same
3285 // registers used to pass 'inreg' arguments so watch out for those.
3286 if (!Subtarget->is64Bit() &&
3287 ((!isa<GlobalAddressSDNode>(Callee) &&
3288 !isa<ExternalSymbolSDNode>(Callee)) ||
3289 getTargetMachine().getRelocationModel() == Reloc::PIC_)) {
3290 unsigned NumInRegs = 0;
3291 // In PIC we need an extra register to formulate the address computation
3293 unsigned MaxInRegs =
3294 (getTargetMachine().getRelocationModel() == Reloc::PIC_) ? 2 : 3;
3296 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3297 CCValAssign &VA = ArgLocs[i];
3300 unsigned Reg = VA.getLocReg();
3303 case X86::EAX: case X86::EDX: case X86::ECX:
3304 if (++NumInRegs == MaxInRegs)
3316 X86TargetLowering::createFastISel(FunctionLoweringInfo &funcInfo,
3317 const TargetLibraryInfo *libInfo) const {
3318 return X86::createFastISel(funcInfo, libInfo);
3321 //===----------------------------------------------------------------------===//
3322 // Other Lowering Hooks
3323 //===----------------------------------------------------------------------===//
3325 static bool MayFoldLoad(SDValue Op) {
3326 return Op.hasOneUse() && ISD::isNormalLoad(Op.getNode());
3329 static bool MayFoldIntoStore(SDValue Op) {
3330 return Op.hasOneUse() && ISD::isNormalStore(*Op.getNode()->use_begin());
3333 static bool isTargetShuffle(unsigned Opcode) {
3335 default: return false;
3336 case X86ISD::PSHUFD:
3337 case X86ISD::PSHUFHW:
3338 case X86ISD::PSHUFLW:
3340 case X86ISD::PALIGNR:
3341 case X86ISD::MOVLHPS:
3342 case X86ISD::MOVLHPD:
3343 case X86ISD::MOVHLPS:
3344 case X86ISD::MOVLPS:
3345 case X86ISD::MOVLPD:
3346 case X86ISD::MOVSHDUP:
3347 case X86ISD::MOVSLDUP:
3348 case X86ISD::MOVDDUP:
3351 case X86ISD::UNPCKL:
3352 case X86ISD::UNPCKH:
3353 case X86ISD::VPERMILP:
3354 case X86ISD::VPERM2X128:
3355 case X86ISD::VPERMI:
3360 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3361 SDValue V1, SelectionDAG &DAG) {
3363 default: llvm_unreachable("Unknown x86 shuffle node");
3364 case X86ISD::MOVSHDUP:
3365 case X86ISD::MOVSLDUP:
3366 case X86ISD::MOVDDUP:
3367 return DAG.getNode(Opc, dl, VT, V1);
3371 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3372 SDValue V1, unsigned TargetMask,
3373 SelectionDAG &DAG) {
3375 default: llvm_unreachable("Unknown x86 shuffle node");
3376 case X86ISD::PSHUFD:
3377 case X86ISD::PSHUFHW:
3378 case X86ISD::PSHUFLW:
3379 case X86ISD::VPERMILP:
3380 case X86ISD::VPERMI:
3381 return DAG.getNode(Opc, dl, VT, V1, DAG.getConstant(TargetMask, MVT::i8));
3385 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3386 SDValue V1, SDValue V2, unsigned TargetMask,
3387 SelectionDAG &DAG) {
3389 default: llvm_unreachable("Unknown x86 shuffle node");
3390 case X86ISD::PALIGNR:
3392 case X86ISD::VPERM2X128:
3393 return DAG.getNode(Opc, dl, VT, V1, V2,
3394 DAG.getConstant(TargetMask, MVT::i8));
3398 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3399 SDValue V1, SDValue V2, SelectionDAG &DAG) {
3401 default: llvm_unreachable("Unknown x86 shuffle node");
3402 case X86ISD::MOVLHPS:
3403 case X86ISD::MOVLHPD:
3404 case X86ISD::MOVHLPS:
3405 case X86ISD::MOVLPS:
3406 case X86ISD::MOVLPD:
3409 case X86ISD::UNPCKL:
3410 case X86ISD::UNPCKH:
3411 return DAG.getNode(Opc, dl, VT, V1, V2);
3415 SDValue X86TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) const {
3416 MachineFunction &MF = DAG.getMachineFunction();
3417 const X86RegisterInfo *RegInfo =
3418 static_cast<const X86RegisterInfo*>(getTargetMachine().getRegisterInfo());
3419 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
3420 int ReturnAddrIndex = FuncInfo->getRAIndex();
3422 if (ReturnAddrIndex == 0) {
3423 // Set up a frame object for the return address.
3424 unsigned SlotSize = RegInfo->getSlotSize();
3425 ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(SlotSize,
3428 FuncInfo->setRAIndex(ReturnAddrIndex);
3431 return DAG.getFrameIndex(ReturnAddrIndex, getPointerTy());
3434 bool X86::isOffsetSuitableForCodeModel(int64_t Offset, CodeModel::Model M,
3435 bool hasSymbolicDisplacement) {
3436 // Offset should fit into 32 bit immediate field.
3437 if (!isInt<32>(Offset))
3440 // If we don't have a symbolic displacement - we don't have any extra
3442 if (!hasSymbolicDisplacement)
3445 // FIXME: Some tweaks might be needed for medium code model.
3446 if (M != CodeModel::Small && M != CodeModel::Kernel)
3449 // For small code model we assume that latest object is 16MB before end of 31
3450 // bits boundary. We may also accept pretty large negative constants knowing
3451 // that all objects are in the positive half of address space.
3452 if (M == CodeModel::Small && Offset < 16*1024*1024)
3455 // For kernel code model we know that all object resist in the negative half
3456 // of 32bits address space. We may not accept negative offsets, since they may
3457 // be just off and we may accept pretty large positive ones.
3458 if (M == CodeModel::Kernel && Offset > 0)
3464 /// isCalleePop - Determines whether the callee is required to pop its
3465 /// own arguments. Callee pop is necessary to support tail calls.
3466 bool X86::isCalleePop(CallingConv::ID CallingConv,
3467 bool is64Bit, bool IsVarArg, bool TailCallOpt) {
3471 switch (CallingConv) {
3474 case CallingConv::X86_StdCall:
3476 case CallingConv::X86_FastCall:
3478 case CallingConv::X86_ThisCall:
3480 case CallingConv::Fast:
3482 case CallingConv::GHC:
3484 case CallingConv::HiPE:
3489 /// \brief Return true if the condition is an unsigned comparison operation.
3490 static bool isX86CCUnsigned(unsigned X86CC) {
3492 default: llvm_unreachable("Invalid integer condition!");
3493 case X86::COND_E: return true;
3494 case X86::COND_G: return false;
3495 case X86::COND_GE: return false;
3496 case X86::COND_L: return false;
3497 case X86::COND_LE: return false;
3498 case X86::COND_NE: return true;
3499 case X86::COND_B: return true;
3500 case X86::COND_A: return true;
3501 case X86::COND_BE: return true;
3502 case X86::COND_AE: return true;
3504 llvm_unreachable("covered switch fell through?!");
3507 /// TranslateX86CC - do a one to one translation of a ISD::CondCode to the X86
3508 /// specific condition code, returning the condition code and the LHS/RHS of the
3509 /// comparison to make.
3510 static unsigned TranslateX86CC(ISD::CondCode SetCCOpcode, bool isFP,
3511 SDValue &LHS, SDValue &RHS, SelectionDAG &DAG) {
3513 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
3514 if (SetCCOpcode == ISD::SETGT && RHSC->isAllOnesValue()) {
3515 // X > -1 -> X == 0, jump !sign.
3516 RHS = DAG.getConstant(0, RHS.getValueType());
3517 return X86::COND_NS;
3519 if (SetCCOpcode == ISD::SETLT && RHSC->isNullValue()) {
3520 // X < 0 -> X == 0, jump on sign.
3523 if (SetCCOpcode == ISD::SETLT && RHSC->getZExtValue() == 1) {
3525 RHS = DAG.getConstant(0, RHS.getValueType());
3526 return X86::COND_LE;
3530 switch (SetCCOpcode) {
3531 default: llvm_unreachable("Invalid integer condition!");
3532 case ISD::SETEQ: return X86::COND_E;
3533 case ISD::SETGT: return X86::COND_G;
3534 case ISD::SETGE: return X86::COND_GE;
3535 case ISD::SETLT: return X86::COND_L;
3536 case ISD::SETLE: return X86::COND_LE;
3537 case ISD::SETNE: return X86::COND_NE;
3538 case ISD::SETULT: return X86::COND_B;
3539 case ISD::SETUGT: return X86::COND_A;
3540 case ISD::SETULE: return X86::COND_BE;
3541 case ISD::SETUGE: return X86::COND_AE;
3545 // First determine if it is required or is profitable to flip the operands.
3547 // If LHS is a foldable load, but RHS is not, flip the condition.
3548 if (ISD::isNON_EXTLoad(LHS.getNode()) &&
3549 !ISD::isNON_EXTLoad(RHS.getNode())) {
3550 SetCCOpcode = getSetCCSwappedOperands(SetCCOpcode);
3551 std::swap(LHS, RHS);
3554 switch (SetCCOpcode) {
3560 std::swap(LHS, RHS);
3564 // On a floating point condition, the flags are set as follows:
3566 // 0 | 0 | 0 | X > Y
3567 // 0 | 0 | 1 | X < Y
3568 // 1 | 0 | 0 | X == Y
3569 // 1 | 1 | 1 | unordered
3570 switch (SetCCOpcode) {
3571 default: llvm_unreachable("Condcode should be pre-legalized away");
3573 case ISD::SETEQ: return X86::COND_E;
3574 case ISD::SETOLT: // flipped
3576 case ISD::SETGT: return X86::COND_A;
3577 case ISD::SETOLE: // flipped
3579 case ISD::SETGE: return X86::COND_AE;
3580 case ISD::SETUGT: // flipped
3582 case ISD::SETLT: return X86::COND_B;
3583 case ISD::SETUGE: // flipped
3585 case ISD::SETLE: return X86::COND_BE;
3587 case ISD::SETNE: return X86::COND_NE;
3588 case ISD::SETUO: return X86::COND_P;
3589 case ISD::SETO: return X86::COND_NP;
3591 case ISD::SETUNE: return X86::COND_INVALID;
3595 /// hasFPCMov - is there a floating point cmov for the specific X86 condition
3596 /// code. Current x86 isa includes the following FP cmov instructions:
3597 /// fcmovb, fcomvbe, fcomve, fcmovu, fcmovae, fcmova, fcmovne, fcmovnu.
3598 static bool hasFPCMov(unsigned X86CC) {
3614 /// isFPImmLegal - Returns true if the target can instruction select the
3615 /// specified FP immediate natively. If false, the legalizer will
3616 /// materialize the FP immediate as a load from a constant pool.
3617 bool X86TargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
3618 for (unsigned i = 0, e = LegalFPImmediates.size(); i != e; ++i) {
3619 if (Imm.bitwiseIsEqual(LegalFPImmediates[i]))
3625 /// \brief Returns true if it is beneficial to convert a load of a constant
3626 /// to just the constant itself.
3627 bool X86TargetLowering::shouldConvertConstantLoadToIntImm(const APInt &Imm,
3629 assert(Ty->isIntegerTy());
3631 unsigned BitSize = Ty->getPrimitiveSizeInBits();
3632 if (BitSize == 0 || BitSize > 64)
3637 /// isUndefOrInRange - Return true if Val is undef or if its value falls within
3638 /// the specified range (L, H].
3639 static bool isUndefOrInRange(int Val, int Low, int Hi) {
3640 return (Val < 0) || (Val >= Low && Val < Hi);
3643 /// isUndefOrEqual - Val is either less than zero (undef) or equal to the
3644 /// specified value.
3645 static bool isUndefOrEqual(int Val, int CmpVal) {
3646 return (Val < 0 || Val == CmpVal);
3649 /// isSequentialOrUndefInRange - Return true if every element in Mask, beginning
3650 /// from position Pos and ending in Pos+Size, falls within the specified
3651 /// sequential range (L, L+Pos]. or is undef.
3652 static bool isSequentialOrUndefInRange(ArrayRef<int> Mask,
3653 unsigned Pos, unsigned Size, int Low) {
3654 for (unsigned i = Pos, e = Pos+Size; i != e; ++i, ++Low)
3655 if (!isUndefOrEqual(Mask[i], Low))
3660 /// isPSHUFDMask - Return true if the node specifies a shuffle of elements that
3661 /// is suitable for input to PSHUFD or PSHUFW. That is, it doesn't reference
3662 /// the second operand.
3663 static bool isPSHUFDMask(ArrayRef<int> Mask, MVT VT) {
3664 if (VT == MVT::v4f32 || VT == MVT::v4i32 )
3665 return (Mask[0] < 4 && Mask[1] < 4 && Mask[2] < 4 && Mask[3] < 4);
3666 if (VT == MVT::v2f64 || VT == MVT::v2i64)
3667 return (Mask[0] < 2 && Mask[1] < 2);
3671 /// isPSHUFHWMask - Return true if the node specifies a shuffle of elements that
3672 /// is suitable for input to PSHUFHW.
3673 static bool isPSHUFHWMask(ArrayRef<int> Mask, MVT VT, bool HasInt256) {
3674 if (VT != MVT::v8i16 && (!HasInt256 || VT != MVT::v16i16))
3677 // Lower quadword copied in order or undef.
3678 if (!isSequentialOrUndefInRange(Mask, 0, 4, 0))
3681 // Upper quadword shuffled.
3682 for (unsigned i = 4; i != 8; ++i)
3683 if (!isUndefOrInRange(Mask[i], 4, 8))
3686 if (VT == MVT::v16i16) {
3687 // Lower quadword copied in order or undef.
3688 if (!isSequentialOrUndefInRange(Mask, 8, 4, 8))
3691 // Upper quadword shuffled.
3692 for (unsigned i = 12; i != 16; ++i)
3693 if (!isUndefOrInRange(Mask[i], 12, 16))
3700 /// isPSHUFLWMask - Return true if the node specifies a shuffle of elements that
3701 /// is suitable for input to PSHUFLW.
3702 static bool isPSHUFLWMask(ArrayRef<int> Mask, MVT VT, bool HasInt256) {
3703 if (VT != MVT::v8i16 && (!HasInt256 || VT != MVT::v16i16))
3706 // Upper quadword copied in order.
3707 if (!isSequentialOrUndefInRange(Mask, 4, 4, 4))
3710 // Lower quadword shuffled.
3711 for (unsigned i = 0; i != 4; ++i)
3712 if (!isUndefOrInRange(Mask[i], 0, 4))
3715 if (VT == MVT::v16i16) {
3716 // Upper quadword copied in order.
3717 if (!isSequentialOrUndefInRange(Mask, 12, 4, 12))
3720 // Lower quadword shuffled.
3721 for (unsigned i = 8; i != 12; ++i)
3722 if (!isUndefOrInRange(Mask[i], 8, 12))
3729 /// isPALIGNRMask - Return true if the node specifies a shuffle of elements that
3730 /// is suitable for input to PALIGNR.
3731 static bool isPALIGNRMask(ArrayRef<int> Mask, MVT VT,
3732 const X86Subtarget *Subtarget) {
3733 if ((VT.is128BitVector() && !Subtarget->hasSSSE3()) ||
3734 (VT.is256BitVector() && !Subtarget->hasInt256()))
3737 unsigned NumElts = VT.getVectorNumElements();
3738 unsigned NumLanes = VT.is512BitVector() ? 1: VT.getSizeInBits()/128;
3739 unsigned NumLaneElts = NumElts/NumLanes;
3741 // Do not handle 64-bit element shuffles with palignr.
3742 if (NumLaneElts == 2)
3745 for (unsigned l = 0; l != NumElts; l+=NumLaneElts) {
3747 for (i = 0; i != NumLaneElts; ++i) {
3752 // Lane is all undef, go to next lane
3753 if (i == NumLaneElts)
3756 int Start = Mask[i+l];
3758 // Make sure its in this lane in one of the sources
3759 if (!isUndefOrInRange(Start, l, l+NumLaneElts) &&
3760 !isUndefOrInRange(Start, l+NumElts, l+NumElts+NumLaneElts))
3763 // If not lane 0, then we must match lane 0
3764 if (l != 0 && Mask[i] >= 0 && !isUndefOrEqual(Start, Mask[i]+l))
3767 // Correct second source to be contiguous with first source
3768 if (Start >= (int)NumElts)
3769 Start -= NumElts - NumLaneElts;
3771 // Make sure we're shifting in the right direction.
3772 if (Start <= (int)(i+l))
3777 // Check the rest of the elements to see if they are consecutive.
3778 for (++i; i != NumLaneElts; ++i) {
3779 int Idx = Mask[i+l];
3781 // Make sure its in this lane
3782 if (!isUndefOrInRange(Idx, l, l+NumLaneElts) &&
3783 !isUndefOrInRange(Idx, l+NumElts, l+NumElts+NumLaneElts))
3786 // If not lane 0, then we must match lane 0
3787 if (l != 0 && Mask[i] >= 0 && !isUndefOrEqual(Idx, Mask[i]+l))
3790 if (Idx >= (int)NumElts)
3791 Idx -= NumElts - NumLaneElts;
3793 if (!isUndefOrEqual(Idx, Start+i))
3802 /// CommuteVectorShuffleMask - Change values in a shuffle permute mask assuming
3803 /// the two vector operands have swapped position.
3804 static void CommuteVectorShuffleMask(SmallVectorImpl<int> &Mask,
3805 unsigned NumElems) {
3806 for (unsigned i = 0; i != NumElems; ++i) {
3810 else if (idx < (int)NumElems)
3811 Mask[i] = idx + NumElems;
3813 Mask[i] = idx - NumElems;
3817 /// isSHUFPMask - Return true if the specified VECTOR_SHUFFLE operand
3818 /// specifies a shuffle of elements that is suitable for input to 128/256-bit
3819 /// SHUFPS and SHUFPD. If Commuted is true, then it checks for sources to be
3820 /// reverse of what x86 shuffles want.
3821 static bool isSHUFPMask(ArrayRef<int> Mask, MVT VT, bool Commuted = false) {
3823 unsigned NumElems = VT.getVectorNumElements();
3824 unsigned NumLanes = VT.getSizeInBits()/128;
3825 unsigned NumLaneElems = NumElems/NumLanes;
3827 if (NumLaneElems != 2 && NumLaneElems != 4)
3830 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
3831 bool symetricMaskRequired =
3832 (VT.getSizeInBits() >= 256) && (EltSize == 32);
3834 // VSHUFPSY divides the resulting vector into 4 chunks.
3835 // The sources are also splitted into 4 chunks, and each destination
3836 // chunk must come from a different source chunk.
3838 // SRC1 => X7 X6 X5 X4 X3 X2 X1 X0
3839 // SRC2 => Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y9
3841 // DST => Y7..Y4, Y7..Y4, X7..X4, X7..X4,
3842 // Y3..Y0, Y3..Y0, X3..X0, X3..X0
3844 // VSHUFPDY divides the resulting vector into 4 chunks.
3845 // The sources are also splitted into 4 chunks, and each destination
3846 // chunk must come from a different source chunk.
3848 // SRC1 => X3 X2 X1 X0
3849 // SRC2 => Y3 Y2 Y1 Y0
3851 // DST => Y3..Y2, X3..X2, Y1..Y0, X1..X0
3853 SmallVector<int, 4> MaskVal(NumLaneElems, -1);
3854 unsigned HalfLaneElems = NumLaneElems/2;
3855 for (unsigned l = 0; l != NumElems; l += NumLaneElems) {
3856 for (unsigned i = 0; i != NumLaneElems; ++i) {
3857 int Idx = Mask[i+l];
3858 unsigned RngStart = l + ((Commuted == (i<HalfLaneElems)) ? NumElems : 0);
3859 if (!isUndefOrInRange(Idx, RngStart, RngStart+NumLaneElems))
3861 // For VSHUFPSY, the mask of the second half must be the same as the
3862 // first but with the appropriate offsets. This works in the same way as
3863 // VPERMILPS works with masks.
3864 if (!symetricMaskRequired || Idx < 0)
3866 if (MaskVal[i] < 0) {
3867 MaskVal[i] = Idx - l;
3870 if ((signed)(Idx - l) != MaskVal[i])
3878 /// isMOVHLPSMask - Return true if the specified VECTOR_SHUFFLE operand
3879 /// specifies a shuffle of elements that is suitable for input to MOVHLPS.
3880 static bool isMOVHLPSMask(ArrayRef<int> Mask, MVT VT) {
3881 if (!VT.is128BitVector())
3884 unsigned NumElems = VT.getVectorNumElements();
3889 // Expect bit0 == 6, bit1 == 7, bit2 == 2, bit3 == 3
3890 return isUndefOrEqual(Mask[0], 6) &&
3891 isUndefOrEqual(Mask[1], 7) &&
3892 isUndefOrEqual(Mask[2], 2) &&
3893 isUndefOrEqual(Mask[3], 3);
3896 /// isMOVHLPS_v_undef_Mask - Special case of isMOVHLPSMask for canonical form
3897 /// of vector_shuffle v, v, <2, 3, 2, 3>, i.e. vector_shuffle v, undef,
3899 static bool isMOVHLPS_v_undef_Mask(ArrayRef<int> Mask, MVT VT) {
3900 if (!VT.is128BitVector())
3903 unsigned NumElems = VT.getVectorNumElements();
3908 return isUndefOrEqual(Mask[0], 2) &&
3909 isUndefOrEqual(Mask[1], 3) &&
3910 isUndefOrEqual(Mask[2], 2) &&
3911 isUndefOrEqual(Mask[3], 3);
3914 /// isMOVLPMask - Return true if the specified VECTOR_SHUFFLE operand
3915 /// specifies a shuffle of elements that is suitable for input to MOVLP{S|D}.
3916 static bool isMOVLPMask(ArrayRef<int> Mask, MVT VT) {
3917 if (!VT.is128BitVector())
3920 unsigned NumElems = VT.getVectorNumElements();
3922 if (NumElems != 2 && NumElems != 4)
3925 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
3926 if (!isUndefOrEqual(Mask[i], i + NumElems))
3929 for (unsigned i = NumElems/2, e = NumElems; i != e; ++i)
3930 if (!isUndefOrEqual(Mask[i], i))
3936 /// isMOVLHPSMask - Return true if the specified VECTOR_SHUFFLE operand
3937 /// specifies a shuffle of elements that is suitable for input to MOVLHPS.
3938 static bool isMOVLHPSMask(ArrayRef<int> Mask, MVT VT) {
3939 if (!VT.is128BitVector())
3942 unsigned NumElems = VT.getVectorNumElements();
3944 if (NumElems != 2 && NumElems != 4)
3947 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
3948 if (!isUndefOrEqual(Mask[i], i))
3951 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
3952 if (!isUndefOrEqual(Mask[i + e], i + NumElems))
3958 /// isINSERTPSMask - Return true if the specified VECTOR_SHUFFLE operand
3959 /// specifies a shuffle of elements that is suitable for input to INSERTPS.
3960 /// i. e: If all but one element come from the same vector.
3961 static bool isINSERTPSMask(ArrayRef<int> Mask, MVT VT) {
3962 // TODO: Deal with AVX's VINSERTPS
3963 if (!VT.is128BitVector() || (VT != MVT::v4f32 && VT != MVT::v4i32))
3966 unsigned CorrectPosV1 = 0;
3967 unsigned CorrectPosV2 = 0;
3968 for (int i = 0, e = (int)VT.getVectorNumElements(); i != e; ++i)
3971 else if (Mask[i] == i + 4)
3974 if (CorrectPosV1 == 3 || CorrectPosV2 == 3)
3975 // We have 3 elements from one vector, and one from another.
3982 // Some special combinations that can be optimized.
3985 SDValue Compact8x32ShuffleNode(ShuffleVectorSDNode *SVOp,
3986 SelectionDAG &DAG) {
3987 MVT VT = SVOp->getSimpleValueType(0);
3990 if (VT != MVT::v8i32 && VT != MVT::v8f32)
3993 ArrayRef<int> Mask = SVOp->getMask();
3995 // These are the special masks that may be optimized.
3996 static const int MaskToOptimizeEven[] = {0, 8, 2, 10, 4, 12, 6, 14};
3997 static const int MaskToOptimizeOdd[] = {1, 9, 3, 11, 5, 13, 7, 15};
3998 bool MatchEvenMask = true;
3999 bool MatchOddMask = true;
4000 for (int i=0; i<8; ++i) {
4001 if (!isUndefOrEqual(Mask[i], MaskToOptimizeEven[i]))
4002 MatchEvenMask = false;
4003 if (!isUndefOrEqual(Mask[i], MaskToOptimizeOdd[i]))
4004 MatchOddMask = false;
4007 if (!MatchEvenMask && !MatchOddMask)
4010 SDValue UndefNode = DAG.getNode(ISD::UNDEF, dl, VT);
4012 SDValue Op0 = SVOp->getOperand(0);
4013 SDValue Op1 = SVOp->getOperand(1);
4015 if (MatchEvenMask) {
4016 // Shift the second operand right to 32 bits.
4017 static const int ShiftRightMask[] = {-1, 0, -1, 2, -1, 4, -1, 6 };
4018 Op1 = DAG.getVectorShuffle(VT, dl, Op1, UndefNode, ShiftRightMask);
4020 // Shift the first operand left to 32 bits.
4021 static const int ShiftLeftMask[] = {1, -1, 3, -1, 5, -1, 7, -1 };
4022 Op0 = DAG.getVectorShuffle(VT, dl, Op0, UndefNode, ShiftLeftMask);
4024 static const int BlendMask[] = {0, 9, 2, 11, 4, 13, 6, 15};
4025 return DAG.getVectorShuffle(VT, dl, Op0, Op1, BlendMask);
4028 /// isUNPCKLMask - Return true if the specified VECTOR_SHUFFLE operand
4029 /// specifies a shuffle of elements that is suitable for input to UNPCKL.
4030 static bool isUNPCKLMask(ArrayRef<int> Mask, MVT VT,
4031 bool HasInt256, bool V2IsSplat = false) {
4033 assert(VT.getSizeInBits() >= 128 &&
4034 "Unsupported vector type for unpckl");
4036 // AVX defines UNPCK* to operate independently on 128-bit lanes.
4038 unsigned NumOf256BitLanes;
4039 unsigned NumElts = VT.getVectorNumElements();
4040 if (VT.is256BitVector()) {
4041 if (NumElts != 4 && NumElts != 8 &&
4042 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
4045 NumOf256BitLanes = 1;
4046 } else if (VT.is512BitVector()) {
4047 assert(VT.getScalarType().getSizeInBits() >= 32 &&
4048 "Unsupported vector type for unpckh");
4050 NumOf256BitLanes = 2;
4053 NumOf256BitLanes = 1;
4056 unsigned NumEltsInStride = NumElts/NumOf256BitLanes;
4057 unsigned NumLaneElts = NumEltsInStride/NumLanes;
4059 for (unsigned l256 = 0; l256 < NumOf256BitLanes; l256 += 1) {
4060 for (unsigned l = 0; l != NumEltsInStride; l += NumLaneElts) {
4061 for (unsigned i = 0, j = l; i != NumLaneElts; i += 2, ++j) {
4062 int BitI = Mask[l256*NumEltsInStride+l+i];
4063 int BitI1 = Mask[l256*NumEltsInStride+l+i+1];
4064 if (!isUndefOrEqual(BitI, j+l256*NumElts))
4066 if (V2IsSplat && !isUndefOrEqual(BitI1, NumElts))
4068 if (!isUndefOrEqual(BitI1, j+l256*NumElts+NumEltsInStride))
4076 /// isUNPCKHMask - Return true if the specified VECTOR_SHUFFLE operand
4077 /// specifies a shuffle of elements that is suitable for input to UNPCKH.
4078 static bool isUNPCKHMask(ArrayRef<int> Mask, MVT VT,
4079 bool HasInt256, bool V2IsSplat = false) {
4080 assert(VT.getSizeInBits() >= 128 &&
4081 "Unsupported vector type for unpckh");
4083 // AVX defines UNPCK* to operate independently on 128-bit lanes.
4085 unsigned NumOf256BitLanes;
4086 unsigned NumElts = VT.getVectorNumElements();
4087 if (VT.is256BitVector()) {
4088 if (NumElts != 4 && NumElts != 8 &&
4089 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
4092 NumOf256BitLanes = 1;
4093 } else if (VT.is512BitVector()) {
4094 assert(VT.getScalarType().getSizeInBits() >= 32 &&
4095 "Unsupported vector type for unpckh");
4097 NumOf256BitLanes = 2;
4100 NumOf256BitLanes = 1;
4103 unsigned NumEltsInStride = NumElts/NumOf256BitLanes;
4104 unsigned NumLaneElts = NumEltsInStride/NumLanes;
4106 for (unsigned l256 = 0; l256 < NumOf256BitLanes; l256 += 1) {
4107 for (unsigned l = 0; l != NumEltsInStride; l += NumLaneElts) {
4108 for (unsigned i = 0, j = l+NumLaneElts/2; i != NumLaneElts; i += 2, ++j) {
4109 int BitI = Mask[l256*NumEltsInStride+l+i];
4110 int BitI1 = Mask[l256*NumEltsInStride+l+i+1];
4111 if (!isUndefOrEqual(BitI, j+l256*NumElts))
4113 if (V2IsSplat && !isUndefOrEqual(BitI1, NumElts))
4115 if (!isUndefOrEqual(BitI1, j+l256*NumElts+NumEltsInStride))
4123 /// isUNPCKL_v_undef_Mask - Special case of isUNPCKLMask for canonical form
4124 /// of vector_shuffle v, v, <0, 4, 1, 5>, i.e. vector_shuffle v, undef,
4126 static bool isUNPCKL_v_undef_Mask(ArrayRef<int> Mask, MVT VT, bool HasInt256) {
4127 unsigned NumElts = VT.getVectorNumElements();
4128 bool Is256BitVec = VT.is256BitVector();
4130 if (VT.is512BitVector())
4132 assert((VT.is128BitVector() || VT.is256BitVector()) &&
4133 "Unsupported vector type for unpckh");
4135 if (Is256BitVec && NumElts != 4 && NumElts != 8 &&
4136 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
4139 // For 256-bit i64/f64, use MOVDDUPY instead, so reject the matching pattern
4140 // FIXME: Need a better way to get rid of this, there's no latency difference
4141 // between UNPCKLPD and MOVDDUP, the later should always be checked first and
4142 // the former later. We should also remove the "_undef" special mask.
4143 if (NumElts == 4 && Is256BitVec)
4146 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
4147 // independently on 128-bit lanes.
4148 unsigned NumLanes = VT.getSizeInBits()/128;
4149 unsigned NumLaneElts = NumElts/NumLanes;
4151 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
4152 for (unsigned i = 0, j = l; i != NumLaneElts; i += 2, ++j) {
4153 int BitI = Mask[l+i];
4154 int BitI1 = Mask[l+i+1];
4156 if (!isUndefOrEqual(BitI, j))
4158 if (!isUndefOrEqual(BitI1, j))
4166 /// isUNPCKH_v_undef_Mask - Special case of isUNPCKHMask for canonical form
4167 /// of vector_shuffle v, v, <2, 6, 3, 7>, i.e. vector_shuffle v, undef,
4169 static bool isUNPCKH_v_undef_Mask(ArrayRef<int> Mask, MVT VT, bool HasInt256) {
4170 unsigned NumElts = VT.getVectorNumElements();
4172 if (VT.is512BitVector())
4175 assert((VT.is128BitVector() || VT.is256BitVector()) &&
4176 "Unsupported vector type for unpckh");
4178 if (VT.is256BitVector() && NumElts != 4 && NumElts != 8 &&
4179 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
4182 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
4183 // independently on 128-bit lanes.
4184 unsigned NumLanes = VT.getSizeInBits()/128;
4185 unsigned NumLaneElts = NumElts/NumLanes;
4187 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
4188 for (unsigned i = 0, j = l+NumLaneElts/2; i != NumLaneElts; i += 2, ++j) {
4189 int BitI = Mask[l+i];
4190 int BitI1 = Mask[l+i+1];
4191 if (!isUndefOrEqual(BitI, j))
4193 if (!isUndefOrEqual(BitI1, j))
4200 // Match for INSERTI64x4 INSERTF64x4 instructions (src0[0], src1[0]) or
4201 // (src1[0], src0[1]), manipulation with 256-bit sub-vectors
4202 static bool isINSERT64x4Mask(ArrayRef<int> Mask, MVT VT, unsigned int *Imm) {
4203 if (!VT.is512BitVector())
4206 unsigned NumElts = VT.getVectorNumElements();
4207 unsigned HalfSize = NumElts/2;
4208 if (isSequentialOrUndefInRange(Mask, 0, HalfSize, 0)) {
4209 if (isSequentialOrUndefInRange(Mask, HalfSize, HalfSize, NumElts)) {
4214 if (isSequentialOrUndefInRange(Mask, 0, HalfSize, NumElts)) {
4215 if (isSequentialOrUndefInRange(Mask, HalfSize, HalfSize, HalfSize)) {
4223 /// isMOVLMask - Return true if the specified VECTOR_SHUFFLE operand
4224 /// specifies a shuffle of elements that is suitable for input to MOVSS,
4225 /// MOVSD, and MOVD, i.e. setting the lowest element.
4226 static bool isMOVLMask(ArrayRef<int> Mask, EVT VT) {
4227 if (VT.getVectorElementType().getSizeInBits() < 32)
4229 if (!VT.is128BitVector())
4232 unsigned NumElts = VT.getVectorNumElements();
4234 if (!isUndefOrEqual(Mask[0], NumElts))
4237 for (unsigned i = 1; i != NumElts; ++i)
4238 if (!isUndefOrEqual(Mask[i], i))
4244 /// isVPERM2X128Mask - Match 256-bit shuffles where the elements are considered
4245 /// as permutations between 128-bit chunks or halves. As an example: this
4247 /// vector_shuffle <4, 5, 6, 7, 12, 13, 14, 15>
4248 /// The first half comes from the second half of V1 and the second half from the
4249 /// the second half of V2.
4250 static bool isVPERM2X128Mask(ArrayRef<int> Mask, MVT VT, bool HasFp256) {
4251 if (!HasFp256 || !VT.is256BitVector())
4254 // The shuffle result is divided into half A and half B. In total the two
4255 // sources have 4 halves, namely: C, D, E, F. The final values of A and
4256 // B must come from C, D, E or F.
4257 unsigned HalfSize = VT.getVectorNumElements()/2;
4258 bool MatchA = false, MatchB = false;
4260 // Check if A comes from one of C, D, E, F.
4261 for (unsigned Half = 0; Half != 4; ++Half) {
4262 if (isSequentialOrUndefInRange(Mask, 0, HalfSize, Half*HalfSize)) {
4268 // Check if B comes from one of C, D, E, F.
4269 for (unsigned Half = 0; Half != 4; ++Half) {
4270 if (isSequentialOrUndefInRange(Mask, HalfSize, HalfSize, Half*HalfSize)) {
4276 return MatchA && MatchB;
4279 /// getShuffleVPERM2X128Immediate - Return the appropriate immediate to shuffle
4280 /// the specified VECTOR_MASK mask with VPERM2F128/VPERM2I128 instructions.
4281 static unsigned getShuffleVPERM2X128Immediate(ShuffleVectorSDNode *SVOp) {
4282 MVT VT = SVOp->getSimpleValueType(0);
4284 unsigned HalfSize = VT.getVectorNumElements()/2;
4286 unsigned FstHalf = 0, SndHalf = 0;
4287 for (unsigned i = 0; i < HalfSize; ++i) {
4288 if (SVOp->getMaskElt(i) > 0) {
4289 FstHalf = SVOp->getMaskElt(i)/HalfSize;
4293 for (unsigned i = HalfSize; i < HalfSize*2; ++i) {
4294 if (SVOp->getMaskElt(i) > 0) {
4295 SndHalf = SVOp->getMaskElt(i)/HalfSize;
4300 return (FstHalf | (SndHalf << 4));
4303 // Symetric in-lane mask. Each lane has 4 elements (for imm8)
4304 static bool isPermImmMask(ArrayRef<int> Mask, MVT VT, unsigned& Imm8) {
4305 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
4309 unsigned NumElts = VT.getVectorNumElements();
4311 if (VT.is128BitVector() || (VT.is256BitVector() && EltSize == 64)) {
4312 for (unsigned i = 0; i != NumElts; ++i) {
4315 Imm8 |= Mask[i] << (i*2);
4320 unsigned LaneSize = 4;
4321 SmallVector<int, 4> MaskVal(LaneSize, -1);
4323 for (unsigned l = 0; l != NumElts; l += LaneSize) {
4324 for (unsigned i = 0; i != LaneSize; ++i) {
4325 if (!isUndefOrInRange(Mask[i+l], l, l+LaneSize))
4329 if (MaskVal[i] < 0) {
4330 MaskVal[i] = Mask[i+l] - l;
4331 Imm8 |= MaskVal[i] << (i*2);
4334 if (Mask[i+l] != (signed)(MaskVal[i]+l))
4341 /// isVPERMILPMask - Return true if the specified VECTOR_SHUFFLE operand
4342 /// specifies a shuffle of elements that is suitable for input to VPERMILPD*.
4343 /// Note that VPERMIL mask matching is different depending whether theunderlying
4344 /// type is 32 or 64. In the VPERMILPS the high half of the mask should point
4345 /// to the same elements of the low, but to the higher half of the source.
4346 /// In VPERMILPD the two lanes could be shuffled independently of each other
4347 /// with the same restriction that lanes can't be crossed. Also handles PSHUFDY.
4348 static bool isVPERMILPMask(ArrayRef<int> Mask, MVT VT) {
4349 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
4350 if (VT.getSizeInBits() < 256 || EltSize < 32)
4352 bool symetricMaskRequired = (EltSize == 32);
4353 unsigned NumElts = VT.getVectorNumElements();
4355 unsigned NumLanes = VT.getSizeInBits()/128;
4356 unsigned LaneSize = NumElts/NumLanes;
4357 // 2 or 4 elements in one lane
4359 SmallVector<int, 4> ExpectedMaskVal(LaneSize, -1);
4360 for (unsigned l = 0; l != NumElts; l += LaneSize) {
4361 for (unsigned i = 0; i != LaneSize; ++i) {
4362 if (!isUndefOrInRange(Mask[i+l], l, l+LaneSize))
4364 if (symetricMaskRequired) {
4365 if (ExpectedMaskVal[i] < 0 && Mask[i+l] >= 0) {
4366 ExpectedMaskVal[i] = Mask[i+l] - l;
4369 if (!isUndefOrEqual(Mask[i+l], ExpectedMaskVal[i]+l))
4377 /// isCommutedMOVLMask - Returns true if the shuffle mask is except the reverse
4378 /// of what x86 movss want. X86 movs requires the lowest element to be lowest
4379 /// element of vector 2 and the other elements to come from vector 1 in order.
4380 static bool isCommutedMOVLMask(ArrayRef<int> Mask, MVT VT,
4381 bool V2IsSplat = false, bool V2IsUndef = false) {
4382 if (!VT.is128BitVector())
4385 unsigned NumOps = VT.getVectorNumElements();
4386 if (NumOps != 2 && NumOps != 4 && NumOps != 8 && NumOps != 16)
4389 if (!isUndefOrEqual(Mask[0], 0))
4392 for (unsigned i = 1; i != NumOps; ++i)
4393 if (!(isUndefOrEqual(Mask[i], i+NumOps) ||
4394 (V2IsUndef && isUndefOrInRange(Mask[i], NumOps, NumOps*2)) ||
4395 (V2IsSplat && isUndefOrEqual(Mask[i], NumOps))))
4401 /// isMOVSHDUPMask - Return true if the specified VECTOR_SHUFFLE operand
4402 /// specifies a shuffle of elements that is suitable for input to MOVSHDUP.
4403 /// Masks to match: <1, 1, 3, 3> or <1, 1, 3, 3, 5, 5, 7, 7>
4404 static bool isMOVSHDUPMask(ArrayRef<int> Mask, MVT VT,
4405 const X86Subtarget *Subtarget) {
4406 if (!Subtarget->hasSSE3())
4409 unsigned NumElems = VT.getVectorNumElements();
4411 if ((VT.is128BitVector() && NumElems != 4) ||
4412 (VT.is256BitVector() && NumElems != 8) ||
4413 (VT.is512BitVector() && NumElems != 16))
4416 // "i+1" is the value the indexed mask element must have
4417 for (unsigned i = 0; i != NumElems; i += 2)
4418 if (!isUndefOrEqual(Mask[i], i+1) ||
4419 !isUndefOrEqual(Mask[i+1], i+1))
4425 /// isMOVSLDUPMask - Return true if the specified VECTOR_SHUFFLE operand
4426 /// specifies a shuffle of elements that is suitable for input to MOVSLDUP.
4427 /// Masks to match: <0, 0, 2, 2> or <0, 0, 2, 2, 4, 4, 6, 6>
4428 static bool isMOVSLDUPMask(ArrayRef<int> Mask, MVT VT,
4429 const X86Subtarget *Subtarget) {
4430 if (!Subtarget->hasSSE3())
4433 unsigned NumElems = VT.getVectorNumElements();
4435 if ((VT.is128BitVector() && NumElems != 4) ||
4436 (VT.is256BitVector() && NumElems != 8) ||
4437 (VT.is512BitVector() && NumElems != 16))
4440 // "i" is the value the indexed mask element must have
4441 for (unsigned i = 0; i != NumElems; i += 2)
4442 if (!isUndefOrEqual(Mask[i], i) ||
4443 !isUndefOrEqual(Mask[i+1], i))
4449 /// isMOVDDUPYMask - Return true if the specified VECTOR_SHUFFLE operand
4450 /// specifies a shuffle of elements that is suitable for input to 256-bit
4451 /// version of MOVDDUP.
4452 static bool isMOVDDUPYMask(ArrayRef<int> Mask, MVT VT, bool HasFp256) {
4453 if (!HasFp256 || !VT.is256BitVector())
4456 unsigned NumElts = VT.getVectorNumElements();
4460 for (unsigned i = 0; i != NumElts/2; ++i)
4461 if (!isUndefOrEqual(Mask[i], 0))
4463 for (unsigned i = NumElts/2; i != NumElts; ++i)
4464 if (!isUndefOrEqual(Mask[i], NumElts/2))
4469 /// isMOVDDUPMask - Return true if the specified VECTOR_SHUFFLE operand
4470 /// specifies a shuffle of elements that is suitable for input to 128-bit
4471 /// version of MOVDDUP.
4472 static bool isMOVDDUPMask(ArrayRef<int> Mask, MVT VT) {
4473 if (!VT.is128BitVector())
4476 unsigned e = VT.getVectorNumElements() / 2;
4477 for (unsigned i = 0; i != e; ++i)
4478 if (!isUndefOrEqual(Mask[i], i))
4480 for (unsigned i = 0; i != e; ++i)
4481 if (!isUndefOrEqual(Mask[e+i], i))
4486 /// isVEXTRACTIndex - Return true if the specified
4487 /// EXTRACT_SUBVECTOR operand specifies a vector extract that is
4488 /// suitable for instruction that extract 128 or 256 bit vectors
4489 static bool isVEXTRACTIndex(SDNode *N, unsigned vecWidth) {
4490 assert((vecWidth == 128 || vecWidth == 256) && "Unexpected vector width");
4491 if (!isa<ConstantSDNode>(N->getOperand(1).getNode()))
4494 // The index should be aligned on a vecWidth-bit boundary.
4496 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
4498 MVT VT = N->getSimpleValueType(0);
4499 unsigned ElSize = VT.getVectorElementType().getSizeInBits();
4500 bool Result = (Index * ElSize) % vecWidth == 0;
4505 /// isVINSERTIndex - Return true if the specified INSERT_SUBVECTOR
4506 /// operand specifies a subvector insert that is suitable for input to
4507 /// insertion of 128 or 256-bit subvectors
4508 static bool isVINSERTIndex(SDNode *N, unsigned vecWidth) {
4509 assert((vecWidth == 128 || vecWidth == 256) && "Unexpected vector width");
4510 if (!isa<ConstantSDNode>(N->getOperand(2).getNode()))
4512 // The index should be aligned on a vecWidth-bit boundary.
4514 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
4516 MVT VT = N->getSimpleValueType(0);
4517 unsigned ElSize = VT.getVectorElementType().getSizeInBits();
4518 bool Result = (Index * ElSize) % vecWidth == 0;
4523 bool X86::isVINSERT128Index(SDNode *N) {
4524 return isVINSERTIndex(N, 128);
4527 bool X86::isVINSERT256Index(SDNode *N) {
4528 return isVINSERTIndex(N, 256);
4531 bool X86::isVEXTRACT128Index(SDNode *N) {
4532 return isVEXTRACTIndex(N, 128);
4535 bool X86::isVEXTRACT256Index(SDNode *N) {
4536 return isVEXTRACTIndex(N, 256);
4539 /// getShuffleSHUFImmediate - Return the appropriate immediate to shuffle
4540 /// the specified VECTOR_SHUFFLE mask with PSHUF* and SHUFP* instructions.
4541 /// Handles 128-bit and 256-bit.
4542 static unsigned getShuffleSHUFImmediate(ShuffleVectorSDNode *N) {
4543 MVT VT = N->getSimpleValueType(0);
4545 assert((VT.getSizeInBits() >= 128) &&
4546 "Unsupported vector type for PSHUF/SHUFP");
4548 // Handle 128 and 256-bit vector lengths. AVX defines PSHUF/SHUFP to operate
4549 // independently on 128-bit lanes.
4550 unsigned NumElts = VT.getVectorNumElements();
4551 unsigned NumLanes = VT.getSizeInBits()/128;
4552 unsigned NumLaneElts = NumElts/NumLanes;
4554 assert((NumLaneElts == 2 || NumLaneElts == 4 || NumLaneElts == 8) &&
4555 "Only supports 2, 4 or 8 elements per lane");
4557 unsigned Shift = (NumLaneElts >= 4) ? 1 : 0;
4559 for (unsigned i = 0; i != NumElts; ++i) {
4560 int Elt = N->getMaskElt(i);
4561 if (Elt < 0) continue;
4562 Elt &= NumLaneElts - 1;
4563 unsigned ShAmt = (i << Shift) % 8;
4564 Mask |= Elt << ShAmt;
4570 /// getShufflePSHUFHWImmediate - Return the appropriate immediate to shuffle
4571 /// the specified VECTOR_SHUFFLE mask with the PSHUFHW instruction.
4572 static unsigned getShufflePSHUFHWImmediate(ShuffleVectorSDNode *N) {
4573 MVT VT = N->getSimpleValueType(0);
4575 assert((VT == MVT::v8i16 || VT == MVT::v16i16) &&
4576 "Unsupported vector type for PSHUFHW");
4578 unsigned NumElts = VT.getVectorNumElements();
4581 for (unsigned l = 0; l != NumElts; l += 8) {
4582 // 8 nodes per lane, but we only care about the last 4.
4583 for (unsigned i = 0; i < 4; ++i) {
4584 int Elt = N->getMaskElt(l+i+4);
4585 if (Elt < 0) continue;
4586 Elt &= 0x3; // only 2-bits.
4587 Mask |= Elt << (i * 2);
4594 /// getShufflePSHUFLWImmediate - Return the appropriate immediate to shuffle
4595 /// the specified VECTOR_SHUFFLE mask with the PSHUFLW instruction.
4596 static unsigned getShufflePSHUFLWImmediate(ShuffleVectorSDNode *N) {
4597 MVT VT = N->getSimpleValueType(0);
4599 assert((VT == MVT::v8i16 || VT == MVT::v16i16) &&
4600 "Unsupported vector type for PSHUFHW");
4602 unsigned NumElts = VT.getVectorNumElements();
4605 for (unsigned l = 0; l != NumElts; l += 8) {
4606 // 8 nodes per lane, but we only care about the first 4.
4607 for (unsigned i = 0; i < 4; ++i) {
4608 int Elt = N->getMaskElt(l+i);
4609 if (Elt < 0) continue;
4610 Elt &= 0x3; // only 2-bits
4611 Mask |= Elt << (i * 2);
4618 /// getShufflePALIGNRImmediate - Return the appropriate immediate to shuffle
4619 /// the specified VECTOR_SHUFFLE mask with the PALIGNR instruction.
4620 static unsigned getShufflePALIGNRImmediate(ShuffleVectorSDNode *SVOp) {
4621 MVT VT = SVOp->getSimpleValueType(0);
4622 unsigned EltSize = VT.is512BitVector() ? 1 :
4623 VT.getVectorElementType().getSizeInBits() >> 3;
4625 unsigned NumElts = VT.getVectorNumElements();
4626 unsigned NumLanes = VT.is512BitVector() ? 1 : VT.getSizeInBits()/128;
4627 unsigned NumLaneElts = NumElts/NumLanes;
4631 for (i = 0; i != NumElts; ++i) {
4632 Val = SVOp->getMaskElt(i);
4636 if (Val >= (int)NumElts)
4637 Val -= NumElts - NumLaneElts;
4639 assert(Val - i > 0 && "PALIGNR imm should be positive");
4640 return (Val - i) * EltSize;
4643 static unsigned getExtractVEXTRACTImmediate(SDNode *N, unsigned vecWidth) {
4644 assert((vecWidth == 128 || vecWidth == 256) && "Unsupported vector width");
4645 if (!isa<ConstantSDNode>(N->getOperand(1).getNode()))
4646 llvm_unreachable("Illegal extract subvector for VEXTRACT");
4649 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
4651 MVT VecVT = N->getOperand(0).getSimpleValueType();
4652 MVT ElVT = VecVT.getVectorElementType();
4654 unsigned NumElemsPerChunk = vecWidth / ElVT.getSizeInBits();
4655 return Index / NumElemsPerChunk;
4658 static unsigned getInsertVINSERTImmediate(SDNode *N, unsigned vecWidth) {
4659 assert((vecWidth == 128 || vecWidth == 256) && "Unsupported vector width");
4660 if (!isa<ConstantSDNode>(N->getOperand(2).getNode()))
4661 llvm_unreachable("Illegal insert subvector for VINSERT");
4664 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
4666 MVT VecVT = N->getSimpleValueType(0);
4667 MVT ElVT = VecVT.getVectorElementType();
4669 unsigned NumElemsPerChunk = vecWidth / ElVT.getSizeInBits();
4670 return Index / NumElemsPerChunk;
4673 /// getExtractVEXTRACT128Immediate - Return the appropriate immediate
4674 /// to extract the specified EXTRACT_SUBVECTOR index with VEXTRACTF128
4675 /// and VINSERTI128 instructions.
4676 unsigned X86::getExtractVEXTRACT128Immediate(SDNode *N) {
4677 return getExtractVEXTRACTImmediate(N, 128);
4680 /// getExtractVEXTRACT256Immediate - Return the appropriate immediate
4681 /// to extract the specified EXTRACT_SUBVECTOR index with VEXTRACTF64x4
4682 /// and VINSERTI64x4 instructions.
4683 unsigned X86::getExtractVEXTRACT256Immediate(SDNode *N) {
4684 return getExtractVEXTRACTImmediate(N, 256);
4687 /// getInsertVINSERT128Immediate - Return the appropriate immediate
4688 /// to insert at the specified INSERT_SUBVECTOR index with VINSERTF128
4689 /// and VINSERTI128 instructions.
4690 unsigned X86::getInsertVINSERT128Immediate(SDNode *N) {
4691 return getInsertVINSERTImmediate(N, 128);
4694 /// getInsertVINSERT256Immediate - Return the appropriate immediate
4695 /// to insert at the specified INSERT_SUBVECTOR index with VINSERTF46x4
4696 /// and VINSERTI64x4 instructions.
4697 unsigned X86::getInsertVINSERT256Immediate(SDNode *N) {
4698 return getInsertVINSERTImmediate(N, 256);
4701 /// isZero - Returns true if Elt is a constant integer zero
4702 static bool isZero(SDValue V) {
4703 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V);
4704 return C && C->isNullValue();
4707 /// isZeroNode - Returns true if Elt is a constant zero or a floating point
4709 bool X86::isZeroNode(SDValue Elt) {
4712 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Elt))
4713 return CFP->getValueAPF().isPosZero();
4717 /// CommuteVectorShuffle - Swap vector_shuffle operands as well as values in
4718 /// their permute mask.
4719 static SDValue CommuteVectorShuffle(ShuffleVectorSDNode *SVOp,
4720 SelectionDAG &DAG) {
4721 MVT VT = SVOp->getSimpleValueType(0);
4722 unsigned NumElems = VT.getVectorNumElements();
4723 SmallVector<int, 8> MaskVec;
4725 for (unsigned i = 0; i != NumElems; ++i) {
4726 int Idx = SVOp->getMaskElt(i);
4728 if (Idx < (int)NumElems)
4733 MaskVec.push_back(Idx);
4735 return DAG.getVectorShuffle(VT, SDLoc(SVOp), SVOp->getOperand(1),
4736 SVOp->getOperand(0), &MaskVec[0]);
4739 /// ShouldXformToMOVHLPS - Return true if the node should be transformed to
4740 /// match movhlps. The lower half elements should come from upper half of
4741 /// V1 (and in order), and the upper half elements should come from the upper
4742 /// half of V2 (and in order).
4743 static bool ShouldXformToMOVHLPS(ArrayRef<int> Mask, MVT VT) {
4744 if (!VT.is128BitVector())
4746 if (VT.getVectorNumElements() != 4)
4748 for (unsigned i = 0, e = 2; i != e; ++i)
4749 if (!isUndefOrEqual(Mask[i], i+2))
4751 for (unsigned i = 2; i != 4; ++i)
4752 if (!isUndefOrEqual(Mask[i], i+4))
4757 /// isScalarLoadToVector - Returns true if the node is a scalar load that
4758 /// is promoted to a vector. It also returns the LoadSDNode by reference if
4760 static bool isScalarLoadToVector(SDNode *N, LoadSDNode **LD = nullptr) {
4761 if (N->getOpcode() != ISD::SCALAR_TO_VECTOR)
4763 N = N->getOperand(0).getNode();
4764 if (!ISD::isNON_EXTLoad(N))
4767 *LD = cast<LoadSDNode>(N);
4771 // Test whether the given value is a vector value which will be legalized
4773 static bool WillBeConstantPoolLoad(SDNode *N) {
4774 if (N->getOpcode() != ISD::BUILD_VECTOR)
4777 // Check for any non-constant elements.
4778 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
4779 switch (N->getOperand(i).getNode()->getOpcode()) {
4781 case ISD::ConstantFP:
4788 // Vectors of all-zeros and all-ones are materialized with special
4789 // instructions rather than being loaded.
4790 return !ISD::isBuildVectorAllZeros(N) &&
4791 !ISD::isBuildVectorAllOnes(N);
4794 /// ShouldXformToMOVLP{S|D} - Return true if the node should be transformed to
4795 /// match movlp{s|d}. The lower half elements should come from lower half of
4796 /// V1 (and in order), and the upper half elements should come from the upper
4797 /// half of V2 (and in order). And since V1 will become the source of the
4798 /// MOVLP, it must be either a vector load or a scalar load to vector.
4799 static bool ShouldXformToMOVLP(SDNode *V1, SDNode *V2,
4800 ArrayRef<int> Mask, MVT VT) {
4801 if (!VT.is128BitVector())
4804 if (!ISD::isNON_EXTLoad(V1) && !isScalarLoadToVector(V1))
4806 // Is V2 is a vector load, don't do this transformation. We will try to use
4807 // load folding shufps op.
4808 if (ISD::isNON_EXTLoad(V2) || WillBeConstantPoolLoad(V2))
4811 unsigned NumElems = VT.getVectorNumElements();
4813 if (NumElems != 2 && NumElems != 4)
4815 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
4816 if (!isUndefOrEqual(Mask[i], i))
4818 for (unsigned i = NumElems/2, e = NumElems; i != e; ++i)
4819 if (!isUndefOrEqual(Mask[i], i+NumElems))
4824 /// isSplatVector - Returns true if N is a BUILD_VECTOR node whose elements are
4826 static bool isSplatVector(SDNode *N) {
4827 if (N->getOpcode() != ISD::BUILD_VECTOR)
4830 SDValue SplatValue = N->getOperand(0);
4831 for (unsigned i = 1, e = N->getNumOperands(); i != e; ++i)
4832 if (N->getOperand(i) != SplatValue)
4837 /// isZeroShuffle - Returns true if N is a VECTOR_SHUFFLE that can be resolved
4838 /// to an zero vector.
4839 /// FIXME: move to dag combiner / method on ShuffleVectorSDNode
4840 static bool isZeroShuffle(ShuffleVectorSDNode *N) {
4841 SDValue V1 = N->getOperand(0);
4842 SDValue V2 = N->getOperand(1);
4843 unsigned NumElems = N->getValueType(0).getVectorNumElements();
4844 for (unsigned i = 0; i != NumElems; ++i) {
4845 int Idx = N->getMaskElt(i);
4846 if (Idx >= (int)NumElems) {
4847 unsigned Opc = V2.getOpcode();
4848 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V2.getNode()))
4850 if (Opc != ISD::BUILD_VECTOR ||
4851 !X86::isZeroNode(V2.getOperand(Idx-NumElems)))
4853 } else if (Idx >= 0) {
4854 unsigned Opc = V1.getOpcode();
4855 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V1.getNode()))
4857 if (Opc != ISD::BUILD_VECTOR ||
4858 !X86::isZeroNode(V1.getOperand(Idx)))
4865 /// getZeroVector - Returns a vector of specified type with all zero elements.
4867 static SDValue getZeroVector(EVT VT, const X86Subtarget *Subtarget,
4868 SelectionDAG &DAG, SDLoc dl) {
4869 assert(VT.isVector() && "Expected a vector type");
4871 // Always build SSE zero vectors as <4 x i32> bitcasted
4872 // to their dest type. This ensures they get CSE'd.
4874 if (VT.is128BitVector()) { // SSE
4875 if (Subtarget->hasSSE2()) { // SSE2
4876 SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
4877 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4879 SDValue Cst = DAG.getTargetConstantFP(+0.0, MVT::f32);
4880 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4f32, Cst, Cst, Cst, Cst);
4882 } else if (VT.is256BitVector()) { // AVX
4883 if (Subtarget->hasInt256()) { // AVX2
4884 SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
4885 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4886 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops);
4888 // 256-bit logic and arithmetic instructions in AVX are all
4889 // floating-point, no support for integer ops. Emit fp zeroed vectors.
4890 SDValue Cst = DAG.getTargetConstantFP(+0.0, MVT::f32);
4891 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4892 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8f32, Ops);
4894 } else if (VT.is512BitVector()) { // AVX-512
4895 SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
4896 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst,
4897 Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4898 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v16i32, Ops);
4899 } else if (VT.getScalarType() == MVT::i1) {
4900 assert(VT.getVectorNumElements() <= 16 && "Unexpected vector type");
4901 SDValue Cst = DAG.getTargetConstant(0, MVT::i1);
4902 SmallVector<SDValue, 16> Ops(VT.getVectorNumElements(), Cst);
4903 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
4905 llvm_unreachable("Unexpected vector type");
4907 return DAG.getNode(ISD::BITCAST, dl, VT, Vec);
4910 /// getOnesVector - Returns a vector of specified type with all bits set.
4911 /// Always build ones vectors as <4 x i32> or <8 x i32>. For 256-bit types with
4912 /// no AVX2 supprt, use two <4 x i32> inserted in a <8 x i32> appropriately.
4913 /// Then bitcast to their original type, ensuring they get CSE'd.
4914 static SDValue getOnesVector(MVT VT, bool HasInt256, SelectionDAG &DAG,
4916 assert(VT.isVector() && "Expected a vector type");
4918 SDValue Cst = DAG.getTargetConstant(~0U, MVT::i32);
4920 if (VT.is256BitVector()) {
4921 if (HasInt256) { // AVX2
4922 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4923 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops);
4925 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4926 Vec = Concat128BitVectors(Vec, Vec, MVT::v8i32, 8, DAG, dl);
4928 } else if (VT.is128BitVector()) {
4929 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4931 llvm_unreachable("Unexpected vector type");
4933 return DAG.getNode(ISD::BITCAST, dl, VT, Vec);
4936 /// NormalizeMask - V2 is a splat, modify the mask (if needed) so all elements
4937 /// that point to V2 points to its first element.
4938 static void NormalizeMask(SmallVectorImpl<int> &Mask, unsigned NumElems) {
4939 for (unsigned i = 0; i != NumElems; ++i) {
4940 if (Mask[i] > (int)NumElems) {
4946 /// getMOVLMask - Returns a vector_shuffle mask for an movs{s|d}, movd
4947 /// operation of specified width.
4948 static SDValue getMOVL(SelectionDAG &DAG, SDLoc dl, EVT VT, SDValue V1,
4950 unsigned NumElems = VT.getVectorNumElements();
4951 SmallVector<int, 8> Mask;
4952 Mask.push_back(NumElems);
4953 for (unsigned i = 1; i != NumElems; ++i)
4955 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
4958 /// getUnpackl - Returns a vector_shuffle node for an unpackl operation.
4959 static SDValue getUnpackl(SelectionDAG &DAG, SDLoc dl, MVT VT, SDValue V1,
4961 unsigned NumElems = VT.getVectorNumElements();
4962 SmallVector<int, 8> Mask;
4963 for (unsigned i = 0, e = NumElems/2; i != e; ++i) {
4965 Mask.push_back(i + NumElems);
4967 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
4970 /// getUnpackh - Returns a vector_shuffle node for an unpackh operation.
4971 static SDValue getUnpackh(SelectionDAG &DAG, SDLoc dl, MVT VT, SDValue V1,
4973 unsigned NumElems = VT.getVectorNumElements();
4974 SmallVector<int, 8> Mask;
4975 for (unsigned i = 0, Half = NumElems/2; i != Half; ++i) {
4976 Mask.push_back(i + Half);
4977 Mask.push_back(i + NumElems + Half);
4979 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
4982 // PromoteSplati8i16 - All i16 and i8 vector types can't be used directly by
4983 // a generic shuffle instruction because the target has no such instructions.
4984 // Generate shuffles which repeat i16 and i8 several times until they can be
4985 // represented by v4f32 and then be manipulated by target suported shuffles.
4986 static SDValue PromoteSplati8i16(SDValue V, SelectionDAG &DAG, int &EltNo) {
4987 MVT VT = V.getSimpleValueType();
4988 int NumElems = VT.getVectorNumElements();
4991 while (NumElems > 4) {
4992 if (EltNo < NumElems/2) {
4993 V = getUnpackl(DAG, dl, VT, V, V);
4995 V = getUnpackh(DAG, dl, VT, V, V);
4996 EltNo -= NumElems/2;
5003 /// getLegalSplat - Generate a legal splat with supported x86 shuffles
5004 static SDValue getLegalSplat(SelectionDAG &DAG, SDValue V, int EltNo) {
5005 MVT VT = V.getSimpleValueType();
5008 if (VT.is128BitVector()) {
5009 V = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V);
5010 int SplatMask[4] = { EltNo, EltNo, EltNo, EltNo };
5011 V = DAG.getVectorShuffle(MVT::v4f32, dl, V, DAG.getUNDEF(MVT::v4f32),
5013 } else if (VT.is256BitVector()) {
5014 // To use VPERMILPS to splat scalars, the second half of indicies must
5015 // refer to the higher part, which is a duplication of the lower one,
5016 // because VPERMILPS can only handle in-lane permutations.
5017 int SplatMask[8] = { EltNo, EltNo, EltNo, EltNo,
5018 EltNo+4, EltNo+4, EltNo+4, EltNo+4 };
5020 V = DAG.getNode(ISD::BITCAST, dl, MVT::v8f32, V);
5021 V = DAG.getVectorShuffle(MVT::v8f32, dl, V, DAG.getUNDEF(MVT::v8f32),
5024 llvm_unreachable("Vector size not supported");
5026 return DAG.getNode(ISD::BITCAST, dl, VT, V);
5029 /// PromoteSplat - Splat is promoted to target supported vector shuffles.
5030 static SDValue PromoteSplat(ShuffleVectorSDNode *SV, SelectionDAG &DAG) {
5031 MVT SrcVT = SV->getSimpleValueType(0);
5032 SDValue V1 = SV->getOperand(0);
5035 int EltNo = SV->getSplatIndex();
5036 int NumElems = SrcVT.getVectorNumElements();
5037 bool Is256BitVec = SrcVT.is256BitVector();
5039 assert(((SrcVT.is128BitVector() && NumElems > 4) || Is256BitVec) &&
5040 "Unknown how to promote splat for type");
5042 // Extract the 128-bit part containing the splat element and update
5043 // the splat element index when it refers to the higher register.
5045 V1 = Extract128BitVector(V1, EltNo, DAG, dl);
5046 if (EltNo >= NumElems/2)
5047 EltNo -= NumElems/2;
5050 // All i16 and i8 vector types can't be used directly by a generic shuffle
5051 // instruction because the target has no such instruction. Generate shuffles
5052 // which repeat i16 and i8 several times until they fit in i32, and then can
5053 // be manipulated by target suported shuffles.
5054 MVT EltVT = SrcVT.getVectorElementType();
5055 if (EltVT == MVT::i8 || EltVT == MVT::i16)
5056 V1 = PromoteSplati8i16(V1, DAG, EltNo);
5058 // Recreate the 256-bit vector and place the same 128-bit vector
5059 // into the low and high part. This is necessary because we want
5060 // to use VPERM* to shuffle the vectors
5062 V1 = DAG.getNode(ISD::CONCAT_VECTORS, dl, SrcVT, V1, V1);
5065 return getLegalSplat(DAG, V1, EltNo);
5068 /// getShuffleVectorZeroOrUndef - Return a vector_shuffle of the specified
5069 /// vector of zero or undef vector. This produces a shuffle where the low
5070 /// element of V2 is swizzled into the zero/undef vector, landing at element
5071 /// Idx. This produces a shuffle mask like 4,1,2,3 (idx=0) or 0,1,2,4 (idx=3).
5072 static SDValue getShuffleVectorZeroOrUndef(SDValue V2, unsigned Idx,
5074 const X86Subtarget *Subtarget,
5075 SelectionDAG &DAG) {
5076 MVT VT = V2.getSimpleValueType();
5078 ? getZeroVector(VT, Subtarget, DAG, SDLoc(V2)) : DAG.getUNDEF(VT);
5079 unsigned NumElems = VT.getVectorNumElements();
5080 SmallVector<int, 16> MaskVec;
5081 for (unsigned i = 0; i != NumElems; ++i)
5082 // If this is the insertion idx, put the low elt of V2 here.
5083 MaskVec.push_back(i == Idx ? NumElems : i);
5084 return DAG.getVectorShuffle(VT, SDLoc(V2), V1, V2, &MaskVec[0]);
5087 /// getTargetShuffleMask - Calculates the shuffle mask corresponding to the
5088 /// target specific opcode. Returns true if the Mask could be calculated.
5089 /// Sets IsUnary to true if only uses one source.
5090 static bool getTargetShuffleMask(SDNode *N, MVT VT,
5091 SmallVectorImpl<int> &Mask, bool &IsUnary) {
5092 unsigned NumElems = VT.getVectorNumElements();
5096 switch(N->getOpcode()) {
5098 ImmN = N->getOperand(N->getNumOperands()-1);
5099 DecodeSHUFPMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5101 case X86ISD::UNPCKH:
5102 DecodeUNPCKHMask(VT, Mask);
5104 case X86ISD::UNPCKL:
5105 DecodeUNPCKLMask(VT, Mask);
5107 case X86ISD::MOVHLPS:
5108 DecodeMOVHLPSMask(NumElems, Mask);
5110 case X86ISD::MOVLHPS:
5111 DecodeMOVLHPSMask(NumElems, Mask);
5113 case X86ISD::PALIGNR:
5114 ImmN = N->getOperand(N->getNumOperands()-1);
5115 DecodePALIGNRMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5117 case X86ISD::PSHUFD:
5118 case X86ISD::VPERMILP:
5119 ImmN = N->getOperand(N->getNumOperands()-1);
5120 DecodePSHUFMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5123 case X86ISD::PSHUFHW:
5124 ImmN = N->getOperand(N->getNumOperands()-1);
5125 DecodePSHUFHWMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5128 case X86ISD::PSHUFLW:
5129 ImmN = N->getOperand(N->getNumOperands()-1);
5130 DecodePSHUFLWMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5133 case X86ISD::VPERMI:
5134 ImmN = N->getOperand(N->getNumOperands()-1);
5135 DecodeVPERMMask(cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5139 case X86ISD::MOVSD: {
5140 // The index 0 always comes from the first element of the second source,
5141 // this is why MOVSS and MOVSD are used in the first place. The other
5142 // elements come from the other positions of the first source vector
5143 Mask.push_back(NumElems);
5144 for (unsigned i = 1; i != NumElems; ++i) {
5149 case X86ISD::VPERM2X128:
5150 ImmN = N->getOperand(N->getNumOperands()-1);
5151 DecodeVPERM2X128Mask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5152 if (Mask.empty()) return false;
5154 case X86ISD::MOVDDUP:
5155 case X86ISD::MOVLHPD:
5156 case X86ISD::MOVLPD:
5157 case X86ISD::MOVLPS:
5158 case X86ISD::MOVSHDUP:
5159 case X86ISD::MOVSLDUP:
5160 // Not yet implemented
5162 default: llvm_unreachable("unknown target shuffle node");
5168 /// getShuffleScalarElt - Returns the scalar element that will make up the ith
5169 /// element of the result of the vector shuffle.
5170 static SDValue getShuffleScalarElt(SDNode *N, unsigned Index, SelectionDAG &DAG,
5173 return SDValue(); // Limit search depth.
5175 SDValue V = SDValue(N, 0);
5176 EVT VT = V.getValueType();
5177 unsigned Opcode = V.getOpcode();
5179 // Recurse into ISD::VECTOR_SHUFFLE node to find scalars.
5180 if (const ShuffleVectorSDNode *SV = dyn_cast<ShuffleVectorSDNode>(N)) {
5181 int Elt = SV->getMaskElt(Index);
5184 return DAG.getUNDEF(VT.getVectorElementType());
5186 unsigned NumElems = VT.getVectorNumElements();
5187 SDValue NewV = (Elt < (int)NumElems) ? SV->getOperand(0)
5188 : SV->getOperand(1);
5189 return getShuffleScalarElt(NewV.getNode(), Elt % NumElems, DAG, Depth+1);
5192 // Recurse into target specific vector shuffles to find scalars.
5193 if (isTargetShuffle(Opcode)) {
5194 MVT ShufVT = V.getSimpleValueType();
5195 unsigned NumElems = ShufVT.getVectorNumElements();
5196 SmallVector<int, 16> ShuffleMask;
5199 if (!getTargetShuffleMask(N, ShufVT, ShuffleMask, IsUnary))
5202 int Elt = ShuffleMask[Index];
5204 return DAG.getUNDEF(ShufVT.getVectorElementType());
5206 SDValue NewV = (Elt < (int)NumElems) ? N->getOperand(0)
5208 return getShuffleScalarElt(NewV.getNode(), Elt % NumElems, DAG,
5212 // Actual nodes that may contain scalar elements
5213 if (Opcode == ISD::BITCAST) {
5214 V = V.getOperand(0);
5215 EVT SrcVT = V.getValueType();
5216 unsigned NumElems = VT.getVectorNumElements();
5218 if (!SrcVT.isVector() || SrcVT.getVectorNumElements() != NumElems)
5222 if (V.getOpcode() == ISD::SCALAR_TO_VECTOR)
5223 return (Index == 0) ? V.getOperand(0)
5224 : DAG.getUNDEF(VT.getVectorElementType());
5226 if (V.getOpcode() == ISD::BUILD_VECTOR)
5227 return V.getOperand(Index);
5232 /// getNumOfConsecutiveZeros - Return the number of elements of a vector
5233 /// shuffle operation which come from a consecutively from a zero. The
5234 /// search can start in two different directions, from left or right.
5235 /// We count undefs as zeros until PreferredNum is reached.
5236 static unsigned getNumOfConsecutiveZeros(ShuffleVectorSDNode *SVOp,
5237 unsigned NumElems, bool ZerosFromLeft,
5239 unsigned PreferredNum = -1U) {
5240 unsigned NumZeros = 0;
5241 for (unsigned i = 0; i != NumElems; ++i) {
5242 unsigned Index = ZerosFromLeft ? i : NumElems - i - 1;
5243 SDValue Elt = getShuffleScalarElt(SVOp, Index, DAG, 0);
5247 if (X86::isZeroNode(Elt))
5249 else if (Elt.getOpcode() == ISD::UNDEF) // Undef as zero up to PreferredNum.
5250 NumZeros = std::min(NumZeros + 1, PreferredNum);
5258 /// isShuffleMaskConsecutive - Check if the shuffle mask indicies [MaskI, MaskE)
5259 /// correspond consecutively to elements from one of the vector operands,
5260 /// starting from its index OpIdx. Also tell OpNum which source vector operand.
5262 bool isShuffleMaskConsecutive(ShuffleVectorSDNode *SVOp,
5263 unsigned MaskI, unsigned MaskE, unsigned OpIdx,
5264 unsigned NumElems, unsigned &OpNum) {
5265 bool SeenV1 = false;
5266 bool SeenV2 = false;
5268 for (unsigned i = MaskI; i != MaskE; ++i, ++OpIdx) {
5269 int Idx = SVOp->getMaskElt(i);
5270 // Ignore undef indicies
5274 if (Idx < (int)NumElems)
5279 // Only accept consecutive elements from the same vector
5280 if ((Idx % NumElems != OpIdx) || (SeenV1 && SeenV2))
5284 OpNum = SeenV1 ? 0 : 1;
5288 /// isVectorShiftRight - Returns true if the shuffle can be implemented as a
5289 /// logical left shift of a vector.
5290 static bool isVectorShiftRight(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
5291 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
5293 SVOp->getSimpleValueType(0).getVectorNumElements();
5294 unsigned NumZeros = getNumOfConsecutiveZeros(
5295 SVOp, NumElems, false /* check zeros from right */, DAG,
5296 SVOp->getMaskElt(0));
5302 // Considering the elements in the mask that are not consecutive zeros,
5303 // check if they consecutively come from only one of the source vectors.
5305 // V1 = {X, A, B, C} 0
5307 // vector_shuffle V1, V2 <1, 2, 3, X>
5309 if (!isShuffleMaskConsecutive(SVOp,
5310 0, // Mask Start Index
5311 NumElems-NumZeros, // Mask End Index(exclusive)
5312 NumZeros, // Where to start looking in the src vector
5313 NumElems, // Number of elements in vector
5314 OpSrc)) // Which source operand ?
5319 ShVal = SVOp->getOperand(OpSrc);
5323 /// isVectorShiftLeft - Returns true if the shuffle can be implemented as a
5324 /// logical left shift of a vector.
5325 static bool isVectorShiftLeft(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
5326 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
5328 SVOp->getSimpleValueType(0).getVectorNumElements();
5329 unsigned NumZeros = getNumOfConsecutiveZeros(
5330 SVOp, NumElems, true /* check zeros from left */, DAG,
5331 NumElems - SVOp->getMaskElt(NumElems - 1) - 1);
5337 // Considering the elements in the mask that are not consecutive zeros,
5338 // check if they consecutively come from only one of the source vectors.
5340 // 0 { A, B, X, X } = V2
5342 // vector_shuffle V1, V2 <X, X, 4, 5>
5344 if (!isShuffleMaskConsecutive(SVOp,
5345 NumZeros, // Mask Start Index
5346 NumElems, // Mask End Index(exclusive)
5347 0, // Where to start looking in the src vector
5348 NumElems, // Number of elements in vector
5349 OpSrc)) // Which source operand ?
5354 ShVal = SVOp->getOperand(OpSrc);
5358 /// isVectorShift - Returns true if the shuffle can be implemented as a
5359 /// logical left or right shift of a vector.
5360 static bool isVectorShift(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
5361 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
5362 // Although the logic below support any bitwidth size, there are no
5363 // shift instructions which handle more than 128-bit vectors.
5364 if (!SVOp->getSimpleValueType(0).is128BitVector())
5367 if (isVectorShiftLeft(SVOp, DAG, isLeft, ShVal, ShAmt) ||
5368 isVectorShiftRight(SVOp, DAG, isLeft, ShVal, ShAmt))
5374 /// LowerBuildVectorv16i8 - Custom lower build_vector of v16i8.
5376 static SDValue LowerBuildVectorv16i8(SDValue Op, unsigned NonZeros,
5377 unsigned NumNonZero, unsigned NumZero,
5379 const X86Subtarget* Subtarget,
5380 const TargetLowering &TLI) {
5387 for (unsigned i = 0; i < 16; ++i) {
5388 bool ThisIsNonZero = (NonZeros & (1 << i)) != 0;
5389 if (ThisIsNonZero && First) {
5391 V = getZeroVector(MVT::v8i16, Subtarget, DAG, dl);
5393 V = DAG.getUNDEF(MVT::v8i16);
5398 SDValue ThisElt, LastElt;
5399 bool LastIsNonZero = (NonZeros & (1 << (i-1))) != 0;
5400 if (LastIsNonZero) {
5401 LastElt = DAG.getNode(ISD::ZERO_EXTEND, dl,
5402 MVT::i16, Op.getOperand(i-1));
5404 if (ThisIsNonZero) {
5405 ThisElt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, Op.getOperand(i));
5406 ThisElt = DAG.getNode(ISD::SHL, dl, MVT::i16,
5407 ThisElt, DAG.getConstant(8, MVT::i8));
5409 ThisElt = DAG.getNode(ISD::OR, dl, MVT::i16, ThisElt, LastElt);
5413 if (ThisElt.getNode())
5414 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, V, ThisElt,
5415 DAG.getIntPtrConstant(i/2));
5419 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V);
5422 /// LowerBuildVectorv8i16 - Custom lower build_vector of v8i16.
5424 static SDValue LowerBuildVectorv8i16(SDValue Op, unsigned NonZeros,
5425 unsigned NumNonZero, unsigned NumZero,
5427 const X86Subtarget* Subtarget,
5428 const TargetLowering &TLI) {
5435 for (unsigned i = 0; i < 8; ++i) {
5436 bool isNonZero = (NonZeros & (1 << i)) != 0;
5440 V = getZeroVector(MVT::v8i16, Subtarget, DAG, dl);
5442 V = DAG.getUNDEF(MVT::v8i16);
5445 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl,
5446 MVT::v8i16, V, Op.getOperand(i),
5447 DAG.getIntPtrConstant(i));
5454 /// LowerBuildVectorv4x32 - Custom lower build_vector of v4i32 or v4f32.
5455 static SDValue LowerBuildVectorv4x32(SDValue Op, unsigned NumElems,
5456 unsigned NonZeros, unsigned NumNonZero,
5457 unsigned NumZero, SelectionDAG &DAG,
5458 const X86Subtarget *Subtarget,
5459 const TargetLowering &TLI) {
5460 // We know there's at least one non-zero element
5461 unsigned FirstNonZeroIdx = 0;
5462 SDValue FirstNonZero = Op->getOperand(FirstNonZeroIdx);
5463 while (FirstNonZero.getOpcode() == ISD::UNDEF ||
5464 X86::isZeroNode(FirstNonZero)) {
5466 FirstNonZero = Op->getOperand(FirstNonZeroIdx);
5469 if (FirstNonZero.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
5470 !isa<ConstantSDNode>(FirstNonZero.getOperand(1)))
5473 SDValue V = FirstNonZero.getOperand(0);
5474 MVT VVT = V.getSimpleValueType();
5475 if (!Subtarget->hasSSE41() || (VVT != MVT::v4f32 && VVT != MVT::v4i32))
5478 unsigned FirstNonZeroDst =
5479 cast<ConstantSDNode>(FirstNonZero.getOperand(1))->getZExtValue();
5480 unsigned CorrectIdx = FirstNonZeroDst == FirstNonZeroIdx;
5481 unsigned IncorrectIdx = CorrectIdx ? -1U : FirstNonZeroIdx;
5482 unsigned IncorrectDst = CorrectIdx ? -1U : FirstNonZeroDst;
5484 for (unsigned Idx = FirstNonZeroIdx + 1; Idx < NumElems; ++Idx) {
5485 SDValue Elem = Op.getOperand(Idx);
5486 if (Elem.getOpcode() == ISD::UNDEF || X86::isZeroNode(Elem))
5489 // TODO: What else can be here? Deal with it.
5490 if (Elem.getOpcode() != ISD::EXTRACT_VECTOR_ELT)
5493 // TODO: Some optimizations are still possible here
5494 // ex: Getting one element from a vector, and the rest from another.
5495 if (Elem.getOperand(0) != V)
5498 unsigned Dst = cast<ConstantSDNode>(Elem.getOperand(1))->getZExtValue();
5501 else if (IncorrectIdx == -1U) {
5505 // There was already one element with an incorrect index.
5506 // We can't optimize this case to an insertps.
5510 if (NumNonZero == CorrectIdx || NumNonZero == CorrectIdx + 1) {
5512 EVT VT = Op.getSimpleValueType();
5513 unsigned ElementMoveMask = 0;
5514 if (IncorrectIdx == -1U)
5515 ElementMoveMask = FirstNonZeroIdx << 6 | FirstNonZeroIdx << 4;
5517 ElementMoveMask = IncorrectDst << 6 | IncorrectIdx << 4;
5519 SDValue InsertpsMask =
5520 DAG.getIntPtrConstant(ElementMoveMask | (~NonZeros & 0xf));
5521 return DAG.getNode(X86ISD::INSERTPS, dl, VT, V, V, InsertpsMask);
5527 /// getVShift - Return a vector logical shift node.
5529 static SDValue getVShift(bool isLeft, EVT VT, SDValue SrcOp,
5530 unsigned NumBits, SelectionDAG &DAG,
5531 const TargetLowering &TLI, SDLoc dl) {
5532 assert(VT.is128BitVector() && "Unknown type for VShift");
5533 EVT ShVT = MVT::v2i64;
5534 unsigned Opc = isLeft ? X86ISD::VSHLDQ : X86ISD::VSRLDQ;
5535 SrcOp = DAG.getNode(ISD::BITCAST, dl, ShVT, SrcOp);
5536 return DAG.getNode(ISD::BITCAST, dl, VT,
5537 DAG.getNode(Opc, dl, ShVT, SrcOp,
5538 DAG.getConstant(NumBits,
5539 TLI.getScalarShiftAmountTy(SrcOp.getValueType()))));
5543 LowerAsSplatVectorLoad(SDValue SrcOp, MVT VT, SDLoc dl, SelectionDAG &DAG) {
5545 // Check if the scalar load can be widened into a vector load. And if
5546 // the address is "base + cst" see if the cst can be "absorbed" into
5547 // the shuffle mask.
5548 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(SrcOp)) {
5549 SDValue Ptr = LD->getBasePtr();
5550 if (!ISD::isNormalLoad(LD) || LD->isVolatile())
5552 EVT PVT = LD->getValueType(0);
5553 if (PVT != MVT::i32 && PVT != MVT::f32)
5558 if (FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr)) {
5559 FI = FINode->getIndex();
5561 } else if (DAG.isBaseWithConstantOffset(Ptr) &&
5562 isa<FrameIndexSDNode>(Ptr.getOperand(0))) {
5563 FI = cast<FrameIndexSDNode>(Ptr.getOperand(0))->getIndex();
5564 Offset = Ptr.getConstantOperandVal(1);
5565 Ptr = Ptr.getOperand(0);
5570 // FIXME: 256-bit vector instructions don't require a strict alignment,
5571 // improve this code to support it better.
5572 unsigned RequiredAlign = VT.getSizeInBits()/8;
5573 SDValue Chain = LD->getChain();
5574 // Make sure the stack object alignment is at least 16 or 32.
5575 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
5576 if (DAG.InferPtrAlignment(Ptr) < RequiredAlign) {
5577 if (MFI->isFixedObjectIndex(FI)) {
5578 // Can't change the alignment. FIXME: It's possible to compute
5579 // the exact stack offset and reference FI + adjust offset instead.
5580 // If someone *really* cares about this. That's the way to implement it.
5583 MFI->setObjectAlignment(FI, RequiredAlign);
5587 // (Offset % 16 or 32) must be multiple of 4. Then address is then
5588 // Ptr + (Offset & ~15).
5591 if ((Offset % RequiredAlign) & 3)
5593 int64_t StartOffset = Offset & ~(RequiredAlign-1);
5595 Ptr = DAG.getNode(ISD::ADD, SDLoc(Ptr), Ptr.getValueType(),
5596 Ptr,DAG.getConstant(StartOffset, Ptr.getValueType()));
5598 int EltNo = (Offset - StartOffset) >> 2;
5599 unsigned NumElems = VT.getVectorNumElements();
5601 EVT NVT = EVT::getVectorVT(*DAG.getContext(), PVT, NumElems);
5602 SDValue V1 = DAG.getLoad(NVT, dl, Chain, Ptr,
5603 LD->getPointerInfo().getWithOffset(StartOffset),
5604 false, false, false, 0);
5606 SmallVector<int, 8> Mask;
5607 for (unsigned i = 0; i != NumElems; ++i)
5608 Mask.push_back(EltNo);
5610 return DAG.getVectorShuffle(NVT, dl, V1, DAG.getUNDEF(NVT), &Mask[0]);
5616 /// EltsFromConsecutiveLoads - Given the initializing elements 'Elts' of a
5617 /// vector of type 'VT', see if the elements can be replaced by a single large
5618 /// load which has the same value as a build_vector whose operands are 'elts'.
5620 /// Example: <load i32 *a, load i32 *a+4, undef, undef> -> zextload a
5622 /// FIXME: we'd also like to handle the case where the last elements are zero
5623 /// rather than undef via VZEXT_LOAD, but we do not detect that case today.
5624 /// There's even a handy isZeroNode for that purpose.
5625 static SDValue EltsFromConsecutiveLoads(EVT VT, SmallVectorImpl<SDValue> &Elts,
5626 SDLoc &DL, SelectionDAG &DAG,
5627 bool isAfterLegalize) {
5628 EVT EltVT = VT.getVectorElementType();
5629 unsigned NumElems = Elts.size();
5631 LoadSDNode *LDBase = nullptr;
5632 unsigned LastLoadedElt = -1U;
5634 // For each element in the initializer, see if we've found a load or an undef.
5635 // If we don't find an initial load element, or later load elements are
5636 // non-consecutive, bail out.
5637 for (unsigned i = 0; i < NumElems; ++i) {
5638 SDValue Elt = Elts[i];
5640 if (!Elt.getNode() ||
5641 (Elt.getOpcode() != ISD::UNDEF && !ISD::isNON_EXTLoad(Elt.getNode())))
5644 if (Elt.getNode()->getOpcode() == ISD::UNDEF)
5646 LDBase = cast<LoadSDNode>(Elt.getNode());
5650 if (Elt.getOpcode() == ISD::UNDEF)
5653 LoadSDNode *LD = cast<LoadSDNode>(Elt);
5654 if (!DAG.isConsecutiveLoad(LD, LDBase, EltVT.getSizeInBits()/8, i))
5659 // If we have found an entire vector of loads and undefs, then return a large
5660 // load of the entire vector width starting at the base pointer. If we found
5661 // consecutive loads for the low half, generate a vzext_load node.
5662 if (LastLoadedElt == NumElems - 1) {
5664 if (isAfterLegalize &&
5665 !DAG.getTargetLoweringInfo().isOperationLegal(ISD::LOAD, VT))
5668 SDValue NewLd = SDValue();
5670 if (DAG.InferPtrAlignment(LDBase->getBasePtr()) >= 16)
5671 NewLd = DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(),
5672 LDBase->getPointerInfo(),
5673 LDBase->isVolatile(), LDBase->isNonTemporal(),
5674 LDBase->isInvariant(), 0);
5675 NewLd = DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(),
5676 LDBase->getPointerInfo(),
5677 LDBase->isVolatile(), LDBase->isNonTemporal(),
5678 LDBase->isInvariant(), LDBase->getAlignment());
5680 if (LDBase->hasAnyUseOfValue(1)) {
5681 SDValue NewChain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
5683 SDValue(NewLd.getNode(), 1));
5684 DAG.ReplaceAllUsesOfValueWith(SDValue(LDBase, 1), NewChain);
5685 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(LDBase, 1),
5686 SDValue(NewLd.getNode(), 1));
5691 if (NumElems == 4 && LastLoadedElt == 1 &&
5692 DAG.getTargetLoweringInfo().isTypeLegal(MVT::v2i64)) {
5693 SDVTList Tys = DAG.getVTList(MVT::v2i64, MVT::Other);
5694 SDValue Ops[] = { LDBase->getChain(), LDBase->getBasePtr() };
5696 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, DL, Tys, Ops, MVT::i64,
5697 LDBase->getPointerInfo(),
5698 LDBase->getAlignment(),
5699 false/*isVolatile*/, true/*ReadMem*/,
5702 // Make sure the newly-created LOAD is in the same position as LDBase in
5703 // terms of dependency. We create a TokenFactor for LDBase and ResNode, and
5704 // update uses of LDBase's output chain to use the TokenFactor.
5705 if (LDBase->hasAnyUseOfValue(1)) {
5706 SDValue NewChain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
5707 SDValue(LDBase, 1), SDValue(ResNode.getNode(), 1));
5708 DAG.ReplaceAllUsesOfValueWith(SDValue(LDBase, 1), NewChain);
5709 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(LDBase, 1),
5710 SDValue(ResNode.getNode(), 1));
5713 return DAG.getNode(ISD::BITCAST, DL, VT, ResNode);
5718 /// LowerVectorBroadcast - Attempt to use the vbroadcast instruction
5719 /// to generate a splat value for the following cases:
5720 /// 1. A splat BUILD_VECTOR which uses a single scalar load, or a constant.
5721 /// 2. A splat shuffle which uses a scalar_to_vector node which comes from
5722 /// a scalar load, or a constant.
5723 /// The VBROADCAST node is returned when a pattern is found,
5724 /// or SDValue() otherwise.
5725 static SDValue LowerVectorBroadcast(SDValue Op, const X86Subtarget* Subtarget,
5726 SelectionDAG &DAG) {
5727 if (!Subtarget->hasFp256())
5730 MVT VT = Op.getSimpleValueType();
5733 assert((VT.is128BitVector() || VT.is256BitVector() || VT.is512BitVector()) &&
5734 "Unsupported vector type for broadcast.");
5739 switch (Op.getOpcode()) {
5741 // Unknown pattern found.
5744 case ISD::BUILD_VECTOR: {
5745 // The BUILD_VECTOR node must be a splat.
5746 if (!isSplatVector(Op.getNode()))
5749 Ld = Op.getOperand(0);
5750 ConstSplatVal = (Ld.getOpcode() == ISD::Constant ||
5751 Ld.getOpcode() == ISD::ConstantFP);
5753 // The suspected load node has several users. Make sure that all
5754 // of its users are from the BUILD_VECTOR node.
5755 // Constants may have multiple users.
5756 if (!ConstSplatVal && !Ld->hasNUsesOfValue(VT.getVectorNumElements(), 0))
5761 case ISD::VECTOR_SHUFFLE: {
5762 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
5764 // Shuffles must have a splat mask where the first element is
5766 if ((!SVOp->isSplat()) || SVOp->getMaskElt(0) != 0)
5769 SDValue Sc = Op.getOperand(0);
5770 if (Sc.getOpcode() != ISD::SCALAR_TO_VECTOR &&
5771 Sc.getOpcode() != ISD::BUILD_VECTOR) {
5773 if (!Subtarget->hasInt256())
5776 // Use the register form of the broadcast instruction available on AVX2.
5777 if (VT.getSizeInBits() >= 256)
5778 Sc = Extract128BitVector(Sc, 0, DAG, dl);
5779 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Sc);
5782 Ld = Sc.getOperand(0);
5783 ConstSplatVal = (Ld.getOpcode() == ISD::Constant ||
5784 Ld.getOpcode() == ISD::ConstantFP);
5786 // The scalar_to_vector node and the suspected
5787 // load node must have exactly one user.
5788 // Constants may have multiple users.
5790 // AVX-512 has register version of the broadcast
5791 bool hasRegVer = Subtarget->hasAVX512() && VT.is512BitVector() &&
5792 Ld.getValueType().getSizeInBits() >= 32;
5793 if (!ConstSplatVal && ((!Sc.hasOneUse() || !Ld.hasOneUse()) &&
5800 bool IsGE256 = (VT.getSizeInBits() >= 256);
5802 // Handle the broadcasting a single constant scalar from the constant pool
5803 // into a vector. On Sandybridge it is still better to load a constant vector
5804 // from the constant pool and not to broadcast it from a scalar.
5805 if (ConstSplatVal && Subtarget->hasInt256()) {
5806 EVT CVT = Ld.getValueType();
5807 assert(!CVT.isVector() && "Must not broadcast a vector type");
5808 unsigned ScalarSize = CVT.getSizeInBits();
5810 if (ScalarSize == 32 || (IsGE256 && ScalarSize == 64)) {
5811 const Constant *C = nullptr;
5812 if (ConstantSDNode *CI = dyn_cast<ConstantSDNode>(Ld))
5813 C = CI->getConstantIntValue();
5814 else if (ConstantFPSDNode *CF = dyn_cast<ConstantFPSDNode>(Ld))
5815 C = CF->getConstantFPValue();
5817 assert(C && "Invalid constant type");
5819 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
5820 SDValue CP = DAG.getConstantPool(C, TLI.getPointerTy());
5821 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
5822 Ld = DAG.getLoad(CVT, dl, DAG.getEntryNode(), CP,
5823 MachinePointerInfo::getConstantPool(),
5824 false, false, false, Alignment);
5826 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5830 bool IsLoad = ISD::isNormalLoad(Ld.getNode());
5831 unsigned ScalarSize = Ld.getValueType().getSizeInBits();
5833 // Handle AVX2 in-register broadcasts.
5834 if (!IsLoad && Subtarget->hasInt256() &&
5835 (ScalarSize == 32 || (IsGE256 && ScalarSize == 64)))
5836 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5838 // The scalar source must be a normal load.
5842 if (ScalarSize == 32 || (IsGE256 && ScalarSize == 64))
5843 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5845 // The integer check is needed for the 64-bit into 128-bit so it doesn't match
5846 // double since there is no vbroadcastsd xmm
5847 if (Subtarget->hasInt256() && Ld.getValueType().isInteger()) {
5848 if (ScalarSize == 8 || ScalarSize == 16 || ScalarSize == 64)
5849 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5852 // Unsupported broadcast.
5856 /// \brief For an EXTRACT_VECTOR_ELT with a constant index return the real
5857 /// underlying vector and index.
5859 /// Modifies \p ExtractedFromVec to the real vector and returns the real
5861 static int getUnderlyingExtractedFromVec(SDValue &ExtractedFromVec,
5863 int Idx = cast<ConstantSDNode>(ExtIdx)->getZExtValue();
5864 if (!isa<ShuffleVectorSDNode>(ExtractedFromVec))
5867 // For 256-bit vectors, LowerEXTRACT_VECTOR_ELT_SSE4 may have already
5869 // (extract_vector_elt (v8f32 %vreg1), Constant<6>)
5871 // (extract_vector_elt (vector_shuffle<2,u,u,u>
5872 // (extract_subvector (v8f32 %vreg0), Constant<4>),
5875 // In this case the vector is the extract_subvector expression and the index
5876 // is 2, as specified by the shuffle.
5877 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(ExtractedFromVec);
5878 SDValue ShuffleVec = SVOp->getOperand(0);
5879 MVT ShuffleVecVT = ShuffleVec.getSimpleValueType();
5880 assert(ShuffleVecVT.getVectorElementType() ==
5881 ExtractedFromVec.getSimpleValueType().getVectorElementType());
5883 int ShuffleIdx = SVOp->getMaskElt(Idx);
5884 if (isUndefOrInRange(ShuffleIdx, 0, ShuffleVecVT.getVectorNumElements())) {
5885 ExtractedFromVec = ShuffleVec;
5891 static SDValue buildFromShuffleMostly(SDValue Op, SelectionDAG &DAG) {
5892 MVT VT = Op.getSimpleValueType();
5894 // Skip if insert_vec_elt is not supported.
5895 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
5896 if (!TLI.isOperationLegalOrCustom(ISD::INSERT_VECTOR_ELT, VT))
5900 unsigned NumElems = Op.getNumOperands();
5904 SmallVector<unsigned, 4> InsertIndices;
5905 SmallVector<int, 8> Mask(NumElems, -1);
5907 for (unsigned i = 0; i != NumElems; ++i) {
5908 unsigned Opc = Op.getOperand(i).getOpcode();
5910 if (Opc == ISD::UNDEF)
5913 if (Opc != ISD::EXTRACT_VECTOR_ELT) {
5914 // Quit if more than 1 elements need inserting.
5915 if (InsertIndices.size() > 1)
5918 InsertIndices.push_back(i);
5922 SDValue ExtractedFromVec = Op.getOperand(i).getOperand(0);
5923 SDValue ExtIdx = Op.getOperand(i).getOperand(1);
5924 // Quit if non-constant index.
5925 if (!isa<ConstantSDNode>(ExtIdx))
5927 int Idx = getUnderlyingExtractedFromVec(ExtractedFromVec, ExtIdx);
5929 // Quit if extracted from vector of different type.
5930 if (ExtractedFromVec.getValueType() != VT)
5933 if (!VecIn1.getNode())
5934 VecIn1 = ExtractedFromVec;
5935 else if (VecIn1 != ExtractedFromVec) {
5936 if (!VecIn2.getNode())
5937 VecIn2 = ExtractedFromVec;
5938 else if (VecIn2 != ExtractedFromVec)
5939 // Quit if more than 2 vectors to shuffle
5943 if (ExtractedFromVec == VecIn1)
5945 else if (ExtractedFromVec == VecIn2)
5946 Mask[i] = Idx + NumElems;
5949 if (!VecIn1.getNode())
5952 VecIn2 = VecIn2.getNode() ? VecIn2 : DAG.getUNDEF(VT);
5953 SDValue NV = DAG.getVectorShuffle(VT, DL, VecIn1, VecIn2, &Mask[0]);
5954 for (unsigned i = 0, e = InsertIndices.size(); i != e; ++i) {
5955 unsigned Idx = InsertIndices[i];
5956 NV = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, VT, NV, Op.getOperand(Idx),
5957 DAG.getIntPtrConstant(Idx));
5963 // Lower BUILD_VECTOR operation for v8i1 and v16i1 types.
5965 X86TargetLowering::LowerBUILD_VECTORvXi1(SDValue Op, SelectionDAG &DAG) const {
5967 MVT VT = Op.getSimpleValueType();
5968 assert((VT.getVectorElementType() == MVT::i1) && (VT.getSizeInBits() <= 16) &&
5969 "Unexpected type in LowerBUILD_VECTORvXi1!");
5972 if (ISD::isBuildVectorAllZeros(Op.getNode())) {
5973 SDValue Cst = DAG.getTargetConstant(0, MVT::i1);
5974 SmallVector<SDValue, 16> Ops(VT.getVectorNumElements(), Cst);
5975 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
5978 if (ISD::isBuildVectorAllOnes(Op.getNode())) {
5979 SDValue Cst = DAG.getTargetConstant(1, MVT::i1);
5980 SmallVector<SDValue, 16> Ops(VT.getVectorNumElements(), Cst);
5981 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
5984 bool AllContants = true;
5985 uint64_t Immediate = 0;
5986 int NonConstIdx = -1;
5987 bool IsSplat = true;
5988 unsigned NumNonConsts = 0;
5989 unsigned NumConsts = 0;
5990 for (unsigned idx = 0, e = Op.getNumOperands(); idx < e; ++idx) {
5991 SDValue In = Op.getOperand(idx);
5992 if (In.getOpcode() == ISD::UNDEF)
5994 if (!isa<ConstantSDNode>(In)) {
5995 AllContants = false;
6001 if (cast<ConstantSDNode>(In)->getZExtValue())
6002 Immediate |= (1ULL << idx);
6004 if (In != Op.getOperand(0))
6009 SDValue FullMask = DAG.getNode(ISD::BITCAST, dl, MVT::v16i1,
6010 DAG.getConstant(Immediate, MVT::i16));
6011 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, FullMask,
6012 DAG.getIntPtrConstant(0));
6015 if (NumNonConsts == 1 && NonConstIdx != 0) {
6018 SDValue VecAsImm = DAG.getConstant(Immediate,
6019 MVT::getIntegerVT(VT.getSizeInBits()));
6020 DstVec = DAG.getNode(ISD::BITCAST, dl, VT, VecAsImm);
6023 DstVec = DAG.getUNDEF(VT);
6024 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, DstVec,
6025 Op.getOperand(NonConstIdx),
6026 DAG.getIntPtrConstant(NonConstIdx));
6028 if (!IsSplat && (NonConstIdx != 0))
6029 llvm_unreachable("Unsupported BUILD_VECTOR operation");
6030 MVT SelectVT = (VT == MVT::v16i1)? MVT::i16 : MVT::i8;
6033 Select = DAG.getNode(ISD::SELECT, dl, SelectVT, Op.getOperand(0),
6034 DAG.getConstant(-1, SelectVT),
6035 DAG.getConstant(0, SelectVT));
6037 Select = DAG.getNode(ISD::SELECT, dl, SelectVT, Op.getOperand(0),
6038 DAG.getConstant((Immediate | 1), SelectVT),
6039 DAG.getConstant(Immediate, SelectVT));
6040 return DAG.getNode(ISD::BITCAST, dl, VT, Select);
6044 X86TargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const {
6047 MVT VT = Op.getSimpleValueType();
6048 MVT ExtVT = VT.getVectorElementType();
6049 unsigned NumElems = Op.getNumOperands();
6051 // Generate vectors for predicate vectors.
6052 if (VT.getScalarType() == MVT::i1 && Subtarget->hasAVX512())
6053 return LowerBUILD_VECTORvXi1(Op, DAG);
6055 // Vectors containing all zeros can be matched by pxor and xorps later
6056 if (ISD::isBuildVectorAllZeros(Op.getNode())) {
6057 // Canonicalize this to <4 x i32> to 1) ensure the zero vectors are CSE'd
6058 // and 2) ensure that i64 scalars are eliminated on x86-32 hosts.
6059 if (VT == MVT::v4i32 || VT == MVT::v8i32 || VT == MVT::v16i32)
6062 return getZeroVector(VT, Subtarget, DAG, dl);
6065 // Vectors containing all ones can be matched by pcmpeqd on 128-bit width
6066 // vectors or broken into v4i32 operations on 256-bit vectors. AVX2 can use
6067 // vpcmpeqd on 256-bit vectors.
6068 if (Subtarget->hasSSE2() && ISD::isBuildVectorAllOnes(Op.getNode())) {
6069 if (VT == MVT::v4i32 || (VT == MVT::v8i32 && Subtarget->hasInt256()))
6072 if (!VT.is512BitVector())
6073 return getOnesVector(VT, Subtarget->hasInt256(), DAG, dl);
6076 SDValue Broadcast = LowerVectorBroadcast(Op, Subtarget, DAG);
6077 if (Broadcast.getNode())
6080 unsigned EVTBits = ExtVT.getSizeInBits();
6082 unsigned NumZero = 0;
6083 unsigned NumNonZero = 0;
6084 unsigned NonZeros = 0;
6085 bool IsAllConstants = true;
6086 SmallSet<SDValue, 8> Values;
6087 for (unsigned i = 0; i < NumElems; ++i) {
6088 SDValue Elt = Op.getOperand(i);
6089 if (Elt.getOpcode() == ISD::UNDEF)
6092 if (Elt.getOpcode() != ISD::Constant &&
6093 Elt.getOpcode() != ISD::ConstantFP)
6094 IsAllConstants = false;
6095 if (X86::isZeroNode(Elt))
6098 NonZeros |= (1 << i);
6103 // All undef vector. Return an UNDEF. All zero vectors were handled above.
6104 if (NumNonZero == 0)
6105 return DAG.getUNDEF(VT);
6107 // Special case for single non-zero, non-undef, element.
6108 if (NumNonZero == 1) {
6109 unsigned Idx = countTrailingZeros(NonZeros);
6110 SDValue Item = Op.getOperand(Idx);
6112 // If this is an insertion of an i64 value on x86-32, and if the top bits of
6113 // the value are obviously zero, truncate the value to i32 and do the
6114 // insertion that way. Only do this if the value is non-constant or if the
6115 // value is a constant being inserted into element 0. It is cheaper to do
6116 // a constant pool load than it is to do a movd + shuffle.
6117 if (ExtVT == MVT::i64 && !Subtarget->is64Bit() &&
6118 (!IsAllConstants || Idx == 0)) {
6119 if (DAG.MaskedValueIsZero(Item, APInt::getBitsSet(64, 32, 64))) {
6121 assert(VT == MVT::v2i64 && "Expected an SSE value type!");
6122 EVT VecVT = MVT::v4i32;
6123 unsigned VecElts = 4;
6125 // Truncate the value (which may itself be a constant) to i32, and
6126 // convert it to a vector with movd (S2V+shuffle to zero extend).
6127 Item = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Item);
6128 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Item);
6129 Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
6131 // Now we have our 32-bit value zero extended in the low element of
6132 // a vector. If Idx != 0, swizzle it into place.
6134 SmallVector<int, 4> Mask;
6135 Mask.push_back(Idx);
6136 for (unsigned i = 1; i != VecElts; ++i)
6138 Item = DAG.getVectorShuffle(VecVT, dl, Item, DAG.getUNDEF(VecVT),
6141 return DAG.getNode(ISD::BITCAST, dl, VT, Item);
6145 // If we have a constant or non-constant insertion into the low element of
6146 // a vector, we can do this with SCALAR_TO_VECTOR + shuffle of zero into
6147 // the rest of the elements. This will be matched as movd/movq/movss/movsd
6148 // depending on what the source datatype is.
6151 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
6153 if (ExtVT == MVT::i32 || ExtVT == MVT::f32 || ExtVT == MVT::f64 ||
6154 (ExtVT == MVT::i64 && Subtarget->is64Bit())) {
6155 if (VT.is256BitVector() || VT.is512BitVector()) {
6156 SDValue ZeroVec = getZeroVector(VT, Subtarget, DAG, dl);
6157 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, ZeroVec,
6158 Item, DAG.getIntPtrConstant(0));
6160 assert(VT.is128BitVector() && "Expected an SSE value type!");
6161 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
6162 // Turn it into a MOVL (i.e. movss, movsd, or movd) to a zero vector.
6163 return getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
6166 if (ExtVT == MVT::i16 || ExtVT == MVT::i8) {
6167 Item = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Item);
6168 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, Item);
6169 if (VT.is256BitVector()) {
6170 SDValue ZeroVec = getZeroVector(MVT::v8i32, Subtarget, DAG, dl);
6171 Item = Insert128BitVector(ZeroVec, Item, 0, DAG, dl);
6173 assert(VT.is128BitVector() && "Expected an SSE value type!");
6174 Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
6176 return DAG.getNode(ISD::BITCAST, dl, VT, Item);
6180 // Is it a vector logical left shift?
6181 if (NumElems == 2 && Idx == 1 &&
6182 X86::isZeroNode(Op.getOperand(0)) &&
6183 !X86::isZeroNode(Op.getOperand(1))) {
6184 unsigned NumBits = VT.getSizeInBits();
6185 return getVShift(true, VT,
6186 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
6187 VT, Op.getOperand(1)),
6188 NumBits/2, DAG, *this, dl);
6191 if (IsAllConstants) // Otherwise, it's better to do a constpool load.
6194 // Otherwise, if this is a vector with i32 or f32 elements, and the element
6195 // is a non-constant being inserted into an element other than the low one,
6196 // we can't use a constant pool load. Instead, use SCALAR_TO_VECTOR (aka
6197 // movd/movss) to move this into the low element, then shuffle it into
6199 if (EVTBits == 32) {
6200 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
6202 // Turn it into a shuffle of zero and zero-extended scalar to vector.
6203 Item = getShuffleVectorZeroOrUndef(Item, 0, NumZero > 0, Subtarget, DAG);
6204 SmallVector<int, 8> MaskVec;
6205 for (unsigned i = 0; i != NumElems; ++i)
6206 MaskVec.push_back(i == Idx ? 0 : 1);
6207 return DAG.getVectorShuffle(VT, dl, Item, DAG.getUNDEF(VT), &MaskVec[0]);
6211 // Splat is obviously ok. Let legalizer expand it to a shuffle.
6212 if (Values.size() == 1) {
6213 if (EVTBits == 32) {
6214 // Instead of a shuffle like this:
6215 // shuffle (scalar_to_vector (load (ptr + 4))), undef, <0, 0, 0, 0>
6216 // Check if it's possible to issue this instead.
6217 // shuffle (vload ptr)), undef, <1, 1, 1, 1>
6218 unsigned Idx = countTrailingZeros(NonZeros);
6219 SDValue Item = Op.getOperand(Idx);
6220 if (Op.getNode()->isOnlyUserOf(Item.getNode()))
6221 return LowerAsSplatVectorLoad(Item, VT, dl, DAG);
6226 // A vector full of immediates; various special cases are already
6227 // handled, so this is best done with a single constant-pool load.
6231 // For AVX-length vectors, build the individual 128-bit pieces and use
6232 // shuffles to put them in place.
6233 if (VT.is256BitVector() || VT.is512BitVector()) {
6234 SmallVector<SDValue, 64> V;
6235 for (unsigned i = 0; i != NumElems; ++i)
6236 V.push_back(Op.getOperand(i));
6238 EVT HVT = EVT::getVectorVT(*DAG.getContext(), ExtVT, NumElems/2);
6240 // Build both the lower and upper subvector.
6241 SDValue Lower = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT,
6242 makeArrayRef(&V[0], NumElems/2));
6243 SDValue Upper = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT,
6244 makeArrayRef(&V[NumElems / 2], NumElems/2));
6246 // Recreate the wider vector with the lower and upper part.
6247 if (VT.is256BitVector())
6248 return Concat128BitVectors(Lower, Upper, VT, NumElems, DAG, dl);
6249 return Concat256BitVectors(Lower, Upper, VT, NumElems, DAG, dl);
6252 // Let legalizer expand 2-wide build_vectors.
6253 if (EVTBits == 64) {
6254 if (NumNonZero == 1) {
6255 // One half is zero or undef.
6256 unsigned Idx = countTrailingZeros(NonZeros);
6257 SDValue V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT,
6258 Op.getOperand(Idx));
6259 return getShuffleVectorZeroOrUndef(V2, Idx, true, Subtarget, DAG);
6264 // If element VT is < 32 bits, convert it to inserts into a zero vector.
6265 if (EVTBits == 8 && NumElems == 16) {
6266 SDValue V = LowerBuildVectorv16i8(Op, NonZeros,NumNonZero,NumZero, DAG,
6268 if (V.getNode()) return V;
6271 if (EVTBits == 16 && NumElems == 8) {
6272 SDValue V = LowerBuildVectorv8i16(Op, NonZeros,NumNonZero,NumZero, DAG,
6274 if (V.getNode()) return V;
6277 // If element VT is == 32 bits and has 4 elems, try to generate an INSERTPS
6278 if (EVTBits == 32 && NumElems == 4) {
6279 SDValue V = LowerBuildVectorv4x32(Op, NumElems, NonZeros, NumNonZero,
6280 NumZero, DAG, Subtarget, *this);
6285 // If element VT is == 32 bits, turn it into a number of shuffles.
6286 SmallVector<SDValue, 8> V(NumElems);
6287 if (NumElems == 4 && NumZero > 0) {
6288 for (unsigned i = 0; i < 4; ++i) {
6289 bool isZero = !(NonZeros & (1 << i));
6291 V[i] = getZeroVector(VT, Subtarget, DAG, dl);
6293 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
6296 for (unsigned i = 0; i < 2; ++i) {
6297 switch ((NonZeros & (0x3 << i*2)) >> (i*2)) {
6300 V[i] = V[i*2]; // Must be a zero vector.
6303 V[i] = getMOVL(DAG, dl, VT, V[i*2+1], V[i*2]);
6306 V[i] = getMOVL(DAG, dl, VT, V[i*2], V[i*2+1]);
6309 V[i] = getUnpackl(DAG, dl, VT, V[i*2], V[i*2+1]);
6314 bool Reverse1 = (NonZeros & 0x3) == 2;
6315 bool Reverse2 = ((NonZeros & (0x3 << 2)) >> 2) == 2;
6319 static_cast<int>(Reverse2 ? NumElems+1 : NumElems),
6320 static_cast<int>(Reverse2 ? NumElems : NumElems+1)
6322 return DAG.getVectorShuffle(VT, dl, V[0], V[1], &MaskVec[0]);
6325 if (Values.size() > 1 && VT.is128BitVector()) {
6326 // Check for a build vector of consecutive loads.
6327 for (unsigned i = 0; i < NumElems; ++i)
6328 V[i] = Op.getOperand(i);
6330 // Check for elements which are consecutive loads.
6331 SDValue LD = EltsFromConsecutiveLoads(VT, V, dl, DAG, false);
6335 // Check for a build vector from mostly shuffle plus few inserting.
6336 SDValue Sh = buildFromShuffleMostly(Op, DAG);
6340 // For SSE 4.1, use insertps to put the high elements into the low element.
6341 if (getSubtarget()->hasSSE41()) {
6343 if (Op.getOperand(0).getOpcode() != ISD::UNDEF)
6344 Result = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(0));
6346 Result = DAG.getUNDEF(VT);
6348 for (unsigned i = 1; i < NumElems; ++i) {
6349 if (Op.getOperand(i).getOpcode() == ISD::UNDEF) continue;
6350 Result = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Result,
6351 Op.getOperand(i), DAG.getIntPtrConstant(i));
6356 // Otherwise, expand into a number of unpckl*, start by extending each of
6357 // our (non-undef) elements to the full vector width with the element in the
6358 // bottom slot of the vector (which generates no code for SSE).
6359 for (unsigned i = 0; i < NumElems; ++i) {
6360 if (Op.getOperand(i).getOpcode() != ISD::UNDEF)
6361 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
6363 V[i] = DAG.getUNDEF(VT);
6366 // Next, we iteratively mix elements, e.g. for v4f32:
6367 // Step 1: unpcklps 0, 2 ==> X: <?, ?, 2, 0>
6368 // : unpcklps 1, 3 ==> Y: <?, ?, 3, 1>
6369 // Step 2: unpcklps X, Y ==> <3, 2, 1, 0>
6370 unsigned EltStride = NumElems >> 1;
6371 while (EltStride != 0) {
6372 for (unsigned i = 0; i < EltStride; ++i) {
6373 // If V[i+EltStride] is undef and this is the first round of mixing,
6374 // then it is safe to just drop this shuffle: V[i] is already in the
6375 // right place, the one element (since it's the first round) being
6376 // inserted as undef can be dropped. This isn't safe for successive
6377 // rounds because they will permute elements within both vectors.
6378 if (V[i+EltStride].getOpcode() == ISD::UNDEF &&
6379 EltStride == NumElems/2)
6382 V[i] = getUnpackl(DAG, dl, VT, V[i], V[i + EltStride]);
6391 // LowerAVXCONCAT_VECTORS - 256-bit AVX can use the vinsertf128 instruction
6392 // to create 256-bit vectors from two other 128-bit ones.
6393 static SDValue LowerAVXCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
6395 MVT ResVT = Op.getSimpleValueType();
6397 assert((ResVT.is256BitVector() ||
6398 ResVT.is512BitVector()) && "Value type must be 256-/512-bit wide");
6400 SDValue V1 = Op.getOperand(0);
6401 SDValue V2 = Op.getOperand(1);
6402 unsigned NumElems = ResVT.getVectorNumElements();
6403 if(ResVT.is256BitVector())
6404 return Concat128BitVectors(V1, V2, ResVT, NumElems, DAG, dl);
6406 if (Op.getNumOperands() == 4) {
6407 MVT HalfVT = MVT::getVectorVT(ResVT.getScalarType(),
6408 ResVT.getVectorNumElements()/2);
6409 SDValue V3 = Op.getOperand(2);
6410 SDValue V4 = Op.getOperand(3);
6411 return Concat256BitVectors(Concat128BitVectors(V1, V2, HalfVT, NumElems/2, DAG, dl),
6412 Concat128BitVectors(V3, V4, HalfVT, NumElems/2, DAG, dl), ResVT, NumElems, DAG, dl);
6414 return Concat256BitVectors(V1, V2, ResVT, NumElems, DAG, dl);
6417 static SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
6418 MVT LLVM_ATTRIBUTE_UNUSED VT = Op.getSimpleValueType();
6419 assert((VT.is256BitVector() && Op.getNumOperands() == 2) ||
6420 (VT.is512BitVector() && (Op.getNumOperands() == 2 ||
6421 Op.getNumOperands() == 4)));
6423 // AVX can use the vinsertf128 instruction to create 256-bit vectors
6424 // from two other 128-bit ones.
6426 // 512-bit vector may contain 2 256-bit vectors or 4 128-bit vectors
6427 return LowerAVXCONCAT_VECTORS(Op, DAG);
6430 // Try to lower a shuffle node into a simple blend instruction.
6432 LowerVECTOR_SHUFFLEtoBlend(ShuffleVectorSDNode *SVOp,
6433 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
6434 SDValue V1 = SVOp->getOperand(0);
6435 SDValue V2 = SVOp->getOperand(1);
6437 MVT VT = SVOp->getSimpleValueType(0);
6438 MVT EltVT = VT.getVectorElementType();
6439 unsigned NumElems = VT.getVectorNumElements();
6441 // There is no blend with immediate in AVX-512.
6442 if (VT.is512BitVector())
6445 if (!Subtarget->hasSSE41() || EltVT == MVT::i8)
6447 if (!Subtarget->hasInt256() && VT == MVT::v16i16)
6450 // Check the mask for BLEND and build the value.
6451 unsigned MaskValue = 0;
6452 // There are 2 lanes if (NumElems > 8), and 1 lane otherwise.
6453 unsigned NumLanes = (NumElems-1)/8 + 1;
6454 unsigned NumElemsInLane = NumElems / NumLanes;
6456 // Blend for v16i16 should be symetric for the both lanes.
6457 for (unsigned i = 0; i < NumElemsInLane; ++i) {
6459 int SndLaneEltIdx = (NumLanes == 2) ?
6460 SVOp->getMaskElt(i + NumElemsInLane) : -1;
6461 int EltIdx = SVOp->getMaskElt(i);
6463 if ((EltIdx < 0 || EltIdx == (int)i) &&
6464 (SndLaneEltIdx < 0 || SndLaneEltIdx == (int)(i + NumElemsInLane)))
6467 if (((unsigned)EltIdx == (i + NumElems)) &&
6468 (SndLaneEltIdx < 0 ||
6469 (unsigned)SndLaneEltIdx == i + NumElems + NumElemsInLane))
6470 MaskValue |= (1<<i);
6475 // Convert i32 vectors to floating point if it is not AVX2.
6476 // AVX2 introduced VPBLENDD instruction for 128 and 256-bit vectors.
6478 if (EltVT == MVT::i64 || (EltVT == MVT::i32 && !Subtarget->hasInt256())) {
6479 BlendVT = MVT::getVectorVT(MVT::getFloatingPointVT(EltVT.getSizeInBits()),
6481 V1 = DAG.getNode(ISD::BITCAST, dl, VT, V1);
6482 V2 = DAG.getNode(ISD::BITCAST, dl, VT, V2);
6485 SDValue Ret = DAG.getNode(X86ISD::BLENDI, dl, BlendVT, V1, V2,
6486 DAG.getConstant(MaskValue, MVT::i32));
6487 return DAG.getNode(ISD::BITCAST, dl, VT, Ret);
6490 /// In vector type \p VT, return true if the element at index \p InputIdx
6491 /// falls on a different 128-bit lane than \p OutputIdx.
6492 static bool ShuffleCrosses128bitLane(MVT VT, unsigned InputIdx,
6493 unsigned OutputIdx) {
6494 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
6495 return InputIdx * EltSize / 128 != OutputIdx * EltSize / 128;
6498 /// Generate a PSHUFB if possible. Selects elements from \p V1 according to
6499 /// \p MaskVals. MaskVals[OutputIdx] = InputIdx specifies that we want to
6500 /// shuffle the element at InputIdx in V1 to OutputIdx in the result. If \p
6501 /// MaskVals refers to elements outside of \p V1 or is undef (-1), insert a
6503 static SDValue getPSHUFB(ArrayRef<int> MaskVals, SDValue V1, SDLoc &dl,
6504 SelectionDAG &DAG) {
6505 MVT VT = V1.getSimpleValueType();
6506 assert(VT.is128BitVector() || VT.is256BitVector());
6508 MVT EltVT = VT.getVectorElementType();
6509 unsigned EltSizeInBytes = EltVT.getSizeInBits() / 8;
6510 unsigned NumElts = VT.getVectorNumElements();
6512 SmallVector<SDValue, 32> PshufbMask;
6513 for (unsigned OutputIdx = 0; OutputIdx < NumElts; ++OutputIdx) {
6514 int InputIdx = MaskVals[OutputIdx];
6515 unsigned InputByteIdx;
6517 if (InputIdx < 0 || NumElts <= (unsigned)InputIdx)
6518 InputByteIdx = 0x80;
6520 // Cross lane is not allowed.
6521 if (ShuffleCrosses128bitLane(VT, InputIdx, OutputIdx))
6523 InputByteIdx = InputIdx * EltSizeInBytes;
6524 // Index is an byte offset within the 128-bit lane.
6525 InputByteIdx &= 0xf;
6528 for (unsigned j = 0; j < EltSizeInBytes; ++j) {
6529 PshufbMask.push_back(DAG.getConstant(InputByteIdx, MVT::i8));
6530 if (InputByteIdx != 0x80)
6535 MVT ShufVT = MVT::getVectorVT(MVT::i8, PshufbMask.size());
6537 V1 = DAG.getNode(ISD::BITCAST, dl, ShufVT, V1);
6538 return DAG.getNode(X86ISD::PSHUFB, dl, ShufVT, V1,
6539 DAG.getNode(ISD::BUILD_VECTOR, dl, ShufVT, PshufbMask));
6542 // v8i16 shuffles - Prefer shuffles in the following order:
6543 // 1. [all] pshuflw, pshufhw, optional move
6544 // 2. [ssse3] 1 x pshufb
6545 // 3. [ssse3] 2 x pshufb + 1 x por
6546 // 4. [all] mov + pshuflw + pshufhw + N x (pextrw + pinsrw)
6548 LowerVECTOR_SHUFFLEv8i16(SDValue Op, const X86Subtarget *Subtarget,
6549 SelectionDAG &DAG) {
6550 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
6551 SDValue V1 = SVOp->getOperand(0);
6552 SDValue V2 = SVOp->getOperand(1);
6554 SmallVector<int, 8> MaskVals;
6556 // Determine if more than 1 of the words in each of the low and high quadwords
6557 // of the result come from the same quadword of one of the two inputs. Undef
6558 // mask values count as coming from any quadword, for better codegen.
6560 // Lo/HiQuad[i] = j indicates how many words from the ith quad of the input
6561 // feeds this quad. For i, 0 and 1 refer to V1, 2 and 3 refer to V2.
6562 unsigned LoQuad[] = { 0, 0, 0, 0 };
6563 unsigned HiQuad[] = { 0, 0, 0, 0 };
6564 // Indices of quads used.
6565 std::bitset<4> InputQuads;
6566 for (unsigned i = 0; i < 8; ++i) {
6567 unsigned *Quad = i < 4 ? LoQuad : HiQuad;
6568 int EltIdx = SVOp->getMaskElt(i);
6569 MaskVals.push_back(EltIdx);
6578 InputQuads.set(EltIdx / 4);
6581 int BestLoQuad = -1;
6582 unsigned MaxQuad = 1;
6583 for (unsigned i = 0; i < 4; ++i) {
6584 if (LoQuad[i] > MaxQuad) {
6586 MaxQuad = LoQuad[i];
6590 int BestHiQuad = -1;
6592 for (unsigned i = 0; i < 4; ++i) {
6593 if (HiQuad[i] > MaxQuad) {
6595 MaxQuad = HiQuad[i];
6599 // For SSSE3, If all 8 words of the result come from only 1 quadword of each
6600 // of the two input vectors, shuffle them into one input vector so only a
6601 // single pshufb instruction is necessary. If there are more than 2 input
6602 // quads, disable the next transformation since it does not help SSSE3.
6603 bool V1Used = InputQuads[0] || InputQuads[1];
6604 bool V2Used = InputQuads[2] || InputQuads[3];
6605 if (Subtarget->hasSSSE3()) {
6606 if (InputQuads.count() == 2 && V1Used && V2Used) {
6607 BestLoQuad = InputQuads[0] ? 0 : 1;
6608 BestHiQuad = InputQuads[2] ? 2 : 3;
6610 if (InputQuads.count() > 2) {
6616 // If BestLoQuad or BestHiQuad are set, shuffle the quads together and update
6617 // the shuffle mask. If a quad is scored as -1, that means that it contains
6618 // words from all 4 input quadwords.
6620 if (BestLoQuad >= 0 || BestHiQuad >= 0) {
6622 BestLoQuad < 0 ? 0 : BestLoQuad,
6623 BestHiQuad < 0 ? 1 : BestHiQuad
6625 NewV = DAG.getVectorShuffle(MVT::v2i64, dl,
6626 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, V1),
6627 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, V2), &MaskV[0]);
6628 NewV = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, NewV);
6630 // Rewrite the MaskVals and assign NewV to V1 if NewV now contains all the
6631 // source words for the shuffle, to aid later transformations.
6632 bool AllWordsInNewV = true;
6633 bool InOrder[2] = { true, true };
6634 for (unsigned i = 0; i != 8; ++i) {
6635 int idx = MaskVals[i];
6637 InOrder[i/4] = false;
6638 if (idx < 0 || (idx/4) == BestLoQuad || (idx/4) == BestHiQuad)
6640 AllWordsInNewV = false;
6644 bool pshuflw = AllWordsInNewV, pshufhw = AllWordsInNewV;
6645 if (AllWordsInNewV) {
6646 for (int i = 0; i != 8; ++i) {
6647 int idx = MaskVals[i];
6650 idx = MaskVals[i] = (idx / 4) == BestLoQuad ? (idx & 3) : (idx & 3) + 4;
6651 if ((idx != i) && idx < 4)
6653 if ((idx != i) && idx > 3)
6662 // If we've eliminated the use of V2, and the new mask is a pshuflw or
6663 // pshufhw, that's as cheap as it gets. Return the new shuffle.
6664 if ((pshufhw && InOrder[0]) || (pshuflw && InOrder[1])) {
6665 unsigned Opc = pshufhw ? X86ISD::PSHUFHW : X86ISD::PSHUFLW;
6666 unsigned TargetMask = 0;
6667 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV,
6668 DAG.getUNDEF(MVT::v8i16), &MaskVals[0]);
6669 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode());
6670 TargetMask = pshufhw ? getShufflePSHUFHWImmediate(SVOp):
6671 getShufflePSHUFLWImmediate(SVOp);
6672 V1 = NewV.getOperand(0);
6673 return getTargetShuffleNode(Opc, dl, MVT::v8i16, V1, TargetMask, DAG);
6677 // Promote splats to a larger type which usually leads to more efficient code.
6678 // FIXME: Is this true if pshufb is available?
6679 if (SVOp->isSplat())
6680 return PromoteSplat(SVOp, DAG);
6682 // If we have SSSE3, and all words of the result are from 1 input vector,
6683 // case 2 is generated, otherwise case 3 is generated. If no SSSE3
6684 // is present, fall back to case 4.
6685 if (Subtarget->hasSSSE3()) {
6686 SmallVector<SDValue,16> pshufbMask;
6688 // If we have elements from both input vectors, set the high bit of the
6689 // shuffle mask element to zero out elements that come from V2 in the V1
6690 // mask, and elements that come from V1 in the V2 mask, so that the two
6691 // results can be OR'd together.
6692 bool TwoInputs = V1Used && V2Used;
6693 V1 = getPSHUFB(MaskVals, V1, dl, DAG);
6695 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
6697 // Calculate the shuffle mask for the second input, shuffle it, and
6698 // OR it with the first shuffled input.
6699 CommuteVectorShuffleMask(MaskVals, 8);
6700 V2 = getPSHUFB(MaskVals, V2, dl, DAG);
6701 V1 = DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
6702 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
6705 // If BestLoQuad >= 0, generate a pshuflw to put the low elements in order,
6706 // and update MaskVals with new element order.
6707 std::bitset<8> InOrder;
6708 if (BestLoQuad >= 0) {
6709 int MaskV[] = { -1, -1, -1, -1, 4, 5, 6, 7 };
6710 for (int i = 0; i != 4; ++i) {
6711 int idx = MaskVals[i];
6714 } else if ((idx / 4) == BestLoQuad) {
6719 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16),
6722 if (NewV.getOpcode() == ISD::VECTOR_SHUFFLE && Subtarget->hasSSE2()) {
6723 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode());
6724 NewV = getTargetShuffleNode(X86ISD::PSHUFLW, dl, MVT::v8i16,
6726 getShufflePSHUFLWImmediate(SVOp), DAG);
6730 // If BestHi >= 0, generate a pshufhw to put the high elements in order,
6731 // and update MaskVals with the new element order.
6732 if (BestHiQuad >= 0) {
6733 int MaskV[] = { 0, 1, 2, 3, -1, -1, -1, -1 };
6734 for (unsigned i = 4; i != 8; ++i) {
6735 int idx = MaskVals[i];
6738 } else if ((idx / 4) == BestHiQuad) {
6739 MaskV[i] = (idx & 3) + 4;
6743 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16),
6746 if (NewV.getOpcode() == ISD::VECTOR_SHUFFLE && Subtarget->hasSSE2()) {
6747 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode());
6748 NewV = getTargetShuffleNode(X86ISD::PSHUFHW, dl, MVT::v8i16,
6750 getShufflePSHUFHWImmediate(SVOp), DAG);
6754 // In case BestHi & BestLo were both -1, which means each quadword has a word
6755 // from each of the four input quadwords, calculate the InOrder bitvector now
6756 // before falling through to the insert/extract cleanup.
6757 if (BestLoQuad == -1 && BestHiQuad == -1) {
6759 for (int i = 0; i != 8; ++i)
6760 if (MaskVals[i] < 0 || MaskVals[i] == i)
6764 // The other elements are put in the right place using pextrw and pinsrw.
6765 for (unsigned i = 0; i != 8; ++i) {
6768 int EltIdx = MaskVals[i];
6771 SDValue ExtOp = (EltIdx < 8) ?
6772 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V1,
6773 DAG.getIntPtrConstant(EltIdx)) :
6774 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V2,
6775 DAG.getIntPtrConstant(EltIdx - 8));
6776 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, ExtOp,
6777 DAG.getIntPtrConstant(i));
6782 /// \brief v16i16 shuffles
6784 /// FIXME: We only support generation of a single pshufb currently. We can
6785 /// generalize the other applicable cases from LowerVECTOR_SHUFFLEv8i16 as
6786 /// well (e.g 2 x pshufb + 1 x por).
6788 LowerVECTOR_SHUFFLEv16i16(SDValue Op, SelectionDAG &DAG) {
6789 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
6790 SDValue V1 = SVOp->getOperand(0);
6791 SDValue V2 = SVOp->getOperand(1);
6794 if (V2.getOpcode() != ISD::UNDEF)
6797 SmallVector<int, 16> MaskVals(SVOp->getMask().begin(), SVOp->getMask().end());
6798 return getPSHUFB(MaskVals, V1, dl, DAG);
6801 // v16i8 shuffles - Prefer shuffles in the following order:
6802 // 1. [ssse3] 1 x pshufb
6803 // 2. [ssse3] 2 x pshufb + 1 x por
6804 // 3. [all] v8i16 shuffle + N x pextrw + rotate + pinsrw
6805 static SDValue LowerVECTOR_SHUFFLEv16i8(ShuffleVectorSDNode *SVOp,
6806 const X86Subtarget* Subtarget,
6807 SelectionDAG &DAG) {
6808 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
6809 SDValue V1 = SVOp->getOperand(0);
6810 SDValue V2 = SVOp->getOperand(1);
6812 ArrayRef<int> MaskVals = SVOp->getMask();
6814 // Promote splats to a larger type which usually leads to more efficient code.
6815 // FIXME: Is this true if pshufb is available?
6816 if (SVOp->isSplat())
6817 return PromoteSplat(SVOp, DAG);
6819 // If we have SSSE3, case 1 is generated when all result bytes come from
6820 // one of the inputs. Otherwise, case 2 is generated. If no SSSE3 is
6821 // present, fall back to case 3.
6823 // If SSSE3, use 1 pshufb instruction per vector with elements in the result.
6824 if (Subtarget->hasSSSE3()) {
6825 SmallVector<SDValue,16> pshufbMask;
6827 // If all result elements are from one input vector, then only translate
6828 // undef mask values to 0x80 (zero out result) in the pshufb mask.
6830 // Otherwise, we have elements from both input vectors, and must zero out
6831 // elements that come from V2 in the first mask, and V1 in the second mask
6832 // so that we can OR them together.
6833 for (unsigned i = 0; i != 16; ++i) {
6834 int EltIdx = MaskVals[i];
6835 if (EltIdx < 0 || EltIdx >= 16)
6837 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
6839 V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1,
6840 DAG.getNode(ISD::BUILD_VECTOR, dl,
6841 MVT::v16i8, pshufbMask));
6843 // As PSHUFB will zero elements with negative indices, it's safe to ignore
6844 // the 2nd operand if it's undefined or zero.
6845 if (V2.getOpcode() == ISD::UNDEF ||
6846 ISD::isBuildVectorAllZeros(V2.getNode()))
6849 // Calculate the shuffle mask for the second input, shuffle it, and
6850 // OR it with the first shuffled input.
6852 for (unsigned i = 0; i != 16; ++i) {
6853 int EltIdx = MaskVals[i];
6854 EltIdx = (EltIdx < 16) ? 0x80 : EltIdx - 16;
6855 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
6857 V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2,
6858 DAG.getNode(ISD::BUILD_VECTOR, dl,
6859 MVT::v16i8, pshufbMask));
6860 return DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
6863 // No SSSE3 - Calculate in place words and then fix all out of place words
6864 // With 0-16 extracts & inserts. Worst case is 16 bytes out of order from
6865 // the 16 different words that comprise the two doublequadword input vectors.
6866 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
6867 V2 = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V2);
6869 for (int i = 0; i != 8; ++i) {
6870 int Elt0 = MaskVals[i*2];
6871 int Elt1 = MaskVals[i*2+1];
6873 // This word of the result is all undef, skip it.
6874 if (Elt0 < 0 && Elt1 < 0)
6877 // This word of the result is already in the correct place, skip it.
6878 if ((Elt0 == i*2) && (Elt1 == i*2+1))
6881 SDValue Elt0Src = Elt0 < 16 ? V1 : V2;
6882 SDValue Elt1Src = Elt1 < 16 ? V1 : V2;
6885 // If Elt0 and Elt1 are defined, are consecutive, and can be load
6886 // using a single extract together, load it and store it.
6887 if ((Elt0 >= 0) && ((Elt0 + 1) == Elt1) && ((Elt0 & 1) == 0)) {
6888 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src,
6889 DAG.getIntPtrConstant(Elt1 / 2));
6890 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt,
6891 DAG.getIntPtrConstant(i));
6895 // If Elt1 is defined, extract it from the appropriate source. If the
6896 // source byte is not also odd, shift the extracted word left 8 bits
6897 // otherwise clear the bottom 8 bits if we need to do an or.
6899 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src,
6900 DAG.getIntPtrConstant(Elt1 / 2));
6901 if ((Elt1 & 1) == 0)
6902 InsElt = DAG.getNode(ISD::SHL, dl, MVT::i16, InsElt,
6904 TLI.getShiftAmountTy(InsElt.getValueType())));
6906 InsElt = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt,
6907 DAG.getConstant(0xFF00, MVT::i16));
6909 // If Elt0 is defined, extract it from the appropriate source. If the
6910 // source byte is not also even, shift the extracted word right 8 bits. If
6911 // Elt1 was also defined, OR the extracted values together before
6912 // inserting them in the result.
6914 SDValue InsElt0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16,
6915 Elt0Src, DAG.getIntPtrConstant(Elt0 / 2));
6916 if ((Elt0 & 1) != 0)
6917 InsElt0 = DAG.getNode(ISD::SRL, dl, MVT::i16, InsElt0,
6919 TLI.getShiftAmountTy(InsElt0.getValueType())));
6921 InsElt0 = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt0,
6922 DAG.getConstant(0x00FF, MVT::i16));
6923 InsElt = Elt1 >= 0 ? DAG.getNode(ISD::OR, dl, MVT::i16, InsElt, InsElt0)
6926 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt,
6927 DAG.getIntPtrConstant(i));
6929 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, NewV);
6932 // v32i8 shuffles - Translate to VPSHUFB if possible.
6934 SDValue LowerVECTOR_SHUFFLEv32i8(ShuffleVectorSDNode *SVOp,
6935 const X86Subtarget *Subtarget,
6936 SelectionDAG &DAG) {
6937 MVT VT = SVOp->getSimpleValueType(0);
6938 SDValue V1 = SVOp->getOperand(0);
6939 SDValue V2 = SVOp->getOperand(1);
6941 SmallVector<int, 32> MaskVals(SVOp->getMask().begin(), SVOp->getMask().end());
6943 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
6944 bool V1IsAllZero = ISD::isBuildVectorAllZeros(V1.getNode());
6945 bool V2IsAllZero = ISD::isBuildVectorAllZeros(V2.getNode());
6947 // VPSHUFB may be generated if
6948 // (1) one of input vector is undefined or zeroinitializer.
6949 // The mask value 0x80 puts 0 in the corresponding slot of the vector.
6950 // And (2) the mask indexes don't cross the 128-bit lane.
6951 if (VT != MVT::v32i8 || !Subtarget->hasInt256() ||
6952 (!V2IsUndef && !V2IsAllZero && !V1IsAllZero))
6955 if (V1IsAllZero && !V2IsAllZero) {
6956 CommuteVectorShuffleMask(MaskVals, 32);
6959 return getPSHUFB(MaskVals, V1, dl, DAG);
6962 /// RewriteAsNarrowerShuffle - Try rewriting v8i16 and v16i8 shuffles as 4 wide
6963 /// ones, or rewriting v4i32 / v4f32 as 2 wide ones if possible. This can be
6964 /// done when every pair / quad of shuffle mask elements point to elements in
6965 /// the right sequence. e.g.
6966 /// vector_shuffle X, Y, <2, 3, | 10, 11, | 0, 1, | 14, 15>
6968 SDValue RewriteAsNarrowerShuffle(ShuffleVectorSDNode *SVOp,
6969 SelectionDAG &DAG) {
6970 MVT VT = SVOp->getSimpleValueType(0);
6972 unsigned NumElems = VT.getVectorNumElements();
6975 switch (VT.SimpleTy) {
6976 default: llvm_unreachable("Unexpected!");
6979 return SDValue(SVOp, 0);
6980 case MVT::v4f32: NewVT = MVT::v2f64; Scale = 2; break;
6981 case MVT::v4i32: NewVT = MVT::v2i64; Scale = 2; break;
6982 case MVT::v8i16: NewVT = MVT::v4i32; Scale = 2; break;
6983 case MVT::v16i8: NewVT = MVT::v4i32; Scale = 4; break;
6984 case MVT::v16i16: NewVT = MVT::v8i32; Scale = 2; break;
6985 case MVT::v32i8: NewVT = MVT::v8i32; Scale = 4; break;
6988 SmallVector<int, 8> MaskVec;
6989 for (unsigned i = 0; i != NumElems; i += Scale) {
6991 for (unsigned j = 0; j != Scale; ++j) {
6992 int EltIdx = SVOp->getMaskElt(i+j);
6996 StartIdx = (EltIdx / Scale);
6997 if (EltIdx != (int)(StartIdx*Scale + j))
7000 MaskVec.push_back(StartIdx);
7003 SDValue V1 = DAG.getNode(ISD::BITCAST, dl, NewVT, SVOp->getOperand(0));
7004 SDValue V2 = DAG.getNode(ISD::BITCAST, dl, NewVT, SVOp->getOperand(1));
7005 return DAG.getVectorShuffle(NewVT, dl, V1, V2, &MaskVec[0]);
7008 /// getVZextMovL - Return a zero-extending vector move low node.
7010 static SDValue getVZextMovL(MVT VT, MVT OpVT,
7011 SDValue SrcOp, SelectionDAG &DAG,
7012 const X86Subtarget *Subtarget, SDLoc dl) {
7013 if (VT == MVT::v2f64 || VT == MVT::v4f32) {
7014 LoadSDNode *LD = nullptr;
7015 if (!isScalarLoadToVector(SrcOp.getNode(), &LD))
7016 LD = dyn_cast<LoadSDNode>(SrcOp);
7018 // movssrr and movsdrr do not clear top bits. Try to use movd, movq
7020 MVT ExtVT = (OpVT == MVT::v2f64) ? MVT::i64 : MVT::i32;
7021 if ((ExtVT != MVT::i64 || Subtarget->is64Bit()) &&
7022 SrcOp.getOpcode() == ISD::SCALAR_TO_VECTOR &&
7023 SrcOp.getOperand(0).getOpcode() == ISD::BITCAST &&
7024 SrcOp.getOperand(0).getOperand(0).getValueType() == ExtVT) {
7026 OpVT = (OpVT == MVT::v2f64) ? MVT::v2i64 : MVT::v4i32;
7027 return DAG.getNode(ISD::BITCAST, dl, VT,
7028 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT,
7029 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
7037 return DAG.getNode(ISD::BITCAST, dl, VT,
7038 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT,
7039 DAG.getNode(ISD::BITCAST, dl,
7043 /// LowerVECTOR_SHUFFLE_256 - Handle all 256-bit wide vectors shuffles
7044 /// which could not be matched by any known target speficic shuffle
7046 LowerVECTOR_SHUFFLE_256(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
7048 SDValue NewOp = Compact8x32ShuffleNode(SVOp, DAG);
7049 if (NewOp.getNode())
7052 MVT VT = SVOp->getSimpleValueType(0);
7054 unsigned NumElems = VT.getVectorNumElements();
7055 unsigned NumLaneElems = NumElems / 2;
7058 MVT EltVT = VT.getVectorElementType();
7059 MVT NVT = MVT::getVectorVT(EltVT, NumLaneElems);
7062 SmallVector<int, 16> Mask;
7063 for (unsigned l = 0; l < 2; ++l) {
7064 // Build a shuffle mask for the output, discovering on the fly which
7065 // input vectors to use as shuffle operands (recorded in InputUsed).
7066 // If building a suitable shuffle vector proves too hard, then bail
7067 // out with UseBuildVector set.
7068 bool UseBuildVector = false;
7069 int InputUsed[2] = { -1, -1 }; // Not yet discovered.
7070 unsigned LaneStart = l * NumLaneElems;
7071 for (unsigned i = 0; i != NumLaneElems; ++i) {
7072 // The mask element. This indexes into the input.
7073 int Idx = SVOp->getMaskElt(i+LaneStart);
7075 // the mask element does not index into any input vector.
7080 // The input vector this mask element indexes into.
7081 int Input = Idx / NumLaneElems;
7083 // Turn the index into an offset from the start of the input vector.
7084 Idx -= Input * NumLaneElems;
7086 // Find or create a shuffle vector operand to hold this input.
7088 for (OpNo = 0; OpNo < array_lengthof(InputUsed); ++OpNo) {
7089 if (InputUsed[OpNo] == Input)
7090 // This input vector is already an operand.
7092 if (InputUsed[OpNo] < 0) {
7093 // Create a new operand for this input vector.
7094 InputUsed[OpNo] = Input;
7099 if (OpNo >= array_lengthof(InputUsed)) {
7100 // More than two input vectors used! Give up on trying to create a
7101 // shuffle vector. Insert all elements into a BUILD_VECTOR instead.
7102 UseBuildVector = true;
7106 // Add the mask index for the new shuffle vector.
7107 Mask.push_back(Idx + OpNo * NumLaneElems);
7110 if (UseBuildVector) {
7111 SmallVector<SDValue, 16> SVOps;
7112 for (unsigned i = 0; i != NumLaneElems; ++i) {
7113 // The mask element. This indexes into the input.
7114 int Idx = SVOp->getMaskElt(i+LaneStart);
7116 SVOps.push_back(DAG.getUNDEF(EltVT));
7120 // The input vector this mask element indexes into.
7121 int Input = Idx / NumElems;
7123 // Turn the index into an offset from the start of the input vector.
7124 Idx -= Input * NumElems;
7126 // Extract the vector element by hand.
7127 SVOps.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT,
7128 SVOp->getOperand(Input),
7129 DAG.getIntPtrConstant(Idx)));
7132 // Construct the output using a BUILD_VECTOR.
7133 Output[l] = DAG.getNode(ISD::BUILD_VECTOR, dl, NVT, SVOps);
7134 } else if (InputUsed[0] < 0) {
7135 // No input vectors were used! The result is undefined.
7136 Output[l] = DAG.getUNDEF(NVT);
7138 SDValue Op0 = Extract128BitVector(SVOp->getOperand(InputUsed[0] / 2),
7139 (InputUsed[0] % 2) * NumLaneElems,
7141 // If only one input was used, use an undefined vector for the other.
7142 SDValue Op1 = (InputUsed[1] < 0) ? DAG.getUNDEF(NVT) :
7143 Extract128BitVector(SVOp->getOperand(InputUsed[1] / 2),
7144 (InputUsed[1] % 2) * NumLaneElems, DAG, dl);
7145 // At least one input vector was used. Create a new shuffle vector.
7146 Output[l] = DAG.getVectorShuffle(NVT, dl, Op0, Op1, &Mask[0]);
7152 // Concatenate the result back
7153 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, Output[0], Output[1]);
7156 /// LowerVECTOR_SHUFFLE_128v4 - Handle all 128-bit wide vectors with
7157 /// 4 elements, and match them with several different shuffle types.
7159 LowerVECTOR_SHUFFLE_128v4(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
7160 SDValue V1 = SVOp->getOperand(0);
7161 SDValue V2 = SVOp->getOperand(1);
7163 MVT VT = SVOp->getSimpleValueType(0);
7165 assert(VT.is128BitVector() && "Unsupported vector size");
7167 std::pair<int, int> Locs[4];
7168 int Mask1[] = { -1, -1, -1, -1 };
7169 SmallVector<int, 8> PermMask(SVOp->getMask().begin(), SVOp->getMask().end());
7173 for (unsigned i = 0; i != 4; ++i) {
7174 int Idx = PermMask[i];
7176 Locs[i] = std::make_pair(-1, -1);
7178 assert(Idx < 8 && "Invalid VECTOR_SHUFFLE index!");
7180 Locs[i] = std::make_pair(0, NumLo);
7184 Locs[i] = std::make_pair(1, NumHi);
7186 Mask1[2+NumHi] = Idx;
7192 if (NumLo <= 2 && NumHi <= 2) {
7193 // If no more than two elements come from either vector. This can be
7194 // implemented with two shuffles. First shuffle gather the elements.
7195 // The second shuffle, which takes the first shuffle as both of its
7196 // vector operands, put the elements into the right order.
7197 V1 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
7199 int Mask2[] = { -1, -1, -1, -1 };
7201 for (unsigned i = 0; i != 4; ++i)
7202 if (Locs[i].first != -1) {
7203 unsigned Idx = (i < 2) ? 0 : 4;
7204 Idx += Locs[i].first * 2 + Locs[i].second;
7208 return DAG.getVectorShuffle(VT, dl, V1, V1, &Mask2[0]);
7211 if (NumLo == 3 || NumHi == 3) {
7212 // Otherwise, we must have three elements from one vector, call it X, and
7213 // one element from the other, call it Y. First, use a shufps to build an
7214 // intermediate vector with the one element from Y and the element from X
7215 // that will be in the same half in the final destination (the indexes don't
7216 // matter). Then, use a shufps to build the final vector, taking the half
7217 // containing the element from Y from the intermediate, and the other half
7220 // Normalize it so the 3 elements come from V1.
7221 CommuteVectorShuffleMask(PermMask, 4);
7225 // Find the element from V2.
7227 for (HiIndex = 0; HiIndex < 3; ++HiIndex) {
7228 int Val = PermMask[HiIndex];
7235 Mask1[0] = PermMask[HiIndex];
7237 Mask1[2] = PermMask[HiIndex^1];
7239 V2 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
7242 Mask1[0] = PermMask[0];
7243 Mask1[1] = PermMask[1];
7244 Mask1[2] = HiIndex & 1 ? 6 : 4;
7245 Mask1[3] = HiIndex & 1 ? 4 : 6;
7246 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
7249 Mask1[0] = HiIndex & 1 ? 2 : 0;
7250 Mask1[1] = HiIndex & 1 ? 0 : 2;
7251 Mask1[2] = PermMask[2];
7252 Mask1[3] = PermMask[3];
7257 return DAG.getVectorShuffle(VT, dl, V2, V1, &Mask1[0]);
7260 // Break it into (shuffle shuffle_hi, shuffle_lo).
7261 int LoMask[] = { -1, -1, -1, -1 };
7262 int HiMask[] = { -1, -1, -1, -1 };
7264 int *MaskPtr = LoMask;
7265 unsigned MaskIdx = 0;
7268 for (unsigned i = 0; i != 4; ++i) {
7275 int Idx = PermMask[i];
7277 Locs[i] = std::make_pair(-1, -1);
7278 } else if (Idx < 4) {
7279 Locs[i] = std::make_pair(MaskIdx, LoIdx);
7280 MaskPtr[LoIdx] = Idx;
7283 Locs[i] = std::make_pair(MaskIdx, HiIdx);
7284 MaskPtr[HiIdx] = Idx;
7289 SDValue LoShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &LoMask[0]);
7290 SDValue HiShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &HiMask[0]);
7291 int MaskOps[] = { -1, -1, -1, -1 };
7292 for (unsigned i = 0; i != 4; ++i)
7293 if (Locs[i].first != -1)
7294 MaskOps[i] = Locs[i].first * 4 + Locs[i].second;
7295 return DAG.getVectorShuffle(VT, dl, LoShuffle, HiShuffle, &MaskOps[0]);
7298 static bool MayFoldVectorLoad(SDValue V) {
7299 while (V.hasOneUse() && V.getOpcode() == ISD::BITCAST)
7300 V = V.getOperand(0);
7302 if (V.hasOneUse() && V.getOpcode() == ISD::SCALAR_TO_VECTOR)
7303 V = V.getOperand(0);
7304 if (V.hasOneUse() && V.getOpcode() == ISD::BUILD_VECTOR &&
7305 V.getNumOperands() == 2 && V.getOperand(1).getOpcode() == ISD::UNDEF)
7306 // BUILD_VECTOR (load), undef
7307 V = V.getOperand(0);
7309 return MayFoldLoad(V);
7313 SDValue getMOVDDup(SDValue &Op, SDLoc &dl, SDValue V1, SelectionDAG &DAG) {
7314 MVT VT = Op.getSimpleValueType();
7316 // Canonizalize to v2f64.
7317 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, V1);
7318 return DAG.getNode(ISD::BITCAST, dl, VT,
7319 getTargetShuffleNode(X86ISD::MOVDDUP, dl, MVT::v2f64,
7324 SDValue getMOVLowToHigh(SDValue &Op, SDLoc &dl, SelectionDAG &DAG,
7326 SDValue V1 = Op.getOperand(0);
7327 SDValue V2 = Op.getOperand(1);
7328 MVT VT = Op.getSimpleValueType();
7330 assert(VT != MVT::v2i64 && "unsupported shuffle type");
7332 if (HasSSE2 && VT == MVT::v2f64)
7333 return getTargetShuffleNode(X86ISD::MOVLHPD, dl, VT, V1, V2, DAG);
7335 // v4f32 or v4i32: canonizalized to v4f32 (which is legal for SSE1)
7336 return DAG.getNode(ISD::BITCAST, dl, VT,
7337 getTargetShuffleNode(X86ISD::MOVLHPS, dl, MVT::v4f32,
7338 DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V1),
7339 DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V2), DAG));
7343 SDValue getMOVHighToLow(SDValue &Op, SDLoc &dl, SelectionDAG &DAG) {
7344 SDValue V1 = Op.getOperand(0);
7345 SDValue V2 = Op.getOperand(1);
7346 MVT VT = Op.getSimpleValueType();
7348 assert((VT == MVT::v4i32 || VT == MVT::v4f32) &&
7349 "unsupported shuffle type");
7351 if (V2.getOpcode() == ISD::UNDEF)
7355 return getTargetShuffleNode(X86ISD::MOVHLPS, dl, VT, V1, V2, DAG);
7359 SDValue getMOVLP(SDValue &Op, SDLoc &dl, SelectionDAG &DAG, bool HasSSE2) {
7360 SDValue V1 = Op.getOperand(0);
7361 SDValue V2 = Op.getOperand(1);
7362 MVT VT = Op.getSimpleValueType();
7363 unsigned NumElems = VT.getVectorNumElements();
7365 // Use MOVLPS and MOVLPD in case V1 or V2 are loads. During isel, the second
7366 // operand of these instructions is only memory, so check if there's a
7367 // potencial load folding here, otherwise use SHUFPS or MOVSD to match the
7369 bool CanFoldLoad = false;
7371 // Trivial case, when V2 comes from a load.
7372 if (MayFoldVectorLoad(V2))
7375 // When V1 is a load, it can be folded later into a store in isel, example:
7376 // (store (v4f32 (X86Movlps (load addr:$src1), VR128:$src2)), addr:$src1)
7378 // (MOVLPSmr addr:$src1, VR128:$src2)
7379 // So, recognize this potential and also use MOVLPS or MOVLPD
7380 else if (MayFoldVectorLoad(V1) && MayFoldIntoStore(Op))
7383 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
7385 if (HasSSE2 && NumElems == 2)
7386 return getTargetShuffleNode(X86ISD::MOVLPD, dl, VT, V1, V2, DAG);
7389 // If we don't care about the second element, proceed to use movss.
7390 if (SVOp->getMaskElt(1) != -1)
7391 return getTargetShuffleNode(X86ISD::MOVLPS, dl, VT, V1, V2, DAG);
7394 // movl and movlp will both match v2i64, but v2i64 is never matched by
7395 // movl earlier because we make it strict to avoid messing with the movlp load
7396 // folding logic (see the code above getMOVLP call). Match it here then,
7397 // this is horrible, but will stay like this until we move all shuffle
7398 // matching to x86 specific nodes. Note that for the 1st condition all
7399 // types are matched with movsd.
7401 // FIXME: isMOVLMask should be checked and matched before getMOVLP,
7402 // as to remove this logic from here, as much as possible
7403 if (NumElems == 2 || !isMOVLMask(SVOp->getMask(), VT))
7404 return getTargetShuffleNode(X86ISD::MOVSD, dl, VT, V1, V2, DAG);
7405 return getTargetShuffleNode(X86ISD::MOVSS, dl, VT, V1, V2, DAG);
7408 assert(VT != MVT::v4i32 && "unsupported shuffle type");
7410 // Invert the operand order and use SHUFPS to match it.
7411 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V2, V1,
7412 getShuffleSHUFImmediate(SVOp), DAG);
7415 static SDValue NarrowVectorLoadToElement(LoadSDNode *Load, unsigned Index,
7416 SelectionDAG &DAG) {
7418 MVT VT = Load->getSimpleValueType(0);
7419 MVT EVT = VT.getVectorElementType();
7420 SDValue Addr = Load->getOperand(1);
7421 SDValue NewAddr = DAG.getNode(
7422 ISD::ADD, dl, Addr.getSimpleValueType(), Addr,
7423 DAG.getConstant(Index * EVT.getStoreSize(), Addr.getSimpleValueType()));
7426 DAG.getLoad(EVT, dl, Load->getChain(), NewAddr,
7427 DAG.getMachineFunction().getMachineMemOperand(
7428 Load->getMemOperand(), 0, EVT.getStoreSize()));
7432 // It is only safe to call this function if isINSERTPSMask is true for
7433 // this shufflevector mask.
7434 static SDValue getINSERTPS(ShuffleVectorSDNode *SVOp, SDLoc &dl,
7435 SelectionDAG &DAG) {
7436 // Generate an insertps instruction when inserting an f32 from memory onto a
7437 // v4f32 or when copying a member from one v4f32 to another.
7438 // We also use it for transferring i32 from one register to another,
7439 // since it simply copies the same bits.
7440 // If we're transferring an i32 from memory to a specific element in a
7441 // register, we output a generic DAG that will match the PINSRD
7443 MVT VT = SVOp->getSimpleValueType(0);
7444 MVT EVT = VT.getVectorElementType();
7445 SDValue V1 = SVOp->getOperand(0);
7446 SDValue V2 = SVOp->getOperand(1);
7447 auto Mask = SVOp->getMask();
7448 assert((VT == MVT::v4f32 || VT == MVT::v4i32) &&
7449 "unsupported vector type for insertps/pinsrd");
7451 int FromV1 = std::count_if(Mask.begin(), Mask.end(),
7452 [](const int &i) { return i < 4; });
7460 DestIndex = std::find_if(Mask.begin(), Mask.end(),
7461 [](const int &i) { return i < 4; }) -
7466 DestIndex = std::find_if(Mask.begin(), Mask.end(),
7467 [](const int &i) { return i >= 4; }) -
7471 if (MayFoldLoad(From)) {
7472 // Trivial case, when From comes from a load and is only used by the
7473 // shuffle. Make it use insertps from the vector that we need from that
7476 NarrowVectorLoadToElement(cast<LoadSDNode>(From), DestIndex, DAG);
7477 if (!NewLoad.getNode())
7480 if (EVT == MVT::f32) {
7481 // Create this as a scalar to vector to match the instruction pattern.
7482 SDValue LoadScalarToVector =
7483 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, NewLoad);
7484 SDValue InsertpsMask = DAG.getIntPtrConstant(DestIndex << 4);
7485 return DAG.getNode(X86ISD::INSERTPS, dl, VT, To, LoadScalarToVector,
7487 } else { // EVT == MVT::i32
7488 // If we're getting an i32 from memory, use an INSERT_VECTOR_ELT
7489 // instruction, to match the PINSRD instruction, which loads an i32 to a
7490 // certain vector element.
7491 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, To, NewLoad,
7492 DAG.getConstant(DestIndex, MVT::i32));
7496 // Vector-element-to-vector
7497 unsigned SrcIndex = Mask[DestIndex] % 4;
7498 SDValue InsertpsMask = DAG.getIntPtrConstant(DestIndex << 4 | SrcIndex << 6);
7499 return DAG.getNode(X86ISD::INSERTPS, dl, VT, To, From, InsertpsMask);
7502 // Reduce a vector shuffle to zext.
7503 static SDValue LowerVectorIntExtend(SDValue Op, const X86Subtarget *Subtarget,
7504 SelectionDAG &DAG) {
7505 // PMOVZX is only available from SSE41.
7506 if (!Subtarget->hasSSE41())
7509 MVT VT = Op.getSimpleValueType();
7511 // Only AVX2 support 256-bit vector integer extending.
7512 if (!Subtarget->hasInt256() && VT.is256BitVector())
7515 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
7517 SDValue V1 = Op.getOperand(0);
7518 SDValue V2 = Op.getOperand(1);
7519 unsigned NumElems = VT.getVectorNumElements();
7521 // Extending is an unary operation and the element type of the source vector
7522 // won't be equal to or larger than i64.
7523 if (V2.getOpcode() != ISD::UNDEF || !VT.isInteger() ||
7524 VT.getVectorElementType() == MVT::i64)
7527 // Find the expansion ratio, e.g. expanding from i8 to i32 has a ratio of 4.
7528 unsigned Shift = 1; // Start from 2, i.e. 1 << 1.
7529 while ((1U << Shift) < NumElems) {
7530 if (SVOp->getMaskElt(1U << Shift) == 1)
7533 // The maximal ratio is 8, i.e. from i8 to i64.
7538 // Check the shuffle mask.
7539 unsigned Mask = (1U << Shift) - 1;
7540 for (unsigned i = 0; i != NumElems; ++i) {
7541 int EltIdx = SVOp->getMaskElt(i);
7542 if ((i & Mask) != 0 && EltIdx != -1)
7544 if ((i & Mask) == 0 && (unsigned)EltIdx != (i >> Shift))
7548 unsigned NBits = VT.getVectorElementType().getSizeInBits() << Shift;
7549 MVT NeVT = MVT::getIntegerVT(NBits);
7550 MVT NVT = MVT::getVectorVT(NeVT, NumElems >> Shift);
7552 if (!DAG.getTargetLoweringInfo().isTypeLegal(NVT))
7555 // Simplify the operand as it's prepared to be fed into shuffle.
7556 unsigned SignificantBits = NVT.getSizeInBits() >> Shift;
7557 if (V1.getOpcode() == ISD::BITCAST &&
7558 V1.getOperand(0).getOpcode() == ISD::SCALAR_TO_VECTOR &&
7559 V1.getOperand(0).getOperand(0).getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
7560 V1.getOperand(0).getOperand(0)
7561 .getSimpleValueType().getSizeInBits() == SignificantBits) {
7562 // (bitcast (sclr2vec (ext_vec_elt x))) -> (bitcast x)
7563 SDValue V = V1.getOperand(0).getOperand(0).getOperand(0);
7564 ConstantSDNode *CIdx =
7565 dyn_cast<ConstantSDNode>(V1.getOperand(0).getOperand(0).getOperand(1));
7566 // If it's foldable, i.e. normal load with single use, we will let code
7567 // selection to fold it. Otherwise, we will short the conversion sequence.
7568 if (CIdx && CIdx->getZExtValue() == 0 &&
7569 (!ISD::isNormalLoad(V.getNode()) || !V.hasOneUse())) {
7570 MVT FullVT = V.getSimpleValueType();
7571 MVT V1VT = V1.getSimpleValueType();
7572 if (FullVT.getSizeInBits() > V1VT.getSizeInBits()) {
7573 // The "ext_vec_elt" node is wider than the result node.
7574 // In this case we should extract subvector from V.
7575 // (bitcast (sclr2vec (ext_vec_elt x))) -> (bitcast (extract_subvector x)).
7576 unsigned Ratio = FullVT.getSizeInBits() / V1VT.getSizeInBits();
7577 MVT SubVecVT = MVT::getVectorVT(FullVT.getVectorElementType(),
7578 FullVT.getVectorNumElements()/Ratio);
7579 V = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SubVecVT, V,
7580 DAG.getIntPtrConstant(0));
7582 V1 = DAG.getNode(ISD::BITCAST, DL, V1VT, V);
7586 return DAG.getNode(ISD::BITCAST, DL, VT,
7587 DAG.getNode(X86ISD::VZEXT, DL, NVT, V1));
7590 static SDValue NormalizeVectorShuffle(SDValue Op, const X86Subtarget *Subtarget,
7591 SelectionDAG &DAG) {
7592 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
7593 MVT VT = Op.getSimpleValueType();
7595 SDValue V1 = Op.getOperand(0);
7596 SDValue V2 = Op.getOperand(1);
7598 if (isZeroShuffle(SVOp))
7599 return getZeroVector(VT, Subtarget, DAG, dl);
7601 // Handle splat operations
7602 if (SVOp->isSplat()) {
7603 // Use vbroadcast whenever the splat comes from a foldable load
7604 SDValue Broadcast = LowerVectorBroadcast(Op, Subtarget, DAG);
7605 if (Broadcast.getNode())
7609 // Check integer expanding shuffles.
7610 SDValue NewOp = LowerVectorIntExtend(Op, Subtarget, DAG);
7611 if (NewOp.getNode())
7614 // If the shuffle can be profitably rewritten as a narrower shuffle, then
7616 if (VT == MVT::v8i16 || VT == MVT::v16i8 || VT == MVT::v16i16 ||
7618 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG);
7619 if (NewOp.getNode())
7620 return DAG.getNode(ISD::BITCAST, dl, VT, NewOp);
7621 } else if (VT.is128BitVector() && Subtarget->hasSSE2()) {
7622 // FIXME: Figure out a cleaner way to do this.
7623 if (ISD::isBuildVectorAllZeros(V2.getNode())) {
7624 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG);
7625 if (NewOp.getNode()) {
7626 MVT NewVT = NewOp.getSimpleValueType();
7627 if (isCommutedMOVLMask(cast<ShuffleVectorSDNode>(NewOp)->getMask(),
7628 NewVT, true, false))
7629 return getVZextMovL(VT, NewVT, NewOp.getOperand(0), DAG, Subtarget,
7632 } else if (ISD::isBuildVectorAllZeros(V1.getNode())) {
7633 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG);
7634 if (NewOp.getNode()) {
7635 MVT NewVT = NewOp.getSimpleValueType();
7636 if (isMOVLMask(cast<ShuffleVectorSDNode>(NewOp)->getMask(), NewVT))
7637 return getVZextMovL(VT, NewVT, NewOp.getOperand(1), DAG, Subtarget,
7646 X86TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const {
7647 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
7648 SDValue V1 = Op.getOperand(0);
7649 SDValue V2 = Op.getOperand(1);
7650 MVT VT = Op.getSimpleValueType();
7652 unsigned NumElems = VT.getVectorNumElements();
7653 bool V1IsUndef = V1.getOpcode() == ISD::UNDEF;
7654 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
7655 bool V1IsSplat = false;
7656 bool V2IsSplat = false;
7657 bool HasSSE2 = Subtarget->hasSSE2();
7658 bool HasFp256 = Subtarget->hasFp256();
7659 bool HasInt256 = Subtarget->hasInt256();
7660 MachineFunction &MF = DAG.getMachineFunction();
7661 bool OptForSize = MF.getFunction()->getAttributes().
7662 hasAttribute(AttributeSet::FunctionIndex, Attribute::OptimizeForSize);
7664 assert(VT.getSizeInBits() != 64 && "Can't lower MMX shuffles");
7666 if (V1IsUndef && V2IsUndef)
7667 return DAG.getUNDEF(VT);
7669 // When we create a shuffle node we put the UNDEF node to second operand,
7670 // but in some cases the first operand may be transformed to UNDEF.
7671 // In this case we should just commute the node.
7673 return CommuteVectorShuffle(SVOp, DAG);
7675 // Vector shuffle lowering takes 3 steps:
7677 // 1) Normalize the input vectors. Here splats, zeroed vectors, profitable
7678 // narrowing and commutation of operands should be handled.
7679 // 2) Matching of shuffles with known shuffle masks to x86 target specific
7681 // 3) Rewriting of unmatched masks into new generic shuffle operations,
7682 // so the shuffle can be broken into other shuffles and the legalizer can
7683 // try the lowering again.
7685 // The general idea is that no vector_shuffle operation should be left to
7686 // be matched during isel, all of them must be converted to a target specific
7689 // Normalize the input vectors. Here splats, zeroed vectors, profitable
7690 // narrowing and commutation of operands should be handled. The actual code
7691 // doesn't include all of those, work in progress...
7692 SDValue NewOp = NormalizeVectorShuffle(Op, Subtarget, DAG);
7693 if (NewOp.getNode())
7696 SmallVector<int, 8> M(SVOp->getMask().begin(), SVOp->getMask().end());
7698 // NOTE: isPSHUFDMask can also match both masks below (unpckl_undef and
7699 // unpckh_undef). Only use pshufd if speed is more important than size.
7700 if (OptForSize && isUNPCKL_v_undef_Mask(M, VT, HasInt256))
7701 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
7702 if (OptForSize && isUNPCKH_v_undef_Mask(M, VT, HasInt256))
7703 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
7705 if (isMOVDDUPMask(M, VT) && Subtarget->hasSSE3() &&
7706 V2IsUndef && MayFoldVectorLoad(V1))
7707 return getMOVDDup(Op, dl, V1, DAG);
7709 if (isMOVHLPS_v_undef_Mask(M, VT))
7710 return getMOVHighToLow(Op, dl, DAG);
7712 // Use to match splats
7713 if (HasSSE2 && isUNPCKHMask(M, VT, HasInt256) && V2IsUndef &&
7714 (VT == MVT::v2f64 || VT == MVT::v2i64))
7715 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
7717 if (isPSHUFDMask(M, VT)) {
7718 // The actual implementation will match the mask in the if above and then
7719 // during isel it can match several different instructions, not only pshufd
7720 // as its name says, sad but true, emulate the behavior for now...
7721 if (isMOVDDUPMask(M, VT) && ((VT == MVT::v4f32 || VT == MVT::v2i64)))
7722 return getTargetShuffleNode(X86ISD::MOVLHPS, dl, VT, V1, V1, DAG);
7724 unsigned TargetMask = getShuffleSHUFImmediate(SVOp);
7726 if (HasSSE2 && (VT == MVT::v4f32 || VT == MVT::v4i32))
7727 return getTargetShuffleNode(X86ISD::PSHUFD, dl, VT, V1, TargetMask, DAG);
7729 if (HasFp256 && (VT == MVT::v4f32 || VT == MVT::v2f64))
7730 return getTargetShuffleNode(X86ISD::VPERMILP, dl, VT, V1, TargetMask,
7733 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V1, V1,
7737 if (isPALIGNRMask(M, VT, Subtarget))
7738 return getTargetShuffleNode(X86ISD::PALIGNR, dl, VT, V1, V2,
7739 getShufflePALIGNRImmediate(SVOp),
7742 // Check if this can be converted into a logical shift.
7743 bool isLeft = false;
7746 bool isShift = HasSSE2 && isVectorShift(SVOp, DAG, isLeft, ShVal, ShAmt);
7747 if (isShift && ShVal.hasOneUse()) {
7748 // If the shifted value has multiple uses, it may be cheaper to use
7749 // v_set0 + movlhps or movhlps, etc.
7750 MVT EltVT = VT.getVectorElementType();
7751 ShAmt *= EltVT.getSizeInBits();
7752 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl);
7755 if (isMOVLMask(M, VT)) {
7756 if (ISD::isBuildVectorAllZeros(V1.getNode()))
7757 return getVZextMovL(VT, VT, V2, DAG, Subtarget, dl);
7758 if (!isMOVLPMask(M, VT)) {
7759 if (HasSSE2 && (VT == MVT::v2i64 || VT == MVT::v2f64))
7760 return getTargetShuffleNode(X86ISD::MOVSD, dl, VT, V1, V2, DAG);
7762 if (VT == MVT::v4i32 || VT == MVT::v4f32)
7763 return getTargetShuffleNode(X86ISD::MOVSS, dl, VT, V1, V2, DAG);
7767 // FIXME: fold these into legal mask.
7768 if (isMOVLHPSMask(M, VT) && !isUNPCKLMask(M, VT, HasInt256))
7769 return getMOVLowToHigh(Op, dl, DAG, HasSSE2);
7771 if (isMOVHLPSMask(M, VT))
7772 return getMOVHighToLow(Op, dl, DAG);
7774 if (V2IsUndef && isMOVSHDUPMask(M, VT, Subtarget))
7775 return getTargetShuffleNode(X86ISD::MOVSHDUP, dl, VT, V1, DAG);
7777 if (V2IsUndef && isMOVSLDUPMask(M, VT, Subtarget))
7778 return getTargetShuffleNode(X86ISD::MOVSLDUP, dl, VT, V1, DAG);
7780 if (isMOVLPMask(M, VT))
7781 return getMOVLP(Op, dl, DAG, HasSSE2);
7783 if (ShouldXformToMOVHLPS(M, VT) ||
7784 ShouldXformToMOVLP(V1.getNode(), V2.getNode(), M, VT))
7785 return CommuteVectorShuffle(SVOp, DAG);
7788 // No better options. Use a vshldq / vsrldq.
7789 MVT EltVT = VT.getVectorElementType();
7790 ShAmt *= EltVT.getSizeInBits();
7791 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl);
7794 bool Commuted = false;
7795 // FIXME: This should also accept a bitcast of a splat? Be careful, not
7796 // 1,1,1,1 -> v8i16 though.
7797 V1IsSplat = isSplatVector(V1.getNode());
7798 V2IsSplat = isSplatVector(V2.getNode());
7800 // Canonicalize the splat or undef, if present, to be on the RHS.
7801 if (!V2IsUndef && V1IsSplat && !V2IsSplat) {
7802 CommuteVectorShuffleMask(M, NumElems);
7804 std::swap(V1IsSplat, V2IsSplat);
7808 if (isCommutedMOVLMask(M, VT, V2IsSplat, V2IsUndef)) {
7809 // Shuffling low element of v1 into undef, just return v1.
7812 // If V2 is a splat, the mask may be malformed such as <4,3,3,3>, which
7813 // the instruction selector will not match, so get a canonical MOVL with
7814 // swapped operands to undo the commute.
7815 return getMOVL(DAG, dl, VT, V2, V1);
7818 if (isUNPCKLMask(M, VT, HasInt256))
7819 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG);
7821 if (isUNPCKHMask(M, VT, HasInt256))
7822 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG);
7825 // Normalize mask so all entries that point to V2 points to its first
7826 // element then try to match unpck{h|l} again. If match, return a
7827 // new vector_shuffle with the corrected mask.p
7828 SmallVector<int, 8> NewMask(M.begin(), M.end());
7829 NormalizeMask(NewMask, NumElems);
7830 if (isUNPCKLMask(NewMask, VT, HasInt256, true))
7831 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG);
7832 if (isUNPCKHMask(NewMask, VT, HasInt256, true))
7833 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG);
7837 // Commute is back and try unpck* again.
7838 // FIXME: this seems wrong.
7839 CommuteVectorShuffleMask(M, NumElems);
7841 std::swap(V1IsSplat, V2IsSplat);
7843 if (isUNPCKLMask(M, VT, HasInt256))
7844 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG);
7846 if (isUNPCKHMask(M, VT, HasInt256))
7847 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG);
7850 // Normalize the node to match x86 shuffle ops if needed
7851 if (!V2IsUndef && (isSHUFPMask(M, VT, /* Commuted */ true)))
7852 return CommuteVectorShuffle(SVOp, DAG);
7854 // The checks below are all present in isShuffleMaskLegal, but they are
7855 // inlined here right now to enable us to directly emit target specific
7856 // nodes, and remove one by one until they don't return Op anymore.
7858 if (ShuffleVectorSDNode::isSplatMask(&M[0], VT) &&
7859 SVOp->getSplatIndex() == 0 && V2IsUndef) {
7860 if (VT == MVT::v2f64 || VT == MVT::v2i64)
7861 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
7864 if (isPSHUFHWMask(M, VT, HasInt256))
7865 return getTargetShuffleNode(X86ISD::PSHUFHW, dl, VT, V1,
7866 getShufflePSHUFHWImmediate(SVOp),
7869 if (isPSHUFLWMask(M, VT, HasInt256))
7870 return getTargetShuffleNode(X86ISD::PSHUFLW, dl, VT, V1,
7871 getShufflePSHUFLWImmediate(SVOp),
7874 if (isSHUFPMask(M, VT))
7875 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V1, V2,
7876 getShuffleSHUFImmediate(SVOp), DAG);
7878 if (isUNPCKL_v_undef_Mask(M, VT, HasInt256))
7879 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
7880 if (isUNPCKH_v_undef_Mask(M, VT, HasInt256))
7881 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
7883 //===--------------------------------------------------------------------===//
7884 // Generate target specific nodes for 128 or 256-bit shuffles only
7885 // supported in the AVX instruction set.
7888 // Handle VMOVDDUPY permutations
7889 if (V2IsUndef && isMOVDDUPYMask(M, VT, HasFp256))
7890 return getTargetShuffleNode(X86ISD::MOVDDUP, dl, VT, V1, DAG);
7892 // Handle VPERMILPS/D* permutations
7893 if (isVPERMILPMask(M, VT)) {
7894 if ((HasInt256 && VT == MVT::v8i32) || VT == MVT::v16i32)
7895 return getTargetShuffleNode(X86ISD::PSHUFD, dl, VT, V1,
7896 getShuffleSHUFImmediate(SVOp), DAG);
7897 return getTargetShuffleNode(X86ISD::VPERMILP, dl, VT, V1,
7898 getShuffleSHUFImmediate(SVOp), DAG);
7902 if (VT.is512BitVector() && isINSERT64x4Mask(M, VT, &Idx))
7903 return Insert256BitVector(V1, Extract256BitVector(V2, 0, DAG, dl),
7904 Idx*(NumElems/2), DAG, dl);
7906 // Handle VPERM2F128/VPERM2I128 permutations
7907 if (isVPERM2X128Mask(M, VT, HasFp256))
7908 return getTargetShuffleNode(X86ISD::VPERM2X128, dl, VT, V1,
7909 V2, getShuffleVPERM2X128Immediate(SVOp), DAG);
7911 SDValue BlendOp = LowerVECTOR_SHUFFLEtoBlend(SVOp, Subtarget, DAG);
7912 if (BlendOp.getNode())
7915 if (Subtarget->hasSSE41() && isINSERTPSMask(M, VT))
7916 return getINSERTPS(SVOp, dl, DAG);
7919 if (V2IsUndef && HasInt256 && isPermImmMask(M, VT, Imm8))
7920 return getTargetShuffleNode(X86ISD::VPERMI, dl, VT, V1, Imm8, DAG);
7922 if ((V2IsUndef && HasInt256 && VT.is256BitVector() && NumElems == 8) ||
7923 VT.is512BitVector()) {
7924 MVT MaskEltVT = MVT::getIntegerVT(VT.getVectorElementType().getSizeInBits());
7925 MVT MaskVectorVT = MVT::getVectorVT(MaskEltVT, NumElems);
7926 SmallVector<SDValue, 16> permclMask;
7927 for (unsigned i = 0; i != NumElems; ++i) {
7928 permclMask.push_back(DAG.getConstant((M[i]>=0) ? M[i] : 0, MaskEltVT));
7931 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, MaskVectorVT, permclMask);
7933 // Bitcast is for VPERMPS since mask is v8i32 but node takes v8f32
7934 return DAG.getNode(X86ISD::VPERMV, dl, VT,
7935 DAG.getNode(ISD::BITCAST, dl, VT, Mask), V1);
7936 return DAG.getNode(X86ISD::VPERMV3, dl, VT, V1,
7937 DAG.getNode(ISD::BITCAST, dl, VT, Mask), V2);
7940 //===--------------------------------------------------------------------===//
7941 // Since no target specific shuffle was selected for this generic one,
7942 // lower it into other known shuffles. FIXME: this isn't true yet, but
7943 // this is the plan.
7946 // Handle v8i16 specifically since SSE can do byte extraction and insertion.
7947 if (VT == MVT::v8i16) {
7948 SDValue NewOp = LowerVECTOR_SHUFFLEv8i16(Op, Subtarget, DAG);
7949 if (NewOp.getNode())
7953 if (VT == MVT::v16i16 && Subtarget->hasInt256()) {
7954 SDValue NewOp = LowerVECTOR_SHUFFLEv16i16(Op, DAG);
7955 if (NewOp.getNode())
7959 if (VT == MVT::v16i8) {
7960 SDValue NewOp = LowerVECTOR_SHUFFLEv16i8(SVOp, Subtarget, DAG);
7961 if (NewOp.getNode())
7965 if (VT == MVT::v32i8) {
7966 SDValue NewOp = LowerVECTOR_SHUFFLEv32i8(SVOp, Subtarget, DAG);
7967 if (NewOp.getNode())
7971 // Handle all 128-bit wide vectors with 4 elements, and match them with
7972 // several different shuffle types.
7973 if (NumElems == 4 && VT.is128BitVector())
7974 return LowerVECTOR_SHUFFLE_128v4(SVOp, DAG);
7976 // Handle general 256-bit shuffles
7977 if (VT.is256BitVector())
7978 return LowerVECTOR_SHUFFLE_256(SVOp, DAG);
7983 // This function assumes its argument is a BUILD_VECTOR of constand or
7984 // undef SDNodes. i.e: ISD::isBuildVectorOfConstantSDNodes(BuildVector) is
7986 static bool BUILD_VECTORtoBlendMask(BuildVectorSDNode *BuildVector,
7987 unsigned &MaskValue) {
7989 unsigned NumElems = BuildVector->getNumOperands();
7990 // There are 2 lanes if (NumElems > 8), and 1 lane otherwise.
7991 unsigned NumLanes = (NumElems - 1) / 8 + 1;
7992 unsigned NumElemsInLane = NumElems / NumLanes;
7994 // Blend for v16i16 should be symetric for the both lanes.
7995 for (unsigned i = 0; i < NumElemsInLane; ++i) {
7996 SDValue EltCond = BuildVector->getOperand(i);
7997 SDValue SndLaneEltCond =
7998 (NumLanes == 2) ? BuildVector->getOperand(i + NumElemsInLane) : EltCond;
8000 int Lane1Cond = -1, Lane2Cond = -1;
8001 if (isa<ConstantSDNode>(EltCond))
8002 Lane1Cond = !isZero(EltCond);
8003 if (isa<ConstantSDNode>(SndLaneEltCond))
8004 Lane2Cond = !isZero(SndLaneEltCond);
8006 if (Lane1Cond == Lane2Cond || Lane2Cond < 0)
8007 MaskValue |= !!Lane1Cond << i;
8008 else if (Lane1Cond < 0)
8009 MaskValue |= !!Lane2Cond << i;
8016 // Try to lower a vselect node into a simple blend instruction.
8017 static SDValue LowerVSELECTtoBlend(SDValue Op, const X86Subtarget *Subtarget,
8018 SelectionDAG &DAG) {
8019 SDValue Cond = Op.getOperand(0);
8020 SDValue LHS = Op.getOperand(1);
8021 SDValue RHS = Op.getOperand(2);
8023 MVT VT = Op.getSimpleValueType();
8024 MVT EltVT = VT.getVectorElementType();
8025 unsigned NumElems = VT.getVectorNumElements();
8027 // There is no blend with immediate in AVX-512.
8028 if (VT.is512BitVector())
8031 if (!Subtarget->hasSSE41() || EltVT == MVT::i8)
8033 if (!Subtarget->hasInt256() && VT == MVT::v16i16)
8036 if (!ISD::isBuildVectorOfConstantSDNodes(Cond.getNode()))
8039 // Check the mask for BLEND and build the value.
8040 unsigned MaskValue = 0;
8041 if (!BUILD_VECTORtoBlendMask(cast<BuildVectorSDNode>(Cond), MaskValue))
8044 // Convert i32 vectors to floating point if it is not AVX2.
8045 // AVX2 introduced VPBLENDD instruction for 128 and 256-bit vectors.
8047 if (EltVT == MVT::i64 || (EltVT == MVT::i32 && !Subtarget->hasInt256())) {
8048 BlendVT = MVT::getVectorVT(MVT::getFloatingPointVT(EltVT.getSizeInBits()),
8050 LHS = DAG.getNode(ISD::BITCAST, dl, VT, LHS);
8051 RHS = DAG.getNode(ISD::BITCAST, dl, VT, RHS);
8054 SDValue Ret = DAG.getNode(X86ISD::BLENDI, dl, BlendVT, LHS, RHS,
8055 DAG.getConstant(MaskValue, MVT::i32));
8056 return DAG.getNode(ISD::BITCAST, dl, VT, Ret);
8059 SDValue X86TargetLowering::LowerVSELECT(SDValue Op, SelectionDAG &DAG) const {
8060 SDValue BlendOp = LowerVSELECTtoBlend(Op, Subtarget, DAG);
8061 if (BlendOp.getNode())
8064 // Some types for vselect were previously set to Expand, not Legal or
8065 // Custom. Return an empty SDValue so we fall-through to Expand, after
8066 // the Custom lowering phase.
8067 MVT VT = Op.getSimpleValueType();
8068 switch (VT.SimpleTy) {
8076 // We couldn't create a "Blend with immediate" node.
8077 // This node should still be legal, but we'll have to emit a blendv*
8082 static SDValue LowerEXTRACT_VECTOR_ELT_SSE4(SDValue Op, SelectionDAG &DAG) {
8083 MVT VT = Op.getSimpleValueType();
8086 if (!Op.getOperand(0).getSimpleValueType().is128BitVector())
8089 if (VT.getSizeInBits() == 8) {
8090 SDValue Extract = DAG.getNode(X86ISD::PEXTRB, dl, MVT::i32,
8091 Op.getOperand(0), Op.getOperand(1));
8092 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
8093 DAG.getValueType(VT));
8094 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
8097 if (VT.getSizeInBits() == 16) {
8098 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
8099 // If Idx is 0, it's cheaper to do a move instead of a pextrw.
8101 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
8102 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
8103 DAG.getNode(ISD::BITCAST, dl,
8107 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, MVT::i32,
8108 Op.getOperand(0), Op.getOperand(1));
8109 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
8110 DAG.getValueType(VT));
8111 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
8114 if (VT == MVT::f32) {
8115 // EXTRACTPS outputs to a GPR32 register which will require a movd to copy
8116 // the result back to FR32 register. It's only worth matching if the
8117 // result has a single use which is a store or a bitcast to i32. And in
8118 // the case of a store, it's not worth it if the index is a constant 0,
8119 // because a MOVSSmr can be used instead, which is smaller and faster.
8120 if (!Op.hasOneUse())
8122 SDNode *User = *Op.getNode()->use_begin();
8123 if ((User->getOpcode() != ISD::STORE ||
8124 (isa<ConstantSDNode>(Op.getOperand(1)) &&
8125 cast<ConstantSDNode>(Op.getOperand(1))->isNullValue())) &&
8126 (User->getOpcode() != ISD::BITCAST ||
8127 User->getValueType(0) != MVT::i32))
8129 SDValue Extract = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
8130 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32,
8133 return DAG.getNode(ISD::BITCAST, dl, MVT::f32, Extract);
8136 if (VT == MVT::i32 || VT == MVT::i64) {
8137 // ExtractPS/pextrq works with constant index.
8138 if (isa<ConstantSDNode>(Op.getOperand(1)))
8144 /// Extract one bit from mask vector, like v16i1 or v8i1.
8145 /// AVX-512 feature.
8147 X86TargetLowering::ExtractBitFromMaskVector(SDValue Op, SelectionDAG &DAG) const {
8148 SDValue Vec = Op.getOperand(0);
8150 MVT VecVT = Vec.getSimpleValueType();
8151 SDValue Idx = Op.getOperand(1);
8152 MVT EltVT = Op.getSimpleValueType();
8154 assert((EltVT == MVT::i1) && "Unexpected operands in ExtractBitFromMaskVector");
8156 // variable index can't be handled in mask registers,
8157 // extend vector to VR512
8158 if (!isa<ConstantSDNode>(Idx)) {
8159 MVT ExtVT = (VecVT == MVT::v8i1 ? MVT::v8i64 : MVT::v16i32);
8160 SDValue Ext = DAG.getNode(ISD::ZERO_EXTEND, dl, ExtVT, Vec);
8161 SDValue Elt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
8162 ExtVT.getVectorElementType(), Ext, Idx);
8163 return DAG.getNode(ISD::TRUNCATE, dl, EltVT, Elt);
8166 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
8167 const TargetRegisterClass* rc = getRegClassFor(VecVT);
8168 unsigned MaxSift = rc->getSize()*8 - 1;
8169 Vec = DAG.getNode(X86ISD::VSHLI, dl, VecVT, Vec,
8170 DAG.getConstant(MaxSift - IdxVal, MVT::i8));
8171 Vec = DAG.getNode(X86ISD::VSRLI, dl, VecVT, Vec,
8172 DAG.getConstant(MaxSift, MVT::i8));
8173 return DAG.getNode(X86ISD::VEXTRACT, dl, MVT::i1, Vec,
8174 DAG.getIntPtrConstant(0));
8178 X86TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op,
8179 SelectionDAG &DAG) const {
8181 SDValue Vec = Op.getOperand(0);
8182 MVT VecVT = Vec.getSimpleValueType();
8183 SDValue Idx = Op.getOperand(1);
8185 if (Op.getSimpleValueType() == MVT::i1)
8186 return ExtractBitFromMaskVector(Op, DAG);
8188 if (!isa<ConstantSDNode>(Idx)) {
8189 if (VecVT.is512BitVector() ||
8190 (VecVT.is256BitVector() && Subtarget->hasInt256() &&
8191 VecVT.getVectorElementType().getSizeInBits() == 32)) {
8194 MVT::getIntegerVT(VecVT.getVectorElementType().getSizeInBits());
8195 MVT MaskVT = MVT::getVectorVT(MaskEltVT, VecVT.getSizeInBits() /
8196 MaskEltVT.getSizeInBits());
8198 Idx = DAG.getZExtOrTrunc(Idx, dl, MaskEltVT);
8199 SDValue Mask = DAG.getNode(X86ISD::VINSERT, dl, MaskVT,
8200 getZeroVector(MaskVT, Subtarget, DAG, dl),
8201 Idx, DAG.getConstant(0, getPointerTy()));
8202 SDValue Perm = DAG.getNode(X86ISD::VPERMV, dl, VecVT, Mask, Vec);
8203 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, Op.getValueType(),
8204 Perm, DAG.getConstant(0, getPointerTy()));
8209 // If this is a 256-bit vector result, first extract the 128-bit vector and
8210 // then extract the element from the 128-bit vector.
8211 if (VecVT.is256BitVector() || VecVT.is512BitVector()) {
8213 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
8214 // Get the 128-bit vector.
8215 Vec = Extract128BitVector(Vec, IdxVal, DAG, dl);
8216 MVT EltVT = VecVT.getVectorElementType();
8218 unsigned ElemsPerChunk = 128 / EltVT.getSizeInBits();
8220 //if (IdxVal >= NumElems/2)
8221 // IdxVal -= NumElems/2;
8222 IdxVal -= (IdxVal/ElemsPerChunk)*ElemsPerChunk;
8223 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, Op.getValueType(), Vec,
8224 DAG.getConstant(IdxVal, MVT::i32));
8227 assert(VecVT.is128BitVector() && "Unexpected vector length");
8229 if (Subtarget->hasSSE41()) {
8230 SDValue Res = LowerEXTRACT_VECTOR_ELT_SSE4(Op, DAG);
8235 MVT VT = Op.getSimpleValueType();
8236 // TODO: handle v16i8.
8237 if (VT.getSizeInBits() == 16) {
8238 SDValue Vec = Op.getOperand(0);
8239 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
8241 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
8242 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
8243 DAG.getNode(ISD::BITCAST, dl,
8246 // Transform it so it match pextrw which produces a 32-bit result.
8247 MVT EltVT = MVT::i32;
8248 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, EltVT,
8249 Op.getOperand(0), Op.getOperand(1));
8250 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, EltVT, Extract,
8251 DAG.getValueType(VT));
8252 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
8255 if (VT.getSizeInBits() == 32) {
8256 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
8260 // SHUFPS the element to the lowest double word, then movss.
8261 int Mask[4] = { static_cast<int>(Idx), -1, -1, -1 };
8262 MVT VVT = Op.getOperand(0).getSimpleValueType();
8263 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
8264 DAG.getUNDEF(VVT), Mask);
8265 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
8266 DAG.getIntPtrConstant(0));
8269 if (VT.getSizeInBits() == 64) {
8270 // FIXME: .td only matches this for <2 x f64>, not <2 x i64> on 32b
8271 // FIXME: seems like this should be unnecessary if mov{h,l}pd were taught
8272 // to match extract_elt for f64.
8273 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
8277 // UNPCKHPD the element to the lowest double word, then movsd.
8278 // Note if the lower 64 bits of the result of the UNPCKHPD is then stored
8279 // to a f64mem, the whole operation is folded into a single MOVHPDmr.
8280 int Mask[2] = { 1, -1 };
8281 MVT VVT = Op.getOperand(0).getSimpleValueType();
8282 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
8283 DAG.getUNDEF(VVT), Mask);
8284 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
8285 DAG.getIntPtrConstant(0));
8291 static SDValue LowerINSERT_VECTOR_ELT_SSE4(SDValue Op, SelectionDAG &DAG) {
8292 MVT VT = Op.getSimpleValueType();
8293 MVT EltVT = VT.getVectorElementType();
8296 SDValue N0 = Op.getOperand(0);
8297 SDValue N1 = Op.getOperand(1);
8298 SDValue N2 = Op.getOperand(2);
8300 if (!VT.is128BitVector())
8303 if ((EltVT.getSizeInBits() == 8 || EltVT.getSizeInBits() == 16) &&
8304 isa<ConstantSDNode>(N2)) {
8306 if (VT == MVT::v8i16)
8307 Opc = X86ISD::PINSRW;
8308 else if (VT == MVT::v16i8)
8309 Opc = X86ISD::PINSRB;
8311 Opc = X86ISD::PINSRB;
8313 // Transform it so it match pinsr{b,w} which expects a GR32 as its second
8315 if (N1.getValueType() != MVT::i32)
8316 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
8317 if (N2.getValueType() != MVT::i32)
8318 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue());
8319 return DAG.getNode(Opc, dl, VT, N0, N1, N2);
8322 if (EltVT == MVT::f32 && isa<ConstantSDNode>(N2)) {
8323 // Bits [7:6] of the constant are the source select. This will always be
8324 // zero here. The DAG Combiner may combine an extract_elt index into these
8325 // bits. For example (insert (extract, 3), 2) could be matched by putting
8326 // the '3' into bits [7:6] of X86ISD::INSERTPS.
8327 // Bits [5:4] of the constant are the destination select. This is the
8328 // value of the incoming immediate.
8329 // Bits [3:0] of the constant are the zero mask. The DAG Combiner may
8330 // combine either bitwise AND or insert of float 0.0 to set these bits.
8331 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue() << 4);
8332 // Create this as a scalar to vector..
8333 N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4f32, N1);
8334 return DAG.getNode(X86ISD::INSERTPS, dl, VT, N0, N1, N2);
8337 if ((EltVT == MVT::i32 || EltVT == MVT::i64) && isa<ConstantSDNode>(N2)) {
8338 // PINSR* works with constant index.
8344 /// Insert one bit to mask vector, like v16i1 or v8i1.
8345 /// AVX-512 feature.
8347 X86TargetLowering::InsertBitToMaskVector(SDValue Op, SelectionDAG &DAG) const {
8349 SDValue Vec = Op.getOperand(0);
8350 SDValue Elt = Op.getOperand(1);
8351 SDValue Idx = Op.getOperand(2);
8352 MVT VecVT = Vec.getSimpleValueType();
8354 if (!isa<ConstantSDNode>(Idx)) {
8355 // Non constant index. Extend source and destination,
8356 // insert element and then truncate the result.
8357 MVT ExtVecVT = (VecVT == MVT::v8i1 ? MVT::v8i64 : MVT::v16i32);
8358 MVT ExtEltVT = (VecVT == MVT::v8i1 ? MVT::i64 : MVT::i32);
8359 SDValue ExtOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, ExtVecVT,
8360 DAG.getNode(ISD::ZERO_EXTEND, dl, ExtVecVT, Vec),
8361 DAG.getNode(ISD::ZERO_EXTEND, dl, ExtEltVT, Elt), Idx);
8362 return DAG.getNode(ISD::TRUNCATE, dl, VecVT, ExtOp);
8365 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
8366 SDValue EltInVec = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Elt);
8367 if (Vec.getOpcode() == ISD::UNDEF)
8368 return DAG.getNode(X86ISD::VSHLI, dl, VecVT, EltInVec,
8369 DAG.getConstant(IdxVal, MVT::i8));
8370 const TargetRegisterClass* rc = getRegClassFor(VecVT);
8371 unsigned MaxSift = rc->getSize()*8 - 1;
8372 EltInVec = DAG.getNode(X86ISD::VSHLI, dl, VecVT, EltInVec,
8373 DAG.getConstant(MaxSift, MVT::i8));
8374 EltInVec = DAG.getNode(X86ISD::VSRLI, dl, VecVT, EltInVec,
8375 DAG.getConstant(MaxSift - IdxVal, MVT::i8));
8376 return DAG.getNode(ISD::OR, dl, VecVT, Vec, EltInVec);
8379 X86TargetLowering::LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const {
8380 MVT VT = Op.getSimpleValueType();
8381 MVT EltVT = VT.getVectorElementType();
8383 if (EltVT == MVT::i1)
8384 return InsertBitToMaskVector(Op, DAG);
8387 SDValue N0 = Op.getOperand(0);
8388 SDValue N1 = Op.getOperand(1);
8389 SDValue N2 = Op.getOperand(2);
8391 // If this is a 256-bit vector result, first extract the 128-bit vector,
8392 // insert the element into the extracted half and then place it back.
8393 if (VT.is256BitVector() || VT.is512BitVector()) {
8394 if (!isa<ConstantSDNode>(N2))
8397 // Get the desired 128-bit vector half.
8398 unsigned IdxVal = cast<ConstantSDNode>(N2)->getZExtValue();
8399 SDValue V = Extract128BitVector(N0, IdxVal, DAG, dl);
8401 // Insert the element into the desired half.
8402 unsigned NumEltsIn128 = 128/EltVT.getSizeInBits();
8403 unsigned IdxIn128 = IdxVal - (IdxVal/NumEltsIn128) * NumEltsIn128;
8405 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, V.getValueType(), V, N1,
8406 DAG.getConstant(IdxIn128, MVT::i32));
8408 // Insert the changed part back to the 256-bit vector
8409 return Insert128BitVector(N0, V, IdxVal, DAG, dl);
8412 if (Subtarget->hasSSE41())
8413 return LowerINSERT_VECTOR_ELT_SSE4(Op, DAG);
8415 if (EltVT == MVT::i8)
8418 if (EltVT.getSizeInBits() == 16 && isa<ConstantSDNode>(N2)) {
8419 // Transform it so it match pinsrw which expects a 16-bit value in a GR32
8420 // as its second argument.
8421 if (N1.getValueType() != MVT::i32)
8422 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
8423 if (N2.getValueType() != MVT::i32)
8424 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue());
8425 return DAG.getNode(X86ISD::PINSRW, dl, VT, N0, N1, N2);
8430 static SDValue LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) {
8432 MVT OpVT = Op.getSimpleValueType();
8434 // If this is a 256-bit vector result, first insert into a 128-bit
8435 // vector and then insert into the 256-bit vector.
8436 if (!OpVT.is128BitVector()) {
8437 // Insert into a 128-bit vector.
8438 unsigned SizeFactor = OpVT.getSizeInBits()/128;
8439 MVT VT128 = MVT::getVectorVT(OpVT.getVectorElementType(),
8440 OpVT.getVectorNumElements() / SizeFactor);
8442 Op = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT128, Op.getOperand(0));
8444 // Insert the 128-bit vector.
8445 return Insert128BitVector(DAG.getUNDEF(OpVT), Op, 0, DAG, dl);
8448 if (OpVT == MVT::v1i64 &&
8449 Op.getOperand(0).getValueType() == MVT::i64)
8450 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v1i64, Op.getOperand(0));
8452 SDValue AnyExt = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, Op.getOperand(0));
8453 assert(OpVT.is128BitVector() && "Expected an SSE type!");
8454 return DAG.getNode(ISD::BITCAST, dl, OpVT,
8455 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,AnyExt));
8458 // Lower a node with an EXTRACT_SUBVECTOR opcode. This may result in
8459 // a simple subregister reference or explicit instructions to grab
8460 // upper bits of a vector.
8461 static SDValue LowerEXTRACT_SUBVECTOR(SDValue Op, const X86Subtarget *Subtarget,
8462 SelectionDAG &DAG) {
8464 SDValue In = Op.getOperand(0);
8465 SDValue Idx = Op.getOperand(1);
8466 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
8467 MVT ResVT = Op.getSimpleValueType();
8468 MVT InVT = In.getSimpleValueType();
8470 if (Subtarget->hasFp256()) {
8471 if (ResVT.is128BitVector() &&
8472 (InVT.is256BitVector() || InVT.is512BitVector()) &&
8473 isa<ConstantSDNode>(Idx)) {
8474 return Extract128BitVector(In, IdxVal, DAG, dl);
8476 if (ResVT.is256BitVector() && InVT.is512BitVector() &&
8477 isa<ConstantSDNode>(Idx)) {
8478 return Extract256BitVector(In, IdxVal, DAG, dl);
8484 // Lower a node with an INSERT_SUBVECTOR opcode. This may result in a
8485 // simple superregister reference or explicit instructions to insert
8486 // the upper bits of a vector.
8487 static SDValue LowerINSERT_SUBVECTOR(SDValue Op, const X86Subtarget *Subtarget,
8488 SelectionDAG &DAG) {
8489 if (Subtarget->hasFp256()) {
8490 SDLoc dl(Op.getNode());
8491 SDValue Vec = Op.getNode()->getOperand(0);
8492 SDValue SubVec = Op.getNode()->getOperand(1);
8493 SDValue Idx = Op.getNode()->getOperand(2);
8495 if ((Op.getNode()->getSimpleValueType(0).is256BitVector() ||
8496 Op.getNode()->getSimpleValueType(0).is512BitVector()) &&
8497 SubVec.getNode()->getSimpleValueType(0).is128BitVector() &&
8498 isa<ConstantSDNode>(Idx)) {
8499 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
8500 return Insert128BitVector(Vec, SubVec, IdxVal, DAG, dl);
8503 if (Op.getNode()->getSimpleValueType(0).is512BitVector() &&
8504 SubVec.getNode()->getSimpleValueType(0).is256BitVector() &&
8505 isa<ConstantSDNode>(Idx)) {
8506 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
8507 return Insert256BitVector(Vec, SubVec, IdxVal, DAG, dl);
8513 // ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as
8514 // their target countpart wrapped in the X86ISD::Wrapper node. Suppose N is
8515 // one of the above mentioned nodes. It has to be wrapped because otherwise
8516 // Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only
8517 // be used to form addressing mode. These wrapped nodes will be selected
8520 X86TargetLowering::LowerConstantPool(SDValue Op, SelectionDAG &DAG) const {
8521 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
8523 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
8525 unsigned char OpFlag = 0;
8526 unsigned WrapperKind = X86ISD::Wrapper;
8527 CodeModel::Model M = getTargetMachine().getCodeModel();
8529 if (Subtarget->isPICStyleRIPRel() &&
8530 (M == CodeModel::Small || M == CodeModel::Kernel))
8531 WrapperKind = X86ISD::WrapperRIP;
8532 else if (Subtarget->isPICStyleGOT())
8533 OpFlag = X86II::MO_GOTOFF;
8534 else if (Subtarget->isPICStyleStubPIC())
8535 OpFlag = X86II::MO_PIC_BASE_OFFSET;
8537 SDValue Result = DAG.getTargetConstantPool(CP->getConstVal(), getPointerTy(),
8539 CP->getOffset(), OpFlag);
8541 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
8542 // With PIC, the address is actually $g + Offset.
8544 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
8545 DAG.getNode(X86ISD::GlobalBaseReg,
8546 SDLoc(), getPointerTy()),
8553 SDValue X86TargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) const {
8554 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
8556 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
8558 unsigned char OpFlag = 0;
8559 unsigned WrapperKind = X86ISD::Wrapper;
8560 CodeModel::Model M = getTargetMachine().getCodeModel();
8562 if (Subtarget->isPICStyleRIPRel() &&
8563 (M == CodeModel::Small || M == CodeModel::Kernel))
8564 WrapperKind = X86ISD::WrapperRIP;
8565 else if (Subtarget->isPICStyleGOT())
8566 OpFlag = X86II::MO_GOTOFF;
8567 else if (Subtarget->isPICStyleStubPIC())
8568 OpFlag = X86II::MO_PIC_BASE_OFFSET;
8570 SDValue Result = DAG.getTargetJumpTable(JT->getIndex(), getPointerTy(),
8573 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
8575 // With PIC, the address is actually $g + Offset.
8577 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
8578 DAG.getNode(X86ISD::GlobalBaseReg,
8579 SDLoc(), getPointerTy()),
8586 X86TargetLowering::LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) const {
8587 const char *Sym = cast<ExternalSymbolSDNode>(Op)->getSymbol();
8589 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
8591 unsigned char OpFlag = 0;
8592 unsigned WrapperKind = X86ISD::Wrapper;
8593 CodeModel::Model M = getTargetMachine().getCodeModel();
8595 if (Subtarget->isPICStyleRIPRel() &&
8596 (M == CodeModel::Small || M == CodeModel::Kernel)) {
8597 if (Subtarget->isTargetDarwin() || Subtarget->isTargetELF())
8598 OpFlag = X86II::MO_GOTPCREL;
8599 WrapperKind = X86ISD::WrapperRIP;
8600 } else if (Subtarget->isPICStyleGOT()) {
8601 OpFlag = X86II::MO_GOT;
8602 } else if (Subtarget->isPICStyleStubPIC()) {
8603 OpFlag = X86II::MO_DARWIN_NONLAZY_PIC_BASE;
8604 } else if (Subtarget->isPICStyleStubNoDynamic()) {
8605 OpFlag = X86II::MO_DARWIN_NONLAZY;
8608 SDValue Result = DAG.getTargetExternalSymbol(Sym, getPointerTy(), OpFlag);
8611 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
8613 // With PIC, the address is actually $g + Offset.
8614 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
8615 !Subtarget->is64Bit()) {
8616 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
8617 DAG.getNode(X86ISD::GlobalBaseReg,
8618 SDLoc(), getPointerTy()),
8622 // For symbols that require a load from a stub to get the address, emit the
8624 if (isGlobalStubReference(OpFlag))
8625 Result = DAG.getLoad(getPointerTy(), DL, DAG.getEntryNode(), Result,
8626 MachinePointerInfo::getGOT(), false, false, false, 0);
8632 X86TargetLowering::LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const {
8633 // Create the TargetBlockAddressAddress node.
8634 unsigned char OpFlags =
8635 Subtarget->ClassifyBlockAddressReference();
8636 CodeModel::Model M = getTargetMachine().getCodeModel();
8637 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
8638 int64_t Offset = cast<BlockAddressSDNode>(Op)->getOffset();
8640 SDValue Result = DAG.getTargetBlockAddress(BA, getPointerTy(), Offset,
8643 if (Subtarget->isPICStyleRIPRel() &&
8644 (M == CodeModel::Small || M == CodeModel::Kernel))
8645 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
8647 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
8649 // With PIC, the address is actually $g + Offset.
8650 if (isGlobalRelativeToPICBase(OpFlags)) {
8651 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
8652 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
8660 X86TargetLowering::LowerGlobalAddress(const GlobalValue *GV, SDLoc dl,
8661 int64_t Offset, SelectionDAG &DAG) const {
8662 // Create the TargetGlobalAddress node, folding in the constant
8663 // offset if it is legal.
8664 unsigned char OpFlags =
8665 Subtarget->ClassifyGlobalReference(GV, getTargetMachine());
8666 CodeModel::Model M = getTargetMachine().getCodeModel();
8668 if (OpFlags == X86II::MO_NO_FLAG &&
8669 X86::isOffsetSuitableForCodeModel(Offset, M)) {
8670 // A direct static reference to a global.
8671 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), Offset);
8674 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), 0, OpFlags);
8677 if (Subtarget->isPICStyleRIPRel() &&
8678 (M == CodeModel::Small || M == CodeModel::Kernel))
8679 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
8681 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
8683 // With PIC, the address is actually $g + Offset.
8684 if (isGlobalRelativeToPICBase(OpFlags)) {
8685 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
8686 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
8690 // For globals that require a load from a stub to get the address, emit the
8692 if (isGlobalStubReference(OpFlags))
8693 Result = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Result,
8694 MachinePointerInfo::getGOT(), false, false, false, 0);
8696 // If there was a non-zero offset that we didn't fold, create an explicit
8699 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(), Result,
8700 DAG.getConstant(Offset, getPointerTy()));
8706 X86TargetLowering::LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const {
8707 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
8708 int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset();
8709 return LowerGlobalAddress(GV, SDLoc(Op), Offset, DAG);
8713 GetTLSADDR(SelectionDAG &DAG, SDValue Chain, GlobalAddressSDNode *GA,
8714 SDValue *InFlag, const EVT PtrVT, unsigned ReturnReg,
8715 unsigned char OperandFlags, bool LocalDynamic = false) {
8716 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
8717 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
8719 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
8720 GA->getValueType(0),
8724 X86ISD::NodeType CallType = LocalDynamic ? X86ISD::TLSBASEADDR
8728 SDValue Ops[] = { Chain, TGA, *InFlag };
8729 Chain = DAG.getNode(CallType, dl, NodeTys, Ops);
8731 SDValue Ops[] = { Chain, TGA };
8732 Chain = DAG.getNode(CallType, dl, NodeTys, Ops);
8735 // TLSADDR will be codegen'ed as call. Inform MFI that function has calls.
8736 MFI->setAdjustsStack(true);
8738 SDValue Flag = Chain.getValue(1);
8739 return DAG.getCopyFromReg(Chain, dl, ReturnReg, PtrVT, Flag);
8742 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 32 bit
8744 LowerToTLSGeneralDynamicModel32(GlobalAddressSDNode *GA, SelectionDAG &DAG,
8747 SDLoc dl(GA); // ? function entry point might be better
8748 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
8749 DAG.getNode(X86ISD::GlobalBaseReg,
8750 SDLoc(), PtrVT), InFlag);
8751 InFlag = Chain.getValue(1);
8753 return GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX, X86II::MO_TLSGD);
8756 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 64 bit
8758 LowerToTLSGeneralDynamicModel64(GlobalAddressSDNode *GA, SelectionDAG &DAG,
8760 return GetTLSADDR(DAG, DAG.getEntryNode(), GA, nullptr, PtrVT,
8761 X86::RAX, X86II::MO_TLSGD);
8764 static SDValue LowerToTLSLocalDynamicModel(GlobalAddressSDNode *GA,
8770 // Get the start address of the TLS block for this module.
8771 X86MachineFunctionInfo* MFI = DAG.getMachineFunction()
8772 .getInfo<X86MachineFunctionInfo>();
8773 MFI->incNumLocalDynamicTLSAccesses();
8777 Base = GetTLSADDR(DAG, DAG.getEntryNode(), GA, nullptr, PtrVT, X86::RAX,
8778 X86II::MO_TLSLD, /*LocalDynamic=*/true);
8781 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
8782 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT), InFlag);
8783 InFlag = Chain.getValue(1);
8784 Base = GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX,
8785 X86II::MO_TLSLDM, /*LocalDynamic=*/true);
8788 // Note: the CleanupLocalDynamicTLSPass will remove redundant computations
8792 unsigned char OperandFlags = X86II::MO_DTPOFF;
8793 unsigned WrapperKind = X86ISD::Wrapper;
8794 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
8795 GA->getValueType(0),
8796 GA->getOffset(), OperandFlags);
8797 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
8799 // Add x@dtpoff with the base.
8800 return DAG.getNode(ISD::ADD, dl, PtrVT, Offset, Base);
8803 // Lower ISD::GlobalTLSAddress using the "initial exec" or "local exec" model.
8804 static SDValue LowerToTLSExecModel(GlobalAddressSDNode *GA, SelectionDAG &DAG,
8805 const EVT PtrVT, TLSModel::Model model,
8806 bool is64Bit, bool isPIC) {
8809 // Get the Thread Pointer, which is %gs:0 (32-bit) or %fs:0 (64-bit).
8810 Value *Ptr = Constant::getNullValue(Type::getInt8PtrTy(*DAG.getContext(),
8811 is64Bit ? 257 : 256));
8813 SDValue ThreadPointer =
8814 DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), DAG.getIntPtrConstant(0),
8815 MachinePointerInfo(Ptr), false, false, false, 0);
8817 unsigned char OperandFlags = 0;
8818 // Most TLS accesses are not RIP relative, even on x86-64. One exception is
8820 unsigned WrapperKind = X86ISD::Wrapper;
8821 if (model == TLSModel::LocalExec) {
8822 OperandFlags = is64Bit ? X86II::MO_TPOFF : X86II::MO_NTPOFF;
8823 } else if (model == TLSModel::InitialExec) {
8825 OperandFlags = X86II::MO_GOTTPOFF;
8826 WrapperKind = X86ISD::WrapperRIP;
8828 OperandFlags = isPIC ? X86II::MO_GOTNTPOFF : X86II::MO_INDNTPOFF;
8831 llvm_unreachable("Unexpected model");
8834 // emit "addl x@ntpoff,%eax" (local exec)
8835 // or "addl x@indntpoff,%eax" (initial exec)
8836 // or "addl x@gotntpoff(%ebx) ,%eax" (initial exec, 32-bit pic)
8838 DAG.getTargetGlobalAddress(GA->getGlobal(), dl, GA->getValueType(0),
8839 GA->getOffset(), OperandFlags);
8840 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
8842 if (model == TLSModel::InitialExec) {
8843 if (isPIC && !is64Bit) {
8844 Offset = DAG.getNode(ISD::ADD, dl, PtrVT,
8845 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT),
8849 Offset = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Offset,
8850 MachinePointerInfo::getGOT(), false, false, false, 0);
8853 // The address of the thread local variable is the add of the thread
8854 // pointer with the offset of the variable.
8855 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset);
8859 X86TargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const {
8861 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
8862 const GlobalValue *GV = GA->getGlobal();
8864 if (Subtarget->isTargetELF()) {
8865 TLSModel::Model model = getTargetMachine().getTLSModel(GV);
8868 case TLSModel::GeneralDynamic:
8869 if (Subtarget->is64Bit())
8870 return LowerToTLSGeneralDynamicModel64(GA, DAG, getPointerTy());
8871 return LowerToTLSGeneralDynamicModel32(GA, DAG, getPointerTy());
8872 case TLSModel::LocalDynamic:
8873 return LowerToTLSLocalDynamicModel(GA, DAG, getPointerTy(),
8874 Subtarget->is64Bit());
8875 case TLSModel::InitialExec:
8876 case TLSModel::LocalExec:
8877 return LowerToTLSExecModel(GA, DAG, getPointerTy(), model,
8878 Subtarget->is64Bit(),
8879 getTargetMachine().getRelocationModel() == Reloc::PIC_);
8881 llvm_unreachable("Unknown TLS model.");
8884 if (Subtarget->isTargetDarwin()) {
8885 // Darwin only has one model of TLS. Lower to that.
8886 unsigned char OpFlag = 0;
8887 unsigned WrapperKind = Subtarget->isPICStyleRIPRel() ?
8888 X86ISD::WrapperRIP : X86ISD::Wrapper;
8890 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
8892 bool PIC32 = (getTargetMachine().getRelocationModel() == Reloc::PIC_) &&
8893 !Subtarget->is64Bit();
8895 OpFlag = X86II::MO_TLVP_PIC_BASE;
8897 OpFlag = X86II::MO_TLVP;
8899 SDValue Result = DAG.getTargetGlobalAddress(GA->getGlobal(), DL,
8900 GA->getValueType(0),
8901 GA->getOffset(), OpFlag);
8902 SDValue Offset = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
8904 // With PIC32, the address is actually $g + Offset.
8906 Offset = DAG.getNode(ISD::ADD, DL, getPointerTy(),
8907 DAG.getNode(X86ISD::GlobalBaseReg,
8908 SDLoc(), getPointerTy()),
8911 // Lowering the machine isd will make sure everything is in the right
8913 SDValue Chain = DAG.getEntryNode();
8914 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
8915 SDValue Args[] = { Chain, Offset };
8916 Chain = DAG.getNode(X86ISD::TLSCALL, DL, NodeTys, Args);
8918 // TLSCALL will be codegen'ed as call. Inform MFI that function has calls.
8919 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
8920 MFI->setAdjustsStack(true);
8922 // And our return value (tls address) is in the standard call return value
8924 unsigned Reg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
8925 return DAG.getCopyFromReg(Chain, DL, Reg, getPointerTy(),
8929 if (Subtarget->isTargetKnownWindowsMSVC() ||
8930 Subtarget->isTargetWindowsGNU()) {
8931 // Just use the implicit TLS architecture
8932 // Need to generate someting similar to:
8933 // mov rdx, qword [gs:abs 58H]; Load pointer to ThreadLocalStorage
8935 // mov ecx, dword [rel _tls_index]: Load index (from C runtime)
8936 // mov rcx, qword [rdx+rcx*8]
8937 // mov eax, .tls$:tlsvar
8938 // [rax+rcx] contains the address
8939 // Windows 64bit: gs:0x58
8940 // Windows 32bit: fs:__tls_array
8942 // If GV is an alias then use the aliasee for determining
8943 // thread-localness.
8944 if (const GlobalAlias *GA = dyn_cast<GlobalAlias>(GV))
8945 GV = GA->getAliasee();
8947 SDValue Chain = DAG.getEntryNode();
8949 // Get the Thread Pointer, which is %fs:__tls_array (32-bit) or
8950 // %gs:0x58 (64-bit). On MinGW, __tls_array is not available, so directly
8951 // use its literal value of 0x2C.
8952 Value *Ptr = Constant::getNullValue(Subtarget->is64Bit()
8953 ? Type::getInt8PtrTy(*DAG.getContext(),
8955 : Type::getInt32PtrTy(*DAG.getContext(),
8959 Subtarget->is64Bit()
8960 ? DAG.getIntPtrConstant(0x58)
8961 : (Subtarget->isTargetWindowsGNU()
8962 ? DAG.getIntPtrConstant(0x2C)
8963 : DAG.getExternalSymbol("_tls_array", getPointerTy()));
8965 SDValue ThreadPointer =
8966 DAG.getLoad(getPointerTy(), dl, Chain, TlsArray,
8967 MachinePointerInfo(Ptr), false, false, false, 0);
8969 // Load the _tls_index variable
8970 SDValue IDX = DAG.getExternalSymbol("_tls_index", getPointerTy());
8971 if (Subtarget->is64Bit())
8972 IDX = DAG.getExtLoad(ISD::ZEXTLOAD, dl, getPointerTy(), Chain,
8973 IDX, MachinePointerInfo(), MVT::i32,
8976 IDX = DAG.getLoad(getPointerTy(), dl, Chain, IDX, MachinePointerInfo(),
8977 false, false, false, 0);
8979 SDValue Scale = DAG.getConstant(Log2_64_Ceil(TD->getPointerSize()),
8981 IDX = DAG.getNode(ISD::SHL, dl, getPointerTy(), IDX, Scale);
8983 SDValue res = DAG.getNode(ISD::ADD, dl, getPointerTy(), ThreadPointer, IDX);
8984 res = DAG.getLoad(getPointerTy(), dl, Chain, res, MachinePointerInfo(),
8985 false, false, false, 0);
8987 // Get the offset of start of .tls section
8988 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
8989 GA->getValueType(0),
8990 GA->getOffset(), X86II::MO_SECREL);
8991 SDValue Offset = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), TGA);
8993 // The address of the thread local variable is the add of the thread
8994 // pointer with the offset of the variable.
8995 return DAG.getNode(ISD::ADD, dl, getPointerTy(), res, Offset);
8998 llvm_unreachable("TLS not implemented for this target.");
9001 /// LowerShiftParts - Lower SRA_PARTS and friends, which return two i32 values
9002 /// and take a 2 x i32 value to shift plus a shift amount.
9003 static SDValue LowerShiftParts(SDValue Op, SelectionDAG &DAG) {
9004 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
9005 MVT VT = Op.getSimpleValueType();
9006 unsigned VTBits = VT.getSizeInBits();
9008 bool isSRA = Op.getOpcode() == ISD::SRA_PARTS;
9009 SDValue ShOpLo = Op.getOperand(0);
9010 SDValue ShOpHi = Op.getOperand(1);
9011 SDValue ShAmt = Op.getOperand(2);
9012 // X86ISD::SHLD and X86ISD::SHRD have defined overflow behavior but the
9013 // generic ISD nodes haven't. Insert an AND to be safe, it's optimized away
9015 SDValue SafeShAmt = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt,
9016 DAG.getConstant(VTBits - 1, MVT::i8));
9017 SDValue Tmp1 = isSRA ? DAG.getNode(ISD::SRA, dl, VT, ShOpHi,
9018 DAG.getConstant(VTBits - 1, MVT::i8))
9019 : DAG.getConstant(0, VT);
9022 if (Op.getOpcode() == ISD::SHL_PARTS) {
9023 Tmp2 = DAG.getNode(X86ISD::SHLD, dl, VT, ShOpHi, ShOpLo, ShAmt);
9024 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, SafeShAmt);
9026 Tmp2 = DAG.getNode(X86ISD::SHRD, dl, VT, ShOpLo, ShOpHi, ShAmt);
9027 Tmp3 = DAG.getNode(isSRA ? ISD::SRA : ISD::SRL, dl, VT, ShOpHi, SafeShAmt);
9030 // If the shift amount is larger or equal than the width of a part we can't
9031 // rely on the results of shld/shrd. Insert a test and select the appropriate
9032 // values for large shift amounts.
9033 SDValue AndNode = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt,
9034 DAG.getConstant(VTBits, MVT::i8));
9035 SDValue Cond = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
9036 AndNode, DAG.getConstant(0, MVT::i8));
9039 SDValue CC = DAG.getConstant(X86::COND_NE, MVT::i8);
9040 SDValue Ops0[4] = { Tmp2, Tmp3, CC, Cond };
9041 SDValue Ops1[4] = { Tmp3, Tmp1, CC, Cond };
9043 if (Op.getOpcode() == ISD::SHL_PARTS) {
9044 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0);
9045 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1);
9047 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0);
9048 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1);
9051 SDValue Ops[2] = { Lo, Hi };
9052 return DAG.getMergeValues(Ops, dl);
9055 SDValue X86TargetLowering::LowerSINT_TO_FP(SDValue Op,
9056 SelectionDAG &DAG) const {
9057 MVT SrcVT = Op.getOperand(0).getSimpleValueType();
9059 if (SrcVT.isVector())
9062 assert(SrcVT <= MVT::i64 && SrcVT >= MVT::i16 &&
9063 "Unknown SINT_TO_FP to lower!");
9065 // These are really Legal; return the operand so the caller accepts it as
9067 if (SrcVT == MVT::i32 && isScalarFPTypeInSSEReg(Op.getValueType()))
9069 if (SrcVT == MVT::i64 && isScalarFPTypeInSSEReg(Op.getValueType()) &&
9070 Subtarget->is64Bit()) {
9075 unsigned Size = SrcVT.getSizeInBits()/8;
9076 MachineFunction &MF = DAG.getMachineFunction();
9077 int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size, false);
9078 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
9079 SDValue Chain = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
9081 MachinePointerInfo::getFixedStack(SSFI),
9083 return BuildFILD(Op, SrcVT, Chain, StackSlot, DAG);
9086 SDValue X86TargetLowering::BuildFILD(SDValue Op, EVT SrcVT, SDValue Chain,
9088 SelectionDAG &DAG) const {
9092 bool useSSE = isScalarFPTypeInSSEReg(Op.getValueType());
9094 Tys = DAG.getVTList(MVT::f64, MVT::Other, MVT::Glue);
9096 Tys = DAG.getVTList(Op.getValueType(), MVT::Other);
9098 unsigned ByteSize = SrcVT.getSizeInBits()/8;
9100 FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(StackSlot);
9101 MachineMemOperand *MMO;
9103 int SSFI = FI->getIndex();
9105 DAG.getMachineFunction()
9106 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
9107 MachineMemOperand::MOLoad, ByteSize, ByteSize);
9109 MMO = cast<LoadSDNode>(StackSlot)->getMemOperand();
9110 StackSlot = StackSlot.getOperand(1);
9112 SDValue Ops[] = { Chain, StackSlot, DAG.getValueType(SrcVT) };
9113 SDValue Result = DAG.getMemIntrinsicNode(useSSE ? X86ISD::FILD_FLAG :
9115 Tys, Ops, SrcVT, MMO);
9118 Chain = Result.getValue(1);
9119 SDValue InFlag = Result.getValue(2);
9121 // FIXME: Currently the FST is flagged to the FILD_FLAG. This
9122 // shouldn't be necessary except that RFP cannot be live across
9123 // multiple blocks. When stackifier is fixed, they can be uncoupled.
9124 MachineFunction &MF = DAG.getMachineFunction();
9125 unsigned SSFISize = Op.getValueType().getSizeInBits()/8;
9126 int SSFI = MF.getFrameInfo()->CreateStackObject(SSFISize, SSFISize, false);
9127 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
9128 Tys = DAG.getVTList(MVT::Other);
9130 Chain, Result, StackSlot, DAG.getValueType(Op.getValueType()), InFlag
9132 MachineMemOperand *MMO =
9133 DAG.getMachineFunction()
9134 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
9135 MachineMemOperand::MOStore, SSFISize, SSFISize);
9137 Chain = DAG.getMemIntrinsicNode(X86ISD::FST, DL, Tys,
9138 Ops, Op.getValueType(), MMO);
9139 Result = DAG.getLoad(Op.getValueType(), DL, Chain, StackSlot,
9140 MachinePointerInfo::getFixedStack(SSFI),
9141 false, false, false, 0);
9147 // LowerUINT_TO_FP_i64 - 64-bit unsigned integer to double expansion.
9148 SDValue X86TargetLowering::LowerUINT_TO_FP_i64(SDValue Op,
9149 SelectionDAG &DAG) const {
9150 // This algorithm is not obvious. Here it is what we're trying to output:
9153 punpckldq (c0), %xmm0 // c0: (uint4){ 0x43300000U, 0x45300000U, 0U, 0U }
9154 subpd (c1), %xmm0 // c1: (double2){ 0x1.0p52, 0x1.0p52 * 0x1.0p32 }
9158 pshufd $0x4e, %xmm0, %xmm1
9164 LLVMContext *Context = DAG.getContext();
9166 // Build some magic constants.
9167 static const uint32_t CV0[] = { 0x43300000, 0x45300000, 0, 0 };
9168 Constant *C0 = ConstantDataVector::get(*Context, CV0);
9169 SDValue CPIdx0 = DAG.getConstantPool(C0, getPointerTy(), 16);
9171 SmallVector<Constant*,2> CV1;
9173 ConstantFP::get(*Context, APFloat(APFloat::IEEEdouble,
9174 APInt(64, 0x4330000000000000ULL))));
9176 ConstantFP::get(*Context, APFloat(APFloat::IEEEdouble,
9177 APInt(64, 0x4530000000000000ULL))));
9178 Constant *C1 = ConstantVector::get(CV1);
9179 SDValue CPIdx1 = DAG.getConstantPool(C1, getPointerTy(), 16);
9181 // Load the 64-bit value into an XMM register.
9182 SDValue XR1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
9184 SDValue CLod0 = DAG.getLoad(MVT::v4i32, dl, DAG.getEntryNode(), CPIdx0,
9185 MachinePointerInfo::getConstantPool(),
9186 false, false, false, 16);
9187 SDValue Unpck1 = getUnpackl(DAG, dl, MVT::v4i32,
9188 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, XR1),
9191 SDValue CLod1 = DAG.getLoad(MVT::v2f64, dl, CLod0.getValue(1), CPIdx1,
9192 MachinePointerInfo::getConstantPool(),
9193 false, false, false, 16);
9194 SDValue XR2F = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Unpck1);
9195 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, XR2F, CLod1);
9198 if (Subtarget->hasSSE3()) {
9199 // FIXME: The 'haddpd' instruction may be slower than 'movhlps + addsd'.
9200 Result = DAG.getNode(X86ISD::FHADD, dl, MVT::v2f64, Sub, Sub);
9202 SDValue S2F = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Sub);
9203 SDValue Shuffle = getTargetShuffleNode(X86ISD::PSHUFD, dl, MVT::v4i32,
9205 Result = DAG.getNode(ISD::FADD, dl, MVT::v2f64,
9206 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Shuffle),
9210 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Result,
9211 DAG.getIntPtrConstant(0));
9214 // LowerUINT_TO_FP_i32 - 32-bit unsigned integer to float expansion.
9215 SDValue X86TargetLowering::LowerUINT_TO_FP_i32(SDValue Op,
9216 SelectionDAG &DAG) const {
9218 // FP constant to bias correct the final result.
9219 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL),
9222 // Load the 32-bit value into an XMM register.
9223 SDValue Load = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,
9226 // Zero out the upper parts of the register.
9227 Load = getShuffleVectorZeroOrUndef(Load, 0, true, Subtarget, DAG);
9229 Load = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
9230 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Load),
9231 DAG.getIntPtrConstant(0));
9233 // Or the load with the bias.
9234 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64,
9235 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
9236 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
9238 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
9239 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
9240 MVT::v2f64, Bias)));
9241 Or = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
9242 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Or),
9243 DAG.getIntPtrConstant(0));
9245 // Subtract the bias.
9246 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Or, Bias);
9248 // Handle final rounding.
9249 EVT DestVT = Op.getValueType();
9251 if (DestVT.bitsLT(MVT::f64))
9252 return DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub,
9253 DAG.getIntPtrConstant(0));
9254 if (DestVT.bitsGT(MVT::f64))
9255 return DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub);
9257 // Handle final rounding.
9261 SDValue X86TargetLowering::lowerUINT_TO_FP_vec(SDValue Op,
9262 SelectionDAG &DAG) const {
9263 SDValue N0 = Op.getOperand(0);
9264 MVT SVT = N0.getSimpleValueType();
9267 assert((SVT == MVT::v4i8 || SVT == MVT::v4i16 ||
9268 SVT == MVT::v8i8 || SVT == MVT::v8i16) &&
9269 "Custom UINT_TO_FP is not supported!");
9271 MVT NVT = MVT::getVectorVT(MVT::i32, SVT.getVectorNumElements());
9272 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(),
9273 DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, N0));
9276 SDValue X86TargetLowering::LowerUINT_TO_FP(SDValue Op,
9277 SelectionDAG &DAG) const {
9278 SDValue N0 = Op.getOperand(0);
9281 if (Op.getValueType().isVector())
9282 return lowerUINT_TO_FP_vec(Op, DAG);
9284 // Since UINT_TO_FP is legal (it's marked custom), dag combiner won't
9285 // optimize it to a SINT_TO_FP when the sign bit is known zero. Perform
9286 // the optimization here.
9287 if (DAG.SignBitIsZero(N0))
9288 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(), N0);
9290 MVT SrcVT = N0.getSimpleValueType();
9291 MVT DstVT = Op.getSimpleValueType();
9292 if (SrcVT == MVT::i64 && DstVT == MVT::f64 && X86ScalarSSEf64)
9293 return LowerUINT_TO_FP_i64(Op, DAG);
9294 if (SrcVT == MVT::i32 && X86ScalarSSEf64)
9295 return LowerUINT_TO_FP_i32(Op, DAG);
9296 if (Subtarget->is64Bit() && SrcVT == MVT::i64 && DstVT == MVT::f32)
9299 // Make a 64-bit buffer, and use it to build an FILD.
9300 SDValue StackSlot = DAG.CreateStackTemporary(MVT::i64);
9301 if (SrcVT == MVT::i32) {
9302 SDValue WordOff = DAG.getConstant(4, getPointerTy());
9303 SDValue OffsetSlot = DAG.getNode(ISD::ADD, dl,
9304 getPointerTy(), StackSlot, WordOff);
9305 SDValue Store1 = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
9306 StackSlot, MachinePointerInfo(),
9308 SDValue Store2 = DAG.getStore(Store1, dl, DAG.getConstant(0, MVT::i32),
9309 OffsetSlot, MachinePointerInfo(),
9311 SDValue Fild = BuildFILD(Op, MVT::i64, Store2, StackSlot, DAG);
9315 assert(SrcVT == MVT::i64 && "Unexpected type in UINT_TO_FP");
9316 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
9317 StackSlot, MachinePointerInfo(),
9319 // For i64 source, we need to add the appropriate power of 2 if the input
9320 // was negative. This is the same as the optimization in
9321 // DAGTypeLegalizer::ExpandIntOp_UNIT_TO_FP, and for it to be safe here,
9322 // we must be careful to do the computation in x87 extended precision, not
9323 // in SSE. (The generic code can't know it's OK to do this, or how to.)
9324 int SSFI = cast<FrameIndexSDNode>(StackSlot)->getIndex();
9325 MachineMemOperand *MMO =
9326 DAG.getMachineFunction()
9327 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
9328 MachineMemOperand::MOLoad, 8, 8);
9330 SDVTList Tys = DAG.getVTList(MVT::f80, MVT::Other);
9331 SDValue Ops[] = { Store, StackSlot, DAG.getValueType(MVT::i64) };
9332 SDValue Fild = DAG.getMemIntrinsicNode(X86ISD::FILD, dl, Tys, Ops,
9335 APInt FF(32, 0x5F800000ULL);
9337 // Check whether the sign bit is set.
9338 SDValue SignSet = DAG.getSetCC(dl,
9339 getSetCCResultType(*DAG.getContext(), MVT::i64),
9340 Op.getOperand(0), DAG.getConstant(0, MVT::i64),
9343 // Build a 64 bit pair (0, FF) in the constant pool, with FF in the lo bits.
9344 SDValue FudgePtr = DAG.getConstantPool(
9345 ConstantInt::get(*DAG.getContext(), FF.zext(64)),
9348 // Get a pointer to FF if the sign bit was set, or to 0 otherwise.
9349 SDValue Zero = DAG.getIntPtrConstant(0);
9350 SDValue Four = DAG.getIntPtrConstant(4);
9351 SDValue Offset = DAG.getNode(ISD::SELECT, dl, Zero.getValueType(), SignSet,
9353 FudgePtr = DAG.getNode(ISD::ADD, dl, getPointerTy(), FudgePtr, Offset);
9355 // Load the value out, extending it from f32 to f80.
9356 // FIXME: Avoid the extend by constructing the right constant pool?
9357 SDValue Fudge = DAG.getExtLoad(ISD::EXTLOAD, dl, MVT::f80, DAG.getEntryNode(),
9358 FudgePtr, MachinePointerInfo::getConstantPool(),
9359 MVT::f32, false, false, 4);
9360 // Extend everything to 80 bits to force it to be done on x87.
9361 SDValue Add = DAG.getNode(ISD::FADD, dl, MVT::f80, Fild, Fudge);
9362 return DAG.getNode(ISD::FP_ROUND, dl, DstVT, Add, DAG.getIntPtrConstant(0));
9365 std::pair<SDValue,SDValue>
9366 X86TargetLowering:: FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG,
9367 bool IsSigned, bool IsReplace) const {
9370 EVT DstTy = Op.getValueType();
9372 if (!IsSigned && !isIntegerTypeFTOL(DstTy)) {
9373 assert(DstTy == MVT::i32 && "Unexpected FP_TO_UINT");
9377 assert(DstTy.getSimpleVT() <= MVT::i64 &&
9378 DstTy.getSimpleVT() >= MVT::i16 &&
9379 "Unknown FP_TO_INT to lower!");
9381 // These are really Legal.
9382 if (DstTy == MVT::i32 &&
9383 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
9384 return std::make_pair(SDValue(), SDValue());
9385 if (Subtarget->is64Bit() &&
9386 DstTy == MVT::i64 &&
9387 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
9388 return std::make_pair(SDValue(), SDValue());
9390 // We lower FP->int64 either into FISTP64 followed by a load from a temporary
9391 // stack slot, or into the FTOL runtime function.
9392 MachineFunction &MF = DAG.getMachineFunction();
9393 unsigned MemSize = DstTy.getSizeInBits()/8;
9394 int SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
9395 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
9398 if (!IsSigned && isIntegerTypeFTOL(DstTy))
9399 Opc = X86ISD::WIN_FTOL;
9401 switch (DstTy.getSimpleVT().SimpleTy) {
9402 default: llvm_unreachable("Invalid FP_TO_SINT to lower!");
9403 case MVT::i16: Opc = X86ISD::FP_TO_INT16_IN_MEM; break;
9404 case MVT::i32: Opc = X86ISD::FP_TO_INT32_IN_MEM; break;
9405 case MVT::i64: Opc = X86ISD::FP_TO_INT64_IN_MEM; break;
9408 SDValue Chain = DAG.getEntryNode();
9409 SDValue Value = Op.getOperand(0);
9410 EVT TheVT = Op.getOperand(0).getValueType();
9411 // FIXME This causes a redundant load/store if the SSE-class value is already
9412 // in memory, such as if it is on the callstack.
9413 if (isScalarFPTypeInSSEReg(TheVT)) {
9414 assert(DstTy == MVT::i64 && "Invalid FP_TO_SINT to lower!");
9415 Chain = DAG.getStore(Chain, DL, Value, StackSlot,
9416 MachinePointerInfo::getFixedStack(SSFI),
9418 SDVTList Tys = DAG.getVTList(Op.getOperand(0).getValueType(), MVT::Other);
9420 Chain, StackSlot, DAG.getValueType(TheVT)
9423 MachineMemOperand *MMO =
9424 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
9425 MachineMemOperand::MOLoad, MemSize, MemSize);
9426 Value = DAG.getMemIntrinsicNode(X86ISD::FLD, DL, Tys, Ops, DstTy, MMO);
9427 Chain = Value.getValue(1);
9428 SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
9429 StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
9432 MachineMemOperand *MMO =
9433 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
9434 MachineMemOperand::MOStore, MemSize, MemSize);
9436 if (Opc != X86ISD::WIN_FTOL) {
9437 // Build the FP_TO_INT*_IN_MEM
9438 SDValue Ops[] = { Chain, Value, StackSlot };
9439 SDValue FIST = DAG.getMemIntrinsicNode(Opc, DL, DAG.getVTList(MVT::Other),
9441 return std::make_pair(FIST, StackSlot);
9443 SDValue ftol = DAG.getNode(X86ISD::WIN_FTOL, DL,
9444 DAG.getVTList(MVT::Other, MVT::Glue),
9446 SDValue eax = DAG.getCopyFromReg(ftol, DL, X86::EAX,
9447 MVT::i32, ftol.getValue(1));
9448 SDValue edx = DAG.getCopyFromReg(eax.getValue(1), DL, X86::EDX,
9449 MVT::i32, eax.getValue(2));
9450 SDValue Ops[] = { eax, edx };
9451 SDValue pair = IsReplace
9452 ? DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops)
9453 : DAG.getMergeValues(Ops, DL);
9454 return std::make_pair(pair, SDValue());
9458 static SDValue LowerAVXExtend(SDValue Op, SelectionDAG &DAG,
9459 const X86Subtarget *Subtarget) {
9460 MVT VT = Op->getSimpleValueType(0);
9461 SDValue In = Op->getOperand(0);
9462 MVT InVT = In.getSimpleValueType();
9465 // Optimize vectors in AVX mode:
9468 // Use vpunpcklwd for 4 lower elements v8i16 -> v4i32.
9469 // Use vpunpckhwd for 4 upper elements v8i16 -> v4i32.
9470 // Concat upper and lower parts.
9473 // Use vpunpckldq for 4 lower elements v4i32 -> v2i64.
9474 // Use vpunpckhdq for 4 upper elements v4i32 -> v2i64.
9475 // Concat upper and lower parts.
9478 if (((VT != MVT::v16i16) || (InVT != MVT::v16i8)) &&
9479 ((VT != MVT::v8i32) || (InVT != MVT::v8i16)) &&
9480 ((VT != MVT::v4i64) || (InVT != MVT::v4i32)))
9483 if (Subtarget->hasInt256())
9484 return DAG.getNode(X86ISD::VZEXT, dl, VT, In);
9486 SDValue ZeroVec = getZeroVector(InVT, Subtarget, DAG, dl);
9487 SDValue Undef = DAG.getUNDEF(InVT);
9488 bool NeedZero = Op.getOpcode() == ISD::ZERO_EXTEND;
9489 SDValue OpLo = getUnpackl(DAG, dl, InVT, In, NeedZero ? ZeroVec : Undef);
9490 SDValue OpHi = getUnpackh(DAG, dl, InVT, In, NeedZero ? ZeroVec : Undef);
9492 MVT HVT = MVT::getVectorVT(VT.getVectorElementType(),
9493 VT.getVectorNumElements()/2);
9495 OpLo = DAG.getNode(ISD::BITCAST, dl, HVT, OpLo);
9496 OpHi = DAG.getNode(ISD::BITCAST, dl, HVT, OpHi);
9498 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi);
9501 static SDValue LowerZERO_EXTEND_AVX512(SDValue Op,
9502 SelectionDAG &DAG) {
9503 MVT VT = Op->getSimpleValueType(0);
9504 SDValue In = Op->getOperand(0);
9505 MVT InVT = In.getSimpleValueType();
9507 unsigned int NumElts = VT.getVectorNumElements();
9508 if (NumElts != 8 && NumElts != 16)
9511 if (VT.is512BitVector() && InVT.getVectorElementType() != MVT::i1)
9512 return DAG.getNode(X86ISD::VZEXT, DL, VT, In);
9514 EVT ExtVT = (NumElts == 8)? MVT::v8i64 : MVT::v16i32;
9515 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
9516 // Now we have only mask extension
9517 assert(InVT.getVectorElementType() == MVT::i1);
9518 SDValue Cst = DAG.getTargetConstant(1, ExtVT.getScalarType());
9519 const Constant *C = (dyn_cast<ConstantSDNode>(Cst))->getConstantIntValue();
9520 SDValue CP = DAG.getConstantPool(C, TLI.getPointerTy());
9521 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
9522 SDValue Ld = DAG.getLoad(Cst.getValueType(), DL, DAG.getEntryNode(), CP,
9523 MachinePointerInfo::getConstantPool(),
9524 false, false, false, Alignment);
9526 SDValue Brcst = DAG.getNode(X86ISD::VBROADCASTM, DL, ExtVT, In, Ld);
9527 if (VT.is512BitVector())
9529 return DAG.getNode(X86ISD::VTRUNC, DL, VT, Brcst);
9532 static SDValue LowerANY_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
9533 SelectionDAG &DAG) {
9534 if (Subtarget->hasFp256()) {
9535 SDValue Res = LowerAVXExtend(Op, DAG, Subtarget);
9543 static SDValue LowerZERO_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
9544 SelectionDAG &DAG) {
9546 MVT VT = Op.getSimpleValueType();
9547 SDValue In = Op.getOperand(0);
9548 MVT SVT = In.getSimpleValueType();
9550 if (VT.is512BitVector() || SVT.getVectorElementType() == MVT::i1)
9551 return LowerZERO_EXTEND_AVX512(Op, DAG);
9553 if (Subtarget->hasFp256()) {
9554 SDValue Res = LowerAVXExtend(Op, DAG, Subtarget);
9559 assert(!VT.is256BitVector() || !SVT.is128BitVector() ||
9560 VT.getVectorNumElements() != SVT.getVectorNumElements());
9564 SDValue X86TargetLowering::LowerTRUNCATE(SDValue Op, SelectionDAG &DAG) const {
9566 MVT VT = Op.getSimpleValueType();
9567 SDValue In = Op.getOperand(0);
9568 MVT InVT = In.getSimpleValueType();
9570 if (VT == MVT::i1) {
9571 assert((InVT.isInteger() && (InVT.getSizeInBits() <= 64)) &&
9572 "Invalid scalar TRUNCATE operation");
9573 if (InVT == MVT::i32)
9575 if (InVT.getSizeInBits() == 64)
9576 In = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::i32, In);
9577 else if (InVT.getSizeInBits() < 32)
9578 In = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i32, In);
9579 return DAG.getNode(ISD::TRUNCATE, DL, VT, In);
9581 assert(VT.getVectorNumElements() == InVT.getVectorNumElements() &&
9582 "Invalid TRUNCATE operation");
9584 if (InVT.is512BitVector() || VT.getVectorElementType() == MVT::i1) {
9585 if (VT.getVectorElementType().getSizeInBits() >=8)
9586 return DAG.getNode(X86ISD::VTRUNC, DL, VT, In);
9588 assert(VT.getVectorElementType() == MVT::i1 && "Unexpected vector type");
9589 unsigned NumElts = InVT.getVectorNumElements();
9590 assert ((NumElts == 8 || NumElts == 16) && "Unexpected vector type");
9591 if (InVT.getSizeInBits() < 512) {
9592 MVT ExtVT = (NumElts == 16)? MVT::v16i32 : MVT::v8i64;
9593 In = DAG.getNode(ISD::SIGN_EXTEND, DL, ExtVT, In);
9597 SDValue Cst = DAG.getTargetConstant(1, InVT.getVectorElementType());
9598 const Constant *C = (dyn_cast<ConstantSDNode>(Cst))->getConstantIntValue();
9599 SDValue CP = DAG.getConstantPool(C, getPointerTy());
9600 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
9601 SDValue Ld = DAG.getLoad(Cst.getValueType(), DL, DAG.getEntryNode(), CP,
9602 MachinePointerInfo::getConstantPool(),
9603 false, false, false, Alignment);
9604 SDValue OneV = DAG.getNode(X86ISD::VBROADCAST, DL, InVT, Ld);
9605 SDValue And = DAG.getNode(ISD::AND, DL, InVT, OneV, In);
9606 return DAG.getNode(X86ISD::TESTM, DL, VT, And, And);
9609 if ((VT == MVT::v4i32) && (InVT == MVT::v4i64)) {
9610 // On AVX2, v4i64 -> v4i32 becomes VPERMD.
9611 if (Subtarget->hasInt256()) {
9612 static const int ShufMask[] = {0, 2, 4, 6, -1, -1, -1, -1};
9613 In = DAG.getNode(ISD::BITCAST, DL, MVT::v8i32, In);
9614 In = DAG.getVectorShuffle(MVT::v8i32, DL, In, DAG.getUNDEF(MVT::v8i32),
9616 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, In,
9617 DAG.getIntPtrConstant(0));
9620 SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
9621 DAG.getIntPtrConstant(0));
9622 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
9623 DAG.getIntPtrConstant(2));
9624 OpLo = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpLo);
9625 OpHi = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpHi);
9626 static const int ShufMask[] = {0, 2, 4, 6};
9627 return DAG.getVectorShuffle(VT, DL, OpLo, OpHi, ShufMask);
9630 if ((VT == MVT::v8i16) && (InVT == MVT::v8i32)) {
9631 // On AVX2, v8i32 -> v8i16 becomed PSHUFB.
9632 if (Subtarget->hasInt256()) {
9633 In = DAG.getNode(ISD::BITCAST, DL, MVT::v32i8, In);
9635 SmallVector<SDValue,32> pshufbMask;
9636 for (unsigned i = 0; i < 2; ++i) {
9637 pshufbMask.push_back(DAG.getConstant(0x0, MVT::i8));
9638 pshufbMask.push_back(DAG.getConstant(0x1, MVT::i8));
9639 pshufbMask.push_back(DAG.getConstant(0x4, MVT::i8));
9640 pshufbMask.push_back(DAG.getConstant(0x5, MVT::i8));
9641 pshufbMask.push_back(DAG.getConstant(0x8, MVT::i8));
9642 pshufbMask.push_back(DAG.getConstant(0x9, MVT::i8));
9643 pshufbMask.push_back(DAG.getConstant(0xc, MVT::i8));
9644 pshufbMask.push_back(DAG.getConstant(0xd, MVT::i8));
9645 for (unsigned j = 0; j < 8; ++j)
9646 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
9648 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v32i8, pshufbMask);
9649 In = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v32i8, In, BV);
9650 In = DAG.getNode(ISD::BITCAST, DL, MVT::v4i64, In);
9652 static const int ShufMask[] = {0, 2, -1, -1};
9653 In = DAG.getVectorShuffle(MVT::v4i64, DL, In, DAG.getUNDEF(MVT::v4i64),
9655 In = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
9656 DAG.getIntPtrConstant(0));
9657 return DAG.getNode(ISD::BITCAST, DL, VT, In);
9660 SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v4i32, In,
9661 DAG.getIntPtrConstant(0));
9663 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v4i32, In,
9664 DAG.getIntPtrConstant(4));
9666 OpLo = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, OpLo);
9667 OpHi = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, OpHi);
9670 static const int ShufMask1[] = {0, 1, 4, 5, 8, 9, 12, 13,
9671 -1, -1, -1, -1, -1, -1, -1, -1};
9673 SDValue Undef = DAG.getUNDEF(MVT::v16i8);
9674 OpLo = DAG.getVectorShuffle(MVT::v16i8, DL, OpLo, Undef, ShufMask1);
9675 OpHi = DAG.getVectorShuffle(MVT::v16i8, DL, OpHi, Undef, ShufMask1);
9677 OpLo = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpLo);
9678 OpHi = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpHi);
9680 // The MOVLHPS Mask:
9681 static const int ShufMask2[] = {0, 1, 4, 5};
9682 SDValue res = DAG.getVectorShuffle(MVT::v4i32, DL, OpLo, OpHi, ShufMask2);
9683 return DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, res);
9686 // Handle truncation of V256 to V128 using shuffles.
9687 if (!VT.is128BitVector() || !InVT.is256BitVector())
9690 assert(Subtarget->hasFp256() && "256-bit vector without AVX!");
9692 unsigned NumElems = VT.getVectorNumElements();
9693 MVT NVT = MVT::getVectorVT(VT.getVectorElementType(), NumElems * 2);
9695 SmallVector<int, 16> MaskVec(NumElems * 2, -1);
9696 // Prepare truncation shuffle mask
9697 for (unsigned i = 0; i != NumElems; ++i)
9699 SDValue V = DAG.getVectorShuffle(NVT, DL,
9700 DAG.getNode(ISD::BITCAST, DL, NVT, In),
9701 DAG.getUNDEF(NVT), &MaskVec[0]);
9702 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, V,
9703 DAG.getIntPtrConstant(0));
9706 SDValue X86TargetLowering::LowerFP_TO_SINT(SDValue Op,
9707 SelectionDAG &DAG) const {
9708 assert(!Op.getSimpleValueType().isVector());
9710 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG,
9711 /*IsSigned=*/ true, /*IsReplace=*/ false);
9712 SDValue FIST = Vals.first, StackSlot = Vals.second;
9713 // If FP_TO_INTHelper failed, the node is actually supposed to be Legal.
9714 if (!FIST.getNode()) return Op;
9716 if (StackSlot.getNode())
9718 return DAG.getLoad(Op.getValueType(), SDLoc(Op),
9719 FIST, StackSlot, MachinePointerInfo(),
9720 false, false, false, 0);
9722 // The node is the result.
9726 SDValue X86TargetLowering::LowerFP_TO_UINT(SDValue Op,
9727 SelectionDAG &DAG) const {
9728 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG,
9729 /*IsSigned=*/ false, /*IsReplace=*/ false);
9730 SDValue FIST = Vals.first, StackSlot = Vals.second;
9731 assert(FIST.getNode() && "Unexpected failure");
9733 if (StackSlot.getNode())
9735 return DAG.getLoad(Op.getValueType(), SDLoc(Op),
9736 FIST, StackSlot, MachinePointerInfo(),
9737 false, false, false, 0);
9739 // The node is the result.
9743 static SDValue LowerFP_EXTEND(SDValue Op, SelectionDAG &DAG) {
9745 MVT VT = Op.getSimpleValueType();
9746 SDValue In = Op.getOperand(0);
9747 MVT SVT = In.getSimpleValueType();
9749 assert(SVT == MVT::v2f32 && "Only customize MVT::v2f32 type legalization!");
9751 return DAG.getNode(X86ISD::VFPEXT, DL, VT,
9752 DAG.getNode(ISD::CONCAT_VECTORS, DL, MVT::v4f32,
9753 In, DAG.getUNDEF(SVT)));
9756 static SDValue LowerFABS(SDValue Op, SelectionDAG &DAG) {
9757 LLVMContext *Context = DAG.getContext();
9759 MVT VT = Op.getSimpleValueType();
9761 unsigned NumElts = VT == MVT::f64 ? 2 : 4;
9762 if (VT.isVector()) {
9763 EltVT = VT.getVectorElementType();
9764 NumElts = VT.getVectorNumElements();
9767 if (EltVT == MVT::f64)
9768 C = ConstantFP::get(*Context, APFloat(APFloat::IEEEdouble,
9769 APInt(64, ~(1ULL << 63))));
9771 C = ConstantFP::get(*Context, APFloat(APFloat::IEEEsingle,
9772 APInt(32, ~(1U << 31))));
9773 C = ConstantVector::getSplat(NumElts, C);
9774 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
9775 SDValue CPIdx = DAG.getConstantPool(C, TLI.getPointerTy());
9776 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
9777 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
9778 MachinePointerInfo::getConstantPool(),
9779 false, false, false, Alignment);
9780 if (VT.isVector()) {
9781 MVT ANDVT = VT.is128BitVector() ? MVT::v2i64 : MVT::v4i64;
9782 return DAG.getNode(ISD::BITCAST, dl, VT,
9783 DAG.getNode(ISD::AND, dl, ANDVT,
9784 DAG.getNode(ISD::BITCAST, dl, ANDVT,
9786 DAG.getNode(ISD::BITCAST, dl, ANDVT, Mask)));
9788 return DAG.getNode(X86ISD::FAND, dl, VT, Op.getOperand(0), Mask);
9791 static SDValue LowerFNEG(SDValue Op, SelectionDAG &DAG) {
9792 LLVMContext *Context = DAG.getContext();
9794 MVT VT = Op.getSimpleValueType();
9796 unsigned NumElts = VT == MVT::f64 ? 2 : 4;
9797 if (VT.isVector()) {
9798 EltVT = VT.getVectorElementType();
9799 NumElts = VT.getVectorNumElements();
9802 if (EltVT == MVT::f64)
9803 C = ConstantFP::get(*Context, APFloat(APFloat::IEEEdouble,
9804 APInt(64, 1ULL << 63)));
9806 C = ConstantFP::get(*Context, APFloat(APFloat::IEEEsingle,
9807 APInt(32, 1U << 31)));
9808 C = ConstantVector::getSplat(NumElts, C);
9809 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
9810 SDValue CPIdx = DAG.getConstantPool(C, TLI.getPointerTy());
9811 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
9812 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
9813 MachinePointerInfo::getConstantPool(),
9814 false, false, false, Alignment);
9815 if (VT.isVector()) {
9816 MVT XORVT = MVT::getVectorVT(MVT::i64, VT.getSizeInBits()/64);
9817 return DAG.getNode(ISD::BITCAST, dl, VT,
9818 DAG.getNode(ISD::XOR, dl, XORVT,
9819 DAG.getNode(ISD::BITCAST, dl, XORVT,
9821 DAG.getNode(ISD::BITCAST, dl, XORVT, Mask)));
9824 return DAG.getNode(X86ISD::FXOR, dl, VT, Op.getOperand(0), Mask);
9827 static SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) {
9828 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
9829 LLVMContext *Context = DAG.getContext();
9830 SDValue Op0 = Op.getOperand(0);
9831 SDValue Op1 = Op.getOperand(1);
9833 MVT VT = Op.getSimpleValueType();
9834 MVT SrcVT = Op1.getSimpleValueType();
9836 // If second operand is smaller, extend it first.
9837 if (SrcVT.bitsLT(VT)) {
9838 Op1 = DAG.getNode(ISD::FP_EXTEND, dl, VT, Op1);
9841 // And if it is bigger, shrink it first.
9842 if (SrcVT.bitsGT(VT)) {
9843 Op1 = DAG.getNode(ISD::FP_ROUND, dl, VT, Op1, DAG.getIntPtrConstant(1));
9847 // At this point the operands and the result should have the same
9848 // type, and that won't be f80 since that is not custom lowered.
9850 // First get the sign bit of second operand.
9851 SmallVector<Constant*,4> CV;
9852 if (SrcVT == MVT::f64) {
9853 const fltSemantics &Sem = APFloat::IEEEdouble;
9854 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(64, 1ULL << 63))));
9855 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(64, 0))));
9857 const fltSemantics &Sem = APFloat::IEEEsingle;
9858 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 1U << 31))));
9859 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
9860 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
9861 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
9863 Constant *C = ConstantVector::get(CV);
9864 SDValue CPIdx = DAG.getConstantPool(C, TLI.getPointerTy(), 16);
9865 SDValue Mask1 = DAG.getLoad(SrcVT, dl, DAG.getEntryNode(), CPIdx,
9866 MachinePointerInfo::getConstantPool(),
9867 false, false, false, 16);
9868 SDValue SignBit = DAG.getNode(X86ISD::FAND, dl, SrcVT, Op1, Mask1);
9870 // Shift sign bit right or left if the two operands have different types.
9871 if (SrcVT.bitsGT(VT)) {
9872 // Op0 is MVT::f32, Op1 is MVT::f64.
9873 SignBit = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f64, SignBit);
9874 SignBit = DAG.getNode(X86ISD::FSRL, dl, MVT::v2f64, SignBit,
9875 DAG.getConstant(32, MVT::i32));
9876 SignBit = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, SignBit);
9877 SignBit = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f32, SignBit,
9878 DAG.getIntPtrConstant(0));
9881 // Clear first operand sign bit.
9883 if (VT == MVT::f64) {
9884 const fltSemantics &Sem = APFloat::IEEEdouble;
9885 CV.push_back(ConstantFP::get(*Context, APFloat(Sem,
9886 APInt(64, ~(1ULL << 63)))));
9887 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(64, 0))));
9889 const fltSemantics &Sem = APFloat::IEEEsingle;
9890 CV.push_back(ConstantFP::get(*Context, APFloat(Sem,
9891 APInt(32, ~(1U << 31)))));
9892 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
9893 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
9894 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
9896 C = ConstantVector::get(CV);
9897 CPIdx = DAG.getConstantPool(C, TLI.getPointerTy(), 16);
9898 SDValue Mask2 = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
9899 MachinePointerInfo::getConstantPool(),
9900 false, false, false, 16);
9901 SDValue Val = DAG.getNode(X86ISD::FAND, dl, VT, Op0, Mask2);
9903 // Or the value with the sign bit.
9904 return DAG.getNode(X86ISD::FOR, dl, VT, Val, SignBit);
9907 static SDValue LowerFGETSIGN(SDValue Op, SelectionDAG &DAG) {
9908 SDValue N0 = Op.getOperand(0);
9910 MVT VT = Op.getSimpleValueType();
9912 // Lower ISD::FGETSIGN to (AND (X86ISD::FGETSIGNx86 ...) 1).
9913 SDValue xFGETSIGN = DAG.getNode(X86ISD::FGETSIGNx86, dl, VT, N0,
9914 DAG.getConstant(1, VT));
9915 return DAG.getNode(ISD::AND, dl, VT, xFGETSIGN, DAG.getConstant(1, VT));
9918 // LowerVectorAllZeroTest - Check whether an OR'd tree is PTEST-able.
9920 static SDValue LowerVectorAllZeroTest(SDValue Op, const X86Subtarget *Subtarget,
9921 SelectionDAG &DAG) {
9922 assert(Op.getOpcode() == ISD::OR && "Only check OR'd tree.");
9924 if (!Subtarget->hasSSE41())
9927 if (!Op->hasOneUse())
9930 SDNode *N = Op.getNode();
9933 SmallVector<SDValue, 8> Opnds;
9934 DenseMap<SDValue, unsigned> VecInMap;
9935 SmallVector<SDValue, 8> VecIns;
9936 EVT VT = MVT::Other;
9938 // Recognize a special case where a vector is casted into wide integer to
9940 Opnds.push_back(N->getOperand(0));
9941 Opnds.push_back(N->getOperand(1));
9943 for (unsigned Slot = 0, e = Opnds.size(); Slot < e; ++Slot) {
9944 SmallVectorImpl<SDValue>::const_iterator I = Opnds.begin() + Slot;
9945 // BFS traverse all OR'd operands.
9946 if (I->getOpcode() == ISD::OR) {
9947 Opnds.push_back(I->getOperand(0));
9948 Opnds.push_back(I->getOperand(1));
9949 // Re-evaluate the number of nodes to be traversed.
9950 e += 2; // 2 more nodes (LHS and RHS) are pushed.
9954 // Quit if a non-EXTRACT_VECTOR_ELT
9955 if (I->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
9958 // Quit if without a constant index.
9959 SDValue Idx = I->getOperand(1);
9960 if (!isa<ConstantSDNode>(Idx))
9963 SDValue ExtractedFromVec = I->getOperand(0);
9964 DenseMap<SDValue, unsigned>::iterator M = VecInMap.find(ExtractedFromVec);
9965 if (M == VecInMap.end()) {
9966 VT = ExtractedFromVec.getValueType();
9967 // Quit if not 128/256-bit vector.
9968 if (!VT.is128BitVector() && !VT.is256BitVector())
9970 // Quit if not the same type.
9971 if (VecInMap.begin() != VecInMap.end() &&
9972 VT != VecInMap.begin()->first.getValueType())
9974 M = VecInMap.insert(std::make_pair(ExtractedFromVec, 0)).first;
9975 VecIns.push_back(ExtractedFromVec);
9977 M->second |= 1U << cast<ConstantSDNode>(Idx)->getZExtValue();
9980 assert((VT.is128BitVector() || VT.is256BitVector()) &&
9981 "Not extracted from 128-/256-bit vector.");
9983 unsigned FullMask = (1U << VT.getVectorNumElements()) - 1U;
9985 for (DenseMap<SDValue, unsigned>::const_iterator
9986 I = VecInMap.begin(), E = VecInMap.end(); I != E; ++I) {
9987 // Quit if not all elements are used.
9988 if (I->second != FullMask)
9992 EVT TestVT = VT.is128BitVector() ? MVT::v2i64 : MVT::v4i64;
9994 // Cast all vectors into TestVT for PTEST.
9995 for (unsigned i = 0, e = VecIns.size(); i < e; ++i)
9996 VecIns[i] = DAG.getNode(ISD::BITCAST, DL, TestVT, VecIns[i]);
9998 // If more than one full vectors are evaluated, OR them first before PTEST.
9999 for (unsigned Slot = 0, e = VecIns.size(); e - Slot > 1; Slot += 2, e += 1) {
10000 // Each iteration will OR 2 nodes and append the result until there is only
10001 // 1 node left, i.e. the final OR'd value of all vectors.
10002 SDValue LHS = VecIns[Slot];
10003 SDValue RHS = VecIns[Slot + 1];
10004 VecIns.push_back(DAG.getNode(ISD::OR, DL, TestVT, LHS, RHS));
10007 return DAG.getNode(X86ISD::PTEST, DL, MVT::i32,
10008 VecIns.back(), VecIns.back());
10011 /// \brief return true if \c Op has a use that doesn't just read flags.
10012 static bool hasNonFlagsUse(SDValue Op) {
10013 for (SDNode::use_iterator UI = Op->use_begin(), UE = Op->use_end(); UI != UE;
10015 SDNode *User = *UI;
10016 unsigned UOpNo = UI.getOperandNo();
10017 if (User->getOpcode() == ISD::TRUNCATE && User->hasOneUse()) {
10018 // Look pass truncate.
10019 UOpNo = User->use_begin().getOperandNo();
10020 User = *User->use_begin();
10023 if (User->getOpcode() != ISD::BRCOND && User->getOpcode() != ISD::SETCC &&
10024 !(User->getOpcode() == ISD::SELECT && UOpNo == 0))
10030 /// Emit nodes that will be selected as "test Op0,Op0", or something
10032 SDValue X86TargetLowering::EmitTest(SDValue Op, unsigned X86CC, SDLoc dl,
10033 SelectionDAG &DAG) const {
10034 if (Op.getValueType() == MVT::i1)
10035 // KORTEST instruction should be selected
10036 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
10037 DAG.getConstant(0, Op.getValueType()));
10039 // CF and OF aren't always set the way we want. Determine which
10040 // of these we need.
10041 bool NeedCF = false;
10042 bool NeedOF = false;
10045 case X86::COND_A: case X86::COND_AE:
10046 case X86::COND_B: case X86::COND_BE:
10049 case X86::COND_G: case X86::COND_GE:
10050 case X86::COND_L: case X86::COND_LE:
10051 case X86::COND_O: case X86::COND_NO:
10055 // See if we can use the EFLAGS value from the operand instead of
10056 // doing a separate TEST. TEST always sets OF and CF to 0, so unless
10057 // we prove that the arithmetic won't overflow, we can't use OF or CF.
10058 if (Op.getResNo() != 0 || NeedOF || NeedCF) {
10059 // Emit a CMP with 0, which is the TEST pattern.
10060 //if (Op.getValueType() == MVT::i1)
10061 // return DAG.getNode(X86ISD::CMP, dl, MVT::i1, Op,
10062 // DAG.getConstant(0, MVT::i1));
10063 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
10064 DAG.getConstant(0, Op.getValueType()));
10066 unsigned Opcode = 0;
10067 unsigned NumOperands = 0;
10069 // Truncate operations may prevent the merge of the SETCC instruction
10070 // and the arithmetic instruction before it. Attempt to truncate the operands
10071 // of the arithmetic instruction and use a reduced bit-width instruction.
10072 bool NeedTruncation = false;
10073 SDValue ArithOp = Op;
10074 if (Op->getOpcode() == ISD::TRUNCATE && Op->hasOneUse()) {
10075 SDValue Arith = Op->getOperand(0);
10076 // Both the trunc and the arithmetic op need to have one user each.
10077 if (Arith->hasOneUse())
10078 switch (Arith.getOpcode()) {
10085 NeedTruncation = true;
10091 // NOTICE: In the code below we use ArithOp to hold the arithmetic operation
10092 // which may be the result of a CAST. We use the variable 'Op', which is the
10093 // non-casted variable when we check for possible users.
10094 switch (ArithOp.getOpcode()) {
10096 // Due to an isel shortcoming, be conservative if this add is likely to be
10097 // selected as part of a load-modify-store instruction. When the root node
10098 // in a match is a store, isel doesn't know how to remap non-chain non-flag
10099 // uses of other nodes in the match, such as the ADD in this case. This
10100 // leads to the ADD being left around and reselected, with the result being
10101 // two adds in the output. Alas, even if none our users are stores, that
10102 // doesn't prove we're O.K. Ergo, if we have any parents that aren't
10103 // CopyToReg or SETCC, eschew INC/DEC. A better fix seems to require
10104 // climbing the DAG back to the root, and it doesn't seem to be worth the
10106 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
10107 UE = Op.getNode()->use_end(); UI != UE; ++UI)
10108 if (UI->getOpcode() != ISD::CopyToReg &&
10109 UI->getOpcode() != ISD::SETCC &&
10110 UI->getOpcode() != ISD::STORE)
10113 if (ConstantSDNode *C =
10114 dyn_cast<ConstantSDNode>(ArithOp.getNode()->getOperand(1))) {
10115 // An add of one will be selected as an INC.
10116 if (C->getAPIntValue() == 1) {
10117 Opcode = X86ISD::INC;
10122 // An add of negative one (subtract of one) will be selected as a DEC.
10123 if (C->getAPIntValue().isAllOnesValue()) {
10124 Opcode = X86ISD::DEC;
10130 // Otherwise use a regular EFLAGS-setting add.
10131 Opcode = X86ISD::ADD;
10136 // If we have a constant logical shift that's only used in a comparison
10137 // against zero turn it into an equivalent AND. This allows turning it into
10138 // a TEST instruction later.
10139 if ((X86CC == X86::COND_E || X86CC == X86::COND_NE) &&
10140 isa<ConstantSDNode>(Op->getOperand(1)) && !hasNonFlagsUse(Op)) {
10141 EVT VT = Op.getValueType();
10142 unsigned BitWidth = VT.getSizeInBits();
10143 unsigned ShAmt = Op->getConstantOperandVal(1);
10144 if (ShAmt >= BitWidth) // Avoid undefined shifts.
10146 APInt Mask = ArithOp.getOpcode() == ISD::SRL
10147 ? APInt::getHighBitsSet(BitWidth, BitWidth - ShAmt)
10148 : APInt::getLowBitsSet(BitWidth, BitWidth - ShAmt);
10149 if (!Mask.isSignedIntN(32)) // Avoid large immediates.
10151 SDValue New = DAG.getNode(ISD::AND, dl, VT, Op->getOperand(0),
10152 DAG.getConstant(Mask, VT));
10153 DAG.ReplaceAllUsesWith(Op, New);
10159 // If the primary and result isn't used, don't bother using X86ISD::AND,
10160 // because a TEST instruction will be better.
10161 if (!hasNonFlagsUse(Op))
10167 // Due to the ISEL shortcoming noted above, be conservative if this op is
10168 // likely to be selected as part of a load-modify-store instruction.
10169 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
10170 UE = Op.getNode()->use_end(); UI != UE; ++UI)
10171 if (UI->getOpcode() == ISD::STORE)
10174 // Otherwise use a regular EFLAGS-setting instruction.
10175 switch (ArithOp.getOpcode()) {
10176 default: llvm_unreachable("unexpected operator!");
10177 case ISD::SUB: Opcode = X86ISD::SUB; break;
10178 case ISD::XOR: Opcode = X86ISD::XOR; break;
10179 case ISD::AND: Opcode = X86ISD::AND; break;
10181 if (!NeedTruncation && (X86CC == X86::COND_E || X86CC == X86::COND_NE)) {
10182 SDValue EFLAGS = LowerVectorAllZeroTest(Op, Subtarget, DAG);
10183 if (EFLAGS.getNode())
10186 Opcode = X86ISD::OR;
10200 return SDValue(Op.getNode(), 1);
10206 // If we found that truncation is beneficial, perform the truncation and
10208 if (NeedTruncation) {
10209 EVT VT = Op.getValueType();
10210 SDValue WideVal = Op->getOperand(0);
10211 EVT WideVT = WideVal.getValueType();
10212 unsigned ConvertedOp = 0;
10213 // Use a target machine opcode to prevent further DAGCombine
10214 // optimizations that may separate the arithmetic operations
10215 // from the setcc node.
10216 switch (WideVal.getOpcode()) {
10218 case ISD::ADD: ConvertedOp = X86ISD::ADD; break;
10219 case ISD::SUB: ConvertedOp = X86ISD::SUB; break;
10220 case ISD::AND: ConvertedOp = X86ISD::AND; break;
10221 case ISD::OR: ConvertedOp = X86ISD::OR; break;
10222 case ISD::XOR: ConvertedOp = X86ISD::XOR; break;
10226 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
10227 if (TLI.isOperationLegal(WideVal.getOpcode(), WideVT)) {
10228 SDValue V0 = DAG.getNode(ISD::TRUNCATE, dl, VT, WideVal.getOperand(0));
10229 SDValue V1 = DAG.getNode(ISD::TRUNCATE, dl, VT, WideVal.getOperand(1));
10230 Op = DAG.getNode(ConvertedOp, dl, VT, V0, V1);
10236 // Emit a CMP with 0, which is the TEST pattern.
10237 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
10238 DAG.getConstant(0, Op.getValueType()));
10240 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
10241 SmallVector<SDValue, 4> Ops;
10242 for (unsigned i = 0; i != NumOperands; ++i)
10243 Ops.push_back(Op.getOperand(i));
10245 SDValue New = DAG.getNode(Opcode, dl, VTs, Ops);
10246 DAG.ReplaceAllUsesWith(Op, New);
10247 return SDValue(New.getNode(), 1);
10250 /// Emit nodes that will be selected as "cmp Op0,Op1", or something
10252 SDValue X86TargetLowering::EmitCmp(SDValue Op0, SDValue Op1, unsigned X86CC,
10253 SDLoc dl, SelectionDAG &DAG) const {
10254 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op1)) {
10255 if (C->getAPIntValue() == 0)
10256 return EmitTest(Op0, X86CC, dl, DAG);
10258 if (Op0.getValueType() == MVT::i1)
10259 llvm_unreachable("Unexpected comparison operation for MVT::i1 operands");
10262 if ((Op0.getValueType() == MVT::i8 || Op0.getValueType() == MVT::i16 ||
10263 Op0.getValueType() == MVT::i32 || Op0.getValueType() == MVT::i64)) {
10264 // Do the comparison at i32 if it's smaller, besides the Atom case.
10265 // This avoids subregister aliasing issues. Keep the smaller reference
10266 // if we're optimizing for size, however, as that'll allow better folding
10267 // of memory operations.
10268 if (Op0.getValueType() != MVT::i32 && Op0.getValueType() != MVT::i64 &&
10269 !DAG.getMachineFunction().getFunction()->getAttributes().hasAttribute(
10270 AttributeSet::FunctionIndex, Attribute::MinSize) &&
10271 !Subtarget->isAtom()) {
10272 unsigned ExtendOp =
10273 isX86CCUnsigned(X86CC) ? ISD::ZERO_EXTEND : ISD::SIGN_EXTEND;
10274 Op0 = DAG.getNode(ExtendOp, dl, MVT::i32, Op0);
10275 Op1 = DAG.getNode(ExtendOp, dl, MVT::i32, Op1);
10277 // Use SUB instead of CMP to enable CSE between SUB and CMP.
10278 SDVTList VTs = DAG.getVTList(Op0.getValueType(), MVT::i32);
10279 SDValue Sub = DAG.getNode(X86ISD::SUB, dl, VTs,
10281 return SDValue(Sub.getNode(), 1);
10283 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op0, Op1);
10286 /// Convert a comparison if required by the subtarget.
10287 SDValue X86TargetLowering::ConvertCmpIfNecessary(SDValue Cmp,
10288 SelectionDAG &DAG) const {
10289 // If the subtarget does not support the FUCOMI instruction, floating-point
10290 // comparisons have to be converted.
10291 if (Subtarget->hasCMov() ||
10292 Cmp.getOpcode() != X86ISD::CMP ||
10293 !Cmp.getOperand(0).getValueType().isFloatingPoint() ||
10294 !Cmp.getOperand(1).getValueType().isFloatingPoint())
10297 // The instruction selector will select an FUCOM instruction instead of
10298 // FUCOMI, which writes the comparison result to FPSW instead of EFLAGS. Hence
10299 // build an SDNode sequence that transfers the result from FPSW into EFLAGS:
10300 // (X86sahf (trunc (srl (X86fp_stsw (trunc (X86cmp ...)), 8))))
10302 SDValue TruncFPSW = DAG.getNode(ISD::TRUNCATE, dl, MVT::i16, Cmp);
10303 SDValue FNStSW = DAG.getNode(X86ISD::FNSTSW16r, dl, MVT::i16, TruncFPSW);
10304 SDValue Srl = DAG.getNode(ISD::SRL, dl, MVT::i16, FNStSW,
10305 DAG.getConstant(8, MVT::i8));
10306 SDValue TruncSrl = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Srl);
10307 return DAG.getNode(X86ISD::SAHF, dl, MVT::i32, TruncSrl);
10310 static bool isAllOnes(SDValue V) {
10311 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V);
10312 return C && C->isAllOnesValue();
10315 /// LowerToBT - Result of 'and' is compared against zero. Turn it into a BT node
10316 /// if it's possible.
10317 SDValue X86TargetLowering::LowerToBT(SDValue And, ISD::CondCode CC,
10318 SDLoc dl, SelectionDAG &DAG) const {
10319 SDValue Op0 = And.getOperand(0);
10320 SDValue Op1 = And.getOperand(1);
10321 if (Op0.getOpcode() == ISD::TRUNCATE)
10322 Op0 = Op0.getOperand(0);
10323 if (Op1.getOpcode() == ISD::TRUNCATE)
10324 Op1 = Op1.getOperand(0);
10327 if (Op1.getOpcode() == ISD::SHL)
10328 std::swap(Op0, Op1);
10329 if (Op0.getOpcode() == ISD::SHL) {
10330 if (ConstantSDNode *And00C = dyn_cast<ConstantSDNode>(Op0.getOperand(0)))
10331 if (And00C->getZExtValue() == 1) {
10332 // If we looked past a truncate, check that it's only truncating away
10334 unsigned BitWidth = Op0.getValueSizeInBits();
10335 unsigned AndBitWidth = And.getValueSizeInBits();
10336 if (BitWidth > AndBitWidth) {
10338 DAG.computeKnownBits(Op0, Zeros, Ones);
10339 if (Zeros.countLeadingOnes() < BitWidth - AndBitWidth)
10343 RHS = Op0.getOperand(1);
10345 } else if (Op1.getOpcode() == ISD::Constant) {
10346 ConstantSDNode *AndRHS = cast<ConstantSDNode>(Op1);
10347 uint64_t AndRHSVal = AndRHS->getZExtValue();
10348 SDValue AndLHS = Op0;
10350 if (AndRHSVal == 1 && AndLHS.getOpcode() == ISD::SRL) {
10351 LHS = AndLHS.getOperand(0);
10352 RHS = AndLHS.getOperand(1);
10355 // Use BT if the immediate can't be encoded in a TEST instruction.
10356 if (!isUInt<32>(AndRHSVal) && isPowerOf2_64(AndRHSVal)) {
10358 RHS = DAG.getConstant(Log2_64_Ceil(AndRHSVal), LHS.getValueType());
10362 if (LHS.getNode()) {
10363 // If LHS is i8, promote it to i32 with any_extend. There is no i8 BT
10364 // instruction. Since the shift amount is in-range-or-undefined, we know
10365 // that doing a bittest on the i32 value is ok. We extend to i32 because
10366 // the encoding for the i16 version is larger than the i32 version.
10367 // Also promote i16 to i32 for performance / code size reason.
10368 if (LHS.getValueType() == MVT::i8 ||
10369 LHS.getValueType() == MVT::i16)
10370 LHS = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, LHS);
10372 // If the operand types disagree, extend the shift amount to match. Since
10373 // BT ignores high bits (like shifts) we can use anyextend.
10374 if (LHS.getValueType() != RHS.getValueType())
10375 RHS = DAG.getNode(ISD::ANY_EXTEND, dl, LHS.getValueType(), RHS);
10377 SDValue BT = DAG.getNode(X86ISD::BT, dl, MVT::i32, LHS, RHS);
10378 X86::CondCode Cond = CC == ISD::SETEQ ? X86::COND_AE : X86::COND_B;
10379 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
10380 DAG.getConstant(Cond, MVT::i8), BT);
10386 /// \brief - Turns an ISD::CondCode into a value suitable for SSE floating point
10388 static int translateX86FSETCC(ISD::CondCode SetCCOpcode, SDValue &Op0,
10393 // SSE Condition code mapping:
10402 switch (SetCCOpcode) {
10403 default: llvm_unreachable("Unexpected SETCC condition");
10405 case ISD::SETEQ: SSECC = 0; break;
10407 case ISD::SETGT: Swap = true; // Fallthrough
10409 case ISD::SETOLT: SSECC = 1; break;
10411 case ISD::SETGE: Swap = true; // Fallthrough
10413 case ISD::SETOLE: SSECC = 2; break;
10414 case ISD::SETUO: SSECC = 3; break;
10416 case ISD::SETNE: SSECC = 4; break;
10417 case ISD::SETULE: Swap = true; // Fallthrough
10418 case ISD::SETUGE: SSECC = 5; break;
10419 case ISD::SETULT: Swap = true; // Fallthrough
10420 case ISD::SETUGT: SSECC = 6; break;
10421 case ISD::SETO: SSECC = 7; break;
10423 case ISD::SETONE: SSECC = 8; break;
10426 std::swap(Op0, Op1);
10431 // Lower256IntVSETCC - Break a VSETCC 256-bit integer VSETCC into two new 128
10432 // ones, and then concatenate the result back.
10433 static SDValue Lower256IntVSETCC(SDValue Op, SelectionDAG &DAG) {
10434 MVT VT = Op.getSimpleValueType();
10436 assert(VT.is256BitVector() && Op.getOpcode() == ISD::SETCC &&
10437 "Unsupported value type for operation");
10439 unsigned NumElems = VT.getVectorNumElements();
10441 SDValue CC = Op.getOperand(2);
10443 // Extract the LHS vectors
10444 SDValue LHS = Op.getOperand(0);
10445 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
10446 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
10448 // Extract the RHS vectors
10449 SDValue RHS = Op.getOperand(1);
10450 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, dl);
10451 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, dl);
10453 // Issue the operation on the smaller types and concatenate the result back
10454 MVT EltVT = VT.getVectorElementType();
10455 MVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
10456 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
10457 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1, CC),
10458 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2, CC));
10461 static SDValue LowerIntVSETCC_AVX512(SDValue Op, SelectionDAG &DAG,
10462 const X86Subtarget *Subtarget) {
10463 SDValue Op0 = Op.getOperand(0);
10464 SDValue Op1 = Op.getOperand(1);
10465 SDValue CC = Op.getOperand(2);
10466 MVT VT = Op.getSimpleValueType();
10469 assert(Op0.getValueType().getVectorElementType().getSizeInBits() >= 32 &&
10470 Op.getValueType().getScalarType() == MVT::i1 &&
10471 "Cannot set masked compare for this operation");
10473 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
10475 bool Unsigned = false;
10478 switch (SetCCOpcode) {
10479 default: llvm_unreachable("Unexpected SETCC condition");
10480 case ISD::SETNE: SSECC = 4; break;
10481 case ISD::SETEQ: Opc = X86ISD::PCMPEQM; break;
10482 case ISD::SETUGT: SSECC = 6; Unsigned = true; break;
10483 case ISD::SETLT: Swap = true; //fall-through
10484 case ISD::SETGT: Opc = X86ISD::PCMPGTM; break;
10485 case ISD::SETULT: SSECC = 1; Unsigned = true; break;
10486 case ISD::SETUGE: SSECC = 5; Unsigned = true; break; //NLT
10487 case ISD::SETGE: Swap = true; SSECC = 2; break; // LE + swap
10488 case ISD::SETULE: Unsigned = true; //fall-through
10489 case ISD::SETLE: SSECC = 2; break;
10493 std::swap(Op0, Op1);
10495 return DAG.getNode(Opc, dl, VT, Op0, Op1);
10496 Opc = Unsigned ? X86ISD::CMPMU: X86ISD::CMPM;
10497 return DAG.getNode(Opc, dl, VT, Op0, Op1,
10498 DAG.getConstant(SSECC, MVT::i8));
10501 /// \brief Try to turn a VSETULT into a VSETULE by modifying its second
10502 /// operand \p Op1. If non-trivial (for example because it's not constant)
10503 /// return an empty value.
10504 static SDValue ChangeVSETULTtoVSETULE(SDLoc dl, SDValue Op1, SelectionDAG &DAG)
10506 BuildVectorSDNode *BV = dyn_cast<BuildVectorSDNode>(Op1.getNode());
10510 MVT VT = Op1.getSimpleValueType();
10511 MVT EVT = VT.getVectorElementType();
10512 unsigned n = VT.getVectorNumElements();
10513 SmallVector<SDValue, 8> ULTOp1;
10515 for (unsigned i = 0; i < n; ++i) {
10516 ConstantSDNode *Elt = dyn_cast<ConstantSDNode>(BV->getOperand(i));
10517 if (!Elt || Elt->isOpaque() || Elt->getValueType(0) != EVT)
10520 // Avoid underflow.
10521 APInt Val = Elt->getAPIntValue();
10525 ULTOp1.push_back(DAG.getConstant(Val - 1, EVT));
10528 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, ULTOp1);
10531 static SDValue LowerVSETCC(SDValue Op, const X86Subtarget *Subtarget,
10532 SelectionDAG &DAG) {
10533 SDValue Op0 = Op.getOperand(0);
10534 SDValue Op1 = Op.getOperand(1);
10535 SDValue CC = Op.getOperand(2);
10536 MVT VT = Op.getSimpleValueType();
10537 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
10538 bool isFP = Op.getOperand(1).getSimpleValueType().isFloatingPoint();
10543 MVT EltVT = Op0.getSimpleValueType().getVectorElementType();
10544 assert(EltVT == MVT::f32 || EltVT == MVT::f64);
10547 unsigned SSECC = translateX86FSETCC(SetCCOpcode, Op0, Op1);
10548 unsigned Opc = X86ISD::CMPP;
10549 if (Subtarget->hasAVX512() && VT.getVectorElementType() == MVT::i1) {
10550 assert(VT.getVectorNumElements() <= 16);
10551 Opc = X86ISD::CMPM;
10553 // In the two special cases we can't handle, emit two comparisons.
10556 unsigned CombineOpc;
10557 if (SetCCOpcode == ISD::SETUEQ) {
10558 CC0 = 3; CC1 = 0; CombineOpc = ISD::OR;
10560 assert(SetCCOpcode == ISD::SETONE);
10561 CC0 = 7; CC1 = 4; CombineOpc = ISD::AND;
10564 SDValue Cmp0 = DAG.getNode(Opc, dl, VT, Op0, Op1,
10565 DAG.getConstant(CC0, MVT::i8));
10566 SDValue Cmp1 = DAG.getNode(Opc, dl, VT, Op0, Op1,
10567 DAG.getConstant(CC1, MVT::i8));
10568 return DAG.getNode(CombineOpc, dl, VT, Cmp0, Cmp1);
10570 // Handle all other FP comparisons here.
10571 return DAG.getNode(Opc, dl, VT, Op0, Op1,
10572 DAG.getConstant(SSECC, MVT::i8));
10575 // Break 256-bit integer vector compare into smaller ones.
10576 if (VT.is256BitVector() && !Subtarget->hasInt256())
10577 return Lower256IntVSETCC(Op, DAG);
10579 bool MaskResult = (VT.getVectorElementType() == MVT::i1);
10580 EVT OpVT = Op1.getValueType();
10581 if (Subtarget->hasAVX512()) {
10582 if (Op1.getValueType().is512BitVector() ||
10583 (MaskResult && OpVT.getVectorElementType().getSizeInBits() >= 32))
10584 return LowerIntVSETCC_AVX512(Op, DAG, Subtarget);
10586 // In AVX-512 architecture setcc returns mask with i1 elements,
10587 // But there is no compare instruction for i8 and i16 elements.
10588 // We are not talking about 512-bit operands in this case, these
10589 // types are illegal.
10591 (OpVT.getVectorElementType().getSizeInBits() < 32 &&
10592 OpVT.getVectorElementType().getSizeInBits() >= 8))
10593 return DAG.getNode(ISD::TRUNCATE, dl, VT,
10594 DAG.getNode(ISD::SETCC, dl, OpVT, Op0, Op1, CC));
10597 // We are handling one of the integer comparisons here. Since SSE only has
10598 // GT and EQ comparisons for integer, swapping operands and multiple
10599 // operations may be required for some comparisons.
10601 bool Swap = false, Invert = false, FlipSigns = false, MinMax = false;
10602 bool Subus = false;
10604 switch (SetCCOpcode) {
10605 default: llvm_unreachable("Unexpected SETCC condition");
10606 case ISD::SETNE: Invert = true;
10607 case ISD::SETEQ: Opc = X86ISD::PCMPEQ; break;
10608 case ISD::SETLT: Swap = true;
10609 case ISD::SETGT: Opc = X86ISD::PCMPGT; break;
10610 case ISD::SETGE: Swap = true;
10611 case ISD::SETLE: Opc = X86ISD::PCMPGT;
10612 Invert = true; break;
10613 case ISD::SETULT: Swap = true;
10614 case ISD::SETUGT: Opc = X86ISD::PCMPGT;
10615 FlipSigns = true; break;
10616 case ISD::SETUGE: Swap = true;
10617 case ISD::SETULE: Opc = X86ISD::PCMPGT;
10618 FlipSigns = true; Invert = true; break;
10621 // Special case: Use min/max operations for SETULE/SETUGE
10622 MVT VET = VT.getVectorElementType();
10624 (Subtarget->hasSSE41() && (VET >= MVT::i8 && VET <= MVT::i32))
10625 || (Subtarget->hasSSE2() && (VET == MVT::i8));
10628 switch (SetCCOpcode) {
10630 case ISD::SETULE: Opc = X86ISD::UMIN; MinMax = true; break;
10631 case ISD::SETUGE: Opc = X86ISD::UMAX; MinMax = true; break;
10634 if (MinMax) { Swap = false; Invert = false; FlipSigns = false; }
10637 bool hasSubus = Subtarget->hasSSE2() && (VET == MVT::i8 || VET == MVT::i16);
10638 if (!MinMax && hasSubus) {
10639 // As another special case, use PSUBUS[BW] when it's profitable. E.g. for
10641 // t = psubus Op0, Op1
10642 // pcmpeq t, <0..0>
10643 switch (SetCCOpcode) {
10645 case ISD::SETULT: {
10646 // If the comparison is against a constant we can turn this into a
10647 // setule. With psubus, setule does not require a swap. This is
10648 // beneficial because the constant in the register is no longer
10649 // destructed as the destination so it can be hoisted out of a loop.
10650 // Only do this pre-AVX since vpcmp* is no longer destructive.
10651 if (Subtarget->hasAVX())
10653 SDValue ULEOp1 = ChangeVSETULTtoVSETULE(dl, Op1, DAG);
10654 if (ULEOp1.getNode()) {
10656 Subus = true; Invert = false; Swap = false;
10660 // Psubus is better than flip-sign because it requires no inversion.
10661 case ISD::SETUGE: Subus = true; Invert = false; Swap = true; break;
10662 case ISD::SETULE: Subus = true; Invert = false; Swap = false; break;
10666 Opc = X86ISD::SUBUS;
10672 std::swap(Op0, Op1);
10674 // Check that the operation in question is available (most are plain SSE2,
10675 // but PCMPGTQ and PCMPEQQ have different requirements).
10676 if (VT == MVT::v2i64) {
10677 if (Opc == X86ISD::PCMPGT && !Subtarget->hasSSE42()) {
10678 assert(Subtarget->hasSSE2() && "Don't know how to lower!");
10680 // First cast everything to the right type.
10681 Op0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op0);
10682 Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op1);
10684 // Since SSE has no unsigned integer comparisons, we need to flip the sign
10685 // bits of the inputs before performing those operations. The lower
10686 // compare is always unsigned.
10689 SB = DAG.getConstant(0x80000000U, MVT::v4i32);
10691 SDValue Sign = DAG.getConstant(0x80000000U, MVT::i32);
10692 SDValue Zero = DAG.getConstant(0x00000000U, MVT::i32);
10693 SB = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32,
10694 Sign, Zero, Sign, Zero);
10696 Op0 = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Op0, SB);
10697 Op1 = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Op1, SB);
10699 // Emulate PCMPGTQ with (hi1 > hi2) | ((hi1 == hi2) & (lo1 > lo2))
10700 SDValue GT = DAG.getNode(X86ISD::PCMPGT, dl, MVT::v4i32, Op0, Op1);
10701 SDValue EQ = DAG.getNode(X86ISD::PCMPEQ, dl, MVT::v4i32, Op0, Op1);
10703 // Create masks for only the low parts/high parts of the 64 bit integers.
10704 static const int MaskHi[] = { 1, 1, 3, 3 };
10705 static const int MaskLo[] = { 0, 0, 2, 2 };
10706 SDValue EQHi = DAG.getVectorShuffle(MVT::v4i32, dl, EQ, EQ, MaskHi);
10707 SDValue GTLo = DAG.getVectorShuffle(MVT::v4i32, dl, GT, GT, MaskLo);
10708 SDValue GTHi = DAG.getVectorShuffle(MVT::v4i32, dl, GT, GT, MaskHi);
10710 SDValue Result = DAG.getNode(ISD::AND, dl, MVT::v4i32, EQHi, GTLo);
10711 Result = DAG.getNode(ISD::OR, dl, MVT::v4i32, Result, GTHi);
10714 Result = DAG.getNOT(dl, Result, MVT::v4i32);
10716 return DAG.getNode(ISD::BITCAST, dl, VT, Result);
10719 if (Opc == X86ISD::PCMPEQ && !Subtarget->hasSSE41()) {
10720 // If pcmpeqq is missing but pcmpeqd is available synthesize pcmpeqq with
10721 // pcmpeqd + pshufd + pand.
10722 assert(Subtarget->hasSSE2() && !FlipSigns && "Don't know how to lower!");
10724 // First cast everything to the right type.
10725 Op0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op0);
10726 Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op1);
10729 SDValue Result = DAG.getNode(Opc, dl, MVT::v4i32, Op0, Op1);
10731 // Make sure the lower and upper halves are both all-ones.
10732 static const int Mask[] = { 1, 0, 3, 2 };
10733 SDValue Shuf = DAG.getVectorShuffle(MVT::v4i32, dl, Result, Result, Mask);
10734 Result = DAG.getNode(ISD::AND, dl, MVT::v4i32, Result, Shuf);
10737 Result = DAG.getNOT(dl, Result, MVT::v4i32);
10739 return DAG.getNode(ISD::BITCAST, dl, VT, Result);
10743 // Since SSE has no unsigned integer comparisons, we need to flip the sign
10744 // bits of the inputs before performing those operations.
10746 EVT EltVT = VT.getVectorElementType();
10747 SDValue SB = DAG.getConstant(APInt::getSignBit(EltVT.getSizeInBits()), VT);
10748 Op0 = DAG.getNode(ISD::XOR, dl, VT, Op0, SB);
10749 Op1 = DAG.getNode(ISD::XOR, dl, VT, Op1, SB);
10752 SDValue Result = DAG.getNode(Opc, dl, VT, Op0, Op1);
10754 // If the logical-not of the result is required, perform that now.
10756 Result = DAG.getNOT(dl, Result, VT);
10759 Result = DAG.getNode(X86ISD::PCMPEQ, dl, VT, Op0, Result);
10762 Result = DAG.getNode(X86ISD::PCMPEQ, dl, VT, Result,
10763 getZeroVector(VT, Subtarget, DAG, dl));
10768 SDValue X86TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
10770 MVT VT = Op.getSimpleValueType();
10772 if (VT.isVector()) return LowerVSETCC(Op, Subtarget, DAG);
10774 assert(((!Subtarget->hasAVX512() && VT == MVT::i8) || (VT == MVT::i1))
10775 && "SetCC type must be 8-bit or 1-bit integer");
10776 SDValue Op0 = Op.getOperand(0);
10777 SDValue Op1 = Op.getOperand(1);
10779 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
10781 // Optimize to BT if possible.
10782 // Lower (X & (1 << N)) == 0 to BT(X, N).
10783 // Lower ((X >>u N) & 1) != 0 to BT(X, N).
10784 // Lower ((X >>s N) & 1) != 0 to BT(X, N).
10785 if (Op0.getOpcode() == ISD::AND && Op0.hasOneUse() &&
10786 Op1.getOpcode() == ISD::Constant &&
10787 cast<ConstantSDNode>(Op1)->isNullValue() &&
10788 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
10789 SDValue NewSetCC = LowerToBT(Op0, CC, dl, DAG);
10790 if (NewSetCC.getNode())
10794 // Look for X == 0, X == 1, X != 0, or X != 1. We can simplify some forms of
10796 if (Op1.getOpcode() == ISD::Constant &&
10797 (cast<ConstantSDNode>(Op1)->getZExtValue() == 1 ||
10798 cast<ConstantSDNode>(Op1)->isNullValue()) &&
10799 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
10801 // If the input is a setcc, then reuse the input setcc or use a new one with
10802 // the inverted condition.
10803 if (Op0.getOpcode() == X86ISD::SETCC) {
10804 X86::CondCode CCode = (X86::CondCode)Op0.getConstantOperandVal(0);
10805 bool Invert = (CC == ISD::SETNE) ^
10806 cast<ConstantSDNode>(Op1)->isNullValue();
10810 CCode = X86::GetOppositeBranchCondition(CCode);
10811 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
10812 DAG.getConstant(CCode, MVT::i8),
10813 Op0.getOperand(1));
10815 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, SetCC);
10819 if ((Op0.getValueType() == MVT::i1) && (Op1.getOpcode() == ISD::Constant) &&
10820 (cast<ConstantSDNode>(Op1)->getZExtValue() == 1) &&
10821 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
10823 ISD::CondCode NewCC = ISD::getSetCCInverse(CC, true);
10824 return DAG.getSetCC(dl, VT, Op0, DAG.getConstant(0, MVT::i1), NewCC);
10827 bool isFP = Op1.getSimpleValueType().isFloatingPoint();
10828 unsigned X86CC = TranslateX86CC(CC, isFP, Op0, Op1, DAG);
10829 if (X86CC == X86::COND_INVALID)
10832 SDValue EFLAGS = EmitCmp(Op0, Op1, X86CC, dl, DAG);
10833 EFLAGS = ConvertCmpIfNecessary(EFLAGS, DAG);
10834 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
10835 DAG.getConstant(X86CC, MVT::i8), EFLAGS);
10837 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, SetCC);
10841 // isX86LogicalCmp - Return true if opcode is a X86 logical comparison.
10842 static bool isX86LogicalCmp(SDValue Op) {
10843 unsigned Opc = Op.getNode()->getOpcode();
10844 if (Opc == X86ISD::CMP || Opc == X86ISD::COMI || Opc == X86ISD::UCOMI ||
10845 Opc == X86ISD::SAHF)
10847 if (Op.getResNo() == 1 &&
10848 (Opc == X86ISD::ADD ||
10849 Opc == X86ISD::SUB ||
10850 Opc == X86ISD::ADC ||
10851 Opc == X86ISD::SBB ||
10852 Opc == X86ISD::SMUL ||
10853 Opc == X86ISD::UMUL ||
10854 Opc == X86ISD::INC ||
10855 Opc == X86ISD::DEC ||
10856 Opc == X86ISD::OR ||
10857 Opc == X86ISD::XOR ||
10858 Opc == X86ISD::AND))
10861 if (Op.getResNo() == 2 && Opc == X86ISD::UMUL)
10867 static bool isTruncWithZeroHighBitsInput(SDValue V, SelectionDAG &DAG) {
10868 if (V.getOpcode() != ISD::TRUNCATE)
10871 SDValue VOp0 = V.getOperand(0);
10872 unsigned InBits = VOp0.getValueSizeInBits();
10873 unsigned Bits = V.getValueSizeInBits();
10874 return DAG.MaskedValueIsZero(VOp0, APInt::getHighBitsSet(InBits,InBits-Bits));
10877 SDValue X86TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {
10878 bool addTest = true;
10879 SDValue Cond = Op.getOperand(0);
10880 SDValue Op1 = Op.getOperand(1);
10881 SDValue Op2 = Op.getOperand(2);
10883 EVT VT = Op1.getValueType();
10886 // Lower fp selects into a CMP/AND/ANDN/OR sequence when the necessary SSE ops
10887 // are available. Otherwise fp cmovs get lowered into a less efficient branch
10888 // sequence later on.
10889 if (Cond.getOpcode() == ISD::SETCC &&
10890 ((Subtarget->hasSSE2() && (VT == MVT::f32 || VT == MVT::f64)) ||
10891 (Subtarget->hasSSE1() && VT == MVT::f32)) &&
10892 VT == Cond.getOperand(0).getValueType() && Cond->hasOneUse()) {
10893 SDValue CondOp0 = Cond.getOperand(0), CondOp1 = Cond.getOperand(1);
10894 int SSECC = translateX86FSETCC(
10895 cast<CondCodeSDNode>(Cond.getOperand(2))->get(), CondOp0, CondOp1);
10898 if (Subtarget->hasAVX512()) {
10899 SDValue Cmp = DAG.getNode(X86ISD::FSETCC, DL, MVT::i1, CondOp0, CondOp1,
10900 DAG.getConstant(SSECC, MVT::i8));
10901 return DAG.getNode(X86ISD::SELECT, DL, VT, Cmp, Op1, Op2);
10903 SDValue Cmp = DAG.getNode(X86ISD::FSETCC, DL, VT, CondOp0, CondOp1,
10904 DAG.getConstant(SSECC, MVT::i8));
10905 SDValue AndN = DAG.getNode(X86ISD::FANDN, DL, VT, Cmp, Op2);
10906 SDValue And = DAG.getNode(X86ISD::FAND, DL, VT, Cmp, Op1);
10907 return DAG.getNode(X86ISD::FOR, DL, VT, AndN, And);
10911 if (Cond.getOpcode() == ISD::SETCC) {
10912 SDValue NewCond = LowerSETCC(Cond, DAG);
10913 if (NewCond.getNode())
10917 // (select (x == 0), -1, y) -> (sign_bit (x - 1)) | y
10918 // (select (x == 0), y, -1) -> ~(sign_bit (x - 1)) | y
10919 // (select (x != 0), y, -1) -> (sign_bit (x - 1)) | y
10920 // (select (x != 0), -1, y) -> ~(sign_bit (x - 1)) | y
10921 if (Cond.getOpcode() == X86ISD::SETCC &&
10922 Cond.getOperand(1).getOpcode() == X86ISD::CMP &&
10923 isZero(Cond.getOperand(1).getOperand(1))) {
10924 SDValue Cmp = Cond.getOperand(1);
10926 unsigned CondCode =cast<ConstantSDNode>(Cond.getOperand(0))->getZExtValue();
10928 if ((isAllOnes(Op1) || isAllOnes(Op2)) &&
10929 (CondCode == X86::COND_E || CondCode == X86::COND_NE)) {
10930 SDValue Y = isAllOnes(Op2) ? Op1 : Op2;
10932 SDValue CmpOp0 = Cmp.getOperand(0);
10933 // Apply further optimizations for special cases
10934 // (select (x != 0), -1, 0) -> neg & sbb
10935 // (select (x == 0), 0, -1) -> neg & sbb
10936 if (ConstantSDNode *YC = dyn_cast<ConstantSDNode>(Y))
10937 if (YC->isNullValue() &&
10938 (isAllOnes(Op1) == (CondCode == X86::COND_NE))) {
10939 SDVTList VTs = DAG.getVTList(CmpOp0.getValueType(), MVT::i32);
10940 SDValue Neg = DAG.getNode(X86ISD::SUB, DL, VTs,
10941 DAG.getConstant(0, CmpOp0.getValueType()),
10943 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
10944 DAG.getConstant(X86::COND_B, MVT::i8),
10945 SDValue(Neg.getNode(), 1));
10949 Cmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32,
10950 CmpOp0, DAG.getConstant(1, CmpOp0.getValueType()));
10951 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
10953 SDValue Res = // Res = 0 or -1.
10954 DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
10955 DAG.getConstant(X86::COND_B, MVT::i8), Cmp);
10957 if (isAllOnes(Op1) != (CondCode == X86::COND_E))
10958 Res = DAG.getNOT(DL, Res, Res.getValueType());
10960 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(Op2);
10961 if (!N2C || !N2C->isNullValue())
10962 Res = DAG.getNode(ISD::OR, DL, Res.getValueType(), Res, Y);
10967 // Look past (and (setcc_carry (cmp ...)), 1).
10968 if (Cond.getOpcode() == ISD::AND &&
10969 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
10970 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
10971 if (C && C->getAPIntValue() == 1)
10972 Cond = Cond.getOperand(0);
10975 // If condition flag is set by a X86ISD::CMP, then use it as the condition
10976 // setting operand in place of the X86ISD::SETCC.
10977 unsigned CondOpcode = Cond.getOpcode();
10978 if (CondOpcode == X86ISD::SETCC ||
10979 CondOpcode == X86ISD::SETCC_CARRY) {
10980 CC = Cond.getOperand(0);
10982 SDValue Cmp = Cond.getOperand(1);
10983 unsigned Opc = Cmp.getOpcode();
10984 MVT VT = Op.getSimpleValueType();
10986 bool IllegalFPCMov = false;
10987 if (VT.isFloatingPoint() && !VT.isVector() &&
10988 !isScalarFPTypeInSSEReg(VT)) // FPStack?
10989 IllegalFPCMov = !hasFPCMov(cast<ConstantSDNode>(CC)->getSExtValue());
10991 if ((isX86LogicalCmp(Cmp) && !IllegalFPCMov) ||
10992 Opc == X86ISD::BT) { // FIXME
10996 } else if (CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO ||
10997 CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO ||
10998 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) &&
10999 Cond.getOperand(0).getValueType() != MVT::i8)) {
11000 SDValue LHS = Cond.getOperand(0);
11001 SDValue RHS = Cond.getOperand(1);
11002 unsigned X86Opcode;
11005 switch (CondOpcode) {
11006 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break;
11007 case ISD::SADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break;
11008 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break;
11009 case ISD::SSUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break;
11010 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break;
11011 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break;
11012 default: llvm_unreachable("unexpected overflowing operator");
11014 if (CondOpcode == ISD::UMULO)
11015 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(),
11018 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
11020 SDValue X86Op = DAG.getNode(X86Opcode, DL, VTs, LHS, RHS);
11022 if (CondOpcode == ISD::UMULO)
11023 Cond = X86Op.getValue(2);
11025 Cond = X86Op.getValue(1);
11027 CC = DAG.getConstant(X86Cond, MVT::i8);
11032 // Look pass the truncate if the high bits are known zero.
11033 if (isTruncWithZeroHighBitsInput(Cond, DAG))
11034 Cond = Cond.getOperand(0);
11036 // We know the result of AND is compared against zero. Try to match
11038 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
11039 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, DL, DAG);
11040 if (NewSetCC.getNode()) {
11041 CC = NewSetCC.getOperand(0);
11042 Cond = NewSetCC.getOperand(1);
11049 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
11050 Cond = EmitTest(Cond, X86::COND_NE, DL, DAG);
11053 // a < b ? -1 : 0 -> RES = ~setcc_carry
11054 // a < b ? 0 : -1 -> RES = setcc_carry
11055 // a >= b ? -1 : 0 -> RES = setcc_carry
11056 // a >= b ? 0 : -1 -> RES = ~setcc_carry
11057 if (Cond.getOpcode() == X86ISD::SUB) {
11058 Cond = ConvertCmpIfNecessary(Cond, DAG);
11059 unsigned CondCode = cast<ConstantSDNode>(CC)->getZExtValue();
11061 if ((CondCode == X86::COND_AE || CondCode == X86::COND_B) &&
11062 (isAllOnes(Op1) || isAllOnes(Op2)) && (isZero(Op1) || isZero(Op2))) {
11063 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
11064 DAG.getConstant(X86::COND_B, MVT::i8), Cond);
11065 if (isAllOnes(Op1) != (CondCode == X86::COND_B))
11066 return DAG.getNOT(DL, Res, Res.getValueType());
11071 // X86 doesn't have an i8 cmov. If both operands are the result of a truncate
11072 // widen the cmov and push the truncate through. This avoids introducing a new
11073 // branch during isel and doesn't add any extensions.
11074 if (Op.getValueType() == MVT::i8 &&
11075 Op1.getOpcode() == ISD::TRUNCATE && Op2.getOpcode() == ISD::TRUNCATE) {
11076 SDValue T1 = Op1.getOperand(0), T2 = Op2.getOperand(0);
11077 if (T1.getValueType() == T2.getValueType() &&
11078 // Blacklist CopyFromReg to avoid partial register stalls.
11079 T1.getOpcode() != ISD::CopyFromReg && T2.getOpcode()!=ISD::CopyFromReg){
11080 SDVTList VTs = DAG.getVTList(T1.getValueType(), MVT::Glue);
11081 SDValue Cmov = DAG.getNode(X86ISD::CMOV, DL, VTs, T2, T1, CC, Cond);
11082 return DAG.getNode(ISD::TRUNCATE, DL, Op.getValueType(), Cmov);
11086 // X86ISD::CMOV means set the result (which is operand 1) to the RHS if
11087 // condition is true.
11088 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue);
11089 SDValue Ops[] = { Op2, Op1, CC, Cond };
11090 return DAG.getNode(X86ISD::CMOV, DL, VTs, Ops);
11093 static SDValue LowerSIGN_EXTEND_AVX512(SDValue Op, SelectionDAG &DAG) {
11094 MVT VT = Op->getSimpleValueType(0);
11095 SDValue In = Op->getOperand(0);
11096 MVT InVT = In.getSimpleValueType();
11099 unsigned int NumElts = VT.getVectorNumElements();
11100 if (NumElts != 8 && NumElts != 16)
11103 if (VT.is512BitVector() && InVT.getVectorElementType() != MVT::i1)
11104 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
11106 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
11107 assert (InVT.getVectorElementType() == MVT::i1 && "Unexpected vector type");
11109 MVT ExtVT = (NumElts == 8) ? MVT::v8i64 : MVT::v16i32;
11110 Constant *C = ConstantInt::get(*DAG.getContext(),
11111 APInt::getAllOnesValue(ExtVT.getScalarType().getSizeInBits()));
11113 SDValue CP = DAG.getConstantPool(C, TLI.getPointerTy());
11114 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
11115 SDValue Ld = DAG.getLoad(ExtVT.getScalarType(), dl, DAG.getEntryNode(), CP,
11116 MachinePointerInfo::getConstantPool(),
11117 false, false, false, Alignment);
11118 SDValue Brcst = DAG.getNode(X86ISD::VBROADCASTM, dl, ExtVT, In, Ld);
11119 if (VT.is512BitVector())
11121 return DAG.getNode(X86ISD::VTRUNC, dl, VT, Brcst);
11124 static SDValue LowerSIGN_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
11125 SelectionDAG &DAG) {
11126 MVT VT = Op->getSimpleValueType(0);
11127 SDValue In = Op->getOperand(0);
11128 MVT InVT = In.getSimpleValueType();
11131 if (VT.is512BitVector() || InVT.getVectorElementType() == MVT::i1)
11132 return LowerSIGN_EXTEND_AVX512(Op, DAG);
11134 if ((VT != MVT::v4i64 || InVT != MVT::v4i32) &&
11135 (VT != MVT::v8i32 || InVT != MVT::v8i16) &&
11136 (VT != MVT::v16i16 || InVT != MVT::v16i8))
11139 if (Subtarget->hasInt256())
11140 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
11142 // Optimize vectors in AVX mode
11143 // Sign extend v8i16 to v8i32 and
11146 // Divide input vector into two parts
11147 // for v4i32 the shuffle mask will be { 0, 1, -1, -1} {2, 3, -1, -1}
11148 // use vpmovsx instruction to extend v4i32 -> v2i64; v8i16 -> v4i32
11149 // concat the vectors to original VT
11151 unsigned NumElems = InVT.getVectorNumElements();
11152 SDValue Undef = DAG.getUNDEF(InVT);
11154 SmallVector<int,8> ShufMask1(NumElems, -1);
11155 for (unsigned i = 0; i != NumElems/2; ++i)
11158 SDValue OpLo = DAG.getVectorShuffle(InVT, dl, In, Undef, &ShufMask1[0]);
11160 SmallVector<int,8> ShufMask2(NumElems, -1);
11161 for (unsigned i = 0; i != NumElems/2; ++i)
11162 ShufMask2[i] = i + NumElems/2;
11164 SDValue OpHi = DAG.getVectorShuffle(InVT, dl, In, Undef, &ShufMask2[0]);
11166 MVT HalfVT = MVT::getVectorVT(VT.getScalarType(),
11167 VT.getVectorNumElements()/2);
11169 OpLo = DAG.getNode(X86ISD::VSEXT, dl, HalfVT, OpLo);
11170 OpHi = DAG.getNode(X86ISD::VSEXT, dl, HalfVT, OpHi);
11172 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi);
11175 // isAndOrOfSingleUseSetCCs - Return true if node is an ISD::AND or
11176 // ISD::OR of two X86ISD::SETCC nodes each of which has no other use apart
11177 // from the AND / OR.
11178 static bool isAndOrOfSetCCs(SDValue Op, unsigned &Opc) {
11179 Opc = Op.getOpcode();
11180 if (Opc != ISD::OR && Opc != ISD::AND)
11182 return (Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
11183 Op.getOperand(0).hasOneUse() &&
11184 Op.getOperand(1).getOpcode() == X86ISD::SETCC &&
11185 Op.getOperand(1).hasOneUse());
11188 // isXor1OfSetCC - Return true if node is an ISD::XOR of a X86ISD::SETCC and
11189 // 1 and that the SETCC node has a single use.
11190 static bool isXor1OfSetCC(SDValue Op) {
11191 if (Op.getOpcode() != ISD::XOR)
11193 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
11194 if (N1C && N1C->getAPIntValue() == 1) {
11195 return Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
11196 Op.getOperand(0).hasOneUse();
11201 SDValue X86TargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) const {
11202 bool addTest = true;
11203 SDValue Chain = Op.getOperand(0);
11204 SDValue Cond = Op.getOperand(1);
11205 SDValue Dest = Op.getOperand(2);
11208 bool Inverted = false;
11210 if (Cond.getOpcode() == ISD::SETCC) {
11211 // Check for setcc([su]{add,sub,mul}o == 0).
11212 if (cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETEQ &&
11213 isa<ConstantSDNode>(Cond.getOperand(1)) &&
11214 cast<ConstantSDNode>(Cond.getOperand(1))->isNullValue() &&
11215 Cond.getOperand(0).getResNo() == 1 &&
11216 (Cond.getOperand(0).getOpcode() == ISD::SADDO ||
11217 Cond.getOperand(0).getOpcode() == ISD::UADDO ||
11218 Cond.getOperand(0).getOpcode() == ISD::SSUBO ||
11219 Cond.getOperand(0).getOpcode() == ISD::USUBO ||
11220 Cond.getOperand(0).getOpcode() == ISD::SMULO ||
11221 Cond.getOperand(0).getOpcode() == ISD::UMULO)) {
11223 Cond = Cond.getOperand(0);
11225 SDValue NewCond = LowerSETCC(Cond, DAG);
11226 if (NewCond.getNode())
11231 // FIXME: LowerXALUO doesn't handle these!!
11232 else if (Cond.getOpcode() == X86ISD::ADD ||
11233 Cond.getOpcode() == X86ISD::SUB ||
11234 Cond.getOpcode() == X86ISD::SMUL ||
11235 Cond.getOpcode() == X86ISD::UMUL)
11236 Cond = LowerXALUO(Cond, DAG);
11239 // Look pass (and (setcc_carry (cmp ...)), 1).
11240 if (Cond.getOpcode() == ISD::AND &&
11241 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
11242 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
11243 if (C && C->getAPIntValue() == 1)
11244 Cond = Cond.getOperand(0);
11247 // If condition flag is set by a X86ISD::CMP, then use it as the condition
11248 // setting operand in place of the X86ISD::SETCC.
11249 unsigned CondOpcode = Cond.getOpcode();
11250 if (CondOpcode == X86ISD::SETCC ||
11251 CondOpcode == X86ISD::SETCC_CARRY) {
11252 CC = Cond.getOperand(0);
11254 SDValue Cmp = Cond.getOperand(1);
11255 unsigned Opc = Cmp.getOpcode();
11256 // FIXME: WHY THE SPECIAL CASING OF LogicalCmp??
11257 if (isX86LogicalCmp(Cmp) || Opc == X86ISD::BT) {
11261 switch (cast<ConstantSDNode>(CC)->getZExtValue()) {
11265 // These can only come from an arithmetic instruction with overflow,
11266 // e.g. SADDO, UADDO.
11267 Cond = Cond.getNode()->getOperand(1);
11273 CondOpcode = Cond.getOpcode();
11274 if (CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO ||
11275 CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO ||
11276 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) &&
11277 Cond.getOperand(0).getValueType() != MVT::i8)) {
11278 SDValue LHS = Cond.getOperand(0);
11279 SDValue RHS = Cond.getOperand(1);
11280 unsigned X86Opcode;
11283 // Keep this in sync with LowerXALUO, otherwise we might create redundant
11284 // instructions that can't be removed afterwards (i.e. X86ISD::ADD and
11286 switch (CondOpcode) {
11287 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break;
11289 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
11291 X86Opcode = X86ISD::INC; X86Cond = X86::COND_O;
11294 X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break;
11295 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break;
11297 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
11299 X86Opcode = X86ISD::DEC; X86Cond = X86::COND_O;
11302 X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break;
11303 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break;
11304 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break;
11305 default: llvm_unreachable("unexpected overflowing operator");
11308 X86Cond = X86::GetOppositeBranchCondition((X86::CondCode)X86Cond);
11309 if (CondOpcode == ISD::UMULO)
11310 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(),
11313 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
11315 SDValue X86Op = DAG.getNode(X86Opcode, dl, VTs, LHS, RHS);
11317 if (CondOpcode == ISD::UMULO)
11318 Cond = X86Op.getValue(2);
11320 Cond = X86Op.getValue(1);
11322 CC = DAG.getConstant(X86Cond, MVT::i8);
11326 if (Cond.hasOneUse() && isAndOrOfSetCCs(Cond, CondOpc)) {
11327 SDValue Cmp = Cond.getOperand(0).getOperand(1);
11328 if (CondOpc == ISD::OR) {
11329 // Also, recognize the pattern generated by an FCMP_UNE. We can emit
11330 // two branches instead of an explicit OR instruction with a
11332 if (Cmp == Cond.getOperand(1).getOperand(1) &&
11333 isX86LogicalCmp(Cmp)) {
11334 CC = Cond.getOperand(0).getOperand(0);
11335 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
11336 Chain, Dest, CC, Cmp);
11337 CC = Cond.getOperand(1).getOperand(0);
11341 } else { // ISD::AND
11342 // Also, recognize the pattern generated by an FCMP_OEQ. We can emit
11343 // two branches instead of an explicit AND instruction with a
11344 // separate test. However, we only do this if this block doesn't
11345 // have a fall-through edge, because this requires an explicit
11346 // jmp when the condition is false.
11347 if (Cmp == Cond.getOperand(1).getOperand(1) &&
11348 isX86LogicalCmp(Cmp) &&
11349 Op.getNode()->hasOneUse()) {
11350 X86::CondCode CCode =
11351 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
11352 CCode = X86::GetOppositeBranchCondition(CCode);
11353 CC = DAG.getConstant(CCode, MVT::i8);
11354 SDNode *User = *Op.getNode()->use_begin();
11355 // Look for an unconditional branch following this conditional branch.
11356 // We need this because we need to reverse the successors in order
11357 // to implement FCMP_OEQ.
11358 if (User->getOpcode() == ISD::BR) {
11359 SDValue FalseBB = User->getOperand(1);
11361 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
11362 assert(NewBR == User);
11366 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
11367 Chain, Dest, CC, Cmp);
11368 X86::CondCode CCode =
11369 (X86::CondCode)Cond.getOperand(1).getConstantOperandVal(0);
11370 CCode = X86::GetOppositeBranchCondition(CCode);
11371 CC = DAG.getConstant(CCode, MVT::i8);
11377 } else if (Cond.hasOneUse() && isXor1OfSetCC(Cond)) {
11378 // Recognize for xorb (setcc), 1 patterns. The xor inverts the condition.
11379 // It should be transformed during dag combiner except when the condition
11380 // is set by a arithmetics with overflow node.
11381 X86::CondCode CCode =
11382 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
11383 CCode = X86::GetOppositeBranchCondition(CCode);
11384 CC = DAG.getConstant(CCode, MVT::i8);
11385 Cond = Cond.getOperand(0).getOperand(1);
11387 } else if (Cond.getOpcode() == ISD::SETCC &&
11388 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETOEQ) {
11389 // For FCMP_OEQ, we can emit
11390 // two branches instead of an explicit AND instruction with a
11391 // separate test. However, we only do this if this block doesn't
11392 // have a fall-through edge, because this requires an explicit
11393 // jmp when the condition is false.
11394 if (Op.getNode()->hasOneUse()) {
11395 SDNode *User = *Op.getNode()->use_begin();
11396 // Look for an unconditional branch following this conditional branch.
11397 // We need this because we need to reverse the successors in order
11398 // to implement FCMP_OEQ.
11399 if (User->getOpcode() == ISD::BR) {
11400 SDValue FalseBB = User->getOperand(1);
11402 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
11403 assert(NewBR == User);
11407 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
11408 Cond.getOperand(0), Cond.getOperand(1));
11409 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
11410 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
11411 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
11412 Chain, Dest, CC, Cmp);
11413 CC = DAG.getConstant(X86::COND_P, MVT::i8);
11418 } else if (Cond.getOpcode() == ISD::SETCC &&
11419 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETUNE) {
11420 // For FCMP_UNE, we can emit
11421 // two branches instead of an explicit AND instruction with a
11422 // separate test. However, we only do this if this block doesn't
11423 // have a fall-through edge, because this requires an explicit
11424 // jmp when the condition is false.
11425 if (Op.getNode()->hasOneUse()) {
11426 SDNode *User = *Op.getNode()->use_begin();
11427 // Look for an unconditional branch following this conditional branch.
11428 // We need this because we need to reverse the successors in order
11429 // to implement FCMP_UNE.
11430 if (User->getOpcode() == ISD::BR) {
11431 SDValue FalseBB = User->getOperand(1);
11433 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
11434 assert(NewBR == User);
11437 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
11438 Cond.getOperand(0), Cond.getOperand(1));
11439 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
11440 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
11441 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
11442 Chain, Dest, CC, Cmp);
11443 CC = DAG.getConstant(X86::COND_NP, MVT::i8);
11453 // Look pass the truncate if the high bits are known zero.
11454 if (isTruncWithZeroHighBitsInput(Cond, DAG))
11455 Cond = Cond.getOperand(0);
11457 // We know the result of AND is compared against zero. Try to match
11459 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
11460 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, dl, DAG);
11461 if (NewSetCC.getNode()) {
11462 CC = NewSetCC.getOperand(0);
11463 Cond = NewSetCC.getOperand(1);
11470 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
11471 Cond = EmitTest(Cond, X86::COND_NE, dl, DAG);
11473 Cond = ConvertCmpIfNecessary(Cond, DAG);
11474 return DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
11475 Chain, Dest, CC, Cond);
11478 // Lower dynamic stack allocation to _alloca call for Cygwin/Mingw targets.
11479 // Calls to _alloca is needed to probe the stack when allocating more than 4k
11480 // bytes in one go. Touching the stack at 4K increments is necessary to ensure
11481 // that the guard pages used by the OS virtual memory manager are allocated in
11482 // correct sequence.
11484 X86TargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
11485 SelectionDAG &DAG) const {
11486 MachineFunction &MF = DAG.getMachineFunction();
11487 bool SplitStack = MF.shouldSplitStack();
11488 bool Lower = (Subtarget->isOSWindows() && !Subtarget->isTargetMacho()) ||
11493 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
11494 SDNode* Node = Op.getNode();
11496 unsigned SPReg = TLI.getStackPointerRegisterToSaveRestore();
11497 assert(SPReg && "Target cannot require DYNAMIC_STACKALLOC expansion and"
11498 " not tell us which reg is the stack pointer!");
11499 EVT VT = Node->getValueType(0);
11500 SDValue Tmp1 = SDValue(Node, 0);
11501 SDValue Tmp2 = SDValue(Node, 1);
11502 SDValue Tmp3 = Node->getOperand(2);
11503 SDValue Chain = Tmp1.getOperand(0);
11505 // Chain the dynamic stack allocation so that it doesn't modify the stack
11506 // pointer when other instructions are using the stack.
11507 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(0, true),
11510 SDValue Size = Tmp2.getOperand(1);
11511 SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, VT);
11512 Chain = SP.getValue(1);
11513 unsigned Align = cast<ConstantSDNode>(Tmp3)->getZExtValue();
11514 const TargetFrameLowering &TFI = *getTargetMachine().getFrameLowering();
11515 unsigned StackAlign = TFI.getStackAlignment();
11516 Tmp1 = DAG.getNode(ISD::SUB, dl, VT, SP, Size); // Value
11517 if (Align > StackAlign)
11518 Tmp1 = DAG.getNode(ISD::AND, dl, VT, Tmp1,
11519 DAG.getConstant(-(uint64_t)Align, VT));
11520 Chain = DAG.getCopyToReg(Chain, dl, SPReg, Tmp1); // Output chain
11522 Tmp2 = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(0, true),
11523 DAG.getIntPtrConstant(0, true), SDValue(),
11526 SDValue Ops[2] = { Tmp1, Tmp2 };
11527 return DAG.getMergeValues(Ops, dl);
11531 SDValue Chain = Op.getOperand(0);
11532 SDValue Size = Op.getOperand(1);
11533 unsigned Align = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue();
11534 EVT VT = Op.getNode()->getValueType(0);
11536 bool Is64Bit = Subtarget->is64Bit();
11537 EVT SPTy = Is64Bit ? MVT::i64 : MVT::i32;
11540 MachineRegisterInfo &MRI = MF.getRegInfo();
11543 // The 64 bit implementation of segmented stacks needs to clobber both r10
11544 // r11. This makes it impossible to use it along with nested parameters.
11545 const Function *F = MF.getFunction();
11547 for (Function::const_arg_iterator I = F->arg_begin(), E = F->arg_end();
11549 if (I->hasNestAttr())
11550 report_fatal_error("Cannot use segmented stacks with functions that "
11551 "have nested arguments.");
11554 const TargetRegisterClass *AddrRegClass =
11555 getRegClassFor(Subtarget->is64Bit() ? MVT::i64:MVT::i32);
11556 unsigned Vreg = MRI.createVirtualRegister(AddrRegClass);
11557 Chain = DAG.getCopyToReg(Chain, dl, Vreg, Size);
11558 SDValue Value = DAG.getNode(X86ISD::SEG_ALLOCA, dl, SPTy, Chain,
11559 DAG.getRegister(Vreg, SPTy));
11560 SDValue Ops1[2] = { Value, Chain };
11561 return DAG.getMergeValues(Ops1, dl);
11564 unsigned Reg = (Subtarget->is64Bit() ? X86::RAX : X86::EAX);
11566 Chain = DAG.getCopyToReg(Chain, dl, Reg, Size, Flag);
11567 Flag = Chain.getValue(1);
11568 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
11570 Chain = DAG.getNode(X86ISD::WIN_ALLOCA, dl, NodeTys, Chain, Flag);
11572 const X86RegisterInfo *RegInfo =
11573 static_cast<const X86RegisterInfo*>(getTargetMachine().getRegisterInfo());
11574 unsigned SPReg = RegInfo->getStackRegister();
11575 SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, SPTy);
11576 Chain = SP.getValue(1);
11579 SP = DAG.getNode(ISD::AND, dl, VT, SP.getValue(0),
11580 DAG.getConstant(-(uint64_t)Align, VT));
11581 Chain = DAG.getCopyToReg(Chain, dl, SPReg, SP);
11584 SDValue Ops1[2] = { SP, Chain };
11585 return DAG.getMergeValues(Ops1, dl);
11589 SDValue X86TargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const {
11590 MachineFunction &MF = DAG.getMachineFunction();
11591 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
11593 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
11596 if (!Subtarget->is64Bit() || Subtarget->isTargetWin64()) {
11597 // vastart just stores the address of the VarArgsFrameIndex slot into the
11598 // memory location argument.
11599 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
11601 return DAG.getStore(Op.getOperand(0), DL, FR, Op.getOperand(1),
11602 MachinePointerInfo(SV), false, false, 0);
11606 // gp_offset (0 - 6 * 8)
11607 // fp_offset (48 - 48 + 8 * 16)
11608 // overflow_arg_area (point to parameters coming in memory).
11610 SmallVector<SDValue, 8> MemOps;
11611 SDValue FIN = Op.getOperand(1);
11613 SDValue Store = DAG.getStore(Op.getOperand(0), DL,
11614 DAG.getConstant(FuncInfo->getVarArgsGPOffset(),
11616 FIN, MachinePointerInfo(SV), false, false, 0);
11617 MemOps.push_back(Store);
11620 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
11621 FIN, DAG.getIntPtrConstant(4));
11622 Store = DAG.getStore(Op.getOperand(0), DL,
11623 DAG.getConstant(FuncInfo->getVarArgsFPOffset(),
11625 FIN, MachinePointerInfo(SV, 4), false, false, 0);
11626 MemOps.push_back(Store);
11628 // Store ptr to overflow_arg_area
11629 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
11630 FIN, DAG.getIntPtrConstant(4));
11631 SDValue OVFIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
11633 Store = DAG.getStore(Op.getOperand(0), DL, OVFIN, FIN,
11634 MachinePointerInfo(SV, 8),
11636 MemOps.push_back(Store);
11638 // Store ptr to reg_save_area.
11639 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
11640 FIN, DAG.getIntPtrConstant(8));
11641 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
11643 Store = DAG.getStore(Op.getOperand(0), DL, RSFIN, FIN,
11644 MachinePointerInfo(SV, 16), false, false, 0);
11645 MemOps.push_back(Store);
11646 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOps);
11649 SDValue X86TargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG) const {
11650 assert(Subtarget->is64Bit() &&
11651 "LowerVAARG only handles 64-bit va_arg!");
11652 assert((Subtarget->isTargetLinux() ||
11653 Subtarget->isTargetDarwin()) &&
11654 "Unhandled target in LowerVAARG");
11655 assert(Op.getNode()->getNumOperands() == 4);
11656 SDValue Chain = Op.getOperand(0);
11657 SDValue SrcPtr = Op.getOperand(1);
11658 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
11659 unsigned Align = Op.getConstantOperandVal(3);
11662 EVT ArgVT = Op.getNode()->getValueType(0);
11663 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
11664 uint32_t ArgSize = getDataLayout()->getTypeAllocSize(ArgTy);
11667 // Decide which area this value should be read from.
11668 // TODO: Implement the AMD64 ABI in its entirety. This simple
11669 // selection mechanism works only for the basic types.
11670 if (ArgVT == MVT::f80) {
11671 llvm_unreachable("va_arg for f80 not yet implemented");
11672 } else if (ArgVT.isFloatingPoint() && ArgSize <= 16 /*bytes*/) {
11673 ArgMode = 2; // Argument passed in XMM register. Use fp_offset.
11674 } else if (ArgVT.isInteger() && ArgSize <= 32 /*bytes*/) {
11675 ArgMode = 1; // Argument passed in GPR64 register(s). Use gp_offset.
11677 llvm_unreachable("Unhandled argument type in LowerVAARG");
11680 if (ArgMode == 2) {
11681 // Sanity Check: Make sure using fp_offset makes sense.
11682 assert(!getTargetMachine().Options.UseSoftFloat &&
11683 !(DAG.getMachineFunction()
11684 .getFunction()->getAttributes()
11685 .hasAttribute(AttributeSet::FunctionIndex,
11686 Attribute::NoImplicitFloat)) &&
11687 Subtarget->hasSSE1());
11690 // Insert VAARG_64 node into the DAG
11691 // VAARG_64 returns two values: Variable Argument Address, Chain
11692 SmallVector<SDValue, 11> InstOps;
11693 InstOps.push_back(Chain);
11694 InstOps.push_back(SrcPtr);
11695 InstOps.push_back(DAG.getConstant(ArgSize, MVT::i32));
11696 InstOps.push_back(DAG.getConstant(ArgMode, MVT::i8));
11697 InstOps.push_back(DAG.getConstant(Align, MVT::i32));
11698 SDVTList VTs = DAG.getVTList(getPointerTy(), MVT::Other);
11699 SDValue VAARG = DAG.getMemIntrinsicNode(X86ISD::VAARG_64, dl,
11700 VTs, InstOps, MVT::i64,
11701 MachinePointerInfo(SV),
11703 /*Volatile=*/false,
11705 /*WriteMem=*/true);
11706 Chain = VAARG.getValue(1);
11708 // Load the next argument and return it
11709 return DAG.getLoad(ArgVT, dl,
11712 MachinePointerInfo(),
11713 false, false, false, 0);
11716 static SDValue LowerVACOPY(SDValue Op, const X86Subtarget *Subtarget,
11717 SelectionDAG &DAG) {
11718 // X86-64 va_list is a struct { i32, i32, i8*, i8* }.
11719 assert(Subtarget->is64Bit() && "This code only handles 64-bit va_copy!");
11720 SDValue Chain = Op.getOperand(0);
11721 SDValue DstPtr = Op.getOperand(1);
11722 SDValue SrcPtr = Op.getOperand(2);
11723 const Value *DstSV = cast<SrcValueSDNode>(Op.getOperand(3))->getValue();
11724 const Value *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
11727 return DAG.getMemcpy(Chain, DL, DstPtr, SrcPtr,
11728 DAG.getIntPtrConstant(24), 8, /*isVolatile*/false,
11730 MachinePointerInfo(DstSV), MachinePointerInfo(SrcSV));
11733 // getTargetVShiftByConstNode - Handle vector element shifts where the shift
11734 // amount is a constant. Takes immediate version of shift as input.
11735 static SDValue getTargetVShiftByConstNode(unsigned Opc, SDLoc dl, MVT VT,
11736 SDValue SrcOp, uint64_t ShiftAmt,
11737 SelectionDAG &DAG) {
11738 MVT ElementType = VT.getVectorElementType();
11740 // Fold this packed shift into its first operand if ShiftAmt is 0.
11744 // Check for ShiftAmt >= element width
11745 if (ShiftAmt >= ElementType.getSizeInBits()) {
11746 if (Opc == X86ISD::VSRAI)
11747 ShiftAmt = ElementType.getSizeInBits() - 1;
11749 return DAG.getConstant(0, VT);
11752 assert((Opc == X86ISD::VSHLI || Opc == X86ISD::VSRLI || Opc == X86ISD::VSRAI)
11753 && "Unknown target vector shift-by-constant node");
11755 // Fold this packed vector shift into a build vector if SrcOp is a
11756 // vector of Constants or UNDEFs, and SrcOp valuetype is the same as VT.
11757 if (VT == SrcOp.getSimpleValueType() &&
11758 ISD::isBuildVectorOfConstantSDNodes(SrcOp.getNode())) {
11759 SmallVector<SDValue, 8> Elts;
11760 unsigned NumElts = SrcOp->getNumOperands();
11761 ConstantSDNode *ND;
11764 default: llvm_unreachable(nullptr);
11765 case X86ISD::VSHLI:
11766 for (unsigned i=0; i!=NumElts; ++i) {
11767 SDValue CurrentOp = SrcOp->getOperand(i);
11768 if (CurrentOp->getOpcode() == ISD::UNDEF) {
11769 Elts.push_back(CurrentOp);
11772 ND = cast<ConstantSDNode>(CurrentOp);
11773 const APInt &C = ND->getAPIntValue();
11774 Elts.push_back(DAG.getConstant(C.shl(ShiftAmt), ElementType));
11777 case X86ISD::VSRLI:
11778 for (unsigned i=0; i!=NumElts; ++i) {
11779 SDValue CurrentOp = SrcOp->getOperand(i);
11780 if (CurrentOp->getOpcode() == ISD::UNDEF) {
11781 Elts.push_back(CurrentOp);
11784 ND = cast<ConstantSDNode>(CurrentOp);
11785 const APInt &C = ND->getAPIntValue();
11786 Elts.push_back(DAG.getConstant(C.lshr(ShiftAmt), ElementType));
11789 case X86ISD::VSRAI:
11790 for (unsigned i=0; i!=NumElts; ++i) {
11791 SDValue CurrentOp = SrcOp->getOperand(i);
11792 if (CurrentOp->getOpcode() == ISD::UNDEF) {
11793 Elts.push_back(CurrentOp);
11796 ND = cast<ConstantSDNode>(CurrentOp);
11797 const APInt &C = ND->getAPIntValue();
11798 Elts.push_back(DAG.getConstant(C.ashr(ShiftAmt), ElementType));
11803 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Elts);
11806 return DAG.getNode(Opc, dl, VT, SrcOp, DAG.getConstant(ShiftAmt, MVT::i8));
11809 // getTargetVShiftNode - Handle vector element shifts where the shift amount
11810 // may or may not be a constant. Takes immediate version of shift as input.
11811 static SDValue getTargetVShiftNode(unsigned Opc, SDLoc dl, MVT VT,
11812 SDValue SrcOp, SDValue ShAmt,
11813 SelectionDAG &DAG) {
11814 assert(ShAmt.getValueType() == MVT::i32 && "ShAmt is not i32");
11816 // Catch shift-by-constant.
11817 if (ConstantSDNode *CShAmt = dyn_cast<ConstantSDNode>(ShAmt))
11818 return getTargetVShiftByConstNode(Opc, dl, VT, SrcOp,
11819 CShAmt->getZExtValue(), DAG);
11821 // Change opcode to non-immediate version
11823 default: llvm_unreachable("Unknown target vector shift node");
11824 case X86ISD::VSHLI: Opc = X86ISD::VSHL; break;
11825 case X86ISD::VSRLI: Opc = X86ISD::VSRL; break;
11826 case X86ISD::VSRAI: Opc = X86ISD::VSRA; break;
11829 // Need to build a vector containing shift amount
11830 // Shift amount is 32-bits, but SSE instructions read 64-bit, so fill with 0
11833 ShOps[1] = DAG.getConstant(0, MVT::i32);
11834 ShOps[2] = ShOps[3] = DAG.getUNDEF(MVT::i32);
11835 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, ShOps);
11837 // The return type has to be a 128-bit type with the same element
11838 // type as the input type.
11839 MVT EltVT = VT.getVectorElementType();
11840 EVT ShVT = MVT::getVectorVT(EltVT, 128/EltVT.getSizeInBits());
11842 ShAmt = DAG.getNode(ISD::BITCAST, dl, ShVT, ShAmt);
11843 return DAG.getNode(Opc, dl, VT, SrcOp, ShAmt);
11846 static SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) {
11848 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
11850 default: return SDValue(); // Don't custom lower most intrinsics.
11851 // Comparison intrinsics.
11852 case Intrinsic::x86_sse_comieq_ss:
11853 case Intrinsic::x86_sse_comilt_ss:
11854 case Intrinsic::x86_sse_comile_ss:
11855 case Intrinsic::x86_sse_comigt_ss:
11856 case Intrinsic::x86_sse_comige_ss:
11857 case Intrinsic::x86_sse_comineq_ss:
11858 case Intrinsic::x86_sse_ucomieq_ss:
11859 case Intrinsic::x86_sse_ucomilt_ss:
11860 case Intrinsic::x86_sse_ucomile_ss:
11861 case Intrinsic::x86_sse_ucomigt_ss:
11862 case Intrinsic::x86_sse_ucomige_ss:
11863 case Intrinsic::x86_sse_ucomineq_ss:
11864 case Intrinsic::x86_sse2_comieq_sd:
11865 case Intrinsic::x86_sse2_comilt_sd:
11866 case Intrinsic::x86_sse2_comile_sd:
11867 case Intrinsic::x86_sse2_comigt_sd:
11868 case Intrinsic::x86_sse2_comige_sd:
11869 case Intrinsic::x86_sse2_comineq_sd:
11870 case Intrinsic::x86_sse2_ucomieq_sd:
11871 case Intrinsic::x86_sse2_ucomilt_sd:
11872 case Intrinsic::x86_sse2_ucomile_sd:
11873 case Intrinsic::x86_sse2_ucomigt_sd:
11874 case Intrinsic::x86_sse2_ucomige_sd:
11875 case Intrinsic::x86_sse2_ucomineq_sd: {
11879 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
11880 case Intrinsic::x86_sse_comieq_ss:
11881 case Intrinsic::x86_sse2_comieq_sd:
11882 Opc = X86ISD::COMI;
11885 case Intrinsic::x86_sse_comilt_ss:
11886 case Intrinsic::x86_sse2_comilt_sd:
11887 Opc = X86ISD::COMI;
11890 case Intrinsic::x86_sse_comile_ss:
11891 case Intrinsic::x86_sse2_comile_sd:
11892 Opc = X86ISD::COMI;
11895 case Intrinsic::x86_sse_comigt_ss:
11896 case Intrinsic::x86_sse2_comigt_sd:
11897 Opc = X86ISD::COMI;
11900 case Intrinsic::x86_sse_comige_ss:
11901 case Intrinsic::x86_sse2_comige_sd:
11902 Opc = X86ISD::COMI;
11905 case Intrinsic::x86_sse_comineq_ss:
11906 case Intrinsic::x86_sse2_comineq_sd:
11907 Opc = X86ISD::COMI;
11910 case Intrinsic::x86_sse_ucomieq_ss:
11911 case Intrinsic::x86_sse2_ucomieq_sd:
11912 Opc = X86ISD::UCOMI;
11915 case Intrinsic::x86_sse_ucomilt_ss:
11916 case Intrinsic::x86_sse2_ucomilt_sd:
11917 Opc = X86ISD::UCOMI;
11920 case Intrinsic::x86_sse_ucomile_ss:
11921 case Intrinsic::x86_sse2_ucomile_sd:
11922 Opc = X86ISD::UCOMI;
11925 case Intrinsic::x86_sse_ucomigt_ss:
11926 case Intrinsic::x86_sse2_ucomigt_sd:
11927 Opc = X86ISD::UCOMI;
11930 case Intrinsic::x86_sse_ucomige_ss:
11931 case Intrinsic::x86_sse2_ucomige_sd:
11932 Opc = X86ISD::UCOMI;
11935 case Intrinsic::x86_sse_ucomineq_ss:
11936 case Intrinsic::x86_sse2_ucomineq_sd:
11937 Opc = X86ISD::UCOMI;
11942 SDValue LHS = Op.getOperand(1);
11943 SDValue RHS = Op.getOperand(2);
11944 unsigned X86CC = TranslateX86CC(CC, true, LHS, RHS, DAG);
11945 assert(X86CC != X86::COND_INVALID && "Unexpected illegal condition!");
11946 SDValue Cond = DAG.getNode(Opc, dl, MVT::i32, LHS, RHS);
11947 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
11948 DAG.getConstant(X86CC, MVT::i8), Cond);
11949 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
11952 // Arithmetic intrinsics.
11953 case Intrinsic::x86_sse2_pmulu_dq:
11954 case Intrinsic::x86_avx2_pmulu_dq:
11955 return DAG.getNode(X86ISD::PMULUDQ, dl, Op.getValueType(),
11956 Op.getOperand(1), Op.getOperand(2));
11958 case Intrinsic::x86_sse41_pmuldq:
11959 case Intrinsic::x86_avx2_pmul_dq:
11960 return DAG.getNode(X86ISD::PMULDQ, dl, Op.getValueType(),
11961 Op.getOperand(1), Op.getOperand(2));
11963 case Intrinsic::x86_sse2_pmulhu_w:
11964 case Intrinsic::x86_avx2_pmulhu_w:
11965 return DAG.getNode(ISD::MULHU, dl, Op.getValueType(),
11966 Op.getOperand(1), Op.getOperand(2));
11968 case Intrinsic::x86_sse2_pmulh_w:
11969 case Intrinsic::x86_avx2_pmulh_w:
11970 return DAG.getNode(ISD::MULHS, dl, Op.getValueType(),
11971 Op.getOperand(1), Op.getOperand(2));
11973 // SSE2/AVX2 sub with unsigned saturation intrinsics
11974 case Intrinsic::x86_sse2_psubus_b:
11975 case Intrinsic::x86_sse2_psubus_w:
11976 case Intrinsic::x86_avx2_psubus_b:
11977 case Intrinsic::x86_avx2_psubus_w:
11978 return DAG.getNode(X86ISD::SUBUS, dl, Op.getValueType(),
11979 Op.getOperand(1), Op.getOperand(2));
11981 // SSE3/AVX horizontal add/sub intrinsics
11982 case Intrinsic::x86_sse3_hadd_ps:
11983 case Intrinsic::x86_sse3_hadd_pd:
11984 case Intrinsic::x86_avx_hadd_ps_256:
11985 case Intrinsic::x86_avx_hadd_pd_256:
11986 case Intrinsic::x86_sse3_hsub_ps:
11987 case Intrinsic::x86_sse3_hsub_pd:
11988 case Intrinsic::x86_avx_hsub_ps_256:
11989 case Intrinsic::x86_avx_hsub_pd_256:
11990 case Intrinsic::x86_ssse3_phadd_w_128:
11991 case Intrinsic::x86_ssse3_phadd_d_128:
11992 case Intrinsic::x86_avx2_phadd_w:
11993 case Intrinsic::x86_avx2_phadd_d:
11994 case Intrinsic::x86_ssse3_phsub_w_128:
11995 case Intrinsic::x86_ssse3_phsub_d_128:
11996 case Intrinsic::x86_avx2_phsub_w:
11997 case Intrinsic::x86_avx2_phsub_d: {
12000 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
12001 case Intrinsic::x86_sse3_hadd_ps:
12002 case Intrinsic::x86_sse3_hadd_pd:
12003 case Intrinsic::x86_avx_hadd_ps_256:
12004 case Intrinsic::x86_avx_hadd_pd_256:
12005 Opcode = X86ISD::FHADD;
12007 case Intrinsic::x86_sse3_hsub_ps:
12008 case Intrinsic::x86_sse3_hsub_pd:
12009 case Intrinsic::x86_avx_hsub_ps_256:
12010 case Intrinsic::x86_avx_hsub_pd_256:
12011 Opcode = X86ISD::FHSUB;
12013 case Intrinsic::x86_ssse3_phadd_w_128:
12014 case Intrinsic::x86_ssse3_phadd_d_128:
12015 case Intrinsic::x86_avx2_phadd_w:
12016 case Intrinsic::x86_avx2_phadd_d:
12017 Opcode = X86ISD::HADD;
12019 case Intrinsic::x86_ssse3_phsub_w_128:
12020 case Intrinsic::x86_ssse3_phsub_d_128:
12021 case Intrinsic::x86_avx2_phsub_w:
12022 case Intrinsic::x86_avx2_phsub_d:
12023 Opcode = X86ISD::HSUB;
12026 return DAG.getNode(Opcode, dl, Op.getValueType(),
12027 Op.getOperand(1), Op.getOperand(2));
12030 // SSE2/SSE41/AVX2 integer max/min intrinsics.
12031 case Intrinsic::x86_sse2_pmaxu_b:
12032 case Intrinsic::x86_sse41_pmaxuw:
12033 case Intrinsic::x86_sse41_pmaxud:
12034 case Intrinsic::x86_avx2_pmaxu_b:
12035 case Intrinsic::x86_avx2_pmaxu_w:
12036 case Intrinsic::x86_avx2_pmaxu_d:
12037 case Intrinsic::x86_sse2_pminu_b:
12038 case Intrinsic::x86_sse41_pminuw:
12039 case Intrinsic::x86_sse41_pminud:
12040 case Intrinsic::x86_avx2_pminu_b:
12041 case Intrinsic::x86_avx2_pminu_w:
12042 case Intrinsic::x86_avx2_pminu_d:
12043 case Intrinsic::x86_sse41_pmaxsb:
12044 case Intrinsic::x86_sse2_pmaxs_w:
12045 case Intrinsic::x86_sse41_pmaxsd:
12046 case Intrinsic::x86_avx2_pmaxs_b:
12047 case Intrinsic::x86_avx2_pmaxs_w:
12048 case Intrinsic::x86_avx2_pmaxs_d:
12049 case Intrinsic::x86_sse41_pminsb:
12050 case Intrinsic::x86_sse2_pmins_w:
12051 case Intrinsic::x86_sse41_pminsd:
12052 case Intrinsic::x86_avx2_pmins_b:
12053 case Intrinsic::x86_avx2_pmins_w:
12054 case Intrinsic::x86_avx2_pmins_d: {
12057 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
12058 case Intrinsic::x86_sse2_pmaxu_b:
12059 case Intrinsic::x86_sse41_pmaxuw:
12060 case Intrinsic::x86_sse41_pmaxud:
12061 case Intrinsic::x86_avx2_pmaxu_b:
12062 case Intrinsic::x86_avx2_pmaxu_w:
12063 case Intrinsic::x86_avx2_pmaxu_d:
12064 Opcode = X86ISD::UMAX;
12066 case Intrinsic::x86_sse2_pminu_b:
12067 case Intrinsic::x86_sse41_pminuw:
12068 case Intrinsic::x86_sse41_pminud:
12069 case Intrinsic::x86_avx2_pminu_b:
12070 case Intrinsic::x86_avx2_pminu_w:
12071 case Intrinsic::x86_avx2_pminu_d:
12072 Opcode = X86ISD::UMIN;
12074 case Intrinsic::x86_sse41_pmaxsb:
12075 case Intrinsic::x86_sse2_pmaxs_w:
12076 case Intrinsic::x86_sse41_pmaxsd:
12077 case Intrinsic::x86_avx2_pmaxs_b:
12078 case Intrinsic::x86_avx2_pmaxs_w:
12079 case Intrinsic::x86_avx2_pmaxs_d:
12080 Opcode = X86ISD::SMAX;
12082 case Intrinsic::x86_sse41_pminsb:
12083 case Intrinsic::x86_sse2_pmins_w:
12084 case Intrinsic::x86_sse41_pminsd:
12085 case Intrinsic::x86_avx2_pmins_b:
12086 case Intrinsic::x86_avx2_pmins_w:
12087 case Intrinsic::x86_avx2_pmins_d:
12088 Opcode = X86ISD::SMIN;
12091 return DAG.getNode(Opcode, dl, Op.getValueType(),
12092 Op.getOperand(1), Op.getOperand(2));
12095 // SSE/SSE2/AVX floating point max/min intrinsics.
12096 case Intrinsic::x86_sse_max_ps:
12097 case Intrinsic::x86_sse2_max_pd:
12098 case Intrinsic::x86_avx_max_ps_256:
12099 case Intrinsic::x86_avx_max_pd_256:
12100 case Intrinsic::x86_sse_min_ps:
12101 case Intrinsic::x86_sse2_min_pd:
12102 case Intrinsic::x86_avx_min_ps_256:
12103 case Intrinsic::x86_avx_min_pd_256: {
12106 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
12107 case Intrinsic::x86_sse_max_ps:
12108 case Intrinsic::x86_sse2_max_pd:
12109 case Intrinsic::x86_avx_max_ps_256:
12110 case Intrinsic::x86_avx_max_pd_256:
12111 Opcode = X86ISD::FMAX;
12113 case Intrinsic::x86_sse_min_ps:
12114 case Intrinsic::x86_sse2_min_pd:
12115 case Intrinsic::x86_avx_min_ps_256:
12116 case Intrinsic::x86_avx_min_pd_256:
12117 Opcode = X86ISD::FMIN;
12120 return DAG.getNode(Opcode, dl, Op.getValueType(),
12121 Op.getOperand(1), Op.getOperand(2));
12124 // AVX2 variable shift intrinsics
12125 case Intrinsic::x86_avx2_psllv_d:
12126 case Intrinsic::x86_avx2_psllv_q:
12127 case Intrinsic::x86_avx2_psllv_d_256:
12128 case Intrinsic::x86_avx2_psllv_q_256:
12129 case Intrinsic::x86_avx2_psrlv_d:
12130 case Intrinsic::x86_avx2_psrlv_q:
12131 case Intrinsic::x86_avx2_psrlv_d_256:
12132 case Intrinsic::x86_avx2_psrlv_q_256:
12133 case Intrinsic::x86_avx2_psrav_d:
12134 case Intrinsic::x86_avx2_psrav_d_256: {
12137 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
12138 case Intrinsic::x86_avx2_psllv_d:
12139 case Intrinsic::x86_avx2_psllv_q:
12140 case Intrinsic::x86_avx2_psllv_d_256:
12141 case Intrinsic::x86_avx2_psllv_q_256:
12144 case Intrinsic::x86_avx2_psrlv_d:
12145 case Intrinsic::x86_avx2_psrlv_q:
12146 case Intrinsic::x86_avx2_psrlv_d_256:
12147 case Intrinsic::x86_avx2_psrlv_q_256:
12150 case Intrinsic::x86_avx2_psrav_d:
12151 case Intrinsic::x86_avx2_psrav_d_256:
12155 return DAG.getNode(Opcode, dl, Op.getValueType(),
12156 Op.getOperand(1), Op.getOperand(2));
12159 case Intrinsic::x86_ssse3_pshuf_b_128:
12160 case Intrinsic::x86_avx2_pshuf_b:
12161 return DAG.getNode(X86ISD::PSHUFB, dl, Op.getValueType(),
12162 Op.getOperand(1), Op.getOperand(2));
12164 case Intrinsic::x86_ssse3_psign_b_128:
12165 case Intrinsic::x86_ssse3_psign_w_128:
12166 case Intrinsic::x86_ssse3_psign_d_128:
12167 case Intrinsic::x86_avx2_psign_b:
12168 case Intrinsic::x86_avx2_psign_w:
12169 case Intrinsic::x86_avx2_psign_d:
12170 return DAG.getNode(X86ISD::PSIGN, dl, Op.getValueType(),
12171 Op.getOperand(1), Op.getOperand(2));
12173 case Intrinsic::x86_sse41_insertps:
12174 return DAG.getNode(X86ISD::INSERTPS, dl, Op.getValueType(),
12175 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
12177 case Intrinsic::x86_avx_vperm2f128_ps_256:
12178 case Intrinsic::x86_avx_vperm2f128_pd_256:
12179 case Intrinsic::x86_avx_vperm2f128_si_256:
12180 case Intrinsic::x86_avx2_vperm2i128:
12181 return DAG.getNode(X86ISD::VPERM2X128, dl, Op.getValueType(),
12182 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
12184 case Intrinsic::x86_avx2_permd:
12185 case Intrinsic::x86_avx2_permps:
12186 // Operands intentionally swapped. Mask is last operand to intrinsic,
12187 // but second operand for node/instruction.
12188 return DAG.getNode(X86ISD::VPERMV, dl, Op.getValueType(),
12189 Op.getOperand(2), Op.getOperand(1));
12191 case Intrinsic::x86_sse_sqrt_ps:
12192 case Intrinsic::x86_sse2_sqrt_pd:
12193 case Intrinsic::x86_avx_sqrt_ps_256:
12194 case Intrinsic::x86_avx_sqrt_pd_256:
12195 return DAG.getNode(ISD::FSQRT, dl, Op.getValueType(), Op.getOperand(1));
12197 // ptest and testp intrinsics. The intrinsic these come from are designed to
12198 // return an integer value, not just an instruction so lower it to the ptest
12199 // or testp pattern and a setcc for the result.
12200 case Intrinsic::x86_sse41_ptestz:
12201 case Intrinsic::x86_sse41_ptestc:
12202 case Intrinsic::x86_sse41_ptestnzc:
12203 case Intrinsic::x86_avx_ptestz_256:
12204 case Intrinsic::x86_avx_ptestc_256:
12205 case Intrinsic::x86_avx_ptestnzc_256:
12206 case Intrinsic::x86_avx_vtestz_ps:
12207 case Intrinsic::x86_avx_vtestc_ps:
12208 case Intrinsic::x86_avx_vtestnzc_ps:
12209 case Intrinsic::x86_avx_vtestz_pd:
12210 case Intrinsic::x86_avx_vtestc_pd:
12211 case Intrinsic::x86_avx_vtestnzc_pd:
12212 case Intrinsic::x86_avx_vtestz_ps_256:
12213 case Intrinsic::x86_avx_vtestc_ps_256:
12214 case Intrinsic::x86_avx_vtestnzc_ps_256:
12215 case Intrinsic::x86_avx_vtestz_pd_256:
12216 case Intrinsic::x86_avx_vtestc_pd_256:
12217 case Intrinsic::x86_avx_vtestnzc_pd_256: {
12218 bool IsTestPacked = false;
12221 default: llvm_unreachable("Bad fallthrough in Intrinsic lowering.");
12222 case Intrinsic::x86_avx_vtestz_ps:
12223 case Intrinsic::x86_avx_vtestz_pd:
12224 case Intrinsic::x86_avx_vtestz_ps_256:
12225 case Intrinsic::x86_avx_vtestz_pd_256:
12226 IsTestPacked = true; // Fallthrough
12227 case Intrinsic::x86_sse41_ptestz:
12228 case Intrinsic::x86_avx_ptestz_256:
12230 X86CC = X86::COND_E;
12232 case Intrinsic::x86_avx_vtestc_ps:
12233 case Intrinsic::x86_avx_vtestc_pd:
12234 case Intrinsic::x86_avx_vtestc_ps_256:
12235 case Intrinsic::x86_avx_vtestc_pd_256:
12236 IsTestPacked = true; // Fallthrough
12237 case Intrinsic::x86_sse41_ptestc:
12238 case Intrinsic::x86_avx_ptestc_256:
12240 X86CC = X86::COND_B;
12242 case Intrinsic::x86_avx_vtestnzc_ps:
12243 case Intrinsic::x86_avx_vtestnzc_pd:
12244 case Intrinsic::x86_avx_vtestnzc_ps_256:
12245 case Intrinsic::x86_avx_vtestnzc_pd_256:
12246 IsTestPacked = true; // Fallthrough
12247 case Intrinsic::x86_sse41_ptestnzc:
12248 case Intrinsic::x86_avx_ptestnzc_256:
12250 X86CC = X86::COND_A;
12254 SDValue LHS = Op.getOperand(1);
12255 SDValue RHS = Op.getOperand(2);
12256 unsigned TestOpc = IsTestPacked ? X86ISD::TESTP : X86ISD::PTEST;
12257 SDValue Test = DAG.getNode(TestOpc, dl, MVT::i32, LHS, RHS);
12258 SDValue CC = DAG.getConstant(X86CC, MVT::i8);
12259 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8, CC, Test);
12260 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
12262 case Intrinsic::x86_avx512_kortestz_w:
12263 case Intrinsic::x86_avx512_kortestc_w: {
12264 unsigned X86CC = (IntNo == Intrinsic::x86_avx512_kortestz_w)? X86::COND_E: X86::COND_B;
12265 SDValue LHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i1, Op.getOperand(1));
12266 SDValue RHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i1, Op.getOperand(2));
12267 SDValue CC = DAG.getConstant(X86CC, MVT::i8);
12268 SDValue Test = DAG.getNode(X86ISD::KORTEST, dl, MVT::i32, LHS, RHS);
12269 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i1, CC, Test);
12270 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
12273 // SSE/AVX shift intrinsics
12274 case Intrinsic::x86_sse2_psll_w:
12275 case Intrinsic::x86_sse2_psll_d:
12276 case Intrinsic::x86_sse2_psll_q:
12277 case Intrinsic::x86_avx2_psll_w:
12278 case Intrinsic::x86_avx2_psll_d:
12279 case Intrinsic::x86_avx2_psll_q:
12280 case Intrinsic::x86_sse2_psrl_w:
12281 case Intrinsic::x86_sse2_psrl_d:
12282 case Intrinsic::x86_sse2_psrl_q:
12283 case Intrinsic::x86_avx2_psrl_w:
12284 case Intrinsic::x86_avx2_psrl_d:
12285 case Intrinsic::x86_avx2_psrl_q:
12286 case Intrinsic::x86_sse2_psra_w:
12287 case Intrinsic::x86_sse2_psra_d:
12288 case Intrinsic::x86_avx2_psra_w:
12289 case Intrinsic::x86_avx2_psra_d: {
12292 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
12293 case Intrinsic::x86_sse2_psll_w:
12294 case Intrinsic::x86_sse2_psll_d:
12295 case Intrinsic::x86_sse2_psll_q:
12296 case Intrinsic::x86_avx2_psll_w:
12297 case Intrinsic::x86_avx2_psll_d:
12298 case Intrinsic::x86_avx2_psll_q:
12299 Opcode = X86ISD::VSHL;
12301 case Intrinsic::x86_sse2_psrl_w:
12302 case Intrinsic::x86_sse2_psrl_d:
12303 case Intrinsic::x86_sse2_psrl_q:
12304 case Intrinsic::x86_avx2_psrl_w:
12305 case Intrinsic::x86_avx2_psrl_d:
12306 case Intrinsic::x86_avx2_psrl_q:
12307 Opcode = X86ISD::VSRL;
12309 case Intrinsic::x86_sse2_psra_w:
12310 case Intrinsic::x86_sse2_psra_d:
12311 case Intrinsic::x86_avx2_psra_w:
12312 case Intrinsic::x86_avx2_psra_d:
12313 Opcode = X86ISD::VSRA;
12316 return DAG.getNode(Opcode, dl, Op.getValueType(),
12317 Op.getOperand(1), Op.getOperand(2));
12320 // SSE/AVX immediate shift intrinsics
12321 case Intrinsic::x86_sse2_pslli_w:
12322 case Intrinsic::x86_sse2_pslli_d:
12323 case Intrinsic::x86_sse2_pslli_q:
12324 case Intrinsic::x86_avx2_pslli_w:
12325 case Intrinsic::x86_avx2_pslli_d:
12326 case Intrinsic::x86_avx2_pslli_q:
12327 case Intrinsic::x86_sse2_psrli_w:
12328 case Intrinsic::x86_sse2_psrli_d:
12329 case Intrinsic::x86_sse2_psrli_q:
12330 case Intrinsic::x86_avx2_psrli_w:
12331 case Intrinsic::x86_avx2_psrli_d:
12332 case Intrinsic::x86_avx2_psrli_q:
12333 case Intrinsic::x86_sse2_psrai_w:
12334 case Intrinsic::x86_sse2_psrai_d:
12335 case Intrinsic::x86_avx2_psrai_w:
12336 case Intrinsic::x86_avx2_psrai_d: {
12339 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
12340 case Intrinsic::x86_sse2_pslli_w:
12341 case Intrinsic::x86_sse2_pslli_d:
12342 case Intrinsic::x86_sse2_pslli_q:
12343 case Intrinsic::x86_avx2_pslli_w:
12344 case Intrinsic::x86_avx2_pslli_d:
12345 case Intrinsic::x86_avx2_pslli_q:
12346 Opcode = X86ISD::VSHLI;
12348 case Intrinsic::x86_sse2_psrli_w:
12349 case Intrinsic::x86_sse2_psrli_d:
12350 case Intrinsic::x86_sse2_psrli_q:
12351 case Intrinsic::x86_avx2_psrli_w:
12352 case Intrinsic::x86_avx2_psrli_d:
12353 case Intrinsic::x86_avx2_psrli_q:
12354 Opcode = X86ISD::VSRLI;
12356 case Intrinsic::x86_sse2_psrai_w:
12357 case Intrinsic::x86_sse2_psrai_d:
12358 case Intrinsic::x86_avx2_psrai_w:
12359 case Intrinsic::x86_avx2_psrai_d:
12360 Opcode = X86ISD::VSRAI;
12363 return getTargetVShiftNode(Opcode, dl, Op.getSimpleValueType(),
12364 Op.getOperand(1), Op.getOperand(2), DAG);
12367 case Intrinsic::x86_sse42_pcmpistria128:
12368 case Intrinsic::x86_sse42_pcmpestria128:
12369 case Intrinsic::x86_sse42_pcmpistric128:
12370 case Intrinsic::x86_sse42_pcmpestric128:
12371 case Intrinsic::x86_sse42_pcmpistrio128:
12372 case Intrinsic::x86_sse42_pcmpestrio128:
12373 case Intrinsic::x86_sse42_pcmpistris128:
12374 case Intrinsic::x86_sse42_pcmpestris128:
12375 case Intrinsic::x86_sse42_pcmpistriz128:
12376 case Intrinsic::x86_sse42_pcmpestriz128: {
12380 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
12381 case Intrinsic::x86_sse42_pcmpistria128:
12382 Opcode = X86ISD::PCMPISTRI;
12383 X86CC = X86::COND_A;
12385 case Intrinsic::x86_sse42_pcmpestria128:
12386 Opcode = X86ISD::PCMPESTRI;
12387 X86CC = X86::COND_A;
12389 case Intrinsic::x86_sse42_pcmpistric128:
12390 Opcode = X86ISD::PCMPISTRI;
12391 X86CC = X86::COND_B;
12393 case Intrinsic::x86_sse42_pcmpestric128:
12394 Opcode = X86ISD::PCMPESTRI;
12395 X86CC = X86::COND_B;
12397 case Intrinsic::x86_sse42_pcmpistrio128:
12398 Opcode = X86ISD::PCMPISTRI;
12399 X86CC = X86::COND_O;
12401 case Intrinsic::x86_sse42_pcmpestrio128:
12402 Opcode = X86ISD::PCMPESTRI;
12403 X86CC = X86::COND_O;
12405 case Intrinsic::x86_sse42_pcmpistris128:
12406 Opcode = X86ISD::PCMPISTRI;
12407 X86CC = X86::COND_S;
12409 case Intrinsic::x86_sse42_pcmpestris128:
12410 Opcode = X86ISD::PCMPESTRI;
12411 X86CC = X86::COND_S;
12413 case Intrinsic::x86_sse42_pcmpistriz128:
12414 Opcode = X86ISD::PCMPISTRI;
12415 X86CC = X86::COND_E;
12417 case Intrinsic::x86_sse42_pcmpestriz128:
12418 Opcode = X86ISD::PCMPESTRI;
12419 X86CC = X86::COND_E;
12422 SmallVector<SDValue, 5> NewOps(Op->op_begin()+1, Op->op_end());
12423 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
12424 SDValue PCMP = DAG.getNode(Opcode, dl, VTs, NewOps);
12425 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
12426 DAG.getConstant(X86CC, MVT::i8),
12427 SDValue(PCMP.getNode(), 1));
12428 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
12431 case Intrinsic::x86_sse42_pcmpistri128:
12432 case Intrinsic::x86_sse42_pcmpestri128: {
12434 if (IntNo == Intrinsic::x86_sse42_pcmpistri128)
12435 Opcode = X86ISD::PCMPISTRI;
12437 Opcode = X86ISD::PCMPESTRI;
12439 SmallVector<SDValue, 5> NewOps(Op->op_begin()+1, Op->op_end());
12440 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
12441 return DAG.getNode(Opcode, dl, VTs, NewOps);
12443 case Intrinsic::x86_fma_vfmadd_ps:
12444 case Intrinsic::x86_fma_vfmadd_pd:
12445 case Intrinsic::x86_fma_vfmsub_ps:
12446 case Intrinsic::x86_fma_vfmsub_pd:
12447 case Intrinsic::x86_fma_vfnmadd_ps:
12448 case Intrinsic::x86_fma_vfnmadd_pd:
12449 case Intrinsic::x86_fma_vfnmsub_ps:
12450 case Intrinsic::x86_fma_vfnmsub_pd:
12451 case Intrinsic::x86_fma_vfmaddsub_ps:
12452 case Intrinsic::x86_fma_vfmaddsub_pd:
12453 case Intrinsic::x86_fma_vfmsubadd_ps:
12454 case Intrinsic::x86_fma_vfmsubadd_pd:
12455 case Intrinsic::x86_fma_vfmadd_ps_256:
12456 case Intrinsic::x86_fma_vfmadd_pd_256:
12457 case Intrinsic::x86_fma_vfmsub_ps_256:
12458 case Intrinsic::x86_fma_vfmsub_pd_256:
12459 case Intrinsic::x86_fma_vfnmadd_ps_256:
12460 case Intrinsic::x86_fma_vfnmadd_pd_256:
12461 case Intrinsic::x86_fma_vfnmsub_ps_256:
12462 case Intrinsic::x86_fma_vfnmsub_pd_256:
12463 case Intrinsic::x86_fma_vfmaddsub_ps_256:
12464 case Intrinsic::x86_fma_vfmaddsub_pd_256:
12465 case Intrinsic::x86_fma_vfmsubadd_ps_256:
12466 case Intrinsic::x86_fma_vfmsubadd_pd_256:
12467 case Intrinsic::x86_fma_vfmadd_ps_512:
12468 case Intrinsic::x86_fma_vfmadd_pd_512:
12469 case Intrinsic::x86_fma_vfmsub_ps_512:
12470 case Intrinsic::x86_fma_vfmsub_pd_512:
12471 case Intrinsic::x86_fma_vfnmadd_ps_512:
12472 case Intrinsic::x86_fma_vfnmadd_pd_512:
12473 case Intrinsic::x86_fma_vfnmsub_ps_512:
12474 case Intrinsic::x86_fma_vfnmsub_pd_512:
12475 case Intrinsic::x86_fma_vfmaddsub_ps_512:
12476 case Intrinsic::x86_fma_vfmaddsub_pd_512:
12477 case Intrinsic::x86_fma_vfmsubadd_ps_512:
12478 case Intrinsic::x86_fma_vfmsubadd_pd_512: {
12481 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
12482 case Intrinsic::x86_fma_vfmadd_ps:
12483 case Intrinsic::x86_fma_vfmadd_pd:
12484 case Intrinsic::x86_fma_vfmadd_ps_256:
12485 case Intrinsic::x86_fma_vfmadd_pd_256:
12486 case Intrinsic::x86_fma_vfmadd_ps_512:
12487 case Intrinsic::x86_fma_vfmadd_pd_512:
12488 Opc = X86ISD::FMADD;
12490 case Intrinsic::x86_fma_vfmsub_ps:
12491 case Intrinsic::x86_fma_vfmsub_pd:
12492 case Intrinsic::x86_fma_vfmsub_ps_256:
12493 case Intrinsic::x86_fma_vfmsub_pd_256:
12494 case Intrinsic::x86_fma_vfmsub_ps_512:
12495 case Intrinsic::x86_fma_vfmsub_pd_512:
12496 Opc = X86ISD::FMSUB;
12498 case Intrinsic::x86_fma_vfnmadd_ps:
12499 case Intrinsic::x86_fma_vfnmadd_pd:
12500 case Intrinsic::x86_fma_vfnmadd_ps_256:
12501 case Intrinsic::x86_fma_vfnmadd_pd_256:
12502 case Intrinsic::x86_fma_vfnmadd_ps_512:
12503 case Intrinsic::x86_fma_vfnmadd_pd_512:
12504 Opc = X86ISD::FNMADD;
12506 case Intrinsic::x86_fma_vfnmsub_ps:
12507 case Intrinsic::x86_fma_vfnmsub_pd:
12508 case Intrinsic::x86_fma_vfnmsub_ps_256:
12509 case Intrinsic::x86_fma_vfnmsub_pd_256:
12510 case Intrinsic::x86_fma_vfnmsub_ps_512:
12511 case Intrinsic::x86_fma_vfnmsub_pd_512:
12512 Opc = X86ISD::FNMSUB;
12514 case Intrinsic::x86_fma_vfmaddsub_ps:
12515 case Intrinsic::x86_fma_vfmaddsub_pd:
12516 case Intrinsic::x86_fma_vfmaddsub_ps_256:
12517 case Intrinsic::x86_fma_vfmaddsub_pd_256:
12518 case Intrinsic::x86_fma_vfmaddsub_ps_512:
12519 case Intrinsic::x86_fma_vfmaddsub_pd_512:
12520 Opc = X86ISD::FMADDSUB;
12522 case Intrinsic::x86_fma_vfmsubadd_ps:
12523 case Intrinsic::x86_fma_vfmsubadd_pd:
12524 case Intrinsic::x86_fma_vfmsubadd_ps_256:
12525 case Intrinsic::x86_fma_vfmsubadd_pd_256:
12526 case Intrinsic::x86_fma_vfmsubadd_ps_512:
12527 case Intrinsic::x86_fma_vfmsubadd_pd_512:
12528 Opc = X86ISD::FMSUBADD;
12532 return DAG.getNode(Opc, dl, Op.getValueType(), Op.getOperand(1),
12533 Op.getOperand(2), Op.getOperand(3));
12538 static SDValue getGatherNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
12539 SDValue Src, SDValue Mask, SDValue Base,
12540 SDValue Index, SDValue ScaleOp, SDValue Chain,
12541 const X86Subtarget * Subtarget) {
12543 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
12544 assert(C && "Invalid scale type");
12545 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), MVT::i8);
12546 EVT MaskVT = MVT::getVectorVT(MVT::i1,
12547 Index.getSimpleValueType().getVectorNumElements());
12549 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(Mask);
12551 MaskInReg = DAG.getTargetConstant(MaskC->getSExtValue(), MaskVT);
12553 MaskInReg = DAG.getNode(ISD::BITCAST, dl, MaskVT, Mask);
12554 SDVTList VTs = DAG.getVTList(Op.getValueType(), MaskVT, MVT::Other);
12555 SDValue Disp = DAG.getTargetConstant(0, MVT::i32);
12556 SDValue Segment = DAG.getRegister(0, MVT::i32);
12557 if (Src.getOpcode() == ISD::UNDEF)
12558 Src = getZeroVector(Op.getValueType(), Subtarget, DAG, dl);
12559 SDValue Ops[] = {Src, MaskInReg, Base, Scale, Index, Disp, Segment, Chain};
12560 SDNode *Res = DAG.getMachineNode(Opc, dl, VTs, Ops);
12561 SDValue RetOps[] = { SDValue(Res, 0), SDValue(Res, 2) };
12562 return DAG.getMergeValues(RetOps, dl);
12565 static SDValue getScatterNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
12566 SDValue Src, SDValue Mask, SDValue Base,
12567 SDValue Index, SDValue ScaleOp, SDValue Chain) {
12569 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
12570 assert(C && "Invalid scale type");
12571 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), MVT::i8);
12572 SDValue Disp = DAG.getTargetConstant(0, MVT::i32);
12573 SDValue Segment = DAG.getRegister(0, MVT::i32);
12574 EVT MaskVT = MVT::getVectorVT(MVT::i1,
12575 Index.getSimpleValueType().getVectorNumElements());
12577 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(Mask);
12579 MaskInReg = DAG.getTargetConstant(MaskC->getSExtValue(), MaskVT);
12581 MaskInReg = DAG.getNode(ISD::BITCAST, dl, MaskVT, Mask);
12582 SDVTList VTs = DAG.getVTList(MaskVT, MVT::Other);
12583 SDValue Ops[] = {Base, Scale, Index, Disp, Segment, MaskInReg, Src, Chain};
12584 SDNode *Res = DAG.getMachineNode(Opc, dl, VTs, Ops);
12585 return SDValue(Res, 1);
12588 static SDValue getPrefetchNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
12589 SDValue Mask, SDValue Base, SDValue Index,
12590 SDValue ScaleOp, SDValue Chain) {
12592 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
12593 assert(C && "Invalid scale type");
12594 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), MVT::i8);
12595 SDValue Disp = DAG.getTargetConstant(0, MVT::i32);
12596 SDValue Segment = DAG.getRegister(0, MVT::i32);
12598 MVT::getVectorVT(MVT::i1, Index.getSimpleValueType().getVectorNumElements());
12600 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(Mask);
12602 MaskInReg = DAG.getTargetConstant(MaskC->getSExtValue(), MaskVT);
12604 MaskInReg = DAG.getNode(ISD::BITCAST, dl, MaskVT, Mask);
12605 //SDVTList VTs = DAG.getVTList(MVT::Other);
12606 SDValue Ops[] = {MaskInReg, Base, Scale, Index, Disp, Segment, Chain};
12607 SDNode *Res = DAG.getMachineNode(Opc, dl, MVT::Other, Ops);
12608 return SDValue(Res, 0);
12611 // getReadTimeStampCounter - Handles the lowering of builtin intrinsics that
12612 // read the time stamp counter (x86_rdtsc and x86_rdtscp). This function is
12613 // also used to custom lower READCYCLECOUNTER nodes.
12614 static void getReadTimeStampCounter(SDNode *N, SDLoc DL, unsigned Opcode,
12615 SelectionDAG &DAG, const X86Subtarget *Subtarget,
12616 SmallVectorImpl<SDValue> &Results) {
12617 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
12618 SDValue rd = DAG.getNode(Opcode, DL, Tys, N->getOperand(0));
12621 // The processor's time-stamp counter (a 64-bit MSR) is stored into the
12622 // EDX:EAX registers. EDX is loaded with the high-order 32 bits of the MSR
12623 // and the EAX register is loaded with the low-order 32 bits.
12624 if (Subtarget->is64Bit()) {
12625 LO = DAG.getCopyFromReg(rd, DL, X86::RAX, MVT::i64, rd.getValue(1));
12626 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::RDX, MVT::i64,
12629 LO = DAG.getCopyFromReg(rd, DL, X86::EAX, MVT::i32, rd.getValue(1));
12630 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::EDX, MVT::i32,
12633 SDValue Chain = HI.getValue(1);
12635 if (Opcode == X86ISD::RDTSCP_DAG) {
12636 assert(N->getNumOperands() == 3 && "Unexpected number of operands!");
12638 // Instruction RDTSCP loads the IA32:TSC_AUX_MSR (address C000_0103H) into
12639 // the ECX register. Add 'ecx' explicitly to the chain.
12640 SDValue ecx = DAG.getCopyFromReg(Chain, DL, X86::ECX, MVT::i32,
12642 // Explicitly store the content of ECX at the location passed in input
12643 // to the 'rdtscp' intrinsic.
12644 Chain = DAG.getStore(ecx.getValue(1), DL, ecx, N->getOperand(2),
12645 MachinePointerInfo(), false, false, 0);
12648 if (Subtarget->is64Bit()) {
12649 // The EDX register is loaded with the high-order 32 bits of the MSR, and
12650 // the EAX register is loaded with the low-order 32 bits.
12651 SDValue Tmp = DAG.getNode(ISD::SHL, DL, MVT::i64, HI,
12652 DAG.getConstant(32, MVT::i8));
12653 Results.push_back(DAG.getNode(ISD::OR, DL, MVT::i64, LO, Tmp));
12654 Results.push_back(Chain);
12658 // Use a buildpair to merge the two 32-bit values into a 64-bit one.
12659 SDValue Ops[] = { LO, HI };
12660 SDValue Pair = DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops);
12661 Results.push_back(Pair);
12662 Results.push_back(Chain);
12665 static SDValue LowerREADCYCLECOUNTER(SDValue Op, const X86Subtarget *Subtarget,
12666 SelectionDAG &DAG) {
12667 SmallVector<SDValue, 2> Results;
12669 getReadTimeStampCounter(Op.getNode(), DL, X86ISD::RDTSC_DAG, DAG, Subtarget,
12671 return DAG.getMergeValues(Results, DL);
12674 enum IntrinsicType {
12675 GATHER, SCATTER, PREFETCH, RDSEED, RDRAND, RDTSC, XTEST
12678 struct IntrinsicData {
12679 IntrinsicData(IntrinsicType IType, unsigned IOpc0, unsigned IOpc1)
12680 :Type(IType), Opc0(IOpc0), Opc1(IOpc1) {}
12681 IntrinsicType Type;
12686 std::map < unsigned, IntrinsicData> IntrMap;
12687 static void InitIntinsicsMap() {
12688 static bool Initialized = false;
12691 IntrMap.insert(std::make_pair(Intrinsic::x86_avx512_gather_qps_512,
12692 IntrinsicData(GATHER, X86::VGATHERQPSZrm, 0)));
12693 IntrMap.insert(std::make_pair(Intrinsic::x86_avx512_gather_qps_512,
12694 IntrinsicData(GATHER, X86::VGATHERQPSZrm, 0)));
12695 IntrMap.insert(std::make_pair(Intrinsic::x86_avx512_gather_qpd_512,
12696 IntrinsicData(GATHER, X86::VGATHERQPDZrm, 0)));
12697 IntrMap.insert(std::make_pair(Intrinsic::x86_avx512_gather_dpd_512,
12698 IntrinsicData(GATHER, X86::VGATHERDPDZrm, 0)));
12699 IntrMap.insert(std::make_pair(Intrinsic::x86_avx512_gather_dps_512,
12700 IntrinsicData(GATHER, X86::VGATHERDPSZrm, 0)));
12701 IntrMap.insert(std::make_pair(Intrinsic::x86_avx512_gather_qpi_512,
12702 IntrinsicData(GATHER, X86::VPGATHERQDZrm, 0)));
12703 IntrMap.insert(std::make_pair(Intrinsic::x86_avx512_gather_qpq_512,
12704 IntrinsicData(GATHER, X86::VPGATHERQQZrm, 0)));
12705 IntrMap.insert(std::make_pair(Intrinsic::x86_avx512_gather_dpi_512,
12706 IntrinsicData(GATHER, X86::VPGATHERDDZrm, 0)));
12707 IntrMap.insert(std::make_pair(Intrinsic::x86_avx512_gather_dpq_512,
12708 IntrinsicData(GATHER, X86::VPGATHERDQZrm, 0)));
12710 IntrMap.insert(std::make_pair(Intrinsic::x86_avx512_scatter_qps_512,
12711 IntrinsicData(SCATTER, X86::VSCATTERQPSZmr, 0)));
12712 IntrMap.insert(std::make_pair(Intrinsic::x86_avx512_scatter_qpd_512,
12713 IntrinsicData(SCATTER, X86::VSCATTERQPDZmr, 0)));
12714 IntrMap.insert(std::make_pair(Intrinsic::x86_avx512_scatter_dpd_512,
12715 IntrinsicData(SCATTER, X86::VSCATTERDPDZmr, 0)));
12716 IntrMap.insert(std::make_pair(Intrinsic::x86_avx512_scatter_dps_512,
12717 IntrinsicData(SCATTER, X86::VSCATTERDPSZmr, 0)));
12718 IntrMap.insert(std::make_pair(Intrinsic::x86_avx512_scatter_qpi_512,
12719 IntrinsicData(SCATTER, X86::VPSCATTERQDZmr, 0)));
12720 IntrMap.insert(std::make_pair(Intrinsic::x86_avx512_scatter_qpq_512,
12721 IntrinsicData(SCATTER, X86::VPSCATTERQQZmr, 0)));
12722 IntrMap.insert(std::make_pair(Intrinsic::x86_avx512_scatter_dpi_512,
12723 IntrinsicData(SCATTER, X86::VPSCATTERDDZmr, 0)));
12724 IntrMap.insert(std::make_pair(Intrinsic::x86_avx512_scatter_dpq_512,
12725 IntrinsicData(SCATTER, X86::VPSCATTERDQZmr, 0)));
12727 IntrMap.insert(std::make_pair(Intrinsic::x86_avx512_gatherpf_qps_512,
12728 IntrinsicData(PREFETCH, X86::VGATHERPF0QPSm,
12729 X86::VGATHERPF1QPSm)));
12730 IntrMap.insert(std::make_pair(Intrinsic::x86_avx512_gatherpf_qpd_512,
12731 IntrinsicData(PREFETCH, X86::VGATHERPF0QPDm,
12732 X86::VGATHERPF1QPDm)));
12733 IntrMap.insert(std::make_pair(Intrinsic::x86_avx512_gatherpf_dpd_512,
12734 IntrinsicData(PREFETCH, X86::VGATHERPF0DPDm,
12735 X86::VGATHERPF1DPDm)));
12736 IntrMap.insert(std::make_pair(Intrinsic::x86_avx512_gatherpf_dps_512,
12737 IntrinsicData(PREFETCH, X86::VGATHERPF0DPSm,
12738 X86::VGATHERPF1DPSm)));
12739 IntrMap.insert(std::make_pair(Intrinsic::x86_avx512_scatterpf_qps_512,
12740 IntrinsicData(PREFETCH, X86::VSCATTERPF0QPSm,
12741 X86::VSCATTERPF1QPSm)));
12742 IntrMap.insert(std::make_pair(Intrinsic::x86_avx512_scatterpf_qpd_512,
12743 IntrinsicData(PREFETCH, X86::VSCATTERPF0QPDm,
12744 X86::VSCATTERPF1QPDm)));
12745 IntrMap.insert(std::make_pair(Intrinsic::x86_avx512_scatterpf_dpd_512,
12746 IntrinsicData(PREFETCH, X86::VSCATTERPF0DPDm,
12747 X86::VSCATTERPF1DPDm)));
12748 IntrMap.insert(std::make_pair(Intrinsic::x86_avx512_scatterpf_dps_512,
12749 IntrinsicData(PREFETCH, X86::VSCATTERPF0DPSm,
12750 X86::VSCATTERPF1DPSm)));
12751 IntrMap.insert(std::make_pair(Intrinsic::x86_rdrand_16,
12752 IntrinsicData(RDRAND, X86ISD::RDRAND, 0)));
12753 IntrMap.insert(std::make_pair(Intrinsic::x86_rdrand_32,
12754 IntrinsicData(RDRAND, X86ISD::RDRAND, 0)));
12755 IntrMap.insert(std::make_pair(Intrinsic::x86_rdrand_64,
12756 IntrinsicData(RDRAND, X86ISD::RDRAND, 0)));
12757 IntrMap.insert(std::make_pair(Intrinsic::x86_rdseed_16,
12758 IntrinsicData(RDSEED, X86ISD::RDSEED, 0)));
12759 IntrMap.insert(std::make_pair(Intrinsic::x86_rdseed_32,
12760 IntrinsicData(RDSEED, X86ISD::RDSEED, 0)));
12761 IntrMap.insert(std::make_pair(Intrinsic::x86_rdseed_64,
12762 IntrinsicData(RDSEED, X86ISD::RDSEED, 0)));
12763 IntrMap.insert(std::make_pair(Intrinsic::x86_xtest,
12764 IntrinsicData(XTEST, X86ISD::XTEST, 0)));
12765 IntrMap.insert(std::make_pair(Intrinsic::x86_rdtsc,
12766 IntrinsicData(RDTSC, X86ISD::RDTSC_DAG, 0)));
12767 IntrMap.insert(std::make_pair(Intrinsic::x86_rdtscp,
12768 IntrinsicData(RDTSC, X86ISD::RDTSCP_DAG, 0)));
12769 Initialized = true;
12772 static SDValue LowerINTRINSIC_W_CHAIN(SDValue Op, const X86Subtarget *Subtarget,
12773 SelectionDAG &DAG) {
12774 InitIntinsicsMap();
12775 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
12776 std::map < unsigned, IntrinsicData>::const_iterator itr = IntrMap.find(IntNo);
12777 if (itr == IntrMap.end())
12781 IntrinsicData Intr = itr->second;
12782 switch(Intr.Type) {
12785 // Emit the node with the right value type.
12786 SDVTList VTs = DAG.getVTList(Op->getValueType(0), MVT::Glue, MVT::Other);
12787 SDValue Result = DAG.getNode(Intr.Opc0, dl, VTs, Op.getOperand(0));
12789 // If the value returned by RDRAND/RDSEED was valid (CF=1), return 1.
12790 // Otherwise return the value from Rand, which is always 0, casted to i32.
12791 SDValue Ops[] = { DAG.getZExtOrTrunc(Result, dl, Op->getValueType(1)),
12792 DAG.getConstant(1, Op->getValueType(1)),
12793 DAG.getConstant(X86::COND_B, MVT::i32),
12794 SDValue(Result.getNode(), 1) };
12795 SDValue isValid = DAG.getNode(X86ISD::CMOV, dl,
12796 DAG.getVTList(Op->getValueType(1), MVT::Glue),
12799 // Return { result, isValid, chain }.
12800 return DAG.getNode(ISD::MERGE_VALUES, dl, Op->getVTList(), Result, isValid,
12801 SDValue(Result.getNode(), 2));
12804 //gather(v1, mask, index, base, scale);
12805 SDValue Chain = Op.getOperand(0);
12806 SDValue Src = Op.getOperand(2);
12807 SDValue Base = Op.getOperand(3);
12808 SDValue Index = Op.getOperand(4);
12809 SDValue Mask = Op.getOperand(5);
12810 SDValue Scale = Op.getOperand(6);
12811 return getGatherNode(Intr.Opc0, Op, DAG, Src, Mask, Base, Index, Scale, Chain,
12815 //scatter(base, mask, index, v1, scale);
12816 SDValue Chain = Op.getOperand(0);
12817 SDValue Base = Op.getOperand(2);
12818 SDValue Mask = Op.getOperand(3);
12819 SDValue Index = Op.getOperand(4);
12820 SDValue Src = Op.getOperand(5);
12821 SDValue Scale = Op.getOperand(6);
12822 return getScatterNode(Intr.Opc0, Op, DAG, Src, Mask, Base, Index, Scale, Chain);
12825 SDValue Hint = Op.getOperand(6);
12827 if (dyn_cast<ConstantSDNode> (Hint) == 0 ||
12828 (HintVal = dyn_cast<ConstantSDNode> (Hint)->getZExtValue()) > 1)
12829 llvm_unreachable("Wrong prefetch hint in intrinsic: should be 0 or 1");
12830 unsigned Opcode = (HintVal ? Intr.Opc1 : Intr.Opc0);
12831 SDValue Chain = Op.getOperand(0);
12832 SDValue Mask = Op.getOperand(2);
12833 SDValue Index = Op.getOperand(3);
12834 SDValue Base = Op.getOperand(4);
12835 SDValue Scale = Op.getOperand(5);
12836 return getPrefetchNode(Opcode, Op, DAG, Mask, Base, Index, Scale, Chain);
12838 // Read Time Stamp Counter (RDTSC) and Processor ID (RDTSCP).
12840 SmallVector<SDValue, 2> Results;
12841 getReadTimeStampCounter(Op.getNode(), dl, Intr.Opc0, DAG, Subtarget, Results);
12842 return DAG.getMergeValues(Results, dl);
12844 // XTEST intrinsics.
12846 SDVTList VTs = DAG.getVTList(Op->getValueType(0), MVT::Other);
12847 SDValue InTrans = DAG.getNode(X86ISD::XTEST, dl, VTs, Op.getOperand(0));
12848 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
12849 DAG.getConstant(X86::COND_NE, MVT::i8),
12851 SDValue Ret = DAG.getNode(ISD::ZERO_EXTEND, dl, Op->getValueType(0), SetCC);
12852 return DAG.getNode(ISD::MERGE_VALUES, dl, Op->getVTList(),
12853 Ret, SDValue(InTrans.getNode(), 1));
12856 llvm_unreachable("Unknown Intrinsic Type");
12859 SDValue X86TargetLowering::LowerRETURNADDR(SDValue Op,
12860 SelectionDAG &DAG) const {
12861 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
12862 MFI->setReturnAddressIsTaken(true);
12864 if (verifyReturnAddressArgumentIsConstant(Op, DAG))
12867 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
12869 EVT PtrVT = getPointerTy();
12872 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
12873 const X86RegisterInfo *RegInfo =
12874 static_cast<const X86RegisterInfo*>(getTargetMachine().getRegisterInfo());
12875 SDValue Offset = DAG.getConstant(RegInfo->getSlotSize(), PtrVT);
12876 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
12877 DAG.getNode(ISD::ADD, dl, PtrVT,
12878 FrameAddr, Offset),
12879 MachinePointerInfo(), false, false, false, 0);
12882 // Just load the return address.
12883 SDValue RetAddrFI = getReturnAddressFrameIndex(DAG);
12884 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
12885 RetAddrFI, MachinePointerInfo(), false, false, false, 0);
12888 SDValue X86TargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {
12889 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
12890 MFI->setFrameAddressIsTaken(true);
12892 EVT VT = Op.getValueType();
12893 SDLoc dl(Op); // FIXME probably not meaningful
12894 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
12895 const X86RegisterInfo *RegInfo =
12896 static_cast<const X86RegisterInfo*>(getTargetMachine().getRegisterInfo());
12897 unsigned FrameReg = RegInfo->getFrameRegister(DAG.getMachineFunction());
12898 assert(((FrameReg == X86::RBP && VT == MVT::i64) ||
12899 (FrameReg == X86::EBP && VT == MVT::i32)) &&
12900 "Invalid Frame Register!");
12901 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT);
12903 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr,
12904 MachinePointerInfo(),
12905 false, false, false, 0);
12909 // FIXME? Maybe this could be a TableGen attribute on some registers and
12910 // this table could be generated automatically from RegInfo.
12911 unsigned X86TargetLowering::getRegisterByName(const char* RegName,
12913 unsigned Reg = StringSwitch<unsigned>(RegName)
12914 .Case("esp", X86::ESP)
12915 .Case("rsp", X86::RSP)
12919 report_fatal_error("Invalid register name global variable");
12922 SDValue X86TargetLowering::LowerFRAME_TO_ARGS_OFFSET(SDValue Op,
12923 SelectionDAG &DAG) const {
12924 const X86RegisterInfo *RegInfo =
12925 static_cast<const X86RegisterInfo*>(getTargetMachine().getRegisterInfo());
12926 return DAG.getIntPtrConstant(2 * RegInfo->getSlotSize());
12929 SDValue X86TargetLowering::LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const {
12930 SDValue Chain = Op.getOperand(0);
12931 SDValue Offset = Op.getOperand(1);
12932 SDValue Handler = Op.getOperand(2);
12935 EVT PtrVT = getPointerTy();
12936 const X86RegisterInfo *RegInfo =
12937 static_cast<const X86RegisterInfo*>(getTargetMachine().getRegisterInfo());
12938 unsigned FrameReg = RegInfo->getFrameRegister(DAG.getMachineFunction());
12939 assert(((FrameReg == X86::RBP && PtrVT == MVT::i64) ||
12940 (FrameReg == X86::EBP && PtrVT == MVT::i32)) &&
12941 "Invalid Frame Register!");
12942 SDValue Frame = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, PtrVT);
12943 unsigned StoreAddrReg = (PtrVT == MVT::i64) ? X86::RCX : X86::ECX;
12945 SDValue StoreAddr = DAG.getNode(ISD::ADD, dl, PtrVT, Frame,
12946 DAG.getIntPtrConstant(RegInfo->getSlotSize()));
12947 StoreAddr = DAG.getNode(ISD::ADD, dl, PtrVT, StoreAddr, Offset);
12948 Chain = DAG.getStore(Chain, dl, Handler, StoreAddr, MachinePointerInfo(),
12950 Chain = DAG.getCopyToReg(Chain, dl, StoreAddrReg, StoreAddr);
12952 return DAG.getNode(X86ISD::EH_RETURN, dl, MVT::Other, Chain,
12953 DAG.getRegister(StoreAddrReg, PtrVT));
12956 SDValue X86TargetLowering::lowerEH_SJLJ_SETJMP(SDValue Op,
12957 SelectionDAG &DAG) const {
12959 return DAG.getNode(X86ISD::EH_SJLJ_SETJMP, DL,
12960 DAG.getVTList(MVT::i32, MVT::Other),
12961 Op.getOperand(0), Op.getOperand(1));
12964 SDValue X86TargetLowering::lowerEH_SJLJ_LONGJMP(SDValue Op,
12965 SelectionDAG &DAG) const {
12967 return DAG.getNode(X86ISD::EH_SJLJ_LONGJMP, DL, MVT::Other,
12968 Op.getOperand(0), Op.getOperand(1));
12971 static SDValue LowerADJUST_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) {
12972 return Op.getOperand(0);
12975 SDValue X86TargetLowering::LowerINIT_TRAMPOLINE(SDValue Op,
12976 SelectionDAG &DAG) const {
12977 SDValue Root = Op.getOperand(0);
12978 SDValue Trmp = Op.getOperand(1); // trampoline
12979 SDValue FPtr = Op.getOperand(2); // nested function
12980 SDValue Nest = Op.getOperand(3); // 'nest' parameter value
12983 const Value *TrmpAddr = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
12984 const TargetRegisterInfo* TRI = getTargetMachine().getRegisterInfo();
12986 if (Subtarget->is64Bit()) {
12987 SDValue OutChains[6];
12989 // Large code-model.
12990 const unsigned char JMP64r = 0xFF; // 64-bit jmp through register opcode.
12991 const unsigned char MOV64ri = 0xB8; // X86::MOV64ri opcode.
12993 const unsigned char N86R10 = TRI->getEncodingValue(X86::R10) & 0x7;
12994 const unsigned char N86R11 = TRI->getEncodingValue(X86::R11) & 0x7;
12996 const unsigned char REX_WB = 0x40 | 0x08 | 0x01; // REX prefix
12998 // Load the pointer to the nested function into R11.
12999 unsigned OpCode = ((MOV64ri | N86R11) << 8) | REX_WB; // movabsq r11
13000 SDValue Addr = Trmp;
13001 OutChains[0] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
13002 Addr, MachinePointerInfo(TrmpAddr),
13005 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
13006 DAG.getConstant(2, MVT::i64));
13007 OutChains[1] = DAG.getStore(Root, dl, FPtr, Addr,
13008 MachinePointerInfo(TrmpAddr, 2),
13011 // Load the 'nest' parameter value into R10.
13012 // R10 is specified in X86CallingConv.td
13013 OpCode = ((MOV64ri | N86R10) << 8) | REX_WB; // movabsq r10
13014 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
13015 DAG.getConstant(10, MVT::i64));
13016 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
13017 Addr, MachinePointerInfo(TrmpAddr, 10),
13020 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
13021 DAG.getConstant(12, MVT::i64));
13022 OutChains[3] = DAG.getStore(Root, dl, Nest, Addr,
13023 MachinePointerInfo(TrmpAddr, 12),
13026 // Jump to the nested function.
13027 OpCode = (JMP64r << 8) | REX_WB; // jmpq *...
13028 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
13029 DAG.getConstant(20, MVT::i64));
13030 OutChains[4] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
13031 Addr, MachinePointerInfo(TrmpAddr, 20),
13034 unsigned char ModRM = N86R11 | (4 << 3) | (3 << 6); // ...r11
13035 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
13036 DAG.getConstant(22, MVT::i64));
13037 OutChains[5] = DAG.getStore(Root, dl, DAG.getConstant(ModRM, MVT::i8), Addr,
13038 MachinePointerInfo(TrmpAddr, 22),
13041 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains);
13043 const Function *Func =
13044 cast<Function>(cast<SrcValueSDNode>(Op.getOperand(5))->getValue());
13045 CallingConv::ID CC = Func->getCallingConv();
13050 llvm_unreachable("Unsupported calling convention");
13051 case CallingConv::C:
13052 case CallingConv::X86_StdCall: {
13053 // Pass 'nest' parameter in ECX.
13054 // Must be kept in sync with X86CallingConv.td
13055 NestReg = X86::ECX;
13057 // Check that ECX wasn't needed by an 'inreg' parameter.
13058 FunctionType *FTy = Func->getFunctionType();
13059 const AttributeSet &Attrs = Func->getAttributes();
13061 if (!Attrs.isEmpty() && !Func->isVarArg()) {
13062 unsigned InRegCount = 0;
13065 for (FunctionType::param_iterator I = FTy->param_begin(),
13066 E = FTy->param_end(); I != E; ++I, ++Idx)
13067 if (Attrs.hasAttribute(Idx, Attribute::InReg))
13068 // FIXME: should only count parameters that are lowered to integers.
13069 InRegCount += (TD->getTypeSizeInBits(*I) + 31) / 32;
13071 if (InRegCount > 2) {
13072 report_fatal_error("Nest register in use - reduce number of inreg"
13078 case CallingConv::X86_FastCall:
13079 case CallingConv::X86_ThisCall:
13080 case CallingConv::Fast:
13081 // Pass 'nest' parameter in EAX.
13082 // Must be kept in sync with X86CallingConv.td
13083 NestReg = X86::EAX;
13087 SDValue OutChains[4];
13088 SDValue Addr, Disp;
13090 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
13091 DAG.getConstant(10, MVT::i32));
13092 Disp = DAG.getNode(ISD::SUB, dl, MVT::i32, FPtr, Addr);
13094 // This is storing the opcode for MOV32ri.
13095 const unsigned char MOV32ri = 0xB8; // X86::MOV32ri's opcode byte.
13096 const unsigned char N86Reg = TRI->getEncodingValue(NestReg) & 0x7;
13097 OutChains[0] = DAG.getStore(Root, dl,
13098 DAG.getConstant(MOV32ri|N86Reg, MVT::i8),
13099 Trmp, MachinePointerInfo(TrmpAddr),
13102 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
13103 DAG.getConstant(1, MVT::i32));
13104 OutChains[1] = DAG.getStore(Root, dl, Nest, Addr,
13105 MachinePointerInfo(TrmpAddr, 1),
13108 const unsigned char JMP = 0xE9; // jmp <32bit dst> opcode.
13109 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
13110 DAG.getConstant(5, MVT::i32));
13111 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(JMP, MVT::i8), Addr,
13112 MachinePointerInfo(TrmpAddr, 5),
13115 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
13116 DAG.getConstant(6, MVT::i32));
13117 OutChains[3] = DAG.getStore(Root, dl, Disp, Addr,
13118 MachinePointerInfo(TrmpAddr, 6),
13121 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains);
13125 SDValue X86TargetLowering::LowerFLT_ROUNDS_(SDValue Op,
13126 SelectionDAG &DAG) const {
13128 The rounding mode is in bits 11:10 of FPSR, and has the following
13130 00 Round to nearest
13135 FLT_ROUNDS, on the other hand, expects the following:
13142 To perform the conversion, we do:
13143 (((((FPSR & 0x800) >> 11) | ((FPSR & 0x400) >> 9)) + 1) & 3)
13146 MachineFunction &MF = DAG.getMachineFunction();
13147 const TargetMachine &TM = MF.getTarget();
13148 const TargetFrameLowering &TFI = *TM.getFrameLowering();
13149 unsigned StackAlignment = TFI.getStackAlignment();
13150 MVT VT = Op.getSimpleValueType();
13153 // Save FP Control Word to stack slot
13154 int SSFI = MF.getFrameInfo()->CreateStackObject(2, StackAlignment, false);
13155 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
13157 MachineMemOperand *MMO =
13158 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
13159 MachineMemOperand::MOStore, 2, 2);
13161 SDValue Ops[] = { DAG.getEntryNode(), StackSlot };
13162 SDValue Chain = DAG.getMemIntrinsicNode(X86ISD::FNSTCW16m, DL,
13163 DAG.getVTList(MVT::Other),
13164 Ops, MVT::i16, MMO);
13166 // Load FP Control Word from stack slot
13167 SDValue CWD = DAG.getLoad(MVT::i16, DL, Chain, StackSlot,
13168 MachinePointerInfo(), false, false, false, 0);
13170 // Transform as necessary
13172 DAG.getNode(ISD::SRL, DL, MVT::i16,
13173 DAG.getNode(ISD::AND, DL, MVT::i16,
13174 CWD, DAG.getConstant(0x800, MVT::i16)),
13175 DAG.getConstant(11, MVT::i8));
13177 DAG.getNode(ISD::SRL, DL, MVT::i16,
13178 DAG.getNode(ISD::AND, DL, MVT::i16,
13179 CWD, DAG.getConstant(0x400, MVT::i16)),
13180 DAG.getConstant(9, MVT::i8));
13183 DAG.getNode(ISD::AND, DL, MVT::i16,
13184 DAG.getNode(ISD::ADD, DL, MVT::i16,
13185 DAG.getNode(ISD::OR, DL, MVT::i16, CWD1, CWD2),
13186 DAG.getConstant(1, MVT::i16)),
13187 DAG.getConstant(3, MVT::i16));
13189 return DAG.getNode((VT.getSizeInBits() < 16 ?
13190 ISD::TRUNCATE : ISD::ZERO_EXTEND), DL, VT, RetVal);
13193 static SDValue LowerCTLZ(SDValue Op, SelectionDAG &DAG) {
13194 MVT VT = Op.getSimpleValueType();
13196 unsigned NumBits = VT.getSizeInBits();
13199 Op = Op.getOperand(0);
13200 if (VT == MVT::i8) {
13201 // Zero extend to i32 since there is not an i8 bsr.
13203 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
13206 // Issue a bsr (scan bits in reverse) which also sets EFLAGS.
13207 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
13208 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
13210 // If src is zero (i.e. bsr sets ZF), returns NumBits.
13213 DAG.getConstant(NumBits+NumBits-1, OpVT),
13214 DAG.getConstant(X86::COND_E, MVT::i8),
13217 Op = DAG.getNode(X86ISD::CMOV, dl, OpVT, Ops);
13219 // Finally xor with NumBits-1.
13220 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT));
13223 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
13227 static SDValue LowerCTLZ_ZERO_UNDEF(SDValue Op, SelectionDAG &DAG) {
13228 MVT VT = Op.getSimpleValueType();
13230 unsigned NumBits = VT.getSizeInBits();
13233 Op = Op.getOperand(0);
13234 if (VT == MVT::i8) {
13235 // Zero extend to i32 since there is not an i8 bsr.
13237 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
13240 // Issue a bsr (scan bits in reverse).
13241 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
13242 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
13244 // And xor with NumBits-1.
13245 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT));
13248 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
13252 static SDValue LowerCTTZ(SDValue Op, SelectionDAG &DAG) {
13253 MVT VT = Op.getSimpleValueType();
13254 unsigned NumBits = VT.getSizeInBits();
13256 Op = Op.getOperand(0);
13258 // Issue a bsf (scan bits forward) which also sets EFLAGS.
13259 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
13260 Op = DAG.getNode(X86ISD::BSF, dl, VTs, Op);
13262 // If src is zero (i.e. bsf sets ZF), returns NumBits.
13265 DAG.getConstant(NumBits, VT),
13266 DAG.getConstant(X86::COND_E, MVT::i8),
13269 return DAG.getNode(X86ISD::CMOV, dl, VT, Ops);
13272 // Lower256IntArith - Break a 256-bit integer operation into two new 128-bit
13273 // ones, and then concatenate the result back.
13274 static SDValue Lower256IntArith(SDValue Op, SelectionDAG &DAG) {
13275 MVT VT = Op.getSimpleValueType();
13277 assert(VT.is256BitVector() && VT.isInteger() &&
13278 "Unsupported value type for operation");
13280 unsigned NumElems = VT.getVectorNumElements();
13283 // Extract the LHS vectors
13284 SDValue LHS = Op.getOperand(0);
13285 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
13286 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
13288 // Extract the RHS vectors
13289 SDValue RHS = Op.getOperand(1);
13290 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, dl);
13291 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, dl);
13293 MVT EltVT = VT.getVectorElementType();
13294 MVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
13296 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
13297 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1),
13298 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2));
13301 static SDValue LowerADD(SDValue Op, SelectionDAG &DAG) {
13302 assert(Op.getSimpleValueType().is256BitVector() &&
13303 Op.getSimpleValueType().isInteger() &&
13304 "Only handle AVX 256-bit vector integer operation");
13305 return Lower256IntArith(Op, DAG);
13308 static SDValue LowerSUB(SDValue Op, SelectionDAG &DAG) {
13309 assert(Op.getSimpleValueType().is256BitVector() &&
13310 Op.getSimpleValueType().isInteger() &&
13311 "Only handle AVX 256-bit vector integer operation");
13312 return Lower256IntArith(Op, DAG);
13315 static SDValue LowerMUL(SDValue Op, const X86Subtarget *Subtarget,
13316 SelectionDAG &DAG) {
13318 MVT VT = Op.getSimpleValueType();
13320 // Decompose 256-bit ops into smaller 128-bit ops.
13321 if (VT.is256BitVector() && !Subtarget->hasInt256())
13322 return Lower256IntArith(Op, DAG);
13324 SDValue A = Op.getOperand(0);
13325 SDValue B = Op.getOperand(1);
13327 // Lower v4i32 mul as 2x shuffle, 2x pmuludq, 2x shuffle.
13328 if (VT == MVT::v4i32) {
13329 assert(Subtarget->hasSSE2() && !Subtarget->hasSSE41() &&
13330 "Should not custom lower when pmuldq is available!");
13332 // Extract the odd parts.
13333 static const int UnpackMask[] = { 1, -1, 3, -1 };
13334 SDValue Aodds = DAG.getVectorShuffle(VT, dl, A, A, UnpackMask);
13335 SDValue Bodds = DAG.getVectorShuffle(VT, dl, B, B, UnpackMask);
13337 // Multiply the even parts.
13338 SDValue Evens = DAG.getNode(X86ISD::PMULUDQ, dl, MVT::v2i64, A, B);
13339 // Now multiply odd parts.
13340 SDValue Odds = DAG.getNode(X86ISD::PMULUDQ, dl, MVT::v2i64, Aodds, Bodds);
13342 Evens = DAG.getNode(ISD::BITCAST, dl, VT, Evens);
13343 Odds = DAG.getNode(ISD::BITCAST, dl, VT, Odds);
13345 // Merge the two vectors back together with a shuffle. This expands into 2
13347 static const int ShufMask[] = { 0, 4, 2, 6 };
13348 return DAG.getVectorShuffle(VT, dl, Evens, Odds, ShufMask);
13351 assert((VT == MVT::v2i64 || VT == MVT::v4i64 || VT == MVT::v8i64) &&
13352 "Only know how to lower V2I64/V4I64/V8I64 multiply");
13354 // Ahi = psrlqi(a, 32);
13355 // Bhi = psrlqi(b, 32);
13357 // AloBlo = pmuludq(a, b);
13358 // AloBhi = pmuludq(a, Bhi);
13359 // AhiBlo = pmuludq(Ahi, b);
13361 // AloBhi = psllqi(AloBhi, 32);
13362 // AhiBlo = psllqi(AhiBlo, 32);
13363 // return AloBlo + AloBhi + AhiBlo;
13365 SDValue Ahi = getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, A, 32, DAG);
13366 SDValue Bhi = getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, B, 32, DAG);
13368 // Bit cast to 32-bit vectors for MULUDQ
13369 EVT MulVT = (VT == MVT::v2i64) ? MVT::v4i32 :
13370 (VT == MVT::v4i64) ? MVT::v8i32 : MVT::v16i32;
13371 A = DAG.getNode(ISD::BITCAST, dl, MulVT, A);
13372 B = DAG.getNode(ISD::BITCAST, dl, MulVT, B);
13373 Ahi = DAG.getNode(ISD::BITCAST, dl, MulVT, Ahi);
13374 Bhi = DAG.getNode(ISD::BITCAST, dl, MulVT, Bhi);
13376 SDValue AloBlo = DAG.getNode(X86ISD::PMULUDQ, dl, VT, A, B);
13377 SDValue AloBhi = DAG.getNode(X86ISD::PMULUDQ, dl, VT, A, Bhi);
13378 SDValue AhiBlo = DAG.getNode(X86ISD::PMULUDQ, dl, VT, Ahi, B);
13380 AloBhi = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, AloBhi, 32, DAG);
13381 AhiBlo = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, AhiBlo, 32, DAG);
13383 SDValue Res = DAG.getNode(ISD::ADD, dl, VT, AloBlo, AloBhi);
13384 return DAG.getNode(ISD::ADD, dl, VT, Res, AhiBlo);
13387 SDValue X86TargetLowering::LowerWin64_i128OP(SDValue Op, SelectionDAG &DAG) const {
13388 assert(Subtarget->isTargetWin64() && "Unexpected target");
13389 EVT VT = Op.getValueType();
13390 assert(VT.isInteger() && VT.getSizeInBits() == 128 &&
13391 "Unexpected return type for lowering");
13395 switch (Op->getOpcode()) {
13396 default: llvm_unreachable("Unexpected request for libcall!");
13397 case ISD::SDIV: isSigned = true; LC = RTLIB::SDIV_I128; break;
13398 case ISD::UDIV: isSigned = false; LC = RTLIB::UDIV_I128; break;
13399 case ISD::SREM: isSigned = true; LC = RTLIB::SREM_I128; break;
13400 case ISD::UREM: isSigned = false; LC = RTLIB::UREM_I128; break;
13401 case ISD::SDIVREM: isSigned = true; LC = RTLIB::SDIVREM_I128; break;
13402 case ISD::UDIVREM: isSigned = false; LC = RTLIB::UDIVREM_I128; break;
13406 SDValue InChain = DAG.getEntryNode();
13408 TargetLowering::ArgListTy Args;
13409 TargetLowering::ArgListEntry Entry;
13410 for (unsigned i = 0, e = Op->getNumOperands(); i != e; ++i) {
13411 EVT ArgVT = Op->getOperand(i).getValueType();
13412 assert(ArgVT.isInteger() && ArgVT.getSizeInBits() == 128 &&
13413 "Unexpected argument type for lowering");
13414 SDValue StackPtr = DAG.CreateStackTemporary(ArgVT, 16);
13415 Entry.Node = StackPtr;
13416 InChain = DAG.getStore(InChain, dl, Op->getOperand(i), StackPtr, MachinePointerInfo(),
13418 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
13419 Entry.Ty = PointerType::get(ArgTy,0);
13420 Entry.isSExt = false;
13421 Entry.isZExt = false;
13422 Args.push_back(Entry);
13425 SDValue Callee = DAG.getExternalSymbol(getLibcallName(LC),
13428 TargetLowering::CallLoweringInfo CLI(DAG);
13429 CLI.setDebugLoc(dl).setChain(InChain)
13430 .setCallee(getLibcallCallingConv(LC),
13431 static_cast<EVT>(MVT::v2i64).getTypeForEVT(*DAG.getContext()),
13433 .setInRegister().setSExtResult(isSigned).setZExtResult(!isSigned);
13435 std::pair<SDValue, SDValue> CallInfo = LowerCallTo(CLI);
13436 return DAG.getNode(ISD::BITCAST, dl, VT, CallInfo.first);
13439 static SDValue LowerMUL_LOHI(SDValue Op, const X86Subtarget *Subtarget,
13440 SelectionDAG &DAG) {
13441 SDValue Op0 = Op.getOperand(0), Op1 = Op.getOperand(1);
13442 EVT VT = Op0.getValueType();
13445 assert((VT == MVT::v4i32 && Subtarget->hasSSE2()) ||
13446 (VT == MVT::v8i32 && Subtarget->hasInt256()));
13448 // Get the high parts.
13449 const int Mask[] = {1, 2, 3, 4, 5, 6, 7, 8};
13450 SDValue Hi0 = DAG.getVectorShuffle(VT, dl, Op0, Op0, Mask);
13451 SDValue Hi1 = DAG.getVectorShuffle(VT, dl, Op1, Op1, Mask);
13453 // Emit two multiplies, one for the lower 2 ints and one for the higher 2
13455 MVT MulVT = VT == MVT::v4i32 ? MVT::v2i64 : MVT::v4i64;
13456 bool IsSigned = Op->getOpcode() == ISD::SMUL_LOHI;
13458 (!IsSigned || !Subtarget->hasSSE41()) ? X86ISD::PMULUDQ : X86ISD::PMULDQ;
13459 SDValue Mul1 = DAG.getNode(ISD::BITCAST, dl, VT,
13460 DAG.getNode(Opcode, dl, MulVT, Op0, Op1));
13461 SDValue Mul2 = DAG.getNode(ISD::BITCAST, dl, VT,
13462 DAG.getNode(Opcode, dl, MulVT, Hi0, Hi1));
13464 // Shuffle it back into the right order.
13465 const int HighMask[] = {1, 5, 3, 7, 9, 13, 11, 15};
13466 SDValue Highs = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, HighMask);
13467 const int LowMask[] = {0, 4, 2, 6, 8, 12, 10, 14};
13468 SDValue Lows = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, LowMask);
13470 // If we have a signed multiply but no PMULDQ fix up the high parts of a
13471 // unsigned multiply.
13472 if (IsSigned && !Subtarget->hasSSE41()) {
13474 DAG.getConstant(31, DAG.getTargetLoweringInfo().getShiftAmountTy(VT));
13475 SDValue T1 = DAG.getNode(ISD::AND, dl, VT,
13476 DAG.getNode(ISD::SRA, dl, VT, Op0, ShAmt), Op1);
13477 SDValue T2 = DAG.getNode(ISD::AND, dl, VT,
13478 DAG.getNode(ISD::SRA, dl, VT, Op1, ShAmt), Op0);
13480 SDValue Fixup = DAG.getNode(ISD::ADD, dl, VT, T1, T2);
13481 Highs = DAG.getNode(ISD::SUB, dl, VT, Highs, Fixup);
13484 return DAG.getNode(ISD::MERGE_VALUES, dl, Op.getValueType(), Highs, Lows);
13487 static SDValue LowerScalarImmediateShift(SDValue Op, SelectionDAG &DAG,
13488 const X86Subtarget *Subtarget) {
13489 MVT VT = Op.getSimpleValueType();
13491 SDValue R = Op.getOperand(0);
13492 SDValue Amt = Op.getOperand(1);
13494 // Optimize shl/srl/sra with constant shift amount.
13495 if (isSplatVector(Amt.getNode())) {
13496 SDValue SclrAmt = Amt->getOperand(0);
13497 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(SclrAmt)) {
13498 uint64_t ShiftAmt = C->getZExtValue();
13500 if (VT == MVT::v2i64 || VT == MVT::v4i32 || VT == MVT::v8i16 ||
13501 (Subtarget->hasInt256() &&
13502 (VT == MVT::v4i64 || VT == MVT::v8i32 || VT == MVT::v16i16)) ||
13503 (Subtarget->hasAVX512() &&
13504 (VT == MVT::v8i64 || VT == MVT::v16i32))) {
13505 if (Op.getOpcode() == ISD::SHL)
13506 return getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, R, ShiftAmt,
13508 if (Op.getOpcode() == ISD::SRL)
13509 return getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, R, ShiftAmt,
13511 if (Op.getOpcode() == ISD::SRA && VT != MVT::v2i64 && VT != MVT::v4i64)
13512 return getTargetVShiftByConstNode(X86ISD::VSRAI, dl, VT, R, ShiftAmt,
13516 if (VT == MVT::v16i8) {
13517 if (Op.getOpcode() == ISD::SHL) {
13518 // Make a large shift.
13519 SDValue SHL = getTargetVShiftByConstNode(X86ISD::VSHLI, dl,
13520 MVT::v8i16, R, ShiftAmt,
13522 SHL = DAG.getNode(ISD::BITCAST, dl, VT, SHL);
13523 // Zero out the rightmost bits.
13524 SmallVector<SDValue, 16> V(16,
13525 DAG.getConstant(uint8_t(-1U << ShiftAmt),
13527 return DAG.getNode(ISD::AND, dl, VT, SHL,
13528 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V));
13530 if (Op.getOpcode() == ISD::SRL) {
13531 // Make a large shift.
13532 SDValue SRL = getTargetVShiftByConstNode(X86ISD::VSRLI, dl,
13533 MVT::v8i16, R, ShiftAmt,
13535 SRL = DAG.getNode(ISD::BITCAST, dl, VT, SRL);
13536 // Zero out the leftmost bits.
13537 SmallVector<SDValue, 16> V(16,
13538 DAG.getConstant(uint8_t(-1U) >> ShiftAmt,
13540 return DAG.getNode(ISD::AND, dl, VT, SRL,
13541 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V));
13543 if (Op.getOpcode() == ISD::SRA) {
13544 if (ShiftAmt == 7) {
13545 // R s>> 7 === R s< 0
13546 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
13547 return DAG.getNode(X86ISD::PCMPGT, dl, VT, Zeros, R);
13550 // R s>> a === ((R u>> a) ^ m) - m
13551 SDValue Res = DAG.getNode(ISD::SRL, dl, VT, R, Amt);
13552 SmallVector<SDValue, 16> V(16, DAG.getConstant(128 >> ShiftAmt,
13554 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V);
13555 Res = DAG.getNode(ISD::XOR, dl, VT, Res, Mask);
13556 Res = DAG.getNode(ISD::SUB, dl, VT, Res, Mask);
13559 llvm_unreachable("Unknown shift opcode.");
13562 if (Subtarget->hasInt256() && VT == MVT::v32i8) {
13563 if (Op.getOpcode() == ISD::SHL) {
13564 // Make a large shift.
13565 SDValue SHL = getTargetVShiftByConstNode(X86ISD::VSHLI, dl,
13566 MVT::v16i16, R, ShiftAmt,
13568 SHL = DAG.getNode(ISD::BITCAST, dl, VT, SHL);
13569 // Zero out the rightmost bits.
13570 SmallVector<SDValue, 32> V(32,
13571 DAG.getConstant(uint8_t(-1U << ShiftAmt),
13573 return DAG.getNode(ISD::AND, dl, VT, SHL,
13574 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V));
13576 if (Op.getOpcode() == ISD::SRL) {
13577 // Make a large shift.
13578 SDValue SRL = getTargetVShiftByConstNode(X86ISD::VSRLI, dl,
13579 MVT::v16i16, R, ShiftAmt,
13581 SRL = DAG.getNode(ISD::BITCAST, dl, VT, SRL);
13582 // Zero out the leftmost bits.
13583 SmallVector<SDValue, 32> V(32,
13584 DAG.getConstant(uint8_t(-1U) >> ShiftAmt,
13586 return DAG.getNode(ISD::AND, dl, VT, SRL,
13587 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V));
13589 if (Op.getOpcode() == ISD::SRA) {
13590 if (ShiftAmt == 7) {
13591 // R s>> 7 === R s< 0
13592 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
13593 return DAG.getNode(X86ISD::PCMPGT, dl, VT, Zeros, R);
13596 // R s>> a === ((R u>> a) ^ m) - m
13597 SDValue Res = DAG.getNode(ISD::SRL, dl, VT, R, Amt);
13598 SmallVector<SDValue, 32> V(32, DAG.getConstant(128 >> ShiftAmt,
13600 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V);
13601 Res = DAG.getNode(ISD::XOR, dl, VT, Res, Mask);
13602 Res = DAG.getNode(ISD::SUB, dl, VT, Res, Mask);
13605 llvm_unreachable("Unknown shift opcode.");
13610 // Special case in 32-bit mode, where i64 is expanded into high and low parts.
13611 if (!Subtarget->is64Bit() &&
13612 (VT == MVT::v2i64 || (Subtarget->hasInt256() && VT == MVT::v4i64)) &&
13613 Amt.getOpcode() == ISD::BITCAST &&
13614 Amt.getOperand(0).getOpcode() == ISD::BUILD_VECTOR) {
13615 Amt = Amt.getOperand(0);
13616 unsigned Ratio = Amt.getSimpleValueType().getVectorNumElements() /
13617 VT.getVectorNumElements();
13618 unsigned RatioInLog2 = Log2_32_Ceil(Ratio);
13619 uint64_t ShiftAmt = 0;
13620 for (unsigned i = 0; i != Ratio; ++i) {
13621 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Amt.getOperand(i));
13625 ShiftAmt |= C->getZExtValue() << (i * (1 << (6 - RatioInLog2)));
13627 // Check remaining shift amounts.
13628 for (unsigned i = Ratio; i != Amt.getNumOperands(); i += Ratio) {
13629 uint64_t ShAmt = 0;
13630 for (unsigned j = 0; j != Ratio; ++j) {
13631 ConstantSDNode *C =
13632 dyn_cast<ConstantSDNode>(Amt.getOperand(i + j));
13636 ShAmt |= C->getZExtValue() << (j * (1 << (6 - RatioInLog2)));
13638 if (ShAmt != ShiftAmt)
13641 switch (Op.getOpcode()) {
13643 llvm_unreachable("Unknown shift opcode!");
13645 return getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, R, ShiftAmt,
13648 return getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, R, ShiftAmt,
13651 return getTargetVShiftByConstNode(X86ISD::VSRAI, dl, VT, R, ShiftAmt,
13659 static SDValue LowerScalarVariableShift(SDValue Op, SelectionDAG &DAG,
13660 const X86Subtarget* Subtarget) {
13661 MVT VT = Op.getSimpleValueType();
13663 SDValue R = Op.getOperand(0);
13664 SDValue Amt = Op.getOperand(1);
13666 if ((VT == MVT::v2i64 && Op.getOpcode() != ISD::SRA) ||
13667 VT == MVT::v4i32 || VT == MVT::v8i16 ||
13668 (Subtarget->hasInt256() &&
13669 ((VT == MVT::v4i64 && Op.getOpcode() != ISD::SRA) ||
13670 VT == MVT::v8i32 || VT == MVT::v16i16)) ||
13671 (Subtarget->hasAVX512() && (VT == MVT::v8i64 || VT == MVT::v16i32))) {
13673 EVT EltVT = VT.getVectorElementType();
13675 if (Amt.getOpcode() == ISD::BUILD_VECTOR) {
13676 unsigned NumElts = VT.getVectorNumElements();
13678 for (i = 0; i != NumElts; ++i) {
13679 if (Amt.getOperand(i).getOpcode() == ISD::UNDEF)
13683 for (j = i; j != NumElts; ++j) {
13684 SDValue Arg = Amt.getOperand(j);
13685 if (Arg.getOpcode() == ISD::UNDEF) continue;
13686 if (Arg != Amt.getOperand(i))
13689 if (i != NumElts && j == NumElts)
13690 BaseShAmt = Amt.getOperand(i);
13692 if (Amt.getOpcode() == ISD::EXTRACT_SUBVECTOR)
13693 Amt = Amt.getOperand(0);
13694 if (Amt.getOpcode() == ISD::VECTOR_SHUFFLE &&
13695 cast<ShuffleVectorSDNode>(Amt)->isSplat()) {
13696 SDValue InVec = Amt.getOperand(0);
13697 if (InVec.getOpcode() == ISD::BUILD_VECTOR) {
13698 unsigned NumElts = InVec.getValueType().getVectorNumElements();
13700 for (; i != NumElts; ++i) {
13701 SDValue Arg = InVec.getOperand(i);
13702 if (Arg.getOpcode() == ISD::UNDEF) continue;
13706 } else if (InVec.getOpcode() == ISD::INSERT_VECTOR_ELT) {
13707 if (ConstantSDNode *C =
13708 dyn_cast<ConstantSDNode>(InVec.getOperand(2))) {
13709 unsigned SplatIdx =
13710 cast<ShuffleVectorSDNode>(Amt)->getSplatIndex();
13711 if (C->getZExtValue() == SplatIdx)
13712 BaseShAmt = InVec.getOperand(1);
13715 if (!BaseShAmt.getNode())
13716 BaseShAmt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, Amt,
13717 DAG.getIntPtrConstant(0));
13721 if (BaseShAmt.getNode()) {
13722 if (EltVT.bitsGT(MVT::i32))
13723 BaseShAmt = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, BaseShAmt);
13724 else if (EltVT.bitsLT(MVT::i32))
13725 BaseShAmt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, BaseShAmt);
13727 switch (Op.getOpcode()) {
13729 llvm_unreachable("Unknown shift opcode!");
13731 switch (VT.SimpleTy) {
13732 default: return SDValue();
13741 return getTargetVShiftNode(X86ISD::VSHLI, dl, VT, R, BaseShAmt, DAG);
13744 switch (VT.SimpleTy) {
13745 default: return SDValue();
13752 return getTargetVShiftNode(X86ISD::VSRAI, dl, VT, R, BaseShAmt, DAG);
13755 switch (VT.SimpleTy) {
13756 default: return SDValue();
13765 return getTargetVShiftNode(X86ISD::VSRLI, dl, VT, R, BaseShAmt, DAG);
13771 // Special case in 32-bit mode, where i64 is expanded into high and low parts.
13772 if (!Subtarget->is64Bit() &&
13773 (VT == MVT::v2i64 || (Subtarget->hasInt256() && VT == MVT::v4i64) ||
13774 (Subtarget->hasAVX512() && VT == MVT::v8i64)) &&
13775 Amt.getOpcode() == ISD::BITCAST &&
13776 Amt.getOperand(0).getOpcode() == ISD::BUILD_VECTOR) {
13777 Amt = Amt.getOperand(0);
13778 unsigned Ratio = Amt.getSimpleValueType().getVectorNumElements() /
13779 VT.getVectorNumElements();
13780 std::vector<SDValue> Vals(Ratio);
13781 for (unsigned i = 0; i != Ratio; ++i)
13782 Vals[i] = Amt.getOperand(i);
13783 for (unsigned i = Ratio; i != Amt.getNumOperands(); i += Ratio) {
13784 for (unsigned j = 0; j != Ratio; ++j)
13785 if (Vals[j] != Amt.getOperand(i + j))
13788 switch (Op.getOpcode()) {
13790 llvm_unreachable("Unknown shift opcode!");
13792 return DAG.getNode(X86ISD::VSHL, dl, VT, R, Op.getOperand(1));
13794 return DAG.getNode(X86ISD::VSRL, dl, VT, R, Op.getOperand(1));
13796 return DAG.getNode(X86ISD::VSRA, dl, VT, R, Op.getOperand(1));
13803 static SDValue LowerShift(SDValue Op, const X86Subtarget* Subtarget,
13804 SelectionDAG &DAG) {
13806 MVT VT = Op.getSimpleValueType();
13808 SDValue R = Op.getOperand(0);
13809 SDValue Amt = Op.getOperand(1);
13812 if (!Subtarget->hasSSE2())
13815 V = LowerScalarImmediateShift(Op, DAG, Subtarget);
13819 V = LowerScalarVariableShift(Op, DAG, Subtarget);
13823 if (Subtarget->hasAVX512() && (VT == MVT::v16i32 || VT == MVT::v8i64))
13825 // AVX2 has VPSLLV/VPSRAV/VPSRLV.
13826 if (Subtarget->hasInt256()) {
13827 if (Op.getOpcode() == ISD::SRL &&
13828 (VT == MVT::v2i64 || VT == MVT::v4i32 ||
13829 VT == MVT::v4i64 || VT == MVT::v8i32))
13831 if (Op.getOpcode() == ISD::SHL &&
13832 (VT == MVT::v2i64 || VT == MVT::v4i32 ||
13833 VT == MVT::v4i64 || VT == MVT::v8i32))
13835 if (Op.getOpcode() == ISD::SRA && (VT == MVT::v4i32 || VT == MVT::v8i32))
13839 // If possible, lower this packed shift into a vector multiply instead of
13840 // expanding it into a sequence of scalar shifts.
13841 // Do this only if the vector shift count is a constant build_vector.
13842 if (Op.getOpcode() == ISD::SHL &&
13843 (VT == MVT::v8i16 || VT == MVT::v4i32 ||
13844 (Subtarget->hasInt256() && VT == MVT::v16i16)) &&
13845 ISD::isBuildVectorOfConstantSDNodes(Amt.getNode())) {
13846 SmallVector<SDValue, 8> Elts;
13847 EVT SVT = VT.getScalarType();
13848 unsigned SVTBits = SVT.getSizeInBits();
13849 const APInt &One = APInt(SVTBits, 1);
13850 unsigned NumElems = VT.getVectorNumElements();
13852 for (unsigned i=0; i !=NumElems; ++i) {
13853 SDValue Op = Amt->getOperand(i);
13854 if (Op->getOpcode() == ISD::UNDEF) {
13855 Elts.push_back(Op);
13859 ConstantSDNode *ND = cast<ConstantSDNode>(Op);
13860 const APInt &C = APInt(SVTBits, ND->getAPIntValue().getZExtValue());
13861 uint64_t ShAmt = C.getZExtValue();
13862 if (ShAmt >= SVTBits) {
13863 Elts.push_back(DAG.getUNDEF(SVT));
13866 Elts.push_back(DAG.getConstant(One.shl(ShAmt), SVT));
13868 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Elts);
13869 return DAG.getNode(ISD::MUL, dl, VT, R, BV);
13872 // Lower SHL with variable shift amount.
13873 if (VT == MVT::v4i32 && Op->getOpcode() == ISD::SHL) {
13874 Op = DAG.getNode(ISD::SHL, dl, VT, Amt, DAG.getConstant(23, VT));
13876 Op = DAG.getNode(ISD::ADD, dl, VT, Op, DAG.getConstant(0x3f800000U, VT));
13877 Op = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, Op);
13878 Op = DAG.getNode(ISD::FP_TO_SINT, dl, VT, Op);
13879 return DAG.getNode(ISD::MUL, dl, VT, Op, R);
13882 // If possible, lower this shift as a sequence of two shifts by
13883 // constant plus a MOVSS/MOVSD instead of scalarizing it.
13885 // (v4i32 (srl A, (build_vector < X, Y, Y, Y>)))
13887 // Could be rewritten as:
13888 // (v4i32 (MOVSS (srl A, <Y,Y,Y,Y>), (srl A, <X,X,X,X>)))
13890 // The advantage is that the two shifts from the example would be
13891 // lowered as X86ISD::VSRLI nodes. This would be cheaper than scalarizing
13892 // the vector shift into four scalar shifts plus four pairs of vector
13894 if ((VT == MVT::v8i16 || VT == MVT::v4i32) &&
13895 ISD::isBuildVectorOfConstantSDNodes(Amt.getNode())) {
13896 unsigned TargetOpcode = X86ISD::MOVSS;
13897 bool CanBeSimplified;
13898 // The splat value for the first packed shift (the 'X' from the example).
13899 SDValue Amt1 = Amt->getOperand(0);
13900 // The splat value for the second packed shift (the 'Y' from the example).
13901 SDValue Amt2 = (VT == MVT::v4i32) ? Amt->getOperand(1) :
13902 Amt->getOperand(2);
13904 // See if it is possible to replace this node with a sequence of
13905 // two shifts followed by a MOVSS/MOVSD
13906 if (VT == MVT::v4i32) {
13907 // Check if it is legal to use a MOVSS.
13908 CanBeSimplified = Amt2 == Amt->getOperand(2) &&
13909 Amt2 == Amt->getOperand(3);
13910 if (!CanBeSimplified) {
13911 // Otherwise, check if we can still simplify this node using a MOVSD.
13912 CanBeSimplified = Amt1 == Amt->getOperand(1) &&
13913 Amt->getOperand(2) == Amt->getOperand(3);
13914 TargetOpcode = X86ISD::MOVSD;
13915 Amt2 = Amt->getOperand(2);
13918 // Do similar checks for the case where the machine value type
13920 CanBeSimplified = Amt1 == Amt->getOperand(1);
13921 for (unsigned i=3; i != 8 && CanBeSimplified; ++i)
13922 CanBeSimplified = Amt2 == Amt->getOperand(i);
13924 if (!CanBeSimplified) {
13925 TargetOpcode = X86ISD::MOVSD;
13926 CanBeSimplified = true;
13927 Amt2 = Amt->getOperand(4);
13928 for (unsigned i=0; i != 4 && CanBeSimplified; ++i)
13929 CanBeSimplified = Amt1 == Amt->getOperand(i);
13930 for (unsigned j=4; j != 8 && CanBeSimplified; ++j)
13931 CanBeSimplified = Amt2 == Amt->getOperand(j);
13935 if (CanBeSimplified && isa<ConstantSDNode>(Amt1) &&
13936 isa<ConstantSDNode>(Amt2)) {
13937 // Replace this node with two shifts followed by a MOVSS/MOVSD.
13938 EVT CastVT = MVT::v4i32;
13940 DAG.getConstant(cast<ConstantSDNode>(Amt1)->getAPIntValue(), VT);
13941 SDValue Shift1 = DAG.getNode(Op->getOpcode(), dl, VT, R, Splat1);
13943 DAG.getConstant(cast<ConstantSDNode>(Amt2)->getAPIntValue(), VT);
13944 SDValue Shift2 = DAG.getNode(Op->getOpcode(), dl, VT, R, Splat2);
13945 if (TargetOpcode == X86ISD::MOVSD)
13946 CastVT = MVT::v2i64;
13947 SDValue BitCast1 = DAG.getNode(ISD::BITCAST, dl, CastVT, Shift1);
13948 SDValue BitCast2 = DAG.getNode(ISD::BITCAST, dl, CastVT, Shift2);
13949 SDValue Result = getTargetShuffleNode(TargetOpcode, dl, CastVT, BitCast2,
13951 return DAG.getNode(ISD::BITCAST, dl, VT, Result);
13955 if (VT == MVT::v16i8 && Op->getOpcode() == ISD::SHL) {
13956 assert(Subtarget->hasSSE2() && "Need SSE2 for pslli/pcmpeq.");
13959 Op = DAG.getNode(ISD::SHL, dl, VT, Amt, DAG.getConstant(5, VT));
13960 Op = DAG.getNode(ISD::BITCAST, dl, VT, Op);
13962 // Turn 'a' into a mask suitable for VSELECT
13963 SDValue VSelM = DAG.getConstant(0x80, VT);
13964 SDValue OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
13965 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
13967 SDValue CM1 = DAG.getConstant(0x0f, VT);
13968 SDValue CM2 = DAG.getConstant(0x3f, VT);
13970 // r = VSELECT(r, psllw(r & (char16)15, 4), a);
13971 SDValue M = DAG.getNode(ISD::AND, dl, VT, R, CM1);
13972 M = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, MVT::v8i16, M, 4, DAG);
13973 M = DAG.getNode(ISD::BITCAST, dl, VT, M);
13974 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel, M, R);
13977 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op);
13978 OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
13979 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
13981 // r = VSELECT(r, psllw(r & (char16)63, 2), a);
13982 M = DAG.getNode(ISD::AND, dl, VT, R, CM2);
13983 M = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, MVT::v8i16, M, 2, DAG);
13984 M = DAG.getNode(ISD::BITCAST, dl, VT, M);
13985 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel, M, R);
13988 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op);
13989 OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
13990 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
13992 // return VSELECT(r, r+r, a);
13993 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel,
13994 DAG.getNode(ISD::ADD, dl, VT, R, R), R);
13998 // It's worth extending once and using the v8i32 shifts for 16-bit types, but
13999 // the extra overheads to get from v16i8 to v8i32 make the existing SSE
14000 // solution better.
14001 if (Subtarget->hasInt256() && VT == MVT::v8i16) {
14002 MVT NewVT = VT == MVT::v8i16 ? MVT::v8i32 : MVT::v16i16;
14004 Op.getOpcode() == ISD::SRA ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
14005 R = DAG.getNode(ExtOpc, dl, NewVT, R);
14006 Amt = DAG.getNode(ISD::ANY_EXTEND, dl, NewVT, Amt);
14007 return DAG.getNode(ISD::TRUNCATE, dl, VT,
14008 DAG.getNode(Op.getOpcode(), dl, NewVT, R, Amt));
14011 // Decompose 256-bit shifts into smaller 128-bit shifts.
14012 if (VT.is256BitVector()) {
14013 unsigned NumElems = VT.getVectorNumElements();
14014 MVT EltVT = VT.getVectorElementType();
14015 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
14017 // Extract the two vectors
14018 SDValue V1 = Extract128BitVector(R, 0, DAG, dl);
14019 SDValue V2 = Extract128BitVector(R, NumElems/2, DAG, dl);
14021 // Recreate the shift amount vectors
14022 SDValue Amt1, Amt2;
14023 if (Amt.getOpcode() == ISD::BUILD_VECTOR) {
14024 // Constant shift amount
14025 SmallVector<SDValue, 4> Amt1Csts;
14026 SmallVector<SDValue, 4> Amt2Csts;
14027 for (unsigned i = 0; i != NumElems/2; ++i)
14028 Amt1Csts.push_back(Amt->getOperand(i));
14029 for (unsigned i = NumElems/2; i != NumElems; ++i)
14030 Amt2Csts.push_back(Amt->getOperand(i));
14032 Amt1 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, Amt1Csts);
14033 Amt2 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, Amt2Csts);
14035 // Variable shift amount
14036 Amt1 = Extract128BitVector(Amt, 0, DAG, dl);
14037 Amt2 = Extract128BitVector(Amt, NumElems/2, DAG, dl);
14040 // Issue new vector shifts for the smaller types
14041 V1 = DAG.getNode(Op.getOpcode(), dl, NewVT, V1, Amt1);
14042 V2 = DAG.getNode(Op.getOpcode(), dl, NewVT, V2, Amt2);
14044 // Concatenate the result back
14045 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, V1, V2);
14051 static SDValue LowerXALUO(SDValue Op, SelectionDAG &DAG) {
14052 // Lower the "add/sub/mul with overflow" instruction into a regular ins plus
14053 // a "setcc" instruction that checks the overflow flag. The "brcond" lowering
14054 // looks for this combo and may remove the "setcc" instruction if the "setcc"
14055 // has only one use.
14056 SDNode *N = Op.getNode();
14057 SDValue LHS = N->getOperand(0);
14058 SDValue RHS = N->getOperand(1);
14059 unsigned BaseOp = 0;
14062 switch (Op.getOpcode()) {
14063 default: llvm_unreachable("Unknown ovf instruction!");
14065 // A subtract of one will be selected as a INC. Note that INC doesn't
14066 // set CF, so we can't do this for UADDO.
14067 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
14069 BaseOp = X86ISD::INC;
14070 Cond = X86::COND_O;
14073 BaseOp = X86ISD::ADD;
14074 Cond = X86::COND_O;
14077 BaseOp = X86ISD::ADD;
14078 Cond = X86::COND_B;
14081 // A subtract of one will be selected as a DEC. Note that DEC doesn't
14082 // set CF, so we can't do this for USUBO.
14083 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
14085 BaseOp = X86ISD::DEC;
14086 Cond = X86::COND_O;
14089 BaseOp = X86ISD::SUB;
14090 Cond = X86::COND_O;
14093 BaseOp = X86ISD::SUB;
14094 Cond = X86::COND_B;
14097 BaseOp = X86ISD::SMUL;
14098 Cond = X86::COND_O;
14100 case ISD::UMULO: { // i64, i8 = umulo lhs, rhs --> i64, i64, i32 umul lhs,rhs
14101 SDVTList VTs = DAG.getVTList(N->getValueType(0), N->getValueType(0),
14103 SDValue Sum = DAG.getNode(X86ISD::UMUL, DL, VTs, LHS, RHS);
14106 DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
14107 DAG.getConstant(X86::COND_O, MVT::i32),
14108 SDValue(Sum.getNode(), 2));
14110 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
14114 // Also sets EFLAGS.
14115 SDVTList VTs = DAG.getVTList(N->getValueType(0), MVT::i32);
14116 SDValue Sum = DAG.getNode(BaseOp, DL, VTs, LHS, RHS);
14119 DAG.getNode(X86ISD::SETCC, DL, N->getValueType(1),
14120 DAG.getConstant(Cond, MVT::i32),
14121 SDValue(Sum.getNode(), 1));
14123 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
14126 SDValue X86TargetLowering::LowerSIGN_EXTEND_INREG(SDValue Op,
14127 SelectionDAG &DAG) const {
14129 EVT ExtraVT = cast<VTSDNode>(Op.getOperand(1))->getVT();
14130 MVT VT = Op.getSimpleValueType();
14132 if (!Subtarget->hasSSE2() || !VT.isVector())
14135 unsigned BitsDiff = VT.getScalarType().getSizeInBits() -
14136 ExtraVT.getScalarType().getSizeInBits();
14138 switch (VT.SimpleTy) {
14139 default: return SDValue();
14142 if (!Subtarget->hasFp256())
14144 if (!Subtarget->hasInt256()) {
14145 // needs to be split
14146 unsigned NumElems = VT.getVectorNumElements();
14148 // Extract the LHS vectors
14149 SDValue LHS = Op.getOperand(0);
14150 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
14151 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
14153 MVT EltVT = VT.getVectorElementType();
14154 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
14156 EVT ExtraEltVT = ExtraVT.getVectorElementType();
14157 unsigned ExtraNumElems = ExtraVT.getVectorNumElements();
14158 ExtraVT = EVT::getVectorVT(*DAG.getContext(), ExtraEltVT,
14160 SDValue Extra = DAG.getValueType(ExtraVT);
14162 LHS1 = DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, Extra);
14163 LHS2 = DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, Extra);
14165 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, LHS1, LHS2);
14170 SDValue Op0 = Op.getOperand(0);
14171 SDValue Op00 = Op0.getOperand(0);
14173 // Hopefully, this VECTOR_SHUFFLE is just a VZEXT.
14174 if (Op0.getOpcode() == ISD::BITCAST &&
14175 Op00.getOpcode() == ISD::VECTOR_SHUFFLE) {
14176 // (sext (vzext x)) -> (vsext x)
14177 Tmp1 = LowerVectorIntExtend(Op00, Subtarget, DAG);
14178 if (Tmp1.getNode()) {
14179 EVT ExtraEltVT = ExtraVT.getVectorElementType();
14180 // This folding is only valid when the in-reg type is a vector of i8,
14182 if (ExtraEltVT == MVT::i8 || ExtraEltVT == MVT::i16 ||
14183 ExtraEltVT == MVT::i32) {
14184 SDValue Tmp1Op0 = Tmp1.getOperand(0);
14185 assert(Tmp1Op0.getOpcode() == X86ISD::VZEXT &&
14186 "This optimization is invalid without a VZEXT.");
14187 return DAG.getNode(X86ISD::VSEXT, dl, VT, Tmp1Op0.getOperand(0));
14193 // If the above didn't work, then just use Shift-Left + Shift-Right.
14194 Tmp1 = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, Op0, BitsDiff,
14196 return getTargetVShiftByConstNode(X86ISD::VSRAI, dl, VT, Tmp1, BitsDiff,
14202 static SDValue LowerATOMIC_FENCE(SDValue Op, const X86Subtarget *Subtarget,
14203 SelectionDAG &DAG) {
14205 AtomicOrdering FenceOrdering = static_cast<AtomicOrdering>(
14206 cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue());
14207 SynchronizationScope FenceScope = static_cast<SynchronizationScope>(
14208 cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue());
14210 // The only fence that needs an instruction is a sequentially-consistent
14211 // cross-thread fence.
14212 if (FenceOrdering == SequentiallyConsistent && FenceScope == CrossThread) {
14213 // Use mfence if we have SSE2 or we're on x86-64 (even if we asked for
14214 // no-sse2). There isn't any reason to disable it if the target processor
14216 if (Subtarget->hasSSE2() || Subtarget->is64Bit())
14217 return DAG.getNode(X86ISD::MFENCE, dl, MVT::Other, Op.getOperand(0));
14219 SDValue Chain = Op.getOperand(0);
14220 SDValue Zero = DAG.getConstant(0, MVT::i32);
14222 DAG.getRegister(X86::ESP, MVT::i32), // Base
14223 DAG.getTargetConstant(1, MVT::i8), // Scale
14224 DAG.getRegister(0, MVT::i32), // Index
14225 DAG.getTargetConstant(0, MVT::i32), // Disp
14226 DAG.getRegister(0, MVT::i32), // Segment.
14230 SDNode *Res = DAG.getMachineNode(X86::OR32mrLocked, dl, MVT::Other, Ops);
14231 return SDValue(Res, 0);
14234 // MEMBARRIER is a compiler barrier; it codegens to a no-op.
14235 return DAG.getNode(X86ISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0));
14238 static SDValue LowerCMP_SWAP(SDValue Op, const X86Subtarget *Subtarget,
14239 SelectionDAG &DAG) {
14240 MVT T = Op.getSimpleValueType();
14244 switch(T.SimpleTy) {
14245 default: llvm_unreachable("Invalid value type!");
14246 case MVT::i8: Reg = X86::AL; size = 1; break;
14247 case MVT::i16: Reg = X86::AX; size = 2; break;
14248 case MVT::i32: Reg = X86::EAX; size = 4; break;
14250 assert(Subtarget->is64Bit() && "Node not type legal!");
14251 Reg = X86::RAX; size = 8;
14254 SDValue cpIn = DAG.getCopyToReg(Op.getOperand(0), DL, Reg,
14255 Op.getOperand(2), SDValue());
14256 SDValue Ops[] = { cpIn.getValue(0),
14259 DAG.getTargetConstant(size, MVT::i8),
14260 cpIn.getValue(1) };
14261 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
14262 MachineMemOperand *MMO = cast<AtomicSDNode>(Op)->getMemOperand();
14263 SDValue Result = DAG.getMemIntrinsicNode(X86ISD::LCMPXCHG_DAG, DL, Tys,
14266 DAG.getCopyFromReg(Result.getValue(0), DL, Reg, T, Result.getValue(1));
14270 static SDValue LowerBITCAST(SDValue Op, const X86Subtarget *Subtarget,
14271 SelectionDAG &DAG) {
14272 MVT SrcVT = Op.getOperand(0).getSimpleValueType();
14273 MVT DstVT = Op.getSimpleValueType();
14275 if (SrcVT == MVT::v2i32) {
14276 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
14277 if (DstVT != MVT::f64)
14278 // This conversion needs to be expanded.
14282 SDValue Elt0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
14283 Op->getOperand(0), DAG.getIntPtrConstant(0));
14284 SDValue Elt1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
14285 Op->getOperand(0), DAG.getIntPtrConstant(1));
14286 SDValue Elts[] = {Elt0, Elt1, Elt0, Elt0};
14287 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Elts);
14288 SDValue ToV2F64 = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, BV);
14289 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, ToV2F64,
14290 DAG.getIntPtrConstant(0));
14293 assert(Subtarget->is64Bit() && !Subtarget->hasSSE2() &&
14294 Subtarget->hasMMX() && "Unexpected custom BITCAST");
14295 assert((DstVT == MVT::i64 ||
14296 (DstVT.isVector() && DstVT.getSizeInBits()==64)) &&
14297 "Unexpected custom BITCAST");
14298 // i64 <=> MMX conversions are Legal.
14299 if (SrcVT==MVT::i64 && DstVT.isVector())
14301 if (DstVT==MVT::i64 && SrcVT.isVector())
14303 // MMX <=> MMX conversions are Legal.
14304 if (SrcVT.isVector() && DstVT.isVector())
14306 // All other conversions need to be expanded.
14310 static SDValue LowerLOAD_SUB(SDValue Op, SelectionDAG &DAG) {
14311 SDNode *Node = Op.getNode();
14313 EVT T = Node->getValueType(0);
14314 SDValue negOp = DAG.getNode(ISD::SUB, dl, T,
14315 DAG.getConstant(0, T), Node->getOperand(2));
14316 return DAG.getAtomic(ISD::ATOMIC_LOAD_ADD, dl,
14317 cast<AtomicSDNode>(Node)->getMemoryVT(),
14318 Node->getOperand(0),
14319 Node->getOperand(1), negOp,
14320 cast<AtomicSDNode>(Node)->getMemOperand(),
14321 cast<AtomicSDNode>(Node)->getOrdering(),
14322 cast<AtomicSDNode>(Node)->getSynchScope());
14325 static SDValue LowerATOMIC_STORE(SDValue Op, SelectionDAG &DAG) {
14326 SDNode *Node = Op.getNode();
14328 EVT VT = cast<AtomicSDNode>(Node)->getMemoryVT();
14330 // Convert seq_cst store -> xchg
14331 // Convert wide store -> swap (-> cmpxchg8b/cmpxchg16b)
14332 // FIXME: On 32-bit, store -> fist or movq would be more efficient
14333 // (The only way to get a 16-byte store is cmpxchg16b)
14334 // FIXME: 16-byte ATOMIC_SWAP isn't actually hooked up at the moment.
14335 if (cast<AtomicSDNode>(Node)->getOrdering() == SequentiallyConsistent ||
14336 !DAG.getTargetLoweringInfo().isTypeLegal(VT)) {
14337 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_SWAP, dl,
14338 cast<AtomicSDNode>(Node)->getMemoryVT(),
14339 Node->getOperand(0),
14340 Node->getOperand(1), Node->getOperand(2),
14341 cast<AtomicSDNode>(Node)->getMemOperand(),
14342 cast<AtomicSDNode>(Node)->getOrdering(),
14343 cast<AtomicSDNode>(Node)->getSynchScope());
14344 return Swap.getValue(1);
14346 // Other atomic stores have a simple pattern.
14350 static SDValue LowerADDC_ADDE_SUBC_SUBE(SDValue Op, SelectionDAG &DAG) {
14351 EVT VT = Op.getNode()->getSimpleValueType(0);
14353 // Let legalize expand this if it isn't a legal type yet.
14354 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
14357 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
14360 bool ExtraOp = false;
14361 switch (Op.getOpcode()) {
14362 default: llvm_unreachable("Invalid code");
14363 case ISD::ADDC: Opc = X86ISD::ADD; break;
14364 case ISD::ADDE: Opc = X86ISD::ADC; ExtraOp = true; break;
14365 case ISD::SUBC: Opc = X86ISD::SUB; break;
14366 case ISD::SUBE: Opc = X86ISD::SBB; ExtraOp = true; break;
14370 return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0),
14372 return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0),
14373 Op.getOperand(1), Op.getOperand(2));
14376 static SDValue LowerFSINCOS(SDValue Op, const X86Subtarget *Subtarget,
14377 SelectionDAG &DAG) {
14378 assert(Subtarget->isTargetDarwin() && Subtarget->is64Bit());
14380 // For MacOSX, we want to call an alternative entry point: __sincos_stret,
14381 // which returns the values as { float, float } (in XMM0) or
14382 // { double, double } (which is returned in XMM0, XMM1).
14384 SDValue Arg = Op.getOperand(0);
14385 EVT ArgVT = Arg.getValueType();
14386 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
14388 TargetLowering::ArgListTy Args;
14389 TargetLowering::ArgListEntry Entry;
14393 Entry.isSExt = false;
14394 Entry.isZExt = false;
14395 Args.push_back(Entry);
14397 bool isF64 = ArgVT == MVT::f64;
14398 // Only optimize x86_64 for now. i386 is a bit messy. For f32,
14399 // the small struct {f32, f32} is returned in (eax, edx). For f64,
14400 // the results are returned via SRet in memory.
14401 const char *LibcallName = isF64 ? "__sincos_stret" : "__sincosf_stret";
14402 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
14403 SDValue Callee = DAG.getExternalSymbol(LibcallName, TLI.getPointerTy());
14405 Type *RetTy = isF64
14406 ? (Type*)StructType::get(ArgTy, ArgTy, NULL)
14407 : (Type*)VectorType::get(ArgTy, 4);
14409 TargetLowering::CallLoweringInfo CLI(DAG);
14410 CLI.setDebugLoc(dl).setChain(DAG.getEntryNode())
14411 .setCallee(CallingConv::C, RetTy, Callee, &Args, 0);
14413 std::pair<SDValue, SDValue> CallResult = TLI.LowerCallTo(CLI);
14416 // Returned in xmm0 and xmm1.
14417 return CallResult.first;
14419 // Returned in bits 0:31 and 32:64 xmm0.
14420 SDValue SinVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ArgVT,
14421 CallResult.first, DAG.getIntPtrConstant(0));
14422 SDValue CosVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ArgVT,
14423 CallResult.first, DAG.getIntPtrConstant(1));
14424 SDVTList Tys = DAG.getVTList(ArgVT, ArgVT);
14425 return DAG.getNode(ISD::MERGE_VALUES, dl, Tys, SinVal, CosVal);
14428 /// LowerOperation - Provide custom lowering hooks for some operations.
14430 SDValue X86TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
14431 switch (Op.getOpcode()) {
14432 default: llvm_unreachable("Should not custom lower this!");
14433 case ISD::SIGN_EXTEND_INREG: return LowerSIGN_EXTEND_INREG(Op,DAG);
14434 case ISD::ATOMIC_FENCE: return LowerATOMIC_FENCE(Op, Subtarget, DAG);
14435 case ISD::ATOMIC_CMP_SWAP: return LowerCMP_SWAP(Op, Subtarget, DAG);
14436 case ISD::ATOMIC_LOAD_SUB: return LowerLOAD_SUB(Op,DAG);
14437 case ISD::ATOMIC_STORE: return LowerATOMIC_STORE(Op,DAG);
14438 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
14439 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG);
14440 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
14441 case ISD::VSELECT: return LowerVSELECT(Op, DAG);
14442 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
14443 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG);
14444 case ISD::EXTRACT_SUBVECTOR: return LowerEXTRACT_SUBVECTOR(Op,Subtarget,DAG);
14445 case ISD::INSERT_SUBVECTOR: return LowerINSERT_SUBVECTOR(Op, Subtarget,DAG);
14446 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
14447 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
14448 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
14449 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
14450 case ISD::ExternalSymbol: return LowerExternalSymbol(Op, DAG);
14451 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
14452 case ISD::SHL_PARTS:
14453 case ISD::SRA_PARTS:
14454 case ISD::SRL_PARTS: return LowerShiftParts(Op, DAG);
14455 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG);
14456 case ISD::UINT_TO_FP: return LowerUINT_TO_FP(Op, DAG);
14457 case ISD::TRUNCATE: return LowerTRUNCATE(Op, DAG);
14458 case ISD::ZERO_EXTEND: return LowerZERO_EXTEND(Op, Subtarget, DAG);
14459 case ISD::SIGN_EXTEND: return LowerSIGN_EXTEND(Op, Subtarget, DAG);
14460 case ISD::ANY_EXTEND: return LowerANY_EXTEND(Op, Subtarget, DAG);
14461 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG);
14462 case ISD::FP_TO_UINT: return LowerFP_TO_UINT(Op, DAG);
14463 case ISD::FP_EXTEND: return LowerFP_EXTEND(Op, DAG);
14464 case ISD::FABS: return LowerFABS(Op, DAG);
14465 case ISD::FNEG: return LowerFNEG(Op, DAG);
14466 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG);
14467 case ISD::FGETSIGN: return LowerFGETSIGN(Op, DAG);
14468 case ISD::SETCC: return LowerSETCC(Op, DAG);
14469 case ISD::SELECT: return LowerSELECT(Op, DAG);
14470 case ISD::BRCOND: return LowerBRCOND(Op, DAG);
14471 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
14472 case ISD::VASTART: return LowerVASTART(Op, DAG);
14473 case ISD::VAARG: return LowerVAARG(Op, DAG);
14474 case ISD::VACOPY: return LowerVACOPY(Op, Subtarget, DAG);
14475 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
14476 case ISD::INTRINSIC_VOID:
14477 case ISD::INTRINSIC_W_CHAIN: return LowerINTRINSIC_W_CHAIN(Op, Subtarget, DAG);
14478 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
14479 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
14480 case ISD::FRAME_TO_ARGS_OFFSET:
14481 return LowerFRAME_TO_ARGS_OFFSET(Op, DAG);
14482 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
14483 case ISD::EH_RETURN: return LowerEH_RETURN(Op, DAG);
14484 case ISD::EH_SJLJ_SETJMP: return lowerEH_SJLJ_SETJMP(Op, DAG);
14485 case ISD::EH_SJLJ_LONGJMP: return lowerEH_SJLJ_LONGJMP(Op, DAG);
14486 case ISD::INIT_TRAMPOLINE: return LowerINIT_TRAMPOLINE(Op, DAG);
14487 case ISD::ADJUST_TRAMPOLINE: return LowerADJUST_TRAMPOLINE(Op, DAG);
14488 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
14489 case ISD::CTLZ: return LowerCTLZ(Op, DAG);
14490 case ISD::CTLZ_ZERO_UNDEF: return LowerCTLZ_ZERO_UNDEF(Op, DAG);
14491 case ISD::CTTZ: return LowerCTTZ(Op, DAG);
14492 case ISD::MUL: return LowerMUL(Op, Subtarget, DAG);
14493 case ISD::UMUL_LOHI:
14494 case ISD::SMUL_LOHI: return LowerMUL_LOHI(Op, Subtarget, DAG);
14497 case ISD::SHL: return LowerShift(Op, Subtarget, DAG);
14503 case ISD::UMULO: return LowerXALUO(Op, DAG);
14504 case ISD::READCYCLECOUNTER: return LowerREADCYCLECOUNTER(Op, Subtarget,DAG);
14505 case ISD::BITCAST: return LowerBITCAST(Op, Subtarget, DAG);
14509 case ISD::SUBE: return LowerADDC_ADDE_SUBC_SUBE(Op, DAG);
14510 case ISD::ADD: return LowerADD(Op, DAG);
14511 case ISD::SUB: return LowerSUB(Op, DAG);
14512 case ISD::FSINCOS: return LowerFSINCOS(Op, Subtarget, DAG);
14516 static void ReplaceATOMIC_LOAD(SDNode *Node,
14517 SmallVectorImpl<SDValue> &Results,
14518 SelectionDAG &DAG) {
14520 EVT VT = cast<AtomicSDNode>(Node)->getMemoryVT();
14522 // Convert wide load -> cmpxchg8b/cmpxchg16b
14523 // FIXME: On 32-bit, load -> fild or movq would be more efficient
14524 // (The only way to get a 16-byte load is cmpxchg16b)
14525 // FIXME: 16-byte ATOMIC_CMP_SWAP isn't actually hooked up at the moment.
14526 SDValue Zero = DAG.getConstant(0, VT);
14527 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_CMP_SWAP, dl, VT,
14528 Node->getOperand(0),
14529 Node->getOperand(1), Zero, Zero,
14530 cast<AtomicSDNode>(Node)->getMemOperand(),
14531 cast<AtomicSDNode>(Node)->getOrdering(),
14532 cast<AtomicSDNode>(Node)->getOrdering(),
14533 cast<AtomicSDNode>(Node)->getSynchScope());
14534 Results.push_back(Swap.getValue(0));
14535 Results.push_back(Swap.getValue(1));
14539 ReplaceATOMIC_BINARY_64(SDNode *Node, SmallVectorImpl<SDValue>&Results,
14540 SelectionDAG &DAG, unsigned NewOp) {
14542 assert (Node->getValueType(0) == MVT::i64 &&
14543 "Only know how to expand i64 atomics");
14545 SDValue Chain = Node->getOperand(0);
14546 SDValue In1 = Node->getOperand(1);
14547 SDValue In2L = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
14548 Node->getOperand(2), DAG.getIntPtrConstant(0));
14549 SDValue In2H = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
14550 Node->getOperand(2), DAG.getIntPtrConstant(1));
14551 SDValue Ops[] = { Chain, In1, In2L, In2H };
14552 SDVTList Tys = DAG.getVTList(MVT::i32, MVT::i32, MVT::Other);
14554 DAG.getMemIntrinsicNode(NewOp, dl, Tys, Ops, MVT::i64,
14555 cast<MemSDNode>(Node)->getMemOperand());
14556 SDValue OpsF[] = { Result.getValue(0), Result.getValue(1)};
14557 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, OpsF));
14558 Results.push_back(Result.getValue(2));
14561 /// ReplaceNodeResults - Replace a node with an illegal result type
14562 /// with a new node built out of custom code.
14563 void X86TargetLowering::ReplaceNodeResults(SDNode *N,
14564 SmallVectorImpl<SDValue>&Results,
14565 SelectionDAG &DAG) const {
14567 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
14568 switch (N->getOpcode()) {
14570 llvm_unreachable("Do not know how to custom type legalize this operation!");
14571 case ISD::SIGN_EXTEND_INREG:
14576 // We don't want to expand or promote these.
14583 case ISD::UDIVREM: {
14584 SDValue V = LowerWin64_i128OP(SDValue(N,0), DAG);
14585 Results.push_back(V);
14588 case ISD::FP_TO_SINT:
14589 case ISD::FP_TO_UINT: {
14590 bool IsSigned = N->getOpcode() == ISD::FP_TO_SINT;
14592 if (!IsSigned && !isIntegerTypeFTOL(SDValue(N, 0).getValueType()))
14595 std::pair<SDValue,SDValue> Vals =
14596 FP_TO_INTHelper(SDValue(N, 0), DAG, IsSigned, /*IsReplace=*/ true);
14597 SDValue FIST = Vals.first, StackSlot = Vals.second;
14598 if (FIST.getNode()) {
14599 EVT VT = N->getValueType(0);
14600 // Return a load from the stack slot.
14601 if (StackSlot.getNode())
14602 Results.push_back(DAG.getLoad(VT, dl, FIST, StackSlot,
14603 MachinePointerInfo(),
14604 false, false, false, 0));
14606 Results.push_back(FIST);
14610 case ISD::UINT_TO_FP: {
14611 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
14612 if (N->getOperand(0).getValueType() != MVT::v2i32 ||
14613 N->getValueType(0) != MVT::v2f32)
14615 SDValue ZExtIn = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v2i64,
14617 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL),
14619 SDValue VBias = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2f64, Bias, Bias);
14620 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64, ZExtIn,
14621 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, VBias));
14622 Or = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Or);
14623 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, Or, VBias);
14624 Results.push_back(DAG.getNode(X86ISD::VFPROUND, dl, MVT::v4f32, Sub));
14627 case ISD::FP_ROUND: {
14628 if (!TLI.isTypeLegal(N->getOperand(0).getValueType()))
14630 SDValue V = DAG.getNode(X86ISD::VFPROUND, dl, MVT::v4f32, N->getOperand(0));
14631 Results.push_back(V);
14634 case ISD::INTRINSIC_W_CHAIN: {
14635 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
14637 default : llvm_unreachable("Do not know how to custom type "
14638 "legalize this intrinsic operation!");
14639 case Intrinsic::x86_rdtsc:
14640 return getReadTimeStampCounter(N, dl, X86ISD::RDTSC_DAG, DAG, Subtarget,
14642 case Intrinsic::x86_rdtscp:
14643 return getReadTimeStampCounter(N, dl, X86ISD::RDTSCP_DAG, DAG, Subtarget,
14647 case ISD::READCYCLECOUNTER: {
14648 return getReadTimeStampCounter(N, dl, X86ISD::RDTSC_DAG, DAG, Subtarget,
14651 case ISD::ATOMIC_CMP_SWAP: {
14652 EVT T = N->getValueType(0);
14653 assert((T == MVT::i64 || T == MVT::i128) && "can only expand cmpxchg pair");
14654 bool Regs64bit = T == MVT::i128;
14655 EVT HalfT = Regs64bit ? MVT::i64 : MVT::i32;
14656 SDValue cpInL, cpInH;
14657 cpInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2),
14658 DAG.getConstant(0, HalfT));
14659 cpInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2),
14660 DAG.getConstant(1, HalfT));
14661 cpInL = DAG.getCopyToReg(N->getOperand(0), dl,
14662 Regs64bit ? X86::RAX : X86::EAX,
14664 cpInH = DAG.getCopyToReg(cpInL.getValue(0), dl,
14665 Regs64bit ? X86::RDX : X86::EDX,
14666 cpInH, cpInL.getValue(1));
14667 SDValue swapInL, swapInH;
14668 swapInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3),
14669 DAG.getConstant(0, HalfT));
14670 swapInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3),
14671 DAG.getConstant(1, HalfT));
14672 swapInL = DAG.getCopyToReg(cpInH.getValue(0), dl,
14673 Regs64bit ? X86::RBX : X86::EBX,
14674 swapInL, cpInH.getValue(1));
14675 swapInH = DAG.getCopyToReg(swapInL.getValue(0), dl,
14676 Regs64bit ? X86::RCX : X86::ECX,
14677 swapInH, swapInL.getValue(1));
14678 SDValue Ops[] = { swapInH.getValue(0),
14680 swapInH.getValue(1) };
14681 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
14682 MachineMemOperand *MMO = cast<AtomicSDNode>(N)->getMemOperand();
14683 unsigned Opcode = Regs64bit ? X86ISD::LCMPXCHG16_DAG :
14684 X86ISD::LCMPXCHG8_DAG;
14685 SDValue Result = DAG.getMemIntrinsicNode(Opcode, dl, Tys, Ops, T, MMO);
14686 SDValue cpOutL = DAG.getCopyFromReg(Result.getValue(0), dl,
14687 Regs64bit ? X86::RAX : X86::EAX,
14688 HalfT, Result.getValue(1));
14689 SDValue cpOutH = DAG.getCopyFromReg(cpOutL.getValue(1), dl,
14690 Regs64bit ? X86::RDX : X86::EDX,
14691 HalfT, cpOutL.getValue(2));
14692 SDValue OpsF[] = { cpOutL.getValue(0), cpOutH.getValue(0)};
14693 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, T, OpsF));
14694 Results.push_back(cpOutH.getValue(1));
14697 case ISD::ATOMIC_LOAD_ADD:
14698 case ISD::ATOMIC_LOAD_AND:
14699 case ISD::ATOMIC_LOAD_NAND:
14700 case ISD::ATOMIC_LOAD_OR:
14701 case ISD::ATOMIC_LOAD_SUB:
14702 case ISD::ATOMIC_LOAD_XOR:
14703 case ISD::ATOMIC_LOAD_MAX:
14704 case ISD::ATOMIC_LOAD_MIN:
14705 case ISD::ATOMIC_LOAD_UMAX:
14706 case ISD::ATOMIC_LOAD_UMIN:
14707 case ISD::ATOMIC_SWAP: {
14709 switch (N->getOpcode()) {
14710 default: llvm_unreachable("Unexpected opcode");
14711 case ISD::ATOMIC_LOAD_ADD:
14712 Opc = X86ISD::ATOMADD64_DAG;
14714 case ISD::ATOMIC_LOAD_AND:
14715 Opc = X86ISD::ATOMAND64_DAG;
14717 case ISD::ATOMIC_LOAD_NAND:
14718 Opc = X86ISD::ATOMNAND64_DAG;
14720 case ISD::ATOMIC_LOAD_OR:
14721 Opc = X86ISD::ATOMOR64_DAG;
14723 case ISD::ATOMIC_LOAD_SUB:
14724 Opc = X86ISD::ATOMSUB64_DAG;
14726 case ISD::ATOMIC_LOAD_XOR:
14727 Opc = X86ISD::ATOMXOR64_DAG;
14729 case ISD::ATOMIC_LOAD_MAX:
14730 Opc = X86ISD::ATOMMAX64_DAG;
14732 case ISD::ATOMIC_LOAD_MIN:
14733 Opc = X86ISD::ATOMMIN64_DAG;
14735 case ISD::ATOMIC_LOAD_UMAX:
14736 Opc = X86ISD::ATOMUMAX64_DAG;
14738 case ISD::ATOMIC_LOAD_UMIN:
14739 Opc = X86ISD::ATOMUMIN64_DAG;
14741 case ISD::ATOMIC_SWAP:
14742 Opc = X86ISD::ATOMSWAP64_DAG;
14745 ReplaceATOMIC_BINARY_64(N, Results, DAG, Opc);
14748 case ISD::ATOMIC_LOAD: {
14749 ReplaceATOMIC_LOAD(N, Results, DAG);
14752 case ISD::BITCAST: {
14753 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
14754 EVT DstVT = N->getValueType(0);
14755 EVT SrcVT = N->getOperand(0)->getValueType(0);
14757 if (SrcVT == MVT::f64 && DstVT == MVT::v2i32) {
14758 SDValue Expanded = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
14759 MVT::v2f64, N->getOperand(0));
14760 SDValue ToV4I32 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Expanded);
14761 SDValue Elt0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
14762 ToV4I32, DAG.getIntPtrConstant(0));
14763 SDValue Elt1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
14764 ToV4I32, DAG.getIntPtrConstant(1));
14765 SDValue Elts[] = {Elt0, Elt1};
14766 Results.push_back(DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2i32, Elts));
14772 const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
14774 default: return nullptr;
14775 case X86ISD::BSF: return "X86ISD::BSF";
14776 case X86ISD::BSR: return "X86ISD::BSR";
14777 case X86ISD::SHLD: return "X86ISD::SHLD";
14778 case X86ISD::SHRD: return "X86ISD::SHRD";
14779 case X86ISD::FAND: return "X86ISD::FAND";
14780 case X86ISD::FANDN: return "X86ISD::FANDN";
14781 case X86ISD::FOR: return "X86ISD::FOR";
14782 case X86ISD::FXOR: return "X86ISD::FXOR";
14783 case X86ISD::FSRL: return "X86ISD::FSRL";
14784 case X86ISD::FILD: return "X86ISD::FILD";
14785 case X86ISD::FILD_FLAG: return "X86ISD::FILD_FLAG";
14786 case X86ISD::FP_TO_INT16_IN_MEM: return "X86ISD::FP_TO_INT16_IN_MEM";
14787 case X86ISD::FP_TO_INT32_IN_MEM: return "X86ISD::FP_TO_INT32_IN_MEM";
14788 case X86ISD::FP_TO_INT64_IN_MEM: return "X86ISD::FP_TO_INT64_IN_MEM";
14789 case X86ISD::FLD: return "X86ISD::FLD";
14790 case X86ISD::FST: return "X86ISD::FST";
14791 case X86ISD::CALL: return "X86ISD::CALL";
14792 case X86ISD::RDTSC_DAG: return "X86ISD::RDTSC_DAG";
14793 case X86ISD::BT: return "X86ISD::BT";
14794 case X86ISD::CMP: return "X86ISD::CMP";
14795 case X86ISD::COMI: return "X86ISD::COMI";
14796 case X86ISD::UCOMI: return "X86ISD::UCOMI";
14797 case X86ISD::CMPM: return "X86ISD::CMPM";
14798 case X86ISD::CMPMU: return "X86ISD::CMPMU";
14799 case X86ISD::SETCC: return "X86ISD::SETCC";
14800 case X86ISD::SETCC_CARRY: return "X86ISD::SETCC_CARRY";
14801 case X86ISD::FSETCC: return "X86ISD::FSETCC";
14802 case X86ISD::CMOV: return "X86ISD::CMOV";
14803 case X86ISD::BRCOND: return "X86ISD::BRCOND";
14804 case X86ISD::RET_FLAG: return "X86ISD::RET_FLAG";
14805 case X86ISD::REP_STOS: return "X86ISD::REP_STOS";
14806 case X86ISD::REP_MOVS: return "X86ISD::REP_MOVS";
14807 case X86ISD::GlobalBaseReg: return "X86ISD::GlobalBaseReg";
14808 case X86ISD::Wrapper: return "X86ISD::Wrapper";
14809 case X86ISD::WrapperRIP: return "X86ISD::WrapperRIP";
14810 case X86ISD::PEXTRB: return "X86ISD::PEXTRB";
14811 case X86ISD::PEXTRW: return "X86ISD::PEXTRW";
14812 case X86ISD::INSERTPS: return "X86ISD::INSERTPS";
14813 case X86ISD::PINSRB: return "X86ISD::PINSRB";
14814 case X86ISD::PINSRW: return "X86ISD::PINSRW";
14815 case X86ISD::PSHUFB: return "X86ISD::PSHUFB";
14816 case X86ISD::ANDNP: return "X86ISD::ANDNP";
14817 case X86ISD::PSIGN: return "X86ISD::PSIGN";
14818 case X86ISD::BLENDV: return "X86ISD::BLENDV";
14819 case X86ISD::BLENDI: return "X86ISD::BLENDI";
14820 case X86ISD::SUBUS: return "X86ISD::SUBUS";
14821 case X86ISD::HADD: return "X86ISD::HADD";
14822 case X86ISD::HSUB: return "X86ISD::HSUB";
14823 case X86ISD::FHADD: return "X86ISD::FHADD";
14824 case X86ISD::FHSUB: return "X86ISD::FHSUB";
14825 case X86ISD::UMAX: return "X86ISD::UMAX";
14826 case X86ISD::UMIN: return "X86ISD::UMIN";
14827 case X86ISD::SMAX: return "X86ISD::SMAX";
14828 case X86ISD::SMIN: return "X86ISD::SMIN";
14829 case X86ISD::FMAX: return "X86ISD::FMAX";
14830 case X86ISD::FMIN: return "X86ISD::FMIN";
14831 case X86ISD::FMAXC: return "X86ISD::FMAXC";
14832 case X86ISD::FMINC: return "X86ISD::FMINC";
14833 case X86ISD::FRSQRT: return "X86ISD::FRSQRT";
14834 case X86ISD::FRCP: return "X86ISD::FRCP";
14835 case X86ISD::TLSADDR: return "X86ISD::TLSADDR";
14836 case X86ISD::TLSBASEADDR: return "X86ISD::TLSBASEADDR";
14837 case X86ISD::TLSCALL: return "X86ISD::TLSCALL";
14838 case X86ISD::EH_SJLJ_SETJMP: return "X86ISD::EH_SJLJ_SETJMP";
14839 case X86ISD::EH_SJLJ_LONGJMP: return "X86ISD::EH_SJLJ_LONGJMP";
14840 case X86ISD::EH_RETURN: return "X86ISD::EH_RETURN";
14841 case X86ISD::TC_RETURN: return "X86ISD::TC_RETURN";
14842 case X86ISD::FNSTCW16m: return "X86ISD::FNSTCW16m";
14843 case X86ISD::FNSTSW16r: return "X86ISD::FNSTSW16r";
14844 case X86ISD::LCMPXCHG_DAG: return "X86ISD::LCMPXCHG_DAG";
14845 case X86ISD::LCMPXCHG8_DAG: return "X86ISD::LCMPXCHG8_DAG";
14846 case X86ISD::ATOMADD64_DAG: return "X86ISD::ATOMADD64_DAG";
14847 case X86ISD::ATOMSUB64_DAG: return "X86ISD::ATOMSUB64_DAG";
14848 case X86ISD::ATOMOR64_DAG: return "X86ISD::ATOMOR64_DAG";
14849 case X86ISD::ATOMXOR64_DAG: return "X86ISD::ATOMXOR64_DAG";
14850 case X86ISD::ATOMAND64_DAG: return "X86ISD::ATOMAND64_DAG";
14851 case X86ISD::ATOMNAND64_DAG: return "X86ISD::ATOMNAND64_DAG";
14852 case X86ISD::VZEXT_MOVL: return "X86ISD::VZEXT_MOVL";
14853 case X86ISD::VZEXT_LOAD: return "X86ISD::VZEXT_LOAD";
14854 case X86ISD::VZEXT: return "X86ISD::VZEXT";
14855 case X86ISD::VSEXT: return "X86ISD::VSEXT";
14856 case X86ISD::VTRUNC: return "X86ISD::VTRUNC";
14857 case X86ISD::VTRUNCM: return "X86ISD::VTRUNCM";
14858 case X86ISD::VINSERT: return "X86ISD::VINSERT";
14859 case X86ISD::VFPEXT: return "X86ISD::VFPEXT";
14860 case X86ISD::VFPROUND: return "X86ISD::VFPROUND";
14861 case X86ISD::VSHLDQ: return "X86ISD::VSHLDQ";
14862 case X86ISD::VSRLDQ: return "X86ISD::VSRLDQ";
14863 case X86ISD::VSHL: return "X86ISD::VSHL";
14864 case X86ISD::VSRL: return "X86ISD::VSRL";
14865 case X86ISD::VSRA: return "X86ISD::VSRA";
14866 case X86ISD::VSHLI: return "X86ISD::VSHLI";
14867 case X86ISD::VSRLI: return "X86ISD::VSRLI";
14868 case X86ISD::VSRAI: return "X86ISD::VSRAI";
14869 case X86ISD::CMPP: return "X86ISD::CMPP";
14870 case X86ISD::PCMPEQ: return "X86ISD::PCMPEQ";
14871 case X86ISD::PCMPGT: return "X86ISD::PCMPGT";
14872 case X86ISD::PCMPEQM: return "X86ISD::PCMPEQM";
14873 case X86ISD::PCMPGTM: return "X86ISD::PCMPGTM";
14874 case X86ISD::ADD: return "X86ISD::ADD";
14875 case X86ISD::SUB: return "X86ISD::SUB";
14876 case X86ISD::ADC: return "X86ISD::ADC";
14877 case X86ISD::SBB: return "X86ISD::SBB";
14878 case X86ISD::SMUL: return "X86ISD::SMUL";
14879 case X86ISD::UMUL: return "X86ISD::UMUL";
14880 case X86ISD::INC: return "X86ISD::INC";
14881 case X86ISD::DEC: return "X86ISD::DEC";
14882 case X86ISD::OR: return "X86ISD::OR";
14883 case X86ISD::XOR: return "X86ISD::XOR";
14884 case X86ISD::AND: return "X86ISD::AND";
14885 case X86ISD::BEXTR: return "X86ISD::BEXTR";
14886 case X86ISD::MUL_IMM: return "X86ISD::MUL_IMM";
14887 case X86ISD::PTEST: return "X86ISD::PTEST";
14888 case X86ISD::TESTP: return "X86ISD::TESTP";
14889 case X86ISD::TESTM: return "X86ISD::TESTM";
14890 case X86ISD::TESTNM: return "X86ISD::TESTNM";
14891 case X86ISD::KORTEST: return "X86ISD::KORTEST";
14892 case X86ISD::PALIGNR: return "X86ISD::PALIGNR";
14893 case X86ISD::PSHUFD: return "X86ISD::PSHUFD";
14894 case X86ISD::PSHUFHW: return "X86ISD::PSHUFHW";
14895 case X86ISD::PSHUFLW: return "X86ISD::PSHUFLW";
14896 case X86ISD::SHUFP: return "X86ISD::SHUFP";
14897 case X86ISD::MOVLHPS: return "X86ISD::MOVLHPS";
14898 case X86ISD::MOVLHPD: return "X86ISD::MOVLHPD";
14899 case X86ISD::MOVHLPS: return "X86ISD::MOVHLPS";
14900 case X86ISD::MOVLPS: return "X86ISD::MOVLPS";
14901 case X86ISD::MOVLPD: return "X86ISD::MOVLPD";
14902 case X86ISD::MOVDDUP: return "X86ISD::MOVDDUP";
14903 case X86ISD::MOVSHDUP: return "X86ISD::MOVSHDUP";
14904 case X86ISD::MOVSLDUP: return "X86ISD::MOVSLDUP";
14905 case X86ISD::MOVSD: return "X86ISD::MOVSD";
14906 case X86ISD::MOVSS: return "X86ISD::MOVSS";
14907 case X86ISD::UNPCKL: return "X86ISD::UNPCKL";
14908 case X86ISD::UNPCKH: return "X86ISD::UNPCKH";
14909 case X86ISD::VBROADCAST: return "X86ISD::VBROADCAST";
14910 case X86ISD::VBROADCASTM: return "X86ISD::VBROADCASTM";
14911 case X86ISD::VEXTRACT: return "X86ISD::VEXTRACT";
14912 case X86ISD::VPERMILP: return "X86ISD::VPERMILP";
14913 case X86ISD::VPERM2X128: return "X86ISD::VPERM2X128";
14914 case X86ISD::VPERMV: return "X86ISD::VPERMV";
14915 case X86ISD::VPERMV3: return "X86ISD::VPERMV3";
14916 case X86ISD::VPERMIV3: return "X86ISD::VPERMIV3";
14917 case X86ISD::VPERMI: return "X86ISD::VPERMI";
14918 case X86ISD::PMULUDQ: return "X86ISD::PMULUDQ";
14919 case X86ISD::PMULDQ: return "X86ISD::PMULDQ";
14920 case X86ISD::VASTART_SAVE_XMM_REGS: return "X86ISD::VASTART_SAVE_XMM_REGS";
14921 case X86ISD::VAARG_64: return "X86ISD::VAARG_64";
14922 case X86ISD::WIN_ALLOCA: return "X86ISD::WIN_ALLOCA";
14923 case X86ISD::MEMBARRIER: return "X86ISD::MEMBARRIER";
14924 case X86ISD::SEG_ALLOCA: return "X86ISD::SEG_ALLOCA";
14925 case X86ISD::WIN_FTOL: return "X86ISD::WIN_FTOL";
14926 case X86ISD::SAHF: return "X86ISD::SAHF";
14927 case X86ISD::RDRAND: return "X86ISD::RDRAND";
14928 case X86ISD::RDSEED: return "X86ISD::RDSEED";
14929 case X86ISD::FMADD: return "X86ISD::FMADD";
14930 case X86ISD::FMSUB: return "X86ISD::FMSUB";
14931 case X86ISD::FNMADD: return "X86ISD::FNMADD";
14932 case X86ISD::FNMSUB: return "X86ISD::FNMSUB";
14933 case X86ISD::FMADDSUB: return "X86ISD::FMADDSUB";
14934 case X86ISD::FMSUBADD: return "X86ISD::FMSUBADD";
14935 case X86ISD::PCMPESTRI: return "X86ISD::PCMPESTRI";
14936 case X86ISD::PCMPISTRI: return "X86ISD::PCMPISTRI";
14937 case X86ISD::XTEST: return "X86ISD::XTEST";
14941 // isLegalAddressingMode - Return true if the addressing mode represented
14942 // by AM is legal for this target, for a load/store of the specified type.
14943 bool X86TargetLowering::isLegalAddressingMode(const AddrMode &AM,
14945 // X86 supports extremely general addressing modes.
14946 CodeModel::Model M = getTargetMachine().getCodeModel();
14947 Reloc::Model R = getTargetMachine().getRelocationModel();
14949 // X86 allows a sign-extended 32-bit immediate field as a displacement.
14950 if (!X86::isOffsetSuitableForCodeModel(AM.BaseOffs, M, AM.BaseGV != nullptr))
14955 Subtarget->ClassifyGlobalReference(AM.BaseGV, getTargetMachine());
14957 // If a reference to this global requires an extra load, we can't fold it.
14958 if (isGlobalStubReference(GVFlags))
14961 // If BaseGV requires a register for the PIC base, we cannot also have a
14962 // BaseReg specified.
14963 if (AM.HasBaseReg && isGlobalRelativeToPICBase(GVFlags))
14966 // If lower 4G is not available, then we must use rip-relative addressing.
14967 if ((M != CodeModel::Small || R != Reloc::Static) &&
14968 Subtarget->is64Bit() && (AM.BaseOffs || AM.Scale > 1))
14972 switch (AM.Scale) {
14978 // These scales always work.
14983 // These scales are formed with basereg+scalereg. Only accept if there is
14988 default: // Other stuff never works.
14995 bool X86TargetLowering::isVectorShiftByScalarCheap(Type *Ty) const {
14996 unsigned Bits = Ty->getScalarSizeInBits();
14998 // 8-bit shifts are always expensive, but versions with a scalar amount aren't
14999 // particularly cheaper than those without.
15003 // On AVX2 there are new vpsllv[dq] instructions (and other shifts), that make
15004 // variable shifts just as cheap as scalar ones.
15005 if (Subtarget->hasInt256() && (Bits == 32 || Bits == 64))
15008 // Otherwise, it's significantly cheaper to shift by a scalar amount than by a
15009 // fully general vector.
15013 bool X86TargetLowering::isTruncateFree(Type *Ty1, Type *Ty2) const {
15014 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
15016 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits();
15017 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits();
15018 return NumBits1 > NumBits2;
15021 bool X86TargetLowering::allowTruncateForTailCall(Type *Ty1, Type *Ty2) const {
15022 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
15025 if (!isTypeLegal(EVT::getEVT(Ty1)))
15028 assert(Ty1->getPrimitiveSizeInBits() <= 64 && "i128 is probably not a noop");
15030 // Assuming the caller doesn't have a zeroext or signext return parameter,
15031 // truncation all the way down to i1 is valid.
15035 bool X86TargetLowering::isLegalICmpImmediate(int64_t Imm) const {
15036 return isInt<32>(Imm);
15039 bool X86TargetLowering::isLegalAddImmediate(int64_t Imm) const {
15040 // Can also use sub to handle negated immediates.
15041 return isInt<32>(Imm);
15044 bool X86TargetLowering::isTruncateFree(EVT VT1, EVT VT2) const {
15045 if (!VT1.isInteger() || !VT2.isInteger())
15047 unsigned NumBits1 = VT1.getSizeInBits();
15048 unsigned NumBits2 = VT2.getSizeInBits();
15049 return NumBits1 > NumBits2;
15052 bool X86TargetLowering::isZExtFree(Type *Ty1, Type *Ty2) const {
15053 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
15054 return Ty1->isIntegerTy(32) && Ty2->isIntegerTy(64) && Subtarget->is64Bit();
15057 bool X86TargetLowering::isZExtFree(EVT VT1, EVT VT2) const {
15058 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
15059 return VT1 == MVT::i32 && VT2 == MVT::i64 && Subtarget->is64Bit();
15062 bool X86TargetLowering::isZExtFree(SDValue Val, EVT VT2) const {
15063 EVT VT1 = Val.getValueType();
15064 if (isZExtFree(VT1, VT2))
15067 if (Val.getOpcode() != ISD::LOAD)
15070 if (!VT1.isSimple() || !VT1.isInteger() ||
15071 !VT2.isSimple() || !VT2.isInteger())
15074 switch (VT1.getSimpleVT().SimpleTy) {
15079 // X86 has 8, 16, and 32-bit zero-extending loads.
15087 X86TargetLowering::isFMAFasterThanFMulAndFAdd(EVT VT) const {
15088 if (!(Subtarget->hasFMA() || Subtarget->hasFMA4()))
15091 VT = VT.getScalarType();
15093 if (!VT.isSimple())
15096 switch (VT.getSimpleVT().SimpleTy) {
15107 bool X86TargetLowering::isNarrowingProfitable(EVT VT1, EVT VT2) const {
15108 // i16 instructions are longer (0x66 prefix) and potentially slower.
15109 return !(VT1 == MVT::i32 && VT2 == MVT::i16);
15112 /// isShuffleMaskLegal - Targets can use this to indicate that they only
15113 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
15114 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
15115 /// are assumed to be legal.
15117 X86TargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M,
15119 if (!VT.isSimple())
15122 MVT SVT = VT.getSimpleVT();
15124 // Very little shuffling can be done for 64-bit vectors right now.
15125 if (VT.getSizeInBits() == 64)
15128 // If this is a single-input shuffle with no 128 bit lane crossings we can
15129 // lower it into pshufb.
15130 if ((SVT.is128BitVector() && Subtarget->hasSSSE3()) ||
15131 (SVT.is256BitVector() && Subtarget->hasInt256())) {
15132 bool isLegal = true;
15133 for (unsigned I = 0, E = M.size(); I != E; ++I) {
15134 if (M[I] >= (int)SVT.getVectorNumElements() ||
15135 ShuffleCrosses128bitLane(SVT, I, M[I])) {
15144 // FIXME: blends, shifts.
15145 return (SVT.getVectorNumElements() == 2 ||
15146 ShuffleVectorSDNode::isSplatMask(&M[0], VT) ||
15147 isMOVLMask(M, SVT) ||
15148 isSHUFPMask(M, SVT) ||
15149 isPSHUFDMask(M, SVT) ||
15150 isPSHUFHWMask(M, SVT, Subtarget->hasInt256()) ||
15151 isPSHUFLWMask(M, SVT, Subtarget->hasInt256()) ||
15152 isPALIGNRMask(M, SVT, Subtarget) ||
15153 isUNPCKLMask(M, SVT, Subtarget->hasInt256()) ||
15154 isUNPCKHMask(M, SVT, Subtarget->hasInt256()) ||
15155 isUNPCKL_v_undef_Mask(M, SVT, Subtarget->hasInt256()) ||
15156 isUNPCKH_v_undef_Mask(M, SVT, Subtarget->hasInt256()));
15160 X86TargetLowering::isVectorClearMaskLegal(const SmallVectorImpl<int> &Mask,
15162 if (!VT.isSimple())
15165 MVT SVT = VT.getSimpleVT();
15166 unsigned NumElts = SVT.getVectorNumElements();
15167 // FIXME: This collection of masks seems suspect.
15170 if (NumElts == 4 && SVT.is128BitVector()) {
15171 return (isMOVLMask(Mask, SVT) ||
15172 isCommutedMOVLMask(Mask, SVT, true) ||
15173 isSHUFPMask(Mask, SVT) ||
15174 isSHUFPMask(Mask, SVT, /* Commuted */ true));
15179 //===----------------------------------------------------------------------===//
15180 // X86 Scheduler Hooks
15181 //===----------------------------------------------------------------------===//
15183 /// Utility function to emit xbegin specifying the start of an RTM region.
15184 static MachineBasicBlock *EmitXBegin(MachineInstr *MI, MachineBasicBlock *MBB,
15185 const TargetInstrInfo *TII) {
15186 DebugLoc DL = MI->getDebugLoc();
15188 const BasicBlock *BB = MBB->getBasicBlock();
15189 MachineFunction::iterator I = MBB;
15192 // For the v = xbegin(), we generate
15203 MachineBasicBlock *thisMBB = MBB;
15204 MachineFunction *MF = MBB->getParent();
15205 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
15206 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
15207 MF->insert(I, mainMBB);
15208 MF->insert(I, sinkMBB);
15210 // Transfer the remainder of BB and its successor edges to sinkMBB.
15211 sinkMBB->splice(sinkMBB->begin(), MBB,
15212 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
15213 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
15217 // # fallthrough to mainMBB
15218 // # abortion to sinkMBB
15219 BuildMI(thisMBB, DL, TII->get(X86::XBEGIN_4)).addMBB(sinkMBB);
15220 thisMBB->addSuccessor(mainMBB);
15221 thisMBB->addSuccessor(sinkMBB);
15225 BuildMI(mainMBB, DL, TII->get(X86::MOV32ri), X86::EAX).addImm(-1);
15226 mainMBB->addSuccessor(sinkMBB);
15229 // EAX is live into the sinkMBB
15230 sinkMBB->addLiveIn(X86::EAX);
15231 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
15232 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
15235 MI->eraseFromParent();
15239 // Get CMPXCHG opcode for the specified data type.
15240 static unsigned getCmpXChgOpcode(EVT VT) {
15241 switch (VT.getSimpleVT().SimpleTy) {
15242 case MVT::i8: return X86::LCMPXCHG8;
15243 case MVT::i16: return X86::LCMPXCHG16;
15244 case MVT::i32: return X86::LCMPXCHG32;
15245 case MVT::i64: return X86::LCMPXCHG64;
15249 llvm_unreachable("Invalid operand size!");
15252 // Get LOAD opcode for the specified data type.
15253 static unsigned getLoadOpcode(EVT VT) {
15254 switch (VT.getSimpleVT().SimpleTy) {
15255 case MVT::i8: return X86::MOV8rm;
15256 case MVT::i16: return X86::MOV16rm;
15257 case MVT::i32: return X86::MOV32rm;
15258 case MVT::i64: return X86::MOV64rm;
15262 llvm_unreachable("Invalid operand size!");
15265 // Get opcode of the non-atomic one from the specified atomic instruction.
15266 static unsigned getNonAtomicOpcode(unsigned Opc) {
15268 case X86::ATOMAND8: return X86::AND8rr;
15269 case X86::ATOMAND16: return X86::AND16rr;
15270 case X86::ATOMAND32: return X86::AND32rr;
15271 case X86::ATOMAND64: return X86::AND64rr;
15272 case X86::ATOMOR8: return X86::OR8rr;
15273 case X86::ATOMOR16: return X86::OR16rr;
15274 case X86::ATOMOR32: return X86::OR32rr;
15275 case X86::ATOMOR64: return X86::OR64rr;
15276 case X86::ATOMXOR8: return X86::XOR8rr;
15277 case X86::ATOMXOR16: return X86::XOR16rr;
15278 case X86::ATOMXOR32: return X86::XOR32rr;
15279 case X86::ATOMXOR64: return X86::XOR64rr;
15281 llvm_unreachable("Unhandled atomic-load-op opcode!");
15284 // Get opcode of the non-atomic one from the specified atomic instruction with
15286 static unsigned getNonAtomicOpcodeWithExtraOpc(unsigned Opc,
15287 unsigned &ExtraOpc) {
15289 case X86::ATOMNAND8: ExtraOpc = X86::NOT8r; return X86::AND8rr;
15290 case X86::ATOMNAND16: ExtraOpc = X86::NOT16r; return X86::AND16rr;
15291 case X86::ATOMNAND32: ExtraOpc = X86::NOT32r; return X86::AND32rr;
15292 case X86::ATOMNAND64: ExtraOpc = X86::NOT64r; return X86::AND64rr;
15293 case X86::ATOMMAX8: ExtraOpc = X86::CMP8rr; return X86::CMOVL32rr;
15294 case X86::ATOMMAX16: ExtraOpc = X86::CMP16rr; return X86::CMOVL16rr;
15295 case X86::ATOMMAX32: ExtraOpc = X86::CMP32rr; return X86::CMOVL32rr;
15296 case X86::ATOMMAX64: ExtraOpc = X86::CMP64rr; return X86::CMOVL64rr;
15297 case X86::ATOMMIN8: ExtraOpc = X86::CMP8rr; return X86::CMOVG32rr;
15298 case X86::ATOMMIN16: ExtraOpc = X86::CMP16rr; return X86::CMOVG16rr;
15299 case X86::ATOMMIN32: ExtraOpc = X86::CMP32rr; return X86::CMOVG32rr;
15300 case X86::ATOMMIN64: ExtraOpc = X86::CMP64rr; return X86::CMOVG64rr;
15301 case X86::ATOMUMAX8: ExtraOpc = X86::CMP8rr; return X86::CMOVB32rr;
15302 case X86::ATOMUMAX16: ExtraOpc = X86::CMP16rr; return X86::CMOVB16rr;
15303 case X86::ATOMUMAX32: ExtraOpc = X86::CMP32rr; return X86::CMOVB32rr;
15304 case X86::ATOMUMAX64: ExtraOpc = X86::CMP64rr; return X86::CMOVB64rr;
15305 case X86::ATOMUMIN8: ExtraOpc = X86::CMP8rr; return X86::CMOVA32rr;
15306 case X86::ATOMUMIN16: ExtraOpc = X86::CMP16rr; return X86::CMOVA16rr;
15307 case X86::ATOMUMIN32: ExtraOpc = X86::CMP32rr; return X86::CMOVA32rr;
15308 case X86::ATOMUMIN64: ExtraOpc = X86::CMP64rr; return X86::CMOVA64rr;
15310 llvm_unreachable("Unhandled atomic-load-op opcode!");
15313 // Get opcode of the non-atomic one from the specified atomic instruction for
15314 // 64-bit data type on 32-bit target.
15315 static unsigned getNonAtomic6432Opcode(unsigned Opc, unsigned &HiOpc) {
15317 case X86::ATOMAND6432: HiOpc = X86::AND32rr; return X86::AND32rr;
15318 case X86::ATOMOR6432: HiOpc = X86::OR32rr; return X86::OR32rr;
15319 case X86::ATOMXOR6432: HiOpc = X86::XOR32rr; return X86::XOR32rr;
15320 case X86::ATOMADD6432: HiOpc = X86::ADC32rr; return X86::ADD32rr;
15321 case X86::ATOMSUB6432: HiOpc = X86::SBB32rr; return X86::SUB32rr;
15322 case X86::ATOMSWAP6432: HiOpc = X86::MOV32rr; return X86::MOV32rr;
15323 case X86::ATOMMAX6432: HiOpc = X86::SETLr; return X86::SETLr;
15324 case X86::ATOMMIN6432: HiOpc = X86::SETGr; return X86::SETGr;
15325 case X86::ATOMUMAX6432: HiOpc = X86::SETBr; return X86::SETBr;
15326 case X86::ATOMUMIN6432: HiOpc = X86::SETAr; return X86::SETAr;
15328 llvm_unreachable("Unhandled atomic-load-op opcode!");
15331 // Get opcode of the non-atomic one from the specified atomic instruction for
15332 // 64-bit data type on 32-bit target with extra opcode.
15333 static unsigned getNonAtomic6432OpcodeWithExtraOpc(unsigned Opc,
15335 unsigned &ExtraOpc) {
15337 case X86::ATOMNAND6432:
15338 ExtraOpc = X86::NOT32r;
15339 HiOpc = X86::AND32rr;
15340 return X86::AND32rr;
15342 llvm_unreachable("Unhandled atomic-load-op opcode!");
15345 // Get pseudo CMOV opcode from the specified data type.
15346 static unsigned getPseudoCMOVOpc(EVT VT) {
15347 switch (VT.getSimpleVT().SimpleTy) {
15348 case MVT::i8: return X86::CMOV_GR8;
15349 case MVT::i16: return X86::CMOV_GR16;
15350 case MVT::i32: return X86::CMOV_GR32;
15354 llvm_unreachable("Unknown CMOV opcode!");
15357 // EmitAtomicLoadArith - emit the code sequence for pseudo atomic instructions.
15358 // They will be translated into a spin-loop or compare-exchange loop from
15361 // dst = atomic-fetch-op MI.addr, MI.val
15367 // t1 = LOAD MI.addr
15369 // t4 = phi(t1, t3 / loop)
15370 // t2 = OP MI.val, t4
15372 // LCMPXCHG [MI.addr], t2, [EAX is implicitly used & defined]
15378 MachineBasicBlock *
15379 X86TargetLowering::EmitAtomicLoadArith(MachineInstr *MI,
15380 MachineBasicBlock *MBB) const {
15381 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
15382 DebugLoc DL = MI->getDebugLoc();
15384 MachineFunction *MF = MBB->getParent();
15385 MachineRegisterInfo &MRI = MF->getRegInfo();
15387 const BasicBlock *BB = MBB->getBasicBlock();
15388 MachineFunction::iterator I = MBB;
15391 assert(MI->getNumOperands() <= X86::AddrNumOperands + 4 &&
15392 "Unexpected number of operands");
15394 assert(MI->hasOneMemOperand() &&
15395 "Expected atomic-load-op to have one memoperand");
15397 // Memory Reference
15398 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
15399 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
15401 unsigned DstReg, SrcReg;
15402 unsigned MemOpndSlot;
15404 unsigned CurOp = 0;
15406 DstReg = MI->getOperand(CurOp++).getReg();
15407 MemOpndSlot = CurOp;
15408 CurOp += X86::AddrNumOperands;
15409 SrcReg = MI->getOperand(CurOp++).getReg();
15411 const TargetRegisterClass *RC = MRI.getRegClass(DstReg);
15412 MVT::SimpleValueType VT = *RC->vt_begin();
15413 unsigned t1 = MRI.createVirtualRegister(RC);
15414 unsigned t2 = MRI.createVirtualRegister(RC);
15415 unsigned t3 = MRI.createVirtualRegister(RC);
15416 unsigned t4 = MRI.createVirtualRegister(RC);
15417 unsigned PhyReg = getX86SubSuperRegister(X86::EAX, VT);
15419 unsigned LCMPXCHGOpc = getCmpXChgOpcode(VT);
15420 unsigned LOADOpc = getLoadOpcode(VT);
15422 // For the atomic load-arith operator, we generate
15425 // t1 = LOAD [MI.addr]
15427 // t4 = phi(t1 / thisMBB, t3 / mainMBB)
15428 // t1 = OP MI.val, EAX
15430 // LCMPXCHG [MI.addr], t1, [EAX is implicitly used & defined]
15436 MachineBasicBlock *thisMBB = MBB;
15437 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
15438 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
15439 MF->insert(I, mainMBB);
15440 MF->insert(I, sinkMBB);
15442 MachineInstrBuilder MIB;
15444 // Transfer the remainder of BB and its successor edges to sinkMBB.
15445 sinkMBB->splice(sinkMBB->begin(), MBB,
15446 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
15447 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
15450 MIB = BuildMI(thisMBB, DL, TII->get(LOADOpc), t1);
15451 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
15452 MachineOperand NewMO = MI->getOperand(MemOpndSlot + i);
15454 NewMO.setIsKill(false);
15455 MIB.addOperand(NewMO);
15457 for (MachineInstr::mmo_iterator MMOI = MMOBegin; MMOI != MMOEnd; ++MMOI) {
15458 unsigned flags = (*MMOI)->getFlags();
15459 flags = (flags & ~MachineMemOperand::MOStore) | MachineMemOperand::MOLoad;
15460 MachineMemOperand *MMO =
15461 MF->getMachineMemOperand((*MMOI)->getPointerInfo(), flags,
15462 (*MMOI)->getSize(),
15463 (*MMOI)->getBaseAlignment(),
15464 (*MMOI)->getTBAAInfo(),
15465 (*MMOI)->getRanges());
15466 MIB.addMemOperand(MMO);
15469 thisMBB->addSuccessor(mainMBB);
15472 MachineBasicBlock *origMainMBB = mainMBB;
15475 MachineInstr *Phi = BuildMI(mainMBB, DL, TII->get(X86::PHI), t4)
15476 .addReg(t1).addMBB(thisMBB).addReg(t3).addMBB(mainMBB);
15478 unsigned Opc = MI->getOpcode();
15481 llvm_unreachable("Unhandled atomic-load-op opcode!");
15482 case X86::ATOMAND8:
15483 case X86::ATOMAND16:
15484 case X86::ATOMAND32:
15485 case X86::ATOMAND64:
15487 case X86::ATOMOR16:
15488 case X86::ATOMOR32:
15489 case X86::ATOMOR64:
15490 case X86::ATOMXOR8:
15491 case X86::ATOMXOR16:
15492 case X86::ATOMXOR32:
15493 case X86::ATOMXOR64: {
15494 unsigned ARITHOpc = getNonAtomicOpcode(Opc);
15495 BuildMI(mainMBB, DL, TII->get(ARITHOpc), t2).addReg(SrcReg)
15499 case X86::ATOMNAND8:
15500 case X86::ATOMNAND16:
15501 case X86::ATOMNAND32:
15502 case X86::ATOMNAND64: {
15503 unsigned Tmp = MRI.createVirtualRegister(RC);
15505 unsigned ANDOpc = getNonAtomicOpcodeWithExtraOpc(Opc, NOTOpc);
15506 BuildMI(mainMBB, DL, TII->get(ANDOpc), Tmp).addReg(SrcReg)
15508 BuildMI(mainMBB, DL, TII->get(NOTOpc), t2).addReg(Tmp);
15511 case X86::ATOMMAX8:
15512 case X86::ATOMMAX16:
15513 case X86::ATOMMAX32:
15514 case X86::ATOMMAX64:
15515 case X86::ATOMMIN8:
15516 case X86::ATOMMIN16:
15517 case X86::ATOMMIN32:
15518 case X86::ATOMMIN64:
15519 case X86::ATOMUMAX8:
15520 case X86::ATOMUMAX16:
15521 case X86::ATOMUMAX32:
15522 case X86::ATOMUMAX64:
15523 case X86::ATOMUMIN8:
15524 case X86::ATOMUMIN16:
15525 case X86::ATOMUMIN32:
15526 case X86::ATOMUMIN64: {
15528 unsigned CMOVOpc = getNonAtomicOpcodeWithExtraOpc(Opc, CMPOpc);
15530 BuildMI(mainMBB, DL, TII->get(CMPOpc))
15534 if (Subtarget->hasCMov()) {
15535 if (VT != MVT::i8) {
15537 BuildMI(mainMBB, DL, TII->get(CMOVOpc), t2)
15541 // Promote i8 to i32 to use CMOV32
15542 const TargetRegisterInfo* TRI = getTargetMachine().getRegisterInfo();
15543 const TargetRegisterClass *RC32 =
15544 TRI->getSubClassWithSubReg(getRegClassFor(MVT::i32), X86::sub_8bit);
15545 unsigned SrcReg32 = MRI.createVirtualRegister(RC32);
15546 unsigned AccReg32 = MRI.createVirtualRegister(RC32);
15547 unsigned Tmp = MRI.createVirtualRegister(RC32);
15549 unsigned Undef = MRI.createVirtualRegister(RC32);
15550 BuildMI(mainMBB, DL, TII->get(TargetOpcode::IMPLICIT_DEF), Undef);
15552 BuildMI(mainMBB, DL, TII->get(TargetOpcode::INSERT_SUBREG), SrcReg32)
15555 .addImm(X86::sub_8bit);
15556 BuildMI(mainMBB, DL, TII->get(TargetOpcode::INSERT_SUBREG), AccReg32)
15559 .addImm(X86::sub_8bit);
15561 BuildMI(mainMBB, DL, TII->get(CMOVOpc), Tmp)
15565 BuildMI(mainMBB, DL, TII->get(TargetOpcode::COPY), t2)
15566 .addReg(Tmp, 0, X86::sub_8bit);
15569 // Use pseudo select and lower them.
15570 assert((VT == MVT::i8 || VT == MVT::i16 || VT == MVT::i32) &&
15571 "Invalid atomic-load-op transformation!");
15572 unsigned SelOpc = getPseudoCMOVOpc(VT);
15573 X86::CondCode CC = X86::getCondFromCMovOpc(CMOVOpc);
15574 assert(CC != X86::COND_INVALID && "Invalid atomic-load-op transformation!");
15575 MIB = BuildMI(mainMBB, DL, TII->get(SelOpc), t2)
15576 .addReg(SrcReg).addReg(t4)
15578 mainMBB = EmitLoweredSelect(MIB, mainMBB);
15579 // Replace the original PHI node as mainMBB is changed after CMOV
15581 BuildMI(*origMainMBB, Phi, DL, TII->get(X86::PHI), t4)
15582 .addReg(t1).addMBB(thisMBB).addReg(t3).addMBB(mainMBB);
15583 Phi->eraseFromParent();
15589 // Copy PhyReg back from virtual register.
15590 BuildMI(mainMBB, DL, TII->get(TargetOpcode::COPY), PhyReg)
15593 MIB = BuildMI(mainMBB, DL, TII->get(LCMPXCHGOpc));
15594 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
15595 MachineOperand NewMO = MI->getOperand(MemOpndSlot + i);
15597 NewMO.setIsKill(false);
15598 MIB.addOperand(NewMO);
15601 MIB.setMemRefs(MMOBegin, MMOEnd);
15603 // Copy PhyReg back to virtual register.
15604 BuildMI(mainMBB, DL, TII->get(TargetOpcode::COPY), t3)
15607 BuildMI(mainMBB, DL, TII->get(X86::JNE_4)).addMBB(origMainMBB);
15609 mainMBB->addSuccessor(origMainMBB);
15610 mainMBB->addSuccessor(sinkMBB);
15613 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
15614 TII->get(TargetOpcode::COPY), DstReg)
15617 MI->eraseFromParent();
15621 // EmitAtomicLoadArith6432 - emit the code sequence for pseudo atomic
15622 // instructions. They will be translated into a spin-loop or compare-exchange
15626 // dst = atomic-fetch-op MI.addr, MI.val
15632 // t1L = LOAD [MI.addr + 0]
15633 // t1H = LOAD [MI.addr + 4]
15635 // t4L = phi(t1L, t3L / loop)
15636 // t4H = phi(t1H, t3H / loop)
15637 // t2L = OP MI.val.lo, t4L
15638 // t2H = OP MI.val.hi, t4H
15643 // LCMPXCHG8B [MI.addr], [ECX:EBX & EDX:EAX are implicitly used and EDX:EAX is implicitly defined]
15651 MachineBasicBlock *
15652 X86TargetLowering::EmitAtomicLoadArith6432(MachineInstr *MI,
15653 MachineBasicBlock *MBB) const {
15654 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
15655 DebugLoc DL = MI->getDebugLoc();
15657 MachineFunction *MF = MBB->getParent();
15658 MachineRegisterInfo &MRI = MF->getRegInfo();
15660 const BasicBlock *BB = MBB->getBasicBlock();
15661 MachineFunction::iterator I = MBB;
15664 assert(MI->getNumOperands() <= X86::AddrNumOperands + 7 &&
15665 "Unexpected number of operands");
15667 assert(MI->hasOneMemOperand() &&
15668 "Expected atomic-load-op32 to have one memoperand");
15670 // Memory Reference
15671 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
15672 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
15674 unsigned DstLoReg, DstHiReg;
15675 unsigned SrcLoReg, SrcHiReg;
15676 unsigned MemOpndSlot;
15678 unsigned CurOp = 0;
15680 DstLoReg = MI->getOperand(CurOp++).getReg();
15681 DstHiReg = MI->getOperand(CurOp++).getReg();
15682 MemOpndSlot = CurOp;
15683 CurOp += X86::AddrNumOperands;
15684 SrcLoReg = MI->getOperand(CurOp++).getReg();
15685 SrcHiReg = MI->getOperand(CurOp++).getReg();
15687 const TargetRegisterClass *RC = &X86::GR32RegClass;
15688 const TargetRegisterClass *RC8 = &X86::GR8RegClass;
15690 unsigned t1L = MRI.createVirtualRegister(RC);
15691 unsigned t1H = MRI.createVirtualRegister(RC);
15692 unsigned t2L = MRI.createVirtualRegister(RC);
15693 unsigned t2H = MRI.createVirtualRegister(RC);
15694 unsigned t3L = MRI.createVirtualRegister(RC);
15695 unsigned t3H = MRI.createVirtualRegister(RC);
15696 unsigned t4L = MRI.createVirtualRegister(RC);
15697 unsigned t4H = MRI.createVirtualRegister(RC);
15699 unsigned LCMPXCHGOpc = X86::LCMPXCHG8B;
15700 unsigned LOADOpc = X86::MOV32rm;
15702 // For the atomic load-arith operator, we generate
15705 // t1L = LOAD [MI.addr + 0]
15706 // t1H = LOAD [MI.addr + 4]
15708 // t4L = phi(t1L / thisMBB, t3L / mainMBB)
15709 // t4H = phi(t1H / thisMBB, t3H / mainMBB)
15710 // t2L = OP MI.val.lo, t4L
15711 // t2H = OP MI.val.hi, t4H
15714 // LCMPXCHG8B [MI.addr], [ECX:EBX & EDX:EAX are implicitly used and EDX:EAX is implicitly defined]
15722 MachineBasicBlock *thisMBB = MBB;
15723 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
15724 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
15725 MF->insert(I, mainMBB);
15726 MF->insert(I, sinkMBB);
15728 MachineInstrBuilder MIB;
15730 // Transfer the remainder of BB and its successor edges to sinkMBB.
15731 sinkMBB->splice(sinkMBB->begin(), MBB,
15732 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
15733 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
15737 MIB = BuildMI(thisMBB, DL, TII->get(LOADOpc), t1L);
15738 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
15739 MachineOperand NewMO = MI->getOperand(MemOpndSlot + i);
15741 NewMO.setIsKill(false);
15742 MIB.addOperand(NewMO);
15744 for (MachineInstr::mmo_iterator MMOI = MMOBegin; MMOI != MMOEnd; ++MMOI) {
15745 unsigned flags = (*MMOI)->getFlags();
15746 flags = (flags & ~MachineMemOperand::MOStore) | MachineMemOperand::MOLoad;
15747 MachineMemOperand *MMO =
15748 MF->getMachineMemOperand((*MMOI)->getPointerInfo(), flags,
15749 (*MMOI)->getSize(),
15750 (*MMOI)->getBaseAlignment(),
15751 (*MMOI)->getTBAAInfo(),
15752 (*MMOI)->getRanges());
15753 MIB.addMemOperand(MMO);
15755 MachineInstr *LowMI = MIB;
15758 MIB = BuildMI(thisMBB, DL, TII->get(LOADOpc), t1H);
15759 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
15760 if (i == X86::AddrDisp) {
15761 MIB.addDisp(MI->getOperand(MemOpndSlot + i), 4); // 4 == sizeof(i32)
15763 MachineOperand NewMO = MI->getOperand(MemOpndSlot + i);
15765 NewMO.setIsKill(false);
15766 MIB.addOperand(NewMO);
15769 MIB.setMemRefs(LowMI->memoperands_begin(), LowMI->memoperands_end());
15771 thisMBB->addSuccessor(mainMBB);
15774 MachineBasicBlock *origMainMBB = mainMBB;
15777 MachineInstr *PhiL = BuildMI(mainMBB, DL, TII->get(X86::PHI), t4L)
15778 .addReg(t1L).addMBB(thisMBB).addReg(t3L).addMBB(mainMBB);
15779 MachineInstr *PhiH = BuildMI(mainMBB, DL, TII->get(X86::PHI), t4H)
15780 .addReg(t1H).addMBB(thisMBB).addReg(t3H).addMBB(mainMBB);
15782 unsigned Opc = MI->getOpcode();
15785 llvm_unreachable("Unhandled atomic-load-op6432 opcode!");
15786 case X86::ATOMAND6432:
15787 case X86::ATOMOR6432:
15788 case X86::ATOMXOR6432:
15789 case X86::ATOMADD6432:
15790 case X86::ATOMSUB6432: {
15792 unsigned LoOpc = getNonAtomic6432Opcode(Opc, HiOpc);
15793 BuildMI(mainMBB, DL, TII->get(LoOpc), t2L).addReg(t4L)
15795 BuildMI(mainMBB, DL, TII->get(HiOpc), t2H).addReg(t4H)
15799 case X86::ATOMNAND6432: {
15800 unsigned HiOpc, NOTOpc;
15801 unsigned LoOpc = getNonAtomic6432OpcodeWithExtraOpc(Opc, HiOpc, NOTOpc);
15802 unsigned TmpL = MRI.createVirtualRegister(RC);
15803 unsigned TmpH = MRI.createVirtualRegister(RC);
15804 BuildMI(mainMBB, DL, TII->get(LoOpc), TmpL).addReg(SrcLoReg)
15806 BuildMI(mainMBB, DL, TII->get(HiOpc), TmpH).addReg(SrcHiReg)
15808 BuildMI(mainMBB, DL, TII->get(NOTOpc), t2L).addReg(TmpL);
15809 BuildMI(mainMBB, DL, TII->get(NOTOpc), t2H).addReg(TmpH);
15812 case X86::ATOMMAX6432:
15813 case X86::ATOMMIN6432:
15814 case X86::ATOMUMAX6432:
15815 case X86::ATOMUMIN6432: {
15817 unsigned LoOpc = getNonAtomic6432Opcode(Opc, HiOpc);
15818 unsigned cL = MRI.createVirtualRegister(RC8);
15819 unsigned cH = MRI.createVirtualRegister(RC8);
15820 unsigned cL32 = MRI.createVirtualRegister(RC);
15821 unsigned cH32 = MRI.createVirtualRegister(RC);
15822 unsigned cc = MRI.createVirtualRegister(RC);
15823 // cl := cmp src_lo, lo
15824 BuildMI(mainMBB, DL, TII->get(X86::CMP32rr))
15825 .addReg(SrcLoReg).addReg(t4L);
15826 BuildMI(mainMBB, DL, TII->get(LoOpc), cL);
15827 BuildMI(mainMBB, DL, TII->get(X86::MOVZX32rr8), cL32).addReg(cL);
15828 // ch := cmp src_hi, hi
15829 BuildMI(mainMBB, DL, TII->get(X86::CMP32rr))
15830 .addReg(SrcHiReg).addReg(t4H);
15831 BuildMI(mainMBB, DL, TII->get(HiOpc), cH);
15832 BuildMI(mainMBB, DL, TII->get(X86::MOVZX32rr8), cH32).addReg(cH);
15833 // cc := if (src_hi == hi) ? cl : ch;
15834 if (Subtarget->hasCMov()) {
15835 BuildMI(mainMBB, DL, TII->get(X86::CMOVE32rr), cc)
15836 .addReg(cH32).addReg(cL32);
15838 MIB = BuildMI(mainMBB, DL, TII->get(X86::CMOV_GR32), cc)
15839 .addReg(cH32).addReg(cL32)
15840 .addImm(X86::COND_E);
15841 mainMBB = EmitLoweredSelect(MIB, mainMBB);
15843 BuildMI(mainMBB, DL, TII->get(X86::TEST32rr)).addReg(cc).addReg(cc);
15844 if (Subtarget->hasCMov()) {
15845 BuildMI(mainMBB, DL, TII->get(X86::CMOVNE32rr), t2L)
15846 .addReg(SrcLoReg).addReg(t4L);
15847 BuildMI(mainMBB, DL, TII->get(X86::CMOVNE32rr), t2H)
15848 .addReg(SrcHiReg).addReg(t4H);
15850 MIB = BuildMI(mainMBB, DL, TII->get(X86::CMOV_GR32), t2L)
15851 .addReg(SrcLoReg).addReg(t4L)
15852 .addImm(X86::COND_NE);
15853 mainMBB = EmitLoweredSelect(MIB, mainMBB);
15854 // As the lowered CMOV won't clobber EFLAGS, we could reuse it for the
15855 // 2nd CMOV lowering.
15856 mainMBB->addLiveIn(X86::EFLAGS);
15857 MIB = BuildMI(mainMBB, DL, TII->get(X86::CMOV_GR32), t2H)
15858 .addReg(SrcHiReg).addReg(t4H)
15859 .addImm(X86::COND_NE);
15860 mainMBB = EmitLoweredSelect(MIB, mainMBB);
15861 // Replace the original PHI node as mainMBB is changed after CMOV
15863 BuildMI(*origMainMBB, PhiL, DL, TII->get(X86::PHI), t4L)
15864 .addReg(t1L).addMBB(thisMBB).addReg(t3L).addMBB(mainMBB);
15865 BuildMI(*origMainMBB, PhiH, DL, TII->get(X86::PHI), t4H)
15866 .addReg(t1H).addMBB(thisMBB).addReg(t3H).addMBB(mainMBB);
15867 PhiL->eraseFromParent();
15868 PhiH->eraseFromParent();
15872 case X86::ATOMSWAP6432: {
15874 unsigned LoOpc = getNonAtomic6432Opcode(Opc, HiOpc);
15875 BuildMI(mainMBB, DL, TII->get(LoOpc), t2L).addReg(SrcLoReg);
15876 BuildMI(mainMBB, DL, TII->get(HiOpc), t2H).addReg(SrcHiReg);
15881 // Copy EDX:EAX back from HiReg:LoReg
15882 BuildMI(mainMBB, DL, TII->get(TargetOpcode::COPY), X86::EAX).addReg(t4L);
15883 BuildMI(mainMBB, DL, TII->get(TargetOpcode::COPY), X86::EDX).addReg(t4H);
15884 // Copy ECX:EBX from t1H:t1L
15885 BuildMI(mainMBB, DL, TII->get(TargetOpcode::COPY), X86::EBX).addReg(t2L);
15886 BuildMI(mainMBB, DL, TII->get(TargetOpcode::COPY), X86::ECX).addReg(t2H);
15888 MIB = BuildMI(mainMBB, DL, TII->get(LCMPXCHGOpc));
15889 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
15890 MachineOperand NewMO = MI->getOperand(MemOpndSlot + i);
15892 NewMO.setIsKill(false);
15893 MIB.addOperand(NewMO);
15895 MIB.setMemRefs(MMOBegin, MMOEnd);
15897 // Copy EDX:EAX back to t3H:t3L
15898 BuildMI(mainMBB, DL, TII->get(TargetOpcode::COPY), t3L).addReg(X86::EAX);
15899 BuildMI(mainMBB, DL, TII->get(TargetOpcode::COPY), t3H).addReg(X86::EDX);
15901 BuildMI(mainMBB, DL, TII->get(X86::JNE_4)).addMBB(origMainMBB);
15903 mainMBB->addSuccessor(origMainMBB);
15904 mainMBB->addSuccessor(sinkMBB);
15907 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
15908 TII->get(TargetOpcode::COPY), DstLoReg)
15910 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
15911 TII->get(TargetOpcode::COPY), DstHiReg)
15914 MI->eraseFromParent();
15918 // FIXME: When we get size specific XMM0 registers, i.e. XMM0_V16I8
15919 // or XMM0_V32I8 in AVX all of this code can be replaced with that
15920 // in the .td file.
15921 static MachineBasicBlock *EmitPCMPSTRM(MachineInstr *MI, MachineBasicBlock *BB,
15922 const TargetInstrInfo *TII) {
15924 switch (MI->getOpcode()) {
15925 default: llvm_unreachable("illegal opcode!");
15926 case X86::PCMPISTRM128REG: Opc = X86::PCMPISTRM128rr; break;
15927 case X86::VPCMPISTRM128REG: Opc = X86::VPCMPISTRM128rr; break;
15928 case X86::PCMPISTRM128MEM: Opc = X86::PCMPISTRM128rm; break;
15929 case X86::VPCMPISTRM128MEM: Opc = X86::VPCMPISTRM128rm; break;
15930 case X86::PCMPESTRM128REG: Opc = X86::PCMPESTRM128rr; break;
15931 case X86::VPCMPESTRM128REG: Opc = X86::VPCMPESTRM128rr; break;
15932 case X86::PCMPESTRM128MEM: Opc = X86::PCMPESTRM128rm; break;
15933 case X86::VPCMPESTRM128MEM: Opc = X86::VPCMPESTRM128rm; break;
15936 DebugLoc dl = MI->getDebugLoc();
15937 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(Opc));
15939 unsigned NumArgs = MI->getNumOperands();
15940 for (unsigned i = 1; i < NumArgs; ++i) {
15941 MachineOperand &Op = MI->getOperand(i);
15942 if (!(Op.isReg() && Op.isImplicit()))
15943 MIB.addOperand(Op);
15945 if (MI->hasOneMemOperand())
15946 MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
15948 BuildMI(*BB, MI, dl,
15949 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
15950 .addReg(X86::XMM0);
15952 MI->eraseFromParent();
15956 // FIXME: Custom handling because TableGen doesn't support multiple implicit
15957 // defs in an instruction pattern
15958 static MachineBasicBlock *EmitPCMPSTRI(MachineInstr *MI, MachineBasicBlock *BB,
15959 const TargetInstrInfo *TII) {
15961 switch (MI->getOpcode()) {
15962 default: llvm_unreachable("illegal opcode!");
15963 case X86::PCMPISTRIREG: Opc = X86::PCMPISTRIrr; break;
15964 case X86::VPCMPISTRIREG: Opc = X86::VPCMPISTRIrr; break;
15965 case X86::PCMPISTRIMEM: Opc = X86::PCMPISTRIrm; break;
15966 case X86::VPCMPISTRIMEM: Opc = X86::VPCMPISTRIrm; break;
15967 case X86::PCMPESTRIREG: Opc = X86::PCMPESTRIrr; break;
15968 case X86::VPCMPESTRIREG: Opc = X86::VPCMPESTRIrr; break;
15969 case X86::PCMPESTRIMEM: Opc = X86::PCMPESTRIrm; break;
15970 case X86::VPCMPESTRIMEM: Opc = X86::VPCMPESTRIrm; break;
15973 DebugLoc dl = MI->getDebugLoc();
15974 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(Opc));
15976 unsigned NumArgs = MI->getNumOperands(); // remove the results
15977 for (unsigned i = 1; i < NumArgs; ++i) {
15978 MachineOperand &Op = MI->getOperand(i);
15979 if (!(Op.isReg() && Op.isImplicit()))
15980 MIB.addOperand(Op);
15982 if (MI->hasOneMemOperand())
15983 MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
15985 BuildMI(*BB, MI, dl,
15986 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
15989 MI->eraseFromParent();
15993 static MachineBasicBlock * EmitMonitor(MachineInstr *MI, MachineBasicBlock *BB,
15994 const TargetInstrInfo *TII,
15995 const X86Subtarget* Subtarget) {
15996 DebugLoc dl = MI->getDebugLoc();
15998 // Address into RAX/EAX, other two args into ECX, EDX.
15999 unsigned MemOpc = Subtarget->is64Bit() ? X86::LEA64r : X86::LEA32r;
16000 unsigned MemReg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
16001 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(MemOpc), MemReg);
16002 for (int i = 0; i < X86::AddrNumOperands; ++i)
16003 MIB.addOperand(MI->getOperand(i));
16005 unsigned ValOps = X86::AddrNumOperands;
16006 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::ECX)
16007 .addReg(MI->getOperand(ValOps).getReg());
16008 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::EDX)
16009 .addReg(MI->getOperand(ValOps+1).getReg());
16011 // The instruction doesn't actually take any operands though.
16012 BuildMI(*BB, MI, dl, TII->get(X86::MONITORrrr));
16014 MI->eraseFromParent(); // The pseudo is gone now.
16018 MachineBasicBlock *
16019 X86TargetLowering::EmitVAARG64WithCustomInserter(
16021 MachineBasicBlock *MBB) const {
16022 // Emit va_arg instruction on X86-64.
16024 // Operands to this pseudo-instruction:
16025 // 0 ) Output : destination address (reg)
16026 // 1-5) Input : va_list address (addr, i64mem)
16027 // 6 ) ArgSize : Size (in bytes) of vararg type
16028 // 7 ) ArgMode : 0=overflow only, 1=use gp_offset, 2=use fp_offset
16029 // 8 ) Align : Alignment of type
16030 // 9 ) EFLAGS (implicit-def)
16032 assert(MI->getNumOperands() == 10 && "VAARG_64 should have 10 operands!");
16033 assert(X86::AddrNumOperands == 5 && "VAARG_64 assumes 5 address operands");
16035 unsigned DestReg = MI->getOperand(0).getReg();
16036 MachineOperand &Base = MI->getOperand(1);
16037 MachineOperand &Scale = MI->getOperand(2);
16038 MachineOperand &Index = MI->getOperand(3);
16039 MachineOperand &Disp = MI->getOperand(4);
16040 MachineOperand &Segment = MI->getOperand(5);
16041 unsigned ArgSize = MI->getOperand(6).getImm();
16042 unsigned ArgMode = MI->getOperand(7).getImm();
16043 unsigned Align = MI->getOperand(8).getImm();
16045 // Memory Reference
16046 assert(MI->hasOneMemOperand() && "Expected VAARG_64 to have one memoperand");
16047 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
16048 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
16050 // Machine Information
16051 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
16052 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
16053 const TargetRegisterClass *AddrRegClass = getRegClassFor(MVT::i64);
16054 const TargetRegisterClass *OffsetRegClass = getRegClassFor(MVT::i32);
16055 DebugLoc DL = MI->getDebugLoc();
16057 // struct va_list {
16060 // i64 overflow_area (address)
16061 // i64 reg_save_area (address)
16063 // sizeof(va_list) = 24
16064 // alignment(va_list) = 8
16066 unsigned TotalNumIntRegs = 6;
16067 unsigned TotalNumXMMRegs = 8;
16068 bool UseGPOffset = (ArgMode == 1);
16069 bool UseFPOffset = (ArgMode == 2);
16070 unsigned MaxOffset = TotalNumIntRegs * 8 +
16071 (UseFPOffset ? TotalNumXMMRegs * 16 : 0);
16073 /* Align ArgSize to a multiple of 8 */
16074 unsigned ArgSizeA8 = (ArgSize + 7) & ~7;
16075 bool NeedsAlign = (Align > 8);
16077 MachineBasicBlock *thisMBB = MBB;
16078 MachineBasicBlock *overflowMBB;
16079 MachineBasicBlock *offsetMBB;
16080 MachineBasicBlock *endMBB;
16082 unsigned OffsetDestReg = 0; // Argument address computed by offsetMBB
16083 unsigned OverflowDestReg = 0; // Argument address computed by overflowMBB
16084 unsigned OffsetReg = 0;
16086 if (!UseGPOffset && !UseFPOffset) {
16087 // If we only pull from the overflow region, we don't create a branch.
16088 // We don't need to alter control flow.
16089 OffsetDestReg = 0; // unused
16090 OverflowDestReg = DestReg;
16092 offsetMBB = nullptr;
16093 overflowMBB = thisMBB;
16096 // First emit code to check if gp_offset (or fp_offset) is below the bound.
16097 // If so, pull the argument from reg_save_area. (branch to offsetMBB)
16098 // If not, pull from overflow_area. (branch to overflowMBB)
16103 // offsetMBB overflowMBB
16108 // Registers for the PHI in endMBB
16109 OffsetDestReg = MRI.createVirtualRegister(AddrRegClass);
16110 OverflowDestReg = MRI.createVirtualRegister(AddrRegClass);
16112 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
16113 MachineFunction *MF = MBB->getParent();
16114 overflowMBB = MF->CreateMachineBasicBlock(LLVM_BB);
16115 offsetMBB = MF->CreateMachineBasicBlock(LLVM_BB);
16116 endMBB = MF->CreateMachineBasicBlock(LLVM_BB);
16118 MachineFunction::iterator MBBIter = MBB;
16121 // Insert the new basic blocks
16122 MF->insert(MBBIter, offsetMBB);
16123 MF->insert(MBBIter, overflowMBB);
16124 MF->insert(MBBIter, endMBB);
16126 // Transfer the remainder of MBB and its successor edges to endMBB.
16127 endMBB->splice(endMBB->begin(), thisMBB,
16128 std::next(MachineBasicBlock::iterator(MI)), thisMBB->end());
16129 endMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
16131 // Make offsetMBB and overflowMBB successors of thisMBB
16132 thisMBB->addSuccessor(offsetMBB);
16133 thisMBB->addSuccessor(overflowMBB);
16135 // endMBB is a successor of both offsetMBB and overflowMBB
16136 offsetMBB->addSuccessor(endMBB);
16137 overflowMBB->addSuccessor(endMBB);
16139 // Load the offset value into a register
16140 OffsetReg = MRI.createVirtualRegister(OffsetRegClass);
16141 BuildMI(thisMBB, DL, TII->get(X86::MOV32rm), OffsetReg)
16145 .addDisp(Disp, UseFPOffset ? 4 : 0)
16146 .addOperand(Segment)
16147 .setMemRefs(MMOBegin, MMOEnd);
16149 // Check if there is enough room left to pull this argument.
16150 BuildMI(thisMBB, DL, TII->get(X86::CMP32ri))
16152 .addImm(MaxOffset + 8 - ArgSizeA8);
16154 // Branch to "overflowMBB" if offset >= max
16155 // Fall through to "offsetMBB" otherwise
16156 BuildMI(thisMBB, DL, TII->get(X86::GetCondBranchFromCond(X86::COND_AE)))
16157 .addMBB(overflowMBB);
16160 // In offsetMBB, emit code to use the reg_save_area.
16162 assert(OffsetReg != 0);
16164 // Read the reg_save_area address.
16165 unsigned RegSaveReg = MRI.createVirtualRegister(AddrRegClass);
16166 BuildMI(offsetMBB, DL, TII->get(X86::MOV64rm), RegSaveReg)
16171 .addOperand(Segment)
16172 .setMemRefs(MMOBegin, MMOEnd);
16174 // Zero-extend the offset
16175 unsigned OffsetReg64 = MRI.createVirtualRegister(AddrRegClass);
16176 BuildMI(offsetMBB, DL, TII->get(X86::SUBREG_TO_REG), OffsetReg64)
16179 .addImm(X86::sub_32bit);
16181 // Add the offset to the reg_save_area to get the final address.
16182 BuildMI(offsetMBB, DL, TII->get(X86::ADD64rr), OffsetDestReg)
16183 .addReg(OffsetReg64)
16184 .addReg(RegSaveReg);
16186 // Compute the offset for the next argument
16187 unsigned NextOffsetReg = MRI.createVirtualRegister(OffsetRegClass);
16188 BuildMI(offsetMBB, DL, TII->get(X86::ADD32ri), NextOffsetReg)
16190 .addImm(UseFPOffset ? 16 : 8);
16192 // Store it back into the va_list.
16193 BuildMI(offsetMBB, DL, TII->get(X86::MOV32mr))
16197 .addDisp(Disp, UseFPOffset ? 4 : 0)
16198 .addOperand(Segment)
16199 .addReg(NextOffsetReg)
16200 .setMemRefs(MMOBegin, MMOEnd);
16203 BuildMI(offsetMBB, DL, TII->get(X86::JMP_4))
16208 // Emit code to use overflow area
16211 // Load the overflow_area address into a register.
16212 unsigned OverflowAddrReg = MRI.createVirtualRegister(AddrRegClass);
16213 BuildMI(overflowMBB, DL, TII->get(X86::MOV64rm), OverflowAddrReg)
16218 .addOperand(Segment)
16219 .setMemRefs(MMOBegin, MMOEnd);
16221 // If we need to align it, do so. Otherwise, just copy the address
16222 // to OverflowDestReg.
16224 // Align the overflow address
16225 assert((Align & (Align-1)) == 0 && "Alignment must be a power of 2");
16226 unsigned TmpReg = MRI.createVirtualRegister(AddrRegClass);
16228 // aligned_addr = (addr + (align-1)) & ~(align-1)
16229 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), TmpReg)
16230 .addReg(OverflowAddrReg)
16233 BuildMI(overflowMBB, DL, TII->get(X86::AND64ri32), OverflowDestReg)
16235 .addImm(~(uint64_t)(Align-1));
16237 BuildMI(overflowMBB, DL, TII->get(TargetOpcode::COPY), OverflowDestReg)
16238 .addReg(OverflowAddrReg);
16241 // Compute the next overflow address after this argument.
16242 // (the overflow address should be kept 8-byte aligned)
16243 unsigned NextAddrReg = MRI.createVirtualRegister(AddrRegClass);
16244 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), NextAddrReg)
16245 .addReg(OverflowDestReg)
16246 .addImm(ArgSizeA8);
16248 // Store the new overflow address.
16249 BuildMI(overflowMBB, DL, TII->get(X86::MOV64mr))
16254 .addOperand(Segment)
16255 .addReg(NextAddrReg)
16256 .setMemRefs(MMOBegin, MMOEnd);
16258 // If we branched, emit the PHI to the front of endMBB.
16260 BuildMI(*endMBB, endMBB->begin(), DL,
16261 TII->get(X86::PHI), DestReg)
16262 .addReg(OffsetDestReg).addMBB(offsetMBB)
16263 .addReg(OverflowDestReg).addMBB(overflowMBB);
16266 // Erase the pseudo instruction
16267 MI->eraseFromParent();
16272 MachineBasicBlock *
16273 X86TargetLowering::EmitVAStartSaveXMMRegsWithCustomInserter(
16275 MachineBasicBlock *MBB) const {
16276 // Emit code to save XMM registers to the stack. The ABI says that the
16277 // number of registers to save is given in %al, so it's theoretically
16278 // possible to do an indirect jump trick to avoid saving all of them,
16279 // however this code takes a simpler approach and just executes all
16280 // of the stores if %al is non-zero. It's less code, and it's probably
16281 // easier on the hardware branch predictor, and stores aren't all that
16282 // expensive anyway.
16284 // Create the new basic blocks. One block contains all the XMM stores,
16285 // and one block is the final destination regardless of whether any
16286 // stores were performed.
16287 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
16288 MachineFunction *F = MBB->getParent();
16289 MachineFunction::iterator MBBIter = MBB;
16291 MachineBasicBlock *XMMSaveMBB = F->CreateMachineBasicBlock(LLVM_BB);
16292 MachineBasicBlock *EndMBB = F->CreateMachineBasicBlock(LLVM_BB);
16293 F->insert(MBBIter, XMMSaveMBB);
16294 F->insert(MBBIter, EndMBB);
16296 // Transfer the remainder of MBB and its successor edges to EndMBB.
16297 EndMBB->splice(EndMBB->begin(), MBB,
16298 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
16299 EndMBB->transferSuccessorsAndUpdatePHIs(MBB);
16301 // The original block will now fall through to the XMM save block.
16302 MBB->addSuccessor(XMMSaveMBB);
16303 // The XMMSaveMBB will fall through to the end block.
16304 XMMSaveMBB->addSuccessor(EndMBB);
16306 // Now add the instructions.
16307 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
16308 DebugLoc DL = MI->getDebugLoc();
16310 unsigned CountReg = MI->getOperand(0).getReg();
16311 int64_t RegSaveFrameIndex = MI->getOperand(1).getImm();
16312 int64_t VarArgsFPOffset = MI->getOperand(2).getImm();
16314 if (!Subtarget->isTargetWin64()) {
16315 // If %al is 0, branch around the XMM save block.
16316 BuildMI(MBB, DL, TII->get(X86::TEST8rr)).addReg(CountReg).addReg(CountReg);
16317 BuildMI(MBB, DL, TII->get(X86::JE_4)).addMBB(EndMBB);
16318 MBB->addSuccessor(EndMBB);
16321 // Make sure the last operand is EFLAGS, which gets clobbered by the branch
16322 // that was just emitted, but clearly shouldn't be "saved".
16323 assert((MI->getNumOperands() <= 3 ||
16324 !MI->getOperand(MI->getNumOperands() - 1).isReg() ||
16325 MI->getOperand(MI->getNumOperands() - 1).getReg() == X86::EFLAGS)
16326 && "Expected last argument to be EFLAGS");
16327 unsigned MOVOpc = Subtarget->hasFp256() ? X86::VMOVAPSmr : X86::MOVAPSmr;
16328 // In the XMM save block, save all the XMM argument registers.
16329 for (int i = 3, e = MI->getNumOperands() - 1; i != e; ++i) {
16330 int64_t Offset = (i - 3) * 16 + VarArgsFPOffset;
16331 MachineMemOperand *MMO =
16332 F->getMachineMemOperand(
16333 MachinePointerInfo::getFixedStack(RegSaveFrameIndex, Offset),
16334 MachineMemOperand::MOStore,
16335 /*Size=*/16, /*Align=*/16);
16336 BuildMI(XMMSaveMBB, DL, TII->get(MOVOpc))
16337 .addFrameIndex(RegSaveFrameIndex)
16338 .addImm(/*Scale=*/1)
16339 .addReg(/*IndexReg=*/0)
16340 .addImm(/*Disp=*/Offset)
16341 .addReg(/*Segment=*/0)
16342 .addReg(MI->getOperand(i).getReg())
16343 .addMemOperand(MMO);
16346 MI->eraseFromParent(); // The pseudo instruction is gone now.
16351 // The EFLAGS operand of SelectItr might be missing a kill marker
16352 // because there were multiple uses of EFLAGS, and ISel didn't know
16353 // which to mark. Figure out whether SelectItr should have had a
16354 // kill marker, and set it if it should. Returns the correct kill
16356 static bool checkAndUpdateEFLAGSKill(MachineBasicBlock::iterator SelectItr,
16357 MachineBasicBlock* BB,
16358 const TargetRegisterInfo* TRI) {
16359 // Scan forward through BB for a use/def of EFLAGS.
16360 MachineBasicBlock::iterator miI(std::next(SelectItr));
16361 for (MachineBasicBlock::iterator miE = BB->end(); miI != miE; ++miI) {
16362 const MachineInstr& mi = *miI;
16363 if (mi.readsRegister(X86::EFLAGS))
16365 if (mi.definesRegister(X86::EFLAGS))
16366 break; // Should have kill-flag - update below.
16369 // If we hit the end of the block, check whether EFLAGS is live into a
16371 if (miI == BB->end()) {
16372 for (MachineBasicBlock::succ_iterator sItr = BB->succ_begin(),
16373 sEnd = BB->succ_end();
16374 sItr != sEnd; ++sItr) {
16375 MachineBasicBlock* succ = *sItr;
16376 if (succ->isLiveIn(X86::EFLAGS))
16381 // We found a def, or hit the end of the basic block and EFLAGS wasn't live
16382 // out. SelectMI should have a kill flag on EFLAGS.
16383 SelectItr->addRegisterKilled(X86::EFLAGS, TRI);
16387 MachineBasicBlock *
16388 X86TargetLowering::EmitLoweredSelect(MachineInstr *MI,
16389 MachineBasicBlock *BB) const {
16390 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
16391 DebugLoc DL = MI->getDebugLoc();
16393 // To "insert" a SELECT_CC instruction, we actually have to insert the
16394 // diamond control-flow pattern. The incoming instruction knows the
16395 // destination vreg to set, the condition code register to branch on, the
16396 // true/false values to select between, and a branch opcode to use.
16397 const BasicBlock *LLVM_BB = BB->getBasicBlock();
16398 MachineFunction::iterator It = BB;
16404 // cmpTY ccX, r1, r2
16406 // fallthrough --> copy0MBB
16407 MachineBasicBlock *thisMBB = BB;
16408 MachineFunction *F = BB->getParent();
16409 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
16410 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
16411 F->insert(It, copy0MBB);
16412 F->insert(It, sinkMBB);
16414 // If the EFLAGS register isn't dead in the terminator, then claim that it's
16415 // live into the sink and copy blocks.
16416 const TargetRegisterInfo* TRI = getTargetMachine().getRegisterInfo();
16417 if (!MI->killsRegister(X86::EFLAGS) &&
16418 !checkAndUpdateEFLAGSKill(MI, BB, TRI)) {
16419 copy0MBB->addLiveIn(X86::EFLAGS);
16420 sinkMBB->addLiveIn(X86::EFLAGS);
16423 // Transfer the remainder of BB and its successor edges to sinkMBB.
16424 sinkMBB->splice(sinkMBB->begin(), BB,
16425 std::next(MachineBasicBlock::iterator(MI)), BB->end());
16426 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
16428 // Add the true and fallthrough blocks as its successors.
16429 BB->addSuccessor(copy0MBB);
16430 BB->addSuccessor(sinkMBB);
16432 // Create the conditional branch instruction.
16434 X86::GetCondBranchFromCond((X86::CondCode)MI->getOperand(3).getImm());
16435 BuildMI(BB, DL, TII->get(Opc)).addMBB(sinkMBB);
16438 // %FalseValue = ...
16439 // # fallthrough to sinkMBB
16440 copy0MBB->addSuccessor(sinkMBB);
16443 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
16445 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
16446 TII->get(X86::PHI), MI->getOperand(0).getReg())
16447 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB)
16448 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
16450 MI->eraseFromParent(); // The pseudo instruction is gone now.
16454 MachineBasicBlock *
16455 X86TargetLowering::EmitLoweredSegAlloca(MachineInstr *MI, MachineBasicBlock *BB,
16456 bool Is64Bit) const {
16457 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
16458 DebugLoc DL = MI->getDebugLoc();
16459 MachineFunction *MF = BB->getParent();
16460 const BasicBlock *LLVM_BB = BB->getBasicBlock();
16462 assert(MF->shouldSplitStack());
16464 unsigned TlsReg = Is64Bit ? X86::FS : X86::GS;
16465 unsigned TlsOffset = Is64Bit ? 0x70 : 0x30;
16468 // ... [Till the alloca]
16469 // If stacklet is not large enough, jump to mallocMBB
16472 // Allocate by subtracting from RSP
16473 // Jump to continueMBB
16476 // Allocate by call to runtime
16480 // [rest of original BB]
16483 MachineBasicBlock *mallocMBB = MF->CreateMachineBasicBlock(LLVM_BB);
16484 MachineBasicBlock *bumpMBB = MF->CreateMachineBasicBlock(LLVM_BB);
16485 MachineBasicBlock *continueMBB = MF->CreateMachineBasicBlock(LLVM_BB);
16487 MachineRegisterInfo &MRI = MF->getRegInfo();
16488 const TargetRegisterClass *AddrRegClass =
16489 getRegClassFor(Is64Bit ? MVT::i64:MVT::i32);
16491 unsigned mallocPtrVReg = MRI.createVirtualRegister(AddrRegClass),
16492 bumpSPPtrVReg = MRI.createVirtualRegister(AddrRegClass),
16493 tmpSPVReg = MRI.createVirtualRegister(AddrRegClass),
16494 SPLimitVReg = MRI.createVirtualRegister(AddrRegClass),
16495 sizeVReg = MI->getOperand(1).getReg(),
16496 physSPReg = Is64Bit ? X86::RSP : X86::ESP;
16498 MachineFunction::iterator MBBIter = BB;
16501 MF->insert(MBBIter, bumpMBB);
16502 MF->insert(MBBIter, mallocMBB);
16503 MF->insert(MBBIter, continueMBB);
16505 continueMBB->splice(continueMBB->begin(), BB,
16506 std::next(MachineBasicBlock::iterator(MI)), BB->end());
16507 continueMBB->transferSuccessorsAndUpdatePHIs(BB);
16509 // Add code to the main basic block to check if the stack limit has been hit,
16510 // and if so, jump to mallocMBB otherwise to bumpMBB.
16511 BuildMI(BB, DL, TII->get(TargetOpcode::COPY), tmpSPVReg).addReg(physSPReg);
16512 BuildMI(BB, DL, TII->get(Is64Bit ? X86::SUB64rr:X86::SUB32rr), SPLimitVReg)
16513 .addReg(tmpSPVReg).addReg(sizeVReg);
16514 BuildMI(BB, DL, TII->get(Is64Bit ? X86::CMP64mr:X86::CMP32mr))
16515 .addReg(0).addImm(1).addReg(0).addImm(TlsOffset).addReg(TlsReg)
16516 .addReg(SPLimitVReg);
16517 BuildMI(BB, DL, TII->get(X86::JG_4)).addMBB(mallocMBB);
16519 // bumpMBB simply decreases the stack pointer, since we know the current
16520 // stacklet has enough space.
16521 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), physSPReg)
16522 .addReg(SPLimitVReg);
16523 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), bumpSPPtrVReg)
16524 .addReg(SPLimitVReg);
16525 BuildMI(bumpMBB, DL, TII->get(X86::JMP_4)).addMBB(continueMBB);
16527 // Calls into a routine in libgcc to allocate more space from the heap.
16528 const uint32_t *RegMask =
16529 getTargetMachine().getRegisterInfo()->getCallPreservedMask(CallingConv::C);
16531 BuildMI(mallocMBB, DL, TII->get(X86::MOV64rr), X86::RDI)
16533 BuildMI(mallocMBB, DL, TII->get(X86::CALL64pcrel32))
16534 .addExternalSymbol("__morestack_allocate_stack_space")
16535 .addRegMask(RegMask)
16536 .addReg(X86::RDI, RegState::Implicit)
16537 .addReg(X86::RAX, RegState::ImplicitDefine);
16539 BuildMI(mallocMBB, DL, TII->get(X86::SUB32ri), physSPReg).addReg(physSPReg)
16541 BuildMI(mallocMBB, DL, TII->get(X86::PUSH32r)).addReg(sizeVReg);
16542 BuildMI(mallocMBB, DL, TII->get(X86::CALLpcrel32))
16543 .addExternalSymbol("__morestack_allocate_stack_space")
16544 .addRegMask(RegMask)
16545 .addReg(X86::EAX, RegState::ImplicitDefine);
16549 BuildMI(mallocMBB, DL, TII->get(X86::ADD32ri), physSPReg).addReg(physSPReg)
16552 BuildMI(mallocMBB, DL, TII->get(TargetOpcode::COPY), mallocPtrVReg)
16553 .addReg(Is64Bit ? X86::RAX : X86::EAX);
16554 BuildMI(mallocMBB, DL, TII->get(X86::JMP_4)).addMBB(continueMBB);
16556 // Set up the CFG correctly.
16557 BB->addSuccessor(bumpMBB);
16558 BB->addSuccessor(mallocMBB);
16559 mallocMBB->addSuccessor(continueMBB);
16560 bumpMBB->addSuccessor(continueMBB);
16562 // Take care of the PHI nodes.
16563 BuildMI(*continueMBB, continueMBB->begin(), DL, TII->get(X86::PHI),
16564 MI->getOperand(0).getReg())
16565 .addReg(mallocPtrVReg).addMBB(mallocMBB)
16566 .addReg(bumpSPPtrVReg).addMBB(bumpMBB);
16568 // Delete the original pseudo instruction.
16569 MI->eraseFromParent();
16572 return continueMBB;
16575 MachineBasicBlock *
16576 X86TargetLowering::EmitLoweredWinAlloca(MachineInstr *MI,
16577 MachineBasicBlock *BB) const {
16578 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
16579 DebugLoc DL = MI->getDebugLoc();
16581 assert(!Subtarget->isTargetMacho());
16583 // The lowering is pretty easy: we're just emitting the call to _alloca. The
16584 // non-trivial part is impdef of ESP.
16586 if (Subtarget->isTargetWin64()) {
16587 if (Subtarget->isTargetCygMing()) {
16588 // ___chkstk(Mingw64):
16589 // Clobbers R10, R11, RAX and EFLAGS.
16591 BuildMI(*BB, MI, DL, TII->get(X86::W64ALLOCA))
16592 .addExternalSymbol("___chkstk")
16593 .addReg(X86::RAX, RegState::Implicit)
16594 .addReg(X86::RSP, RegState::Implicit)
16595 .addReg(X86::RAX, RegState::Define | RegState::Implicit)
16596 .addReg(X86::RSP, RegState::Define | RegState::Implicit)
16597 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
16599 // __chkstk(MSVCRT): does not update stack pointer.
16600 // Clobbers R10, R11 and EFLAGS.
16601 BuildMI(*BB, MI, DL, TII->get(X86::W64ALLOCA))
16602 .addExternalSymbol("__chkstk")
16603 .addReg(X86::RAX, RegState::Implicit)
16604 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
16605 // RAX has the offset to be subtracted from RSP.
16606 BuildMI(*BB, MI, DL, TII->get(X86::SUB64rr), X86::RSP)
16611 const char *StackProbeSymbol =
16612 Subtarget->isTargetKnownWindowsMSVC() ? "_chkstk" : "_alloca";
16614 BuildMI(*BB, MI, DL, TII->get(X86::CALLpcrel32))
16615 .addExternalSymbol(StackProbeSymbol)
16616 .addReg(X86::EAX, RegState::Implicit)
16617 .addReg(X86::ESP, RegState::Implicit)
16618 .addReg(X86::EAX, RegState::Define | RegState::Implicit)
16619 .addReg(X86::ESP, RegState::Define | RegState::Implicit)
16620 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
16623 MI->eraseFromParent(); // The pseudo instruction is gone now.
16627 MachineBasicBlock *
16628 X86TargetLowering::EmitLoweredTLSCall(MachineInstr *MI,
16629 MachineBasicBlock *BB) const {
16630 // This is pretty easy. We're taking the value that we received from
16631 // our load from the relocation, sticking it in either RDI (x86-64)
16632 // or EAX and doing an indirect call. The return value will then
16633 // be in the normal return register.
16634 const X86InstrInfo *TII
16635 = static_cast<const X86InstrInfo*>(getTargetMachine().getInstrInfo());
16636 DebugLoc DL = MI->getDebugLoc();
16637 MachineFunction *F = BB->getParent();
16639 assert(Subtarget->isTargetDarwin() && "Darwin only instr emitted?");
16640 assert(MI->getOperand(3).isGlobal() && "This should be a global");
16642 // Get a register mask for the lowered call.
16643 // FIXME: The 32-bit calls have non-standard calling conventions. Use a
16644 // proper register mask.
16645 const uint32_t *RegMask =
16646 getTargetMachine().getRegisterInfo()->getCallPreservedMask(CallingConv::C);
16647 if (Subtarget->is64Bit()) {
16648 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
16649 TII->get(X86::MOV64rm), X86::RDI)
16651 .addImm(0).addReg(0)
16652 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
16653 MI->getOperand(3).getTargetFlags())
16655 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL64m));
16656 addDirectMem(MIB, X86::RDI);
16657 MIB.addReg(X86::RAX, RegState::ImplicitDefine).addRegMask(RegMask);
16658 } else if (getTargetMachine().getRelocationModel() != Reloc::PIC_) {
16659 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
16660 TII->get(X86::MOV32rm), X86::EAX)
16662 .addImm(0).addReg(0)
16663 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
16664 MI->getOperand(3).getTargetFlags())
16666 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
16667 addDirectMem(MIB, X86::EAX);
16668 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask);
16670 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
16671 TII->get(X86::MOV32rm), X86::EAX)
16672 .addReg(TII->getGlobalBaseReg(F))
16673 .addImm(0).addReg(0)
16674 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
16675 MI->getOperand(3).getTargetFlags())
16677 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
16678 addDirectMem(MIB, X86::EAX);
16679 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask);
16682 MI->eraseFromParent(); // The pseudo instruction is gone now.
16686 MachineBasicBlock *
16687 X86TargetLowering::emitEHSjLjSetJmp(MachineInstr *MI,
16688 MachineBasicBlock *MBB) const {
16689 DebugLoc DL = MI->getDebugLoc();
16690 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
16692 MachineFunction *MF = MBB->getParent();
16693 MachineRegisterInfo &MRI = MF->getRegInfo();
16695 const BasicBlock *BB = MBB->getBasicBlock();
16696 MachineFunction::iterator I = MBB;
16699 // Memory Reference
16700 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
16701 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
16704 unsigned MemOpndSlot = 0;
16706 unsigned CurOp = 0;
16708 DstReg = MI->getOperand(CurOp++).getReg();
16709 const TargetRegisterClass *RC = MRI.getRegClass(DstReg);
16710 assert(RC->hasType(MVT::i32) && "Invalid destination!");
16711 unsigned mainDstReg = MRI.createVirtualRegister(RC);
16712 unsigned restoreDstReg = MRI.createVirtualRegister(RC);
16714 MemOpndSlot = CurOp;
16716 MVT PVT = getPointerTy();
16717 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
16718 "Invalid Pointer Size!");
16720 // For v = setjmp(buf), we generate
16723 // buf[LabelOffset] = restoreMBB
16724 // SjLjSetup restoreMBB
16730 // v = phi(main, restore)
16735 MachineBasicBlock *thisMBB = MBB;
16736 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
16737 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
16738 MachineBasicBlock *restoreMBB = MF->CreateMachineBasicBlock(BB);
16739 MF->insert(I, mainMBB);
16740 MF->insert(I, sinkMBB);
16741 MF->push_back(restoreMBB);
16743 MachineInstrBuilder MIB;
16745 // Transfer the remainder of BB and its successor edges to sinkMBB.
16746 sinkMBB->splice(sinkMBB->begin(), MBB,
16747 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
16748 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
16751 unsigned PtrStoreOpc = 0;
16752 unsigned LabelReg = 0;
16753 const int64_t LabelOffset = 1 * PVT.getStoreSize();
16754 Reloc::Model RM = getTargetMachine().getRelocationModel();
16755 bool UseImmLabel = (getTargetMachine().getCodeModel() == CodeModel::Small) &&
16756 (RM == Reloc::Static || RM == Reloc::DynamicNoPIC);
16758 // Prepare IP either in reg or imm.
16759 if (!UseImmLabel) {
16760 PtrStoreOpc = (PVT == MVT::i64) ? X86::MOV64mr : X86::MOV32mr;
16761 const TargetRegisterClass *PtrRC = getRegClassFor(PVT);
16762 LabelReg = MRI.createVirtualRegister(PtrRC);
16763 if (Subtarget->is64Bit()) {
16764 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::LEA64r), LabelReg)
16768 .addMBB(restoreMBB)
16771 const X86InstrInfo *XII = static_cast<const X86InstrInfo*>(TII);
16772 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::LEA32r), LabelReg)
16773 .addReg(XII->getGlobalBaseReg(MF))
16776 .addMBB(restoreMBB, Subtarget->ClassifyBlockAddressReference())
16780 PtrStoreOpc = (PVT == MVT::i64) ? X86::MOV64mi32 : X86::MOV32mi;
16782 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PtrStoreOpc));
16783 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
16784 if (i == X86::AddrDisp)
16785 MIB.addDisp(MI->getOperand(MemOpndSlot + i), LabelOffset);
16787 MIB.addOperand(MI->getOperand(MemOpndSlot + i));
16790 MIB.addReg(LabelReg);
16792 MIB.addMBB(restoreMBB);
16793 MIB.setMemRefs(MMOBegin, MMOEnd);
16795 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::EH_SjLj_Setup))
16796 .addMBB(restoreMBB);
16798 const X86RegisterInfo *RegInfo =
16799 static_cast<const X86RegisterInfo*>(getTargetMachine().getRegisterInfo());
16800 MIB.addRegMask(RegInfo->getNoPreservedMask());
16801 thisMBB->addSuccessor(mainMBB);
16802 thisMBB->addSuccessor(restoreMBB);
16806 BuildMI(mainMBB, DL, TII->get(X86::MOV32r0), mainDstReg);
16807 mainMBB->addSuccessor(sinkMBB);
16810 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
16811 TII->get(X86::PHI), DstReg)
16812 .addReg(mainDstReg).addMBB(mainMBB)
16813 .addReg(restoreDstReg).addMBB(restoreMBB);
16816 BuildMI(restoreMBB, DL, TII->get(X86::MOV32ri), restoreDstReg).addImm(1);
16817 BuildMI(restoreMBB, DL, TII->get(X86::JMP_4)).addMBB(sinkMBB);
16818 restoreMBB->addSuccessor(sinkMBB);
16820 MI->eraseFromParent();
16824 MachineBasicBlock *
16825 X86TargetLowering::emitEHSjLjLongJmp(MachineInstr *MI,
16826 MachineBasicBlock *MBB) const {
16827 DebugLoc DL = MI->getDebugLoc();
16828 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
16830 MachineFunction *MF = MBB->getParent();
16831 MachineRegisterInfo &MRI = MF->getRegInfo();
16833 // Memory Reference
16834 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
16835 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
16837 MVT PVT = getPointerTy();
16838 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
16839 "Invalid Pointer Size!");
16841 const TargetRegisterClass *RC =
16842 (PVT == MVT::i64) ? &X86::GR64RegClass : &X86::GR32RegClass;
16843 unsigned Tmp = MRI.createVirtualRegister(RC);
16844 // Since FP is only updated here but NOT referenced, it's treated as GPR.
16845 const X86RegisterInfo *RegInfo =
16846 static_cast<const X86RegisterInfo*>(getTargetMachine().getRegisterInfo());
16847 unsigned FP = (PVT == MVT::i64) ? X86::RBP : X86::EBP;
16848 unsigned SP = RegInfo->getStackRegister();
16850 MachineInstrBuilder MIB;
16852 const int64_t LabelOffset = 1 * PVT.getStoreSize();
16853 const int64_t SPOffset = 2 * PVT.getStoreSize();
16855 unsigned PtrLoadOpc = (PVT == MVT::i64) ? X86::MOV64rm : X86::MOV32rm;
16856 unsigned IJmpOpc = (PVT == MVT::i64) ? X86::JMP64r : X86::JMP32r;
16859 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), FP);
16860 for (unsigned i = 0; i < X86::AddrNumOperands; ++i)
16861 MIB.addOperand(MI->getOperand(i));
16862 MIB.setMemRefs(MMOBegin, MMOEnd);
16864 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), Tmp);
16865 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
16866 if (i == X86::AddrDisp)
16867 MIB.addDisp(MI->getOperand(i), LabelOffset);
16869 MIB.addOperand(MI->getOperand(i));
16871 MIB.setMemRefs(MMOBegin, MMOEnd);
16873 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), SP);
16874 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
16875 if (i == X86::AddrDisp)
16876 MIB.addDisp(MI->getOperand(i), SPOffset);
16878 MIB.addOperand(MI->getOperand(i));
16880 MIB.setMemRefs(MMOBegin, MMOEnd);
16882 BuildMI(*MBB, MI, DL, TII->get(IJmpOpc)).addReg(Tmp);
16884 MI->eraseFromParent();
16888 // Replace 213-type (isel default) FMA3 instructions with 231-type for
16889 // accumulator loops. Writing back to the accumulator allows the coalescer
16890 // to remove extra copies in the loop.
16891 MachineBasicBlock *
16892 X86TargetLowering::emitFMA3Instr(MachineInstr *MI,
16893 MachineBasicBlock *MBB) const {
16894 MachineOperand &AddendOp = MI->getOperand(3);
16896 // Bail out early if the addend isn't a register - we can't switch these.
16897 if (!AddendOp.isReg())
16900 MachineFunction &MF = *MBB->getParent();
16901 MachineRegisterInfo &MRI = MF.getRegInfo();
16903 // Check whether the addend is defined by a PHI:
16904 assert(MRI.hasOneDef(AddendOp.getReg()) && "Multiple defs in SSA?");
16905 MachineInstr &AddendDef = *MRI.def_instr_begin(AddendOp.getReg());
16906 if (!AddendDef.isPHI())
16909 // Look for the following pattern:
16911 // %addend = phi [%entry, 0], [%loop, %result]
16913 // %result<tied1> = FMA213 %m2<tied0>, %m1, %addend
16917 // %addend = phi [%entry, 0], [%loop, %result]
16919 // %result<tied1> = FMA231 %addend<tied0>, %m1, %m2
16921 for (unsigned i = 1, e = AddendDef.getNumOperands(); i < e; i += 2) {
16922 assert(AddendDef.getOperand(i).isReg());
16923 MachineOperand PHISrcOp = AddendDef.getOperand(i);
16924 MachineInstr &PHISrcInst = *MRI.def_instr_begin(PHISrcOp.getReg());
16925 if (&PHISrcInst == MI) {
16926 // Found a matching instruction.
16927 unsigned NewFMAOpc = 0;
16928 switch (MI->getOpcode()) {
16929 case X86::VFMADDPDr213r: NewFMAOpc = X86::VFMADDPDr231r; break;
16930 case X86::VFMADDPSr213r: NewFMAOpc = X86::VFMADDPSr231r; break;
16931 case X86::VFMADDSDr213r: NewFMAOpc = X86::VFMADDSDr231r; break;
16932 case X86::VFMADDSSr213r: NewFMAOpc = X86::VFMADDSSr231r; break;
16933 case X86::VFMSUBPDr213r: NewFMAOpc = X86::VFMSUBPDr231r; break;
16934 case X86::VFMSUBPSr213r: NewFMAOpc = X86::VFMSUBPSr231r; break;
16935 case X86::VFMSUBSDr213r: NewFMAOpc = X86::VFMSUBSDr231r; break;
16936 case X86::VFMSUBSSr213r: NewFMAOpc = X86::VFMSUBSSr231r; break;
16937 case X86::VFNMADDPDr213r: NewFMAOpc = X86::VFNMADDPDr231r; break;
16938 case X86::VFNMADDPSr213r: NewFMAOpc = X86::VFNMADDPSr231r; break;
16939 case X86::VFNMADDSDr213r: NewFMAOpc = X86::VFNMADDSDr231r; break;
16940 case X86::VFNMADDSSr213r: NewFMAOpc = X86::VFNMADDSSr231r; break;
16941 case X86::VFNMSUBPDr213r: NewFMAOpc = X86::VFNMSUBPDr231r; break;
16942 case X86::VFNMSUBPSr213r: NewFMAOpc = X86::VFNMSUBPSr231r; break;
16943 case X86::VFNMSUBSDr213r: NewFMAOpc = X86::VFNMSUBSDr231r; break;
16944 case X86::VFNMSUBSSr213r: NewFMAOpc = X86::VFNMSUBSSr231r; break;
16945 case X86::VFMADDPDr213rY: NewFMAOpc = X86::VFMADDPDr231rY; break;
16946 case X86::VFMADDPSr213rY: NewFMAOpc = X86::VFMADDPSr231rY; break;
16947 case X86::VFMSUBPDr213rY: NewFMAOpc = X86::VFMSUBPDr231rY; break;
16948 case X86::VFMSUBPSr213rY: NewFMAOpc = X86::VFMSUBPSr231rY; break;
16949 case X86::VFNMADDPDr213rY: NewFMAOpc = X86::VFNMADDPDr231rY; break;
16950 case X86::VFNMADDPSr213rY: NewFMAOpc = X86::VFNMADDPSr231rY; break;
16951 case X86::VFNMSUBPDr213rY: NewFMAOpc = X86::VFNMSUBPDr231rY; break;
16952 case X86::VFNMSUBPSr213rY: NewFMAOpc = X86::VFNMSUBPSr231rY; break;
16953 default: llvm_unreachable("Unrecognized FMA variant.");
16956 const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo();
16957 MachineInstrBuilder MIB =
16958 BuildMI(MF, MI->getDebugLoc(), TII.get(NewFMAOpc))
16959 .addOperand(MI->getOperand(0))
16960 .addOperand(MI->getOperand(3))
16961 .addOperand(MI->getOperand(2))
16962 .addOperand(MI->getOperand(1));
16963 MBB->insert(MachineBasicBlock::iterator(MI), MIB);
16964 MI->eraseFromParent();
16971 MachineBasicBlock *
16972 X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
16973 MachineBasicBlock *BB) const {
16974 switch (MI->getOpcode()) {
16975 default: llvm_unreachable("Unexpected instr type to insert");
16976 case X86::TAILJMPd64:
16977 case X86::TAILJMPr64:
16978 case X86::TAILJMPm64:
16979 llvm_unreachable("TAILJMP64 would not be touched here.");
16980 case X86::TCRETURNdi64:
16981 case X86::TCRETURNri64:
16982 case X86::TCRETURNmi64:
16984 case X86::WIN_ALLOCA:
16985 return EmitLoweredWinAlloca(MI, BB);
16986 case X86::SEG_ALLOCA_32:
16987 return EmitLoweredSegAlloca(MI, BB, false);
16988 case X86::SEG_ALLOCA_64:
16989 return EmitLoweredSegAlloca(MI, BB, true);
16990 case X86::TLSCall_32:
16991 case X86::TLSCall_64:
16992 return EmitLoweredTLSCall(MI, BB);
16993 case X86::CMOV_GR8:
16994 case X86::CMOV_FR32:
16995 case X86::CMOV_FR64:
16996 case X86::CMOV_V4F32:
16997 case X86::CMOV_V2F64:
16998 case X86::CMOV_V2I64:
16999 case X86::CMOV_V8F32:
17000 case X86::CMOV_V4F64:
17001 case X86::CMOV_V4I64:
17002 case X86::CMOV_V16F32:
17003 case X86::CMOV_V8F64:
17004 case X86::CMOV_V8I64:
17005 case X86::CMOV_GR16:
17006 case X86::CMOV_GR32:
17007 case X86::CMOV_RFP32:
17008 case X86::CMOV_RFP64:
17009 case X86::CMOV_RFP80:
17010 return EmitLoweredSelect(MI, BB);
17012 case X86::FP32_TO_INT16_IN_MEM:
17013 case X86::FP32_TO_INT32_IN_MEM:
17014 case X86::FP32_TO_INT64_IN_MEM:
17015 case X86::FP64_TO_INT16_IN_MEM:
17016 case X86::FP64_TO_INT32_IN_MEM:
17017 case X86::FP64_TO_INT64_IN_MEM:
17018 case X86::FP80_TO_INT16_IN_MEM:
17019 case X86::FP80_TO_INT32_IN_MEM:
17020 case X86::FP80_TO_INT64_IN_MEM: {
17021 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
17022 DebugLoc DL = MI->getDebugLoc();
17024 // Change the floating point control register to use "round towards zero"
17025 // mode when truncating to an integer value.
17026 MachineFunction *F = BB->getParent();
17027 int CWFrameIdx = F->getFrameInfo()->CreateStackObject(2, 2, false);
17028 addFrameReference(BuildMI(*BB, MI, DL,
17029 TII->get(X86::FNSTCW16m)), CWFrameIdx);
17031 // Load the old value of the high byte of the control word...
17033 F->getRegInfo().createVirtualRegister(&X86::GR16RegClass);
17034 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16rm), OldCW),
17037 // Set the high part to be round to zero...
17038 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mi)), CWFrameIdx)
17041 // Reload the modified control word now...
17042 addFrameReference(BuildMI(*BB, MI, DL,
17043 TII->get(X86::FLDCW16m)), CWFrameIdx);
17045 // Restore the memory image of control word to original value
17046 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mr)), CWFrameIdx)
17049 // Get the X86 opcode to use.
17051 switch (MI->getOpcode()) {
17052 default: llvm_unreachable("illegal opcode!");
17053 case X86::FP32_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m32; break;
17054 case X86::FP32_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m32; break;
17055 case X86::FP32_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m32; break;
17056 case X86::FP64_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m64; break;
17057 case X86::FP64_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m64; break;
17058 case X86::FP64_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m64; break;
17059 case X86::FP80_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m80; break;
17060 case X86::FP80_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m80; break;
17061 case X86::FP80_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m80; break;
17065 MachineOperand &Op = MI->getOperand(0);
17067 AM.BaseType = X86AddressMode::RegBase;
17068 AM.Base.Reg = Op.getReg();
17070 AM.BaseType = X86AddressMode::FrameIndexBase;
17071 AM.Base.FrameIndex = Op.getIndex();
17073 Op = MI->getOperand(1);
17075 AM.Scale = Op.getImm();
17076 Op = MI->getOperand(2);
17078 AM.IndexReg = Op.getImm();
17079 Op = MI->getOperand(3);
17080 if (Op.isGlobal()) {
17081 AM.GV = Op.getGlobal();
17083 AM.Disp = Op.getImm();
17085 addFullAddress(BuildMI(*BB, MI, DL, TII->get(Opc)), AM)
17086 .addReg(MI->getOperand(X86::AddrNumOperands).getReg());
17088 // Reload the original control word now.
17089 addFrameReference(BuildMI(*BB, MI, DL,
17090 TII->get(X86::FLDCW16m)), CWFrameIdx);
17092 MI->eraseFromParent(); // The pseudo instruction is gone now.
17095 // String/text processing lowering.
17096 case X86::PCMPISTRM128REG:
17097 case X86::VPCMPISTRM128REG:
17098 case X86::PCMPISTRM128MEM:
17099 case X86::VPCMPISTRM128MEM:
17100 case X86::PCMPESTRM128REG:
17101 case X86::VPCMPESTRM128REG:
17102 case X86::PCMPESTRM128MEM:
17103 case X86::VPCMPESTRM128MEM:
17104 assert(Subtarget->hasSSE42() &&
17105 "Target must have SSE4.2 or AVX features enabled");
17106 return EmitPCMPSTRM(MI, BB, getTargetMachine().getInstrInfo());
17108 // String/text processing lowering.
17109 case X86::PCMPISTRIREG:
17110 case X86::VPCMPISTRIREG:
17111 case X86::PCMPISTRIMEM:
17112 case X86::VPCMPISTRIMEM:
17113 case X86::PCMPESTRIREG:
17114 case X86::VPCMPESTRIREG:
17115 case X86::PCMPESTRIMEM:
17116 case X86::VPCMPESTRIMEM:
17117 assert(Subtarget->hasSSE42() &&
17118 "Target must have SSE4.2 or AVX features enabled");
17119 return EmitPCMPSTRI(MI, BB, getTargetMachine().getInstrInfo());
17121 // Thread synchronization.
17123 return EmitMonitor(MI, BB, getTargetMachine().getInstrInfo(), Subtarget);
17127 return EmitXBegin(MI, BB, getTargetMachine().getInstrInfo());
17129 // Atomic Lowering.
17130 case X86::ATOMAND8:
17131 case X86::ATOMAND16:
17132 case X86::ATOMAND32:
17133 case X86::ATOMAND64:
17136 case X86::ATOMOR16:
17137 case X86::ATOMOR32:
17138 case X86::ATOMOR64:
17140 case X86::ATOMXOR16:
17141 case X86::ATOMXOR8:
17142 case X86::ATOMXOR32:
17143 case X86::ATOMXOR64:
17145 case X86::ATOMNAND8:
17146 case X86::ATOMNAND16:
17147 case X86::ATOMNAND32:
17148 case X86::ATOMNAND64:
17150 case X86::ATOMMAX8:
17151 case X86::ATOMMAX16:
17152 case X86::ATOMMAX32:
17153 case X86::ATOMMAX64:
17155 case X86::ATOMMIN8:
17156 case X86::ATOMMIN16:
17157 case X86::ATOMMIN32:
17158 case X86::ATOMMIN64:
17160 case X86::ATOMUMAX8:
17161 case X86::ATOMUMAX16:
17162 case X86::ATOMUMAX32:
17163 case X86::ATOMUMAX64:
17165 case X86::ATOMUMIN8:
17166 case X86::ATOMUMIN16:
17167 case X86::ATOMUMIN32:
17168 case X86::ATOMUMIN64:
17169 return EmitAtomicLoadArith(MI, BB);
17171 // This group does 64-bit operations on a 32-bit host.
17172 case X86::ATOMAND6432:
17173 case X86::ATOMOR6432:
17174 case X86::ATOMXOR6432:
17175 case X86::ATOMNAND6432:
17176 case X86::ATOMADD6432:
17177 case X86::ATOMSUB6432:
17178 case X86::ATOMMAX6432:
17179 case X86::ATOMMIN6432:
17180 case X86::ATOMUMAX6432:
17181 case X86::ATOMUMIN6432:
17182 case X86::ATOMSWAP6432:
17183 return EmitAtomicLoadArith6432(MI, BB);
17185 case X86::VASTART_SAVE_XMM_REGS:
17186 return EmitVAStartSaveXMMRegsWithCustomInserter(MI, BB);
17188 case X86::VAARG_64:
17189 return EmitVAARG64WithCustomInserter(MI, BB);
17191 case X86::EH_SjLj_SetJmp32:
17192 case X86::EH_SjLj_SetJmp64:
17193 return emitEHSjLjSetJmp(MI, BB);
17195 case X86::EH_SjLj_LongJmp32:
17196 case X86::EH_SjLj_LongJmp64:
17197 return emitEHSjLjLongJmp(MI, BB);
17199 case TargetOpcode::STACKMAP:
17200 case TargetOpcode::PATCHPOINT:
17201 return emitPatchPoint(MI, BB);
17203 case X86::VFMADDPDr213r:
17204 case X86::VFMADDPSr213r:
17205 case X86::VFMADDSDr213r:
17206 case X86::VFMADDSSr213r:
17207 case X86::VFMSUBPDr213r:
17208 case X86::VFMSUBPSr213r:
17209 case X86::VFMSUBSDr213r:
17210 case X86::VFMSUBSSr213r:
17211 case X86::VFNMADDPDr213r:
17212 case X86::VFNMADDPSr213r:
17213 case X86::VFNMADDSDr213r:
17214 case X86::VFNMADDSSr213r:
17215 case X86::VFNMSUBPDr213r:
17216 case X86::VFNMSUBPSr213r:
17217 case X86::VFNMSUBSDr213r:
17218 case X86::VFNMSUBSSr213r:
17219 case X86::VFMADDPDr213rY:
17220 case X86::VFMADDPSr213rY:
17221 case X86::VFMSUBPDr213rY:
17222 case X86::VFMSUBPSr213rY:
17223 case X86::VFNMADDPDr213rY:
17224 case X86::VFNMADDPSr213rY:
17225 case X86::VFNMSUBPDr213rY:
17226 case X86::VFNMSUBPSr213rY:
17227 return emitFMA3Instr(MI, BB);
17231 //===----------------------------------------------------------------------===//
17232 // X86 Optimization Hooks
17233 //===----------------------------------------------------------------------===//
17235 void X86TargetLowering::computeKnownBitsForTargetNode(const SDValue Op,
17238 const SelectionDAG &DAG,
17239 unsigned Depth) const {
17240 unsigned BitWidth = KnownZero.getBitWidth();
17241 unsigned Opc = Op.getOpcode();
17242 assert((Opc >= ISD::BUILTIN_OP_END ||
17243 Opc == ISD::INTRINSIC_WO_CHAIN ||
17244 Opc == ISD::INTRINSIC_W_CHAIN ||
17245 Opc == ISD::INTRINSIC_VOID) &&
17246 "Should use MaskedValueIsZero if you don't know whether Op"
17247 " is a target node!");
17249 KnownZero = KnownOne = APInt(BitWidth, 0); // Don't know anything.
17263 // These nodes' second result is a boolean.
17264 if (Op.getResNo() == 0)
17267 case X86ISD::SETCC:
17268 KnownZero |= APInt::getHighBitsSet(BitWidth, BitWidth - 1);
17270 case ISD::INTRINSIC_WO_CHAIN: {
17271 unsigned IntId = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
17272 unsigned NumLoBits = 0;
17275 case Intrinsic::x86_sse_movmsk_ps:
17276 case Intrinsic::x86_avx_movmsk_ps_256:
17277 case Intrinsic::x86_sse2_movmsk_pd:
17278 case Intrinsic::x86_avx_movmsk_pd_256:
17279 case Intrinsic::x86_mmx_pmovmskb:
17280 case Intrinsic::x86_sse2_pmovmskb_128:
17281 case Intrinsic::x86_avx2_pmovmskb: {
17282 // High bits of movmskp{s|d}, pmovmskb are known zero.
17284 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
17285 case Intrinsic::x86_sse_movmsk_ps: NumLoBits = 4; break;
17286 case Intrinsic::x86_avx_movmsk_ps_256: NumLoBits = 8; break;
17287 case Intrinsic::x86_sse2_movmsk_pd: NumLoBits = 2; break;
17288 case Intrinsic::x86_avx_movmsk_pd_256: NumLoBits = 4; break;
17289 case Intrinsic::x86_mmx_pmovmskb: NumLoBits = 8; break;
17290 case Intrinsic::x86_sse2_pmovmskb_128: NumLoBits = 16; break;
17291 case Intrinsic::x86_avx2_pmovmskb: NumLoBits = 32; break;
17293 KnownZero = APInt::getHighBitsSet(BitWidth, BitWidth - NumLoBits);
17302 unsigned X86TargetLowering::ComputeNumSignBitsForTargetNode(
17304 const SelectionDAG &,
17305 unsigned Depth) const {
17306 // SETCC_CARRY sets the dest to ~0 for true or 0 for false.
17307 if (Op.getOpcode() == X86ISD::SETCC_CARRY)
17308 return Op.getValueType().getScalarType().getSizeInBits();
17314 /// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the
17315 /// node is a GlobalAddress + offset.
17316 bool X86TargetLowering::isGAPlusOffset(SDNode *N,
17317 const GlobalValue* &GA,
17318 int64_t &Offset) const {
17319 if (N->getOpcode() == X86ISD::Wrapper) {
17320 if (isa<GlobalAddressSDNode>(N->getOperand(0))) {
17321 GA = cast<GlobalAddressSDNode>(N->getOperand(0))->getGlobal();
17322 Offset = cast<GlobalAddressSDNode>(N->getOperand(0))->getOffset();
17326 return TargetLowering::isGAPlusOffset(N, GA, Offset);
17329 /// isShuffleHigh128VectorInsertLow - Checks whether the shuffle node is the
17330 /// same as extracting the high 128-bit part of 256-bit vector and then
17331 /// inserting the result into the low part of a new 256-bit vector
17332 static bool isShuffleHigh128VectorInsertLow(ShuffleVectorSDNode *SVOp) {
17333 EVT VT = SVOp->getValueType(0);
17334 unsigned NumElems = VT.getVectorNumElements();
17336 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
17337 for (unsigned i = 0, j = NumElems/2; i != NumElems/2; ++i, ++j)
17338 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) ||
17339 SVOp->getMaskElt(j) >= 0)
17345 /// isShuffleLow128VectorInsertHigh - Checks whether the shuffle node is the
17346 /// same as extracting the low 128-bit part of 256-bit vector and then
17347 /// inserting the result into the high part of a new 256-bit vector
17348 static bool isShuffleLow128VectorInsertHigh(ShuffleVectorSDNode *SVOp) {
17349 EVT VT = SVOp->getValueType(0);
17350 unsigned NumElems = VT.getVectorNumElements();
17352 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
17353 for (unsigned i = NumElems/2, j = 0; i != NumElems; ++i, ++j)
17354 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) ||
17355 SVOp->getMaskElt(j) >= 0)
17361 /// PerformShuffleCombine256 - Performs shuffle combines for 256-bit vectors.
17362 static SDValue PerformShuffleCombine256(SDNode *N, SelectionDAG &DAG,
17363 TargetLowering::DAGCombinerInfo &DCI,
17364 const X86Subtarget* Subtarget) {
17366 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
17367 SDValue V1 = SVOp->getOperand(0);
17368 SDValue V2 = SVOp->getOperand(1);
17369 EVT VT = SVOp->getValueType(0);
17370 unsigned NumElems = VT.getVectorNumElements();
17372 if (V1.getOpcode() == ISD::CONCAT_VECTORS &&
17373 V2.getOpcode() == ISD::CONCAT_VECTORS) {
17377 // V UNDEF BUILD_VECTOR UNDEF
17379 // CONCAT_VECTOR CONCAT_VECTOR
17382 // RESULT: V + zero extended
17384 if (V2.getOperand(0).getOpcode() != ISD::BUILD_VECTOR ||
17385 V2.getOperand(1).getOpcode() != ISD::UNDEF ||
17386 V1.getOperand(1).getOpcode() != ISD::UNDEF)
17389 if (!ISD::isBuildVectorAllZeros(V2.getOperand(0).getNode()))
17392 // To match the shuffle mask, the first half of the mask should
17393 // be exactly the first vector, and all the rest a splat with the
17394 // first element of the second one.
17395 for (unsigned i = 0; i != NumElems/2; ++i)
17396 if (!isUndefOrEqual(SVOp->getMaskElt(i), i) ||
17397 !isUndefOrEqual(SVOp->getMaskElt(i+NumElems/2), NumElems))
17400 // If V1 is coming from a vector load then just fold to a VZEXT_LOAD.
17401 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(V1.getOperand(0))) {
17402 if (Ld->hasNUsesOfValue(1, 0)) {
17403 SDVTList Tys = DAG.getVTList(MVT::v4i64, MVT::Other);
17404 SDValue Ops[] = { Ld->getChain(), Ld->getBasePtr() };
17406 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, dl, Tys, Ops,
17408 Ld->getPointerInfo(),
17409 Ld->getAlignment(),
17410 false/*isVolatile*/, true/*ReadMem*/,
17411 false/*WriteMem*/);
17413 // Make sure the newly-created LOAD is in the same position as Ld in
17414 // terms of dependency. We create a TokenFactor for Ld and ResNode,
17415 // and update uses of Ld's output chain to use the TokenFactor.
17416 if (Ld->hasAnyUseOfValue(1)) {
17417 SDValue NewChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
17418 SDValue(Ld, 1), SDValue(ResNode.getNode(), 1));
17419 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), NewChain);
17420 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(Ld, 1),
17421 SDValue(ResNode.getNode(), 1));
17424 return DAG.getNode(ISD::BITCAST, dl, VT, ResNode);
17428 // Emit a zeroed vector and insert the desired subvector on its
17430 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
17431 SDValue InsV = Insert128BitVector(Zeros, V1.getOperand(0), 0, DAG, dl);
17432 return DCI.CombineTo(N, InsV);
17435 //===--------------------------------------------------------------------===//
17436 // Combine some shuffles into subvector extracts and inserts:
17439 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
17440 if (isShuffleHigh128VectorInsertLow(SVOp)) {
17441 SDValue V = Extract128BitVector(V1, NumElems/2, DAG, dl);
17442 SDValue InsV = Insert128BitVector(DAG.getUNDEF(VT), V, 0, DAG, dl);
17443 return DCI.CombineTo(N, InsV);
17446 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
17447 if (isShuffleLow128VectorInsertHigh(SVOp)) {
17448 SDValue V = Extract128BitVector(V1, 0, DAG, dl);
17449 SDValue InsV = Insert128BitVector(DAG.getUNDEF(VT), V, NumElems/2, DAG, dl);
17450 return DCI.CombineTo(N, InsV);
17456 /// PerformShuffleCombine - Performs several different shuffle combines.
17457 static SDValue PerformShuffleCombine(SDNode *N, SelectionDAG &DAG,
17458 TargetLowering::DAGCombinerInfo &DCI,
17459 const X86Subtarget *Subtarget) {
17461 EVT VT = N->getValueType(0);
17463 // Don't create instructions with illegal types after legalize types has run.
17464 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
17465 if (!DCI.isBeforeLegalize() && !TLI.isTypeLegal(VT.getVectorElementType()))
17468 // Combine 256-bit vector shuffles. This is only profitable when in AVX mode
17469 if (Subtarget->hasFp256() && VT.is256BitVector() &&
17470 N->getOpcode() == ISD::VECTOR_SHUFFLE)
17471 return PerformShuffleCombine256(N, DAG, DCI, Subtarget);
17473 // Only handle 128 wide vector from here on.
17474 if (!VT.is128BitVector())
17477 // Combine a vector_shuffle that is equal to build_vector load1, load2, load3,
17478 // load4, <0, 1, 2, 3> into a 128-bit load if the load addresses are
17479 // consecutive, non-overlapping, and in the right order.
17480 SmallVector<SDValue, 16> Elts;
17481 for (unsigned i = 0, e = VT.getVectorNumElements(); i != e; ++i)
17482 Elts.push_back(getShuffleScalarElt(N, i, DAG, 0));
17484 return EltsFromConsecutiveLoads(VT, Elts, dl, DAG, true);
17487 /// PerformTruncateCombine - Converts truncate operation to
17488 /// a sequence of vector shuffle operations.
17489 /// It is possible when we truncate 256-bit vector to 128-bit vector
17490 static SDValue PerformTruncateCombine(SDNode *N, SelectionDAG &DAG,
17491 TargetLowering::DAGCombinerInfo &DCI,
17492 const X86Subtarget *Subtarget) {
17496 /// XFormVExtractWithShuffleIntoLoad - Check if a vector extract from a target
17497 /// specific shuffle of a load can be folded into a single element load.
17498 /// Similar handling for VECTOR_SHUFFLE is performed by DAGCombiner, but
17499 /// shuffles have been customed lowered so we need to handle those here.
17500 static SDValue XFormVExtractWithShuffleIntoLoad(SDNode *N, SelectionDAG &DAG,
17501 TargetLowering::DAGCombinerInfo &DCI) {
17502 if (DCI.isBeforeLegalizeOps())
17505 SDValue InVec = N->getOperand(0);
17506 SDValue EltNo = N->getOperand(1);
17508 if (!isa<ConstantSDNode>(EltNo))
17511 EVT VT = InVec.getValueType();
17513 bool HasShuffleIntoBitcast = false;
17514 if (InVec.getOpcode() == ISD::BITCAST) {
17515 // Don't duplicate a load with other uses.
17516 if (!InVec.hasOneUse())
17518 EVT BCVT = InVec.getOperand(0).getValueType();
17519 if (BCVT.getVectorNumElements() != VT.getVectorNumElements())
17521 InVec = InVec.getOperand(0);
17522 HasShuffleIntoBitcast = true;
17525 if (!isTargetShuffle(InVec.getOpcode()))
17528 // Don't duplicate a load with other uses.
17529 if (!InVec.hasOneUse())
17532 SmallVector<int, 16> ShuffleMask;
17534 if (!getTargetShuffleMask(InVec.getNode(), VT.getSimpleVT(), ShuffleMask,
17538 // Select the input vector, guarding against out of range extract vector.
17539 unsigned NumElems = VT.getVectorNumElements();
17540 int Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();
17541 int Idx = (Elt > (int)NumElems) ? -1 : ShuffleMask[Elt];
17542 SDValue LdNode = (Idx < (int)NumElems) ? InVec.getOperand(0)
17543 : InVec.getOperand(1);
17545 // If inputs to shuffle are the same for both ops, then allow 2 uses
17546 unsigned AllowedUses = InVec.getOperand(0) == InVec.getOperand(1) ? 2 : 1;
17548 if (LdNode.getOpcode() == ISD::BITCAST) {
17549 // Don't duplicate a load with other uses.
17550 if (!LdNode.getNode()->hasNUsesOfValue(AllowedUses, 0))
17553 AllowedUses = 1; // only allow 1 load use if we have a bitcast
17554 LdNode = LdNode.getOperand(0);
17557 if (!ISD::isNormalLoad(LdNode.getNode()))
17560 LoadSDNode *LN0 = cast<LoadSDNode>(LdNode);
17562 if (!LN0 ||!LN0->hasNUsesOfValue(AllowedUses, 0) || LN0->isVolatile())
17565 if (HasShuffleIntoBitcast) {
17566 // If there's a bitcast before the shuffle, check if the load type and
17567 // alignment is valid.
17568 unsigned Align = LN0->getAlignment();
17569 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
17570 unsigned NewAlign = TLI.getDataLayout()->
17571 getABITypeAlignment(VT.getTypeForEVT(*DAG.getContext()));
17573 if (NewAlign > Align || !TLI.isOperationLegalOrCustom(ISD::LOAD, VT))
17577 // All checks match so transform back to vector_shuffle so that DAG combiner
17578 // can finish the job
17581 // Create shuffle node taking into account the case that its a unary shuffle
17582 SDValue Shuffle = (UnaryShuffle) ? DAG.getUNDEF(VT) : InVec.getOperand(1);
17583 Shuffle = DAG.getVectorShuffle(InVec.getValueType(), dl,
17584 InVec.getOperand(0), Shuffle,
17586 Shuffle = DAG.getNode(ISD::BITCAST, dl, VT, Shuffle);
17587 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, N->getValueType(0), Shuffle,
17591 /// PerformEXTRACT_VECTOR_ELTCombine - Detect vector gather/scatter index
17592 /// generation and convert it from being a bunch of shuffles and extracts
17593 /// to a simple store and scalar loads to extract the elements.
17594 static SDValue PerformEXTRACT_VECTOR_ELTCombine(SDNode *N, SelectionDAG &DAG,
17595 TargetLowering::DAGCombinerInfo &DCI) {
17596 SDValue NewOp = XFormVExtractWithShuffleIntoLoad(N, DAG, DCI);
17597 if (NewOp.getNode())
17600 SDValue InputVector = N->getOperand(0);
17602 // Detect whether we are trying to convert from mmx to i32 and the bitcast
17603 // from mmx to v2i32 has a single usage.
17604 if (InputVector.getNode()->getOpcode() == llvm::ISD::BITCAST &&
17605 InputVector.getNode()->getOperand(0).getValueType() == MVT::x86mmx &&
17606 InputVector.hasOneUse() && N->getValueType(0) == MVT::i32)
17607 return DAG.getNode(X86ISD::MMX_MOVD2W, SDLoc(InputVector),
17608 N->getValueType(0),
17609 InputVector.getNode()->getOperand(0));
17611 // Only operate on vectors of 4 elements, where the alternative shuffling
17612 // gets to be more expensive.
17613 if (InputVector.getValueType() != MVT::v4i32)
17616 // Check whether every use of InputVector is an EXTRACT_VECTOR_ELT with a
17617 // single use which is a sign-extend or zero-extend, and all elements are
17619 SmallVector<SDNode *, 4> Uses;
17620 unsigned ExtractedElements = 0;
17621 for (SDNode::use_iterator UI = InputVector.getNode()->use_begin(),
17622 UE = InputVector.getNode()->use_end(); UI != UE; ++UI) {
17623 if (UI.getUse().getResNo() != InputVector.getResNo())
17626 SDNode *Extract = *UI;
17627 if (Extract->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
17630 if (Extract->getValueType(0) != MVT::i32)
17632 if (!Extract->hasOneUse())
17634 if (Extract->use_begin()->getOpcode() != ISD::SIGN_EXTEND &&
17635 Extract->use_begin()->getOpcode() != ISD::ZERO_EXTEND)
17637 if (!isa<ConstantSDNode>(Extract->getOperand(1)))
17640 // Record which element was extracted.
17641 ExtractedElements |=
17642 1 << cast<ConstantSDNode>(Extract->getOperand(1))->getZExtValue();
17644 Uses.push_back(Extract);
17647 // If not all the elements were used, this may not be worthwhile.
17648 if (ExtractedElements != 15)
17651 // Ok, we've now decided to do the transformation.
17652 SDLoc dl(InputVector);
17654 // Store the value to a temporary stack slot.
17655 SDValue StackPtr = DAG.CreateStackTemporary(InputVector.getValueType());
17656 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, InputVector, StackPtr,
17657 MachinePointerInfo(), false, false, 0);
17659 // Replace each use (extract) with a load of the appropriate element.
17660 for (SmallVectorImpl<SDNode *>::iterator UI = Uses.begin(),
17661 UE = Uses.end(); UI != UE; ++UI) {
17662 SDNode *Extract = *UI;
17664 // cOMpute the element's address.
17665 SDValue Idx = Extract->getOperand(1);
17667 InputVector.getValueType().getVectorElementType().getSizeInBits()/8;
17668 uint64_t Offset = EltSize * cast<ConstantSDNode>(Idx)->getZExtValue();
17669 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
17670 SDValue OffsetVal = DAG.getConstant(Offset, TLI.getPointerTy());
17672 SDValue ScalarAddr = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(),
17673 StackPtr, OffsetVal);
17675 // Load the scalar.
17676 SDValue LoadScalar = DAG.getLoad(Extract->getValueType(0), dl, Ch,
17677 ScalarAddr, MachinePointerInfo(),
17678 false, false, false, 0);
17680 // Replace the exact with the load.
17681 DAG.ReplaceAllUsesOfValueWith(SDValue(Extract, 0), LoadScalar);
17684 // The replacement was made in place; don't return anything.
17688 /// \brief Matches a VSELECT onto min/max or return 0 if the node doesn't match.
17689 static std::pair<unsigned, bool>
17690 matchIntegerMINMAX(SDValue Cond, EVT VT, SDValue LHS, SDValue RHS,
17691 SelectionDAG &DAG, const X86Subtarget *Subtarget) {
17692 if (!VT.isVector())
17693 return std::make_pair(0, false);
17695 bool NeedSplit = false;
17696 switch (VT.getSimpleVT().SimpleTy) {
17697 default: return std::make_pair(0, false);
17701 if (!Subtarget->hasAVX2())
17703 if (!Subtarget->hasAVX())
17704 return std::make_pair(0, false);
17709 if (!Subtarget->hasSSE2())
17710 return std::make_pair(0, false);
17713 // SSE2 has only a small subset of the operations.
17714 bool hasUnsigned = Subtarget->hasSSE41() ||
17715 (Subtarget->hasSSE2() && VT == MVT::v16i8);
17716 bool hasSigned = Subtarget->hasSSE41() ||
17717 (Subtarget->hasSSE2() && VT == MVT::v8i16);
17719 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
17722 // Check for x CC y ? x : y.
17723 if (DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
17724 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
17729 Opc = hasUnsigned ? X86ISD::UMIN : 0; break;
17732 Opc = hasUnsigned ? X86ISD::UMAX : 0; break;
17735 Opc = hasSigned ? X86ISD::SMIN : 0; break;
17738 Opc = hasSigned ? X86ISD::SMAX : 0; break;
17740 // Check for x CC y ? y : x -- a min/max with reversed arms.
17741 } else if (DAG.isEqualTo(LHS, Cond.getOperand(1)) &&
17742 DAG.isEqualTo(RHS, Cond.getOperand(0))) {
17747 Opc = hasUnsigned ? X86ISD::UMAX : 0; break;
17750 Opc = hasUnsigned ? X86ISD::UMIN : 0; break;
17753 Opc = hasSigned ? X86ISD::SMAX : 0; break;
17756 Opc = hasSigned ? X86ISD::SMIN : 0; break;
17760 return std::make_pair(Opc, NeedSplit);
17764 TransformVSELECTtoBlendVECTOR_SHUFFLE(SDNode *N, SelectionDAG &DAG,
17765 const X86Subtarget *Subtarget) {
17767 SDValue Cond = N->getOperand(0);
17768 SDValue LHS = N->getOperand(1);
17769 SDValue RHS = N->getOperand(2);
17771 if (Cond.getOpcode() == ISD::SIGN_EXTEND) {
17772 SDValue CondSrc = Cond->getOperand(0);
17773 if (CondSrc->getOpcode() == ISD::SIGN_EXTEND_INREG)
17774 Cond = CondSrc->getOperand(0);
17777 MVT VT = N->getSimpleValueType(0);
17778 MVT EltVT = VT.getVectorElementType();
17779 unsigned NumElems = VT.getVectorNumElements();
17780 // There is no blend with immediate in AVX-512.
17781 if (VT.is512BitVector())
17784 if (!Subtarget->hasSSE41() || EltVT == MVT::i8)
17786 if (!Subtarget->hasInt256() && VT == MVT::v16i16)
17789 if (!ISD::isBuildVectorOfConstantSDNodes(Cond.getNode()))
17792 unsigned MaskValue = 0;
17793 if (!BUILD_VECTORtoBlendMask(cast<BuildVectorSDNode>(Cond), MaskValue))
17796 SmallVector<int, 8> ShuffleMask(NumElems, -1);
17797 for (unsigned i = 0; i < NumElems; ++i) {
17798 // Be sure we emit undef where we can.
17799 if (Cond.getOperand(i)->getOpcode() == ISD::UNDEF)
17800 ShuffleMask[i] = -1;
17802 ShuffleMask[i] = i + NumElems * ((MaskValue >> i) & 1);
17805 return DAG.getVectorShuffle(VT, dl, LHS, RHS, &ShuffleMask[0]);
17808 /// PerformSELECTCombine - Do target-specific dag combines on SELECT and VSELECT
17810 static SDValue PerformSELECTCombine(SDNode *N, SelectionDAG &DAG,
17811 TargetLowering::DAGCombinerInfo &DCI,
17812 const X86Subtarget *Subtarget) {
17814 SDValue Cond = N->getOperand(0);
17815 // Get the LHS/RHS of the select.
17816 SDValue LHS = N->getOperand(1);
17817 SDValue RHS = N->getOperand(2);
17818 EVT VT = LHS.getValueType();
17819 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
17821 // If we have SSE[12] support, try to form min/max nodes. SSE min/max
17822 // instructions match the semantics of the common C idiom x<y?x:y but not
17823 // x<=y?x:y, because of how they handle negative zero (which can be
17824 // ignored in unsafe-math mode).
17825 if (Cond.getOpcode() == ISD::SETCC && VT.isFloatingPoint() &&
17826 VT != MVT::f80 && TLI.isTypeLegal(VT) &&
17827 (Subtarget->hasSSE2() ||
17828 (Subtarget->hasSSE1() && VT.getScalarType() == MVT::f32))) {
17829 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
17831 unsigned Opcode = 0;
17832 // Check for x CC y ? x : y.
17833 if (DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
17834 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
17838 // Converting this to a min would handle NaNs incorrectly, and swapping
17839 // the operands would cause it to handle comparisons between positive
17840 // and negative zero incorrectly.
17841 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
17842 if (!DAG.getTarget().Options.UnsafeFPMath &&
17843 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
17845 std::swap(LHS, RHS);
17847 Opcode = X86ISD::FMIN;
17850 // Converting this to a min would handle comparisons between positive
17851 // and negative zero incorrectly.
17852 if (!DAG.getTarget().Options.UnsafeFPMath &&
17853 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
17855 Opcode = X86ISD::FMIN;
17858 // Converting this to a min would handle both negative zeros and NaNs
17859 // incorrectly, but we can swap the operands to fix both.
17860 std::swap(LHS, RHS);
17864 Opcode = X86ISD::FMIN;
17868 // Converting this to a max would handle comparisons between positive
17869 // and negative zero incorrectly.
17870 if (!DAG.getTarget().Options.UnsafeFPMath &&
17871 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
17873 Opcode = X86ISD::FMAX;
17876 // Converting this to a max would handle NaNs incorrectly, and swapping
17877 // the operands would cause it to handle comparisons between positive
17878 // and negative zero incorrectly.
17879 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
17880 if (!DAG.getTarget().Options.UnsafeFPMath &&
17881 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
17883 std::swap(LHS, RHS);
17885 Opcode = X86ISD::FMAX;
17888 // Converting this to a max would handle both negative zeros and NaNs
17889 // incorrectly, but we can swap the operands to fix both.
17890 std::swap(LHS, RHS);
17894 Opcode = X86ISD::FMAX;
17897 // Check for x CC y ? y : x -- a min/max with reversed arms.
17898 } else if (DAG.isEqualTo(LHS, Cond.getOperand(1)) &&
17899 DAG.isEqualTo(RHS, Cond.getOperand(0))) {
17903 // Converting this to a min would handle comparisons between positive
17904 // and negative zero incorrectly, and swapping the operands would
17905 // cause it to handle NaNs incorrectly.
17906 if (!DAG.getTarget().Options.UnsafeFPMath &&
17907 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS))) {
17908 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
17910 std::swap(LHS, RHS);
17912 Opcode = X86ISD::FMIN;
17915 // Converting this to a min would handle NaNs incorrectly.
17916 if (!DAG.getTarget().Options.UnsafeFPMath &&
17917 (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)))
17919 Opcode = X86ISD::FMIN;
17922 // Converting this to a min would handle both negative zeros and NaNs
17923 // incorrectly, but we can swap the operands to fix both.
17924 std::swap(LHS, RHS);
17928 Opcode = X86ISD::FMIN;
17932 // Converting this to a max would handle NaNs incorrectly.
17933 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
17935 Opcode = X86ISD::FMAX;
17938 // Converting this to a max would handle comparisons between positive
17939 // and negative zero incorrectly, and swapping the operands would
17940 // cause it to handle NaNs incorrectly.
17941 if (!DAG.getTarget().Options.UnsafeFPMath &&
17942 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS)) {
17943 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
17945 std::swap(LHS, RHS);
17947 Opcode = X86ISD::FMAX;
17950 // Converting this to a max would handle both negative zeros and NaNs
17951 // incorrectly, but we can swap the operands to fix both.
17952 std::swap(LHS, RHS);
17956 Opcode = X86ISD::FMAX;
17962 return DAG.getNode(Opcode, DL, N->getValueType(0), LHS, RHS);
17965 EVT CondVT = Cond.getValueType();
17966 if (Subtarget->hasAVX512() && VT.isVector() && CondVT.isVector() &&
17967 CondVT.getVectorElementType() == MVT::i1) {
17968 // v16i8 (select v16i1, v16i8, v16i8) does not have a proper
17969 // lowering on AVX-512. In this case we convert it to
17970 // v16i8 (select v16i8, v16i8, v16i8) and use AVX instruction.
17971 // The same situation for all 128 and 256-bit vectors of i8 and i16
17972 EVT OpVT = LHS.getValueType();
17973 if ((OpVT.is128BitVector() || OpVT.is256BitVector()) &&
17974 (OpVT.getVectorElementType() == MVT::i8 ||
17975 OpVT.getVectorElementType() == MVT::i16)) {
17976 Cond = DAG.getNode(ISD::SIGN_EXTEND, DL, OpVT, Cond);
17977 DCI.AddToWorklist(Cond.getNode());
17978 return DAG.getNode(N->getOpcode(), DL, OpVT, Cond, LHS, RHS);
17981 // If this is a select between two integer constants, try to do some
17983 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(LHS)) {
17984 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(RHS))
17985 // Don't do this for crazy integer types.
17986 if (DAG.getTargetLoweringInfo().isTypeLegal(LHS.getValueType())) {
17987 // If this is efficiently invertible, canonicalize the LHSC/RHSC values
17988 // so that TrueC (the true value) is larger than FalseC.
17989 bool NeedsCondInvert = false;
17991 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue()) &&
17992 // Efficiently invertible.
17993 (Cond.getOpcode() == ISD::SETCC || // setcc -> invertible.
17994 (Cond.getOpcode() == ISD::XOR && // xor(X, C) -> invertible.
17995 isa<ConstantSDNode>(Cond.getOperand(1))))) {
17996 NeedsCondInvert = true;
17997 std::swap(TrueC, FalseC);
18000 // Optimize C ? 8 : 0 -> zext(C) << 3. Likewise for any pow2/0.
18001 if (FalseC->getAPIntValue() == 0 &&
18002 TrueC->getAPIntValue().isPowerOf2()) {
18003 if (NeedsCondInvert) // Invert the condition if needed.
18004 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
18005 DAG.getConstant(1, Cond.getValueType()));
18007 // Zero extend the condition if needed.
18008 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, LHS.getValueType(), Cond);
18010 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
18011 return DAG.getNode(ISD::SHL, DL, LHS.getValueType(), Cond,
18012 DAG.getConstant(ShAmt, MVT::i8));
18015 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst.
18016 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
18017 if (NeedsCondInvert) // Invert the condition if needed.
18018 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
18019 DAG.getConstant(1, Cond.getValueType()));
18021 // Zero extend the condition if needed.
18022 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
18023 FalseC->getValueType(0), Cond);
18024 return DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
18025 SDValue(FalseC, 0));
18028 // Optimize cases that will turn into an LEA instruction. This requires
18029 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
18030 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
18031 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
18032 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
18034 bool isFastMultiplier = false;
18036 switch ((unsigned char)Diff) {
18038 case 1: // result = add base, cond
18039 case 2: // result = lea base( , cond*2)
18040 case 3: // result = lea base(cond, cond*2)
18041 case 4: // result = lea base( , cond*4)
18042 case 5: // result = lea base(cond, cond*4)
18043 case 8: // result = lea base( , cond*8)
18044 case 9: // result = lea base(cond, cond*8)
18045 isFastMultiplier = true;
18050 if (isFastMultiplier) {
18051 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
18052 if (NeedsCondInvert) // Invert the condition if needed.
18053 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
18054 DAG.getConstant(1, Cond.getValueType()));
18056 // Zero extend the condition if needed.
18057 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
18059 // Scale the condition by the difference.
18061 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
18062 DAG.getConstant(Diff, Cond.getValueType()));
18064 // Add the base if non-zero.
18065 if (FalseC->getAPIntValue() != 0)
18066 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
18067 SDValue(FalseC, 0));
18074 // Canonicalize max and min:
18075 // (x > y) ? x : y -> (x >= y) ? x : y
18076 // (x < y) ? x : y -> (x <= y) ? x : y
18077 // This allows use of COND_S / COND_NS (see TranslateX86CC) which eliminates
18078 // the need for an extra compare
18079 // against zero. e.g.
18080 // (x - y) > 0 : (x - y) ? 0 -> (x - y) >= 0 : (x - y) ? 0
18082 // testl %edi, %edi
18084 // cmovgl %edi, %eax
18088 // cmovsl %eax, %edi
18089 if (N->getOpcode() == ISD::SELECT && Cond.getOpcode() == ISD::SETCC &&
18090 DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
18091 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
18092 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
18097 ISD::CondCode NewCC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGE;
18098 Cond = DAG.getSetCC(SDLoc(Cond), Cond.getValueType(),
18099 Cond.getOperand(0), Cond.getOperand(1), NewCC);
18100 return DAG.getNode(ISD::SELECT, DL, VT, Cond, LHS, RHS);
18105 // Early exit check
18106 if (!TLI.isTypeLegal(VT))
18109 // Match VSELECTs into subs with unsigned saturation.
18110 if (N->getOpcode() == ISD::VSELECT && Cond.getOpcode() == ISD::SETCC &&
18111 // psubus is available in SSE2 and AVX2 for i8 and i16 vectors.
18112 ((Subtarget->hasSSE2() && (VT == MVT::v16i8 || VT == MVT::v8i16)) ||
18113 (Subtarget->hasAVX2() && (VT == MVT::v32i8 || VT == MVT::v16i16)))) {
18114 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
18116 // Check if one of the arms of the VSELECT is a zero vector. If it's on the
18117 // left side invert the predicate to simplify logic below.
18119 if (ISD::isBuildVectorAllZeros(LHS.getNode())) {
18121 CC = ISD::getSetCCInverse(CC, true);
18122 } else if (ISD::isBuildVectorAllZeros(RHS.getNode())) {
18126 if (Other.getNode() && Other->getNumOperands() == 2 &&
18127 DAG.isEqualTo(Other->getOperand(0), Cond.getOperand(0))) {
18128 SDValue OpLHS = Other->getOperand(0), OpRHS = Other->getOperand(1);
18129 SDValue CondRHS = Cond->getOperand(1);
18131 // Look for a general sub with unsigned saturation first.
18132 // x >= y ? x-y : 0 --> subus x, y
18133 // x > y ? x-y : 0 --> subus x, y
18134 if ((CC == ISD::SETUGE || CC == ISD::SETUGT) &&
18135 Other->getOpcode() == ISD::SUB && DAG.isEqualTo(OpRHS, CondRHS))
18136 return DAG.getNode(X86ISD::SUBUS, DL, VT, OpLHS, OpRHS);
18138 // If the RHS is a constant we have to reverse the const canonicalization.
18139 // x > C-1 ? x+-C : 0 --> subus x, C
18140 if (CC == ISD::SETUGT && Other->getOpcode() == ISD::ADD &&
18141 isSplatVector(CondRHS.getNode()) && isSplatVector(OpRHS.getNode())) {
18142 APInt A = cast<ConstantSDNode>(OpRHS.getOperand(0))->getAPIntValue();
18143 if (CondRHS.getConstantOperandVal(0) == -A-1)
18144 return DAG.getNode(X86ISD::SUBUS, DL, VT, OpLHS,
18145 DAG.getConstant(-A, VT));
18148 // Another special case: If C was a sign bit, the sub has been
18149 // canonicalized into a xor.
18150 // FIXME: Would it be better to use computeKnownBits to determine whether
18151 // it's safe to decanonicalize the xor?
18152 // x s< 0 ? x^C : 0 --> subus x, C
18153 if (CC == ISD::SETLT && Other->getOpcode() == ISD::XOR &&
18154 ISD::isBuildVectorAllZeros(CondRHS.getNode()) &&
18155 isSplatVector(OpRHS.getNode())) {
18156 APInt A = cast<ConstantSDNode>(OpRHS.getOperand(0))->getAPIntValue();
18158 return DAG.getNode(X86ISD::SUBUS, DL, VT, OpLHS, OpRHS);
18163 // Try to match a min/max vector operation.
18164 if (N->getOpcode() == ISD::VSELECT && Cond.getOpcode() == ISD::SETCC) {
18165 std::pair<unsigned, bool> ret = matchIntegerMINMAX(Cond, VT, LHS, RHS, DAG, Subtarget);
18166 unsigned Opc = ret.first;
18167 bool NeedSplit = ret.second;
18169 if (Opc && NeedSplit) {
18170 unsigned NumElems = VT.getVectorNumElements();
18171 // Extract the LHS vectors
18172 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, DL);
18173 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, DL);
18175 // Extract the RHS vectors
18176 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, DL);
18177 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, DL);
18179 // Create min/max for each subvector
18180 LHS = DAG.getNode(Opc, DL, LHS1.getValueType(), LHS1, RHS1);
18181 RHS = DAG.getNode(Opc, DL, LHS2.getValueType(), LHS2, RHS2);
18183 // Merge the result
18184 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, LHS, RHS);
18186 return DAG.getNode(Opc, DL, VT, LHS, RHS);
18189 // Simplify vector selection if the selector will be produced by CMPP*/PCMP*.
18190 if (N->getOpcode() == ISD::VSELECT && Cond.getOpcode() == ISD::SETCC &&
18191 // Check if SETCC has already been promoted
18192 TLI.getSetCCResultType(*DAG.getContext(), VT) == CondVT &&
18193 // Check that condition value type matches vselect operand type
18196 assert(Cond.getValueType().isVector() &&
18197 "vector select expects a vector selector!");
18199 bool TValIsAllOnes = ISD::isBuildVectorAllOnes(LHS.getNode());
18200 bool FValIsAllZeros = ISD::isBuildVectorAllZeros(RHS.getNode());
18202 if (!TValIsAllOnes && !FValIsAllZeros) {
18203 // Try invert the condition if true value is not all 1s and false value
18205 bool TValIsAllZeros = ISD::isBuildVectorAllZeros(LHS.getNode());
18206 bool FValIsAllOnes = ISD::isBuildVectorAllOnes(RHS.getNode());
18208 if (TValIsAllZeros || FValIsAllOnes) {
18209 SDValue CC = Cond.getOperand(2);
18210 ISD::CondCode NewCC =
18211 ISD::getSetCCInverse(cast<CondCodeSDNode>(CC)->get(),
18212 Cond.getOperand(0).getValueType().isInteger());
18213 Cond = DAG.getSetCC(DL, CondVT, Cond.getOperand(0), Cond.getOperand(1), NewCC);
18214 std::swap(LHS, RHS);
18215 TValIsAllOnes = FValIsAllOnes;
18216 FValIsAllZeros = TValIsAllZeros;
18220 if (TValIsAllOnes || FValIsAllZeros) {
18223 if (TValIsAllOnes && FValIsAllZeros)
18225 else if (TValIsAllOnes)
18226 Ret = DAG.getNode(ISD::OR, DL, CondVT, Cond,
18227 DAG.getNode(ISD::BITCAST, DL, CondVT, RHS));
18228 else if (FValIsAllZeros)
18229 Ret = DAG.getNode(ISD::AND, DL, CondVT, Cond,
18230 DAG.getNode(ISD::BITCAST, DL, CondVT, LHS));
18232 return DAG.getNode(ISD::BITCAST, DL, VT, Ret);
18236 // Try to fold this VSELECT into a MOVSS/MOVSD
18237 if (N->getOpcode() == ISD::VSELECT &&
18238 Cond.getOpcode() == ISD::BUILD_VECTOR && !DCI.isBeforeLegalize()) {
18239 if (VT == MVT::v4i32 || VT == MVT::v4f32 ||
18240 (Subtarget->hasSSE2() && (VT == MVT::v2i64 || VT == MVT::v2f64))) {
18241 bool CanFold = false;
18242 unsigned NumElems = Cond.getNumOperands();
18246 if (isZero(Cond.getOperand(0))) {
18249 // fold (vselect <0,-1,-1,-1>, A, B) -> (movss A, B)
18250 // fold (vselect <0,-1> -> (movsd A, B)
18251 for (unsigned i = 1, e = NumElems; i != e && CanFold; ++i)
18252 CanFold = isAllOnes(Cond.getOperand(i));
18253 } else if (isAllOnes(Cond.getOperand(0))) {
18257 // fold (vselect <-1,0,0,0>, A, B) -> (movss B, A)
18258 // fold (vselect <-1,0> -> (movsd B, A)
18259 for (unsigned i = 1, e = NumElems; i != e && CanFold; ++i)
18260 CanFold = isZero(Cond.getOperand(i));
18264 if (VT == MVT::v4i32 || VT == MVT::v4f32)
18265 return getTargetShuffleNode(X86ISD::MOVSS, DL, VT, A, B, DAG);
18266 return getTargetShuffleNode(X86ISD::MOVSD, DL, VT, A, B, DAG);
18269 if (Subtarget->hasSSE2() && (VT == MVT::v4i32 || VT == MVT::v4f32)) {
18270 // fold (v4i32: vselect <0,0,-1,-1>, A, B) ->
18271 // (v4i32 (bitcast (movsd (v2i64 (bitcast A)),
18272 // (v2i64 (bitcast B)))))
18274 // fold (v4f32: vselect <0,0,-1,-1>, A, B) ->
18275 // (v4f32 (bitcast (movsd (v2f64 (bitcast A)),
18276 // (v2f64 (bitcast B)))))
18278 // fold (v4i32: vselect <-1,-1,0,0>, A, B) ->
18279 // (v4i32 (bitcast (movsd (v2i64 (bitcast B)),
18280 // (v2i64 (bitcast A)))))
18282 // fold (v4f32: vselect <-1,-1,0,0>, A, B) ->
18283 // (v4f32 (bitcast (movsd (v2f64 (bitcast B)),
18284 // (v2f64 (bitcast A)))))
18286 CanFold = (isZero(Cond.getOperand(0)) &&
18287 isZero(Cond.getOperand(1)) &&
18288 isAllOnes(Cond.getOperand(2)) &&
18289 isAllOnes(Cond.getOperand(3)));
18291 if (!CanFold && isAllOnes(Cond.getOperand(0)) &&
18292 isAllOnes(Cond.getOperand(1)) &&
18293 isZero(Cond.getOperand(2)) &&
18294 isZero(Cond.getOperand(3))) {
18296 std::swap(LHS, RHS);
18300 EVT NVT = (VT == MVT::v4i32) ? MVT::v2i64 : MVT::v2f64;
18301 SDValue NewA = DAG.getNode(ISD::BITCAST, DL, NVT, LHS);
18302 SDValue NewB = DAG.getNode(ISD::BITCAST, DL, NVT, RHS);
18303 SDValue Select = getTargetShuffleNode(X86ISD::MOVSD, DL, NVT, NewA,
18305 return DAG.getNode(ISD::BITCAST, DL, VT, Select);
18311 // If we know that this node is legal then we know that it is going to be
18312 // matched by one of the SSE/AVX BLEND instructions. These instructions only
18313 // depend on the highest bit in each word. Try to use SimplifyDemandedBits
18314 // to simplify previous instructions.
18315 if (N->getOpcode() == ISD::VSELECT && DCI.isBeforeLegalizeOps() &&
18316 !DCI.isBeforeLegalize() &&
18317 // We explicitly check against v8i16 and v16i16 because, although
18318 // they're marked as Custom, they might only be legal when Cond is a
18319 // build_vector of constants. This will be taken care in a later
18321 (TLI.isOperationLegalOrCustom(ISD::VSELECT, VT) && VT != MVT::v16i16 &&
18322 VT != MVT::v8i16)) {
18323 unsigned BitWidth = Cond.getValueType().getScalarType().getSizeInBits();
18325 // Don't optimize vector selects that map to mask-registers.
18329 // Check all uses of that condition operand to check whether it will be
18330 // consumed by non-BLEND instructions, which may depend on all bits are set
18332 for (SDNode::use_iterator I = Cond->use_begin(),
18333 E = Cond->use_end(); I != E; ++I)
18334 if (I->getOpcode() != ISD::VSELECT)
18335 // TODO: Add other opcodes eventually lowered into BLEND.
18338 assert(BitWidth >= 8 && BitWidth <= 64 && "Invalid mask size");
18339 APInt DemandedMask = APInt::getHighBitsSet(BitWidth, 1);
18341 APInt KnownZero, KnownOne;
18342 TargetLowering::TargetLoweringOpt TLO(DAG, DCI.isBeforeLegalize(),
18343 DCI.isBeforeLegalizeOps());
18344 if (TLO.ShrinkDemandedConstant(Cond, DemandedMask) ||
18345 TLI.SimplifyDemandedBits(Cond, DemandedMask, KnownZero, KnownOne, TLO))
18346 DCI.CommitTargetLoweringOpt(TLO);
18349 // We should generate an X86ISD::BLENDI from a vselect if its argument
18350 // is a sign_extend_inreg of an any_extend of a BUILD_VECTOR of
18351 // constants. This specific pattern gets generated when we split a
18352 // selector for a 512 bit vector in a machine without AVX512 (but with
18353 // 256-bit vectors), during legalization:
18355 // (vselect (sign_extend (any_extend (BUILD_VECTOR)) i1) LHS RHS)
18357 // Iff we find this pattern and the build_vectors are built from
18358 // constants, we translate the vselect into a shuffle_vector that we
18359 // know will be matched by LowerVECTOR_SHUFFLEtoBlend.
18360 if (N->getOpcode() == ISD::VSELECT && !DCI.isBeforeLegalize()) {
18361 SDValue Shuffle = TransformVSELECTtoBlendVECTOR_SHUFFLE(N, DAG, Subtarget);
18362 if (Shuffle.getNode())
18369 // Check whether a boolean test is testing a boolean value generated by
18370 // X86ISD::SETCC. If so, return the operand of that SETCC and proper condition
18373 // Simplify the following patterns:
18374 // (Op (CMP (SETCC Cond EFLAGS) 1) EQ) or
18375 // (Op (CMP (SETCC Cond EFLAGS) 0) NEQ)
18376 // to (Op EFLAGS Cond)
18378 // (Op (CMP (SETCC Cond EFLAGS) 0) EQ) or
18379 // (Op (CMP (SETCC Cond EFLAGS) 1) NEQ)
18380 // to (Op EFLAGS !Cond)
18382 // where Op could be BRCOND or CMOV.
18384 static SDValue checkBoolTestSetCCCombine(SDValue Cmp, X86::CondCode &CC) {
18385 // Quit if not CMP and SUB with its value result used.
18386 if (Cmp.getOpcode() != X86ISD::CMP &&
18387 (Cmp.getOpcode() != X86ISD::SUB || Cmp.getNode()->hasAnyUseOfValue(0)))
18390 // Quit if not used as a boolean value.
18391 if (CC != X86::COND_E && CC != X86::COND_NE)
18394 // Check CMP operands. One of them should be 0 or 1 and the other should be
18395 // an SetCC or extended from it.
18396 SDValue Op1 = Cmp.getOperand(0);
18397 SDValue Op2 = Cmp.getOperand(1);
18400 const ConstantSDNode* C = nullptr;
18401 bool needOppositeCond = (CC == X86::COND_E);
18402 bool checkAgainstTrue = false; // Is it a comparison against 1?
18404 if ((C = dyn_cast<ConstantSDNode>(Op1)))
18406 else if ((C = dyn_cast<ConstantSDNode>(Op2)))
18408 else // Quit if all operands are not constants.
18411 if (C->getZExtValue() == 1) {
18412 needOppositeCond = !needOppositeCond;
18413 checkAgainstTrue = true;
18414 } else if (C->getZExtValue() != 0)
18415 // Quit if the constant is neither 0 or 1.
18418 bool truncatedToBoolWithAnd = false;
18419 // Skip (zext $x), (trunc $x), or (and $x, 1) node.
18420 while (SetCC.getOpcode() == ISD::ZERO_EXTEND ||
18421 SetCC.getOpcode() == ISD::TRUNCATE ||
18422 SetCC.getOpcode() == ISD::AND) {
18423 if (SetCC.getOpcode() == ISD::AND) {
18425 ConstantSDNode *CS;
18426 if ((CS = dyn_cast<ConstantSDNode>(SetCC.getOperand(0))) &&
18427 CS->getZExtValue() == 1)
18429 if ((CS = dyn_cast<ConstantSDNode>(SetCC.getOperand(1))) &&
18430 CS->getZExtValue() == 1)
18434 SetCC = SetCC.getOperand(OpIdx);
18435 truncatedToBoolWithAnd = true;
18437 SetCC = SetCC.getOperand(0);
18440 switch (SetCC.getOpcode()) {
18441 case X86ISD::SETCC_CARRY:
18442 // Since SETCC_CARRY gives output based on R = CF ? ~0 : 0, it's unsafe to
18443 // simplify it if the result of SETCC_CARRY is not canonicalized to 0 or 1,
18444 // i.e. it's a comparison against true but the result of SETCC_CARRY is not
18445 // truncated to i1 using 'and'.
18446 if (checkAgainstTrue && !truncatedToBoolWithAnd)
18448 assert(X86::CondCode(SetCC.getConstantOperandVal(0)) == X86::COND_B &&
18449 "Invalid use of SETCC_CARRY!");
18451 case X86ISD::SETCC:
18452 // Set the condition code or opposite one if necessary.
18453 CC = X86::CondCode(SetCC.getConstantOperandVal(0));
18454 if (needOppositeCond)
18455 CC = X86::GetOppositeBranchCondition(CC);
18456 return SetCC.getOperand(1);
18457 case X86ISD::CMOV: {
18458 // Check whether false/true value has canonical one, i.e. 0 or 1.
18459 ConstantSDNode *FVal = dyn_cast<ConstantSDNode>(SetCC.getOperand(0));
18460 ConstantSDNode *TVal = dyn_cast<ConstantSDNode>(SetCC.getOperand(1));
18461 // Quit if true value is not a constant.
18464 // Quit if false value is not a constant.
18466 SDValue Op = SetCC.getOperand(0);
18467 // Skip 'zext' or 'trunc' node.
18468 if (Op.getOpcode() == ISD::ZERO_EXTEND ||
18469 Op.getOpcode() == ISD::TRUNCATE)
18470 Op = Op.getOperand(0);
18471 // A special case for rdrand/rdseed, where 0 is set if false cond is
18473 if ((Op.getOpcode() != X86ISD::RDRAND &&
18474 Op.getOpcode() != X86ISD::RDSEED) || Op.getResNo() != 0)
18477 // Quit if false value is not the constant 0 or 1.
18478 bool FValIsFalse = true;
18479 if (FVal && FVal->getZExtValue() != 0) {
18480 if (FVal->getZExtValue() != 1)
18482 // If FVal is 1, opposite cond is needed.
18483 needOppositeCond = !needOppositeCond;
18484 FValIsFalse = false;
18486 // Quit if TVal is not the constant opposite of FVal.
18487 if (FValIsFalse && TVal->getZExtValue() != 1)
18489 if (!FValIsFalse && TVal->getZExtValue() != 0)
18491 CC = X86::CondCode(SetCC.getConstantOperandVal(2));
18492 if (needOppositeCond)
18493 CC = X86::GetOppositeBranchCondition(CC);
18494 return SetCC.getOperand(3);
18501 /// Optimize X86ISD::CMOV [LHS, RHS, CONDCODE (e.g. X86::COND_NE), CONDVAL]
18502 static SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG,
18503 TargetLowering::DAGCombinerInfo &DCI,
18504 const X86Subtarget *Subtarget) {
18507 // If the flag operand isn't dead, don't touch this CMOV.
18508 if (N->getNumValues() == 2 && !SDValue(N, 1).use_empty())
18511 SDValue FalseOp = N->getOperand(0);
18512 SDValue TrueOp = N->getOperand(1);
18513 X86::CondCode CC = (X86::CondCode)N->getConstantOperandVal(2);
18514 SDValue Cond = N->getOperand(3);
18516 if (CC == X86::COND_E || CC == X86::COND_NE) {
18517 switch (Cond.getOpcode()) {
18521 // If operand of BSR / BSF are proven never zero, then ZF cannot be set.
18522 if (DAG.isKnownNeverZero(Cond.getOperand(0)))
18523 return (CC == X86::COND_E) ? FalseOp : TrueOp;
18529 Flags = checkBoolTestSetCCCombine(Cond, CC);
18530 if (Flags.getNode() &&
18531 // Extra check as FCMOV only supports a subset of X86 cond.
18532 (FalseOp.getValueType() != MVT::f80 || hasFPCMov(CC))) {
18533 SDValue Ops[] = { FalseOp, TrueOp,
18534 DAG.getConstant(CC, MVT::i8), Flags };
18535 return DAG.getNode(X86ISD::CMOV, DL, N->getVTList(), Ops);
18538 // If this is a select between two integer constants, try to do some
18539 // optimizations. Note that the operands are ordered the opposite of SELECT
18541 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(TrueOp)) {
18542 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(FalseOp)) {
18543 // Canonicalize the TrueC/FalseC values so that TrueC (the true value) is
18544 // larger than FalseC (the false value).
18545 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue())) {
18546 CC = X86::GetOppositeBranchCondition(CC);
18547 std::swap(TrueC, FalseC);
18548 std::swap(TrueOp, FalseOp);
18551 // Optimize C ? 8 : 0 -> zext(setcc(C)) << 3. Likewise for any pow2/0.
18552 // This is efficient for any integer data type (including i8/i16) and
18554 if (FalseC->getAPIntValue() == 0 && TrueC->getAPIntValue().isPowerOf2()) {
18555 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
18556 DAG.getConstant(CC, MVT::i8), Cond);
18558 // Zero extend the condition if needed.
18559 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, TrueC->getValueType(0), Cond);
18561 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
18562 Cond = DAG.getNode(ISD::SHL, DL, Cond.getValueType(), Cond,
18563 DAG.getConstant(ShAmt, MVT::i8));
18564 if (N->getNumValues() == 2) // Dead flag value?
18565 return DCI.CombineTo(N, Cond, SDValue());
18569 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst. This is efficient
18570 // for any integer data type, including i8/i16.
18571 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
18572 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
18573 DAG.getConstant(CC, MVT::i8), Cond);
18575 // Zero extend the condition if needed.
18576 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
18577 FalseC->getValueType(0), Cond);
18578 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
18579 SDValue(FalseC, 0));
18581 if (N->getNumValues() == 2) // Dead flag value?
18582 return DCI.CombineTo(N, Cond, SDValue());
18586 // Optimize cases that will turn into an LEA instruction. This requires
18587 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
18588 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
18589 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
18590 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
18592 bool isFastMultiplier = false;
18594 switch ((unsigned char)Diff) {
18596 case 1: // result = add base, cond
18597 case 2: // result = lea base( , cond*2)
18598 case 3: // result = lea base(cond, cond*2)
18599 case 4: // result = lea base( , cond*4)
18600 case 5: // result = lea base(cond, cond*4)
18601 case 8: // result = lea base( , cond*8)
18602 case 9: // result = lea base(cond, cond*8)
18603 isFastMultiplier = true;
18608 if (isFastMultiplier) {
18609 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
18610 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
18611 DAG.getConstant(CC, MVT::i8), Cond);
18612 // Zero extend the condition if needed.
18613 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
18615 // Scale the condition by the difference.
18617 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
18618 DAG.getConstant(Diff, Cond.getValueType()));
18620 // Add the base if non-zero.
18621 if (FalseC->getAPIntValue() != 0)
18622 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
18623 SDValue(FalseC, 0));
18624 if (N->getNumValues() == 2) // Dead flag value?
18625 return DCI.CombineTo(N, Cond, SDValue());
18632 // Handle these cases:
18633 // (select (x != c), e, c) -> select (x != c), e, x),
18634 // (select (x == c), c, e) -> select (x == c), x, e)
18635 // where the c is an integer constant, and the "select" is the combination
18636 // of CMOV and CMP.
18638 // The rationale for this change is that the conditional-move from a constant
18639 // needs two instructions, however, conditional-move from a register needs
18640 // only one instruction.
18642 // CAVEAT: By replacing a constant with a symbolic value, it may obscure
18643 // some instruction-combining opportunities. This opt needs to be
18644 // postponed as late as possible.
18646 if (!DCI.isBeforeLegalize() && !DCI.isBeforeLegalizeOps()) {
18647 // the DCI.xxxx conditions are provided to postpone the optimization as
18648 // late as possible.
18650 ConstantSDNode *CmpAgainst = nullptr;
18651 if ((Cond.getOpcode() == X86ISD::CMP || Cond.getOpcode() == X86ISD::SUB) &&
18652 (CmpAgainst = dyn_cast<ConstantSDNode>(Cond.getOperand(1))) &&
18653 !isa<ConstantSDNode>(Cond.getOperand(0))) {
18655 if (CC == X86::COND_NE &&
18656 CmpAgainst == dyn_cast<ConstantSDNode>(FalseOp)) {
18657 CC = X86::GetOppositeBranchCondition(CC);
18658 std::swap(TrueOp, FalseOp);
18661 if (CC == X86::COND_E &&
18662 CmpAgainst == dyn_cast<ConstantSDNode>(TrueOp)) {
18663 SDValue Ops[] = { FalseOp, Cond.getOperand(0),
18664 DAG.getConstant(CC, MVT::i8), Cond };
18665 return DAG.getNode(X86ISD::CMOV, DL, N->getVTList (), Ops);
18673 static SDValue PerformINTRINSIC_WO_CHAINCombine(SDNode *N, SelectionDAG &DAG,
18674 const X86Subtarget *Subtarget) {
18675 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(0))->getZExtValue();
18677 default: return SDValue();
18678 // SSE/AVX/AVX2 blend intrinsics.
18679 case Intrinsic::x86_avx2_pblendvb:
18680 case Intrinsic::x86_avx2_pblendw:
18681 case Intrinsic::x86_avx2_pblendd_128:
18682 case Intrinsic::x86_avx2_pblendd_256:
18683 // Don't try to simplify this intrinsic if we don't have AVX2.
18684 if (!Subtarget->hasAVX2())
18687 case Intrinsic::x86_avx_blend_pd_256:
18688 case Intrinsic::x86_avx_blend_ps_256:
18689 case Intrinsic::x86_avx_blendv_pd_256:
18690 case Intrinsic::x86_avx_blendv_ps_256:
18691 // Don't try to simplify this intrinsic if we don't have AVX.
18692 if (!Subtarget->hasAVX())
18695 case Intrinsic::x86_sse41_pblendw:
18696 case Intrinsic::x86_sse41_blendpd:
18697 case Intrinsic::x86_sse41_blendps:
18698 case Intrinsic::x86_sse41_blendvps:
18699 case Intrinsic::x86_sse41_blendvpd:
18700 case Intrinsic::x86_sse41_pblendvb: {
18701 SDValue Op0 = N->getOperand(1);
18702 SDValue Op1 = N->getOperand(2);
18703 SDValue Mask = N->getOperand(3);
18705 // Don't try to simplify this intrinsic if we don't have SSE4.1.
18706 if (!Subtarget->hasSSE41())
18709 // fold (blend A, A, Mask) -> A
18712 // fold (blend A, B, allZeros) -> A
18713 if (ISD::isBuildVectorAllZeros(Mask.getNode()))
18715 // fold (blend A, B, allOnes) -> B
18716 if (ISD::isBuildVectorAllOnes(Mask.getNode()))
18719 // Simplify the case where the mask is a constant i32 value.
18720 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Mask)) {
18721 if (C->isNullValue())
18723 if (C->isAllOnesValue())
18728 // Packed SSE2/AVX2 arithmetic shift immediate intrinsics.
18729 case Intrinsic::x86_sse2_psrai_w:
18730 case Intrinsic::x86_sse2_psrai_d:
18731 case Intrinsic::x86_avx2_psrai_w:
18732 case Intrinsic::x86_avx2_psrai_d:
18733 case Intrinsic::x86_sse2_psra_w:
18734 case Intrinsic::x86_sse2_psra_d:
18735 case Intrinsic::x86_avx2_psra_w:
18736 case Intrinsic::x86_avx2_psra_d: {
18737 SDValue Op0 = N->getOperand(1);
18738 SDValue Op1 = N->getOperand(2);
18739 EVT VT = Op0.getValueType();
18740 assert(VT.isVector() && "Expected a vector type!");
18742 if (isa<BuildVectorSDNode>(Op1))
18743 Op1 = Op1.getOperand(0);
18745 if (!isa<ConstantSDNode>(Op1))
18748 EVT SVT = VT.getVectorElementType();
18749 unsigned SVTBits = SVT.getSizeInBits();
18751 ConstantSDNode *CND = cast<ConstantSDNode>(Op1);
18752 const APInt &C = APInt(SVTBits, CND->getAPIntValue().getZExtValue());
18753 uint64_t ShAmt = C.getZExtValue();
18755 // Don't try to convert this shift into a ISD::SRA if the shift
18756 // count is bigger than or equal to the element size.
18757 if (ShAmt >= SVTBits)
18760 // Trivial case: if the shift count is zero, then fold this
18761 // into the first operand.
18765 // Replace this packed shift intrinsic with a target independent
18767 SDValue Splat = DAG.getConstant(C, VT);
18768 return DAG.getNode(ISD::SRA, SDLoc(N), VT, Op0, Splat);
18773 /// PerformMulCombine - Optimize a single multiply with constant into two
18774 /// in order to implement it with two cheaper instructions, e.g.
18775 /// LEA + SHL, LEA + LEA.
18776 static SDValue PerformMulCombine(SDNode *N, SelectionDAG &DAG,
18777 TargetLowering::DAGCombinerInfo &DCI) {
18778 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer())
18781 EVT VT = N->getValueType(0);
18782 if (VT != MVT::i64)
18785 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
18788 uint64_t MulAmt = C->getZExtValue();
18789 if (isPowerOf2_64(MulAmt) || MulAmt == 3 || MulAmt == 5 || MulAmt == 9)
18792 uint64_t MulAmt1 = 0;
18793 uint64_t MulAmt2 = 0;
18794 if ((MulAmt % 9) == 0) {
18796 MulAmt2 = MulAmt / 9;
18797 } else if ((MulAmt % 5) == 0) {
18799 MulAmt2 = MulAmt / 5;
18800 } else if ((MulAmt % 3) == 0) {
18802 MulAmt2 = MulAmt / 3;
18805 (isPowerOf2_64(MulAmt2) || MulAmt2 == 3 || MulAmt2 == 5 || MulAmt2 == 9)){
18808 if (isPowerOf2_64(MulAmt2) &&
18809 !(N->hasOneUse() && N->use_begin()->getOpcode() == ISD::ADD))
18810 // If second multiplifer is pow2, issue it first. We want the multiply by
18811 // 3, 5, or 9 to be folded into the addressing mode unless the lone use
18813 std::swap(MulAmt1, MulAmt2);
18816 if (isPowerOf2_64(MulAmt1))
18817 NewMul = DAG.getNode(ISD::SHL, DL, VT, N->getOperand(0),
18818 DAG.getConstant(Log2_64(MulAmt1), MVT::i8));
18820 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, N->getOperand(0),
18821 DAG.getConstant(MulAmt1, VT));
18823 if (isPowerOf2_64(MulAmt2))
18824 NewMul = DAG.getNode(ISD::SHL, DL, VT, NewMul,
18825 DAG.getConstant(Log2_64(MulAmt2), MVT::i8));
18827 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, NewMul,
18828 DAG.getConstant(MulAmt2, VT));
18830 // Do not add new nodes to DAG combiner worklist.
18831 DCI.CombineTo(N, NewMul, false);
18836 static SDValue PerformSHLCombine(SDNode *N, SelectionDAG &DAG) {
18837 SDValue N0 = N->getOperand(0);
18838 SDValue N1 = N->getOperand(1);
18839 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
18840 EVT VT = N0.getValueType();
18842 // fold (shl (and (setcc_c), c1), c2) -> (and setcc_c, (c1 << c2))
18843 // since the result of setcc_c is all zero's or all ones.
18844 if (VT.isInteger() && !VT.isVector() &&
18845 N1C && N0.getOpcode() == ISD::AND &&
18846 N0.getOperand(1).getOpcode() == ISD::Constant) {
18847 SDValue N00 = N0.getOperand(0);
18848 if (N00.getOpcode() == X86ISD::SETCC_CARRY ||
18849 ((N00.getOpcode() == ISD::ANY_EXTEND ||
18850 N00.getOpcode() == ISD::ZERO_EXTEND) &&
18851 N00.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY)) {
18852 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
18853 APInt ShAmt = N1C->getAPIntValue();
18854 Mask = Mask.shl(ShAmt);
18856 return DAG.getNode(ISD::AND, SDLoc(N), VT,
18857 N00, DAG.getConstant(Mask, VT));
18861 // Hardware support for vector shifts is sparse which makes us scalarize the
18862 // vector operations in many cases. Also, on sandybridge ADD is faster than
18864 // (shl V, 1) -> add V,V
18865 if (isSplatVector(N1.getNode())) {
18866 assert(N0.getValueType().isVector() && "Invalid vector shift type");
18867 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1->getOperand(0));
18868 // We shift all of the values by one. In many cases we do not have
18869 // hardware support for this operation. This is better expressed as an ADD
18871 if (N1C && (1 == N1C->getZExtValue())) {
18872 return DAG.getNode(ISD::ADD, SDLoc(N), VT, N0, N0);
18879 /// \brief Returns a vector of 0s if the node in input is a vector logical
18880 /// shift by a constant amount which is known to be bigger than or equal
18881 /// to the vector element size in bits.
18882 static SDValue performShiftToAllZeros(SDNode *N, SelectionDAG &DAG,
18883 const X86Subtarget *Subtarget) {
18884 EVT VT = N->getValueType(0);
18886 if (VT != MVT::v2i64 && VT != MVT::v4i32 && VT != MVT::v8i16 &&
18887 (!Subtarget->hasInt256() ||
18888 (VT != MVT::v4i64 && VT != MVT::v8i32 && VT != MVT::v16i16)))
18891 SDValue Amt = N->getOperand(1);
18893 if (isSplatVector(Amt.getNode())) {
18894 SDValue SclrAmt = Amt->getOperand(0);
18895 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(SclrAmt)) {
18896 APInt ShiftAmt = C->getAPIntValue();
18897 unsigned MaxAmount = VT.getVectorElementType().getSizeInBits();
18899 // SSE2/AVX2 logical shifts always return a vector of 0s
18900 // if the shift amount is bigger than or equal to
18901 // the element size. The constant shift amount will be
18902 // encoded as a 8-bit immediate.
18903 if (ShiftAmt.trunc(8).uge(MaxAmount))
18904 return getZeroVector(VT, Subtarget, DAG, DL);
18911 /// PerformShiftCombine - Combine shifts.
18912 static SDValue PerformShiftCombine(SDNode* N, SelectionDAG &DAG,
18913 TargetLowering::DAGCombinerInfo &DCI,
18914 const X86Subtarget *Subtarget) {
18915 if (N->getOpcode() == ISD::SHL) {
18916 SDValue V = PerformSHLCombine(N, DAG);
18917 if (V.getNode()) return V;
18920 if (N->getOpcode() != ISD::SRA) {
18921 // Try to fold this logical shift into a zero vector.
18922 SDValue V = performShiftToAllZeros(N, DAG, Subtarget);
18923 if (V.getNode()) return V;
18929 // CMPEQCombine - Recognize the distinctive (AND (setcc ...) (setcc ..))
18930 // where both setccs reference the same FP CMP, and rewrite for CMPEQSS
18931 // and friends. Likewise for OR -> CMPNEQSS.
18932 static SDValue CMPEQCombine(SDNode *N, SelectionDAG &DAG,
18933 TargetLowering::DAGCombinerInfo &DCI,
18934 const X86Subtarget *Subtarget) {
18937 // SSE1 supports CMP{eq|ne}SS, and SSE2 added CMP{eq|ne}SD, but
18938 // we're requiring SSE2 for both.
18939 if (Subtarget->hasSSE2() && isAndOrOfSetCCs(SDValue(N, 0U), opcode)) {
18940 SDValue N0 = N->getOperand(0);
18941 SDValue N1 = N->getOperand(1);
18942 SDValue CMP0 = N0->getOperand(1);
18943 SDValue CMP1 = N1->getOperand(1);
18946 // The SETCCs should both refer to the same CMP.
18947 if (CMP0.getOpcode() != X86ISD::CMP || CMP0 != CMP1)
18950 SDValue CMP00 = CMP0->getOperand(0);
18951 SDValue CMP01 = CMP0->getOperand(1);
18952 EVT VT = CMP00.getValueType();
18954 if (VT == MVT::f32 || VT == MVT::f64) {
18955 bool ExpectingFlags = false;
18956 // Check for any users that want flags:
18957 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end();
18958 !ExpectingFlags && UI != UE; ++UI)
18959 switch (UI->getOpcode()) {
18964 ExpectingFlags = true;
18966 case ISD::CopyToReg:
18967 case ISD::SIGN_EXTEND:
18968 case ISD::ZERO_EXTEND:
18969 case ISD::ANY_EXTEND:
18973 if (!ExpectingFlags) {
18974 enum X86::CondCode cc0 = (enum X86::CondCode)N0.getConstantOperandVal(0);
18975 enum X86::CondCode cc1 = (enum X86::CondCode)N1.getConstantOperandVal(0);
18977 if (cc1 == X86::COND_E || cc1 == X86::COND_NE) {
18978 X86::CondCode tmp = cc0;
18983 if ((cc0 == X86::COND_E && cc1 == X86::COND_NP) ||
18984 (cc0 == X86::COND_NE && cc1 == X86::COND_P)) {
18985 // FIXME: need symbolic constants for these magic numbers.
18986 // See X86ATTInstPrinter.cpp:printSSECC().
18987 unsigned x86cc = (cc0 == X86::COND_E) ? 0 : 4;
18988 if (Subtarget->hasAVX512()) {
18989 SDValue FSetCC = DAG.getNode(X86ISD::FSETCC, DL, MVT::i1, CMP00,
18990 CMP01, DAG.getConstant(x86cc, MVT::i8));
18991 if (N->getValueType(0) != MVT::i1)
18992 return DAG.getNode(ISD::ZERO_EXTEND, DL, N->getValueType(0),
18996 SDValue OnesOrZeroesF = DAG.getNode(X86ISD::FSETCC, DL,
18997 CMP00.getValueType(), CMP00, CMP01,
18998 DAG.getConstant(x86cc, MVT::i8));
19000 bool is64BitFP = (CMP00.getValueType() == MVT::f64);
19001 MVT IntVT = is64BitFP ? MVT::i64 : MVT::i32;
19003 if (is64BitFP && !Subtarget->is64Bit()) {
19004 // On a 32-bit target, we cannot bitcast the 64-bit float to a
19005 // 64-bit integer, since that's not a legal type. Since
19006 // OnesOrZeroesF is all ones of all zeroes, we don't need all the
19007 // bits, but can do this little dance to extract the lowest 32 bits
19008 // and work with those going forward.
19009 SDValue Vector64 = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, MVT::v2f64,
19011 SDValue Vector32 = DAG.getNode(ISD::BITCAST, DL, MVT::v4f32,
19013 OnesOrZeroesF = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32,
19014 Vector32, DAG.getIntPtrConstant(0));
19018 SDValue OnesOrZeroesI = DAG.getNode(ISD::BITCAST, DL, IntVT, OnesOrZeroesF);
19019 SDValue ANDed = DAG.getNode(ISD::AND, DL, IntVT, OnesOrZeroesI,
19020 DAG.getConstant(1, IntVT));
19021 SDValue OneBitOfTruth = DAG.getNode(ISD::TRUNCATE, DL, MVT::i8, ANDed);
19022 return OneBitOfTruth;
19030 /// CanFoldXORWithAllOnes - Test whether the XOR operand is a AllOnes vector
19031 /// so it can be folded inside ANDNP.
19032 static bool CanFoldXORWithAllOnes(const SDNode *N) {
19033 EVT VT = N->getValueType(0);
19035 // Match direct AllOnes for 128 and 256-bit vectors
19036 if (ISD::isBuildVectorAllOnes(N))
19039 // Look through a bit convert.
19040 if (N->getOpcode() == ISD::BITCAST)
19041 N = N->getOperand(0).getNode();
19043 // Sometimes the operand may come from a insert_subvector building a 256-bit
19045 if (VT.is256BitVector() &&
19046 N->getOpcode() == ISD::INSERT_SUBVECTOR) {
19047 SDValue V1 = N->getOperand(0);
19048 SDValue V2 = N->getOperand(1);
19050 if (V1.getOpcode() == ISD::INSERT_SUBVECTOR &&
19051 V1.getOperand(0).getOpcode() == ISD::UNDEF &&
19052 ISD::isBuildVectorAllOnes(V1.getOperand(1).getNode()) &&
19053 ISD::isBuildVectorAllOnes(V2.getNode()))
19060 // On AVX/AVX2 the type v8i1 is legalized to v8i16, which is an XMM sized
19061 // register. In most cases we actually compare or select YMM-sized registers
19062 // and mixing the two types creates horrible code. This method optimizes
19063 // some of the transition sequences.
19064 static SDValue WidenMaskArithmetic(SDNode *N, SelectionDAG &DAG,
19065 TargetLowering::DAGCombinerInfo &DCI,
19066 const X86Subtarget *Subtarget) {
19067 EVT VT = N->getValueType(0);
19068 if (!VT.is256BitVector())
19071 assert((N->getOpcode() == ISD::ANY_EXTEND ||
19072 N->getOpcode() == ISD::ZERO_EXTEND ||
19073 N->getOpcode() == ISD::SIGN_EXTEND) && "Invalid Node");
19075 SDValue Narrow = N->getOperand(0);
19076 EVT NarrowVT = Narrow->getValueType(0);
19077 if (!NarrowVT.is128BitVector())
19080 if (Narrow->getOpcode() != ISD::XOR &&
19081 Narrow->getOpcode() != ISD::AND &&
19082 Narrow->getOpcode() != ISD::OR)
19085 SDValue N0 = Narrow->getOperand(0);
19086 SDValue N1 = Narrow->getOperand(1);
19089 // The Left side has to be a trunc.
19090 if (N0.getOpcode() != ISD::TRUNCATE)
19093 // The type of the truncated inputs.
19094 EVT WideVT = N0->getOperand(0)->getValueType(0);
19098 // The right side has to be a 'trunc' or a constant vector.
19099 bool RHSTrunc = N1.getOpcode() == ISD::TRUNCATE;
19100 bool RHSConst = (isSplatVector(N1.getNode()) &&
19101 isa<ConstantSDNode>(N1->getOperand(0)));
19102 if (!RHSTrunc && !RHSConst)
19105 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
19107 if (!TLI.isOperationLegalOrPromote(Narrow->getOpcode(), WideVT))
19110 // Set N0 and N1 to hold the inputs to the new wide operation.
19111 N0 = N0->getOperand(0);
19113 N1 = DAG.getNode(ISD::ZERO_EXTEND, DL, WideVT.getScalarType(),
19114 N1->getOperand(0));
19115 SmallVector<SDValue, 8> C(WideVT.getVectorNumElements(), N1);
19116 N1 = DAG.getNode(ISD::BUILD_VECTOR, DL, WideVT, C);
19117 } else if (RHSTrunc) {
19118 N1 = N1->getOperand(0);
19121 // Generate the wide operation.
19122 SDValue Op = DAG.getNode(Narrow->getOpcode(), DL, WideVT, N0, N1);
19123 unsigned Opcode = N->getOpcode();
19125 case ISD::ANY_EXTEND:
19127 case ISD::ZERO_EXTEND: {
19128 unsigned InBits = NarrowVT.getScalarType().getSizeInBits();
19129 APInt Mask = APInt::getAllOnesValue(InBits);
19130 Mask = Mask.zext(VT.getScalarType().getSizeInBits());
19131 return DAG.getNode(ISD::AND, DL, VT,
19132 Op, DAG.getConstant(Mask, VT));
19134 case ISD::SIGN_EXTEND:
19135 return DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, VT,
19136 Op, DAG.getValueType(NarrowVT));
19138 llvm_unreachable("Unexpected opcode");
19142 static SDValue PerformAndCombine(SDNode *N, SelectionDAG &DAG,
19143 TargetLowering::DAGCombinerInfo &DCI,
19144 const X86Subtarget *Subtarget) {
19145 EVT VT = N->getValueType(0);
19146 if (DCI.isBeforeLegalizeOps())
19149 SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget);
19153 // Create BEXTR instructions
19154 // BEXTR is ((X >> imm) & (2**size-1))
19155 if (VT == MVT::i32 || VT == MVT::i64) {
19156 SDValue N0 = N->getOperand(0);
19157 SDValue N1 = N->getOperand(1);
19160 // Check for BEXTR.
19161 if ((Subtarget->hasBMI() || Subtarget->hasTBM()) &&
19162 (N0.getOpcode() == ISD::SRA || N0.getOpcode() == ISD::SRL)) {
19163 ConstantSDNode *MaskNode = dyn_cast<ConstantSDNode>(N1);
19164 ConstantSDNode *ShiftNode = dyn_cast<ConstantSDNode>(N0.getOperand(1));
19165 if (MaskNode && ShiftNode) {
19166 uint64_t Mask = MaskNode->getZExtValue();
19167 uint64_t Shift = ShiftNode->getZExtValue();
19168 if (isMask_64(Mask)) {
19169 uint64_t MaskSize = CountPopulation_64(Mask);
19170 if (Shift + MaskSize <= VT.getSizeInBits())
19171 return DAG.getNode(X86ISD::BEXTR, DL, VT, N0.getOperand(0),
19172 DAG.getConstant(Shift | (MaskSize << 8), VT));
19180 // Want to form ANDNP nodes:
19181 // 1) In the hopes of then easily combining them with OR and AND nodes
19182 // to form PBLEND/PSIGN.
19183 // 2) To match ANDN packed intrinsics
19184 if (VT != MVT::v2i64 && VT != MVT::v4i64)
19187 SDValue N0 = N->getOperand(0);
19188 SDValue N1 = N->getOperand(1);
19191 // Check LHS for vnot
19192 if (N0.getOpcode() == ISD::XOR &&
19193 //ISD::isBuildVectorAllOnes(N0.getOperand(1).getNode()))
19194 CanFoldXORWithAllOnes(N0.getOperand(1).getNode()))
19195 return DAG.getNode(X86ISD::ANDNP, DL, VT, N0.getOperand(0), N1);
19197 // Check RHS for vnot
19198 if (N1.getOpcode() == ISD::XOR &&
19199 //ISD::isBuildVectorAllOnes(N1.getOperand(1).getNode()))
19200 CanFoldXORWithAllOnes(N1.getOperand(1).getNode()))
19201 return DAG.getNode(X86ISD::ANDNP, DL, VT, N1.getOperand(0), N0);
19206 static SDValue PerformOrCombine(SDNode *N, SelectionDAG &DAG,
19207 TargetLowering::DAGCombinerInfo &DCI,
19208 const X86Subtarget *Subtarget) {
19209 if (DCI.isBeforeLegalizeOps())
19212 SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget);
19216 SDValue N0 = N->getOperand(0);
19217 SDValue N1 = N->getOperand(1);
19218 EVT VT = N->getValueType(0);
19220 // look for psign/blend
19221 if (VT == MVT::v2i64 || VT == MVT::v4i64) {
19222 if (!Subtarget->hasSSSE3() ||
19223 (VT == MVT::v4i64 && !Subtarget->hasInt256()))
19226 // Canonicalize pandn to RHS
19227 if (N0.getOpcode() == X86ISD::ANDNP)
19229 // or (and (m, y), (pandn m, x))
19230 if (N0.getOpcode() == ISD::AND && N1.getOpcode() == X86ISD::ANDNP) {
19231 SDValue Mask = N1.getOperand(0);
19232 SDValue X = N1.getOperand(1);
19234 if (N0.getOperand(0) == Mask)
19235 Y = N0.getOperand(1);
19236 if (N0.getOperand(1) == Mask)
19237 Y = N0.getOperand(0);
19239 // Check to see if the mask appeared in both the AND and ANDNP and
19243 // Validate that X, Y, and Mask are BIT_CONVERTS, and see through them.
19244 // Look through mask bitcast.
19245 if (Mask.getOpcode() == ISD::BITCAST)
19246 Mask = Mask.getOperand(0);
19247 if (X.getOpcode() == ISD::BITCAST)
19248 X = X.getOperand(0);
19249 if (Y.getOpcode() == ISD::BITCAST)
19250 Y = Y.getOperand(0);
19252 EVT MaskVT = Mask.getValueType();
19254 // Validate that the Mask operand is a vector sra node.
19255 // FIXME: what to do for bytes, since there is a psignb/pblendvb, but
19256 // there is no psrai.b
19257 unsigned EltBits = MaskVT.getVectorElementType().getSizeInBits();
19258 unsigned SraAmt = ~0;
19259 if (Mask.getOpcode() == ISD::SRA) {
19260 SDValue Amt = Mask.getOperand(1);
19261 if (isSplatVector(Amt.getNode())) {
19262 SDValue SclrAmt = Amt->getOperand(0);
19263 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(SclrAmt))
19264 SraAmt = C->getZExtValue();
19266 } else if (Mask.getOpcode() == X86ISD::VSRAI) {
19267 SDValue SraC = Mask.getOperand(1);
19268 SraAmt = cast<ConstantSDNode>(SraC)->getZExtValue();
19270 if ((SraAmt + 1) != EltBits)
19275 // Now we know we at least have a plendvb with the mask val. See if
19276 // we can form a psignb/w/d.
19277 // psign = x.type == y.type == mask.type && y = sub(0, x);
19278 if (Y.getOpcode() == ISD::SUB && Y.getOperand(1) == X &&
19279 ISD::isBuildVectorAllZeros(Y.getOperand(0).getNode()) &&
19280 X.getValueType() == MaskVT && Y.getValueType() == MaskVT) {
19281 assert((EltBits == 8 || EltBits == 16 || EltBits == 32) &&
19282 "Unsupported VT for PSIGN");
19283 Mask = DAG.getNode(X86ISD::PSIGN, DL, MaskVT, X, Mask.getOperand(0));
19284 return DAG.getNode(ISD::BITCAST, DL, VT, Mask);
19286 // PBLENDVB only available on SSE 4.1
19287 if (!Subtarget->hasSSE41())
19290 EVT BlendVT = (VT == MVT::v4i64) ? MVT::v32i8 : MVT::v16i8;
19292 X = DAG.getNode(ISD::BITCAST, DL, BlendVT, X);
19293 Y = DAG.getNode(ISD::BITCAST, DL, BlendVT, Y);
19294 Mask = DAG.getNode(ISD::BITCAST, DL, BlendVT, Mask);
19295 Mask = DAG.getNode(ISD::VSELECT, DL, BlendVT, Mask, Y, X);
19296 return DAG.getNode(ISD::BITCAST, DL, VT, Mask);
19300 if (VT != MVT::i16 && VT != MVT::i32 && VT != MVT::i64)
19303 // fold (or (x << c) | (y >> (64 - c))) ==> (shld64 x, y, c)
19304 MachineFunction &MF = DAG.getMachineFunction();
19305 bool OptForSize = MF.getFunction()->getAttributes().
19306 hasAttribute(AttributeSet::FunctionIndex, Attribute::OptimizeForSize);
19308 // SHLD/SHRD instructions have lower register pressure, but on some
19309 // platforms they have higher latency than the equivalent
19310 // series of shifts/or that would otherwise be generated.
19311 // Don't fold (or (x << c) | (y >> (64 - c))) if SHLD/SHRD instructions
19312 // have higher latencies and we are not optimizing for size.
19313 if (!OptForSize && Subtarget->isSHLDSlow())
19316 if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL)
19318 if (N0.getOpcode() != ISD::SHL || N1.getOpcode() != ISD::SRL)
19320 if (!N0.hasOneUse() || !N1.hasOneUse())
19323 SDValue ShAmt0 = N0.getOperand(1);
19324 if (ShAmt0.getValueType() != MVT::i8)
19326 SDValue ShAmt1 = N1.getOperand(1);
19327 if (ShAmt1.getValueType() != MVT::i8)
19329 if (ShAmt0.getOpcode() == ISD::TRUNCATE)
19330 ShAmt0 = ShAmt0.getOperand(0);
19331 if (ShAmt1.getOpcode() == ISD::TRUNCATE)
19332 ShAmt1 = ShAmt1.getOperand(0);
19335 unsigned Opc = X86ISD::SHLD;
19336 SDValue Op0 = N0.getOperand(0);
19337 SDValue Op1 = N1.getOperand(0);
19338 if (ShAmt0.getOpcode() == ISD::SUB) {
19339 Opc = X86ISD::SHRD;
19340 std::swap(Op0, Op1);
19341 std::swap(ShAmt0, ShAmt1);
19344 unsigned Bits = VT.getSizeInBits();
19345 if (ShAmt1.getOpcode() == ISD::SUB) {
19346 SDValue Sum = ShAmt1.getOperand(0);
19347 if (ConstantSDNode *SumC = dyn_cast<ConstantSDNode>(Sum)) {
19348 SDValue ShAmt1Op1 = ShAmt1.getOperand(1);
19349 if (ShAmt1Op1.getNode()->getOpcode() == ISD::TRUNCATE)
19350 ShAmt1Op1 = ShAmt1Op1.getOperand(0);
19351 if (SumC->getSExtValue() == Bits && ShAmt1Op1 == ShAmt0)
19352 return DAG.getNode(Opc, DL, VT,
19354 DAG.getNode(ISD::TRUNCATE, DL,
19357 } else if (ConstantSDNode *ShAmt1C = dyn_cast<ConstantSDNode>(ShAmt1)) {
19358 ConstantSDNode *ShAmt0C = dyn_cast<ConstantSDNode>(ShAmt0);
19360 ShAmt0C->getSExtValue() + ShAmt1C->getSExtValue() == Bits)
19361 return DAG.getNode(Opc, DL, VT,
19362 N0.getOperand(0), N1.getOperand(0),
19363 DAG.getNode(ISD::TRUNCATE, DL,
19370 // Generate NEG and CMOV for integer abs.
19371 static SDValue performIntegerAbsCombine(SDNode *N, SelectionDAG &DAG) {
19372 EVT VT = N->getValueType(0);
19374 // Since X86 does not have CMOV for 8-bit integer, we don't convert
19375 // 8-bit integer abs to NEG and CMOV.
19376 if (VT.isInteger() && VT.getSizeInBits() == 8)
19379 SDValue N0 = N->getOperand(0);
19380 SDValue N1 = N->getOperand(1);
19383 // Check pattern of XOR(ADD(X,Y), Y) where Y is SRA(X, size(X)-1)
19384 // and change it to SUB and CMOV.
19385 if (VT.isInteger() && N->getOpcode() == ISD::XOR &&
19386 N0.getOpcode() == ISD::ADD &&
19387 N0.getOperand(1) == N1 &&
19388 N1.getOpcode() == ISD::SRA &&
19389 N1.getOperand(0) == N0.getOperand(0))
19390 if (ConstantSDNode *Y1C = dyn_cast<ConstantSDNode>(N1.getOperand(1)))
19391 if (Y1C->getAPIntValue() == VT.getSizeInBits()-1) {
19392 // Generate SUB & CMOV.
19393 SDValue Neg = DAG.getNode(X86ISD::SUB, DL, DAG.getVTList(VT, MVT::i32),
19394 DAG.getConstant(0, VT), N0.getOperand(0));
19396 SDValue Ops[] = { N0.getOperand(0), Neg,
19397 DAG.getConstant(X86::COND_GE, MVT::i8),
19398 SDValue(Neg.getNode(), 1) };
19399 return DAG.getNode(X86ISD::CMOV, DL, DAG.getVTList(VT, MVT::Glue), Ops);
19404 // PerformXorCombine - Attempts to turn XOR nodes into BLSMSK nodes
19405 static SDValue PerformXorCombine(SDNode *N, SelectionDAG &DAG,
19406 TargetLowering::DAGCombinerInfo &DCI,
19407 const X86Subtarget *Subtarget) {
19408 if (DCI.isBeforeLegalizeOps())
19411 if (Subtarget->hasCMov()) {
19412 SDValue RV = performIntegerAbsCombine(N, DAG);
19420 /// PerformLOADCombine - Do target-specific dag combines on LOAD nodes.
19421 static SDValue PerformLOADCombine(SDNode *N, SelectionDAG &DAG,
19422 TargetLowering::DAGCombinerInfo &DCI,
19423 const X86Subtarget *Subtarget) {
19424 LoadSDNode *Ld = cast<LoadSDNode>(N);
19425 EVT RegVT = Ld->getValueType(0);
19426 EVT MemVT = Ld->getMemoryVT();
19428 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
19429 unsigned RegSz = RegVT.getSizeInBits();
19431 // On Sandybridge unaligned 256bit loads are inefficient.
19432 ISD::LoadExtType Ext = Ld->getExtensionType();
19433 unsigned Alignment = Ld->getAlignment();
19434 bool IsAligned = Alignment == 0 || Alignment >= MemVT.getSizeInBits()/8;
19435 if (RegVT.is256BitVector() && !Subtarget->hasInt256() &&
19436 !DCI.isBeforeLegalizeOps() && !IsAligned && Ext == ISD::NON_EXTLOAD) {
19437 unsigned NumElems = RegVT.getVectorNumElements();
19441 SDValue Ptr = Ld->getBasePtr();
19442 SDValue Increment = DAG.getConstant(16, TLI.getPointerTy());
19444 EVT HalfVT = EVT::getVectorVT(*DAG.getContext(), MemVT.getScalarType(),
19446 SDValue Load1 = DAG.getLoad(HalfVT, dl, Ld->getChain(), Ptr,
19447 Ld->getPointerInfo(), Ld->isVolatile(),
19448 Ld->isNonTemporal(), Ld->isInvariant(),
19450 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
19451 SDValue Load2 = DAG.getLoad(HalfVT, dl, Ld->getChain(), Ptr,
19452 Ld->getPointerInfo(), Ld->isVolatile(),
19453 Ld->isNonTemporal(), Ld->isInvariant(),
19454 std::min(16U, Alignment));
19455 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
19457 Load2.getValue(1));
19459 SDValue NewVec = DAG.getUNDEF(RegVT);
19460 NewVec = Insert128BitVector(NewVec, Load1, 0, DAG, dl);
19461 NewVec = Insert128BitVector(NewVec, Load2, NumElems/2, DAG, dl);
19462 return DCI.CombineTo(N, NewVec, TF, true);
19465 // If this is a vector EXT Load then attempt to optimize it using a
19466 // shuffle. If SSSE3 is not available we may emit an illegal shuffle but the
19467 // expansion is still better than scalar code.
19468 // We generate X86ISD::VSEXT for SEXTLOADs if it's available, otherwise we'll
19469 // emit a shuffle and a arithmetic shift.
19470 // TODO: It is possible to support ZExt by zeroing the undef values
19471 // during the shuffle phase or after the shuffle.
19472 if (RegVT.isVector() && RegVT.isInteger() && Subtarget->hasSSE2() &&
19473 (Ext == ISD::EXTLOAD || Ext == ISD::SEXTLOAD)) {
19474 assert(MemVT != RegVT && "Cannot extend to the same type");
19475 assert(MemVT.isVector() && "Must load a vector from memory");
19477 unsigned NumElems = RegVT.getVectorNumElements();
19478 unsigned MemSz = MemVT.getSizeInBits();
19479 assert(RegSz > MemSz && "Register size must be greater than the mem size");
19481 if (Ext == ISD::SEXTLOAD && RegSz == 256 && !Subtarget->hasInt256())
19484 // All sizes must be a power of two.
19485 if (!isPowerOf2_32(RegSz * MemSz * NumElems))
19488 // Attempt to load the original value using scalar loads.
19489 // Find the largest scalar type that divides the total loaded size.
19490 MVT SclrLoadTy = MVT::i8;
19491 for (unsigned tp = MVT::FIRST_INTEGER_VALUETYPE;
19492 tp < MVT::LAST_INTEGER_VALUETYPE; ++tp) {
19493 MVT Tp = (MVT::SimpleValueType)tp;
19494 if (TLI.isTypeLegal(Tp) && ((MemSz % Tp.getSizeInBits()) == 0)) {
19499 // On 32bit systems, we can't save 64bit integers. Try bitcasting to F64.
19500 if (TLI.isTypeLegal(MVT::f64) && SclrLoadTy.getSizeInBits() < 64 &&
19502 SclrLoadTy = MVT::f64;
19504 // Calculate the number of scalar loads that we need to perform
19505 // in order to load our vector from memory.
19506 unsigned NumLoads = MemSz / SclrLoadTy.getSizeInBits();
19507 if (Ext == ISD::SEXTLOAD && NumLoads > 1)
19510 unsigned loadRegZize = RegSz;
19511 if (Ext == ISD::SEXTLOAD && RegSz == 256)
19514 // Represent our vector as a sequence of elements which are the
19515 // largest scalar that we can load.
19516 EVT LoadUnitVecVT = EVT::getVectorVT(*DAG.getContext(), SclrLoadTy,
19517 loadRegZize/SclrLoadTy.getSizeInBits());
19519 // Represent the data using the same element type that is stored in
19520 // memory. In practice, we ''widen'' MemVT.
19522 EVT::getVectorVT(*DAG.getContext(), MemVT.getScalarType(),
19523 loadRegZize/MemVT.getScalarType().getSizeInBits());
19525 assert(WideVecVT.getSizeInBits() == LoadUnitVecVT.getSizeInBits() &&
19526 "Invalid vector type");
19528 // We can't shuffle using an illegal type.
19529 if (!TLI.isTypeLegal(WideVecVT))
19532 SmallVector<SDValue, 8> Chains;
19533 SDValue Ptr = Ld->getBasePtr();
19534 SDValue Increment = DAG.getConstant(SclrLoadTy.getSizeInBits()/8,
19535 TLI.getPointerTy());
19536 SDValue Res = DAG.getUNDEF(LoadUnitVecVT);
19538 for (unsigned i = 0; i < NumLoads; ++i) {
19539 // Perform a single load.
19540 SDValue ScalarLoad = DAG.getLoad(SclrLoadTy, dl, Ld->getChain(),
19541 Ptr, Ld->getPointerInfo(),
19542 Ld->isVolatile(), Ld->isNonTemporal(),
19543 Ld->isInvariant(), Ld->getAlignment());
19544 Chains.push_back(ScalarLoad.getValue(1));
19545 // Create the first element type using SCALAR_TO_VECTOR in order to avoid
19546 // another round of DAGCombining.
19548 Res = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, LoadUnitVecVT, ScalarLoad);
19550 Res = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, LoadUnitVecVT, Res,
19551 ScalarLoad, DAG.getIntPtrConstant(i));
19553 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
19556 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Chains);
19558 // Bitcast the loaded value to a vector of the original element type, in
19559 // the size of the target vector type.
19560 SDValue SlicedVec = DAG.getNode(ISD::BITCAST, dl, WideVecVT, Res);
19561 unsigned SizeRatio = RegSz/MemSz;
19563 if (Ext == ISD::SEXTLOAD) {
19564 // If we have SSE4.1 we can directly emit a VSEXT node.
19565 if (Subtarget->hasSSE41()) {
19566 SDValue Sext = DAG.getNode(X86ISD::VSEXT, dl, RegVT, SlicedVec);
19567 return DCI.CombineTo(N, Sext, TF, true);
19570 // Otherwise we'll shuffle the small elements in the high bits of the
19571 // larger type and perform an arithmetic shift. If the shift is not legal
19572 // it's better to scalarize.
19573 if (!TLI.isOperationLegalOrCustom(ISD::SRA, RegVT))
19576 // Redistribute the loaded elements into the different locations.
19577 SmallVector<int, 8> ShuffleVec(NumElems * SizeRatio, -1);
19578 for (unsigned i = 0; i != NumElems; ++i)
19579 ShuffleVec[i*SizeRatio + SizeRatio-1] = i;
19581 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, SlicedVec,
19582 DAG.getUNDEF(WideVecVT),
19585 Shuff = DAG.getNode(ISD::BITCAST, dl, RegVT, Shuff);
19587 // Build the arithmetic shift.
19588 unsigned Amt = RegVT.getVectorElementType().getSizeInBits() -
19589 MemVT.getVectorElementType().getSizeInBits();
19590 Shuff = DAG.getNode(ISD::SRA, dl, RegVT, Shuff,
19591 DAG.getConstant(Amt, RegVT));
19593 return DCI.CombineTo(N, Shuff, TF, true);
19596 // Redistribute the loaded elements into the different locations.
19597 SmallVector<int, 8> ShuffleVec(NumElems * SizeRatio, -1);
19598 for (unsigned i = 0; i != NumElems; ++i)
19599 ShuffleVec[i*SizeRatio] = i;
19601 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, SlicedVec,
19602 DAG.getUNDEF(WideVecVT),
19605 // Bitcast to the requested type.
19606 Shuff = DAG.getNode(ISD::BITCAST, dl, RegVT, Shuff);
19607 // Replace the original load with the new sequence
19608 // and return the new chain.
19609 return DCI.CombineTo(N, Shuff, TF, true);
19615 /// PerformSTORECombine - Do target-specific dag combines on STORE nodes.
19616 static SDValue PerformSTORECombine(SDNode *N, SelectionDAG &DAG,
19617 const X86Subtarget *Subtarget) {
19618 StoreSDNode *St = cast<StoreSDNode>(N);
19619 EVT VT = St->getValue().getValueType();
19620 EVT StVT = St->getMemoryVT();
19622 SDValue StoredVal = St->getOperand(1);
19623 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
19625 // If we are saving a concatenation of two XMM registers, perform two stores.
19626 // On Sandy Bridge, 256-bit memory operations are executed by two
19627 // 128-bit ports. However, on Haswell it is better to issue a single 256-bit
19628 // memory operation.
19629 unsigned Alignment = St->getAlignment();
19630 bool IsAligned = Alignment == 0 || Alignment >= VT.getSizeInBits()/8;
19631 if (VT.is256BitVector() && !Subtarget->hasInt256() &&
19632 StVT == VT && !IsAligned) {
19633 unsigned NumElems = VT.getVectorNumElements();
19637 SDValue Value0 = Extract128BitVector(StoredVal, 0, DAG, dl);
19638 SDValue Value1 = Extract128BitVector(StoredVal, NumElems/2, DAG, dl);
19640 SDValue Stride = DAG.getConstant(16, TLI.getPointerTy());
19641 SDValue Ptr0 = St->getBasePtr();
19642 SDValue Ptr1 = DAG.getNode(ISD::ADD, dl, Ptr0.getValueType(), Ptr0, Stride);
19644 SDValue Ch0 = DAG.getStore(St->getChain(), dl, Value0, Ptr0,
19645 St->getPointerInfo(), St->isVolatile(),
19646 St->isNonTemporal(), Alignment);
19647 SDValue Ch1 = DAG.getStore(St->getChain(), dl, Value1, Ptr1,
19648 St->getPointerInfo(), St->isVolatile(),
19649 St->isNonTemporal(),
19650 std::min(16U, Alignment));
19651 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Ch0, Ch1);
19654 // Optimize trunc store (of multiple scalars) to shuffle and store.
19655 // First, pack all of the elements in one place. Next, store to memory
19656 // in fewer chunks.
19657 if (St->isTruncatingStore() && VT.isVector()) {
19658 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
19659 unsigned NumElems = VT.getVectorNumElements();
19660 assert(StVT != VT && "Cannot truncate to the same type");
19661 unsigned FromSz = VT.getVectorElementType().getSizeInBits();
19662 unsigned ToSz = StVT.getVectorElementType().getSizeInBits();
19664 // From, To sizes and ElemCount must be pow of two
19665 if (!isPowerOf2_32(NumElems * FromSz * ToSz)) return SDValue();
19666 // We are going to use the original vector elt for storing.
19667 // Accumulated smaller vector elements must be a multiple of the store size.
19668 if (0 != (NumElems * FromSz) % ToSz) return SDValue();
19670 unsigned SizeRatio = FromSz / ToSz;
19672 assert(SizeRatio * NumElems * ToSz == VT.getSizeInBits());
19674 // Create a type on which we perform the shuffle
19675 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(),
19676 StVT.getScalarType(), NumElems*SizeRatio);
19678 assert(WideVecVT.getSizeInBits() == VT.getSizeInBits());
19680 SDValue WideVec = DAG.getNode(ISD::BITCAST, dl, WideVecVT, St->getValue());
19681 SmallVector<int, 8> ShuffleVec(NumElems * SizeRatio, -1);
19682 for (unsigned i = 0; i != NumElems; ++i)
19683 ShuffleVec[i] = i * SizeRatio;
19685 // Can't shuffle using an illegal type.
19686 if (!TLI.isTypeLegal(WideVecVT))
19689 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, WideVec,
19690 DAG.getUNDEF(WideVecVT),
19692 // At this point all of the data is stored at the bottom of the
19693 // register. We now need to save it to mem.
19695 // Find the largest store unit
19696 MVT StoreType = MVT::i8;
19697 for (unsigned tp = MVT::FIRST_INTEGER_VALUETYPE;
19698 tp < MVT::LAST_INTEGER_VALUETYPE; ++tp) {
19699 MVT Tp = (MVT::SimpleValueType)tp;
19700 if (TLI.isTypeLegal(Tp) && Tp.getSizeInBits() <= NumElems * ToSz)
19704 // On 32bit systems, we can't save 64bit integers. Try bitcasting to F64.
19705 if (TLI.isTypeLegal(MVT::f64) && StoreType.getSizeInBits() < 64 &&
19706 (64 <= NumElems * ToSz))
19707 StoreType = MVT::f64;
19709 // Bitcast the original vector into a vector of store-size units
19710 EVT StoreVecVT = EVT::getVectorVT(*DAG.getContext(),
19711 StoreType, VT.getSizeInBits()/StoreType.getSizeInBits());
19712 assert(StoreVecVT.getSizeInBits() == VT.getSizeInBits());
19713 SDValue ShuffWide = DAG.getNode(ISD::BITCAST, dl, StoreVecVT, Shuff);
19714 SmallVector<SDValue, 8> Chains;
19715 SDValue Increment = DAG.getConstant(StoreType.getSizeInBits()/8,
19716 TLI.getPointerTy());
19717 SDValue Ptr = St->getBasePtr();
19719 // Perform one or more big stores into memory.
19720 for (unsigned i=0, e=(ToSz*NumElems)/StoreType.getSizeInBits(); i!=e; ++i) {
19721 SDValue SubVec = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
19722 StoreType, ShuffWide,
19723 DAG.getIntPtrConstant(i));
19724 SDValue Ch = DAG.getStore(St->getChain(), dl, SubVec, Ptr,
19725 St->getPointerInfo(), St->isVolatile(),
19726 St->isNonTemporal(), St->getAlignment());
19727 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
19728 Chains.push_back(Ch);
19731 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Chains);
19734 // Turn load->store of MMX types into GPR load/stores. This avoids clobbering
19735 // the FP state in cases where an emms may be missing.
19736 // A preferable solution to the general problem is to figure out the right
19737 // places to insert EMMS. This qualifies as a quick hack.
19739 // Similarly, turn load->store of i64 into double load/stores in 32-bit mode.
19740 if (VT.getSizeInBits() != 64)
19743 const Function *F = DAG.getMachineFunction().getFunction();
19744 bool NoImplicitFloatOps = F->getAttributes().
19745 hasAttribute(AttributeSet::FunctionIndex, Attribute::NoImplicitFloat);
19746 bool F64IsLegal = !DAG.getTarget().Options.UseSoftFloat && !NoImplicitFloatOps
19747 && Subtarget->hasSSE2();
19748 if ((VT.isVector() ||
19749 (VT == MVT::i64 && F64IsLegal && !Subtarget->is64Bit())) &&
19750 isa<LoadSDNode>(St->getValue()) &&
19751 !cast<LoadSDNode>(St->getValue())->isVolatile() &&
19752 St->getChain().hasOneUse() && !St->isVolatile()) {
19753 SDNode* LdVal = St->getValue().getNode();
19754 LoadSDNode *Ld = nullptr;
19755 int TokenFactorIndex = -1;
19756 SmallVector<SDValue, 8> Ops;
19757 SDNode* ChainVal = St->getChain().getNode();
19758 // Must be a store of a load. We currently handle two cases: the load
19759 // is a direct child, and it's under an intervening TokenFactor. It is
19760 // possible to dig deeper under nested TokenFactors.
19761 if (ChainVal == LdVal)
19762 Ld = cast<LoadSDNode>(St->getChain());
19763 else if (St->getValue().hasOneUse() &&
19764 ChainVal->getOpcode() == ISD::TokenFactor) {
19765 for (unsigned i = 0, e = ChainVal->getNumOperands(); i != e; ++i) {
19766 if (ChainVal->getOperand(i).getNode() == LdVal) {
19767 TokenFactorIndex = i;
19768 Ld = cast<LoadSDNode>(St->getValue());
19770 Ops.push_back(ChainVal->getOperand(i));
19774 if (!Ld || !ISD::isNormalLoad(Ld))
19777 // If this is not the MMX case, i.e. we are just turning i64 load/store
19778 // into f64 load/store, avoid the transformation if there are multiple
19779 // uses of the loaded value.
19780 if (!VT.isVector() && !Ld->hasNUsesOfValue(1, 0))
19785 // If we are a 64-bit capable x86, lower to a single movq load/store pair.
19786 // Otherwise, if it's legal to use f64 SSE instructions, use f64 load/store
19788 if (Subtarget->is64Bit() || F64IsLegal) {
19789 EVT LdVT = Subtarget->is64Bit() ? MVT::i64 : MVT::f64;
19790 SDValue NewLd = DAG.getLoad(LdVT, LdDL, Ld->getChain(), Ld->getBasePtr(),
19791 Ld->getPointerInfo(), Ld->isVolatile(),
19792 Ld->isNonTemporal(), Ld->isInvariant(),
19793 Ld->getAlignment());
19794 SDValue NewChain = NewLd.getValue(1);
19795 if (TokenFactorIndex != -1) {
19796 Ops.push_back(NewChain);
19797 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, Ops);
19799 return DAG.getStore(NewChain, StDL, NewLd, St->getBasePtr(),
19800 St->getPointerInfo(),
19801 St->isVolatile(), St->isNonTemporal(),
19802 St->getAlignment());
19805 // Otherwise, lower to two pairs of 32-bit loads / stores.
19806 SDValue LoAddr = Ld->getBasePtr();
19807 SDValue HiAddr = DAG.getNode(ISD::ADD, LdDL, MVT::i32, LoAddr,
19808 DAG.getConstant(4, MVT::i32));
19810 SDValue LoLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), LoAddr,
19811 Ld->getPointerInfo(),
19812 Ld->isVolatile(), Ld->isNonTemporal(),
19813 Ld->isInvariant(), Ld->getAlignment());
19814 SDValue HiLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), HiAddr,
19815 Ld->getPointerInfo().getWithOffset(4),
19816 Ld->isVolatile(), Ld->isNonTemporal(),
19818 MinAlign(Ld->getAlignment(), 4));
19820 SDValue NewChain = LoLd.getValue(1);
19821 if (TokenFactorIndex != -1) {
19822 Ops.push_back(LoLd);
19823 Ops.push_back(HiLd);
19824 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, Ops);
19827 LoAddr = St->getBasePtr();
19828 HiAddr = DAG.getNode(ISD::ADD, StDL, MVT::i32, LoAddr,
19829 DAG.getConstant(4, MVT::i32));
19831 SDValue LoSt = DAG.getStore(NewChain, StDL, LoLd, LoAddr,
19832 St->getPointerInfo(),
19833 St->isVolatile(), St->isNonTemporal(),
19834 St->getAlignment());
19835 SDValue HiSt = DAG.getStore(NewChain, StDL, HiLd, HiAddr,
19836 St->getPointerInfo().getWithOffset(4),
19838 St->isNonTemporal(),
19839 MinAlign(St->getAlignment(), 4));
19840 return DAG.getNode(ISD::TokenFactor, StDL, MVT::Other, LoSt, HiSt);
19845 /// isHorizontalBinOp - Return 'true' if this vector operation is "horizontal"
19846 /// and return the operands for the horizontal operation in LHS and RHS. A
19847 /// horizontal operation performs the binary operation on successive elements
19848 /// of its first operand, then on successive elements of its second operand,
19849 /// returning the resulting values in a vector. For example, if
19850 /// A = < float a0, float a1, float a2, float a3 >
19852 /// B = < float b0, float b1, float b2, float b3 >
19853 /// then the result of doing a horizontal operation on A and B is
19854 /// A horizontal-op B = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >.
19855 /// In short, LHS and RHS are inspected to see if LHS op RHS is of the form
19856 /// A horizontal-op B, for some already available A and B, and if so then LHS is
19857 /// set to A, RHS to B, and the routine returns 'true'.
19858 /// Note that the binary operation should have the property that if one of the
19859 /// operands is UNDEF then the result is UNDEF.
19860 static bool isHorizontalBinOp(SDValue &LHS, SDValue &RHS, bool IsCommutative) {
19861 // Look for the following pattern: if
19862 // A = < float a0, float a1, float a2, float a3 >
19863 // B = < float b0, float b1, float b2, float b3 >
19865 // LHS = VECTOR_SHUFFLE A, B, <0, 2, 4, 6>
19866 // RHS = VECTOR_SHUFFLE A, B, <1, 3, 5, 7>
19867 // then LHS op RHS = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >
19868 // which is A horizontal-op B.
19870 // At least one of the operands should be a vector shuffle.
19871 if (LHS.getOpcode() != ISD::VECTOR_SHUFFLE &&
19872 RHS.getOpcode() != ISD::VECTOR_SHUFFLE)
19875 MVT VT = LHS.getSimpleValueType();
19877 assert((VT.is128BitVector() || VT.is256BitVector()) &&
19878 "Unsupported vector type for horizontal add/sub");
19880 // Handle 128 and 256-bit vector lengths. AVX defines horizontal add/sub to
19881 // operate independently on 128-bit lanes.
19882 unsigned NumElts = VT.getVectorNumElements();
19883 unsigned NumLanes = VT.getSizeInBits()/128;
19884 unsigned NumLaneElts = NumElts / NumLanes;
19885 assert((NumLaneElts % 2 == 0) &&
19886 "Vector type should have an even number of elements in each lane");
19887 unsigned HalfLaneElts = NumLaneElts/2;
19889 // View LHS in the form
19890 // LHS = VECTOR_SHUFFLE A, B, LMask
19891 // If LHS is not a shuffle then pretend it is the shuffle
19892 // LHS = VECTOR_SHUFFLE LHS, undef, <0, 1, ..., N-1>
19893 // NOTE: in what follows a default initialized SDValue represents an UNDEF of
19896 SmallVector<int, 16> LMask(NumElts);
19897 if (LHS.getOpcode() == ISD::VECTOR_SHUFFLE) {
19898 if (LHS.getOperand(0).getOpcode() != ISD::UNDEF)
19899 A = LHS.getOperand(0);
19900 if (LHS.getOperand(1).getOpcode() != ISD::UNDEF)
19901 B = LHS.getOperand(1);
19902 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(LHS.getNode())->getMask();
19903 std::copy(Mask.begin(), Mask.end(), LMask.begin());
19905 if (LHS.getOpcode() != ISD::UNDEF)
19907 for (unsigned i = 0; i != NumElts; ++i)
19911 // Likewise, view RHS in the form
19912 // RHS = VECTOR_SHUFFLE C, D, RMask
19914 SmallVector<int, 16> RMask(NumElts);
19915 if (RHS.getOpcode() == ISD::VECTOR_SHUFFLE) {
19916 if (RHS.getOperand(0).getOpcode() != ISD::UNDEF)
19917 C = RHS.getOperand(0);
19918 if (RHS.getOperand(1).getOpcode() != ISD::UNDEF)
19919 D = RHS.getOperand(1);
19920 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(RHS.getNode())->getMask();
19921 std::copy(Mask.begin(), Mask.end(), RMask.begin());
19923 if (RHS.getOpcode() != ISD::UNDEF)
19925 for (unsigned i = 0; i != NumElts; ++i)
19929 // Check that the shuffles are both shuffling the same vectors.
19930 if (!(A == C && B == D) && !(A == D && B == C))
19933 // If everything is UNDEF then bail out: it would be better to fold to UNDEF.
19934 if (!A.getNode() && !B.getNode())
19937 // If A and B occur in reverse order in RHS, then "swap" them (which means
19938 // rewriting the mask).
19940 CommuteVectorShuffleMask(RMask, NumElts);
19942 // At this point LHS and RHS are equivalent to
19943 // LHS = VECTOR_SHUFFLE A, B, LMask
19944 // RHS = VECTOR_SHUFFLE A, B, RMask
19945 // Check that the masks correspond to performing a horizontal operation.
19946 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
19947 for (unsigned i = 0; i != NumLaneElts; ++i) {
19948 int LIdx = LMask[i+l], RIdx = RMask[i+l];
19950 // Ignore any UNDEF components.
19951 if (LIdx < 0 || RIdx < 0 ||
19952 (!A.getNode() && (LIdx < (int)NumElts || RIdx < (int)NumElts)) ||
19953 (!B.getNode() && (LIdx >= (int)NumElts || RIdx >= (int)NumElts)))
19956 // Check that successive elements are being operated on. If not, this is
19957 // not a horizontal operation.
19958 unsigned Src = (i/HalfLaneElts); // each lane is split between srcs
19959 int Index = 2*(i%HalfLaneElts) + NumElts*Src + l;
19960 if (!(LIdx == Index && RIdx == Index + 1) &&
19961 !(IsCommutative && LIdx == Index + 1 && RIdx == Index))
19966 LHS = A.getNode() ? A : B; // If A is 'UNDEF', use B for it.
19967 RHS = B.getNode() ? B : A; // If B is 'UNDEF', use A for it.
19971 /// PerformFADDCombine - Do target-specific dag combines on floating point adds.
19972 static SDValue PerformFADDCombine(SDNode *N, SelectionDAG &DAG,
19973 const X86Subtarget *Subtarget) {
19974 EVT VT = N->getValueType(0);
19975 SDValue LHS = N->getOperand(0);
19976 SDValue RHS = N->getOperand(1);
19978 // Try to synthesize horizontal adds from adds of shuffles.
19979 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
19980 (Subtarget->hasFp256() && (VT == MVT::v8f32 || VT == MVT::v4f64))) &&
19981 isHorizontalBinOp(LHS, RHS, true))
19982 return DAG.getNode(X86ISD::FHADD, SDLoc(N), VT, LHS, RHS);
19986 /// PerformFSUBCombine - Do target-specific dag combines on floating point subs.
19987 static SDValue PerformFSUBCombine(SDNode *N, SelectionDAG &DAG,
19988 const X86Subtarget *Subtarget) {
19989 EVT VT = N->getValueType(0);
19990 SDValue LHS = N->getOperand(0);
19991 SDValue RHS = N->getOperand(1);
19993 // Try to synthesize horizontal subs from subs of shuffles.
19994 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
19995 (Subtarget->hasFp256() && (VT == MVT::v8f32 || VT == MVT::v4f64))) &&
19996 isHorizontalBinOp(LHS, RHS, false))
19997 return DAG.getNode(X86ISD::FHSUB, SDLoc(N), VT, LHS, RHS);
20001 /// PerformFORCombine - Do target-specific dag combines on X86ISD::FOR and
20002 /// X86ISD::FXOR nodes.
20003 static SDValue PerformFORCombine(SDNode *N, SelectionDAG &DAG) {
20004 assert(N->getOpcode() == X86ISD::FOR || N->getOpcode() == X86ISD::FXOR);
20005 // F[X]OR(0.0, x) -> x
20006 // F[X]OR(x, 0.0) -> x
20007 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
20008 if (C->getValueAPF().isPosZero())
20009 return N->getOperand(1);
20010 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
20011 if (C->getValueAPF().isPosZero())
20012 return N->getOperand(0);
20016 /// PerformFMinFMaxCombine - Do target-specific dag combines on X86ISD::FMIN and
20017 /// X86ISD::FMAX nodes.
20018 static SDValue PerformFMinFMaxCombine(SDNode *N, SelectionDAG &DAG) {
20019 assert(N->getOpcode() == X86ISD::FMIN || N->getOpcode() == X86ISD::FMAX);
20021 // Only perform optimizations if UnsafeMath is used.
20022 if (!DAG.getTarget().Options.UnsafeFPMath)
20025 // If we run in unsafe-math mode, then convert the FMAX and FMIN nodes
20026 // into FMINC and FMAXC, which are Commutative operations.
20027 unsigned NewOp = 0;
20028 switch (N->getOpcode()) {
20029 default: llvm_unreachable("unknown opcode");
20030 case X86ISD::FMIN: NewOp = X86ISD::FMINC; break;
20031 case X86ISD::FMAX: NewOp = X86ISD::FMAXC; break;
20034 return DAG.getNode(NewOp, SDLoc(N), N->getValueType(0),
20035 N->getOperand(0), N->getOperand(1));
20038 /// PerformFANDCombine - Do target-specific dag combines on X86ISD::FAND nodes.
20039 static SDValue PerformFANDCombine(SDNode *N, SelectionDAG &DAG) {
20040 // FAND(0.0, x) -> 0.0
20041 // FAND(x, 0.0) -> 0.0
20042 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
20043 if (C->getValueAPF().isPosZero())
20044 return N->getOperand(0);
20045 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
20046 if (C->getValueAPF().isPosZero())
20047 return N->getOperand(1);
20051 /// PerformFANDNCombine - Do target-specific dag combines on X86ISD::FANDN nodes
20052 static SDValue PerformFANDNCombine(SDNode *N, SelectionDAG &DAG) {
20053 // FANDN(x, 0.0) -> 0.0
20054 // FANDN(0.0, x) -> x
20055 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
20056 if (C->getValueAPF().isPosZero())
20057 return N->getOperand(1);
20058 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
20059 if (C->getValueAPF().isPosZero())
20060 return N->getOperand(1);
20064 static SDValue PerformBTCombine(SDNode *N,
20066 TargetLowering::DAGCombinerInfo &DCI) {
20067 // BT ignores high bits in the bit index operand.
20068 SDValue Op1 = N->getOperand(1);
20069 if (Op1.hasOneUse()) {
20070 unsigned BitWidth = Op1.getValueSizeInBits();
20071 APInt DemandedMask = APInt::getLowBitsSet(BitWidth, Log2_32(BitWidth));
20072 APInt KnownZero, KnownOne;
20073 TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(),
20074 !DCI.isBeforeLegalizeOps());
20075 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
20076 if (TLO.ShrinkDemandedConstant(Op1, DemandedMask) ||
20077 TLI.SimplifyDemandedBits(Op1, DemandedMask, KnownZero, KnownOne, TLO))
20078 DCI.CommitTargetLoweringOpt(TLO);
20083 static SDValue PerformVZEXT_MOVLCombine(SDNode *N, SelectionDAG &DAG) {
20084 SDValue Op = N->getOperand(0);
20085 if (Op.getOpcode() == ISD::BITCAST)
20086 Op = Op.getOperand(0);
20087 EVT VT = N->getValueType(0), OpVT = Op.getValueType();
20088 if (Op.getOpcode() == X86ISD::VZEXT_LOAD &&
20089 VT.getVectorElementType().getSizeInBits() ==
20090 OpVT.getVectorElementType().getSizeInBits()) {
20091 return DAG.getNode(ISD::BITCAST, SDLoc(N), VT, Op);
20096 static SDValue PerformSIGN_EXTEND_INREGCombine(SDNode *N, SelectionDAG &DAG,
20097 const X86Subtarget *Subtarget) {
20098 EVT VT = N->getValueType(0);
20099 if (!VT.isVector())
20102 SDValue N0 = N->getOperand(0);
20103 SDValue N1 = N->getOperand(1);
20104 EVT ExtraVT = cast<VTSDNode>(N1)->getVT();
20107 // The SIGN_EXTEND_INREG to v4i64 is expensive operation on the
20108 // both SSE and AVX2 since there is no sign-extended shift right
20109 // operation on a vector with 64-bit elements.
20110 //(sext_in_reg (v4i64 anyext (v4i32 x )), ExtraVT) ->
20111 // (v4i64 sext (v4i32 sext_in_reg (v4i32 x , ExtraVT)))
20112 if (VT == MVT::v4i64 && (N0.getOpcode() == ISD::ANY_EXTEND ||
20113 N0.getOpcode() == ISD::SIGN_EXTEND)) {
20114 SDValue N00 = N0.getOperand(0);
20116 // EXTLOAD has a better solution on AVX2,
20117 // it may be replaced with X86ISD::VSEXT node.
20118 if (N00.getOpcode() == ISD::LOAD && Subtarget->hasInt256())
20119 if (!ISD::isNormalLoad(N00.getNode()))
20122 if (N00.getValueType() == MVT::v4i32 && ExtraVT.getSizeInBits() < 128) {
20123 SDValue Tmp = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, MVT::v4i32,
20125 return DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v4i64, Tmp);
20131 static SDValue PerformSExtCombine(SDNode *N, SelectionDAG &DAG,
20132 TargetLowering::DAGCombinerInfo &DCI,
20133 const X86Subtarget *Subtarget) {
20134 if (!DCI.isBeforeLegalizeOps())
20137 if (!Subtarget->hasFp256())
20140 EVT VT = N->getValueType(0);
20141 if (VT.isVector() && VT.getSizeInBits() == 256) {
20142 SDValue R = WidenMaskArithmetic(N, DAG, DCI, Subtarget);
20150 static SDValue PerformFMACombine(SDNode *N, SelectionDAG &DAG,
20151 const X86Subtarget* Subtarget) {
20153 EVT VT = N->getValueType(0);
20155 // Let legalize expand this if it isn't a legal type yet.
20156 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
20159 EVT ScalarVT = VT.getScalarType();
20160 if ((ScalarVT != MVT::f32 && ScalarVT != MVT::f64) ||
20161 (!Subtarget->hasFMA() && !Subtarget->hasFMA4()))
20164 SDValue A = N->getOperand(0);
20165 SDValue B = N->getOperand(1);
20166 SDValue C = N->getOperand(2);
20168 bool NegA = (A.getOpcode() == ISD::FNEG);
20169 bool NegB = (B.getOpcode() == ISD::FNEG);
20170 bool NegC = (C.getOpcode() == ISD::FNEG);
20172 // Negative multiplication when NegA xor NegB
20173 bool NegMul = (NegA != NegB);
20175 A = A.getOperand(0);
20177 B = B.getOperand(0);
20179 C = C.getOperand(0);
20183 Opcode = (!NegC) ? X86ISD::FMADD : X86ISD::FMSUB;
20185 Opcode = (!NegC) ? X86ISD::FNMADD : X86ISD::FNMSUB;
20187 return DAG.getNode(Opcode, dl, VT, A, B, C);
20190 static SDValue PerformZExtCombine(SDNode *N, SelectionDAG &DAG,
20191 TargetLowering::DAGCombinerInfo &DCI,
20192 const X86Subtarget *Subtarget) {
20193 // (i32 zext (and (i8 x86isd::setcc_carry), 1)) ->
20194 // (and (i32 x86isd::setcc_carry), 1)
20195 // This eliminates the zext. This transformation is necessary because
20196 // ISD::SETCC is always legalized to i8.
20198 SDValue N0 = N->getOperand(0);
20199 EVT VT = N->getValueType(0);
20201 if (N0.getOpcode() == ISD::AND &&
20203 N0.getOperand(0).hasOneUse()) {
20204 SDValue N00 = N0.getOperand(0);
20205 if (N00.getOpcode() == X86ISD::SETCC_CARRY) {
20206 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
20207 if (!C || C->getZExtValue() != 1)
20209 return DAG.getNode(ISD::AND, dl, VT,
20210 DAG.getNode(X86ISD::SETCC_CARRY, dl, VT,
20211 N00.getOperand(0), N00.getOperand(1)),
20212 DAG.getConstant(1, VT));
20216 if (N0.getOpcode() == ISD::TRUNCATE &&
20218 N0.getOperand(0).hasOneUse()) {
20219 SDValue N00 = N0.getOperand(0);
20220 if (N00.getOpcode() == X86ISD::SETCC_CARRY) {
20221 return DAG.getNode(ISD::AND, dl, VT,
20222 DAG.getNode(X86ISD::SETCC_CARRY, dl, VT,
20223 N00.getOperand(0), N00.getOperand(1)),
20224 DAG.getConstant(1, VT));
20227 if (VT.is256BitVector()) {
20228 SDValue R = WidenMaskArithmetic(N, DAG, DCI, Subtarget);
20236 // Optimize x == -y --> x+y == 0
20237 // x != -y --> x+y != 0
20238 static SDValue PerformISDSETCCCombine(SDNode *N, SelectionDAG &DAG,
20239 const X86Subtarget* Subtarget) {
20240 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(2))->get();
20241 SDValue LHS = N->getOperand(0);
20242 SDValue RHS = N->getOperand(1);
20243 EVT VT = N->getValueType(0);
20246 if ((CC == ISD::SETNE || CC == ISD::SETEQ) && LHS.getOpcode() == ISD::SUB)
20247 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(LHS.getOperand(0)))
20248 if (C->getAPIntValue() == 0 && LHS.hasOneUse()) {
20249 SDValue addV = DAG.getNode(ISD::ADD, SDLoc(N),
20250 LHS.getValueType(), RHS, LHS.getOperand(1));
20251 return DAG.getSetCC(SDLoc(N), N->getValueType(0),
20252 addV, DAG.getConstant(0, addV.getValueType()), CC);
20254 if ((CC == ISD::SETNE || CC == ISD::SETEQ) && RHS.getOpcode() == ISD::SUB)
20255 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS.getOperand(0)))
20256 if (C->getAPIntValue() == 0 && RHS.hasOneUse()) {
20257 SDValue addV = DAG.getNode(ISD::ADD, SDLoc(N),
20258 RHS.getValueType(), LHS, RHS.getOperand(1));
20259 return DAG.getSetCC(SDLoc(N), N->getValueType(0),
20260 addV, DAG.getConstant(0, addV.getValueType()), CC);
20263 if (VT.getScalarType() == MVT::i1) {
20264 bool IsSEXT0 = (LHS.getOpcode() == ISD::SIGN_EXTEND) &&
20265 (LHS.getOperand(0).getValueType().getScalarType() == MVT::i1);
20266 bool IsVZero0 = ISD::isBuildVectorAllZeros(LHS.getNode());
20267 if (!IsSEXT0 && !IsVZero0)
20269 bool IsSEXT1 = (RHS.getOpcode() == ISD::SIGN_EXTEND) &&
20270 (RHS.getOperand(0).getValueType().getScalarType() == MVT::i1);
20271 bool IsVZero1 = ISD::isBuildVectorAllZeros(RHS.getNode());
20273 if (!IsSEXT1 && !IsVZero1)
20276 if (IsSEXT0 && IsVZero1) {
20277 assert(VT == LHS.getOperand(0).getValueType() && "Uexpected operand type");
20278 if (CC == ISD::SETEQ)
20279 return DAG.getNOT(DL, LHS.getOperand(0), VT);
20280 return LHS.getOperand(0);
20282 if (IsSEXT1 && IsVZero0) {
20283 assert(VT == RHS.getOperand(0).getValueType() && "Uexpected operand type");
20284 if (CC == ISD::SETEQ)
20285 return DAG.getNOT(DL, RHS.getOperand(0), VT);
20286 return RHS.getOperand(0);
20293 static SDValue PerformINSERTPSCombine(SDNode *N, SelectionDAG &DAG,
20294 const X86Subtarget *Subtarget) {
20296 MVT VT = N->getOperand(1)->getSimpleValueType(0);
20297 assert((VT == MVT::v4f32 || VT == MVT::v4i32) &&
20298 "X86insertps is only defined for v4x32");
20300 SDValue Ld = N->getOperand(1);
20301 if (MayFoldLoad(Ld)) {
20302 // Extract the countS bits from the immediate so we can get the proper
20303 // address when narrowing the vector load to a specific element.
20304 // When the second source op is a memory address, interps doesn't use
20305 // countS and just gets an f32 from that address.
20306 unsigned DestIndex =
20307 cast<ConstantSDNode>(N->getOperand(2))->getZExtValue() >> 6;
20308 Ld = NarrowVectorLoadToElement(cast<LoadSDNode>(Ld), DestIndex, DAG);
20312 // Create this as a scalar to vector to match the instruction pattern.
20313 SDValue LoadScalarToVector = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Ld);
20314 // countS bits are ignored when loading from memory on insertps, which
20315 // means we don't need to explicitly set them to 0.
20316 return DAG.getNode(X86ISD::INSERTPS, dl, VT, N->getOperand(0),
20317 LoadScalarToVector, N->getOperand(2));
20320 // Helper function of PerformSETCCCombine. It is to materialize "setb reg"
20321 // as "sbb reg,reg", since it can be extended without zext and produces
20322 // an all-ones bit which is more useful than 0/1 in some cases.
20323 static SDValue MaterializeSETB(SDLoc DL, SDValue EFLAGS, SelectionDAG &DAG,
20326 return DAG.getNode(ISD::AND, DL, VT,
20327 DAG.getNode(X86ISD::SETCC_CARRY, DL, MVT::i8,
20328 DAG.getConstant(X86::COND_B, MVT::i8), EFLAGS),
20329 DAG.getConstant(1, VT));
20330 assert (VT == MVT::i1 && "Unexpected type for SECCC node");
20331 return DAG.getNode(ISD::TRUNCATE, DL, MVT::i1,
20332 DAG.getNode(X86ISD::SETCC_CARRY, DL, MVT::i8,
20333 DAG.getConstant(X86::COND_B, MVT::i8), EFLAGS));
20336 // Optimize RES = X86ISD::SETCC CONDCODE, EFLAG_INPUT
20337 static SDValue PerformSETCCCombine(SDNode *N, SelectionDAG &DAG,
20338 TargetLowering::DAGCombinerInfo &DCI,
20339 const X86Subtarget *Subtarget) {
20341 X86::CondCode CC = X86::CondCode(N->getConstantOperandVal(0));
20342 SDValue EFLAGS = N->getOperand(1);
20344 if (CC == X86::COND_A) {
20345 // Try to convert COND_A into COND_B in an attempt to facilitate
20346 // materializing "setb reg".
20348 // Do not flip "e > c", where "c" is a constant, because Cmp instruction
20349 // cannot take an immediate as its first operand.
20351 if (EFLAGS.getOpcode() == X86ISD::SUB && EFLAGS.hasOneUse() &&
20352 EFLAGS.getValueType().isInteger() &&
20353 !isa<ConstantSDNode>(EFLAGS.getOperand(1))) {
20354 SDValue NewSub = DAG.getNode(X86ISD::SUB, SDLoc(EFLAGS),
20355 EFLAGS.getNode()->getVTList(),
20356 EFLAGS.getOperand(1), EFLAGS.getOperand(0));
20357 SDValue NewEFLAGS = SDValue(NewSub.getNode(), EFLAGS.getResNo());
20358 return MaterializeSETB(DL, NewEFLAGS, DAG, N->getSimpleValueType(0));
20362 // Materialize "setb reg" as "sbb reg,reg", since it can be extended without
20363 // a zext and produces an all-ones bit which is more useful than 0/1 in some
20365 if (CC == X86::COND_B)
20366 return MaterializeSETB(DL, EFLAGS, DAG, N->getSimpleValueType(0));
20370 Flags = checkBoolTestSetCCCombine(EFLAGS, CC);
20371 if (Flags.getNode()) {
20372 SDValue Cond = DAG.getConstant(CC, MVT::i8);
20373 return DAG.getNode(X86ISD::SETCC, DL, N->getVTList(), Cond, Flags);
20379 // Optimize branch condition evaluation.
20381 static SDValue PerformBrCondCombine(SDNode *N, SelectionDAG &DAG,
20382 TargetLowering::DAGCombinerInfo &DCI,
20383 const X86Subtarget *Subtarget) {
20385 SDValue Chain = N->getOperand(0);
20386 SDValue Dest = N->getOperand(1);
20387 SDValue EFLAGS = N->getOperand(3);
20388 X86::CondCode CC = X86::CondCode(N->getConstantOperandVal(2));
20392 Flags = checkBoolTestSetCCCombine(EFLAGS, CC);
20393 if (Flags.getNode()) {
20394 SDValue Cond = DAG.getConstant(CC, MVT::i8);
20395 return DAG.getNode(X86ISD::BRCOND, DL, N->getVTList(), Chain, Dest, Cond,
20402 static SDValue PerformSINT_TO_FPCombine(SDNode *N, SelectionDAG &DAG,
20403 const X86TargetLowering *XTLI) {
20404 SDValue Op0 = N->getOperand(0);
20405 EVT InVT = Op0->getValueType(0);
20407 // SINT_TO_FP(v4i8) -> SINT_TO_FP(SEXT(v4i8 to v4i32))
20408 if (InVT == MVT::v8i8 || InVT == MVT::v4i8) {
20410 MVT DstVT = InVT == MVT::v4i8 ? MVT::v4i32 : MVT::v8i32;
20411 SDValue P = DAG.getNode(ISD::SIGN_EXTEND, dl, DstVT, Op0);
20412 return DAG.getNode(ISD::SINT_TO_FP, dl, N->getValueType(0), P);
20415 // Transform (SINT_TO_FP (i64 ...)) into an x87 operation if we have
20416 // a 32-bit target where SSE doesn't support i64->FP operations.
20417 if (Op0.getOpcode() == ISD::LOAD) {
20418 LoadSDNode *Ld = cast<LoadSDNode>(Op0.getNode());
20419 EVT VT = Ld->getValueType(0);
20420 if (!Ld->isVolatile() && !N->getValueType(0).isVector() &&
20421 ISD::isNON_EXTLoad(Op0.getNode()) && Op0.hasOneUse() &&
20422 !XTLI->getSubtarget()->is64Bit() &&
20424 SDValue FILDChain = XTLI->BuildFILD(SDValue(N, 0), Ld->getValueType(0),
20425 Ld->getChain(), Op0, DAG);
20426 DAG.ReplaceAllUsesOfValueWith(Op0.getValue(1), FILDChain.getValue(1));
20433 // Optimize RES, EFLAGS = X86ISD::ADC LHS, RHS, EFLAGS
20434 static SDValue PerformADCCombine(SDNode *N, SelectionDAG &DAG,
20435 X86TargetLowering::DAGCombinerInfo &DCI) {
20436 // If the LHS and RHS of the ADC node are zero, then it can't overflow and
20437 // the result is either zero or one (depending on the input carry bit).
20438 // Strength reduce this down to a "set on carry" aka SETCC_CARRY&1.
20439 if (X86::isZeroNode(N->getOperand(0)) &&
20440 X86::isZeroNode(N->getOperand(1)) &&
20441 // We don't have a good way to replace an EFLAGS use, so only do this when
20443 SDValue(N, 1).use_empty()) {
20445 EVT VT = N->getValueType(0);
20446 SDValue CarryOut = DAG.getConstant(0, N->getValueType(1));
20447 SDValue Res1 = DAG.getNode(ISD::AND, DL, VT,
20448 DAG.getNode(X86ISD::SETCC_CARRY, DL, VT,
20449 DAG.getConstant(X86::COND_B,MVT::i8),
20451 DAG.getConstant(1, VT));
20452 return DCI.CombineTo(N, Res1, CarryOut);
20458 // fold (add Y, (sete X, 0)) -> adc 0, Y
20459 // (add Y, (setne X, 0)) -> sbb -1, Y
20460 // (sub (sete X, 0), Y) -> sbb 0, Y
20461 // (sub (setne X, 0), Y) -> adc -1, Y
20462 static SDValue OptimizeConditionalInDecrement(SDNode *N, SelectionDAG &DAG) {
20465 // Look through ZExts.
20466 SDValue Ext = N->getOperand(N->getOpcode() == ISD::SUB ? 1 : 0);
20467 if (Ext.getOpcode() != ISD::ZERO_EXTEND || !Ext.hasOneUse())
20470 SDValue SetCC = Ext.getOperand(0);
20471 if (SetCC.getOpcode() != X86ISD::SETCC || !SetCC.hasOneUse())
20474 X86::CondCode CC = (X86::CondCode)SetCC.getConstantOperandVal(0);
20475 if (CC != X86::COND_E && CC != X86::COND_NE)
20478 SDValue Cmp = SetCC.getOperand(1);
20479 if (Cmp.getOpcode() != X86ISD::CMP || !Cmp.hasOneUse() ||
20480 !X86::isZeroNode(Cmp.getOperand(1)) ||
20481 !Cmp.getOperand(0).getValueType().isInteger())
20484 SDValue CmpOp0 = Cmp.getOperand(0);
20485 SDValue NewCmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32, CmpOp0,
20486 DAG.getConstant(1, CmpOp0.getValueType()));
20488 SDValue OtherVal = N->getOperand(N->getOpcode() == ISD::SUB ? 0 : 1);
20489 if (CC == X86::COND_NE)
20490 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::ADC : X86ISD::SBB,
20491 DL, OtherVal.getValueType(), OtherVal,
20492 DAG.getConstant(-1ULL, OtherVal.getValueType()), NewCmp);
20493 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::SBB : X86ISD::ADC,
20494 DL, OtherVal.getValueType(), OtherVal,
20495 DAG.getConstant(0, OtherVal.getValueType()), NewCmp);
20498 /// PerformADDCombine - Do target-specific dag combines on integer adds.
20499 static SDValue PerformAddCombine(SDNode *N, SelectionDAG &DAG,
20500 const X86Subtarget *Subtarget) {
20501 EVT VT = N->getValueType(0);
20502 SDValue Op0 = N->getOperand(0);
20503 SDValue Op1 = N->getOperand(1);
20505 // Try to synthesize horizontal adds from adds of shuffles.
20506 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) ||
20507 (Subtarget->hasInt256() && (VT == MVT::v16i16 || VT == MVT::v8i32))) &&
20508 isHorizontalBinOp(Op0, Op1, true))
20509 return DAG.getNode(X86ISD::HADD, SDLoc(N), VT, Op0, Op1);
20511 return OptimizeConditionalInDecrement(N, DAG);
20514 static SDValue PerformSubCombine(SDNode *N, SelectionDAG &DAG,
20515 const X86Subtarget *Subtarget) {
20516 SDValue Op0 = N->getOperand(0);
20517 SDValue Op1 = N->getOperand(1);
20519 // X86 can't encode an immediate LHS of a sub. See if we can push the
20520 // negation into a preceding instruction.
20521 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op0)) {
20522 // If the RHS of the sub is a XOR with one use and a constant, invert the
20523 // immediate. Then add one to the LHS of the sub so we can turn
20524 // X-Y -> X+~Y+1, saving one register.
20525 if (Op1->hasOneUse() && Op1.getOpcode() == ISD::XOR &&
20526 isa<ConstantSDNode>(Op1.getOperand(1))) {
20527 APInt XorC = cast<ConstantSDNode>(Op1.getOperand(1))->getAPIntValue();
20528 EVT VT = Op0.getValueType();
20529 SDValue NewXor = DAG.getNode(ISD::XOR, SDLoc(Op1), VT,
20531 DAG.getConstant(~XorC, VT));
20532 return DAG.getNode(ISD::ADD, SDLoc(N), VT, NewXor,
20533 DAG.getConstant(C->getAPIntValue()+1, VT));
20537 // Try to synthesize horizontal adds from adds of shuffles.
20538 EVT VT = N->getValueType(0);
20539 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) ||
20540 (Subtarget->hasInt256() && (VT == MVT::v16i16 || VT == MVT::v8i32))) &&
20541 isHorizontalBinOp(Op0, Op1, true))
20542 return DAG.getNode(X86ISD::HSUB, SDLoc(N), VT, Op0, Op1);
20544 return OptimizeConditionalInDecrement(N, DAG);
20547 /// performVZEXTCombine - Performs build vector combines
20548 static SDValue performVZEXTCombine(SDNode *N, SelectionDAG &DAG,
20549 TargetLowering::DAGCombinerInfo &DCI,
20550 const X86Subtarget *Subtarget) {
20551 // (vzext (bitcast (vzext (x)) -> (vzext x)
20552 SDValue In = N->getOperand(0);
20553 while (In.getOpcode() == ISD::BITCAST)
20554 In = In.getOperand(0);
20556 if (In.getOpcode() != X86ISD::VZEXT)
20559 return DAG.getNode(X86ISD::VZEXT, SDLoc(N), N->getValueType(0),
20563 SDValue X86TargetLowering::PerformDAGCombine(SDNode *N,
20564 DAGCombinerInfo &DCI) const {
20565 SelectionDAG &DAG = DCI.DAG;
20566 switch (N->getOpcode()) {
20568 case ISD::EXTRACT_VECTOR_ELT:
20569 return PerformEXTRACT_VECTOR_ELTCombine(N, DAG, DCI);
20571 case ISD::SELECT: return PerformSELECTCombine(N, DAG, DCI, Subtarget);
20572 case X86ISD::CMOV: return PerformCMOVCombine(N, DAG, DCI, Subtarget);
20573 case ISD::ADD: return PerformAddCombine(N, DAG, Subtarget);
20574 case ISD::SUB: return PerformSubCombine(N, DAG, Subtarget);
20575 case X86ISD::ADC: return PerformADCCombine(N, DAG, DCI);
20576 case ISD::MUL: return PerformMulCombine(N, DAG, DCI);
20579 case ISD::SRL: return PerformShiftCombine(N, DAG, DCI, Subtarget);
20580 case ISD::AND: return PerformAndCombine(N, DAG, DCI, Subtarget);
20581 case ISD::OR: return PerformOrCombine(N, DAG, DCI, Subtarget);
20582 case ISD::XOR: return PerformXorCombine(N, DAG, DCI, Subtarget);
20583 case ISD::LOAD: return PerformLOADCombine(N, DAG, DCI, Subtarget);
20584 case ISD::STORE: return PerformSTORECombine(N, DAG, Subtarget);
20585 case ISD::SINT_TO_FP: return PerformSINT_TO_FPCombine(N, DAG, this);
20586 case ISD::FADD: return PerformFADDCombine(N, DAG, Subtarget);
20587 case ISD::FSUB: return PerformFSUBCombine(N, DAG, Subtarget);
20589 case X86ISD::FOR: return PerformFORCombine(N, DAG);
20591 case X86ISD::FMAX: return PerformFMinFMaxCombine(N, DAG);
20592 case X86ISD::FAND: return PerformFANDCombine(N, DAG);
20593 case X86ISD::FANDN: return PerformFANDNCombine(N, DAG);
20594 case X86ISD::BT: return PerformBTCombine(N, DAG, DCI);
20595 case X86ISD::VZEXT_MOVL: return PerformVZEXT_MOVLCombine(N, DAG);
20596 case ISD::ANY_EXTEND:
20597 case ISD::ZERO_EXTEND: return PerformZExtCombine(N, DAG, DCI, Subtarget);
20598 case ISD::SIGN_EXTEND: return PerformSExtCombine(N, DAG, DCI, Subtarget);
20599 case ISD::SIGN_EXTEND_INREG:
20600 return PerformSIGN_EXTEND_INREGCombine(N, DAG, Subtarget);
20601 case ISD::TRUNCATE: return PerformTruncateCombine(N, DAG,DCI,Subtarget);
20602 case ISD::SETCC: return PerformISDSETCCCombine(N, DAG, Subtarget);
20603 case X86ISD::SETCC: return PerformSETCCCombine(N, DAG, DCI, Subtarget);
20604 case X86ISD::BRCOND: return PerformBrCondCombine(N, DAG, DCI, Subtarget);
20605 case X86ISD::VZEXT: return performVZEXTCombine(N, DAG, DCI, Subtarget);
20606 case X86ISD::SHUFP: // Handle all target specific shuffles
20607 case X86ISD::PALIGNR:
20608 case X86ISD::UNPCKH:
20609 case X86ISD::UNPCKL:
20610 case X86ISD::MOVHLPS:
20611 case X86ISD::MOVLHPS:
20612 case X86ISD::PSHUFD:
20613 case X86ISD::PSHUFHW:
20614 case X86ISD::PSHUFLW:
20615 case X86ISD::MOVSS:
20616 case X86ISD::MOVSD:
20617 case X86ISD::VPERMILP:
20618 case X86ISD::VPERM2X128:
20619 case ISD::VECTOR_SHUFFLE: return PerformShuffleCombine(N, DAG, DCI,Subtarget);
20620 case ISD::FMA: return PerformFMACombine(N, DAG, Subtarget);
20621 case ISD::INTRINSIC_WO_CHAIN:
20622 return PerformINTRINSIC_WO_CHAINCombine(N, DAG, Subtarget);
20623 case X86ISD::INSERTPS:
20624 return PerformINSERTPSCombine(N, DAG, Subtarget);
20630 /// isTypeDesirableForOp - Return true if the target has native support for
20631 /// the specified value type and it is 'desirable' to use the type for the
20632 /// given node type. e.g. On x86 i16 is legal, but undesirable since i16
20633 /// instruction encodings are longer and some i16 instructions are slow.
20634 bool X86TargetLowering::isTypeDesirableForOp(unsigned Opc, EVT VT) const {
20635 if (!isTypeLegal(VT))
20637 if (VT != MVT::i16)
20644 case ISD::SIGN_EXTEND:
20645 case ISD::ZERO_EXTEND:
20646 case ISD::ANY_EXTEND:
20659 /// IsDesirableToPromoteOp - This method query the target whether it is
20660 /// beneficial for dag combiner to promote the specified node. If true, it
20661 /// should return the desired promotion type by reference.
20662 bool X86TargetLowering::IsDesirableToPromoteOp(SDValue Op, EVT &PVT) const {
20663 EVT VT = Op.getValueType();
20664 if (VT != MVT::i16)
20667 bool Promote = false;
20668 bool Commute = false;
20669 switch (Op.getOpcode()) {
20672 LoadSDNode *LD = cast<LoadSDNode>(Op);
20673 // If the non-extending load has a single use and it's not live out, then it
20674 // might be folded.
20675 if (LD->getExtensionType() == ISD::NON_EXTLOAD /*&&
20676 Op.hasOneUse()*/) {
20677 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
20678 UE = Op.getNode()->use_end(); UI != UE; ++UI) {
20679 // The only case where we'd want to promote LOAD (rather then it being
20680 // promoted as an operand is when it's only use is liveout.
20681 if (UI->getOpcode() != ISD::CopyToReg)
20688 case ISD::SIGN_EXTEND:
20689 case ISD::ZERO_EXTEND:
20690 case ISD::ANY_EXTEND:
20695 SDValue N0 = Op.getOperand(0);
20696 // Look out for (store (shl (load), x)).
20697 if (MayFoldLoad(N0) && MayFoldIntoStore(Op))
20710 SDValue N0 = Op.getOperand(0);
20711 SDValue N1 = Op.getOperand(1);
20712 if (!Commute && MayFoldLoad(N1))
20714 // Avoid disabling potential load folding opportunities.
20715 if (MayFoldLoad(N0) && (!isa<ConstantSDNode>(N1) || MayFoldIntoStore(Op)))
20717 if (MayFoldLoad(N1) && (!isa<ConstantSDNode>(N0) || MayFoldIntoStore(Op)))
20727 //===----------------------------------------------------------------------===//
20728 // X86 Inline Assembly Support
20729 //===----------------------------------------------------------------------===//
20732 // Helper to match a string separated by whitespace.
20733 bool matchAsmImpl(StringRef s, ArrayRef<const StringRef *> args) {
20734 s = s.substr(s.find_first_not_of(" \t")); // Skip leading whitespace.
20736 for (unsigned i = 0, e = args.size(); i != e; ++i) {
20737 StringRef piece(*args[i]);
20738 if (!s.startswith(piece)) // Check if the piece matches.
20741 s = s.substr(piece.size());
20742 StringRef::size_type pos = s.find_first_not_of(" \t");
20743 if (pos == 0) // We matched a prefix.
20751 const VariadicFunction1<bool, StringRef, StringRef, matchAsmImpl> matchAsm={};
20754 static bool clobbersFlagRegisters(const SmallVector<StringRef, 4> &AsmPieces) {
20756 if (AsmPieces.size() == 3 || AsmPieces.size() == 4) {
20757 if (std::count(AsmPieces.begin(), AsmPieces.end(), "~{cc}") &&
20758 std::count(AsmPieces.begin(), AsmPieces.end(), "~{flags}") &&
20759 std::count(AsmPieces.begin(), AsmPieces.end(), "~{fpsr}")) {
20761 if (AsmPieces.size() == 3)
20763 else if (std::count(AsmPieces.begin(), AsmPieces.end(), "~{dirflag}"))
20770 bool X86TargetLowering::ExpandInlineAsm(CallInst *CI) const {
20771 InlineAsm *IA = cast<InlineAsm>(CI->getCalledValue());
20773 std::string AsmStr = IA->getAsmString();
20775 IntegerType *Ty = dyn_cast<IntegerType>(CI->getType());
20776 if (!Ty || Ty->getBitWidth() % 16 != 0)
20779 // TODO: should remove alternatives from the asmstring: "foo {a|b}" -> "foo a"
20780 SmallVector<StringRef, 4> AsmPieces;
20781 SplitString(AsmStr, AsmPieces, ";\n");
20783 switch (AsmPieces.size()) {
20784 default: return false;
20786 // FIXME: this should verify that we are targeting a 486 or better. If not,
20787 // we will turn this bswap into something that will be lowered to logical
20788 // ops instead of emitting the bswap asm. For now, we don't support 486 or
20789 // lower so don't worry about this.
20791 if (matchAsm(AsmPieces[0], "bswap", "$0") ||
20792 matchAsm(AsmPieces[0], "bswapl", "$0") ||
20793 matchAsm(AsmPieces[0], "bswapq", "$0") ||
20794 matchAsm(AsmPieces[0], "bswap", "${0:q}") ||
20795 matchAsm(AsmPieces[0], "bswapl", "${0:q}") ||
20796 matchAsm(AsmPieces[0], "bswapq", "${0:q}")) {
20797 // No need to check constraints, nothing other than the equivalent of
20798 // "=r,0" would be valid here.
20799 return IntrinsicLowering::LowerToByteSwap(CI);
20802 // rorw $$8, ${0:w} --> llvm.bswap.i16
20803 if (CI->getType()->isIntegerTy(16) &&
20804 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 &&
20805 (matchAsm(AsmPieces[0], "rorw", "$$8,", "${0:w}") ||
20806 matchAsm(AsmPieces[0], "rolw", "$$8,", "${0:w}"))) {
20808 const std::string &ConstraintsStr = IA->getConstraintString();
20809 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
20810 array_pod_sort(AsmPieces.begin(), AsmPieces.end());
20811 if (clobbersFlagRegisters(AsmPieces))
20812 return IntrinsicLowering::LowerToByteSwap(CI);
20816 if (CI->getType()->isIntegerTy(32) &&
20817 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 &&
20818 matchAsm(AsmPieces[0], "rorw", "$$8,", "${0:w}") &&
20819 matchAsm(AsmPieces[1], "rorl", "$$16,", "$0") &&
20820 matchAsm(AsmPieces[2], "rorw", "$$8,", "${0:w}")) {
20822 const std::string &ConstraintsStr = IA->getConstraintString();
20823 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
20824 array_pod_sort(AsmPieces.begin(), AsmPieces.end());
20825 if (clobbersFlagRegisters(AsmPieces))
20826 return IntrinsicLowering::LowerToByteSwap(CI);
20829 if (CI->getType()->isIntegerTy(64)) {
20830 InlineAsm::ConstraintInfoVector Constraints = IA->ParseConstraints();
20831 if (Constraints.size() >= 2 &&
20832 Constraints[0].Codes.size() == 1 && Constraints[0].Codes[0] == "A" &&
20833 Constraints[1].Codes.size() == 1 && Constraints[1].Codes[0] == "0") {
20834 // bswap %eax / bswap %edx / xchgl %eax, %edx -> llvm.bswap.i64
20835 if (matchAsm(AsmPieces[0], "bswap", "%eax") &&
20836 matchAsm(AsmPieces[1], "bswap", "%edx") &&
20837 matchAsm(AsmPieces[2], "xchgl", "%eax,", "%edx"))
20838 return IntrinsicLowering::LowerToByteSwap(CI);
20846 /// getConstraintType - Given a constraint letter, return the type of
20847 /// constraint it is for this target.
20848 X86TargetLowering::ConstraintType
20849 X86TargetLowering::getConstraintType(const std::string &Constraint) const {
20850 if (Constraint.size() == 1) {
20851 switch (Constraint[0]) {
20862 return C_RegisterClass;
20886 return TargetLowering::getConstraintType(Constraint);
20889 /// Examine constraint type and operand type and determine a weight value.
20890 /// This object must already have been set up with the operand type
20891 /// and the current alternative constraint selected.
20892 TargetLowering::ConstraintWeight
20893 X86TargetLowering::getSingleConstraintMatchWeight(
20894 AsmOperandInfo &info, const char *constraint) const {
20895 ConstraintWeight weight = CW_Invalid;
20896 Value *CallOperandVal = info.CallOperandVal;
20897 // If we don't have a value, we can't do a match,
20898 // but allow it at the lowest weight.
20899 if (!CallOperandVal)
20901 Type *type = CallOperandVal->getType();
20902 // Look at the constraint type.
20903 switch (*constraint) {
20905 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
20916 if (CallOperandVal->getType()->isIntegerTy())
20917 weight = CW_SpecificReg;
20922 if (type->isFloatingPointTy())
20923 weight = CW_SpecificReg;
20926 if (type->isX86_MMXTy() && Subtarget->hasMMX())
20927 weight = CW_SpecificReg;
20931 if (((type->getPrimitiveSizeInBits() == 128) && Subtarget->hasSSE1()) ||
20932 ((type->getPrimitiveSizeInBits() == 256) && Subtarget->hasFp256()))
20933 weight = CW_Register;
20936 if (ConstantInt *C = dyn_cast<ConstantInt>(info.CallOperandVal)) {
20937 if (C->getZExtValue() <= 31)
20938 weight = CW_Constant;
20942 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
20943 if (C->getZExtValue() <= 63)
20944 weight = CW_Constant;
20948 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
20949 if ((C->getSExtValue() >= -0x80) && (C->getSExtValue() <= 0x7f))
20950 weight = CW_Constant;
20954 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
20955 if ((C->getZExtValue() == 0xff) || (C->getZExtValue() == 0xffff))
20956 weight = CW_Constant;
20960 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
20961 if (C->getZExtValue() <= 3)
20962 weight = CW_Constant;
20966 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
20967 if (C->getZExtValue() <= 0xff)
20968 weight = CW_Constant;
20973 if (dyn_cast<ConstantFP>(CallOperandVal)) {
20974 weight = CW_Constant;
20978 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
20979 if ((C->getSExtValue() >= -0x80000000LL) &&
20980 (C->getSExtValue() <= 0x7fffffffLL))
20981 weight = CW_Constant;
20985 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
20986 if (C->getZExtValue() <= 0xffffffff)
20987 weight = CW_Constant;
20994 /// LowerXConstraint - try to replace an X constraint, which matches anything,
20995 /// with another that has more specific requirements based on the type of the
20996 /// corresponding operand.
20997 const char *X86TargetLowering::
20998 LowerXConstraint(EVT ConstraintVT) const {
20999 // FP X constraints get lowered to SSE1/2 registers if available, otherwise
21000 // 'f' like normal targets.
21001 if (ConstraintVT.isFloatingPoint()) {
21002 if (Subtarget->hasSSE2())
21004 if (Subtarget->hasSSE1())
21008 return TargetLowering::LowerXConstraint(ConstraintVT);
21011 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
21012 /// vector. If it is invalid, don't add anything to Ops.
21013 void X86TargetLowering::LowerAsmOperandForConstraint(SDValue Op,
21014 std::string &Constraint,
21015 std::vector<SDValue>&Ops,
21016 SelectionDAG &DAG) const {
21019 // Only support length 1 constraints for now.
21020 if (Constraint.length() > 1) return;
21022 char ConstraintLetter = Constraint[0];
21023 switch (ConstraintLetter) {
21026 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
21027 if (C->getZExtValue() <= 31) {
21028 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
21034 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
21035 if (C->getZExtValue() <= 63) {
21036 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
21042 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
21043 if (isInt<8>(C->getSExtValue())) {
21044 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
21050 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
21051 if (C->getZExtValue() <= 255) {
21052 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
21058 // 32-bit signed value
21059 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
21060 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
21061 C->getSExtValue())) {
21062 // Widen to 64 bits here to get it sign extended.
21063 Result = DAG.getTargetConstant(C->getSExtValue(), MVT::i64);
21066 // FIXME gcc accepts some relocatable values here too, but only in certain
21067 // memory models; it's complicated.
21072 // 32-bit unsigned value
21073 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
21074 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
21075 C->getZExtValue())) {
21076 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
21080 // FIXME gcc accepts some relocatable values here too, but only in certain
21081 // memory models; it's complicated.
21085 // Literal immediates are always ok.
21086 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op)) {
21087 // Widen to 64 bits here to get it sign extended.
21088 Result = DAG.getTargetConstant(CST->getSExtValue(), MVT::i64);
21092 // In any sort of PIC mode addresses need to be computed at runtime by
21093 // adding in a register or some sort of table lookup. These can't
21094 // be used as immediates.
21095 if (Subtarget->isPICStyleGOT() || Subtarget->isPICStyleStubPIC())
21098 // If we are in non-pic codegen mode, we allow the address of a global (with
21099 // an optional displacement) to be used with 'i'.
21100 GlobalAddressSDNode *GA = nullptr;
21101 int64_t Offset = 0;
21103 // Match either (GA), (GA+C), (GA+C1+C2), etc.
21105 if ((GA = dyn_cast<GlobalAddressSDNode>(Op))) {
21106 Offset += GA->getOffset();
21108 } else if (Op.getOpcode() == ISD::ADD) {
21109 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
21110 Offset += C->getZExtValue();
21111 Op = Op.getOperand(0);
21114 } else if (Op.getOpcode() == ISD::SUB) {
21115 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
21116 Offset += -C->getZExtValue();
21117 Op = Op.getOperand(0);
21122 // Otherwise, this isn't something we can handle, reject it.
21126 const GlobalValue *GV = GA->getGlobal();
21127 // If we require an extra load to get this address, as in PIC mode, we
21128 // can't accept it.
21129 if (isGlobalStubReference(Subtarget->ClassifyGlobalReference(GV,
21130 getTargetMachine())))
21133 Result = DAG.getTargetGlobalAddress(GV, SDLoc(Op),
21134 GA->getValueType(0), Offset);
21139 if (Result.getNode()) {
21140 Ops.push_back(Result);
21143 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
21146 std::pair<unsigned, const TargetRegisterClass*>
21147 X86TargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
21149 // First, see if this is a constraint that directly corresponds to an LLVM
21151 if (Constraint.size() == 1) {
21152 // GCC Constraint Letters
21153 switch (Constraint[0]) {
21155 // TODO: Slight differences here in allocation order and leaving
21156 // RIP in the class. Do they matter any more here than they do
21157 // in the normal allocation?
21158 case 'q': // GENERAL_REGS in 64-bit mode, Q_REGS in 32-bit mode.
21159 if (Subtarget->is64Bit()) {
21160 if (VT == MVT::i32 || VT == MVT::f32)
21161 return std::make_pair(0U, &X86::GR32RegClass);
21162 if (VT == MVT::i16)
21163 return std::make_pair(0U, &X86::GR16RegClass);
21164 if (VT == MVT::i8 || VT == MVT::i1)
21165 return std::make_pair(0U, &X86::GR8RegClass);
21166 if (VT == MVT::i64 || VT == MVT::f64)
21167 return std::make_pair(0U, &X86::GR64RegClass);
21170 // 32-bit fallthrough
21171 case 'Q': // Q_REGS
21172 if (VT == MVT::i32 || VT == MVT::f32)
21173 return std::make_pair(0U, &X86::GR32_ABCDRegClass);
21174 if (VT == MVT::i16)
21175 return std::make_pair(0U, &X86::GR16_ABCDRegClass);
21176 if (VT == MVT::i8 || VT == MVT::i1)
21177 return std::make_pair(0U, &X86::GR8_ABCD_LRegClass);
21178 if (VT == MVT::i64)
21179 return std::make_pair(0U, &X86::GR64_ABCDRegClass);
21181 case 'r': // GENERAL_REGS
21182 case 'l': // INDEX_REGS
21183 if (VT == MVT::i8 || VT == MVT::i1)
21184 return std::make_pair(0U, &X86::GR8RegClass);
21185 if (VT == MVT::i16)
21186 return std::make_pair(0U, &X86::GR16RegClass);
21187 if (VT == MVT::i32 || VT == MVT::f32 || !Subtarget->is64Bit())
21188 return std::make_pair(0U, &X86::GR32RegClass);
21189 return std::make_pair(0U, &X86::GR64RegClass);
21190 case 'R': // LEGACY_REGS
21191 if (VT == MVT::i8 || VT == MVT::i1)
21192 return std::make_pair(0U, &X86::GR8_NOREXRegClass);
21193 if (VT == MVT::i16)
21194 return std::make_pair(0U, &X86::GR16_NOREXRegClass);
21195 if (VT == MVT::i32 || !Subtarget->is64Bit())
21196 return std::make_pair(0U, &X86::GR32_NOREXRegClass);
21197 return std::make_pair(0U, &X86::GR64_NOREXRegClass);
21198 case 'f': // FP Stack registers.
21199 // If SSE is enabled for this VT, use f80 to ensure the isel moves the
21200 // value to the correct fpstack register class.
21201 if (VT == MVT::f32 && !isScalarFPTypeInSSEReg(VT))
21202 return std::make_pair(0U, &X86::RFP32RegClass);
21203 if (VT == MVT::f64 && !isScalarFPTypeInSSEReg(VT))
21204 return std::make_pair(0U, &X86::RFP64RegClass);
21205 return std::make_pair(0U, &X86::RFP80RegClass);
21206 case 'y': // MMX_REGS if MMX allowed.
21207 if (!Subtarget->hasMMX()) break;
21208 return std::make_pair(0U, &X86::VR64RegClass);
21209 case 'Y': // SSE_REGS if SSE2 allowed
21210 if (!Subtarget->hasSSE2()) break;
21212 case 'x': // SSE_REGS if SSE1 allowed or AVX_REGS if AVX allowed
21213 if (!Subtarget->hasSSE1()) break;
21215 switch (VT.SimpleTy) {
21217 // Scalar SSE types.
21220 return std::make_pair(0U, &X86::FR32RegClass);
21223 return std::make_pair(0U, &X86::FR64RegClass);
21231 return std::make_pair(0U, &X86::VR128RegClass);
21239 return std::make_pair(0U, &X86::VR256RegClass);
21244 return std::make_pair(0U, &X86::VR512RegClass);
21250 // Use the default implementation in TargetLowering to convert the register
21251 // constraint into a member of a register class.
21252 std::pair<unsigned, const TargetRegisterClass*> Res;
21253 Res = TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
21255 // Not found as a standard register?
21257 // Map st(0) -> st(7) -> ST0
21258 if (Constraint.size() == 7 && Constraint[0] == '{' &&
21259 tolower(Constraint[1]) == 's' &&
21260 tolower(Constraint[2]) == 't' &&
21261 Constraint[3] == '(' &&
21262 (Constraint[4] >= '0' && Constraint[4] <= '7') &&
21263 Constraint[5] == ')' &&
21264 Constraint[6] == '}') {
21266 Res.first = X86::ST0+Constraint[4]-'0';
21267 Res.second = &X86::RFP80RegClass;
21271 // GCC allows "st(0)" to be called just plain "st".
21272 if (StringRef("{st}").equals_lower(Constraint)) {
21273 Res.first = X86::ST0;
21274 Res.second = &X86::RFP80RegClass;
21279 if (StringRef("{flags}").equals_lower(Constraint)) {
21280 Res.first = X86::EFLAGS;
21281 Res.second = &X86::CCRRegClass;
21285 // 'A' means EAX + EDX.
21286 if (Constraint == "A") {
21287 Res.first = X86::EAX;
21288 Res.second = &X86::GR32_ADRegClass;
21294 // Otherwise, check to see if this is a register class of the wrong value
21295 // type. For example, we want to map "{ax},i32" -> {eax}, we don't want it to
21296 // turn into {ax},{dx}.
21297 if (Res.second->hasType(VT))
21298 return Res; // Correct type already, nothing to do.
21300 // All of the single-register GCC register classes map their values onto
21301 // 16-bit register pieces "ax","dx","cx","bx","si","di","bp","sp". If we
21302 // really want an 8-bit or 32-bit register, map to the appropriate register
21303 // class and return the appropriate register.
21304 if (Res.second == &X86::GR16RegClass) {
21305 if (VT == MVT::i8 || VT == MVT::i1) {
21306 unsigned DestReg = 0;
21307 switch (Res.first) {
21309 case X86::AX: DestReg = X86::AL; break;
21310 case X86::DX: DestReg = X86::DL; break;
21311 case X86::CX: DestReg = X86::CL; break;
21312 case X86::BX: DestReg = X86::BL; break;
21315 Res.first = DestReg;
21316 Res.second = &X86::GR8RegClass;
21318 } else if (VT == MVT::i32 || VT == MVT::f32) {
21319 unsigned DestReg = 0;
21320 switch (Res.first) {
21322 case X86::AX: DestReg = X86::EAX; break;
21323 case X86::DX: DestReg = X86::EDX; break;
21324 case X86::CX: DestReg = X86::ECX; break;
21325 case X86::BX: DestReg = X86::EBX; break;
21326 case X86::SI: DestReg = X86::ESI; break;
21327 case X86::DI: DestReg = X86::EDI; break;
21328 case X86::BP: DestReg = X86::EBP; break;
21329 case X86::SP: DestReg = X86::ESP; break;
21332 Res.first = DestReg;
21333 Res.second = &X86::GR32RegClass;
21335 } else if (VT == MVT::i64 || VT == MVT::f64) {
21336 unsigned DestReg = 0;
21337 switch (Res.first) {
21339 case X86::AX: DestReg = X86::RAX; break;
21340 case X86::DX: DestReg = X86::RDX; break;
21341 case X86::CX: DestReg = X86::RCX; break;
21342 case X86::BX: DestReg = X86::RBX; break;
21343 case X86::SI: DestReg = X86::RSI; break;
21344 case X86::DI: DestReg = X86::RDI; break;
21345 case X86::BP: DestReg = X86::RBP; break;
21346 case X86::SP: DestReg = X86::RSP; break;
21349 Res.first = DestReg;
21350 Res.second = &X86::GR64RegClass;
21353 } else if (Res.second == &X86::FR32RegClass ||
21354 Res.second == &X86::FR64RegClass ||
21355 Res.second == &X86::VR128RegClass ||
21356 Res.second == &X86::VR256RegClass ||
21357 Res.second == &X86::FR32XRegClass ||
21358 Res.second == &X86::FR64XRegClass ||
21359 Res.second == &X86::VR128XRegClass ||
21360 Res.second == &X86::VR256XRegClass ||
21361 Res.second == &X86::VR512RegClass) {
21362 // Handle references to XMM physical registers that got mapped into the
21363 // wrong class. This can happen with constraints like {xmm0} where the
21364 // target independent register mapper will just pick the first match it can
21365 // find, ignoring the required type.
21367 if (VT == MVT::f32 || VT == MVT::i32)
21368 Res.second = &X86::FR32RegClass;
21369 else if (VT == MVT::f64 || VT == MVT::i64)
21370 Res.second = &X86::FR64RegClass;
21371 else if (X86::VR128RegClass.hasType(VT))
21372 Res.second = &X86::VR128RegClass;
21373 else if (X86::VR256RegClass.hasType(VT))
21374 Res.second = &X86::VR256RegClass;
21375 else if (X86::VR512RegClass.hasType(VT))
21376 Res.second = &X86::VR512RegClass;
21382 int X86TargetLowering::getScalingFactorCost(const AddrMode &AM,
21384 // Scaling factors are not free at all.
21385 // An indexed folded instruction, i.e., inst (reg1, reg2, scale),
21386 // will take 2 allocations in the out of order engine instead of 1
21387 // for plain addressing mode, i.e. inst (reg1).
21389 // vaddps (%rsi,%drx), %ymm0, %ymm1
21390 // Requires two allocations (one for the load, one for the computation)
21392 // vaddps (%rsi), %ymm0, %ymm1
21393 // Requires just 1 allocation, i.e., freeing allocations for other operations
21394 // and having less micro operations to execute.
21396 // For some X86 architectures, this is even worse because for instance for
21397 // stores, the complex addressing mode forces the instruction to use the
21398 // "load" ports instead of the dedicated "store" port.
21399 // E.g., on Haswell:
21400 // vmovaps %ymm1, (%r8, %rdi) can use port 2 or 3.
21401 // vmovaps %ymm1, (%r8) can use port 2, 3, or 7.
21402 if (isLegalAddressingMode(AM, Ty))
21403 // Scale represents reg2 * scale, thus account for 1
21404 // as soon as we use a second register.
21405 return AM.Scale != 0;