1 //===-- X86ISelLowering.cpp - X86 DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that X86 uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #include "X86ISelLowering.h"
16 #include "Utils/X86ShuffleDecode.h"
17 #include "X86CallingConv.h"
18 #include "X86FrameLowering.h"
19 #include "X86InstrBuilder.h"
20 #include "X86MachineFunctionInfo.h"
21 #include "X86TargetMachine.h"
22 #include "X86TargetObjectFile.h"
23 #include "llvm/ADT/SmallBitVector.h"
24 #include "llvm/ADT/SmallSet.h"
25 #include "llvm/ADT/Statistic.h"
26 #include "llvm/ADT/StringExtras.h"
27 #include "llvm/ADT/StringSwitch.h"
28 #include "llvm/CodeGen/IntrinsicLowering.h"
29 #include "llvm/CodeGen/MachineFrameInfo.h"
30 #include "llvm/CodeGen/MachineFunction.h"
31 #include "llvm/CodeGen/MachineInstrBuilder.h"
32 #include "llvm/CodeGen/MachineJumpTableInfo.h"
33 #include "llvm/CodeGen/MachineModuleInfo.h"
34 #include "llvm/CodeGen/MachineRegisterInfo.h"
35 #include "llvm/CodeGen/WinEHFuncInfo.h"
36 #include "llvm/IR/CallSite.h"
37 #include "llvm/IR/CallingConv.h"
38 #include "llvm/IR/Constants.h"
39 #include "llvm/IR/DerivedTypes.h"
40 #include "llvm/IR/Function.h"
41 #include "llvm/IR/GlobalAlias.h"
42 #include "llvm/IR/GlobalVariable.h"
43 #include "llvm/IR/Instructions.h"
44 #include "llvm/IR/Intrinsics.h"
45 #include "llvm/MC/MCAsmInfo.h"
46 #include "llvm/MC/MCContext.h"
47 #include "llvm/MC/MCExpr.h"
48 #include "llvm/MC/MCSymbol.h"
49 #include "llvm/Support/CommandLine.h"
50 #include "llvm/Support/Debug.h"
51 #include "llvm/Support/ErrorHandling.h"
52 #include "llvm/Support/MathExtras.h"
53 #include "llvm/Target/TargetOptions.h"
54 #include "X86IntrinsicsInfo.h"
60 #define DEBUG_TYPE "x86-isel"
62 STATISTIC(NumTailCalls, "Number of tail calls");
64 static cl::opt<bool> ExperimentalVectorWideningLegalization(
65 "x86-experimental-vector-widening-legalization", cl::init(false),
66 cl::desc("Enable an experimental vector type legalization through widening "
67 "rather than promotion."),
70 // Forward declarations.
71 static SDValue getMOVL(SelectionDAG &DAG, SDLoc dl, EVT VT, SDValue V1,
74 X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM,
75 const X86Subtarget &STI)
76 : TargetLowering(TM), Subtarget(&STI) {
77 X86ScalarSSEf64 = Subtarget->hasSSE2();
78 X86ScalarSSEf32 = Subtarget->hasSSE1();
81 // Set up the TargetLowering object.
82 static const MVT IntVTs[] = { MVT::i8, MVT::i16, MVT::i32, MVT::i64 };
84 // X86 is weird. It always uses i8 for shift amounts and setcc results.
85 setBooleanContents(ZeroOrOneBooleanContent);
86 // X86-SSE is even stranger. It uses -1 or 0 for vector masks.
87 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
89 // For 64-bit, since we have so many registers, use the ILP scheduler.
90 // For 32-bit, use the register pressure specific scheduling.
91 // For Atom, always use ILP scheduling.
92 if (Subtarget->isAtom())
93 setSchedulingPreference(Sched::ILP);
94 else if (Subtarget->is64Bit())
95 setSchedulingPreference(Sched::ILP);
97 setSchedulingPreference(Sched::RegPressure);
98 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
99 setStackPointerRegisterToSaveRestore(RegInfo->getStackRegister());
101 // Bypass expensive divides on Atom when compiling with O2.
102 if (TM.getOptLevel() >= CodeGenOpt::Default) {
103 if (Subtarget->hasSlowDivide32())
104 addBypassSlowDiv(32, 8);
105 if (Subtarget->hasSlowDivide64() && Subtarget->is64Bit())
106 addBypassSlowDiv(64, 16);
109 if (Subtarget->isTargetKnownWindowsMSVC()) {
110 // Setup Windows compiler runtime calls.
111 setLibcallName(RTLIB::SDIV_I64, "_alldiv");
112 setLibcallName(RTLIB::UDIV_I64, "_aulldiv");
113 setLibcallName(RTLIB::SREM_I64, "_allrem");
114 setLibcallName(RTLIB::UREM_I64, "_aullrem");
115 setLibcallName(RTLIB::MUL_I64, "_allmul");
116 setLibcallCallingConv(RTLIB::SDIV_I64, CallingConv::X86_StdCall);
117 setLibcallCallingConv(RTLIB::UDIV_I64, CallingConv::X86_StdCall);
118 setLibcallCallingConv(RTLIB::SREM_I64, CallingConv::X86_StdCall);
119 setLibcallCallingConv(RTLIB::UREM_I64, CallingConv::X86_StdCall);
120 setLibcallCallingConv(RTLIB::MUL_I64, CallingConv::X86_StdCall);
122 // The _ftol2 runtime function has an unusual calling conv, which
123 // is modeled by a special pseudo-instruction.
124 setLibcallName(RTLIB::FPTOUINT_F64_I64, nullptr);
125 setLibcallName(RTLIB::FPTOUINT_F32_I64, nullptr);
126 setLibcallName(RTLIB::FPTOUINT_F64_I32, nullptr);
127 setLibcallName(RTLIB::FPTOUINT_F32_I32, nullptr);
130 if (Subtarget->isTargetDarwin()) {
131 // Darwin should use _setjmp/_longjmp instead of setjmp/longjmp.
132 setUseUnderscoreSetJmp(false);
133 setUseUnderscoreLongJmp(false);
134 } else if (Subtarget->isTargetWindowsGNU()) {
135 // MS runtime is weird: it exports _setjmp, but longjmp!
136 setUseUnderscoreSetJmp(true);
137 setUseUnderscoreLongJmp(false);
139 setUseUnderscoreSetJmp(true);
140 setUseUnderscoreLongJmp(true);
143 // Set up the register classes.
144 addRegisterClass(MVT::i8, &X86::GR8RegClass);
145 addRegisterClass(MVT::i16, &X86::GR16RegClass);
146 addRegisterClass(MVT::i32, &X86::GR32RegClass);
147 if (Subtarget->is64Bit())
148 addRegisterClass(MVT::i64, &X86::GR64RegClass);
150 for (MVT VT : MVT::integer_valuetypes())
151 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote);
153 // We don't accept any truncstore of integer registers.
154 setTruncStoreAction(MVT::i64, MVT::i32, Expand);
155 setTruncStoreAction(MVT::i64, MVT::i16, Expand);
156 setTruncStoreAction(MVT::i64, MVT::i8 , Expand);
157 setTruncStoreAction(MVT::i32, MVT::i16, Expand);
158 setTruncStoreAction(MVT::i32, MVT::i8 , Expand);
159 setTruncStoreAction(MVT::i16, MVT::i8, Expand);
161 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
163 // SETOEQ and SETUNE require checking two conditions.
164 setCondCodeAction(ISD::SETOEQ, MVT::f32, Expand);
165 setCondCodeAction(ISD::SETOEQ, MVT::f64, Expand);
166 setCondCodeAction(ISD::SETOEQ, MVT::f80, Expand);
167 setCondCodeAction(ISD::SETUNE, MVT::f32, Expand);
168 setCondCodeAction(ISD::SETUNE, MVT::f64, Expand);
169 setCondCodeAction(ISD::SETUNE, MVT::f80, Expand);
171 // Promote all UINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have this
173 setOperationAction(ISD::UINT_TO_FP , MVT::i1 , Promote);
174 setOperationAction(ISD::UINT_TO_FP , MVT::i8 , Promote);
175 setOperationAction(ISD::UINT_TO_FP , MVT::i16 , Promote);
177 if (Subtarget->is64Bit()) {
178 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote);
179 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
180 } else if (!Subtarget->useSoftFloat()) {
181 // We have an algorithm for SSE2->double, and we turn this into a
182 // 64-bit FILD followed by conditional FADD for other targets.
183 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
184 // We have an algorithm for SSE2, and we turn this into a 64-bit
185 // FILD for other targets.
186 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Custom);
189 // Promote i1/i8 SINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have
191 setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote);
192 setOperationAction(ISD::SINT_TO_FP , MVT::i8 , Promote);
194 if (!Subtarget->useSoftFloat()) {
195 // SSE has no i16 to fp conversion, only i32
196 if (X86ScalarSSEf32) {
197 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
198 // f32 and f64 cases are Legal, f80 case is not
199 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
201 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Custom);
202 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
205 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
206 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Promote);
209 // In 32-bit mode these are custom lowered. In 64-bit mode F32 and F64
210 // are Legal, f80 is custom lowered.
211 setOperationAction(ISD::FP_TO_SINT , MVT::i64 , Custom);
212 setOperationAction(ISD::SINT_TO_FP , MVT::i64 , Custom);
214 // Promote i1/i8 FP_TO_SINT to larger FP_TO_SINTS's, as X86 doesn't have
216 setOperationAction(ISD::FP_TO_SINT , MVT::i1 , Promote);
217 setOperationAction(ISD::FP_TO_SINT , MVT::i8 , Promote);
219 if (X86ScalarSSEf32) {
220 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Promote);
221 // f32 and f64 cases are Legal, f80 case is not
222 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
224 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Custom);
225 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
228 // Handle FP_TO_UINT by promoting the destination to a larger signed
230 setOperationAction(ISD::FP_TO_UINT , MVT::i1 , Promote);
231 setOperationAction(ISD::FP_TO_UINT , MVT::i8 , Promote);
232 setOperationAction(ISD::FP_TO_UINT , MVT::i16 , Promote);
234 if (Subtarget->is64Bit()) {
235 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Expand);
236 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote);
237 } else if (!Subtarget->useSoftFloat()) {
238 // Since AVX is a superset of SSE3, only check for SSE here.
239 if (Subtarget->hasSSE1() && !Subtarget->hasSSE3())
240 // Expand FP_TO_UINT into a select.
241 // FIXME: We would like to use a Custom expander here eventually to do
242 // the optimal thing for SSE vs. the default expansion in the legalizer.
243 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Expand);
245 // With SSE3 we can use fisttpll to convert to a signed i64; without
246 // SSE, we're stuck with a fistpll.
247 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Custom);
250 if (isTargetFTOL()) {
251 // Use the _ftol2 runtime function, which has a pseudo-instruction
252 // to handle its weird calling convention.
253 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Custom);
256 // TODO: when we have SSE, these could be more efficient, by using movd/movq.
257 if (!X86ScalarSSEf64) {
258 setOperationAction(ISD::BITCAST , MVT::f32 , Expand);
259 setOperationAction(ISD::BITCAST , MVT::i32 , Expand);
260 if (Subtarget->is64Bit()) {
261 setOperationAction(ISD::BITCAST , MVT::f64 , Expand);
262 // Without SSE, i64->f64 goes through memory.
263 setOperationAction(ISD::BITCAST , MVT::i64 , Expand);
267 // Scalar integer divide and remainder are lowered to use operations that
268 // produce two results, to match the available instructions. This exposes
269 // the two-result form to trivial CSE, which is able to combine x/y and x%y
270 // into a single instruction.
272 // Scalar integer multiply-high is also lowered to use two-result
273 // operations, to match the available instructions. However, plain multiply
274 // (low) operations are left as Legal, as there are single-result
275 // instructions for this in x86. Using the two-result multiply instructions
276 // when both high and low results are needed must be arranged by dagcombine.
277 for (unsigned i = 0; i != array_lengthof(IntVTs); ++i) {
279 setOperationAction(ISD::MULHS, VT, Expand);
280 setOperationAction(ISD::MULHU, VT, Expand);
281 setOperationAction(ISD::SDIV, VT, Expand);
282 setOperationAction(ISD::UDIV, VT, Expand);
283 setOperationAction(ISD::SREM, VT, Expand);
284 setOperationAction(ISD::UREM, VT, Expand);
286 // Add/Sub overflow ops with MVT::Glues are lowered to EFLAGS dependences.
287 setOperationAction(ISD::ADDC, VT, Custom);
288 setOperationAction(ISD::ADDE, VT, Custom);
289 setOperationAction(ISD::SUBC, VT, Custom);
290 setOperationAction(ISD::SUBE, VT, Custom);
293 setOperationAction(ISD::BR_JT , MVT::Other, Expand);
294 setOperationAction(ISD::BRCOND , MVT::Other, Custom);
295 setOperationAction(ISD::BR_CC , MVT::f32, Expand);
296 setOperationAction(ISD::BR_CC , MVT::f64, Expand);
297 setOperationAction(ISD::BR_CC , MVT::f80, Expand);
298 setOperationAction(ISD::BR_CC , MVT::i8, Expand);
299 setOperationAction(ISD::BR_CC , MVT::i16, Expand);
300 setOperationAction(ISD::BR_CC , MVT::i32, Expand);
301 setOperationAction(ISD::BR_CC , MVT::i64, Expand);
302 setOperationAction(ISD::SELECT_CC , MVT::f32, Expand);
303 setOperationAction(ISD::SELECT_CC , MVT::f64, Expand);
304 setOperationAction(ISD::SELECT_CC , MVT::f80, Expand);
305 setOperationAction(ISD::SELECT_CC , MVT::i8, Expand);
306 setOperationAction(ISD::SELECT_CC , MVT::i16, Expand);
307 setOperationAction(ISD::SELECT_CC , MVT::i32, Expand);
308 setOperationAction(ISD::SELECT_CC , MVT::i64, Expand);
309 if (Subtarget->is64Bit())
310 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal);
311 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Legal);
312 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Legal);
313 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
314 setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand);
315 setOperationAction(ISD::FREM , MVT::f32 , Expand);
316 setOperationAction(ISD::FREM , MVT::f64 , Expand);
317 setOperationAction(ISD::FREM , MVT::f80 , Expand);
318 setOperationAction(ISD::FLT_ROUNDS_ , MVT::i32 , Custom);
320 // Promote the i8 variants and force them on up to i32 which has a shorter
322 setOperationAction(ISD::CTTZ , MVT::i8 , Promote);
323 AddPromotedToType (ISD::CTTZ , MVT::i8 , MVT::i32);
324 setOperationAction(ISD::CTTZ_ZERO_UNDEF , MVT::i8 , Promote);
325 AddPromotedToType (ISD::CTTZ_ZERO_UNDEF , MVT::i8 , MVT::i32);
326 if (Subtarget->hasBMI()) {
327 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i16 , Expand);
328 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32 , Expand);
329 if (Subtarget->is64Bit())
330 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand);
332 setOperationAction(ISD::CTTZ , MVT::i16 , Custom);
333 setOperationAction(ISD::CTTZ , MVT::i32 , Custom);
334 if (Subtarget->is64Bit())
335 setOperationAction(ISD::CTTZ , MVT::i64 , Custom);
338 if (Subtarget->hasLZCNT()) {
339 // When promoting the i8 variants, force them to i32 for a shorter
341 setOperationAction(ISD::CTLZ , MVT::i8 , Promote);
342 AddPromotedToType (ISD::CTLZ , MVT::i8 , MVT::i32);
343 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Promote);
344 AddPromotedToType (ISD::CTLZ_ZERO_UNDEF, MVT::i8 , MVT::i32);
345 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Expand);
346 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Expand);
347 if (Subtarget->is64Bit())
348 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Expand);
350 setOperationAction(ISD::CTLZ , MVT::i8 , Custom);
351 setOperationAction(ISD::CTLZ , MVT::i16 , Custom);
352 setOperationAction(ISD::CTLZ , MVT::i32 , Custom);
353 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Custom);
354 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Custom);
355 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Custom);
356 if (Subtarget->is64Bit()) {
357 setOperationAction(ISD::CTLZ , MVT::i64 , Custom);
358 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Custom);
362 // Special handling for half-precision floating point conversions.
363 // If we don't have F16C support, then lower half float conversions
364 // into library calls.
365 if (Subtarget->useSoftFloat() || !Subtarget->hasF16C()) {
366 setOperationAction(ISD::FP16_TO_FP, MVT::f32, Expand);
367 setOperationAction(ISD::FP_TO_FP16, MVT::f32, Expand);
370 // There's never any support for operations beyond MVT::f32.
371 setOperationAction(ISD::FP16_TO_FP, MVT::f64, Expand);
372 setOperationAction(ISD::FP16_TO_FP, MVT::f80, Expand);
373 setOperationAction(ISD::FP_TO_FP16, MVT::f64, Expand);
374 setOperationAction(ISD::FP_TO_FP16, MVT::f80, Expand);
376 setLoadExtAction(ISD::EXTLOAD, MVT::f32, MVT::f16, Expand);
377 setLoadExtAction(ISD::EXTLOAD, MVT::f64, MVT::f16, Expand);
378 setLoadExtAction(ISD::EXTLOAD, MVT::f80, MVT::f16, Expand);
379 setTruncStoreAction(MVT::f32, MVT::f16, Expand);
380 setTruncStoreAction(MVT::f64, MVT::f16, Expand);
381 setTruncStoreAction(MVT::f80, MVT::f16, Expand);
383 if (Subtarget->hasPOPCNT()) {
384 setOperationAction(ISD::CTPOP , MVT::i8 , Promote);
386 setOperationAction(ISD::CTPOP , MVT::i8 , Expand);
387 setOperationAction(ISD::CTPOP , MVT::i16 , Expand);
388 setOperationAction(ISD::CTPOP , MVT::i32 , Expand);
389 if (Subtarget->is64Bit())
390 setOperationAction(ISD::CTPOP , MVT::i64 , Expand);
393 setOperationAction(ISD::READCYCLECOUNTER , MVT::i64 , Custom);
395 if (!Subtarget->hasMOVBE())
396 setOperationAction(ISD::BSWAP , MVT::i16 , Expand);
398 // These should be promoted to a larger select which is supported.
399 setOperationAction(ISD::SELECT , MVT::i1 , Promote);
400 // X86 wants to expand cmov itself.
401 setOperationAction(ISD::SELECT , MVT::i8 , Custom);
402 setOperationAction(ISD::SELECT , MVT::i16 , Custom);
403 setOperationAction(ISD::SELECT , MVT::i32 , Custom);
404 setOperationAction(ISD::SELECT , MVT::f32 , Custom);
405 setOperationAction(ISD::SELECT , MVT::f64 , Custom);
406 setOperationAction(ISD::SELECT , MVT::f80 , Custom);
407 setOperationAction(ISD::SETCC , MVT::i8 , Custom);
408 setOperationAction(ISD::SETCC , MVT::i16 , Custom);
409 setOperationAction(ISD::SETCC , MVT::i32 , Custom);
410 setOperationAction(ISD::SETCC , MVT::f32 , Custom);
411 setOperationAction(ISD::SETCC , MVT::f64 , Custom);
412 setOperationAction(ISD::SETCC , MVT::f80 , Custom);
413 if (Subtarget->is64Bit()) {
414 setOperationAction(ISD::SELECT , MVT::i64 , Custom);
415 setOperationAction(ISD::SETCC , MVT::i64 , Custom);
417 setOperationAction(ISD::EH_RETURN , MVT::Other, Custom);
418 // NOTE: EH_SJLJ_SETJMP/_LONGJMP supported here is NOT intended to support
419 // SjLj exception handling but a light-weight setjmp/longjmp replacement to
420 // support continuation, user-level threading, and etc.. As a result, no
421 // other SjLj exception interfaces are implemented and please don't build
422 // your own exception handling based on them.
423 // LLVM/Clang supports zero-cost DWARF exception handling.
424 setOperationAction(ISD::EH_SJLJ_SETJMP, MVT::i32, Custom);
425 setOperationAction(ISD::EH_SJLJ_LONGJMP, MVT::Other, Custom);
428 setOperationAction(ISD::ConstantPool , MVT::i32 , Custom);
429 setOperationAction(ISD::JumpTable , MVT::i32 , Custom);
430 setOperationAction(ISD::GlobalAddress , MVT::i32 , Custom);
431 setOperationAction(ISD::GlobalTLSAddress, MVT::i32 , Custom);
432 if (Subtarget->is64Bit())
433 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
434 setOperationAction(ISD::ExternalSymbol , MVT::i32 , Custom);
435 setOperationAction(ISD::BlockAddress , MVT::i32 , Custom);
436 if (Subtarget->is64Bit()) {
437 setOperationAction(ISD::ConstantPool , MVT::i64 , Custom);
438 setOperationAction(ISD::JumpTable , MVT::i64 , Custom);
439 setOperationAction(ISD::GlobalAddress , MVT::i64 , Custom);
440 setOperationAction(ISD::ExternalSymbol, MVT::i64 , Custom);
441 setOperationAction(ISD::BlockAddress , MVT::i64 , Custom);
443 // 64-bit addm sub, shl, sra, srl (iff 32-bit x86)
444 setOperationAction(ISD::SHL_PARTS , MVT::i32 , Custom);
445 setOperationAction(ISD::SRA_PARTS , MVT::i32 , Custom);
446 setOperationAction(ISD::SRL_PARTS , MVT::i32 , Custom);
447 if (Subtarget->is64Bit()) {
448 setOperationAction(ISD::SHL_PARTS , MVT::i64 , Custom);
449 setOperationAction(ISD::SRA_PARTS , MVT::i64 , Custom);
450 setOperationAction(ISD::SRL_PARTS , MVT::i64 , Custom);
453 if (Subtarget->hasSSE1())
454 setOperationAction(ISD::PREFETCH , MVT::Other, Legal);
456 setOperationAction(ISD::ATOMIC_FENCE , MVT::Other, Custom);
458 // Expand certain atomics
459 for (unsigned i = 0; i != array_lengthof(IntVTs); ++i) {
461 setOperationAction(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, VT, Custom);
462 setOperationAction(ISD::ATOMIC_LOAD_SUB, VT, Custom);
463 setOperationAction(ISD::ATOMIC_STORE, VT, Custom);
466 if (Subtarget->hasCmpxchg16b()) {
467 setOperationAction(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, MVT::i128, Custom);
470 // FIXME - use subtarget debug flags
471 if (!Subtarget->isTargetDarwin() && !Subtarget->isTargetELF() &&
472 !Subtarget->isTargetCygMing() && !Subtarget->isTargetWin64()) {
473 setOperationAction(ISD::EH_LABEL, MVT::Other, Expand);
476 if (Subtarget->is64Bit()) {
477 setExceptionPointerRegister(X86::RAX);
478 setExceptionSelectorRegister(X86::RDX);
480 setExceptionPointerRegister(X86::EAX);
481 setExceptionSelectorRegister(X86::EDX);
483 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i32, Custom);
484 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i64, Custom);
486 setOperationAction(ISD::INIT_TRAMPOLINE, MVT::Other, Custom);
487 setOperationAction(ISD::ADJUST_TRAMPOLINE, MVT::Other, Custom);
489 setOperationAction(ISD::TRAP, MVT::Other, Legal);
490 setOperationAction(ISD::DEBUGTRAP, MVT::Other, Legal);
492 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
493 setOperationAction(ISD::VASTART , MVT::Other, Custom);
494 setOperationAction(ISD::VAEND , MVT::Other, Expand);
495 if (Subtarget->is64Bit() && !Subtarget->isTargetWin64()) {
496 // TargetInfo::X86_64ABIBuiltinVaList
497 setOperationAction(ISD::VAARG , MVT::Other, Custom);
498 setOperationAction(ISD::VACOPY , MVT::Other, Custom);
500 // TargetInfo::CharPtrBuiltinVaList
501 setOperationAction(ISD::VAARG , MVT::Other, Expand);
502 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
505 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
506 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
508 setOperationAction(ISD::DYNAMIC_STACKALLOC, getPointerTy(), Custom);
510 // GC_TRANSITION_START and GC_TRANSITION_END need custom lowering.
511 setOperationAction(ISD::GC_TRANSITION_START, MVT::Other, Custom);
512 setOperationAction(ISD::GC_TRANSITION_END, MVT::Other, Custom);
514 if (!Subtarget->useSoftFloat() && X86ScalarSSEf64) {
515 // f32 and f64 use SSE.
516 // Set up the FP register classes.
517 addRegisterClass(MVT::f32, &X86::FR32RegClass);
518 addRegisterClass(MVT::f64, &X86::FR64RegClass);
520 // Use ANDPD to simulate FABS.
521 setOperationAction(ISD::FABS , MVT::f64, Custom);
522 setOperationAction(ISD::FABS , MVT::f32, Custom);
524 // Use XORP to simulate FNEG.
525 setOperationAction(ISD::FNEG , MVT::f64, Custom);
526 setOperationAction(ISD::FNEG , MVT::f32, Custom);
528 // Use ANDPD and ORPD to simulate FCOPYSIGN.
529 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
530 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
532 // Lower this to FGETSIGNx86 plus an AND.
533 setOperationAction(ISD::FGETSIGN, MVT::i64, Custom);
534 setOperationAction(ISD::FGETSIGN, MVT::i32, Custom);
536 // We don't support sin/cos/fmod
537 setOperationAction(ISD::FSIN , MVT::f64, Expand);
538 setOperationAction(ISD::FCOS , MVT::f64, Expand);
539 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
540 setOperationAction(ISD::FSIN , MVT::f32, Expand);
541 setOperationAction(ISD::FCOS , MVT::f32, Expand);
542 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
544 // Expand FP immediates into loads from the stack, except for the special
546 addLegalFPImmediate(APFloat(+0.0)); // xorpd
547 addLegalFPImmediate(APFloat(+0.0f)); // xorps
548 } else if (!Subtarget->useSoftFloat() && X86ScalarSSEf32) {
549 // Use SSE for f32, x87 for f64.
550 // Set up the FP register classes.
551 addRegisterClass(MVT::f32, &X86::FR32RegClass);
552 addRegisterClass(MVT::f64, &X86::RFP64RegClass);
554 // Use ANDPS to simulate FABS.
555 setOperationAction(ISD::FABS , MVT::f32, Custom);
557 // Use XORP to simulate FNEG.
558 setOperationAction(ISD::FNEG , MVT::f32, Custom);
560 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
562 // Use ANDPS and ORPS to simulate FCOPYSIGN.
563 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
564 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
566 // We don't support sin/cos/fmod
567 setOperationAction(ISD::FSIN , MVT::f32, Expand);
568 setOperationAction(ISD::FCOS , MVT::f32, Expand);
569 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
571 // Special cases we handle for FP constants.
572 addLegalFPImmediate(APFloat(+0.0f)); // xorps
573 addLegalFPImmediate(APFloat(+0.0)); // FLD0
574 addLegalFPImmediate(APFloat(+1.0)); // FLD1
575 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
576 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
578 if (!TM.Options.UnsafeFPMath) {
579 setOperationAction(ISD::FSIN , MVT::f64, Expand);
580 setOperationAction(ISD::FCOS , MVT::f64, Expand);
581 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
583 } else if (!Subtarget->useSoftFloat()) {
584 // f32 and f64 in x87.
585 // Set up the FP register classes.
586 addRegisterClass(MVT::f64, &X86::RFP64RegClass);
587 addRegisterClass(MVT::f32, &X86::RFP32RegClass);
589 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
590 setOperationAction(ISD::UNDEF, MVT::f32, Expand);
591 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
592 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
594 if (!TM.Options.UnsafeFPMath) {
595 setOperationAction(ISD::FSIN , MVT::f64, Expand);
596 setOperationAction(ISD::FSIN , MVT::f32, Expand);
597 setOperationAction(ISD::FCOS , MVT::f64, Expand);
598 setOperationAction(ISD::FCOS , MVT::f32, Expand);
599 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
600 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
602 addLegalFPImmediate(APFloat(+0.0)); // FLD0
603 addLegalFPImmediate(APFloat(+1.0)); // FLD1
604 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
605 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
606 addLegalFPImmediate(APFloat(+0.0f)); // FLD0
607 addLegalFPImmediate(APFloat(+1.0f)); // FLD1
608 addLegalFPImmediate(APFloat(-0.0f)); // FLD0/FCHS
609 addLegalFPImmediate(APFloat(-1.0f)); // FLD1/FCHS
612 // We don't support FMA.
613 setOperationAction(ISD::FMA, MVT::f64, Expand);
614 setOperationAction(ISD::FMA, MVT::f32, Expand);
616 // Long double always uses X87.
617 if (!Subtarget->useSoftFloat()) {
618 addRegisterClass(MVT::f80, &X86::RFP80RegClass);
619 setOperationAction(ISD::UNDEF, MVT::f80, Expand);
620 setOperationAction(ISD::FCOPYSIGN, MVT::f80, Expand);
622 APFloat TmpFlt = APFloat::getZero(APFloat::x87DoubleExtended);
623 addLegalFPImmediate(TmpFlt); // FLD0
625 addLegalFPImmediate(TmpFlt); // FLD0/FCHS
628 APFloat TmpFlt2(+1.0);
629 TmpFlt2.convert(APFloat::x87DoubleExtended, APFloat::rmNearestTiesToEven,
631 addLegalFPImmediate(TmpFlt2); // FLD1
632 TmpFlt2.changeSign();
633 addLegalFPImmediate(TmpFlt2); // FLD1/FCHS
636 if (!TM.Options.UnsafeFPMath) {
637 setOperationAction(ISD::FSIN , MVT::f80, Expand);
638 setOperationAction(ISD::FCOS , MVT::f80, Expand);
639 setOperationAction(ISD::FSINCOS, MVT::f80, Expand);
642 setOperationAction(ISD::FFLOOR, MVT::f80, Expand);
643 setOperationAction(ISD::FCEIL, MVT::f80, Expand);
644 setOperationAction(ISD::FTRUNC, MVT::f80, Expand);
645 setOperationAction(ISD::FRINT, MVT::f80, Expand);
646 setOperationAction(ISD::FNEARBYINT, MVT::f80, Expand);
647 setOperationAction(ISD::FMA, MVT::f80, Expand);
650 // Always use a library call for pow.
651 setOperationAction(ISD::FPOW , MVT::f32 , Expand);
652 setOperationAction(ISD::FPOW , MVT::f64 , Expand);
653 setOperationAction(ISD::FPOW , MVT::f80 , Expand);
655 setOperationAction(ISD::FLOG, MVT::f80, Expand);
656 setOperationAction(ISD::FLOG2, MVT::f80, Expand);
657 setOperationAction(ISD::FLOG10, MVT::f80, Expand);
658 setOperationAction(ISD::FEXP, MVT::f80, Expand);
659 setOperationAction(ISD::FEXP2, MVT::f80, Expand);
660 setOperationAction(ISD::FMINNUM, MVT::f80, Expand);
661 setOperationAction(ISD::FMAXNUM, MVT::f80, Expand);
663 // First set operation action for all vector types to either promote
664 // (for widening) or expand (for scalarization). Then we will selectively
665 // turn on ones that can be effectively codegen'd.
666 for (MVT VT : MVT::vector_valuetypes()) {
667 setOperationAction(ISD::ADD , VT, Expand);
668 setOperationAction(ISD::SUB , VT, Expand);
669 setOperationAction(ISD::FADD, VT, Expand);
670 setOperationAction(ISD::FNEG, VT, Expand);
671 setOperationAction(ISD::FSUB, VT, Expand);
672 setOperationAction(ISD::MUL , VT, Expand);
673 setOperationAction(ISD::FMUL, VT, Expand);
674 setOperationAction(ISD::SDIV, VT, Expand);
675 setOperationAction(ISD::UDIV, VT, Expand);
676 setOperationAction(ISD::FDIV, VT, Expand);
677 setOperationAction(ISD::SREM, VT, Expand);
678 setOperationAction(ISD::UREM, VT, Expand);
679 setOperationAction(ISD::LOAD, VT, Expand);
680 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Expand);
681 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT,Expand);
682 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Expand);
683 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT,Expand);
684 setOperationAction(ISD::INSERT_SUBVECTOR, VT,Expand);
685 setOperationAction(ISD::FABS, VT, Expand);
686 setOperationAction(ISD::FSIN, VT, Expand);
687 setOperationAction(ISD::FSINCOS, VT, Expand);
688 setOperationAction(ISD::FCOS, VT, Expand);
689 setOperationAction(ISD::FSINCOS, VT, Expand);
690 setOperationAction(ISD::FREM, VT, Expand);
691 setOperationAction(ISD::FMA, VT, Expand);
692 setOperationAction(ISD::FPOWI, VT, Expand);
693 setOperationAction(ISD::FSQRT, VT, Expand);
694 setOperationAction(ISD::FCOPYSIGN, VT, Expand);
695 setOperationAction(ISD::FFLOOR, VT, Expand);
696 setOperationAction(ISD::FCEIL, VT, Expand);
697 setOperationAction(ISD::FTRUNC, VT, Expand);
698 setOperationAction(ISD::FRINT, VT, Expand);
699 setOperationAction(ISD::FNEARBYINT, VT, Expand);
700 setOperationAction(ISD::SMUL_LOHI, VT, Expand);
701 setOperationAction(ISD::MULHS, VT, Expand);
702 setOperationAction(ISD::UMUL_LOHI, VT, Expand);
703 setOperationAction(ISD::MULHU, VT, Expand);
704 setOperationAction(ISD::SDIVREM, VT, Expand);
705 setOperationAction(ISD::UDIVREM, VT, Expand);
706 setOperationAction(ISD::FPOW, VT, Expand);
707 setOperationAction(ISD::CTPOP, VT, Expand);
708 setOperationAction(ISD::CTTZ, VT, Expand);
709 setOperationAction(ISD::CTTZ_ZERO_UNDEF, VT, Expand);
710 setOperationAction(ISD::CTLZ, VT, Expand);
711 setOperationAction(ISD::CTLZ_ZERO_UNDEF, VT, Expand);
712 setOperationAction(ISD::SHL, VT, Expand);
713 setOperationAction(ISD::SRA, VT, Expand);
714 setOperationAction(ISD::SRL, VT, Expand);
715 setOperationAction(ISD::ROTL, VT, Expand);
716 setOperationAction(ISD::ROTR, VT, Expand);
717 setOperationAction(ISD::BSWAP, VT, Expand);
718 setOperationAction(ISD::SETCC, VT, Expand);
719 setOperationAction(ISD::FLOG, VT, Expand);
720 setOperationAction(ISD::FLOG2, VT, Expand);
721 setOperationAction(ISD::FLOG10, VT, Expand);
722 setOperationAction(ISD::FEXP, VT, Expand);
723 setOperationAction(ISD::FEXP2, VT, Expand);
724 setOperationAction(ISD::FP_TO_UINT, VT, Expand);
725 setOperationAction(ISD::FP_TO_SINT, VT, Expand);
726 setOperationAction(ISD::UINT_TO_FP, VT, Expand);
727 setOperationAction(ISD::SINT_TO_FP, VT, Expand);
728 setOperationAction(ISD::SIGN_EXTEND_INREG, VT,Expand);
729 setOperationAction(ISD::TRUNCATE, VT, Expand);
730 setOperationAction(ISD::SIGN_EXTEND, VT, Expand);
731 setOperationAction(ISD::ZERO_EXTEND, VT, Expand);
732 setOperationAction(ISD::ANY_EXTEND, VT, Expand);
733 setOperationAction(ISD::VSELECT, VT, Expand);
734 setOperationAction(ISD::SELECT_CC, VT, Expand);
735 for (MVT InnerVT : MVT::vector_valuetypes()) {
736 setTruncStoreAction(InnerVT, VT, Expand);
738 setLoadExtAction(ISD::SEXTLOAD, InnerVT, VT, Expand);
739 setLoadExtAction(ISD::ZEXTLOAD, InnerVT, VT, Expand);
741 // N.b. ISD::EXTLOAD legality is basically ignored except for i1-like
742 // types, we have to deal with them whether we ask for Expansion or not.
743 // Setting Expand causes its own optimisation problems though, so leave
745 if (VT.getVectorElementType() == MVT::i1)
746 setLoadExtAction(ISD::EXTLOAD, InnerVT, VT, Expand);
748 // EXTLOAD for MVT::f16 vectors is not legal because f16 vectors are
749 // split/scalarized right now.
750 if (VT.getVectorElementType() == MVT::f16)
751 setLoadExtAction(ISD::EXTLOAD, InnerVT, VT, Expand);
755 // FIXME: In order to prevent SSE instructions being expanded to MMX ones
756 // with -msoft-float, disable use of MMX as well.
757 if (!Subtarget->useSoftFloat() && Subtarget->hasMMX()) {
758 addRegisterClass(MVT::x86mmx, &X86::VR64RegClass);
759 // No operations on x86mmx supported, everything uses intrinsics.
762 // MMX-sized vectors (other than x86mmx) are expected to be expanded
763 // into smaller operations.
764 for (MVT MMXTy : {MVT::v8i8, MVT::v4i16, MVT::v2i32, MVT::v1i64}) {
765 setOperationAction(ISD::MULHS, MMXTy, Expand);
766 setOperationAction(ISD::AND, MMXTy, Expand);
767 setOperationAction(ISD::OR, MMXTy, Expand);
768 setOperationAction(ISD::XOR, MMXTy, Expand);
769 setOperationAction(ISD::SCALAR_TO_VECTOR, MMXTy, Expand);
770 setOperationAction(ISD::SELECT, MMXTy, Expand);
771 setOperationAction(ISD::BITCAST, MMXTy, Expand);
773 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v1i64, Expand);
775 if (!Subtarget->useSoftFloat() && Subtarget->hasSSE1()) {
776 addRegisterClass(MVT::v4f32, &X86::VR128RegClass);
778 setOperationAction(ISD::FADD, MVT::v4f32, Legal);
779 setOperationAction(ISD::FSUB, MVT::v4f32, Legal);
780 setOperationAction(ISD::FMUL, MVT::v4f32, Legal);
781 setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
782 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal);
783 setOperationAction(ISD::FNEG, MVT::v4f32, Custom);
784 setOperationAction(ISD::FABS, MVT::v4f32, Custom);
785 setOperationAction(ISD::LOAD, MVT::v4f32, Legal);
786 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
787 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f32, Custom);
788 setOperationAction(ISD::VSELECT, MVT::v4f32, Custom);
789 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
790 setOperationAction(ISD::SELECT, MVT::v4f32, Custom);
791 setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Custom);
794 if (!Subtarget->useSoftFloat() && Subtarget->hasSSE2()) {
795 addRegisterClass(MVT::v2f64, &X86::VR128RegClass);
797 // FIXME: Unfortunately, -soft-float and -no-implicit-float mean XMM
798 // registers cannot be used even for integer operations.
799 addRegisterClass(MVT::v16i8, &X86::VR128RegClass);
800 addRegisterClass(MVT::v8i16, &X86::VR128RegClass);
801 addRegisterClass(MVT::v4i32, &X86::VR128RegClass);
802 addRegisterClass(MVT::v2i64, &X86::VR128RegClass);
804 setOperationAction(ISD::ADD, MVT::v16i8, Legal);
805 setOperationAction(ISD::ADD, MVT::v8i16, Legal);
806 setOperationAction(ISD::ADD, MVT::v4i32, Legal);
807 setOperationAction(ISD::ADD, MVT::v2i64, Legal);
808 setOperationAction(ISD::MUL, MVT::v16i8, Custom);
809 setOperationAction(ISD::MUL, MVT::v4i32, Custom);
810 setOperationAction(ISD::MUL, MVT::v2i64, Custom);
811 setOperationAction(ISD::UMUL_LOHI, MVT::v4i32, Custom);
812 setOperationAction(ISD::SMUL_LOHI, MVT::v4i32, Custom);
813 setOperationAction(ISD::MULHU, MVT::v8i16, Legal);
814 setOperationAction(ISD::MULHS, MVT::v8i16, Legal);
815 setOperationAction(ISD::SUB, MVT::v16i8, Legal);
816 setOperationAction(ISD::SUB, MVT::v8i16, Legal);
817 setOperationAction(ISD::SUB, MVT::v4i32, Legal);
818 setOperationAction(ISD::SUB, MVT::v2i64, Legal);
819 setOperationAction(ISD::MUL, MVT::v8i16, Legal);
820 setOperationAction(ISD::FADD, MVT::v2f64, Legal);
821 setOperationAction(ISD::FSUB, MVT::v2f64, Legal);
822 setOperationAction(ISD::FMUL, MVT::v2f64, Legal);
823 setOperationAction(ISD::FDIV, MVT::v2f64, Legal);
824 setOperationAction(ISD::FSQRT, MVT::v2f64, Legal);
825 setOperationAction(ISD::FNEG, MVT::v2f64, Custom);
826 setOperationAction(ISD::FABS, MVT::v2f64, Custom);
828 setOperationAction(ISD::SETCC, MVT::v2i64, Custom);
829 setOperationAction(ISD::SETCC, MVT::v16i8, Custom);
830 setOperationAction(ISD::SETCC, MVT::v8i16, Custom);
831 setOperationAction(ISD::SETCC, MVT::v4i32, Custom);
833 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Custom);
834 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Custom);
835 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
836 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
837 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
839 setOperationAction(ISD::CTPOP, MVT::v16i8, Custom);
840 setOperationAction(ISD::CTPOP, MVT::v8i16, Custom);
841 setOperationAction(ISD::CTPOP, MVT::v4i32, Custom);
842 setOperationAction(ISD::CTPOP, MVT::v2i64, Custom);
844 // Custom lower build_vector, vector_shuffle, and extract_vector_elt.
845 for (int i = MVT::v16i8; i != MVT::v2i64; ++i) {
846 MVT VT = (MVT::SimpleValueType)i;
847 // Do not attempt to custom lower non-power-of-2 vectors
848 if (!isPowerOf2_32(VT.getVectorNumElements()))
850 // Do not attempt to custom lower non-128-bit vectors
851 if (!VT.is128BitVector())
853 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
854 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
855 setOperationAction(ISD::VSELECT, VT, Custom);
856 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
859 // We support custom legalizing of sext and anyext loads for specific
860 // memory vector types which we can load as a scalar (or sequence of
861 // scalars) and extend in-register to a legal 128-bit vector type. For sext
862 // loads these must work with a single scalar load.
863 for (MVT VT : MVT::integer_vector_valuetypes()) {
864 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v4i8, Custom);
865 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v4i16, Custom);
866 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v8i8, Custom);
867 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v2i8, Custom);
868 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v2i16, Custom);
869 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v2i32, Custom);
870 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v4i8, Custom);
871 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v4i16, Custom);
872 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v8i8, Custom);
875 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f64, Custom);
876 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i64, Custom);
877 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Custom);
878 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Custom);
879 setOperationAction(ISD::VSELECT, MVT::v2f64, Custom);
880 setOperationAction(ISD::VSELECT, MVT::v2i64, Custom);
881 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f64, Custom);
882 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Custom);
884 if (Subtarget->is64Bit()) {
885 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
886 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
889 // Promote v16i8, v8i16, v4i32 load, select, and, or, xor to v2i64.
890 for (int i = MVT::v16i8; i != MVT::v2i64; ++i) {
891 MVT VT = (MVT::SimpleValueType)i;
893 // Do not attempt to promote non-128-bit vectors
894 if (!VT.is128BitVector())
897 setOperationAction(ISD::AND, VT, Promote);
898 AddPromotedToType (ISD::AND, VT, MVT::v2i64);
899 setOperationAction(ISD::OR, VT, Promote);
900 AddPromotedToType (ISD::OR, VT, MVT::v2i64);
901 setOperationAction(ISD::XOR, VT, Promote);
902 AddPromotedToType (ISD::XOR, VT, MVT::v2i64);
903 setOperationAction(ISD::LOAD, VT, Promote);
904 AddPromotedToType (ISD::LOAD, VT, MVT::v2i64);
905 setOperationAction(ISD::SELECT, VT, Promote);
906 AddPromotedToType (ISD::SELECT, VT, MVT::v2i64);
909 // Custom lower v2i64 and v2f64 selects.
910 setOperationAction(ISD::LOAD, MVT::v2f64, Legal);
911 setOperationAction(ISD::LOAD, MVT::v2i64, Legal);
912 setOperationAction(ISD::SELECT, MVT::v2f64, Custom);
913 setOperationAction(ISD::SELECT, MVT::v2i64, Custom);
915 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal);
916 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal);
918 setOperationAction(ISD::UINT_TO_FP, MVT::v4i8, Custom);
919 setOperationAction(ISD::UINT_TO_FP, MVT::v4i16, Custom);
920 // As there is no 64-bit GPR available, we need build a special custom
921 // sequence to convert from v2i32 to v2f32.
922 if (!Subtarget->is64Bit())
923 setOperationAction(ISD::UINT_TO_FP, MVT::v2f32, Custom);
925 setOperationAction(ISD::FP_EXTEND, MVT::v2f32, Custom);
926 setOperationAction(ISD::FP_ROUND, MVT::v2f32, Custom);
928 for (MVT VT : MVT::fp_vector_valuetypes())
929 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v2f32, Legal);
931 setOperationAction(ISD::BITCAST, MVT::v2i32, Custom);
932 setOperationAction(ISD::BITCAST, MVT::v4i16, Custom);
933 setOperationAction(ISD::BITCAST, MVT::v8i8, Custom);
936 if (!Subtarget->useSoftFloat() && Subtarget->hasSSE41()) {
937 for (MVT RoundedTy : {MVT::f32, MVT::f64, MVT::v4f32, MVT::v2f64}) {
938 setOperationAction(ISD::FFLOOR, RoundedTy, Legal);
939 setOperationAction(ISD::FCEIL, RoundedTy, Legal);
940 setOperationAction(ISD::FTRUNC, RoundedTy, Legal);
941 setOperationAction(ISD::FRINT, RoundedTy, Legal);
942 setOperationAction(ISD::FNEARBYINT, RoundedTy, Legal);
945 // FIXME: Do we need to handle scalar-to-vector here?
946 setOperationAction(ISD::MUL, MVT::v4i32, Legal);
948 // We directly match byte blends in the backend as they match the VSELECT
950 setOperationAction(ISD::VSELECT, MVT::v16i8, Legal);
952 // SSE41 brings specific instructions for doing vector sign extend even in
953 // cases where we don't have SRA.
954 for (MVT VT : MVT::integer_vector_valuetypes()) {
955 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v2i8, Custom);
956 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v2i16, Custom);
957 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v2i32, Custom);
960 // SSE41 also has vector sign/zero extending loads, PMOV[SZ]X
961 setLoadExtAction(ISD::SEXTLOAD, MVT::v8i16, MVT::v8i8, Legal);
962 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i32, MVT::v4i8, Legal);
963 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i64, MVT::v2i8, Legal);
964 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i32, MVT::v4i16, Legal);
965 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i64, MVT::v2i16, Legal);
966 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i64, MVT::v2i32, Legal);
968 setLoadExtAction(ISD::ZEXTLOAD, MVT::v8i16, MVT::v8i8, Legal);
969 setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i32, MVT::v4i8, Legal);
970 setLoadExtAction(ISD::ZEXTLOAD, MVT::v2i64, MVT::v2i8, Legal);
971 setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i32, MVT::v4i16, Legal);
972 setLoadExtAction(ISD::ZEXTLOAD, MVT::v2i64, MVT::v2i16, Legal);
973 setLoadExtAction(ISD::ZEXTLOAD, MVT::v2i64, MVT::v2i32, Legal);
975 // i8 and i16 vectors are custom because the source register and source
976 // source memory operand types are not the same width. f32 vectors are
977 // custom since the immediate controlling the insert encodes additional
979 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i8, Custom);
980 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
981 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
982 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
984 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i8, Custom);
985 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i16, Custom);
986 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i32, Custom);
987 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
989 // FIXME: these should be Legal, but that's only for the case where
990 // the index is constant. For now custom expand to deal with that.
991 if (Subtarget->is64Bit()) {
992 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
993 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
997 if (Subtarget->hasSSE2()) {
998 setOperationAction(ISD::SIGN_EXTEND_VECTOR_INREG, MVT::v2i64, Custom);
999 setOperationAction(ISD::SIGN_EXTEND_VECTOR_INREG, MVT::v4i32, Custom);
1000 setOperationAction(ISD::SIGN_EXTEND_VECTOR_INREG, MVT::v8i16, Custom);
1002 setOperationAction(ISD::SRL, MVT::v8i16, Custom);
1003 setOperationAction(ISD::SRL, MVT::v16i8, Custom);
1005 setOperationAction(ISD::SHL, MVT::v8i16, Custom);
1006 setOperationAction(ISD::SHL, MVT::v16i8, Custom);
1008 setOperationAction(ISD::SRA, MVT::v8i16, Custom);
1009 setOperationAction(ISD::SRA, MVT::v16i8, Custom);
1011 // In the customized shift lowering, the legal cases in AVX2 will be
1013 setOperationAction(ISD::SRL, MVT::v2i64, Custom);
1014 setOperationAction(ISD::SRL, MVT::v4i32, Custom);
1016 setOperationAction(ISD::SHL, MVT::v2i64, Custom);
1017 setOperationAction(ISD::SHL, MVT::v4i32, Custom);
1019 setOperationAction(ISD::SRA, MVT::v4i32, Custom);
1022 if (!Subtarget->useSoftFloat() && Subtarget->hasFp256()) {
1023 addRegisterClass(MVT::v32i8, &X86::VR256RegClass);
1024 addRegisterClass(MVT::v16i16, &X86::VR256RegClass);
1025 addRegisterClass(MVT::v8i32, &X86::VR256RegClass);
1026 addRegisterClass(MVT::v8f32, &X86::VR256RegClass);
1027 addRegisterClass(MVT::v4i64, &X86::VR256RegClass);
1028 addRegisterClass(MVT::v4f64, &X86::VR256RegClass);
1030 setOperationAction(ISD::LOAD, MVT::v8f32, Legal);
1031 setOperationAction(ISD::LOAD, MVT::v4f64, Legal);
1032 setOperationAction(ISD::LOAD, MVT::v4i64, Legal);
1034 setOperationAction(ISD::FADD, MVT::v8f32, Legal);
1035 setOperationAction(ISD::FSUB, MVT::v8f32, Legal);
1036 setOperationAction(ISD::FMUL, MVT::v8f32, Legal);
1037 setOperationAction(ISD::FDIV, MVT::v8f32, Legal);
1038 setOperationAction(ISD::FSQRT, MVT::v8f32, Legal);
1039 setOperationAction(ISD::FFLOOR, MVT::v8f32, Legal);
1040 setOperationAction(ISD::FCEIL, MVT::v8f32, Legal);
1041 setOperationAction(ISD::FTRUNC, MVT::v8f32, Legal);
1042 setOperationAction(ISD::FRINT, MVT::v8f32, Legal);
1043 setOperationAction(ISD::FNEARBYINT, MVT::v8f32, Legal);
1044 setOperationAction(ISD::FNEG, MVT::v8f32, Custom);
1045 setOperationAction(ISD::FABS, MVT::v8f32, Custom);
1047 setOperationAction(ISD::FADD, MVT::v4f64, Legal);
1048 setOperationAction(ISD::FSUB, MVT::v4f64, Legal);
1049 setOperationAction(ISD::FMUL, MVT::v4f64, Legal);
1050 setOperationAction(ISD::FDIV, MVT::v4f64, Legal);
1051 setOperationAction(ISD::FSQRT, MVT::v4f64, Legal);
1052 setOperationAction(ISD::FFLOOR, MVT::v4f64, Legal);
1053 setOperationAction(ISD::FCEIL, MVT::v4f64, Legal);
1054 setOperationAction(ISD::FTRUNC, MVT::v4f64, Legal);
1055 setOperationAction(ISD::FRINT, MVT::v4f64, Legal);
1056 setOperationAction(ISD::FNEARBYINT, MVT::v4f64, Legal);
1057 setOperationAction(ISD::FNEG, MVT::v4f64, Custom);
1058 setOperationAction(ISD::FABS, MVT::v4f64, Custom);
1060 // (fp_to_int:v8i16 (v8f32 ..)) requires the result type to be promoted
1061 // even though v8i16 is a legal type.
1062 setOperationAction(ISD::FP_TO_SINT, MVT::v8i16, Promote);
1063 setOperationAction(ISD::FP_TO_UINT, MVT::v8i16, Promote);
1064 setOperationAction(ISD::FP_TO_SINT, MVT::v8i32, Legal);
1066 setOperationAction(ISD::SINT_TO_FP, MVT::v8i16, Promote);
1067 setOperationAction(ISD::SINT_TO_FP, MVT::v8i32, Legal);
1068 setOperationAction(ISD::FP_ROUND, MVT::v4f32, Legal);
1070 setOperationAction(ISD::UINT_TO_FP, MVT::v8i8, Custom);
1071 setOperationAction(ISD::UINT_TO_FP, MVT::v8i16, Custom);
1073 for (MVT VT : MVT::fp_vector_valuetypes())
1074 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v4f32, Legal);
1076 setOperationAction(ISD::SRL, MVT::v16i16, Custom);
1077 setOperationAction(ISD::SRL, MVT::v32i8, Custom);
1079 setOperationAction(ISD::SHL, MVT::v16i16, Custom);
1080 setOperationAction(ISD::SHL, MVT::v32i8, Custom);
1082 setOperationAction(ISD::SRA, MVT::v16i16, Custom);
1083 setOperationAction(ISD::SRA, MVT::v32i8, Custom);
1085 setOperationAction(ISD::SETCC, MVT::v32i8, Custom);
1086 setOperationAction(ISD::SETCC, MVT::v16i16, Custom);
1087 setOperationAction(ISD::SETCC, MVT::v8i32, Custom);
1088 setOperationAction(ISD::SETCC, MVT::v4i64, Custom);
1090 setOperationAction(ISD::SELECT, MVT::v4f64, Custom);
1091 setOperationAction(ISD::SELECT, MVT::v4i64, Custom);
1092 setOperationAction(ISD::SELECT, MVT::v8f32, Custom);
1094 setOperationAction(ISD::SIGN_EXTEND, MVT::v4i64, Custom);
1095 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i32, Custom);
1096 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i16, Custom);
1097 setOperationAction(ISD::ZERO_EXTEND, MVT::v4i64, Custom);
1098 setOperationAction(ISD::ZERO_EXTEND, MVT::v8i32, Custom);
1099 setOperationAction(ISD::ZERO_EXTEND, MVT::v16i16, Custom);
1100 setOperationAction(ISD::ANY_EXTEND, MVT::v4i64, Custom);
1101 setOperationAction(ISD::ANY_EXTEND, MVT::v8i32, Custom);
1102 setOperationAction(ISD::ANY_EXTEND, MVT::v16i16, Custom);
1103 setOperationAction(ISD::TRUNCATE, MVT::v16i8, Custom);
1104 setOperationAction(ISD::TRUNCATE, MVT::v8i16, Custom);
1105 setOperationAction(ISD::TRUNCATE, MVT::v4i32, Custom);
1107 setOperationAction(ISD::CTPOP, MVT::v32i8, Custom);
1108 setOperationAction(ISD::CTPOP, MVT::v16i16, Custom);
1109 setOperationAction(ISD::CTPOP, MVT::v8i32, Custom);
1110 setOperationAction(ISD::CTPOP, MVT::v4i64, Custom);
1112 if (Subtarget->hasFMA() || Subtarget->hasFMA4()) {
1113 setOperationAction(ISD::FMA, MVT::v8f32, Legal);
1114 setOperationAction(ISD::FMA, MVT::v4f64, Legal);
1115 setOperationAction(ISD::FMA, MVT::v4f32, Legal);
1116 setOperationAction(ISD::FMA, MVT::v2f64, Legal);
1117 setOperationAction(ISD::FMA, MVT::f32, Legal);
1118 setOperationAction(ISD::FMA, MVT::f64, Legal);
1121 if (Subtarget->hasInt256()) {
1122 setOperationAction(ISD::ADD, MVT::v4i64, Legal);
1123 setOperationAction(ISD::ADD, MVT::v8i32, Legal);
1124 setOperationAction(ISD::ADD, MVT::v16i16, Legal);
1125 setOperationAction(ISD::ADD, MVT::v32i8, Legal);
1127 setOperationAction(ISD::SUB, MVT::v4i64, Legal);
1128 setOperationAction(ISD::SUB, MVT::v8i32, Legal);
1129 setOperationAction(ISD::SUB, MVT::v16i16, Legal);
1130 setOperationAction(ISD::SUB, MVT::v32i8, Legal);
1132 setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1133 setOperationAction(ISD::MUL, MVT::v8i32, Legal);
1134 setOperationAction(ISD::MUL, MVT::v16i16, Legal);
1135 setOperationAction(ISD::MUL, MVT::v32i8, Custom);
1137 setOperationAction(ISD::UMUL_LOHI, MVT::v8i32, Custom);
1138 setOperationAction(ISD::SMUL_LOHI, MVT::v8i32, Custom);
1139 setOperationAction(ISD::MULHU, MVT::v16i16, Legal);
1140 setOperationAction(ISD::MULHS, MVT::v16i16, Legal);
1142 // The custom lowering for UINT_TO_FP for v8i32 becomes interesting
1143 // when we have a 256bit-wide blend with immediate.
1144 setOperationAction(ISD::UINT_TO_FP, MVT::v8i32, Custom);
1146 // AVX2 also has wider vector sign/zero extending loads, VPMOV[SZ]X
1147 setLoadExtAction(ISD::SEXTLOAD, MVT::v16i16, MVT::v16i8, Legal);
1148 setLoadExtAction(ISD::SEXTLOAD, MVT::v8i32, MVT::v8i8, Legal);
1149 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i64, MVT::v4i8, Legal);
1150 setLoadExtAction(ISD::SEXTLOAD, MVT::v8i32, MVT::v8i16, Legal);
1151 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i64, MVT::v4i16, Legal);
1152 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i64, MVT::v4i32, Legal);
1154 setLoadExtAction(ISD::ZEXTLOAD, MVT::v16i16, MVT::v16i8, Legal);
1155 setLoadExtAction(ISD::ZEXTLOAD, MVT::v8i32, MVT::v8i8, Legal);
1156 setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i64, MVT::v4i8, Legal);
1157 setLoadExtAction(ISD::ZEXTLOAD, MVT::v8i32, MVT::v8i16, Legal);
1158 setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i64, MVT::v4i16, Legal);
1159 setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i64, MVT::v4i32, Legal);
1161 setOperationAction(ISD::ADD, MVT::v4i64, Custom);
1162 setOperationAction(ISD::ADD, MVT::v8i32, Custom);
1163 setOperationAction(ISD::ADD, MVT::v16i16, Custom);
1164 setOperationAction(ISD::ADD, MVT::v32i8, Custom);
1166 setOperationAction(ISD::SUB, MVT::v4i64, Custom);
1167 setOperationAction(ISD::SUB, MVT::v8i32, Custom);
1168 setOperationAction(ISD::SUB, MVT::v16i16, Custom);
1169 setOperationAction(ISD::SUB, MVT::v32i8, Custom);
1171 setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1172 setOperationAction(ISD::MUL, MVT::v8i32, Custom);
1173 setOperationAction(ISD::MUL, MVT::v16i16, Custom);
1174 setOperationAction(ISD::MUL, MVT::v32i8, Custom);
1177 // In the customized shift lowering, the legal cases in AVX2 will be
1179 setOperationAction(ISD::SRL, MVT::v4i64, Custom);
1180 setOperationAction(ISD::SRL, MVT::v8i32, Custom);
1182 setOperationAction(ISD::SHL, MVT::v4i64, Custom);
1183 setOperationAction(ISD::SHL, MVT::v8i32, Custom);
1185 setOperationAction(ISD::SRA, MVT::v8i32, Custom);
1187 // Custom lower several nodes for 256-bit types.
1188 for (MVT VT : MVT::vector_valuetypes()) {
1189 if (VT.getScalarSizeInBits() >= 32) {
1190 setOperationAction(ISD::MLOAD, VT, Legal);
1191 setOperationAction(ISD::MSTORE, VT, Legal);
1193 // Extract subvector is special because the value type
1194 // (result) is 128-bit but the source is 256-bit wide.
1195 if (VT.is128BitVector()) {
1196 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom);
1198 // Do not attempt to custom lower other non-256-bit vectors
1199 if (!VT.is256BitVector())
1202 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1203 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1204 setOperationAction(ISD::VSELECT, VT, Custom);
1205 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
1206 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1207 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom);
1208 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom);
1209 setOperationAction(ISD::CONCAT_VECTORS, VT, Custom);
1212 if (Subtarget->hasInt256())
1213 setOperationAction(ISD::VSELECT, MVT::v32i8, Legal);
1216 // Promote v32i8, v16i16, v8i32 select, and, or, xor to v4i64.
1217 for (int i = MVT::v32i8; i != MVT::v4i64; ++i) {
1218 MVT VT = (MVT::SimpleValueType)i;
1220 // Do not attempt to promote non-256-bit vectors
1221 if (!VT.is256BitVector())
1224 setOperationAction(ISD::AND, VT, Promote);
1225 AddPromotedToType (ISD::AND, VT, MVT::v4i64);
1226 setOperationAction(ISD::OR, VT, Promote);
1227 AddPromotedToType (ISD::OR, VT, MVT::v4i64);
1228 setOperationAction(ISD::XOR, VT, Promote);
1229 AddPromotedToType (ISD::XOR, VT, MVT::v4i64);
1230 setOperationAction(ISD::LOAD, VT, Promote);
1231 AddPromotedToType (ISD::LOAD, VT, MVT::v4i64);
1232 setOperationAction(ISD::SELECT, VT, Promote);
1233 AddPromotedToType (ISD::SELECT, VT, MVT::v4i64);
1237 if (!Subtarget->useSoftFloat() && Subtarget->hasAVX512()) {
1238 addRegisterClass(MVT::v16i32, &X86::VR512RegClass);
1239 addRegisterClass(MVT::v16f32, &X86::VR512RegClass);
1240 addRegisterClass(MVT::v8i64, &X86::VR512RegClass);
1241 addRegisterClass(MVT::v8f64, &X86::VR512RegClass);
1243 addRegisterClass(MVT::i1, &X86::VK1RegClass);
1244 addRegisterClass(MVT::v8i1, &X86::VK8RegClass);
1245 addRegisterClass(MVT::v16i1, &X86::VK16RegClass);
1247 for (MVT VT : MVT::fp_vector_valuetypes())
1248 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v8f32, Legal);
1250 setLoadExtAction(ISD::ZEXTLOAD, MVT::v16i32, MVT::v16i8, Legal);
1251 setLoadExtAction(ISD::SEXTLOAD, MVT::v16i32, MVT::v16i8, Legal);
1252 setLoadExtAction(ISD::ZEXTLOAD, MVT::v16i32, MVT::v16i16, Legal);
1253 setLoadExtAction(ISD::SEXTLOAD, MVT::v16i32, MVT::v16i16, Legal);
1254 setLoadExtAction(ISD::ZEXTLOAD, MVT::v32i16, MVT::v32i8, Legal);
1255 setLoadExtAction(ISD::SEXTLOAD, MVT::v32i16, MVT::v32i8, Legal);
1256 setLoadExtAction(ISD::ZEXTLOAD, MVT::v8i64, MVT::v8i8, Legal);
1257 setLoadExtAction(ISD::SEXTLOAD, MVT::v8i64, MVT::v8i8, Legal);
1258 setLoadExtAction(ISD::ZEXTLOAD, MVT::v8i64, MVT::v8i16, Legal);
1259 setLoadExtAction(ISD::SEXTLOAD, MVT::v8i64, MVT::v8i16, Legal);
1260 setLoadExtAction(ISD::ZEXTLOAD, MVT::v8i64, MVT::v8i32, Legal);
1261 setLoadExtAction(ISD::SEXTLOAD, MVT::v8i64, MVT::v8i32, Legal);
1263 setOperationAction(ISD::BR_CC, MVT::i1, Expand);
1264 setOperationAction(ISD::SETCC, MVT::i1, Custom);
1265 setOperationAction(ISD::XOR, MVT::i1, Legal);
1266 setOperationAction(ISD::OR, MVT::i1, Legal);
1267 setOperationAction(ISD::AND, MVT::i1, Legal);
1268 setOperationAction(ISD::SUB, MVT::i1, Custom);
1269 setOperationAction(ISD::ADD, MVT::i1, Custom);
1270 setOperationAction(ISD::MUL, MVT::i1, Custom);
1271 setOperationAction(ISD::LOAD, MVT::v16f32, Legal);
1272 setOperationAction(ISD::LOAD, MVT::v8f64, Legal);
1273 setOperationAction(ISD::LOAD, MVT::v8i64, Legal);
1274 setOperationAction(ISD::LOAD, MVT::v16i32, Legal);
1275 setOperationAction(ISD::LOAD, MVT::v16i1, Legal);
1277 setOperationAction(ISD::FADD, MVT::v16f32, Legal);
1278 setOperationAction(ISD::FSUB, MVT::v16f32, Legal);
1279 setOperationAction(ISD::FMUL, MVT::v16f32, Legal);
1280 setOperationAction(ISD::FDIV, MVT::v16f32, Legal);
1281 setOperationAction(ISD::FSQRT, MVT::v16f32, Legal);
1282 setOperationAction(ISD::FNEG, MVT::v16f32, Custom);
1284 setOperationAction(ISD::FADD, MVT::v8f64, Legal);
1285 setOperationAction(ISD::FSUB, MVT::v8f64, Legal);
1286 setOperationAction(ISD::FMUL, MVT::v8f64, Legal);
1287 setOperationAction(ISD::FDIV, MVT::v8f64, Legal);
1288 setOperationAction(ISD::FSQRT, MVT::v8f64, Legal);
1289 setOperationAction(ISD::FNEG, MVT::v8f64, Custom);
1290 setOperationAction(ISD::FMA, MVT::v8f64, Legal);
1291 setOperationAction(ISD::FMA, MVT::v16f32, Legal);
1293 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Legal);
1294 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Legal);
1295 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Legal);
1296 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Legal);
1297 if (Subtarget->is64Bit()) {
1298 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Legal);
1299 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Legal);
1300 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Legal);
1301 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Legal);
1303 setOperationAction(ISD::FP_TO_SINT, MVT::v16i32, Legal);
1304 setOperationAction(ISD::FP_TO_UINT, MVT::v16i32, Legal);
1305 setOperationAction(ISD::FP_TO_UINT, MVT::v8i32, Legal);
1306 setOperationAction(ISD::FP_TO_UINT, MVT::v4i32, Legal);
1307 setOperationAction(ISD::SINT_TO_FP, MVT::v16i32, Legal);
1308 setOperationAction(ISD::SINT_TO_FP, MVT::v8i1, Custom);
1309 setOperationAction(ISD::SINT_TO_FP, MVT::v16i1, Custom);
1310 setOperationAction(ISD::SINT_TO_FP, MVT::v16i8, Promote);
1311 setOperationAction(ISD::SINT_TO_FP, MVT::v16i16, Promote);
1312 setOperationAction(ISD::UINT_TO_FP, MVT::v16i32, Legal);
1313 setOperationAction(ISD::UINT_TO_FP, MVT::v8i32, Legal);
1314 setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Legal);
1315 setOperationAction(ISD::UINT_TO_FP, MVT::v16i8, Custom);
1316 setOperationAction(ISD::UINT_TO_FP, MVT::v16i16, Custom);
1317 setOperationAction(ISD::FP_ROUND, MVT::v8f32, Legal);
1318 setOperationAction(ISD::FP_EXTEND, MVT::v8f32, Legal);
1320 setOperationAction(ISD::TRUNCATE, MVT::i1, Custom);
1321 setOperationAction(ISD::TRUNCATE, MVT::v16i8, Custom);
1322 setOperationAction(ISD::TRUNCATE, MVT::v8i32, Custom);
1323 if (Subtarget->hasDQI()) {
1324 setOperationAction(ISD::TRUNCATE, MVT::v2i1, Custom);
1325 setOperationAction(ISD::TRUNCATE, MVT::v4i1, Custom);
1327 setOperationAction(ISD::TRUNCATE, MVT::v8i1, Custom);
1328 setOperationAction(ISD::TRUNCATE, MVT::v16i1, Custom);
1329 setOperationAction(ISD::TRUNCATE, MVT::v16i16, Custom);
1330 setOperationAction(ISD::ZERO_EXTEND, MVT::v16i32, Custom);
1331 setOperationAction(ISD::ZERO_EXTEND, MVT::v8i64, Custom);
1332 setOperationAction(ISD::ANY_EXTEND, MVT::v16i32, Custom);
1333 setOperationAction(ISD::ANY_EXTEND, MVT::v8i64, Custom);
1334 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i32, Custom);
1335 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i64, Custom);
1336 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i8, Custom);
1337 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i16, Custom);
1338 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i16, Custom);
1339 if (Subtarget->hasDQI()) {
1340 setOperationAction(ISD::SIGN_EXTEND, MVT::v4i32, Custom);
1341 setOperationAction(ISD::SIGN_EXTEND, MVT::v2i64, Custom);
1343 setOperationAction(ISD::FFLOOR, MVT::v16f32, Legal);
1344 setOperationAction(ISD::FFLOOR, MVT::v8f64, Legal);
1345 setOperationAction(ISD::FCEIL, MVT::v16f32, Legal);
1346 setOperationAction(ISD::FCEIL, MVT::v8f64, Legal);
1347 setOperationAction(ISD::FTRUNC, MVT::v16f32, Legal);
1348 setOperationAction(ISD::FTRUNC, MVT::v8f64, Legal);
1349 setOperationAction(ISD::FRINT, MVT::v16f32, Legal);
1350 setOperationAction(ISD::FRINT, MVT::v8f64, Legal);
1351 setOperationAction(ISD::FNEARBYINT, MVT::v16f32, Legal);
1352 setOperationAction(ISD::FNEARBYINT, MVT::v8f64, Legal);
1354 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8f64, Custom);
1355 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i64, Custom);
1356 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16f32, Custom);
1357 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i32, Custom);
1358 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i1, Legal);
1360 setOperationAction(ISD::SETCC, MVT::v16i1, Custom);
1361 setOperationAction(ISD::SETCC, MVT::v8i1, Custom);
1363 setOperationAction(ISD::MUL, MVT::v8i64, Custom);
1365 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i1, Custom);
1366 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i1, Custom);
1367 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i1, Custom);
1368 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i1, Custom);
1369 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i1, Custom);
1370 setOperationAction(ISD::BUILD_VECTOR, MVT::v16i1, Custom);
1371 setOperationAction(ISD::SELECT, MVT::v8f64, Custom);
1372 setOperationAction(ISD::SELECT, MVT::v8i64, Custom);
1373 setOperationAction(ISD::SELECT, MVT::v16f32, Custom);
1374 setOperationAction(ISD::SELECT, MVT::v16i1, Custom);
1375 setOperationAction(ISD::SELECT, MVT::v8i1, Custom);
1377 setOperationAction(ISD::ADD, MVT::v8i64, Legal);
1378 setOperationAction(ISD::ADD, MVT::v16i32, Legal);
1380 setOperationAction(ISD::SUB, MVT::v8i64, Legal);
1381 setOperationAction(ISD::SUB, MVT::v16i32, Legal);
1383 setOperationAction(ISD::MUL, MVT::v16i32, Legal);
1385 setOperationAction(ISD::SRL, MVT::v8i64, Custom);
1386 setOperationAction(ISD::SRL, MVT::v16i32, Custom);
1388 setOperationAction(ISD::SHL, MVT::v8i64, Custom);
1389 setOperationAction(ISD::SHL, MVT::v16i32, Custom);
1391 setOperationAction(ISD::SRA, MVT::v8i64, Custom);
1392 setOperationAction(ISD::SRA, MVT::v16i32, Custom);
1394 setOperationAction(ISD::AND, MVT::v8i64, Legal);
1395 setOperationAction(ISD::OR, MVT::v8i64, Legal);
1396 setOperationAction(ISD::XOR, MVT::v8i64, Legal);
1397 setOperationAction(ISD::AND, MVT::v16i32, Legal);
1398 setOperationAction(ISD::OR, MVT::v16i32, Legal);
1399 setOperationAction(ISD::XOR, MVT::v16i32, Legal);
1401 if (Subtarget->hasCDI()) {
1402 setOperationAction(ISD::CTLZ, MVT::v8i64, Legal);
1403 setOperationAction(ISD::CTLZ, MVT::v16i32, Legal);
1405 if (Subtarget->hasDQI()) {
1406 setOperationAction(ISD::MUL, MVT::v2i64, Legal);
1407 setOperationAction(ISD::MUL, MVT::v4i64, Legal);
1408 setOperationAction(ISD::MUL, MVT::v8i64, Legal);
1410 // Custom lower several nodes.
1411 for (MVT VT : MVT::vector_valuetypes()) {
1412 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
1414 setOperationAction(ISD::AND, VT, Legal);
1415 setOperationAction(ISD::OR, VT, Legal);
1416 setOperationAction(ISD::XOR, VT, Legal);
1418 if (EltSize >= 32 && VT.getSizeInBits() <= 512) {
1419 setOperationAction(ISD::MGATHER, VT, Custom);
1420 setOperationAction(ISD::MSCATTER, VT, Custom);
1422 // Extract subvector is special because the value type
1423 // (result) is 256/128-bit but the source is 512-bit wide.
1424 if (VT.is128BitVector() || VT.is256BitVector()) {
1425 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom);
1427 if (VT.getVectorElementType() == MVT::i1)
1428 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Legal);
1430 // Do not attempt to custom lower other non-512-bit vectors
1431 if (!VT.is512BitVector())
1434 if (EltSize >= 32) {
1435 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1436 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
1437 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1438 setOperationAction(ISD::VSELECT, VT, Legal);
1439 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1440 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom);
1441 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom);
1442 setOperationAction(ISD::MLOAD, VT, Legal);
1443 setOperationAction(ISD::MSTORE, VT, Legal);
1446 for (int i = MVT::v32i8; i != MVT::v8i64; ++i) {
1447 MVT VT = (MVT::SimpleValueType)i;
1449 // Do not attempt to promote non-512-bit vectors.
1450 if (!VT.is512BitVector())
1453 setOperationAction(ISD::SELECT, VT, Promote);
1454 AddPromotedToType (ISD::SELECT, VT, MVT::v8i64);
1458 if (!Subtarget->useSoftFloat() && Subtarget->hasBWI()) {
1459 addRegisterClass(MVT::v32i16, &X86::VR512RegClass);
1460 addRegisterClass(MVT::v64i8, &X86::VR512RegClass);
1462 addRegisterClass(MVT::v32i1, &X86::VK32RegClass);
1463 addRegisterClass(MVT::v64i1, &X86::VK64RegClass);
1465 setOperationAction(ISD::LOAD, MVT::v32i16, Legal);
1466 setOperationAction(ISD::LOAD, MVT::v64i8, Legal);
1467 setOperationAction(ISD::SETCC, MVT::v32i1, Custom);
1468 setOperationAction(ISD::SETCC, MVT::v64i1, Custom);
1469 setOperationAction(ISD::ADD, MVT::v32i16, Legal);
1470 setOperationAction(ISD::ADD, MVT::v64i8, Legal);
1471 setOperationAction(ISD::SUB, MVT::v32i16, Legal);
1472 setOperationAction(ISD::SUB, MVT::v64i8, Legal);
1473 setOperationAction(ISD::MUL, MVT::v32i16, Legal);
1474 setOperationAction(ISD::CONCAT_VECTORS, MVT::v32i1, Custom);
1475 setOperationAction(ISD::CONCAT_VECTORS, MVT::v64i1, Custom);
1476 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v32i1, Custom);
1477 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v64i1, Custom);
1478 setOperationAction(ISD::SELECT, MVT::v32i1, Custom);
1479 setOperationAction(ISD::SELECT, MVT::v64i1, Custom);
1480 setOperationAction(ISD::SIGN_EXTEND, MVT::v32i8, Custom);
1481 setOperationAction(ISD::ZERO_EXTEND, MVT::v32i8, Custom);
1482 setOperationAction(ISD::SIGN_EXTEND, MVT::v32i16, Custom);
1483 setOperationAction(ISD::ZERO_EXTEND, MVT::v32i16, Custom);
1484 setOperationAction(ISD::SIGN_EXTEND, MVT::v64i8, Custom);
1485 setOperationAction(ISD::ZERO_EXTEND, MVT::v64i8, Custom);
1486 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v32i1, Custom);
1487 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v64i1, Custom);
1488 setOperationAction(ISD::VSELECT, MVT::v32i16, Legal);
1489 setOperationAction(ISD::VSELECT, MVT::v64i8, Legal);
1490 setOperationAction(ISD::TRUNCATE, MVT::v32i1, Custom);
1491 setOperationAction(ISD::TRUNCATE, MVT::v64i1, Custom);
1493 for (int i = MVT::v32i8; i != MVT::v8i64; ++i) {
1494 const MVT VT = (MVT::SimpleValueType)i;
1496 const unsigned EltSize = VT.getVectorElementType().getSizeInBits();
1498 // Do not attempt to promote non-512-bit vectors.
1499 if (!VT.is512BitVector())
1503 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1504 setOperationAction(ISD::VSELECT, VT, Legal);
1509 if (!Subtarget->useSoftFloat() && Subtarget->hasVLX()) {
1510 addRegisterClass(MVT::v4i1, &X86::VK4RegClass);
1511 addRegisterClass(MVT::v2i1, &X86::VK2RegClass);
1513 setOperationAction(ISD::SETCC, MVT::v4i1, Custom);
1514 setOperationAction(ISD::SETCC, MVT::v2i1, Custom);
1515 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4i1, Custom);
1516 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i1, Custom);
1517 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v8i1, Custom);
1518 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v4i1, Custom);
1519 setOperationAction(ISD::SELECT, MVT::v4i1, Custom);
1520 setOperationAction(ISD::SELECT, MVT::v2i1, Custom);
1521 setOperationAction(ISD::BUILD_VECTOR, MVT::v4i1, Custom);
1522 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i1, Custom);
1524 setOperationAction(ISD::AND, MVT::v8i32, Legal);
1525 setOperationAction(ISD::OR, MVT::v8i32, Legal);
1526 setOperationAction(ISD::XOR, MVT::v8i32, Legal);
1527 setOperationAction(ISD::AND, MVT::v4i32, Legal);
1528 setOperationAction(ISD::OR, MVT::v4i32, Legal);
1529 setOperationAction(ISD::XOR, MVT::v4i32, Legal);
1530 setOperationAction(ISD::SRA, MVT::v2i64, Custom);
1531 setOperationAction(ISD::SRA, MVT::v4i64, Custom);
1534 // We want to custom lower some of our intrinsics.
1535 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
1536 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::Other, Custom);
1537 setOperationAction(ISD::INTRINSIC_VOID, MVT::Other, Custom);
1538 if (!Subtarget->is64Bit())
1539 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::i64, Custom);
1541 // Only custom-lower 64-bit SADDO and friends on 64-bit because we don't
1542 // handle type legalization for these operations here.
1544 // FIXME: We really should do custom legalization for addition and
1545 // subtraction on x86-32 once PR3203 is fixed. We really can't do much better
1546 // than generic legalization for 64-bit multiplication-with-overflow, though.
1547 for (unsigned i = 0, e = 3+Subtarget->is64Bit(); i != e; ++i) {
1548 // Add/Sub/Mul with overflow operations are custom lowered.
1550 setOperationAction(ISD::SADDO, VT, Custom);
1551 setOperationAction(ISD::UADDO, VT, Custom);
1552 setOperationAction(ISD::SSUBO, VT, Custom);
1553 setOperationAction(ISD::USUBO, VT, Custom);
1554 setOperationAction(ISD::SMULO, VT, Custom);
1555 setOperationAction(ISD::UMULO, VT, Custom);
1559 if (!Subtarget->is64Bit()) {
1560 // These libcalls are not available in 32-bit.
1561 setLibcallName(RTLIB::SHL_I128, nullptr);
1562 setLibcallName(RTLIB::SRL_I128, nullptr);
1563 setLibcallName(RTLIB::SRA_I128, nullptr);
1566 // Combine sin / cos into one node or libcall if possible.
1567 if (Subtarget->hasSinCos()) {
1568 setLibcallName(RTLIB::SINCOS_F32, "sincosf");
1569 setLibcallName(RTLIB::SINCOS_F64, "sincos");
1570 if (Subtarget->isTargetDarwin()) {
1571 // For MacOSX, we don't want the normal expansion of a libcall to sincos.
1572 // We want to issue a libcall to __sincos_stret to avoid memory traffic.
1573 setOperationAction(ISD::FSINCOS, MVT::f64, Custom);
1574 setOperationAction(ISD::FSINCOS, MVT::f32, Custom);
1578 if (Subtarget->isTargetWin64()) {
1579 setOperationAction(ISD::SDIV, MVT::i128, Custom);
1580 setOperationAction(ISD::UDIV, MVT::i128, Custom);
1581 setOperationAction(ISD::SREM, MVT::i128, Custom);
1582 setOperationAction(ISD::UREM, MVT::i128, Custom);
1583 setOperationAction(ISD::SDIVREM, MVT::i128, Custom);
1584 setOperationAction(ISD::UDIVREM, MVT::i128, Custom);
1587 // We have target-specific dag combine patterns for the following nodes:
1588 setTargetDAGCombine(ISD::VECTOR_SHUFFLE);
1589 setTargetDAGCombine(ISD::EXTRACT_VECTOR_ELT);
1590 setTargetDAGCombine(ISD::BITCAST);
1591 setTargetDAGCombine(ISD::VSELECT);
1592 setTargetDAGCombine(ISD::SELECT);
1593 setTargetDAGCombine(ISD::SHL);
1594 setTargetDAGCombine(ISD::SRA);
1595 setTargetDAGCombine(ISD::SRL);
1596 setTargetDAGCombine(ISD::OR);
1597 setTargetDAGCombine(ISD::AND);
1598 setTargetDAGCombine(ISD::ADD);
1599 setTargetDAGCombine(ISD::FADD);
1600 setTargetDAGCombine(ISD::FSUB);
1601 setTargetDAGCombine(ISD::FMA);
1602 setTargetDAGCombine(ISD::SUB);
1603 setTargetDAGCombine(ISD::LOAD);
1604 setTargetDAGCombine(ISD::MLOAD);
1605 setTargetDAGCombine(ISD::STORE);
1606 setTargetDAGCombine(ISD::MSTORE);
1607 setTargetDAGCombine(ISD::ZERO_EXTEND);
1608 setTargetDAGCombine(ISD::ANY_EXTEND);
1609 setTargetDAGCombine(ISD::SIGN_EXTEND);
1610 setTargetDAGCombine(ISD::SIGN_EXTEND_INREG);
1611 setTargetDAGCombine(ISD::SINT_TO_FP);
1612 setTargetDAGCombine(ISD::SETCC);
1613 setTargetDAGCombine(ISD::INTRINSIC_WO_CHAIN);
1614 setTargetDAGCombine(ISD::BUILD_VECTOR);
1615 setTargetDAGCombine(ISD::MUL);
1616 setTargetDAGCombine(ISD::XOR);
1618 computeRegisterProperties(Subtarget->getRegisterInfo());
1620 // On Darwin, -Os means optimize for size without hurting performance,
1621 // do not reduce the limit.
1622 MaxStoresPerMemset = 16; // For @llvm.memset -> sequence of stores
1623 MaxStoresPerMemsetOptSize = Subtarget->isTargetDarwin() ? 16 : 8;
1624 MaxStoresPerMemcpy = 8; // For @llvm.memcpy -> sequence of stores
1625 MaxStoresPerMemcpyOptSize = Subtarget->isTargetDarwin() ? 8 : 4;
1626 MaxStoresPerMemmove = 8; // For @llvm.memmove -> sequence of stores
1627 MaxStoresPerMemmoveOptSize = Subtarget->isTargetDarwin() ? 8 : 4;
1628 setPrefLoopAlignment(4); // 2^4 bytes.
1630 // Predictable cmov don't hurt on atom because it's in-order.
1631 PredictableSelectIsExpensive = !Subtarget->isAtom();
1632 EnableExtLdPromotion = true;
1633 setPrefFunctionAlignment(4); // 2^4 bytes.
1635 verifyIntrinsicTables();
1638 // This has so far only been implemented for 64-bit MachO.
1639 bool X86TargetLowering::useLoadStackGuardNode() const {
1640 return Subtarget->isTargetMachO() && Subtarget->is64Bit();
1643 TargetLoweringBase::LegalizeTypeAction
1644 X86TargetLowering::getPreferredVectorAction(EVT VT) const {
1645 if (ExperimentalVectorWideningLegalization &&
1646 VT.getVectorNumElements() != 1 &&
1647 VT.getVectorElementType().getSimpleVT() != MVT::i1)
1648 return TypeWidenVector;
1650 return TargetLoweringBase::getPreferredVectorAction(VT);
1653 EVT X86TargetLowering::getSetCCResultType(LLVMContext &, EVT VT) const {
1655 return Subtarget->hasAVX512() ? MVT::i1: MVT::i8;
1657 const unsigned NumElts = VT.getVectorNumElements();
1658 const EVT EltVT = VT.getVectorElementType();
1659 if (VT.is512BitVector()) {
1660 if (Subtarget->hasAVX512())
1661 if (EltVT == MVT::i32 || EltVT == MVT::i64 ||
1662 EltVT == MVT::f32 || EltVT == MVT::f64)
1664 case 8: return MVT::v8i1;
1665 case 16: return MVT::v16i1;
1667 if (Subtarget->hasBWI())
1668 if (EltVT == MVT::i8 || EltVT == MVT::i16)
1670 case 32: return MVT::v32i1;
1671 case 64: return MVT::v64i1;
1675 if (VT.is256BitVector() || VT.is128BitVector()) {
1676 if (Subtarget->hasVLX())
1677 if (EltVT == MVT::i32 || EltVT == MVT::i64 ||
1678 EltVT == MVT::f32 || EltVT == MVT::f64)
1680 case 2: return MVT::v2i1;
1681 case 4: return MVT::v4i1;
1682 case 8: return MVT::v8i1;
1684 if (Subtarget->hasBWI() && Subtarget->hasVLX())
1685 if (EltVT == MVT::i8 || EltVT == MVT::i16)
1687 case 8: return MVT::v8i1;
1688 case 16: return MVT::v16i1;
1689 case 32: return MVT::v32i1;
1693 return VT.changeVectorElementTypeToInteger();
1696 /// Helper for getByValTypeAlignment to determine
1697 /// the desired ByVal argument alignment.
1698 static void getMaxByValAlign(Type *Ty, unsigned &MaxAlign) {
1701 if (VectorType *VTy = dyn_cast<VectorType>(Ty)) {
1702 if (VTy->getBitWidth() == 128)
1704 } else if (ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
1705 unsigned EltAlign = 0;
1706 getMaxByValAlign(ATy->getElementType(), EltAlign);
1707 if (EltAlign > MaxAlign)
1708 MaxAlign = EltAlign;
1709 } else if (StructType *STy = dyn_cast<StructType>(Ty)) {
1710 for (unsigned i = 0, e = STy->getNumElements(); i != e; ++i) {
1711 unsigned EltAlign = 0;
1712 getMaxByValAlign(STy->getElementType(i), EltAlign);
1713 if (EltAlign > MaxAlign)
1714 MaxAlign = EltAlign;
1721 /// Return the desired alignment for ByVal aggregate
1722 /// function arguments in the caller parameter area. For X86, aggregates
1723 /// that contain SSE vectors are placed at 16-byte boundaries while the rest
1724 /// are at 4-byte boundaries.
1725 unsigned X86TargetLowering::getByValTypeAlignment(Type *Ty) const {
1726 if (Subtarget->is64Bit()) {
1727 // Max of 8 and alignment of type.
1728 unsigned TyAlign = TD->getABITypeAlignment(Ty);
1735 if (Subtarget->hasSSE1())
1736 getMaxByValAlign(Ty, Align);
1740 /// Returns the target specific optimal type for load
1741 /// and store operations as a result of memset, memcpy, and memmove
1742 /// lowering. If DstAlign is zero that means it's safe to destination
1743 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
1744 /// means there isn't a need to check it against alignment requirement,
1745 /// probably because the source does not need to be loaded. If 'IsMemset' is
1746 /// true, that means it's expanding a memset. If 'ZeroMemset' is true, that
1747 /// means it's a memset of zero. 'MemcpyStrSrc' indicates whether the memcpy
1748 /// source is constant so it does not need to be loaded.
1749 /// It returns EVT::Other if the type should be determined using generic
1750 /// target-independent logic.
1752 X86TargetLowering::getOptimalMemOpType(uint64_t Size,
1753 unsigned DstAlign, unsigned SrcAlign,
1754 bool IsMemset, bool ZeroMemset,
1756 MachineFunction &MF) const {
1757 const Function *F = MF.getFunction();
1758 if ((!IsMemset || ZeroMemset) &&
1759 !F->hasFnAttribute(Attribute::NoImplicitFloat)) {
1761 (Subtarget->isUnalignedMemAccessFast() ||
1762 ((DstAlign == 0 || DstAlign >= 16) &&
1763 (SrcAlign == 0 || SrcAlign >= 16)))) {
1765 if (Subtarget->hasInt256())
1767 if (Subtarget->hasFp256())
1770 if (Subtarget->hasSSE2())
1772 if (Subtarget->hasSSE1())
1774 } else if (!MemcpyStrSrc && Size >= 8 &&
1775 !Subtarget->is64Bit() &&
1776 Subtarget->hasSSE2()) {
1777 // Do not use f64 to lower memcpy if source is string constant. It's
1778 // better to use i32 to avoid the loads.
1782 if (Subtarget->is64Bit() && Size >= 8)
1787 bool X86TargetLowering::isSafeMemOpType(MVT VT) const {
1789 return X86ScalarSSEf32;
1790 else if (VT == MVT::f64)
1791 return X86ScalarSSEf64;
1796 X86TargetLowering::allowsMisalignedMemoryAccesses(EVT VT,
1801 *Fast = Subtarget->isUnalignedMemAccessFast();
1805 /// Return the entry encoding for a jump table in the
1806 /// current function. The returned value is a member of the
1807 /// MachineJumpTableInfo::JTEntryKind enum.
1808 unsigned X86TargetLowering::getJumpTableEncoding() const {
1809 // In GOT pic mode, each entry in the jump table is emitted as a @GOTOFF
1811 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1812 Subtarget->isPICStyleGOT())
1813 return MachineJumpTableInfo::EK_Custom32;
1815 // Otherwise, use the normal jump table encoding heuristics.
1816 return TargetLowering::getJumpTableEncoding();
1819 bool X86TargetLowering::useSoftFloat() const {
1820 return Subtarget->useSoftFloat();
1824 X86TargetLowering::LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI,
1825 const MachineBasicBlock *MBB,
1826 unsigned uid,MCContext &Ctx) const{
1827 assert(MBB->getParent()->getTarget().getRelocationModel() == Reloc::PIC_ &&
1828 Subtarget->isPICStyleGOT());
1829 // In 32-bit ELF systems, our jump table entries are formed with @GOTOFF
1831 return MCSymbolRefExpr::create(MBB->getSymbol(),
1832 MCSymbolRefExpr::VK_GOTOFF, Ctx);
1835 /// Returns relocation base for the given PIC jumptable.
1836 SDValue X86TargetLowering::getPICJumpTableRelocBase(SDValue Table,
1837 SelectionDAG &DAG) const {
1838 if (!Subtarget->is64Bit())
1839 // This doesn't have SDLoc associated with it, but is not really the
1840 // same as a Register.
1841 return DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), getPointerTy());
1845 /// This returns the relocation base for the given PIC jumptable,
1846 /// the same as getPICJumpTableRelocBase, but as an MCExpr.
1847 const MCExpr *X86TargetLowering::
1848 getPICJumpTableRelocBaseExpr(const MachineFunction *MF, unsigned JTI,
1849 MCContext &Ctx) const {
1850 // X86-64 uses RIP relative addressing based on the jump table label.
1851 if (Subtarget->isPICStyleRIPRel())
1852 return TargetLowering::getPICJumpTableRelocBaseExpr(MF, JTI, Ctx);
1854 // Otherwise, the reference is relative to the PIC base.
1855 return MCSymbolRefExpr::create(MF->getPICBaseSymbol(), Ctx);
1858 std::pair<const TargetRegisterClass *, uint8_t>
1859 X86TargetLowering::findRepresentativeClass(const TargetRegisterInfo *TRI,
1861 const TargetRegisterClass *RRC = nullptr;
1863 switch (VT.SimpleTy) {
1865 return TargetLowering::findRepresentativeClass(TRI, VT);
1866 case MVT::i8: case MVT::i16: case MVT::i32: case MVT::i64:
1867 RRC = Subtarget->is64Bit() ? &X86::GR64RegClass : &X86::GR32RegClass;
1870 RRC = &X86::VR64RegClass;
1872 case MVT::f32: case MVT::f64:
1873 case MVT::v16i8: case MVT::v8i16: case MVT::v4i32: case MVT::v2i64:
1874 case MVT::v4f32: case MVT::v2f64:
1875 case MVT::v32i8: case MVT::v8i32: case MVT::v4i64: case MVT::v8f32:
1877 RRC = &X86::VR128RegClass;
1880 return std::make_pair(RRC, Cost);
1883 bool X86TargetLowering::getStackCookieLocation(unsigned &AddressSpace,
1884 unsigned &Offset) const {
1885 if (!Subtarget->isTargetLinux())
1888 if (Subtarget->is64Bit()) {
1889 // %fs:0x28, unless we're using a Kernel code model, in which case it's %gs:
1891 if (getTargetMachine().getCodeModel() == CodeModel::Kernel)
1903 bool X86TargetLowering::isNoopAddrSpaceCast(unsigned SrcAS,
1904 unsigned DestAS) const {
1905 assert(SrcAS != DestAS && "Expected different address spaces!");
1907 return SrcAS < 256 && DestAS < 256;
1910 //===----------------------------------------------------------------------===//
1911 // Return Value Calling Convention Implementation
1912 //===----------------------------------------------------------------------===//
1914 #include "X86GenCallingConv.inc"
1917 X86TargetLowering::CanLowerReturn(CallingConv::ID CallConv,
1918 MachineFunction &MF, bool isVarArg,
1919 const SmallVectorImpl<ISD::OutputArg> &Outs,
1920 LLVMContext &Context) const {
1921 SmallVector<CCValAssign, 16> RVLocs;
1922 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, Context);
1923 return CCInfo.CheckReturn(Outs, RetCC_X86);
1926 const MCPhysReg *X86TargetLowering::getScratchRegisters(CallingConv::ID) const {
1927 static const MCPhysReg ScratchRegs[] = { X86::R11, 0 };
1932 X86TargetLowering::LowerReturn(SDValue Chain,
1933 CallingConv::ID CallConv, bool isVarArg,
1934 const SmallVectorImpl<ISD::OutputArg> &Outs,
1935 const SmallVectorImpl<SDValue> &OutVals,
1936 SDLoc dl, SelectionDAG &DAG) const {
1937 MachineFunction &MF = DAG.getMachineFunction();
1938 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1940 SmallVector<CCValAssign, 16> RVLocs;
1941 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, *DAG.getContext());
1942 CCInfo.AnalyzeReturn(Outs, RetCC_X86);
1945 SmallVector<SDValue, 6> RetOps;
1946 RetOps.push_back(Chain); // Operand #0 = Chain (updated below)
1947 // Operand #1 = Bytes To Pop
1948 RetOps.push_back(DAG.getTargetConstant(FuncInfo->getBytesToPopOnReturn(), dl,
1951 // Copy the result values into the output registers.
1952 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1953 CCValAssign &VA = RVLocs[i];
1954 assert(VA.isRegLoc() && "Can only return in registers!");
1955 SDValue ValToCopy = OutVals[i];
1956 EVT ValVT = ValToCopy.getValueType();
1958 // Promote values to the appropriate types.
1959 if (VA.getLocInfo() == CCValAssign::SExt)
1960 ValToCopy = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), ValToCopy);
1961 else if (VA.getLocInfo() == CCValAssign::ZExt)
1962 ValToCopy = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), ValToCopy);
1963 else if (VA.getLocInfo() == CCValAssign::AExt) {
1964 if (ValVT.isVector() && ValVT.getScalarType() == MVT::i1)
1965 ValToCopy = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), ValToCopy);
1967 ValToCopy = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), ValToCopy);
1969 else if (VA.getLocInfo() == CCValAssign::BCvt)
1970 ValToCopy = DAG.getBitcast(VA.getLocVT(), ValToCopy);
1972 assert(VA.getLocInfo() != CCValAssign::FPExt &&
1973 "Unexpected FP-extend for return value.");
1975 // If this is x86-64, and we disabled SSE, we can't return FP values,
1976 // or SSE or MMX vectors.
1977 if ((ValVT == MVT::f32 || ValVT == MVT::f64 ||
1978 VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) &&
1979 (Subtarget->is64Bit() && !Subtarget->hasSSE1())) {
1980 report_fatal_error("SSE register return with SSE disabled");
1982 // Likewise we can't return F64 values with SSE1 only. gcc does so, but
1983 // llvm-gcc has never done it right and no one has noticed, so this
1984 // should be OK for now.
1985 if (ValVT == MVT::f64 &&
1986 (Subtarget->is64Bit() && !Subtarget->hasSSE2()))
1987 report_fatal_error("SSE2 register return with SSE2 disabled");
1989 // Returns in ST0/ST1 are handled specially: these are pushed as operands to
1990 // the RET instruction and handled by the FP Stackifier.
1991 if (VA.getLocReg() == X86::FP0 ||
1992 VA.getLocReg() == X86::FP1) {
1993 // If this is a copy from an xmm register to ST(0), use an FPExtend to
1994 // change the value to the FP stack register class.
1995 if (isScalarFPTypeInSSEReg(VA.getValVT()))
1996 ValToCopy = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f80, ValToCopy);
1997 RetOps.push_back(ValToCopy);
1998 // Don't emit a copytoreg.
2002 // 64-bit vector (MMX) values are returned in XMM0 / XMM1 except for v1i64
2003 // which is returned in RAX / RDX.
2004 if (Subtarget->is64Bit()) {
2005 if (ValVT == MVT::x86mmx) {
2006 if (VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) {
2007 ValToCopy = DAG.getBitcast(MVT::i64, ValToCopy);
2008 ValToCopy = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
2010 // If we don't have SSE2 available, convert to v4f32 so the generated
2011 // register is legal.
2012 if (!Subtarget->hasSSE2())
2013 ValToCopy = DAG.getBitcast(MVT::v4f32, ValToCopy);
2018 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), ValToCopy, Flag);
2019 Flag = Chain.getValue(1);
2020 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
2023 // All x86 ABIs require that for returning structs by value we copy
2024 // the sret argument into %rax/%eax (depending on ABI) for the return.
2025 // We saved the argument into a virtual register in the entry block,
2026 // so now we copy the value out and into %rax/%eax.
2028 // Checking Function.hasStructRetAttr() here is insufficient because the IR
2029 // may not have an explicit sret argument. If FuncInfo.CanLowerReturn is
2030 // false, then an sret argument may be implicitly inserted in the SelDAG. In
2031 // either case FuncInfo->setSRetReturnReg() will have been called.
2032 if (unsigned SRetReg = FuncInfo->getSRetReturnReg()) {
2033 SDValue Val = DAG.getCopyFromReg(Chain, dl, SRetReg, getPointerTy());
2036 = (Subtarget->is64Bit() && !Subtarget->isTarget64BitILP32()) ?
2037 X86::RAX : X86::EAX;
2038 Chain = DAG.getCopyToReg(Chain, dl, RetValReg, Val, Flag);
2039 Flag = Chain.getValue(1);
2041 // RAX/EAX now acts like a return value.
2042 RetOps.push_back(DAG.getRegister(RetValReg, getPointerTy()));
2045 RetOps[0] = Chain; // Update chain.
2047 // Add the flag if we have it.
2049 RetOps.push_back(Flag);
2051 return DAG.getNode(X86ISD::RET_FLAG, dl, MVT::Other, RetOps);
2054 bool X86TargetLowering::isUsedByReturnOnly(SDNode *N, SDValue &Chain) const {
2055 if (N->getNumValues() != 1)
2057 if (!N->hasNUsesOfValue(1, 0))
2060 SDValue TCChain = Chain;
2061 SDNode *Copy = *N->use_begin();
2062 if (Copy->getOpcode() == ISD::CopyToReg) {
2063 // If the copy has a glue operand, we conservatively assume it isn't safe to
2064 // perform a tail call.
2065 if (Copy->getOperand(Copy->getNumOperands()-1).getValueType() == MVT::Glue)
2067 TCChain = Copy->getOperand(0);
2068 } else if (Copy->getOpcode() != ISD::FP_EXTEND)
2071 bool HasRet = false;
2072 for (SDNode::use_iterator UI = Copy->use_begin(), UE = Copy->use_end();
2074 if (UI->getOpcode() != X86ISD::RET_FLAG)
2076 // If we are returning more than one value, we can definitely
2077 // not make a tail call see PR19530
2078 if (UI->getNumOperands() > 4)
2080 if (UI->getNumOperands() == 4 &&
2081 UI->getOperand(UI->getNumOperands()-1).getValueType() != MVT::Glue)
2094 X86TargetLowering::getTypeForExtArgOrReturn(LLVMContext &Context, EVT VT,
2095 ISD::NodeType ExtendKind) const {
2097 // TODO: Is this also valid on 32-bit?
2098 if (Subtarget->is64Bit() && VT == MVT::i1 && ExtendKind == ISD::ZERO_EXTEND)
2099 ReturnMVT = MVT::i8;
2101 ReturnMVT = MVT::i32;
2103 EVT MinVT = getRegisterType(Context, ReturnMVT);
2104 return VT.bitsLT(MinVT) ? MinVT : VT;
2107 /// Lower the result values of a call into the
2108 /// appropriate copies out of appropriate physical registers.
2111 X86TargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
2112 CallingConv::ID CallConv, bool isVarArg,
2113 const SmallVectorImpl<ISD::InputArg> &Ins,
2114 SDLoc dl, SelectionDAG &DAG,
2115 SmallVectorImpl<SDValue> &InVals) const {
2117 // Assign locations to each value returned by this call.
2118 SmallVector<CCValAssign, 16> RVLocs;
2119 bool Is64Bit = Subtarget->is64Bit();
2120 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
2122 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
2124 // Copy all of the result registers out of their specified physreg.
2125 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
2126 CCValAssign &VA = RVLocs[i];
2127 EVT CopyVT = VA.getLocVT();
2129 // If this is x86-64, and we disabled SSE, we can't return FP values
2130 if ((CopyVT == MVT::f32 || CopyVT == MVT::f64) &&
2131 ((Is64Bit || Ins[i].Flags.isInReg()) && !Subtarget->hasSSE1())) {
2132 report_fatal_error("SSE register return with SSE disabled");
2135 // If we prefer to use the value in xmm registers, copy it out as f80 and
2136 // use a truncate to move it from fp stack reg to xmm reg.
2137 bool RoundAfterCopy = false;
2138 if ((VA.getLocReg() == X86::FP0 || VA.getLocReg() == X86::FP1) &&
2139 isScalarFPTypeInSSEReg(VA.getValVT())) {
2141 RoundAfterCopy = (CopyVT != VA.getLocVT());
2144 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(),
2145 CopyVT, InFlag).getValue(1);
2146 SDValue Val = Chain.getValue(0);
2149 Val = DAG.getNode(ISD::FP_ROUND, dl, VA.getValVT(), Val,
2150 // This truncation won't change the value.
2151 DAG.getIntPtrConstant(1, dl));
2153 if (VA.isExtInLoc() && VA.getValVT().getScalarType() == MVT::i1)
2154 Val = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Val);
2156 InFlag = Chain.getValue(2);
2157 InVals.push_back(Val);
2163 //===----------------------------------------------------------------------===//
2164 // C & StdCall & Fast Calling Convention implementation
2165 //===----------------------------------------------------------------------===//
2166 // StdCall calling convention seems to be standard for many Windows' API
2167 // routines and around. It differs from C calling convention just a little:
2168 // callee should clean up the stack, not caller. Symbols should be also
2169 // decorated in some fancy way :) It doesn't support any vector arguments.
2170 // For info on fast calling convention see Fast Calling Convention (tail call)
2171 // implementation LowerX86_32FastCCCallTo.
2173 /// CallIsStructReturn - Determines whether a call uses struct return
2175 enum StructReturnType {
2180 static StructReturnType
2181 callIsStructReturn(const SmallVectorImpl<ISD::OutputArg> &Outs) {
2183 return NotStructReturn;
2185 const ISD::ArgFlagsTy &Flags = Outs[0].Flags;
2186 if (!Flags.isSRet())
2187 return NotStructReturn;
2188 if (Flags.isInReg())
2189 return RegStructReturn;
2190 return StackStructReturn;
2193 /// Determines whether a function uses struct return semantics.
2194 static StructReturnType
2195 argsAreStructReturn(const SmallVectorImpl<ISD::InputArg> &Ins) {
2197 return NotStructReturn;
2199 const ISD::ArgFlagsTy &Flags = Ins[0].Flags;
2200 if (!Flags.isSRet())
2201 return NotStructReturn;
2202 if (Flags.isInReg())
2203 return RegStructReturn;
2204 return StackStructReturn;
2207 /// Make a copy of an aggregate at address specified by "Src" to address
2208 /// "Dst" with size and alignment information specified by the specific
2209 /// parameter attribute. The copy will be passed as a byval function parameter.
2211 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
2212 ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
2214 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), dl, MVT::i32);
2216 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
2217 /*isVolatile*/false, /*AlwaysInline=*/true,
2218 /*isTailCall*/false,
2219 MachinePointerInfo(), MachinePointerInfo());
2222 /// Return true if the calling convention is one that
2223 /// supports tail call optimization.
2224 static bool IsTailCallConvention(CallingConv::ID CC) {
2225 return (CC == CallingConv::Fast || CC == CallingConv::GHC ||
2226 CC == CallingConv::HiPE);
2229 /// \brief Return true if the calling convention is a C calling convention.
2230 static bool IsCCallConvention(CallingConv::ID CC) {
2231 return (CC == CallingConv::C || CC == CallingConv::X86_64_Win64 ||
2232 CC == CallingConv::X86_64_SysV);
2235 bool X86TargetLowering::mayBeEmittedAsTailCall(CallInst *CI) const {
2237 CI->getParent()->getParent()->getFnAttribute("disable-tail-calls");
2238 if (!CI->isTailCall() || Attr.getValueAsString() == "true")
2242 CallingConv::ID CalleeCC = CS.getCallingConv();
2243 if (!IsTailCallConvention(CalleeCC) && !IsCCallConvention(CalleeCC))
2249 /// Return true if the function is being made into
2250 /// a tailcall target by changing its ABI.
2251 static bool FuncIsMadeTailCallSafe(CallingConv::ID CC,
2252 bool GuaranteedTailCallOpt) {
2253 return GuaranteedTailCallOpt && IsTailCallConvention(CC);
2257 X86TargetLowering::LowerMemArgument(SDValue Chain,
2258 CallingConv::ID CallConv,
2259 const SmallVectorImpl<ISD::InputArg> &Ins,
2260 SDLoc dl, SelectionDAG &DAG,
2261 const CCValAssign &VA,
2262 MachineFrameInfo *MFI,
2264 // Create the nodes corresponding to a load from this parameter slot.
2265 ISD::ArgFlagsTy Flags = Ins[i].Flags;
2266 bool AlwaysUseMutable = FuncIsMadeTailCallSafe(
2267 CallConv, DAG.getTarget().Options.GuaranteedTailCallOpt);
2268 bool isImmutable = !AlwaysUseMutable && !Flags.isByVal();
2271 // If value is passed by pointer we have address passed instead of the value
2273 bool ExtendedInMem = VA.isExtInLoc() &&
2274 VA.getValVT().getScalarType() == MVT::i1;
2276 if (VA.getLocInfo() == CCValAssign::Indirect || ExtendedInMem)
2277 ValVT = VA.getLocVT();
2279 ValVT = VA.getValVT();
2281 // FIXME: For now, all byval parameter objects are marked mutable. This can be
2282 // changed with more analysis.
2283 // In case of tail call optimization mark all arguments mutable. Since they
2284 // could be overwritten by lowering of arguments in case of a tail call.
2285 if (Flags.isByVal()) {
2286 unsigned Bytes = Flags.getByValSize();
2287 if (Bytes == 0) Bytes = 1; // Don't create zero-sized stack objects.
2288 int FI = MFI->CreateFixedObject(Bytes, VA.getLocMemOffset(), isImmutable);
2289 return DAG.getFrameIndex(FI, getPointerTy());
2291 int FI = MFI->CreateFixedObject(ValVT.getSizeInBits()/8,
2292 VA.getLocMemOffset(), isImmutable);
2293 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
2294 SDValue Val = DAG.getLoad(ValVT, dl, Chain, FIN,
2295 MachinePointerInfo::getFixedStack(FI),
2296 false, false, false, 0);
2297 return ExtendedInMem ?
2298 DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Val) : Val;
2302 // FIXME: Get this from tablegen.
2303 static ArrayRef<MCPhysReg> get64BitArgumentGPRs(CallingConv::ID CallConv,
2304 const X86Subtarget *Subtarget) {
2305 assert(Subtarget->is64Bit());
2307 if (Subtarget->isCallingConvWin64(CallConv)) {
2308 static const MCPhysReg GPR64ArgRegsWin64[] = {
2309 X86::RCX, X86::RDX, X86::R8, X86::R9
2311 return makeArrayRef(std::begin(GPR64ArgRegsWin64), std::end(GPR64ArgRegsWin64));
2314 static const MCPhysReg GPR64ArgRegs64Bit[] = {
2315 X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9
2317 return makeArrayRef(std::begin(GPR64ArgRegs64Bit), std::end(GPR64ArgRegs64Bit));
2320 // FIXME: Get this from tablegen.
2321 static ArrayRef<MCPhysReg> get64BitArgumentXMMs(MachineFunction &MF,
2322 CallingConv::ID CallConv,
2323 const X86Subtarget *Subtarget) {
2324 assert(Subtarget->is64Bit());
2325 if (Subtarget->isCallingConvWin64(CallConv)) {
2326 // The XMM registers which might contain var arg parameters are shadowed
2327 // in their paired GPR. So we only need to save the GPR to their home
2329 // TODO: __vectorcall will change this.
2333 const Function *Fn = MF.getFunction();
2334 bool NoImplicitFloatOps = Fn->hasFnAttribute(Attribute::NoImplicitFloat);
2335 bool isSoftFloat = Subtarget->useSoftFloat();
2336 assert(!(isSoftFloat && NoImplicitFloatOps) &&
2337 "SSE register cannot be used when SSE is disabled!");
2338 if (isSoftFloat || NoImplicitFloatOps || !Subtarget->hasSSE1())
2339 // Kernel mode asks for SSE to be disabled, so there are no XMM argument
2343 static const MCPhysReg XMMArgRegs64Bit[] = {
2344 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
2345 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
2347 return makeArrayRef(std::begin(XMMArgRegs64Bit), std::end(XMMArgRegs64Bit));
2351 X86TargetLowering::LowerFormalArguments(SDValue Chain,
2352 CallingConv::ID CallConv,
2354 const SmallVectorImpl<ISD::InputArg> &Ins,
2357 SmallVectorImpl<SDValue> &InVals)
2359 MachineFunction &MF = DAG.getMachineFunction();
2360 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
2361 const TargetFrameLowering &TFI = *Subtarget->getFrameLowering();
2363 const Function* Fn = MF.getFunction();
2364 if (Fn->hasExternalLinkage() &&
2365 Subtarget->isTargetCygMing() &&
2366 Fn->getName() == "main")
2367 FuncInfo->setForceFramePointer(true);
2369 MachineFrameInfo *MFI = MF.getFrameInfo();
2370 bool Is64Bit = Subtarget->is64Bit();
2371 bool IsWin64 = Subtarget->isCallingConvWin64(CallConv);
2373 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
2374 "Var args not supported with calling convention fastcc, ghc or hipe");
2376 // Assign locations to all of the incoming arguments.
2377 SmallVector<CCValAssign, 16> ArgLocs;
2378 CCState CCInfo(CallConv, isVarArg, MF, ArgLocs, *DAG.getContext());
2380 // Allocate shadow area for Win64
2382 CCInfo.AllocateStack(32, 8);
2384 CCInfo.AnalyzeFormalArguments(Ins, CC_X86);
2386 unsigned LastVal = ~0U;
2388 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2389 CCValAssign &VA = ArgLocs[i];
2390 // TODO: If an arg is passed in two places (e.g. reg and stack), skip later
2392 assert(VA.getValNo() != LastVal &&
2393 "Don't support value assigned to multiple locs yet");
2395 LastVal = VA.getValNo();
2397 if (VA.isRegLoc()) {
2398 EVT RegVT = VA.getLocVT();
2399 const TargetRegisterClass *RC;
2400 if (RegVT == MVT::i32)
2401 RC = &X86::GR32RegClass;
2402 else if (Is64Bit && RegVT == MVT::i64)
2403 RC = &X86::GR64RegClass;
2404 else if (RegVT == MVT::f32)
2405 RC = &X86::FR32RegClass;
2406 else if (RegVT == MVT::f64)
2407 RC = &X86::FR64RegClass;
2408 else if (RegVT.is512BitVector())
2409 RC = &X86::VR512RegClass;
2410 else if (RegVT.is256BitVector())
2411 RC = &X86::VR256RegClass;
2412 else if (RegVT.is128BitVector())
2413 RC = &X86::VR128RegClass;
2414 else if (RegVT == MVT::x86mmx)
2415 RC = &X86::VR64RegClass;
2416 else if (RegVT == MVT::i1)
2417 RC = &X86::VK1RegClass;
2418 else if (RegVT == MVT::v8i1)
2419 RC = &X86::VK8RegClass;
2420 else if (RegVT == MVT::v16i1)
2421 RC = &X86::VK16RegClass;
2422 else if (RegVT == MVT::v32i1)
2423 RC = &X86::VK32RegClass;
2424 else if (RegVT == MVT::v64i1)
2425 RC = &X86::VK64RegClass;
2427 llvm_unreachable("Unknown argument type!");
2429 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
2430 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
2432 // If this is an 8 or 16-bit value, it is really passed promoted to 32
2433 // bits. Insert an assert[sz]ext to capture this, then truncate to the
2435 if (VA.getLocInfo() == CCValAssign::SExt)
2436 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
2437 DAG.getValueType(VA.getValVT()));
2438 else if (VA.getLocInfo() == CCValAssign::ZExt)
2439 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
2440 DAG.getValueType(VA.getValVT()));
2441 else if (VA.getLocInfo() == CCValAssign::BCvt)
2442 ArgValue = DAG.getBitcast(VA.getValVT(), ArgValue);
2444 if (VA.isExtInLoc()) {
2445 // Handle MMX values passed in XMM regs.
2446 if (RegVT.isVector() && VA.getValVT().getScalarType() != MVT::i1)
2447 ArgValue = DAG.getNode(X86ISD::MOVDQ2Q, dl, VA.getValVT(), ArgValue);
2449 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
2452 assert(VA.isMemLoc());
2453 ArgValue = LowerMemArgument(Chain, CallConv, Ins, dl, DAG, VA, MFI, i);
2456 // If value is passed via pointer - do a load.
2457 if (VA.getLocInfo() == CCValAssign::Indirect)
2458 ArgValue = DAG.getLoad(VA.getValVT(), dl, Chain, ArgValue,
2459 MachinePointerInfo(), false, false, false, 0);
2461 InVals.push_back(ArgValue);
2464 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2465 // All x86 ABIs require that for returning structs by value we copy the
2466 // sret argument into %rax/%eax (depending on ABI) for the return. Save
2467 // the argument into a virtual register so that we can access it from the
2469 if (Ins[i].Flags.isSRet()) {
2470 unsigned Reg = FuncInfo->getSRetReturnReg();
2472 MVT PtrTy = getPointerTy();
2473 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(PtrTy));
2474 FuncInfo->setSRetReturnReg(Reg);
2476 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, InVals[i]);
2477 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain);
2482 unsigned StackSize = CCInfo.getNextStackOffset();
2483 // Align stack specially for tail calls.
2484 if (FuncIsMadeTailCallSafe(CallConv,
2485 MF.getTarget().Options.GuaranteedTailCallOpt))
2486 StackSize = GetAlignedArgumentStackSize(StackSize, DAG);
2488 // If the function takes variable number of arguments, make a frame index for
2489 // the start of the first vararg value... for expansion of llvm.va_start. We
2490 // can skip this if there are no va_start calls.
2491 if (MFI->hasVAStart() &&
2492 (Is64Bit || (CallConv != CallingConv::X86_FastCall &&
2493 CallConv != CallingConv::X86_ThisCall))) {
2494 FuncInfo->setVarArgsFrameIndex(
2495 MFI->CreateFixedObject(1, StackSize, true));
2498 MachineModuleInfo &MMI = MF.getMMI();
2499 const Function *WinEHParent = nullptr;
2500 if (IsWin64 && MMI.hasWinEHFuncInfo(Fn))
2501 WinEHParent = MMI.getWinEHParent(Fn);
2502 bool IsWinEHOutlined = WinEHParent && WinEHParent != Fn;
2503 bool IsWinEHParent = WinEHParent && WinEHParent == Fn;
2505 // Figure out if XMM registers are in use.
2506 assert(!(Subtarget->useSoftFloat() &&
2507 Fn->hasFnAttribute(Attribute::NoImplicitFloat)) &&
2508 "SSE register cannot be used when SSE is disabled!");
2510 // 64-bit calling conventions support varargs and register parameters, so we
2511 // have to do extra work to spill them in the prologue.
2512 if (Is64Bit && isVarArg && MFI->hasVAStart()) {
2513 // Find the first unallocated argument registers.
2514 ArrayRef<MCPhysReg> ArgGPRs = get64BitArgumentGPRs(CallConv, Subtarget);
2515 ArrayRef<MCPhysReg> ArgXMMs = get64BitArgumentXMMs(MF, CallConv, Subtarget);
2516 unsigned NumIntRegs = CCInfo.getFirstUnallocated(ArgGPRs);
2517 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(ArgXMMs);
2518 assert(!(NumXMMRegs && !Subtarget->hasSSE1()) &&
2519 "SSE register cannot be used when SSE is disabled!");
2521 // Gather all the live in physical registers.
2522 SmallVector<SDValue, 6> LiveGPRs;
2523 SmallVector<SDValue, 8> LiveXMMRegs;
2525 for (MCPhysReg Reg : ArgGPRs.slice(NumIntRegs)) {
2526 unsigned GPR = MF.addLiveIn(Reg, &X86::GR64RegClass);
2528 DAG.getCopyFromReg(Chain, dl, GPR, MVT::i64));
2530 if (!ArgXMMs.empty()) {
2531 unsigned AL = MF.addLiveIn(X86::AL, &X86::GR8RegClass);
2532 ALVal = DAG.getCopyFromReg(Chain, dl, AL, MVT::i8);
2533 for (MCPhysReg Reg : ArgXMMs.slice(NumXMMRegs)) {
2534 unsigned XMMReg = MF.addLiveIn(Reg, &X86::VR128RegClass);
2535 LiveXMMRegs.push_back(
2536 DAG.getCopyFromReg(Chain, dl, XMMReg, MVT::v4f32));
2541 // Get to the caller-allocated home save location. Add 8 to account
2542 // for the return address.
2543 int HomeOffset = TFI.getOffsetOfLocalArea() + 8;
2544 FuncInfo->setRegSaveFrameIndex(
2545 MFI->CreateFixedObject(1, NumIntRegs * 8 + HomeOffset, false));
2546 // Fixup to set vararg frame on shadow area (4 x i64).
2548 FuncInfo->setVarArgsFrameIndex(FuncInfo->getRegSaveFrameIndex());
2550 // For X86-64, if there are vararg parameters that are passed via
2551 // registers, then we must store them to their spots on the stack so
2552 // they may be loaded by deferencing the result of va_next.
2553 FuncInfo->setVarArgsGPOffset(NumIntRegs * 8);
2554 FuncInfo->setVarArgsFPOffset(ArgGPRs.size() * 8 + NumXMMRegs * 16);
2555 FuncInfo->setRegSaveFrameIndex(MFI->CreateStackObject(
2556 ArgGPRs.size() * 8 + ArgXMMs.size() * 16, 16, false));
2559 // Store the integer parameter registers.
2560 SmallVector<SDValue, 8> MemOps;
2561 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
2563 unsigned Offset = FuncInfo->getVarArgsGPOffset();
2564 for (SDValue Val : LiveGPRs) {
2565 SDValue FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), RSFIN,
2566 DAG.getIntPtrConstant(Offset, dl));
2568 DAG.getStore(Val.getValue(1), dl, Val, FIN,
2569 MachinePointerInfo::getFixedStack(
2570 FuncInfo->getRegSaveFrameIndex(), Offset),
2572 MemOps.push_back(Store);
2576 if (!ArgXMMs.empty() && NumXMMRegs != ArgXMMs.size()) {
2577 // Now store the XMM (fp + vector) parameter registers.
2578 SmallVector<SDValue, 12> SaveXMMOps;
2579 SaveXMMOps.push_back(Chain);
2580 SaveXMMOps.push_back(ALVal);
2581 SaveXMMOps.push_back(DAG.getIntPtrConstant(
2582 FuncInfo->getRegSaveFrameIndex(), dl));
2583 SaveXMMOps.push_back(DAG.getIntPtrConstant(
2584 FuncInfo->getVarArgsFPOffset(), dl));
2585 SaveXMMOps.insert(SaveXMMOps.end(), LiveXMMRegs.begin(),
2587 MemOps.push_back(DAG.getNode(X86ISD::VASTART_SAVE_XMM_REGS, dl,
2588 MVT::Other, SaveXMMOps));
2591 if (!MemOps.empty())
2592 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps);
2593 } else if (IsWinEHOutlined) {
2594 // Get to the caller-allocated home save location. Add 8 to account
2595 // for the return address.
2596 int HomeOffset = TFI.getOffsetOfLocalArea() + 8;
2597 FuncInfo->setRegSaveFrameIndex(MFI->CreateFixedObject(
2598 /*Size=*/1, /*SPOffset=*/HomeOffset + 8, /*Immutable=*/false));
2600 MMI.getWinEHFuncInfo(Fn)
2601 .CatchHandlerParentFrameObjIdx[const_cast<Function *>(Fn)] =
2602 FuncInfo->getRegSaveFrameIndex();
2604 // Store the second integer parameter (rdx) into rsp+16 relative to the
2605 // stack pointer at the entry of the function.
2607 DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(), getPointerTy());
2608 unsigned GPR = MF.addLiveIn(X86::RDX, &X86::GR64RegClass);
2609 SDValue Val = DAG.getCopyFromReg(Chain, dl, GPR, MVT::i64);
2610 Chain = DAG.getStore(
2611 Val.getValue(1), dl, Val, RSFIN,
2612 MachinePointerInfo::getFixedStack(FuncInfo->getRegSaveFrameIndex()),
2613 /*isVolatile=*/true, /*isNonTemporal=*/false, /*Alignment=*/0);
2616 if (isVarArg && MFI->hasMustTailInVarArgFunc()) {
2617 // Find the largest legal vector type.
2618 MVT VecVT = MVT::Other;
2619 // FIXME: Only some x86_32 calling conventions support AVX512.
2620 if (Subtarget->hasAVX512() &&
2621 (Is64Bit || (CallConv == CallingConv::X86_VectorCall ||
2622 CallConv == CallingConv::Intel_OCL_BI)))
2623 VecVT = MVT::v16f32;
2624 else if (Subtarget->hasAVX())
2626 else if (Subtarget->hasSSE2())
2629 // We forward some GPRs and some vector types.
2630 SmallVector<MVT, 2> RegParmTypes;
2631 MVT IntVT = Is64Bit ? MVT::i64 : MVT::i32;
2632 RegParmTypes.push_back(IntVT);
2633 if (VecVT != MVT::Other)
2634 RegParmTypes.push_back(VecVT);
2636 // Compute the set of forwarded registers. The rest are scratch.
2637 SmallVectorImpl<ForwardedRegister> &Forwards =
2638 FuncInfo->getForwardedMustTailRegParms();
2639 CCInfo.analyzeMustTailForwardedRegisters(Forwards, RegParmTypes, CC_X86);
2641 // Conservatively forward AL on x86_64, since it might be used for varargs.
2642 if (Is64Bit && !CCInfo.isAllocated(X86::AL)) {
2643 unsigned ALVReg = MF.addLiveIn(X86::AL, &X86::GR8RegClass);
2644 Forwards.push_back(ForwardedRegister(ALVReg, X86::AL, MVT::i8));
2647 // Copy all forwards from physical to virtual registers.
2648 for (ForwardedRegister &F : Forwards) {
2649 // FIXME: Can we use a less constrained schedule?
2650 SDValue RegVal = DAG.getCopyFromReg(Chain, dl, F.VReg, F.VT);
2651 F.VReg = MF.getRegInfo().createVirtualRegister(getRegClassFor(F.VT));
2652 Chain = DAG.getCopyToReg(Chain, dl, F.VReg, RegVal);
2656 // Some CCs need callee pop.
2657 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg,
2658 MF.getTarget().Options.GuaranteedTailCallOpt)) {
2659 FuncInfo->setBytesToPopOnReturn(StackSize); // Callee pops everything.
2661 FuncInfo->setBytesToPopOnReturn(0); // Callee pops nothing.
2662 // If this is an sret function, the return should pop the hidden pointer.
2663 if (!Is64Bit && !IsTailCallConvention(CallConv) &&
2664 !Subtarget->getTargetTriple().isOSMSVCRT() &&
2665 argsAreStructReturn(Ins) == StackStructReturn)
2666 FuncInfo->setBytesToPopOnReturn(4);
2670 // RegSaveFrameIndex is X86-64 only.
2671 FuncInfo->setRegSaveFrameIndex(0xAAAAAAA);
2672 if (CallConv == CallingConv::X86_FastCall ||
2673 CallConv == CallingConv::X86_ThisCall)
2674 // fastcc functions can't have varargs.
2675 FuncInfo->setVarArgsFrameIndex(0xAAAAAAA);
2678 FuncInfo->setArgumentStackSize(StackSize);
2680 if (IsWinEHParent) {
2681 int UnwindHelpFI = MFI->CreateStackObject(8, 8, /*isSS=*/false);
2682 SDValue StackSlot = DAG.getFrameIndex(UnwindHelpFI, MVT::i64);
2683 MMI.getWinEHFuncInfo(MF.getFunction()).UnwindHelpFrameIdx = UnwindHelpFI;
2684 SDValue Neg2 = DAG.getConstant(-2, dl, MVT::i64);
2685 Chain = DAG.getStore(Chain, dl, Neg2, StackSlot,
2686 MachinePointerInfo::getFixedStack(UnwindHelpFI),
2687 /*isVolatile=*/true,
2688 /*isNonTemporal=*/false, /*Alignment=*/0);
2695 X86TargetLowering::LowerMemOpCallTo(SDValue Chain,
2696 SDValue StackPtr, SDValue Arg,
2697 SDLoc dl, SelectionDAG &DAG,
2698 const CCValAssign &VA,
2699 ISD::ArgFlagsTy Flags) const {
2700 unsigned LocMemOffset = VA.getLocMemOffset();
2701 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset, dl);
2702 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
2703 if (Flags.isByVal())
2704 return CreateCopyOfByValArgument(Arg, PtrOff, Chain, Flags, DAG, dl);
2706 return DAG.getStore(Chain, dl, Arg, PtrOff,
2707 MachinePointerInfo::getStack(LocMemOffset),
2711 /// Emit a load of return address if tail call
2712 /// optimization is performed and it is required.
2714 X86TargetLowering::EmitTailCallLoadRetAddr(SelectionDAG &DAG,
2715 SDValue &OutRetAddr, SDValue Chain,
2716 bool IsTailCall, bool Is64Bit,
2717 int FPDiff, SDLoc dl) const {
2718 // Adjust the Return address stack slot.
2719 EVT VT = getPointerTy();
2720 OutRetAddr = getReturnAddressFrameIndex(DAG);
2722 // Load the "old" Return address.
2723 OutRetAddr = DAG.getLoad(VT, dl, Chain, OutRetAddr, MachinePointerInfo(),
2724 false, false, false, 0);
2725 return SDValue(OutRetAddr.getNode(), 1);
2728 /// Emit a store of the return address if tail call
2729 /// optimization is performed and it is required (FPDiff!=0).
2730 static SDValue EmitTailCallStoreRetAddr(SelectionDAG &DAG, MachineFunction &MF,
2731 SDValue Chain, SDValue RetAddrFrIdx,
2732 EVT PtrVT, unsigned SlotSize,
2733 int FPDiff, SDLoc dl) {
2734 // Store the return address to the appropriate stack slot.
2735 if (!FPDiff) return Chain;
2736 // Calculate the new stack slot for the return address.
2737 int NewReturnAddrFI =
2738 MF.getFrameInfo()->CreateFixedObject(SlotSize, (int64_t)FPDiff - SlotSize,
2740 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewReturnAddrFI, PtrVT);
2741 Chain = DAG.getStore(Chain, dl, RetAddrFrIdx, NewRetAddrFrIdx,
2742 MachinePointerInfo::getFixedStack(NewReturnAddrFI),
2748 X86TargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
2749 SmallVectorImpl<SDValue> &InVals) const {
2750 SelectionDAG &DAG = CLI.DAG;
2752 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
2753 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
2754 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
2755 SDValue Chain = CLI.Chain;
2756 SDValue Callee = CLI.Callee;
2757 CallingConv::ID CallConv = CLI.CallConv;
2758 bool &isTailCall = CLI.IsTailCall;
2759 bool isVarArg = CLI.IsVarArg;
2761 MachineFunction &MF = DAG.getMachineFunction();
2762 bool Is64Bit = Subtarget->is64Bit();
2763 bool IsWin64 = Subtarget->isCallingConvWin64(CallConv);
2764 StructReturnType SR = callIsStructReturn(Outs);
2765 bool IsSibcall = false;
2766 X86MachineFunctionInfo *X86Info = MF.getInfo<X86MachineFunctionInfo>();
2767 auto Attr = MF.getFunction()->getFnAttribute("disable-tail-calls");
2769 if (Attr.getValueAsString() == "true")
2772 if (Subtarget->isPICStyleGOT() &&
2773 !MF.getTarget().Options.GuaranteedTailCallOpt) {
2774 // If we are using a GOT, disable tail calls to external symbols with
2775 // default visibility. Tail calling such a symbol requires using a GOT
2776 // relocation, which forces early binding of the symbol. This breaks code
2777 // that require lazy function symbol resolution. Using musttail or
2778 // GuaranteedTailCallOpt will override this.
2779 GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee);
2780 if (!G || (!G->getGlobal()->hasLocalLinkage() &&
2781 G->getGlobal()->hasDefaultVisibility()))
2785 bool IsMustTail = CLI.CS && CLI.CS->isMustTailCall();
2787 // Force this to be a tail call. The verifier rules are enough to ensure
2788 // that we can lower this successfully without moving the return address
2791 } else if (isTailCall) {
2792 // Check if it's really possible to do a tail call.
2793 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv,
2794 isVarArg, SR != NotStructReturn,
2795 MF.getFunction()->hasStructRetAttr(), CLI.RetTy,
2796 Outs, OutVals, Ins, DAG);
2798 // Sibcalls are automatically detected tailcalls which do not require
2800 if (!MF.getTarget().Options.GuaranteedTailCallOpt && isTailCall)
2807 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
2808 "Var args not supported with calling convention fastcc, ghc or hipe");
2810 // Analyze operands of the call, assigning locations to each operand.
2811 SmallVector<CCValAssign, 16> ArgLocs;
2812 CCState CCInfo(CallConv, isVarArg, MF, ArgLocs, *DAG.getContext());
2814 // Allocate shadow area for Win64
2816 CCInfo.AllocateStack(32, 8);
2818 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
2820 // Get a count of how many bytes are to be pushed on the stack.
2821 unsigned NumBytes = CCInfo.getNextStackOffset();
2823 // This is a sibcall. The memory operands are available in caller's
2824 // own caller's stack.
2826 else if (MF.getTarget().Options.GuaranteedTailCallOpt &&
2827 IsTailCallConvention(CallConv))
2828 NumBytes = GetAlignedArgumentStackSize(NumBytes, DAG);
2831 if (isTailCall && !IsSibcall && !IsMustTail) {
2832 // Lower arguments at fp - stackoffset + fpdiff.
2833 unsigned NumBytesCallerPushed = X86Info->getBytesToPopOnReturn();
2835 FPDiff = NumBytesCallerPushed - NumBytes;
2837 // Set the delta of movement of the returnaddr stackslot.
2838 // But only set if delta is greater than previous delta.
2839 if (FPDiff < X86Info->getTCReturnAddrDelta())
2840 X86Info->setTCReturnAddrDelta(FPDiff);
2843 unsigned NumBytesToPush = NumBytes;
2844 unsigned NumBytesToPop = NumBytes;
2846 // If we have an inalloca argument, all stack space has already been allocated
2847 // for us and be right at the top of the stack. We don't support multiple
2848 // arguments passed in memory when using inalloca.
2849 if (!Outs.empty() && Outs.back().Flags.isInAlloca()) {
2851 if (!ArgLocs.back().isMemLoc())
2852 report_fatal_error("cannot use inalloca attribute on a register "
2854 if (ArgLocs.back().getLocMemOffset() != 0)
2855 report_fatal_error("any parameter with the inalloca attribute must be "
2856 "the only memory argument");
2860 Chain = DAG.getCALLSEQ_START(
2861 Chain, DAG.getIntPtrConstant(NumBytesToPush, dl, true), dl);
2863 SDValue RetAddrFrIdx;
2864 // Load return address for tail calls.
2865 if (isTailCall && FPDiff)
2866 Chain = EmitTailCallLoadRetAddr(DAG, RetAddrFrIdx, Chain, isTailCall,
2867 Is64Bit, FPDiff, dl);
2869 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
2870 SmallVector<SDValue, 8> MemOpChains;
2873 // Walk the register/memloc assignments, inserting copies/loads. In the case
2874 // of tail call optimization arguments are handle later.
2875 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
2876 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2877 // Skip inalloca arguments, they have already been written.
2878 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2879 if (Flags.isInAlloca())
2882 CCValAssign &VA = ArgLocs[i];
2883 EVT RegVT = VA.getLocVT();
2884 SDValue Arg = OutVals[i];
2885 bool isByVal = Flags.isByVal();
2887 // Promote the value if needed.
2888 switch (VA.getLocInfo()) {
2889 default: llvm_unreachable("Unknown loc info!");
2890 case CCValAssign::Full: break;
2891 case CCValAssign::SExt:
2892 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, RegVT, Arg);
2894 case CCValAssign::ZExt:
2895 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, RegVT, Arg);
2897 case CCValAssign::AExt:
2898 if (Arg.getValueType().isVector() &&
2899 Arg.getValueType().getScalarType() == MVT::i1)
2900 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, RegVT, Arg);
2901 else if (RegVT.is128BitVector()) {
2902 // Special case: passing MMX values in XMM registers.
2903 Arg = DAG.getBitcast(MVT::i64, Arg);
2904 Arg = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, Arg);
2905 Arg = getMOVL(DAG, dl, MVT::v2i64, DAG.getUNDEF(MVT::v2i64), Arg);
2907 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, RegVT, Arg);
2909 case CCValAssign::BCvt:
2910 Arg = DAG.getBitcast(RegVT, Arg);
2912 case CCValAssign::Indirect: {
2913 // Store the argument.
2914 SDValue SpillSlot = DAG.CreateStackTemporary(VA.getValVT());
2915 int FI = cast<FrameIndexSDNode>(SpillSlot)->getIndex();
2916 Chain = DAG.getStore(Chain, dl, Arg, SpillSlot,
2917 MachinePointerInfo::getFixedStack(FI),
2924 if (VA.isRegLoc()) {
2925 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
2926 if (isVarArg && IsWin64) {
2927 // Win64 ABI requires argument XMM reg to be copied to the corresponding
2928 // shadow reg if callee is a varargs function.
2929 unsigned ShadowReg = 0;
2930 switch (VA.getLocReg()) {
2931 case X86::XMM0: ShadowReg = X86::RCX; break;
2932 case X86::XMM1: ShadowReg = X86::RDX; break;
2933 case X86::XMM2: ShadowReg = X86::R8; break;
2934 case X86::XMM3: ShadowReg = X86::R9; break;
2937 RegsToPass.push_back(std::make_pair(ShadowReg, Arg));
2939 } else if (!IsSibcall && (!isTailCall || isByVal)) {
2940 assert(VA.isMemLoc());
2941 if (!StackPtr.getNode())
2942 StackPtr = DAG.getCopyFromReg(Chain, dl, RegInfo->getStackRegister(),
2944 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Arg,
2945 dl, DAG, VA, Flags));
2949 if (!MemOpChains.empty())
2950 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains);
2952 if (Subtarget->isPICStyleGOT()) {
2953 // ELF / PIC requires GOT in the EBX register before function calls via PLT
2956 RegsToPass.push_back(std::make_pair(unsigned(X86::EBX),
2957 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), getPointerTy())));
2959 // If we are tail calling and generating PIC/GOT style code load the
2960 // address of the callee into ECX. The value in ecx is used as target of
2961 // the tail jump. This is done to circumvent the ebx/callee-saved problem
2962 // for tail calls on PIC/GOT architectures. Normally we would just put the
2963 // address of GOT into ebx and then call target@PLT. But for tail calls
2964 // ebx would be restored (since ebx is callee saved) before jumping to the
2967 // Note: The actual moving to ECX is done further down.
2968 GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee);
2969 if (G && !G->getGlobal()->hasLocalLinkage() &&
2970 G->getGlobal()->hasDefaultVisibility())
2971 Callee = LowerGlobalAddress(Callee, DAG);
2972 else if (isa<ExternalSymbolSDNode>(Callee))
2973 Callee = LowerExternalSymbol(Callee, DAG);
2977 if (Is64Bit && isVarArg && !IsWin64 && !IsMustTail) {
2978 // From AMD64 ABI document:
2979 // For calls that may call functions that use varargs or stdargs
2980 // (prototype-less calls or calls to functions containing ellipsis (...) in
2981 // the declaration) %al is used as hidden argument to specify the number
2982 // of SSE registers used. The contents of %al do not need to match exactly
2983 // the number of registers, but must be an ubound on the number of SSE
2984 // registers used and is in the range 0 - 8 inclusive.
2986 // Count the number of XMM registers allocated.
2987 static const MCPhysReg XMMArgRegs[] = {
2988 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
2989 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
2991 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs);
2992 assert((Subtarget->hasSSE1() || !NumXMMRegs)
2993 && "SSE registers cannot be used when SSE is disabled");
2995 RegsToPass.push_back(std::make_pair(unsigned(X86::AL),
2996 DAG.getConstant(NumXMMRegs, dl,
3000 if (isVarArg && IsMustTail) {
3001 const auto &Forwards = X86Info->getForwardedMustTailRegParms();
3002 for (const auto &F : Forwards) {
3003 SDValue Val = DAG.getCopyFromReg(Chain, dl, F.VReg, F.VT);
3004 RegsToPass.push_back(std::make_pair(unsigned(F.PReg), Val));
3008 // For tail calls lower the arguments to the 'real' stack slots. Sibcalls
3009 // don't need this because the eligibility check rejects calls that require
3010 // shuffling arguments passed in memory.
3011 if (!IsSibcall && isTailCall) {
3012 // Force all the incoming stack arguments to be loaded from the stack
3013 // before any new outgoing arguments are stored to the stack, because the
3014 // outgoing stack slots may alias the incoming argument stack slots, and
3015 // the alias isn't otherwise explicit. This is slightly more conservative
3016 // than necessary, because it means that each store effectively depends
3017 // on every argument instead of just those arguments it would clobber.
3018 SDValue ArgChain = DAG.getStackArgumentTokenFactor(Chain);
3020 SmallVector<SDValue, 8> MemOpChains2;
3023 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3024 CCValAssign &VA = ArgLocs[i];
3027 assert(VA.isMemLoc());
3028 SDValue Arg = OutVals[i];
3029 ISD::ArgFlagsTy Flags = Outs[i].Flags;
3030 // Skip inalloca arguments. They don't require any work.
3031 if (Flags.isInAlloca())
3033 // Create frame index.
3034 int32_t Offset = VA.getLocMemOffset()+FPDiff;
3035 uint32_t OpSize = (VA.getLocVT().getSizeInBits()+7)/8;
3036 FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true);
3037 FIN = DAG.getFrameIndex(FI, getPointerTy());
3039 if (Flags.isByVal()) {
3040 // Copy relative to framepointer.
3041 SDValue Source = DAG.getIntPtrConstant(VA.getLocMemOffset(), dl);
3042 if (!StackPtr.getNode())
3043 StackPtr = DAG.getCopyFromReg(Chain, dl,
3044 RegInfo->getStackRegister(),
3046 Source = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, Source);
3048 MemOpChains2.push_back(CreateCopyOfByValArgument(Source, FIN,
3052 // Store relative to framepointer.
3053 MemOpChains2.push_back(
3054 DAG.getStore(ArgChain, dl, Arg, FIN,
3055 MachinePointerInfo::getFixedStack(FI),
3060 if (!MemOpChains2.empty())
3061 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains2);
3063 // Store the return address to the appropriate stack slot.
3064 Chain = EmitTailCallStoreRetAddr(DAG, MF, Chain, RetAddrFrIdx,
3065 getPointerTy(), RegInfo->getSlotSize(),
3069 // Build a sequence of copy-to-reg nodes chained together with token chain
3070 // and flag operands which copy the outgoing args into registers.
3072 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
3073 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
3074 RegsToPass[i].second, InFlag);
3075 InFlag = Chain.getValue(1);
3078 if (DAG.getTarget().getCodeModel() == CodeModel::Large) {
3079 assert(Is64Bit && "Large code model is only legal in 64-bit mode.");
3080 // In the 64-bit large code model, we have to make all calls
3081 // through a register, since the call instruction's 32-bit
3082 // pc-relative offset may not be large enough to hold the whole
3084 } else if (Callee->getOpcode() == ISD::GlobalAddress) {
3085 // If the callee is a GlobalAddress node (quite common, every direct call
3086 // is) turn it into a TargetGlobalAddress node so that legalize doesn't hack
3088 GlobalAddressSDNode* G = cast<GlobalAddressSDNode>(Callee);
3090 // We should use extra load for direct calls to dllimported functions in
3092 const GlobalValue *GV = G->getGlobal();
3093 if (!GV->hasDLLImportStorageClass()) {
3094 unsigned char OpFlags = 0;
3095 bool ExtraLoad = false;
3096 unsigned WrapperKind = ISD::DELETED_NODE;
3098 // On ELF targets, in both X86-64 and X86-32 mode, direct calls to
3099 // external symbols most go through the PLT in PIC mode. If the symbol
3100 // has hidden or protected visibility, or if it is static or local, then
3101 // we don't need to use the PLT - we can directly call it.
3102 if (Subtarget->isTargetELF() &&
3103 DAG.getTarget().getRelocationModel() == Reloc::PIC_ &&
3104 GV->hasDefaultVisibility() && !GV->hasLocalLinkage()) {
3105 OpFlags = X86II::MO_PLT;
3106 } else if (Subtarget->isPICStyleStubAny() &&
3107 (GV->isDeclaration() || GV->isWeakForLinker()) &&
3108 (!Subtarget->getTargetTriple().isMacOSX() ||
3109 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
3110 // PC-relative references to external symbols should go through $stub,
3111 // unless we're building with the leopard linker or later, which
3112 // automatically synthesizes these stubs.
3113 OpFlags = X86II::MO_DARWIN_STUB;
3114 } else if (Subtarget->isPICStyleRIPRel() && isa<Function>(GV) &&
3115 cast<Function>(GV)->hasFnAttribute(Attribute::NonLazyBind)) {
3116 // If the function is marked as non-lazy, generate an indirect call
3117 // which loads from the GOT directly. This avoids runtime overhead
3118 // at the cost of eager binding (and one extra byte of encoding).
3119 OpFlags = X86II::MO_GOTPCREL;
3120 WrapperKind = X86ISD::WrapperRIP;
3124 Callee = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(),
3125 G->getOffset(), OpFlags);
3127 // Add a wrapper if needed.
3128 if (WrapperKind != ISD::DELETED_NODE)
3129 Callee = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Callee);
3130 // Add extra indirection if needed.
3132 Callee = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Callee,
3133 MachinePointerInfo::getGOT(),
3134 false, false, false, 0);
3136 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
3137 unsigned char OpFlags = 0;
3139 // On ELF targets, in either X86-64 or X86-32 mode, direct calls to
3140 // external symbols should go through the PLT.
3141 if (Subtarget->isTargetELF() &&
3142 DAG.getTarget().getRelocationModel() == Reloc::PIC_) {
3143 OpFlags = X86II::MO_PLT;
3144 } else if (Subtarget->isPICStyleStubAny() &&
3145 (!Subtarget->getTargetTriple().isMacOSX() ||
3146 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
3147 // PC-relative references to external symbols should go through $stub,
3148 // unless we're building with the leopard linker or later, which
3149 // automatically synthesizes these stubs.
3150 OpFlags = X86II::MO_DARWIN_STUB;
3153 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy(),
3155 } else if (Subtarget->isTarget64BitILP32() &&
3156 Callee->getValueType(0) == MVT::i32) {
3157 // Zero-extend the 32-bit Callee address into a 64-bit according to x32 ABI
3158 Callee = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i64, Callee);
3161 // Returns a chain & a flag for retval copy to use.
3162 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
3163 SmallVector<SDValue, 8> Ops;
3165 if (!IsSibcall && isTailCall) {
3166 Chain = DAG.getCALLSEQ_END(Chain,
3167 DAG.getIntPtrConstant(NumBytesToPop, dl, true),
3168 DAG.getIntPtrConstant(0, dl, true), InFlag, dl);
3169 InFlag = Chain.getValue(1);
3172 Ops.push_back(Chain);
3173 Ops.push_back(Callee);
3176 Ops.push_back(DAG.getConstant(FPDiff, dl, MVT::i32));
3178 // Add argument registers to the end of the list so that they are known live
3180 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
3181 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
3182 RegsToPass[i].second.getValueType()));
3184 // Add a register mask operand representing the call-preserved registers.
3185 const TargetRegisterInfo *TRI = Subtarget->getRegisterInfo();
3186 const uint32_t *Mask = TRI->getCallPreservedMask(MF, CallConv);
3187 assert(Mask && "Missing call preserved mask for calling convention");
3188 Ops.push_back(DAG.getRegisterMask(Mask));
3190 if (InFlag.getNode())
3191 Ops.push_back(InFlag);
3195 //// If this is the first return lowered for this function, add the regs
3196 //// to the liveout set for the function.
3197 // This isn't right, although it's probably harmless on x86; liveouts
3198 // should be computed from returns not tail calls. Consider a void
3199 // function making a tail call to a function returning int.
3200 MF.getFrameInfo()->setHasTailCall();
3201 return DAG.getNode(X86ISD::TC_RETURN, dl, NodeTys, Ops);
3204 Chain = DAG.getNode(X86ISD::CALL, dl, NodeTys, Ops);
3205 InFlag = Chain.getValue(1);
3207 // Create the CALLSEQ_END node.
3208 unsigned NumBytesForCalleeToPop;
3209 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg,
3210 DAG.getTarget().Options.GuaranteedTailCallOpt))
3211 NumBytesForCalleeToPop = NumBytes; // Callee pops everything
3212 else if (!Is64Bit && !IsTailCallConvention(CallConv) &&
3213 !Subtarget->getTargetTriple().isOSMSVCRT() &&
3214 SR == StackStructReturn)
3215 // If this is a call to a struct-return function, the callee
3216 // pops the hidden struct pointer, so we have to push it back.
3217 // This is common for Darwin/X86, Linux & Mingw32 targets.
3218 // For MSVC Win32 targets, the caller pops the hidden struct pointer.
3219 NumBytesForCalleeToPop = 4;
3221 NumBytesForCalleeToPop = 0; // Callee pops nothing.
3223 // Returns a flag for retval copy to use.
3225 Chain = DAG.getCALLSEQ_END(Chain,
3226 DAG.getIntPtrConstant(NumBytesToPop, dl, true),
3227 DAG.getIntPtrConstant(NumBytesForCalleeToPop, dl,
3230 InFlag = Chain.getValue(1);
3233 // Handle result values, copying them out of physregs into vregs that we
3235 return LowerCallResult(Chain, InFlag, CallConv, isVarArg,
3236 Ins, dl, DAG, InVals);
3239 //===----------------------------------------------------------------------===//
3240 // Fast Calling Convention (tail call) implementation
3241 //===----------------------------------------------------------------------===//
3243 // Like std call, callee cleans arguments, convention except that ECX is
3244 // reserved for storing the tail called function address. Only 2 registers are
3245 // free for argument passing (inreg). Tail call optimization is performed
3247 // * tailcallopt is enabled
3248 // * caller/callee are fastcc
3249 // On X86_64 architecture with GOT-style position independent code only local
3250 // (within module) calls are supported at the moment.
3251 // To keep the stack aligned according to platform abi the function
3252 // GetAlignedArgumentStackSize ensures that argument delta is always multiples
3253 // of stack alignment. (Dynamic linkers need this - darwin's dyld for example)
3254 // If a tail called function callee has more arguments than the caller the
3255 // caller needs to make sure that there is room to move the RETADDR to. This is
3256 // achieved by reserving an area the size of the argument delta right after the
3257 // original RETADDR, but before the saved framepointer or the spilled registers
3258 // e.g. caller(arg1, arg2) calls callee(arg1, arg2,arg3,arg4)
3270 /// GetAlignedArgumentStackSize - Make the stack size align e.g 16n + 12 aligned
3271 /// for a 16 byte align requirement.
3273 X86TargetLowering::GetAlignedArgumentStackSize(unsigned StackSize,
3274 SelectionDAG& DAG) const {
3275 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
3276 const TargetFrameLowering &TFI = *Subtarget->getFrameLowering();
3277 unsigned StackAlignment = TFI.getStackAlignment();
3278 uint64_t AlignMask = StackAlignment - 1;
3279 int64_t Offset = StackSize;
3280 unsigned SlotSize = RegInfo->getSlotSize();
3281 if ( (Offset & AlignMask) <= (StackAlignment - SlotSize) ) {
3282 // Number smaller than 12 so just add the difference.
3283 Offset += ((StackAlignment - SlotSize) - (Offset & AlignMask));
3285 // Mask out lower bits, add stackalignment once plus the 12 bytes.
3286 Offset = ((~AlignMask) & Offset) + StackAlignment +
3287 (StackAlignment-SlotSize);
3292 /// MatchingStackOffset - Return true if the given stack call argument is
3293 /// already available in the same position (relatively) of the caller's
3294 /// incoming argument stack.
3296 bool MatchingStackOffset(SDValue Arg, unsigned Offset, ISD::ArgFlagsTy Flags,
3297 MachineFrameInfo *MFI, const MachineRegisterInfo *MRI,
3298 const X86InstrInfo *TII) {
3299 unsigned Bytes = Arg.getValueType().getSizeInBits() / 8;
3301 if (Arg.getOpcode() == ISD::CopyFromReg) {
3302 unsigned VR = cast<RegisterSDNode>(Arg.getOperand(1))->getReg();
3303 if (!TargetRegisterInfo::isVirtualRegister(VR))
3305 MachineInstr *Def = MRI->getVRegDef(VR);
3308 if (!Flags.isByVal()) {
3309 if (!TII->isLoadFromStackSlot(Def, FI))
3312 unsigned Opcode = Def->getOpcode();
3313 if ((Opcode == X86::LEA32r || Opcode == X86::LEA64r ||
3314 Opcode == X86::LEA64_32r) &&
3315 Def->getOperand(1).isFI()) {
3316 FI = Def->getOperand(1).getIndex();
3317 Bytes = Flags.getByValSize();
3321 } else if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Arg)) {
3322 if (Flags.isByVal())
3323 // ByVal argument is passed in as a pointer but it's now being
3324 // dereferenced. e.g.
3325 // define @foo(%struct.X* %A) {
3326 // tail call @bar(%struct.X* byval %A)
3329 SDValue Ptr = Ld->getBasePtr();
3330 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr);
3333 FI = FINode->getIndex();
3334 } else if (Arg.getOpcode() == ISD::FrameIndex && Flags.isByVal()) {
3335 FrameIndexSDNode *FINode = cast<FrameIndexSDNode>(Arg);
3336 FI = FINode->getIndex();
3337 Bytes = Flags.getByValSize();
3341 assert(FI != INT_MAX);
3342 if (!MFI->isFixedObjectIndex(FI))
3344 return Offset == MFI->getObjectOffset(FI) && Bytes == MFI->getObjectSize(FI);
3347 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
3348 /// for tail call optimization. Targets which want to do tail call
3349 /// optimization should implement this function.
3351 X86TargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
3352 CallingConv::ID CalleeCC,
3354 bool isCalleeStructRet,
3355 bool isCallerStructRet,
3357 const SmallVectorImpl<ISD::OutputArg> &Outs,
3358 const SmallVectorImpl<SDValue> &OutVals,
3359 const SmallVectorImpl<ISD::InputArg> &Ins,
3360 SelectionDAG &DAG) const {
3361 if (!IsTailCallConvention(CalleeCC) && !IsCCallConvention(CalleeCC))
3364 // If -tailcallopt is specified, make fastcc functions tail-callable.
3365 const MachineFunction &MF = DAG.getMachineFunction();
3366 const Function *CallerF = MF.getFunction();
3368 // If the function return type is x86_fp80 and the callee return type is not,
3369 // then the FP_EXTEND of the call result is not a nop. It's not safe to
3370 // perform a tailcall optimization here.
3371 if (CallerF->getReturnType()->isX86_FP80Ty() && !RetTy->isX86_FP80Ty())
3374 CallingConv::ID CallerCC = CallerF->getCallingConv();
3375 bool CCMatch = CallerCC == CalleeCC;
3376 bool IsCalleeWin64 = Subtarget->isCallingConvWin64(CalleeCC);
3377 bool IsCallerWin64 = Subtarget->isCallingConvWin64(CallerCC);
3379 // Win64 functions have extra shadow space for argument homing. Don't do the
3380 // sibcall if the caller and callee have mismatched expectations for this
3382 if (IsCalleeWin64 != IsCallerWin64)
3385 if (DAG.getTarget().Options.GuaranteedTailCallOpt) {
3386 if (IsTailCallConvention(CalleeCC) && CCMatch)
3391 // Look for obvious safe cases to perform tail call optimization that do not
3392 // require ABI changes. This is what gcc calls sibcall.
3394 // Can't do sibcall if stack needs to be dynamically re-aligned. PEI needs to
3395 // emit a special epilogue.
3396 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
3397 if (RegInfo->needsStackRealignment(MF))
3400 // Also avoid sibcall optimization if either caller or callee uses struct
3401 // return semantics.
3402 if (isCalleeStructRet || isCallerStructRet)
3405 // An stdcall/thiscall caller is expected to clean up its arguments; the
3406 // callee isn't going to do that.
3407 // FIXME: this is more restrictive than needed. We could produce a tailcall
3408 // when the stack adjustment matches. For example, with a thiscall that takes
3409 // only one argument.
3410 if (!CCMatch && (CallerCC == CallingConv::X86_StdCall ||
3411 CallerCC == CallingConv::X86_ThisCall))
3414 // Do not sibcall optimize vararg calls unless all arguments are passed via
3416 if (isVarArg && !Outs.empty()) {
3418 // Optimizing for varargs on Win64 is unlikely to be safe without
3419 // additional testing.
3420 if (IsCalleeWin64 || IsCallerWin64)
3423 SmallVector<CCValAssign, 16> ArgLocs;
3424 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(), ArgLocs,
3427 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
3428 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i)
3429 if (!ArgLocs[i].isRegLoc())
3433 // If the call result is in ST0 / ST1, it needs to be popped off the x87
3434 // stack. Therefore, if it's not used by the call it is not safe to optimize
3435 // this into a sibcall.
3436 bool Unused = false;
3437 for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
3444 SmallVector<CCValAssign, 16> RVLocs;
3445 CCState CCInfo(CalleeCC, false, DAG.getMachineFunction(), RVLocs,
3447 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
3448 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
3449 CCValAssign &VA = RVLocs[i];
3450 if (VA.getLocReg() == X86::FP0 || VA.getLocReg() == X86::FP1)
3455 // If the calling conventions do not match, then we'd better make sure the
3456 // results are returned in the same way as what the caller expects.
3458 SmallVector<CCValAssign, 16> RVLocs1;
3459 CCState CCInfo1(CalleeCC, false, DAG.getMachineFunction(), RVLocs1,
3461 CCInfo1.AnalyzeCallResult(Ins, RetCC_X86);
3463 SmallVector<CCValAssign, 16> RVLocs2;
3464 CCState CCInfo2(CallerCC, false, DAG.getMachineFunction(), RVLocs2,
3466 CCInfo2.AnalyzeCallResult(Ins, RetCC_X86);
3468 if (RVLocs1.size() != RVLocs2.size())
3470 for (unsigned i = 0, e = RVLocs1.size(); i != e; ++i) {
3471 if (RVLocs1[i].isRegLoc() != RVLocs2[i].isRegLoc())
3473 if (RVLocs1[i].getLocInfo() != RVLocs2[i].getLocInfo())
3475 if (RVLocs1[i].isRegLoc()) {
3476 if (RVLocs1[i].getLocReg() != RVLocs2[i].getLocReg())
3479 if (RVLocs1[i].getLocMemOffset() != RVLocs2[i].getLocMemOffset())
3485 // If the callee takes no arguments then go on to check the results of the
3487 if (!Outs.empty()) {
3488 // Check if stack adjustment is needed. For now, do not do this if any
3489 // argument is passed on the stack.
3490 SmallVector<CCValAssign, 16> ArgLocs;
3491 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(), ArgLocs,
3494 // Allocate shadow area for Win64
3496 CCInfo.AllocateStack(32, 8);
3498 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
3499 if (CCInfo.getNextStackOffset()) {
3500 MachineFunction &MF = DAG.getMachineFunction();
3501 if (MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn())
3504 // Check if the arguments are already laid out in the right way as
3505 // the caller's fixed stack objects.
3506 MachineFrameInfo *MFI = MF.getFrameInfo();
3507 const MachineRegisterInfo *MRI = &MF.getRegInfo();
3508 const X86InstrInfo *TII = Subtarget->getInstrInfo();
3509 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3510 CCValAssign &VA = ArgLocs[i];
3511 SDValue Arg = OutVals[i];
3512 ISD::ArgFlagsTy Flags = Outs[i].Flags;
3513 if (VA.getLocInfo() == CCValAssign::Indirect)
3515 if (!VA.isRegLoc()) {
3516 if (!MatchingStackOffset(Arg, VA.getLocMemOffset(), Flags,
3523 // If the tailcall address may be in a register, then make sure it's
3524 // possible to register allocate for it. In 32-bit, the call address can
3525 // only target EAX, EDX, or ECX since the tail call must be scheduled after
3526 // callee-saved registers are restored. These happen to be the same
3527 // registers used to pass 'inreg' arguments so watch out for those.
3528 if (!Subtarget->is64Bit() &&
3529 ((!isa<GlobalAddressSDNode>(Callee) &&
3530 !isa<ExternalSymbolSDNode>(Callee)) ||
3531 DAG.getTarget().getRelocationModel() == Reloc::PIC_)) {
3532 unsigned NumInRegs = 0;
3533 // In PIC we need an extra register to formulate the address computation
3535 unsigned MaxInRegs =
3536 (DAG.getTarget().getRelocationModel() == Reloc::PIC_) ? 2 : 3;
3538 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3539 CCValAssign &VA = ArgLocs[i];
3542 unsigned Reg = VA.getLocReg();
3545 case X86::EAX: case X86::EDX: case X86::ECX:
3546 if (++NumInRegs == MaxInRegs)
3558 X86TargetLowering::createFastISel(FunctionLoweringInfo &funcInfo,
3559 const TargetLibraryInfo *libInfo) const {
3560 return X86::createFastISel(funcInfo, libInfo);
3563 //===----------------------------------------------------------------------===//
3564 // Other Lowering Hooks
3565 //===----------------------------------------------------------------------===//
3567 static bool MayFoldLoad(SDValue Op) {
3568 return Op.hasOneUse() && ISD::isNormalLoad(Op.getNode());
3571 static bool MayFoldIntoStore(SDValue Op) {
3572 return Op.hasOneUse() && ISD::isNormalStore(*Op.getNode()->use_begin());
3575 static bool isTargetShuffle(unsigned Opcode) {
3577 default: return false;
3578 case X86ISD::BLENDI:
3579 case X86ISD::PSHUFB:
3580 case X86ISD::PSHUFD:
3581 case X86ISD::PSHUFHW:
3582 case X86ISD::PSHUFLW:
3584 case X86ISD::PALIGNR:
3585 case X86ISD::MOVLHPS:
3586 case X86ISD::MOVLHPD:
3587 case X86ISD::MOVHLPS:
3588 case X86ISD::MOVLPS:
3589 case X86ISD::MOVLPD:
3590 case X86ISD::MOVSHDUP:
3591 case X86ISD::MOVSLDUP:
3592 case X86ISD::MOVDDUP:
3595 case X86ISD::UNPCKL:
3596 case X86ISD::UNPCKH:
3597 case X86ISD::VPERMILPI:
3598 case X86ISD::VPERM2X128:
3599 case X86ISD::VPERMI:
3604 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3605 SDValue V1, unsigned TargetMask,
3606 SelectionDAG &DAG) {
3608 default: llvm_unreachable("Unknown x86 shuffle node");
3609 case X86ISD::PSHUFD:
3610 case X86ISD::PSHUFHW:
3611 case X86ISD::PSHUFLW:
3612 case X86ISD::VPERMILPI:
3613 case X86ISD::VPERMI:
3614 return DAG.getNode(Opc, dl, VT, V1,
3615 DAG.getConstant(TargetMask, dl, MVT::i8));
3619 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3620 SDValue V1, SDValue V2, SelectionDAG &DAG) {
3622 default: llvm_unreachable("Unknown x86 shuffle node");
3623 case X86ISD::MOVLHPS:
3624 case X86ISD::MOVLHPD:
3625 case X86ISD::MOVHLPS:
3626 case X86ISD::MOVLPS:
3627 case X86ISD::MOVLPD:
3630 case X86ISD::UNPCKL:
3631 case X86ISD::UNPCKH:
3632 return DAG.getNode(Opc, dl, VT, V1, V2);
3636 SDValue X86TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) const {
3637 MachineFunction &MF = DAG.getMachineFunction();
3638 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
3639 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
3640 int ReturnAddrIndex = FuncInfo->getRAIndex();
3642 if (ReturnAddrIndex == 0) {
3643 // Set up a frame object for the return address.
3644 unsigned SlotSize = RegInfo->getSlotSize();
3645 ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(SlotSize,
3648 FuncInfo->setRAIndex(ReturnAddrIndex);
3651 return DAG.getFrameIndex(ReturnAddrIndex, getPointerTy());
3654 bool X86::isOffsetSuitableForCodeModel(int64_t Offset, CodeModel::Model M,
3655 bool hasSymbolicDisplacement) {
3656 // Offset should fit into 32 bit immediate field.
3657 if (!isInt<32>(Offset))
3660 // If we don't have a symbolic displacement - we don't have any extra
3662 if (!hasSymbolicDisplacement)
3665 // FIXME: Some tweaks might be needed for medium code model.
3666 if (M != CodeModel::Small && M != CodeModel::Kernel)
3669 // For small code model we assume that latest object is 16MB before end of 31
3670 // bits boundary. We may also accept pretty large negative constants knowing
3671 // that all objects are in the positive half of address space.
3672 if (M == CodeModel::Small && Offset < 16*1024*1024)
3675 // For kernel code model we know that all object resist in the negative half
3676 // of 32bits address space. We may not accept negative offsets, since they may
3677 // be just off and we may accept pretty large positive ones.
3678 if (M == CodeModel::Kernel && Offset >= 0)
3684 /// isCalleePop - Determines whether the callee is required to pop its
3685 /// own arguments. Callee pop is necessary to support tail calls.
3686 bool X86::isCalleePop(CallingConv::ID CallingConv,
3687 bool is64Bit, bool IsVarArg, bool TailCallOpt) {
3688 switch (CallingConv) {
3691 case CallingConv::X86_StdCall:
3692 case CallingConv::X86_FastCall:
3693 case CallingConv::X86_ThisCall:
3695 case CallingConv::Fast:
3696 case CallingConv::GHC:
3697 case CallingConv::HiPE:
3704 /// \brief Return true if the condition is an unsigned comparison operation.
3705 static bool isX86CCUnsigned(unsigned X86CC) {
3707 default: llvm_unreachable("Invalid integer condition!");
3708 case X86::COND_E: return true;
3709 case X86::COND_G: return false;
3710 case X86::COND_GE: return false;
3711 case X86::COND_L: return false;
3712 case X86::COND_LE: return false;
3713 case X86::COND_NE: return true;
3714 case X86::COND_B: return true;
3715 case X86::COND_A: return true;
3716 case X86::COND_BE: return true;
3717 case X86::COND_AE: return true;
3719 llvm_unreachable("covered switch fell through?!");
3722 /// TranslateX86CC - do a one to one translation of a ISD::CondCode to the X86
3723 /// specific condition code, returning the condition code and the LHS/RHS of the
3724 /// comparison to make.
3725 static unsigned TranslateX86CC(ISD::CondCode SetCCOpcode, SDLoc DL, bool isFP,
3726 SDValue &LHS, SDValue &RHS, SelectionDAG &DAG) {
3728 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
3729 if (SetCCOpcode == ISD::SETGT && RHSC->isAllOnesValue()) {
3730 // X > -1 -> X == 0, jump !sign.
3731 RHS = DAG.getConstant(0, DL, RHS.getValueType());
3732 return X86::COND_NS;
3734 if (SetCCOpcode == ISD::SETLT && RHSC->isNullValue()) {
3735 // X < 0 -> X == 0, jump on sign.
3738 if (SetCCOpcode == ISD::SETLT && RHSC->getZExtValue() == 1) {
3740 RHS = DAG.getConstant(0, DL, RHS.getValueType());
3741 return X86::COND_LE;
3745 switch (SetCCOpcode) {
3746 default: llvm_unreachable("Invalid integer condition!");
3747 case ISD::SETEQ: return X86::COND_E;
3748 case ISD::SETGT: return X86::COND_G;
3749 case ISD::SETGE: return X86::COND_GE;
3750 case ISD::SETLT: return X86::COND_L;
3751 case ISD::SETLE: return X86::COND_LE;
3752 case ISD::SETNE: return X86::COND_NE;
3753 case ISD::SETULT: return X86::COND_B;
3754 case ISD::SETUGT: return X86::COND_A;
3755 case ISD::SETULE: return X86::COND_BE;
3756 case ISD::SETUGE: return X86::COND_AE;
3760 // First determine if it is required or is profitable to flip the operands.
3762 // If LHS is a foldable load, but RHS is not, flip the condition.
3763 if (ISD::isNON_EXTLoad(LHS.getNode()) &&
3764 !ISD::isNON_EXTLoad(RHS.getNode())) {
3765 SetCCOpcode = getSetCCSwappedOperands(SetCCOpcode);
3766 std::swap(LHS, RHS);
3769 switch (SetCCOpcode) {
3775 std::swap(LHS, RHS);
3779 // On a floating point condition, the flags are set as follows:
3781 // 0 | 0 | 0 | X > Y
3782 // 0 | 0 | 1 | X < Y
3783 // 1 | 0 | 0 | X == Y
3784 // 1 | 1 | 1 | unordered
3785 switch (SetCCOpcode) {
3786 default: llvm_unreachable("Condcode should be pre-legalized away");
3788 case ISD::SETEQ: return X86::COND_E;
3789 case ISD::SETOLT: // flipped
3791 case ISD::SETGT: return X86::COND_A;
3792 case ISD::SETOLE: // flipped
3794 case ISD::SETGE: return X86::COND_AE;
3795 case ISD::SETUGT: // flipped
3797 case ISD::SETLT: return X86::COND_B;
3798 case ISD::SETUGE: // flipped
3800 case ISD::SETLE: return X86::COND_BE;
3802 case ISD::SETNE: return X86::COND_NE;
3803 case ISD::SETUO: return X86::COND_P;
3804 case ISD::SETO: return X86::COND_NP;
3806 case ISD::SETUNE: return X86::COND_INVALID;
3810 /// hasFPCMov - is there a floating point cmov for the specific X86 condition
3811 /// code. Current x86 isa includes the following FP cmov instructions:
3812 /// fcmovb, fcomvbe, fcomve, fcmovu, fcmovae, fcmova, fcmovne, fcmovnu.
3813 static bool hasFPCMov(unsigned X86CC) {
3829 /// isFPImmLegal - Returns true if the target can instruction select the
3830 /// specified FP immediate natively. If false, the legalizer will
3831 /// materialize the FP immediate as a load from a constant pool.
3832 bool X86TargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
3833 for (unsigned i = 0, e = LegalFPImmediates.size(); i != e; ++i) {
3834 if (Imm.bitwiseIsEqual(LegalFPImmediates[i]))
3840 bool X86TargetLowering::shouldReduceLoadWidth(SDNode *Load,
3841 ISD::LoadExtType ExtTy,
3843 // "ELF Handling for Thread-Local Storage" specifies that R_X86_64_GOTTPOFF
3844 // relocation target a movq or addq instruction: don't let the load shrink.
3845 SDValue BasePtr = cast<LoadSDNode>(Load)->getBasePtr();
3846 if (BasePtr.getOpcode() == X86ISD::WrapperRIP)
3847 if (const auto *GA = dyn_cast<GlobalAddressSDNode>(BasePtr.getOperand(0)))
3848 return GA->getTargetFlags() != X86II::MO_GOTTPOFF;
3852 /// \brief Returns true if it is beneficial to convert a load of a constant
3853 /// to just the constant itself.
3854 bool X86TargetLowering::shouldConvertConstantLoadToIntImm(const APInt &Imm,
3856 assert(Ty->isIntegerTy());
3858 unsigned BitSize = Ty->getPrimitiveSizeInBits();
3859 if (BitSize == 0 || BitSize > 64)
3864 bool X86TargetLowering::isExtractSubvectorCheap(EVT ResVT,
3865 unsigned Index) const {
3866 if (!isOperationLegalOrCustom(ISD::EXTRACT_SUBVECTOR, ResVT))
3869 return (Index == 0 || Index == ResVT.getVectorNumElements());
3872 bool X86TargetLowering::isCheapToSpeculateCttz() const {
3873 // Speculate cttz only if we can directly use TZCNT.
3874 return Subtarget->hasBMI();
3877 bool X86TargetLowering::isCheapToSpeculateCtlz() const {
3878 // Speculate ctlz only if we can directly use LZCNT.
3879 return Subtarget->hasLZCNT();
3882 /// isUndefOrInRange - Return true if Val is undef or if its value falls within
3883 /// the specified range (L, H].
3884 static bool isUndefOrInRange(int Val, int Low, int Hi) {
3885 return (Val < 0) || (Val >= Low && Val < Hi);
3888 /// isUndefOrEqual - Val is either less than zero (undef) or equal to the
3889 /// specified value.
3890 static bool isUndefOrEqual(int Val, int CmpVal) {
3891 return (Val < 0 || Val == CmpVal);
3894 /// isSequentialOrUndefInRange - Return true if every element in Mask, beginning
3895 /// from position Pos and ending in Pos+Size, falls within the specified
3896 /// sequential range (Low, Low+Size]. or is undef.
3897 static bool isSequentialOrUndefInRange(ArrayRef<int> Mask,
3898 unsigned Pos, unsigned Size, int Low) {
3899 for (unsigned i = Pos, e = Pos+Size; i != e; ++i, ++Low)
3900 if (!isUndefOrEqual(Mask[i], Low))
3905 /// isVEXTRACTIndex - Return true if the specified
3906 /// EXTRACT_SUBVECTOR operand specifies a vector extract that is
3907 /// suitable for instruction that extract 128 or 256 bit vectors
3908 static bool isVEXTRACTIndex(SDNode *N, unsigned vecWidth) {
3909 assert((vecWidth == 128 || vecWidth == 256) && "Unexpected vector width");
3910 if (!isa<ConstantSDNode>(N->getOperand(1).getNode()))
3913 // The index should be aligned on a vecWidth-bit boundary.
3915 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
3917 MVT VT = N->getSimpleValueType(0);
3918 unsigned ElSize = VT.getVectorElementType().getSizeInBits();
3919 bool Result = (Index * ElSize) % vecWidth == 0;
3924 /// isVINSERTIndex - Return true if the specified INSERT_SUBVECTOR
3925 /// operand specifies a subvector insert that is suitable for input to
3926 /// insertion of 128 or 256-bit subvectors
3927 static bool isVINSERTIndex(SDNode *N, unsigned vecWidth) {
3928 assert((vecWidth == 128 || vecWidth == 256) && "Unexpected vector width");
3929 if (!isa<ConstantSDNode>(N->getOperand(2).getNode()))
3931 // The index should be aligned on a vecWidth-bit boundary.
3933 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
3935 MVT VT = N->getSimpleValueType(0);
3936 unsigned ElSize = VT.getVectorElementType().getSizeInBits();
3937 bool Result = (Index * ElSize) % vecWidth == 0;
3942 bool X86::isVINSERT128Index(SDNode *N) {
3943 return isVINSERTIndex(N, 128);
3946 bool X86::isVINSERT256Index(SDNode *N) {
3947 return isVINSERTIndex(N, 256);
3950 bool X86::isVEXTRACT128Index(SDNode *N) {
3951 return isVEXTRACTIndex(N, 128);
3954 bool X86::isVEXTRACT256Index(SDNode *N) {
3955 return isVEXTRACTIndex(N, 256);
3958 static unsigned getExtractVEXTRACTImmediate(SDNode *N, unsigned vecWidth) {
3959 assert((vecWidth == 128 || vecWidth == 256) && "Unsupported vector width");
3960 if (!isa<ConstantSDNode>(N->getOperand(1).getNode()))
3961 llvm_unreachable("Illegal extract subvector for VEXTRACT");
3964 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
3966 MVT VecVT = N->getOperand(0).getSimpleValueType();
3967 MVT ElVT = VecVT.getVectorElementType();
3969 unsigned NumElemsPerChunk = vecWidth / ElVT.getSizeInBits();
3970 return Index / NumElemsPerChunk;
3973 static unsigned getInsertVINSERTImmediate(SDNode *N, unsigned vecWidth) {
3974 assert((vecWidth == 128 || vecWidth == 256) && "Unsupported vector width");
3975 if (!isa<ConstantSDNode>(N->getOperand(2).getNode()))
3976 llvm_unreachable("Illegal insert subvector for VINSERT");
3979 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
3981 MVT VecVT = N->getSimpleValueType(0);
3982 MVT ElVT = VecVT.getVectorElementType();
3984 unsigned NumElemsPerChunk = vecWidth / ElVT.getSizeInBits();
3985 return Index / NumElemsPerChunk;
3988 /// getExtractVEXTRACT128Immediate - Return the appropriate immediate
3989 /// to extract the specified EXTRACT_SUBVECTOR index with VEXTRACTF128
3990 /// and VINSERTI128 instructions.
3991 unsigned X86::getExtractVEXTRACT128Immediate(SDNode *N) {
3992 return getExtractVEXTRACTImmediate(N, 128);
3995 /// getExtractVEXTRACT256Immediate - Return the appropriate immediate
3996 /// to extract the specified EXTRACT_SUBVECTOR index with VEXTRACTF64x4
3997 /// and VINSERTI64x4 instructions.
3998 unsigned X86::getExtractVEXTRACT256Immediate(SDNode *N) {
3999 return getExtractVEXTRACTImmediate(N, 256);
4002 /// getInsertVINSERT128Immediate - Return the appropriate immediate
4003 /// to insert at the specified INSERT_SUBVECTOR index with VINSERTF128
4004 /// and VINSERTI128 instructions.
4005 unsigned X86::getInsertVINSERT128Immediate(SDNode *N) {
4006 return getInsertVINSERTImmediate(N, 128);
4009 /// getInsertVINSERT256Immediate - Return the appropriate immediate
4010 /// to insert at the specified INSERT_SUBVECTOR index with VINSERTF46x4
4011 /// and VINSERTI64x4 instructions.
4012 unsigned X86::getInsertVINSERT256Immediate(SDNode *N) {
4013 return getInsertVINSERTImmediate(N, 256);
4016 /// isZero - Returns true if Elt is a constant integer zero
4017 static bool isZero(SDValue V) {
4018 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V);
4019 return C && C->isNullValue();
4022 /// isZeroNode - Returns true if Elt is a constant zero or a floating point
4024 bool X86::isZeroNode(SDValue Elt) {
4027 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Elt))
4028 return CFP->getValueAPF().isPosZero();
4032 /// getZeroVector - Returns a vector of specified type with all zero elements.
4034 static SDValue getZeroVector(EVT VT, const X86Subtarget *Subtarget,
4035 SelectionDAG &DAG, SDLoc dl) {
4036 assert(VT.isVector() && "Expected a vector type");
4038 // Always build SSE zero vectors as <4 x i32> bitcasted
4039 // to their dest type. This ensures they get CSE'd.
4041 if (VT.is128BitVector()) { // SSE
4042 if (Subtarget->hasSSE2()) { // SSE2
4043 SDValue Cst = DAG.getConstant(0, dl, MVT::i32);
4044 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4046 SDValue Cst = DAG.getConstantFP(+0.0, dl, MVT::f32);
4047 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4f32, Cst, Cst, Cst, Cst);
4049 } else if (VT.is256BitVector()) { // AVX
4050 if (Subtarget->hasInt256()) { // AVX2
4051 SDValue Cst = DAG.getConstant(0, dl, MVT::i32);
4052 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4053 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops);
4055 // 256-bit logic and arithmetic instructions in AVX are all
4056 // floating-point, no support for integer ops. Emit fp zeroed vectors.
4057 SDValue Cst = DAG.getConstantFP(+0.0, dl, MVT::f32);
4058 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4059 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8f32, Ops);
4061 } else if (VT.is512BitVector()) { // AVX-512
4062 SDValue Cst = DAG.getConstant(0, dl, MVT::i32);
4063 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst,
4064 Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4065 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v16i32, Ops);
4066 } else if (VT.getScalarType() == MVT::i1) {
4068 assert((Subtarget->hasBWI() || VT.getVectorNumElements() <= 16)
4069 && "Unexpected vector type");
4070 assert((Subtarget->hasVLX() || VT.getVectorNumElements() >= 8)
4071 && "Unexpected vector type");
4072 SDValue Cst = DAG.getConstant(0, dl, MVT::i1);
4073 SmallVector<SDValue, 64> Ops(VT.getVectorNumElements(), Cst);
4074 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
4076 llvm_unreachable("Unexpected vector type");
4078 return DAG.getBitcast(VT, Vec);
4081 static SDValue ExtractSubVector(SDValue Vec, unsigned IdxVal,
4082 SelectionDAG &DAG, SDLoc dl,
4083 unsigned vectorWidth) {
4084 assert((vectorWidth == 128 || vectorWidth == 256) &&
4085 "Unsupported vector width");
4086 EVT VT = Vec.getValueType();
4087 EVT ElVT = VT.getVectorElementType();
4088 unsigned Factor = VT.getSizeInBits()/vectorWidth;
4089 EVT ResultVT = EVT::getVectorVT(*DAG.getContext(), ElVT,
4090 VT.getVectorNumElements()/Factor);
4092 // Extract from UNDEF is UNDEF.
4093 if (Vec.getOpcode() == ISD::UNDEF)
4094 return DAG.getUNDEF(ResultVT);
4096 // Extract the relevant vectorWidth bits. Generate an EXTRACT_SUBVECTOR
4097 unsigned ElemsPerChunk = vectorWidth / ElVT.getSizeInBits();
4099 // This is the index of the first element of the vectorWidth-bit chunk
4101 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits()) / vectorWidth)
4104 // If the input is a buildvector just emit a smaller one.
4105 if (Vec.getOpcode() == ISD::BUILD_VECTOR)
4106 return DAG.getNode(ISD::BUILD_VECTOR, dl, ResultVT,
4107 makeArrayRef(Vec->op_begin() + NormalizedIdxVal,
4110 SDValue VecIdx = DAG.getIntPtrConstant(NormalizedIdxVal, dl);
4111 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, ResultVT, Vec, VecIdx);
4114 /// Generate a DAG to grab 128-bits from a vector > 128 bits. This
4115 /// sets things up to match to an AVX VEXTRACTF128 / VEXTRACTI128
4116 /// or AVX-512 VEXTRACTF32x4 / VEXTRACTI32x4
4117 /// instructions or a simple subregister reference. Idx is an index in the
4118 /// 128 bits we want. It need not be aligned to a 128-bit boundary. That makes
4119 /// lowering EXTRACT_VECTOR_ELT operations easier.
4120 static SDValue Extract128BitVector(SDValue Vec, unsigned IdxVal,
4121 SelectionDAG &DAG, SDLoc dl) {
4122 assert((Vec.getValueType().is256BitVector() ||
4123 Vec.getValueType().is512BitVector()) && "Unexpected vector size!");
4124 return ExtractSubVector(Vec, IdxVal, DAG, dl, 128);
4127 /// Generate a DAG to grab 256-bits from a 512-bit vector.
4128 static SDValue Extract256BitVector(SDValue Vec, unsigned IdxVal,
4129 SelectionDAG &DAG, SDLoc dl) {
4130 assert(Vec.getValueType().is512BitVector() && "Unexpected vector size!");
4131 return ExtractSubVector(Vec, IdxVal, DAG, dl, 256);
4134 static SDValue InsertSubVector(SDValue Result, SDValue Vec,
4135 unsigned IdxVal, SelectionDAG &DAG,
4136 SDLoc dl, unsigned vectorWidth) {
4137 assert((vectorWidth == 128 || vectorWidth == 256) &&
4138 "Unsupported vector width");
4139 // Inserting UNDEF is Result
4140 if (Vec.getOpcode() == ISD::UNDEF)
4142 EVT VT = Vec.getValueType();
4143 EVT ElVT = VT.getVectorElementType();
4144 EVT ResultVT = Result.getValueType();
4146 // Insert the relevant vectorWidth bits.
4147 unsigned ElemsPerChunk = vectorWidth/ElVT.getSizeInBits();
4149 // This is the index of the first element of the vectorWidth-bit chunk
4151 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits())/vectorWidth)
4154 SDValue VecIdx = DAG.getIntPtrConstant(NormalizedIdxVal, dl);
4155 return DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResultVT, Result, Vec, VecIdx);
4158 /// Generate a DAG to put 128-bits into a vector > 128 bits. This
4159 /// sets things up to match to an AVX VINSERTF128/VINSERTI128 or
4160 /// AVX-512 VINSERTF32x4/VINSERTI32x4 instructions or a
4161 /// simple superregister reference. Idx is an index in the 128 bits
4162 /// we want. It need not be aligned to a 128-bit boundary. That makes
4163 /// lowering INSERT_VECTOR_ELT operations easier.
4164 static SDValue Insert128BitVector(SDValue Result, SDValue Vec, unsigned IdxVal,
4165 SelectionDAG &DAG, SDLoc dl) {
4166 assert(Vec.getValueType().is128BitVector() && "Unexpected vector size!");
4168 // For insertion into the zero index (low half) of a 256-bit vector, it is
4169 // more efficient to generate a blend with immediate instead of an insert*128.
4170 // We are still creating an INSERT_SUBVECTOR below with an undef node to
4171 // extend the subvector to the size of the result vector. Make sure that
4172 // we are not recursing on that node by checking for undef here.
4173 if (IdxVal == 0 && Result.getValueType().is256BitVector() &&
4174 Result.getOpcode() != ISD::UNDEF) {
4175 EVT ResultVT = Result.getValueType();
4176 SDValue ZeroIndex = DAG.getIntPtrConstant(0, dl);
4177 SDValue Undef = DAG.getUNDEF(ResultVT);
4178 SDValue Vec256 = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResultVT, Undef,
4181 // The blend instruction, and therefore its mask, depend on the data type.
4182 MVT ScalarType = ResultVT.getScalarType().getSimpleVT();
4183 if (ScalarType.isFloatingPoint()) {
4184 // Choose either vblendps (float) or vblendpd (double).
4185 unsigned ScalarSize = ScalarType.getSizeInBits();
4186 assert((ScalarSize == 64 || ScalarSize == 32) && "Unknown float type");
4187 unsigned MaskVal = (ScalarSize == 64) ? 0x03 : 0x0f;
4188 SDValue Mask = DAG.getConstant(MaskVal, dl, MVT::i8);
4189 return DAG.getNode(X86ISD::BLENDI, dl, ResultVT, Result, Vec256, Mask);
4192 const X86Subtarget &Subtarget =
4193 static_cast<const X86Subtarget &>(DAG.getSubtarget());
4195 // AVX2 is needed for 256-bit integer blend support.
4196 // Integers must be cast to 32-bit because there is only vpblendd;
4197 // vpblendw can't be used for this because it has a handicapped mask.
4199 // If we don't have AVX2, then cast to float. Using a wrong domain blend
4200 // is still more efficient than using the wrong domain vinsertf128 that
4201 // will be created by InsertSubVector().
4202 MVT CastVT = Subtarget.hasAVX2() ? MVT::v8i32 : MVT::v8f32;
4204 SDValue Mask = DAG.getConstant(0x0f, dl, MVT::i8);
4205 Vec256 = DAG.getBitcast(CastVT, Vec256);
4206 Vec256 = DAG.getNode(X86ISD::BLENDI, dl, CastVT, Result, Vec256, Mask);
4207 return DAG.getBitcast(ResultVT, Vec256);
4210 return InsertSubVector(Result, Vec, IdxVal, DAG, dl, 128);
4213 static SDValue Insert256BitVector(SDValue Result, SDValue Vec, unsigned IdxVal,
4214 SelectionDAG &DAG, SDLoc dl) {
4215 assert(Vec.getValueType().is256BitVector() && "Unexpected vector size!");
4216 return InsertSubVector(Result, Vec, IdxVal, DAG, dl, 256);
4219 /// Concat two 128-bit vectors into a 256 bit vector using VINSERTF128
4220 /// instructions. This is used because creating CONCAT_VECTOR nodes of
4221 /// BUILD_VECTORS returns a larger BUILD_VECTOR while we're trying to lower
4222 /// large BUILD_VECTORS.
4223 static SDValue Concat128BitVectors(SDValue V1, SDValue V2, EVT VT,
4224 unsigned NumElems, SelectionDAG &DAG,
4226 SDValue V = Insert128BitVector(DAG.getUNDEF(VT), V1, 0, DAG, dl);
4227 return Insert128BitVector(V, V2, NumElems/2, DAG, dl);
4230 static SDValue Concat256BitVectors(SDValue V1, SDValue V2, EVT VT,
4231 unsigned NumElems, SelectionDAG &DAG,
4233 SDValue V = Insert256BitVector(DAG.getUNDEF(VT), V1, 0, DAG, dl);
4234 return Insert256BitVector(V, V2, NumElems/2, DAG, dl);
4237 /// getOnesVector - Returns a vector of specified type with all bits set.
4238 /// Always build ones vectors as <4 x i32> or <8 x i32>. For 256-bit types with
4239 /// no AVX2 supprt, use two <4 x i32> inserted in a <8 x i32> appropriately.
4240 /// Then bitcast to their original type, ensuring they get CSE'd.
4241 static SDValue getOnesVector(MVT VT, bool HasInt256, SelectionDAG &DAG,
4243 assert(VT.isVector() && "Expected a vector type");
4245 SDValue Cst = DAG.getConstant(~0U, dl, MVT::i32);
4247 if (VT.is256BitVector()) {
4248 if (HasInt256) { // AVX2
4249 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4250 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops);
4252 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4253 Vec = Concat128BitVectors(Vec, Vec, MVT::v8i32, 8, DAG, dl);
4255 } else if (VT.is128BitVector()) {
4256 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4258 llvm_unreachable("Unexpected vector type");
4260 return DAG.getBitcast(VT, Vec);
4263 /// getMOVLMask - Returns a vector_shuffle mask for an movs{s|d}, movd
4264 /// operation of specified width.
4265 static SDValue getMOVL(SelectionDAG &DAG, SDLoc dl, EVT VT, SDValue V1,
4267 unsigned NumElems = VT.getVectorNumElements();
4268 SmallVector<int, 8> Mask;
4269 Mask.push_back(NumElems);
4270 for (unsigned i = 1; i != NumElems; ++i)
4272 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
4275 /// getUnpackl - Returns a vector_shuffle node for an unpackl operation.
4276 static SDValue getUnpackl(SelectionDAG &DAG, SDLoc dl, MVT VT, SDValue V1,
4278 unsigned NumElems = VT.getVectorNumElements();
4279 SmallVector<int, 8> Mask;
4280 for (unsigned i = 0, e = NumElems/2; i != e; ++i) {
4282 Mask.push_back(i + NumElems);
4284 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
4287 /// getUnpackh - Returns a vector_shuffle node for an unpackh operation.
4288 static SDValue getUnpackh(SelectionDAG &DAG, SDLoc dl, MVT VT, SDValue V1,
4290 unsigned NumElems = VT.getVectorNumElements();
4291 SmallVector<int, 8> Mask;
4292 for (unsigned i = 0, Half = NumElems/2; i != Half; ++i) {
4293 Mask.push_back(i + Half);
4294 Mask.push_back(i + NumElems + Half);
4296 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
4299 /// getShuffleVectorZeroOrUndef - Return a vector_shuffle of the specified
4300 /// vector of zero or undef vector. This produces a shuffle where the low
4301 /// element of V2 is swizzled into the zero/undef vector, landing at element
4302 /// Idx. This produces a shuffle mask like 4,1,2,3 (idx=0) or 0,1,2,4 (idx=3).
4303 static SDValue getShuffleVectorZeroOrUndef(SDValue V2, unsigned Idx,
4305 const X86Subtarget *Subtarget,
4306 SelectionDAG &DAG) {
4307 MVT VT = V2.getSimpleValueType();
4309 ? getZeroVector(VT, Subtarget, DAG, SDLoc(V2)) : DAG.getUNDEF(VT);
4310 unsigned NumElems = VT.getVectorNumElements();
4311 SmallVector<int, 16> MaskVec;
4312 for (unsigned i = 0; i != NumElems; ++i)
4313 // If this is the insertion idx, put the low elt of V2 here.
4314 MaskVec.push_back(i == Idx ? NumElems : i);
4315 return DAG.getVectorShuffle(VT, SDLoc(V2), V1, V2, &MaskVec[0]);
4318 /// getTargetShuffleMask - Calculates the shuffle mask corresponding to the
4319 /// target specific opcode. Returns true if the Mask could be calculated. Sets
4320 /// IsUnary to true if only uses one source. Note that this will set IsUnary for
4321 /// shuffles which use a single input multiple times, and in those cases it will
4322 /// adjust the mask to only have indices within that single input.
4323 static bool getTargetShuffleMask(SDNode *N, MVT VT,
4324 SmallVectorImpl<int> &Mask, bool &IsUnary) {
4325 unsigned NumElems = VT.getVectorNumElements();
4329 bool IsFakeUnary = false;
4330 switch(N->getOpcode()) {
4331 case X86ISD::BLENDI:
4332 ImmN = N->getOperand(N->getNumOperands()-1);
4333 DecodeBLENDMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4336 ImmN = N->getOperand(N->getNumOperands()-1);
4337 DecodeSHUFPMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4338 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
4340 case X86ISD::UNPCKH:
4341 DecodeUNPCKHMask(VT, Mask);
4342 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
4344 case X86ISD::UNPCKL:
4345 DecodeUNPCKLMask(VT, Mask);
4346 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
4348 case X86ISD::MOVHLPS:
4349 DecodeMOVHLPSMask(NumElems, Mask);
4350 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
4352 case X86ISD::MOVLHPS:
4353 DecodeMOVLHPSMask(NumElems, Mask);
4354 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
4356 case X86ISD::PALIGNR:
4357 ImmN = N->getOperand(N->getNumOperands()-1);
4358 DecodePALIGNRMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4360 case X86ISD::PSHUFD:
4361 case X86ISD::VPERMILPI:
4362 ImmN = N->getOperand(N->getNumOperands()-1);
4363 DecodePSHUFMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4366 case X86ISD::PSHUFHW:
4367 ImmN = N->getOperand(N->getNumOperands()-1);
4368 DecodePSHUFHWMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4371 case X86ISD::PSHUFLW:
4372 ImmN = N->getOperand(N->getNumOperands()-1);
4373 DecodePSHUFLWMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4376 case X86ISD::PSHUFB: {
4378 SDValue MaskNode = N->getOperand(1);
4379 while (MaskNode->getOpcode() == ISD::BITCAST)
4380 MaskNode = MaskNode->getOperand(0);
4382 if (MaskNode->getOpcode() == ISD::BUILD_VECTOR) {
4383 // If we have a build-vector, then things are easy.
4384 EVT VT = MaskNode.getValueType();
4385 assert(VT.isVector() &&
4386 "Can't produce a non-vector with a build_vector!");
4387 if (!VT.isInteger())
4390 int NumBytesPerElement = VT.getVectorElementType().getSizeInBits() / 8;
4392 SmallVector<uint64_t, 32> RawMask;
4393 for (int i = 0, e = MaskNode->getNumOperands(); i < e; ++i) {
4394 SDValue Op = MaskNode->getOperand(i);
4395 if (Op->getOpcode() == ISD::UNDEF) {
4396 RawMask.push_back((uint64_t)SM_SentinelUndef);
4399 auto *CN = dyn_cast<ConstantSDNode>(Op.getNode());
4402 APInt MaskElement = CN->getAPIntValue();
4404 // We now have to decode the element which could be any integer size and
4405 // extract each byte of it.
4406 for (int j = 0; j < NumBytesPerElement; ++j) {
4407 // Note that this is x86 and so always little endian: the low byte is
4408 // the first byte of the mask.
4409 RawMask.push_back(MaskElement.getLoBits(8).getZExtValue());
4410 MaskElement = MaskElement.lshr(8);
4413 DecodePSHUFBMask(RawMask, Mask);
4417 auto *MaskLoad = dyn_cast<LoadSDNode>(MaskNode);
4421 SDValue Ptr = MaskLoad->getBasePtr();
4422 if (Ptr->getOpcode() == X86ISD::Wrapper ||
4423 Ptr->getOpcode() == X86ISD::WrapperRIP)
4424 Ptr = Ptr->getOperand(0);
4426 auto *MaskCP = dyn_cast<ConstantPoolSDNode>(Ptr);
4427 if (!MaskCP || MaskCP->isMachineConstantPoolEntry())
4430 if (auto *C = dyn_cast<Constant>(MaskCP->getConstVal())) {
4431 DecodePSHUFBMask(C, Mask);
4439 case X86ISD::VPERMI:
4440 ImmN = N->getOperand(N->getNumOperands()-1);
4441 DecodeVPERMMask(cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4446 DecodeScalarMoveMask(VT, /* IsLoad */ false, Mask);
4448 case X86ISD::VPERM2X128:
4449 ImmN = N->getOperand(N->getNumOperands()-1);
4450 DecodeVPERM2X128Mask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4451 if (Mask.empty()) return false;
4453 case X86ISD::MOVSLDUP:
4454 DecodeMOVSLDUPMask(VT, Mask);
4457 case X86ISD::MOVSHDUP:
4458 DecodeMOVSHDUPMask(VT, Mask);
4461 case X86ISD::MOVDDUP:
4462 DecodeMOVDDUPMask(VT, Mask);
4465 case X86ISD::MOVLHPD:
4466 case X86ISD::MOVLPD:
4467 case X86ISD::MOVLPS:
4468 // Not yet implemented
4470 default: llvm_unreachable("unknown target shuffle node");
4473 // If we have a fake unary shuffle, the shuffle mask is spread across two
4474 // inputs that are actually the same node. Re-map the mask to always point
4475 // into the first input.
4478 if (M >= (int)Mask.size())
4484 /// getShuffleScalarElt - Returns the scalar element that will make up the ith
4485 /// element of the result of the vector shuffle.
4486 static SDValue getShuffleScalarElt(SDNode *N, unsigned Index, SelectionDAG &DAG,
4489 return SDValue(); // Limit search depth.
4491 SDValue V = SDValue(N, 0);
4492 EVT VT = V.getValueType();
4493 unsigned Opcode = V.getOpcode();
4495 // Recurse into ISD::VECTOR_SHUFFLE node to find scalars.
4496 if (const ShuffleVectorSDNode *SV = dyn_cast<ShuffleVectorSDNode>(N)) {
4497 int Elt = SV->getMaskElt(Index);
4500 return DAG.getUNDEF(VT.getVectorElementType());
4502 unsigned NumElems = VT.getVectorNumElements();
4503 SDValue NewV = (Elt < (int)NumElems) ? SV->getOperand(0)
4504 : SV->getOperand(1);
4505 return getShuffleScalarElt(NewV.getNode(), Elt % NumElems, DAG, Depth+1);
4508 // Recurse into target specific vector shuffles to find scalars.
4509 if (isTargetShuffle(Opcode)) {
4510 MVT ShufVT = V.getSimpleValueType();
4511 unsigned NumElems = ShufVT.getVectorNumElements();
4512 SmallVector<int, 16> ShuffleMask;
4515 if (!getTargetShuffleMask(N, ShufVT, ShuffleMask, IsUnary))
4518 int Elt = ShuffleMask[Index];
4520 return DAG.getUNDEF(ShufVT.getVectorElementType());
4522 SDValue NewV = (Elt < (int)NumElems) ? N->getOperand(0)
4524 return getShuffleScalarElt(NewV.getNode(), Elt % NumElems, DAG,
4528 // Actual nodes that may contain scalar elements
4529 if (Opcode == ISD::BITCAST) {
4530 V = V.getOperand(0);
4531 EVT SrcVT = V.getValueType();
4532 unsigned NumElems = VT.getVectorNumElements();
4534 if (!SrcVT.isVector() || SrcVT.getVectorNumElements() != NumElems)
4538 if (V.getOpcode() == ISD::SCALAR_TO_VECTOR)
4539 return (Index == 0) ? V.getOperand(0)
4540 : DAG.getUNDEF(VT.getVectorElementType());
4542 if (V.getOpcode() == ISD::BUILD_VECTOR)
4543 return V.getOperand(Index);
4548 /// LowerBuildVectorv16i8 - Custom lower build_vector of v16i8.
4550 static SDValue LowerBuildVectorv16i8(SDValue Op, unsigned NonZeros,
4551 unsigned NumNonZero, unsigned NumZero,
4553 const X86Subtarget* Subtarget,
4554 const TargetLowering &TLI) {
4562 // SSE4.1 - use PINSRB to insert each byte directly.
4563 if (Subtarget->hasSSE41()) {
4564 for (unsigned i = 0; i < 16; ++i) {
4565 bool isNonZero = (NonZeros & (1 << i)) != 0;
4569 V = getZeroVector(MVT::v16i8, Subtarget, DAG, dl);
4571 V = DAG.getUNDEF(MVT::v16i8);
4574 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl,
4575 MVT::v16i8, V, Op.getOperand(i),
4576 DAG.getIntPtrConstant(i, dl));
4583 // Pre-SSE4.1 - merge byte pairs and insert with PINSRW.
4584 for (unsigned i = 0; i < 16; ++i) {
4585 bool ThisIsNonZero = (NonZeros & (1 << i)) != 0;
4586 if (ThisIsNonZero && First) {
4588 V = getZeroVector(MVT::v8i16, Subtarget, DAG, dl);
4590 V = DAG.getUNDEF(MVT::v8i16);
4595 SDValue ThisElt, LastElt;
4596 bool LastIsNonZero = (NonZeros & (1 << (i-1))) != 0;
4597 if (LastIsNonZero) {
4598 LastElt = DAG.getNode(ISD::ZERO_EXTEND, dl,
4599 MVT::i16, Op.getOperand(i-1));
4601 if (ThisIsNonZero) {
4602 ThisElt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, Op.getOperand(i));
4603 ThisElt = DAG.getNode(ISD::SHL, dl, MVT::i16,
4604 ThisElt, DAG.getConstant(8, dl, MVT::i8));
4606 ThisElt = DAG.getNode(ISD::OR, dl, MVT::i16, ThisElt, LastElt);
4610 if (ThisElt.getNode())
4611 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, V, ThisElt,
4612 DAG.getIntPtrConstant(i/2, dl));
4616 return DAG.getBitcast(MVT::v16i8, V);
4619 /// LowerBuildVectorv8i16 - Custom lower build_vector of v8i16.
4621 static SDValue LowerBuildVectorv8i16(SDValue Op, unsigned NonZeros,
4622 unsigned NumNonZero, unsigned NumZero,
4624 const X86Subtarget* Subtarget,
4625 const TargetLowering &TLI) {
4632 for (unsigned i = 0; i < 8; ++i) {
4633 bool isNonZero = (NonZeros & (1 << i)) != 0;
4637 V = getZeroVector(MVT::v8i16, Subtarget, DAG, dl);
4639 V = DAG.getUNDEF(MVT::v8i16);
4642 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl,
4643 MVT::v8i16, V, Op.getOperand(i),
4644 DAG.getIntPtrConstant(i, dl));
4651 /// LowerBuildVectorv4x32 - Custom lower build_vector of v4i32 or v4f32.
4652 static SDValue LowerBuildVectorv4x32(SDValue Op, SelectionDAG &DAG,
4653 const X86Subtarget *Subtarget,
4654 const TargetLowering &TLI) {
4655 // Find all zeroable elements.
4656 std::bitset<4> Zeroable;
4657 for (int i=0; i < 4; ++i) {
4658 SDValue Elt = Op->getOperand(i);
4659 Zeroable[i] = (Elt.getOpcode() == ISD::UNDEF || X86::isZeroNode(Elt));
4661 assert(Zeroable.size() - Zeroable.count() > 1 &&
4662 "We expect at least two non-zero elements!");
4664 // We only know how to deal with build_vector nodes where elements are either
4665 // zeroable or extract_vector_elt with constant index.
4666 SDValue FirstNonZero;
4667 unsigned FirstNonZeroIdx;
4668 for (unsigned i=0; i < 4; ++i) {
4671 SDValue Elt = Op->getOperand(i);
4672 if (Elt.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
4673 !isa<ConstantSDNode>(Elt.getOperand(1)))
4675 // Make sure that this node is extracting from a 128-bit vector.
4676 MVT VT = Elt.getOperand(0).getSimpleValueType();
4677 if (!VT.is128BitVector())
4679 if (!FirstNonZero.getNode()) {
4681 FirstNonZeroIdx = i;
4685 assert(FirstNonZero.getNode() && "Unexpected build vector of all zeros!");
4686 SDValue V1 = FirstNonZero.getOperand(0);
4687 MVT VT = V1.getSimpleValueType();
4689 // See if this build_vector can be lowered as a blend with zero.
4691 unsigned EltMaskIdx, EltIdx;
4693 for (EltIdx = 0; EltIdx < 4; ++EltIdx) {
4694 if (Zeroable[EltIdx]) {
4695 // The zero vector will be on the right hand side.
4696 Mask[EltIdx] = EltIdx+4;
4700 Elt = Op->getOperand(EltIdx);
4701 // By construction, Elt is a EXTRACT_VECTOR_ELT with constant index.
4702 EltMaskIdx = cast<ConstantSDNode>(Elt.getOperand(1))->getZExtValue();
4703 if (Elt.getOperand(0) != V1 || EltMaskIdx != EltIdx)
4705 Mask[EltIdx] = EltIdx;
4709 // Let the shuffle legalizer deal with blend operations.
4710 SDValue VZero = getZeroVector(VT, Subtarget, DAG, SDLoc(Op));
4711 if (V1.getSimpleValueType() != VT)
4712 V1 = DAG.getNode(ISD::BITCAST, SDLoc(V1), VT, V1);
4713 return DAG.getVectorShuffle(VT, SDLoc(V1), V1, VZero, &Mask[0]);
4716 // See if we can lower this build_vector to a INSERTPS.
4717 if (!Subtarget->hasSSE41())
4720 SDValue V2 = Elt.getOperand(0);
4721 if (Elt == FirstNonZero && EltIdx == FirstNonZeroIdx)
4724 bool CanFold = true;
4725 for (unsigned i = EltIdx + 1; i < 4 && CanFold; ++i) {
4729 SDValue Current = Op->getOperand(i);
4730 SDValue SrcVector = Current->getOperand(0);
4733 CanFold = SrcVector == V1 &&
4734 cast<ConstantSDNode>(Current.getOperand(1))->getZExtValue() == i;
4740 assert(V1.getNode() && "Expected at least two non-zero elements!");
4741 if (V1.getSimpleValueType() != MVT::v4f32)
4742 V1 = DAG.getNode(ISD::BITCAST, SDLoc(V1), MVT::v4f32, V1);
4743 if (V2.getSimpleValueType() != MVT::v4f32)
4744 V2 = DAG.getNode(ISD::BITCAST, SDLoc(V2), MVT::v4f32, V2);
4746 // Ok, we can emit an INSERTPS instruction.
4747 unsigned ZMask = Zeroable.to_ulong();
4749 unsigned InsertPSMask = EltMaskIdx << 6 | EltIdx << 4 | ZMask;
4750 assert((InsertPSMask & ~0xFFu) == 0 && "Invalid mask!");
4752 SDValue Result = DAG.getNode(X86ISD::INSERTPS, DL, MVT::v4f32, V1, V2,
4753 DAG.getIntPtrConstant(InsertPSMask, DL));
4754 return DAG.getBitcast(VT, Result);
4757 /// Return a vector logical shift node.
4758 static SDValue getVShift(bool isLeft, EVT VT, SDValue SrcOp,
4759 unsigned NumBits, SelectionDAG &DAG,
4760 const TargetLowering &TLI, SDLoc dl) {
4761 assert(VT.is128BitVector() && "Unknown type for VShift");
4762 MVT ShVT = MVT::v2i64;
4763 unsigned Opc = isLeft ? X86ISD::VSHLDQ : X86ISD::VSRLDQ;
4764 SrcOp = DAG.getBitcast(ShVT, SrcOp);
4765 MVT ScalarShiftTy = TLI.getScalarShiftAmountTy(SrcOp.getValueType());
4766 assert(NumBits % 8 == 0 && "Only support byte sized shifts");
4767 SDValue ShiftVal = DAG.getConstant(NumBits/8, dl, ScalarShiftTy);
4768 return DAG.getBitcast(VT, DAG.getNode(Opc, dl, ShVT, SrcOp, ShiftVal));
4772 LowerAsSplatVectorLoad(SDValue SrcOp, MVT VT, SDLoc dl, SelectionDAG &DAG) {
4774 // Check if the scalar load can be widened into a vector load. And if
4775 // the address is "base + cst" see if the cst can be "absorbed" into
4776 // the shuffle mask.
4777 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(SrcOp)) {
4778 SDValue Ptr = LD->getBasePtr();
4779 if (!ISD::isNormalLoad(LD) || LD->isVolatile())
4781 EVT PVT = LD->getValueType(0);
4782 if (PVT != MVT::i32 && PVT != MVT::f32)
4787 if (FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr)) {
4788 FI = FINode->getIndex();
4790 } else if (DAG.isBaseWithConstantOffset(Ptr) &&
4791 isa<FrameIndexSDNode>(Ptr.getOperand(0))) {
4792 FI = cast<FrameIndexSDNode>(Ptr.getOperand(0))->getIndex();
4793 Offset = Ptr.getConstantOperandVal(1);
4794 Ptr = Ptr.getOperand(0);
4799 // FIXME: 256-bit vector instructions don't require a strict alignment,
4800 // improve this code to support it better.
4801 unsigned RequiredAlign = VT.getSizeInBits()/8;
4802 SDValue Chain = LD->getChain();
4803 // Make sure the stack object alignment is at least 16 or 32.
4804 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
4805 if (DAG.InferPtrAlignment(Ptr) < RequiredAlign) {
4806 if (MFI->isFixedObjectIndex(FI)) {
4807 // Can't change the alignment. FIXME: It's possible to compute
4808 // the exact stack offset and reference FI + adjust offset instead.
4809 // If someone *really* cares about this. That's the way to implement it.
4812 MFI->setObjectAlignment(FI, RequiredAlign);
4816 // (Offset % 16 or 32) must be multiple of 4. Then address is then
4817 // Ptr + (Offset & ~15).
4820 if ((Offset % RequiredAlign) & 3)
4822 int64_t StartOffset = Offset & ~(RequiredAlign-1);
4825 Ptr = DAG.getNode(ISD::ADD, DL, Ptr.getValueType(), Ptr,
4826 DAG.getConstant(StartOffset, DL, Ptr.getValueType()));
4829 int EltNo = (Offset - StartOffset) >> 2;
4830 unsigned NumElems = VT.getVectorNumElements();
4832 EVT NVT = EVT::getVectorVT(*DAG.getContext(), PVT, NumElems);
4833 SDValue V1 = DAG.getLoad(NVT, dl, Chain, Ptr,
4834 LD->getPointerInfo().getWithOffset(StartOffset),
4835 false, false, false, 0);
4837 SmallVector<int, 8> Mask(NumElems, EltNo);
4839 return DAG.getVectorShuffle(NVT, dl, V1, DAG.getUNDEF(NVT), &Mask[0]);
4845 /// Given the initializing elements 'Elts' of a vector of type 'VT', see if the
4846 /// elements can be replaced by a single large load which has the same value as
4847 /// a build_vector or insert_subvector whose loaded operands are 'Elts'.
4849 /// Example: <load i32 *a, load i32 *a+4, undef, undef> -> zextload a
4851 /// FIXME: we'd also like to handle the case where the last elements are zero
4852 /// rather than undef via VZEXT_LOAD, but we do not detect that case today.
4853 /// There's even a handy isZeroNode for that purpose.
4854 static SDValue EltsFromConsecutiveLoads(EVT VT, ArrayRef<SDValue> Elts,
4855 SDLoc &DL, SelectionDAG &DAG,
4856 bool isAfterLegalize) {
4857 unsigned NumElems = Elts.size();
4859 LoadSDNode *LDBase = nullptr;
4860 unsigned LastLoadedElt = -1U;
4862 // For each element in the initializer, see if we've found a load or an undef.
4863 // If we don't find an initial load element, or later load elements are
4864 // non-consecutive, bail out.
4865 for (unsigned i = 0; i < NumElems; ++i) {
4866 SDValue Elt = Elts[i];
4867 // Look through a bitcast.
4868 if (Elt.getNode() && Elt.getOpcode() == ISD::BITCAST)
4869 Elt = Elt.getOperand(0);
4870 if (!Elt.getNode() ||
4871 (Elt.getOpcode() != ISD::UNDEF && !ISD::isNON_EXTLoad(Elt.getNode())))
4874 if (Elt.getNode()->getOpcode() == ISD::UNDEF)
4876 LDBase = cast<LoadSDNode>(Elt.getNode());
4880 if (Elt.getOpcode() == ISD::UNDEF)
4883 LoadSDNode *LD = cast<LoadSDNode>(Elt);
4884 EVT LdVT = Elt.getValueType();
4885 // Each loaded element must be the correct fractional portion of the
4886 // requested vector load.
4887 if (LdVT.getSizeInBits() != VT.getSizeInBits() / NumElems)
4889 if (!DAG.isConsecutiveLoad(LD, LDBase, LdVT.getSizeInBits() / 8, i))
4894 // If we have found an entire vector of loads and undefs, then return a large
4895 // load of the entire vector width starting at the base pointer. If we found
4896 // consecutive loads for the low half, generate a vzext_load node.
4897 if (LastLoadedElt == NumElems - 1) {
4898 assert(LDBase && "Did not find base load for merging consecutive loads");
4899 EVT EltVT = LDBase->getValueType(0);
4900 // Ensure that the input vector size for the merged loads matches the
4901 // cumulative size of the input elements.
4902 if (VT.getSizeInBits() != EltVT.getSizeInBits() * NumElems)
4905 if (isAfterLegalize &&
4906 !DAG.getTargetLoweringInfo().isOperationLegal(ISD::LOAD, VT))
4909 SDValue NewLd = SDValue();
4911 NewLd = DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(),
4912 LDBase->getPointerInfo(), LDBase->isVolatile(),
4913 LDBase->isNonTemporal(), LDBase->isInvariant(),
4914 LDBase->getAlignment());
4916 if (LDBase->hasAnyUseOfValue(1)) {
4917 SDValue NewChain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
4919 SDValue(NewLd.getNode(), 1));
4920 DAG.ReplaceAllUsesOfValueWith(SDValue(LDBase, 1), NewChain);
4921 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(LDBase, 1),
4922 SDValue(NewLd.getNode(), 1));
4928 //TODO: The code below fires only for for loading the low v2i32 / v2f32
4929 //of a v4i32 / v4f32. It's probably worth generalizing.
4930 EVT EltVT = VT.getVectorElementType();
4931 if (NumElems == 4 && LastLoadedElt == 1 && (EltVT.getSizeInBits() == 32) &&
4932 DAG.getTargetLoweringInfo().isTypeLegal(MVT::v2i64)) {
4933 SDVTList Tys = DAG.getVTList(MVT::v2i64, MVT::Other);
4934 SDValue Ops[] = { LDBase->getChain(), LDBase->getBasePtr() };
4936 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, DL, Tys, Ops, MVT::i64,
4937 LDBase->getPointerInfo(),
4938 LDBase->getAlignment(),
4939 false/*isVolatile*/, true/*ReadMem*/,
4942 // Make sure the newly-created LOAD is in the same position as LDBase in
4943 // terms of dependency. We create a TokenFactor for LDBase and ResNode, and
4944 // update uses of LDBase's output chain to use the TokenFactor.
4945 if (LDBase->hasAnyUseOfValue(1)) {
4946 SDValue NewChain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
4947 SDValue(LDBase, 1), SDValue(ResNode.getNode(), 1));
4948 DAG.ReplaceAllUsesOfValueWith(SDValue(LDBase, 1), NewChain);
4949 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(LDBase, 1),
4950 SDValue(ResNode.getNode(), 1));
4953 return DAG.getBitcast(VT, ResNode);
4958 /// LowerVectorBroadcast - Attempt to use the vbroadcast instruction
4959 /// to generate a splat value for the following cases:
4960 /// 1. A splat BUILD_VECTOR which uses a single scalar load, or a constant.
4961 /// 2. A splat shuffle which uses a scalar_to_vector node which comes from
4962 /// a scalar load, or a constant.
4963 /// The VBROADCAST node is returned when a pattern is found,
4964 /// or SDValue() otherwise.
4965 static SDValue LowerVectorBroadcast(SDValue Op, const X86Subtarget* Subtarget,
4966 SelectionDAG &DAG) {
4967 // VBROADCAST requires AVX.
4968 // TODO: Splats could be generated for non-AVX CPUs using SSE
4969 // instructions, but there's less potential gain for only 128-bit vectors.
4970 if (!Subtarget->hasAVX())
4973 MVT VT = Op.getSimpleValueType();
4976 assert((VT.is128BitVector() || VT.is256BitVector() || VT.is512BitVector()) &&
4977 "Unsupported vector type for broadcast.");
4982 switch (Op.getOpcode()) {
4984 // Unknown pattern found.
4987 case ISD::BUILD_VECTOR: {
4988 auto *BVOp = cast<BuildVectorSDNode>(Op.getNode());
4989 BitVector UndefElements;
4990 SDValue Splat = BVOp->getSplatValue(&UndefElements);
4992 // We need a splat of a single value to use broadcast, and it doesn't
4993 // make any sense if the value is only in one element of the vector.
4994 if (!Splat || (VT.getVectorNumElements() - UndefElements.count()) <= 1)
4998 ConstSplatVal = (Ld.getOpcode() == ISD::Constant ||
4999 Ld.getOpcode() == ISD::ConstantFP);
5001 // Make sure that all of the users of a non-constant load are from the
5002 // BUILD_VECTOR node.
5003 if (!ConstSplatVal && !BVOp->isOnlyUserOf(Ld.getNode()))
5008 case ISD::VECTOR_SHUFFLE: {
5009 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
5011 // Shuffles must have a splat mask where the first element is
5013 if ((!SVOp->isSplat()) || SVOp->getMaskElt(0) != 0)
5016 SDValue Sc = Op.getOperand(0);
5017 if (Sc.getOpcode() != ISD::SCALAR_TO_VECTOR &&
5018 Sc.getOpcode() != ISD::BUILD_VECTOR) {
5020 if (!Subtarget->hasInt256())
5023 // Use the register form of the broadcast instruction available on AVX2.
5024 if (VT.getSizeInBits() >= 256)
5025 Sc = Extract128BitVector(Sc, 0, DAG, dl);
5026 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Sc);
5029 Ld = Sc.getOperand(0);
5030 ConstSplatVal = (Ld.getOpcode() == ISD::Constant ||
5031 Ld.getOpcode() == ISD::ConstantFP);
5033 // The scalar_to_vector node and the suspected
5034 // load node must have exactly one user.
5035 // Constants may have multiple users.
5037 // AVX-512 has register version of the broadcast
5038 bool hasRegVer = Subtarget->hasAVX512() && VT.is512BitVector() &&
5039 Ld.getValueType().getSizeInBits() >= 32;
5040 if (!ConstSplatVal && ((!Sc.hasOneUse() || !Ld.hasOneUse()) &&
5047 unsigned ScalarSize = Ld.getValueType().getSizeInBits();
5048 bool IsGE256 = (VT.getSizeInBits() >= 256);
5050 // When optimizing for size, generate up to 5 extra bytes for a broadcast
5051 // instruction to save 8 or more bytes of constant pool data.
5052 // TODO: If multiple splats are generated to load the same constant,
5053 // it may be detrimental to overall size. There needs to be a way to detect
5054 // that condition to know if this is truly a size win.
5055 const Function *F = DAG.getMachineFunction().getFunction();
5056 bool OptForSize = F->hasFnAttribute(Attribute::OptimizeForSize);
5058 // Handle broadcasting a single constant scalar from the constant pool
5060 // On Sandybridge (no AVX2), it is still better to load a constant vector
5061 // from the constant pool and not to broadcast it from a scalar.
5062 // But override that restriction when optimizing for size.
5063 // TODO: Check if splatting is recommended for other AVX-capable CPUs.
5064 if (ConstSplatVal && (Subtarget->hasAVX2() || OptForSize)) {
5065 EVT CVT = Ld.getValueType();
5066 assert(!CVT.isVector() && "Must not broadcast a vector type");
5068 // Splat f32, i32, v4f64, v4i64 in all cases with AVX2.
5069 // For size optimization, also splat v2f64 and v2i64, and for size opt
5070 // with AVX2, also splat i8 and i16.
5071 // With pattern matching, the VBROADCAST node may become a VMOVDDUP.
5072 if (ScalarSize == 32 || (IsGE256 && ScalarSize == 64) ||
5073 (OptForSize && (ScalarSize == 64 || Subtarget->hasAVX2()))) {
5074 const Constant *C = nullptr;
5075 if (ConstantSDNode *CI = dyn_cast<ConstantSDNode>(Ld))
5076 C = CI->getConstantIntValue();
5077 else if (ConstantFPSDNode *CF = dyn_cast<ConstantFPSDNode>(Ld))
5078 C = CF->getConstantFPValue();
5080 assert(C && "Invalid constant type");
5082 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
5083 SDValue CP = DAG.getConstantPool(C, TLI.getPointerTy());
5084 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
5085 Ld = DAG.getLoad(CVT, dl, DAG.getEntryNode(), CP,
5086 MachinePointerInfo::getConstantPool(),
5087 false, false, false, Alignment);
5089 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5093 bool IsLoad = ISD::isNormalLoad(Ld.getNode());
5095 // Handle AVX2 in-register broadcasts.
5096 if (!IsLoad && Subtarget->hasInt256() &&
5097 (ScalarSize == 32 || (IsGE256 && ScalarSize == 64)))
5098 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5100 // The scalar source must be a normal load.
5104 if (ScalarSize == 32 || (IsGE256 && ScalarSize == 64) ||
5105 (Subtarget->hasVLX() && ScalarSize == 64))
5106 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5108 // The integer check is needed for the 64-bit into 128-bit so it doesn't match
5109 // double since there is no vbroadcastsd xmm
5110 if (Subtarget->hasInt256() && Ld.getValueType().isInteger()) {
5111 if (ScalarSize == 8 || ScalarSize == 16 || ScalarSize == 64)
5112 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5115 // Unsupported broadcast.
5119 /// \brief For an EXTRACT_VECTOR_ELT with a constant index return the real
5120 /// underlying vector and index.
5122 /// Modifies \p ExtractedFromVec to the real vector and returns the real
5124 static int getUnderlyingExtractedFromVec(SDValue &ExtractedFromVec,
5126 int Idx = cast<ConstantSDNode>(ExtIdx)->getZExtValue();
5127 if (!isa<ShuffleVectorSDNode>(ExtractedFromVec))
5130 // For 256-bit vectors, LowerEXTRACT_VECTOR_ELT_SSE4 may have already
5132 // (extract_vector_elt (v8f32 %vreg1), Constant<6>)
5134 // (extract_vector_elt (vector_shuffle<2,u,u,u>
5135 // (extract_subvector (v8f32 %vreg0), Constant<4>),
5138 // In this case the vector is the extract_subvector expression and the index
5139 // is 2, as specified by the shuffle.
5140 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(ExtractedFromVec);
5141 SDValue ShuffleVec = SVOp->getOperand(0);
5142 MVT ShuffleVecVT = ShuffleVec.getSimpleValueType();
5143 assert(ShuffleVecVT.getVectorElementType() ==
5144 ExtractedFromVec.getSimpleValueType().getVectorElementType());
5146 int ShuffleIdx = SVOp->getMaskElt(Idx);
5147 if (isUndefOrInRange(ShuffleIdx, 0, ShuffleVecVT.getVectorNumElements())) {
5148 ExtractedFromVec = ShuffleVec;
5154 static SDValue buildFromShuffleMostly(SDValue Op, SelectionDAG &DAG) {
5155 MVT VT = Op.getSimpleValueType();
5157 // Skip if insert_vec_elt is not supported.
5158 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
5159 if (!TLI.isOperationLegalOrCustom(ISD::INSERT_VECTOR_ELT, VT))
5163 unsigned NumElems = Op.getNumOperands();
5167 SmallVector<unsigned, 4> InsertIndices;
5168 SmallVector<int, 8> Mask(NumElems, -1);
5170 for (unsigned i = 0; i != NumElems; ++i) {
5171 unsigned Opc = Op.getOperand(i).getOpcode();
5173 if (Opc == ISD::UNDEF)
5176 if (Opc != ISD::EXTRACT_VECTOR_ELT) {
5177 // Quit if more than 1 elements need inserting.
5178 if (InsertIndices.size() > 1)
5181 InsertIndices.push_back(i);
5185 SDValue ExtractedFromVec = Op.getOperand(i).getOperand(0);
5186 SDValue ExtIdx = Op.getOperand(i).getOperand(1);
5187 // Quit if non-constant index.
5188 if (!isa<ConstantSDNode>(ExtIdx))
5190 int Idx = getUnderlyingExtractedFromVec(ExtractedFromVec, ExtIdx);
5192 // Quit if extracted from vector of different type.
5193 if (ExtractedFromVec.getValueType() != VT)
5196 if (!VecIn1.getNode())
5197 VecIn1 = ExtractedFromVec;
5198 else if (VecIn1 != ExtractedFromVec) {
5199 if (!VecIn2.getNode())
5200 VecIn2 = ExtractedFromVec;
5201 else if (VecIn2 != ExtractedFromVec)
5202 // Quit if more than 2 vectors to shuffle
5206 if (ExtractedFromVec == VecIn1)
5208 else if (ExtractedFromVec == VecIn2)
5209 Mask[i] = Idx + NumElems;
5212 if (!VecIn1.getNode())
5215 VecIn2 = VecIn2.getNode() ? VecIn2 : DAG.getUNDEF(VT);
5216 SDValue NV = DAG.getVectorShuffle(VT, DL, VecIn1, VecIn2, &Mask[0]);
5217 for (unsigned i = 0, e = InsertIndices.size(); i != e; ++i) {
5218 unsigned Idx = InsertIndices[i];
5219 NV = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, VT, NV, Op.getOperand(Idx),
5220 DAG.getIntPtrConstant(Idx, DL));
5226 static SDValue ConvertI1VectorToInterger(SDValue Op, SelectionDAG &DAG) {
5227 assert(ISD::isBuildVectorOfConstantSDNodes(Op.getNode()) &&
5228 Op.getScalarValueSizeInBits() == 1 &&
5229 "Can not convert non-constant vector");
5230 uint64_t Immediate = 0;
5231 for (unsigned idx = 0, e = Op.getNumOperands(); idx < e; ++idx) {
5232 SDValue In = Op.getOperand(idx);
5233 if (In.getOpcode() != ISD::UNDEF)
5234 Immediate |= cast<ConstantSDNode>(In)->getZExtValue() << idx;
5238 MVT::getIntegerVT(std::max((int)Op.getValueType().getSizeInBits(), 8));
5239 return DAG.getConstant(Immediate, dl, VT);
5241 // Lower BUILD_VECTOR operation for v8i1 and v16i1 types.
5243 X86TargetLowering::LowerBUILD_VECTORvXi1(SDValue Op, SelectionDAG &DAG) const {
5245 MVT VT = Op.getSimpleValueType();
5246 assert((VT.getVectorElementType() == MVT::i1) &&
5247 "Unexpected type in LowerBUILD_VECTORvXi1!");
5250 if (ISD::isBuildVectorAllZeros(Op.getNode())) {
5251 SDValue Cst = DAG.getTargetConstant(0, dl, MVT::i1);
5252 SmallVector<SDValue, 16> Ops(VT.getVectorNumElements(), Cst);
5253 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
5256 if (ISD::isBuildVectorAllOnes(Op.getNode())) {
5257 SDValue Cst = DAG.getTargetConstant(1, dl, MVT::i1);
5258 SmallVector<SDValue, 16> Ops(VT.getVectorNumElements(), Cst);
5259 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
5262 if (ISD::isBuildVectorOfConstantSDNodes(Op.getNode())) {
5263 SDValue Imm = ConvertI1VectorToInterger(Op, DAG);
5264 if (Imm.getValueSizeInBits() == VT.getSizeInBits())
5265 return DAG.getBitcast(VT, Imm);
5266 SDValue ExtVec = DAG.getBitcast(MVT::v8i1, Imm);
5267 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, ExtVec,
5268 DAG.getIntPtrConstant(0, dl));
5271 // Vector has one or more non-const elements
5272 uint64_t Immediate = 0;
5273 SmallVector<unsigned, 16> NonConstIdx;
5274 bool IsSplat = true;
5275 bool HasConstElts = false;
5277 for (unsigned idx = 0, e = Op.getNumOperands(); idx < e; ++idx) {
5278 SDValue In = Op.getOperand(idx);
5279 if (In.getOpcode() == ISD::UNDEF)
5281 if (!isa<ConstantSDNode>(In))
5282 NonConstIdx.push_back(idx);
5284 Immediate |= cast<ConstantSDNode>(In)->getZExtValue() << idx;
5285 HasConstElts = true;
5289 else if (In != Op.getOperand(SplatIdx))
5293 // for splat use " (select i1 splat_elt, all-ones, all-zeroes)"
5295 return DAG.getNode(ISD::SELECT, dl, VT, Op.getOperand(SplatIdx),
5296 DAG.getConstant(1, dl, VT),
5297 DAG.getConstant(0, dl, VT));
5299 // insert elements one by one
5303 MVT ImmVT = MVT::getIntegerVT(std::max((int)VT.getSizeInBits(), 8));
5304 Imm = DAG.getConstant(Immediate, dl, ImmVT);
5306 else if (HasConstElts)
5307 Imm = DAG.getConstant(0, dl, VT);
5309 Imm = DAG.getUNDEF(VT);
5310 if (Imm.getValueSizeInBits() == VT.getSizeInBits())
5311 DstVec = DAG.getBitcast(VT, Imm);
5313 SDValue ExtVec = DAG.getBitcast(MVT::v8i1, Imm);
5314 DstVec = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, ExtVec,
5315 DAG.getIntPtrConstant(0, dl));
5318 for (unsigned i = 0; i < NonConstIdx.size(); ++i) {
5319 unsigned InsertIdx = NonConstIdx[i];
5320 DstVec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, DstVec,
5321 Op.getOperand(InsertIdx),
5322 DAG.getIntPtrConstant(InsertIdx, dl));
5327 /// \brief Return true if \p N implements a horizontal binop and return the
5328 /// operands for the horizontal binop into V0 and V1.
5330 /// This is a helper function of LowerToHorizontalOp().
5331 /// This function checks that the build_vector \p N in input implements a
5332 /// horizontal operation. Parameter \p Opcode defines the kind of horizontal
5333 /// operation to match.
5334 /// For example, if \p Opcode is equal to ISD::ADD, then this function
5335 /// checks if \p N implements a horizontal arithmetic add; if instead \p Opcode
5336 /// is equal to ISD::SUB, then this function checks if this is a horizontal
5339 /// This function only analyzes elements of \p N whose indices are
5340 /// in range [BaseIdx, LastIdx).
5341 static bool isHorizontalBinOp(const BuildVectorSDNode *N, unsigned Opcode,
5343 unsigned BaseIdx, unsigned LastIdx,
5344 SDValue &V0, SDValue &V1) {
5345 EVT VT = N->getValueType(0);
5347 assert(BaseIdx * 2 <= LastIdx && "Invalid Indices in input!");
5348 assert(VT.isVector() && VT.getVectorNumElements() >= LastIdx &&
5349 "Invalid Vector in input!");
5351 bool IsCommutable = (Opcode == ISD::ADD || Opcode == ISD::FADD);
5352 bool CanFold = true;
5353 unsigned ExpectedVExtractIdx = BaseIdx;
5354 unsigned NumElts = LastIdx - BaseIdx;
5355 V0 = DAG.getUNDEF(VT);
5356 V1 = DAG.getUNDEF(VT);
5358 // Check if N implements a horizontal binop.
5359 for (unsigned i = 0, e = NumElts; i != e && CanFold; ++i) {
5360 SDValue Op = N->getOperand(i + BaseIdx);
5363 if (Op->getOpcode() == ISD::UNDEF) {
5364 // Update the expected vector extract index.
5365 if (i * 2 == NumElts)
5366 ExpectedVExtractIdx = BaseIdx;
5367 ExpectedVExtractIdx += 2;
5371 CanFold = Op->getOpcode() == Opcode && Op->hasOneUse();
5376 SDValue Op0 = Op.getOperand(0);
5377 SDValue Op1 = Op.getOperand(1);
5379 // Try to match the following pattern:
5380 // (BINOP (extract_vector_elt A, I), (extract_vector_elt A, I+1))
5381 CanFold = (Op0.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
5382 Op1.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
5383 Op0.getOperand(0) == Op1.getOperand(0) &&
5384 isa<ConstantSDNode>(Op0.getOperand(1)) &&
5385 isa<ConstantSDNode>(Op1.getOperand(1)));
5389 unsigned I0 = cast<ConstantSDNode>(Op0.getOperand(1))->getZExtValue();
5390 unsigned I1 = cast<ConstantSDNode>(Op1.getOperand(1))->getZExtValue();
5392 if (i * 2 < NumElts) {
5393 if (V0.getOpcode() == ISD::UNDEF) {
5394 V0 = Op0.getOperand(0);
5395 if (V0.getValueType() != VT)
5399 if (V1.getOpcode() == ISD::UNDEF) {
5400 V1 = Op0.getOperand(0);
5401 if (V1.getValueType() != VT)
5404 if (i * 2 == NumElts)
5405 ExpectedVExtractIdx = BaseIdx;
5408 SDValue Expected = (i * 2 < NumElts) ? V0 : V1;
5409 if (I0 == ExpectedVExtractIdx)
5410 CanFold = I1 == I0 + 1 && Op0.getOperand(0) == Expected;
5411 else if (IsCommutable && I1 == ExpectedVExtractIdx) {
5412 // Try to match the following dag sequence:
5413 // (BINOP (extract_vector_elt A, I+1), (extract_vector_elt A, I))
5414 CanFold = I0 == I1 + 1 && Op1.getOperand(0) == Expected;
5418 ExpectedVExtractIdx += 2;
5424 /// \brief Emit a sequence of two 128-bit horizontal add/sub followed by
5425 /// a concat_vector.
5427 /// This is a helper function of LowerToHorizontalOp().
5428 /// This function expects two 256-bit vectors called V0 and V1.
5429 /// At first, each vector is split into two separate 128-bit vectors.
5430 /// Then, the resulting 128-bit vectors are used to implement two
5431 /// horizontal binary operations.
5433 /// The kind of horizontal binary operation is defined by \p X86Opcode.
5435 /// \p Mode specifies how the 128-bit parts of V0 and V1 are passed in input to
5436 /// the two new horizontal binop.
5437 /// When Mode is set, the first horizontal binop dag node would take as input
5438 /// the lower 128-bit of V0 and the upper 128-bit of V0. The second
5439 /// horizontal binop dag node would take as input the lower 128-bit of V1
5440 /// and the upper 128-bit of V1.
5442 /// HADD V0_LO, V0_HI
5443 /// HADD V1_LO, V1_HI
5445 /// Otherwise, the first horizontal binop dag node takes as input the lower
5446 /// 128-bit of V0 and the lower 128-bit of V1, and the second horizontal binop
5447 /// dag node takes the the upper 128-bit of V0 and the upper 128-bit of V1.
5449 /// HADD V0_LO, V1_LO
5450 /// HADD V0_HI, V1_HI
5452 /// If \p isUndefLO is set, then the algorithm propagates UNDEF to the lower
5453 /// 128-bits of the result. If \p isUndefHI is set, then UNDEF is propagated to
5454 /// the upper 128-bits of the result.
5455 static SDValue ExpandHorizontalBinOp(const SDValue &V0, const SDValue &V1,
5456 SDLoc DL, SelectionDAG &DAG,
5457 unsigned X86Opcode, bool Mode,
5458 bool isUndefLO, bool isUndefHI) {
5459 EVT VT = V0.getValueType();
5460 assert(VT.is256BitVector() && VT == V1.getValueType() &&
5461 "Invalid nodes in input!");
5463 unsigned NumElts = VT.getVectorNumElements();
5464 SDValue V0_LO = Extract128BitVector(V0, 0, DAG, DL);
5465 SDValue V0_HI = Extract128BitVector(V0, NumElts/2, DAG, DL);
5466 SDValue V1_LO = Extract128BitVector(V1, 0, DAG, DL);
5467 SDValue V1_HI = Extract128BitVector(V1, NumElts/2, DAG, DL);
5468 EVT NewVT = V0_LO.getValueType();
5470 SDValue LO = DAG.getUNDEF(NewVT);
5471 SDValue HI = DAG.getUNDEF(NewVT);
5474 // Don't emit a horizontal binop if the result is expected to be UNDEF.
5475 if (!isUndefLO && V0->getOpcode() != ISD::UNDEF)
5476 LO = DAG.getNode(X86Opcode, DL, NewVT, V0_LO, V0_HI);
5477 if (!isUndefHI && V1->getOpcode() != ISD::UNDEF)
5478 HI = DAG.getNode(X86Opcode, DL, NewVT, V1_LO, V1_HI);
5480 // Don't emit a horizontal binop if the result is expected to be UNDEF.
5481 if (!isUndefLO && (V0_LO->getOpcode() != ISD::UNDEF ||
5482 V1_LO->getOpcode() != ISD::UNDEF))
5483 LO = DAG.getNode(X86Opcode, DL, NewVT, V0_LO, V1_LO);
5485 if (!isUndefHI && (V0_HI->getOpcode() != ISD::UNDEF ||
5486 V1_HI->getOpcode() != ISD::UNDEF))
5487 HI = DAG.getNode(X86Opcode, DL, NewVT, V0_HI, V1_HI);
5490 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, LO, HI);
5493 /// Try to fold a build_vector that performs an 'addsub' to an X86ISD::ADDSUB
5495 static SDValue LowerToAddSub(const BuildVectorSDNode *BV,
5496 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
5497 EVT VT = BV->getValueType(0);
5498 if ((!Subtarget->hasSSE3() || (VT != MVT::v4f32 && VT != MVT::v2f64)) &&
5499 (!Subtarget->hasAVX() || (VT != MVT::v8f32 && VT != MVT::v4f64)))
5503 unsigned NumElts = VT.getVectorNumElements();
5504 SDValue InVec0 = DAG.getUNDEF(VT);
5505 SDValue InVec1 = DAG.getUNDEF(VT);
5507 assert((VT == MVT::v8f32 || VT == MVT::v4f64 || VT == MVT::v4f32 ||
5508 VT == MVT::v2f64) && "build_vector with an invalid type found!");
5510 // Odd-numbered elements in the input build vector are obtained from
5511 // adding two integer/float elements.
5512 // Even-numbered elements in the input build vector are obtained from
5513 // subtracting two integer/float elements.
5514 unsigned ExpectedOpcode = ISD::FSUB;
5515 unsigned NextExpectedOpcode = ISD::FADD;
5516 bool AddFound = false;
5517 bool SubFound = false;
5519 for (unsigned i = 0, e = NumElts; i != e; ++i) {
5520 SDValue Op = BV->getOperand(i);
5522 // Skip 'undef' values.
5523 unsigned Opcode = Op.getOpcode();
5524 if (Opcode == ISD::UNDEF) {
5525 std::swap(ExpectedOpcode, NextExpectedOpcode);
5529 // Early exit if we found an unexpected opcode.
5530 if (Opcode != ExpectedOpcode)
5533 SDValue Op0 = Op.getOperand(0);
5534 SDValue Op1 = Op.getOperand(1);
5536 // Try to match the following pattern:
5537 // (BINOP (extract_vector_elt A, i), (extract_vector_elt B, i))
5538 // Early exit if we cannot match that sequence.
5539 if (Op0.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
5540 Op1.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
5541 !isa<ConstantSDNode>(Op0.getOperand(1)) ||
5542 !isa<ConstantSDNode>(Op1.getOperand(1)) ||
5543 Op0.getOperand(1) != Op1.getOperand(1))
5546 unsigned I0 = cast<ConstantSDNode>(Op0.getOperand(1))->getZExtValue();
5550 // We found a valid add/sub node. Update the information accordingly.
5556 // Update InVec0 and InVec1.
5557 if (InVec0.getOpcode() == ISD::UNDEF) {
5558 InVec0 = Op0.getOperand(0);
5559 if (InVec0.getValueType() != VT)
5562 if (InVec1.getOpcode() == ISD::UNDEF) {
5563 InVec1 = Op1.getOperand(0);
5564 if (InVec1.getValueType() != VT)
5568 // Make sure that operands in input to each add/sub node always
5569 // come from a same pair of vectors.
5570 if (InVec0 != Op0.getOperand(0)) {
5571 if (ExpectedOpcode == ISD::FSUB)
5574 // FADD is commutable. Try to commute the operands
5575 // and then test again.
5576 std::swap(Op0, Op1);
5577 if (InVec0 != Op0.getOperand(0))
5581 if (InVec1 != Op1.getOperand(0))
5584 // Update the pair of expected opcodes.
5585 std::swap(ExpectedOpcode, NextExpectedOpcode);
5588 // Don't try to fold this build_vector into an ADDSUB if the inputs are undef.
5589 if (AddFound && SubFound && InVec0.getOpcode() != ISD::UNDEF &&
5590 InVec1.getOpcode() != ISD::UNDEF)
5591 return DAG.getNode(X86ISD::ADDSUB, DL, VT, InVec0, InVec1);
5596 /// Lower BUILD_VECTOR to a horizontal add/sub operation if possible.
5597 static SDValue LowerToHorizontalOp(const BuildVectorSDNode *BV,
5598 const X86Subtarget *Subtarget,
5599 SelectionDAG &DAG) {
5600 EVT VT = BV->getValueType(0);
5601 unsigned NumElts = VT.getVectorNumElements();
5602 unsigned NumUndefsLO = 0;
5603 unsigned NumUndefsHI = 0;
5604 unsigned Half = NumElts/2;
5606 // Count the number of UNDEF operands in the build_vector in input.
5607 for (unsigned i = 0, e = Half; i != e; ++i)
5608 if (BV->getOperand(i)->getOpcode() == ISD::UNDEF)
5611 for (unsigned i = Half, e = NumElts; i != e; ++i)
5612 if (BV->getOperand(i)->getOpcode() == ISD::UNDEF)
5615 // Early exit if this is either a build_vector of all UNDEFs or all the
5616 // operands but one are UNDEF.
5617 if (NumUndefsLO + NumUndefsHI + 1 >= NumElts)
5621 SDValue InVec0, InVec1;
5622 if ((VT == MVT::v4f32 || VT == MVT::v2f64) && Subtarget->hasSSE3()) {
5623 // Try to match an SSE3 float HADD/HSUB.
5624 if (isHorizontalBinOp(BV, ISD::FADD, DAG, 0, NumElts, InVec0, InVec1))
5625 return DAG.getNode(X86ISD::FHADD, DL, VT, InVec0, InVec1);
5627 if (isHorizontalBinOp(BV, ISD::FSUB, DAG, 0, NumElts, InVec0, InVec1))
5628 return DAG.getNode(X86ISD::FHSUB, DL, VT, InVec0, InVec1);
5629 } else if ((VT == MVT::v4i32 || VT == MVT::v8i16) && Subtarget->hasSSSE3()) {
5630 // Try to match an SSSE3 integer HADD/HSUB.
5631 if (isHorizontalBinOp(BV, ISD::ADD, DAG, 0, NumElts, InVec0, InVec1))
5632 return DAG.getNode(X86ISD::HADD, DL, VT, InVec0, InVec1);
5634 if (isHorizontalBinOp(BV, ISD::SUB, DAG, 0, NumElts, InVec0, InVec1))
5635 return DAG.getNode(X86ISD::HSUB, DL, VT, InVec0, InVec1);
5638 if (!Subtarget->hasAVX())
5641 if ((VT == MVT::v8f32 || VT == MVT::v4f64)) {
5642 // Try to match an AVX horizontal add/sub of packed single/double
5643 // precision floating point values from 256-bit vectors.
5644 SDValue InVec2, InVec3;
5645 if (isHorizontalBinOp(BV, ISD::FADD, DAG, 0, Half, InVec0, InVec1) &&
5646 isHorizontalBinOp(BV, ISD::FADD, DAG, Half, NumElts, InVec2, InVec3) &&
5647 ((InVec0.getOpcode() == ISD::UNDEF ||
5648 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
5649 ((InVec1.getOpcode() == ISD::UNDEF ||
5650 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
5651 return DAG.getNode(X86ISD::FHADD, DL, VT, InVec0, InVec1);
5653 if (isHorizontalBinOp(BV, ISD::FSUB, DAG, 0, Half, InVec0, InVec1) &&
5654 isHorizontalBinOp(BV, ISD::FSUB, DAG, Half, NumElts, InVec2, InVec3) &&
5655 ((InVec0.getOpcode() == ISD::UNDEF ||
5656 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
5657 ((InVec1.getOpcode() == ISD::UNDEF ||
5658 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
5659 return DAG.getNode(X86ISD::FHSUB, DL, VT, InVec0, InVec1);
5660 } else if (VT == MVT::v8i32 || VT == MVT::v16i16) {
5661 // Try to match an AVX2 horizontal add/sub of signed integers.
5662 SDValue InVec2, InVec3;
5664 bool CanFold = true;
5666 if (isHorizontalBinOp(BV, ISD::ADD, DAG, 0, Half, InVec0, InVec1) &&
5667 isHorizontalBinOp(BV, ISD::ADD, DAG, Half, NumElts, InVec2, InVec3) &&
5668 ((InVec0.getOpcode() == ISD::UNDEF ||
5669 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
5670 ((InVec1.getOpcode() == ISD::UNDEF ||
5671 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
5672 X86Opcode = X86ISD::HADD;
5673 else if (isHorizontalBinOp(BV, ISD::SUB, DAG, 0, Half, InVec0, InVec1) &&
5674 isHorizontalBinOp(BV, ISD::SUB, DAG, Half, NumElts, InVec2, InVec3) &&
5675 ((InVec0.getOpcode() == ISD::UNDEF ||
5676 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
5677 ((InVec1.getOpcode() == ISD::UNDEF ||
5678 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
5679 X86Opcode = X86ISD::HSUB;
5684 // Fold this build_vector into a single horizontal add/sub.
5685 // Do this only if the target has AVX2.
5686 if (Subtarget->hasAVX2())
5687 return DAG.getNode(X86Opcode, DL, VT, InVec0, InVec1);
5689 // Do not try to expand this build_vector into a pair of horizontal
5690 // add/sub if we can emit a pair of scalar add/sub.
5691 if (NumUndefsLO + 1 == Half || NumUndefsHI + 1 == Half)
5694 // Convert this build_vector into a pair of horizontal binop followed by
5696 bool isUndefLO = NumUndefsLO == Half;
5697 bool isUndefHI = NumUndefsHI == Half;
5698 return ExpandHorizontalBinOp(InVec0, InVec1, DL, DAG, X86Opcode, false,
5699 isUndefLO, isUndefHI);
5703 if ((VT == MVT::v8f32 || VT == MVT::v4f64 || VT == MVT::v8i32 ||
5704 VT == MVT::v16i16) && Subtarget->hasAVX()) {
5706 if (isHorizontalBinOp(BV, ISD::ADD, DAG, 0, NumElts, InVec0, InVec1))
5707 X86Opcode = X86ISD::HADD;
5708 else if (isHorizontalBinOp(BV, ISD::SUB, DAG, 0, NumElts, InVec0, InVec1))
5709 X86Opcode = X86ISD::HSUB;
5710 else if (isHorizontalBinOp(BV, ISD::FADD, DAG, 0, NumElts, InVec0, InVec1))
5711 X86Opcode = X86ISD::FHADD;
5712 else if (isHorizontalBinOp(BV, ISD::FSUB, DAG, 0, NumElts, InVec0, InVec1))
5713 X86Opcode = X86ISD::FHSUB;
5717 // Don't try to expand this build_vector into a pair of horizontal add/sub
5718 // if we can simply emit a pair of scalar add/sub.
5719 if (NumUndefsLO + 1 == Half || NumUndefsHI + 1 == Half)
5722 // Convert this build_vector into two horizontal add/sub followed by
5724 bool isUndefLO = NumUndefsLO == Half;
5725 bool isUndefHI = NumUndefsHI == Half;
5726 return ExpandHorizontalBinOp(InVec0, InVec1, DL, DAG, X86Opcode, true,
5727 isUndefLO, isUndefHI);
5734 X86TargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const {
5737 MVT VT = Op.getSimpleValueType();
5738 MVT ExtVT = VT.getVectorElementType();
5739 unsigned NumElems = Op.getNumOperands();
5741 // Generate vectors for predicate vectors.
5742 if (VT.getScalarType() == MVT::i1 && Subtarget->hasAVX512())
5743 return LowerBUILD_VECTORvXi1(Op, DAG);
5745 // Vectors containing all zeros can be matched by pxor and xorps later
5746 if (ISD::isBuildVectorAllZeros(Op.getNode())) {
5747 // Canonicalize this to <4 x i32> to 1) ensure the zero vectors are CSE'd
5748 // and 2) ensure that i64 scalars are eliminated on x86-32 hosts.
5749 if (VT == MVT::v4i32 || VT == MVT::v8i32 || VT == MVT::v16i32)
5752 return getZeroVector(VT, Subtarget, DAG, dl);
5755 // Vectors containing all ones can be matched by pcmpeqd on 128-bit width
5756 // vectors or broken into v4i32 operations on 256-bit vectors. AVX2 can use
5757 // vpcmpeqd on 256-bit vectors.
5758 if (Subtarget->hasSSE2() && ISD::isBuildVectorAllOnes(Op.getNode())) {
5759 if (VT == MVT::v4i32 || (VT == MVT::v8i32 && Subtarget->hasInt256()))
5762 if (!VT.is512BitVector())
5763 return getOnesVector(VT, Subtarget->hasInt256(), DAG, dl);
5766 BuildVectorSDNode *BV = cast<BuildVectorSDNode>(Op.getNode());
5767 if (SDValue AddSub = LowerToAddSub(BV, Subtarget, DAG))
5769 if (SDValue HorizontalOp = LowerToHorizontalOp(BV, Subtarget, DAG))
5770 return HorizontalOp;
5771 if (SDValue Broadcast = LowerVectorBroadcast(Op, Subtarget, DAG))
5774 unsigned EVTBits = ExtVT.getSizeInBits();
5776 unsigned NumZero = 0;
5777 unsigned NumNonZero = 0;
5778 unsigned NonZeros = 0;
5779 bool IsAllConstants = true;
5780 SmallSet<SDValue, 8> Values;
5781 for (unsigned i = 0; i < NumElems; ++i) {
5782 SDValue Elt = Op.getOperand(i);
5783 if (Elt.getOpcode() == ISD::UNDEF)
5786 if (Elt.getOpcode() != ISD::Constant &&
5787 Elt.getOpcode() != ISD::ConstantFP)
5788 IsAllConstants = false;
5789 if (X86::isZeroNode(Elt))
5792 NonZeros |= (1 << i);
5797 // All undef vector. Return an UNDEF. All zero vectors were handled above.
5798 if (NumNonZero == 0)
5799 return DAG.getUNDEF(VT);
5801 // Special case for single non-zero, non-undef, element.
5802 if (NumNonZero == 1) {
5803 unsigned Idx = countTrailingZeros(NonZeros);
5804 SDValue Item = Op.getOperand(Idx);
5806 // If this is an insertion of an i64 value on x86-32, and if the top bits of
5807 // the value are obviously zero, truncate the value to i32 and do the
5808 // insertion that way. Only do this if the value is non-constant or if the
5809 // value is a constant being inserted into element 0. It is cheaper to do
5810 // a constant pool load than it is to do a movd + shuffle.
5811 if (ExtVT == MVT::i64 && !Subtarget->is64Bit() &&
5812 (!IsAllConstants || Idx == 0)) {
5813 if (DAG.MaskedValueIsZero(Item, APInt::getBitsSet(64, 32, 64))) {
5815 assert(VT == MVT::v2i64 && "Expected an SSE value type!");
5816 EVT VecVT = MVT::v4i32;
5818 // Truncate the value (which may itself be a constant) to i32, and
5819 // convert it to a vector with movd (S2V+shuffle to zero extend).
5820 Item = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Item);
5821 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Item);
5822 return DAG.getBitcast(VT, getShuffleVectorZeroOrUndef(
5823 Item, Idx * 2, true, Subtarget, DAG));
5827 // If we have a constant or non-constant insertion into the low element of
5828 // a vector, we can do this with SCALAR_TO_VECTOR + shuffle of zero into
5829 // the rest of the elements. This will be matched as movd/movq/movss/movsd
5830 // depending on what the source datatype is.
5833 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
5835 if (ExtVT == MVT::i32 || ExtVT == MVT::f32 || ExtVT == MVT::f64 ||
5836 (ExtVT == MVT::i64 && Subtarget->is64Bit())) {
5837 if (VT.is512BitVector()) {
5838 SDValue ZeroVec = getZeroVector(VT, Subtarget, DAG, dl);
5839 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, ZeroVec,
5840 Item, DAG.getIntPtrConstant(0, dl));
5842 assert((VT.is128BitVector() || VT.is256BitVector()) &&
5843 "Expected an SSE value type!");
5844 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
5845 // Turn it into a MOVL (i.e. movss, movsd, or movd) to a zero vector.
5846 return getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
5849 // We can't directly insert an i8 or i16 into a vector, so zero extend
5851 if (ExtVT == MVT::i16 || ExtVT == MVT::i8) {
5852 Item = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Item);
5853 if (VT.is256BitVector()) {
5854 if (Subtarget->hasAVX()) {
5855 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v8i32, Item);
5856 Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
5858 // Without AVX, we need to extend to a 128-bit vector and then
5859 // insert into the 256-bit vector.
5860 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, Item);
5861 SDValue ZeroVec = getZeroVector(MVT::v8i32, Subtarget, DAG, dl);
5862 Item = Insert128BitVector(ZeroVec, Item, 0, DAG, dl);
5865 assert(VT.is128BitVector() && "Expected an SSE value type!");
5866 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, Item);
5867 Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
5869 return DAG.getBitcast(VT, Item);
5873 // Is it a vector logical left shift?
5874 if (NumElems == 2 && Idx == 1 &&
5875 X86::isZeroNode(Op.getOperand(0)) &&
5876 !X86::isZeroNode(Op.getOperand(1))) {
5877 unsigned NumBits = VT.getSizeInBits();
5878 return getVShift(true, VT,
5879 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
5880 VT, Op.getOperand(1)),
5881 NumBits/2, DAG, *this, dl);
5884 if (IsAllConstants) // Otherwise, it's better to do a constpool load.
5887 // Otherwise, if this is a vector with i32 or f32 elements, and the element
5888 // is a non-constant being inserted into an element other than the low one,
5889 // we can't use a constant pool load. Instead, use SCALAR_TO_VECTOR (aka
5890 // movd/movss) to move this into the low element, then shuffle it into
5892 if (EVTBits == 32) {
5893 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
5894 return getShuffleVectorZeroOrUndef(Item, Idx, NumZero > 0, Subtarget, DAG);
5898 // Splat is obviously ok. Let legalizer expand it to a shuffle.
5899 if (Values.size() == 1) {
5900 if (EVTBits == 32) {
5901 // Instead of a shuffle like this:
5902 // shuffle (scalar_to_vector (load (ptr + 4))), undef, <0, 0, 0, 0>
5903 // Check if it's possible to issue this instead.
5904 // shuffle (vload ptr)), undef, <1, 1, 1, 1>
5905 unsigned Idx = countTrailingZeros(NonZeros);
5906 SDValue Item = Op.getOperand(Idx);
5907 if (Op.getNode()->isOnlyUserOf(Item.getNode()))
5908 return LowerAsSplatVectorLoad(Item, VT, dl, DAG);
5913 // A vector full of immediates; various special cases are already
5914 // handled, so this is best done with a single constant-pool load.
5918 // For AVX-length vectors, see if we can use a vector load to get all of the
5919 // elements, otherwise build the individual 128-bit pieces and use
5920 // shuffles to put them in place.
5921 if (VT.is256BitVector() || VT.is512BitVector()) {
5922 SmallVector<SDValue, 64> V(Op->op_begin(), Op->op_begin() + NumElems);
5924 // Check for a build vector of consecutive loads.
5925 if (SDValue LD = EltsFromConsecutiveLoads(VT, V, dl, DAG, false))
5928 EVT HVT = EVT::getVectorVT(*DAG.getContext(), ExtVT, NumElems/2);
5930 // Build both the lower and upper subvector.
5931 SDValue Lower = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT,
5932 makeArrayRef(&V[0], NumElems/2));
5933 SDValue Upper = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT,
5934 makeArrayRef(&V[NumElems / 2], NumElems/2));
5936 // Recreate the wider vector with the lower and upper part.
5937 if (VT.is256BitVector())
5938 return Concat128BitVectors(Lower, Upper, VT, NumElems, DAG, dl);
5939 return Concat256BitVectors(Lower, Upper, VT, NumElems, DAG, dl);
5942 // Let legalizer expand 2-wide build_vectors.
5943 if (EVTBits == 64) {
5944 if (NumNonZero == 1) {
5945 // One half is zero or undef.
5946 unsigned Idx = countTrailingZeros(NonZeros);
5947 SDValue V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT,
5948 Op.getOperand(Idx));
5949 return getShuffleVectorZeroOrUndef(V2, Idx, true, Subtarget, DAG);
5954 // If element VT is < 32 bits, convert it to inserts into a zero vector.
5955 if (EVTBits == 8 && NumElems == 16)
5956 if (SDValue V = LowerBuildVectorv16i8(Op, NonZeros,NumNonZero,NumZero, DAG,
5960 if (EVTBits == 16 && NumElems == 8)
5961 if (SDValue V = LowerBuildVectorv8i16(Op, NonZeros,NumNonZero,NumZero, DAG,
5965 // If element VT is == 32 bits and has 4 elems, try to generate an INSERTPS
5966 if (EVTBits == 32 && NumElems == 4)
5967 if (SDValue V = LowerBuildVectorv4x32(Op, DAG, Subtarget, *this))
5970 // If element VT is == 32 bits, turn it into a number of shuffles.
5971 SmallVector<SDValue, 8> V(NumElems);
5972 if (NumElems == 4 && NumZero > 0) {
5973 for (unsigned i = 0; i < 4; ++i) {
5974 bool isZero = !(NonZeros & (1 << i));
5976 V[i] = getZeroVector(VT, Subtarget, DAG, dl);
5978 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
5981 for (unsigned i = 0; i < 2; ++i) {
5982 switch ((NonZeros & (0x3 << i*2)) >> (i*2)) {
5985 V[i] = V[i*2]; // Must be a zero vector.
5988 V[i] = getMOVL(DAG, dl, VT, V[i*2+1], V[i*2]);
5991 V[i] = getMOVL(DAG, dl, VT, V[i*2], V[i*2+1]);
5994 V[i] = getUnpackl(DAG, dl, VT, V[i*2], V[i*2+1]);
5999 bool Reverse1 = (NonZeros & 0x3) == 2;
6000 bool Reverse2 = ((NonZeros & (0x3 << 2)) >> 2) == 2;
6004 static_cast<int>(Reverse2 ? NumElems+1 : NumElems),
6005 static_cast<int>(Reverse2 ? NumElems : NumElems+1)
6007 return DAG.getVectorShuffle(VT, dl, V[0], V[1], &MaskVec[0]);
6010 if (Values.size() > 1 && VT.is128BitVector()) {
6011 // Check for a build vector of consecutive loads.
6012 for (unsigned i = 0; i < NumElems; ++i)
6013 V[i] = Op.getOperand(i);
6015 // Check for elements which are consecutive loads.
6016 if (SDValue LD = EltsFromConsecutiveLoads(VT, V, dl, DAG, false))
6019 // Check for a build vector from mostly shuffle plus few inserting.
6020 if (SDValue Sh = buildFromShuffleMostly(Op, DAG))
6023 // For SSE 4.1, use insertps to put the high elements into the low element.
6024 if (Subtarget->hasSSE41()) {
6026 if (Op.getOperand(0).getOpcode() != ISD::UNDEF)
6027 Result = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(0));
6029 Result = DAG.getUNDEF(VT);
6031 for (unsigned i = 1; i < NumElems; ++i) {
6032 if (Op.getOperand(i).getOpcode() == ISD::UNDEF) continue;
6033 Result = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Result,
6034 Op.getOperand(i), DAG.getIntPtrConstant(i, dl));
6039 // Otherwise, expand into a number of unpckl*, start by extending each of
6040 // our (non-undef) elements to the full vector width with the element in the
6041 // bottom slot of the vector (which generates no code for SSE).
6042 for (unsigned i = 0; i < NumElems; ++i) {
6043 if (Op.getOperand(i).getOpcode() != ISD::UNDEF)
6044 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
6046 V[i] = DAG.getUNDEF(VT);
6049 // Next, we iteratively mix elements, e.g. for v4f32:
6050 // Step 1: unpcklps 0, 2 ==> X: <?, ?, 2, 0>
6051 // : unpcklps 1, 3 ==> Y: <?, ?, 3, 1>
6052 // Step 2: unpcklps X, Y ==> <3, 2, 1, 0>
6053 unsigned EltStride = NumElems >> 1;
6054 while (EltStride != 0) {
6055 for (unsigned i = 0; i < EltStride; ++i) {
6056 // If V[i+EltStride] is undef and this is the first round of mixing,
6057 // then it is safe to just drop this shuffle: V[i] is already in the
6058 // right place, the one element (since it's the first round) being
6059 // inserted as undef can be dropped. This isn't safe for successive
6060 // rounds because they will permute elements within both vectors.
6061 if (V[i+EltStride].getOpcode() == ISD::UNDEF &&
6062 EltStride == NumElems/2)
6065 V[i] = getUnpackl(DAG, dl, VT, V[i], V[i + EltStride]);
6074 // LowerAVXCONCAT_VECTORS - 256-bit AVX can use the vinsertf128 instruction
6075 // to create 256-bit vectors from two other 128-bit ones.
6076 static SDValue LowerAVXCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
6078 MVT ResVT = Op.getSimpleValueType();
6080 assert((ResVT.is256BitVector() ||
6081 ResVT.is512BitVector()) && "Value type must be 256-/512-bit wide");
6083 SDValue V1 = Op.getOperand(0);
6084 SDValue V2 = Op.getOperand(1);
6085 unsigned NumElems = ResVT.getVectorNumElements();
6086 if (ResVT.is256BitVector())
6087 return Concat128BitVectors(V1, V2, ResVT, NumElems, DAG, dl);
6089 if (Op.getNumOperands() == 4) {
6090 MVT HalfVT = MVT::getVectorVT(ResVT.getScalarType(),
6091 ResVT.getVectorNumElements()/2);
6092 SDValue V3 = Op.getOperand(2);
6093 SDValue V4 = Op.getOperand(3);
6094 return Concat256BitVectors(Concat128BitVectors(V1, V2, HalfVT, NumElems/2, DAG, dl),
6095 Concat128BitVectors(V3, V4, HalfVT, NumElems/2, DAG, dl), ResVT, NumElems, DAG, dl);
6097 return Concat256BitVectors(V1, V2, ResVT, NumElems, DAG, dl);
6100 static SDValue LowerCONCAT_VECTORSvXi1(SDValue Op,
6101 const X86Subtarget *Subtarget,
6102 SelectionDAG & DAG) {
6104 MVT ResVT = Op.getSimpleValueType();
6105 unsigned NumOfOperands = Op.getNumOperands();
6107 assert(isPowerOf2_32(NumOfOperands) &&
6108 "Unexpected number of operands in CONCAT_VECTORS");
6110 if (NumOfOperands > 2) {
6111 MVT HalfVT = MVT::getVectorVT(ResVT.getScalarType(),
6112 ResVT.getVectorNumElements()/2);
6113 SmallVector<SDValue, 2> Ops;
6114 for (unsigned i = 0; i < NumOfOperands/2; i++)
6115 Ops.push_back(Op.getOperand(i));
6116 SDValue Lo = DAG.getNode(ISD::CONCAT_VECTORS, dl, HalfVT, Ops);
6118 for (unsigned i = NumOfOperands/2; i < NumOfOperands; i++)
6119 Ops.push_back(Op.getOperand(i));
6120 SDValue Hi = DAG.getNode(ISD::CONCAT_VECTORS, dl, HalfVT, Ops);
6121 return DAG.getNode(ISD::CONCAT_VECTORS, dl, ResVT, Lo, Hi);
6124 SDValue V1 = Op.getOperand(0);
6125 SDValue V2 = Op.getOperand(1);
6126 bool IsZeroV1 = ISD::isBuildVectorAllZeros(V1.getNode());
6127 bool IsZeroV2 = ISD::isBuildVectorAllZeros(V2.getNode());
6129 if (IsZeroV1 && IsZeroV2)
6130 return getZeroVector(ResVT, Subtarget, DAG, dl);
6132 SDValue ZeroIdx = DAG.getIntPtrConstant(0, dl);
6133 SDValue Undef = DAG.getUNDEF(ResVT);
6134 unsigned NumElems = ResVT.getVectorNumElements();
6135 SDValue ShiftBits = DAG.getConstant(NumElems/2, dl, MVT::i8);
6137 V2 = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResVT, Undef, V2, ZeroIdx);
6138 V2 = DAG.getNode(X86ISD::VSHLI, dl, ResVT, V2, ShiftBits);
6142 V1 = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResVT, Undef, V1, ZeroIdx);
6143 // Zero the upper bits of V1
6144 V1 = DAG.getNode(X86ISD::VSHLI, dl, ResVT, V1, ShiftBits);
6145 V1 = DAG.getNode(X86ISD::VSRLI, dl, ResVT, V1, ShiftBits);
6148 return DAG.getNode(ISD::OR, dl, ResVT, V1, V2);
6151 static SDValue LowerCONCAT_VECTORS(SDValue Op,
6152 const X86Subtarget *Subtarget,
6153 SelectionDAG &DAG) {
6154 MVT VT = Op.getSimpleValueType();
6155 if (VT.getVectorElementType() == MVT::i1)
6156 return LowerCONCAT_VECTORSvXi1(Op, Subtarget, DAG);
6158 assert((VT.is256BitVector() && Op.getNumOperands() == 2) ||
6159 (VT.is512BitVector() && (Op.getNumOperands() == 2 ||
6160 Op.getNumOperands() == 4)));
6162 // AVX can use the vinsertf128 instruction to create 256-bit vectors
6163 // from two other 128-bit ones.
6165 // 512-bit vector may contain 2 256-bit vectors or 4 128-bit vectors
6166 return LowerAVXCONCAT_VECTORS(Op, DAG);
6170 //===----------------------------------------------------------------------===//
6171 // Vector shuffle lowering
6173 // This is an experimental code path for lowering vector shuffles on x86. It is
6174 // designed to handle arbitrary vector shuffles and blends, gracefully
6175 // degrading performance as necessary. It works hard to recognize idiomatic
6176 // shuffles and lower them to optimal instruction patterns without leaving
6177 // a framework that allows reasonably efficient handling of all vector shuffle
6179 //===----------------------------------------------------------------------===//
6181 /// \brief Tiny helper function to identify a no-op mask.
6183 /// This is a somewhat boring predicate function. It checks whether the mask
6184 /// array input, which is assumed to be a single-input shuffle mask of the kind
6185 /// used by the X86 shuffle instructions (not a fully general
6186 /// ShuffleVectorSDNode mask) requires any shuffles to occur. Both undef and an
6187 /// in-place shuffle are 'no-op's.
6188 static bool isNoopShuffleMask(ArrayRef<int> Mask) {
6189 for (int i = 0, Size = Mask.size(); i < Size; ++i)
6190 if (Mask[i] != -1 && Mask[i] != i)
6195 /// \brief Helper function to classify a mask as a single-input mask.
6197 /// This isn't a generic single-input test because in the vector shuffle
6198 /// lowering we canonicalize single inputs to be the first input operand. This
6199 /// means we can more quickly test for a single input by only checking whether
6200 /// an input from the second operand exists. We also assume that the size of
6201 /// mask corresponds to the size of the input vectors which isn't true in the
6202 /// fully general case.
6203 static bool isSingleInputShuffleMask(ArrayRef<int> Mask) {
6205 if (M >= (int)Mask.size())
6210 /// \brief Test whether there are elements crossing 128-bit lanes in this
6213 /// X86 divides up its shuffles into in-lane and cross-lane shuffle operations
6214 /// and we routinely test for these.
6215 static bool is128BitLaneCrossingShuffleMask(MVT VT, ArrayRef<int> Mask) {
6216 int LaneSize = 128 / VT.getScalarSizeInBits();
6217 int Size = Mask.size();
6218 for (int i = 0; i < Size; ++i)
6219 if (Mask[i] >= 0 && (Mask[i] % Size) / LaneSize != i / LaneSize)
6224 /// \brief Test whether a shuffle mask is equivalent within each 128-bit lane.
6226 /// This checks a shuffle mask to see if it is performing the same
6227 /// 128-bit lane-relative shuffle in each 128-bit lane. This trivially implies
6228 /// that it is also not lane-crossing. It may however involve a blend from the
6229 /// same lane of a second vector.
6231 /// The specific repeated shuffle mask is populated in \p RepeatedMask, as it is
6232 /// non-trivial to compute in the face of undef lanes. The representation is
6233 /// *not* suitable for use with existing 128-bit shuffles as it will contain
6234 /// entries from both V1 and V2 inputs to the wider mask.
6236 is128BitLaneRepeatedShuffleMask(MVT VT, ArrayRef<int> Mask,
6237 SmallVectorImpl<int> &RepeatedMask) {
6238 int LaneSize = 128 / VT.getScalarSizeInBits();
6239 RepeatedMask.resize(LaneSize, -1);
6240 int Size = Mask.size();
6241 for (int i = 0; i < Size; ++i) {
6244 if ((Mask[i] % Size) / LaneSize != i / LaneSize)
6245 // This entry crosses lanes, so there is no way to model this shuffle.
6248 // Ok, handle the in-lane shuffles by detecting if and when they repeat.
6249 if (RepeatedMask[i % LaneSize] == -1)
6250 // This is the first non-undef entry in this slot of a 128-bit lane.
6251 RepeatedMask[i % LaneSize] =
6252 Mask[i] < Size ? Mask[i] % LaneSize : Mask[i] % LaneSize + Size;
6253 else if (RepeatedMask[i % LaneSize] + (i / LaneSize) * LaneSize != Mask[i])
6254 // Found a mismatch with the repeated mask.
6260 /// \brief Test whether a shuffle mask is equivalent within each 256-bit lane.
6262 /// This checks a shuffle mask to see if it is performing the same
6263 /// 256-bit lane-relative shuffle in each 256-bit lane. This trivially implies
6264 /// that it is also not lane-crossing. It may however involve a blend from the
6265 /// same lane of a second vector.
6267 /// The specific repeated shuffle mask is populated in \p RepeatedMask, as it is
6268 /// non-trivial to compute in the face of undef lanes. The representation is
6269 /// *not* suitable for use with existing 256-bit shuffles as it will contain
6270 /// entries from both V1 and V2 inputs to the wider mask.
6272 is256BitLaneRepeatedShuffleMask(MVT VT, ArrayRef<int> Mask,
6273 SmallVectorImpl<int> &RepeatedMask) {
6274 int LaneSize = 256 / VT.getScalarSizeInBits();
6275 RepeatedMask.resize(LaneSize, -1);
6276 int Size = Mask.size();
6277 for (int i = 0; i < Size; ++i) {
6280 if ((Mask[i] % Size) / LaneSize != i / LaneSize)
6281 // This entry crosses lanes, so there is no way to model this shuffle.
6284 // Ok, handle the in-lane shuffles by detecting if and when they repeat.
6285 if (RepeatedMask[i % LaneSize] == -1)
6286 // This is the first non-undef entry in this slot of a 256-bit lane.
6287 RepeatedMask[i % LaneSize] =
6288 Mask[i] < Size ? Mask[i] % LaneSize : Mask[i] % LaneSize + Size;
6289 else if (RepeatedMask[i % LaneSize] + (i / LaneSize) * LaneSize != Mask[i])
6290 // Found a mismatch with the repeated mask.
6296 /// \brief Checks whether a shuffle mask is equivalent to an explicit list of
6299 /// This is a fast way to test a shuffle mask against a fixed pattern:
6301 /// if (isShuffleEquivalent(Mask, 3, 2, {1, 0})) { ... }
6303 /// It returns true if the mask is exactly as wide as the argument list, and
6304 /// each element of the mask is either -1 (signifying undef) or the value given
6305 /// in the argument.
6306 static bool isShuffleEquivalent(SDValue V1, SDValue V2, ArrayRef<int> Mask,
6307 ArrayRef<int> ExpectedMask) {
6308 if (Mask.size() != ExpectedMask.size())
6311 int Size = Mask.size();
6313 // If the values are build vectors, we can look through them to find
6314 // equivalent inputs that make the shuffles equivalent.
6315 auto *BV1 = dyn_cast<BuildVectorSDNode>(V1);
6316 auto *BV2 = dyn_cast<BuildVectorSDNode>(V2);
6318 for (int i = 0; i < Size; ++i)
6319 if (Mask[i] != -1 && Mask[i] != ExpectedMask[i]) {
6320 auto *MaskBV = Mask[i] < Size ? BV1 : BV2;
6321 auto *ExpectedBV = ExpectedMask[i] < Size ? BV1 : BV2;
6322 if (!MaskBV || !ExpectedBV ||
6323 MaskBV->getOperand(Mask[i] % Size) !=
6324 ExpectedBV->getOperand(ExpectedMask[i] % Size))
6331 /// \brief Get a 4-lane 8-bit shuffle immediate for a mask.
6333 /// This helper function produces an 8-bit shuffle immediate corresponding to
6334 /// the ubiquitous shuffle encoding scheme used in x86 instructions for
6335 /// shuffling 4 lanes. It can be used with most of the PSHUF instructions for
6338 /// NB: We rely heavily on "undef" masks preserving the input lane.
6339 static SDValue getV4X86ShuffleImm8ForMask(ArrayRef<int> Mask, SDLoc DL,
6340 SelectionDAG &DAG) {
6341 assert(Mask.size() == 4 && "Only 4-lane shuffle masks");
6342 assert(Mask[0] >= -1 && Mask[0] < 4 && "Out of bound mask element!");
6343 assert(Mask[1] >= -1 && Mask[1] < 4 && "Out of bound mask element!");
6344 assert(Mask[2] >= -1 && Mask[2] < 4 && "Out of bound mask element!");
6345 assert(Mask[3] >= -1 && Mask[3] < 4 && "Out of bound mask element!");
6348 Imm |= (Mask[0] == -1 ? 0 : Mask[0]) << 0;
6349 Imm |= (Mask[1] == -1 ? 1 : Mask[1]) << 2;
6350 Imm |= (Mask[2] == -1 ? 2 : Mask[2]) << 4;
6351 Imm |= (Mask[3] == -1 ? 3 : Mask[3]) << 6;
6352 return DAG.getConstant(Imm, DL, MVT::i8);
6355 /// \brief Get a 8-bit shuffle, 1 bit per lane, immediate for a mask.
6357 /// This helper function produces an 8-bit shuffle immediate corresponding to
6358 /// the ubiquitous shuffle encoding scheme used in x86 instructions for
6359 /// shuffling 8 lanes.
6360 static SDValue get1bitLaneShuffleImm8ForMask(ArrayRef<int> Mask, SDLoc DL,
6361 SelectionDAG &DAG) {
6362 assert(Mask.size() <= 8 &&
6363 "Up to 8 elts may be in Imm8 1-bit lane shuffle mask");
6365 for (unsigned i = 0; i < Mask.size(); ++i)
6367 Imm |= (Mask[i] % 2) << i;
6368 return DAG.getConstant(Imm, DL, MVT::i8);
6371 /// \brief Try to emit a blend instruction for a shuffle using bit math.
6373 /// This is used as a fallback approach when first class blend instructions are
6374 /// unavailable. Currently it is only suitable for integer vectors, but could
6375 /// be generalized for floating point vectors if desirable.
6376 static SDValue lowerVectorShuffleAsBitBlend(SDLoc DL, MVT VT, SDValue V1,
6377 SDValue V2, ArrayRef<int> Mask,
6378 SelectionDAG &DAG) {
6379 assert(VT.isInteger() && "Only supports integer vector types!");
6380 MVT EltVT = VT.getScalarType();
6381 int NumEltBits = EltVT.getSizeInBits();
6382 SDValue Zero = DAG.getConstant(0, DL, EltVT);
6383 SDValue AllOnes = DAG.getConstant(APInt::getAllOnesValue(NumEltBits), DL,
6385 SmallVector<SDValue, 16> MaskOps;
6386 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
6387 if (Mask[i] != -1 && Mask[i] != i && Mask[i] != i + Size)
6388 return SDValue(); // Shuffled input!
6389 MaskOps.push_back(Mask[i] < Size ? AllOnes : Zero);
6392 SDValue V1Mask = DAG.getNode(ISD::BUILD_VECTOR, DL, VT, MaskOps);
6393 V1 = DAG.getNode(ISD::AND, DL, VT, V1, V1Mask);
6394 // We have to cast V2 around.
6395 MVT MaskVT = MVT::getVectorVT(MVT::i64, VT.getSizeInBits() / 64);
6396 V2 = DAG.getBitcast(VT, DAG.getNode(X86ISD::ANDNP, DL, MaskVT,
6397 DAG.getBitcast(MaskVT, V1Mask),
6398 DAG.getBitcast(MaskVT, V2)));
6399 return DAG.getNode(ISD::OR, DL, VT, V1, V2);
6402 /// \brief Try to emit a blend instruction for a shuffle.
6404 /// This doesn't do any checks for the availability of instructions for blending
6405 /// these values. It relies on the availability of the X86ISD::BLENDI pattern to
6406 /// be matched in the backend with the type given. What it does check for is
6407 /// that the shuffle mask is in fact a blend.
6408 static SDValue lowerVectorShuffleAsBlend(SDLoc DL, MVT VT, SDValue V1,
6409 SDValue V2, ArrayRef<int> Mask,
6410 const X86Subtarget *Subtarget,
6411 SelectionDAG &DAG) {
6412 unsigned BlendMask = 0;
6413 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
6414 if (Mask[i] >= Size) {
6415 if (Mask[i] != i + Size)
6416 return SDValue(); // Shuffled V2 input!
6417 BlendMask |= 1u << i;
6420 if (Mask[i] >= 0 && Mask[i] != i)
6421 return SDValue(); // Shuffled V1 input!
6423 switch (VT.SimpleTy) {
6428 return DAG.getNode(X86ISD::BLENDI, DL, VT, V1, V2,
6429 DAG.getConstant(BlendMask, DL, MVT::i8));
6433 assert(Subtarget->hasAVX2() && "256-bit integer blends require AVX2!");
6437 // If we have AVX2 it is faster to use VPBLENDD when the shuffle fits into
6438 // that instruction.
6439 if (Subtarget->hasAVX2()) {
6440 // Scale the blend by the number of 32-bit dwords per element.
6441 int Scale = VT.getScalarSizeInBits() / 32;
6443 for (int i = 0, Size = Mask.size(); i < Size; ++i)
6444 if (Mask[i] >= Size)
6445 for (int j = 0; j < Scale; ++j)
6446 BlendMask |= 1u << (i * Scale + j);
6448 MVT BlendVT = VT.getSizeInBits() > 128 ? MVT::v8i32 : MVT::v4i32;
6449 V1 = DAG.getBitcast(BlendVT, V1);
6450 V2 = DAG.getBitcast(BlendVT, V2);
6451 return DAG.getBitcast(
6452 VT, DAG.getNode(X86ISD::BLENDI, DL, BlendVT, V1, V2,
6453 DAG.getConstant(BlendMask, DL, MVT::i8)));
6457 // For integer shuffles we need to expand the mask and cast the inputs to
6458 // v8i16s prior to blending.
6459 int Scale = 8 / VT.getVectorNumElements();
6461 for (int i = 0, Size = Mask.size(); i < Size; ++i)
6462 if (Mask[i] >= Size)
6463 for (int j = 0; j < Scale; ++j)
6464 BlendMask |= 1u << (i * Scale + j);
6466 V1 = DAG.getBitcast(MVT::v8i16, V1);
6467 V2 = DAG.getBitcast(MVT::v8i16, V2);
6468 return DAG.getBitcast(VT,
6469 DAG.getNode(X86ISD::BLENDI, DL, MVT::v8i16, V1, V2,
6470 DAG.getConstant(BlendMask, DL, MVT::i8)));
6474 assert(Subtarget->hasAVX2() && "256-bit integer blends require AVX2!");
6475 SmallVector<int, 8> RepeatedMask;
6476 if (is128BitLaneRepeatedShuffleMask(MVT::v16i16, Mask, RepeatedMask)) {
6477 // We can lower these with PBLENDW which is mirrored across 128-bit lanes.
6478 assert(RepeatedMask.size() == 8 && "Repeated mask size doesn't match!");
6480 for (int i = 0; i < 8; ++i)
6481 if (RepeatedMask[i] >= 16)
6482 BlendMask |= 1u << i;
6483 return DAG.getNode(X86ISD::BLENDI, DL, MVT::v16i16, V1, V2,
6484 DAG.getConstant(BlendMask, DL, MVT::i8));
6490 assert((VT.getSizeInBits() == 128 || Subtarget->hasAVX2()) &&
6491 "256-bit byte-blends require AVX2 support!");
6493 // Scale the blend by the number of bytes per element.
6494 int Scale = VT.getScalarSizeInBits() / 8;
6496 // This form of blend is always done on bytes. Compute the byte vector
6498 MVT BlendVT = MVT::getVectorVT(MVT::i8, VT.getSizeInBits() / 8);
6500 // Compute the VSELECT mask. Note that VSELECT is really confusing in the
6501 // mix of LLVM's code generator and the x86 backend. We tell the code
6502 // generator that boolean values in the elements of an x86 vector register
6503 // are -1 for true and 0 for false. We then use the LLVM semantics of 'true'
6504 // mapping a select to operand #1, and 'false' mapping to operand #2. The
6505 // reality in x86 is that vector masks (pre-AVX-512) use only the high bit
6506 // of the element (the remaining are ignored) and 0 in that high bit would
6507 // mean operand #1 while 1 in the high bit would mean operand #2. So while
6508 // the LLVM model for boolean values in vector elements gets the relevant
6509 // bit set, it is set backwards and over constrained relative to x86's
6511 SmallVector<SDValue, 32> VSELECTMask;
6512 for (int i = 0, Size = Mask.size(); i < Size; ++i)
6513 for (int j = 0; j < Scale; ++j)
6514 VSELECTMask.push_back(
6515 Mask[i] < 0 ? DAG.getUNDEF(MVT::i8)
6516 : DAG.getConstant(Mask[i] < Size ? -1 : 0, DL,
6519 V1 = DAG.getBitcast(BlendVT, V1);
6520 V2 = DAG.getBitcast(BlendVT, V2);
6521 return DAG.getBitcast(VT, DAG.getNode(ISD::VSELECT, DL, BlendVT,
6522 DAG.getNode(ISD::BUILD_VECTOR, DL,
6523 BlendVT, VSELECTMask),
6528 llvm_unreachable("Not a supported integer vector type!");
6532 /// \brief Try to lower as a blend of elements from two inputs followed by
6533 /// a single-input permutation.
6535 /// This matches the pattern where we can blend elements from two inputs and
6536 /// then reduce the shuffle to a single-input permutation.
6537 static SDValue lowerVectorShuffleAsBlendAndPermute(SDLoc DL, MVT VT, SDValue V1,
6540 SelectionDAG &DAG) {
6541 // We build up the blend mask while checking whether a blend is a viable way
6542 // to reduce the shuffle.
6543 SmallVector<int, 32> BlendMask(Mask.size(), -1);
6544 SmallVector<int, 32> PermuteMask(Mask.size(), -1);
6546 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
6550 assert(Mask[i] < Size * 2 && "Shuffle input is out of bounds.");
6552 if (BlendMask[Mask[i] % Size] == -1)
6553 BlendMask[Mask[i] % Size] = Mask[i];
6554 else if (BlendMask[Mask[i] % Size] != Mask[i])
6555 return SDValue(); // Can't blend in the needed input!
6557 PermuteMask[i] = Mask[i] % Size;
6560 SDValue V = DAG.getVectorShuffle(VT, DL, V1, V2, BlendMask);
6561 return DAG.getVectorShuffle(VT, DL, V, DAG.getUNDEF(VT), PermuteMask);
6564 /// \brief Generic routine to decompose a shuffle and blend into indepndent
6565 /// blends and permutes.
6567 /// This matches the extremely common pattern for handling combined
6568 /// shuffle+blend operations on newer X86 ISAs where we have very fast blend
6569 /// operations. It will try to pick the best arrangement of shuffles and
6571 static SDValue lowerVectorShuffleAsDecomposedShuffleBlend(SDLoc DL, MVT VT,
6575 SelectionDAG &DAG) {
6576 // Shuffle the input elements into the desired positions in V1 and V2 and
6577 // blend them together.
6578 SmallVector<int, 32> V1Mask(Mask.size(), -1);
6579 SmallVector<int, 32> V2Mask(Mask.size(), -1);
6580 SmallVector<int, 32> BlendMask(Mask.size(), -1);
6581 for (int i = 0, Size = Mask.size(); i < Size; ++i)
6582 if (Mask[i] >= 0 && Mask[i] < Size) {
6583 V1Mask[i] = Mask[i];
6585 } else if (Mask[i] >= Size) {
6586 V2Mask[i] = Mask[i] - Size;
6587 BlendMask[i] = i + Size;
6590 // Try to lower with the simpler initial blend strategy unless one of the
6591 // input shuffles would be a no-op. We prefer to shuffle inputs as the
6592 // shuffle may be able to fold with a load or other benefit. However, when
6593 // we'll have to do 2x as many shuffles in order to achieve this, blending
6594 // first is a better strategy.
6595 if (!isNoopShuffleMask(V1Mask) && !isNoopShuffleMask(V2Mask))
6596 if (SDValue BlendPerm =
6597 lowerVectorShuffleAsBlendAndPermute(DL, VT, V1, V2, Mask, DAG))
6600 V1 = DAG.getVectorShuffle(VT, DL, V1, DAG.getUNDEF(VT), V1Mask);
6601 V2 = DAG.getVectorShuffle(VT, DL, V2, DAG.getUNDEF(VT), V2Mask);
6602 return DAG.getVectorShuffle(VT, DL, V1, V2, BlendMask);
6605 /// \brief Try to lower a vector shuffle as a byte rotation.
6607 /// SSSE3 has a generic PALIGNR instruction in x86 that will do an arbitrary
6608 /// byte-rotation of the concatenation of two vectors; pre-SSSE3 can use
6609 /// a PSRLDQ/PSLLDQ/POR pattern to get a similar effect. This routine will
6610 /// try to generically lower a vector shuffle through such an pattern. It
6611 /// does not check for the profitability of lowering either as PALIGNR or
6612 /// PSRLDQ/PSLLDQ/POR, only whether the mask is valid to lower in that form.
6613 /// This matches shuffle vectors that look like:
6615 /// v8i16 [11, 12, 13, 14, 15, 0, 1, 2]
6617 /// Essentially it concatenates V1 and V2, shifts right by some number of
6618 /// elements, and takes the low elements as the result. Note that while this is
6619 /// specified as a *right shift* because x86 is little-endian, it is a *left
6620 /// rotate* of the vector lanes.
6621 static SDValue lowerVectorShuffleAsByteRotate(SDLoc DL, MVT VT, SDValue V1,
6624 const X86Subtarget *Subtarget,
6625 SelectionDAG &DAG) {
6626 assert(!isNoopShuffleMask(Mask) && "We shouldn't lower no-op shuffles!");
6628 int NumElts = Mask.size();
6629 int NumLanes = VT.getSizeInBits() / 128;
6630 int NumLaneElts = NumElts / NumLanes;
6632 // We need to detect various ways of spelling a rotation:
6633 // [11, 12, 13, 14, 15, 0, 1, 2]
6634 // [-1, 12, 13, 14, -1, -1, 1, -1]
6635 // [-1, -1, -1, -1, -1, -1, 1, 2]
6636 // [ 3, 4, 5, 6, 7, 8, 9, 10]
6637 // [-1, 4, 5, 6, -1, -1, 9, -1]
6638 // [-1, 4, 5, 6, -1, -1, -1, -1]
6641 for (int l = 0; l < NumElts; l += NumLaneElts) {
6642 for (int i = 0; i < NumLaneElts; ++i) {
6643 if (Mask[l + i] == -1)
6645 assert(Mask[l + i] >= 0 && "Only -1 is a valid negative mask element!");
6647 // Get the mod-Size index and lane correct it.
6648 int LaneIdx = (Mask[l + i] % NumElts) - l;
6649 // Make sure it was in this lane.
6650 if (LaneIdx < 0 || LaneIdx >= NumLaneElts)
6653 // Determine where a rotated vector would have started.
6654 int StartIdx = i - LaneIdx;
6656 // The identity rotation isn't interesting, stop.
6659 // If we found the tail of a vector the rotation must be the missing
6660 // front. If we found the head of a vector, it must be how much of the
6662 int CandidateRotation = StartIdx < 0 ? -StartIdx : NumLaneElts - StartIdx;
6665 Rotation = CandidateRotation;
6666 else if (Rotation != CandidateRotation)
6667 // The rotations don't match, so we can't match this mask.
6670 // Compute which value this mask is pointing at.
6671 SDValue MaskV = Mask[l + i] < NumElts ? V1 : V2;
6673 // Compute which of the two target values this index should be assigned
6674 // to. This reflects whether the high elements are remaining or the low
6675 // elements are remaining.
6676 SDValue &TargetV = StartIdx < 0 ? Hi : Lo;
6678 // Either set up this value if we've not encountered it before, or check
6679 // that it remains consistent.
6682 else if (TargetV != MaskV)
6683 // This may be a rotation, but it pulls from the inputs in some
6684 // unsupported interleaving.
6689 // Check that we successfully analyzed the mask, and normalize the results.
6690 assert(Rotation != 0 && "Failed to locate a viable rotation!");
6691 assert((Lo || Hi) && "Failed to find a rotated input vector!");
6697 // The actual rotate instruction rotates bytes, so we need to scale the
6698 // rotation based on how many bytes are in the vector lane.
6699 int Scale = 16 / NumLaneElts;
6701 // SSSE3 targets can use the palignr instruction.
6702 if (Subtarget->hasSSSE3()) {
6703 // Cast the inputs to i8 vector of correct length to match PALIGNR.
6704 MVT AlignVT = MVT::getVectorVT(MVT::i8, 16 * NumLanes);
6705 Lo = DAG.getBitcast(AlignVT, Lo);
6706 Hi = DAG.getBitcast(AlignVT, Hi);
6708 return DAG.getBitcast(
6709 VT, DAG.getNode(X86ISD::PALIGNR, DL, AlignVT, Hi, Lo,
6710 DAG.getConstant(Rotation * Scale, DL, MVT::i8)));
6713 assert(VT.getSizeInBits() == 128 &&
6714 "Rotate-based lowering only supports 128-bit lowering!");
6715 assert(Mask.size() <= 16 &&
6716 "Can shuffle at most 16 bytes in a 128-bit vector!");
6718 // Default SSE2 implementation
6719 int LoByteShift = 16 - Rotation * Scale;
6720 int HiByteShift = Rotation * Scale;
6722 // Cast the inputs to v2i64 to match PSLLDQ/PSRLDQ.
6723 Lo = DAG.getBitcast(MVT::v2i64, Lo);
6724 Hi = DAG.getBitcast(MVT::v2i64, Hi);
6726 SDValue LoShift = DAG.getNode(X86ISD::VSHLDQ, DL, MVT::v2i64, Lo,
6727 DAG.getConstant(LoByteShift, DL, MVT::i8));
6728 SDValue HiShift = DAG.getNode(X86ISD::VSRLDQ, DL, MVT::v2i64, Hi,
6729 DAG.getConstant(HiByteShift, DL, MVT::i8));
6730 return DAG.getBitcast(VT,
6731 DAG.getNode(ISD::OR, DL, MVT::v2i64, LoShift, HiShift));
6734 /// \brief Compute whether each element of a shuffle is zeroable.
6736 /// A "zeroable" vector shuffle element is one which can be lowered to zero.
6737 /// Either it is an undef element in the shuffle mask, the element of the input
6738 /// referenced is undef, or the element of the input referenced is known to be
6739 /// zero. Many x86 shuffles can zero lanes cheaply and we often want to handle
6740 /// as many lanes with this technique as possible to simplify the remaining
6742 static SmallBitVector computeZeroableShuffleElements(ArrayRef<int> Mask,
6743 SDValue V1, SDValue V2) {
6744 SmallBitVector Zeroable(Mask.size(), false);
6746 while (V1.getOpcode() == ISD::BITCAST)
6747 V1 = V1->getOperand(0);
6748 while (V2.getOpcode() == ISD::BITCAST)
6749 V2 = V2->getOperand(0);
6751 bool V1IsZero = ISD::isBuildVectorAllZeros(V1.getNode());
6752 bool V2IsZero = ISD::isBuildVectorAllZeros(V2.getNode());
6754 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
6756 // Handle the easy cases.
6757 if (M < 0 || (M >= 0 && M < Size && V1IsZero) || (M >= Size && V2IsZero)) {
6762 // If this is an index into a build_vector node (which has the same number
6763 // of elements), dig out the input value and use it.
6764 SDValue V = M < Size ? V1 : V2;
6765 if (V.getOpcode() != ISD::BUILD_VECTOR || Size != (int)V.getNumOperands())
6768 SDValue Input = V.getOperand(M % Size);
6769 // The UNDEF opcode check really should be dead code here, but not quite
6770 // worth asserting on (it isn't invalid, just unexpected).
6771 if (Input.getOpcode() == ISD::UNDEF || X86::isZeroNode(Input))
6778 /// \brief Try to emit a bitmask instruction for a shuffle.
6780 /// This handles cases where we can model a blend exactly as a bitmask due to
6781 /// one of the inputs being zeroable.
6782 static SDValue lowerVectorShuffleAsBitMask(SDLoc DL, MVT VT, SDValue V1,
6783 SDValue V2, ArrayRef<int> Mask,
6784 SelectionDAG &DAG) {
6785 MVT EltVT = VT.getScalarType();
6786 int NumEltBits = EltVT.getSizeInBits();
6787 MVT IntEltVT = MVT::getIntegerVT(NumEltBits);
6788 SDValue Zero = DAG.getConstant(0, DL, IntEltVT);
6789 SDValue AllOnes = DAG.getConstant(APInt::getAllOnesValue(NumEltBits), DL,
6791 if (EltVT.isFloatingPoint()) {
6792 Zero = DAG.getBitcast(EltVT, Zero);
6793 AllOnes = DAG.getBitcast(EltVT, AllOnes);
6795 SmallVector<SDValue, 16> VMaskOps(Mask.size(), Zero);
6796 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
6798 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
6801 if (Mask[i] % Size != i)
6802 return SDValue(); // Not a blend.
6804 V = Mask[i] < Size ? V1 : V2;
6805 else if (V != (Mask[i] < Size ? V1 : V2))
6806 return SDValue(); // Can only let one input through the mask.
6808 VMaskOps[i] = AllOnes;
6811 return SDValue(); // No non-zeroable elements!
6813 SDValue VMask = DAG.getNode(ISD::BUILD_VECTOR, DL, VT, VMaskOps);
6814 V = DAG.getNode(VT.isFloatingPoint()
6815 ? (unsigned) X86ISD::FAND : (unsigned) ISD::AND,
6820 /// \brief Try to lower a vector shuffle as a bit shift (shifts in zeros).
6822 /// Attempts to match a shuffle mask against the PSLL(W/D/Q/DQ) and
6823 /// PSRL(W/D/Q/DQ) SSE2 and AVX2 logical bit-shift instructions. The function
6824 /// matches elements from one of the input vectors shuffled to the left or
6825 /// right with zeroable elements 'shifted in'. It handles both the strictly
6826 /// bit-wise element shifts and the byte shift across an entire 128-bit double
6829 /// PSHL : (little-endian) left bit shift.
6830 /// [ zz, 0, zz, 2 ]
6831 /// [ -1, 4, zz, -1 ]
6832 /// PSRL : (little-endian) right bit shift.
6834 /// [ -1, -1, 7, zz]
6835 /// PSLLDQ : (little-endian) left byte shift
6836 /// [ zz, 0, 1, 2, 3, 4, 5, 6]
6837 /// [ zz, zz, -1, -1, 2, 3, 4, -1]
6838 /// [ zz, zz, zz, zz, zz, zz, -1, 1]
6839 /// PSRLDQ : (little-endian) right byte shift
6840 /// [ 5, 6, 7, zz, zz, zz, zz, zz]
6841 /// [ -1, 5, 6, 7, zz, zz, zz, zz]
6842 /// [ 1, 2, -1, -1, -1, -1, zz, zz]
6843 static SDValue lowerVectorShuffleAsShift(SDLoc DL, MVT VT, SDValue V1,
6844 SDValue V2, ArrayRef<int> Mask,
6845 SelectionDAG &DAG) {
6846 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
6848 int Size = Mask.size();
6849 assert(Size == (int)VT.getVectorNumElements() && "Unexpected mask size");
6851 auto CheckZeros = [&](int Shift, int Scale, bool Left) {
6852 for (int i = 0; i < Size; i += Scale)
6853 for (int j = 0; j < Shift; ++j)
6854 if (!Zeroable[i + j + (Left ? 0 : (Scale - Shift))])
6860 auto MatchShift = [&](int Shift, int Scale, bool Left, SDValue V) {
6861 for (int i = 0; i != Size; i += Scale) {
6862 unsigned Pos = Left ? i + Shift : i;
6863 unsigned Low = Left ? i : i + Shift;
6864 unsigned Len = Scale - Shift;
6865 if (!isSequentialOrUndefInRange(Mask, Pos, Len,
6866 Low + (V == V1 ? 0 : Size)))
6870 int ShiftEltBits = VT.getScalarSizeInBits() * Scale;
6871 bool ByteShift = ShiftEltBits > 64;
6872 unsigned OpCode = Left ? (ByteShift ? X86ISD::VSHLDQ : X86ISD::VSHLI)
6873 : (ByteShift ? X86ISD::VSRLDQ : X86ISD::VSRLI);
6874 int ShiftAmt = Shift * VT.getScalarSizeInBits() / (ByteShift ? 8 : 1);
6876 // Normalize the scale for byte shifts to still produce an i64 element
6878 Scale = ByteShift ? Scale / 2 : Scale;
6880 // We need to round trip through the appropriate type for the shift.
6881 MVT ShiftSVT = MVT::getIntegerVT(VT.getScalarSizeInBits() * Scale);
6882 MVT ShiftVT = MVT::getVectorVT(ShiftSVT, Size / Scale);
6883 assert(DAG.getTargetLoweringInfo().isTypeLegal(ShiftVT) &&
6884 "Illegal integer vector type");
6885 V = DAG.getBitcast(ShiftVT, V);
6887 V = DAG.getNode(OpCode, DL, ShiftVT, V,
6888 DAG.getConstant(ShiftAmt, DL, MVT::i8));
6889 return DAG.getBitcast(VT, V);
6892 // SSE/AVX supports logical shifts up to 64-bit integers - so we can just
6893 // keep doubling the size of the integer elements up to that. We can
6894 // then shift the elements of the integer vector by whole multiples of
6895 // their width within the elements of the larger integer vector. Test each
6896 // multiple to see if we can find a match with the moved element indices
6897 // and that the shifted in elements are all zeroable.
6898 for (int Scale = 2; Scale * VT.getScalarSizeInBits() <= 128; Scale *= 2)
6899 for (int Shift = 1; Shift != Scale; ++Shift)
6900 for (bool Left : {true, false})
6901 if (CheckZeros(Shift, Scale, Left))
6902 for (SDValue V : {V1, V2})
6903 if (SDValue Match = MatchShift(Shift, Scale, Left, V))
6910 /// \brief Lower a vector shuffle as a zero or any extension.
6912 /// Given a specific number of elements, element bit width, and extension
6913 /// stride, produce either a zero or any extension based on the available
6914 /// features of the subtarget.
6915 static SDValue lowerVectorShuffleAsSpecificZeroOrAnyExtend(
6916 SDLoc DL, MVT VT, int Scale, bool AnyExt, SDValue InputV,
6917 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
6918 assert(Scale > 1 && "Need a scale to extend.");
6919 int NumElements = VT.getVectorNumElements();
6920 int EltBits = VT.getScalarSizeInBits();
6921 assert((EltBits == 8 || EltBits == 16 || EltBits == 32) &&
6922 "Only 8, 16, and 32 bit elements can be extended.");
6923 assert(Scale * EltBits <= 64 && "Cannot zero extend past 64 bits.");
6925 // Found a valid zext mask! Try various lowering strategies based on the
6926 // input type and available ISA extensions.
6927 if (Subtarget->hasSSE41()) {
6928 MVT ExtVT = MVT::getVectorVT(MVT::getIntegerVT(EltBits * Scale),
6929 NumElements / Scale);
6930 return DAG.getBitcast(VT, DAG.getNode(X86ISD::VZEXT, DL, ExtVT, InputV));
6933 // For any extends we can cheat for larger element sizes and use shuffle
6934 // instructions that can fold with a load and/or copy.
6935 if (AnyExt && EltBits == 32) {
6936 int PSHUFDMask[4] = {0, -1, 1, -1};
6937 return DAG.getBitcast(
6938 VT, DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32,
6939 DAG.getBitcast(MVT::v4i32, InputV),
6940 getV4X86ShuffleImm8ForMask(PSHUFDMask, DL, DAG)));
6942 if (AnyExt && EltBits == 16 && Scale > 2) {
6943 int PSHUFDMask[4] = {0, -1, 0, -1};
6944 InputV = DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32,
6945 DAG.getBitcast(MVT::v4i32, InputV),
6946 getV4X86ShuffleImm8ForMask(PSHUFDMask, DL, DAG));
6947 int PSHUFHWMask[4] = {1, -1, -1, -1};
6948 return DAG.getBitcast(
6949 VT, DAG.getNode(X86ISD::PSHUFHW, DL, MVT::v8i16,
6950 DAG.getBitcast(MVT::v8i16, InputV),
6951 getV4X86ShuffleImm8ForMask(PSHUFHWMask, DL, DAG)));
6954 // If this would require more than 2 unpack instructions to expand, use
6955 // pshufb when available. We can only use more than 2 unpack instructions
6956 // when zero extending i8 elements which also makes it easier to use pshufb.
6957 if (Scale > 4 && EltBits == 8 && Subtarget->hasSSSE3()) {
6958 assert(NumElements == 16 && "Unexpected byte vector width!");
6959 SDValue PSHUFBMask[16];
6960 for (int i = 0; i < 16; ++i)
6962 DAG.getConstant((i % Scale == 0) ? i / Scale : 0x80, DL, MVT::i8);
6963 InputV = DAG.getBitcast(MVT::v16i8, InputV);
6964 return DAG.getBitcast(VT,
6965 DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8, InputV,
6966 DAG.getNode(ISD::BUILD_VECTOR, DL,
6967 MVT::v16i8, PSHUFBMask)));
6970 // Otherwise emit a sequence of unpacks.
6972 MVT InputVT = MVT::getVectorVT(MVT::getIntegerVT(EltBits), NumElements);
6973 SDValue Ext = AnyExt ? DAG.getUNDEF(InputVT)
6974 : getZeroVector(InputVT, Subtarget, DAG, DL);
6975 InputV = DAG.getBitcast(InputVT, InputV);
6976 InputV = DAG.getNode(X86ISD::UNPCKL, DL, InputVT, InputV, Ext);
6980 } while (Scale > 1);
6981 return DAG.getBitcast(VT, InputV);
6984 /// \brief Try to lower a vector shuffle as a zero extension on any microarch.
6986 /// This routine will try to do everything in its power to cleverly lower
6987 /// a shuffle which happens to match the pattern of a zero extend. It doesn't
6988 /// check for the profitability of this lowering, it tries to aggressively
6989 /// match this pattern. It will use all of the micro-architectural details it
6990 /// can to emit an efficient lowering. It handles both blends with all-zero
6991 /// inputs to explicitly zero-extend and undef-lanes (sometimes undef due to
6992 /// masking out later).
6994 /// The reason we have dedicated lowering for zext-style shuffles is that they
6995 /// are both incredibly common and often quite performance sensitive.
6996 static SDValue lowerVectorShuffleAsZeroOrAnyExtend(
6997 SDLoc DL, MVT VT, SDValue V1, SDValue V2, ArrayRef<int> Mask,
6998 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
6999 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
7001 int Bits = VT.getSizeInBits();
7002 int NumElements = VT.getVectorNumElements();
7003 assert(VT.getScalarSizeInBits() <= 32 &&
7004 "Exceeds 32-bit integer zero extension limit");
7005 assert((int)Mask.size() == NumElements && "Unexpected shuffle mask size");
7007 // Define a helper function to check a particular ext-scale and lower to it if
7009 auto Lower = [&](int Scale) -> SDValue {
7012 for (int i = 0; i < NumElements; ++i) {
7014 continue; // Valid anywhere but doesn't tell us anything.
7015 if (i % Scale != 0) {
7016 // Each of the extended elements need to be zeroable.
7020 // We no longer are in the anyext case.
7025 // Each of the base elements needs to be consecutive indices into the
7026 // same input vector.
7027 SDValue V = Mask[i] < NumElements ? V1 : V2;
7030 else if (InputV != V)
7031 return SDValue(); // Flip-flopping inputs.
7033 if (Mask[i] % NumElements != i / Scale)
7034 return SDValue(); // Non-consecutive strided elements.
7037 // If we fail to find an input, we have a zero-shuffle which should always
7038 // have already been handled.
7039 // FIXME: Maybe handle this here in case during blending we end up with one?
7043 return lowerVectorShuffleAsSpecificZeroOrAnyExtend(
7044 DL, VT, Scale, AnyExt, InputV, Subtarget, DAG);
7047 // The widest scale possible for extending is to a 64-bit integer.
7048 assert(Bits % 64 == 0 &&
7049 "The number of bits in a vector must be divisible by 64 on x86!");
7050 int NumExtElements = Bits / 64;
7052 // Each iteration, try extending the elements half as much, but into twice as
7054 for (; NumExtElements < NumElements; NumExtElements *= 2) {
7055 assert(NumElements % NumExtElements == 0 &&
7056 "The input vector size must be divisible by the extended size.");
7057 if (SDValue V = Lower(NumElements / NumExtElements))
7061 // General extends failed, but 128-bit vectors may be able to use MOVQ.
7065 // Returns one of the source operands if the shuffle can be reduced to a
7066 // MOVQ, copying the lower 64-bits and zero-extending to the upper 64-bits.
7067 auto CanZExtLowHalf = [&]() {
7068 for (int i = NumElements / 2; i != NumElements; ++i)
7071 if (isSequentialOrUndefInRange(Mask, 0, NumElements / 2, 0))
7073 if (isSequentialOrUndefInRange(Mask, 0, NumElements / 2, NumElements))
7078 if (SDValue V = CanZExtLowHalf()) {
7079 V = DAG.getBitcast(MVT::v2i64, V);
7080 V = DAG.getNode(X86ISD::VZEXT_MOVL, DL, MVT::v2i64, V);
7081 return DAG.getBitcast(VT, V);
7084 // No viable ext lowering found.
7088 /// \brief Try to get a scalar value for a specific element of a vector.
7090 /// Looks through BUILD_VECTOR and SCALAR_TO_VECTOR nodes to find a scalar.
7091 static SDValue getScalarValueForVectorElement(SDValue V, int Idx,
7092 SelectionDAG &DAG) {
7093 MVT VT = V.getSimpleValueType();
7094 MVT EltVT = VT.getVectorElementType();
7095 while (V.getOpcode() == ISD::BITCAST)
7096 V = V.getOperand(0);
7097 // If the bitcasts shift the element size, we can't extract an equivalent
7099 MVT NewVT = V.getSimpleValueType();
7100 if (!NewVT.isVector() || NewVT.getScalarSizeInBits() != VT.getScalarSizeInBits())
7103 if (V.getOpcode() == ISD::BUILD_VECTOR ||
7104 (Idx == 0 && V.getOpcode() == ISD::SCALAR_TO_VECTOR)) {
7105 // Ensure the scalar operand is the same size as the destination.
7106 // FIXME: Add support for scalar truncation where possible.
7107 SDValue S = V.getOperand(Idx);
7108 if (EltVT.getSizeInBits() == S.getSimpleValueType().getSizeInBits())
7109 return DAG.getNode(ISD::BITCAST, SDLoc(V), EltVT, S);
7115 /// \brief Helper to test for a load that can be folded with x86 shuffles.
7117 /// This is particularly important because the set of instructions varies
7118 /// significantly based on whether the operand is a load or not.
7119 static bool isShuffleFoldableLoad(SDValue V) {
7120 while (V.getOpcode() == ISD::BITCAST)
7121 V = V.getOperand(0);
7123 return ISD::isNON_EXTLoad(V.getNode());
7126 /// \brief Try to lower insertion of a single element into a zero vector.
7128 /// This is a common pattern that we have especially efficient patterns to lower
7129 /// across all subtarget feature sets.
7130 static SDValue lowerVectorShuffleAsElementInsertion(
7131 SDLoc DL, MVT VT, SDValue V1, SDValue V2, ArrayRef<int> Mask,
7132 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
7133 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
7135 MVT EltVT = VT.getVectorElementType();
7137 int V2Index = std::find_if(Mask.begin(), Mask.end(),
7138 [&Mask](int M) { return M >= (int)Mask.size(); }) -
7140 bool IsV1Zeroable = true;
7141 for (int i = 0, Size = Mask.size(); i < Size; ++i)
7142 if (i != V2Index && !Zeroable[i]) {
7143 IsV1Zeroable = false;
7147 // Check for a single input from a SCALAR_TO_VECTOR node.
7148 // FIXME: All of this should be canonicalized into INSERT_VECTOR_ELT and
7149 // all the smarts here sunk into that routine. However, the current
7150 // lowering of BUILD_VECTOR makes that nearly impossible until the old
7151 // vector shuffle lowering is dead.
7152 if (SDValue V2S = getScalarValueForVectorElement(
7153 V2, Mask[V2Index] - Mask.size(), DAG)) {
7154 // We need to zext the scalar if it is smaller than an i32.
7155 V2S = DAG.getBitcast(EltVT, V2S);
7156 if (EltVT == MVT::i8 || EltVT == MVT::i16) {
7157 // Using zext to expand a narrow element won't work for non-zero
7162 // Zero-extend directly to i32.
7164 V2S = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i32, V2S);
7166 V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, ExtVT, V2S);
7167 } else if (Mask[V2Index] != (int)Mask.size() || EltVT == MVT::i8 ||
7168 EltVT == MVT::i16) {
7169 // Either not inserting from the low element of the input or the input
7170 // element size is too small to use VZEXT_MOVL to clear the high bits.
7174 if (!IsV1Zeroable) {
7175 // If V1 can't be treated as a zero vector we have fewer options to lower
7176 // this. We can't support integer vectors or non-zero targets cheaply, and
7177 // the V1 elements can't be permuted in any way.
7178 assert(VT == ExtVT && "Cannot change extended type when non-zeroable!");
7179 if (!VT.isFloatingPoint() || V2Index != 0)
7181 SmallVector<int, 8> V1Mask(Mask.begin(), Mask.end());
7182 V1Mask[V2Index] = -1;
7183 if (!isNoopShuffleMask(V1Mask))
7185 // This is essentially a special case blend operation, but if we have
7186 // general purpose blend operations, they are always faster. Bail and let
7187 // the rest of the lowering handle these as blends.
7188 if (Subtarget->hasSSE41())
7191 // Otherwise, use MOVSD or MOVSS.
7192 assert((EltVT == MVT::f32 || EltVT == MVT::f64) &&
7193 "Only two types of floating point element types to handle!");
7194 return DAG.getNode(EltVT == MVT::f32 ? X86ISD::MOVSS : X86ISD::MOVSD, DL,
7198 // This lowering only works for the low element with floating point vectors.
7199 if (VT.isFloatingPoint() && V2Index != 0)
7202 V2 = DAG.getNode(X86ISD::VZEXT_MOVL, DL, ExtVT, V2);
7204 V2 = DAG.getBitcast(VT, V2);
7207 // If we have 4 or fewer lanes we can cheaply shuffle the element into
7208 // the desired position. Otherwise it is more efficient to do a vector
7209 // shift left. We know that we can do a vector shift left because all
7210 // the inputs are zero.
7211 if (VT.isFloatingPoint() || VT.getVectorNumElements() <= 4) {
7212 SmallVector<int, 4> V2Shuffle(Mask.size(), 1);
7213 V2Shuffle[V2Index] = 0;
7214 V2 = DAG.getVectorShuffle(VT, DL, V2, DAG.getUNDEF(VT), V2Shuffle);
7216 V2 = DAG.getBitcast(MVT::v2i64, V2);
7218 X86ISD::VSHLDQ, DL, MVT::v2i64, V2,
7220 V2Index * EltVT.getSizeInBits()/8, DL,
7221 DAG.getTargetLoweringInfo().getScalarShiftAmountTy(MVT::v2i64)));
7222 V2 = DAG.getBitcast(VT, V2);
7228 /// \brief Try to lower broadcast of a single element.
7230 /// For convenience, this code also bundles all of the subtarget feature set
7231 /// filtering. While a little annoying to re-dispatch on type here, there isn't
7232 /// a convenient way to factor it out.
7233 static SDValue lowerVectorShuffleAsBroadcast(SDLoc DL, MVT VT, SDValue V,
7235 const X86Subtarget *Subtarget,
7236 SelectionDAG &DAG) {
7237 if (!Subtarget->hasAVX())
7239 if (VT.isInteger() && !Subtarget->hasAVX2())
7242 // Check that the mask is a broadcast.
7243 int BroadcastIdx = -1;
7245 if (M >= 0 && BroadcastIdx == -1)
7247 else if (M >= 0 && M != BroadcastIdx)
7250 assert(BroadcastIdx < (int)Mask.size() && "We only expect to be called with "
7251 "a sorted mask where the broadcast "
7254 // Go up the chain of (vector) values to find a scalar load that we can
7255 // combine with the broadcast.
7257 switch (V.getOpcode()) {
7258 case ISD::CONCAT_VECTORS: {
7259 int OperandSize = Mask.size() / V.getNumOperands();
7260 V = V.getOperand(BroadcastIdx / OperandSize);
7261 BroadcastIdx %= OperandSize;
7265 case ISD::INSERT_SUBVECTOR: {
7266 SDValue VOuter = V.getOperand(0), VInner = V.getOperand(1);
7267 auto ConstantIdx = dyn_cast<ConstantSDNode>(V.getOperand(2));
7271 int BeginIdx = (int)ConstantIdx->getZExtValue();
7273 BeginIdx + (int)VInner.getValueType().getVectorNumElements();
7274 if (BroadcastIdx >= BeginIdx && BroadcastIdx < EndIdx) {
7275 BroadcastIdx -= BeginIdx;
7286 // Check if this is a broadcast of a scalar. We special case lowering
7287 // for scalars so that we can more effectively fold with loads.
7288 if (V.getOpcode() == ISD::BUILD_VECTOR ||
7289 (V.getOpcode() == ISD::SCALAR_TO_VECTOR && BroadcastIdx == 0)) {
7290 V = V.getOperand(BroadcastIdx);
7292 // If the scalar isn't a load, we can't broadcast from it in AVX1.
7293 // Only AVX2 has register broadcasts.
7294 if (!Subtarget->hasAVX2() && !isShuffleFoldableLoad(V))
7296 } else if (BroadcastIdx != 0 || !Subtarget->hasAVX2()) {
7297 // We can't broadcast from a vector register without AVX2, and we can only
7298 // broadcast from the zero-element of a vector register.
7302 return DAG.getNode(X86ISD::VBROADCAST, DL, VT, V);
7305 // Check for whether we can use INSERTPS to perform the shuffle. We only use
7306 // INSERTPS when the V1 elements are already in the correct locations
7307 // because otherwise we can just always use two SHUFPS instructions which
7308 // are much smaller to encode than a SHUFPS and an INSERTPS. We can also
7309 // perform INSERTPS if a single V1 element is out of place and all V2
7310 // elements are zeroable.
7311 static SDValue lowerVectorShuffleAsInsertPS(SDValue Op, SDValue V1, SDValue V2,
7313 SelectionDAG &DAG) {
7314 assert(Op.getSimpleValueType() == MVT::v4f32 && "Bad shuffle type!");
7315 assert(V1.getSimpleValueType() == MVT::v4f32 && "Bad operand type!");
7316 assert(V2.getSimpleValueType() == MVT::v4f32 && "Bad operand type!");
7317 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
7319 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
7322 int V1DstIndex = -1;
7323 int V2DstIndex = -1;
7324 bool V1UsedInPlace = false;
7326 for (int i = 0; i < 4; ++i) {
7327 // Synthesize a zero mask from the zeroable elements (includes undefs).
7333 // Flag if we use any V1 inputs in place.
7335 V1UsedInPlace = true;
7339 // We can only insert a single non-zeroable element.
7340 if (V1DstIndex != -1 || V2DstIndex != -1)
7344 // V1 input out of place for insertion.
7347 // V2 input for insertion.
7352 // Don't bother if we have no (non-zeroable) element for insertion.
7353 if (V1DstIndex == -1 && V2DstIndex == -1)
7356 // Determine element insertion src/dst indices. The src index is from the
7357 // start of the inserted vector, not the start of the concatenated vector.
7358 unsigned V2SrcIndex = 0;
7359 if (V1DstIndex != -1) {
7360 // If we have a V1 input out of place, we use V1 as the V2 element insertion
7361 // and don't use the original V2 at all.
7362 V2SrcIndex = Mask[V1DstIndex];
7363 V2DstIndex = V1DstIndex;
7366 V2SrcIndex = Mask[V2DstIndex] - 4;
7369 // If no V1 inputs are used in place, then the result is created only from
7370 // the zero mask and the V2 insertion - so remove V1 dependency.
7372 V1 = DAG.getUNDEF(MVT::v4f32);
7374 unsigned InsertPSMask = V2SrcIndex << 6 | V2DstIndex << 4 | ZMask;
7375 assert((InsertPSMask & ~0xFFu) == 0 && "Invalid mask!");
7377 // Insert the V2 element into the desired position.
7379 return DAG.getNode(X86ISD::INSERTPS, DL, MVT::v4f32, V1, V2,
7380 DAG.getConstant(InsertPSMask, DL, MVT::i8));
7383 /// \brief Try to lower a shuffle as a permute of the inputs followed by an
7384 /// UNPCK instruction.
7386 /// This specifically targets cases where we end up with alternating between
7387 /// the two inputs, and so can permute them into something that feeds a single
7388 /// UNPCK instruction. Note that this routine only targets integer vectors
7389 /// because for floating point vectors we have a generalized SHUFPS lowering
7390 /// strategy that handles everything that doesn't *exactly* match an unpack,
7391 /// making this clever lowering unnecessary.
7392 static SDValue lowerVectorShuffleAsUnpack(SDLoc DL, MVT VT, SDValue V1,
7393 SDValue V2, ArrayRef<int> Mask,
7394 SelectionDAG &DAG) {
7395 assert(!VT.isFloatingPoint() &&
7396 "This routine only supports integer vectors.");
7397 assert(!isSingleInputShuffleMask(Mask) &&
7398 "This routine should only be used when blending two inputs.");
7399 assert(Mask.size() >= 2 && "Single element masks are invalid.");
7401 int Size = Mask.size();
7403 int NumLoInputs = std::count_if(Mask.begin(), Mask.end(), [Size](int M) {
7404 return M >= 0 && M % Size < Size / 2;
7406 int NumHiInputs = std::count_if(
7407 Mask.begin(), Mask.end(), [Size](int M) { return M % Size >= Size / 2; });
7409 bool UnpackLo = NumLoInputs >= NumHiInputs;
7411 auto TryUnpack = [&](MVT UnpackVT, int Scale) {
7412 SmallVector<int, 32> V1Mask(Mask.size(), -1);
7413 SmallVector<int, 32> V2Mask(Mask.size(), -1);
7415 for (int i = 0; i < Size; ++i) {
7419 // Each element of the unpack contains Scale elements from this mask.
7420 int UnpackIdx = i / Scale;
7422 // We only handle the case where V1 feeds the first slots of the unpack.
7423 // We rely on canonicalization to ensure this is the case.
7424 if ((UnpackIdx % 2 == 0) != (Mask[i] < Size))
7427 // Setup the mask for this input. The indexing is tricky as we have to
7428 // handle the unpack stride.
7429 SmallVectorImpl<int> &VMask = (UnpackIdx % 2 == 0) ? V1Mask : V2Mask;
7430 VMask[(UnpackIdx / 2) * Scale + i % Scale + (UnpackLo ? 0 : Size / 2)] =
7434 // If we will have to shuffle both inputs to use the unpack, check whether
7435 // we can just unpack first and shuffle the result. If so, skip this unpack.
7436 if ((NumLoInputs == 0 || NumHiInputs == 0) && !isNoopShuffleMask(V1Mask) &&
7437 !isNoopShuffleMask(V2Mask))
7440 // Shuffle the inputs into place.
7441 V1 = DAG.getVectorShuffle(VT, DL, V1, DAG.getUNDEF(VT), V1Mask);
7442 V2 = DAG.getVectorShuffle(VT, DL, V2, DAG.getUNDEF(VT), V2Mask);
7444 // Cast the inputs to the type we will use to unpack them.
7445 V1 = DAG.getBitcast(UnpackVT, V1);
7446 V2 = DAG.getBitcast(UnpackVT, V2);
7448 // Unpack the inputs and cast the result back to the desired type.
7449 return DAG.getBitcast(
7450 VT, DAG.getNode(UnpackLo ? X86ISD::UNPCKL : X86ISD::UNPCKH, DL,
7454 // We try each unpack from the largest to the smallest to try and find one
7455 // that fits this mask.
7456 int OrigNumElements = VT.getVectorNumElements();
7457 int OrigScalarSize = VT.getScalarSizeInBits();
7458 for (int ScalarSize = 64; ScalarSize >= OrigScalarSize; ScalarSize /= 2) {
7459 int Scale = ScalarSize / OrigScalarSize;
7460 int NumElements = OrigNumElements / Scale;
7461 MVT UnpackVT = MVT::getVectorVT(MVT::getIntegerVT(ScalarSize), NumElements);
7462 if (SDValue Unpack = TryUnpack(UnpackVT, Scale))
7466 // If none of the unpack-rooted lowerings worked (or were profitable) try an
7468 if (NumLoInputs == 0 || NumHiInputs == 0) {
7469 assert((NumLoInputs > 0 || NumHiInputs > 0) &&
7470 "We have to have *some* inputs!");
7471 int HalfOffset = NumLoInputs == 0 ? Size / 2 : 0;
7473 // FIXME: We could consider the total complexity of the permute of each
7474 // possible unpacking. Or at the least we should consider how many
7475 // half-crossings are created.
7476 // FIXME: We could consider commuting the unpacks.
7478 SmallVector<int, 32> PermMask;
7479 PermMask.assign(Size, -1);
7480 for (int i = 0; i < Size; ++i) {
7484 assert(Mask[i] % Size >= HalfOffset && "Found input from wrong half!");
7487 2 * ((Mask[i] % Size) - HalfOffset) + (Mask[i] < Size ? 0 : 1);
7489 return DAG.getVectorShuffle(
7490 VT, DL, DAG.getNode(NumLoInputs == 0 ? X86ISD::UNPCKH : X86ISD::UNPCKL,
7492 DAG.getUNDEF(VT), PermMask);
7498 /// \brief Handle lowering of 2-lane 64-bit floating point shuffles.
7500 /// This is the basis function for the 2-lane 64-bit shuffles as we have full
7501 /// support for floating point shuffles but not integer shuffles. These
7502 /// instructions will incur a domain crossing penalty on some chips though so
7503 /// it is better to avoid lowering through this for integer vectors where
7505 static SDValue lowerV2F64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
7506 const X86Subtarget *Subtarget,
7507 SelectionDAG &DAG) {
7509 assert(Op.getSimpleValueType() == MVT::v2f64 && "Bad shuffle type!");
7510 assert(V1.getSimpleValueType() == MVT::v2f64 && "Bad operand type!");
7511 assert(V2.getSimpleValueType() == MVT::v2f64 && "Bad operand type!");
7512 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
7513 ArrayRef<int> Mask = SVOp->getMask();
7514 assert(Mask.size() == 2 && "Unexpected mask size for v2 shuffle!");
7516 if (isSingleInputShuffleMask(Mask)) {
7517 // Use low duplicate instructions for masks that match their pattern.
7518 if (Subtarget->hasSSE3())
7519 if (isShuffleEquivalent(V1, V2, Mask, {0, 0}))
7520 return DAG.getNode(X86ISD::MOVDDUP, DL, MVT::v2f64, V1);
7522 // Straight shuffle of a single input vector. Simulate this by using the
7523 // single input as both of the "inputs" to this instruction..
7524 unsigned SHUFPDMask = (Mask[0] == 1) | ((Mask[1] == 1) << 1);
7526 if (Subtarget->hasAVX()) {
7527 // If we have AVX, we can use VPERMILPS which will allow folding a load
7528 // into the shuffle.
7529 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v2f64, V1,
7530 DAG.getConstant(SHUFPDMask, DL, MVT::i8));
7533 return DAG.getNode(X86ISD::SHUFP, DL, MVT::v2f64, V1, V1,
7534 DAG.getConstant(SHUFPDMask, DL, MVT::i8));
7536 assert(Mask[0] >= 0 && Mask[0] < 2 && "Non-canonicalized blend!");
7537 assert(Mask[1] >= 2 && "Non-canonicalized blend!");
7539 // If we have a single input, insert that into V1 if we can do so cheaply.
7540 if ((Mask[0] >= 2) + (Mask[1] >= 2) == 1) {
7541 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
7542 DL, MVT::v2f64, V1, V2, Mask, Subtarget, DAG))
7544 // Try inverting the insertion since for v2 masks it is easy to do and we
7545 // can't reliably sort the mask one way or the other.
7546 int InverseMask[2] = {Mask[0] < 0 ? -1 : (Mask[0] ^ 2),
7547 Mask[1] < 0 ? -1 : (Mask[1] ^ 2)};
7548 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
7549 DL, MVT::v2f64, V2, V1, InverseMask, Subtarget, DAG))
7553 // Try to use one of the special instruction patterns to handle two common
7554 // blend patterns if a zero-blend above didn't work.
7555 if (isShuffleEquivalent(V1, V2, Mask, {0, 3}) ||
7556 isShuffleEquivalent(V1, V2, Mask, {1, 3}))
7557 if (SDValue V1S = getScalarValueForVectorElement(V1, Mask[0], DAG))
7558 // We can either use a special instruction to load over the low double or
7559 // to move just the low double.
7561 isShuffleFoldableLoad(V1S) ? X86ISD::MOVLPD : X86ISD::MOVSD,
7563 DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, MVT::v2f64, V1S));
7565 if (Subtarget->hasSSE41())
7566 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v2f64, V1, V2, Mask,
7570 // Use dedicated unpack instructions for masks that match their pattern.
7571 if (isShuffleEquivalent(V1, V2, Mask, {0, 2}))
7572 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v2f64, V1, V2);
7573 if (isShuffleEquivalent(V1, V2, Mask, {1, 3}))
7574 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v2f64, V1, V2);
7576 unsigned SHUFPDMask = (Mask[0] == 1) | (((Mask[1] - 2) == 1) << 1);
7577 return DAG.getNode(X86ISD::SHUFP, DL, MVT::v2f64, V1, V2,
7578 DAG.getConstant(SHUFPDMask, DL, MVT::i8));
7581 /// \brief Handle lowering of 2-lane 64-bit integer shuffles.
7583 /// Tries to lower a 2-lane 64-bit shuffle using shuffle operations provided by
7584 /// the integer unit to minimize domain crossing penalties. However, for blends
7585 /// it falls back to the floating point shuffle operation with appropriate bit
7587 static SDValue lowerV2I64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
7588 const X86Subtarget *Subtarget,
7589 SelectionDAG &DAG) {
7591 assert(Op.getSimpleValueType() == MVT::v2i64 && "Bad shuffle type!");
7592 assert(V1.getSimpleValueType() == MVT::v2i64 && "Bad operand type!");
7593 assert(V2.getSimpleValueType() == MVT::v2i64 && "Bad operand type!");
7594 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
7595 ArrayRef<int> Mask = SVOp->getMask();
7596 assert(Mask.size() == 2 && "Unexpected mask size for v2 shuffle!");
7598 if (isSingleInputShuffleMask(Mask)) {
7599 // Check for being able to broadcast a single element.
7600 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v2i64, V1,
7601 Mask, Subtarget, DAG))
7604 // Straight shuffle of a single input vector. For everything from SSE2
7605 // onward this has a single fast instruction with no scary immediates.
7606 // We have to map the mask as it is actually a v4i32 shuffle instruction.
7607 V1 = DAG.getBitcast(MVT::v4i32, V1);
7608 int WidenedMask[4] = {
7609 std::max(Mask[0], 0) * 2, std::max(Mask[0], 0) * 2 + 1,
7610 std::max(Mask[1], 0) * 2, std::max(Mask[1], 0) * 2 + 1};
7611 return DAG.getBitcast(
7613 DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32, V1,
7614 getV4X86ShuffleImm8ForMask(WidenedMask, DL, DAG)));
7616 assert(Mask[0] != -1 && "No undef lanes in multi-input v2 shuffles!");
7617 assert(Mask[1] != -1 && "No undef lanes in multi-input v2 shuffles!");
7618 assert(Mask[0] < 2 && "We sort V1 to be the first input.");
7619 assert(Mask[1] >= 2 && "We sort V2 to be the second input.");
7621 // If we have a blend of two PACKUS operations an the blend aligns with the
7622 // low and half halves, we can just merge the PACKUS operations. This is
7623 // particularly important as it lets us merge shuffles that this routine itself
7625 auto GetPackNode = [](SDValue V) {
7626 while (V.getOpcode() == ISD::BITCAST)
7627 V = V.getOperand(0);
7629 return V.getOpcode() == X86ISD::PACKUS ? V : SDValue();
7631 if (SDValue V1Pack = GetPackNode(V1))
7632 if (SDValue V2Pack = GetPackNode(V2))
7633 return DAG.getBitcast(MVT::v2i64,
7634 DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8,
7635 Mask[0] == 0 ? V1Pack.getOperand(0)
7636 : V1Pack.getOperand(1),
7637 Mask[1] == 2 ? V2Pack.getOperand(0)
7638 : V2Pack.getOperand(1)));
7640 // Try to use shift instructions.
7642 lowerVectorShuffleAsShift(DL, MVT::v2i64, V1, V2, Mask, DAG))
7645 // When loading a scalar and then shuffling it into a vector we can often do
7646 // the insertion cheaply.
7647 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
7648 DL, MVT::v2i64, V1, V2, Mask, Subtarget, DAG))
7650 // Try inverting the insertion since for v2 masks it is easy to do and we
7651 // can't reliably sort the mask one way or the other.
7652 int InverseMask[2] = {Mask[0] ^ 2, Mask[1] ^ 2};
7653 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
7654 DL, MVT::v2i64, V2, V1, InverseMask, Subtarget, DAG))
7657 // We have different paths for blend lowering, but they all must use the
7658 // *exact* same predicate.
7659 bool IsBlendSupported = Subtarget->hasSSE41();
7660 if (IsBlendSupported)
7661 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v2i64, V1, V2, Mask,
7665 // Use dedicated unpack instructions for masks that match their pattern.
7666 if (isShuffleEquivalent(V1, V2, Mask, {0, 2}))
7667 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v2i64, V1, V2);
7668 if (isShuffleEquivalent(V1, V2, Mask, {1, 3}))
7669 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v2i64, V1, V2);
7671 // Try to use byte rotation instructions.
7672 // Its more profitable for pre-SSSE3 to use shuffles/unpacks.
7673 if (Subtarget->hasSSSE3())
7674 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
7675 DL, MVT::v2i64, V1, V2, Mask, Subtarget, DAG))
7678 // If we have direct support for blends, we should lower by decomposing into
7679 // a permute. That will be faster than the domain cross.
7680 if (IsBlendSupported)
7681 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v2i64, V1, V2,
7684 // We implement this with SHUFPD which is pretty lame because it will likely
7685 // incur 2 cycles of stall for integer vectors on Nehalem and older chips.
7686 // However, all the alternatives are still more cycles and newer chips don't
7687 // have this problem. It would be really nice if x86 had better shuffles here.
7688 V1 = DAG.getBitcast(MVT::v2f64, V1);
7689 V2 = DAG.getBitcast(MVT::v2f64, V2);
7690 return DAG.getBitcast(MVT::v2i64,
7691 DAG.getVectorShuffle(MVT::v2f64, DL, V1, V2, Mask));
7694 /// \brief Test whether this can be lowered with a single SHUFPS instruction.
7696 /// This is used to disable more specialized lowerings when the shufps lowering
7697 /// will happen to be efficient.
7698 static bool isSingleSHUFPSMask(ArrayRef<int> Mask) {
7699 // This routine only handles 128-bit shufps.
7700 assert(Mask.size() == 4 && "Unsupported mask size!");
7702 // To lower with a single SHUFPS we need to have the low half and high half
7703 // each requiring a single input.
7704 if (Mask[0] != -1 && Mask[1] != -1 && (Mask[0] < 4) != (Mask[1] < 4))
7706 if (Mask[2] != -1 && Mask[3] != -1 && (Mask[2] < 4) != (Mask[3] < 4))
7712 /// \brief Lower a vector shuffle using the SHUFPS instruction.
7714 /// This is a helper routine dedicated to lowering vector shuffles using SHUFPS.
7715 /// It makes no assumptions about whether this is the *best* lowering, it simply
7717 static SDValue lowerVectorShuffleWithSHUFPS(SDLoc DL, MVT VT,
7718 ArrayRef<int> Mask, SDValue V1,
7719 SDValue V2, SelectionDAG &DAG) {
7720 SDValue LowV = V1, HighV = V2;
7721 int NewMask[4] = {Mask[0], Mask[1], Mask[2], Mask[3]};
7724 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; });
7726 if (NumV2Elements == 1) {
7728 std::find_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; }) -
7731 // Compute the index adjacent to V2Index and in the same half by toggling
7733 int V2AdjIndex = V2Index ^ 1;
7735 if (Mask[V2AdjIndex] == -1) {
7736 // Handles all the cases where we have a single V2 element and an undef.
7737 // This will only ever happen in the high lanes because we commute the
7738 // vector otherwise.
7740 std::swap(LowV, HighV);
7741 NewMask[V2Index] -= 4;
7743 // Handle the case where the V2 element ends up adjacent to a V1 element.
7744 // To make this work, blend them together as the first step.
7745 int V1Index = V2AdjIndex;
7746 int BlendMask[4] = {Mask[V2Index] - 4, 0, Mask[V1Index], 0};
7747 V2 = DAG.getNode(X86ISD::SHUFP, DL, VT, V2, V1,
7748 getV4X86ShuffleImm8ForMask(BlendMask, DL, DAG));
7750 // Now proceed to reconstruct the final blend as we have the necessary
7751 // high or low half formed.
7758 NewMask[V1Index] = 2; // We put the V1 element in V2[2].
7759 NewMask[V2Index] = 0; // We shifted the V2 element into V2[0].
7761 } else if (NumV2Elements == 2) {
7762 if (Mask[0] < 4 && Mask[1] < 4) {
7763 // Handle the easy case where we have V1 in the low lanes and V2 in the
7767 } else if (Mask[2] < 4 && Mask[3] < 4) {
7768 // We also handle the reversed case because this utility may get called
7769 // when we detect a SHUFPS pattern but can't easily commute the shuffle to
7770 // arrange things in the right direction.
7776 // We have a mixture of V1 and V2 in both low and high lanes. Rather than
7777 // trying to place elements directly, just blend them and set up the final
7778 // shuffle to place them.
7780 // The first two blend mask elements are for V1, the second two are for
7782 int BlendMask[4] = {Mask[0] < 4 ? Mask[0] : Mask[1],
7783 Mask[2] < 4 ? Mask[2] : Mask[3],
7784 (Mask[0] >= 4 ? Mask[0] : Mask[1]) - 4,
7785 (Mask[2] >= 4 ? Mask[2] : Mask[3]) - 4};
7786 V1 = DAG.getNode(X86ISD::SHUFP, DL, VT, V1, V2,
7787 getV4X86ShuffleImm8ForMask(BlendMask, DL, DAG));
7789 // Now we do a normal shuffle of V1 by giving V1 as both operands to
7792 NewMask[0] = Mask[0] < 4 ? 0 : 2;
7793 NewMask[1] = Mask[0] < 4 ? 2 : 0;
7794 NewMask[2] = Mask[2] < 4 ? 1 : 3;
7795 NewMask[3] = Mask[2] < 4 ? 3 : 1;
7798 return DAG.getNode(X86ISD::SHUFP, DL, VT, LowV, HighV,
7799 getV4X86ShuffleImm8ForMask(NewMask, DL, DAG));
7802 /// \brief Lower 4-lane 32-bit floating point shuffles.
7804 /// Uses instructions exclusively from the floating point unit to minimize
7805 /// domain crossing penalties, as these are sufficient to implement all v4f32
7807 static SDValue lowerV4F32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
7808 const X86Subtarget *Subtarget,
7809 SelectionDAG &DAG) {
7811 assert(Op.getSimpleValueType() == MVT::v4f32 && "Bad shuffle type!");
7812 assert(V1.getSimpleValueType() == MVT::v4f32 && "Bad operand type!");
7813 assert(V2.getSimpleValueType() == MVT::v4f32 && "Bad operand type!");
7814 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
7815 ArrayRef<int> Mask = SVOp->getMask();
7816 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
7819 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; });
7821 if (NumV2Elements == 0) {
7822 // Check for being able to broadcast a single element.
7823 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v4f32, V1,
7824 Mask, Subtarget, DAG))
7827 // Use even/odd duplicate instructions for masks that match their pattern.
7828 if (Subtarget->hasSSE3()) {
7829 if (isShuffleEquivalent(V1, V2, Mask, {0, 0, 2, 2}))
7830 return DAG.getNode(X86ISD::MOVSLDUP, DL, MVT::v4f32, V1);
7831 if (isShuffleEquivalent(V1, V2, Mask, {1, 1, 3, 3}))
7832 return DAG.getNode(X86ISD::MOVSHDUP, DL, MVT::v4f32, V1);
7835 if (Subtarget->hasAVX()) {
7836 // If we have AVX, we can use VPERMILPS which will allow folding a load
7837 // into the shuffle.
7838 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v4f32, V1,
7839 getV4X86ShuffleImm8ForMask(Mask, DL, DAG));
7842 // Otherwise, use a straight shuffle of a single input vector. We pass the
7843 // input vector to both operands to simulate this with a SHUFPS.
7844 return DAG.getNode(X86ISD::SHUFP, DL, MVT::v4f32, V1, V1,
7845 getV4X86ShuffleImm8ForMask(Mask, DL, DAG));
7848 // There are special ways we can lower some single-element blends. However, we
7849 // have custom ways we can lower more complex single-element blends below that
7850 // we defer to if both this and BLENDPS fail to match, so restrict this to
7851 // when the V2 input is targeting element 0 of the mask -- that is the fast
7853 if (NumV2Elements == 1 && Mask[0] >= 4)
7854 if (SDValue V = lowerVectorShuffleAsElementInsertion(DL, MVT::v4f32, V1, V2,
7855 Mask, Subtarget, DAG))
7858 if (Subtarget->hasSSE41()) {
7859 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4f32, V1, V2, Mask,
7863 // Use INSERTPS if we can complete the shuffle efficiently.
7864 if (SDValue V = lowerVectorShuffleAsInsertPS(Op, V1, V2, Mask, DAG))
7867 if (!isSingleSHUFPSMask(Mask))
7868 if (SDValue BlendPerm = lowerVectorShuffleAsBlendAndPermute(
7869 DL, MVT::v4f32, V1, V2, Mask, DAG))
7873 // Use dedicated unpack instructions for masks that match their pattern.
7874 if (isShuffleEquivalent(V1, V2, Mask, {0, 4, 1, 5}))
7875 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4f32, V1, V2);
7876 if (isShuffleEquivalent(V1, V2, Mask, {2, 6, 3, 7}))
7877 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4f32, V1, V2);
7878 if (isShuffleEquivalent(V1, V2, Mask, {4, 0, 5, 1}))
7879 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4f32, V2, V1);
7880 if (isShuffleEquivalent(V1, V2, Mask, {6, 2, 7, 3}))
7881 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4f32, V2, V1);
7883 // Otherwise fall back to a SHUFPS lowering strategy.
7884 return lowerVectorShuffleWithSHUFPS(DL, MVT::v4f32, Mask, V1, V2, DAG);
7887 /// \brief Lower 4-lane i32 vector shuffles.
7889 /// We try to handle these with integer-domain shuffles where we can, but for
7890 /// blends we use the floating point domain blend instructions.
7891 static SDValue lowerV4I32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
7892 const X86Subtarget *Subtarget,
7893 SelectionDAG &DAG) {
7895 assert(Op.getSimpleValueType() == MVT::v4i32 && "Bad shuffle type!");
7896 assert(V1.getSimpleValueType() == MVT::v4i32 && "Bad operand type!");
7897 assert(V2.getSimpleValueType() == MVT::v4i32 && "Bad operand type!");
7898 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
7899 ArrayRef<int> Mask = SVOp->getMask();
7900 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
7902 // Whenever we can lower this as a zext, that instruction is strictly faster
7903 // than any alternative. It also allows us to fold memory operands into the
7904 // shuffle in many cases.
7905 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(DL, MVT::v4i32, V1, V2,
7906 Mask, Subtarget, DAG))
7910 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; });
7912 if (NumV2Elements == 0) {
7913 // Check for being able to broadcast a single element.
7914 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v4i32, V1,
7915 Mask, Subtarget, DAG))
7918 // Straight shuffle of a single input vector. For everything from SSE2
7919 // onward this has a single fast instruction with no scary immediates.
7920 // We coerce the shuffle pattern to be compatible with UNPCK instructions
7921 // but we aren't actually going to use the UNPCK instruction because doing
7922 // so prevents folding a load into this instruction or making a copy.
7923 const int UnpackLoMask[] = {0, 0, 1, 1};
7924 const int UnpackHiMask[] = {2, 2, 3, 3};
7925 if (isShuffleEquivalent(V1, V2, Mask, {0, 0, 1, 1}))
7926 Mask = UnpackLoMask;
7927 else if (isShuffleEquivalent(V1, V2, Mask, {2, 2, 3, 3}))
7928 Mask = UnpackHiMask;
7930 return DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32, V1,
7931 getV4X86ShuffleImm8ForMask(Mask, DL, DAG));
7934 // Try to use shift instructions.
7936 lowerVectorShuffleAsShift(DL, MVT::v4i32, V1, V2, Mask, DAG))
7939 // There are special ways we can lower some single-element blends.
7940 if (NumV2Elements == 1)
7941 if (SDValue V = lowerVectorShuffleAsElementInsertion(DL, MVT::v4i32, V1, V2,
7942 Mask, Subtarget, DAG))
7945 // We have different paths for blend lowering, but they all must use the
7946 // *exact* same predicate.
7947 bool IsBlendSupported = Subtarget->hasSSE41();
7948 if (IsBlendSupported)
7949 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4i32, V1, V2, Mask,
7953 if (SDValue Masked =
7954 lowerVectorShuffleAsBitMask(DL, MVT::v4i32, V1, V2, Mask, DAG))
7957 // Use dedicated unpack instructions for masks that match their pattern.
7958 if (isShuffleEquivalent(V1, V2, Mask, {0, 4, 1, 5}))
7959 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4i32, V1, V2);
7960 if (isShuffleEquivalent(V1, V2, Mask, {2, 6, 3, 7}))
7961 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4i32, V1, V2);
7962 if (isShuffleEquivalent(V1, V2, Mask, {4, 0, 5, 1}))
7963 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4i32, V2, V1);
7964 if (isShuffleEquivalent(V1, V2, Mask, {6, 2, 7, 3}))
7965 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4i32, V2, V1);
7967 // Try to use byte rotation instructions.
7968 // Its more profitable for pre-SSSE3 to use shuffles/unpacks.
7969 if (Subtarget->hasSSSE3())
7970 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
7971 DL, MVT::v4i32, V1, V2, Mask, Subtarget, DAG))
7974 // If we have direct support for blends, we should lower by decomposing into
7975 // a permute. That will be faster than the domain cross.
7976 if (IsBlendSupported)
7977 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v4i32, V1, V2,
7980 // Try to lower by permuting the inputs into an unpack instruction.
7981 if (SDValue Unpack =
7982 lowerVectorShuffleAsUnpack(DL, MVT::v4i32, V1, V2, Mask, DAG))
7985 // We implement this with SHUFPS because it can blend from two vectors.
7986 // Because we're going to eventually use SHUFPS, we use SHUFPS even to build
7987 // up the inputs, bypassing domain shift penalties that we would encur if we
7988 // directly used PSHUFD on Nehalem and older. For newer chips, this isn't
7990 return DAG.getBitcast(
7992 DAG.getVectorShuffle(MVT::v4f32, DL, DAG.getBitcast(MVT::v4f32, V1),
7993 DAG.getBitcast(MVT::v4f32, V2), Mask));
7996 /// \brief Lowering of single-input v8i16 shuffles is the cornerstone of SSE2
7997 /// shuffle lowering, and the most complex part.
7999 /// The lowering strategy is to try to form pairs of input lanes which are
8000 /// targeted at the same half of the final vector, and then use a dword shuffle
8001 /// to place them onto the right half, and finally unpack the paired lanes into
8002 /// their final position.
8004 /// The exact breakdown of how to form these dword pairs and align them on the
8005 /// correct sides is really tricky. See the comments within the function for
8006 /// more of the details.
8008 /// This code also handles repeated 128-bit lanes of v8i16 shuffles, but each
8009 /// lane must shuffle the *exact* same way. In fact, you must pass a v8 Mask to
8010 /// this routine for it to work correctly. To shuffle a 256-bit or 512-bit i16
8011 /// vector, form the analogous 128-bit 8-element Mask.
8012 static SDValue lowerV8I16GeneralSingleInputVectorShuffle(
8013 SDLoc DL, MVT VT, SDValue V, MutableArrayRef<int> Mask,
8014 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
8015 assert(VT.getScalarType() == MVT::i16 && "Bad input type!");
8016 MVT PSHUFDVT = MVT::getVectorVT(MVT::i32, VT.getVectorNumElements() / 2);
8018 assert(Mask.size() == 8 && "Shuffle mask length doen't match!");
8019 MutableArrayRef<int> LoMask = Mask.slice(0, 4);
8020 MutableArrayRef<int> HiMask = Mask.slice(4, 4);
8022 SmallVector<int, 4> LoInputs;
8023 std::copy_if(LoMask.begin(), LoMask.end(), std::back_inserter(LoInputs),
8024 [](int M) { return M >= 0; });
8025 std::sort(LoInputs.begin(), LoInputs.end());
8026 LoInputs.erase(std::unique(LoInputs.begin(), LoInputs.end()), LoInputs.end());
8027 SmallVector<int, 4> HiInputs;
8028 std::copy_if(HiMask.begin(), HiMask.end(), std::back_inserter(HiInputs),
8029 [](int M) { return M >= 0; });
8030 std::sort(HiInputs.begin(), HiInputs.end());
8031 HiInputs.erase(std::unique(HiInputs.begin(), HiInputs.end()), HiInputs.end());
8033 std::lower_bound(LoInputs.begin(), LoInputs.end(), 4) - LoInputs.begin();
8034 int NumHToL = LoInputs.size() - NumLToL;
8036 std::lower_bound(HiInputs.begin(), HiInputs.end(), 4) - HiInputs.begin();
8037 int NumHToH = HiInputs.size() - NumLToH;
8038 MutableArrayRef<int> LToLInputs(LoInputs.data(), NumLToL);
8039 MutableArrayRef<int> LToHInputs(HiInputs.data(), NumLToH);
8040 MutableArrayRef<int> HToLInputs(LoInputs.data() + NumLToL, NumHToL);
8041 MutableArrayRef<int> HToHInputs(HiInputs.data() + NumLToH, NumHToH);
8043 // Simplify the 1-into-3 and 3-into-1 cases with a single pshufd. For all
8044 // such inputs we can swap two of the dwords across the half mark and end up
8045 // with <=2 inputs to each half in each half. Once there, we can fall through
8046 // to the generic code below. For example:
8048 // Input: [a, b, c, d, e, f, g, h] -PSHUFD[0,2,1,3]-> [a, b, e, f, c, d, g, h]
8049 // Mask: [0, 1, 2, 7, 4, 5, 6, 3] -----------------> [0, 1, 4, 7, 2, 3, 6, 5]
8051 // However in some very rare cases we have a 1-into-3 or 3-into-1 on one half
8052 // and an existing 2-into-2 on the other half. In this case we may have to
8053 // pre-shuffle the 2-into-2 half to avoid turning it into a 3-into-1 or
8054 // 1-into-3 which could cause us to cycle endlessly fixing each side in turn.
8055 // Fortunately, we don't have to handle anything but a 2-into-2 pattern
8056 // because any other situation (including a 3-into-1 or 1-into-3 in the other
8057 // half than the one we target for fixing) will be fixed when we re-enter this
8058 // path. We will also combine away any sequence of PSHUFD instructions that
8059 // result into a single instruction. Here is an example of the tricky case:
8061 // Input: [a, b, c, d, e, f, g, h] -PSHUFD[0,2,1,3]-> [a, b, e, f, c, d, g, h]
8062 // Mask: [3, 7, 1, 0, 2, 7, 3, 5] -THIS-IS-BAD!!!!-> [5, 7, 1, 0, 4, 7, 5, 3]
8064 // This now has a 1-into-3 in the high half! Instead, we do two shuffles:
8066 // Input: [a, b, c, d, e, f, g, h] PSHUFHW[0,2,1,3]-> [a, b, c, d, e, g, f, h]
8067 // Mask: [3, 7, 1, 0, 2, 7, 3, 5] -----------------> [3, 7, 1, 0, 2, 7, 3, 6]
8069 // Input: [a, b, c, d, e, g, f, h] -PSHUFD[0,2,1,3]-> [a, b, e, g, c, d, f, h]
8070 // Mask: [3, 7, 1, 0, 2, 7, 3, 6] -----------------> [5, 7, 1, 0, 4, 7, 5, 6]
8072 // The result is fine to be handled by the generic logic.
8073 auto balanceSides = [&](ArrayRef<int> AToAInputs, ArrayRef<int> BToAInputs,
8074 ArrayRef<int> BToBInputs, ArrayRef<int> AToBInputs,
8075 int AOffset, int BOffset) {
8076 assert((AToAInputs.size() == 3 || AToAInputs.size() == 1) &&
8077 "Must call this with A having 3 or 1 inputs from the A half.");
8078 assert((BToAInputs.size() == 1 || BToAInputs.size() == 3) &&
8079 "Must call this with B having 1 or 3 inputs from the B half.");
8080 assert(AToAInputs.size() + BToAInputs.size() == 4 &&
8081 "Must call this with either 3:1 or 1:3 inputs (summing to 4).");
8083 // Compute the index of dword with only one word among the three inputs in
8084 // a half by taking the sum of the half with three inputs and subtracting
8085 // the sum of the actual three inputs. The difference is the remaining
8088 int &TripleDWord = AToAInputs.size() == 3 ? ADWord : BDWord;
8089 int &OneInputDWord = AToAInputs.size() == 3 ? BDWord : ADWord;
8090 int TripleInputOffset = AToAInputs.size() == 3 ? AOffset : BOffset;
8091 ArrayRef<int> TripleInputs = AToAInputs.size() == 3 ? AToAInputs : BToAInputs;
8092 int OneInput = AToAInputs.size() == 3 ? BToAInputs[0] : AToAInputs[0];
8093 int TripleInputSum = 0 + 1 + 2 + 3 + (4 * TripleInputOffset);
8094 int TripleNonInputIdx =
8095 TripleInputSum - std::accumulate(TripleInputs.begin(), TripleInputs.end(), 0);
8096 TripleDWord = TripleNonInputIdx / 2;
8098 // We use xor with one to compute the adjacent DWord to whichever one the
8100 OneInputDWord = (OneInput / 2) ^ 1;
8102 // Check for one tricky case: We're fixing a 3<-1 or a 1<-3 shuffle for AToA
8103 // and BToA inputs. If there is also such a problem with the BToB and AToB
8104 // inputs, we don't try to fix it necessarily -- we'll recurse and see it in
8105 // the next pass. However, if we have a 2<-2 in the BToB and AToB inputs, it
8106 // is essential that we don't *create* a 3<-1 as then we might oscillate.
8107 if (BToBInputs.size() == 2 && AToBInputs.size() == 2) {
8108 // Compute how many inputs will be flipped by swapping these DWords. We
8110 // to balance this to ensure we don't form a 3-1 shuffle in the other
8112 int NumFlippedAToBInputs =
8113 std::count(AToBInputs.begin(), AToBInputs.end(), 2 * ADWord) +
8114 std::count(AToBInputs.begin(), AToBInputs.end(), 2 * ADWord + 1);
8115 int NumFlippedBToBInputs =
8116 std::count(BToBInputs.begin(), BToBInputs.end(), 2 * BDWord) +
8117 std::count(BToBInputs.begin(), BToBInputs.end(), 2 * BDWord + 1);
8118 if ((NumFlippedAToBInputs == 1 &&
8119 (NumFlippedBToBInputs == 0 || NumFlippedBToBInputs == 2)) ||
8120 (NumFlippedBToBInputs == 1 &&
8121 (NumFlippedAToBInputs == 0 || NumFlippedAToBInputs == 2))) {
8122 // We choose whether to fix the A half or B half based on whether that
8123 // half has zero flipped inputs. At zero, we may not be able to fix it
8124 // with that half. We also bias towards fixing the B half because that
8125 // will more commonly be the high half, and we have to bias one way.
8126 auto FixFlippedInputs = [&V, &DL, &Mask, &DAG](int PinnedIdx, int DWord,
8127 ArrayRef<int> Inputs) {
8128 int FixIdx = PinnedIdx ^ 1; // The adjacent slot to the pinned slot.
8129 bool IsFixIdxInput = std::find(Inputs.begin(), Inputs.end(),
8130 PinnedIdx ^ 1) != Inputs.end();
8131 // Determine whether the free index is in the flipped dword or the
8132 // unflipped dword based on where the pinned index is. We use this bit
8133 // in an xor to conditionally select the adjacent dword.
8134 int FixFreeIdx = 2 * (DWord ^ (PinnedIdx / 2 == DWord));
8135 bool IsFixFreeIdxInput = std::find(Inputs.begin(), Inputs.end(),
8136 FixFreeIdx) != Inputs.end();
8137 if (IsFixIdxInput == IsFixFreeIdxInput)
8139 IsFixFreeIdxInput = std::find(Inputs.begin(), Inputs.end(),
8140 FixFreeIdx) != Inputs.end();
8141 assert(IsFixIdxInput != IsFixFreeIdxInput &&
8142 "We need to be changing the number of flipped inputs!");
8143 int PSHUFHalfMask[] = {0, 1, 2, 3};
8144 std::swap(PSHUFHalfMask[FixFreeIdx % 4], PSHUFHalfMask[FixIdx % 4]);
8145 V = DAG.getNode(FixIdx < 4 ? X86ISD::PSHUFLW : X86ISD::PSHUFHW, DL,
8147 getV4X86ShuffleImm8ForMask(PSHUFHalfMask, DL, DAG));
8150 if (M != -1 && M == FixIdx)
8152 else if (M != -1 && M == FixFreeIdx)
8155 if (NumFlippedBToBInputs != 0) {
8157 BToAInputs.size() == 3 ? TripleNonInputIdx : OneInput;
8158 FixFlippedInputs(BPinnedIdx, BDWord, BToBInputs);
8160 assert(NumFlippedAToBInputs != 0 && "Impossible given predicates!");
8162 AToAInputs.size() == 3 ? TripleNonInputIdx : OneInput;
8163 FixFlippedInputs(APinnedIdx, ADWord, AToBInputs);
8168 int PSHUFDMask[] = {0, 1, 2, 3};
8169 PSHUFDMask[ADWord] = BDWord;
8170 PSHUFDMask[BDWord] = ADWord;
8173 DAG.getNode(X86ISD::PSHUFD, DL, PSHUFDVT, DAG.getBitcast(PSHUFDVT, V),
8174 getV4X86ShuffleImm8ForMask(PSHUFDMask, DL, DAG)));
8176 // Adjust the mask to match the new locations of A and B.
8178 if (M != -1 && M/2 == ADWord)
8179 M = 2 * BDWord + M % 2;
8180 else if (M != -1 && M/2 == BDWord)
8181 M = 2 * ADWord + M % 2;
8183 // Recurse back into this routine to re-compute state now that this isn't
8184 // a 3 and 1 problem.
8185 return lowerV8I16GeneralSingleInputVectorShuffle(DL, VT, V, Mask, Subtarget,
8188 if ((NumLToL == 3 && NumHToL == 1) || (NumLToL == 1 && NumHToL == 3))
8189 return balanceSides(LToLInputs, HToLInputs, HToHInputs, LToHInputs, 0, 4);
8190 else if ((NumHToH == 3 && NumLToH == 1) || (NumHToH == 1 && NumLToH == 3))
8191 return balanceSides(HToHInputs, LToHInputs, LToLInputs, HToLInputs, 4, 0);
8193 // At this point there are at most two inputs to the low and high halves from
8194 // each half. That means the inputs can always be grouped into dwords and
8195 // those dwords can then be moved to the correct half with a dword shuffle.
8196 // We use at most one low and one high word shuffle to collect these paired
8197 // inputs into dwords, and finally a dword shuffle to place them.
8198 int PSHUFLMask[4] = {-1, -1, -1, -1};
8199 int PSHUFHMask[4] = {-1, -1, -1, -1};
8200 int PSHUFDMask[4] = {-1, -1, -1, -1};
8202 // First fix the masks for all the inputs that are staying in their
8203 // original halves. This will then dictate the targets of the cross-half
8205 auto fixInPlaceInputs =
8206 [&PSHUFDMask](ArrayRef<int> InPlaceInputs, ArrayRef<int> IncomingInputs,
8207 MutableArrayRef<int> SourceHalfMask,
8208 MutableArrayRef<int> HalfMask, int HalfOffset) {
8209 if (InPlaceInputs.empty())
8211 if (InPlaceInputs.size() == 1) {
8212 SourceHalfMask[InPlaceInputs[0] - HalfOffset] =
8213 InPlaceInputs[0] - HalfOffset;
8214 PSHUFDMask[InPlaceInputs[0] / 2] = InPlaceInputs[0] / 2;
8217 if (IncomingInputs.empty()) {
8218 // Just fix all of the in place inputs.
8219 for (int Input : InPlaceInputs) {
8220 SourceHalfMask[Input - HalfOffset] = Input - HalfOffset;
8221 PSHUFDMask[Input / 2] = Input / 2;
8226 assert(InPlaceInputs.size() == 2 && "Cannot handle 3 or 4 inputs!");
8227 SourceHalfMask[InPlaceInputs[0] - HalfOffset] =
8228 InPlaceInputs[0] - HalfOffset;
8229 // Put the second input next to the first so that they are packed into
8230 // a dword. We find the adjacent index by toggling the low bit.
8231 int AdjIndex = InPlaceInputs[0] ^ 1;
8232 SourceHalfMask[AdjIndex - HalfOffset] = InPlaceInputs[1] - HalfOffset;
8233 std::replace(HalfMask.begin(), HalfMask.end(), InPlaceInputs[1], AdjIndex);
8234 PSHUFDMask[AdjIndex / 2] = AdjIndex / 2;
8236 fixInPlaceInputs(LToLInputs, HToLInputs, PSHUFLMask, LoMask, 0);
8237 fixInPlaceInputs(HToHInputs, LToHInputs, PSHUFHMask, HiMask, 4);
8239 // Now gather the cross-half inputs and place them into a free dword of
8240 // their target half.
8241 // FIXME: This operation could almost certainly be simplified dramatically to
8242 // look more like the 3-1 fixing operation.
8243 auto moveInputsToRightHalf = [&PSHUFDMask](
8244 MutableArrayRef<int> IncomingInputs, ArrayRef<int> ExistingInputs,
8245 MutableArrayRef<int> SourceHalfMask, MutableArrayRef<int> HalfMask,
8246 MutableArrayRef<int> FinalSourceHalfMask, int SourceOffset,
8248 auto isWordClobbered = [](ArrayRef<int> SourceHalfMask, int Word) {
8249 return SourceHalfMask[Word] != -1 && SourceHalfMask[Word] != Word;
8251 auto isDWordClobbered = [&isWordClobbered](ArrayRef<int> SourceHalfMask,
8253 int LowWord = Word & ~1;
8254 int HighWord = Word | 1;
8255 return isWordClobbered(SourceHalfMask, LowWord) ||
8256 isWordClobbered(SourceHalfMask, HighWord);
8259 if (IncomingInputs.empty())
8262 if (ExistingInputs.empty()) {
8263 // Map any dwords with inputs from them into the right half.
8264 for (int Input : IncomingInputs) {
8265 // If the source half mask maps over the inputs, turn those into
8266 // swaps and use the swapped lane.
8267 if (isWordClobbered(SourceHalfMask, Input - SourceOffset)) {
8268 if (SourceHalfMask[SourceHalfMask[Input - SourceOffset]] == -1) {
8269 SourceHalfMask[SourceHalfMask[Input - SourceOffset]] =
8270 Input - SourceOffset;
8271 // We have to swap the uses in our half mask in one sweep.
8272 for (int &M : HalfMask)
8273 if (M == SourceHalfMask[Input - SourceOffset] + SourceOffset)
8275 else if (M == Input)
8276 M = SourceHalfMask[Input - SourceOffset] + SourceOffset;
8278 assert(SourceHalfMask[SourceHalfMask[Input - SourceOffset]] ==
8279 Input - SourceOffset &&
8280 "Previous placement doesn't match!");
8282 // Note that this correctly re-maps both when we do a swap and when
8283 // we observe the other side of the swap above. We rely on that to
8284 // avoid swapping the members of the input list directly.
8285 Input = SourceHalfMask[Input - SourceOffset] + SourceOffset;
8288 // Map the input's dword into the correct half.
8289 if (PSHUFDMask[(Input - SourceOffset + DestOffset) / 2] == -1)
8290 PSHUFDMask[(Input - SourceOffset + DestOffset) / 2] = Input / 2;
8292 assert(PSHUFDMask[(Input - SourceOffset + DestOffset) / 2] ==
8294 "Previous placement doesn't match!");
8297 // And just directly shift any other-half mask elements to be same-half
8298 // as we will have mirrored the dword containing the element into the
8299 // same position within that half.
8300 for (int &M : HalfMask)
8301 if (M >= SourceOffset && M < SourceOffset + 4) {
8302 M = M - SourceOffset + DestOffset;
8303 assert(M >= 0 && "This should never wrap below zero!");
8308 // Ensure we have the input in a viable dword of its current half. This
8309 // is particularly tricky because the original position may be clobbered
8310 // by inputs being moved and *staying* in that half.
8311 if (IncomingInputs.size() == 1) {
8312 if (isWordClobbered(SourceHalfMask, IncomingInputs[0] - SourceOffset)) {
8313 int InputFixed = std::find(std::begin(SourceHalfMask),
8314 std::end(SourceHalfMask), -1) -
8315 std::begin(SourceHalfMask) + SourceOffset;
8316 SourceHalfMask[InputFixed - SourceOffset] =
8317 IncomingInputs[0] - SourceOffset;
8318 std::replace(HalfMask.begin(), HalfMask.end(), IncomingInputs[0],
8320 IncomingInputs[0] = InputFixed;
8322 } else if (IncomingInputs.size() == 2) {
8323 if (IncomingInputs[0] / 2 != IncomingInputs[1] / 2 ||
8324 isDWordClobbered(SourceHalfMask, IncomingInputs[0] - SourceOffset)) {
8325 // We have two non-adjacent or clobbered inputs we need to extract from
8326 // the source half. To do this, we need to map them into some adjacent
8327 // dword slot in the source mask.
8328 int InputsFixed[2] = {IncomingInputs[0] - SourceOffset,
8329 IncomingInputs[1] - SourceOffset};
8331 // If there is a free slot in the source half mask adjacent to one of
8332 // the inputs, place the other input in it. We use (Index XOR 1) to
8333 // compute an adjacent index.
8334 if (!isWordClobbered(SourceHalfMask, InputsFixed[0]) &&
8335 SourceHalfMask[InputsFixed[0] ^ 1] == -1) {
8336 SourceHalfMask[InputsFixed[0]] = InputsFixed[0];
8337 SourceHalfMask[InputsFixed[0] ^ 1] = InputsFixed[1];
8338 InputsFixed[1] = InputsFixed[0] ^ 1;
8339 } else if (!isWordClobbered(SourceHalfMask, InputsFixed[1]) &&
8340 SourceHalfMask[InputsFixed[1] ^ 1] == -1) {
8341 SourceHalfMask[InputsFixed[1]] = InputsFixed[1];
8342 SourceHalfMask[InputsFixed[1] ^ 1] = InputsFixed[0];
8343 InputsFixed[0] = InputsFixed[1] ^ 1;
8344 } else if (SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1)] == -1 &&
8345 SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1) + 1] == -1) {
8346 // The two inputs are in the same DWord but it is clobbered and the
8347 // adjacent DWord isn't used at all. Move both inputs to the free
8349 SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1)] = InputsFixed[0];
8350 SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1) + 1] = InputsFixed[1];
8351 InputsFixed[0] = 2 * ((InputsFixed[0] / 2) ^ 1);
8352 InputsFixed[1] = 2 * ((InputsFixed[0] / 2) ^ 1) + 1;
8354 // The only way we hit this point is if there is no clobbering
8355 // (because there are no off-half inputs to this half) and there is no
8356 // free slot adjacent to one of the inputs. In this case, we have to
8357 // swap an input with a non-input.
8358 for (int i = 0; i < 4; ++i)
8359 assert((SourceHalfMask[i] == -1 || SourceHalfMask[i] == i) &&
8360 "We can't handle any clobbers here!");
8361 assert(InputsFixed[1] != (InputsFixed[0] ^ 1) &&
8362 "Cannot have adjacent inputs here!");
8364 SourceHalfMask[InputsFixed[0] ^ 1] = InputsFixed[1];
8365 SourceHalfMask[InputsFixed[1]] = InputsFixed[0] ^ 1;
8367 // We also have to update the final source mask in this case because
8368 // it may need to undo the above swap.
8369 for (int &M : FinalSourceHalfMask)
8370 if (M == (InputsFixed[0] ^ 1) + SourceOffset)
8371 M = InputsFixed[1] + SourceOffset;
8372 else if (M == InputsFixed[1] + SourceOffset)
8373 M = (InputsFixed[0] ^ 1) + SourceOffset;
8375 InputsFixed[1] = InputsFixed[0] ^ 1;
8378 // Point everything at the fixed inputs.
8379 for (int &M : HalfMask)
8380 if (M == IncomingInputs[0])
8381 M = InputsFixed[0] + SourceOffset;
8382 else if (M == IncomingInputs[1])
8383 M = InputsFixed[1] + SourceOffset;
8385 IncomingInputs[0] = InputsFixed[0] + SourceOffset;
8386 IncomingInputs[1] = InputsFixed[1] + SourceOffset;
8389 llvm_unreachable("Unhandled input size!");
8392 // Now hoist the DWord down to the right half.
8393 int FreeDWord = (PSHUFDMask[DestOffset / 2] == -1 ? 0 : 1) + DestOffset / 2;
8394 assert(PSHUFDMask[FreeDWord] == -1 && "DWord not free");
8395 PSHUFDMask[FreeDWord] = IncomingInputs[0] / 2;
8396 for (int &M : HalfMask)
8397 for (int Input : IncomingInputs)
8399 M = FreeDWord * 2 + Input % 2;
8401 moveInputsToRightHalf(HToLInputs, LToLInputs, PSHUFHMask, LoMask, HiMask,
8402 /*SourceOffset*/ 4, /*DestOffset*/ 0);
8403 moveInputsToRightHalf(LToHInputs, HToHInputs, PSHUFLMask, HiMask, LoMask,
8404 /*SourceOffset*/ 0, /*DestOffset*/ 4);
8406 // Now enact all the shuffles we've computed to move the inputs into their
8408 if (!isNoopShuffleMask(PSHUFLMask))
8409 V = DAG.getNode(X86ISD::PSHUFLW, DL, VT, V,
8410 getV4X86ShuffleImm8ForMask(PSHUFLMask, DL, DAG));
8411 if (!isNoopShuffleMask(PSHUFHMask))
8412 V = DAG.getNode(X86ISD::PSHUFHW, DL, VT, V,
8413 getV4X86ShuffleImm8ForMask(PSHUFHMask, DL, DAG));
8414 if (!isNoopShuffleMask(PSHUFDMask))
8417 DAG.getNode(X86ISD::PSHUFD, DL, PSHUFDVT, DAG.getBitcast(PSHUFDVT, V),
8418 getV4X86ShuffleImm8ForMask(PSHUFDMask, DL, DAG)));
8420 // At this point, each half should contain all its inputs, and we can then
8421 // just shuffle them into their final position.
8422 assert(std::count_if(LoMask.begin(), LoMask.end(),
8423 [](int M) { return M >= 4; }) == 0 &&
8424 "Failed to lift all the high half inputs to the low mask!");
8425 assert(std::count_if(HiMask.begin(), HiMask.end(),
8426 [](int M) { return M >= 0 && M < 4; }) == 0 &&
8427 "Failed to lift all the low half inputs to the high mask!");
8429 // Do a half shuffle for the low mask.
8430 if (!isNoopShuffleMask(LoMask))
8431 V = DAG.getNode(X86ISD::PSHUFLW, DL, VT, V,
8432 getV4X86ShuffleImm8ForMask(LoMask, DL, DAG));
8434 // Do a half shuffle with the high mask after shifting its values down.
8435 for (int &M : HiMask)
8438 if (!isNoopShuffleMask(HiMask))
8439 V = DAG.getNode(X86ISD::PSHUFHW, DL, VT, V,
8440 getV4X86ShuffleImm8ForMask(HiMask, DL, DAG));
8445 /// \brief Helper to form a PSHUFB-based shuffle+blend.
8446 static SDValue lowerVectorShuffleAsPSHUFB(SDLoc DL, MVT VT, SDValue V1,
8447 SDValue V2, ArrayRef<int> Mask,
8448 SelectionDAG &DAG, bool &V1InUse,
8450 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
8456 int Size = Mask.size();
8457 int Scale = 16 / Size;
8458 for (int i = 0; i < 16; ++i) {
8459 if (Mask[i / Scale] == -1) {
8460 V1Mask[i] = V2Mask[i] = DAG.getUNDEF(MVT::i8);
8462 const int ZeroMask = 0x80;
8463 int V1Idx = Mask[i / Scale] < Size ? Mask[i / Scale] * Scale + i % Scale
8465 int V2Idx = Mask[i / Scale] < Size
8467 : (Mask[i / Scale] - Size) * Scale + i % Scale;
8468 if (Zeroable[i / Scale])
8469 V1Idx = V2Idx = ZeroMask;
8470 V1Mask[i] = DAG.getConstant(V1Idx, DL, MVT::i8);
8471 V2Mask[i] = DAG.getConstant(V2Idx, DL, MVT::i8);
8472 V1InUse |= (ZeroMask != V1Idx);
8473 V2InUse |= (ZeroMask != V2Idx);
8478 V1 = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8,
8479 DAG.getBitcast(MVT::v16i8, V1),
8480 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v16i8, V1Mask));
8482 V2 = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8,
8483 DAG.getBitcast(MVT::v16i8, V2),
8484 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v16i8, V2Mask));
8486 // If we need shuffled inputs from both, blend the two.
8488 if (V1InUse && V2InUse)
8489 V = DAG.getNode(ISD::OR, DL, MVT::v16i8, V1, V2);
8491 V = V1InUse ? V1 : V2;
8493 // Cast the result back to the correct type.
8494 return DAG.getBitcast(VT, V);
8497 /// \brief Generic lowering of 8-lane i16 shuffles.
8499 /// This handles both single-input shuffles and combined shuffle/blends with
8500 /// two inputs. The single input shuffles are immediately delegated to
8501 /// a dedicated lowering routine.
8503 /// The blends are lowered in one of three fundamental ways. If there are few
8504 /// enough inputs, it delegates to a basic UNPCK-based strategy. If the shuffle
8505 /// of the input is significantly cheaper when lowered as an interleaving of
8506 /// the two inputs, try to interleave them. Otherwise, blend the low and high
8507 /// halves of the inputs separately (making them have relatively few inputs)
8508 /// and then concatenate them.
8509 static SDValue lowerV8I16VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8510 const X86Subtarget *Subtarget,
8511 SelectionDAG &DAG) {
8513 assert(Op.getSimpleValueType() == MVT::v8i16 && "Bad shuffle type!");
8514 assert(V1.getSimpleValueType() == MVT::v8i16 && "Bad operand type!");
8515 assert(V2.getSimpleValueType() == MVT::v8i16 && "Bad operand type!");
8516 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8517 ArrayRef<int> OrigMask = SVOp->getMask();
8518 int MaskStorage[8] = {OrigMask[0], OrigMask[1], OrigMask[2], OrigMask[3],
8519 OrigMask[4], OrigMask[5], OrigMask[6], OrigMask[7]};
8520 MutableArrayRef<int> Mask(MaskStorage);
8522 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
8524 // Whenever we can lower this as a zext, that instruction is strictly faster
8525 // than any alternative.
8526 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(
8527 DL, MVT::v8i16, V1, V2, OrigMask, Subtarget, DAG))
8530 auto isV1 = [](int M) { return M >= 0 && M < 8; };
8532 auto isV2 = [](int M) { return M >= 8; };
8534 int NumV2Inputs = std::count_if(Mask.begin(), Mask.end(), isV2);
8536 if (NumV2Inputs == 0) {
8537 // Check for being able to broadcast a single element.
8538 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v8i16, V1,
8539 Mask, Subtarget, DAG))
8542 // Try to use shift instructions.
8544 lowerVectorShuffleAsShift(DL, MVT::v8i16, V1, V1, Mask, DAG))
8547 // Use dedicated unpack instructions for masks that match their pattern.
8548 if (isShuffleEquivalent(V1, V1, Mask, {0, 0, 1, 1, 2, 2, 3, 3}))
8549 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8i16, V1, V1);
8550 if (isShuffleEquivalent(V1, V1, Mask, {4, 4, 5, 5, 6, 6, 7, 7}))
8551 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8i16, V1, V1);
8553 // Try to use byte rotation instructions.
8554 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(DL, MVT::v8i16, V1, V1,
8555 Mask, Subtarget, DAG))
8558 return lowerV8I16GeneralSingleInputVectorShuffle(DL, MVT::v8i16, V1, Mask,
8562 assert(std::any_of(Mask.begin(), Mask.end(), isV1) &&
8563 "All single-input shuffles should be canonicalized to be V1-input "
8566 // Try to use shift instructions.
8568 lowerVectorShuffleAsShift(DL, MVT::v8i16, V1, V2, Mask, DAG))
8571 // There are special ways we can lower some single-element blends.
8572 if (NumV2Inputs == 1)
8573 if (SDValue V = lowerVectorShuffleAsElementInsertion(DL, MVT::v8i16, V1, V2,
8574 Mask, Subtarget, DAG))
8577 // We have different paths for blend lowering, but they all must use the
8578 // *exact* same predicate.
8579 bool IsBlendSupported = Subtarget->hasSSE41();
8580 if (IsBlendSupported)
8581 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v8i16, V1, V2, Mask,
8585 if (SDValue Masked =
8586 lowerVectorShuffleAsBitMask(DL, MVT::v8i16, V1, V2, Mask, DAG))
8589 // Use dedicated unpack instructions for masks that match their pattern.
8590 if (isShuffleEquivalent(V1, V2, Mask, {0, 8, 1, 9, 2, 10, 3, 11}))
8591 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8i16, V1, V2);
8592 if (isShuffleEquivalent(V1, V2, Mask, {4, 12, 5, 13, 6, 14, 7, 15}))
8593 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8i16, V1, V2);
8595 // Try to use byte rotation instructions.
8596 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
8597 DL, MVT::v8i16, V1, V2, Mask, Subtarget, DAG))
8600 if (SDValue BitBlend =
8601 lowerVectorShuffleAsBitBlend(DL, MVT::v8i16, V1, V2, Mask, DAG))
8604 if (SDValue Unpack =
8605 lowerVectorShuffleAsUnpack(DL, MVT::v8i16, V1, V2, Mask, DAG))
8608 // If we can't directly blend but can use PSHUFB, that will be better as it
8609 // can both shuffle and set up the inefficient blend.
8610 if (!IsBlendSupported && Subtarget->hasSSSE3()) {
8611 bool V1InUse, V2InUse;
8612 return lowerVectorShuffleAsPSHUFB(DL, MVT::v8i16, V1, V2, Mask, DAG,
8616 // We can always bit-blend if we have to so the fallback strategy is to
8617 // decompose into single-input permutes and blends.
8618 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v8i16, V1, V2,
8622 /// \brief Check whether a compaction lowering can be done by dropping even
8623 /// elements and compute how many times even elements must be dropped.
8625 /// This handles shuffles which take every Nth element where N is a power of
8626 /// two. Example shuffle masks:
8628 /// N = 1: 0, 2, 4, 6, 8, 10, 12, 14, 0, 2, 4, 6, 8, 10, 12, 14
8629 /// N = 1: 0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30
8630 /// N = 2: 0, 4, 8, 12, 0, 4, 8, 12, 0, 4, 8, 12, 0, 4, 8, 12
8631 /// N = 2: 0, 4, 8, 12, 16, 20, 24, 28, 0, 4, 8, 12, 16, 20, 24, 28
8632 /// N = 3: 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 0, 8
8633 /// N = 3: 0, 8, 16, 24, 0, 8, 16, 24, 0, 8, 16, 24, 0, 8, 16, 24
8635 /// Any of these lanes can of course be undef.
8637 /// This routine only supports N <= 3.
8638 /// FIXME: Evaluate whether either AVX or AVX-512 have any opportunities here
8641 /// \returns N above, or the number of times even elements must be dropped if
8642 /// there is such a number. Otherwise returns zero.
8643 static int canLowerByDroppingEvenElements(ArrayRef<int> Mask) {
8644 // Figure out whether we're looping over two inputs or just one.
8645 bool IsSingleInput = isSingleInputShuffleMask(Mask);
8647 // The modulus for the shuffle vector entries is based on whether this is
8648 // a single input or not.
8649 int ShuffleModulus = Mask.size() * (IsSingleInput ? 1 : 2);
8650 assert(isPowerOf2_32((uint32_t)ShuffleModulus) &&
8651 "We should only be called with masks with a power-of-2 size!");
8653 uint64_t ModMask = (uint64_t)ShuffleModulus - 1;
8655 // We track whether the input is viable for all power-of-2 strides 2^1, 2^2,
8656 // and 2^3 simultaneously. This is because we may have ambiguity with
8657 // partially undef inputs.
8658 bool ViableForN[3] = {true, true, true};
8660 for (int i = 0, e = Mask.size(); i < e; ++i) {
8661 // Ignore undef lanes, we'll optimistically collapse them to the pattern we
8666 bool IsAnyViable = false;
8667 for (unsigned j = 0; j != array_lengthof(ViableForN); ++j)
8668 if (ViableForN[j]) {
8671 // The shuffle mask must be equal to (i * 2^N) % M.
8672 if ((uint64_t)Mask[i] == (((uint64_t)i << N) & ModMask))
8675 ViableForN[j] = false;
8677 // Early exit if we exhaust the possible powers of two.
8682 for (unsigned j = 0; j != array_lengthof(ViableForN); ++j)
8686 // Return 0 as there is no viable power of two.
8690 /// \brief Generic lowering of v16i8 shuffles.
8692 /// This is a hybrid strategy to lower v16i8 vectors. It first attempts to
8693 /// detect any complexity reducing interleaving. If that doesn't help, it uses
8694 /// UNPCK to spread the i8 elements across two i16-element vectors, and uses
8695 /// the existing lowering for v8i16 blends on each half, finally PACK-ing them
8697 static SDValue lowerV16I8VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8698 const X86Subtarget *Subtarget,
8699 SelectionDAG &DAG) {
8701 assert(Op.getSimpleValueType() == MVT::v16i8 && "Bad shuffle type!");
8702 assert(V1.getSimpleValueType() == MVT::v16i8 && "Bad operand type!");
8703 assert(V2.getSimpleValueType() == MVT::v16i8 && "Bad operand type!");
8704 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8705 ArrayRef<int> Mask = SVOp->getMask();
8706 assert(Mask.size() == 16 && "Unexpected mask size for v16 shuffle!");
8708 // Try to use shift instructions.
8710 lowerVectorShuffleAsShift(DL, MVT::v16i8, V1, V2, Mask, DAG))
8713 // Try to use byte rotation instructions.
8714 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
8715 DL, MVT::v16i8, V1, V2, Mask, Subtarget, DAG))
8718 // Try to use a zext lowering.
8719 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(
8720 DL, MVT::v16i8, V1, V2, Mask, Subtarget, DAG))
8724 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 16; });
8726 // For single-input shuffles, there are some nicer lowering tricks we can use.
8727 if (NumV2Elements == 0) {
8728 // Check for being able to broadcast a single element.
8729 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v16i8, V1,
8730 Mask, Subtarget, DAG))
8733 // Check whether we can widen this to an i16 shuffle by duplicating bytes.
8734 // Notably, this handles splat and partial-splat shuffles more efficiently.
8735 // However, it only makes sense if the pre-duplication shuffle simplifies
8736 // things significantly. Currently, this means we need to be able to
8737 // express the pre-duplication shuffle as an i16 shuffle.
8739 // FIXME: We should check for other patterns which can be widened into an
8740 // i16 shuffle as well.
8741 auto canWidenViaDuplication = [](ArrayRef<int> Mask) {
8742 for (int i = 0; i < 16; i += 2)
8743 if (Mask[i] != -1 && Mask[i + 1] != -1 && Mask[i] != Mask[i + 1])
8748 auto tryToWidenViaDuplication = [&]() -> SDValue {
8749 if (!canWidenViaDuplication(Mask))
8751 SmallVector<int, 4> LoInputs;
8752 std::copy_if(Mask.begin(), Mask.end(), std::back_inserter(LoInputs),
8753 [](int M) { return M >= 0 && M < 8; });
8754 std::sort(LoInputs.begin(), LoInputs.end());
8755 LoInputs.erase(std::unique(LoInputs.begin(), LoInputs.end()),
8757 SmallVector<int, 4> HiInputs;
8758 std::copy_if(Mask.begin(), Mask.end(), std::back_inserter(HiInputs),
8759 [](int M) { return M >= 8; });
8760 std::sort(HiInputs.begin(), HiInputs.end());
8761 HiInputs.erase(std::unique(HiInputs.begin(), HiInputs.end()),
8764 bool TargetLo = LoInputs.size() >= HiInputs.size();
8765 ArrayRef<int> InPlaceInputs = TargetLo ? LoInputs : HiInputs;
8766 ArrayRef<int> MovingInputs = TargetLo ? HiInputs : LoInputs;
8768 int PreDupI16Shuffle[] = {-1, -1, -1, -1, -1, -1, -1, -1};
8769 SmallDenseMap<int, int, 8> LaneMap;
8770 for (int I : InPlaceInputs) {
8771 PreDupI16Shuffle[I/2] = I/2;
8774 int j = TargetLo ? 0 : 4, je = j + 4;
8775 for (int i = 0, ie = MovingInputs.size(); i < ie; ++i) {
8776 // Check if j is already a shuffle of this input. This happens when
8777 // there are two adjacent bytes after we move the low one.
8778 if (PreDupI16Shuffle[j] != MovingInputs[i] / 2) {
8779 // If we haven't yet mapped the input, search for a slot into which
8781 while (j < je && PreDupI16Shuffle[j] != -1)
8785 // We can't place the inputs into a single half with a simple i16 shuffle, so bail.
8788 // Map this input with the i16 shuffle.
8789 PreDupI16Shuffle[j] = MovingInputs[i] / 2;
8792 // Update the lane map based on the mapping we ended up with.
8793 LaneMap[MovingInputs[i]] = 2 * j + MovingInputs[i] % 2;
8795 V1 = DAG.getBitcast(
8797 DAG.getVectorShuffle(MVT::v8i16, DL, DAG.getBitcast(MVT::v8i16, V1),
8798 DAG.getUNDEF(MVT::v8i16), PreDupI16Shuffle));
8800 // Unpack the bytes to form the i16s that will be shuffled into place.
8801 V1 = DAG.getNode(TargetLo ? X86ISD::UNPCKL : X86ISD::UNPCKH, DL,
8802 MVT::v16i8, V1, V1);
8804 int PostDupI16Shuffle[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
8805 for (int i = 0; i < 16; ++i)
8806 if (Mask[i] != -1) {
8807 int MappedMask = LaneMap[Mask[i]] - (TargetLo ? 0 : 8);
8808 assert(MappedMask < 8 && "Invalid v8 shuffle mask!");
8809 if (PostDupI16Shuffle[i / 2] == -1)
8810 PostDupI16Shuffle[i / 2] = MappedMask;
8812 assert(PostDupI16Shuffle[i / 2] == MappedMask &&
8813 "Conflicting entrties in the original shuffle!");
8815 return DAG.getBitcast(
8817 DAG.getVectorShuffle(MVT::v8i16, DL, DAG.getBitcast(MVT::v8i16, V1),
8818 DAG.getUNDEF(MVT::v8i16), PostDupI16Shuffle));
8820 if (SDValue V = tryToWidenViaDuplication())
8824 // Use dedicated unpack instructions for masks that match their pattern.
8825 if (isShuffleEquivalent(V1, V2, Mask, {// Low half.
8826 0, 16, 1, 17, 2, 18, 3, 19,
8828 4, 20, 5, 21, 6, 22, 7, 23}))
8829 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v16i8, V1, V2);
8830 if (isShuffleEquivalent(V1, V2, Mask, {// Low half.
8831 8, 24, 9, 25, 10, 26, 11, 27,
8833 12, 28, 13, 29, 14, 30, 15, 31}))
8834 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v16i8, V1, V2);
8836 // Check for SSSE3 which lets us lower all v16i8 shuffles much more directly
8837 // with PSHUFB. It is important to do this before we attempt to generate any
8838 // blends but after all of the single-input lowerings. If the single input
8839 // lowerings can find an instruction sequence that is faster than a PSHUFB, we
8840 // want to preserve that and we can DAG combine any longer sequences into
8841 // a PSHUFB in the end. But once we start blending from multiple inputs,
8842 // the complexity of DAG combining bad patterns back into PSHUFB is too high,
8843 // and there are *very* few patterns that would actually be faster than the
8844 // PSHUFB approach because of its ability to zero lanes.
8846 // FIXME: The only exceptions to the above are blends which are exact
8847 // interleavings with direct instructions supporting them. We currently don't
8848 // handle those well here.
8849 if (Subtarget->hasSSSE3()) {
8850 bool V1InUse = false;
8851 bool V2InUse = false;
8853 SDValue PSHUFB = lowerVectorShuffleAsPSHUFB(DL, MVT::v16i8, V1, V2, Mask,
8854 DAG, V1InUse, V2InUse);
8856 // If both V1 and V2 are in use and we can use a direct blend or an unpack,
8857 // do so. This avoids using them to handle blends-with-zero which is
8858 // important as a single pshufb is significantly faster for that.
8859 if (V1InUse && V2InUse) {
8860 if (Subtarget->hasSSE41())
8861 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v16i8, V1, V2,
8862 Mask, Subtarget, DAG))
8865 // We can use an unpack to do the blending rather than an or in some
8866 // cases. Even though the or may be (very minorly) more efficient, we
8867 // preference this lowering because there are common cases where part of
8868 // the complexity of the shuffles goes away when we do the final blend as
8870 // FIXME: It might be worth trying to detect if the unpack-feeding
8871 // shuffles will both be pshufb, in which case we shouldn't bother with
8873 if (SDValue Unpack =
8874 lowerVectorShuffleAsUnpack(DL, MVT::v16i8, V1, V2, Mask, DAG))
8881 // There are special ways we can lower some single-element blends.
8882 if (NumV2Elements == 1)
8883 if (SDValue V = lowerVectorShuffleAsElementInsertion(DL, MVT::v16i8, V1, V2,
8884 Mask, Subtarget, DAG))
8887 if (SDValue BitBlend =
8888 lowerVectorShuffleAsBitBlend(DL, MVT::v16i8, V1, V2, Mask, DAG))
8891 // Check whether a compaction lowering can be done. This handles shuffles
8892 // which take every Nth element for some even N. See the helper function for
8895 // We special case these as they can be particularly efficiently handled with
8896 // the PACKUSB instruction on x86 and they show up in common patterns of
8897 // rearranging bytes to truncate wide elements.
8898 if (int NumEvenDrops = canLowerByDroppingEvenElements(Mask)) {
8899 // NumEvenDrops is the power of two stride of the elements. Another way of
8900 // thinking about it is that we need to drop the even elements this many
8901 // times to get the original input.
8902 bool IsSingleInput = isSingleInputShuffleMask(Mask);
8904 // First we need to zero all the dropped bytes.
8905 assert(NumEvenDrops <= 3 &&
8906 "No support for dropping even elements more than 3 times.");
8907 // We use the mask type to pick which bytes are preserved based on how many
8908 // elements are dropped.
8909 MVT MaskVTs[] = { MVT::v8i16, MVT::v4i32, MVT::v2i64 };
8910 SDValue ByteClearMask = DAG.getBitcast(
8911 MVT::v16i8, DAG.getConstant(0xFF, DL, MaskVTs[NumEvenDrops - 1]));
8912 V1 = DAG.getNode(ISD::AND, DL, MVT::v16i8, V1, ByteClearMask);
8914 V2 = DAG.getNode(ISD::AND, DL, MVT::v16i8, V2, ByteClearMask);
8916 // Now pack things back together.
8917 V1 = DAG.getBitcast(MVT::v8i16, V1);
8918 V2 = IsSingleInput ? V1 : DAG.getBitcast(MVT::v8i16, V2);
8919 SDValue Result = DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8, V1, V2);
8920 for (int i = 1; i < NumEvenDrops; ++i) {
8921 Result = DAG.getBitcast(MVT::v8i16, Result);
8922 Result = DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8, Result, Result);
8928 // Handle multi-input cases by blending single-input shuffles.
8929 if (NumV2Elements > 0)
8930 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v16i8, V1, V2,
8933 // The fallback path for single-input shuffles widens this into two v8i16
8934 // vectors with unpacks, shuffles those, and then pulls them back together
8938 int LoBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
8939 int HiBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
8940 for (int i = 0; i < 16; ++i)
8942 (i < 8 ? LoBlendMask[i] : HiBlendMask[i % 8]) = Mask[i];
8944 SDValue Zero = getZeroVector(MVT::v8i16, Subtarget, DAG, DL);
8946 SDValue VLoHalf, VHiHalf;
8947 // Check if any of the odd lanes in the v16i8 are used. If not, we can mask
8948 // them out and avoid using UNPCK{L,H} to extract the elements of V as
8950 if (std::none_of(std::begin(LoBlendMask), std::end(LoBlendMask),
8951 [](int M) { return M >= 0 && M % 2 == 1; }) &&
8952 std::none_of(std::begin(HiBlendMask), std::end(HiBlendMask),
8953 [](int M) { return M >= 0 && M % 2 == 1; })) {
8954 // Use a mask to drop the high bytes.
8955 VLoHalf = DAG.getBitcast(MVT::v8i16, V);
8956 VLoHalf = DAG.getNode(ISD::AND, DL, MVT::v8i16, VLoHalf,
8957 DAG.getConstant(0x00FF, DL, MVT::v8i16));
8959 // This will be a single vector shuffle instead of a blend so nuke VHiHalf.
8960 VHiHalf = DAG.getUNDEF(MVT::v8i16);
8962 // Squash the masks to point directly into VLoHalf.
8963 for (int &M : LoBlendMask)
8966 for (int &M : HiBlendMask)
8970 // Otherwise just unpack the low half of V into VLoHalf and the high half into
8971 // VHiHalf so that we can blend them as i16s.
8972 VLoHalf = DAG.getBitcast(
8973 MVT::v8i16, DAG.getNode(X86ISD::UNPCKL, DL, MVT::v16i8, V, Zero));
8974 VHiHalf = DAG.getBitcast(
8975 MVT::v8i16, DAG.getNode(X86ISD::UNPCKH, DL, MVT::v16i8, V, Zero));
8978 SDValue LoV = DAG.getVectorShuffle(MVT::v8i16, DL, VLoHalf, VHiHalf, LoBlendMask);
8979 SDValue HiV = DAG.getVectorShuffle(MVT::v8i16, DL, VLoHalf, VHiHalf, HiBlendMask);
8981 return DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8, LoV, HiV);
8984 /// \brief Dispatching routine to lower various 128-bit x86 vector shuffles.
8986 /// This routine breaks down the specific type of 128-bit shuffle and
8987 /// dispatches to the lowering routines accordingly.
8988 static SDValue lower128BitVectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8989 MVT VT, const X86Subtarget *Subtarget,
8990 SelectionDAG &DAG) {
8991 switch (VT.SimpleTy) {
8993 return lowerV2I64VectorShuffle(Op, V1, V2, Subtarget, DAG);
8995 return lowerV2F64VectorShuffle(Op, V1, V2, Subtarget, DAG);
8997 return lowerV4I32VectorShuffle(Op, V1, V2, Subtarget, DAG);
8999 return lowerV4F32VectorShuffle(Op, V1, V2, Subtarget, DAG);
9001 return lowerV8I16VectorShuffle(Op, V1, V2, Subtarget, DAG);
9003 return lowerV16I8VectorShuffle(Op, V1, V2, Subtarget, DAG);
9006 llvm_unreachable("Unimplemented!");
9010 /// \brief Helper function to test whether a shuffle mask could be
9011 /// simplified by widening the elements being shuffled.
9013 /// Appends the mask for wider elements in WidenedMask if valid. Otherwise
9014 /// leaves it in an unspecified state.
9016 /// NOTE: This must handle normal vector shuffle masks and *target* vector
9017 /// shuffle masks. The latter have the special property of a '-2' representing
9018 /// a zero-ed lane of a vector.
9019 static bool canWidenShuffleElements(ArrayRef<int> Mask,
9020 SmallVectorImpl<int> &WidenedMask) {
9021 for (int i = 0, Size = Mask.size(); i < Size; i += 2) {
9022 // If both elements are undef, its trivial.
9023 if (Mask[i] == SM_SentinelUndef && Mask[i + 1] == SM_SentinelUndef) {
9024 WidenedMask.push_back(SM_SentinelUndef);
9028 // Check for an undef mask and a mask value properly aligned to fit with
9029 // a pair of values. If we find such a case, use the non-undef mask's value.
9030 if (Mask[i] == SM_SentinelUndef && Mask[i + 1] >= 0 && Mask[i + 1] % 2 == 1) {
9031 WidenedMask.push_back(Mask[i + 1] / 2);
9034 if (Mask[i + 1] == SM_SentinelUndef && Mask[i] >= 0 && Mask[i] % 2 == 0) {
9035 WidenedMask.push_back(Mask[i] / 2);
9039 // When zeroing, we need to spread the zeroing across both lanes to widen.
9040 if (Mask[i] == SM_SentinelZero || Mask[i + 1] == SM_SentinelZero) {
9041 if ((Mask[i] == SM_SentinelZero || Mask[i] == SM_SentinelUndef) &&
9042 (Mask[i + 1] == SM_SentinelZero || Mask[i + 1] == SM_SentinelUndef)) {
9043 WidenedMask.push_back(SM_SentinelZero);
9049 // Finally check if the two mask values are adjacent and aligned with
9051 if (Mask[i] != SM_SentinelUndef && Mask[i] % 2 == 0 && Mask[i] + 1 == Mask[i + 1]) {
9052 WidenedMask.push_back(Mask[i] / 2);
9056 // Otherwise we can't safely widen the elements used in this shuffle.
9059 assert(WidenedMask.size() == Mask.size() / 2 &&
9060 "Incorrect size of mask after widening the elements!");
9065 /// \brief Generic routine to split vector shuffle into half-sized shuffles.
9067 /// This routine just extracts two subvectors, shuffles them independently, and
9068 /// then concatenates them back together. This should work effectively with all
9069 /// AVX vector shuffle types.
9070 static SDValue splitAndLowerVectorShuffle(SDLoc DL, MVT VT, SDValue V1,
9071 SDValue V2, ArrayRef<int> Mask,
9072 SelectionDAG &DAG) {
9073 assert(VT.getSizeInBits() >= 256 &&
9074 "Only for 256-bit or wider vector shuffles!");
9075 assert(V1.getSimpleValueType() == VT && "Bad operand type!");
9076 assert(V2.getSimpleValueType() == VT && "Bad operand type!");
9078 ArrayRef<int> LoMask = Mask.slice(0, Mask.size() / 2);
9079 ArrayRef<int> HiMask = Mask.slice(Mask.size() / 2);
9081 int NumElements = VT.getVectorNumElements();
9082 int SplitNumElements = NumElements / 2;
9083 MVT ScalarVT = VT.getScalarType();
9084 MVT SplitVT = MVT::getVectorVT(ScalarVT, NumElements / 2);
9086 // Rather than splitting build-vectors, just build two narrower build
9087 // vectors. This helps shuffling with splats and zeros.
9088 auto SplitVector = [&](SDValue V) {
9089 while (V.getOpcode() == ISD::BITCAST)
9090 V = V->getOperand(0);
9092 MVT OrigVT = V.getSimpleValueType();
9093 int OrigNumElements = OrigVT.getVectorNumElements();
9094 int OrigSplitNumElements = OrigNumElements / 2;
9095 MVT OrigScalarVT = OrigVT.getScalarType();
9096 MVT OrigSplitVT = MVT::getVectorVT(OrigScalarVT, OrigNumElements / 2);
9100 auto *BV = dyn_cast<BuildVectorSDNode>(V);
9102 LoV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, OrigSplitVT, V,
9103 DAG.getIntPtrConstant(0, DL));
9104 HiV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, OrigSplitVT, V,
9105 DAG.getIntPtrConstant(OrigSplitNumElements, DL));
9108 SmallVector<SDValue, 16> LoOps, HiOps;
9109 for (int i = 0; i < OrigSplitNumElements; ++i) {
9110 LoOps.push_back(BV->getOperand(i));
9111 HiOps.push_back(BV->getOperand(i + OrigSplitNumElements));
9113 LoV = DAG.getNode(ISD::BUILD_VECTOR, DL, OrigSplitVT, LoOps);
9114 HiV = DAG.getNode(ISD::BUILD_VECTOR, DL, OrigSplitVT, HiOps);
9116 return std::make_pair(DAG.getBitcast(SplitVT, LoV),
9117 DAG.getBitcast(SplitVT, HiV));
9120 SDValue LoV1, HiV1, LoV2, HiV2;
9121 std::tie(LoV1, HiV1) = SplitVector(V1);
9122 std::tie(LoV2, HiV2) = SplitVector(V2);
9124 // Now create two 4-way blends of these half-width vectors.
9125 auto HalfBlend = [&](ArrayRef<int> HalfMask) {
9126 bool UseLoV1 = false, UseHiV1 = false, UseLoV2 = false, UseHiV2 = false;
9127 SmallVector<int, 32> V1BlendMask, V2BlendMask, BlendMask;
9128 for (int i = 0; i < SplitNumElements; ++i) {
9129 int M = HalfMask[i];
9130 if (M >= NumElements) {
9131 if (M >= NumElements + SplitNumElements)
9135 V2BlendMask.push_back(M - NumElements);
9136 V1BlendMask.push_back(-1);
9137 BlendMask.push_back(SplitNumElements + i);
9138 } else if (M >= 0) {
9139 if (M >= SplitNumElements)
9143 V2BlendMask.push_back(-1);
9144 V1BlendMask.push_back(M);
9145 BlendMask.push_back(i);
9147 V2BlendMask.push_back(-1);
9148 V1BlendMask.push_back(-1);
9149 BlendMask.push_back(-1);
9153 // Because the lowering happens after all combining takes place, we need to
9154 // manually combine these blend masks as much as possible so that we create
9155 // a minimal number of high-level vector shuffle nodes.
9157 // First try just blending the halves of V1 or V2.
9158 if (!UseLoV1 && !UseHiV1 && !UseLoV2 && !UseHiV2)
9159 return DAG.getUNDEF(SplitVT);
9160 if (!UseLoV2 && !UseHiV2)
9161 return DAG.getVectorShuffle(SplitVT, DL, LoV1, HiV1, V1BlendMask);
9162 if (!UseLoV1 && !UseHiV1)
9163 return DAG.getVectorShuffle(SplitVT, DL, LoV2, HiV2, V2BlendMask);
9165 SDValue V1Blend, V2Blend;
9166 if (UseLoV1 && UseHiV1) {
9168 DAG.getVectorShuffle(SplitVT, DL, LoV1, HiV1, V1BlendMask);
9170 // We only use half of V1 so map the usage down into the final blend mask.
9171 V1Blend = UseLoV1 ? LoV1 : HiV1;
9172 for (int i = 0; i < SplitNumElements; ++i)
9173 if (BlendMask[i] >= 0 && BlendMask[i] < SplitNumElements)
9174 BlendMask[i] = V1BlendMask[i] - (UseLoV1 ? 0 : SplitNumElements);
9176 if (UseLoV2 && UseHiV2) {
9178 DAG.getVectorShuffle(SplitVT, DL, LoV2, HiV2, V2BlendMask);
9180 // We only use half of V2 so map the usage down into the final blend mask.
9181 V2Blend = UseLoV2 ? LoV2 : HiV2;
9182 for (int i = 0; i < SplitNumElements; ++i)
9183 if (BlendMask[i] >= SplitNumElements)
9184 BlendMask[i] = V2BlendMask[i] + (UseLoV2 ? SplitNumElements : 0);
9186 return DAG.getVectorShuffle(SplitVT, DL, V1Blend, V2Blend, BlendMask);
9188 SDValue Lo = HalfBlend(LoMask);
9189 SDValue Hi = HalfBlend(HiMask);
9190 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, Lo, Hi);
9193 /// \brief Either split a vector in halves or decompose the shuffles and the
9196 /// This is provided as a good fallback for many lowerings of non-single-input
9197 /// shuffles with more than one 128-bit lane. In those cases, we want to select
9198 /// between splitting the shuffle into 128-bit components and stitching those
9199 /// back together vs. extracting the single-input shuffles and blending those
9201 static SDValue lowerVectorShuffleAsSplitOrBlend(SDLoc DL, MVT VT, SDValue V1,
9202 SDValue V2, ArrayRef<int> Mask,
9203 SelectionDAG &DAG) {
9204 assert(!isSingleInputShuffleMask(Mask) && "This routine must not be used to "
9205 "lower single-input shuffles as it "
9206 "could then recurse on itself.");
9207 int Size = Mask.size();
9209 // If this can be modeled as a broadcast of two elements followed by a blend,
9210 // prefer that lowering. This is especially important because broadcasts can
9211 // often fold with memory operands.
9212 auto DoBothBroadcast = [&] {
9213 int V1BroadcastIdx = -1, V2BroadcastIdx = -1;
9216 if (V2BroadcastIdx == -1)
9217 V2BroadcastIdx = M - Size;
9218 else if (M - Size != V2BroadcastIdx)
9220 } else if (M >= 0) {
9221 if (V1BroadcastIdx == -1)
9223 else if (M != V1BroadcastIdx)
9228 if (DoBothBroadcast())
9229 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, VT, V1, V2, Mask,
9232 // If the inputs all stem from a single 128-bit lane of each input, then we
9233 // split them rather than blending because the split will decompose to
9234 // unusually few instructions.
9235 int LaneCount = VT.getSizeInBits() / 128;
9236 int LaneSize = Size / LaneCount;
9237 SmallBitVector LaneInputs[2];
9238 LaneInputs[0].resize(LaneCount, false);
9239 LaneInputs[1].resize(LaneCount, false);
9240 for (int i = 0; i < Size; ++i)
9242 LaneInputs[Mask[i] / Size][(Mask[i] % Size) / LaneSize] = true;
9243 if (LaneInputs[0].count() <= 1 && LaneInputs[1].count() <= 1)
9244 return splitAndLowerVectorShuffle(DL, VT, V1, V2, Mask, DAG);
9246 // Otherwise, just fall back to decomposed shuffles and a blend. This requires
9247 // that the decomposed single-input shuffles don't end up here.
9248 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, VT, V1, V2, Mask, DAG);
9251 /// \brief Lower a vector shuffle crossing multiple 128-bit lanes as
9252 /// a permutation and blend of those lanes.
9254 /// This essentially blends the out-of-lane inputs to each lane into the lane
9255 /// from a permuted copy of the vector. This lowering strategy results in four
9256 /// instructions in the worst case for a single-input cross lane shuffle which
9257 /// is lower than any other fully general cross-lane shuffle strategy I'm aware
9258 /// of. Special cases for each particular shuffle pattern should be handled
9259 /// prior to trying this lowering.
9260 static SDValue lowerVectorShuffleAsLanePermuteAndBlend(SDLoc DL, MVT VT,
9261 SDValue V1, SDValue V2,
9263 SelectionDAG &DAG) {
9264 // FIXME: This should probably be generalized for 512-bit vectors as well.
9265 assert(VT.getSizeInBits() == 256 && "Only for 256-bit vector shuffles!");
9266 int LaneSize = Mask.size() / 2;
9268 // If there are only inputs from one 128-bit lane, splitting will in fact be
9269 // less expensive. The flags track whether the given lane contains an element
9270 // that crosses to another lane.
9271 bool LaneCrossing[2] = {false, false};
9272 for (int i = 0, Size = Mask.size(); i < Size; ++i)
9273 if (Mask[i] >= 0 && (Mask[i] % Size) / LaneSize != i / LaneSize)
9274 LaneCrossing[(Mask[i] % Size) / LaneSize] = true;
9275 if (!LaneCrossing[0] || !LaneCrossing[1])
9276 return splitAndLowerVectorShuffle(DL, VT, V1, V2, Mask, DAG);
9278 if (isSingleInputShuffleMask(Mask)) {
9279 SmallVector<int, 32> FlippedBlendMask;
9280 for (int i = 0, Size = Mask.size(); i < Size; ++i)
9281 FlippedBlendMask.push_back(
9282 Mask[i] < 0 ? -1 : (((Mask[i] % Size) / LaneSize == i / LaneSize)
9284 : Mask[i] % LaneSize +
9285 (i / LaneSize) * LaneSize + Size));
9287 // Flip the vector, and blend the results which should now be in-lane. The
9288 // VPERM2X128 mask uses the low 2 bits for the low source and bits 4 and
9289 // 5 for the high source. The value 3 selects the high half of source 2 and
9290 // the value 2 selects the low half of source 2. We only use source 2 to
9291 // allow folding it into a memory operand.
9292 unsigned PERMMask = 3 | 2 << 4;
9293 SDValue Flipped = DAG.getNode(X86ISD::VPERM2X128, DL, VT, DAG.getUNDEF(VT),
9294 V1, DAG.getConstant(PERMMask, DL, MVT::i8));
9295 return DAG.getVectorShuffle(VT, DL, V1, Flipped, FlippedBlendMask);
9298 // This now reduces to two single-input shuffles of V1 and V2 which at worst
9299 // will be handled by the above logic and a blend of the results, much like
9300 // other patterns in AVX.
9301 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, VT, V1, V2, Mask, DAG);
9304 /// \brief Handle lowering 2-lane 128-bit shuffles.
9305 static SDValue lowerV2X128VectorShuffle(SDLoc DL, MVT VT, SDValue V1,
9306 SDValue V2, ArrayRef<int> Mask,
9307 const X86Subtarget *Subtarget,
9308 SelectionDAG &DAG) {
9309 // TODO: If minimizing size and one of the inputs is a zero vector and the
9310 // the zero vector has only one use, we could use a VPERM2X128 to save the
9311 // instruction bytes needed to explicitly generate the zero vector.
9313 // Blends are faster and handle all the non-lane-crossing cases.
9314 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, VT, V1, V2, Mask,
9318 bool IsV1Zero = ISD::isBuildVectorAllZeros(V1.getNode());
9319 bool IsV2Zero = ISD::isBuildVectorAllZeros(V2.getNode());
9321 // If either input operand is a zero vector, use VPERM2X128 because its mask
9322 // allows us to replace the zero input with an implicit zero.
9323 if (!IsV1Zero && !IsV2Zero) {
9324 // Check for patterns which can be matched with a single insert of a 128-bit
9326 bool OnlyUsesV1 = isShuffleEquivalent(V1, V2, Mask, {0, 1, 0, 1});
9327 if (OnlyUsesV1 || isShuffleEquivalent(V1, V2, Mask, {0, 1, 4, 5})) {
9328 MVT SubVT = MVT::getVectorVT(VT.getVectorElementType(),
9329 VT.getVectorNumElements() / 2);
9330 SDValue LoV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SubVT, V1,
9331 DAG.getIntPtrConstant(0, DL));
9332 SDValue HiV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SubVT,
9333 OnlyUsesV1 ? V1 : V2,
9334 DAG.getIntPtrConstant(0, DL));
9335 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, LoV, HiV);
9339 // Otherwise form a 128-bit permutation. After accounting for undefs,
9340 // convert the 64-bit shuffle mask selection values into 128-bit
9341 // selection bits by dividing the indexes by 2 and shifting into positions
9342 // defined by a vperm2*128 instruction's immediate control byte.
9344 // The immediate permute control byte looks like this:
9345 // [1:0] - select 128 bits from sources for low half of destination
9347 // [3] - zero low half of destination
9348 // [5:4] - select 128 bits from sources for high half of destination
9350 // [7] - zero high half of destination
9352 int MaskLO = Mask[0];
9353 if (MaskLO == SM_SentinelUndef)
9354 MaskLO = Mask[1] == SM_SentinelUndef ? 0 : Mask[1];
9356 int MaskHI = Mask[2];
9357 if (MaskHI == SM_SentinelUndef)
9358 MaskHI = Mask[3] == SM_SentinelUndef ? 0 : Mask[3];
9360 unsigned PermMask = MaskLO / 2 | (MaskHI / 2) << 4;
9362 // If either input is a zero vector, replace it with an undef input.
9363 // Shuffle mask values < 4 are selecting elements of V1.
9364 // Shuffle mask values >= 4 are selecting elements of V2.
9365 // Adjust each half of the permute mask by clearing the half that was
9366 // selecting the zero vector and setting the zero mask bit.
9368 V1 = DAG.getUNDEF(VT);
9370 PermMask = (PermMask & 0xf0) | 0x08;
9372 PermMask = (PermMask & 0x0f) | 0x80;
9375 V2 = DAG.getUNDEF(VT);
9377 PermMask = (PermMask & 0xf0) | 0x08;
9379 PermMask = (PermMask & 0x0f) | 0x80;
9382 return DAG.getNode(X86ISD::VPERM2X128, DL, VT, V1, V2,
9383 DAG.getConstant(PermMask, DL, MVT::i8));
9386 /// \brief Lower a vector shuffle by first fixing the 128-bit lanes and then
9387 /// shuffling each lane.
9389 /// This will only succeed when the result of fixing the 128-bit lanes results
9390 /// in a single-input non-lane-crossing shuffle with a repeating shuffle mask in
9391 /// each 128-bit lanes. This handles many cases where we can quickly blend away
9392 /// the lane crosses early and then use simpler shuffles within each lane.
9394 /// FIXME: It might be worthwhile at some point to support this without
9395 /// requiring the 128-bit lane-relative shuffles to be repeating, but currently
9396 /// in x86 only floating point has interesting non-repeating shuffles, and even
9397 /// those are still *marginally* more expensive.
9398 static SDValue lowerVectorShuffleByMerging128BitLanes(
9399 SDLoc DL, MVT VT, SDValue V1, SDValue V2, ArrayRef<int> Mask,
9400 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
9401 assert(!isSingleInputShuffleMask(Mask) &&
9402 "This is only useful with multiple inputs.");
9404 int Size = Mask.size();
9405 int LaneSize = 128 / VT.getScalarSizeInBits();
9406 int NumLanes = Size / LaneSize;
9407 assert(NumLanes > 1 && "Only handles 256-bit and wider shuffles.");
9409 // See if we can build a hypothetical 128-bit lane-fixing shuffle mask. Also
9410 // check whether the in-128-bit lane shuffles share a repeating pattern.
9411 SmallVector<int, 4> Lanes;
9412 Lanes.resize(NumLanes, -1);
9413 SmallVector<int, 4> InLaneMask;
9414 InLaneMask.resize(LaneSize, -1);
9415 for (int i = 0; i < Size; ++i) {
9419 int j = i / LaneSize;
9422 // First entry we've seen for this lane.
9423 Lanes[j] = Mask[i] / LaneSize;
9424 } else if (Lanes[j] != Mask[i] / LaneSize) {
9425 // This doesn't match the lane selected previously!
9429 // Check that within each lane we have a consistent shuffle mask.
9430 int k = i % LaneSize;
9431 if (InLaneMask[k] < 0) {
9432 InLaneMask[k] = Mask[i] % LaneSize;
9433 } else if (InLaneMask[k] != Mask[i] % LaneSize) {
9434 // This doesn't fit a repeating in-lane mask.
9439 // First shuffle the lanes into place.
9440 MVT LaneVT = MVT::getVectorVT(VT.isFloatingPoint() ? MVT::f64 : MVT::i64,
9441 VT.getSizeInBits() / 64);
9442 SmallVector<int, 8> LaneMask;
9443 LaneMask.resize(NumLanes * 2, -1);
9444 for (int i = 0; i < NumLanes; ++i)
9445 if (Lanes[i] >= 0) {
9446 LaneMask[2 * i + 0] = 2*Lanes[i] + 0;
9447 LaneMask[2 * i + 1] = 2*Lanes[i] + 1;
9450 V1 = DAG.getBitcast(LaneVT, V1);
9451 V2 = DAG.getBitcast(LaneVT, V2);
9452 SDValue LaneShuffle = DAG.getVectorShuffle(LaneVT, DL, V1, V2, LaneMask);
9454 // Cast it back to the type we actually want.
9455 LaneShuffle = DAG.getBitcast(VT, LaneShuffle);
9457 // Now do a simple shuffle that isn't lane crossing.
9458 SmallVector<int, 8> NewMask;
9459 NewMask.resize(Size, -1);
9460 for (int i = 0; i < Size; ++i)
9462 NewMask[i] = (i / LaneSize) * LaneSize + Mask[i] % LaneSize;
9463 assert(!is128BitLaneCrossingShuffleMask(VT, NewMask) &&
9464 "Must not introduce lane crosses at this point!");
9466 return DAG.getVectorShuffle(VT, DL, LaneShuffle, DAG.getUNDEF(VT), NewMask);
9469 /// \brief Test whether the specified input (0 or 1) is in-place blended by the
9472 /// This returns true if the elements from a particular input are already in the
9473 /// slot required by the given mask and require no permutation.
9474 static bool isShuffleMaskInputInPlace(int Input, ArrayRef<int> Mask) {
9475 assert((Input == 0 || Input == 1) && "Only two inputs to shuffles.");
9476 int Size = Mask.size();
9477 for (int i = 0; i < Size; ++i)
9478 if (Mask[i] >= 0 && Mask[i] / Size == Input && Mask[i] % Size != i)
9484 static SDValue lowerVectorShuffleWithSHUFPD(SDLoc DL, MVT VT,
9485 ArrayRef<int> Mask, SDValue V1,
9486 SDValue V2, SelectionDAG &DAG) {
9488 // Mask for V8F64: 0/1, 8/9, 2/3, 10/11, 4/5, ..
9489 // Mask for V4F64; 0/1, 4/5, 2/3, 6/7..
9490 assert(VT.getScalarSizeInBits() == 64 && "Unexpected data type for VSHUFPD");
9491 int NumElts = VT.getVectorNumElements();
9492 bool ShufpdMask = true;
9493 bool CommutableMask = true;
9494 unsigned Immediate = 0;
9495 for (int i = 0; i < NumElts; ++i) {
9498 int Val = (i & 6) + NumElts * (i & 1);
9499 int CommutVal = (i & 0xe) + NumElts * ((i & 1)^1);
9500 if (Mask[i] < Val || Mask[i] > Val + 1)
9502 if (Mask[i] < CommutVal || Mask[i] > CommutVal + 1)
9503 CommutableMask = false;
9504 Immediate |= (Mask[i] % 2) << i;
9507 return DAG.getNode(X86ISD::SHUFP, DL, VT, V1, V2,
9508 DAG.getConstant(Immediate, DL, MVT::i8));
9510 return DAG.getNode(X86ISD::SHUFP, DL, VT, V2, V1,
9511 DAG.getConstant(Immediate, DL, MVT::i8));
9515 /// \brief Handle lowering of 4-lane 64-bit floating point shuffles.
9517 /// Also ends up handling lowering of 4-lane 64-bit integer shuffles when AVX2
9518 /// isn't available.
9519 static SDValue lowerV4F64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9520 const X86Subtarget *Subtarget,
9521 SelectionDAG &DAG) {
9523 assert(V1.getSimpleValueType() == MVT::v4f64 && "Bad operand type!");
9524 assert(V2.getSimpleValueType() == MVT::v4f64 && "Bad operand type!");
9525 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9526 ArrayRef<int> Mask = SVOp->getMask();
9527 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
9529 SmallVector<int, 4> WidenedMask;
9530 if (canWidenShuffleElements(Mask, WidenedMask))
9531 return lowerV2X128VectorShuffle(DL, MVT::v4f64, V1, V2, Mask, Subtarget,
9534 if (isSingleInputShuffleMask(Mask)) {
9535 // Check for being able to broadcast a single element.
9536 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v4f64, V1,
9537 Mask, Subtarget, DAG))
9540 // Use low duplicate instructions for masks that match their pattern.
9541 if (isShuffleEquivalent(V1, V2, Mask, {0, 0, 2, 2}))
9542 return DAG.getNode(X86ISD::MOVDDUP, DL, MVT::v4f64, V1);
9544 if (!is128BitLaneCrossingShuffleMask(MVT::v4f64, Mask)) {
9545 // Non-half-crossing single input shuffles can be lowerid with an
9546 // interleaved permutation.
9547 unsigned VPERMILPMask = (Mask[0] == 1) | ((Mask[1] == 1) << 1) |
9548 ((Mask[2] == 3) << 2) | ((Mask[3] == 3) << 3);
9549 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v4f64, V1,
9550 DAG.getConstant(VPERMILPMask, DL, MVT::i8));
9553 // With AVX2 we have direct support for this permutation.
9554 if (Subtarget->hasAVX2())
9555 return DAG.getNode(X86ISD::VPERMI, DL, MVT::v4f64, V1,
9556 getV4X86ShuffleImm8ForMask(Mask, DL, DAG));
9558 // Otherwise, fall back.
9559 return lowerVectorShuffleAsLanePermuteAndBlend(DL, MVT::v4f64, V1, V2, Mask,
9563 // X86 has dedicated unpack instructions that can handle specific blend
9564 // operations: UNPCKH and UNPCKL.
9565 if (isShuffleEquivalent(V1, V2, Mask, {0, 4, 2, 6}))
9566 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4f64, V1, V2);
9567 if (isShuffleEquivalent(V1, V2, Mask, {1, 5, 3, 7}))
9568 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4f64, V1, V2);
9569 if (isShuffleEquivalent(V1, V2, Mask, {4, 0, 6, 2}))
9570 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4f64, V2, V1);
9571 if (isShuffleEquivalent(V1, V2, Mask, {5, 1, 7, 3}))
9572 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4f64, V2, V1);
9574 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4f64, V1, V2, Mask,
9578 // Check if the blend happens to exactly fit that of SHUFPD.
9580 lowerVectorShuffleWithSHUFPD(DL, MVT::v4f64, Mask, V1, V2, DAG))
9583 // Try to simplify this by merging 128-bit lanes to enable a lane-based
9584 // shuffle. However, if we have AVX2 and either inputs are already in place,
9585 // we will be able to shuffle even across lanes the other input in a single
9586 // instruction so skip this pattern.
9587 if (!(Subtarget->hasAVX2() && (isShuffleMaskInputInPlace(0, Mask) ||
9588 isShuffleMaskInputInPlace(1, Mask))))
9589 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
9590 DL, MVT::v4f64, V1, V2, Mask, Subtarget, DAG))
9593 // If we have AVX2 then we always want to lower with a blend because an v4 we
9594 // can fully permute the elements.
9595 if (Subtarget->hasAVX2())
9596 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v4f64, V1, V2,
9599 // Otherwise fall back on generic lowering.
9600 return lowerVectorShuffleAsSplitOrBlend(DL, MVT::v4f64, V1, V2, Mask, DAG);
9603 /// \brief Handle lowering of 4-lane 64-bit integer shuffles.
9605 /// This routine is only called when we have AVX2 and thus a reasonable
9606 /// instruction set for v4i64 shuffling..
9607 static SDValue lowerV4I64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9608 const X86Subtarget *Subtarget,
9609 SelectionDAG &DAG) {
9611 assert(V1.getSimpleValueType() == MVT::v4i64 && "Bad operand type!");
9612 assert(V2.getSimpleValueType() == MVT::v4i64 && "Bad operand type!");
9613 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9614 ArrayRef<int> Mask = SVOp->getMask();
9615 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
9616 assert(Subtarget->hasAVX2() && "We can only lower v4i64 with AVX2!");
9618 SmallVector<int, 4> WidenedMask;
9619 if (canWidenShuffleElements(Mask, WidenedMask))
9620 return lowerV2X128VectorShuffle(DL, MVT::v4i64, V1, V2, Mask, Subtarget,
9623 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4i64, V1, V2, Mask,
9627 // Check for being able to broadcast a single element.
9628 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v4i64, V1,
9629 Mask, Subtarget, DAG))
9632 // When the shuffle is mirrored between the 128-bit lanes of the unit, we can
9633 // use lower latency instructions that will operate on both 128-bit lanes.
9634 SmallVector<int, 2> RepeatedMask;
9635 if (is128BitLaneRepeatedShuffleMask(MVT::v4i64, Mask, RepeatedMask)) {
9636 if (isSingleInputShuffleMask(Mask)) {
9637 int PSHUFDMask[] = {-1, -1, -1, -1};
9638 for (int i = 0; i < 2; ++i)
9639 if (RepeatedMask[i] >= 0) {
9640 PSHUFDMask[2 * i] = 2 * RepeatedMask[i];
9641 PSHUFDMask[2 * i + 1] = 2 * RepeatedMask[i] + 1;
9643 return DAG.getBitcast(
9645 DAG.getNode(X86ISD::PSHUFD, DL, MVT::v8i32,
9646 DAG.getBitcast(MVT::v8i32, V1),
9647 getV4X86ShuffleImm8ForMask(PSHUFDMask, DL, DAG)));
9651 // AVX2 provides a direct instruction for permuting a single input across
9653 if (isSingleInputShuffleMask(Mask))
9654 return DAG.getNode(X86ISD::VPERMI, DL, MVT::v4i64, V1,
9655 getV4X86ShuffleImm8ForMask(Mask, DL, DAG));
9657 // Try to use shift instructions.
9659 lowerVectorShuffleAsShift(DL, MVT::v4i64, V1, V2, Mask, DAG))
9662 // Use dedicated unpack instructions for masks that match their pattern.
9663 if (isShuffleEquivalent(V1, V2, Mask, {0, 4, 2, 6}))
9664 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4i64, V1, V2);
9665 if (isShuffleEquivalent(V1, V2, Mask, {1, 5, 3, 7}))
9666 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4i64, V1, V2);
9667 if (isShuffleEquivalent(V1, V2, Mask, {4, 0, 6, 2}))
9668 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4i64, V2, V1);
9669 if (isShuffleEquivalent(V1, V2, Mask, {5, 1, 7, 3}))
9670 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4i64, V2, V1);
9672 // Try to simplify this by merging 128-bit lanes to enable a lane-based
9673 // shuffle. However, if we have AVX2 and either inputs are already in place,
9674 // we will be able to shuffle even across lanes the other input in a single
9675 // instruction so skip this pattern.
9676 if (!(Subtarget->hasAVX2() && (isShuffleMaskInputInPlace(0, Mask) ||
9677 isShuffleMaskInputInPlace(1, Mask))))
9678 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
9679 DL, MVT::v4i64, V1, V2, Mask, Subtarget, DAG))
9682 // Otherwise fall back on generic blend lowering.
9683 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v4i64, V1, V2,
9687 /// \brief Handle lowering of 8-lane 32-bit floating point shuffles.
9689 /// Also ends up handling lowering of 8-lane 32-bit integer shuffles when AVX2
9690 /// isn't available.
9691 static SDValue lowerV8F32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9692 const X86Subtarget *Subtarget,
9693 SelectionDAG &DAG) {
9695 assert(V1.getSimpleValueType() == MVT::v8f32 && "Bad operand type!");
9696 assert(V2.getSimpleValueType() == MVT::v8f32 && "Bad operand type!");
9697 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9698 ArrayRef<int> Mask = SVOp->getMask();
9699 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
9701 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v8f32, V1, V2, Mask,
9705 // Check for being able to broadcast a single element.
9706 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v8f32, V1,
9707 Mask, Subtarget, DAG))
9710 // If the shuffle mask is repeated in each 128-bit lane, we have many more
9711 // options to efficiently lower the shuffle.
9712 SmallVector<int, 4> RepeatedMask;
9713 if (is128BitLaneRepeatedShuffleMask(MVT::v8f32, Mask, RepeatedMask)) {
9714 assert(RepeatedMask.size() == 4 &&
9715 "Repeated masks must be half the mask width!");
9717 // Use even/odd duplicate instructions for masks that match their pattern.
9718 if (isShuffleEquivalent(V1, V2, Mask, {0, 0, 2, 2, 4, 4, 6, 6}))
9719 return DAG.getNode(X86ISD::MOVSLDUP, DL, MVT::v8f32, V1);
9720 if (isShuffleEquivalent(V1, V2, Mask, {1, 1, 3, 3, 5, 5, 7, 7}))
9721 return DAG.getNode(X86ISD::MOVSHDUP, DL, MVT::v8f32, V1);
9723 if (isSingleInputShuffleMask(Mask))
9724 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v8f32, V1,
9725 getV4X86ShuffleImm8ForMask(RepeatedMask, DL, DAG));
9727 // Use dedicated unpack instructions for masks that match their pattern.
9728 if (isShuffleEquivalent(V1, V2, Mask, {0, 8, 1, 9, 4, 12, 5, 13}))
9729 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8f32, V1, V2);
9730 if (isShuffleEquivalent(V1, V2, Mask, {2, 10, 3, 11, 6, 14, 7, 15}))
9731 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8f32, V1, V2);
9732 if (isShuffleEquivalent(V1, V2, Mask, {8, 0, 9, 1, 12, 4, 13, 5}))
9733 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8f32, V2, V1);
9734 if (isShuffleEquivalent(V1, V2, Mask, {10, 2, 11, 3, 14, 6, 15, 7}))
9735 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8f32, V2, V1);
9737 // Otherwise, fall back to a SHUFPS sequence. Here it is important that we
9738 // have already handled any direct blends. We also need to squash the
9739 // repeated mask into a simulated v4f32 mask.
9740 for (int i = 0; i < 4; ++i)
9741 if (RepeatedMask[i] >= 8)
9742 RepeatedMask[i] -= 4;
9743 return lowerVectorShuffleWithSHUFPS(DL, MVT::v8f32, RepeatedMask, V1, V2, DAG);
9746 // If we have a single input shuffle with different shuffle patterns in the
9747 // two 128-bit lanes use the variable mask to VPERMILPS.
9748 if (isSingleInputShuffleMask(Mask)) {
9749 SDValue VPermMask[8];
9750 for (int i = 0; i < 8; ++i)
9751 VPermMask[i] = Mask[i] < 0 ? DAG.getUNDEF(MVT::i32)
9752 : DAG.getConstant(Mask[i], DL, MVT::i32);
9753 if (!is128BitLaneCrossingShuffleMask(MVT::v8f32, Mask))
9755 X86ISD::VPERMILPV, DL, MVT::v8f32, V1,
9756 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v8i32, VPermMask));
9758 if (Subtarget->hasAVX2())
9760 X86ISD::VPERMV, DL, MVT::v8f32,
9761 DAG.getBitcast(MVT::v8f32, DAG.getNode(ISD::BUILD_VECTOR, DL,
9762 MVT::v8i32, VPermMask)),
9765 // Otherwise, fall back.
9766 return lowerVectorShuffleAsLanePermuteAndBlend(DL, MVT::v8f32, V1, V2, Mask,
9770 // Try to simplify this by merging 128-bit lanes to enable a lane-based
9772 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
9773 DL, MVT::v8f32, V1, V2, Mask, Subtarget, DAG))
9776 // If we have AVX2 then we always want to lower with a blend because at v8 we
9777 // can fully permute the elements.
9778 if (Subtarget->hasAVX2())
9779 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v8f32, V1, V2,
9782 // Otherwise fall back on generic lowering.
9783 return lowerVectorShuffleAsSplitOrBlend(DL, MVT::v8f32, V1, V2, Mask, DAG);
9786 /// \brief Handle lowering of 8-lane 32-bit integer shuffles.
9788 /// This routine is only called when we have AVX2 and thus a reasonable
9789 /// instruction set for v8i32 shuffling..
9790 static SDValue lowerV8I32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9791 const X86Subtarget *Subtarget,
9792 SelectionDAG &DAG) {
9794 assert(V1.getSimpleValueType() == MVT::v8i32 && "Bad operand type!");
9795 assert(V2.getSimpleValueType() == MVT::v8i32 && "Bad operand type!");
9796 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9797 ArrayRef<int> Mask = SVOp->getMask();
9798 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
9799 assert(Subtarget->hasAVX2() && "We can only lower v8i32 with AVX2!");
9801 // Whenever we can lower this as a zext, that instruction is strictly faster
9802 // than any alternative. It also allows us to fold memory operands into the
9803 // shuffle in many cases.
9804 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(DL, MVT::v8i32, V1, V2,
9805 Mask, Subtarget, DAG))
9808 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v8i32, V1, V2, Mask,
9812 // Check for being able to broadcast a single element.
9813 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v8i32, V1,
9814 Mask, Subtarget, DAG))
9817 // If the shuffle mask is repeated in each 128-bit lane we can use more
9818 // efficient instructions that mirror the shuffles across the two 128-bit
9820 SmallVector<int, 4> RepeatedMask;
9821 if (is128BitLaneRepeatedShuffleMask(MVT::v8i32, Mask, RepeatedMask)) {
9822 assert(RepeatedMask.size() == 4 && "Unexpected repeated mask size!");
9823 if (isSingleInputShuffleMask(Mask))
9824 return DAG.getNode(X86ISD::PSHUFD, DL, MVT::v8i32, V1,
9825 getV4X86ShuffleImm8ForMask(RepeatedMask, DL, DAG));
9827 // Use dedicated unpack instructions for masks that match their pattern.
9828 if (isShuffleEquivalent(V1, V2, Mask, {0, 8, 1, 9, 4, 12, 5, 13}))
9829 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8i32, V1, V2);
9830 if (isShuffleEquivalent(V1, V2, Mask, {2, 10, 3, 11, 6, 14, 7, 15}))
9831 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8i32, V1, V2);
9832 if (isShuffleEquivalent(V1, V2, Mask, {8, 0, 9, 1, 12, 4, 13, 5}))
9833 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8i32, V2, V1);
9834 if (isShuffleEquivalent(V1, V2, Mask, {10, 2, 11, 3, 14, 6, 15, 7}))
9835 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8i32, V2, V1);
9838 // Try to use shift instructions.
9840 lowerVectorShuffleAsShift(DL, MVT::v8i32, V1, V2, Mask, DAG))
9843 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
9844 DL, MVT::v8i32, V1, V2, Mask, Subtarget, DAG))
9847 // If the shuffle patterns aren't repeated but it is a single input, directly
9848 // generate a cross-lane VPERMD instruction.
9849 if (isSingleInputShuffleMask(Mask)) {
9850 SDValue VPermMask[8];
9851 for (int i = 0; i < 8; ++i)
9852 VPermMask[i] = Mask[i] < 0 ? DAG.getUNDEF(MVT::i32)
9853 : DAG.getConstant(Mask[i], DL, MVT::i32);
9855 X86ISD::VPERMV, DL, MVT::v8i32,
9856 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v8i32, VPermMask), V1);
9859 // Try to simplify this by merging 128-bit lanes to enable a lane-based
9861 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
9862 DL, MVT::v8i32, V1, V2, Mask, Subtarget, DAG))
9865 // Otherwise fall back on generic blend lowering.
9866 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v8i32, V1, V2,
9870 /// \brief Handle lowering of 16-lane 16-bit integer shuffles.
9872 /// This routine is only called when we have AVX2 and thus a reasonable
9873 /// instruction set for v16i16 shuffling..
9874 static SDValue lowerV16I16VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9875 const X86Subtarget *Subtarget,
9876 SelectionDAG &DAG) {
9878 assert(V1.getSimpleValueType() == MVT::v16i16 && "Bad operand type!");
9879 assert(V2.getSimpleValueType() == MVT::v16i16 && "Bad operand type!");
9880 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9881 ArrayRef<int> Mask = SVOp->getMask();
9882 assert(Mask.size() == 16 && "Unexpected mask size for v16 shuffle!");
9883 assert(Subtarget->hasAVX2() && "We can only lower v16i16 with AVX2!");
9885 // Whenever we can lower this as a zext, that instruction is strictly faster
9886 // than any alternative. It also allows us to fold memory operands into the
9887 // shuffle in many cases.
9888 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(DL, MVT::v16i16, V1, V2,
9889 Mask, Subtarget, DAG))
9892 // Check for being able to broadcast a single element.
9893 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v16i16, V1,
9894 Mask, Subtarget, DAG))
9897 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v16i16, V1, V2, Mask,
9901 // Use dedicated unpack instructions for masks that match their pattern.
9902 if (isShuffleEquivalent(V1, V2, Mask,
9903 {// First 128-bit lane:
9904 0, 16, 1, 17, 2, 18, 3, 19,
9905 // Second 128-bit lane:
9906 8, 24, 9, 25, 10, 26, 11, 27}))
9907 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v16i16, V1, V2);
9908 if (isShuffleEquivalent(V1, V2, Mask,
9909 {// First 128-bit lane:
9910 4, 20, 5, 21, 6, 22, 7, 23,
9911 // Second 128-bit lane:
9912 12, 28, 13, 29, 14, 30, 15, 31}))
9913 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v16i16, V1, V2);
9915 // Try to use shift instructions.
9917 lowerVectorShuffleAsShift(DL, MVT::v16i16, V1, V2, Mask, DAG))
9920 // Try to use byte rotation instructions.
9921 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
9922 DL, MVT::v16i16, V1, V2, Mask, Subtarget, DAG))
9925 if (isSingleInputShuffleMask(Mask)) {
9926 // There are no generalized cross-lane shuffle operations available on i16
9928 if (is128BitLaneCrossingShuffleMask(MVT::v16i16, Mask))
9929 return lowerVectorShuffleAsLanePermuteAndBlend(DL, MVT::v16i16, V1, V2,
9932 SmallVector<int, 8> RepeatedMask;
9933 if (is128BitLaneRepeatedShuffleMask(MVT::v16i16, Mask, RepeatedMask)) {
9934 // As this is a single-input shuffle, the repeated mask should be
9935 // a strictly valid v8i16 mask that we can pass through to the v8i16
9936 // lowering to handle even the v16 case.
9937 return lowerV8I16GeneralSingleInputVectorShuffle(
9938 DL, MVT::v16i16, V1, RepeatedMask, Subtarget, DAG);
9941 SDValue PSHUFBMask[32];
9942 for (int i = 0; i < 16; ++i) {
9943 if (Mask[i] == -1) {
9944 PSHUFBMask[2 * i] = PSHUFBMask[2 * i + 1] = DAG.getUNDEF(MVT::i8);
9948 int M = i < 8 ? Mask[i] : Mask[i] - 8;
9949 assert(M >= 0 && M < 8 && "Invalid single-input mask!");
9950 PSHUFBMask[2 * i] = DAG.getConstant(2 * M, DL, MVT::i8);
9951 PSHUFBMask[2 * i + 1] = DAG.getConstant(2 * M + 1, DL, MVT::i8);
9953 return DAG.getBitcast(MVT::v16i16,
9954 DAG.getNode(X86ISD::PSHUFB, DL, MVT::v32i8,
9955 DAG.getBitcast(MVT::v32i8, V1),
9956 DAG.getNode(ISD::BUILD_VECTOR, DL,
9957 MVT::v32i8, PSHUFBMask)));
9960 // Try to simplify this by merging 128-bit lanes to enable a lane-based
9962 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
9963 DL, MVT::v16i16, V1, V2, Mask, Subtarget, DAG))
9966 // Otherwise fall back on generic lowering.
9967 return lowerVectorShuffleAsSplitOrBlend(DL, MVT::v16i16, V1, V2, Mask, DAG);
9970 /// \brief Handle lowering of 32-lane 8-bit integer shuffles.
9972 /// This routine is only called when we have AVX2 and thus a reasonable
9973 /// instruction set for v32i8 shuffling..
9974 static SDValue lowerV32I8VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9975 const X86Subtarget *Subtarget,
9976 SelectionDAG &DAG) {
9978 assert(V1.getSimpleValueType() == MVT::v32i8 && "Bad operand type!");
9979 assert(V2.getSimpleValueType() == MVT::v32i8 && "Bad operand type!");
9980 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9981 ArrayRef<int> Mask = SVOp->getMask();
9982 assert(Mask.size() == 32 && "Unexpected mask size for v32 shuffle!");
9983 assert(Subtarget->hasAVX2() && "We can only lower v32i8 with AVX2!");
9985 // Whenever we can lower this as a zext, that instruction is strictly faster
9986 // than any alternative. It also allows us to fold memory operands into the
9987 // shuffle in many cases.
9988 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(DL, MVT::v32i8, V1, V2,
9989 Mask, Subtarget, DAG))
9992 // Check for being able to broadcast a single element.
9993 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v32i8, V1,
9994 Mask, Subtarget, DAG))
9997 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v32i8, V1, V2, Mask,
10001 // Use dedicated unpack instructions for masks that match their pattern.
10002 // Note that these are repeated 128-bit lane unpacks, not unpacks across all
10004 if (isShuffleEquivalent(
10006 {// First 128-bit lane:
10007 0, 32, 1, 33, 2, 34, 3, 35, 4, 36, 5, 37, 6, 38, 7, 39,
10008 // Second 128-bit lane:
10009 16, 48, 17, 49, 18, 50, 19, 51, 20, 52, 21, 53, 22, 54, 23, 55}))
10010 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v32i8, V1, V2);
10011 if (isShuffleEquivalent(
10013 {// First 128-bit lane:
10014 8, 40, 9, 41, 10, 42, 11, 43, 12, 44, 13, 45, 14, 46, 15, 47,
10015 // Second 128-bit lane:
10016 24, 56, 25, 57, 26, 58, 27, 59, 28, 60, 29, 61, 30, 62, 31, 63}))
10017 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v32i8, V1, V2);
10019 // Try to use shift instructions.
10020 if (SDValue Shift =
10021 lowerVectorShuffleAsShift(DL, MVT::v32i8, V1, V2, Mask, DAG))
10024 // Try to use byte rotation instructions.
10025 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
10026 DL, MVT::v32i8, V1, V2, Mask, Subtarget, DAG))
10029 if (isSingleInputShuffleMask(Mask)) {
10030 // There are no generalized cross-lane shuffle operations available on i8
10032 if (is128BitLaneCrossingShuffleMask(MVT::v32i8, Mask))
10033 return lowerVectorShuffleAsLanePermuteAndBlend(DL, MVT::v32i8, V1, V2,
10036 SDValue PSHUFBMask[32];
10037 for (int i = 0; i < 32; ++i)
10040 ? DAG.getUNDEF(MVT::i8)
10041 : DAG.getConstant(Mask[i] < 16 ? Mask[i] : Mask[i] - 16, DL,
10044 return DAG.getNode(
10045 X86ISD::PSHUFB, DL, MVT::v32i8, V1,
10046 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v32i8, PSHUFBMask));
10049 // Try to simplify this by merging 128-bit lanes to enable a lane-based
10051 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
10052 DL, MVT::v32i8, V1, V2, Mask, Subtarget, DAG))
10055 // Otherwise fall back on generic lowering.
10056 return lowerVectorShuffleAsSplitOrBlend(DL, MVT::v32i8, V1, V2, Mask, DAG);
10059 /// \brief High-level routine to lower various 256-bit x86 vector shuffles.
10061 /// This routine either breaks down the specific type of a 256-bit x86 vector
10062 /// shuffle or splits it into two 128-bit shuffles and fuses the results back
10063 /// together based on the available instructions.
10064 static SDValue lower256BitVectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10065 MVT VT, const X86Subtarget *Subtarget,
10066 SelectionDAG &DAG) {
10068 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10069 ArrayRef<int> Mask = SVOp->getMask();
10071 // If we have a single input to the zero element, insert that into V1 if we
10072 // can do so cheaply.
10073 int NumElts = VT.getVectorNumElements();
10074 int NumV2Elements = std::count_if(Mask.begin(), Mask.end(), [NumElts](int M) {
10075 return M >= NumElts;
10078 if (NumV2Elements == 1 && Mask[0] >= NumElts)
10079 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
10080 DL, VT, V1, V2, Mask, Subtarget, DAG))
10083 // There is a really nice hard cut-over between AVX1 and AVX2 that means we can
10084 // check for those subtargets here and avoid much of the subtarget querying in
10085 // the per-vector-type lowering routines. With AVX1 we have essentially *zero*
10086 // ability to manipulate a 256-bit vector with integer types. Since we'll use
10087 // floating point types there eventually, just immediately cast everything to
10088 // a float and operate entirely in that domain.
10089 if (VT.isInteger() && !Subtarget->hasAVX2()) {
10090 int ElementBits = VT.getScalarSizeInBits();
10091 if (ElementBits < 32)
10092 // No floating point type available, decompose into 128-bit vectors.
10093 return splitAndLowerVectorShuffle(DL, VT, V1, V2, Mask, DAG);
10095 MVT FpVT = MVT::getVectorVT(MVT::getFloatingPointVT(ElementBits),
10096 VT.getVectorNumElements());
10097 V1 = DAG.getBitcast(FpVT, V1);
10098 V2 = DAG.getBitcast(FpVT, V2);
10099 return DAG.getBitcast(VT, DAG.getVectorShuffle(FpVT, DL, V1, V2, Mask));
10102 switch (VT.SimpleTy) {
10104 return lowerV4F64VectorShuffle(Op, V1, V2, Subtarget, DAG);
10106 return lowerV4I64VectorShuffle(Op, V1, V2, Subtarget, DAG);
10108 return lowerV8F32VectorShuffle(Op, V1, V2, Subtarget, DAG);
10110 return lowerV8I32VectorShuffle(Op, V1, V2, Subtarget, DAG);
10112 return lowerV16I16VectorShuffle(Op, V1, V2, Subtarget, DAG);
10114 return lowerV32I8VectorShuffle(Op, V1, V2, Subtarget, DAG);
10117 llvm_unreachable("Not a valid 256-bit x86 vector type!");
10121 static SDValue lowerVectorShuffleWithVALIGN(SDLoc DL, MVT VT,
10122 ArrayRef<int> Mask, SDValue V1,
10123 SDValue V2, SelectionDAG &DAG) {
10125 assert(VT.getScalarSizeInBits() >= 32 && "Unexpected data type for VALIGN");
10126 // VALIGN pattern 2, 3, 4, 5, .. (sequential, shifted right)
10128 for (int i = 0; i < (signed)VT.getVectorNumElements(); ++i) {
10133 if (AlignVal == -1)
10134 AlignVal = Mask[i] - i;
10135 else if (Mask[i] - i != AlignVal)
10138 // Vector source operands should be swapped
10139 return DAG.getNode(X86ISD::VALIGN, DL, VT, V2, V1,
10140 DAG.getConstant(AlignVal, DL, MVT::i8));
10143 static SDValue lowerVectorShuffleWithPERMV(SDLoc DL, MVT VT,
10144 ArrayRef<int> Mask, SDValue V1,
10145 SDValue V2, SelectionDAG &DAG) {
10147 assert(VT.getScalarSizeInBits() >= 16 && "Unexpected data type for PERMV");
10149 MVT MaskEltVT = MVT::getIntegerVT(VT.getScalarSizeInBits());
10150 MVT MaskVecVT = MVT::getVectorVT(MaskEltVT, VT.getVectorNumElements());
10152 SmallVector<SDValue, 32> VPermMask;
10153 for (unsigned i = 0; i < VT.getVectorNumElements(); ++i)
10154 VPermMask.push_back(Mask[i] < 0 ? DAG.getUNDEF(MaskEltVT) :
10155 DAG.getConstant(Mask[i], DL,MaskEltVT));
10156 SDValue MaskNode = DAG.getNode(ISD::BUILD_VECTOR, DL, MaskVecVT,
10158 if (isSingleInputShuffleMask(Mask))
10159 return DAG.getNode(X86ISD::VPERMV, DL, VT, MaskNode, V1);
10161 return DAG.getNode(X86ISD::VPERMV3, DL, VT, MaskNode, V1, V2);
10165 /// \brief Handle lowering of 8-lane 64-bit floating point shuffles.
10166 static SDValue lowerV8X64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10167 const X86Subtarget *Subtarget,
10168 SelectionDAG &DAG) {
10170 MVT VT = Op.getSimpleValueType();
10171 assert((V1.getSimpleValueType() == MVT::v8f64 ||
10172 V1.getSimpleValueType() == MVT::v8i64) && "Bad operand type!");
10173 assert((V2.getSimpleValueType() == MVT::v8f64 ||
10174 V2.getSimpleValueType() == MVT::v8i64) && "Bad operand type!");
10175 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10176 ArrayRef<int> Mask = SVOp->getMask();
10177 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
10179 // X86 has dedicated unpack instructions that can handle specific blend
10180 // operations: UNPCKH and UNPCKL.
10181 if (isShuffleEquivalent(V1, V2, Mask, {0, 8, 2, 10, 4, 12, 6, 14}))
10182 return DAG.getNode(X86ISD::UNPCKL, DL, VT, V1, V2);
10183 if (isShuffleEquivalent(V1, V2, Mask, {1, 9, 3, 11, 5, 13, 7, 15}))
10184 return DAG.getNode(X86ISD::UNPCKH, DL, VT, V1, V2);
10186 if (SDValue Op = lowerVectorShuffleWithVALIGN(DL, VT, Mask, V1, V2, DAG))
10189 if (SDValue Op = lowerVectorShuffleWithSHUFPD(DL, VT, Mask, V1, V2, DAG))
10192 // PERMILPD instruction - mask 0/1, 0/1, 2/3, 2/3, 4/5, 4/5, 6/7, 6/7
10193 if (isSingleInputShuffleMask(Mask)) {
10194 if (!is128BitLaneCrossingShuffleMask(VT, Mask))
10195 return DAG.getNode(X86ISD::VPERMILPI, DL, VT, V1,
10196 get1bitLaneShuffleImm8ForMask(Mask, DL, DAG));
10198 SmallVector<int, 4> RepeatedMask;
10199 if (is256BitLaneRepeatedShuffleMask(VT, Mask, RepeatedMask))
10200 return DAG.getNode(X86ISD::VPERMI, DL, VT, V1,
10201 getV4X86ShuffleImm8ForMask(RepeatedMask, DL, DAG));
10203 return lowerVectorShuffleWithPERMV(DL, VT, Mask, V1, V2, DAG);
10206 /// \brief Handle lowering of 16-lane 32-bit integer shuffles.
10207 static SDValue lowerV16X32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10208 const X86Subtarget *Subtarget,
10209 SelectionDAG &DAG) {
10210 MVT VT = Op.getSimpleValueType();
10212 assert((V1.getSimpleValueType() == MVT::v16i32 ||
10213 V1.getSimpleValueType() == MVT::v16f32) && "Bad operand type!");
10214 assert((V2.getSimpleValueType() == MVT::v16i32 ||
10215 V2.getSimpleValueType() == MVT::v16f32) && "Bad operand type!");
10216 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10217 ArrayRef<int> Mask = SVOp->getMask();
10218 assert(Mask.size() == 16 && "Unexpected mask size for v16 shuffle!");
10220 // Use dedicated unpack instructions for masks that match their pattern.
10221 if (isShuffleEquivalent(V1, V2, Mask,
10222 {// First 128-bit lane.
10223 0, 16, 1, 17, 4, 20, 5, 21,
10224 // Second 128-bit lane.
10225 8, 24, 9, 25, 12, 28, 13, 29}))
10226 return DAG.getNode(X86ISD::UNPCKL, DL, VT, V1, V2);
10227 if (isShuffleEquivalent(V1, V2, Mask,
10228 {// First 128-bit lane.
10229 2, 18, 3, 19, 6, 22, 7, 23,
10230 // Second 128-bit lane.
10231 10, 26, 11, 27, 14, 30, 15, 31}))
10232 return DAG.getNode(X86ISD::UNPCKH, DL, VT, V1, V2);
10234 if (isShuffleEquivalent(V1, V2, Mask, {0, 0, 2, 2, 4, 4, 6, 6, 8, 8, 10, 10,
10236 return DAG.getNode(X86ISD::MOVSLDUP, DL, VT, V1);
10237 if (isShuffleEquivalent(V1, V2, Mask, {1, 1, 3, 3, 5, 5, 7, 7, 9, 9, 11, 11,
10239 return DAG.getNode(X86ISD::MOVSHDUP, DL, VT, V1);
10241 SmallVector<int, 4> RepeatedMask;
10242 if (is128BitLaneRepeatedShuffleMask(VT, Mask, RepeatedMask)) {
10243 if (isSingleInputShuffleMask(Mask)) {
10244 unsigned Opc = VT.isInteger() ? X86ISD::PSHUFD : X86ISD::VPERMILPI;
10245 return DAG.getNode(Opc, DL, VT, V1,
10246 getV4X86ShuffleImm8ForMask(RepeatedMask, DL, DAG));
10249 for (int i = 0; i < 4; ++i)
10250 if (RepeatedMask[i] >= 16)
10251 RepeatedMask[i] -= 12;
10252 return lowerVectorShuffleWithSHUFPS(DL, VT, RepeatedMask, V1, V2, DAG);
10255 if (SDValue Op = lowerVectorShuffleWithVALIGN(DL, VT, Mask, V1, V2, DAG))
10258 return lowerVectorShuffleWithPERMV(DL, VT, Mask, V1, V2, DAG);
10261 /// \brief Handle lowering of 32-lane 16-bit integer shuffles.
10262 static SDValue lowerV32I16VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10263 const X86Subtarget *Subtarget,
10264 SelectionDAG &DAG) {
10266 assert(V1.getSimpleValueType() == MVT::v32i16 && "Bad operand type!");
10267 assert(V2.getSimpleValueType() == MVT::v32i16 && "Bad operand type!");
10268 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10269 ArrayRef<int> Mask = SVOp->getMask();
10270 assert(Mask.size() == 32 && "Unexpected mask size for v32 shuffle!");
10271 assert(Subtarget->hasBWI() && "We can only lower v32i16 with AVX-512-BWI!");
10273 // FIXME: Implement direct support for this type!
10274 return splitAndLowerVectorShuffle(DL, MVT::v32i16, V1, V2, Mask, DAG);
10277 /// \brief Handle lowering of 64-lane 8-bit integer shuffles.
10278 static SDValue lowerV64I8VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10279 const X86Subtarget *Subtarget,
10280 SelectionDAG &DAG) {
10282 assert(V1.getSimpleValueType() == MVT::v64i8 && "Bad operand type!");
10283 assert(V2.getSimpleValueType() == MVT::v64i8 && "Bad operand type!");
10284 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10285 ArrayRef<int> Mask = SVOp->getMask();
10286 assert(Mask.size() == 64 && "Unexpected mask size for v64 shuffle!");
10287 assert(Subtarget->hasBWI() && "We can only lower v64i8 with AVX-512-BWI!");
10289 // FIXME: Implement direct support for this type!
10290 return splitAndLowerVectorShuffle(DL, MVT::v64i8, V1, V2, Mask, DAG);
10293 /// \brief High-level routine to lower various 512-bit x86 vector shuffles.
10295 /// This routine either breaks down the specific type of a 512-bit x86 vector
10296 /// shuffle or splits it into two 256-bit shuffles and fuses the results back
10297 /// together based on the available instructions.
10298 static SDValue lower512BitVectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10299 MVT VT, const X86Subtarget *Subtarget,
10300 SelectionDAG &DAG) {
10302 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10303 ArrayRef<int> Mask = SVOp->getMask();
10304 assert(Subtarget->hasAVX512() &&
10305 "Cannot lower 512-bit vectors w/ basic ISA!");
10307 // Check for being able to broadcast a single element.
10308 if (SDValue Broadcast =
10309 lowerVectorShuffleAsBroadcast(DL, VT, V1, Mask, Subtarget, DAG))
10312 // Dispatch to each element type for lowering. If we don't have supprot for
10313 // specific element type shuffles at 512 bits, immediately split them and
10314 // lower them. Each lowering routine of a given type is allowed to assume that
10315 // the requisite ISA extensions for that element type are available.
10316 switch (VT.SimpleTy) {
10319 return lowerV8X64VectorShuffle(Op, V1, V2, Subtarget, DAG);
10322 return lowerV16X32VectorShuffle(Op, V1, V2, Subtarget, DAG);
10324 if (Subtarget->hasBWI())
10325 return lowerV32I16VectorShuffle(Op, V1, V2, Subtarget, DAG);
10328 if (Subtarget->hasBWI())
10329 return lowerV64I8VectorShuffle(Op, V1, V2, Subtarget, DAG);
10333 llvm_unreachable("Not a valid 512-bit x86 vector type!");
10336 // Otherwise fall back on splitting.
10337 return splitAndLowerVectorShuffle(DL, VT, V1, V2, Mask, DAG);
10340 /// \brief Top-level lowering for x86 vector shuffles.
10342 /// This handles decomposition, canonicalization, and lowering of all x86
10343 /// vector shuffles. Most of the specific lowering strategies are encapsulated
10344 /// above in helper routines. The canonicalization attempts to widen shuffles
10345 /// to involve fewer lanes of wider elements, consolidate symmetric patterns
10346 /// s.t. only one of the two inputs needs to be tested, etc.
10347 static SDValue lowerVectorShuffle(SDValue Op, const X86Subtarget *Subtarget,
10348 SelectionDAG &DAG) {
10349 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10350 ArrayRef<int> Mask = SVOp->getMask();
10351 SDValue V1 = Op.getOperand(0);
10352 SDValue V2 = Op.getOperand(1);
10353 MVT VT = Op.getSimpleValueType();
10354 int NumElements = VT.getVectorNumElements();
10357 assert(VT.getSizeInBits() != 64 && "Can't lower MMX shuffles");
10359 bool V1IsUndef = V1.getOpcode() == ISD::UNDEF;
10360 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
10361 if (V1IsUndef && V2IsUndef)
10362 return DAG.getUNDEF(VT);
10364 // When we create a shuffle node we put the UNDEF node to second operand,
10365 // but in some cases the first operand may be transformed to UNDEF.
10366 // In this case we should just commute the node.
10368 return DAG.getCommutedVectorShuffle(*SVOp);
10370 // Check for non-undef masks pointing at an undef vector and make the masks
10371 // undef as well. This makes it easier to match the shuffle based solely on
10375 if (M >= NumElements) {
10376 SmallVector<int, 8> NewMask(Mask.begin(), Mask.end());
10377 for (int &M : NewMask)
10378 if (M >= NumElements)
10380 return DAG.getVectorShuffle(VT, dl, V1, V2, NewMask);
10383 // We actually see shuffles that are entirely re-arrangements of a set of
10384 // zero inputs. This mostly happens while decomposing complex shuffles into
10385 // simple ones. Directly lower these as a buildvector of zeros.
10386 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
10387 if (Zeroable.all())
10388 return getZeroVector(VT, Subtarget, DAG, dl);
10390 // Try to collapse shuffles into using a vector type with fewer elements but
10391 // wider element types. We cap this to not form integers or floating point
10392 // elements wider than 64 bits, but it might be interesting to form i128
10393 // integers to handle flipping the low and high halves of AVX 256-bit vectors.
10394 SmallVector<int, 16> WidenedMask;
10395 if (VT.getScalarSizeInBits() < 64 &&
10396 canWidenShuffleElements(Mask, WidenedMask)) {
10397 MVT NewEltVT = VT.isFloatingPoint()
10398 ? MVT::getFloatingPointVT(VT.getScalarSizeInBits() * 2)
10399 : MVT::getIntegerVT(VT.getScalarSizeInBits() * 2);
10400 MVT NewVT = MVT::getVectorVT(NewEltVT, VT.getVectorNumElements() / 2);
10401 // Make sure that the new vector type is legal. For example, v2f64 isn't
10403 if (DAG.getTargetLoweringInfo().isTypeLegal(NewVT)) {
10404 V1 = DAG.getBitcast(NewVT, V1);
10405 V2 = DAG.getBitcast(NewVT, V2);
10406 return DAG.getBitcast(
10407 VT, DAG.getVectorShuffle(NewVT, dl, V1, V2, WidenedMask));
10411 int NumV1Elements = 0, NumUndefElements = 0, NumV2Elements = 0;
10412 for (int M : SVOp->getMask())
10414 ++NumUndefElements;
10415 else if (M < NumElements)
10420 // Commute the shuffle as needed such that more elements come from V1 than
10421 // V2. This allows us to match the shuffle pattern strictly on how many
10422 // elements come from V1 without handling the symmetric cases.
10423 if (NumV2Elements > NumV1Elements)
10424 return DAG.getCommutedVectorShuffle(*SVOp);
10426 // When the number of V1 and V2 elements are the same, try to minimize the
10427 // number of uses of V2 in the low half of the vector. When that is tied,
10428 // ensure that the sum of indices for V1 is equal to or lower than the sum
10429 // indices for V2. When those are equal, try to ensure that the number of odd
10430 // indices for V1 is lower than the number of odd indices for V2.
10431 if (NumV1Elements == NumV2Elements) {
10432 int LowV1Elements = 0, LowV2Elements = 0;
10433 for (int M : SVOp->getMask().slice(0, NumElements / 2))
10434 if (M >= NumElements)
10438 if (LowV2Elements > LowV1Elements) {
10439 return DAG.getCommutedVectorShuffle(*SVOp);
10440 } else if (LowV2Elements == LowV1Elements) {
10441 int SumV1Indices = 0, SumV2Indices = 0;
10442 for (int i = 0, Size = SVOp->getMask().size(); i < Size; ++i)
10443 if (SVOp->getMask()[i] >= NumElements)
10445 else if (SVOp->getMask()[i] >= 0)
10447 if (SumV2Indices < SumV1Indices) {
10448 return DAG.getCommutedVectorShuffle(*SVOp);
10449 } else if (SumV2Indices == SumV1Indices) {
10450 int NumV1OddIndices = 0, NumV2OddIndices = 0;
10451 for (int i = 0, Size = SVOp->getMask().size(); i < Size; ++i)
10452 if (SVOp->getMask()[i] >= NumElements)
10453 NumV2OddIndices += i % 2;
10454 else if (SVOp->getMask()[i] >= 0)
10455 NumV1OddIndices += i % 2;
10456 if (NumV2OddIndices < NumV1OddIndices)
10457 return DAG.getCommutedVectorShuffle(*SVOp);
10462 // For each vector width, delegate to a specialized lowering routine.
10463 if (VT.getSizeInBits() == 128)
10464 return lower128BitVectorShuffle(Op, V1, V2, VT, Subtarget, DAG);
10466 if (VT.getSizeInBits() == 256)
10467 return lower256BitVectorShuffle(Op, V1, V2, VT, Subtarget, DAG);
10469 // Force AVX-512 vectors to be scalarized for now.
10470 // FIXME: Implement AVX-512 support!
10471 if (VT.getSizeInBits() == 512)
10472 return lower512BitVectorShuffle(Op, V1, V2, VT, Subtarget, DAG);
10474 llvm_unreachable("Unimplemented!");
10477 // This function assumes its argument is a BUILD_VECTOR of constants or
10478 // undef SDNodes. i.e: ISD::isBuildVectorOfConstantSDNodes(BuildVector) is
10480 static bool BUILD_VECTORtoBlendMask(BuildVectorSDNode *BuildVector,
10481 unsigned &MaskValue) {
10483 unsigned NumElems = BuildVector->getNumOperands();
10484 // There are 2 lanes if (NumElems > 8), and 1 lane otherwise.
10485 unsigned NumLanes = (NumElems - 1) / 8 + 1;
10486 unsigned NumElemsInLane = NumElems / NumLanes;
10488 // Blend for v16i16 should be symetric for the both lanes.
10489 for (unsigned i = 0; i < NumElemsInLane; ++i) {
10490 SDValue EltCond = BuildVector->getOperand(i);
10491 SDValue SndLaneEltCond =
10492 (NumLanes == 2) ? BuildVector->getOperand(i + NumElemsInLane) : EltCond;
10494 int Lane1Cond = -1, Lane2Cond = -1;
10495 if (isa<ConstantSDNode>(EltCond))
10496 Lane1Cond = !isZero(EltCond);
10497 if (isa<ConstantSDNode>(SndLaneEltCond))
10498 Lane2Cond = !isZero(SndLaneEltCond);
10500 if (Lane1Cond == Lane2Cond || Lane2Cond < 0)
10501 // Lane1Cond != 0, means we want the first argument.
10502 // Lane1Cond == 0, means we want the second argument.
10503 // The encoding of this argument is 0 for the first argument, 1
10504 // for the second. Therefore, invert the condition.
10505 MaskValue |= !Lane1Cond << i;
10506 else if (Lane1Cond < 0)
10507 MaskValue |= !Lane2Cond << i;
10514 /// \brief Try to lower a VSELECT instruction to a vector shuffle.
10515 static SDValue lowerVSELECTtoVectorShuffle(SDValue Op,
10516 const X86Subtarget *Subtarget,
10517 SelectionDAG &DAG) {
10518 SDValue Cond = Op.getOperand(0);
10519 SDValue LHS = Op.getOperand(1);
10520 SDValue RHS = Op.getOperand(2);
10522 MVT VT = Op.getSimpleValueType();
10524 if (!ISD::isBuildVectorOfConstantSDNodes(Cond.getNode()))
10526 auto *CondBV = cast<BuildVectorSDNode>(Cond);
10528 // Only non-legal VSELECTs reach this lowering, convert those into generic
10529 // shuffles and re-use the shuffle lowering path for blends.
10530 SmallVector<int, 32> Mask;
10531 for (int i = 0, Size = VT.getVectorNumElements(); i < Size; ++i) {
10532 SDValue CondElt = CondBV->getOperand(i);
10534 isa<ConstantSDNode>(CondElt) ? i + (isZero(CondElt) ? Size : 0) : -1);
10536 return DAG.getVectorShuffle(VT, dl, LHS, RHS, Mask);
10539 SDValue X86TargetLowering::LowerVSELECT(SDValue Op, SelectionDAG &DAG) const {
10540 // A vselect where all conditions and data are constants can be optimized into
10541 // a single vector load by SelectionDAGLegalize::ExpandBUILD_VECTOR().
10542 if (ISD::isBuildVectorOfConstantSDNodes(Op.getOperand(0).getNode()) &&
10543 ISD::isBuildVectorOfConstantSDNodes(Op.getOperand(1).getNode()) &&
10544 ISD::isBuildVectorOfConstantSDNodes(Op.getOperand(2).getNode()))
10547 // Try to lower this to a blend-style vector shuffle. This can handle all
10548 // constant condition cases.
10549 if (SDValue BlendOp = lowerVSELECTtoVectorShuffle(Op, Subtarget, DAG))
10552 // Variable blends are only legal from SSE4.1 onward.
10553 if (!Subtarget->hasSSE41())
10556 // Only some types will be legal on some subtargets. If we can emit a legal
10557 // VSELECT-matching blend, return Op, and but if we need to expand, return
10559 switch (Op.getSimpleValueType().SimpleTy) {
10561 // Most of the vector types have blends past SSE4.1.
10565 // The byte blends for AVX vectors were introduced only in AVX2.
10566 if (Subtarget->hasAVX2())
10573 // AVX-512 BWI and VLX features support VSELECT with i16 elements.
10574 if (Subtarget->hasBWI() && Subtarget->hasVLX())
10577 // FIXME: We should custom lower this by fixing the condition and using i8
10583 static SDValue LowerEXTRACT_VECTOR_ELT_SSE4(SDValue Op, SelectionDAG &DAG) {
10584 MVT VT = Op.getSimpleValueType();
10587 if (!Op.getOperand(0).getSimpleValueType().is128BitVector())
10590 if (VT.getSizeInBits() == 8) {
10591 SDValue Extract = DAG.getNode(X86ISD::PEXTRB, dl, MVT::i32,
10592 Op.getOperand(0), Op.getOperand(1));
10593 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
10594 DAG.getValueType(VT));
10595 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
10598 if (VT.getSizeInBits() == 16) {
10599 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
10600 // If Idx is 0, it's cheaper to do a move instead of a pextrw.
10602 return DAG.getNode(
10603 ISD::TRUNCATE, dl, MVT::i16,
10604 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
10605 DAG.getBitcast(MVT::v4i32, Op.getOperand(0)),
10606 Op.getOperand(1)));
10607 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, MVT::i32,
10608 Op.getOperand(0), Op.getOperand(1));
10609 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
10610 DAG.getValueType(VT));
10611 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
10614 if (VT == MVT::f32) {
10615 // EXTRACTPS outputs to a GPR32 register which will require a movd to copy
10616 // the result back to FR32 register. It's only worth matching if the
10617 // result has a single use which is a store or a bitcast to i32. And in
10618 // the case of a store, it's not worth it if the index is a constant 0,
10619 // because a MOVSSmr can be used instead, which is smaller and faster.
10620 if (!Op.hasOneUse())
10622 SDNode *User = *Op.getNode()->use_begin();
10623 if ((User->getOpcode() != ISD::STORE ||
10624 (isa<ConstantSDNode>(Op.getOperand(1)) &&
10625 cast<ConstantSDNode>(Op.getOperand(1))->isNullValue())) &&
10626 (User->getOpcode() != ISD::BITCAST ||
10627 User->getValueType(0) != MVT::i32))
10629 SDValue Extract = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
10630 DAG.getBitcast(MVT::v4i32, Op.getOperand(0)),
10632 return DAG.getBitcast(MVT::f32, Extract);
10635 if (VT == MVT::i32 || VT == MVT::i64) {
10636 // ExtractPS/pextrq works with constant index.
10637 if (isa<ConstantSDNode>(Op.getOperand(1)))
10643 /// Extract one bit from mask vector, like v16i1 or v8i1.
10644 /// AVX-512 feature.
10646 X86TargetLowering::ExtractBitFromMaskVector(SDValue Op, SelectionDAG &DAG) const {
10647 SDValue Vec = Op.getOperand(0);
10649 MVT VecVT = Vec.getSimpleValueType();
10650 SDValue Idx = Op.getOperand(1);
10651 MVT EltVT = Op.getSimpleValueType();
10653 assert((EltVT == MVT::i1) && "Unexpected operands in ExtractBitFromMaskVector");
10654 assert((VecVT.getVectorNumElements() <= 16 || Subtarget->hasBWI()) &&
10655 "Unexpected vector type in ExtractBitFromMaskVector");
10657 // variable index can't be handled in mask registers,
10658 // extend vector to VR512
10659 if (!isa<ConstantSDNode>(Idx)) {
10660 MVT ExtVT = (VecVT == MVT::v8i1 ? MVT::v8i64 : MVT::v16i32);
10661 SDValue Ext = DAG.getNode(ISD::ZERO_EXTEND, dl, ExtVT, Vec);
10662 SDValue Elt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
10663 ExtVT.getVectorElementType(), Ext, Idx);
10664 return DAG.getNode(ISD::TRUNCATE, dl, EltVT, Elt);
10667 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
10668 const TargetRegisterClass* rc = getRegClassFor(VecVT);
10669 if (!Subtarget->hasDQI() && (VecVT.getVectorNumElements() <= 8))
10670 rc = getRegClassFor(MVT::v16i1);
10671 unsigned MaxSift = rc->getSize()*8 - 1;
10672 Vec = DAG.getNode(X86ISD::VSHLI, dl, VecVT, Vec,
10673 DAG.getConstant(MaxSift - IdxVal, dl, MVT::i8));
10674 Vec = DAG.getNode(X86ISD::VSRLI, dl, VecVT, Vec,
10675 DAG.getConstant(MaxSift, dl, MVT::i8));
10676 return DAG.getNode(X86ISD::VEXTRACT, dl, MVT::i1, Vec,
10677 DAG.getIntPtrConstant(0, dl));
10681 X86TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op,
10682 SelectionDAG &DAG) const {
10684 SDValue Vec = Op.getOperand(0);
10685 MVT VecVT = Vec.getSimpleValueType();
10686 SDValue Idx = Op.getOperand(1);
10688 if (Op.getSimpleValueType() == MVT::i1)
10689 return ExtractBitFromMaskVector(Op, DAG);
10691 if (!isa<ConstantSDNode>(Idx)) {
10692 if (VecVT.is512BitVector() ||
10693 (VecVT.is256BitVector() && Subtarget->hasInt256() &&
10694 VecVT.getVectorElementType().getSizeInBits() == 32)) {
10697 MVT::getIntegerVT(VecVT.getVectorElementType().getSizeInBits());
10698 MVT MaskVT = MVT::getVectorVT(MaskEltVT, VecVT.getSizeInBits() /
10699 MaskEltVT.getSizeInBits());
10701 Idx = DAG.getZExtOrTrunc(Idx, dl, MaskEltVT);
10702 SDValue Mask = DAG.getNode(X86ISD::VINSERT, dl, MaskVT,
10703 getZeroVector(MaskVT, Subtarget, DAG, dl),
10704 Idx, DAG.getConstant(0, dl, getPointerTy()));
10705 SDValue Perm = DAG.getNode(X86ISD::VPERMV, dl, VecVT, Mask, Vec);
10706 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, Op.getValueType(),
10707 Perm, DAG.getConstant(0, dl, getPointerTy()));
10712 // If this is a 256-bit vector result, first extract the 128-bit vector and
10713 // then extract the element from the 128-bit vector.
10714 if (VecVT.is256BitVector() || VecVT.is512BitVector()) {
10716 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
10717 // Get the 128-bit vector.
10718 Vec = Extract128BitVector(Vec, IdxVal, DAG, dl);
10719 MVT EltVT = VecVT.getVectorElementType();
10721 unsigned ElemsPerChunk = 128 / EltVT.getSizeInBits();
10723 //if (IdxVal >= NumElems/2)
10724 // IdxVal -= NumElems/2;
10725 IdxVal -= (IdxVal/ElemsPerChunk)*ElemsPerChunk;
10726 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, Op.getValueType(), Vec,
10727 DAG.getConstant(IdxVal, dl, MVT::i32));
10730 assert(VecVT.is128BitVector() && "Unexpected vector length");
10732 if (Subtarget->hasSSE41()) {
10733 SDValue Res = LowerEXTRACT_VECTOR_ELT_SSE4(Op, DAG);
10738 MVT VT = Op.getSimpleValueType();
10739 // TODO: handle v16i8.
10740 if (VT.getSizeInBits() == 16) {
10741 SDValue Vec = Op.getOperand(0);
10742 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
10744 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
10745 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
10746 DAG.getBitcast(MVT::v4i32, Vec),
10747 Op.getOperand(1)));
10748 // Transform it so it match pextrw which produces a 32-bit result.
10749 MVT EltVT = MVT::i32;
10750 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, EltVT,
10751 Op.getOperand(0), Op.getOperand(1));
10752 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, EltVT, Extract,
10753 DAG.getValueType(VT));
10754 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
10757 if (VT.getSizeInBits() == 32) {
10758 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
10762 // SHUFPS the element to the lowest double word, then movss.
10763 int Mask[4] = { static_cast<int>(Idx), -1, -1, -1 };
10764 MVT VVT = Op.getOperand(0).getSimpleValueType();
10765 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
10766 DAG.getUNDEF(VVT), Mask);
10767 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
10768 DAG.getIntPtrConstant(0, dl));
10771 if (VT.getSizeInBits() == 64) {
10772 // FIXME: .td only matches this for <2 x f64>, not <2 x i64> on 32b
10773 // FIXME: seems like this should be unnecessary if mov{h,l}pd were taught
10774 // to match extract_elt for f64.
10775 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
10779 // UNPCKHPD the element to the lowest double word, then movsd.
10780 // Note if the lower 64 bits of the result of the UNPCKHPD is then stored
10781 // to a f64mem, the whole operation is folded into a single MOVHPDmr.
10782 int Mask[2] = { 1, -1 };
10783 MVT VVT = Op.getOperand(0).getSimpleValueType();
10784 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
10785 DAG.getUNDEF(VVT), Mask);
10786 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
10787 DAG.getIntPtrConstant(0, dl));
10793 /// Insert one bit to mask vector, like v16i1 or v8i1.
10794 /// AVX-512 feature.
10796 X86TargetLowering::InsertBitToMaskVector(SDValue Op, SelectionDAG &DAG) const {
10798 SDValue Vec = Op.getOperand(0);
10799 SDValue Elt = Op.getOperand(1);
10800 SDValue Idx = Op.getOperand(2);
10801 MVT VecVT = Vec.getSimpleValueType();
10803 if (!isa<ConstantSDNode>(Idx)) {
10804 // Non constant index. Extend source and destination,
10805 // insert element and then truncate the result.
10806 MVT ExtVecVT = (VecVT == MVT::v8i1 ? MVT::v8i64 : MVT::v16i32);
10807 MVT ExtEltVT = (VecVT == MVT::v8i1 ? MVT::i64 : MVT::i32);
10808 SDValue ExtOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, ExtVecVT,
10809 DAG.getNode(ISD::ZERO_EXTEND, dl, ExtVecVT, Vec),
10810 DAG.getNode(ISD::ZERO_EXTEND, dl, ExtEltVT, Elt), Idx);
10811 return DAG.getNode(ISD::TRUNCATE, dl, VecVT, ExtOp);
10814 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
10815 SDValue EltInVec = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Elt);
10817 EltInVec = DAG.getNode(X86ISD::VSHLI, dl, VecVT, EltInVec,
10818 DAG.getConstant(IdxVal, dl, MVT::i8));
10819 if (Vec.getOpcode() == ISD::UNDEF)
10821 return DAG.getNode(ISD::OR, dl, VecVT, Vec, EltInVec);
10824 SDValue X86TargetLowering::LowerINSERT_VECTOR_ELT(SDValue Op,
10825 SelectionDAG &DAG) const {
10826 MVT VT = Op.getSimpleValueType();
10827 MVT EltVT = VT.getVectorElementType();
10829 if (EltVT == MVT::i1)
10830 return InsertBitToMaskVector(Op, DAG);
10833 SDValue N0 = Op.getOperand(0);
10834 SDValue N1 = Op.getOperand(1);
10835 SDValue N2 = Op.getOperand(2);
10836 if (!isa<ConstantSDNode>(N2))
10838 auto *N2C = cast<ConstantSDNode>(N2);
10839 unsigned IdxVal = N2C->getZExtValue();
10841 // If the vector is wider than 128 bits, extract the 128-bit subvector, insert
10842 // into that, and then insert the subvector back into the result.
10843 if (VT.is256BitVector() || VT.is512BitVector()) {
10844 // With a 256-bit vector, we can insert into the zero element efficiently
10845 // using a blend if we have AVX or AVX2 and the right data type.
10846 if (VT.is256BitVector() && IdxVal == 0) {
10847 // TODO: It is worthwhile to cast integer to floating point and back
10848 // and incur a domain crossing penalty if that's what we'll end up
10849 // doing anyway after extracting to a 128-bit vector.
10850 if ((Subtarget->hasAVX() && (EltVT == MVT::f64 || EltVT == MVT::f32)) ||
10851 (Subtarget->hasAVX2() && EltVT == MVT::i32)) {
10852 SDValue N1Vec = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, N1);
10853 N2 = DAG.getIntPtrConstant(1, dl);
10854 return DAG.getNode(X86ISD::BLENDI, dl, VT, N0, N1Vec, N2);
10858 // Get the desired 128-bit vector chunk.
10859 SDValue V = Extract128BitVector(N0, IdxVal, DAG, dl);
10861 // Insert the element into the desired chunk.
10862 unsigned NumEltsIn128 = 128 / EltVT.getSizeInBits();
10863 unsigned IdxIn128 = IdxVal - (IdxVal / NumEltsIn128) * NumEltsIn128;
10865 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, V.getValueType(), V, N1,
10866 DAG.getConstant(IdxIn128, dl, MVT::i32));
10868 // Insert the changed part back into the bigger vector
10869 return Insert128BitVector(N0, V, IdxVal, DAG, dl);
10871 assert(VT.is128BitVector() && "Only 128-bit vector types should be left!");
10873 if (Subtarget->hasSSE41()) {
10874 if (EltVT.getSizeInBits() == 8 || EltVT.getSizeInBits() == 16) {
10876 if (VT == MVT::v8i16) {
10877 Opc = X86ISD::PINSRW;
10879 assert(VT == MVT::v16i8);
10880 Opc = X86ISD::PINSRB;
10883 // Transform it so it match pinsr{b,w} which expects a GR32 as its second
10885 if (N1.getValueType() != MVT::i32)
10886 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
10887 if (N2.getValueType() != MVT::i32)
10888 N2 = DAG.getIntPtrConstant(IdxVal, dl);
10889 return DAG.getNode(Opc, dl, VT, N0, N1, N2);
10892 if (EltVT == MVT::f32) {
10893 // Bits [7:6] of the constant are the source select. This will always be
10894 // zero here. The DAG Combiner may combine an extract_elt index into
10895 // these bits. For example (insert (extract, 3), 2) could be matched by
10896 // putting the '3' into bits [7:6] of X86ISD::INSERTPS.
10897 // Bits [5:4] of the constant are the destination select. This is the
10898 // value of the incoming immediate.
10899 // Bits [3:0] of the constant are the zero mask. The DAG Combiner may
10900 // combine either bitwise AND or insert of float 0.0 to set these bits.
10902 const Function *F = DAG.getMachineFunction().getFunction();
10903 bool MinSize = F->hasFnAttribute(Attribute::MinSize);
10904 if (IdxVal == 0 && (!MinSize || !MayFoldLoad(N1))) {
10905 // If this is an insertion of 32-bits into the low 32-bits of
10906 // a vector, we prefer to generate a blend with immediate rather
10907 // than an insertps. Blends are simpler operations in hardware and so
10908 // will always have equal or better performance than insertps.
10909 // But if optimizing for size and there's a load folding opportunity,
10910 // generate insertps because blendps does not have a 32-bit memory
10912 N2 = DAG.getIntPtrConstant(1, dl);
10913 N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4f32, N1);
10914 return DAG.getNode(X86ISD::BLENDI, dl, VT, N0, N1, N2);
10916 N2 = DAG.getIntPtrConstant(IdxVal << 4, dl);
10917 // Create this as a scalar to vector..
10918 N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4f32, N1);
10919 return DAG.getNode(X86ISD::INSERTPS, dl, VT, N0, N1, N2);
10922 if (EltVT == MVT::i32 || EltVT == MVT::i64) {
10923 // PINSR* works with constant index.
10928 if (EltVT == MVT::i8)
10931 if (EltVT.getSizeInBits() == 16) {
10932 // Transform it so it match pinsrw which expects a 16-bit value in a GR32
10933 // as its second argument.
10934 if (N1.getValueType() != MVT::i32)
10935 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
10936 if (N2.getValueType() != MVT::i32)
10937 N2 = DAG.getIntPtrConstant(IdxVal, dl);
10938 return DAG.getNode(X86ISD::PINSRW, dl, VT, N0, N1, N2);
10943 static SDValue LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) {
10945 MVT OpVT = Op.getSimpleValueType();
10947 // If this is a 256-bit vector result, first insert into a 128-bit
10948 // vector and then insert into the 256-bit vector.
10949 if (!OpVT.is128BitVector()) {
10950 // Insert into a 128-bit vector.
10951 unsigned SizeFactor = OpVT.getSizeInBits()/128;
10952 MVT VT128 = MVT::getVectorVT(OpVT.getVectorElementType(),
10953 OpVT.getVectorNumElements() / SizeFactor);
10955 Op = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT128, Op.getOperand(0));
10957 // Insert the 128-bit vector.
10958 return Insert128BitVector(DAG.getUNDEF(OpVT), Op, 0, DAG, dl);
10961 if (OpVT == MVT::v1i64 &&
10962 Op.getOperand(0).getValueType() == MVT::i64)
10963 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v1i64, Op.getOperand(0));
10965 SDValue AnyExt = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, Op.getOperand(0));
10966 assert(OpVT.is128BitVector() && "Expected an SSE type!");
10967 return DAG.getBitcast(
10968 OpVT, DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, AnyExt));
10971 // Lower a node with an EXTRACT_SUBVECTOR opcode. This may result in
10972 // a simple subregister reference or explicit instructions to grab
10973 // upper bits of a vector.
10974 static SDValue LowerEXTRACT_SUBVECTOR(SDValue Op, const X86Subtarget *Subtarget,
10975 SelectionDAG &DAG) {
10977 SDValue In = Op.getOperand(0);
10978 SDValue Idx = Op.getOperand(1);
10979 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
10980 MVT ResVT = Op.getSimpleValueType();
10981 MVT InVT = In.getSimpleValueType();
10983 if (Subtarget->hasFp256()) {
10984 if (ResVT.is128BitVector() &&
10985 (InVT.is256BitVector() || InVT.is512BitVector()) &&
10986 isa<ConstantSDNode>(Idx)) {
10987 return Extract128BitVector(In, IdxVal, DAG, dl);
10989 if (ResVT.is256BitVector() && InVT.is512BitVector() &&
10990 isa<ConstantSDNode>(Idx)) {
10991 return Extract256BitVector(In, IdxVal, DAG, dl);
10997 // Lower a node with an INSERT_SUBVECTOR opcode. This may result in a
10998 // simple superregister reference or explicit instructions to insert
10999 // the upper bits of a vector.
11000 static SDValue LowerINSERT_SUBVECTOR(SDValue Op, const X86Subtarget *Subtarget,
11001 SelectionDAG &DAG) {
11002 if (!Subtarget->hasAVX())
11006 SDValue Vec = Op.getOperand(0);
11007 SDValue SubVec = Op.getOperand(1);
11008 SDValue Idx = Op.getOperand(2);
11010 if (!isa<ConstantSDNode>(Idx))
11013 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
11014 MVT OpVT = Op.getSimpleValueType();
11015 MVT SubVecVT = SubVec.getSimpleValueType();
11017 // Fold two 16-byte subvector loads into one 32-byte load:
11018 // (insert_subvector (insert_subvector undef, (load addr), 0),
11019 // (load addr + 16), Elts/2)
11021 if ((IdxVal == OpVT.getVectorNumElements() / 2) &&
11022 Vec.getOpcode() == ISD::INSERT_SUBVECTOR &&
11023 OpVT.is256BitVector() && SubVecVT.is128BitVector() &&
11024 !Subtarget->isUnalignedMem32Slow()) {
11025 SDValue SubVec2 = Vec.getOperand(1);
11026 if (auto *Idx2 = dyn_cast<ConstantSDNode>(Vec.getOperand(2))) {
11027 if (Idx2->getZExtValue() == 0) {
11028 SDValue Ops[] = { SubVec2, SubVec };
11029 SDValue LD = EltsFromConsecutiveLoads(OpVT, Ops, dl, DAG, false);
11036 if ((OpVT.is256BitVector() || OpVT.is512BitVector()) &&
11037 SubVecVT.is128BitVector())
11038 return Insert128BitVector(Vec, SubVec, IdxVal, DAG, dl);
11040 if (OpVT.is512BitVector() && SubVecVT.is256BitVector())
11041 return Insert256BitVector(Vec, SubVec, IdxVal, DAG, dl);
11043 if (OpVT.getVectorElementType() == MVT::i1) {
11044 if (IdxVal == 0 && Vec.getOpcode() == ISD::UNDEF) // the operation is legal
11046 SDValue ZeroIdx = DAG.getIntPtrConstant(0, dl);
11047 SDValue Undef = DAG.getUNDEF(OpVT);
11048 unsigned NumElems = OpVT.getVectorNumElements();
11049 SDValue ShiftBits = DAG.getConstant(NumElems/2, dl, MVT::i8);
11051 if (IdxVal == OpVT.getVectorNumElements() / 2) {
11052 // Zero upper bits of the Vec
11053 Vec = DAG.getNode(X86ISD::VSHLI, dl, OpVT, Vec, ShiftBits);
11054 Vec = DAG.getNode(X86ISD::VSRLI, dl, OpVT, Vec, ShiftBits);
11056 SDValue Vec2 = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, OpVT, Undef,
11058 Vec2 = DAG.getNode(X86ISD::VSHLI, dl, OpVT, Vec2, ShiftBits);
11059 return DAG.getNode(ISD::OR, dl, OpVT, Vec, Vec2);
11062 SDValue Vec2 = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, OpVT, Undef,
11064 // Zero upper bits of the Vec2
11065 Vec2 = DAG.getNode(X86ISD::VSHLI, dl, OpVT, Vec2, ShiftBits);
11066 Vec2 = DAG.getNode(X86ISD::VSRLI, dl, OpVT, Vec2, ShiftBits);
11067 // Zero lower bits of the Vec
11068 Vec = DAG.getNode(X86ISD::VSRLI, dl, OpVT, Vec, ShiftBits);
11069 Vec = DAG.getNode(X86ISD::VSHLI, dl, OpVT, Vec, ShiftBits);
11070 // Merge them together
11071 return DAG.getNode(ISD::OR, dl, OpVT, Vec, Vec2);
11077 // ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as
11078 // their target countpart wrapped in the X86ISD::Wrapper node. Suppose N is
11079 // one of the above mentioned nodes. It has to be wrapped because otherwise
11080 // Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only
11081 // be used to form addressing mode. These wrapped nodes will be selected
11084 X86TargetLowering::LowerConstantPool(SDValue Op, SelectionDAG &DAG) const {
11085 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
11087 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
11088 // global base reg.
11089 unsigned char OpFlag = 0;
11090 unsigned WrapperKind = X86ISD::Wrapper;
11091 CodeModel::Model M = DAG.getTarget().getCodeModel();
11093 if (Subtarget->isPICStyleRIPRel() &&
11094 (M == CodeModel::Small || M == CodeModel::Kernel))
11095 WrapperKind = X86ISD::WrapperRIP;
11096 else if (Subtarget->isPICStyleGOT())
11097 OpFlag = X86II::MO_GOTOFF;
11098 else if (Subtarget->isPICStyleStubPIC())
11099 OpFlag = X86II::MO_PIC_BASE_OFFSET;
11101 SDValue Result = DAG.getTargetConstantPool(CP->getConstVal(), getPointerTy(),
11102 CP->getAlignment(),
11103 CP->getOffset(), OpFlag);
11105 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
11106 // With PIC, the address is actually $g + Offset.
11108 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
11109 DAG.getNode(X86ISD::GlobalBaseReg,
11110 SDLoc(), getPointerTy()),
11117 SDValue X86TargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) const {
11118 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
11120 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
11121 // global base reg.
11122 unsigned char OpFlag = 0;
11123 unsigned WrapperKind = X86ISD::Wrapper;
11124 CodeModel::Model M = DAG.getTarget().getCodeModel();
11126 if (Subtarget->isPICStyleRIPRel() &&
11127 (M == CodeModel::Small || M == CodeModel::Kernel))
11128 WrapperKind = X86ISD::WrapperRIP;
11129 else if (Subtarget->isPICStyleGOT())
11130 OpFlag = X86II::MO_GOTOFF;
11131 else if (Subtarget->isPICStyleStubPIC())
11132 OpFlag = X86II::MO_PIC_BASE_OFFSET;
11134 SDValue Result = DAG.getTargetJumpTable(JT->getIndex(), getPointerTy(),
11137 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
11139 // With PIC, the address is actually $g + Offset.
11141 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
11142 DAG.getNode(X86ISD::GlobalBaseReg,
11143 SDLoc(), getPointerTy()),
11150 X86TargetLowering::LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) const {
11151 const char *Sym = cast<ExternalSymbolSDNode>(Op)->getSymbol();
11153 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
11154 // global base reg.
11155 unsigned char OpFlag = 0;
11156 unsigned WrapperKind = X86ISD::Wrapper;
11157 CodeModel::Model M = DAG.getTarget().getCodeModel();
11159 if (Subtarget->isPICStyleRIPRel() &&
11160 (M == CodeModel::Small || M == CodeModel::Kernel)) {
11161 if (Subtarget->isTargetDarwin() || Subtarget->isTargetELF())
11162 OpFlag = X86II::MO_GOTPCREL;
11163 WrapperKind = X86ISD::WrapperRIP;
11164 } else if (Subtarget->isPICStyleGOT()) {
11165 OpFlag = X86II::MO_GOT;
11166 } else if (Subtarget->isPICStyleStubPIC()) {
11167 OpFlag = X86II::MO_DARWIN_NONLAZY_PIC_BASE;
11168 } else if (Subtarget->isPICStyleStubNoDynamic()) {
11169 OpFlag = X86II::MO_DARWIN_NONLAZY;
11172 SDValue Result = DAG.getTargetExternalSymbol(Sym, getPointerTy(), OpFlag);
11175 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
11177 // With PIC, the address is actually $g + Offset.
11178 if (DAG.getTarget().getRelocationModel() == Reloc::PIC_ &&
11179 !Subtarget->is64Bit()) {
11180 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
11181 DAG.getNode(X86ISD::GlobalBaseReg,
11182 SDLoc(), getPointerTy()),
11186 // For symbols that require a load from a stub to get the address, emit the
11188 if (isGlobalStubReference(OpFlag))
11189 Result = DAG.getLoad(getPointerTy(), DL, DAG.getEntryNode(), Result,
11190 MachinePointerInfo::getGOT(), false, false, false, 0);
11196 X86TargetLowering::LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const {
11197 // Create the TargetBlockAddressAddress node.
11198 unsigned char OpFlags =
11199 Subtarget->ClassifyBlockAddressReference();
11200 CodeModel::Model M = DAG.getTarget().getCodeModel();
11201 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
11202 int64_t Offset = cast<BlockAddressSDNode>(Op)->getOffset();
11204 SDValue Result = DAG.getTargetBlockAddress(BA, getPointerTy(), Offset,
11207 if (Subtarget->isPICStyleRIPRel() &&
11208 (M == CodeModel::Small || M == CodeModel::Kernel))
11209 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
11211 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
11213 // With PIC, the address is actually $g + Offset.
11214 if (isGlobalRelativeToPICBase(OpFlags)) {
11215 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
11216 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
11224 X86TargetLowering::LowerGlobalAddress(const GlobalValue *GV, SDLoc dl,
11225 int64_t Offset, SelectionDAG &DAG) const {
11226 // Create the TargetGlobalAddress node, folding in the constant
11227 // offset if it is legal.
11228 unsigned char OpFlags =
11229 Subtarget->ClassifyGlobalReference(GV, DAG.getTarget());
11230 CodeModel::Model M = DAG.getTarget().getCodeModel();
11232 if (OpFlags == X86II::MO_NO_FLAG &&
11233 X86::isOffsetSuitableForCodeModel(Offset, M)) {
11234 // A direct static reference to a global.
11235 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), Offset);
11238 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), 0, OpFlags);
11241 if (Subtarget->isPICStyleRIPRel() &&
11242 (M == CodeModel::Small || M == CodeModel::Kernel))
11243 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
11245 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
11247 // With PIC, the address is actually $g + Offset.
11248 if (isGlobalRelativeToPICBase(OpFlags)) {
11249 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
11250 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
11254 // For globals that require a load from a stub to get the address, emit the
11256 if (isGlobalStubReference(OpFlags))
11257 Result = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Result,
11258 MachinePointerInfo::getGOT(), false, false, false, 0);
11260 // If there was a non-zero offset that we didn't fold, create an explicit
11261 // addition for it.
11263 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(), Result,
11264 DAG.getConstant(Offset, dl, getPointerTy()));
11270 X86TargetLowering::LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const {
11271 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
11272 int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset();
11273 return LowerGlobalAddress(GV, SDLoc(Op), Offset, DAG);
11277 GetTLSADDR(SelectionDAG &DAG, SDValue Chain, GlobalAddressSDNode *GA,
11278 SDValue *InFlag, const EVT PtrVT, unsigned ReturnReg,
11279 unsigned char OperandFlags, bool LocalDynamic = false) {
11280 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
11281 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
11283 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
11284 GA->getValueType(0),
11288 X86ISD::NodeType CallType = LocalDynamic ? X86ISD::TLSBASEADDR
11292 SDValue Ops[] = { Chain, TGA, *InFlag };
11293 Chain = DAG.getNode(CallType, dl, NodeTys, Ops);
11295 SDValue Ops[] = { Chain, TGA };
11296 Chain = DAG.getNode(CallType, dl, NodeTys, Ops);
11299 // TLSADDR will be codegen'ed as call. Inform MFI that function has calls.
11300 MFI->setAdjustsStack(true);
11301 MFI->setHasCalls(true);
11303 SDValue Flag = Chain.getValue(1);
11304 return DAG.getCopyFromReg(Chain, dl, ReturnReg, PtrVT, Flag);
11307 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 32 bit
11309 LowerToTLSGeneralDynamicModel32(GlobalAddressSDNode *GA, SelectionDAG &DAG,
11312 SDLoc dl(GA); // ? function entry point might be better
11313 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
11314 DAG.getNode(X86ISD::GlobalBaseReg,
11315 SDLoc(), PtrVT), InFlag);
11316 InFlag = Chain.getValue(1);
11318 return GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX, X86II::MO_TLSGD);
11321 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 64 bit
11323 LowerToTLSGeneralDynamicModel64(GlobalAddressSDNode *GA, SelectionDAG &DAG,
11325 return GetTLSADDR(DAG, DAG.getEntryNode(), GA, nullptr, PtrVT,
11326 X86::RAX, X86II::MO_TLSGD);
11329 static SDValue LowerToTLSLocalDynamicModel(GlobalAddressSDNode *GA,
11335 // Get the start address of the TLS block for this module.
11336 X86MachineFunctionInfo* MFI = DAG.getMachineFunction()
11337 .getInfo<X86MachineFunctionInfo>();
11338 MFI->incNumLocalDynamicTLSAccesses();
11342 Base = GetTLSADDR(DAG, DAG.getEntryNode(), GA, nullptr, PtrVT, X86::RAX,
11343 X86II::MO_TLSLD, /*LocalDynamic=*/true);
11346 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
11347 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT), InFlag);
11348 InFlag = Chain.getValue(1);
11349 Base = GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX,
11350 X86II::MO_TLSLDM, /*LocalDynamic=*/true);
11353 // Note: the CleanupLocalDynamicTLSPass will remove redundant computations
11357 unsigned char OperandFlags = X86II::MO_DTPOFF;
11358 unsigned WrapperKind = X86ISD::Wrapper;
11359 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
11360 GA->getValueType(0),
11361 GA->getOffset(), OperandFlags);
11362 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
11364 // Add x@dtpoff with the base.
11365 return DAG.getNode(ISD::ADD, dl, PtrVT, Offset, Base);
11368 // Lower ISD::GlobalTLSAddress using the "initial exec" or "local exec" model.
11369 static SDValue LowerToTLSExecModel(GlobalAddressSDNode *GA, SelectionDAG &DAG,
11370 const EVT PtrVT, TLSModel::Model model,
11371 bool is64Bit, bool isPIC) {
11374 // Get the Thread Pointer, which is %gs:0 (32-bit) or %fs:0 (64-bit).
11375 Value *Ptr = Constant::getNullValue(Type::getInt8PtrTy(*DAG.getContext(),
11376 is64Bit ? 257 : 256));
11378 SDValue ThreadPointer =
11379 DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), DAG.getIntPtrConstant(0, dl),
11380 MachinePointerInfo(Ptr), false, false, false, 0);
11382 unsigned char OperandFlags = 0;
11383 // Most TLS accesses are not RIP relative, even on x86-64. One exception is
11385 unsigned WrapperKind = X86ISD::Wrapper;
11386 if (model == TLSModel::LocalExec) {
11387 OperandFlags = is64Bit ? X86II::MO_TPOFF : X86II::MO_NTPOFF;
11388 } else if (model == TLSModel::InitialExec) {
11390 OperandFlags = X86II::MO_GOTTPOFF;
11391 WrapperKind = X86ISD::WrapperRIP;
11393 OperandFlags = isPIC ? X86II::MO_GOTNTPOFF : X86II::MO_INDNTPOFF;
11396 llvm_unreachable("Unexpected model");
11399 // emit "addl x@ntpoff,%eax" (local exec)
11400 // or "addl x@indntpoff,%eax" (initial exec)
11401 // or "addl x@gotntpoff(%ebx) ,%eax" (initial exec, 32-bit pic)
11403 DAG.getTargetGlobalAddress(GA->getGlobal(), dl, GA->getValueType(0),
11404 GA->getOffset(), OperandFlags);
11405 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
11407 if (model == TLSModel::InitialExec) {
11408 if (isPIC && !is64Bit) {
11409 Offset = DAG.getNode(ISD::ADD, dl, PtrVT,
11410 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT),
11414 Offset = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Offset,
11415 MachinePointerInfo::getGOT(), false, false, false, 0);
11418 // The address of the thread local variable is the add of the thread
11419 // pointer with the offset of the variable.
11420 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset);
11424 X86TargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const {
11426 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
11427 const GlobalValue *GV = GA->getGlobal();
11429 if (Subtarget->isTargetELF()) {
11430 TLSModel::Model model = DAG.getTarget().getTLSModel(GV);
11432 case TLSModel::GeneralDynamic:
11433 if (Subtarget->is64Bit())
11434 return LowerToTLSGeneralDynamicModel64(GA, DAG, getPointerTy());
11435 return LowerToTLSGeneralDynamicModel32(GA, DAG, getPointerTy());
11436 case TLSModel::LocalDynamic:
11437 return LowerToTLSLocalDynamicModel(GA, DAG, getPointerTy(),
11438 Subtarget->is64Bit());
11439 case TLSModel::InitialExec:
11440 case TLSModel::LocalExec:
11441 return LowerToTLSExecModel(
11442 GA, DAG, getPointerTy(), model, Subtarget->is64Bit(),
11443 DAG.getTarget().getRelocationModel() == Reloc::PIC_);
11445 llvm_unreachable("Unknown TLS model.");
11448 if (Subtarget->isTargetDarwin()) {
11449 // Darwin only has one model of TLS. Lower to that.
11450 unsigned char OpFlag = 0;
11451 unsigned WrapperKind = Subtarget->isPICStyleRIPRel() ?
11452 X86ISD::WrapperRIP : X86ISD::Wrapper;
11454 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
11455 // global base reg.
11456 bool PIC32 = (DAG.getTarget().getRelocationModel() == Reloc::PIC_) &&
11457 !Subtarget->is64Bit();
11459 OpFlag = X86II::MO_TLVP_PIC_BASE;
11461 OpFlag = X86II::MO_TLVP;
11463 SDValue Result = DAG.getTargetGlobalAddress(GA->getGlobal(), DL,
11464 GA->getValueType(0),
11465 GA->getOffset(), OpFlag);
11466 SDValue Offset = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
11468 // With PIC32, the address is actually $g + Offset.
11470 Offset = DAG.getNode(ISD::ADD, DL, getPointerTy(),
11471 DAG.getNode(X86ISD::GlobalBaseReg,
11472 SDLoc(), getPointerTy()),
11475 // Lowering the machine isd will make sure everything is in the right
11477 SDValue Chain = DAG.getEntryNode();
11478 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
11479 SDValue Args[] = { Chain, Offset };
11480 Chain = DAG.getNode(X86ISD::TLSCALL, DL, NodeTys, Args);
11482 // TLSCALL will be codegen'ed as call. Inform MFI that function has calls.
11483 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
11484 MFI->setAdjustsStack(true);
11486 // And our return value (tls address) is in the standard call return value
11488 unsigned Reg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
11489 return DAG.getCopyFromReg(Chain, DL, Reg, getPointerTy(),
11490 Chain.getValue(1));
11493 if (Subtarget->isTargetKnownWindowsMSVC() ||
11494 Subtarget->isTargetWindowsGNU()) {
11495 // Just use the implicit TLS architecture
11496 // Need to generate someting similar to:
11497 // mov rdx, qword [gs:abs 58H]; Load pointer to ThreadLocalStorage
11499 // mov ecx, dword [rel _tls_index]: Load index (from C runtime)
11500 // mov rcx, qword [rdx+rcx*8]
11501 // mov eax, .tls$:tlsvar
11502 // [rax+rcx] contains the address
11503 // Windows 64bit: gs:0x58
11504 // Windows 32bit: fs:__tls_array
11507 SDValue Chain = DAG.getEntryNode();
11509 // Get the Thread Pointer, which is %fs:__tls_array (32-bit) or
11510 // %gs:0x58 (64-bit). On MinGW, __tls_array is not available, so directly
11511 // use its literal value of 0x2C.
11512 Value *Ptr = Constant::getNullValue(Subtarget->is64Bit()
11513 ? Type::getInt8PtrTy(*DAG.getContext(),
11515 : Type::getInt32PtrTy(*DAG.getContext(),
11519 Subtarget->is64Bit()
11520 ? DAG.getIntPtrConstant(0x58, dl)
11521 : (Subtarget->isTargetWindowsGNU()
11522 ? DAG.getIntPtrConstant(0x2C, dl)
11523 : DAG.getExternalSymbol("_tls_array", getPointerTy()));
11525 SDValue ThreadPointer =
11526 DAG.getLoad(getPointerTy(), dl, Chain, TlsArray,
11527 MachinePointerInfo(Ptr), false, false, false, 0);
11530 if (GV->getThreadLocalMode() == GlobalVariable::LocalExecTLSModel) {
11531 res = ThreadPointer;
11533 // Load the _tls_index variable
11534 SDValue IDX = DAG.getExternalSymbol("_tls_index", getPointerTy());
11535 if (Subtarget->is64Bit())
11536 IDX = DAG.getExtLoad(ISD::ZEXTLOAD, dl, getPointerTy(), Chain, IDX,
11537 MachinePointerInfo(), MVT::i32, false, false,
11540 IDX = DAG.getLoad(getPointerTy(), dl, Chain, IDX, MachinePointerInfo(),
11541 false, false, false, 0);
11543 SDValue Scale = DAG.getConstant(Log2_64_Ceil(TD->getPointerSize()), dl,
11545 IDX = DAG.getNode(ISD::SHL, dl, getPointerTy(), IDX, Scale);
11547 res = DAG.getNode(ISD::ADD, dl, getPointerTy(), ThreadPointer, IDX);
11550 res = DAG.getLoad(getPointerTy(), dl, Chain, res, MachinePointerInfo(),
11551 false, false, false, 0);
11553 // Get the offset of start of .tls section
11554 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
11555 GA->getValueType(0),
11556 GA->getOffset(), X86II::MO_SECREL);
11557 SDValue Offset = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), TGA);
11559 // The address of the thread local variable is the add of the thread
11560 // pointer with the offset of the variable.
11561 return DAG.getNode(ISD::ADD, dl, getPointerTy(), res, Offset);
11564 llvm_unreachable("TLS not implemented for this target.");
11567 /// LowerShiftParts - Lower SRA_PARTS and friends, which return two i32 values
11568 /// and take a 2 x i32 value to shift plus a shift amount.
11569 static SDValue LowerShiftParts(SDValue Op, SelectionDAG &DAG) {
11570 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
11571 MVT VT = Op.getSimpleValueType();
11572 unsigned VTBits = VT.getSizeInBits();
11574 bool isSRA = Op.getOpcode() == ISD::SRA_PARTS;
11575 SDValue ShOpLo = Op.getOperand(0);
11576 SDValue ShOpHi = Op.getOperand(1);
11577 SDValue ShAmt = Op.getOperand(2);
11578 // X86ISD::SHLD and X86ISD::SHRD have defined overflow behavior but the
11579 // generic ISD nodes haven't. Insert an AND to be safe, it's optimized away
11581 SDValue SafeShAmt = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt,
11582 DAG.getConstant(VTBits - 1, dl, MVT::i8));
11583 SDValue Tmp1 = isSRA ? DAG.getNode(ISD::SRA, dl, VT, ShOpHi,
11584 DAG.getConstant(VTBits - 1, dl, MVT::i8))
11585 : DAG.getConstant(0, dl, VT);
11587 SDValue Tmp2, Tmp3;
11588 if (Op.getOpcode() == ISD::SHL_PARTS) {
11589 Tmp2 = DAG.getNode(X86ISD::SHLD, dl, VT, ShOpHi, ShOpLo, ShAmt);
11590 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, SafeShAmt);
11592 Tmp2 = DAG.getNode(X86ISD::SHRD, dl, VT, ShOpLo, ShOpHi, ShAmt);
11593 Tmp3 = DAG.getNode(isSRA ? ISD::SRA : ISD::SRL, dl, VT, ShOpHi, SafeShAmt);
11596 // If the shift amount is larger or equal than the width of a part we can't
11597 // rely on the results of shld/shrd. Insert a test and select the appropriate
11598 // values for large shift amounts.
11599 SDValue AndNode = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt,
11600 DAG.getConstant(VTBits, dl, MVT::i8));
11601 SDValue Cond = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
11602 AndNode, DAG.getConstant(0, dl, MVT::i8));
11605 SDValue CC = DAG.getConstant(X86::COND_NE, dl, MVT::i8);
11606 SDValue Ops0[4] = { Tmp2, Tmp3, CC, Cond };
11607 SDValue Ops1[4] = { Tmp3, Tmp1, CC, Cond };
11609 if (Op.getOpcode() == ISD::SHL_PARTS) {
11610 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0);
11611 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1);
11613 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0);
11614 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1);
11617 SDValue Ops[2] = { Lo, Hi };
11618 return DAG.getMergeValues(Ops, dl);
11621 SDValue X86TargetLowering::LowerSINT_TO_FP(SDValue Op,
11622 SelectionDAG &DAG) const {
11623 MVT SrcVT = Op.getOperand(0).getSimpleValueType();
11626 if (SrcVT.isVector()) {
11627 if (SrcVT.getVectorElementType() == MVT::i1) {
11628 MVT IntegerVT = MVT::getVectorVT(MVT::i32, SrcVT.getVectorNumElements());
11629 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(),
11630 DAG.getNode(ISD::SIGN_EXTEND, dl, IntegerVT,
11631 Op.getOperand(0)));
11636 assert(SrcVT <= MVT::i64 && SrcVT >= MVT::i16 &&
11637 "Unknown SINT_TO_FP to lower!");
11639 // These are really Legal; return the operand so the caller accepts it as
11641 if (SrcVT == MVT::i32 && isScalarFPTypeInSSEReg(Op.getValueType()))
11643 if (SrcVT == MVT::i64 && isScalarFPTypeInSSEReg(Op.getValueType()) &&
11644 Subtarget->is64Bit()) {
11648 unsigned Size = SrcVT.getSizeInBits()/8;
11649 MachineFunction &MF = DAG.getMachineFunction();
11650 int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size, false);
11651 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
11652 SDValue Chain = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
11654 MachinePointerInfo::getFixedStack(SSFI),
11656 return BuildFILD(Op, SrcVT, Chain, StackSlot, DAG);
11659 SDValue X86TargetLowering::BuildFILD(SDValue Op, EVT SrcVT, SDValue Chain,
11661 SelectionDAG &DAG) const {
11665 bool useSSE = isScalarFPTypeInSSEReg(Op.getValueType());
11667 Tys = DAG.getVTList(MVT::f64, MVT::Other, MVT::Glue);
11669 Tys = DAG.getVTList(Op.getValueType(), MVT::Other);
11671 unsigned ByteSize = SrcVT.getSizeInBits()/8;
11673 FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(StackSlot);
11674 MachineMemOperand *MMO;
11676 int SSFI = FI->getIndex();
11678 DAG.getMachineFunction()
11679 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
11680 MachineMemOperand::MOLoad, ByteSize, ByteSize);
11682 MMO = cast<LoadSDNode>(StackSlot)->getMemOperand();
11683 StackSlot = StackSlot.getOperand(1);
11685 SDValue Ops[] = { Chain, StackSlot, DAG.getValueType(SrcVT) };
11686 SDValue Result = DAG.getMemIntrinsicNode(useSSE ? X86ISD::FILD_FLAG :
11688 Tys, Ops, SrcVT, MMO);
11691 Chain = Result.getValue(1);
11692 SDValue InFlag = Result.getValue(2);
11694 // FIXME: Currently the FST is flagged to the FILD_FLAG. This
11695 // shouldn't be necessary except that RFP cannot be live across
11696 // multiple blocks. When stackifier is fixed, they can be uncoupled.
11697 MachineFunction &MF = DAG.getMachineFunction();
11698 unsigned SSFISize = Op.getValueType().getSizeInBits()/8;
11699 int SSFI = MF.getFrameInfo()->CreateStackObject(SSFISize, SSFISize, false);
11700 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
11701 Tys = DAG.getVTList(MVT::Other);
11703 Chain, Result, StackSlot, DAG.getValueType(Op.getValueType()), InFlag
11705 MachineMemOperand *MMO =
11706 DAG.getMachineFunction()
11707 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
11708 MachineMemOperand::MOStore, SSFISize, SSFISize);
11710 Chain = DAG.getMemIntrinsicNode(X86ISD::FST, DL, Tys,
11711 Ops, Op.getValueType(), MMO);
11712 Result = DAG.getLoad(Op.getValueType(), DL, Chain, StackSlot,
11713 MachinePointerInfo::getFixedStack(SSFI),
11714 false, false, false, 0);
11720 // LowerUINT_TO_FP_i64 - 64-bit unsigned integer to double expansion.
11721 SDValue X86TargetLowering::LowerUINT_TO_FP_i64(SDValue Op,
11722 SelectionDAG &DAG) const {
11723 // This algorithm is not obvious. Here it is what we're trying to output:
11726 punpckldq (c0), %xmm0 // c0: (uint4){ 0x43300000U, 0x45300000U, 0U, 0U }
11727 subpd (c1), %xmm0 // c1: (double2){ 0x1.0p52, 0x1.0p52 * 0x1.0p32 }
11729 haddpd %xmm0, %xmm0
11731 pshufd $0x4e, %xmm0, %xmm1
11737 LLVMContext *Context = DAG.getContext();
11739 // Build some magic constants.
11740 static const uint32_t CV0[] = { 0x43300000, 0x45300000, 0, 0 };
11741 Constant *C0 = ConstantDataVector::get(*Context, CV0);
11742 SDValue CPIdx0 = DAG.getConstantPool(C0, getPointerTy(), 16);
11744 SmallVector<Constant*,2> CV1;
11746 ConstantFP::get(*Context, APFloat(APFloat::IEEEdouble,
11747 APInt(64, 0x4330000000000000ULL))));
11749 ConstantFP::get(*Context, APFloat(APFloat::IEEEdouble,
11750 APInt(64, 0x4530000000000000ULL))));
11751 Constant *C1 = ConstantVector::get(CV1);
11752 SDValue CPIdx1 = DAG.getConstantPool(C1, getPointerTy(), 16);
11754 // Load the 64-bit value into an XMM register.
11755 SDValue XR1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
11757 SDValue CLod0 = DAG.getLoad(MVT::v4i32, dl, DAG.getEntryNode(), CPIdx0,
11758 MachinePointerInfo::getConstantPool(),
11759 false, false, false, 16);
11761 getUnpackl(DAG, dl, MVT::v4i32, DAG.getBitcast(MVT::v4i32, XR1), CLod0);
11763 SDValue CLod1 = DAG.getLoad(MVT::v2f64, dl, CLod0.getValue(1), CPIdx1,
11764 MachinePointerInfo::getConstantPool(),
11765 false, false, false, 16);
11766 SDValue XR2F = DAG.getBitcast(MVT::v2f64, Unpck1);
11767 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, XR2F, CLod1);
11770 if (Subtarget->hasSSE3()) {
11771 // FIXME: The 'haddpd' instruction may be slower than 'movhlps + addsd'.
11772 Result = DAG.getNode(X86ISD::FHADD, dl, MVT::v2f64, Sub, Sub);
11774 SDValue S2F = DAG.getBitcast(MVT::v4i32, Sub);
11775 SDValue Shuffle = getTargetShuffleNode(X86ISD::PSHUFD, dl, MVT::v4i32,
11777 Result = DAG.getNode(ISD::FADD, dl, MVT::v2f64,
11778 DAG.getBitcast(MVT::v2f64, Shuffle), Sub);
11781 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Result,
11782 DAG.getIntPtrConstant(0, dl));
11785 // LowerUINT_TO_FP_i32 - 32-bit unsigned integer to float expansion.
11786 SDValue X86TargetLowering::LowerUINT_TO_FP_i32(SDValue Op,
11787 SelectionDAG &DAG) const {
11789 // FP constant to bias correct the final result.
11790 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL), dl,
11793 // Load the 32-bit value into an XMM register.
11794 SDValue Load = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,
11797 // Zero out the upper parts of the register.
11798 Load = getShuffleVectorZeroOrUndef(Load, 0, true, Subtarget, DAG);
11800 Load = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
11801 DAG.getBitcast(MVT::v2f64, Load),
11802 DAG.getIntPtrConstant(0, dl));
11804 // Or the load with the bias.
11805 SDValue Or = DAG.getNode(
11806 ISD::OR, dl, MVT::v2i64,
11807 DAG.getBitcast(MVT::v2i64,
11808 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f64, Load)),
11809 DAG.getBitcast(MVT::v2i64,
11810 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f64, Bias)));
11812 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
11813 DAG.getBitcast(MVT::v2f64, Or), DAG.getIntPtrConstant(0, dl));
11815 // Subtract the bias.
11816 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Or, Bias);
11818 // Handle final rounding.
11819 EVT DestVT = Op.getValueType();
11821 if (DestVT.bitsLT(MVT::f64))
11822 return DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub,
11823 DAG.getIntPtrConstant(0, dl));
11824 if (DestVT.bitsGT(MVT::f64))
11825 return DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub);
11827 // Handle final rounding.
11831 static SDValue lowerUINT_TO_FP_vXi32(SDValue Op, SelectionDAG &DAG,
11832 const X86Subtarget &Subtarget) {
11833 // The algorithm is the following:
11834 // #ifdef __SSE4_1__
11835 // uint4 lo = _mm_blend_epi16( v, (uint4) 0x4b000000, 0xaa);
11836 // uint4 hi = _mm_blend_epi16( _mm_srli_epi32(v,16),
11837 // (uint4) 0x53000000, 0xaa);
11839 // uint4 lo = (v & (uint4) 0xffff) | (uint4) 0x4b000000;
11840 // uint4 hi = (v >> 16) | (uint4) 0x53000000;
11842 // float4 fhi = (float4) hi - (0x1.0p39f + 0x1.0p23f);
11843 // return (float4) lo + fhi;
11846 SDValue V = Op->getOperand(0);
11847 EVT VecIntVT = V.getValueType();
11848 bool Is128 = VecIntVT == MVT::v4i32;
11849 EVT VecFloatVT = Is128 ? MVT::v4f32 : MVT::v8f32;
11850 // If we convert to something else than the supported type, e.g., to v4f64,
11852 if (VecFloatVT != Op->getValueType(0))
11855 unsigned NumElts = VecIntVT.getVectorNumElements();
11856 assert((VecIntVT == MVT::v4i32 || VecIntVT == MVT::v8i32) &&
11857 "Unsupported custom type");
11858 assert(NumElts <= 8 && "The size of the constant array must be fixed");
11860 // In the #idef/#else code, we have in common:
11861 // - The vector of constants:
11867 // Create the splat vector for 0x4b000000.
11868 SDValue CstLow = DAG.getConstant(0x4b000000, DL, MVT::i32);
11869 SDValue CstLowArray[] = {CstLow, CstLow, CstLow, CstLow,
11870 CstLow, CstLow, CstLow, CstLow};
11871 SDValue VecCstLow = DAG.getNode(ISD::BUILD_VECTOR, DL, VecIntVT,
11872 makeArrayRef(&CstLowArray[0], NumElts));
11873 // Create the splat vector for 0x53000000.
11874 SDValue CstHigh = DAG.getConstant(0x53000000, DL, MVT::i32);
11875 SDValue CstHighArray[] = {CstHigh, CstHigh, CstHigh, CstHigh,
11876 CstHigh, CstHigh, CstHigh, CstHigh};
11877 SDValue VecCstHigh = DAG.getNode(ISD::BUILD_VECTOR, DL, VecIntVT,
11878 makeArrayRef(&CstHighArray[0], NumElts));
11880 // Create the right shift.
11881 SDValue CstShift = DAG.getConstant(16, DL, MVT::i32);
11882 SDValue CstShiftArray[] = {CstShift, CstShift, CstShift, CstShift,
11883 CstShift, CstShift, CstShift, CstShift};
11884 SDValue VecCstShift = DAG.getNode(ISD::BUILD_VECTOR, DL, VecIntVT,
11885 makeArrayRef(&CstShiftArray[0], NumElts));
11886 SDValue HighShift = DAG.getNode(ISD::SRL, DL, VecIntVT, V, VecCstShift);
11889 if (Subtarget.hasSSE41()) {
11890 EVT VecI16VT = Is128 ? MVT::v8i16 : MVT::v16i16;
11891 // uint4 lo = _mm_blend_epi16( v, (uint4) 0x4b000000, 0xaa);
11892 SDValue VecCstLowBitcast = DAG.getBitcast(VecI16VT, VecCstLow);
11893 SDValue VecBitcast = DAG.getBitcast(VecI16VT, V);
11894 // Low will be bitcasted right away, so do not bother bitcasting back to its
11896 Low = DAG.getNode(X86ISD::BLENDI, DL, VecI16VT, VecBitcast,
11897 VecCstLowBitcast, DAG.getConstant(0xaa, DL, MVT::i32));
11898 // uint4 hi = _mm_blend_epi16( _mm_srli_epi32(v,16),
11899 // (uint4) 0x53000000, 0xaa);
11900 SDValue VecCstHighBitcast = DAG.getBitcast(VecI16VT, VecCstHigh);
11901 SDValue VecShiftBitcast = DAG.getBitcast(VecI16VT, HighShift);
11902 // High will be bitcasted right away, so do not bother bitcasting back to
11903 // its original type.
11904 High = DAG.getNode(X86ISD::BLENDI, DL, VecI16VT, VecShiftBitcast,
11905 VecCstHighBitcast, DAG.getConstant(0xaa, DL, MVT::i32));
11907 SDValue CstMask = DAG.getConstant(0xffff, DL, MVT::i32);
11908 SDValue VecCstMask = DAG.getNode(ISD::BUILD_VECTOR, DL, VecIntVT, CstMask,
11909 CstMask, CstMask, CstMask);
11910 // uint4 lo = (v & (uint4) 0xffff) | (uint4) 0x4b000000;
11911 SDValue LowAnd = DAG.getNode(ISD::AND, DL, VecIntVT, V, VecCstMask);
11912 Low = DAG.getNode(ISD::OR, DL, VecIntVT, LowAnd, VecCstLow);
11914 // uint4 hi = (v >> 16) | (uint4) 0x53000000;
11915 High = DAG.getNode(ISD::OR, DL, VecIntVT, HighShift, VecCstHigh);
11918 // Create the vector constant for -(0x1.0p39f + 0x1.0p23f).
11919 SDValue CstFAdd = DAG.getConstantFP(
11920 APFloat(APFloat::IEEEsingle, APInt(32, 0xD3000080)), DL, MVT::f32);
11921 SDValue CstFAddArray[] = {CstFAdd, CstFAdd, CstFAdd, CstFAdd,
11922 CstFAdd, CstFAdd, CstFAdd, CstFAdd};
11923 SDValue VecCstFAdd = DAG.getNode(ISD::BUILD_VECTOR, DL, VecFloatVT,
11924 makeArrayRef(&CstFAddArray[0], NumElts));
11926 // float4 fhi = (float4) hi - (0x1.0p39f + 0x1.0p23f);
11927 SDValue HighBitcast = DAG.getBitcast(VecFloatVT, High);
11929 DAG.getNode(ISD::FADD, DL, VecFloatVT, HighBitcast, VecCstFAdd);
11930 // return (float4) lo + fhi;
11931 SDValue LowBitcast = DAG.getBitcast(VecFloatVT, Low);
11932 return DAG.getNode(ISD::FADD, DL, VecFloatVT, LowBitcast, FHigh);
11935 SDValue X86TargetLowering::lowerUINT_TO_FP_vec(SDValue Op,
11936 SelectionDAG &DAG) const {
11937 SDValue N0 = Op.getOperand(0);
11938 MVT SVT = N0.getSimpleValueType();
11941 switch (SVT.SimpleTy) {
11943 llvm_unreachable("Custom UINT_TO_FP is not supported!");
11948 MVT NVT = MVT::getVectorVT(MVT::i32, SVT.getVectorNumElements());
11949 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(),
11950 DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, N0));
11954 return lowerUINT_TO_FP_vXi32(Op, DAG, *Subtarget);
11957 if (Subtarget->hasAVX512())
11958 return DAG.getNode(ISD::UINT_TO_FP, dl, Op.getValueType(),
11959 DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v16i32, N0));
11961 llvm_unreachable(nullptr);
11964 SDValue X86TargetLowering::LowerUINT_TO_FP(SDValue Op,
11965 SelectionDAG &DAG) const {
11966 SDValue N0 = Op.getOperand(0);
11969 if (Op.getValueType().isVector())
11970 return lowerUINT_TO_FP_vec(Op, DAG);
11972 // Since UINT_TO_FP is legal (it's marked custom), dag combiner won't
11973 // optimize it to a SINT_TO_FP when the sign bit is known zero. Perform
11974 // the optimization here.
11975 if (DAG.SignBitIsZero(N0))
11976 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(), N0);
11978 MVT SrcVT = N0.getSimpleValueType();
11979 MVT DstVT = Op.getSimpleValueType();
11980 if (SrcVT == MVT::i64 && DstVT == MVT::f64 && X86ScalarSSEf64)
11981 return LowerUINT_TO_FP_i64(Op, DAG);
11982 if (SrcVT == MVT::i32 && X86ScalarSSEf64)
11983 return LowerUINT_TO_FP_i32(Op, DAG);
11984 if (Subtarget->is64Bit() && SrcVT == MVT::i64 && DstVT == MVT::f32)
11987 // Make a 64-bit buffer, and use it to build an FILD.
11988 SDValue StackSlot = DAG.CreateStackTemporary(MVT::i64);
11989 if (SrcVT == MVT::i32) {
11990 SDValue WordOff = DAG.getConstant(4, dl, getPointerTy());
11991 SDValue OffsetSlot = DAG.getNode(ISD::ADD, dl,
11992 getPointerTy(), StackSlot, WordOff);
11993 SDValue Store1 = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
11994 StackSlot, MachinePointerInfo(),
11996 SDValue Store2 = DAG.getStore(Store1, dl, DAG.getConstant(0, dl, MVT::i32),
11997 OffsetSlot, MachinePointerInfo(),
11999 SDValue Fild = BuildFILD(Op, MVT::i64, Store2, StackSlot, DAG);
12003 assert(SrcVT == MVT::i64 && "Unexpected type in UINT_TO_FP");
12004 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
12005 StackSlot, MachinePointerInfo(),
12007 // For i64 source, we need to add the appropriate power of 2 if the input
12008 // was negative. This is the same as the optimization in
12009 // DAGTypeLegalizer::ExpandIntOp_UNIT_TO_FP, and for it to be safe here,
12010 // we must be careful to do the computation in x87 extended precision, not
12011 // in SSE. (The generic code can't know it's OK to do this, or how to.)
12012 int SSFI = cast<FrameIndexSDNode>(StackSlot)->getIndex();
12013 MachineMemOperand *MMO =
12014 DAG.getMachineFunction()
12015 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
12016 MachineMemOperand::MOLoad, 8, 8);
12018 SDVTList Tys = DAG.getVTList(MVT::f80, MVT::Other);
12019 SDValue Ops[] = { Store, StackSlot, DAG.getValueType(MVT::i64) };
12020 SDValue Fild = DAG.getMemIntrinsicNode(X86ISD::FILD, dl, Tys, Ops,
12023 APInt FF(32, 0x5F800000ULL);
12025 // Check whether the sign bit is set.
12026 SDValue SignSet = DAG.getSetCC(dl,
12027 getSetCCResultType(*DAG.getContext(), MVT::i64),
12029 DAG.getConstant(0, dl, MVT::i64), ISD::SETLT);
12031 // Build a 64 bit pair (0, FF) in the constant pool, with FF in the lo bits.
12032 SDValue FudgePtr = DAG.getConstantPool(
12033 ConstantInt::get(*DAG.getContext(), FF.zext(64)),
12036 // Get a pointer to FF if the sign bit was set, or to 0 otherwise.
12037 SDValue Zero = DAG.getIntPtrConstant(0, dl);
12038 SDValue Four = DAG.getIntPtrConstant(4, dl);
12039 SDValue Offset = DAG.getNode(ISD::SELECT, dl, Zero.getValueType(), SignSet,
12041 FudgePtr = DAG.getNode(ISD::ADD, dl, getPointerTy(), FudgePtr, Offset);
12043 // Load the value out, extending it from f32 to f80.
12044 // FIXME: Avoid the extend by constructing the right constant pool?
12045 SDValue Fudge = DAG.getExtLoad(ISD::EXTLOAD, dl, MVT::f80, DAG.getEntryNode(),
12046 FudgePtr, MachinePointerInfo::getConstantPool(),
12047 MVT::f32, false, false, false, 4);
12048 // Extend everything to 80 bits to force it to be done on x87.
12049 SDValue Add = DAG.getNode(ISD::FADD, dl, MVT::f80, Fild, Fudge);
12050 return DAG.getNode(ISD::FP_ROUND, dl, DstVT, Add,
12051 DAG.getIntPtrConstant(0, dl));
12054 std::pair<SDValue,SDValue>
12055 X86TargetLowering:: FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG,
12056 bool IsSigned, bool IsReplace) const {
12059 EVT DstTy = Op.getValueType();
12061 if (!IsSigned && !isIntegerTypeFTOL(DstTy)) {
12062 assert(DstTy == MVT::i32 && "Unexpected FP_TO_UINT");
12066 assert(DstTy.getSimpleVT() <= MVT::i64 &&
12067 DstTy.getSimpleVT() >= MVT::i16 &&
12068 "Unknown FP_TO_INT to lower!");
12070 // These are really Legal.
12071 if (DstTy == MVT::i32 &&
12072 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
12073 return std::make_pair(SDValue(), SDValue());
12074 if (Subtarget->is64Bit() &&
12075 DstTy == MVT::i64 &&
12076 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
12077 return std::make_pair(SDValue(), SDValue());
12079 // We lower FP->int64 either into FISTP64 followed by a load from a temporary
12080 // stack slot, or into the FTOL runtime function.
12081 MachineFunction &MF = DAG.getMachineFunction();
12082 unsigned MemSize = DstTy.getSizeInBits()/8;
12083 int SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
12084 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
12087 if (!IsSigned && isIntegerTypeFTOL(DstTy))
12088 Opc = X86ISD::WIN_FTOL;
12090 switch (DstTy.getSimpleVT().SimpleTy) {
12091 default: llvm_unreachable("Invalid FP_TO_SINT to lower!");
12092 case MVT::i16: Opc = X86ISD::FP_TO_INT16_IN_MEM; break;
12093 case MVT::i32: Opc = X86ISD::FP_TO_INT32_IN_MEM; break;
12094 case MVT::i64: Opc = X86ISD::FP_TO_INT64_IN_MEM; break;
12097 SDValue Chain = DAG.getEntryNode();
12098 SDValue Value = Op.getOperand(0);
12099 EVT TheVT = Op.getOperand(0).getValueType();
12100 // FIXME This causes a redundant load/store if the SSE-class value is already
12101 // in memory, such as if it is on the callstack.
12102 if (isScalarFPTypeInSSEReg(TheVT)) {
12103 assert(DstTy == MVT::i64 && "Invalid FP_TO_SINT to lower!");
12104 Chain = DAG.getStore(Chain, DL, Value, StackSlot,
12105 MachinePointerInfo::getFixedStack(SSFI),
12107 SDVTList Tys = DAG.getVTList(Op.getOperand(0).getValueType(), MVT::Other);
12109 Chain, StackSlot, DAG.getValueType(TheVT)
12112 MachineMemOperand *MMO =
12113 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
12114 MachineMemOperand::MOLoad, MemSize, MemSize);
12115 Value = DAG.getMemIntrinsicNode(X86ISD::FLD, DL, Tys, Ops, DstTy, MMO);
12116 Chain = Value.getValue(1);
12117 SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
12118 StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
12121 MachineMemOperand *MMO =
12122 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
12123 MachineMemOperand::MOStore, MemSize, MemSize);
12125 if (Opc != X86ISD::WIN_FTOL) {
12126 // Build the FP_TO_INT*_IN_MEM
12127 SDValue Ops[] = { Chain, Value, StackSlot };
12128 SDValue FIST = DAG.getMemIntrinsicNode(Opc, DL, DAG.getVTList(MVT::Other),
12130 return std::make_pair(FIST, StackSlot);
12132 SDValue ftol = DAG.getNode(X86ISD::WIN_FTOL, DL,
12133 DAG.getVTList(MVT::Other, MVT::Glue),
12135 SDValue eax = DAG.getCopyFromReg(ftol, DL, X86::EAX,
12136 MVT::i32, ftol.getValue(1));
12137 SDValue edx = DAG.getCopyFromReg(eax.getValue(1), DL, X86::EDX,
12138 MVT::i32, eax.getValue(2));
12139 SDValue Ops[] = { eax, edx };
12140 SDValue pair = IsReplace
12141 ? DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops)
12142 : DAG.getMergeValues(Ops, DL);
12143 return std::make_pair(pair, SDValue());
12147 static SDValue LowerAVXExtend(SDValue Op, SelectionDAG &DAG,
12148 const X86Subtarget *Subtarget) {
12149 MVT VT = Op->getSimpleValueType(0);
12150 SDValue In = Op->getOperand(0);
12151 MVT InVT = In.getSimpleValueType();
12154 if (VT.is512BitVector() || InVT.getScalarType() == MVT::i1)
12155 return DAG.getNode(ISD::ZERO_EXTEND, dl, VT, In);
12157 // Optimize vectors in AVX mode:
12160 // Use vpunpcklwd for 4 lower elements v8i16 -> v4i32.
12161 // Use vpunpckhwd for 4 upper elements v8i16 -> v4i32.
12162 // Concat upper and lower parts.
12165 // Use vpunpckldq for 4 lower elements v4i32 -> v2i64.
12166 // Use vpunpckhdq for 4 upper elements v4i32 -> v2i64.
12167 // Concat upper and lower parts.
12170 if (((VT != MVT::v16i16) || (InVT != MVT::v16i8)) &&
12171 ((VT != MVT::v8i32) || (InVT != MVT::v8i16)) &&
12172 ((VT != MVT::v4i64) || (InVT != MVT::v4i32)))
12175 if (Subtarget->hasInt256())
12176 return DAG.getNode(X86ISD::VZEXT, dl, VT, In);
12178 SDValue ZeroVec = getZeroVector(InVT, Subtarget, DAG, dl);
12179 SDValue Undef = DAG.getUNDEF(InVT);
12180 bool NeedZero = Op.getOpcode() == ISD::ZERO_EXTEND;
12181 SDValue OpLo = getUnpackl(DAG, dl, InVT, In, NeedZero ? ZeroVec : Undef);
12182 SDValue OpHi = getUnpackh(DAG, dl, InVT, In, NeedZero ? ZeroVec : Undef);
12184 MVT HVT = MVT::getVectorVT(VT.getVectorElementType(),
12185 VT.getVectorNumElements()/2);
12187 OpLo = DAG.getBitcast(HVT, OpLo);
12188 OpHi = DAG.getBitcast(HVT, OpHi);
12190 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi);
12193 static SDValue LowerZERO_EXTEND_AVX512(SDValue Op,
12194 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
12195 MVT VT = Op->getSimpleValueType(0);
12196 SDValue In = Op->getOperand(0);
12197 MVT InVT = In.getSimpleValueType();
12199 unsigned int NumElts = VT.getVectorNumElements();
12200 if (NumElts != 8 && NumElts != 16 && !Subtarget->hasBWI())
12203 if (VT.is512BitVector() && InVT.getVectorElementType() != MVT::i1)
12204 return DAG.getNode(X86ISD::VZEXT, DL, VT, In);
12206 assert(InVT.getVectorElementType() == MVT::i1);
12207 MVT ExtVT = NumElts == 8 ? MVT::v8i64 : MVT::v16i32;
12209 DAG.getConstant(APInt(ExtVT.getScalarSizeInBits(), 1), DL, ExtVT);
12211 DAG.getConstant(APInt::getNullValue(ExtVT.getScalarSizeInBits()), DL, ExtVT);
12213 SDValue V = DAG.getNode(ISD::VSELECT, DL, ExtVT, In, One, Zero);
12214 if (VT.is512BitVector())
12216 return DAG.getNode(X86ISD::VTRUNC, DL, VT, V);
12219 static SDValue LowerANY_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
12220 SelectionDAG &DAG) {
12221 if (Subtarget->hasFp256()) {
12222 SDValue Res = LowerAVXExtend(Op, DAG, Subtarget);
12230 static SDValue LowerZERO_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
12231 SelectionDAG &DAG) {
12233 MVT VT = Op.getSimpleValueType();
12234 SDValue In = Op.getOperand(0);
12235 MVT SVT = In.getSimpleValueType();
12237 if (VT.is512BitVector() || SVT.getVectorElementType() == MVT::i1)
12238 return LowerZERO_EXTEND_AVX512(Op, Subtarget, DAG);
12240 if (Subtarget->hasFp256()) {
12241 SDValue Res = LowerAVXExtend(Op, DAG, Subtarget);
12246 assert(!VT.is256BitVector() || !SVT.is128BitVector() ||
12247 VT.getVectorNumElements() != SVT.getVectorNumElements());
12251 SDValue X86TargetLowering::LowerTRUNCATE(SDValue Op, SelectionDAG &DAG) const {
12253 MVT VT = Op.getSimpleValueType();
12254 SDValue In = Op.getOperand(0);
12255 MVT InVT = In.getSimpleValueType();
12257 if (VT == MVT::i1) {
12258 assert((InVT.isInteger() && (InVT.getSizeInBits() <= 64)) &&
12259 "Invalid scalar TRUNCATE operation");
12260 if (InVT.getSizeInBits() >= 32)
12262 In = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i32, In);
12263 return DAG.getNode(ISD::TRUNCATE, DL, VT, In);
12265 assert(VT.getVectorNumElements() == InVT.getVectorNumElements() &&
12266 "Invalid TRUNCATE operation");
12268 // move vector to mask - truncate solution for SKX
12269 if (VT.getVectorElementType() == MVT::i1) {
12270 if (InVT.is512BitVector() && InVT.getScalarSizeInBits() <= 16 &&
12271 Subtarget->hasBWI())
12272 return Op; // legal, will go to VPMOVB2M, VPMOVW2M
12273 if ((InVT.is256BitVector() || InVT.is128BitVector())
12274 && InVT.getScalarSizeInBits() <= 16 &&
12275 Subtarget->hasBWI() && Subtarget->hasVLX())
12276 return Op; // legal, will go to VPMOVB2M, VPMOVW2M
12277 if (InVT.is512BitVector() && InVT.getScalarSizeInBits() >= 32 &&
12278 Subtarget->hasDQI())
12279 return Op; // legal, will go to VPMOVD2M, VPMOVQ2M
12280 if ((InVT.is256BitVector() || InVT.is128BitVector())
12281 && InVT.getScalarSizeInBits() >= 32 &&
12282 Subtarget->hasDQI() && Subtarget->hasVLX())
12283 return Op; // legal, will go to VPMOVB2M, VPMOVQ2M
12285 if (InVT.is512BitVector() || VT.getVectorElementType() == MVT::i1) {
12286 if (VT.getVectorElementType().getSizeInBits() >=8)
12287 return DAG.getNode(X86ISD::VTRUNC, DL, VT, In);
12289 assert(VT.getVectorElementType() == MVT::i1 && "Unexpected vector type");
12290 unsigned NumElts = InVT.getVectorNumElements();
12291 assert ((NumElts == 8 || NumElts == 16) && "Unexpected vector type");
12292 if (InVT.getSizeInBits() < 512) {
12293 MVT ExtVT = (NumElts == 16)? MVT::v16i32 : MVT::v8i64;
12294 In = DAG.getNode(ISD::SIGN_EXTEND, DL, ExtVT, In);
12299 DAG.getConstant(APInt::getSignBit(InVT.getScalarSizeInBits()), DL, InVT);
12300 SDValue And = DAG.getNode(ISD::AND, DL, InVT, OneV, In);
12301 return DAG.getNode(X86ISD::TESTM, DL, VT, And, And);
12304 if ((VT == MVT::v4i32) && (InVT == MVT::v4i64)) {
12305 // On AVX2, v4i64 -> v4i32 becomes VPERMD.
12306 if (Subtarget->hasInt256()) {
12307 static const int ShufMask[] = {0, 2, 4, 6, -1, -1, -1, -1};
12308 In = DAG.getBitcast(MVT::v8i32, In);
12309 In = DAG.getVectorShuffle(MVT::v8i32, DL, In, DAG.getUNDEF(MVT::v8i32),
12311 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, In,
12312 DAG.getIntPtrConstant(0, DL));
12315 SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
12316 DAG.getIntPtrConstant(0, DL));
12317 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
12318 DAG.getIntPtrConstant(2, DL));
12319 OpLo = DAG.getBitcast(MVT::v4i32, OpLo);
12320 OpHi = DAG.getBitcast(MVT::v4i32, OpHi);
12321 static const int ShufMask[] = {0, 2, 4, 6};
12322 return DAG.getVectorShuffle(VT, DL, OpLo, OpHi, ShufMask);
12325 if ((VT == MVT::v8i16) && (InVT == MVT::v8i32)) {
12326 // On AVX2, v8i32 -> v8i16 becomed PSHUFB.
12327 if (Subtarget->hasInt256()) {
12328 In = DAG.getBitcast(MVT::v32i8, In);
12330 SmallVector<SDValue,32> pshufbMask;
12331 for (unsigned i = 0; i < 2; ++i) {
12332 pshufbMask.push_back(DAG.getConstant(0x0, DL, MVT::i8));
12333 pshufbMask.push_back(DAG.getConstant(0x1, DL, MVT::i8));
12334 pshufbMask.push_back(DAG.getConstant(0x4, DL, MVT::i8));
12335 pshufbMask.push_back(DAG.getConstant(0x5, DL, MVT::i8));
12336 pshufbMask.push_back(DAG.getConstant(0x8, DL, MVT::i8));
12337 pshufbMask.push_back(DAG.getConstant(0x9, DL, MVT::i8));
12338 pshufbMask.push_back(DAG.getConstant(0xc, DL, MVT::i8));
12339 pshufbMask.push_back(DAG.getConstant(0xd, DL, MVT::i8));
12340 for (unsigned j = 0; j < 8; ++j)
12341 pshufbMask.push_back(DAG.getConstant(0x80, DL, MVT::i8));
12343 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v32i8, pshufbMask);
12344 In = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v32i8, In, BV);
12345 In = DAG.getBitcast(MVT::v4i64, In);
12347 static const int ShufMask[] = {0, 2, -1, -1};
12348 In = DAG.getVectorShuffle(MVT::v4i64, DL, In, DAG.getUNDEF(MVT::v4i64),
12350 In = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
12351 DAG.getIntPtrConstant(0, DL));
12352 return DAG.getBitcast(VT, In);
12355 SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v4i32, In,
12356 DAG.getIntPtrConstant(0, DL));
12358 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v4i32, In,
12359 DAG.getIntPtrConstant(4, DL));
12361 OpLo = DAG.getBitcast(MVT::v16i8, OpLo);
12362 OpHi = DAG.getBitcast(MVT::v16i8, OpHi);
12364 // The PSHUFB mask:
12365 static const int ShufMask1[] = {0, 1, 4, 5, 8, 9, 12, 13,
12366 -1, -1, -1, -1, -1, -1, -1, -1};
12368 SDValue Undef = DAG.getUNDEF(MVT::v16i8);
12369 OpLo = DAG.getVectorShuffle(MVT::v16i8, DL, OpLo, Undef, ShufMask1);
12370 OpHi = DAG.getVectorShuffle(MVT::v16i8, DL, OpHi, Undef, ShufMask1);
12372 OpLo = DAG.getBitcast(MVT::v4i32, OpLo);
12373 OpHi = DAG.getBitcast(MVT::v4i32, OpHi);
12375 // The MOVLHPS Mask:
12376 static const int ShufMask2[] = {0, 1, 4, 5};
12377 SDValue res = DAG.getVectorShuffle(MVT::v4i32, DL, OpLo, OpHi, ShufMask2);
12378 return DAG.getBitcast(MVT::v8i16, res);
12381 // Handle truncation of V256 to V128 using shuffles.
12382 if (!VT.is128BitVector() || !InVT.is256BitVector())
12385 assert(Subtarget->hasFp256() && "256-bit vector without AVX!");
12387 unsigned NumElems = VT.getVectorNumElements();
12388 MVT NVT = MVT::getVectorVT(VT.getVectorElementType(), NumElems * 2);
12390 SmallVector<int, 16> MaskVec(NumElems * 2, -1);
12391 // Prepare truncation shuffle mask
12392 for (unsigned i = 0; i != NumElems; ++i)
12393 MaskVec[i] = i * 2;
12394 SDValue V = DAG.getVectorShuffle(NVT, DL, DAG.getBitcast(NVT, In),
12395 DAG.getUNDEF(NVT), &MaskVec[0]);
12396 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, V,
12397 DAG.getIntPtrConstant(0, DL));
12400 SDValue X86TargetLowering::LowerFP_TO_SINT(SDValue Op,
12401 SelectionDAG &DAG) const {
12402 assert(!Op.getSimpleValueType().isVector());
12404 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG,
12405 /*IsSigned=*/ true, /*IsReplace=*/ false);
12406 SDValue FIST = Vals.first, StackSlot = Vals.second;
12407 // If FP_TO_INTHelper failed, the node is actually supposed to be Legal.
12408 if (!FIST.getNode()) return Op;
12410 if (StackSlot.getNode())
12411 // Load the result.
12412 return DAG.getLoad(Op.getValueType(), SDLoc(Op),
12413 FIST, StackSlot, MachinePointerInfo(),
12414 false, false, false, 0);
12416 // The node is the result.
12420 SDValue X86TargetLowering::LowerFP_TO_UINT(SDValue Op,
12421 SelectionDAG &DAG) const {
12422 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG,
12423 /*IsSigned=*/ false, /*IsReplace=*/ false);
12424 SDValue FIST = Vals.first, StackSlot = Vals.second;
12425 assert(FIST.getNode() && "Unexpected failure");
12427 if (StackSlot.getNode())
12428 // Load the result.
12429 return DAG.getLoad(Op.getValueType(), SDLoc(Op),
12430 FIST, StackSlot, MachinePointerInfo(),
12431 false, false, false, 0);
12433 // The node is the result.
12437 static SDValue LowerFP_EXTEND(SDValue Op, SelectionDAG &DAG) {
12439 MVT VT = Op.getSimpleValueType();
12440 SDValue In = Op.getOperand(0);
12441 MVT SVT = In.getSimpleValueType();
12443 assert(SVT == MVT::v2f32 && "Only customize MVT::v2f32 type legalization!");
12445 return DAG.getNode(X86ISD::VFPEXT, DL, VT,
12446 DAG.getNode(ISD::CONCAT_VECTORS, DL, MVT::v4f32,
12447 In, DAG.getUNDEF(SVT)));
12450 /// The only differences between FABS and FNEG are the mask and the logic op.
12451 /// FNEG also has a folding opportunity for FNEG(FABS(x)).
12452 static SDValue LowerFABSorFNEG(SDValue Op, SelectionDAG &DAG) {
12453 assert((Op.getOpcode() == ISD::FABS || Op.getOpcode() == ISD::FNEG) &&
12454 "Wrong opcode for lowering FABS or FNEG.");
12456 bool IsFABS = (Op.getOpcode() == ISD::FABS);
12458 // If this is a FABS and it has an FNEG user, bail out to fold the combination
12459 // into an FNABS. We'll lower the FABS after that if it is still in use.
12461 for (SDNode *User : Op->uses())
12462 if (User->getOpcode() == ISD::FNEG)
12465 SDValue Op0 = Op.getOperand(0);
12466 bool IsFNABS = !IsFABS && (Op0.getOpcode() == ISD::FABS);
12469 MVT VT = Op.getSimpleValueType();
12470 // Assume scalar op for initialization; update for vector if needed.
12471 // Note that there are no scalar bitwise logical SSE/AVX instructions, so we
12472 // generate a 16-byte vector constant and logic op even for the scalar case.
12473 // Using a 16-byte mask allows folding the load of the mask with
12474 // the logic op, so it can save (~4 bytes) on code size.
12476 unsigned NumElts = VT == MVT::f64 ? 2 : 4;
12477 // FIXME: Use function attribute "OptimizeForSize" and/or CodeGenOpt::Level to
12478 // decide if we should generate a 16-byte constant mask when we only need 4 or
12479 // 8 bytes for the scalar case.
12480 if (VT.isVector()) {
12481 EltVT = VT.getVectorElementType();
12482 NumElts = VT.getVectorNumElements();
12485 unsigned EltBits = EltVT.getSizeInBits();
12486 LLVMContext *Context = DAG.getContext();
12487 // For FABS, mask is 0x7f...; for FNEG, mask is 0x80...
12489 IsFABS ? APInt::getSignedMaxValue(EltBits) : APInt::getSignBit(EltBits);
12490 Constant *C = ConstantInt::get(*Context, MaskElt);
12491 C = ConstantVector::getSplat(NumElts, C);
12492 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
12493 SDValue CPIdx = DAG.getConstantPool(C, TLI.getPointerTy());
12494 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
12495 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
12496 MachinePointerInfo::getConstantPool(),
12497 false, false, false, Alignment);
12499 if (VT.isVector()) {
12500 // For a vector, cast operands to a vector type, perform the logic op,
12501 // and cast the result back to the original value type.
12502 MVT VecVT = MVT::getVectorVT(MVT::i64, VT.getSizeInBits() / 64);
12503 SDValue MaskCasted = DAG.getBitcast(VecVT, Mask);
12504 SDValue Operand = IsFNABS ? DAG.getBitcast(VecVT, Op0.getOperand(0))
12505 : DAG.getBitcast(VecVT, Op0);
12506 unsigned BitOp = IsFABS ? ISD::AND : IsFNABS ? ISD::OR : ISD::XOR;
12507 return DAG.getBitcast(VT,
12508 DAG.getNode(BitOp, dl, VecVT, Operand, MaskCasted));
12511 // If not vector, then scalar.
12512 unsigned BitOp = IsFABS ? X86ISD::FAND : IsFNABS ? X86ISD::FOR : X86ISD::FXOR;
12513 SDValue Operand = IsFNABS ? Op0.getOperand(0) : Op0;
12514 return DAG.getNode(BitOp, dl, VT, Operand, Mask);
12517 static SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) {
12518 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
12519 LLVMContext *Context = DAG.getContext();
12520 SDValue Op0 = Op.getOperand(0);
12521 SDValue Op1 = Op.getOperand(1);
12523 MVT VT = Op.getSimpleValueType();
12524 MVT SrcVT = Op1.getSimpleValueType();
12526 // If second operand is smaller, extend it first.
12527 if (SrcVT.bitsLT(VT)) {
12528 Op1 = DAG.getNode(ISD::FP_EXTEND, dl, VT, Op1);
12531 // And if it is bigger, shrink it first.
12532 if (SrcVT.bitsGT(VT)) {
12533 Op1 = DAG.getNode(ISD::FP_ROUND, dl, VT, Op1, DAG.getIntPtrConstant(1, dl));
12537 // At this point the operands and the result should have the same
12538 // type, and that won't be f80 since that is not custom lowered.
12540 const fltSemantics &Sem =
12541 VT == MVT::f64 ? APFloat::IEEEdouble : APFloat::IEEEsingle;
12542 const unsigned SizeInBits = VT.getSizeInBits();
12544 SmallVector<Constant *, 4> CV(
12545 VT == MVT::f64 ? 2 : 4,
12546 ConstantFP::get(*Context, APFloat(Sem, APInt(SizeInBits, 0))));
12548 // First, clear all bits but the sign bit from the second operand (sign).
12549 CV[0] = ConstantFP::get(*Context,
12550 APFloat(Sem, APInt::getHighBitsSet(SizeInBits, 1)));
12551 Constant *C = ConstantVector::get(CV);
12552 SDValue CPIdx = DAG.getConstantPool(C, TLI.getPointerTy(), 16);
12553 SDValue Mask1 = DAG.getLoad(SrcVT, dl, DAG.getEntryNode(), CPIdx,
12554 MachinePointerInfo::getConstantPool(),
12555 false, false, false, 16);
12556 SDValue SignBit = DAG.getNode(X86ISD::FAND, dl, SrcVT, Op1, Mask1);
12558 // Next, clear the sign bit from the first operand (magnitude).
12559 // If it's a constant, we can clear it here.
12560 if (ConstantFPSDNode *Op0CN = dyn_cast<ConstantFPSDNode>(Op0)) {
12561 APFloat APF = Op0CN->getValueAPF();
12562 // If the magnitude is a positive zero, the sign bit alone is enough.
12563 if (APF.isPosZero())
12566 CV[0] = ConstantFP::get(*Context, APF);
12568 CV[0] = ConstantFP::get(
12570 APFloat(Sem, APInt::getLowBitsSet(SizeInBits, SizeInBits - 1)));
12572 C = ConstantVector::get(CV);
12573 CPIdx = DAG.getConstantPool(C, TLI.getPointerTy(), 16);
12574 SDValue Val = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
12575 MachinePointerInfo::getConstantPool(),
12576 false, false, false, 16);
12577 // If the magnitude operand wasn't a constant, we need to AND out the sign.
12578 if (!isa<ConstantFPSDNode>(Op0))
12579 Val = DAG.getNode(X86ISD::FAND, dl, VT, Op0, Val);
12581 // OR the magnitude value with the sign bit.
12582 return DAG.getNode(X86ISD::FOR, dl, VT, Val, SignBit);
12585 static SDValue LowerFGETSIGN(SDValue Op, SelectionDAG &DAG) {
12586 SDValue N0 = Op.getOperand(0);
12588 MVT VT = Op.getSimpleValueType();
12590 // Lower ISD::FGETSIGN to (AND (X86ISD::FGETSIGNx86 ...) 1).
12591 SDValue xFGETSIGN = DAG.getNode(X86ISD::FGETSIGNx86, dl, VT, N0,
12592 DAG.getConstant(1, dl, VT));
12593 return DAG.getNode(ISD::AND, dl, VT, xFGETSIGN, DAG.getConstant(1, dl, VT));
12596 // Check whether an OR'd tree is PTEST-able.
12597 static SDValue LowerVectorAllZeroTest(SDValue Op, const X86Subtarget *Subtarget,
12598 SelectionDAG &DAG) {
12599 assert(Op.getOpcode() == ISD::OR && "Only check OR'd tree.");
12601 if (!Subtarget->hasSSE41())
12604 if (!Op->hasOneUse())
12607 SDNode *N = Op.getNode();
12610 SmallVector<SDValue, 8> Opnds;
12611 DenseMap<SDValue, unsigned> VecInMap;
12612 SmallVector<SDValue, 8> VecIns;
12613 EVT VT = MVT::Other;
12615 // Recognize a special case where a vector is casted into wide integer to
12617 Opnds.push_back(N->getOperand(0));
12618 Opnds.push_back(N->getOperand(1));
12620 for (unsigned Slot = 0, e = Opnds.size(); Slot < e; ++Slot) {
12621 SmallVectorImpl<SDValue>::const_iterator I = Opnds.begin() + Slot;
12622 // BFS traverse all OR'd operands.
12623 if (I->getOpcode() == ISD::OR) {
12624 Opnds.push_back(I->getOperand(0));
12625 Opnds.push_back(I->getOperand(1));
12626 // Re-evaluate the number of nodes to be traversed.
12627 e += 2; // 2 more nodes (LHS and RHS) are pushed.
12631 // Quit if a non-EXTRACT_VECTOR_ELT
12632 if (I->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
12635 // Quit if without a constant index.
12636 SDValue Idx = I->getOperand(1);
12637 if (!isa<ConstantSDNode>(Idx))
12640 SDValue ExtractedFromVec = I->getOperand(0);
12641 DenseMap<SDValue, unsigned>::iterator M = VecInMap.find(ExtractedFromVec);
12642 if (M == VecInMap.end()) {
12643 VT = ExtractedFromVec.getValueType();
12644 // Quit if not 128/256-bit vector.
12645 if (!VT.is128BitVector() && !VT.is256BitVector())
12647 // Quit if not the same type.
12648 if (VecInMap.begin() != VecInMap.end() &&
12649 VT != VecInMap.begin()->first.getValueType())
12651 M = VecInMap.insert(std::make_pair(ExtractedFromVec, 0)).first;
12652 VecIns.push_back(ExtractedFromVec);
12654 M->second |= 1U << cast<ConstantSDNode>(Idx)->getZExtValue();
12657 assert((VT.is128BitVector() || VT.is256BitVector()) &&
12658 "Not extracted from 128-/256-bit vector.");
12660 unsigned FullMask = (1U << VT.getVectorNumElements()) - 1U;
12662 for (DenseMap<SDValue, unsigned>::const_iterator
12663 I = VecInMap.begin(), E = VecInMap.end(); I != E; ++I) {
12664 // Quit if not all elements are used.
12665 if (I->second != FullMask)
12669 EVT TestVT = VT.is128BitVector() ? MVT::v2i64 : MVT::v4i64;
12671 // Cast all vectors into TestVT for PTEST.
12672 for (unsigned i = 0, e = VecIns.size(); i < e; ++i)
12673 VecIns[i] = DAG.getBitcast(TestVT, VecIns[i]);
12675 // If more than one full vectors are evaluated, OR them first before PTEST.
12676 for (unsigned Slot = 0, e = VecIns.size(); e - Slot > 1; Slot += 2, e += 1) {
12677 // Each iteration will OR 2 nodes and append the result until there is only
12678 // 1 node left, i.e. the final OR'd value of all vectors.
12679 SDValue LHS = VecIns[Slot];
12680 SDValue RHS = VecIns[Slot + 1];
12681 VecIns.push_back(DAG.getNode(ISD::OR, DL, TestVT, LHS, RHS));
12684 return DAG.getNode(X86ISD::PTEST, DL, MVT::i32,
12685 VecIns.back(), VecIns.back());
12688 /// \brief return true if \c Op has a use that doesn't just read flags.
12689 static bool hasNonFlagsUse(SDValue Op) {
12690 for (SDNode::use_iterator UI = Op->use_begin(), UE = Op->use_end(); UI != UE;
12692 SDNode *User = *UI;
12693 unsigned UOpNo = UI.getOperandNo();
12694 if (User->getOpcode() == ISD::TRUNCATE && User->hasOneUse()) {
12695 // Look pass truncate.
12696 UOpNo = User->use_begin().getOperandNo();
12697 User = *User->use_begin();
12700 if (User->getOpcode() != ISD::BRCOND && User->getOpcode() != ISD::SETCC &&
12701 !(User->getOpcode() == ISD::SELECT && UOpNo == 0))
12707 /// Emit nodes that will be selected as "test Op0,Op0", or something
12709 SDValue X86TargetLowering::EmitTest(SDValue Op, unsigned X86CC, SDLoc dl,
12710 SelectionDAG &DAG) const {
12711 if (Op.getValueType() == MVT::i1) {
12712 SDValue ExtOp = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i8, Op);
12713 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, ExtOp,
12714 DAG.getConstant(0, dl, MVT::i8));
12716 // CF and OF aren't always set the way we want. Determine which
12717 // of these we need.
12718 bool NeedCF = false;
12719 bool NeedOF = false;
12722 case X86::COND_A: case X86::COND_AE:
12723 case X86::COND_B: case X86::COND_BE:
12726 case X86::COND_G: case X86::COND_GE:
12727 case X86::COND_L: case X86::COND_LE:
12728 case X86::COND_O: case X86::COND_NO: {
12729 // Check if we really need to set the
12730 // Overflow flag. If NoSignedWrap is present
12731 // that is not actually needed.
12732 switch (Op->getOpcode()) {
12737 const auto *BinNode = cast<BinaryWithFlagsSDNode>(Op.getNode());
12738 if (BinNode->Flags.hasNoSignedWrap())
12748 // See if we can use the EFLAGS value from the operand instead of
12749 // doing a separate TEST. TEST always sets OF and CF to 0, so unless
12750 // we prove that the arithmetic won't overflow, we can't use OF or CF.
12751 if (Op.getResNo() != 0 || NeedOF || NeedCF) {
12752 // Emit a CMP with 0, which is the TEST pattern.
12753 //if (Op.getValueType() == MVT::i1)
12754 // return DAG.getNode(X86ISD::CMP, dl, MVT::i1, Op,
12755 // DAG.getConstant(0, MVT::i1));
12756 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
12757 DAG.getConstant(0, dl, Op.getValueType()));
12759 unsigned Opcode = 0;
12760 unsigned NumOperands = 0;
12762 // Truncate operations may prevent the merge of the SETCC instruction
12763 // and the arithmetic instruction before it. Attempt to truncate the operands
12764 // of the arithmetic instruction and use a reduced bit-width instruction.
12765 bool NeedTruncation = false;
12766 SDValue ArithOp = Op;
12767 if (Op->getOpcode() == ISD::TRUNCATE && Op->hasOneUse()) {
12768 SDValue Arith = Op->getOperand(0);
12769 // Both the trunc and the arithmetic op need to have one user each.
12770 if (Arith->hasOneUse())
12771 switch (Arith.getOpcode()) {
12778 NeedTruncation = true;
12784 // NOTICE: In the code below we use ArithOp to hold the arithmetic operation
12785 // which may be the result of a CAST. We use the variable 'Op', which is the
12786 // non-casted variable when we check for possible users.
12787 switch (ArithOp.getOpcode()) {
12789 // Due to an isel shortcoming, be conservative if this add is likely to be
12790 // selected as part of a load-modify-store instruction. When the root node
12791 // in a match is a store, isel doesn't know how to remap non-chain non-flag
12792 // uses of other nodes in the match, such as the ADD in this case. This
12793 // leads to the ADD being left around and reselected, with the result being
12794 // two adds in the output. Alas, even if none our users are stores, that
12795 // doesn't prove we're O.K. Ergo, if we have any parents that aren't
12796 // CopyToReg or SETCC, eschew INC/DEC. A better fix seems to require
12797 // climbing the DAG back to the root, and it doesn't seem to be worth the
12799 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
12800 UE = Op.getNode()->use_end(); UI != UE; ++UI)
12801 if (UI->getOpcode() != ISD::CopyToReg &&
12802 UI->getOpcode() != ISD::SETCC &&
12803 UI->getOpcode() != ISD::STORE)
12806 if (ConstantSDNode *C =
12807 dyn_cast<ConstantSDNode>(ArithOp.getNode()->getOperand(1))) {
12808 // An add of one will be selected as an INC.
12809 if (C->getAPIntValue() == 1 && !Subtarget->slowIncDec()) {
12810 Opcode = X86ISD::INC;
12815 // An add of negative one (subtract of one) will be selected as a DEC.
12816 if (C->getAPIntValue().isAllOnesValue() && !Subtarget->slowIncDec()) {
12817 Opcode = X86ISD::DEC;
12823 // Otherwise use a regular EFLAGS-setting add.
12824 Opcode = X86ISD::ADD;
12829 // If we have a constant logical shift that's only used in a comparison
12830 // against zero turn it into an equivalent AND. This allows turning it into
12831 // a TEST instruction later.
12832 if ((X86CC == X86::COND_E || X86CC == X86::COND_NE) && Op->hasOneUse() &&
12833 isa<ConstantSDNode>(Op->getOperand(1)) && !hasNonFlagsUse(Op)) {
12834 EVT VT = Op.getValueType();
12835 unsigned BitWidth = VT.getSizeInBits();
12836 unsigned ShAmt = Op->getConstantOperandVal(1);
12837 if (ShAmt >= BitWidth) // Avoid undefined shifts.
12839 APInt Mask = ArithOp.getOpcode() == ISD::SRL
12840 ? APInt::getHighBitsSet(BitWidth, BitWidth - ShAmt)
12841 : APInt::getLowBitsSet(BitWidth, BitWidth - ShAmt);
12842 if (!Mask.isSignedIntN(32)) // Avoid large immediates.
12844 SDValue New = DAG.getNode(ISD::AND, dl, VT, Op->getOperand(0),
12845 DAG.getConstant(Mask, dl, VT));
12846 DAG.ReplaceAllUsesWith(Op, New);
12852 // If the primary and result isn't used, don't bother using X86ISD::AND,
12853 // because a TEST instruction will be better.
12854 if (!hasNonFlagsUse(Op))
12860 // Due to the ISEL shortcoming noted above, be conservative if this op is
12861 // likely to be selected as part of a load-modify-store instruction.
12862 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
12863 UE = Op.getNode()->use_end(); UI != UE; ++UI)
12864 if (UI->getOpcode() == ISD::STORE)
12867 // Otherwise use a regular EFLAGS-setting instruction.
12868 switch (ArithOp.getOpcode()) {
12869 default: llvm_unreachable("unexpected operator!");
12870 case ISD::SUB: Opcode = X86ISD::SUB; break;
12871 case ISD::XOR: Opcode = X86ISD::XOR; break;
12872 case ISD::AND: Opcode = X86ISD::AND; break;
12874 if (!NeedTruncation && (X86CC == X86::COND_E || X86CC == X86::COND_NE)) {
12875 SDValue EFLAGS = LowerVectorAllZeroTest(Op, Subtarget, DAG);
12876 if (EFLAGS.getNode())
12879 Opcode = X86ISD::OR;
12893 return SDValue(Op.getNode(), 1);
12899 // If we found that truncation is beneficial, perform the truncation and
12901 if (NeedTruncation) {
12902 EVT VT = Op.getValueType();
12903 SDValue WideVal = Op->getOperand(0);
12904 EVT WideVT = WideVal.getValueType();
12905 unsigned ConvertedOp = 0;
12906 // Use a target machine opcode to prevent further DAGCombine
12907 // optimizations that may separate the arithmetic operations
12908 // from the setcc node.
12909 switch (WideVal.getOpcode()) {
12911 case ISD::ADD: ConvertedOp = X86ISD::ADD; break;
12912 case ISD::SUB: ConvertedOp = X86ISD::SUB; break;
12913 case ISD::AND: ConvertedOp = X86ISD::AND; break;
12914 case ISD::OR: ConvertedOp = X86ISD::OR; break;
12915 case ISD::XOR: ConvertedOp = X86ISD::XOR; break;
12919 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
12920 if (TLI.isOperationLegal(WideVal.getOpcode(), WideVT)) {
12921 SDValue V0 = DAG.getNode(ISD::TRUNCATE, dl, VT, WideVal.getOperand(0));
12922 SDValue V1 = DAG.getNode(ISD::TRUNCATE, dl, VT, WideVal.getOperand(1));
12923 Op = DAG.getNode(ConvertedOp, dl, VT, V0, V1);
12929 // Emit a CMP with 0, which is the TEST pattern.
12930 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
12931 DAG.getConstant(0, dl, Op.getValueType()));
12933 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
12934 SmallVector<SDValue, 4> Ops(Op->op_begin(), Op->op_begin() + NumOperands);
12936 SDValue New = DAG.getNode(Opcode, dl, VTs, Ops);
12937 DAG.ReplaceAllUsesWith(Op, New);
12938 return SDValue(New.getNode(), 1);
12941 /// Emit nodes that will be selected as "cmp Op0,Op1", or something
12943 SDValue X86TargetLowering::EmitCmp(SDValue Op0, SDValue Op1, unsigned X86CC,
12944 SDLoc dl, SelectionDAG &DAG) const {
12945 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op1)) {
12946 if (C->getAPIntValue() == 0)
12947 return EmitTest(Op0, X86CC, dl, DAG);
12949 if (Op0.getValueType() == MVT::i1)
12950 llvm_unreachable("Unexpected comparison operation for MVT::i1 operands");
12953 if ((Op0.getValueType() == MVT::i8 || Op0.getValueType() == MVT::i16 ||
12954 Op0.getValueType() == MVT::i32 || Op0.getValueType() == MVT::i64)) {
12955 // Do the comparison at i32 if it's smaller, besides the Atom case.
12956 // This avoids subregister aliasing issues. Keep the smaller reference
12957 // if we're optimizing for size, however, as that'll allow better folding
12958 // of memory operations.
12959 if (Op0.getValueType() != MVT::i32 && Op0.getValueType() != MVT::i64 &&
12960 !DAG.getMachineFunction().getFunction()->hasFnAttribute(
12961 Attribute::MinSize) &&
12962 !Subtarget->isAtom()) {
12963 unsigned ExtendOp =
12964 isX86CCUnsigned(X86CC) ? ISD::ZERO_EXTEND : ISD::SIGN_EXTEND;
12965 Op0 = DAG.getNode(ExtendOp, dl, MVT::i32, Op0);
12966 Op1 = DAG.getNode(ExtendOp, dl, MVT::i32, Op1);
12968 // Use SUB instead of CMP to enable CSE between SUB and CMP.
12969 SDVTList VTs = DAG.getVTList(Op0.getValueType(), MVT::i32);
12970 SDValue Sub = DAG.getNode(X86ISD::SUB, dl, VTs,
12972 return SDValue(Sub.getNode(), 1);
12974 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op0, Op1);
12977 /// Convert a comparison if required by the subtarget.
12978 SDValue X86TargetLowering::ConvertCmpIfNecessary(SDValue Cmp,
12979 SelectionDAG &DAG) const {
12980 // If the subtarget does not support the FUCOMI instruction, floating-point
12981 // comparisons have to be converted.
12982 if (Subtarget->hasCMov() ||
12983 Cmp.getOpcode() != X86ISD::CMP ||
12984 !Cmp.getOperand(0).getValueType().isFloatingPoint() ||
12985 !Cmp.getOperand(1).getValueType().isFloatingPoint())
12988 // The instruction selector will select an FUCOM instruction instead of
12989 // FUCOMI, which writes the comparison result to FPSW instead of EFLAGS. Hence
12990 // build an SDNode sequence that transfers the result from FPSW into EFLAGS:
12991 // (X86sahf (trunc (srl (X86fp_stsw (trunc (X86cmp ...)), 8))))
12993 SDValue TruncFPSW = DAG.getNode(ISD::TRUNCATE, dl, MVT::i16, Cmp);
12994 SDValue FNStSW = DAG.getNode(X86ISD::FNSTSW16r, dl, MVT::i16, TruncFPSW);
12995 SDValue Srl = DAG.getNode(ISD::SRL, dl, MVT::i16, FNStSW,
12996 DAG.getConstant(8, dl, MVT::i8));
12997 SDValue TruncSrl = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Srl);
12998 return DAG.getNode(X86ISD::SAHF, dl, MVT::i32, TruncSrl);
13001 /// The minimum architected relative accuracy is 2^-12. We need one
13002 /// Newton-Raphson step to have a good float result (24 bits of precision).
13003 SDValue X86TargetLowering::getRsqrtEstimate(SDValue Op,
13004 DAGCombinerInfo &DCI,
13005 unsigned &RefinementSteps,
13006 bool &UseOneConstNR) const {
13007 EVT VT = Op.getValueType();
13008 const char *RecipOp;
13010 // SSE1 has rsqrtss and rsqrtps. AVX adds a 256-bit variant for rsqrtps.
13011 // TODO: Add support for AVX512 (v16f32).
13012 // It is likely not profitable to do this for f64 because a double-precision
13013 // rsqrt estimate with refinement on x86 prior to FMA requires at least 16
13014 // instructions: convert to single, rsqrtss, convert back to double, refine
13015 // (3 steps = at least 13 insts). If an 'rsqrtsd' variant was added to the ISA
13016 // along with FMA, this could be a throughput win.
13017 if (VT == MVT::f32 && Subtarget->hasSSE1())
13019 else if ((VT == MVT::v4f32 && Subtarget->hasSSE1()) ||
13020 (VT == MVT::v8f32 && Subtarget->hasAVX()))
13021 RecipOp = "vec-sqrtf";
13025 TargetRecip Recips = DCI.DAG.getTarget().Options.Reciprocals;
13026 if (!Recips.isEnabled(RecipOp))
13029 RefinementSteps = Recips.getRefinementSteps(RecipOp);
13030 UseOneConstNR = false;
13031 return DCI.DAG.getNode(X86ISD::FRSQRT, SDLoc(Op), VT, Op);
13034 /// The minimum architected relative accuracy is 2^-12. We need one
13035 /// Newton-Raphson step to have a good float result (24 bits of precision).
13036 SDValue X86TargetLowering::getRecipEstimate(SDValue Op,
13037 DAGCombinerInfo &DCI,
13038 unsigned &RefinementSteps) const {
13039 EVT VT = Op.getValueType();
13040 const char *RecipOp;
13042 // SSE1 has rcpss and rcpps. AVX adds a 256-bit variant for rcpps.
13043 // TODO: Add support for AVX512 (v16f32).
13044 // It is likely not profitable to do this for f64 because a double-precision
13045 // reciprocal estimate with refinement on x86 prior to FMA requires
13046 // 15 instructions: convert to single, rcpss, convert back to double, refine
13047 // (3 steps = 12 insts). If an 'rcpsd' variant was added to the ISA
13048 // along with FMA, this could be a throughput win.
13049 if (VT == MVT::f32 && Subtarget->hasSSE1())
13051 else if ((VT == MVT::v4f32 && Subtarget->hasSSE1()) ||
13052 (VT == MVT::v8f32 && Subtarget->hasAVX()))
13053 RecipOp = "vec-divf";
13057 TargetRecip Recips = DCI.DAG.getTarget().Options.Reciprocals;
13058 if (!Recips.isEnabled(RecipOp))
13061 RefinementSteps = Recips.getRefinementSteps(RecipOp);
13062 return DCI.DAG.getNode(X86ISD::FRCP, SDLoc(Op), VT, Op);
13065 /// If we have at least two divisions that use the same divisor, convert to
13066 /// multplication by a reciprocal. This may need to be adjusted for a given
13067 /// CPU if a division's cost is not at least twice the cost of a multiplication.
13068 /// This is because we still need one division to calculate the reciprocal and
13069 /// then we need two multiplies by that reciprocal as replacements for the
13070 /// original divisions.
13071 bool X86TargetLowering::combineRepeatedFPDivisors(unsigned NumUsers) const {
13072 return NumUsers > 1;
13075 static bool isAllOnes(SDValue V) {
13076 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V);
13077 return C && C->isAllOnesValue();
13080 /// LowerToBT - Result of 'and' is compared against zero. Turn it into a BT node
13081 /// if it's possible.
13082 SDValue X86TargetLowering::LowerToBT(SDValue And, ISD::CondCode CC,
13083 SDLoc dl, SelectionDAG &DAG) const {
13084 SDValue Op0 = And.getOperand(0);
13085 SDValue Op1 = And.getOperand(1);
13086 if (Op0.getOpcode() == ISD::TRUNCATE)
13087 Op0 = Op0.getOperand(0);
13088 if (Op1.getOpcode() == ISD::TRUNCATE)
13089 Op1 = Op1.getOperand(0);
13092 if (Op1.getOpcode() == ISD::SHL)
13093 std::swap(Op0, Op1);
13094 if (Op0.getOpcode() == ISD::SHL) {
13095 if (ConstantSDNode *And00C = dyn_cast<ConstantSDNode>(Op0.getOperand(0)))
13096 if (And00C->getZExtValue() == 1) {
13097 // If we looked past a truncate, check that it's only truncating away
13099 unsigned BitWidth = Op0.getValueSizeInBits();
13100 unsigned AndBitWidth = And.getValueSizeInBits();
13101 if (BitWidth > AndBitWidth) {
13103 DAG.computeKnownBits(Op0, Zeros, Ones);
13104 if (Zeros.countLeadingOnes() < BitWidth - AndBitWidth)
13108 RHS = Op0.getOperand(1);
13110 } else if (Op1.getOpcode() == ISD::Constant) {
13111 ConstantSDNode *AndRHS = cast<ConstantSDNode>(Op1);
13112 uint64_t AndRHSVal = AndRHS->getZExtValue();
13113 SDValue AndLHS = Op0;
13115 if (AndRHSVal == 1 && AndLHS.getOpcode() == ISD::SRL) {
13116 LHS = AndLHS.getOperand(0);
13117 RHS = AndLHS.getOperand(1);
13120 // Use BT if the immediate can't be encoded in a TEST instruction.
13121 if (!isUInt<32>(AndRHSVal) && isPowerOf2_64(AndRHSVal)) {
13123 RHS = DAG.getConstant(Log2_64_Ceil(AndRHSVal), dl, LHS.getValueType());
13127 if (LHS.getNode()) {
13128 // If LHS is i8, promote it to i32 with any_extend. There is no i8 BT
13129 // instruction. Since the shift amount is in-range-or-undefined, we know
13130 // that doing a bittest on the i32 value is ok. We extend to i32 because
13131 // the encoding for the i16 version is larger than the i32 version.
13132 // Also promote i16 to i32 for performance / code size reason.
13133 if (LHS.getValueType() == MVT::i8 ||
13134 LHS.getValueType() == MVT::i16)
13135 LHS = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, LHS);
13137 // If the operand types disagree, extend the shift amount to match. Since
13138 // BT ignores high bits (like shifts) we can use anyextend.
13139 if (LHS.getValueType() != RHS.getValueType())
13140 RHS = DAG.getNode(ISD::ANY_EXTEND, dl, LHS.getValueType(), RHS);
13142 SDValue BT = DAG.getNode(X86ISD::BT, dl, MVT::i32, LHS, RHS);
13143 X86::CondCode Cond = CC == ISD::SETEQ ? X86::COND_AE : X86::COND_B;
13144 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
13145 DAG.getConstant(Cond, dl, MVT::i8), BT);
13151 /// \brief - Turns an ISD::CondCode into a value suitable for SSE floating point
13153 static int translateX86FSETCC(ISD::CondCode SetCCOpcode, SDValue &Op0,
13158 // SSE Condition code mapping:
13167 switch (SetCCOpcode) {
13168 default: llvm_unreachable("Unexpected SETCC condition");
13170 case ISD::SETEQ: SSECC = 0; break;
13172 case ISD::SETGT: Swap = true; // Fallthrough
13174 case ISD::SETOLT: SSECC = 1; break;
13176 case ISD::SETGE: Swap = true; // Fallthrough
13178 case ISD::SETOLE: SSECC = 2; break;
13179 case ISD::SETUO: SSECC = 3; break;
13181 case ISD::SETNE: SSECC = 4; break;
13182 case ISD::SETULE: Swap = true; // Fallthrough
13183 case ISD::SETUGE: SSECC = 5; break;
13184 case ISD::SETULT: Swap = true; // Fallthrough
13185 case ISD::SETUGT: SSECC = 6; break;
13186 case ISD::SETO: SSECC = 7; break;
13188 case ISD::SETONE: SSECC = 8; break;
13191 std::swap(Op0, Op1);
13196 // Lower256IntVSETCC - Break a VSETCC 256-bit integer VSETCC into two new 128
13197 // ones, and then concatenate the result back.
13198 static SDValue Lower256IntVSETCC(SDValue Op, SelectionDAG &DAG) {
13199 MVT VT = Op.getSimpleValueType();
13201 assert(VT.is256BitVector() && Op.getOpcode() == ISD::SETCC &&
13202 "Unsupported value type for operation");
13204 unsigned NumElems = VT.getVectorNumElements();
13206 SDValue CC = Op.getOperand(2);
13208 // Extract the LHS vectors
13209 SDValue LHS = Op.getOperand(0);
13210 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
13211 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
13213 // Extract the RHS vectors
13214 SDValue RHS = Op.getOperand(1);
13215 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, dl);
13216 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, dl);
13218 // Issue the operation on the smaller types and concatenate the result back
13219 MVT EltVT = VT.getVectorElementType();
13220 MVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
13221 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
13222 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1, CC),
13223 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2, CC));
13226 static SDValue LowerBoolVSETCC_AVX512(SDValue Op, SelectionDAG &DAG) {
13227 SDValue Op0 = Op.getOperand(0);
13228 SDValue Op1 = Op.getOperand(1);
13229 SDValue CC = Op.getOperand(2);
13230 MVT VT = Op.getSimpleValueType();
13233 assert(Op0.getValueType().getVectorElementType() == MVT::i1 &&
13234 "Unexpected type for boolean compare operation");
13235 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
13236 SDValue NotOp0 = DAG.getNode(ISD::XOR, dl, VT, Op0,
13237 DAG.getConstant(-1, dl, VT));
13238 SDValue NotOp1 = DAG.getNode(ISD::XOR, dl, VT, Op1,
13239 DAG.getConstant(-1, dl, VT));
13240 switch (SetCCOpcode) {
13241 default: llvm_unreachable("Unexpected SETCC condition");
13243 // (x == y) -> ~(x ^ y)
13244 return DAG.getNode(ISD::XOR, dl, VT,
13245 DAG.getNode(ISD::XOR, dl, VT, Op0, Op1),
13246 DAG.getConstant(-1, dl, VT));
13248 // (x != y) -> (x ^ y)
13249 return DAG.getNode(ISD::XOR, dl, VT, Op0, Op1);
13252 // (x > y) -> (x & ~y)
13253 return DAG.getNode(ISD::AND, dl, VT, Op0, NotOp1);
13256 // (x < y) -> (~x & y)
13257 return DAG.getNode(ISD::AND, dl, VT, NotOp0, Op1);
13260 // (x <= y) -> (~x | y)
13261 return DAG.getNode(ISD::OR, dl, VT, NotOp0, Op1);
13264 // (x >=y) -> (x | ~y)
13265 return DAG.getNode(ISD::OR, dl, VT, Op0, NotOp1);
13269 static SDValue LowerIntVSETCC_AVX512(SDValue Op, SelectionDAG &DAG,
13270 const X86Subtarget *Subtarget) {
13271 SDValue Op0 = Op.getOperand(0);
13272 SDValue Op1 = Op.getOperand(1);
13273 SDValue CC = Op.getOperand(2);
13274 MVT VT = Op.getSimpleValueType();
13277 assert(Op0.getValueType().getVectorElementType().getSizeInBits() >= 8 &&
13278 Op.getValueType().getScalarType() == MVT::i1 &&
13279 "Cannot set masked compare for this operation");
13281 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
13283 bool Unsigned = false;
13286 switch (SetCCOpcode) {
13287 default: llvm_unreachable("Unexpected SETCC condition");
13288 case ISD::SETNE: SSECC = 4; break;
13289 case ISD::SETEQ: Opc = X86ISD::PCMPEQM; break;
13290 case ISD::SETUGT: SSECC = 6; Unsigned = true; break;
13291 case ISD::SETLT: Swap = true; //fall-through
13292 case ISD::SETGT: Opc = X86ISD::PCMPGTM; break;
13293 case ISD::SETULT: SSECC = 1; Unsigned = true; break;
13294 case ISD::SETUGE: SSECC = 5; Unsigned = true; break; //NLT
13295 case ISD::SETGE: Swap = true; SSECC = 2; break; // LE + swap
13296 case ISD::SETULE: Unsigned = true; //fall-through
13297 case ISD::SETLE: SSECC = 2; break;
13301 std::swap(Op0, Op1);
13303 return DAG.getNode(Opc, dl, VT, Op0, Op1);
13304 Opc = Unsigned ? X86ISD::CMPMU: X86ISD::CMPM;
13305 return DAG.getNode(Opc, dl, VT, Op0, Op1,
13306 DAG.getConstant(SSECC, dl, MVT::i8));
13309 /// \brief Try to turn a VSETULT into a VSETULE by modifying its second
13310 /// operand \p Op1. If non-trivial (for example because it's not constant)
13311 /// return an empty value.
13312 static SDValue ChangeVSETULTtoVSETULE(SDLoc dl, SDValue Op1, SelectionDAG &DAG)
13314 BuildVectorSDNode *BV = dyn_cast<BuildVectorSDNode>(Op1.getNode());
13318 MVT VT = Op1.getSimpleValueType();
13319 MVT EVT = VT.getVectorElementType();
13320 unsigned n = VT.getVectorNumElements();
13321 SmallVector<SDValue, 8> ULTOp1;
13323 for (unsigned i = 0; i < n; ++i) {
13324 ConstantSDNode *Elt = dyn_cast<ConstantSDNode>(BV->getOperand(i));
13325 if (!Elt || Elt->isOpaque() || Elt->getValueType(0) != EVT)
13328 // Avoid underflow.
13329 APInt Val = Elt->getAPIntValue();
13333 ULTOp1.push_back(DAG.getConstant(Val - 1, dl, EVT));
13336 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, ULTOp1);
13339 static SDValue LowerVSETCC(SDValue Op, const X86Subtarget *Subtarget,
13340 SelectionDAG &DAG) {
13341 SDValue Op0 = Op.getOperand(0);
13342 SDValue Op1 = Op.getOperand(1);
13343 SDValue CC = Op.getOperand(2);
13344 MVT VT = Op.getSimpleValueType();
13345 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
13346 bool isFP = Op.getOperand(1).getSimpleValueType().isFloatingPoint();
13351 MVT EltVT = Op0.getSimpleValueType().getVectorElementType();
13352 assert(EltVT == MVT::f32 || EltVT == MVT::f64);
13355 unsigned SSECC = translateX86FSETCC(SetCCOpcode, Op0, Op1);
13356 unsigned Opc = X86ISD::CMPP;
13357 if (Subtarget->hasAVX512() && VT.getVectorElementType() == MVT::i1) {
13358 assert(VT.getVectorNumElements() <= 16);
13359 Opc = X86ISD::CMPM;
13361 // In the two special cases we can't handle, emit two comparisons.
13364 unsigned CombineOpc;
13365 if (SetCCOpcode == ISD::SETUEQ) {
13366 CC0 = 3; CC1 = 0; CombineOpc = ISD::OR;
13368 assert(SetCCOpcode == ISD::SETONE);
13369 CC0 = 7; CC1 = 4; CombineOpc = ISD::AND;
13372 SDValue Cmp0 = DAG.getNode(Opc, dl, VT, Op0, Op1,
13373 DAG.getConstant(CC0, dl, MVT::i8));
13374 SDValue Cmp1 = DAG.getNode(Opc, dl, VT, Op0, Op1,
13375 DAG.getConstant(CC1, dl, MVT::i8));
13376 return DAG.getNode(CombineOpc, dl, VT, Cmp0, Cmp1);
13378 // Handle all other FP comparisons here.
13379 return DAG.getNode(Opc, dl, VT, Op0, Op1,
13380 DAG.getConstant(SSECC, dl, MVT::i8));
13383 // Break 256-bit integer vector compare into smaller ones.
13384 if (VT.is256BitVector() && !Subtarget->hasInt256())
13385 return Lower256IntVSETCC(Op, DAG);
13387 EVT OpVT = Op1.getValueType();
13388 if (OpVT.getVectorElementType() == MVT::i1)
13389 return LowerBoolVSETCC_AVX512(Op, DAG);
13391 bool MaskResult = (VT.getVectorElementType() == MVT::i1);
13392 if (Subtarget->hasAVX512()) {
13393 if (Op1.getValueType().is512BitVector() ||
13394 (Subtarget->hasBWI() && Subtarget->hasVLX()) ||
13395 (MaskResult && OpVT.getVectorElementType().getSizeInBits() >= 32))
13396 return LowerIntVSETCC_AVX512(Op, DAG, Subtarget);
13398 // In AVX-512 architecture setcc returns mask with i1 elements,
13399 // But there is no compare instruction for i8 and i16 elements in KNL.
13400 // We are not talking about 512-bit operands in this case, these
13401 // types are illegal.
13403 (OpVT.getVectorElementType().getSizeInBits() < 32 &&
13404 OpVT.getVectorElementType().getSizeInBits() >= 8))
13405 return DAG.getNode(ISD::TRUNCATE, dl, VT,
13406 DAG.getNode(ISD::SETCC, dl, OpVT, Op0, Op1, CC));
13409 // We are handling one of the integer comparisons here. Since SSE only has
13410 // GT and EQ comparisons for integer, swapping operands and multiple
13411 // operations may be required for some comparisons.
13413 bool Swap = false, Invert = false, FlipSigns = false, MinMax = false;
13414 bool Subus = false;
13416 switch (SetCCOpcode) {
13417 default: llvm_unreachable("Unexpected SETCC condition");
13418 case ISD::SETNE: Invert = true;
13419 case ISD::SETEQ: Opc = X86ISD::PCMPEQ; break;
13420 case ISD::SETLT: Swap = true;
13421 case ISD::SETGT: Opc = X86ISD::PCMPGT; break;
13422 case ISD::SETGE: Swap = true;
13423 case ISD::SETLE: Opc = X86ISD::PCMPGT;
13424 Invert = true; break;
13425 case ISD::SETULT: Swap = true;
13426 case ISD::SETUGT: Opc = X86ISD::PCMPGT;
13427 FlipSigns = true; break;
13428 case ISD::SETUGE: Swap = true;
13429 case ISD::SETULE: Opc = X86ISD::PCMPGT;
13430 FlipSigns = true; Invert = true; break;
13433 // Special case: Use min/max operations for SETULE/SETUGE
13434 MVT VET = VT.getVectorElementType();
13436 (Subtarget->hasSSE41() && (VET >= MVT::i8 && VET <= MVT::i32))
13437 || (Subtarget->hasSSE2() && (VET == MVT::i8));
13440 switch (SetCCOpcode) {
13442 case ISD::SETULE: Opc = X86ISD::UMIN; MinMax = true; break;
13443 case ISD::SETUGE: Opc = X86ISD::UMAX; MinMax = true; break;
13446 if (MinMax) { Swap = false; Invert = false; FlipSigns = false; }
13449 bool hasSubus = Subtarget->hasSSE2() && (VET == MVT::i8 || VET == MVT::i16);
13450 if (!MinMax && hasSubus) {
13451 // As another special case, use PSUBUS[BW] when it's profitable. E.g. for
13453 // t = psubus Op0, Op1
13454 // pcmpeq t, <0..0>
13455 switch (SetCCOpcode) {
13457 case ISD::SETULT: {
13458 // If the comparison is against a constant we can turn this into a
13459 // setule. With psubus, setule does not require a swap. This is
13460 // beneficial because the constant in the register is no longer
13461 // destructed as the destination so it can be hoisted out of a loop.
13462 // Only do this pre-AVX since vpcmp* is no longer destructive.
13463 if (Subtarget->hasAVX())
13465 SDValue ULEOp1 = ChangeVSETULTtoVSETULE(dl, Op1, DAG);
13466 if (ULEOp1.getNode()) {
13468 Subus = true; Invert = false; Swap = false;
13472 // Psubus is better than flip-sign because it requires no inversion.
13473 case ISD::SETUGE: Subus = true; Invert = false; Swap = true; break;
13474 case ISD::SETULE: Subus = true; Invert = false; Swap = false; break;
13478 Opc = X86ISD::SUBUS;
13484 std::swap(Op0, Op1);
13486 // Check that the operation in question is available (most are plain SSE2,
13487 // but PCMPGTQ and PCMPEQQ have different requirements).
13488 if (VT == MVT::v2i64) {
13489 if (Opc == X86ISD::PCMPGT && !Subtarget->hasSSE42()) {
13490 assert(Subtarget->hasSSE2() && "Don't know how to lower!");
13492 // First cast everything to the right type.
13493 Op0 = DAG.getBitcast(MVT::v4i32, Op0);
13494 Op1 = DAG.getBitcast(MVT::v4i32, Op1);
13496 // Since SSE has no unsigned integer comparisons, we need to flip the sign
13497 // bits of the inputs before performing those operations. The lower
13498 // compare is always unsigned.
13501 SB = DAG.getConstant(0x80000000U, dl, MVT::v4i32);
13503 SDValue Sign = DAG.getConstant(0x80000000U, dl, MVT::i32);
13504 SDValue Zero = DAG.getConstant(0x00000000U, dl, MVT::i32);
13505 SB = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32,
13506 Sign, Zero, Sign, Zero);
13508 Op0 = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Op0, SB);
13509 Op1 = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Op1, SB);
13511 // Emulate PCMPGTQ with (hi1 > hi2) | ((hi1 == hi2) & (lo1 > lo2))
13512 SDValue GT = DAG.getNode(X86ISD::PCMPGT, dl, MVT::v4i32, Op0, Op1);
13513 SDValue EQ = DAG.getNode(X86ISD::PCMPEQ, dl, MVT::v4i32, Op0, Op1);
13515 // Create masks for only the low parts/high parts of the 64 bit integers.
13516 static const int MaskHi[] = { 1, 1, 3, 3 };
13517 static const int MaskLo[] = { 0, 0, 2, 2 };
13518 SDValue EQHi = DAG.getVectorShuffle(MVT::v4i32, dl, EQ, EQ, MaskHi);
13519 SDValue GTLo = DAG.getVectorShuffle(MVT::v4i32, dl, GT, GT, MaskLo);
13520 SDValue GTHi = DAG.getVectorShuffle(MVT::v4i32, dl, GT, GT, MaskHi);
13522 SDValue Result = DAG.getNode(ISD::AND, dl, MVT::v4i32, EQHi, GTLo);
13523 Result = DAG.getNode(ISD::OR, dl, MVT::v4i32, Result, GTHi);
13526 Result = DAG.getNOT(dl, Result, MVT::v4i32);
13528 return DAG.getBitcast(VT, Result);
13531 if (Opc == X86ISD::PCMPEQ && !Subtarget->hasSSE41()) {
13532 // If pcmpeqq is missing but pcmpeqd is available synthesize pcmpeqq with
13533 // pcmpeqd + pshufd + pand.
13534 assert(Subtarget->hasSSE2() && !FlipSigns && "Don't know how to lower!");
13536 // First cast everything to the right type.
13537 Op0 = DAG.getBitcast(MVT::v4i32, Op0);
13538 Op1 = DAG.getBitcast(MVT::v4i32, Op1);
13541 SDValue Result = DAG.getNode(Opc, dl, MVT::v4i32, Op0, Op1);
13543 // Make sure the lower and upper halves are both all-ones.
13544 static const int Mask[] = { 1, 0, 3, 2 };
13545 SDValue Shuf = DAG.getVectorShuffle(MVT::v4i32, dl, Result, Result, Mask);
13546 Result = DAG.getNode(ISD::AND, dl, MVT::v4i32, Result, Shuf);
13549 Result = DAG.getNOT(dl, Result, MVT::v4i32);
13551 return DAG.getBitcast(VT, Result);
13555 // Since SSE has no unsigned integer comparisons, we need to flip the sign
13556 // bits of the inputs before performing those operations.
13558 EVT EltVT = VT.getVectorElementType();
13559 SDValue SB = DAG.getConstant(APInt::getSignBit(EltVT.getSizeInBits()), dl,
13561 Op0 = DAG.getNode(ISD::XOR, dl, VT, Op0, SB);
13562 Op1 = DAG.getNode(ISD::XOR, dl, VT, Op1, SB);
13565 SDValue Result = DAG.getNode(Opc, dl, VT, Op0, Op1);
13567 // If the logical-not of the result is required, perform that now.
13569 Result = DAG.getNOT(dl, Result, VT);
13572 Result = DAG.getNode(X86ISD::PCMPEQ, dl, VT, Op0, Result);
13575 Result = DAG.getNode(X86ISD::PCMPEQ, dl, VT, Result,
13576 getZeroVector(VT, Subtarget, DAG, dl));
13581 SDValue X86TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
13583 MVT VT = Op.getSimpleValueType();
13585 if (VT.isVector()) return LowerVSETCC(Op, Subtarget, DAG);
13587 assert(((!Subtarget->hasAVX512() && VT == MVT::i8) || (VT == MVT::i1))
13588 && "SetCC type must be 8-bit or 1-bit integer");
13589 SDValue Op0 = Op.getOperand(0);
13590 SDValue Op1 = Op.getOperand(1);
13592 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
13594 // Optimize to BT if possible.
13595 // Lower (X & (1 << N)) == 0 to BT(X, N).
13596 // Lower ((X >>u N) & 1) != 0 to BT(X, N).
13597 // Lower ((X >>s N) & 1) != 0 to BT(X, N).
13598 if (Op0.getOpcode() == ISD::AND && Op0.hasOneUse() &&
13599 Op1.getOpcode() == ISD::Constant &&
13600 cast<ConstantSDNode>(Op1)->isNullValue() &&
13601 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
13602 SDValue NewSetCC = LowerToBT(Op0, CC, dl, DAG);
13603 if (NewSetCC.getNode()) {
13605 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, NewSetCC);
13610 // Look for X == 0, X == 1, X != 0, or X != 1. We can simplify some forms of
13612 if (Op1.getOpcode() == ISD::Constant &&
13613 (cast<ConstantSDNode>(Op1)->getZExtValue() == 1 ||
13614 cast<ConstantSDNode>(Op1)->isNullValue()) &&
13615 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
13617 // If the input is a setcc, then reuse the input setcc or use a new one with
13618 // the inverted condition.
13619 if (Op0.getOpcode() == X86ISD::SETCC) {
13620 X86::CondCode CCode = (X86::CondCode)Op0.getConstantOperandVal(0);
13621 bool Invert = (CC == ISD::SETNE) ^
13622 cast<ConstantSDNode>(Op1)->isNullValue();
13626 CCode = X86::GetOppositeBranchCondition(CCode);
13627 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
13628 DAG.getConstant(CCode, dl, MVT::i8),
13629 Op0.getOperand(1));
13631 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, SetCC);
13635 if ((Op0.getValueType() == MVT::i1) && (Op1.getOpcode() == ISD::Constant) &&
13636 (cast<ConstantSDNode>(Op1)->getZExtValue() == 1) &&
13637 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
13639 ISD::CondCode NewCC = ISD::getSetCCInverse(CC, true);
13640 return DAG.getSetCC(dl, VT, Op0, DAG.getConstant(0, dl, MVT::i1), NewCC);
13643 bool isFP = Op1.getSimpleValueType().isFloatingPoint();
13644 unsigned X86CC = TranslateX86CC(CC, dl, isFP, Op0, Op1, DAG);
13645 if (X86CC == X86::COND_INVALID)
13648 SDValue EFLAGS = EmitCmp(Op0, Op1, X86CC, dl, DAG);
13649 EFLAGS = ConvertCmpIfNecessary(EFLAGS, DAG);
13650 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
13651 DAG.getConstant(X86CC, dl, MVT::i8), EFLAGS);
13653 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, SetCC);
13657 // isX86LogicalCmp - Return true if opcode is a X86 logical comparison.
13658 static bool isX86LogicalCmp(SDValue Op) {
13659 unsigned Opc = Op.getNode()->getOpcode();
13660 if (Opc == X86ISD::CMP || Opc == X86ISD::COMI || Opc == X86ISD::UCOMI ||
13661 Opc == X86ISD::SAHF)
13663 if (Op.getResNo() == 1 &&
13664 (Opc == X86ISD::ADD ||
13665 Opc == X86ISD::SUB ||
13666 Opc == X86ISD::ADC ||
13667 Opc == X86ISD::SBB ||
13668 Opc == X86ISD::SMUL ||
13669 Opc == X86ISD::UMUL ||
13670 Opc == X86ISD::INC ||
13671 Opc == X86ISD::DEC ||
13672 Opc == X86ISD::OR ||
13673 Opc == X86ISD::XOR ||
13674 Opc == X86ISD::AND))
13677 if (Op.getResNo() == 2 && Opc == X86ISD::UMUL)
13683 static bool isTruncWithZeroHighBitsInput(SDValue V, SelectionDAG &DAG) {
13684 if (V.getOpcode() != ISD::TRUNCATE)
13687 SDValue VOp0 = V.getOperand(0);
13688 unsigned InBits = VOp0.getValueSizeInBits();
13689 unsigned Bits = V.getValueSizeInBits();
13690 return DAG.MaskedValueIsZero(VOp0, APInt::getHighBitsSet(InBits,InBits-Bits));
13693 SDValue X86TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {
13694 bool addTest = true;
13695 SDValue Cond = Op.getOperand(0);
13696 SDValue Op1 = Op.getOperand(1);
13697 SDValue Op2 = Op.getOperand(2);
13699 EVT VT = Op1.getValueType();
13702 // Lower FP selects into a CMP/AND/ANDN/OR sequence when the necessary SSE ops
13703 // are available or VBLENDV if AVX is available.
13704 // Otherwise FP cmovs get lowered into a less efficient branch sequence later.
13705 if (Cond.getOpcode() == ISD::SETCC &&
13706 ((Subtarget->hasSSE2() && (VT == MVT::f32 || VT == MVT::f64)) ||
13707 (Subtarget->hasSSE1() && VT == MVT::f32)) &&
13708 VT == Cond.getOperand(0).getValueType() && Cond->hasOneUse()) {
13709 SDValue CondOp0 = Cond.getOperand(0), CondOp1 = Cond.getOperand(1);
13710 int SSECC = translateX86FSETCC(
13711 cast<CondCodeSDNode>(Cond.getOperand(2))->get(), CondOp0, CondOp1);
13714 if (Subtarget->hasAVX512()) {
13715 SDValue Cmp = DAG.getNode(X86ISD::FSETCC, DL, MVT::i1, CondOp0, CondOp1,
13716 DAG.getConstant(SSECC, DL, MVT::i8));
13717 return DAG.getNode(X86ISD::SELECT, DL, VT, Cmp, Op1, Op2);
13720 SDValue Cmp = DAG.getNode(X86ISD::FSETCC, DL, VT, CondOp0, CondOp1,
13721 DAG.getConstant(SSECC, DL, MVT::i8));
13723 // If we have AVX, we can use a variable vector select (VBLENDV) instead
13724 // of 3 logic instructions for size savings and potentially speed.
13725 // Unfortunately, there is no scalar form of VBLENDV.
13727 // If either operand is a constant, don't try this. We can expect to
13728 // optimize away at least one of the logic instructions later in that
13729 // case, so that sequence would be faster than a variable blend.
13731 // BLENDV was introduced with SSE 4.1, but the 2 register form implicitly
13732 // uses XMM0 as the selection register. That may need just as many
13733 // instructions as the AND/ANDN/OR sequence due to register moves, so
13736 if (Subtarget->hasAVX() &&
13737 !isa<ConstantFPSDNode>(Op1) && !isa<ConstantFPSDNode>(Op2)) {
13739 // Convert to vectors, do a VSELECT, and convert back to scalar.
13740 // All of the conversions should be optimized away.
13742 EVT VecVT = VT == MVT::f32 ? MVT::v4f32 : MVT::v2f64;
13743 SDValue VOp1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, VecVT, Op1);
13744 SDValue VOp2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, VecVT, Op2);
13745 SDValue VCmp = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, VecVT, Cmp);
13747 EVT VCmpVT = VT == MVT::f32 ? MVT::v4i32 : MVT::v2i64;
13748 VCmp = DAG.getBitcast(VCmpVT, VCmp);
13750 SDValue VSel = DAG.getNode(ISD::VSELECT, DL, VecVT, VCmp, VOp1, VOp2);
13752 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, VT,
13753 VSel, DAG.getIntPtrConstant(0, DL));
13755 SDValue AndN = DAG.getNode(X86ISD::FANDN, DL, VT, Cmp, Op2);
13756 SDValue And = DAG.getNode(X86ISD::FAND, DL, VT, Cmp, Op1);
13757 return DAG.getNode(X86ISD::FOR, DL, VT, AndN, And);
13761 if (VT.isVector() && VT.getScalarType() == MVT::i1) {
13763 if (ISD::isBuildVectorOfConstantSDNodes(Op1.getNode()))
13764 Op1Scalar = ConvertI1VectorToInterger(Op1, DAG);
13765 else if (Op1.getOpcode() == ISD::BITCAST && Op1.getOperand(0))
13766 Op1Scalar = Op1.getOperand(0);
13768 if (ISD::isBuildVectorOfConstantSDNodes(Op2.getNode()))
13769 Op2Scalar = ConvertI1VectorToInterger(Op2, DAG);
13770 else if (Op2.getOpcode() == ISD::BITCAST && Op2.getOperand(0))
13771 Op2Scalar = Op2.getOperand(0);
13772 if (Op1Scalar.getNode() && Op2Scalar.getNode()) {
13773 SDValue newSelect = DAG.getNode(ISD::SELECT, DL,
13774 Op1Scalar.getValueType(),
13775 Cond, Op1Scalar, Op2Scalar);
13776 if (newSelect.getValueSizeInBits() == VT.getSizeInBits())
13777 return DAG.getBitcast(VT, newSelect);
13778 SDValue ExtVec = DAG.getBitcast(MVT::v8i1, newSelect);
13779 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, ExtVec,
13780 DAG.getIntPtrConstant(0, DL));
13784 if (VT == MVT::v4i1 || VT == MVT::v2i1) {
13785 SDValue zeroConst = DAG.getIntPtrConstant(0, DL);
13786 Op1 = DAG.getNode(ISD::INSERT_SUBVECTOR, DL, MVT::v8i1,
13787 DAG.getUNDEF(MVT::v8i1), Op1, zeroConst);
13788 Op2 = DAG.getNode(ISD::INSERT_SUBVECTOR, DL, MVT::v8i1,
13789 DAG.getUNDEF(MVT::v8i1), Op2, zeroConst);
13790 SDValue newSelect = DAG.getNode(ISD::SELECT, DL, MVT::v8i1,
13792 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, newSelect, zeroConst);
13795 if (Cond.getOpcode() == ISD::SETCC) {
13796 SDValue NewCond = LowerSETCC(Cond, DAG);
13797 if (NewCond.getNode())
13801 // (select (x == 0), -1, y) -> (sign_bit (x - 1)) | y
13802 // (select (x == 0), y, -1) -> ~(sign_bit (x - 1)) | y
13803 // (select (x != 0), y, -1) -> (sign_bit (x - 1)) | y
13804 // (select (x != 0), -1, y) -> ~(sign_bit (x - 1)) | y
13805 if (Cond.getOpcode() == X86ISD::SETCC &&
13806 Cond.getOperand(1).getOpcode() == X86ISD::CMP &&
13807 isZero(Cond.getOperand(1).getOperand(1))) {
13808 SDValue Cmp = Cond.getOperand(1);
13810 unsigned CondCode =cast<ConstantSDNode>(Cond.getOperand(0))->getZExtValue();
13812 if ((isAllOnes(Op1) || isAllOnes(Op2)) &&
13813 (CondCode == X86::COND_E || CondCode == X86::COND_NE)) {
13814 SDValue Y = isAllOnes(Op2) ? Op1 : Op2;
13816 SDValue CmpOp0 = Cmp.getOperand(0);
13817 // Apply further optimizations for special cases
13818 // (select (x != 0), -1, 0) -> neg & sbb
13819 // (select (x == 0), 0, -1) -> neg & sbb
13820 if (ConstantSDNode *YC = dyn_cast<ConstantSDNode>(Y))
13821 if (YC->isNullValue() &&
13822 (isAllOnes(Op1) == (CondCode == X86::COND_NE))) {
13823 SDVTList VTs = DAG.getVTList(CmpOp0.getValueType(), MVT::i32);
13824 SDValue Neg = DAG.getNode(X86ISD::SUB, DL, VTs,
13825 DAG.getConstant(0, DL,
13826 CmpOp0.getValueType()),
13828 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
13829 DAG.getConstant(X86::COND_B, DL, MVT::i8),
13830 SDValue(Neg.getNode(), 1));
13834 Cmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32,
13835 CmpOp0, DAG.getConstant(1, DL, CmpOp0.getValueType()));
13836 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
13838 SDValue Res = // Res = 0 or -1.
13839 DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
13840 DAG.getConstant(X86::COND_B, DL, MVT::i8), Cmp);
13842 if (isAllOnes(Op1) != (CondCode == X86::COND_E))
13843 Res = DAG.getNOT(DL, Res, Res.getValueType());
13845 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(Op2);
13846 if (!N2C || !N2C->isNullValue())
13847 Res = DAG.getNode(ISD::OR, DL, Res.getValueType(), Res, Y);
13852 // Look past (and (setcc_carry (cmp ...)), 1).
13853 if (Cond.getOpcode() == ISD::AND &&
13854 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
13855 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
13856 if (C && C->getAPIntValue() == 1)
13857 Cond = Cond.getOperand(0);
13860 // If condition flag is set by a X86ISD::CMP, then use it as the condition
13861 // setting operand in place of the X86ISD::SETCC.
13862 unsigned CondOpcode = Cond.getOpcode();
13863 if (CondOpcode == X86ISD::SETCC ||
13864 CondOpcode == X86ISD::SETCC_CARRY) {
13865 CC = Cond.getOperand(0);
13867 SDValue Cmp = Cond.getOperand(1);
13868 unsigned Opc = Cmp.getOpcode();
13869 MVT VT = Op.getSimpleValueType();
13871 bool IllegalFPCMov = false;
13872 if (VT.isFloatingPoint() && !VT.isVector() &&
13873 !isScalarFPTypeInSSEReg(VT)) // FPStack?
13874 IllegalFPCMov = !hasFPCMov(cast<ConstantSDNode>(CC)->getSExtValue());
13876 if ((isX86LogicalCmp(Cmp) && !IllegalFPCMov) ||
13877 Opc == X86ISD::BT) { // FIXME
13881 } else if (CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO ||
13882 CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO ||
13883 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) &&
13884 Cond.getOperand(0).getValueType() != MVT::i8)) {
13885 SDValue LHS = Cond.getOperand(0);
13886 SDValue RHS = Cond.getOperand(1);
13887 unsigned X86Opcode;
13890 switch (CondOpcode) {
13891 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break;
13892 case ISD::SADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break;
13893 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break;
13894 case ISD::SSUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break;
13895 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break;
13896 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break;
13897 default: llvm_unreachable("unexpected overflowing operator");
13899 if (CondOpcode == ISD::UMULO)
13900 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(),
13903 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
13905 SDValue X86Op = DAG.getNode(X86Opcode, DL, VTs, LHS, RHS);
13907 if (CondOpcode == ISD::UMULO)
13908 Cond = X86Op.getValue(2);
13910 Cond = X86Op.getValue(1);
13912 CC = DAG.getConstant(X86Cond, DL, MVT::i8);
13917 // Look pass the truncate if the high bits are known zero.
13918 if (isTruncWithZeroHighBitsInput(Cond, DAG))
13919 Cond = Cond.getOperand(0);
13921 // We know the result of AND is compared against zero. Try to match
13923 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
13924 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, DL, DAG);
13925 if (NewSetCC.getNode()) {
13926 CC = NewSetCC.getOperand(0);
13927 Cond = NewSetCC.getOperand(1);
13934 CC = DAG.getConstant(X86::COND_NE, DL, MVT::i8);
13935 Cond = EmitTest(Cond, X86::COND_NE, DL, DAG);
13938 // a < b ? -1 : 0 -> RES = ~setcc_carry
13939 // a < b ? 0 : -1 -> RES = setcc_carry
13940 // a >= b ? -1 : 0 -> RES = setcc_carry
13941 // a >= b ? 0 : -1 -> RES = ~setcc_carry
13942 if (Cond.getOpcode() == X86ISD::SUB) {
13943 Cond = ConvertCmpIfNecessary(Cond, DAG);
13944 unsigned CondCode = cast<ConstantSDNode>(CC)->getZExtValue();
13946 if ((CondCode == X86::COND_AE || CondCode == X86::COND_B) &&
13947 (isAllOnes(Op1) || isAllOnes(Op2)) && (isZero(Op1) || isZero(Op2))) {
13948 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
13949 DAG.getConstant(X86::COND_B, DL, MVT::i8),
13951 if (isAllOnes(Op1) != (CondCode == X86::COND_B))
13952 return DAG.getNOT(DL, Res, Res.getValueType());
13957 // X86 doesn't have an i8 cmov. If both operands are the result of a truncate
13958 // widen the cmov and push the truncate through. This avoids introducing a new
13959 // branch during isel and doesn't add any extensions.
13960 if (Op.getValueType() == MVT::i8 &&
13961 Op1.getOpcode() == ISD::TRUNCATE && Op2.getOpcode() == ISD::TRUNCATE) {
13962 SDValue T1 = Op1.getOperand(0), T2 = Op2.getOperand(0);
13963 if (T1.getValueType() == T2.getValueType() &&
13964 // Blacklist CopyFromReg to avoid partial register stalls.
13965 T1.getOpcode() != ISD::CopyFromReg && T2.getOpcode()!=ISD::CopyFromReg){
13966 SDVTList VTs = DAG.getVTList(T1.getValueType(), MVT::Glue);
13967 SDValue Cmov = DAG.getNode(X86ISD::CMOV, DL, VTs, T2, T1, CC, Cond);
13968 return DAG.getNode(ISD::TRUNCATE, DL, Op.getValueType(), Cmov);
13972 // X86ISD::CMOV means set the result (which is operand 1) to the RHS if
13973 // condition is true.
13974 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue);
13975 SDValue Ops[] = { Op2, Op1, CC, Cond };
13976 return DAG.getNode(X86ISD::CMOV, DL, VTs, Ops);
13979 static SDValue LowerSIGN_EXTEND_AVX512(SDValue Op,
13980 const X86Subtarget *Subtarget,
13981 SelectionDAG &DAG) {
13982 MVT VT = Op->getSimpleValueType(0);
13983 SDValue In = Op->getOperand(0);
13984 MVT InVT = In.getSimpleValueType();
13985 MVT VTElt = VT.getVectorElementType();
13986 MVT InVTElt = InVT.getVectorElementType();
13990 if ((InVTElt == MVT::i1) &&
13991 (((Subtarget->hasBWI() && Subtarget->hasVLX() &&
13992 VT.getSizeInBits() <= 256 && VTElt.getSizeInBits() <= 16)) ||
13994 ((Subtarget->hasBWI() && VT.is512BitVector() &&
13995 VTElt.getSizeInBits() <= 16)) ||
13997 ((Subtarget->hasDQI() && Subtarget->hasVLX() &&
13998 VT.getSizeInBits() <= 256 && VTElt.getSizeInBits() >= 32)) ||
14000 ((Subtarget->hasDQI() && VT.is512BitVector() &&
14001 VTElt.getSizeInBits() >= 32))))
14002 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
14004 unsigned int NumElts = VT.getVectorNumElements();
14006 if (NumElts != 8 && NumElts != 16 && !Subtarget->hasBWI())
14009 if (VT.is512BitVector() && InVT.getVectorElementType() != MVT::i1) {
14010 if (In.getOpcode() == X86ISD::VSEXT || In.getOpcode() == X86ISD::VZEXT)
14011 return DAG.getNode(In.getOpcode(), dl, VT, In.getOperand(0));
14012 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
14015 assert (InVT.getVectorElementType() == MVT::i1 && "Unexpected vector type");
14016 MVT ExtVT = NumElts == 8 ? MVT::v8i64 : MVT::v16i32;
14018 DAG.getConstant(APInt::getAllOnesValue(ExtVT.getScalarSizeInBits()), dl,
14021 DAG.getConstant(APInt::getNullValue(ExtVT.getScalarSizeInBits()), dl, ExtVT);
14023 SDValue V = DAG.getNode(ISD::VSELECT, dl, ExtVT, In, NegOne, Zero);
14024 if (VT.is512BitVector())
14026 return DAG.getNode(X86ISD::VTRUNC, dl, VT, V);
14029 static SDValue LowerSIGN_EXTEND_VECTOR_INREG(SDValue Op,
14030 const X86Subtarget *Subtarget,
14031 SelectionDAG &DAG) {
14032 SDValue In = Op->getOperand(0);
14033 MVT VT = Op->getSimpleValueType(0);
14034 MVT InVT = In.getSimpleValueType();
14035 assert(VT.getSizeInBits() == InVT.getSizeInBits());
14037 MVT InSVT = InVT.getScalarType();
14038 assert(VT.getScalarType().getScalarSizeInBits() > InSVT.getScalarSizeInBits());
14040 if (VT != MVT::v2i64 && VT != MVT::v4i32 && VT != MVT::v8i16)
14042 if (InSVT != MVT::i32 && InSVT != MVT::i16 && InSVT != MVT::i8)
14047 // SSE41 targets can use the pmovsx* instructions directly.
14048 if (Subtarget->hasSSE41())
14049 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
14051 // pre-SSE41 targets unpack lower lanes and then sign-extend using SRAI.
14055 // As SRAI is only available on i16/i32 types, we expand only up to i32
14056 // and handle i64 separately.
14057 while (CurrVT != VT && CurrVT.getScalarType() != MVT::i32) {
14058 Curr = DAG.getNode(X86ISD::UNPCKL, dl, CurrVT, DAG.getUNDEF(CurrVT), Curr);
14059 MVT CurrSVT = MVT::getIntegerVT(CurrVT.getScalarSizeInBits() * 2);
14060 CurrVT = MVT::getVectorVT(CurrSVT, CurrVT.getVectorNumElements() / 2);
14061 Curr = DAG.getBitcast(CurrVT, Curr);
14064 SDValue SignExt = Curr;
14065 if (CurrVT != InVT) {
14066 unsigned SignExtShift =
14067 CurrVT.getScalarSizeInBits() - InSVT.getScalarSizeInBits();
14068 SignExt = DAG.getNode(X86ISD::VSRAI, dl, CurrVT, Curr,
14069 DAG.getConstant(SignExtShift, dl, MVT::i8));
14075 if (VT == MVT::v2i64 && CurrVT == MVT::v4i32) {
14076 SDValue Sign = DAG.getNode(X86ISD::VSRAI, dl, CurrVT, Curr,
14077 DAG.getConstant(31, dl, MVT::i8));
14078 SDValue Ext = DAG.getVectorShuffle(CurrVT, dl, SignExt, Sign, {0, 4, 1, 5});
14079 return DAG.getBitcast(VT, Ext);
14085 static SDValue LowerSIGN_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
14086 SelectionDAG &DAG) {
14087 MVT VT = Op->getSimpleValueType(0);
14088 SDValue In = Op->getOperand(0);
14089 MVT InVT = In.getSimpleValueType();
14092 if (VT.is512BitVector() || InVT.getVectorElementType() == MVT::i1)
14093 return LowerSIGN_EXTEND_AVX512(Op, Subtarget, DAG);
14095 if ((VT != MVT::v4i64 || InVT != MVT::v4i32) &&
14096 (VT != MVT::v8i32 || InVT != MVT::v8i16) &&
14097 (VT != MVT::v16i16 || InVT != MVT::v16i8))
14100 if (Subtarget->hasInt256())
14101 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
14103 // Optimize vectors in AVX mode
14104 // Sign extend v8i16 to v8i32 and
14107 // Divide input vector into two parts
14108 // for v4i32 the shuffle mask will be { 0, 1, -1, -1} {2, 3, -1, -1}
14109 // use vpmovsx instruction to extend v4i32 -> v2i64; v8i16 -> v4i32
14110 // concat the vectors to original VT
14112 unsigned NumElems = InVT.getVectorNumElements();
14113 SDValue Undef = DAG.getUNDEF(InVT);
14115 SmallVector<int,8> ShufMask1(NumElems, -1);
14116 for (unsigned i = 0; i != NumElems/2; ++i)
14119 SDValue OpLo = DAG.getVectorShuffle(InVT, dl, In, Undef, &ShufMask1[0]);
14121 SmallVector<int,8> ShufMask2(NumElems, -1);
14122 for (unsigned i = 0; i != NumElems/2; ++i)
14123 ShufMask2[i] = i + NumElems/2;
14125 SDValue OpHi = DAG.getVectorShuffle(InVT, dl, In, Undef, &ShufMask2[0]);
14127 MVT HalfVT = MVT::getVectorVT(VT.getScalarType(),
14128 VT.getVectorNumElements()/2);
14130 OpLo = DAG.getNode(X86ISD::VSEXT, dl, HalfVT, OpLo);
14131 OpHi = DAG.getNode(X86ISD::VSEXT, dl, HalfVT, OpHi);
14133 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi);
14136 // Lower vector extended loads using a shuffle. If SSSE3 is not available we
14137 // may emit an illegal shuffle but the expansion is still better than scalar
14138 // code. We generate X86ISD::VSEXT for SEXTLOADs if it's available, otherwise
14139 // we'll emit a shuffle and a arithmetic shift.
14140 // FIXME: Is the expansion actually better than scalar code? It doesn't seem so.
14141 // TODO: It is possible to support ZExt by zeroing the undef values during
14142 // the shuffle phase or after the shuffle.
14143 static SDValue LowerExtendedLoad(SDValue Op, const X86Subtarget *Subtarget,
14144 SelectionDAG &DAG) {
14145 MVT RegVT = Op.getSimpleValueType();
14146 assert(RegVT.isVector() && "We only custom lower vector sext loads.");
14147 assert(RegVT.isInteger() &&
14148 "We only custom lower integer vector sext loads.");
14150 // Nothing useful we can do without SSE2 shuffles.
14151 assert(Subtarget->hasSSE2() && "We only custom lower sext loads with SSE2.");
14153 LoadSDNode *Ld = cast<LoadSDNode>(Op.getNode());
14155 EVT MemVT = Ld->getMemoryVT();
14156 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
14157 unsigned RegSz = RegVT.getSizeInBits();
14159 ISD::LoadExtType Ext = Ld->getExtensionType();
14161 assert((Ext == ISD::EXTLOAD || Ext == ISD::SEXTLOAD)
14162 && "Only anyext and sext are currently implemented.");
14163 assert(MemVT != RegVT && "Cannot extend to the same type");
14164 assert(MemVT.isVector() && "Must load a vector from memory");
14166 unsigned NumElems = RegVT.getVectorNumElements();
14167 unsigned MemSz = MemVT.getSizeInBits();
14168 assert(RegSz > MemSz && "Register size must be greater than the mem size");
14170 if (Ext == ISD::SEXTLOAD && RegSz == 256 && !Subtarget->hasInt256()) {
14171 // The only way in which we have a legal 256-bit vector result but not the
14172 // integer 256-bit operations needed to directly lower a sextload is if we
14173 // have AVX1 but not AVX2. In that case, we can always emit a sextload to
14174 // a 128-bit vector and a normal sign_extend to 256-bits that should get
14175 // correctly legalized. We do this late to allow the canonical form of
14176 // sextload to persist throughout the rest of the DAG combiner -- it wants
14177 // to fold together any extensions it can, and so will fuse a sign_extend
14178 // of an sextload into a sextload targeting a wider value.
14180 if (MemSz == 128) {
14181 // Just switch this to a normal load.
14182 assert(TLI.isTypeLegal(MemVT) && "If the memory type is a 128-bit type, "
14183 "it must be a legal 128-bit vector "
14185 Load = DAG.getLoad(MemVT, dl, Ld->getChain(), Ld->getBasePtr(),
14186 Ld->getPointerInfo(), Ld->isVolatile(), Ld->isNonTemporal(),
14187 Ld->isInvariant(), Ld->getAlignment());
14189 assert(MemSz < 128 &&
14190 "Can't extend a type wider than 128 bits to a 256 bit vector!");
14191 // Do an sext load to a 128-bit vector type. We want to use the same
14192 // number of elements, but elements half as wide. This will end up being
14193 // recursively lowered by this routine, but will succeed as we definitely
14194 // have all the necessary features if we're using AVX1.
14196 EVT::getIntegerVT(*DAG.getContext(), RegVT.getScalarSizeInBits() / 2);
14197 EVT HalfVecVT = EVT::getVectorVT(*DAG.getContext(), HalfEltVT, NumElems);
14199 DAG.getExtLoad(Ext, dl, HalfVecVT, Ld->getChain(), Ld->getBasePtr(),
14200 Ld->getPointerInfo(), MemVT, Ld->isVolatile(),
14201 Ld->isNonTemporal(), Ld->isInvariant(),
14202 Ld->getAlignment());
14205 // Replace chain users with the new chain.
14206 assert(Load->getNumValues() == 2 && "Loads must carry a chain!");
14207 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), Load.getValue(1));
14209 // Finally, do a normal sign-extend to the desired register.
14210 return DAG.getSExtOrTrunc(Load, dl, RegVT);
14213 // All sizes must be a power of two.
14214 assert(isPowerOf2_32(RegSz * MemSz * NumElems) &&
14215 "Non-power-of-two elements are not custom lowered!");
14217 // Attempt to load the original value using scalar loads.
14218 // Find the largest scalar type that divides the total loaded size.
14219 MVT SclrLoadTy = MVT::i8;
14220 for (MVT Tp : MVT::integer_valuetypes()) {
14221 if (TLI.isTypeLegal(Tp) && ((MemSz % Tp.getSizeInBits()) == 0)) {
14226 // On 32bit systems, we can't save 64bit integers. Try bitcasting to F64.
14227 if (TLI.isTypeLegal(MVT::f64) && SclrLoadTy.getSizeInBits() < 64 &&
14229 SclrLoadTy = MVT::f64;
14231 // Calculate the number of scalar loads that we need to perform
14232 // in order to load our vector from memory.
14233 unsigned NumLoads = MemSz / SclrLoadTy.getSizeInBits();
14235 assert((Ext != ISD::SEXTLOAD || NumLoads == 1) &&
14236 "Can only lower sext loads with a single scalar load!");
14238 unsigned loadRegZize = RegSz;
14239 if (Ext == ISD::SEXTLOAD && RegSz >= 256)
14242 // Represent our vector as a sequence of elements which are the
14243 // largest scalar that we can load.
14244 EVT LoadUnitVecVT = EVT::getVectorVT(
14245 *DAG.getContext(), SclrLoadTy, loadRegZize / SclrLoadTy.getSizeInBits());
14247 // Represent the data using the same element type that is stored in
14248 // memory. In practice, we ''widen'' MemVT.
14250 EVT::getVectorVT(*DAG.getContext(), MemVT.getScalarType(),
14251 loadRegZize / MemVT.getScalarType().getSizeInBits());
14253 assert(WideVecVT.getSizeInBits() == LoadUnitVecVT.getSizeInBits() &&
14254 "Invalid vector type");
14256 // We can't shuffle using an illegal type.
14257 assert(TLI.isTypeLegal(WideVecVT) &&
14258 "We only lower types that form legal widened vector types");
14260 SmallVector<SDValue, 8> Chains;
14261 SDValue Ptr = Ld->getBasePtr();
14262 SDValue Increment =
14263 DAG.getConstant(SclrLoadTy.getSizeInBits() / 8, dl, TLI.getPointerTy());
14264 SDValue Res = DAG.getUNDEF(LoadUnitVecVT);
14266 for (unsigned i = 0; i < NumLoads; ++i) {
14267 // Perform a single load.
14268 SDValue ScalarLoad =
14269 DAG.getLoad(SclrLoadTy, dl, Ld->getChain(), Ptr, Ld->getPointerInfo(),
14270 Ld->isVolatile(), Ld->isNonTemporal(), Ld->isInvariant(),
14271 Ld->getAlignment());
14272 Chains.push_back(ScalarLoad.getValue(1));
14273 // Create the first element type using SCALAR_TO_VECTOR in order to avoid
14274 // another round of DAGCombining.
14276 Res = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, LoadUnitVecVT, ScalarLoad);
14278 Res = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, LoadUnitVecVT, Res,
14279 ScalarLoad, DAG.getIntPtrConstant(i, dl));
14281 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
14284 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Chains);
14286 // Bitcast the loaded value to a vector of the original element type, in
14287 // the size of the target vector type.
14288 SDValue SlicedVec = DAG.getBitcast(WideVecVT, Res);
14289 unsigned SizeRatio = RegSz / MemSz;
14291 if (Ext == ISD::SEXTLOAD) {
14292 // If we have SSE4.1, we can directly emit a VSEXT node.
14293 if (Subtarget->hasSSE41()) {
14294 SDValue Sext = DAG.getNode(X86ISD::VSEXT, dl, RegVT, SlicedVec);
14295 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), TF);
14299 // Otherwise we'll shuffle the small elements in the high bits of the
14300 // larger type and perform an arithmetic shift. If the shift is not legal
14301 // it's better to scalarize.
14302 assert(TLI.isOperationLegalOrCustom(ISD::SRA, RegVT) &&
14303 "We can't implement a sext load without an arithmetic right shift!");
14305 // Redistribute the loaded elements into the different locations.
14306 SmallVector<int, 16> ShuffleVec(NumElems * SizeRatio, -1);
14307 for (unsigned i = 0; i != NumElems; ++i)
14308 ShuffleVec[i * SizeRatio + SizeRatio - 1] = i;
14310 SDValue Shuff = DAG.getVectorShuffle(
14311 WideVecVT, dl, SlicedVec, DAG.getUNDEF(WideVecVT), &ShuffleVec[0]);
14313 Shuff = DAG.getBitcast(RegVT, Shuff);
14315 // Build the arithmetic shift.
14316 unsigned Amt = RegVT.getVectorElementType().getSizeInBits() -
14317 MemVT.getVectorElementType().getSizeInBits();
14319 DAG.getNode(ISD::SRA, dl, RegVT, Shuff,
14320 DAG.getConstant(Amt, dl, RegVT));
14322 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), TF);
14326 // Redistribute the loaded elements into the different locations.
14327 SmallVector<int, 16> ShuffleVec(NumElems * SizeRatio, -1);
14328 for (unsigned i = 0; i != NumElems; ++i)
14329 ShuffleVec[i * SizeRatio] = i;
14331 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, SlicedVec,
14332 DAG.getUNDEF(WideVecVT), &ShuffleVec[0]);
14334 // Bitcast to the requested type.
14335 Shuff = DAG.getBitcast(RegVT, Shuff);
14336 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), TF);
14340 // isAndOrOfSingleUseSetCCs - Return true if node is an ISD::AND or
14341 // ISD::OR of two X86ISD::SETCC nodes each of which has no other use apart
14342 // from the AND / OR.
14343 static bool isAndOrOfSetCCs(SDValue Op, unsigned &Opc) {
14344 Opc = Op.getOpcode();
14345 if (Opc != ISD::OR && Opc != ISD::AND)
14347 return (Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
14348 Op.getOperand(0).hasOneUse() &&
14349 Op.getOperand(1).getOpcode() == X86ISD::SETCC &&
14350 Op.getOperand(1).hasOneUse());
14353 // isXor1OfSetCC - Return true if node is an ISD::XOR of a X86ISD::SETCC and
14354 // 1 and that the SETCC node has a single use.
14355 static bool isXor1OfSetCC(SDValue Op) {
14356 if (Op.getOpcode() != ISD::XOR)
14358 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
14359 if (N1C && N1C->getAPIntValue() == 1) {
14360 return Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
14361 Op.getOperand(0).hasOneUse();
14366 SDValue X86TargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) const {
14367 bool addTest = true;
14368 SDValue Chain = Op.getOperand(0);
14369 SDValue Cond = Op.getOperand(1);
14370 SDValue Dest = Op.getOperand(2);
14373 bool Inverted = false;
14375 if (Cond.getOpcode() == ISD::SETCC) {
14376 // Check for setcc([su]{add,sub,mul}o == 0).
14377 if (cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETEQ &&
14378 isa<ConstantSDNode>(Cond.getOperand(1)) &&
14379 cast<ConstantSDNode>(Cond.getOperand(1))->isNullValue() &&
14380 Cond.getOperand(0).getResNo() == 1 &&
14381 (Cond.getOperand(0).getOpcode() == ISD::SADDO ||
14382 Cond.getOperand(0).getOpcode() == ISD::UADDO ||
14383 Cond.getOperand(0).getOpcode() == ISD::SSUBO ||
14384 Cond.getOperand(0).getOpcode() == ISD::USUBO ||
14385 Cond.getOperand(0).getOpcode() == ISD::SMULO ||
14386 Cond.getOperand(0).getOpcode() == ISD::UMULO)) {
14388 Cond = Cond.getOperand(0);
14390 SDValue NewCond = LowerSETCC(Cond, DAG);
14391 if (NewCond.getNode())
14396 // FIXME: LowerXALUO doesn't handle these!!
14397 else if (Cond.getOpcode() == X86ISD::ADD ||
14398 Cond.getOpcode() == X86ISD::SUB ||
14399 Cond.getOpcode() == X86ISD::SMUL ||
14400 Cond.getOpcode() == X86ISD::UMUL)
14401 Cond = LowerXALUO(Cond, DAG);
14404 // Look pass (and (setcc_carry (cmp ...)), 1).
14405 if (Cond.getOpcode() == ISD::AND &&
14406 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
14407 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
14408 if (C && C->getAPIntValue() == 1)
14409 Cond = Cond.getOperand(0);
14412 // If condition flag is set by a X86ISD::CMP, then use it as the condition
14413 // setting operand in place of the X86ISD::SETCC.
14414 unsigned CondOpcode = Cond.getOpcode();
14415 if (CondOpcode == X86ISD::SETCC ||
14416 CondOpcode == X86ISD::SETCC_CARRY) {
14417 CC = Cond.getOperand(0);
14419 SDValue Cmp = Cond.getOperand(1);
14420 unsigned Opc = Cmp.getOpcode();
14421 // FIXME: WHY THE SPECIAL CASING OF LogicalCmp??
14422 if (isX86LogicalCmp(Cmp) || Opc == X86ISD::BT) {
14426 switch (cast<ConstantSDNode>(CC)->getZExtValue()) {
14430 // These can only come from an arithmetic instruction with overflow,
14431 // e.g. SADDO, UADDO.
14432 Cond = Cond.getNode()->getOperand(1);
14438 CondOpcode = Cond.getOpcode();
14439 if (CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO ||
14440 CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO ||
14441 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) &&
14442 Cond.getOperand(0).getValueType() != MVT::i8)) {
14443 SDValue LHS = Cond.getOperand(0);
14444 SDValue RHS = Cond.getOperand(1);
14445 unsigned X86Opcode;
14448 // Keep this in sync with LowerXALUO, otherwise we might create redundant
14449 // instructions that can't be removed afterwards (i.e. X86ISD::ADD and
14451 switch (CondOpcode) {
14452 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break;
14454 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
14456 X86Opcode = X86ISD::INC; X86Cond = X86::COND_O;
14459 X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break;
14460 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break;
14462 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
14464 X86Opcode = X86ISD::DEC; X86Cond = X86::COND_O;
14467 X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break;
14468 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break;
14469 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break;
14470 default: llvm_unreachable("unexpected overflowing operator");
14473 X86Cond = X86::GetOppositeBranchCondition((X86::CondCode)X86Cond);
14474 if (CondOpcode == ISD::UMULO)
14475 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(),
14478 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
14480 SDValue X86Op = DAG.getNode(X86Opcode, dl, VTs, LHS, RHS);
14482 if (CondOpcode == ISD::UMULO)
14483 Cond = X86Op.getValue(2);
14485 Cond = X86Op.getValue(1);
14487 CC = DAG.getConstant(X86Cond, dl, MVT::i8);
14491 if (Cond.hasOneUse() && isAndOrOfSetCCs(Cond, CondOpc)) {
14492 SDValue Cmp = Cond.getOperand(0).getOperand(1);
14493 if (CondOpc == ISD::OR) {
14494 // Also, recognize the pattern generated by an FCMP_UNE. We can emit
14495 // two branches instead of an explicit OR instruction with a
14497 if (Cmp == Cond.getOperand(1).getOperand(1) &&
14498 isX86LogicalCmp(Cmp)) {
14499 CC = Cond.getOperand(0).getOperand(0);
14500 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
14501 Chain, Dest, CC, Cmp);
14502 CC = Cond.getOperand(1).getOperand(0);
14506 } else { // ISD::AND
14507 // Also, recognize the pattern generated by an FCMP_OEQ. We can emit
14508 // two branches instead of an explicit AND instruction with a
14509 // separate test. However, we only do this if this block doesn't
14510 // have a fall-through edge, because this requires an explicit
14511 // jmp when the condition is false.
14512 if (Cmp == Cond.getOperand(1).getOperand(1) &&
14513 isX86LogicalCmp(Cmp) &&
14514 Op.getNode()->hasOneUse()) {
14515 X86::CondCode CCode =
14516 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
14517 CCode = X86::GetOppositeBranchCondition(CCode);
14518 CC = DAG.getConstant(CCode, dl, MVT::i8);
14519 SDNode *User = *Op.getNode()->use_begin();
14520 // Look for an unconditional branch following this conditional branch.
14521 // We need this because we need to reverse the successors in order
14522 // to implement FCMP_OEQ.
14523 if (User->getOpcode() == ISD::BR) {
14524 SDValue FalseBB = User->getOperand(1);
14526 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
14527 assert(NewBR == User);
14531 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
14532 Chain, Dest, CC, Cmp);
14533 X86::CondCode CCode =
14534 (X86::CondCode)Cond.getOperand(1).getConstantOperandVal(0);
14535 CCode = X86::GetOppositeBranchCondition(CCode);
14536 CC = DAG.getConstant(CCode, dl, MVT::i8);
14542 } else if (Cond.hasOneUse() && isXor1OfSetCC(Cond)) {
14543 // Recognize for xorb (setcc), 1 patterns. The xor inverts the condition.
14544 // It should be transformed during dag combiner except when the condition
14545 // is set by a arithmetics with overflow node.
14546 X86::CondCode CCode =
14547 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
14548 CCode = X86::GetOppositeBranchCondition(CCode);
14549 CC = DAG.getConstant(CCode, dl, MVT::i8);
14550 Cond = Cond.getOperand(0).getOperand(1);
14552 } else if (Cond.getOpcode() == ISD::SETCC &&
14553 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETOEQ) {
14554 // For FCMP_OEQ, we can emit
14555 // two branches instead of an explicit AND instruction with a
14556 // separate test. However, we only do this if this block doesn't
14557 // have a fall-through edge, because this requires an explicit
14558 // jmp when the condition is false.
14559 if (Op.getNode()->hasOneUse()) {
14560 SDNode *User = *Op.getNode()->use_begin();
14561 // Look for an unconditional branch following this conditional branch.
14562 // We need this because we need to reverse the successors in order
14563 // to implement FCMP_OEQ.
14564 if (User->getOpcode() == ISD::BR) {
14565 SDValue FalseBB = User->getOperand(1);
14567 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
14568 assert(NewBR == User);
14572 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
14573 Cond.getOperand(0), Cond.getOperand(1));
14574 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
14575 CC = DAG.getConstant(X86::COND_NE, dl, MVT::i8);
14576 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
14577 Chain, Dest, CC, Cmp);
14578 CC = DAG.getConstant(X86::COND_P, dl, MVT::i8);
14583 } else if (Cond.getOpcode() == ISD::SETCC &&
14584 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETUNE) {
14585 // For FCMP_UNE, we can emit
14586 // two branches instead of an explicit AND instruction with a
14587 // separate test. However, we only do this if this block doesn't
14588 // have a fall-through edge, because this requires an explicit
14589 // jmp when the condition is false.
14590 if (Op.getNode()->hasOneUse()) {
14591 SDNode *User = *Op.getNode()->use_begin();
14592 // Look for an unconditional branch following this conditional branch.
14593 // We need this because we need to reverse the successors in order
14594 // to implement FCMP_UNE.
14595 if (User->getOpcode() == ISD::BR) {
14596 SDValue FalseBB = User->getOperand(1);
14598 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
14599 assert(NewBR == User);
14602 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
14603 Cond.getOperand(0), Cond.getOperand(1));
14604 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
14605 CC = DAG.getConstant(X86::COND_NE, dl, MVT::i8);
14606 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
14607 Chain, Dest, CC, Cmp);
14608 CC = DAG.getConstant(X86::COND_NP, dl, MVT::i8);
14618 // Look pass the truncate if the high bits are known zero.
14619 if (isTruncWithZeroHighBitsInput(Cond, DAG))
14620 Cond = Cond.getOperand(0);
14622 // We know the result of AND is compared against zero. Try to match
14624 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
14625 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, dl, DAG);
14626 if (NewSetCC.getNode()) {
14627 CC = NewSetCC.getOperand(0);
14628 Cond = NewSetCC.getOperand(1);
14635 X86::CondCode X86Cond = Inverted ? X86::COND_E : X86::COND_NE;
14636 CC = DAG.getConstant(X86Cond, dl, MVT::i8);
14637 Cond = EmitTest(Cond, X86Cond, dl, DAG);
14639 Cond = ConvertCmpIfNecessary(Cond, DAG);
14640 return DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
14641 Chain, Dest, CC, Cond);
14644 // Lower dynamic stack allocation to _alloca call for Cygwin/Mingw targets.
14645 // Calls to _alloca are needed to probe the stack when allocating more than 4k
14646 // bytes in one go. Touching the stack at 4K increments is necessary to ensure
14647 // that the guard pages used by the OS virtual memory manager are allocated in
14648 // correct sequence.
14650 X86TargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
14651 SelectionDAG &DAG) const {
14652 MachineFunction &MF = DAG.getMachineFunction();
14653 bool SplitStack = MF.shouldSplitStack();
14654 bool Lower = (Subtarget->isOSWindows() && !Subtarget->isTargetMachO()) ||
14659 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
14660 SDNode* Node = Op.getNode();
14662 unsigned SPReg = TLI.getStackPointerRegisterToSaveRestore();
14663 assert(SPReg && "Target cannot require DYNAMIC_STACKALLOC expansion and"
14664 " not tell us which reg is the stack pointer!");
14665 EVT VT = Node->getValueType(0);
14666 SDValue Tmp1 = SDValue(Node, 0);
14667 SDValue Tmp2 = SDValue(Node, 1);
14668 SDValue Tmp3 = Node->getOperand(2);
14669 SDValue Chain = Tmp1.getOperand(0);
14671 // Chain the dynamic stack allocation so that it doesn't modify the stack
14672 // pointer when other instructions are using the stack.
14673 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(0, dl, true),
14676 SDValue Size = Tmp2.getOperand(1);
14677 SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, VT);
14678 Chain = SP.getValue(1);
14679 unsigned Align = cast<ConstantSDNode>(Tmp3)->getZExtValue();
14680 const TargetFrameLowering &TFI = *Subtarget->getFrameLowering();
14681 unsigned StackAlign = TFI.getStackAlignment();
14682 Tmp1 = DAG.getNode(ISD::SUB, dl, VT, SP, Size); // Value
14683 if (Align > StackAlign)
14684 Tmp1 = DAG.getNode(ISD::AND, dl, VT, Tmp1,
14685 DAG.getConstant(-(uint64_t)Align, dl, VT));
14686 Chain = DAG.getCopyToReg(Chain, dl, SPReg, Tmp1); // Output chain
14688 Tmp2 = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(0, dl, true),
14689 DAG.getIntPtrConstant(0, dl, true), SDValue(),
14692 SDValue Ops[2] = { Tmp1, Tmp2 };
14693 return DAG.getMergeValues(Ops, dl);
14697 SDValue Chain = Op.getOperand(0);
14698 SDValue Size = Op.getOperand(1);
14699 unsigned Align = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue();
14700 EVT VT = Op.getNode()->getValueType(0);
14702 bool Is64Bit = Subtarget->is64Bit();
14703 EVT SPTy = getPointerTy();
14706 MachineRegisterInfo &MRI = MF.getRegInfo();
14709 // The 64 bit implementation of segmented stacks needs to clobber both r10
14710 // r11. This makes it impossible to use it along with nested parameters.
14711 const Function *F = MF.getFunction();
14713 for (Function::const_arg_iterator I = F->arg_begin(), E = F->arg_end();
14715 if (I->hasNestAttr())
14716 report_fatal_error("Cannot use segmented stacks with functions that "
14717 "have nested arguments.");
14720 const TargetRegisterClass *AddrRegClass =
14721 getRegClassFor(getPointerTy());
14722 unsigned Vreg = MRI.createVirtualRegister(AddrRegClass);
14723 Chain = DAG.getCopyToReg(Chain, dl, Vreg, Size);
14724 SDValue Value = DAG.getNode(X86ISD::SEG_ALLOCA, dl, SPTy, Chain,
14725 DAG.getRegister(Vreg, SPTy));
14726 SDValue Ops1[2] = { Value, Chain };
14727 return DAG.getMergeValues(Ops1, dl);
14730 const unsigned Reg = (Subtarget->isTarget64BitLP64() ? X86::RAX : X86::EAX);
14732 Chain = DAG.getCopyToReg(Chain, dl, Reg, Size, Flag);
14733 Flag = Chain.getValue(1);
14734 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
14736 Chain = DAG.getNode(X86ISD::WIN_ALLOCA, dl, NodeTys, Chain, Flag);
14738 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
14739 unsigned SPReg = RegInfo->getStackRegister();
14740 SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, SPTy);
14741 Chain = SP.getValue(1);
14744 SP = DAG.getNode(ISD::AND, dl, VT, SP.getValue(0),
14745 DAG.getConstant(-(uint64_t)Align, dl, VT));
14746 Chain = DAG.getCopyToReg(Chain, dl, SPReg, SP);
14749 SDValue Ops1[2] = { SP, Chain };
14750 return DAG.getMergeValues(Ops1, dl);
14754 SDValue X86TargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const {
14755 MachineFunction &MF = DAG.getMachineFunction();
14756 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
14758 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
14761 if (!Subtarget->is64Bit() || Subtarget->isTargetWin64()) {
14762 // vastart just stores the address of the VarArgsFrameIndex slot into the
14763 // memory location argument.
14764 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
14766 return DAG.getStore(Op.getOperand(0), DL, FR, Op.getOperand(1),
14767 MachinePointerInfo(SV), false, false, 0);
14771 // gp_offset (0 - 6 * 8)
14772 // fp_offset (48 - 48 + 8 * 16)
14773 // overflow_arg_area (point to parameters coming in memory).
14775 SmallVector<SDValue, 8> MemOps;
14776 SDValue FIN = Op.getOperand(1);
14778 SDValue Store = DAG.getStore(Op.getOperand(0), DL,
14779 DAG.getConstant(FuncInfo->getVarArgsGPOffset(),
14781 FIN, MachinePointerInfo(SV), false, false, 0);
14782 MemOps.push_back(Store);
14785 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
14786 FIN, DAG.getIntPtrConstant(4, DL));
14787 Store = DAG.getStore(Op.getOperand(0), DL,
14788 DAG.getConstant(FuncInfo->getVarArgsFPOffset(), DL,
14790 FIN, MachinePointerInfo(SV, 4), false, false, 0);
14791 MemOps.push_back(Store);
14793 // Store ptr to overflow_arg_area
14794 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
14795 FIN, DAG.getIntPtrConstant(4, DL));
14796 SDValue OVFIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
14798 Store = DAG.getStore(Op.getOperand(0), DL, OVFIN, FIN,
14799 MachinePointerInfo(SV, 8),
14801 MemOps.push_back(Store);
14803 // Store ptr to reg_save_area.
14804 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
14805 FIN, DAG.getIntPtrConstant(8, DL));
14806 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
14808 Store = DAG.getStore(Op.getOperand(0), DL, RSFIN, FIN,
14809 MachinePointerInfo(SV, 16), false, false, 0);
14810 MemOps.push_back(Store);
14811 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOps);
14814 SDValue X86TargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG) const {
14815 assert(Subtarget->is64Bit() &&
14816 "LowerVAARG only handles 64-bit va_arg!");
14817 assert((Subtarget->isTargetLinux() ||
14818 Subtarget->isTargetDarwin()) &&
14819 "Unhandled target in LowerVAARG");
14820 assert(Op.getNode()->getNumOperands() == 4);
14821 SDValue Chain = Op.getOperand(0);
14822 SDValue SrcPtr = Op.getOperand(1);
14823 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
14824 unsigned Align = Op.getConstantOperandVal(3);
14827 EVT ArgVT = Op.getNode()->getValueType(0);
14828 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
14829 uint32_t ArgSize = getDataLayout()->getTypeAllocSize(ArgTy);
14832 // Decide which area this value should be read from.
14833 // TODO: Implement the AMD64 ABI in its entirety. This simple
14834 // selection mechanism works only for the basic types.
14835 if (ArgVT == MVT::f80) {
14836 llvm_unreachable("va_arg for f80 not yet implemented");
14837 } else if (ArgVT.isFloatingPoint() && ArgSize <= 16 /*bytes*/) {
14838 ArgMode = 2; // Argument passed in XMM register. Use fp_offset.
14839 } else if (ArgVT.isInteger() && ArgSize <= 32 /*bytes*/) {
14840 ArgMode = 1; // Argument passed in GPR64 register(s). Use gp_offset.
14842 llvm_unreachable("Unhandled argument type in LowerVAARG");
14845 if (ArgMode == 2) {
14846 // Sanity Check: Make sure using fp_offset makes sense.
14847 assert(!Subtarget->useSoftFloat() &&
14848 !(DAG.getMachineFunction().getFunction()->hasFnAttribute(
14849 Attribute::NoImplicitFloat)) &&
14850 Subtarget->hasSSE1());
14853 // Insert VAARG_64 node into the DAG
14854 // VAARG_64 returns two values: Variable Argument Address, Chain
14855 SDValue InstOps[] = {Chain, SrcPtr, DAG.getConstant(ArgSize, dl, MVT::i32),
14856 DAG.getConstant(ArgMode, dl, MVT::i8),
14857 DAG.getConstant(Align, dl, MVT::i32)};
14858 SDVTList VTs = DAG.getVTList(getPointerTy(), MVT::Other);
14859 SDValue VAARG = DAG.getMemIntrinsicNode(X86ISD::VAARG_64, dl,
14860 VTs, InstOps, MVT::i64,
14861 MachinePointerInfo(SV),
14863 /*Volatile=*/false,
14865 /*WriteMem=*/true);
14866 Chain = VAARG.getValue(1);
14868 // Load the next argument and return it
14869 return DAG.getLoad(ArgVT, dl,
14872 MachinePointerInfo(),
14873 false, false, false, 0);
14876 static SDValue LowerVACOPY(SDValue Op, const X86Subtarget *Subtarget,
14877 SelectionDAG &DAG) {
14878 // X86-64 va_list is a struct { i32, i32, i8*, i8* }.
14879 assert(Subtarget->is64Bit() && "This code only handles 64-bit va_copy!");
14880 SDValue Chain = Op.getOperand(0);
14881 SDValue DstPtr = Op.getOperand(1);
14882 SDValue SrcPtr = Op.getOperand(2);
14883 const Value *DstSV = cast<SrcValueSDNode>(Op.getOperand(3))->getValue();
14884 const Value *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
14887 return DAG.getMemcpy(Chain, DL, DstPtr, SrcPtr,
14888 DAG.getIntPtrConstant(24, DL), 8, /*isVolatile*/false,
14890 MachinePointerInfo(DstSV), MachinePointerInfo(SrcSV));
14893 // getTargetVShiftByConstNode - Handle vector element shifts where the shift
14894 // amount is a constant. Takes immediate version of shift as input.
14895 static SDValue getTargetVShiftByConstNode(unsigned Opc, SDLoc dl, MVT VT,
14896 SDValue SrcOp, uint64_t ShiftAmt,
14897 SelectionDAG &DAG) {
14898 MVT ElementType = VT.getVectorElementType();
14900 // Fold this packed shift into its first operand if ShiftAmt is 0.
14904 // Check for ShiftAmt >= element width
14905 if (ShiftAmt >= ElementType.getSizeInBits()) {
14906 if (Opc == X86ISD::VSRAI)
14907 ShiftAmt = ElementType.getSizeInBits() - 1;
14909 return DAG.getConstant(0, dl, VT);
14912 assert((Opc == X86ISD::VSHLI || Opc == X86ISD::VSRLI || Opc == X86ISD::VSRAI)
14913 && "Unknown target vector shift-by-constant node");
14915 // Fold this packed vector shift into a build vector if SrcOp is a
14916 // vector of Constants or UNDEFs, and SrcOp valuetype is the same as VT.
14917 if (VT == SrcOp.getSimpleValueType() &&
14918 ISD::isBuildVectorOfConstantSDNodes(SrcOp.getNode())) {
14919 SmallVector<SDValue, 8> Elts;
14920 unsigned NumElts = SrcOp->getNumOperands();
14921 ConstantSDNode *ND;
14924 default: llvm_unreachable(nullptr);
14925 case X86ISD::VSHLI:
14926 for (unsigned i=0; i!=NumElts; ++i) {
14927 SDValue CurrentOp = SrcOp->getOperand(i);
14928 if (CurrentOp->getOpcode() == ISD::UNDEF) {
14929 Elts.push_back(CurrentOp);
14932 ND = cast<ConstantSDNode>(CurrentOp);
14933 const APInt &C = ND->getAPIntValue();
14934 Elts.push_back(DAG.getConstant(C.shl(ShiftAmt), dl, ElementType));
14937 case X86ISD::VSRLI:
14938 for (unsigned i=0; i!=NumElts; ++i) {
14939 SDValue CurrentOp = SrcOp->getOperand(i);
14940 if (CurrentOp->getOpcode() == ISD::UNDEF) {
14941 Elts.push_back(CurrentOp);
14944 ND = cast<ConstantSDNode>(CurrentOp);
14945 const APInt &C = ND->getAPIntValue();
14946 Elts.push_back(DAG.getConstant(C.lshr(ShiftAmt), dl, ElementType));
14949 case X86ISD::VSRAI:
14950 for (unsigned i=0; i!=NumElts; ++i) {
14951 SDValue CurrentOp = SrcOp->getOperand(i);
14952 if (CurrentOp->getOpcode() == ISD::UNDEF) {
14953 Elts.push_back(CurrentOp);
14956 ND = cast<ConstantSDNode>(CurrentOp);
14957 const APInt &C = ND->getAPIntValue();
14958 Elts.push_back(DAG.getConstant(C.ashr(ShiftAmt), dl, ElementType));
14963 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Elts);
14966 return DAG.getNode(Opc, dl, VT, SrcOp,
14967 DAG.getConstant(ShiftAmt, dl, MVT::i8));
14970 // getTargetVShiftNode - Handle vector element shifts where the shift amount
14971 // may or may not be a constant. Takes immediate version of shift as input.
14972 static SDValue getTargetVShiftNode(unsigned Opc, SDLoc dl, MVT VT,
14973 SDValue SrcOp, SDValue ShAmt,
14974 SelectionDAG &DAG) {
14975 MVT SVT = ShAmt.getSimpleValueType();
14976 assert((SVT == MVT::i32 || SVT == MVT::i64) && "Unexpected value type!");
14978 // Catch shift-by-constant.
14979 if (ConstantSDNode *CShAmt = dyn_cast<ConstantSDNode>(ShAmt))
14980 return getTargetVShiftByConstNode(Opc, dl, VT, SrcOp,
14981 CShAmt->getZExtValue(), DAG);
14983 // Change opcode to non-immediate version
14985 default: llvm_unreachable("Unknown target vector shift node");
14986 case X86ISD::VSHLI: Opc = X86ISD::VSHL; break;
14987 case X86ISD::VSRLI: Opc = X86ISD::VSRL; break;
14988 case X86ISD::VSRAI: Opc = X86ISD::VSRA; break;
14991 const X86Subtarget &Subtarget =
14992 static_cast<const X86Subtarget &>(DAG.getSubtarget());
14993 if (Subtarget.hasSSE41() && ShAmt.getOpcode() == ISD::ZERO_EXTEND &&
14994 ShAmt.getOperand(0).getSimpleValueType() == MVT::i16) {
14995 // Let the shuffle legalizer expand this shift amount node.
14996 SDValue Op0 = ShAmt.getOperand(0);
14997 Op0 = DAG.getNode(ISD::SCALAR_TO_VECTOR, SDLoc(Op0), MVT::v8i16, Op0);
14998 ShAmt = getShuffleVectorZeroOrUndef(Op0, 0, true, &Subtarget, DAG);
15000 // Need to build a vector containing shift amount.
15001 // SSE/AVX packed shifts only use the lower 64-bit of the shift count.
15002 SmallVector<SDValue, 4> ShOps;
15003 ShOps.push_back(ShAmt);
15004 if (SVT == MVT::i32) {
15005 ShOps.push_back(DAG.getConstant(0, dl, SVT));
15006 ShOps.push_back(DAG.getUNDEF(SVT));
15008 ShOps.push_back(DAG.getUNDEF(SVT));
15010 MVT BVT = SVT == MVT::i32 ? MVT::v4i32 : MVT::v2i64;
15011 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, BVT, ShOps);
15014 // The return type has to be a 128-bit type with the same element
15015 // type as the input type.
15016 MVT EltVT = VT.getVectorElementType();
15017 EVT ShVT = MVT::getVectorVT(EltVT, 128/EltVT.getSizeInBits());
15019 ShAmt = DAG.getBitcast(ShVT, ShAmt);
15020 return DAG.getNode(Opc, dl, VT, SrcOp, ShAmt);
15023 /// \brief Return (and \p Op, \p Mask) for compare instructions or
15024 /// (vselect \p Mask, \p Op, \p PreservedSrc) for others along with the
15025 /// necessary casting for \p Mask when lowering masking intrinsics.
15026 static SDValue getVectorMaskingNode(SDValue Op, SDValue Mask,
15027 SDValue PreservedSrc,
15028 const X86Subtarget *Subtarget,
15029 SelectionDAG &DAG) {
15030 EVT VT = Op.getValueType();
15031 EVT MaskVT = EVT::getVectorVT(*DAG.getContext(),
15032 MVT::i1, VT.getVectorNumElements());
15033 EVT BitcastVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
15034 Mask.getValueType().getSizeInBits());
15037 assert(MaskVT.isSimple() && "invalid mask type");
15039 if (isAllOnes(Mask))
15042 // In case when MaskVT equals v2i1 or v4i1, low 2 or 4 elements
15043 // are extracted by EXTRACT_SUBVECTOR.
15044 SDValue VMask = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MaskVT,
15045 DAG.getBitcast(BitcastVT, Mask),
15046 DAG.getIntPtrConstant(0, dl));
15048 switch (Op.getOpcode()) {
15050 case X86ISD::PCMPEQM:
15051 case X86ISD::PCMPGTM:
15053 case X86ISD::CMPMU:
15054 return DAG.getNode(ISD::AND, dl, VT, Op, VMask);
15056 if (PreservedSrc.getOpcode() == ISD::UNDEF)
15057 PreservedSrc = getZeroVector(VT, Subtarget, DAG, dl);
15058 return DAG.getNode(ISD::VSELECT, dl, VT, VMask, Op, PreservedSrc);
15061 /// \brief Creates an SDNode for a predicated scalar operation.
15062 /// \returns (X86vselect \p Mask, \p Op, \p PreservedSrc).
15063 /// The mask is comming as MVT::i8 and it should be truncated
15064 /// to MVT::i1 while lowering masking intrinsics.
15065 /// The main difference between ScalarMaskingNode and VectorMaskingNode is using
15066 /// "X86select" instead of "vselect". We just can't create the "vselect" node for
15067 /// a scalar instruction.
15068 static SDValue getScalarMaskingNode(SDValue Op, SDValue Mask,
15069 SDValue PreservedSrc,
15070 const X86Subtarget *Subtarget,
15071 SelectionDAG &DAG) {
15072 if (isAllOnes(Mask))
15075 EVT VT = Op.getValueType();
15077 // The mask should be of type MVT::i1
15078 SDValue IMask = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, Mask);
15080 if (PreservedSrc.getOpcode() == ISD::UNDEF)
15081 PreservedSrc = getZeroVector(VT, Subtarget, DAG, dl);
15082 return DAG.getNode(X86ISD::SELECT, dl, VT, IMask, Op, PreservedSrc);
15085 static SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, const X86Subtarget *Subtarget,
15086 SelectionDAG &DAG) {
15088 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
15089 EVT VT = Op.getValueType();
15090 const IntrinsicData* IntrData = getIntrinsicWithoutChain(IntNo);
15092 switch(IntrData->Type) {
15093 case INTR_TYPE_1OP:
15094 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1));
15095 case INTR_TYPE_2OP:
15096 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1),
15098 case INTR_TYPE_3OP:
15099 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1),
15100 Op.getOperand(2), Op.getOperand(3));
15101 case INTR_TYPE_1OP_MASK_RM: {
15102 SDValue Src = Op.getOperand(1);
15103 SDValue PassThru = Op.getOperand(2);
15104 SDValue Mask = Op.getOperand(3);
15105 SDValue RoundingMode;
15106 if (Op.getNumOperands() == 4)
15107 RoundingMode = DAG.getConstant(X86::STATIC_ROUNDING::CUR_DIRECTION, dl, MVT::i32);
15109 RoundingMode = Op.getOperand(4);
15110 unsigned IntrWithRoundingModeOpcode = IntrData->Opc1;
15111 if (IntrWithRoundingModeOpcode != 0) {
15112 unsigned Round = cast<ConstantSDNode>(RoundingMode)->getZExtValue();
15113 if (Round != X86::STATIC_ROUNDING::CUR_DIRECTION)
15114 return getVectorMaskingNode(DAG.getNode(IntrWithRoundingModeOpcode,
15115 dl, Op.getValueType(), Src, RoundingMode),
15116 Mask, PassThru, Subtarget, DAG);
15118 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT, Src,
15120 Mask, PassThru, Subtarget, DAG);
15122 case INTR_TYPE_1OP_MASK: {
15123 SDValue Src = Op.getOperand(1);
15124 SDValue Passthru = Op.getOperand(2);
15125 SDValue Mask = Op.getOperand(3);
15126 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT, Src),
15127 Mask, Passthru, Subtarget, DAG);
15129 case INTR_TYPE_SCALAR_MASK_RM: {
15130 SDValue Src1 = Op.getOperand(1);
15131 SDValue Src2 = Op.getOperand(2);
15132 SDValue Src0 = Op.getOperand(3);
15133 SDValue Mask = Op.getOperand(4);
15134 // There are 2 kinds of intrinsics in this group:
15135 // (1) With supress-all-exceptions (sae) or rounding mode- 6 operands
15136 // (2) With rounding mode and sae - 7 operands.
15137 if (Op.getNumOperands() == 6) {
15138 SDValue Sae = Op.getOperand(5);
15139 unsigned Opc = IntrData->Opc1 ? IntrData->Opc1 : IntrData->Opc0;
15140 return getScalarMaskingNode(DAG.getNode(Opc, dl, VT, Src1, Src2,
15142 Mask, Src0, Subtarget, DAG);
15144 assert(Op.getNumOperands() == 7 && "Unexpected intrinsic form");
15145 SDValue RoundingMode = Op.getOperand(5);
15146 SDValue Sae = Op.getOperand(6);
15147 return getScalarMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT, Src1, Src2,
15148 RoundingMode, Sae),
15149 Mask, Src0, Subtarget, DAG);
15151 case INTR_TYPE_2OP_MASK: {
15152 SDValue Src1 = Op.getOperand(1);
15153 SDValue Src2 = Op.getOperand(2);
15154 SDValue PassThru = Op.getOperand(3);
15155 SDValue Mask = Op.getOperand(4);
15156 // We specify 2 possible opcodes for intrinsics with rounding modes.
15157 // First, we check if the intrinsic may have non-default rounding mode,
15158 // (IntrData->Opc1 != 0), then we check the rounding mode operand.
15159 unsigned IntrWithRoundingModeOpcode = IntrData->Opc1;
15160 if (IntrWithRoundingModeOpcode != 0) {
15161 SDValue Rnd = Op.getOperand(5);
15162 unsigned Round = cast<ConstantSDNode>(Rnd)->getZExtValue();
15163 if (Round != X86::STATIC_ROUNDING::CUR_DIRECTION) {
15164 return getVectorMaskingNode(DAG.getNode(IntrWithRoundingModeOpcode,
15165 dl, Op.getValueType(),
15167 Mask, PassThru, Subtarget, DAG);
15170 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT,
15172 Mask, PassThru, Subtarget, DAG);
15174 case INTR_TYPE_3OP_MASK: {
15175 SDValue Src1 = Op.getOperand(1);
15176 SDValue Src2 = Op.getOperand(2);
15177 SDValue Src3 = Op.getOperand(3);
15178 SDValue PassThru = Op.getOperand(4);
15179 SDValue Mask = Op.getOperand(5);
15180 // We specify 2 possible opcodes for intrinsics with rounding modes.
15181 // First, we check if the intrinsic may have non-default rounding mode,
15182 // (IntrData->Opc1 != 0), then we check the rounding mode operand.
15183 unsigned IntrWithRoundingModeOpcode = IntrData->Opc1;
15184 if (IntrWithRoundingModeOpcode != 0) {
15185 SDValue Rnd = Op.getOperand(6);
15186 unsigned Round = cast<ConstantSDNode>(Rnd)->getZExtValue();
15187 if (Round != X86::STATIC_ROUNDING::CUR_DIRECTION) {
15188 return getVectorMaskingNode(DAG.getNode(IntrWithRoundingModeOpcode,
15189 dl, Op.getValueType(),
15190 Src1, Src2, Src3, Rnd),
15191 Mask, PassThru, Subtarget, DAG);
15194 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT,
15196 Mask, PassThru, Subtarget, DAG);
15198 case FMA_OP_MASK: {
15199 SDValue Src1 = Op.getOperand(1);
15200 SDValue Src2 = Op.getOperand(2);
15201 SDValue Src3 = Op.getOperand(3);
15202 SDValue Mask = Op.getOperand(4);
15203 // We specify 2 possible opcodes for intrinsics with rounding modes.
15204 // First, we check if the intrinsic may have non-default rounding mode,
15205 // (IntrData->Opc1 != 0), then we check the rounding mode operand.
15206 unsigned IntrWithRoundingModeOpcode = IntrData->Opc1;
15207 if (IntrWithRoundingModeOpcode != 0) {
15208 SDValue Rnd = Op.getOperand(5);
15209 if (cast<ConstantSDNode>(Rnd)->getZExtValue() !=
15210 X86::STATIC_ROUNDING::CUR_DIRECTION)
15211 return getVectorMaskingNode(DAG.getNode(IntrWithRoundingModeOpcode,
15212 dl, Op.getValueType(),
15213 Src1, Src2, Src3, Rnd),
15214 Mask, Src1, Subtarget, DAG);
15216 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0,
15217 dl, Op.getValueType(),
15219 Mask, Src1, Subtarget, DAG);
15222 case CMP_MASK_CC: {
15223 // Comparison intrinsics with masks.
15224 // Example of transformation:
15225 // (i8 (int_x86_avx512_mask_pcmpeq_q_128
15226 // (v2i64 %a), (v2i64 %b), (i8 %mask))) ->
15228 // (v8i1 (insert_subvector undef,
15229 // (v2i1 (and (PCMPEQM %a, %b),
15230 // (extract_subvector
15231 // (v8i1 (bitcast %mask)), 0))), 0))))
15232 EVT VT = Op.getOperand(1).getValueType();
15233 EVT MaskVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
15234 VT.getVectorNumElements());
15235 SDValue Mask = Op.getOperand((IntrData->Type == CMP_MASK_CC) ? 4 : 3);
15236 EVT BitcastVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
15237 Mask.getValueType().getSizeInBits());
15239 if (IntrData->Type == CMP_MASK_CC) {
15240 SDValue CC = Op.getOperand(3);
15241 CC = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, CC);
15242 // We specify 2 possible opcodes for intrinsics with rounding modes.
15243 // First, we check if the intrinsic may have non-default rounding mode,
15244 // (IntrData->Opc1 != 0), then we check the rounding mode operand.
15245 if (IntrData->Opc1 != 0) {
15246 SDValue Rnd = Op.getOperand(5);
15247 if (cast<ConstantSDNode>(Rnd)->getZExtValue() !=
15248 X86::STATIC_ROUNDING::CUR_DIRECTION)
15249 Cmp = DAG.getNode(IntrData->Opc1, dl, MaskVT, Op.getOperand(1),
15250 Op.getOperand(2), CC, Rnd);
15252 //default rounding mode
15254 Cmp = DAG.getNode(IntrData->Opc0, dl, MaskVT, Op.getOperand(1),
15255 Op.getOperand(2), CC);
15258 assert(IntrData->Type == CMP_MASK && "Unexpected intrinsic type!");
15259 Cmp = DAG.getNode(IntrData->Opc0, dl, MaskVT, Op.getOperand(1),
15262 SDValue CmpMask = getVectorMaskingNode(Cmp, Mask,
15263 DAG.getTargetConstant(0, dl,
15266 SDValue Res = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, BitcastVT,
15267 DAG.getUNDEF(BitcastVT), CmpMask,
15268 DAG.getIntPtrConstant(0, dl));
15269 return DAG.getBitcast(Op.getValueType(), Res);
15271 case COMI: { // Comparison intrinsics
15272 ISD::CondCode CC = (ISD::CondCode)IntrData->Opc1;
15273 SDValue LHS = Op.getOperand(1);
15274 SDValue RHS = Op.getOperand(2);
15275 unsigned X86CC = TranslateX86CC(CC, dl, true, LHS, RHS, DAG);
15276 assert(X86CC != X86::COND_INVALID && "Unexpected illegal condition!");
15277 SDValue Cond = DAG.getNode(IntrData->Opc0, dl, MVT::i32, LHS, RHS);
15278 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
15279 DAG.getConstant(X86CC, dl, MVT::i8), Cond);
15280 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
15283 return getTargetVShiftNode(IntrData->Opc0, dl, Op.getSimpleValueType(),
15284 Op.getOperand(1), Op.getOperand(2), DAG);
15286 return getVectorMaskingNode(getTargetVShiftNode(IntrData->Opc0, dl,
15287 Op.getSimpleValueType(),
15289 Op.getOperand(2), DAG),
15290 Op.getOperand(4), Op.getOperand(3), Subtarget,
15292 case COMPRESS_EXPAND_IN_REG: {
15293 SDValue Mask = Op.getOperand(3);
15294 SDValue DataToCompress = Op.getOperand(1);
15295 SDValue PassThru = Op.getOperand(2);
15296 if (isAllOnes(Mask)) // return data as is
15297 return Op.getOperand(1);
15298 EVT VT = Op.getValueType();
15299 EVT MaskVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
15300 VT.getVectorNumElements());
15301 EVT BitcastVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
15302 Mask.getValueType().getSizeInBits());
15304 SDValue VMask = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MaskVT,
15305 DAG.getBitcast(BitcastVT, Mask),
15306 DAG.getIntPtrConstant(0, dl));
15308 return DAG.getNode(IntrData->Opc0, dl, VT, VMask, DataToCompress,
15312 SDValue Mask = Op.getOperand(3);
15313 EVT VT = Op.getValueType();
15314 EVT MaskVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
15315 VT.getVectorNumElements());
15316 EVT BitcastVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
15317 Mask.getValueType().getSizeInBits());
15319 SDValue VMask = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MaskVT,
15320 DAG.getBitcast(BitcastVT, Mask),
15321 DAG.getIntPtrConstant(0, dl));
15322 return DAG.getNode(IntrData->Opc0, dl, VT, VMask, Op.getOperand(1),
15331 default: return SDValue(); // Don't custom lower most intrinsics.
15333 case Intrinsic::x86_avx2_permd:
15334 case Intrinsic::x86_avx2_permps:
15335 // Operands intentionally swapped. Mask is last operand to intrinsic,
15336 // but second operand for node/instruction.
15337 return DAG.getNode(X86ISD::VPERMV, dl, Op.getValueType(),
15338 Op.getOperand(2), Op.getOperand(1));
15340 // ptest and testp intrinsics. The intrinsic these come from are designed to
15341 // return an integer value, not just an instruction so lower it to the ptest
15342 // or testp pattern and a setcc for the result.
15343 case Intrinsic::x86_sse41_ptestz:
15344 case Intrinsic::x86_sse41_ptestc:
15345 case Intrinsic::x86_sse41_ptestnzc:
15346 case Intrinsic::x86_avx_ptestz_256:
15347 case Intrinsic::x86_avx_ptestc_256:
15348 case Intrinsic::x86_avx_ptestnzc_256:
15349 case Intrinsic::x86_avx_vtestz_ps:
15350 case Intrinsic::x86_avx_vtestc_ps:
15351 case Intrinsic::x86_avx_vtestnzc_ps:
15352 case Intrinsic::x86_avx_vtestz_pd:
15353 case Intrinsic::x86_avx_vtestc_pd:
15354 case Intrinsic::x86_avx_vtestnzc_pd:
15355 case Intrinsic::x86_avx_vtestz_ps_256:
15356 case Intrinsic::x86_avx_vtestc_ps_256:
15357 case Intrinsic::x86_avx_vtestnzc_ps_256:
15358 case Intrinsic::x86_avx_vtestz_pd_256:
15359 case Intrinsic::x86_avx_vtestc_pd_256:
15360 case Intrinsic::x86_avx_vtestnzc_pd_256: {
15361 bool IsTestPacked = false;
15364 default: llvm_unreachable("Bad fallthrough in Intrinsic lowering.");
15365 case Intrinsic::x86_avx_vtestz_ps:
15366 case Intrinsic::x86_avx_vtestz_pd:
15367 case Intrinsic::x86_avx_vtestz_ps_256:
15368 case Intrinsic::x86_avx_vtestz_pd_256:
15369 IsTestPacked = true; // Fallthrough
15370 case Intrinsic::x86_sse41_ptestz:
15371 case Intrinsic::x86_avx_ptestz_256:
15373 X86CC = X86::COND_E;
15375 case Intrinsic::x86_avx_vtestc_ps:
15376 case Intrinsic::x86_avx_vtestc_pd:
15377 case Intrinsic::x86_avx_vtestc_ps_256:
15378 case Intrinsic::x86_avx_vtestc_pd_256:
15379 IsTestPacked = true; // Fallthrough
15380 case Intrinsic::x86_sse41_ptestc:
15381 case Intrinsic::x86_avx_ptestc_256:
15383 X86CC = X86::COND_B;
15385 case Intrinsic::x86_avx_vtestnzc_ps:
15386 case Intrinsic::x86_avx_vtestnzc_pd:
15387 case Intrinsic::x86_avx_vtestnzc_ps_256:
15388 case Intrinsic::x86_avx_vtestnzc_pd_256:
15389 IsTestPacked = true; // Fallthrough
15390 case Intrinsic::x86_sse41_ptestnzc:
15391 case Intrinsic::x86_avx_ptestnzc_256:
15393 X86CC = X86::COND_A;
15397 SDValue LHS = Op.getOperand(1);
15398 SDValue RHS = Op.getOperand(2);
15399 unsigned TestOpc = IsTestPacked ? X86ISD::TESTP : X86ISD::PTEST;
15400 SDValue Test = DAG.getNode(TestOpc, dl, MVT::i32, LHS, RHS);
15401 SDValue CC = DAG.getConstant(X86CC, dl, MVT::i8);
15402 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8, CC, Test);
15403 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
15405 case Intrinsic::x86_avx512_kortestz_w:
15406 case Intrinsic::x86_avx512_kortestc_w: {
15407 unsigned X86CC = (IntNo == Intrinsic::x86_avx512_kortestz_w)? X86::COND_E: X86::COND_B;
15408 SDValue LHS = DAG.getBitcast(MVT::v16i1, Op.getOperand(1));
15409 SDValue RHS = DAG.getBitcast(MVT::v16i1, Op.getOperand(2));
15410 SDValue CC = DAG.getConstant(X86CC, dl, MVT::i8);
15411 SDValue Test = DAG.getNode(X86ISD::KORTEST, dl, MVT::i32, LHS, RHS);
15412 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i1, CC, Test);
15413 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
15416 case Intrinsic::x86_sse42_pcmpistria128:
15417 case Intrinsic::x86_sse42_pcmpestria128:
15418 case Intrinsic::x86_sse42_pcmpistric128:
15419 case Intrinsic::x86_sse42_pcmpestric128:
15420 case Intrinsic::x86_sse42_pcmpistrio128:
15421 case Intrinsic::x86_sse42_pcmpestrio128:
15422 case Intrinsic::x86_sse42_pcmpistris128:
15423 case Intrinsic::x86_sse42_pcmpestris128:
15424 case Intrinsic::x86_sse42_pcmpistriz128:
15425 case Intrinsic::x86_sse42_pcmpestriz128: {
15429 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
15430 case Intrinsic::x86_sse42_pcmpistria128:
15431 Opcode = X86ISD::PCMPISTRI;
15432 X86CC = X86::COND_A;
15434 case Intrinsic::x86_sse42_pcmpestria128:
15435 Opcode = X86ISD::PCMPESTRI;
15436 X86CC = X86::COND_A;
15438 case Intrinsic::x86_sse42_pcmpistric128:
15439 Opcode = X86ISD::PCMPISTRI;
15440 X86CC = X86::COND_B;
15442 case Intrinsic::x86_sse42_pcmpestric128:
15443 Opcode = X86ISD::PCMPESTRI;
15444 X86CC = X86::COND_B;
15446 case Intrinsic::x86_sse42_pcmpistrio128:
15447 Opcode = X86ISD::PCMPISTRI;
15448 X86CC = X86::COND_O;
15450 case Intrinsic::x86_sse42_pcmpestrio128:
15451 Opcode = X86ISD::PCMPESTRI;
15452 X86CC = X86::COND_O;
15454 case Intrinsic::x86_sse42_pcmpistris128:
15455 Opcode = X86ISD::PCMPISTRI;
15456 X86CC = X86::COND_S;
15458 case Intrinsic::x86_sse42_pcmpestris128:
15459 Opcode = X86ISD::PCMPESTRI;
15460 X86CC = X86::COND_S;
15462 case Intrinsic::x86_sse42_pcmpistriz128:
15463 Opcode = X86ISD::PCMPISTRI;
15464 X86CC = X86::COND_E;
15466 case Intrinsic::x86_sse42_pcmpestriz128:
15467 Opcode = X86ISD::PCMPESTRI;
15468 X86CC = X86::COND_E;
15471 SmallVector<SDValue, 5> NewOps(Op->op_begin()+1, Op->op_end());
15472 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
15473 SDValue PCMP = DAG.getNode(Opcode, dl, VTs, NewOps);
15474 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
15475 DAG.getConstant(X86CC, dl, MVT::i8),
15476 SDValue(PCMP.getNode(), 1));
15477 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
15480 case Intrinsic::x86_sse42_pcmpistri128:
15481 case Intrinsic::x86_sse42_pcmpestri128: {
15483 if (IntNo == Intrinsic::x86_sse42_pcmpistri128)
15484 Opcode = X86ISD::PCMPISTRI;
15486 Opcode = X86ISD::PCMPESTRI;
15488 SmallVector<SDValue, 5> NewOps(Op->op_begin()+1, Op->op_end());
15489 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
15490 return DAG.getNode(Opcode, dl, VTs, NewOps);
15493 case Intrinsic::x86_seh_lsda: {
15494 // Compute the symbol for the LSDA. We know it'll get emitted later.
15495 MachineFunction &MF = DAG.getMachineFunction();
15496 SDValue Op1 = Op.getOperand(1);
15497 auto *Fn = cast<Function>(cast<GlobalAddressSDNode>(Op1)->getGlobal());
15498 MCSymbol *LSDASym = MF.getMMI().getContext().getOrCreateLSDASymbol(
15499 GlobalValue::getRealLinkageName(Fn->getName()));
15500 StringRef Name = LSDASym->getName();
15501 assert(Name.data()[Name.size()] == '\0' && "not null terminated");
15503 // Generate a simple absolute symbol reference. This intrinsic is only
15504 // supported on 32-bit Windows, which isn't PIC.
15506 DAG.getTargetExternalSymbol(Name.data(), VT, X86II::MO_NOPREFIX);
15507 return DAG.getNode(X86ISD::Wrapper, dl, VT, Result);
15512 static SDValue getGatherNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
15513 SDValue Src, SDValue Mask, SDValue Base,
15514 SDValue Index, SDValue ScaleOp, SDValue Chain,
15515 const X86Subtarget * Subtarget) {
15517 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
15518 assert(C && "Invalid scale type");
15519 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), dl, MVT::i8);
15520 EVT MaskVT = MVT::getVectorVT(MVT::i1,
15521 Index.getSimpleValueType().getVectorNumElements());
15523 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(Mask);
15525 MaskInReg = DAG.getTargetConstant(MaskC->getSExtValue(), dl, MaskVT);
15527 MaskInReg = DAG.getBitcast(MaskVT, Mask);
15528 SDVTList VTs = DAG.getVTList(Op.getValueType(), MaskVT, MVT::Other);
15529 SDValue Disp = DAG.getTargetConstant(0, dl, MVT::i32);
15530 SDValue Segment = DAG.getRegister(0, MVT::i32);
15531 if (Src.getOpcode() == ISD::UNDEF)
15532 Src = getZeroVector(Op.getValueType(), Subtarget, DAG, dl);
15533 SDValue Ops[] = {Src, MaskInReg, Base, Scale, Index, Disp, Segment, Chain};
15534 SDNode *Res = DAG.getMachineNode(Opc, dl, VTs, Ops);
15535 SDValue RetOps[] = { SDValue(Res, 0), SDValue(Res, 2) };
15536 return DAG.getMergeValues(RetOps, dl);
15539 static SDValue getScatterNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
15540 SDValue Src, SDValue Mask, SDValue Base,
15541 SDValue Index, SDValue ScaleOp, SDValue Chain) {
15543 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
15544 assert(C && "Invalid scale type");
15545 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), dl, MVT::i8);
15546 SDValue Disp = DAG.getTargetConstant(0, dl, MVT::i32);
15547 SDValue Segment = DAG.getRegister(0, MVT::i32);
15548 EVT MaskVT = MVT::getVectorVT(MVT::i1,
15549 Index.getSimpleValueType().getVectorNumElements());
15551 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(Mask);
15553 MaskInReg = DAG.getTargetConstant(MaskC->getSExtValue(), dl, MaskVT);
15555 MaskInReg = DAG.getBitcast(MaskVT, Mask);
15556 SDVTList VTs = DAG.getVTList(MaskVT, MVT::Other);
15557 SDValue Ops[] = {Base, Scale, Index, Disp, Segment, MaskInReg, Src, Chain};
15558 SDNode *Res = DAG.getMachineNode(Opc, dl, VTs, Ops);
15559 return SDValue(Res, 1);
15562 static SDValue getPrefetchNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
15563 SDValue Mask, SDValue Base, SDValue Index,
15564 SDValue ScaleOp, SDValue Chain) {
15566 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
15567 assert(C && "Invalid scale type");
15568 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), dl, MVT::i8);
15569 SDValue Disp = DAG.getTargetConstant(0, dl, MVT::i32);
15570 SDValue Segment = DAG.getRegister(0, MVT::i32);
15572 MVT::getVectorVT(MVT::i1, Index.getSimpleValueType().getVectorNumElements());
15574 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(Mask);
15576 MaskInReg = DAG.getTargetConstant(MaskC->getSExtValue(), dl, MaskVT);
15578 MaskInReg = DAG.getBitcast(MaskVT, Mask);
15579 //SDVTList VTs = DAG.getVTList(MVT::Other);
15580 SDValue Ops[] = {MaskInReg, Base, Scale, Index, Disp, Segment, Chain};
15581 SDNode *Res = DAG.getMachineNode(Opc, dl, MVT::Other, Ops);
15582 return SDValue(Res, 0);
15585 // getReadPerformanceCounter - Handles the lowering of builtin intrinsics that
15586 // read performance monitor counters (x86_rdpmc).
15587 static void getReadPerformanceCounter(SDNode *N, SDLoc DL,
15588 SelectionDAG &DAG, const X86Subtarget *Subtarget,
15589 SmallVectorImpl<SDValue> &Results) {
15590 assert(N->getNumOperands() == 3 && "Unexpected number of operands!");
15591 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
15594 // The ECX register is used to select the index of the performance counter
15596 SDValue Chain = DAG.getCopyToReg(N->getOperand(0), DL, X86::ECX,
15598 SDValue rd = DAG.getNode(X86ISD::RDPMC_DAG, DL, Tys, Chain);
15600 // Reads the content of a 64-bit performance counter and returns it in the
15601 // registers EDX:EAX.
15602 if (Subtarget->is64Bit()) {
15603 LO = DAG.getCopyFromReg(rd, DL, X86::RAX, MVT::i64, rd.getValue(1));
15604 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::RDX, MVT::i64,
15607 LO = DAG.getCopyFromReg(rd, DL, X86::EAX, MVT::i32, rd.getValue(1));
15608 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::EDX, MVT::i32,
15611 Chain = HI.getValue(1);
15613 if (Subtarget->is64Bit()) {
15614 // The EAX register is loaded with the low-order 32 bits. The EDX register
15615 // is loaded with the supported high-order bits of the counter.
15616 SDValue Tmp = DAG.getNode(ISD::SHL, DL, MVT::i64, HI,
15617 DAG.getConstant(32, DL, MVT::i8));
15618 Results.push_back(DAG.getNode(ISD::OR, DL, MVT::i64, LO, Tmp));
15619 Results.push_back(Chain);
15623 // Use a buildpair to merge the two 32-bit values into a 64-bit one.
15624 SDValue Ops[] = { LO, HI };
15625 SDValue Pair = DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops);
15626 Results.push_back(Pair);
15627 Results.push_back(Chain);
15630 // getReadTimeStampCounter - Handles the lowering of builtin intrinsics that
15631 // read the time stamp counter (x86_rdtsc and x86_rdtscp). This function is
15632 // also used to custom lower READCYCLECOUNTER nodes.
15633 static void getReadTimeStampCounter(SDNode *N, SDLoc DL, unsigned Opcode,
15634 SelectionDAG &DAG, const X86Subtarget *Subtarget,
15635 SmallVectorImpl<SDValue> &Results) {
15636 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
15637 SDValue rd = DAG.getNode(Opcode, DL, Tys, N->getOperand(0));
15640 // The processor's time-stamp counter (a 64-bit MSR) is stored into the
15641 // EDX:EAX registers. EDX is loaded with the high-order 32 bits of the MSR
15642 // and the EAX register is loaded with the low-order 32 bits.
15643 if (Subtarget->is64Bit()) {
15644 LO = DAG.getCopyFromReg(rd, DL, X86::RAX, MVT::i64, rd.getValue(1));
15645 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::RDX, MVT::i64,
15648 LO = DAG.getCopyFromReg(rd, DL, X86::EAX, MVT::i32, rd.getValue(1));
15649 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::EDX, MVT::i32,
15652 SDValue Chain = HI.getValue(1);
15654 if (Opcode == X86ISD::RDTSCP_DAG) {
15655 assert(N->getNumOperands() == 3 && "Unexpected number of operands!");
15657 // Instruction RDTSCP loads the IA32:TSC_AUX_MSR (address C000_0103H) into
15658 // the ECX register. Add 'ecx' explicitly to the chain.
15659 SDValue ecx = DAG.getCopyFromReg(Chain, DL, X86::ECX, MVT::i32,
15661 // Explicitly store the content of ECX at the location passed in input
15662 // to the 'rdtscp' intrinsic.
15663 Chain = DAG.getStore(ecx.getValue(1), DL, ecx, N->getOperand(2),
15664 MachinePointerInfo(), false, false, 0);
15667 if (Subtarget->is64Bit()) {
15668 // The EDX register is loaded with the high-order 32 bits of the MSR, and
15669 // the EAX register is loaded with the low-order 32 bits.
15670 SDValue Tmp = DAG.getNode(ISD::SHL, DL, MVT::i64, HI,
15671 DAG.getConstant(32, DL, MVT::i8));
15672 Results.push_back(DAG.getNode(ISD::OR, DL, MVT::i64, LO, Tmp));
15673 Results.push_back(Chain);
15677 // Use a buildpair to merge the two 32-bit values into a 64-bit one.
15678 SDValue Ops[] = { LO, HI };
15679 SDValue Pair = DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops);
15680 Results.push_back(Pair);
15681 Results.push_back(Chain);
15684 static SDValue LowerREADCYCLECOUNTER(SDValue Op, const X86Subtarget *Subtarget,
15685 SelectionDAG &DAG) {
15686 SmallVector<SDValue, 2> Results;
15688 getReadTimeStampCounter(Op.getNode(), DL, X86ISD::RDTSC_DAG, DAG, Subtarget,
15690 return DAG.getMergeValues(Results, DL);
15693 static SDValue LowerEXCEPTIONINFO(SDValue Op, const X86Subtarget *Subtarget,
15694 SelectionDAG &DAG) {
15695 MachineFunction &MF = DAG.getMachineFunction();
15697 SDValue FnOp = Op.getOperand(2);
15698 SDValue FPOp = Op.getOperand(3);
15700 // Compute the symbol for the parent EH registration. We know it'll get
15702 auto *Fn = cast<Function>(cast<GlobalAddressSDNode>(FnOp)->getGlobal());
15703 MCSymbol *ParentFrameSym =
15704 MF.getMMI().getContext().getOrCreateParentFrameOffsetSymbol(
15705 GlobalValue::getRealLinkageName(Fn->getName()));
15706 StringRef Name = ParentFrameSym->getName();
15707 assert(Name.data()[Name.size()] == '\0' && "not null terminated");
15709 // Create a TargetExternalSymbol for the label to avoid any target lowering
15710 // that would make this PC relative.
15711 MVT PtrVT = Op.getSimpleValueType();
15712 SDValue OffsetSym = DAG.getTargetExternalSymbol(Name.data(), PtrVT);
15713 SDValue OffsetVal =
15714 DAG.getNode(ISD::FRAME_ALLOC_RECOVER, dl, PtrVT, OffsetSym);
15716 // Add the offset to the FP.
15717 SDValue Add = DAG.getNode(ISD::ADD, dl, PtrVT, FPOp, OffsetVal);
15719 // Load the second field of the struct, which is 4 bytes in. See
15720 // WinEHStatePass for more info.
15721 Add = DAG.getNode(ISD::ADD, dl, PtrVT, Add, DAG.getConstant(4, dl, PtrVT));
15722 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Add, MachinePointerInfo(),
15723 false, false, false, 0);
15726 static SDValue LowerINTRINSIC_W_CHAIN(SDValue Op, const X86Subtarget *Subtarget,
15727 SelectionDAG &DAG) {
15728 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
15730 const IntrinsicData* IntrData = getIntrinsicWithChain(IntNo);
15732 if (IntNo == Intrinsic::x86_seh_exceptioninfo)
15733 return LowerEXCEPTIONINFO(Op, Subtarget, DAG);
15738 switch(IntrData->Type) {
15740 llvm_unreachable("Unknown Intrinsic Type");
15744 // Emit the node with the right value type.
15745 SDVTList VTs = DAG.getVTList(Op->getValueType(0), MVT::Glue, MVT::Other);
15746 SDValue Result = DAG.getNode(IntrData->Opc0, dl, VTs, Op.getOperand(0));
15748 // If the value returned by RDRAND/RDSEED was valid (CF=1), return 1.
15749 // Otherwise return the value from Rand, which is always 0, casted to i32.
15750 SDValue Ops[] = { DAG.getZExtOrTrunc(Result, dl, Op->getValueType(1)),
15751 DAG.getConstant(1, dl, Op->getValueType(1)),
15752 DAG.getConstant(X86::COND_B, dl, MVT::i32),
15753 SDValue(Result.getNode(), 1) };
15754 SDValue isValid = DAG.getNode(X86ISD::CMOV, dl,
15755 DAG.getVTList(Op->getValueType(1), MVT::Glue),
15758 // Return { result, isValid, chain }.
15759 return DAG.getNode(ISD::MERGE_VALUES, dl, Op->getVTList(), Result, isValid,
15760 SDValue(Result.getNode(), 2));
15763 //gather(v1, mask, index, base, scale);
15764 SDValue Chain = Op.getOperand(0);
15765 SDValue Src = Op.getOperand(2);
15766 SDValue Base = Op.getOperand(3);
15767 SDValue Index = Op.getOperand(4);
15768 SDValue Mask = Op.getOperand(5);
15769 SDValue Scale = Op.getOperand(6);
15770 return getGatherNode(IntrData->Opc0, Op, DAG, Src, Mask, Base, Index, Scale,
15774 //scatter(base, mask, index, v1, scale);
15775 SDValue Chain = Op.getOperand(0);
15776 SDValue Base = Op.getOperand(2);
15777 SDValue Mask = Op.getOperand(3);
15778 SDValue Index = Op.getOperand(4);
15779 SDValue Src = Op.getOperand(5);
15780 SDValue Scale = Op.getOperand(6);
15781 return getScatterNode(IntrData->Opc0, Op, DAG, Src, Mask, Base, Index,
15785 SDValue Hint = Op.getOperand(6);
15786 unsigned HintVal = cast<ConstantSDNode>(Hint)->getZExtValue();
15787 assert(HintVal < 2 && "Wrong prefetch hint in intrinsic: should be 0 or 1");
15788 unsigned Opcode = (HintVal ? IntrData->Opc1 : IntrData->Opc0);
15789 SDValue Chain = Op.getOperand(0);
15790 SDValue Mask = Op.getOperand(2);
15791 SDValue Index = Op.getOperand(3);
15792 SDValue Base = Op.getOperand(4);
15793 SDValue Scale = Op.getOperand(5);
15794 return getPrefetchNode(Opcode, Op, DAG, Mask, Base, Index, Scale, Chain);
15796 // Read Time Stamp Counter (RDTSC) and Processor ID (RDTSCP).
15798 SmallVector<SDValue, 2> Results;
15799 getReadTimeStampCounter(Op.getNode(), dl, IntrData->Opc0, DAG, Subtarget,
15801 return DAG.getMergeValues(Results, dl);
15803 // Read Performance Monitoring Counters.
15805 SmallVector<SDValue, 2> Results;
15806 getReadPerformanceCounter(Op.getNode(), dl, DAG, Subtarget, Results);
15807 return DAG.getMergeValues(Results, dl);
15809 // XTEST intrinsics.
15811 SDVTList VTs = DAG.getVTList(Op->getValueType(0), MVT::Other);
15812 SDValue InTrans = DAG.getNode(IntrData->Opc0, dl, VTs, Op.getOperand(0));
15813 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
15814 DAG.getConstant(X86::COND_NE, dl, MVT::i8),
15816 SDValue Ret = DAG.getNode(ISD::ZERO_EXTEND, dl, Op->getValueType(0), SetCC);
15817 return DAG.getNode(ISD::MERGE_VALUES, dl, Op->getVTList(),
15818 Ret, SDValue(InTrans.getNode(), 1));
15822 SmallVector<SDValue, 2> Results;
15823 SDVTList CFVTs = DAG.getVTList(Op->getValueType(0), MVT::Other);
15824 SDVTList VTs = DAG.getVTList(Op.getOperand(3)->getValueType(0), MVT::Other);
15825 SDValue GenCF = DAG.getNode(X86ISD::ADD, dl, CFVTs, Op.getOperand(2),
15826 DAG.getConstant(-1, dl, MVT::i8));
15827 SDValue Res = DAG.getNode(IntrData->Opc0, dl, VTs, Op.getOperand(3),
15828 Op.getOperand(4), GenCF.getValue(1));
15829 SDValue Store = DAG.getStore(Op.getOperand(0), dl, Res.getValue(0),
15830 Op.getOperand(5), MachinePointerInfo(),
15832 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
15833 DAG.getConstant(X86::COND_B, dl, MVT::i8),
15835 Results.push_back(SetCC);
15836 Results.push_back(Store);
15837 return DAG.getMergeValues(Results, dl);
15839 case COMPRESS_TO_MEM: {
15841 SDValue Mask = Op.getOperand(4);
15842 SDValue DataToCompress = Op.getOperand(3);
15843 SDValue Addr = Op.getOperand(2);
15844 SDValue Chain = Op.getOperand(0);
15846 EVT VT = DataToCompress.getValueType();
15847 if (isAllOnes(Mask)) // return just a store
15848 return DAG.getStore(Chain, dl, DataToCompress, Addr,
15849 MachinePointerInfo(), false, false,
15850 VT.getScalarSizeInBits()/8);
15852 EVT MaskVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
15853 VT.getVectorNumElements());
15854 EVT BitcastVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
15855 Mask.getValueType().getSizeInBits());
15856 SDValue VMask = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MaskVT,
15857 DAG.getBitcast(BitcastVT, Mask),
15858 DAG.getIntPtrConstant(0, dl));
15860 SDValue Compressed = DAG.getNode(IntrData->Opc0, dl, VT, VMask,
15861 DataToCompress, DAG.getUNDEF(VT));
15862 return DAG.getStore(Chain, dl, Compressed, Addr,
15863 MachinePointerInfo(), false, false,
15864 VT.getScalarSizeInBits()/8);
15866 case EXPAND_FROM_MEM: {
15868 SDValue Mask = Op.getOperand(4);
15869 SDValue PathThru = Op.getOperand(3);
15870 SDValue Addr = Op.getOperand(2);
15871 SDValue Chain = Op.getOperand(0);
15872 EVT VT = Op.getValueType();
15874 if (isAllOnes(Mask)) // return just a load
15875 return DAG.getLoad(VT, dl, Chain, Addr, MachinePointerInfo(), false, false,
15876 false, VT.getScalarSizeInBits()/8);
15877 EVT MaskVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
15878 VT.getVectorNumElements());
15879 EVT BitcastVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
15880 Mask.getValueType().getSizeInBits());
15881 SDValue VMask = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MaskVT,
15882 DAG.getBitcast(BitcastVT, Mask),
15883 DAG.getIntPtrConstant(0, dl));
15885 SDValue DataToExpand = DAG.getLoad(VT, dl, Chain, Addr, MachinePointerInfo(),
15886 false, false, false,
15887 VT.getScalarSizeInBits()/8);
15889 SDValue Results[] = {
15890 DAG.getNode(IntrData->Opc0, dl, VT, VMask, DataToExpand, PathThru),
15892 return DAG.getMergeValues(Results, dl);
15897 SDValue X86TargetLowering::LowerRETURNADDR(SDValue Op,
15898 SelectionDAG &DAG) const {
15899 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
15900 MFI->setReturnAddressIsTaken(true);
15902 if (verifyReturnAddressArgumentIsConstant(Op, DAG))
15905 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
15907 EVT PtrVT = getPointerTy();
15910 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
15911 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
15912 SDValue Offset = DAG.getConstant(RegInfo->getSlotSize(), dl, PtrVT);
15913 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
15914 DAG.getNode(ISD::ADD, dl, PtrVT,
15915 FrameAddr, Offset),
15916 MachinePointerInfo(), false, false, false, 0);
15919 // Just load the return address.
15920 SDValue RetAddrFI = getReturnAddressFrameIndex(DAG);
15921 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
15922 RetAddrFI, MachinePointerInfo(), false, false, false, 0);
15925 SDValue X86TargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {
15926 MachineFunction &MF = DAG.getMachineFunction();
15927 MachineFrameInfo *MFI = MF.getFrameInfo();
15928 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
15929 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
15930 EVT VT = Op.getValueType();
15932 MFI->setFrameAddressIsTaken(true);
15934 if (MF.getTarget().getMCAsmInfo()->usesWindowsCFI()) {
15935 // Depth > 0 makes no sense on targets which use Windows unwind codes. It
15936 // is not possible to crawl up the stack without looking at the unwind codes
15938 int FrameAddrIndex = FuncInfo->getFAIndex();
15939 if (!FrameAddrIndex) {
15940 // Set up a frame object for the return address.
15941 unsigned SlotSize = RegInfo->getSlotSize();
15942 FrameAddrIndex = MF.getFrameInfo()->CreateFixedObject(
15943 SlotSize, /*Offset=*/0, /*IsImmutable=*/false);
15944 FuncInfo->setFAIndex(FrameAddrIndex);
15946 return DAG.getFrameIndex(FrameAddrIndex, VT);
15949 unsigned FrameReg =
15950 RegInfo->getPtrSizedFrameRegister(DAG.getMachineFunction());
15951 SDLoc dl(Op); // FIXME probably not meaningful
15952 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
15953 assert(((FrameReg == X86::RBP && VT == MVT::i64) ||
15954 (FrameReg == X86::EBP && VT == MVT::i32)) &&
15955 "Invalid Frame Register!");
15956 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT);
15958 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr,
15959 MachinePointerInfo(),
15960 false, false, false, 0);
15964 // FIXME? Maybe this could be a TableGen attribute on some registers and
15965 // this table could be generated automatically from RegInfo.
15966 unsigned X86TargetLowering::getRegisterByName(const char* RegName,
15968 unsigned Reg = StringSwitch<unsigned>(RegName)
15969 .Case("esp", X86::ESP)
15970 .Case("rsp", X86::RSP)
15974 report_fatal_error("Invalid register name global variable");
15977 SDValue X86TargetLowering::LowerFRAME_TO_ARGS_OFFSET(SDValue Op,
15978 SelectionDAG &DAG) const {
15979 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
15980 return DAG.getIntPtrConstant(2 * RegInfo->getSlotSize(), SDLoc(Op));
15983 SDValue X86TargetLowering::LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const {
15984 SDValue Chain = Op.getOperand(0);
15985 SDValue Offset = Op.getOperand(1);
15986 SDValue Handler = Op.getOperand(2);
15989 EVT PtrVT = getPointerTy();
15990 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
15991 unsigned FrameReg = RegInfo->getFrameRegister(DAG.getMachineFunction());
15992 assert(((FrameReg == X86::RBP && PtrVT == MVT::i64) ||
15993 (FrameReg == X86::EBP && PtrVT == MVT::i32)) &&
15994 "Invalid Frame Register!");
15995 SDValue Frame = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, PtrVT);
15996 unsigned StoreAddrReg = (PtrVT == MVT::i64) ? X86::RCX : X86::ECX;
15998 SDValue StoreAddr = DAG.getNode(ISD::ADD, dl, PtrVT, Frame,
15999 DAG.getIntPtrConstant(RegInfo->getSlotSize(),
16001 StoreAddr = DAG.getNode(ISD::ADD, dl, PtrVT, StoreAddr, Offset);
16002 Chain = DAG.getStore(Chain, dl, Handler, StoreAddr, MachinePointerInfo(),
16004 Chain = DAG.getCopyToReg(Chain, dl, StoreAddrReg, StoreAddr);
16006 return DAG.getNode(X86ISD::EH_RETURN, dl, MVT::Other, Chain,
16007 DAG.getRegister(StoreAddrReg, PtrVT));
16010 SDValue X86TargetLowering::lowerEH_SJLJ_SETJMP(SDValue Op,
16011 SelectionDAG &DAG) const {
16013 return DAG.getNode(X86ISD::EH_SJLJ_SETJMP, DL,
16014 DAG.getVTList(MVT::i32, MVT::Other),
16015 Op.getOperand(0), Op.getOperand(1));
16018 SDValue X86TargetLowering::lowerEH_SJLJ_LONGJMP(SDValue Op,
16019 SelectionDAG &DAG) const {
16021 return DAG.getNode(X86ISD::EH_SJLJ_LONGJMP, DL, MVT::Other,
16022 Op.getOperand(0), Op.getOperand(1));
16025 static SDValue LowerADJUST_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) {
16026 return Op.getOperand(0);
16029 SDValue X86TargetLowering::LowerINIT_TRAMPOLINE(SDValue Op,
16030 SelectionDAG &DAG) const {
16031 SDValue Root = Op.getOperand(0);
16032 SDValue Trmp = Op.getOperand(1); // trampoline
16033 SDValue FPtr = Op.getOperand(2); // nested function
16034 SDValue Nest = Op.getOperand(3); // 'nest' parameter value
16037 const Value *TrmpAddr = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
16038 const TargetRegisterInfo *TRI = Subtarget->getRegisterInfo();
16040 if (Subtarget->is64Bit()) {
16041 SDValue OutChains[6];
16043 // Large code-model.
16044 const unsigned char JMP64r = 0xFF; // 64-bit jmp through register opcode.
16045 const unsigned char MOV64ri = 0xB8; // X86::MOV64ri opcode.
16047 const unsigned char N86R10 = TRI->getEncodingValue(X86::R10) & 0x7;
16048 const unsigned char N86R11 = TRI->getEncodingValue(X86::R11) & 0x7;
16050 const unsigned char REX_WB = 0x40 | 0x08 | 0x01; // REX prefix
16052 // Load the pointer to the nested function into R11.
16053 unsigned OpCode = ((MOV64ri | N86R11) << 8) | REX_WB; // movabsq r11
16054 SDValue Addr = Trmp;
16055 OutChains[0] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, dl, MVT::i16),
16056 Addr, MachinePointerInfo(TrmpAddr),
16059 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
16060 DAG.getConstant(2, dl, MVT::i64));
16061 OutChains[1] = DAG.getStore(Root, dl, FPtr, Addr,
16062 MachinePointerInfo(TrmpAddr, 2),
16065 // Load the 'nest' parameter value into R10.
16066 // R10 is specified in X86CallingConv.td
16067 OpCode = ((MOV64ri | N86R10) << 8) | REX_WB; // movabsq r10
16068 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
16069 DAG.getConstant(10, dl, MVT::i64));
16070 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, dl, MVT::i16),
16071 Addr, MachinePointerInfo(TrmpAddr, 10),
16074 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
16075 DAG.getConstant(12, dl, MVT::i64));
16076 OutChains[3] = DAG.getStore(Root, dl, Nest, Addr,
16077 MachinePointerInfo(TrmpAddr, 12),
16080 // Jump to the nested function.
16081 OpCode = (JMP64r << 8) | REX_WB; // jmpq *...
16082 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
16083 DAG.getConstant(20, dl, MVT::i64));
16084 OutChains[4] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, dl, MVT::i16),
16085 Addr, MachinePointerInfo(TrmpAddr, 20),
16088 unsigned char ModRM = N86R11 | (4 << 3) | (3 << 6); // ...r11
16089 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
16090 DAG.getConstant(22, dl, MVT::i64));
16091 OutChains[5] = DAG.getStore(Root, dl, DAG.getConstant(ModRM, dl, MVT::i8),
16092 Addr, MachinePointerInfo(TrmpAddr, 22),
16095 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains);
16097 const Function *Func =
16098 cast<Function>(cast<SrcValueSDNode>(Op.getOperand(5))->getValue());
16099 CallingConv::ID CC = Func->getCallingConv();
16104 llvm_unreachable("Unsupported calling convention");
16105 case CallingConv::C:
16106 case CallingConv::X86_StdCall: {
16107 // Pass 'nest' parameter in ECX.
16108 // Must be kept in sync with X86CallingConv.td
16109 NestReg = X86::ECX;
16111 // Check that ECX wasn't needed by an 'inreg' parameter.
16112 FunctionType *FTy = Func->getFunctionType();
16113 const AttributeSet &Attrs = Func->getAttributes();
16115 if (!Attrs.isEmpty() && !Func->isVarArg()) {
16116 unsigned InRegCount = 0;
16119 for (FunctionType::param_iterator I = FTy->param_begin(),
16120 E = FTy->param_end(); I != E; ++I, ++Idx)
16121 if (Attrs.hasAttribute(Idx, Attribute::InReg))
16122 // FIXME: should only count parameters that are lowered to integers.
16123 InRegCount += (TD->getTypeSizeInBits(*I) + 31) / 32;
16125 if (InRegCount > 2) {
16126 report_fatal_error("Nest register in use - reduce number of inreg"
16132 case CallingConv::X86_FastCall:
16133 case CallingConv::X86_ThisCall:
16134 case CallingConv::Fast:
16135 // Pass 'nest' parameter in EAX.
16136 // Must be kept in sync with X86CallingConv.td
16137 NestReg = X86::EAX;
16141 SDValue OutChains[4];
16142 SDValue Addr, Disp;
16144 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
16145 DAG.getConstant(10, dl, MVT::i32));
16146 Disp = DAG.getNode(ISD::SUB, dl, MVT::i32, FPtr, Addr);
16148 // This is storing the opcode for MOV32ri.
16149 const unsigned char MOV32ri = 0xB8; // X86::MOV32ri's opcode byte.
16150 const unsigned char N86Reg = TRI->getEncodingValue(NestReg) & 0x7;
16151 OutChains[0] = DAG.getStore(Root, dl,
16152 DAG.getConstant(MOV32ri|N86Reg, dl, MVT::i8),
16153 Trmp, MachinePointerInfo(TrmpAddr),
16156 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
16157 DAG.getConstant(1, dl, MVT::i32));
16158 OutChains[1] = DAG.getStore(Root, dl, Nest, Addr,
16159 MachinePointerInfo(TrmpAddr, 1),
16162 const unsigned char JMP = 0xE9; // jmp <32bit dst> opcode.
16163 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
16164 DAG.getConstant(5, dl, MVT::i32));
16165 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(JMP, dl, MVT::i8),
16166 Addr, MachinePointerInfo(TrmpAddr, 5),
16169 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
16170 DAG.getConstant(6, dl, MVT::i32));
16171 OutChains[3] = DAG.getStore(Root, dl, Disp, Addr,
16172 MachinePointerInfo(TrmpAddr, 6),
16175 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains);
16179 SDValue X86TargetLowering::LowerFLT_ROUNDS_(SDValue Op,
16180 SelectionDAG &DAG) const {
16182 The rounding mode is in bits 11:10 of FPSR, and has the following
16184 00 Round to nearest
16189 FLT_ROUNDS, on the other hand, expects the following:
16196 To perform the conversion, we do:
16197 (((((FPSR & 0x800) >> 11) | ((FPSR & 0x400) >> 9)) + 1) & 3)
16200 MachineFunction &MF = DAG.getMachineFunction();
16201 const TargetFrameLowering &TFI = *Subtarget->getFrameLowering();
16202 unsigned StackAlignment = TFI.getStackAlignment();
16203 MVT VT = Op.getSimpleValueType();
16206 // Save FP Control Word to stack slot
16207 int SSFI = MF.getFrameInfo()->CreateStackObject(2, StackAlignment, false);
16208 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
16210 MachineMemOperand *MMO =
16211 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
16212 MachineMemOperand::MOStore, 2, 2);
16214 SDValue Ops[] = { DAG.getEntryNode(), StackSlot };
16215 SDValue Chain = DAG.getMemIntrinsicNode(X86ISD::FNSTCW16m, DL,
16216 DAG.getVTList(MVT::Other),
16217 Ops, MVT::i16, MMO);
16219 // Load FP Control Word from stack slot
16220 SDValue CWD = DAG.getLoad(MVT::i16, DL, Chain, StackSlot,
16221 MachinePointerInfo(), false, false, false, 0);
16223 // Transform as necessary
16225 DAG.getNode(ISD::SRL, DL, MVT::i16,
16226 DAG.getNode(ISD::AND, DL, MVT::i16,
16227 CWD, DAG.getConstant(0x800, DL, MVT::i16)),
16228 DAG.getConstant(11, DL, MVT::i8));
16230 DAG.getNode(ISD::SRL, DL, MVT::i16,
16231 DAG.getNode(ISD::AND, DL, MVT::i16,
16232 CWD, DAG.getConstant(0x400, DL, MVT::i16)),
16233 DAG.getConstant(9, DL, MVT::i8));
16236 DAG.getNode(ISD::AND, DL, MVT::i16,
16237 DAG.getNode(ISD::ADD, DL, MVT::i16,
16238 DAG.getNode(ISD::OR, DL, MVT::i16, CWD1, CWD2),
16239 DAG.getConstant(1, DL, MVT::i16)),
16240 DAG.getConstant(3, DL, MVT::i16));
16242 return DAG.getNode((VT.getSizeInBits() < 16 ?
16243 ISD::TRUNCATE : ISD::ZERO_EXTEND), DL, VT, RetVal);
16246 static SDValue LowerCTLZ(SDValue Op, SelectionDAG &DAG) {
16247 MVT VT = Op.getSimpleValueType();
16249 unsigned NumBits = VT.getSizeInBits();
16252 Op = Op.getOperand(0);
16253 if (VT == MVT::i8) {
16254 // Zero extend to i32 since there is not an i8 bsr.
16256 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
16259 // Issue a bsr (scan bits in reverse) which also sets EFLAGS.
16260 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
16261 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
16263 // If src is zero (i.e. bsr sets ZF), returns NumBits.
16266 DAG.getConstant(NumBits + NumBits - 1, dl, OpVT),
16267 DAG.getConstant(X86::COND_E, dl, MVT::i8),
16270 Op = DAG.getNode(X86ISD::CMOV, dl, OpVT, Ops);
16272 // Finally xor with NumBits-1.
16273 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op,
16274 DAG.getConstant(NumBits - 1, dl, OpVT));
16277 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
16281 static SDValue LowerCTLZ_ZERO_UNDEF(SDValue Op, SelectionDAG &DAG) {
16282 MVT VT = Op.getSimpleValueType();
16284 unsigned NumBits = VT.getSizeInBits();
16287 Op = Op.getOperand(0);
16288 if (VT == MVT::i8) {
16289 // Zero extend to i32 since there is not an i8 bsr.
16291 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
16294 // Issue a bsr (scan bits in reverse).
16295 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
16296 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
16298 // And xor with NumBits-1.
16299 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op,
16300 DAG.getConstant(NumBits - 1, dl, OpVT));
16303 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
16307 static SDValue LowerCTTZ(SDValue Op, SelectionDAG &DAG) {
16308 MVT VT = Op.getSimpleValueType();
16309 unsigned NumBits = VT.getSizeInBits();
16311 Op = Op.getOperand(0);
16313 // Issue a bsf (scan bits forward) which also sets EFLAGS.
16314 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
16315 Op = DAG.getNode(X86ISD::BSF, dl, VTs, Op);
16317 // If src is zero (i.e. bsf sets ZF), returns NumBits.
16320 DAG.getConstant(NumBits, dl, VT),
16321 DAG.getConstant(X86::COND_E, dl, MVT::i8),
16324 return DAG.getNode(X86ISD::CMOV, dl, VT, Ops);
16327 // Lower256IntArith - Break a 256-bit integer operation into two new 128-bit
16328 // ones, and then concatenate the result back.
16329 static SDValue Lower256IntArith(SDValue Op, SelectionDAG &DAG) {
16330 MVT VT = Op.getSimpleValueType();
16332 assert(VT.is256BitVector() && VT.isInteger() &&
16333 "Unsupported value type for operation");
16335 unsigned NumElems = VT.getVectorNumElements();
16338 // Extract the LHS vectors
16339 SDValue LHS = Op.getOperand(0);
16340 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
16341 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
16343 // Extract the RHS vectors
16344 SDValue RHS = Op.getOperand(1);
16345 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, dl);
16346 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, dl);
16348 MVT EltVT = VT.getVectorElementType();
16349 MVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
16351 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
16352 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1),
16353 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2));
16356 static SDValue LowerADD(SDValue Op, SelectionDAG &DAG) {
16357 if (Op.getValueType() == MVT::i1)
16358 return DAG.getNode(ISD::XOR, SDLoc(Op), Op.getValueType(),
16359 Op.getOperand(0), Op.getOperand(1));
16360 assert(Op.getSimpleValueType().is256BitVector() &&
16361 Op.getSimpleValueType().isInteger() &&
16362 "Only handle AVX 256-bit vector integer operation");
16363 return Lower256IntArith(Op, DAG);
16366 static SDValue LowerSUB(SDValue Op, SelectionDAG &DAG) {
16367 if (Op.getValueType() == MVT::i1)
16368 return DAG.getNode(ISD::XOR, SDLoc(Op), Op.getValueType(),
16369 Op.getOperand(0), Op.getOperand(1));
16370 assert(Op.getSimpleValueType().is256BitVector() &&
16371 Op.getSimpleValueType().isInteger() &&
16372 "Only handle AVX 256-bit vector integer operation");
16373 return Lower256IntArith(Op, DAG);
16376 static SDValue LowerMUL(SDValue Op, const X86Subtarget *Subtarget,
16377 SelectionDAG &DAG) {
16379 MVT VT = Op.getSimpleValueType();
16382 return DAG.getNode(ISD::AND, dl, VT, Op.getOperand(0), Op.getOperand(1));
16384 // Decompose 256-bit ops into smaller 128-bit ops.
16385 if (VT.is256BitVector() && !Subtarget->hasInt256())
16386 return Lower256IntArith(Op, DAG);
16388 SDValue A = Op.getOperand(0);
16389 SDValue B = Op.getOperand(1);
16391 // Lower v16i8/v32i8 mul as promotion to v8i16/v16i16 vector
16392 // pairs, multiply and truncate.
16393 if (VT == MVT::v16i8 || VT == MVT::v32i8) {
16394 if (Subtarget->hasInt256()) {
16395 if (VT == MVT::v32i8) {
16396 MVT SubVT = MVT::getVectorVT(MVT::i8, VT.getVectorNumElements() / 2);
16397 SDValue Lo = DAG.getIntPtrConstant(0, dl);
16398 SDValue Hi = DAG.getIntPtrConstant(VT.getVectorNumElements() / 2, dl);
16399 SDValue ALo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, SubVT, A, Lo);
16400 SDValue BLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, SubVT, B, Lo);
16401 SDValue AHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, SubVT, A, Hi);
16402 SDValue BHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, SubVT, B, Hi);
16403 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
16404 DAG.getNode(ISD::MUL, dl, SubVT, ALo, BLo),
16405 DAG.getNode(ISD::MUL, dl, SubVT, AHi, BHi));
16408 MVT ExVT = MVT::getVectorVT(MVT::i16, VT.getVectorNumElements());
16409 return DAG.getNode(
16410 ISD::TRUNCATE, dl, VT,
16411 DAG.getNode(ISD::MUL, dl, ExVT,
16412 DAG.getNode(ISD::SIGN_EXTEND, dl, ExVT, A),
16413 DAG.getNode(ISD::SIGN_EXTEND, dl, ExVT, B)));
16416 assert(VT == MVT::v16i8 &&
16417 "Pre-AVX2 support only supports v16i8 multiplication");
16418 MVT ExVT = MVT::v8i16;
16420 // Extract the lo parts and sign extend to i16
16422 if (Subtarget->hasSSE41()) {
16423 ALo = DAG.getNode(X86ISD::VSEXT, dl, ExVT, A);
16424 BLo = DAG.getNode(X86ISD::VSEXT, dl, ExVT, B);
16426 const int ShufMask[] = {-1, 0, -1, 1, -1, 2, -1, 3,
16427 -1, 4, -1, 5, -1, 6, -1, 7};
16428 ALo = DAG.getVectorShuffle(VT, dl, A, A, ShufMask);
16429 BLo = DAG.getVectorShuffle(VT, dl, B, B, ShufMask);
16430 ALo = DAG.getBitcast(ExVT, ALo);
16431 BLo = DAG.getBitcast(ExVT, BLo);
16432 ALo = DAG.getNode(ISD::SRA, dl, ExVT, ALo, DAG.getConstant(8, dl, ExVT));
16433 BLo = DAG.getNode(ISD::SRA, dl, ExVT, BLo, DAG.getConstant(8, dl, ExVT));
16436 // Extract the hi parts and sign extend to i16
16438 if (Subtarget->hasSSE41()) {
16439 const int ShufMask[] = {8, 9, 10, 11, 12, 13, 14, 15,
16440 -1, -1, -1, -1, -1, -1, -1, -1};
16441 AHi = DAG.getVectorShuffle(VT, dl, A, A, ShufMask);
16442 BHi = DAG.getVectorShuffle(VT, dl, B, B, ShufMask);
16443 AHi = DAG.getNode(X86ISD::VSEXT, dl, ExVT, AHi);
16444 BHi = DAG.getNode(X86ISD::VSEXT, dl, ExVT, BHi);
16446 const int ShufMask[] = {-1, 8, -1, 9, -1, 10, -1, 11,
16447 -1, 12, -1, 13, -1, 14, -1, 15};
16448 AHi = DAG.getVectorShuffle(VT, dl, A, A, ShufMask);
16449 BHi = DAG.getVectorShuffle(VT, dl, B, B, ShufMask);
16450 AHi = DAG.getBitcast(ExVT, AHi);
16451 BHi = DAG.getBitcast(ExVT, BHi);
16452 AHi = DAG.getNode(ISD::SRA, dl, ExVT, AHi, DAG.getConstant(8, dl, ExVT));
16453 BHi = DAG.getNode(ISD::SRA, dl, ExVT, BHi, DAG.getConstant(8, dl, ExVT));
16456 // Multiply, mask the lower 8bits of the lo/hi results and pack
16457 SDValue RLo = DAG.getNode(ISD::MUL, dl, ExVT, ALo, BLo);
16458 SDValue RHi = DAG.getNode(ISD::MUL, dl, ExVT, AHi, BHi);
16459 RLo = DAG.getNode(ISD::AND, dl, ExVT, RLo, DAG.getConstant(255, dl, ExVT));
16460 RHi = DAG.getNode(ISD::AND, dl, ExVT, RHi, DAG.getConstant(255, dl, ExVT));
16461 return DAG.getNode(X86ISD::PACKUS, dl, VT, RLo, RHi);
16464 // Lower v4i32 mul as 2x shuffle, 2x pmuludq, 2x shuffle.
16465 if (VT == MVT::v4i32) {
16466 assert(Subtarget->hasSSE2() && !Subtarget->hasSSE41() &&
16467 "Should not custom lower when pmuldq is available!");
16469 // Extract the odd parts.
16470 static const int UnpackMask[] = { 1, -1, 3, -1 };
16471 SDValue Aodds = DAG.getVectorShuffle(VT, dl, A, A, UnpackMask);
16472 SDValue Bodds = DAG.getVectorShuffle(VT, dl, B, B, UnpackMask);
16474 // Multiply the even parts.
16475 SDValue Evens = DAG.getNode(X86ISD::PMULUDQ, dl, MVT::v2i64, A, B);
16476 // Now multiply odd parts.
16477 SDValue Odds = DAG.getNode(X86ISD::PMULUDQ, dl, MVT::v2i64, Aodds, Bodds);
16479 Evens = DAG.getBitcast(VT, Evens);
16480 Odds = DAG.getBitcast(VT, Odds);
16482 // Merge the two vectors back together with a shuffle. This expands into 2
16484 static const int ShufMask[] = { 0, 4, 2, 6 };
16485 return DAG.getVectorShuffle(VT, dl, Evens, Odds, ShufMask);
16488 assert((VT == MVT::v2i64 || VT == MVT::v4i64 || VT == MVT::v8i64) &&
16489 "Only know how to lower V2I64/V4I64/V8I64 multiply");
16491 // Ahi = psrlqi(a, 32);
16492 // Bhi = psrlqi(b, 32);
16494 // AloBlo = pmuludq(a, b);
16495 // AloBhi = pmuludq(a, Bhi);
16496 // AhiBlo = pmuludq(Ahi, b);
16498 // AloBhi = psllqi(AloBhi, 32);
16499 // AhiBlo = psllqi(AhiBlo, 32);
16500 // return AloBlo + AloBhi + AhiBlo;
16502 SDValue Ahi = getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, A, 32, DAG);
16503 SDValue Bhi = getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, B, 32, DAG);
16505 // Bit cast to 32-bit vectors for MULUDQ
16506 EVT MulVT = (VT == MVT::v2i64) ? MVT::v4i32 :
16507 (VT == MVT::v4i64) ? MVT::v8i32 : MVT::v16i32;
16508 A = DAG.getBitcast(MulVT, A);
16509 B = DAG.getBitcast(MulVT, B);
16510 Ahi = DAG.getBitcast(MulVT, Ahi);
16511 Bhi = DAG.getBitcast(MulVT, Bhi);
16513 SDValue AloBlo = DAG.getNode(X86ISD::PMULUDQ, dl, VT, A, B);
16514 SDValue AloBhi = DAG.getNode(X86ISD::PMULUDQ, dl, VT, A, Bhi);
16515 SDValue AhiBlo = DAG.getNode(X86ISD::PMULUDQ, dl, VT, Ahi, B);
16517 AloBhi = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, AloBhi, 32, DAG);
16518 AhiBlo = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, AhiBlo, 32, DAG);
16520 SDValue Res = DAG.getNode(ISD::ADD, dl, VT, AloBlo, AloBhi);
16521 return DAG.getNode(ISD::ADD, dl, VT, Res, AhiBlo);
16524 SDValue X86TargetLowering::LowerWin64_i128OP(SDValue Op, SelectionDAG &DAG) const {
16525 assert(Subtarget->isTargetWin64() && "Unexpected target");
16526 EVT VT = Op.getValueType();
16527 assert(VT.isInteger() && VT.getSizeInBits() == 128 &&
16528 "Unexpected return type for lowering");
16532 switch (Op->getOpcode()) {
16533 default: llvm_unreachable("Unexpected request for libcall!");
16534 case ISD::SDIV: isSigned = true; LC = RTLIB::SDIV_I128; break;
16535 case ISD::UDIV: isSigned = false; LC = RTLIB::UDIV_I128; break;
16536 case ISD::SREM: isSigned = true; LC = RTLIB::SREM_I128; break;
16537 case ISD::UREM: isSigned = false; LC = RTLIB::UREM_I128; break;
16538 case ISD::SDIVREM: isSigned = true; LC = RTLIB::SDIVREM_I128; break;
16539 case ISD::UDIVREM: isSigned = false; LC = RTLIB::UDIVREM_I128; break;
16543 SDValue InChain = DAG.getEntryNode();
16545 TargetLowering::ArgListTy Args;
16546 TargetLowering::ArgListEntry Entry;
16547 for (unsigned i = 0, e = Op->getNumOperands(); i != e; ++i) {
16548 EVT ArgVT = Op->getOperand(i).getValueType();
16549 assert(ArgVT.isInteger() && ArgVT.getSizeInBits() == 128 &&
16550 "Unexpected argument type for lowering");
16551 SDValue StackPtr = DAG.CreateStackTemporary(ArgVT, 16);
16552 Entry.Node = StackPtr;
16553 InChain = DAG.getStore(InChain, dl, Op->getOperand(i), StackPtr, MachinePointerInfo(),
16555 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
16556 Entry.Ty = PointerType::get(ArgTy,0);
16557 Entry.isSExt = false;
16558 Entry.isZExt = false;
16559 Args.push_back(Entry);
16562 SDValue Callee = DAG.getExternalSymbol(getLibcallName(LC),
16565 TargetLowering::CallLoweringInfo CLI(DAG);
16566 CLI.setDebugLoc(dl).setChain(InChain)
16567 .setCallee(getLibcallCallingConv(LC),
16568 static_cast<EVT>(MVT::v2i64).getTypeForEVT(*DAG.getContext()),
16569 Callee, std::move(Args), 0)
16570 .setInRegister().setSExtResult(isSigned).setZExtResult(!isSigned);
16572 std::pair<SDValue, SDValue> CallInfo = LowerCallTo(CLI);
16573 return DAG.getBitcast(VT, CallInfo.first);
16576 static SDValue LowerMUL_LOHI(SDValue Op, const X86Subtarget *Subtarget,
16577 SelectionDAG &DAG) {
16578 SDValue Op0 = Op.getOperand(0), Op1 = Op.getOperand(1);
16579 EVT VT = Op0.getValueType();
16582 assert((VT == MVT::v4i32 && Subtarget->hasSSE2()) ||
16583 (VT == MVT::v8i32 && Subtarget->hasInt256()));
16585 // PMULxD operations multiply each even value (starting at 0) of LHS with
16586 // the related value of RHS and produce a widen result.
16587 // E.g., PMULUDQ <4 x i32> <a|b|c|d>, <4 x i32> <e|f|g|h>
16588 // => <2 x i64> <ae|cg>
16590 // In other word, to have all the results, we need to perform two PMULxD:
16591 // 1. one with the even values.
16592 // 2. one with the odd values.
16593 // To achieve #2, with need to place the odd values at an even position.
16595 // Place the odd value at an even position (basically, shift all values 1
16596 // step to the left):
16597 const int Mask[] = {1, -1, 3, -1, 5, -1, 7, -1};
16598 // <a|b|c|d> => <b|undef|d|undef>
16599 SDValue Odd0 = DAG.getVectorShuffle(VT, dl, Op0, Op0, Mask);
16600 // <e|f|g|h> => <f|undef|h|undef>
16601 SDValue Odd1 = DAG.getVectorShuffle(VT, dl, Op1, Op1, Mask);
16603 // Emit two multiplies, one for the lower 2 ints and one for the higher 2
16605 MVT MulVT = VT == MVT::v4i32 ? MVT::v2i64 : MVT::v4i64;
16606 bool IsSigned = Op->getOpcode() == ISD::SMUL_LOHI;
16608 (!IsSigned || !Subtarget->hasSSE41()) ? X86ISD::PMULUDQ : X86ISD::PMULDQ;
16609 // PMULUDQ <4 x i32> <a|b|c|d>, <4 x i32> <e|f|g|h>
16610 // => <2 x i64> <ae|cg>
16611 SDValue Mul1 = DAG.getBitcast(VT, DAG.getNode(Opcode, dl, MulVT, Op0, Op1));
16612 // PMULUDQ <4 x i32> <b|undef|d|undef>, <4 x i32> <f|undef|h|undef>
16613 // => <2 x i64> <bf|dh>
16614 SDValue Mul2 = DAG.getBitcast(VT, DAG.getNode(Opcode, dl, MulVT, Odd0, Odd1));
16616 // Shuffle it back into the right order.
16617 SDValue Highs, Lows;
16618 if (VT == MVT::v8i32) {
16619 const int HighMask[] = {1, 9, 3, 11, 5, 13, 7, 15};
16620 Highs = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, HighMask);
16621 const int LowMask[] = {0, 8, 2, 10, 4, 12, 6, 14};
16622 Lows = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, LowMask);
16624 const int HighMask[] = {1, 5, 3, 7};
16625 Highs = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, HighMask);
16626 const int LowMask[] = {0, 4, 2, 6};
16627 Lows = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, LowMask);
16630 // If we have a signed multiply but no PMULDQ fix up the high parts of a
16631 // unsigned multiply.
16632 if (IsSigned && !Subtarget->hasSSE41()) {
16634 DAG.getConstant(31, dl,
16635 DAG.getTargetLoweringInfo().getShiftAmountTy(VT));
16636 SDValue T1 = DAG.getNode(ISD::AND, dl, VT,
16637 DAG.getNode(ISD::SRA, dl, VT, Op0, ShAmt), Op1);
16638 SDValue T2 = DAG.getNode(ISD::AND, dl, VT,
16639 DAG.getNode(ISD::SRA, dl, VT, Op1, ShAmt), Op0);
16641 SDValue Fixup = DAG.getNode(ISD::ADD, dl, VT, T1, T2);
16642 Highs = DAG.getNode(ISD::SUB, dl, VT, Highs, Fixup);
16645 // The first result of MUL_LOHI is actually the low value, followed by the
16647 SDValue Ops[] = {Lows, Highs};
16648 return DAG.getMergeValues(Ops, dl);
16651 // Return true if the requred (according to Opcode) shift-imm form is natively
16652 // supported by the Subtarget
16653 static bool SupportedVectorShiftWithImm(MVT VT, const X86Subtarget *Subtarget,
16655 if (VT.getScalarSizeInBits() < 16)
16658 if (VT.is512BitVector() &&
16659 (VT.getScalarSizeInBits() > 16 || Subtarget->hasBWI()))
16662 bool LShift = VT.is128BitVector() ||
16663 (VT.is256BitVector() && Subtarget->hasInt256());
16665 bool AShift = LShift && (Subtarget->hasVLX() ||
16666 (VT != MVT::v2i64 && VT != MVT::v4i64));
16667 return (Opcode == ISD::SRA) ? AShift : LShift;
16670 // The shift amount is a variable, but it is the same for all vector lanes.
16671 // These instrcutions are defined together with shift-immediate.
16673 bool SupportedVectorShiftWithBaseAmnt(MVT VT, const X86Subtarget *Subtarget,
16675 return SupportedVectorShiftWithImm(VT, Subtarget, Opcode);
16678 // Return true if the requred (according to Opcode) variable-shift form is
16679 // natively supported by the Subtarget
16680 static bool SupportedVectorVarShift(MVT VT, const X86Subtarget *Subtarget,
16683 if (!Subtarget->hasInt256() || VT.getScalarSizeInBits() < 16)
16686 // vXi16 supported only on AVX-512, BWI
16687 if (VT.getScalarSizeInBits() == 16 && !Subtarget->hasBWI())
16690 if (VT.is512BitVector() || Subtarget->hasVLX())
16693 bool LShift = VT.is128BitVector() || VT.is256BitVector();
16694 bool AShift = LShift && VT != MVT::v2i64 && VT != MVT::v4i64;
16695 return (Opcode == ISD::SRA) ? AShift : LShift;
16698 static SDValue LowerScalarImmediateShift(SDValue Op, SelectionDAG &DAG,
16699 const X86Subtarget *Subtarget) {
16700 MVT VT = Op.getSimpleValueType();
16702 SDValue R = Op.getOperand(0);
16703 SDValue Amt = Op.getOperand(1);
16705 unsigned X86Opc = (Op.getOpcode() == ISD::SHL) ? X86ISD::VSHLI :
16706 (Op.getOpcode() == ISD::SRL) ? X86ISD::VSRLI : X86ISD::VSRAI;
16708 // Optimize shl/srl/sra with constant shift amount.
16709 if (auto *BVAmt = dyn_cast<BuildVectorSDNode>(Amt)) {
16710 if (auto *ShiftConst = BVAmt->getConstantSplatNode()) {
16711 uint64_t ShiftAmt = ShiftConst->getZExtValue();
16713 if (SupportedVectorShiftWithImm(VT, Subtarget, Op.getOpcode()))
16714 return getTargetVShiftByConstNode(X86Opc, dl, VT, R, ShiftAmt, DAG);
16716 if (VT == MVT::v16i8 || (Subtarget->hasInt256() && VT == MVT::v32i8)) {
16717 unsigned NumElts = VT.getVectorNumElements();
16718 MVT ShiftVT = MVT::getVectorVT(MVT::i16, NumElts / 2);
16720 if (Op.getOpcode() == ISD::SHL) {
16721 // Simple i8 add case
16723 return DAG.getNode(ISD::ADD, dl, VT, R, R);
16725 // Make a large shift.
16726 SDValue SHL = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, ShiftVT,
16728 SHL = DAG.getBitcast(VT, SHL);
16729 // Zero out the rightmost bits.
16730 SmallVector<SDValue, 32> V(
16731 NumElts, DAG.getConstant(uint8_t(-1U << ShiftAmt), dl, MVT::i8));
16732 return DAG.getNode(ISD::AND, dl, VT, SHL,
16733 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V));
16735 if (Op.getOpcode() == ISD::SRL) {
16736 // Make a large shift.
16737 SDValue SRL = getTargetVShiftByConstNode(X86ISD::VSRLI, dl, ShiftVT,
16739 SRL = DAG.getBitcast(VT, SRL);
16740 // Zero out the leftmost bits.
16741 SmallVector<SDValue, 32> V(
16742 NumElts, DAG.getConstant(uint8_t(-1U) >> ShiftAmt, dl, MVT::i8));
16743 return DAG.getNode(ISD::AND, dl, VT, SRL,
16744 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V));
16746 if (Op.getOpcode() == ISD::SRA) {
16747 if (ShiftAmt == 7) {
16748 // R s>> 7 === R s< 0
16749 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
16750 return DAG.getNode(X86ISD::PCMPGT, dl, VT, Zeros, R);
16753 // R s>> a === ((R u>> a) ^ m) - m
16754 SDValue Res = DAG.getNode(ISD::SRL, dl, VT, R, Amt);
16755 SmallVector<SDValue, 32> V(NumElts,
16756 DAG.getConstant(128 >> ShiftAmt, dl,
16758 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V);
16759 Res = DAG.getNode(ISD::XOR, dl, VT, Res, Mask);
16760 Res = DAG.getNode(ISD::SUB, dl, VT, Res, Mask);
16763 llvm_unreachable("Unknown shift opcode.");
16768 // Special case in 32-bit mode, where i64 is expanded into high and low parts.
16769 if (!Subtarget->is64Bit() &&
16770 (VT == MVT::v2i64 || (Subtarget->hasInt256() && VT == MVT::v4i64)) &&
16771 Amt.getOpcode() == ISD::BITCAST &&
16772 Amt.getOperand(0).getOpcode() == ISD::BUILD_VECTOR) {
16773 Amt = Amt.getOperand(0);
16774 unsigned Ratio = Amt.getSimpleValueType().getVectorNumElements() /
16775 VT.getVectorNumElements();
16776 unsigned RatioInLog2 = Log2_32_Ceil(Ratio);
16777 uint64_t ShiftAmt = 0;
16778 for (unsigned i = 0; i != Ratio; ++i) {
16779 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Amt.getOperand(i));
16783 ShiftAmt |= C->getZExtValue() << (i * (1 << (6 - RatioInLog2)));
16785 // Check remaining shift amounts.
16786 for (unsigned i = Ratio; i != Amt.getNumOperands(); i += Ratio) {
16787 uint64_t ShAmt = 0;
16788 for (unsigned j = 0; j != Ratio; ++j) {
16789 ConstantSDNode *C =
16790 dyn_cast<ConstantSDNode>(Amt.getOperand(i + j));
16794 ShAmt |= C->getZExtValue() << (j * (1 << (6 - RatioInLog2)));
16796 if (ShAmt != ShiftAmt)
16799 return getTargetVShiftByConstNode(X86Opc, dl, VT, R, ShiftAmt, DAG);
16805 static SDValue LowerScalarVariableShift(SDValue Op, SelectionDAG &DAG,
16806 const X86Subtarget* Subtarget) {
16807 MVT VT = Op.getSimpleValueType();
16809 SDValue R = Op.getOperand(0);
16810 SDValue Amt = Op.getOperand(1);
16812 unsigned X86OpcI = (Op.getOpcode() == ISD::SHL) ? X86ISD::VSHLI :
16813 (Op.getOpcode() == ISD::SRL) ? X86ISD::VSRLI : X86ISD::VSRAI;
16815 unsigned X86OpcV = (Op.getOpcode() == ISD::SHL) ? X86ISD::VSHL :
16816 (Op.getOpcode() == ISD::SRL) ? X86ISD::VSRL : X86ISD::VSRA;
16818 if (SupportedVectorShiftWithBaseAmnt(VT, Subtarget, Op.getOpcode())) {
16820 EVT EltVT = VT.getVectorElementType();
16822 if (BuildVectorSDNode *BV = dyn_cast<BuildVectorSDNode>(Amt)) {
16823 // Check if this build_vector node is doing a splat.
16824 // If so, then set BaseShAmt equal to the splat value.
16825 BaseShAmt = BV->getSplatValue();
16826 if (BaseShAmt && BaseShAmt.getOpcode() == ISD::UNDEF)
16827 BaseShAmt = SDValue();
16829 if (Amt.getOpcode() == ISD::EXTRACT_SUBVECTOR)
16830 Amt = Amt.getOperand(0);
16832 ShuffleVectorSDNode *SVN = dyn_cast<ShuffleVectorSDNode>(Amt);
16833 if (SVN && SVN->isSplat()) {
16834 unsigned SplatIdx = (unsigned)SVN->getSplatIndex();
16835 SDValue InVec = Amt.getOperand(0);
16836 if (InVec.getOpcode() == ISD::BUILD_VECTOR) {
16837 assert((SplatIdx < InVec.getValueType().getVectorNumElements()) &&
16838 "Unexpected shuffle index found!");
16839 BaseShAmt = InVec.getOperand(SplatIdx);
16840 } else if (InVec.getOpcode() == ISD::INSERT_VECTOR_ELT) {
16841 if (ConstantSDNode *C =
16842 dyn_cast<ConstantSDNode>(InVec.getOperand(2))) {
16843 if (C->getZExtValue() == SplatIdx)
16844 BaseShAmt = InVec.getOperand(1);
16849 // Avoid introducing an extract element from a shuffle.
16850 BaseShAmt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, InVec,
16851 DAG.getIntPtrConstant(SplatIdx, dl));
16855 if (BaseShAmt.getNode()) {
16856 assert(EltVT.bitsLE(MVT::i64) && "Unexpected element type!");
16857 if (EltVT != MVT::i64 && EltVT.bitsGT(MVT::i32))
16858 BaseShAmt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i64, BaseShAmt);
16859 else if (EltVT.bitsLT(MVT::i32))
16860 BaseShAmt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, BaseShAmt);
16862 return getTargetVShiftNode(X86OpcI, dl, VT, R, BaseShAmt, DAG);
16866 // Special case in 32-bit mode, where i64 is expanded into high and low parts.
16867 if (!Subtarget->is64Bit() && VT == MVT::v2i64 &&
16868 Amt.getOpcode() == ISD::BITCAST &&
16869 Amt.getOperand(0).getOpcode() == ISD::BUILD_VECTOR) {
16870 Amt = Amt.getOperand(0);
16871 unsigned Ratio = Amt.getSimpleValueType().getVectorNumElements() /
16872 VT.getVectorNumElements();
16873 std::vector<SDValue> Vals(Ratio);
16874 for (unsigned i = 0; i != Ratio; ++i)
16875 Vals[i] = Amt.getOperand(i);
16876 for (unsigned i = Ratio; i != Amt.getNumOperands(); i += Ratio) {
16877 for (unsigned j = 0; j != Ratio; ++j)
16878 if (Vals[j] != Amt.getOperand(i + j))
16881 return DAG.getNode(X86OpcV, dl, VT, R, Op.getOperand(1));
16886 static SDValue LowerShift(SDValue Op, const X86Subtarget* Subtarget,
16887 SelectionDAG &DAG) {
16888 MVT VT = Op.getSimpleValueType();
16890 SDValue R = Op.getOperand(0);
16891 SDValue Amt = Op.getOperand(1);
16893 assert(VT.isVector() && "Custom lowering only for vector shifts!");
16894 assert(Subtarget->hasSSE2() && "Only custom lower when we have SSE2!");
16896 if (SDValue V = LowerScalarImmediateShift(Op, DAG, Subtarget))
16899 if (SDValue V = LowerScalarVariableShift(Op, DAG, Subtarget))
16902 if (SupportedVectorVarShift(VT, Subtarget, Op.getOpcode()))
16905 // 2i64 vector logical shifts can efficiently avoid scalarization - do the
16906 // shifts per-lane and then shuffle the partial results back together.
16907 if (VT == MVT::v2i64 && Op.getOpcode() != ISD::SRA) {
16908 // Splat the shift amounts so the scalar shifts above will catch it.
16909 SDValue Amt0 = DAG.getVectorShuffle(VT, dl, Amt, Amt, {0, 0});
16910 SDValue Amt1 = DAG.getVectorShuffle(VT, dl, Amt, Amt, {1, 1});
16911 SDValue R0 = DAG.getNode(Op->getOpcode(), dl, VT, R, Amt0);
16912 SDValue R1 = DAG.getNode(Op->getOpcode(), dl, VT, R, Amt1);
16913 return DAG.getVectorShuffle(VT, dl, R0, R1, {0, 3});
16916 // If possible, lower this packed shift into a vector multiply instead of
16917 // expanding it into a sequence of scalar shifts.
16918 // Do this only if the vector shift count is a constant build_vector.
16919 if (Op.getOpcode() == ISD::SHL &&
16920 (VT == MVT::v8i16 || VT == MVT::v4i32 ||
16921 (Subtarget->hasInt256() && VT == MVT::v16i16)) &&
16922 ISD::isBuildVectorOfConstantSDNodes(Amt.getNode())) {
16923 SmallVector<SDValue, 8> Elts;
16924 EVT SVT = VT.getScalarType();
16925 unsigned SVTBits = SVT.getSizeInBits();
16926 const APInt &One = APInt(SVTBits, 1);
16927 unsigned NumElems = VT.getVectorNumElements();
16929 for (unsigned i=0; i !=NumElems; ++i) {
16930 SDValue Op = Amt->getOperand(i);
16931 if (Op->getOpcode() == ISD::UNDEF) {
16932 Elts.push_back(Op);
16936 ConstantSDNode *ND = cast<ConstantSDNode>(Op);
16937 const APInt &C = APInt(SVTBits, ND->getAPIntValue().getZExtValue());
16938 uint64_t ShAmt = C.getZExtValue();
16939 if (ShAmt >= SVTBits) {
16940 Elts.push_back(DAG.getUNDEF(SVT));
16943 Elts.push_back(DAG.getConstant(One.shl(ShAmt), dl, SVT));
16945 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Elts);
16946 return DAG.getNode(ISD::MUL, dl, VT, R, BV);
16949 // Lower SHL with variable shift amount.
16950 if (VT == MVT::v4i32 && Op->getOpcode() == ISD::SHL) {
16951 Op = DAG.getNode(ISD::SHL, dl, VT, Amt, DAG.getConstant(23, dl, VT));
16953 Op = DAG.getNode(ISD::ADD, dl, VT, Op,
16954 DAG.getConstant(0x3f800000U, dl, VT));
16955 Op = DAG.getBitcast(MVT::v4f32, Op);
16956 Op = DAG.getNode(ISD::FP_TO_SINT, dl, VT, Op);
16957 return DAG.getNode(ISD::MUL, dl, VT, Op, R);
16960 // If possible, lower this shift as a sequence of two shifts by
16961 // constant plus a MOVSS/MOVSD instead of scalarizing it.
16963 // (v4i32 (srl A, (build_vector < X, Y, Y, Y>)))
16965 // Could be rewritten as:
16966 // (v4i32 (MOVSS (srl A, <Y,Y,Y,Y>), (srl A, <X,X,X,X>)))
16968 // The advantage is that the two shifts from the example would be
16969 // lowered as X86ISD::VSRLI nodes. This would be cheaper than scalarizing
16970 // the vector shift into four scalar shifts plus four pairs of vector
16972 if ((VT == MVT::v8i16 || VT == MVT::v4i32) &&
16973 ISD::isBuildVectorOfConstantSDNodes(Amt.getNode())) {
16974 unsigned TargetOpcode = X86ISD::MOVSS;
16975 bool CanBeSimplified;
16976 // The splat value for the first packed shift (the 'X' from the example).
16977 SDValue Amt1 = Amt->getOperand(0);
16978 // The splat value for the second packed shift (the 'Y' from the example).
16979 SDValue Amt2 = (VT == MVT::v4i32) ? Amt->getOperand(1) :
16980 Amt->getOperand(2);
16982 // See if it is possible to replace this node with a sequence of
16983 // two shifts followed by a MOVSS/MOVSD
16984 if (VT == MVT::v4i32) {
16985 // Check if it is legal to use a MOVSS.
16986 CanBeSimplified = Amt2 == Amt->getOperand(2) &&
16987 Amt2 == Amt->getOperand(3);
16988 if (!CanBeSimplified) {
16989 // Otherwise, check if we can still simplify this node using a MOVSD.
16990 CanBeSimplified = Amt1 == Amt->getOperand(1) &&
16991 Amt->getOperand(2) == Amt->getOperand(3);
16992 TargetOpcode = X86ISD::MOVSD;
16993 Amt2 = Amt->getOperand(2);
16996 // Do similar checks for the case where the machine value type
16998 CanBeSimplified = Amt1 == Amt->getOperand(1);
16999 for (unsigned i=3; i != 8 && CanBeSimplified; ++i)
17000 CanBeSimplified = Amt2 == Amt->getOperand(i);
17002 if (!CanBeSimplified) {
17003 TargetOpcode = X86ISD::MOVSD;
17004 CanBeSimplified = true;
17005 Amt2 = Amt->getOperand(4);
17006 for (unsigned i=0; i != 4 && CanBeSimplified; ++i)
17007 CanBeSimplified = Amt1 == Amt->getOperand(i);
17008 for (unsigned j=4; j != 8 && CanBeSimplified; ++j)
17009 CanBeSimplified = Amt2 == Amt->getOperand(j);
17013 if (CanBeSimplified && isa<ConstantSDNode>(Amt1) &&
17014 isa<ConstantSDNode>(Amt2)) {
17015 // Replace this node with two shifts followed by a MOVSS/MOVSD.
17016 EVT CastVT = MVT::v4i32;
17018 DAG.getConstant(cast<ConstantSDNode>(Amt1)->getAPIntValue(), dl, VT);
17019 SDValue Shift1 = DAG.getNode(Op->getOpcode(), dl, VT, R, Splat1);
17021 DAG.getConstant(cast<ConstantSDNode>(Amt2)->getAPIntValue(), dl, VT);
17022 SDValue Shift2 = DAG.getNode(Op->getOpcode(), dl, VT, R, Splat2);
17023 if (TargetOpcode == X86ISD::MOVSD)
17024 CastVT = MVT::v2i64;
17025 SDValue BitCast1 = DAG.getBitcast(CastVT, Shift1);
17026 SDValue BitCast2 = DAG.getBitcast(CastVT, Shift2);
17027 SDValue Result = getTargetShuffleNode(TargetOpcode, dl, CastVT, BitCast2,
17029 return DAG.getBitcast(VT, Result);
17033 if (VT == MVT::v16i8 || (VT == MVT::v32i8 && Subtarget->hasInt256())) {
17034 MVT ExtVT = MVT::getVectorVT(MVT::i16, VT.getVectorNumElements() / 2);
17035 unsigned ShiftOpcode = Op->getOpcode();
17037 auto SignBitSelect = [&](MVT SelVT, SDValue Sel, SDValue V0, SDValue V1) {
17038 // On SSE41 targets we make use of the fact that VSELECT lowers
17039 // to PBLENDVB which selects bytes based just on the sign bit.
17040 if (Subtarget->hasSSE41()) {
17041 V0 = DAG.getBitcast(VT, V0);
17042 V1 = DAG.getBitcast(VT, V1);
17043 Sel = DAG.getBitcast(VT, Sel);
17044 return DAG.getBitcast(SelVT,
17045 DAG.getNode(ISD::VSELECT, dl, VT, Sel, V0, V1));
17047 // On pre-SSE41 targets we test for the sign bit by comparing to
17048 // zero - a negative value will set all bits of the lanes to true
17049 // and VSELECT uses that in its OR(AND(V0,C),AND(V1,~C)) lowering.
17050 SDValue Z = getZeroVector(SelVT, Subtarget, DAG, dl);
17051 SDValue C = DAG.getNode(X86ISD::PCMPGT, dl, SelVT, Z, Sel);
17052 return DAG.getNode(ISD::VSELECT, dl, SelVT, C, V0, V1);
17055 // Turn 'a' into a mask suitable for VSELECT: a = a << 5;
17056 // We can safely do this using i16 shifts as we're only interested in
17057 // the 3 lower bits of each byte.
17058 Amt = DAG.getBitcast(ExtVT, Amt);
17059 Amt = DAG.getNode(ISD::SHL, dl, ExtVT, Amt, DAG.getConstant(5, dl, ExtVT));
17060 Amt = DAG.getBitcast(VT, Amt);
17062 if (Op->getOpcode() == ISD::SHL || Op->getOpcode() == ISD::SRL) {
17063 // r = VSELECT(r, shift(r, 4), a);
17065 DAG.getNode(ShiftOpcode, dl, VT, R, DAG.getConstant(4, dl, VT));
17066 R = SignBitSelect(VT, Amt, M, R);
17069 Amt = DAG.getNode(ISD::ADD, dl, VT, Amt, Amt);
17071 // r = VSELECT(r, shift(r, 2), a);
17072 M = DAG.getNode(ShiftOpcode, dl, VT, R, DAG.getConstant(2, dl, VT));
17073 R = SignBitSelect(VT, Amt, M, R);
17076 Amt = DAG.getNode(ISD::ADD, dl, VT, Amt, Amt);
17078 // return VSELECT(r, shift(r, 1), a);
17079 M = DAG.getNode(ShiftOpcode, dl, VT, R, DAG.getConstant(1, dl, VT));
17080 R = SignBitSelect(VT, Amt, M, R);
17084 if (Op->getOpcode() == ISD::SRA) {
17085 // For SRA we need to unpack each byte to the higher byte of a i16 vector
17086 // so we can correctly sign extend. We don't care what happens to the
17088 SDValue ALo = DAG.getNode(X86ISD::UNPCKL, dl, VT, DAG.getUNDEF(VT), Amt);
17089 SDValue AHi = DAG.getNode(X86ISD::UNPCKH, dl, VT, DAG.getUNDEF(VT), Amt);
17090 SDValue RLo = DAG.getNode(X86ISD::UNPCKL, dl, VT, DAG.getUNDEF(VT), R);
17091 SDValue RHi = DAG.getNode(X86ISD::UNPCKH, dl, VT, DAG.getUNDEF(VT), R);
17092 ALo = DAG.getBitcast(ExtVT, ALo);
17093 AHi = DAG.getBitcast(ExtVT, AHi);
17094 RLo = DAG.getBitcast(ExtVT, RLo);
17095 RHi = DAG.getBitcast(ExtVT, RHi);
17097 // r = VSELECT(r, shift(r, 4), a);
17098 SDValue MLo = DAG.getNode(ShiftOpcode, dl, ExtVT, RLo,
17099 DAG.getConstant(4, dl, ExtVT));
17100 SDValue MHi = DAG.getNode(ShiftOpcode, dl, ExtVT, RHi,
17101 DAG.getConstant(4, dl, ExtVT));
17102 RLo = SignBitSelect(ExtVT, ALo, MLo, RLo);
17103 RHi = SignBitSelect(ExtVT, AHi, MHi, RHi);
17106 ALo = DAG.getNode(ISD::ADD, dl, ExtVT, ALo, ALo);
17107 AHi = DAG.getNode(ISD::ADD, dl, ExtVT, AHi, AHi);
17109 // r = VSELECT(r, shift(r, 2), a);
17110 MLo = DAG.getNode(ShiftOpcode, dl, ExtVT, RLo,
17111 DAG.getConstant(2, dl, ExtVT));
17112 MHi = DAG.getNode(ShiftOpcode, dl, ExtVT, RHi,
17113 DAG.getConstant(2, dl, ExtVT));
17114 RLo = SignBitSelect(ExtVT, ALo, MLo, RLo);
17115 RHi = SignBitSelect(ExtVT, AHi, MHi, RHi);
17118 ALo = DAG.getNode(ISD::ADD, dl, ExtVT, ALo, ALo);
17119 AHi = DAG.getNode(ISD::ADD, dl, ExtVT, AHi, AHi);
17121 // r = VSELECT(r, shift(r, 1), a);
17122 MLo = DAG.getNode(ShiftOpcode, dl, ExtVT, RLo,
17123 DAG.getConstant(1, dl, ExtVT));
17124 MHi = DAG.getNode(ShiftOpcode, dl, ExtVT, RHi,
17125 DAG.getConstant(1, dl, ExtVT));
17126 RLo = SignBitSelect(ExtVT, ALo, MLo, RLo);
17127 RHi = SignBitSelect(ExtVT, AHi, MHi, RHi);
17129 // Logical shift the result back to the lower byte, leaving a zero upper
17131 // meaning that we can safely pack with PACKUSWB.
17133 DAG.getNode(ISD::SRL, dl, ExtVT, RLo, DAG.getConstant(8, dl, ExtVT));
17135 DAG.getNode(ISD::SRL, dl, ExtVT, RHi, DAG.getConstant(8, dl, ExtVT));
17136 return DAG.getNode(X86ISD::PACKUS, dl, VT, RLo, RHi);
17140 // It's worth extending once and using the v8i32 shifts for 16-bit types, but
17141 // the extra overheads to get from v16i8 to v8i32 make the existing SSE
17142 // solution better.
17143 if (Subtarget->hasInt256() && VT == MVT::v8i16) {
17144 MVT ExtVT = MVT::v8i32;
17146 Op.getOpcode() == ISD::SRA ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
17147 R = DAG.getNode(ExtOpc, dl, ExtVT, R);
17148 Amt = DAG.getNode(ISD::ANY_EXTEND, dl, ExtVT, Amt);
17149 return DAG.getNode(ISD::TRUNCATE, dl, VT,
17150 DAG.getNode(Op.getOpcode(), dl, ExtVT, R, Amt));
17153 if (Subtarget->hasInt256() && VT == MVT::v16i16) {
17154 MVT ExtVT = MVT::v8i32;
17155 SDValue Z = getZeroVector(VT, Subtarget, DAG, dl);
17156 SDValue ALo = DAG.getNode(X86ISD::UNPCKL, dl, VT, Amt, Z);
17157 SDValue AHi = DAG.getNode(X86ISD::UNPCKH, dl, VT, Amt, Z);
17158 SDValue RLo = DAG.getNode(X86ISD::UNPCKL, dl, VT, R, R);
17159 SDValue RHi = DAG.getNode(X86ISD::UNPCKH, dl, VT, R, R);
17160 ALo = DAG.getBitcast(ExtVT, ALo);
17161 AHi = DAG.getBitcast(ExtVT, AHi);
17162 RLo = DAG.getBitcast(ExtVT, RLo);
17163 RHi = DAG.getBitcast(ExtVT, RHi);
17164 SDValue Lo = DAG.getNode(Op.getOpcode(), dl, ExtVT, RLo, ALo);
17165 SDValue Hi = DAG.getNode(Op.getOpcode(), dl, ExtVT, RHi, AHi);
17166 Lo = DAG.getNode(ISD::SRL, dl, ExtVT, Lo, DAG.getConstant(16, dl, ExtVT));
17167 Hi = DAG.getNode(ISD::SRL, dl, ExtVT, Hi, DAG.getConstant(16, dl, ExtVT));
17168 return DAG.getNode(X86ISD::PACKUS, dl, VT, Lo, Hi);
17171 if (VT == MVT::v8i16) {
17172 unsigned ShiftOpcode = Op->getOpcode();
17174 auto SignBitSelect = [&](SDValue Sel, SDValue V0, SDValue V1) {
17175 // On SSE41 targets we make use of the fact that VSELECT lowers
17176 // to PBLENDVB which selects bytes based just on the sign bit.
17177 if (Subtarget->hasSSE41()) {
17178 MVT ExtVT = MVT::getVectorVT(MVT::i8, VT.getVectorNumElements() * 2);
17179 V0 = DAG.getBitcast(ExtVT, V0);
17180 V1 = DAG.getBitcast(ExtVT, V1);
17181 Sel = DAG.getBitcast(ExtVT, Sel);
17182 return DAG.getBitcast(
17183 VT, DAG.getNode(ISD::VSELECT, dl, ExtVT, Sel, V0, V1));
17185 // On pre-SSE41 targets we splat the sign bit - a negative value will
17186 // set all bits of the lanes to true and VSELECT uses that in
17187 // its OR(AND(V0,C),AND(V1,~C)) lowering.
17189 DAG.getNode(ISD::SRA, dl, VT, Sel, DAG.getConstant(15, dl, VT));
17190 return DAG.getNode(ISD::VSELECT, dl, VT, C, V0, V1);
17193 // Turn 'a' into a mask suitable for VSELECT: a = a << 12;
17194 if (Subtarget->hasSSE41()) {
17195 // On SSE41 targets we need to replicate the shift mask in both
17196 // bytes for PBLENDVB.
17199 DAG.getNode(ISD::SHL, dl, VT, Amt, DAG.getConstant(4, dl, VT)),
17200 DAG.getNode(ISD::SHL, dl, VT, Amt, DAG.getConstant(12, dl, VT)));
17202 Amt = DAG.getNode(ISD::SHL, dl, VT, Amt, DAG.getConstant(12, dl, VT));
17205 // r = VSELECT(r, shift(r, 8), a);
17206 SDValue M = DAG.getNode(ShiftOpcode, dl, VT, R, DAG.getConstant(8, dl, VT));
17207 R = SignBitSelect(Amt, M, R);
17210 Amt = DAG.getNode(ISD::ADD, dl, VT, Amt, Amt);
17212 // r = VSELECT(r, shift(r, 4), a);
17213 M = DAG.getNode(ShiftOpcode, dl, VT, R, DAG.getConstant(4, dl, VT));
17214 R = SignBitSelect(Amt, M, R);
17217 Amt = DAG.getNode(ISD::ADD, dl, VT, Amt, Amt);
17219 // r = VSELECT(r, shift(r, 2), a);
17220 M = DAG.getNode(ShiftOpcode, dl, VT, R, DAG.getConstant(2, dl, VT));
17221 R = SignBitSelect(Amt, M, R);
17224 Amt = DAG.getNode(ISD::ADD, dl, VT, Amt, Amt);
17226 // return VSELECT(r, shift(r, 1), a);
17227 M = DAG.getNode(ShiftOpcode, dl, VT, R, DAG.getConstant(1, dl, VT));
17228 R = SignBitSelect(Amt, M, R);
17232 // Decompose 256-bit shifts into smaller 128-bit shifts.
17233 if (VT.is256BitVector()) {
17234 unsigned NumElems = VT.getVectorNumElements();
17235 MVT EltVT = VT.getVectorElementType();
17236 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
17238 // Extract the two vectors
17239 SDValue V1 = Extract128BitVector(R, 0, DAG, dl);
17240 SDValue V2 = Extract128BitVector(R, NumElems/2, DAG, dl);
17242 // Recreate the shift amount vectors
17243 SDValue Amt1, Amt2;
17244 if (Amt.getOpcode() == ISD::BUILD_VECTOR) {
17245 // Constant shift amount
17246 SmallVector<SDValue, 8> Ops(Amt->op_begin(), Amt->op_begin() + NumElems);
17247 ArrayRef<SDValue> Amt1Csts = makeArrayRef(Ops).slice(0, NumElems / 2);
17248 ArrayRef<SDValue> Amt2Csts = makeArrayRef(Ops).slice(NumElems / 2);
17250 Amt1 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, Amt1Csts);
17251 Amt2 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, Amt2Csts);
17253 // Variable shift amount
17254 Amt1 = Extract128BitVector(Amt, 0, DAG, dl);
17255 Amt2 = Extract128BitVector(Amt, NumElems/2, DAG, dl);
17258 // Issue new vector shifts for the smaller types
17259 V1 = DAG.getNode(Op.getOpcode(), dl, NewVT, V1, Amt1);
17260 V2 = DAG.getNode(Op.getOpcode(), dl, NewVT, V2, Amt2);
17262 // Concatenate the result back
17263 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, V1, V2);
17269 static SDValue LowerXALUO(SDValue Op, SelectionDAG &DAG) {
17270 // Lower the "add/sub/mul with overflow" instruction into a regular ins plus
17271 // a "setcc" instruction that checks the overflow flag. The "brcond" lowering
17272 // looks for this combo and may remove the "setcc" instruction if the "setcc"
17273 // has only one use.
17274 SDNode *N = Op.getNode();
17275 SDValue LHS = N->getOperand(0);
17276 SDValue RHS = N->getOperand(1);
17277 unsigned BaseOp = 0;
17280 switch (Op.getOpcode()) {
17281 default: llvm_unreachable("Unknown ovf instruction!");
17283 // A subtract of one will be selected as a INC. Note that INC doesn't
17284 // set CF, so we can't do this for UADDO.
17285 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
17287 BaseOp = X86ISD::INC;
17288 Cond = X86::COND_O;
17291 BaseOp = X86ISD::ADD;
17292 Cond = X86::COND_O;
17295 BaseOp = X86ISD::ADD;
17296 Cond = X86::COND_B;
17299 // A subtract of one will be selected as a DEC. Note that DEC doesn't
17300 // set CF, so we can't do this for USUBO.
17301 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
17303 BaseOp = X86ISD::DEC;
17304 Cond = X86::COND_O;
17307 BaseOp = X86ISD::SUB;
17308 Cond = X86::COND_O;
17311 BaseOp = X86ISD::SUB;
17312 Cond = X86::COND_B;
17315 BaseOp = N->getValueType(0) == MVT::i8 ? X86ISD::SMUL8 : X86ISD::SMUL;
17316 Cond = X86::COND_O;
17318 case ISD::UMULO: { // i64, i8 = umulo lhs, rhs --> i64, i64, i32 umul lhs,rhs
17319 if (N->getValueType(0) == MVT::i8) {
17320 BaseOp = X86ISD::UMUL8;
17321 Cond = X86::COND_O;
17324 SDVTList VTs = DAG.getVTList(N->getValueType(0), N->getValueType(0),
17326 SDValue Sum = DAG.getNode(X86ISD::UMUL, DL, VTs, LHS, RHS);
17329 DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
17330 DAG.getConstant(X86::COND_O, DL, MVT::i32),
17331 SDValue(Sum.getNode(), 2));
17333 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
17337 // Also sets EFLAGS.
17338 SDVTList VTs = DAG.getVTList(N->getValueType(0), MVT::i32);
17339 SDValue Sum = DAG.getNode(BaseOp, DL, VTs, LHS, RHS);
17342 DAG.getNode(X86ISD::SETCC, DL, N->getValueType(1),
17343 DAG.getConstant(Cond, DL, MVT::i32),
17344 SDValue(Sum.getNode(), 1));
17346 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
17349 /// Returns true if the operand type is exactly twice the native width, and
17350 /// the corresponding cmpxchg8b or cmpxchg16b instruction is available.
17351 /// Used to know whether to use cmpxchg8/16b when expanding atomic operations
17352 /// (otherwise we leave them alone to become __sync_fetch_and_... calls).
17353 bool X86TargetLowering::needsCmpXchgNb(const Type *MemType) const {
17354 unsigned OpWidth = MemType->getPrimitiveSizeInBits();
17357 return !Subtarget->is64Bit(); // FIXME this should be Subtarget.hasCmpxchg8b
17358 else if (OpWidth == 128)
17359 return Subtarget->hasCmpxchg16b();
17364 bool X86TargetLowering::shouldExpandAtomicStoreInIR(StoreInst *SI) const {
17365 return needsCmpXchgNb(SI->getValueOperand()->getType());
17368 // Note: this turns large loads into lock cmpxchg8b/16b.
17369 // FIXME: On 32 bits x86, fild/movq might be faster than lock cmpxchg8b.
17370 bool X86TargetLowering::shouldExpandAtomicLoadInIR(LoadInst *LI) const {
17371 auto PTy = cast<PointerType>(LI->getPointerOperand()->getType());
17372 return needsCmpXchgNb(PTy->getElementType());
17375 TargetLoweringBase::AtomicRMWExpansionKind
17376 X86TargetLowering::shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const {
17377 unsigned NativeWidth = Subtarget->is64Bit() ? 64 : 32;
17378 const Type *MemType = AI->getType();
17380 // If the operand is too big, we must see if cmpxchg8/16b is available
17381 // and default to library calls otherwise.
17382 if (MemType->getPrimitiveSizeInBits() > NativeWidth) {
17383 return needsCmpXchgNb(MemType) ? AtomicRMWExpansionKind::CmpXChg
17384 : AtomicRMWExpansionKind::None;
17387 AtomicRMWInst::BinOp Op = AI->getOperation();
17390 llvm_unreachable("Unknown atomic operation");
17391 case AtomicRMWInst::Xchg:
17392 case AtomicRMWInst::Add:
17393 case AtomicRMWInst::Sub:
17394 // It's better to use xadd, xsub or xchg for these in all cases.
17395 return AtomicRMWExpansionKind::None;
17396 case AtomicRMWInst::Or:
17397 case AtomicRMWInst::And:
17398 case AtomicRMWInst::Xor:
17399 // If the atomicrmw's result isn't actually used, we can just add a "lock"
17400 // prefix to a normal instruction for these operations.
17401 return !AI->use_empty() ? AtomicRMWExpansionKind::CmpXChg
17402 : AtomicRMWExpansionKind::None;
17403 case AtomicRMWInst::Nand:
17404 case AtomicRMWInst::Max:
17405 case AtomicRMWInst::Min:
17406 case AtomicRMWInst::UMax:
17407 case AtomicRMWInst::UMin:
17408 // These always require a non-trivial set of data operations on x86. We must
17409 // use a cmpxchg loop.
17410 return AtomicRMWExpansionKind::CmpXChg;
17414 static bool hasMFENCE(const X86Subtarget& Subtarget) {
17415 // Use mfence if we have SSE2 or we're on x86-64 (even if we asked for
17416 // no-sse2). There isn't any reason to disable it if the target processor
17418 return Subtarget.hasSSE2() || Subtarget.is64Bit();
17422 X86TargetLowering::lowerIdempotentRMWIntoFencedLoad(AtomicRMWInst *AI) const {
17423 unsigned NativeWidth = Subtarget->is64Bit() ? 64 : 32;
17424 const Type *MemType = AI->getType();
17425 // Accesses larger than the native width are turned into cmpxchg/libcalls, so
17426 // there is no benefit in turning such RMWs into loads, and it is actually
17427 // harmful as it introduces a mfence.
17428 if (MemType->getPrimitiveSizeInBits() > NativeWidth)
17431 auto Builder = IRBuilder<>(AI);
17432 Module *M = Builder.GetInsertBlock()->getParent()->getParent();
17433 auto SynchScope = AI->getSynchScope();
17434 // We must restrict the ordering to avoid generating loads with Release or
17435 // ReleaseAcquire orderings.
17436 auto Order = AtomicCmpXchgInst::getStrongestFailureOrdering(AI->getOrdering());
17437 auto Ptr = AI->getPointerOperand();
17439 // Before the load we need a fence. Here is an example lifted from
17440 // http://www.hpl.hp.com/techreports/2012/HPL-2012-68.pdf showing why a fence
17443 // x.store(1, relaxed);
17444 // r1 = y.fetch_add(0, release);
17446 // y.fetch_add(42, acquire);
17447 // r2 = x.load(relaxed);
17448 // r1 = r2 = 0 is impossible, but becomes possible if the idempotent rmw is
17449 // lowered to just a load without a fence. A mfence flushes the store buffer,
17450 // making the optimization clearly correct.
17451 // FIXME: it is required if isAtLeastRelease(Order) but it is not clear
17452 // otherwise, we might be able to be more agressive on relaxed idempotent
17453 // rmw. In practice, they do not look useful, so we don't try to be
17454 // especially clever.
17455 if (SynchScope == SingleThread)
17456 // FIXME: we could just insert an X86ISD::MEMBARRIER here, except we are at
17457 // the IR level, so we must wrap it in an intrinsic.
17460 if (!hasMFENCE(*Subtarget))
17461 // FIXME: it might make sense to use a locked operation here but on a
17462 // different cache-line to prevent cache-line bouncing. In practice it
17463 // is probably a small win, and x86 processors without mfence are rare
17464 // enough that we do not bother.
17468 llvm::Intrinsic::getDeclaration(M, Intrinsic::x86_sse2_mfence);
17469 Builder.CreateCall(MFence, {});
17471 // Finally we can emit the atomic load.
17472 LoadInst *Loaded = Builder.CreateAlignedLoad(Ptr,
17473 AI->getType()->getPrimitiveSizeInBits());
17474 Loaded->setAtomic(Order, SynchScope);
17475 AI->replaceAllUsesWith(Loaded);
17476 AI->eraseFromParent();
17480 static SDValue LowerATOMIC_FENCE(SDValue Op, const X86Subtarget *Subtarget,
17481 SelectionDAG &DAG) {
17483 AtomicOrdering FenceOrdering = static_cast<AtomicOrdering>(
17484 cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue());
17485 SynchronizationScope FenceScope = static_cast<SynchronizationScope>(
17486 cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue());
17488 // The only fence that needs an instruction is a sequentially-consistent
17489 // cross-thread fence.
17490 if (FenceOrdering == SequentiallyConsistent && FenceScope == CrossThread) {
17491 if (hasMFENCE(*Subtarget))
17492 return DAG.getNode(X86ISD::MFENCE, dl, MVT::Other, Op.getOperand(0));
17494 SDValue Chain = Op.getOperand(0);
17495 SDValue Zero = DAG.getConstant(0, dl, MVT::i32);
17497 DAG.getRegister(X86::ESP, MVT::i32), // Base
17498 DAG.getTargetConstant(1, dl, MVT::i8), // Scale
17499 DAG.getRegister(0, MVT::i32), // Index
17500 DAG.getTargetConstant(0, dl, MVT::i32), // Disp
17501 DAG.getRegister(0, MVT::i32), // Segment.
17505 SDNode *Res = DAG.getMachineNode(X86::OR32mrLocked, dl, MVT::Other, Ops);
17506 return SDValue(Res, 0);
17509 // MEMBARRIER is a compiler barrier; it codegens to a no-op.
17510 return DAG.getNode(X86ISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0));
17513 static SDValue LowerCMP_SWAP(SDValue Op, const X86Subtarget *Subtarget,
17514 SelectionDAG &DAG) {
17515 MVT T = Op.getSimpleValueType();
17519 switch(T.SimpleTy) {
17520 default: llvm_unreachable("Invalid value type!");
17521 case MVT::i8: Reg = X86::AL; size = 1; break;
17522 case MVT::i16: Reg = X86::AX; size = 2; break;
17523 case MVT::i32: Reg = X86::EAX; size = 4; break;
17525 assert(Subtarget->is64Bit() && "Node not type legal!");
17526 Reg = X86::RAX; size = 8;
17529 SDValue cpIn = DAG.getCopyToReg(Op.getOperand(0), DL, Reg,
17530 Op.getOperand(2), SDValue());
17531 SDValue Ops[] = { cpIn.getValue(0),
17534 DAG.getTargetConstant(size, DL, MVT::i8),
17535 cpIn.getValue(1) };
17536 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
17537 MachineMemOperand *MMO = cast<AtomicSDNode>(Op)->getMemOperand();
17538 SDValue Result = DAG.getMemIntrinsicNode(X86ISD::LCMPXCHG_DAG, DL, Tys,
17542 DAG.getCopyFromReg(Result.getValue(0), DL, Reg, T, Result.getValue(1));
17543 SDValue EFLAGS = DAG.getCopyFromReg(cpOut.getValue(1), DL, X86::EFLAGS,
17544 MVT::i32, cpOut.getValue(2));
17545 SDValue Success = DAG.getNode(X86ISD::SETCC, DL, Op->getValueType(1),
17546 DAG.getConstant(X86::COND_E, DL, MVT::i8),
17549 DAG.ReplaceAllUsesOfValueWith(Op.getValue(0), cpOut);
17550 DAG.ReplaceAllUsesOfValueWith(Op.getValue(1), Success);
17551 DAG.ReplaceAllUsesOfValueWith(Op.getValue(2), EFLAGS.getValue(1));
17555 static SDValue LowerBITCAST(SDValue Op, const X86Subtarget *Subtarget,
17556 SelectionDAG &DAG) {
17557 MVT SrcVT = Op.getOperand(0).getSimpleValueType();
17558 MVT DstVT = Op.getSimpleValueType();
17560 if (SrcVT == MVT::v2i32 || SrcVT == MVT::v4i16 || SrcVT == MVT::v8i8) {
17561 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
17562 if (DstVT != MVT::f64)
17563 // This conversion needs to be expanded.
17566 SDValue InVec = Op->getOperand(0);
17568 unsigned NumElts = SrcVT.getVectorNumElements();
17569 EVT SVT = SrcVT.getVectorElementType();
17571 // Widen the vector in input in the case of MVT::v2i32.
17572 // Example: from MVT::v2i32 to MVT::v4i32.
17573 SmallVector<SDValue, 16> Elts;
17574 for (unsigned i = 0, e = NumElts; i != e; ++i)
17575 Elts.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, SVT, InVec,
17576 DAG.getIntPtrConstant(i, dl)));
17578 // Explicitly mark the extra elements as Undef.
17579 Elts.append(NumElts, DAG.getUNDEF(SVT));
17581 EVT NewVT = EVT::getVectorVT(*DAG.getContext(), SVT, NumElts * 2);
17582 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, Elts);
17583 SDValue ToV2F64 = DAG.getBitcast(MVT::v2f64, BV);
17584 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, ToV2F64,
17585 DAG.getIntPtrConstant(0, dl));
17588 assert(Subtarget->is64Bit() && !Subtarget->hasSSE2() &&
17589 Subtarget->hasMMX() && "Unexpected custom BITCAST");
17590 assert((DstVT == MVT::i64 ||
17591 (DstVT.isVector() && DstVT.getSizeInBits()==64)) &&
17592 "Unexpected custom BITCAST");
17593 // i64 <=> MMX conversions are Legal.
17594 if (SrcVT==MVT::i64 && DstVT.isVector())
17596 if (DstVT==MVT::i64 && SrcVT.isVector())
17598 // MMX <=> MMX conversions are Legal.
17599 if (SrcVT.isVector() && DstVT.isVector())
17601 // All other conversions need to be expanded.
17605 /// Compute the horizontal sum of bytes in V for the elements of VT.
17607 /// Requires V to be a byte vector and VT to be an integer vector type with
17608 /// wider elements than V's type. The width of the elements of VT determines
17609 /// how many bytes of V are summed horizontally to produce each element of the
17611 static SDValue LowerHorizontalByteSum(SDValue V, MVT VT,
17612 const X86Subtarget *Subtarget,
17613 SelectionDAG &DAG) {
17615 MVT ByteVecVT = V.getSimpleValueType();
17616 MVT EltVT = VT.getVectorElementType();
17617 int NumElts = VT.getVectorNumElements();
17618 assert(ByteVecVT.getVectorElementType() == MVT::i8 &&
17619 "Expected value to have byte element type.");
17620 assert(EltVT != MVT::i8 &&
17621 "Horizontal byte sum only makes sense for wider elements!");
17622 unsigned VecSize = VT.getSizeInBits();
17623 assert(ByteVecVT.getSizeInBits() == VecSize && "Cannot change vector size!");
17625 // PSADBW instruction horizontally add all bytes and leave the result in i64
17626 // chunks, thus directly computes the pop count for v2i64 and v4i64.
17627 if (EltVT == MVT::i64) {
17628 SDValue Zeros = getZeroVector(ByteVecVT, Subtarget, DAG, DL);
17629 V = DAG.getNode(X86ISD::PSADBW, DL, ByteVecVT, V, Zeros);
17630 return DAG.getBitcast(VT, V);
17633 if (EltVT == MVT::i32) {
17634 // We unpack the low half and high half into i32s interleaved with zeros so
17635 // that we can use PSADBW to horizontally sum them. The most useful part of
17636 // this is that it lines up the results of two PSADBW instructions to be
17637 // two v2i64 vectors which concatenated are the 4 population counts. We can
17638 // then use PACKUSWB to shrink and concatenate them into a v4i32 again.
17639 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, DL);
17640 SDValue Low = DAG.getNode(X86ISD::UNPCKL, DL, VT, V, Zeros);
17641 SDValue High = DAG.getNode(X86ISD::UNPCKH, DL, VT, V, Zeros);
17643 // Do the horizontal sums into two v2i64s.
17644 Zeros = getZeroVector(ByteVecVT, Subtarget, DAG, DL);
17645 Low = DAG.getNode(X86ISD::PSADBW, DL, ByteVecVT,
17646 DAG.getBitcast(ByteVecVT, Low), Zeros);
17647 High = DAG.getNode(X86ISD::PSADBW, DL, ByteVecVT,
17648 DAG.getBitcast(ByteVecVT, High), Zeros);
17650 // Merge them together.
17651 MVT ShortVecVT = MVT::getVectorVT(MVT::i16, VecSize / 16);
17652 V = DAG.getNode(X86ISD::PACKUS, DL, ByteVecVT,
17653 DAG.getBitcast(ShortVecVT, Low),
17654 DAG.getBitcast(ShortVecVT, High));
17656 return DAG.getBitcast(VT, V);
17659 // The only element type left is i16.
17660 assert(EltVT == MVT::i16 && "Unknown how to handle type");
17662 // To obtain pop count for each i16 element starting from the pop count for
17663 // i8 elements, shift the i16s left by 8, sum as i8s, and then shift as i16s
17664 // right by 8. It is important to shift as i16s as i8 vector shift isn't
17665 // directly supported.
17666 SmallVector<SDValue, 16> Shifters(NumElts, DAG.getConstant(8, DL, EltVT));
17667 SDValue Shifter = DAG.getNode(ISD::BUILD_VECTOR, DL, VT, Shifters);
17668 SDValue Shl = DAG.getNode(ISD::SHL, DL, VT, DAG.getBitcast(VT, V), Shifter);
17669 V = DAG.getNode(ISD::ADD, DL, ByteVecVT, DAG.getBitcast(ByteVecVT, Shl),
17670 DAG.getBitcast(ByteVecVT, V));
17671 return DAG.getNode(ISD::SRL, DL, VT, DAG.getBitcast(VT, V), Shifter);
17674 static SDValue LowerVectorCTPOPInRegLUT(SDValue Op, SDLoc DL,
17675 const X86Subtarget *Subtarget,
17676 SelectionDAG &DAG) {
17677 MVT VT = Op.getSimpleValueType();
17678 MVT EltVT = VT.getVectorElementType();
17679 unsigned VecSize = VT.getSizeInBits();
17681 // Implement a lookup table in register by using an algorithm based on:
17682 // http://wm.ite.pl/articles/sse-popcount.html
17684 // The general idea is that every lower byte nibble in the input vector is an
17685 // index into a in-register pre-computed pop count table. We then split up the
17686 // input vector in two new ones: (1) a vector with only the shifted-right
17687 // higher nibbles for each byte and (2) a vector with the lower nibbles (and
17688 // masked out higher ones) for each byte. PSHUB is used separately with both
17689 // to index the in-register table. Next, both are added and the result is a
17690 // i8 vector where each element contains the pop count for input byte.
17692 // To obtain the pop count for elements != i8, we follow up with the same
17693 // approach and use additional tricks as described below.
17695 const int LUT[16] = {/* 0 */ 0, /* 1 */ 1, /* 2 */ 1, /* 3 */ 2,
17696 /* 4 */ 1, /* 5 */ 2, /* 6 */ 2, /* 7 */ 3,
17697 /* 8 */ 1, /* 9 */ 2, /* a */ 2, /* b */ 3,
17698 /* c */ 2, /* d */ 3, /* e */ 3, /* f */ 4};
17700 int NumByteElts = VecSize / 8;
17701 MVT ByteVecVT = MVT::getVectorVT(MVT::i8, NumByteElts);
17702 SDValue In = DAG.getBitcast(ByteVecVT, Op);
17703 SmallVector<SDValue, 16> LUTVec;
17704 for (int i = 0; i < NumByteElts; ++i)
17705 LUTVec.push_back(DAG.getConstant(LUT[i % 16], DL, MVT::i8));
17706 SDValue InRegLUT = DAG.getNode(ISD::BUILD_VECTOR, DL, ByteVecVT, LUTVec);
17707 SmallVector<SDValue, 16> Mask0F(NumByteElts,
17708 DAG.getConstant(0x0F, DL, MVT::i8));
17709 SDValue M0F = DAG.getNode(ISD::BUILD_VECTOR, DL, ByteVecVT, Mask0F);
17712 SmallVector<SDValue, 16> Four(NumByteElts, DAG.getConstant(4, DL, MVT::i8));
17713 SDValue FourV = DAG.getNode(ISD::BUILD_VECTOR, DL, ByteVecVT, Four);
17714 SDValue HighNibbles = DAG.getNode(ISD::SRL, DL, ByteVecVT, In, FourV);
17717 SDValue LowNibbles = DAG.getNode(ISD::AND, DL, ByteVecVT, In, M0F);
17719 // The input vector is used as the shuffle mask that index elements into the
17720 // LUT. After counting low and high nibbles, add the vector to obtain the
17721 // final pop count per i8 element.
17722 SDValue HighPopCnt =
17723 DAG.getNode(X86ISD::PSHUFB, DL, ByteVecVT, InRegLUT, HighNibbles);
17724 SDValue LowPopCnt =
17725 DAG.getNode(X86ISD::PSHUFB, DL, ByteVecVT, InRegLUT, LowNibbles);
17726 SDValue PopCnt = DAG.getNode(ISD::ADD, DL, ByteVecVT, HighPopCnt, LowPopCnt);
17728 if (EltVT == MVT::i8)
17731 return LowerHorizontalByteSum(PopCnt, VT, Subtarget, DAG);
17734 static SDValue LowerVectorCTPOPBitmath(SDValue Op, SDLoc DL,
17735 const X86Subtarget *Subtarget,
17736 SelectionDAG &DAG) {
17737 MVT VT = Op.getSimpleValueType();
17738 assert(VT.is128BitVector() &&
17739 "Only 128-bit vector bitmath lowering supported.");
17741 int VecSize = VT.getSizeInBits();
17742 MVT EltVT = VT.getVectorElementType();
17743 int Len = EltVT.getSizeInBits();
17745 // This is the vectorized version of the "best" algorithm from
17746 // http://graphics.stanford.edu/~seander/bithacks.html#CountBitsSetParallel
17747 // with a minor tweak to use a series of adds + shifts instead of vector
17748 // multiplications. Implemented for all integer vector types. We only use
17749 // this when we don't have SSSE3 which allows a LUT-based lowering that is
17750 // much faster, even faster than using native popcnt instructions.
17752 auto GetShift = [&](unsigned OpCode, SDValue V, int Shifter) {
17753 MVT VT = V.getSimpleValueType();
17754 SmallVector<SDValue, 32> Shifters(
17755 VT.getVectorNumElements(),
17756 DAG.getConstant(Shifter, DL, VT.getVectorElementType()));
17757 return DAG.getNode(OpCode, DL, VT, V,
17758 DAG.getNode(ISD::BUILD_VECTOR, DL, VT, Shifters));
17760 auto GetMask = [&](SDValue V, APInt Mask) {
17761 MVT VT = V.getSimpleValueType();
17762 SmallVector<SDValue, 32> Masks(
17763 VT.getVectorNumElements(),
17764 DAG.getConstant(Mask, DL, VT.getVectorElementType()));
17765 return DAG.getNode(ISD::AND, DL, VT, V,
17766 DAG.getNode(ISD::BUILD_VECTOR, DL, VT, Masks));
17769 // We don't want to incur the implicit masks required to SRL vNi8 vectors on
17770 // x86, so set the SRL type to have elements at least i16 wide. This is
17771 // correct because all of our SRLs are followed immediately by a mask anyways
17772 // that handles any bits that sneak into the high bits of the byte elements.
17773 MVT SrlVT = Len > 8 ? VT : MVT::getVectorVT(MVT::i16, VecSize / 16);
17777 // v = v - ((v >> 1) & 0x55555555...)
17779 DAG.getBitcast(VT, GetShift(ISD::SRL, DAG.getBitcast(SrlVT, V), 1));
17780 SDValue And = GetMask(Srl, APInt::getSplat(Len, APInt(8, 0x55)));
17781 V = DAG.getNode(ISD::SUB, DL, VT, V, And);
17783 // v = (v & 0x33333333...) + ((v >> 2) & 0x33333333...)
17784 SDValue AndLHS = GetMask(V, APInt::getSplat(Len, APInt(8, 0x33)));
17785 Srl = DAG.getBitcast(VT, GetShift(ISD::SRL, DAG.getBitcast(SrlVT, V), 2));
17786 SDValue AndRHS = GetMask(Srl, APInt::getSplat(Len, APInt(8, 0x33)));
17787 V = DAG.getNode(ISD::ADD, DL, VT, AndLHS, AndRHS);
17789 // v = (v + (v >> 4)) & 0x0F0F0F0F...
17790 Srl = DAG.getBitcast(VT, GetShift(ISD::SRL, DAG.getBitcast(SrlVT, V), 4));
17791 SDValue Add = DAG.getNode(ISD::ADD, DL, VT, V, Srl);
17792 V = GetMask(Add, APInt::getSplat(Len, APInt(8, 0x0F)));
17794 // At this point, V contains the byte-wise population count, and we are
17795 // merely doing a horizontal sum if necessary to get the wider element
17797 if (EltVT == MVT::i8)
17800 return LowerHorizontalByteSum(
17801 DAG.getBitcast(MVT::getVectorVT(MVT::i8, VecSize / 8), V), VT, Subtarget,
17805 static SDValue LowerVectorCTPOP(SDValue Op, const X86Subtarget *Subtarget,
17806 SelectionDAG &DAG) {
17807 MVT VT = Op.getSimpleValueType();
17808 // FIXME: Need to add AVX-512 support here!
17809 assert((VT.is256BitVector() || VT.is128BitVector()) &&
17810 "Unknown CTPOP type to handle");
17811 SDLoc DL(Op.getNode());
17812 SDValue Op0 = Op.getOperand(0);
17814 if (!Subtarget->hasSSSE3()) {
17815 // We can't use the fast LUT approach, so fall back on vectorized bitmath.
17816 assert(VT.is128BitVector() && "Only 128-bit vectors supported in SSE!");
17817 return LowerVectorCTPOPBitmath(Op0, DL, Subtarget, DAG);
17820 if (VT.is256BitVector() && !Subtarget->hasInt256()) {
17821 unsigned NumElems = VT.getVectorNumElements();
17823 // Extract each 128-bit vector, compute pop count and concat the result.
17824 SDValue LHS = Extract128BitVector(Op0, 0, DAG, DL);
17825 SDValue RHS = Extract128BitVector(Op0, NumElems/2, DAG, DL);
17827 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT,
17828 LowerVectorCTPOPInRegLUT(LHS, DL, Subtarget, DAG),
17829 LowerVectorCTPOPInRegLUT(RHS, DL, Subtarget, DAG));
17832 return LowerVectorCTPOPInRegLUT(Op0, DL, Subtarget, DAG);
17835 static SDValue LowerCTPOP(SDValue Op, const X86Subtarget *Subtarget,
17836 SelectionDAG &DAG) {
17837 assert(Op.getValueType().isVector() &&
17838 "We only do custom lowering for vector population count.");
17839 return LowerVectorCTPOP(Op, Subtarget, DAG);
17842 static SDValue LowerLOAD_SUB(SDValue Op, SelectionDAG &DAG) {
17843 SDNode *Node = Op.getNode();
17845 EVT T = Node->getValueType(0);
17846 SDValue negOp = DAG.getNode(ISD::SUB, dl, T,
17847 DAG.getConstant(0, dl, T), Node->getOperand(2));
17848 return DAG.getAtomic(ISD::ATOMIC_LOAD_ADD, dl,
17849 cast<AtomicSDNode>(Node)->getMemoryVT(),
17850 Node->getOperand(0),
17851 Node->getOperand(1), negOp,
17852 cast<AtomicSDNode>(Node)->getMemOperand(),
17853 cast<AtomicSDNode>(Node)->getOrdering(),
17854 cast<AtomicSDNode>(Node)->getSynchScope());
17857 static SDValue LowerATOMIC_STORE(SDValue Op, SelectionDAG &DAG) {
17858 SDNode *Node = Op.getNode();
17860 EVT VT = cast<AtomicSDNode>(Node)->getMemoryVT();
17862 // Convert seq_cst store -> xchg
17863 // Convert wide store -> swap (-> cmpxchg8b/cmpxchg16b)
17864 // FIXME: On 32-bit, store -> fist or movq would be more efficient
17865 // (The only way to get a 16-byte store is cmpxchg16b)
17866 // FIXME: 16-byte ATOMIC_SWAP isn't actually hooked up at the moment.
17867 if (cast<AtomicSDNode>(Node)->getOrdering() == SequentiallyConsistent ||
17868 !DAG.getTargetLoweringInfo().isTypeLegal(VT)) {
17869 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_SWAP, dl,
17870 cast<AtomicSDNode>(Node)->getMemoryVT(),
17871 Node->getOperand(0),
17872 Node->getOperand(1), Node->getOperand(2),
17873 cast<AtomicSDNode>(Node)->getMemOperand(),
17874 cast<AtomicSDNode>(Node)->getOrdering(),
17875 cast<AtomicSDNode>(Node)->getSynchScope());
17876 return Swap.getValue(1);
17878 // Other atomic stores have a simple pattern.
17882 static SDValue LowerADDC_ADDE_SUBC_SUBE(SDValue Op, SelectionDAG &DAG) {
17883 EVT VT = Op.getNode()->getSimpleValueType(0);
17885 // Let legalize expand this if it isn't a legal type yet.
17886 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
17889 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
17892 bool ExtraOp = false;
17893 switch (Op.getOpcode()) {
17894 default: llvm_unreachable("Invalid code");
17895 case ISD::ADDC: Opc = X86ISD::ADD; break;
17896 case ISD::ADDE: Opc = X86ISD::ADC; ExtraOp = true; break;
17897 case ISD::SUBC: Opc = X86ISD::SUB; break;
17898 case ISD::SUBE: Opc = X86ISD::SBB; ExtraOp = true; break;
17902 return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0),
17904 return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0),
17905 Op.getOperand(1), Op.getOperand(2));
17908 static SDValue LowerFSINCOS(SDValue Op, const X86Subtarget *Subtarget,
17909 SelectionDAG &DAG) {
17910 assert(Subtarget->isTargetDarwin() && Subtarget->is64Bit());
17912 // For MacOSX, we want to call an alternative entry point: __sincos_stret,
17913 // which returns the values as { float, float } (in XMM0) or
17914 // { double, double } (which is returned in XMM0, XMM1).
17916 SDValue Arg = Op.getOperand(0);
17917 EVT ArgVT = Arg.getValueType();
17918 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
17920 TargetLowering::ArgListTy Args;
17921 TargetLowering::ArgListEntry Entry;
17925 Entry.isSExt = false;
17926 Entry.isZExt = false;
17927 Args.push_back(Entry);
17929 bool isF64 = ArgVT == MVT::f64;
17930 // Only optimize x86_64 for now. i386 is a bit messy. For f32,
17931 // the small struct {f32, f32} is returned in (eax, edx). For f64,
17932 // the results are returned via SRet in memory.
17933 const char *LibcallName = isF64 ? "__sincos_stret" : "__sincosf_stret";
17934 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
17935 SDValue Callee = DAG.getExternalSymbol(LibcallName, TLI.getPointerTy());
17937 Type *RetTy = isF64
17938 ? (Type*)StructType::get(ArgTy, ArgTy, nullptr)
17939 : (Type*)VectorType::get(ArgTy, 4);
17941 TargetLowering::CallLoweringInfo CLI(DAG);
17942 CLI.setDebugLoc(dl).setChain(DAG.getEntryNode())
17943 .setCallee(CallingConv::C, RetTy, Callee, std::move(Args), 0);
17945 std::pair<SDValue, SDValue> CallResult = TLI.LowerCallTo(CLI);
17948 // Returned in xmm0 and xmm1.
17949 return CallResult.first;
17951 // Returned in bits 0:31 and 32:64 xmm0.
17952 SDValue SinVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ArgVT,
17953 CallResult.first, DAG.getIntPtrConstant(0, dl));
17954 SDValue CosVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ArgVT,
17955 CallResult.first, DAG.getIntPtrConstant(1, dl));
17956 SDVTList Tys = DAG.getVTList(ArgVT, ArgVT);
17957 return DAG.getNode(ISD::MERGE_VALUES, dl, Tys, SinVal, CosVal);
17960 static SDValue LowerMSCATTER(SDValue Op, const X86Subtarget *Subtarget,
17961 SelectionDAG &DAG) {
17962 assert(Subtarget->hasAVX512() &&
17963 "MGATHER/MSCATTER are supported on AVX-512 arch only");
17965 MaskedScatterSDNode *N = cast<MaskedScatterSDNode>(Op.getNode());
17966 EVT VT = N->getValue().getValueType();
17967 assert(VT.getScalarSizeInBits() >= 32 && "Unsupported scatter op");
17970 // X86 scatter kills mask register, so its type should be added to
17971 // the list of return values
17972 if (N->getNumValues() == 1) {
17973 SDValue Index = N->getIndex();
17974 if (!Subtarget->hasVLX() && !VT.is512BitVector() &&
17975 !Index.getValueType().is512BitVector())
17976 Index = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v8i64, Index);
17978 SDVTList VTs = DAG.getVTList(N->getMask().getValueType(), MVT::Other);
17979 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), N->getOperand(2),
17980 N->getOperand(3), Index };
17982 SDValue NewScatter = DAG.getMaskedScatter(VTs, VT, dl, Ops, N->getMemOperand());
17983 DAG.ReplaceAllUsesWith(Op, SDValue(NewScatter.getNode(), 1));
17984 return SDValue(NewScatter.getNode(), 0);
17989 static SDValue LowerMGATHER(SDValue Op, const X86Subtarget *Subtarget,
17990 SelectionDAG &DAG) {
17991 assert(Subtarget->hasAVX512() &&
17992 "MGATHER/MSCATTER are supported on AVX-512 arch only");
17994 MaskedGatherSDNode *N = cast<MaskedGatherSDNode>(Op.getNode());
17995 EVT VT = Op.getValueType();
17996 assert(VT.getScalarSizeInBits() >= 32 && "Unsupported gather op");
17999 SDValue Index = N->getIndex();
18000 if (!Subtarget->hasVLX() && !VT.is512BitVector() &&
18001 !Index.getValueType().is512BitVector()) {
18002 Index = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v8i64, Index);
18003 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), N->getOperand(2),
18004 N->getOperand(3), Index };
18005 DAG.UpdateNodeOperands(N, Ops);
18010 SDValue X86TargetLowering::LowerGC_TRANSITION_START(SDValue Op,
18011 SelectionDAG &DAG) const {
18012 // TODO: Eventually, the lowering of these nodes should be informed by or
18013 // deferred to the GC strategy for the function in which they appear. For
18014 // now, however, they must be lowered to something. Since they are logically
18015 // no-ops in the case of a null GC strategy (or a GC strategy which does not
18016 // require special handling for these nodes), lower them as literal NOOPs for
18018 SmallVector<SDValue, 2> Ops;
18020 Ops.push_back(Op.getOperand(0));
18021 if (Op->getGluedNode())
18022 Ops.push_back(Op->getOperand(Op->getNumOperands() - 1));
18025 SDVTList VTs = DAG.getVTList(MVT::Other, MVT::Glue);
18026 SDValue NOOP(DAG.getMachineNode(X86::NOOP, SDLoc(Op), VTs, Ops), 0);
18031 SDValue X86TargetLowering::LowerGC_TRANSITION_END(SDValue Op,
18032 SelectionDAG &DAG) const {
18033 // TODO: Eventually, the lowering of these nodes should be informed by or
18034 // deferred to the GC strategy for the function in which they appear. For
18035 // now, however, they must be lowered to something. Since they are logically
18036 // no-ops in the case of a null GC strategy (or a GC strategy which does not
18037 // require special handling for these nodes), lower them as literal NOOPs for
18039 SmallVector<SDValue, 2> Ops;
18041 Ops.push_back(Op.getOperand(0));
18042 if (Op->getGluedNode())
18043 Ops.push_back(Op->getOperand(Op->getNumOperands() - 1));
18046 SDVTList VTs = DAG.getVTList(MVT::Other, MVT::Glue);
18047 SDValue NOOP(DAG.getMachineNode(X86::NOOP, SDLoc(Op), VTs, Ops), 0);
18052 /// LowerOperation - Provide custom lowering hooks for some operations.
18054 SDValue X86TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
18055 switch (Op.getOpcode()) {
18056 default: llvm_unreachable("Should not custom lower this!");
18057 case ISD::ATOMIC_FENCE: return LowerATOMIC_FENCE(Op, Subtarget, DAG);
18058 case ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS:
18059 return LowerCMP_SWAP(Op, Subtarget, DAG);
18060 case ISD::CTPOP: return LowerCTPOP(Op, Subtarget, DAG);
18061 case ISD::ATOMIC_LOAD_SUB: return LowerLOAD_SUB(Op,DAG);
18062 case ISD::ATOMIC_STORE: return LowerATOMIC_STORE(Op,DAG);
18063 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
18064 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, Subtarget, DAG);
18065 case ISD::VECTOR_SHUFFLE: return lowerVectorShuffle(Op, Subtarget, DAG);
18066 case ISD::VSELECT: return LowerVSELECT(Op, DAG);
18067 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
18068 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG);
18069 case ISD::EXTRACT_SUBVECTOR: return LowerEXTRACT_SUBVECTOR(Op,Subtarget,DAG);
18070 case ISD::INSERT_SUBVECTOR: return LowerINSERT_SUBVECTOR(Op, Subtarget,DAG);
18071 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
18072 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
18073 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
18074 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
18075 case ISD::ExternalSymbol: return LowerExternalSymbol(Op, DAG);
18076 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
18077 case ISD::SHL_PARTS:
18078 case ISD::SRA_PARTS:
18079 case ISD::SRL_PARTS: return LowerShiftParts(Op, DAG);
18080 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG);
18081 case ISD::UINT_TO_FP: return LowerUINT_TO_FP(Op, DAG);
18082 case ISD::TRUNCATE: return LowerTRUNCATE(Op, DAG);
18083 case ISD::ZERO_EXTEND: return LowerZERO_EXTEND(Op, Subtarget, DAG);
18084 case ISD::SIGN_EXTEND: return LowerSIGN_EXTEND(Op, Subtarget, DAG);
18085 case ISD::ANY_EXTEND: return LowerANY_EXTEND(Op, Subtarget, DAG);
18086 case ISD::SIGN_EXTEND_VECTOR_INREG:
18087 return LowerSIGN_EXTEND_VECTOR_INREG(Op, Subtarget, DAG);
18088 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG);
18089 case ISD::FP_TO_UINT: return LowerFP_TO_UINT(Op, DAG);
18090 case ISD::FP_EXTEND: return LowerFP_EXTEND(Op, DAG);
18091 case ISD::LOAD: return LowerExtendedLoad(Op, Subtarget, DAG);
18093 case ISD::FNEG: return LowerFABSorFNEG(Op, DAG);
18094 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG);
18095 case ISD::FGETSIGN: return LowerFGETSIGN(Op, DAG);
18096 case ISD::SETCC: return LowerSETCC(Op, DAG);
18097 case ISD::SELECT: return LowerSELECT(Op, DAG);
18098 case ISD::BRCOND: return LowerBRCOND(Op, DAG);
18099 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
18100 case ISD::VASTART: return LowerVASTART(Op, DAG);
18101 case ISD::VAARG: return LowerVAARG(Op, DAG);
18102 case ISD::VACOPY: return LowerVACOPY(Op, Subtarget, DAG);
18103 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, Subtarget, DAG);
18104 case ISD::INTRINSIC_VOID:
18105 case ISD::INTRINSIC_W_CHAIN: return LowerINTRINSIC_W_CHAIN(Op, Subtarget, DAG);
18106 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
18107 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
18108 case ISD::FRAME_TO_ARGS_OFFSET:
18109 return LowerFRAME_TO_ARGS_OFFSET(Op, DAG);
18110 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
18111 case ISD::EH_RETURN: return LowerEH_RETURN(Op, DAG);
18112 case ISD::EH_SJLJ_SETJMP: return lowerEH_SJLJ_SETJMP(Op, DAG);
18113 case ISD::EH_SJLJ_LONGJMP: return lowerEH_SJLJ_LONGJMP(Op, DAG);
18114 case ISD::INIT_TRAMPOLINE: return LowerINIT_TRAMPOLINE(Op, DAG);
18115 case ISD::ADJUST_TRAMPOLINE: return LowerADJUST_TRAMPOLINE(Op, DAG);
18116 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
18117 case ISD::CTLZ: return LowerCTLZ(Op, DAG);
18118 case ISD::CTLZ_ZERO_UNDEF: return LowerCTLZ_ZERO_UNDEF(Op, DAG);
18119 case ISD::CTTZ: return LowerCTTZ(Op, DAG);
18120 case ISD::MUL: return LowerMUL(Op, Subtarget, DAG);
18121 case ISD::UMUL_LOHI:
18122 case ISD::SMUL_LOHI: return LowerMUL_LOHI(Op, Subtarget, DAG);
18125 case ISD::SHL: return LowerShift(Op, Subtarget, DAG);
18131 case ISD::UMULO: return LowerXALUO(Op, DAG);
18132 case ISD::READCYCLECOUNTER: return LowerREADCYCLECOUNTER(Op, Subtarget,DAG);
18133 case ISD::BITCAST: return LowerBITCAST(Op, Subtarget, DAG);
18137 case ISD::SUBE: return LowerADDC_ADDE_SUBC_SUBE(Op, DAG);
18138 case ISD::ADD: return LowerADD(Op, DAG);
18139 case ISD::SUB: return LowerSUB(Op, DAG);
18140 case ISD::FSINCOS: return LowerFSINCOS(Op, Subtarget, DAG);
18141 case ISD::MGATHER: return LowerMGATHER(Op, Subtarget, DAG);
18142 case ISD::MSCATTER: return LowerMSCATTER(Op, Subtarget, DAG);
18143 case ISD::GC_TRANSITION_START:
18144 return LowerGC_TRANSITION_START(Op, DAG);
18145 case ISD::GC_TRANSITION_END: return LowerGC_TRANSITION_END(Op, DAG);
18149 /// ReplaceNodeResults - Replace a node with an illegal result type
18150 /// with a new node built out of custom code.
18151 void X86TargetLowering::ReplaceNodeResults(SDNode *N,
18152 SmallVectorImpl<SDValue>&Results,
18153 SelectionDAG &DAG) const {
18155 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
18156 switch (N->getOpcode()) {
18158 llvm_unreachable("Do not know how to custom type legalize this operation!");
18159 // We might have generated v2f32 FMIN/FMAX operations. Widen them to v4f32.
18160 case X86ISD::FMINC:
18162 case X86ISD::FMAXC:
18163 case X86ISD::FMAX: {
18164 EVT VT = N->getValueType(0);
18165 if (VT != MVT::v2f32)
18166 llvm_unreachable("Unexpected type (!= v2f32) on FMIN/FMAX.");
18167 SDValue UNDEF = DAG.getUNDEF(VT);
18168 SDValue LHS = DAG.getNode(ISD::CONCAT_VECTORS, dl, MVT::v4f32,
18169 N->getOperand(0), UNDEF);
18170 SDValue RHS = DAG.getNode(ISD::CONCAT_VECTORS, dl, MVT::v4f32,
18171 N->getOperand(1), UNDEF);
18172 Results.push_back(DAG.getNode(N->getOpcode(), dl, MVT::v4f32, LHS, RHS));
18175 case ISD::SIGN_EXTEND_INREG:
18180 // We don't want to expand or promote these.
18187 case ISD::UDIVREM: {
18188 SDValue V = LowerWin64_i128OP(SDValue(N,0), DAG);
18189 Results.push_back(V);
18192 case ISD::FP_TO_SINT:
18193 // FP_TO_INT*_IN_MEM is not legal for f16 inputs. Do not convert
18194 // (FP_TO_SINT (load f16)) to FP_TO_INT*.
18195 if (N->getOperand(0).getValueType() == MVT::f16)
18198 case ISD::FP_TO_UINT: {
18199 bool IsSigned = N->getOpcode() == ISD::FP_TO_SINT;
18201 if (!IsSigned && !isIntegerTypeFTOL(SDValue(N, 0).getValueType()))
18204 std::pair<SDValue,SDValue> Vals =
18205 FP_TO_INTHelper(SDValue(N, 0), DAG, IsSigned, /*IsReplace=*/ true);
18206 SDValue FIST = Vals.first, StackSlot = Vals.second;
18207 if (FIST.getNode()) {
18208 EVT VT = N->getValueType(0);
18209 // Return a load from the stack slot.
18210 if (StackSlot.getNode())
18211 Results.push_back(DAG.getLoad(VT, dl, FIST, StackSlot,
18212 MachinePointerInfo(),
18213 false, false, false, 0));
18215 Results.push_back(FIST);
18219 case ISD::UINT_TO_FP: {
18220 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
18221 if (N->getOperand(0).getValueType() != MVT::v2i32 ||
18222 N->getValueType(0) != MVT::v2f32)
18224 SDValue ZExtIn = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v2i64,
18226 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL), dl,
18228 SDValue VBias = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2f64, Bias, Bias);
18229 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64, ZExtIn,
18230 DAG.getBitcast(MVT::v2i64, VBias));
18231 Or = DAG.getBitcast(MVT::v2f64, Or);
18232 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, Or, VBias);
18233 Results.push_back(DAG.getNode(X86ISD::VFPROUND, dl, MVT::v4f32, Sub));
18236 case ISD::FP_ROUND: {
18237 if (!TLI.isTypeLegal(N->getOperand(0).getValueType()))
18239 SDValue V = DAG.getNode(X86ISD::VFPROUND, dl, MVT::v4f32, N->getOperand(0));
18240 Results.push_back(V);
18243 case ISD::FP_EXTEND: {
18244 // Right now, only MVT::v2f32 has OperationAction for FP_EXTEND.
18245 // No other ValueType for FP_EXTEND should reach this point.
18246 assert(N->getValueType(0) == MVT::v2f32 &&
18247 "Do not know how to legalize this Node");
18250 case ISD::INTRINSIC_W_CHAIN: {
18251 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
18253 default : llvm_unreachable("Do not know how to custom type "
18254 "legalize this intrinsic operation!");
18255 case Intrinsic::x86_rdtsc:
18256 return getReadTimeStampCounter(N, dl, X86ISD::RDTSC_DAG, DAG, Subtarget,
18258 case Intrinsic::x86_rdtscp:
18259 return getReadTimeStampCounter(N, dl, X86ISD::RDTSCP_DAG, DAG, Subtarget,
18261 case Intrinsic::x86_rdpmc:
18262 return getReadPerformanceCounter(N, dl, DAG, Subtarget, Results);
18265 case ISD::READCYCLECOUNTER: {
18266 return getReadTimeStampCounter(N, dl, X86ISD::RDTSC_DAG, DAG, Subtarget,
18269 case ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS: {
18270 EVT T = N->getValueType(0);
18271 assert((T == MVT::i64 || T == MVT::i128) && "can only expand cmpxchg pair");
18272 bool Regs64bit = T == MVT::i128;
18273 EVT HalfT = Regs64bit ? MVT::i64 : MVT::i32;
18274 SDValue cpInL, cpInH;
18275 cpInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2),
18276 DAG.getConstant(0, dl, HalfT));
18277 cpInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2),
18278 DAG.getConstant(1, dl, HalfT));
18279 cpInL = DAG.getCopyToReg(N->getOperand(0), dl,
18280 Regs64bit ? X86::RAX : X86::EAX,
18282 cpInH = DAG.getCopyToReg(cpInL.getValue(0), dl,
18283 Regs64bit ? X86::RDX : X86::EDX,
18284 cpInH, cpInL.getValue(1));
18285 SDValue swapInL, swapInH;
18286 swapInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3),
18287 DAG.getConstant(0, dl, HalfT));
18288 swapInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3),
18289 DAG.getConstant(1, dl, HalfT));
18290 swapInL = DAG.getCopyToReg(cpInH.getValue(0), dl,
18291 Regs64bit ? X86::RBX : X86::EBX,
18292 swapInL, cpInH.getValue(1));
18293 swapInH = DAG.getCopyToReg(swapInL.getValue(0), dl,
18294 Regs64bit ? X86::RCX : X86::ECX,
18295 swapInH, swapInL.getValue(1));
18296 SDValue Ops[] = { swapInH.getValue(0),
18298 swapInH.getValue(1) };
18299 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
18300 MachineMemOperand *MMO = cast<AtomicSDNode>(N)->getMemOperand();
18301 unsigned Opcode = Regs64bit ? X86ISD::LCMPXCHG16_DAG :
18302 X86ISD::LCMPXCHG8_DAG;
18303 SDValue Result = DAG.getMemIntrinsicNode(Opcode, dl, Tys, Ops, T, MMO);
18304 SDValue cpOutL = DAG.getCopyFromReg(Result.getValue(0), dl,
18305 Regs64bit ? X86::RAX : X86::EAX,
18306 HalfT, Result.getValue(1));
18307 SDValue cpOutH = DAG.getCopyFromReg(cpOutL.getValue(1), dl,
18308 Regs64bit ? X86::RDX : X86::EDX,
18309 HalfT, cpOutL.getValue(2));
18310 SDValue OpsF[] = { cpOutL.getValue(0), cpOutH.getValue(0)};
18312 SDValue EFLAGS = DAG.getCopyFromReg(cpOutH.getValue(1), dl, X86::EFLAGS,
18313 MVT::i32, cpOutH.getValue(2));
18315 DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
18316 DAG.getConstant(X86::COND_E, dl, MVT::i8), EFLAGS);
18317 Success = DAG.getZExtOrTrunc(Success, dl, N->getValueType(1));
18319 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, T, OpsF));
18320 Results.push_back(Success);
18321 Results.push_back(EFLAGS.getValue(1));
18324 case ISD::ATOMIC_SWAP:
18325 case ISD::ATOMIC_LOAD_ADD:
18326 case ISD::ATOMIC_LOAD_SUB:
18327 case ISD::ATOMIC_LOAD_AND:
18328 case ISD::ATOMIC_LOAD_OR:
18329 case ISD::ATOMIC_LOAD_XOR:
18330 case ISD::ATOMIC_LOAD_NAND:
18331 case ISD::ATOMIC_LOAD_MIN:
18332 case ISD::ATOMIC_LOAD_MAX:
18333 case ISD::ATOMIC_LOAD_UMIN:
18334 case ISD::ATOMIC_LOAD_UMAX:
18335 case ISD::ATOMIC_LOAD: {
18336 // Delegate to generic TypeLegalization. Situations we can really handle
18337 // should have already been dealt with by AtomicExpandPass.cpp.
18340 case ISD::BITCAST: {
18341 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
18342 EVT DstVT = N->getValueType(0);
18343 EVT SrcVT = N->getOperand(0)->getValueType(0);
18345 if (SrcVT != MVT::f64 ||
18346 (DstVT != MVT::v2i32 && DstVT != MVT::v4i16 && DstVT != MVT::v8i8))
18349 unsigned NumElts = DstVT.getVectorNumElements();
18350 EVT SVT = DstVT.getVectorElementType();
18351 EVT WiderVT = EVT::getVectorVT(*DAG.getContext(), SVT, NumElts * 2);
18352 SDValue Expanded = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
18353 MVT::v2f64, N->getOperand(0));
18354 SDValue ToVecInt = DAG.getBitcast(WiderVT, Expanded);
18356 if (ExperimentalVectorWideningLegalization) {
18357 // If we are legalizing vectors by widening, we already have the desired
18358 // legal vector type, just return it.
18359 Results.push_back(ToVecInt);
18363 SmallVector<SDValue, 8> Elts;
18364 for (unsigned i = 0, e = NumElts; i != e; ++i)
18365 Elts.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, SVT,
18366 ToVecInt, DAG.getIntPtrConstant(i, dl)));
18368 Results.push_back(DAG.getNode(ISD::BUILD_VECTOR, dl, DstVT, Elts));
18373 const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
18374 switch ((X86ISD::NodeType)Opcode) {
18375 case X86ISD::FIRST_NUMBER: break;
18376 case X86ISD::BSF: return "X86ISD::BSF";
18377 case X86ISD::BSR: return "X86ISD::BSR";
18378 case X86ISD::SHLD: return "X86ISD::SHLD";
18379 case X86ISD::SHRD: return "X86ISD::SHRD";
18380 case X86ISD::FAND: return "X86ISD::FAND";
18381 case X86ISD::FANDN: return "X86ISD::FANDN";
18382 case X86ISD::FOR: return "X86ISD::FOR";
18383 case X86ISD::FXOR: return "X86ISD::FXOR";
18384 case X86ISD::FILD: return "X86ISD::FILD";
18385 case X86ISD::FILD_FLAG: return "X86ISD::FILD_FLAG";
18386 case X86ISD::FP_TO_INT16_IN_MEM: return "X86ISD::FP_TO_INT16_IN_MEM";
18387 case X86ISD::FP_TO_INT32_IN_MEM: return "X86ISD::FP_TO_INT32_IN_MEM";
18388 case X86ISD::FP_TO_INT64_IN_MEM: return "X86ISD::FP_TO_INT64_IN_MEM";
18389 case X86ISD::FLD: return "X86ISD::FLD";
18390 case X86ISD::FST: return "X86ISD::FST";
18391 case X86ISD::CALL: return "X86ISD::CALL";
18392 case X86ISD::RDTSC_DAG: return "X86ISD::RDTSC_DAG";
18393 case X86ISD::RDTSCP_DAG: return "X86ISD::RDTSCP_DAG";
18394 case X86ISD::RDPMC_DAG: return "X86ISD::RDPMC_DAG";
18395 case X86ISD::BT: return "X86ISD::BT";
18396 case X86ISD::CMP: return "X86ISD::CMP";
18397 case X86ISD::COMI: return "X86ISD::COMI";
18398 case X86ISD::UCOMI: return "X86ISD::UCOMI";
18399 case X86ISD::CMPM: return "X86ISD::CMPM";
18400 case X86ISD::CMPMU: return "X86ISD::CMPMU";
18401 case X86ISD::CMPM_RND: return "X86ISD::CMPM_RND";
18402 case X86ISD::SETCC: return "X86ISD::SETCC";
18403 case X86ISD::SETCC_CARRY: return "X86ISD::SETCC_CARRY";
18404 case X86ISD::FSETCC: return "X86ISD::FSETCC";
18405 case X86ISD::FGETSIGNx86: return "X86ISD::FGETSIGNx86";
18406 case X86ISD::CMOV: return "X86ISD::CMOV";
18407 case X86ISD::BRCOND: return "X86ISD::BRCOND";
18408 case X86ISD::RET_FLAG: return "X86ISD::RET_FLAG";
18409 case X86ISD::REP_STOS: return "X86ISD::REP_STOS";
18410 case X86ISD::REP_MOVS: return "X86ISD::REP_MOVS";
18411 case X86ISD::GlobalBaseReg: return "X86ISD::GlobalBaseReg";
18412 case X86ISD::Wrapper: return "X86ISD::Wrapper";
18413 case X86ISD::WrapperRIP: return "X86ISD::WrapperRIP";
18414 case X86ISD::MOVDQ2Q: return "X86ISD::MOVDQ2Q";
18415 case X86ISD::MMX_MOVD2W: return "X86ISD::MMX_MOVD2W";
18416 case X86ISD::MMX_MOVW2D: return "X86ISD::MMX_MOVW2D";
18417 case X86ISD::PEXTRB: return "X86ISD::PEXTRB";
18418 case X86ISD::PEXTRW: return "X86ISD::PEXTRW";
18419 case X86ISD::INSERTPS: return "X86ISD::INSERTPS";
18420 case X86ISD::PINSRB: return "X86ISD::PINSRB";
18421 case X86ISD::PINSRW: return "X86ISD::PINSRW";
18422 case X86ISD::MMX_PINSRW: return "X86ISD::MMX_PINSRW";
18423 case X86ISD::PSHUFB: return "X86ISD::PSHUFB";
18424 case X86ISD::ANDNP: return "X86ISD::ANDNP";
18425 case X86ISD::PSIGN: return "X86ISD::PSIGN";
18426 case X86ISD::BLENDI: return "X86ISD::BLENDI";
18427 case X86ISD::SHRUNKBLEND: return "X86ISD::SHRUNKBLEND";
18428 case X86ISD::ADDUS: return "X86ISD::ADDUS";
18429 case X86ISD::SUBUS: return "X86ISD::SUBUS";
18430 case X86ISD::HADD: return "X86ISD::HADD";
18431 case X86ISD::HSUB: return "X86ISD::HSUB";
18432 case X86ISD::FHADD: return "X86ISD::FHADD";
18433 case X86ISD::FHSUB: return "X86ISD::FHSUB";
18434 case X86ISD::UMAX: return "X86ISD::UMAX";
18435 case X86ISD::UMIN: return "X86ISD::UMIN";
18436 case X86ISD::SMAX: return "X86ISD::SMAX";
18437 case X86ISD::SMIN: return "X86ISD::SMIN";
18438 case X86ISD::FMAX: return "X86ISD::FMAX";
18439 case X86ISD::FMAX_RND: return "X86ISD::FMAX_RND";
18440 case X86ISD::FMIN: return "X86ISD::FMIN";
18441 case X86ISD::FMIN_RND: return "X86ISD::FMIN_RND";
18442 case X86ISD::FMAXC: return "X86ISD::FMAXC";
18443 case X86ISD::FMINC: return "X86ISD::FMINC";
18444 case X86ISD::FRSQRT: return "X86ISD::FRSQRT";
18445 case X86ISD::FRCP: return "X86ISD::FRCP";
18446 case X86ISD::TLSADDR: return "X86ISD::TLSADDR";
18447 case X86ISD::TLSBASEADDR: return "X86ISD::TLSBASEADDR";
18448 case X86ISD::TLSCALL: return "X86ISD::TLSCALL";
18449 case X86ISD::EH_SJLJ_SETJMP: return "X86ISD::EH_SJLJ_SETJMP";
18450 case X86ISD::EH_SJLJ_LONGJMP: return "X86ISD::EH_SJLJ_LONGJMP";
18451 case X86ISD::EH_RETURN: return "X86ISD::EH_RETURN";
18452 case X86ISD::TC_RETURN: return "X86ISD::TC_RETURN";
18453 case X86ISD::FNSTCW16m: return "X86ISD::FNSTCW16m";
18454 case X86ISD::FNSTSW16r: return "X86ISD::FNSTSW16r";
18455 case X86ISD::LCMPXCHG_DAG: return "X86ISD::LCMPXCHG_DAG";
18456 case X86ISD::LCMPXCHG8_DAG: return "X86ISD::LCMPXCHG8_DAG";
18457 case X86ISD::LCMPXCHG16_DAG: return "X86ISD::LCMPXCHG16_DAG";
18458 case X86ISD::VZEXT_MOVL: return "X86ISD::VZEXT_MOVL";
18459 case X86ISD::VZEXT_LOAD: return "X86ISD::VZEXT_LOAD";
18460 case X86ISD::VZEXT: return "X86ISD::VZEXT";
18461 case X86ISD::VSEXT: return "X86ISD::VSEXT";
18462 case X86ISD::VTRUNC: return "X86ISD::VTRUNC";
18463 case X86ISD::VTRUNCM: return "X86ISD::VTRUNCM";
18464 case X86ISD::VINSERT: return "X86ISD::VINSERT";
18465 case X86ISD::VFPEXT: return "X86ISD::VFPEXT";
18466 case X86ISD::VFPROUND: return "X86ISD::VFPROUND";
18467 case X86ISD::VSHLDQ: return "X86ISD::VSHLDQ";
18468 case X86ISD::VSRLDQ: return "X86ISD::VSRLDQ";
18469 case X86ISD::VSHL: return "X86ISD::VSHL";
18470 case X86ISD::VSRL: return "X86ISD::VSRL";
18471 case X86ISD::VSRA: return "X86ISD::VSRA";
18472 case X86ISD::VSHLI: return "X86ISD::VSHLI";
18473 case X86ISD::VSRLI: return "X86ISD::VSRLI";
18474 case X86ISD::VSRAI: return "X86ISD::VSRAI";
18475 case X86ISD::CMPP: return "X86ISD::CMPP";
18476 case X86ISD::PCMPEQ: return "X86ISD::PCMPEQ";
18477 case X86ISD::PCMPGT: return "X86ISD::PCMPGT";
18478 case X86ISD::PCMPEQM: return "X86ISD::PCMPEQM";
18479 case X86ISD::PCMPGTM: return "X86ISD::PCMPGTM";
18480 case X86ISD::ADD: return "X86ISD::ADD";
18481 case X86ISD::SUB: return "X86ISD::SUB";
18482 case X86ISD::ADC: return "X86ISD::ADC";
18483 case X86ISD::SBB: return "X86ISD::SBB";
18484 case X86ISD::SMUL: return "X86ISD::SMUL";
18485 case X86ISD::UMUL: return "X86ISD::UMUL";
18486 case X86ISD::SMUL8: return "X86ISD::SMUL8";
18487 case X86ISD::UMUL8: return "X86ISD::UMUL8";
18488 case X86ISD::SDIVREM8_SEXT_HREG: return "X86ISD::SDIVREM8_SEXT_HREG";
18489 case X86ISD::UDIVREM8_ZEXT_HREG: return "X86ISD::UDIVREM8_ZEXT_HREG";
18490 case X86ISD::INC: return "X86ISD::INC";
18491 case X86ISD::DEC: return "X86ISD::DEC";
18492 case X86ISD::OR: return "X86ISD::OR";
18493 case X86ISD::XOR: return "X86ISD::XOR";
18494 case X86ISD::AND: return "X86ISD::AND";
18495 case X86ISD::BEXTR: return "X86ISD::BEXTR";
18496 case X86ISD::MUL_IMM: return "X86ISD::MUL_IMM";
18497 case X86ISD::PTEST: return "X86ISD::PTEST";
18498 case X86ISD::TESTP: return "X86ISD::TESTP";
18499 case X86ISD::TESTM: return "X86ISD::TESTM";
18500 case X86ISD::TESTNM: return "X86ISD::TESTNM";
18501 case X86ISD::KORTEST: return "X86ISD::KORTEST";
18502 case X86ISD::PACKSS: return "X86ISD::PACKSS";
18503 case X86ISD::PACKUS: return "X86ISD::PACKUS";
18504 case X86ISD::PALIGNR: return "X86ISD::PALIGNR";
18505 case X86ISD::VALIGN: return "X86ISD::VALIGN";
18506 case X86ISD::PSHUFD: return "X86ISD::PSHUFD";
18507 case X86ISD::PSHUFHW: return "X86ISD::PSHUFHW";
18508 case X86ISD::PSHUFLW: return "X86ISD::PSHUFLW";
18509 case X86ISD::SHUFP: return "X86ISD::SHUFP";
18510 case X86ISD::SHUF128: return "X86ISD::SHUF128";
18511 case X86ISD::MOVLHPS: return "X86ISD::MOVLHPS";
18512 case X86ISD::MOVLHPD: return "X86ISD::MOVLHPD";
18513 case X86ISD::MOVHLPS: return "X86ISD::MOVHLPS";
18514 case X86ISD::MOVLPS: return "X86ISD::MOVLPS";
18515 case X86ISD::MOVLPD: return "X86ISD::MOVLPD";
18516 case X86ISD::MOVDDUP: return "X86ISD::MOVDDUP";
18517 case X86ISD::MOVSHDUP: return "X86ISD::MOVSHDUP";
18518 case X86ISD::MOVSLDUP: return "X86ISD::MOVSLDUP";
18519 case X86ISD::MOVSD: return "X86ISD::MOVSD";
18520 case X86ISD::MOVSS: return "X86ISD::MOVSS";
18521 case X86ISD::UNPCKL: return "X86ISD::UNPCKL";
18522 case X86ISD::UNPCKH: return "X86ISD::UNPCKH";
18523 case X86ISD::VBROADCAST: return "X86ISD::VBROADCAST";
18524 case X86ISD::SUBV_BROADCAST: return "X86ISD::SUBV_BROADCAST";
18525 case X86ISD::VEXTRACT: return "X86ISD::VEXTRACT";
18526 case X86ISD::VPERMILPV: return "X86ISD::VPERMILPV";
18527 case X86ISD::VPERMILPI: return "X86ISD::VPERMILPI";
18528 case X86ISD::VPERM2X128: return "X86ISD::VPERM2X128";
18529 case X86ISD::VPERMV: return "X86ISD::VPERMV";
18530 case X86ISD::VPERMV3: return "X86ISD::VPERMV3";
18531 case X86ISD::VPERMIV3: return "X86ISD::VPERMIV3";
18532 case X86ISD::VPERMI: return "X86ISD::VPERMI";
18533 case X86ISD::VFIXUPIMM: return "X86ISD::VFIXUPIMM";
18534 case X86ISD::VRANGE: return "X86ISD::VRANGE";
18535 case X86ISD::PMULUDQ: return "X86ISD::PMULUDQ";
18536 case X86ISD::PMULDQ: return "X86ISD::PMULDQ";
18537 case X86ISD::PSADBW: return "X86ISD::PSADBW";
18538 case X86ISD::VASTART_SAVE_XMM_REGS: return "X86ISD::VASTART_SAVE_XMM_REGS";
18539 case X86ISD::VAARG_64: return "X86ISD::VAARG_64";
18540 case X86ISD::WIN_ALLOCA: return "X86ISD::WIN_ALLOCA";
18541 case X86ISD::MEMBARRIER: return "X86ISD::MEMBARRIER";
18542 case X86ISD::MFENCE: return "X86ISD::MFENCE";
18543 case X86ISD::SFENCE: return "X86ISD::SFENCE";
18544 case X86ISD::LFENCE: return "X86ISD::LFENCE";
18545 case X86ISD::SEG_ALLOCA: return "X86ISD::SEG_ALLOCA";
18546 case X86ISD::WIN_FTOL: return "X86ISD::WIN_FTOL";
18547 case X86ISD::SAHF: return "X86ISD::SAHF";
18548 case X86ISD::RDRAND: return "X86ISD::RDRAND";
18549 case X86ISD::RDSEED: return "X86ISD::RDSEED";
18550 case X86ISD::FMADD: return "X86ISD::FMADD";
18551 case X86ISD::FMSUB: return "X86ISD::FMSUB";
18552 case X86ISD::FNMADD: return "X86ISD::FNMADD";
18553 case X86ISD::FNMSUB: return "X86ISD::FNMSUB";
18554 case X86ISD::FMADDSUB: return "X86ISD::FMADDSUB";
18555 case X86ISD::FMSUBADD: return "X86ISD::FMSUBADD";
18556 case X86ISD::FMADD_RND: return "X86ISD::FMADD_RND";
18557 case X86ISD::FNMADD_RND: return "X86ISD::FNMADD_RND";
18558 case X86ISD::FMSUB_RND: return "X86ISD::FMSUB_RND";
18559 case X86ISD::FNMSUB_RND: return "X86ISD::FNMSUB_RND";
18560 case X86ISD::FMADDSUB_RND: return "X86ISD::FMADDSUB_RND";
18561 case X86ISD::FMSUBADD_RND: return "X86ISD::FMSUBADD_RND";
18562 case X86ISD::RNDSCALE: return "X86ISD::RNDSCALE";
18563 case X86ISD::PCMPESTRI: return "X86ISD::PCMPESTRI";
18564 case X86ISD::PCMPISTRI: return "X86ISD::PCMPISTRI";
18565 case X86ISD::XTEST: return "X86ISD::XTEST";
18566 case X86ISD::COMPRESS: return "X86ISD::COMPRESS";
18567 case X86ISD::EXPAND: return "X86ISD::EXPAND";
18568 case X86ISD::SELECT: return "X86ISD::SELECT";
18569 case X86ISD::ADDSUB: return "X86ISD::ADDSUB";
18570 case X86ISD::RCP28: return "X86ISD::RCP28";
18571 case X86ISD::EXP2: return "X86ISD::EXP2";
18572 case X86ISD::RSQRT28: return "X86ISD::RSQRT28";
18573 case X86ISD::FADD_RND: return "X86ISD::FADD_RND";
18574 case X86ISD::FSUB_RND: return "X86ISD::FSUB_RND";
18575 case X86ISD::FMUL_RND: return "X86ISD::FMUL_RND";
18576 case X86ISD::FDIV_RND: return "X86ISD::FDIV_RND";
18577 case X86ISD::FSQRT_RND: return "X86ISD::FSQRT_RND";
18578 case X86ISD::FGETEXP_RND: return "X86ISD::FGETEXP_RND";
18579 case X86ISD::ADDS: return "X86ISD::ADDS";
18580 case X86ISD::SUBS: return "X86ISD::SUBS";
18585 // isLegalAddressingMode - Return true if the addressing mode represented
18586 // by AM is legal for this target, for a load/store of the specified type.
18587 bool X86TargetLowering::isLegalAddressingMode(const AddrMode &AM,
18589 unsigned AS) const {
18590 // X86 supports extremely general addressing modes.
18591 CodeModel::Model M = getTargetMachine().getCodeModel();
18592 Reloc::Model R = getTargetMachine().getRelocationModel();
18594 // X86 allows a sign-extended 32-bit immediate field as a displacement.
18595 if (!X86::isOffsetSuitableForCodeModel(AM.BaseOffs, M, AM.BaseGV != nullptr))
18600 Subtarget->ClassifyGlobalReference(AM.BaseGV, getTargetMachine());
18602 // If a reference to this global requires an extra load, we can't fold it.
18603 if (isGlobalStubReference(GVFlags))
18606 // If BaseGV requires a register for the PIC base, we cannot also have a
18607 // BaseReg specified.
18608 if (AM.HasBaseReg && isGlobalRelativeToPICBase(GVFlags))
18611 // If lower 4G is not available, then we must use rip-relative addressing.
18612 if ((M != CodeModel::Small || R != Reloc::Static) &&
18613 Subtarget->is64Bit() && (AM.BaseOffs || AM.Scale > 1))
18617 switch (AM.Scale) {
18623 // These scales always work.
18628 // These scales are formed with basereg+scalereg. Only accept if there is
18633 default: // Other stuff never works.
18640 bool X86TargetLowering::isVectorShiftByScalarCheap(Type *Ty) const {
18641 unsigned Bits = Ty->getScalarSizeInBits();
18643 // 8-bit shifts are always expensive, but versions with a scalar amount aren't
18644 // particularly cheaper than those without.
18648 // On AVX2 there are new vpsllv[dq] instructions (and other shifts), that make
18649 // variable shifts just as cheap as scalar ones.
18650 if (Subtarget->hasInt256() && (Bits == 32 || Bits == 64))
18653 // Otherwise, it's significantly cheaper to shift by a scalar amount than by a
18654 // fully general vector.
18658 bool X86TargetLowering::isTruncateFree(Type *Ty1, Type *Ty2) const {
18659 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
18661 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits();
18662 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits();
18663 return NumBits1 > NumBits2;
18666 bool X86TargetLowering::allowTruncateForTailCall(Type *Ty1, Type *Ty2) const {
18667 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
18670 if (!isTypeLegal(EVT::getEVT(Ty1)))
18673 assert(Ty1->getPrimitiveSizeInBits() <= 64 && "i128 is probably not a noop");
18675 // Assuming the caller doesn't have a zeroext or signext return parameter,
18676 // truncation all the way down to i1 is valid.
18680 bool X86TargetLowering::isLegalICmpImmediate(int64_t Imm) const {
18681 return isInt<32>(Imm);
18684 bool X86TargetLowering::isLegalAddImmediate(int64_t Imm) const {
18685 // Can also use sub to handle negated immediates.
18686 return isInt<32>(Imm);
18689 bool X86TargetLowering::isTruncateFree(EVT VT1, EVT VT2) const {
18690 if (!VT1.isInteger() || !VT2.isInteger())
18692 unsigned NumBits1 = VT1.getSizeInBits();
18693 unsigned NumBits2 = VT2.getSizeInBits();
18694 return NumBits1 > NumBits2;
18697 bool X86TargetLowering::isZExtFree(Type *Ty1, Type *Ty2) const {
18698 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
18699 return Ty1->isIntegerTy(32) && Ty2->isIntegerTy(64) && Subtarget->is64Bit();
18702 bool X86TargetLowering::isZExtFree(EVT VT1, EVT VT2) const {
18703 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
18704 return VT1 == MVT::i32 && VT2 == MVT::i64 && Subtarget->is64Bit();
18707 bool X86TargetLowering::isZExtFree(SDValue Val, EVT VT2) const {
18708 EVT VT1 = Val.getValueType();
18709 if (isZExtFree(VT1, VT2))
18712 if (Val.getOpcode() != ISD::LOAD)
18715 if (!VT1.isSimple() || !VT1.isInteger() ||
18716 !VT2.isSimple() || !VT2.isInteger())
18719 switch (VT1.getSimpleVT().SimpleTy) {
18724 // X86 has 8, 16, and 32-bit zero-extending loads.
18731 bool X86TargetLowering::isVectorLoadExtDesirable(SDValue) const { return true; }
18734 X86TargetLowering::isFMAFasterThanFMulAndFAdd(EVT VT) const {
18735 if (!(Subtarget->hasFMA() || Subtarget->hasFMA4()))
18738 VT = VT.getScalarType();
18740 if (!VT.isSimple())
18743 switch (VT.getSimpleVT().SimpleTy) {
18754 bool X86TargetLowering::isNarrowingProfitable(EVT VT1, EVT VT2) const {
18755 // i16 instructions are longer (0x66 prefix) and potentially slower.
18756 return !(VT1 == MVT::i32 && VT2 == MVT::i16);
18759 /// isShuffleMaskLegal - Targets can use this to indicate that they only
18760 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
18761 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
18762 /// are assumed to be legal.
18764 X86TargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M,
18766 if (!VT.isSimple())
18769 // Not for i1 vectors
18770 if (VT.getScalarType() == MVT::i1)
18773 // Very little shuffling can be done for 64-bit vectors right now.
18774 if (VT.getSizeInBits() == 64)
18777 // We only care that the types being shuffled are legal. The lowering can
18778 // handle any possible shuffle mask that results.
18779 return isTypeLegal(VT.getSimpleVT());
18783 X86TargetLowering::isVectorClearMaskLegal(const SmallVectorImpl<int> &Mask,
18785 // Just delegate to the generic legality, clear masks aren't special.
18786 return isShuffleMaskLegal(Mask, VT);
18789 //===----------------------------------------------------------------------===//
18790 // X86 Scheduler Hooks
18791 //===----------------------------------------------------------------------===//
18793 /// Utility function to emit xbegin specifying the start of an RTM region.
18794 static MachineBasicBlock *EmitXBegin(MachineInstr *MI, MachineBasicBlock *MBB,
18795 const TargetInstrInfo *TII) {
18796 DebugLoc DL = MI->getDebugLoc();
18798 const BasicBlock *BB = MBB->getBasicBlock();
18799 MachineFunction::iterator I = MBB;
18802 // For the v = xbegin(), we generate
18813 MachineBasicBlock *thisMBB = MBB;
18814 MachineFunction *MF = MBB->getParent();
18815 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
18816 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
18817 MF->insert(I, mainMBB);
18818 MF->insert(I, sinkMBB);
18820 // Transfer the remainder of BB and its successor edges to sinkMBB.
18821 sinkMBB->splice(sinkMBB->begin(), MBB,
18822 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
18823 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
18827 // # fallthrough to mainMBB
18828 // # abortion to sinkMBB
18829 BuildMI(thisMBB, DL, TII->get(X86::XBEGIN_4)).addMBB(sinkMBB);
18830 thisMBB->addSuccessor(mainMBB);
18831 thisMBB->addSuccessor(sinkMBB);
18835 BuildMI(mainMBB, DL, TII->get(X86::MOV32ri), X86::EAX).addImm(-1);
18836 mainMBB->addSuccessor(sinkMBB);
18839 // EAX is live into the sinkMBB
18840 sinkMBB->addLiveIn(X86::EAX);
18841 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
18842 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
18845 MI->eraseFromParent();
18849 // FIXME: When we get size specific XMM0 registers, i.e. XMM0_V16I8
18850 // or XMM0_V32I8 in AVX all of this code can be replaced with that
18851 // in the .td file.
18852 static MachineBasicBlock *EmitPCMPSTRM(MachineInstr *MI, MachineBasicBlock *BB,
18853 const TargetInstrInfo *TII) {
18855 switch (MI->getOpcode()) {
18856 default: llvm_unreachable("illegal opcode!");
18857 case X86::PCMPISTRM128REG: Opc = X86::PCMPISTRM128rr; break;
18858 case X86::VPCMPISTRM128REG: Opc = X86::VPCMPISTRM128rr; break;
18859 case X86::PCMPISTRM128MEM: Opc = X86::PCMPISTRM128rm; break;
18860 case X86::VPCMPISTRM128MEM: Opc = X86::VPCMPISTRM128rm; break;
18861 case X86::PCMPESTRM128REG: Opc = X86::PCMPESTRM128rr; break;
18862 case X86::VPCMPESTRM128REG: Opc = X86::VPCMPESTRM128rr; break;
18863 case X86::PCMPESTRM128MEM: Opc = X86::PCMPESTRM128rm; break;
18864 case X86::VPCMPESTRM128MEM: Opc = X86::VPCMPESTRM128rm; break;
18867 DebugLoc dl = MI->getDebugLoc();
18868 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(Opc));
18870 unsigned NumArgs = MI->getNumOperands();
18871 for (unsigned i = 1; i < NumArgs; ++i) {
18872 MachineOperand &Op = MI->getOperand(i);
18873 if (!(Op.isReg() && Op.isImplicit()))
18874 MIB.addOperand(Op);
18876 if (MI->hasOneMemOperand())
18877 MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
18879 BuildMI(*BB, MI, dl,
18880 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
18881 .addReg(X86::XMM0);
18883 MI->eraseFromParent();
18887 // FIXME: Custom handling because TableGen doesn't support multiple implicit
18888 // defs in an instruction pattern
18889 static MachineBasicBlock *EmitPCMPSTRI(MachineInstr *MI, MachineBasicBlock *BB,
18890 const TargetInstrInfo *TII) {
18892 switch (MI->getOpcode()) {
18893 default: llvm_unreachable("illegal opcode!");
18894 case X86::PCMPISTRIREG: Opc = X86::PCMPISTRIrr; break;
18895 case X86::VPCMPISTRIREG: Opc = X86::VPCMPISTRIrr; break;
18896 case X86::PCMPISTRIMEM: Opc = X86::PCMPISTRIrm; break;
18897 case X86::VPCMPISTRIMEM: Opc = X86::VPCMPISTRIrm; break;
18898 case X86::PCMPESTRIREG: Opc = X86::PCMPESTRIrr; break;
18899 case X86::VPCMPESTRIREG: Opc = X86::VPCMPESTRIrr; break;
18900 case X86::PCMPESTRIMEM: Opc = X86::PCMPESTRIrm; break;
18901 case X86::VPCMPESTRIMEM: Opc = X86::VPCMPESTRIrm; break;
18904 DebugLoc dl = MI->getDebugLoc();
18905 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(Opc));
18907 unsigned NumArgs = MI->getNumOperands(); // remove the results
18908 for (unsigned i = 1; i < NumArgs; ++i) {
18909 MachineOperand &Op = MI->getOperand(i);
18910 if (!(Op.isReg() && Op.isImplicit()))
18911 MIB.addOperand(Op);
18913 if (MI->hasOneMemOperand())
18914 MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
18916 BuildMI(*BB, MI, dl,
18917 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
18920 MI->eraseFromParent();
18924 static MachineBasicBlock *EmitMonitor(MachineInstr *MI, MachineBasicBlock *BB,
18925 const X86Subtarget *Subtarget) {
18926 DebugLoc dl = MI->getDebugLoc();
18927 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
18928 // Address into RAX/EAX, other two args into ECX, EDX.
18929 unsigned MemOpc = Subtarget->is64Bit() ? X86::LEA64r : X86::LEA32r;
18930 unsigned MemReg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
18931 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(MemOpc), MemReg);
18932 for (int i = 0; i < X86::AddrNumOperands; ++i)
18933 MIB.addOperand(MI->getOperand(i));
18935 unsigned ValOps = X86::AddrNumOperands;
18936 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::ECX)
18937 .addReg(MI->getOperand(ValOps).getReg());
18938 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::EDX)
18939 .addReg(MI->getOperand(ValOps+1).getReg());
18941 // The instruction doesn't actually take any operands though.
18942 BuildMI(*BB, MI, dl, TII->get(X86::MONITORrrr));
18944 MI->eraseFromParent(); // The pseudo is gone now.
18948 MachineBasicBlock *
18949 X86TargetLowering::EmitVAARG64WithCustomInserter(MachineInstr *MI,
18950 MachineBasicBlock *MBB) const {
18951 // Emit va_arg instruction on X86-64.
18953 // Operands to this pseudo-instruction:
18954 // 0 ) Output : destination address (reg)
18955 // 1-5) Input : va_list address (addr, i64mem)
18956 // 6 ) ArgSize : Size (in bytes) of vararg type
18957 // 7 ) ArgMode : 0=overflow only, 1=use gp_offset, 2=use fp_offset
18958 // 8 ) Align : Alignment of type
18959 // 9 ) EFLAGS (implicit-def)
18961 assert(MI->getNumOperands() == 10 && "VAARG_64 should have 10 operands!");
18962 static_assert(X86::AddrNumOperands == 5,
18963 "VAARG_64 assumes 5 address operands");
18965 unsigned DestReg = MI->getOperand(0).getReg();
18966 MachineOperand &Base = MI->getOperand(1);
18967 MachineOperand &Scale = MI->getOperand(2);
18968 MachineOperand &Index = MI->getOperand(3);
18969 MachineOperand &Disp = MI->getOperand(4);
18970 MachineOperand &Segment = MI->getOperand(5);
18971 unsigned ArgSize = MI->getOperand(6).getImm();
18972 unsigned ArgMode = MI->getOperand(7).getImm();
18973 unsigned Align = MI->getOperand(8).getImm();
18975 // Memory Reference
18976 assert(MI->hasOneMemOperand() && "Expected VAARG_64 to have one memoperand");
18977 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
18978 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
18980 // Machine Information
18981 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
18982 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
18983 const TargetRegisterClass *AddrRegClass = getRegClassFor(MVT::i64);
18984 const TargetRegisterClass *OffsetRegClass = getRegClassFor(MVT::i32);
18985 DebugLoc DL = MI->getDebugLoc();
18987 // struct va_list {
18990 // i64 overflow_area (address)
18991 // i64 reg_save_area (address)
18993 // sizeof(va_list) = 24
18994 // alignment(va_list) = 8
18996 unsigned TotalNumIntRegs = 6;
18997 unsigned TotalNumXMMRegs = 8;
18998 bool UseGPOffset = (ArgMode == 1);
18999 bool UseFPOffset = (ArgMode == 2);
19000 unsigned MaxOffset = TotalNumIntRegs * 8 +
19001 (UseFPOffset ? TotalNumXMMRegs * 16 : 0);
19003 /* Align ArgSize to a multiple of 8 */
19004 unsigned ArgSizeA8 = (ArgSize + 7) & ~7;
19005 bool NeedsAlign = (Align > 8);
19007 MachineBasicBlock *thisMBB = MBB;
19008 MachineBasicBlock *overflowMBB;
19009 MachineBasicBlock *offsetMBB;
19010 MachineBasicBlock *endMBB;
19012 unsigned OffsetDestReg = 0; // Argument address computed by offsetMBB
19013 unsigned OverflowDestReg = 0; // Argument address computed by overflowMBB
19014 unsigned OffsetReg = 0;
19016 if (!UseGPOffset && !UseFPOffset) {
19017 // If we only pull from the overflow region, we don't create a branch.
19018 // We don't need to alter control flow.
19019 OffsetDestReg = 0; // unused
19020 OverflowDestReg = DestReg;
19022 offsetMBB = nullptr;
19023 overflowMBB = thisMBB;
19026 // First emit code to check if gp_offset (or fp_offset) is below the bound.
19027 // If so, pull the argument from reg_save_area. (branch to offsetMBB)
19028 // If not, pull from overflow_area. (branch to overflowMBB)
19033 // offsetMBB overflowMBB
19038 // Registers for the PHI in endMBB
19039 OffsetDestReg = MRI.createVirtualRegister(AddrRegClass);
19040 OverflowDestReg = MRI.createVirtualRegister(AddrRegClass);
19042 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
19043 MachineFunction *MF = MBB->getParent();
19044 overflowMBB = MF->CreateMachineBasicBlock(LLVM_BB);
19045 offsetMBB = MF->CreateMachineBasicBlock(LLVM_BB);
19046 endMBB = MF->CreateMachineBasicBlock(LLVM_BB);
19048 MachineFunction::iterator MBBIter = MBB;
19051 // Insert the new basic blocks
19052 MF->insert(MBBIter, offsetMBB);
19053 MF->insert(MBBIter, overflowMBB);
19054 MF->insert(MBBIter, endMBB);
19056 // Transfer the remainder of MBB and its successor edges to endMBB.
19057 endMBB->splice(endMBB->begin(), thisMBB,
19058 std::next(MachineBasicBlock::iterator(MI)), thisMBB->end());
19059 endMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
19061 // Make offsetMBB and overflowMBB successors of thisMBB
19062 thisMBB->addSuccessor(offsetMBB);
19063 thisMBB->addSuccessor(overflowMBB);
19065 // endMBB is a successor of both offsetMBB and overflowMBB
19066 offsetMBB->addSuccessor(endMBB);
19067 overflowMBB->addSuccessor(endMBB);
19069 // Load the offset value into a register
19070 OffsetReg = MRI.createVirtualRegister(OffsetRegClass);
19071 BuildMI(thisMBB, DL, TII->get(X86::MOV32rm), OffsetReg)
19075 .addDisp(Disp, UseFPOffset ? 4 : 0)
19076 .addOperand(Segment)
19077 .setMemRefs(MMOBegin, MMOEnd);
19079 // Check if there is enough room left to pull this argument.
19080 BuildMI(thisMBB, DL, TII->get(X86::CMP32ri))
19082 .addImm(MaxOffset + 8 - ArgSizeA8);
19084 // Branch to "overflowMBB" if offset >= max
19085 // Fall through to "offsetMBB" otherwise
19086 BuildMI(thisMBB, DL, TII->get(X86::GetCondBranchFromCond(X86::COND_AE)))
19087 .addMBB(overflowMBB);
19090 // In offsetMBB, emit code to use the reg_save_area.
19092 assert(OffsetReg != 0);
19094 // Read the reg_save_area address.
19095 unsigned RegSaveReg = MRI.createVirtualRegister(AddrRegClass);
19096 BuildMI(offsetMBB, DL, TII->get(X86::MOV64rm), RegSaveReg)
19101 .addOperand(Segment)
19102 .setMemRefs(MMOBegin, MMOEnd);
19104 // Zero-extend the offset
19105 unsigned OffsetReg64 = MRI.createVirtualRegister(AddrRegClass);
19106 BuildMI(offsetMBB, DL, TII->get(X86::SUBREG_TO_REG), OffsetReg64)
19109 .addImm(X86::sub_32bit);
19111 // Add the offset to the reg_save_area to get the final address.
19112 BuildMI(offsetMBB, DL, TII->get(X86::ADD64rr), OffsetDestReg)
19113 .addReg(OffsetReg64)
19114 .addReg(RegSaveReg);
19116 // Compute the offset for the next argument
19117 unsigned NextOffsetReg = MRI.createVirtualRegister(OffsetRegClass);
19118 BuildMI(offsetMBB, DL, TII->get(X86::ADD32ri), NextOffsetReg)
19120 .addImm(UseFPOffset ? 16 : 8);
19122 // Store it back into the va_list.
19123 BuildMI(offsetMBB, DL, TII->get(X86::MOV32mr))
19127 .addDisp(Disp, UseFPOffset ? 4 : 0)
19128 .addOperand(Segment)
19129 .addReg(NextOffsetReg)
19130 .setMemRefs(MMOBegin, MMOEnd);
19133 BuildMI(offsetMBB, DL, TII->get(X86::JMP_1))
19138 // Emit code to use overflow area
19141 // Load the overflow_area address into a register.
19142 unsigned OverflowAddrReg = MRI.createVirtualRegister(AddrRegClass);
19143 BuildMI(overflowMBB, DL, TII->get(X86::MOV64rm), OverflowAddrReg)
19148 .addOperand(Segment)
19149 .setMemRefs(MMOBegin, MMOEnd);
19151 // If we need to align it, do so. Otherwise, just copy the address
19152 // to OverflowDestReg.
19154 // Align the overflow address
19155 assert((Align & (Align-1)) == 0 && "Alignment must be a power of 2");
19156 unsigned TmpReg = MRI.createVirtualRegister(AddrRegClass);
19158 // aligned_addr = (addr + (align-1)) & ~(align-1)
19159 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), TmpReg)
19160 .addReg(OverflowAddrReg)
19163 BuildMI(overflowMBB, DL, TII->get(X86::AND64ri32), OverflowDestReg)
19165 .addImm(~(uint64_t)(Align-1));
19167 BuildMI(overflowMBB, DL, TII->get(TargetOpcode::COPY), OverflowDestReg)
19168 .addReg(OverflowAddrReg);
19171 // Compute the next overflow address after this argument.
19172 // (the overflow address should be kept 8-byte aligned)
19173 unsigned NextAddrReg = MRI.createVirtualRegister(AddrRegClass);
19174 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), NextAddrReg)
19175 .addReg(OverflowDestReg)
19176 .addImm(ArgSizeA8);
19178 // Store the new overflow address.
19179 BuildMI(overflowMBB, DL, TII->get(X86::MOV64mr))
19184 .addOperand(Segment)
19185 .addReg(NextAddrReg)
19186 .setMemRefs(MMOBegin, MMOEnd);
19188 // If we branched, emit the PHI to the front of endMBB.
19190 BuildMI(*endMBB, endMBB->begin(), DL,
19191 TII->get(X86::PHI), DestReg)
19192 .addReg(OffsetDestReg).addMBB(offsetMBB)
19193 .addReg(OverflowDestReg).addMBB(overflowMBB);
19196 // Erase the pseudo instruction
19197 MI->eraseFromParent();
19202 MachineBasicBlock *
19203 X86TargetLowering::EmitVAStartSaveXMMRegsWithCustomInserter(
19205 MachineBasicBlock *MBB) const {
19206 // Emit code to save XMM registers to the stack. The ABI says that the
19207 // number of registers to save is given in %al, so it's theoretically
19208 // possible to do an indirect jump trick to avoid saving all of them,
19209 // however this code takes a simpler approach and just executes all
19210 // of the stores if %al is non-zero. It's less code, and it's probably
19211 // easier on the hardware branch predictor, and stores aren't all that
19212 // expensive anyway.
19214 // Create the new basic blocks. One block contains all the XMM stores,
19215 // and one block is the final destination regardless of whether any
19216 // stores were performed.
19217 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
19218 MachineFunction *F = MBB->getParent();
19219 MachineFunction::iterator MBBIter = MBB;
19221 MachineBasicBlock *XMMSaveMBB = F->CreateMachineBasicBlock(LLVM_BB);
19222 MachineBasicBlock *EndMBB = F->CreateMachineBasicBlock(LLVM_BB);
19223 F->insert(MBBIter, XMMSaveMBB);
19224 F->insert(MBBIter, EndMBB);
19226 // Transfer the remainder of MBB and its successor edges to EndMBB.
19227 EndMBB->splice(EndMBB->begin(), MBB,
19228 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
19229 EndMBB->transferSuccessorsAndUpdatePHIs(MBB);
19231 // The original block will now fall through to the XMM save block.
19232 MBB->addSuccessor(XMMSaveMBB);
19233 // The XMMSaveMBB will fall through to the end block.
19234 XMMSaveMBB->addSuccessor(EndMBB);
19236 // Now add the instructions.
19237 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
19238 DebugLoc DL = MI->getDebugLoc();
19240 unsigned CountReg = MI->getOperand(0).getReg();
19241 int64_t RegSaveFrameIndex = MI->getOperand(1).getImm();
19242 int64_t VarArgsFPOffset = MI->getOperand(2).getImm();
19244 if (!Subtarget->isTargetWin64()) {
19245 // If %al is 0, branch around the XMM save block.
19246 BuildMI(MBB, DL, TII->get(X86::TEST8rr)).addReg(CountReg).addReg(CountReg);
19247 BuildMI(MBB, DL, TII->get(X86::JE_1)).addMBB(EndMBB);
19248 MBB->addSuccessor(EndMBB);
19251 // Make sure the last operand is EFLAGS, which gets clobbered by the branch
19252 // that was just emitted, but clearly shouldn't be "saved".
19253 assert((MI->getNumOperands() <= 3 ||
19254 !MI->getOperand(MI->getNumOperands() - 1).isReg() ||
19255 MI->getOperand(MI->getNumOperands() - 1).getReg() == X86::EFLAGS)
19256 && "Expected last argument to be EFLAGS");
19257 unsigned MOVOpc = Subtarget->hasFp256() ? X86::VMOVAPSmr : X86::MOVAPSmr;
19258 // In the XMM save block, save all the XMM argument registers.
19259 for (int i = 3, e = MI->getNumOperands() - 1; i != e; ++i) {
19260 int64_t Offset = (i - 3) * 16 + VarArgsFPOffset;
19261 MachineMemOperand *MMO =
19262 F->getMachineMemOperand(
19263 MachinePointerInfo::getFixedStack(RegSaveFrameIndex, Offset),
19264 MachineMemOperand::MOStore,
19265 /*Size=*/16, /*Align=*/16);
19266 BuildMI(XMMSaveMBB, DL, TII->get(MOVOpc))
19267 .addFrameIndex(RegSaveFrameIndex)
19268 .addImm(/*Scale=*/1)
19269 .addReg(/*IndexReg=*/0)
19270 .addImm(/*Disp=*/Offset)
19271 .addReg(/*Segment=*/0)
19272 .addReg(MI->getOperand(i).getReg())
19273 .addMemOperand(MMO);
19276 MI->eraseFromParent(); // The pseudo instruction is gone now.
19281 // The EFLAGS operand of SelectItr might be missing a kill marker
19282 // because there were multiple uses of EFLAGS, and ISel didn't know
19283 // which to mark. Figure out whether SelectItr should have had a
19284 // kill marker, and set it if it should. Returns the correct kill
19286 static bool checkAndUpdateEFLAGSKill(MachineBasicBlock::iterator SelectItr,
19287 MachineBasicBlock* BB,
19288 const TargetRegisterInfo* TRI) {
19289 // Scan forward through BB for a use/def of EFLAGS.
19290 MachineBasicBlock::iterator miI(std::next(SelectItr));
19291 for (MachineBasicBlock::iterator miE = BB->end(); miI != miE; ++miI) {
19292 const MachineInstr& mi = *miI;
19293 if (mi.readsRegister(X86::EFLAGS))
19295 if (mi.definesRegister(X86::EFLAGS))
19296 break; // Should have kill-flag - update below.
19299 // If we hit the end of the block, check whether EFLAGS is live into a
19301 if (miI == BB->end()) {
19302 for (MachineBasicBlock::succ_iterator sItr = BB->succ_begin(),
19303 sEnd = BB->succ_end();
19304 sItr != sEnd; ++sItr) {
19305 MachineBasicBlock* succ = *sItr;
19306 if (succ->isLiveIn(X86::EFLAGS))
19311 // We found a def, or hit the end of the basic block and EFLAGS wasn't live
19312 // out. SelectMI should have a kill flag on EFLAGS.
19313 SelectItr->addRegisterKilled(X86::EFLAGS, TRI);
19317 MachineBasicBlock *
19318 X86TargetLowering::EmitLoweredSelect(MachineInstr *MI,
19319 MachineBasicBlock *BB) const {
19320 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
19321 DebugLoc DL = MI->getDebugLoc();
19323 // To "insert" a SELECT_CC instruction, we actually have to insert the
19324 // diamond control-flow pattern. The incoming instruction knows the
19325 // destination vreg to set, the condition code register to branch on, the
19326 // true/false values to select between, and a branch opcode to use.
19327 const BasicBlock *LLVM_BB = BB->getBasicBlock();
19328 MachineFunction::iterator It = BB;
19334 // cmpTY ccX, r1, r2
19336 // fallthrough --> copy0MBB
19337 MachineBasicBlock *thisMBB = BB;
19338 MachineFunction *F = BB->getParent();
19340 // We also lower double CMOVs:
19341 // (CMOV (CMOV F, T, cc1), T, cc2)
19342 // to two successives branches. For that, we look for another CMOV as the
19343 // following instruction.
19345 // Without this, we would add a PHI between the two jumps, which ends up
19346 // creating a few copies all around. For instance, for
19348 // (sitofp (zext (fcmp une)))
19350 // we would generate:
19352 // ucomiss %xmm1, %xmm0
19353 // movss <1.0f>, %xmm0
19354 // movaps %xmm0, %xmm1
19356 // xorps %xmm1, %xmm1
19359 // movaps %xmm1, %xmm0
19363 // because this custom-inserter would have generated:
19375 // A: X = ...; Y = ...
19377 // C: Z = PHI [X, A], [Y, B]
19379 // E: PHI [X, C], [Z, D]
19381 // If we lower both CMOVs in a single step, we can instead generate:
19393 // A: X = ...; Y = ...
19395 // E: PHI [X, A], [X, C], [Y, D]
19397 // Which, in our sitofp/fcmp example, gives us something like:
19399 // ucomiss %xmm1, %xmm0
19400 // movss <1.0f>, %xmm0
19403 // xorps %xmm0, %xmm0
19407 MachineInstr *NextCMOV = nullptr;
19408 MachineBasicBlock::iterator NextMIIt =
19409 std::next(MachineBasicBlock::iterator(MI));
19410 if (NextMIIt != BB->end() && NextMIIt->getOpcode() == MI->getOpcode() &&
19411 NextMIIt->getOperand(2).getReg() == MI->getOperand(2).getReg() &&
19412 NextMIIt->getOperand(1).getReg() == MI->getOperand(0).getReg())
19413 NextCMOV = &*NextMIIt;
19415 MachineBasicBlock *jcc1MBB = nullptr;
19417 // If we have a double CMOV, we lower it to two successive branches to
19418 // the same block. EFLAGS is used by both, so mark it as live in the second.
19420 jcc1MBB = F->CreateMachineBasicBlock(LLVM_BB);
19421 F->insert(It, jcc1MBB);
19422 jcc1MBB->addLiveIn(X86::EFLAGS);
19425 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
19426 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
19427 F->insert(It, copy0MBB);
19428 F->insert(It, sinkMBB);
19430 // If the EFLAGS register isn't dead in the terminator, then claim that it's
19431 // live into the sink and copy blocks.
19432 const TargetRegisterInfo *TRI = Subtarget->getRegisterInfo();
19434 MachineInstr *LastEFLAGSUser = NextCMOV ? NextCMOV : MI;
19435 if (!LastEFLAGSUser->killsRegister(X86::EFLAGS) &&
19436 !checkAndUpdateEFLAGSKill(LastEFLAGSUser, BB, TRI)) {
19437 copy0MBB->addLiveIn(X86::EFLAGS);
19438 sinkMBB->addLiveIn(X86::EFLAGS);
19441 // Transfer the remainder of BB and its successor edges to sinkMBB.
19442 sinkMBB->splice(sinkMBB->begin(), BB,
19443 std::next(MachineBasicBlock::iterator(MI)), BB->end());
19444 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
19446 // Add the true and fallthrough blocks as its successors.
19448 // The fallthrough block may be jcc1MBB, if we have a double CMOV.
19449 BB->addSuccessor(jcc1MBB);
19451 // In that case, jcc1MBB will itself fallthrough the copy0MBB, and
19452 // jump to the sinkMBB.
19453 jcc1MBB->addSuccessor(copy0MBB);
19454 jcc1MBB->addSuccessor(sinkMBB);
19456 BB->addSuccessor(copy0MBB);
19459 // The true block target of the first (or only) branch is always sinkMBB.
19460 BB->addSuccessor(sinkMBB);
19462 // Create the conditional branch instruction.
19464 X86::GetCondBranchFromCond((X86::CondCode)MI->getOperand(3).getImm());
19465 BuildMI(BB, DL, TII->get(Opc)).addMBB(sinkMBB);
19468 unsigned Opc2 = X86::GetCondBranchFromCond(
19469 (X86::CondCode)NextCMOV->getOperand(3).getImm());
19470 BuildMI(jcc1MBB, DL, TII->get(Opc2)).addMBB(sinkMBB);
19474 // %FalseValue = ...
19475 // # fallthrough to sinkMBB
19476 copy0MBB->addSuccessor(sinkMBB);
19479 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
19481 MachineInstrBuilder MIB =
19482 BuildMI(*sinkMBB, sinkMBB->begin(), DL, TII->get(X86::PHI),
19483 MI->getOperand(0).getReg())
19484 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB)
19485 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
19487 // If we have a double CMOV, the second Jcc provides the same incoming
19488 // value as the first Jcc (the True operand of the SELECT_CC/CMOV nodes).
19490 MIB.addReg(MI->getOperand(2).getReg()).addMBB(jcc1MBB);
19491 // Copy the PHI result to the register defined by the second CMOV.
19492 BuildMI(*sinkMBB, std::next(MachineBasicBlock::iterator(MIB.getInstr())),
19493 DL, TII->get(TargetOpcode::COPY), NextCMOV->getOperand(0).getReg())
19494 .addReg(MI->getOperand(0).getReg());
19495 NextCMOV->eraseFromParent();
19498 MI->eraseFromParent(); // The pseudo instruction is gone now.
19502 MachineBasicBlock *
19503 X86TargetLowering::EmitLoweredSegAlloca(MachineInstr *MI,
19504 MachineBasicBlock *BB) const {
19505 MachineFunction *MF = BB->getParent();
19506 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
19507 DebugLoc DL = MI->getDebugLoc();
19508 const BasicBlock *LLVM_BB = BB->getBasicBlock();
19510 assert(MF->shouldSplitStack());
19512 const bool Is64Bit = Subtarget->is64Bit();
19513 const bool IsLP64 = Subtarget->isTarget64BitLP64();
19515 const unsigned TlsReg = Is64Bit ? X86::FS : X86::GS;
19516 const unsigned TlsOffset = IsLP64 ? 0x70 : Is64Bit ? 0x40 : 0x30;
19519 // ... [Till the alloca]
19520 // If stacklet is not large enough, jump to mallocMBB
19523 // Allocate by subtracting from RSP
19524 // Jump to continueMBB
19527 // Allocate by call to runtime
19531 // [rest of original BB]
19534 MachineBasicBlock *mallocMBB = MF->CreateMachineBasicBlock(LLVM_BB);
19535 MachineBasicBlock *bumpMBB = MF->CreateMachineBasicBlock(LLVM_BB);
19536 MachineBasicBlock *continueMBB = MF->CreateMachineBasicBlock(LLVM_BB);
19538 MachineRegisterInfo &MRI = MF->getRegInfo();
19539 const TargetRegisterClass *AddrRegClass =
19540 getRegClassFor(getPointerTy());
19542 unsigned mallocPtrVReg = MRI.createVirtualRegister(AddrRegClass),
19543 bumpSPPtrVReg = MRI.createVirtualRegister(AddrRegClass),
19544 tmpSPVReg = MRI.createVirtualRegister(AddrRegClass),
19545 SPLimitVReg = MRI.createVirtualRegister(AddrRegClass),
19546 sizeVReg = MI->getOperand(1).getReg(),
19547 physSPReg = IsLP64 || Subtarget->isTargetNaCl64() ? X86::RSP : X86::ESP;
19549 MachineFunction::iterator MBBIter = BB;
19552 MF->insert(MBBIter, bumpMBB);
19553 MF->insert(MBBIter, mallocMBB);
19554 MF->insert(MBBIter, continueMBB);
19556 continueMBB->splice(continueMBB->begin(), BB,
19557 std::next(MachineBasicBlock::iterator(MI)), BB->end());
19558 continueMBB->transferSuccessorsAndUpdatePHIs(BB);
19560 // Add code to the main basic block to check if the stack limit has been hit,
19561 // and if so, jump to mallocMBB otherwise to bumpMBB.
19562 BuildMI(BB, DL, TII->get(TargetOpcode::COPY), tmpSPVReg).addReg(physSPReg);
19563 BuildMI(BB, DL, TII->get(IsLP64 ? X86::SUB64rr:X86::SUB32rr), SPLimitVReg)
19564 .addReg(tmpSPVReg).addReg(sizeVReg);
19565 BuildMI(BB, DL, TII->get(IsLP64 ? X86::CMP64mr:X86::CMP32mr))
19566 .addReg(0).addImm(1).addReg(0).addImm(TlsOffset).addReg(TlsReg)
19567 .addReg(SPLimitVReg);
19568 BuildMI(BB, DL, TII->get(X86::JG_1)).addMBB(mallocMBB);
19570 // bumpMBB simply decreases the stack pointer, since we know the current
19571 // stacklet has enough space.
19572 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), physSPReg)
19573 .addReg(SPLimitVReg);
19574 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), bumpSPPtrVReg)
19575 .addReg(SPLimitVReg);
19576 BuildMI(bumpMBB, DL, TII->get(X86::JMP_1)).addMBB(continueMBB);
19578 // Calls into a routine in libgcc to allocate more space from the heap.
19579 const uint32_t *RegMask =
19580 Subtarget->getRegisterInfo()->getCallPreservedMask(*MF, CallingConv::C);
19582 BuildMI(mallocMBB, DL, TII->get(X86::MOV64rr), X86::RDI)
19584 BuildMI(mallocMBB, DL, TII->get(X86::CALL64pcrel32))
19585 .addExternalSymbol("__morestack_allocate_stack_space")
19586 .addRegMask(RegMask)
19587 .addReg(X86::RDI, RegState::Implicit)
19588 .addReg(X86::RAX, RegState::ImplicitDefine);
19589 } else if (Is64Bit) {
19590 BuildMI(mallocMBB, DL, TII->get(X86::MOV32rr), X86::EDI)
19592 BuildMI(mallocMBB, DL, TII->get(X86::CALL64pcrel32))
19593 .addExternalSymbol("__morestack_allocate_stack_space")
19594 .addRegMask(RegMask)
19595 .addReg(X86::EDI, RegState::Implicit)
19596 .addReg(X86::EAX, RegState::ImplicitDefine);
19598 BuildMI(mallocMBB, DL, TII->get(X86::SUB32ri), physSPReg).addReg(physSPReg)
19600 BuildMI(mallocMBB, DL, TII->get(X86::PUSH32r)).addReg(sizeVReg);
19601 BuildMI(mallocMBB, DL, TII->get(X86::CALLpcrel32))
19602 .addExternalSymbol("__morestack_allocate_stack_space")
19603 .addRegMask(RegMask)
19604 .addReg(X86::EAX, RegState::ImplicitDefine);
19608 BuildMI(mallocMBB, DL, TII->get(X86::ADD32ri), physSPReg).addReg(physSPReg)
19611 BuildMI(mallocMBB, DL, TII->get(TargetOpcode::COPY), mallocPtrVReg)
19612 .addReg(IsLP64 ? X86::RAX : X86::EAX);
19613 BuildMI(mallocMBB, DL, TII->get(X86::JMP_1)).addMBB(continueMBB);
19615 // Set up the CFG correctly.
19616 BB->addSuccessor(bumpMBB);
19617 BB->addSuccessor(mallocMBB);
19618 mallocMBB->addSuccessor(continueMBB);
19619 bumpMBB->addSuccessor(continueMBB);
19621 // Take care of the PHI nodes.
19622 BuildMI(*continueMBB, continueMBB->begin(), DL, TII->get(X86::PHI),
19623 MI->getOperand(0).getReg())
19624 .addReg(mallocPtrVReg).addMBB(mallocMBB)
19625 .addReg(bumpSPPtrVReg).addMBB(bumpMBB);
19627 // Delete the original pseudo instruction.
19628 MI->eraseFromParent();
19631 return continueMBB;
19634 MachineBasicBlock *
19635 X86TargetLowering::EmitLoweredWinAlloca(MachineInstr *MI,
19636 MachineBasicBlock *BB) const {
19637 DebugLoc DL = MI->getDebugLoc();
19639 assert(!Subtarget->isTargetMachO());
19641 X86FrameLowering::emitStackProbeCall(*BB->getParent(), *BB, MI, DL);
19643 MI->eraseFromParent(); // The pseudo instruction is gone now.
19647 MachineBasicBlock *
19648 X86TargetLowering::EmitLoweredTLSCall(MachineInstr *MI,
19649 MachineBasicBlock *BB) const {
19650 // This is pretty easy. We're taking the value that we received from
19651 // our load from the relocation, sticking it in either RDI (x86-64)
19652 // or EAX and doing an indirect call. The return value will then
19653 // be in the normal return register.
19654 MachineFunction *F = BB->getParent();
19655 const X86InstrInfo *TII = Subtarget->getInstrInfo();
19656 DebugLoc DL = MI->getDebugLoc();
19658 assert(Subtarget->isTargetDarwin() && "Darwin only instr emitted?");
19659 assert(MI->getOperand(3).isGlobal() && "This should be a global");
19661 // Get a register mask for the lowered call.
19662 // FIXME: The 32-bit calls have non-standard calling conventions. Use a
19663 // proper register mask.
19664 const uint32_t *RegMask =
19665 Subtarget->getRegisterInfo()->getCallPreservedMask(*F, CallingConv::C);
19666 if (Subtarget->is64Bit()) {
19667 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
19668 TII->get(X86::MOV64rm), X86::RDI)
19670 .addImm(0).addReg(0)
19671 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
19672 MI->getOperand(3).getTargetFlags())
19674 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL64m));
19675 addDirectMem(MIB, X86::RDI);
19676 MIB.addReg(X86::RAX, RegState::ImplicitDefine).addRegMask(RegMask);
19677 } else if (F->getTarget().getRelocationModel() != Reloc::PIC_) {
19678 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
19679 TII->get(X86::MOV32rm), X86::EAX)
19681 .addImm(0).addReg(0)
19682 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
19683 MI->getOperand(3).getTargetFlags())
19685 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
19686 addDirectMem(MIB, X86::EAX);
19687 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask);
19689 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
19690 TII->get(X86::MOV32rm), X86::EAX)
19691 .addReg(TII->getGlobalBaseReg(F))
19692 .addImm(0).addReg(0)
19693 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
19694 MI->getOperand(3).getTargetFlags())
19696 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
19697 addDirectMem(MIB, X86::EAX);
19698 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask);
19701 MI->eraseFromParent(); // The pseudo instruction is gone now.
19705 MachineBasicBlock *
19706 X86TargetLowering::emitEHSjLjSetJmp(MachineInstr *MI,
19707 MachineBasicBlock *MBB) const {
19708 DebugLoc DL = MI->getDebugLoc();
19709 MachineFunction *MF = MBB->getParent();
19710 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
19711 MachineRegisterInfo &MRI = MF->getRegInfo();
19713 const BasicBlock *BB = MBB->getBasicBlock();
19714 MachineFunction::iterator I = MBB;
19717 // Memory Reference
19718 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
19719 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
19722 unsigned MemOpndSlot = 0;
19724 unsigned CurOp = 0;
19726 DstReg = MI->getOperand(CurOp++).getReg();
19727 const TargetRegisterClass *RC = MRI.getRegClass(DstReg);
19728 assert(RC->hasType(MVT::i32) && "Invalid destination!");
19729 unsigned mainDstReg = MRI.createVirtualRegister(RC);
19730 unsigned restoreDstReg = MRI.createVirtualRegister(RC);
19732 MemOpndSlot = CurOp;
19734 MVT PVT = getPointerTy();
19735 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
19736 "Invalid Pointer Size!");
19738 // For v = setjmp(buf), we generate
19741 // buf[LabelOffset] = restoreMBB
19742 // SjLjSetup restoreMBB
19748 // v = phi(main, restore)
19751 // if base pointer being used, load it from frame
19754 MachineBasicBlock *thisMBB = MBB;
19755 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
19756 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
19757 MachineBasicBlock *restoreMBB = MF->CreateMachineBasicBlock(BB);
19758 MF->insert(I, mainMBB);
19759 MF->insert(I, sinkMBB);
19760 MF->push_back(restoreMBB);
19762 MachineInstrBuilder MIB;
19764 // Transfer the remainder of BB and its successor edges to sinkMBB.
19765 sinkMBB->splice(sinkMBB->begin(), MBB,
19766 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
19767 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
19770 unsigned PtrStoreOpc = 0;
19771 unsigned LabelReg = 0;
19772 const int64_t LabelOffset = 1 * PVT.getStoreSize();
19773 Reloc::Model RM = MF->getTarget().getRelocationModel();
19774 bool UseImmLabel = (MF->getTarget().getCodeModel() == CodeModel::Small) &&
19775 (RM == Reloc::Static || RM == Reloc::DynamicNoPIC);
19777 // Prepare IP either in reg or imm.
19778 if (!UseImmLabel) {
19779 PtrStoreOpc = (PVT == MVT::i64) ? X86::MOV64mr : X86::MOV32mr;
19780 const TargetRegisterClass *PtrRC = getRegClassFor(PVT);
19781 LabelReg = MRI.createVirtualRegister(PtrRC);
19782 if (Subtarget->is64Bit()) {
19783 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::LEA64r), LabelReg)
19787 .addMBB(restoreMBB)
19790 const X86InstrInfo *XII = static_cast<const X86InstrInfo*>(TII);
19791 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::LEA32r), LabelReg)
19792 .addReg(XII->getGlobalBaseReg(MF))
19795 .addMBB(restoreMBB, Subtarget->ClassifyBlockAddressReference())
19799 PtrStoreOpc = (PVT == MVT::i64) ? X86::MOV64mi32 : X86::MOV32mi;
19801 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PtrStoreOpc));
19802 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
19803 if (i == X86::AddrDisp)
19804 MIB.addDisp(MI->getOperand(MemOpndSlot + i), LabelOffset);
19806 MIB.addOperand(MI->getOperand(MemOpndSlot + i));
19809 MIB.addReg(LabelReg);
19811 MIB.addMBB(restoreMBB);
19812 MIB.setMemRefs(MMOBegin, MMOEnd);
19814 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::EH_SjLj_Setup))
19815 .addMBB(restoreMBB);
19817 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
19818 MIB.addRegMask(RegInfo->getNoPreservedMask());
19819 thisMBB->addSuccessor(mainMBB);
19820 thisMBB->addSuccessor(restoreMBB);
19824 BuildMI(mainMBB, DL, TII->get(X86::MOV32r0), mainDstReg);
19825 mainMBB->addSuccessor(sinkMBB);
19828 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
19829 TII->get(X86::PHI), DstReg)
19830 .addReg(mainDstReg).addMBB(mainMBB)
19831 .addReg(restoreDstReg).addMBB(restoreMBB);
19834 if (RegInfo->hasBasePointer(*MF)) {
19835 const bool Uses64BitFramePtr =
19836 Subtarget->isTarget64BitLP64() || Subtarget->isTargetNaCl64();
19837 X86MachineFunctionInfo *X86FI = MF->getInfo<X86MachineFunctionInfo>();
19838 X86FI->setRestoreBasePointer(MF);
19839 unsigned FramePtr = RegInfo->getFrameRegister(*MF);
19840 unsigned BasePtr = RegInfo->getBaseRegister();
19841 unsigned Opm = Uses64BitFramePtr ? X86::MOV64rm : X86::MOV32rm;
19842 addRegOffset(BuildMI(restoreMBB, DL, TII->get(Opm), BasePtr),
19843 FramePtr, true, X86FI->getRestoreBasePointerOffset())
19844 .setMIFlag(MachineInstr::FrameSetup);
19846 BuildMI(restoreMBB, DL, TII->get(X86::MOV32ri), restoreDstReg).addImm(1);
19847 BuildMI(restoreMBB, DL, TII->get(X86::JMP_1)).addMBB(sinkMBB);
19848 restoreMBB->addSuccessor(sinkMBB);
19850 MI->eraseFromParent();
19854 MachineBasicBlock *
19855 X86TargetLowering::emitEHSjLjLongJmp(MachineInstr *MI,
19856 MachineBasicBlock *MBB) const {
19857 DebugLoc DL = MI->getDebugLoc();
19858 MachineFunction *MF = MBB->getParent();
19859 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
19860 MachineRegisterInfo &MRI = MF->getRegInfo();
19862 // Memory Reference
19863 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
19864 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
19866 MVT PVT = getPointerTy();
19867 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
19868 "Invalid Pointer Size!");
19870 const TargetRegisterClass *RC =
19871 (PVT == MVT::i64) ? &X86::GR64RegClass : &X86::GR32RegClass;
19872 unsigned Tmp = MRI.createVirtualRegister(RC);
19873 // Since FP is only updated here but NOT referenced, it's treated as GPR.
19874 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
19875 unsigned FP = (PVT == MVT::i64) ? X86::RBP : X86::EBP;
19876 unsigned SP = RegInfo->getStackRegister();
19878 MachineInstrBuilder MIB;
19880 const int64_t LabelOffset = 1 * PVT.getStoreSize();
19881 const int64_t SPOffset = 2 * PVT.getStoreSize();
19883 unsigned PtrLoadOpc = (PVT == MVT::i64) ? X86::MOV64rm : X86::MOV32rm;
19884 unsigned IJmpOpc = (PVT == MVT::i64) ? X86::JMP64r : X86::JMP32r;
19887 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), FP);
19888 for (unsigned i = 0; i < X86::AddrNumOperands; ++i)
19889 MIB.addOperand(MI->getOperand(i));
19890 MIB.setMemRefs(MMOBegin, MMOEnd);
19892 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), Tmp);
19893 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
19894 if (i == X86::AddrDisp)
19895 MIB.addDisp(MI->getOperand(i), LabelOffset);
19897 MIB.addOperand(MI->getOperand(i));
19899 MIB.setMemRefs(MMOBegin, MMOEnd);
19901 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), SP);
19902 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
19903 if (i == X86::AddrDisp)
19904 MIB.addDisp(MI->getOperand(i), SPOffset);
19906 MIB.addOperand(MI->getOperand(i));
19908 MIB.setMemRefs(MMOBegin, MMOEnd);
19910 BuildMI(*MBB, MI, DL, TII->get(IJmpOpc)).addReg(Tmp);
19912 MI->eraseFromParent();
19916 // Replace 213-type (isel default) FMA3 instructions with 231-type for
19917 // accumulator loops. Writing back to the accumulator allows the coalescer
19918 // to remove extra copies in the loop.
19919 MachineBasicBlock *
19920 X86TargetLowering::emitFMA3Instr(MachineInstr *MI,
19921 MachineBasicBlock *MBB) const {
19922 MachineOperand &AddendOp = MI->getOperand(3);
19924 // Bail out early if the addend isn't a register - we can't switch these.
19925 if (!AddendOp.isReg())
19928 MachineFunction &MF = *MBB->getParent();
19929 MachineRegisterInfo &MRI = MF.getRegInfo();
19931 // Check whether the addend is defined by a PHI:
19932 assert(MRI.hasOneDef(AddendOp.getReg()) && "Multiple defs in SSA?");
19933 MachineInstr &AddendDef = *MRI.def_instr_begin(AddendOp.getReg());
19934 if (!AddendDef.isPHI())
19937 // Look for the following pattern:
19939 // %addend = phi [%entry, 0], [%loop, %result]
19941 // %result<tied1> = FMA213 %m2<tied0>, %m1, %addend
19945 // %addend = phi [%entry, 0], [%loop, %result]
19947 // %result<tied1> = FMA231 %addend<tied0>, %m1, %m2
19949 for (unsigned i = 1, e = AddendDef.getNumOperands(); i < e; i += 2) {
19950 assert(AddendDef.getOperand(i).isReg());
19951 MachineOperand PHISrcOp = AddendDef.getOperand(i);
19952 MachineInstr &PHISrcInst = *MRI.def_instr_begin(PHISrcOp.getReg());
19953 if (&PHISrcInst == MI) {
19954 // Found a matching instruction.
19955 unsigned NewFMAOpc = 0;
19956 switch (MI->getOpcode()) {
19957 case X86::VFMADDPDr213r: NewFMAOpc = X86::VFMADDPDr231r; break;
19958 case X86::VFMADDPSr213r: NewFMAOpc = X86::VFMADDPSr231r; break;
19959 case X86::VFMADDSDr213r: NewFMAOpc = X86::VFMADDSDr231r; break;
19960 case X86::VFMADDSSr213r: NewFMAOpc = X86::VFMADDSSr231r; break;
19961 case X86::VFMSUBPDr213r: NewFMAOpc = X86::VFMSUBPDr231r; break;
19962 case X86::VFMSUBPSr213r: NewFMAOpc = X86::VFMSUBPSr231r; break;
19963 case X86::VFMSUBSDr213r: NewFMAOpc = X86::VFMSUBSDr231r; break;
19964 case X86::VFMSUBSSr213r: NewFMAOpc = X86::VFMSUBSSr231r; break;
19965 case X86::VFNMADDPDr213r: NewFMAOpc = X86::VFNMADDPDr231r; break;
19966 case X86::VFNMADDPSr213r: NewFMAOpc = X86::VFNMADDPSr231r; break;
19967 case X86::VFNMADDSDr213r: NewFMAOpc = X86::VFNMADDSDr231r; break;
19968 case X86::VFNMADDSSr213r: NewFMAOpc = X86::VFNMADDSSr231r; break;
19969 case X86::VFNMSUBPDr213r: NewFMAOpc = X86::VFNMSUBPDr231r; break;
19970 case X86::VFNMSUBPSr213r: NewFMAOpc = X86::VFNMSUBPSr231r; break;
19971 case X86::VFNMSUBSDr213r: NewFMAOpc = X86::VFNMSUBSDr231r; break;
19972 case X86::VFNMSUBSSr213r: NewFMAOpc = X86::VFNMSUBSSr231r; break;
19973 case X86::VFMADDSUBPDr213r: NewFMAOpc = X86::VFMADDSUBPDr231r; break;
19974 case X86::VFMADDSUBPSr213r: NewFMAOpc = X86::VFMADDSUBPSr231r; break;
19975 case X86::VFMSUBADDPDr213r: NewFMAOpc = X86::VFMSUBADDPDr231r; break;
19976 case X86::VFMSUBADDPSr213r: NewFMAOpc = X86::VFMSUBADDPSr231r; break;
19978 case X86::VFMADDPDr213rY: NewFMAOpc = X86::VFMADDPDr231rY; break;
19979 case X86::VFMADDPSr213rY: NewFMAOpc = X86::VFMADDPSr231rY; break;
19980 case X86::VFMSUBPDr213rY: NewFMAOpc = X86::VFMSUBPDr231rY; break;
19981 case X86::VFMSUBPSr213rY: NewFMAOpc = X86::VFMSUBPSr231rY; break;
19982 case X86::VFNMADDPDr213rY: NewFMAOpc = X86::VFNMADDPDr231rY; break;
19983 case X86::VFNMADDPSr213rY: NewFMAOpc = X86::VFNMADDPSr231rY; break;
19984 case X86::VFNMSUBPDr213rY: NewFMAOpc = X86::VFNMSUBPDr231rY; break;
19985 case X86::VFNMSUBPSr213rY: NewFMAOpc = X86::VFNMSUBPSr231rY; break;
19986 case X86::VFMADDSUBPDr213rY: NewFMAOpc = X86::VFMADDSUBPDr231rY; break;
19987 case X86::VFMADDSUBPSr213rY: NewFMAOpc = X86::VFMADDSUBPSr231rY; break;
19988 case X86::VFMSUBADDPDr213rY: NewFMAOpc = X86::VFMSUBADDPDr231rY; break;
19989 case X86::VFMSUBADDPSr213rY: NewFMAOpc = X86::VFMSUBADDPSr231rY; break;
19990 default: llvm_unreachable("Unrecognized FMA variant.");
19993 const TargetInstrInfo &TII = *Subtarget->getInstrInfo();
19994 MachineInstrBuilder MIB =
19995 BuildMI(MF, MI->getDebugLoc(), TII.get(NewFMAOpc))
19996 .addOperand(MI->getOperand(0))
19997 .addOperand(MI->getOperand(3))
19998 .addOperand(MI->getOperand(2))
19999 .addOperand(MI->getOperand(1));
20000 MBB->insert(MachineBasicBlock::iterator(MI), MIB);
20001 MI->eraseFromParent();
20008 MachineBasicBlock *
20009 X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
20010 MachineBasicBlock *BB) const {
20011 switch (MI->getOpcode()) {
20012 default: llvm_unreachable("Unexpected instr type to insert");
20013 case X86::TAILJMPd64:
20014 case X86::TAILJMPr64:
20015 case X86::TAILJMPm64:
20016 case X86::TAILJMPd64_REX:
20017 case X86::TAILJMPr64_REX:
20018 case X86::TAILJMPm64_REX:
20019 llvm_unreachable("TAILJMP64 would not be touched here.");
20020 case X86::TCRETURNdi64:
20021 case X86::TCRETURNri64:
20022 case X86::TCRETURNmi64:
20024 case X86::WIN_ALLOCA:
20025 return EmitLoweredWinAlloca(MI, BB);
20026 case X86::SEG_ALLOCA_32:
20027 case X86::SEG_ALLOCA_64:
20028 return EmitLoweredSegAlloca(MI, BB);
20029 case X86::TLSCall_32:
20030 case X86::TLSCall_64:
20031 return EmitLoweredTLSCall(MI, BB);
20032 case X86::CMOV_GR8:
20033 case X86::CMOV_FR32:
20034 case X86::CMOV_FR64:
20035 case X86::CMOV_V4F32:
20036 case X86::CMOV_V2F64:
20037 case X86::CMOV_V2I64:
20038 case X86::CMOV_V8F32:
20039 case X86::CMOV_V4F64:
20040 case X86::CMOV_V4I64:
20041 case X86::CMOV_V16F32:
20042 case X86::CMOV_V8F64:
20043 case X86::CMOV_V8I64:
20044 case X86::CMOV_GR16:
20045 case X86::CMOV_GR32:
20046 case X86::CMOV_RFP32:
20047 case X86::CMOV_RFP64:
20048 case X86::CMOV_RFP80:
20049 case X86::CMOV_V8I1:
20050 case X86::CMOV_V16I1:
20051 case X86::CMOV_V32I1:
20052 case X86::CMOV_V64I1:
20053 return EmitLoweredSelect(MI, BB);
20055 case X86::FP32_TO_INT16_IN_MEM:
20056 case X86::FP32_TO_INT32_IN_MEM:
20057 case X86::FP32_TO_INT64_IN_MEM:
20058 case X86::FP64_TO_INT16_IN_MEM:
20059 case X86::FP64_TO_INT32_IN_MEM:
20060 case X86::FP64_TO_INT64_IN_MEM:
20061 case X86::FP80_TO_INT16_IN_MEM:
20062 case X86::FP80_TO_INT32_IN_MEM:
20063 case X86::FP80_TO_INT64_IN_MEM: {
20064 MachineFunction *F = BB->getParent();
20065 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
20066 DebugLoc DL = MI->getDebugLoc();
20068 // Change the floating point control register to use "round towards zero"
20069 // mode when truncating to an integer value.
20070 int CWFrameIdx = F->getFrameInfo()->CreateStackObject(2, 2, false);
20071 addFrameReference(BuildMI(*BB, MI, DL,
20072 TII->get(X86::FNSTCW16m)), CWFrameIdx);
20074 // Load the old value of the high byte of the control word...
20076 F->getRegInfo().createVirtualRegister(&X86::GR16RegClass);
20077 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16rm), OldCW),
20080 // Set the high part to be round to zero...
20081 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mi)), CWFrameIdx)
20084 // Reload the modified control word now...
20085 addFrameReference(BuildMI(*BB, MI, DL,
20086 TII->get(X86::FLDCW16m)), CWFrameIdx);
20088 // Restore the memory image of control word to original value
20089 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mr)), CWFrameIdx)
20092 // Get the X86 opcode to use.
20094 switch (MI->getOpcode()) {
20095 default: llvm_unreachable("illegal opcode!");
20096 case X86::FP32_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m32; break;
20097 case X86::FP32_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m32; break;
20098 case X86::FP32_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m32; break;
20099 case X86::FP64_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m64; break;
20100 case X86::FP64_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m64; break;
20101 case X86::FP64_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m64; break;
20102 case X86::FP80_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m80; break;
20103 case X86::FP80_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m80; break;
20104 case X86::FP80_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m80; break;
20108 MachineOperand &Op = MI->getOperand(0);
20110 AM.BaseType = X86AddressMode::RegBase;
20111 AM.Base.Reg = Op.getReg();
20113 AM.BaseType = X86AddressMode::FrameIndexBase;
20114 AM.Base.FrameIndex = Op.getIndex();
20116 Op = MI->getOperand(1);
20118 AM.Scale = Op.getImm();
20119 Op = MI->getOperand(2);
20121 AM.IndexReg = Op.getImm();
20122 Op = MI->getOperand(3);
20123 if (Op.isGlobal()) {
20124 AM.GV = Op.getGlobal();
20126 AM.Disp = Op.getImm();
20128 addFullAddress(BuildMI(*BB, MI, DL, TII->get(Opc)), AM)
20129 .addReg(MI->getOperand(X86::AddrNumOperands).getReg());
20131 // Reload the original control word now.
20132 addFrameReference(BuildMI(*BB, MI, DL,
20133 TII->get(X86::FLDCW16m)), CWFrameIdx);
20135 MI->eraseFromParent(); // The pseudo instruction is gone now.
20138 // String/text processing lowering.
20139 case X86::PCMPISTRM128REG:
20140 case X86::VPCMPISTRM128REG:
20141 case X86::PCMPISTRM128MEM:
20142 case X86::VPCMPISTRM128MEM:
20143 case X86::PCMPESTRM128REG:
20144 case X86::VPCMPESTRM128REG:
20145 case X86::PCMPESTRM128MEM:
20146 case X86::VPCMPESTRM128MEM:
20147 assert(Subtarget->hasSSE42() &&
20148 "Target must have SSE4.2 or AVX features enabled");
20149 return EmitPCMPSTRM(MI, BB, Subtarget->getInstrInfo());
20151 // String/text processing lowering.
20152 case X86::PCMPISTRIREG:
20153 case X86::VPCMPISTRIREG:
20154 case X86::PCMPISTRIMEM:
20155 case X86::VPCMPISTRIMEM:
20156 case X86::PCMPESTRIREG:
20157 case X86::VPCMPESTRIREG:
20158 case X86::PCMPESTRIMEM:
20159 case X86::VPCMPESTRIMEM:
20160 assert(Subtarget->hasSSE42() &&
20161 "Target must have SSE4.2 or AVX features enabled");
20162 return EmitPCMPSTRI(MI, BB, Subtarget->getInstrInfo());
20164 // Thread synchronization.
20166 return EmitMonitor(MI, BB, Subtarget);
20170 return EmitXBegin(MI, BB, Subtarget->getInstrInfo());
20172 case X86::VASTART_SAVE_XMM_REGS:
20173 return EmitVAStartSaveXMMRegsWithCustomInserter(MI, BB);
20175 case X86::VAARG_64:
20176 return EmitVAARG64WithCustomInserter(MI, BB);
20178 case X86::EH_SjLj_SetJmp32:
20179 case X86::EH_SjLj_SetJmp64:
20180 return emitEHSjLjSetJmp(MI, BB);
20182 case X86::EH_SjLj_LongJmp32:
20183 case X86::EH_SjLj_LongJmp64:
20184 return emitEHSjLjLongJmp(MI, BB);
20186 case TargetOpcode::STATEPOINT:
20187 // As an implementation detail, STATEPOINT shares the STACKMAP format at
20188 // this point in the process. We diverge later.
20189 return emitPatchPoint(MI, BB);
20191 case TargetOpcode::STACKMAP:
20192 case TargetOpcode::PATCHPOINT:
20193 return emitPatchPoint(MI, BB);
20195 case X86::VFMADDPDr213r:
20196 case X86::VFMADDPSr213r:
20197 case X86::VFMADDSDr213r:
20198 case X86::VFMADDSSr213r:
20199 case X86::VFMSUBPDr213r:
20200 case X86::VFMSUBPSr213r:
20201 case X86::VFMSUBSDr213r:
20202 case X86::VFMSUBSSr213r:
20203 case X86::VFNMADDPDr213r:
20204 case X86::VFNMADDPSr213r:
20205 case X86::VFNMADDSDr213r:
20206 case X86::VFNMADDSSr213r:
20207 case X86::VFNMSUBPDr213r:
20208 case X86::VFNMSUBPSr213r:
20209 case X86::VFNMSUBSDr213r:
20210 case X86::VFNMSUBSSr213r:
20211 case X86::VFMADDSUBPDr213r:
20212 case X86::VFMADDSUBPSr213r:
20213 case X86::VFMSUBADDPDr213r:
20214 case X86::VFMSUBADDPSr213r:
20215 case X86::VFMADDPDr213rY:
20216 case X86::VFMADDPSr213rY:
20217 case X86::VFMSUBPDr213rY:
20218 case X86::VFMSUBPSr213rY:
20219 case X86::VFNMADDPDr213rY:
20220 case X86::VFNMADDPSr213rY:
20221 case X86::VFNMSUBPDr213rY:
20222 case X86::VFNMSUBPSr213rY:
20223 case X86::VFMADDSUBPDr213rY:
20224 case X86::VFMADDSUBPSr213rY:
20225 case X86::VFMSUBADDPDr213rY:
20226 case X86::VFMSUBADDPSr213rY:
20227 return emitFMA3Instr(MI, BB);
20231 //===----------------------------------------------------------------------===//
20232 // X86 Optimization Hooks
20233 //===----------------------------------------------------------------------===//
20235 void X86TargetLowering::computeKnownBitsForTargetNode(const SDValue Op,
20238 const SelectionDAG &DAG,
20239 unsigned Depth) const {
20240 unsigned BitWidth = KnownZero.getBitWidth();
20241 unsigned Opc = Op.getOpcode();
20242 assert((Opc >= ISD::BUILTIN_OP_END ||
20243 Opc == ISD::INTRINSIC_WO_CHAIN ||
20244 Opc == ISD::INTRINSIC_W_CHAIN ||
20245 Opc == ISD::INTRINSIC_VOID) &&
20246 "Should use MaskedValueIsZero if you don't know whether Op"
20247 " is a target node!");
20249 KnownZero = KnownOne = APInt(BitWidth, 0); // Don't know anything.
20263 // These nodes' second result is a boolean.
20264 if (Op.getResNo() == 0)
20267 case X86ISD::SETCC:
20268 KnownZero |= APInt::getHighBitsSet(BitWidth, BitWidth - 1);
20270 case ISD::INTRINSIC_WO_CHAIN: {
20271 unsigned IntId = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
20272 unsigned NumLoBits = 0;
20275 case Intrinsic::x86_sse_movmsk_ps:
20276 case Intrinsic::x86_avx_movmsk_ps_256:
20277 case Intrinsic::x86_sse2_movmsk_pd:
20278 case Intrinsic::x86_avx_movmsk_pd_256:
20279 case Intrinsic::x86_mmx_pmovmskb:
20280 case Intrinsic::x86_sse2_pmovmskb_128:
20281 case Intrinsic::x86_avx2_pmovmskb: {
20282 // High bits of movmskp{s|d}, pmovmskb are known zero.
20284 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
20285 case Intrinsic::x86_sse_movmsk_ps: NumLoBits = 4; break;
20286 case Intrinsic::x86_avx_movmsk_ps_256: NumLoBits = 8; break;
20287 case Intrinsic::x86_sse2_movmsk_pd: NumLoBits = 2; break;
20288 case Intrinsic::x86_avx_movmsk_pd_256: NumLoBits = 4; break;
20289 case Intrinsic::x86_mmx_pmovmskb: NumLoBits = 8; break;
20290 case Intrinsic::x86_sse2_pmovmskb_128: NumLoBits = 16; break;
20291 case Intrinsic::x86_avx2_pmovmskb: NumLoBits = 32; break;
20293 KnownZero = APInt::getHighBitsSet(BitWidth, BitWidth - NumLoBits);
20302 unsigned X86TargetLowering::ComputeNumSignBitsForTargetNode(
20304 const SelectionDAG &,
20305 unsigned Depth) const {
20306 // SETCC_CARRY sets the dest to ~0 for true or 0 for false.
20307 if (Op.getOpcode() == X86ISD::SETCC_CARRY)
20308 return Op.getValueType().getScalarType().getSizeInBits();
20314 /// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the
20315 /// node is a GlobalAddress + offset.
20316 bool X86TargetLowering::isGAPlusOffset(SDNode *N,
20317 const GlobalValue* &GA,
20318 int64_t &Offset) const {
20319 if (N->getOpcode() == X86ISD::Wrapper) {
20320 if (isa<GlobalAddressSDNode>(N->getOperand(0))) {
20321 GA = cast<GlobalAddressSDNode>(N->getOperand(0))->getGlobal();
20322 Offset = cast<GlobalAddressSDNode>(N->getOperand(0))->getOffset();
20326 return TargetLowering::isGAPlusOffset(N, GA, Offset);
20329 /// isShuffleHigh128VectorInsertLow - Checks whether the shuffle node is the
20330 /// same as extracting the high 128-bit part of 256-bit vector and then
20331 /// inserting the result into the low part of a new 256-bit vector
20332 static bool isShuffleHigh128VectorInsertLow(ShuffleVectorSDNode *SVOp) {
20333 EVT VT = SVOp->getValueType(0);
20334 unsigned NumElems = VT.getVectorNumElements();
20336 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
20337 for (unsigned i = 0, j = NumElems/2; i != NumElems/2; ++i, ++j)
20338 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) ||
20339 SVOp->getMaskElt(j) >= 0)
20345 /// isShuffleLow128VectorInsertHigh - Checks whether the shuffle node is the
20346 /// same as extracting the low 128-bit part of 256-bit vector and then
20347 /// inserting the result into the high part of a new 256-bit vector
20348 static bool isShuffleLow128VectorInsertHigh(ShuffleVectorSDNode *SVOp) {
20349 EVT VT = SVOp->getValueType(0);
20350 unsigned NumElems = VT.getVectorNumElements();
20352 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
20353 for (unsigned i = NumElems/2, j = 0; i != NumElems; ++i, ++j)
20354 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) ||
20355 SVOp->getMaskElt(j) >= 0)
20361 /// PerformShuffleCombine256 - Performs shuffle combines for 256-bit vectors.
20362 static SDValue PerformShuffleCombine256(SDNode *N, SelectionDAG &DAG,
20363 TargetLowering::DAGCombinerInfo &DCI,
20364 const X86Subtarget* Subtarget) {
20366 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
20367 SDValue V1 = SVOp->getOperand(0);
20368 SDValue V2 = SVOp->getOperand(1);
20369 EVT VT = SVOp->getValueType(0);
20370 unsigned NumElems = VT.getVectorNumElements();
20372 if (V1.getOpcode() == ISD::CONCAT_VECTORS &&
20373 V2.getOpcode() == ISD::CONCAT_VECTORS) {
20377 // V UNDEF BUILD_VECTOR UNDEF
20379 // CONCAT_VECTOR CONCAT_VECTOR
20382 // RESULT: V + zero extended
20384 if (V2.getOperand(0).getOpcode() != ISD::BUILD_VECTOR ||
20385 V2.getOperand(1).getOpcode() != ISD::UNDEF ||
20386 V1.getOperand(1).getOpcode() != ISD::UNDEF)
20389 if (!ISD::isBuildVectorAllZeros(V2.getOperand(0).getNode()))
20392 // To match the shuffle mask, the first half of the mask should
20393 // be exactly the first vector, and all the rest a splat with the
20394 // first element of the second one.
20395 for (unsigned i = 0; i != NumElems/2; ++i)
20396 if (!isUndefOrEqual(SVOp->getMaskElt(i), i) ||
20397 !isUndefOrEqual(SVOp->getMaskElt(i+NumElems/2), NumElems))
20400 // If V1 is coming from a vector load then just fold to a VZEXT_LOAD.
20401 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(V1.getOperand(0))) {
20402 if (Ld->hasNUsesOfValue(1, 0)) {
20403 SDVTList Tys = DAG.getVTList(MVT::v4i64, MVT::Other);
20404 SDValue Ops[] = { Ld->getChain(), Ld->getBasePtr() };
20406 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, dl, Tys, Ops,
20408 Ld->getPointerInfo(),
20409 Ld->getAlignment(),
20410 false/*isVolatile*/, true/*ReadMem*/,
20411 false/*WriteMem*/);
20413 // Make sure the newly-created LOAD is in the same position as Ld in
20414 // terms of dependency. We create a TokenFactor for Ld and ResNode,
20415 // and update uses of Ld's output chain to use the TokenFactor.
20416 if (Ld->hasAnyUseOfValue(1)) {
20417 SDValue NewChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
20418 SDValue(Ld, 1), SDValue(ResNode.getNode(), 1));
20419 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), NewChain);
20420 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(Ld, 1),
20421 SDValue(ResNode.getNode(), 1));
20424 return DAG.getBitcast(VT, ResNode);
20428 // Emit a zeroed vector and insert the desired subvector on its
20430 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
20431 SDValue InsV = Insert128BitVector(Zeros, V1.getOperand(0), 0, DAG, dl);
20432 return DCI.CombineTo(N, InsV);
20435 //===--------------------------------------------------------------------===//
20436 // Combine some shuffles into subvector extracts and inserts:
20439 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
20440 if (isShuffleHigh128VectorInsertLow(SVOp)) {
20441 SDValue V = Extract128BitVector(V1, NumElems/2, DAG, dl);
20442 SDValue InsV = Insert128BitVector(DAG.getUNDEF(VT), V, 0, DAG, dl);
20443 return DCI.CombineTo(N, InsV);
20446 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
20447 if (isShuffleLow128VectorInsertHigh(SVOp)) {
20448 SDValue V = Extract128BitVector(V1, 0, DAG, dl);
20449 SDValue InsV = Insert128BitVector(DAG.getUNDEF(VT), V, NumElems/2, DAG, dl);
20450 return DCI.CombineTo(N, InsV);
20456 /// \brief Combine an arbitrary chain of shuffles into a single instruction if
20459 /// This is the leaf of the recursive combinine below. When we have found some
20460 /// chain of single-use x86 shuffle instructions and accumulated the combined
20461 /// shuffle mask represented by them, this will try to pattern match that mask
20462 /// into either a single instruction if there is a special purpose instruction
20463 /// for this operation, or into a PSHUFB instruction which is a fully general
20464 /// instruction but should only be used to replace chains over a certain depth.
20465 static bool combineX86ShuffleChain(SDValue Op, SDValue Root, ArrayRef<int> Mask,
20466 int Depth, bool HasPSHUFB, SelectionDAG &DAG,
20467 TargetLowering::DAGCombinerInfo &DCI,
20468 const X86Subtarget *Subtarget) {
20469 assert(!Mask.empty() && "Cannot combine an empty shuffle mask!");
20471 // Find the operand that enters the chain. Note that multiple uses are OK
20472 // here, we're not going to remove the operand we find.
20473 SDValue Input = Op.getOperand(0);
20474 while (Input.getOpcode() == ISD::BITCAST)
20475 Input = Input.getOperand(0);
20477 MVT VT = Input.getSimpleValueType();
20478 MVT RootVT = Root.getSimpleValueType();
20481 // Just remove no-op shuffle masks.
20482 if (Mask.size() == 1) {
20483 DCI.CombineTo(Root.getNode(), DAG.getBitcast(RootVT, Input),
20488 // Use the float domain if the operand type is a floating point type.
20489 bool FloatDomain = VT.isFloatingPoint();
20491 // For floating point shuffles, we don't have free copies in the shuffle
20492 // instructions or the ability to load as part of the instruction, so
20493 // canonicalize their shuffles to UNPCK or MOV variants.
20495 // Note that even with AVX we prefer the PSHUFD form of shuffle for integer
20496 // vectors because it can have a load folded into it that UNPCK cannot. This
20497 // doesn't preclude something switching to the shorter encoding post-RA.
20499 // FIXME: Should teach these routines about AVX vector widths.
20500 if (FloatDomain && VT.getSizeInBits() == 128) {
20501 if (Mask.equals({0, 0}) || Mask.equals({1, 1})) {
20502 bool Lo = Mask.equals({0, 0});
20505 // Check if we have SSE3 which will let us use MOVDDUP. That instruction
20506 // is no slower than UNPCKLPD but has the option to fold the input operand
20507 // into even an unaligned memory load.
20508 if (Lo && Subtarget->hasSSE3()) {
20509 Shuffle = X86ISD::MOVDDUP;
20510 ShuffleVT = MVT::v2f64;
20512 // We have MOVLHPS and MOVHLPS throughout SSE and they encode smaller
20513 // than the UNPCK variants.
20514 Shuffle = Lo ? X86ISD::MOVLHPS : X86ISD::MOVHLPS;
20515 ShuffleVT = MVT::v4f32;
20517 if (Depth == 1 && Root->getOpcode() == Shuffle)
20518 return false; // Nothing to do!
20519 Op = DAG.getBitcast(ShuffleVT, Input);
20520 DCI.AddToWorklist(Op.getNode());
20521 if (Shuffle == X86ISD::MOVDDUP)
20522 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op);
20524 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op, Op);
20525 DCI.AddToWorklist(Op.getNode());
20526 DCI.CombineTo(Root.getNode(), DAG.getBitcast(RootVT, Op),
20530 if (Subtarget->hasSSE3() &&
20531 (Mask.equals({0, 0, 2, 2}) || Mask.equals({1, 1, 3, 3}))) {
20532 bool Lo = Mask.equals({0, 0, 2, 2});
20533 unsigned Shuffle = Lo ? X86ISD::MOVSLDUP : X86ISD::MOVSHDUP;
20534 MVT ShuffleVT = MVT::v4f32;
20535 if (Depth == 1 && Root->getOpcode() == Shuffle)
20536 return false; // Nothing to do!
20537 Op = DAG.getBitcast(ShuffleVT, Input);
20538 DCI.AddToWorklist(Op.getNode());
20539 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op);
20540 DCI.AddToWorklist(Op.getNode());
20541 DCI.CombineTo(Root.getNode(), DAG.getBitcast(RootVT, Op),
20545 if (Mask.equals({0, 0, 1, 1}) || Mask.equals({2, 2, 3, 3})) {
20546 bool Lo = Mask.equals({0, 0, 1, 1});
20547 unsigned Shuffle = Lo ? X86ISD::UNPCKL : X86ISD::UNPCKH;
20548 MVT ShuffleVT = MVT::v4f32;
20549 if (Depth == 1 && Root->getOpcode() == Shuffle)
20550 return false; // Nothing to do!
20551 Op = DAG.getBitcast(ShuffleVT, Input);
20552 DCI.AddToWorklist(Op.getNode());
20553 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op, Op);
20554 DCI.AddToWorklist(Op.getNode());
20555 DCI.CombineTo(Root.getNode(), DAG.getBitcast(RootVT, Op),
20561 // We always canonicalize the 8 x i16 and 16 x i8 shuffles into their UNPCK
20562 // variants as none of these have single-instruction variants that are
20563 // superior to the UNPCK formulation.
20564 if (!FloatDomain && VT.getSizeInBits() == 128 &&
20565 (Mask.equals({0, 0, 1, 1, 2, 2, 3, 3}) ||
20566 Mask.equals({4, 4, 5, 5, 6, 6, 7, 7}) ||
20567 Mask.equals({0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7}) ||
20569 {8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 15}))) {
20570 bool Lo = Mask[0] == 0;
20571 unsigned Shuffle = Lo ? X86ISD::UNPCKL : X86ISD::UNPCKH;
20572 if (Depth == 1 && Root->getOpcode() == Shuffle)
20573 return false; // Nothing to do!
20575 switch (Mask.size()) {
20577 ShuffleVT = MVT::v8i16;
20580 ShuffleVT = MVT::v16i8;
20583 llvm_unreachable("Impossible mask size!");
20585 Op = DAG.getBitcast(ShuffleVT, Input);
20586 DCI.AddToWorklist(Op.getNode());
20587 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op, Op);
20588 DCI.AddToWorklist(Op.getNode());
20589 DCI.CombineTo(Root.getNode(), DAG.getBitcast(RootVT, Op),
20594 // Don't try to re-form single instruction chains under any circumstances now
20595 // that we've done encoding canonicalization for them.
20599 // If we have 3 or more shuffle instructions or a chain involving PSHUFB, we
20600 // can replace them with a single PSHUFB instruction profitably. Intel's
20601 // manuals suggest only using PSHUFB if doing so replacing 5 instructions, but
20602 // in practice PSHUFB tends to be *very* fast so we're more aggressive.
20603 if ((Depth >= 3 || HasPSHUFB) && Subtarget->hasSSSE3()) {
20604 SmallVector<SDValue, 16> PSHUFBMask;
20605 int NumBytes = VT.getSizeInBits() / 8;
20606 int Ratio = NumBytes / Mask.size();
20607 for (int i = 0; i < NumBytes; ++i) {
20608 if (Mask[i / Ratio] == SM_SentinelUndef) {
20609 PSHUFBMask.push_back(DAG.getUNDEF(MVT::i8));
20612 int M = Mask[i / Ratio] != SM_SentinelZero
20613 ? Ratio * Mask[i / Ratio] + i % Ratio
20615 PSHUFBMask.push_back(DAG.getConstant(M, DL, MVT::i8));
20617 MVT ByteVT = MVT::getVectorVT(MVT::i8, NumBytes);
20618 Op = DAG.getBitcast(ByteVT, Input);
20619 DCI.AddToWorklist(Op.getNode());
20620 SDValue PSHUFBMaskOp =
20621 DAG.getNode(ISD::BUILD_VECTOR, DL, ByteVT, PSHUFBMask);
20622 DCI.AddToWorklist(PSHUFBMaskOp.getNode());
20623 Op = DAG.getNode(X86ISD::PSHUFB, DL, ByteVT, Op, PSHUFBMaskOp);
20624 DCI.AddToWorklist(Op.getNode());
20625 DCI.CombineTo(Root.getNode(), DAG.getBitcast(RootVT, Op),
20630 // Failed to find any combines.
20634 /// \brief Fully generic combining of x86 shuffle instructions.
20636 /// This should be the last combine run over the x86 shuffle instructions. Once
20637 /// they have been fully optimized, this will recursively consider all chains
20638 /// of single-use shuffle instructions, build a generic model of the cumulative
20639 /// shuffle operation, and check for simpler instructions which implement this
20640 /// operation. We use this primarily for two purposes:
20642 /// 1) Collapse generic shuffles to specialized single instructions when
20643 /// equivalent. In most cases, this is just an encoding size win, but
20644 /// sometimes we will collapse multiple generic shuffles into a single
20645 /// special-purpose shuffle.
20646 /// 2) Look for sequences of shuffle instructions with 3 or more total
20647 /// instructions, and replace them with the slightly more expensive SSSE3
20648 /// PSHUFB instruction if available. We do this as the last combining step
20649 /// to ensure we avoid using PSHUFB if we can implement the shuffle with
20650 /// a suitable short sequence of other instructions. The PHUFB will either
20651 /// use a register or have to read from memory and so is slightly (but only
20652 /// slightly) more expensive than the other shuffle instructions.
20654 /// Because this is inherently a quadratic operation (for each shuffle in
20655 /// a chain, we recurse up the chain), the depth is limited to 8 instructions.
20656 /// This should never be an issue in practice as the shuffle lowering doesn't
20657 /// produce sequences of more than 8 instructions.
20659 /// FIXME: We will currently miss some cases where the redundant shuffling
20660 /// would simplify under the threshold for PSHUFB formation because of
20661 /// combine-ordering. To fix this, we should do the redundant instruction
20662 /// combining in this recursive walk.
20663 static bool combineX86ShufflesRecursively(SDValue Op, SDValue Root,
20664 ArrayRef<int> RootMask,
20665 int Depth, bool HasPSHUFB,
20667 TargetLowering::DAGCombinerInfo &DCI,
20668 const X86Subtarget *Subtarget) {
20669 // Bound the depth of our recursive combine because this is ultimately
20670 // quadratic in nature.
20674 // Directly rip through bitcasts to find the underlying operand.
20675 while (Op.getOpcode() == ISD::BITCAST && Op.getOperand(0).hasOneUse())
20676 Op = Op.getOperand(0);
20678 MVT VT = Op.getSimpleValueType();
20679 if (!VT.isVector())
20680 return false; // Bail if we hit a non-vector.
20682 assert(Root.getSimpleValueType().isVector() &&
20683 "Shuffles operate on vector types!");
20684 assert(VT.getSizeInBits() == Root.getSimpleValueType().getSizeInBits() &&
20685 "Can only combine shuffles of the same vector register size.");
20687 if (!isTargetShuffle(Op.getOpcode()))
20689 SmallVector<int, 16> OpMask;
20691 bool HaveMask = getTargetShuffleMask(Op.getNode(), VT, OpMask, IsUnary);
20692 // We only can combine unary shuffles which we can decode the mask for.
20693 if (!HaveMask || !IsUnary)
20696 assert(VT.getVectorNumElements() == OpMask.size() &&
20697 "Different mask size from vector size!");
20698 assert(((RootMask.size() > OpMask.size() &&
20699 RootMask.size() % OpMask.size() == 0) ||
20700 (OpMask.size() > RootMask.size() &&
20701 OpMask.size() % RootMask.size() == 0) ||
20702 OpMask.size() == RootMask.size()) &&
20703 "The smaller number of elements must divide the larger.");
20704 int RootRatio = std::max<int>(1, OpMask.size() / RootMask.size());
20705 int OpRatio = std::max<int>(1, RootMask.size() / OpMask.size());
20706 assert(((RootRatio == 1 && OpRatio == 1) ||
20707 (RootRatio == 1) != (OpRatio == 1)) &&
20708 "Must not have a ratio for both incoming and op masks!");
20710 SmallVector<int, 16> Mask;
20711 Mask.reserve(std::max(OpMask.size(), RootMask.size()));
20713 // Merge this shuffle operation's mask into our accumulated mask. Note that
20714 // this shuffle's mask will be the first applied to the input, followed by the
20715 // root mask to get us all the way to the root value arrangement. The reason
20716 // for this order is that we are recursing up the operation chain.
20717 for (int i = 0, e = std::max(OpMask.size(), RootMask.size()); i < e; ++i) {
20718 int RootIdx = i / RootRatio;
20719 if (RootMask[RootIdx] < 0) {
20720 // This is a zero or undef lane, we're done.
20721 Mask.push_back(RootMask[RootIdx]);
20725 int RootMaskedIdx = RootMask[RootIdx] * RootRatio + i % RootRatio;
20726 int OpIdx = RootMaskedIdx / OpRatio;
20727 if (OpMask[OpIdx] < 0) {
20728 // The incoming lanes are zero or undef, it doesn't matter which ones we
20730 Mask.push_back(OpMask[OpIdx]);
20734 // Ok, we have non-zero lanes, map them through.
20735 Mask.push_back(OpMask[OpIdx] * OpRatio +
20736 RootMaskedIdx % OpRatio);
20739 // See if we can recurse into the operand to combine more things.
20740 switch (Op.getOpcode()) {
20741 case X86ISD::PSHUFB:
20743 case X86ISD::PSHUFD:
20744 case X86ISD::PSHUFHW:
20745 case X86ISD::PSHUFLW:
20746 if (Op.getOperand(0).hasOneUse() &&
20747 combineX86ShufflesRecursively(Op.getOperand(0), Root, Mask, Depth + 1,
20748 HasPSHUFB, DAG, DCI, Subtarget))
20752 case X86ISD::UNPCKL:
20753 case X86ISD::UNPCKH:
20754 assert(Op.getOperand(0) == Op.getOperand(1) && "We only combine unary shuffles!");
20755 // We can't check for single use, we have to check that this shuffle is the only user.
20756 if (Op->isOnlyUserOf(Op.getOperand(0).getNode()) &&
20757 combineX86ShufflesRecursively(Op.getOperand(0), Root, Mask, Depth + 1,
20758 HasPSHUFB, DAG, DCI, Subtarget))
20763 // Minor canonicalization of the accumulated shuffle mask to make it easier
20764 // to match below. All this does is detect masks with squential pairs of
20765 // elements, and shrink them to the half-width mask. It does this in a loop
20766 // so it will reduce the size of the mask to the minimal width mask which
20767 // performs an equivalent shuffle.
20768 SmallVector<int, 16> WidenedMask;
20769 while (Mask.size() > 1 && canWidenShuffleElements(Mask, WidenedMask)) {
20770 Mask = std::move(WidenedMask);
20771 WidenedMask.clear();
20774 return combineX86ShuffleChain(Op, Root, Mask, Depth, HasPSHUFB, DAG, DCI,
20778 /// \brief Get the PSHUF-style mask from PSHUF node.
20780 /// This is a very minor wrapper around getTargetShuffleMask to easy forming v4
20781 /// PSHUF-style masks that can be reused with such instructions.
20782 static SmallVector<int, 4> getPSHUFShuffleMask(SDValue N) {
20783 MVT VT = N.getSimpleValueType();
20784 SmallVector<int, 4> Mask;
20786 bool HaveMask = getTargetShuffleMask(N.getNode(), VT, Mask, IsUnary);
20790 // If we have more than 128-bits, only the low 128-bits of shuffle mask
20791 // matter. Check that the upper masks are repeats and remove them.
20792 if (VT.getSizeInBits() > 128) {
20793 int LaneElts = 128 / VT.getScalarSizeInBits();
20795 for (int i = 1, NumLanes = VT.getSizeInBits() / 128; i < NumLanes; ++i)
20796 for (int j = 0; j < LaneElts; ++j)
20797 assert(Mask[j] == Mask[i * LaneElts + j] - (LaneElts * i) &&
20798 "Mask doesn't repeat in high 128-bit lanes!");
20800 Mask.resize(LaneElts);
20803 switch (N.getOpcode()) {
20804 case X86ISD::PSHUFD:
20806 case X86ISD::PSHUFLW:
20809 case X86ISD::PSHUFHW:
20810 Mask.erase(Mask.begin(), Mask.begin() + 4);
20811 for (int &M : Mask)
20815 llvm_unreachable("No valid shuffle instruction found!");
20819 /// \brief Search for a combinable shuffle across a chain ending in pshufd.
20821 /// We walk up the chain and look for a combinable shuffle, skipping over
20822 /// shuffles that we could hoist this shuffle's transformation past without
20823 /// altering anything.
20825 combineRedundantDWordShuffle(SDValue N, MutableArrayRef<int> Mask,
20827 TargetLowering::DAGCombinerInfo &DCI) {
20828 assert(N.getOpcode() == X86ISD::PSHUFD &&
20829 "Called with something other than an x86 128-bit half shuffle!");
20832 // Walk up a single-use chain looking for a combinable shuffle. Keep a stack
20833 // of the shuffles in the chain so that we can form a fresh chain to replace
20835 SmallVector<SDValue, 8> Chain;
20836 SDValue V = N.getOperand(0);
20837 for (; V.hasOneUse(); V = V.getOperand(0)) {
20838 switch (V.getOpcode()) {
20840 return SDValue(); // Nothing combined!
20843 // Skip bitcasts as we always know the type for the target specific
20847 case X86ISD::PSHUFD:
20848 // Found another dword shuffle.
20851 case X86ISD::PSHUFLW:
20852 // Check that the low words (being shuffled) are the identity in the
20853 // dword shuffle, and the high words are self-contained.
20854 if (Mask[0] != 0 || Mask[1] != 1 ||
20855 !(Mask[2] >= 2 && Mask[2] < 4 && Mask[3] >= 2 && Mask[3] < 4))
20858 Chain.push_back(V);
20861 case X86ISD::PSHUFHW:
20862 // Check that the high words (being shuffled) are the identity in the
20863 // dword shuffle, and the low words are self-contained.
20864 if (Mask[2] != 2 || Mask[3] != 3 ||
20865 !(Mask[0] >= 0 && Mask[0] < 2 && Mask[1] >= 0 && Mask[1] < 2))
20868 Chain.push_back(V);
20871 case X86ISD::UNPCKL:
20872 case X86ISD::UNPCKH:
20873 // For either i8 -> i16 or i16 -> i32 unpacks, we can combine a dword
20874 // shuffle into a preceding word shuffle.
20875 if (V.getSimpleValueType().getScalarType() != MVT::i8 &&
20876 V.getSimpleValueType().getScalarType() != MVT::i16)
20879 // Search for a half-shuffle which we can combine with.
20880 unsigned CombineOp =
20881 V.getOpcode() == X86ISD::UNPCKL ? X86ISD::PSHUFLW : X86ISD::PSHUFHW;
20882 if (V.getOperand(0) != V.getOperand(1) ||
20883 !V->isOnlyUserOf(V.getOperand(0).getNode()))
20885 Chain.push_back(V);
20886 V = V.getOperand(0);
20888 switch (V.getOpcode()) {
20890 return SDValue(); // Nothing to combine.
20892 case X86ISD::PSHUFLW:
20893 case X86ISD::PSHUFHW:
20894 if (V.getOpcode() == CombineOp)
20897 Chain.push_back(V);
20901 V = V.getOperand(0);
20905 } while (V.hasOneUse());
20908 // Break out of the loop if we break out of the switch.
20912 if (!V.hasOneUse())
20913 // We fell out of the loop without finding a viable combining instruction.
20916 // Merge this node's mask and our incoming mask.
20917 SmallVector<int, 4> VMask = getPSHUFShuffleMask(V);
20918 for (int &M : Mask)
20920 V = DAG.getNode(V.getOpcode(), DL, V.getValueType(), V.getOperand(0),
20921 getV4X86ShuffleImm8ForMask(Mask, DL, DAG));
20923 // Rebuild the chain around this new shuffle.
20924 while (!Chain.empty()) {
20925 SDValue W = Chain.pop_back_val();
20927 if (V.getValueType() != W.getOperand(0).getValueType())
20928 V = DAG.getBitcast(W.getOperand(0).getValueType(), V);
20930 switch (W.getOpcode()) {
20932 llvm_unreachable("Only PSHUF and UNPCK instructions get here!");
20934 case X86ISD::UNPCKL:
20935 case X86ISD::UNPCKH:
20936 V = DAG.getNode(W.getOpcode(), DL, W.getValueType(), V, V);
20939 case X86ISD::PSHUFD:
20940 case X86ISD::PSHUFLW:
20941 case X86ISD::PSHUFHW:
20942 V = DAG.getNode(W.getOpcode(), DL, W.getValueType(), V, W.getOperand(1));
20946 if (V.getValueType() != N.getValueType())
20947 V = DAG.getBitcast(N.getValueType(), V);
20949 // Return the new chain to replace N.
20953 /// \brief Search for a combinable shuffle across a chain ending in pshuflw or pshufhw.
20955 /// We walk up the chain, skipping shuffles of the other half and looking
20956 /// through shuffles which switch halves trying to find a shuffle of the same
20957 /// pair of dwords.
20958 static bool combineRedundantHalfShuffle(SDValue N, MutableArrayRef<int> Mask,
20960 TargetLowering::DAGCombinerInfo &DCI) {
20962 (N.getOpcode() == X86ISD::PSHUFLW || N.getOpcode() == X86ISD::PSHUFHW) &&
20963 "Called with something other than an x86 128-bit half shuffle!");
20965 unsigned CombineOpcode = N.getOpcode();
20967 // Walk up a single-use chain looking for a combinable shuffle.
20968 SDValue V = N.getOperand(0);
20969 for (; V.hasOneUse(); V = V.getOperand(0)) {
20970 switch (V.getOpcode()) {
20972 return false; // Nothing combined!
20975 // Skip bitcasts as we always know the type for the target specific
20979 case X86ISD::PSHUFLW:
20980 case X86ISD::PSHUFHW:
20981 if (V.getOpcode() == CombineOpcode)
20984 // Other-half shuffles are no-ops.
20987 // Break out of the loop if we break out of the switch.
20991 if (!V.hasOneUse())
20992 // We fell out of the loop without finding a viable combining instruction.
20995 // Combine away the bottom node as its shuffle will be accumulated into
20996 // a preceding shuffle.
20997 DCI.CombineTo(N.getNode(), N.getOperand(0), /*AddTo*/ true);
20999 // Record the old value.
21002 // Merge this node's mask and our incoming mask (adjusted to account for all
21003 // the pshufd instructions encountered).
21004 SmallVector<int, 4> VMask = getPSHUFShuffleMask(V);
21005 for (int &M : Mask)
21007 V = DAG.getNode(V.getOpcode(), DL, MVT::v8i16, V.getOperand(0),
21008 getV4X86ShuffleImm8ForMask(Mask, DL, DAG));
21010 // Check that the shuffles didn't cancel each other out. If not, we need to
21011 // combine to the new one.
21013 // Replace the combinable shuffle with the combined one, updating all users
21014 // so that we re-evaluate the chain here.
21015 DCI.CombineTo(Old.getNode(), V, /*AddTo*/ true);
21020 /// \brief Try to combine x86 target specific shuffles.
21021 static SDValue PerformTargetShuffleCombine(SDValue N, SelectionDAG &DAG,
21022 TargetLowering::DAGCombinerInfo &DCI,
21023 const X86Subtarget *Subtarget) {
21025 MVT VT = N.getSimpleValueType();
21026 SmallVector<int, 4> Mask;
21028 switch (N.getOpcode()) {
21029 case X86ISD::PSHUFD:
21030 case X86ISD::PSHUFLW:
21031 case X86ISD::PSHUFHW:
21032 Mask = getPSHUFShuffleMask(N);
21033 assert(Mask.size() == 4);
21039 // Nuke no-op shuffles that show up after combining.
21040 if (isNoopShuffleMask(Mask))
21041 return DCI.CombineTo(N.getNode(), N.getOperand(0), /*AddTo*/ true);
21043 // Look for simplifications involving one or two shuffle instructions.
21044 SDValue V = N.getOperand(0);
21045 switch (N.getOpcode()) {
21048 case X86ISD::PSHUFLW:
21049 case X86ISD::PSHUFHW:
21050 assert(VT.getScalarType() == MVT::i16 && "Bad word shuffle type!");
21052 if (combineRedundantHalfShuffle(N, Mask, DAG, DCI))
21053 return SDValue(); // We combined away this shuffle, so we're done.
21055 // See if this reduces to a PSHUFD which is no more expensive and can
21056 // combine with more operations. Note that it has to at least flip the
21057 // dwords as otherwise it would have been removed as a no-op.
21058 if (makeArrayRef(Mask).equals({2, 3, 0, 1})) {
21059 int DMask[] = {0, 1, 2, 3};
21060 int DOffset = N.getOpcode() == X86ISD::PSHUFLW ? 0 : 2;
21061 DMask[DOffset + 0] = DOffset + 1;
21062 DMask[DOffset + 1] = DOffset + 0;
21063 MVT DVT = MVT::getVectorVT(MVT::i32, VT.getVectorNumElements() / 2);
21064 V = DAG.getBitcast(DVT, V);
21065 DCI.AddToWorklist(V.getNode());
21066 V = DAG.getNode(X86ISD::PSHUFD, DL, DVT, V,
21067 getV4X86ShuffleImm8ForMask(DMask, DL, DAG));
21068 DCI.AddToWorklist(V.getNode());
21069 return DAG.getBitcast(VT, V);
21072 // Look for shuffle patterns which can be implemented as a single unpack.
21073 // FIXME: This doesn't handle the location of the PSHUFD generically, and
21074 // only works when we have a PSHUFD followed by two half-shuffles.
21075 if (Mask[0] == Mask[1] && Mask[2] == Mask[3] &&
21076 (V.getOpcode() == X86ISD::PSHUFLW ||
21077 V.getOpcode() == X86ISD::PSHUFHW) &&
21078 V.getOpcode() != N.getOpcode() &&
21080 SDValue D = V.getOperand(0);
21081 while (D.getOpcode() == ISD::BITCAST && D.hasOneUse())
21082 D = D.getOperand(0);
21083 if (D.getOpcode() == X86ISD::PSHUFD && D.hasOneUse()) {
21084 SmallVector<int, 4> VMask = getPSHUFShuffleMask(V);
21085 SmallVector<int, 4> DMask = getPSHUFShuffleMask(D);
21086 int NOffset = N.getOpcode() == X86ISD::PSHUFLW ? 0 : 4;
21087 int VOffset = V.getOpcode() == X86ISD::PSHUFLW ? 0 : 4;
21089 for (int i = 0; i < 4; ++i) {
21090 WordMask[i + NOffset] = Mask[i] + NOffset;
21091 WordMask[i + VOffset] = VMask[i] + VOffset;
21093 // Map the word mask through the DWord mask.
21095 for (int i = 0; i < 8; ++i)
21096 MappedMask[i] = 2 * DMask[WordMask[i] / 2] + WordMask[i] % 2;
21097 if (makeArrayRef(MappedMask).equals({0, 0, 1, 1, 2, 2, 3, 3}) ||
21098 makeArrayRef(MappedMask).equals({4, 4, 5, 5, 6, 6, 7, 7})) {
21099 // We can replace all three shuffles with an unpack.
21100 V = DAG.getBitcast(VT, D.getOperand(0));
21101 DCI.AddToWorklist(V.getNode());
21102 return DAG.getNode(MappedMask[0] == 0 ? X86ISD::UNPCKL
21111 case X86ISD::PSHUFD:
21112 if (SDValue NewN = combineRedundantDWordShuffle(N, Mask, DAG, DCI))
21121 /// \brief Try to combine a shuffle into a target-specific add-sub node.
21123 /// We combine this directly on the abstract vector shuffle nodes so it is
21124 /// easier to generically match. We also insert dummy vector shuffle nodes for
21125 /// the operands which explicitly discard the lanes which are unused by this
21126 /// operation to try to flow through the rest of the combiner the fact that
21127 /// they're unused.
21128 static SDValue combineShuffleToAddSub(SDNode *N, SelectionDAG &DAG) {
21130 EVT VT = N->getValueType(0);
21132 // We only handle target-independent shuffles.
21133 // FIXME: It would be easy and harmless to use the target shuffle mask
21134 // extraction tool to support more.
21135 if (N->getOpcode() != ISD::VECTOR_SHUFFLE)
21138 auto *SVN = cast<ShuffleVectorSDNode>(N);
21139 ArrayRef<int> Mask = SVN->getMask();
21140 SDValue V1 = N->getOperand(0);
21141 SDValue V2 = N->getOperand(1);
21143 // We require the first shuffle operand to be the SUB node, and the second to
21144 // be the ADD node.
21145 // FIXME: We should support the commuted patterns.
21146 if (V1->getOpcode() != ISD::FSUB || V2->getOpcode() != ISD::FADD)
21149 // If there are other uses of these operations we can't fold them.
21150 if (!V1->hasOneUse() || !V2->hasOneUse())
21153 // Ensure that both operations have the same operands. Note that we can
21154 // commute the FADD operands.
21155 SDValue LHS = V1->getOperand(0), RHS = V1->getOperand(1);
21156 if ((V2->getOperand(0) != LHS || V2->getOperand(1) != RHS) &&
21157 (V2->getOperand(0) != RHS || V2->getOperand(1) != LHS))
21160 // We're looking for blends between FADD and FSUB nodes. We insist on these
21161 // nodes being lined up in a specific expected pattern.
21162 if (!(isShuffleEquivalent(V1, V2, Mask, {0, 3}) ||
21163 isShuffleEquivalent(V1, V2, Mask, {0, 5, 2, 7}) ||
21164 isShuffleEquivalent(V1, V2, Mask, {0, 9, 2, 11, 4, 13, 6, 15})))
21167 // Only specific types are legal at this point, assert so we notice if and
21168 // when these change.
21169 assert((VT == MVT::v4f32 || VT == MVT::v2f64 || VT == MVT::v8f32 ||
21170 VT == MVT::v4f64) &&
21171 "Unknown vector type encountered!");
21173 return DAG.getNode(X86ISD::ADDSUB, DL, VT, LHS, RHS);
21176 /// PerformShuffleCombine - Performs several different shuffle combines.
21177 static SDValue PerformShuffleCombine(SDNode *N, SelectionDAG &DAG,
21178 TargetLowering::DAGCombinerInfo &DCI,
21179 const X86Subtarget *Subtarget) {
21181 SDValue N0 = N->getOperand(0);
21182 SDValue N1 = N->getOperand(1);
21183 EVT VT = N->getValueType(0);
21185 // Don't create instructions with illegal types after legalize types has run.
21186 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
21187 if (!DCI.isBeforeLegalize() && !TLI.isTypeLegal(VT.getVectorElementType()))
21190 // If we have legalized the vector types, look for blends of FADD and FSUB
21191 // nodes that we can fuse into an ADDSUB node.
21192 if (TLI.isTypeLegal(VT) && Subtarget->hasSSE3())
21193 if (SDValue AddSub = combineShuffleToAddSub(N, DAG))
21196 // Combine 256-bit vector shuffles. This is only profitable when in AVX mode
21197 if (Subtarget->hasFp256() && VT.is256BitVector() &&
21198 N->getOpcode() == ISD::VECTOR_SHUFFLE)
21199 return PerformShuffleCombine256(N, DAG, DCI, Subtarget);
21201 // During Type Legalization, when promoting illegal vector types,
21202 // the backend might introduce new shuffle dag nodes and bitcasts.
21204 // This code performs the following transformation:
21205 // fold: (shuffle (bitcast (BINOP A, B)), Undef, <Mask>) ->
21206 // (shuffle (BINOP (bitcast A), (bitcast B)), Undef, <Mask>)
21208 // We do this only if both the bitcast and the BINOP dag nodes have
21209 // one use. Also, perform this transformation only if the new binary
21210 // operation is legal. This is to avoid introducing dag nodes that
21211 // potentially need to be further expanded (or custom lowered) into a
21212 // less optimal sequence of dag nodes.
21213 if (!DCI.isBeforeLegalize() && DCI.isBeforeLegalizeOps() &&
21214 N1.getOpcode() == ISD::UNDEF && N0.hasOneUse() &&
21215 N0.getOpcode() == ISD::BITCAST) {
21216 SDValue BC0 = N0.getOperand(0);
21217 EVT SVT = BC0.getValueType();
21218 unsigned Opcode = BC0.getOpcode();
21219 unsigned NumElts = VT.getVectorNumElements();
21221 if (BC0.hasOneUse() && SVT.isVector() &&
21222 SVT.getVectorNumElements() * 2 == NumElts &&
21223 TLI.isOperationLegal(Opcode, VT)) {
21224 bool CanFold = false;
21236 unsigned SVTNumElts = SVT.getVectorNumElements();
21237 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
21238 for (unsigned i = 0, e = SVTNumElts; i != e && CanFold; ++i)
21239 CanFold = SVOp->getMaskElt(i) == (int)(i * 2);
21240 for (unsigned i = SVTNumElts, e = NumElts; i != e && CanFold; ++i)
21241 CanFold = SVOp->getMaskElt(i) < 0;
21244 SDValue BC00 = DAG.getBitcast(VT, BC0.getOperand(0));
21245 SDValue BC01 = DAG.getBitcast(VT, BC0.getOperand(1));
21246 SDValue NewBinOp = DAG.getNode(BC0.getOpcode(), dl, VT, BC00, BC01);
21247 return DAG.getVectorShuffle(VT, dl, NewBinOp, N1, &SVOp->getMask()[0]);
21252 // Combine a vector_shuffle that is equal to build_vector load1, load2, load3,
21253 // load4, <0, 1, 2, 3> into a 128-bit load if the load addresses are
21254 // consecutive, non-overlapping, and in the right order.
21255 SmallVector<SDValue, 16> Elts;
21256 for (unsigned i = 0, e = VT.getVectorNumElements(); i != e; ++i)
21257 Elts.push_back(getShuffleScalarElt(N, i, DAG, 0));
21259 SDValue LD = EltsFromConsecutiveLoads(VT, Elts, dl, DAG, true);
21263 if (isTargetShuffle(N->getOpcode())) {
21265 PerformTargetShuffleCombine(SDValue(N, 0), DAG, DCI, Subtarget);
21266 if (Shuffle.getNode())
21269 // Try recursively combining arbitrary sequences of x86 shuffle
21270 // instructions into higher-order shuffles. We do this after combining
21271 // specific PSHUF instruction sequences into their minimal form so that we
21272 // can evaluate how many specialized shuffle instructions are involved in
21273 // a particular chain.
21274 SmallVector<int, 1> NonceMask; // Just a placeholder.
21275 NonceMask.push_back(0);
21276 if (combineX86ShufflesRecursively(SDValue(N, 0), SDValue(N, 0), NonceMask,
21277 /*Depth*/ 1, /*HasPSHUFB*/ false, DAG,
21279 return SDValue(); // This routine will use CombineTo to replace N.
21285 /// XFormVExtractWithShuffleIntoLoad - Check if a vector extract from a target
21286 /// specific shuffle of a load can be folded into a single element load.
21287 /// Similar handling for VECTOR_SHUFFLE is performed by DAGCombiner, but
21288 /// shuffles have been custom lowered so we need to handle those here.
21289 static SDValue XFormVExtractWithShuffleIntoLoad(SDNode *N, SelectionDAG &DAG,
21290 TargetLowering::DAGCombinerInfo &DCI) {
21291 if (DCI.isBeforeLegalizeOps())
21294 SDValue InVec = N->getOperand(0);
21295 SDValue EltNo = N->getOperand(1);
21297 if (!isa<ConstantSDNode>(EltNo))
21300 EVT OriginalVT = InVec.getValueType();
21302 if (InVec.getOpcode() == ISD::BITCAST) {
21303 // Don't duplicate a load with other uses.
21304 if (!InVec.hasOneUse())
21306 EVT BCVT = InVec.getOperand(0).getValueType();
21307 if (!BCVT.isVector() ||
21308 BCVT.getVectorNumElements() != OriginalVT.getVectorNumElements())
21310 InVec = InVec.getOperand(0);
21313 EVT CurrentVT = InVec.getValueType();
21315 if (!isTargetShuffle(InVec.getOpcode()))
21318 // Don't duplicate a load with other uses.
21319 if (!InVec.hasOneUse())
21322 SmallVector<int, 16> ShuffleMask;
21324 if (!getTargetShuffleMask(InVec.getNode(), CurrentVT.getSimpleVT(),
21325 ShuffleMask, UnaryShuffle))
21328 // Select the input vector, guarding against out of range extract vector.
21329 unsigned NumElems = CurrentVT.getVectorNumElements();
21330 int Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();
21331 int Idx = (Elt > (int)NumElems) ? -1 : ShuffleMask[Elt];
21332 SDValue LdNode = (Idx < (int)NumElems) ? InVec.getOperand(0)
21333 : InVec.getOperand(1);
21335 // If inputs to shuffle are the same for both ops, then allow 2 uses
21336 unsigned AllowedUses = InVec.getNumOperands() > 1 &&
21337 InVec.getOperand(0) == InVec.getOperand(1) ? 2 : 1;
21339 if (LdNode.getOpcode() == ISD::BITCAST) {
21340 // Don't duplicate a load with other uses.
21341 if (!LdNode.getNode()->hasNUsesOfValue(AllowedUses, 0))
21344 AllowedUses = 1; // only allow 1 load use if we have a bitcast
21345 LdNode = LdNode.getOperand(0);
21348 if (!ISD::isNormalLoad(LdNode.getNode()))
21351 LoadSDNode *LN0 = cast<LoadSDNode>(LdNode);
21353 if (!LN0 ||!LN0->hasNUsesOfValue(AllowedUses, 0) || LN0->isVolatile())
21356 EVT EltVT = N->getValueType(0);
21357 // If there's a bitcast before the shuffle, check if the load type and
21358 // alignment is valid.
21359 unsigned Align = LN0->getAlignment();
21360 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
21361 unsigned NewAlign = TLI.getDataLayout()->getABITypeAlignment(
21362 EltVT.getTypeForEVT(*DAG.getContext()));
21364 if (NewAlign > Align || !TLI.isOperationLegalOrCustom(ISD::LOAD, EltVT))
21367 // All checks match so transform back to vector_shuffle so that DAG combiner
21368 // can finish the job
21371 // Create shuffle node taking into account the case that its a unary shuffle
21372 SDValue Shuffle = (UnaryShuffle) ? DAG.getUNDEF(CurrentVT)
21373 : InVec.getOperand(1);
21374 Shuffle = DAG.getVectorShuffle(CurrentVT, dl,
21375 InVec.getOperand(0), Shuffle,
21377 Shuffle = DAG.getBitcast(OriginalVT, Shuffle);
21378 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, N->getValueType(0), Shuffle,
21382 /// \brief Detect bitcasts between i32 to x86mmx low word. Since MMX types are
21383 /// special and don't usually play with other vector types, it's better to
21384 /// handle them early to be sure we emit efficient code by avoiding
21385 /// store-load conversions.
21386 static SDValue PerformBITCASTCombine(SDNode *N, SelectionDAG &DAG) {
21387 if (N->getValueType(0) != MVT::x86mmx ||
21388 N->getOperand(0)->getOpcode() != ISD::BUILD_VECTOR ||
21389 N->getOperand(0)->getValueType(0) != MVT::v2i32)
21392 SDValue V = N->getOperand(0);
21393 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V.getOperand(1));
21394 if (C && C->getZExtValue() == 0 && V.getOperand(0).getValueType() == MVT::i32)
21395 return DAG.getNode(X86ISD::MMX_MOVW2D, SDLoc(V.getOperand(0)),
21396 N->getValueType(0), V.getOperand(0));
21401 /// PerformEXTRACT_VECTOR_ELTCombine - Detect vector gather/scatter index
21402 /// generation and convert it from being a bunch of shuffles and extracts
21403 /// into a somewhat faster sequence. For i686, the best sequence is apparently
21404 /// storing the value and loading scalars back, while for x64 we should
21405 /// use 64-bit extracts and shifts.
21406 static SDValue PerformEXTRACT_VECTOR_ELTCombine(SDNode *N, SelectionDAG &DAG,
21407 TargetLowering::DAGCombinerInfo &DCI) {
21408 SDValue NewOp = XFormVExtractWithShuffleIntoLoad(N, DAG, DCI);
21409 if (NewOp.getNode())
21412 SDValue InputVector = N->getOperand(0);
21413 SDLoc dl(InputVector);
21414 // Detect mmx to i32 conversion through a v2i32 elt extract.
21415 if (InputVector.getOpcode() == ISD::BITCAST && InputVector.hasOneUse() &&
21416 N->getValueType(0) == MVT::i32 &&
21417 InputVector.getValueType() == MVT::v2i32) {
21419 // The bitcast source is a direct mmx result.
21420 SDValue MMXSrc = InputVector.getNode()->getOperand(0);
21421 if (MMXSrc.getValueType() == MVT::x86mmx)
21422 return DAG.getNode(X86ISD::MMX_MOVD2W, SDLoc(InputVector),
21423 N->getValueType(0),
21424 InputVector.getNode()->getOperand(0));
21426 // The mmx is indirect: (i64 extract_elt (v1i64 bitcast (x86mmx ...))).
21427 SDValue MMXSrcOp = MMXSrc.getOperand(0);
21428 if (MMXSrc.getOpcode() == ISD::EXTRACT_VECTOR_ELT && MMXSrc.hasOneUse() &&
21429 MMXSrc.getValueType() == MVT::i64 && MMXSrcOp.hasOneUse() &&
21430 MMXSrcOp.getOpcode() == ISD::BITCAST &&
21431 MMXSrcOp.getValueType() == MVT::v1i64 &&
21432 MMXSrcOp.getOperand(0).getValueType() == MVT::x86mmx)
21433 return DAG.getNode(X86ISD::MMX_MOVD2W, SDLoc(InputVector),
21434 N->getValueType(0),
21435 MMXSrcOp.getOperand(0));
21438 EVT VT = N->getValueType(0);
21440 if (VT == MVT::i1 && dyn_cast<ConstantSDNode>(N->getOperand(1)) &&
21441 InputVector.getOpcode() == ISD::BITCAST &&
21442 dyn_cast<ConstantSDNode>(InputVector.getOperand(0))) {
21443 uint64_t ExtractedElt =
21444 cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
21445 uint64_t InputValue =
21446 cast<ConstantSDNode>(InputVector.getOperand(0))->getZExtValue();
21447 uint64_t Res = (InputValue >> ExtractedElt) & 1;
21448 return DAG.getConstant(Res, dl, MVT::i1);
21450 // Only operate on vectors of 4 elements, where the alternative shuffling
21451 // gets to be more expensive.
21452 if (InputVector.getValueType() != MVT::v4i32)
21455 // Check whether every use of InputVector is an EXTRACT_VECTOR_ELT with a
21456 // single use which is a sign-extend or zero-extend, and all elements are
21458 SmallVector<SDNode *, 4> Uses;
21459 unsigned ExtractedElements = 0;
21460 for (SDNode::use_iterator UI = InputVector.getNode()->use_begin(),
21461 UE = InputVector.getNode()->use_end(); UI != UE; ++UI) {
21462 if (UI.getUse().getResNo() != InputVector.getResNo())
21465 SDNode *Extract = *UI;
21466 if (Extract->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
21469 if (Extract->getValueType(0) != MVT::i32)
21471 if (!Extract->hasOneUse())
21473 if (Extract->use_begin()->getOpcode() != ISD::SIGN_EXTEND &&
21474 Extract->use_begin()->getOpcode() != ISD::ZERO_EXTEND)
21476 if (!isa<ConstantSDNode>(Extract->getOperand(1)))
21479 // Record which element was extracted.
21480 ExtractedElements |=
21481 1 << cast<ConstantSDNode>(Extract->getOperand(1))->getZExtValue();
21483 Uses.push_back(Extract);
21486 // If not all the elements were used, this may not be worthwhile.
21487 if (ExtractedElements != 15)
21490 // Ok, we've now decided to do the transformation.
21491 // If 64-bit shifts are legal, use the extract-shift sequence,
21492 // otherwise bounce the vector off the cache.
21493 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
21496 if (TLI.isOperationLegal(ISD::SRA, MVT::i64)) {
21497 SDValue Cst = DAG.getBitcast(MVT::v2i64, InputVector);
21498 EVT VecIdxTy = DAG.getTargetLoweringInfo().getVectorIdxTy();
21499 SDValue BottomHalf = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i64, Cst,
21500 DAG.getConstant(0, dl, VecIdxTy));
21501 SDValue TopHalf = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i64, Cst,
21502 DAG.getConstant(1, dl, VecIdxTy));
21504 SDValue ShAmt = DAG.getConstant(32, dl,
21505 DAG.getTargetLoweringInfo().getShiftAmountTy(MVT::i64));
21506 Vals[0] = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, BottomHalf);
21507 Vals[1] = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32,
21508 DAG.getNode(ISD::SRA, dl, MVT::i64, BottomHalf, ShAmt));
21509 Vals[2] = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, TopHalf);
21510 Vals[3] = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32,
21511 DAG.getNode(ISD::SRA, dl, MVT::i64, TopHalf, ShAmt));
21513 // Store the value to a temporary stack slot.
21514 SDValue StackPtr = DAG.CreateStackTemporary(InputVector.getValueType());
21515 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, InputVector, StackPtr,
21516 MachinePointerInfo(), false, false, 0);
21518 EVT ElementType = InputVector.getValueType().getVectorElementType();
21519 unsigned EltSize = ElementType.getSizeInBits() / 8;
21521 // Replace each use (extract) with a load of the appropriate element.
21522 for (unsigned i = 0; i < 4; ++i) {
21523 uint64_t Offset = EltSize * i;
21524 SDValue OffsetVal = DAG.getConstant(Offset, dl, TLI.getPointerTy());
21526 SDValue ScalarAddr = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(),
21527 StackPtr, OffsetVal);
21529 // Load the scalar.
21530 Vals[i] = DAG.getLoad(ElementType, dl, Ch,
21531 ScalarAddr, MachinePointerInfo(),
21532 false, false, false, 0);
21537 // Replace the extracts
21538 for (SmallVectorImpl<SDNode *>::iterator UI = Uses.begin(),
21539 UE = Uses.end(); UI != UE; ++UI) {
21540 SDNode *Extract = *UI;
21542 SDValue Idx = Extract->getOperand(1);
21543 uint64_t IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
21544 DAG.ReplaceAllUsesOfValueWith(SDValue(Extract, 0), Vals[IdxVal]);
21547 // The replacement was made in place; don't return anything.
21551 /// \brief Matches a VSELECT onto min/max or return 0 if the node doesn't match.
21552 static std::pair<unsigned, bool>
21553 matchIntegerMINMAX(SDValue Cond, EVT VT, SDValue LHS, SDValue RHS,
21554 SelectionDAG &DAG, const X86Subtarget *Subtarget) {
21555 if (!VT.isVector())
21556 return std::make_pair(0, false);
21558 bool NeedSplit = false;
21559 switch (VT.getSimpleVT().SimpleTy) {
21560 default: return std::make_pair(0, false);
21563 if (!Subtarget->hasVLX())
21564 return std::make_pair(0, false);
21568 if (!Subtarget->hasBWI())
21569 return std::make_pair(0, false);
21573 if (!Subtarget->hasAVX512())
21574 return std::make_pair(0, false);
21579 if (!Subtarget->hasAVX2())
21581 if (!Subtarget->hasAVX())
21582 return std::make_pair(0, false);
21587 if (!Subtarget->hasSSE2())
21588 return std::make_pair(0, false);
21591 // SSE2 has only a small subset of the operations.
21592 bool hasUnsigned = Subtarget->hasSSE41() ||
21593 (Subtarget->hasSSE2() && VT == MVT::v16i8);
21594 bool hasSigned = Subtarget->hasSSE41() ||
21595 (Subtarget->hasSSE2() && VT == MVT::v8i16);
21597 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
21600 // Check for x CC y ? x : y.
21601 if (DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
21602 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
21607 Opc = hasUnsigned ? X86ISD::UMIN : 0u; break;
21610 Opc = hasUnsigned ? X86ISD::UMAX : 0u; break;
21613 Opc = hasSigned ? X86ISD::SMIN : 0u; break;
21616 Opc = hasSigned ? X86ISD::SMAX : 0u; break;
21618 // Check for x CC y ? y : x -- a min/max with reversed arms.
21619 } else if (DAG.isEqualTo(LHS, Cond.getOperand(1)) &&
21620 DAG.isEqualTo(RHS, Cond.getOperand(0))) {
21625 Opc = hasUnsigned ? X86ISD::UMAX : 0u; break;
21628 Opc = hasUnsigned ? X86ISD::UMIN : 0u; break;
21631 Opc = hasSigned ? X86ISD::SMAX : 0u; break;
21634 Opc = hasSigned ? X86ISD::SMIN : 0u; break;
21638 return std::make_pair(Opc, NeedSplit);
21642 transformVSELECTtoBlendVECTOR_SHUFFLE(SDNode *N, SelectionDAG &DAG,
21643 const X86Subtarget *Subtarget) {
21645 SDValue Cond = N->getOperand(0);
21646 SDValue LHS = N->getOperand(1);
21647 SDValue RHS = N->getOperand(2);
21649 if (Cond.getOpcode() == ISD::SIGN_EXTEND) {
21650 SDValue CondSrc = Cond->getOperand(0);
21651 if (CondSrc->getOpcode() == ISD::SIGN_EXTEND_INREG)
21652 Cond = CondSrc->getOperand(0);
21655 if (!ISD::isBuildVectorOfConstantSDNodes(Cond.getNode()))
21658 // A vselect where all conditions and data are constants can be optimized into
21659 // a single vector load by SelectionDAGLegalize::ExpandBUILD_VECTOR().
21660 if (ISD::isBuildVectorOfConstantSDNodes(LHS.getNode()) &&
21661 ISD::isBuildVectorOfConstantSDNodes(RHS.getNode()))
21664 unsigned MaskValue = 0;
21665 if (!BUILD_VECTORtoBlendMask(cast<BuildVectorSDNode>(Cond), MaskValue))
21668 MVT VT = N->getSimpleValueType(0);
21669 unsigned NumElems = VT.getVectorNumElements();
21670 SmallVector<int, 8> ShuffleMask(NumElems, -1);
21671 for (unsigned i = 0; i < NumElems; ++i) {
21672 // Be sure we emit undef where we can.
21673 if (Cond.getOperand(i)->getOpcode() == ISD::UNDEF)
21674 ShuffleMask[i] = -1;
21676 ShuffleMask[i] = i + NumElems * ((MaskValue >> i) & 1);
21679 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
21680 if (!TLI.isShuffleMaskLegal(ShuffleMask, VT))
21682 return DAG.getVectorShuffle(VT, dl, LHS, RHS, &ShuffleMask[0]);
21685 /// PerformSELECTCombine - Do target-specific dag combines on SELECT and VSELECT
21687 static SDValue PerformSELECTCombine(SDNode *N, SelectionDAG &DAG,
21688 TargetLowering::DAGCombinerInfo &DCI,
21689 const X86Subtarget *Subtarget) {
21691 SDValue Cond = N->getOperand(0);
21692 // Get the LHS/RHS of the select.
21693 SDValue LHS = N->getOperand(1);
21694 SDValue RHS = N->getOperand(2);
21695 EVT VT = LHS.getValueType();
21696 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
21698 // If we have SSE[12] support, try to form min/max nodes. SSE min/max
21699 // instructions match the semantics of the common C idiom x<y?x:y but not
21700 // x<=y?x:y, because of how they handle negative zero (which can be
21701 // ignored in unsafe-math mode).
21702 // We also try to create v2f32 min/max nodes, which we later widen to v4f32.
21703 if (Cond.getOpcode() == ISD::SETCC && VT.isFloatingPoint() &&
21704 VT != MVT::f80 && (TLI.isTypeLegal(VT) || VT == MVT::v2f32) &&
21705 (Subtarget->hasSSE2() ||
21706 (Subtarget->hasSSE1() && VT.getScalarType() == MVT::f32))) {
21707 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
21709 unsigned Opcode = 0;
21710 // Check for x CC y ? x : y.
21711 if (DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
21712 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
21716 // Converting this to a min would handle NaNs incorrectly, and swapping
21717 // the operands would cause it to handle comparisons between positive
21718 // and negative zero incorrectly.
21719 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
21720 if (!DAG.getTarget().Options.UnsafeFPMath &&
21721 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
21723 std::swap(LHS, RHS);
21725 Opcode = X86ISD::FMIN;
21728 // Converting this to a min would handle comparisons between positive
21729 // and negative zero incorrectly.
21730 if (!DAG.getTarget().Options.UnsafeFPMath &&
21731 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
21733 Opcode = X86ISD::FMIN;
21736 // Converting this to a min would handle both negative zeros and NaNs
21737 // incorrectly, but we can swap the operands to fix both.
21738 std::swap(LHS, RHS);
21742 Opcode = X86ISD::FMIN;
21746 // Converting this to a max would handle comparisons between positive
21747 // and negative zero incorrectly.
21748 if (!DAG.getTarget().Options.UnsafeFPMath &&
21749 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
21751 Opcode = X86ISD::FMAX;
21754 // Converting this to a max would handle NaNs incorrectly, and swapping
21755 // the operands would cause it to handle comparisons between positive
21756 // and negative zero incorrectly.
21757 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
21758 if (!DAG.getTarget().Options.UnsafeFPMath &&
21759 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
21761 std::swap(LHS, RHS);
21763 Opcode = X86ISD::FMAX;
21766 // Converting this to a max would handle both negative zeros and NaNs
21767 // incorrectly, but we can swap the operands to fix both.
21768 std::swap(LHS, RHS);
21772 Opcode = X86ISD::FMAX;
21775 // Check for x CC y ? y : x -- a min/max with reversed arms.
21776 } else if (DAG.isEqualTo(LHS, Cond.getOperand(1)) &&
21777 DAG.isEqualTo(RHS, Cond.getOperand(0))) {
21781 // Converting this to a min would handle comparisons between positive
21782 // and negative zero incorrectly, and swapping the operands would
21783 // cause it to handle NaNs incorrectly.
21784 if (!DAG.getTarget().Options.UnsafeFPMath &&
21785 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS))) {
21786 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
21788 std::swap(LHS, RHS);
21790 Opcode = X86ISD::FMIN;
21793 // Converting this to a min would handle NaNs incorrectly.
21794 if (!DAG.getTarget().Options.UnsafeFPMath &&
21795 (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)))
21797 Opcode = X86ISD::FMIN;
21800 // Converting this to a min would handle both negative zeros and NaNs
21801 // incorrectly, but we can swap the operands to fix both.
21802 std::swap(LHS, RHS);
21806 Opcode = X86ISD::FMIN;
21810 // Converting this to a max would handle NaNs incorrectly.
21811 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
21813 Opcode = X86ISD::FMAX;
21816 // Converting this to a max would handle comparisons between positive
21817 // and negative zero incorrectly, and swapping the operands would
21818 // cause it to handle NaNs incorrectly.
21819 if (!DAG.getTarget().Options.UnsafeFPMath &&
21820 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS)) {
21821 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
21823 std::swap(LHS, RHS);
21825 Opcode = X86ISD::FMAX;
21828 // Converting this to a max would handle both negative zeros and NaNs
21829 // incorrectly, but we can swap the operands to fix both.
21830 std::swap(LHS, RHS);
21834 Opcode = X86ISD::FMAX;
21840 return DAG.getNode(Opcode, DL, N->getValueType(0), LHS, RHS);
21843 EVT CondVT = Cond.getValueType();
21844 if (Subtarget->hasAVX512() && VT.isVector() && CondVT.isVector() &&
21845 CondVT.getVectorElementType() == MVT::i1) {
21846 // v16i8 (select v16i1, v16i8, v16i8) does not have a proper
21847 // lowering on KNL. In this case we convert it to
21848 // v16i8 (select v16i8, v16i8, v16i8) and use AVX instruction.
21849 // The same situation for all 128 and 256-bit vectors of i8 and i16.
21850 // Since SKX these selects have a proper lowering.
21851 EVT OpVT = LHS.getValueType();
21852 if ((OpVT.is128BitVector() || OpVT.is256BitVector()) &&
21853 (OpVT.getVectorElementType() == MVT::i8 ||
21854 OpVT.getVectorElementType() == MVT::i16) &&
21855 !(Subtarget->hasBWI() && Subtarget->hasVLX())) {
21856 Cond = DAG.getNode(ISD::SIGN_EXTEND, DL, OpVT, Cond);
21857 DCI.AddToWorklist(Cond.getNode());
21858 return DAG.getNode(N->getOpcode(), DL, OpVT, Cond, LHS, RHS);
21861 // If this is a select between two integer constants, try to do some
21863 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(LHS)) {
21864 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(RHS))
21865 // Don't do this for crazy integer types.
21866 if (DAG.getTargetLoweringInfo().isTypeLegal(LHS.getValueType())) {
21867 // If this is efficiently invertible, canonicalize the LHSC/RHSC values
21868 // so that TrueC (the true value) is larger than FalseC.
21869 bool NeedsCondInvert = false;
21871 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue()) &&
21872 // Efficiently invertible.
21873 (Cond.getOpcode() == ISD::SETCC || // setcc -> invertible.
21874 (Cond.getOpcode() == ISD::XOR && // xor(X, C) -> invertible.
21875 isa<ConstantSDNode>(Cond.getOperand(1))))) {
21876 NeedsCondInvert = true;
21877 std::swap(TrueC, FalseC);
21880 // Optimize C ? 8 : 0 -> zext(C) << 3. Likewise for any pow2/0.
21881 if (FalseC->getAPIntValue() == 0 &&
21882 TrueC->getAPIntValue().isPowerOf2()) {
21883 if (NeedsCondInvert) // Invert the condition if needed.
21884 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
21885 DAG.getConstant(1, DL, Cond.getValueType()));
21887 // Zero extend the condition if needed.
21888 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, LHS.getValueType(), Cond);
21890 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
21891 return DAG.getNode(ISD::SHL, DL, LHS.getValueType(), Cond,
21892 DAG.getConstant(ShAmt, DL, MVT::i8));
21895 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst.
21896 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
21897 if (NeedsCondInvert) // Invert the condition if needed.
21898 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
21899 DAG.getConstant(1, DL, Cond.getValueType()));
21901 // Zero extend the condition if needed.
21902 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
21903 FalseC->getValueType(0), Cond);
21904 return DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
21905 SDValue(FalseC, 0));
21908 // Optimize cases that will turn into an LEA instruction. This requires
21909 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
21910 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
21911 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
21912 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
21914 bool isFastMultiplier = false;
21916 switch ((unsigned char)Diff) {
21918 case 1: // result = add base, cond
21919 case 2: // result = lea base( , cond*2)
21920 case 3: // result = lea base(cond, cond*2)
21921 case 4: // result = lea base( , cond*4)
21922 case 5: // result = lea base(cond, cond*4)
21923 case 8: // result = lea base( , cond*8)
21924 case 9: // result = lea base(cond, cond*8)
21925 isFastMultiplier = true;
21930 if (isFastMultiplier) {
21931 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
21932 if (NeedsCondInvert) // Invert the condition if needed.
21933 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
21934 DAG.getConstant(1, DL, Cond.getValueType()));
21936 // Zero extend the condition if needed.
21937 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
21939 // Scale the condition by the difference.
21941 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
21942 DAG.getConstant(Diff, DL,
21943 Cond.getValueType()));
21945 // Add the base if non-zero.
21946 if (FalseC->getAPIntValue() != 0)
21947 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
21948 SDValue(FalseC, 0));
21955 // Canonicalize max and min:
21956 // (x > y) ? x : y -> (x >= y) ? x : y
21957 // (x < y) ? x : y -> (x <= y) ? x : y
21958 // This allows use of COND_S / COND_NS (see TranslateX86CC) which eliminates
21959 // the need for an extra compare
21960 // against zero. e.g.
21961 // (x - y) > 0 : (x - y) ? 0 -> (x - y) >= 0 : (x - y) ? 0
21963 // testl %edi, %edi
21965 // cmovgl %edi, %eax
21969 // cmovsl %eax, %edi
21970 if (N->getOpcode() == ISD::SELECT && Cond.getOpcode() == ISD::SETCC &&
21971 DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
21972 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
21973 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
21978 ISD::CondCode NewCC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGE;
21979 Cond = DAG.getSetCC(SDLoc(Cond), Cond.getValueType(),
21980 Cond.getOperand(0), Cond.getOperand(1), NewCC);
21981 return DAG.getNode(ISD::SELECT, DL, VT, Cond, LHS, RHS);
21986 // Early exit check
21987 if (!TLI.isTypeLegal(VT))
21990 // Match VSELECTs into subs with unsigned saturation.
21991 if (N->getOpcode() == ISD::VSELECT && Cond.getOpcode() == ISD::SETCC &&
21992 // psubus is available in SSE2 and AVX2 for i8 and i16 vectors.
21993 ((Subtarget->hasSSE2() && (VT == MVT::v16i8 || VT == MVT::v8i16)) ||
21994 (Subtarget->hasAVX2() && (VT == MVT::v32i8 || VT == MVT::v16i16)))) {
21995 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
21997 // Check if one of the arms of the VSELECT is a zero vector. If it's on the
21998 // left side invert the predicate to simplify logic below.
22000 if (ISD::isBuildVectorAllZeros(LHS.getNode())) {
22002 CC = ISD::getSetCCInverse(CC, true);
22003 } else if (ISD::isBuildVectorAllZeros(RHS.getNode())) {
22007 if (Other.getNode() && Other->getNumOperands() == 2 &&
22008 DAG.isEqualTo(Other->getOperand(0), Cond.getOperand(0))) {
22009 SDValue OpLHS = Other->getOperand(0), OpRHS = Other->getOperand(1);
22010 SDValue CondRHS = Cond->getOperand(1);
22012 // Look for a general sub with unsigned saturation first.
22013 // x >= y ? x-y : 0 --> subus x, y
22014 // x > y ? x-y : 0 --> subus x, y
22015 if ((CC == ISD::SETUGE || CC == ISD::SETUGT) &&
22016 Other->getOpcode() == ISD::SUB && DAG.isEqualTo(OpRHS, CondRHS))
22017 return DAG.getNode(X86ISD::SUBUS, DL, VT, OpLHS, OpRHS);
22019 if (auto *OpRHSBV = dyn_cast<BuildVectorSDNode>(OpRHS))
22020 if (auto *OpRHSConst = OpRHSBV->getConstantSplatNode()) {
22021 if (auto *CondRHSBV = dyn_cast<BuildVectorSDNode>(CondRHS))
22022 if (auto *CondRHSConst = CondRHSBV->getConstantSplatNode())
22023 // If the RHS is a constant we have to reverse the const
22024 // canonicalization.
22025 // x > C-1 ? x+-C : 0 --> subus x, C
22026 if (CC == ISD::SETUGT && Other->getOpcode() == ISD::ADD &&
22027 CondRHSConst->getAPIntValue() ==
22028 (-OpRHSConst->getAPIntValue() - 1))
22029 return DAG.getNode(
22030 X86ISD::SUBUS, DL, VT, OpLHS,
22031 DAG.getConstant(-OpRHSConst->getAPIntValue(), DL, VT));
22033 // Another special case: If C was a sign bit, the sub has been
22034 // canonicalized into a xor.
22035 // FIXME: Would it be better to use computeKnownBits to determine
22036 // whether it's safe to decanonicalize the xor?
22037 // x s< 0 ? x^C : 0 --> subus x, C
22038 if (CC == ISD::SETLT && Other->getOpcode() == ISD::XOR &&
22039 ISD::isBuildVectorAllZeros(CondRHS.getNode()) &&
22040 OpRHSConst->getAPIntValue().isSignBit())
22041 // Note that we have to rebuild the RHS constant here to ensure we
22042 // don't rely on particular values of undef lanes.
22043 return DAG.getNode(
22044 X86ISD::SUBUS, DL, VT, OpLHS,
22045 DAG.getConstant(OpRHSConst->getAPIntValue(), DL, VT));
22050 // Try to match a min/max vector operation.
22051 if (N->getOpcode() == ISD::VSELECT && Cond.getOpcode() == ISD::SETCC) {
22052 std::pair<unsigned, bool> ret = matchIntegerMINMAX(Cond, VT, LHS, RHS, DAG, Subtarget);
22053 unsigned Opc = ret.first;
22054 bool NeedSplit = ret.second;
22056 if (Opc && NeedSplit) {
22057 unsigned NumElems = VT.getVectorNumElements();
22058 // Extract the LHS vectors
22059 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, DL);
22060 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, DL);
22062 // Extract the RHS vectors
22063 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, DL);
22064 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, DL);
22066 // Create min/max for each subvector
22067 LHS = DAG.getNode(Opc, DL, LHS1.getValueType(), LHS1, RHS1);
22068 RHS = DAG.getNode(Opc, DL, LHS2.getValueType(), LHS2, RHS2);
22070 // Merge the result
22071 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, LHS, RHS);
22073 return DAG.getNode(Opc, DL, VT, LHS, RHS);
22076 // Simplify vector selection if condition value type matches vselect
22078 if (N->getOpcode() == ISD::VSELECT && CondVT == VT) {
22079 assert(Cond.getValueType().isVector() &&
22080 "vector select expects a vector selector!");
22082 bool TValIsAllOnes = ISD::isBuildVectorAllOnes(LHS.getNode());
22083 bool FValIsAllZeros = ISD::isBuildVectorAllZeros(RHS.getNode());
22085 // Try invert the condition if true value is not all 1s and false value
22087 if (!TValIsAllOnes && !FValIsAllZeros &&
22088 // Check if the selector will be produced by CMPP*/PCMP*
22089 Cond.getOpcode() == ISD::SETCC &&
22090 // Check if SETCC has already been promoted
22091 TLI.getSetCCResultType(*DAG.getContext(), VT) == CondVT) {
22092 bool TValIsAllZeros = ISD::isBuildVectorAllZeros(LHS.getNode());
22093 bool FValIsAllOnes = ISD::isBuildVectorAllOnes(RHS.getNode());
22095 if (TValIsAllZeros || FValIsAllOnes) {
22096 SDValue CC = Cond.getOperand(2);
22097 ISD::CondCode NewCC =
22098 ISD::getSetCCInverse(cast<CondCodeSDNode>(CC)->get(),
22099 Cond.getOperand(0).getValueType().isInteger());
22100 Cond = DAG.getSetCC(DL, CondVT, Cond.getOperand(0), Cond.getOperand(1), NewCC);
22101 std::swap(LHS, RHS);
22102 TValIsAllOnes = FValIsAllOnes;
22103 FValIsAllZeros = TValIsAllZeros;
22107 if (TValIsAllOnes || FValIsAllZeros) {
22110 if (TValIsAllOnes && FValIsAllZeros)
22112 else if (TValIsAllOnes)
22114 DAG.getNode(ISD::OR, DL, CondVT, Cond, DAG.getBitcast(CondVT, RHS));
22115 else if (FValIsAllZeros)
22116 Ret = DAG.getNode(ISD::AND, DL, CondVT, Cond,
22117 DAG.getBitcast(CondVT, LHS));
22119 return DAG.getBitcast(VT, Ret);
22123 // We should generate an X86ISD::BLENDI from a vselect if its argument
22124 // is a sign_extend_inreg of an any_extend of a BUILD_VECTOR of
22125 // constants. This specific pattern gets generated when we split a
22126 // selector for a 512 bit vector in a machine without AVX512 (but with
22127 // 256-bit vectors), during legalization:
22129 // (vselect (sign_extend (any_extend (BUILD_VECTOR)) i1) LHS RHS)
22131 // Iff we find this pattern and the build_vectors are built from
22132 // constants, we translate the vselect into a shuffle_vector that we
22133 // know will be matched by LowerVECTOR_SHUFFLEtoBlend.
22134 if ((N->getOpcode() == ISD::VSELECT ||
22135 N->getOpcode() == X86ISD::SHRUNKBLEND) &&
22136 !DCI.isBeforeLegalize() && !VT.is512BitVector()) {
22137 SDValue Shuffle = transformVSELECTtoBlendVECTOR_SHUFFLE(N, DAG, Subtarget);
22138 if (Shuffle.getNode())
22142 // If this is a *dynamic* select (non-constant condition) and we can match
22143 // this node with one of the variable blend instructions, restructure the
22144 // condition so that the blends can use the high bit of each element and use
22145 // SimplifyDemandedBits to simplify the condition operand.
22146 if (N->getOpcode() == ISD::VSELECT && DCI.isBeforeLegalizeOps() &&
22147 !DCI.isBeforeLegalize() &&
22148 !ISD::isBuildVectorOfConstantSDNodes(Cond.getNode())) {
22149 unsigned BitWidth = Cond.getValueType().getScalarType().getSizeInBits();
22151 // Don't optimize vector selects that map to mask-registers.
22155 // We can only handle the cases where VSELECT is directly legal on the
22156 // subtarget. We custom lower VSELECT nodes with constant conditions and
22157 // this makes it hard to see whether a dynamic VSELECT will correctly
22158 // lower, so we both check the operation's status and explicitly handle the
22159 // cases where a *dynamic* blend will fail even though a constant-condition
22160 // blend could be custom lowered.
22161 // FIXME: We should find a better way to handle this class of problems.
22162 // Potentially, we should combine constant-condition vselect nodes
22163 // pre-legalization into shuffles and not mark as many types as custom
22165 if (!TLI.isOperationLegalOrCustom(ISD::VSELECT, VT))
22167 // FIXME: We don't support i16-element blends currently. We could and
22168 // should support them by making *all* the bits in the condition be set
22169 // rather than just the high bit and using an i8-element blend.
22170 if (VT.getScalarType() == MVT::i16)
22172 // Dynamic blending was only available from SSE4.1 onward.
22173 if (VT.getSizeInBits() == 128 && !Subtarget->hasSSE41())
22175 // Byte blends are only available in AVX2
22176 if (VT.getSizeInBits() == 256 && VT.getScalarType() == MVT::i8 &&
22177 !Subtarget->hasAVX2())
22180 assert(BitWidth >= 8 && BitWidth <= 64 && "Invalid mask size");
22181 APInt DemandedMask = APInt::getHighBitsSet(BitWidth, 1);
22183 APInt KnownZero, KnownOne;
22184 TargetLowering::TargetLoweringOpt TLO(DAG, DCI.isBeforeLegalize(),
22185 DCI.isBeforeLegalizeOps());
22186 if (TLO.ShrinkDemandedConstant(Cond, DemandedMask) ||
22187 TLI.SimplifyDemandedBits(Cond, DemandedMask, KnownZero, KnownOne,
22189 // If we changed the computation somewhere in the DAG, this change
22190 // will affect all users of Cond.
22191 // Make sure it is fine and update all the nodes so that we do not
22192 // use the generic VSELECT anymore. Otherwise, we may perform
22193 // wrong optimizations as we messed up with the actual expectation
22194 // for the vector boolean values.
22195 if (Cond != TLO.Old) {
22196 // Check all uses of that condition operand to check whether it will be
22197 // consumed by non-BLEND instructions, which may depend on all bits are
22199 for (SDNode::use_iterator I = Cond->use_begin(), E = Cond->use_end();
22201 if (I->getOpcode() != ISD::VSELECT)
22202 // TODO: Add other opcodes eventually lowered into BLEND.
22205 // Update all the users of the condition, before committing the change,
22206 // so that the VSELECT optimizations that expect the correct vector
22207 // boolean value will not be triggered.
22208 for (SDNode::use_iterator I = Cond->use_begin(), E = Cond->use_end();
22210 DAG.ReplaceAllUsesOfValueWith(
22212 DAG.getNode(X86ISD::SHRUNKBLEND, SDLoc(*I), I->getValueType(0),
22213 Cond, I->getOperand(1), I->getOperand(2)));
22214 DCI.CommitTargetLoweringOpt(TLO);
22217 // At this point, only Cond is changed. Change the condition
22218 // just for N to keep the opportunity to optimize all other
22219 // users their own way.
22220 DAG.ReplaceAllUsesOfValueWith(
22222 DAG.getNode(X86ISD::SHRUNKBLEND, SDLoc(N), N->getValueType(0),
22223 TLO.New, N->getOperand(1), N->getOperand(2)));
22231 // Check whether a boolean test is testing a boolean value generated by
22232 // X86ISD::SETCC. If so, return the operand of that SETCC and proper condition
22235 // Simplify the following patterns:
22236 // (Op (CMP (SETCC Cond EFLAGS) 1) EQ) or
22237 // (Op (CMP (SETCC Cond EFLAGS) 0) NEQ)
22238 // to (Op EFLAGS Cond)
22240 // (Op (CMP (SETCC Cond EFLAGS) 0) EQ) or
22241 // (Op (CMP (SETCC Cond EFLAGS) 1) NEQ)
22242 // to (Op EFLAGS !Cond)
22244 // where Op could be BRCOND or CMOV.
22246 static SDValue checkBoolTestSetCCCombine(SDValue Cmp, X86::CondCode &CC) {
22247 // Quit if not CMP and SUB with its value result used.
22248 if (Cmp.getOpcode() != X86ISD::CMP &&
22249 (Cmp.getOpcode() != X86ISD::SUB || Cmp.getNode()->hasAnyUseOfValue(0)))
22252 // Quit if not used as a boolean value.
22253 if (CC != X86::COND_E && CC != X86::COND_NE)
22256 // Check CMP operands. One of them should be 0 or 1 and the other should be
22257 // an SetCC or extended from it.
22258 SDValue Op1 = Cmp.getOperand(0);
22259 SDValue Op2 = Cmp.getOperand(1);
22262 const ConstantSDNode* C = nullptr;
22263 bool needOppositeCond = (CC == X86::COND_E);
22264 bool checkAgainstTrue = false; // Is it a comparison against 1?
22266 if ((C = dyn_cast<ConstantSDNode>(Op1)))
22268 else if ((C = dyn_cast<ConstantSDNode>(Op2)))
22270 else // Quit if all operands are not constants.
22273 if (C->getZExtValue() == 1) {
22274 needOppositeCond = !needOppositeCond;
22275 checkAgainstTrue = true;
22276 } else if (C->getZExtValue() != 0)
22277 // Quit if the constant is neither 0 or 1.
22280 bool truncatedToBoolWithAnd = false;
22281 // Skip (zext $x), (trunc $x), or (and $x, 1) node.
22282 while (SetCC.getOpcode() == ISD::ZERO_EXTEND ||
22283 SetCC.getOpcode() == ISD::TRUNCATE ||
22284 SetCC.getOpcode() == ISD::AND) {
22285 if (SetCC.getOpcode() == ISD::AND) {
22287 ConstantSDNode *CS;
22288 if ((CS = dyn_cast<ConstantSDNode>(SetCC.getOperand(0))) &&
22289 CS->getZExtValue() == 1)
22291 if ((CS = dyn_cast<ConstantSDNode>(SetCC.getOperand(1))) &&
22292 CS->getZExtValue() == 1)
22296 SetCC = SetCC.getOperand(OpIdx);
22297 truncatedToBoolWithAnd = true;
22299 SetCC = SetCC.getOperand(0);
22302 switch (SetCC.getOpcode()) {
22303 case X86ISD::SETCC_CARRY:
22304 // Since SETCC_CARRY gives output based on R = CF ? ~0 : 0, it's unsafe to
22305 // simplify it if the result of SETCC_CARRY is not canonicalized to 0 or 1,
22306 // i.e. it's a comparison against true but the result of SETCC_CARRY is not
22307 // truncated to i1 using 'and'.
22308 if (checkAgainstTrue && !truncatedToBoolWithAnd)
22310 assert(X86::CondCode(SetCC.getConstantOperandVal(0)) == X86::COND_B &&
22311 "Invalid use of SETCC_CARRY!");
22313 case X86ISD::SETCC:
22314 // Set the condition code or opposite one if necessary.
22315 CC = X86::CondCode(SetCC.getConstantOperandVal(0));
22316 if (needOppositeCond)
22317 CC = X86::GetOppositeBranchCondition(CC);
22318 return SetCC.getOperand(1);
22319 case X86ISD::CMOV: {
22320 // Check whether false/true value has canonical one, i.e. 0 or 1.
22321 ConstantSDNode *FVal = dyn_cast<ConstantSDNode>(SetCC.getOperand(0));
22322 ConstantSDNode *TVal = dyn_cast<ConstantSDNode>(SetCC.getOperand(1));
22323 // Quit if true value is not a constant.
22326 // Quit if false value is not a constant.
22328 SDValue Op = SetCC.getOperand(0);
22329 // Skip 'zext' or 'trunc' node.
22330 if (Op.getOpcode() == ISD::ZERO_EXTEND ||
22331 Op.getOpcode() == ISD::TRUNCATE)
22332 Op = Op.getOperand(0);
22333 // A special case for rdrand/rdseed, where 0 is set if false cond is
22335 if ((Op.getOpcode() != X86ISD::RDRAND &&
22336 Op.getOpcode() != X86ISD::RDSEED) || Op.getResNo() != 0)
22339 // Quit if false value is not the constant 0 or 1.
22340 bool FValIsFalse = true;
22341 if (FVal && FVal->getZExtValue() != 0) {
22342 if (FVal->getZExtValue() != 1)
22344 // If FVal is 1, opposite cond is needed.
22345 needOppositeCond = !needOppositeCond;
22346 FValIsFalse = false;
22348 // Quit if TVal is not the constant opposite of FVal.
22349 if (FValIsFalse && TVal->getZExtValue() != 1)
22351 if (!FValIsFalse && TVal->getZExtValue() != 0)
22353 CC = X86::CondCode(SetCC.getConstantOperandVal(2));
22354 if (needOppositeCond)
22355 CC = X86::GetOppositeBranchCondition(CC);
22356 return SetCC.getOperand(3);
22363 /// Check whether Cond is an AND/OR of SETCCs off of the same EFLAGS.
22365 /// (X86or (X86setcc) (X86setcc))
22366 /// (X86cmp (and (X86setcc) (X86setcc)), 0)
22367 static bool checkBoolTestAndOrSetCCCombine(SDValue Cond, X86::CondCode &CC0,
22368 X86::CondCode &CC1, SDValue &Flags,
22370 if (Cond->getOpcode() == X86ISD::CMP) {
22371 ConstantSDNode *CondOp1C = dyn_cast<ConstantSDNode>(Cond->getOperand(1));
22372 if (!CondOp1C || !CondOp1C->isNullValue())
22375 Cond = Cond->getOperand(0);
22380 SDValue SetCC0, SetCC1;
22381 switch (Cond->getOpcode()) {
22382 default: return false;
22389 SetCC0 = Cond->getOperand(0);
22390 SetCC1 = Cond->getOperand(1);
22394 // Make sure we have SETCC nodes, using the same flags value.
22395 if (SetCC0.getOpcode() != X86ISD::SETCC ||
22396 SetCC1.getOpcode() != X86ISD::SETCC ||
22397 SetCC0->getOperand(1) != SetCC1->getOperand(1))
22400 CC0 = (X86::CondCode)SetCC0->getConstantOperandVal(0);
22401 CC1 = (X86::CondCode)SetCC1->getConstantOperandVal(0);
22402 Flags = SetCC0->getOperand(1);
22406 /// Optimize X86ISD::CMOV [LHS, RHS, CONDCODE (e.g. X86::COND_NE), CONDVAL]
22407 static SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG,
22408 TargetLowering::DAGCombinerInfo &DCI,
22409 const X86Subtarget *Subtarget) {
22412 // If the flag operand isn't dead, don't touch this CMOV.
22413 if (N->getNumValues() == 2 && !SDValue(N, 1).use_empty())
22416 SDValue FalseOp = N->getOperand(0);
22417 SDValue TrueOp = N->getOperand(1);
22418 X86::CondCode CC = (X86::CondCode)N->getConstantOperandVal(2);
22419 SDValue Cond = N->getOperand(3);
22421 if (CC == X86::COND_E || CC == X86::COND_NE) {
22422 switch (Cond.getOpcode()) {
22426 // If operand of BSR / BSF are proven never zero, then ZF cannot be set.
22427 if (DAG.isKnownNeverZero(Cond.getOperand(0)))
22428 return (CC == X86::COND_E) ? FalseOp : TrueOp;
22434 Flags = checkBoolTestSetCCCombine(Cond, CC);
22435 if (Flags.getNode() &&
22436 // Extra check as FCMOV only supports a subset of X86 cond.
22437 (FalseOp.getValueType() != MVT::f80 || hasFPCMov(CC))) {
22438 SDValue Ops[] = { FalseOp, TrueOp,
22439 DAG.getConstant(CC, DL, MVT::i8), Flags };
22440 return DAG.getNode(X86ISD::CMOV, DL, N->getVTList(), Ops);
22443 // If this is a select between two integer constants, try to do some
22444 // optimizations. Note that the operands are ordered the opposite of SELECT
22446 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(TrueOp)) {
22447 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(FalseOp)) {
22448 // Canonicalize the TrueC/FalseC values so that TrueC (the true value) is
22449 // larger than FalseC (the false value).
22450 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue())) {
22451 CC = X86::GetOppositeBranchCondition(CC);
22452 std::swap(TrueC, FalseC);
22453 std::swap(TrueOp, FalseOp);
22456 // Optimize C ? 8 : 0 -> zext(setcc(C)) << 3. Likewise for any pow2/0.
22457 // This is efficient for any integer data type (including i8/i16) and
22459 if (FalseC->getAPIntValue() == 0 && TrueC->getAPIntValue().isPowerOf2()) {
22460 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
22461 DAG.getConstant(CC, DL, MVT::i8), Cond);
22463 // Zero extend the condition if needed.
22464 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, TrueC->getValueType(0), Cond);
22466 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
22467 Cond = DAG.getNode(ISD::SHL, DL, Cond.getValueType(), Cond,
22468 DAG.getConstant(ShAmt, DL, MVT::i8));
22469 if (N->getNumValues() == 2) // Dead flag value?
22470 return DCI.CombineTo(N, Cond, SDValue());
22474 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst. This is efficient
22475 // for any integer data type, including i8/i16.
22476 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
22477 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
22478 DAG.getConstant(CC, DL, MVT::i8), Cond);
22480 // Zero extend the condition if needed.
22481 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
22482 FalseC->getValueType(0), Cond);
22483 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
22484 SDValue(FalseC, 0));
22486 if (N->getNumValues() == 2) // Dead flag value?
22487 return DCI.CombineTo(N, Cond, SDValue());
22491 // Optimize cases that will turn into an LEA instruction. This requires
22492 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
22493 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
22494 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
22495 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
22497 bool isFastMultiplier = false;
22499 switch ((unsigned char)Diff) {
22501 case 1: // result = add base, cond
22502 case 2: // result = lea base( , cond*2)
22503 case 3: // result = lea base(cond, cond*2)
22504 case 4: // result = lea base( , cond*4)
22505 case 5: // result = lea base(cond, cond*4)
22506 case 8: // result = lea base( , cond*8)
22507 case 9: // result = lea base(cond, cond*8)
22508 isFastMultiplier = true;
22513 if (isFastMultiplier) {
22514 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
22515 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
22516 DAG.getConstant(CC, DL, MVT::i8), Cond);
22517 // Zero extend the condition if needed.
22518 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
22520 // Scale the condition by the difference.
22522 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
22523 DAG.getConstant(Diff, DL, Cond.getValueType()));
22525 // Add the base if non-zero.
22526 if (FalseC->getAPIntValue() != 0)
22527 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
22528 SDValue(FalseC, 0));
22529 if (N->getNumValues() == 2) // Dead flag value?
22530 return DCI.CombineTo(N, Cond, SDValue());
22537 // Handle these cases:
22538 // (select (x != c), e, c) -> select (x != c), e, x),
22539 // (select (x == c), c, e) -> select (x == c), x, e)
22540 // where the c is an integer constant, and the "select" is the combination
22541 // of CMOV and CMP.
22543 // The rationale for this change is that the conditional-move from a constant
22544 // needs two instructions, however, conditional-move from a register needs
22545 // only one instruction.
22547 // CAVEAT: By replacing a constant with a symbolic value, it may obscure
22548 // some instruction-combining opportunities. This opt needs to be
22549 // postponed as late as possible.
22551 if (!DCI.isBeforeLegalize() && !DCI.isBeforeLegalizeOps()) {
22552 // the DCI.xxxx conditions are provided to postpone the optimization as
22553 // late as possible.
22555 ConstantSDNode *CmpAgainst = nullptr;
22556 if ((Cond.getOpcode() == X86ISD::CMP || Cond.getOpcode() == X86ISD::SUB) &&
22557 (CmpAgainst = dyn_cast<ConstantSDNode>(Cond.getOperand(1))) &&
22558 !isa<ConstantSDNode>(Cond.getOperand(0))) {
22560 if (CC == X86::COND_NE &&
22561 CmpAgainst == dyn_cast<ConstantSDNode>(FalseOp)) {
22562 CC = X86::GetOppositeBranchCondition(CC);
22563 std::swap(TrueOp, FalseOp);
22566 if (CC == X86::COND_E &&
22567 CmpAgainst == dyn_cast<ConstantSDNode>(TrueOp)) {
22568 SDValue Ops[] = { FalseOp, Cond.getOperand(0),
22569 DAG.getConstant(CC, DL, MVT::i8), Cond };
22570 return DAG.getNode(X86ISD::CMOV, DL, N->getVTList (), Ops);
22575 // Fold and/or of setcc's to double CMOV:
22576 // (CMOV F, T, ((cc1 | cc2) != 0)) -> (CMOV (CMOV F, T, cc1), T, cc2)
22577 // (CMOV F, T, ((cc1 & cc2) != 0)) -> (CMOV (CMOV T, F, !cc1), F, !cc2)
22579 // This combine lets us generate:
22580 // cmovcc1 (jcc1 if we don't have CMOV)
22586 // cmovne (jne if we don't have CMOV)
22587 // When we can't use the CMOV instruction, it might increase branch
22589 // When we can use CMOV, or when there is no mispredict, this improves
22590 // throughput and reduces register pressure.
22592 if (CC == X86::COND_NE) {
22594 X86::CondCode CC0, CC1;
22596 if (checkBoolTestAndOrSetCCCombine(Cond, CC0, CC1, Flags, isAndSetCC)) {
22598 std::swap(FalseOp, TrueOp);
22599 CC0 = X86::GetOppositeBranchCondition(CC0);
22600 CC1 = X86::GetOppositeBranchCondition(CC1);
22603 SDValue LOps[] = {FalseOp, TrueOp, DAG.getConstant(CC0, DL, MVT::i8),
22605 SDValue LCMOV = DAG.getNode(X86ISD::CMOV, DL, N->getVTList(), LOps);
22606 SDValue Ops[] = {LCMOV, TrueOp, DAG.getConstant(CC1, DL, MVT::i8), Flags};
22607 SDValue CMOV = DAG.getNode(X86ISD::CMOV, DL, N->getVTList(), Ops);
22608 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), SDValue(CMOV.getNode(), 1));
22616 static SDValue PerformINTRINSIC_WO_CHAINCombine(SDNode *N, SelectionDAG &DAG,
22617 const X86Subtarget *Subtarget) {
22618 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(0))->getZExtValue();
22620 default: return SDValue();
22621 // SSE/AVX/AVX2 blend intrinsics.
22622 case Intrinsic::x86_avx2_pblendvb:
22623 // Don't try to simplify this intrinsic if we don't have AVX2.
22624 if (!Subtarget->hasAVX2())
22627 case Intrinsic::x86_avx_blendv_pd_256:
22628 case Intrinsic::x86_avx_blendv_ps_256:
22629 // Don't try to simplify this intrinsic if we don't have AVX.
22630 if (!Subtarget->hasAVX())
22633 case Intrinsic::x86_sse41_blendvps:
22634 case Intrinsic::x86_sse41_blendvpd:
22635 case Intrinsic::x86_sse41_pblendvb: {
22636 SDValue Op0 = N->getOperand(1);
22637 SDValue Op1 = N->getOperand(2);
22638 SDValue Mask = N->getOperand(3);
22640 // Don't try to simplify this intrinsic if we don't have SSE4.1.
22641 if (!Subtarget->hasSSE41())
22644 // fold (blend A, A, Mask) -> A
22647 // fold (blend A, B, allZeros) -> A
22648 if (ISD::isBuildVectorAllZeros(Mask.getNode()))
22650 // fold (blend A, B, allOnes) -> B
22651 if (ISD::isBuildVectorAllOnes(Mask.getNode()))
22654 // Simplify the case where the mask is a constant i32 value.
22655 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Mask)) {
22656 if (C->isNullValue())
22658 if (C->isAllOnesValue())
22665 // Packed SSE2/AVX2 arithmetic shift immediate intrinsics.
22666 case Intrinsic::x86_sse2_psrai_w:
22667 case Intrinsic::x86_sse2_psrai_d:
22668 case Intrinsic::x86_avx2_psrai_w:
22669 case Intrinsic::x86_avx2_psrai_d:
22670 case Intrinsic::x86_sse2_psra_w:
22671 case Intrinsic::x86_sse2_psra_d:
22672 case Intrinsic::x86_avx2_psra_w:
22673 case Intrinsic::x86_avx2_psra_d: {
22674 SDValue Op0 = N->getOperand(1);
22675 SDValue Op1 = N->getOperand(2);
22676 EVT VT = Op0.getValueType();
22677 assert(VT.isVector() && "Expected a vector type!");
22679 if (isa<BuildVectorSDNode>(Op1))
22680 Op1 = Op1.getOperand(0);
22682 if (!isa<ConstantSDNode>(Op1))
22685 EVT SVT = VT.getVectorElementType();
22686 unsigned SVTBits = SVT.getSizeInBits();
22688 ConstantSDNode *CND = cast<ConstantSDNode>(Op1);
22689 const APInt &C = APInt(SVTBits, CND->getAPIntValue().getZExtValue());
22690 uint64_t ShAmt = C.getZExtValue();
22692 // Don't try to convert this shift into a ISD::SRA if the shift
22693 // count is bigger than or equal to the element size.
22694 if (ShAmt >= SVTBits)
22697 // Trivial case: if the shift count is zero, then fold this
22698 // into the first operand.
22702 // Replace this packed shift intrinsic with a target independent
22705 SDValue Splat = DAG.getConstant(C, DL, VT);
22706 return DAG.getNode(ISD::SRA, DL, VT, Op0, Splat);
22711 /// PerformMulCombine - Optimize a single multiply with constant into two
22712 /// in order to implement it with two cheaper instructions, e.g.
22713 /// LEA + SHL, LEA + LEA.
22714 static SDValue PerformMulCombine(SDNode *N, SelectionDAG &DAG,
22715 TargetLowering::DAGCombinerInfo &DCI) {
22716 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer())
22719 EVT VT = N->getValueType(0);
22720 if (VT != MVT::i64 && VT != MVT::i32)
22723 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
22726 uint64_t MulAmt = C->getZExtValue();
22727 if (isPowerOf2_64(MulAmt) || MulAmt == 3 || MulAmt == 5 || MulAmt == 9)
22730 uint64_t MulAmt1 = 0;
22731 uint64_t MulAmt2 = 0;
22732 if ((MulAmt % 9) == 0) {
22734 MulAmt2 = MulAmt / 9;
22735 } else if ((MulAmt % 5) == 0) {
22737 MulAmt2 = MulAmt / 5;
22738 } else if ((MulAmt % 3) == 0) {
22740 MulAmt2 = MulAmt / 3;
22743 (isPowerOf2_64(MulAmt2) || MulAmt2 == 3 || MulAmt2 == 5 || MulAmt2 == 9)){
22746 if (isPowerOf2_64(MulAmt2) &&
22747 !(N->hasOneUse() && N->use_begin()->getOpcode() == ISD::ADD))
22748 // If second multiplifer is pow2, issue it first. We want the multiply by
22749 // 3, 5, or 9 to be folded into the addressing mode unless the lone use
22751 std::swap(MulAmt1, MulAmt2);
22754 if (isPowerOf2_64(MulAmt1))
22755 NewMul = DAG.getNode(ISD::SHL, DL, VT, N->getOperand(0),
22756 DAG.getConstant(Log2_64(MulAmt1), DL, MVT::i8));
22758 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, N->getOperand(0),
22759 DAG.getConstant(MulAmt1, DL, VT));
22761 if (isPowerOf2_64(MulAmt2))
22762 NewMul = DAG.getNode(ISD::SHL, DL, VT, NewMul,
22763 DAG.getConstant(Log2_64(MulAmt2), DL, MVT::i8));
22765 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, NewMul,
22766 DAG.getConstant(MulAmt2, DL, VT));
22768 // Do not add new nodes to DAG combiner worklist.
22769 DCI.CombineTo(N, NewMul, false);
22774 static SDValue PerformSHLCombine(SDNode *N, SelectionDAG &DAG) {
22775 SDValue N0 = N->getOperand(0);
22776 SDValue N1 = N->getOperand(1);
22777 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
22778 EVT VT = N0.getValueType();
22780 // fold (shl (and (setcc_c), c1), c2) -> (and setcc_c, (c1 << c2))
22781 // since the result of setcc_c is all zero's or all ones.
22782 if (VT.isInteger() && !VT.isVector() &&
22783 N1C && N0.getOpcode() == ISD::AND &&
22784 N0.getOperand(1).getOpcode() == ISD::Constant) {
22785 SDValue N00 = N0.getOperand(0);
22786 if (N00.getOpcode() == X86ISD::SETCC_CARRY ||
22787 ((N00.getOpcode() == ISD::ANY_EXTEND ||
22788 N00.getOpcode() == ISD::ZERO_EXTEND) &&
22789 N00.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY)) {
22790 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
22791 APInt ShAmt = N1C->getAPIntValue();
22792 Mask = Mask.shl(ShAmt);
22795 return DAG.getNode(ISD::AND, DL, VT,
22796 N00, DAG.getConstant(Mask, DL, VT));
22801 // Hardware support for vector shifts is sparse which makes us scalarize the
22802 // vector operations in many cases. Also, on sandybridge ADD is faster than
22804 // (shl V, 1) -> add V,V
22805 if (auto *N1BV = dyn_cast<BuildVectorSDNode>(N1))
22806 if (auto *N1SplatC = N1BV->getConstantSplatNode()) {
22807 assert(N0.getValueType().isVector() && "Invalid vector shift type");
22808 // We shift all of the values by one. In many cases we do not have
22809 // hardware support for this operation. This is better expressed as an ADD
22811 if (N1SplatC->getZExtValue() == 1)
22812 return DAG.getNode(ISD::ADD, SDLoc(N), VT, N0, N0);
22818 /// \brief Returns a vector of 0s if the node in input is a vector logical
22819 /// shift by a constant amount which is known to be bigger than or equal
22820 /// to the vector element size in bits.
22821 static SDValue performShiftToAllZeros(SDNode *N, SelectionDAG &DAG,
22822 const X86Subtarget *Subtarget) {
22823 EVT VT = N->getValueType(0);
22825 if (VT != MVT::v2i64 && VT != MVT::v4i32 && VT != MVT::v8i16 &&
22826 (!Subtarget->hasInt256() ||
22827 (VT != MVT::v4i64 && VT != MVT::v8i32 && VT != MVT::v16i16)))
22830 SDValue Amt = N->getOperand(1);
22832 if (auto *AmtBV = dyn_cast<BuildVectorSDNode>(Amt))
22833 if (auto *AmtSplat = AmtBV->getConstantSplatNode()) {
22834 APInt ShiftAmt = AmtSplat->getAPIntValue();
22835 unsigned MaxAmount = VT.getVectorElementType().getSizeInBits();
22837 // SSE2/AVX2 logical shifts always return a vector of 0s
22838 // if the shift amount is bigger than or equal to
22839 // the element size. The constant shift amount will be
22840 // encoded as a 8-bit immediate.
22841 if (ShiftAmt.trunc(8).uge(MaxAmount))
22842 return getZeroVector(VT, Subtarget, DAG, DL);
22848 /// PerformShiftCombine - Combine shifts.
22849 static SDValue PerformShiftCombine(SDNode* N, SelectionDAG &DAG,
22850 TargetLowering::DAGCombinerInfo &DCI,
22851 const X86Subtarget *Subtarget) {
22852 if (N->getOpcode() == ISD::SHL) {
22853 SDValue V = PerformSHLCombine(N, DAG);
22854 if (V.getNode()) return V;
22857 if (N->getOpcode() != ISD::SRA) {
22858 // Try to fold this logical shift into a zero vector.
22859 SDValue V = performShiftToAllZeros(N, DAG, Subtarget);
22860 if (V.getNode()) return V;
22866 // CMPEQCombine - Recognize the distinctive (AND (setcc ...) (setcc ..))
22867 // where both setccs reference the same FP CMP, and rewrite for CMPEQSS
22868 // and friends. Likewise for OR -> CMPNEQSS.
22869 static SDValue CMPEQCombine(SDNode *N, SelectionDAG &DAG,
22870 TargetLowering::DAGCombinerInfo &DCI,
22871 const X86Subtarget *Subtarget) {
22874 // SSE1 supports CMP{eq|ne}SS, and SSE2 added CMP{eq|ne}SD, but
22875 // we're requiring SSE2 for both.
22876 if (Subtarget->hasSSE2() && isAndOrOfSetCCs(SDValue(N, 0U), opcode)) {
22877 SDValue N0 = N->getOperand(0);
22878 SDValue N1 = N->getOperand(1);
22879 SDValue CMP0 = N0->getOperand(1);
22880 SDValue CMP1 = N1->getOperand(1);
22883 // The SETCCs should both refer to the same CMP.
22884 if (CMP0.getOpcode() != X86ISD::CMP || CMP0 != CMP1)
22887 SDValue CMP00 = CMP0->getOperand(0);
22888 SDValue CMP01 = CMP0->getOperand(1);
22889 EVT VT = CMP00.getValueType();
22891 if (VT == MVT::f32 || VT == MVT::f64) {
22892 bool ExpectingFlags = false;
22893 // Check for any users that want flags:
22894 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end();
22895 !ExpectingFlags && UI != UE; ++UI)
22896 switch (UI->getOpcode()) {
22901 ExpectingFlags = true;
22903 case ISD::CopyToReg:
22904 case ISD::SIGN_EXTEND:
22905 case ISD::ZERO_EXTEND:
22906 case ISD::ANY_EXTEND:
22910 if (!ExpectingFlags) {
22911 enum X86::CondCode cc0 = (enum X86::CondCode)N0.getConstantOperandVal(0);
22912 enum X86::CondCode cc1 = (enum X86::CondCode)N1.getConstantOperandVal(0);
22914 if (cc1 == X86::COND_E || cc1 == X86::COND_NE) {
22915 X86::CondCode tmp = cc0;
22920 if ((cc0 == X86::COND_E && cc1 == X86::COND_NP) ||
22921 (cc0 == X86::COND_NE && cc1 == X86::COND_P)) {
22922 // FIXME: need symbolic constants for these magic numbers.
22923 // See X86ATTInstPrinter.cpp:printSSECC().
22924 unsigned x86cc = (cc0 == X86::COND_E) ? 0 : 4;
22925 if (Subtarget->hasAVX512()) {
22926 SDValue FSetCC = DAG.getNode(X86ISD::FSETCC, DL, MVT::i1, CMP00,
22928 DAG.getConstant(x86cc, DL, MVT::i8));
22929 if (N->getValueType(0) != MVT::i1)
22930 return DAG.getNode(ISD::ZERO_EXTEND, DL, N->getValueType(0),
22934 SDValue OnesOrZeroesF = DAG.getNode(X86ISD::FSETCC, DL,
22935 CMP00.getValueType(), CMP00, CMP01,
22936 DAG.getConstant(x86cc, DL,
22939 bool is64BitFP = (CMP00.getValueType() == MVT::f64);
22940 MVT IntVT = is64BitFP ? MVT::i64 : MVT::i32;
22942 if (is64BitFP && !Subtarget->is64Bit()) {
22943 // On a 32-bit target, we cannot bitcast the 64-bit float to a
22944 // 64-bit integer, since that's not a legal type. Since
22945 // OnesOrZeroesF is all ones of all zeroes, we don't need all the
22946 // bits, but can do this little dance to extract the lowest 32 bits
22947 // and work with those going forward.
22948 SDValue Vector64 = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, MVT::v2f64,
22950 SDValue Vector32 = DAG.getBitcast(MVT::v4f32, Vector64);
22951 OnesOrZeroesF = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32,
22952 Vector32, DAG.getIntPtrConstant(0, DL));
22956 SDValue OnesOrZeroesI = DAG.getBitcast(IntVT, OnesOrZeroesF);
22957 SDValue ANDed = DAG.getNode(ISD::AND, DL, IntVT, OnesOrZeroesI,
22958 DAG.getConstant(1, DL, IntVT));
22959 SDValue OneBitOfTruth = DAG.getNode(ISD::TRUNCATE, DL, MVT::i8,
22961 return OneBitOfTruth;
22969 /// CanFoldXORWithAllOnes - Test whether the XOR operand is a AllOnes vector
22970 /// so it can be folded inside ANDNP.
22971 static bool CanFoldXORWithAllOnes(const SDNode *N) {
22972 EVT VT = N->getValueType(0);
22974 // Match direct AllOnes for 128 and 256-bit vectors
22975 if (ISD::isBuildVectorAllOnes(N))
22978 // Look through a bit convert.
22979 if (N->getOpcode() == ISD::BITCAST)
22980 N = N->getOperand(0).getNode();
22982 // Sometimes the operand may come from a insert_subvector building a 256-bit
22984 if (VT.is256BitVector() &&
22985 N->getOpcode() == ISD::INSERT_SUBVECTOR) {
22986 SDValue V1 = N->getOperand(0);
22987 SDValue V2 = N->getOperand(1);
22989 if (V1.getOpcode() == ISD::INSERT_SUBVECTOR &&
22990 V1.getOperand(0).getOpcode() == ISD::UNDEF &&
22991 ISD::isBuildVectorAllOnes(V1.getOperand(1).getNode()) &&
22992 ISD::isBuildVectorAllOnes(V2.getNode()))
22999 // On AVX/AVX2 the type v8i1 is legalized to v8i16, which is an XMM sized
23000 // register. In most cases we actually compare or select YMM-sized registers
23001 // and mixing the two types creates horrible code. This method optimizes
23002 // some of the transition sequences.
23003 static SDValue WidenMaskArithmetic(SDNode *N, SelectionDAG &DAG,
23004 TargetLowering::DAGCombinerInfo &DCI,
23005 const X86Subtarget *Subtarget) {
23006 EVT VT = N->getValueType(0);
23007 if (!VT.is256BitVector())
23010 assert((N->getOpcode() == ISD::ANY_EXTEND ||
23011 N->getOpcode() == ISD::ZERO_EXTEND ||
23012 N->getOpcode() == ISD::SIGN_EXTEND) && "Invalid Node");
23014 SDValue Narrow = N->getOperand(0);
23015 EVT NarrowVT = Narrow->getValueType(0);
23016 if (!NarrowVT.is128BitVector())
23019 if (Narrow->getOpcode() != ISD::XOR &&
23020 Narrow->getOpcode() != ISD::AND &&
23021 Narrow->getOpcode() != ISD::OR)
23024 SDValue N0 = Narrow->getOperand(0);
23025 SDValue N1 = Narrow->getOperand(1);
23028 // The Left side has to be a trunc.
23029 if (N0.getOpcode() != ISD::TRUNCATE)
23032 // The type of the truncated inputs.
23033 EVT WideVT = N0->getOperand(0)->getValueType(0);
23037 // The right side has to be a 'trunc' or a constant vector.
23038 bool RHSTrunc = N1.getOpcode() == ISD::TRUNCATE;
23039 ConstantSDNode *RHSConstSplat = nullptr;
23040 if (auto *RHSBV = dyn_cast<BuildVectorSDNode>(N1))
23041 RHSConstSplat = RHSBV->getConstantSplatNode();
23042 if (!RHSTrunc && !RHSConstSplat)
23045 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
23047 if (!TLI.isOperationLegalOrPromote(Narrow->getOpcode(), WideVT))
23050 // Set N0 and N1 to hold the inputs to the new wide operation.
23051 N0 = N0->getOperand(0);
23052 if (RHSConstSplat) {
23053 N1 = DAG.getNode(ISD::ZERO_EXTEND, DL, WideVT.getScalarType(),
23054 SDValue(RHSConstSplat, 0));
23055 SmallVector<SDValue, 8> C(WideVT.getVectorNumElements(), N1);
23056 N1 = DAG.getNode(ISD::BUILD_VECTOR, DL, WideVT, C);
23057 } else if (RHSTrunc) {
23058 N1 = N1->getOperand(0);
23061 // Generate the wide operation.
23062 SDValue Op = DAG.getNode(Narrow->getOpcode(), DL, WideVT, N0, N1);
23063 unsigned Opcode = N->getOpcode();
23065 case ISD::ANY_EXTEND:
23067 case ISD::ZERO_EXTEND: {
23068 unsigned InBits = NarrowVT.getScalarType().getSizeInBits();
23069 APInt Mask = APInt::getAllOnesValue(InBits);
23070 Mask = Mask.zext(VT.getScalarType().getSizeInBits());
23071 return DAG.getNode(ISD::AND, DL, VT,
23072 Op, DAG.getConstant(Mask, DL, VT));
23074 case ISD::SIGN_EXTEND:
23075 return DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, VT,
23076 Op, DAG.getValueType(NarrowVT));
23078 llvm_unreachable("Unexpected opcode");
23082 static SDValue VectorZextCombine(SDNode *N, SelectionDAG &DAG,
23083 TargetLowering::DAGCombinerInfo &DCI,
23084 const X86Subtarget *Subtarget) {
23085 SDValue N0 = N->getOperand(0);
23086 SDValue N1 = N->getOperand(1);
23089 // A vector zext_in_reg may be represented as a shuffle,
23090 // feeding into a bitcast (this represents anyext) feeding into
23091 // an and with a mask.
23092 // We'd like to try to combine that into a shuffle with zero
23093 // plus a bitcast, removing the and.
23094 if (N0.getOpcode() != ISD::BITCAST ||
23095 N0.getOperand(0).getOpcode() != ISD::VECTOR_SHUFFLE)
23098 // The other side of the AND should be a splat of 2^C, where C
23099 // is the number of bits in the source type.
23100 if (N1.getOpcode() == ISD::BITCAST)
23101 N1 = N1.getOperand(0);
23102 if (N1.getOpcode() != ISD::BUILD_VECTOR)
23104 BuildVectorSDNode *Vector = cast<BuildVectorSDNode>(N1);
23106 ShuffleVectorSDNode *Shuffle = cast<ShuffleVectorSDNode>(N0.getOperand(0));
23107 EVT SrcType = Shuffle->getValueType(0);
23109 // We expect a single-source shuffle
23110 if (Shuffle->getOperand(1)->getOpcode() != ISD::UNDEF)
23113 unsigned SrcSize = SrcType.getScalarSizeInBits();
23115 APInt SplatValue, SplatUndef;
23116 unsigned SplatBitSize;
23118 if (!Vector->isConstantSplat(SplatValue, SplatUndef,
23119 SplatBitSize, HasAnyUndefs))
23122 unsigned ResSize = N1.getValueType().getScalarSizeInBits();
23123 // Make sure the splat matches the mask we expect
23124 if (SplatBitSize > ResSize ||
23125 (SplatValue + 1).exactLogBase2() != (int)SrcSize)
23128 // Make sure the input and output size make sense
23129 if (SrcSize >= ResSize || ResSize % SrcSize)
23132 // We expect a shuffle of the form <0, u, u, u, 1, u, u, u...>
23133 // The number of u's between each two values depends on the ratio between
23134 // the source and dest type.
23135 unsigned ZextRatio = ResSize / SrcSize;
23136 bool IsZext = true;
23137 for (unsigned i = 0; i < SrcType.getVectorNumElements(); ++i) {
23138 if (i % ZextRatio) {
23139 if (Shuffle->getMaskElt(i) > 0) {
23145 if (Shuffle->getMaskElt(i) != (int)(i / ZextRatio)) {
23146 // Expected element number
23156 // Ok, perform the transformation - replace the shuffle with
23157 // a shuffle of the form <0, k, k, k, 1, k, k, k> with zero
23158 // (instead of undef) where the k elements come from the zero vector.
23159 SmallVector<int, 8> Mask;
23160 unsigned NumElems = SrcType.getVectorNumElements();
23161 for (unsigned i = 0; i < NumElems; ++i)
23163 Mask.push_back(NumElems);
23165 Mask.push_back(i / ZextRatio);
23167 SDValue NewShuffle = DAG.getVectorShuffle(Shuffle->getValueType(0), DL,
23168 Shuffle->getOperand(0), DAG.getConstant(0, DL, SrcType), Mask);
23169 return DAG.getBitcast(N0.getValueType(), NewShuffle);
23172 static SDValue PerformAndCombine(SDNode *N, SelectionDAG &DAG,
23173 TargetLowering::DAGCombinerInfo &DCI,
23174 const X86Subtarget *Subtarget) {
23175 if (DCI.isBeforeLegalizeOps())
23178 if (SDValue Zext = VectorZextCombine(N, DAG, DCI, Subtarget))
23181 if (SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget))
23184 EVT VT = N->getValueType(0);
23185 SDValue N0 = N->getOperand(0);
23186 SDValue N1 = N->getOperand(1);
23189 // Create BEXTR instructions
23190 // BEXTR is ((X >> imm) & (2**size-1))
23191 if (VT == MVT::i32 || VT == MVT::i64) {
23192 // Check for BEXTR.
23193 if ((Subtarget->hasBMI() || Subtarget->hasTBM()) &&
23194 (N0.getOpcode() == ISD::SRA || N0.getOpcode() == ISD::SRL)) {
23195 ConstantSDNode *MaskNode = dyn_cast<ConstantSDNode>(N1);
23196 ConstantSDNode *ShiftNode = dyn_cast<ConstantSDNode>(N0.getOperand(1));
23197 if (MaskNode && ShiftNode) {
23198 uint64_t Mask = MaskNode->getZExtValue();
23199 uint64_t Shift = ShiftNode->getZExtValue();
23200 if (isMask_64(Mask)) {
23201 uint64_t MaskSize = countPopulation(Mask);
23202 if (Shift + MaskSize <= VT.getSizeInBits())
23203 return DAG.getNode(X86ISD::BEXTR, DL, VT, N0.getOperand(0),
23204 DAG.getConstant(Shift | (MaskSize << 8), DL,
23213 // Want to form ANDNP nodes:
23214 // 1) In the hopes of then easily combining them with OR and AND nodes
23215 // to form PBLEND/PSIGN.
23216 // 2) To match ANDN packed intrinsics
23217 if (VT != MVT::v2i64 && VT != MVT::v4i64)
23220 // Check LHS for vnot
23221 if (N0.getOpcode() == ISD::XOR &&
23222 //ISD::isBuildVectorAllOnes(N0.getOperand(1).getNode()))
23223 CanFoldXORWithAllOnes(N0.getOperand(1).getNode()))
23224 return DAG.getNode(X86ISD::ANDNP, DL, VT, N0.getOperand(0), N1);
23226 // Check RHS for vnot
23227 if (N1.getOpcode() == ISD::XOR &&
23228 //ISD::isBuildVectorAllOnes(N1.getOperand(1).getNode()))
23229 CanFoldXORWithAllOnes(N1.getOperand(1).getNode()))
23230 return DAG.getNode(X86ISD::ANDNP, DL, VT, N1.getOperand(0), N0);
23235 static SDValue PerformOrCombine(SDNode *N, SelectionDAG &DAG,
23236 TargetLowering::DAGCombinerInfo &DCI,
23237 const X86Subtarget *Subtarget) {
23238 if (DCI.isBeforeLegalizeOps())
23241 SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget);
23245 SDValue N0 = N->getOperand(0);
23246 SDValue N1 = N->getOperand(1);
23247 EVT VT = N->getValueType(0);
23249 // look for psign/blend
23250 if (VT == MVT::v2i64 || VT == MVT::v4i64) {
23251 if (!Subtarget->hasSSSE3() ||
23252 (VT == MVT::v4i64 && !Subtarget->hasInt256()))
23255 // Canonicalize pandn to RHS
23256 if (N0.getOpcode() == X86ISD::ANDNP)
23258 // or (and (m, y), (pandn m, x))
23259 if (N0.getOpcode() == ISD::AND && N1.getOpcode() == X86ISD::ANDNP) {
23260 SDValue Mask = N1.getOperand(0);
23261 SDValue X = N1.getOperand(1);
23263 if (N0.getOperand(0) == Mask)
23264 Y = N0.getOperand(1);
23265 if (N0.getOperand(1) == Mask)
23266 Y = N0.getOperand(0);
23268 // Check to see if the mask appeared in both the AND and ANDNP and
23272 // Validate that X, Y, and Mask are BIT_CONVERTS, and see through them.
23273 // Look through mask bitcast.
23274 if (Mask.getOpcode() == ISD::BITCAST)
23275 Mask = Mask.getOperand(0);
23276 if (X.getOpcode() == ISD::BITCAST)
23277 X = X.getOperand(0);
23278 if (Y.getOpcode() == ISD::BITCAST)
23279 Y = Y.getOperand(0);
23281 EVT MaskVT = Mask.getValueType();
23283 // Validate that the Mask operand is a vector sra node.
23284 // FIXME: what to do for bytes, since there is a psignb/pblendvb, but
23285 // there is no psrai.b
23286 unsigned EltBits = MaskVT.getVectorElementType().getSizeInBits();
23287 unsigned SraAmt = ~0;
23288 if (Mask.getOpcode() == ISD::SRA) {
23289 if (auto *AmtBV = dyn_cast<BuildVectorSDNode>(Mask.getOperand(1)))
23290 if (auto *AmtConst = AmtBV->getConstantSplatNode())
23291 SraAmt = AmtConst->getZExtValue();
23292 } else if (Mask.getOpcode() == X86ISD::VSRAI) {
23293 SDValue SraC = Mask.getOperand(1);
23294 SraAmt = cast<ConstantSDNode>(SraC)->getZExtValue();
23296 if ((SraAmt + 1) != EltBits)
23301 // Now we know we at least have a plendvb with the mask val. See if
23302 // we can form a psignb/w/d.
23303 // psign = x.type == y.type == mask.type && y = sub(0, x);
23304 if (Y.getOpcode() == ISD::SUB && Y.getOperand(1) == X &&
23305 ISD::isBuildVectorAllZeros(Y.getOperand(0).getNode()) &&
23306 X.getValueType() == MaskVT && Y.getValueType() == MaskVT) {
23307 assert((EltBits == 8 || EltBits == 16 || EltBits == 32) &&
23308 "Unsupported VT for PSIGN");
23309 Mask = DAG.getNode(X86ISD::PSIGN, DL, MaskVT, X, Mask.getOperand(0));
23310 return DAG.getBitcast(VT, Mask);
23312 // PBLENDVB only available on SSE 4.1
23313 if (!Subtarget->hasSSE41())
23316 EVT BlendVT = (VT == MVT::v4i64) ? MVT::v32i8 : MVT::v16i8;
23318 X = DAG.getBitcast(BlendVT, X);
23319 Y = DAG.getBitcast(BlendVT, Y);
23320 Mask = DAG.getBitcast(BlendVT, Mask);
23321 Mask = DAG.getNode(ISD::VSELECT, DL, BlendVT, Mask, Y, X);
23322 return DAG.getBitcast(VT, Mask);
23326 if (VT != MVT::i16 && VT != MVT::i32 && VT != MVT::i64)
23329 // fold (or (x << c) | (y >> (64 - c))) ==> (shld64 x, y, c)
23330 MachineFunction &MF = DAG.getMachineFunction();
23332 MF.getFunction()->hasFnAttribute(Attribute::OptimizeForSize);
23334 // SHLD/SHRD instructions have lower register pressure, but on some
23335 // platforms they have higher latency than the equivalent
23336 // series of shifts/or that would otherwise be generated.
23337 // Don't fold (or (x << c) | (y >> (64 - c))) if SHLD/SHRD instructions
23338 // have higher latencies and we are not optimizing for size.
23339 if (!OptForSize && Subtarget->isSHLDSlow())
23342 if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL)
23344 if (N0.getOpcode() != ISD::SHL || N1.getOpcode() != ISD::SRL)
23346 if (!N0.hasOneUse() || !N1.hasOneUse())
23349 SDValue ShAmt0 = N0.getOperand(1);
23350 if (ShAmt0.getValueType() != MVT::i8)
23352 SDValue ShAmt1 = N1.getOperand(1);
23353 if (ShAmt1.getValueType() != MVT::i8)
23355 if (ShAmt0.getOpcode() == ISD::TRUNCATE)
23356 ShAmt0 = ShAmt0.getOperand(0);
23357 if (ShAmt1.getOpcode() == ISD::TRUNCATE)
23358 ShAmt1 = ShAmt1.getOperand(0);
23361 unsigned Opc = X86ISD::SHLD;
23362 SDValue Op0 = N0.getOperand(0);
23363 SDValue Op1 = N1.getOperand(0);
23364 if (ShAmt0.getOpcode() == ISD::SUB) {
23365 Opc = X86ISD::SHRD;
23366 std::swap(Op0, Op1);
23367 std::swap(ShAmt0, ShAmt1);
23370 unsigned Bits = VT.getSizeInBits();
23371 if (ShAmt1.getOpcode() == ISD::SUB) {
23372 SDValue Sum = ShAmt1.getOperand(0);
23373 if (ConstantSDNode *SumC = dyn_cast<ConstantSDNode>(Sum)) {
23374 SDValue ShAmt1Op1 = ShAmt1.getOperand(1);
23375 if (ShAmt1Op1.getNode()->getOpcode() == ISD::TRUNCATE)
23376 ShAmt1Op1 = ShAmt1Op1.getOperand(0);
23377 if (SumC->getSExtValue() == Bits && ShAmt1Op1 == ShAmt0)
23378 return DAG.getNode(Opc, DL, VT,
23380 DAG.getNode(ISD::TRUNCATE, DL,
23383 } else if (ConstantSDNode *ShAmt1C = dyn_cast<ConstantSDNode>(ShAmt1)) {
23384 ConstantSDNode *ShAmt0C = dyn_cast<ConstantSDNode>(ShAmt0);
23386 ShAmt0C->getSExtValue() + ShAmt1C->getSExtValue() == Bits)
23387 return DAG.getNode(Opc, DL, VT,
23388 N0.getOperand(0), N1.getOperand(0),
23389 DAG.getNode(ISD::TRUNCATE, DL,
23396 // Generate NEG and CMOV for integer abs.
23397 static SDValue performIntegerAbsCombine(SDNode *N, SelectionDAG &DAG) {
23398 EVT VT = N->getValueType(0);
23400 // Since X86 does not have CMOV for 8-bit integer, we don't convert
23401 // 8-bit integer abs to NEG and CMOV.
23402 if (VT.isInteger() && VT.getSizeInBits() == 8)
23405 SDValue N0 = N->getOperand(0);
23406 SDValue N1 = N->getOperand(1);
23409 // Check pattern of XOR(ADD(X,Y), Y) where Y is SRA(X, size(X)-1)
23410 // and change it to SUB and CMOV.
23411 if (VT.isInteger() && N->getOpcode() == ISD::XOR &&
23412 N0.getOpcode() == ISD::ADD &&
23413 N0.getOperand(1) == N1 &&
23414 N1.getOpcode() == ISD::SRA &&
23415 N1.getOperand(0) == N0.getOperand(0))
23416 if (ConstantSDNode *Y1C = dyn_cast<ConstantSDNode>(N1.getOperand(1)))
23417 if (Y1C->getAPIntValue() == VT.getSizeInBits()-1) {
23418 // Generate SUB & CMOV.
23419 SDValue Neg = DAG.getNode(X86ISD::SUB, DL, DAG.getVTList(VT, MVT::i32),
23420 DAG.getConstant(0, DL, VT), N0.getOperand(0));
23422 SDValue Ops[] = { N0.getOperand(0), Neg,
23423 DAG.getConstant(X86::COND_GE, DL, MVT::i8),
23424 SDValue(Neg.getNode(), 1) };
23425 return DAG.getNode(X86ISD::CMOV, DL, DAG.getVTList(VT, MVT::Glue), Ops);
23430 // PerformXorCombine - Attempts to turn XOR nodes into BLSMSK nodes
23431 static SDValue PerformXorCombine(SDNode *N, SelectionDAG &DAG,
23432 TargetLowering::DAGCombinerInfo &DCI,
23433 const X86Subtarget *Subtarget) {
23434 if (DCI.isBeforeLegalizeOps())
23437 if (Subtarget->hasCMov()) {
23438 SDValue RV = performIntegerAbsCombine(N, DAG);
23446 /// PerformLOADCombine - Do target-specific dag combines on LOAD nodes.
23447 static SDValue PerformLOADCombine(SDNode *N, SelectionDAG &DAG,
23448 TargetLowering::DAGCombinerInfo &DCI,
23449 const X86Subtarget *Subtarget) {
23450 LoadSDNode *Ld = cast<LoadSDNode>(N);
23451 EVT RegVT = Ld->getValueType(0);
23452 EVT MemVT = Ld->getMemoryVT();
23454 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
23456 // For chips with slow 32-byte unaligned loads, break the 32-byte operation
23457 // into two 16-byte operations.
23458 ISD::LoadExtType Ext = Ld->getExtensionType();
23459 unsigned Alignment = Ld->getAlignment();
23460 bool IsAligned = Alignment == 0 || Alignment >= MemVT.getSizeInBits()/8;
23461 if (RegVT.is256BitVector() && Subtarget->isUnalignedMem32Slow() &&
23462 !DCI.isBeforeLegalizeOps() && !IsAligned && Ext == ISD::NON_EXTLOAD) {
23463 unsigned NumElems = RegVT.getVectorNumElements();
23467 SDValue Ptr = Ld->getBasePtr();
23468 SDValue Increment = DAG.getConstant(16, dl, TLI.getPointerTy());
23470 EVT HalfVT = EVT::getVectorVT(*DAG.getContext(), MemVT.getScalarType(),
23472 SDValue Load1 = DAG.getLoad(HalfVT, dl, Ld->getChain(), Ptr,
23473 Ld->getPointerInfo(), Ld->isVolatile(),
23474 Ld->isNonTemporal(), Ld->isInvariant(),
23476 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
23477 SDValue Load2 = DAG.getLoad(HalfVT, dl, Ld->getChain(), Ptr,
23478 Ld->getPointerInfo(), Ld->isVolatile(),
23479 Ld->isNonTemporal(), Ld->isInvariant(),
23480 std::min(16U, Alignment));
23481 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
23483 Load2.getValue(1));
23485 SDValue NewVec = DAG.getUNDEF(RegVT);
23486 NewVec = Insert128BitVector(NewVec, Load1, 0, DAG, dl);
23487 NewVec = Insert128BitVector(NewVec, Load2, NumElems/2, DAG, dl);
23488 return DCI.CombineTo(N, NewVec, TF, true);
23494 /// PerformMLOADCombine - Resolve extending loads
23495 static SDValue PerformMLOADCombine(SDNode *N, SelectionDAG &DAG,
23496 TargetLowering::DAGCombinerInfo &DCI,
23497 const X86Subtarget *Subtarget) {
23498 MaskedLoadSDNode *Mld = cast<MaskedLoadSDNode>(N);
23499 if (Mld->getExtensionType() != ISD::SEXTLOAD)
23502 EVT VT = Mld->getValueType(0);
23503 unsigned NumElems = VT.getVectorNumElements();
23504 EVT LdVT = Mld->getMemoryVT();
23507 assert(LdVT != VT && "Cannot extend to the same type");
23508 unsigned ToSz = VT.getVectorElementType().getSizeInBits();
23509 unsigned FromSz = LdVT.getVectorElementType().getSizeInBits();
23510 // From, To sizes and ElemCount must be pow of two
23511 assert (isPowerOf2_32(NumElems * FromSz * ToSz) &&
23512 "Unexpected size for extending masked load");
23514 unsigned SizeRatio = ToSz / FromSz;
23515 assert(SizeRatio * NumElems * FromSz == VT.getSizeInBits());
23517 // Create a type on which we perform the shuffle
23518 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(),
23519 LdVT.getScalarType(), NumElems*SizeRatio);
23520 assert(WideVecVT.getSizeInBits() == VT.getSizeInBits());
23522 // Convert Src0 value
23523 SDValue WideSrc0 = DAG.getBitcast(WideVecVT, Mld->getSrc0());
23524 if (Mld->getSrc0().getOpcode() != ISD::UNDEF) {
23525 SmallVector<int, 16> ShuffleVec(NumElems * SizeRatio, -1);
23526 for (unsigned i = 0; i != NumElems; ++i)
23527 ShuffleVec[i] = i * SizeRatio;
23529 // Can't shuffle using an illegal type.
23530 assert (DAG.getTargetLoweringInfo().isTypeLegal(WideVecVT)
23531 && "WideVecVT should be legal");
23532 WideSrc0 = DAG.getVectorShuffle(WideVecVT, dl, WideSrc0,
23533 DAG.getUNDEF(WideVecVT), &ShuffleVec[0]);
23535 // Prepare the new mask
23537 SDValue Mask = Mld->getMask();
23538 if (Mask.getValueType() == VT) {
23539 // Mask and original value have the same type
23540 NewMask = DAG.getBitcast(WideVecVT, Mask);
23541 SmallVector<int, 16> ShuffleVec(NumElems * SizeRatio, -1);
23542 for (unsigned i = 0; i != NumElems; ++i)
23543 ShuffleVec[i] = i * SizeRatio;
23544 for (unsigned i = NumElems; i != NumElems*SizeRatio; ++i)
23545 ShuffleVec[i] = NumElems*SizeRatio;
23546 NewMask = DAG.getVectorShuffle(WideVecVT, dl, NewMask,
23547 DAG.getConstant(0, dl, WideVecVT),
23551 assert(Mask.getValueType().getVectorElementType() == MVT::i1);
23552 unsigned WidenNumElts = NumElems*SizeRatio;
23553 unsigned MaskNumElts = VT.getVectorNumElements();
23554 EVT NewMaskVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
23557 unsigned NumConcat = WidenNumElts / MaskNumElts;
23558 SmallVector<SDValue, 16> Ops(NumConcat);
23559 SDValue ZeroVal = DAG.getConstant(0, dl, Mask.getValueType());
23561 for (unsigned i = 1; i != NumConcat; ++i)
23564 NewMask = DAG.getNode(ISD::CONCAT_VECTORS, dl, NewMaskVT, Ops);
23567 SDValue WideLd = DAG.getMaskedLoad(WideVecVT, dl, Mld->getChain(),
23568 Mld->getBasePtr(), NewMask, WideSrc0,
23569 Mld->getMemoryVT(), Mld->getMemOperand(),
23571 SDValue NewVec = DAG.getNode(X86ISD::VSEXT, dl, VT, WideLd);
23572 return DCI.CombineTo(N, NewVec, WideLd.getValue(1), true);
23575 /// PerformMSTORECombine - Resolve truncating stores
23576 static SDValue PerformMSTORECombine(SDNode *N, SelectionDAG &DAG,
23577 const X86Subtarget *Subtarget) {
23578 MaskedStoreSDNode *Mst = cast<MaskedStoreSDNode>(N);
23579 if (!Mst->isTruncatingStore())
23582 EVT VT = Mst->getValue().getValueType();
23583 unsigned NumElems = VT.getVectorNumElements();
23584 EVT StVT = Mst->getMemoryVT();
23587 assert(StVT != VT && "Cannot truncate to the same type");
23588 unsigned FromSz = VT.getVectorElementType().getSizeInBits();
23589 unsigned ToSz = StVT.getVectorElementType().getSizeInBits();
23591 // From, To sizes and ElemCount must be pow of two
23592 assert (isPowerOf2_32(NumElems * FromSz * ToSz) &&
23593 "Unexpected size for truncating masked store");
23594 // We are going to use the original vector elt for storing.
23595 // Accumulated smaller vector elements must be a multiple of the store size.
23596 assert (((NumElems * FromSz) % ToSz) == 0 &&
23597 "Unexpected ratio for truncating masked store");
23599 unsigned SizeRatio = FromSz / ToSz;
23600 assert(SizeRatio * NumElems * ToSz == VT.getSizeInBits());
23602 // Create a type on which we perform the shuffle
23603 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(),
23604 StVT.getScalarType(), NumElems*SizeRatio);
23606 assert(WideVecVT.getSizeInBits() == VT.getSizeInBits());
23608 SDValue WideVec = DAG.getBitcast(WideVecVT, Mst->getValue());
23609 SmallVector<int, 16> ShuffleVec(NumElems * SizeRatio, -1);
23610 for (unsigned i = 0; i != NumElems; ++i)
23611 ShuffleVec[i] = i * SizeRatio;
23613 // Can't shuffle using an illegal type.
23614 assert (DAG.getTargetLoweringInfo().isTypeLegal(WideVecVT)
23615 && "WideVecVT should be legal");
23617 SDValue TruncatedVal = DAG.getVectorShuffle(WideVecVT, dl, WideVec,
23618 DAG.getUNDEF(WideVecVT),
23622 SDValue Mask = Mst->getMask();
23623 if (Mask.getValueType() == VT) {
23624 // Mask and original value have the same type
23625 NewMask = DAG.getBitcast(WideVecVT, Mask);
23626 for (unsigned i = 0; i != NumElems; ++i)
23627 ShuffleVec[i] = i * SizeRatio;
23628 for (unsigned i = NumElems; i != NumElems*SizeRatio; ++i)
23629 ShuffleVec[i] = NumElems*SizeRatio;
23630 NewMask = DAG.getVectorShuffle(WideVecVT, dl, NewMask,
23631 DAG.getConstant(0, dl, WideVecVT),
23635 assert(Mask.getValueType().getVectorElementType() == MVT::i1);
23636 unsigned WidenNumElts = NumElems*SizeRatio;
23637 unsigned MaskNumElts = VT.getVectorNumElements();
23638 EVT NewMaskVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
23641 unsigned NumConcat = WidenNumElts / MaskNumElts;
23642 SmallVector<SDValue, 16> Ops(NumConcat);
23643 SDValue ZeroVal = DAG.getConstant(0, dl, Mask.getValueType());
23645 for (unsigned i = 1; i != NumConcat; ++i)
23648 NewMask = DAG.getNode(ISD::CONCAT_VECTORS, dl, NewMaskVT, Ops);
23651 return DAG.getMaskedStore(Mst->getChain(), dl, TruncatedVal, Mst->getBasePtr(),
23652 NewMask, StVT, Mst->getMemOperand(), false);
23654 /// PerformSTORECombine - Do target-specific dag combines on STORE nodes.
23655 static SDValue PerformSTORECombine(SDNode *N, SelectionDAG &DAG,
23656 const X86Subtarget *Subtarget) {
23657 StoreSDNode *St = cast<StoreSDNode>(N);
23658 EVT VT = St->getValue().getValueType();
23659 EVT StVT = St->getMemoryVT();
23661 SDValue StoredVal = St->getOperand(1);
23662 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
23664 // If we are saving a concatenation of two XMM registers and 32-byte stores
23665 // are slow, such as on Sandy Bridge, perform two 16-byte stores.
23666 unsigned Alignment = St->getAlignment();
23667 bool IsAligned = Alignment == 0 || Alignment >= VT.getSizeInBits()/8;
23668 if (VT.is256BitVector() && Subtarget->isUnalignedMem32Slow() &&
23669 StVT == VT && !IsAligned) {
23670 unsigned NumElems = VT.getVectorNumElements();
23674 SDValue Value0 = Extract128BitVector(StoredVal, 0, DAG, dl);
23675 SDValue Value1 = Extract128BitVector(StoredVal, NumElems/2, DAG, dl);
23677 SDValue Stride = DAG.getConstant(16, dl, TLI.getPointerTy());
23678 SDValue Ptr0 = St->getBasePtr();
23679 SDValue Ptr1 = DAG.getNode(ISD::ADD, dl, Ptr0.getValueType(), Ptr0, Stride);
23681 SDValue Ch0 = DAG.getStore(St->getChain(), dl, Value0, Ptr0,
23682 St->getPointerInfo(), St->isVolatile(),
23683 St->isNonTemporal(), Alignment);
23684 SDValue Ch1 = DAG.getStore(St->getChain(), dl, Value1, Ptr1,
23685 St->getPointerInfo(), St->isVolatile(),
23686 St->isNonTemporal(),
23687 std::min(16U, Alignment));
23688 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Ch0, Ch1);
23691 // Optimize trunc store (of multiple scalars) to shuffle and store.
23692 // First, pack all of the elements in one place. Next, store to memory
23693 // in fewer chunks.
23694 if (St->isTruncatingStore() && VT.isVector()) {
23695 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
23696 unsigned NumElems = VT.getVectorNumElements();
23697 assert(StVT != VT && "Cannot truncate to the same type");
23698 unsigned FromSz = VT.getVectorElementType().getSizeInBits();
23699 unsigned ToSz = StVT.getVectorElementType().getSizeInBits();
23701 // From, To sizes and ElemCount must be pow of two
23702 if (!isPowerOf2_32(NumElems * FromSz * ToSz)) return SDValue();
23703 // We are going to use the original vector elt for storing.
23704 // Accumulated smaller vector elements must be a multiple of the store size.
23705 if (0 != (NumElems * FromSz) % ToSz) return SDValue();
23707 unsigned SizeRatio = FromSz / ToSz;
23709 assert(SizeRatio * NumElems * ToSz == VT.getSizeInBits());
23711 // Create a type on which we perform the shuffle
23712 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(),
23713 StVT.getScalarType(), NumElems*SizeRatio);
23715 assert(WideVecVT.getSizeInBits() == VT.getSizeInBits());
23717 SDValue WideVec = DAG.getBitcast(WideVecVT, St->getValue());
23718 SmallVector<int, 8> ShuffleVec(NumElems * SizeRatio, -1);
23719 for (unsigned i = 0; i != NumElems; ++i)
23720 ShuffleVec[i] = i * SizeRatio;
23722 // Can't shuffle using an illegal type.
23723 if (!TLI.isTypeLegal(WideVecVT))
23726 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, WideVec,
23727 DAG.getUNDEF(WideVecVT),
23729 // At this point all of the data is stored at the bottom of the
23730 // register. We now need to save it to mem.
23732 // Find the largest store unit
23733 MVT StoreType = MVT::i8;
23734 for (MVT Tp : MVT::integer_valuetypes()) {
23735 if (TLI.isTypeLegal(Tp) && Tp.getSizeInBits() <= NumElems * ToSz)
23739 // On 32bit systems, we can't save 64bit integers. Try bitcasting to F64.
23740 if (TLI.isTypeLegal(MVT::f64) && StoreType.getSizeInBits() < 64 &&
23741 (64 <= NumElems * ToSz))
23742 StoreType = MVT::f64;
23744 // Bitcast the original vector into a vector of store-size units
23745 EVT StoreVecVT = EVT::getVectorVT(*DAG.getContext(),
23746 StoreType, VT.getSizeInBits()/StoreType.getSizeInBits());
23747 assert(StoreVecVT.getSizeInBits() == VT.getSizeInBits());
23748 SDValue ShuffWide = DAG.getBitcast(StoreVecVT, Shuff);
23749 SmallVector<SDValue, 8> Chains;
23750 SDValue Increment = DAG.getConstant(StoreType.getSizeInBits()/8, dl,
23751 TLI.getPointerTy());
23752 SDValue Ptr = St->getBasePtr();
23754 // Perform one or more big stores into memory.
23755 for (unsigned i=0, e=(ToSz*NumElems)/StoreType.getSizeInBits(); i!=e; ++i) {
23756 SDValue SubVec = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
23757 StoreType, ShuffWide,
23758 DAG.getIntPtrConstant(i, dl));
23759 SDValue Ch = DAG.getStore(St->getChain(), dl, SubVec, Ptr,
23760 St->getPointerInfo(), St->isVolatile(),
23761 St->isNonTemporal(), St->getAlignment());
23762 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
23763 Chains.push_back(Ch);
23766 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Chains);
23769 // Turn load->store of MMX types into GPR load/stores. This avoids clobbering
23770 // the FP state in cases where an emms may be missing.
23771 // A preferable solution to the general problem is to figure out the right
23772 // places to insert EMMS. This qualifies as a quick hack.
23774 // Similarly, turn load->store of i64 into double load/stores in 32-bit mode.
23775 if (VT.getSizeInBits() != 64)
23778 const Function *F = DAG.getMachineFunction().getFunction();
23779 bool NoImplicitFloatOps = F->hasFnAttribute(Attribute::NoImplicitFloat);
23781 !Subtarget->useSoftFloat() && !NoImplicitFloatOps && Subtarget->hasSSE2();
23782 if ((VT.isVector() ||
23783 (VT == MVT::i64 && F64IsLegal && !Subtarget->is64Bit())) &&
23784 isa<LoadSDNode>(St->getValue()) &&
23785 !cast<LoadSDNode>(St->getValue())->isVolatile() &&
23786 St->getChain().hasOneUse() && !St->isVolatile()) {
23787 SDNode* LdVal = St->getValue().getNode();
23788 LoadSDNode *Ld = nullptr;
23789 int TokenFactorIndex = -1;
23790 SmallVector<SDValue, 8> Ops;
23791 SDNode* ChainVal = St->getChain().getNode();
23792 // Must be a store of a load. We currently handle two cases: the load
23793 // is a direct child, and it's under an intervening TokenFactor. It is
23794 // possible to dig deeper under nested TokenFactors.
23795 if (ChainVal == LdVal)
23796 Ld = cast<LoadSDNode>(St->getChain());
23797 else if (St->getValue().hasOneUse() &&
23798 ChainVal->getOpcode() == ISD::TokenFactor) {
23799 for (unsigned i = 0, e = ChainVal->getNumOperands(); i != e; ++i) {
23800 if (ChainVal->getOperand(i).getNode() == LdVal) {
23801 TokenFactorIndex = i;
23802 Ld = cast<LoadSDNode>(St->getValue());
23804 Ops.push_back(ChainVal->getOperand(i));
23808 if (!Ld || !ISD::isNormalLoad(Ld))
23811 // If this is not the MMX case, i.e. we are just turning i64 load/store
23812 // into f64 load/store, avoid the transformation if there are multiple
23813 // uses of the loaded value.
23814 if (!VT.isVector() && !Ld->hasNUsesOfValue(1, 0))
23819 // If we are a 64-bit capable x86, lower to a single movq load/store pair.
23820 // Otherwise, if it's legal to use f64 SSE instructions, use f64 load/store
23822 if (Subtarget->is64Bit() || F64IsLegal) {
23823 EVT LdVT = Subtarget->is64Bit() ? MVT::i64 : MVT::f64;
23824 SDValue NewLd = DAG.getLoad(LdVT, LdDL, Ld->getChain(), Ld->getBasePtr(),
23825 Ld->getPointerInfo(), Ld->isVolatile(),
23826 Ld->isNonTemporal(), Ld->isInvariant(),
23827 Ld->getAlignment());
23828 SDValue NewChain = NewLd.getValue(1);
23829 if (TokenFactorIndex != -1) {
23830 Ops.push_back(NewChain);
23831 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, Ops);
23833 return DAG.getStore(NewChain, StDL, NewLd, St->getBasePtr(),
23834 St->getPointerInfo(),
23835 St->isVolatile(), St->isNonTemporal(),
23836 St->getAlignment());
23839 // Otherwise, lower to two pairs of 32-bit loads / stores.
23840 SDValue LoAddr = Ld->getBasePtr();
23841 SDValue HiAddr = DAG.getNode(ISD::ADD, LdDL, MVT::i32, LoAddr,
23842 DAG.getConstant(4, LdDL, MVT::i32));
23844 SDValue LoLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), LoAddr,
23845 Ld->getPointerInfo(),
23846 Ld->isVolatile(), Ld->isNonTemporal(),
23847 Ld->isInvariant(), Ld->getAlignment());
23848 SDValue HiLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), HiAddr,
23849 Ld->getPointerInfo().getWithOffset(4),
23850 Ld->isVolatile(), Ld->isNonTemporal(),
23852 MinAlign(Ld->getAlignment(), 4));
23854 SDValue NewChain = LoLd.getValue(1);
23855 if (TokenFactorIndex != -1) {
23856 Ops.push_back(LoLd);
23857 Ops.push_back(HiLd);
23858 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, Ops);
23861 LoAddr = St->getBasePtr();
23862 HiAddr = DAG.getNode(ISD::ADD, StDL, MVT::i32, LoAddr,
23863 DAG.getConstant(4, StDL, MVT::i32));
23865 SDValue LoSt = DAG.getStore(NewChain, StDL, LoLd, LoAddr,
23866 St->getPointerInfo(),
23867 St->isVolatile(), St->isNonTemporal(),
23868 St->getAlignment());
23869 SDValue HiSt = DAG.getStore(NewChain, StDL, HiLd, HiAddr,
23870 St->getPointerInfo().getWithOffset(4),
23872 St->isNonTemporal(),
23873 MinAlign(St->getAlignment(), 4));
23874 return DAG.getNode(ISD::TokenFactor, StDL, MVT::Other, LoSt, HiSt);
23877 // This is similar to the above case, but here we handle a scalar 64-bit
23878 // integer store that is extracted from a vector on a 32-bit target.
23879 // If we have SSE2, then we can treat it like a floating-point double
23880 // to get past legalization. The execution dependencies fixup pass will
23881 // choose the optimal machine instruction for the store if this really is
23882 // an integer or v2f32 rather than an f64.
23883 if (VT == MVT::i64 && F64IsLegal && !Subtarget->is64Bit() &&
23884 St->getOperand(1).getOpcode() == ISD::EXTRACT_VECTOR_ELT) {
23885 SDValue OldExtract = St->getOperand(1);
23886 SDValue ExtOp0 = OldExtract.getOperand(0);
23887 unsigned VecSize = ExtOp0.getValueSizeInBits();
23888 EVT VecVT = EVT::getVectorVT(*DAG.getContext(), MVT::f64, VecSize / 64);
23889 SDValue BitCast = DAG.getBitcast(VecVT, ExtOp0);
23890 SDValue NewExtract = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
23891 BitCast, OldExtract.getOperand(1));
23892 return DAG.getStore(St->getChain(), dl, NewExtract, St->getBasePtr(),
23893 St->getPointerInfo(), St->isVolatile(),
23894 St->isNonTemporal(), St->getAlignment());
23900 /// Return 'true' if this vector operation is "horizontal"
23901 /// and return the operands for the horizontal operation in LHS and RHS. A
23902 /// horizontal operation performs the binary operation on successive elements
23903 /// of its first operand, then on successive elements of its second operand,
23904 /// returning the resulting values in a vector. For example, if
23905 /// A = < float a0, float a1, float a2, float a3 >
23907 /// B = < float b0, float b1, float b2, float b3 >
23908 /// then the result of doing a horizontal operation on A and B is
23909 /// A horizontal-op B = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >.
23910 /// In short, LHS and RHS are inspected to see if LHS op RHS is of the form
23911 /// A horizontal-op B, for some already available A and B, and if so then LHS is
23912 /// set to A, RHS to B, and the routine returns 'true'.
23913 /// Note that the binary operation should have the property that if one of the
23914 /// operands is UNDEF then the result is UNDEF.
23915 static bool isHorizontalBinOp(SDValue &LHS, SDValue &RHS, bool IsCommutative) {
23916 // Look for the following pattern: if
23917 // A = < float a0, float a1, float a2, float a3 >
23918 // B = < float b0, float b1, float b2, float b3 >
23920 // LHS = VECTOR_SHUFFLE A, B, <0, 2, 4, 6>
23921 // RHS = VECTOR_SHUFFLE A, B, <1, 3, 5, 7>
23922 // then LHS op RHS = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >
23923 // which is A horizontal-op B.
23925 // At least one of the operands should be a vector shuffle.
23926 if (LHS.getOpcode() != ISD::VECTOR_SHUFFLE &&
23927 RHS.getOpcode() != ISD::VECTOR_SHUFFLE)
23930 MVT VT = LHS.getSimpleValueType();
23932 assert((VT.is128BitVector() || VT.is256BitVector()) &&
23933 "Unsupported vector type for horizontal add/sub");
23935 // Handle 128 and 256-bit vector lengths. AVX defines horizontal add/sub to
23936 // operate independently on 128-bit lanes.
23937 unsigned NumElts = VT.getVectorNumElements();
23938 unsigned NumLanes = VT.getSizeInBits()/128;
23939 unsigned NumLaneElts = NumElts / NumLanes;
23940 assert((NumLaneElts % 2 == 0) &&
23941 "Vector type should have an even number of elements in each lane");
23942 unsigned HalfLaneElts = NumLaneElts/2;
23944 // View LHS in the form
23945 // LHS = VECTOR_SHUFFLE A, B, LMask
23946 // If LHS is not a shuffle then pretend it is the shuffle
23947 // LHS = VECTOR_SHUFFLE LHS, undef, <0, 1, ..., N-1>
23948 // NOTE: in what follows a default initialized SDValue represents an UNDEF of
23951 SmallVector<int, 16> LMask(NumElts);
23952 if (LHS.getOpcode() == ISD::VECTOR_SHUFFLE) {
23953 if (LHS.getOperand(0).getOpcode() != ISD::UNDEF)
23954 A = LHS.getOperand(0);
23955 if (LHS.getOperand(1).getOpcode() != ISD::UNDEF)
23956 B = LHS.getOperand(1);
23957 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(LHS.getNode())->getMask();
23958 std::copy(Mask.begin(), Mask.end(), LMask.begin());
23960 if (LHS.getOpcode() != ISD::UNDEF)
23962 for (unsigned i = 0; i != NumElts; ++i)
23966 // Likewise, view RHS in the form
23967 // RHS = VECTOR_SHUFFLE C, D, RMask
23969 SmallVector<int, 16> RMask(NumElts);
23970 if (RHS.getOpcode() == ISD::VECTOR_SHUFFLE) {
23971 if (RHS.getOperand(0).getOpcode() != ISD::UNDEF)
23972 C = RHS.getOperand(0);
23973 if (RHS.getOperand(1).getOpcode() != ISD::UNDEF)
23974 D = RHS.getOperand(1);
23975 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(RHS.getNode())->getMask();
23976 std::copy(Mask.begin(), Mask.end(), RMask.begin());
23978 if (RHS.getOpcode() != ISD::UNDEF)
23980 for (unsigned i = 0; i != NumElts; ++i)
23984 // Check that the shuffles are both shuffling the same vectors.
23985 if (!(A == C && B == D) && !(A == D && B == C))
23988 // If everything is UNDEF then bail out: it would be better to fold to UNDEF.
23989 if (!A.getNode() && !B.getNode())
23992 // If A and B occur in reverse order in RHS, then "swap" them (which means
23993 // rewriting the mask).
23995 ShuffleVectorSDNode::commuteMask(RMask);
23997 // At this point LHS and RHS are equivalent to
23998 // LHS = VECTOR_SHUFFLE A, B, LMask
23999 // RHS = VECTOR_SHUFFLE A, B, RMask
24000 // Check that the masks correspond to performing a horizontal operation.
24001 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
24002 for (unsigned i = 0; i != NumLaneElts; ++i) {
24003 int LIdx = LMask[i+l], RIdx = RMask[i+l];
24005 // Ignore any UNDEF components.
24006 if (LIdx < 0 || RIdx < 0 ||
24007 (!A.getNode() && (LIdx < (int)NumElts || RIdx < (int)NumElts)) ||
24008 (!B.getNode() && (LIdx >= (int)NumElts || RIdx >= (int)NumElts)))
24011 // Check that successive elements are being operated on. If not, this is
24012 // not a horizontal operation.
24013 unsigned Src = (i/HalfLaneElts); // each lane is split between srcs
24014 int Index = 2*(i%HalfLaneElts) + NumElts*Src + l;
24015 if (!(LIdx == Index && RIdx == Index + 1) &&
24016 !(IsCommutative && LIdx == Index + 1 && RIdx == Index))
24021 LHS = A.getNode() ? A : B; // If A is 'UNDEF', use B for it.
24022 RHS = B.getNode() ? B : A; // If B is 'UNDEF', use A for it.
24026 /// Do target-specific dag combines on floating point adds.
24027 static SDValue PerformFADDCombine(SDNode *N, SelectionDAG &DAG,
24028 const X86Subtarget *Subtarget) {
24029 EVT VT = N->getValueType(0);
24030 SDValue LHS = N->getOperand(0);
24031 SDValue RHS = N->getOperand(1);
24033 // Try to synthesize horizontal adds from adds of shuffles.
24034 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
24035 (Subtarget->hasFp256() && (VT == MVT::v8f32 || VT == MVT::v4f64))) &&
24036 isHorizontalBinOp(LHS, RHS, true))
24037 return DAG.getNode(X86ISD::FHADD, SDLoc(N), VT, LHS, RHS);
24041 /// Do target-specific dag combines on floating point subs.
24042 static SDValue PerformFSUBCombine(SDNode *N, SelectionDAG &DAG,
24043 const X86Subtarget *Subtarget) {
24044 EVT VT = N->getValueType(0);
24045 SDValue LHS = N->getOperand(0);
24046 SDValue RHS = N->getOperand(1);
24048 // Try to synthesize horizontal subs from subs of shuffles.
24049 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
24050 (Subtarget->hasFp256() && (VT == MVT::v8f32 || VT == MVT::v4f64))) &&
24051 isHorizontalBinOp(LHS, RHS, false))
24052 return DAG.getNode(X86ISD::FHSUB, SDLoc(N), VT, LHS, RHS);
24056 /// Do target-specific dag combines on X86ISD::FOR and X86ISD::FXOR nodes.
24057 static SDValue PerformFORCombine(SDNode *N, SelectionDAG &DAG) {
24058 assert(N->getOpcode() == X86ISD::FOR || N->getOpcode() == X86ISD::FXOR);
24060 // F[X]OR(0.0, x) -> x
24061 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
24062 if (C->getValueAPF().isPosZero())
24063 return N->getOperand(1);
24065 // F[X]OR(x, 0.0) -> x
24066 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
24067 if (C->getValueAPF().isPosZero())
24068 return N->getOperand(0);
24072 /// Do target-specific dag combines on X86ISD::FMIN and X86ISD::FMAX nodes.
24073 static SDValue PerformFMinFMaxCombine(SDNode *N, SelectionDAG &DAG) {
24074 assert(N->getOpcode() == X86ISD::FMIN || N->getOpcode() == X86ISD::FMAX);
24076 // Only perform optimizations if UnsafeMath is used.
24077 if (!DAG.getTarget().Options.UnsafeFPMath)
24080 // If we run in unsafe-math mode, then convert the FMAX and FMIN nodes
24081 // into FMINC and FMAXC, which are Commutative operations.
24082 unsigned NewOp = 0;
24083 switch (N->getOpcode()) {
24084 default: llvm_unreachable("unknown opcode");
24085 case X86ISD::FMIN: NewOp = X86ISD::FMINC; break;
24086 case X86ISD::FMAX: NewOp = X86ISD::FMAXC; break;
24089 return DAG.getNode(NewOp, SDLoc(N), N->getValueType(0),
24090 N->getOperand(0), N->getOperand(1));
24093 /// Do target-specific dag combines on X86ISD::FAND nodes.
24094 static SDValue PerformFANDCombine(SDNode *N, SelectionDAG &DAG) {
24095 // FAND(0.0, x) -> 0.0
24096 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
24097 if (C->getValueAPF().isPosZero())
24098 return N->getOperand(0);
24100 // FAND(x, 0.0) -> 0.0
24101 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
24102 if (C->getValueAPF().isPosZero())
24103 return N->getOperand(1);
24108 /// Do target-specific dag combines on X86ISD::FANDN nodes
24109 static SDValue PerformFANDNCombine(SDNode *N, SelectionDAG &DAG) {
24110 // FANDN(0.0, x) -> x
24111 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
24112 if (C->getValueAPF().isPosZero())
24113 return N->getOperand(1);
24115 // FANDN(x, 0.0) -> 0.0
24116 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
24117 if (C->getValueAPF().isPosZero())
24118 return N->getOperand(1);
24123 static SDValue PerformBTCombine(SDNode *N,
24125 TargetLowering::DAGCombinerInfo &DCI) {
24126 // BT ignores high bits in the bit index operand.
24127 SDValue Op1 = N->getOperand(1);
24128 if (Op1.hasOneUse()) {
24129 unsigned BitWidth = Op1.getValueSizeInBits();
24130 APInt DemandedMask = APInt::getLowBitsSet(BitWidth, Log2_32(BitWidth));
24131 APInt KnownZero, KnownOne;
24132 TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(),
24133 !DCI.isBeforeLegalizeOps());
24134 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
24135 if (TLO.ShrinkDemandedConstant(Op1, DemandedMask) ||
24136 TLI.SimplifyDemandedBits(Op1, DemandedMask, KnownZero, KnownOne, TLO))
24137 DCI.CommitTargetLoweringOpt(TLO);
24142 static SDValue PerformVZEXT_MOVLCombine(SDNode *N, SelectionDAG &DAG) {
24143 SDValue Op = N->getOperand(0);
24144 if (Op.getOpcode() == ISD::BITCAST)
24145 Op = Op.getOperand(0);
24146 EVT VT = N->getValueType(0), OpVT = Op.getValueType();
24147 if (Op.getOpcode() == X86ISD::VZEXT_LOAD &&
24148 VT.getVectorElementType().getSizeInBits() ==
24149 OpVT.getVectorElementType().getSizeInBits()) {
24150 return DAG.getNode(ISD::BITCAST, SDLoc(N), VT, Op);
24155 static SDValue PerformSIGN_EXTEND_INREGCombine(SDNode *N, SelectionDAG &DAG,
24156 const X86Subtarget *Subtarget) {
24157 EVT VT = N->getValueType(0);
24158 if (!VT.isVector())
24161 SDValue N0 = N->getOperand(0);
24162 SDValue N1 = N->getOperand(1);
24163 EVT ExtraVT = cast<VTSDNode>(N1)->getVT();
24166 // The SIGN_EXTEND_INREG to v4i64 is expensive operation on the
24167 // both SSE and AVX2 since there is no sign-extended shift right
24168 // operation on a vector with 64-bit elements.
24169 //(sext_in_reg (v4i64 anyext (v4i32 x )), ExtraVT) ->
24170 // (v4i64 sext (v4i32 sext_in_reg (v4i32 x , ExtraVT)))
24171 if (VT == MVT::v4i64 && (N0.getOpcode() == ISD::ANY_EXTEND ||
24172 N0.getOpcode() == ISD::SIGN_EXTEND)) {
24173 SDValue N00 = N0.getOperand(0);
24175 // EXTLOAD has a better solution on AVX2,
24176 // it may be replaced with X86ISD::VSEXT node.
24177 if (N00.getOpcode() == ISD::LOAD && Subtarget->hasInt256())
24178 if (!ISD::isNormalLoad(N00.getNode()))
24181 if (N00.getValueType() == MVT::v4i32 && ExtraVT.getSizeInBits() < 128) {
24182 SDValue Tmp = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, MVT::v4i32,
24184 return DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v4i64, Tmp);
24190 static SDValue PerformSExtCombine(SDNode *N, SelectionDAG &DAG,
24191 TargetLowering::DAGCombinerInfo &DCI,
24192 const X86Subtarget *Subtarget) {
24193 SDValue N0 = N->getOperand(0);
24194 EVT VT = N->getValueType(0);
24195 EVT SVT = VT.getScalarType();
24196 EVT InVT = N0->getValueType(0);
24197 EVT InSVT = InVT.getScalarType();
24200 // (i8,i32 sext (sdivrem (i8 x, i8 y)) ->
24201 // (i8,i32 (sdivrem_sext_hreg (i8 x, i8 y)
24202 // This exposes the sext to the sdivrem lowering, so that it directly extends
24203 // from AH (which we otherwise need to do contortions to access).
24204 if (N0.getOpcode() == ISD::SDIVREM && N0.getResNo() == 1 &&
24205 InVT == MVT::i8 && VT == MVT::i32) {
24206 SDVTList NodeTys = DAG.getVTList(MVT::i8, VT);
24207 SDValue R = DAG.getNode(X86ISD::SDIVREM8_SEXT_HREG, DL, NodeTys,
24208 N0.getOperand(0), N0.getOperand(1));
24209 DAG.ReplaceAllUsesOfValueWith(N0.getValue(0), R.getValue(0));
24210 return R.getValue(1);
24213 if (!DCI.isBeforeLegalizeOps()) {
24214 if (N0.getValueType() == MVT::i1) {
24215 SDValue Zero = DAG.getConstant(0, DL, VT);
24217 DAG.getConstant(APInt::getAllOnesValue(VT.getSizeInBits()), DL, VT);
24218 return DAG.getNode(ISD::SELECT, DL, VT, N0, AllOnes, Zero);
24223 if (VT.isVector()) {
24224 auto ExtendToVec128 = [&DAG](SDLoc DL, SDValue N) {
24225 EVT InVT = N->getValueType(0);
24226 EVT OutVT = EVT::getVectorVT(*DAG.getContext(), InVT.getScalarType(),
24227 128 / InVT.getScalarSizeInBits());
24228 SmallVector<SDValue, 8> Opnds(128 / InVT.getSizeInBits(),
24229 DAG.getUNDEF(InVT));
24231 return DAG.getNode(ISD::CONCAT_VECTORS, DL, OutVT, Opnds);
24234 // If target-size is 128-bits, then convert to ISD::SIGN_EXTEND_VECTOR_INREG
24235 // which ensures lowering to X86ISD::VSEXT (pmovsx*).
24236 if (VT.getSizeInBits() == 128 &&
24237 (SVT == MVT::i64 || SVT == MVT::i32 || SVT == MVT::i16) &&
24238 (InSVT == MVT::i32 || InSVT == MVT::i16 || InSVT == MVT::i8)) {
24239 SDValue ExOp = ExtendToVec128(DL, N0);
24240 return DAG.getSignExtendVectorInReg(ExOp, DL, VT);
24243 // On pre-AVX2 targets, split into 128-bit nodes of
24244 // ISD::SIGN_EXTEND_VECTOR_INREG.
24245 if (!Subtarget->hasInt256() && !(VT.getSizeInBits() % 128) &&
24246 (SVT == MVT::i64 || SVT == MVT::i32 || SVT == MVT::i16) &&
24247 (InSVT == MVT::i32 || InSVT == MVT::i16 || InSVT == MVT::i8)) {
24248 unsigned NumVecs = VT.getSizeInBits() / 128;
24249 unsigned NumSubElts = 128 / SVT.getSizeInBits();
24250 EVT SubVT = EVT::getVectorVT(*DAG.getContext(), SVT, NumSubElts);
24251 EVT InSubVT = EVT::getVectorVT(*DAG.getContext(), InSVT, NumSubElts);
24253 SmallVector<SDValue, 8> Opnds;
24254 for (unsigned i = 0, Offset = 0; i != NumVecs;
24255 ++i, Offset += NumSubElts) {
24256 SDValue SrcVec = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, InSubVT, N0,
24257 DAG.getIntPtrConstant(Offset, DL));
24258 SrcVec = ExtendToVec128(DL, SrcVec);
24259 SrcVec = DAG.getSignExtendVectorInReg(SrcVec, DL, SubVT);
24260 Opnds.push_back(SrcVec);
24262 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, Opnds);
24266 if (!Subtarget->hasFp256())
24269 if (VT.isVector() && VT.getSizeInBits() == 256) {
24270 SDValue R = WidenMaskArithmetic(N, DAG, DCI, Subtarget);
24278 static SDValue PerformFMACombine(SDNode *N, SelectionDAG &DAG,
24279 const X86Subtarget* Subtarget) {
24281 EVT VT = N->getValueType(0);
24283 // Let legalize expand this if it isn't a legal type yet.
24284 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
24287 EVT ScalarVT = VT.getScalarType();
24288 if ((ScalarVT != MVT::f32 && ScalarVT != MVT::f64) ||
24289 (!Subtarget->hasFMA() && !Subtarget->hasFMA4()))
24292 SDValue A = N->getOperand(0);
24293 SDValue B = N->getOperand(1);
24294 SDValue C = N->getOperand(2);
24296 bool NegA = (A.getOpcode() == ISD::FNEG);
24297 bool NegB = (B.getOpcode() == ISD::FNEG);
24298 bool NegC = (C.getOpcode() == ISD::FNEG);
24300 // Negative multiplication when NegA xor NegB
24301 bool NegMul = (NegA != NegB);
24303 A = A.getOperand(0);
24305 B = B.getOperand(0);
24307 C = C.getOperand(0);
24311 Opcode = (!NegC) ? X86ISD::FMADD : X86ISD::FMSUB;
24313 Opcode = (!NegC) ? X86ISD::FNMADD : X86ISD::FNMSUB;
24315 return DAG.getNode(Opcode, dl, VT, A, B, C);
24318 static SDValue PerformZExtCombine(SDNode *N, SelectionDAG &DAG,
24319 TargetLowering::DAGCombinerInfo &DCI,
24320 const X86Subtarget *Subtarget) {
24321 // (i32 zext (and (i8 x86isd::setcc_carry), 1)) ->
24322 // (and (i32 x86isd::setcc_carry), 1)
24323 // This eliminates the zext. This transformation is necessary because
24324 // ISD::SETCC is always legalized to i8.
24326 SDValue N0 = N->getOperand(0);
24327 EVT VT = N->getValueType(0);
24329 if (N0.getOpcode() == ISD::AND &&
24331 N0.getOperand(0).hasOneUse()) {
24332 SDValue N00 = N0.getOperand(0);
24333 if (N00.getOpcode() == X86ISD::SETCC_CARRY) {
24334 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
24335 if (!C || C->getZExtValue() != 1)
24337 return DAG.getNode(ISD::AND, dl, VT,
24338 DAG.getNode(X86ISD::SETCC_CARRY, dl, VT,
24339 N00.getOperand(0), N00.getOperand(1)),
24340 DAG.getConstant(1, dl, VT));
24344 if (N0.getOpcode() == ISD::TRUNCATE &&
24346 N0.getOperand(0).hasOneUse()) {
24347 SDValue N00 = N0.getOperand(0);
24348 if (N00.getOpcode() == X86ISD::SETCC_CARRY) {
24349 return DAG.getNode(ISD::AND, dl, VT,
24350 DAG.getNode(X86ISD::SETCC_CARRY, dl, VT,
24351 N00.getOperand(0), N00.getOperand(1)),
24352 DAG.getConstant(1, dl, VT));
24355 if (VT.is256BitVector()) {
24356 SDValue R = WidenMaskArithmetic(N, DAG, DCI, Subtarget);
24361 // (i8,i32 zext (udivrem (i8 x, i8 y)) ->
24362 // (i8,i32 (udivrem_zext_hreg (i8 x, i8 y)
24363 // This exposes the zext to the udivrem lowering, so that it directly extends
24364 // from AH (which we otherwise need to do contortions to access).
24365 if (N0.getOpcode() == ISD::UDIVREM &&
24366 N0.getResNo() == 1 && N0.getValueType() == MVT::i8 &&
24367 (VT == MVT::i32 || VT == MVT::i64)) {
24368 SDVTList NodeTys = DAG.getVTList(MVT::i8, VT);
24369 SDValue R = DAG.getNode(X86ISD::UDIVREM8_ZEXT_HREG, dl, NodeTys,
24370 N0.getOperand(0), N0.getOperand(1));
24371 DAG.ReplaceAllUsesOfValueWith(N0.getValue(0), R.getValue(0));
24372 return R.getValue(1);
24378 // Optimize x == -y --> x+y == 0
24379 // x != -y --> x+y != 0
24380 static SDValue PerformISDSETCCCombine(SDNode *N, SelectionDAG &DAG,
24381 const X86Subtarget* Subtarget) {
24382 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(2))->get();
24383 SDValue LHS = N->getOperand(0);
24384 SDValue RHS = N->getOperand(1);
24385 EVT VT = N->getValueType(0);
24388 if ((CC == ISD::SETNE || CC == ISD::SETEQ) && LHS.getOpcode() == ISD::SUB)
24389 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(LHS.getOperand(0)))
24390 if (C->getAPIntValue() == 0 && LHS.hasOneUse()) {
24391 SDValue addV = DAG.getNode(ISD::ADD, DL, LHS.getValueType(), RHS,
24392 LHS.getOperand(1));
24393 return DAG.getSetCC(DL, N->getValueType(0), addV,
24394 DAG.getConstant(0, DL, addV.getValueType()), CC);
24396 if ((CC == ISD::SETNE || CC == ISD::SETEQ) && RHS.getOpcode() == ISD::SUB)
24397 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS.getOperand(0)))
24398 if (C->getAPIntValue() == 0 && RHS.hasOneUse()) {
24399 SDValue addV = DAG.getNode(ISD::ADD, DL, RHS.getValueType(), LHS,
24400 RHS.getOperand(1));
24401 return DAG.getSetCC(DL, N->getValueType(0), addV,
24402 DAG.getConstant(0, DL, addV.getValueType()), CC);
24405 if (VT.getScalarType() == MVT::i1 &&
24406 (CC == ISD::SETNE || CC == ISD::SETEQ || ISD::isSignedIntSetCC(CC))) {
24408 (LHS.getOpcode() == ISD::SIGN_EXTEND) &&
24409 (LHS.getOperand(0).getValueType().getScalarType() == MVT::i1);
24410 bool IsVZero1 = ISD::isBuildVectorAllZeros(RHS.getNode());
24412 if (!IsSEXT0 || !IsVZero1) {
24413 // Swap the operands and update the condition code.
24414 std::swap(LHS, RHS);
24415 CC = ISD::getSetCCSwappedOperands(CC);
24417 IsSEXT0 = (LHS.getOpcode() == ISD::SIGN_EXTEND) &&
24418 (LHS.getOperand(0).getValueType().getScalarType() == MVT::i1);
24419 IsVZero1 = ISD::isBuildVectorAllZeros(RHS.getNode());
24422 if (IsSEXT0 && IsVZero1) {
24423 assert(VT == LHS.getOperand(0).getValueType() &&
24424 "Uexpected operand type");
24425 if (CC == ISD::SETGT)
24426 return DAG.getConstant(0, DL, VT);
24427 if (CC == ISD::SETLE)
24428 return DAG.getConstant(1, DL, VT);
24429 if (CC == ISD::SETEQ || CC == ISD::SETGE)
24430 return DAG.getNOT(DL, LHS.getOperand(0), VT);
24432 assert((CC == ISD::SETNE || CC == ISD::SETLT) &&
24433 "Unexpected condition code!");
24434 return LHS.getOperand(0);
24441 static SDValue NarrowVectorLoadToElement(LoadSDNode *Load, unsigned Index,
24442 SelectionDAG &DAG) {
24444 MVT VT = Load->getSimpleValueType(0);
24445 MVT EVT = VT.getVectorElementType();
24446 SDValue Addr = Load->getOperand(1);
24447 SDValue NewAddr = DAG.getNode(
24448 ISD::ADD, dl, Addr.getSimpleValueType(), Addr,
24449 DAG.getConstant(Index * EVT.getStoreSize(), dl,
24450 Addr.getSimpleValueType()));
24453 DAG.getLoad(EVT, dl, Load->getChain(), NewAddr,
24454 DAG.getMachineFunction().getMachineMemOperand(
24455 Load->getMemOperand(), 0, EVT.getStoreSize()));
24459 static SDValue PerformINSERTPSCombine(SDNode *N, SelectionDAG &DAG,
24460 const X86Subtarget *Subtarget) {
24462 MVT VT = N->getOperand(1)->getSimpleValueType(0);
24463 assert((VT == MVT::v4f32 || VT == MVT::v4i32) &&
24464 "X86insertps is only defined for v4x32");
24466 SDValue Ld = N->getOperand(1);
24467 if (MayFoldLoad(Ld)) {
24468 // Extract the countS bits from the immediate so we can get the proper
24469 // address when narrowing the vector load to a specific element.
24470 // When the second source op is a memory address, insertps doesn't use
24471 // countS and just gets an f32 from that address.
24472 unsigned DestIndex =
24473 cast<ConstantSDNode>(N->getOperand(2))->getZExtValue() >> 6;
24475 Ld = NarrowVectorLoadToElement(cast<LoadSDNode>(Ld), DestIndex, DAG);
24477 // Create this as a scalar to vector to match the instruction pattern.
24478 SDValue LoadScalarToVector = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Ld);
24479 // countS bits are ignored when loading from memory on insertps, which
24480 // means we don't need to explicitly set them to 0.
24481 return DAG.getNode(X86ISD::INSERTPS, dl, VT, N->getOperand(0),
24482 LoadScalarToVector, N->getOperand(2));
24487 static SDValue PerformBLENDICombine(SDNode *N, SelectionDAG &DAG) {
24488 SDValue V0 = N->getOperand(0);
24489 SDValue V1 = N->getOperand(1);
24491 EVT VT = N->getValueType(0);
24493 // Canonicalize a v2f64 blend with a mask of 2 by swapping the vector
24494 // operands and changing the mask to 1. This saves us a bunch of
24495 // pattern-matching possibilities related to scalar math ops in SSE/AVX.
24496 // x86InstrInfo knows how to commute this back after instruction selection
24497 // if it would help register allocation.
24499 // TODO: If optimizing for size or a processor that doesn't suffer from
24500 // partial register update stalls, this should be transformed into a MOVSD
24501 // instruction because a MOVSD is 1-2 bytes smaller than a BLENDPD.
24503 if (VT == MVT::v2f64)
24504 if (auto *Mask = dyn_cast<ConstantSDNode>(N->getOperand(2)))
24505 if (Mask->getZExtValue() == 2 && !isShuffleFoldableLoad(V0)) {
24506 SDValue NewMask = DAG.getConstant(1, DL, MVT::i8);
24507 return DAG.getNode(X86ISD::BLENDI, DL, VT, V1, V0, NewMask);
24513 // Helper function of PerformSETCCCombine. It is to materialize "setb reg"
24514 // as "sbb reg,reg", since it can be extended without zext and produces
24515 // an all-ones bit which is more useful than 0/1 in some cases.
24516 static SDValue MaterializeSETB(SDLoc DL, SDValue EFLAGS, SelectionDAG &DAG,
24519 return DAG.getNode(ISD::AND, DL, VT,
24520 DAG.getNode(X86ISD::SETCC_CARRY, DL, MVT::i8,
24521 DAG.getConstant(X86::COND_B, DL, MVT::i8),
24523 DAG.getConstant(1, DL, VT));
24524 assert (VT == MVT::i1 && "Unexpected type for SECCC node");
24525 return DAG.getNode(ISD::TRUNCATE, DL, MVT::i1,
24526 DAG.getNode(X86ISD::SETCC_CARRY, DL, MVT::i8,
24527 DAG.getConstant(X86::COND_B, DL, MVT::i8),
24531 // Optimize RES = X86ISD::SETCC CONDCODE, EFLAG_INPUT
24532 static SDValue PerformSETCCCombine(SDNode *N, SelectionDAG &DAG,
24533 TargetLowering::DAGCombinerInfo &DCI,
24534 const X86Subtarget *Subtarget) {
24536 X86::CondCode CC = X86::CondCode(N->getConstantOperandVal(0));
24537 SDValue EFLAGS = N->getOperand(1);
24539 if (CC == X86::COND_A) {
24540 // Try to convert COND_A into COND_B in an attempt to facilitate
24541 // materializing "setb reg".
24543 // Do not flip "e > c", where "c" is a constant, because Cmp instruction
24544 // cannot take an immediate as its first operand.
24546 if (EFLAGS.getOpcode() == X86ISD::SUB && EFLAGS.hasOneUse() &&
24547 EFLAGS.getValueType().isInteger() &&
24548 !isa<ConstantSDNode>(EFLAGS.getOperand(1))) {
24549 SDValue NewSub = DAG.getNode(X86ISD::SUB, SDLoc(EFLAGS),
24550 EFLAGS.getNode()->getVTList(),
24551 EFLAGS.getOperand(1), EFLAGS.getOperand(0));
24552 SDValue NewEFLAGS = SDValue(NewSub.getNode(), EFLAGS.getResNo());
24553 return MaterializeSETB(DL, NewEFLAGS, DAG, N->getSimpleValueType(0));
24557 // Materialize "setb reg" as "sbb reg,reg", since it can be extended without
24558 // a zext and produces an all-ones bit which is more useful than 0/1 in some
24560 if (CC == X86::COND_B)
24561 return MaterializeSETB(DL, EFLAGS, DAG, N->getSimpleValueType(0));
24565 Flags = checkBoolTestSetCCCombine(EFLAGS, CC);
24566 if (Flags.getNode()) {
24567 SDValue Cond = DAG.getConstant(CC, DL, MVT::i8);
24568 return DAG.getNode(X86ISD::SETCC, DL, N->getVTList(), Cond, Flags);
24574 // Optimize branch condition evaluation.
24576 static SDValue PerformBrCondCombine(SDNode *N, SelectionDAG &DAG,
24577 TargetLowering::DAGCombinerInfo &DCI,
24578 const X86Subtarget *Subtarget) {
24580 SDValue Chain = N->getOperand(0);
24581 SDValue Dest = N->getOperand(1);
24582 SDValue EFLAGS = N->getOperand(3);
24583 X86::CondCode CC = X86::CondCode(N->getConstantOperandVal(2));
24587 Flags = checkBoolTestSetCCCombine(EFLAGS, CC);
24588 if (Flags.getNode()) {
24589 SDValue Cond = DAG.getConstant(CC, DL, MVT::i8);
24590 return DAG.getNode(X86ISD::BRCOND, DL, N->getVTList(), Chain, Dest, Cond,
24597 static SDValue performVectorCompareAndMaskUnaryOpCombine(SDNode *N,
24598 SelectionDAG &DAG) {
24599 // Take advantage of vector comparisons producing 0 or -1 in each lane to
24600 // optimize away operation when it's from a constant.
24602 // The general transformation is:
24603 // UNARYOP(AND(VECTOR_CMP(x,y), constant)) -->
24604 // AND(VECTOR_CMP(x,y), constant2)
24605 // constant2 = UNARYOP(constant)
24607 // Early exit if this isn't a vector operation, the operand of the
24608 // unary operation isn't a bitwise AND, or if the sizes of the operations
24609 // aren't the same.
24610 EVT VT = N->getValueType(0);
24611 if (!VT.isVector() || N->getOperand(0)->getOpcode() != ISD::AND ||
24612 N->getOperand(0)->getOperand(0)->getOpcode() != ISD::SETCC ||
24613 VT.getSizeInBits() != N->getOperand(0)->getValueType(0).getSizeInBits())
24616 // Now check that the other operand of the AND is a constant. We could
24617 // make the transformation for non-constant splats as well, but it's unclear
24618 // that would be a benefit as it would not eliminate any operations, just
24619 // perform one more step in scalar code before moving to the vector unit.
24620 if (BuildVectorSDNode *BV =
24621 dyn_cast<BuildVectorSDNode>(N->getOperand(0)->getOperand(1))) {
24622 // Bail out if the vector isn't a constant.
24623 if (!BV->isConstant())
24626 // Everything checks out. Build up the new and improved node.
24628 EVT IntVT = BV->getValueType(0);
24629 // Create a new constant of the appropriate type for the transformed
24631 SDValue SourceConst = DAG.getNode(N->getOpcode(), DL, VT, SDValue(BV, 0));
24632 // The AND node needs bitcasts to/from an integer vector type around it.
24633 SDValue MaskConst = DAG.getBitcast(IntVT, SourceConst);
24634 SDValue NewAnd = DAG.getNode(ISD::AND, DL, IntVT,
24635 N->getOperand(0)->getOperand(0), MaskConst);
24636 SDValue Res = DAG.getBitcast(VT, NewAnd);
24643 static SDValue PerformSINT_TO_FPCombine(SDNode *N, SelectionDAG &DAG,
24644 const X86Subtarget *Subtarget) {
24645 // First try to optimize away the conversion entirely when it's
24646 // conditionally from a constant. Vectors only.
24647 SDValue Res = performVectorCompareAndMaskUnaryOpCombine(N, DAG);
24648 if (Res != SDValue())
24651 // Now move on to more general possibilities.
24652 SDValue Op0 = N->getOperand(0);
24653 EVT InVT = Op0->getValueType(0);
24655 // SINT_TO_FP(v4i8) -> SINT_TO_FP(SEXT(v4i8 to v4i32))
24656 if (InVT == MVT::v8i8 || InVT == MVT::v4i8) {
24658 MVT DstVT = InVT == MVT::v4i8 ? MVT::v4i32 : MVT::v8i32;
24659 SDValue P = DAG.getNode(ISD::SIGN_EXTEND, dl, DstVT, Op0);
24660 return DAG.getNode(ISD::SINT_TO_FP, dl, N->getValueType(0), P);
24663 // Transform (SINT_TO_FP (i64 ...)) into an x87 operation if we have
24664 // a 32-bit target where SSE doesn't support i64->FP operations.
24665 if (Op0.getOpcode() == ISD::LOAD) {
24666 LoadSDNode *Ld = cast<LoadSDNode>(Op0.getNode());
24667 EVT VT = Ld->getValueType(0);
24669 // This transformation is not supported if the result type is f16
24670 if (N->getValueType(0) == MVT::f16)
24673 if (!Ld->isVolatile() && !N->getValueType(0).isVector() &&
24674 ISD::isNON_EXTLoad(Op0.getNode()) && Op0.hasOneUse() &&
24675 !Subtarget->is64Bit() && VT == MVT::i64) {
24676 SDValue FILDChain = Subtarget->getTargetLowering()->BuildFILD(
24677 SDValue(N, 0), Ld->getValueType(0), Ld->getChain(), Op0, DAG);
24678 DAG.ReplaceAllUsesOfValueWith(Op0.getValue(1), FILDChain.getValue(1));
24685 // Optimize RES, EFLAGS = X86ISD::ADC LHS, RHS, EFLAGS
24686 static SDValue PerformADCCombine(SDNode *N, SelectionDAG &DAG,
24687 X86TargetLowering::DAGCombinerInfo &DCI) {
24688 // If the LHS and RHS of the ADC node are zero, then it can't overflow and
24689 // the result is either zero or one (depending on the input carry bit).
24690 // Strength reduce this down to a "set on carry" aka SETCC_CARRY&1.
24691 if (X86::isZeroNode(N->getOperand(0)) &&
24692 X86::isZeroNode(N->getOperand(1)) &&
24693 // We don't have a good way to replace an EFLAGS use, so only do this when
24695 SDValue(N, 1).use_empty()) {
24697 EVT VT = N->getValueType(0);
24698 SDValue CarryOut = DAG.getConstant(0, DL, N->getValueType(1));
24699 SDValue Res1 = DAG.getNode(ISD::AND, DL, VT,
24700 DAG.getNode(X86ISD::SETCC_CARRY, DL, VT,
24701 DAG.getConstant(X86::COND_B, DL,
24704 DAG.getConstant(1, DL, VT));
24705 return DCI.CombineTo(N, Res1, CarryOut);
24711 // fold (add Y, (sete X, 0)) -> adc 0, Y
24712 // (add Y, (setne X, 0)) -> sbb -1, Y
24713 // (sub (sete X, 0), Y) -> sbb 0, Y
24714 // (sub (setne X, 0), Y) -> adc -1, Y
24715 static SDValue OptimizeConditionalInDecrement(SDNode *N, SelectionDAG &DAG) {
24718 // Look through ZExts.
24719 SDValue Ext = N->getOperand(N->getOpcode() == ISD::SUB ? 1 : 0);
24720 if (Ext.getOpcode() != ISD::ZERO_EXTEND || !Ext.hasOneUse())
24723 SDValue SetCC = Ext.getOperand(0);
24724 if (SetCC.getOpcode() != X86ISD::SETCC || !SetCC.hasOneUse())
24727 X86::CondCode CC = (X86::CondCode)SetCC.getConstantOperandVal(0);
24728 if (CC != X86::COND_E && CC != X86::COND_NE)
24731 SDValue Cmp = SetCC.getOperand(1);
24732 if (Cmp.getOpcode() != X86ISD::CMP || !Cmp.hasOneUse() ||
24733 !X86::isZeroNode(Cmp.getOperand(1)) ||
24734 !Cmp.getOperand(0).getValueType().isInteger())
24737 SDValue CmpOp0 = Cmp.getOperand(0);
24738 SDValue NewCmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32, CmpOp0,
24739 DAG.getConstant(1, DL, CmpOp0.getValueType()));
24741 SDValue OtherVal = N->getOperand(N->getOpcode() == ISD::SUB ? 0 : 1);
24742 if (CC == X86::COND_NE)
24743 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::ADC : X86ISD::SBB,
24744 DL, OtherVal.getValueType(), OtherVal,
24745 DAG.getConstant(-1ULL, DL, OtherVal.getValueType()),
24747 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::SBB : X86ISD::ADC,
24748 DL, OtherVal.getValueType(), OtherVal,
24749 DAG.getConstant(0, DL, OtherVal.getValueType()), NewCmp);
24752 /// PerformADDCombine - Do target-specific dag combines on integer adds.
24753 static SDValue PerformAddCombine(SDNode *N, SelectionDAG &DAG,
24754 const X86Subtarget *Subtarget) {
24755 EVT VT = N->getValueType(0);
24756 SDValue Op0 = N->getOperand(0);
24757 SDValue Op1 = N->getOperand(1);
24759 // Try to synthesize horizontal adds from adds of shuffles.
24760 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) ||
24761 (Subtarget->hasInt256() && (VT == MVT::v16i16 || VT == MVT::v8i32))) &&
24762 isHorizontalBinOp(Op0, Op1, true))
24763 return DAG.getNode(X86ISD::HADD, SDLoc(N), VT, Op0, Op1);
24765 return OptimizeConditionalInDecrement(N, DAG);
24768 static SDValue PerformSubCombine(SDNode *N, SelectionDAG &DAG,
24769 const X86Subtarget *Subtarget) {
24770 SDValue Op0 = N->getOperand(0);
24771 SDValue Op1 = N->getOperand(1);
24773 // X86 can't encode an immediate LHS of a sub. See if we can push the
24774 // negation into a preceding instruction.
24775 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op0)) {
24776 // If the RHS of the sub is a XOR with one use and a constant, invert the
24777 // immediate. Then add one to the LHS of the sub so we can turn
24778 // X-Y -> X+~Y+1, saving one register.
24779 if (Op1->hasOneUse() && Op1.getOpcode() == ISD::XOR &&
24780 isa<ConstantSDNode>(Op1.getOperand(1))) {
24781 APInt XorC = cast<ConstantSDNode>(Op1.getOperand(1))->getAPIntValue();
24782 EVT VT = Op0.getValueType();
24783 SDValue NewXor = DAG.getNode(ISD::XOR, SDLoc(Op1), VT,
24785 DAG.getConstant(~XorC, SDLoc(Op1), VT));
24786 return DAG.getNode(ISD::ADD, SDLoc(N), VT, NewXor,
24787 DAG.getConstant(C->getAPIntValue() + 1, SDLoc(N), VT));
24791 // Try to synthesize horizontal adds from adds of shuffles.
24792 EVT VT = N->getValueType(0);
24793 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) ||
24794 (Subtarget->hasInt256() && (VT == MVT::v16i16 || VT == MVT::v8i32))) &&
24795 isHorizontalBinOp(Op0, Op1, true))
24796 return DAG.getNode(X86ISD::HSUB, SDLoc(N), VT, Op0, Op1);
24798 return OptimizeConditionalInDecrement(N, DAG);
24801 /// performVZEXTCombine - Performs build vector combines
24802 static SDValue performVZEXTCombine(SDNode *N, SelectionDAG &DAG,
24803 TargetLowering::DAGCombinerInfo &DCI,
24804 const X86Subtarget *Subtarget) {
24806 MVT VT = N->getSimpleValueType(0);
24807 SDValue Op = N->getOperand(0);
24808 MVT OpVT = Op.getSimpleValueType();
24809 MVT OpEltVT = OpVT.getVectorElementType();
24810 unsigned InputBits = OpEltVT.getSizeInBits() * VT.getVectorNumElements();
24812 // (vzext (bitcast (vzext (x)) -> (vzext x)
24814 while (V.getOpcode() == ISD::BITCAST)
24815 V = V.getOperand(0);
24817 if (V != Op && V.getOpcode() == X86ISD::VZEXT) {
24818 MVT InnerVT = V.getSimpleValueType();
24819 MVT InnerEltVT = InnerVT.getVectorElementType();
24821 // If the element sizes match exactly, we can just do one larger vzext. This
24822 // is always an exact type match as vzext operates on integer types.
24823 if (OpEltVT == InnerEltVT) {
24824 assert(OpVT == InnerVT && "Types must match for vzext!");
24825 return DAG.getNode(X86ISD::VZEXT, DL, VT, V.getOperand(0));
24828 // The only other way we can combine them is if only a single element of the
24829 // inner vzext is used in the input to the outer vzext.
24830 if (InnerEltVT.getSizeInBits() < InputBits)
24833 // In this case, the inner vzext is completely dead because we're going to
24834 // only look at bits inside of the low element. Just do the outer vzext on
24835 // a bitcast of the input to the inner.
24836 return DAG.getNode(X86ISD::VZEXT, DL, VT, DAG.getBitcast(OpVT, V));
24839 // Check if we can bypass extracting and re-inserting an element of an input
24840 // vector. Essentialy:
24841 // (bitcast (sclr2vec (ext_vec_elt x))) -> (bitcast x)
24842 if (V.getOpcode() == ISD::SCALAR_TO_VECTOR &&
24843 V.getOperand(0).getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
24844 V.getOperand(0).getSimpleValueType().getSizeInBits() == InputBits) {
24845 SDValue ExtractedV = V.getOperand(0);
24846 SDValue OrigV = ExtractedV.getOperand(0);
24847 if (auto *ExtractIdx = dyn_cast<ConstantSDNode>(ExtractedV.getOperand(1)))
24848 if (ExtractIdx->getZExtValue() == 0) {
24849 MVT OrigVT = OrigV.getSimpleValueType();
24850 // Extract a subvector if necessary...
24851 if (OrigVT.getSizeInBits() > OpVT.getSizeInBits()) {
24852 int Ratio = OrigVT.getSizeInBits() / OpVT.getSizeInBits();
24853 OrigVT = MVT::getVectorVT(OrigVT.getVectorElementType(),
24854 OrigVT.getVectorNumElements() / Ratio);
24855 OrigV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, OrigVT, OrigV,
24856 DAG.getIntPtrConstant(0, DL));
24858 Op = DAG.getBitcast(OpVT, OrigV);
24859 return DAG.getNode(X86ISD::VZEXT, DL, VT, Op);
24866 SDValue X86TargetLowering::PerformDAGCombine(SDNode *N,
24867 DAGCombinerInfo &DCI) const {
24868 SelectionDAG &DAG = DCI.DAG;
24869 switch (N->getOpcode()) {
24871 case ISD::EXTRACT_VECTOR_ELT:
24872 return PerformEXTRACT_VECTOR_ELTCombine(N, DAG, DCI);
24875 case X86ISD::SHRUNKBLEND:
24876 return PerformSELECTCombine(N, DAG, DCI, Subtarget);
24877 case ISD::BITCAST: return PerformBITCASTCombine(N, DAG);
24878 case X86ISD::CMOV: return PerformCMOVCombine(N, DAG, DCI, Subtarget);
24879 case ISD::ADD: return PerformAddCombine(N, DAG, Subtarget);
24880 case ISD::SUB: return PerformSubCombine(N, DAG, Subtarget);
24881 case X86ISD::ADC: return PerformADCCombine(N, DAG, DCI);
24882 case ISD::MUL: return PerformMulCombine(N, DAG, DCI);
24885 case ISD::SRL: return PerformShiftCombine(N, DAG, DCI, Subtarget);
24886 case ISD::AND: return PerformAndCombine(N, DAG, DCI, Subtarget);
24887 case ISD::OR: return PerformOrCombine(N, DAG, DCI, Subtarget);
24888 case ISD::XOR: return PerformXorCombine(N, DAG, DCI, Subtarget);
24889 case ISD::LOAD: return PerformLOADCombine(N, DAG, DCI, Subtarget);
24890 case ISD::MLOAD: return PerformMLOADCombine(N, DAG, DCI, Subtarget);
24891 case ISD::STORE: return PerformSTORECombine(N, DAG, Subtarget);
24892 case ISD::MSTORE: return PerformMSTORECombine(N, DAG, Subtarget);
24893 case ISD::SINT_TO_FP: return PerformSINT_TO_FPCombine(N, DAG, Subtarget);
24894 case ISD::FADD: return PerformFADDCombine(N, DAG, Subtarget);
24895 case ISD::FSUB: return PerformFSUBCombine(N, DAG, Subtarget);
24897 case X86ISD::FOR: return PerformFORCombine(N, DAG);
24899 case X86ISD::FMAX: return PerformFMinFMaxCombine(N, DAG);
24900 case X86ISD::FAND: return PerformFANDCombine(N, DAG);
24901 case X86ISD::FANDN: return PerformFANDNCombine(N, DAG);
24902 case X86ISD::BT: return PerformBTCombine(N, DAG, DCI);
24903 case X86ISD::VZEXT_MOVL: return PerformVZEXT_MOVLCombine(N, DAG);
24904 case ISD::ANY_EXTEND:
24905 case ISD::ZERO_EXTEND: return PerformZExtCombine(N, DAG, DCI, Subtarget);
24906 case ISD::SIGN_EXTEND: return PerformSExtCombine(N, DAG, DCI, Subtarget);
24907 case ISD::SIGN_EXTEND_INREG:
24908 return PerformSIGN_EXTEND_INREGCombine(N, DAG, Subtarget);
24909 case ISD::SETCC: return PerformISDSETCCCombine(N, DAG, Subtarget);
24910 case X86ISD::SETCC: return PerformSETCCCombine(N, DAG, DCI, Subtarget);
24911 case X86ISD::BRCOND: return PerformBrCondCombine(N, DAG, DCI, Subtarget);
24912 case X86ISD::VZEXT: return performVZEXTCombine(N, DAG, DCI, Subtarget);
24913 case X86ISD::SHUFP: // Handle all target specific shuffles
24914 case X86ISD::PALIGNR:
24915 case X86ISD::UNPCKH:
24916 case X86ISD::UNPCKL:
24917 case X86ISD::MOVHLPS:
24918 case X86ISD::MOVLHPS:
24919 case X86ISD::PSHUFB:
24920 case X86ISD::PSHUFD:
24921 case X86ISD::PSHUFHW:
24922 case X86ISD::PSHUFLW:
24923 case X86ISD::MOVSS:
24924 case X86ISD::MOVSD:
24925 case X86ISD::VPERMILPI:
24926 case X86ISD::VPERM2X128:
24927 case ISD::VECTOR_SHUFFLE: return PerformShuffleCombine(N, DAG, DCI,Subtarget);
24928 case ISD::FMA: return PerformFMACombine(N, DAG, Subtarget);
24929 case ISD::INTRINSIC_WO_CHAIN:
24930 return PerformINTRINSIC_WO_CHAINCombine(N, DAG, Subtarget);
24931 case X86ISD::INSERTPS: {
24932 if (getTargetMachine().getOptLevel() > CodeGenOpt::None)
24933 return PerformINSERTPSCombine(N, DAG, Subtarget);
24936 case X86ISD::BLENDI: return PerformBLENDICombine(N, DAG);
24942 /// isTypeDesirableForOp - Return true if the target has native support for
24943 /// the specified value type and it is 'desirable' to use the type for the
24944 /// given node type. e.g. On x86 i16 is legal, but undesirable since i16
24945 /// instruction encodings are longer and some i16 instructions are slow.
24946 bool X86TargetLowering::isTypeDesirableForOp(unsigned Opc, EVT VT) const {
24947 if (!isTypeLegal(VT))
24949 if (VT != MVT::i16)
24956 case ISD::SIGN_EXTEND:
24957 case ISD::ZERO_EXTEND:
24958 case ISD::ANY_EXTEND:
24971 /// IsDesirableToPromoteOp - This method query the target whether it is
24972 /// beneficial for dag combiner to promote the specified node. If true, it
24973 /// should return the desired promotion type by reference.
24974 bool X86TargetLowering::IsDesirableToPromoteOp(SDValue Op, EVT &PVT) const {
24975 EVT VT = Op.getValueType();
24976 if (VT != MVT::i16)
24979 bool Promote = false;
24980 bool Commute = false;
24981 switch (Op.getOpcode()) {
24984 LoadSDNode *LD = cast<LoadSDNode>(Op);
24985 // If the non-extending load has a single use and it's not live out, then it
24986 // might be folded.
24987 if (LD->getExtensionType() == ISD::NON_EXTLOAD /*&&
24988 Op.hasOneUse()*/) {
24989 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
24990 UE = Op.getNode()->use_end(); UI != UE; ++UI) {
24991 // The only case where we'd want to promote LOAD (rather then it being
24992 // promoted as an operand is when it's only use is liveout.
24993 if (UI->getOpcode() != ISD::CopyToReg)
25000 case ISD::SIGN_EXTEND:
25001 case ISD::ZERO_EXTEND:
25002 case ISD::ANY_EXTEND:
25007 SDValue N0 = Op.getOperand(0);
25008 // Look out for (store (shl (load), x)).
25009 if (MayFoldLoad(N0) && MayFoldIntoStore(Op))
25022 SDValue N0 = Op.getOperand(0);
25023 SDValue N1 = Op.getOperand(1);
25024 if (!Commute && MayFoldLoad(N1))
25026 // Avoid disabling potential load folding opportunities.
25027 if (MayFoldLoad(N0) && (!isa<ConstantSDNode>(N1) || MayFoldIntoStore(Op)))
25029 if (MayFoldLoad(N1) && (!isa<ConstantSDNode>(N0) || MayFoldIntoStore(Op)))
25039 //===----------------------------------------------------------------------===//
25040 // X86 Inline Assembly Support
25041 //===----------------------------------------------------------------------===//
25043 // Helper to match a string separated by whitespace.
25044 static bool matchAsm(StringRef S, ArrayRef<const char *> Pieces) {
25045 S = S.substr(S.find_first_not_of(" \t")); // Skip leading whitespace.
25047 for (StringRef Piece : Pieces) {
25048 if (!S.startswith(Piece)) // Check if the piece matches.
25051 S = S.substr(Piece.size());
25052 StringRef::size_type Pos = S.find_first_not_of(" \t");
25053 if (Pos == 0) // We matched a prefix.
25062 static bool clobbersFlagRegisters(const SmallVector<StringRef, 4> &AsmPieces) {
25064 if (AsmPieces.size() == 3 || AsmPieces.size() == 4) {
25065 if (std::count(AsmPieces.begin(), AsmPieces.end(), "~{cc}") &&
25066 std::count(AsmPieces.begin(), AsmPieces.end(), "~{flags}") &&
25067 std::count(AsmPieces.begin(), AsmPieces.end(), "~{fpsr}")) {
25069 if (AsmPieces.size() == 3)
25071 else if (std::count(AsmPieces.begin(), AsmPieces.end(), "~{dirflag}"))
25078 bool X86TargetLowering::ExpandInlineAsm(CallInst *CI) const {
25079 InlineAsm *IA = cast<InlineAsm>(CI->getCalledValue());
25081 std::string AsmStr = IA->getAsmString();
25083 IntegerType *Ty = dyn_cast<IntegerType>(CI->getType());
25084 if (!Ty || Ty->getBitWidth() % 16 != 0)
25087 // TODO: should remove alternatives from the asmstring: "foo {a|b}" -> "foo a"
25088 SmallVector<StringRef, 4> AsmPieces;
25089 SplitString(AsmStr, AsmPieces, ";\n");
25091 switch (AsmPieces.size()) {
25092 default: return false;
25094 // FIXME: this should verify that we are targeting a 486 or better. If not,
25095 // we will turn this bswap into something that will be lowered to logical
25096 // ops instead of emitting the bswap asm. For now, we don't support 486 or
25097 // lower so don't worry about this.
25099 if (matchAsm(AsmPieces[0], {"bswap", "$0"}) ||
25100 matchAsm(AsmPieces[0], {"bswapl", "$0"}) ||
25101 matchAsm(AsmPieces[0], {"bswapq", "$0"}) ||
25102 matchAsm(AsmPieces[0], {"bswap", "${0:q}"}) ||
25103 matchAsm(AsmPieces[0], {"bswapl", "${0:q}"}) ||
25104 matchAsm(AsmPieces[0], {"bswapq", "${0:q}"})) {
25105 // No need to check constraints, nothing other than the equivalent of
25106 // "=r,0" would be valid here.
25107 return IntrinsicLowering::LowerToByteSwap(CI);
25110 // rorw $$8, ${0:w} --> llvm.bswap.i16
25111 if (CI->getType()->isIntegerTy(16) &&
25112 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 &&
25113 (matchAsm(AsmPieces[0], {"rorw", "$$8,", "${0:w}"}) ||
25114 matchAsm(AsmPieces[0], {"rolw", "$$8,", "${0:w}"}))) {
25116 const std::string &ConstraintsStr = IA->getConstraintString();
25117 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
25118 array_pod_sort(AsmPieces.begin(), AsmPieces.end());
25119 if (clobbersFlagRegisters(AsmPieces))
25120 return IntrinsicLowering::LowerToByteSwap(CI);
25124 if (CI->getType()->isIntegerTy(32) &&
25125 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 &&
25126 matchAsm(AsmPieces[0], {"rorw", "$$8,", "${0:w}"}) &&
25127 matchAsm(AsmPieces[1], {"rorl", "$$16,", "$0"}) &&
25128 matchAsm(AsmPieces[2], {"rorw", "$$8,", "${0:w}"})) {
25130 const std::string &ConstraintsStr = IA->getConstraintString();
25131 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
25132 array_pod_sort(AsmPieces.begin(), AsmPieces.end());
25133 if (clobbersFlagRegisters(AsmPieces))
25134 return IntrinsicLowering::LowerToByteSwap(CI);
25137 if (CI->getType()->isIntegerTy(64)) {
25138 InlineAsm::ConstraintInfoVector Constraints = IA->ParseConstraints();
25139 if (Constraints.size() >= 2 &&
25140 Constraints[0].Codes.size() == 1 && Constraints[0].Codes[0] == "A" &&
25141 Constraints[1].Codes.size() == 1 && Constraints[1].Codes[0] == "0") {
25142 // bswap %eax / bswap %edx / xchgl %eax, %edx -> llvm.bswap.i64
25143 if (matchAsm(AsmPieces[0], {"bswap", "%eax"}) &&
25144 matchAsm(AsmPieces[1], {"bswap", "%edx"}) &&
25145 matchAsm(AsmPieces[2], {"xchgl", "%eax,", "%edx"}))
25146 return IntrinsicLowering::LowerToByteSwap(CI);
25154 /// getConstraintType - Given a constraint letter, return the type of
25155 /// constraint it is for this target.
25156 X86TargetLowering::ConstraintType
25157 X86TargetLowering::getConstraintType(const std::string &Constraint) const {
25158 if (Constraint.size() == 1) {
25159 switch (Constraint[0]) {
25170 return C_RegisterClass;
25194 return TargetLowering::getConstraintType(Constraint);
25197 /// Examine constraint type and operand type and determine a weight value.
25198 /// This object must already have been set up with the operand type
25199 /// and the current alternative constraint selected.
25200 TargetLowering::ConstraintWeight
25201 X86TargetLowering::getSingleConstraintMatchWeight(
25202 AsmOperandInfo &info, const char *constraint) const {
25203 ConstraintWeight weight = CW_Invalid;
25204 Value *CallOperandVal = info.CallOperandVal;
25205 // If we don't have a value, we can't do a match,
25206 // but allow it at the lowest weight.
25207 if (!CallOperandVal)
25209 Type *type = CallOperandVal->getType();
25210 // Look at the constraint type.
25211 switch (*constraint) {
25213 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
25224 if (CallOperandVal->getType()->isIntegerTy())
25225 weight = CW_SpecificReg;
25230 if (type->isFloatingPointTy())
25231 weight = CW_SpecificReg;
25234 if (type->isX86_MMXTy() && Subtarget->hasMMX())
25235 weight = CW_SpecificReg;
25239 if (((type->getPrimitiveSizeInBits() == 128) && Subtarget->hasSSE1()) ||
25240 ((type->getPrimitiveSizeInBits() == 256) && Subtarget->hasFp256()))
25241 weight = CW_Register;
25244 if (ConstantInt *C = dyn_cast<ConstantInt>(info.CallOperandVal)) {
25245 if (C->getZExtValue() <= 31)
25246 weight = CW_Constant;
25250 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
25251 if (C->getZExtValue() <= 63)
25252 weight = CW_Constant;
25256 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
25257 if ((C->getSExtValue() >= -0x80) && (C->getSExtValue() <= 0x7f))
25258 weight = CW_Constant;
25262 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
25263 if ((C->getZExtValue() == 0xff) || (C->getZExtValue() == 0xffff))
25264 weight = CW_Constant;
25268 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
25269 if (C->getZExtValue() <= 3)
25270 weight = CW_Constant;
25274 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
25275 if (C->getZExtValue() <= 0xff)
25276 weight = CW_Constant;
25281 if (isa<ConstantFP>(CallOperandVal)) {
25282 weight = CW_Constant;
25286 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
25287 if ((C->getSExtValue() >= -0x80000000LL) &&
25288 (C->getSExtValue() <= 0x7fffffffLL))
25289 weight = CW_Constant;
25293 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
25294 if (C->getZExtValue() <= 0xffffffff)
25295 weight = CW_Constant;
25302 /// LowerXConstraint - try to replace an X constraint, which matches anything,
25303 /// with another that has more specific requirements based on the type of the
25304 /// corresponding operand.
25305 const char *X86TargetLowering::
25306 LowerXConstraint(EVT ConstraintVT) const {
25307 // FP X constraints get lowered to SSE1/2 registers if available, otherwise
25308 // 'f' like normal targets.
25309 if (ConstraintVT.isFloatingPoint()) {
25310 if (Subtarget->hasSSE2())
25312 if (Subtarget->hasSSE1())
25316 return TargetLowering::LowerXConstraint(ConstraintVT);
25319 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
25320 /// vector. If it is invalid, don't add anything to Ops.
25321 void X86TargetLowering::LowerAsmOperandForConstraint(SDValue Op,
25322 std::string &Constraint,
25323 std::vector<SDValue>&Ops,
25324 SelectionDAG &DAG) const {
25327 // Only support length 1 constraints for now.
25328 if (Constraint.length() > 1) return;
25330 char ConstraintLetter = Constraint[0];
25331 switch (ConstraintLetter) {
25334 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
25335 if (C->getZExtValue() <= 31) {
25336 Result = DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op),
25337 Op.getValueType());
25343 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
25344 if (C->getZExtValue() <= 63) {
25345 Result = DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op),
25346 Op.getValueType());
25352 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
25353 if (isInt<8>(C->getSExtValue())) {
25354 Result = DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op),
25355 Op.getValueType());
25361 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
25362 if (C->getZExtValue() == 0xff || C->getZExtValue() == 0xffff ||
25363 (Subtarget->is64Bit() && C->getZExtValue() == 0xffffffff)) {
25364 Result = DAG.getTargetConstant(C->getSExtValue(), SDLoc(Op),
25365 Op.getValueType());
25371 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
25372 if (C->getZExtValue() <= 3) {
25373 Result = DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op),
25374 Op.getValueType());
25380 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
25381 if (C->getZExtValue() <= 255) {
25382 Result = DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op),
25383 Op.getValueType());
25389 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
25390 if (C->getZExtValue() <= 127) {
25391 Result = DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op),
25392 Op.getValueType());
25398 // 32-bit signed value
25399 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
25400 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
25401 C->getSExtValue())) {
25402 // Widen to 64 bits here to get it sign extended.
25403 Result = DAG.getTargetConstant(C->getSExtValue(), SDLoc(Op), MVT::i64);
25406 // FIXME gcc accepts some relocatable values here too, but only in certain
25407 // memory models; it's complicated.
25412 // 32-bit unsigned value
25413 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
25414 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
25415 C->getZExtValue())) {
25416 Result = DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op),
25417 Op.getValueType());
25421 // FIXME gcc accepts some relocatable values here too, but only in certain
25422 // memory models; it's complicated.
25426 // Literal immediates are always ok.
25427 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op)) {
25428 // Widen to 64 bits here to get it sign extended.
25429 Result = DAG.getTargetConstant(CST->getSExtValue(), SDLoc(Op), MVT::i64);
25433 // In any sort of PIC mode addresses need to be computed at runtime by
25434 // adding in a register or some sort of table lookup. These can't
25435 // be used as immediates.
25436 if (Subtarget->isPICStyleGOT() || Subtarget->isPICStyleStubPIC())
25439 // If we are in non-pic codegen mode, we allow the address of a global (with
25440 // an optional displacement) to be used with 'i'.
25441 GlobalAddressSDNode *GA = nullptr;
25442 int64_t Offset = 0;
25444 // Match either (GA), (GA+C), (GA+C1+C2), etc.
25446 if ((GA = dyn_cast<GlobalAddressSDNode>(Op))) {
25447 Offset += GA->getOffset();
25449 } else if (Op.getOpcode() == ISD::ADD) {
25450 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
25451 Offset += C->getZExtValue();
25452 Op = Op.getOperand(0);
25455 } else if (Op.getOpcode() == ISD::SUB) {
25456 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
25457 Offset += -C->getZExtValue();
25458 Op = Op.getOperand(0);
25463 // Otherwise, this isn't something we can handle, reject it.
25467 const GlobalValue *GV = GA->getGlobal();
25468 // If we require an extra load to get this address, as in PIC mode, we
25469 // can't accept it.
25470 if (isGlobalStubReference(
25471 Subtarget->ClassifyGlobalReference(GV, DAG.getTarget())))
25474 Result = DAG.getTargetGlobalAddress(GV, SDLoc(Op),
25475 GA->getValueType(0), Offset);
25480 if (Result.getNode()) {
25481 Ops.push_back(Result);
25484 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
25487 std::pair<unsigned, const TargetRegisterClass *>
25488 X86TargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
25489 const std::string &Constraint,
25491 // First, see if this is a constraint that directly corresponds to an LLVM
25493 if (Constraint.size() == 1) {
25494 // GCC Constraint Letters
25495 switch (Constraint[0]) {
25497 // TODO: Slight differences here in allocation order and leaving
25498 // RIP in the class. Do they matter any more here than they do
25499 // in the normal allocation?
25500 case 'q': // GENERAL_REGS in 64-bit mode, Q_REGS in 32-bit mode.
25501 if (Subtarget->is64Bit()) {
25502 if (VT == MVT::i32 || VT == MVT::f32)
25503 return std::make_pair(0U, &X86::GR32RegClass);
25504 if (VT == MVT::i16)
25505 return std::make_pair(0U, &X86::GR16RegClass);
25506 if (VT == MVT::i8 || VT == MVT::i1)
25507 return std::make_pair(0U, &X86::GR8RegClass);
25508 if (VT == MVT::i64 || VT == MVT::f64)
25509 return std::make_pair(0U, &X86::GR64RegClass);
25512 // 32-bit fallthrough
25513 case 'Q': // Q_REGS
25514 if (VT == MVT::i32 || VT == MVT::f32)
25515 return std::make_pair(0U, &X86::GR32_ABCDRegClass);
25516 if (VT == MVT::i16)
25517 return std::make_pair(0U, &X86::GR16_ABCDRegClass);
25518 if (VT == MVT::i8 || VT == MVT::i1)
25519 return std::make_pair(0U, &X86::GR8_ABCD_LRegClass);
25520 if (VT == MVT::i64)
25521 return std::make_pair(0U, &X86::GR64_ABCDRegClass);
25523 case 'r': // GENERAL_REGS
25524 case 'l': // INDEX_REGS
25525 if (VT == MVT::i8 || VT == MVT::i1)
25526 return std::make_pair(0U, &X86::GR8RegClass);
25527 if (VT == MVT::i16)
25528 return std::make_pair(0U, &X86::GR16RegClass);
25529 if (VT == MVT::i32 || VT == MVT::f32 || !Subtarget->is64Bit())
25530 return std::make_pair(0U, &X86::GR32RegClass);
25531 return std::make_pair(0U, &X86::GR64RegClass);
25532 case 'R': // LEGACY_REGS
25533 if (VT == MVT::i8 || VT == MVT::i1)
25534 return std::make_pair(0U, &X86::GR8_NOREXRegClass);
25535 if (VT == MVT::i16)
25536 return std::make_pair(0U, &X86::GR16_NOREXRegClass);
25537 if (VT == MVT::i32 || !Subtarget->is64Bit())
25538 return std::make_pair(0U, &X86::GR32_NOREXRegClass);
25539 return std::make_pair(0U, &X86::GR64_NOREXRegClass);
25540 case 'f': // FP Stack registers.
25541 // If SSE is enabled for this VT, use f80 to ensure the isel moves the
25542 // value to the correct fpstack register class.
25543 if (VT == MVT::f32 && !isScalarFPTypeInSSEReg(VT))
25544 return std::make_pair(0U, &X86::RFP32RegClass);
25545 if (VT == MVT::f64 && !isScalarFPTypeInSSEReg(VT))
25546 return std::make_pair(0U, &X86::RFP64RegClass);
25547 return std::make_pair(0U, &X86::RFP80RegClass);
25548 case 'y': // MMX_REGS if MMX allowed.
25549 if (!Subtarget->hasMMX()) break;
25550 return std::make_pair(0U, &X86::VR64RegClass);
25551 case 'Y': // SSE_REGS if SSE2 allowed
25552 if (!Subtarget->hasSSE2()) break;
25554 case 'x': // SSE_REGS if SSE1 allowed or AVX_REGS if AVX allowed
25555 if (!Subtarget->hasSSE1()) break;
25557 switch (VT.SimpleTy) {
25559 // Scalar SSE types.
25562 return std::make_pair(0U, &X86::FR32RegClass);
25565 return std::make_pair(0U, &X86::FR64RegClass);
25573 return std::make_pair(0U, &X86::VR128RegClass);
25581 return std::make_pair(0U, &X86::VR256RegClass);
25586 return std::make_pair(0U, &X86::VR512RegClass);
25592 // Use the default implementation in TargetLowering to convert the register
25593 // constraint into a member of a register class.
25594 std::pair<unsigned, const TargetRegisterClass*> Res;
25595 Res = TargetLowering::getRegForInlineAsmConstraint(TRI, Constraint, VT);
25597 // Not found as a standard register?
25599 // Map st(0) -> st(7) -> ST0
25600 if (Constraint.size() == 7 && Constraint[0] == '{' &&
25601 tolower(Constraint[1]) == 's' &&
25602 tolower(Constraint[2]) == 't' &&
25603 Constraint[3] == '(' &&
25604 (Constraint[4] >= '0' && Constraint[4] <= '7') &&
25605 Constraint[5] == ')' &&
25606 Constraint[6] == '}') {
25608 Res.first = X86::FP0+Constraint[4]-'0';
25609 Res.second = &X86::RFP80RegClass;
25613 // GCC allows "st(0)" to be called just plain "st".
25614 if (StringRef("{st}").equals_lower(Constraint)) {
25615 Res.first = X86::FP0;
25616 Res.second = &X86::RFP80RegClass;
25621 if (StringRef("{flags}").equals_lower(Constraint)) {
25622 Res.first = X86::EFLAGS;
25623 Res.second = &X86::CCRRegClass;
25627 // 'A' means EAX + EDX.
25628 if (Constraint == "A") {
25629 Res.first = X86::EAX;
25630 Res.second = &X86::GR32_ADRegClass;
25636 // Otherwise, check to see if this is a register class of the wrong value
25637 // type. For example, we want to map "{ax},i32" -> {eax}, we don't want it to
25638 // turn into {ax},{dx}.
25639 if (Res.second->hasType(VT))
25640 return Res; // Correct type already, nothing to do.
25642 // All of the single-register GCC register classes map their values onto
25643 // 16-bit register pieces "ax","dx","cx","bx","si","di","bp","sp". If we
25644 // really want an 8-bit or 32-bit register, map to the appropriate register
25645 // class and return the appropriate register.
25646 if (Res.second == &X86::GR16RegClass) {
25647 if (VT == MVT::i8 || VT == MVT::i1) {
25648 unsigned DestReg = 0;
25649 switch (Res.first) {
25651 case X86::AX: DestReg = X86::AL; break;
25652 case X86::DX: DestReg = X86::DL; break;
25653 case X86::CX: DestReg = X86::CL; break;
25654 case X86::BX: DestReg = X86::BL; break;
25657 Res.first = DestReg;
25658 Res.second = &X86::GR8RegClass;
25660 } else if (VT == MVT::i32 || VT == MVT::f32) {
25661 unsigned DestReg = 0;
25662 switch (Res.first) {
25664 case X86::AX: DestReg = X86::EAX; break;
25665 case X86::DX: DestReg = X86::EDX; break;
25666 case X86::CX: DestReg = X86::ECX; break;
25667 case X86::BX: DestReg = X86::EBX; break;
25668 case X86::SI: DestReg = X86::ESI; break;
25669 case X86::DI: DestReg = X86::EDI; break;
25670 case X86::BP: DestReg = X86::EBP; break;
25671 case X86::SP: DestReg = X86::ESP; break;
25674 Res.first = DestReg;
25675 Res.second = &X86::GR32RegClass;
25677 } else if (VT == MVT::i64 || VT == MVT::f64) {
25678 unsigned DestReg = 0;
25679 switch (Res.first) {
25681 case X86::AX: DestReg = X86::RAX; break;
25682 case X86::DX: DestReg = X86::RDX; break;
25683 case X86::CX: DestReg = X86::RCX; break;
25684 case X86::BX: DestReg = X86::RBX; break;
25685 case X86::SI: DestReg = X86::RSI; break;
25686 case X86::DI: DestReg = X86::RDI; break;
25687 case X86::BP: DestReg = X86::RBP; break;
25688 case X86::SP: DestReg = X86::RSP; break;
25691 Res.first = DestReg;
25692 Res.second = &X86::GR64RegClass;
25694 } else if (VT != MVT::Other) {
25695 // Type mismatch and not a clobber: Return an error;
25697 Res.second = nullptr;
25699 } else if (Res.second == &X86::FR32RegClass ||
25700 Res.second == &X86::FR64RegClass ||
25701 Res.second == &X86::VR128RegClass ||
25702 Res.second == &X86::VR256RegClass ||
25703 Res.second == &X86::FR32XRegClass ||
25704 Res.second == &X86::FR64XRegClass ||
25705 Res.second == &X86::VR128XRegClass ||
25706 Res.second == &X86::VR256XRegClass ||
25707 Res.second == &X86::VR512RegClass) {
25708 // Handle references to XMM physical registers that got mapped into the
25709 // wrong class. This can happen with constraints like {xmm0} where the
25710 // target independent register mapper will just pick the first match it can
25711 // find, ignoring the required type.
25713 if (VT == MVT::f32 || VT == MVT::i32)
25714 Res.second = &X86::FR32RegClass;
25715 else if (VT == MVT::f64 || VT == MVT::i64)
25716 Res.second = &X86::FR64RegClass;
25717 else if (X86::VR128RegClass.hasType(VT))
25718 Res.second = &X86::VR128RegClass;
25719 else if (X86::VR256RegClass.hasType(VT))
25720 Res.second = &X86::VR256RegClass;
25721 else if (X86::VR512RegClass.hasType(VT))
25722 Res.second = &X86::VR512RegClass;
25723 else if (VT != MVT::Other) {
25724 // Type mismatch and not a clobber: Return an error;
25726 Res.second = nullptr;
25728 } else if (VT != MVT::Other) {
25729 // Type mismatch and not a clobber: Return an error;
25731 Res.second = nullptr;
25737 int X86TargetLowering::getScalingFactorCost(const AddrMode &AM,
25739 unsigned AS) const {
25740 // Scaling factors are not free at all.
25741 // An indexed folded instruction, i.e., inst (reg1, reg2, scale),
25742 // will take 2 allocations in the out of order engine instead of 1
25743 // for plain addressing mode, i.e. inst (reg1).
25745 // vaddps (%rsi,%drx), %ymm0, %ymm1
25746 // Requires two allocations (one for the load, one for the computation)
25748 // vaddps (%rsi), %ymm0, %ymm1
25749 // Requires just 1 allocation, i.e., freeing allocations for other operations
25750 // and having less micro operations to execute.
25752 // For some X86 architectures, this is even worse because for instance for
25753 // stores, the complex addressing mode forces the instruction to use the
25754 // "load" ports instead of the dedicated "store" port.
25755 // E.g., on Haswell:
25756 // vmovaps %ymm1, (%r8, %rdi) can use port 2 or 3.
25757 // vmovaps %ymm1, (%r8) can use port 2, 3, or 7.
25758 if (isLegalAddressingMode(AM, Ty, AS))
25759 // Scale represents reg2 * scale, thus account for 1
25760 // as soon as we use a second register.
25761 return AM.Scale != 0;
25765 bool X86TargetLowering::isTargetFTOL() const {
25766 return Subtarget->isTargetKnownWindowsMSVC() && !Subtarget->is64Bit();