1 //===-- X86ISelLowering.cpp - X86 DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that X86 uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "x86-isel"
17 #include "X86InstrBuilder.h"
18 #include "X86ISelLowering.h"
19 #include "X86TargetMachine.h"
20 #include "X86TargetObjectFile.h"
21 #include "Utils/X86ShuffleDecode.h"
22 #include "llvm/CallingConv.h"
23 #include "llvm/Constants.h"
24 #include "llvm/DerivedTypes.h"
25 #include "llvm/GlobalAlias.h"
26 #include "llvm/GlobalVariable.h"
27 #include "llvm/Function.h"
28 #include "llvm/Instructions.h"
29 #include "llvm/Intrinsics.h"
30 #include "llvm/LLVMContext.h"
31 #include "llvm/CodeGen/IntrinsicLowering.h"
32 #include "llvm/CodeGen/MachineFrameInfo.h"
33 #include "llvm/CodeGen/MachineFunction.h"
34 #include "llvm/CodeGen/MachineInstrBuilder.h"
35 #include "llvm/CodeGen/MachineJumpTableInfo.h"
36 #include "llvm/CodeGen/MachineModuleInfo.h"
37 #include "llvm/CodeGen/MachineRegisterInfo.h"
38 #include "llvm/MC/MCAsmInfo.h"
39 #include "llvm/MC/MCContext.h"
40 #include "llvm/MC/MCExpr.h"
41 #include "llvm/MC/MCSymbol.h"
42 #include "llvm/ADT/BitVector.h"
43 #include "llvm/ADT/SmallSet.h"
44 #include "llvm/ADT/Statistic.h"
45 #include "llvm/ADT/StringExtras.h"
46 #include "llvm/ADT/VariadicFunction.h"
47 #include "llvm/Support/CallSite.h"
48 #include "llvm/Support/Debug.h"
49 #include "llvm/Support/Dwarf.h"
50 #include "llvm/Support/ErrorHandling.h"
51 #include "llvm/Support/MathExtras.h"
52 #include "llvm/Support/raw_ostream.h"
53 #include "llvm/Target/TargetOptions.h"
55 using namespace dwarf;
57 STATISTIC(NumTailCalls, "Number of tail calls");
59 // Forward declarations.
60 static SDValue getMOVL(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1,
63 static SDValue Insert128BitVector(SDValue Result,
69 static SDValue Extract128BitVector(SDValue Vec,
74 /// Generate a DAG to grab 128-bits from a vector > 128 bits. This
75 /// sets things up to match to an AVX VEXTRACTF128 instruction or a
76 /// simple subregister reference. Idx is an index in the 128 bits we
77 /// want. It need not be aligned to a 128-bit bounday. That makes
78 /// lowering EXTRACT_VECTOR_ELT operations easier.
79 static SDValue Extract128BitVector(SDValue Vec,
83 EVT VT = Vec.getValueType();
84 assert(VT.getSizeInBits() == 256 && "Unexpected vector size!");
85 EVT ElVT = VT.getVectorElementType();
86 int Factor = VT.getSizeInBits()/128;
87 EVT ResultVT = EVT::getVectorVT(*DAG.getContext(), ElVT,
88 VT.getVectorNumElements()/Factor);
90 // Extract from UNDEF is UNDEF.
91 if (Vec.getOpcode() == ISD::UNDEF)
92 return DAG.getNode(ISD::UNDEF, dl, ResultVT);
94 if (isa<ConstantSDNode>(Idx)) {
95 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
97 // Extract the relevant 128 bits. Generate an EXTRACT_SUBVECTOR
98 // we can match to VEXTRACTF128.
99 unsigned ElemsPerChunk = 128 / ElVT.getSizeInBits();
101 // This is the index of the first element of the 128-bit chunk
103 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits()) / 128)
106 SDValue VecIdx = DAG.getConstant(NormalizedIdxVal, MVT::i32);
107 SDValue Result = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, ResultVT, Vec,
116 /// Generate a DAG to put 128-bits into a vector > 128 bits. This
117 /// sets things up to match to an AVX VINSERTF128 instruction or a
118 /// simple superregister reference. Idx is an index in the 128 bits
119 /// we want. It need not be aligned to a 128-bit bounday. That makes
120 /// lowering INSERT_VECTOR_ELT operations easier.
121 static SDValue Insert128BitVector(SDValue Result,
126 if (isa<ConstantSDNode>(Idx)) {
127 EVT VT = Vec.getValueType();
128 assert(VT.getSizeInBits() == 128 && "Unexpected vector size!");
130 EVT ElVT = VT.getVectorElementType();
131 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
132 EVT ResultVT = Result.getValueType();
134 // Insert the relevant 128 bits.
135 unsigned ElemsPerChunk = 128/ElVT.getSizeInBits();
137 // This is the index of the first element of the 128-bit chunk
139 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits())/128)
142 SDValue VecIdx = DAG.getConstant(NormalizedIdxVal, MVT::i32);
143 Result = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResultVT, Result, Vec,
151 static TargetLoweringObjectFile *createTLOF(X86TargetMachine &TM) {
152 const X86Subtarget *Subtarget = &TM.getSubtarget<X86Subtarget>();
153 bool is64Bit = Subtarget->is64Bit();
155 if (Subtarget->isTargetEnvMacho()) {
157 return new X8664_MachoTargetObjectFile();
158 return new TargetLoweringObjectFileMachO();
161 if (Subtarget->isTargetELF())
162 return new TargetLoweringObjectFileELF();
163 if (Subtarget->isTargetCOFF() && !Subtarget->isTargetEnvMacho())
164 return new TargetLoweringObjectFileCOFF();
165 llvm_unreachable("unknown subtarget type");
168 X86TargetLowering::X86TargetLowering(X86TargetMachine &TM)
169 : TargetLowering(TM, createTLOF(TM)) {
170 Subtarget = &TM.getSubtarget<X86Subtarget>();
171 X86ScalarSSEf64 = Subtarget->hasSSE2();
172 X86ScalarSSEf32 = Subtarget->hasSSE1();
173 X86StackPtr = Subtarget->is64Bit() ? X86::RSP : X86::ESP;
175 RegInfo = TM.getRegisterInfo();
176 TD = getTargetData();
178 // Set up the TargetLowering object.
179 static MVT IntVTs[] = { MVT::i8, MVT::i16, MVT::i32, MVT::i64 };
181 // X86 is weird, it always uses i8 for shift amounts and setcc results.
182 setBooleanContents(ZeroOrOneBooleanContent);
183 // X86-SSE is even stranger. It uses -1 or 0 for vector masks.
184 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
186 // For 64-bit since we have so many registers use the ILP scheduler, for
187 // 32-bit code use the register pressure specific scheduling.
188 if (Subtarget->is64Bit())
189 setSchedulingPreference(Sched::ILP);
191 setSchedulingPreference(Sched::RegPressure);
192 setStackPointerRegisterToSaveRestore(X86StackPtr);
194 if (Subtarget->isTargetWindows() && !Subtarget->isTargetCygMing()) {
195 // Setup Windows compiler runtime calls.
196 setLibcallName(RTLIB::SDIV_I64, "_alldiv");
197 setLibcallName(RTLIB::UDIV_I64, "_aulldiv");
198 setLibcallName(RTLIB::SREM_I64, "_allrem");
199 setLibcallName(RTLIB::UREM_I64, "_aullrem");
200 setLibcallName(RTLIB::MUL_I64, "_allmul");
201 setLibcallName(RTLIB::FPTOUINT_F64_I64, "_ftol2");
202 setLibcallName(RTLIB::FPTOUINT_F32_I64, "_ftol2");
203 setLibcallCallingConv(RTLIB::SDIV_I64, CallingConv::X86_StdCall);
204 setLibcallCallingConv(RTLIB::UDIV_I64, CallingConv::X86_StdCall);
205 setLibcallCallingConv(RTLIB::SREM_I64, CallingConv::X86_StdCall);
206 setLibcallCallingConv(RTLIB::UREM_I64, CallingConv::X86_StdCall);
207 setLibcallCallingConv(RTLIB::MUL_I64, CallingConv::X86_StdCall);
208 setLibcallCallingConv(RTLIB::FPTOUINT_F64_I64, CallingConv::C);
209 setLibcallCallingConv(RTLIB::FPTOUINT_F32_I64, CallingConv::C);
212 if (Subtarget->isTargetDarwin()) {
213 // Darwin should use _setjmp/_longjmp instead of setjmp/longjmp.
214 setUseUnderscoreSetJmp(false);
215 setUseUnderscoreLongJmp(false);
216 } else if (Subtarget->isTargetMingw()) {
217 // MS runtime is weird: it exports _setjmp, but longjmp!
218 setUseUnderscoreSetJmp(true);
219 setUseUnderscoreLongJmp(false);
221 setUseUnderscoreSetJmp(true);
222 setUseUnderscoreLongJmp(true);
225 // Set up the register classes.
226 addRegisterClass(MVT::i8, X86::GR8RegisterClass);
227 addRegisterClass(MVT::i16, X86::GR16RegisterClass);
228 addRegisterClass(MVT::i32, X86::GR32RegisterClass);
229 if (Subtarget->is64Bit())
230 addRegisterClass(MVT::i64, X86::GR64RegisterClass);
232 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
234 // We don't accept any truncstore of integer registers.
235 setTruncStoreAction(MVT::i64, MVT::i32, Expand);
236 setTruncStoreAction(MVT::i64, MVT::i16, Expand);
237 setTruncStoreAction(MVT::i64, MVT::i8 , Expand);
238 setTruncStoreAction(MVT::i32, MVT::i16, Expand);
239 setTruncStoreAction(MVT::i32, MVT::i8 , Expand);
240 setTruncStoreAction(MVT::i16, MVT::i8, Expand);
242 // SETOEQ and SETUNE require checking two conditions.
243 setCondCodeAction(ISD::SETOEQ, MVT::f32, Expand);
244 setCondCodeAction(ISD::SETOEQ, MVT::f64, Expand);
245 setCondCodeAction(ISD::SETOEQ, MVT::f80, Expand);
246 setCondCodeAction(ISD::SETUNE, MVT::f32, Expand);
247 setCondCodeAction(ISD::SETUNE, MVT::f64, Expand);
248 setCondCodeAction(ISD::SETUNE, MVT::f80, Expand);
250 // Promote all UINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have this
252 setOperationAction(ISD::UINT_TO_FP , MVT::i1 , Promote);
253 setOperationAction(ISD::UINT_TO_FP , MVT::i8 , Promote);
254 setOperationAction(ISD::UINT_TO_FP , MVT::i16 , Promote);
256 if (Subtarget->is64Bit()) {
257 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote);
258 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
259 } else if (!TM.Options.UseSoftFloat) {
260 // We have an algorithm for SSE2->double, and we turn this into a
261 // 64-bit FILD followed by conditional FADD for other targets.
262 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
263 // We have an algorithm for SSE2, and we turn this into a 64-bit
264 // FILD for other targets.
265 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Custom);
268 // Promote i1/i8 SINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have
270 setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote);
271 setOperationAction(ISD::SINT_TO_FP , MVT::i8 , Promote);
273 if (!TM.Options.UseSoftFloat) {
274 // SSE has no i16 to fp conversion, only i32
275 if (X86ScalarSSEf32) {
276 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
277 // f32 and f64 cases are Legal, f80 case is not
278 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
280 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Custom);
281 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
284 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
285 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Promote);
288 // In 32-bit mode these are custom lowered. In 64-bit mode F32 and F64
289 // are Legal, f80 is custom lowered.
290 setOperationAction(ISD::FP_TO_SINT , MVT::i64 , Custom);
291 setOperationAction(ISD::SINT_TO_FP , MVT::i64 , Custom);
293 // Promote i1/i8 FP_TO_SINT to larger FP_TO_SINTS's, as X86 doesn't have
295 setOperationAction(ISD::FP_TO_SINT , MVT::i1 , Promote);
296 setOperationAction(ISD::FP_TO_SINT , MVT::i8 , Promote);
298 if (X86ScalarSSEf32) {
299 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Promote);
300 // f32 and f64 cases are Legal, f80 case is not
301 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
303 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Custom);
304 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
307 // Handle FP_TO_UINT by promoting the destination to a larger signed
309 setOperationAction(ISD::FP_TO_UINT , MVT::i1 , Promote);
310 setOperationAction(ISD::FP_TO_UINT , MVT::i8 , Promote);
311 setOperationAction(ISD::FP_TO_UINT , MVT::i16 , Promote);
313 if (Subtarget->is64Bit()) {
314 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Expand);
315 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote);
316 } else if (!TM.Options.UseSoftFloat) {
317 // Since AVX is a superset of SSE3, only check for SSE here.
318 if (Subtarget->hasSSE1() && !Subtarget->hasSSE3())
319 // Expand FP_TO_UINT into a select.
320 // FIXME: We would like to use a Custom expander here eventually to do
321 // the optimal thing for SSE vs. the default expansion in the legalizer.
322 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Expand);
324 // With SSE3 we can use fisttpll to convert to a signed i64; without
325 // SSE, we're stuck with a fistpll.
326 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Custom);
329 // TODO: when we have SSE, these could be more efficient, by using movd/movq.
330 if (!X86ScalarSSEf64) {
331 setOperationAction(ISD::BITCAST , MVT::f32 , Expand);
332 setOperationAction(ISD::BITCAST , MVT::i32 , Expand);
333 if (Subtarget->is64Bit()) {
334 setOperationAction(ISD::BITCAST , MVT::f64 , Expand);
335 // Without SSE, i64->f64 goes through memory.
336 setOperationAction(ISD::BITCAST , MVT::i64 , Expand);
340 // Scalar integer divide and remainder are lowered to use operations that
341 // produce two results, to match the available instructions. This exposes
342 // the two-result form to trivial CSE, which is able to combine x/y and x%y
343 // into a single instruction.
345 // Scalar integer multiply-high is also lowered to use two-result
346 // operations, to match the available instructions. However, plain multiply
347 // (low) operations are left as Legal, as there are single-result
348 // instructions for this in x86. Using the two-result multiply instructions
349 // when both high and low results are needed must be arranged by dagcombine.
350 for (unsigned i = 0, e = 4; i != e; ++i) {
352 setOperationAction(ISD::MULHS, VT, Expand);
353 setOperationAction(ISD::MULHU, VT, Expand);
354 setOperationAction(ISD::SDIV, VT, Expand);
355 setOperationAction(ISD::UDIV, VT, Expand);
356 setOperationAction(ISD::SREM, VT, Expand);
357 setOperationAction(ISD::UREM, VT, Expand);
359 // Add/Sub overflow ops with MVT::Glues are lowered to EFLAGS dependences.
360 setOperationAction(ISD::ADDC, VT, Custom);
361 setOperationAction(ISD::ADDE, VT, Custom);
362 setOperationAction(ISD::SUBC, VT, Custom);
363 setOperationAction(ISD::SUBE, VT, Custom);
366 setOperationAction(ISD::BR_JT , MVT::Other, Expand);
367 setOperationAction(ISD::BRCOND , MVT::Other, Custom);
368 setOperationAction(ISD::BR_CC , MVT::Other, Expand);
369 setOperationAction(ISD::SELECT_CC , MVT::Other, Expand);
370 if (Subtarget->is64Bit())
371 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal);
372 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Legal);
373 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Legal);
374 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
375 setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand);
376 setOperationAction(ISD::FREM , MVT::f32 , Expand);
377 setOperationAction(ISD::FREM , MVT::f64 , Expand);
378 setOperationAction(ISD::FREM , MVT::f80 , Expand);
379 setOperationAction(ISD::FLT_ROUNDS_ , MVT::i32 , Custom);
381 // Promote the i8 variants and force them on up to i32 which has a shorter
383 setOperationAction(ISD::CTTZ , MVT::i8 , Promote);
384 AddPromotedToType (ISD::CTTZ , MVT::i8 , MVT::i32);
385 setOperationAction(ISD::CTTZ_ZERO_UNDEF , MVT::i8 , Promote);
386 AddPromotedToType (ISD::CTTZ_ZERO_UNDEF , MVT::i8 , MVT::i32);
387 if (Subtarget->hasBMI()) {
388 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i16 , Expand);
389 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32 , Expand);
390 if (Subtarget->is64Bit())
391 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand);
393 setOperationAction(ISD::CTTZ , MVT::i16 , Custom);
394 setOperationAction(ISD::CTTZ , MVT::i32 , Custom);
395 if (Subtarget->is64Bit())
396 setOperationAction(ISD::CTTZ , MVT::i64 , Custom);
399 if (Subtarget->hasLZCNT()) {
400 // When promoting the i8 variants, force them to i32 for a shorter
402 setOperationAction(ISD::CTLZ , MVT::i8 , Promote);
403 AddPromotedToType (ISD::CTLZ , MVT::i8 , MVT::i32);
404 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Promote);
405 AddPromotedToType (ISD::CTLZ_ZERO_UNDEF, MVT::i8 , MVT::i32);
406 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Expand);
407 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Expand);
408 if (Subtarget->is64Bit())
409 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Expand);
411 setOperationAction(ISD::CTLZ , MVT::i8 , Custom);
412 setOperationAction(ISD::CTLZ , MVT::i16 , Custom);
413 setOperationAction(ISD::CTLZ , MVT::i32 , Custom);
414 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Custom);
415 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Custom);
416 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Custom);
417 if (Subtarget->is64Bit()) {
418 setOperationAction(ISD::CTLZ , MVT::i64 , Custom);
419 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Custom);
423 if (Subtarget->hasPOPCNT()) {
424 setOperationAction(ISD::CTPOP , MVT::i8 , Promote);
426 setOperationAction(ISD::CTPOP , MVT::i8 , Expand);
427 setOperationAction(ISD::CTPOP , MVT::i16 , Expand);
428 setOperationAction(ISD::CTPOP , MVT::i32 , Expand);
429 if (Subtarget->is64Bit())
430 setOperationAction(ISD::CTPOP , MVT::i64 , Expand);
433 setOperationAction(ISD::READCYCLECOUNTER , MVT::i64 , Custom);
434 setOperationAction(ISD::BSWAP , MVT::i16 , Expand);
436 // These should be promoted to a larger select which is supported.
437 setOperationAction(ISD::SELECT , MVT::i1 , Promote);
438 // X86 wants to expand cmov itself.
439 setOperationAction(ISD::SELECT , MVT::i8 , Custom);
440 setOperationAction(ISD::SELECT , MVT::i16 , Custom);
441 setOperationAction(ISD::SELECT , MVT::i32 , Custom);
442 setOperationAction(ISD::SELECT , MVT::f32 , Custom);
443 setOperationAction(ISD::SELECT , MVT::f64 , Custom);
444 setOperationAction(ISD::SELECT , MVT::f80 , Custom);
445 setOperationAction(ISD::SETCC , MVT::i8 , Custom);
446 setOperationAction(ISD::SETCC , MVT::i16 , Custom);
447 setOperationAction(ISD::SETCC , MVT::i32 , Custom);
448 setOperationAction(ISD::SETCC , MVT::f32 , Custom);
449 setOperationAction(ISD::SETCC , MVT::f64 , Custom);
450 setOperationAction(ISD::SETCC , MVT::f80 , Custom);
451 if (Subtarget->is64Bit()) {
452 setOperationAction(ISD::SELECT , MVT::i64 , Custom);
453 setOperationAction(ISD::SETCC , MVT::i64 , Custom);
455 setOperationAction(ISD::EH_RETURN , MVT::Other, Custom);
458 setOperationAction(ISD::ConstantPool , MVT::i32 , Custom);
459 setOperationAction(ISD::JumpTable , MVT::i32 , Custom);
460 setOperationAction(ISD::GlobalAddress , MVT::i32 , Custom);
461 setOperationAction(ISD::GlobalTLSAddress, MVT::i32 , Custom);
462 if (Subtarget->is64Bit())
463 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
464 setOperationAction(ISD::ExternalSymbol , MVT::i32 , Custom);
465 setOperationAction(ISD::BlockAddress , MVT::i32 , Custom);
466 if (Subtarget->is64Bit()) {
467 setOperationAction(ISD::ConstantPool , MVT::i64 , Custom);
468 setOperationAction(ISD::JumpTable , MVT::i64 , Custom);
469 setOperationAction(ISD::GlobalAddress , MVT::i64 , Custom);
470 setOperationAction(ISD::ExternalSymbol, MVT::i64 , Custom);
471 setOperationAction(ISD::BlockAddress , MVT::i64 , Custom);
473 // 64-bit addm sub, shl, sra, srl (iff 32-bit x86)
474 setOperationAction(ISD::SHL_PARTS , MVT::i32 , Custom);
475 setOperationAction(ISD::SRA_PARTS , MVT::i32 , Custom);
476 setOperationAction(ISD::SRL_PARTS , MVT::i32 , Custom);
477 if (Subtarget->is64Bit()) {
478 setOperationAction(ISD::SHL_PARTS , MVT::i64 , Custom);
479 setOperationAction(ISD::SRA_PARTS , MVT::i64 , Custom);
480 setOperationAction(ISD::SRL_PARTS , MVT::i64 , Custom);
483 if (Subtarget->hasSSE1())
484 setOperationAction(ISD::PREFETCH , MVT::Other, Legal);
486 setOperationAction(ISD::MEMBARRIER , MVT::Other, Custom);
487 setOperationAction(ISD::ATOMIC_FENCE , MVT::Other, Custom);
489 // On X86 and X86-64, atomic operations are lowered to locked instructions.
490 // Locked instructions, in turn, have implicit fence semantics (all memory
491 // operations are flushed before issuing the locked instruction, and they
492 // are not buffered), so we can fold away the common pattern of
493 // fence-atomic-fence.
494 setShouldFoldAtomicFences(true);
496 // Expand certain atomics
497 for (unsigned i = 0, e = 4; i != e; ++i) {
499 setOperationAction(ISD::ATOMIC_CMP_SWAP, VT, Custom);
500 setOperationAction(ISD::ATOMIC_LOAD_SUB, VT, Custom);
501 setOperationAction(ISD::ATOMIC_STORE, VT, Custom);
504 if (!Subtarget->is64Bit()) {
505 setOperationAction(ISD::ATOMIC_LOAD, MVT::i64, Custom);
506 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i64, Custom);
507 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i64, Custom);
508 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i64, Custom);
509 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i64, Custom);
510 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i64, Custom);
511 setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i64, Custom);
512 setOperationAction(ISD::ATOMIC_SWAP, MVT::i64, Custom);
515 if (Subtarget->hasCmpxchg16b()) {
516 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i128, Custom);
519 // FIXME - use subtarget debug flags
520 if (!Subtarget->isTargetDarwin() &&
521 !Subtarget->isTargetELF() &&
522 !Subtarget->isTargetCygMing()) {
523 setOperationAction(ISD::EH_LABEL, MVT::Other, Expand);
526 setOperationAction(ISD::EXCEPTIONADDR, MVT::i64, Expand);
527 setOperationAction(ISD::EHSELECTION, MVT::i64, Expand);
528 setOperationAction(ISD::EXCEPTIONADDR, MVT::i32, Expand);
529 setOperationAction(ISD::EHSELECTION, MVT::i32, Expand);
530 if (Subtarget->is64Bit()) {
531 setExceptionPointerRegister(X86::RAX);
532 setExceptionSelectorRegister(X86::RDX);
534 setExceptionPointerRegister(X86::EAX);
535 setExceptionSelectorRegister(X86::EDX);
537 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i32, Custom);
538 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i64, Custom);
540 setOperationAction(ISD::INIT_TRAMPOLINE, MVT::Other, Custom);
541 setOperationAction(ISD::ADJUST_TRAMPOLINE, MVT::Other, Custom);
543 setOperationAction(ISD::TRAP, MVT::Other, Legal);
545 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
546 setOperationAction(ISD::VASTART , MVT::Other, Custom);
547 setOperationAction(ISD::VAEND , MVT::Other, Expand);
548 if (Subtarget->is64Bit()) {
549 setOperationAction(ISD::VAARG , MVT::Other, Custom);
550 setOperationAction(ISD::VACOPY , MVT::Other, Custom);
552 setOperationAction(ISD::VAARG , MVT::Other, Expand);
553 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
556 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
557 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
559 if (Subtarget->isTargetCOFF() && !Subtarget->isTargetEnvMacho())
560 setOperationAction(ISD::DYNAMIC_STACKALLOC, Subtarget->is64Bit() ?
561 MVT::i64 : MVT::i32, Custom);
562 else if (TM.Options.EnableSegmentedStacks)
563 setOperationAction(ISD::DYNAMIC_STACKALLOC, Subtarget->is64Bit() ?
564 MVT::i64 : MVT::i32, Custom);
566 setOperationAction(ISD::DYNAMIC_STACKALLOC, Subtarget->is64Bit() ?
567 MVT::i64 : MVT::i32, Expand);
569 if (!TM.Options.UseSoftFloat && X86ScalarSSEf64) {
570 // f32 and f64 use SSE.
571 // Set up the FP register classes.
572 addRegisterClass(MVT::f32, X86::FR32RegisterClass);
573 addRegisterClass(MVT::f64, X86::FR64RegisterClass);
575 // Use ANDPD to simulate FABS.
576 setOperationAction(ISD::FABS , MVT::f64, Custom);
577 setOperationAction(ISD::FABS , MVT::f32, Custom);
579 // Use XORP to simulate FNEG.
580 setOperationAction(ISD::FNEG , MVT::f64, Custom);
581 setOperationAction(ISD::FNEG , MVT::f32, Custom);
583 // Use ANDPD and ORPD to simulate FCOPYSIGN.
584 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
585 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
587 // Lower this to FGETSIGNx86 plus an AND.
588 setOperationAction(ISD::FGETSIGN, MVT::i64, Custom);
589 setOperationAction(ISD::FGETSIGN, MVT::i32, Custom);
591 // We don't support sin/cos/fmod
592 setOperationAction(ISD::FSIN , MVT::f64, Expand);
593 setOperationAction(ISD::FCOS , MVT::f64, Expand);
594 setOperationAction(ISD::FSIN , MVT::f32, Expand);
595 setOperationAction(ISD::FCOS , MVT::f32, Expand);
597 // Expand FP immediates into loads from the stack, except for the special
599 addLegalFPImmediate(APFloat(+0.0)); // xorpd
600 addLegalFPImmediate(APFloat(+0.0f)); // xorps
601 } else if (!TM.Options.UseSoftFloat && X86ScalarSSEf32) {
602 // Use SSE for f32, x87 for f64.
603 // Set up the FP register classes.
604 addRegisterClass(MVT::f32, X86::FR32RegisterClass);
605 addRegisterClass(MVT::f64, X86::RFP64RegisterClass);
607 // Use ANDPS to simulate FABS.
608 setOperationAction(ISD::FABS , MVT::f32, Custom);
610 // Use XORP to simulate FNEG.
611 setOperationAction(ISD::FNEG , MVT::f32, Custom);
613 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
615 // Use ANDPS and ORPS to simulate FCOPYSIGN.
616 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
617 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
619 // We don't support sin/cos/fmod
620 setOperationAction(ISD::FSIN , MVT::f32, Expand);
621 setOperationAction(ISD::FCOS , MVT::f32, Expand);
623 // Special cases we handle for FP constants.
624 addLegalFPImmediate(APFloat(+0.0f)); // xorps
625 addLegalFPImmediate(APFloat(+0.0)); // FLD0
626 addLegalFPImmediate(APFloat(+1.0)); // FLD1
627 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
628 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
630 if (!TM.Options.UnsafeFPMath) {
631 setOperationAction(ISD::FSIN , MVT::f64 , Expand);
632 setOperationAction(ISD::FCOS , MVT::f64 , Expand);
634 } else if (!TM.Options.UseSoftFloat) {
635 // f32 and f64 in x87.
636 // Set up the FP register classes.
637 addRegisterClass(MVT::f64, X86::RFP64RegisterClass);
638 addRegisterClass(MVT::f32, X86::RFP32RegisterClass);
640 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
641 setOperationAction(ISD::UNDEF, MVT::f32, Expand);
642 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
643 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
645 if (!TM.Options.UnsafeFPMath) {
646 setOperationAction(ISD::FSIN , MVT::f64 , Expand);
647 setOperationAction(ISD::FCOS , MVT::f64 , Expand);
649 addLegalFPImmediate(APFloat(+0.0)); // FLD0
650 addLegalFPImmediate(APFloat(+1.0)); // FLD1
651 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
652 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
653 addLegalFPImmediate(APFloat(+0.0f)); // FLD0
654 addLegalFPImmediate(APFloat(+1.0f)); // FLD1
655 addLegalFPImmediate(APFloat(-0.0f)); // FLD0/FCHS
656 addLegalFPImmediate(APFloat(-1.0f)); // FLD1/FCHS
659 // We don't support FMA.
660 setOperationAction(ISD::FMA, MVT::f64, Expand);
661 setOperationAction(ISD::FMA, MVT::f32, Expand);
663 // Long double always uses X87.
664 if (!TM.Options.UseSoftFloat) {
665 addRegisterClass(MVT::f80, X86::RFP80RegisterClass);
666 setOperationAction(ISD::UNDEF, MVT::f80, Expand);
667 setOperationAction(ISD::FCOPYSIGN, MVT::f80, Expand);
669 APFloat TmpFlt = APFloat::getZero(APFloat::x87DoubleExtended);
670 addLegalFPImmediate(TmpFlt); // FLD0
672 addLegalFPImmediate(TmpFlt); // FLD0/FCHS
675 APFloat TmpFlt2(+1.0);
676 TmpFlt2.convert(APFloat::x87DoubleExtended, APFloat::rmNearestTiesToEven,
678 addLegalFPImmediate(TmpFlt2); // FLD1
679 TmpFlt2.changeSign();
680 addLegalFPImmediate(TmpFlt2); // FLD1/FCHS
683 if (!TM.Options.UnsafeFPMath) {
684 setOperationAction(ISD::FSIN , MVT::f80 , Expand);
685 setOperationAction(ISD::FCOS , MVT::f80 , Expand);
688 setOperationAction(ISD::FFLOOR, MVT::f80, Expand);
689 setOperationAction(ISD::FCEIL, MVT::f80, Expand);
690 setOperationAction(ISD::FTRUNC, MVT::f80, Expand);
691 setOperationAction(ISD::FRINT, MVT::f80, Expand);
692 setOperationAction(ISD::FNEARBYINT, MVT::f80, Expand);
693 setOperationAction(ISD::FMA, MVT::f80, Expand);
696 // Always use a library call for pow.
697 setOperationAction(ISD::FPOW , MVT::f32 , Expand);
698 setOperationAction(ISD::FPOW , MVT::f64 , Expand);
699 setOperationAction(ISD::FPOW , MVT::f80 , Expand);
701 setOperationAction(ISD::FLOG, MVT::f80, Expand);
702 setOperationAction(ISD::FLOG2, MVT::f80, Expand);
703 setOperationAction(ISD::FLOG10, MVT::f80, Expand);
704 setOperationAction(ISD::FEXP, MVT::f80, Expand);
705 setOperationAction(ISD::FEXP2, MVT::f80, Expand);
707 // First set operation action for all vector types to either promote
708 // (for widening) or expand (for scalarization). Then we will selectively
709 // turn on ones that can be effectively codegen'd.
710 for (unsigned VT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
711 VT <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++VT) {
712 setOperationAction(ISD::ADD , (MVT::SimpleValueType)VT, Expand);
713 setOperationAction(ISD::SUB , (MVT::SimpleValueType)VT, Expand);
714 setOperationAction(ISD::FADD, (MVT::SimpleValueType)VT, Expand);
715 setOperationAction(ISD::FNEG, (MVT::SimpleValueType)VT, Expand);
716 setOperationAction(ISD::FSUB, (MVT::SimpleValueType)VT, Expand);
717 setOperationAction(ISD::MUL , (MVT::SimpleValueType)VT, Expand);
718 setOperationAction(ISD::FMUL, (MVT::SimpleValueType)VT, Expand);
719 setOperationAction(ISD::SDIV, (MVT::SimpleValueType)VT, Expand);
720 setOperationAction(ISD::UDIV, (MVT::SimpleValueType)VT, Expand);
721 setOperationAction(ISD::FDIV, (MVT::SimpleValueType)VT, Expand);
722 setOperationAction(ISD::SREM, (MVT::SimpleValueType)VT, Expand);
723 setOperationAction(ISD::UREM, (MVT::SimpleValueType)VT, Expand);
724 setOperationAction(ISD::LOAD, (MVT::SimpleValueType)VT, Expand);
725 setOperationAction(ISD::VECTOR_SHUFFLE, (MVT::SimpleValueType)VT, Expand);
726 setOperationAction(ISD::EXTRACT_VECTOR_ELT,(MVT::SimpleValueType)VT,Expand);
727 setOperationAction(ISD::INSERT_VECTOR_ELT,(MVT::SimpleValueType)VT, Expand);
728 setOperationAction(ISD::EXTRACT_SUBVECTOR,(MVT::SimpleValueType)VT,Expand);
729 setOperationAction(ISD::INSERT_SUBVECTOR,(MVT::SimpleValueType)VT,Expand);
730 setOperationAction(ISD::FABS, (MVT::SimpleValueType)VT, Expand);
731 setOperationAction(ISD::FSIN, (MVT::SimpleValueType)VT, Expand);
732 setOperationAction(ISD::FCOS, (MVT::SimpleValueType)VT, Expand);
733 setOperationAction(ISD::FREM, (MVT::SimpleValueType)VT, Expand);
734 setOperationAction(ISD::FPOWI, (MVT::SimpleValueType)VT, Expand);
735 setOperationAction(ISD::FSQRT, (MVT::SimpleValueType)VT, Expand);
736 setOperationAction(ISD::FCOPYSIGN, (MVT::SimpleValueType)VT, Expand);
737 setOperationAction(ISD::SMUL_LOHI, (MVT::SimpleValueType)VT, Expand);
738 setOperationAction(ISD::UMUL_LOHI, (MVT::SimpleValueType)VT, Expand);
739 setOperationAction(ISD::SDIVREM, (MVT::SimpleValueType)VT, Expand);
740 setOperationAction(ISD::UDIVREM, (MVT::SimpleValueType)VT, Expand);
741 setOperationAction(ISD::FPOW, (MVT::SimpleValueType)VT, Expand);
742 setOperationAction(ISD::CTPOP, (MVT::SimpleValueType)VT, Expand);
743 setOperationAction(ISD::CTTZ, (MVT::SimpleValueType)VT, Expand);
744 setOperationAction(ISD::CTTZ_ZERO_UNDEF, (MVT::SimpleValueType)VT, Expand);
745 setOperationAction(ISD::CTLZ, (MVT::SimpleValueType)VT, Expand);
746 setOperationAction(ISD::CTLZ_ZERO_UNDEF, (MVT::SimpleValueType)VT, Expand);
747 setOperationAction(ISD::SHL, (MVT::SimpleValueType)VT, Expand);
748 setOperationAction(ISD::SRA, (MVT::SimpleValueType)VT, Expand);
749 setOperationAction(ISD::SRL, (MVT::SimpleValueType)VT, Expand);
750 setOperationAction(ISD::ROTL, (MVT::SimpleValueType)VT, Expand);
751 setOperationAction(ISD::ROTR, (MVT::SimpleValueType)VT, Expand);
752 setOperationAction(ISD::BSWAP, (MVT::SimpleValueType)VT, Expand);
753 setOperationAction(ISD::SETCC, (MVT::SimpleValueType)VT, Expand);
754 setOperationAction(ISD::FLOG, (MVT::SimpleValueType)VT, Expand);
755 setOperationAction(ISD::FLOG2, (MVT::SimpleValueType)VT, Expand);
756 setOperationAction(ISD::FLOG10, (MVT::SimpleValueType)VT, Expand);
757 setOperationAction(ISD::FEXP, (MVT::SimpleValueType)VT, Expand);
758 setOperationAction(ISD::FEXP2, (MVT::SimpleValueType)VT, Expand);
759 setOperationAction(ISD::FP_TO_UINT, (MVT::SimpleValueType)VT, Expand);
760 setOperationAction(ISD::FP_TO_SINT, (MVT::SimpleValueType)VT, Expand);
761 setOperationAction(ISD::UINT_TO_FP, (MVT::SimpleValueType)VT, Expand);
762 setOperationAction(ISD::SINT_TO_FP, (MVT::SimpleValueType)VT, Expand);
763 setOperationAction(ISD::SIGN_EXTEND_INREG, (MVT::SimpleValueType)VT,Expand);
764 setOperationAction(ISD::TRUNCATE, (MVT::SimpleValueType)VT, Expand);
765 setOperationAction(ISD::SIGN_EXTEND, (MVT::SimpleValueType)VT, Expand);
766 setOperationAction(ISD::ZERO_EXTEND, (MVT::SimpleValueType)VT, Expand);
767 setOperationAction(ISD::ANY_EXTEND, (MVT::SimpleValueType)VT, Expand);
768 setOperationAction(ISD::VSELECT, (MVT::SimpleValueType)VT, Expand);
769 for (unsigned InnerVT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
770 InnerVT <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++InnerVT)
771 setTruncStoreAction((MVT::SimpleValueType)VT,
772 (MVT::SimpleValueType)InnerVT, Expand);
773 setLoadExtAction(ISD::SEXTLOAD, (MVT::SimpleValueType)VT, Expand);
774 setLoadExtAction(ISD::ZEXTLOAD, (MVT::SimpleValueType)VT, Expand);
775 setLoadExtAction(ISD::EXTLOAD, (MVT::SimpleValueType)VT, Expand);
778 // FIXME: In order to prevent SSE instructions being expanded to MMX ones
779 // with -msoft-float, disable use of MMX as well.
780 if (!TM.Options.UseSoftFloat && Subtarget->hasMMX()) {
781 addRegisterClass(MVT::x86mmx, X86::VR64RegisterClass);
782 // No operations on x86mmx supported, everything uses intrinsics.
785 // MMX-sized vectors (other than x86mmx) are expected to be expanded
786 // into smaller operations.
787 setOperationAction(ISD::MULHS, MVT::v8i8, Expand);
788 setOperationAction(ISD::MULHS, MVT::v4i16, Expand);
789 setOperationAction(ISD::MULHS, MVT::v2i32, Expand);
790 setOperationAction(ISD::MULHS, MVT::v1i64, Expand);
791 setOperationAction(ISD::AND, MVT::v8i8, Expand);
792 setOperationAction(ISD::AND, MVT::v4i16, Expand);
793 setOperationAction(ISD::AND, MVT::v2i32, Expand);
794 setOperationAction(ISD::AND, MVT::v1i64, Expand);
795 setOperationAction(ISD::OR, MVT::v8i8, Expand);
796 setOperationAction(ISD::OR, MVT::v4i16, Expand);
797 setOperationAction(ISD::OR, MVT::v2i32, Expand);
798 setOperationAction(ISD::OR, MVT::v1i64, Expand);
799 setOperationAction(ISD::XOR, MVT::v8i8, Expand);
800 setOperationAction(ISD::XOR, MVT::v4i16, Expand);
801 setOperationAction(ISD::XOR, MVT::v2i32, Expand);
802 setOperationAction(ISD::XOR, MVT::v1i64, Expand);
803 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i8, Expand);
804 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i16, Expand);
805 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2i32, Expand);
806 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v1i64, Expand);
807 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v1i64, Expand);
808 setOperationAction(ISD::SELECT, MVT::v8i8, Expand);
809 setOperationAction(ISD::SELECT, MVT::v4i16, Expand);
810 setOperationAction(ISD::SELECT, MVT::v2i32, Expand);
811 setOperationAction(ISD::SELECT, MVT::v1i64, Expand);
812 setOperationAction(ISD::BITCAST, MVT::v8i8, Expand);
813 setOperationAction(ISD::BITCAST, MVT::v4i16, Expand);
814 setOperationAction(ISD::BITCAST, MVT::v2i32, Expand);
815 setOperationAction(ISD::BITCAST, MVT::v1i64, Expand);
817 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE1()) {
818 addRegisterClass(MVT::v4f32, X86::VR128RegisterClass);
820 setOperationAction(ISD::FADD, MVT::v4f32, Legal);
821 setOperationAction(ISD::FSUB, MVT::v4f32, Legal);
822 setOperationAction(ISD::FMUL, MVT::v4f32, Legal);
823 setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
824 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal);
825 setOperationAction(ISD::FNEG, MVT::v4f32, Custom);
826 setOperationAction(ISD::LOAD, MVT::v4f32, Legal);
827 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
828 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f32, Custom);
829 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
830 setOperationAction(ISD::SELECT, MVT::v4f32, Custom);
831 setOperationAction(ISD::SETCC, MVT::v4f32, Custom);
834 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE2()) {
835 addRegisterClass(MVT::v2f64, X86::VR128RegisterClass);
837 // FIXME: Unfortunately -soft-float and -no-implicit-float means XMM
838 // registers cannot be used even for integer operations.
839 addRegisterClass(MVT::v16i8, X86::VR128RegisterClass);
840 addRegisterClass(MVT::v8i16, X86::VR128RegisterClass);
841 addRegisterClass(MVT::v4i32, X86::VR128RegisterClass);
842 addRegisterClass(MVT::v2i64, X86::VR128RegisterClass);
844 setOperationAction(ISD::ADD, MVT::v16i8, Legal);
845 setOperationAction(ISD::ADD, MVT::v8i16, Legal);
846 setOperationAction(ISD::ADD, MVT::v4i32, Legal);
847 setOperationAction(ISD::ADD, MVT::v2i64, Legal);
848 setOperationAction(ISD::MUL, MVT::v2i64, Custom);
849 setOperationAction(ISD::SUB, MVT::v16i8, Legal);
850 setOperationAction(ISD::SUB, MVT::v8i16, Legal);
851 setOperationAction(ISD::SUB, MVT::v4i32, Legal);
852 setOperationAction(ISD::SUB, MVT::v2i64, Legal);
853 setOperationAction(ISD::MUL, MVT::v8i16, Legal);
854 setOperationAction(ISD::FADD, MVT::v2f64, Legal);
855 setOperationAction(ISD::FSUB, MVT::v2f64, Legal);
856 setOperationAction(ISD::FMUL, MVT::v2f64, Legal);
857 setOperationAction(ISD::FDIV, MVT::v2f64, Legal);
858 setOperationAction(ISD::FSQRT, MVT::v2f64, Legal);
859 setOperationAction(ISD::FNEG, MVT::v2f64, Custom);
861 setOperationAction(ISD::SETCC, MVT::v2i64, Custom);
862 setOperationAction(ISD::SETCC, MVT::v16i8, Custom);
863 setOperationAction(ISD::SETCC, MVT::v8i16, Custom);
864 setOperationAction(ISD::SETCC, MVT::v4i32, Custom);
866 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Custom);
867 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Custom);
868 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
869 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
870 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
872 setOperationAction(ISD::CONCAT_VECTORS, MVT::v2f64, Custom);
873 setOperationAction(ISD::CONCAT_VECTORS, MVT::v2i64, Custom);
874 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i8, Custom);
875 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i16, Custom);
876 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4i32, Custom);
878 // Custom lower build_vector, vector_shuffle, and extract_vector_elt.
879 for (unsigned i = (unsigned)MVT::v16i8; i != (unsigned)MVT::v2i64; ++i) {
880 EVT VT = (MVT::SimpleValueType)i;
881 // Do not attempt to custom lower non-power-of-2 vectors
882 if (!isPowerOf2_32(VT.getVectorNumElements()))
884 // Do not attempt to custom lower non-128-bit vectors
885 if (!VT.is128BitVector())
887 setOperationAction(ISD::BUILD_VECTOR,
888 VT.getSimpleVT().SimpleTy, Custom);
889 setOperationAction(ISD::VECTOR_SHUFFLE,
890 VT.getSimpleVT().SimpleTy, Custom);
891 setOperationAction(ISD::EXTRACT_VECTOR_ELT,
892 VT.getSimpleVT().SimpleTy, Custom);
895 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f64, Custom);
896 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i64, Custom);
897 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Custom);
898 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Custom);
899 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f64, Custom);
900 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Custom);
902 if (Subtarget->is64Bit()) {
903 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
904 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
907 // Promote v16i8, v8i16, v4i32 load, select, and, or, xor to v2i64.
908 for (unsigned i = (unsigned)MVT::v16i8; i != (unsigned)MVT::v2i64; i++) {
909 MVT::SimpleValueType SVT = (MVT::SimpleValueType)i;
912 // Do not attempt to promote non-128-bit vectors
913 if (!VT.is128BitVector())
916 setOperationAction(ISD::AND, SVT, Promote);
917 AddPromotedToType (ISD::AND, SVT, MVT::v2i64);
918 setOperationAction(ISD::OR, SVT, Promote);
919 AddPromotedToType (ISD::OR, SVT, MVT::v2i64);
920 setOperationAction(ISD::XOR, SVT, Promote);
921 AddPromotedToType (ISD::XOR, SVT, MVT::v2i64);
922 setOperationAction(ISD::LOAD, SVT, Promote);
923 AddPromotedToType (ISD::LOAD, SVT, MVT::v2i64);
924 setOperationAction(ISD::SELECT, SVT, Promote);
925 AddPromotedToType (ISD::SELECT, SVT, MVT::v2i64);
928 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
930 // Custom lower v2i64 and v2f64 selects.
931 setOperationAction(ISD::LOAD, MVT::v2f64, Legal);
932 setOperationAction(ISD::LOAD, MVT::v2i64, Legal);
933 setOperationAction(ISD::SELECT, MVT::v2f64, Custom);
934 setOperationAction(ISD::SELECT, MVT::v2i64, Custom);
936 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal);
937 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal);
940 if (Subtarget->hasSSE41()) {
941 setOperationAction(ISD::FFLOOR, MVT::f32, Legal);
942 setOperationAction(ISD::FCEIL, MVT::f32, Legal);
943 setOperationAction(ISD::FTRUNC, MVT::f32, Legal);
944 setOperationAction(ISD::FRINT, MVT::f32, Legal);
945 setOperationAction(ISD::FNEARBYINT, MVT::f32, Legal);
946 setOperationAction(ISD::FFLOOR, MVT::f64, Legal);
947 setOperationAction(ISD::FCEIL, MVT::f64, Legal);
948 setOperationAction(ISD::FTRUNC, MVT::f64, Legal);
949 setOperationAction(ISD::FRINT, MVT::f64, Legal);
950 setOperationAction(ISD::FNEARBYINT, MVT::f64, Legal);
952 // FIXME: Do we need to handle scalar-to-vector here?
953 setOperationAction(ISD::MUL, MVT::v4i32, Legal);
955 setOperationAction(ISD::VSELECT, MVT::v2f64, Legal);
956 setOperationAction(ISD::VSELECT, MVT::v2i64, Legal);
957 setOperationAction(ISD::VSELECT, MVT::v16i8, Legal);
958 setOperationAction(ISD::VSELECT, MVT::v4i32, Legal);
959 setOperationAction(ISD::VSELECT, MVT::v4f32, Legal);
961 // i8 and i16 vectors are custom , because the source register and source
962 // source memory operand types are not the same width. f32 vectors are
963 // custom since the immediate controlling the insert encodes additional
965 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i8, Custom);
966 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
967 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
968 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
970 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i8, Custom);
971 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i16, Custom);
972 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i32, Custom);
973 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
975 // FIXME: these should be Legal but thats only for the case where
976 // the index is constant. For now custom expand to deal with that.
977 if (Subtarget->is64Bit()) {
978 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
979 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
983 if (Subtarget->hasSSE2()) {
984 setOperationAction(ISD::SRL, MVT::v8i16, Custom);
985 setOperationAction(ISD::SRL, MVT::v16i8, Custom);
987 setOperationAction(ISD::SHL, MVT::v8i16, Custom);
988 setOperationAction(ISD::SHL, MVT::v16i8, Custom);
990 setOperationAction(ISD::SRA, MVT::v8i16, Custom);
991 setOperationAction(ISD::SRA, MVT::v16i8, Custom);
993 if (Subtarget->hasAVX2()) {
994 setOperationAction(ISD::SRL, MVT::v2i64, Legal);
995 setOperationAction(ISD::SRL, MVT::v4i32, Legal);
997 setOperationAction(ISD::SHL, MVT::v2i64, Legal);
998 setOperationAction(ISD::SHL, MVT::v4i32, Legal);
1000 setOperationAction(ISD::SRA, MVT::v4i32, Legal);
1002 setOperationAction(ISD::SRL, MVT::v2i64, Custom);
1003 setOperationAction(ISD::SRL, MVT::v4i32, Custom);
1005 setOperationAction(ISD::SHL, MVT::v2i64, Custom);
1006 setOperationAction(ISD::SHL, MVT::v4i32, Custom);
1008 setOperationAction(ISD::SRA, MVT::v4i32, Custom);
1012 if (Subtarget->hasSSE42())
1013 setOperationAction(ISD::SETCC, MVT::v2i64, Custom);
1015 if (!TM.Options.UseSoftFloat && Subtarget->hasAVX()) {
1016 addRegisterClass(MVT::v32i8, X86::VR256RegisterClass);
1017 addRegisterClass(MVT::v16i16, X86::VR256RegisterClass);
1018 addRegisterClass(MVT::v8i32, X86::VR256RegisterClass);
1019 addRegisterClass(MVT::v8f32, X86::VR256RegisterClass);
1020 addRegisterClass(MVT::v4i64, X86::VR256RegisterClass);
1021 addRegisterClass(MVT::v4f64, X86::VR256RegisterClass);
1023 setOperationAction(ISD::LOAD, MVT::v8f32, Legal);
1024 setOperationAction(ISD::LOAD, MVT::v4f64, Legal);
1025 setOperationAction(ISD::LOAD, MVT::v4i64, Legal);
1027 setOperationAction(ISD::FADD, MVT::v8f32, Legal);
1028 setOperationAction(ISD::FSUB, MVT::v8f32, Legal);
1029 setOperationAction(ISD::FMUL, MVT::v8f32, Legal);
1030 setOperationAction(ISD::FDIV, MVT::v8f32, Legal);
1031 setOperationAction(ISD::FSQRT, MVT::v8f32, Legal);
1032 setOperationAction(ISD::FNEG, MVT::v8f32, Custom);
1034 setOperationAction(ISD::FADD, MVT::v4f64, Legal);
1035 setOperationAction(ISD::FSUB, MVT::v4f64, Legal);
1036 setOperationAction(ISD::FMUL, MVT::v4f64, Legal);
1037 setOperationAction(ISD::FDIV, MVT::v4f64, Legal);
1038 setOperationAction(ISD::FSQRT, MVT::v4f64, Legal);
1039 setOperationAction(ISD::FNEG, MVT::v4f64, Custom);
1041 setOperationAction(ISD::FP_TO_SINT, MVT::v8i32, Legal);
1042 setOperationAction(ISD::SINT_TO_FP, MVT::v8i32, Legal);
1043 setOperationAction(ISD::FP_ROUND, MVT::v4f32, Legal);
1045 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4f64, Custom);
1046 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4i64, Custom);
1047 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8f32, Custom);
1048 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i32, Custom);
1049 setOperationAction(ISD::CONCAT_VECTORS, MVT::v32i8, Custom);
1050 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i16, Custom);
1052 setOperationAction(ISD::SRL, MVT::v16i16, Custom);
1053 setOperationAction(ISD::SRL, MVT::v32i8, Custom);
1055 setOperationAction(ISD::SHL, MVT::v16i16, Custom);
1056 setOperationAction(ISD::SHL, MVT::v32i8, Custom);
1058 setOperationAction(ISD::SRA, MVT::v16i16, Custom);
1059 setOperationAction(ISD::SRA, MVT::v32i8, Custom);
1061 setOperationAction(ISD::SETCC, MVT::v32i8, Custom);
1062 setOperationAction(ISD::SETCC, MVT::v16i16, Custom);
1063 setOperationAction(ISD::SETCC, MVT::v8i32, Custom);
1064 setOperationAction(ISD::SETCC, MVT::v4i64, Custom);
1066 setOperationAction(ISD::SELECT, MVT::v4f64, Custom);
1067 setOperationAction(ISD::SELECT, MVT::v4i64, Custom);
1068 setOperationAction(ISD::SELECT, MVT::v8f32, Custom);
1070 setOperationAction(ISD::VSELECT, MVT::v4f64, Legal);
1071 setOperationAction(ISD::VSELECT, MVT::v4i64, Legal);
1072 setOperationAction(ISD::VSELECT, MVT::v8i32, Legal);
1073 setOperationAction(ISD::VSELECT, MVT::v8f32, Legal);
1075 if (Subtarget->hasAVX2()) {
1076 setOperationAction(ISD::ADD, MVT::v4i64, Legal);
1077 setOperationAction(ISD::ADD, MVT::v8i32, Legal);
1078 setOperationAction(ISD::ADD, MVT::v16i16, Legal);
1079 setOperationAction(ISD::ADD, MVT::v32i8, Legal);
1081 setOperationAction(ISD::SUB, MVT::v4i64, Legal);
1082 setOperationAction(ISD::SUB, MVT::v8i32, Legal);
1083 setOperationAction(ISD::SUB, MVT::v16i16, Legal);
1084 setOperationAction(ISD::SUB, MVT::v32i8, Legal);
1086 setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1087 setOperationAction(ISD::MUL, MVT::v8i32, Legal);
1088 setOperationAction(ISD::MUL, MVT::v16i16, Legal);
1089 // Don't lower v32i8 because there is no 128-bit byte mul
1091 setOperationAction(ISD::VSELECT, MVT::v32i8, Legal);
1093 setOperationAction(ISD::SRL, MVT::v4i64, Legal);
1094 setOperationAction(ISD::SRL, MVT::v8i32, Legal);
1096 setOperationAction(ISD::SHL, MVT::v4i64, Legal);
1097 setOperationAction(ISD::SHL, MVT::v8i32, Legal);
1099 setOperationAction(ISD::SRA, MVT::v8i32, Legal);
1101 setOperationAction(ISD::ADD, MVT::v4i64, Custom);
1102 setOperationAction(ISD::ADD, MVT::v8i32, Custom);
1103 setOperationAction(ISD::ADD, MVT::v16i16, Custom);
1104 setOperationAction(ISD::ADD, MVT::v32i8, Custom);
1106 setOperationAction(ISD::SUB, MVT::v4i64, Custom);
1107 setOperationAction(ISD::SUB, MVT::v8i32, Custom);
1108 setOperationAction(ISD::SUB, MVT::v16i16, Custom);
1109 setOperationAction(ISD::SUB, MVT::v32i8, Custom);
1111 setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1112 setOperationAction(ISD::MUL, MVT::v8i32, Custom);
1113 setOperationAction(ISD::MUL, MVT::v16i16, Custom);
1114 // Don't lower v32i8 because there is no 128-bit byte mul
1116 setOperationAction(ISD::SRL, MVT::v4i64, Custom);
1117 setOperationAction(ISD::SRL, MVT::v8i32, Custom);
1119 setOperationAction(ISD::SHL, MVT::v4i64, Custom);
1120 setOperationAction(ISD::SHL, MVT::v8i32, Custom);
1122 setOperationAction(ISD::SRA, MVT::v8i32, Custom);
1125 // Custom lower several nodes for 256-bit types.
1126 for (unsigned i = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
1127 i <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++i) {
1128 MVT::SimpleValueType SVT = (MVT::SimpleValueType)i;
1131 // Extract subvector is special because the value type
1132 // (result) is 128-bit but the source is 256-bit wide.
1133 if (VT.is128BitVector())
1134 setOperationAction(ISD::EXTRACT_SUBVECTOR, SVT, Custom);
1136 // Do not attempt to custom lower other non-256-bit vectors
1137 if (!VT.is256BitVector())
1140 setOperationAction(ISD::BUILD_VECTOR, SVT, Custom);
1141 setOperationAction(ISD::VECTOR_SHUFFLE, SVT, Custom);
1142 setOperationAction(ISD::INSERT_VECTOR_ELT, SVT, Custom);
1143 setOperationAction(ISD::EXTRACT_VECTOR_ELT, SVT, Custom);
1144 setOperationAction(ISD::SCALAR_TO_VECTOR, SVT, Custom);
1145 setOperationAction(ISD::INSERT_SUBVECTOR, SVT, Custom);
1148 // Promote v32i8, v16i16, v8i32 select, and, or, xor to v4i64.
1149 for (unsigned i = (unsigned)MVT::v32i8; i != (unsigned)MVT::v4i64; ++i) {
1150 MVT::SimpleValueType SVT = (MVT::SimpleValueType)i;
1153 // Do not attempt to promote non-256-bit vectors
1154 if (!VT.is256BitVector())
1157 setOperationAction(ISD::AND, SVT, Promote);
1158 AddPromotedToType (ISD::AND, SVT, MVT::v4i64);
1159 setOperationAction(ISD::OR, SVT, Promote);
1160 AddPromotedToType (ISD::OR, SVT, MVT::v4i64);
1161 setOperationAction(ISD::XOR, SVT, Promote);
1162 AddPromotedToType (ISD::XOR, SVT, MVT::v4i64);
1163 setOperationAction(ISD::LOAD, SVT, Promote);
1164 AddPromotedToType (ISD::LOAD, SVT, MVT::v4i64);
1165 setOperationAction(ISD::SELECT, SVT, Promote);
1166 AddPromotedToType (ISD::SELECT, SVT, MVT::v4i64);
1170 // SIGN_EXTEND_INREGs are evaluated by the extend type. Handle the expansion
1171 // of this type with custom code.
1172 for (unsigned VT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
1173 VT != (unsigned)MVT::LAST_VECTOR_VALUETYPE; VT++) {
1174 setOperationAction(ISD::SIGN_EXTEND_INREG, (MVT::SimpleValueType)VT,
1178 // We want to custom lower some of our intrinsics.
1179 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
1182 // Only custom-lower 64-bit SADDO and friends on 64-bit because we don't
1183 // handle type legalization for these operations here.
1185 // FIXME: We really should do custom legalization for addition and
1186 // subtraction on x86-32 once PR3203 is fixed. We really can't do much better
1187 // than generic legalization for 64-bit multiplication-with-overflow, though.
1188 for (unsigned i = 0, e = 3+Subtarget->is64Bit(); i != e; ++i) {
1189 // Add/Sub/Mul with overflow operations are custom lowered.
1191 setOperationAction(ISD::SADDO, VT, Custom);
1192 setOperationAction(ISD::UADDO, VT, Custom);
1193 setOperationAction(ISD::SSUBO, VT, Custom);
1194 setOperationAction(ISD::USUBO, VT, Custom);
1195 setOperationAction(ISD::SMULO, VT, Custom);
1196 setOperationAction(ISD::UMULO, VT, Custom);
1199 // There are no 8-bit 3-address imul/mul instructions
1200 setOperationAction(ISD::SMULO, MVT::i8, Expand);
1201 setOperationAction(ISD::UMULO, MVT::i8, Expand);
1203 if (!Subtarget->is64Bit()) {
1204 // These libcalls are not available in 32-bit.
1205 setLibcallName(RTLIB::SHL_I128, 0);
1206 setLibcallName(RTLIB::SRL_I128, 0);
1207 setLibcallName(RTLIB::SRA_I128, 0);
1210 // We have target-specific dag combine patterns for the following nodes:
1211 setTargetDAGCombine(ISD::VECTOR_SHUFFLE);
1212 setTargetDAGCombine(ISD::EXTRACT_VECTOR_ELT);
1213 setTargetDAGCombine(ISD::VSELECT);
1214 setTargetDAGCombine(ISD::SELECT);
1215 setTargetDAGCombine(ISD::SHL);
1216 setTargetDAGCombine(ISD::SRA);
1217 setTargetDAGCombine(ISD::SRL);
1218 setTargetDAGCombine(ISD::OR);
1219 setTargetDAGCombine(ISD::AND);
1220 setTargetDAGCombine(ISD::ADD);
1221 setTargetDAGCombine(ISD::FADD);
1222 setTargetDAGCombine(ISD::FSUB);
1223 setTargetDAGCombine(ISD::SUB);
1224 setTargetDAGCombine(ISD::LOAD);
1225 setTargetDAGCombine(ISD::STORE);
1226 setTargetDAGCombine(ISD::ZERO_EXTEND);
1227 setTargetDAGCombine(ISD::SINT_TO_FP);
1228 if (Subtarget->is64Bit())
1229 setTargetDAGCombine(ISD::MUL);
1230 if (Subtarget->hasBMI())
1231 setTargetDAGCombine(ISD::XOR);
1233 computeRegisterProperties();
1235 // On Darwin, -Os means optimize for size without hurting performance,
1236 // do not reduce the limit.
1237 maxStoresPerMemset = 16; // For @llvm.memset -> sequence of stores
1238 maxStoresPerMemsetOptSize = Subtarget->isTargetDarwin() ? 16 : 8;
1239 maxStoresPerMemcpy = 8; // For @llvm.memcpy -> sequence of stores
1240 maxStoresPerMemcpyOptSize = Subtarget->isTargetDarwin() ? 8 : 4;
1241 maxStoresPerMemmove = 8; // For @llvm.memmove -> sequence of stores
1242 maxStoresPerMemmoveOptSize = Subtarget->isTargetDarwin() ? 8 : 4;
1243 setPrefLoopAlignment(4); // 2^4 bytes.
1244 benefitFromCodePlacementOpt = true;
1246 setPrefFunctionAlignment(4); // 2^4 bytes.
1250 EVT X86TargetLowering::getSetCCResultType(EVT VT) const {
1251 if (!VT.isVector()) return MVT::i8;
1252 return VT.changeVectorElementTypeToInteger();
1256 /// getMaxByValAlign - Helper for getByValTypeAlignment to determine
1257 /// the desired ByVal argument alignment.
1258 static void getMaxByValAlign(Type *Ty, unsigned &MaxAlign) {
1261 if (VectorType *VTy = dyn_cast<VectorType>(Ty)) {
1262 if (VTy->getBitWidth() == 128)
1264 } else if (ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
1265 unsigned EltAlign = 0;
1266 getMaxByValAlign(ATy->getElementType(), EltAlign);
1267 if (EltAlign > MaxAlign)
1268 MaxAlign = EltAlign;
1269 } else if (StructType *STy = dyn_cast<StructType>(Ty)) {
1270 for (unsigned i = 0, e = STy->getNumElements(); i != e; ++i) {
1271 unsigned EltAlign = 0;
1272 getMaxByValAlign(STy->getElementType(i), EltAlign);
1273 if (EltAlign > MaxAlign)
1274 MaxAlign = EltAlign;
1282 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
1283 /// function arguments in the caller parameter area. For X86, aggregates
1284 /// that contain SSE vectors are placed at 16-byte boundaries while the rest
1285 /// are at 4-byte boundaries.
1286 unsigned X86TargetLowering::getByValTypeAlignment(Type *Ty) const {
1287 if (Subtarget->is64Bit()) {
1288 // Max of 8 and alignment of type.
1289 unsigned TyAlign = TD->getABITypeAlignment(Ty);
1296 if (Subtarget->hasSSE1())
1297 getMaxByValAlign(Ty, Align);
1301 /// getOptimalMemOpType - Returns the target specific optimal type for load
1302 /// and store operations as a result of memset, memcpy, and memmove
1303 /// lowering. If DstAlign is zero that means it's safe to destination
1304 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
1305 /// means there isn't a need to check it against alignment requirement,
1306 /// probably because the source does not need to be loaded. If
1307 /// 'IsZeroVal' is true, that means it's safe to return a
1308 /// non-scalar-integer type, e.g. empty string source, constant, or loaded
1309 /// from memory. 'MemcpyStrSrc' indicates whether the memcpy source is
1310 /// constant so it does not need to be loaded.
1311 /// It returns EVT::Other if the type should be determined using generic
1312 /// target-independent logic.
1314 X86TargetLowering::getOptimalMemOpType(uint64_t Size,
1315 unsigned DstAlign, unsigned SrcAlign,
1318 MachineFunction &MF) const {
1319 // FIXME: This turns off use of xmm stores for memset/memcpy on targets like
1320 // linux. This is because the stack realignment code can't handle certain
1321 // cases like PR2962. This should be removed when PR2962 is fixed.
1322 const Function *F = MF.getFunction();
1324 !F->hasFnAttr(Attribute::NoImplicitFloat)) {
1326 (Subtarget->isUnalignedMemAccessFast() ||
1327 ((DstAlign == 0 || DstAlign >= 16) &&
1328 (SrcAlign == 0 || SrcAlign >= 16))) &&
1329 Subtarget->getStackAlignment() >= 16) {
1330 if (Subtarget->getStackAlignment() >= 32) {
1331 if (Subtarget->hasAVX2())
1333 if (Subtarget->hasAVX())
1336 if (Subtarget->hasSSE2())
1338 if (Subtarget->hasSSE1())
1340 } else if (!MemcpyStrSrc && Size >= 8 &&
1341 !Subtarget->is64Bit() &&
1342 Subtarget->getStackAlignment() >= 8 &&
1343 Subtarget->hasSSE2()) {
1344 // Do not use f64 to lower memcpy if source is string constant. It's
1345 // better to use i32 to avoid the loads.
1349 if (Subtarget->is64Bit() && Size >= 8)
1354 /// getJumpTableEncoding - Return the entry encoding for a jump table in the
1355 /// current function. The returned value is a member of the
1356 /// MachineJumpTableInfo::JTEntryKind enum.
1357 unsigned X86TargetLowering::getJumpTableEncoding() const {
1358 // In GOT pic mode, each entry in the jump table is emitted as a @GOTOFF
1360 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1361 Subtarget->isPICStyleGOT())
1362 return MachineJumpTableInfo::EK_Custom32;
1364 // Otherwise, use the normal jump table encoding heuristics.
1365 return TargetLowering::getJumpTableEncoding();
1369 X86TargetLowering::LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI,
1370 const MachineBasicBlock *MBB,
1371 unsigned uid,MCContext &Ctx) const{
1372 assert(getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1373 Subtarget->isPICStyleGOT());
1374 // In 32-bit ELF systems, our jump table entries are formed with @GOTOFF
1376 return MCSymbolRefExpr::Create(MBB->getSymbol(),
1377 MCSymbolRefExpr::VK_GOTOFF, Ctx);
1380 /// getPICJumpTableRelocaBase - Returns relocation base for the given PIC
1382 SDValue X86TargetLowering::getPICJumpTableRelocBase(SDValue Table,
1383 SelectionDAG &DAG) const {
1384 if (!Subtarget->is64Bit())
1385 // This doesn't have DebugLoc associated with it, but is not really the
1386 // same as a Register.
1387 return DAG.getNode(X86ISD::GlobalBaseReg, DebugLoc(), getPointerTy());
1391 /// getPICJumpTableRelocBaseExpr - This returns the relocation base for the
1392 /// given PIC jumptable, the same as getPICJumpTableRelocBase, but as an
1394 const MCExpr *X86TargetLowering::
1395 getPICJumpTableRelocBaseExpr(const MachineFunction *MF, unsigned JTI,
1396 MCContext &Ctx) const {
1397 // X86-64 uses RIP relative addressing based on the jump table label.
1398 if (Subtarget->isPICStyleRIPRel())
1399 return TargetLowering::getPICJumpTableRelocBaseExpr(MF, JTI, Ctx);
1401 // Otherwise, the reference is relative to the PIC base.
1402 return MCSymbolRefExpr::Create(MF->getPICBaseSymbol(), Ctx);
1405 // FIXME: Why this routine is here? Move to RegInfo!
1406 std::pair<const TargetRegisterClass*, uint8_t>
1407 X86TargetLowering::findRepresentativeClass(EVT VT) const{
1408 const TargetRegisterClass *RRC = 0;
1410 switch (VT.getSimpleVT().SimpleTy) {
1412 return TargetLowering::findRepresentativeClass(VT);
1413 case MVT::i8: case MVT::i16: case MVT::i32: case MVT::i64:
1414 RRC = (Subtarget->is64Bit()
1415 ? X86::GR64RegisterClass : X86::GR32RegisterClass);
1418 RRC = X86::VR64RegisterClass;
1420 case MVT::f32: case MVT::f64:
1421 case MVT::v16i8: case MVT::v8i16: case MVT::v4i32: case MVT::v2i64:
1422 case MVT::v4f32: case MVT::v2f64:
1423 case MVT::v32i8: case MVT::v8i32: case MVT::v4i64: case MVT::v8f32:
1425 RRC = X86::VR128RegisterClass;
1428 return std::make_pair(RRC, Cost);
1431 bool X86TargetLowering::getStackCookieLocation(unsigned &AddressSpace,
1432 unsigned &Offset) const {
1433 if (!Subtarget->isTargetLinux())
1436 if (Subtarget->is64Bit()) {
1437 // %fs:0x28, unless we're using a Kernel code model, in which case it's %gs:
1439 if (getTargetMachine().getCodeModel() == CodeModel::Kernel)
1452 //===----------------------------------------------------------------------===//
1453 // Return Value Calling Convention Implementation
1454 //===----------------------------------------------------------------------===//
1456 #include "X86GenCallingConv.inc"
1459 X86TargetLowering::CanLowerReturn(CallingConv::ID CallConv,
1460 MachineFunction &MF, bool isVarArg,
1461 const SmallVectorImpl<ISD::OutputArg> &Outs,
1462 LLVMContext &Context) const {
1463 SmallVector<CCValAssign, 16> RVLocs;
1464 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(),
1466 return CCInfo.CheckReturn(Outs, RetCC_X86);
1470 X86TargetLowering::LowerReturn(SDValue Chain,
1471 CallingConv::ID CallConv, bool isVarArg,
1472 const SmallVectorImpl<ISD::OutputArg> &Outs,
1473 const SmallVectorImpl<SDValue> &OutVals,
1474 DebugLoc dl, SelectionDAG &DAG) const {
1475 MachineFunction &MF = DAG.getMachineFunction();
1476 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1478 SmallVector<CCValAssign, 16> RVLocs;
1479 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(),
1480 RVLocs, *DAG.getContext());
1481 CCInfo.AnalyzeReturn(Outs, RetCC_X86);
1483 // Add the regs to the liveout set for the function.
1484 MachineRegisterInfo &MRI = DAG.getMachineFunction().getRegInfo();
1485 for (unsigned i = 0; i != RVLocs.size(); ++i)
1486 if (RVLocs[i].isRegLoc() && !MRI.isLiveOut(RVLocs[i].getLocReg()))
1487 MRI.addLiveOut(RVLocs[i].getLocReg());
1491 SmallVector<SDValue, 6> RetOps;
1492 RetOps.push_back(Chain); // Operand #0 = Chain (updated below)
1493 // Operand #1 = Bytes To Pop
1494 RetOps.push_back(DAG.getTargetConstant(FuncInfo->getBytesToPopOnReturn(),
1497 // Copy the result values into the output registers.
1498 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1499 CCValAssign &VA = RVLocs[i];
1500 assert(VA.isRegLoc() && "Can only return in registers!");
1501 SDValue ValToCopy = OutVals[i];
1502 EVT ValVT = ValToCopy.getValueType();
1504 // If this is x86-64, and we disabled SSE, we can't return FP values,
1505 // or SSE or MMX vectors.
1506 if ((ValVT == MVT::f32 || ValVT == MVT::f64 ||
1507 VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) &&
1508 (Subtarget->is64Bit() && !Subtarget->hasSSE1())) {
1509 report_fatal_error("SSE register return with SSE disabled");
1511 // Likewise we can't return F64 values with SSE1 only. gcc does so, but
1512 // llvm-gcc has never done it right and no one has noticed, so this
1513 // should be OK for now.
1514 if (ValVT == MVT::f64 &&
1515 (Subtarget->is64Bit() && !Subtarget->hasSSE2()))
1516 report_fatal_error("SSE2 register return with SSE2 disabled");
1518 // Returns in ST0/ST1 are handled specially: these are pushed as operands to
1519 // the RET instruction and handled by the FP Stackifier.
1520 if (VA.getLocReg() == X86::ST0 ||
1521 VA.getLocReg() == X86::ST1) {
1522 // If this is a copy from an xmm register to ST(0), use an FPExtend to
1523 // change the value to the FP stack register class.
1524 if (isScalarFPTypeInSSEReg(VA.getValVT()))
1525 ValToCopy = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f80, ValToCopy);
1526 RetOps.push_back(ValToCopy);
1527 // Don't emit a copytoreg.
1531 // 64-bit vector (MMX) values are returned in XMM0 / XMM1 except for v1i64
1532 // which is returned in RAX / RDX.
1533 if (Subtarget->is64Bit()) {
1534 if (ValVT == MVT::x86mmx) {
1535 if (VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) {
1536 ValToCopy = DAG.getNode(ISD::BITCAST, dl, MVT::i64, ValToCopy);
1537 ValToCopy = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
1539 // If we don't have SSE2 available, convert to v4f32 so the generated
1540 // register is legal.
1541 if (!Subtarget->hasSSE2())
1542 ValToCopy = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32,ValToCopy);
1547 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), ValToCopy, Flag);
1548 Flag = Chain.getValue(1);
1551 // The x86-64 ABI for returning structs by value requires that we copy
1552 // the sret argument into %rax for the return. We saved the argument into
1553 // a virtual register in the entry block, so now we copy the value out
1555 if (Subtarget->is64Bit() &&
1556 DAG.getMachineFunction().getFunction()->hasStructRetAttr()) {
1557 MachineFunction &MF = DAG.getMachineFunction();
1558 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1559 unsigned Reg = FuncInfo->getSRetReturnReg();
1561 "SRetReturnReg should have been set in LowerFormalArguments().");
1562 SDValue Val = DAG.getCopyFromReg(Chain, dl, Reg, getPointerTy());
1564 Chain = DAG.getCopyToReg(Chain, dl, X86::RAX, Val, Flag);
1565 Flag = Chain.getValue(1);
1567 // RAX now acts like a return value.
1568 MRI.addLiveOut(X86::RAX);
1571 RetOps[0] = Chain; // Update chain.
1573 // Add the flag if we have it.
1575 RetOps.push_back(Flag);
1577 return DAG.getNode(X86ISD::RET_FLAG, dl,
1578 MVT::Other, &RetOps[0], RetOps.size());
1581 bool X86TargetLowering::isUsedByReturnOnly(SDNode *N) const {
1582 if (N->getNumValues() != 1)
1584 if (!N->hasNUsesOfValue(1, 0))
1587 SDNode *Copy = *N->use_begin();
1588 if (Copy->getOpcode() != ISD::CopyToReg &&
1589 Copy->getOpcode() != ISD::FP_EXTEND)
1592 bool HasRet = false;
1593 for (SDNode::use_iterator UI = Copy->use_begin(), UE = Copy->use_end();
1595 if (UI->getOpcode() != X86ISD::RET_FLAG)
1604 X86TargetLowering::getTypeForExtArgOrReturn(LLVMContext &Context, EVT VT,
1605 ISD::NodeType ExtendKind) const {
1607 // TODO: Is this also valid on 32-bit?
1608 if (Subtarget->is64Bit() && VT == MVT::i1 && ExtendKind == ISD::ZERO_EXTEND)
1609 ReturnMVT = MVT::i8;
1611 ReturnMVT = MVT::i32;
1613 EVT MinVT = getRegisterType(Context, ReturnMVT);
1614 return VT.bitsLT(MinVT) ? MinVT : VT;
1617 /// LowerCallResult - Lower the result values of a call into the
1618 /// appropriate copies out of appropriate physical registers.
1621 X86TargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
1622 CallingConv::ID CallConv, bool isVarArg,
1623 const SmallVectorImpl<ISD::InputArg> &Ins,
1624 DebugLoc dl, SelectionDAG &DAG,
1625 SmallVectorImpl<SDValue> &InVals) const {
1627 // Assign locations to each value returned by this call.
1628 SmallVector<CCValAssign, 16> RVLocs;
1629 bool Is64Bit = Subtarget->is64Bit();
1630 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
1631 getTargetMachine(), RVLocs, *DAG.getContext());
1632 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
1634 // Copy all of the result registers out of their specified physreg.
1635 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1636 CCValAssign &VA = RVLocs[i];
1637 EVT CopyVT = VA.getValVT();
1639 // If this is x86-64, and we disabled SSE, we can't return FP values
1640 if ((CopyVT == MVT::f32 || CopyVT == MVT::f64) &&
1641 ((Is64Bit || Ins[i].Flags.isInReg()) && !Subtarget->hasSSE1())) {
1642 report_fatal_error("SSE register return with SSE disabled");
1647 // If this is a call to a function that returns an fp value on the floating
1648 // point stack, we must guarantee the the value is popped from the stack, so
1649 // a CopyFromReg is not good enough - the copy instruction may be eliminated
1650 // if the return value is not used. We use the FpPOP_RETVAL instruction
1652 if (VA.getLocReg() == X86::ST0 || VA.getLocReg() == X86::ST1) {
1653 // If we prefer to use the value in xmm registers, copy it out as f80 and
1654 // use a truncate to move it from fp stack reg to xmm reg.
1655 if (isScalarFPTypeInSSEReg(VA.getValVT())) CopyVT = MVT::f80;
1656 SDValue Ops[] = { Chain, InFlag };
1657 Chain = SDValue(DAG.getMachineNode(X86::FpPOP_RETVAL, dl, CopyVT,
1658 MVT::Other, MVT::Glue, Ops, 2), 1);
1659 Val = Chain.getValue(0);
1661 // Round the f80 to the right size, which also moves it to the appropriate
1663 if (CopyVT != VA.getValVT())
1664 Val = DAG.getNode(ISD::FP_ROUND, dl, VA.getValVT(), Val,
1665 // This truncation won't change the value.
1666 DAG.getIntPtrConstant(1));
1668 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(),
1669 CopyVT, InFlag).getValue(1);
1670 Val = Chain.getValue(0);
1672 InFlag = Chain.getValue(2);
1673 InVals.push_back(Val);
1680 //===----------------------------------------------------------------------===//
1681 // C & StdCall & Fast Calling Convention implementation
1682 //===----------------------------------------------------------------------===//
1683 // StdCall calling convention seems to be standard for many Windows' API
1684 // routines and around. It differs from C calling convention just a little:
1685 // callee should clean up the stack, not caller. Symbols should be also
1686 // decorated in some fancy way :) It doesn't support any vector arguments.
1687 // For info on fast calling convention see Fast Calling Convention (tail call)
1688 // implementation LowerX86_32FastCCCallTo.
1690 /// CallIsStructReturn - Determines whether a call uses struct return
1692 static bool CallIsStructReturn(const SmallVectorImpl<ISD::OutputArg> &Outs) {
1696 return Outs[0].Flags.isSRet();
1699 /// ArgsAreStructReturn - Determines whether a function uses struct
1700 /// return semantics.
1702 ArgsAreStructReturn(const SmallVectorImpl<ISD::InputArg> &Ins) {
1706 return Ins[0].Flags.isSRet();
1709 /// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified
1710 /// by "Src" to address "Dst" with size and alignment information specified by
1711 /// the specific parameter attribute. The copy will be passed as a byval
1712 /// function parameter.
1714 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
1715 ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
1717 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32);
1719 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
1720 /*isVolatile*/false, /*AlwaysInline=*/true,
1721 MachinePointerInfo(), MachinePointerInfo());
1724 /// IsTailCallConvention - Return true if the calling convention is one that
1725 /// supports tail call optimization.
1726 static bool IsTailCallConvention(CallingConv::ID CC) {
1727 return (CC == CallingConv::Fast || CC == CallingConv::GHC);
1730 bool X86TargetLowering::mayBeEmittedAsTailCall(CallInst *CI) const {
1731 if (!CI->isTailCall())
1735 CallingConv::ID CalleeCC = CS.getCallingConv();
1736 if (!IsTailCallConvention(CalleeCC) && CalleeCC != CallingConv::C)
1742 /// FuncIsMadeTailCallSafe - Return true if the function is being made into
1743 /// a tailcall target by changing its ABI.
1744 static bool FuncIsMadeTailCallSafe(CallingConv::ID CC,
1745 bool GuaranteedTailCallOpt) {
1746 return GuaranteedTailCallOpt && IsTailCallConvention(CC);
1750 X86TargetLowering::LowerMemArgument(SDValue Chain,
1751 CallingConv::ID CallConv,
1752 const SmallVectorImpl<ISD::InputArg> &Ins,
1753 DebugLoc dl, SelectionDAG &DAG,
1754 const CCValAssign &VA,
1755 MachineFrameInfo *MFI,
1757 // Create the nodes corresponding to a load from this parameter slot.
1758 ISD::ArgFlagsTy Flags = Ins[i].Flags;
1759 bool AlwaysUseMutable = FuncIsMadeTailCallSafe(CallConv,
1760 getTargetMachine().Options.GuaranteedTailCallOpt);
1761 bool isImmutable = !AlwaysUseMutable && !Flags.isByVal();
1764 // If value is passed by pointer we have address passed instead of the value
1766 if (VA.getLocInfo() == CCValAssign::Indirect)
1767 ValVT = VA.getLocVT();
1769 ValVT = VA.getValVT();
1771 // FIXME: For now, all byval parameter objects are marked mutable. This can be
1772 // changed with more analysis.
1773 // In case of tail call optimization mark all arguments mutable. Since they
1774 // could be overwritten by lowering of arguments in case of a tail call.
1775 if (Flags.isByVal()) {
1776 unsigned Bytes = Flags.getByValSize();
1777 if (Bytes == 0) Bytes = 1; // Don't create zero-sized stack objects.
1778 int FI = MFI->CreateFixedObject(Bytes, VA.getLocMemOffset(), isImmutable);
1779 return DAG.getFrameIndex(FI, getPointerTy());
1781 int FI = MFI->CreateFixedObject(ValVT.getSizeInBits()/8,
1782 VA.getLocMemOffset(), isImmutable);
1783 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
1784 return DAG.getLoad(ValVT, dl, Chain, FIN,
1785 MachinePointerInfo::getFixedStack(FI),
1786 false, false, false, 0);
1791 X86TargetLowering::LowerFormalArguments(SDValue Chain,
1792 CallingConv::ID CallConv,
1794 const SmallVectorImpl<ISD::InputArg> &Ins,
1797 SmallVectorImpl<SDValue> &InVals)
1799 MachineFunction &MF = DAG.getMachineFunction();
1800 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1802 const Function* Fn = MF.getFunction();
1803 if (Fn->hasExternalLinkage() &&
1804 Subtarget->isTargetCygMing() &&
1805 Fn->getName() == "main")
1806 FuncInfo->setForceFramePointer(true);
1808 MachineFrameInfo *MFI = MF.getFrameInfo();
1809 bool Is64Bit = Subtarget->is64Bit();
1810 bool IsWin64 = Subtarget->isTargetWin64();
1812 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
1813 "Var args not supported with calling convention fastcc or ghc");
1815 // Assign locations to all of the incoming arguments.
1816 SmallVector<CCValAssign, 16> ArgLocs;
1817 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(),
1818 ArgLocs, *DAG.getContext());
1820 // Allocate shadow area for Win64
1822 CCInfo.AllocateStack(32, 8);
1825 CCInfo.AnalyzeFormalArguments(Ins, CC_X86);
1827 unsigned LastVal = ~0U;
1829 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1830 CCValAssign &VA = ArgLocs[i];
1831 // TODO: If an arg is passed in two places (e.g. reg and stack), skip later
1833 assert(VA.getValNo() != LastVal &&
1834 "Don't support value assigned to multiple locs yet");
1836 LastVal = VA.getValNo();
1838 if (VA.isRegLoc()) {
1839 EVT RegVT = VA.getLocVT();
1840 TargetRegisterClass *RC = NULL;
1841 if (RegVT == MVT::i32)
1842 RC = X86::GR32RegisterClass;
1843 else if (Is64Bit && RegVT == MVT::i64)
1844 RC = X86::GR64RegisterClass;
1845 else if (RegVT == MVT::f32)
1846 RC = X86::FR32RegisterClass;
1847 else if (RegVT == MVT::f64)
1848 RC = X86::FR64RegisterClass;
1849 else if (RegVT.isVector() && RegVT.getSizeInBits() == 256)
1850 RC = X86::VR256RegisterClass;
1851 else if (RegVT.isVector() && RegVT.getSizeInBits() == 128)
1852 RC = X86::VR128RegisterClass;
1853 else if (RegVT == MVT::x86mmx)
1854 RC = X86::VR64RegisterClass;
1856 llvm_unreachable("Unknown argument type!");
1858 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
1859 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
1861 // If this is an 8 or 16-bit value, it is really passed promoted to 32
1862 // bits. Insert an assert[sz]ext to capture this, then truncate to the
1864 if (VA.getLocInfo() == CCValAssign::SExt)
1865 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
1866 DAG.getValueType(VA.getValVT()));
1867 else if (VA.getLocInfo() == CCValAssign::ZExt)
1868 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
1869 DAG.getValueType(VA.getValVT()));
1870 else if (VA.getLocInfo() == CCValAssign::BCvt)
1871 ArgValue = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), ArgValue);
1873 if (VA.isExtInLoc()) {
1874 // Handle MMX values passed in XMM regs.
1875 if (RegVT.isVector()) {
1876 ArgValue = DAG.getNode(X86ISD::MOVDQ2Q, dl, VA.getValVT(),
1879 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
1882 assert(VA.isMemLoc());
1883 ArgValue = LowerMemArgument(Chain, CallConv, Ins, dl, DAG, VA, MFI, i);
1886 // If value is passed via pointer - do a load.
1887 if (VA.getLocInfo() == CCValAssign::Indirect)
1888 ArgValue = DAG.getLoad(VA.getValVT(), dl, Chain, ArgValue,
1889 MachinePointerInfo(), false, false, false, 0);
1891 InVals.push_back(ArgValue);
1894 // The x86-64 ABI for returning structs by value requires that we copy
1895 // the sret argument into %rax for the return. Save the argument into
1896 // a virtual register so that we can access it from the return points.
1897 if (Is64Bit && MF.getFunction()->hasStructRetAttr()) {
1898 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1899 unsigned Reg = FuncInfo->getSRetReturnReg();
1901 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(MVT::i64));
1902 FuncInfo->setSRetReturnReg(Reg);
1904 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, InVals[0]);
1905 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain);
1908 unsigned StackSize = CCInfo.getNextStackOffset();
1909 // Align stack specially for tail calls.
1910 if (FuncIsMadeTailCallSafe(CallConv,
1911 MF.getTarget().Options.GuaranteedTailCallOpt))
1912 StackSize = GetAlignedArgumentStackSize(StackSize, DAG);
1914 // If the function takes variable number of arguments, make a frame index for
1915 // the start of the first vararg value... for expansion of llvm.va_start.
1917 if (Is64Bit || (CallConv != CallingConv::X86_FastCall &&
1918 CallConv != CallingConv::X86_ThisCall)) {
1919 FuncInfo->setVarArgsFrameIndex(MFI->CreateFixedObject(1, StackSize,true));
1922 unsigned TotalNumIntRegs = 0, TotalNumXMMRegs = 0;
1924 // FIXME: We should really autogenerate these arrays
1925 static const unsigned GPR64ArgRegsWin64[] = {
1926 X86::RCX, X86::RDX, X86::R8, X86::R9
1928 static const unsigned GPR64ArgRegs64Bit[] = {
1929 X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9
1931 static const unsigned XMMArgRegs64Bit[] = {
1932 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
1933 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
1935 const unsigned *GPR64ArgRegs;
1936 unsigned NumXMMRegs = 0;
1939 // The XMM registers which might contain var arg parameters are shadowed
1940 // in their paired GPR. So we only need to save the GPR to their home
1942 TotalNumIntRegs = 4;
1943 GPR64ArgRegs = GPR64ArgRegsWin64;
1945 TotalNumIntRegs = 6; TotalNumXMMRegs = 8;
1946 GPR64ArgRegs = GPR64ArgRegs64Bit;
1948 NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs64Bit,
1951 unsigned NumIntRegs = CCInfo.getFirstUnallocated(GPR64ArgRegs,
1954 bool NoImplicitFloatOps = Fn->hasFnAttr(Attribute::NoImplicitFloat);
1955 assert(!(NumXMMRegs && !Subtarget->hasSSE1()) &&
1956 "SSE register cannot be used when SSE is disabled!");
1957 assert(!(NumXMMRegs && MF.getTarget().Options.UseSoftFloat &&
1958 NoImplicitFloatOps) &&
1959 "SSE register cannot be used when SSE is disabled!");
1960 if (MF.getTarget().Options.UseSoftFloat || NoImplicitFloatOps ||
1961 !Subtarget->hasSSE1())
1962 // Kernel mode asks for SSE to be disabled, so don't push them
1964 TotalNumXMMRegs = 0;
1967 const TargetFrameLowering &TFI = *getTargetMachine().getFrameLowering();
1968 // Get to the caller-allocated home save location. Add 8 to account
1969 // for the return address.
1970 int HomeOffset = TFI.getOffsetOfLocalArea() + 8;
1971 FuncInfo->setRegSaveFrameIndex(
1972 MFI->CreateFixedObject(1, NumIntRegs * 8 + HomeOffset, false));
1973 // Fixup to set vararg frame on shadow area (4 x i64).
1975 FuncInfo->setVarArgsFrameIndex(FuncInfo->getRegSaveFrameIndex());
1977 // For X86-64, if there are vararg parameters that are passed via
1978 // registers, then we must store them to their spots on the stack so
1979 // they may be loaded by deferencing the result of va_next.
1980 FuncInfo->setVarArgsGPOffset(NumIntRegs * 8);
1981 FuncInfo->setVarArgsFPOffset(TotalNumIntRegs * 8 + NumXMMRegs * 16);
1982 FuncInfo->setRegSaveFrameIndex(
1983 MFI->CreateStackObject(TotalNumIntRegs * 8 + TotalNumXMMRegs * 16, 16,
1987 // Store the integer parameter registers.
1988 SmallVector<SDValue, 8> MemOps;
1989 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
1991 unsigned Offset = FuncInfo->getVarArgsGPOffset();
1992 for (; NumIntRegs != TotalNumIntRegs; ++NumIntRegs) {
1993 SDValue FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), RSFIN,
1994 DAG.getIntPtrConstant(Offset));
1995 unsigned VReg = MF.addLiveIn(GPR64ArgRegs[NumIntRegs],
1996 X86::GR64RegisterClass);
1997 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64);
1999 DAG.getStore(Val.getValue(1), dl, Val, FIN,
2000 MachinePointerInfo::getFixedStack(
2001 FuncInfo->getRegSaveFrameIndex(), Offset),
2003 MemOps.push_back(Store);
2007 if (TotalNumXMMRegs != 0 && NumXMMRegs != TotalNumXMMRegs) {
2008 // Now store the XMM (fp + vector) parameter registers.
2009 SmallVector<SDValue, 11> SaveXMMOps;
2010 SaveXMMOps.push_back(Chain);
2012 unsigned AL = MF.addLiveIn(X86::AL, X86::GR8RegisterClass);
2013 SDValue ALVal = DAG.getCopyFromReg(DAG.getEntryNode(), dl, AL, MVT::i8);
2014 SaveXMMOps.push_back(ALVal);
2016 SaveXMMOps.push_back(DAG.getIntPtrConstant(
2017 FuncInfo->getRegSaveFrameIndex()));
2018 SaveXMMOps.push_back(DAG.getIntPtrConstant(
2019 FuncInfo->getVarArgsFPOffset()));
2021 for (; NumXMMRegs != TotalNumXMMRegs; ++NumXMMRegs) {
2022 unsigned VReg = MF.addLiveIn(XMMArgRegs64Bit[NumXMMRegs],
2023 X86::VR128RegisterClass);
2024 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::v4f32);
2025 SaveXMMOps.push_back(Val);
2027 MemOps.push_back(DAG.getNode(X86ISD::VASTART_SAVE_XMM_REGS, dl,
2029 &SaveXMMOps[0], SaveXMMOps.size()));
2032 if (!MemOps.empty())
2033 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
2034 &MemOps[0], MemOps.size());
2038 // Some CCs need callee pop.
2039 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg,
2040 MF.getTarget().Options.GuaranteedTailCallOpt)) {
2041 FuncInfo->setBytesToPopOnReturn(StackSize); // Callee pops everything.
2043 FuncInfo->setBytesToPopOnReturn(0); // Callee pops nothing.
2044 // If this is an sret function, the return should pop the hidden pointer.
2045 if (!Is64Bit && !IsTailCallConvention(CallConv) && ArgsAreStructReturn(Ins))
2046 FuncInfo->setBytesToPopOnReturn(4);
2050 // RegSaveFrameIndex is X86-64 only.
2051 FuncInfo->setRegSaveFrameIndex(0xAAAAAAA);
2052 if (CallConv == CallingConv::X86_FastCall ||
2053 CallConv == CallingConv::X86_ThisCall)
2054 // fastcc functions can't have varargs.
2055 FuncInfo->setVarArgsFrameIndex(0xAAAAAAA);
2058 FuncInfo->setArgumentStackSize(StackSize);
2064 X86TargetLowering::LowerMemOpCallTo(SDValue Chain,
2065 SDValue StackPtr, SDValue Arg,
2066 DebugLoc dl, SelectionDAG &DAG,
2067 const CCValAssign &VA,
2068 ISD::ArgFlagsTy Flags) const {
2069 unsigned LocMemOffset = VA.getLocMemOffset();
2070 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
2071 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
2072 if (Flags.isByVal())
2073 return CreateCopyOfByValArgument(Arg, PtrOff, Chain, Flags, DAG, dl);
2075 return DAG.getStore(Chain, dl, Arg, PtrOff,
2076 MachinePointerInfo::getStack(LocMemOffset),
2080 /// EmitTailCallLoadRetAddr - Emit a load of return address if tail call
2081 /// optimization is performed and it is required.
2083 X86TargetLowering::EmitTailCallLoadRetAddr(SelectionDAG &DAG,
2084 SDValue &OutRetAddr, SDValue Chain,
2085 bool IsTailCall, bool Is64Bit,
2086 int FPDiff, DebugLoc dl) const {
2087 // Adjust the Return address stack slot.
2088 EVT VT = getPointerTy();
2089 OutRetAddr = getReturnAddressFrameIndex(DAG);
2091 // Load the "old" Return address.
2092 OutRetAddr = DAG.getLoad(VT, dl, Chain, OutRetAddr, MachinePointerInfo(),
2093 false, false, false, 0);
2094 return SDValue(OutRetAddr.getNode(), 1);
2097 /// EmitTailCallStoreRetAddr - Emit a store of the return address if tail call
2098 /// optimization is performed and it is required (FPDiff!=0).
2100 EmitTailCallStoreRetAddr(SelectionDAG & DAG, MachineFunction &MF,
2101 SDValue Chain, SDValue RetAddrFrIdx,
2102 bool Is64Bit, int FPDiff, DebugLoc dl) {
2103 // Store the return address to the appropriate stack slot.
2104 if (!FPDiff) return Chain;
2105 // Calculate the new stack slot for the return address.
2106 int SlotSize = Is64Bit ? 8 : 4;
2107 int NewReturnAddrFI =
2108 MF.getFrameInfo()->CreateFixedObject(SlotSize, FPDiff-SlotSize, false);
2109 EVT VT = Is64Bit ? MVT::i64 : MVT::i32;
2110 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewReturnAddrFI, VT);
2111 Chain = DAG.getStore(Chain, dl, RetAddrFrIdx, NewRetAddrFrIdx,
2112 MachinePointerInfo::getFixedStack(NewReturnAddrFI),
2118 X86TargetLowering::LowerCall(SDValue Chain, SDValue Callee,
2119 CallingConv::ID CallConv, bool isVarArg,
2121 const SmallVectorImpl<ISD::OutputArg> &Outs,
2122 const SmallVectorImpl<SDValue> &OutVals,
2123 const SmallVectorImpl<ISD::InputArg> &Ins,
2124 DebugLoc dl, SelectionDAG &DAG,
2125 SmallVectorImpl<SDValue> &InVals) const {
2126 MachineFunction &MF = DAG.getMachineFunction();
2127 bool Is64Bit = Subtarget->is64Bit();
2128 bool IsWin64 = Subtarget->isTargetWin64();
2129 bool IsStructRet = CallIsStructReturn(Outs);
2130 bool IsSibcall = false;
2133 // Check if it's really possible to do a tail call.
2134 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv,
2135 isVarArg, IsStructRet, MF.getFunction()->hasStructRetAttr(),
2136 Outs, OutVals, Ins, DAG);
2138 // Sibcalls are automatically detected tailcalls which do not require
2140 if (!MF.getTarget().Options.GuaranteedTailCallOpt && isTailCall)
2147 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
2148 "Var args not supported with calling convention fastcc or ghc");
2150 // Analyze operands of the call, assigning locations to each operand.
2151 SmallVector<CCValAssign, 16> ArgLocs;
2152 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(),
2153 ArgLocs, *DAG.getContext());
2155 // Allocate shadow area for Win64
2157 CCInfo.AllocateStack(32, 8);
2160 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
2162 // Get a count of how many bytes are to be pushed on the stack.
2163 unsigned NumBytes = CCInfo.getNextStackOffset();
2165 // This is a sibcall. The memory operands are available in caller's
2166 // own caller's stack.
2168 else if (getTargetMachine().Options.GuaranteedTailCallOpt &&
2169 IsTailCallConvention(CallConv))
2170 NumBytes = GetAlignedArgumentStackSize(NumBytes, DAG);
2173 if (isTailCall && !IsSibcall) {
2174 // Lower arguments at fp - stackoffset + fpdiff.
2175 unsigned NumBytesCallerPushed =
2176 MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn();
2177 FPDiff = NumBytesCallerPushed - NumBytes;
2179 // Set the delta of movement of the returnaddr stackslot.
2180 // But only set if delta is greater than previous delta.
2181 if (FPDiff < (MF.getInfo<X86MachineFunctionInfo>()->getTCReturnAddrDelta()))
2182 MF.getInfo<X86MachineFunctionInfo>()->setTCReturnAddrDelta(FPDiff);
2186 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true));
2188 SDValue RetAddrFrIdx;
2189 // Load return address for tail calls.
2190 if (isTailCall && FPDiff)
2191 Chain = EmitTailCallLoadRetAddr(DAG, RetAddrFrIdx, Chain, isTailCall,
2192 Is64Bit, FPDiff, dl);
2194 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
2195 SmallVector<SDValue, 8> MemOpChains;
2198 // Walk the register/memloc assignments, inserting copies/loads. In the case
2199 // of tail call optimization arguments are handle later.
2200 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2201 CCValAssign &VA = ArgLocs[i];
2202 EVT RegVT = VA.getLocVT();
2203 SDValue Arg = OutVals[i];
2204 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2205 bool isByVal = Flags.isByVal();
2207 // Promote the value if needed.
2208 switch (VA.getLocInfo()) {
2209 default: llvm_unreachable("Unknown loc info!");
2210 case CCValAssign::Full: break;
2211 case CCValAssign::SExt:
2212 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, RegVT, Arg);
2214 case CCValAssign::ZExt:
2215 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, RegVT, Arg);
2217 case CCValAssign::AExt:
2218 if (RegVT.isVector() && RegVT.getSizeInBits() == 128) {
2219 // Special case: passing MMX values in XMM registers.
2220 Arg = DAG.getNode(ISD::BITCAST, dl, MVT::i64, Arg);
2221 Arg = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, Arg);
2222 Arg = getMOVL(DAG, dl, MVT::v2i64, DAG.getUNDEF(MVT::v2i64), Arg);
2224 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, RegVT, Arg);
2226 case CCValAssign::BCvt:
2227 Arg = DAG.getNode(ISD::BITCAST, dl, RegVT, Arg);
2229 case CCValAssign::Indirect: {
2230 // Store the argument.
2231 SDValue SpillSlot = DAG.CreateStackTemporary(VA.getValVT());
2232 int FI = cast<FrameIndexSDNode>(SpillSlot)->getIndex();
2233 Chain = DAG.getStore(Chain, dl, Arg, SpillSlot,
2234 MachinePointerInfo::getFixedStack(FI),
2241 if (VA.isRegLoc()) {
2242 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
2243 if (isVarArg && IsWin64) {
2244 // Win64 ABI requires argument XMM reg to be copied to the corresponding
2245 // shadow reg if callee is a varargs function.
2246 unsigned ShadowReg = 0;
2247 switch (VA.getLocReg()) {
2248 case X86::XMM0: ShadowReg = X86::RCX; break;
2249 case X86::XMM1: ShadowReg = X86::RDX; break;
2250 case X86::XMM2: ShadowReg = X86::R8; break;
2251 case X86::XMM3: ShadowReg = X86::R9; break;
2254 RegsToPass.push_back(std::make_pair(ShadowReg, Arg));
2256 } else if (!IsSibcall && (!isTailCall || isByVal)) {
2257 assert(VA.isMemLoc());
2258 if (StackPtr.getNode() == 0)
2259 StackPtr = DAG.getCopyFromReg(Chain, dl, X86StackPtr, getPointerTy());
2260 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Arg,
2261 dl, DAG, VA, Flags));
2265 if (!MemOpChains.empty())
2266 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
2267 &MemOpChains[0], MemOpChains.size());
2269 // Build a sequence of copy-to-reg nodes chained together with token chain
2270 // and flag operands which copy the outgoing args into registers.
2272 // Tail call byval lowering might overwrite argument registers so in case of
2273 // tail call optimization the copies to registers are lowered later.
2275 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
2276 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
2277 RegsToPass[i].second, InFlag);
2278 InFlag = Chain.getValue(1);
2281 if (Subtarget->isPICStyleGOT()) {
2282 // ELF / PIC requires GOT in the EBX register before function calls via PLT
2285 Chain = DAG.getCopyToReg(Chain, dl, X86::EBX,
2286 DAG.getNode(X86ISD::GlobalBaseReg,
2287 DebugLoc(), getPointerTy()),
2289 InFlag = Chain.getValue(1);
2291 // If we are tail calling and generating PIC/GOT style code load the
2292 // address of the callee into ECX. The value in ecx is used as target of
2293 // the tail jump. This is done to circumvent the ebx/callee-saved problem
2294 // for tail calls on PIC/GOT architectures. Normally we would just put the
2295 // address of GOT into ebx and then call target@PLT. But for tail calls
2296 // ebx would be restored (since ebx is callee saved) before jumping to the
2299 // Note: The actual moving to ECX is done further down.
2300 GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee);
2301 if (G && !G->getGlobal()->hasHiddenVisibility() &&
2302 !G->getGlobal()->hasProtectedVisibility())
2303 Callee = LowerGlobalAddress(Callee, DAG);
2304 else if (isa<ExternalSymbolSDNode>(Callee))
2305 Callee = LowerExternalSymbol(Callee, DAG);
2309 if (Is64Bit && isVarArg && !IsWin64) {
2310 // From AMD64 ABI document:
2311 // For calls that may call functions that use varargs or stdargs
2312 // (prototype-less calls or calls to functions containing ellipsis (...) in
2313 // the declaration) %al is used as hidden argument to specify the number
2314 // of SSE registers used. The contents of %al do not need to match exactly
2315 // the number of registers, but must be an ubound on the number of SSE
2316 // registers used and is in the range 0 - 8 inclusive.
2318 // Count the number of XMM registers allocated.
2319 static const unsigned XMMArgRegs[] = {
2320 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
2321 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
2323 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs, 8);
2324 assert((Subtarget->hasSSE1() || !NumXMMRegs)
2325 && "SSE registers cannot be used when SSE is disabled");
2327 Chain = DAG.getCopyToReg(Chain, dl, X86::AL,
2328 DAG.getConstant(NumXMMRegs, MVT::i8), InFlag);
2329 InFlag = Chain.getValue(1);
2333 // For tail calls lower the arguments to the 'real' stack slot.
2335 // Force all the incoming stack arguments to be loaded from the stack
2336 // before any new outgoing arguments are stored to the stack, because the
2337 // outgoing stack slots may alias the incoming argument stack slots, and
2338 // the alias isn't otherwise explicit. This is slightly more conservative
2339 // than necessary, because it means that each store effectively depends
2340 // on every argument instead of just those arguments it would clobber.
2341 SDValue ArgChain = DAG.getStackArgumentTokenFactor(Chain);
2343 SmallVector<SDValue, 8> MemOpChains2;
2346 // Do not flag preceding copytoreg stuff together with the following stuff.
2348 if (getTargetMachine().Options.GuaranteedTailCallOpt) {
2349 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2350 CCValAssign &VA = ArgLocs[i];
2353 assert(VA.isMemLoc());
2354 SDValue Arg = OutVals[i];
2355 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2356 // Create frame index.
2357 int32_t Offset = VA.getLocMemOffset()+FPDiff;
2358 uint32_t OpSize = (VA.getLocVT().getSizeInBits()+7)/8;
2359 FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true);
2360 FIN = DAG.getFrameIndex(FI, getPointerTy());
2362 if (Flags.isByVal()) {
2363 // Copy relative to framepointer.
2364 SDValue Source = DAG.getIntPtrConstant(VA.getLocMemOffset());
2365 if (StackPtr.getNode() == 0)
2366 StackPtr = DAG.getCopyFromReg(Chain, dl, X86StackPtr,
2368 Source = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, Source);
2370 MemOpChains2.push_back(CreateCopyOfByValArgument(Source, FIN,
2374 // Store relative to framepointer.
2375 MemOpChains2.push_back(
2376 DAG.getStore(ArgChain, dl, Arg, FIN,
2377 MachinePointerInfo::getFixedStack(FI),
2383 if (!MemOpChains2.empty())
2384 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
2385 &MemOpChains2[0], MemOpChains2.size());
2387 // Copy arguments to their registers.
2388 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
2389 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
2390 RegsToPass[i].second, InFlag);
2391 InFlag = Chain.getValue(1);
2395 // Store the return address to the appropriate stack slot.
2396 Chain = EmitTailCallStoreRetAddr(DAG, MF, Chain, RetAddrFrIdx, Is64Bit,
2400 if (getTargetMachine().getCodeModel() == CodeModel::Large) {
2401 assert(Is64Bit && "Large code model is only legal in 64-bit mode.");
2402 // In the 64-bit large code model, we have to make all calls
2403 // through a register, since the call instruction's 32-bit
2404 // pc-relative offset may not be large enough to hold the whole
2406 } else if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
2407 // If the callee is a GlobalAddress node (quite common, every direct call
2408 // is) turn it into a TargetGlobalAddress node so that legalize doesn't hack
2411 // We should use extra load for direct calls to dllimported functions in
2413 const GlobalValue *GV = G->getGlobal();
2414 if (!GV->hasDLLImportLinkage()) {
2415 unsigned char OpFlags = 0;
2416 bool ExtraLoad = false;
2417 unsigned WrapperKind = ISD::DELETED_NODE;
2419 // On ELF targets, in both X86-64 and X86-32 mode, direct calls to
2420 // external symbols most go through the PLT in PIC mode. If the symbol
2421 // has hidden or protected visibility, or if it is static or local, then
2422 // we don't need to use the PLT - we can directly call it.
2423 if (Subtarget->isTargetELF() &&
2424 getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
2425 GV->hasDefaultVisibility() && !GV->hasLocalLinkage()) {
2426 OpFlags = X86II::MO_PLT;
2427 } else if (Subtarget->isPICStyleStubAny() &&
2428 (GV->isDeclaration() || GV->isWeakForLinker()) &&
2429 (!Subtarget->getTargetTriple().isMacOSX() ||
2430 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
2431 // PC-relative references to external symbols should go through $stub,
2432 // unless we're building with the leopard linker or later, which
2433 // automatically synthesizes these stubs.
2434 OpFlags = X86II::MO_DARWIN_STUB;
2435 } else if (Subtarget->isPICStyleRIPRel() &&
2436 isa<Function>(GV) &&
2437 cast<Function>(GV)->hasFnAttr(Attribute::NonLazyBind)) {
2438 // If the function is marked as non-lazy, generate an indirect call
2439 // which loads from the GOT directly. This avoids runtime overhead
2440 // at the cost of eager binding (and one extra byte of encoding).
2441 OpFlags = X86II::MO_GOTPCREL;
2442 WrapperKind = X86ISD::WrapperRIP;
2446 Callee = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(),
2447 G->getOffset(), OpFlags);
2449 // Add a wrapper if needed.
2450 if (WrapperKind != ISD::DELETED_NODE)
2451 Callee = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Callee);
2452 // Add extra indirection if needed.
2454 Callee = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Callee,
2455 MachinePointerInfo::getGOT(),
2456 false, false, false, 0);
2458 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
2459 unsigned char OpFlags = 0;
2461 // On ELF targets, in either X86-64 or X86-32 mode, direct calls to
2462 // external symbols should go through the PLT.
2463 if (Subtarget->isTargetELF() &&
2464 getTargetMachine().getRelocationModel() == Reloc::PIC_) {
2465 OpFlags = X86II::MO_PLT;
2466 } else if (Subtarget->isPICStyleStubAny() &&
2467 (!Subtarget->getTargetTriple().isMacOSX() ||
2468 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
2469 // PC-relative references to external symbols should go through $stub,
2470 // unless we're building with the leopard linker or later, which
2471 // automatically synthesizes these stubs.
2472 OpFlags = X86II::MO_DARWIN_STUB;
2475 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy(),
2479 // Returns a chain & a flag for retval copy to use.
2480 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
2481 SmallVector<SDValue, 8> Ops;
2483 if (!IsSibcall && isTailCall) {
2484 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
2485 DAG.getIntPtrConstant(0, true), InFlag);
2486 InFlag = Chain.getValue(1);
2489 Ops.push_back(Chain);
2490 Ops.push_back(Callee);
2493 Ops.push_back(DAG.getConstant(FPDiff, MVT::i32));
2495 // Add argument registers to the end of the list so that they are known live
2497 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
2498 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
2499 RegsToPass[i].second.getValueType()));
2501 // Add an implicit use GOT pointer in EBX.
2502 if (!isTailCall && Subtarget->isPICStyleGOT())
2503 Ops.push_back(DAG.getRegister(X86::EBX, getPointerTy()));
2505 // Add an implicit use of AL for non-Windows x86 64-bit vararg functions.
2506 if (Is64Bit && isVarArg && !IsWin64)
2507 Ops.push_back(DAG.getRegister(X86::AL, MVT::i8));
2509 if (InFlag.getNode())
2510 Ops.push_back(InFlag);
2514 //// If this is the first return lowered for this function, add the regs
2515 //// to the liveout set for the function.
2516 // This isn't right, although it's probably harmless on x86; liveouts
2517 // should be computed from returns not tail calls. Consider a void
2518 // function making a tail call to a function returning int.
2519 return DAG.getNode(X86ISD::TC_RETURN, dl,
2520 NodeTys, &Ops[0], Ops.size());
2523 Chain = DAG.getNode(X86ISD::CALL, dl, NodeTys, &Ops[0], Ops.size());
2524 InFlag = Chain.getValue(1);
2526 // Create the CALLSEQ_END node.
2527 unsigned NumBytesForCalleeToPush;
2528 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg,
2529 getTargetMachine().Options.GuaranteedTailCallOpt))
2530 NumBytesForCalleeToPush = NumBytes; // Callee pops everything
2531 else if (!Is64Bit && !IsTailCallConvention(CallConv) && IsStructRet)
2532 // If this is a call to a struct-return function, the callee
2533 // pops the hidden struct pointer, so we have to push it back.
2534 // This is common for Darwin/X86, Linux & Mingw32 targets.
2535 NumBytesForCalleeToPush = 4;
2537 NumBytesForCalleeToPush = 0; // Callee pops nothing.
2539 // Returns a flag for retval copy to use.
2541 Chain = DAG.getCALLSEQ_END(Chain,
2542 DAG.getIntPtrConstant(NumBytes, true),
2543 DAG.getIntPtrConstant(NumBytesForCalleeToPush,
2546 InFlag = Chain.getValue(1);
2549 // Handle result values, copying them out of physregs into vregs that we
2551 return LowerCallResult(Chain, InFlag, CallConv, isVarArg,
2552 Ins, dl, DAG, InVals);
2556 //===----------------------------------------------------------------------===//
2557 // Fast Calling Convention (tail call) implementation
2558 //===----------------------------------------------------------------------===//
2560 // Like std call, callee cleans arguments, convention except that ECX is
2561 // reserved for storing the tail called function address. Only 2 registers are
2562 // free for argument passing (inreg). Tail call optimization is performed
2564 // * tailcallopt is enabled
2565 // * caller/callee are fastcc
2566 // On X86_64 architecture with GOT-style position independent code only local
2567 // (within module) calls are supported at the moment.
2568 // To keep the stack aligned according to platform abi the function
2569 // GetAlignedArgumentStackSize ensures that argument delta is always multiples
2570 // of stack alignment. (Dynamic linkers need this - darwin's dyld for example)
2571 // If a tail called function callee has more arguments than the caller the
2572 // caller needs to make sure that there is room to move the RETADDR to. This is
2573 // achieved by reserving an area the size of the argument delta right after the
2574 // original REtADDR, but before the saved framepointer or the spilled registers
2575 // e.g. caller(arg1, arg2) calls callee(arg1, arg2,arg3,arg4)
2587 /// GetAlignedArgumentStackSize - Make the stack size align e.g 16n + 12 aligned
2588 /// for a 16 byte align requirement.
2590 X86TargetLowering::GetAlignedArgumentStackSize(unsigned StackSize,
2591 SelectionDAG& DAG) const {
2592 MachineFunction &MF = DAG.getMachineFunction();
2593 const TargetMachine &TM = MF.getTarget();
2594 const TargetFrameLowering &TFI = *TM.getFrameLowering();
2595 unsigned StackAlignment = TFI.getStackAlignment();
2596 uint64_t AlignMask = StackAlignment - 1;
2597 int64_t Offset = StackSize;
2598 uint64_t SlotSize = TD->getPointerSize();
2599 if ( (Offset & AlignMask) <= (StackAlignment - SlotSize) ) {
2600 // Number smaller than 12 so just add the difference.
2601 Offset += ((StackAlignment - SlotSize) - (Offset & AlignMask));
2603 // Mask out lower bits, add stackalignment once plus the 12 bytes.
2604 Offset = ((~AlignMask) & Offset) + StackAlignment +
2605 (StackAlignment-SlotSize);
2610 /// MatchingStackOffset - Return true if the given stack call argument is
2611 /// already available in the same position (relatively) of the caller's
2612 /// incoming argument stack.
2614 bool MatchingStackOffset(SDValue Arg, unsigned Offset, ISD::ArgFlagsTy Flags,
2615 MachineFrameInfo *MFI, const MachineRegisterInfo *MRI,
2616 const X86InstrInfo *TII) {
2617 unsigned Bytes = Arg.getValueType().getSizeInBits() / 8;
2619 if (Arg.getOpcode() == ISD::CopyFromReg) {
2620 unsigned VR = cast<RegisterSDNode>(Arg.getOperand(1))->getReg();
2621 if (!TargetRegisterInfo::isVirtualRegister(VR))
2623 MachineInstr *Def = MRI->getVRegDef(VR);
2626 if (!Flags.isByVal()) {
2627 if (!TII->isLoadFromStackSlot(Def, FI))
2630 unsigned Opcode = Def->getOpcode();
2631 if ((Opcode == X86::LEA32r || Opcode == X86::LEA64r) &&
2632 Def->getOperand(1).isFI()) {
2633 FI = Def->getOperand(1).getIndex();
2634 Bytes = Flags.getByValSize();
2638 } else if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Arg)) {
2639 if (Flags.isByVal())
2640 // ByVal argument is passed in as a pointer but it's now being
2641 // dereferenced. e.g.
2642 // define @foo(%struct.X* %A) {
2643 // tail call @bar(%struct.X* byval %A)
2646 SDValue Ptr = Ld->getBasePtr();
2647 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr);
2650 FI = FINode->getIndex();
2651 } else if (Arg.getOpcode() == ISD::FrameIndex && Flags.isByVal()) {
2652 FrameIndexSDNode *FINode = cast<FrameIndexSDNode>(Arg);
2653 FI = FINode->getIndex();
2654 Bytes = Flags.getByValSize();
2658 assert(FI != INT_MAX);
2659 if (!MFI->isFixedObjectIndex(FI))
2661 return Offset == MFI->getObjectOffset(FI) && Bytes == MFI->getObjectSize(FI);
2664 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
2665 /// for tail call optimization. Targets which want to do tail call
2666 /// optimization should implement this function.
2668 X86TargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
2669 CallingConv::ID CalleeCC,
2671 bool isCalleeStructRet,
2672 bool isCallerStructRet,
2673 const SmallVectorImpl<ISD::OutputArg> &Outs,
2674 const SmallVectorImpl<SDValue> &OutVals,
2675 const SmallVectorImpl<ISD::InputArg> &Ins,
2676 SelectionDAG& DAG) const {
2677 if (!IsTailCallConvention(CalleeCC) &&
2678 CalleeCC != CallingConv::C)
2681 // If -tailcallopt is specified, make fastcc functions tail-callable.
2682 const MachineFunction &MF = DAG.getMachineFunction();
2683 const Function *CallerF = DAG.getMachineFunction().getFunction();
2684 CallingConv::ID CallerCC = CallerF->getCallingConv();
2685 bool CCMatch = CallerCC == CalleeCC;
2687 if (getTargetMachine().Options.GuaranteedTailCallOpt) {
2688 if (IsTailCallConvention(CalleeCC) && CCMatch)
2693 // Look for obvious safe cases to perform tail call optimization that do not
2694 // require ABI changes. This is what gcc calls sibcall.
2696 // Can't do sibcall if stack needs to be dynamically re-aligned. PEI needs to
2697 // emit a special epilogue.
2698 if (RegInfo->needsStackRealignment(MF))
2701 // Also avoid sibcall optimization if either caller or callee uses struct
2702 // return semantics.
2703 if (isCalleeStructRet || isCallerStructRet)
2706 // An stdcall caller is expected to clean up its arguments; the callee
2707 // isn't going to do that.
2708 if (!CCMatch && CallerCC==CallingConv::X86_StdCall)
2711 // Do not sibcall optimize vararg calls unless all arguments are passed via
2713 if (isVarArg && !Outs.empty()) {
2715 // Optimizing for varargs on Win64 is unlikely to be safe without
2716 // additional testing.
2717 if (Subtarget->isTargetWin64())
2720 SmallVector<CCValAssign, 16> ArgLocs;
2721 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(),
2722 getTargetMachine(), ArgLocs, *DAG.getContext());
2724 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
2725 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i)
2726 if (!ArgLocs[i].isRegLoc())
2730 // If the call result is in ST0 / ST1, it needs to be popped off the x87
2731 // stack. Therefore, if it's not used by the call it is not safe to optimize
2732 // this into a sibcall.
2733 bool Unused = false;
2734 for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
2741 SmallVector<CCValAssign, 16> RVLocs;
2742 CCState CCInfo(CalleeCC, false, DAG.getMachineFunction(),
2743 getTargetMachine(), RVLocs, *DAG.getContext());
2744 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
2745 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
2746 CCValAssign &VA = RVLocs[i];
2747 if (VA.getLocReg() == X86::ST0 || VA.getLocReg() == X86::ST1)
2752 // If the calling conventions do not match, then we'd better make sure the
2753 // results are returned in the same way as what the caller expects.
2755 SmallVector<CCValAssign, 16> RVLocs1;
2756 CCState CCInfo1(CalleeCC, false, DAG.getMachineFunction(),
2757 getTargetMachine(), RVLocs1, *DAG.getContext());
2758 CCInfo1.AnalyzeCallResult(Ins, RetCC_X86);
2760 SmallVector<CCValAssign, 16> RVLocs2;
2761 CCState CCInfo2(CallerCC, false, DAG.getMachineFunction(),
2762 getTargetMachine(), RVLocs2, *DAG.getContext());
2763 CCInfo2.AnalyzeCallResult(Ins, RetCC_X86);
2765 if (RVLocs1.size() != RVLocs2.size())
2767 for (unsigned i = 0, e = RVLocs1.size(); i != e; ++i) {
2768 if (RVLocs1[i].isRegLoc() != RVLocs2[i].isRegLoc())
2770 if (RVLocs1[i].getLocInfo() != RVLocs2[i].getLocInfo())
2772 if (RVLocs1[i].isRegLoc()) {
2773 if (RVLocs1[i].getLocReg() != RVLocs2[i].getLocReg())
2776 if (RVLocs1[i].getLocMemOffset() != RVLocs2[i].getLocMemOffset())
2782 // If the callee takes no arguments then go on to check the results of the
2784 if (!Outs.empty()) {
2785 // Check if stack adjustment is needed. For now, do not do this if any
2786 // argument is passed on the stack.
2787 SmallVector<CCValAssign, 16> ArgLocs;
2788 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(),
2789 getTargetMachine(), ArgLocs, *DAG.getContext());
2791 // Allocate shadow area for Win64
2792 if (Subtarget->isTargetWin64()) {
2793 CCInfo.AllocateStack(32, 8);
2796 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
2797 if (CCInfo.getNextStackOffset()) {
2798 MachineFunction &MF = DAG.getMachineFunction();
2799 if (MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn())
2802 // Check if the arguments are already laid out in the right way as
2803 // the caller's fixed stack objects.
2804 MachineFrameInfo *MFI = MF.getFrameInfo();
2805 const MachineRegisterInfo *MRI = &MF.getRegInfo();
2806 const X86InstrInfo *TII =
2807 ((X86TargetMachine&)getTargetMachine()).getInstrInfo();
2808 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2809 CCValAssign &VA = ArgLocs[i];
2810 SDValue Arg = OutVals[i];
2811 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2812 if (VA.getLocInfo() == CCValAssign::Indirect)
2814 if (!VA.isRegLoc()) {
2815 if (!MatchingStackOffset(Arg, VA.getLocMemOffset(), Flags,
2822 // If the tailcall address may be in a register, then make sure it's
2823 // possible to register allocate for it. In 32-bit, the call address can
2824 // only target EAX, EDX, or ECX since the tail call must be scheduled after
2825 // callee-saved registers are restored. These happen to be the same
2826 // registers used to pass 'inreg' arguments so watch out for those.
2827 if (!Subtarget->is64Bit() &&
2828 !isa<GlobalAddressSDNode>(Callee) &&
2829 !isa<ExternalSymbolSDNode>(Callee)) {
2830 unsigned NumInRegs = 0;
2831 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2832 CCValAssign &VA = ArgLocs[i];
2835 unsigned Reg = VA.getLocReg();
2838 case X86::EAX: case X86::EDX: case X86::ECX:
2839 if (++NumInRegs == 3)
2851 X86TargetLowering::createFastISel(FunctionLoweringInfo &funcInfo) const {
2852 return X86::createFastISel(funcInfo);
2856 //===----------------------------------------------------------------------===//
2857 // Other Lowering Hooks
2858 //===----------------------------------------------------------------------===//
2860 static bool MayFoldLoad(SDValue Op) {
2861 return Op.hasOneUse() && ISD::isNormalLoad(Op.getNode());
2864 static bool MayFoldIntoStore(SDValue Op) {
2865 return Op.hasOneUse() && ISD::isNormalStore(*Op.getNode()->use_begin());
2868 static bool isTargetShuffle(unsigned Opcode) {
2870 default: return false;
2871 case X86ISD::PSHUFD:
2872 case X86ISD::PSHUFHW:
2873 case X86ISD::PSHUFLW:
2875 case X86ISD::PALIGN:
2876 case X86ISD::MOVLHPS:
2877 case X86ISD::MOVLHPD:
2878 case X86ISD::MOVHLPS:
2879 case X86ISD::MOVLPS:
2880 case X86ISD::MOVLPD:
2881 case X86ISD::MOVSHDUP:
2882 case X86ISD::MOVSLDUP:
2883 case X86ISD::MOVDDUP:
2886 case X86ISD::UNPCKL:
2887 case X86ISD::UNPCKH:
2888 case X86ISD::VPERMILP:
2889 case X86ISD::VPERM2X128:
2895 static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT,
2896 SDValue V1, SelectionDAG &DAG) {
2898 default: llvm_unreachable("Unknown x86 shuffle node");
2899 case X86ISD::MOVSHDUP:
2900 case X86ISD::MOVSLDUP:
2901 case X86ISD::MOVDDUP:
2902 return DAG.getNode(Opc, dl, VT, V1);
2908 static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT,
2909 SDValue V1, unsigned TargetMask, SelectionDAG &DAG) {
2911 default: llvm_unreachable("Unknown x86 shuffle node");
2912 case X86ISD::PSHUFD:
2913 case X86ISD::PSHUFHW:
2914 case X86ISD::PSHUFLW:
2915 case X86ISD::VPERMILP:
2916 return DAG.getNode(Opc, dl, VT, V1, DAG.getConstant(TargetMask, MVT::i8));
2922 static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT,
2923 SDValue V1, SDValue V2, unsigned TargetMask, SelectionDAG &DAG) {
2925 default: llvm_unreachable("Unknown x86 shuffle node");
2926 case X86ISD::PALIGN:
2928 case X86ISD::VPERM2X128:
2929 return DAG.getNode(Opc, dl, VT, V1, V2,
2930 DAG.getConstant(TargetMask, MVT::i8));
2935 static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT,
2936 SDValue V1, SDValue V2, SelectionDAG &DAG) {
2938 default: llvm_unreachable("Unknown x86 shuffle node");
2939 case X86ISD::MOVLHPS:
2940 case X86ISD::MOVLHPD:
2941 case X86ISD::MOVHLPS:
2942 case X86ISD::MOVLPS:
2943 case X86ISD::MOVLPD:
2946 case X86ISD::UNPCKL:
2947 case X86ISD::UNPCKH:
2948 return DAG.getNode(Opc, dl, VT, V1, V2);
2953 SDValue X86TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) const {
2954 MachineFunction &MF = DAG.getMachineFunction();
2955 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
2956 int ReturnAddrIndex = FuncInfo->getRAIndex();
2958 if (ReturnAddrIndex == 0) {
2959 // Set up a frame object for the return address.
2960 uint64_t SlotSize = TD->getPointerSize();
2961 ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(SlotSize, -SlotSize,
2963 FuncInfo->setRAIndex(ReturnAddrIndex);
2966 return DAG.getFrameIndex(ReturnAddrIndex, getPointerTy());
2970 bool X86::isOffsetSuitableForCodeModel(int64_t Offset, CodeModel::Model M,
2971 bool hasSymbolicDisplacement) {
2972 // Offset should fit into 32 bit immediate field.
2973 if (!isInt<32>(Offset))
2976 // If we don't have a symbolic displacement - we don't have any extra
2978 if (!hasSymbolicDisplacement)
2981 // FIXME: Some tweaks might be needed for medium code model.
2982 if (M != CodeModel::Small && M != CodeModel::Kernel)
2985 // For small code model we assume that latest object is 16MB before end of 31
2986 // bits boundary. We may also accept pretty large negative constants knowing
2987 // that all objects are in the positive half of address space.
2988 if (M == CodeModel::Small && Offset < 16*1024*1024)
2991 // For kernel code model we know that all object resist in the negative half
2992 // of 32bits address space. We may not accept negative offsets, since they may
2993 // be just off and we may accept pretty large positive ones.
2994 if (M == CodeModel::Kernel && Offset > 0)
3000 /// isCalleePop - Determines whether the callee is required to pop its
3001 /// own arguments. Callee pop is necessary to support tail calls.
3002 bool X86::isCalleePop(CallingConv::ID CallingConv,
3003 bool is64Bit, bool IsVarArg, bool TailCallOpt) {
3007 switch (CallingConv) {
3010 case CallingConv::X86_StdCall:
3012 case CallingConv::X86_FastCall:
3014 case CallingConv::X86_ThisCall:
3016 case CallingConv::Fast:
3018 case CallingConv::GHC:
3023 /// TranslateX86CC - do a one to one translation of a ISD::CondCode to the X86
3024 /// specific condition code, returning the condition code and the LHS/RHS of the
3025 /// comparison to make.
3026 static unsigned TranslateX86CC(ISD::CondCode SetCCOpcode, bool isFP,
3027 SDValue &LHS, SDValue &RHS, SelectionDAG &DAG) {
3029 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
3030 if (SetCCOpcode == ISD::SETGT && RHSC->isAllOnesValue()) {
3031 // X > -1 -> X == 0, jump !sign.
3032 RHS = DAG.getConstant(0, RHS.getValueType());
3033 return X86::COND_NS;
3034 } else if (SetCCOpcode == ISD::SETLT && RHSC->isNullValue()) {
3035 // X < 0 -> X == 0, jump on sign.
3037 } else if (SetCCOpcode == ISD::SETLT && RHSC->getZExtValue() == 1) {
3039 RHS = DAG.getConstant(0, RHS.getValueType());
3040 return X86::COND_LE;
3044 switch (SetCCOpcode) {
3045 default: llvm_unreachable("Invalid integer condition!");
3046 case ISD::SETEQ: return X86::COND_E;
3047 case ISD::SETGT: return X86::COND_G;
3048 case ISD::SETGE: return X86::COND_GE;
3049 case ISD::SETLT: return X86::COND_L;
3050 case ISD::SETLE: return X86::COND_LE;
3051 case ISD::SETNE: return X86::COND_NE;
3052 case ISD::SETULT: return X86::COND_B;
3053 case ISD::SETUGT: return X86::COND_A;
3054 case ISD::SETULE: return X86::COND_BE;
3055 case ISD::SETUGE: return X86::COND_AE;
3059 // First determine if it is required or is profitable to flip the operands.
3061 // If LHS is a foldable load, but RHS is not, flip the condition.
3062 if (ISD::isNON_EXTLoad(LHS.getNode()) &&
3063 !ISD::isNON_EXTLoad(RHS.getNode())) {
3064 SetCCOpcode = getSetCCSwappedOperands(SetCCOpcode);
3065 std::swap(LHS, RHS);
3068 switch (SetCCOpcode) {
3074 std::swap(LHS, RHS);
3078 // On a floating point condition, the flags are set as follows:
3080 // 0 | 0 | 0 | X > Y
3081 // 0 | 0 | 1 | X < Y
3082 // 1 | 0 | 0 | X == Y
3083 // 1 | 1 | 1 | unordered
3084 switch (SetCCOpcode) {
3085 default: llvm_unreachable("Condcode should be pre-legalized away");
3087 case ISD::SETEQ: return X86::COND_E;
3088 case ISD::SETOLT: // flipped
3090 case ISD::SETGT: return X86::COND_A;
3091 case ISD::SETOLE: // flipped
3093 case ISD::SETGE: return X86::COND_AE;
3094 case ISD::SETUGT: // flipped
3096 case ISD::SETLT: return X86::COND_B;
3097 case ISD::SETUGE: // flipped
3099 case ISD::SETLE: return X86::COND_BE;
3101 case ISD::SETNE: return X86::COND_NE;
3102 case ISD::SETUO: return X86::COND_P;
3103 case ISD::SETO: return X86::COND_NP;
3105 case ISD::SETUNE: return X86::COND_INVALID;
3109 /// hasFPCMov - is there a floating point cmov for the specific X86 condition
3110 /// code. Current x86 isa includes the following FP cmov instructions:
3111 /// fcmovb, fcomvbe, fcomve, fcmovu, fcmovae, fcmova, fcmovne, fcmovnu.
3112 static bool hasFPCMov(unsigned X86CC) {
3128 /// isFPImmLegal - Returns true if the target can instruction select the
3129 /// specified FP immediate natively. If false, the legalizer will
3130 /// materialize the FP immediate as a load from a constant pool.
3131 bool X86TargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
3132 for (unsigned i = 0, e = LegalFPImmediates.size(); i != e; ++i) {
3133 if (Imm.bitwiseIsEqual(LegalFPImmediates[i]))
3139 /// isUndefOrInRange - Return true if Val is undef or if its value falls within
3140 /// the specified range (L, H].
3141 static bool isUndefOrInRange(int Val, int Low, int Hi) {
3142 return (Val < 0) || (Val >= Low && Val < Hi);
3145 /// isUndefOrInRange - Return true if every element in Mask, begining
3146 /// from position Pos and ending in Pos+Size, falls within the specified
3147 /// range (L, L+Pos]. or is undef.
3148 static bool isUndefOrInRange(ArrayRef<int> Mask,
3149 int Pos, int Size, int Low, int Hi) {
3150 for (int i = Pos, e = Pos+Size; i != e; ++i)
3151 if (!isUndefOrInRange(Mask[i], Low, Hi))
3156 /// isUndefOrEqual - Val is either less than zero (undef) or equal to the
3157 /// specified value.
3158 static bool isUndefOrEqual(int Val, int CmpVal) {
3159 if (Val < 0 || Val == CmpVal)
3164 /// isSequentialOrUndefInRange - Return true if every element in Mask, begining
3165 /// from position Pos and ending in Pos+Size, falls within the specified
3166 /// sequential range (L, L+Pos]. or is undef.
3167 static bool isSequentialOrUndefInRange(ArrayRef<int> Mask,
3168 int Pos, int Size, int Low) {
3169 for (int i = Pos, e = Pos+Size; i != e; ++i, ++Low)
3170 if (!isUndefOrEqual(Mask[i], Low))
3175 /// isPSHUFDMask - Return true if the node specifies a shuffle of elements that
3176 /// is suitable for input to PSHUFD or PSHUFW. That is, it doesn't reference
3177 /// the second operand.
3178 static bool isPSHUFDMask(ArrayRef<int> Mask, EVT VT) {
3179 if (VT == MVT::v4f32 || VT == MVT::v4i32 )
3180 return (Mask[0] < 4 && Mask[1] < 4 && Mask[2] < 4 && Mask[3] < 4);
3181 if (VT == MVT::v2f64 || VT == MVT::v2i64)
3182 return (Mask[0] < 2 && Mask[1] < 2);
3186 bool X86::isPSHUFDMask(ShuffleVectorSDNode *N) {
3187 return ::isPSHUFDMask(N->getMask(), N->getValueType(0));
3190 /// isPSHUFHWMask - Return true if the node specifies a shuffle of elements that
3191 /// is suitable for input to PSHUFHW.
3192 static bool isPSHUFHWMask(ArrayRef<int> Mask, EVT VT) {
3193 if (VT != MVT::v8i16)
3196 // Lower quadword copied in order or undef.
3197 if (!isSequentialOrUndefInRange(Mask, 0, 4, 0))
3200 // Upper quadword shuffled.
3201 for (unsigned i = 4; i != 8; ++i)
3202 if (Mask[i] >= 0 && (Mask[i] < 4 || Mask[i] > 7))
3208 bool X86::isPSHUFHWMask(ShuffleVectorSDNode *N) {
3209 return ::isPSHUFHWMask(N->getMask(), N->getValueType(0));
3212 /// isPSHUFLWMask - Return true if the node specifies a shuffle of elements that
3213 /// is suitable for input to PSHUFLW.
3214 static bool isPSHUFLWMask(ArrayRef<int> Mask, EVT VT) {
3215 if (VT != MVT::v8i16)
3218 // Upper quadword copied in order.
3219 if (!isSequentialOrUndefInRange(Mask, 4, 4, 4))
3222 // Lower quadword shuffled.
3223 for (unsigned i = 0; i != 4; ++i)
3230 bool X86::isPSHUFLWMask(ShuffleVectorSDNode *N) {
3231 return ::isPSHUFLWMask(N->getMask(), N->getValueType(0));
3234 /// isPALIGNRMask - Return true if the node specifies a shuffle of elements that
3235 /// is suitable for input to PALIGNR.
3236 static bool isPALIGNRMask(ArrayRef<int> Mask, EVT VT, bool hasSSSE3) {
3237 int i, e = VT.getVectorNumElements();
3238 if (VT.getSizeInBits() != 128)
3241 // Do not handle v2i64 / v2f64 shuffles with palignr.
3242 if (e < 4 || !hasSSSE3)
3245 for (i = 0; i != e; ++i)
3249 // All undef, not a palignr.
3253 // Make sure we're shifting in the right direction.
3257 int s = Mask[i] - i;
3259 // Check the rest of the elements to see if they are consecutive.
3260 for (++i; i != e; ++i) {
3262 if (m >= 0 && m != s+i)
3268 /// isVSHUFPYMask - Return true if the specified VECTOR_SHUFFLE operand
3269 /// specifies a shuffle of elements that is suitable for input to 256-bit
3271 static bool isVSHUFPYMask(ArrayRef<int> Mask, EVT VT,
3272 bool HasAVX, bool Commuted = false) {
3273 int NumElems = VT.getVectorNumElements();
3275 if (!HasAVX || VT.getSizeInBits() != 256)
3278 if (NumElems != 4 && NumElems != 8)
3281 // VSHUFPSY divides the resulting vector into 4 chunks.
3282 // The sources are also splitted into 4 chunks, and each destination
3283 // chunk must come from a different source chunk.
3285 // SRC1 => X7 X6 X5 X4 X3 X2 X1 X0
3286 // SRC2 => Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y9
3288 // DST => Y7..Y4, Y7..Y4, X7..X4, X7..X4,
3289 // Y3..Y0, Y3..Y0, X3..X0, X3..X0
3291 // VSHUFPDY divides the resulting vector into 4 chunks.
3292 // The sources are also splitted into 4 chunks, and each destination
3293 // chunk must come from a different source chunk.
3295 // SRC1 => X3 X2 X1 X0
3296 // SRC2 => Y3 Y2 Y1 Y0
3298 // DST => Y3..Y2, X3..X2, Y1..Y0, X1..X0
3300 unsigned QuarterSize = NumElems/4;
3301 unsigned HalfSize = QuarterSize*2;
3302 for (unsigned l = 0; l != 2; ++l) {
3303 unsigned LaneStart = l*HalfSize;
3304 for (unsigned s = 0; s != 2; ++s) {
3305 unsigned QuarterStart = s*QuarterSize;
3306 unsigned Src = (Commuted) ? (1-s) : s;
3307 unsigned SrcStart = Src*NumElems + LaneStart;
3308 for (unsigned i = 0; i != QuarterSize; ++i) {
3309 int Idx = Mask[i+QuarterStart+LaneStart];
3310 if (!isUndefOrInRange(Idx, SrcStart, SrcStart+HalfSize))
3312 // For VSHUFPSY, the mask of the second half must be the same as the
3313 // first but with the appropriate offsets. This works in the same way as
3314 // VPERMILPS works with masks.
3315 if (NumElems == 4 || l == 0 || Mask[i+QuarterStart] < 0)
3317 if (!isUndefOrEqual(Idx, Mask[i+QuarterStart]+LaneStart))
3326 /// getShuffleVSHUFPYImmediate - Return the appropriate immediate to shuffle
3327 /// the specified VECTOR_MASK mask with VSHUFPSY/VSHUFPDY instructions.
3328 static unsigned getShuffleVSHUFPYImmediate(ShuffleVectorSDNode *SVOp) {
3329 EVT VT = SVOp->getValueType(0);
3330 unsigned NumElems = VT.getVectorNumElements();
3332 assert(VT.getSizeInBits() == 256 && "Only supports 256-bit types");
3333 assert((NumElems == 4 || NumElems == 8) && "Only supports v4 and v8 types");
3335 unsigned HalfSize = NumElems/2;
3336 unsigned Mul = (NumElems == 8) ? 2 : 1;
3338 for (unsigned i = 0; i != NumElems; ++i) {
3339 int Elt = SVOp->getMaskElt(i);
3344 // For VSHUFPSY, the mask of the first half must be equal to the second one.
3345 if (NumElems == 8) Shamt %= HalfSize;
3346 Mask |= Elt << (Shamt*Mul);
3352 /// CommuteVectorShuffleMask - Change values in a shuffle permute mask assuming
3353 /// the two vector operands have swapped position.
3354 static void CommuteVectorShuffleMask(SmallVectorImpl<int> &Mask,
3355 unsigned NumElems) {
3356 for (unsigned i = 0; i != NumElems; ++i) {
3360 else if (idx < (int)NumElems)
3361 Mask[i] = idx + NumElems;
3363 Mask[i] = idx - NumElems;
3367 /// isSHUFPMask - Return true if the specified VECTOR_SHUFFLE operand
3368 /// specifies a shuffle of elements that is suitable for input to 128-bit
3369 /// SHUFPS and SHUFPD. If Commuted is true, then it checks for sources to be
3370 /// reverse of what x86 shuffles want.
3371 static bool isSHUFPMask(ArrayRef<int> Mask, EVT VT, bool Commuted = false) {
3372 unsigned NumElems = VT.getVectorNumElements();
3374 if (VT.getSizeInBits() != 128)
3377 if (NumElems != 2 && NumElems != 4)
3380 unsigned Half = NumElems / 2;
3381 unsigned SrcStart = Commuted ? NumElems : 0;
3382 for (unsigned i = 0; i != Half; ++i)
3383 if (!isUndefOrInRange(Mask[i], SrcStart, SrcStart+NumElems))
3385 SrcStart = Commuted ? 0 : NumElems;
3386 for (unsigned i = Half; i != NumElems; ++i)
3387 if (!isUndefOrInRange(Mask[i], SrcStart, SrcStart+NumElems))
3393 bool X86::isSHUFPMask(ShuffleVectorSDNode *N) {
3394 return ::isSHUFPMask(N->getMask(), N->getValueType(0));
3397 /// isMOVHLPSMask - Return true if the specified VECTOR_SHUFFLE operand
3398 /// specifies a shuffle of elements that is suitable for input to MOVHLPS.
3399 bool X86::isMOVHLPSMask(ShuffleVectorSDNode *N) {
3400 EVT VT = N->getValueType(0);
3401 unsigned NumElems = VT.getVectorNumElements();
3403 if (VT.getSizeInBits() != 128)
3409 // Expect bit0 == 6, bit1 == 7, bit2 == 2, bit3 == 3
3410 return isUndefOrEqual(N->getMaskElt(0), 6) &&
3411 isUndefOrEqual(N->getMaskElt(1), 7) &&
3412 isUndefOrEqual(N->getMaskElt(2), 2) &&
3413 isUndefOrEqual(N->getMaskElt(3), 3);
3416 /// isMOVHLPS_v_undef_Mask - Special case of isMOVHLPSMask for canonical form
3417 /// of vector_shuffle v, v, <2, 3, 2, 3>, i.e. vector_shuffle v, undef,
3419 bool X86::isMOVHLPS_v_undef_Mask(ShuffleVectorSDNode *N) {
3420 EVT VT = N->getValueType(0);
3421 unsigned NumElems = VT.getVectorNumElements();
3423 if (VT.getSizeInBits() != 128)
3429 return isUndefOrEqual(N->getMaskElt(0), 2) &&
3430 isUndefOrEqual(N->getMaskElt(1), 3) &&
3431 isUndefOrEqual(N->getMaskElt(2), 2) &&
3432 isUndefOrEqual(N->getMaskElt(3), 3);
3435 /// isMOVLPMask - Return true if the specified VECTOR_SHUFFLE operand
3436 /// specifies a shuffle of elements that is suitable for input to MOVLP{S|D}.
3437 bool X86::isMOVLPMask(ShuffleVectorSDNode *N) {
3438 EVT VT = N->getValueType(0);
3440 if (VT.getSizeInBits() != 128)
3443 unsigned NumElems = N->getValueType(0).getVectorNumElements();
3445 if (NumElems != 2 && NumElems != 4)
3448 for (unsigned i = 0; i < NumElems/2; ++i)
3449 if (!isUndefOrEqual(N->getMaskElt(i), i + NumElems))
3452 for (unsigned i = NumElems/2; i < NumElems; ++i)
3453 if (!isUndefOrEqual(N->getMaskElt(i), i))
3459 /// isMOVLHPSMask - Return true if the specified VECTOR_SHUFFLE operand
3460 /// specifies a shuffle of elements that is suitable for input to MOVLHPS.
3461 bool X86::isMOVLHPSMask(ShuffleVectorSDNode *N) {
3462 unsigned NumElems = N->getValueType(0).getVectorNumElements();
3464 if ((NumElems != 2 && NumElems != 4)
3465 || N->getValueType(0).getSizeInBits() > 128)
3468 for (unsigned i = 0; i < NumElems/2; ++i)
3469 if (!isUndefOrEqual(N->getMaskElt(i), i))
3472 for (unsigned i = 0; i < NumElems/2; ++i)
3473 if (!isUndefOrEqual(N->getMaskElt(i + NumElems/2), i + NumElems))
3479 /// isUNPCKLMask - Return true if the specified VECTOR_SHUFFLE operand
3480 /// specifies a shuffle of elements that is suitable for input to UNPCKL.
3481 static bool isUNPCKLMask(ArrayRef<int> Mask, EVT VT,
3482 bool HasAVX2, bool V2IsSplat = false) {
3483 unsigned NumElts = VT.getVectorNumElements();
3485 assert((VT.is128BitVector() || VT.is256BitVector()) &&
3486 "Unsupported vector type for unpckh");
3488 if (VT.getSizeInBits() == 256 && NumElts != 4 && NumElts != 8 &&
3489 (!HasAVX2 || (NumElts != 16 && NumElts != 32)))
3492 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
3493 // independently on 128-bit lanes.
3494 unsigned NumLanes = VT.getSizeInBits()/128;
3495 unsigned NumLaneElts = NumElts/NumLanes;
3497 for (unsigned l = 0; l != NumLanes; ++l) {
3498 for (unsigned i = l*NumLaneElts, j = l*NumLaneElts;
3499 i != (l+1)*NumLaneElts;
3502 int BitI1 = Mask[i+1];
3503 if (!isUndefOrEqual(BitI, j))
3506 if (!isUndefOrEqual(BitI1, NumElts))
3509 if (!isUndefOrEqual(BitI1, j + NumElts))
3518 bool X86::isUNPCKLMask(ShuffleVectorSDNode *N, bool HasAVX2, bool V2IsSplat) {
3519 return ::isUNPCKLMask(N->getMask(), N->getValueType(0), HasAVX2, V2IsSplat);
3522 /// isUNPCKHMask - Return true if the specified VECTOR_SHUFFLE operand
3523 /// specifies a shuffle of elements that is suitable for input to UNPCKH.
3524 static bool isUNPCKHMask(ArrayRef<int> Mask, EVT VT,
3525 bool HasAVX2, bool V2IsSplat = false) {
3526 unsigned NumElts = VT.getVectorNumElements();
3528 assert((VT.is128BitVector() || VT.is256BitVector()) &&
3529 "Unsupported vector type for unpckh");
3531 if (VT.getSizeInBits() == 256 && NumElts != 4 && NumElts != 8 &&
3532 (!HasAVX2 || (NumElts != 16 && NumElts != 32)))
3535 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
3536 // independently on 128-bit lanes.
3537 unsigned NumLanes = VT.getSizeInBits()/128;
3538 unsigned NumLaneElts = NumElts/NumLanes;
3540 for (unsigned l = 0; l != NumLanes; ++l) {
3541 for (unsigned i = l*NumLaneElts, j = (l*NumLaneElts)+NumLaneElts/2;
3542 i != (l+1)*NumLaneElts; i += 2, ++j) {
3544 int BitI1 = Mask[i+1];
3545 if (!isUndefOrEqual(BitI, j))
3548 if (isUndefOrEqual(BitI1, NumElts))
3551 if (!isUndefOrEqual(BitI1, j+NumElts))
3559 bool X86::isUNPCKHMask(ShuffleVectorSDNode *N, bool HasAVX2, bool V2IsSplat) {
3560 return ::isUNPCKHMask(N->getMask(), N->getValueType(0), HasAVX2, V2IsSplat);
3563 /// isUNPCKL_v_undef_Mask - Special case of isUNPCKLMask for canonical form
3564 /// of vector_shuffle v, v, <0, 4, 1, 5>, i.e. vector_shuffle v, undef,
3566 static bool isUNPCKL_v_undef_Mask(ArrayRef<int> Mask, EVT VT,
3568 unsigned NumElts = VT.getVectorNumElements();
3570 assert((VT.is128BitVector() || VT.is256BitVector()) &&
3571 "Unsupported vector type for unpckh");
3573 if (VT.getSizeInBits() == 256 && NumElts != 4 && NumElts != 8 &&
3574 (!HasAVX2 || (NumElts != 16 && NumElts != 32)))
3577 // For 256-bit i64/f64, use MOVDDUPY instead, so reject the matching pattern
3578 // FIXME: Need a better way to get rid of this, there's no latency difference
3579 // between UNPCKLPD and MOVDDUP, the later should always be checked first and
3580 // the former later. We should also remove the "_undef" special mask.
3581 if (NumElts == 4 && VT.getSizeInBits() == 256)
3584 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
3585 // independently on 128-bit lanes.
3586 unsigned NumLanes = VT.getSizeInBits()/128;
3587 unsigned NumLaneElts = NumElts/NumLanes;
3589 for (unsigned l = 0; l != NumLanes; ++l) {
3590 for (unsigned i = l*NumLaneElts, j = l*NumLaneElts;
3591 i != (l+1)*NumLaneElts;
3594 int BitI1 = Mask[i+1];
3596 if (!isUndefOrEqual(BitI, j))
3598 if (!isUndefOrEqual(BitI1, j))
3606 bool X86::isUNPCKL_v_undef_Mask(ShuffleVectorSDNode *N, bool HasAVX2) {
3607 return ::isUNPCKL_v_undef_Mask(N->getMask(), N->getValueType(0), HasAVX2);
3610 /// isUNPCKH_v_undef_Mask - Special case of isUNPCKHMask for canonical form
3611 /// of vector_shuffle v, v, <2, 6, 3, 7>, i.e. vector_shuffle v, undef,
3613 static bool isUNPCKH_v_undef_Mask(ArrayRef<int> Mask, EVT VT, bool HasAVX2) {
3614 unsigned NumElts = VT.getVectorNumElements();
3616 assert((VT.is128BitVector() || VT.is256BitVector()) &&
3617 "Unsupported vector type for unpckh");
3619 if (VT.getSizeInBits() == 256 && NumElts != 4 && NumElts != 8 &&
3620 (!HasAVX2 || (NumElts != 16 && NumElts != 32)))
3623 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
3624 // independently on 128-bit lanes.
3625 unsigned NumLanes = VT.getSizeInBits()/128;
3626 unsigned NumLaneElts = NumElts/NumLanes;
3628 for (unsigned l = 0; l != NumLanes; ++l) {
3629 for (unsigned i = l*NumLaneElts, j = (l*NumLaneElts)+NumLaneElts/2;
3630 i != (l+1)*NumLaneElts; i += 2, ++j) {
3632 int BitI1 = Mask[i+1];
3633 if (!isUndefOrEqual(BitI, j))
3635 if (!isUndefOrEqual(BitI1, j))
3642 bool X86::isUNPCKH_v_undef_Mask(ShuffleVectorSDNode *N, bool HasAVX2) {
3643 return ::isUNPCKH_v_undef_Mask(N->getMask(), N->getValueType(0), HasAVX2);
3646 /// isMOVLMask - Return true if the specified VECTOR_SHUFFLE operand
3647 /// specifies a shuffle of elements that is suitable for input to MOVSS,
3648 /// MOVSD, and MOVD, i.e. setting the lowest element.
3649 static bool isMOVLMask(ArrayRef<int> Mask, EVT VT) {
3650 if (VT.getVectorElementType().getSizeInBits() < 32)
3652 if (VT.getSizeInBits() == 256)
3655 unsigned NumElts = VT.getVectorNumElements();
3657 if (!isUndefOrEqual(Mask[0], NumElts))
3660 for (unsigned i = 1; i != NumElts; ++i)
3661 if (!isUndefOrEqual(Mask[i], i))
3667 bool X86::isMOVLMask(ShuffleVectorSDNode *N) {
3668 return ::isMOVLMask(N->getMask(), N->getValueType(0));
3671 /// isVPERM2X128Mask - Match 256-bit shuffles where the elements are considered
3672 /// as permutations between 128-bit chunks or halves. As an example: this
3674 /// vector_shuffle <4, 5, 6, 7, 12, 13, 14, 15>
3675 /// The first half comes from the second half of V1 and the second half from the
3676 /// the second half of V2.
3677 static bool isVPERM2X128Mask(ArrayRef<int> Mask, EVT VT, bool HasAVX) {
3678 if (!HasAVX || VT.getSizeInBits() != 256)
3681 // The shuffle result is divided into half A and half B. In total the two
3682 // sources have 4 halves, namely: C, D, E, F. The final values of A and
3683 // B must come from C, D, E or F.
3684 unsigned HalfSize = VT.getVectorNumElements()/2;
3685 bool MatchA = false, MatchB = false;
3687 // Check if A comes from one of C, D, E, F.
3688 for (unsigned Half = 0; Half != 4; ++Half) {
3689 if (isSequentialOrUndefInRange(Mask, 0, HalfSize, Half*HalfSize)) {
3695 // Check if B comes from one of C, D, E, F.
3696 for (unsigned Half = 0; Half != 4; ++Half) {
3697 if (isSequentialOrUndefInRange(Mask, HalfSize, HalfSize, Half*HalfSize)) {
3703 return MatchA && MatchB;
3706 /// getShuffleVPERM2X128Immediate - Return the appropriate immediate to shuffle
3707 /// the specified VECTOR_MASK mask with VPERM2F128/VPERM2I128 instructions.
3708 static unsigned getShuffleVPERM2X128Immediate(ShuffleVectorSDNode *SVOp) {
3709 EVT VT = SVOp->getValueType(0);
3711 unsigned HalfSize = VT.getVectorNumElements()/2;
3713 unsigned FstHalf = 0, SndHalf = 0;
3714 for (unsigned i = 0; i < HalfSize; ++i) {
3715 if (SVOp->getMaskElt(i) > 0) {
3716 FstHalf = SVOp->getMaskElt(i)/HalfSize;
3720 for (unsigned i = HalfSize; i < HalfSize*2; ++i) {
3721 if (SVOp->getMaskElt(i) > 0) {
3722 SndHalf = SVOp->getMaskElt(i)/HalfSize;
3727 return (FstHalf | (SndHalf << 4));
3730 /// isVPERMILPMask - Return true if the specified VECTOR_SHUFFLE operand
3731 /// specifies a shuffle of elements that is suitable for input to VPERMILPD*.
3732 /// Note that VPERMIL mask matching is different depending whether theunderlying
3733 /// type is 32 or 64. In the VPERMILPS the high half of the mask should point
3734 /// to the same elements of the low, but to the higher half of the source.
3735 /// In VPERMILPD the two lanes could be shuffled independently of each other
3736 /// with the same restriction that lanes can't be crossed.
3737 static bool isVPERMILPMask(ArrayRef<int> Mask, EVT VT, bool HasAVX) {
3741 unsigned NumElts = VT.getVectorNumElements();
3742 // Only match 256-bit with 32/64-bit types
3743 if (VT.getSizeInBits() != 256 || (NumElts != 4 && NumElts != 8))
3746 unsigned NumLanes = VT.getSizeInBits()/128;
3747 unsigned LaneSize = NumElts/NumLanes;
3748 for (unsigned l = 0; l != NumLanes; ++l) {
3749 unsigned LaneStart = l*LaneSize;
3750 for (unsigned i = 0; i != LaneSize; ++i) {
3751 if (!isUndefOrInRange(Mask[i+LaneStart], LaneStart, LaneStart+LaneSize))
3753 if (NumElts == 4 || l == 0)
3755 // VPERMILPS handling
3758 if (!isUndefOrEqual(Mask[i+LaneStart], Mask[i]+LaneStart))
3766 /// getShuffleVPERMILPImmediate - Return the appropriate immediate to shuffle
3767 /// the specified VECTOR_MASK mask with VPERMILPS/D* instructions.
3768 static unsigned getShuffleVPERMILPImmediate(ShuffleVectorSDNode *SVOp) {
3769 EVT VT = SVOp->getValueType(0);
3771 unsigned NumElts = VT.getVectorNumElements();
3772 unsigned NumLanes = VT.getSizeInBits()/128;
3773 unsigned LaneSize = NumElts/NumLanes;
3775 // Although the mask is equal for both lanes do it twice to get the cases
3776 // where a mask will match because the same mask element is undef on the
3777 // first half but valid on the second. This would get pathological cases
3778 // such as: shuffle <u, 0, 1, 2, 4, 4, 5, 6>, which is completely valid.
3779 unsigned Shift = (LaneSize == 4) ? 2 : 1;
3781 for (unsigned i = 0; i != NumElts; ++i) {
3782 int MaskElt = SVOp->getMaskElt(i);
3785 MaskElt %= LaneSize;
3787 // VPERMILPSY, the mask of the first half must be equal to the second one
3788 if (NumElts == 8) Shamt %= LaneSize;
3789 Mask |= MaskElt << (Shamt*Shift);
3795 /// isCommutedMOVL - Returns true if the shuffle mask is except the reverse
3796 /// of what x86 movss want. X86 movs requires the lowest element to be lowest
3797 /// element of vector 2 and the other elements to come from vector 1 in order.
3798 static bool isCommutedMOVLMask(ArrayRef<int> Mask, EVT VT,
3799 bool V2IsSplat = false, bool V2IsUndef = false) {
3800 unsigned NumOps = VT.getVectorNumElements();
3801 if (NumOps != 2 && NumOps != 4 && NumOps != 8 && NumOps != 16)
3804 if (!isUndefOrEqual(Mask[0], 0))
3807 for (unsigned i = 1; i != NumOps; ++i)
3808 if (!(isUndefOrEqual(Mask[i], i+NumOps) ||
3809 (V2IsUndef && isUndefOrInRange(Mask[i], NumOps, NumOps*2)) ||
3810 (V2IsSplat && isUndefOrEqual(Mask[i], NumOps))))
3816 static bool isCommutedMOVL(ShuffleVectorSDNode *N, bool V2IsSplat = false,
3817 bool V2IsUndef = false) {
3818 return isCommutedMOVLMask(N->getMask(), N->getValueType(0),
3819 V2IsSplat, V2IsUndef);
3822 /// isMOVSHDUPMask - Return true if the specified VECTOR_SHUFFLE operand
3823 /// specifies a shuffle of elements that is suitable for input to MOVSHDUP.
3824 /// Masks to match: <1, 1, 3, 3> or <1, 1, 3, 3, 5, 5, 7, 7>
3825 bool X86::isMOVSHDUPMask(ShuffleVectorSDNode *N,
3826 const X86Subtarget *Subtarget) {
3827 if (!Subtarget->hasSSE3())
3830 // The second vector must be undef
3831 if (N->getOperand(1).getOpcode() != ISD::UNDEF)
3834 EVT VT = N->getValueType(0);
3835 unsigned NumElems = VT.getVectorNumElements();
3837 if ((VT.getSizeInBits() == 128 && NumElems != 4) ||
3838 (VT.getSizeInBits() == 256 && NumElems != 8))
3841 // "i+1" is the value the indexed mask element must have
3842 for (unsigned i = 0; i < NumElems; i += 2)
3843 if (!isUndefOrEqual(N->getMaskElt(i), i+1) ||
3844 !isUndefOrEqual(N->getMaskElt(i+1), i+1))
3850 /// isMOVSLDUPMask - Return true if the specified VECTOR_SHUFFLE operand
3851 /// specifies a shuffle of elements that is suitable for input to MOVSLDUP.
3852 /// Masks to match: <0, 0, 2, 2> or <0, 0, 2, 2, 4, 4, 6, 6>
3853 bool X86::isMOVSLDUPMask(ShuffleVectorSDNode *N,
3854 const X86Subtarget *Subtarget) {
3855 if (!Subtarget->hasSSE3())
3858 // The second vector must be undef
3859 if (N->getOperand(1).getOpcode() != ISD::UNDEF)
3862 EVT VT = N->getValueType(0);
3863 unsigned NumElems = VT.getVectorNumElements();
3865 if ((VT.getSizeInBits() == 128 && NumElems != 4) ||
3866 (VT.getSizeInBits() == 256 && NumElems != 8))
3869 // "i" is the value the indexed mask element must have
3870 for (unsigned i = 0; i != NumElems; i += 2)
3871 if (!isUndefOrEqual(N->getMaskElt(i), i) ||
3872 !isUndefOrEqual(N->getMaskElt(i+1), i))
3878 /// isMOVDDUPYMask - Return true if the specified VECTOR_SHUFFLE operand
3879 /// specifies a shuffle of elements that is suitable for input to 256-bit
3880 /// version of MOVDDUP.
3881 static bool isMOVDDUPYMask(ArrayRef<int> Mask, EVT VT, bool HasAVX) {
3882 unsigned NumElts = VT.getVectorNumElements();
3884 if (!HasAVX || VT.getSizeInBits() != 256 || NumElts != 4)
3887 for (unsigned i = 0; i != NumElts/2; ++i)
3888 if (!isUndefOrEqual(Mask[i], 0))
3890 for (unsigned i = NumElts/2; i != NumElts; ++i)
3891 if (!isUndefOrEqual(Mask[i], NumElts/2))
3896 /// isMOVDDUPMask - Return true if the specified VECTOR_SHUFFLE operand
3897 /// specifies a shuffle of elements that is suitable for input to 128-bit
3898 /// version of MOVDDUP.
3899 bool X86::isMOVDDUPMask(ShuffleVectorSDNode *N) {
3900 EVT VT = N->getValueType(0);
3902 if (VT.getSizeInBits() != 128)
3905 unsigned e = VT.getVectorNumElements() / 2;
3906 for (unsigned i = 0; i != e; ++i)
3907 if (!isUndefOrEqual(N->getMaskElt(i), i))
3909 for (unsigned i = 0; i != e; ++i)
3910 if (!isUndefOrEqual(N->getMaskElt(e+i), i))
3915 /// isVEXTRACTF128Index - Return true if the specified
3916 /// EXTRACT_SUBVECTOR operand specifies a vector extract that is
3917 /// suitable for input to VEXTRACTF128.
3918 bool X86::isVEXTRACTF128Index(SDNode *N) {
3919 if (!isa<ConstantSDNode>(N->getOperand(1).getNode()))
3922 // The index should be aligned on a 128-bit boundary.
3924 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
3926 unsigned VL = N->getValueType(0).getVectorNumElements();
3927 unsigned VBits = N->getValueType(0).getSizeInBits();
3928 unsigned ElSize = VBits / VL;
3929 bool Result = (Index * ElSize) % 128 == 0;
3934 /// isVINSERTF128Index - Return true if the specified INSERT_SUBVECTOR
3935 /// operand specifies a subvector insert that is suitable for input to
3937 bool X86::isVINSERTF128Index(SDNode *N) {
3938 if (!isa<ConstantSDNode>(N->getOperand(2).getNode()))
3941 // The index should be aligned on a 128-bit boundary.
3943 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
3945 unsigned VL = N->getValueType(0).getVectorNumElements();
3946 unsigned VBits = N->getValueType(0).getSizeInBits();
3947 unsigned ElSize = VBits / VL;
3948 bool Result = (Index * ElSize) % 128 == 0;
3953 /// getShuffleSHUFImmediate - Return the appropriate immediate to shuffle
3954 /// the specified VECTOR_SHUFFLE mask with PSHUF* and SHUFP* instructions.
3955 unsigned X86::getShuffleSHUFImmediate(SDNode *N) {
3956 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
3957 unsigned NumOperands = SVOp->getValueType(0).getVectorNumElements();
3959 unsigned Shift = (NumOperands == 4) ? 2 : 1;
3961 for (unsigned i = 0; i != NumOperands; ++i) {
3962 int Val = SVOp->getMaskElt(NumOperands-i-1);
3963 if (Val < 0) Val = 0;
3964 if (Val >= (int)NumOperands) Val -= NumOperands;
3966 if (i != NumOperands - 1)
3972 /// getShufflePSHUFHWImmediate - Return the appropriate immediate to shuffle
3973 /// the specified VECTOR_SHUFFLE mask with the PSHUFHW instruction.
3974 unsigned X86::getShufflePSHUFHWImmediate(SDNode *N) {
3975 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
3977 // 8 nodes, but we only care about the last 4.
3978 for (unsigned i = 7; i >= 4; --i) {
3979 int Val = SVOp->getMaskElt(i);
3988 /// getShufflePSHUFLWImmediate - Return the appropriate immediate to shuffle
3989 /// the specified VECTOR_SHUFFLE mask with the PSHUFLW instruction.
3990 unsigned X86::getShufflePSHUFLWImmediate(SDNode *N) {
3991 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
3993 // 8 nodes, but we only care about the first 4.
3994 for (int i = 3; i >= 0; --i) {
3995 int Val = SVOp->getMaskElt(i);
4004 /// getShufflePALIGNRImmediate - Return the appropriate immediate to shuffle
4005 /// the specified VECTOR_SHUFFLE mask with the PALIGNR instruction.
4006 static unsigned getShufflePALIGNRImmediate(ShuffleVectorSDNode *SVOp) {
4007 EVT VT = SVOp->getValueType(0);
4008 unsigned EltSize = VT.getVectorElementType().getSizeInBits() >> 3;
4012 for (i = 0, e = VT.getVectorNumElements(); i != e; ++i) {
4013 Val = SVOp->getMaskElt(i);
4017 assert(Val - i > 0 && "PALIGNR imm should be positive");
4018 return (Val - i) * EltSize;
4021 /// getExtractVEXTRACTF128Immediate - Return the appropriate immediate
4022 /// to extract the specified EXTRACT_SUBVECTOR index with VEXTRACTF128
4024 unsigned X86::getExtractVEXTRACTF128Immediate(SDNode *N) {
4025 if (!isa<ConstantSDNode>(N->getOperand(1).getNode()))
4026 llvm_unreachable("Illegal extract subvector for VEXTRACTF128");
4029 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
4031 EVT VecVT = N->getOperand(0).getValueType();
4032 EVT ElVT = VecVT.getVectorElementType();
4034 unsigned NumElemsPerChunk = 128 / ElVT.getSizeInBits();
4035 return Index / NumElemsPerChunk;
4038 /// getInsertVINSERTF128Immediate - Return the appropriate immediate
4039 /// to insert at the specified INSERT_SUBVECTOR index with VINSERTF128
4041 unsigned X86::getInsertVINSERTF128Immediate(SDNode *N) {
4042 if (!isa<ConstantSDNode>(N->getOperand(2).getNode()))
4043 llvm_unreachable("Illegal insert subvector for VINSERTF128");
4046 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
4048 EVT VecVT = N->getValueType(0);
4049 EVT ElVT = VecVT.getVectorElementType();
4051 unsigned NumElemsPerChunk = 128 / ElVT.getSizeInBits();
4052 return Index / NumElemsPerChunk;
4055 /// isZeroNode - Returns true if Elt is a constant zero or a floating point
4057 bool X86::isZeroNode(SDValue Elt) {
4058 return ((isa<ConstantSDNode>(Elt) &&
4059 cast<ConstantSDNode>(Elt)->isNullValue()) ||
4060 (isa<ConstantFPSDNode>(Elt) &&
4061 cast<ConstantFPSDNode>(Elt)->getValueAPF().isPosZero()));
4064 /// CommuteVectorShuffle - Swap vector_shuffle operands as well as values in
4065 /// their permute mask.
4066 static SDValue CommuteVectorShuffle(ShuffleVectorSDNode *SVOp,
4067 SelectionDAG &DAG) {
4068 EVT VT = SVOp->getValueType(0);
4069 unsigned NumElems = VT.getVectorNumElements();
4070 SmallVector<int, 8> MaskVec;
4072 for (unsigned i = 0; i != NumElems; ++i) {
4073 int idx = SVOp->getMaskElt(i);
4075 MaskVec.push_back(idx);
4076 else if (idx < (int)NumElems)
4077 MaskVec.push_back(idx + NumElems);
4079 MaskVec.push_back(idx - NumElems);
4081 return DAG.getVectorShuffle(VT, SVOp->getDebugLoc(), SVOp->getOperand(1),
4082 SVOp->getOperand(0), &MaskVec[0]);
4085 /// ShouldXformToMOVHLPS - Return true if the node should be transformed to
4086 /// match movhlps. The lower half elements should come from upper half of
4087 /// V1 (and in order), and the upper half elements should come from the upper
4088 /// half of V2 (and in order).
4089 static bool ShouldXformToMOVHLPS(ShuffleVectorSDNode *Op) {
4090 EVT VT = Op->getValueType(0);
4091 if (VT.getSizeInBits() != 128)
4093 if (VT.getVectorNumElements() != 4)
4095 for (unsigned i = 0, e = 2; i != e; ++i)
4096 if (!isUndefOrEqual(Op->getMaskElt(i), i+2))
4098 for (unsigned i = 2; i != 4; ++i)
4099 if (!isUndefOrEqual(Op->getMaskElt(i), i+4))
4104 /// isScalarLoadToVector - Returns true if the node is a scalar load that
4105 /// is promoted to a vector. It also returns the LoadSDNode by reference if
4107 static bool isScalarLoadToVector(SDNode *N, LoadSDNode **LD = NULL) {
4108 if (N->getOpcode() != ISD::SCALAR_TO_VECTOR)
4110 N = N->getOperand(0).getNode();
4111 if (!ISD::isNON_EXTLoad(N))
4114 *LD = cast<LoadSDNode>(N);
4118 // Test whether the given value is a vector value which will be legalized
4120 static bool WillBeConstantPoolLoad(SDNode *N) {
4121 if (N->getOpcode() != ISD::BUILD_VECTOR)
4124 // Check for any non-constant elements.
4125 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
4126 switch (N->getOperand(i).getNode()->getOpcode()) {
4128 case ISD::ConstantFP:
4135 // Vectors of all-zeros and all-ones are materialized with special
4136 // instructions rather than being loaded.
4137 return !ISD::isBuildVectorAllZeros(N) &&
4138 !ISD::isBuildVectorAllOnes(N);
4141 /// ShouldXformToMOVLP{S|D} - Return true if the node should be transformed to
4142 /// match movlp{s|d}. The lower half elements should come from lower half of
4143 /// V1 (and in order), and the upper half elements should come from the upper
4144 /// half of V2 (and in order). And since V1 will become the source of the
4145 /// MOVLP, it must be either a vector load or a scalar load to vector.
4146 static bool ShouldXformToMOVLP(SDNode *V1, SDNode *V2,
4147 ShuffleVectorSDNode *Op) {
4148 EVT VT = Op->getValueType(0);
4149 if (VT.getSizeInBits() != 128)
4152 if (!ISD::isNON_EXTLoad(V1) && !isScalarLoadToVector(V1))
4154 // Is V2 is a vector load, don't do this transformation. We will try to use
4155 // load folding shufps op.
4156 if (ISD::isNON_EXTLoad(V2) || WillBeConstantPoolLoad(V2))
4159 unsigned NumElems = VT.getVectorNumElements();
4161 if (NumElems != 2 && NumElems != 4)
4163 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
4164 if (!isUndefOrEqual(Op->getMaskElt(i), i))
4166 for (unsigned i = NumElems/2; i != NumElems; ++i)
4167 if (!isUndefOrEqual(Op->getMaskElt(i), i+NumElems))
4172 /// isSplatVector - Returns true if N is a BUILD_VECTOR node whose elements are
4174 static bool isSplatVector(SDNode *N) {
4175 if (N->getOpcode() != ISD::BUILD_VECTOR)
4178 SDValue SplatValue = N->getOperand(0);
4179 for (unsigned i = 1, e = N->getNumOperands(); i != e; ++i)
4180 if (N->getOperand(i) != SplatValue)
4185 /// isZeroShuffle - Returns true if N is a VECTOR_SHUFFLE that can be resolved
4186 /// to an zero vector.
4187 /// FIXME: move to dag combiner / method on ShuffleVectorSDNode
4188 static bool isZeroShuffle(ShuffleVectorSDNode *N) {
4189 SDValue V1 = N->getOperand(0);
4190 SDValue V2 = N->getOperand(1);
4191 unsigned NumElems = N->getValueType(0).getVectorNumElements();
4192 for (unsigned i = 0; i != NumElems; ++i) {
4193 int Idx = N->getMaskElt(i);
4194 if (Idx >= (int)NumElems) {
4195 unsigned Opc = V2.getOpcode();
4196 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V2.getNode()))
4198 if (Opc != ISD::BUILD_VECTOR ||
4199 !X86::isZeroNode(V2.getOperand(Idx-NumElems)))
4201 } else if (Idx >= 0) {
4202 unsigned Opc = V1.getOpcode();
4203 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V1.getNode()))
4205 if (Opc != ISD::BUILD_VECTOR ||
4206 !X86::isZeroNode(V1.getOperand(Idx)))
4213 /// getZeroVector - Returns a vector of specified type with all zero elements.
4215 static SDValue getZeroVector(EVT VT, bool HasSSE2, bool HasAVX2,
4216 SelectionDAG &DAG, DebugLoc dl) {
4217 assert(VT.isVector() && "Expected a vector type");
4219 // Always build SSE zero vectors as <4 x i32> bitcasted
4220 // to their dest type. This ensures they get CSE'd.
4222 if (VT.getSizeInBits() == 128) { // SSE
4223 if (HasSSE2) { // SSE2
4224 SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
4225 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4227 SDValue Cst = DAG.getTargetConstantFP(+0.0, MVT::f32);
4228 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4f32, Cst, Cst, Cst, Cst);
4230 } else if (VT.getSizeInBits() == 256) { // AVX
4231 if (HasAVX2) { // AVX2
4232 SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
4233 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4234 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops, 8);
4236 // 256-bit logic and arithmetic instructions in AVX are all
4237 // floating-point, no support for integer ops. Emit fp zeroed vectors.
4238 SDValue Cst = DAG.getTargetConstantFP(+0.0, MVT::f32);
4239 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4240 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8f32, Ops, 8);
4243 return DAG.getNode(ISD::BITCAST, dl, VT, Vec);
4246 /// getOnesVector - Returns a vector of specified type with all bits set.
4247 /// Always build ones vectors as <4 x i32> or <8 x i32>. For 256-bit types with
4248 /// no AVX2 supprt, use two <4 x i32> inserted in a <8 x i32> appropriately.
4249 /// Then bitcast to their original type, ensuring they get CSE'd.
4250 static SDValue getOnesVector(EVT VT, bool HasAVX2, SelectionDAG &DAG,
4252 assert(VT.isVector() && "Expected a vector type");
4253 assert((VT.is128BitVector() || VT.is256BitVector())
4254 && "Expected a 128-bit or 256-bit vector type");
4256 SDValue Cst = DAG.getTargetConstant(~0U, MVT::i32);
4258 if (VT.getSizeInBits() == 256) {
4259 if (HasAVX2) { // AVX2
4260 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4261 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops, 8);
4263 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4264 SDValue InsV = Insert128BitVector(DAG.getNode(ISD::UNDEF, dl, MVT::v8i32),
4265 Vec, DAG.getConstant(0, MVT::i32), DAG, dl);
4266 Vec = Insert128BitVector(InsV, Vec,
4267 DAG.getConstant(4 /* NumElems/2 */, MVT::i32), DAG, dl);
4270 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4273 return DAG.getNode(ISD::BITCAST, dl, VT, Vec);
4276 /// NormalizeMask - V2 is a splat, modify the mask (if needed) so all elements
4277 /// that point to V2 points to its first element.
4278 static SDValue NormalizeMask(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
4279 EVT VT = SVOp->getValueType(0);
4280 unsigned NumElems = VT.getVectorNumElements();
4282 bool Changed = false;
4283 SmallVector<int, 8> MaskVec(SVOp->getMask().begin(), SVOp->getMask().end());
4285 for (unsigned i = 0; i != NumElems; ++i) {
4286 if (MaskVec[i] > (int)NumElems) {
4287 MaskVec[i] = NumElems;
4292 return DAG.getVectorShuffle(VT, SVOp->getDebugLoc(), SVOp->getOperand(0),
4293 SVOp->getOperand(1), &MaskVec[0]);
4294 return SDValue(SVOp, 0);
4297 /// getMOVLMask - Returns a vector_shuffle mask for an movs{s|d}, movd
4298 /// operation of specified width.
4299 static SDValue getMOVL(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1,
4301 unsigned NumElems = VT.getVectorNumElements();
4302 SmallVector<int, 8> Mask;
4303 Mask.push_back(NumElems);
4304 for (unsigned i = 1; i != NumElems; ++i)
4306 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
4309 /// getUnpackl - Returns a vector_shuffle node for an unpackl operation.
4310 static SDValue getUnpackl(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1,
4312 unsigned NumElems = VT.getVectorNumElements();
4313 SmallVector<int, 8> Mask;
4314 for (unsigned i = 0, e = NumElems/2; i != e; ++i) {
4316 Mask.push_back(i + NumElems);
4318 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
4321 /// getUnpackh - Returns a vector_shuffle node for an unpackh operation.
4322 static SDValue getUnpackh(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1,
4324 unsigned NumElems = VT.getVectorNumElements();
4325 unsigned Half = NumElems/2;
4326 SmallVector<int, 8> Mask;
4327 for (unsigned i = 0; i != Half; ++i) {
4328 Mask.push_back(i + Half);
4329 Mask.push_back(i + NumElems + Half);
4331 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
4334 // PromoteSplati8i16 - All i16 and i8 vector types can't be used directly by
4335 // a generic shuffle instruction because the target has no such instructions.
4336 // Generate shuffles which repeat i16 and i8 several times until they can be
4337 // represented by v4f32 and then be manipulated by target suported shuffles.
4338 static SDValue PromoteSplati8i16(SDValue V, SelectionDAG &DAG, int &EltNo) {
4339 EVT VT = V.getValueType();
4340 int NumElems = VT.getVectorNumElements();
4341 DebugLoc dl = V.getDebugLoc();
4343 while (NumElems > 4) {
4344 if (EltNo < NumElems/2) {
4345 V = getUnpackl(DAG, dl, VT, V, V);
4347 V = getUnpackh(DAG, dl, VT, V, V);
4348 EltNo -= NumElems/2;
4355 /// getLegalSplat - Generate a legal splat with supported x86 shuffles
4356 static SDValue getLegalSplat(SelectionDAG &DAG, SDValue V, int EltNo) {
4357 EVT VT = V.getValueType();
4358 DebugLoc dl = V.getDebugLoc();
4359 assert((VT.getSizeInBits() == 128 || VT.getSizeInBits() == 256)
4360 && "Vector size not supported");
4362 if (VT.getSizeInBits() == 128) {
4363 V = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V);
4364 int SplatMask[4] = { EltNo, EltNo, EltNo, EltNo };
4365 V = DAG.getVectorShuffle(MVT::v4f32, dl, V, DAG.getUNDEF(MVT::v4f32),
4368 // To use VPERMILPS to splat scalars, the second half of indicies must
4369 // refer to the higher part, which is a duplication of the lower one,
4370 // because VPERMILPS can only handle in-lane permutations.
4371 int SplatMask[8] = { EltNo, EltNo, EltNo, EltNo,
4372 EltNo+4, EltNo+4, EltNo+4, EltNo+4 };
4374 V = DAG.getNode(ISD::BITCAST, dl, MVT::v8f32, V);
4375 V = DAG.getVectorShuffle(MVT::v8f32, dl, V, DAG.getUNDEF(MVT::v8f32),
4379 return DAG.getNode(ISD::BITCAST, dl, VT, V);
4382 /// PromoteSplat - Splat is promoted to target supported vector shuffles.
4383 static SDValue PromoteSplat(ShuffleVectorSDNode *SV, SelectionDAG &DAG) {
4384 EVT SrcVT = SV->getValueType(0);
4385 SDValue V1 = SV->getOperand(0);
4386 DebugLoc dl = SV->getDebugLoc();
4388 int EltNo = SV->getSplatIndex();
4389 int NumElems = SrcVT.getVectorNumElements();
4390 unsigned Size = SrcVT.getSizeInBits();
4392 assert(((Size == 128 && NumElems > 4) || Size == 256) &&
4393 "Unknown how to promote splat for type");
4395 // Extract the 128-bit part containing the splat element and update
4396 // the splat element index when it refers to the higher register.
4398 unsigned Idx = (EltNo >= NumElems/2) ? NumElems/2 : 0;
4399 V1 = Extract128BitVector(V1, DAG.getConstant(Idx, MVT::i32), DAG, dl);
4401 EltNo -= NumElems/2;
4404 // All i16 and i8 vector types can't be used directly by a generic shuffle
4405 // instruction because the target has no such instruction. Generate shuffles
4406 // which repeat i16 and i8 several times until they fit in i32, and then can
4407 // be manipulated by target suported shuffles.
4408 EVT EltVT = SrcVT.getVectorElementType();
4409 if (EltVT == MVT::i8 || EltVT == MVT::i16)
4410 V1 = PromoteSplati8i16(V1, DAG, EltNo);
4412 // Recreate the 256-bit vector and place the same 128-bit vector
4413 // into the low and high part. This is necessary because we want
4414 // to use VPERM* to shuffle the vectors
4416 SDValue InsV = Insert128BitVector(DAG.getUNDEF(SrcVT), V1,
4417 DAG.getConstant(0, MVT::i32), DAG, dl);
4418 V1 = Insert128BitVector(InsV, V1,
4419 DAG.getConstant(NumElems/2, MVT::i32), DAG, dl);
4422 return getLegalSplat(DAG, V1, EltNo);
4425 /// getShuffleVectorZeroOrUndef - Return a vector_shuffle of the specified
4426 /// vector of zero or undef vector. This produces a shuffle where the low
4427 /// element of V2 is swizzled into the zero/undef vector, landing at element
4428 /// Idx. This produces a shuffle mask like 4,1,2,3 (idx=0) or 0,1,2,4 (idx=3).
4429 static SDValue getShuffleVectorZeroOrUndef(SDValue V2, unsigned Idx,
4431 const X86Subtarget *Subtarget,
4432 SelectionDAG &DAG) {
4433 EVT VT = V2.getValueType();
4435 ? getZeroVector(VT, Subtarget->hasSSE2(), Subtarget->hasAVX2(), DAG,
4436 V2.getDebugLoc()) : DAG.getUNDEF(VT);
4437 unsigned NumElems = VT.getVectorNumElements();
4438 SmallVector<int, 16> MaskVec;
4439 for (unsigned i = 0; i != NumElems; ++i)
4440 // If this is the insertion idx, put the low elt of V2 here.
4441 MaskVec.push_back(i == Idx ? NumElems : i);
4442 return DAG.getVectorShuffle(VT, V2.getDebugLoc(), V1, V2, &MaskVec[0]);
4445 /// getShuffleScalarElt - Returns the scalar element that will make up the ith
4446 /// element of the result of the vector shuffle.
4447 static SDValue getShuffleScalarElt(SDNode *N, int Index, SelectionDAG &DAG,
4450 return SDValue(); // Limit search depth.
4452 SDValue V = SDValue(N, 0);
4453 EVT VT = V.getValueType();
4454 unsigned Opcode = V.getOpcode();
4456 // Recurse into ISD::VECTOR_SHUFFLE node to find scalars.
4457 if (const ShuffleVectorSDNode *SV = dyn_cast<ShuffleVectorSDNode>(N)) {
4458 Index = SV->getMaskElt(Index);
4461 return DAG.getUNDEF(VT.getVectorElementType());
4463 int NumElems = VT.getVectorNumElements();
4464 SDValue NewV = (Index < NumElems) ? SV->getOperand(0) : SV->getOperand(1);
4465 return getShuffleScalarElt(NewV.getNode(), Index % NumElems, DAG, Depth+1);
4468 // Recurse into target specific vector shuffles to find scalars.
4469 if (isTargetShuffle(Opcode)) {
4470 int NumElems = VT.getVectorNumElements();
4471 SmallVector<unsigned, 16> ShuffleMask;
4476 ImmN = N->getOperand(N->getNumOperands()-1);
4477 DecodeSHUFPMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(),
4480 case X86ISD::UNPCKH:
4481 DecodeUNPCKHMask(VT, ShuffleMask);
4483 case X86ISD::UNPCKL:
4484 DecodeUNPCKLMask(VT, ShuffleMask);
4486 case X86ISD::MOVHLPS:
4487 DecodeMOVHLPSMask(NumElems, ShuffleMask);
4489 case X86ISD::MOVLHPS:
4490 DecodeMOVLHPSMask(NumElems, ShuffleMask);
4492 case X86ISD::PSHUFD:
4493 ImmN = N->getOperand(N->getNumOperands()-1);
4494 DecodePSHUFMask(NumElems,
4495 cast<ConstantSDNode>(ImmN)->getZExtValue(),
4498 case X86ISD::PSHUFHW:
4499 ImmN = N->getOperand(N->getNumOperands()-1);
4500 DecodePSHUFHWMask(cast<ConstantSDNode>(ImmN)->getZExtValue(),
4503 case X86ISD::PSHUFLW:
4504 ImmN = N->getOperand(N->getNumOperands()-1);
4505 DecodePSHUFLWMask(cast<ConstantSDNode>(ImmN)->getZExtValue(),
4509 case X86ISD::MOVSD: {
4510 // The index 0 always comes from the first element of the second source,
4511 // this is why MOVSS and MOVSD are used in the first place. The other
4512 // elements come from the other positions of the first source vector.
4513 unsigned OpNum = (Index == 0) ? 1 : 0;
4514 return getShuffleScalarElt(V.getOperand(OpNum).getNode(), Index, DAG,
4517 case X86ISD::VPERMILP:
4518 ImmN = N->getOperand(N->getNumOperands()-1);
4519 DecodeVPERMILPMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(),
4522 case X86ISD::VPERM2X128:
4523 ImmN = N->getOperand(N->getNumOperands()-1);
4524 DecodeVPERM2F128Mask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(),
4527 case X86ISD::MOVDDUP:
4528 case X86ISD::MOVLHPD:
4529 case X86ISD::MOVLPD:
4530 case X86ISD::MOVLPS:
4531 case X86ISD::MOVSHDUP:
4532 case X86ISD::MOVSLDUP:
4533 case X86ISD::PALIGN:
4534 return SDValue(); // Not yet implemented.
4536 assert(0 && "unknown target shuffle node");
4540 Index = ShuffleMask[Index];
4542 return DAG.getUNDEF(VT.getVectorElementType());
4544 SDValue NewV = (Index < NumElems) ? N->getOperand(0) : N->getOperand(1);
4545 return getShuffleScalarElt(NewV.getNode(), Index % NumElems, DAG,
4549 // Actual nodes that may contain scalar elements
4550 if (Opcode == ISD::BITCAST) {
4551 V = V.getOperand(0);
4552 EVT SrcVT = V.getValueType();
4553 unsigned NumElems = VT.getVectorNumElements();
4555 if (!SrcVT.isVector() || SrcVT.getVectorNumElements() != NumElems)
4559 if (V.getOpcode() == ISD::SCALAR_TO_VECTOR)
4560 return (Index == 0) ? V.getOperand(0)
4561 : DAG.getUNDEF(VT.getVectorElementType());
4563 if (V.getOpcode() == ISD::BUILD_VECTOR)
4564 return V.getOperand(Index);
4569 /// getNumOfConsecutiveZeros - Return the number of elements of a vector
4570 /// shuffle operation which come from a consecutively from a zero. The
4571 /// search can start in two different directions, from left or right.
4573 unsigned getNumOfConsecutiveZeros(SDNode *N, int NumElems,
4574 bool ZerosFromLeft, SelectionDAG &DAG) {
4577 while (i < NumElems) {
4578 unsigned Index = ZerosFromLeft ? i : NumElems-i-1;
4579 SDValue Elt = getShuffleScalarElt(N, Index, DAG, 0);
4580 if (!(Elt.getNode() &&
4581 (Elt.getOpcode() == ISD::UNDEF || X86::isZeroNode(Elt))))
4589 /// isShuffleMaskConsecutive - Check if the shuffle mask indicies from MaskI to
4590 /// MaskE correspond consecutively to elements from one of the vector operands,
4591 /// starting from its index OpIdx. Also tell OpNum which source vector operand.
4593 bool isShuffleMaskConsecutive(ShuffleVectorSDNode *SVOp, int MaskI, int MaskE,
4594 int OpIdx, int NumElems, unsigned &OpNum) {
4595 bool SeenV1 = false;
4596 bool SeenV2 = false;
4598 for (int i = MaskI; i <= MaskE; ++i, ++OpIdx) {
4599 int Idx = SVOp->getMaskElt(i);
4600 // Ignore undef indicies
4609 // Only accept consecutive elements from the same vector
4610 if ((Idx % NumElems != OpIdx) || (SeenV1 && SeenV2))
4614 OpNum = SeenV1 ? 0 : 1;
4618 /// isVectorShiftRight - Returns true if the shuffle can be implemented as a
4619 /// logical left shift of a vector.
4620 static bool isVectorShiftRight(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
4621 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
4622 unsigned NumElems = SVOp->getValueType(0).getVectorNumElements();
4623 unsigned NumZeros = getNumOfConsecutiveZeros(SVOp, NumElems,
4624 false /* check zeros from right */, DAG);
4630 // Considering the elements in the mask that are not consecutive zeros,
4631 // check if they consecutively come from only one of the source vectors.
4633 // V1 = {X, A, B, C} 0
4635 // vector_shuffle V1, V2 <1, 2, 3, X>
4637 if (!isShuffleMaskConsecutive(SVOp,
4638 0, // Mask Start Index
4639 NumElems-NumZeros-1, // Mask End Index
4640 NumZeros, // Where to start looking in the src vector
4641 NumElems, // Number of elements in vector
4642 OpSrc)) // Which source operand ?
4647 ShVal = SVOp->getOperand(OpSrc);
4651 /// isVectorShiftLeft - Returns true if the shuffle can be implemented as a
4652 /// logical left shift of a vector.
4653 static bool isVectorShiftLeft(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
4654 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
4655 unsigned NumElems = SVOp->getValueType(0).getVectorNumElements();
4656 unsigned NumZeros = getNumOfConsecutiveZeros(SVOp, NumElems,
4657 true /* check zeros from left */, DAG);
4663 // Considering the elements in the mask that are not consecutive zeros,
4664 // check if they consecutively come from only one of the source vectors.
4666 // 0 { A, B, X, X } = V2
4668 // vector_shuffle V1, V2 <X, X, 4, 5>
4670 if (!isShuffleMaskConsecutive(SVOp,
4671 NumZeros, // Mask Start Index
4672 NumElems-1, // Mask End Index
4673 0, // Where to start looking in the src vector
4674 NumElems, // Number of elements in vector
4675 OpSrc)) // Which source operand ?
4680 ShVal = SVOp->getOperand(OpSrc);
4684 /// isVectorShift - Returns true if the shuffle can be implemented as a
4685 /// logical left or right shift of a vector.
4686 static bool isVectorShift(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
4687 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
4688 // Although the logic below support any bitwidth size, there are no
4689 // shift instructions which handle more than 128-bit vectors.
4690 if (SVOp->getValueType(0).getSizeInBits() > 128)
4693 if (isVectorShiftLeft(SVOp, DAG, isLeft, ShVal, ShAmt) ||
4694 isVectorShiftRight(SVOp, DAG, isLeft, ShVal, ShAmt))
4700 /// LowerBuildVectorv16i8 - Custom lower build_vector of v16i8.
4702 static SDValue LowerBuildVectorv16i8(SDValue Op, unsigned NonZeros,
4703 unsigned NumNonZero, unsigned NumZero,
4705 const TargetLowering &TLI) {
4709 DebugLoc dl = Op.getDebugLoc();
4712 for (unsigned i = 0; i < 16; ++i) {
4713 bool ThisIsNonZero = (NonZeros & (1 << i)) != 0;
4714 if (ThisIsNonZero && First) {
4716 V = getZeroVector(MVT::v8i16, /*HasSSE2*/ true, /*HasAVX2*/ false,
4719 V = DAG.getUNDEF(MVT::v8i16);
4724 SDValue ThisElt(0, 0), LastElt(0, 0);
4725 bool LastIsNonZero = (NonZeros & (1 << (i-1))) != 0;
4726 if (LastIsNonZero) {
4727 LastElt = DAG.getNode(ISD::ZERO_EXTEND, dl,
4728 MVT::i16, Op.getOperand(i-1));
4730 if (ThisIsNonZero) {
4731 ThisElt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, Op.getOperand(i));
4732 ThisElt = DAG.getNode(ISD::SHL, dl, MVT::i16,
4733 ThisElt, DAG.getConstant(8, MVT::i8));
4735 ThisElt = DAG.getNode(ISD::OR, dl, MVT::i16, ThisElt, LastElt);
4739 if (ThisElt.getNode())
4740 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, V, ThisElt,
4741 DAG.getIntPtrConstant(i/2));
4745 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V);
4748 /// LowerBuildVectorv8i16 - Custom lower build_vector of v8i16.
4750 static SDValue LowerBuildVectorv8i16(SDValue Op, unsigned NonZeros,
4751 unsigned NumNonZero, unsigned NumZero,
4753 const TargetLowering &TLI) {
4757 DebugLoc dl = Op.getDebugLoc();
4760 for (unsigned i = 0; i < 8; ++i) {
4761 bool isNonZero = (NonZeros & (1 << i)) != 0;
4765 V = getZeroVector(MVT::v8i16, /*HasSSE2*/ true, /*HasAVX2*/ false,
4768 V = DAG.getUNDEF(MVT::v8i16);
4771 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl,
4772 MVT::v8i16, V, Op.getOperand(i),
4773 DAG.getIntPtrConstant(i));
4780 /// getVShift - Return a vector logical shift node.
4782 static SDValue getVShift(bool isLeft, EVT VT, SDValue SrcOp,
4783 unsigned NumBits, SelectionDAG &DAG,
4784 const TargetLowering &TLI, DebugLoc dl) {
4785 assert(VT.getSizeInBits() == 128 && "Unknown type for VShift");
4786 EVT ShVT = MVT::v2i64;
4787 unsigned Opc = isLeft ? X86ISD::VSHL : X86ISD::VSRL;
4788 SrcOp = DAG.getNode(ISD::BITCAST, dl, ShVT, SrcOp);
4789 return DAG.getNode(ISD::BITCAST, dl, VT,
4790 DAG.getNode(Opc, dl, ShVT, SrcOp,
4791 DAG.getConstant(NumBits,
4792 TLI.getShiftAmountTy(SrcOp.getValueType()))));
4796 X86TargetLowering::LowerAsSplatVectorLoad(SDValue SrcOp, EVT VT, DebugLoc dl,
4797 SelectionDAG &DAG) const {
4799 // Check if the scalar load can be widened into a vector load. And if
4800 // the address is "base + cst" see if the cst can be "absorbed" into
4801 // the shuffle mask.
4802 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(SrcOp)) {
4803 SDValue Ptr = LD->getBasePtr();
4804 if (!ISD::isNormalLoad(LD) || LD->isVolatile())
4806 EVT PVT = LD->getValueType(0);
4807 if (PVT != MVT::i32 && PVT != MVT::f32)
4812 if (FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr)) {
4813 FI = FINode->getIndex();
4815 } else if (DAG.isBaseWithConstantOffset(Ptr) &&
4816 isa<FrameIndexSDNode>(Ptr.getOperand(0))) {
4817 FI = cast<FrameIndexSDNode>(Ptr.getOperand(0))->getIndex();
4818 Offset = Ptr.getConstantOperandVal(1);
4819 Ptr = Ptr.getOperand(0);
4824 // FIXME: 256-bit vector instructions don't require a strict alignment,
4825 // improve this code to support it better.
4826 unsigned RequiredAlign = VT.getSizeInBits()/8;
4827 SDValue Chain = LD->getChain();
4828 // Make sure the stack object alignment is at least 16 or 32.
4829 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
4830 if (DAG.InferPtrAlignment(Ptr) < RequiredAlign) {
4831 if (MFI->isFixedObjectIndex(FI)) {
4832 // Can't change the alignment. FIXME: It's possible to compute
4833 // the exact stack offset and reference FI + adjust offset instead.
4834 // If someone *really* cares about this. That's the way to implement it.
4837 MFI->setObjectAlignment(FI, RequiredAlign);
4841 // (Offset % 16 or 32) must be multiple of 4. Then address is then
4842 // Ptr + (Offset & ~15).
4845 if ((Offset % RequiredAlign) & 3)
4847 int64_t StartOffset = Offset & ~(RequiredAlign-1);
4849 Ptr = DAG.getNode(ISD::ADD, Ptr.getDebugLoc(), Ptr.getValueType(),
4850 Ptr,DAG.getConstant(StartOffset, Ptr.getValueType()));
4852 int EltNo = (Offset - StartOffset) >> 2;
4853 int NumElems = VT.getVectorNumElements();
4855 EVT CanonVT = VT.getSizeInBits() == 128 ? MVT::v4i32 : MVT::v8i32;
4856 EVT NVT = EVT::getVectorVT(*DAG.getContext(), PVT, NumElems);
4857 SDValue V1 = DAG.getLoad(NVT, dl, Chain, Ptr,
4858 LD->getPointerInfo().getWithOffset(StartOffset),
4859 false, false, false, 0);
4861 // Canonicalize it to a v4i32 or v8i32 shuffle.
4862 SmallVector<int, 8> Mask;
4863 for (int i = 0; i < NumElems; ++i)
4864 Mask.push_back(EltNo);
4866 V1 = DAG.getNode(ISD::BITCAST, dl, CanonVT, V1);
4867 return DAG.getNode(ISD::BITCAST, dl, NVT,
4868 DAG.getVectorShuffle(CanonVT, dl, V1,
4869 DAG.getUNDEF(CanonVT),&Mask[0]));
4875 /// EltsFromConsecutiveLoads - Given the initializing elements 'Elts' of a
4876 /// vector of type 'VT', see if the elements can be replaced by a single large
4877 /// load which has the same value as a build_vector whose operands are 'elts'.
4879 /// Example: <load i32 *a, load i32 *a+4, undef, undef> -> zextload a
4881 /// FIXME: we'd also like to handle the case where the last elements are zero
4882 /// rather than undef via VZEXT_LOAD, but we do not detect that case today.
4883 /// There's even a handy isZeroNode for that purpose.
4884 static SDValue EltsFromConsecutiveLoads(EVT VT, SmallVectorImpl<SDValue> &Elts,
4885 DebugLoc &DL, SelectionDAG &DAG) {
4886 EVT EltVT = VT.getVectorElementType();
4887 unsigned NumElems = Elts.size();
4889 LoadSDNode *LDBase = NULL;
4890 unsigned LastLoadedElt = -1U;
4892 // For each element in the initializer, see if we've found a load or an undef.
4893 // If we don't find an initial load element, or later load elements are
4894 // non-consecutive, bail out.
4895 for (unsigned i = 0; i < NumElems; ++i) {
4896 SDValue Elt = Elts[i];
4898 if (!Elt.getNode() ||
4899 (Elt.getOpcode() != ISD::UNDEF && !ISD::isNON_EXTLoad(Elt.getNode())))
4902 if (Elt.getNode()->getOpcode() == ISD::UNDEF)
4904 LDBase = cast<LoadSDNode>(Elt.getNode());
4908 if (Elt.getOpcode() == ISD::UNDEF)
4911 LoadSDNode *LD = cast<LoadSDNode>(Elt);
4912 if (!DAG.isConsecutiveLoad(LD, LDBase, EltVT.getSizeInBits()/8, i))
4917 // If we have found an entire vector of loads and undefs, then return a large
4918 // load of the entire vector width starting at the base pointer. If we found
4919 // consecutive loads for the low half, generate a vzext_load node.
4920 if (LastLoadedElt == NumElems - 1) {
4921 if (DAG.InferPtrAlignment(LDBase->getBasePtr()) >= 16)
4922 return DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(),
4923 LDBase->getPointerInfo(),
4924 LDBase->isVolatile(), LDBase->isNonTemporal(),
4925 LDBase->isInvariant(), 0);
4926 return DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(),
4927 LDBase->getPointerInfo(),
4928 LDBase->isVolatile(), LDBase->isNonTemporal(),
4929 LDBase->isInvariant(), LDBase->getAlignment());
4930 } else if (NumElems == 4 && LastLoadedElt == 1 &&
4931 DAG.getTargetLoweringInfo().isTypeLegal(MVT::v2i64)) {
4932 SDVTList Tys = DAG.getVTList(MVT::v2i64, MVT::Other);
4933 SDValue Ops[] = { LDBase->getChain(), LDBase->getBasePtr() };
4935 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, DL, Tys, Ops, 2, MVT::i64,
4936 LDBase->getPointerInfo(),
4937 LDBase->getAlignment(),
4938 false/*isVolatile*/, true/*ReadMem*/,
4940 return DAG.getNode(ISD::BITCAST, DL, VT, ResNode);
4945 /// isVectorBroadcast - Check if the node chain is suitable to be xformed to
4946 /// a vbroadcast node. We support two patterns:
4947 /// 1. A splat BUILD_VECTOR which uses a single scalar load.
4948 /// 2. A splat shuffle which uses a scalar_to_vector node which comes from
4950 /// The scalar load node is returned when a pattern is found,
4951 /// or SDValue() otherwise.
4952 static SDValue isVectorBroadcast(SDValue &Op, const X86Subtarget *Subtarget) {
4953 if (!Subtarget->hasAVX())
4956 EVT VT = Op.getValueType();
4959 if (V.hasOneUse() && V.getOpcode() == ISD::BITCAST)
4960 V = V.getOperand(0);
4962 //A suspected load to be broadcasted.
4965 switch (V.getOpcode()) {
4967 // Unknown pattern found.
4970 case ISD::BUILD_VECTOR: {
4971 // The BUILD_VECTOR node must be a splat.
4972 if (!isSplatVector(V.getNode()))
4975 Ld = V.getOperand(0);
4977 // The suspected load node has several users. Make sure that all
4978 // of its users are from the BUILD_VECTOR node.
4979 if (!Ld->hasNUsesOfValue(VT.getVectorNumElements(), 0))
4984 case ISD::VECTOR_SHUFFLE: {
4985 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
4987 // Shuffles must have a splat mask where the first element is
4989 if ((!SVOp->isSplat()) || SVOp->getMaskElt(0) != 0)
4992 SDValue Sc = Op.getOperand(0);
4993 if (Sc.getOpcode() != ISD::SCALAR_TO_VECTOR)
4996 Ld = Sc.getOperand(0);
4998 // The scalar_to_vector node and the suspected
4999 // load node must have exactly one user.
5000 if (!Sc.hasOneUse() || !Ld.hasOneUse())
5006 // The scalar source must be a normal load.
5007 if (!ISD::isNormalLoad(Ld.getNode()))
5010 bool Is256 = VT.getSizeInBits() == 256;
5011 bool Is128 = VT.getSizeInBits() == 128;
5012 unsigned ScalarSize = Ld.getValueType().getSizeInBits();
5014 // VBroadcast to YMM
5015 if (Is256 && (ScalarSize == 32 || ScalarSize == 64))
5018 // VBroadcast to XMM
5019 if (Is128 && (ScalarSize == 32))
5022 // The integer check is needed for the 64-bit into 128-bit so it doesn't match
5023 // double since there is vbroadcastsd xmm
5024 if (Subtarget->hasAVX2() && Ld.getValueType().isInteger()) {
5025 // VBroadcast to YMM
5026 if (Is256 && (ScalarSize == 8 || ScalarSize == 16))
5029 // VBroadcast to XMM
5030 if (Is128 && (ScalarSize == 8 || ScalarSize == 16 || ScalarSize == 64))
5034 // Unsupported broadcast.
5039 X86TargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const {
5040 DebugLoc dl = Op.getDebugLoc();
5042 EVT VT = Op.getValueType();
5043 EVT ExtVT = VT.getVectorElementType();
5044 unsigned NumElems = Op.getNumOperands();
5046 // Vectors containing all zeros can be matched by pxor and xorps later
5047 if (ISD::isBuildVectorAllZeros(Op.getNode())) {
5048 // Canonicalize this to <4 x i32> to 1) ensure the zero vectors are CSE'd
5049 // and 2) ensure that i64 scalars are eliminated on x86-32 hosts.
5050 if (Op.getValueType() == MVT::v4i32 ||
5051 Op.getValueType() == MVT::v8i32)
5054 return getZeroVector(Op.getValueType(), Subtarget->hasSSE2(),
5055 Subtarget->hasAVX2(), DAG, dl);
5058 // Vectors containing all ones can be matched by pcmpeqd on 128-bit width
5059 // vectors or broken into v4i32 operations on 256-bit vectors. AVX2 can use
5060 // vpcmpeqd on 256-bit vectors.
5061 if (ISD::isBuildVectorAllOnes(Op.getNode())) {
5062 if (Op.getValueType() == MVT::v4i32 ||
5063 (Op.getValueType() == MVT::v8i32 && Subtarget->hasAVX2()))
5066 return getOnesVector(Op.getValueType(), Subtarget->hasAVX2(), DAG, dl);
5069 SDValue LD = isVectorBroadcast(Op, Subtarget);
5071 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, LD);
5073 unsigned EVTBits = ExtVT.getSizeInBits();
5075 unsigned NumZero = 0;
5076 unsigned NumNonZero = 0;
5077 unsigned NonZeros = 0;
5078 bool IsAllConstants = true;
5079 SmallSet<SDValue, 8> Values;
5080 for (unsigned i = 0; i < NumElems; ++i) {
5081 SDValue Elt = Op.getOperand(i);
5082 if (Elt.getOpcode() == ISD::UNDEF)
5085 if (Elt.getOpcode() != ISD::Constant &&
5086 Elt.getOpcode() != ISD::ConstantFP)
5087 IsAllConstants = false;
5088 if (X86::isZeroNode(Elt))
5091 NonZeros |= (1 << i);
5096 // All undef vector. Return an UNDEF. All zero vectors were handled above.
5097 if (NumNonZero == 0)
5098 return DAG.getUNDEF(VT);
5100 // Special case for single non-zero, non-undef, element.
5101 if (NumNonZero == 1) {
5102 unsigned Idx = CountTrailingZeros_32(NonZeros);
5103 SDValue Item = Op.getOperand(Idx);
5105 // If this is an insertion of an i64 value on x86-32, and if the top bits of
5106 // the value are obviously zero, truncate the value to i32 and do the
5107 // insertion that way. Only do this if the value is non-constant or if the
5108 // value is a constant being inserted into element 0. It is cheaper to do
5109 // a constant pool load than it is to do a movd + shuffle.
5110 if (ExtVT == MVT::i64 && !Subtarget->is64Bit() &&
5111 (!IsAllConstants || Idx == 0)) {
5112 if (DAG.MaskedValueIsZero(Item, APInt::getBitsSet(64, 32, 64))) {
5114 assert(VT == MVT::v2i64 && "Expected an SSE value type!");
5115 EVT VecVT = MVT::v4i32;
5116 unsigned VecElts = 4;
5118 // Truncate the value (which may itself be a constant) to i32, and
5119 // convert it to a vector with movd (S2V+shuffle to zero extend).
5120 Item = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Item);
5121 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Item);
5122 Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
5124 // Now we have our 32-bit value zero extended in the low element of
5125 // a vector. If Idx != 0, swizzle it into place.
5127 SmallVector<int, 4> Mask;
5128 Mask.push_back(Idx);
5129 for (unsigned i = 1; i != VecElts; ++i)
5131 Item = DAG.getVectorShuffle(VecVT, dl, Item,
5132 DAG.getUNDEF(Item.getValueType()),
5135 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Item);
5139 // If we have a constant or non-constant insertion into the low element of
5140 // a vector, we can do this with SCALAR_TO_VECTOR + shuffle of zero into
5141 // the rest of the elements. This will be matched as movd/movq/movss/movsd
5142 // depending on what the source datatype is.
5145 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
5147 if (ExtVT == MVT::i32 || ExtVT == MVT::f32 || ExtVT == MVT::f64 ||
5148 (ExtVT == MVT::i64 && Subtarget->is64Bit())) {
5149 if (VT.getSizeInBits() == 256) {
5150 SDValue ZeroVec = getZeroVector(VT, Subtarget->hasSSE2(),
5151 Subtarget->hasAVX2(), DAG, dl);
5152 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, ZeroVec,
5153 Item, DAG.getIntPtrConstant(0));
5155 assert(VT.getSizeInBits() == 128 && "Expected an SSE value type!");
5156 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
5157 // Turn it into a MOVL (i.e. movss, movsd, or movd) to a zero vector.
5158 return getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
5161 if (ExtVT == MVT::i16 || ExtVT == MVT::i8) {
5162 Item = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Item);
5163 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, Item);
5164 if (VT.getSizeInBits() == 256) {
5165 SDValue ZeroVec = getZeroVector(MVT::v8i32, Subtarget->hasSSE2(),
5166 Subtarget->hasAVX2(), DAG, dl);
5167 Item = Insert128BitVector(ZeroVec, Item, DAG.getConstant(0, MVT::i32),
5170 assert(VT.getSizeInBits() == 128 && "Expected an SSE value type!");
5171 Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
5173 return DAG.getNode(ISD::BITCAST, dl, VT, Item);
5177 // Is it a vector logical left shift?
5178 if (NumElems == 2 && Idx == 1 &&
5179 X86::isZeroNode(Op.getOperand(0)) &&
5180 !X86::isZeroNode(Op.getOperand(1))) {
5181 unsigned NumBits = VT.getSizeInBits();
5182 return getVShift(true, VT,
5183 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
5184 VT, Op.getOperand(1)),
5185 NumBits/2, DAG, *this, dl);
5188 if (IsAllConstants) // Otherwise, it's better to do a constpool load.
5191 // Otherwise, if this is a vector with i32 or f32 elements, and the element
5192 // is a non-constant being inserted into an element other than the low one,
5193 // we can't use a constant pool load. Instead, use SCALAR_TO_VECTOR (aka
5194 // movd/movss) to move this into the low element, then shuffle it into
5196 if (EVTBits == 32) {
5197 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
5199 // Turn it into a shuffle of zero and zero-extended scalar to vector.
5200 Item = getShuffleVectorZeroOrUndef(Item, 0, NumZero > 0, Subtarget, DAG);
5201 SmallVector<int, 8> MaskVec;
5202 for (unsigned i = 0; i < NumElems; i++)
5203 MaskVec.push_back(i == Idx ? 0 : 1);
5204 return DAG.getVectorShuffle(VT, dl, Item, DAG.getUNDEF(VT), &MaskVec[0]);
5208 // Splat is obviously ok. Let legalizer expand it to a shuffle.
5209 if (Values.size() == 1) {
5210 if (EVTBits == 32) {
5211 // Instead of a shuffle like this:
5212 // shuffle (scalar_to_vector (load (ptr + 4))), undef, <0, 0, 0, 0>
5213 // Check if it's possible to issue this instead.
5214 // shuffle (vload ptr)), undef, <1, 1, 1, 1>
5215 unsigned Idx = CountTrailingZeros_32(NonZeros);
5216 SDValue Item = Op.getOperand(Idx);
5217 if (Op.getNode()->isOnlyUserOf(Item.getNode()))
5218 return LowerAsSplatVectorLoad(Item, VT, dl, DAG);
5223 // A vector full of immediates; various special cases are already
5224 // handled, so this is best done with a single constant-pool load.
5228 // For AVX-length vectors, build the individual 128-bit pieces and use
5229 // shuffles to put them in place.
5230 if (VT.getSizeInBits() == 256 && !ISD::isBuildVectorAllZeros(Op.getNode())) {
5231 SmallVector<SDValue, 32> V;
5232 for (unsigned i = 0; i < NumElems; ++i)
5233 V.push_back(Op.getOperand(i));
5235 EVT HVT = EVT::getVectorVT(*DAG.getContext(), ExtVT, NumElems/2);
5237 // Build both the lower and upper subvector.
5238 SDValue Lower = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT, &V[0], NumElems/2);
5239 SDValue Upper = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT, &V[NumElems / 2],
5242 // Recreate the wider vector with the lower and upper part.
5243 SDValue Vec = Insert128BitVector(DAG.getNode(ISD::UNDEF, dl, VT), Lower,
5244 DAG.getConstant(0, MVT::i32), DAG, dl);
5245 return Insert128BitVector(Vec, Upper, DAG.getConstant(NumElems/2, MVT::i32),
5249 // Let legalizer expand 2-wide build_vectors.
5250 if (EVTBits == 64) {
5251 if (NumNonZero == 1) {
5252 // One half is zero or undef.
5253 unsigned Idx = CountTrailingZeros_32(NonZeros);
5254 SDValue V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT,
5255 Op.getOperand(Idx));
5256 return getShuffleVectorZeroOrUndef(V2, Idx, true, Subtarget, DAG);
5261 // If element VT is < 32 bits, convert it to inserts into a zero vector.
5262 if (EVTBits == 8 && NumElems == 16) {
5263 SDValue V = LowerBuildVectorv16i8(Op, NonZeros,NumNonZero,NumZero, DAG,
5265 if (V.getNode()) return V;
5268 if (EVTBits == 16 && NumElems == 8) {
5269 SDValue V = LowerBuildVectorv8i16(Op, NonZeros,NumNonZero,NumZero, DAG,
5271 if (V.getNode()) return V;
5274 // If element VT is == 32 bits, turn it into a number of shuffles.
5275 SmallVector<SDValue, 8> V;
5277 if (NumElems == 4 && NumZero > 0) {
5278 for (unsigned i = 0; i < 4; ++i) {
5279 bool isZero = !(NonZeros & (1 << i));
5281 V[i] = getZeroVector(VT, Subtarget->hasSSE2(), Subtarget->hasAVX2(),
5284 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
5287 for (unsigned i = 0; i < 2; ++i) {
5288 switch ((NonZeros & (0x3 << i*2)) >> (i*2)) {
5291 V[i] = V[i*2]; // Must be a zero vector.
5294 V[i] = getMOVL(DAG, dl, VT, V[i*2+1], V[i*2]);
5297 V[i] = getMOVL(DAG, dl, VT, V[i*2], V[i*2+1]);
5300 V[i] = getUnpackl(DAG, dl, VT, V[i*2], V[i*2+1]);
5305 SmallVector<int, 8> MaskVec;
5306 bool Reverse = (NonZeros & 0x3) == 2;
5307 for (unsigned i = 0; i < 2; ++i)
5308 MaskVec.push_back(Reverse ? 1-i : i);
5309 Reverse = ((NonZeros & (0x3 << 2)) >> 2) == 2;
5310 for (unsigned i = 0; i < 2; ++i)
5311 MaskVec.push_back(Reverse ? 1-i+NumElems : i+NumElems);
5312 return DAG.getVectorShuffle(VT, dl, V[0], V[1], &MaskVec[0]);
5315 if (Values.size() > 1 && VT.getSizeInBits() == 128) {
5316 // Check for a build vector of consecutive loads.
5317 for (unsigned i = 0; i < NumElems; ++i)
5318 V[i] = Op.getOperand(i);
5320 // Check for elements which are consecutive loads.
5321 SDValue LD = EltsFromConsecutiveLoads(VT, V, dl, DAG);
5325 // For SSE 4.1, use insertps to put the high elements into the low element.
5326 if (getSubtarget()->hasSSE41()) {
5328 if (Op.getOperand(0).getOpcode() != ISD::UNDEF)
5329 Result = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(0));
5331 Result = DAG.getUNDEF(VT);
5333 for (unsigned i = 1; i < NumElems; ++i) {
5334 if (Op.getOperand(i).getOpcode() == ISD::UNDEF) continue;
5335 Result = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Result,
5336 Op.getOperand(i), DAG.getIntPtrConstant(i));
5341 // Otherwise, expand into a number of unpckl*, start by extending each of
5342 // our (non-undef) elements to the full vector width with the element in the
5343 // bottom slot of the vector (which generates no code for SSE).
5344 for (unsigned i = 0; i < NumElems; ++i) {
5345 if (Op.getOperand(i).getOpcode() != ISD::UNDEF)
5346 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
5348 V[i] = DAG.getUNDEF(VT);
5351 // Next, we iteratively mix elements, e.g. for v4f32:
5352 // Step 1: unpcklps 0, 2 ==> X: <?, ?, 2, 0>
5353 // : unpcklps 1, 3 ==> Y: <?, ?, 3, 1>
5354 // Step 2: unpcklps X, Y ==> <3, 2, 1, 0>
5355 unsigned EltStride = NumElems >> 1;
5356 while (EltStride != 0) {
5357 for (unsigned i = 0; i < EltStride; ++i) {
5358 // If V[i+EltStride] is undef and this is the first round of mixing,
5359 // then it is safe to just drop this shuffle: V[i] is already in the
5360 // right place, the one element (since it's the first round) being
5361 // inserted as undef can be dropped. This isn't safe for successive
5362 // rounds because they will permute elements within both vectors.
5363 if (V[i+EltStride].getOpcode() == ISD::UNDEF &&
5364 EltStride == NumElems/2)
5367 V[i] = getUnpackl(DAG, dl, VT, V[i], V[i + EltStride]);
5376 // LowerMMXCONCAT_VECTORS - We support concatenate two MMX registers and place
5377 // them in a MMX register. This is better than doing a stack convert.
5378 static SDValue LowerMMXCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
5379 DebugLoc dl = Op.getDebugLoc();
5380 EVT ResVT = Op.getValueType();
5382 assert(ResVT == MVT::v2i64 || ResVT == MVT::v4i32 ||
5383 ResVT == MVT::v8i16 || ResVT == MVT::v16i8);
5385 SDValue InVec = DAG.getNode(ISD::BITCAST,dl, MVT::v1i64, Op.getOperand(0));
5386 SDValue VecOp = DAG.getNode(X86ISD::MOVQ2DQ, dl, MVT::v2i64, InVec);
5387 InVec = Op.getOperand(1);
5388 if (InVec.getOpcode() == ISD::SCALAR_TO_VECTOR) {
5389 unsigned NumElts = ResVT.getVectorNumElements();
5390 VecOp = DAG.getNode(ISD::BITCAST, dl, ResVT, VecOp);
5391 VecOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, ResVT, VecOp,
5392 InVec.getOperand(0), DAG.getIntPtrConstant(NumElts/2+1));
5394 InVec = DAG.getNode(ISD::BITCAST, dl, MVT::v1i64, InVec);
5395 SDValue VecOp2 = DAG.getNode(X86ISD::MOVQ2DQ, dl, MVT::v2i64, InVec);
5396 Mask[0] = 0; Mask[1] = 2;
5397 VecOp = DAG.getVectorShuffle(MVT::v2i64, dl, VecOp, VecOp2, Mask);
5399 return DAG.getNode(ISD::BITCAST, dl, ResVT, VecOp);
5402 // LowerAVXCONCAT_VECTORS - 256-bit AVX can use the vinsertf128 instruction
5403 // to create 256-bit vectors from two other 128-bit ones.
5404 static SDValue LowerAVXCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
5405 DebugLoc dl = Op.getDebugLoc();
5406 EVT ResVT = Op.getValueType();
5408 assert(ResVT.getSizeInBits() == 256 && "Value type must be 256-bit wide");
5410 SDValue V1 = Op.getOperand(0);
5411 SDValue V2 = Op.getOperand(1);
5412 unsigned NumElems = ResVT.getVectorNumElements();
5414 SDValue V = Insert128BitVector(DAG.getNode(ISD::UNDEF, dl, ResVT), V1,
5415 DAG.getConstant(0, MVT::i32), DAG, dl);
5416 return Insert128BitVector(V, V2, DAG.getConstant(NumElems/2, MVT::i32),
5421 X86TargetLowering::LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) const {
5422 EVT ResVT = Op.getValueType();
5424 assert(Op.getNumOperands() == 2);
5425 assert((ResVT.getSizeInBits() == 128 || ResVT.getSizeInBits() == 256) &&
5426 "Unsupported CONCAT_VECTORS for value type");
5428 // We support concatenate two MMX registers and place them in a MMX register.
5429 // This is better than doing a stack convert.
5430 if (ResVT.is128BitVector())
5431 return LowerMMXCONCAT_VECTORS(Op, DAG);
5433 // 256-bit AVX can use the vinsertf128 instruction to create 256-bit vectors
5434 // from two other 128-bit ones.
5435 return LowerAVXCONCAT_VECTORS(Op, DAG);
5438 // v8i16 shuffles - Prefer shuffles in the following order:
5439 // 1. [all] pshuflw, pshufhw, optional move
5440 // 2. [ssse3] 1 x pshufb
5441 // 3. [ssse3] 2 x pshufb + 1 x por
5442 // 4. [all] mov + pshuflw + pshufhw + N x (pextrw + pinsrw)
5444 X86TargetLowering::LowerVECTOR_SHUFFLEv8i16(SDValue Op,
5445 SelectionDAG &DAG) const {
5446 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
5447 SDValue V1 = SVOp->getOperand(0);
5448 SDValue V2 = SVOp->getOperand(1);
5449 DebugLoc dl = SVOp->getDebugLoc();
5450 SmallVector<int, 8> MaskVals;
5452 // Determine if more than 1 of the words in each of the low and high quadwords
5453 // of the result come from the same quadword of one of the two inputs. Undef
5454 // mask values count as coming from any quadword, for better codegen.
5455 unsigned LoQuad[] = { 0, 0, 0, 0 };
5456 unsigned HiQuad[] = { 0, 0, 0, 0 };
5457 BitVector InputQuads(4);
5458 for (unsigned i = 0; i < 8; ++i) {
5459 unsigned *Quad = i < 4 ? LoQuad : HiQuad;
5460 int EltIdx = SVOp->getMaskElt(i);
5461 MaskVals.push_back(EltIdx);
5470 InputQuads.set(EltIdx / 4);
5473 int BestLoQuad = -1;
5474 unsigned MaxQuad = 1;
5475 for (unsigned i = 0; i < 4; ++i) {
5476 if (LoQuad[i] > MaxQuad) {
5478 MaxQuad = LoQuad[i];
5482 int BestHiQuad = -1;
5484 for (unsigned i = 0; i < 4; ++i) {
5485 if (HiQuad[i] > MaxQuad) {
5487 MaxQuad = HiQuad[i];
5491 // For SSSE3, If all 8 words of the result come from only 1 quadword of each
5492 // of the two input vectors, shuffle them into one input vector so only a
5493 // single pshufb instruction is necessary. If There are more than 2 input
5494 // quads, disable the next transformation since it does not help SSSE3.
5495 bool V1Used = InputQuads[0] || InputQuads[1];
5496 bool V2Used = InputQuads[2] || InputQuads[3];
5497 if (Subtarget->hasSSSE3()) {
5498 if (InputQuads.count() == 2 && V1Used && V2Used) {
5499 BestLoQuad = InputQuads.find_first();
5500 BestHiQuad = InputQuads.find_next(BestLoQuad);
5502 if (InputQuads.count() > 2) {
5508 // If BestLoQuad or BestHiQuad are set, shuffle the quads together and update
5509 // the shuffle mask. If a quad is scored as -1, that means that it contains
5510 // words from all 4 input quadwords.
5512 if (BestLoQuad >= 0 || BestHiQuad >= 0) {
5513 SmallVector<int, 8> MaskV;
5514 MaskV.push_back(BestLoQuad < 0 ? 0 : BestLoQuad);
5515 MaskV.push_back(BestHiQuad < 0 ? 1 : BestHiQuad);
5516 NewV = DAG.getVectorShuffle(MVT::v2i64, dl,
5517 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, V1),
5518 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, V2), &MaskV[0]);
5519 NewV = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, NewV);
5521 // Rewrite the MaskVals and assign NewV to V1 if NewV now contains all the
5522 // source words for the shuffle, to aid later transformations.
5523 bool AllWordsInNewV = true;
5524 bool InOrder[2] = { true, true };
5525 for (unsigned i = 0; i != 8; ++i) {
5526 int idx = MaskVals[i];
5528 InOrder[i/4] = false;
5529 if (idx < 0 || (idx/4) == BestLoQuad || (idx/4) == BestHiQuad)
5531 AllWordsInNewV = false;
5535 bool pshuflw = AllWordsInNewV, pshufhw = AllWordsInNewV;
5536 if (AllWordsInNewV) {
5537 for (int i = 0; i != 8; ++i) {
5538 int idx = MaskVals[i];
5541 idx = MaskVals[i] = (idx / 4) == BestLoQuad ? (idx & 3) : (idx & 3) + 4;
5542 if ((idx != i) && idx < 4)
5544 if ((idx != i) && idx > 3)
5553 // If we've eliminated the use of V2, and the new mask is a pshuflw or
5554 // pshufhw, that's as cheap as it gets. Return the new shuffle.
5555 if ((pshufhw && InOrder[0]) || (pshuflw && InOrder[1])) {
5556 unsigned Opc = pshufhw ? X86ISD::PSHUFHW : X86ISD::PSHUFLW;
5557 unsigned TargetMask = 0;
5558 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV,
5559 DAG.getUNDEF(MVT::v8i16), &MaskVals[0]);
5560 TargetMask = pshufhw ? X86::getShufflePSHUFHWImmediate(NewV.getNode()):
5561 X86::getShufflePSHUFLWImmediate(NewV.getNode());
5562 V1 = NewV.getOperand(0);
5563 return getTargetShuffleNode(Opc, dl, MVT::v8i16, V1, TargetMask, DAG);
5567 // If we have SSSE3, and all words of the result are from 1 input vector,
5568 // case 2 is generated, otherwise case 3 is generated. If no SSSE3
5569 // is present, fall back to case 4.
5570 if (Subtarget->hasSSSE3()) {
5571 SmallVector<SDValue,16> pshufbMask;
5573 // If we have elements from both input vectors, set the high bit of the
5574 // shuffle mask element to zero out elements that come from V2 in the V1
5575 // mask, and elements that come from V1 in the V2 mask, so that the two
5576 // results can be OR'd together.
5577 bool TwoInputs = V1Used && V2Used;
5578 for (unsigned i = 0; i != 8; ++i) {
5579 int EltIdx = MaskVals[i] * 2;
5580 if (TwoInputs && (EltIdx >= 16)) {
5581 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
5582 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
5585 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
5586 pshufbMask.push_back(DAG.getConstant(EltIdx+1, MVT::i8));
5588 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V1);
5589 V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1,
5590 DAG.getNode(ISD::BUILD_VECTOR, dl,
5591 MVT::v16i8, &pshufbMask[0], 16));
5593 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
5595 // Calculate the shuffle mask for the second input, shuffle it, and
5596 // OR it with the first shuffled input.
5598 for (unsigned i = 0; i != 8; ++i) {
5599 int EltIdx = MaskVals[i] * 2;
5601 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
5602 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
5605 pshufbMask.push_back(DAG.getConstant(EltIdx - 16, MVT::i8));
5606 pshufbMask.push_back(DAG.getConstant(EltIdx - 15, MVT::i8));
5608 V2 = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V2);
5609 V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2,
5610 DAG.getNode(ISD::BUILD_VECTOR, dl,
5611 MVT::v16i8, &pshufbMask[0], 16));
5612 V1 = DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
5613 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
5616 // If BestLoQuad >= 0, generate a pshuflw to put the low elements in order,
5617 // and update MaskVals with new element order.
5618 BitVector InOrder(8);
5619 if (BestLoQuad >= 0) {
5620 SmallVector<int, 8> MaskV;
5621 for (int i = 0; i != 4; ++i) {
5622 int idx = MaskVals[i];
5624 MaskV.push_back(-1);
5626 } else if ((idx / 4) == BestLoQuad) {
5627 MaskV.push_back(idx & 3);
5630 MaskV.push_back(-1);
5633 for (unsigned i = 4; i != 8; ++i)
5635 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16),
5638 if (NewV.getOpcode() == ISD::VECTOR_SHUFFLE && Subtarget->hasSSSE3())
5639 NewV = getTargetShuffleNode(X86ISD::PSHUFLW, dl, MVT::v8i16,
5641 X86::getShufflePSHUFLWImmediate(NewV.getNode()),
5645 // If BestHi >= 0, generate a pshufhw to put the high elements in order,
5646 // and update MaskVals with the new element order.
5647 if (BestHiQuad >= 0) {
5648 SmallVector<int, 8> MaskV;
5649 for (unsigned i = 0; i != 4; ++i)
5651 for (unsigned i = 4; i != 8; ++i) {
5652 int idx = MaskVals[i];
5654 MaskV.push_back(-1);
5656 } else if ((idx / 4) == BestHiQuad) {
5657 MaskV.push_back((idx & 3) + 4);
5660 MaskV.push_back(-1);
5663 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16),
5666 if (NewV.getOpcode() == ISD::VECTOR_SHUFFLE && Subtarget->hasSSSE3())
5667 NewV = getTargetShuffleNode(X86ISD::PSHUFHW, dl, MVT::v8i16,
5669 X86::getShufflePSHUFHWImmediate(NewV.getNode()),
5673 // In case BestHi & BestLo were both -1, which means each quadword has a word
5674 // from each of the four input quadwords, calculate the InOrder bitvector now
5675 // before falling through to the insert/extract cleanup.
5676 if (BestLoQuad == -1 && BestHiQuad == -1) {
5678 for (int i = 0; i != 8; ++i)
5679 if (MaskVals[i] < 0 || MaskVals[i] == i)
5683 // The other elements are put in the right place using pextrw and pinsrw.
5684 for (unsigned i = 0; i != 8; ++i) {
5687 int EltIdx = MaskVals[i];
5690 SDValue ExtOp = (EltIdx < 8)
5691 ? DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V1,
5692 DAG.getIntPtrConstant(EltIdx))
5693 : DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V2,
5694 DAG.getIntPtrConstant(EltIdx - 8));
5695 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, ExtOp,
5696 DAG.getIntPtrConstant(i));
5701 // v16i8 shuffles - Prefer shuffles in the following order:
5702 // 1. [ssse3] 1 x pshufb
5703 // 2. [ssse3] 2 x pshufb + 1 x por
5704 // 3. [all] v8i16 shuffle + N x pextrw + rotate + pinsrw
5706 SDValue LowerVECTOR_SHUFFLEv16i8(ShuffleVectorSDNode *SVOp,
5708 const X86TargetLowering &TLI) {
5709 SDValue V1 = SVOp->getOperand(0);
5710 SDValue V2 = SVOp->getOperand(1);
5711 DebugLoc dl = SVOp->getDebugLoc();
5712 ArrayRef<int> MaskVals = SVOp->getMask();
5714 // If we have SSSE3, case 1 is generated when all result bytes come from
5715 // one of the inputs. Otherwise, case 2 is generated. If no SSSE3 is
5716 // present, fall back to case 3.
5717 // FIXME: kill V2Only once shuffles are canonizalized by getNode.
5720 for (unsigned i = 0; i < 16; ++i) {
5721 int EltIdx = MaskVals[i];
5730 // If SSSE3, use 1 pshufb instruction per vector with elements in the result.
5731 if (TLI.getSubtarget()->hasSSSE3()) {
5732 SmallVector<SDValue,16> pshufbMask;
5734 // If all result elements are from one input vector, then only translate
5735 // undef mask values to 0x80 (zero out result) in the pshufb mask.
5737 // Otherwise, we have elements from both input vectors, and must zero out
5738 // elements that come from V2 in the first mask, and V1 in the second mask
5739 // so that we can OR them together.
5740 bool TwoInputs = !(V1Only || V2Only);
5741 for (unsigned i = 0; i != 16; ++i) {
5742 int EltIdx = MaskVals[i];
5743 if (EltIdx < 0 || (TwoInputs && EltIdx >= 16)) {
5744 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
5747 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
5749 // If all the elements are from V2, assign it to V1 and return after
5750 // building the first pshufb.
5753 V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1,
5754 DAG.getNode(ISD::BUILD_VECTOR, dl,
5755 MVT::v16i8, &pshufbMask[0], 16));
5759 // Calculate the shuffle mask for the second input, shuffle it, and
5760 // OR it with the first shuffled input.
5762 for (unsigned i = 0; i != 16; ++i) {
5763 int EltIdx = MaskVals[i];
5765 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
5768 pshufbMask.push_back(DAG.getConstant(EltIdx - 16, MVT::i8));
5770 V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2,
5771 DAG.getNode(ISD::BUILD_VECTOR, dl,
5772 MVT::v16i8, &pshufbMask[0], 16));
5773 return DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
5776 // No SSSE3 - Calculate in place words and then fix all out of place words
5777 // With 0-16 extracts & inserts. Worst case is 16 bytes out of order from
5778 // the 16 different words that comprise the two doublequadword input vectors.
5779 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
5780 V2 = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V2);
5781 SDValue NewV = V2Only ? V2 : V1;
5782 for (int i = 0; i != 8; ++i) {
5783 int Elt0 = MaskVals[i*2];
5784 int Elt1 = MaskVals[i*2+1];
5786 // This word of the result is all undef, skip it.
5787 if (Elt0 < 0 && Elt1 < 0)
5790 // This word of the result is already in the correct place, skip it.
5791 if (V1Only && (Elt0 == i*2) && (Elt1 == i*2+1))
5793 if (V2Only && (Elt0 == i*2+16) && (Elt1 == i*2+17))
5796 SDValue Elt0Src = Elt0 < 16 ? V1 : V2;
5797 SDValue Elt1Src = Elt1 < 16 ? V1 : V2;
5800 // If Elt0 and Elt1 are defined, are consecutive, and can be load
5801 // using a single extract together, load it and store it.
5802 if ((Elt0 >= 0) && ((Elt0 + 1) == Elt1) && ((Elt0 & 1) == 0)) {
5803 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src,
5804 DAG.getIntPtrConstant(Elt1 / 2));
5805 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt,
5806 DAG.getIntPtrConstant(i));
5810 // If Elt1 is defined, extract it from the appropriate source. If the
5811 // source byte is not also odd, shift the extracted word left 8 bits
5812 // otherwise clear the bottom 8 bits if we need to do an or.
5814 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src,
5815 DAG.getIntPtrConstant(Elt1 / 2));
5816 if ((Elt1 & 1) == 0)
5817 InsElt = DAG.getNode(ISD::SHL, dl, MVT::i16, InsElt,
5819 TLI.getShiftAmountTy(InsElt.getValueType())));
5821 InsElt = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt,
5822 DAG.getConstant(0xFF00, MVT::i16));
5824 // If Elt0 is defined, extract it from the appropriate source. If the
5825 // source byte is not also even, shift the extracted word right 8 bits. If
5826 // Elt1 was also defined, OR the extracted values together before
5827 // inserting them in the result.
5829 SDValue InsElt0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16,
5830 Elt0Src, DAG.getIntPtrConstant(Elt0 / 2));
5831 if ((Elt0 & 1) != 0)
5832 InsElt0 = DAG.getNode(ISD::SRL, dl, MVT::i16, InsElt0,
5834 TLI.getShiftAmountTy(InsElt0.getValueType())));
5836 InsElt0 = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt0,
5837 DAG.getConstant(0x00FF, MVT::i16));
5838 InsElt = Elt1 >= 0 ? DAG.getNode(ISD::OR, dl, MVT::i16, InsElt, InsElt0)
5841 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt,
5842 DAG.getIntPtrConstant(i));
5844 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, NewV);
5847 /// RewriteAsNarrowerShuffle - Try rewriting v8i16 and v16i8 shuffles as 4 wide
5848 /// ones, or rewriting v4i32 / v4f32 as 2 wide ones if possible. This can be
5849 /// done when every pair / quad of shuffle mask elements point to elements in
5850 /// the right sequence. e.g.
5851 /// vector_shuffle X, Y, <2, 3, | 10, 11, | 0, 1, | 14, 15>
5853 SDValue RewriteAsNarrowerShuffle(ShuffleVectorSDNode *SVOp,
5854 SelectionDAG &DAG, DebugLoc dl) {
5855 EVT VT = SVOp->getValueType(0);
5856 SDValue V1 = SVOp->getOperand(0);
5857 SDValue V2 = SVOp->getOperand(1);
5858 unsigned NumElems = VT.getVectorNumElements();
5859 unsigned NewWidth = (NumElems == 4) ? 2 : 4;
5861 switch (VT.getSimpleVT().SimpleTy) {
5862 default: assert(false && "Unexpected!");
5863 case MVT::v4f32: NewVT = MVT::v2f64; break;
5864 case MVT::v4i32: NewVT = MVT::v2i64; break;
5865 case MVT::v8i16: NewVT = MVT::v4i32; break;
5866 case MVT::v16i8: NewVT = MVT::v4i32; break;
5869 int Scale = NumElems / NewWidth;
5870 SmallVector<int, 8> MaskVec;
5871 for (unsigned i = 0; i < NumElems; i += Scale) {
5873 for (int j = 0; j < Scale; ++j) {
5874 int EltIdx = SVOp->getMaskElt(i+j);
5878 StartIdx = EltIdx - (EltIdx % Scale);
5879 if (EltIdx != StartIdx + j)
5883 MaskVec.push_back(-1);
5885 MaskVec.push_back(StartIdx / Scale);
5888 V1 = DAG.getNode(ISD::BITCAST, dl, NewVT, V1);
5889 V2 = DAG.getNode(ISD::BITCAST, dl, NewVT, V2);
5890 return DAG.getVectorShuffle(NewVT, dl, V1, V2, &MaskVec[0]);
5893 /// getVZextMovL - Return a zero-extending vector move low node.
5895 static SDValue getVZextMovL(EVT VT, EVT OpVT,
5896 SDValue SrcOp, SelectionDAG &DAG,
5897 const X86Subtarget *Subtarget, DebugLoc dl) {
5898 if (VT == MVT::v2f64 || VT == MVT::v4f32) {
5899 LoadSDNode *LD = NULL;
5900 if (!isScalarLoadToVector(SrcOp.getNode(), &LD))
5901 LD = dyn_cast<LoadSDNode>(SrcOp);
5903 // movssrr and movsdrr do not clear top bits. Try to use movd, movq
5905 MVT ExtVT = (OpVT == MVT::v2f64) ? MVT::i64 : MVT::i32;
5906 if ((ExtVT != MVT::i64 || Subtarget->is64Bit()) &&
5907 SrcOp.getOpcode() == ISD::SCALAR_TO_VECTOR &&
5908 SrcOp.getOperand(0).getOpcode() == ISD::BITCAST &&
5909 SrcOp.getOperand(0).getOperand(0).getValueType() == ExtVT) {
5911 OpVT = (OpVT == MVT::v2f64) ? MVT::v2i64 : MVT::v4i32;
5912 return DAG.getNode(ISD::BITCAST, dl, VT,
5913 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT,
5914 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
5922 return DAG.getNode(ISD::BITCAST, dl, VT,
5923 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT,
5924 DAG.getNode(ISD::BITCAST, dl,
5928 /// areShuffleHalvesWithinDisjointLanes - Check whether each half of a vector
5929 /// shuffle node referes to only one lane in the sources.
5930 static bool areShuffleHalvesWithinDisjointLanes(ShuffleVectorSDNode *SVOp) {
5931 EVT VT = SVOp->getValueType(0);
5932 int NumElems = VT.getVectorNumElements();
5933 int HalfSize = NumElems/2;
5934 ArrayRef<int> M = SVOp->getMask();
5935 bool MatchA = false, MatchB = false;
5937 for (int l = 0; l < NumElems*2; l += HalfSize) {
5938 if (isUndefOrInRange(M, 0, HalfSize, l, l+HalfSize)) {
5944 for (int l = 0; l < NumElems*2; l += HalfSize) {
5945 if (isUndefOrInRange(M, HalfSize, HalfSize, l, l+HalfSize)) {
5951 return MatchA && MatchB;
5954 /// LowerVECTOR_SHUFFLE_256 - Handle all 256-bit wide vectors shuffles
5955 /// which could not be matched by any known target speficic shuffle
5957 LowerVECTOR_SHUFFLE_256(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
5958 if (areShuffleHalvesWithinDisjointLanes(SVOp)) {
5959 // If each half of a vector shuffle node referes to only one lane in the
5960 // source vectors, extract each used 128-bit lane and shuffle them using
5961 // 128-bit shuffles. Then, concatenate the results. Otherwise leave
5962 // the work to the legalizer.
5963 DebugLoc dl = SVOp->getDebugLoc();
5964 EVT VT = SVOp->getValueType(0);
5965 int NumElems = VT.getVectorNumElements();
5966 int HalfSize = NumElems/2;
5968 // Extract the reference for each half
5969 int FstVecExtractIdx = 0, SndVecExtractIdx = 0;
5970 int FstVecOpNum = 0, SndVecOpNum = 0;
5971 for (int i = 0; i < HalfSize; ++i) {
5972 int Elt = SVOp->getMaskElt(i);
5973 if (SVOp->getMaskElt(i) < 0)
5975 FstVecOpNum = Elt/NumElems;
5976 FstVecExtractIdx = Elt % NumElems < HalfSize ? 0 : HalfSize;
5979 for (int i = HalfSize; i < NumElems; ++i) {
5980 int Elt = SVOp->getMaskElt(i);
5981 if (SVOp->getMaskElt(i) < 0)
5983 SndVecOpNum = Elt/NumElems;
5984 SndVecExtractIdx = Elt % NumElems < HalfSize ? 0 : HalfSize;
5988 // Extract the subvectors
5989 SDValue V1 = Extract128BitVector(SVOp->getOperand(FstVecOpNum),
5990 DAG.getConstant(FstVecExtractIdx, MVT::i32), DAG, dl);
5991 SDValue V2 = Extract128BitVector(SVOp->getOperand(SndVecOpNum),
5992 DAG.getConstant(SndVecExtractIdx, MVT::i32), DAG, dl);
5994 // Generate 128-bit shuffles
5995 SmallVector<int, 16> MaskV1, MaskV2;
5996 for (int i = 0; i < HalfSize; ++i) {
5997 int Elt = SVOp->getMaskElt(i);
5998 MaskV1.push_back(Elt < 0 ? Elt : Elt % HalfSize);
6000 for (int i = HalfSize; i < NumElems; ++i) {
6001 int Elt = SVOp->getMaskElt(i);
6002 MaskV2.push_back(Elt < 0 ? Elt : Elt % HalfSize);
6005 EVT NVT = V1.getValueType();
6006 V1 = DAG.getVectorShuffle(NVT, dl, V1, DAG.getUNDEF(NVT), &MaskV1[0]);
6007 V2 = DAG.getVectorShuffle(NVT, dl, V2, DAG.getUNDEF(NVT), &MaskV2[0]);
6009 // Concatenate the result back
6010 SDValue V = Insert128BitVector(DAG.getNode(ISD::UNDEF, dl, VT), V1,
6011 DAG.getConstant(0, MVT::i32), DAG, dl);
6012 return Insert128BitVector(V, V2, DAG.getConstant(NumElems/2, MVT::i32),
6019 /// LowerVECTOR_SHUFFLE_128v4 - Handle all 128-bit wide vectors with
6020 /// 4 elements, and match them with several different shuffle types.
6022 LowerVECTOR_SHUFFLE_128v4(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
6023 SDValue V1 = SVOp->getOperand(0);
6024 SDValue V2 = SVOp->getOperand(1);
6025 DebugLoc dl = SVOp->getDebugLoc();
6026 EVT VT = SVOp->getValueType(0);
6028 assert(VT.getSizeInBits() == 128 && "Unsupported vector size");
6030 SmallVector<std::pair<int, int>, 8> Locs;
6032 SmallVector<int, 8> Mask1(4U, -1);
6033 SmallVector<int, 8> PermMask(SVOp->getMask().begin(), SVOp->getMask().end());
6037 for (unsigned i = 0; i != 4; ++i) {
6038 int Idx = PermMask[i];
6040 Locs[i] = std::make_pair(-1, -1);
6042 assert(Idx < 8 && "Invalid VECTOR_SHUFFLE index!");
6044 Locs[i] = std::make_pair(0, NumLo);
6048 Locs[i] = std::make_pair(1, NumHi);
6050 Mask1[2+NumHi] = Idx;
6056 if (NumLo <= 2 && NumHi <= 2) {
6057 // If no more than two elements come from either vector. This can be
6058 // implemented with two shuffles. First shuffle gather the elements.
6059 // The second shuffle, which takes the first shuffle as both of its
6060 // vector operands, put the elements into the right order.
6061 V1 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
6063 SmallVector<int, 8> Mask2(4U, -1);
6065 for (unsigned i = 0; i != 4; ++i) {
6066 if (Locs[i].first == -1)
6069 unsigned Idx = (i < 2) ? 0 : 4;
6070 Idx += Locs[i].first * 2 + Locs[i].second;
6075 return DAG.getVectorShuffle(VT, dl, V1, V1, &Mask2[0]);
6076 } else if (NumLo == 3 || NumHi == 3) {
6077 // Otherwise, we must have three elements from one vector, call it X, and
6078 // one element from the other, call it Y. First, use a shufps to build an
6079 // intermediate vector with the one element from Y and the element from X
6080 // that will be in the same half in the final destination (the indexes don't
6081 // matter). Then, use a shufps to build the final vector, taking the half
6082 // containing the element from Y from the intermediate, and the other half
6085 // Normalize it so the 3 elements come from V1.
6086 CommuteVectorShuffleMask(PermMask, 4);
6090 // Find the element from V2.
6092 for (HiIndex = 0; HiIndex < 3; ++HiIndex) {
6093 int Val = PermMask[HiIndex];
6100 Mask1[0] = PermMask[HiIndex];
6102 Mask1[2] = PermMask[HiIndex^1];
6104 V2 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
6107 Mask1[0] = PermMask[0];
6108 Mask1[1] = PermMask[1];
6109 Mask1[2] = HiIndex & 1 ? 6 : 4;
6110 Mask1[3] = HiIndex & 1 ? 4 : 6;
6111 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
6113 Mask1[0] = HiIndex & 1 ? 2 : 0;
6114 Mask1[1] = HiIndex & 1 ? 0 : 2;
6115 Mask1[2] = PermMask[2];
6116 Mask1[3] = PermMask[3];
6121 return DAG.getVectorShuffle(VT, dl, V2, V1, &Mask1[0]);
6125 // Break it into (shuffle shuffle_hi, shuffle_lo).
6128 SmallVector<int,8> LoMask(4U, -1);
6129 SmallVector<int,8> HiMask(4U, -1);
6131 SmallVector<int,8> *MaskPtr = &LoMask;
6132 unsigned MaskIdx = 0;
6135 for (unsigned i = 0; i != 4; ++i) {
6142 int Idx = PermMask[i];
6144 Locs[i] = std::make_pair(-1, -1);
6145 } else if (Idx < 4) {
6146 Locs[i] = std::make_pair(MaskIdx, LoIdx);
6147 (*MaskPtr)[LoIdx] = Idx;
6150 Locs[i] = std::make_pair(MaskIdx, HiIdx);
6151 (*MaskPtr)[HiIdx] = Idx;
6156 SDValue LoShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &LoMask[0]);
6157 SDValue HiShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &HiMask[0]);
6158 SmallVector<int, 8> MaskOps;
6159 for (unsigned i = 0; i != 4; ++i) {
6160 if (Locs[i].first == -1) {
6161 MaskOps.push_back(-1);
6163 unsigned Idx = Locs[i].first * 4 + Locs[i].second;
6164 MaskOps.push_back(Idx);
6167 return DAG.getVectorShuffle(VT, dl, LoShuffle, HiShuffle, &MaskOps[0]);
6170 static bool MayFoldVectorLoad(SDValue V) {
6171 if (V.hasOneUse() && V.getOpcode() == ISD::BITCAST)
6172 V = V.getOperand(0);
6173 if (V.hasOneUse() && V.getOpcode() == ISD::SCALAR_TO_VECTOR)
6174 V = V.getOperand(0);
6175 if (V.hasOneUse() && V.getOpcode() == ISD::BUILD_VECTOR &&
6176 V.getNumOperands() == 2 && V.getOperand(1).getOpcode() == ISD::UNDEF)
6177 // BUILD_VECTOR (load), undef
6178 V = V.getOperand(0);
6184 // FIXME: the version above should always be used. Since there's
6185 // a bug where several vector shuffles can't be folded because the
6186 // DAG is not updated during lowering and a node claims to have two
6187 // uses while it only has one, use this version, and let isel match
6188 // another instruction if the load really happens to have more than
6189 // one use. Remove this version after this bug get fixed.
6190 // rdar://8434668, PR8156
6191 static bool RelaxedMayFoldVectorLoad(SDValue V) {
6192 if (V.hasOneUse() && V.getOpcode() == ISD::BITCAST)
6193 V = V.getOperand(0);
6194 if (V.hasOneUse() && V.getOpcode() == ISD::SCALAR_TO_VECTOR)
6195 V = V.getOperand(0);
6196 if (ISD::isNormalLoad(V.getNode()))
6201 /// CanFoldShuffleIntoVExtract - Check if the current shuffle is used by
6202 /// a vector extract, and if both can be later optimized into a single load.
6203 /// This is done in visitEXTRACT_VECTOR_ELT and the conditions are checked
6204 /// here because otherwise a target specific shuffle node is going to be
6205 /// emitted for this shuffle, and the optimization not done.
6206 /// FIXME: This is probably not the best approach, but fix the problem
6207 /// until the right path is decided.
6209 bool CanXFormVExtractWithShuffleIntoLoad(SDValue V, SelectionDAG &DAG,
6210 const TargetLowering &TLI) {
6211 EVT VT = V.getValueType();
6212 ShuffleVectorSDNode *SVOp = dyn_cast<ShuffleVectorSDNode>(V);
6214 // Be sure that the vector shuffle is present in a pattern like this:
6215 // (vextract (v4f32 shuffle (load $addr), <1,u,u,u>), c) -> (f32 load $addr)
6219 SDNode *N = *V.getNode()->use_begin();
6220 if (N->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
6223 SDValue EltNo = N->getOperand(1);
6224 if (!isa<ConstantSDNode>(EltNo))
6227 // If the bit convert changed the number of elements, it is unsafe
6228 // to examine the mask.
6229 bool HasShuffleIntoBitcast = false;
6230 if (V.getOpcode() == ISD::BITCAST) {
6231 EVT SrcVT = V.getOperand(0).getValueType();
6232 if (SrcVT.getVectorNumElements() != VT.getVectorNumElements())
6234 V = V.getOperand(0);
6235 HasShuffleIntoBitcast = true;
6238 // Select the input vector, guarding against out of range extract vector.
6239 unsigned NumElems = VT.getVectorNumElements();
6240 unsigned Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();
6241 int Idx = (Elt > NumElems) ? -1 : SVOp->getMaskElt(Elt);
6242 V = (Idx < (int)NumElems) ? V.getOperand(0) : V.getOperand(1);
6244 // Skip one more bit_convert if necessary
6245 if (V.getOpcode() == ISD::BITCAST)
6246 V = V.getOperand(0);
6248 if (!ISD::isNormalLoad(V.getNode()))
6251 // Is the original load suitable?
6252 LoadSDNode *LN0 = cast<LoadSDNode>(V);
6254 if (!LN0 || !LN0->hasNUsesOfValue(1,0) || LN0->isVolatile())
6257 if (!HasShuffleIntoBitcast)
6260 // If there's a bitcast before the shuffle, check if the load type and
6261 // alignment is valid.
6262 unsigned Align = LN0->getAlignment();
6264 TLI.getTargetData()->getABITypeAlignment(
6265 VT.getTypeForEVT(*DAG.getContext()));
6267 if (NewAlign > Align || !TLI.isOperationLegalOrCustom(ISD::LOAD, VT))
6274 SDValue getMOVDDup(SDValue &Op, DebugLoc &dl, SDValue V1, SelectionDAG &DAG) {
6275 EVT VT = Op.getValueType();
6277 // Canonizalize to v2f64.
6278 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, V1);
6279 return DAG.getNode(ISD::BITCAST, dl, VT,
6280 getTargetShuffleNode(X86ISD::MOVDDUP, dl, MVT::v2f64,
6285 SDValue getMOVLowToHigh(SDValue &Op, DebugLoc &dl, SelectionDAG &DAG,
6287 SDValue V1 = Op.getOperand(0);
6288 SDValue V2 = Op.getOperand(1);
6289 EVT VT = Op.getValueType();
6291 assert(VT != MVT::v2i64 && "unsupported shuffle type");
6293 if (HasSSE2 && VT == MVT::v2f64)
6294 return getTargetShuffleNode(X86ISD::MOVLHPD, dl, VT, V1, V2, DAG);
6296 // v4f32 or v4i32: canonizalized to v4f32 (which is legal for SSE1)
6297 return DAG.getNode(ISD::BITCAST, dl, VT,
6298 getTargetShuffleNode(X86ISD::MOVLHPS, dl, MVT::v4f32,
6299 DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V1),
6300 DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V2), DAG));
6304 SDValue getMOVHighToLow(SDValue &Op, DebugLoc &dl, SelectionDAG &DAG) {
6305 SDValue V1 = Op.getOperand(0);
6306 SDValue V2 = Op.getOperand(1);
6307 EVT VT = Op.getValueType();
6309 assert((VT == MVT::v4i32 || VT == MVT::v4f32) &&
6310 "unsupported shuffle type");
6312 if (V2.getOpcode() == ISD::UNDEF)
6316 return getTargetShuffleNode(X86ISD::MOVHLPS, dl, VT, V1, V2, DAG);
6320 SDValue getMOVLP(SDValue &Op, DebugLoc &dl, SelectionDAG &DAG, bool HasSSE2) {
6321 SDValue V1 = Op.getOperand(0);
6322 SDValue V2 = Op.getOperand(1);
6323 EVT VT = Op.getValueType();
6324 unsigned NumElems = VT.getVectorNumElements();
6326 // Use MOVLPS and MOVLPD in case V1 or V2 are loads. During isel, the second
6327 // operand of these instructions is only memory, so check if there's a
6328 // potencial load folding here, otherwise use SHUFPS or MOVSD to match the
6330 bool CanFoldLoad = false;
6332 // Trivial case, when V2 comes from a load.
6333 if (MayFoldVectorLoad(V2))
6336 // When V1 is a load, it can be folded later into a store in isel, example:
6337 // (store (v4f32 (X86Movlps (load addr:$src1), VR128:$src2)), addr:$src1)
6339 // (MOVLPSmr addr:$src1, VR128:$src2)
6340 // So, recognize this potential and also use MOVLPS or MOVLPD
6341 else if (MayFoldVectorLoad(V1) && MayFoldIntoStore(Op))
6344 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
6346 if (HasSSE2 && NumElems == 2)
6347 return getTargetShuffleNode(X86ISD::MOVLPD, dl, VT, V1, V2, DAG);
6350 // If we don't care about the second element, procede to use movss.
6351 if (SVOp->getMaskElt(1) != -1)
6352 return getTargetShuffleNode(X86ISD::MOVLPS, dl, VT, V1, V2, DAG);
6355 // movl and movlp will both match v2i64, but v2i64 is never matched by
6356 // movl earlier because we make it strict to avoid messing with the movlp load
6357 // folding logic (see the code above getMOVLP call). Match it here then,
6358 // this is horrible, but will stay like this until we move all shuffle
6359 // matching to x86 specific nodes. Note that for the 1st condition all
6360 // types are matched with movsd.
6362 // FIXME: isMOVLMask should be checked and matched before getMOVLP,
6363 // as to remove this logic from here, as much as possible
6364 if (NumElems == 2 || !X86::isMOVLMask(SVOp))
6365 return getTargetShuffleNode(X86ISD::MOVSD, dl, VT, V1, V2, DAG);
6366 return getTargetShuffleNode(X86ISD::MOVSS, dl, VT, V1, V2, DAG);
6369 assert(VT != MVT::v4i32 && "unsupported shuffle type");
6371 // Invert the operand order and use SHUFPS to match it.
6372 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V2, V1,
6373 X86::getShuffleSHUFImmediate(SVOp), DAG);
6377 SDValue NormalizeVectorShuffle(SDValue Op, SelectionDAG &DAG,
6378 const TargetLowering &TLI,
6379 const X86Subtarget *Subtarget) {
6380 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
6381 EVT VT = Op.getValueType();
6382 DebugLoc dl = Op.getDebugLoc();
6383 SDValue V1 = Op.getOperand(0);
6384 SDValue V2 = Op.getOperand(1);
6386 if (isZeroShuffle(SVOp))
6387 return getZeroVector(VT, Subtarget->hasSSE2(), Subtarget->hasAVX2(),
6390 // Handle splat operations
6391 if (SVOp->isSplat()) {
6392 unsigned NumElem = VT.getVectorNumElements();
6393 int Size = VT.getSizeInBits();
6394 // Special case, this is the only place now where it's allowed to return
6395 // a vector_shuffle operation without using a target specific node, because
6396 // *hopefully* it will be optimized away by the dag combiner. FIXME: should
6397 // this be moved to DAGCombine instead?
6398 if (NumElem <= 4 && CanXFormVExtractWithShuffleIntoLoad(Op, DAG, TLI))
6401 // Use vbroadcast whenever the splat comes from a foldable load
6402 SDValue LD = isVectorBroadcast(Op, Subtarget);
6404 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, LD);
6406 // Handle splats by matching through known shuffle masks
6407 if ((Size == 128 && NumElem <= 4) ||
6408 (Size == 256 && NumElem < 8))
6411 // All remaning splats are promoted to target supported vector shuffles.
6412 return PromoteSplat(SVOp, DAG);
6415 // If the shuffle can be profitably rewritten as a narrower shuffle, then
6417 if (VT == MVT::v8i16 || VT == MVT::v16i8) {
6418 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG, dl);
6419 if (NewOp.getNode())
6420 return DAG.getNode(ISD::BITCAST, dl, VT, NewOp);
6421 } else if ((VT == MVT::v4i32 ||
6422 (VT == MVT::v4f32 && Subtarget->hasSSE2()))) {
6423 // FIXME: Figure out a cleaner way to do this.
6424 // Try to make use of movq to zero out the top part.
6425 if (ISD::isBuildVectorAllZeros(V2.getNode())) {
6426 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG, dl);
6427 if (NewOp.getNode()) {
6428 if (isCommutedMOVL(cast<ShuffleVectorSDNode>(NewOp), true, false))
6429 return getVZextMovL(VT, NewOp.getValueType(), NewOp.getOperand(0),
6430 DAG, Subtarget, dl);
6432 } else if (ISD::isBuildVectorAllZeros(V1.getNode())) {
6433 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG, dl);
6434 if (NewOp.getNode() && X86::isMOVLMask(cast<ShuffleVectorSDNode>(NewOp)))
6435 return getVZextMovL(VT, NewOp.getValueType(), NewOp.getOperand(1),
6436 DAG, Subtarget, dl);
6443 X86TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const {
6444 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
6445 SDValue V1 = Op.getOperand(0);
6446 SDValue V2 = Op.getOperand(1);
6447 EVT VT = Op.getValueType();
6448 DebugLoc dl = Op.getDebugLoc();
6449 unsigned NumElems = VT.getVectorNumElements();
6450 bool V1IsUndef = V1.getOpcode() == ISD::UNDEF;
6451 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
6452 bool V1IsSplat = false;
6453 bool V2IsSplat = false;
6454 bool HasSSE2 = Subtarget->hasSSE2();
6455 bool HasAVX = Subtarget->hasAVX();
6456 bool HasAVX2 = Subtarget->hasAVX2();
6457 MachineFunction &MF = DAG.getMachineFunction();
6458 bool OptForSize = MF.getFunction()->hasFnAttr(Attribute::OptimizeForSize);
6460 assert(VT.getSizeInBits() != 64 && "Can't lower MMX shuffles");
6462 if (V1IsUndef && V2IsUndef)
6463 return DAG.getUNDEF(VT);
6465 assert(!V1IsUndef && "Op 1 of shuffle should not be undef");
6467 // Vector shuffle lowering takes 3 steps:
6469 // 1) Normalize the input vectors. Here splats, zeroed vectors, profitable
6470 // narrowing and commutation of operands should be handled.
6471 // 2) Matching of shuffles with known shuffle masks to x86 target specific
6473 // 3) Rewriting of unmatched masks into new generic shuffle operations,
6474 // so the shuffle can be broken into other shuffles and the legalizer can
6475 // try the lowering again.
6477 // The general idea is that no vector_shuffle operation should be left to
6478 // be matched during isel, all of them must be converted to a target specific
6481 // Normalize the input vectors. Here splats, zeroed vectors, profitable
6482 // narrowing and commutation of operands should be handled. The actual code
6483 // doesn't include all of those, work in progress...
6484 SDValue NewOp = NormalizeVectorShuffle(Op, DAG, *this, Subtarget);
6485 if (NewOp.getNode())
6488 // NOTE: isPSHUFDMask can also match both masks below (unpckl_undef and
6489 // unpckh_undef). Only use pshufd if speed is more important than size.
6490 if (OptForSize && X86::isUNPCKL_v_undef_Mask(SVOp, HasAVX2))
6491 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
6492 if (OptForSize && X86::isUNPCKH_v_undef_Mask(SVOp, HasAVX2))
6493 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
6495 if (X86::isMOVDDUPMask(SVOp) && Subtarget->hasSSE3() &&
6496 V2IsUndef && RelaxedMayFoldVectorLoad(V1))
6497 return getMOVDDup(Op, dl, V1, DAG);
6499 if (X86::isMOVHLPS_v_undef_Mask(SVOp))
6500 return getMOVHighToLow(Op, dl, DAG);
6502 // Use to match splats
6503 if (HasSSE2 && X86::isUNPCKHMask(SVOp, HasAVX2) && V2IsUndef &&
6504 (VT == MVT::v2f64 || VT == MVT::v2i64))
6505 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
6507 if (X86::isPSHUFDMask(SVOp)) {
6508 // The actual implementation will match the mask in the if above and then
6509 // during isel it can match several different instructions, not only pshufd
6510 // as its name says, sad but true, emulate the behavior for now...
6511 if (X86::isMOVDDUPMask(SVOp) && ((VT == MVT::v4f32 || VT == MVT::v2i64)))
6512 return getTargetShuffleNode(X86ISD::MOVLHPS, dl, VT, V1, V1, DAG);
6514 unsigned TargetMask = X86::getShuffleSHUFImmediate(SVOp);
6516 if (HasSSE2 && (VT == MVT::v4f32 || VT == MVT::v4i32))
6517 return getTargetShuffleNode(X86ISD::PSHUFD, dl, VT, V1, TargetMask, DAG);
6519 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V1, V1,
6523 // Check if this can be converted into a logical shift.
6524 bool isLeft = false;
6527 bool isShift = HasSSE2 && isVectorShift(SVOp, DAG, isLeft, ShVal, ShAmt);
6528 if (isShift && ShVal.hasOneUse()) {
6529 // If the shifted value has multiple uses, it may be cheaper to use
6530 // v_set0 + movlhps or movhlps, etc.
6531 EVT EltVT = VT.getVectorElementType();
6532 ShAmt *= EltVT.getSizeInBits();
6533 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl);
6536 if (X86::isMOVLMask(SVOp)) {
6537 if (ISD::isBuildVectorAllZeros(V1.getNode()))
6538 return getVZextMovL(VT, VT, V2, DAG, Subtarget, dl);
6539 if (!X86::isMOVLPMask(SVOp)) {
6540 if (HasSSE2 && (VT == MVT::v2i64 || VT == MVT::v2f64))
6541 return getTargetShuffleNode(X86ISD::MOVSD, dl, VT, V1, V2, DAG);
6543 if (VT == MVT::v4i32 || VT == MVT::v4f32)
6544 return getTargetShuffleNode(X86ISD::MOVSS, dl, VT, V1, V2, DAG);
6548 // FIXME: fold these into legal mask.
6549 if (X86::isMOVLHPSMask(SVOp) && !X86::isUNPCKLMask(SVOp, HasAVX2))
6550 return getMOVLowToHigh(Op, dl, DAG, HasSSE2);
6552 if (X86::isMOVHLPSMask(SVOp))
6553 return getMOVHighToLow(Op, dl, DAG);
6555 if (X86::isMOVSHDUPMask(SVOp, Subtarget))
6556 return getTargetShuffleNode(X86ISD::MOVSHDUP, dl, VT, V1, DAG);
6558 if (X86::isMOVSLDUPMask(SVOp, Subtarget))
6559 return getTargetShuffleNode(X86ISD::MOVSLDUP, dl, VT, V1, DAG);
6561 if (X86::isMOVLPMask(SVOp))
6562 return getMOVLP(Op, dl, DAG, HasSSE2);
6564 if (ShouldXformToMOVHLPS(SVOp) ||
6565 ShouldXformToMOVLP(V1.getNode(), V2.getNode(), SVOp))
6566 return CommuteVectorShuffle(SVOp, DAG);
6569 // No better options. Use a vshl / vsrl.
6570 EVT EltVT = VT.getVectorElementType();
6571 ShAmt *= EltVT.getSizeInBits();
6572 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl);
6575 bool Commuted = false;
6576 // FIXME: This should also accept a bitcast of a splat? Be careful, not
6577 // 1,1,1,1 -> v8i16 though.
6578 V1IsSplat = isSplatVector(V1.getNode());
6579 V2IsSplat = isSplatVector(V2.getNode());
6581 // Canonicalize the splat or undef, if present, to be on the RHS.
6582 if (V1IsSplat && !V2IsSplat) {
6583 Op = CommuteVectorShuffle(SVOp, DAG);
6584 SVOp = cast<ShuffleVectorSDNode>(Op);
6585 V1 = SVOp->getOperand(0);
6586 V2 = SVOp->getOperand(1);
6587 std::swap(V1IsSplat, V2IsSplat);
6591 ArrayRef<int> M = SVOp->getMask();
6593 if (isCommutedMOVLMask(M, VT, V2IsSplat, V2IsUndef)) {
6594 // Shuffling low element of v1 into undef, just return v1.
6597 // If V2 is a splat, the mask may be malformed such as <4,3,3,3>, which
6598 // the instruction selector will not match, so get a canonical MOVL with
6599 // swapped operands to undo the commute.
6600 return getMOVL(DAG, dl, VT, V2, V1);
6603 if (isUNPCKLMask(M, VT, HasAVX2))
6604 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG);
6606 if (isUNPCKHMask(M, VT, HasAVX2))
6607 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG);
6610 // Normalize mask so all entries that point to V2 points to its first
6611 // element then try to match unpck{h|l} again. If match, return a
6612 // new vector_shuffle with the corrected mask.
6613 SDValue NewMask = NormalizeMask(SVOp, DAG);
6614 ShuffleVectorSDNode *NSVOp = cast<ShuffleVectorSDNode>(NewMask);
6615 if (NSVOp != SVOp) {
6616 if (X86::isUNPCKLMask(NSVOp, HasAVX2, true)) {
6618 } else if (X86::isUNPCKHMask(NSVOp, HasAVX2, true)) {
6625 // Commute is back and try unpck* again.
6626 // FIXME: this seems wrong.
6627 SDValue NewOp = CommuteVectorShuffle(SVOp, DAG);
6628 ShuffleVectorSDNode *NewSVOp = cast<ShuffleVectorSDNode>(NewOp);
6630 if (X86::isUNPCKLMask(NewSVOp, HasAVX2))
6631 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V2, V1, DAG);
6633 if (X86::isUNPCKHMask(NewSVOp, HasAVX2))
6634 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V2, V1, DAG);
6637 // Normalize the node to match x86 shuffle ops if needed
6638 if (!V2IsUndef && (isSHUFPMask(M, VT, /* Commuted */ true) ||
6639 isVSHUFPYMask(M, VT, HasAVX, /* Commuted */ true)))
6640 return CommuteVectorShuffle(SVOp, DAG);
6642 // The checks below are all present in isShuffleMaskLegal, but they are
6643 // inlined here right now to enable us to directly emit target specific
6644 // nodes, and remove one by one until they don't return Op anymore.
6646 if (isPALIGNRMask(M, VT, Subtarget->hasSSSE3()))
6647 return getTargetShuffleNode(X86ISD::PALIGN, dl, VT, V1, V2,
6648 getShufflePALIGNRImmediate(SVOp),
6651 if (ShuffleVectorSDNode::isSplatMask(&M[0], VT) &&
6652 SVOp->getSplatIndex() == 0 && V2IsUndef) {
6653 if (VT == MVT::v2f64 || VT == MVT::v2i64)
6654 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
6657 if (isPSHUFHWMask(M, VT))
6658 return getTargetShuffleNode(X86ISD::PSHUFHW, dl, VT, V1,
6659 X86::getShufflePSHUFHWImmediate(SVOp),
6662 if (isPSHUFLWMask(M, VT))
6663 return getTargetShuffleNode(X86ISD::PSHUFLW, dl, VT, V1,
6664 X86::getShufflePSHUFLWImmediate(SVOp),
6667 if (isSHUFPMask(M, VT))
6668 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V1, V2,
6669 X86::getShuffleSHUFImmediate(SVOp), DAG);
6671 if (isUNPCKL_v_undef_Mask(M, VT, HasAVX2))
6672 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
6673 if (isUNPCKH_v_undef_Mask(M, VT, HasAVX2))
6674 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
6676 //===--------------------------------------------------------------------===//
6677 // Generate target specific nodes for 128 or 256-bit shuffles only
6678 // supported in the AVX instruction set.
6681 // Handle VMOVDDUPY permutations
6682 if (V2IsUndef && isMOVDDUPYMask(M, VT, HasAVX))
6683 return getTargetShuffleNode(X86ISD::MOVDDUP, dl, VT, V1, DAG);
6685 // Handle VPERMILPS/D* permutations
6686 if (isVPERMILPMask(M, VT, HasAVX))
6687 return getTargetShuffleNode(X86ISD::VPERMILP, dl, VT, V1,
6688 getShuffleVPERMILPImmediate(SVOp), DAG);
6690 // Handle VPERM2F128/VPERM2I128 permutations
6691 if (isVPERM2X128Mask(M, VT, HasAVX))
6692 return getTargetShuffleNode(X86ISD::VPERM2X128, dl, VT, V1,
6693 V2, getShuffleVPERM2X128Immediate(SVOp), DAG);
6695 // Handle VSHUFPS/DY permutations
6696 if (isVSHUFPYMask(M, VT, HasAVX))
6697 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V1, V2,
6698 getShuffleVSHUFPYImmediate(SVOp), DAG);
6700 //===--------------------------------------------------------------------===//
6701 // Since no target specific shuffle was selected for this generic one,
6702 // lower it into other known shuffles. FIXME: this isn't true yet, but
6703 // this is the plan.
6706 // Handle v8i16 specifically since SSE can do byte extraction and insertion.
6707 if (VT == MVT::v8i16) {
6708 SDValue NewOp = LowerVECTOR_SHUFFLEv8i16(Op, DAG);
6709 if (NewOp.getNode())
6713 if (VT == MVT::v16i8) {
6714 SDValue NewOp = LowerVECTOR_SHUFFLEv16i8(SVOp, DAG, *this);
6715 if (NewOp.getNode())
6719 // Handle all 128-bit wide vectors with 4 elements, and match them with
6720 // several different shuffle types.
6721 if (NumElems == 4 && VT.getSizeInBits() == 128)
6722 return LowerVECTOR_SHUFFLE_128v4(SVOp, DAG);
6724 // Handle general 256-bit shuffles
6725 if (VT.is256BitVector())
6726 return LowerVECTOR_SHUFFLE_256(SVOp, DAG);
6732 X86TargetLowering::LowerEXTRACT_VECTOR_ELT_SSE4(SDValue Op,
6733 SelectionDAG &DAG) const {
6734 EVT VT = Op.getValueType();
6735 DebugLoc dl = Op.getDebugLoc();
6737 if (Op.getOperand(0).getValueType().getSizeInBits() != 128)
6740 if (VT.getSizeInBits() == 8) {
6741 SDValue Extract = DAG.getNode(X86ISD::PEXTRB, dl, MVT::i32,
6742 Op.getOperand(0), Op.getOperand(1));
6743 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
6744 DAG.getValueType(VT));
6745 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
6746 } else if (VT.getSizeInBits() == 16) {
6747 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
6748 // If Idx is 0, it's cheaper to do a move instead of a pextrw.
6750 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
6751 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
6752 DAG.getNode(ISD::BITCAST, dl,
6756 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, MVT::i32,
6757 Op.getOperand(0), Op.getOperand(1));
6758 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
6759 DAG.getValueType(VT));
6760 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
6761 } else if (VT == MVT::f32) {
6762 // EXTRACTPS outputs to a GPR32 register which will require a movd to copy
6763 // the result back to FR32 register. It's only worth matching if the
6764 // result has a single use which is a store or a bitcast to i32. And in
6765 // the case of a store, it's not worth it if the index is a constant 0,
6766 // because a MOVSSmr can be used instead, which is smaller and faster.
6767 if (!Op.hasOneUse())
6769 SDNode *User = *Op.getNode()->use_begin();
6770 if ((User->getOpcode() != ISD::STORE ||
6771 (isa<ConstantSDNode>(Op.getOperand(1)) &&
6772 cast<ConstantSDNode>(Op.getOperand(1))->isNullValue())) &&
6773 (User->getOpcode() != ISD::BITCAST ||
6774 User->getValueType(0) != MVT::i32))
6776 SDValue Extract = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
6777 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32,
6780 return DAG.getNode(ISD::BITCAST, dl, MVT::f32, Extract);
6781 } else if (VT == MVT::i32 || VT == MVT::i64) {
6782 // ExtractPS/pextrq works with constant index.
6783 if (isa<ConstantSDNode>(Op.getOperand(1)))
6791 X86TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op,
6792 SelectionDAG &DAG) const {
6793 if (!isa<ConstantSDNode>(Op.getOperand(1)))
6796 SDValue Vec = Op.getOperand(0);
6797 EVT VecVT = Vec.getValueType();
6799 // If this is a 256-bit vector result, first extract the 128-bit vector and
6800 // then extract the element from the 128-bit vector.
6801 if (VecVT.getSizeInBits() == 256) {
6802 DebugLoc dl = Op.getNode()->getDebugLoc();
6803 unsigned NumElems = VecVT.getVectorNumElements();
6804 SDValue Idx = Op.getOperand(1);
6805 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
6807 // Get the 128-bit vector.
6808 bool Upper = IdxVal >= NumElems/2;
6809 Vec = Extract128BitVector(Vec,
6810 DAG.getConstant(Upper ? NumElems/2 : 0, MVT::i32), DAG, dl);
6812 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, Op.getValueType(), Vec,
6813 Upper ? DAG.getConstant(IdxVal-NumElems/2, MVT::i32) : Idx);
6816 assert(Vec.getValueSizeInBits() <= 128 && "Unexpected vector length");
6818 if (Subtarget->hasSSE41()) {
6819 SDValue Res = LowerEXTRACT_VECTOR_ELT_SSE4(Op, DAG);
6824 EVT VT = Op.getValueType();
6825 DebugLoc dl = Op.getDebugLoc();
6826 // TODO: handle v16i8.
6827 if (VT.getSizeInBits() == 16) {
6828 SDValue Vec = Op.getOperand(0);
6829 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
6831 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
6832 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
6833 DAG.getNode(ISD::BITCAST, dl,
6836 // Transform it so it match pextrw which produces a 32-bit result.
6837 EVT EltVT = MVT::i32;
6838 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, EltVT,
6839 Op.getOperand(0), Op.getOperand(1));
6840 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, EltVT, Extract,
6841 DAG.getValueType(VT));
6842 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
6843 } else if (VT.getSizeInBits() == 32) {
6844 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
6848 // SHUFPS the element to the lowest double word, then movss.
6849 int Mask[4] = { static_cast<int>(Idx), -1, -1, -1 };
6850 EVT VVT = Op.getOperand(0).getValueType();
6851 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
6852 DAG.getUNDEF(VVT), Mask);
6853 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
6854 DAG.getIntPtrConstant(0));
6855 } else if (VT.getSizeInBits() == 64) {
6856 // FIXME: .td only matches this for <2 x f64>, not <2 x i64> on 32b
6857 // FIXME: seems like this should be unnecessary if mov{h,l}pd were taught
6858 // to match extract_elt for f64.
6859 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
6863 // UNPCKHPD the element to the lowest double word, then movsd.
6864 // Note if the lower 64 bits of the result of the UNPCKHPD is then stored
6865 // to a f64mem, the whole operation is folded into a single MOVHPDmr.
6866 int Mask[2] = { 1, -1 };
6867 EVT VVT = Op.getOperand(0).getValueType();
6868 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
6869 DAG.getUNDEF(VVT), Mask);
6870 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
6871 DAG.getIntPtrConstant(0));
6878 X86TargetLowering::LowerINSERT_VECTOR_ELT_SSE4(SDValue Op,
6879 SelectionDAG &DAG) const {
6880 EVT VT = Op.getValueType();
6881 EVT EltVT = VT.getVectorElementType();
6882 DebugLoc dl = Op.getDebugLoc();
6884 SDValue N0 = Op.getOperand(0);
6885 SDValue N1 = Op.getOperand(1);
6886 SDValue N2 = Op.getOperand(2);
6888 if (VT.getSizeInBits() == 256)
6891 if ((EltVT.getSizeInBits() == 8 || EltVT.getSizeInBits() == 16) &&
6892 isa<ConstantSDNode>(N2)) {
6894 if (VT == MVT::v8i16)
6895 Opc = X86ISD::PINSRW;
6896 else if (VT == MVT::v16i8)
6897 Opc = X86ISD::PINSRB;
6899 Opc = X86ISD::PINSRB;
6901 // Transform it so it match pinsr{b,w} which expects a GR32 as its second
6903 if (N1.getValueType() != MVT::i32)
6904 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
6905 if (N2.getValueType() != MVT::i32)
6906 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue());
6907 return DAG.getNode(Opc, dl, VT, N0, N1, N2);
6908 } else if (EltVT == MVT::f32 && isa<ConstantSDNode>(N2)) {
6909 // Bits [7:6] of the constant are the source select. This will always be
6910 // zero here. The DAG Combiner may combine an extract_elt index into these
6911 // bits. For example (insert (extract, 3), 2) could be matched by putting
6912 // the '3' into bits [7:6] of X86ISD::INSERTPS.
6913 // Bits [5:4] of the constant are the destination select. This is the
6914 // value of the incoming immediate.
6915 // Bits [3:0] of the constant are the zero mask. The DAG Combiner may
6916 // combine either bitwise AND or insert of float 0.0 to set these bits.
6917 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue() << 4);
6918 // Create this as a scalar to vector..
6919 N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4f32, N1);
6920 return DAG.getNode(X86ISD::INSERTPS, dl, VT, N0, N1, N2);
6921 } else if ((EltVT == MVT::i32 || EltVT == MVT::i64) &&
6922 isa<ConstantSDNode>(N2)) {
6923 // PINSR* works with constant index.
6930 X86TargetLowering::LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const {
6931 EVT VT = Op.getValueType();
6932 EVT EltVT = VT.getVectorElementType();
6934 DebugLoc dl = Op.getDebugLoc();
6935 SDValue N0 = Op.getOperand(0);
6936 SDValue N1 = Op.getOperand(1);
6937 SDValue N2 = Op.getOperand(2);
6939 // If this is a 256-bit vector result, first extract the 128-bit vector,
6940 // insert the element into the extracted half and then place it back.
6941 if (VT.getSizeInBits() == 256) {
6942 if (!isa<ConstantSDNode>(N2))
6945 // Get the desired 128-bit vector half.
6946 unsigned NumElems = VT.getVectorNumElements();
6947 unsigned IdxVal = cast<ConstantSDNode>(N2)->getZExtValue();
6948 bool Upper = IdxVal >= NumElems/2;
6949 SDValue Ins128Idx = DAG.getConstant(Upper ? NumElems/2 : 0, MVT::i32);
6950 SDValue V = Extract128BitVector(N0, Ins128Idx, DAG, dl);
6952 // Insert the element into the desired half.
6953 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, V.getValueType(), V,
6954 N1, Upper ? DAG.getConstant(IdxVal-NumElems/2, MVT::i32) : N2);
6956 // Insert the changed part back to the 256-bit vector
6957 return Insert128BitVector(N0, V, Ins128Idx, DAG, dl);
6960 if (Subtarget->hasSSE41())
6961 return LowerINSERT_VECTOR_ELT_SSE4(Op, DAG);
6963 if (EltVT == MVT::i8)
6966 if (EltVT.getSizeInBits() == 16 && isa<ConstantSDNode>(N2)) {
6967 // Transform it so it match pinsrw which expects a 16-bit value in a GR32
6968 // as its second argument.
6969 if (N1.getValueType() != MVT::i32)
6970 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
6971 if (N2.getValueType() != MVT::i32)
6972 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue());
6973 return DAG.getNode(X86ISD::PINSRW, dl, VT, N0, N1, N2);
6979 X86TargetLowering::LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) const {
6980 LLVMContext *Context = DAG.getContext();
6981 DebugLoc dl = Op.getDebugLoc();
6982 EVT OpVT = Op.getValueType();
6984 // If this is a 256-bit vector result, first insert into a 128-bit
6985 // vector and then insert into the 256-bit vector.
6986 if (OpVT.getSizeInBits() > 128) {
6987 // Insert into a 128-bit vector.
6988 EVT VT128 = EVT::getVectorVT(*Context,
6989 OpVT.getVectorElementType(),
6990 OpVT.getVectorNumElements() / 2);
6992 Op = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT128, Op.getOperand(0));
6994 // Insert the 128-bit vector.
6995 return Insert128BitVector(DAG.getNode(ISD::UNDEF, dl, OpVT), Op,
6996 DAG.getConstant(0, MVT::i32),
7000 if (Op.getValueType() == MVT::v1i64 &&
7001 Op.getOperand(0).getValueType() == MVT::i64)
7002 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v1i64, Op.getOperand(0));
7004 SDValue AnyExt = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, Op.getOperand(0));
7005 assert(Op.getValueType().getSimpleVT().getSizeInBits() == 128 &&
7006 "Expected an SSE type!");
7007 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(),
7008 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,AnyExt));
7011 // Lower a node with an EXTRACT_SUBVECTOR opcode. This may result in
7012 // a simple subregister reference or explicit instructions to grab
7013 // upper bits of a vector.
7015 X86TargetLowering::LowerEXTRACT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const {
7016 if (Subtarget->hasAVX()) {
7017 DebugLoc dl = Op.getNode()->getDebugLoc();
7018 SDValue Vec = Op.getNode()->getOperand(0);
7019 SDValue Idx = Op.getNode()->getOperand(1);
7021 if (Op.getNode()->getValueType(0).getSizeInBits() == 128
7022 && Vec.getNode()->getValueType(0).getSizeInBits() == 256) {
7023 return Extract128BitVector(Vec, Idx, DAG, dl);
7029 // Lower a node with an INSERT_SUBVECTOR opcode. This may result in a
7030 // simple superregister reference or explicit instructions to insert
7031 // the upper bits of a vector.
7033 X86TargetLowering::LowerINSERT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const {
7034 if (Subtarget->hasAVX()) {
7035 DebugLoc dl = Op.getNode()->getDebugLoc();
7036 SDValue Vec = Op.getNode()->getOperand(0);
7037 SDValue SubVec = Op.getNode()->getOperand(1);
7038 SDValue Idx = Op.getNode()->getOperand(2);
7040 if (Op.getNode()->getValueType(0).getSizeInBits() == 256
7041 && SubVec.getNode()->getValueType(0).getSizeInBits() == 128) {
7042 return Insert128BitVector(Vec, SubVec, Idx, DAG, dl);
7048 // ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as
7049 // their target countpart wrapped in the X86ISD::Wrapper node. Suppose N is
7050 // one of the above mentioned nodes. It has to be wrapped because otherwise
7051 // Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only
7052 // be used to form addressing mode. These wrapped nodes will be selected
7055 X86TargetLowering::LowerConstantPool(SDValue Op, SelectionDAG &DAG) const {
7056 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
7058 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
7060 unsigned char OpFlag = 0;
7061 unsigned WrapperKind = X86ISD::Wrapper;
7062 CodeModel::Model M = getTargetMachine().getCodeModel();
7064 if (Subtarget->isPICStyleRIPRel() &&
7065 (M == CodeModel::Small || M == CodeModel::Kernel))
7066 WrapperKind = X86ISD::WrapperRIP;
7067 else if (Subtarget->isPICStyleGOT())
7068 OpFlag = X86II::MO_GOTOFF;
7069 else if (Subtarget->isPICStyleStubPIC())
7070 OpFlag = X86II::MO_PIC_BASE_OFFSET;
7072 SDValue Result = DAG.getTargetConstantPool(CP->getConstVal(), getPointerTy(),
7074 CP->getOffset(), OpFlag);
7075 DebugLoc DL = CP->getDebugLoc();
7076 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
7077 // With PIC, the address is actually $g + Offset.
7079 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
7080 DAG.getNode(X86ISD::GlobalBaseReg,
7081 DebugLoc(), getPointerTy()),
7088 SDValue X86TargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) const {
7089 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
7091 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
7093 unsigned char OpFlag = 0;
7094 unsigned WrapperKind = X86ISD::Wrapper;
7095 CodeModel::Model M = getTargetMachine().getCodeModel();
7097 if (Subtarget->isPICStyleRIPRel() &&
7098 (M == CodeModel::Small || M == CodeModel::Kernel))
7099 WrapperKind = X86ISD::WrapperRIP;
7100 else if (Subtarget->isPICStyleGOT())
7101 OpFlag = X86II::MO_GOTOFF;
7102 else if (Subtarget->isPICStyleStubPIC())
7103 OpFlag = X86II::MO_PIC_BASE_OFFSET;
7105 SDValue Result = DAG.getTargetJumpTable(JT->getIndex(), getPointerTy(),
7107 DebugLoc DL = JT->getDebugLoc();
7108 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
7110 // With PIC, the address is actually $g + Offset.
7112 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
7113 DAG.getNode(X86ISD::GlobalBaseReg,
7114 DebugLoc(), getPointerTy()),
7121 X86TargetLowering::LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) const {
7122 const char *Sym = cast<ExternalSymbolSDNode>(Op)->getSymbol();
7124 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
7126 unsigned char OpFlag = 0;
7127 unsigned WrapperKind = X86ISD::Wrapper;
7128 CodeModel::Model M = getTargetMachine().getCodeModel();
7130 if (Subtarget->isPICStyleRIPRel() &&
7131 (M == CodeModel::Small || M == CodeModel::Kernel)) {
7132 if (Subtarget->isTargetDarwin() || Subtarget->isTargetELF())
7133 OpFlag = X86II::MO_GOTPCREL;
7134 WrapperKind = X86ISD::WrapperRIP;
7135 } else if (Subtarget->isPICStyleGOT()) {
7136 OpFlag = X86II::MO_GOT;
7137 } else if (Subtarget->isPICStyleStubPIC()) {
7138 OpFlag = X86II::MO_DARWIN_NONLAZY_PIC_BASE;
7139 } else if (Subtarget->isPICStyleStubNoDynamic()) {
7140 OpFlag = X86II::MO_DARWIN_NONLAZY;
7143 SDValue Result = DAG.getTargetExternalSymbol(Sym, getPointerTy(), OpFlag);
7145 DebugLoc DL = Op.getDebugLoc();
7146 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
7149 // With PIC, the address is actually $g + Offset.
7150 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
7151 !Subtarget->is64Bit()) {
7152 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
7153 DAG.getNode(X86ISD::GlobalBaseReg,
7154 DebugLoc(), getPointerTy()),
7158 // For symbols that require a load from a stub to get the address, emit the
7160 if (isGlobalStubReference(OpFlag))
7161 Result = DAG.getLoad(getPointerTy(), DL, DAG.getEntryNode(), Result,
7162 MachinePointerInfo::getGOT(), false, false, false, 0);
7168 X86TargetLowering::LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const {
7169 // Create the TargetBlockAddressAddress node.
7170 unsigned char OpFlags =
7171 Subtarget->ClassifyBlockAddressReference();
7172 CodeModel::Model M = getTargetMachine().getCodeModel();
7173 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
7174 DebugLoc dl = Op.getDebugLoc();
7175 SDValue Result = DAG.getBlockAddress(BA, getPointerTy(),
7176 /*isTarget=*/true, OpFlags);
7178 if (Subtarget->isPICStyleRIPRel() &&
7179 (M == CodeModel::Small || M == CodeModel::Kernel))
7180 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
7182 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
7184 // With PIC, the address is actually $g + Offset.
7185 if (isGlobalRelativeToPICBase(OpFlags)) {
7186 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
7187 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
7195 X86TargetLowering::LowerGlobalAddress(const GlobalValue *GV, DebugLoc dl,
7197 SelectionDAG &DAG) const {
7198 // Create the TargetGlobalAddress node, folding in the constant
7199 // offset if it is legal.
7200 unsigned char OpFlags =
7201 Subtarget->ClassifyGlobalReference(GV, getTargetMachine());
7202 CodeModel::Model M = getTargetMachine().getCodeModel();
7204 if (OpFlags == X86II::MO_NO_FLAG &&
7205 X86::isOffsetSuitableForCodeModel(Offset, M)) {
7206 // A direct static reference to a global.
7207 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), Offset);
7210 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), 0, OpFlags);
7213 if (Subtarget->isPICStyleRIPRel() &&
7214 (M == CodeModel::Small || M == CodeModel::Kernel))
7215 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
7217 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
7219 // With PIC, the address is actually $g + Offset.
7220 if (isGlobalRelativeToPICBase(OpFlags)) {
7221 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
7222 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
7226 // For globals that require a load from a stub to get the address, emit the
7228 if (isGlobalStubReference(OpFlags))
7229 Result = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Result,
7230 MachinePointerInfo::getGOT(), false, false, false, 0);
7232 // If there was a non-zero offset that we didn't fold, create an explicit
7235 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(), Result,
7236 DAG.getConstant(Offset, getPointerTy()));
7242 X86TargetLowering::LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const {
7243 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
7244 int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset();
7245 return LowerGlobalAddress(GV, Op.getDebugLoc(), Offset, DAG);
7249 GetTLSADDR(SelectionDAG &DAG, SDValue Chain, GlobalAddressSDNode *GA,
7250 SDValue *InFlag, const EVT PtrVT, unsigned ReturnReg,
7251 unsigned char OperandFlags) {
7252 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
7253 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
7254 DebugLoc dl = GA->getDebugLoc();
7255 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
7256 GA->getValueType(0),
7260 SDValue Ops[] = { Chain, TGA, *InFlag };
7261 Chain = DAG.getNode(X86ISD::TLSADDR, dl, NodeTys, Ops, 3);
7263 SDValue Ops[] = { Chain, TGA };
7264 Chain = DAG.getNode(X86ISD::TLSADDR, dl, NodeTys, Ops, 2);
7267 // TLSADDR will be codegen'ed as call. Inform MFI that function has calls.
7268 MFI->setAdjustsStack(true);
7270 SDValue Flag = Chain.getValue(1);
7271 return DAG.getCopyFromReg(Chain, dl, ReturnReg, PtrVT, Flag);
7274 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 32 bit
7276 LowerToTLSGeneralDynamicModel32(GlobalAddressSDNode *GA, SelectionDAG &DAG,
7279 DebugLoc dl = GA->getDebugLoc(); // ? function entry point might be better
7280 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
7281 DAG.getNode(X86ISD::GlobalBaseReg,
7282 DebugLoc(), PtrVT), InFlag);
7283 InFlag = Chain.getValue(1);
7285 return GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX, X86II::MO_TLSGD);
7288 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 64 bit
7290 LowerToTLSGeneralDynamicModel64(GlobalAddressSDNode *GA, SelectionDAG &DAG,
7292 return GetTLSADDR(DAG, DAG.getEntryNode(), GA, NULL, PtrVT,
7293 X86::RAX, X86II::MO_TLSGD);
7296 // Lower ISD::GlobalTLSAddress using the "initial exec" (for no-pic) or
7297 // "local exec" model.
7298 static SDValue LowerToTLSExecModel(GlobalAddressSDNode *GA, SelectionDAG &DAG,
7299 const EVT PtrVT, TLSModel::Model model,
7301 DebugLoc dl = GA->getDebugLoc();
7303 // Get the Thread Pointer, which is %gs:0 (32-bit) or %fs:0 (64-bit).
7304 Value *Ptr = Constant::getNullValue(Type::getInt8PtrTy(*DAG.getContext(),
7305 is64Bit ? 257 : 256));
7307 SDValue ThreadPointer = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
7308 DAG.getIntPtrConstant(0),
7309 MachinePointerInfo(Ptr),
7310 false, false, false, 0);
7312 unsigned char OperandFlags = 0;
7313 // Most TLS accesses are not RIP relative, even on x86-64. One exception is
7315 unsigned WrapperKind = X86ISD::Wrapper;
7316 if (model == TLSModel::LocalExec) {
7317 OperandFlags = is64Bit ? X86II::MO_TPOFF : X86II::MO_NTPOFF;
7318 } else if (is64Bit) {
7319 assert(model == TLSModel::InitialExec);
7320 OperandFlags = X86II::MO_GOTTPOFF;
7321 WrapperKind = X86ISD::WrapperRIP;
7323 assert(model == TLSModel::InitialExec);
7324 OperandFlags = X86II::MO_INDNTPOFF;
7327 // emit "addl x@ntpoff,%eax" (local exec) or "addl x@indntpoff,%eax" (initial
7329 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
7330 GA->getValueType(0),
7331 GA->getOffset(), OperandFlags);
7332 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
7334 if (model == TLSModel::InitialExec)
7335 Offset = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Offset,
7336 MachinePointerInfo::getGOT(), false, false, false, 0);
7338 // The address of the thread local variable is the add of the thread
7339 // pointer with the offset of the variable.
7340 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset);
7344 X86TargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const {
7346 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
7347 const GlobalValue *GV = GA->getGlobal();
7349 if (Subtarget->isTargetELF()) {
7350 // TODO: implement the "local dynamic" model
7351 // TODO: implement the "initial exec"model for pic executables
7353 // If GV is an alias then use the aliasee for determining
7354 // thread-localness.
7355 if (const GlobalAlias *GA = dyn_cast<GlobalAlias>(GV))
7356 GV = GA->resolveAliasedGlobal(false);
7358 TLSModel::Model model
7359 = getTLSModel(GV, getTargetMachine().getRelocationModel());
7362 case TLSModel::GeneralDynamic:
7363 case TLSModel::LocalDynamic: // not implemented
7364 if (Subtarget->is64Bit())
7365 return LowerToTLSGeneralDynamicModel64(GA, DAG, getPointerTy());
7366 return LowerToTLSGeneralDynamicModel32(GA, DAG, getPointerTy());
7368 case TLSModel::InitialExec:
7369 case TLSModel::LocalExec:
7370 return LowerToTLSExecModel(GA, DAG, getPointerTy(), model,
7371 Subtarget->is64Bit());
7373 } else if (Subtarget->isTargetDarwin()) {
7374 // Darwin only has one model of TLS. Lower to that.
7375 unsigned char OpFlag = 0;
7376 unsigned WrapperKind = Subtarget->isPICStyleRIPRel() ?
7377 X86ISD::WrapperRIP : X86ISD::Wrapper;
7379 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
7381 bool PIC32 = (getTargetMachine().getRelocationModel() == Reloc::PIC_) &&
7382 !Subtarget->is64Bit();
7384 OpFlag = X86II::MO_TLVP_PIC_BASE;
7386 OpFlag = X86II::MO_TLVP;
7387 DebugLoc DL = Op.getDebugLoc();
7388 SDValue Result = DAG.getTargetGlobalAddress(GA->getGlobal(), DL,
7389 GA->getValueType(0),
7390 GA->getOffset(), OpFlag);
7391 SDValue Offset = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
7393 // With PIC32, the address is actually $g + Offset.
7395 Offset = DAG.getNode(ISD::ADD, DL, getPointerTy(),
7396 DAG.getNode(X86ISD::GlobalBaseReg,
7397 DebugLoc(), getPointerTy()),
7400 // Lowering the machine isd will make sure everything is in the right
7402 SDValue Chain = DAG.getEntryNode();
7403 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
7404 SDValue Args[] = { Chain, Offset };
7405 Chain = DAG.getNode(X86ISD::TLSCALL, DL, NodeTys, Args, 2);
7407 // TLSCALL will be codegen'ed as call. Inform MFI that function has calls.
7408 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
7409 MFI->setAdjustsStack(true);
7411 // And our return value (tls address) is in the standard call return value
7413 unsigned Reg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
7414 return DAG.getCopyFromReg(Chain, DL, Reg, getPointerTy(),
7419 "TLS not implemented for this target.");
7421 llvm_unreachable("Unreachable");
7426 /// LowerShiftParts - Lower SRA_PARTS and friends, which return two i32 values
7427 /// and take a 2 x i32 value to shift plus a shift amount.
7428 SDValue X86TargetLowering::LowerShiftParts(SDValue Op, SelectionDAG &DAG) const{
7429 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
7430 EVT VT = Op.getValueType();
7431 unsigned VTBits = VT.getSizeInBits();
7432 DebugLoc dl = Op.getDebugLoc();
7433 bool isSRA = Op.getOpcode() == ISD::SRA_PARTS;
7434 SDValue ShOpLo = Op.getOperand(0);
7435 SDValue ShOpHi = Op.getOperand(1);
7436 SDValue ShAmt = Op.getOperand(2);
7437 SDValue Tmp1 = isSRA ? DAG.getNode(ISD::SRA, dl, VT, ShOpHi,
7438 DAG.getConstant(VTBits - 1, MVT::i8))
7439 : DAG.getConstant(0, VT);
7442 if (Op.getOpcode() == ISD::SHL_PARTS) {
7443 Tmp2 = DAG.getNode(X86ISD::SHLD, dl, VT, ShOpHi, ShOpLo, ShAmt);
7444 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ShAmt);
7446 Tmp2 = DAG.getNode(X86ISD::SHRD, dl, VT, ShOpLo, ShOpHi, ShAmt);
7447 Tmp3 = DAG.getNode(isSRA ? ISD::SRA : ISD::SRL, dl, VT, ShOpHi, ShAmt);
7450 SDValue AndNode = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt,
7451 DAG.getConstant(VTBits, MVT::i8));
7452 SDValue Cond = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
7453 AndNode, DAG.getConstant(0, MVT::i8));
7456 SDValue CC = DAG.getConstant(X86::COND_NE, MVT::i8);
7457 SDValue Ops0[4] = { Tmp2, Tmp3, CC, Cond };
7458 SDValue Ops1[4] = { Tmp3, Tmp1, CC, Cond };
7460 if (Op.getOpcode() == ISD::SHL_PARTS) {
7461 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0, 4);
7462 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1, 4);
7464 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0, 4);
7465 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1, 4);
7468 SDValue Ops[2] = { Lo, Hi };
7469 return DAG.getMergeValues(Ops, 2, dl);
7472 SDValue X86TargetLowering::LowerSINT_TO_FP(SDValue Op,
7473 SelectionDAG &DAG) const {
7474 EVT SrcVT = Op.getOperand(0).getValueType();
7476 if (SrcVT.isVector())
7479 assert(SrcVT.getSimpleVT() <= MVT::i64 && SrcVT.getSimpleVT() >= MVT::i16 &&
7480 "Unknown SINT_TO_FP to lower!");
7482 // These are really Legal; return the operand so the caller accepts it as
7484 if (SrcVT == MVT::i32 && isScalarFPTypeInSSEReg(Op.getValueType()))
7486 if (SrcVT == MVT::i64 && isScalarFPTypeInSSEReg(Op.getValueType()) &&
7487 Subtarget->is64Bit()) {
7491 DebugLoc dl = Op.getDebugLoc();
7492 unsigned Size = SrcVT.getSizeInBits()/8;
7493 MachineFunction &MF = DAG.getMachineFunction();
7494 int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size, false);
7495 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
7496 SDValue Chain = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
7498 MachinePointerInfo::getFixedStack(SSFI),
7500 return BuildFILD(Op, SrcVT, Chain, StackSlot, DAG);
7503 SDValue X86TargetLowering::BuildFILD(SDValue Op, EVT SrcVT, SDValue Chain,
7505 SelectionDAG &DAG) const {
7507 DebugLoc DL = Op.getDebugLoc();
7509 bool useSSE = isScalarFPTypeInSSEReg(Op.getValueType());
7511 Tys = DAG.getVTList(MVT::f64, MVT::Other, MVT::Glue);
7513 Tys = DAG.getVTList(Op.getValueType(), MVT::Other);
7515 unsigned ByteSize = SrcVT.getSizeInBits()/8;
7517 FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(StackSlot);
7518 MachineMemOperand *MMO;
7520 int SSFI = FI->getIndex();
7522 DAG.getMachineFunction()
7523 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
7524 MachineMemOperand::MOLoad, ByteSize, ByteSize);
7526 MMO = cast<LoadSDNode>(StackSlot)->getMemOperand();
7527 StackSlot = StackSlot.getOperand(1);
7529 SDValue Ops[] = { Chain, StackSlot, DAG.getValueType(SrcVT) };
7530 SDValue Result = DAG.getMemIntrinsicNode(useSSE ? X86ISD::FILD_FLAG :
7532 Tys, Ops, array_lengthof(Ops),
7536 Chain = Result.getValue(1);
7537 SDValue InFlag = Result.getValue(2);
7539 // FIXME: Currently the FST is flagged to the FILD_FLAG. This
7540 // shouldn't be necessary except that RFP cannot be live across
7541 // multiple blocks. When stackifier is fixed, they can be uncoupled.
7542 MachineFunction &MF = DAG.getMachineFunction();
7543 unsigned SSFISize = Op.getValueType().getSizeInBits()/8;
7544 int SSFI = MF.getFrameInfo()->CreateStackObject(SSFISize, SSFISize, false);
7545 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
7546 Tys = DAG.getVTList(MVT::Other);
7548 Chain, Result, StackSlot, DAG.getValueType(Op.getValueType()), InFlag
7550 MachineMemOperand *MMO =
7551 DAG.getMachineFunction()
7552 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
7553 MachineMemOperand::MOStore, SSFISize, SSFISize);
7555 Chain = DAG.getMemIntrinsicNode(X86ISD::FST, DL, Tys,
7556 Ops, array_lengthof(Ops),
7557 Op.getValueType(), MMO);
7558 Result = DAG.getLoad(Op.getValueType(), DL, Chain, StackSlot,
7559 MachinePointerInfo::getFixedStack(SSFI),
7560 false, false, false, 0);
7566 // LowerUINT_TO_FP_i64 - 64-bit unsigned integer to double expansion.
7567 SDValue X86TargetLowering::LowerUINT_TO_FP_i64(SDValue Op,
7568 SelectionDAG &DAG) const {
7569 // This algorithm is not obvious. Here it is what we're trying to output:
7572 punpckldq (c0), %xmm0 // c0: (uint4){ 0x43300000U, 0x45300000U, 0U, 0U }
7573 subpd (c1), %xmm0 // c1: (double2){ 0x1.0p52, 0x1.0p52 * 0x1.0p32 }
7577 pshufd $0x4e, %xmm0, %xmm1
7582 DebugLoc dl = Op.getDebugLoc();
7583 LLVMContext *Context = DAG.getContext();
7585 // Build some magic constants.
7586 SmallVector<Constant*,4> CV0;
7587 CV0.push_back(ConstantInt::get(*Context, APInt(32, 0x43300000)));
7588 CV0.push_back(ConstantInt::get(*Context, APInt(32, 0x45300000)));
7589 CV0.push_back(ConstantInt::get(*Context, APInt(32, 0)));
7590 CV0.push_back(ConstantInt::get(*Context, APInt(32, 0)));
7591 Constant *C0 = ConstantVector::get(CV0);
7592 SDValue CPIdx0 = DAG.getConstantPool(C0, getPointerTy(), 16);
7594 SmallVector<Constant*,2> CV1;
7596 ConstantFP::get(*Context, APFloat(APInt(64, 0x4330000000000000ULL))));
7598 ConstantFP::get(*Context, APFloat(APInt(64, 0x4530000000000000ULL))));
7599 Constant *C1 = ConstantVector::get(CV1);
7600 SDValue CPIdx1 = DAG.getConstantPool(C1, getPointerTy(), 16);
7602 // Load the 64-bit value into an XMM register.
7603 SDValue XR1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
7605 SDValue CLod0 = DAG.getLoad(MVT::v4i32, dl, DAG.getEntryNode(), CPIdx0,
7606 MachinePointerInfo::getConstantPool(),
7607 false, false, false, 16);
7608 SDValue Unpck1 = getUnpackl(DAG, dl, MVT::v4i32,
7609 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, XR1),
7612 SDValue CLod1 = DAG.getLoad(MVT::v2f64, dl, CLod0.getValue(1), CPIdx1,
7613 MachinePointerInfo::getConstantPool(),
7614 false, false, false, 16);
7615 SDValue XR2F = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Unpck1);
7616 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, XR2F, CLod1);
7619 if (Subtarget->hasSSE3()) {
7620 // FIXME: The 'haddpd' instruction may be slower than 'movhlps + addsd'.
7621 Result = DAG.getNode(X86ISD::FHADD, dl, MVT::v2f64, Sub, Sub);
7623 SDValue S2F = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Sub);
7624 SDValue Shuffle = getTargetShuffleNode(X86ISD::PSHUFD, dl, MVT::v4i32,
7626 Result = DAG.getNode(ISD::FADD, dl, MVT::v2f64,
7627 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Shuffle),
7631 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Result,
7632 DAG.getIntPtrConstant(0));
7635 // LowerUINT_TO_FP_i32 - 32-bit unsigned integer to float expansion.
7636 SDValue X86TargetLowering::LowerUINT_TO_FP_i32(SDValue Op,
7637 SelectionDAG &DAG) const {
7638 DebugLoc dl = Op.getDebugLoc();
7639 // FP constant to bias correct the final result.
7640 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL),
7643 // Load the 32-bit value into an XMM register.
7644 SDValue Load = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,
7647 // Zero out the upper parts of the register.
7648 Load = getShuffleVectorZeroOrUndef(Load, 0, true, Subtarget, DAG);
7650 Load = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
7651 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Load),
7652 DAG.getIntPtrConstant(0));
7654 // Or the load with the bias.
7655 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64,
7656 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
7657 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
7659 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
7660 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
7661 MVT::v2f64, Bias)));
7662 Or = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
7663 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Or),
7664 DAG.getIntPtrConstant(0));
7666 // Subtract the bias.
7667 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Or, Bias);
7669 // Handle final rounding.
7670 EVT DestVT = Op.getValueType();
7672 if (DestVT.bitsLT(MVT::f64)) {
7673 return DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub,
7674 DAG.getIntPtrConstant(0));
7675 } else if (DestVT.bitsGT(MVT::f64)) {
7676 return DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub);
7679 // Handle final rounding.
7683 SDValue X86TargetLowering::LowerUINT_TO_FP(SDValue Op,
7684 SelectionDAG &DAG) const {
7685 SDValue N0 = Op.getOperand(0);
7686 DebugLoc dl = Op.getDebugLoc();
7688 // Since UINT_TO_FP is legal (it's marked custom), dag combiner won't
7689 // optimize it to a SINT_TO_FP when the sign bit is known zero. Perform
7690 // the optimization here.
7691 if (DAG.SignBitIsZero(N0))
7692 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(), N0);
7694 EVT SrcVT = N0.getValueType();
7695 EVT DstVT = Op.getValueType();
7696 if (SrcVT == MVT::i64 && DstVT == MVT::f64 && X86ScalarSSEf64)
7697 return LowerUINT_TO_FP_i64(Op, DAG);
7698 else if (SrcVT == MVT::i32 && X86ScalarSSEf64)
7699 return LowerUINT_TO_FP_i32(Op, DAG);
7700 else if (Subtarget->is64Bit() &&
7701 SrcVT == MVT::i64 && DstVT == MVT::f32)
7704 // Make a 64-bit buffer, and use it to build an FILD.
7705 SDValue StackSlot = DAG.CreateStackTemporary(MVT::i64);
7706 if (SrcVT == MVT::i32) {
7707 SDValue WordOff = DAG.getConstant(4, getPointerTy());
7708 SDValue OffsetSlot = DAG.getNode(ISD::ADD, dl,
7709 getPointerTy(), StackSlot, WordOff);
7710 SDValue Store1 = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
7711 StackSlot, MachinePointerInfo(),
7713 SDValue Store2 = DAG.getStore(Store1, dl, DAG.getConstant(0, MVT::i32),
7714 OffsetSlot, MachinePointerInfo(),
7716 SDValue Fild = BuildFILD(Op, MVT::i64, Store2, StackSlot, DAG);
7720 assert(SrcVT == MVT::i64 && "Unexpected type in UINT_TO_FP");
7721 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
7722 StackSlot, MachinePointerInfo(),
7724 // For i64 source, we need to add the appropriate power of 2 if the input
7725 // was negative. This is the same as the optimization in
7726 // DAGTypeLegalizer::ExpandIntOp_UNIT_TO_FP, and for it to be safe here,
7727 // we must be careful to do the computation in x87 extended precision, not
7728 // in SSE. (The generic code can't know it's OK to do this, or how to.)
7729 int SSFI = cast<FrameIndexSDNode>(StackSlot)->getIndex();
7730 MachineMemOperand *MMO =
7731 DAG.getMachineFunction()
7732 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
7733 MachineMemOperand::MOLoad, 8, 8);
7735 SDVTList Tys = DAG.getVTList(MVT::f80, MVT::Other);
7736 SDValue Ops[] = { Store, StackSlot, DAG.getValueType(MVT::i64) };
7737 SDValue Fild = DAG.getMemIntrinsicNode(X86ISD::FILD, dl, Tys, Ops, 3,
7740 APInt FF(32, 0x5F800000ULL);
7742 // Check whether the sign bit is set.
7743 SDValue SignSet = DAG.getSetCC(dl, getSetCCResultType(MVT::i64),
7744 Op.getOperand(0), DAG.getConstant(0, MVT::i64),
7747 // Build a 64 bit pair (0, FF) in the constant pool, with FF in the lo bits.
7748 SDValue FudgePtr = DAG.getConstantPool(
7749 ConstantInt::get(*DAG.getContext(), FF.zext(64)),
7752 // Get a pointer to FF if the sign bit was set, or to 0 otherwise.
7753 SDValue Zero = DAG.getIntPtrConstant(0);
7754 SDValue Four = DAG.getIntPtrConstant(4);
7755 SDValue Offset = DAG.getNode(ISD::SELECT, dl, Zero.getValueType(), SignSet,
7757 FudgePtr = DAG.getNode(ISD::ADD, dl, getPointerTy(), FudgePtr, Offset);
7759 // Load the value out, extending it from f32 to f80.
7760 // FIXME: Avoid the extend by constructing the right constant pool?
7761 SDValue Fudge = DAG.getExtLoad(ISD::EXTLOAD, dl, MVT::f80, DAG.getEntryNode(),
7762 FudgePtr, MachinePointerInfo::getConstantPool(),
7763 MVT::f32, false, false, 4);
7764 // Extend everything to 80 bits to force it to be done on x87.
7765 SDValue Add = DAG.getNode(ISD::FADD, dl, MVT::f80, Fild, Fudge);
7766 return DAG.getNode(ISD::FP_ROUND, dl, DstVT, Add, DAG.getIntPtrConstant(0));
7769 std::pair<SDValue,SDValue> X86TargetLowering::
7770 FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG, bool IsSigned) const {
7771 DebugLoc DL = Op.getDebugLoc();
7773 EVT DstTy = Op.getValueType();
7776 assert(DstTy == MVT::i32 && "Unexpected FP_TO_UINT");
7780 assert(DstTy.getSimpleVT() <= MVT::i64 &&
7781 DstTy.getSimpleVT() >= MVT::i16 &&
7782 "Unknown FP_TO_SINT to lower!");
7784 // These are really Legal.
7785 if (DstTy == MVT::i32 &&
7786 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
7787 return std::make_pair(SDValue(), SDValue());
7788 if (Subtarget->is64Bit() &&
7789 DstTy == MVT::i64 &&
7790 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
7791 return std::make_pair(SDValue(), SDValue());
7793 // We lower FP->sint64 into FISTP64, followed by a load, all to a temporary
7795 MachineFunction &MF = DAG.getMachineFunction();
7796 unsigned MemSize = DstTy.getSizeInBits()/8;
7797 int SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
7798 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
7803 switch (DstTy.getSimpleVT().SimpleTy) {
7804 default: llvm_unreachable("Invalid FP_TO_SINT to lower!");
7805 case MVT::i16: Opc = X86ISD::FP_TO_INT16_IN_MEM; break;
7806 case MVT::i32: Opc = X86ISD::FP_TO_INT32_IN_MEM; break;
7807 case MVT::i64: Opc = X86ISD::FP_TO_INT64_IN_MEM; break;
7810 SDValue Chain = DAG.getEntryNode();
7811 SDValue Value = Op.getOperand(0);
7812 EVT TheVT = Op.getOperand(0).getValueType();
7813 if (isScalarFPTypeInSSEReg(TheVT)) {
7814 assert(DstTy == MVT::i64 && "Invalid FP_TO_SINT to lower!");
7815 Chain = DAG.getStore(Chain, DL, Value, StackSlot,
7816 MachinePointerInfo::getFixedStack(SSFI),
7818 SDVTList Tys = DAG.getVTList(Op.getOperand(0).getValueType(), MVT::Other);
7820 Chain, StackSlot, DAG.getValueType(TheVT)
7823 MachineMemOperand *MMO =
7824 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
7825 MachineMemOperand::MOLoad, MemSize, MemSize);
7826 Value = DAG.getMemIntrinsicNode(X86ISD::FLD, DL, Tys, Ops, 3,
7828 Chain = Value.getValue(1);
7829 SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
7830 StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
7833 MachineMemOperand *MMO =
7834 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
7835 MachineMemOperand::MOStore, MemSize, MemSize);
7837 // Build the FP_TO_INT*_IN_MEM
7838 SDValue Ops[] = { Chain, Value, StackSlot };
7839 SDValue FIST = DAG.getMemIntrinsicNode(Opc, DL, DAG.getVTList(MVT::Other),
7840 Ops, 3, DstTy, MMO);
7842 return std::make_pair(FIST, StackSlot);
7845 SDValue X86TargetLowering::LowerFP_TO_SINT(SDValue Op,
7846 SelectionDAG &DAG) const {
7847 if (Op.getValueType().isVector())
7850 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG, true);
7851 SDValue FIST = Vals.first, StackSlot = Vals.second;
7852 // If FP_TO_INTHelper failed, the node is actually supposed to be Legal.
7853 if (FIST.getNode() == 0) return Op;
7856 return DAG.getLoad(Op.getValueType(), Op.getDebugLoc(),
7857 FIST, StackSlot, MachinePointerInfo(),
7858 false, false, false, 0);
7861 SDValue X86TargetLowering::LowerFP_TO_UINT(SDValue Op,
7862 SelectionDAG &DAG) const {
7863 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG, false);
7864 SDValue FIST = Vals.first, StackSlot = Vals.second;
7865 assert(FIST.getNode() && "Unexpected failure");
7868 return DAG.getLoad(Op.getValueType(), Op.getDebugLoc(),
7869 FIST, StackSlot, MachinePointerInfo(),
7870 false, false, false, 0);
7873 SDValue X86TargetLowering::LowerFABS(SDValue Op,
7874 SelectionDAG &DAG) const {
7875 LLVMContext *Context = DAG.getContext();
7876 DebugLoc dl = Op.getDebugLoc();
7877 EVT VT = Op.getValueType();
7880 EltVT = VT.getVectorElementType();
7881 SmallVector<Constant*,4> CV;
7882 if (EltVT == MVT::f64) {
7883 Constant *C = ConstantFP::get(*Context, APFloat(APInt(64, ~(1ULL << 63))));
7886 Constant *C = ConstantFP::get(*Context, APFloat(APInt(32, ~(1U << 31))));
7889 Constant *C = ConstantVector::get(CV);
7890 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
7891 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
7892 MachinePointerInfo::getConstantPool(),
7893 false, false, false, 16);
7894 return DAG.getNode(X86ISD::FAND, dl, VT, Op.getOperand(0), Mask);
7897 SDValue X86TargetLowering::LowerFNEG(SDValue Op, SelectionDAG &DAG) const {
7898 LLVMContext *Context = DAG.getContext();
7899 DebugLoc dl = Op.getDebugLoc();
7900 EVT VT = Op.getValueType();
7902 unsigned NumElts = VT == MVT::f64 ? 2 : 4;
7903 if (VT.isVector()) {
7904 EltVT = VT.getVectorElementType();
7905 NumElts = VT.getVectorNumElements();
7907 SmallVector<Constant*,8> CV;
7908 if (EltVT == MVT::f64) {
7909 Constant *C = ConstantFP::get(*Context, APFloat(APInt(64, 1ULL << 63)));
7910 CV.assign(NumElts, C);
7912 Constant *C = ConstantFP::get(*Context, APFloat(APInt(32, 1U << 31)));
7913 CV.assign(NumElts, C);
7915 Constant *C = ConstantVector::get(CV);
7916 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
7917 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
7918 MachinePointerInfo::getConstantPool(),
7919 false, false, false, 16);
7920 if (VT.isVector()) {
7921 MVT XORVT = VT.getSizeInBits() == 128 ? MVT::v2i64 : MVT::v4i64;
7922 return DAG.getNode(ISD::BITCAST, dl, VT,
7923 DAG.getNode(ISD::XOR, dl, XORVT,
7924 DAG.getNode(ISD::BITCAST, dl, XORVT,
7926 DAG.getNode(ISD::BITCAST, dl, XORVT, Mask)));
7928 return DAG.getNode(X86ISD::FXOR, dl, VT, Op.getOperand(0), Mask);
7932 SDValue X86TargetLowering::LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const {
7933 LLVMContext *Context = DAG.getContext();
7934 SDValue Op0 = Op.getOperand(0);
7935 SDValue Op1 = Op.getOperand(1);
7936 DebugLoc dl = Op.getDebugLoc();
7937 EVT VT = Op.getValueType();
7938 EVT SrcVT = Op1.getValueType();
7940 // If second operand is smaller, extend it first.
7941 if (SrcVT.bitsLT(VT)) {
7942 Op1 = DAG.getNode(ISD::FP_EXTEND, dl, VT, Op1);
7945 // And if it is bigger, shrink it first.
7946 if (SrcVT.bitsGT(VT)) {
7947 Op1 = DAG.getNode(ISD::FP_ROUND, dl, VT, Op1, DAG.getIntPtrConstant(1));
7951 // At this point the operands and the result should have the same
7952 // type, and that won't be f80 since that is not custom lowered.
7954 // First get the sign bit of second operand.
7955 SmallVector<Constant*,4> CV;
7956 if (SrcVT == MVT::f64) {
7957 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, 1ULL << 63))));
7958 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, 0))));
7960 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 1U << 31))));
7961 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
7962 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
7963 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
7965 Constant *C = ConstantVector::get(CV);
7966 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
7967 SDValue Mask1 = DAG.getLoad(SrcVT, dl, DAG.getEntryNode(), CPIdx,
7968 MachinePointerInfo::getConstantPool(),
7969 false, false, false, 16);
7970 SDValue SignBit = DAG.getNode(X86ISD::FAND, dl, SrcVT, Op1, Mask1);
7972 // Shift sign bit right or left if the two operands have different types.
7973 if (SrcVT.bitsGT(VT)) {
7974 // Op0 is MVT::f32, Op1 is MVT::f64.
7975 SignBit = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f64, SignBit);
7976 SignBit = DAG.getNode(X86ISD::FSRL, dl, MVT::v2f64, SignBit,
7977 DAG.getConstant(32, MVT::i32));
7978 SignBit = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, SignBit);
7979 SignBit = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f32, SignBit,
7980 DAG.getIntPtrConstant(0));
7983 // Clear first operand sign bit.
7985 if (VT == MVT::f64) {
7986 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, ~(1ULL << 63)))));
7987 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, 0))));
7989 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, ~(1U << 31)))));
7990 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
7991 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
7992 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
7994 C = ConstantVector::get(CV);
7995 CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
7996 SDValue Mask2 = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
7997 MachinePointerInfo::getConstantPool(),
7998 false, false, false, 16);
7999 SDValue Val = DAG.getNode(X86ISD::FAND, dl, VT, Op0, Mask2);
8001 // Or the value with the sign bit.
8002 return DAG.getNode(X86ISD::FOR, dl, VT, Val, SignBit);
8005 SDValue X86TargetLowering::LowerFGETSIGN(SDValue Op, SelectionDAG &DAG) const {
8006 SDValue N0 = Op.getOperand(0);
8007 DebugLoc dl = Op.getDebugLoc();
8008 EVT VT = Op.getValueType();
8010 // Lower ISD::FGETSIGN to (AND (X86ISD::FGETSIGNx86 ...) 1).
8011 SDValue xFGETSIGN = DAG.getNode(X86ISD::FGETSIGNx86, dl, VT, N0,
8012 DAG.getConstant(1, VT));
8013 return DAG.getNode(ISD::AND, dl, VT, xFGETSIGN, DAG.getConstant(1, VT));
8016 /// Emit nodes that will be selected as "test Op0,Op0", or something
8018 SDValue X86TargetLowering::EmitTest(SDValue Op, unsigned X86CC,
8019 SelectionDAG &DAG) const {
8020 DebugLoc dl = Op.getDebugLoc();
8022 // CF and OF aren't always set the way we want. Determine which
8023 // of these we need.
8024 bool NeedCF = false;
8025 bool NeedOF = false;
8028 case X86::COND_A: case X86::COND_AE:
8029 case X86::COND_B: case X86::COND_BE:
8032 case X86::COND_G: case X86::COND_GE:
8033 case X86::COND_L: case X86::COND_LE:
8034 case X86::COND_O: case X86::COND_NO:
8039 // See if we can use the EFLAGS value from the operand instead of
8040 // doing a separate TEST. TEST always sets OF and CF to 0, so unless
8041 // we prove that the arithmetic won't overflow, we can't use OF or CF.
8042 if (Op.getResNo() != 0 || NeedOF || NeedCF)
8043 // Emit a CMP with 0, which is the TEST pattern.
8044 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
8045 DAG.getConstant(0, Op.getValueType()));
8047 unsigned Opcode = 0;
8048 unsigned NumOperands = 0;
8049 switch (Op.getNode()->getOpcode()) {
8051 // Due to an isel shortcoming, be conservative if this add is likely to be
8052 // selected as part of a load-modify-store instruction. When the root node
8053 // in a match is a store, isel doesn't know how to remap non-chain non-flag
8054 // uses of other nodes in the match, such as the ADD in this case. This
8055 // leads to the ADD being left around and reselected, with the result being
8056 // two adds in the output. Alas, even if none our users are stores, that
8057 // doesn't prove we're O.K. Ergo, if we have any parents that aren't
8058 // CopyToReg or SETCC, eschew INC/DEC. A better fix seems to require
8059 // climbing the DAG back to the root, and it doesn't seem to be worth the
8061 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
8062 UE = Op.getNode()->use_end(); UI != UE; ++UI)
8063 if (UI->getOpcode() != ISD::CopyToReg &&
8064 UI->getOpcode() != ISD::SETCC &&
8065 UI->getOpcode() != ISD::STORE)
8068 if (ConstantSDNode *C =
8069 dyn_cast<ConstantSDNode>(Op.getNode()->getOperand(1))) {
8070 // An add of one will be selected as an INC.
8071 if (C->getAPIntValue() == 1) {
8072 Opcode = X86ISD::INC;
8077 // An add of negative one (subtract of one) will be selected as a DEC.
8078 if (C->getAPIntValue().isAllOnesValue()) {
8079 Opcode = X86ISD::DEC;
8085 // Otherwise use a regular EFLAGS-setting add.
8086 Opcode = X86ISD::ADD;
8090 // If the primary and result isn't used, don't bother using X86ISD::AND,
8091 // because a TEST instruction will be better.
8092 bool NonFlagUse = false;
8093 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
8094 UE = Op.getNode()->use_end(); UI != UE; ++UI) {
8096 unsigned UOpNo = UI.getOperandNo();
8097 if (User->getOpcode() == ISD::TRUNCATE && User->hasOneUse()) {
8098 // Look pass truncate.
8099 UOpNo = User->use_begin().getOperandNo();
8100 User = *User->use_begin();
8103 if (User->getOpcode() != ISD::BRCOND &&
8104 User->getOpcode() != ISD::SETCC &&
8105 (User->getOpcode() != ISD::SELECT || UOpNo != 0)) {
8118 // Due to the ISEL shortcoming noted above, be conservative if this op is
8119 // likely to be selected as part of a load-modify-store instruction.
8120 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
8121 UE = Op.getNode()->use_end(); UI != UE; ++UI)
8122 if (UI->getOpcode() == ISD::STORE)
8125 // Otherwise use a regular EFLAGS-setting instruction.
8126 switch (Op.getNode()->getOpcode()) {
8127 default: llvm_unreachable("unexpected operator!");
8128 case ISD::SUB: Opcode = X86ISD::SUB; break;
8129 case ISD::OR: Opcode = X86ISD::OR; break;
8130 case ISD::XOR: Opcode = X86ISD::XOR; break;
8131 case ISD::AND: Opcode = X86ISD::AND; break;
8143 return SDValue(Op.getNode(), 1);
8150 // Emit a CMP with 0, which is the TEST pattern.
8151 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
8152 DAG.getConstant(0, Op.getValueType()));
8154 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
8155 SmallVector<SDValue, 4> Ops;
8156 for (unsigned i = 0; i != NumOperands; ++i)
8157 Ops.push_back(Op.getOperand(i));
8159 SDValue New = DAG.getNode(Opcode, dl, VTs, &Ops[0], NumOperands);
8160 DAG.ReplaceAllUsesWith(Op, New);
8161 return SDValue(New.getNode(), 1);
8164 /// Emit nodes that will be selected as "cmp Op0,Op1", or something
8166 SDValue X86TargetLowering::EmitCmp(SDValue Op0, SDValue Op1, unsigned X86CC,
8167 SelectionDAG &DAG) const {
8168 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op1))
8169 if (C->getAPIntValue() == 0)
8170 return EmitTest(Op0, X86CC, DAG);
8172 DebugLoc dl = Op0.getDebugLoc();
8173 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op0, Op1);
8176 /// LowerToBT - Result of 'and' is compared against zero. Turn it into a BT node
8177 /// if it's possible.
8178 SDValue X86TargetLowering::LowerToBT(SDValue And, ISD::CondCode CC,
8179 DebugLoc dl, SelectionDAG &DAG) const {
8180 SDValue Op0 = And.getOperand(0);
8181 SDValue Op1 = And.getOperand(1);
8182 if (Op0.getOpcode() == ISD::TRUNCATE)
8183 Op0 = Op0.getOperand(0);
8184 if (Op1.getOpcode() == ISD::TRUNCATE)
8185 Op1 = Op1.getOperand(0);
8188 if (Op1.getOpcode() == ISD::SHL)
8189 std::swap(Op0, Op1);
8190 if (Op0.getOpcode() == ISD::SHL) {
8191 if (ConstantSDNode *And00C = dyn_cast<ConstantSDNode>(Op0.getOperand(0)))
8192 if (And00C->getZExtValue() == 1) {
8193 // If we looked past a truncate, check that it's only truncating away
8195 unsigned BitWidth = Op0.getValueSizeInBits();
8196 unsigned AndBitWidth = And.getValueSizeInBits();
8197 if (BitWidth > AndBitWidth) {
8198 APInt Mask = APInt::getAllOnesValue(BitWidth), Zeros, Ones;
8199 DAG.ComputeMaskedBits(Op0, Mask, Zeros, Ones);
8200 if (Zeros.countLeadingOnes() < BitWidth - AndBitWidth)
8204 RHS = Op0.getOperand(1);
8206 } else if (Op1.getOpcode() == ISD::Constant) {
8207 ConstantSDNode *AndRHS = cast<ConstantSDNode>(Op1);
8208 uint64_t AndRHSVal = AndRHS->getZExtValue();
8209 SDValue AndLHS = Op0;
8211 if (AndRHSVal == 1 && AndLHS.getOpcode() == ISD::SRL) {
8212 LHS = AndLHS.getOperand(0);
8213 RHS = AndLHS.getOperand(1);
8216 // Use BT if the immediate can't be encoded in a TEST instruction.
8217 if (!isUInt<32>(AndRHSVal) && isPowerOf2_64(AndRHSVal)) {
8219 RHS = DAG.getConstant(Log2_64_Ceil(AndRHSVal), LHS.getValueType());
8223 if (LHS.getNode()) {
8224 // If LHS is i8, promote it to i32 with any_extend. There is no i8 BT
8225 // instruction. Since the shift amount is in-range-or-undefined, we know
8226 // that doing a bittest on the i32 value is ok. We extend to i32 because
8227 // the encoding for the i16 version is larger than the i32 version.
8228 // Also promote i16 to i32 for performance / code size reason.
8229 if (LHS.getValueType() == MVT::i8 ||
8230 LHS.getValueType() == MVT::i16)
8231 LHS = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, LHS);
8233 // If the operand types disagree, extend the shift amount to match. Since
8234 // BT ignores high bits (like shifts) we can use anyextend.
8235 if (LHS.getValueType() != RHS.getValueType())
8236 RHS = DAG.getNode(ISD::ANY_EXTEND, dl, LHS.getValueType(), RHS);
8238 SDValue BT = DAG.getNode(X86ISD::BT, dl, MVT::i32, LHS, RHS);
8239 unsigned Cond = CC == ISD::SETEQ ? X86::COND_AE : X86::COND_B;
8240 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
8241 DAG.getConstant(Cond, MVT::i8), BT);
8247 SDValue X86TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
8249 if (Op.getValueType().isVector()) return LowerVSETCC(Op, DAG);
8251 assert(Op.getValueType() == MVT::i8 && "SetCC type must be 8-bit integer");
8252 SDValue Op0 = Op.getOperand(0);
8253 SDValue Op1 = Op.getOperand(1);
8254 DebugLoc dl = Op.getDebugLoc();
8255 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
8257 // Optimize to BT if possible.
8258 // Lower (X & (1 << N)) == 0 to BT(X, N).
8259 // Lower ((X >>u N) & 1) != 0 to BT(X, N).
8260 // Lower ((X >>s N) & 1) != 0 to BT(X, N).
8261 if (Op0.getOpcode() == ISD::AND && Op0.hasOneUse() &&
8262 Op1.getOpcode() == ISD::Constant &&
8263 cast<ConstantSDNode>(Op1)->isNullValue() &&
8264 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
8265 SDValue NewSetCC = LowerToBT(Op0, CC, dl, DAG);
8266 if (NewSetCC.getNode())
8270 // Look for X == 0, X == 1, X != 0, or X != 1. We can simplify some forms of
8272 if (Op1.getOpcode() == ISD::Constant &&
8273 (cast<ConstantSDNode>(Op1)->getZExtValue() == 1 ||
8274 cast<ConstantSDNode>(Op1)->isNullValue()) &&
8275 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
8277 // If the input is a setcc, then reuse the input setcc or use a new one with
8278 // the inverted condition.
8279 if (Op0.getOpcode() == X86ISD::SETCC) {
8280 X86::CondCode CCode = (X86::CondCode)Op0.getConstantOperandVal(0);
8281 bool Invert = (CC == ISD::SETNE) ^
8282 cast<ConstantSDNode>(Op1)->isNullValue();
8283 if (!Invert) return Op0;
8285 CCode = X86::GetOppositeBranchCondition(CCode);
8286 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
8287 DAG.getConstant(CCode, MVT::i8), Op0.getOperand(1));
8291 bool isFP = Op1.getValueType().isFloatingPoint();
8292 unsigned X86CC = TranslateX86CC(CC, isFP, Op0, Op1, DAG);
8293 if (X86CC == X86::COND_INVALID)
8296 SDValue EFLAGS = EmitCmp(Op0, Op1, X86CC, DAG);
8297 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
8298 DAG.getConstant(X86CC, MVT::i8), EFLAGS);
8301 // Lower256IntVSETCC - Break a VSETCC 256-bit integer VSETCC into two new 128
8302 // ones, and then concatenate the result back.
8303 static SDValue Lower256IntVSETCC(SDValue Op, SelectionDAG &DAG) {
8304 EVT VT = Op.getValueType();
8306 assert(VT.getSizeInBits() == 256 && Op.getOpcode() == ISD::SETCC &&
8307 "Unsupported value type for operation");
8309 int NumElems = VT.getVectorNumElements();
8310 DebugLoc dl = Op.getDebugLoc();
8311 SDValue CC = Op.getOperand(2);
8312 SDValue Idx0 = DAG.getConstant(0, MVT::i32);
8313 SDValue Idx1 = DAG.getConstant(NumElems/2, MVT::i32);
8315 // Extract the LHS vectors
8316 SDValue LHS = Op.getOperand(0);
8317 SDValue LHS1 = Extract128BitVector(LHS, Idx0, DAG, dl);
8318 SDValue LHS2 = Extract128BitVector(LHS, Idx1, DAG, dl);
8320 // Extract the RHS vectors
8321 SDValue RHS = Op.getOperand(1);
8322 SDValue RHS1 = Extract128BitVector(RHS, Idx0, DAG, dl);
8323 SDValue RHS2 = Extract128BitVector(RHS, Idx1, DAG, dl);
8325 // Issue the operation on the smaller types and concatenate the result back
8326 MVT EltVT = VT.getVectorElementType().getSimpleVT();
8327 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
8328 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
8329 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1, CC),
8330 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2, CC));
8334 SDValue X86TargetLowering::LowerVSETCC(SDValue Op, SelectionDAG &DAG) const {
8336 SDValue Op0 = Op.getOperand(0);
8337 SDValue Op1 = Op.getOperand(1);
8338 SDValue CC = Op.getOperand(2);
8339 EVT VT = Op.getValueType();
8340 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
8341 bool isFP = Op.getOperand(1).getValueType().isFloatingPoint();
8342 DebugLoc dl = Op.getDebugLoc();
8346 EVT EltVT = Op0.getValueType().getVectorElementType();
8347 assert(EltVT == MVT::f32 || EltVT == MVT::f64);
8349 unsigned Opc = EltVT == MVT::f32 ? X86ISD::CMPPS : X86ISD::CMPPD;
8352 // SSE Condition code mapping:
8361 switch (SetCCOpcode) {
8364 case ISD::SETEQ: SSECC = 0; break;
8366 case ISD::SETGT: Swap = true; // Fallthrough
8368 case ISD::SETOLT: SSECC = 1; break;
8370 case ISD::SETGE: Swap = true; // Fallthrough
8372 case ISD::SETOLE: SSECC = 2; break;
8373 case ISD::SETUO: SSECC = 3; break;
8375 case ISD::SETNE: SSECC = 4; break;
8376 case ISD::SETULE: Swap = true;
8377 case ISD::SETUGE: SSECC = 5; break;
8378 case ISD::SETULT: Swap = true;
8379 case ISD::SETUGT: SSECC = 6; break;
8380 case ISD::SETO: SSECC = 7; break;
8383 std::swap(Op0, Op1);
8385 // In the two special cases we can't handle, emit two comparisons.
8387 if (SetCCOpcode == ISD::SETUEQ) {
8389 UNORD = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(3, MVT::i8));
8390 EQ = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(0, MVT::i8));
8391 return DAG.getNode(ISD::OR, dl, VT, UNORD, EQ);
8392 } else if (SetCCOpcode == ISD::SETONE) {
8394 ORD = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(7, MVT::i8));
8395 NEQ = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(4, MVT::i8));
8396 return DAG.getNode(ISD::AND, dl, VT, ORD, NEQ);
8398 llvm_unreachable("Illegal FP comparison");
8400 // Handle all other FP comparisons here.
8401 return DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(SSECC, MVT::i8));
8404 // Break 256-bit integer vector compare into smaller ones.
8405 if (VT.getSizeInBits() == 256 && !Subtarget->hasAVX2())
8406 return Lower256IntVSETCC(Op, DAG);
8408 // We are handling one of the integer comparisons here. Since SSE only has
8409 // GT and EQ comparisons for integer, swapping operands and multiple
8410 // operations may be required for some comparisons.
8411 unsigned Opc = 0, EQOpc = 0, GTOpc = 0;
8412 bool Swap = false, Invert = false, FlipSigns = false;
8414 switch (VT.getVectorElementType().getSimpleVT().SimpleTy) {
8416 case MVT::i8: EQOpc = X86ISD::PCMPEQB; GTOpc = X86ISD::PCMPGTB; break;
8417 case MVT::i16: EQOpc = X86ISD::PCMPEQW; GTOpc = X86ISD::PCMPGTW; break;
8418 case MVT::i32: EQOpc = X86ISD::PCMPEQD; GTOpc = X86ISD::PCMPGTD; break;
8419 case MVT::i64: EQOpc = X86ISD::PCMPEQQ; GTOpc = X86ISD::PCMPGTQ; break;
8422 switch (SetCCOpcode) {
8424 case ISD::SETNE: Invert = true;
8425 case ISD::SETEQ: Opc = EQOpc; break;
8426 case ISD::SETLT: Swap = true;
8427 case ISD::SETGT: Opc = GTOpc; break;
8428 case ISD::SETGE: Swap = true;
8429 case ISD::SETLE: Opc = GTOpc; Invert = true; break;
8430 case ISD::SETULT: Swap = true;
8431 case ISD::SETUGT: Opc = GTOpc; FlipSigns = true; break;
8432 case ISD::SETUGE: Swap = true;
8433 case ISD::SETULE: Opc = GTOpc; FlipSigns = true; Invert = true; break;
8436 std::swap(Op0, Op1);
8438 // Check that the operation in question is available (most are plain SSE2,
8439 // but PCMPGTQ and PCMPEQQ have different requirements).
8440 if (Opc == X86ISD::PCMPGTQ && !Subtarget->hasSSE42())
8442 if (Opc == X86ISD::PCMPEQQ && !Subtarget->hasSSE41())
8445 // Since SSE has no unsigned integer comparisons, we need to flip the sign
8446 // bits of the inputs before performing those operations.
8448 EVT EltVT = VT.getVectorElementType();
8449 SDValue SignBit = DAG.getConstant(APInt::getSignBit(EltVT.getSizeInBits()),
8451 std::vector<SDValue> SignBits(VT.getVectorNumElements(), SignBit);
8452 SDValue SignVec = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &SignBits[0],
8454 Op0 = DAG.getNode(ISD::XOR, dl, VT, Op0, SignVec);
8455 Op1 = DAG.getNode(ISD::XOR, dl, VT, Op1, SignVec);
8458 SDValue Result = DAG.getNode(Opc, dl, VT, Op0, Op1);
8460 // If the logical-not of the result is required, perform that now.
8462 Result = DAG.getNOT(dl, Result, VT);
8467 // isX86LogicalCmp - Return true if opcode is a X86 logical comparison.
8468 static bool isX86LogicalCmp(SDValue Op) {
8469 unsigned Opc = Op.getNode()->getOpcode();
8470 if (Opc == X86ISD::CMP || Opc == X86ISD::COMI || Opc == X86ISD::UCOMI)
8472 if (Op.getResNo() == 1 &&
8473 (Opc == X86ISD::ADD ||
8474 Opc == X86ISD::SUB ||
8475 Opc == X86ISD::ADC ||
8476 Opc == X86ISD::SBB ||
8477 Opc == X86ISD::SMUL ||
8478 Opc == X86ISD::UMUL ||
8479 Opc == X86ISD::INC ||
8480 Opc == X86ISD::DEC ||
8481 Opc == X86ISD::OR ||
8482 Opc == X86ISD::XOR ||
8483 Opc == X86ISD::AND))
8486 if (Op.getResNo() == 2 && Opc == X86ISD::UMUL)
8492 static bool isZero(SDValue V) {
8493 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V);
8494 return C && C->isNullValue();
8497 static bool isAllOnes(SDValue V) {
8498 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V);
8499 return C && C->isAllOnesValue();
8502 SDValue X86TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {
8503 bool addTest = true;
8504 SDValue Cond = Op.getOperand(0);
8505 SDValue Op1 = Op.getOperand(1);
8506 SDValue Op2 = Op.getOperand(2);
8507 DebugLoc DL = Op.getDebugLoc();
8510 if (Cond.getOpcode() == ISD::SETCC) {
8511 SDValue NewCond = LowerSETCC(Cond, DAG);
8512 if (NewCond.getNode())
8516 // (select (x == 0), -1, y) -> (sign_bit (x - 1)) | y
8517 // (select (x == 0), y, -1) -> ~(sign_bit (x - 1)) | y
8518 // (select (x != 0), y, -1) -> (sign_bit (x - 1)) | y
8519 // (select (x != 0), -1, y) -> ~(sign_bit (x - 1)) | y
8520 if (Cond.getOpcode() == X86ISD::SETCC &&
8521 Cond.getOperand(1).getOpcode() == X86ISD::CMP &&
8522 isZero(Cond.getOperand(1).getOperand(1))) {
8523 SDValue Cmp = Cond.getOperand(1);
8525 unsigned CondCode =cast<ConstantSDNode>(Cond.getOperand(0))->getZExtValue();
8527 if ((isAllOnes(Op1) || isAllOnes(Op2)) &&
8528 (CondCode == X86::COND_E || CondCode == X86::COND_NE)) {
8529 SDValue Y = isAllOnes(Op2) ? Op1 : Op2;
8531 SDValue CmpOp0 = Cmp.getOperand(0);
8532 Cmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32,
8533 CmpOp0, DAG.getConstant(1, CmpOp0.getValueType()));
8535 SDValue Res = // Res = 0 or -1.
8536 DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
8537 DAG.getConstant(X86::COND_B, MVT::i8), Cmp);
8539 if (isAllOnes(Op1) != (CondCode == X86::COND_E))
8540 Res = DAG.getNOT(DL, Res, Res.getValueType());
8542 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(Op2);
8543 if (N2C == 0 || !N2C->isNullValue())
8544 Res = DAG.getNode(ISD::OR, DL, Res.getValueType(), Res, Y);
8549 // Look past (and (setcc_carry (cmp ...)), 1).
8550 if (Cond.getOpcode() == ISD::AND &&
8551 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
8552 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
8553 if (C && C->getAPIntValue() == 1)
8554 Cond = Cond.getOperand(0);
8557 // If condition flag is set by a X86ISD::CMP, then use it as the condition
8558 // setting operand in place of the X86ISD::SETCC.
8559 unsigned CondOpcode = Cond.getOpcode();
8560 if (CondOpcode == X86ISD::SETCC ||
8561 CondOpcode == X86ISD::SETCC_CARRY) {
8562 CC = Cond.getOperand(0);
8564 SDValue Cmp = Cond.getOperand(1);
8565 unsigned Opc = Cmp.getOpcode();
8566 EVT VT = Op.getValueType();
8568 bool IllegalFPCMov = false;
8569 if (VT.isFloatingPoint() && !VT.isVector() &&
8570 !isScalarFPTypeInSSEReg(VT)) // FPStack?
8571 IllegalFPCMov = !hasFPCMov(cast<ConstantSDNode>(CC)->getSExtValue());
8573 if ((isX86LogicalCmp(Cmp) && !IllegalFPCMov) ||
8574 Opc == X86ISD::BT) { // FIXME
8578 } else if (CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO ||
8579 CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO ||
8580 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) &&
8581 Cond.getOperand(0).getValueType() != MVT::i8)) {
8582 SDValue LHS = Cond.getOperand(0);
8583 SDValue RHS = Cond.getOperand(1);
8587 switch (CondOpcode) {
8588 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break;
8589 case ISD::SADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break;
8590 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break;
8591 case ISD::SSUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break;
8592 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break;
8593 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break;
8594 default: llvm_unreachable("unexpected overflowing operator");
8596 if (CondOpcode == ISD::UMULO)
8597 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(),
8600 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
8602 SDValue X86Op = DAG.getNode(X86Opcode, DL, VTs, LHS, RHS);
8604 if (CondOpcode == ISD::UMULO)
8605 Cond = X86Op.getValue(2);
8607 Cond = X86Op.getValue(1);
8609 CC = DAG.getConstant(X86Cond, MVT::i8);
8614 // Look pass the truncate.
8615 if (Cond.getOpcode() == ISD::TRUNCATE)
8616 Cond = Cond.getOperand(0);
8618 // We know the result of AND is compared against zero. Try to match
8620 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
8621 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, DL, DAG);
8622 if (NewSetCC.getNode()) {
8623 CC = NewSetCC.getOperand(0);
8624 Cond = NewSetCC.getOperand(1);
8631 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
8632 Cond = EmitTest(Cond, X86::COND_NE, DAG);
8635 // a < b ? -1 : 0 -> RES = ~setcc_carry
8636 // a < b ? 0 : -1 -> RES = setcc_carry
8637 // a >= b ? -1 : 0 -> RES = setcc_carry
8638 // a >= b ? 0 : -1 -> RES = ~setcc_carry
8639 if (Cond.getOpcode() == X86ISD::CMP) {
8640 unsigned CondCode = cast<ConstantSDNode>(CC)->getZExtValue();
8642 if ((CondCode == X86::COND_AE || CondCode == X86::COND_B) &&
8643 (isAllOnes(Op1) || isAllOnes(Op2)) && (isZero(Op1) || isZero(Op2))) {
8644 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
8645 DAG.getConstant(X86::COND_B, MVT::i8), Cond);
8646 if (isAllOnes(Op1) != (CondCode == X86::COND_B))
8647 return DAG.getNOT(DL, Res, Res.getValueType());
8652 // X86ISD::CMOV means set the result (which is operand 1) to the RHS if
8653 // condition is true.
8654 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue);
8655 SDValue Ops[] = { Op2, Op1, CC, Cond };
8656 return DAG.getNode(X86ISD::CMOV, DL, VTs, Ops, array_lengthof(Ops));
8659 // isAndOrOfSingleUseSetCCs - Return true if node is an ISD::AND or
8660 // ISD::OR of two X86ISD::SETCC nodes each of which has no other use apart
8661 // from the AND / OR.
8662 static bool isAndOrOfSetCCs(SDValue Op, unsigned &Opc) {
8663 Opc = Op.getOpcode();
8664 if (Opc != ISD::OR && Opc != ISD::AND)
8666 return (Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
8667 Op.getOperand(0).hasOneUse() &&
8668 Op.getOperand(1).getOpcode() == X86ISD::SETCC &&
8669 Op.getOperand(1).hasOneUse());
8672 // isXor1OfSetCC - Return true if node is an ISD::XOR of a X86ISD::SETCC and
8673 // 1 and that the SETCC node has a single use.
8674 static bool isXor1OfSetCC(SDValue Op) {
8675 if (Op.getOpcode() != ISD::XOR)
8677 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
8678 if (N1C && N1C->getAPIntValue() == 1) {
8679 return Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
8680 Op.getOperand(0).hasOneUse();
8685 SDValue X86TargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) const {
8686 bool addTest = true;
8687 SDValue Chain = Op.getOperand(0);
8688 SDValue Cond = Op.getOperand(1);
8689 SDValue Dest = Op.getOperand(2);
8690 DebugLoc dl = Op.getDebugLoc();
8692 bool Inverted = false;
8694 if (Cond.getOpcode() == ISD::SETCC) {
8695 // Check for setcc([su]{add,sub,mul}o == 0).
8696 if (cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETEQ &&
8697 isa<ConstantSDNode>(Cond.getOperand(1)) &&
8698 cast<ConstantSDNode>(Cond.getOperand(1))->isNullValue() &&
8699 Cond.getOperand(0).getResNo() == 1 &&
8700 (Cond.getOperand(0).getOpcode() == ISD::SADDO ||
8701 Cond.getOperand(0).getOpcode() == ISD::UADDO ||
8702 Cond.getOperand(0).getOpcode() == ISD::SSUBO ||
8703 Cond.getOperand(0).getOpcode() == ISD::USUBO ||
8704 Cond.getOperand(0).getOpcode() == ISD::SMULO ||
8705 Cond.getOperand(0).getOpcode() == ISD::UMULO)) {
8707 Cond = Cond.getOperand(0);
8709 SDValue NewCond = LowerSETCC(Cond, DAG);
8710 if (NewCond.getNode())
8715 // FIXME: LowerXALUO doesn't handle these!!
8716 else if (Cond.getOpcode() == X86ISD::ADD ||
8717 Cond.getOpcode() == X86ISD::SUB ||
8718 Cond.getOpcode() == X86ISD::SMUL ||
8719 Cond.getOpcode() == X86ISD::UMUL)
8720 Cond = LowerXALUO(Cond, DAG);
8723 // Look pass (and (setcc_carry (cmp ...)), 1).
8724 if (Cond.getOpcode() == ISD::AND &&
8725 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
8726 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
8727 if (C && C->getAPIntValue() == 1)
8728 Cond = Cond.getOperand(0);
8731 // If condition flag is set by a X86ISD::CMP, then use it as the condition
8732 // setting operand in place of the X86ISD::SETCC.
8733 unsigned CondOpcode = Cond.getOpcode();
8734 if (CondOpcode == X86ISD::SETCC ||
8735 CondOpcode == X86ISD::SETCC_CARRY) {
8736 CC = Cond.getOperand(0);
8738 SDValue Cmp = Cond.getOperand(1);
8739 unsigned Opc = Cmp.getOpcode();
8740 // FIXME: WHY THE SPECIAL CASING OF LogicalCmp??
8741 if (isX86LogicalCmp(Cmp) || Opc == X86ISD::BT) {
8745 switch (cast<ConstantSDNode>(CC)->getZExtValue()) {
8749 // These can only come from an arithmetic instruction with overflow,
8750 // e.g. SADDO, UADDO.
8751 Cond = Cond.getNode()->getOperand(1);
8757 CondOpcode = Cond.getOpcode();
8758 if (CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO ||
8759 CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO ||
8760 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) &&
8761 Cond.getOperand(0).getValueType() != MVT::i8)) {
8762 SDValue LHS = Cond.getOperand(0);
8763 SDValue RHS = Cond.getOperand(1);
8767 switch (CondOpcode) {
8768 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break;
8769 case ISD::SADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break;
8770 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break;
8771 case ISD::SSUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break;
8772 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break;
8773 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break;
8774 default: llvm_unreachable("unexpected overflowing operator");
8777 X86Cond = X86::GetOppositeBranchCondition((X86::CondCode)X86Cond);
8778 if (CondOpcode == ISD::UMULO)
8779 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(),
8782 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
8784 SDValue X86Op = DAG.getNode(X86Opcode, dl, VTs, LHS, RHS);
8786 if (CondOpcode == ISD::UMULO)
8787 Cond = X86Op.getValue(2);
8789 Cond = X86Op.getValue(1);
8791 CC = DAG.getConstant(X86Cond, MVT::i8);
8795 if (Cond.hasOneUse() && isAndOrOfSetCCs(Cond, CondOpc)) {
8796 SDValue Cmp = Cond.getOperand(0).getOperand(1);
8797 if (CondOpc == ISD::OR) {
8798 // Also, recognize the pattern generated by an FCMP_UNE. We can emit
8799 // two branches instead of an explicit OR instruction with a
8801 if (Cmp == Cond.getOperand(1).getOperand(1) &&
8802 isX86LogicalCmp(Cmp)) {
8803 CC = Cond.getOperand(0).getOperand(0);
8804 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
8805 Chain, Dest, CC, Cmp);
8806 CC = Cond.getOperand(1).getOperand(0);
8810 } else { // ISD::AND
8811 // Also, recognize the pattern generated by an FCMP_OEQ. We can emit
8812 // two branches instead of an explicit AND instruction with a
8813 // separate test. However, we only do this if this block doesn't
8814 // have a fall-through edge, because this requires an explicit
8815 // jmp when the condition is false.
8816 if (Cmp == Cond.getOperand(1).getOperand(1) &&
8817 isX86LogicalCmp(Cmp) &&
8818 Op.getNode()->hasOneUse()) {
8819 X86::CondCode CCode =
8820 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
8821 CCode = X86::GetOppositeBranchCondition(CCode);
8822 CC = DAG.getConstant(CCode, MVT::i8);
8823 SDNode *User = *Op.getNode()->use_begin();
8824 // Look for an unconditional branch following this conditional branch.
8825 // We need this because we need to reverse the successors in order
8826 // to implement FCMP_OEQ.
8827 if (User->getOpcode() == ISD::BR) {
8828 SDValue FalseBB = User->getOperand(1);
8830 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
8831 assert(NewBR == User);
8835 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
8836 Chain, Dest, CC, Cmp);
8837 X86::CondCode CCode =
8838 (X86::CondCode)Cond.getOperand(1).getConstantOperandVal(0);
8839 CCode = X86::GetOppositeBranchCondition(CCode);
8840 CC = DAG.getConstant(CCode, MVT::i8);
8846 } else if (Cond.hasOneUse() && isXor1OfSetCC(Cond)) {
8847 // Recognize for xorb (setcc), 1 patterns. The xor inverts the condition.
8848 // It should be transformed during dag combiner except when the condition
8849 // is set by a arithmetics with overflow node.
8850 X86::CondCode CCode =
8851 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
8852 CCode = X86::GetOppositeBranchCondition(CCode);
8853 CC = DAG.getConstant(CCode, MVT::i8);
8854 Cond = Cond.getOperand(0).getOperand(1);
8856 } else if (Cond.getOpcode() == ISD::SETCC &&
8857 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETOEQ) {
8858 // For FCMP_OEQ, we can emit
8859 // two branches instead of an explicit AND instruction with a
8860 // separate test. However, we only do this if this block doesn't
8861 // have a fall-through edge, because this requires an explicit
8862 // jmp when the condition is false.
8863 if (Op.getNode()->hasOneUse()) {
8864 SDNode *User = *Op.getNode()->use_begin();
8865 // Look for an unconditional branch following this conditional branch.
8866 // We need this because we need to reverse the successors in order
8867 // to implement FCMP_OEQ.
8868 if (User->getOpcode() == ISD::BR) {
8869 SDValue FalseBB = User->getOperand(1);
8871 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
8872 assert(NewBR == User);
8876 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
8877 Cond.getOperand(0), Cond.getOperand(1));
8878 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
8879 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
8880 Chain, Dest, CC, Cmp);
8881 CC = DAG.getConstant(X86::COND_P, MVT::i8);
8886 } else if (Cond.getOpcode() == ISD::SETCC &&
8887 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETUNE) {
8888 // For FCMP_UNE, we can emit
8889 // two branches instead of an explicit AND instruction with a
8890 // separate test. However, we only do this if this block doesn't
8891 // have a fall-through edge, because this requires an explicit
8892 // jmp when the condition is false.
8893 if (Op.getNode()->hasOneUse()) {
8894 SDNode *User = *Op.getNode()->use_begin();
8895 // Look for an unconditional branch following this conditional branch.
8896 // We need this because we need to reverse the successors in order
8897 // to implement FCMP_UNE.
8898 if (User->getOpcode() == ISD::BR) {
8899 SDValue FalseBB = User->getOperand(1);
8901 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
8902 assert(NewBR == User);
8905 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
8906 Cond.getOperand(0), Cond.getOperand(1));
8907 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
8908 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
8909 Chain, Dest, CC, Cmp);
8910 CC = DAG.getConstant(X86::COND_NP, MVT::i8);
8920 // Look pass the truncate.
8921 if (Cond.getOpcode() == ISD::TRUNCATE)
8922 Cond = Cond.getOperand(0);
8924 // We know the result of AND is compared against zero. Try to match
8926 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
8927 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, dl, DAG);
8928 if (NewSetCC.getNode()) {
8929 CC = NewSetCC.getOperand(0);
8930 Cond = NewSetCC.getOperand(1);
8937 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
8938 Cond = EmitTest(Cond, X86::COND_NE, DAG);
8940 return DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
8941 Chain, Dest, CC, Cond);
8945 // Lower dynamic stack allocation to _alloca call for Cygwin/Mingw targets.
8946 // Calls to _alloca is needed to probe the stack when allocating more than 4k
8947 // bytes in one go. Touching the stack at 4K increments is necessary to ensure
8948 // that the guard pages used by the OS virtual memory manager are allocated in
8949 // correct sequence.
8951 X86TargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
8952 SelectionDAG &DAG) const {
8953 assert((Subtarget->isTargetCygMing() || Subtarget->isTargetWindows() ||
8954 getTargetMachine().Options.EnableSegmentedStacks) &&
8955 "This should be used only on Windows targets or when segmented stacks "
8957 assert(!Subtarget->isTargetEnvMacho() && "Not implemented");
8958 DebugLoc dl = Op.getDebugLoc();
8961 SDValue Chain = Op.getOperand(0);
8962 SDValue Size = Op.getOperand(1);
8963 // FIXME: Ensure alignment here
8965 bool Is64Bit = Subtarget->is64Bit();
8966 EVT SPTy = Is64Bit ? MVT::i64 : MVT::i32;
8968 if (getTargetMachine().Options.EnableSegmentedStacks) {
8969 MachineFunction &MF = DAG.getMachineFunction();
8970 MachineRegisterInfo &MRI = MF.getRegInfo();
8973 // The 64 bit implementation of segmented stacks needs to clobber both r10
8974 // r11. This makes it impossible to use it along with nested parameters.
8975 const Function *F = MF.getFunction();
8977 for (Function::const_arg_iterator I = F->arg_begin(), E = F->arg_end();
8979 if (I->hasNestAttr())
8980 report_fatal_error("Cannot use segmented stacks with functions that "
8981 "have nested arguments.");
8984 const TargetRegisterClass *AddrRegClass =
8985 getRegClassFor(Subtarget->is64Bit() ? MVT::i64:MVT::i32);
8986 unsigned Vreg = MRI.createVirtualRegister(AddrRegClass);
8987 Chain = DAG.getCopyToReg(Chain, dl, Vreg, Size);
8988 SDValue Value = DAG.getNode(X86ISD::SEG_ALLOCA, dl, SPTy, Chain,
8989 DAG.getRegister(Vreg, SPTy));
8990 SDValue Ops1[2] = { Value, Chain };
8991 return DAG.getMergeValues(Ops1, 2, dl);
8994 unsigned Reg = (Subtarget->is64Bit() ? X86::RAX : X86::EAX);
8996 Chain = DAG.getCopyToReg(Chain, dl, Reg, Size, Flag);
8997 Flag = Chain.getValue(1);
8998 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
9000 Chain = DAG.getNode(X86ISD::WIN_ALLOCA, dl, NodeTys, Chain, Flag);
9001 Flag = Chain.getValue(1);
9003 Chain = DAG.getCopyFromReg(Chain, dl, X86StackPtr, SPTy).getValue(1);
9005 SDValue Ops1[2] = { Chain.getValue(0), Chain };
9006 return DAG.getMergeValues(Ops1, 2, dl);
9010 SDValue X86TargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const {
9011 MachineFunction &MF = DAG.getMachineFunction();
9012 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
9014 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
9015 DebugLoc DL = Op.getDebugLoc();
9017 if (!Subtarget->is64Bit() || Subtarget->isTargetWin64()) {
9018 // vastart just stores the address of the VarArgsFrameIndex slot into the
9019 // memory location argument.
9020 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
9022 return DAG.getStore(Op.getOperand(0), DL, FR, Op.getOperand(1),
9023 MachinePointerInfo(SV), false, false, 0);
9027 // gp_offset (0 - 6 * 8)
9028 // fp_offset (48 - 48 + 8 * 16)
9029 // overflow_arg_area (point to parameters coming in memory).
9031 SmallVector<SDValue, 8> MemOps;
9032 SDValue FIN = Op.getOperand(1);
9034 SDValue Store = DAG.getStore(Op.getOperand(0), DL,
9035 DAG.getConstant(FuncInfo->getVarArgsGPOffset(),
9037 FIN, MachinePointerInfo(SV), false, false, 0);
9038 MemOps.push_back(Store);
9041 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
9042 FIN, DAG.getIntPtrConstant(4));
9043 Store = DAG.getStore(Op.getOperand(0), DL,
9044 DAG.getConstant(FuncInfo->getVarArgsFPOffset(),
9046 FIN, MachinePointerInfo(SV, 4), false, false, 0);
9047 MemOps.push_back(Store);
9049 // Store ptr to overflow_arg_area
9050 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
9051 FIN, DAG.getIntPtrConstant(4));
9052 SDValue OVFIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
9054 Store = DAG.getStore(Op.getOperand(0), DL, OVFIN, FIN,
9055 MachinePointerInfo(SV, 8),
9057 MemOps.push_back(Store);
9059 // Store ptr to reg_save_area.
9060 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
9061 FIN, DAG.getIntPtrConstant(8));
9062 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
9064 Store = DAG.getStore(Op.getOperand(0), DL, RSFIN, FIN,
9065 MachinePointerInfo(SV, 16), false, false, 0);
9066 MemOps.push_back(Store);
9067 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
9068 &MemOps[0], MemOps.size());
9071 SDValue X86TargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG) const {
9072 assert(Subtarget->is64Bit() &&
9073 "LowerVAARG only handles 64-bit va_arg!");
9074 assert((Subtarget->isTargetLinux() ||
9075 Subtarget->isTargetDarwin()) &&
9076 "Unhandled target in LowerVAARG");
9077 assert(Op.getNode()->getNumOperands() == 4);
9078 SDValue Chain = Op.getOperand(0);
9079 SDValue SrcPtr = Op.getOperand(1);
9080 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
9081 unsigned Align = Op.getConstantOperandVal(3);
9082 DebugLoc dl = Op.getDebugLoc();
9084 EVT ArgVT = Op.getNode()->getValueType(0);
9085 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
9086 uint32_t ArgSize = getTargetData()->getTypeAllocSize(ArgTy);
9089 // Decide which area this value should be read from.
9090 // TODO: Implement the AMD64 ABI in its entirety. This simple
9091 // selection mechanism works only for the basic types.
9092 if (ArgVT == MVT::f80) {
9093 llvm_unreachable("va_arg for f80 not yet implemented");
9094 } else if (ArgVT.isFloatingPoint() && ArgSize <= 16 /*bytes*/) {
9095 ArgMode = 2; // Argument passed in XMM register. Use fp_offset.
9096 } else if (ArgVT.isInteger() && ArgSize <= 32 /*bytes*/) {
9097 ArgMode = 1; // Argument passed in GPR64 register(s). Use gp_offset.
9099 llvm_unreachable("Unhandled argument type in LowerVAARG");
9103 // Sanity Check: Make sure using fp_offset makes sense.
9104 assert(!getTargetMachine().Options.UseSoftFloat &&
9105 !(DAG.getMachineFunction()
9106 .getFunction()->hasFnAttr(Attribute::NoImplicitFloat)) &&
9107 Subtarget->hasSSE1());
9110 // Insert VAARG_64 node into the DAG
9111 // VAARG_64 returns two values: Variable Argument Address, Chain
9112 SmallVector<SDValue, 11> InstOps;
9113 InstOps.push_back(Chain);
9114 InstOps.push_back(SrcPtr);
9115 InstOps.push_back(DAG.getConstant(ArgSize, MVT::i32));
9116 InstOps.push_back(DAG.getConstant(ArgMode, MVT::i8));
9117 InstOps.push_back(DAG.getConstant(Align, MVT::i32));
9118 SDVTList VTs = DAG.getVTList(getPointerTy(), MVT::Other);
9119 SDValue VAARG = DAG.getMemIntrinsicNode(X86ISD::VAARG_64, dl,
9120 VTs, &InstOps[0], InstOps.size(),
9122 MachinePointerInfo(SV),
9127 Chain = VAARG.getValue(1);
9129 // Load the next argument and return it
9130 return DAG.getLoad(ArgVT, dl,
9133 MachinePointerInfo(),
9134 false, false, false, 0);
9137 SDValue X86TargetLowering::LowerVACOPY(SDValue Op, SelectionDAG &DAG) const {
9138 // X86-64 va_list is a struct { i32, i32, i8*, i8* }.
9139 assert(Subtarget->is64Bit() && "This code only handles 64-bit va_copy!");
9140 SDValue Chain = Op.getOperand(0);
9141 SDValue DstPtr = Op.getOperand(1);
9142 SDValue SrcPtr = Op.getOperand(2);
9143 const Value *DstSV = cast<SrcValueSDNode>(Op.getOperand(3))->getValue();
9144 const Value *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
9145 DebugLoc DL = Op.getDebugLoc();
9147 return DAG.getMemcpy(Chain, DL, DstPtr, SrcPtr,
9148 DAG.getIntPtrConstant(24), 8, /*isVolatile*/false,
9150 MachinePointerInfo(DstSV), MachinePointerInfo(SrcSV));
9154 X86TargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const {
9155 DebugLoc dl = Op.getDebugLoc();
9156 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
9158 default: return SDValue(); // Don't custom lower most intrinsics.
9159 // Comparison intrinsics.
9160 case Intrinsic::x86_sse_comieq_ss:
9161 case Intrinsic::x86_sse_comilt_ss:
9162 case Intrinsic::x86_sse_comile_ss:
9163 case Intrinsic::x86_sse_comigt_ss:
9164 case Intrinsic::x86_sse_comige_ss:
9165 case Intrinsic::x86_sse_comineq_ss:
9166 case Intrinsic::x86_sse_ucomieq_ss:
9167 case Intrinsic::x86_sse_ucomilt_ss:
9168 case Intrinsic::x86_sse_ucomile_ss:
9169 case Intrinsic::x86_sse_ucomigt_ss:
9170 case Intrinsic::x86_sse_ucomige_ss:
9171 case Intrinsic::x86_sse_ucomineq_ss:
9172 case Intrinsic::x86_sse2_comieq_sd:
9173 case Intrinsic::x86_sse2_comilt_sd:
9174 case Intrinsic::x86_sse2_comile_sd:
9175 case Intrinsic::x86_sse2_comigt_sd:
9176 case Intrinsic::x86_sse2_comige_sd:
9177 case Intrinsic::x86_sse2_comineq_sd:
9178 case Intrinsic::x86_sse2_ucomieq_sd:
9179 case Intrinsic::x86_sse2_ucomilt_sd:
9180 case Intrinsic::x86_sse2_ucomile_sd:
9181 case Intrinsic::x86_sse2_ucomigt_sd:
9182 case Intrinsic::x86_sse2_ucomige_sd:
9183 case Intrinsic::x86_sse2_ucomineq_sd: {
9185 ISD::CondCode CC = ISD::SETCC_INVALID;
9188 case Intrinsic::x86_sse_comieq_ss:
9189 case Intrinsic::x86_sse2_comieq_sd:
9193 case Intrinsic::x86_sse_comilt_ss:
9194 case Intrinsic::x86_sse2_comilt_sd:
9198 case Intrinsic::x86_sse_comile_ss:
9199 case Intrinsic::x86_sse2_comile_sd:
9203 case Intrinsic::x86_sse_comigt_ss:
9204 case Intrinsic::x86_sse2_comigt_sd:
9208 case Intrinsic::x86_sse_comige_ss:
9209 case Intrinsic::x86_sse2_comige_sd:
9213 case Intrinsic::x86_sse_comineq_ss:
9214 case Intrinsic::x86_sse2_comineq_sd:
9218 case Intrinsic::x86_sse_ucomieq_ss:
9219 case Intrinsic::x86_sse2_ucomieq_sd:
9220 Opc = X86ISD::UCOMI;
9223 case Intrinsic::x86_sse_ucomilt_ss:
9224 case Intrinsic::x86_sse2_ucomilt_sd:
9225 Opc = X86ISD::UCOMI;
9228 case Intrinsic::x86_sse_ucomile_ss:
9229 case Intrinsic::x86_sse2_ucomile_sd:
9230 Opc = X86ISD::UCOMI;
9233 case Intrinsic::x86_sse_ucomigt_ss:
9234 case Intrinsic::x86_sse2_ucomigt_sd:
9235 Opc = X86ISD::UCOMI;
9238 case Intrinsic::x86_sse_ucomige_ss:
9239 case Intrinsic::x86_sse2_ucomige_sd:
9240 Opc = X86ISD::UCOMI;
9243 case Intrinsic::x86_sse_ucomineq_ss:
9244 case Intrinsic::x86_sse2_ucomineq_sd:
9245 Opc = X86ISD::UCOMI;
9250 SDValue LHS = Op.getOperand(1);
9251 SDValue RHS = Op.getOperand(2);
9252 unsigned X86CC = TranslateX86CC(CC, true, LHS, RHS, DAG);
9253 assert(X86CC != X86::COND_INVALID && "Unexpected illegal condition!");
9254 SDValue Cond = DAG.getNode(Opc, dl, MVT::i32, LHS, RHS);
9255 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
9256 DAG.getConstant(X86CC, MVT::i8), Cond);
9257 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
9259 // Arithmetic intrinsics.
9260 case Intrinsic::x86_sse3_hadd_ps:
9261 case Intrinsic::x86_sse3_hadd_pd:
9262 case Intrinsic::x86_avx_hadd_ps_256:
9263 case Intrinsic::x86_avx_hadd_pd_256:
9264 return DAG.getNode(X86ISD::FHADD, dl, Op.getValueType(),
9265 Op.getOperand(1), Op.getOperand(2));
9266 case Intrinsic::x86_sse3_hsub_ps:
9267 case Intrinsic::x86_sse3_hsub_pd:
9268 case Intrinsic::x86_avx_hsub_ps_256:
9269 case Intrinsic::x86_avx_hsub_pd_256:
9270 return DAG.getNode(X86ISD::FHSUB, dl, Op.getValueType(),
9271 Op.getOperand(1), Op.getOperand(2));
9272 case Intrinsic::x86_avx2_psllv_d:
9273 case Intrinsic::x86_avx2_psllv_q:
9274 case Intrinsic::x86_avx2_psllv_d_256:
9275 case Intrinsic::x86_avx2_psllv_q_256:
9276 return DAG.getNode(ISD::SHL, dl, Op.getValueType(),
9277 Op.getOperand(1), Op.getOperand(2));
9278 case Intrinsic::x86_avx2_psrlv_d:
9279 case Intrinsic::x86_avx2_psrlv_q:
9280 case Intrinsic::x86_avx2_psrlv_d_256:
9281 case Intrinsic::x86_avx2_psrlv_q_256:
9282 return DAG.getNode(ISD::SRL, dl, Op.getValueType(),
9283 Op.getOperand(1), Op.getOperand(2));
9284 case Intrinsic::x86_avx2_psrav_d:
9285 case Intrinsic::x86_avx2_psrav_d_256:
9286 return DAG.getNode(ISD::SRA, dl, Op.getValueType(),
9287 Op.getOperand(1), Op.getOperand(2));
9289 // ptest and testp intrinsics. The intrinsic these come from are designed to
9290 // return an integer value, not just an instruction so lower it to the ptest
9291 // or testp pattern and a setcc for the result.
9292 case Intrinsic::x86_sse41_ptestz:
9293 case Intrinsic::x86_sse41_ptestc:
9294 case Intrinsic::x86_sse41_ptestnzc:
9295 case Intrinsic::x86_avx_ptestz_256:
9296 case Intrinsic::x86_avx_ptestc_256:
9297 case Intrinsic::x86_avx_ptestnzc_256:
9298 case Intrinsic::x86_avx_vtestz_ps:
9299 case Intrinsic::x86_avx_vtestc_ps:
9300 case Intrinsic::x86_avx_vtestnzc_ps:
9301 case Intrinsic::x86_avx_vtestz_pd:
9302 case Intrinsic::x86_avx_vtestc_pd:
9303 case Intrinsic::x86_avx_vtestnzc_pd:
9304 case Intrinsic::x86_avx_vtestz_ps_256:
9305 case Intrinsic::x86_avx_vtestc_ps_256:
9306 case Intrinsic::x86_avx_vtestnzc_ps_256:
9307 case Intrinsic::x86_avx_vtestz_pd_256:
9308 case Intrinsic::x86_avx_vtestc_pd_256:
9309 case Intrinsic::x86_avx_vtestnzc_pd_256: {
9310 bool IsTestPacked = false;
9313 default: llvm_unreachable("Bad fallthrough in Intrinsic lowering.");
9314 case Intrinsic::x86_avx_vtestz_ps:
9315 case Intrinsic::x86_avx_vtestz_pd:
9316 case Intrinsic::x86_avx_vtestz_ps_256:
9317 case Intrinsic::x86_avx_vtestz_pd_256:
9318 IsTestPacked = true; // Fallthrough
9319 case Intrinsic::x86_sse41_ptestz:
9320 case Intrinsic::x86_avx_ptestz_256:
9322 X86CC = X86::COND_E;
9324 case Intrinsic::x86_avx_vtestc_ps:
9325 case Intrinsic::x86_avx_vtestc_pd:
9326 case Intrinsic::x86_avx_vtestc_ps_256:
9327 case Intrinsic::x86_avx_vtestc_pd_256:
9328 IsTestPacked = true; // Fallthrough
9329 case Intrinsic::x86_sse41_ptestc:
9330 case Intrinsic::x86_avx_ptestc_256:
9332 X86CC = X86::COND_B;
9334 case Intrinsic::x86_avx_vtestnzc_ps:
9335 case Intrinsic::x86_avx_vtestnzc_pd:
9336 case Intrinsic::x86_avx_vtestnzc_ps_256:
9337 case Intrinsic::x86_avx_vtestnzc_pd_256:
9338 IsTestPacked = true; // Fallthrough
9339 case Intrinsic::x86_sse41_ptestnzc:
9340 case Intrinsic::x86_avx_ptestnzc_256:
9342 X86CC = X86::COND_A;
9346 SDValue LHS = Op.getOperand(1);
9347 SDValue RHS = Op.getOperand(2);
9348 unsigned TestOpc = IsTestPacked ? X86ISD::TESTP : X86ISD::PTEST;
9349 SDValue Test = DAG.getNode(TestOpc, dl, MVT::i32, LHS, RHS);
9350 SDValue CC = DAG.getConstant(X86CC, MVT::i8);
9351 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8, CC, Test);
9352 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
9355 // Fix vector shift instructions where the last operand is a non-immediate
9357 case Intrinsic::x86_avx2_pslli_w:
9358 case Intrinsic::x86_avx2_pslli_d:
9359 case Intrinsic::x86_avx2_pslli_q:
9360 case Intrinsic::x86_avx2_psrli_w:
9361 case Intrinsic::x86_avx2_psrli_d:
9362 case Intrinsic::x86_avx2_psrli_q:
9363 case Intrinsic::x86_avx2_psrai_w:
9364 case Intrinsic::x86_avx2_psrai_d:
9365 case Intrinsic::x86_sse2_pslli_w:
9366 case Intrinsic::x86_sse2_pslli_d:
9367 case Intrinsic::x86_sse2_pslli_q:
9368 case Intrinsic::x86_sse2_psrli_w:
9369 case Intrinsic::x86_sse2_psrli_d:
9370 case Intrinsic::x86_sse2_psrli_q:
9371 case Intrinsic::x86_sse2_psrai_w:
9372 case Intrinsic::x86_sse2_psrai_d:
9373 case Intrinsic::x86_mmx_pslli_w:
9374 case Intrinsic::x86_mmx_pslli_d:
9375 case Intrinsic::x86_mmx_pslli_q:
9376 case Intrinsic::x86_mmx_psrli_w:
9377 case Intrinsic::x86_mmx_psrli_d:
9378 case Intrinsic::x86_mmx_psrli_q:
9379 case Intrinsic::x86_mmx_psrai_w:
9380 case Intrinsic::x86_mmx_psrai_d: {
9381 SDValue ShAmt = Op.getOperand(2);
9382 if (isa<ConstantSDNode>(ShAmt))
9385 unsigned NewIntNo = 0;
9386 EVT ShAmtVT = MVT::v4i32;
9388 case Intrinsic::x86_sse2_pslli_w:
9389 NewIntNo = Intrinsic::x86_sse2_psll_w;
9391 case Intrinsic::x86_sse2_pslli_d:
9392 NewIntNo = Intrinsic::x86_sse2_psll_d;
9394 case Intrinsic::x86_sse2_pslli_q:
9395 NewIntNo = Intrinsic::x86_sse2_psll_q;
9397 case Intrinsic::x86_sse2_psrli_w:
9398 NewIntNo = Intrinsic::x86_sse2_psrl_w;
9400 case Intrinsic::x86_sse2_psrli_d:
9401 NewIntNo = Intrinsic::x86_sse2_psrl_d;
9403 case Intrinsic::x86_sse2_psrli_q:
9404 NewIntNo = Intrinsic::x86_sse2_psrl_q;
9406 case Intrinsic::x86_sse2_psrai_w:
9407 NewIntNo = Intrinsic::x86_sse2_psra_w;
9409 case Intrinsic::x86_sse2_psrai_d:
9410 NewIntNo = Intrinsic::x86_sse2_psra_d;
9412 case Intrinsic::x86_avx2_pslli_w:
9413 NewIntNo = Intrinsic::x86_avx2_psll_w;
9415 case Intrinsic::x86_avx2_pslli_d:
9416 NewIntNo = Intrinsic::x86_avx2_psll_d;
9418 case Intrinsic::x86_avx2_pslli_q:
9419 NewIntNo = Intrinsic::x86_avx2_psll_q;
9421 case Intrinsic::x86_avx2_psrli_w:
9422 NewIntNo = Intrinsic::x86_avx2_psrl_w;
9424 case Intrinsic::x86_avx2_psrli_d:
9425 NewIntNo = Intrinsic::x86_avx2_psrl_d;
9427 case Intrinsic::x86_avx2_psrli_q:
9428 NewIntNo = Intrinsic::x86_avx2_psrl_q;
9430 case Intrinsic::x86_avx2_psrai_w:
9431 NewIntNo = Intrinsic::x86_avx2_psra_w;
9433 case Intrinsic::x86_avx2_psrai_d:
9434 NewIntNo = Intrinsic::x86_avx2_psra_d;
9437 ShAmtVT = MVT::v2i32;
9439 case Intrinsic::x86_mmx_pslli_w:
9440 NewIntNo = Intrinsic::x86_mmx_psll_w;
9442 case Intrinsic::x86_mmx_pslli_d:
9443 NewIntNo = Intrinsic::x86_mmx_psll_d;
9445 case Intrinsic::x86_mmx_pslli_q:
9446 NewIntNo = Intrinsic::x86_mmx_psll_q;
9448 case Intrinsic::x86_mmx_psrli_w:
9449 NewIntNo = Intrinsic::x86_mmx_psrl_w;
9451 case Intrinsic::x86_mmx_psrli_d:
9452 NewIntNo = Intrinsic::x86_mmx_psrl_d;
9454 case Intrinsic::x86_mmx_psrli_q:
9455 NewIntNo = Intrinsic::x86_mmx_psrl_q;
9457 case Intrinsic::x86_mmx_psrai_w:
9458 NewIntNo = Intrinsic::x86_mmx_psra_w;
9460 case Intrinsic::x86_mmx_psrai_d:
9461 NewIntNo = Intrinsic::x86_mmx_psra_d;
9463 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
9469 // The vector shift intrinsics with scalars uses 32b shift amounts but
9470 // the sse2/mmx shift instructions reads 64 bits. Set the upper 32 bits
9474 ShOps[1] = DAG.getConstant(0, MVT::i32);
9475 if (ShAmtVT == MVT::v4i32) {
9476 ShOps[2] = DAG.getUNDEF(MVT::i32);
9477 ShOps[3] = DAG.getUNDEF(MVT::i32);
9478 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, ShAmtVT, &ShOps[0], 4);
9480 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, ShAmtVT, &ShOps[0], 2);
9481 // FIXME this must be lowered to get rid of the invalid type.
9484 EVT VT = Op.getValueType();
9485 ShAmt = DAG.getNode(ISD::BITCAST, dl, VT, ShAmt);
9486 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
9487 DAG.getConstant(NewIntNo, MVT::i32),
9488 Op.getOperand(1), ShAmt);
9493 SDValue X86TargetLowering::LowerRETURNADDR(SDValue Op,
9494 SelectionDAG &DAG) const {
9495 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
9496 MFI->setReturnAddressIsTaken(true);
9498 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
9499 DebugLoc dl = Op.getDebugLoc();
9502 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
9504 DAG.getConstant(TD->getPointerSize(),
9505 Subtarget->is64Bit() ? MVT::i64 : MVT::i32);
9506 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(),
9507 DAG.getNode(ISD::ADD, dl, getPointerTy(),
9509 MachinePointerInfo(), false, false, false, 0);
9512 // Just load the return address.
9513 SDValue RetAddrFI = getReturnAddressFrameIndex(DAG);
9514 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(),
9515 RetAddrFI, MachinePointerInfo(), false, false, false, 0);
9518 SDValue X86TargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {
9519 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
9520 MFI->setFrameAddressIsTaken(true);
9522 EVT VT = Op.getValueType();
9523 DebugLoc dl = Op.getDebugLoc(); // FIXME probably not meaningful
9524 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
9525 unsigned FrameReg = Subtarget->is64Bit() ? X86::RBP : X86::EBP;
9526 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT);
9528 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr,
9529 MachinePointerInfo(),
9530 false, false, false, 0);
9534 SDValue X86TargetLowering::LowerFRAME_TO_ARGS_OFFSET(SDValue Op,
9535 SelectionDAG &DAG) const {
9536 return DAG.getIntPtrConstant(2*TD->getPointerSize());
9539 SDValue X86TargetLowering::LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const {
9540 MachineFunction &MF = DAG.getMachineFunction();
9541 SDValue Chain = Op.getOperand(0);
9542 SDValue Offset = Op.getOperand(1);
9543 SDValue Handler = Op.getOperand(2);
9544 DebugLoc dl = Op.getDebugLoc();
9546 SDValue Frame = DAG.getCopyFromReg(DAG.getEntryNode(), dl,
9547 Subtarget->is64Bit() ? X86::RBP : X86::EBP,
9549 unsigned StoreAddrReg = (Subtarget->is64Bit() ? X86::RCX : X86::ECX);
9551 SDValue StoreAddr = DAG.getNode(ISD::ADD, dl, getPointerTy(), Frame,
9552 DAG.getIntPtrConstant(TD->getPointerSize()));
9553 StoreAddr = DAG.getNode(ISD::ADD, dl, getPointerTy(), StoreAddr, Offset);
9554 Chain = DAG.getStore(Chain, dl, Handler, StoreAddr, MachinePointerInfo(),
9556 Chain = DAG.getCopyToReg(Chain, dl, StoreAddrReg, StoreAddr);
9557 MF.getRegInfo().addLiveOut(StoreAddrReg);
9559 return DAG.getNode(X86ISD::EH_RETURN, dl,
9561 Chain, DAG.getRegister(StoreAddrReg, getPointerTy()));
9564 SDValue X86TargetLowering::LowerADJUST_TRAMPOLINE(SDValue Op,
9565 SelectionDAG &DAG) const {
9566 return Op.getOperand(0);
9569 SDValue X86TargetLowering::LowerINIT_TRAMPOLINE(SDValue Op,
9570 SelectionDAG &DAG) const {
9571 SDValue Root = Op.getOperand(0);
9572 SDValue Trmp = Op.getOperand(1); // trampoline
9573 SDValue FPtr = Op.getOperand(2); // nested function
9574 SDValue Nest = Op.getOperand(3); // 'nest' parameter value
9575 DebugLoc dl = Op.getDebugLoc();
9577 const Value *TrmpAddr = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
9579 if (Subtarget->is64Bit()) {
9580 SDValue OutChains[6];
9582 // Large code-model.
9583 const unsigned char JMP64r = 0xFF; // 64-bit jmp through register opcode.
9584 const unsigned char MOV64ri = 0xB8; // X86::MOV64ri opcode.
9586 const unsigned char N86R10 = X86_MC::getX86RegNum(X86::R10);
9587 const unsigned char N86R11 = X86_MC::getX86RegNum(X86::R11);
9589 const unsigned char REX_WB = 0x40 | 0x08 | 0x01; // REX prefix
9591 // Load the pointer to the nested function into R11.
9592 unsigned OpCode = ((MOV64ri | N86R11) << 8) | REX_WB; // movabsq r11
9593 SDValue Addr = Trmp;
9594 OutChains[0] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
9595 Addr, MachinePointerInfo(TrmpAddr),
9598 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
9599 DAG.getConstant(2, MVT::i64));
9600 OutChains[1] = DAG.getStore(Root, dl, FPtr, Addr,
9601 MachinePointerInfo(TrmpAddr, 2),
9604 // Load the 'nest' parameter value into R10.
9605 // R10 is specified in X86CallingConv.td
9606 OpCode = ((MOV64ri | N86R10) << 8) | REX_WB; // movabsq r10
9607 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
9608 DAG.getConstant(10, MVT::i64));
9609 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
9610 Addr, MachinePointerInfo(TrmpAddr, 10),
9613 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
9614 DAG.getConstant(12, MVT::i64));
9615 OutChains[3] = DAG.getStore(Root, dl, Nest, Addr,
9616 MachinePointerInfo(TrmpAddr, 12),
9619 // Jump to the nested function.
9620 OpCode = (JMP64r << 8) | REX_WB; // jmpq *...
9621 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
9622 DAG.getConstant(20, MVT::i64));
9623 OutChains[4] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
9624 Addr, MachinePointerInfo(TrmpAddr, 20),
9627 unsigned char ModRM = N86R11 | (4 << 3) | (3 << 6); // ...r11
9628 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
9629 DAG.getConstant(22, MVT::i64));
9630 OutChains[5] = DAG.getStore(Root, dl, DAG.getConstant(ModRM, MVT::i8), Addr,
9631 MachinePointerInfo(TrmpAddr, 22),
9634 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains, 6);
9636 const Function *Func =
9637 cast<Function>(cast<SrcValueSDNode>(Op.getOperand(5))->getValue());
9638 CallingConv::ID CC = Func->getCallingConv();
9643 llvm_unreachable("Unsupported calling convention");
9644 case CallingConv::C:
9645 case CallingConv::X86_StdCall: {
9646 // Pass 'nest' parameter in ECX.
9647 // Must be kept in sync with X86CallingConv.td
9650 // Check that ECX wasn't needed by an 'inreg' parameter.
9651 FunctionType *FTy = Func->getFunctionType();
9652 const AttrListPtr &Attrs = Func->getAttributes();
9654 if (!Attrs.isEmpty() && !Func->isVarArg()) {
9655 unsigned InRegCount = 0;
9658 for (FunctionType::param_iterator I = FTy->param_begin(),
9659 E = FTy->param_end(); I != E; ++I, ++Idx)
9660 if (Attrs.paramHasAttr(Idx, Attribute::InReg))
9661 // FIXME: should only count parameters that are lowered to integers.
9662 InRegCount += (TD->getTypeSizeInBits(*I) + 31) / 32;
9664 if (InRegCount > 2) {
9665 report_fatal_error("Nest register in use - reduce number of inreg"
9671 case CallingConv::X86_FastCall:
9672 case CallingConv::X86_ThisCall:
9673 case CallingConv::Fast:
9674 // Pass 'nest' parameter in EAX.
9675 // Must be kept in sync with X86CallingConv.td
9680 SDValue OutChains[4];
9683 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
9684 DAG.getConstant(10, MVT::i32));
9685 Disp = DAG.getNode(ISD::SUB, dl, MVT::i32, FPtr, Addr);
9687 // This is storing the opcode for MOV32ri.
9688 const unsigned char MOV32ri = 0xB8; // X86::MOV32ri's opcode byte.
9689 const unsigned char N86Reg = X86_MC::getX86RegNum(NestReg);
9690 OutChains[0] = DAG.getStore(Root, dl,
9691 DAG.getConstant(MOV32ri|N86Reg, MVT::i8),
9692 Trmp, MachinePointerInfo(TrmpAddr),
9695 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
9696 DAG.getConstant(1, MVT::i32));
9697 OutChains[1] = DAG.getStore(Root, dl, Nest, Addr,
9698 MachinePointerInfo(TrmpAddr, 1),
9701 const unsigned char JMP = 0xE9; // jmp <32bit dst> opcode.
9702 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
9703 DAG.getConstant(5, MVT::i32));
9704 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(JMP, MVT::i8), Addr,
9705 MachinePointerInfo(TrmpAddr, 5),
9708 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
9709 DAG.getConstant(6, MVT::i32));
9710 OutChains[3] = DAG.getStore(Root, dl, Disp, Addr,
9711 MachinePointerInfo(TrmpAddr, 6),
9714 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains, 4);
9718 SDValue X86TargetLowering::LowerFLT_ROUNDS_(SDValue Op,
9719 SelectionDAG &DAG) const {
9721 The rounding mode is in bits 11:10 of FPSR, and has the following
9728 FLT_ROUNDS, on the other hand, expects the following:
9735 To perform the conversion, we do:
9736 (((((FPSR & 0x800) >> 11) | ((FPSR & 0x400) >> 9)) + 1) & 3)
9739 MachineFunction &MF = DAG.getMachineFunction();
9740 const TargetMachine &TM = MF.getTarget();
9741 const TargetFrameLowering &TFI = *TM.getFrameLowering();
9742 unsigned StackAlignment = TFI.getStackAlignment();
9743 EVT VT = Op.getValueType();
9744 DebugLoc DL = Op.getDebugLoc();
9746 // Save FP Control Word to stack slot
9747 int SSFI = MF.getFrameInfo()->CreateStackObject(2, StackAlignment, false);
9748 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
9751 MachineMemOperand *MMO =
9752 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
9753 MachineMemOperand::MOStore, 2, 2);
9755 SDValue Ops[] = { DAG.getEntryNode(), StackSlot };
9756 SDValue Chain = DAG.getMemIntrinsicNode(X86ISD::FNSTCW16m, DL,
9757 DAG.getVTList(MVT::Other),
9758 Ops, 2, MVT::i16, MMO);
9760 // Load FP Control Word from stack slot
9761 SDValue CWD = DAG.getLoad(MVT::i16, DL, Chain, StackSlot,
9762 MachinePointerInfo(), false, false, false, 0);
9764 // Transform as necessary
9766 DAG.getNode(ISD::SRL, DL, MVT::i16,
9767 DAG.getNode(ISD::AND, DL, MVT::i16,
9768 CWD, DAG.getConstant(0x800, MVT::i16)),
9769 DAG.getConstant(11, MVT::i8));
9771 DAG.getNode(ISD::SRL, DL, MVT::i16,
9772 DAG.getNode(ISD::AND, DL, MVT::i16,
9773 CWD, DAG.getConstant(0x400, MVT::i16)),
9774 DAG.getConstant(9, MVT::i8));
9777 DAG.getNode(ISD::AND, DL, MVT::i16,
9778 DAG.getNode(ISD::ADD, DL, MVT::i16,
9779 DAG.getNode(ISD::OR, DL, MVT::i16, CWD1, CWD2),
9780 DAG.getConstant(1, MVT::i16)),
9781 DAG.getConstant(3, MVT::i16));
9784 return DAG.getNode((VT.getSizeInBits() < 16 ?
9785 ISD::TRUNCATE : ISD::ZERO_EXTEND), DL, VT, RetVal);
9788 SDValue X86TargetLowering::LowerCTLZ(SDValue Op, SelectionDAG &DAG) const {
9789 EVT VT = Op.getValueType();
9791 unsigned NumBits = VT.getSizeInBits();
9792 DebugLoc dl = Op.getDebugLoc();
9794 Op = Op.getOperand(0);
9795 if (VT == MVT::i8) {
9796 // Zero extend to i32 since there is not an i8 bsr.
9798 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
9801 // Issue a bsr (scan bits in reverse) which also sets EFLAGS.
9802 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
9803 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
9805 // If src is zero (i.e. bsr sets ZF), returns NumBits.
9808 DAG.getConstant(NumBits+NumBits-1, OpVT),
9809 DAG.getConstant(X86::COND_E, MVT::i8),
9812 Op = DAG.getNode(X86ISD::CMOV, dl, OpVT, Ops, array_lengthof(Ops));
9814 // Finally xor with NumBits-1.
9815 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT));
9818 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
9822 SDValue X86TargetLowering::LowerCTLZ_ZERO_UNDEF(SDValue Op,
9823 SelectionDAG &DAG) const {
9824 EVT VT = Op.getValueType();
9826 unsigned NumBits = VT.getSizeInBits();
9827 DebugLoc dl = Op.getDebugLoc();
9829 Op = Op.getOperand(0);
9830 if (VT == MVT::i8) {
9831 // Zero extend to i32 since there is not an i8 bsr.
9833 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
9836 // Issue a bsr (scan bits in reverse).
9837 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
9838 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
9840 // And xor with NumBits-1.
9841 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT));
9844 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
9848 SDValue X86TargetLowering::LowerCTTZ(SDValue Op, SelectionDAG &DAG) const {
9849 EVT VT = Op.getValueType();
9850 unsigned NumBits = VT.getSizeInBits();
9851 DebugLoc dl = Op.getDebugLoc();
9852 Op = Op.getOperand(0);
9854 // Issue a bsf (scan bits forward) which also sets EFLAGS.
9855 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
9856 Op = DAG.getNode(X86ISD::BSF, dl, VTs, Op);
9858 // If src is zero (i.e. bsf sets ZF), returns NumBits.
9861 DAG.getConstant(NumBits, VT),
9862 DAG.getConstant(X86::COND_E, MVT::i8),
9865 return DAG.getNode(X86ISD::CMOV, dl, VT, Ops, array_lengthof(Ops));
9868 // Lower256IntArith - Break a 256-bit integer operation into two new 128-bit
9869 // ones, and then concatenate the result back.
9870 static SDValue Lower256IntArith(SDValue Op, SelectionDAG &DAG) {
9871 EVT VT = Op.getValueType();
9873 assert(VT.getSizeInBits() == 256 && VT.isInteger() &&
9874 "Unsupported value type for operation");
9876 int NumElems = VT.getVectorNumElements();
9877 DebugLoc dl = Op.getDebugLoc();
9878 SDValue Idx0 = DAG.getConstant(0, MVT::i32);
9879 SDValue Idx1 = DAG.getConstant(NumElems/2, MVT::i32);
9881 // Extract the LHS vectors
9882 SDValue LHS = Op.getOperand(0);
9883 SDValue LHS1 = Extract128BitVector(LHS, Idx0, DAG, dl);
9884 SDValue LHS2 = Extract128BitVector(LHS, Idx1, DAG, dl);
9886 // Extract the RHS vectors
9887 SDValue RHS = Op.getOperand(1);
9888 SDValue RHS1 = Extract128BitVector(RHS, Idx0, DAG, dl);
9889 SDValue RHS2 = Extract128BitVector(RHS, Idx1, DAG, dl);
9891 MVT EltVT = VT.getVectorElementType().getSimpleVT();
9892 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
9894 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
9895 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1),
9896 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2));
9899 SDValue X86TargetLowering::LowerADD(SDValue Op, SelectionDAG &DAG) const {
9900 assert(Op.getValueType().getSizeInBits() == 256 &&
9901 Op.getValueType().isInteger() &&
9902 "Only handle AVX 256-bit vector integer operation");
9903 return Lower256IntArith(Op, DAG);
9906 SDValue X86TargetLowering::LowerSUB(SDValue Op, SelectionDAG &DAG) const {
9907 assert(Op.getValueType().getSizeInBits() == 256 &&
9908 Op.getValueType().isInteger() &&
9909 "Only handle AVX 256-bit vector integer operation");
9910 return Lower256IntArith(Op, DAG);
9913 SDValue X86TargetLowering::LowerMUL(SDValue Op, SelectionDAG &DAG) const {
9914 EVT VT = Op.getValueType();
9916 // Decompose 256-bit ops into smaller 128-bit ops.
9917 if (VT.getSizeInBits() == 256 && !Subtarget->hasAVX2())
9918 return Lower256IntArith(Op, DAG);
9920 DebugLoc dl = Op.getDebugLoc();
9922 SDValue A = Op.getOperand(0);
9923 SDValue B = Op.getOperand(1);
9925 if (VT == MVT::v4i64) {
9926 assert(Subtarget->hasAVX2() && "Lowering v4i64 multiply requires AVX2");
9928 // ulong2 Ahi = __builtin_ia32_psrlqi256( a, 32);
9929 // ulong2 Bhi = __builtin_ia32_psrlqi256( b, 32);
9930 // ulong2 AloBlo = __builtin_ia32_pmuludq256( a, b );
9931 // ulong2 AloBhi = __builtin_ia32_pmuludq256( a, Bhi );
9932 // ulong2 AhiBlo = __builtin_ia32_pmuludq256( Ahi, b );
9934 // AloBhi = __builtin_ia32_psllqi256( AloBhi, 32 );
9935 // AhiBlo = __builtin_ia32_psllqi256( AhiBlo, 32 );
9936 // return AloBlo + AloBhi + AhiBlo;
9938 SDValue Ahi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
9939 DAG.getConstant(Intrinsic::x86_avx2_psrli_q, MVT::i32),
9940 A, DAG.getConstant(32, MVT::i32));
9941 SDValue Bhi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
9942 DAG.getConstant(Intrinsic::x86_avx2_psrli_q, MVT::i32),
9943 B, DAG.getConstant(32, MVT::i32));
9944 SDValue AloBlo = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
9945 DAG.getConstant(Intrinsic::x86_avx2_pmulu_dq, MVT::i32),
9947 SDValue AloBhi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
9948 DAG.getConstant(Intrinsic::x86_avx2_pmulu_dq, MVT::i32),
9950 SDValue AhiBlo = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
9951 DAG.getConstant(Intrinsic::x86_avx2_pmulu_dq, MVT::i32),
9953 AloBhi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
9954 DAG.getConstant(Intrinsic::x86_avx2_pslli_q, MVT::i32),
9955 AloBhi, DAG.getConstant(32, MVT::i32));
9956 AhiBlo = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
9957 DAG.getConstant(Intrinsic::x86_avx2_pslli_q, MVT::i32),
9958 AhiBlo, DAG.getConstant(32, MVT::i32));
9959 SDValue Res = DAG.getNode(ISD::ADD, dl, VT, AloBlo, AloBhi);
9960 Res = DAG.getNode(ISD::ADD, dl, VT, Res, AhiBlo);
9964 assert(VT == MVT::v2i64 && "Only know how to lower V2I64 multiply");
9966 // ulong2 Ahi = __builtin_ia32_psrlqi128( a, 32);
9967 // ulong2 Bhi = __builtin_ia32_psrlqi128( b, 32);
9968 // ulong2 AloBlo = __builtin_ia32_pmuludq128( a, b );
9969 // ulong2 AloBhi = __builtin_ia32_pmuludq128( a, Bhi );
9970 // ulong2 AhiBlo = __builtin_ia32_pmuludq128( Ahi, b );
9972 // AloBhi = __builtin_ia32_psllqi128( AloBhi, 32 );
9973 // AhiBlo = __builtin_ia32_psllqi128( AhiBlo, 32 );
9974 // return AloBlo + AloBhi + AhiBlo;
9976 SDValue Ahi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
9977 DAG.getConstant(Intrinsic::x86_sse2_psrli_q, MVT::i32),
9978 A, DAG.getConstant(32, MVT::i32));
9979 SDValue Bhi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
9980 DAG.getConstant(Intrinsic::x86_sse2_psrli_q, MVT::i32),
9981 B, DAG.getConstant(32, MVT::i32));
9982 SDValue AloBlo = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
9983 DAG.getConstant(Intrinsic::x86_sse2_pmulu_dq, MVT::i32),
9985 SDValue AloBhi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
9986 DAG.getConstant(Intrinsic::x86_sse2_pmulu_dq, MVT::i32),
9988 SDValue AhiBlo = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
9989 DAG.getConstant(Intrinsic::x86_sse2_pmulu_dq, MVT::i32),
9991 AloBhi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
9992 DAG.getConstant(Intrinsic::x86_sse2_pslli_q, MVT::i32),
9993 AloBhi, DAG.getConstant(32, MVT::i32));
9994 AhiBlo = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
9995 DAG.getConstant(Intrinsic::x86_sse2_pslli_q, MVT::i32),
9996 AhiBlo, DAG.getConstant(32, MVT::i32));
9997 SDValue Res = DAG.getNode(ISD::ADD, dl, VT, AloBlo, AloBhi);
9998 Res = DAG.getNode(ISD::ADD, dl, VT, Res, AhiBlo);
10002 SDValue X86TargetLowering::LowerShift(SDValue Op, SelectionDAG &DAG) const {
10004 EVT VT = Op.getValueType();
10005 DebugLoc dl = Op.getDebugLoc();
10006 SDValue R = Op.getOperand(0);
10007 SDValue Amt = Op.getOperand(1);
10008 LLVMContext *Context = DAG.getContext();
10010 if (!Subtarget->hasSSE2())
10013 // Optimize shl/srl/sra with constant shift amount.
10014 if (isSplatVector(Amt.getNode())) {
10015 SDValue SclrAmt = Amt->getOperand(0);
10016 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(SclrAmt)) {
10017 uint64_t ShiftAmt = C->getZExtValue();
10019 if (VT == MVT::v16i8 && Op.getOpcode() == ISD::SHL) {
10020 // Make a large shift.
10022 DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
10023 DAG.getConstant(Intrinsic::x86_sse2_pslli_w, MVT::i32),
10024 R, DAG.getConstant(ShiftAmt, MVT::i32));
10025 // Zero out the rightmost bits.
10026 SmallVector<SDValue, 16> V(16, DAG.getConstant(uint8_t(-1U << ShiftAmt),
10028 return DAG.getNode(ISD::AND, dl, VT, SHL,
10029 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 16));
10032 if (VT == MVT::v2i64 && Op.getOpcode() == ISD::SHL)
10033 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
10034 DAG.getConstant(Intrinsic::x86_sse2_pslli_q, MVT::i32),
10035 R, DAG.getConstant(ShiftAmt, MVT::i32));
10037 if (VT == MVT::v4i32 && Op.getOpcode() == ISD::SHL)
10038 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
10039 DAG.getConstant(Intrinsic::x86_sse2_pslli_d, MVT::i32),
10040 R, DAG.getConstant(ShiftAmt, MVT::i32));
10042 if (VT == MVT::v8i16 && Op.getOpcode() == ISD::SHL)
10043 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
10044 DAG.getConstant(Intrinsic::x86_sse2_pslli_w, MVT::i32),
10045 R, DAG.getConstant(ShiftAmt, MVT::i32));
10047 if (VT == MVT::v16i8 && Op.getOpcode() == ISD::SRL) {
10048 // Make a large shift.
10050 DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
10051 DAG.getConstant(Intrinsic::x86_sse2_psrli_w, MVT::i32),
10052 R, DAG.getConstant(ShiftAmt, MVT::i32));
10053 // Zero out the leftmost bits.
10054 SmallVector<SDValue, 16> V(16, DAG.getConstant(uint8_t(-1U) >> ShiftAmt,
10056 return DAG.getNode(ISD::AND, dl, VT, SRL,
10057 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 16));
10060 if (VT == MVT::v2i64 && Op.getOpcode() == ISD::SRL)
10061 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
10062 DAG.getConstant(Intrinsic::x86_sse2_psrli_q, MVT::i32),
10063 R, DAG.getConstant(ShiftAmt, MVT::i32));
10065 if (VT == MVT::v4i32 && Op.getOpcode() == ISD::SRL)
10066 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
10067 DAG.getConstant(Intrinsic::x86_sse2_psrli_d, MVT::i32),
10068 R, DAG.getConstant(ShiftAmt, MVT::i32));
10070 if (VT == MVT::v8i16 && Op.getOpcode() == ISD::SRL)
10071 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
10072 DAG.getConstant(Intrinsic::x86_sse2_psrli_w, MVT::i32),
10073 R, DAG.getConstant(ShiftAmt, MVT::i32));
10075 if (VT == MVT::v4i32 && Op.getOpcode() == ISD::SRA)
10076 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
10077 DAG.getConstant(Intrinsic::x86_sse2_psrai_d, MVT::i32),
10078 R, DAG.getConstant(ShiftAmt, MVT::i32));
10080 if (VT == MVT::v8i16 && Op.getOpcode() == ISD::SRA)
10081 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
10082 DAG.getConstant(Intrinsic::x86_sse2_psrai_w, MVT::i32),
10083 R, DAG.getConstant(ShiftAmt, MVT::i32));
10085 if (VT == MVT::v16i8 && Op.getOpcode() == ISD::SRA) {
10086 if (ShiftAmt == 7) {
10087 // R s>> 7 === R s< 0
10088 SDValue Zeros = getZeroVector(VT, /* HasSSE2 */true,
10089 /* HasAVX2 */false, DAG, dl);
10090 return DAG.getNode(X86ISD::PCMPGTB, dl, VT, Zeros, R);
10093 // R s>> a === ((R u>> a) ^ m) - m
10094 SDValue Res = DAG.getNode(ISD::SRL, dl, VT, R, Amt);
10095 SmallVector<SDValue, 16> V(16, DAG.getConstant(128 >> ShiftAmt,
10097 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 16);
10098 Res = DAG.getNode(ISD::XOR, dl, VT, Res, Mask);
10099 Res = DAG.getNode(ISD::SUB, dl, VT, Res, Mask);
10103 if (Subtarget->hasAVX2() && VT == MVT::v32i8) {
10104 if (Op.getOpcode() == ISD::SHL) {
10105 // Make a large shift.
10107 DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
10108 DAG.getConstant(Intrinsic::x86_avx2_pslli_w, MVT::i32),
10109 R, DAG.getConstant(ShiftAmt, MVT::i32));
10110 // Zero out the rightmost bits.
10111 SmallVector<SDValue, 32> V(32, DAG.getConstant(uint8_t(-1U << ShiftAmt),
10113 return DAG.getNode(ISD::AND, dl, VT, SHL,
10114 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 32));
10116 if (Op.getOpcode() == ISD::SRL) {
10117 // Make a large shift.
10119 DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
10120 DAG.getConstant(Intrinsic::x86_avx2_psrli_w, MVT::i32),
10121 R, DAG.getConstant(ShiftAmt, MVT::i32));
10122 // Zero out the leftmost bits.
10123 SmallVector<SDValue, 32> V(32, DAG.getConstant(uint8_t(-1U) >> ShiftAmt,
10125 return DAG.getNode(ISD::AND, dl, VT, SRL,
10126 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 32));
10128 if (Op.getOpcode() == ISD::SRA) {
10129 if (ShiftAmt == 7) {
10130 // R s>> 7 === R s< 0
10131 SDValue Zeros = getZeroVector(VT, true /* HasSSE2 */,
10132 true /* HasAVX2 */, DAG, dl);
10133 return DAG.getNode(X86ISD::PCMPGTB, dl, VT, Zeros, R);
10136 // R s>> a === ((R u>> a) ^ m) - m
10137 SDValue Res = DAG.getNode(ISD::SRL, dl, VT, R, Amt);
10138 SmallVector<SDValue, 32> V(32, DAG.getConstant(128 >> ShiftAmt,
10140 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 32);
10141 Res = DAG.getNode(ISD::XOR, dl, VT, Res, Mask);
10142 Res = DAG.getNode(ISD::SUB, dl, VT, Res, Mask);
10149 // Lower SHL with variable shift amount.
10150 if (VT == MVT::v4i32 && Op->getOpcode() == ISD::SHL) {
10151 Op = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
10152 DAG.getConstant(Intrinsic::x86_sse2_pslli_d, MVT::i32),
10153 Op.getOperand(1), DAG.getConstant(23, MVT::i32));
10155 ConstantInt *CI = ConstantInt::get(*Context, APInt(32, 0x3f800000U));
10157 std::vector<Constant*> CV(4, CI);
10158 Constant *C = ConstantVector::get(CV);
10159 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
10160 SDValue Addend = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
10161 MachinePointerInfo::getConstantPool(),
10162 false, false, false, 16);
10164 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Addend);
10165 Op = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, Op);
10166 Op = DAG.getNode(ISD::FP_TO_SINT, dl, VT, Op);
10167 return DAG.getNode(ISD::MUL, dl, VT, Op, R);
10169 if (VT == MVT::v16i8 && Op->getOpcode() == ISD::SHL) {
10170 assert((Subtarget->hasSSE2() || Subtarget->hasAVX()) &&
10171 "Need SSE2 for pslli/pcmpeq.");
10174 Op = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
10175 DAG.getConstant(Intrinsic::x86_sse2_pslli_w, MVT::i32),
10176 Op.getOperand(1), DAG.getConstant(5, MVT::i32));
10178 // Turn 'a' into a mask suitable for VSELECT
10179 SDValue VSelM = DAG.getConstant(0x80, VT);
10180 SDValue OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
10181 OpVSel = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
10182 DAG.getConstant(Intrinsic::x86_sse2_pcmpeq_b, MVT::i32),
10185 SDValue CM1 = DAG.getConstant(0x0f, VT);
10186 SDValue CM2 = DAG.getConstant(0x3f, VT);
10188 // r = VSELECT(r, psllw(r & (char16)15, 4), a);
10189 SDValue M = DAG.getNode(ISD::AND, dl, VT, R, CM1);
10190 M = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
10191 DAG.getConstant(Intrinsic::x86_sse2_pslli_w, MVT::i32), M,
10192 DAG.getConstant(4, MVT::i32));
10193 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel, M, R);
10196 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op);
10197 OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
10198 OpVSel = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
10199 DAG.getConstant(Intrinsic::x86_sse2_pcmpeq_b, MVT::i32),
10202 // r = VSELECT(r, psllw(r & (char16)63, 2), a);
10203 M = DAG.getNode(ISD::AND, dl, VT, R, CM2);
10204 M = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
10205 DAG.getConstant(Intrinsic::x86_sse2_pslli_w, MVT::i32), M,
10206 DAG.getConstant(2, MVT::i32));
10207 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel, M, R);
10210 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op);
10211 OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
10212 OpVSel = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
10213 DAG.getConstant(Intrinsic::x86_sse2_pcmpeq_b, MVT::i32),
10216 // return VSELECT(r, r+r, a);
10217 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel,
10218 DAG.getNode(ISD::ADD, dl, VT, R, R), R);
10222 // Decompose 256-bit shifts into smaller 128-bit shifts.
10223 if (VT.getSizeInBits() == 256) {
10224 int NumElems = VT.getVectorNumElements();
10225 MVT EltVT = VT.getVectorElementType().getSimpleVT();
10226 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
10228 // Extract the two vectors
10229 SDValue V1 = Extract128BitVector(R, DAG.getConstant(0, MVT::i32), DAG, dl);
10230 SDValue V2 = Extract128BitVector(R, DAG.getConstant(NumElems/2, MVT::i32),
10233 // Recreate the shift amount vectors
10234 SDValue Amt1, Amt2;
10235 if (Amt.getOpcode() == ISD::BUILD_VECTOR) {
10236 // Constant shift amount
10237 SmallVector<SDValue, 4> Amt1Csts;
10238 SmallVector<SDValue, 4> Amt2Csts;
10239 for (int i = 0; i < NumElems/2; ++i)
10240 Amt1Csts.push_back(Amt->getOperand(i));
10241 for (int i = NumElems/2; i < NumElems; ++i)
10242 Amt2Csts.push_back(Amt->getOperand(i));
10244 Amt1 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT,
10245 &Amt1Csts[0], NumElems/2);
10246 Amt2 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT,
10247 &Amt2Csts[0], NumElems/2);
10249 // Variable shift amount
10250 Amt1 = Extract128BitVector(Amt, DAG.getConstant(0, MVT::i32), DAG, dl);
10251 Amt2 = Extract128BitVector(Amt, DAG.getConstant(NumElems/2, MVT::i32),
10255 // Issue new vector shifts for the smaller types
10256 V1 = DAG.getNode(Op.getOpcode(), dl, NewVT, V1, Amt1);
10257 V2 = DAG.getNode(Op.getOpcode(), dl, NewVT, V2, Amt2);
10259 // Concatenate the result back
10260 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, V1, V2);
10266 SDValue X86TargetLowering::LowerXALUO(SDValue Op, SelectionDAG &DAG) const {
10267 // Lower the "add/sub/mul with overflow" instruction into a regular ins plus
10268 // a "setcc" instruction that checks the overflow flag. The "brcond" lowering
10269 // looks for this combo and may remove the "setcc" instruction if the "setcc"
10270 // has only one use.
10271 SDNode *N = Op.getNode();
10272 SDValue LHS = N->getOperand(0);
10273 SDValue RHS = N->getOperand(1);
10274 unsigned BaseOp = 0;
10276 DebugLoc DL = Op.getDebugLoc();
10277 switch (Op.getOpcode()) {
10278 default: llvm_unreachable("Unknown ovf instruction!");
10280 // A subtract of one will be selected as a INC. Note that INC doesn't
10281 // set CF, so we can't do this for UADDO.
10282 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
10284 BaseOp = X86ISD::INC;
10285 Cond = X86::COND_O;
10288 BaseOp = X86ISD::ADD;
10289 Cond = X86::COND_O;
10292 BaseOp = X86ISD::ADD;
10293 Cond = X86::COND_B;
10296 // A subtract of one will be selected as a DEC. Note that DEC doesn't
10297 // set CF, so we can't do this for USUBO.
10298 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
10300 BaseOp = X86ISD::DEC;
10301 Cond = X86::COND_O;
10304 BaseOp = X86ISD::SUB;
10305 Cond = X86::COND_O;
10308 BaseOp = X86ISD::SUB;
10309 Cond = X86::COND_B;
10312 BaseOp = X86ISD::SMUL;
10313 Cond = X86::COND_O;
10315 case ISD::UMULO: { // i64, i8 = umulo lhs, rhs --> i64, i64, i32 umul lhs,rhs
10316 SDVTList VTs = DAG.getVTList(N->getValueType(0), N->getValueType(0),
10318 SDValue Sum = DAG.getNode(X86ISD::UMUL, DL, VTs, LHS, RHS);
10321 DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
10322 DAG.getConstant(X86::COND_O, MVT::i32),
10323 SDValue(Sum.getNode(), 2));
10325 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
10329 // Also sets EFLAGS.
10330 SDVTList VTs = DAG.getVTList(N->getValueType(0), MVT::i32);
10331 SDValue Sum = DAG.getNode(BaseOp, DL, VTs, LHS, RHS);
10334 DAG.getNode(X86ISD::SETCC, DL, N->getValueType(1),
10335 DAG.getConstant(Cond, MVT::i32),
10336 SDValue(Sum.getNode(), 1));
10338 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
10341 SDValue X86TargetLowering::LowerSIGN_EXTEND_INREG(SDValue Op,
10342 SelectionDAG &DAG) const {
10343 DebugLoc dl = Op.getDebugLoc();
10344 EVT ExtraVT = cast<VTSDNode>(Op.getOperand(1))->getVT();
10345 EVT VT = Op.getValueType();
10347 if (Subtarget->hasSSE2() && VT.isVector()) {
10348 unsigned BitsDiff = VT.getScalarType().getSizeInBits() -
10349 ExtraVT.getScalarType().getSizeInBits();
10350 SDValue ShAmt = DAG.getConstant(BitsDiff, MVT::i32);
10352 unsigned SHLIntrinsicsID = 0;
10353 unsigned SRAIntrinsicsID = 0;
10354 switch (VT.getSimpleVT().SimpleTy) {
10358 SHLIntrinsicsID = Intrinsic::x86_sse2_pslli_d;
10359 SRAIntrinsicsID = Intrinsic::x86_sse2_psrai_d;
10362 SHLIntrinsicsID = Intrinsic::x86_sse2_pslli_w;
10363 SRAIntrinsicsID = Intrinsic::x86_sse2_psrai_w;
10367 if (!Subtarget->hasAVX())
10369 if (!Subtarget->hasAVX2()) {
10370 // needs to be split
10371 int NumElems = VT.getVectorNumElements();
10372 SDValue Idx0 = DAG.getConstant(0, MVT::i32);
10373 SDValue Idx1 = DAG.getConstant(NumElems/2, MVT::i32);
10375 // Extract the LHS vectors
10376 SDValue LHS = Op.getOperand(0);
10377 SDValue LHS1 = Extract128BitVector(LHS, Idx0, DAG, dl);
10378 SDValue LHS2 = Extract128BitVector(LHS, Idx1, DAG, dl);
10380 MVT EltVT = VT.getVectorElementType().getSimpleVT();
10381 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
10383 EVT ExtraEltVT = ExtraVT.getVectorElementType();
10384 int ExtraNumElems = ExtraVT.getVectorNumElements();
10385 ExtraVT = EVT::getVectorVT(*DAG.getContext(), ExtraEltVT,
10387 SDValue Extra = DAG.getValueType(ExtraVT);
10389 LHS1 = DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, Extra);
10390 LHS2 = DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, Extra);
10392 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, LHS1, LHS2);;
10394 if (VT == MVT::v8i32) {
10395 SHLIntrinsicsID = Intrinsic::x86_avx2_pslli_d;
10396 SRAIntrinsicsID = Intrinsic::x86_avx2_psrai_d;
10398 SHLIntrinsicsID = Intrinsic::x86_avx2_pslli_w;
10399 SRAIntrinsicsID = Intrinsic::x86_avx2_psrai_w;
10403 SDValue Tmp1 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
10404 DAG.getConstant(SHLIntrinsicsID, MVT::i32),
10405 Op.getOperand(0), ShAmt);
10407 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
10408 DAG.getConstant(SRAIntrinsicsID, MVT::i32),
10416 SDValue X86TargetLowering::LowerMEMBARRIER(SDValue Op, SelectionDAG &DAG) const{
10417 DebugLoc dl = Op.getDebugLoc();
10419 // Go ahead and emit the fence on x86-64 even if we asked for no-sse2.
10420 // There isn't any reason to disable it if the target processor supports it.
10421 if (!Subtarget->hasSSE2() && !Subtarget->is64Bit()) {
10422 SDValue Chain = Op.getOperand(0);
10423 SDValue Zero = DAG.getConstant(0, MVT::i32);
10425 DAG.getRegister(X86::ESP, MVT::i32), // Base
10426 DAG.getTargetConstant(1, MVT::i8), // Scale
10427 DAG.getRegister(0, MVT::i32), // Index
10428 DAG.getTargetConstant(0, MVT::i32), // Disp
10429 DAG.getRegister(0, MVT::i32), // Segment.
10434 DAG.getMachineNode(X86::OR32mrLocked, dl, MVT::Other, Ops,
10435 array_lengthof(Ops));
10436 return SDValue(Res, 0);
10439 unsigned isDev = cast<ConstantSDNode>(Op.getOperand(5))->getZExtValue();
10441 return DAG.getNode(X86ISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0));
10443 unsigned Op1 = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
10444 unsigned Op2 = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue();
10445 unsigned Op3 = cast<ConstantSDNode>(Op.getOperand(3))->getZExtValue();
10446 unsigned Op4 = cast<ConstantSDNode>(Op.getOperand(4))->getZExtValue();
10448 // def : Pat<(membarrier (i8 0), (i8 0), (i8 0), (i8 1), (i8 1)), (SFENCE)>;
10449 if (!Op1 && !Op2 && !Op3 && Op4)
10450 return DAG.getNode(X86ISD::SFENCE, dl, MVT::Other, Op.getOperand(0));
10452 // def : Pat<(membarrier (i8 1), (i8 0), (i8 0), (i8 0), (i8 1)), (LFENCE)>;
10453 if (Op1 && !Op2 && !Op3 && !Op4)
10454 return DAG.getNode(X86ISD::LFENCE, dl, MVT::Other, Op.getOperand(0));
10456 // def : Pat<(membarrier (i8 imm), (i8 imm), (i8 imm), (i8 imm), (i8 1)),
10458 return DAG.getNode(X86ISD::MFENCE, dl, MVT::Other, Op.getOperand(0));
10461 SDValue X86TargetLowering::LowerATOMIC_FENCE(SDValue Op,
10462 SelectionDAG &DAG) const {
10463 DebugLoc dl = Op.getDebugLoc();
10464 AtomicOrdering FenceOrdering = static_cast<AtomicOrdering>(
10465 cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue());
10466 SynchronizationScope FenceScope = static_cast<SynchronizationScope>(
10467 cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue());
10469 // The only fence that needs an instruction is a sequentially-consistent
10470 // cross-thread fence.
10471 if (FenceOrdering == SequentiallyConsistent && FenceScope == CrossThread) {
10472 // Use mfence if we have SSE2 or we're on x86-64 (even if we asked for
10473 // no-sse2). There isn't any reason to disable it if the target processor
10475 if (Subtarget->hasSSE2() || Subtarget->is64Bit())
10476 return DAG.getNode(X86ISD::MFENCE, dl, MVT::Other, Op.getOperand(0));
10478 SDValue Chain = Op.getOperand(0);
10479 SDValue Zero = DAG.getConstant(0, MVT::i32);
10481 DAG.getRegister(X86::ESP, MVT::i32), // Base
10482 DAG.getTargetConstant(1, MVT::i8), // Scale
10483 DAG.getRegister(0, MVT::i32), // Index
10484 DAG.getTargetConstant(0, MVT::i32), // Disp
10485 DAG.getRegister(0, MVT::i32), // Segment.
10490 DAG.getMachineNode(X86::OR32mrLocked, dl, MVT::Other, Ops,
10491 array_lengthof(Ops));
10492 return SDValue(Res, 0);
10495 // MEMBARRIER is a compiler barrier; it codegens to a no-op.
10496 return DAG.getNode(X86ISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0));
10500 SDValue X86TargetLowering::LowerCMP_SWAP(SDValue Op, SelectionDAG &DAG) const {
10501 EVT T = Op.getValueType();
10502 DebugLoc DL = Op.getDebugLoc();
10505 switch(T.getSimpleVT().SimpleTy) {
10507 assert(false && "Invalid value type!");
10508 case MVT::i8: Reg = X86::AL; size = 1; break;
10509 case MVT::i16: Reg = X86::AX; size = 2; break;
10510 case MVT::i32: Reg = X86::EAX; size = 4; break;
10512 assert(Subtarget->is64Bit() && "Node not type legal!");
10513 Reg = X86::RAX; size = 8;
10516 SDValue cpIn = DAG.getCopyToReg(Op.getOperand(0), DL, Reg,
10517 Op.getOperand(2), SDValue());
10518 SDValue Ops[] = { cpIn.getValue(0),
10521 DAG.getTargetConstant(size, MVT::i8),
10522 cpIn.getValue(1) };
10523 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
10524 MachineMemOperand *MMO = cast<AtomicSDNode>(Op)->getMemOperand();
10525 SDValue Result = DAG.getMemIntrinsicNode(X86ISD::LCMPXCHG_DAG, DL, Tys,
10528 DAG.getCopyFromReg(Result.getValue(0), DL, Reg, T, Result.getValue(1));
10532 SDValue X86TargetLowering::LowerREADCYCLECOUNTER(SDValue Op,
10533 SelectionDAG &DAG) const {
10534 assert(Subtarget->is64Bit() && "Result not type legalized?");
10535 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
10536 SDValue TheChain = Op.getOperand(0);
10537 DebugLoc dl = Op.getDebugLoc();
10538 SDValue rd = DAG.getNode(X86ISD::RDTSC_DAG, dl, Tys, &TheChain, 1);
10539 SDValue rax = DAG.getCopyFromReg(rd, dl, X86::RAX, MVT::i64, rd.getValue(1));
10540 SDValue rdx = DAG.getCopyFromReg(rax.getValue(1), dl, X86::RDX, MVT::i64,
10542 SDValue Tmp = DAG.getNode(ISD::SHL, dl, MVT::i64, rdx,
10543 DAG.getConstant(32, MVT::i8));
10545 DAG.getNode(ISD::OR, dl, MVT::i64, rax, Tmp),
10548 return DAG.getMergeValues(Ops, 2, dl);
10551 SDValue X86TargetLowering::LowerBITCAST(SDValue Op,
10552 SelectionDAG &DAG) const {
10553 EVT SrcVT = Op.getOperand(0).getValueType();
10554 EVT DstVT = Op.getValueType();
10555 assert(Subtarget->is64Bit() && !Subtarget->hasSSE2() &&
10556 Subtarget->hasMMX() && "Unexpected custom BITCAST");
10557 assert((DstVT == MVT::i64 ||
10558 (DstVT.isVector() && DstVT.getSizeInBits()==64)) &&
10559 "Unexpected custom BITCAST");
10560 // i64 <=> MMX conversions are Legal.
10561 if (SrcVT==MVT::i64 && DstVT.isVector())
10563 if (DstVT==MVT::i64 && SrcVT.isVector())
10565 // MMX <=> MMX conversions are Legal.
10566 if (SrcVT.isVector() && DstVT.isVector())
10568 // All other conversions need to be expanded.
10572 SDValue X86TargetLowering::LowerLOAD_SUB(SDValue Op, SelectionDAG &DAG) const {
10573 SDNode *Node = Op.getNode();
10574 DebugLoc dl = Node->getDebugLoc();
10575 EVT T = Node->getValueType(0);
10576 SDValue negOp = DAG.getNode(ISD::SUB, dl, T,
10577 DAG.getConstant(0, T), Node->getOperand(2));
10578 return DAG.getAtomic(ISD::ATOMIC_LOAD_ADD, dl,
10579 cast<AtomicSDNode>(Node)->getMemoryVT(),
10580 Node->getOperand(0),
10581 Node->getOperand(1), negOp,
10582 cast<AtomicSDNode>(Node)->getSrcValue(),
10583 cast<AtomicSDNode>(Node)->getAlignment(),
10584 cast<AtomicSDNode>(Node)->getOrdering(),
10585 cast<AtomicSDNode>(Node)->getSynchScope());
10588 static SDValue LowerATOMIC_STORE(SDValue Op, SelectionDAG &DAG) {
10589 SDNode *Node = Op.getNode();
10590 DebugLoc dl = Node->getDebugLoc();
10591 EVT VT = cast<AtomicSDNode>(Node)->getMemoryVT();
10593 // Convert seq_cst store -> xchg
10594 // Convert wide store -> swap (-> cmpxchg8b/cmpxchg16b)
10595 // FIXME: On 32-bit, store -> fist or movq would be more efficient
10596 // (The only way to get a 16-byte store is cmpxchg16b)
10597 // FIXME: 16-byte ATOMIC_SWAP isn't actually hooked up at the moment.
10598 if (cast<AtomicSDNode>(Node)->getOrdering() == SequentiallyConsistent ||
10599 !DAG.getTargetLoweringInfo().isTypeLegal(VT)) {
10600 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_SWAP, dl,
10601 cast<AtomicSDNode>(Node)->getMemoryVT(),
10602 Node->getOperand(0),
10603 Node->getOperand(1), Node->getOperand(2),
10604 cast<AtomicSDNode>(Node)->getMemOperand(),
10605 cast<AtomicSDNode>(Node)->getOrdering(),
10606 cast<AtomicSDNode>(Node)->getSynchScope());
10607 return Swap.getValue(1);
10609 // Other atomic stores have a simple pattern.
10613 static SDValue LowerADDC_ADDE_SUBC_SUBE(SDValue Op, SelectionDAG &DAG) {
10614 EVT VT = Op.getNode()->getValueType(0);
10616 // Let legalize expand this if it isn't a legal type yet.
10617 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
10620 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
10623 bool ExtraOp = false;
10624 switch (Op.getOpcode()) {
10625 default: assert(0 && "Invalid code");
10626 case ISD::ADDC: Opc = X86ISD::ADD; break;
10627 case ISD::ADDE: Opc = X86ISD::ADC; ExtraOp = true; break;
10628 case ISD::SUBC: Opc = X86ISD::SUB; break;
10629 case ISD::SUBE: Opc = X86ISD::SBB; ExtraOp = true; break;
10633 return DAG.getNode(Opc, Op->getDebugLoc(), VTs, Op.getOperand(0),
10635 return DAG.getNode(Opc, Op->getDebugLoc(), VTs, Op.getOperand(0),
10636 Op.getOperand(1), Op.getOperand(2));
10639 /// LowerOperation - Provide custom lowering hooks for some operations.
10641 SDValue X86TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
10642 switch (Op.getOpcode()) {
10643 default: llvm_unreachable("Should not custom lower this!");
10644 case ISD::SIGN_EXTEND_INREG: return LowerSIGN_EXTEND_INREG(Op,DAG);
10645 case ISD::MEMBARRIER: return LowerMEMBARRIER(Op,DAG);
10646 case ISD::ATOMIC_FENCE: return LowerATOMIC_FENCE(Op,DAG);
10647 case ISD::ATOMIC_CMP_SWAP: return LowerCMP_SWAP(Op,DAG);
10648 case ISD::ATOMIC_LOAD_SUB: return LowerLOAD_SUB(Op,DAG);
10649 case ISD::ATOMIC_STORE: return LowerATOMIC_STORE(Op,DAG);
10650 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
10651 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG);
10652 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
10653 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
10654 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG);
10655 case ISD::EXTRACT_SUBVECTOR: return LowerEXTRACT_SUBVECTOR(Op, DAG);
10656 case ISD::INSERT_SUBVECTOR: return LowerINSERT_SUBVECTOR(Op, DAG);
10657 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
10658 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
10659 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
10660 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
10661 case ISD::ExternalSymbol: return LowerExternalSymbol(Op, DAG);
10662 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
10663 case ISD::SHL_PARTS:
10664 case ISD::SRA_PARTS:
10665 case ISD::SRL_PARTS: return LowerShiftParts(Op, DAG);
10666 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG);
10667 case ISD::UINT_TO_FP: return LowerUINT_TO_FP(Op, DAG);
10668 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG);
10669 case ISD::FP_TO_UINT: return LowerFP_TO_UINT(Op, DAG);
10670 case ISD::FABS: return LowerFABS(Op, DAG);
10671 case ISD::FNEG: return LowerFNEG(Op, DAG);
10672 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG);
10673 case ISD::FGETSIGN: return LowerFGETSIGN(Op, DAG);
10674 case ISD::SETCC: return LowerSETCC(Op, DAG);
10675 case ISD::SELECT: return LowerSELECT(Op, DAG);
10676 case ISD::BRCOND: return LowerBRCOND(Op, DAG);
10677 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
10678 case ISD::VASTART: return LowerVASTART(Op, DAG);
10679 case ISD::VAARG: return LowerVAARG(Op, DAG);
10680 case ISD::VACOPY: return LowerVACOPY(Op, DAG);
10681 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
10682 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
10683 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
10684 case ISD::FRAME_TO_ARGS_OFFSET:
10685 return LowerFRAME_TO_ARGS_OFFSET(Op, DAG);
10686 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
10687 case ISD::EH_RETURN: return LowerEH_RETURN(Op, DAG);
10688 case ISD::INIT_TRAMPOLINE: return LowerINIT_TRAMPOLINE(Op, DAG);
10689 case ISD::ADJUST_TRAMPOLINE: return LowerADJUST_TRAMPOLINE(Op, DAG);
10690 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
10691 case ISD::CTLZ: return LowerCTLZ(Op, DAG);
10692 case ISD::CTLZ_ZERO_UNDEF: return LowerCTLZ_ZERO_UNDEF(Op, DAG);
10693 case ISD::CTTZ: return LowerCTTZ(Op, DAG);
10694 case ISD::MUL: return LowerMUL(Op, DAG);
10697 case ISD::SHL: return LowerShift(Op, DAG);
10703 case ISD::UMULO: return LowerXALUO(Op, DAG);
10704 case ISD::READCYCLECOUNTER: return LowerREADCYCLECOUNTER(Op, DAG);
10705 case ISD::BITCAST: return LowerBITCAST(Op, DAG);
10709 case ISD::SUBE: return LowerADDC_ADDE_SUBC_SUBE(Op, DAG);
10710 case ISD::ADD: return LowerADD(Op, DAG);
10711 case ISD::SUB: return LowerSUB(Op, DAG);
10715 static void ReplaceATOMIC_LOAD(SDNode *Node,
10716 SmallVectorImpl<SDValue> &Results,
10717 SelectionDAG &DAG) {
10718 DebugLoc dl = Node->getDebugLoc();
10719 EVT VT = cast<AtomicSDNode>(Node)->getMemoryVT();
10721 // Convert wide load -> cmpxchg8b/cmpxchg16b
10722 // FIXME: On 32-bit, load -> fild or movq would be more efficient
10723 // (The only way to get a 16-byte load is cmpxchg16b)
10724 // FIXME: 16-byte ATOMIC_CMP_SWAP isn't actually hooked up at the moment.
10725 SDValue Zero = DAG.getConstant(0, VT);
10726 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_CMP_SWAP, dl, VT,
10727 Node->getOperand(0),
10728 Node->getOperand(1), Zero, Zero,
10729 cast<AtomicSDNode>(Node)->getMemOperand(),
10730 cast<AtomicSDNode>(Node)->getOrdering(),
10731 cast<AtomicSDNode>(Node)->getSynchScope());
10732 Results.push_back(Swap.getValue(0));
10733 Results.push_back(Swap.getValue(1));
10736 void X86TargetLowering::
10737 ReplaceATOMIC_BINARY_64(SDNode *Node, SmallVectorImpl<SDValue>&Results,
10738 SelectionDAG &DAG, unsigned NewOp) const {
10739 DebugLoc dl = Node->getDebugLoc();
10740 assert (Node->getValueType(0) == MVT::i64 &&
10741 "Only know how to expand i64 atomics");
10743 SDValue Chain = Node->getOperand(0);
10744 SDValue In1 = Node->getOperand(1);
10745 SDValue In2L = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
10746 Node->getOperand(2), DAG.getIntPtrConstant(0));
10747 SDValue In2H = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
10748 Node->getOperand(2), DAG.getIntPtrConstant(1));
10749 SDValue Ops[] = { Chain, In1, In2L, In2H };
10750 SDVTList Tys = DAG.getVTList(MVT::i32, MVT::i32, MVT::Other);
10752 DAG.getMemIntrinsicNode(NewOp, dl, Tys, Ops, 4, MVT::i64,
10753 cast<MemSDNode>(Node)->getMemOperand());
10754 SDValue OpsF[] = { Result.getValue(0), Result.getValue(1)};
10755 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, OpsF, 2));
10756 Results.push_back(Result.getValue(2));
10759 /// ReplaceNodeResults - Replace a node with an illegal result type
10760 /// with a new node built out of custom code.
10761 void X86TargetLowering::ReplaceNodeResults(SDNode *N,
10762 SmallVectorImpl<SDValue>&Results,
10763 SelectionDAG &DAG) const {
10764 DebugLoc dl = N->getDebugLoc();
10765 switch (N->getOpcode()) {
10767 assert(false && "Do not know how to custom type legalize this operation!");
10769 case ISD::SIGN_EXTEND_INREG:
10774 // We don't want to expand or promote these.
10776 case ISD::FP_TO_SINT: {
10777 std::pair<SDValue,SDValue> Vals =
10778 FP_TO_INTHelper(SDValue(N, 0), DAG, true);
10779 SDValue FIST = Vals.first, StackSlot = Vals.second;
10780 if (FIST.getNode() != 0) {
10781 EVT VT = N->getValueType(0);
10782 // Return a load from the stack slot.
10783 Results.push_back(DAG.getLoad(VT, dl, FIST, StackSlot,
10784 MachinePointerInfo(),
10785 false, false, false, 0));
10789 case ISD::READCYCLECOUNTER: {
10790 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
10791 SDValue TheChain = N->getOperand(0);
10792 SDValue rd = DAG.getNode(X86ISD::RDTSC_DAG, dl, Tys, &TheChain, 1);
10793 SDValue eax = DAG.getCopyFromReg(rd, dl, X86::EAX, MVT::i32,
10795 SDValue edx = DAG.getCopyFromReg(eax.getValue(1), dl, X86::EDX, MVT::i32,
10797 // Use a buildpair to merge the two 32-bit values into a 64-bit one.
10798 SDValue Ops[] = { eax, edx };
10799 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Ops, 2));
10800 Results.push_back(edx.getValue(1));
10803 case ISD::ATOMIC_CMP_SWAP: {
10804 EVT T = N->getValueType(0);
10805 assert((T == MVT::i64 || T == MVT::i128) && "can only expand cmpxchg pair");
10806 bool Regs64bit = T == MVT::i128;
10807 EVT HalfT = Regs64bit ? MVT::i64 : MVT::i32;
10808 SDValue cpInL, cpInH;
10809 cpInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2),
10810 DAG.getConstant(0, HalfT));
10811 cpInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2),
10812 DAG.getConstant(1, HalfT));
10813 cpInL = DAG.getCopyToReg(N->getOperand(0), dl,
10814 Regs64bit ? X86::RAX : X86::EAX,
10816 cpInH = DAG.getCopyToReg(cpInL.getValue(0), dl,
10817 Regs64bit ? X86::RDX : X86::EDX,
10818 cpInH, cpInL.getValue(1));
10819 SDValue swapInL, swapInH;
10820 swapInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3),
10821 DAG.getConstant(0, HalfT));
10822 swapInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3),
10823 DAG.getConstant(1, HalfT));
10824 swapInL = DAG.getCopyToReg(cpInH.getValue(0), dl,
10825 Regs64bit ? X86::RBX : X86::EBX,
10826 swapInL, cpInH.getValue(1));
10827 swapInH = DAG.getCopyToReg(swapInL.getValue(0), dl,
10828 Regs64bit ? X86::RCX : X86::ECX,
10829 swapInH, swapInL.getValue(1));
10830 SDValue Ops[] = { swapInH.getValue(0),
10832 swapInH.getValue(1) };
10833 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
10834 MachineMemOperand *MMO = cast<AtomicSDNode>(N)->getMemOperand();
10835 unsigned Opcode = Regs64bit ? X86ISD::LCMPXCHG16_DAG :
10836 X86ISD::LCMPXCHG8_DAG;
10837 SDValue Result = DAG.getMemIntrinsicNode(Opcode, dl, Tys,
10839 SDValue cpOutL = DAG.getCopyFromReg(Result.getValue(0), dl,
10840 Regs64bit ? X86::RAX : X86::EAX,
10841 HalfT, Result.getValue(1));
10842 SDValue cpOutH = DAG.getCopyFromReg(cpOutL.getValue(1), dl,
10843 Regs64bit ? X86::RDX : X86::EDX,
10844 HalfT, cpOutL.getValue(2));
10845 SDValue OpsF[] = { cpOutL.getValue(0), cpOutH.getValue(0)};
10846 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, T, OpsF, 2));
10847 Results.push_back(cpOutH.getValue(1));
10850 case ISD::ATOMIC_LOAD_ADD:
10851 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMADD64_DAG);
10853 case ISD::ATOMIC_LOAD_AND:
10854 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMAND64_DAG);
10856 case ISD::ATOMIC_LOAD_NAND:
10857 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMNAND64_DAG);
10859 case ISD::ATOMIC_LOAD_OR:
10860 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMOR64_DAG);
10862 case ISD::ATOMIC_LOAD_SUB:
10863 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMSUB64_DAG);
10865 case ISD::ATOMIC_LOAD_XOR:
10866 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMXOR64_DAG);
10868 case ISD::ATOMIC_SWAP:
10869 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMSWAP64_DAG);
10871 case ISD::ATOMIC_LOAD:
10872 ReplaceATOMIC_LOAD(N, Results, DAG);
10876 const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
10878 default: return NULL;
10879 case X86ISD::BSF: return "X86ISD::BSF";
10880 case X86ISD::BSR: return "X86ISD::BSR";
10881 case X86ISD::SHLD: return "X86ISD::SHLD";
10882 case X86ISD::SHRD: return "X86ISD::SHRD";
10883 case X86ISD::FAND: return "X86ISD::FAND";
10884 case X86ISD::FOR: return "X86ISD::FOR";
10885 case X86ISD::FXOR: return "X86ISD::FXOR";
10886 case X86ISD::FSRL: return "X86ISD::FSRL";
10887 case X86ISD::FILD: return "X86ISD::FILD";
10888 case X86ISD::FILD_FLAG: return "X86ISD::FILD_FLAG";
10889 case X86ISD::FP_TO_INT16_IN_MEM: return "X86ISD::FP_TO_INT16_IN_MEM";
10890 case X86ISD::FP_TO_INT32_IN_MEM: return "X86ISD::FP_TO_INT32_IN_MEM";
10891 case X86ISD::FP_TO_INT64_IN_MEM: return "X86ISD::FP_TO_INT64_IN_MEM";
10892 case X86ISD::FLD: return "X86ISD::FLD";
10893 case X86ISD::FST: return "X86ISD::FST";
10894 case X86ISD::CALL: return "X86ISD::CALL";
10895 case X86ISD::RDTSC_DAG: return "X86ISD::RDTSC_DAG";
10896 case X86ISD::BT: return "X86ISD::BT";
10897 case X86ISD::CMP: return "X86ISD::CMP";
10898 case X86ISD::COMI: return "X86ISD::COMI";
10899 case X86ISD::UCOMI: return "X86ISD::UCOMI";
10900 case X86ISD::SETCC: return "X86ISD::SETCC";
10901 case X86ISD::SETCC_CARRY: return "X86ISD::SETCC_CARRY";
10902 case X86ISD::FSETCCsd: return "X86ISD::FSETCCsd";
10903 case X86ISD::FSETCCss: return "X86ISD::FSETCCss";
10904 case X86ISD::CMOV: return "X86ISD::CMOV";
10905 case X86ISD::BRCOND: return "X86ISD::BRCOND";
10906 case X86ISD::RET_FLAG: return "X86ISD::RET_FLAG";
10907 case X86ISD::REP_STOS: return "X86ISD::REP_STOS";
10908 case X86ISD::REP_MOVS: return "X86ISD::REP_MOVS";
10909 case X86ISD::GlobalBaseReg: return "X86ISD::GlobalBaseReg";
10910 case X86ISD::Wrapper: return "X86ISD::Wrapper";
10911 case X86ISD::WrapperRIP: return "X86ISD::WrapperRIP";
10912 case X86ISD::PEXTRB: return "X86ISD::PEXTRB";
10913 case X86ISD::PEXTRW: return "X86ISD::PEXTRW";
10914 case X86ISD::INSERTPS: return "X86ISD::INSERTPS";
10915 case X86ISD::PINSRB: return "X86ISD::PINSRB";
10916 case X86ISD::PINSRW: return "X86ISD::PINSRW";
10917 case X86ISD::PSHUFB: return "X86ISD::PSHUFB";
10918 case X86ISD::ANDNP: return "X86ISD::ANDNP";
10919 case X86ISD::PSIGN: return "X86ISD::PSIGN";
10920 case X86ISD::BLENDV: return "X86ISD::BLENDV";
10921 case X86ISD::HADD: return "X86ISD::HADD";
10922 case X86ISD::HSUB: return "X86ISD::HSUB";
10923 case X86ISD::FHADD: return "X86ISD::FHADD";
10924 case X86ISD::FHSUB: return "X86ISD::FHSUB";
10925 case X86ISD::FMAX: return "X86ISD::FMAX";
10926 case X86ISD::FMIN: return "X86ISD::FMIN";
10927 case X86ISD::FRSQRT: return "X86ISD::FRSQRT";
10928 case X86ISD::FRCP: return "X86ISD::FRCP";
10929 case X86ISD::TLSADDR: return "X86ISD::TLSADDR";
10930 case X86ISD::TLSCALL: return "X86ISD::TLSCALL";
10931 case X86ISD::EH_RETURN: return "X86ISD::EH_RETURN";
10932 case X86ISD::TC_RETURN: return "X86ISD::TC_RETURN";
10933 case X86ISD::FNSTCW16m: return "X86ISD::FNSTCW16m";
10934 case X86ISD::LCMPXCHG_DAG: return "X86ISD::LCMPXCHG_DAG";
10935 case X86ISD::LCMPXCHG8_DAG: return "X86ISD::LCMPXCHG8_DAG";
10936 case X86ISD::ATOMADD64_DAG: return "X86ISD::ATOMADD64_DAG";
10937 case X86ISD::ATOMSUB64_DAG: return "X86ISD::ATOMSUB64_DAG";
10938 case X86ISD::ATOMOR64_DAG: return "X86ISD::ATOMOR64_DAG";
10939 case X86ISD::ATOMXOR64_DAG: return "X86ISD::ATOMXOR64_DAG";
10940 case X86ISD::ATOMAND64_DAG: return "X86ISD::ATOMAND64_DAG";
10941 case X86ISD::ATOMNAND64_DAG: return "X86ISD::ATOMNAND64_DAG";
10942 case X86ISD::VZEXT_MOVL: return "X86ISD::VZEXT_MOVL";
10943 case X86ISD::VZEXT_LOAD: return "X86ISD::VZEXT_LOAD";
10944 case X86ISD::VSHL: return "X86ISD::VSHL";
10945 case X86ISD::VSRL: return "X86ISD::VSRL";
10946 case X86ISD::CMPPD: return "X86ISD::CMPPD";
10947 case X86ISD::CMPPS: return "X86ISD::CMPPS";
10948 case X86ISD::PCMPEQB: return "X86ISD::PCMPEQB";
10949 case X86ISD::PCMPEQW: return "X86ISD::PCMPEQW";
10950 case X86ISD::PCMPEQD: return "X86ISD::PCMPEQD";
10951 case X86ISD::PCMPEQQ: return "X86ISD::PCMPEQQ";
10952 case X86ISD::PCMPGTB: return "X86ISD::PCMPGTB";
10953 case X86ISD::PCMPGTW: return "X86ISD::PCMPGTW";
10954 case X86ISD::PCMPGTD: return "X86ISD::PCMPGTD";
10955 case X86ISD::PCMPGTQ: return "X86ISD::PCMPGTQ";
10956 case X86ISD::ADD: return "X86ISD::ADD";
10957 case X86ISD::SUB: return "X86ISD::SUB";
10958 case X86ISD::ADC: return "X86ISD::ADC";
10959 case X86ISD::SBB: return "X86ISD::SBB";
10960 case X86ISD::SMUL: return "X86ISD::SMUL";
10961 case X86ISD::UMUL: return "X86ISD::UMUL";
10962 case X86ISD::INC: return "X86ISD::INC";
10963 case X86ISD::DEC: return "X86ISD::DEC";
10964 case X86ISD::OR: return "X86ISD::OR";
10965 case X86ISD::XOR: return "X86ISD::XOR";
10966 case X86ISD::AND: return "X86ISD::AND";
10967 case X86ISD::ANDN: return "X86ISD::ANDN";
10968 case X86ISD::BLSI: return "X86ISD::BLSI";
10969 case X86ISD::BLSMSK: return "X86ISD::BLSMSK";
10970 case X86ISD::BLSR: return "X86ISD::BLSR";
10971 case X86ISD::MUL_IMM: return "X86ISD::MUL_IMM";
10972 case X86ISD::PTEST: return "X86ISD::PTEST";
10973 case X86ISD::TESTP: return "X86ISD::TESTP";
10974 case X86ISD::PALIGN: return "X86ISD::PALIGN";
10975 case X86ISD::PSHUFD: return "X86ISD::PSHUFD";
10976 case X86ISD::PSHUFHW: return "X86ISD::PSHUFHW";
10977 case X86ISD::PSHUFHW_LD: return "X86ISD::PSHUFHW_LD";
10978 case X86ISD::PSHUFLW: return "X86ISD::PSHUFLW";
10979 case X86ISD::PSHUFLW_LD: return "X86ISD::PSHUFLW_LD";
10980 case X86ISD::SHUFP: return "X86ISD::SHUFP";
10981 case X86ISD::MOVLHPS: return "X86ISD::MOVLHPS";
10982 case X86ISD::MOVLHPD: return "X86ISD::MOVLHPD";
10983 case X86ISD::MOVHLPS: return "X86ISD::MOVHLPS";
10984 case X86ISD::MOVLPS: return "X86ISD::MOVLPS";
10985 case X86ISD::MOVLPD: return "X86ISD::MOVLPD";
10986 case X86ISD::MOVDDUP: return "X86ISD::MOVDDUP";
10987 case X86ISD::MOVSHDUP: return "X86ISD::MOVSHDUP";
10988 case X86ISD::MOVSLDUP: return "X86ISD::MOVSLDUP";
10989 case X86ISD::MOVSHDUP_LD: return "X86ISD::MOVSHDUP_LD";
10990 case X86ISD::MOVSLDUP_LD: return "X86ISD::MOVSLDUP_LD";
10991 case X86ISD::MOVSD: return "X86ISD::MOVSD";
10992 case X86ISD::MOVSS: return "X86ISD::MOVSS";
10993 case X86ISD::UNPCKL: return "X86ISD::UNPCKL";
10994 case X86ISD::UNPCKH: return "X86ISD::UNPCKH";
10995 case X86ISD::VBROADCAST: return "X86ISD::VBROADCAST";
10996 case X86ISD::VPERMILP: return "X86ISD::VPERMILP";
10997 case X86ISD::VPERM2X128: return "X86ISD::VPERM2X128";
10998 case X86ISD::VASTART_SAVE_XMM_REGS: return "X86ISD::VASTART_SAVE_XMM_REGS";
10999 case X86ISD::VAARG_64: return "X86ISD::VAARG_64";
11000 case X86ISD::WIN_ALLOCA: return "X86ISD::WIN_ALLOCA";
11001 case X86ISD::MEMBARRIER: return "X86ISD::MEMBARRIER";
11002 case X86ISD::SEG_ALLOCA: return "X86ISD::SEG_ALLOCA";
11006 // isLegalAddressingMode - Return true if the addressing mode represented
11007 // by AM is legal for this target, for a load/store of the specified type.
11008 bool X86TargetLowering::isLegalAddressingMode(const AddrMode &AM,
11010 // X86 supports extremely general addressing modes.
11011 CodeModel::Model M = getTargetMachine().getCodeModel();
11012 Reloc::Model R = getTargetMachine().getRelocationModel();
11014 // X86 allows a sign-extended 32-bit immediate field as a displacement.
11015 if (!X86::isOffsetSuitableForCodeModel(AM.BaseOffs, M, AM.BaseGV != NULL))
11020 Subtarget->ClassifyGlobalReference(AM.BaseGV, getTargetMachine());
11022 // If a reference to this global requires an extra load, we can't fold it.
11023 if (isGlobalStubReference(GVFlags))
11026 // If BaseGV requires a register for the PIC base, we cannot also have a
11027 // BaseReg specified.
11028 if (AM.HasBaseReg && isGlobalRelativeToPICBase(GVFlags))
11031 // If lower 4G is not available, then we must use rip-relative addressing.
11032 if ((M != CodeModel::Small || R != Reloc::Static) &&
11033 Subtarget->is64Bit() && (AM.BaseOffs || AM.Scale > 1))
11037 switch (AM.Scale) {
11043 // These scales always work.
11048 // These scales are formed with basereg+scalereg. Only accept if there is
11053 default: // Other stuff never works.
11061 bool X86TargetLowering::isTruncateFree(Type *Ty1, Type *Ty2) const {
11062 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
11064 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits();
11065 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits();
11066 if (NumBits1 <= NumBits2)
11071 bool X86TargetLowering::isTruncateFree(EVT VT1, EVT VT2) const {
11072 if (!VT1.isInteger() || !VT2.isInteger())
11074 unsigned NumBits1 = VT1.getSizeInBits();
11075 unsigned NumBits2 = VT2.getSizeInBits();
11076 if (NumBits1 <= NumBits2)
11081 bool X86TargetLowering::isZExtFree(Type *Ty1, Type *Ty2) const {
11082 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
11083 return Ty1->isIntegerTy(32) && Ty2->isIntegerTy(64) && Subtarget->is64Bit();
11086 bool X86TargetLowering::isZExtFree(EVT VT1, EVT VT2) const {
11087 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
11088 return VT1 == MVT::i32 && VT2 == MVT::i64 && Subtarget->is64Bit();
11091 bool X86TargetLowering::isNarrowingProfitable(EVT VT1, EVT VT2) const {
11092 // i16 instructions are longer (0x66 prefix) and potentially slower.
11093 return !(VT1 == MVT::i32 && VT2 == MVT::i16);
11096 /// isShuffleMaskLegal - Targets can use this to indicate that they only
11097 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
11098 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
11099 /// are assumed to be legal.
11101 X86TargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M,
11103 // Very little shuffling can be done for 64-bit vectors right now.
11104 if (VT.getSizeInBits() == 64)
11107 // FIXME: pshufb, blends, shifts.
11108 return (VT.getVectorNumElements() == 2 ||
11109 ShuffleVectorSDNode::isSplatMask(&M[0], VT) ||
11110 isMOVLMask(M, VT) ||
11111 isSHUFPMask(M, VT) ||
11112 isPSHUFDMask(M, VT) ||
11113 isPSHUFHWMask(M, VT) ||
11114 isPSHUFLWMask(M, VT) ||
11115 isPALIGNRMask(M, VT, Subtarget->hasSSSE3()) ||
11116 isUNPCKLMask(M, VT, Subtarget->hasAVX2()) ||
11117 isUNPCKHMask(M, VT, Subtarget->hasAVX2()) ||
11118 isUNPCKL_v_undef_Mask(M, VT, Subtarget->hasAVX2()) ||
11119 isUNPCKH_v_undef_Mask(M, VT, Subtarget->hasAVX2()));
11123 X86TargetLowering::isVectorClearMaskLegal(const SmallVectorImpl<int> &Mask,
11125 unsigned NumElts = VT.getVectorNumElements();
11126 // FIXME: This collection of masks seems suspect.
11129 if (NumElts == 4 && VT.getSizeInBits() == 128) {
11130 return (isMOVLMask(Mask, VT) ||
11131 isCommutedMOVLMask(Mask, VT, true) ||
11132 isSHUFPMask(Mask, VT) ||
11133 isSHUFPMask(Mask, VT, /* Commuted */ true));
11138 //===----------------------------------------------------------------------===//
11139 // X86 Scheduler Hooks
11140 //===----------------------------------------------------------------------===//
11142 // private utility function
11143 MachineBasicBlock *
11144 X86TargetLowering::EmitAtomicBitwiseWithCustomInserter(MachineInstr *bInstr,
11145 MachineBasicBlock *MBB,
11152 TargetRegisterClass *RC,
11153 bool invSrc) const {
11154 // For the atomic bitwise operator, we generate
11157 // ld t1 = [bitinstr.addr]
11158 // op t2 = t1, [bitinstr.val]
11160 // lcs dest = [bitinstr.addr], t2 [EAX is implicit]
11162 // fallthrough -->nextMBB
11163 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
11164 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
11165 MachineFunction::iterator MBBIter = MBB;
11168 /// First build the CFG
11169 MachineFunction *F = MBB->getParent();
11170 MachineBasicBlock *thisMBB = MBB;
11171 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB);
11172 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB);
11173 F->insert(MBBIter, newMBB);
11174 F->insert(MBBIter, nextMBB);
11176 // Transfer the remainder of thisMBB and its successor edges to nextMBB.
11177 nextMBB->splice(nextMBB->begin(), thisMBB,
11178 llvm::next(MachineBasicBlock::iterator(bInstr)),
11180 nextMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
11182 // Update thisMBB to fall through to newMBB
11183 thisMBB->addSuccessor(newMBB);
11185 // newMBB jumps to itself and fall through to nextMBB
11186 newMBB->addSuccessor(nextMBB);
11187 newMBB->addSuccessor(newMBB);
11189 // Insert instructions into newMBB based on incoming instruction
11190 assert(bInstr->getNumOperands() < X86::AddrNumOperands + 4 &&
11191 "unexpected number of operands");
11192 DebugLoc dl = bInstr->getDebugLoc();
11193 MachineOperand& destOper = bInstr->getOperand(0);
11194 MachineOperand* argOpers[2 + X86::AddrNumOperands];
11195 int numArgs = bInstr->getNumOperands() - 1;
11196 for (int i=0; i < numArgs; ++i)
11197 argOpers[i] = &bInstr->getOperand(i+1);
11199 // x86 address has 4 operands: base, index, scale, and displacement
11200 int lastAddrIndx = X86::AddrNumOperands - 1; // [0,3]
11201 int valArgIndx = lastAddrIndx + 1;
11203 unsigned t1 = F->getRegInfo().createVirtualRegister(RC);
11204 MachineInstrBuilder MIB = BuildMI(newMBB, dl, TII->get(LoadOpc), t1);
11205 for (int i=0; i <= lastAddrIndx; ++i)
11206 (*MIB).addOperand(*argOpers[i]);
11208 unsigned tt = F->getRegInfo().createVirtualRegister(RC);
11210 MIB = BuildMI(newMBB, dl, TII->get(notOpc), tt).addReg(t1);
11215 unsigned t2 = F->getRegInfo().createVirtualRegister(RC);
11216 assert((argOpers[valArgIndx]->isReg() ||
11217 argOpers[valArgIndx]->isImm()) &&
11218 "invalid operand");
11219 if (argOpers[valArgIndx]->isReg())
11220 MIB = BuildMI(newMBB, dl, TII->get(regOpc), t2);
11222 MIB = BuildMI(newMBB, dl, TII->get(immOpc), t2);
11224 (*MIB).addOperand(*argOpers[valArgIndx]);
11226 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), EAXreg);
11229 MIB = BuildMI(newMBB, dl, TII->get(CXchgOpc));
11230 for (int i=0; i <= lastAddrIndx; ++i)
11231 (*MIB).addOperand(*argOpers[i]);
11233 assert(bInstr->hasOneMemOperand() && "Unexpected number of memoperand");
11234 (*MIB).setMemRefs(bInstr->memoperands_begin(),
11235 bInstr->memoperands_end());
11237 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), destOper.getReg());
11238 MIB.addReg(EAXreg);
11241 BuildMI(newMBB, dl, TII->get(X86::JNE_4)).addMBB(newMBB);
11243 bInstr->eraseFromParent(); // The pseudo instruction is gone now.
11247 // private utility function: 64 bit atomics on 32 bit host.
11248 MachineBasicBlock *
11249 X86TargetLowering::EmitAtomicBit6432WithCustomInserter(MachineInstr *bInstr,
11250 MachineBasicBlock *MBB,
11255 bool invSrc) const {
11256 // For the atomic bitwise operator, we generate
11257 // thisMBB (instructions are in pairs, except cmpxchg8b)
11258 // ld t1,t2 = [bitinstr.addr]
11260 // out1, out2 = phi (thisMBB, t1/t2) (newMBB, t3/t4)
11261 // op t5, t6 <- out1, out2, [bitinstr.val]
11262 // (for SWAP, substitute: mov t5, t6 <- [bitinstr.val])
11263 // mov ECX, EBX <- t5, t6
11264 // mov EAX, EDX <- t1, t2
11265 // cmpxchg8b [bitinstr.addr] [EAX, EDX, EBX, ECX implicit]
11266 // mov t3, t4 <- EAX, EDX
11268 // result in out1, out2
11269 // fallthrough -->nextMBB
11271 const TargetRegisterClass *RC = X86::GR32RegisterClass;
11272 const unsigned LoadOpc = X86::MOV32rm;
11273 const unsigned NotOpc = X86::NOT32r;
11274 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
11275 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
11276 MachineFunction::iterator MBBIter = MBB;
11279 /// First build the CFG
11280 MachineFunction *F = MBB->getParent();
11281 MachineBasicBlock *thisMBB = MBB;
11282 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB);
11283 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB);
11284 F->insert(MBBIter, newMBB);
11285 F->insert(MBBIter, nextMBB);
11287 // Transfer the remainder of thisMBB and its successor edges to nextMBB.
11288 nextMBB->splice(nextMBB->begin(), thisMBB,
11289 llvm::next(MachineBasicBlock::iterator(bInstr)),
11291 nextMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
11293 // Update thisMBB to fall through to newMBB
11294 thisMBB->addSuccessor(newMBB);
11296 // newMBB jumps to itself and fall through to nextMBB
11297 newMBB->addSuccessor(nextMBB);
11298 newMBB->addSuccessor(newMBB);
11300 DebugLoc dl = bInstr->getDebugLoc();
11301 // Insert instructions into newMBB based on incoming instruction
11302 // There are 8 "real" operands plus 9 implicit def/uses, ignored here.
11303 assert(bInstr->getNumOperands() < X86::AddrNumOperands + 14 &&
11304 "unexpected number of operands");
11305 MachineOperand& dest1Oper = bInstr->getOperand(0);
11306 MachineOperand& dest2Oper = bInstr->getOperand(1);
11307 MachineOperand* argOpers[2 + X86::AddrNumOperands];
11308 for (int i=0; i < 2 + X86::AddrNumOperands; ++i) {
11309 argOpers[i] = &bInstr->getOperand(i+2);
11311 // We use some of the operands multiple times, so conservatively just
11312 // clear any kill flags that might be present.
11313 if (argOpers[i]->isReg() && argOpers[i]->isUse())
11314 argOpers[i]->setIsKill(false);
11317 // x86 address has 5 operands: base, index, scale, displacement, and segment.
11318 int lastAddrIndx = X86::AddrNumOperands - 1; // [0,3]
11320 unsigned t1 = F->getRegInfo().createVirtualRegister(RC);
11321 MachineInstrBuilder MIB = BuildMI(thisMBB, dl, TII->get(LoadOpc), t1);
11322 for (int i=0; i <= lastAddrIndx; ++i)
11323 (*MIB).addOperand(*argOpers[i]);
11324 unsigned t2 = F->getRegInfo().createVirtualRegister(RC);
11325 MIB = BuildMI(thisMBB, dl, TII->get(LoadOpc), t2);
11326 // add 4 to displacement.
11327 for (int i=0; i <= lastAddrIndx-2; ++i)
11328 (*MIB).addOperand(*argOpers[i]);
11329 MachineOperand newOp3 = *(argOpers[3]);
11330 if (newOp3.isImm())
11331 newOp3.setImm(newOp3.getImm()+4);
11333 newOp3.setOffset(newOp3.getOffset()+4);
11334 (*MIB).addOperand(newOp3);
11335 (*MIB).addOperand(*argOpers[lastAddrIndx]);
11337 // t3/4 are defined later, at the bottom of the loop
11338 unsigned t3 = F->getRegInfo().createVirtualRegister(RC);
11339 unsigned t4 = F->getRegInfo().createVirtualRegister(RC);
11340 BuildMI(newMBB, dl, TII->get(X86::PHI), dest1Oper.getReg())
11341 .addReg(t1).addMBB(thisMBB).addReg(t3).addMBB(newMBB);
11342 BuildMI(newMBB, dl, TII->get(X86::PHI), dest2Oper.getReg())
11343 .addReg(t2).addMBB(thisMBB).addReg(t4).addMBB(newMBB);
11345 // The subsequent operations should be using the destination registers of
11346 //the PHI instructions.
11348 t1 = F->getRegInfo().createVirtualRegister(RC);
11349 t2 = F->getRegInfo().createVirtualRegister(RC);
11350 MIB = BuildMI(newMBB, dl, TII->get(NotOpc), t1).addReg(dest1Oper.getReg());
11351 MIB = BuildMI(newMBB, dl, TII->get(NotOpc), t2).addReg(dest2Oper.getReg());
11353 t1 = dest1Oper.getReg();
11354 t2 = dest2Oper.getReg();
11357 int valArgIndx = lastAddrIndx + 1;
11358 assert((argOpers[valArgIndx]->isReg() ||
11359 argOpers[valArgIndx]->isImm()) &&
11360 "invalid operand");
11361 unsigned t5 = F->getRegInfo().createVirtualRegister(RC);
11362 unsigned t6 = F->getRegInfo().createVirtualRegister(RC);
11363 if (argOpers[valArgIndx]->isReg())
11364 MIB = BuildMI(newMBB, dl, TII->get(regOpcL), t5);
11366 MIB = BuildMI(newMBB, dl, TII->get(immOpcL), t5);
11367 if (regOpcL != X86::MOV32rr)
11369 (*MIB).addOperand(*argOpers[valArgIndx]);
11370 assert(argOpers[valArgIndx + 1]->isReg() ==
11371 argOpers[valArgIndx]->isReg());
11372 assert(argOpers[valArgIndx + 1]->isImm() ==
11373 argOpers[valArgIndx]->isImm());
11374 if (argOpers[valArgIndx + 1]->isReg())
11375 MIB = BuildMI(newMBB, dl, TII->get(regOpcH), t6);
11377 MIB = BuildMI(newMBB, dl, TII->get(immOpcH), t6);
11378 if (regOpcH != X86::MOV32rr)
11380 (*MIB).addOperand(*argOpers[valArgIndx + 1]);
11382 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::EAX);
11384 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::EDX);
11387 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::EBX);
11389 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::ECX);
11392 MIB = BuildMI(newMBB, dl, TII->get(X86::LCMPXCHG8B));
11393 for (int i=0; i <= lastAddrIndx; ++i)
11394 (*MIB).addOperand(*argOpers[i]);
11396 assert(bInstr->hasOneMemOperand() && "Unexpected number of memoperand");
11397 (*MIB).setMemRefs(bInstr->memoperands_begin(),
11398 bInstr->memoperands_end());
11400 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), t3);
11401 MIB.addReg(X86::EAX);
11402 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), t4);
11403 MIB.addReg(X86::EDX);
11406 BuildMI(newMBB, dl, TII->get(X86::JNE_4)).addMBB(newMBB);
11408 bInstr->eraseFromParent(); // The pseudo instruction is gone now.
11412 // private utility function
11413 MachineBasicBlock *
11414 X86TargetLowering::EmitAtomicMinMaxWithCustomInserter(MachineInstr *mInstr,
11415 MachineBasicBlock *MBB,
11416 unsigned cmovOpc) const {
11417 // For the atomic min/max operator, we generate
11420 // ld t1 = [min/max.addr]
11421 // mov t2 = [min/max.val]
11423 // cmov[cond] t2 = t1
11425 // lcs dest = [bitinstr.addr], t2 [EAX is implicit]
11427 // fallthrough -->nextMBB
11429 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
11430 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
11431 MachineFunction::iterator MBBIter = MBB;
11434 /// First build the CFG
11435 MachineFunction *F = MBB->getParent();
11436 MachineBasicBlock *thisMBB = MBB;
11437 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB);
11438 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB);
11439 F->insert(MBBIter, newMBB);
11440 F->insert(MBBIter, nextMBB);
11442 // Transfer the remainder of thisMBB and its successor edges to nextMBB.
11443 nextMBB->splice(nextMBB->begin(), thisMBB,
11444 llvm::next(MachineBasicBlock::iterator(mInstr)),
11446 nextMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
11448 // Update thisMBB to fall through to newMBB
11449 thisMBB->addSuccessor(newMBB);
11451 // newMBB jumps to newMBB and fall through to nextMBB
11452 newMBB->addSuccessor(nextMBB);
11453 newMBB->addSuccessor(newMBB);
11455 DebugLoc dl = mInstr->getDebugLoc();
11456 // Insert instructions into newMBB based on incoming instruction
11457 assert(mInstr->getNumOperands() < X86::AddrNumOperands + 4 &&
11458 "unexpected number of operands");
11459 MachineOperand& destOper = mInstr->getOperand(0);
11460 MachineOperand* argOpers[2 + X86::AddrNumOperands];
11461 int numArgs = mInstr->getNumOperands() - 1;
11462 for (int i=0; i < numArgs; ++i)
11463 argOpers[i] = &mInstr->getOperand(i+1);
11465 // x86 address has 4 operands: base, index, scale, and displacement
11466 int lastAddrIndx = X86::AddrNumOperands - 1; // [0,3]
11467 int valArgIndx = lastAddrIndx + 1;
11469 unsigned t1 = F->getRegInfo().createVirtualRegister(X86::GR32RegisterClass);
11470 MachineInstrBuilder MIB = BuildMI(newMBB, dl, TII->get(X86::MOV32rm), t1);
11471 for (int i=0; i <= lastAddrIndx; ++i)
11472 (*MIB).addOperand(*argOpers[i]);
11474 // We only support register and immediate values
11475 assert((argOpers[valArgIndx]->isReg() ||
11476 argOpers[valArgIndx]->isImm()) &&
11477 "invalid operand");
11479 unsigned t2 = F->getRegInfo().createVirtualRegister(X86::GR32RegisterClass);
11480 if (argOpers[valArgIndx]->isReg())
11481 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), t2);
11483 MIB = BuildMI(newMBB, dl, TII->get(X86::MOV32rr), t2);
11484 (*MIB).addOperand(*argOpers[valArgIndx]);
11486 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::EAX);
11489 MIB = BuildMI(newMBB, dl, TII->get(X86::CMP32rr));
11494 unsigned t3 = F->getRegInfo().createVirtualRegister(X86::GR32RegisterClass);
11495 MIB = BuildMI(newMBB, dl, TII->get(cmovOpc),t3);
11499 // Cmp and exchange if none has modified the memory location
11500 MIB = BuildMI(newMBB, dl, TII->get(X86::LCMPXCHG32));
11501 for (int i=0; i <= lastAddrIndx; ++i)
11502 (*MIB).addOperand(*argOpers[i]);
11504 assert(mInstr->hasOneMemOperand() && "Unexpected number of memoperand");
11505 (*MIB).setMemRefs(mInstr->memoperands_begin(),
11506 mInstr->memoperands_end());
11508 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), destOper.getReg());
11509 MIB.addReg(X86::EAX);
11512 BuildMI(newMBB, dl, TII->get(X86::JNE_4)).addMBB(newMBB);
11514 mInstr->eraseFromParent(); // The pseudo instruction is gone now.
11518 // FIXME: When we get size specific XMM0 registers, i.e. XMM0_V16I8
11519 // or XMM0_V32I8 in AVX all of this code can be replaced with that
11520 // in the .td file.
11521 MachineBasicBlock *
11522 X86TargetLowering::EmitPCMP(MachineInstr *MI, MachineBasicBlock *BB,
11523 unsigned numArgs, bool memArg) const {
11524 assert(Subtarget->hasSSE42() &&
11525 "Target must have SSE4.2 or AVX features enabled");
11527 DebugLoc dl = MI->getDebugLoc();
11528 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
11530 if (!Subtarget->hasAVX()) {
11532 Opc = numArgs == 3 ? X86::PCMPISTRM128rm : X86::PCMPESTRM128rm;
11534 Opc = numArgs == 3 ? X86::PCMPISTRM128rr : X86::PCMPESTRM128rr;
11537 Opc = numArgs == 3 ? X86::VPCMPISTRM128rm : X86::VPCMPESTRM128rm;
11539 Opc = numArgs == 3 ? X86::VPCMPISTRM128rr : X86::VPCMPESTRM128rr;
11542 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(Opc));
11543 for (unsigned i = 0; i < numArgs; ++i) {
11544 MachineOperand &Op = MI->getOperand(i+1);
11545 if (!(Op.isReg() && Op.isImplicit()))
11546 MIB.addOperand(Op);
11548 BuildMI(*BB, MI, dl,
11549 TII->get(Subtarget->hasAVX() ? X86::VMOVAPSrr : X86::MOVAPSrr),
11550 MI->getOperand(0).getReg())
11551 .addReg(X86::XMM0);
11553 MI->eraseFromParent();
11557 MachineBasicBlock *
11558 X86TargetLowering::EmitMonitor(MachineInstr *MI, MachineBasicBlock *BB) const {
11559 DebugLoc dl = MI->getDebugLoc();
11560 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
11562 // Address into RAX/EAX, other two args into ECX, EDX.
11563 unsigned MemOpc = Subtarget->is64Bit() ? X86::LEA64r : X86::LEA32r;
11564 unsigned MemReg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
11565 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(MemOpc), MemReg);
11566 for (int i = 0; i < X86::AddrNumOperands; ++i)
11567 MIB.addOperand(MI->getOperand(i));
11569 unsigned ValOps = X86::AddrNumOperands;
11570 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::ECX)
11571 .addReg(MI->getOperand(ValOps).getReg());
11572 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::EDX)
11573 .addReg(MI->getOperand(ValOps+1).getReg());
11575 // The instruction doesn't actually take any operands though.
11576 BuildMI(*BB, MI, dl, TII->get(X86::MONITORrrr));
11578 MI->eraseFromParent(); // The pseudo is gone now.
11582 MachineBasicBlock *
11583 X86TargetLowering::EmitMwait(MachineInstr *MI, MachineBasicBlock *BB) const {
11584 DebugLoc dl = MI->getDebugLoc();
11585 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
11587 // First arg in ECX, the second in EAX.
11588 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::ECX)
11589 .addReg(MI->getOperand(0).getReg());
11590 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::EAX)
11591 .addReg(MI->getOperand(1).getReg());
11593 // The instruction doesn't actually take any operands though.
11594 BuildMI(*BB, MI, dl, TII->get(X86::MWAITrr));
11596 MI->eraseFromParent(); // The pseudo is gone now.
11600 MachineBasicBlock *
11601 X86TargetLowering::EmitVAARG64WithCustomInserter(
11603 MachineBasicBlock *MBB) const {
11604 // Emit va_arg instruction on X86-64.
11606 // Operands to this pseudo-instruction:
11607 // 0 ) Output : destination address (reg)
11608 // 1-5) Input : va_list address (addr, i64mem)
11609 // 6 ) ArgSize : Size (in bytes) of vararg type
11610 // 7 ) ArgMode : 0=overflow only, 1=use gp_offset, 2=use fp_offset
11611 // 8 ) Align : Alignment of type
11612 // 9 ) EFLAGS (implicit-def)
11614 assert(MI->getNumOperands() == 10 && "VAARG_64 should have 10 operands!");
11615 assert(X86::AddrNumOperands == 5 && "VAARG_64 assumes 5 address operands");
11617 unsigned DestReg = MI->getOperand(0).getReg();
11618 MachineOperand &Base = MI->getOperand(1);
11619 MachineOperand &Scale = MI->getOperand(2);
11620 MachineOperand &Index = MI->getOperand(3);
11621 MachineOperand &Disp = MI->getOperand(4);
11622 MachineOperand &Segment = MI->getOperand(5);
11623 unsigned ArgSize = MI->getOperand(6).getImm();
11624 unsigned ArgMode = MI->getOperand(7).getImm();
11625 unsigned Align = MI->getOperand(8).getImm();
11627 // Memory Reference
11628 assert(MI->hasOneMemOperand() && "Expected VAARG_64 to have one memoperand");
11629 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
11630 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
11632 // Machine Information
11633 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
11634 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
11635 const TargetRegisterClass *AddrRegClass = getRegClassFor(MVT::i64);
11636 const TargetRegisterClass *OffsetRegClass = getRegClassFor(MVT::i32);
11637 DebugLoc DL = MI->getDebugLoc();
11639 // struct va_list {
11642 // i64 overflow_area (address)
11643 // i64 reg_save_area (address)
11645 // sizeof(va_list) = 24
11646 // alignment(va_list) = 8
11648 unsigned TotalNumIntRegs = 6;
11649 unsigned TotalNumXMMRegs = 8;
11650 bool UseGPOffset = (ArgMode == 1);
11651 bool UseFPOffset = (ArgMode == 2);
11652 unsigned MaxOffset = TotalNumIntRegs * 8 +
11653 (UseFPOffset ? TotalNumXMMRegs * 16 : 0);
11655 /* Align ArgSize to a multiple of 8 */
11656 unsigned ArgSizeA8 = (ArgSize + 7) & ~7;
11657 bool NeedsAlign = (Align > 8);
11659 MachineBasicBlock *thisMBB = MBB;
11660 MachineBasicBlock *overflowMBB;
11661 MachineBasicBlock *offsetMBB;
11662 MachineBasicBlock *endMBB;
11664 unsigned OffsetDestReg = 0; // Argument address computed by offsetMBB
11665 unsigned OverflowDestReg = 0; // Argument address computed by overflowMBB
11666 unsigned OffsetReg = 0;
11668 if (!UseGPOffset && !UseFPOffset) {
11669 // If we only pull from the overflow region, we don't create a branch.
11670 // We don't need to alter control flow.
11671 OffsetDestReg = 0; // unused
11672 OverflowDestReg = DestReg;
11675 overflowMBB = thisMBB;
11678 // First emit code to check if gp_offset (or fp_offset) is below the bound.
11679 // If so, pull the argument from reg_save_area. (branch to offsetMBB)
11680 // If not, pull from overflow_area. (branch to overflowMBB)
11685 // offsetMBB overflowMBB
11690 // Registers for the PHI in endMBB
11691 OffsetDestReg = MRI.createVirtualRegister(AddrRegClass);
11692 OverflowDestReg = MRI.createVirtualRegister(AddrRegClass);
11694 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
11695 MachineFunction *MF = MBB->getParent();
11696 overflowMBB = MF->CreateMachineBasicBlock(LLVM_BB);
11697 offsetMBB = MF->CreateMachineBasicBlock(LLVM_BB);
11698 endMBB = MF->CreateMachineBasicBlock(LLVM_BB);
11700 MachineFunction::iterator MBBIter = MBB;
11703 // Insert the new basic blocks
11704 MF->insert(MBBIter, offsetMBB);
11705 MF->insert(MBBIter, overflowMBB);
11706 MF->insert(MBBIter, endMBB);
11708 // Transfer the remainder of MBB and its successor edges to endMBB.
11709 endMBB->splice(endMBB->begin(), thisMBB,
11710 llvm::next(MachineBasicBlock::iterator(MI)),
11712 endMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
11714 // Make offsetMBB and overflowMBB successors of thisMBB
11715 thisMBB->addSuccessor(offsetMBB);
11716 thisMBB->addSuccessor(overflowMBB);
11718 // endMBB is a successor of both offsetMBB and overflowMBB
11719 offsetMBB->addSuccessor(endMBB);
11720 overflowMBB->addSuccessor(endMBB);
11722 // Load the offset value into a register
11723 OffsetReg = MRI.createVirtualRegister(OffsetRegClass);
11724 BuildMI(thisMBB, DL, TII->get(X86::MOV32rm), OffsetReg)
11728 .addDisp(Disp, UseFPOffset ? 4 : 0)
11729 .addOperand(Segment)
11730 .setMemRefs(MMOBegin, MMOEnd);
11732 // Check if there is enough room left to pull this argument.
11733 BuildMI(thisMBB, DL, TII->get(X86::CMP32ri))
11735 .addImm(MaxOffset + 8 - ArgSizeA8);
11737 // Branch to "overflowMBB" if offset >= max
11738 // Fall through to "offsetMBB" otherwise
11739 BuildMI(thisMBB, DL, TII->get(X86::GetCondBranchFromCond(X86::COND_AE)))
11740 .addMBB(overflowMBB);
11743 // In offsetMBB, emit code to use the reg_save_area.
11745 assert(OffsetReg != 0);
11747 // Read the reg_save_area address.
11748 unsigned RegSaveReg = MRI.createVirtualRegister(AddrRegClass);
11749 BuildMI(offsetMBB, DL, TII->get(X86::MOV64rm), RegSaveReg)
11754 .addOperand(Segment)
11755 .setMemRefs(MMOBegin, MMOEnd);
11757 // Zero-extend the offset
11758 unsigned OffsetReg64 = MRI.createVirtualRegister(AddrRegClass);
11759 BuildMI(offsetMBB, DL, TII->get(X86::SUBREG_TO_REG), OffsetReg64)
11762 .addImm(X86::sub_32bit);
11764 // Add the offset to the reg_save_area to get the final address.
11765 BuildMI(offsetMBB, DL, TII->get(X86::ADD64rr), OffsetDestReg)
11766 .addReg(OffsetReg64)
11767 .addReg(RegSaveReg);
11769 // Compute the offset for the next argument
11770 unsigned NextOffsetReg = MRI.createVirtualRegister(OffsetRegClass);
11771 BuildMI(offsetMBB, DL, TII->get(X86::ADD32ri), NextOffsetReg)
11773 .addImm(UseFPOffset ? 16 : 8);
11775 // Store it back into the va_list.
11776 BuildMI(offsetMBB, DL, TII->get(X86::MOV32mr))
11780 .addDisp(Disp, UseFPOffset ? 4 : 0)
11781 .addOperand(Segment)
11782 .addReg(NextOffsetReg)
11783 .setMemRefs(MMOBegin, MMOEnd);
11786 BuildMI(offsetMBB, DL, TII->get(X86::JMP_4))
11791 // Emit code to use overflow area
11794 // Load the overflow_area address into a register.
11795 unsigned OverflowAddrReg = MRI.createVirtualRegister(AddrRegClass);
11796 BuildMI(overflowMBB, DL, TII->get(X86::MOV64rm), OverflowAddrReg)
11801 .addOperand(Segment)
11802 .setMemRefs(MMOBegin, MMOEnd);
11804 // If we need to align it, do so. Otherwise, just copy the address
11805 // to OverflowDestReg.
11807 // Align the overflow address
11808 assert((Align & (Align-1)) == 0 && "Alignment must be a power of 2");
11809 unsigned TmpReg = MRI.createVirtualRegister(AddrRegClass);
11811 // aligned_addr = (addr + (align-1)) & ~(align-1)
11812 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), TmpReg)
11813 .addReg(OverflowAddrReg)
11816 BuildMI(overflowMBB, DL, TII->get(X86::AND64ri32), OverflowDestReg)
11818 .addImm(~(uint64_t)(Align-1));
11820 BuildMI(overflowMBB, DL, TII->get(TargetOpcode::COPY), OverflowDestReg)
11821 .addReg(OverflowAddrReg);
11824 // Compute the next overflow address after this argument.
11825 // (the overflow address should be kept 8-byte aligned)
11826 unsigned NextAddrReg = MRI.createVirtualRegister(AddrRegClass);
11827 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), NextAddrReg)
11828 .addReg(OverflowDestReg)
11829 .addImm(ArgSizeA8);
11831 // Store the new overflow address.
11832 BuildMI(overflowMBB, DL, TII->get(X86::MOV64mr))
11837 .addOperand(Segment)
11838 .addReg(NextAddrReg)
11839 .setMemRefs(MMOBegin, MMOEnd);
11841 // If we branched, emit the PHI to the front of endMBB.
11843 BuildMI(*endMBB, endMBB->begin(), DL,
11844 TII->get(X86::PHI), DestReg)
11845 .addReg(OffsetDestReg).addMBB(offsetMBB)
11846 .addReg(OverflowDestReg).addMBB(overflowMBB);
11849 // Erase the pseudo instruction
11850 MI->eraseFromParent();
11855 MachineBasicBlock *
11856 X86TargetLowering::EmitVAStartSaveXMMRegsWithCustomInserter(
11858 MachineBasicBlock *MBB) const {
11859 // Emit code to save XMM registers to the stack. The ABI says that the
11860 // number of registers to save is given in %al, so it's theoretically
11861 // possible to do an indirect jump trick to avoid saving all of them,
11862 // however this code takes a simpler approach and just executes all
11863 // of the stores if %al is non-zero. It's less code, and it's probably
11864 // easier on the hardware branch predictor, and stores aren't all that
11865 // expensive anyway.
11867 // Create the new basic blocks. One block contains all the XMM stores,
11868 // and one block is the final destination regardless of whether any
11869 // stores were performed.
11870 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
11871 MachineFunction *F = MBB->getParent();
11872 MachineFunction::iterator MBBIter = MBB;
11874 MachineBasicBlock *XMMSaveMBB = F->CreateMachineBasicBlock(LLVM_BB);
11875 MachineBasicBlock *EndMBB = F->CreateMachineBasicBlock(LLVM_BB);
11876 F->insert(MBBIter, XMMSaveMBB);
11877 F->insert(MBBIter, EndMBB);
11879 // Transfer the remainder of MBB and its successor edges to EndMBB.
11880 EndMBB->splice(EndMBB->begin(), MBB,
11881 llvm::next(MachineBasicBlock::iterator(MI)),
11883 EndMBB->transferSuccessorsAndUpdatePHIs(MBB);
11885 // The original block will now fall through to the XMM save block.
11886 MBB->addSuccessor(XMMSaveMBB);
11887 // The XMMSaveMBB will fall through to the end block.
11888 XMMSaveMBB->addSuccessor(EndMBB);
11890 // Now add the instructions.
11891 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
11892 DebugLoc DL = MI->getDebugLoc();
11894 unsigned CountReg = MI->getOperand(0).getReg();
11895 int64_t RegSaveFrameIndex = MI->getOperand(1).getImm();
11896 int64_t VarArgsFPOffset = MI->getOperand(2).getImm();
11898 if (!Subtarget->isTargetWin64()) {
11899 // If %al is 0, branch around the XMM save block.
11900 BuildMI(MBB, DL, TII->get(X86::TEST8rr)).addReg(CountReg).addReg(CountReg);
11901 BuildMI(MBB, DL, TII->get(X86::JE_4)).addMBB(EndMBB);
11902 MBB->addSuccessor(EndMBB);
11905 unsigned MOVOpc = Subtarget->hasAVX() ? X86::VMOVAPSmr : X86::MOVAPSmr;
11906 // In the XMM save block, save all the XMM argument registers.
11907 for (int i = 3, e = MI->getNumOperands(); i != e; ++i) {
11908 int64_t Offset = (i - 3) * 16 + VarArgsFPOffset;
11909 MachineMemOperand *MMO =
11910 F->getMachineMemOperand(
11911 MachinePointerInfo::getFixedStack(RegSaveFrameIndex, Offset),
11912 MachineMemOperand::MOStore,
11913 /*Size=*/16, /*Align=*/16);
11914 BuildMI(XMMSaveMBB, DL, TII->get(MOVOpc))
11915 .addFrameIndex(RegSaveFrameIndex)
11916 .addImm(/*Scale=*/1)
11917 .addReg(/*IndexReg=*/0)
11918 .addImm(/*Disp=*/Offset)
11919 .addReg(/*Segment=*/0)
11920 .addReg(MI->getOperand(i).getReg())
11921 .addMemOperand(MMO);
11924 MI->eraseFromParent(); // The pseudo instruction is gone now.
11929 MachineBasicBlock *
11930 X86TargetLowering::EmitLoweredSelect(MachineInstr *MI,
11931 MachineBasicBlock *BB) const {
11932 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
11933 DebugLoc DL = MI->getDebugLoc();
11935 // To "insert" a SELECT_CC instruction, we actually have to insert the
11936 // diamond control-flow pattern. The incoming instruction knows the
11937 // destination vreg to set, the condition code register to branch on, the
11938 // true/false values to select between, and a branch opcode to use.
11939 const BasicBlock *LLVM_BB = BB->getBasicBlock();
11940 MachineFunction::iterator It = BB;
11946 // cmpTY ccX, r1, r2
11948 // fallthrough --> copy0MBB
11949 MachineBasicBlock *thisMBB = BB;
11950 MachineFunction *F = BB->getParent();
11951 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
11952 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
11953 F->insert(It, copy0MBB);
11954 F->insert(It, sinkMBB);
11956 // If the EFLAGS register isn't dead in the terminator, then claim that it's
11957 // live into the sink and copy blocks.
11958 if (!MI->killsRegister(X86::EFLAGS)) {
11959 copy0MBB->addLiveIn(X86::EFLAGS);
11960 sinkMBB->addLiveIn(X86::EFLAGS);
11963 // Transfer the remainder of BB and its successor edges to sinkMBB.
11964 sinkMBB->splice(sinkMBB->begin(), BB,
11965 llvm::next(MachineBasicBlock::iterator(MI)),
11967 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
11969 // Add the true and fallthrough blocks as its successors.
11970 BB->addSuccessor(copy0MBB);
11971 BB->addSuccessor(sinkMBB);
11973 // Create the conditional branch instruction.
11975 X86::GetCondBranchFromCond((X86::CondCode)MI->getOperand(3).getImm());
11976 BuildMI(BB, DL, TII->get(Opc)).addMBB(sinkMBB);
11979 // %FalseValue = ...
11980 // # fallthrough to sinkMBB
11981 copy0MBB->addSuccessor(sinkMBB);
11984 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
11986 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
11987 TII->get(X86::PHI), MI->getOperand(0).getReg())
11988 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB)
11989 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
11991 MI->eraseFromParent(); // The pseudo instruction is gone now.
11995 MachineBasicBlock *
11996 X86TargetLowering::EmitLoweredSegAlloca(MachineInstr *MI, MachineBasicBlock *BB,
11997 bool Is64Bit) const {
11998 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
11999 DebugLoc DL = MI->getDebugLoc();
12000 MachineFunction *MF = BB->getParent();
12001 const BasicBlock *LLVM_BB = BB->getBasicBlock();
12003 assert(getTargetMachine().Options.EnableSegmentedStacks);
12005 unsigned TlsReg = Is64Bit ? X86::FS : X86::GS;
12006 unsigned TlsOffset = Is64Bit ? 0x70 : 0x30;
12009 // ... [Till the alloca]
12010 // If stacklet is not large enough, jump to mallocMBB
12013 // Allocate by subtracting from RSP
12014 // Jump to continueMBB
12017 // Allocate by call to runtime
12021 // [rest of original BB]
12024 MachineBasicBlock *mallocMBB = MF->CreateMachineBasicBlock(LLVM_BB);
12025 MachineBasicBlock *bumpMBB = MF->CreateMachineBasicBlock(LLVM_BB);
12026 MachineBasicBlock *continueMBB = MF->CreateMachineBasicBlock(LLVM_BB);
12028 MachineRegisterInfo &MRI = MF->getRegInfo();
12029 const TargetRegisterClass *AddrRegClass =
12030 getRegClassFor(Is64Bit ? MVT::i64:MVT::i32);
12032 unsigned mallocPtrVReg = MRI.createVirtualRegister(AddrRegClass),
12033 bumpSPPtrVReg = MRI.createVirtualRegister(AddrRegClass),
12034 tmpSPVReg = MRI.createVirtualRegister(AddrRegClass),
12035 SPLimitVReg = MRI.createVirtualRegister(AddrRegClass),
12036 sizeVReg = MI->getOperand(1).getReg(),
12037 physSPReg = Is64Bit ? X86::RSP : X86::ESP;
12039 MachineFunction::iterator MBBIter = BB;
12042 MF->insert(MBBIter, bumpMBB);
12043 MF->insert(MBBIter, mallocMBB);
12044 MF->insert(MBBIter, continueMBB);
12046 continueMBB->splice(continueMBB->begin(), BB, llvm::next
12047 (MachineBasicBlock::iterator(MI)), BB->end());
12048 continueMBB->transferSuccessorsAndUpdatePHIs(BB);
12050 // Add code to the main basic block to check if the stack limit has been hit,
12051 // and if so, jump to mallocMBB otherwise to bumpMBB.
12052 BuildMI(BB, DL, TII->get(TargetOpcode::COPY), tmpSPVReg).addReg(physSPReg);
12053 BuildMI(BB, DL, TII->get(Is64Bit ? X86::SUB64rr:X86::SUB32rr), SPLimitVReg)
12054 .addReg(tmpSPVReg).addReg(sizeVReg);
12055 BuildMI(BB, DL, TII->get(Is64Bit ? X86::CMP64mr:X86::CMP32mr))
12056 .addReg(0).addImm(1).addReg(0).addImm(TlsOffset).addReg(TlsReg)
12057 .addReg(SPLimitVReg);
12058 BuildMI(BB, DL, TII->get(X86::JG_4)).addMBB(mallocMBB);
12060 // bumpMBB simply decreases the stack pointer, since we know the current
12061 // stacklet has enough space.
12062 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), physSPReg)
12063 .addReg(SPLimitVReg);
12064 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), bumpSPPtrVReg)
12065 .addReg(SPLimitVReg);
12066 BuildMI(bumpMBB, DL, TII->get(X86::JMP_4)).addMBB(continueMBB);
12068 // Calls into a routine in libgcc to allocate more space from the heap.
12070 BuildMI(mallocMBB, DL, TII->get(X86::MOV64rr), X86::RDI)
12072 BuildMI(mallocMBB, DL, TII->get(X86::CALL64pcrel32))
12073 .addExternalSymbol("__morestack_allocate_stack_space").addReg(X86::RDI);
12075 BuildMI(mallocMBB, DL, TII->get(X86::SUB32ri), physSPReg).addReg(physSPReg)
12077 BuildMI(mallocMBB, DL, TII->get(X86::PUSH32r)).addReg(sizeVReg);
12078 BuildMI(mallocMBB, DL, TII->get(X86::CALLpcrel32))
12079 .addExternalSymbol("__morestack_allocate_stack_space");
12083 BuildMI(mallocMBB, DL, TII->get(X86::ADD32ri), physSPReg).addReg(physSPReg)
12086 BuildMI(mallocMBB, DL, TII->get(TargetOpcode::COPY), mallocPtrVReg)
12087 .addReg(Is64Bit ? X86::RAX : X86::EAX);
12088 BuildMI(mallocMBB, DL, TII->get(X86::JMP_4)).addMBB(continueMBB);
12090 // Set up the CFG correctly.
12091 BB->addSuccessor(bumpMBB);
12092 BB->addSuccessor(mallocMBB);
12093 mallocMBB->addSuccessor(continueMBB);
12094 bumpMBB->addSuccessor(continueMBB);
12096 // Take care of the PHI nodes.
12097 BuildMI(*continueMBB, continueMBB->begin(), DL, TII->get(X86::PHI),
12098 MI->getOperand(0).getReg())
12099 .addReg(mallocPtrVReg).addMBB(mallocMBB)
12100 .addReg(bumpSPPtrVReg).addMBB(bumpMBB);
12102 // Delete the original pseudo instruction.
12103 MI->eraseFromParent();
12106 return continueMBB;
12109 MachineBasicBlock *
12110 X86TargetLowering::EmitLoweredWinAlloca(MachineInstr *MI,
12111 MachineBasicBlock *BB) const {
12112 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
12113 DebugLoc DL = MI->getDebugLoc();
12115 assert(!Subtarget->isTargetEnvMacho());
12117 // The lowering is pretty easy: we're just emitting the call to _alloca. The
12118 // non-trivial part is impdef of ESP.
12120 if (Subtarget->isTargetWin64()) {
12121 if (Subtarget->isTargetCygMing()) {
12122 // ___chkstk(Mingw64):
12123 // Clobbers R10, R11, RAX and EFLAGS.
12125 BuildMI(*BB, MI, DL, TII->get(X86::W64ALLOCA))
12126 .addExternalSymbol("___chkstk")
12127 .addReg(X86::RAX, RegState::Implicit)
12128 .addReg(X86::RSP, RegState::Implicit)
12129 .addReg(X86::RAX, RegState::Define | RegState::Implicit)
12130 .addReg(X86::RSP, RegState::Define | RegState::Implicit)
12131 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
12133 // __chkstk(MSVCRT): does not update stack pointer.
12134 // Clobbers R10, R11 and EFLAGS.
12135 // FIXME: RAX(allocated size) might be reused and not killed.
12136 BuildMI(*BB, MI, DL, TII->get(X86::W64ALLOCA))
12137 .addExternalSymbol("__chkstk")
12138 .addReg(X86::RAX, RegState::Implicit)
12139 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
12140 // RAX has the offset to subtracted from RSP.
12141 BuildMI(*BB, MI, DL, TII->get(X86::SUB64rr), X86::RSP)
12146 const char *StackProbeSymbol =
12147 Subtarget->isTargetWindows() ? "_chkstk" : "_alloca";
12149 BuildMI(*BB, MI, DL, TII->get(X86::CALLpcrel32))
12150 .addExternalSymbol(StackProbeSymbol)
12151 .addReg(X86::EAX, RegState::Implicit)
12152 .addReg(X86::ESP, RegState::Implicit)
12153 .addReg(X86::EAX, RegState::Define | RegState::Implicit)
12154 .addReg(X86::ESP, RegState::Define | RegState::Implicit)
12155 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
12158 MI->eraseFromParent(); // The pseudo instruction is gone now.
12162 MachineBasicBlock *
12163 X86TargetLowering::EmitLoweredTLSCall(MachineInstr *MI,
12164 MachineBasicBlock *BB) const {
12165 // This is pretty easy. We're taking the value that we received from
12166 // our load from the relocation, sticking it in either RDI (x86-64)
12167 // or EAX and doing an indirect call. The return value will then
12168 // be in the normal return register.
12169 const X86InstrInfo *TII
12170 = static_cast<const X86InstrInfo*>(getTargetMachine().getInstrInfo());
12171 DebugLoc DL = MI->getDebugLoc();
12172 MachineFunction *F = BB->getParent();
12174 assert(Subtarget->isTargetDarwin() && "Darwin only instr emitted?");
12175 assert(MI->getOperand(3).isGlobal() && "This should be a global");
12177 if (Subtarget->is64Bit()) {
12178 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
12179 TII->get(X86::MOV64rm), X86::RDI)
12181 .addImm(0).addReg(0)
12182 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
12183 MI->getOperand(3).getTargetFlags())
12185 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL64m));
12186 addDirectMem(MIB, X86::RDI);
12187 } else if (getTargetMachine().getRelocationModel() != Reloc::PIC_) {
12188 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
12189 TII->get(X86::MOV32rm), X86::EAX)
12191 .addImm(0).addReg(0)
12192 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
12193 MI->getOperand(3).getTargetFlags())
12195 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
12196 addDirectMem(MIB, X86::EAX);
12198 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
12199 TII->get(X86::MOV32rm), X86::EAX)
12200 .addReg(TII->getGlobalBaseReg(F))
12201 .addImm(0).addReg(0)
12202 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
12203 MI->getOperand(3).getTargetFlags())
12205 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
12206 addDirectMem(MIB, X86::EAX);
12209 MI->eraseFromParent(); // The pseudo instruction is gone now.
12213 MachineBasicBlock *
12214 X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
12215 MachineBasicBlock *BB) const {
12216 switch (MI->getOpcode()) {
12217 default: assert(0 && "Unexpected instr type to insert");
12218 case X86::TAILJMPd64:
12219 case X86::TAILJMPr64:
12220 case X86::TAILJMPm64:
12221 assert(0 && "TAILJMP64 would not be touched here.");
12222 case X86::TCRETURNdi64:
12223 case X86::TCRETURNri64:
12224 case X86::TCRETURNmi64:
12225 // Defs of TCRETURNxx64 has Win64's callee-saved registers, as subset.
12226 // On AMD64, additional defs should be added before register allocation.
12227 if (!Subtarget->isTargetWin64()) {
12228 MI->addRegisterDefined(X86::RSI);
12229 MI->addRegisterDefined(X86::RDI);
12230 MI->addRegisterDefined(X86::XMM6);
12231 MI->addRegisterDefined(X86::XMM7);
12232 MI->addRegisterDefined(X86::XMM8);
12233 MI->addRegisterDefined(X86::XMM9);
12234 MI->addRegisterDefined(X86::XMM10);
12235 MI->addRegisterDefined(X86::XMM11);
12236 MI->addRegisterDefined(X86::XMM12);
12237 MI->addRegisterDefined(X86::XMM13);
12238 MI->addRegisterDefined(X86::XMM14);
12239 MI->addRegisterDefined(X86::XMM15);
12242 case X86::WIN_ALLOCA:
12243 return EmitLoweredWinAlloca(MI, BB);
12244 case X86::SEG_ALLOCA_32:
12245 return EmitLoweredSegAlloca(MI, BB, false);
12246 case X86::SEG_ALLOCA_64:
12247 return EmitLoweredSegAlloca(MI, BB, true);
12248 case X86::TLSCall_32:
12249 case X86::TLSCall_64:
12250 return EmitLoweredTLSCall(MI, BB);
12251 case X86::CMOV_GR8:
12252 case X86::CMOV_FR32:
12253 case X86::CMOV_FR64:
12254 case X86::CMOV_V4F32:
12255 case X86::CMOV_V2F64:
12256 case X86::CMOV_V2I64:
12257 case X86::CMOV_V8F32:
12258 case X86::CMOV_V4F64:
12259 case X86::CMOV_V4I64:
12260 case X86::CMOV_GR16:
12261 case X86::CMOV_GR32:
12262 case X86::CMOV_RFP32:
12263 case X86::CMOV_RFP64:
12264 case X86::CMOV_RFP80:
12265 return EmitLoweredSelect(MI, BB);
12267 case X86::FP32_TO_INT16_IN_MEM:
12268 case X86::FP32_TO_INT32_IN_MEM:
12269 case X86::FP32_TO_INT64_IN_MEM:
12270 case X86::FP64_TO_INT16_IN_MEM:
12271 case X86::FP64_TO_INT32_IN_MEM:
12272 case X86::FP64_TO_INT64_IN_MEM:
12273 case X86::FP80_TO_INT16_IN_MEM:
12274 case X86::FP80_TO_INT32_IN_MEM:
12275 case X86::FP80_TO_INT64_IN_MEM: {
12276 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
12277 DebugLoc DL = MI->getDebugLoc();
12279 // Change the floating point control register to use "round towards zero"
12280 // mode when truncating to an integer value.
12281 MachineFunction *F = BB->getParent();
12282 int CWFrameIdx = F->getFrameInfo()->CreateStackObject(2, 2, false);
12283 addFrameReference(BuildMI(*BB, MI, DL,
12284 TII->get(X86::FNSTCW16m)), CWFrameIdx);
12286 // Load the old value of the high byte of the control word...
12288 F->getRegInfo().createVirtualRegister(X86::GR16RegisterClass);
12289 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16rm), OldCW),
12292 // Set the high part to be round to zero...
12293 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mi)), CWFrameIdx)
12296 // Reload the modified control word now...
12297 addFrameReference(BuildMI(*BB, MI, DL,
12298 TII->get(X86::FLDCW16m)), CWFrameIdx);
12300 // Restore the memory image of control word to original value
12301 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mr)), CWFrameIdx)
12304 // Get the X86 opcode to use.
12306 switch (MI->getOpcode()) {
12307 default: llvm_unreachable("illegal opcode!");
12308 case X86::FP32_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m32; break;
12309 case X86::FP32_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m32; break;
12310 case X86::FP32_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m32; break;
12311 case X86::FP64_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m64; break;
12312 case X86::FP64_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m64; break;
12313 case X86::FP64_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m64; break;
12314 case X86::FP80_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m80; break;
12315 case X86::FP80_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m80; break;
12316 case X86::FP80_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m80; break;
12320 MachineOperand &Op = MI->getOperand(0);
12322 AM.BaseType = X86AddressMode::RegBase;
12323 AM.Base.Reg = Op.getReg();
12325 AM.BaseType = X86AddressMode::FrameIndexBase;
12326 AM.Base.FrameIndex = Op.getIndex();
12328 Op = MI->getOperand(1);
12330 AM.Scale = Op.getImm();
12331 Op = MI->getOperand(2);
12333 AM.IndexReg = Op.getImm();
12334 Op = MI->getOperand(3);
12335 if (Op.isGlobal()) {
12336 AM.GV = Op.getGlobal();
12338 AM.Disp = Op.getImm();
12340 addFullAddress(BuildMI(*BB, MI, DL, TII->get(Opc)), AM)
12341 .addReg(MI->getOperand(X86::AddrNumOperands).getReg());
12343 // Reload the original control word now.
12344 addFrameReference(BuildMI(*BB, MI, DL,
12345 TII->get(X86::FLDCW16m)), CWFrameIdx);
12347 MI->eraseFromParent(); // The pseudo instruction is gone now.
12350 // String/text processing lowering.
12351 case X86::PCMPISTRM128REG:
12352 case X86::VPCMPISTRM128REG:
12353 return EmitPCMP(MI, BB, 3, false /* in-mem */);
12354 case X86::PCMPISTRM128MEM:
12355 case X86::VPCMPISTRM128MEM:
12356 return EmitPCMP(MI, BB, 3, true /* in-mem */);
12357 case X86::PCMPESTRM128REG:
12358 case X86::VPCMPESTRM128REG:
12359 return EmitPCMP(MI, BB, 5, false /* in mem */);
12360 case X86::PCMPESTRM128MEM:
12361 case X86::VPCMPESTRM128MEM:
12362 return EmitPCMP(MI, BB, 5, true /* in mem */);
12364 // Thread synchronization.
12366 return EmitMonitor(MI, BB);
12368 return EmitMwait(MI, BB);
12370 // Atomic Lowering.
12371 case X86::ATOMAND32:
12372 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND32rr,
12373 X86::AND32ri, X86::MOV32rm,
12375 X86::NOT32r, X86::EAX,
12376 X86::GR32RegisterClass);
12377 case X86::ATOMOR32:
12378 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR32rr,
12379 X86::OR32ri, X86::MOV32rm,
12381 X86::NOT32r, X86::EAX,
12382 X86::GR32RegisterClass);
12383 case X86::ATOMXOR32:
12384 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR32rr,
12385 X86::XOR32ri, X86::MOV32rm,
12387 X86::NOT32r, X86::EAX,
12388 X86::GR32RegisterClass);
12389 case X86::ATOMNAND32:
12390 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND32rr,
12391 X86::AND32ri, X86::MOV32rm,
12393 X86::NOT32r, X86::EAX,
12394 X86::GR32RegisterClass, true);
12395 case X86::ATOMMIN32:
12396 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL32rr);
12397 case X86::ATOMMAX32:
12398 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG32rr);
12399 case X86::ATOMUMIN32:
12400 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB32rr);
12401 case X86::ATOMUMAX32:
12402 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA32rr);
12404 case X86::ATOMAND16:
12405 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND16rr,
12406 X86::AND16ri, X86::MOV16rm,
12408 X86::NOT16r, X86::AX,
12409 X86::GR16RegisterClass);
12410 case X86::ATOMOR16:
12411 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR16rr,
12412 X86::OR16ri, X86::MOV16rm,
12414 X86::NOT16r, X86::AX,
12415 X86::GR16RegisterClass);
12416 case X86::ATOMXOR16:
12417 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR16rr,
12418 X86::XOR16ri, X86::MOV16rm,
12420 X86::NOT16r, X86::AX,
12421 X86::GR16RegisterClass);
12422 case X86::ATOMNAND16:
12423 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND16rr,
12424 X86::AND16ri, X86::MOV16rm,
12426 X86::NOT16r, X86::AX,
12427 X86::GR16RegisterClass, true);
12428 case X86::ATOMMIN16:
12429 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL16rr);
12430 case X86::ATOMMAX16:
12431 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG16rr);
12432 case X86::ATOMUMIN16:
12433 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB16rr);
12434 case X86::ATOMUMAX16:
12435 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA16rr);
12437 case X86::ATOMAND8:
12438 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND8rr,
12439 X86::AND8ri, X86::MOV8rm,
12441 X86::NOT8r, X86::AL,
12442 X86::GR8RegisterClass);
12444 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR8rr,
12445 X86::OR8ri, X86::MOV8rm,
12447 X86::NOT8r, X86::AL,
12448 X86::GR8RegisterClass);
12449 case X86::ATOMXOR8:
12450 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR8rr,
12451 X86::XOR8ri, X86::MOV8rm,
12453 X86::NOT8r, X86::AL,
12454 X86::GR8RegisterClass);
12455 case X86::ATOMNAND8:
12456 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND8rr,
12457 X86::AND8ri, X86::MOV8rm,
12459 X86::NOT8r, X86::AL,
12460 X86::GR8RegisterClass, true);
12461 // FIXME: There are no CMOV8 instructions; MIN/MAX need some other way.
12462 // This group is for 64-bit host.
12463 case X86::ATOMAND64:
12464 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND64rr,
12465 X86::AND64ri32, X86::MOV64rm,
12467 X86::NOT64r, X86::RAX,
12468 X86::GR64RegisterClass);
12469 case X86::ATOMOR64:
12470 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR64rr,
12471 X86::OR64ri32, X86::MOV64rm,
12473 X86::NOT64r, X86::RAX,
12474 X86::GR64RegisterClass);
12475 case X86::ATOMXOR64:
12476 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR64rr,
12477 X86::XOR64ri32, X86::MOV64rm,
12479 X86::NOT64r, X86::RAX,
12480 X86::GR64RegisterClass);
12481 case X86::ATOMNAND64:
12482 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND64rr,
12483 X86::AND64ri32, X86::MOV64rm,
12485 X86::NOT64r, X86::RAX,
12486 X86::GR64RegisterClass, true);
12487 case X86::ATOMMIN64:
12488 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL64rr);
12489 case X86::ATOMMAX64:
12490 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG64rr);
12491 case X86::ATOMUMIN64:
12492 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB64rr);
12493 case X86::ATOMUMAX64:
12494 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA64rr);
12496 // This group does 64-bit operations on a 32-bit host.
12497 case X86::ATOMAND6432:
12498 return EmitAtomicBit6432WithCustomInserter(MI, BB,
12499 X86::AND32rr, X86::AND32rr,
12500 X86::AND32ri, X86::AND32ri,
12502 case X86::ATOMOR6432:
12503 return EmitAtomicBit6432WithCustomInserter(MI, BB,
12504 X86::OR32rr, X86::OR32rr,
12505 X86::OR32ri, X86::OR32ri,
12507 case X86::ATOMXOR6432:
12508 return EmitAtomicBit6432WithCustomInserter(MI, BB,
12509 X86::XOR32rr, X86::XOR32rr,
12510 X86::XOR32ri, X86::XOR32ri,
12512 case X86::ATOMNAND6432:
12513 return EmitAtomicBit6432WithCustomInserter(MI, BB,
12514 X86::AND32rr, X86::AND32rr,
12515 X86::AND32ri, X86::AND32ri,
12517 case X86::ATOMADD6432:
12518 return EmitAtomicBit6432WithCustomInserter(MI, BB,
12519 X86::ADD32rr, X86::ADC32rr,
12520 X86::ADD32ri, X86::ADC32ri,
12522 case X86::ATOMSUB6432:
12523 return EmitAtomicBit6432WithCustomInserter(MI, BB,
12524 X86::SUB32rr, X86::SBB32rr,
12525 X86::SUB32ri, X86::SBB32ri,
12527 case X86::ATOMSWAP6432:
12528 return EmitAtomicBit6432WithCustomInserter(MI, BB,
12529 X86::MOV32rr, X86::MOV32rr,
12530 X86::MOV32ri, X86::MOV32ri,
12532 case X86::VASTART_SAVE_XMM_REGS:
12533 return EmitVAStartSaveXMMRegsWithCustomInserter(MI, BB);
12535 case X86::VAARG_64:
12536 return EmitVAARG64WithCustomInserter(MI, BB);
12540 //===----------------------------------------------------------------------===//
12541 // X86 Optimization Hooks
12542 //===----------------------------------------------------------------------===//
12544 void X86TargetLowering::computeMaskedBitsForTargetNode(const SDValue Op,
12548 const SelectionDAG &DAG,
12549 unsigned Depth) const {
12550 unsigned Opc = Op.getOpcode();
12551 assert((Opc >= ISD::BUILTIN_OP_END ||
12552 Opc == ISD::INTRINSIC_WO_CHAIN ||
12553 Opc == ISD::INTRINSIC_W_CHAIN ||
12554 Opc == ISD::INTRINSIC_VOID) &&
12555 "Should use MaskedValueIsZero if you don't know whether Op"
12556 " is a target node!");
12558 KnownZero = KnownOne = APInt(Mask.getBitWidth(), 0); // Don't know anything.
12572 // These nodes' second result is a boolean.
12573 if (Op.getResNo() == 0)
12576 case X86ISD::SETCC:
12577 KnownZero |= APInt::getHighBitsSet(Mask.getBitWidth(),
12578 Mask.getBitWidth() - 1);
12580 case ISD::INTRINSIC_WO_CHAIN: {
12581 unsigned IntId = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
12582 unsigned NumLoBits = 0;
12585 case Intrinsic::x86_sse_movmsk_ps:
12586 case Intrinsic::x86_avx_movmsk_ps_256:
12587 case Intrinsic::x86_sse2_movmsk_pd:
12588 case Intrinsic::x86_avx_movmsk_pd_256:
12589 case Intrinsic::x86_mmx_pmovmskb:
12590 case Intrinsic::x86_sse2_pmovmskb_128:
12591 case Intrinsic::x86_avx2_pmovmskb: {
12592 // High bits of movmskp{s|d}, pmovmskb are known zero.
12594 case Intrinsic::x86_sse_movmsk_ps: NumLoBits = 4; break;
12595 case Intrinsic::x86_avx_movmsk_ps_256: NumLoBits = 8; break;
12596 case Intrinsic::x86_sse2_movmsk_pd: NumLoBits = 2; break;
12597 case Intrinsic::x86_avx_movmsk_pd_256: NumLoBits = 4; break;
12598 case Intrinsic::x86_mmx_pmovmskb: NumLoBits = 8; break;
12599 case Intrinsic::x86_sse2_pmovmskb_128: NumLoBits = 16; break;
12600 case Intrinsic::x86_avx2_pmovmskb: NumLoBits = 32; break;
12602 KnownZero = APInt::getHighBitsSet(Mask.getBitWidth(),
12603 Mask.getBitWidth() - NumLoBits);
12612 unsigned X86TargetLowering::ComputeNumSignBitsForTargetNode(SDValue Op,
12613 unsigned Depth) const {
12614 // SETCC_CARRY sets the dest to ~0 for true or 0 for false.
12615 if (Op.getOpcode() == X86ISD::SETCC_CARRY)
12616 return Op.getValueType().getScalarType().getSizeInBits();
12622 /// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the
12623 /// node is a GlobalAddress + offset.
12624 bool X86TargetLowering::isGAPlusOffset(SDNode *N,
12625 const GlobalValue* &GA,
12626 int64_t &Offset) const {
12627 if (N->getOpcode() == X86ISD::Wrapper) {
12628 if (isa<GlobalAddressSDNode>(N->getOperand(0))) {
12629 GA = cast<GlobalAddressSDNode>(N->getOperand(0))->getGlobal();
12630 Offset = cast<GlobalAddressSDNode>(N->getOperand(0))->getOffset();
12634 return TargetLowering::isGAPlusOffset(N, GA, Offset);
12637 /// isShuffleHigh128VectorInsertLow - Checks whether the shuffle node is the
12638 /// same as extracting the high 128-bit part of 256-bit vector and then
12639 /// inserting the result into the low part of a new 256-bit vector
12640 static bool isShuffleHigh128VectorInsertLow(ShuffleVectorSDNode *SVOp) {
12641 EVT VT = SVOp->getValueType(0);
12642 int NumElems = VT.getVectorNumElements();
12644 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
12645 for (int i = 0, j = NumElems/2; i < NumElems/2; ++i, ++j)
12646 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) ||
12647 SVOp->getMaskElt(j) >= 0)
12653 /// isShuffleLow128VectorInsertHigh - Checks whether the shuffle node is the
12654 /// same as extracting the low 128-bit part of 256-bit vector and then
12655 /// inserting the result into the high part of a new 256-bit vector
12656 static bool isShuffleLow128VectorInsertHigh(ShuffleVectorSDNode *SVOp) {
12657 EVT VT = SVOp->getValueType(0);
12658 int NumElems = VT.getVectorNumElements();
12660 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
12661 for (int i = NumElems/2, j = 0; i < NumElems; ++i, ++j)
12662 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) ||
12663 SVOp->getMaskElt(j) >= 0)
12669 /// PerformShuffleCombine256 - Performs shuffle combines for 256-bit vectors.
12670 static SDValue PerformShuffleCombine256(SDNode *N, SelectionDAG &DAG,
12671 TargetLowering::DAGCombinerInfo &DCI,
12673 DebugLoc dl = N->getDebugLoc();
12674 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
12675 SDValue V1 = SVOp->getOperand(0);
12676 SDValue V2 = SVOp->getOperand(1);
12677 EVT VT = SVOp->getValueType(0);
12678 int NumElems = VT.getVectorNumElements();
12680 if (V1.getOpcode() == ISD::CONCAT_VECTORS &&
12681 V2.getOpcode() == ISD::CONCAT_VECTORS) {
12685 // V UNDEF BUILD_VECTOR UNDEF
12687 // CONCAT_VECTOR CONCAT_VECTOR
12690 // RESULT: V + zero extended
12692 if (V2.getOperand(0).getOpcode() != ISD::BUILD_VECTOR ||
12693 V2.getOperand(1).getOpcode() != ISD::UNDEF ||
12694 V1.getOperand(1).getOpcode() != ISD::UNDEF)
12697 if (!ISD::isBuildVectorAllZeros(V2.getOperand(0).getNode()))
12700 // To match the shuffle mask, the first half of the mask should
12701 // be exactly the first vector, and all the rest a splat with the
12702 // first element of the second one.
12703 for (int i = 0; i < NumElems/2; ++i)
12704 if (!isUndefOrEqual(SVOp->getMaskElt(i), i) ||
12705 !isUndefOrEqual(SVOp->getMaskElt(i+NumElems/2), NumElems))
12708 // If V1 is coming from a vector load then just fold to a VZEXT_LOAD.
12709 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(V1.getOperand(0))) {
12710 SDVTList Tys = DAG.getVTList(MVT::v4i64, MVT::Other);
12711 SDValue Ops[] = { Ld->getChain(), Ld->getBasePtr() };
12713 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, dl, Tys, Ops, 2,
12715 Ld->getPointerInfo(),
12716 Ld->getAlignment(),
12717 false/*isVolatile*/, true/*ReadMem*/,
12718 false/*WriteMem*/);
12719 return DAG.getNode(ISD::BITCAST, dl, VT, ResNode);
12722 // Emit a zeroed vector and insert the desired subvector on its
12724 SDValue Zeros = getZeroVector(VT, true /* HasSSE2 */, HasAVX2, DAG, dl);
12725 SDValue InsV = Insert128BitVector(Zeros, V1.getOperand(0),
12726 DAG.getConstant(0, MVT::i32), DAG, dl);
12727 return DCI.CombineTo(N, InsV);
12730 //===--------------------------------------------------------------------===//
12731 // Combine some shuffles into subvector extracts and inserts:
12734 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
12735 if (isShuffleHigh128VectorInsertLow(SVOp)) {
12736 SDValue V = Extract128BitVector(V1, DAG.getConstant(NumElems/2, MVT::i32),
12738 SDValue InsV = Insert128BitVector(DAG.getNode(ISD::UNDEF, dl, VT),
12739 V, DAG.getConstant(0, MVT::i32), DAG, dl);
12740 return DCI.CombineTo(N, InsV);
12743 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
12744 if (isShuffleLow128VectorInsertHigh(SVOp)) {
12745 SDValue V = Extract128BitVector(V1, DAG.getConstant(0, MVT::i32), DAG, dl);
12746 SDValue InsV = Insert128BitVector(DAG.getNode(ISD::UNDEF, dl, VT),
12747 V, DAG.getConstant(NumElems/2, MVT::i32), DAG, dl);
12748 return DCI.CombineTo(N, InsV);
12754 /// PerformShuffleCombine - Performs several different shuffle combines.
12755 static SDValue PerformShuffleCombine(SDNode *N, SelectionDAG &DAG,
12756 TargetLowering::DAGCombinerInfo &DCI,
12757 const X86Subtarget *Subtarget) {
12758 DebugLoc dl = N->getDebugLoc();
12759 EVT VT = N->getValueType(0);
12761 // Don't create instructions with illegal types after legalize types has run.
12762 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
12763 if (!DCI.isBeforeLegalize() && !TLI.isTypeLegal(VT.getVectorElementType()))
12766 // Combine 256-bit vector shuffles. This is only profitable when in AVX mode
12767 if (Subtarget->hasAVX() && VT.getSizeInBits() == 256 &&
12768 N->getOpcode() == ISD::VECTOR_SHUFFLE)
12769 return PerformShuffleCombine256(N, DAG, DCI, Subtarget->hasAVX2());
12771 // Only handle 128 wide vector from here on.
12772 if (VT.getSizeInBits() != 128)
12775 // Combine a vector_shuffle that is equal to build_vector load1, load2, load3,
12776 // load4, <0, 1, 2, 3> into a 128-bit load if the load addresses are
12777 // consecutive, non-overlapping, and in the right order.
12778 SmallVector<SDValue, 16> Elts;
12779 for (unsigned i = 0, e = VT.getVectorNumElements(); i != e; ++i)
12780 Elts.push_back(getShuffleScalarElt(N, i, DAG, 0));
12782 return EltsFromConsecutiveLoads(VT, Elts, dl, DAG);
12785 /// PerformEXTRACT_VECTOR_ELTCombine - Detect vector gather/scatter index
12786 /// generation and convert it from being a bunch of shuffles and extracts
12787 /// to a simple store and scalar loads to extract the elements.
12788 static SDValue PerformEXTRACT_VECTOR_ELTCombine(SDNode *N, SelectionDAG &DAG,
12789 const TargetLowering &TLI) {
12790 SDValue InputVector = N->getOperand(0);
12792 // Only operate on vectors of 4 elements, where the alternative shuffling
12793 // gets to be more expensive.
12794 if (InputVector.getValueType() != MVT::v4i32)
12797 // Check whether every use of InputVector is an EXTRACT_VECTOR_ELT with a
12798 // single use which is a sign-extend or zero-extend, and all elements are
12800 SmallVector<SDNode *, 4> Uses;
12801 unsigned ExtractedElements = 0;
12802 for (SDNode::use_iterator UI = InputVector.getNode()->use_begin(),
12803 UE = InputVector.getNode()->use_end(); UI != UE; ++UI) {
12804 if (UI.getUse().getResNo() != InputVector.getResNo())
12807 SDNode *Extract = *UI;
12808 if (Extract->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
12811 if (Extract->getValueType(0) != MVT::i32)
12813 if (!Extract->hasOneUse())
12815 if (Extract->use_begin()->getOpcode() != ISD::SIGN_EXTEND &&
12816 Extract->use_begin()->getOpcode() != ISD::ZERO_EXTEND)
12818 if (!isa<ConstantSDNode>(Extract->getOperand(1)))
12821 // Record which element was extracted.
12822 ExtractedElements |=
12823 1 << cast<ConstantSDNode>(Extract->getOperand(1))->getZExtValue();
12825 Uses.push_back(Extract);
12828 // If not all the elements were used, this may not be worthwhile.
12829 if (ExtractedElements != 15)
12832 // Ok, we've now decided to do the transformation.
12833 DebugLoc dl = InputVector.getDebugLoc();
12835 // Store the value to a temporary stack slot.
12836 SDValue StackPtr = DAG.CreateStackTemporary(InputVector.getValueType());
12837 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, InputVector, StackPtr,
12838 MachinePointerInfo(), false, false, 0);
12840 // Replace each use (extract) with a load of the appropriate element.
12841 for (SmallVectorImpl<SDNode *>::iterator UI = Uses.begin(),
12842 UE = Uses.end(); UI != UE; ++UI) {
12843 SDNode *Extract = *UI;
12845 // cOMpute the element's address.
12846 SDValue Idx = Extract->getOperand(1);
12848 InputVector.getValueType().getVectorElementType().getSizeInBits()/8;
12849 uint64_t Offset = EltSize * cast<ConstantSDNode>(Idx)->getZExtValue();
12850 SDValue OffsetVal = DAG.getConstant(Offset, TLI.getPointerTy());
12852 SDValue ScalarAddr = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(),
12853 StackPtr, OffsetVal);
12855 // Load the scalar.
12856 SDValue LoadScalar = DAG.getLoad(Extract->getValueType(0), dl, Ch,
12857 ScalarAddr, MachinePointerInfo(),
12858 false, false, false, 0);
12860 // Replace the exact with the load.
12861 DAG.ReplaceAllUsesOfValueWith(SDValue(Extract, 0), LoadScalar);
12864 // The replacement was made in place; don't return anything.
12868 /// PerformSELECTCombine - Do target-specific dag combines on SELECT and VSELECT
12870 static SDValue PerformSELECTCombine(SDNode *N, SelectionDAG &DAG,
12871 const X86Subtarget *Subtarget) {
12872 DebugLoc DL = N->getDebugLoc();
12873 SDValue Cond = N->getOperand(0);
12874 // Get the LHS/RHS of the select.
12875 SDValue LHS = N->getOperand(1);
12876 SDValue RHS = N->getOperand(2);
12877 EVT VT = LHS.getValueType();
12879 // If we have SSE[12] support, try to form min/max nodes. SSE min/max
12880 // instructions match the semantics of the common C idiom x<y?x:y but not
12881 // x<=y?x:y, because of how they handle negative zero (which can be
12882 // ignored in unsafe-math mode).
12883 if (Cond.getOpcode() == ISD::SETCC && VT.isFloatingPoint() &&
12884 VT != MVT::f80 && DAG.getTargetLoweringInfo().isTypeLegal(VT) &&
12885 (Subtarget->hasSSE2() ||
12886 (Subtarget->hasSSE1() && VT.getScalarType() == MVT::f32))) {
12887 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
12889 unsigned Opcode = 0;
12890 // Check for x CC y ? x : y.
12891 if (DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
12892 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
12896 // Converting this to a min would handle NaNs incorrectly, and swapping
12897 // the operands would cause it to handle comparisons between positive
12898 // and negative zero incorrectly.
12899 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
12900 if (!DAG.getTarget().Options.UnsafeFPMath &&
12901 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
12903 std::swap(LHS, RHS);
12905 Opcode = X86ISD::FMIN;
12908 // Converting this to a min would handle comparisons between positive
12909 // and negative zero incorrectly.
12910 if (!DAG.getTarget().Options.UnsafeFPMath &&
12911 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
12913 Opcode = X86ISD::FMIN;
12916 // Converting this to a min would handle both negative zeros and NaNs
12917 // incorrectly, but we can swap the operands to fix both.
12918 std::swap(LHS, RHS);
12922 Opcode = X86ISD::FMIN;
12926 // Converting this to a max would handle comparisons between positive
12927 // and negative zero incorrectly.
12928 if (!DAG.getTarget().Options.UnsafeFPMath &&
12929 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
12931 Opcode = X86ISD::FMAX;
12934 // Converting this to a max would handle NaNs incorrectly, and swapping
12935 // the operands would cause it to handle comparisons between positive
12936 // and negative zero incorrectly.
12937 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
12938 if (!DAG.getTarget().Options.UnsafeFPMath &&
12939 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
12941 std::swap(LHS, RHS);
12943 Opcode = X86ISD::FMAX;
12946 // Converting this to a max would handle both negative zeros and NaNs
12947 // incorrectly, but we can swap the operands to fix both.
12948 std::swap(LHS, RHS);
12952 Opcode = X86ISD::FMAX;
12955 // Check for x CC y ? y : x -- a min/max with reversed arms.
12956 } else if (DAG.isEqualTo(LHS, Cond.getOperand(1)) &&
12957 DAG.isEqualTo(RHS, Cond.getOperand(0))) {
12961 // Converting this to a min would handle comparisons between positive
12962 // and negative zero incorrectly, and swapping the operands would
12963 // cause it to handle NaNs incorrectly.
12964 if (!DAG.getTarget().Options.UnsafeFPMath &&
12965 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS))) {
12966 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
12968 std::swap(LHS, RHS);
12970 Opcode = X86ISD::FMIN;
12973 // Converting this to a min would handle NaNs incorrectly.
12974 if (!DAG.getTarget().Options.UnsafeFPMath &&
12975 (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)))
12977 Opcode = X86ISD::FMIN;
12980 // Converting this to a min would handle both negative zeros and NaNs
12981 // incorrectly, but we can swap the operands to fix both.
12982 std::swap(LHS, RHS);
12986 Opcode = X86ISD::FMIN;
12990 // Converting this to a max would handle NaNs incorrectly.
12991 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
12993 Opcode = X86ISD::FMAX;
12996 // Converting this to a max would handle comparisons between positive
12997 // and negative zero incorrectly, and swapping the operands would
12998 // cause it to handle NaNs incorrectly.
12999 if (!DAG.getTarget().Options.UnsafeFPMath &&
13000 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS)) {
13001 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
13003 std::swap(LHS, RHS);
13005 Opcode = X86ISD::FMAX;
13008 // Converting this to a max would handle both negative zeros and NaNs
13009 // incorrectly, but we can swap the operands to fix both.
13010 std::swap(LHS, RHS);
13014 Opcode = X86ISD::FMAX;
13020 return DAG.getNode(Opcode, DL, N->getValueType(0), LHS, RHS);
13023 // If this is a select between two integer constants, try to do some
13025 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(LHS)) {
13026 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(RHS))
13027 // Don't do this for crazy integer types.
13028 if (DAG.getTargetLoweringInfo().isTypeLegal(LHS.getValueType())) {
13029 // If this is efficiently invertible, canonicalize the LHSC/RHSC values
13030 // so that TrueC (the true value) is larger than FalseC.
13031 bool NeedsCondInvert = false;
13033 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue()) &&
13034 // Efficiently invertible.
13035 (Cond.getOpcode() == ISD::SETCC || // setcc -> invertible.
13036 (Cond.getOpcode() == ISD::XOR && // xor(X, C) -> invertible.
13037 isa<ConstantSDNode>(Cond.getOperand(1))))) {
13038 NeedsCondInvert = true;
13039 std::swap(TrueC, FalseC);
13042 // Optimize C ? 8 : 0 -> zext(C) << 3. Likewise for any pow2/0.
13043 if (FalseC->getAPIntValue() == 0 &&
13044 TrueC->getAPIntValue().isPowerOf2()) {
13045 if (NeedsCondInvert) // Invert the condition if needed.
13046 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
13047 DAG.getConstant(1, Cond.getValueType()));
13049 // Zero extend the condition if needed.
13050 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, LHS.getValueType(), Cond);
13052 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
13053 return DAG.getNode(ISD::SHL, DL, LHS.getValueType(), Cond,
13054 DAG.getConstant(ShAmt, MVT::i8));
13057 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst.
13058 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
13059 if (NeedsCondInvert) // Invert the condition if needed.
13060 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
13061 DAG.getConstant(1, Cond.getValueType()));
13063 // Zero extend the condition if needed.
13064 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
13065 FalseC->getValueType(0), Cond);
13066 return DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
13067 SDValue(FalseC, 0));
13070 // Optimize cases that will turn into an LEA instruction. This requires
13071 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
13072 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
13073 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
13074 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
13076 bool isFastMultiplier = false;
13078 switch ((unsigned char)Diff) {
13080 case 1: // result = add base, cond
13081 case 2: // result = lea base( , cond*2)
13082 case 3: // result = lea base(cond, cond*2)
13083 case 4: // result = lea base( , cond*4)
13084 case 5: // result = lea base(cond, cond*4)
13085 case 8: // result = lea base( , cond*8)
13086 case 9: // result = lea base(cond, cond*8)
13087 isFastMultiplier = true;
13092 if (isFastMultiplier) {
13093 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
13094 if (NeedsCondInvert) // Invert the condition if needed.
13095 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
13096 DAG.getConstant(1, Cond.getValueType()));
13098 // Zero extend the condition if needed.
13099 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
13101 // Scale the condition by the difference.
13103 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
13104 DAG.getConstant(Diff, Cond.getValueType()));
13106 // Add the base if non-zero.
13107 if (FalseC->getAPIntValue() != 0)
13108 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
13109 SDValue(FalseC, 0));
13116 // Canonicalize max and min:
13117 // (x > y) ? x : y -> (x >= y) ? x : y
13118 // (x < y) ? x : y -> (x <= y) ? x : y
13119 // This allows use of COND_S / COND_NS (see TranslateX86CC) which eliminates
13120 // the need for an extra compare
13121 // against zero. e.g.
13122 // (x - y) > 0 : (x - y) ? 0 -> (x - y) >= 0 : (x - y) ? 0
13124 // testl %edi, %edi
13126 // cmovgl %edi, %eax
13130 // cmovsl %eax, %edi
13131 if (N->getOpcode() == ISD::SELECT && Cond.getOpcode() == ISD::SETCC &&
13132 DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
13133 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
13134 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
13139 ISD::CondCode NewCC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGE;
13140 Cond = DAG.getSetCC(Cond.getDebugLoc(), Cond.getValueType(),
13141 Cond.getOperand(0), Cond.getOperand(1), NewCC);
13142 return DAG.getNode(ISD::SELECT, DL, VT, Cond, LHS, RHS);
13150 /// Optimize X86ISD::CMOV [LHS, RHS, CONDCODE (e.g. X86::COND_NE), CONDVAL]
13151 static SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG,
13152 TargetLowering::DAGCombinerInfo &DCI) {
13153 DebugLoc DL = N->getDebugLoc();
13155 // If the flag operand isn't dead, don't touch this CMOV.
13156 if (N->getNumValues() == 2 && !SDValue(N, 1).use_empty())
13159 SDValue FalseOp = N->getOperand(0);
13160 SDValue TrueOp = N->getOperand(1);
13161 X86::CondCode CC = (X86::CondCode)N->getConstantOperandVal(2);
13162 SDValue Cond = N->getOperand(3);
13163 if (CC == X86::COND_E || CC == X86::COND_NE) {
13164 switch (Cond.getOpcode()) {
13168 // If operand of BSR / BSF are proven never zero, then ZF cannot be set.
13169 if (DAG.isKnownNeverZero(Cond.getOperand(0)))
13170 return (CC == X86::COND_E) ? FalseOp : TrueOp;
13174 // If this is a select between two integer constants, try to do some
13175 // optimizations. Note that the operands are ordered the opposite of SELECT
13177 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(TrueOp)) {
13178 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(FalseOp)) {
13179 // Canonicalize the TrueC/FalseC values so that TrueC (the true value) is
13180 // larger than FalseC (the false value).
13181 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue())) {
13182 CC = X86::GetOppositeBranchCondition(CC);
13183 std::swap(TrueC, FalseC);
13186 // Optimize C ? 8 : 0 -> zext(setcc(C)) << 3. Likewise for any pow2/0.
13187 // This is efficient for any integer data type (including i8/i16) and
13189 if (FalseC->getAPIntValue() == 0 && TrueC->getAPIntValue().isPowerOf2()) {
13190 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
13191 DAG.getConstant(CC, MVT::i8), Cond);
13193 // Zero extend the condition if needed.
13194 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, TrueC->getValueType(0), Cond);
13196 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
13197 Cond = DAG.getNode(ISD::SHL, DL, Cond.getValueType(), Cond,
13198 DAG.getConstant(ShAmt, MVT::i8));
13199 if (N->getNumValues() == 2) // Dead flag value?
13200 return DCI.CombineTo(N, Cond, SDValue());
13204 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst. This is efficient
13205 // for any integer data type, including i8/i16.
13206 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
13207 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
13208 DAG.getConstant(CC, MVT::i8), Cond);
13210 // Zero extend the condition if needed.
13211 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
13212 FalseC->getValueType(0), Cond);
13213 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
13214 SDValue(FalseC, 0));
13216 if (N->getNumValues() == 2) // Dead flag value?
13217 return DCI.CombineTo(N, Cond, SDValue());
13221 // Optimize cases that will turn into an LEA instruction. This requires
13222 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
13223 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
13224 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
13225 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
13227 bool isFastMultiplier = false;
13229 switch ((unsigned char)Diff) {
13231 case 1: // result = add base, cond
13232 case 2: // result = lea base( , cond*2)
13233 case 3: // result = lea base(cond, cond*2)
13234 case 4: // result = lea base( , cond*4)
13235 case 5: // result = lea base(cond, cond*4)
13236 case 8: // result = lea base( , cond*8)
13237 case 9: // result = lea base(cond, cond*8)
13238 isFastMultiplier = true;
13243 if (isFastMultiplier) {
13244 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
13245 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
13246 DAG.getConstant(CC, MVT::i8), Cond);
13247 // Zero extend the condition if needed.
13248 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
13250 // Scale the condition by the difference.
13252 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
13253 DAG.getConstant(Diff, Cond.getValueType()));
13255 // Add the base if non-zero.
13256 if (FalseC->getAPIntValue() != 0)
13257 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
13258 SDValue(FalseC, 0));
13259 if (N->getNumValues() == 2) // Dead flag value?
13260 return DCI.CombineTo(N, Cond, SDValue());
13270 /// PerformMulCombine - Optimize a single multiply with constant into two
13271 /// in order to implement it with two cheaper instructions, e.g.
13272 /// LEA + SHL, LEA + LEA.
13273 static SDValue PerformMulCombine(SDNode *N, SelectionDAG &DAG,
13274 TargetLowering::DAGCombinerInfo &DCI) {
13275 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer())
13278 EVT VT = N->getValueType(0);
13279 if (VT != MVT::i64)
13282 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
13285 uint64_t MulAmt = C->getZExtValue();
13286 if (isPowerOf2_64(MulAmt) || MulAmt == 3 || MulAmt == 5 || MulAmt == 9)
13289 uint64_t MulAmt1 = 0;
13290 uint64_t MulAmt2 = 0;
13291 if ((MulAmt % 9) == 0) {
13293 MulAmt2 = MulAmt / 9;
13294 } else if ((MulAmt % 5) == 0) {
13296 MulAmt2 = MulAmt / 5;
13297 } else if ((MulAmt % 3) == 0) {
13299 MulAmt2 = MulAmt / 3;
13302 (isPowerOf2_64(MulAmt2) || MulAmt2 == 3 || MulAmt2 == 5 || MulAmt2 == 9)){
13303 DebugLoc DL = N->getDebugLoc();
13305 if (isPowerOf2_64(MulAmt2) &&
13306 !(N->hasOneUse() && N->use_begin()->getOpcode() == ISD::ADD))
13307 // If second multiplifer is pow2, issue it first. We want the multiply by
13308 // 3, 5, or 9 to be folded into the addressing mode unless the lone use
13310 std::swap(MulAmt1, MulAmt2);
13313 if (isPowerOf2_64(MulAmt1))
13314 NewMul = DAG.getNode(ISD::SHL, DL, VT, N->getOperand(0),
13315 DAG.getConstant(Log2_64(MulAmt1), MVT::i8));
13317 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, N->getOperand(0),
13318 DAG.getConstant(MulAmt1, VT));
13320 if (isPowerOf2_64(MulAmt2))
13321 NewMul = DAG.getNode(ISD::SHL, DL, VT, NewMul,
13322 DAG.getConstant(Log2_64(MulAmt2), MVT::i8));
13324 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, NewMul,
13325 DAG.getConstant(MulAmt2, VT));
13327 // Do not add new nodes to DAG combiner worklist.
13328 DCI.CombineTo(N, NewMul, false);
13333 static SDValue PerformSHLCombine(SDNode *N, SelectionDAG &DAG) {
13334 SDValue N0 = N->getOperand(0);
13335 SDValue N1 = N->getOperand(1);
13336 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
13337 EVT VT = N0.getValueType();
13339 // fold (shl (and (setcc_c), c1), c2) -> (and setcc_c, (c1 << c2))
13340 // since the result of setcc_c is all zero's or all ones.
13341 if (VT.isInteger() && !VT.isVector() &&
13342 N1C && N0.getOpcode() == ISD::AND &&
13343 N0.getOperand(1).getOpcode() == ISD::Constant) {
13344 SDValue N00 = N0.getOperand(0);
13345 if (N00.getOpcode() == X86ISD::SETCC_CARRY ||
13346 ((N00.getOpcode() == ISD::ANY_EXTEND ||
13347 N00.getOpcode() == ISD::ZERO_EXTEND) &&
13348 N00.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY)) {
13349 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
13350 APInt ShAmt = N1C->getAPIntValue();
13351 Mask = Mask.shl(ShAmt);
13353 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT,
13354 N00, DAG.getConstant(Mask, VT));
13359 // Hardware support for vector shifts is sparse which makes us scalarize the
13360 // vector operations in many cases. Also, on sandybridge ADD is faster than
13362 // (shl V, 1) -> add V,V
13363 if (isSplatVector(N1.getNode())) {
13364 assert(N0.getValueType().isVector() && "Invalid vector shift type");
13365 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1->getOperand(0));
13366 // We shift all of the values by one. In many cases we do not have
13367 // hardware support for this operation. This is better expressed as an ADD
13369 if (N1C && (1 == N1C->getZExtValue())) {
13370 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N0, N0);
13377 /// PerformShiftCombine - Transforms vector shift nodes to use vector shifts
13379 static SDValue PerformShiftCombine(SDNode* N, SelectionDAG &DAG,
13380 const X86Subtarget *Subtarget) {
13381 EVT VT = N->getValueType(0);
13382 if (N->getOpcode() == ISD::SHL) {
13383 SDValue V = PerformSHLCombine(N, DAG);
13384 if (V.getNode()) return V;
13387 // On X86 with SSE2 support, we can transform this to a vector shift if
13388 // all elements are shifted by the same amount. We can't do this in legalize
13389 // because the a constant vector is typically transformed to a constant pool
13390 // so we have no knowledge of the shift amount.
13391 if (!Subtarget->hasSSE2())
13394 if (VT != MVT::v2i64 && VT != MVT::v4i32 && VT != MVT::v8i16 &&
13395 (!Subtarget->hasAVX2() ||
13396 (VT != MVT::v4i64 && VT != MVT::v8i32 && VT != MVT::v16i16)))
13399 SDValue ShAmtOp = N->getOperand(1);
13400 EVT EltVT = VT.getVectorElementType();
13401 DebugLoc DL = N->getDebugLoc();
13402 SDValue BaseShAmt = SDValue();
13403 if (ShAmtOp.getOpcode() == ISD::BUILD_VECTOR) {
13404 unsigned NumElts = VT.getVectorNumElements();
13406 for (; i != NumElts; ++i) {
13407 SDValue Arg = ShAmtOp.getOperand(i);
13408 if (Arg.getOpcode() == ISD::UNDEF) continue;
13412 for (; i != NumElts; ++i) {
13413 SDValue Arg = ShAmtOp.getOperand(i);
13414 if (Arg.getOpcode() == ISD::UNDEF) continue;
13415 if (Arg != BaseShAmt) {
13419 } else if (ShAmtOp.getOpcode() == ISD::VECTOR_SHUFFLE &&
13420 cast<ShuffleVectorSDNode>(ShAmtOp)->isSplat()) {
13421 SDValue InVec = ShAmtOp.getOperand(0);
13422 if (InVec.getOpcode() == ISD::BUILD_VECTOR) {
13423 unsigned NumElts = InVec.getValueType().getVectorNumElements();
13425 for (; i != NumElts; ++i) {
13426 SDValue Arg = InVec.getOperand(i);
13427 if (Arg.getOpcode() == ISD::UNDEF) continue;
13431 } else if (InVec.getOpcode() == ISD::INSERT_VECTOR_ELT) {
13432 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(InVec.getOperand(2))) {
13433 unsigned SplatIdx= cast<ShuffleVectorSDNode>(ShAmtOp)->getSplatIndex();
13434 if (C->getZExtValue() == SplatIdx)
13435 BaseShAmt = InVec.getOperand(1);
13438 if (BaseShAmt.getNode() == 0)
13439 BaseShAmt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, EltVT, ShAmtOp,
13440 DAG.getIntPtrConstant(0));
13444 // The shift amount is an i32.
13445 if (EltVT.bitsGT(MVT::i32))
13446 BaseShAmt = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, BaseShAmt);
13447 else if (EltVT.bitsLT(MVT::i32))
13448 BaseShAmt = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i32, BaseShAmt);
13450 // The shift amount is identical so we can do a vector shift.
13451 SDValue ValOp = N->getOperand(0);
13452 switch (N->getOpcode()) {
13454 llvm_unreachable("Unknown shift opcode!");
13457 if (VT == MVT::v2i64)
13458 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
13459 DAG.getConstant(Intrinsic::x86_sse2_pslli_q, MVT::i32),
13461 if (VT == MVT::v4i32)
13462 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
13463 DAG.getConstant(Intrinsic::x86_sse2_pslli_d, MVT::i32),
13465 if (VT == MVT::v8i16)
13466 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
13467 DAG.getConstant(Intrinsic::x86_sse2_pslli_w, MVT::i32),
13469 if (VT == MVT::v4i64)
13470 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
13471 DAG.getConstant(Intrinsic::x86_avx2_pslli_q, MVT::i32),
13473 if (VT == MVT::v8i32)
13474 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
13475 DAG.getConstant(Intrinsic::x86_avx2_pslli_d, MVT::i32),
13477 if (VT == MVT::v16i16)
13478 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
13479 DAG.getConstant(Intrinsic::x86_avx2_pslli_w, MVT::i32),
13483 if (VT == MVT::v4i32)
13484 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
13485 DAG.getConstant(Intrinsic::x86_sse2_psrai_d, MVT::i32),
13487 if (VT == MVT::v8i16)
13488 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
13489 DAG.getConstant(Intrinsic::x86_sse2_psrai_w, MVT::i32),
13491 if (VT == MVT::v8i32)
13492 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
13493 DAG.getConstant(Intrinsic::x86_avx2_psrai_d, MVT::i32),
13495 if (VT == MVT::v16i16)
13496 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
13497 DAG.getConstant(Intrinsic::x86_avx2_psrai_w, MVT::i32),
13501 if (VT == MVT::v2i64)
13502 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
13503 DAG.getConstant(Intrinsic::x86_sse2_psrli_q, MVT::i32),
13505 if (VT == MVT::v4i32)
13506 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
13507 DAG.getConstant(Intrinsic::x86_sse2_psrli_d, MVT::i32),
13509 if (VT == MVT::v8i16)
13510 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
13511 DAG.getConstant(Intrinsic::x86_sse2_psrli_w, MVT::i32),
13513 if (VT == MVT::v4i64)
13514 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
13515 DAG.getConstant(Intrinsic::x86_avx2_psrli_q, MVT::i32),
13517 if (VT == MVT::v8i32)
13518 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
13519 DAG.getConstant(Intrinsic::x86_avx2_psrli_d, MVT::i32),
13521 if (VT == MVT::v16i16)
13522 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
13523 DAG.getConstant(Intrinsic::x86_avx2_psrli_w, MVT::i32),
13531 // CMPEQCombine - Recognize the distinctive (AND (setcc ...) (setcc ..))
13532 // where both setccs reference the same FP CMP, and rewrite for CMPEQSS
13533 // and friends. Likewise for OR -> CMPNEQSS.
13534 static SDValue CMPEQCombine(SDNode *N, SelectionDAG &DAG,
13535 TargetLowering::DAGCombinerInfo &DCI,
13536 const X86Subtarget *Subtarget) {
13539 // SSE1 supports CMP{eq|ne}SS, and SSE2 added CMP{eq|ne}SD, but
13540 // we're requiring SSE2 for both.
13541 if (Subtarget->hasSSE2() && isAndOrOfSetCCs(SDValue(N, 0U), opcode)) {
13542 SDValue N0 = N->getOperand(0);
13543 SDValue N1 = N->getOperand(1);
13544 SDValue CMP0 = N0->getOperand(1);
13545 SDValue CMP1 = N1->getOperand(1);
13546 DebugLoc DL = N->getDebugLoc();
13548 // The SETCCs should both refer to the same CMP.
13549 if (CMP0.getOpcode() != X86ISD::CMP || CMP0 != CMP1)
13552 SDValue CMP00 = CMP0->getOperand(0);
13553 SDValue CMP01 = CMP0->getOperand(1);
13554 EVT VT = CMP00.getValueType();
13556 if (VT == MVT::f32 || VT == MVT::f64) {
13557 bool ExpectingFlags = false;
13558 // Check for any users that want flags:
13559 for (SDNode::use_iterator UI = N->use_begin(),
13561 !ExpectingFlags && UI != UE; ++UI)
13562 switch (UI->getOpcode()) {
13567 ExpectingFlags = true;
13569 case ISD::CopyToReg:
13570 case ISD::SIGN_EXTEND:
13571 case ISD::ZERO_EXTEND:
13572 case ISD::ANY_EXTEND:
13576 if (!ExpectingFlags) {
13577 enum X86::CondCode cc0 = (enum X86::CondCode)N0.getConstantOperandVal(0);
13578 enum X86::CondCode cc1 = (enum X86::CondCode)N1.getConstantOperandVal(0);
13580 if (cc1 == X86::COND_E || cc1 == X86::COND_NE) {
13581 X86::CondCode tmp = cc0;
13586 if ((cc0 == X86::COND_E && cc1 == X86::COND_NP) ||
13587 (cc0 == X86::COND_NE && cc1 == X86::COND_P)) {
13588 bool is64BitFP = (CMP00.getValueType() == MVT::f64);
13589 X86ISD::NodeType NTOperator = is64BitFP ?
13590 X86ISD::FSETCCsd : X86ISD::FSETCCss;
13591 // FIXME: need symbolic constants for these magic numbers.
13592 // See X86ATTInstPrinter.cpp:printSSECC().
13593 unsigned x86cc = (cc0 == X86::COND_E) ? 0 : 4;
13594 SDValue OnesOrZeroesF = DAG.getNode(NTOperator, DL, MVT::f32, CMP00, CMP01,
13595 DAG.getConstant(x86cc, MVT::i8));
13596 SDValue OnesOrZeroesI = DAG.getNode(ISD::BITCAST, DL, MVT::i32,
13598 SDValue ANDed = DAG.getNode(ISD::AND, DL, MVT::i32, OnesOrZeroesI,
13599 DAG.getConstant(1, MVT::i32));
13600 SDValue OneBitOfTruth = DAG.getNode(ISD::TRUNCATE, DL, MVT::i8, ANDed);
13601 return OneBitOfTruth;
13609 /// CanFoldXORWithAllOnes - Test whether the XOR operand is a AllOnes vector
13610 /// so it can be folded inside ANDNP.
13611 static bool CanFoldXORWithAllOnes(const SDNode *N) {
13612 EVT VT = N->getValueType(0);
13614 // Match direct AllOnes for 128 and 256-bit vectors
13615 if (ISD::isBuildVectorAllOnes(N))
13618 // Look through a bit convert.
13619 if (N->getOpcode() == ISD::BITCAST)
13620 N = N->getOperand(0).getNode();
13622 // Sometimes the operand may come from a insert_subvector building a 256-bit
13624 if (VT.getSizeInBits() == 256 &&
13625 N->getOpcode() == ISD::INSERT_SUBVECTOR) {
13626 SDValue V1 = N->getOperand(0);
13627 SDValue V2 = N->getOperand(1);
13629 if (V1.getOpcode() == ISD::INSERT_SUBVECTOR &&
13630 V1.getOperand(0).getOpcode() == ISD::UNDEF &&
13631 ISD::isBuildVectorAllOnes(V1.getOperand(1).getNode()) &&
13632 ISD::isBuildVectorAllOnes(V2.getNode()))
13639 static SDValue PerformAndCombine(SDNode *N, SelectionDAG &DAG,
13640 TargetLowering::DAGCombinerInfo &DCI,
13641 const X86Subtarget *Subtarget) {
13642 if (DCI.isBeforeLegalizeOps())
13645 SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget);
13649 EVT VT = N->getValueType(0);
13651 // Create ANDN, BLSI, and BLSR instructions
13652 // BLSI is X & (-X)
13653 // BLSR is X & (X-1)
13654 if (Subtarget->hasBMI() && (VT == MVT::i32 || VT == MVT::i64)) {
13655 SDValue N0 = N->getOperand(0);
13656 SDValue N1 = N->getOperand(1);
13657 DebugLoc DL = N->getDebugLoc();
13659 // Check LHS for not
13660 if (N0.getOpcode() == ISD::XOR && isAllOnes(N0.getOperand(1)))
13661 return DAG.getNode(X86ISD::ANDN, DL, VT, N0.getOperand(0), N1);
13662 // Check RHS for not
13663 if (N1.getOpcode() == ISD::XOR && isAllOnes(N1.getOperand(1)))
13664 return DAG.getNode(X86ISD::ANDN, DL, VT, N1.getOperand(0), N0);
13666 // Check LHS for neg
13667 if (N0.getOpcode() == ISD::SUB && N0.getOperand(1) == N1 &&
13668 isZero(N0.getOperand(0)))
13669 return DAG.getNode(X86ISD::BLSI, DL, VT, N1);
13671 // Check RHS for neg
13672 if (N1.getOpcode() == ISD::SUB && N1.getOperand(1) == N0 &&
13673 isZero(N1.getOperand(0)))
13674 return DAG.getNode(X86ISD::BLSI, DL, VT, N0);
13676 // Check LHS for X-1
13677 if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1 &&
13678 isAllOnes(N0.getOperand(1)))
13679 return DAG.getNode(X86ISD::BLSR, DL, VT, N1);
13681 // Check RHS for X-1
13682 if (N1.getOpcode() == ISD::ADD && N1.getOperand(0) == N0 &&
13683 isAllOnes(N1.getOperand(1)))
13684 return DAG.getNode(X86ISD::BLSR, DL, VT, N0);
13689 // Want to form ANDNP nodes:
13690 // 1) In the hopes of then easily combining them with OR and AND nodes
13691 // to form PBLEND/PSIGN.
13692 // 2) To match ANDN packed intrinsics
13693 if (VT != MVT::v2i64 && VT != MVT::v4i64)
13696 SDValue N0 = N->getOperand(0);
13697 SDValue N1 = N->getOperand(1);
13698 DebugLoc DL = N->getDebugLoc();
13700 // Check LHS for vnot
13701 if (N0.getOpcode() == ISD::XOR &&
13702 //ISD::isBuildVectorAllOnes(N0.getOperand(1).getNode()))
13703 CanFoldXORWithAllOnes(N0.getOperand(1).getNode()))
13704 return DAG.getNode(X86ISD::ANDNP, DL, VT, N0.getOperand(0), N1);
13706 // Check RHS for vnot
13707 if (N1.getOpcode() == ISD::XOR &&
13708 //ISD::isBuildVectorAllOnes(N1.getOperand(1).getNode()))
13709 CanFoldXORWithAllOnes(N1.getOperand(1).getNode()))
13710 return DAG.getNode(X86ISD::ANDNP, DL, VT, N1.getOperand(0), N0);
13715 static SDValue PerformOrCombine(SDNode *N, SelectionDAG &DAG,
13716 TargetLowering::DAGCombinerInfo &DCI,
13717 const X86Subtarget *Subtarget) {
13718 if (DCI.isBeforeLegalizeOps())
13721 SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget);
13725 EVT VT = N->getValueType(0);
13727 SDValue N0 = N->getOperand(0);
13728 SDValue N1 = N->getOperand(1);
13730 // look for psign/blend
13731 if (VT == MVT::v2i64 || VT == MVT::v4i64) {
13732 if (!Subtarget->hasSSSE3() ||
13733 (VT == MVT::v4i64 && !Subtarget->hasAVX2()))
13736 // Canonicalize pandn to RHS
13737 if (N0.getOpcode() == X86ISD::ANDNP)
13739 // or (and (m, y), (pandn m, x))
13740 if (N0.getOpcode() == ISD::AND && N1.getOpcode() == X86ISD::ANDNP) {
13741 SDValue Mask = N1.getOperand(0);
13742 SDValue X = N1.getOperand(1);
13744 if (N0.getOperand(0) == Mask)
13745 Y = N0.getOperand(1);
13746 if (N0.getOperand(1) == Mask)
13747 Y = N0.getOperand(0);
13749 // Check to see if the mask appeared in both the AND and ANDNP and
13753 // Validate that X, Y, and Mask are BIT_CONVERTS, and see through them.
13754 if (Mask.getOpcode() != ISD::BITCAST ||
13755 X.getOpcode() != ISD::BITCAST ||
13756 Y.getOpcode() != ISD::BITCAST)
13759 // Look through mask bitcast.
13760 Mask = Mask.getOperand(0);
13761 EVT MaskVT = Mask.getValueType();
13763 // Validate that the Mask operand is a vector sra node. The sra node
13764 // will be an intrinsic.
13765 if (Mask.getOpcode() != ISD::INTRINSIC_WO_CHAIN)
13768 // FIXME: what to do for bytes, since there is a psignb/pblendvb, but
13769 // there is no psrai.b
13770 switch (cast<ConstantSDNode>(Mask.getOperand(0))->getZExtValue()) {
13771 case Intrinsic::x86_sse2_psrai_w:
13772 case Intrinsic::x86_sse2_psrai_d:
13773 case Intrinsic::x86_avx2_psrai_w:
13774 case Intrinsic::x86_avx2_psrai_d:
13776 default: return SDValue();
13779 // Check that the SRA is all signbits.
13780 SDValue SraC = Mask.getOperand(2);
13781 unsigned SraAmt = cast<ConstantSDNode>(SraC)->getZExtValue();
13782 unsigned EltBits = MaskVT.getVectorElementType().getSizeInBits();
13783 if ((SraAmt + 1) != EltBits)
13786 DebugLoc DL = N->getDebugLoc();
13788 // Now we know we at least have a plendvb with the mask val. See if
13789 // we can form a psignb/w/d.
13790 // psign = x.type == y.type == mask.type && y = sub(0, x);
13791 X = X.getOperand(0);
13792 Y = Y.getOperand(0);
13793 if (Y.getOpcode() == ISD::SUB && Y.getOperand(1) == X &&
13794 ISD::isBuildVectorAllZeros(Y.getOperand(0).getNode()) &&
13795 X.getValueType() == MaskVT && X.getValueType() == Y.getValueType() &&
13796 (EltBits == 8 || EltBits == 16 || EltBits == 32)) {
13797 SDValue Sign = DAG.getNode(X86ISD::PSIGN, DL, MaskVT, X,
13798 Mask.getOperand(1));
13799 return DAG.getNode(ISD::BITCAST, DL, VT, Sign);
13801 // PBLENDVB only available on SSE 4.1
13802 if (!Subtarget->hasSSE41())
13805 EVT BlendVT = (VT == MVT::v4i64) ? MVT::v32i8 : MVT::v16i8;
13807 X = DAG.getNode(ISD::BITCAST, DL, BlendVT, X);
13808 Y = DAG.getNode(ISD::BITCAST, DL, BlendVT, Y);
13809 Mask = DAG.getNode(ISD::BITCAST, DL, BlendVT, Mask);
13810 Mask = DAG.getNode(ISD::VSELECT, DL, BlendVT, Mask, Y, X);
13811 return DAG.getNode(ISD::BITCAST, DL, VT, Mask);
13815 if (VT != MVT::i16 && VT != MVT::i32 && VT != MVT::i64)
13818 // fold (or (x << c) | (y >> (64 - c))) ==> (shld64 x, y, c)
13819 if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL)
13821 if (N0.getOpcode() != ISD::SHL || N1.getOpcode() != ISD::SRL)
13823 if (!N0.hasOneUse() || !N1.hasOneUse())
13826 SDValue ShAmt0 = N0.getOperand(1);
13827 if (ShAmt0.getValueType() != MVT::i8)
13829 SDValue ShAmt1 = N1.getOperand(1);
13830 if (ShAmt1.getValueType() != MVT::i8)
13832 if (ShAmt0.getOpcode() == ISD::TRUNCATE)
13833 ShAmt0 = ShAmt0.getOperand(0);
13834 if (ShAmt1.getOpcode() == ISD::TRUNCATE)
13835 ShAmt1 = ShAmt1.getOperand(0);
13837 DebugLoc DL = N->getDebugLoc();
13838 unsigned Opc = X86ISD::SHLD;
13839 SDValue Op0 = N0.getOperand(0);
13840 SDValue Op1 = N1.getOperand(0);
13841 if (ShAmt0.getOpcode() == ISD::SUB) {
13842 Opc = X86ISD::SHRD;
13843 std::swap(Op0, Op1);
13844 std::swap(ShAmt0, ShAmt1);
13847 unsigned Bits = VT.getSizeInBits();
13848 if (ShAmt1.getOpcode() == ISD::SUB) {
13849 SDValue Sum = ShAmt1.getOperand(0);
13850 if (ConstantSDNode *SumC = dyn_cast<ConstantSDNode>(Sum)) {
13851 SDValue ShAmt1Op1 = ShAmt1.getOperand(1);
13852 if (ShAmt1Op1.getNode()->getOpcode() == ISD::TRUNCATE)
13853 ShAmt1Op1 = ShAmt1Op1.getOperand(0);
13854 if (SumC->getSExtValue() == Bits && ShAmt1Op1 == ShAmt0)
13855 return DAG.getNode(Opc, DL, VT,
13857 DAG.getNode(ISD::TRUNCATE, DL,
13860 } else if (ConstantSDNode *ShAmt1C = dyn_cast<ConstantSDNode>(ShAmt1)) {
13861 ConstantSDNode *ShAmt0C = dyn_cast<ConstantSDNode>(ShAmt0);
13863 ShAmt0C->getSExtValue() + ShAmt1C->getSExtValue() == Bits)
13864 return DAG.getNode(Opc, DL, VT,
13865 N0.getOperand(0), N1.getOperand(0),
13866 DAG.getNode(ISD::TRUNCATE, DL,
13873 // PerformXorCombine - Attempts to turn XOR nodes into BLSMSK nodes
13874 static SDValue PerformXorCombine(SDNode *N, SelectionDAG &DAG,
13875 TargetLowering::DAGCombinerInfo &DCI,
13876 const X86Subtarget *Subtarget) {
13877 if (DCI.isBeforeLegalizeOps())
13880 EVT VT = N->getValueType(0);
13882 if (VT != MVT::i32 && VT != MVT::i64)
13885 assert(Subtarget->hasBMI() && "Creating BLSMSK requires BMI instructions");
13887 // Create BLSMSK instructions by finding X ^ (X-1)
13888 SDValue N0 = N->getOperand(0);
13889 SDValue N1 = N->getOperand(1);
13890 DebugLoc DL = N->getDebugLoc();
13892 if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1 &&
13893 isAllOnes(N0.getOperand(1)))
13894 return DAG.getNode(X86ISD::BLSMSK, DL, VT, N1);
13896 if (N1.getOpcode() == ISD::ADD && N1.getOperand(0) == N0 &&
13897 isAllOnes(N1.getOperand(1)))
13898 return DAG.getNode(X86ISD::BLSMSK, DL, VT, N0);
13903 /// PerformLOADCombine - Do target-specific dag combines on LOAD nodes.
13904 static SDValue PerformLOADCombine(SDNode *N, SelectionDAG &DAG,
13905 const X86Subtarget *Subtarget) {
13906 LoadSDNode *Ld = cast<LoadSDNode>(N);
13907 EVT RegVT = Ld->getValueType(0);
13908 EVT MemVT = Ld->getMemoryVT();
13909 DebugLoc dl = Ld->getDebugLoc();
13910 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
13912 ISD::LoadExtType Ext = Ld->getExtensionType();
13914 // If this is a vector EXT Load then attempt to optimize it using a
13915 // shuffle. We need SSE4 for the shuffles.
13916 // TODO: It is possible to support ZExt by zeroing the undef values
13917 // during the shuffle phase or after the shuffle.
13918 if (RegVT.isVector() && RegVT.isInteger() &&
13919 Ext == ISD::EXTLOAD && Subtarget->hasSSE41()) {
13920 assert(MemVT != RegVT && "Cannot extend to the same type");
13921 assert(MemVT.isVector() && "Must load a vector from memory");
13923 unsigned NumElems = RegVT.getVectorNumElements();
13924 unsigned RegSz = RegVT.getSizeInBits();
13925 unsigned MemSz = MemVT.getSizeInBits();
13926 assert(RegSz > MemSz && "Register size must be greater than the mem size");
13927 // All sizes must be a power of two
13928 if (!isPowerOf2_32(RegSz * MemSz * NumElems)) return SDValue();
13930 // Attempt to load the original value using a single load op.
13931 // Find a scalar type which is equal to the loaded word size.
13932 MVT SclrLoadTy = MVT::i8;
13933 for (unsigned tp = MVT::FIRST_INTEGER_VALUETYPE;
13934 tp < MVT::LAST_INTEGER_VALUETYPE; ++tp) {
13935 MVT Tp = (MVT::SimpleValueType)tp;
13936 if (TLI.isTypeLegal(Tp) && Tp.getSizeInBits() == MemSz) {
13942 // Proceed if a load word is found.
13943 if (SclrLoadTy.getSizeInBits() != MemSz) return SDValue();
13945 EVT LoadUnitVecVT = EVT::getVectorVT(*DAG.getContext(), SclrLoadTy,
13946 RegSz/SclrLoadTy.getSizeInBits());
13948 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(), MemVT.getScalarType(),
13949 RegSz/MemVT.getScalarType().getSizeInBits());
13950 // Can't shuffle using an illegal type.
13951 if (!TLI.isTypeLegal(WideVecVT)) return SDValue();
13953 // Perform a single load.
13954 SDValue ScalarLoad = DAG.getLoad(SclrLoadTy, dl, Ld->getChain(),
13956 Ld->getPointerInfo(), Ld->isVolatile(),
13957 Ld->isNonTemporal(), Ld->isInvariant(),
13958 Ld->getAlignment());
13960 // Insert the word loaded into a vector.
13961 SDValue ScalarInVector = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
13962 LoadUnitVecVT, ScalarLoad);
13964 // Bitcast the loaded value to a vector of the original element type, in
13965 // the size of the target vector type.
13966 SDValue SlicedVec = DAG.getNode(ISD::BITCAST, dl, WideVecVT,
13968 unsigned SizeRatio = RegSz/MemSz;
13970 // Redistribute the loaded elements into the different locations.
13971 SmallVector<int, 8> ShuffleVec(NumElems * SizeRatio, -1);
13972 for (unsigned i = 0; i < NumElems; i++) ShuffleVec[i*SizeRatio] = i;
13974 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, SlicedVec,
13975 DAG.getUNDEF(SlicedVec.getValueType()),
13976 ShuffleVec.data());
13978 // Bitcast to the requested type.
13979 Shuff = DAG.getNode(ISD::BITCAST, dl, RegVT, Shuff);
13980 // Replace the original load with the new sequence
13981 // and return the new chain.
13982 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Shuff);
13983 return SDValue(ScalarLoad.getNode(), 1);
13989 /// PerformSTORECombine - Do target-specific dag combines on STORE nodes.
13990 static SDValue PerformSTORECombine(SDNode *N, SelectionDAG &DAG,
13991 const X86Subtarget *Subtarget) {
13992 StoreSDNode *St = cast<StoreSDNode>(N);
13993 EVT VT = St->getValue().getValueType();
13994 EVT StVT = St->getMemoryVT();
13995 DebugLoc dl = St->getDebugLoc();
13996 SDValue StoredVal = St->getOperand(1);
13997 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
13999 // If we are saving a concatenation of two XMM registers, perform two stores.
14000 // This is better in Sandy Bridge cause one 256-bit mem op is done via two
14001 // 128-bit ones. If in the future the cost becomes only one memory access the
14002 // first version would be better.
14003 if (VT.getSizeInBits() == 256 &&
14004 StoredVal.getNode()->getOpcode() == ISD::CONCAT_VECTORS &&
14005 StoredVal.getNumOperands() == 2) {
14007 SDValue Value0 = StoredVal.getOperand(0);
14008 SDValue Value1 = StoredVal.getOperand(1);
14010 SDValue Stride = DAG.getConstant(16, TLI.getPointerTy());
14011 SDValue Ptr0 = St->getBasePtr();
14012 SDValue Ptr1 = DAG.getNode(ISD::ADD, dl, Ptr0.getValueType(), Ptr0, Stride);
14014 SDValue Ch0 = DAG.getStore(St->getChain(), dl, Value0, Ptr0,
14015 St->getPointerInfo(), St->isVolatile(),
14016 St->isNonTemporal(), St->getAlignment());
14017 SDValue Ch1 = DAG.getStore(St->getChain(), dl, Value1, Ptr1,
14018 St->getPointerInfo(), St->isVolatile(),
14019 St->isNonTemporal(), St->getAlignment());
14020 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Ch0, Ch1);
14023 // Optimize trunc store (of multiple scalars) to shuffle and store.
14024 // First, pack all of the elements in one place. Next, store to memory
14025 // in fewer chunks.
14026 if (St->isTruncatingStore() && VT.isVector()) {
14027 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
14028 unsigned NumElems = VT.getVectorNumElements();
14029 assert(StVT != VT && "Cannot truncate to the same type");
14030 unsigned FromSz = VT.getVectorElementType().getSizeInBits();
14031 unsigned ToSz = StVT.getVectorElementType().getSizeInBits();
14033 // From, To sizes and ElemCount must be pow of two
14034 if (!isPowerOf2_32(NumElems * FromSz * ToSz)) return SDValue();
14035 // We are going to use the original vector elt for storing.
14036 // Accumulated smaller vector elements must be a multiple of the store size.
14037 if (0 != (NumElems * FromSz) % ToSz) return SDValue();
14039 unsigned SizeRatio = FromSz / ToSz;
14041 assert(SizeRatio * NumElems * ToSz == VT.getSizeInBits());
14043 // Create a type on which we perform the shuffle
14044 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(),
14045 StVT.getScalarType(), NumElems*SizeRatio);
14047 assert(WideVecVT.getSizeInBits() == VT.getSizeInBits());
14049 SDValue WideVec = DAG.getNode(ISD::BITCAST, dl, WideVecVT, St->getValue());
14050 SmallVector<int, 8> ShuffleVec(NumElems * SizeRatio, -1);
14051 for (unsigned i = 0; i < NumElems; i++ ) ShuffleVec[i] = i * SizeRatio;
14053 // Can't shuffle using an illegal type
14054 if (!TLI.isTypeLegal(WideVecVT)) return SDValue();
14056 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, WideVec,
14057 DAG.getUNDEF(WideVec.getValueType()),
14058 ShuffleVec.data());
14059 // At this point all of the data is stored at the bottom of the
14060 // register. We now need to save it to mem.
14062 // Find the largest store unit
14063 MVT StoreType = MVT::i8;
14064 for (unsigned tp = MVT::FIRST_INTEGER_VALUETYPE;
14065 tp < MVT::LAST_INTEGER_VALUETYPE; ++tp) {
14066 MVT Tp = (MVT::SimpleValueType)tp;
14067 if (TLI.isTypeLegal(Tp) && StoreType.getSizeInBits() < NumElems * ToSz)
14071 // Bitcast the original vector into a vector of store-size units
14072 EVT StoreVecVT = EVT::getVectorVT(*DAG.getContext(),
14073 StoreType, VT.getSizeInBits()/EVT(StoreType).getSizeInBits());
14074 assert(StoreVecVT.getSizeInBits() == VT.getSizeInBits());
14075 SDValue ShuffWide = DAG.getNode(ISD::BITCAST, dl, StoreVecVT, Shuff);
14076 SmallVector<SDValue, 8> Chains;
14077 SDValue Increment = DAG.getConstant(StoreType.getSizeInBits()/8,
14078 TLI.getPointerTy());
14079 SDValue Ptr = St->getBasePtr();
14081 // Perform one or more big stores into memory.
14082 for (unsigned i = 0; i < (ToSz*NumElems)/StoreType.getSizeInBits() ; i++) {
14083 SDValue SubVec = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
14084 StoreType, ShuffWide,
14085 DAG.getIntPtrConstant(i));
14086 SDValue Ch = DAG.getStore(St->getChain(), dl, SubVec, Ptr,
14087 St->getPointerInfo(), St->isVolatile(),
14088 St->isNonTemporal(), St->getAlignment());
14089 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
14090 Chains.push_back(Ch);
14093 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Chains[0],
14098 // Turn load->store of MMX types into GPR load/stores. This avoids clobbering
14099 // the FP state in cases where an emms may be missing.
14100 // A preferable solution to the general problem is to figure out the right
14101 // places to insert EMMS. This qualifies as a quick hack.
14103 // Similarly, turn load->store of i64 into double load/stores in 32-bit mode.
14104 if (VT.getSizeInBits() != 64)
14107 const Function *F = DAG.getMachineFunction().getFunction();
14108 bool NoImplicitFloatOps = F->hasFnAttr(Attribute::NoImplicitFloat);
14109 bool F64IsLegal = !DAG.getTarget().Options.UseSoftFloat && !NoImplicitFloatOps
14110 && Subtarget->hasSSE2();
14111 if ((VT.isVector() ||
14112 (VT == MVT::i64 && F64IsLegal && !Subtarget->is64Bit())) &&
14113 isa<LoadSDNode>(St->getValue()) &&
14114 !cast<LoadSDNode>(St->getValue())->isVolatile() &&
14115 St->getChain().hasOneUse() && !St->isVolatile()) {
14116 SDNode* LdVal = St->getValue().getNode();
14117 LoadSDNode *Ld = 0;
14118 int TokenFactorIndex = -1;
14119 SmallVector<SDValue, 8> Ops;
14120 SDNode* ChainVal = St->getChain().getNode();
14121 // Must be a store of a load. We currently handle two cases: the load
14122 // is a direct child, and it's under an intervening TokenFactor. It is
14123 // possible to dig deeper under nested TokenFactors.
14124 if (ChainVal == LdVal)
14125 Ld = cast<LoadSDNode>(St->getChain());
14126 else if (St->getValue().hasOneUse() &&
14127 ChainVal->getOpcode() == ISD::TokenFactor) {
14128 for (unsigned i=0, e = ChainVal->getNumOperands(); i != e; ++i) {
14129 if (ChainVal->getOperand(i).getNode() == LdVal) {
14130 TokenFactorIndex = i;
14131 Ld = cast<LoadSDNode>(St->getValue());
14133 Ops.push_back(ChainVal->getOperand(i));
14137 if (!Ld || !ISD::isNormalLoad(Ld))
14140 // If this is not the MMX case, i.e. we are just turning i64 load/store
14141 // into f64 load/store, avoid the transformation if there are multiple
14142 // uses of the loaded value.
14143 if (!VT.isVector() && !Ld->hasNUsesOfValue(1, 0))
14146 DebugLoc LdDL = Ld->getDebugLoc();
14147 DebugLoc StDL = N->getDebugLoc();
14148 // If we are a 64-bit capable x86, lower to a single movq load/store pair.
14149 // Otherwise, if it's legal to use f64 SSE instructions, use f64 load/store
14151 if (Subtarget->is64Bit() || F64IsLegal) {
14152 EVT LdVT = Subtarget->is64Bit() ? MVT::i64 : MVT::f64;
14153 SDValue NewLd = DAG.getLoad(LdVT, LdDL, Ld->getChain(), Ld->getBasePtr(),
14154 Ld->getPointerInfo(), Ld->isVolatile(),
14155 Ld->isNonTemporal(), Ld->isInvariant(),
14156 Ld->getAlignment());
14157 SDValue NewChain = NewLd.getValue(1);
14158 if (TokenFactorIndex != -1) {
14159 Ops.push_back(NewChain);
14160 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, &Ops[0],
14163 return DAG.getStore(NewChain, StDL, NewLd, St->getBasePtr(),
14164 St->getPointerInfo(),
14165 St->isVolatile(), St->isNonTemporal(),
14166 St->getAlignment());
14169 // Otherwise, lower to two pairs of 32-bit loads / stores.
14170 SDValue LoAddr = Ld->getBasePtr();
14171 SDValue HiAddr = DAG.getNode(ISD::ADD, LdDL, MVT::i32, LoAddr,
14172 DAG.getConstant(4, MVT::i32));
14174 SDValue LoLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), LoAddr,
14175 Ld->getPointerInfo(),
14176 Ld->isVolatile(), Ld->isNonTemporal(),
14177 Ld->isInvariant(), Ld->getAlignment());
14178 SDValue HiLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), HiAddr,
14179 Ld->getPointerInfo().getWithOffset(4),
14180 Ld->isVolatile(), Ld->isNonTemporal(),
14182 MinAlign(Ld->getAlignment(), 4));
14184 SDValue NewChain = LoLd.getValue(1);
14185 if (TokenFactorIndex != -1) {
14186 Ops.push_back(LoLd);
14187 Ops.push_back(HiLd);
14188 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, &Ops[0],
14192 LoAddr = St->getBasePtr();
14193 HiAddr = DAG.getNode(ISD::ADD, StDL, MVT::i32, LoAddr,
14194 DAG.getConstant(4, MVT::i32));
14196 SDValue LoSt = DAG.getStore(NewChain, StDL, LoLd, LoAddr,
14197 St->getPointerInfo(),
14198 St->isVolatile(), St->isNonTemporal(),
14199 St->getAlignment());
14200 SDValue HiSt = DAG.getStore(NewChain, StDL, HiLd, HiAddr,
14201 St->getPointerInfo().getWithOffset(4),
14203 St->isNonTemporal(),
14204 MinAlign(St->getAlignment(), 4));
14205 return DAG.getNode(ISD::TokenFactor, StDL, MVT::Other, LoSt, HiSt);
14210 /// isHorizontalBinOp - Return 'true' if this vector operation is "horizontal"
14211 /// and return the operands for the horizontal operation in LHS and RHS. A
14212 /// horizontal operation performs the binary operation on successive elements
14213 /// of its first operand, then on successive elements of its second operand,
14214 /// returning the resulting values in a vector. For example, if
14215 /// A = < float a0, float a1, float a2, float a3 >
14217 /// B = < float b0, float b1, float b2, float b3 >
14218 /// then the result of doing a horizontal operation on A and B is
14219 /// A horizontal-op B = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >.
14220 /// In short, LHS and RHS are inspected to see if LHS op RHS is of the form
14221 /// A horizontal-op B, for some already available A and B, and if so then LHS is
14222 /// set to A, RHS to B, and the routine returns 'true'.
14223 /// Note that the binary operation should have the property that if one of the
14224 /// operands is UNDEF then the result is UNDEF.
14225 static bool isHorizontalBinOp(SDValue &LHS, SDValue &RHS, bool IsCommutative) {
14226 // Look for the following pattern: if
14227 // A = < float a0, float a1, float a2, float a3 >
14228 // B = < float b0, float b1, float b2, float b3 >
14230 // LHS = VECTOR_SHUFFLE A, B, <0, 2, 4, 6>
14231 // RHS = VECTOR_SHUFFLE A, B, <1, 3, 5, 7>
14232 // then LHS op RHS = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >
14233 // which is A horizontal-op B.
14235 // At least one of the operands should be a vector shuffle.
14236 if (LHS.getOpcode() != ISD::VECTOR_SHUFFLE &&
14237 RHS.getOpcode() != ISD::VECTOR_SHUFFLE)
14240 EVT VT = LHS.getValueType();
14242 assert((VT.is128BitVector() || VT.is256BitVector()) &&
14243 "Unsupported vector type for horizontal add/sub");
14245 // Handle 128 and 256-bit vector lengths. AVX defines horizontal add/sub to
14246 // operate independently on 128-bit lanes.
14247 unsigned NumElts = VT.getVectorNumElements();
14248 unsigned NumLanes = VT.getSizeInBits()/128;
14249 unsigned NumLaneElts = NumElts / NumLanes;
14250 assert((NumLaneElts % 2 == 0) &&
14251 "Vector type should have an even number of elements in each lane");
14252 unsigned HalfLaneElts = NumLaneElts/2;
14254 // View LHS in the form
14255 // LHS = VECTOR_SHUFFLE A, B, LMask
14256 // If LHS is not a shuffle then pretend it is the shuffle
14257 // LHS = VECTOR_SHUFFLE LHS, undef, <0, 1, ..., N-1>
14258 // NOTE: in what follows a default initialized SDValue represents an UNDEF of
14261 SmallVector<int, 16> LMask(NumElts);
14262 if (LHS.getOpcode() == ISD::VECTOR_SHUFFLE) {
14263 if (LHS.getOperand(0).getOpcode() != ISD::UNDEF)
14264 A = LHS.getOperand(0);
14265 if (LHS.getOperand(1).getOpcode() != ISD::UNDEF)
14266 B = LHS.getOperand(1);
14267 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(LHS.getNode())->getMask();
14268 std::copy(Mask.begin(), Mask.end(), LMask.begin());
14270 if (LHS.getOpcode() != ISD::UNDEF)
14272 for (unsigned i = 0; i != NumElts; ++i)
14276 // Likewise, view RHS in the form
14277 // RHS = VECTOR_SHUFFLE C, D, RMask
14279 SmallVector<int, 16> RMask(NumElts);
14280 if (RHS.getOpcode() == ISD::VECTOR_SHUFFLE) {
14281 if (RHS.getOperand(0).getOpcode() != ISD::UNDEF)
14282 C = RHS.getOperand(0);
14283 if (RHS.getOperand(1).getOpcode() != ISD::UNDEF)
14284 D = RHS.getOperand(1);
14285 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(RHS.getNode())->getMask();
14286 std::copy(Mask.begin(), Mask.end(), RMask.begin());
14288 if (RHS.getOpcode() != ISD::UNDEF)
14290 for (unsigned i = 0; i != NumElts; ++i)
14294 // Check that the shuffles are both shuffling the same vectors.
14295 if (!(A == C && B == D) && !(A == D && B == C))
14298 // If everything is UNDEF then bail out: it would be better to fold to UNDEF.
14299 if (!A.getNode() && !B.getNode())
14302 // If A and B occur in reverse order in RHS, then "swap" them (which means
14303 // rewriting the mask).
14305 CommuteVectorShuffleMask(RMask, NumElts);
14307 // At this point LHS and RHS are equivalent to
14308 // LHS = VECTOR_SHUFFLE A, B, LMask
14309 // RHS = VECTOR_SHUFFLE A, B, RMask
14310 // Check that the masks correspond to performing a horizontal operation.
14311 for (unsigned i = 0; i != NumElts; ++i) {
14312 int LIdx = LMask[i], RIdx = RMask[i];
14314 // Ignore any UNDEF components.
14315 if (LIdx < 0 || RIdx < 0 ||
14316 (!A.getNode() && (LIdx < (int)NumElts || RIdx < (int)NumElts)) ||
14317 (!B.getNode() && (LIdx >= (int)NumElts || RIdx >= (int)NumElts)))
14320 // Check that successive elements are being operated on. If not, this is
14321 // not a horizontal operation.
14322 unsigned Src = (i/HalfLaneElts) % 2; // each lane is split between srcs
14323 unsigned LaneStart = (i/NumLaneElts) * NumLaneElts;
14324 int Index = 2*(i%HalfLaneElts) + NumElts*Src + LaneStart;
14325 if (!(LIdx == Index && RIdx == Index + 1) &&
14326 !(IsCommutative && LIdx == Index + 1 && RIdx == Index))
14330 LHS = A.getNode() ? A : B; // If A is 'UNDEF', use B for it.
14331 RHS = B.getNode() ? B : A; // If B is 'UNDEF', use A for it.
14335 /// PerformFADDCombine - Do target-specific dag combines on floating point adds.
14336 static SDValue PerformFADDCombine(SDNode *N, SelectionDAG &DAG,
14337 const X86Subtarget *Subtarget) {
14338 EVT VT = N->getValueType(0);
14339 SDValue LHS = N->getOperand(0);
14340 SDValue RHS = N->getOperand(1);
14342 // Try to synthesize horizontal adds from adds of shuffles.
14343 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
14344 (Subtarget->hasAVX() && (VT == MVT::v8f32 || VT == MVT::v4f64))) &&
14345 isHorizontalBinOp(LHS, RHS, true))
14346 return DAG.getNode(X86ISD::FHADD, N->getDebugLoc(), VT, LHS, RHS);
14350 /// PerformFSUBCombine - Do target-specific dag combines on floating point subs.
14351 static SDValue PerformFSUBCombine(SDNode *N, SelectionDAG &DAG,
14352 const X86Subtarget *Subtarget) {
14353 EVT VT = N->getValueType(0);
14354 SDValue LHS = N->getOperand(0);
14355 SDValue RHS = N->getOperand(1);
14357 // Try to synthesize horizontal subs from subs of shuffles.
14358 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
14359 (Subtarget->hasAVX() && (VT == MVT::v8f32 || VT == MVT::v4f64))) &&
14360 isHorizontalBinOp(LHS, RHS, false))
14361 return DAG.getNode(X86ISD::FHSUB, N->getDebugLoc(), VT, LHS, RHS);
14365 /// PerformFORCombine - Do target-specific dag combines on X86ISD::FOR and
14366 /// X86ISD::FXOR nodes.
14367 static SDValue PerformFORCombine(SDNode *N, SelectionDAG &DAG) {
14368 assert(N->getOpcode() == X86ISD::FOR || N->getOpcode() == X86ISD::FXOR);
14369 // F[X]OR(0.0, x) -> x
14370 // F[X]OR(x, 0.0) -> x
14371 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
14372 if (C->getValueAPF().isPosZero())
14373 return N->getOperand(1);
14374 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
14375 if (C->getValueAPF().isPosZero())
14376 return N->getOperand(0);
14380 /// PerformFANDCombine - Do target-specific dag combines on X86ISD::FAND nodes.
14381 static SDValue PerformFANDCombine(SDNode *N, SelectionDAG &DAG) {
14382 // FAND(0.0, x) -> 0.0
14383 // FAND(x, 0.0) -> 0.0
14384 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
14385 if (C->getValueAPF().isPosZero())
14386 return N->getOperand(0);
14387 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
14388 if (C->getValueAPF().isPosZero())
14389 return N->getOperand(1);
14393 static SDValue PerformBTCombine(SDNode *N,
14395 TargetLowering::DAGCombinerInfo &DCI) {
14396 // BT ignores high bits in the bit index operand.
14397 SDValue Op1 = N->getOperand(1);
14398 if (Op1.hasOneUse()) {
14399 unsigned BitWidth = Op1.getValueSizeInBits();
14400 APInt DemandedMask = APInt::getLowBitsSet(BitWidth, Log2_32(BitWidth));
14401 APInt KnownZero, KnownOne;
14402 TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(),
14403 !DCI.isBeforeLegalizeOps());
14404 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
14405 if (TLO.ShrinkDemandedConstant(Op1, DemandedMask) ||
14406 TLI.SimplifyDemandedBits(Op1, DemandedMask, KnownZero, KnownOne, TLO))
14407 DCI.CommitTargetLoweringOpt(TLO);
14412 static SDValue PerformVZEXT_MOVLCombine(SDNode *N, SelectionDAG &DAG) {
14413 SDValue Op = N->getOperand(0);
14414 if (Op.getOpcode() == ISD::BITCAST)
14415 Op = Op.getOperand(0);
14416 EVT VT = N->getValueType(0), OpVT = Op.getValueType();
14417 if (Op.getOpcode() == X86ISD::VZEXT_LOAD &&
14418 VT.getVectorElementType().getSizeInBits() ==
14419 OpVT.getVectorElementType().getSizeInBits()) {
14420 return DAG.getNode(ISD::BITCAST, N->getDebugLoc(), VT, Op);
14425 static SDValue PerformZExtCombine(SDNode *N, SelectionDAG &DAG) {
14426 // (i32 zext (and (i8 x86isd::setcc_carry), 1)) ->
14427 // (and (i32 x86isd::setcc_carry), 1)
14428 // This eliminates the zext. This transformation is necessary because
14429 // ISD::SETCC is always legalized to i8.
14430 DebugLoc dl = N->getDebugLoc();
14431 SDValue N0 = N->getOperand(0);
14432 EVT VT = N->getValueType(0);
14433 if (N0.getOpcode() == ISD::AND &&
14435 N0.getOperand(0).hasOneUse()) {
14436 SDValue N00 = N0.getOperand(0);
14437 if (N00.getOpcode() != X86ISD::SETCC_CARRY)
14439 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
14440 if (!C || C->getZExtValue() != 1)
14442 return DAG.getNode(ISD::AND, dl, VT,
14443 DAG.getNode(X86ISD::SETCC_CARRY, dl, VT,
14444 N00.getOperand(0), N00.getOperand(1)),
14445 DAG.getConstant(1, VT));
14451 // Optimize RES = X86ISD::SETCC CONDCODE, EFLAG_INPUT
14452 static SDValue PerformSETCCCombine(SDNode *N, SelectionDAG &DAG) {
14453 unsigned X86CC = N->getConstantOperandVal(0);
14454 SDValue EFLAG = N->getOperand(1);
14455 DebugLoc DL = N->getDebugLoc();
14457 // Materialize "setb reg" as "sbb reg,reg", since it can be extended without
14458 // a zext and produces an all-ones bit which is more useful than 0/1 in some
14460 if (X86CC == X86::COND_B)
14461 return DAG.getNode(ISD::AND, DL, MVT::i8,
14462 DAG.getNode(X86ISD::SETCC_CARRY, DL, MVT::i8,
14463 DAG.getConstant(X86CC, MVT::i8), EFLAG),
14464 DAG.getConstant(1, MVT::i8));
14469 static SDValue PerformSINT_TO_FPCombine(SDNode *N, SelectionDAG &DAG,
14470 const X86TargetLowering *XTLI) {
14471 SDValue Op0 = N->getOperand(0);
14472 // Transform (SINT_TO_FP (i64 ...)) into an x87 operation if we have
14473 // a 32-bit target where SSE doesn't support i64->FP operations.
14474 if (Op0.getOpcode() == ISD::LOAD) {
14475 LoadSDNode *Ld = cast<LoadSDNode>(Op0.getNode());
14476 EVT VT = Ld->getValueType(0);
14477 if (!Ld->isVolatile() && !N->getValueType(0).isVector() &&
14478 ISD::isNON_EXTLoad(Op0.getNode()) && Op0.hasOneUse() &&
14479 !XTLI->getSubtarget()->is64Bit() &&
14480 !DAG.getTargetLoweringInfo().isTypeLegal(VT)) {
14481 SDValue FILDChain = XTLI->BuildFILD(SDValue(N, 0), Ld->getValueType(0),
14482 Ld->getChain(), Op0, DAG);
14483 DAG.ReplaceAllUsesOfValueWith(Op0.getValue(1), FILDChain.getValue(1));
14490 // Optimize RES, EFLAGS = X86ISD::ADC LHS, RHS, EFLAGS
14491 static SDValue PerformADCCombine(SDNode *N, SelectionDAG &DAG,
14492 X86TargetLowering::DAGCombinerInfo &DCI) {
14493 // If the LHS and RHS of the ADC node are zero, then it can't overflow and
14494 // the result is either zero or one (depending on the input carry bit).
14495 // Strength reduce this down to a "set on carry" aka SETCC_CARRY&1.
14496 if (X86::isZeroNode(N->getOperand(0)) &&
14497 X86::isZeroNode(N->getOperand(1)) &&
14498 // We don't have a good way to replace an EFLAGS use, so only do this when
14500 SDValue(N, 1).use_empty()) {
14501 DebugLoc DL = N->getDebugLoc();
14502 EVT VT = N->getValueType(0);
14503 SDValue CarryOut = DAG.getConstant(0, N->getValueType(1));
14504 SDValue Res1 = DAG.getNode(ISD::AND, DL, VT,
14505 DAG.getNode(X86ISD::SETCC_CARRY, DL, VT,
14506 DAG.getConstant(X86::COND_B,MVT::i8),
14508 DAG.getConstant(1, VT));
14509 return DCI.CombineTo(N, Res1, CarryOut);
14515 // fold (add Y, (sete X, 0)) -> adc 0, Y
14516 // (add Y, (setne X, 0)) -> sbb -1, Y
14517 // (sub (sete X, 0), Y) -> sbb 0, Y
14518 // (sub (setne X, 0), Y) -> adc -1, Y
14519 static SDValue OptimizeConditionalInDecrement(SDNode *N, SelectionDAG &DAG) {
14520 DebugLoc DL = N->getDebugLoc();
14522 // Look through ZExts.
14523 SDValue Ext = N->getOperand(N->getOpcode() == ISD::SUB ? 1 : 0);
14524 if (Ext.getOpcode() != ISD::ZERO_EXTEND || !Ext.hasOneUse())
14527 SDValue SetCC = Ext.getOperand(0);
14528 if (SetCC.getOpcode() != X86ISD::SETCC || !SetCC.hasOneUse())
14531 X86::CondCode CC = (X86::CondCode)SetCC.getConstantOperandVal(0);
14532 if (CC != X86::COND_E && CC != X86::COND_NE)
14535 SDValue Cmp = SetCC.getOperand(1);
14536 if (Cmp.getOpcode() != X86ISD::CMP || !Cmp.hasOneUse() ||
14537 !X86::isZeroNode(Cmp.getOperand(1)) ||
14538 !Cmp.getOperand(0).getValueType().isInteger())
14541 SDValue CmpOp0 = Cmp.getOperand(0);
14542 SDValue NewCmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32, CmpOp0,
14543 DAG.getConstant(1, CmpOp0.getValueType()));
14545 SDValue OtherVal = N->getOperand(N->getOpcode() == ISD::SUB ? 0 : 1);
14546 if (CC == X86::COND_NE)
14547 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::ADC : X86ISD::SBB,
14548 DL, OtherVal.getValueType(), OtherVal,
14549 DAG.getConstant(-1ULL, OtherVal.getValueType()), NewCmp);
14550 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::SBB : X86ISD::ADC,
14551 DL, OtherVal.getValueType(), OtherVal,
14552 DAG.getConstant(0, OtherVal.getValueType()), NewCmp);
14555 /// PerformADDCombine - Do target-specific dag combines on integer adds.
14556 static SDValue PerformAddCombine(SDNode *N, SelectionDAG &DAG,
14557 const X86Subtarget *Subtarget) {
14558 EVT VT = N->getValueType(0);
14559 SDValue Op0 = N->getOperand(0);
14560 SDValue Op1 = N->getOperand(1);
14562 // Try to synthesize horizontal adds from adds of shuffles.
14563 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) ||
14564 (Subtarget->hasAVX2() && (VT == MVT::v16i16 || VT == MVT::v8i32))) &&
14565 isHorizontalBinOp(Op0, Op1, true))
14566 return DAG.getNode(X86ISD::HADD, N->getDebugLoc(), VT, Op0, Op1);
14568 return OptimizeConditionalInDecrement(N, DAG);
14571 static SDValue PerformSubCombine(SDNode *N, SelectionDAG &DAG,
14572 const X86Subtarget *Subtarget) {
14573 SDValue Op0 = N->getOperand(0);
14574 SDValue Op1 = N->getOperand(1);
14576 // X86 can't encode an immediate LHS of a sub. See if we can push the
14577 // negation into a preceding instruction.
14578 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op0)) {
14579 // If the RHS of the sub is a XOR with one use and a constant, invert the
14580 // immediate. Then add one to the LHS of the sub so we can turn
14581 // X-Y -> X+~Y+1, saving one register.
14582 if (Op1->hasOneUse() && Op1.getOpcode() == ISD::XOR &&
14583 isa<ConstantSDNode>(Op1.getOperand(1))) {
14584 APInt XorC = cast<ConstantSDNode>(Op1.getOperand(1))->getAPIntValue();
14585 EVT VT = Op0.getValueType();
14586 SDValue NewXor = DAG.getNode(ISD::XOR, Op1.getDebugLoc(), VT,
14588 DAG.getConstant(~XorC, VT));
14589 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, NewXor,
14590 DAG.getConstant(C->getAPIntValue()+1, VT));
14594 // Try to synthesize horizontal adds from adds of shuffles.
14595 EVT VT = N->getValueType(0);
14596 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) ||
14597 (Subtarget->hasAVX2() && (VT == MVT::v16i16 || VT == MVT::v8i32))) &&
14598 isHorizontalBinOp(Op0, Op1, true))
14599 return DAG.getNode(X86ISD::HSUB, N->getDebugLoc(), VT, Op0, Op1);
14601 return OptimizeConditionalInDecrement(N, DAG);
14604 SDValue X86TargetLowering::PerformDAGCombine(SDNode *N,
14605 DAGCombinerInfo &DCI) const {
14606 SelectionDAG &DAG = DCI.DAG;
14607 switch (N->getOpcode()) {
14609 case ISD::EXTRACT_VECTOR_ELT:
14610 return PerformEXTRACT_VECTOR_ELTCombine(N, DAG, *this);
14612 case ISD::SELECT: return PerformSELECTCombine(N, DAG, Subtarget);
14613 case X86ISD::CMOV: return PerformCMOVCombine(N, DAG, DCI);
14614 case ISD::ADD: return PerformAddCombine(N, DAG, Subtarget);
14615 case ISD::SUB: return PerformSubCombine(N, DAG, Subtarget);
14616 case X86ISD::ADC: return PerformADCCombine(N, DAG, DCI);
14617 case ISD::MUL: return PerformMulCombine(N, DAG, DCI);
14620 case ISD::SRL: return PerformShiftCombine(N, DAG, Subtarget);
14621 case ISD::AND: return PerformAndCombine(N, DAG, DCI, Subtarget);
14622 case ISD::OR: return PerformOrCombine(N, DAG, DCI, Subtarget);
14623 case ISD::XOR: return PerformXorCombine(N, DAG, DCI, Subtarget);
14624 case ISD::LOAD: return PerformLOADCombine(N, DAG, Subtarget);
14625 case ISD::STORE: return PerformSTORECombine(N, DAG, Subtarget);
14626 case ISD::SINT_TO_FP: return PerformSINT_TO_FPCombine(N, DAG, this);
14627 case ISD::FADD: return PerformFADDCombine(N, DAG, Subtarget);
14628 case ISD::FSUB: return PerformFSUBCombine(N, DAG, Subtarget);
14630 case X86ISD::FOR: return PerformFORCombine(N, DAG);
14631 case X86ISD::FAND: return PerformFANDCombine(N, DAG);
14632 case X86ISD::BT: return PerformBTCombine(N, DAG, DCI);
14633 case X86ISD::VZEXT_MOVL: return PerformVZEXT_MOVLCombine(N, DAG);
14634 case ISD::ZERO_EXTEND: return PerformZExtCombine(N, DAG);
14635 case X86ISD::SETCC: return PerformSETCCCombine(N, DAG);
14636 case X86ISD::SHUFP: // Handle all target specific shuffles
14637 case X86ISD::PALIGN:
14638 case X86ISD::UNPCKH:
14639 case X86ISD::UNPCKL:
14640 case X86ISD::MOVHLPS:
14641 case X86ISD::MOVLHPS:
14642 case X86ISD::PSHUFD:
14643 case X86ISD::PSHUFHW:
14644 case X86ISD::PSHUFLW:
14645 case X86ISD::MOVSS:
14646 case X86ISD::MOVSD:
14647 case X86ISD::VPERMILP:
14648 case X86ISD::VPERM2X128:
14649 case ISD::VECTOR_SHUFFLE: return PerformShuffleCombine(N, DAG, DCI,Subtarget);
14655 /// isTypeDesirableForOp - Return true if the target has native support for
14656 /// the specified value type and it is 'desirable' to use the type for the
14657 /// given node type. e.g. On x86 i16 is legal, but undesirable since i16
14658 /// instruction encodings are longer and some i16 instructions are slow.
14659 bool X86TargetLowering::isTypeDesirableForOp(unsigned Opc, EVT VT) const {
14660 if (!isTypeLegal(VT))
14662 if (VT != MVT::i16)
14669 case ISD::SIGN_EXTEND:
14670 case ISD::ZERO_EXTEND:
14671 case ISD::ANY_EXTEND:
14684 /// IsDesirableToPromoteOp - This method query the target whether it is
14685 /// beneficial for dag combiner to promote the specified node. If true, it
14686 /// should return the desired promotion type by reference.
14687 bool X86TargetLowering::IsDesirableToPromoteOp(SDValue Op, EVT &PVT) const {
14688 EVT VT = Op.getValueType();
14689 if (VT != MVT::i16)
14692 bool Promote = false;
14693 bool Commute = false;
14694 switch (Op.getOpcode()) {
14697 LoadSDNode *LD = cast<LoadSDNode>(Op);
14698 // If the non-extending load has a single use and it's not live out, then it
14699 // might be folded.
14700 if (LD->getExtensionType() == ISD::NON_EXTLOAD /*&&
14701 Op.hasOneUse()*/) {
14702 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
14703 UE = Op.getNode()->use_end(); UI != UE; ++UI) {
14704 // The only case where we'd want to promote LOAD (rather then it being
14705 // promoted as an operand is when it's only use is liveout.
14706 if (UI->getOpcode() != ISD::CopyToReg)
14713 case ISD::SIGN_EXTEND:
14714 case ISD::ZERO_EXTEND:
14715 case ISD::ANY_EXTEND:
14720 SDValue N0 = Op.getOperand(0);
14721 // Look out for (store (shl (load), x)).
14722 if (MayFoldLoad(N0) && MayFoldIntoStore(Op))
14735 SDValue N0 = Op.getOperand(0);
14736 SDValue N1 = Op.getOperand(1);
14737 if (!Commute && MayFoldLoad(N1))
14739 // Avoid disabling potential load folding opportunities.
14740 if (MayFoldLoad(N0) && (!isa<ConstantSDNode>(N1) || MayFoldIntoStore(Op)))
14742 if (MayFoldLoad(N1) && (!isa<ConstantSDNode>(N0) || MayFoldIntoStore(Op)))
14752 //===----------------------------------------------------------------------===//
14753 // X86 Inline Assembly Support
14754 //===----------------------------------------------------------------------===//
14757 // Helper to match a string separated by whitespace.
14758 bool matchAsmImpl(StringRef s, ArrayRef<const StringRef *> args) {
14759 s = s.substr(s.find_first_not_of(" \t")); // Skip leading whitespace.
14761 for (unsigned i = 0, e = args.size(); i != e; ++i) {
14762 StringRef piece(*args[i]);
14763 if (!s.startswith(piece)) // Check if the piece matches.
14766 s = s.substr(piece.size());
14767 StringRef::size_type pos = s.find_first_not_of(" \t");
14768 if (pos == 0) // We matched a prefix.
14776 const VariadicFunction1<bool, StringRef, StringRef, matchAsmImpl> matchAsm={};
14779 bool X86TargetLowering::ExpandInlineAsm(CallInst *CI) const {
14780 InlineAsm *IA = cast<InlineAsm>(CI->getCalledValue());
14782 std::string AsmStr = IA->getAsmString();
14784 IntegerType *Ty = dyn_cast<IntegerType>(CI->getType());
14785 if (!Ty || Ty->getBitWidth() % 16 != 0)
14788 // TODO: should remove alternatives from the asmstring: "foo {a|b}" -> "foo a"
14789 SmallVector<StringRef, 4> AsmPieces;
14790 SplitString(AsmStr, AsmPieces, ";\n");
14792 switch (AsmPieces.size()) {
14793 default: return false;
14795 // FIXME: this should verify that we are targeting a 486 or better. If not,
14796 // we will turn this bswap into something that will be lowered to logical
14797 // ops instead of emitting the bswap asm. For now, we don't support 486 or
14798 // lower so don't worry about this.
14800 if (matchAsm(AsmPieces[0], "bswap", "$0") ||
14801 matchAsm(AsmPieces[0], "bswapl", "$0") ||
14802 matchAsm(AsmPieces[0], "bswapq", "$0") ||
14803 matchAsm(AsmPieces[0], "bswap", "${0:q}") ||
14804 matchAsm(AsmPieces[0], "bswapl", "${0:q}") ||
14805 matchAsm(AsmPieces[0], "bswapq", "${0:q}")) {
14806 // No need to check constraints, nothing other than the equivalent of
14807 // "=r,0" would be valid here.
14808 return IntrinsicLowering::LowerToByteSwap(CI);
14811 // rorw $$8, ${0:w} --> llvm.bswap.i16
14812 if (CI->getType()->isIntegerTy(16) &&
14813 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 &&
14814 (matchAsm(AsmPieces[0], "rorw", "$$8,", "${0:w}") ||
14815 matchAsm(AsmPieces[0], "rolw", "$$8,", "${0:w}"))) {
14817 const std::string &ConstraintsStr = IA->getConstraintString();
14818 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
14819 std::sort(AsmPieces.begin(), AsmPieces.end());
14820 if (AsmPieces.size() == 4 &&
14821 AsmPieces[0] == "~{cc}" &&
14822 AsmPieces[1] == "~{dirflag}" &&
14823 AsmPieces[2] == "~{flags}" &&
14824 AsmPieces[3] == "~{fpsr}")
14825 return IntrinsicLowering::LowerToByteSwap(CI);
14829 if (CI->getType()->isIntegerTy(32) &&
14830 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 &&
14831 matchAsm(AsmPieces[0], "rorw", "$$8,", "${0:w}") &&
14832 matchAsm(AsmPieces[1], "rorl", "$$16,", "$0") &&
14833 matchAsm(AsmPieces[2], "rorw", "$$8,", "${0:w}")) {
14835 const std::string &ConstraintsStr = IA->getConstraintString();
14836 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
14837 std::sort(AsmPieces.begin(), AsmPieces.end());
14838 if (AsmPieces.size() == 4 &&
14839 AsmPieces[0] == "~{cc}" &&
14840 AsmPieces[1] == "~{dirflag}" &&
14841 AsmPieces[2] == "~{flags}" &&
14842 AsmPieces[3] == "~{fpsr}")
14843 return IntrinsicLowering::LowerToByteSwap(CI);
14846 if (CI->getType()->isIntegerTy(64)) {
14847 InlineAsm::ConstraintInfoVector Constraints = IA->ParseConstraints();
14848 if (Constraints.size() >= 2 &&
14849 Constraints[0].Codes.size() == 1 && Constraints[0].Codes[0] == "A" &&
14850 Constraints[1].Codes.size() == 1 && Constraints[1].Codes[0] == "0") {
14851 // bswap %eax / bswap %edx / xchgl %eax, %edx -> llvm.bswap.i64
14852 if (matchAsm(AsmPieces[0], "bswap", "%eax") &&
14853 matchAsm(AsmPieces[1], "bswap", "%edx") &&
14854 matchAsm(AsmPieces[2], "xchgl", "%eax,", "%edx"))
14855 return IntrinsicLowering::LowerToByteSwap(CI);
14865 /// getConstraintType - Given a constraint letter, return the type of
14866 /// constraint it is for this target.
14867 X86TargetLowering::ConstraintType
14868 X86TargetLowering::getConstraintType(const std::string &Constraint) const {
14869 if (Constraint.size() == 1) {
14870 switch (Constraint[0]) {
14881 return C_RegisterClass;
14905 return TargetLowering::getConstraintType(Constraint);
14908 /// Examine constraint type and operand type and determine a weight value.
14909 /// This object must already have been set up with the operand type
14910 /// and the current alternative constraint selected.
14911 TargetLowering::ConstraintWeight
14912 X86TargetLowering::getSingleConstraintMatchWeight(
14913 AsmOperandInfo &info, const char *constraint) const {
14914 ConstraintWeight weight = CW_Invalid;
14915 Value *CallOperandVal = info.CallOperandVal;
14916 // If we don't have a value, we can't do a match,
14917 // but allow it at the lowest weight.
14918 if (CallOperandVal == NULL)
14920 Type *type = CallOperandVal->getType();
14921 // Look at the constraint type.
14922 switch (*constraint) {
14924 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
14935 if (CallOperandVal->getType()->isIntegerTy())
14936 weight = CW_SpecificReg;
14941 if (type->isFloatingPointTy())
14942 weight = CW_SpecificReg;
14945 if (type->isX86_MMXTy() && Subtarget->hasMMX())
14946 weight = CW_SpecificReg;
14950 if (((type->getPrimitiveSizeInBits() == 128) && Subtarget->hasSSE1()) ||
14951 ((type->getPrimitiveSizeInBits() == 256) && Subtarget->hasAVX()))
14952 weight = CW_Register;
14955 if (ConstantInt *C = dyn_cast<ConstantInt>(info.CallOperandVal)) {
14956 if (C->getZExtValue() <= 31)
14957 weight = CW_Constant;
14961 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
14962 if (C->getZExtValue() <= 63)
14963 weight = CW_Constant;
14967 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
14968 if ((C->getSExtValue() >= -0x80) && (C->getSExtValue() <= 0x7f))
14969 weight = CW_Constant;
14973 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
14974 if ((C->getZExtValue() == 0xff) || (C->getZExtValue() == 0xffff))
14975 weight = CW_Constant;
14979 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
14980 if (C->getZExtValue() <= 3)
14981 weight = CW_Constant;
14985 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
14986 if (C->getZExtValue() <= 0xff)
14987 weight = CW_Constant;
14992 if (dyn_cast<ConstantFP>(CallOperandVal)) {
14993 weight = CW_Constant;
14997 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
14998 if ((C->getSExtValue() >= -0x80000000LL) &&
14999 (C->getSExtValue() <= 0x7fffffffLL))
15000 weight = CW_Constant;
15004 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
15005 if (C->getZExtValue() <= 0xffffffff)
15006 weight = CW_Constant;
15013 /// LowerXConstraint - try to replace an X constraint, which matches anything,
15014 /// with another that has more specific requirements based on the type of the
15015 /// corresponding operand.
15016 const char *X86TargetLowering::
15017 LowerXConstraint(EVT ConstraintVT) const {
15018 // FP X constraints get lowered to SSE1/2 registers if available, otherwise
15019 // 'f' like normal targets.
15020 if (ConstraintVT.isFloatingPoint()) {
15021 if (Subtarget->hasSSE2())
15023 if (Subtarget->hasSSE1())
15027 return TargetLowering::LowerXConstraint(ConstraintVT);
15030 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
15031 /// vector. If it is invalid, don't add anything to Ops.
15032 void X86TargetLowering::LowerAsmOperandForConstraint(SDValue Op,
15033 std::string &Constraint,
15034 std::vector<SDValue>&Ops,
15035 SelectionDAG &DAG) const {
15036 SDValue Result(0, 0);
15038 // Only support length 1 constraints for now.
15039 if (Constraint.length() > 1) return;
15041 char ConstraintLetter = Constraint[0];
15042 switch (ConstraintLetter) {
15045 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
15046 if (C->getZExtValue() <= 31) {
15047 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
15053 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
15054 if (C->getZExtValue() <= 63) {
15055 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
15061 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
15062 if ((int8_t)C->getSExtValue() == C->getSExtValue()) {
15063 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
15069 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
15070 if (C->getZExtValue() <= 255) {
15071 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
15077 // 32-bit signed value
15078 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
15079 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
15080 C->getSExtValue())) {
15081 // Widen to 64 bits here to get it sign extended.
15082 Result = DAG.getTargetConstant(C->getSExtValue(), MVT::i64);
15085 // FIXME gcc accepts some relocatable values here too, but only in certain
15086 // memory models; it's complicated.
15091 // 32-bit unsigned value
15092 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
15093 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
15094 C->getZExtValue())) {
15095 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
15099 // FIXME gcc accepts some relocatable values here too, but only in certain
15100 // memory models; it's complicated.
15104 // Literal immediates are always ok.
15105 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op)) {
15106 // Widen to 64 bits here to get it sign extended.
15107 Result = DAG.getTargetConstant(CST->getSExtValue(), MVT::i64);
15111 // In any sort of PIC mode addresses need to be computed at runtime by
15112 // adding in a register or some sort of table lookup. These can't
15113 // be used as immediates.
15114 if (Subtarget->isPICStyleGOT() || Subtarget->isPICStyleStubPIC())
15117 // If we are in non-pic codegen mode, we allow the address of a global (with
15118 // an optional displacement) to be used with 'i'.
15119 GlobalAddressSDNode *GA = 0;
15120 int64_t Offset = 0;
15122 // Match either (GA), (GA+C), (GA+C1+C2), etc.
15124 if ((GA = dyn_cast<GlobalAddressSDNode>(Op))) {
15125 Offset += GA->getOffset();
15127 } else if (Op.getOpcode() == ISD::ADD) {
15128 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
15129 Offset += C->getZExtValue();
15130 Op = Op.getOperand(0);
15133 } else if (Op.getOpcode() == ISD::SUB) {
15134 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
15135 Offset += -C->getZExtValue();
15136 Op = Op.getOperand(0);
15141 // Otherwise, this isn't something we can handle, reject it.
15145 const GlobalValue *GV = GA->getGlobal();
15146 // If we require an extra load to get this address, as in PIC mode, we
15147 // can't accept it.
15148 if (isGlobalStubReference(Subtarget->ClassifyGlobalReference(GV,
15149 getTargetMachine())))
15152 Result = DAG.getTargetGlobalAddress(GV, Op.getDebugLoc(),
15153 GA->getValueType(0), Offset);
15158 if (Result.getNode()) {
15159 Ops.push_back(Result);
15162 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
15165 std::pair<unsigned, const TargetRegisterClass*>
15166 X86TargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
15168 // First, see if this is a constraint that directly corresponds to an LLVM
15170 if (Constraint.size() == 1) {
15171 // GCC Constraint Letters
15172 switch (Constraint[0]) {
15174 // TODO: Slight differences here in allocation order and leaving
15175 // RIP in the class. Do they matter any more here than they do
15176 // in the normal allocation?
15177 case 'q': // GENERAL_REGS in 64-bit mode, Q_REGS in 32-bit mode.
15178 if (Subtarget->is64Bit()) {
15179 if (VT == MVT::i32 || VT == MVT::f32)
15180 return std::make_pair(0U, X86::GR32RegisterClass);
15181 else if (VT == MVT::i16)
15182 return std::make_pair(0U, X86::GR16RegisterClass);
15183 else if (VT == MVT::i8 || VT == MVT::i1)
15184 return std::make_pair(0U, X86::GR8RegisterClass);
15185 else if (VT == MVT::i64 || VT == MVT::f64)
15186 return std::make_pair(0U, X86::GR64RegisterClass);
15189 // 32-bit fallthrough
15190 case 'Q': // Q_REGS
15191 if (VT == MVT::i32 || VT == MVT::f32)
15192 return std::make_pair(0U, X86::GR32_ABCDRegisterClass);
15193 else if (VT == MVT::i16)
15194 return std::make_pair(0U, X86::GR16_ABCDRegisterClass);
15195 else if (VT == MVT::i8 || VT == MVT::i1)
15196 return std::make_pair(0U, X86::GR8_ABCD_LRegisterClass);
15197 else if (VT == MVT::i64)
15198 return std::make_pair(0U, X86::GR64_ABCDRegisterClass);
15200 case 'r': // GENERAL_REGS
15201 case 'l': // INDEX_REGS
15202 if (VT == MVT::i8 || VT == MVT::i1)
15203 return std::make_pair(0U, X86::GR8RegisterClass);
15204 if (VT == MVT::i16)
15205 return std::make_pair(0U, X86::GR16RegisterClass);
15206 if (VT == MVT::i32 || VT == MVT::f32 || !Subtarget->is64Bit())
15207 return std::make_pair(0U, X86::GR32RegisterClass);
15208 return std::make_pair(0U, X86::GR64RegisterClass);
15209 case 'R': // LEGACY_REGS
15210 if (VT == MVT::i8 || VT == MVT::i1)
15211 return std::make_pair(0U, X86::GR8_NOREXRegisterClass);
15212 if (VT == MVT::i16)
15213 return std::make_pair(0U, X86::GR16_NOREXRegisterClass);
15214 if (VT == MVT::i32 || !Subtarget->is64Bit())
15215 return std::make_pair(0U, X86::GR32_NOREXRegisterClass);
15216 return std::make_pair(0U, X86::GR64_NOREXRegisterClass);
15217 case 'f': // FP Stack registers.
15218 // If SSE is enabled for this VT, use f80 to ensure the isel moves the
15219 // value to the correct fpstack register class.
15220 if (VT == MVT::f32 && !isScalarFPTypeInSSEReg(VT))
15221 return std::make_pair(0U, X86::RFP32RegisterClass);
15222 if (VT == MVT::f64 && !isScalarFPTypeInSSEReg(VT))
15223 return std::make_pair(0U, X86::RFP64RegisterClass);
15224 return std::make_pair(0U, X86::RFP80RegisterClass);
15225 case 'y': // MMX_REGS if MMX allowed.
15226 if (!Subtarget->hasMMX()) break;
15227 return std::make_pair(0U, X86::VR64RegisterClass);
15228 case 'Y': // SSE_REGS if SSE2 allowed
15229 if (!Subtarget->hasSSE2()) break;
15231 case 'x': // SSE_REGS if SSE1 allowed or AVX_REGS if AVX allowed
15232 if (!Subtarget->hasSSE1()) break;
15234 switch (VT.getSimpleVT().SimpleTy) {
15236 // Scalar SSE types.
15239 return std::make_pair(0U, X86::FR32RegisterClass);
15242 return std::make_pair(0U, X86::FR64RegisterClass);
15250 return std::make_pair(0U, X86::VR128RegisterClass);
15258 return std::make_pair(0U, X86::VR256RegisterClass);
15265 // Use the default implementation in TargetLowering to convert the register
15266 // constraint into a member of a register class.
15267 std::pair<unsigned, const TargetRegisterClass*> Res;
15268 Res = TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
15270 // Not found as a standard register?
15271 if (Res.second == 0) {
15272 // Map st(0) -> st(7) -> ST0
15273 if (Constraint.size() == 7 && Constraint[0] == '{' &&
15274 tolower(Constraint[1]) == 's' &&
15275 tolower(Constraint[2]) == 't' &&
15276 Constraint[3] == '(' &&
15277 (Constraint[4] >= '0' && Constraint[4] <= '7') &&
15278 Constraint[5] == ')' &&
15279 Constraint[6] == '}') {
15281 Res.first = X86::ST0+Constraint[4]-'0';
15282 Res.second = X86::RFP80RegisterClass;
15286 // GCC allows "st(0)" to be called just plain "st".
15287 if (StringRef("{st}").equals_lower(Constraint)) {
15288 Res.first = X86::ST0;
15289 Res.second = X86::RFP80RegisterClass;
15294 if (StringRef("{flags}").equals_lower(Constraint)) {
15295 Res.first = X86::EFLAGS;
15296 Res.second = X86::CCRRegisterClass;
15300 // 'A' means EAX + EDX.
15301 if (Constraint == "A") {
15302 Res.first = X86::EAX;
15303 Res.second = X86::GR32_ADRegisterClass;
15309 // Otherwise, check to see if this is a register class of the wrong value
15310 // type. For example, we want to map "{ax},i32" -> {eax}, we don't want it to
15311 // turn into {ax},{dx}.
15312 if (Res.second->hasType(VT))
15313 return Res; // Correct type already, nothing to do.
15315 // All of the single-register GCC register classes map their values onto
15316 // 16-bit register pieces "ax","dx","cx","bx","si","di","bp","sp". If we
15317 // really want an 8-bit or 32-bit register, map to the appropriate register
15318 // class and return the appropriate register.
15319 if (Res.second == X86::GR16RegisterClass) {
15320 if (VT == MVT::i8) {
15321 unsigned DestReg = 0;
15322 switch (Res.first) {
15324 case X86::AX: DestReg = X86::AL; break;
15325 case X86::DX: DestReg = X86::DL; break;
15326 case X86::CX: DestReg = X86::CL; break;
15327 case X86::BX: DestReg = X86::BL; break;
15330 Res.first = DestReg;
15331 Res.second = X86::GR8RegisterClass;
15333 } else if (VT == MVT::i32) {
15334 unsigned DestReg = 0;
15335 switch (Res.first) {
15337 case X86::AX: DestReg = X86::EAX; break;
15338 case X86::DX: DestReg = X86::EDX; break;
15339 case X86::CX: DestReg = X86::ECX; break;
15340 case X86::BX: DestReg = X86::EBX; break;
15341 case X86::SI: DestReg = X86::ESI; break;
15342 case X86::DI: DestReg = X86::EDI; break;
15343 case X86::BP: DestReg = X86::EBP; break;
15344 case X86::SP: DestReg = X86::ESP; break;
15347 Res.first = DestReg;
15348 Res.second = X86::GR32RegisterClass;
15350 } else if (VT == MVT::i64) {
15351 unsigned DestReg = 0;
15352 switch (Res.first) {
15354 case X86::AX: DestReg = X86::RAX; break;
15355 case X86::DX: DestReg = X86::RDX; break;
15356 case X86::CX: DestReg = X86::RCX; break;
15357 case X86::BX: DestReg = X86::RBX; break;
15358 case X86::SI: DestReg = X86::RSI; break;
15359 case X86::DI: DestReg = X86::RDI; break;
15360 case X86::BP: DestReg = X86::RBP; break;
15361 case X86::SP: DestReg = X86::RSP; break;
15364 Res.first = DestReg;
15365 Res.second = X86::GR64RegisterClass;
15368 } else if (Res.second == X86::FR32RegisterClass ||
15369 Res.second == X86::FR64RegisterClass ||
15370 Res.second == X86::VR128RegisterClass) {
15371 // Handle references to XMM physical registers that got mapped into the
15372 // wrong class. This can happen with constraints like {xmm0} where the
15373 // target independent register mapper will just pick the first match it can
15374 // find, ignoring the required type.
15375 if (VT == MVT::f32)
15376 Res.second = X86::FR32RegisterClass;
15377 else if (VT == MVT::f64)
15378 Res.second = X86::FR64RegisterClass;
15379 else if (X86::VR128RegisterClass->hasType(VT))
15380 Res.second = X86::VR128RegisterClass;