1 //===-- X86ISelLowering.cpp - X86 DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that X86 uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #include "X86ISelLowering.h"
16 #include "Utils/X86ShuffleDecode.h"
17 #include "X86CallingConv.h"
18 #include "X86InstrBuilder.h"
19 #include "X86MachineFunctionInfo.h"
20 #include "X86TargetMachine.h"
21 #include "X86TargetObjectFile.h"
22 #include "llvm/ADT/SmallBitVector.h"
23 #include "llvm/ADT/SmallSet.h"
24 #include "llvm/ADT/Statistic.h"
25 #include "llvm/ADT/StringExtras.h"
26 #include "llvm/ADT/StringSwitch.h"
27 #include "llvm/ADT/VariadicFunction.h"
28 #include "llvm/CodeGen/IntrinsicLowering.h"
29 #include "llvm/CodeGen/MachineFrameInfo.h"
30 #include "llvm/CodeGen/MachineFunction.h"
31 #include "llvm/CodeGen/MachineInstrBuilder.h"
32 #include "llvm/CodeGen/MachineJumpTableInfo.h"
33 #include "llvm/CodeGen/MachineModuleInfo.h"
34 #include "llvm/CodeGen/MachineRegisterInfo.h"
35 #include "llvm/IR/CallSite.h"
36 #include "llvm/IR/CallingConv.h"
37 #include "llvm/IR/Constants.h"
38 #include "llvm/IR/DerivedTypes.h"
39 #include "llvm/IR/Function.h"
40 #include "llvm/IR/GlobalAlias.h"
41 #include "llvm/IR/GlobalVariable.h"
42 #include "llvm/IR/Instructions.h"
43 #include "llvm/IR/Intrinsics.h"
44 #include "llvm/MC/MCAsmInfo.h"
45 #include "llvm/MC/MCContext.h"
46 #include "llvm/MC/MCExpr.h"
47 #include "llvm/MC/MCSymbol.h"
48 #include "llvm/Support/CommandLine.h"
49 #include "llvm/Support/Debug.h"
50 #include "llvm/Support/ErrorHandling.h"
51 #include "llvm/Support/MathExtras.h"
52 #include "llvm/Target/TargetOptions.h"
53 #include "X86IntrinsicsInfo.h"
59 #define DEBUG_TYPE "x86-isel"
61 STATISTIC(NumTailCalls, "Number of tail calls");
63 static cl::opt<bool> ExperimentalVectorWideningLegalization(
64 "x86-experimental-vector-widening-legalization", cl::init(false),
65 cl::desc("Enable an experimental vector type legalization through widening "
66 "rather than promotion."),
69 static cl::opt<bool> ExperimentalVectorShuffleLowering(
70 "x86-experimental-vector-shuffle-lowering", cl::init(true),
71 cl::desc("Enable an experimental vector shuffle lowering code path."),
74 static cl::opt<int> ReciprocalEstimateRefinementSteps(
75 "x86-recip-refinement-steps", cl::init(1),
76 cl::desc("Specify the number of Newton-Raphson iterations applied to the "
77 "result of the hardware reciprocal estimate instruction."),
80 // Forward declarations.
81 static SDValue getMOVL(SelectionDAG &DAG, SDLoc dl, EVT VT, SDValue V1,
84 static SDValue ExtractSubVector(SDValue Vec, unsigned IdxVal,
85 SelectionDAG &DAG, SDLoc dl,
86 unsigned vectorWidth) {
87 assert((vectorWidth == 128 || vectorWidth == 256) &&
88 "Unsupported vector width");
89 EVT VT = Vec.getValueType();
90 EVT ElVT = VT.getVectorElementType();
91 unsigned Factor = VT.getSizeInBits()/vectorWidth;
92 EVT ResultVT = EVT::getVectorVT(*DAG.getContext(), ElVT,
93 VT.getVectorNumElements()/Factor);
95 // Extract from UNDEF is UNDEF.
96 if (Vec.getOpcode() == ISD::UNDEF)
97 return DAG.getUNDEF(ResultVT);
99 // Extract the relevant vectorWidth bits. Generate an EXTRACT_SUBVECTOR
100 unsigned ElemsPerChunk = vectorWidth / ElVT.getSizeInBits();
102 // This is the index of the first element of the vectorWidth-bit chunk
104 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits()) / vectorWidth)
107 // If the input is a buildvector just emit a smaller one.
108 if (Vec.getOpcode() == ISD::BUILD_VECTOR)
109 return DAG.getNode(ISD::BUILD_VECTOR, dl, ResultVT,
110 makeArrayRef(Vec->op_begin()+NormalizedIdxVal,
113 SDValue VecIdx = DAG.getIntPtrConstant(NormalizedIdxVal);
114 SDValue Result = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, ResultVT, Vec,
120 /// Generate a DAG to grab 128-bits from a vector > 128 bits. This
121 /// sets things up to match to an AVX VEXTRACTF128 / VEXTRACTI128
122 /// or AVX-512 VEXTRACTF32x4 / VEXTRACTI32x4
123 /// instructions or a simple subregister reference. Idx is an index in the
124 /// 128 bits we want. It need not be aligned to a 128-bit bounday. That makes
125 /// lowering EXTRACT_VECTOR_ELT operations easier.
126 static SDValue Extract128BitVector(SDValue Vec, unsigned IdxVal,
127 SelectionDAG &DAG, SDLoc dl) {
128 assert((Vec.getValueType().is256BitVector() ||
129 Vec.getValueType().is512BitVector()) && "Unexpected vector size!");
130 return ExtractSubVector(Vec, IdxVal, DAG, dl, 128);
133 /// Generate a DAG to grab 256-bits from a 512-bit vector.
134 static SDValue Extract256BitVector(SDValue Vec, unsigned IdxVal,
135 SelectionDAG &DAG, SDLoc dl) {
136 assert(Vec.getValueType().is512BitVector() && "Unexpected vector size!");
137 return ExtractSubVector(Vec, IdxVal, DAG, dl, 256);
140 static SDValue InsertSubVector(SDValue Result, SDValue Vec,
141 unsigned IdxVal, SelectionDAG &DAG,
142 SDLoc dl, unsigned vectorWidth) {
143 assert((vectorWidth == 128 || vectorWidth == 256) &&
144 "Unsupported vector width");
145 // Inserting UNDEF is Result
146 if (Vec.getOpcode() == ISD::UNDEF)
148 EVT VT = Vec.getValueType();
149 EVT ElVT = VT.getVectorElementType();
150 EVT ResultVT = Result.getValueType();
152 // Insert the relevant vectorWidth bits.
153 unsigned ElemsPerChunk = vectorWidth/ElVT.getSizeInBits();
155 // This is the index of the first element of the vectorWidth-bit chunk
157 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits())/vectorWidth)
160 SDValue VecIdx = DAG.getIntPtrConstant(NormalizedIdxVal);
161 return DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResultVT, Result, Vec,
164 /// Generate a DAG to put 128-bits into a vector > 128 bits. This
165 /// sets things up to match to an AVX VINSERTF128/VINSERTI128 or
166 /// AVX-512 VINSERTF32x4/VINSERTI32x4 instructions or a
167 /// simple superregister reference. Idx is an index in the 128 bits
168 /// we want. It need not be aligned to a 128-bit bounday. That makes
169 /// lowering INSERT_VECTOR_ELT operations easier.
170 static SDValue Insert128BitVector(SDValue Result, SDValue Vec,
171 unsigned IdxVal, SelectionDAG &DAG,
173 assert(Vec.getValueType().is128BitVector() && "Unexpected vector size!");
174 return InsertSubVector(Result, Vec, IdxVal, DAG, dl, 128);
177 static SDValue Insert256BitVector(SDValue Result, SDValue Vec,
178 unsigned IdxVal, SelectionDAG &DAG,
180 assert(Vec.getValueType().is256BitVector() && "Unexpected vector size!");
181 return InsertSubVector(Result, Vec, IdxVal, DAG, dl, 256);
184 /// Concat two 128-bit vectors into a 256 bit vector using VINSERTF128
185 /// instructions. This is used because creating CONCAT_VECTOR nodes of
186 /// BUILD_VECTORS returns a larger BUILD_VECTOR while we're trying to lower
187 /// large BUILD_VECTORS.
188 static SDValue Concat128BitVectors(SDValue V1, SDValue V2, EVT VT,
189 unsigned NumElems, SelectionDAG &DAG,
191 SDValue V = Insert128BitVector(DAG.getUNDEF(VT), V1, 0, DAG, dl);
192 return Insert128BitVector(V, V2, NumElems/2, DAG, dl);
195 static SDValue Concat256BitVectors(SDValue V1, SDValue V2, EVT VT,
196 unsigned NumElems, SelectionDAG &DAG,
198 SDValue V = Insert256BitVector(DAG.getUNDEF(VT), V1, 0, DAG, dl);
199 return Insert256BitVector(V, V2, NumElems/2, DAG, dl);
202 // FIXME: This should stop caching the target machine as soon as
203 // we can remove resetOperationActions et al.
204 X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM)
205 : TargetLowering(TM) {
206 Subtarget = &TM.getSubtarget<X86Subtarget>();
207 X86ScalarSSEf64 = Subtarget->hasSSE2();
208 X86ScalarSSEf32 = Subtarget->hasSSE1();
209 TD = getDataLayout();
211 resetOperationActions();
214 void X86TargetLowering::resetOperationActions() {
215 const TargetMachine &TM = getTargetMachine();
216 static bool FirstTimeThrough = true;
218 // If none of the target options have changed, then we don't need to reset the
219 // operation actions.
220 if (!FirstTimeThrough && TO == TM.Options) return;
222 if (!FirstTimeThrough) {
223 // Reinitialize the actions.
225 FirstTimeThrough = false;
230 // Set up the TargetLowering object.
231 static const MVT IntVTs[] = { MVT::i8, MVT::i16, MVT::i32, MVT::i64 };
233 // X86 is weird, it always uses i8 for shift amounts and setcc results.
234 setBooleanContents(ZeroOrOneBooleanContent);
235 // X86-SSE is even stranger. It uses -1 or 0 for vector masks.
236 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
238 // For 64-bit since we have so many registers use the ILP scheduler, for
239 // 32-bit code use the register pressure specific scheduling.
240 // For Atom, always use ILP scheduling.
241 if (Subtarget->isAtom())
242 setSchedulingPreference(Sched::ILP);
243 else if (Subtarget->is64Bit())
244 setSchedulingPreference(Sched::ILP);
246 setSchedulingPreference(Sched::RegPressure);
247 const X86RegisterInfo *RegInfo =
248 TM.getSubtarget<X86Subtarget>().getRegisterInfo();
249 setStackPointerRegisterToSaveRestore(RegInfo->getStackRegister());
251 // Bypass expensive divides on Atom when compiling with O2
252 if (TM.getOptLevel() >= CodeGenOpt::Default) {
253 if (Subtarget->hasSlowDivide32())
254 addBypassSlowDiv(32, 8);
255 if (Subtarget->hasSlowDivide64() && Subtarget->is64Bit())
256 addBypassSlowDiv(64, 16);
259 if (Subtarget->isTargetKnownWindowsMSVC()) {
260 // Setup Windows compiler runtime calls.
261 setLibcallName(RTLIB::SDIV_I64, "_alldiv");
262 setLibcallName(RTLIB::UDIV_I64, "_aulldiv");
263 setLibcallName(RTLIB::SREM_I64, "_allrem");
264 setLibcallName(RTLIB::UREM_I64, "_aullrem");
265 setLibcallName(RTLIB::MUL_I64, "_allmul");
266 setLibcallCallingConv(RTLIB::SDIV_I64, CallingConv::X86_StdCall);
267 setLibcallCallingConv(RTLIB::UDIV_I64, CallingConv::X86_StdCall);
268 setLibcallCallingConv(RTLIB::SREM_I64, CallingConv::X86_StdCall);
269 setLibcallCallingConv(RTLIB::UREM_I64, CallingConv::X86_StdCall);
270 setLibcallCallingConv(RTLIB::MUL_I64, CallingConv::X86_StdCall);
272 // The _ftol2 runtime function has an unusual calling conv, which
273 // is modeled by a special pseudo-instruction.
274 setLibcallName(RTLIB::FPTOUINT_F64_I64, nullptr);
275 setLibcallName(RTLIB::FPTOUINT_F32_I64, nullptr);
276 setLibcallName(RTLIB::FPTOUINT_F64_I32, nullptr);
277 setLibcallName(RTLIB::FPTOUINT_F32_I32, nullptr);
280 if (Subtarget->isTargetDarwin()) {
281 // Darwin should use _setjmp/_longjmp instead of setjmp/longjmp.
282 setUseUnderscoreSetJmp(false);
283 setUseUnderscoreLongJmp(false);
284 } else if (Subtarget->isTargetWindowsGNU()) {
285 // MS runtime is weird: it exports _setjmp, but longjmp!
286 setUseUnderscoreSetJmp(true);
287 setUseUnderscoreLongJmp(false);
289 setUseUnderscoreSetJmp(true);
290 setUseUnderscoreLongJmp(true);
293 // Set up the register classes.
294 addRegisterClass(MVT::i8, &X86::GR8RegClass);
295 addRegisterClass(MVT::i16, &X86::GR16RegClass);
296 addRegisterClass(MVT::i32, &X86::GR32RegClass);
297 if (Subtarget->is64Bit())
298 addRegisterClass(MVT::i64, &X86::GR64RegClass);
300 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
302 // We don't accept any truncstore of integer registers.
303 setTruncStoreAction(MVT::i64, MVT::i32, Expand);
304 setTruncStoreAction(MVT::i64, MVT::i16, Expand);
305 setTruncStoreAction(MVT::i64, MVT::i8 , Expand);
306 setTruncStoreAction(MVT::i32, MVT::i16, Expand);
307 setTruncStoreAction(MVT::i32, MVT::i8 , Expand);
308 setTruncStoreAction(MVT::i16, MVT::i8, Expand);
310 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
312 // SETOEQ and SETUNE require checking two conditions.
313 setCondCodeAction(ISD::SETOEQ, MVT::f32, Expand);
314 setCondCodeAction(ISD::SETOEQ, MVT::f64, Expand);
315 setCondCodeAction(ISD::SETOEQ, MVT::f80, Expand);
316 setCondCodeAction(ISD::SETUNE, MVT::f32, Expand);
317 setCondCodeAction(ISD::SETUNE, MVT::f64, Expand);
318 setCondCodeAction(ISD::SETUNE, MVT::f80, Expand);
320 // Promote all UINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have this
322 setOperationAction(ISD::UINT_TO_FP , MVT::i1 , Promote);
323 setOperationAction(ISD::UINT_TO_FP , MVT::i8 , Promote);
324 setOperationAction(ISD::UINT_TO_FP , MVT::i16 , Promote);
326 if (Subtarget->is64Bit()) {
327 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote);
328 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
329 } else if (!TM.Options.UseSoftFloat) {
330 // We have an algorithm for SSE2->double, and we turn this into a
331 // 64-bit FILD followed by conditional FADD for other targets.
332 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
333 // We have an algorithm for SSE2, and we turn this into a 64-bit
334 // FILD for other targets.
335 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Custom);
338 // Promote i1/i8 SINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have
340 setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote);
341 setOperationAction(ISD::SINT_TO_FP , MVT::i8 , Promote);
343 if (!TM.Options.UseSoftFloat) {
344 // SSE has no i16 to fp conversion, only i32
345 if (X86ScalarSSEf32) {
346 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
347 // f32 and f64 cases are Legal, f80 case is not
348 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
350 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Custom);
351 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
354 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
355 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Promote);
358 // In 32-bit mode these are custom lowered. In 64-bit mode F32 and F64
359 // are Legal, f80 is custom lowered.
360 setOperationAction(ISD::FP_TO_SINT , MVT::i64 , Custom);
361 setOperationAction(ISD::SINT_TO_FP , MVT::i64 , Custom);
363 // Promote i1/i8 FP_TO_SINT to larger FP_TO_SINTS's, as X86 doesn't have
365 setOperationAction(ISD::FP_TO_SINT , MVT::i1 , Promote);
366 setOperationAction(ISD::FP_TO_SINT , MVT::i8 , Promote);
368 if (X86ScalarSSEf32) {
369 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Promote);
370 // f32 and f64 cases are Legal, f80 case is not
371 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
373 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Custom);
374 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
377 // Handle FP_TO_UINT by promoting the destination to a larger signed
379 setOperationAction(ISD::FP_TO_UINT , MVT::i1 , Promote);
380 setOperationAction(ISD::FP_TO_UINT , MVT::i8 , Promote);
381 setOperationAction(ISD::FP_TO_UINT , MVT::i16 , Promote);
383 if (Subtarget->is64Bit()) {
384 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Expand);
385 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote);
386 } else if (!TM.Options.UseSoftFloat) {
387 // Since AVX is a superset of SSE3, only check for SSE here.
388 if (Subtarget->hasSSE1() && !Subtarget->hasSSE3())
389 // Expand FP_TO_UINT into a select.
390 // FIXME: We would like to use a Custom expander here eventually to do
391 // the optimal thing for SSE vs. the default expansion in the legalizer.
392 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Expand);
394 // With SSE3 we can use fisttpll to convert to a signed i64; without
395 // SSE, we're stuck with a fistpll.
396 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Custom);
399 if (isTargetFTOL()) {
400 // Use the _ftol2 runtime function, which has a pseudo-instruction
401 // to handle its weird calling convention.
402 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Custom);
405 // TODO: when we have SSE, these could be more efficient, by using movd/movq.
406 if (!X86ScalarSSEf64) {
407 setOperationAction(ISD::BITCAST , MVT::f32 , Expand);
408 setOperationAction(ISD::BITCAST , MVT::i32 , Expand);
409 if (Subtarget->is64Bit()) {
410 setOperationAction(ISD::BITCAST , MVT::f64 , Expand);
411 // Without SSE, i64->f64 goes through memory.
412 setOperationAction(ISD::BITCAST , MVT::i64 , Expand);
416 // Scalar integer divide and remainder are lowered to use operations that
417 // produce two results, to match the available instructions. This exposes
418 // the two-result form to trivial CSE, which is able to combine x/y and x%y
419 // into a single instruction.
421 // Scalar integer multiply-high is also lowered to use two-result
422 // operations, to match the available instructions. However, plain multiply
423 // (low) operations are left as Legal, as there are single-result
424 // instructions for this in x86. Using the two-result multiply instructions
425 // when both high and low results are needed must be arranged by dagcombine.
426 for (unsigned i = 0; i != array_lengthof(IntVTs); ++i) {
428 setOperationAction(ISD::MULHS, VT, Expand);
429 setOperationAction(ISD::MULHU, VT, Expand);
430 setOperationAction(ISD::SDIV, VT, Expand);
431 setOperationAction(ISD::UDIV, VT, Expand);
432 setOperationAction(ISD::SREM, VT, Expand);
433 setOperationAction(ISD::UREM, VT, Expand);
435 // Add/Sub overflow ops with MVT::Glues are lowered to EFLAGS dependences.
436 setOperationAction(ISD::ADDC, VT, Custom);
437 setOperationAction(ISD::ADDE, VT, Custom);
438 setOperationAction(ISD::SUBC, VT, Custom);
439 setOperationAction(ISD::SUBE, VT, Custom);
442 setOperationAction(ISD::BR_JT , MVT::Other, Expand);
443 setOperationAction(ISD::BRCOND , MVT::Other, Custom);
444 setOperationAction(ISD::BR_CC , MVT::f32, Expand);
445 setOperationAction(ISD::BR_CC , MVT::f64, Expand);
446 setOperationAction(ISD::BR_CC , MVT::f80, Expand);
447 setOperationAction(ISD::BR_CC , MVT::i8, Expand);
448 setOperationAction(ISD::BR_CC , MVT::i16, Expand);
449 setOperationAction(ISD::BR_CC , MVT::i32, Expand);
450 setOperationAction(ISD::BR_CC , MVT::i64, Expand);
451 setOperationAction(ISD::SELECT_CC , MVT::f32, Expand);
452 setOperationAction(ISD::SELECT_CC , MVT::f64, Expand);
453 setOperationAction(ISD::SELECT_CC , MVT::f80, Expand);
454 setOperationAction(ISD::SELECT_CC , MVT::i8, Expand);
455 setOperationAction(ISD::SELECT_CC , MVT::i16, Expand);
456 setOperationAction(ISD::SELECT_CC , MVT::i32, Expand);
457 setOperationAction(ISD::SELECT_CC , MVT::i64, Expand);
458 if (Subtarget->is64Bit())
459 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal);
460 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Legal);
461 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Legal);
462 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
463 setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand);
464 setOperationAction(ISD::FREM , MVT::f32 , Expand);
465 setOperationAction(ISD::FREM , MVT::f64 , Expand);
466 setOperationAction(ISD::FREM , MVT::f80 , Expand);
467 setOperationAction(ISD::FLT_ROUNDS_ , MVT::i32 , Custom);
469 // Promote the i8 variants and force them on up to i32 which has a shorter
471 setOperationAction(ISD::CTTZ , MVT::i8 , Promote);
472 AddPromotedToType (ISD::CTTZ , MVT::i8 , MVT::i32);
473 setOperationAction(ISD::CTTZ_ZERO_UNDEF , MVT::i8 , Promote);
474 AddPromotedToType (ISD::CTTZ_ZERO_UNDEF , MVT::i8 , MVT::i32);
475 if (Subtarget->hasBMI()) {
476 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i16 , Expand);
477 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32 , Expand);
478 if (Subtarget->is64Bit())
479 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand);
481 setOperationAction(ISD::CTTZ , MVT::i16 , Custom);
482 setOperationAction(ISD::CTTZ , MVT::i32 , Custom);
483 if (Subtarget->is64Bit())
484 setOperationAction(ISD::CTTZ , MVT::i64 , Custom);
487 if (Subtarget->hasLZCNT()) {
488 // When promoting the i8 variants, force them to i32 for a shorter
490 setOperationAction(ISD::CTLZ , MVT::i8 , Promote);
491 AddPromotedToType (ISD::CTLZ , MVT::i8 , MVT::i32);
492 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Promote);
493 AddPromotedToType (ISD::CTLZ_ZERO_UNDEF, MVT::i8 , MVT::i32);
494 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Expand);
495 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Expand);
496 if (Subtarget->is64Bit())
497 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Expand);
499 setOperationAction(ISD::CTLZ , MVT::i8 , Custom);
500 setOperationAction(ISD::CTLZ , MVT::i16 , Custom);
501 setOperationAction(ISD::CTLZ , MVT::i32 , Custom);
502 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Custom);
503 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Custom);
504 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Custom);
505 if (Subtarget->is64Bit()) {
506 setOperationAction(ISD::CTLZ , MVT::i64 , Custom);
507 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Custom);
511 // Special handling for half-precision floating point conversions.
512 // If we don't have F16C support, then lower half float conversions
513 // into library calls.
514 if (TM.Options.UseSoftFloat || !Subtarget->hasF16C()) {
515 setOperationAction(ISD::FP16_TO_FP, MVT::f32, Expand);
516 setOperationAction(ISD::FP_TO_FP16, MVT::f32, Expand);
519 // There's never any support for operations beyond MVT::f32.
520 setOperationAction(ISD::FP16_TO_FP, MVT::f64, Expand);
521 setOperationAction(ISD::FP16_TO_FP, MVT::f80, Expand);
522 setOperationAction(ISD::FP_TO_FP16, MVT::f64, Expand);
523 setOperationAction(ISD::FP_TO_FP16, MVT::f80, Expand);
525 setLoadExtAction(ISD::EXTLOAD, MVT::f16, Expand);
526 setTruncStoreAction(MVT::f32, MVT::f16, Expand);
527 setTruncStoreAction(MVT::f64, MVT::f16, Expand);
528 setTruncStoreAction(MVT::f80, MVT::f16, Expand);
530 if (Subtarget->hasPOPCNT()) {
531 setOperationAction(ISD::CTPOP , MVT::i8 , Promote);
533 setOperationAction(ISD::CTPOP , MVT::i8 , Expand);
534 setOperationAction(ISD::CTPOP , MVT::i16 , Expand);
535 setOperationAction(ISD::CTPOP , MVT::i32 , Expand);
536 if (Subtarget->is64Bit())
537 setOperationAction(ISD::CTPOP , MVT::i64 , Expand);
540 setOperationAction(ISD::READCYCLECOUNTER , MVT::i64 , Custom);
542 if (!Subtarget->hasMOVBE())
543 setOperationAction(ISD::BSWAP , MVT::i16 , Expand);
545 // These should be promoted to a larger select which is supported.
546 setOperationAction(ISD::SELECT , MVT::i1 , Promote);
547 // X86 wants to expand cmov itself.
548 setOperationAction(ISD::SELECT , MVT::i8 , Custom);
549 setOperationAction(ISD::SELECT , MVT::i16 , Custom);
550 setOperationAction(ISD::SELECT , MVT::i32 , Custom);
551 setOperationAction(ISD::SELECT , MVT::f32 , Custom);
552 setOperationAction(ISD::SELECT , MVT::f64 , Custom);
553 setOperationAction(ISD::SELECT , MVT::f80 , Custom);
554 setOperationAction(ISD::SETCC , MVT::i8 , Custom);
555 setOperationAction(ISD::SETCC , MVT::i16 , Custom);
556 setOperationAction(ISD::SETCC , MVT::i32 , Custom);
557 setOperationAction(ISD::SETCC , MVT::f32 , Custom);
558 setOperationAction(ISD::SETCC , MVT::f64 , Custom);
559 setOperationAction(ISD::SETCC , MVT::f80 , Custom);
560 if (Subtarget->is64Bit()) {
561 setOperationAction(ISD::SELECT , MVT::i64 , Custom);
562 setOperationAction(ISD::SETCC , MVT::i64 , Custom);
564 setOperationAction(ISD::EH_RETURN , MVT::Other, Custom);
565 // NOTE: EH_SJLJ_SETJMP/_LONGJMP supported here is NOT intended to support
566 // SjLj exception handling but a light-weight setjmp/longjmp replacement to
567 // support continuation, user-level threading, and etc.. As a result, no
568 // other SjLj exception interfaces are implemented and please don't build
569 // your own exception handling based on them.
570 // LLVM/Clang supports zero-cost DWARF exception handling.
571 setOperationAction(ISD::EH_SJLJ_SETJMP, MVT::i32, Custom);
572 setOperationAction(ISD::EH_SJLJ_LONGJMP, MVT::Other, Custom);
575 setOperationAction(ISD::ConstantPool , MVT::i32 , Custom);
576 setOperationAction(ISD::JumpTable , MVT::i32 , Custom);
577 setOperationAction(ISD::GlobalAddress , MVT::i32 , Custom);
578 setOperationAction(ISD::GlobalTLSAddress, MVT::i32 , Custom);
579 if (Subtarget->is64Bit())
580 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
581 setOperationAction(ISD::ExternalSymbol , MVT::i32 , Custom);
582 setOperationAction(ISD::BlockAddress , MVT::i32 , Custom);
583 if (Subtarget->is64Bit()) {
584 setOperationAction(ISD::ConstantPool , MVT::i64 , Custom);
585 setOperationAction(ISD::JumpTable , MVT::i64 , Custom);
586 setOperationAction(ISD::GlobalAddress , MVT::i64 , Custom);
587 setOperationAction(ISD::ExternalSymbol, MVT::i64 , Custom);
588 setOperationAction(ISD::BlockAddress , MVT::i64 , Custom);
590 // 64-bit addm sub, shl, sra, srl (iff 32-bit x86)
591 setOperationAction(ISD::SHL_PARTS , MVT::i32 , Custom);
592 setOperationAction(ISD::SRA_PARTS , MVT::i32 , Custom);
593 setOperationAction(ISD::SRL_PARTS , MVT::i32 , Custom);
594 if (Subtarget->is64Bit()) {
595 setOperationAction(ISD::SHL_PARTS , MVT::i64 , Custom);
596 setOperationAction(ISD::SRA_PARTS , MVT::i64 , Custom);
597 setOperationAction(ISD::SRL_PARTS , MVT::i64 , Custom);
600 if (Subtarget->hasSSE1())
601 setOperationAction(ISD::PREFETCH , MVT::Other, Legal);
603 setOperationAction(ISD::ATOMIC_FENCE , MVT::Other, Custom);
605 // Expand certain atomics
606 for (unsigned i = 0; i != array_lengthof(IntVTs); ++i) {
608 setOperationAction(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, VT, Custom);
609 setOperationAction(ISD::ATOMIC_LOAD_SUB, VT, Custom);
610 setOperationAction(ISD::ATOMIC_STORE, VT, Custom);
613 if (Subtarget->hasCmpxchg16b()) {
614 setOperationAction(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, MVT::i128, Custom);
617 // FIXME - use subtarget debug flags
618 if (!Subtarget->isTargetDarwin() && !Subtarget->isTargetELF() &&
619 !Subtarget->isTargetCygMing() && !Subtarget->isTargetWin64()) {
620 setOperationAction(ISD::EH_LABEL, MVT::Other, Expand);
623 if (Subtarget->is64Bit()) {
624 setExceptionPointerRegister(X86::RAX);
625 setExceptionSelectorRegister(X86::RDX);
627 setExceptionPointerRegister(X86::EAX);
628 setExceptionSelectorRegister(X86::EDX);
630 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i32, Custom);
631 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i64, Custom);
633 setOperationAction(ISD::INIT_TRAMPOLINE, MVT::Other, Custom);
634 setOperationAction(ISD::ADJUST_TRAMPOLINE, MVT::Other, Custom);
636 setOperationAction(ISD::TRAP, MVT::Other, Legal);
637 setOperationAction(ISD::DEBUGTRAP, MVT::Other, Legal);
639 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
640 setOperationAction(ISD::VASTART , MVT::Other, Custom);
641 setOperationAction(ISD::VAEND , MVT::Other, Expand);
642 if (Subtarget->is64Bit() && !Subtarget->isTargetWin64()) {
643 // TargetInfo::X86_64ABIBuiltinVaList
644 setOperationAction(ISD::VAARG , MVT::Other, Custom);
645 setOperationAction(ISD::VACOPY , MVT::Other, Custom);
647 // TargetInfo::CharPtrBuiltinVaList
648 setOperationAction(ISD::VAARG , MVT::Other, Expand);
649 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
652 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
653 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
655 setOperationAction(ISD::DYNAMIC_STACKALLOC, getPointerTy(), Custom);
657 if (!TM.Options.UseSoftFloat && X86ScalarSSEf64) {
658 // f32 and f64 use SSE.
659 // Set up the FP register classes.
660 addRegisterClass(MVT::f32, &X86::FR32RegClass);
661 addRegisterClass(MVT::f64, &X86::FR64RegClass);
663 // Use ANDPD to simulate FABS.
664 setOperationAction(ISD::FABS , MVT::f64, Custom);
665 setOperationAction(ISD::FABS , MVT::f32, Custom);
667 // Use XORP to simulate FNEG.
668 setOperationAction(ISD::FNEG , MVT::f64, Custom);
669 setOperationAction(ISD::FNEG , MVT::f32, Custom);
671 // Use ANDPD and ORPD to simulate FCOPYSIGN.
672 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
673 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
675 // Lower this to FGETSIGNx86 plus an AND.
676 setOperationAction(ISD::FGETSIGN, MVT::i64, Custom);
677 setOperationAction(ISD::FGETSIGN, MVT::i32, Custom);
679 // We don't support sin/cos/fmod
680 setOperationAction(ISD::FSIN , MVT::f64, Expand);
681 setOperationAction(ISD::FCOS , MVT::f64, Expand);
682 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
683 setOperationAction(ISD::FSIN , MVT::f32, Expand);
684 setOperationAction(ISD::FCOS , MVT::f32, Expand);
685 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
687 // Expand FP immediates into loads from the stack, except for the special
689 addLegalFPImmediate(APFloat(+0.0)); // xorpd
690 addLegalFPImmediate(APFloat(+0.0f)); // xorps
691 } else if (!TM.Options.UseSoftFloat && X86ScalarSSEf32) {
692 // Use SSE for f32, x87 for f64.
693 // Set up the FP register classes.
694 addRegisterClass(MVT::f32, &X86::FR32RegClass);
695 addRegisterClass(MVT::f64, &X86::RFP64RegClass);
697 // Use ANDPS to simulate FABS.
698 setOperationAction(ISD::FABS , MVT::f32, Custom);
700 // Use XORP to simulate FNEG.
701 setOperationAction(ISD::FNEG , MVT::f32, Custom);
703 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
705 // Use ANDPS and ORPS to simulate FCOPYSIGN.
706 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
707 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
709 // We don't support sin/cos/fmod
710 setOperationAction(ISD::FSIN , MVT::f32, Expand);
711 setOperationAction(ISD::FCOS , MVT::f32, Expand);
712 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
714 // Special cases we handle for FP constants.
715 addLegalFPImmediate(APFloat(+0.0f)); // xorps
716 addLegalFPImmediate(APFloat(+0.0)); // FLD0
717 addLegalFPImmediate(APFloat(+1.0)); // FLD1
718 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
719 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
721 if (!TM.Options.UnsafeFPMath) {
722 setOperationAction(ISD::FSIN , MVT::f64, Expand);
723 setOperationAction(ISD::FCOS , MVT::f64, Expand);
724 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
726 } else if (!TM.Options.UseSoftFloat) {
727 // f32 and f64 in x87.
728 // Set up the FP register classes.
729 addRegisterClass(MVT::f64, &X86::RFP64RegClass);
730 addRegisterClass(MVT::f32, &X86::RFP32RegClass);
732 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
733 setOperationAction(ISD::UNDEF, MVT::f32, Expand);
734 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
735 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
737 if (!TM.Options.UnsafeFPMath) {
738 setOperationAction(ISD::FSIN , MVT::f64, Expand);
739 setOperationAction(ISD::FSIN , MVT::f32, Expand);
740 setOperationAction(ISD::FCOS , MVT::f64, Expand);
741 setOperationAction(ISD::FCOS , MVT::f32, Expand);
742 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
743 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
745 addLegalFPImmediate(APFloat(+0.0)); // FLD0
746 addLegalFPImmediate(APFloat(+1.0)); // FLD1
747 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
748 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
749 addLegalFPImmediate(APFloat(+0.0f)); // FLD0
750 addLegalFPImmediate(APFloat(+1.0f)); // FLD1
751 addLegalFPImmediate(APFloat(-0.0f)); // FLD0/FCHS
752 addLegalFPImmediate(APFloat(-1.0f)); // FLD1/FCHS
755 // We don't support FMA.
756 setOperationAction(ISD::FMA, MVT::f64, Expand);
757 setOperationAction(ISD::FMA, MVT::f32, Expand);
759 // Long double always uses X87.
760 if (!TM.Options.UseSoftFloat) {
761 addRegisterClass(MVT::f80, &X86::RFP80RegClass);
762 setOperationAction(ISD::UNDEF, MVT::f80, Expand);
763 setOperationAction(ISD::FCOPYSIGN, MVT::f80, Expand);
765 APFloat TmpFlt = APFloat::getZero(APFloat::x87DoubleExtended);
766 addLegalFPImmediate(TmpFlt); // FLD0
768 addLegalFPImmediate(TmpFlt); // FLD0/FCHS
771 APFloat TmpFlt2(+1.0);
772 TmpFlt2.convert(APFloat::x87DoubleExtended, APFloat::rmNearestTiesToEven,
774 addLegalFPImmediate(TmpFlt2); // FLD1
775 TmpFlt2.changeSign();
776 addLegalFPImmediate(TmpFlt2); // FLD1/FCHS
779 if (!TM.Options.UnsafeFPMath) {
780 setOperationAction(ISD::FSIN , MVT::f80, Expand);
781 setOperationAction(ISD::FCOS , MVT::f80, Expand);
782 setOperationAction(ISD::FSINCOS, MVT::f80, Expand);
785 setOperationAction(ISD::FFLOOR, MVT::f80, Expand);
786 setOperationAction(ISD::FCEIL, MVT::f80, Expand);
787 setOperationAction(ISD::FTRUNC, MVT::f80, Expand);
788 setOperationAction(ISD::FRINT, MVT::f80, Expand);
789 setOperationAction(ISD::FNEARBYINT, MVT::f80, Expand);
790 setOperationAction(ISD::FMA, MVT::f80, Expand);
793 // Always use a library call for pow.
794 setOperationAction(ISD::FPOW , MVT::f32 , Expand);
795 setOperationAction(ISD::FPOW , MVT::f64 , Expand);
796 setOperationAction(ISD::FPOW , MVT::f80 , Expand);
798 setOperationAction(ISD::FLOG, MVT::f80, Expand);
799 setOperationAction(ISD::FLOG2, MVT::f80, Expand);
800 setOperationAction(ISD::FLOG10, MVT::f80, Expand);
801 setOperationAction(ISD::FEXP, MVT::f80, Expand);
802 setOperationAction(ISD::FEXP2, MVT::f80, Expand);
803 setOperationAction(ISD::FMINNUM, MVT::f80, Expand);
804 setOperationAction(ISD::FMAXNUM, MVT::f80, Expand);
806 // First set operation action for all vector types to either promote
807 // (for widening) or expand (for scalarization). Then we will selectively
808 // turn on ones that can be effectively codegen'd.
809 for (int i = MVT::FIRST_VECTOR_VALUETYPE;
810 i <= MVT::LAST_VECTOR_VALUETYPE; ++i) {
811 MVT VT = (MVT::SimpleValueType)i;
812 setOperationAction(ISD::ADD , VT, Expand);
813 setOperationAction(ISD::SUB , VT, Expand);
814 setOperationAction(ISD::FADD, VT, Expand);
815 setOperationAction(ISD::FNEG, VT, Expand);
816 setOperationAction(ISD::FSUB, VT, Expand);
817 setOperationAction(ISD::MUL , VT, Expand);
818 setOperationAction(ISD::FMUL, VT, Expand);
819 setOperationAction(ISD::SDIV, VT, Expand);
820 setOperationAction(ISD::UDIV, VT, Expand);
821 setOperationAction(ISD::FDIV, VT, Expand);
822 setOperationAction(ISD::SREM, VT, Expand);
823 setOperationAction(ISD::UREM, VT, Expand);
824 setOperationAction(ISD::LOAD, VT, Expand);
825 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Expand);
826 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT,Expand);
827 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Expand);
828 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT,Expand);
829 setOperationAction(ISD::INSERT_SUBVECTOR, VT,Expand);
830 setOperationAction(ISD::FABS, VT, Expand);
831 setOperationAction(ISD::FSIN, VT, Expand);
832 setOperationAction(ISD::FSINCOS, VT, Expand);
833 setOperationAction(ISD::FCOS, VT, Expand);
834 setOperationAction(ISD::FSINCOS, VT, Expand);
835 setOperationAction(ISD::FREM, VT, Expand);
836 setOperationAction(ISD::FMA, VT, Expand);
837 setOperationAction(ISD::FPOWI, VT, Expand);
838 setOperationAction(ISD::FSQRT, VT, Expand);
839 setOperationAction(ISD::FCOPYSIGN, VT, Expand);
840 setOperationAction(ISD::FFLOOR, VT, Expand);
841 setOperationAction(ISD::FCEIL, VT, Expand);
842 setOperationAction(ISD::FTRUNC, VT, Expand);
843 setOperationAction(ISD::FRINT, VT, Expand);
844 setOperationAction(ISD::FNEARBYINT, VT, Expand);
845 setOperationAction(ISD::SMUL_LOHI, VT, Expand);
846 setOperationAction(ISD::MULHS, VT, Expand);
847 setOperationAction(ISD::UMUL_LOHI, VT, Expand);
848 setOperationAction(ISD::MULHU, VT, Expand);
849 setOperationAction(ISD::SDIVREM, VT, Expand);
850 setOperationAction(ISD::UDIVREM, VT, Expand);
851 setOperationAction(ISD::FPOW, VT, Expand);
852 setOperationAction(ISD::CTPOP, VT, Expand);
853 setOperationAction(ISD::CTTZ, VT, Expand);
854 setOperationAction(ISD::CTTZ_ZERO_UNDEF, VT, Expand);
855 setOperationAction(ISD::CTLZ, VT, Expand);
856 setOperationAction(ISD::CTLZ_ZERO_UNDEF, VT, Expand);
857 setOperationAction(ISD::SHL, VT, Expand);
858 setOperationAction(ISD::SRA, VT, Expand);
859 setOperationAction(ISD::SRL, VT, Expand);
860 setOperationAction(ISD::ROTL, VT, Expand);
861 setOperationAction(ISD::ROTR, VT, Expand);
862 setOperationAction(ISD::BSWAP, VT, Expand);
863 setOperationAction(ISD::SETCC, VT, Expand);
864 setOperationAction(ISD::FLOG, VT, Expand);
865 setOperationAction(ISD::FLOG2, VT, Expand);
866 setOperationAction(ISD::FLOG10, VT, Expand);
867 setOperationAction(ISD::FEXP, VT, Expand);
868 setOperationAction(ISD::FEXP2, VT, Expand);
869 setOperationAction(ISD::FP_TO_UINT, VT, Expand);
870 setOperationAction(ISD::FP_TO_SINT, VT, Expand);
871 setOperationAction(ISD::UINT_TO_FP, VT, Expand);
872 setOperationAction(ISD::SINT_TO_FP, VT, Expand);
873 setOperationAction(ISD::SIGN_EXTEND_INREG, VT,Expand);
874 setOperationAction(ISD::TRUNCATE, VT, Expand);
875 setOperationAction(ISD::SIGN_EXTEND, VT, Expand);
876 setOperationAction(ISD::ZERO_EXTEND, VT, Expand);
877 setOperationAction(ISD::ANY_EXTEND, VT, Expand);
878 setOperationAction(ISD::VSELECT, VT, Expand);
879 setOperationAction(ISD::SELECT_CC, VT, Expand);
880 for (int InnerVT = MVT::FIRST_VECTOR_VALUETYPE;
881 InnerVT <= MVT::LAST_VECTOR_VALUETYPE; ++InnerVT)
882 setTruncStoreAction(VT,
883 (MVT::SimpleValueType)InnerVT, Expand);
884 setLoadExtAction(ISD::SEXTLOAD, VT, Expand);
885 setLoadExtAction(ISD::ZEXTLOAD, VT, Expand);
887 // N.b. ISD::EXTLOAD legality is basically ignored except for i1-like types,
888 // we have to deal with them whether we ask for Expansion or not. Setting
889 // Expand causes its own optimisation problems though, so leave them legal.
890 if (VT.getVectorElementType() == MVT::i1)
891 setLoadExtAction(ISD::EXTLOAD, VT, Expand);
894 // FIXME: In order to prevent SSE instructions being expanded to MMX ones
895 // with -msoft-float, disable use of MMX as well.
896 if (!TM.Options.UseSoftFloat && Subtarget->hasMMX()) {
897 addRegisterClass(MVT::x86mmx, &X86::VR64RegClass);
898 // No operations on x86mmx supported, everything uses intrinsics.
901 // MMX-sized vectors (other than x86mmx) are expected to be expanded
902 // into smaller operations.
903 setOperationAction(ISD::MULHS, MVT::v8i8, Expand);
904 setOperationAction(ISD::MULHS, MVT::v4i16, Expand);
905 setOperationAction(ISD::MULHS, MVT::v2i32, Expand);
906 setOperationAction(ISD::MULHS, MVT::v1i64, Expand);
907 setOperationAction(ISD::AND, MVT::v8i8, Expand);
908 setOperationAction(ISD::AND, MVT::v4i16, Expand);
909 setOperationAction(ISD::AND, MVT::v2i32, Expand);
910 setOperationAction(ISD::AND, MVT::v1i64, Expand);
911 setOperationAction(ISD::OR, MVT::v8i8, Expand);
912 setOperationAction(ISD::OR, MVT::v4i16, Expand);
913 setOperationAction(ISD::OR, MVT::v2i32, Expand);
914 setOperationAction(ISD::OR, MVT::v1i64, Expand);
915 setOperationAction(ISD::XOR, MVT::v8i8, Expand);
916 setOperationAction(ISD::XOR, MVT::v4i16, Expand);
917 setOperationAction(ISD::XOR, MVT::v2i32, Expand);
918 setOperationAction(ISD::XOR, MVT::v1i64, Expand);
919 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i8, Expand);
920 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i16, Expand);
921 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2i32, Expand);
922 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v1i64, Expand);
923 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v1i64, Expand);
924 setOperationAction(ISD::SELECT, MVT::v8i8, Expand);
925 setOperationAction(ISD::SELECT, MVT::v4i16, Expand);
926 setOperationAction(ISD::SELECT, MVT::v2i32, Expand);
927 setOperationAction(ISD::SELECT, MVT::v1i64, Expand);
928 setOperationAction(ISD::BITCAST, MVT::v8i8, Expand);
929 setOperationAction(ISD::BITCAST, MVT::v4i16, Expand);
930 setOperationAction(ISD::BITCAST, MVT::v2i32, Expand);
931 setOperationAction(ISD::BITCAST, MVT::v1i64, Expand);
933 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE1()) {
934 addRegisterClass(MVT::v4f32, &X86::VR128RegClass);
936 setOperationAction(ISD::FADD, MVT::v4f32, Legal);
937 setOperationAction(ISD::FSUB, MVT::v4f32, Legal);
938 setOperationAction(ISD::FMUL, MVT::v4f32, Legal);
939 setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
940 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal);
941 setOperationAction(ISD::FNEG, MVT::v4f32, Custom);
942 setOperationAction(ISD::FABS, MVT::v4f32, Custom);
943 setOperationAction(ISD::LOAD, MVT::v4f32, Legal);
944 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
945 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f32, Custom);
946 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
947 setOperationAction(ISD::SELECT, MVT::v4f32, Custom);
948 setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Custom);
951 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE2()) {
952 addRegisterClass(MVT::v2f64, &X86::VR128RegClass);
954 // FIXME: Unfortunately, -soft-float and -no-implicit-float mean XMM
955 // registers cannot be used even for integer operations.
956 addRegisterClass(MVT::v16i8, &X86::VR128RegClass);
957 addRegisterClass(MVT::v8i16, &X86::VR128RegClass);
958 addRegisterClass(MVT::v4i32, &X86::VR128RegClass);
959 addRegisterClass(MVT::v2i64, &X86::VR128RegClass);
961 setOperationAction(ISD::ADD, MVT::v16i8, Legal);
962 setOperationAction(ISD::ADD, MVT::v8i16, Legal);
963 setOperationAction(ISD::ADD, MVT::v4i32, Legal);
964 setOperationAction(ISD::ADD, MVT::v2i64, Legal);
965 setOperationAction(ISD::MUL, MVT::v4i32, Custom);
966 setOperationAction(ISD::MUL, MVT::v2i64, Custom);
967 setOperationAction(ISD::UMUL_LOHI, MVT::v4i32, Custom);
968 setOperationAction(ISD::SMUL_LOHI, MVT::v4i32, Custom);
969 setOperationAction(ISD::MULHU, MVT::v8i16, Legal);
970 setOperationAction(ISD::MULHS, MVT::v8i16, Legal);
971 setOperationAction(ISD::SUB, MVT::v16i8, Legal);
972 setOperationAction(ISD::SUB, MVT::v8i16, Legal);
973 setOperationAction(ISD::SUB, MVT::v4i32, Legal);
974 setOperationAction(ISD::SUB, MVT::v2i64, Legal);
975 setOperationAction(ISD::MUL, MVT::v8i16, Legal);
976 setOperationAction(ISD::FADD, MVT::v2f64, Legal);
977 setOperationAction(ISD::FSUB, MVT::v2f64, Legal);
978 setOperationAction(ISD::FMUL, MVT::v2f64, Legal);
979 setOperationAction(ISD::FDIV, MVT::v2f64, Legal);
980 setOperationAction(ISD::FSQRT, MVT::v2f64, Legal);
981 setOperationAction(ISD::FNEG, MVT::v2f64, Custom);
982 setOperationAction(ISD::FABS, MVT::v2f64, Custom);
984 setOperationAction(ISD::SETCC, MVT::v2i64, Custom);
985 setOperationAction(ISD::SETCC, MVT::v16i8, Custom);
986 setOperationAction(ISD::SETCC, MVT::v8i16, Custom);
987 setOperationAction(ISD::SETCC, MVT::v4i32, Custom);
989 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Custom);
990 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Custom);
991 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
992 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
993 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
995 // Custom lower build_vector, vector_shuffle, and extract_vector_elt.
996 for (int i = MVT::v16i8; i != MVT::v2i64; ++i) {
997 MVT VT = (MVT::SimpleValueType)i;
998 // Do not attempt to custom lower non-power-of-2 vectors
999 if (!isPowerOf2_32(VT.getVectorNumElements()))
1001 // Do not attempt to custom lower non-128-bit vectors
1002 if (!VT.is128BitVector())
1004 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1005 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1006 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1009 // We support custom legalizing of sext and anyext loads for specific
1010 // memory vector types which we can load as a scalar (or sequence of
1011 // scalars) and extend in-register to a legal 128-bit vector type. For sext
1012 // loads these must work with a single scalar load.
1013 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i8, Custom);
1014 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i16, Custom);
1015 setLoadExtAction(ISD::SEXTLOAD, MVT::v8i8, Custom);
1016 setLoadExtAction(ISD::EXTLOAD, MVT::v2i8, Custom);
1017 setLoadExtAction(ISD::EXTLOAD, MVT::v2i16, Custom);
1018 setLoadExtAction(ISD::EXTLOAD, MVT::v2i32, Custom);
1019 setLoadExtAction(ISD::EXTLOAD, MVT::v4i8, Custom);
1020 setLoadExtAction(ISD::EXTLOAD, MVT::v4i16, Custom);
1021 setLoadExtAction(ISD::EXTLOAD, MVT::v8i8, Custom);
1023 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f64, Custom);
1024 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i64, Custom);
1025 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Custom);
1026 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Custom);
1027 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f64, Custom);
1028 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Custom);
1030 if (Subtarget->is64Bit()) {
1031 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
1032 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
1035 // Promote v16i8, v8i16, v4i32 load, select, and, or, xor to v2i64.
1036 for (int i = MVT::v16i8; i != MVT::v2i64; ++i) {
1037 MVT VT = (MVT::SimpleValueType)i;
1039 // Do not attempt to promote non-128-bit vectors
1040 if (!VT.is128BitVector())
1043 setOperationAction(ISD::AND, VT, Promote);
1044 AddPromotedToType (ISD::AND, VT, MVT::v2i64);
1045 setOperationAction(ISD::OR, VT, Promote);
1046 AddPromotedToType (ISD::OR, VT, MVT::v2i64);
1047 setOperationAction(ISD::XOR, VT, Promote);
1048 AddPromotedToType (ISD::XOR, VT, MVT::v2i64);
1049 setOperationAction(ISD::LOAD, VT, Promote);
1050 AddPromotedToType (ISD::LOAD, VT, MVT::v2i64);
1051 setOperationAction(ISD::SELECT, VT, Promote);
1052 AddPromotedToType (ISD::SELECT, VT, MVT::v2i64);
1055 // Custom lower v2i64 and v2f64 selects.
1056 setOperationAction(ISD::LOAD, MVT::v2f64, Legal);
1057 setOperationAction(ISD::LOAD, MVT::v2i64, Legal);
1058 setOperationAction(ISD::SELECT, MVT::v2f64, Custom);
1059 setOperationAction(ISD::SELECT, MVT::v2i64, Custom);
1061 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal);
1062 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal);
1064 setOperationAction(ISD::UINT_TO_FP, MVT::v4i8, Custom);
1065 setOperationAction(ISD::UINT_TO_FP, MVT::v4i16, Custom);
1066 // As there is no 64-bit GPR available, we need build a special custom
1067 // sequence to convert from v2i32 to v2f32.
1068 if (!Subtarget->is64Bit())
1069 setOperationAction(ISD::UINT_TO_FP, MVT::v2f32, Custom);
1071 setOperationAction(ISD::FP_EXTEND, MVT::v2f32, Custom);
1072 setOperationAction(ISD::FP_ROUND, MVT::v2f32, Custom);
1074 setLoadExtAction(ISD::EXTLOAD, MVT::v2f32, Legal);
1076 setOperationAction(ISD::BITCAST, MVT::v2i32, Custom);
1077 setOperationAction(ISD::BITCAST, MVT::v4i16, Custom);
1078 setOperationAction(ISD::BITCAST, MVT::v8i8, Custom);
1081 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE41()) {
1082 setOperationAction(ISD::FFLOOR, MVT::f32, Legal);
1083 setOperationAction(ISD::FCEIL, MVT::f32, Legal);
1084 setOperationAction(ISD::FTRUNC, MVT::f32, Legal);
1085 setOperationAction(ISD::FRINT, MVT::f32, Legal);
1086 setOperationAction(ISD::FNEARBYINT, MVT::f32, Legal);
1087 setOperationAction(ISD::FFLOOR, MVT::f64, Legal);
1088 setOperationAction(ISD::FCEIL, MVT::f64, Legal);
1089 setOperationAction(ISD::FTRUNC, MVT::f64, Legal);
1090 setOperationAction(ISD::FRINT, MVT::f64, Legal);
1091 setOperationAction(ISD::FNEARBYINT, MVT::f64, Legal);
1093 setOperationAction(ISD::FFLOOR, MVT::v4f32, Legal);
1094 setOperationAction(ISD::FCEIL, MVT::v4f32, Legal);
1095 setOperationAction(ISD::FTRUNC, MVT::v4f32, Legal);
1096 setOperationAction(ISD::FRINT, MVT::v4f32, Legal);
1097 setOperationAction(ISD::FNEARBYINT, MVT::v4f32, Legal);
1098 setOperationAction(ISD::FFLOOR, MVT::v2f64, Legal);
1099 setOperationAction(ISD::FCEIL, MVT::v2f64, Legal);
1100 setOperationAction(ISD::FTRUNC, MVT::v2f64, Legal);
1101 setOperationAction(ISD::FRINT, MVT::v2f64, Legal);
1102 setOperationAction(ISD::FNEARBYINT, MVT::v2f64, Legal);
1104 // FIXME: Do we need to handle scalar-to-vector here?
1105 setOperationAction(ISD::MUL, MVT::v4i32, Legal);
1107 setOperationAction(ISD::VSELECT, MVT::v2f64, Custom);
1108 setOperationAction(ISD::VSELECT, MVT::v2i64, Custom);
1109 setOperationAction(ISD::VSELECT, MVT::v4i32, Custom);
1110 setOperationAction(ISD::VSELECT, MVT::v4f32, Custom);
1111 setOperationAction(ISD::VSELECT, MVT::v8i16, Custom);
1112 // There is no BLENDI for byte vectors. We don't need to custom lower
1113 // some vselects for now.
1114 setOperationAction(ISD::VSELECT, MVT::v16i8, Legal);
1116 // SSE41 brings specific instructions for doing vector sign extend even in
1117 // cases where we don't have SRA.
1118 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i8, Custom);
1119 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i16, Custom);
1120 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i32, Custom);
1122 // i8 and i16 vectors are custom because the source register and source
1123 // source memory operand types are not the same width. f32 vectors are
1124 // custom since the immediate controlling the insert encodes additional
1126 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i8, Custom);
1127 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
1128 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
1129 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
1131 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i8, Custom);
1132 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i16, Custom);
1133 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i32, Custom);
1134 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
1136 // FIXME: these should be Legal, but that's only for the case where
1137 // the index is constant. For now custom expand to deal with that.
1138 if (Subtarget->is64Bit()) {
1139 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
1140 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
1144 if (Subtarget->hasSSE2()) {
1145 setOperationAction(ISD::SRL, MVT::v8i16, Custom);
1146 setOperationAction(ISD::SRL, MVT::v16i8, Custom);
1148 setOperationAction(ISD::SHL, MVT::v8i16, Custom);
1149 setOperationAction(ISD::SHL, MVT::v16i8, Custom);
1151 setOperationAction(ISD::SRA, MVT::v8i16, Custom);
1152 setOperationAction(ISD::SRA, MVT::v16i8, Custom);
1154 // In the customized shift lowering, the legal cases in AVX2 will be
1156 setOperationAction(ISD::SRL, MVT::v2i64, Custom);
1157 setOperationAction(ISD::SRL, MVT::v4i32, Custom);
1159 setOperationAction(ISD::SHL, MVT::v2i64, Custom);
1160 setOperationAction(ISD::SHL, MVT::v4i32, Custom);
1162 setOperationAction(ISD::SRA, MVT::v4i32, Custom);
1165 if (!TM.Options.UseSoftFloat && Subtarget->hasFp256()) {
1166 addRegisterClass(MVT::v32i8, &X86::VR256RegClass);
1167 addRegisterClass(MVT::v16i16, &X86::VR256RegClass);
1168 addRegisterClass(MVT::v8i32, &X86::VR256RegClass);
1169 addRegisterClass(MVT::v8f32, &X86::VR256RegClass);
1170 addRegisterClass(MVT::v4i64, &X86::VR256RegClass);
1171 addRegisterClass(MVT::v4f64, &X86::VR256RegClass);
1173 setOperationAction(ISD::LOAD, MVT::v8f32, Legal);
1174 setOperationAction(ISD::LOAD, MVT::v4f64, Legal);
1175 setOperationAction(ISD::LOAD, MVT::v4i64, Legal);
1177 setOperationAction(ISD::FADD, MVT::v8f32, Legal);
1178 setOperationAction(ISD::FSUB, MVT::v8f32, Legal);
1179 setOperationAction(ISD::FMUL, MVT::v8f32, Legal);
1180 setOperationAction(ISD::FDIV, MVT::v8f32, Legal);
1181 setOperationAction(ISD::FSQRT, MVT::v8f32, Legal);
1182 setOperationAction(ISD::FFLOOR, MVT::v8f32, Legal);
1183 setOperationAction(ISD::FCEIL, MVT::v8f32, Legal);
1184 setOperationAction(ISD::FTRUNC, MVT::v8f32, Legal);
1185 setOperationAction(ISD::FRINT, MVT::v8f32, Legal);
1186 setOperationAction(ISD::FNEARBYINT, MVT::v8f32, Legal);
1187 setOperationAction(ISD::FNEG, MVT::v8f32, Custom);
1188 setOperationAction(ISD::FABS, MVT::v8f32, Custom);
1190 setOperationAction(ISD::FADD, MVT::v4f64, Legal);
1191 setOperationAction(ISD::FSUB, MVT::v4f64, Legal);
1192 setOperationAction(ISD::FMUL, MVT::v4f64, Legal);
1193 setOperationAction(ISD::FDIV, MVT::v4f64, Legal);
1194 setOperationAction(ISD::FSQRT, MVT::v4f64, Legal);
1195 setOperationAction(ISD::FFLOOR, MVT::v4f64, Legal);
1196 setOperationAction(ISD::FCEIL, MVT::v4f64, Legal);
1197 setOperationAction(ISD::FTRUNC, MVT::v4f64, Legal);
1198 setOperationAction(ISD::FRINT, MVT::v4f64, Legal);
1199 setOperationAction(ISD::FNEARBYINT, MVT::v4f64, Legal);
1200 setOperationAction(ISD::FNEG, MVT::v4f64, Custom);
1201 setOperationAction(ISD::FABS, MVT::v4f64, Custom);
1203 // (fp_to_int:v8i16 (v8f32 ..)) requires the result type to be promoted
1204 // even though v8i16 is a legal type.
1205 setOperationAction(ISD::FP_TO_SINT, MVT::v8i16, Promote);
1206 setOperationAction(ISD::FP_TO_UINT, MVT::v8i16, Promote);
1207 setOperationAction(ISD::FP_TO_SINT, MVT::v8i32, Legal);
1209 setOperationAction(ISD::SINT_TO_FP, MVT::v8i16, Promote);
1210 setOperationAction(ISD::SINT_TO_FP, MVT::v8i32, Legal);
1211 setOperationAction(ISD::FP_ROUND, MVT::v4f32, Legal);
1213 setOperationAction(ISD::UINT_TO_FP, MVT::v8i8, Custom);
1214 setOperationAction(ISD::UINT_TO_FP, MVT::v8i16, Custom);
1216 setLoadExtAction(ISD::EXTLOAD, MVT::v4f32, Legal);
1218 setOperationAction(ISD::SRL, MVT::v16i16, Custom);
1219 setOperationAction(ISD::SRL, MVT::v32i8, Custom);
1221 setOperationAction(ISD::SHL, MVT::v16i16, Custom);
1222 setOperationAction(ISD::SHL, MVT::v32i8, Custom);
1224 setOperationAction(ISD::SRA, MVT::v16i16, Custom);
1225 setOperationAction(ISD::SRA, MVT::v32i8, Custom);
1227 setOperationAction(ISD::SETCC, MVT::v32i8, Custom);
1228 setOperationAction(ISD::SETCC, MVT::v16i16, Custom);
1229 setOperationAction(ISD::SETCC, MVT::v8i32, Custom);
1230 setOperationAction(ISD::SETCC, MVT::v4i64, Custom);
1232 setOperationAction(ISD::SELECT, MVT::v4f64, Custom);
1233 setOperationAction(ISD::SELECT, MVT::v4i64, Custom);
1234 setOperationAction(ISD::SELECT, MVT::v8f32, Custom);
1236 setOperationAction(ISD::VSELECT, MVT::v4f64, Custom);
1237 setOperationAction(ISD::VSELECT, MVT::v4i64, Custom);
1238 setOperationAction(ISD::VSELECT, MVT::v8i32, Custom);
1239 setOperationAction(ISD::VSELECT, MVT::v8f32, Custom);
1241 setOperationAction(ISD::SIGN_EXTEND, MVT::v4i64, Custom);
1242 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i32, Custom);
1243 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i16, Custom);
1244 setOperationAction(ISD::ZERO_EXTEND, MVT::v4i64, Custom);
1245 setOperationAction(ISD::ZERO_EXTEND, MVT::v8i32, Custom);
1246 setOperationAction(ISD::ZERO_EXTEND, MVT::v16i16, Custom);
1247 setOperationAction(ISD::ANY_EXTEND, MVT::v4i64, Custom);
1248 setOperationAction(ISD::ANY_EXTEND, MVT::v8i32, Custom);
1249 setOperationAction(ISD::ANY_EXTEND, MVT::v16i16, Custom);
1250 setOperationAction(ISD::TRUNCATE, MVT::v16i8, Custom);
1251 setOperationAction(ISD::TRUNCATE, MVT::v8i16, Custom);
1252 setOperationAction(ISD::TRUNCATE, MVT::v4i32, Custom);
1254 if (Subtarget->hasFMA() || Subtarget->hasFMA4()) {
1255 setOperationAction(ISD::FMA, MVT::v8f32, Legal);
1256 setOperationAction(ISD::FMA, MVT::v4f64, Legal);
1257 setOperationAction(ISD::FMA, MVT::v4f32, Legal);
1258 setOperationAction(ISD::FMA, MVT::v2f64, Legal);
1259 setOperationAction(ISD::FMA, MVT::f32, Legal);
1260 setOperationAction(ISD::FMA, MVT::f64, Legal);
1263 if (Subtarget->hasInt256()) {
1264 setOperationAction(ISD::ADD, MVT::v4i64, Legal);
1265 setOperationAction(ISD::ADD, MVT::v8i32, Legal);
1266 setOperationAction(ISD::ADD, MVT::v16i16, Legal);
1267 setOperationAction(ISD::ADD, MVT::v32i8, Legal);
1269 setOperationAction(ISD::SUB, MVT::v4i64, Legal);
1270 setOperationAction(ISD::SUB, MVT::v8i32, Legal);
1271 setOperationAction(ISD::SUB, MVT::v16i16, Legal);
1272 setOperationAction(ISD::SUB, MVT::v32i8, Legal);
1274 setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1275 setOperationAction(ISD::MUL, MVT::v8i32, Legal);
1276 setOperationAction(ISD::MUL, MVT::v16i16, Legal);
1277 // Don't lower v32i8 because there is no 128-bit byte mul
1279 setOperationAction(ISD::UMUL_LOHI, MVT::v8i32, Custom);
1280 setOperationAction(ISD::SMUL_LOHI, MVT::v8i32, Custom);
1281 setOperationAction(ISD::MULHU, MVT::v16i16, Legal);
1282 setOperationAction(ISD::MULHS, MVT::v16i16, Legal);
1284 setOperationAction(ISD::VSELECT, MVT::v16i16, Custom);
1285 setOperationAction(ISD::VSELECT, MVT::v32i8, Legal);
1287 // The custom lowering for UINT_TO_FP for v8i32 becomes interesting
1288 // when we have a 256bit-wide blend with immediate.
1289 setOperationAction(ISD::UINT_TO_FP, MVT::v8i32, Custom);
1291 setOperationAction(ISD::ADD, MVT::v4i64, Custom);
1292 setOperationAction(ISD::ADD, MVT::v8i32, Custom);
1293 setOperationAction(ISD::ADD, MVT::v16i16, Custom);
1294 setOperationAction(ISD::ADD, MVT::v32i8, Custom);
1296 setOperationAction(ISD::SUB, MVT::v4i64, Custom);
1297 setOperationAction(ISD::SUB, MVT::v8i32, Custom);
1298 setOperationAction(ISD::SUB, MVT::v16i16, Custom);
1299 setOperationAction(ISD::SUB, MVT::v32i8, Custom);
1301 setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1302 setOperationAction(ISD::MUL, MVT::v8i32, Custom);
1303 setOperationAction(ISD::MUL, MVT::v16i16, Custom);
1304 // Don't lower v32i8 because there is no 128-bit byte mul
1307 // In the customized shift lowering, the legal cases in AVX2 will be
1309 setOperationAction(ISD::SRL, MVT::v4i64, Custom);
1310 setOperationAction(ISD::SRL, MVT::v8i32, Custom);
1312 setOperationAction(ISD::SHL, MVT::v4i64, Custom);
1313 setOperationAction(ISD::SHL, MVT::v8i32, Custom);
1315 setOperationAction(ISD::SRA, MVT::v8i32, Custom);
1317 // Custom lower several nodes for 256-bit types.
1318 for (int i = MVT::FIRST_VECTOR_VALUETYPE;
1319 i <= MVT::LAST_VECTOR_VALUETYPE; ++i) {
1320 MVT VT = (MVT::SimpleValueType)i;
1322 // Extract subvector is special because the value type
1323 // (result) is 128-bit but the source is 256-bit wide.
1324 if (VT.is128BitVector()) {
1325 if (VT.getScalarSizeInBits() >= 32) {
1326 setOperationAction(ISD::MLOAD, VT, Custom);
1327 setOperationAction(ISD::MSTORE, VT, Custom);
1329 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom);
1331 // Do not attempt to custom lower other non-256-bit vectors
1332 if (!VT.is256BitVector())
1335 if (VT.getScalarSizeInBits() >= 32) {
1336 setOperationAction(ISD::MLOAD, VT, Legal);
1337 setOperationAction(ISD::MSTORE, VT, Legal);
1339 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1340 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1341 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
1342 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1343 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom);
1344 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom);
1345 setOperationAction(ISD::CONCAT_VECTORS, VT, Custom);
1348 // Promote v32i8, v16i16, v8i32 select, and, or, xor to v4i64.
1349 for (int i = MVT::v32i8; i != MVT::v4i64; ++i) {
1350 MVT VT = (MVT::SimpleValueType)i;
1352 // Do not attempt to promote non-256-bit vectors
1353 if (!VT.is256BitVector())
1356 setOperationAction(ISD::AND, VT, Promote);
1357 AddPromotedToType (ISD::AND, VT, MVT::v4i64);
1358 setOperationAction(ISD::OR, VT, Promote);
1359 AddPromotedToType (ISD::OR, VT, MVT::v4i64);
1360 setOperationAction(ISD::XOR, VT, Promote);
1361 AddPromotedToType (ISD::XOR, VT, MVT::v4i64);
1362 setOperationAction(ISD::LOAD, VT, Promote);
1363 AddPromotedToType (ISD::LOAD, VT, MVT::v4i64);
1364 setOperationAction(ISD::SELECT, VT, Promote);
1365 AddPromotedToType (ISD::SELECT, VT, MVT::v4i64);
1369 if (!TM.Options.UseSoftFloat && Subtarget->hasAVX512()) {
1370 addRegisterClass(MVT::v16i32, &X86::VR512RegClass);
1371 addRegisterClass(MVT::v16f32, &X86::VR512RegClass);
1372 addRegisterClass(MVT::v8i64, &X86::VR512RegClass);
1373 addRegisterClass(MVT::v8f64, &X86::VR512RegClass);
1375 addRegisterClass(MVT::i1, &X86::VK1RegClass);
1376 addRegisterClass(MVT::v8i1, &X86::VK8RegClass);
1377 addRegisterClass(MVT::v16i1, &X86::VK16RegClass);
1379 setOperationAction(ISD::BR_CC, MVT::i1, Expand);
1380 setOperationAction(ISD::SETCC, MVT::i1, Custom);
1381 setOperationAction(ISD::XOR, MVT::i1, Legal);
1382 setOperationAction(ISD::OR, MVT::i1, Legal);
1383 setOperationAction(ISD::AND, MVT::i1, Legal);
1384 setLoadExtAction(ISD::EXTLOAD, MVT::v8f32, Legal);
1385 setOperationAction(ISD::LOAD, MVT::v16f32, Legal);
1386 setOperationAction(ISD::LOAD, MVT::v8f64, Legal);
1387 setOperationAction(ISD::LOAD, MVT::v8i64, Legal);
1388 setOperationAction(ISD::LOAD, MVT::v16i32, Legal);
1389 setOperationAction(ISD::LOAD, MVT::v16i1, Legal);
1391 setOperationAction(ISD::FADD, MVT::v16f32, Legal);
1392 setOperationAction(ISD::FSUB, MVT::v16f32, Legal);
1393 setOperationAction(ISD::FMUL, MVT::v16f32, Legal);
1394 setOperationAction(ISD::FDIV, MVT::v16f32, Legal);
1395 setOperationAction(ISD::FSQRT, MVT::v16f32, Legal);
1396 setOperationAction(ISD::FNEG, MVT::v16f32, Custom);
1398 setOperationAction(ISD::FADD, MVT::v8f64, Legal);
1399 setOperationAction(ISD::FSUB, MVT::v8f64, Legal);
1400 setOperationAction(ISD::FMUL, MVT::v8f64, Legal);
1401 setOperationAction(ISD::FDIV, MVT::v8f64, Legal);
1402 setOperationAction(ISD::FSQRT, MVT::v8f64, Legal);
1403 setOperationAction(ISD::FNEG, MVT::v8f64, Custom);
1404 setOperationAction(ISD::FMA, MVT::v8f64, Legal);
1405 setOperationAction(ISD::FMA, MVT::v16f32, Legal);
1407 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Legal);
1408 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Legal);
1409 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Legal);
1410 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Legal);
1411 if (Subtarget->is64Bit()) {
1412 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Legal);
1413 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Legal);
1414 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Legal);
1415 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Legal);
1417 setOperationAction(ISD::FP_TO_SINT, MVT::v16i32, Legal);
1418 setOperationAction(ISD::FP_TO_UINT, MVT::v16i32, Legal);
1419 setOperationAction(ISD::FP_TO_UINT, MVT::v8i32, Legal);
1420 setOperationAction(ISD::FP_TO_UINT, MVT::v4i32, Legal);
1421 setOperationAction(ISD::SINT_TO_FP, MVT::v16i32, Legal);
1422 setOperationAction(ISD::SINT_TO_FP, MVT::v8i1, Custom);
1423 setOperationAction(ISD::SINT_TO_FP, MVT::v16i1, Custom);
1424 setOperationAction(ISD::SINT_TO_FP, MVT::v16i8, Promote);
1425 setOperationAction(ISD::SINT_TO_FP, MVT::v16i16, Promote);
1426 setOperationAction(ISD::UINT_TO_FP, MVT::v16i32, Legal);
1427 setOperationAction(ISD::UINT_TO_FP, MVT::v8i32, Legal);
1428 setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Legal);
1429 setOperationAction(ISD::FP_ROUND, MVT::v8f32, Legal);
1430 setOperationAction(ISD::FP_EXTEND, MVT::v8f32, Legal);
1432 setOperationAction(ISD::TRUNCATE, MVT::i1, Custom);
1433 setOperationAction(ISD::TRUNCATE, MVT::v16i8, Custom);
1434 setOperationAction(ISD::TRUNCATE, MVT::v8i32, Custom);
1435 setOperationAction(ISD::TRUNCATE, MVT::v8i1, Custom);
1436 setOperationAction(ISD::TRUNCATE, MVT::v16i1, Custom);
1437 setOperationAction(ISD::TRUNCATE, MVT::v16i16, Custom);
1438 setOperationAction(ISD::ZERO_EXTEND, MVT::v16i32, Custom);
1439 setOperationAction(ISD::ZERO_EXTEND, MVT::v8i64, Custom);
1440 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i32, Custom);
1441 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i64, Custom);
1442 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i8, Custom);
1443 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i16, Custom);
1444 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i16, Custom);
1446 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8f64, Custom);
1447 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i64, Custom);
1448 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16f32, Custom);
1449 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i32, Custom);
1450 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i1, Custom);
1451 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i1, Legal);
1453 setOperationAction(ISD::SETCC, MVT::v16i1, Custom);
1454 setOperationAction(ISD::SETCC, MVT::v8i1, Custom);
1456 setOperationAction(ISD::MUL, MVT::v8i64, Custom);
1458 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i1, Custom);
1459 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i1, Custom);
1460 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i1, Custom);
1461 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i1, Custom);
1462 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i1, Custom);
1463 setOperationAction(ISD::BUILD_VECTOR, MVT::v16i1, Custom);
1464 setOperationAction(ISD::SELECT, MVT::v8f64, Custom);
1465 setOperationAction(ISD::SELECT, MVT::v8i64, Custom);
1466 setOperationAction(ISD::SELECT, MVT::v16f32, Custom);
1468 setOperationAction(ISD::ADD, MVT::v8i64, Legal);
1469 setOperationAction(ISD::ADD, MVT::v16i32, Legal);
1471 setOperationAction(ISD::SUB, MVT::v8i64, Legal);
1472 setOperationAction(ISD::SUB, MVT::v16i32, Legal);
1474 setOperationAction(ISD::MUL, MVT::v16i32, Legal);
1476 setOperationAction(ISD::SRL, MVT::v8i64, Custom);
1477 setOperationAction(ISD::SRL, MVT::v16i32, Custom);
1479 setOperationAction(ISD::SHL, MVT::v8i64, Custom);
1480 setOperationAction(ISD::SHL, MVT::v16i32, Custom);
1482 setOperationAction(ISD::SRA, MVT::v8i64, Custom);
1483 setOperationAction(ISD::SRA, MVT::v16i32, Custom);
1485 setOperationAction(ISD::AND, MVT::v8i64, Legal);
1486 setOperationAction(ISD::OR, MVT::v8i64, Legal);
1487 setOperationAction(ISD::XOR, MVT::v8i64, Legal);
1488 setOperationAction(ISD::AND, MVT::v16i32, Legal);
1489 setOperationAction(ISD::OR, MVT::v16i32, Legal);
1490 setOperationAction(ISD::XOR, MVT::v16i32, Legal);
1492 if (Subtarget->hasCDI()) {
1493 setOperationAction(ISD::CTLZ, MVT::v8i64, Legal);
1494 setOperationAction(ISD::CTLZ, MVT::v16i32, Legal);
1497 // Custom lower several nodes.
1498 for (int i = MVT::FIRST_VECTOR_VALUETYPE;
1499 i <= MVT::LAST_VECTOR_VALUETYPE; ++i) {
1500 MVT VT = (MVT::SimpleValueType)i;
1502 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
1503 // Extract subvector is special because the value type
1504 // (result) is 256/128-bit but the source is 512-bit wide.
1505 if (VT.is128BitVector() || VT.is256BitVector()) {
1506 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom);
1507 if ( EltSize >= 32) {
1508 setOperationAction(ISD::MLOAD, VT, Legal);
1509 setOperationAction(ISD::MSTORE, VT, Legal);
1512 if (VT.getVectorElementType() == MVT::i1)
1513 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Legal);
1515 // Do not attempt to custom lower other non-512-bit vectors
1516 if (!VT.is512BitVector())
1519 if ( EltSize >= 32) {
1520 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1521 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
1522 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1523 setOperationAction(ISD::VSELECT, VT, Legal);
1524 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1525 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom);
1526 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom);
1527 setOperationAction(ISD::MLOAD, VT, Legal);
1528 setOperationAction(ISD::MSTORE, VT, Legal);
1531 for (int i = MVT::v32i8; i != MVT::v8i64; ++i) {
1532 MVT VT = (MVT::SimpleValueType)i;
1534 // Do not attempt to promote non-256-bit vectors
1535 if (!VT.is512BitVector())
1538 setOperationAction(ISD::SELECT, VT, Promote);
1539 AddPromotedToType (ISD::SELECT, VT, MVT::v8i64);
1543 if (!TM.Options.UseSoftFloat && Subtarget->hasBWI()) {
1544 addRegisterClass(MVT::v32i16, &X86::VR512RegClass);
1545 addRegisterClass(MVT::v64i8, &X86::VR512RegClass);
1547 addRegisterClass(MVT::v32i1, &X86::VK32RegClass);
1548 addRegisterClass(MVT::v64i1, &X86::VK64RegClass);
1550 setOperationAction(ISD::LOAD, MVT::v32i16, Legal);
1551 setOperationAction(ISD::LOAD, MVT::v64i8, Legal);
1552 setOperationAction(ISD::SETCC, MVT::v32i1, Custom);
1553 setOperationAction(ISD::SETCC, MVT::v64i1, Custom);
1555 for (int i = MVT::v32i8; i != MVT::v8i64; ++i) {
1556 const MVT VT = (MVT::SimpleValueType)i;
1558 const unsigned EltSize = VT.getVectorElementType().getSizeInBits();
1560 // Do not attempt to promote non-256-bit vectors
1561 if (!VT.is512BitVector())
1564 if ( EltSize < 32) {
1565 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1566 setOperationAction(ISD::VSELECT, VT, Legal);
1571 if (!TM.Options.UseSoftFloat && Subtarget->hasVLX()) {
1572 addRegisterClass(MVT::v4i1, &X86::VK4RegClass);
1573 addRegisterClass(MVT::v2i1, &X86::VK2RegClass);
1575 setOperationAction(ISD::SETCC, MVT::v4i1, Custom);
1576 setOperationAction(ISD::SETCC, MVT::v2i1, Custom);
1577 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v8i1, Legal);
1580 // SIGN_EXTEND_INREGs are evaluated by the extend type. Handle the expansion
1581 // of this type with custom code.
1582 for (int VT = MVT::FIRST_VECTOR_VALUETYPE;
1583 VT != MVT::LAST_VECTOR_VALUETYPE; VT++) {
1584 setOperationAction(ISD::SIGN_EXTEND_INREG, (MVT::SimpleValueType)VT,
1588 // We want to custom lower some of our intrinsics.
1589 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
1590 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::Other, Custom);
1591 setOperationAction(ISD::INTRINSIC_VOID, MVT::Other, Custom);
1592 if (!Subtarget->is64Bit())
1593 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::i64, Custom);
1595 // Only custom-lower 64-bit SADDO and friends on 64-bit because we don't
1596 // handle type legalization for these operations here.
1598 // FIXME: We really should do custom legalization for addition and
1599 // subtraction on x86-32 once PR3203 is fixed. We really can't do much better
1600 // than generic legalization for 64-bit multiplication-with-overflow, though.
1601 for (unsigned i = 0, e = 3+Subtarget->is64Bit(); i != e; ++i) {
1602 // Add/Sub/Mul with overflow operations are custom lowered.
1604 setOperationAction(ISD::SADDO, VT, Custom);
1605 setOperationAction(ISD::UADDO, VT, Custom);
1606 setOperationAction(ISD::SSUBO, VT, Custom);
1607 setOperationAction(ISD::USUBO, VT, Custom);
1608 setOperationAction(ISD::SMULO, VT, Custom);
1609 setOperationAction(ISD::UMULO, VT, Custom);
1613 if (!Subtarget->is64Bit()) {
1614 // These libcalls are not available in 32-bit.
1615 setLibcallName(RTLIB::SHL_I128, nullptr);
1616 setLibcallName(RTLIB::SRL_I128, nullptr);
1617 setLibcallName(RTLIB::SRA_I128, nullptr);
1620 // Combine sin / cos into one node or libcall if possible.
1621 if (Subtarget->hasSinCos()) {
1622 setLibcallName(RTLIB::SINCOS_F32, "sincosf");
1623 setLibcallName(RTLIB::SINCOS_F64, "sincos");
1624 if (Subtarget->isTargetDarwin()) {
1625 // For MacOSX, we don't want to the normal expansion of a libcall to
1626 // sincos. We want to issue a libcall to __sincos_stret to avoid memory
1628 setOperationAction(ISD::FSINCOS, MVT::f64, Custom);
1629 setOperationAction(ISD::FSINCOS, MVT::f32, Custom);
1633 if (Subtarget->isTargetWin64()) {
1634 setOperationAction(ISD::SDIV, MVT::i128, Custom);
1635 setOperationAction(ISD::UDIV, MVT::i128, Custom);
1636 setOperationAction(ISD::SREM, MVT::i128, Custom);
1637 setOperationAction(ISD::UREM, MVT::i128, Custom);
1638 setOperationAction(ISD::SDIVREM, MVT::i128, Custom);
1639 setOperationAction(ISD::UDIVREM, MVT::i128, Custom);
1642 // We have target-specific dag combine patterns for the following nodes:
1643 setTargetDAGCombine(ISD::VECTOR_SHUFFLE);
1644 setTargetDAGCombine(ISD::EXTRACT_VECTOR_ELT);
1645 setTargetDAGCombine(ISD::VSELECT);
1646 setTargetDAGCombine(ISD::SELECT);
1647 setTargetDAGCombine(ISD::SHL);
1648 setTargetDAGCombine(ISD::SRA);
1649 setTargetDAGCombine(ISD::SRL);
1650 setTargetDAGCombine(ISD::OR);
1651 setTargetDAGCombine(ISD::AND);
1652 setTargetDAGCombine(ISD::ADD);
1653 setTargetDAGCombine(ISD::FADD);
1654 setTargetDAGCombine(ISD::FSUB);
1655 setTargetDAGCombine(ISD::FMA);
1656 setTargetDAGCombine(ISD::SUB);
1657 setTargetDAGCombine(ISD::LOAD);
1658 setTargetDAGCombine(ISD::STORE);
1659 setTargetDAGCombine(ISD::ZERO_EXTEND);
1660 setTargetDAGCombine(ISD::ANY_EXTEND);
1661 setTargetDAGCombine(ISD::SIGN_EXTEND);
1662 setTargetDAGCombine(ISD::SIGN_EXTEND_INREG);
1663 setTargetDAGCombine(ISD::TRUNCATE);
1664 setTargetDAGCombine(ISD::SINT_TO_FP);
1665 setTargetDAGCombine(ISD::SETCC);
1666 setTargetDAGCombine(ISD::INTRINSIC_WO_CHAIN);
1667 setTargetDAGCombine(ISD::BUILD_VECTOR);
1668 if (Subtarget->is64Bit())
1669 setTargetDAGCombine(ISD::MUL);
1670 setTargetDAGCombine(ISD::XOR);
1672 computeRegisterProperties();
1674 // On Darwin, -Os means optimize for size without hurting performance,
1675 // do not reduce the limit.
1676 MaxStoresPerMemset = 16; // For @llvm.memset -> sequence of stores
1677 MaxStoresPerMemsetOptSize = Subtarget->isTargetDarwin() ? 16 : 8;
1678 MaxStoresPerMemcpy = 8; // For @llvm.memcpy -> sequence of stores
1679 MaxStoresPerMemcpyOptSize = Subtarget->isTargetDarwin() ? 8 : 4;
1680 MaxStoresPerMemmove = 8; // For @llvm.memmove -> sequence of stores
1681 MaxStoresPerMemmoveOptSize = Subtarget->isTargetDarwin() ? 8 : 4;
1682 setPrefLoopAlignment(4); // 2^4 bytes.
1684 // Predictable cmov don't hurt on atom because it's in-order.
1685 PredictableSelectIsExpensive = !Subtarget->isAtom();
1687 setPrefFunctionAlignment(4); // 2^4 bytes.
1689 verifyIntrinsicTables();
1692 // This has so far only been implemented for 64-bit MachO.
1693 bool X86TargetLowering::useLoadStackGuardNode() const {
1694 return Subtarget->getTargetTriple().getObjectFormat() == Triple::MachO &&
1695 Subtarget->is64Bit();
1698 TargetLoweringBase::LegalizeTypeAction
1699 X86TargetLowering::getPreferredVectorAction(EVT VT) const {
1700 if (ExperimentalVectorWideningLegalization &&
1701 VT.getVectorNumElements() != 1 &&
1702 VT.getVectorElementType().getSimpleVT() != MVT::i1)
1703 return TypeWidenVector;
1705 return TargetLoweringBase::getPreferredVectorAction(VT);
1708 EVT X86TargetLowering::getSetCCResultType(LLVMContext &, EVT VT) const {
1710 return Subtarget->hasAVX512() ? MVT::i1: MVT::i8;
1712 const unsigned NumElts = VT.getVectorNumElements();
1713 const EVT EltVT = VT.getVectorElementType();
1714 if (VT.is512BitVector()) {
1715 if (Subtarget->hasAVX512())
1716 if (EltVT == MVT::i32 || EltVT == MVT::i64 ||
1717 EltVT == MVT::f32 || EltVT == MVT::f64)
1719 case 8: return MVT::v8i1;
1720 case 16: return MVT::v16i1;
1722 if (Subtarget->hasBWI())
1723 if (EltVT == MVT::i8 || EltVT == MVT::i16)
1725 case 32: return MVT::v32i1;
1726 case 64: return MVT::v64i1;
1730 if (VT.is256BitVector() || VT.is128BitVector()) {
1731 if (Subtarget->hasVLX())
1732 if (EltVT == MVT::i32 || EltVT == MVT::i64 ||
1733 EltVT == MVT::f32 || EltVT == MVT::f64)
1735 case 2: return MVT::v2i1;
1736 case 4: return MVT::v4i1;
1737 case 8: return MVT::v8i1;
1739 if (Subtarget->hasBWI() && Subtarget->hasVLX())
1740 if (EltVT == MVT::i8 || EltVT == MVT::i16)
1742 case 8: return MVT::v8i1;
1743 case 16: return MVT::v16i1;
1744 case 32: return MVT::v32i1;
1748 return VT.changeVectorElementTypeToInteger();
1751 /// getMaxByValAlign - Helper for getByValTypeAlignment to determine
1752 /// the desired ByVal argument alignment.
1753 static void getMaxByValAlign(Type *Ty, unsigned &MaxAlign) {
1756 if (VectorType *VTy = dyn_cast<VectorType>(Ty)) {
1757 if (VTy->getBitWidth() == 128)
1759 } else if (ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
1760 unsigned EltAlign = 0;
1761 getMaxByValAlign(ATy->getElementType(), EltAlign);
1762 if (EltAlign > MaxAlign)
1763 MaxAlign = EltAlign;
1764 } else if (StructType *STy = dyn_cast<StructType>(Ty)) {
1765 for (unsigned i = 0, e = STy->getNumElements(); i != e; ++i) {
1766 unsigned EltAlign = 0;
1767 getMaxByValAlign(STy->getElementType(i), EltAlign);
1768 if (EltAlign > MaxAlign)
1769 MaxAlign = EltAlign;
1776 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
1777 /// function arguments in the caller parameter area. For X86, aggregates
1778 /// that contain SSE vectors are placed at 16-byte boundaries while the rest
1779 /// are at 4-byte boundaries.
1780 unsigned X86TargetLowering::getByValTypeAlignment(Type *Ty) const {
1781 if (Subtarget->is64Bit()) {
1782 // Max of 8 and alignment of type.
1783 unsigned TyAlign = TD->getABITypeAlignment(Ty);
1790 if (Subtarget->hasSSE1())
1791 getMaxByValAlign(Ty, Align);
1795 /// getOptimalMemOpType - Returns the target specific optimal type for load
1796 /// and store operations as a result of memset, memcpy, and memmove
1797 /// lowering. If DstAlign is zero that means it's safe to destination
1798 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
1799 /// means there isn't a need to check it against alignment requirement,
1800 /// probably because the source does not need to be loaded. If 'IsMemset' is
1801 /// true, that means it's expanding a memset. If 'ZeroMemset' is true, that
1802 /// means it's a memset of zero. 'MemcpyStrSrc' indicates whether the memcpy
1803 /// source is constant so it does not need to be loaded.
1804 /// It returns EVT::Other if the type should be determined using generic
1805 /// target-independent logic.
1807 X86TargetLowering::getOptimalMemOpType(uint64_t Size,
1808 unsigned DstAlign, unsigned SrcAlign,
1809 bool IsMemset, bool ZeroMemset,
1811 MachineFunction &MF) const {
1812 const Function *F = MF.getFunction();
1813 if ((!IsMemset || ZeroMemset) &&
1814 !F->getAttributes().hasAttribute(AttributeSet::FunctionIndex,
1815 Attribute::NoImplicitFloat)) {
1817 (Subtarget->isUnalignedMemAccessFast() ||
1818 ((DstAlign == 0 || DstAlign >= 16) &&
1819 (SrcAlign == 0 || SrcAlign >= 16)))) {
1821 if (Subtarget->hasInt256())
1823 if (Subtarget->hasFp256())
1826 if (Subtarget->hasSSE2())
1828 if (Subtarget->hasSSE1())
1830 } else if (!MemcpyStrSrc && Size >= 8 &&
1831 !Subtarget->is64Bit() &&
1832 Subtarget->hasSSE2()) {
1833 // Do not use f64 to lower memcpy if source is string constant. It's
1834 // better to use i32 to avoid the loads.
1838 if (Subtarget->is64Bit() && Size >= 8)
1843 bool X86TargetLowering::isSafeMemOpType(MVT VT) const {
1845 return X86ScalarSSEf32;
1846 else if (VT == MVT::f64)
1847 return X86ScalarSSEf64;
1852 X86TargetLowering::allowsMisalignedMemoryAccesses(EVT VT,
1857 *Fast = Subtarget->isUnalignedMemAccessFast();
1861 /// getJumpTableEncoding - Return the entry encoding for a jump table in the
1862 /// current function. The returned value is a member of the
1863 /// MachineJumpTableInfo::JTEntryKind enum.
1864 unsigned X86TargetLowering::getJumpTableEncoding() const {
1865 // In GOT pic mode, each entry in the jump table is emitted as a @GOTOFF
1867 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1868 Subtarget->isPICStyleGOT())
1869 return MachineJumpTableInfo::EK_Custom32;
1871 // Otherwise, use the normal jump table encoding heuristics.
1872 return TargetLowering::getJumpTableEncoding();
1876 X86TargetLowering::LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI,
1877 const MachineBasicBlock *MBB,
1878 unsigned uid,MCContext &Ctx) const{
1879 assert(MBB->getParent()->getTarget().getRelocationModel() == Reloc::PIC_ &&
1880 Subtarget->isPICStyleGOT());
1881 // In 32-bit ELF systems, our jump table entries are formed with @GOTOFF
1883 return MCSymbolRefExpr::Create(MBB->getSymbol(),
1884 MCSymbolRefExpr::VK_GOTOFF, Ctx);
1887 /// getPICJumpTableRelocaBase - Returns relocation base for the given PIC
1889 SDValue X86TargetLowering::getPICJumpTableRelocBase(SDValue Table,
1890 SelectionDAG &DAG) const {
1891 if (!Subtarget->is64Bit())
1892 // This doesn't have SDLoc associated with it, but is not really the
1893 // same as a Register.
1894 return DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), getPointerTy());
1898 /// getPICJumpTableRelocBaseExpr - This returns the relocation base for the
1899 /// given PIC jumptable, the same as getPICJumpTableRelocBase, but as an
1901 const MCExpr *X86TargetLowering::
1902 getPICJumpTableRelocBaseExpr(const MachineFunction *MF, unsigned JTI,
1903 MCContext &Ctx) const {
1904 // X86-64 uses RIP relative addressing based on the jump table label.
1905 if (Subtarget->isPICStyleRIPRel())
1906 return TargetLowering::getPICJumpTableRelocBaseExpr(MF, JTI, Ctx);
1908 // Otherwise, the reference is relative to the PIC base.
1909 return MCSymbolRefExpr::Create(MF->getPICBaseSymbol(), Ctx);
1912 // FIXME: Why this routine is here? Move to RegInfo!
1913 std::pair<const TargetRegisterClass*, uint8_t>
1914 X86TargetLowering::findRepresentativeClass(MVT VT) const{
1915 const TargetRegisterClass *RRC = nullptr;
1917 switch (VT.SimpleTy) {
1919 return TargetLowering::findRepresentativeClass(VT);
1920 case MVT::i8: case MVT::i16: case MVT::i32: case MVT::i64:
1921 RRC = Subtarget->is64Bit() ? &X86::GR64RegClass : &X86::GR32RegClass;
1924 RRC = &X86::VR64RegClass;
1926 case MVT::f32: case MVT::f64:
1927 case MVT::v16i8: case MVT::v8i16: case MVT::v4i32: case MVT::v2i64:
1928 case MVT::v4f32: case MVT::v2f64:
1929 case MVT::v32i8: case MVT::v8i32: case MVT::v4i64: case MVT::v8f32:
1931 RRC = &X86::VR128RegClass;
1934 return std::make_pair(RRC, Cost);
1937 bool X86TargetLowering::getStackCookieLocation(unsigned &AddressSpace,
1938 unsigned &Offset) const {
1939 if (!Subtarget->isTargetLinux())
1942 if (Subtarget->is64Bit()) {
1943 // %fs:0x28, unless we're using a Kernel code model, in which case it's %gs:
1945 if (getTargetMachine().getCodeModel() == CodeModel::Kernel)
1957 bool X86TargetLowering::isNoopAddrSpaceCast(unsigned SrcAS,
1958 unsigned DestAS) const {
1959 assert(SrcAS != DestAS && "Expected different address spaces!");
1961 return SrcAS < 256 && DestAS < 256;
1964 //===----------------------------------------------------------------------===//
1965 // Return Value Calling Convention Implementation
1966 //===----------------------------------------------------------------------===//
1968 #include "X86GenCallingConv.inc"
1971 X86TargetLowering::CanLowerReturn(CallingConv::ID CallConv,
1972 MachineFunction &MF, bool isVarArg,
1973 const SmallVectorImpl<ISD::OutputArg> &Outs,
1974 LLVMContext &Context) const {
1975 SmallVector<CCValAssign, 16> RVLocs;
1976 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, Context);
1977 return CCInfo.CheckReturn(Outs, RetCC_X86);
1980 const MCPhysReg *X86TargetLowering::getScratchRegisters(CallingConv::ID) const {
1981 static const MCPhysReg ScratchRegs[] = { X86::R11, 0 };
1986 X86TargetLowering::LowerReturn(SDValue Chain,
1987 CallingConv::ID CallConv, bool isVarArg,
1988 const SmallVectorImpl<ISD::OutputArg> &Outs,
1989 const SmallVectorImpl<SDValue> &OutVals,
1990 SDLoc dl, SelectionDAG &DAG) const {
1991 MachineFunction &MF = DAG.getMachineFunction();
1992 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1994 SmallVector<CCValAssign, 16> RVLocs;
1995 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, *DAG.getContext());
1996 CCInfo.AnalyzeReturn(Outs, RetCC_X86);
1999 SmallVector<SDValue, 6> RetOps;
2000 RetOps.push_back(Chain); // Operand #0 = Chain (updated below)
2001 // Operand #1 = Bytes To Pop
2002 RetOps.push_back(DAG.getTargetConstant(FuncInfo->getBytesToPopOnReturn(),
2005 // Copy the result values into the output registers.
2006 for (unsigned i = 0; i != RVLocs.size(); ++i) {
2007 CCValAssign &VA = RVLocs[i];
2008 assert(VA.isRegLoc() && "Can only return in registers!");
2009 SDValue ValToCopy = OutVals[i];
2010 EVT ValVT = ValToCopy.getValueType();
2012 // Promote values to the appropriate types
2013 if (VA.getLocInfo() == CCValAssign::SExt)
2014 ValToCopy = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), ValToCopy);
2015 else if (VA.getLocInfo() == CCValAssign::ZExt)
2016 ValToCopy = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), ValToCopy);
2017 else if (VA.getLocInfo() == CCValAssign::AExt)
2018 ValToCopy = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), ValToCopy);
2019 else if (VA.getLocInfo() == CCValAssign::BCvt)
2020 ValToCopy = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), ValToCopy);
2022 assert(VA.getLocInfo() != CCValAssign::FPExt &&
2023 "Unexpected FP-extend for return value.");
2025 // If this is x86-64, and we disabled SSE, we can't return FP values,
2026 // or SSE or MMX vectors.
2027 if ((ValVT == MVT::f32 || ValVT == MVT::f64 ||
2028 VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) &&
2029 (Subtarget->is64Bit() && !Subtarget->hasSSE1())) {
2030 report_fatal_error("SSE register return with SSE disabled");
2032 // Likewise we can't return F64 values with SSE1 only. gcc does so, but
2033 // llvm-gcc has never done it right and no one has noticed, so this
2034 // should be OK for now.
2035 if (ValVT == MVT::f64 &&
2036 (Subtarget->is64Bit() && !Subtarget->hasSSE2()))
2037 report_fatal_error("SSE2 register return with SSE2 disabled");
2039 // Returns in ST0/ST1 are handled specially: these are pushed as operands to
2040 // the RET instruction and handled by the FP Stackifier.
2041 if (VA.getLocReg() == X86::FP0 ||
2042 VA.getLocReg() == X86::FP1) {
2043 // If this is a copy from an xmm register to ST(0), use an FPExtend to
2044 // change the value to the FP stack register class.
2045 if (isScalarFPTypeInSSEReg(VA.getValVT()))
2046 ValToCopy = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f80, ValToCopy);
2047 RetOps.push_back(ValToCopy);
2048 // Don't emit a copytoreg.
2052 // 64-bit vector (MMX) values are returned in XMM0 / XMM1 except for v1i64
2053 // which is returned in RAX / RDX.
2054 if (Subtarget->is64Bit()) {
2055 if (ValVT == MVT::x86mmx) {
2056 if (VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) {
2057 ValToCopy = DAG.getNode(ISD::BITCAST, dl, MVT::i64, ValToCopy);
2058 ValToCopy = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
2060 // If we don't have SSE2 available, convert to v4f32 so the generated
2061 // register is legal.
2062 if (!Subtarget->hasSSE2())
2063 ValToCopy = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32,ValToCopy);
2068 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), ValToCopy, Flag);
2069 Flag = Chain.getValue(1);
2070 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
2073 // The x86-64 ABIs require that for returning structs by value we copy
2074 // the sret argument into %rax/%eax (depending on ABI) for the return.
2075 // Win32 requires us to put the sret argument to %eax as well.
2076 // We saved the argument into a virtual register in the entry block,
2077 // so now we copy the value out and into %rax/%eax.
2078 if (DAG.getMachineFunction().getFunction()->hasStructRetAttr() &&
2079 (Subtarget->is64Bit() || Subtarget->isTargetKnownWindowsMSVC())) {
2080 MachineFunction &MF = DAG.getMachineFunction();
2081 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
2082 unsigned Reg = FuncInfo->getSRetReturnReg();
2084 "SRetReturnReg should have been set in LowerFormalArguments().");
2085 SDValue Val = DAG.getCopyFromReg(Chain, dl, Reg, getPointerTy());
2088 = (Subtarget->is64Bit() && !Subtarget->isTarget64BitILP32()) ?
2089 X86::RAX : X86::EAX;
2090 Chain = DAG.getCopyToReg(Chain, dl, RetValReg, Val, Flag);
2091 Flag = Chain.getValue(1);
2093 // RAX/EAX now acts like a return value.
2094 RetOps.push_back(DAG.getRegister(RetValReg, getPointerTy()));
2097 RetOps[0] = Chain; // Update chain.
2099 // Add the flag if we have it.
2101 RetOps.push_back(Flag);
2103 return DAG.getNode(X86ISD::RET_FLAG, dl, MVT::Other, RetOps);
2106 bool X86TargetLowering::isUsedByReturnOnly(SDNode *N, SDValue &Chain) const {
2107 if (N->getNumValues() != 1)
2109 if (!N->hasNUsesOfValue(1, 0))
2112 SDValue TCChain = Chain;
2113 SDNode *Copy = *N->use_begin();
2114 if (Copy->getOpcode() == ISD::CopyToReg) {
2115 // If the copy has a glue operand, we conservatively assume it isn't safe to
2116 // perform a tail call.
2117 if (Copy->getOperand(Copy->getNumOperands()-1).getValueType() == MVT::Glue)
2119 TCChain = Copy->getOperand(0);
2120 } else if (Copy->getOpcode() != ISD::FP_EXTEND)
2123 bool HasRet = false;
2124 for (SDNode::use_iterator UI = Copy->use_begin(), UE = Copy->use_end();
2126 if (UI->getOpcode() != X86ISD::RET_FLAG)
2128 // If we are returning more than one value, we can definitely
2129 // not make a tail call see PR19530
2130 if (UI->getNumOperands() > 4)
2132 if (UI->getNumOperands() == 4 &&
2133 UI->getOperand(UI->getNumOperands()-1).getValueType() != MVT::Glue)
2146 X86TargetLowering::getTypeForExtArgOrReturn(LLVMContext &Context, EVT VT,
2147 ISD::NodeType ExtendKind) const {
2149 // TODO: Is this also valid on 32-bit?
2150 if (Subtarget->is64Bit() && VT == MVT::i1 && ExtendKind == ISD::ZERO_EXTEND)
2151 ReturnMVT = MVT::i8;
2153 ReturnMVT = MVT::i32;
2155 EVT MinVT = getRegisterType(Context, ReturnMVT);
2156 return VT.bitsLT(MinVT) ? MinVT : VT;
2159 /// LowerCallResult - Lower the result values of a call into the
2160 /// appropriate copies out of appropriate physical registers.
2163 X86TargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
2164 CallingConv::ID CallConv, bool isVarArg,
2165 const SmallVectorImpl<ISD::InputArg> &Ins,
2166 SDLoc dl, SelectionDAG &DAG,
2167 SmallVectorImpl<SDValue> &InVals) const {
2169 // Assign locations to each value returned by this call.
2170 SmallVector<CCValAssign, 16> RVLocs;
2171 bool Is64Bit = Subtarget->is64Bit();
2172 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
2174 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
2176 // Copy all of the result registers out of their specified physreg.
2177 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
2178 CCValAssign &VA = RVLocs[i];
2179 EVT CopyVT = VA.getValVT();
2181 // If this is x86-64, and we disabled SSE, we can't return FP values
2182 if ((CopyVT == MVT::f32 || CopyVT == MVT::f64) &&
2183 ((Is64Bit || Ins[i].Flags.isInReg()) && !Subtarget->hasSSE1())) {
2184 report_fatal_error("SSE register return with SSE disabled");
2187 // If we prefer to use the value in xmm registers, copy it out as f80 and
2188 // use a truncate to move it from fp stack reg to xmm reg.
2189 if ((VA.getLocReg() == X86::FP0 || VA.getLocReg() == X86::FP1) &&
2190 isScalarFPTypeInSSEReg(VA.getValVT()))
2193 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(),
2194 CopyVT, InFlag).getValue(1);
2195 SDValue Val = Chain.getValue(0);
2197 if (CopyVT != VA.getValVT())
2198 Val = DAG.getNode(ISD::FP_ROUND, dl, VA.getValVT(), Val,
2199 // This truncation won't change the value.
2200 DAG.getIntPtrConstant(1));
2202 InFlag = Chain.getValue(2);
2203 InVals.push_back(Val);
2209 //===----------------------------------------------------------------------===//
2210 // C & StdCall & Fast Calling Convention implementation
2211 //===----------------------------------------------------------------------===//
2212 // StdCall calling convention seems to be standard for many Windows' API
2213 // routines and around. It differs from C calling convention just a little:
2214 // callee should clean up the stack, not caller. Symbols should be also
2215 // decorated in some fancy way :) It doesn't support any vector arguments.
2216 // For info on fast calling convention see Fast Calling Convention (tail call)
2217 // implementation LowerX86_32FastCCCallTo.
2219 /// CallIsStructReturn - Determines whether a call uses struct return
2221 enum StructReturnType {
2226 static StructReturnType
2227 callIsStructReturn(const SmallVectorImpl<ISD::OutputArg> &Outs) {
2229 return NotStructReturn;
2231 const ISD::ArgFlagsTy &Flags = Outs[0].Flags;
2232 if (!Flags.isSRet())
2233 return NotStructReturn;
2234 if (Flags.isInReg())
2235 return RegStructReturn;
2236 return StackStructReturn;
2239 /// ArgsAreStructReturn - Determines whether a function uses struct
2240 /// return semantics.
2241 static StructReturnType
2242 argsAreStructReturn(const SmallVectorImpl<ISD::InputArg> &Ins) {
2244 return NotStructReturn;
2246 const ISD::ArgFlagsTy &Flags = Ins[0].Flags;
2247 if (!Flags.isSRet())
2248 return NotStructReturn;
2249 if (Flags.isInReg())
2250 return RegStructReturn;
2251 return StackStructReturn;
2254 /// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified
2255 /// by "Src" to address "Dst" with size and alignment information specified by
2256 /// the specific parameter attribute. The copy will be passed as a byval
2257 /// function parameter.
2259 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
2260 ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
2262 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32);
2264 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
2265 /*isVolatile*/false, /*AlwaysInline=*/true,
2266 MachinePointerInfo(), MachinePointerInfo());
2269 /// IsTailCallConvention - Return true if the calling convention is one that
2270 /// supports tail call optimization.
2271 static bool IsTailCallConvention(CallingConv::ID CC) {
2272 return (CC == CallingConv::Fast || CC == CallingConv::GHC ||
2273 CC == CallingConv::HiPE);
2276 /// \brief Return true if the calling convention is a C calling convention.
2277 static bool IsCCallConvention(CallingConv::ID CC) {
2278 return (CC == CallingConv::C || CC == CallingConv::X86_64_Win64 ||
2279 CC == CallingConv::X86_64_SysV);
2282 bool X86TargetLowering::mayBeEmittedAsTailCall(CallInst *CI) const {
2283 if (!CI->isTailCall() || getTargetMachine().Options.DisableTailCalls)
2287 CallingConv::ID CalleeCC = CS.getCallingConv();
2288 if (!IsTailCallConvention(CalleeCC) && !IsCCallConvention(CalleeCC))
2294 /// FuncIsMadeTailCallSafe - Return true if the function is being made into
2295 /// a tailcall target by changing its ABI.
2296 static bool FuncIsMadeTailCallSafe(CallingConv::ID CC,
2297 bool GuaranteedTailCallOpt) {
2298 return GuaranteedTailCallOpt && IsTailCallConvention(CC);
2302 X86TargetLowering::LowerMemArgument(SDValue Chain,
2303 CallingConv::ID CallConv,
2304 const SmallVectorImpl<ISD::InputArg> &Ins,
2305 SDLoc dl, SelectionDAG &DAG,
2306 const CCValAssign &VA,
2307 MachineFrameInfo *MFI,
2309 // Create the nodes corresponding to a load from this parameter slot.
2310 ISD::ArgFlagsTy Flags = Ins[i].Flags;
2311 bool AlwaysUseMutable = FuncIsMadeTailCallSafe(
2312 CallConv, DAG.getTarget().Options.GuaranteedTailCallOpt);
2313 bool isImmutable = !AlwaysUseMutable && !Flags.isByVal();
2316 // If value is passed by pointer we have address passed instead of the value
2318 if (VA.getLocInfo() == CCValAssign::Indirect)
2319 ValVT = VA.getLocVT();
2321 ValVT = VA.getValVT();
2323 // FIXME: For now, all byval parameter objects are marked mutable. This can be
2324 // changed with more analysis.
2325 // In case of tail call optimization mark all arguments mutable. Since they
2326 // could be overwritten by lowering of arguments in case of a tail call.
2327 if (Flags.isByVal()) {
2328 unsigned Bytes = Flags.getByValSize();
2329 if (Bytes == 0) Bytes = 1; // Don't create zero-sized stack objects.
2330 int FI = MFI->CreateFixedObject(Bytes, VA.getLocMemOffset(), isImmutable);
2331 return DAG.getFrameIndex(FI, getPointerTy());
2333 int FI = MFI->CreateFixedObject(ValVT.getSizeInBits()/8,
2334 VA.getLocMemOffset(), isImmutable);
2335 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
2336 return DAG.getLoad(ValVT, dl, Chain, FIN,
2337 MachinePointerInfo::getFixedStack(FI),
2338 false, false, false, 0);
2342 // FIXME: Get this from tablegen.
2343 static ArrayRef<MCPhysReg> get64BitArgumentGPRs(CallingConv::ID CallConv,
2344 const X86Subtarget *Subtarget) {
2345 assert(Subtarget->is64Bit());
2347 if (Subtarget->isCallingConvWin64(CallConv)) {
2348 static const MCPhysReg GPR64ArgRegsWin64[] = {
2349 X86::RCX, X86::RDX, X86::R8, X86::R9
2351 return makeArrayRef(std::begin(GPR64ArgRegsWin64), std::end(GPR64ArgRegsWin64));
2354 static const MCPhysReg GPR64ArgRegs64Bit[] = {
2355 X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9
2357 return makeArrayRef(std::begin(GPR64ArgRegs64Bit), std::end(GPR64ArgRegs64Bit));
2360 // FIXME: Get this from tablegen.
2361 static ArrayRef<MCPhysReg> get64BitArgumentXMMs(MachineFunction &MF,
2362 CallingConv::ID CallConv,
2363 const X86Subtarget *Subtarget) {
2364 assert(Subtarget->is64Bit());
2365 if (Subtarget->isCallingConvWin64(CallConv)) {
2366 // The XMM registers which might contain var arg parameters are shadowed
2367 // in their paired GPR. So we only need to save the GPR to their home
2369 // TODO: __vectorcall will change this.
2373 const Function *Fn = MF.getFunction();
2374 bool NoImplicitFloatOps = Fn->getAttributes().
2375 hasAttribute(AttributeSet::FunctionIndex, Attribute::NoImplicitFloat);
2376 assert(!(MF.getTarget().Options.UseSoftFloat && NoImplicitFloatOps) &&
2377 "SSE register cannot be used when SSE is disabled!");
2378 if (MF.getTarget().Options.UseSoftFloat || NoImplicitFloatOps ||
2379 !Subtarget->hasSSE1())
2380 // Kernel mode asks for SSE to be disabled, so there are no XMM argument
2384 static const MCPhysReg XMMArgRegs64Bit[] = {
2385 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
2386 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
2388 return makeArrayRef(std::begin(XMMArgRegs64Bit), std::end(XMMArgRegs64Bit));
2392 X86TargetLowering::LowerFormalArguments(SDValue Chain,
2393 CallingConv::ID CallConv,
2395 const SmallVectorImpl<ISD::InputArg> &Ins,
2398 SmallVectorImpl<SDValue> &InVals)
2400 MachineFunction &MF = DAG.getMachineFunction();
2401 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
2403 const Function* Fn = MF.getFunction();
2404 if (Fn->hasExternalLinkage() &&
2405 Subtarget->isTargetCygMing() &&
2406 Fn->getName() == "main")
2407 FuncInfo->setForceFramePointer(true);
2409 MachineFrameInfo *MFI = MF.getFrameInfo();
2410 bool Is64Bit = Subtarget->is64Bit();
2411 bool IsWin64 = Subtarget->isCallingConvWin64(CallConv);
2413 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
2414 "Var args not supported with calling convention fastcc, ghc or hipe");
2416 // Assign locations to all of the incoming arguments.
2417 SmallVector<CCValAssign, 16> ArgLocs;
2418 CCState CCInfo(CallConv, isVarArg, MF, ArgLocs, *DAG.getContext());
2420 // Allocate shadow area for Win64
2422 CCInfo.AllocateStack(32, 8);
2424 CCInfo.AnalyzeFormalArguments(Ins, CC_X86);
2426 unsigned LastVal = ~0U;
2428 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2429 CCValAssign &VA = ArgLocs[i];
2430 // TODO: If an arg is passed in two places (e.g. reg and stack), skip later
2432 assert(VA.getValNo() != LastVal &&
2433 "Don't support value assigned to multiple locs yet");
2435 LastVal = VA.getValNo();
2437 if (VA.isRegLoc()) {
2438 EVT RegVT = VA.getLocVT();
2439 const TargetRegisterClass *RC;
2440 if (RegVT == MVT::i32)
2441 RC = &X86::GR32RegClass;
2442 else if (Is64Bit && RegVT == MVT::i64)
2443 RC = &X86::GR64RegClass;
2444 else if (RegVT == MVT::f32)
2445 RC = &X86::FR32RegClass;
2446 else if (RegVT == MVT::f64)
2447 RC = &X86::FR64RegClass;
2448 else if (RegVT.is512BitVector())
2449 RC = &X86::VR512RegClass;
2450 else if (RegVT.is256BitVector())
2451 RC = &X86::VR256RegClass;
2452 else if (RegVT.is128BitVector())
2453 RC = &X86::VR128RegClass;
2454 else if (RegVT == MVT::x86mmx)
2455 RC = &X86::VR64RegClass;
2456 else if (RegVT == MVT::i1)
2457 RC = &X86::VK1RegClass;
2458 else if (RegVT == MVT::v8i1)
2459 RC = &X86::VK8RegClass;
2460 else if (RegVT == MVT::v16i1)
2461 RC = &X86::VK16RegClass;
2462 else if (RegVT == MVT::v32i1)
2463 RC = &X86::VK32RegClass;
2464 else if (RegVT == MVT::v64i1)
2465 RC = &X86::VK64RegClass;
2467 llvm_unreachable("Unknown argument type!");
2469 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
2470 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
2472 // If this is an 8 or 16-bit value, it is really passed promoted to 32
2473 // bits. Insert an assert[sz]ext to capture this, then truncate to the
2475 if (VA.getLocInfo() == CCValAssign::SExt)
2476 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
2477 DAG.getValueType(VA.getValVT()));
2478 else if (VA.getLocInfo() == CCValAssign::ZExt)
2479 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
2480 DAG.getValueType(VA.getValVT()));
2481 else if (VA.getLocInfo() == CCValAssign::BCvt)
2482 ArgValue = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), ArgValue);
2484 if (VA.isExtInLoc()) {
2485 // Handle MMX values passed in XMM regs.
2486 if (RegVT.isVector())
2487 ArgValue = DAG.getNode(X86ISD::MOVDQ2Q, dl, VA.getValVT(), ArgValue);
2489 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
2492 assert(VA.isMemLoc());
2493 ArgValue = LowerMemArgument(Chain, CallConv, Ins, dl, DAG, VA, MFI, i);
2496 // If value is passed via pointer - do a load.
2497 if (VA.getLocInfo() == CCValAssign::Indirect)
2498 ArgValue = DAG.getLoad(VA.getValVT(), dl, Chain, ArgValue,
2499 MachinePointerInfo(), false, false, false, 0);
2501 InVals.push_back(ArgValue);
2504 if (Subtarget->is64Bit() || Subtarget->isTargetKnownWindowsMSVC()) {
2505 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2506 // The x86-64 ABIs require that for returning structs by value we copy
2507 // the sret argument into %rax/%eax (depending on ABI) for the return.
2508 // Win32 requires us to put the sret argument to %eax as well.
2509 // Save the argument into a virtual register so that we can access it
2510 // from the return points.
2511 if (Ins[i].Flags.isSRet()) {
2512 unsigned Reg = FuncInfo->getSRetReturnReg();
2514 MVT PtrTy = getPointerTy();
2515 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(PtrTy));
2516 FuncInfo->setSRetReturnReg(Reg);
2518 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, InVals[i]);
2519 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain);
2525 unsigned StackSize = CCInfo.getNextStackOffset();
2526 // Align stack specially for tail calls.
2527 if (FuncIsMadeTailCallSafe(CallConv,
2528 MF.getTarget().Options.GuaranteedTailCallOpt))
2529 StackSize = GetAlignedArgumentStackSize(StackSize, DAG);
2531 // If the function takes variable number of arguments, make a frame index for
2532 // the start of the first vararg value... for expansion of llvm.va_start. We
2533 // can skip this if there are no va_start calls.
2534 if (MFI->hasVAStart() &&
2535 (Is64Bit || (CallConv != CallingConv::X86_FastCall &&
2536 CallConv != CallingConv::X86_ThisCall))) {
2537 FuncInfo->setVarArgsFrameIndex(
2538 MFI->CreateFixedObject(1, StackSize, true));
2541 // 64-bit calling conventions support varargs and register parameters, so we
2542 // have to do extra work to spill them in the prologue or forward them to
2544 if (Is64Bit && isVarArg &&
2545 (MFI->hasVAStart() || MFI->hasMustTailInVarArgFunc())) {
2546 // Find the first unallocated argument registers.
2547 ArrayRef<MCPhysReg> ArgGPRs = get64BitArgumentGPRs(CallConv, Subtarget);
2548 ArrayRef<MCPhysReg> ArgXMMs = get64BitArgumentXMMs(MF, CallConv, Subtarget);
2549 unsigned NumIntRegs =
2550 CCInfo.getFirstUnallocated(ArgGPRs.data(), ArgGPRs.size());
2551 unsigned NumXMMRegs =
2552 CCInfo.getFirstUnallocated(ArgXMMs.data(), ArgXMMs.size());
2553 assert(!(NumXMMRegs && !Subtarget->hasSSE1()) &&
2554 "SSE register cannot be used when SSE is disabled!");
2556 // Gather all the live in physical registers.
2557 SmallVector<SDValue, 6> LiveGPRs;
2558 SmallVector<SDValue, 8> LiveXMMRegs;
2560 for (MCPhysReg Reg : ArgGPRs.slice(NumIntRegs)) {
2561 unsigned GPR = MF.addLiveIn(Reg, &X86::GR64RegClass);
2563 DAG.getCopyFromReg(Chain, dl, GPR, MVT::i64));
2565 if (!ArgXMMs.empty()) {
2566 unsigned AL = MF.addLiveIn(X86::AL, &X86::GR8RegClass);
2567 ALVal = DAG.getCopyFromReg(Chain, dl, AL, MVT::i8);
2568 for (MCPhysReg Reg : ArgXMMs.slice(NumXMMRegs)) {
2569 unsigned XMMReg = MF.addLiveIn(Reg, &X86::VR128RegClass);
2570 LiveXMMRegs.push_back(
2571 DAG.getCopyFromReg(Chain, dl, XMMReg, MVT::v4f32));
2575 // Store them to the va_list returned by va_start.
2576 if (MFI->hasVAStart()) {
2578 const TargetFrameLowering &TFI = *MF.getSubtarget().getFrameLowering();
2579 // Get to the caller-allocated home save location. Add 8 to account
2580 // for the return address.
2581 int HomeOffset = TFI.getOffsetOfLocalArea() + 8;
2582 FuncInfo->setRegSaveFrameIndex(
2583 MFI->CreateFixedObject(1, NumIntRegs * 8 + HomeOffset, false));
2584 // Fixup to set vararg frame on shadow area (4 x i64).
2586 FuncInfo->setVarArgsFrameIndex(FuncInfo->getRegSaveFrameIndex());
2588 // For X86-64, if there are vararg parameters that are passed via
2589 // registers, then we must store them to their spots on the stack so
2590 // they may be loaded by deferencing the result of va_next.
2591 FuncInfo->setVarArgsGPOffset(NumIntRegs * 8);
2592 FuncInfo->setVarArgsFPOffset(ArgGPRs.size() * 8 + NumXMMRegs * 16);
2593 FuncInfo->setRegSaveFrameIndex(MFI->CreateStackObject(
2594 ArgGPRs.size() * 8 + ArgXMMs.size() * 16, 16, false));
2597 // Store the integer parameter registers.
2598 SmallVector<SDValue, 8> MemOps;
2599 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
2601 unsigned Offset = FuncInfo->getVarArgsGPOffset();
2602 for (SDValue Val : LiveGPRs) {
2603 SDValue FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), RSFIN,
2604 DAG.getIntPtrConstant(Offset));
2606 DAG.getStore(Val.getValue(1), dl, Val, FIN,
2607 MachinePointerInfo::getFixedStack(
2608 FuncInfo->getRegSaveFrameIndex(), Offset),
2610 MemOps.push_back(Store);
2614 if (!ArgXMMs.empty() && NumXMMRegs != ArgXMMs.size()) {
2615 // Now store the XMM (fp + vector) parameter registers.
2616 SmallVector<SDValue, 12> SaveXMMOps;
2617 SaveXMMOps.push_back(Chain);
2618 SaveXMMOps.push_back(ALVal);
2619 SaveXMMOps.push_back(DAG.getIntPtrConstant(
2620 FuncInfo->getRegSaveFrameIndex()));
2621 SaveXMMOps.push_back(DAG.getIntPtrConstant(
2622 FuncInfo->getVarArgsFPOffset()));
2623 SaveXMMOps.insert(SaveXMMOps.end(), LiveXMMRegs.begin(),
2625 MemOps.push_back(DAG.getNode(X86ISD::VASTART_SAVE_XMM_REGS, dl,
2626 MVT::Other, SaveXMMOps));
2629 if (!MemOps.empty())
2630 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps);
2632 // Add all GPRs, al, and XMMs to the list of forwards. We will add then
2633 // to the liveout set on a musttail call.
2634 assert(MFI->hasMustTailInVarArgFunc());
2635 auto &Forwards = FuncInfo->getForwardedMustTailRegParms();
2636 typedef X86MachineFunctionInfo::Forward Forward;
2638 for (unsigned I = 0, E = LiveGPRs.size(); I != E; ++I) {
2640 MF.getRegInfo().createVirtualRegister(&X86::GR64RegClass);
2641 Chain = DAG.getCopyToReg(Chain, dl, VReg, LiveGPRs[I]);
2642 Forwards.push_back(Forward(VReg, ArgGPRs[NumIntRegs + I], MVT::i64));
2645 if (!ArgXMMs.empty()) {
2647 MF.getRegInfo().createVirtualRegister(&X86::GR8RegClass);
2648 Chain = DAG.getCopyToReg(Chain, dl, ALVReg, ALVal);
2649 Forwards.push_back(Forward(ALVReg, X86::AL, MVT::i8));
2651 for (unsigned I = 0, E = LiveXMMRegs.size(); I != E; ++I) {
2653 MF.getRegInfo().createVirtualRegister(&X86::VR128RegClass);
2654 Chain = DAG.getCopyToReg(Chain, dl, VReg, LiveXMMRegs[I]);
2656 Forward(VReg, ArgXMMs[NumXMMRegs + I], MVT::v4f32));
2662 // Some CCs need callee pop.
2663 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg,
2664 MF.getTarget().Options.GuaranteedTailCallOpt)) {
2665 FuncInfo->setBytesToPopOnReturn(StackSize); // Callee pops everything.
2667 FuncInfo->setBytesToPopOnReturn(0); // Callee pops nothing.
2668 // If this is an sret function, the return should pop the hidden pointer.
2669 if (!Is64Bit && !IsTailCallConvention(CallConv) &&
2670 !Subtarget->getTargetTriple().isOSMSVCRT() &&
2671 argsAreStructReturn(Ins) == StackStructReturn)
2672 FuncInfo->setBytesToPopOnReturn(4);
2676 // RegSaveFrameIndex is X86-64 only.
2677 FuncInfo->setRegSaveFrameIndex(0xAAAAAAA);
2678 if (CallConv == CallingConv::X86_FastCall ||
2679 CallConv == CallingConv::X86_ThisCall)
2680 // fastcc functions can't have varargs.
2681 FuncInfo->setVarArgsFrameIndex(0xAAAAAAA);
2684 FuncInfo->setArgumentStackSize(StackSize);
2690 X86TargetLowering::LowerMemOpCallTo(SDValue Chain,
2691 SDValue StackPtr, SDValue Arg,
2692 SDLoc dl, SelectionDAG &DAG,
2693 const CCValAssign &VA,
2694 ISD::ArgFlagsTy Flags) const {
2695 unsigned LocMemOffset = VA.getLocMemOffset();
2696 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
2697 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
2698 if (Flags.isByVal())
2699 return CreateCopyOfByValArgument(Arg, PtrOff, Chain, Flags, DAG, dl);
2701 return DAG.getStore(Chain, dl, Arg, PtrOff,
2702 MachinePointerInfo::getStack(LocMemOffset),
2706 /// EmitTailCallLoadRetAddr - Emit a load of return address if tail call
2707 /// optimization is performed and it is required.
2709 X86TargetLowering::EmitTailCallLoadRetAddr(SelectionDAG &DAG,
2710 SDValue &OutRetAddr, SDValue Chain,
2711 bool IsTailCall, bool Is64Bit,
2712 int FPDiff, SDLoc dl) const {
2713 // Adjust the Return address stack slot.
2714 EVT VT = getPointerTy();
2715 OutRetAddr = getReturnAddressFrameIndex(DAG);
2717 // Load the "old" Return address.
2718 OutRetAddr = DAG.getLoad(VT, dl, Chain, OutRetAddr, MachinePointerInfo(),
2719 false, false, false, 0);
2720 return SDValue(OutRetAddr.getNode(), 1);
2723 /// EmitTailCallStoreRetAddr - Emit a store of the return address if tail call
2724 /// optimization is performed and it is required (FPDiff!=0).
2725 static SDValue EmitTailCallStoreRetAddr(SelectionDAG &DAG, MachineFunction &MF,
2726 SDValue Chain, SDValue RetAddrFrIdx,
2727 EVT PtrVT, unsigned SlotSize,
2728 int FPDiff, SDLoc dl) {
2729 // Store the return address to the appropriate stack slot.
2730 if (!FPDiff) return Chain;
2731 // Calculate the new stack slot for the return address.
2732 int NewReturnAddrFI =
2733 MF.getFrameInfo()->CreateFixedObject(SlotSize, (int64_t)FPDiff - SlotSize,
2735 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewReturnAddrFI, PtrVT);
2736 Chain = DAG.getStore(Chain, dl, RetAddrFrIdx, NewRetAddrFrIdx,
2737 MachinePointerInfo::getFixedStack(NewReturnAddrFI),
2743 X86TargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
2744 SmallVectorImpl<SDValue> &InVals) const {
2745 SelectionDAG &DAG = CLI.DAG;
2747 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
2748 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
2749 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
2750 SDValue Chain = CLI.Chain;
2751 SDValue Callee = CLI.Callee;
2752 CallingConv::ID CallConv = CLI.CallConv;
2753 bool &isTailCall = CLI.IsTailCall;
2754 bool isVarArg = CLI.IsVarArg;
2756 MachineFunction &MF = DAG.getMachineFunction();
2757 bool Is64Bit = Subtarget->is64Bit();
2758 bool IsWin64 = Subtarget->isCallingConvWin64(CallConv);
2759 StructReturnType SR = callIsStructReturn(Outs);
2760 bool IsSibcall = false;
2761 X86MachineFunctionInfo *X86Info = MF.getInfo<X86MachineFunctionInfo>();
2763 if (MF.getTarget().Options.DisableTailCalls)
2766 bool IsMustTail = CLI.CS && CLI.CS->isMustTailCall();
2768 // Force this to be a tail call. The verifier rules are enough to ensure
2769 // that we can lower this successfully without moving the return address
2772 } else if (isTailCall) {
2773 // Check if it's really possible to do a tail call.
2774 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv,
2775 isVarArg, SR != NotStructReturn,
2776 MF.getFunction()->hasStructRetAttr(), CLI.RetTy,
2777 Outs, OutVals, Ins, DAG);
2779 // Sibcalls are automatically detected tailcalls which do not require
2781 if (!MF.getTarget().Options.GuaranteedTailCallOpt && isTailCall)
2788 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
2789 "Var args not supported with calling convention fastcc, ghc or hipe");
2791 // Analyze operands of the call, assigning locations to each operand.
2792 SmallVector<CCValAssign, 16> ArgLocs;
2793 CCState CCInfo(CallConv, isVarArg, MF, ArgLocs, *DAG.getContext());
2795 // Allocate shadow area for Win64
2797 CCInfo.AllocateStack(32, 8);
2799 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
2801 // Get a count of how many bytes are to be pushed on the stack.
2802 unsigned NumBytes = CCInfo.getNextStackOffset();
2804 // This is a sibcall. The memory operands are available in caller's
2805 // own caller's stack.
2807 else if (MF.getTarget().Options.GuaranteedTailCallOpt &&
2808 IsTailCallConvention(CallConv))
2809 NumBytes = GetAlignedArgumentStackSize(NumBytes, DAG);
2812 if (isTailCall && !IsSibcall && !IsMustTail) {
2813 // Lower arguments at fp - stackoffset + fpdiff.
2814 unsigned NumBytesCallerPushed = X86Info->getBytesToPopOnReturn();
2816 FPDiff = NumBytesCallerPushed - NumBytes;
2818 // Set the delta of movement of the returnaddr stackslot.
2819 // But only set if delta is greater than previous delta.
2820 if (FPDiff < X86Info->getTCReturnAddrDelta())
2821 X86Info->setTCReturnAddrDelta(FPDiff);
2824 unsigned NumBytesToPush = NumBytes;
2825 unsigned NumBytesToPop = NumBytes;
2827 // If we have an inalloca argument, all stack space has already been allocated
2828 // for us and be right at the top of the stack. We don't support multiple
2829 // arguments passed in memory when using inalloca.
2830 if (!Outs.empty() && Outs.back().Flags.isInAlloca()) {
2832 if (!ArgLocs.back().isMemLoc())
2833 report_fatal_error("cannot use inalloca attribute on a register "
2835 if (ArgLocs.back().getLocMemOffset() != 0)
2836 report_fatal_error("any parameter with the inalloca attribute must be "
2837 "the only memory argument");
2841 Chain = DAG.getCALLSEQ_START(
2842 Chain, DAG.getIntPtrConstant(NumBytesToPush, true), dl);
2844 SDValue RetAddrFrIdx;
2845 // Load return address for tail calls.
2846 if (isTailCall && FPDiff)
2847 Chain = EmitTailCallLoadRetAddr(DAG, RetAddrFrIdx, Chain, isTailCall,
2848 Is64Bit, FPDiff, dl);
2850 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
2851 SmallVector<SDValue, 8> MemOpChains;
2854 // Walk the register/memloc assignments, inserting copies/loads. In the case
2855 // of tail call optimization arguments are handle later.
2856 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
2857 DAG.getSubtarget().getRegisterInfo());
2858 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2859 // Skip inalloca arguments, they have already been written.
2860 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2861 if (Flags.isInAlloca())
2864 CCValAssign &VA = ArgLocs[i];
2865 EVT RegVT = VA.getLocVT();
2866 SDValue Arg = OutVals[i];
2867 bool isByVal = Flags.isByVal();
2869 // Promote the value if needed.
2870 switch (VA.getLocInfo()) {
2871 default: llvm_unreachable("Unknown loc info!");
2872 case CCValAssign::Full: break;
2873 case CCValAssign::SExt:
2874 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, RegVT, Arg);
2876 case CCValAssign::ZExt:
2877 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, RegVT, Arg);
2879 case CCValAssign::AExt:
2880 if (RegVT.is128BitVector()) {
2881 // Special case: passing MMX values in XMM registers.
2882 Arg = DAG.getNode(ISD::BITCAST, dl, MVT::i64, Arg);
2883 Arg = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, Arg);
2884 Arg = getMOVL(DAG, dl, MVT::v2i64, DAG.getUNDEF(MVT::v2i64), Arg);
2886 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, RegVT, Arg);
2888 case CCValAssign::BCvt:
2889 Arg = DAG.getNode(ISD::BITCAST, dl, RegVT, Arg);
2891 case CCValAssign::Indirect: {
2892 // Store the argument.
2893 SDValue SpillSlot = DAG.CreateStackTemporary(VA.getValVT());
2894 int FI = cast<FrameIndexSDNode>(SpillSlot)->getIndex();
2895 Chain = DAG.getStore(Chain, dl, Arg, SpillSlot,
2896 MachinePointerInfo::getFixedStack(FI),
2903 if (VA.isRegLoc()) {
2904 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
2905 if (isVarArg && IsWin64) {
2906 // Win64 ABI requires argument XMM reg to be copied to the corresponding
2907 // shadow reg if callee is a varargs function.
2908 unsigned ShadowReg = 0;
2909 switch (VA.getLocReg()) {
2910 case X86::XMM0: ShadowReg = X86::RCX; break;
2911 case X86::XMM1: ShadowReg = X86::RDX; break;
2912 case X86::XMM2: ShadowReg = X86::R8; break;
2913 case X86::XMM3: ShadowReg = X86::R9; break;
2916 RegsToPass.push_back(std::make_pair(ShadowReg, Arg));
2918 } else if (!IsSibcall && (!isTailCall || isByVal)) {
2919 assert(VA.isMemLoc());
2920 if (!StackPtr.getNode())
2921 StackPtr = DAG.getCopyFromReg(Chain, dl, RegInfo->getStackRegister(),
2923 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Arg,
2924 dl, DAG, VA, Flags));
2928 if (!MemOpChains.empty())
2929 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains);
2931 if (Subtarget->isPICStyleGOT()) {
2932 // ELF / PIC requires GOT in the EBX register before function calls via PLT
2935 RegsToPass.push_back(std::make_pair(unsigned(X86::EBX),
2936 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), getPointerTy())));
2938 // If we are tail calling and generating PIC/GOT style code load the
2939 // address of the callee into ECX. The value in ecx is used as target of
2940 // the tail jump. This is done to circumvent the ebx/callee-saved problem
2941 // for tail calls on PIC/GOT architectures. Normally we would just put the
2942 // address of GOT into ebx and then call target@PLT. But for tail calls
2943 // ebx would be restored (since ebx is callee saved) before jumping to the
2946 // Note: The actual moving to ECX is done further down.
2947 GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee);
2948 if (G && !G->getGlobal()->hasHiddenVisibility() &&
2949 !G->getGlobal()->hasProtectedVisibility())
2950 Callee = LowerGlobalAddress(Callee, DAG);
2951 else if (isa<ExternalSymbolSDNode>(Callee))
2952 Callee = LowerExternalSymbol(Callee, DAG);
2956 if (Is64Bit && isVarArg && !IsWin64 && !IsMustTail) {
2957 // From AMD64 ABI document:
2958 // For calls that may call functions that use varargs or stdargs
2959 // (prototype-less calls or calls to functions containing ellipsis (...) in
2960 // the declaration) %al is used as hidden argument to specify the number
2961 // of SSE registers used. The contents of %al do not need to match exactly
2962 // the number of registers, but must be an ubound on the number of SSE
2963 // registers used and is in the range 0 - 8 inclusive.
2965 // Count the number of XMM registers allocated.
2966 static const MCPhysReg XMMArgRegs[] = {
2967 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
2968 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
2970 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs, 8);
2971 assert((Subtarget->hasSSE1() || !NumXMMRegs)
2972 && "SSE registers cannot be used when SSE is disabled");
2974 RegsToPass.push_back(std::make_pair(unsigned(X86::AL),
2975 DAG.getConstant(NumXMMRegs, MVT::i8)));
2978 if (Is64Bit && isVarArg && IsMustTail) {
2979 const auto &Forwards = X86Info->getForwardedMustTailRegParms();
2980 for (const auto &F : Forwards) {
2981 SDValue Val = DAG.getCopyFromReg(Chain, dl, F.VReg, F.VT);
2982 RegsToPass.push_back(std::make_pair(unsigned(F.PReg), Val));
2986 // For tail calls lower the arguments to the 'real' stack slots. Sibcalls
2987 // don't need this because the eligibility check rejects calls that require
2988 // shuffling arguments passed in memory.
2989 if (!IsSibcall && isTailCall) {
2990 // Force all the incoming stack arguments to be loaded from the stack
2991 // before any new outgoing arguments are stored to the stack, because the
2992 // outgoing stack slots may alias the incoming argument stack slots, and
2993 // the alias isn't otherwise explicit. This is slightly more conservative
2994 // than necessary, because it means that each store effectively depends
2995 // on every argument instead of just those arguments it would clobber.
2996 SDValue ArgChain = DAG.getStackArgumentTokenFactor(Chain);
2998 SmallVector<SDValue, 8> MemOpChains2;
3001 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3002 CCValAssign &VA = ArgLocs[i];
3005 assert(VA.isMemLoc());
3006 SDValue Arg = OutVals[i];
3007 ISD::ArgFlagsTy Flags = Outs[i].Flags;
3008 // Skip inalloca arguments. They don't require any work.
3009 if (Flags.isInAlloca())
3011 // Create frame index.
3012 int32_t Offset = VA.getLocMemOffset()+FPDiff;
3013 uint32_t OpSize = (VA.getLocVT().getSizeInBits()+7)/8;
3014 FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true);
3015 FIN = DAG.getFrameIndex(FI, getPointerTy());
3017 if (Flags.isByVal()) {
3018 // Copy relative to framepointer.
3019 SDValue Source = DAG.getIntPtrConstant(VA.getLocMemOffset());
3020 if (!StackPtr.getNode())
3021 StackPtr = DAG.getCopyFromReg(Chain, dl,
3022 RegInfo->getStackRegister(),
3024 Source = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, Source);
3026 MemOpChains2.push_back(CreateCopyOfByValArgument(Source, FIN,
3030 // Store relative to framepointer.
3031 MemOpChains2.push_back(
3032 DAG.getStore(ArgChain, dl, Arg, FIN,
3033 MachinePointerInfo::getFixedStack(FI),
3038 if (!MemOpChains2.empty())
3039 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains2);
3041 // Store the return address to the appropriate stack slot.
3042 Chain = EmitTailCallStoreRetAddr(DAG, MF, Chain, RetAddrFrIdx,
3043 getPointerTy(), RegInfo->getSlotSize(),
3047 // Build a sequence of copy-to-reg nodes chained together with token chain
3048 // and flag operands which copy the outgoing args into registers.
3050 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
3051 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
3052 RegsToPass[i].second, InFlag);
3053 InFlag = Chain.getValue(1);
3056 if (DAG.getTarget().getCodeModel() == CodeModel::Large) {
3057 assert(Is64Bit && "Large code model is only legal in 64-bit mode.");
3058 // In the 64-bit large code model, we have to make all calls
3059 // through a register, since the call instruction's 32-bit
3060 // pc-relative offset may not be large enough to hold the whole
3062 } else if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
3063 // If the callee is a GlobalAddress node (quite common, every direct call
3064 // is) turn it into a TargetGlobalAddress node so that legalize doesn't hack
3067 // We should use extra load for direct calls to dllimported functions in
3069 const GlobalValue *GV = G->getGlobal();
3070 if (!GV->hasDLLImportStorageClass()) {
3071 unsigned char OpFlags = 0;
3072 bool ExtraLoad = false;
3073 unsigned WrapperKind = ISD::DELETED_NODE;
3075 // On ELF targets, in both X86-64 and X86-32 mode, direct calls to
3076 // external symbols most go through the PLT in PIC mode. If the symbol
3077 // has hidden or protected visibility, or if it is static or local, then
3078 // we don't need to use the PLT - we can directly call it.
3079 if (Subtarget->isTargetELF() &&
3080 DAG.getTarget().getRelocationModel() == Reloc::PIC_ &&
3081 GV->hasDefaultVisibility() && !GV->hasLocalLinkage()) {
3082 OpFlags = X86II::MO_PLT;
3083 } else if (Subtarget->isPICStyleStubAny() &&
3084 (GV->isDeclaration() || GV->isWeakForLinker()) &&
3085 (!Subtarget->getTargetTriple().isMacOSX() ||
3086 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
3087 // PC-relative references to external symbols should go through $stub,
3088 // unless we're building with the leopard linker or later, which
3089 // automatically synthesizes these stubs.
3090 OpFlags = X86II::MO_DARWIN_STUB;
3091 } else if (Subtarget->isPICStyleRIPRel() &&
3092 isa<Function>(GV) &&
3093 cast<Function>(GV)->getAttributes().
3094 hasAttribute(AttributeSet::FunctionIndex,
3095 Attribute::NonLazyBind)) {
3096 // If the function is marked as non-lazy, generate an indirect call
3097 // which loads from the GOT directly. This avoids runtime overhead
3098 // at the cost of eager binding (and one extra byte of encoding).
3099 OpFlags = X86II::MO_GOTPCREL;
3100 WrapperKind = X86ISD::WrapperRIP;
3104 Callee = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(),
3105 G->getOffset(), OpFlags);
3107 // Add a wrapper if needed.
3108 if (WrapperKind != ISD::DELETED_NODE)
3109 Callee = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Callee);
3110 // Add extra indirection if needed.
3112 Callee = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Callee,
3113 MachinePointerInfo::getGOT(),
3114 false, false, false, 0);
3116 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
3117 unsigned char OpFlags = 0;
3119 // On ELF targets, in either X86-64 or X86-32 mode, direct calls to
3120 // external symbols should go through the PLT.
3121 if (Subtarget->isTargetELF() &&
3122 DAG.getTarget().getRelocationModel() == Reloc::PIC_) {
3123 OpFlags = X86II::MO_PLT;
3124 } else if (Subtarget->isPICStyleStubAny() &&
3125 (!Subtarget->getTargetTriple().isMacOSX() ||
3126 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
3127 // PC-relative references to external symbols should go through $stub,
3128 // unless we're building with the leopard linker or later, which
3129 // automatically synthesizes these stubs.
3130 OpFlags = X86II::MO_DARWIN_STUB;
3133 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy(),
3135 } else if (Subtarget->isTarget64BitILP32() && Callee->getValueType(0) == MVT::i32) {
3136 // Zero-extend the 32-bit Callee address into a 64-bit according to x32 ABI
3137 Callee = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i64, Callee);
3140 // Returns a chain & a flag for retval copy to use.
3141 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
3142 SmallVector<SDValue, 8> Ops;
3144 if (!IsSibcall && isTailCall) {
3145 Chain = DAG.getCALLSEQ_END(Chain,
3146 DAG.getIntPtrConstant(NumBytesToPop, true),
3147 DAG.getIntPtrConstant(0, true), InFlag, dl);
3148 InFlag = Chain.getValue(1);
3151 Ops.push_back(Chain);
3152 Ops.push_back(Callee);
3155 Ops.push_back(DAG.getConstant(FPDiff, MVT::i32));
3157 // Add argument registers to the end of the list so that they are known live
3159 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
3160 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
3161 RegsToPass[i].second.getValueType()));
3163 // Add a register mask operand representing the call-preserved registers.
3164 const TargetRegisterInfo *TRI = DAG.getSubtarget().getRegisterInfo();
3165 const uint32_t *Mask = TRI->getCallPreservedMask(CallConv);
3166 assert(Mask && "Missing call preserved mask for calling convention");
3167 Ops.push_back(DAG.getRegisterMask(Mask));
3169 if (InFlag.getNode())
3170 Ops.push_back(InFlag);
3174 //// If this is the first return lowered for this function, add the regs
3175 //// to the liveout set for the function.
3176 // This isn't right, although it's probably harmless on x86; liveouts
3177 // should be computed from returns not tail calls. Consider a void
3178 // function making a tail call to a function returning int.
3179 return DAG.getNode(X86ISD::TC_RETURN, dl, NodeTys, Ops);
3182 Chain = DAG.getNode(X86ISD::CALL, dl, NodeTys, Ops);
3183 InFlag = Chain.getValue(1);
3185 // Create the CALLSEQ_END node.
3186 unsigned NumBytesForCalleeToPop;
3187 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg,
3188 DAG.getTarget().Options.GuaranteedTailCallOpt))
3189 NumBytesForCalleeToPop = NumBytes; // Callee pops everything
3190 else if (!Is64Bit && !IsTailCallConvention(CallConv) &&
3191 !Subtarget->getTargetTriple().isOSMSVCRT() &&
3192 SR == StackStructReturn)
3193 // If this is a call to a struct-return function, the callee
3194 // pops the hidden struct pointer, so we have to push it back.
3195 // This is common for Darwin/X86, Linux & Mingw32 targets.
3196 // For MSVC Win32 targets, the caller pops the hidden struct pointer.
3197 NumBytesForCalleeToPop = 4;
3199 NumBytesForCalleeToPop = 0; // Callee pops nothing.
3201 // Returns a flag for retval copy to use.
3203 Chain = DAG.getCALLSEQ_END(Chain,
3204 DAG.getIntPtrConstant(NumBytesToPop, true),
3205 DAG.getIntPtrConstant(NumBytesForCalleeToPop,
3208 InFlag = Chain.getValue(1);
3211 // Handle result values, copying them out of physregs into vregs that we
3213 return LowerCallResult(Chain, InFlag, CallConv, isVarArg,
3214 Ins, dl, DAG, InVals);
3217 //===----------------------------------------------------------------------===//
3218 // Fast Calling Convention (tail call) implementation
3219 //===----------------------------------------------------------------------===//
3221 // Like std call, callee cleans arguments, convention except that ECX is
3222 // reserved for storing the tail called function address. Only 2 registers are
3223 // free for argument passing (inreg). Tail call optimization is performed
3225 // * tailcallopt is enabled
3226 // * caller/callee are fastcc
3227 // On X86_64 architecture with GOT-style position independent code only local
3228 // (within module) calls are supported at the moment.
3229 // To keep the stack aligned according to platform abi the function
3230 // GetAlignedArgumentStackSize ensures that argument delta is always multiples
3231 // of stack alignment. (Dynamic linkers need this - darwin's dyld for example)
3232 // If a tail called function callee has more arguments than the caller the
3233 // caller needs to make sure that there is room to move the RETADDR to. This is
3234 // achieved by reserving an area the size of the argument delta right after the
3235 // original RETADDR, but before the saved framepointer or the spilled registers
3236 // e.g. caller(arg1, arg2) calls callee(arg1, arg2,arg3,arg4)
3248 /// GetAlignedArgumentStackSize - Make the stack size align e.g 16n + 12 aligned
3249 /// for a 16 byte align requirement.
3251 X86TargetLowering::GetAlignedArgumentStackSize(unsigned StackSize,
3252 SelectionDAG& DAG) const {
3253 MachineFunction &MF = DAG.getMachineFunction();
3254 const TargetMachine &TM = MF.getTarget();
3255 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
3256 TM.getSubtargetImpl()->getRegisterInfo());
3257 const TargetFrameLowering &TFI = *TM.getSubtargetImpl()->getFrameLowering();
3258 unsigned StackAlignment = TFI.getStackAlignment();
3259 uint64_t AlignMask = StackAlignment - 1;
3260 int64_t Offset = StackSize;
3261 unsigned SlotSize = RegInfo->getSlotSize();
3262 if ( (Offset & AlignMask) <= (StackAlignment - SlotSize) ) {
3263 // Number smaller than 12 so just add the difference.
3264 Offset += ((StackAlignment - SlotSize) - (Offset & AlignMask));
3266 // Mask out lower bits, add stackalignment once plus the 12 bytes.
3267 Offset = ((~AlignMask) & Offset) + StackAlignment +
3268 (StackAlignment-SlotSize);
3273 /// MatchingStackOffset - Return true if the given stack call argument is
3274 /// already available in the same position (relatively) of the caller's
3275 /// incoming argument stack.
3277 bool MatchingStackOffset(SDValue Arg, unsigned Offset, ISD::ArgFlagsTy Flags,
3278 MachineFrameInfo *MFI, const MachineRegisterInfo *MRI,
3279 const X86InstrInfo *TII) {
3280 unsigned Bytes = Arg.getValueType().getSizeInBits() / 8;
3282 if (Arg.getOpcode() == ISD::CopyFromReg) {
3283 unsigned VR = cast<RegisterSDNode>(Arg.getOperand(1))->getReg();
3284 if (!TargetRegisterInfo::isVirtualRegister(VR))
3286 MachineInstr *Def = MRI->getVRegDef(VR);
3289 if (!Flags.isByVal()) {
3290 if (!TII->isLoadFromStackSlot(Def, FI))
3293 unsigned Opcode = Def->getOpcode();
3294 if ((Opcode == X86::LEA32r || Opcode == X86::LEA64r) &&
3295 Def->getOperand(1).isFI()) {
3296 FI = Def->getOperand(1).getIndex();
3297 Bytes = Flags.getByValSize();
3301 } else if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Arg)) {
3302 if (Flags.isByVal())
3303 // ByVal argument is passed in as a pointer but it's now being
3304 // dereferenced. e.g.
3305 // define @foo(%struct.X* %A) {
3306 // tail call @bar(%struct.X* byval %A)
3309 SDValue Ptr = Ld->getBasePtr();
3310 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr);
3313 FI = FINode->getIndex();
3314 } else if (Arg.getOpcode() == ISD::FrameIndex && Flags.isByVal()) {
3315 FrameIndexSDNode *FINode = cast<FrameIndexSDNode>(Arg);
3316 FI = FINode->getIndex();
3317 Bytes = Flags.getByValSize();
3321 assert(FI != INT_MAX);
3322 if (!MFI->isFixedObjectIndex(FI))
3324 return Offset == MFI->getObjectOffset(FI) && Bytes == MFI->getObjectSize(FI);
3327 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
3328 /// for tail call optimization. Targets which want to do tail call
3329 /// optimization should implement this function.
3331 X86TargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
3332 CallingConv::ID CalleeCC,
3334 bool isCalleeStructRet,
3335 bool isCallerStructRet,
3337 const SmallVectorImpl<ISD::OutputArg> &Outs,
3338 const SmallVectorImpl<SDValue> &OutVals,
3339 const SmallVectorImpl<ISD::InputArg> &Ins,
3340 SelectionDAG &DAG) const {
3341 if (!IsTailCallConvention(CalleeCC) && !IsCCallConvention(CalleeCC))
3344 // If -tailcallopt is specified, make fastcc functions tail-callable.
3345 const MachineFunction &MF = DAG.getMachineFunction();
3346 const Function *CallerF = MF.getFunction();
3348 // If the function return type is x86_fp80 and the callee return type is not,
3349 // then the FP_EXTEND of the call result is not a nop. It's not safe to
3350 // perform a tailcall optimization here.
3351 if (CallerF->getReturnType()->isX86_FP80Ty() && !RetTy->isX86_FP80Ty())
3354 CallingConv::ID CallerCC = CallerF->getCallingConv();
3355 bool CCMatch = CallerCC == CalleeCC;
3356 bool IsCalleeWin64 = Subtarget->isCallingConvWin64(CalleeCC);
3357 bool IsCallerWin64 = Subtarget->isCallingConvWin64(CallerCC);
3359 if (DAG.getTarget().Options.GuaranteedTailCallOpt) {
3360 if (IsTailCallConvention(CalleeCC) && CCMatch)
3365 // Look for obvious safe cases to perform tail call optimization that do not
3366 // require ABI changes. This is what gcc calls sibcall.
3368 // Can't do sibcall if stack needs to be dynamically re-aligned. PEI needs to
3369 // emit a special epilogue.
3370 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
3371 DAG.getSubtarget().getRegisterInfo());
3372 if (RegInfo->needsStackRealignment(MF))
3375 // Also avoid sibcall optimization if either caller or callee uses struct
3376 // return semantics.
3377 if (isCalleeStructRet || isCallerStructRet)
3380 // An stdcall/thiscall caller is expected to clean up its arguments; the
3381 // callee isn't going to do that.
3382 // FIXME: this is more restrictive than needed. We could produce a tailcall
3383 // when the stack adjustment matches. For example, with a thiscall that takes
3384 // only one argument.
3385 if (!CCMatch && (CallerCC == CallingConv::X86_StdCall ||
3386 CallerCC == CallingConv::X86_ThisCall))
3389 // Do not sibcall optimize vararg calls unless all arguments are passed via
3391 if (isVarArg && !Outs.empty()) {
3393 // Optimizing for varargs on Win64 is unlikely to be safe without
3394 // additional testing.
3395 if (IsCalleeWin64 || IsCallerWin64)
3398 SmallVector<CCValAssign, 16> ArgLocs;
3399 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(), ArgLocs,
3402 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
3403 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i)
3404 if (!ArgLocs[i].isRegLoc())
3408 // If the call result is in ST0 / ST1, it needs to be popped off the x87
3409 // stack. Therefore, if it's not used by the call it is not safe to optimize
3410 // this into a sibcall.
3411 bool Unused = false;
3412 for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
3419 SmallVector<CCValAssign, 16> RVLocs;
3420 CCState CCInfo(CalleeCC, false, DAG.getMachineFunction(), RVLocs,
3422 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
3423 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
3424 CCValAssign &VA = RVLocs[i];
3425 if (VA.getLocReg() == X86::FP0 || VA.getLocReg() == X86::FP1)
3430 // If the calling conventions do not match, then we'd better make sure the
3431 // results are returned in the same way as what the caller expects.
3433 SmallVector<CCValAssign, 16> RVLocs1;
3434 CCState CCInfo1(CalleeCC, false, DAG.getMachineFunction(), RVLocs1,
3436 CCInfo1.AnalyzeCallResult(Ins, RetCC_X86);
3438 SmallVector<CCValAssign, 16> RVLocs2;
3439 CCState CCInfo2(CallerCC, false, DAG.getMachineFunction(), RVLocs2,
3441 CCInfo2.AnalyzeCallResult(Ins, RetCC_X86);
3443 if (RVLocs1.size() != RVLocs2.size())
3445 for (unsigned i = 0, e = RVLocs1.size(); i != e; ++i) {
3446 if (RVLocs1[i].isRegLoc() != RVLocs2[i].isRegLoc())
3448 if (RVLocs1[i].getLocInfo() != RVLocs2[i].getLocInfo())
3450 if (RVLocs1[i].isRegLoc()) {
3451 if (RVLocs1[i].getLocReg() != RVLocs2[i].getLocReg())
3454 if (RVLocs1[i].getLocMemOffset() != RVLocs2[i].getLocMemOffset())
3460 // If the callee takes no arguments then go on to check the results of the
3462 if (!Outs.empty()) {
3463 // Check if stack adjustment is needed. For now, do not do this if any
3464 // argument is passed on the stack.
3465 SmallVector<CCValAssign, 16> ArgLocs;
3466 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(), ArgLocs,
3469 // Allocate shadow area for Win64
3471 CCInfo.AllocateStack(32, 8);
3473 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
3474 if (CCInfo.getNextStackOffset()) {
3475 MachineFunction &MF = DAG.getMachineFunction();
3476 if (MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn())
3479 // Check if the arguments are already laid out in the right way as
3480 // the caller's fixed stack objects.
3481 MachineFrameInfo *MFI = MF.getFrameInfo();
3482 const MachineRegisterInfo *MRI = &MF.getRegInfo();
3483 const X86InstrInfo *TII =
3484 static_cast<const X86InstrInfo *>(DAG.getSubtarget().getInstrInfo());
3485 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3486 CCValAssign &VA = ArgLocs[i];
3487 SDValue Arg = OutVals[i];
3488 ISD::ArgFlagsTy Flags = Outs[i].Flags;
3489 if (VA.getLocInfo() == CCValAssign::Indirect)
3491 if (!VA.isRegLoc()) {
3492 if (!MatchingStackOffset(Arg, VA.getLocMemOffset(), Flags,
3499 // If the tailcall address may be in a register, then make sure it's
3500 // possible to register allocate for it. In 32-bit, the call address can
3501 // only target EAX, EDX, or ECX since the tail call must be scheduled after
3502 // callee-saved registers are restored. These happen to be the same
3503 // registers used to pass 'inreg' arguments so watch out for those.
3504 if (!Subtarget->is64Bit() &&
3505 ((!isa<GlobalAddressSDNode>(Callee) &&
3506 !isa<ExternalSymbolSDNode>(Callee)) ||
3507 DAG.getTarget().getRelocationModel() == Reloc::PIC_)) {
3508 unsigned NumInRegs = 0;
3509 // In PIC we need an extra register to formulate the address computation
3511 unsigned MaxInRegs =
3512 (DAG.getTarget().getRelocationModel() == Reloc::PIC_) ? 2 : 3;
3514 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3515 CCValAssign &VA = ArgLocs[i];
3518 unsigned Reg = VA.getLocReg();
3521 case X86::EAX: case X86::EDX: case X86::ECX:
3522 if (++NumInRegs == MaxInRegs)
3534 X86TargetLowering::createFastISel(FunctionLoweringInfo &funcInfo,
3535 const TargetLibraryInfo *libInfo) const {
3536 return X86::createFastISel(funcInfo, libInfo);
3539 //===----------------------------------------------------------------------===//
3540 // Other Lowering Hooks
3541 //===----------------------------------------------------------------------===//
3543 static bool MayFoldLoad(SDValue Op) {
3544 return Op.hasOneUse() && ISD::isNormalLoad(Op.getNode());
3547 static bool MayFoldIntoStore(SDValue Op) {
3548 return Op.hasOneUse() && ISD::isNormalStore(*Op.getNode()->use_begin());
3551 static bool isTargetShuffle(unsigned Opcode) {
3553 default: return false;
3554 case X86ISD::BLENDI:
3555 case X86ISD::PSHUFB:
3556 case X86ISD::PSHUFD:
3557 case X86ISD::PSHUFHW:
3558 case X86ISD::PSHUFLW:
3560 case X86ISD::PALIGNR:
3561 case X86ISD::MOVLHPS:
3562 case X86ISD::MOVLHPD:
3563 case X86ISD::MOVHLPS:
3564 case X86ISD::MOVLPS:
3565 case X86ISD::MOVLPD:
3566 case X86ISD::MOVSHDUP:
3567 case X86ISD::MOVSLDUP:
3568 case X86ISD::MOVDDUP:
3571 case X86ISD::UNPCKL:
3572 case X86ISD::UNPCKH:
3573 case X86ISD::VPERMILPI:
3574 case X86ISD::VPERM2X128:
3575 case X86ISD::VPERMI:
3580 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3581 SDValue V1, SelectionDAG &DAG) {
3583 default: llvm_unreachable("Unknown x86 shuffle node");
3584 case X86ISD::MOVSHDUP:
3585 case X86ISD::MOVSLDUP:
3586 case X86ISD::MOVDDUP:
3587 return DAG.getNode(Opc, dl, VT, V1);
3591 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3592 SDValue V1, unsigned TargetMask,
3593 SelectionDAG &DAG) {
3595 default: llvm_unreachable("Unknown x86 shuffle node");
3596 case X86ISD::PSHUFD:
3597 case X86ISD::PSHUFHW:
3598 case X86ISD::PSHUFLW:
3599 case X86ISD::VPERMILPI:
3600 case X86ISD::VPERMI:
3601 return DAG.getNode(Opc, dl, VT, V1, DAG.getConstant(TargetMask, MVT::i8));
3605 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3606 SDValue V1, SDValue V2, unsigned TargetMask,
3607 SelectionDAG &DAG) {
3609 default: llvm_unreachable("Unknown x86 shuffle node");
3610 case X86ISD::PALIGNR:
3611 case X86ISD::VALIGN:
3613 case X86ISD::VPERM2X128:
3614 return DAG.getNode(Opc, dl, VT, V1, V2,
3615 DAG.getConstant(TargetMask, MVT::i8));
3619 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3620 SDValue V1, SDValue V2, SelectionDAG &DAG) {
3622 default: llvm_unreachable("Unknown x86 shuffle node");
3623 case X86ISD::MOVLHPS:
3624 case X86ISD::MOVLHPD:
3625 case X86ISD::MOVHLPS:
3626 case X86ISD::MOVLPS:
3627 case X86ISD::MOVLPD:
3630 case X86ISD::UNPCKL:
3631 case X86ISD::UNPCKH:
3632 return DAG.getNode(Opc, dl, VT, V1, V2);
3636 SDValue X86TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) const {
3637 MachineFunction &MF = DAG.getMachineFunction();
3638 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
3639 DAG.getSubtarget().getRegisterInfo());
3640 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
3641 int ReturnAddrIndex = FuncInfo->getRAIndex();
3643 if (ReturnAddrIndex == 0) {
3644 // Set up a frame object for the return address.
3645 unsigned SlotSize = RegInfo->getSlotSize();
3646 ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(SlotSize,
3649 FuncInfo->setRAIndex(ReturnAddrIndex);
3652 return DAG.getFrameIndex(ReturnAddrIndex, getPointerTy());
3655 bool X86::isOffsetSuitableForCodeModel(int64_t Offset, CodeModel::Model M,
3656 bool hasSymbolicDisplacement) {
3657 // Offset should fit into 32 bit immediate field.
3658 if (!isInt<32>(Offset))
3661 // If we don't have a symbolic displacement - we don't have any extra
3663 if (!hasSymbolicDisplacement)
3666 // FIXME: Some tweaks might be needed for medium code model.
3667 if (M != CodeModel::Small && M != CodeModel::Kernel)
3670 // For small code model we assume that latest object is 16MB before end of 31
3671 // bits boundary. We may also accept pretty large negative constants knowing
3672 // that all objects are in the positive half of address space.
3673 if (M == CodeModel::Small && Offset < 16*1024*1024)
3676 // For kernel code model we know that all object resist in the negative half
3677 // of 32bits address space. We may not accept negative offsets, since they may
3678 // be just off and we may accept pretty large positive ones.
3679 if (M == CodeModel::Kernel && Offset > 0)
3685 /// isCalleePop - Determines whether the callee is required to pop its
3686 /// own arguments. Callee pop is necessary to support tail calls.
3687 bool X86::isCalleePop(CallingConv::ID CallingConv,
3688 bool is64Bit, bool IsVarArg, bool TailCallOpt) {
3689 switch (CallingConv) {
3692 case CallingConv::X86_StdCall:
3693 case CallingConv::X86_FastCall:
3694 case CallingConv::X86_ThisCall:
3696 case CallingConv::Fast:
3697 case CallingConv::GHC:
3698 case CallingConv::HiPE:
3705 /// \brief Return true if the condition is an unsigned comparison operation.
3706 static bool isX86CCUnsigned(unsigned X86CC) {
3708 default: llvm_unreachable("Invalid integer condition!");
3709 case X86::COND_E: return true;
3710 case X86::COND_G: return false;
3711 case X86::COND_GE: return false;
3712 case X86::COND_L: return false;
3713 case X86::COND_LE: return false;
3714 case X86::COND_NE: return true;
3715 case X86::COND_B: return true;
3716 case X86::COND_A: return true;
3717 case X86::COND_BE: return true;
3718 case X86::COND_AE: return true;
3720 llvm_unreachable("covered switch fell through?!");
3723 /// TranslateX86CC - do a one to one translation of a ISD::CondCode to the X86
3724 /// specific condition code, returning the condition code and the LHS/RHS of the
3725 /// comparison to make.
3726 static unsigned TranslateX86CC(ISD::CondCode SetCCOpcode, bool isFP,
3727 SDValue &LHS, SDValue &RHS, SelectionDAG &DAG) {
3729 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
3730 if (SetCCOpcode == ISD::SETGT && RHSC->isAllOnesValue()) {
3731 // X > -1 -> X == 0, jump !sign.
3732 RHS = DAG.getConstant(0, RHS.getValueType());
3733 return X86::COND_NS;
3735 if (SetCCOpcode == ISD::SETLT && RHSC->isNullValue()) {
3736 // X < 0 -> X == 0, jump on sign.
3739 if (SetCCOpcode == ISD::SETLT && RHSC->getZExtValue() == 1) {
3741 RHS = DAG.getConstant(0, RHS.getValueType());
3742 return X86::COND_LE;
3746 switch (SetCCOpcode) {
3747 default: llvm_unreachable("Invalid integer condition!");
3748 case ISD::SETEQ: return X86::COND_E;
3749 case ISD::SETGT: return X86::COND_G;
3750 case ISD::SETGE: return X86::COND_GE;
3751 case ISD::SETLT: return X86::COND_L;
3752 case ISD::SETLE: return X86::COND_LE;
3753 case ISD::SETNE: return X86::COND_NE;
3754 case ISD::SETULT: return X86::COND_B;
3755 case ISD::SETUGT: return X86::COND_A;
3756 case ISD::SETULE: return X86::COND_BE;
3757 case ISD::SETUGE: return X86::COND_AE;
3761 // First determine if it is required or is profitable to flip the operands.
3763 // If LHS is a foldable load, but RHS is not, flip the condition.
3764 if (ISD::isNON_EXTLoad(LHS.getNode()) &&
3765 !ISD::isNON_EXTLoad(RHS.getNode())) {
3766 SetCCOpcode = getSetCCSwappedOperands(SetCCOpcode);
3767 std::swap(LHS, RHS);
3770 switch (SetCCOpcode) {
3776 std::swap(LHS, RHS);
3780 // On a floating point condition, the flags are set as follows:
3782 // 0 | 0 | 0 | X > Y
3783 // 0 | 0 | 1 | X < Y
3784 // 1 | 0 | 0 | X == Y
3785 // 1 | 1 | 1 | unordered
3786 switch (SetCCOpcode) {
3787 default: llvm_unreachable("Condcode should be pre-legalized away");
3789 case ISD::SETEQ: return X86::COND_E;
3790 case ISD::SETOLT: // flipped
3792 case ISD::SETGT: return X86::COND_A;
3793 case ISD::SETOLE: // flipped
3795 case ISD::SETGE: return X86::COND_AE;
3796 case ISD::SETUGT: // flipped
3798 case ISD::SETLT: return X86::COND_B;
3799 case ISD::SETUGE: // flipped
3801 case ISD::SETLE: return X86::COND_BE;
3803 case ISD::SETNE: return X86::COND_NE;
3804 case ISD::SETUO: return X86::COND_P;
3805 case ISD::SETO: return X86::COND_NP;
3807 case ISD::SETUNE: return X86::COND_INVALID;
3811 /// hasFPCMov - is there a floating point cmov for the specific X86 condition
3812 /// code. Current x86 isa includes the following FP cmov instructions:
3813 /// fcmovb, fcomvbe, fcomve, fcmovu, fcmovae, fcmova, fcmovne, fcmovnu.
3814 static bool hasFPCMov(unsigned X86CC) {
3830 /// isFPImmLegal - Returns true if the target can instruction select the
3831 /// specified FP immediate natively. If false, the legalizer will
3832 /// materialize the FP immediate as a load from a constant pool.
3833 bool X86TargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
3834 for (unsigned i = 0, e = LegalFPImmediates.size(); i != e; ++i) {
3835 if (Imm.bitwiseIsEqual(LegalFPImmediates[i]))
3841 /// \brief Returns true if it is beneficial to convert a load of a constant
3842 /// to just the constant itself.
3843 bool X86TargetLowering::shouldConvertConstantLoadToIntImm(const APInt &Imm,
3845 assert(Ty->isIntegerTy());
3847 unsigned BitSize = Ty->getPrimitiveSizeInBits();
3848 if (BitSize == 0 || BitSize > 64)
3853 /// isUndefOrInRange - Return true if Val is undef or if its value falls within
3854 /// the specified range (L, H].
3855 static bool isUndefOrInRange(int Val, int Low, int Hi) {
3856 return (Val < 0) || (Val >= Low && Val < Hi);
3859 /// isUndefOrEqual - Val is either less than zero (undef) or equal to the
3860 /// specified value.
3861 static bool isUndefOrEqual(int Val, int CmpVal) {
3862 return (Val < 0 || Val == CmpVal);
3865 /// isSequentialOrUndefInRange - Return true if every element in Mask, beginning
3866 /// from position Pos and ending in Pos+Size, falls within the specified
3867 /// sequential range (L, L+Pos]. or is undef.
3868 static bool isSequentialOrUndefInRange(ArrayRef<int> Mask,
3869 unsigned Pos, unsigned Size, int Low) {
3870 for (unsigned i = Pos, e = Pos+Size; i != e; ++i, ++Low)
3871 if (!isUndefOrEqual(Mask[i], Low))
3876 /// isPSHUFDMask - Return true if the node specifies a shuffle of elements that
3877 /// is suitable for input to PSHUFD. That is, it doesn't reference the other
3878 /// operand - by default will match for first operand.
3879 static bool isPSHUFDMask(ArrayRef<int> Mask, MVT VT,
3880 bool TestSecondOperand = false) {
3881 if (VT != MVT::v4f32 && VT != MVT::v4i32 &&
3882 VT != MVT::v2f64 && VT != MVT::v2i64)
3885 unsigned NumElems = VT.getVectorNumElements();
3886 unsigned Lo = TestSecondOperand ? NumElems : 0;
3887 unsigned Hi = Lo + NumElems;
3889 for (unsigned i = 0; i < NumElems; ++i)
3890 if (!isUndefOrInRange(Mask[i], (int)Lo, (int)Hi))
3896 /// isPSHUFHWMask - Return true if the node specifies a shuffle of elements that
3897 /// is suitable for input to PSHUFHW.
3898 static bool isPSHUFHWMask(ArrayRef<int> Mask, MVT VT, bool HasInt256) {
3899 if (VT != MVT::v8i16 && (!HasInt256 || VT != MVT::v16i16))
3902 // Lower quadword copied in order or undef.
3903 if (!isSequentialOrUndefInRange(Mask, 0, 4, 0))
3906 // Upper quadword shuffled.
3907 for (unsigned i = 4; i != 8; ++i)
3908 if (!isUndefOrInRange(Mask[i], 4, 8))
3911 if (VT == MVT::v16i16) {
3912 // Lower quadword copied in order or undef.
3913 if (!isSequentialOrUndefInRange(Mask, 8, 4, 8))
3916 // Upper quadword shuffled.
3917 for (unsigned i = 12; i != 16; ++i)
3918 if (!isUndefOrInRange(Mask[i], 12, 16))
3925 /// isPSHUFLWMask - Return true if the node specifies a shuffle of elements that
3926 /// is suitable for input to PSHUFLW.
3927 static bool isPSHUFLWMask(ArrayRef<int> Mask, MVT VT, bool HasInt256) {
3928 if (VT != MVT::v8i16 && (!HasInt256 || VT != MVT::v16i16))
3931 // Upper quadword copied in order.
3932 if (!isSequentialOrUndefInRange(Mask, 4, 4, 4))
3935 // Lower quadword shuffled.
3936 for (unsigned i = 0; i != 4; ++i)
3937 if (!isUndefOrInRange(Mask[i], 0, 4))
3940 if (VT == MVT::v16i16) {
3941 // Upper quadword copied in order.
3942 if (!isSequentialOrUndefInRange(Mask, 12, 4, 12))
3945 // Lower quadword shuffled.
3946 for (unsigned i = 8; i != 12; ++i)
3947 if (!isUndefOrInRange(Mask[i], 8, 12))
3954 /// \brief Return true if the mask specifies a shuffle of elements that is
3955 /// suitable for input to intralane (palignr) or interlane (valign) vector
3957 static bool isAlignrMask(ArrayRef<int> Mask, MVT VT, bool InterLane) {
3958 unsigned NumElts = VT.getVectorNumElements();
3959 unsigned NumLanes = InterLane ? 1: VT.getSizeInBits()/128;
3960 unsigned NumLaneElts = NumElts/NumLanes;
3962 // Do not handle 64-bit element shuffles with palignr.
3963 if (NumLaneElts == 2)
3966 for (unsigned l = 0; l != NumElts; l+=NumLaneElts) {
3968 for (i = 0; i != NumLaneElts; ++i) {
3973 // Lane is all undef, go to next lane
3974 if (i == NumLaneElts)
3977 int Start = Mask[i+l];
3979 // Make sure its in this lane in one of the sources
3980 if (!isUndefOrInRange(Start, l, l+NumLaneElts) &&
3981 !isUndefOrInRange(Start, l+NumElts, l+NumElts+NumLaneElts))
3984 // If not lane 0, then we must match lane 0
3985 if (l != 0 && Mask[i] >= 0 && !isUndefOrEqual(Start, Mask[i]+l))
3988 // Correct second source to be contiguous with first source
3989 if (Start >= (int)NumElts)
3990 Start -= NumElts - NumLaneElts;
3992 // Make sure we're shifting in the right direction.
3993 if (Start <= (int)(i+l))
3998 // Check the rest of the elements to see if they are consecutive.
3999 for (++i; i != NumLaneElts; ++i) {
4000 int Idx = Mask[i+l];
4002 // Make sure its in this lane
4003 if (!isUndefOrInRange(Idx, l, l+NumLaneElts) &&
4004 !isUndefOrInRange(Idx, l+NumElts, l+NumElts+NumLaneElts))
4007 // If not lane 0, then we must match lane 0
4008 if (l != 0 && Mask[i] >= 0 && !isUndefOrEqual(Idx, Mask[i]+l))
4011 if (Idx >= (int)NumElts)
4012 Idx -= NumElts - NumLaneElts;
4014 if (!isUndefOrEqual(Idx, Start+i))
4023 /// \brief Return true if the node specifies a shuffle of elements that is
4024 /// suitable for input to PALIGNR.
4025 static bool isPALIGNRMask(ArrayRef<int> Mask, MVT VT,
4026 const X86Subtarget *Subtarget) {
4027 if ((VT.is128BitVector() && !Subtarget->hasSSSE3()) ||
4028 (VT.is256BitVector() && !Subtarget->hasInt256()) ||
4029 VT.is512BitVector())
4030 // FIXME: Add AVX512BW.
4033 return isAlignrMask(Mask, VT, false);
4036 /// \brief Return true if the node specifies a shuffle of elements that is
4037 /// suitable for input to VALIGN.
4038 static bool isVALIGNMask(ArrayRef<int> Mask, MVT VT,
4039 const X86Subtarget *Subtarget) {
4040 // FIXME: Add AVX512VL.
4041 if (!VT.is512BitVector() || !Subtarget->hasAVX512())
4043 return isAlignrMask(Mask, VT, true);
4046 /// CommuteVectorShuffleMask - Change values in a shuffle permute mask assuming
4047 /// the two vector operands have swapped position.
4048 static void CommuteVectorShuffleMask(SmallVectorImpl<int> &Mask,
4049 unsigned NumElems) {
4050 for (unsigned i = 0; i != NumElems; ++i) {
4054 else if (idx < (int)NumElems)
4055 Mask[i] = idx + NumElems;
4057 Mask[i] = idx - NumElems;
4061 /// isSHUFPMask - Return true if the specified VECTOR_SHUFFLE operand
4062 /// specifies a shuffle of elements that is suitable for input to 128/256-bit
4063 /// SHUFPS and SHUFPD. If Commuted is true, then it checks for sources to be
4064 /// reverse of what x86 shuffles want.
4065 static bool isSHUFPMask(ArrayRef<int> Mask, MVT VT, bool Commuted = false) {
4067 unsigned NumElems = VT.getVectorNumElements();
4068 unsigned NumLanes = VT.getSizeInBits()/128;
4069 unsigned NumLaneElems = NumElems/NumLanes;
4071 if (NumLaneElems != 2 && NumLaneElems != 4)
4074 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
4075 bool symetricMaskRequired =
4076 (VT.getSizeInBits() >= 256) && (EltSize == 32);
4078 // VSHUFPSY divides the resulting vector into 4 chunks.
4079 // The sources are also splitted into 4 chunks, and each destination
4080 // chunk must come from a different source chunk.
4082 // SRC1 => X7 X6 X5 X4 X3 X2 X1 X0
4083 // SRC2 => Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y9
4085 // DST => Y7..Y4, Y7..Y4, X7..X4, X7..X4,
4086 // Y3..Y0, Y3..Y0, X3..X0, X3..X0
4088 // VSHUFPDY divides the resulting vector into 4 chunks.
4089 // The sources are also splitted into 4 chunks, and each destination
4090 // chunk must come from a different source chunk.
4092 // SRC1 => X3 X2 X1 X0
4093 // SRC2 => Y3 Y2 Y1 Y0
4095 // DST => Y3..Y2, X3..X2, Y1..Y0, X1..X0
4097 SmallVector<int, 4> MaskVal(NumLaneElems, -1);
4098 unsigned HalfLaneElems = NumLaneElems/2;
4099 for (unsigned l = 0; l != NumElems; l += NumLaneElems) {
4100 for (unsigned i = 0; i != NumLaneElems; ++i) {
4101 int Idx = Mask[i+l];
4102 unsigned RngStart = l + ((Commuted == (i<HalfLaneElems)) ? NumElems : 0);
4103 if (!isUndefOrInRange(Idx, RngStart, RngStart+NumLaneElems))
4105 // For VSHUFPSY, the mask of the second half must be the same as the
4106 // first but with the appropriate offsets. This works in the same way as
4107 // VPERMILPS works with masks.
4108 if (!symetricMaskRequired || Idx < 0)
4110 if (MaskVal[i] < 0) {
4111 MaskVal[i] = Idx - l;
4114 if ((signed)(Idx - l) != MaskVal[i])
4122 /// isMOVHLPSMask - Return true if the specified VECTOR_SHUFFLE operand
4123 /// specifies a shuffle of elements that is suitable for input to MOVHLPS.
4124 static bool isMOVHLPSMask(ArrayRef<int> Mask, MVT VT) {
4125 if (!VT.is128BitVector())
4128 unsigned NumElems = VT.getVectorNumElements();
4133 // Expect bit0 == 6, bit1 == 7, bit2 == 2, bit3 == 3
4134 return isUndefOrEqual(Mask[0], 6) &&
4135 isUndefOrEqual(Mask[1], 7) &&
4136 isUndefOrEqual(Mask[2], 2) &&
4137 isUndefOrEqual(Mask[3], 3);
4140 /// isMOVHLPS_v_undef_Mask - Special case of isMOVHLPSMask for canonical form
4141 /// of vector_shuffle v, v, <2, 3, 2, 3>, i.e. vector_shuffle v, undef,
4143 static bool isMOVHLPS_v_undef_Mask(ArrayRef<int> Mask, MVT VT) {
4144 if (!VT.is128BitVector())
4147 unsigned NumElems = VT.getVectorNumElements();
4152 return isUndefOrEqual(Mask[0], 2) &&
4153 isUndefOrEqual(Mask[1], 3) &&
4154 isUndefOrEqual(Mask[2], 2) &&
4155 isUndefOrEqual(Mask[3], 3);
4158 /// isMOVLPMask - Return true if the specified VECTOR_SHUFFLE operand
4159 /// specifies a shuffle of elements that is suitable for input to MOVLP{S|D}.
4160 static bool isMOVLPMask(ArrayRef<int> Mask, MVT VT) {
4161 if (!VT.is128BitVector())
4164 unsigned NumElems = VT.getVectorNumElements();
4166 if (NumElems != 2 && NumElems != 4)
4169 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
4170 if (!isUndefOrEqual(Mask[i], i + NumElems))
4173 for (unsigned i = NumElems/2, e = NumElems; i != e; ++i)
4174 if (!isUndefOrEqual(Mask[i], i))
4180 /// isMOVLHPSMask - Return true if the specified VECTOR_SHUFFLE operand
4181 /// specifies a shuffle of elements that is suitable for input to MOVLHPS.
4182 static bool isMOVLHPSMask(ArrayRef<int> Mask, MVT VT) {
4183 if (!VT.is128BitVector())
4186 unsigned NumElems = VT.getVectorNumElements();
4188 if (NumElems != 2 && NumElems != 4)
4191 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
4192 if (!isUndefOrEqual(Mask[i], i))
4195 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
4196 if (!isUndefOrEqual(Mask[i + e], i + NumElems))
4202 /// isINSERTPSMask - Return true if the specified VECTOR_SHUFFLE operand
4203 /// specifies a shuffle of elements that is suitable for input to INSERTPS.
4204 /// i. e: If all but one element come from the same vector.
4205 static bool isINSERTPSMask(ArrayRef<int> Mask, MVT VT) {
4206 // TODO: Deal with AVX's VINSERTPS
4207 if (!VT.is128BitVector() || (VT != MVT::v4f32 && VT != MVT::v4i32))
4210 unsigned CorrectPosV1 = 0;
4211 unsigned CorrectPosV2 = 0;
4212 for (int i = 0, e = (int)VT.getVectorNumElements(); i != e; ++i) {
4213 if (Mask[i] == -1) {
4221 else if (Mask[i] == i + 4)
4225 if (CorrectPosV1 == 3 || CorrectPosV2 == 3)
4226 // We have 3 elements (undefs count as elements from any vector) from one
4227 // vector, and one from another.
4234 // Some special combinations that can be optimized.
4237 SDValue Compact8x32ShuffleNode(ShuffleVectorSDNode *SVOp,
4238 SelectionDAG &DAG) {
4239 MVT VT = SVOp->getSimpleValueType(0);
4242 if (VT != MVT::v8i32 && VT != MVT::v8f32)
4245 ArrayRef<int> Mask = SVOp->getMask();
4247 // These are the special masks that may be optimized.
4248 static const int MaskToOptimizeEven[] = {0, 8, 2, 10, 4, 12, 6, 14};
4249 static const int MaskToOptimizeOdd[] = {1, 9, 3, 11, 5, 13, 7, 15};
4250 bool MatchEvenMask = true;
4251 bool MatchOddMask = true;
4252 for (int i=0; i<8; ++i) {
4253 if (!isUndefOrEqual(Mask[i], MaskToOptimizeEven[i]))
4254 MatchEvenMask = false;
4255 if (!isUndefOrEqual(Mask[i], MaskToOptimizeOdd[i]))
4256 MatchOddMask = false;
4259 if (!MatchEvenMask && !MatchOddMask)
4262 SDValue UndefNode = DAG.getNode(ISD::UNDEF, dl, VT);
4264 SDValue Op0 = SVOp->getOperand(0);
4265 SDValue Op1 = SVOp->getOperand(1);
4267 if (MatchEvenMask) {
4268 // Shift the second operand right to 32 bits.
4269 static const int ShiftRightMask[] = {-1, 0, -1, 2, -1, 4, -1, 6 };
4270 Op1 = DAG.getVectorShuffle(VT, dl, Op1, UndefNode, ShiftRightMask);
4272 // Shift the first operand left to 32 bits.
4273 static const int ShiftLeftMask[] = {1, -1, 3, -1, 5, -1, 7, -1 };
4274 Op0 = DAG.getVectorShuffle(VT, dl, Op0, UndefNode, ShiftLeftMask);
4276 static const int BlendMask[] = {0, 9, 2, 11, 4, 13, 6, 15};
4277 return DAG.getVectorShuffle(VT, dl, Op0, Op1, BlendMask);
4280 /// isUNPCKLMask - Return true if the specified VECTOR_SHUFFLE operand
4281 /// specifies a shuffle of elements that is suitable for input to UNPCKL.
4282 static bool isUNPCKLMask(ArrayRef<int> Mask, MVT VT,
4283 bool HasInt256, bool V2IsSplat = false) {
4285 assert(VT.getSizeInBits() >= 128 &&
4286 "Unsupported vector type for unpckl");
4288 unsigned NumElts = VT.getVectorNumElements();
4289 if (VT.is256BitVector() && NumElts != 4 && NumElts != 8 &&
4290 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
4293 assert((!VT.is512BitVector() || VT.getScalarType().getSizeInBits() >= 32) &&
4294 "Unsupported vector type for unpckh");
4296 // AVX defines UNPCK* to operate independently on 128-bit lanes.
4297 unsigned NumLanes = VT.getSizeInBits()/128;
4298 unsigned NumLaneElts = NumElts/NumLanes;
4300 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
4301 for (unsigned i = 0, j = l; i != NumLaneElts; i += 2, ++j) {
4302 int BitI = Mask[l+i];
4303 int BitI1 = Mask[l+i+1];
4304 if (!isUndefOrEqual(BitI, j))
4307 if (!isUndefOrEqual(BitI1, NumElts))
4310 if (!isUndefOrEqual(BitI1, j + NumElts))
4319 /// isUNPCKHMask - Return true if the specified VECTOR_SHUFFLE operand
4320 /// specifies a shuffle of elements that is suitable for input to UNPCKH.
4321 static bool isUNPCKHMask(ArrayRef<int> Mask, MVT VT,
4322 bool HasInt256, bool V2IsSplat = false) {
4323 assert(VT.getSizeInBits() >= 128 &&
4324 "Unsupported vector type for unpckh");
4326 unsigned NumElts = VT.getVectorNumElements();
4327 if (VT.is256BitVector() && NumElts != 4 && NumElts != 8 &&
4328 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
4331 assert((!VT.is512BitVector() || VT.getScalarType().getSizeInBits() >= 32) &&
4332 "Unsupported vector type for unpckh");
4334 // AVX defines UNPCK* to operate independently on 128-bit lanes.
4335 unsigned NumLanes = VT.getSizeInBits()/128;
4336 unsigned NumLaneElts = NumElts/NumLanes;
4338 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
4339 for (unsigned i = 0, j = l+NumLaneElts/2; i != NumLaneElts; i += 2, ++j) {
4340 int BitI = Mask[l+i];
4341 int BitI1 = Mask[l+i+1];
4342 if (!isUndefOrEqual(BitI, j))
4345 if (isUndefOrEqual(BitI1, NumElts))
4348 if (!isUndefOrEqual(BitI1, j+NumElts))
4356 /// isUNPCKL_v_undef_Mask - Special case of isUNPCKLMask for canonical form
4357 /// of vector_shuffle v, v, <0, 4, 1, 5>, i.e. vector_shuffle v, undef,
4359 static bool isUNPCKL_v_undef_Mask(ArrayRef<int> Mask, MVT VT, bool HasInt256) {
4360 unsigned NumElts = VT.getVectorNumElements();
4361 bool Is256BitVec = VT.is256BitVector();
4363 if (VT.is512BitVector())
4365 assert((VT.is128BitVector() || VT.is256BitVector()) &&
4366 "Unsupported vector type for unpckh");
4368 if (Is256BitVec && NumElts != 4 && NumElts != 8 &&
4369 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
4372 // For 256-bit i64/f64, use MOVDDUPY instead, so reject the matching pattern
4373 // FIXME: Need a better way to get rid of this, there's no latency difference
4374 // between UNPCKLPD and MOVDDUP, the later should always be checked first and
4375 // the former later. We should also remove the "_undef" special mask.
4376 if (NumElts == 4 && Is256BitVec)
4379 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
4380 // independently on 128-bit lanes.
4381 unsigned NumLanes = VT.getSizeInBits()/128;
4382 unsigned NumLaneElts = NumElts/NumLanes;
4384 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
4385 for (unsigned i = 0, j = l; i != NumLaneElts; i += 2, ++j) {
4386 int BitI = Mask[l+i];
4387 int BitI1 = Mask[l+i+1];
4389 if (!isUndefOrEqual(BitI, j))
4391 if (!isUndefOrEqual(BitI1, j))
4399 /// isUNPCKH_v_undef_Mask - Special case of isUNPCKHMask for canonical form
4400 /// of vector_shuffle v, v, <2, 6, 3, 7>, i.e. vector_shuffle v, undef,
4402 static bool isUNPCKH_v_undef_Mask(ArrayRef<int> Mask, MVT VT, bool HasInt256) {
4403 unsigned NumElts = VT.getVectorNumElements();
4405 if (VT.is512BitVector())
4408 assert((VT.is128BitVector() || VT.is256BitVector()) &&
4409 "Unsupported vector type for unpckh");
4411 if (VT.is256BitVector() && NumElts != 4 && NumElts != 8 &&
4412 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
4415 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
4416 // independently on 128-bit lanes.
4417 unsigned NumLanes = VT.getSizeInBits()/128;
4418 unsigned NumLaneElts = NumElts/NumLanes;
4420 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
4421 for (unsigned i = 0, j = l+NumLaneElts/2; i != NumLaneElts; i += 2, ++j) {
4422 int BitI = Mask[l+i];
4423 int BitI1 = Mask[l+i+1];
4424 if (!isUndefOrEqual(BitI, j))
4426 if (!isUndefOrEqual(BitI1, j))
4433 // Match for INSERTI64x4 INSERTF64x4 instructions (src0[0], src1[0]) or
4434 // (src1[0], src0[1]), manipulation with 256-bit sub-vectors
4435 static bool isINSERT64x4Mask(ArrayRef<int> Mask, MVT VT, unsigned int *Imm) {
4436 if (!VT.is512BitVector())
4439 unsigned NumElts = VT.getVectorNumElements();
4440 unsigned HalfSize = NumElts/2;
4441 if (isSequentialOrUndefInRange(Mask, 0, HalfSize, 0)) {
4442 if (isSequentialOrUndefInRange(Mask, HalfSize, HalfSize, NumElts)) {
4447 if (isSequentialOrUndefInRange(Mask, 0, HalfSize, NumElts)) {
4448 if (isSequentialOrUndefInRange(Mask, HalfSize, HalfSize, HalfSize)) {
4456 /// isMOVLMask - Return true if the specified VECTOR_SHUFFLE operand
4457 /// specifies a shuffle of elements that is suitable for input to MOVSS,
4458 /// MOVSD, and MOVD, i.e. setting the lowest element.
4459 static bool isMOVLMask(ArrayRef<int> Mask, EVT VT) {
4460 if (VT.getVectorElementType().getSizeInBits() < 32)
4462 if (!VT.is128BitVector())
4465 unsigned NumElts = VT.getVectorNumElements();
4467 if (!isUndefOrEqual(Mask[0], NumElts))
4470 for (unsigned i = 1; i != NumElts; ++i)
4471 if (!isUndefOrEqual(Mask[i], i))
4477 /// isVPERM2X128Mask - Match 256-bit shuffles where the elements are considered
4478 /// as permutations between 128-bit chunks or halves. As an example: this
4480 /// vector_shuffle <4, 5, 6, 7, 12, 13, 14, 15>
4481 /// The first half comes from the second half of V1 and the second half from the
4482 /// the second half of V2.
4483 static bool isVPERM2X128Mask(ArrayRef<int> Mask, MVT VT, bool HasFp256) {
4484 if (!HasFp256 || !VT.is256BitVector())
4487 // The shuffle result is divided into half A and half B. In total the two
4488 // sources have 4 halves, namely: C, D, E, F. The final values of A and
4489 // B must come from C, D, E or F.
4490 unsigned HalfSize = VT.getVectorNumElements()/2;
4491 bool MatchA = false, MatchB = false;
4493 // Check if A comes from one of C, D, E, F.
4494 for (unsigned Half = 0; Half != 4; ++Half) {
4495 if (isSequentialOrUndefInRange(Mask, 0, HalfSize, Half*HalfSize)) {
4501 // Check if B comes from one of C, D, E, F.
4502 for (unsigned Half = 0; Half != 4; ++Half) {
4503 if (isSequentialOrUndefInRange(Mask, HalfSize, HalfSize, Half*HalfSize)) {
4509 return MatchA && MatchB;
4512 /// getShuffleVPERM2X128Immediate - Return the appropriate immediate to shuffle
4513 /// the specified VECTOR_MASK mask with VPERM2F128/VPERM2I128 instructions.
4514 static unsigned getShuffleVPERM2X128Immediate(ShuffleVectorSDNode *SVOp) {
4515 MVT VT = SVOp->getSimpleValueType(0);
4517 unsigned HalfSize = VT.getVectorNumElements()/2;
4519 unsigned FstHalf = 0, SndHalf = 0;
4520 for (unsigned i = 0; i < HalfSize; ++i) {
4521 if (SVOp->getMaskElt(i) > 0) {
4522 FstHalf = SVOp->getMaskElt(i)/HalfSize;
4526 for (unsigned i = HalfSize; i < HalfSize*2; ++i) {
4527 if (SVOp->getMaskElt(i) > 0) {
4528 SndHalf = SVOp->getMaskElt(i)/HalfSize;
4533 return (FstHalf | (SndHalf << 4));
4536 // Symetric in-lane mask. Each lane has 4 elements (for imm8)
4537 static bool isPermImmMask(ArrayRef<int> Mask, MVT VT, unsigned& Imm8) {
4538 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
4542 unsigned NumElts = VT.getVectorNumElements();
4544 if (VT.is128BitVector() || (VT.is256BitVector() && EltSize == 64)) {
4545 for (unsigned i = 0; i != NumElts; ++i) {
4548 Imm8 |= Mask[i] << (i*2);
4553 unsigned LaneSize = 4;
4554 SmallVector<int, 4> MaskVal(LaneSize, -1);
4556 for (unsigned l = 0; l != NumElts; l += LaneSize) {
4557 for (unsigned i = 0; i != LaneSize; ++i) {
4558 if (!isUndefOrInRange(Mask[i+l], l, l+LaneSize))
4562 if (MaskVal[i] < 0) {
4563 MaskVal[i] = Mask[i+l] - l;
4564 Imm8 |= MaskVal[i] << (i*2);
4567 if (Mask[i+l] != (signed)(MaskVal[i]+l))
4574 /// isVPERMILPMask - Return true if the specified VECTOR_SHUFFLE operand
4575 /// specifies a shuffle of elements that is suitable for input to VPERMILPD*.
4576 /// Note that VPERMIL mask matching is different depending whether theunderlying
4577 /// type is 32 or 64. In the VPERMILPS the high half of the mask should point
4578 /// to the same elements of the low, but to the higher half of the source.
4579 /// In VPERMILPD the two lanes could be shuffled independently of each other
4580 /// with the same restriction that lanes can't be crossed. Also handles PSHUFDY.
4581 static bool isVPERMILPMask(ArrayRef<int> Mask, MVT VT) {
4582 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
4583 if (VT.getSizeInBits() < 256 || EltSize < 32)
4585 bool symetricMaskRequired = (EltSize == 32);
4586 unsigned NumElts = VT.getVectorNumElements();
4588 unsigned NumLanes = VT.getSizeInBits()/128;
4589 unsigned LaneSize = NumElts/NumLanes;
4590 // 2 or 4 elements in one lane
4592 SmallVector<int, 4> ExpectedMaskVal(LaneSize, -1);
4593 for (unsigned l = 0; l != NumElts; l += LaneSize) {
4594 for (unsigned i = 0; i != LaneSize; ++i) {
4595 if (!isUndefOrInRange(Mask[i+l], l, l+LaneSize))
4597 if (symetricMaskRequired) {
4598 if (ExpectedMaskVal[i] < 0 && Mask[i+l] >= 0) {
4599 ExpectedMaskVal[i] = Mask[i+l] - l;
4602 if (!isUndefOrEqual(Mask[i+l], ExpectedMaskVal[i]+l))
4610 /// isCommutedMOVLMask - Returns true if the shuffle mask is except the reverse
4611 /// of what x86 movss want. X86 movs requires the lowest element to be lowest
4612 /// element of vector 2 and the other elements to come from vector 1 in order.
4613 static bool isCommutedMOVLMask(ArrayRef<int> Mask, MVT VT,
4614 bool V2IsSplat = false, bool V2IsUndef = false) {
4615 if (!VT.is128BitVector())
4618 unsigned NumOps = VT.getVectorNumElements();
4619 if (NumOps != 2 && NumOps != 4 && NumOps != 8 && NumOps != 16)
4622 if (!isUndefOrEqual(Mask[0], 0))
4625 for (unsigned i = 1; i != NumOps; ++i)
4626 if (!(isUndefOrEqual(Mask[i], i+NumOps) ||
4627 (V2IsUndef && isUndefOrInRange(Mask[i], NumOps, NumOps*2)) ||
4628 (V2IsSplat && isUndefOrEqual(Mask[i], NumOps))))
4634 /// isMOVSHDUPMask - Return true if the specified VECTOR_SHUFFLE operand
4635 /// specifies a shuffle of elements that is suitable for input to MOVSHDUP.
4636 /// Masks to match: <1, 1, 3, 3> or <1, 1, 3, 3, 5, 5, 7, 7>
4637 static bool isMOVSHDUPMask(ArrayRef<int> Mask, MVT VT,
4638 const X86Subtarget *Subtarget) {
4639 if (!Subtarget->hasSSE3())
4642 unsigned NumElems = VT.getVectorNumElements();
4644 if ((VT.is128BitVector() && NumElems != 4) ||
4645 (VT.is256BitVector() && NumElems != 8) ||
4646 (VT.is512BitVector() && NumElems != 16))
4649 // "i+1" is the value the indexed mask element must have
4650 for (unsigned i = 0; i != NumElems; i += 2)
4651 if (!isUndefOrEqual(Mask[i], i+1) ||
4652 !isUndefOrEqual(Mask[i+1], i+1))
4658 /// isMOVSLDUPMask - Return true if the specified VECTOR_SHUFFLE operand
4659 /// specifies a shuffle of elements that is suitable for input to MOVSLDUP.
4660 /// Masks to match: <0, 0, 2, 2> or <0, 0, 2, 2, 4, 4, 6, 6>
4661 static bool isMOVSLDUPMask(ArrayRef<int> Mask, MVT VT,
4662 const X86Subtarget *Subtarget) {
4663 if (!Subtarget->hasSSE3())
4666 unsigned NumElems = VT.getVectorNumElements();
4668 if ((VT.is128BitVector() && NumElems != 4) ||
4669 (VT.is256BitVector() && NumElems != 8) ||
4670 (VT.is512BitVector() && NumElems != 16))
4673 // "i" is the value the indexed mask element must have
4674 for (unsigned i = 0; i != NumElems; i += 2)
4675 if (!isUndefOrEqual(Mask[i], i) ||
4676 !isUndefOrEqual(Mask[i+1], i))
4682 /// isMOVDDUPYMask - Return true if the specified VECTOR_SHUFFLE operand
4683 /// specifies a shuffle of elements that is suitable for input to 256-bit
4684 /// version of MOVDDUP.
4685 static bool isMOVDDUPYMask(ArrayRef<int> Mask, MVT VT, bool HasFp256) {
4686 if (!HasFp256 || !VT.is256BitVector())
4689 unsigned NumElts = VT.getVectorNumElements();
4693 for (unsigned i = 0; i != NumElts/2; ++i)
4694 if (!isUndefOrEqual(Mask[i], 0))
4696 for (unsigned i = NumElts/2; i != NumElts; ++i)
4697 if (!isUndefOrEqual(Mask[i], NumElts/2))
4702 /// isMOVDDUPMask - Return true if the specified VECTOR_SHUFFLE operand
4703 /// specifies a shuffle of elements that is suitable for input to 128-bit
4704 /// version of MOVDDUP.
4705 static bool isMOVDDUPMask(ArrayRef<int> Mask, MVT VT) {
4706 if (!VT.is128BitVector())
4709 unsigned e = VT.getVectorNumElements() / 2;
4710 for (unsigned i = 0; i != e; ++i)
4711 if (!isUndefOrEqual(Mask[i], i))
4713 for (unsigned i = 0; i != e; ++i)
4714 if (!isUndefOrEqual(Mask[e+i], i))
4719 /// isVEXTRACTIndex - Return true if the specified
4720 /// EXTRACT_SUBVECTOR operand specifies a vector extract that is
4721 /// suitable for instruction that extract 128 or 256 bit vectors
4722 static bool isVEXTRACTIndex(SDNode *N, unsigned vecWidth) {
4723 assert((vecWidth == 128 || vecWidth == 256) && "Unexpected vector width");
4724 if (!isa<ConstantSDNode>(N->getOperand(1).getNode()))
4727 // The index should be aligned on a vecWidth-bit boundary.
4729 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
4731 MVT VT = N->getSimpleValueType(0);
4732 unsigned ElSize = VT.getVectorElementType().getSizeInBits();
4733 bool Result = (Index * ElSize) % vecWidth == 0;
4738 /// isVINSERTIndex - Return true if the specified INSERT_SUBVECTOR
4739 /// operand specifies a subvector insert that is suitable for input to
4740 /// insertion of 128 or 256-bit subvectors
4741 static bool isVINSERTIndex(SDNode *N, unsigned vecWidth) {
4742 assert((vecWidth == 128 || vecWidth == 256) && "Unexpected vector width");
4743 if (!isa<ConstantSDNode>(N->getOperand(2).getNode()))
4745 // The index should be aligned on a vecWidth-bit boundary.
4747 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
4749 MVT VT = N->getSimpleValueType(0);
4750 unsigned ElSize = VT.getVectorElementType().getSizeInBits();
4751 bool Result = (Index * ElSize) % vecWidth == 0;
4756 bool X86::isVINSERT128Index(SDNode *N) {
4757 return isVINSERTIndex(N, 128);
4760 bool X86::isVINSERT256Index(SDNode *N) {
4761 return isVINSERTIndex(N, 256);
4764 bool X86::isVEXTRACT128Index(SDNode *N) {
4765 return isVEXTRACTIndex(N, 128);
4768 bool X86::isVEXTRACT256Index(SDNode *N) {
4769 return isVEXTRACTIndex(N, 256);
4772 /// getShuffleSHUFImmediate - Return the appropriate immediate to shuffle
4773 /// the specified VECTOR_SHUFFLE mask with PSHUF* and SHUFP* instructions.
4774 /// Handles 128-bit and 256-bit.
4775 static unsigned getShuffleSHUFImmediate(ShuffleVectorSDNode *N) {
4776 MVT VT = N->getSimpleValueType(0);
4778 assert((VT.getSizeInBits() >= 128) &&
4779 "Unsupported vector type for PSHUF/SHUFP");
4781 // Handle 128 and 256-bit vector lengths. AVX defines PSHUF/SHUFP to operate
4782 // independently on 128-bit lanes.
4783 unsigned NumElts = VT.getVectorNumElements();
4784 unsigned NumLanes = VT.getSizeInBits()/128;
4785 unsigned NumLaneElts = NumElts/NumLanes;
4787 assert((NumLaneElts == 2 || NumLaneElts == 4 || NumLaneElts == 8) &&
4788 "Only supports 2, 4 or 8 elements per lane");
4790 unsigned Shift = (NumLaneElts >= 4) ? 1 : 0;
4792 for (unsigned i = 0; i != NumElts; ++i) {
4793 int Elt = N->getMaskElt(i);
4794 if (Elt < 0) continue;
4795 Elt &= NumLaneElts - 1;
4796 unsigned ShAmt = (i << Shift) % 8;
4797 Mask |= Elt << ShAmt;
4803 /// getShufflePSHUFHWImmediate - Return the appropriate immediate to shuffle
4804 /// the specified VECTOR_SHUFFLE mask with the PSHUFHW instruction.
4805 static unsigned getShufflePSHUFHWImmediate(ShuffleVectorSDNode *N) {
4806 MVT VT = N->getSimpleValueType(0);
4808 assert((VT == MVT::v8i16 || VT == MVT::v16i16) &&
4809 "Unsupported vector type for PSHUFHW");
4811 unsigned NumElts = VT.getVectorNumElements();
4814 for (unsigned l = 0; l != NumElts; l += 8) {
4815 // 8 nodes per lane, but we only care about the last 4.
4816 for (unsigned i = 0; i < 4; ++i) {
4817 int Elt = N->getMaskElt(l+i+4);
4818 if (Elt < 0) continue;
4819 Elt &= 0x3; // only 2-bits.
4820 Mask |= Elt << (i * 2);
4827 /// getShufflePSHUFLWImmediate - Return the appropriate immediate to shuffle
4828 /// the specified VECTOR_SHUFFLE mask with the PSHUFLW instruction.
4829 static unsigned getShufflePSHUFLWImmediate(ShuffleVectorSDNode *N) {
4830 MVT VT = N->getSimpleValueType(0);
4832 assert((VT == MVT::v8i16 || VT == MVT::v16i16) &&
4833 "Unsupported vector type for PSHUFHW");
4835 unsigned NumElts = VT.getVectorNumElements();
4838 for (unsigned l = 0; l != NumElts; l += 8) {
4839 // 8 nodes per lane, but we only care about the first 4.
4840 for (unsigned i = 0; i < 4; ++i) {
4841 int Elt = N->getMaskElt(l+i);
4842 if (Elt < 0) continue;
4843 Elt &= 0x3; // only 2-bits
4844 Mask |= Elt << (i * 2);
4851 /// \brief Return the appropriate immediate to shuffle the specified
4852 /// VECTOR_SHUFFLE mask with the PALIGNR (if InterLane is false) or with
4853 /// VALIGN (if Interlane is true) instructions.
4854 static unsigned getShuffleAlignrImmediate(ShuffleVectorSDNode *SVOp,
4856 MVT VT = SVOp->getSimpleValueType(0);
4857 unsigned EltSize = InterLane ? 1 :
4858 VT.getVectorElementType().getSizeInBits() >> 3;
4860 unsigned NumElts = VT.getVectorNumElements();
4861 unsigned NumLanes = VT.is512BitVector() ? 1 : VT.getSizeInBits()/128;
4862 unsigned NumLaneElts = NumElts/NumLanes;
4866 for (i = 0; i != NumElts; ++i) {
4867 Val = SVOp->getMaskElt(i);
4871 if (Val >= (int)NumElts)
4872 Val -= NumElts - NumLaneElts;
4874 assert(Val - i > 0 && "PALIGNR imm should be positive");
4875 return (Val - i) * EltSize;
4878 /// \brief Return the appropriate immediate to shuffle the specified
4879 /// VECTOR_SHUFFLE mask with the PALIGNR instruction.
4880 static unsigned getShufflePALIGNRImmediate(ShuffleVectorSDNode *SVOp) {
4881 return getShuffleAlignrImmediate(SVOp, false);
4884 /// \brief Return the appropriate immediate to shuffle the specified
4885 /// VECTOR_SHUFFLE mask with the VALIGN instruction.
4886 static unsigned getShuffleVALIGNImmediate(ShuffleVectorSDNode *SVOp) {
4887 return getShuffleAlignrImmediate(SVOp, true);
4891 static unsigned getExtractVEXTRACTImmediate(SDNode *N, unsigned vecWidth) {
4892 assert((vecWidth == 128 || vecWidth == 256) && "Unsupported vector width");
4893 if (!isa<ConstantSDNode>(N->getOperand(1).getNode()))
4894 llvm_unreachable("Illegal extract subvector for VEXTRACT");
4897 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
4899 MVT VecVT = N->getOperand(0).getSimpleValueType();
4900 MVT ElVT = VecVT.getVectorElementType();
4902 unsigned NumElemsPerChunk = vecWidth / ElVT.getSizeInBits();
4903 return Index / NumElemsPerChunk;
4906 static unsigned getInsertVINSERTImmediate(SDNode *N, unsigned vecWidth) {
4907 assert((vecWidth == 128 || vecWidth == 256) && "Unsupported vector width");
4908 if (!isa<ConstantSDNode>(N->getOperand(2).getNode()))
4909 llvm_unreachable("Illegal insert subvector for VINSERT");
4912 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
4914 MVT VecVT = N->getSimpleValueType(0);
4915 MVT ElVT = VecVT.getVectorElementType();
4917 unsigned NumElemsPerChunk = vecWidth / ElVT.getSizeInBits();
4918 return Index / NumElemsPerChunk;
4921 /// getExtractVEXTRACT128Immediate - Return the appropriate immediate
4922 /// to extract the specified EXTRACT_SUBVECTOR index with VEXTRACTF128
4923 /// and VINSERTI128 instructions.
4924 unsigned X86::getExtractVEXTRACT128Immediate(SDNode *N) {
4925 return getExtractVEXTRACTImmediate(N, 128);
4928 /// getExtractVEXTRACT256Immediate - Return the appropriate immediate
4929 /// to extract the specified EXTRACT_SUBVECTOR index with VEXTRACTF64x4
4930 /// and VINSERTI64x4 instructions.
4931 unsigned X86::getExtractVEXTRACT256Immediate(SDNode *N) {
4932 return getExtractVEXTRACTImmediate(N, 256);
4935 /// getInsertVINSERT128Immediate - Return the appropriate immediate
4936 /// to insert at the specified INSERT_SUBVECTOR index with VINSERTF128
4937 /// and VINSERTI128 instructions.
4938 unsigned X86::getInsertVINSERT128Immediate(SDNode *N) {
4939 return getInsertVINSERTImmediate(N, 128);
4942 /// getInsertVINSERT256Immediate - Return the appropriate immediate
4943 /// to insert at the specified INSERT_SUBVECTOR index with VINSERTF46x4
4944 /// and VINSERTI64x4 instructions.
4945 unsigned X86::getInsertVINSERT256Immediate(SDNode *N) {
4946 return getInsertVINSERTImmediate(N, 256);
4949 /// isZero - Returns true if Elt is a constant integer zero
4950 static bool isZero(SDValue V) {
4951 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V);
4952 return C && C->isNullValue();
4955 /// isZeroNode - Returns true if Elt is a constant zero or a floating point
4957 bool X86::isZeroNode(SDValue Elt) {
4960 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Elt))
4961 return CFP->getValueAPF().isPosZero();
4965 /// ShouldXformToMOVHLPS - Return true if the node should be transformed to
4966 /// match movhlps. The lower half elements should come from upper half of
4967 /// V1 (and in order), and the upper half elements should come from the upper
4968 /// half of V2 (and in order).
4969 static bool ShouldXformToMOVHLPS(ArrayRef<int> Mask, MVT VT) {
4970 if (!VT.is128BitVector())
4972 if (VT.getVectorNumElements() != 4)
4974 for (unsigned i = 0, e = 2; i != e; ++i)
4975 if (!isUndefOrEqual(Mask[i], i+2))
4977 for (unsigned i = 2; i != 4; ++i)
4978 if (!isUndefOrEqual(Mask[i], i+4))
4983 /// isScalarLoadToVector - Returns true if the node is a scalar load that
4984 /// is promoted to a vector. It also returns the LoadSDNode by reference if
4986 static bool isScalarLoadToVector(SDNode *N, LoadSDNode **LD = nullptr) {
4987 if (N->getOpcode() != ISD::SCALAR_TO_VECTOR)
4989 N = N->getOperand(0).getNode();
4990 if (!ISD::isNON_EXTLoad(N))
4993 *LD = cast<LoadSDNode>(N);
4997 // Test whether the given value is a vector value which will be legalized
4999 static bool WillBeConstantPoolLoad(SDNode *N) {
5000 if (N->getOpcode() != ISD::BUILD_VECTOR)
5003 // Check for any non-constant elements.
5004 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
5005 switch (N->getOperand(i).getNode()->getOpcode()) {
5007 case ISD::ConstantFP:
5014 // Vectors of all-zeros and all-ones are materialized with special
5015 // instructions rather than being loaded.
5016 return !ISD::isBuildVectorAllZeros(N) &&
5017 !ISD::isBuildVectorAllOnes(N);
5020 /// ShouldXformToMOVLP{S|D} - Return true if the node should be transformed to
5021 /// match movlp{s|d}. The lower half elements should come from lower half of
5022 /// V1 (and in order), and the upper half elements should come from the upper
5023 /// half of V2 (and in order). And since V1 will become the source of the
5024 /// MOVLP, it must be either a vector load or a scalar load to vector.
5025 static bool ShouldXformToMOVLP(SDNode *V1, SDNode *V2,
5026 ArrayRef<int> Mask, MVT VT) {
5027 if (!VT.is128BitVector())
5030 if (!ISD::isNON_EXTLoad(V1) && !isScalarLoadToVector(V1))
5032 // Is V2 is a vector load, don't do this transformation. We will try to use
5033 // load folding shufps op.
5034 if (ISD::isNON_EXTLoad(V2) || WillBeConstantPoolLoad(V2))
5037 unsigned NumElems = VT.getVectorNumElements();
5039 if (NumElems != 2 && NumElems != 4)
5041 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
5042 if (!isUndefOrEqual(Mask[i], i))
5044 for (unsigned i = NumElems/2, e = NumElems; i != e; ++i)
5045 if (!isUndefOrEqual(Mask[i], i+NumElems))
5050 /// isZeroShuffle - Returns true if N is a VECTOR_SHUFFLE that can be resolved
5051 /// to an zero vector.
5052 /// FIXME: move to dag combiner / method on ShuffleVectorSDNode
5053 static bool isZeroShuffle(ShuffleVectorSDNode *N) {
5054 SDValue V1 = N->getOperand(0);
5055 SDValue V2 = N->getOperand(1);
5056 unsigned NumElems = N->getValueType(0).getVectorNumElements();
5057 for (unsigned i = 0; i != NumElems; ++i) {
5058 int Idx = N->getMaskElt(i);
5059 if (Idx >= (int)NumElems) {
5060 unsigned Opc = V2.getOpcode();
5061 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V2.getNode()))
5063 if (Opc != ISD::BUILD_VECTOR ||
5064 !X86::isZeroNode(V2.getOperand(Idx-NumElems)))
5066 } else if (Idx >= 0) {
5067 unsigned Opc = V1.getOpcode();
5068 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V1.getNode()))
5070 if (Opc != ISD::BUILD_VECTOR ||
5071 !X86::isZeroNode(V1.getOperand(Idx)))
5078 /// getZeroVector - Returns a vector of specified type with all zero elements.
5080 static SDValue getZeroVector(EVT VT, const X86Subtarget *Subtarget,
5081 SelectionDAG &DAG, SDLoc dl) {
5082 assert(VT.isVector() && "Expected a vector type");
5084 // Always build SSE zero vectors as <4 x i32> bitcasted
5085 // to their dest type. This ensures they get CSE'd.
5087 if (VT.is128BitVector()) { // SSE
5088 if (Subtarget->hasSSE2()) { // SSE2
5089 SDValue Cst = DAG.getConstant(0, MVT::i32);
5090 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
5092 SDValue Cst = DAG.getConstantFP(+0.0, MVT::f32);
5093 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4f32, Cst, Cst, Cst, Cst);
5095 } else if (VT.is256BitVector()) { // AVX
5096 if (Subtarget->hasInt256()) { // AVX2
5097 SDValue Cst = DAG.getConstant(0, MVT::i32);
5098 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
5099 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops);
5101 // 256-bit logic and arithmetic instructions in AVX are all
5102 // floating-point, no support for integer ops. Emit fp zeroed vectors.
5103 SDValue Cst = DAG.getConstantFP(+0.0, MVT::f32);
5104 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
5105 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8f32, Ops);
5107 } else if (VT.is512BitVector()) { // AVX-512
5108 SDValue Cst = DAG.getConstant(0, MVT::i32);
5109 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst,
5110 Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
5111 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v16i32, Ops);
5112 } else if (VT.getScalarType() == MVT::i1) {
5113 assert(VT.getVectorNumElements() <= 16 && "Unexpected vector type");
5114 SDValue Cst = DAG.getConstant(0, MVT::i1);
5115 SmallVector<SDValue, 16> Ops(VT.getVectorNumElements(), Cst);
5116 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
5118 llvm_unreachable("Unexpected vector type");
5120 return DAG.getNode(ISD::BITCAST, dl, VT, Vec);
5123 /// getOnesVector - Returns a vector of specified type with all bits set.
5124 /// Always build ones vectors as <4 x i32> or <8 x i32>. For 256-bit types with
5125 /// no AVX2 supprt, use two <4 x i32> inserted in a <8 x i32> appropriately.
5126 /// Then bitcast to their original type, ensuring they get CSE'd.
5127 static SDValue getOnesVector(MVT VT, bool HasInt256, SelectionDAG &DAG,
5129 assert(VT.isVector() && "Expected a vector type");
5131 SDValue Cst = DAG.getConstant(~0U, MVT::i32);
5133 if (VT.is256BitVector()) {
5134 if (HasInt256) { // AVX2
5135 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
5136 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops);
5138 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
5139 Vec = Concat128BitVectors(Vec, Vec, MVT::v8i32, 8, DAG, dl);
5141 } else if (VT.is128BitVector()) {
5142 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
5144 llvm_unreachable("Unexpected vector type");
5146 return DAG.getNode(ISD::BITCAST, dl, VT, Vec);
5149 /// NormalizeMask - V2 is a splat, modify the mask (if needed) so all elements
5150 /// that point to V2 points to its first element.
5151 static void NormalizeMask(SmallVectorImpl<int> &Mask, unsigned NumElems) {
5152 for (unsigned i = 0; i != NumElems; ++i) {
5153 if (Mask[i] > (int)NumElems) {
5159 /// getMOVLMask - Returns a vector_shuffle mask for an movs{s|d}, movd
5160 /// operation of specified width.
5161 static SDValue getMOVL(SelectionDAG &DAG, SDLoc dl, EVT VT, SDValue V1,
5163 unsigned NumElems = VT.getVectorNumElements();
5164 SmallVector<int, 8> Mask;
5165 Mask.push_back(NumElems);
5166 for (unsigned i = 1; i != NumElems; ++i)
5168 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
5171 /// getUnpackl - Returns a vector_shuffle node for an unpackl operation.
5172 static SDValue getUnpackl(SelectionDAG &DAG, SDLoc dl, MVT VT, SDValue V1,
5174 unsigned NumElems = VT.getVectorNumElements();
5175 SmallVector<int, 8> Mask;
5176 for (unsigned i = 0, e = NumElems/2; i != e; ++i) {
5178 Mask.push_back(i + NumElems);
5180 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
5183 /// getUnpackh - Returns a vector_shuffle node for an unpackh operation.
5184 static SDValue getUnpackh(SelectionDAG &DAG, SDLoc dl, MVT VT, SDValue V1,
5186 unsigned NumElems = VT.getVectorNumElements();
5187 SmallVector<int, 8> Mask;
5188 for (unsigned i = 0, Half = NumElems/2; i != Half; ++i) {
5189 Mask.push_back(i + Half);
5190 Mask.push_back(i + NumElems + Half);
5192 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
5195 // PromoteSplati8i16 - All i16 and i8 vector types can't be used directly by
5196 // a generic shuffle instruction because the target has no such instructions.
5197 // Generate shuffles which repeat i16 and i8 several times until they can be
5198 // represented by v4f32 and then be manipulated by target suported shuffles.
5199 static SDValue PromoteSplati8i16(SDValue V, SelectionDAG &DAG, int &EltNo) {
5200 MVT VT = V.getSimpleValueType();
5201 int NumElems = VT.getVectorNumElements();
5204 while (NumElems > 4) {
5205 if (EltNo < NumElems/2) {
5206 V = getUnpackl(DAG, dl, VT, V, V);
5208 V = getUnpackh(DAG, dl, VT, V, V);
5209 EltNo -= NumElems/2;
5216 /// getLegalSplat - Generate a legal splat with supported x86 shuffles
5217 static SDValue getLegalSplat(SelectionDAG &DAG, SDValue V, int EltNo) {
5218 MVT VT = V.getSimpleValueType();
5221 if (VT.is128BitVector()) {
5222 V = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V);
5223 int SplatMask[4] = { EltNo, EltNo, EltNo, EltNo };
5224 V = DAG.getVectorShuffle(MVT::v4f32, dl, V, DAG.getUNDEF(MVT::v4f32),
5226 } else if (VT.is256BitVector()) {
5227 // To use VPERMILPS to splat scalars, the second half of indicies must
5228 // refer to the higher part, which is a duplication of the lower one,
5229 // because VPERMILPS can only handle in-lane permutations.
5230 int SplatMask[8] = { EltNo, EltNo, EltNo, EltNo,
5231 EltNo+4, EltNo+4, EltNo+4, EltNo+4 };
5233 V = DAG.getNode(ISD::BITCAST, dl, MVT::v8f32, V);
5234 V = DAG.getVectorShuffle(MVT::v8f32, dl, V, DAG.getUNDEF(MVT::v8f32),
5237 llvm_unreachable("Vector size not supported");
5239 return DAG.getNode(ISD::BITCAST, dl, VT, V);
5242 /// PromoteSplat - Splat is promoted to target supported vector shuffles.
5243 static SDValue PromoteSplat(ShuffleVectorSDNode *SV, SelectionDAG &DAG) {
5244 MVT SrcVT = SV->getSimpleValueType(0);
5245 SDValue V1 = SV->getOperand(0);
5248 int EltNo = SV->getSplatIndex();
5249 int NumElems = SrcVT.getVectorNumElements();
5250 bool Is256BitVec = SrcVT.is256BitVector();
5252 assert(((SrcVT.is128BitVector() && NumElems > 4) || Is256BitVec) &&
5253 "Unknown how to promote splat for type");
5255 // Extract the 128-bit part containing the splat element and update
5256 // the splat element index when it refers to the higher register.
5258 V1 = Extract128BitVector(V1, EltNo, DAG, dl);
5259 if (EltNo >= NumElems/2)
5260 EltNo -= NumElems/2;
5263 // All i16 and i8 vector types can't be used directly by a generic shuffle
5264 // instruction because the target has no such instruction. Generate shuffles
5265 // which repeat i16 and i8 several times until they fit in i32, and then can
5266 // be manipulated by target suported shuffles.
5267 MVT EltVT = SrcVT.getVectorElementType();
5268 if (EltVT == MVT::i8 || EltVT == MVT::i16)
5269 V1 = PromoteSplati8i16(V1, DAG, EltNo);
5271 // Recreate the 256-bit vector and place the same 128-bit vector
5272 // into the low and high part. This is necessary because we want
5273 // to use VPERM* to shuffle the vectors
5275 V1 = DAG.getNode(ISD::CONCAT_VECTORS, dl, SrcVT, V1, V1);
5278 return getLegalSplat(DAG, V1, EltNo);
5281 /// getShuffleVectorZeroOrUndef - Return a vector_shuffle of the specified
5282 /// vector of zero or undef vector. This produces a shuffle where the low
5283 /// element of V2 is swizzled into the zero/undef vector, landing at element
5284 /// Idx. This produces a shuffle mask like 4,1,2,3 (idx=0) or 0,1,2,4 (idx=3).
5285 static SDValue getShuffleVectorZeroOrUndef(SDValue V2, unsigned Idx,
5287 const X86Subtarget *Subtarget,
5288 SelectionDAG &DAG) {
5289 MVT VT = V2.getSimpleValueType();
5291 ? getZeroVector(VT, Subtarget, DAG, SDLoc(V2)) : DAG.getUNDEF(VT);
5292 unsigned NumElems = VT.getVectorNumElements();
5293 SmallVector<int, 16> MaskVec;
5294 for (unsigned i = 0; i != NumElems; ++i)
5295 // If this is the insertion idx, put the low elt of V2 here.
5296 MaskVec.push_back(i == Idx ? NumElems : i);
5297 return DAG.getVectorShuffle(VT, SDLoc(V2), V1, V2, &MaskVec[0]);
5300 /// getTargetShuffleMask - Calculates the shuffle mask corresponding to the
5301 /// target specific opcode. Returns true if the Mask could be calculated. Sets
5302 /// IsUnary to true if only uses one source. Note that this will set IsUnary for
5303 /// shuffles which use a single input multiple times, and in those cases it will
5304 /// adjust the mask to only have indices within that single input.
5305 static bool getTargetShuffleMask(SDNode *N, MVT VT,
5306 SmallVectorImpl<int> &Mask, bool &IsUnary) {
5307 unsigned NumElems = VT.getVectorNumElements();
5311 bool IsFakeUnary = false;
5312 switch(N->getOpcode()) {
5313 case X86ISD::BLENDI:
5314 ImmN = N->getOperand(N->getNumOperands()-1);
5315 DecodeBLENDMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5318 ImmN = N->getOperand(N->getNumOperands()-1);
5319 DecodeSHUFPMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5320 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
5322 case X86ISD::UNPCKH:
5323 DecodeUNPCKHMask(VT, Mask);
5324 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
5326 case X86ISD::UNPCKL:
5327 DecodeUNPCKLMask(VT, Mask);
5328 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
5330 case X86ISD::MOVHLPS:
5331 DecodeMOVHLPSMask(NumElems, Mask);
5332 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
5334 case X86ISD::MOVLHPS:
5335 DecodeMOVLHPSMask(NumElems, Mask);
5336 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
5338 case X86ISD::PALIGNR:
5339 ImmN = N->getOperand(N->getNumOperands()-1);
5340 DecodePALIGNRMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5342 case X86ISD::PSHUFD:
5343 case X86ISD::VPERMILPI:
5344 ImmN = N->getOperand(N->getNumOperands()-1);
5345 DecodePSHUFMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5348 case X86ISD::PSHUFHW:
5349 ImmN = N->getOperand(N->getNumOperands()-1);
5350 DecodePSHUFHWMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5353 case X86ISD::PSHUFLW:
5354 ImmN = N->getOperand(N->getNumOperands()-1);
5355 DecodePSHUFLWMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5358 case X86ISD::PSHUFB: {
5360 SDValue MaskNode = N->getOperand(1);
5361 while (MaskNode->getOpcode() == ISD::BITCAST)
5362 MaskNode = MaskNode->getOperand(0);
5364 if (MaskNode->getOpcode() == ISD::BUILD_VECTOR) {
5365 // If we have a build-vector, then things are easy.
5366 EVT VT = MaskNode.getValueType();
5367 assert(VT.isVector() &&
5368 "Can't produce a non-vector with a build_vector!");
5369 if (!VT.isInteger())
5372 int NumBytesPerElement = VT.getVectorElementType().getSizeInBits() / 8;
5374 SmallVector<uint64_t, 32> RawMask;
5375 for (int i = 0, e = MaskNode->getNumOperands(); i < e; ++i) {
5376 SDValue Op = MaskNode->getOperand(i);
5377 if (Op->getOpcode() == ISD::UNDEF) {
5378 RawMask.push_back((uint64_t)SM_SentinelUndef);
5381 auto *CN = dyn_cast<ConstantSDNode>(Op.getNode());
5384 APInt MaskElement = CN->getAPIntValue();
5386 // We now have to decode the element which could be any integer size and
5387 // extract each byte of it.
5388 for (int j = 0; j < NumBytesPerElement; ++j) {
5389 // Note that this is x86 and so always little endian: the low byte is
5390 // the first byte of the mask.
5391 RawMask.push_back(MaskElement.getLoBits(8).getZExtValue());
5392 MaskElement = MaskElement.lshr(8);
5395 DecodePSHUFBMask(RawMask, Mask);
5399 auto *MaskLoad = dyn_cast<LoadSDNode>(MaskNode);
5403 SDValue Ptr = MaskLoad->getBasePtr();
5404 if (Ptr->getOpcode() == X86ISD::Wrapper)
5405 Ptr = Ptr->getOperand(0);
5407 auto *MaskCP = dyn_cast<ConstantPoolSDNode>(Ptr);
5408 if (!MaskCP || MaskCP->isMachineConstantPoolEntry())
5411 if (auto *C = dyn_cast<Constant>(MaskCP->getConstVal())) {
5412 // FIXME: Support AVX-512 here.
5413 Type *Ty = C->getType();
5414 if (!Ty->isVectorTy() || (Ty->getVectorNumElements() != 16 &&
5415 Ty->getVectorNumElements() != 32))
5418 DecodePSHUFBMask(C, Mask);
5424 case X86ISD::VPERMI:
5425 ImmN = N->getOperand(N->getNumOperands()-1);
5426 DecodeVPERMMask(cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5430 case X86ISD::MOVSD: {
5431 // The index 0 always comes from the first element of the second source,
5432 // this is why MOVSS and MOVSD are used in the first place. The other
5433 // elements come from the other positions of the first source vector
5434 Mask.push_back(NumElems);
5435 for (unsigned i = 1; i != NumElems; ++i) {
5440 case X86ISD::VPERM2X128:
5441 ImmN = N->getOperand(N->getNumOperands()-1);
5442 DecodeVPERM2X128Mask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5443 if (Mask.empty()) return false;
5445 case X86ISD::MOVSLDUP:
5446 DecodeMOVSLDUPMask(VT, Mask);
5448 case X86ISD::MOVSHDUP:
5449 DecodeMOVSHDUPMask(VT, Mask);
5451 case X86ISD::MOVDDUP:
5452 case X86ISD::MOVLHPD:
5453 case X86ISD::MOVLPD:
5454 case X86ISD::MOVLPS:
5455 // Not yet implemented
5457 default: llvm_unreachable("unknown target shuffle node");
5460 // If we have a fake unary shuffle, the shuffle mask is spread across two
5461 // inputs that are actually the same node. Re-map the mask to always point
5462 // into the first input.
5465 if (M >= (int)Mask.size())
5471 /// getShuffleScalarElt - Returns the scalar element that will make up the ith
5472 /// element of the result of the vector shuffle.
5473 static SDValue getShuffleScalarElt(SDNode *N, unsigned Index, SelectionDAG &DAG,
5476 return SDValue(); // Limit search depth.
5478 SDValue V = SDValue(N, 0);
5479 EVT VT = V.getValueType();
5480 unsigned Opcode = V.getOpcode();
5482 // Recurse into ISD::VECTOR_SHUFFLE node to find scalars.
5483 if (const ShuffleVectorSDNode *SV = dyn_cast<ShuffleVectorSDNode>(N)) {
5484 int Elt = SV->getMaskElt(Index);
5487 return DAG.getUNDEF(VT.getVectorElementType());
5489 unsigned NumElems = VT.getVectorNumElements();
5490 SDValue NewV = (Elt < (int)NumElems) ? SV->getOperand(0)
5491 : SV->getOperand(1);
5492 return getShuffleScalarElt(NewV.getNode(), Elt % NumElems, DAG, Depth+1);
5495 // Recurse into target specific vector shuffles to find scalars.
5496 if (isTargetShuffle(Opcode)) {
5497 MVT ShufVT = V.getSimpleValueType();
5498 unsigned NumElems = ShufVT.getVectorNumElements();
5499 SmallVector<int, 16> ShuffleMask;
5502 if (!getTargetShuffleMask(N, ShufVT, ShuffleMask, IsUnary))
5505 int Elt = ShuffleMask[Index];
5507 return DAG.getUNDEF(ShufVT.getVectorElementType());
5509 SDValue NewV = (Elt < (int)NumElems) ? N->getOperand(0)
5511 return getShuffleScalarElt(NewV.getNode(), Elt % NumElems, DAG,
5515 // Actual nodes that may contain scalar elements
5516 if (Opcode == ISD::BITCAST) {
5517 V = V.getOperand(0);
5518 EVT SrcVT = V.getValueType();
5519 unsigned NumElems = VT.getVectorNumElements();
5521 if (!SrcVT.isVector() || SrcVT.getVectorNumElements() != NumElems)
5525 if (V.getOpcode() == ISD::SCALAR_TO_VECTOR)
5526 return (Index == 0) ? V.getOperand(0)
5527 : DAG.getUNDEF(VT.getVectorElementType());
5529 if (V.getOpcode() == ISD::BUILD_VECTOR)
5530 return V.getOperand(Index);
5535 /// getNumOfConsecutiveZeros - Return the number of elements of a vector
5536 /// shuffle operation which come from a consecutively from a zero. The
5537 /// search can start in two different directions, from left or right.
5538 /// We count undefs as zeros until PreferredNum is reached.
5539 static unsigned getNumOfConsecutiveZeros(ShuffleVectorSDNode *SVOp,
5540 unsigned NumElems, bool ZerosFromLeft,
5542 unsigned PreferredNum = -1U) {
5543 unsigned NumZeros = 0;
5544 for (unsigned i = 0; i != NumElems; ++i) {
5545 unsigned Index = ZerosFromLeft ? i : NumElems - i - 1;
5546 SDValue Elt = getShuffleScalarElt(SVOp, Index, DAG, 0);
5550 if (X86::isZeroNode(Elt))
5552 else if (Elt.getOpcode() == ISD::UNDEF) // Undef as zero up to PreferredNum.
5553 NumZeros = std::min(NumZeros + 1, PreferredNum);
5561 /// isShuffleMaskConsecutive - Check if the shuffle mask indicies [MaskI, MaskE)
5562 /// correspond consecutively to elements from one of the vector operands,
5563 /// starting from its index OpIdx. Also tell OpNum which source vector operand.
5565 bool isShuffleMaskConsecutive(ShuffleVectorSDNode *SVOp,
5566 unsigned MaskI, unsigned MaskE, unsigned OpIdx,
5567 unsigned NumElems, unsigned &OpNum) {
5568 bool SeenV1 = false;
5569 bool SeenV2 = false;
5571 for (unsigned i = MaskI; i != MaskE; ++i, ++OpIdx) {
5572 int Idx = SVOp->getMaskElt(i);
5573 // Ignore undef indicies
5577 if (Idx < (int)NumElems)
5582 // Only accept consecutive elements from the same vector
5583 if ((Idx % NumElems != OpIdx) || (SeenV1 && SeenV2))
5587 OpNum = SeenV1 ? 0 : 1;
5591 /// isVectorShiftRight - Returns true if the shuffle can be implemented as a
5592 /// logical left shift of a vector.
5593 static bool isVectorShiftRight(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
5594 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
5596 SVOp->getSimpleValueType(0).getVectorNumElements();
5597 unsigned NumZeros = getNumOfConsecutiveZeros(
5598 SVOp, NumElems, false /* check zeros from right */, DAG,
5599 SVOp->getMaskElt(0));
5605 // Considering the elements in the mask that are not consecutive zeros,
5606 // check if they consecutively come from only one of the source vectors.
5608 // V1 = {X, A, B, C} 0
5610 // vector_shuffle V1, V2 <1, 2, 3, X>
5612 if (!isShuffleMaskConsecutive(SVOp,
5613 0, // Mask Start Index
5614 NumElems-NumZeros, // Mask End Index(exclusive)
5615 NumZeros, // Where to start looking in the src vector
5616 NumElems, // Number of elements in vector
5617 OpSrc)) // Which source operand ?
5622 ShVal = SVOp->getOperand(OpSrc);
5626 /// isVectorShiftLeft - Returns true if the shuffle can be implemented as a
5627 /// logical left shift of a vector.
5628 static bool isVectorShiftLeft(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
5629 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
5631 SVOp->getSimpleValueType(0).getVectorNumElements();
5632 unsigned NumZeros = getNumOfConsecutiveZeros(
5633 SVOp, NumElems, true /* check zeros from left */, DAG,
5634 NumElems - SVOp->getMaskElt(NumElems - 1) - 1);
5640 // Considering the elements in the mask that are not consecutive zeros,
5641 // check if they consecutively come from only one of the source vectors.
5643 // 0 { A, B, X, X } = V2
5645 // vector_shuffle V1, V2 <X, X, 4, 5>
5647 if (!isShuffleMaskConsecutive(SVOp,
5648 NumZeros, // Mask Start Index
5649 NumElems, // Mask End Index(exclusive)
5650 0, // Where to start looking in the src vector
5651 NumElems, // Number of elements in vector
5652 OpSrc)) // Which source operand ?
5657 ShVal = SVOp->getOperand(OpSrc);
5661 /// isVectorShift - Returns true if the shuffle can be implemented as a
5662 /// logical left or right shift of a vector.
5663 static bool isVectorShift(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
5664 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
5665 // Although the logic below support any bitwidth size, there are no
5666 // shift instructions which handle more than 128-bit vectors.
5667 if (!SVOp->getSimpleValueType(0).is128BitVector())
5670 if (isVectorShiftLeft(SVOp, DAG, isLeft, ShVal, ShAmt) ||
5671 isVectorShiftRight(SVOp, DAG, isLeft, ShVal, ShAmt))
5677 /// LowerBuildVectorv16i8 - Custom lower build_vector of v16i8.
5679 static SDValue LowerBuildVectorv16i8(SDValue Op, unsigned NonZeros,
5680 unsigned NumNonZero, unsigned NumZero,
5682 const X86Subtarget* Subtarget,
5683 const TargetLowering &TLI) {
5690 for (unsigned i = 0; i < 16; ++i) {
5691 bool ThisIsNonZero = (NonZeros & (1 << i)) != 0;
5692 if (ThisIsNonZero && First) {
5694 V = getZeroVector(MVT::v8i16, Subtarget, DAG, dl);
5696 V = DAG.getUNDEF(MVT::v8i16);
5701 SDValue ThisElt, LastElt;
5702 bool LastIsNonZero = (NonZeros & (1 << (i-1))) != 0;
5703 if (LastIsNonZero) {
5704 LastElt = DAG.getNode(ISD::ZERO_EXTEND, dl,
5705 MVT::i16, Op.getOperand(i-1));
5707 if (ThisIsNonZero) {
5708 ThisElt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, Op.getOperand(i));
5709 ThisElt = DAG.getNode(ISD::SHL, dl, MVT::i16,
5710 ThisElt, DAG.getConstant(8, MVT::i8));
5712 ThisElt = DAG.getNode(ISD::OR, dl, MVT::i16, ThisElt, LastElt);
5716 if (ThisElt.getNode())
5717 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, V, ThisElt,
5718 DAG.getIntPtrConstant(i/2));
5722 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V);
5725 /// LowerBuildVectorv8i16 - Custom lower build_vector of v8i16.
5727 static SDValue LowerBuildVectorv8i16(SDValue Op, unsigned NonZeros,
5728 unsigned NumNonZero, unsigned NumZero,
5730 const X86Subtarget* Subtarget,
5731 const TargetLowering &TLI) {
5738 for (unsigned i = 0; i < 8; ++i) {
5739 bool isNonZero = (NonZeros & (1 << i)) != 0;
5743 V = getZeroVector(MVT::v8i16, Subtarget, DAG, dl);
5745 V = DAG.getUNDEF(MVT::v8i16);
5748 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl,
5749 MVT::v8i16, V, Op.getOperand(i),
5750 DAG.getIntPtrConstant(i));
5757 /// LowerBuildVectorv4x32 - Custom lower build_vector of v4i32 or v4f32.
5758 static SDValue LowerBuildVectorv4x32(SDValue Op, SelectionDAG &DAG,
5759 const X86Subtarget *Subtarget,
5760 const TargetLowering &TLI) {
5761 // Find all zeroable elements.
5763 for (int i=0; i < 4; ++i) {
5764 SDValue Elt = Op->getOperand(i);
5765 Zeroable[i] = (Elt.getOpcode() == ISD::UNDEF || X86::isZeroNode(Elt));
5767 assert(std::count_if(&Zeroable[0], &Zeroable[4],
5768 [](bool M) { return !M; }) > 1 &&
5769 "We expect at least two non-zero elements!");
5771 // We only know how to deal with build_vector nodes where elements are either
5772 // zeroable or extract_vector_elt with constant index.
5773 SDValue FirstNonZero;
5774 unsigned FirstNonZeroIdx;
5775 for (unsigned i=0; i < 4; ++i) {
5778 SDValue Elt = Op->getOperand(i);
5779 if (Elt.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
5780 !isa<ConstantSDNode>(Elt.getOperand(1)))
5782 // Make sure that this node is extracting from a 128-bit vector.
5783 MVT VT = Elt.getOperand(0).getSimpleValueType();
5784 if (!VT.is128BitVector())
5786 if (!FirstNonZero.getNode()) {
5788 FirstNonZeroIdx = i;
5792 assert(FirstNonZero.getNode() && "Unexpected build vector of all zeros!");
5793 SDValue V1 = FirstNonZero.getOperand(0);
5794 MVT VT = V1.getSimpleValueType();
5796 // See if this build_vector can be lowered as a blend with zero.
5798 unsigned EltMaskIdx, EltIdx;
5800 for (EltIdx = 0; EltIdx < 4; ++EltIdx) {
5801 if (Zeroable[EltIdx]) {
5802 // The zero vector will be on the right hand side.
5803 Mask[EltIdx] = EltIdx+4;
5807 Elt = Op->getOperand(EltIdx);
5808 // By construction, Elt is a EXTRACT_VECTOR_ELT with constant index.
5809 EltMaskIdx = cast<ConstantSDNode>(Elt.getOperand(1))->getZExtValue();
5810 if (Elt.getOperand(0) != V1 || EltMaskIdx != EltIdx)
5812 Mask[EltIdx] = EltIdx;
5816 // Let the shuffle legalizer deal with blend operations.
5817 SDValue VZero = getZeroVector(VT, Subtarget, DAG, SDLoc(Op));
5818 if (V1.getSimpleValueType() != VT)
5819 V1 = DAG.getNode(ISD::BITCAST, SDLoc(V1), VT, V1);
5820 return DAG.getVectorShuffle(VT, SDLoc(V1), V1, VZero, &Mask[0]);
5823 // See if we can lower this build_vector to a INSERTPS.
5824 if (!Subtarget->hasSSE41())
5827 SDValue V2 = Elt.getOperand(0);
5828 if (Elt == FirstNonZero && EltIdx == FirstNonZeroIdx)
5831 bool CanFold = true;
5832 for (unsigned i = EltIdx + 1; i < 4 && CanFold; ++i) {
5836 SDValue Current = Op->getOperand(i);
5837 SDValue SrcVector = Current->getOperand(0);
5840 CanFold = SrcVector == V1 &&
5841 cast<ConstantSDNode>(Current.getOperand(1))->getZExtValue() == i;
5847 assert(V1.getNode() && "Expected at least two non-zero elements!");
5848 if (V1.getSimpleValueType() != MVT::v4f32)
5849 V1 = DAG.getNode(ISD::BITCAST, SDLoc(V1), MVT::v4f32, V1);
5850 if (V2.getSimpleValueType() != MVT::v4f32)
5851 V2 = DAG.getNode(ISD::BITCAST, SDLoc(V2), MVT::v4f32, V2);
5853 // Ok, we can emit an INSERTPS instruction.
5855 for (int i = 0; i < 4; ++i)
5859 unsigned InsertPSMask = EltMaskIdx << 6 | EltIdx << 4 | ZMask;
5860 assert((InsertPSMask & ~0xFFu) == 0 && "Invalid mask!");
5861 SDValue Result = DAG.getNode(X86ISD::INSERTPS, SDLoc(Op), MVT::v4f32, V1, V2,
5862 DAG.getIntPtrConstant(InsertPSMask));
5863 return DAG.getNode(ISD::BITCAST, SDLoc(Op), VT, Result);
5866 /// getVShift - Return a vector logical shift node.
5868 static SDValue getVShift(bool isLeft, EVT VT, SDValue SrcOp,
5869 unsigned NumBits, SelectionDAG &DAG,
5870 const TargetLowering &TLI, SDLoc dl) {
5871 assert(VT.is128BitVector() && "Unknown type for VShift");
5872 EVT ShVT = MVT::v2i64;
5873 unsigned Opc = isLeft ? X86ISD::VSHLDQ : X86ISD::VSRLDQ;
5874 SrcOp = DAG.getNode(ISD::BITCAST, dl, ShVT, SrcOp);
5875 return DAG.getNode(ISD::BITCAST, dl, VT,
5876 DAG.getNode(Opc, dl, ShVT, SrcOp,
5877 DAG.getConstant(NumBits,
5878 TLI.getScalarShiftAmountTy(SrcOp.getValueType()))));
5882 LowerAsSplatVectorLoad(SDValue SrcOp, MVT VT, SDLoc dl, SelectionDAG &DAG) {
5884 // Check if the scalar load can be widened into a vector load. And if
5885 // the address is "base + cst" see if the cst can be "absorbed" into
5886 // the shuffle mask.
5887 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(SrcOp)) {
5888 SDValue Ptr = LD->getBasePtr();
5889 if (!ISD::isNormalLoad(LD) || LD->isVolatile())
5891 EVT PVT = LD->getValueType(0);
5892 if (PVT != MVT::i32 && PVT != MVT::f32)
5897 if (FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr)) {
5898 FI = FINode->getIndex();
5900 } else if (DAG.isBaseWithConstantOffset(Ptr) &&
5901 isa<FrameIndexSDNode>(Ptr.getOperand(0))) {
5902 FI = cast<FrameIndexSDNode>(Ptr.getOperand(0))->getIndex();
5903 Offset = Ptr.getConstantOperandVal(1);
5904 Ptr = Ptr.getOperand(0);
5909 // FIXME: 256-bit vector instructions don't require a strict alignment,
5910 // improve this code to support it better.
5911 unsigned RequiredAlign = VT.getSizeInBits()/8;
5912 SDValue Chain = LD->getChain();
5913 // Make sure the stack object alignment is at least 16 or 32.
5914 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
5915 if (DAG.InferPtrAlignment(Ptr) < RequiredAlign) {
5916 if (MFI->isFixedObjectIndex(FI)) {
5917 // Can't change the alignment. FIXME: It's possible to compute
5918 // the exact stack offset and reference FI + adjust offset instead.
5919 // If someone *really* cares about this. That's the way to implement it.
5922 MFI->setObjectAlignment(FI, RequiredAlign);
5926 // (Offset % 16 or 32) must be multiple of 4. Then address is then
5927 // Ptr + (Offset & ~15).
5930 if ((Offset % RequiredAlign) & 3)
5932 int64_t StartOffset = Offset & ~(RequiredAlign-1);
5934 Ptr = DAG.getNode(ISD::ADD, SDLoc(Ptr), Ptr.getValueType(),
5935 Ptr,DAG.getConstant(StartOffset, Ptr.getValueType()));
5937 int EltNo = (Offset - StartOffset) >> 2;
5938 unsigned NumElems = VT.getVectorNumElements();
5940 EVT NVT = EVT::getVectorVT(*DAG.getContext(), PVT, NumElems);
5941 SDValue V1 = DAG.getLoad(NVT, dl, Chain, Ptr,
5942 LD->getPointerInfo().getWithOffset(StartOffset),
5943 false, false, false, 0);
5945 SmallVector<int, 8> Mask;
5946 for (unsigned i = 0; i != NumElems; ++i)
5947 Mask.push_back(EltNo);
5949 return DAG.getVectorShuffle(NVT, dl, V1, DAG.getUNDEF(NVT), &Mask[0]);
5955 /// EltsFromConsecutiveLoads - Given the initializing elements 'Elts' of a
5956 /// vector of type 'VT', see if the elements can be replaced by a single large
5957 /// load which has the same value as a build_vector whose operands are 'elts'.
5959 /// Example: <load i32 *a, load i32 *a+4, undef, undef> -> zextload a
5961 /// FIXME: we'd also like to handle the case where the last elements are zero
5962 /// rather than undef via VZEXT_LOAD, but we do not detect that case today.
5963 /// There's even a handy isZeroNode for that purpose.
5964 static SDValue EltsFromConsecutiveLoads(EVT VT, SmallVectorImpl<SDValue> &Elts,
5965 SDLoc &DL, SelectionDAG &DAG,
5966 bool isAfterLegalize) {
5967 EVT EltVT = VT.getVectorElementType();
5968 unsigned NumElems = Elts.size();
5970 LoadSDNode *LDBase = nullptr;
5971 unsigned LastLoadedElt = -1U;
5973 // For each element in the initializer, see if we've found a load or an undef.
5974 // If we don't find an initial load element, or later load elements are
5975 // non-consecutive, bail out.
5976 for (unsigned i = 0; i < NumElems; ++i) {
5977 SDValue Elt = Elts[i];
5979 if (!Elt.getNode() ||
5980 (Elt.getOpcode() != ISD::UNDEF && !ISD::isNON_EXTLoad(Elt.getNode())))
5983 if (Elt.getNode()->getOpcode() == ISD::UNDEF)
5985 LDBase = cast<LoadSDNode>(Elt.getNode());
5989 if (Elt.getOpcode() == ISD::UNDEF)
5992 LoadSDNode *LD = cast<LoadSDNode>(Elt);
5993 if (!DAG.isConsecutiveLoad(LD, LDBase, EltVT.getSizeInBits()/8, i))
5998 // If we have found an entire vector of loads and undefs, then return a large
5999 // load of the entire vector width starting at the base pointer. If we found
6000 // consecutive loads for the low half, generate a vzext_load node.
6001 if (LastLoadedElt == NumElems - 1) {
6003 if (isAfterLegalize &&
6004 !DAG.getTargetLoweringInfo().isOperationLegal(ISD::LOAD, VT))
6007 SDValue NewLd = SDValue();
6009 if (DAG.InferPtrAlignment(LDBase->getBasePtr()) >= 16)
6010 NewLd = DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(),
6011 LDBase->getPointerInfo(),
6012 LDBase->isVolatile(), LDBase->isNonTemporal(),
6013 LDBase->isInvariant(), 0);
6014 NewLd = DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(),
6015 LDBase->getPointerInfo(),
6016 LDBase->isVolatile(), LDBase->isNonTemporal(),
6017 LDBase->isInvariant(), LDBase->getAlignment());
6019 if (LDBase->hasAnyUseOfValue(1)) {
6020 SDValue NewChain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
6022 SDValue(NewLd.getNode(), 1));
6023 DAG.ReplaceAllUsesOfValueWith(SDValue(LDBase, 1), NewChain);
6024 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(LDBase, 1),
6025 SDValue(NewLd.getNode(), 1));
6030 if (NumElems == 4 && LastLoadedElt == 1 &&
6031 DAG.getTargetLoweringInfo().isTypeLegal(MVT::v2i64)) {
6032 SDVTList Tys = DAG.getVTList(MVT::v2i64, MVT::Other);
6033 SDValue Ops[] = { LDBase->getChain(), LDBase->getBasePtr() };
6035 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, DL, Tys, Ops, MVT::i64,
6036 LDBase->getPointerInfo(),
6037 LDBase->getAlignment(),
6038 false/*isVolatile*/, true/*ReadMem*/,
6041 // Make sure the newly-created LOAD is in the same position as LDBase in
6042 // terms of dependency. We create a TokenFactor for LDBase and ResNode, and
6043 // update uses of LDBase's output chain to use the TokenFactor.
6044 if (LDBase->hasAnyUseOfValue(1)) {
6045 SDValue NewChain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
6046 SDValue(LDBase, 1), SDValue(ResNode.getNode(), 1));
6047 DAG.ReplaceAllUsesOfValueWith(SDValue(LDBase, 1), NewChain);
6048 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(LDBase, 1),
6049 SDValue(ResNode.getNode(), 1));
6052 return DAG.getNode(ISD::BITCAST, DL, VT, ResNode);
6057 /// LowerVectorBroadcast - Attempt to use the vbroadcast instruction
6058 /// to generate a splat value for the following cases:
6059 /// 1. A splat BUILD_VECTOR which uses a single scalar load, or a constant.
6060 /// 2. A splat shuffle which uses a scalar_to_vector node which comes from
6061 /// a scalar load, or a constant.
6062 /// The VBROADCAST node is returned when a pattern is found,
6063 /// or SDValue() otherwise.
6064 static SDValue LowerVectorBroadcast(SDValue Op, const X86Subtarget* Subtarget,
6065 SelectionDAG &DAG) {
6066 // VBROADCAST requires AVX.
6067 // TODO: Splats could be generated for non-AVX CPUs using SSE
6068 // instructions, but there's less potential gain for only 128-bit vectors.
6069 if (!Subtarget->hasAVX())
6072 MVT VT = Op.getSimpleValueType();
6075 assert((VT.is128BitVector() || VT.is256BitVector() || VT.is512BitVector()) &&
6076 "Unsupported vector type for broadcast.");
6081 switch (Op.getOpcode()) {
6083 // Unknown pattern found.
6086 case ISD::BUILD_VECTOR: {
6087 auto *BVOp = cast<BuildVectorSDNode>(Op.getNode());
6088 BitVector UndefElements;
6089 SDValue Splat = BVOp->getSplatValue(&UndefElements);
6091 // We need a splat of a single value to use broadcast, and it doesn't
6092 // make any sense if the value is only in one element of the vector.
6093 if (!Splat || (VT.getVectorNumElements() - UndefElements.count()) <= 1)
6097 ConstSplatVal = (Ld.getOpcode() == ISD::Constant ||
6098 Ld.getOpcode() == ISD::ConstantFP);
6100 // Make sure that all of the users of a non-constant load are from the
6101 // BUILD_VECTOR node.
6102 if (!ConstSplatVal && !BVOp->isOnlyUserOf(Ld.getNode()))
6107 case ISD::VECTOR_SHUFFLE: {
6108 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
6110 // Shuffles must have a splat mask where the first element is
6112 if ((!SVOp->isSplat()) || SVOp->getMaskElt(0) != 0)
6115 SDValue Sc = Op.getOperand(0);
6116 if (Sc.getOpcode() != ISD::SCALAR_TO_VECTOR &&
6117 Sc.getOpcode() != ISD::BUILD_VECTOR) {
6119 if (!Subtarget->hasInt256())
6122 // Use the register form of the broadcast instruction available on AVX2.
6123 if (VT.getSizeInBits() >= 256)
6124 Sc = Extract128BitVector(Sc, 0, DAG, dl);
6125 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Sc);
6128 Ld = Sc.getOperand(0);
6129 ConstSplatVal = (Ld.getOpcode() == ISD::Constant ||
6130 Ld.getOpcode() == ISD::ConstantFP);
6132 // The scalar_to_vector node and the suspected
6133 // load node must have exactly one user.
6134 // Constants may have multiple users.
6136 // AVX-512 has register version of the broadcast
6137 bool hasRegVer = Subtarget->hasAVX512() && VT.is512BitVector() &&
6138 Ld.getValueType().getSizeInBits() >= 32;
6139 if (!ConstSplatVal && ((!Sc.hasOneUse() || !Ld.hasOneUse()) &&
6146 unsigned ScalarSize = Ld.getValueType().getSizeInBits();
6147 bool IsGE256 = (VT.getSizeInBits() >= 256);
6149 // When optimizing for size, generate up to 5 extra bytes for a broadcast
6150 // instruction to save 8 or more bytes of constant pool data.
6151 // TODO: If multiple splats are generated to load the same constant,
6152 // it may be detrimental to overall size. There needs to be a way to detect
6153 // that condition to know if this is truly a size win.
6154 const Function *F = DAG.getMachineFunction().getFunction();
6155 bool OptForSize = F->getAttributes().
6156 hasAttribute(AttributeSet::FunctionIndex, Attribute::OptimizeForSize);
6158 // Handle broadcasting a single constant scalar from the constant pool
6160 // On Sandybridge (no AVX2), it is still better to load a constant vector
6161 // from the constant pool and not to broadcast it from a scalar.
6162 // But override that restriction when optimizing for size.
6163 // TODO: Check if splatting is recommended for other AVX-capable CPUs.
6164 if (ConstSplatVal && (Subtarget->hasAVX2() || OptForSize)) {
6165 EVT CVT = Ld.getValueType();
6166 assert(!CVT.isVector() && "Must not broadcast a vector type");
6168 // Splat f32, i32, v4f64, v4i64 in all cases with AVX2.
6169 // For size optimization, also splat v2f64 and v2i64, and for size opt
6170 // with AVX2, also splat i8 and i16.
6171 // With pattern matching, the VBROADCAST node may become a VMOVDDUP.
6172 if (ScalarSize == 32 || (IsGE256 && ScalarSize == 64) ||
6173 (OptForSize && (ScalarSize == 64 || Subtarget->hasAVX2()))) {
6174 const Constant *C = nullptr;
6175 if (ConstantSDNode *CI = dyn_cast<ConstantSDNode>(Ld))
6176 C = CI->getConstantIntValue();
6177 else if (ConstantFPSDNode *CF = dyn_cast<ConstantFPSDNode>(Ld))
6178 C = CF->getConstantFPValue();
6180 assert(C && "Invalid constant type");
6182 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
6183 SDValue CP = DAG.getConstantPool(C, TLI.getPointerTy());
6184 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
6185 Ld = DAG.getLoad(CVT, dl, DAG.getEntryNode(), CP,
6186 MachinePointerInfo::getConstantPool(),
6187 false, false, false, Alignment);
6189 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
6193 bool IsLoad = ISD::isNormalLoad(Ld.getNode());
6195 // Handle AVX2 in-register broadcasts.
6196 if (!IsLoad && Subtarget->hasInt256() &&
6197 (ScalarSize == 32 || (IsGE256 && ScalarSize == 64)))
6198 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
6200 // The scalar source must be a normal load.
6204 if (ScalarSize == 32 || (IsGE256 && ScalarSize == 64))
6205 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
6207 // The integer check is needed for the 64-bit into 128-bit so it doesn't match
6208 // double since there is no vbroadcastsd xmm
6209 if (Subtarget->hasInt256() && Ld.getValueType().isInteger()) {
6210 if (ScalarSize == 8 || ScalarSize == 16 || ScalarSize == 64)
6211 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
6214 // Unsupported broadcast.
6218 /// \brief For an EXTRACT_VECTOR_ELT with a constant index return the real
6219 /// underlying vector and index.
6221 /// Modifies \p ExtractedFromVec to the real vector and returns the real
6223 static int getUnderlyingExtractedFromVec(SDValue &ExtractedFromVec,
6225 int Idx = cast<ConstantSDNode>(ExtIdx)->getZExtValue();
6226 if (!isa<ShuffleVectorSDNode>(ExtractedFromVec))
6229 // For 256-bit vectors, LowerEXTRACT_VECTOR_ELT_SSE4 may have already
6231 // (extract_vector_elt (v8f32 %vreg1), Constant<6>)
6233 // (extract_vector_elt (vector_shuffle<2,u,u,u>
6234 // (extract_subvector (v8f32 %vreg0), Constant<4>),
6237 // In this case the vector is the extract_subvector expression and the index
6238 // is 2, as specified by the shuffle.
6239 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(ExtractedFromVec);
6240 SDValue ShuffleVec = SVOp->getOperand(0);
6241 MVT ShuffleVecVT = ShuffleVec.getSimpleValueType();
6242 assert(ShuffleVecVT.getVectorElementType() ==
6243 ExtractedFromVec.getSimpleValueType().getVectorElementType());
6245 int ShuffleIdx = SVOp->getMaskElt(Idx);
6246 if (isUndefOrInRange(ShuffleIdx, 0, ShuffleVecVT.getVectorNumElements())) {
6247 ExtractedFromVec = ShuffleVec;
6253 static SDValue buildFromShuffleMostly(SDValue Op, SelectionDAG &DAG) {
6254 MVT VT = Op.getSimpleValueType();
6256 // Skip if insert_vec_elt is not supported.
6257 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
6258 if (!TLI.isOperationLegalOrCustom(ISD::INSERT_VECTOR_ELT, VT))
6262 unsigned NumElems = Op.getNumOperands();
6266 SmallVector<unsigned, 4> InsertIndices;
6267 SmallVector<int, 8> Mask(NumElems, -1);
6269 for (unsigned i = 0; i != NumElems; ++i) {
6270 unsigned Opc = Op.getOperand(i).getOpcode();
6272 if (Opc == ISD::UNDEF)
6275 if (Opc != ISD::EXTRACT_VECTOR_ELT) {
6276 // Quit if more than 1 elements need inserting.
6277 if (InsertIndices.size() > 1)
6280 InsertIndices.push_back(i);
6284 SDValue ExtractedFromVec = Op.getOperand(i).getOperand(0);
6285 SDValue ExtIdx = Op.getOperand(i).getOperand(1);
6286 // Quit if non-constant index.
6287 if (!isa<ConstantSDNode>(ExtIdx))
6289 int Idx = getUnderlyingExtractedFromVec(ExtractedFromVec, ExtIdx);
6291 // Quit if extracted from vector of different type.
6292 if (ExtractedFromVec.getValueType() != VT)
6295 if (!VecIn1.getNode())
6296 VecIn1 = ExtractedFromVec;
6297 else if (VecIn1 != ExtractedFromVec) {
6298 if (!VecIn2.getNode())
6299 VecIn2 = ExtractedFromVec;
6300 else if (VecIn2 != ExtractedFromVec)
6301 // Quit if more than 2 vectors to shuffle
6305 if (ExtractedFromVec == VecIn1)
6307 else if (ExtractedFromVec == VecIn2)
6308 Mask[i] = Idx + NumElems;
6311 if (!VecIn1.getNode())
6314 VecIn2 = VecIn2.getNode() ? VecIn2 : DAG.getUNDEF(VT);
6315 SDValue NV = DAG.getVectorShuffle(VT, DL, VecIn1, VecIn2, &Mask[0]);
6316 for (unsigned i = 0, e = InsertIndices.size(); i != e; ++i) {
6317 unsigned Idx = InsertIndices[i];
6318 NV = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, VT, NV, Op.getOperand(Idx),
6319 DAG.getIntPtrConstant(Idx));
6325 // Lower BUILD_VECTOR operation for v8i1 and v16i1 types.
6327 X86TargetLowering::LowerBUILD_VECTORvXi1(SDValue Op, SelectionDAG &DAG) const {
6329 MVT VT = Op.getSimpleValueType();
6330 assert((VT.getVectorElementType() == MVT::i1) && (VT.getSizeInBits() <= 16) &&
6331 "Unexpected type in LowerBUILD_VECTORvXi1!");
6334 if (ISD::isBuildVectorAllZeros(Op.getNode())) {
6335 SDValue Cst = DAG.getTargetConstant(0, MVT::i1);
6336 SmallVector<SDValue, 16> Ops(VT.getVectorNumElements(), Cst);
6337 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
6340 if (ISD::isBuildVectorAllOnes(Op.getNode())) {
6341 SDValue Cst = DAG.getTargetConstant(1, MVT::i1);
6342 SmallVector<SDValue, 16> Ops(VT.getVectorNumElements(), Cst);
6343 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
6346 bool AllContants = true;
6347 uint64_t Immediate = 0;
6348 int NonConstIdx = -1;
6349 bool IsSplat = true;
6350 unsigned NumNonConsts = 0;
6351 unsigned NumConsts = 0;
6352 for (unsigned idx = 0, e = Op.getNumOperands(); idx < e; ++idx) {
6353 SDValue In = Op.getOperand(idx);
6354 if (In.getOpcode() == ISD::UNDEF)
6356 if (!isa<ConstantSDNode>(In)) {
6357 AllContants = false;
6363 if (cast<ConstantSDNode>(In)->getZExtValue())
6364 Immediate |= (1ULL << idx);
6366 if (In != Op.getOperand(0))
6371 SDValue FullMask = DAG.getNode(ISD::BITCAST, dl, MVT::v16i1,
6372 DAG.getConstant(Immediate, MVT::i16));
6373 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, FullMask,
6374 DAG.getIntPtrConstant(0));
6377 if (NumNonConsts == 1 && NonConstIdx != 0) {
6380 SDValue VecAsImm = DAG.getConstant(Immediate,
6381 MVT::getIntegerVT(VT.getSizeInBits()));
6382 DstVec = DAG.getNode(ISD::BITCAST, dl, VT, VecAsImm);
6385 DstVec = DAG.getUNDEF(VT);
6386 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, DstVec,
6387 Op.getOperand(NonConstIdx),
6388 DAG.getIntPtrConstant(NonConstIdx));
6390 if (!IsSplat && (NonConstIdx != 0))
6391 llvm_unreachable("Unsupported BUILD_VECTOR operation");
6392 MVT SelectVT = (VT == MVT::v16i1)? MVT::i16 : MVT::i8;
6395 Select = DAG.getNode(ISD::SELECT, dl, SelectVT, Op.getOperand(0),
6396 DAG.getConstant(-1, SelectVT),
6397 DAG.getConstant(0, SelectVT));
6399 Select = DAG.getNode(ISD::SELECT, dl, SelectVT, Op.getOperand(0),
6400 DAG.getConstant((Immediate | 1), SelectVT),
6401 DAG.getConstant(Immediate, SelectVT));
6402 return DAG.getNode(ISD::BITCAST, dl, VT, Select);
6405 /// \brief Return true if \p N implements a horizontal binop and return the
6406 /// operands for the horizontal binop into V0 and V1.
6408 /// This is a helper function of PerformBUILD_VECTORCombine.
6409 /// This function checks that the build_vector \p N in input implements a
6410 /// horizontal operation. Parameter \p Opcode defines the kind of horizontal
6411 /// operation to match.
6412 /// For example, if \p Opcode is equal to ISD::ADD, then this function
6413 /// checks if \p N implements a horizontal arithmetic add; if instead \p Opcode
6414 /// is equal to ISD::SUB, then this function checks if this is a horizontal
6417 /// This function only analyzes elements of \p N whose indices are
6418 /// in range [BaseIdx, LastIdx).
6419 static bool isHorizontalBinOp(const BuildVectorSDNode *N, unsigned Opcode,
6421 unsigned BaseIdx, unsigned LastIdx,
6422 SDValue &V0, SDValue &V1) {
6423 EVT VT = N->getValueType(0);
6425 assert(BaseIdx * 2 <= LastIdx && "Invalid Indices in input!");
6426 assert(VT.isVector() && VT.getVectorNumElements() >= LastIdx &&
6427 "Invalid Vector in input!");
6429 bool IsCommutable = (Opcode == ISD::ADD || Opcode == ISD::FADD);
6430 bool CanFold = true;
6431 unsigned ExpectedVExtractIdx = BaseIdx;
6432 unsigned NumElts = LastIdx - BaseIdx;
6433 V0 = DAG.getUNDEF(VT);
6434 V1 = DAG.getUNDEF(VT);
6436 // Check if N implements a horizontal binop.
6437 for (unsigned i = 0, e = NumElts; i != e && CanFold; ++i) {
6438 SDValue Op = N->getOperand(i + BaseIdx);
6441 if (Op->getOpcode() == ISD::UNDEF) {
6442 // Update the expected vector extract index.
6443 if (i * 2 == NumElts)
6444 ExpectedVExtractIdx = BaseIdx;
6445 ExpectedVExtractIdx += 2;
6449 CanFold = Op->getOpcode() == Opcode && Op->hasOneUse();
6454 SDValue Op0 = Op.getOperand(0);
6455 SDValue Op1 = Op.getOperand(1);
6457 // Try to match the following pattern:
6458 // (BINOP (extract_vector_elt A, I), (extract_vector_elt A, I+1))
6459 CanFold = (Op0.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
6460 Op1.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
6461 Op0.getOperand(0) == Op1.getOperand(0) &&
6462 isa<ConstantSDNode>(Op0.getOperand(1)) &&
6463 isa<ConstantSDNode>(Op1.getOperand(1)));
6467 unsigned I0 = cast<ConstantSDNode>(Op0.getOperand(1))->getZExtValue();
6468 unsigned I1 = cast<ConstantSDNode>(Op1.getOperand(1))->getZExtValue();
6470 if (i * 2 < NumElts) {
6471 if (V0.getOpcode() == ISD::UNDEF)
6472 V0 = Op0.getOperand(0);
6474 if (V1.getOpcode() == ISD::UNDEF)
6475 V1 = Op0.getOperand(0);
6476 if (i * 2 == NumElts)
6477 ExpectedVExtractIdx = BaseIdx;
6480 SDValue Expected = (i * 2 < NumElts) ? V0 : V1;
6481 if (I0 == ExpectedVExtractIdx)
6482 CanFold = I1 == I0 + 1 && Op0.getOperand(0) == Expected;
6483 else if (IsCommutable && I1 == ExpectedVExtractIdx) {
6484 // Try to match the following dag sequence:
6485 // (BINOP (extract_vector_elt A, I+1), (extract_vector_elt A, I))
6486 CanFold = I0 == I1 + 1 && Op1.getOperand(0) == Expected;
6490 ExpectedVExtractIdx += 2;
6496 /// \brief Emit a sequence of two 128-bit horizontal add/sub followed by
6497 /// a concat_vector.
6499 /// This is a helper function of PerformBUILD_VECTORCombine.
6500 /// This function expects two 256-bit vectors called V0 and V1.
6501 /// At first, each vector is split into two separate 128-bit vectors.
6502 /// Then, the resulting 128-bit vectors are used to implement two
6503 /// horizontal binary operations.
6505 /// The kind of horizontal binary operation is defined by \p X86Opcode.
6507 /// \p Mode specifies how the 128-bit parts of V0 and V1 are passed in input to
6508 /// the two new horizontal binop.
6509 /// When Mode is set, the first horizontal binop dag node would take as input
6510 /// the lower 128-bit of V0 and the upper 128-bit of V0. The second
6511 /// horizontal binop dag node would take as input the lower 128-bit of V1
6512 /// and the upper 128-bit of V1.
6514 /// HADD V0_LO, V0_HI
6515 /// HADD V1_LO, V1_HI
6517 /// Otherwise, the first horizontal binop dag node takes as input the lower
6518 /// 128-bit of V0 and the lower 128-bit of V1, and the second horizontal binop
6519 /// dag node takes the the upper 128-bit of V0 and the upper 128-bit of V1.
6521 /// HADD V0_LO, V1_LO
6522 /// HADD V0_HI, V1_HI
6524 /// If \p isUndefLO is set, then the algorithm propagates UNDEF to the lower
6525 /// 128-bits of the result. If \p isUndefHI is set, then UNDEF is propagated to
6526 /// the upper 128-bits of the result.
6527 static SDValue ExpandHorizontalBinOp(const SDValue &V0, const SDValue &V1,
6528 SDLoc DL, SelectionDAG &DAG,
6529 unsigned X86Opcode, bool Mode,
6530 bool isUndefLO, bool isUndefHI) {
6531 EVT VT = V0.getValueType();
6532 assert(VT.is256BitVector() && VT == V1.getValueType() &&
6533 "Invalid nodes in input!");
6535 unsigned NumElts = VT.getVectorNumElements();
6536 SDValue V0_LO = Extract128BitVector(V0, 0, DAG, DL);
6537 SDValue V0_HI = Extract128BitVector(V0, NumElts/2, DAG, DL);
6538 SDValue V1_LO = Extract128BitVector(V1, 0, DAG, DL);
6539 SDValue V1_HI = Extract128BitVector(V1, NumElts/2, DAG, DL);
6540 EVT NewVT = V0_LO.getValueType();
6542 SDValue LO = DAG.getUNDEF(NewVT);
6543 SDValue HI = DAG.getUNDEF(NewVT);
6546 // Don't emit a horizontal binop if the result is expected to be UNDEF.
6547 if (!isUndefLO && V0->getOpcode() != ISD::UNDEF)
6548 LO = DAG.getNode(X86Opcode, DL, NewVT, V0_LO, V0_HI);
6549 if (!isUndefHI && V1->getOpcode() != ISD::UNDEF)
6550 HI = DAG.getNode(X86Opcode, DL, NewVT, V1_LO, V1_HI);
6552 // Don't emit a horizontal binop if the result is expected to be UNDEF.
6553 if (!isUndefLO && (V0_LO->getOpcode() != ISD::UNDEF ||
6554 V1_LO->getOpcode() != ISD::UNDEF))
6555 LO = DAG.getNode(X86Opcode, DL, NewVT, V0_LO, V1_LO);
6557 if (!isUndefHI && (V0_HI->getOpcode() != ISD::UNDEF ||
6558 V1_HI->getOpcode() != ISD::UNDEF))
6559 HI = DAG.getNode(X86Opcode, DL, NewVT, V0_HI, V1_HI);
6562 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, LO, HI);
6565 /// \brief Try to fold a build_vector that performs an 'addsub' into the
6566 /// sequence of 'vadd + vsub + blendi'.
6567 static SDValue matchAddSub(const BuildVectorSDNode *BV, SelectionDAG &DAG,
6568 const X86Subtarget *Subtarget) {
6570 EVT VT = BV->getValueType(0);
6571 unsigned NumElts = VT.getVectorNumElements();
6572 SDValue InVec0 = DAG.getUNDEF(VT);
6573 SDValue InVec1 = DAG.getUNDEF(VT);
6575 assert((VT == MVT::v8f32 || VT == MVT::v4f64 || VT == MVT::v4f32 ||
6576 VT == MVT::v2f64) && "build_vector with an invalid type found!");
6578 // Odd-numbered elements in the input build vector are obtained from
6579 // adding two integer/float elements.
6580 // Even-numbered elements in the input build vector are obtained from
6581 // subtracting two integer/float elements.
6582 unsigned ExpectedOpcode = ISD::FSUB;
6583 unsigned NextExpectedOpcode = ISD::FADD;
6584 bool AddFound = false;
6585 bool SubFound = false;
6587 for (unsigned i = 0, e = NumElts; i != e; i++) {
6588 SDValue Op = BV->getOperand(i);
6590 // Skip 'undef' values.
6591 unsigned Opcode = Op.getOpcode();
6592 if (Opcode == ISD::UNDEF) {
6593 std::swap(ExpectedOpcode, NextExpectedOpcode);
6597 // Early exit if we found an unexpected opcode.
6598 if (Opcode != ExpectedOpcode)
6601 SDValue Op0 = Op.getOperand(0);
6602 SDValue Op1 = Op.getOperand(1);
6604 // Try to match the following pattern:
6605 // (BINOP (extract_vector_elt A, i), (extract_vector_elt B, i))
6606 // Early exit if we cannot match that sequence.
6607 if (Op0.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
6608 Op1.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
6609 !isa<ConstantSDNode>(Op0.getOperand(1)) ||
6610 !isa<ConstantSDNode>(Op1.getOperand(1)) ||
6611 Op0.getOperand(1) != Op1.getOperand(1))
6614 unsigned I0 = cast<ConstantSDNode>(Op0.getOperand(1))->getZExtValue();
6618 // We found a valid add/sub node. Update the information accordingly.
6624 // Update InVec0 and InVec1.
6625 if (InVec0.getOpcode() == ISD::UNDEF)
6626 InVec0 = Op0.getOperand(0);
6627 if (InVec1.getOpcode() == ISD::UNDEF)
6628 InVec1 = Op1.getOperand(0);
6630 // Make sure that operands in input to each add/sub node always
6631 // come from a same pair of vectors.
6632 if (InVec0 != Op0.getOperand(0)) {
6633 if (ExpectedOpcode == ISD::FSUB)
6636 // FADD is commutable. Try to commute the operands
6637 // and then test again.
6638 std::swap(Op0, Op1);
6639 if (InVec0 != Op0.getOperand(0))
6643 if (InVec1 != Op1.getOperand(0))
6646 // Update the pair of expected opcodes.
6647 std::swap(ExpectedOpcode, NextExpectedOpcode);
6650 // Don't try to fold this build_vector into an ADDSUB if the inputs are undef.
6651 if (AddFound && SubFound && InVec0.getOpcode() != ISD::UNDEF &&
6652 InVec1.getOpcode() != ISD::UNDEF)
6653 return DAG.getNode(X86ISD::ADDSUB, DL, VT, InVec0, InVec1);
6658 static SDValue PerformBUILD_VECTORCombine(SDNode *N, SelectionDAG &DAG,
6659 const X86Subtarget *Subtarget) {
6661 EVT VT = N->getValueType(0);
6662 unsigned NumElts = VT.getVectorNumElements();
6663 BuildVectorSDNode *BV = cast<BuildVectorSDNode>(N);
6664 SDValue InVec0, InVec1;
6666 // Try to match an ADDSUB.
6667 if ((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
6668 (Subtarget->hasAVX() && (VT == MVT::v8f32 || VT == MVT::v4f64))) {
6669 SDValue Value = matchAddSub(BV, DAG, Subtarget);
6670 if (Value.getNode())
6674 // Try to match horizontal ADD/SUB.
6675 unsigned NumUndefsLO = 0;
6676 unsigned NumUndefsHI = 0;
6677 unsigned Half = NumElts/2;
6679 // Count the number of UNDEF operands in the build_vector in input.
6680 for (unsigned i = 0, e = Half; i != e; ++i)
6681 if (BV->getOperand(i)->getOpcode() == ISD::UNDEF)
6684 for (unsigned i = Half, e = NumElts; i != e; ++i)
6685 if (BV->getOperand(i)->getOpcode() == ISD::UNDEF)
6688 // Early exit if this is either a build_vector of all UNDEFs or all the
6689 // operands but one are UNDEF.
6690 if (NumUndefsLO + NumUndefsHI + 1 >= NumElts)
6693 if ((VT == MVT::v4f32 || VT == MVT::v2f64) && Subtarget->hasSSE3()) {
6694 // Try to match an SSE3 float HADD/HSUB.
6695 if (isHorizontalBinOp(BV, ISD::FADD, DAG, 0, NumElts, InVec0, InVec1))
6696 return DAG.getNode(X86ISD::FHADD, DL, VT, InVec0, InVec1);
6698 if (isHorizontalBinOp(BV, ISD::FSUB, DAG, 0, NumElts, InVec0, InVec1))
6699 return DAG.getNode(X86ISD::FHSUB, DL, VT, InVec0, InVec1);
6700 } else if ((VT == MVT::v4i32 || VT == MVT::v8i16) && Subtarget->hasSSSE3()) {
6701 // Try to match an SSSE3 integer HADD/HSUB.
6702 if (isHorizontalBinOp(BV, ISD::ADD, DAG, 0, NumElts, InVec0, InVec1))
6703 return DAG.getNode(X86ISD::HADD, DL, VT, InVec0, InVec1);
6705 if (isHorizontalBinOp(BV, ISD::SUB, DAG, 0, NumElts, InVec0, InVec1))
6706 return DAG.getNode(X86ISD::HSUB, DL, VT, InVec0, InVec1);
6709 if (!Subtarget->hasAVX())
6712 if ((VT == MVT::v8f32 || VT == MVT::v4f64)) {
6713 // Try to match an AVX horizontal add/sub of packed single/double
6714 // precision floating point values from 256-bit vectors.
6715 SDValue InVec2, InVec3;
6716 if (isHorizontalBinOp(BV, ISD::FADD, DAG, 0, Half, InVec0, InVec1) &&
6717 isHorizontalBinOp(BV, ISD::FADD, DAG, Half, NumElts, InVec2, InVec3) &&
6718 ((InVec0.getOpcode() == ISD::UNDEF ||
6719 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
6720 ((InVec1.getOpcode() == ISD::UNDEF ||
6721 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
6722 return DAG.getNode(X86ISD::FHADD, DL, VT, InVec0, InVec1);
6724 if (isHorizontalBinOp(BV, ISD::FSUB, DAG, 0, Half, InVec0, InVec1) &&
6725 isHorizontalBinOp(BV, ISD::FSUB, DAG, Half, NumElts, InVec2, InVec3) &&
6726 ((InVec0.getOpcode() == ISD::UNDEF ||
6727 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
6728 ((InVec1.getOpcode() == ISD::UNDEF ||
6729 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
6730 return DAG.getNode(X86ISD::FHSUB, DL, VT, InVec0, InVec1);
6731 } else if (VT == MVT::v8i32 || VT == MVT::v16i16) {
6732 // Try to match an AVX2 horizontal add/sub of signed integers.
6733 SDValue InVec2, InVec3;
6735 bool CanFold = true;
6737 if (isHorizontalBinOp(BV, ISD::ADD, DAG, 0, Half, InVec0, InVec1) &&
6738 isHorizontalBinOp(BV, ISD::ADD, DAG, Half, NumElts, InVec2, InVec3) &&
6739 ((InVec0.getOpcode() == ISD::UNDEF ||
6740 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
6741 ((InVec1.getOpcode() == ISD::UNDEF ||
6742 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
6743 X86Opcode = X86ISD::HADD;
6744 else if (isHorizontalBinOp(BV, ISD::SUB, DAG, 0, Half, InVec0, InVec1) &&
6745 isHorizontalBinOp(BV, ISD::SUB, DAG, Half, NumElts, InVec2, InVec3) &&
6746 ((InVec0.getOpcode() == ISD::UNDEF ||
6747 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
6748 ((InVec1.getOpcode() == ISD::UNDEF ||
6749 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
6750 X86Opcode = X86ISD::HSUB;
6755 // Fold this build_vector into a single horizontal add/sub.
6756 // Do this only if the target has AVX2.
6757 if (Subtarget->hasAVX2())
6758 return DAG.getNode(X86Opcode, DL, VT, InVec0, InVec1);
6760 // Do not try to expand this build_vector into a pair of horizontal
6761 // add/sub if we can emit a pair of scalar add/sub.
6762 if (NumUndefsLO + 1 == Half || NumUndefsHI + 1 == Half)
6765 // Convert this build_vector into a pair of horizontal binop followed by
6767 bool isUndefLO = NumUndefsLO == Half;
6768 bool isUndefHI = NumUndefsHI == Half;
6769 return ExpandHorizontalBinOp(InVec0, InVec1, DL, DAG, X86Opcode, false,
6770 isUndefLO, isUndefHI);
6774 if ((VT == MVT::v8f32 || VT == MVT::v4f64 || VT == MVT::v8i32 ||
6775 VT == MVT::v16i16) && Subtarget->hasAVX()) {
6777 if (isHorizontalBinOp(BV, ISD::ADD, DAG, 0, NumElts, InVec0, InVec1))
6778 X86Opcode = X86ISD::HADD;
6779 else if (isHorizontalBinOp(BV, ISD::SUB, DAG, 0, NumElts, InVec0, InVec1))
6780 X86Opcode = X86ISD::HSUB;
6781 else if (isHorizontalBinOp(BV, ISD::FADD, DAG, 0, NumElts, InVec0, InVec1))
6782 X86Opcode = X86ISD::FHADD;
6783 else if (isHorizontalBinOp(BV, ISD::FSUB, DAG, 0, NumElts, InVec0, InVec1))
6784 X86Opcode = X86ISD::FHSUB;
6788 // Don't try to expand this build_vector into a pair of horizontal add/sub
6789 // if we can simply emit a pair of scalar add/sub.
6790 if (NumUndefsLO + 1 == Half || NumUndefsHI + 1 == Half)
6793 // Convert this build_vector into two horizontal add/sub followed by
6795 bool isUndefLO = NumUndefsLO == Half;
6796 bool isUndefHI = NumUndefsHI == Half;
6797 return ExpandHorizontalBinOp(InVec0, InVec1, DL, DAG, X86Opcode, true,
6798 isUndefLO, isUndefHI);
6805 X86TargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const {
6808 MVT VT = Op.getSimpleValueType();
6809 MVT ExtVT = VT.getVectorElementType();
6810 unsigned NumElems = Op.getNumOperands();
6812 // Generate vectors for predicate vectors.
6813 if (VT.getScalarType() == MVT::i1 && Subtarget->hasAVX512())
6814 return LowerBUILD_VECTORvXi1(Op, DAG);
6816 // Vectors containing all zeros can be matched by pxor and xorps later
6817 if (ISD::isBuildVectorAllZeros(Op.getNode())) {
6818 // Canonicalize this to <4 x i32> to 1) ensure the zero vectors are CSE'd
6819 // and 2) ensure that i64 scalars are eliminated on x86-32 hosts.
6820 if (VT == MVT::v4i32 || VT == MVT::v8i32 || VT == MVT::v16i32)
6823 return getZeroVector(VT, Subtarget, DAG, dl);
6826 // Vectors containing all ones can be matched by pcmpeqd on 128-bit width
6827 // vectors or broken into v4i32 operations on 256-bit vectors. AVX2 can use
6828 // vpcmpeqd on 256-bit vectors.
6829 if (Subtarget->hasSSE2() && ISD::isBuildVectorAllOnes(Op.getNode())) {
6830 if (VT == MVT::v4i32 || (VT == MVT::v8i32 && Subtarget->hasInt256()))
6833 if (!VT.is512BitVector())
6834 return getOnesVector(VT, Subtarget->hasInt256(), DAG, dl);
6837 SDValue Broadcast = LowerVectorBroadcast(Op, Subtarget, DAG);
6838 if (Broadcast.getNode())
6841 unsigned EVTBits = ExtVT.getSizeInBits();
6843 unsigned NumZero = 0;
6844 unsigned NumNonZero = 0;
6845 unsigned NonZeros = 0;
6846 bool IsAllConstants = true;
6847 SmallSet<SDValue, 8> Values;
6848 for (unsigned i = 0; i < NumElems; ++i) {
6849 SDValue Elt = Op.getOperand(i);
6850 if (Elt.getOpcode() == ISD::UNDEF)
6853 if (Elt.getOpcode() != ISD::Constant &&
6854 Elt.getOpcode() != ISD::ConstantFP)
6855 IsAllConstants = false;
6856 if (X86::isZeroNode(Elt))
6859 NonZeros |= (1 << i);
6864 // All undef vector. Return an UNDEF. All zero vectors were handled above.
6865 if (NumNonZero == 0)
6866 return DAG.getUNDEF(VT);
6868 // Special case for single non-zero, non-undef, element.
6869 if (NumNonZero == 1) {
6870 unsigned Idx = countTrailingZeros(NonZeros);
6871 SDValue Item = Op.getOperand(Idx);
6873 // If this is an insertion of an i64 value on x86-32, and if the top bits of
6874 // the value are obviously zero, truncate the value to i32 and do the
6875 // insertion that way. Only do this if the value is non-constant or if the
6876 // value is a constant being inserted into element 0. It is cheaper to do
6877 // a constant pool load than it is to do a movd + shuffle.
6878 if (ExtVT == MVT::i64 && !Subtarget->is64Bit() &&
6879 (!IsAllConstants || Idx == 0)) {
6880 if (DAG.MaskedValueIsZero(Item, APInt::getBitsSet(64, 32, 64))) {
6882 assert(VT == MVT::v2i64 && "Expected an SSE value type!");
6883 EVT VecVT = MVT::v4i32;
6884 unsigned VecElts = 4;
6886 // Truncate the value (which may itself be a constant) to i32, and
6887 // convert it to a vector with movd (S2V+shuffle to zero extend).
6888 Item = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Item);
6889 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Item);
6891 // If using the new shuffle lowering, just directly insert this.
6892 if (ExperimentalVectorShuffleLowering)
6894 ISD::BITCAST, dl, VT,
6895 getShuffleVectorZeroOrUndef(Item, Idx * 2, true, Subtarget, DAG));
6897 Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
6899 // Now we have our 32-bit value zero extended in the low element of
6900 // a vector. If Idx != 0, swizzle it into place.
6902 SmallVector<int, 4> Mask;
6903 Mask.push_back(Idx);
6904 for (unsigned i = 1; i != VecElts; ++i)
6906 Item = DAG.getVectorShuffle(VecVT, dl, Item, DAG.getUNDEF(VecVT),
6909 return DAG.getNode(ISD::BITCAST, dl, VT, Item);
6913 // If we have a constant or non-constant insertion into the low element of
6914 // a vector, we can do this with SCALAR_TO_VECTOR + shuffle of zero into
6915 // the rest of the elements. This will be matched as movd/movq/movss/movsd
6916 // depending on what the source datatype is.
6919 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
6921 if (ExtVT == MVT::i32 || ExtVT == MVT::f32 || ExtVT == MVT::f64 ||
6922 (ExtVT == MVT::i64 && Subtarget->is64Bit())) {
6923 if (VT.is256BitVector() || VT.is512BitVector()) {
6924 SDValue ZeroVec = getZeroVector(VT, Subtarget, DAG, dl);
6925 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, ZeroVec,
6926 Item, DAG.getIntPtrConstant(0));
6928 assert(VT.is128BitVector() && "Expected an SSE value type!");
6929 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
6930 // Turn it into a MOVL (i.e. movss, movsd, or movd) to a zero vector.
6931 return getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
6934 if (ExtVT == MVT::i16 || ExtVT == MVT::i8) {
6935 Item = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Item);
6936 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, Item);
6937 if (VT.is256BitVector()) {
6938 SDValue ZeroVec = getZeroVector(MVT::v8i32, Subtarget, DAG, dl);
6939 Item = Insert128BitVector(ZeroVec, Item, 0, DAG, dl);
6941 assert(VT.is128BitVector() && "Expected an SSE value type!");
6942 Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
6944 return DAG.getNode(ISD::BITCAST, dl, VT, Item);
6948 // Is it a vector logical left shift?
6949 if (NumElems == 2 && Idx == 1 &&
6950 X86::isZeroNode(Op.getOperand(0)) &&
6951 !X86::isZeroNode(Op.getOperand(1))) {
6952 unsigned NumBits = VT.getSizeInBits();
6953 return getVShift(true, VT,
6954 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
6955 VT, Op.getOperand(1)),
6956 NumBits/2, DAG, *this, dl);
6959 if (IsAllConstants) // Otherwise, it's better to do a constpool load.
6962 // Otherwise, if this is a vector with i32 or f32 elements, and the element
6963 // is a non-constant being inserted into an element other than the low one,
6964 // we can't use a constant pool load. Instead, use SCALAR_TO_VECTOR (aka
6965 // movd/movss) to move this into the low element, then shuffle it into
6967 if (EVTBits == 32) {
6968 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
6970 // If using the new shuffle lowering, just directly insert this.
6971 if (ExperimentalVectorShuffleLowering)
6972 return getShuffleVectorZeroOrUndef(Item, Idx, NumZero > 0, Subtarget, DAG);
6974 // Turn it into a shuffle of zero and zero-extended scalar to vector.
6975 Item = getShuffleVectorZeroOrUndef(Item, 0, NumZero > 0, Subtarget, DAG);
6976 SmallVector<int, 8> MaskVec;
6977 for (unsigned i = 0; i != NumElems; ++i)
6978 MaskVec.push_back(i == Idx ? 0 : 1);
6979 return DAG.getVectorShuffle(VT, dl, Item, DAG.getUNDEF(VT), &MaskVec[0]);
6983 // Splat is obviously ok. Let legalizer expand it to a shuffle.
6984 if (Values.size() == 1) {
6985 if (EVTBits == 32) {
6986 // Instead of a shuffle like this:
6987 // shuffle (scalar_to_vector (load (ptr + 4))), undef, <0, 0, 0, 0>
6988 // Check if it's possible to issue this instead.
6989 // shuffle (vload ptr)), undef, <1, 1, 1, 1>
6990 unsigned Idx = countTrailingZeros(NonZeros);
6991 SDValue Item = Op.getOperand(Idx);
6992 if (Op.getNode()->isOnlyUserOf(Item.getNode()))
6993 return LowerAsSplatVectorLoad(Item, VT, dl, DAG);
6998 // A vector full of immediates; various special cases are already
6999 // handled, so this is best done with a single constant-pool load.
7003 // For AVX-length vectors, build the individual 128-bit pieces and use
7004 // shuffles to put them in place.
7005 if (VT.is256BitVector() || VT.is512BitVector()) {
7006 SmallVector<SDValue, 64> V;
7007 for (unsigned i = 0; i != NumElems; ++i)
7008 V.push_back(Op.getOperand(i));
7010 EVT HVT = EVT::getVectorVT(*DAG.getContext(), ExtVT, NumElems/2);
7012 // Build both the lower and upper subvector.
7013 SDValue Lower = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT,
7014 makeArrayRef(&V[0], NumElems/2));
7015 SDValue Upper = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT,
7016 makeArrayRef(&V[NumElems / 2], NumElems/2));
7018 // Recreate the wider vector with the lower and upper part.
7019 if (VT.is256BitVector())
7020 return Concat128BitVectors(Lower, Upper, VT, NumElems, DAG, dl);
7021 return Concat256BitVectors(Lower, Upper, VT, NumElems, DAG, dl);
7024 // Let legalizer expand 2-wide build_vectors.
7025 if (EVTBits == 64) {
7026 if (NumNonZero == 1) {
7027 // One half is zero or undef.
7028 unsigned Idx = countTrailingZeros(NonZeros);
7029 SDValue V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT,
7030 Op.getOperand(Idx));
7031 return getShuffleVectorZeroOrUndef(V2, Idx, true, Subtarget, DAG);
7036 // If element VT is < 32 bits, convert it to inserts into a zero vector.
7037 if (EVTBits == 8 && NumElems == 16) {
7038 SDValue V = LowerBuildVectorv16i8(Op, NonZeros,NumNonZero,NumZero, DAG,
7040 if (V.getNode()) return V;
7043 if (EVTBits == 16 && NumElems == 8) {
7044 SDValue V = LowerBuildVectorv8i16(Op, NonZeros,NumNonZero,NumZero, DAG,
7046 if (V.getNode()) return V;
7049 // If element VT is == 32 bits and has 4 elems, try to generate an INSERTPS
7050 if (EVTBits == 32 && NumElems == 4) {
7051 SDValue V = LowerBuildVectorv4x32(Op, DAG, Subtarget, *this);
7056 // If element VT is == 32 bits, turn it into a number of shuffles.
7057 SmallVector<SDValue, 8> V(NumElems);
7058 if (NumElems == 4 && NumZero > 0) {
7059 for (unsigned i = 0; i < 4; ++i) {
7060 bool isZero = !(NonZeros & (1 << i));
7062 V[i] = getZeroVector(VT, Subtarget, DAG, dl);
7064 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
7067 for (unsigned i = 0; i < 2; ++i) {
7068 switch ((NonZeros & (0x3 << i*2)) >> (i*2)) {
7071 V[i] = V[i*2]; // Must be a zero vector.
7074 V[i] = getMOVL(DAG, dl, VT, V[i*2+1], V[i*2]);
7077 V[i] = getMOVL(DAG, dl, VT, V[i*2], V[i*2+1]);
7080 V[i] = getUnpackl(DAG, dl, VT, V[i*2], V[i*2+1]);
7085 bool Reverse1 = (NonZeros & 0x3) == 2;
7086 bool Reverse2 = ((NonZeros & (0x3 << 2)) >> 2) == 2;
7090 static_cast<int>(Reverse2 ? NumElems+1 : NumElems),
7091 static_cast<int>(Reverse2 ? NumElems : NumElems+1)
7093 return DAG.getVectorShuffle(VT, dl, V[0], V[1], &MaskVec[0]);
7096 if (Values.size() > 1 && VT.is128BitVector()) {
7097 // Check for a build vector of consecutive loads.
7098 for (unsigned i = 0; i < NumElems; ++i)
7099 V[i] = Op.getOperand(i);
7101 // Check for elements which are consecutive loads.
7102 SDValue LD = EltsFromConsecutiveLoads(VT, V, dl, DAG, false);
7106 // Check for a build vector from mostly shuffle plus few inserting.
7107 SDValue Sh = buildFromShuffleMostly(Op, DAG);
7111 // For SSE 4.1, use insertps to put the high elements into the low element.
7112 if (getSubtarget()->hasSSE41()) {
7114 if (Op.getOperand(0).getOpcode() != ISD::UNDEF)
7115 Result = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(0));
7117 Result = DAG.getUNDEF(VT);
7119 for (unsigned i = 1; i < NumElems; ++i) {
7120 if (Op.getOperand(i).getOpcode() == ISD::UNDEF) continue;
7121 Result = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Result,
7122 Op.getOperand(i), DAG.getIntPtrConstant(i));
7127 // Otherwise, expand into a number of unpckl*, start by extending each of
7128 // our (non-undef) elements to the full vector width with the element in the
7129 // bottom slot of the vector (which generates no code for SSE).
7130 for (unsigned i = 0; i < NumElems; ++i) {
7131 if (Op.getOperand(i).getOpcode() != ISD::UNDEF)
7132 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
7134 V[i] = DAG.getUNDEF(VT);
7137 // Next, we iteratively mix elements, e.g. for v4f32:
7138 // Step 1: unpcklps 0, 2 ==> X: <?, ?, 2, 0>
7139 // : unpcklps 1, 3 ==> Y: <?, ?, 3, 1>
7140 // Step 2: unpcklps X, Y ==> <3, 2, 1, 0>
7141 unsigned EltStride = NumElems >> 1;
7142 while (EltStride != 0) {
7143 for (unsigned i = 0; i < EltStride; ++i) {
7144 // If V[i+EltStride] is undef and this is the first round of mixing,
7145 // then it is safe to just drop this shuffle: V[i] is already in the
7146 // right place, the one element (since it's the first round) being
7147 // inserted as undef can be dropped. This isn't safe for successive
7148 // rounds because they will permute elements within both vectors.
7149 if (V[i+EltStride].getOpcode() == ISD::UNDEF &&
7150 EltStride == NumElems/2)
7153 V[i] = getUnpackl(DAG, dl, VT, V[i], V[i + EltStride]);
7162 // LowerAVXCONCAT_VECTORS - 256-bit AVX can use the vinsertf128 instruction
7163 // to create 256-bit vectors from two other 128-bit ones.
7164 static SDValue LowerAVXCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
7166 MVT ResVT = Op.getSimpleValueType();
7168 assert((ResVT.is256BitVector() ||
7169 ResVT.is512BitVector()) && "Value type must be 256-/512-bit wide");
7171 SDValue V1 = Op.getOperand(0);
7172 SDValue V2 = Op.getOperand(1);
7173 unsigned NumElems = ResVT.getVectorNumElements();
7174 if(ResVT.is256BitVector())
7175 return Concat128BitVectors(V1, V2, ResVT, NumElems, DAG, dl);
7177 if (Op.getNumOperands() == 4) {
7178 MVT HalfVT = MVT::getVectorVT(ResVT.getScalarType(),
7179 ResVT.getVectorNumElements()/2);
7180 SDValue V3 = Op.getOperand(2);
7181 SDValue V4 = Op.getOperand(3);
7182 return Concat256BitVectors(Concat128BitVectors(V1, V2, HalfVT, NumElems/2, DAG, dl),
7183 Concat128BitVectors(V3, V4, HalfVT, NumElems/2, DAG, dl), ResVT, NumElems, DAG, dl);
7185 return Concat256BitVectors(V1, V2, ResVT, NumElems, DAG, dl);
7188 static SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
7189 MVT LLVM_ATTRIBUTE_UNUSED VT = Op.getSimpleValueType();
7190 assert((VT.is256BitVector() && Op.getNumOperands() == 2) ||
7191 (VT.is512BitVector() && (Op.getNumOperands() == 2 ||
7192 Op.getNumOperands() == 4)));
7194 // AVX can use the vinsertf128 instruction to create 256-bit vectors
7195 // from two other 128-bit ones.
7197 // 512-bit vector may contain 2 256-bit vectors or 4 128-bit vectors
7198 return LowerAVXCONCAT_VECTORS(Op, DAG);
7202 //===----------------------------------------------------------------------===//
7203 // Vector shuffle lowering
7205 // This is an experimental code path for lowering vector shuffles on x86. It is
7206 // designed to handle arbitrary vector shuffles and blends, gracefully
7207 // degrading performance as necessary. It works hard to recognize idiomatic
7208 // shuffles and lower them to optimal instruction patterns without leaving
7209 // a framework that allows reasonably efficient handling of all vector shuffle
7211 //===----------------------------------------------------------------------===//
7213 /// \brief Tiny helper function to identify a no-op mask.
7215 /// This is a somewhat boring predicate function. It checks whether the mask
7216 /// array input, which is assumed to be a single-input shuffle mask of the kind
7217 /// used by the X86 shuffle instructions (not a fully general
7218 /// ShuffleVectorSDNode mask) requires any shuffles to occur. Both undef and an
7219 /// in-place shuffle are 'no-op's.
7220 static bool isNoopShuffleMask(ArrayRef<int> Mask) {
7221 for (int i = 0, Size = Mask.size(); i < Size; ++i)
7222 if (Mask[i] != -1 && Mask[i] != i)
7227 /// \brief Helper function to classify a mask as a single-input mask.
7229 /// This isn't a generic single-input test because in the vector shuffle
7230 /// lowering we canonicalize single inputs to be the first input operand. This
7231 /// means we can more quickly test for a single input by only checking whether
7232 /// an input from the second operand exists. We also assume that the size of
7233 /// mask corresponds to the size of the input vectors which isn't true in the
7234 /// fully general case.
7235 static bool isSingleInputShuffleMask(ArrayRef<int> Mask) {
7237 if (M >= (int)Mask.size())
7242 /// \brief Test whether there are elements crossing 128-bit lanes in this
7245 /// X86 divides up its shuffles into in-lane and cross-lane shuffle operations
7246 /// and we routinely test for these.
7247 static bool is128BitLaneCrossingShuffleMask(MVT VT, ArrayRef<int> Mask) {
7248 int LaneSize = 128 / VT.getScalarSizeInBits();
7249 int Size = Mask.size();
7250 for (int i = 0; i < Size; ++i)
7251 if (Mask[i] >= 0 && (Mask[i] % Size) / LaneSize != i / LaneSize)
7256 /// \brief Test whether a shuffle mask is equivalent within each 128-bit lane.
7258 /// This checks a shuffle mask to see if it is performing the same
7259 /// 128-bit lane-relative shuffle in each 128-bit lane. This trivially implies
7260 /// that it is also not lane-crossing. It may however involve a blend from the
7261 /// same lane of a second vector.
7263 /// The specific repeated shuffle mask is populated in \p RepeatedMask, as it is
7264 /// non-trivial to compute in the face of undef lanes. The representation is
7265 /// *not* suitable for use with existing 128-bit shuffles as it will contain
7266 /// entries from both V1 and V2 inputs to the wider mask.
7268 is128BitLaneRepeatedShuffleMask(MVT VT, ArrayRef<int> Mask,
7269 SmallVectorImpl<int> &RepeatedMask) {
7270 int LaneSize = 128 / VT.getScalarSizeInBits();
7271 RepeatedMask.resize(LaneSize, -1);
7272 int Size = Mask.size();
7273 for (int i = 0; i < Size; ++i) {
7276 if ((Mask[i] % Size) / LaneSize != i / LaneSize)
7277 // This entry crosses lanes, so there is no way to model this shuffle.
7280 // Ok, handle the in-lane shuffles by detecting if and when they repeat.
7281 if (RepeatedMask[i % LaneSize] == -1)
7282 // This is the first non-undef entry in this slot of a 128-bit lane.
7283 RepeatedMask[i % LaneSize] =
7284 Mask[i] < Size ? Mask[i] % LaneSize : Mask[i] % LaneSize + Size;
7285 else if (RepeatedMask[i % LaneSize] + (i / LaneSize) * LaneSize != Mask[i])
7286 // Found a mismatch with the repeated mask.
7292 // Hide this symbol with an anonymous namespace instead of 'static' so that MSVC
7293 // 2013 will allow us to use it as a non-type template parameter.
7296 /// \brief Implementation of the \c isShuffleEquivalent variadic functor.
7298 /// See its documentation for details.
7299 bool isShuffleEquivalentImpl(ArrayRef<int> Mask, ArrayRef<const int *> Args) {
7300 if (Mask.size() != Args.size())
7302 for (int i = 0, e = Mask.size(); i < e; ++i) {
7303 assert(*Args[i] >= 0 && "Arguments must be positive integers!");
7304 if (Mask[i] != -1 && Mask[i] != *Args[i])
7312 /// \brief Checks whether a shuffle mask is equivalent to an explicit list of
7315 /// This is a fast way to test a shuffle mask against a fixed pattern:
7317 /// if (isShuffleEquivalent(Mask, 3, 2, 1, 0)) { ... }
7319 /// It returns true if the mask is exactly as wide as the argument list, and
7320 /// each element of the mask is either -1 (signifying undef) or the value given
7321 /// in the argument.
7322 static const VariadicFunction1<
7323 bool, ArrayRef<int>, int, isShuffleEquivalentImpl> isShuffleEquivalent = {};
7325 /// \brief Get a 4-lane 8-bit shuffle immediate for a mask.
7327 /// This helper function produces an 8-bit shuffle immediate corresponding to
7328 /// the ubiquitous shuffle encoding scheme used in x86 instructions for
7329 /// shuffling 4 lanes. It can be used with most of the PSHUF instructions for
7332 /// NB: We rely heavily on "undef" masks preserving the input lane.
7333 static SDValue getV4X86ShuffleImm8ForMask(ArrayRef<int> Mask,
7334 SelectionDAG &DAG) {
7335 assert(Mask.size() == 4 && "Only 4-lane shuffle masks");
7336 assert(Mask[0] >= -1 && Mask[0] < 4 && "Out of bound mask element!");
7337 assert(Mask[1] >= -1 && Mask[1] < 4 && "Out of bound mask element!");
7338 assert(Mask[2] >= -1 && Mask[2] < 4 && "Out of bound mask element!");
7339 assert(Mask[3] >= -1 && Mask[3] < 4 && "Out of bound mask element!");
7342 Imm |= (Mask[0] == -1 ? 0 : Mask[0]) << 0;
7343 Imm |= (Mask[1] == -1 ? 1 : Mask[1]) << 2;
7344 Imm |= (Mask[2] == -1 ? 2 : Mask[2]) << 4;
7345 Imm |= (Mask[3] == -1 ? 3 : Mask[3]) << 6;
7346 return DAG.getConstant(Imm, MVT::i8);
7349 /// \brief Try to emit a blend instruction for a shuffle.
7351 /// This doesn't do any checks for the availability of instructions for blending
7352 /// these values. It relies on the availability of the X86ISD::BLENDI pattern to
7353 /// be matched in the backend with the type given. What it does check for is
7354 /// that the shuffle mask is in fact a blend.
7355 static SDValue lowerVectorShuffleAsBlend(SDLoc DL, MVT VT, SDValue V1,
7356 SDValue V2, ArrayRef<int> Mask,
7357 const X86Subtarget *Subtarget,
7358 SelectionDAG &DAG) {
7360 unsigned BlendMask = 0;
7361 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
7362 if (Mask[i] >= Size) {
7363 if (Mask[i] != i + Size)
7364 return SDValue(); // Shuffled V2 input!
7365 BlendMask |= 1u << i;
7368 if (Mask[i] >= 0 && Mask[i] != i)
7369 return SDValue(); // Shuffled V1 input!
7371 switch (VT.SimpleTy) {
7376 return DAG.getNode(X86ISD::BLENDI, DL, VT, V1, V2,
7377 DAG.getConstant(BlendMask, MVT::i8));
7381 assert(Subtarget->hasAVX2() && "256-bit integer blends require AVX2!");
7385 // If we have AVX2 it is faster to use VPBLENDD when the shuffle fits into
7386 // that instruction.
7387 if (Subtarget->hasAVX2()) {
7388 // Scale the blend by the number of 32-bit dwords per element.
7389 int Scale = VT.getScalarSizeInBits() / 32;
7391 for (int i = 0, Size = Mask.size(); i < Size; ++i)
7392 if (Mask[i] >= Size)
7393 for (int j = 0; j < Scale; ++j)
7394 BlendMask |= 1u << (i * Scale + j);
7396 MVT BlendVT = VT.getSizeInBits() > 128 ? MVT::v8i32 : MVT::v4i32;
7397 V1 = DAG.getNode(ISD::BITCAST, DL, BlendVT, V1);
7398 V2 = DAG.getNode(ISD::BITCAST, DL, BlendVT, V2);
7399 return DAG.getNode(ISD::BITCAST, DL, VT,
7400 DAG.getNode(X86ISD::BLENDI, DL, BlendVT, V1, V2,
7401 DAG.getConstant(BlendMask, MVT::i8)));
7405 // For integer shuffles we need to expand the mask and cast the inputs to
7406 // v8i16s prior to blending.
7407 int Scale = 8 / VT.getVectorNumElements();
7409 for (int i = 0, Size = Mask.size(); i < Size; ++i)
7410 if (Mask[i] >= Size)
7411 for (int j = 0; j < Scale; ++j)
7412 BlendMask |= 1u << (i * Scale + j);
7414 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V1);
7415 V2 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V2);
7416 return DAG.getNode(ISD::BITCAST, DL, VT,
7417 DAG.getNode(X86ISD::BLENDI, DL, MVT::v8i16, V1, V2,
7418 DAG.getConstant(BlendMask, MVT::i8)));
7422 assert(Subtarget->hasAVX2() && "256-bit integer blends require AVX2!");
7423 SmallVector<int, 8> RepeatedMask;
7424 if (is128BitLaneRepeatedShuffleMask(MVT::v16i16, Mask, RepeatedMask)) {
7425 // We can lower these with PBLENDW which is mirrored across 128-bit lanes.
7426 assert(RepeatedMask.size() == 8 && "Repeated mask size doesn't match!");
7428 for (int i = 0; i < 8; ++i)
7429 if (RepeatedMask[i] >= 16)
7430 BlendMask |= 1u << i;
7431 return DAG.getNode(X86ISD::BLENDI, DL, MVT::v16i16, V1, V2,
7432 DAG.getConstant(BlendMask, MVT::i8));
7437 assert(Subtarget->hasAVX2() && "256-bit integer blends require AVX2!");
7438 // Scale the blend by the number of bytes per element.
7439 int Scale = VT.getScalarSizeInBits() / 8;
7440 assert(Mask.size() * Scale == 32 && "Not a 256-bit vector!");
7442 // Compute the VSELECT mask. Note that VSELECT is really confusing in the
7443 // mix of LLVM's code generator and the x86 backend. We tell the code
7444 // generator that boolean values in the elements of an x86 vector register
7445 // are -1 for true and 0 for false. We then use the LLVM semantics of 'true'
7446 // mapping a select to operand #1, and 'false' mapping to operand #2. The
7447 // reality in x86 is that vector masks (pre-AVX-512) use only the high bit
7448 // of the element (the remaining are ignored) and 0 in that high bit would
7449 // mean operand #1 while 1 in the high bit would mean operand #2. So while
7450 // the LLVM model for boolean values in vector elements gets the relevant
7451 // bit set, it is set backwards and over constrained relative to x86's
7453 SDValue VSELECTMask[32];
7454 for (int i = 0, Size = Mask.size(); i < Size; ++i)
7455 for (int j = 0; j < Scale; ++j)
7456 VSELECTMask[Scale * i + j] =
7457 Mask[i] < 0 ? DAG.getUNDEF(MVT::i8)
7458 : DAG.getConstant(Mask[i] < Size ? -1 : 0, MVT::i8);
7460 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v32i8, V1);
7461 V2 = DAG.getNode(ISD::BITCAST, DL, MVT::v32i8, V2);
7463 ISD::BITCAST, DL, VT,
7464 DAG.getNode(ISD::VSELECT, DL, MVT::v32i8,
7465 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v32i8, VSELECTMask),
7470 llvm_unreachable("Not a supported integer vector type!");
7474 /// \brief Generic routine to lower a shuffle and blend as a decomposed set of
7475 /// unblended shuffles followed by an unshuffled blend.
7477 /// This matches the extremely common pattern for handling combined
7478 /// shuffle+blend operations on newer X86 ISAs where we have very fast blend
7480 static SDValue lowerVectorShuffleAsDecomposedShuffleBlend(SDLoc DL, MVT VT,
7484 SelectionDAG &DAG) {
7485 // Shuffle the input elements into the desired positions in V1 and V2 and
7486 // blend them together.
7487 SmallVector<int, 32> V1Mask(Mask.size(), -1);
7488 SmallVector<int, 32> V2Mask(Mask.size(), -1);
7489 SmallVector<int, 32> BlendMask(Mask.size(), -1);
7490 for (int i = 0, Size = Mask.size(); i < Size; ++i)
7491 if (Mask[i] >= 0 && Mask[i] < Size) {
7492 V1Mask[i] = Mask[i];
7494 } else if (Mask[i] >= Size) {
7495 V2Mask[i] = Mask[i] - Size;
7496 BlendMask[i] = i + Size;
7499 V1 = DAG.getVectorShuffle(VT, DL, V1, DAG.getUNDEF(VT), V1Mask);
7500 V2 = DAG.getVectorShuffle(VT, DL, V2, DAG.getUNDEF(VT), V2Mask);
7501 return DAG.getVectorShuffle(VT, DL, V1, V2, BlendMask);
7504 /// \brief Try to lower a vector shuffle as a byte rotation.
7506 /// SSSE3 has a generic PALIGNR instruction in x86 that will do an arbitrary
7507 /// byte-rotation of the concatenation of two vectors; pre-SSSE3 can use
7508 /// a PSRLDQ/PSLLDQ/POR pattern to get a similar effect. This routine will
7509 /// try to generically lower a vector shuffle through such an pattern. It
7510 /// does not check for the profitability of lowering either as PALIGNR or
7511 /// PSRLDQ/PSLLDQ/POR, only whether the mask is valid to lower in that form.
7512 /// This matches shuffle vectors that look like:
7514 /// v8i16 [11, 12, 13, 14, 15, 0, 1, 2]
7516 /// Essentially it concatenates V1 and V2, shifts right by some number of
7517 /// elements, and takes the low elements as the result. Note that while this is
7518 /// specified as a *right shift* because x86 is little-endian, it is a *left
7519 /// rotate* of the vector lanes.
7521 /// Note that this only handles 128-bit vector widths currently.
7522 static SDValue lowerVectorShuffleAsByteRotate(SDLoc DL, MVT VT, SDValue V1,
7525 const X86Subtarget *Subtarget,
7526 SelectionDAG &DAG) {
7527 assert(!isNoopShuffleMask(Mask) && "We shouldn't lower no-op shuffles!");
7529 // We need to detect various ways of spelling a rotation:
7530 // [11, 12, 13, 14, 15, 0, 1, 2]
7531 // [-1, 12, 13, 14, -1, -1, 1, -1]
7532 // [-1, -1, -1, -1, -1, -1, 1, 2]
7533 // [ 3, 4, 5, 6, 7, 8, 9, 10]
7534 // [-1, 4, 5, 6, -1, -1, 9, -1]
7535 // [-1, 4, 5, 6, -1, -1, -1, -1]
7538 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
7541 assert(Mask[i] >= 0 && "Only -1 is a valid negative mask element!");
7543 // Based on the mod-Size value of this mask element determine where
7544 // a rotated vector would have started.
7545 int StartIdx = i - (Mask[i] % Size);
7547 // The identity rotation isn't interesting, stop.
7550 // If we found the tail of a vector the rotation must be the missing
7551 // front. If we found the head of a vector, it must be how much of the head.
7552 int CandidateRotation = StartIdx < 0 ? -StartIdx : Size - StartIdx;
7555 Rotation = CandidateRotation;
7556 else if (Rotation != CandidateRotation)
7557 // The rotations don't match, so we can't match this mask.
7560 // Compute which value this mask is pointing at.
7561 SDValue MaskV = Mask[i] < Size ? V1 : V2;
7563 // Compute which of the two target values this index should be assigned to.
7564 // This reflects whether the high elements are remaining or the low elements
7566 SDValue &TargetV = StartIdx < 0 ? Hi : Lo;
7568 // Either set up this value if we've not encountered it before, or check
7569 // that it remains consistent.
7572 else if (TargetV != MaskV)
7573 // This may be a rotation, but it pulls from the inputs in some
7574 // unsupported interleaving.
7578 // Check that we successfully analyzed the mask, and normalize the results.
7579 assert(Rotation != 0 && "Failed to locate a viable rotation!");
7580 assert((Lo || Hi) && "Failed to find a rotated input vector!");
7586 assert(VT.getSizeInBits() == 128 &&
7587 "Rotate-based lowering only supports 128-bit lowering!");
7588 assert(Mask.size() <= 16 &&
7589 "Can shuffle at most 16 bytes in a 128-bit vector!");
7591 // The actual rotate instruction rotates bytes, so we need to scale the
7592 // rotation based on how many bytes are in the vector.
7593 int Scale = 16 / Mask.size();
7595 // SSSE3 targets can use the palignr instruction
7596 if (Subtarget->hasSSSE3()) {
7597 // Cast the inputs to v16i8 to match PALIGNR.
7598 Lo = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, Lo);
7599 Hi = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, Hi);
7601 return DAG.getNode(ISD::BITCAST, DL, VT,
7602 DAG.getNode(X86ISD::PALIGNR, DL, MVT::v16i8, Hi, Lo,
7603 DAG.getConstant(Rotation * Scale, MVT::i8)));
7606 // Default SSE2 implementation
7607 int LoByteShift = 16 - Rotation * Scale;
7608 int HiByteShift = Rotation * Scale;
7610 // Cast the inputs to v2i64 to match PSLLDQ/PSRLDQ.
7611 Lo = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, Lo);
7612 Hi = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, Hi);
7614 SDValue LoShift = DAG.getNode(X86ISD::VSHLDQ, DL, MVT::v2i64, Lo,
7615 DAG.getConstant(8 * LoByteShift, MVT::i8));
7616 SDValue HiShift = DAG.getNode(X86ISD::VSRLDQ, DL, MVT::v2i64, Hi,
7617 DAG.getConstant(8 * HiByteShift, MVT::i8));
7618 return DAG.getNode(ISD::BITCAST, DL, VT,
7619 DAG.getNode(ISD::OR, DL, MVT::v2i64, LoShift, HiShift));
7622 /// \brief Compute whether each element of a shuffle is zeroable.
7624 /// A "zeroable" vector shuffle element is one which can be lowered to zero.
7625 /// Either it is an undef element in the shuffle mask, the element of the input
7626 /// referenced is undef, or the element of the input referenced is known to be
7627 /// zero. Many x86 shuffles can zero lanes cheaply and we often want to handle
7628 /// as many lanes with this technique as possible to simplify the remaining
7630 static SmallBitVector computeZeroableShuffleElements(ArrayRef<int> Mask,
7631 SDValue V1, SDValue V2) {
7632 SmallBitVector Zeroable(Mask.size(), false);
7634 bool V1IsZero = ISD::isBuildVectorAllZeros(V1.getNode());
7635 bool V2IsZero = ISD::isBuildVectorAllZeros(V2.getNode());
7637 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
7639 // Handle the easy cases.
7640 if (M < 0 || (M >= 0 && M < Size && V1IsZero) || (M >= Size && V2IsZero)) {
7645 // If this is an index into a build_vector node, dig out the input value and
7647 SDValue V = M < Size ? V1 : V2;
7648 if (V.getOpcode() != ISD::BUILD_VECTOR)
7651 SDValue Input = V.getOperand(M % Size);
7652 // The UNDEF opcode check really should be dead code here, but not quite
7653 // worth asserting on (it isn't invalid, just unexpected).
7654 if (Input.getOpcode() == ISD::UNDEF || X86::isZeroNode(Input))
7661 /// \brief Try to lower a vector shuffle as a byte shift (shifts in zeros).
7663 /// Attempts to match a shuffle mask against the PSRLDQ and PSLLDQ SSE2
7664 /// byte-shift instructions. The mask must consist of a shifted sequential
7665 /// shuffle from one of the input vectors and zeroable elements for the
7666 /// remaining 'shifted in' elements.
7668 /// Note that this only handles 128-bit vector widths currently.
7669 static SDValue lowerVectorShuffleAsByteShift(SDLoc DL, MVT VT, SDValue V1,
7670 SDValue V2, ArrayRef<int> Mask,
7671 SelectionDAG &DAG) {
7672 assert(!isNoopShuffleMask(Mask) && "We shouldn't lower no-op shuffles!");
7674 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
7676 int Size = Mask.size();
7677 int Scale = 16 / Size;
7679 auto isSequential = [](int Base, int StartIndex, int EndIndex, int MaskOffset,
7680 ArrayRef<int> Mask) {
7681 for (int i = StartIndex; i < EndIndex; i++) {
7684 if (i + Base != Mask[i] - MaskOffset)
7690 for (int Shift = 1; Shift < Size; Shift++) {
7691 int ByteShift = Shift * Scale;
7693 // PSRLDQ : (little-endian) right byte shift
7694 // [ 5, 6, 7, zz, zz, zz, zz, zz]
7695 // [ -1, 5, 6, 7, zz, zz, zz, zz]
7696 // [ 1, 2, -1, -1, -1, -1, zz, zz]
7697 bool ZeroableRight = true;
7698 for (int i = Size - Shift; i < Size; i++) {
7699 ZeroableRight &= Zeroable[i];
7702 if (ZeroableRight) {
7703 bool ValidShiftRight1 = isSequential(Shift, 0, Size - Shift, 0, Mask);
7704 bool ValidShiftRight2 = isSequential(Shift, 0, Size - Shift, Size, Mask);
7706 if (ValidShiftRight1 || ValidShiftRight2) {
7707 // Cast the inputs to v2i64 to match PSRLDQ.
7708 SDValue &TargetV = ValidShiftRight1 ? V1 : V2;
7709 SDValue V = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, TargetV);
7710 SDValue Shifted = DAG.getNode(X86ISD::VSRLDQ, DL, MVT::v2i64, V,
7711 DAG.getConstant(ByteShift * 8, MVT::i8));
7712 return DAG.getNode(ISD::BITCAST, DL, VT, Shifted);
7716 // PSLLDQ : (little-endian) left byte shift
7717 // [ zz, 0, 1, 2, 3, 4, 5, 6]
7718 // [ zz, zz, -1, -1, 2, 3, 4, -1]
7719 // [ zz, zz, zz, zz, zz, zz, -1, 1]
7720 bool ZeroableLeft = true;
7721 for (int i = 0; i < Shift; i++) {
7722 ZeroableLeft &= Zeroable[i];
7726 bool ValidShiftLeft1 = isSequential(-Shift, Shift, Size, 0, Mask);
7727 bool ValidShiftLeft2 = isSequential(-Shift, Shift, Size, Size, Mask);
7729 if (ValidShiftLeft1 || ValidShiftLeft2) {
7730 // Cast the inputs to v2i64 to match PSLLDQ.
7731 SDValue &TargetV = ValidShiftLeft1 ? V1 : V2;
7732 SDValue V = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, TargetV);
7733 SDValue Shifted = DAG.getNode(X86ISD::VSHLDQ, DL, MVT::v2i64, V,
7734 DAG.getConstant(ByteShift * 8, MVT::i8));
7735 return DAG.getNode(ISD::BITCAST, DL, VT, Shifted);
7743 /// \brief Lower a vector shuffle as a zero or any extension.
7745 /// Given a specific number of elements, element bit width, and extension
7746 /// stride, produce either a zero or any extension based on the available
7747 /// features of the subtarget.
7748 static SDValue lowerVectorShuffleAsSpecificZeroOrAnyExtend(
7749 SDLoc DL, MVT VT, int NumElements, int Scale, bool AnyExt, SDValue InputV,
7750 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
7751 assert(Scale > 1 && "Need a scale to extend.");
7752 int EltBits = VT.getSizeInBits() / NumElements;
7753 assert((EltBits == 8 || EltBits == 16 || EltBits == 32) &&
7754 "Only 8, 16, and 32 bit elements can be extended.");
7755 assert(Scale * EltBits <= 64 && "Cannot zero extend past 64 bits.");
7757 // Found a valid zext mask! Try various lowering strategies based on the
7758 // input type and available ISA extensions.
7759 if (Subtarget->hasSSE41()) {
7760 MVT InputVT = MVT::getVectorVT(MVT::getIntegerVT(EltBits), NumElements);
7761 MVT ExtVT = MVT::getVectorVT(MVT::getIntegerVT(EltBits * Scale),
7762 NumElements / Scale);
7763 InputV = DAG.getNode(ISD::BITCAST, DL, InputVT, InputV);
7764 return DAG.getNode(ISD::BITCAST, DL, VT,
7765 DAG.getNode(X86ISD::VZEXT, DL, ExtVT, InputV));
7768 // For any extends we can cheat for larger element sizes and use shuffle
7769 // instructions that can fold with a load and/or copy.
7770 if (AnyExt && EltBits == 32) {
7771 int PSHUFDMask[4] = {0, -1, 1, -1};
7773 ISD::BITCAST, DL, VT,
7774 DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32,
7775 DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, InputV),
7776 getV4X86ShuffleImm8ForMask(PSHUFDMask, DAG)));
7778 if (AnyExt && EltBits == 16 && Scale > 2) {
7779 int PSHUFDMask[4] = {0, -1, 0, -1};
7780 InputV = DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32,
7781 DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, InputV),
7782 getV4X86ShuffleImm8ForMask(PSHUFDMask, DAG));
7783 int PSHUFHWMask[4] = {1, -1, -1, -1};
7785 ISD::BITCAST, DL, VT,
7786 DAG.getNode(X86ISD::PSHUFHW, DL, MVT::v8i16,
7787 DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, InputV),
7788 getV4X86ShuffleImm8ForMask(PSHUFHWMask, DAG)));
7791 // If this would require more than 2 unpack instructions to expand, use
7792 // pshufb when available. We can only use more than 2 unpack instructions
7793 // when zero extending i8 elements which also makes it easier to use pshufb.
7794 if (Scale > 4 && EltBits == 8 && Subtarget->hasSSSE3()) {
7795 assert(NumElements == 16 && "Unexpected byte vector width!");
7796 SDValue PSHUFBMask[16];
7797 for (int i = 0; i < 16; ++i)
7799 DAG.getConstant((i % Scale == 0) ? i / Scale : 0x80, MVT::i8);
7800 InputV = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, InputV);
7801 return DAG.getNode(ISD::BITCAST, DL, VT,
7802 DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8, InputV,
7803 DAG.getNode(ISD::BUILD_VECTOR, DL,
7804 MVT::v16i8, PSHUFBMask)));
7807 // Otherwise emit a sequence of unpacks.
7809 MVT InputVT = MVT::getVectorVT(MVT::getIntegerVT(EltBits), NumElements);
7810 SDValue Ext = AnyExt ? DAG.getUNDEF(InputVT)
7811 : getZeroVector(InputVT, Subtarget, DAG, DL);
7812 InputV = DAG.getNode(ISD::BITCAST, DL, InputVT, InputV);
7813 InputV = DAG.getNode(X86ISD::UNPCKL, DL, InputVT, InputV, Ext);
7817 } while (Scale > 1);
7818 return DAG.getNode(ISD::BITCAST, DL, VT, InputV);
7821 /// \brief Try to lower a vector shuffle as a zero extension on any micrarch.
7823 /// This routine will try to do everything in its power to cleverly lower
7824 /// a shuffle which happens to match the pattern of a zero extend. It doesn't
7825 /// check for the profitability of this lowering, it tries to aggressively
7826 /// match this pattern. It will use all of the micro-architectural details it
7827 /// can to emit an efficient lowering. It handles both blends with all-zero
7828 /// inputs to explicitly zero-extend and undef-lanes (sometimes undef due to
7829 /// masking out later).
7831 /// The reason we have dedicated lowering for zext-style shuffles is that they
7832 /// are both incredibly common and often quite performance sensitive.
7833 static SDValue lowerVectorShuffleAsZeroOrAnyExtend(
7834 SDLoc DL, MVT VT, SDValue V1, SDValue V2, ArrayRef<int> Mask,
7835 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
7836 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
7838 int Bits = VT.getSizeInBits();
7839 int NumElements = Mask.size();
7841 // Define a helper function to check a particular ext-scale and lower to it if
7843 auto Lower = [&](int Scale) -> SDValue {
7846 for (int i = 0; i < NumElements; ++i) {
7848 continue; // Valid anywhere but doesn't tell us anything.
7849 if (i % Scale != 0) {
7850 // Each of the extend elements needs to be zeroable.
7854 // We no lorger are in the anyext case.
7859 // Each of the base elements needs to be consecutive indices into the
7860 // same input vector.
7861 SDValue V = Mask[i] < NumElements ? V1 : V2;
7864 else if (InputV != V)
7865 return SDValue(); // Flip-flopping inputs.
7867 if (Mask[i] % NumElements != i / Scale)
7868 return SDValue(); // Non-consecutive strided elemenst.
7871 // If we fail to find an input, we have a zero-shuffle which should always
7872 // have already been handled.
7873 // FIXME: Maybe handle this here in case during blending we end up with one?
7877 return lowerVectorShuffleAsSpecificZeroOrAnyExtend(
7878 DL, VT, NumElements, Scale, AnyExt, InputV, Subtarget, DAG);
7881 // The widest scale possible for extending is to a 64-bit integer.
7882 assert(Bits % 64 == 0 &&
7883 "The number of bits in a vector must be divisible by 64 on x86!");
7884 int NumExtElements = Bits / 64;
7886 // Each iteration, try extending the elements half as much, but into twice as
7888 for (; NumExtElements < NumElements; NumExtElements *= 2) {
7889 assert(NumElements % NumExtElements == 0 &&
7890 "The input vector size must be divisble by the extended size.");
7891 if (SDValue V = Lower(NumElements / NumExtElements))
7895 // No viable ext lowering found.
7899 /// \brief Try to get a scalar value for a specific element of a vector.
7901 /// Looks through BUILD_VECTOR and SCALAR_TO_VECTOR nodes to find a scalar.
7902 static SDValue getScalarValueForVectorElement(SDValue V, int Idx,
7903 SelectionDAG &DAG) {
7904 MVT VT = V.getSimpleValueType();
7905 MVT EltVT = VT.getVectorElementType();
7906 while (V.getOpcode() == ISD::BITCAST)
7907 V = V.getOperand(0);
7908 // If the bitcasts shift the element size, we can't extract an equivalent
7910 MVT NewVT = V.getSimpleValueType();
7911 if (!NewVT.isVector() || NewVT.getScalarSizeInBits() != VT.getScalarSizeInBits())
7914 if (V.getOpcode() == ISD::BUILD_VECTOR ||
7915 (Idx == 0 && V.getOpcode() == ISD::SCALAR_TO_VECTOR))
7916 return DAG.getNode(ISD::BITCAST, SDLoc(V), EltVT, V.getOperand(Idx));
7921 /// \brief Helper to test for a load that can be folded with x86 shuffles.
7923 /// This is particularly important because the set of instructions varies
7924 /// significantly based on whether the operand is a load or not.
7925 static bool isShuffleFoldableLoad(SDValue V) {
7926 while (V.getOpcode() == ISD::BITCAST)
7927 V = V.getOperand(0);
7929 return ISD::isNON_EXTLoad(V.getNode());
7932 /// \brief Try to lower insertion of a single element into a zero vector.
7934 /// This is a common pattern that we have especially efficient patterns to lower
7935 /// across all subtarget feature sets.
7936 static SDValue lowerVectorShuffleAsElementInsertion(
7937 MVT VT, SDLoc DL, SDValue V1, SDValue V2, ArrayRef<int> Mask,
7938 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
7939 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
7941 MVT EltVT = VT.getVectorElementType();
7943 int V2Index = std::find_if(Mask.begin(), Mask.end(),
7944 [&Mask](int M) { return M >= (int)Mask.size(); }) -
7946 bool IsV1Zeroable = true;
7947 for (int i = 0, Size = Mask.size(); i < Size; ++i)
7948 if (i != V2Index && !Zeroable[i]) {
7949 IsV1Zeroable = false;
7953 // Check for a single input from a SCALAR_TO_VECTOR node.
7954 // FIXME: All of this should be canonicalized into INSERT_VECTOR_ELT and
7955 // all the smarts here sunk into that routine. However, the current
7956 // lowering of BUILD_VECTOR makes that nearly impossible until the old
7957 // vector shuffle lowering is dead.
7958 if (SDValue V2S = getScalarValueForVectorElement(
7959 V2, Mask[V2Index] - Mask.size(), DAG)) {
7960 // We need to zext the scalar if it is smaller than an i32.
7961 V2S = DAG.getNode(ISD::BITCAST, DL, EltVT, V2S);
7962 if (EltVT == MVT::i8 || EltVT == MVT::i16) {
7963 // Using zext to expand a narrow element won't work for non-zero
7968 // Zero-extend directly to i32.
7970 V2S = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i32, V2S);
7972 V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, ExtVT, V2S);
7973 } else if (Mask[V2Index] != (int)Mask.size() || EltVT == MVT::i8 ||
7974 EltVT == MVT::i16) {
7975 // Either not inserting from the low element of the input or the input
7976 // element size is too small to use VZEXT_MOVL to clear the high bits.
7980 if (!IsV1Zeroable) {
7981 // If V1 can't be treated as a zero vector we have fewer options to lower
7982 // this. We can't support integer vectors or non-zero targets cheaply, and
7983 // the V1 elements can't be permuted in any way.
7984 assert(VT == ExtVT && "Cannot change extended type when non-zeroable!");
7985 if (!VT.isFloatingPoint() || V2Index != 0)
7987 SmallVector<int, 8> V1Mask(Mask.begin(), Mask.end());
7988 V1Mask[V2Index] = -1;
7989 if (!isNoopShuffleMask(V1Mask))
7991 // This is essentially a special case blend operation, but if we have
7992 // general purpose blend operations, they are always faster. Bail and let
7993 // the rest of the lowering handle these as blends.
7994 if (Subtarget->hasSSE41())
7997 // Otherwise, use MOVSD or MOVSS.
7998 assert((EltVT == MVT::f32 || EltVT == MVT::f64) &&
7999 "Only two types of floating point element types to handle!");
8000 return DAG.getNode(EltVT == MVT::f32 ? X86ISD::MOVSS : X86ISD::MOVSD, DL,
8004 V2 = DAG.getNode(X86ISD::VZEXT_MOVL, DL, ExtVT, V2);
8006 V2 = DAG.getNode(ISD::BITCAST, DL, VT, V2);
8009 // If we have 4 or fewer lanes we can cheaply shuffle the element into
8010 // the desired position. Otherwise it is more efficient to do a vector
8011 // shift left. We know that we can do a vector shift left because all
8012 // the inputs are zero.
8013 if (VT.isFloatingPoint() || VT.getVectorNumElements() <= 4) {
8014 SmallVector<int, 4> V2Shuffle(Mask.size(), 1);
8015 V2Shuffle[V2Index] = 0;
8016 V2 = DAG.getVectorShuffle(VT, DL, V2, DAG.getUNDEF(VT), V2Shuffle);
8018 V2 = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, V2);
8020 X86ISD::VSHLDQ, DL, MVT::v2i64, V2,
8022 V2Index * EltVT.getSizeInBits(),
8023 DAG.getTargetLoweringInfo().getScalarShiftAmountTy(MVT::v2i64)));
8024 V2 = DAG.getNode(ISD::BITCAST, DL, VT, V2);
8030 /// \brief Try to lower broadcast of a single element.
8032 /// For convenience, this code also bundles all of the subtarget feature set
8033 /// filtering. While a little annoying to re-dispatch on type here, there isn't
8034 /// a convenient way to factor it out.
8035 static SDValue lowerVectorShuffleAsBroadcast(MVT VT, SDLoc DL, SDValue V,
8037 const X86Subtarget *Subtarget,
8038 SelectionDAG &DAG) {
8039 if (!Subtarget->hasAVX())
8041 if (VT.isInteger() && !Subtarget->hasAVX2())
8044 // Check that the mask is a broadcast.
8045 int BroadcastIdx = -1;
8047 if (M >= 0 && BroadcastIdx == -1)
8049 else if (M >= 0 && M != BroadcastIdx)
8052 assert(BroadcastIdx < (int)Mask.size() && "We only expect to be called with "
8053 "a sorted mask where the broadcast "
8056 // Go up the chain of (vector) values to try and find a scalar load that
8057 // we can combine with the broadcast.
8059 switch (V.getOpcode()) {
8060 case ISD::CONCAT_VECTORS: {
8061 int OperandSize = Mask.size() / V.getNumOperands();
8062 V = V.getOperand(BroadcastIdx / OperandSize);
8063 BroadcastIdx %= OperandSize;
8067 case ISD::INSERT_SUBVECTOR: {
8068 SDValue VOuter = V.getOperand(0), VInner = V.getOperand(1);
8069 auto ConstantIdx = dyn_cast<ConstantSDNode>(V.getOperand(2));
8073 int BeginIdx = (int)ConstantIdx->getZExtValue();
8075 BeginIdx + (int)VInner.getValueType().getVectorNumElements();
8076 if (BroadcastIdx >= BeginIdx && BroadcastIdx < EndIdx) {
8077 BroadcastIdx -= BeginIdx;
8088 // Check if this is a broadcast of a scalar. We special case lowering
8089 // for scalars so that we can more effectively fold with loads.
8090 if (V.getOpcode() == ISD::BUILD_VECTOR ||
8091 (V.getOpcode() == ISD::SCALAR_TO_VECTOR && BroadcastIdx == 0)) {
8092 V = V.getOperand(BroadcastIdx);
8094 // If the scalar isn't a load we can't broadcast from it in AVX1, only with
8096 if (!Subtarget->hasAVX2() && !isShuffleFoldableLoad(V))
8098 } else if (BroadcastIdx != 0 || !Subtarget->hasAVX2()) {
8099 // We can't broadcast from a vector register w/o AVX2, and we can only
8100 // broadcast from the zero-element of a vector register.
8104 return DAG.getNode(X86ISD::VBROADCAST, DL, VT, V);
8107 /// \brief Handle lowering of 2-lane 64-bit floating point shuffles.
8109 /// This is the basis function for the 2-lane 64-bit shuffles as we have full
8110 /// support for floating point shuffles but not integer shuffles. These
8111 /// instructions will incur a domain crossing penalty on some chips though so
8112 /// it is better to avoid lowering through this for integer vectors where
8114 static SDValue lowerV2F64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8115 const X86Subtarget *Subtarget,
8116 SelectionDAG &DAG) {
8118 assert(Op.getSimpleValueType() == MVT::v2f64 && "Bad shuffle type!");
8119 assert(V1.getSimpleValueType() == MVT::v2f64 && "Bad operand type!");
8120 assert(V2.getSimpleValueType() == MVT::v2f64 && "Bad operand type!");
8121 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8122 ArrayRef<int> Mask = SVOp->getMask();
8123 assert(Mask.size() == 2 && "Unexpected mask size for v2 shuffle!");
8125 if (isSingleInputShuffleMask(Mask)) {
8126 // Straight shuffle of a single input vector. Simulate this by using the
8127 // single input as both of the "inputs" to this instruction..
8128 unsigned SHUFPDMask = (Mask[0] == 1) | ((Mask[1] == 1) << 1);
8130 if (Subtarget->hasAVX()) {
8131 // If we have AVX, we can use VPERMILPS which will allow folding a load
8132 // into the shuffle.
8133 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v2f64, V1,
8134 DAG.getConstant(SHUFPDMask, MVT::i8));
8137 return DAG.getNode(X86ISD::SHUFP, SDLoc(Op), MVT::v2f64, V1, V1,
8138 DAG.getConstant(SHUFPDMask, MVT::i8));
8140 assert(Mask[0] >= 0 && Mask[0] < 2 && "Non-canonicalized blend!");
8141 assert(Mask[1] >= 2 && "Non-canonicalized blend!");
8143 // Use dedicated unpack instructions for masks that match their pattern.
8144 if (isShuffleEquivalent(Mask, 0, 2))
8145 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v2f64, V1, V2);
8146 if (isShuffleEquivalent(Mask, 1, 3))
8147 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v2f64, V1, V2);
8149 // If we have a single input, insert that into V1 if we can do so cheaply.
8150 if ((Mask[0] >= 2) + (Mask[1] >= 2) == 1) {
8151 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
8152 MVT::v2f64, DL, V1, V2, Mask, Subtarget, DAG))
8154 // Try inverting the insertion since for v2 masks it is easy to do and we
8155 // can't reliably sort the mask one way or the other.
8156 int InverseMask[2] = {Mask[0] < 0 ? -1 : (Mask[0] ^ 2),
8157 Mask[1] < 0 ? -1 : (Mask[1] ^ 2)};
8158 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
8159 MVT::v2f64, DL, V2, V1, InverseMask, Subtarget, DAG))
8163 // Try to use one of the special instruction patterns to handle two common
8164 // blend patterns if a zero-blend above didn't work.
8165 if (isShuffleEquivalent(Mask, 0, 3) || isShuffleEquivalent(Mask, 1, 3))
8166 if (SDValue V1S = getScalarValueForVectorElement(V1, Mask[0], DAG))
8167 // We can either use a special instruction to load over the low double or
8168 // to move just the low double.
8170 isShuffleFoldableLoad(V1S) ? X86ISD::MOVLPD : X86ISD::MOVSD,
8172 DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, MVT::v2f64, V1S));
8174 if (Subtarget->hasSSE41())
8175 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v2f64, V1, V2, Mask,
8179 unsigned SHUFPDMask = (Mask[0] == 1) | (((Mask[1] - 2) == 1) << 1);
8180 return DAG.getNode(X86ISD::SHUFP, SDLoc(Op), MVT::v2f64, V1, V2,
8181 DAG.getConstant(SHUFPDMask, MVT::i8));
8184 /// \brief Handle lowering of 2-lane 64-bit integer shuffles.
8186 /// Tries to lower a 2-lane 64-bit shuffle using shuffle operations provided by
8187 /// the integer unit to minimize domain crossing penalties. However, for blends
8188 /// it falls back to the floating point shuffle operation with appropriate bit
8190 static SDValue lowerV2I64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8191 const X86Subtarget *Subtarget,
8192 SelectionDAG &DAG) {
8194 assert(Op.getSimpleValueType() == MVT::v2i64 && "Bad shuffle type!");
8195 assert(V1.getSimpleValueType() == MVT::v2i64 && "Bad operand type!");
8196 assert(V2.getSimpleValueType() == MVT::v2i64 && "Bad operand type!");
8197 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8198 ArrayRef<int> Mask = SVOp->getMask();
8199 assert(Mask.size() == 2 && "Unexpected mask size for v2 shuffle!");
8201 if (isSingleInputShuffleMask(Mask)) {
8202 // Check for being able to broadcast a single element.
8203 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v2i64, DL, V1,
8204 Mask, Subtarget, DAG))
8207 // Straight shuffle of a single input vector. For everything from SSE2
8208 // onward this has a single fast instruction with no scary immediates.
8209 // We have to map the mask as it is actually a v4i32 shuffle instruction.
8210 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, V1);
8211 int WidenedMask[4] = {
8212 std::max(Mask[0], 0) * 2, std::max(Mask[0], 0) * 2 + 1,
8213 std::max(Mask[1], 0) * 2, std::max(Mask[1], 0) * 2 + 1};
8215 ISD::BITCAST, DL, MVT::v2i64,
8216 DAG.getNode(X86ISD::PSHUFD, SDLoc(Op), MVT::v4i32, V1,
8217 getV4X86ShuffleImm8ForMask(WidenedMask, DAG)));
8220 // If we have a single input from V2 insert that into V1 if we can do so
8222 if ((Mask[0] >= 2) + (Mask[1] >= 2) == 1) {
8223 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
8224 MVT::v2i64, DL, V1, V2, Mask, Subtarget, DAG))
8226 // Try inverting the insertion since for v2 masks it is easy to do and we
8227 // can't reliably sort the mask one way or the other.
8228 int InverseMask[2] = {Mask[0] < 0 ? -1 : (Mask[0] ^ 2),
8229 Mask[1] < 0 ? -1 : (Mask[1] ^ 2)};
8230 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
8231 MVT::v2i64, DL, V2, V1, InverseMask, Subtarget, DAG))
8235 // Use dedicated unpack instructions for masks that match their pattern.
8236 if (isShuffleEquivalent(Mask, 0, 2))
8237 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v2i64, V1, V2);
8238 if (isShuffleEquivalent(Mask, 1, 3))
8239 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v2i64, V1, V2);
8241 if (Subtarget->hasSSE41())
8242 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v2i64, V1, V2, Mask,
8246 // Try to use byte shift instructions.
8247 if (SDValue Shift = lowerVectorShuffleAsByteShift(
8248 DL, MVT::v2i64, V1, V2, Mask, DAG))
8251 // Try to use byte rotation instructions.
8252 // Its more profitable for pre-SSSE3 to use shuffles/unpacks.
8253 if (Subtarget->hasSSSE3())
8254 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
8255 DL, MVT::v2i64, V1, V2, Mask, Subtarget, DAG))
8258 // We implement this with SHUFPD which is pretty lame because it will likely
8259 // incur 2 cycles of stall for integer vectors on Nehalem and older chips.
8260 // However, all the alternatives are still more cycles and newer chips don't
8261 // have this problem. It would be really nice if x86 had better shuffles here.
8262 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v2f64, V1);
8263 V2 = DAG.getNode(ISD::BITCAST, DL, MVT::v2f64, V2);
8264 return DAG.getNode(ISD::BITCAST, DL, MVT::v2i64,
8265 DAG.getVectorShuffle(MVT::v2f64, DL, V1, V2, Mask));
8268 /// \brief Lower a vector shuffle using the SHUFPS instruction.
8270 /// This is a helper routine dedicated to lowering vector shuffles using SHUFPS.
8271 /// It makes no assumptions about whether this is the *best* lowering, it simply
8273 static SDValue lowerVectorShuffleWithSHUFPS(SDLoc DL, MVT VT,
8274 ArrayRef<int> Mask, SDValue V1,
8275 SDValue V2, SelectionDAG &DAG) {
8276 SDValue LowV = V1, HighV = V2;
8277 int NewMask[4] = {Mask[0], Mask[1], Mask[2], Mask[3]};
8280 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; });
8282 if (NumV2Elements == 1) {
8284 std::find_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; }) -
8287 // Compute the index adjacent to V2Index and in the same half by toggling
8289 int V2AdjIndex = V2Index ^ 1;
8291 if (Mask[V2AdjIndex] == -1) {
8292 // Handles all the cases where we have a single V2 element and an undef.
8293 // This will only ever happen in the high lanes because we commute the
8294 // vector otherwise.
8296 std::swap(LowV, HighV);
8297 NewMask[V2Index] -= 4;
8299 // Handle the case where the V2 element ends up adjacent to a V1 element.
8300 // To make this work, blend them together as the first step.
8301 int V1Index = V2AdjIndex;
8302 int BlendMask[4] = {Mask[V2Index] - 4, 0, Mask[V1Index], 0};
8303 V2 = DAG.getNode(X86ISD::SHUFP, DL, VT, V2, V1,
8304 getV4X86ShuffleImm8ForMask(BlendMask, DAG));
8306 // Now proceed to reconstruct the final blend as we have the necessary
8307 // high or low half formed.
8314 NewMask[V1Index] = 2; // We put the V1 element in V2[2].
8315 NewMask[V2Index] = 0; // We shifted the V2 element into V2[0].
8317 } else if (NumV2Elements == 2) {
8318 if (Mask[0] < 4 && Mask[1] < 4) {
8319 // Handle the easy case where we have V1 in the low lanes and V2 in the
8323 } else if (Mask[2] < 4 && Mask[3] < 4) {
8324 // We also handle the reversed case because this utility may get called
8325 // when we detect a SHUFPS pattern but can't easily commute the shuffle to
8326 // arrange things in the right direction.
8332 // We have a mixture of V1 and V2 in both low and high lanes. Rather than
8333 // trying to place elements directly, just blend them and set up the final
8334 // shuffle to place them.
8336 // The first two blend mask elements are for V1, the second two are for
8338 int BlendMask[4] = {Mask[0] < 4 ? Mask[0] : Mask[1],
8339 Mask[2] < 4 ? Mask[2] : Mask[3],
8340 (Mask[0] >= 4 ? Mask[0] : Mask[1]) - 4,
8341 (Mask[2] >= 4 ? Mask[2] : Mask[3]) - 4};
8342 V1 = DAG.getNode(X86ISD::SHUFP, DL, VT, V1, V2,
8343 getV4X86ShuffleImm8ForMask(BlendMask, DAG));
8345 // Now we do a normal shuffle of V1 by giving V1 as both operands to
8348 NewMask[0] = Mask[0] < 4 ? 0 : 2;
8349 NewMask[1] = Mask[0] < 4 ? 2 : 0;
8350 NewMask[2] = Mask[2] < 4 ? 1 : 3;
8351 NewMask[3] = Mask[2] < 4 ? 3 : 1;
8354 return DAG.getNode(X86ISD::SHUFP, DL, VT, LowV, HighV,
8355 getV4X86ShuffleImm8ForMask(NewMask, DAG));
8358 /// \brief Lower 4-lane 32-bit floating point shuffles.
8360 /// Uses instructions exclusively from the floating point unit to minimize
8361 /// domain crossing penalties, as these are sufficient to implement all v4f32
8363 static SDValue lowerV4F32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8364 const X86Subtarget *Subtarget,
8365 SelectionDAG &DAG) {
8367 assert(Op.getSimpleValueType() == MVT::v4f32 && "Bad shuffle type!");
8368 assert(V1.getSimpleValueType() == MVT::v4f32 && "Bad operand type!");
8369 assert(V2.getSimpleValueType() == MVT::v4f32 && "Bad operand type!");
8370 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8371 ArrayRef<int> Mask = SVOp->getMask();
8372 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
8375 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; });
8377 if (NumV2Elements == 0) {
8378 // Check for being able to broadcast a single element.
8379 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v4f32, DL, V1,
8380 Mask, Subtarget, DAG))
8383 if (Subtarget->hasAVX()) {
8384 // If we have AVX, we can use VPERMILPS which will allow folding a load
8385 // into the shuffle.
8386 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v4f32, V1,
8387 getV4X86ShuffleImm8ForMask(Mask, DAG));
8390 // Otherwise, use a straight shuffle of a single input vector. We pass the
8391 // input vector to both operands to simulate this with a SHUFPS.
8392 return DAG.getNode(X86ISD::SHUFP, DL, MVT::v4f32, V1, V1,
8393 getV4X86ShuffleImm8ForMask(Mask, DAG));
8396 // Use dedicated unpack instructions for masks that match their pattern.
8397 if (isShuffleEquivalent(Mask, 0, 4, 1, 5))
8398 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4f32, V1, V2);
8399 if (isShuffleEquivalent(Mask, 2, 6, 3, 7))
8400 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4f32, V1, V2);
8402 // There are special ways we can lower some single-element blends. However, we
8403 // have custom ways we can lower more complex single-element blends below that
8404 // we defer to if both this and BLENDPS fail to match, so restrict this to
8405 // when the V2 input is targeting element 0 of the mask -- that is the fast
8407 if (NumV2Elements == 1 && Mask[0] >= 4)
8408 if (SDValue V = lowerVectorShuffleAsElementInsertion(MVT::v4f32, DL, V1, V2,
8409 Mask, Subtarget, DAG))
8412 if (Subtarget->hasSSE41())
8413 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4f32, V1, V2, Mask,
8417 // Check for whether we can use INSERTPS to perform the blend. We only use
8418 // INSERTPS when the V1 elements are already in the correct locations
8419 // because otherwise we can just always use two SHUFPS instructions which
8420 // are much smaller to encode than a SHUFPS and an INSERTPS.
8421 if (NumV2Elements == 1 && Subtarget->hasSSE41()) {
8423 std::find_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; }) -
8426 // When using INSERTPS we can zero any lane of the destination. Collect
8427 // the zero inputs into a mask and drop them from the lanes of V1 which
8428 // actually need to be present as inputs to the INSERTPS.
8429 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
8431 // Synthesize a shuffle mask for the non-zero and non-v2 inputs.
8432 bool InsertNeedsShuffle = false;
8434 for (int i = 0; i < 4; ++i)
8438 } else if (Mask[i] != i) {
8439 InsertNeedsShuffle = true;
8444 // We don't want to use INSERTPS or other insertion techniques if it will
8445 // require shuffling anyways.
8446 if (!InsertNeedsShuffle) {
8447 // If all of V1 is zeroable, replace it with undef.
8448 if ((ZMask | 1 << V2Index) == 0xF)
8449 V1 = DAG.getUNDEF(MVT::v4f32);
8451 unsigned InsertPSMask = (Mask[V2Index] - 4) << 6 | V2Index << 4 | ZMask;
8452 assert((InsertPSMask & ~0xFFu) == 0 && "Invalid mask!");
8454 // Insert the V2 element into the desired position.
8455 return DAG.getNode(X86ISD::INSERTPS, DL, MVT::v4f32, V1, V2,
8456 DAG.getConstant(InsertPSMask, MVT::i8));
8460 // Otherwise fall back to a SHUFPS lowering strategy.
8461 return lowerVectorShuffleWithSHUFPS(DL, MVT::v4f32, Mask, V1, V2, DAG);
8464 /// \brief Lower 4-lane i32 vector shuffles.
8466 /// We try to handle these with integer-domain shuffles where we can, but for
8467 /// blends we use the floating point domain blend instructions.
8468 static SDValue lowerV4I32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8469 const X86Subtarget *Subtarget,
8470 SelectionDAG &DAG) {
8472 assert(Op.getSimpleValueType() == MVT::v4i32 && "Bad shuffle type!");
8473 assert(V1.getSimpleValueType() == MVT::v4i32 && "Bad operand type!");
8474 assert(V2.getSimpleValueType() == MVT::v4i32 && "Bad operand type!");
8475 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8476 ArrayRef<int> Mask = SVOp->getMask();
8477 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
8479 // Whenever we can lower this as a zext, that instruction is strictly faster
8480 // than any alternative. It also allows us to fold memory operands into the
8481 // shuffle in many cases.
8482 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(DL, MVT::v4i32, V1, V2,
8483 Mask, Subtarget, DAG))
8487 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; });
8489 if (NumV2Elements == 0) {
8490 // Check for being able to broadcast a single element.
8491 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v4i32, DL, V1,
8492 Mask, Subtarget, DAG))
8495 // Straight shuffle of a single input vector. For everything from SSE2
8496 // onward this has a single fast instruction with no scary immediates.
8497 // We coerce the shuffle pattern to be compatible with UNPCK instructions
8498 // but we aren't actually going to use the UNPCK instruction because doing
8499 // so prevents folding a load into this instruction or making a copy.
8500 const int UnpackLoMask[] = {0, 0, 1, 1};
8501 const int UnpackHiMask[] = {2, 2, 3, 3};
8502 if (isShuffleEquivalent(Mask, 0, 0, 1, 1))
8503 Mask = UnpackLoMask;
8504 else if (isShuffleEquivalent(Mask, 2, 2, 3, 3))
8505 Mask = UnpackHiMask;
8507 return DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32, V1,
8508 getV4X86ShuffleImm8ForMask(Mask, DAG));
8511 // There are special ways we can lower some single-element blends.
8512 if (NumV2Elements == 1)
8513 if (SDValue V = lowerVectorShuffleAsElementInsertion(MVT::v4i32, DL, V1, V2,
8514 Mask, Subtarget, DAG))
8517 // Use dedicated unpack instructions for masks that match their pattern.
8518 if (isShuffleEquivalent(Mask, 0, 4, 1, 5))
8519 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4i32, V1, V2);
8520 if (isShuffleEquivalent(Mask, 2, 6, 3, 7))
8521 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4i32, V1, V2);
8523 if (Subtarget->hasSSE41())
8524 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4i32, V1, V2, Mask,
8528 // Try to use byte shift instructions.
8529 if (SDValue Shift = lowerVectorShuffleAsByteShift(
8530 DL, MVT::v4i32, V1, V2, Mask, DAG))
8533 // Try to use byte rotation instructions.
8534 // Its more profitable for pre-SSSE3 to use shuffles/unpacks.
8535 if (Subtarget->hasSSSE3())
8536 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
8537 DL, MVT::v4i32, V1, V2, Mask, Subtarget, DAG))
8540 // We implement this with SHUFPS because it can blend from two vectors.
8541 // Because we're going to eventually use SHUFPS, we use SHUFPS even to build
8542 // up the inputs, bypassing domain shift penalties that we would encur if we
8543 // directly used PSHUFD on Nehalem and older. For newer chips, this isn't
8545 return DAG.getNode(ISD::BITCAST, DL, MVT::v4i32,
8546 DAG.getVectorShuffle(
8548 DAG.getNode(ISD::BITCAST, DL, MVT::v4f32, V1),
8549 DAG.getNode(ISD::BITCAST, DL, MVT::v4f32, V2), Mask));
8552 /// \brief Lowering of single-input v8i16 shuffles is the cornerstone of SSE2
8553 /// shuffle lowering, and the most complex part.
8555 /// The lowering strategy is to try to form pairs of input lanes which are
8556 /// targeted at the same half of the final vector, and then use a dword shuffle
8557 /// to place them onto the right half, and finally unpack the paired lanes into
8558 /// their final position.
8560 /// The exact breakdown of how to form these dword pairs and align them on the
8561 /// correct sides is really tricky. See the comments within the function for
8562 /// more of the details.
8563 static SDValue lowerV8I16SingleInputVectorShuffle(
8564 SDLoc DL, SDValue V, MutableArrayRef<int> Mask,
8565 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
8566 assert(V.getSimpleValueType() == MVT::v8i16 && "Bad input type!");
8567 MutableArrayRef<int> LoMask = Mask.slice(0, 4);
8568 MutableArrayRef<int> HiMask = Mask.slice(4, 4);
8570 SmallVector<int, 4> LoInputs;
8571 std::copy_if(LoMask.begin(), LoMask.end(), std::back_inserter(LoInputs),
8572 [](int M) { return M >= 0; });
8573 std::sort(LoInputs.begin(), LoInputs.end());
8574 LoInputs.erase(std::unique(LoInputs.begin(), LoInputs.end()), LoInputs.end());
8575 SmallVector<int, 4> HiInputs;
8576 std::copy_if(HiMask.begin(), HiMask.end(), std::back_inserter(HiInputs),
8577 [](int M) { return M >= 0; });
8578 std::sort(HiInputs.begin(), HiInputs.end());
8579 HiInputs.erase(std::unique(HiInputs.begin(), HiInputs.end()), HiInputs.end());
8581 std::lower_bound(LoInputs.begin(), LoInputs.end(), 4) - LoInputs.begin();
8582 int NumHToL = LoInputs.size() - NumLToL;
8584 std::lower_bound(HiInputs.begin(), HiInputs.end(), 4) - HiInputs.begin();
8585 int NumHToH = HiInputs.size() - NumLToH;
8586 MutableArrayRef<int> LToLInputs(LoInputs.data(), NumLToL);
8587 MutableArrayRef<int> LToHInputs(HiInputs.data(), NumLToH);
8588 MutableArrayRef<int> HToLInputs(LoInputs.data() + NumLToL, NumHToL);
8589 MutableArrayRef<int> HToHInputs(HiInputs.data() + NumLToH, NumHToH);
8591 // Check for being able to broadcast a single element.
8592 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v8i16, DL, V,
8593 Mask, Subtarget, DAG))
8596 // Use dedicated unpack instructions for masks that match their pattern.
8597 if (isShuffleEquivalent(Mask, 0, 0, 1, 1, 2, 2, 3, 3))
8598 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8i16, V, V);
8599 if (isShuffleEquivalent(Mask, 4, 4, 5, 5, 6, 6, 7, 7))
8600 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8i16, V, V);
8602 // Try to use byte shift instructions.
8603 if (SDValue Shift = lowerVectorShuffleAsByteShift(
8604 DL, MVT::v8i16, V, V, Mask, DAG))
8607 // Try to use byte rotation instructions.
8608 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
8609 DL, MVT::v8i16, V, V, Mask, Subtarget, DAG))
8612 // Simplify the 1-into-3 and 3-into-1 cases with a single pshufd. For all
8613 // such inputs we can swap two of the dwords across the half mark and end up
8614 // with <=2 inputs to each half in each half. Once there, we can fall through
8615 // to the generic code below. For example:
8617 // Input: [a, b, c, d, e, f, g, h] -PSHUFD[0,2,1,3]-> [a, b, e, f, c, d, g, h]
8618 // Mask: [0, 1, 2, 7, 4, 5, 6, 3] -----------------> [0, 1, 4, 7, 2, 3, 6, 5]
8620 // However in some very rare cases we have a 1-into-3 or 3-into-1 on one half
8621 // and an existing 2-into-2 on the other half. In this case we may have to
8622 // pre-shuffle the 2-into-2 half to avoid turning it into a 3-into-1 or
8623 // 1-into-3 which could cause us to cycle endlessly fixing each side in turn.
8624 // Fortunately, we don't have to handle anything but a 2-into-2 pattern
8625 // because any other situation (including a 3-into-1 or 1-into-3 in the other
8626 // half than the one we target for fixing) will be fixed when we re-enter this
8627 // path. We will also combine away any sequence of PSHUFD instructions that
8628 // result into a single instruction. Here is an example of the tricky case:
8630 // Input: [a, b, c, d, e, f, g, h] -PSHUFD[0,2,1,3]-> [a, b, e, f, c, d, g, h]
8631 // Mask: [3, 7, 1, 0, 2, 7, 3, 5] -THIS-IS-BAD!!!!-> [5, 7, 1, 0, 4, 7, 5, 3]
8633 // This now has a 1-into-3 in the high half! Instead, we do two shuffles:
8635 // Input: [a, b, c, d, e, f, g, h] PSHUFHW[0,2,1,3]-> [a, b, c, d, e, g, f, h]
8636 // Mask: [3, 7, 1, 0, 2, 7, 3, 5] -----------------> [3, 7, 1, 0, 2, 7, 3, 6]
8638 // Input: [a, b, c, d, e, g, f, h] -PSHUFD[0,2,1,3]-> [a, b, e, g, c, d, f, h]
8639 // Mask: [3, 7, 1, 0, 2, 7, 3, 6] -----------------> [5, 7, 1, 0, 4, 7, 5, 6]
8641 // The result is fine to be handled by the generic logic.
8642 auto balanceSides = [&](ArrayRef<int> AToAInputs, ArrayRef<int> BToAInputs,
8643 ArrayRef<int> BToBInputs, ArrayRef<int> AToBInputs,
8644 int AOffset, int BOffset) {
8645 assert((AToAInputs.size() == 3 || AToAInputs.size() == 1) &&
8646 "Must call this with A having 3 or 1 inputs from the A half.");
8647 assert((BToAInputs.size() == 1 || BToAInputs.size() == 3) &&
8648 "Must call this with B having 1 or 3 inputs from the B half.");
8649 assert(AToAInputs.size() + BToAInputs.size() == 4 &&
8650 "Must call this with either 3:1 or 1:3 inputs (summing to 4).");
8652 // Compute the index of dword with only one word among the three inputs in
8653 // a half by taking the sum of the half with three inputs and subtracting
8654 // the sum of the actual three inputs. The difference is the remaining
8657 int &TripleDWord = AToAInputs.size() == 3 ? ADWord : BDWord;
8658 int &OneInputDWord = AToAInputs.size() == 3 ? BDWord : ADWord;
8659 int TripleInputOffset = AToAInputs.size() == 3 ? AOffset : BOffset;
8660 ArrayRef<int> TripleInputs = AToAInputs.size() == 3 ? AToAInputs : BToAInputs;
8661 int OneInput = AToAInputs.size() == 3 ? BToAInputs[0] : AToAInputs[0];
8662 int TripleInputSum = 0 + 1 + 2 + 3 + (4 * TripleInputOffset);
8663 int TripleNonInputIdx =
8664 TripleInputSum - std::accumulate(TripleInputs.begin(), TripleInputs.end(), 0);
8665 TripleDWord = TripleNonInputIdx / 2;
8667 // We use xor with one to compute the adjacent DWord to whichever one the
8669 OneInputDWord = (OneInput / 2) ^ 1;
8671 // Check for one tricky case: We're fixing a 3<-1 or a 1<-3 shuffle for AToA
8672 // and BToA inputs. If there is also such a problem with the BToB and AToB
8673 // inputs, we don't try to fix it necessarily -- we'll recurse and see it in
8674 // the next pass. However, if we have a 2<-2 in the BToB and AToB inputs, it
8675 // is essential that we don't *create* a 3<-1 as then we might oscillate.
8676 if (BToBInputs.size() == 2 && AToBInputs.size() == 2) {
8677 // Compute how many inputs will be flipped by swapping these DWords. We
8679 // to balance this to ensure we don't form a 3-1 shuffle in the other
8681 int NumFlippedAToBInputs =
8682 std::count(AToBInputs.begin(), AToBInputs.end(), 2 * ADWord) +
8683 std::count(AToBInputs.begin(), AToBInputs.end(), 2 * ADWord + 1);
8684 int NumFlippedBToBInputs =
8685 std::count(BToBInputs.begin(), BToBInputs.end(), 2 * BDWord) +
8686 std::count(BToBInputs.begin(), BToBInputs.end(), 2 * BDWord + 1);
8687 if ((NumFlippedAToBInputs == 1 &&
8688 (NumFlippedBToBInputs == 0 || NumFlippedBToBInputs == 2)) ||
8689 (NumFlippedBToBInputs == 1 &&
8690 (NumFlippedAToBInputs == 0 || NumFlippedAToBInputs == 2))) {
8691 // We choose whether to fix the A half or B half based on whether that
8692 // half has zero flipped inputs. At zero, we may not be able to fix it
8693 // with that half. We also bias towards fixing the B half because that
8694 // will more commonly be the high half, and we have to bias one way.
8695 auto FixFlippedInputs = [&V, &DL, &Mask, &DAG](int PinnedIdx, int DWord,
8696 ArrayRef<int> Inputs) {
8697 int FixIdx = PinnedIdx ^ 1; // The adjacent slot to the pinned slot.
8698 bool IsFixIdxInput = std::find(Inputs.begin(), Inputs.end(),
8699 PinnedIdx ^ 1) != Inputs.end();
8700 // Determine whether the free index is in the flipped dword or the
8701 // unflipped dword based on where the pinned index is. We use this bit
8702 // in an xor to conditionally select the adjacent dword.
8703 int FixFreeIdx = 2 * (DWord ^ (PinnedIdx / 2 == DWord));
8704 bool IsFixFreeIdxInput = std::find(Inputs.begin(), Inputs.end(),
8705 FixFreeIdx) != Inputs.end();
8706 if (IsFixIdxInput == IsFixFreeIdxInput)
8708 IsFixFreeIdxInput = std::find(Inputs.begin(), Inputs.end(),
8709 FixFreeIdx) != Inputs.end();
8710 assert(IsFixIdxInput != IsFixFreeIdxInput &&
8711 "We need to be changing the number of flipped inputs!");
8712 int PSHUFHalfMask[] = {0, 1, 2, 3};
8713 std::swap(PSHUFHalfMask[FixFreeIdx % 4], PSHUFHalfMask[FixIdx % 4]);
8714 V = DAG.getNode(FixIdx < 4 ? X86ISD::PSHUFLW : X86ISD::PSHUFHW, DL,
8716 getV4X86ShuffleImm8ForMask(PSHUFHalfMask, DAG));
8719 if (M != -1 && M == FixIdx)
8721 else if (M != -1 && M == FixFreeIdx)
8724 if (NumFlippedBToBInputs != 0) {
8726 BToAInputs.size() == 3 ? TripleNonInputIdx : OneInput;
8727 FixFlippedInputs(BPinnedIdx, BDWord, BToBInputs);
8729 assert(NumFlippedAToBInputs != 0 && "Impossible given predicates!");
8731 AToAInputs.size() == 3 ? TripleNonInputIdx : OneInput;
8732 FixFlippedInputs(APinnedIdx, ADWord, AToBInputs);
8737 int PSHUFDMask[] = {0, 1, 2, 3};
8738 PSHUFDMask[ADWord] = BDWord;
8739 PSHUFDMask[BDWord] = ADWord;
8740 V = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16,
8741 DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32,
8742 DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, V),
8743 getV4X86ShuffleImm8ForMask(PSHUFDMask, DAG)));
8745 // Adjust the mask to match the new locations of A and B.
8747 if (M != -1 && M/2 == ADWord)
8748 M = 2 * BDWord + M % 2;
8749 else if (M != -1 && M/2 == BDWord)
8750 M = 2 * ADWord + M % 2;
8752 // Recurse back into this routine to re-compute state now that this isn't
8753 // a 3 and 1 problem.
8754 return DAG.getVectorShuffle(MVT::v8i16, DL, V, DAG.getUNDEF(MVT::v8i16),
8757 if ((NumLToL == 3 && NumHToL == 1) || (NumLToL == 1 && NumHToL == 3))
8758 return balanceSides(LToLInputs, HToLInputs, HToHInputs, LToHInputs, 0, 4);
8759 else if ((NumHToH == 3 && NumLToH == 1) || (NumHToH == 1 && NumLToH == 3))
8760 return balanceSides(HToHInputs, LToHInputs, LToLInputs, HToLInputs, 4, 0);
8762 // At this point there are at most two inputs to the low and high halves from
8763 // each half. That means the inputs can always be grouped into dwords and
8764 // those dwords can then be moved to the correct half with a dword shuffle.
8765 // We use at most one low and one high word shuffle to collect these paired
8766 // inputs into dwords, and finally a dword shuffle to place them.
8767 int PSHUFLMask[4] = {-1, -1, -1, -1};
8768 int PSHUFHMask[4] = {-1, -1, -1, -1};
8769 int PSHUFDMask[4] = {-1, -1, -1, -1};
8771 // First fix the masks for all the inputs that are staying in their
8772 // original halves. This will then dictate the targets of the cross-half
8774 auto fixInPlaceInputs =
8775 [&PSHUFDMask](ArrayRef<int> InPlaceInputs, ArrayRef<int> IncomingInputs,
8776 MutableArrayRef<int> SourceHalfMask,
8777 MutableArrayRef<int> HalfMask, int HalfOffset) {
8778 if (InPlaceInputs.empty())
8780 if (InPlaceInputs.size() == 1) {
8781 SourceHalfMask[InPlaceInputs[0] - HalfOffset] =
8782 InPlaceInputs[0] - HalfOffset;
8783 PSHUFDMask[InPlaceInputs[0] / 2] = InPlaceInputs[0] / 2;
8786 if (IncomingInputs.empty()) {
8787 // Just fix all of the in place inputs.
8788 for (int Input : InPlaceInputs) {
8789 SourceHalfMask[Input - HalfOffset] = Input - HalfOffset;
8790 PSHUFDMask[Input / 2] = Input / 2;
8795 assert(InPlaceInputs.size() == 2 && "Cannot handle 3 or 4 inputs!");
8796 SourceHalfMask[InPlaceInputs[0] - HalfOffset] =
8797 InPlaceInputs[0] - HalfOffset;
8798 // Put the second input next to the first so that they are packed into
8799 // a dword. We find the adjacent index by toggling the low bit.
8800 int AdjIndex = InPlaceInputs[0] ^ 1;
8801 SourceHalfMask[AdjIndex - HalfOffset] = InPlaceInputs[1] - HalfOffset;
8802 std::replace(HalfMask.begin(), HalfMask.end(), InPlaceInputs[1], AdjIndex);
8803 PSHUFDMask[AdjIndex / 2] = AdjIndex / 2;
8805 fixInPlaceInputs(LToLInputs, HToLInputs, PSHUFLMask, LoMask, 0);
8806 fixInPlaceInputs(HToHInputs, LToHInputs, PSHUFHMask, HiMask, 4);
8808 // Now gather the cross-half inputs and place them into a free dword of
8809 // their target half.
8810 // FIXME: This operation could almost certainly be simplified dramatically to
8811 // look more like the 3-1 fixing operation.
8812 auto moveInputsToRightHalf = [&PSHUFDMask](
8813 MutableArrayRef<int> IncomingInputs, ArrayRef<int> ExistingInputs,
8814 MutableArrayRef<int> SourceHalfMask, MutableArrayRef<int> HalfMask,
8815 MutableArrayRef<int> FinalSourceHalfMask, int SourceOffset,
8817 auto isWordClobbered = [](ArrayRef<int> SourceHalfMask, int Word) {
8818 return SourceHalfMask[Word] != -1 && SourceHalfMask[Word] != Word;
8820 auto isDWordClobbered = [&isWordClobbered](ArrayRef<int> SourceHalfMask,
8822 int LowWord = Word & ~1;
8823 int HighWord = Word | 1;
8824 return isWordClobbered(SourceHalfMask, LowWord) ||
8825 isWordClobbered(SourceHalfMask, HighWord);
8828 if (IncomingInputs.empty())
8831 if (ExistingInputs.empty()) {
8832 // Map any dwords with inputs from them into the right half.
8833 for (int Input : IncomingInputs) {
8834 // If the source half mask maps over the inputs, turn those into
8835 // swaps and use the swapped lane.
8836 if (isWordClobbered(SourceHalfMask, Input - SourceOffset)) {
8837 if (SourceHalfMask[SourceHalfMask[Input - SourceOffset]] == -1) {
8838 SourceHalfMask[SourceHalfMask[Input - SourceOffset]] =
8839 Input - SourceOffset;
8840 // We have to swap the uses in our half mask in one sweep.
8841 for (int &M : HalfMask)
8842 if (M == SourceHalfMask[Input - SourceOffset] + SourceOffset)
8844 else if (M == Input)
8845 M = SourceHalfMask[Input - SourceOffset] + SourceOffset;
8847 assert(SourceHalfMask[SourceHalfMask[Input - SourceOffset]] ==
8848 Input - SourceOffset &&
8849 "Previous placement doesn't match!");
8851 // Note that this correctly re-maps both when we do a swap and when
8852 // we observe the other side of the swap above. We rely on that to
8853 // avoid swapping the members of the input list directly.
8854 Input = SourceHalfMask[Input - SourceOffset] + SourceOffset;
8857 // Map the input's dword into the correct half.
8858 if (PSHUFDMask[(Input - SourceOffset + DestOffset) / 2] == -1)
8859 PSHUFDMask[(Input - SourceOffset + DestOffset) / 2] = Input / 2;
8861 assert(PSHUFDMask[(Input - SourceOffset + DestOffset) / 2] ==
8863 "Previous placement doesn't match!");
8866 // And just directly shift any other-half mask elements to be same-half
8867 // as we will have mirrored the dword containing the element into the
8868 // same position within that half.
8869 for (int &M : HalfMask)
8870 if (M >= SourceOffset && M < SourceOffset + 4) {
8871 M = M - SourceOffset + DestOffset;
8872 assert(M >= 0 && "This should never wrap below zero!");
8877 // Ensure we have the input in a viable dword of its current half. This
8878 // is particularly tricky because the original position may be clobbered
8879 // by inputs being moved and *staying* in that half.
8880 if (IncomingInputs.size() == 1) {
8881 if (isWordClobbered(SourceHalfMask, IncomingInputs[0] - SourceOffset)) {
8882 int InputFixed = std::find(std::begin(SourceHalfMask),
8883 std::end(SourceHalfMask), -1) -
8884 std::begin(SourceHalfMask) + SourceOffset;
8885 SourceHalfMask[InputFixed - SourceOffset] =
8886 IncomingInputs[0] - SourceOffset;
8887 std::replace(HalfMask.begin(), HalfMask.end(), IncomingInputs[0],
8889 IncomingInputs[0] = InputFixed;
8891 } else if (IncomingInputs.size() == 2) {
8892 if (IncomingInputs[0] / 2 != IncomingInputs[1] / 2 ||
8893 isDWordClobbered(SourceHalfMask, IncomingInputs[0] - SourceOffset)) {
8894 // We have two non-adjacent or clobbered inputs we need to extract from
8895 // the source half. To do this, we need to map them into some adjacent
8896 // dword slot in the source mask.
8897 int InputsFixed[2] = {IncomingInputs[0] - SourceOffset,
8898 IncomingInputs[1] - SourceOffset};
8900 // If there is a free slot in the source half mask adjacent to one of
8901 // the inputs, place the other input in it. We use (Index XOR 1) to
8902 // compute an adjacent index.
8903 if (!isWordClobbered(SourceHalfMask, InputsFixed[0]) &&
8904 SourceHalfMask[InputsFixed[0] ^ 1] == -1) {
8905 SourceHalfMask[InputsFixed[0]] = InputsFixed[0];
8906 SourceHalfMask[InputsFixed[0] ^ 1] = InputsFixed[1];
8907 InputsFixed[1] = InputsFixed[0] ^ 1;
8908 } else if (!isWordClobbered(SourceHalfMask, InputsFixed[1]) &&
8909 SourceHalfMask[InputsFixed[1] ^ 1] == -1) {
8910 SourceHalfMask[InputsFixed[1]] = InputsFixed[1];
8911 SourceHalfMask[InputsFixed[1] ^ 1] = InputsFixed[0];
8912 InputsFixed[0] = InputsFixed[1] ^ 1;
8913 } else if (SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1)] == -1 &&
8914 SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1) + 1] == -1) {
8915 // The two inputs are in the same DWord but it is clobbered and the
8916 // adjacent DWord isn't used at all. Move both inputs to the free
8918 SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1)] = InputsFixed[0];
8919 SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1) + 1] = InputsFixed[1];
8920 InputsFixed[0] = 2 * ((InputsFixed[0] / 2) ^ 1);
8921 InputsFixed[1] = 2 * ((InputsFixed[0] / 2) ^ 1) + 1;
8923 // The only way we hit this point is if there is no clobbering
8924 // (because there are no off-half inputs to this half) and there is no
8925 // free slot adjacent to one of the inputs. In this case, we have to
8926 // swap an input with a non-input.
8927 for (int i = 0; i < 4; ++i)
8928 assert((SourceHalfMask[i] == -1 || SourceHalfMask[i] == i) &&
8929 "We can't handle any clobbers here!");
8930 assert(InputsFixed[1] != (InputsFixed[0] ^ 1) &&
8931 "Cannot have adjacent inputs here!");
8933 SourceHalfMask[InputsFixed[0] ^ 1] = InputsFixed[1];
8934 SourceHalfMask[InputsFixed[1]] = InputsFixed[0] ^ 1;
8936 // We also have to update the final source mask in this case because
8937 // it may need to undo the above swap.
8938 for (int &M : FinalSourceHalfMask)
8939 if (M == (InputsFixed[0] ^ 1) + SourceOffset)
8940 M = InputsFixed[1] + SourceOffset;
8941 else if (M == InputsFixed[1] + SourceOffset)
8942 M = (InputsFixed[0] ^ 1) + SourceOffset;
8944 InputsFixed[1] = InputsFixed[0] ^ 1;
8947 // Point everything at the fixed inputs.
8948 for (int &M : HalfMask)
8949 if (M == IncomingInputs[0])
8950 M = InputsFixed[0] + SourceOffset;
8951 else if (M == IncomingInputs[1])
8952 M = InputsFixed[1] + SourceOffset;
8954 IncomingInputs[0] = InputsFixed[0] + SourceOffset;
8955 IncomingInputs[1] = InputsFixed[1] + SourceOffset;
8958 llvm_unreachable("Unhandled input size!");
8961 // Now hoist the DWord down to the right half.
8962 int FreeDWord = (PSHUFDMask[DestOffset / 2] == -1 ? 0 : 1) + DestOffset / 2;
8963 assert(PSHUFDMask[FreeDWord] == -1 && "DWord not free");
8964 PSHUFDMask[FreeDWord] = IncomingInputs[0] / 2;
8965 for (int &M : HalfMask)
8966 for (int Input : IncomingInputs)
8968 M = FreeDWord * 2 + Input % 2;
8970 moveInputsToRightHalf(HToLInputs, LToLInputs, PSHUFHMask, LoMask, HiMask,
8971 /*SourceOffset*/ 4, /*DestOffset*/ 0);
8972 moveInputsToRightHalf(LToHInputs, HToHInputs, PSHUFLMask, HiMask, LoMask,
8973 /*SourceOffset*/ 0, /*DestOffset*/ 4);
8975 // Now enact all the shuffles we've computed to move the inputs into their
8977 if (!isNoopShuffleMask(PSHUFLMask))
8978 V = DAG.getNode(X86ISD::PSHUFLW, DL, MVT::v8i16, V,
8979 getV4X86ShuffleImm8ForMask(PSHUFLMask, DAG));
8980 if (!isNoopShuffleMask(PSHUFHMask))
8981 V = DAG.getNode(X86ISD::PSHUFHW, DL, MVT::v8i16, V,
8982 getV4X86ShuffleImm8ForMask(PSHUFHMask, DAG));
8983 if (!isNoopShuffleMask(PSHUFDMask))
8984 V = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16,
8985 DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32,
8986 DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, V),
8987 getV4X86ShuffleImm8ForMask(PSHUFDMask, DAG)));
8989 // At this point, each half should contain all its inputs, and we can then
8990 // just shuffle them into their final position.
8991 assert(std::count_if(LoMask.begin(), LoMask.end(),
8992 [](int M) { return M >= 4; }) == 0 &&
8993 "Failed to lift all the high half inputs to the low mask!");
8994 assert(std::count_if(HiMask.begin(), HiMask.end(),
8995 [](int M) { return M >= 0 && M < 4; }) == 0 &&
8996 "Failed to lift all the low half inputs to the high mask!");
8998 // Do a half shuffle for the low mask.
8999 if (!isNoopShuffleMask(LoMask))
9000 V = DAG.getNode(X86ISD::PSHUFLW, DL, MVT::v8i16, V,
9001 getV4X86ShuffleImm8ForMask(LoMask, DAG));
9003 // Do a half shuffle with the high mask after shifting its values down.
9004 for (int &M : HiMask)
9007 if (!isNoopShuffleMask(HiMask))
9008 V = DAG.getNode(X86ISD::PSHUFHW, DL, MVT::v8i16, V,
9009 getV4X86ShuffleImm8ForMask(HiMask, DAG));
9014 /// \brief Detect whether the mask pattern should be lowered through
9017 /// This essentially tests whether viewing the mask as an interleaving of two
9018 /// sub-sequences reduces the cross-input traffic of a blend operation. If so,
9019 /// lowering it through interleaving is a significantly better strategy.
9020 static bool shouldLowerAsInterleaving(ArrayRef<int> Mask) {
9021 int NumEvenInputs[2] = {0, 0};
9022 int NumOddInputs[2] = {0, 0};
9023 int NumLoInputs[2] = {0, 0};
9024 int NumHiInputs[2] = {0, 0};
9025 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
9029 int InputIdx = Mask[i] >= Size;
9032 ++NumLoInputs[InputIdx];
9034 ++NumHiInputs[InputIdx];
9037 ++NumEvenInputs[InputIdx];
9039 ++NumOddInputs[InputIdx];
9042 // The minimum number of cross-input results for both the interleaved and
9043 // split cases. If interleaving results in fewer cross-input results, return
9045 int InterleavedCrosses = std::min(NumEvenInputs[1] + NumOddInputs[0],
9046 NumEvenInputs[0] + NumOddInputs[1]);
9047 int SplitCrosses = std::min(NumLoInputs[1] + NumHiInputs[0],
9048 NumLoInputs[0] + NumHiInputs[1]);
9049 return InterleavedCrosses < SplitCrosses;
9052 /// \brief Blend two v8i16 vectors using a naive unpack strategy.
9054 /// This strategy only works when the inputs from each vector fit into a single
9055 /// half of that vector, and generally there are not so many inputs as to leave
9056 /// the in-place shuffles required highly constrained (and thus expensive). It
9057 /// shifts all the inputs into a single side of both input vectors and then
9058 /// uses an unpack to interleave these inputs in a single vector. At that
9059 /// point, we will fall back on the generic single input shuffle lowering.
9060 static SDValue lowerV8I16BasicBlendVectorShuffle(SDLoc DL, SDValue V1,
9062 MutableArrayRef<int> Mask,
9063 const X86Subtarget *Subtarget,
9064 SelectionDAG &DAG) {
9065 assert(V1.getSimpleValueType() == MVT::v8i16 && "Bad input type!");
9066 assert(V2.getSimpleValueType() == MVT::v8i16 && "Bad input type!");
9067 SmallVector<int, 3> LoV1Inputs, HiV1Inputs, LoV2Inputs, HiV2Inputs;
9068 for (int i = 0; i < 8; ++i)
9069 if (Mask[i] >= 0 && Mask[i] < 4)
9070 LoV1Inputs.push_back(i);
9071 else if (Mask[i] >= 4 && Mask[i] < 8)
9072 HiV1Inputs.push_back(i);
9073 else if (Mask[i] >= 8 && Mask[i] < 12)
9074 LoV2Inputs.push_back(i);
9075 else if (Mask[i] >= 12)
9076 HiV2Inputs.push_back(i);
9078 int NumV1Inputs = LoV1Inputs.size() + HiV1Inputs.size();
9079 int NumV2Inputs = LoV2Inputs.size() + HiV2Inputs.size();
9082 assert(NumV1Inputs > 0 && NumV1Inputs <= 3 && "At most 3 inputs supported");
9083 assert(NumV2Inputs > 0 && NumV2Inputs <= 3 && "At most 3 inputs supported");
9084 assert(NumV1Inputs + NumV2Inputs <= 4 && "At most 4 combined inputs");
9086 bool MergeFromLo = LoV1Inputs.size() + LoV2Inputs.size() >=
9087 HiV1Inputs.size() + HiV2Inputs.size();
9089 auto moveInputsToHalf = [&](SDValue V, ArrayRef<int> LoInputs,
9090 ArrayRef<int> HiInputs, bool MoveToLo,
9092 ArrayRef<int> GoodInputs = MoveToLo ? LoInputs : HiInputs;
9093 ArrayRef<int> BadInputs = MoveToLo ? HiInputs : LoInputs;
9094 if (BadInputs.empty())
9097 int MoveMask[] = {-1, -1, -1, -1, -1, -1, -1, -1};
9098 int MoveOffset = MoveToLo ? 0 : 4;
9100 if (GoodInputs.empty()) {
9101 for (int BadInput : BadInputs) {
9102 MoveMask[Mask[BadInput] % 4 + MoveOffset] = Mask[BadInput] - MaskOffset;
9103 Mask[BadInput] = Mask[BadInput] % 4 + MoveOffset + MaskOffset;
9106 if (GoodInputs.size() == 2) {
9107 // If the low inputs are spread across two dwords, pack them into
9109 MoveMask[MoveOffset] = Mask[GoodInputs[0]] - MaskOffset;
9110 MoveMask[MoveOffset + 1] = Mask[GoodInputs[1]] - MaskOffset;
9111 Mask[GoodInputs[0]] = MoveOffset + MaskOffset;
9112 Mask[GoodInputs[1]] = MoveOffset + 1 + MaskOffset;
9114 // Otherwise pin the good inputs.
9115 for (int GoodInput : GoodInputs)
9116 MoveMask[Mask[GoodInput] - MaskOffset] = Mask[GoodInput] - MaskOffset;
9119 if (BadInputs.size() == 2) {
9120 // If we have two bad inputs then there may be either one or two good
9121 // inputs fixed in place. Find a fixed input, and then find the *other*
9122 // two adjacent indices by using modular arithmetic.
9124 std::find_if(std::begin(MoveMask) + MoveOffset, std::end(MoveMask),
9125 [](int M) { return M >= 0; }) -
9126 std::begin(MoveMask);
9128 ((((GoodMaskIdx - MoveOffset) & ~1) + 2) % 4) + MoveOffset;
9129 assert(MoveMask[MoveMaskIdx] == -1 && "Expected empty slot");
9130 assert(MoveMask[MoveMaskIdx + 1] == -1 && "Expected empty slot");
9131 MoveMask[MoveMaskIdx] = Mask[BadInputs[0]] - MaskOffset;
9132 MoveMask[MoveMaskIdx + 1] = Mask[BadInputs[1]] - MaskOffset;
9133 Mask[BadInputs[0]] = MoveMaskIdx + MaskOffset;
9134 Mask[BadInputs[1]] = MoveMaskIdx + 1 + MaskOffset;
9136 assert(BadInputs.size() == 1 && "All sizes handled");
9137 int MoveMaskIdx = std::find(std::begin(MoveMask) + MoveOffset,
9138 std::end(MoveMask), -1) -
9139 std::begin(MoveMask);
9140 MoveMask[MoveMaskIdx] = Mask[BadInputs[0]] - MaskOffset;
9141 Mask[BadInputs[0]] = MoveMaskIdx + MaskOffset;
9145 return DAG.getVectorShuffle(MVT::v8i16, DL, V, DAG.getUNDEF(MVT::v8i16),
9148 V1 = moveInputsToHalf(V1, LoV1Inputs, HiV1Inputs, MergeFromLo,
9150 V2 = moveInputsToHalf(V2, LoV2Inputs, HiV2Inputs, MergeFromLo,
9153 // FIXME: Select an interleaving of the merge of V1 and V2 that minimizes
9154 // cross-half traffic in the final shuffle.
9156 // Munge the mask to be a single-input mask after the unpack merges the
9160 M = 2 * (M % 4) + (M / 8);
9162 return DAG.getVectorShuffle(
9163 MVT::v8i16, DL, DAG.getNode(MergeFromLo ? X86ISD::UNPCKL : X86ISD::UNPCKH,
9164 DL, MVT::v8i16, V1, V2),
9165 DAG.getUNDEF(MVT::v8i16), Mask);
9168 /// \brief Generic lowering of 8-lane i16 shuffles.
9170 /// This handles both single-input shuffles and combined shuffle/blends with
9171 /// two inputs. The single input shuffles are immediately delegated to
9172 /// a dedicated lowering routine.
9174 /// The blends are lowered in one of three fundamental ways. If there are few
9175 /// enough inputs, it delegates to a basic UNPCK-based strategy. If the shuffle
9176 /// of the input is significantly cheaper when lowered as an interleaving of
9177 /// the two inputs, try to interleave them. Otherwise, blend the low and high
9178 /// halves of the inputs separately (making them have relatively few inputs)
9179 /// and then concatenate them.
9180 static SDValue lowerV8I16VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9181 const X86Subtarget *Subtarget,
9182 SelectionDAG &DAG) {
9184 assert(Op.getSimpleValueType() == MVT::v8i16 && "Bad shuffle type!");
9185 assert(V1.getSimpleValueType() == MVT::v8i16 && "Bad operand type!");
9186 assert(V2.getSimpleValueType() == MVT::v8i16 && "Bad operand type!");
9187 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9188 ArrayRef<int> OrigMask = SVOp->getMask();
9189 int MaskStorage[8] = {OrigMask[0], OrigMask[1], OrigMask[2], OrigMask[3],
9190 OrigMask[4], OrigMask[5], OrigMask[6], OrigMask[7]};
9191 MutableArrayRef<int> Mask(MaskStorage);
9193 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
9195 // Whenever we can lower this as a zext, that instruction is strictly faster
9196 // than any alternative.
9197 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(
9198 DL, MVT::v8i16, V1, V2, OrigMask, Subtarget, DAG))
9201 auto isV1 = [](int M) { return M >= 0 && M < 8; };
9202 auto isV2 = [](int M) { return M >= 8; };
9204 int NumV1Inputs = std::count_if(Mask.begin(), Mask.end(), isV1);
9205 int NumV2Inputs = std::count_if(Mask.begin(), Mask.end(), isV2);
9207 if (NumV2Inputs == 0)
9208 return lowerV8I16SingleInputVectorShuffle(DL, V1, Mask, Subtarget, DAG);
9210 assert(NumV1Inputs > 0 && "All single-input shuffles should be canonicalized "
9211 "to be V1-input shuffles.");
9213 // There are special ways we can lower some single-element blends.
9214 if (NumV2Inputs == 1)
9215 if (SDValue V = lowerVectorShuffleAsElementInsertion(MVT::v8i16, DL, V1, V2,
9216 Mask, Subtarget, DAG))
9219 // Use dedicated unpack instructions for masks that match their pattern.
9220 if (isShuffleEquivalent(Mask, 0, 8, 1, 9, 2, 10, 3, 11))
9221 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8i16, V1, V2);
9222 if (isShuffleEquivalent(Mask, 4, 12, 5, 13, 6, 14, 7, 15))
9223 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8i16, V1, V2);
9225 if (Subtarget->hasSSE41())
9226 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v8i16, V1, V2, Mask,
9230 // Try to use byte shift instructions.
9231 if (SDValue Shift = lowerVectorShuffleAsByteShift(
9232 DL, MVT::v8i16, V1, V2, Mask, DAG))
9235 // Try to use byte rotation instructions.
9236 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
9237 DL, MVT::v8i16, V1, V2, Mask, Subtarget, DAG))
9240 if (NumV1Inputs + NumV2Inputs <= 4)
9241 return lowerV8I16BasicBlendVectorShuffle(DL, V1, V2, Mask, Subtarget, DAG);
9243 // Check whether an interleaving lowering is likely to be more efficient.
9244 // This isn't perfect but it is a strong heuristic that tends to work well on
9245 // the kinds of shuffles that show up in practice.
9247 // FIXME: Handle 1x, 2x, and 4x interleaving.
9248 if (shouldLowerAsInterleaving(Mask)) {
9249 // FIXME: Figure out whether we should pack these into the low or high
9252 int EMask[8], OMask[8];
9253 for (int i = 0; i < 4; ++i) {
9254 EMask[i] = Mask[2*i];
9255 OMask[i] = Mask[2*i + 1];
9260 SDValue Evens = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, EMask);
9261 SDValue Odds = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, OMask);
9263 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8i16, Evens, Odds);
9266 int LoBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9267 int HiBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9269 for (int i = 0; i < 4; ++i) {
9270 LoBlendMask[i] = Mask[i];
9271 HiBlendMask[i] = Mask[i + 4];
9274 SDValue LoV = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, LoBlendMask);
9275 SDValue HiV = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, HiBlendMask);
9276 LoV = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, LoV);
9277 HiV = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, HiV);
9279 return DAG.getNode(ISD::BITCAST, DL, MVT::v8i16,
9280 DAG.getNode(X86ISD::UNPCKL, DL, MVT::v2i64, LoV, HiV));
9283 /// \brief Check whether a compaction lowering can be done by dropping even
9284 /// elements and compute how many times even elements must be dropped.
9286 /// This handles shuffles which take every Nth element where N is a power of
9287 /// two. Example shuffle masks:
9289 /// N = 1: 0, 2, 4, 6, 8, 10, 12, 14, 0, 2, 4, 6, 8, 10, 12, 14
9290 /// N = 1: 0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30
9291 /// N = 2: 0, 4, 8, 12, 0, 4, 8, 12, 0, 4, 8, 12, 0, 4, 8, 12
9292 /// N = 2: 0, 4, 8, 12, 16, 20, 24, 28, 0, 4, 8, 12, 16, 20, 24, 28
9293 /// N = 3: 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 0, 8
9294 /// N = 3: 0, 8, 16, 24, 0, 8, 16, 24, 0, 8, 16, 24, 0, 8, 16, 24
9296 /// Any of these lanes can of course be undef.
9298 /// This routine only supports N <= 3.
9299 /// FIXME: Evaluate whether either AVX or AVX-512 have any opportunities here
9302 /// \returns N above, or the number of times even elements must be dropped if
9303 /// there is such a number. Otherwise returns zero.
9304 static int canLowerByDroppingEvenElements(ArrayRef<int> Mask) {
9305 // Figure out whether we're looping over two inputs or just one.
9306 bool IsSingleInput = isSingleInputShuffleMask(Mask);
9308 // The modulus for the shuffle vector entries is based on whether this is
9309 // a single input or not.
9310 int ShuffleModulus = Mask.size() * (IsSingleInput ? 1 : 2);
9311 assert(isPowerOf2_32((uint32_t)ShuffleModulus) &&
9312 "We should only be called with masks with a power-of-2 size!");
9314 uint64_t ModMask = (uint64_t)ShuffleModulus - 1;
9316 // We track whether the input is viable for all power-of-2 strides 2^1, 2^2,
9317 // and 2^3 simultaneously. This is because we may have ambiguity with
9318 // partially undef inputs.
9319 bool ViableForN[3] = {true, true, true};
9321 for (int i = 0, e = Mask.size(); i < e; ++i) {
9322 // Ignore undef lanes, we'll optimistically collapse them to the pattern we
9327 bool IsAnyViable = false;
9328 for (unsigned j = 0; j != array_lengthof(ViableForN); ++j)
9329 if (ViableForN[j]) {
9332 // The shuffle mask must be equal to (i * 2^N) % M.
9333 if ((uint64_t)Mask[i] == (((uint64_t)i << N) & ModMask))
9336 ViableForN[j] = false;
9338 // Early exit if we exhaust the possible powers of two.
9343 for (unsigned j = 0; j != array_lengthof(ViableForN); ++j)
9347 // Return 0 as there is no viable power of two.
9351 /// \brief Generic lowering of v16i8 shuffles.
9353 /// This is a hybrid strategy to lower v16i8 vectors. It first attempts to
9354 /// detect any complexity reducing interleaving. If that doesn't help, it uses
9355 /// UNPCK to spread the i8 elements across two i16-element vectors, and uses
9356 /// the existing lowering for v8i16 blends on each half, finally PACK-ing them
9358 static SDValue lowerV16I8VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9359 const X86Subtarget *Subtarget,
9360 SelectionDAG &DAG) {
9362 assert(Op.getSimpleValueType() == MVT::v16i8 && "Bad shuffle type!");
9363 assert(V1.getSimpleValueType() == MVT::v16i8 && "Bad operand type!");
9364 assert(V2.getSimpleValueType() == MVT::v16i8 && "Bad operand type!");
9365 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9366 ArrayRef<int> OrigMask = SVOp->getMask();
9367 assert(OrigMask.size() == 16 && "Unexpected mask size for v16 shuffle!");
9369 // Try to use byte shift instructions.
9370 if (SDValue Shift = lowerVectorShuffleAsByteShift(
9371 DL, MVT::v16i8, V1, V2, OrigMask, DAG))
9374 // Try to use byte rotation instructions.
9375 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
9376 DL, MVT::v16i8, V1, V2, OrigMask, Subtarget, DAG))
9379 // Try to use a zext lowering.
9380 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(
9381 DL, MVT::v16i8, V1, V2, OrigMask, Subtarget, DAG))
9384 int MaskStorage[16] = {
9385 OrigMask[0], OrigMask[1], OrigMask[2], OrigMask[3],
9386 OrigMask[4], OrigMask[5], OrigMask[6], OrigMask[7],
9387 OrigMask[8], OrigMask[9], OrigMask[10], OrigMask[11],
9388 OrigMask[12], OrigMask[13], OrigMask[14], OrigMask[15]};
9389 MutableArrayRef<int> Mask(MaskStorage);
9390 MutableArrayRef<int> LoMask = Mask.slice(0, 8);
9391 MutableArrayRef<int> HiMask = Mask.slice(8, 8);
9394 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 16; });
9396 // For single-input shuffles, there are some nicer lowering tricks we can use.
9397 if (NumV2Elements == 0) {
9398 // Check for being able to broadcast a single element.
9399 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v16i8, DL, V1,
9400 Mask, Subtarget, DAG))
9403 // Check whether we can widen this to an i16 shuffle by duplicating bytes.
9404 // Notably, this handles splat and partial-splat shuffles more efficiently.
9405 // However, it only makes sense if the pre-duplication shuffle simplifies
9406 // things significantly. Currently, this means we need to be able to
9407 // express the pre-duplication shuffle as an i16 shuffle.
9409 // FIXME: We should check for other patterns which can be widened into an
9410 // i16 shuffle as well.
9411 auto canWidenViaDuplication = [](ArrayRef<int> Mask) {
9412 for (int i = 0; i < 16; i += 2)
9413 if (Mask[i] != -1 && Mask[i + 1] != -1 && Mask[i] != Mask[i + 1])
9418 auto tryToWidenViaDuplication = [&]() -> SDValue {
9419 if (!canWidenViaDuplication(Mask))
9421 SmallVector<int, 4> LoInputs;
9422 std::copy_if(Mask.begin(), Mask.end(), std::back_inserter(LoInputs),
9423 [](int M) { return M >= 0 && M < 8; });
9424 std::sort(LoInputs.begin(), LoInputs.end());
9425 LoInputs.erase(std::unique(LoInputs.begin(), LoInputs.end()),
9427 SmallVector<int, 4> HiInputs;
9428 std::copy_if(Mask.begin(), Mask.end(), std::back_inserter(HiInputs),
9429 [](int M) { return M >= 8; });
9430 std::sort(HiInputs.begin(), HiInputs.end());
9431 HiInputs.erase(std::unique(HiInputs.begin(), HiInputs.end()),
9434 bool TargetLo = LoInputs.size() >= HiInputs.size();
9435 ArrayRef<int> InPlaceInputs = TargetLo ? LoInputs : HiInputs;
9436 ArrayRef<int> MovingInputs = TargetLo ? HiInputs : LoInputs;
9438 int PreDupI16Shuffle[] = {-1, -1, -1, -1, -1, -1, -1, -1};
9439 SmallDenseMap<int, int, 8> LaneMap;
9440 for (int I : InPlaceInputs) {
9441 PreDupI16Shuffle[I/2] = I/2;
9444 int j = TargetLo ? 0 : 4, je = j + 4;
9445 for (int i = 0, ie = MovingInputs.size(); i < ie; ++i) {
9446 // Check if j is already a shuffle of this input. This happens when
9447 // there are two adjacent bytes after we move the low one.
9448 if (PreDupI16Shuffle[j] != MovingInputs[i] / 2) {
9449 // If we haven't yet mapped the input, search for a slot into which
9451 while (j < je && PreDupI16Shuffle[j] != -1)
9455 // We can't place the inputs into a single half with a simple i16 shuffle, so bail.
9458 // Map this input with the i16 shuffle.
9459 PreDupI16Shuffle[j] = MovingInputs[i] / 2;
9462 // Update the lane map based on the mapping we ended up with.
9463 LaneMap[MovingInputs[i]] = 2 * j + MovingInputs[i] % 2;
9466 ISD::BITCAST, DL, MVT::v16i8,
9467 DAG.getVectorShuffle(MVT::v8i16, DL,
9468 DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V1),
9469 DAG.getUNDEF(MVT::v8i16), PreDupI16Shuffle));
9471 // Unpack the bytes to form the i16s that will be shuffled into place.
9472 V1 = DAG.getNode(TargetLo ? X86ISD::UNPCKL : X86ISD::UNPCKH, DL,
9473 MVT::v16i8, V1, V1);
9475 int PostDupI16Shuffle[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9476 for (int i = 0; i < 16; ++i)
9477 if (Mask[i] != -1) {
9478 int MappedMask = LaneMap[Mask[i]] - (TargetLo ? 0 : 8);
9479 assert(MappedMask < 8 && "Invalid v8 shuffle mask!");
9480 if (PostDupI16Shuffle[i / 2] == -1)
9481 PostDupI16Shuffle[i / 2] = MappedMask;
9483 assert(PostDupI16Shuffle[i / 2] == MappedMask &&
9484 "Conflicting entrties in the original shuffle!");
9487 ISD::BITCAST, DL, MVT::v16i8,
9488 DAG.getVectorShuffle(MVT::v8i16, DL,
9489 DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V1),
9490 DAG.getUNDEF(MVT::v8i16), PostDupI16Shuffle));
9492 if (SDValue V = tryToWidenViaDuplication())
9496 // Check whether an interleaving lowering is likely to be more efficient.
9497 // This isn't perfect but it is a strong heuristic that tends to work well on
9498 // the kinds of shuffles that show up in practice.
9500 // FIXME: We need to handle other interleaving widths (i16, i32, ...).
9501 if (shouldLowerAsInterleaving(Mask)) {
9502 int NumLoHalf = std::count_if(Mask.begin(), Mask.end(), [](int M) {
9503 return (M >= 0 && M < 8) || (M >= 16 && M < 24);
9505 int NumHiHalf = std::count_if(Mask.begin(), Mask.end(), [](int M) {
9506 return (M >= 8 && M < 16) || M >= 24;
9508 int EMask[16] = {-1, -1, -1, -1, -1, -1, -1, -1,
9509 -1, -1, -1, -1, -1, -1, -1, -1};
9510 int OMask[16] = {-1, -1, -1, -1, -1, -1, -1, -1,
9511 -1, -1, -1, -1, -1, -1, -1, -1};
9512 bool UnpackLo = NumLoHalf >= NumHiHalf;
9513 MutableArrayRef<int> TargetEMask(UnpackLo ? EMask : EMask + 8, 8);
9514 MutableArrayRef<int> TargetOMask(UnpackLo ? OMask : OMask + 8, 8);
9515 for (int i = 0; i < 8; ++i) {
9516 TargetEMask[i] = Mask[2 * i];
9517 TargetOMask[i] = Mask[2 * i + 1];
9520 SDValue Evens = DAG.getVectorShuffle(MVT::v16i8, DL, V1, V2, EMask);
9521 SDValue Odds = DAG.getVectorShuffle(MVT::v16i8, DL, V1, V2, OMask);
9523 return DAG.getNode(UnpackLo ? X86ISD::UNPCKL : X86ISD::UNPCKH, DL,
9524 MVT::v16i8, Evens, Odds);
9527 // Check for SSSE3 which lets us lower all v16i8 shuffles much more directly
9528 // with PSHUFB. It is important to do this before we attempt to generate any
9529 // blends but after all of the single-input lowerings. If the single input
9530 // lowerings can find an instruction sequence that is faster than a PSHUFB, we
9531 // want to preserve that and we can DAG combine any longer sequences into
9532 // a PSHUFB in the end. But once we start blending from multiple inputs,
9533 // the complexity of DAG combining bad patterns back into PSHUFB is too high,
9534 // and there are *very* few patterns that would actually be faster than the
9535 // PSHUFB approach because of its ability to zero lanes.
9537 // FIXME: The only exceptions to the above are blends which are exact
9538 // interleavings with direct instructions supporting them. We currently don't
9539 // handle those well here.
9540 if (Subtarget->hasSSSE3()) {
9543 for (int i = 0; i < 16; ++i)
9544 if (Mask[i] == -1) {
9545 V1Mask[i] = V2Mask[i] = DAG.getUNDEF(MVT::i8);
9547 V1Mask[i] = DAG.getConstant(Mask[i] < 16 ? Mask[i] : 0x80, MVT::i8);
9549 DAG.getConstant(Mask[i] < 16 ? 0x80 : Mask[i] - 16, MVT::i8);
9551 V1 = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8, V1,
9552 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v16i8, V1Mask));
9553 if (isSingleInputShuffleMask(Mask))
9554 return V1; // Single inputs are easy.
9556 // Otherwise, blend the two.
9557 V2 = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8, V2,
9558 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v16i8, V2Mask));
9559 return DAG.getNode(ISD::OR, DL, MVT::v16i8, V1, V2);
9562 // There are special ways we can lower some single-element blends.
9563 if (NumV2Elements == 1)
9564 if (SDValue V = lowerVectorShuffleAsElementInsertion(MVT::v16i8, DL, V1, V2,
9565 Mask, Subtarget, DAG))
9568 // Check whether a compaction lowering can be done. This handles shuffles
9569 // which take every Nth element for some even N. See the helper function for
9572 // We special case these as they can be particularly efficiently handled with
9573 // the PACKUSB instruction on x86 and they show up in common patterns of
9574 // rearranging bytes to truncate wide elements.
9575 if (int NumEvenDrops = canLowerByDroppingEvenElements(Mask)) {
9576 // NumEvenDrops is the power of two stride of the elements. Another way of
9577 // thinking about it is that we need to drop the even elements this many
9578 // times to get the original input.
9579 bool IsSingleInput = isSingleInputShuffleMask(Mask);
9581 // First we need to zero all the dropped bytes.
9582 assert(NumEvenDrops <= 3 &&
9583 "No support for dropping even elements more than 3 times.");
9584 // We use the mask type to pick which bytes are preserved based on how many
9585 // elements are dropped.
9586 MVT MaskVTs[] = { MVT::v8i16, MVT::v4i32, MVT::v2i64 };
9587 SDValue ByteClearMask =
9588 DAG.getNode(ISD::BITCAST, DL, MVT::v16i8,
9589 DAG.getConstant(0xFF, MaskVTs[NumEvenDrops - 1]));
9590 V1 = DAG.getNode(ISD::AND, DL, MVT::v16i8, V1, ByteClearMask);
9592 V2 = DAG.getNode(ISD::AND, DL, MVT::v16i8, V2, ByteClearMask);
9594 // Now pack things back together.
9595 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V1);
9596 V2 = IsSingleInput ? V1 : DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V2);
9597 SDValue Result = DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8, V1, V2);
9598 for (int i = 1; i < NumEvenDrops; ++i) {
9599 Result = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, Result);
9600 Result = DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8, Result, Result);
9606 int V1LoBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9607 int V1HiBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9608 int V2LoBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9609 int V2HiBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9611 auto buildBlendMasks = [](MutableArrayRef<int> HalfMask,
9612 MutableArrayRef<int> V1HalfBlendMask,
9613 MutableArrayRef<int> V2HalfBlendMask) {
9614 for (int i = 0; i < 8; ++i)
9615 if (HalfMask[i] >= 0 && HalfMask[i] < 16) {
9616 V1HalfBlendMask[i] = HalfMask[i];
9618 } else if (HalfMask[i] >= 16) {
9619 V2HalfBlendMask[i] = HalfMask[i] - 16;
9620 HalfMask[i] = i + 8;
9623 buildBlendMasks(LoMask, V1LoBlendMask, V2LoBlendMask);
9624 buildBlendMasks(HiMask, V1HiBlendMask, V2HiBlendMask);
9626 SDValue Zero = getZeroVector(MVT::v8i16, Subtarget, DAG, DL);
9628 auto buildLoAndHiV8s = [&](SDValue V, MutableArrayRef<int> LoBlendMask,
9629 MutableArrayRef<int> HiBlendMask) {
9631 // Check if any of the odd lanes in the v16i8 are used. If not, we can mask
9632 // them out and avoid using UNPCK{L,H} to extract the elements of V as
9634 if (std::none_of(LoBlendMask.begin(), LoBlendMask.end(),
9635 [](int M) { return M >= 0 && M % 2 == 1; }) &&
9636 std::none_of(HiBlendMask.begin(), HiBlendMask.end(),
9637 [](int M) { return M >= 0 && M % 2 == 1; })) {
9638 // Use a mask to drop the high bytes.
9639 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V);
9640 V1 = DAG.getNode(ISD::AND, DL, MVT::v8i16, V1,
9641 DAG.getConstant(0x00FF, MVT::v8i16));
9643 // This will be a single vector shuffle instead of a blend so nuke V2.
9644 V2 = DAG.getUNDEF(MVT::v8i16);
9646 // Squash the masks to point directly into V1.
9647 for (int &M : LoBlendMask)
9650 for (int &M : HiBlendMask)
9654 // Otherwise just unpack the low half of V into V1 and the high half into
9655 // V2 so that we can blend them as i16s.
9656 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16,
9657 DAG.getNode(X86ISD::UNPCKL, DL, MVT::v16i8, V, Zero));
9658 V2 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16,
9659 DAG.getNode(X86ISD::UNPCKH, DL, MVT::v16i8, V, Zero));
9662 SDValue BlendedLo = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, LoBlendMask);
9663 SDValue BlendedHi = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, HiBlendMask);
9664 return std::make_pair(BlendedLo, BlendedHi);
9666 SDValue V1Lo, V1Hi, V2Lo, V2Hi;
9667 std::tie(V1Lo, V1Hi) = buildLoAndHiV8s(V1, V1LoBlendMask, V1HiBlendMask);
9668 std::tie(V2Lo, V2Hi) = buildLoAndHiV8s(V2, V2LoBlendMask, V2HiBlendMask);
9670 SDValue LoV = DAG.getVectorShuffle(MVT::v8i16, DL, V1Lo, V2Lo, LoMask);
9671 SDValue HiV = DAG.getVectorShuffle(MVT::v8i16, DL, V1Hi, V2Hi, HiMask);
9673 return DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8, LoV, HiV);
9676 /// \brief Dispatching routine to lower various 128-bit x86 vector shuffles.
9678 /// This routine breaks down the specific type of 128-bit shuffle and
9679 /// dispatches to the lowering routines accordingly.
9680 static SDValue lower128BitVectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9681 MVT VT, const X86Subtarget *Subtarget,
9682 SelectionDAG &DAG) {
9683 switch (VT.SimpleTy) {
9685 return lowerV2I64VectorShuffle(Op, V1, V2, Subtarget, DAG);
9687 return lowerV2F64VectorShuffle(Op, V1, V2, Subtarget, DAG);
9689 return lowerV4I32VectorShuffle(Op, V1, V2, Subtarget, DAG);
9691 return lowerV4F32VectorShuffle(Op, V1, V2, Subtarget, DAG);
9693 return lowerV8I16VectorShuffle(Op, V1, V2, Subtarget, DAG);
9695 return lowerV16I8VectorShuffle(Op, V1, V2, Subtarget, DAG);
9698 llvm_unreachable("Unimplemented!");
9702 /// \brief Helper function to test whether a shuffle mask could be
9703 /// simplified by widening the elements being shuffled.
9705 /// Appends the mask for wider elements in WidenedMask if valid. Otherwise
9706 /// leaves it in an unspecified state.
9708 /// NOTE: This must handle normal vector shuffle masks and *target* vector
9709 /// shuffle masks. The latter have the special property of a '-2' representing
9710 /// a zero-ed lane of a vector.
9711 static bool canWidenShuffleElements(ArrayRef<int> Mask,
9712 SmallVectorImpl<int> &WidenedMask) {
9713 for (int i = 0, Size = Mask.size(); i < Size; i += 2) {
9714 // If both elements are undef, its trivial.
9715 if (Mask[i] == SM_SentinelUndef && Mask[i + 1] == SM_SentinelUndef) {
9716 WidenedMask.push_back(SM_SentinelUndef);
9720 // Check for an undef mask and a mask value properly aligned to fit with
9721 // a pair of values. If we find such a case, use the non-undef mask's value.
9722 if (Mask[i] == SM_SentinelUndef && Mask[i + 1] >= 0 && Mask[i + 1] % 2 == 1) {
9723 WidenedMask.push_back(Mask[i + 1] / 2);
9726 if (Mask[i + 1] == SM_SentinelUndef && Mask[i] >= 0 && Mask[i] % 2 == 0) {
9727 WidenedMask.push_back(Mask[i] / 2);
9731 // When zeroing, we need to spread the zeroing across both lanes to widen.
9732 if (Mask[i] == SM_SentinelZero || Mask[i + 1] == SM_SentinelZero) {
9733 if ((Mask[i] == SM_SentinelZero || Mask[i] == SM_SentinelUndef) &&
9734 (Mask[i + 1] == SM_SentinelZero || Mask[i + 1] == SM_SentinelUndef)) {
9735 WidenedMask.push_back(SM_SentinelZero);
9741 // Finally check if the two mask values are adjacent and aligned with
9743 if (Mask[i] != SM_SentinelUndef && Mask[i] % 2 == 0 && Mask[i] + 1 == Mask[i + 1]) {
9744 WidenedMask.push_back(Mask[i] / 2);
9748 // Otherwise we can't safely widen the elements used in this shuffle.
9751 assert(WidenedMask.size() == Mask.size() / 2 &&
9752 "Incorrect size of mask after widening the elements!");
9757 /// \brief Generic routine to split ector shuffle into half-sized shuffles.
9759 /// This routine just extracts two subvectors, shuffles them independently, and
9760 /// then concatenates them back together. This should work effectively with all
9761 /// AVX vector shuffle types.
9762 static SDValue splitAndLowerVectorShuffle(SDLoc DL, MVT VT, SDValue V1,
9763 SDValue V2, ArrayRef<int> Mask,
9764 SelectionDAG &DAG) {
9765 assert(VT.getSizeInBits() >= 256 &&
9766 "Only for 256-bit or wider vector shuffles!");
9767 assert(V1.getSimpleValueType() == VT && "Bad operand type!");
9768 assert(V2.getSimpleValueType() == VT && "Bad operand type!");
9770 ArrayRef<int> LoMask = Mask.slice(0, Mask.size() / 2);
9771 ArrayRef<int> HiMask = Mask.slice(Mask.size() / 2);
9773 int NumElements = VT.getVectorNumElements();
9774 int SplitNumElements = NumElements / 2;
9775 MVT ScalarVT = VT.getScalarType();
9776 MVT SplitVT = MVT::getVectorVT(ScalarVT, NumElements / 2);
9778 SDValue LoV1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SplitVT, V1,
9779 DAG.getIntPtrConstant(0));
9780 SDValue HiV1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SplitVT, V1,
9781 DAG.getIntPtrConstant(SplitNumElements));
9782 SDValue LoV2 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SplitVT, V2,
9783 DAG.getIntPtrConstant(0));
9784 SDValue HiV2 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SplitVT, V2,
9785 DAG.getIntPtrConstant(SplitNumElements));
9787 // Now create two 4-way blends of these half-width vectors.
9788 auto HalfBlend = [&](ArrayRef<int> HalfMask) {
9789 bool UseLoV1 = false, UseHiV1 = false, UseLoV2 = false, UseHiV2 = false;
9790 SmallVector<int, 32> V1BlendMask, V2BlendMask, BlendMask;
9791 for (int i = 0; i < SplitNumElements; ++i) {
9792 int M = HalfMask[i];
9793 if (M >= NumElements) {
9794 if (M >= NumElements + SplitNumElements)
9798 V2BlendMask.push_back(M - NumElements);
9799 V1BlendMask.push_back(-1);
9800 BlendMask.push_back(SplitNumElements + i);
9801 } else if (M >= 0) {
9802 if (M >= SplitNumElements)
9806 V2BlendMask.push_back(-1);
9807 V1BlendMask.push_back(M);
9808 BlendMask.push_back(i);
9810 V2BlendMask.push_back(-1);
9811 V1BlendMask.push_back(-1);
9812 BlendMask.push_back(-1);
9816 // Because the lowering happens after all combining takes place, we need to
9817 // manually combine these blend masks as much as possible so that we create
9818 // a minimal number of high-level vector shuffle nodes.
9820 // First try just blending the halves of V1 or V2.
9821 if (!UseLoV1 && !UseHiV1 && !UseLoV2 && !UseHiV2)
9822 return DAG.getUNDEF(SplitVT);
9823 if (!UseLoV2 && !UseHiV2)
9824 return DAG.getVectorShuffle(SplitVT, DL, LoV1, HiV1, V1BlendMask);
9825 if (!UseLoV1 && !UseHiV1)
9826 return DAG.getVectorShuffle(SplitVT, DL, LoV2, HiV2, V2BlendMask);
9828 SDValue V1Blend, V2Blend;
9829 if (UseLoV1 && UseHiV1) {
9831 DAG.getVectorShuffle(SplitVT, DL, LoV1, HiV1, V1BlendMask);
9833 // We only use half of V1 so map the usage down into the final blend mask.
9834 V1Blend = UseLoV1 ? LoV1 : HiV1;
9835 for (int i = 0; i < SplitNumElements; ++i)
9836 if (BlendMask[i] >= 0 && BlendMask[i] < SplitNumElements)
9837 BlendMask[i] = V1BlendMask[i] - (UseLoV1 ? 0 : SplitNumElements);
9839 if (UseLoV2 && UseHiV2) {
9841 DAG.getVectorShuffle(SplitVT, DL, LoV2, HiV2, V2BlendMask);
9843 // We only use half of V2 so map the usage down into the final blend mask.
9844 V2Blend = UseLoV2 ? LoV2 : HiV2;
9845 for (int i = 0; i < SplitNumElements; ++i)
9846 if (BlendMask[i] >= SplitNumElements)
9847 BlendMask[i] = V2BlendMask[i] + (UseLoV2 ? SplitNumElements : 0);
9849 return DAG.getVectorShuffle(SplitVT, DL, V1Blend, V2Blend, BlendMask);
9851 SDValue Lo = HalfBlend(LoMask);
9852 SDValue Hi = HalfBlend(HiMask);
9853 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, Lo, Hi);
9856 /// \brief Either split a vector in halves or decompose the shuffles and the
9859 /// This is provided as a good fallback for many lowerings of non-single-input
9860 /// shuffles with more than one 128-bit lane. In those cases, we want to select
9861 /// between splitting the shuffle into 128-bit components and stitching those
9862 /// back together vs. extracting the single-input shuffles and blending those
9864 static SDValue lowerVectorShuffleAsSplitOrBlend(SDLoc DL, MVT VT, SDValue V1,
9865 SDValue V2, ArrayRef<int> Mask,
9866 SelectionDAG &DAG) {
9867 assert(!isSingleInputShuffleMask(Mask) && "This routine must not be used to "
9868 "lower single-input shuffles as it "
9869 "could then recurse on itself.");
9870 int Size = Mask.size();
9872 // If this can be modeled as a broadcast of two elements followed by a blend,
9873 // prefer that lowering. This is especially important because broadcasts can
9874 // often fold with memory operands.
9875 auto DoBothBroadcast = [&] {
9876 int V1BroadcastIdx = -1, V2BroadcastIdx = -1;
9879 if (V2BroadcastIdx == -1)
9880 V2BroadcastIdx = M - Size;
9881 else if (M - Size != V2BroadcastIdx)
9883 } else if (M >= 0) {
9884 if (V1BroadcastIdx == -1)
9886 else if (M != V1BroadcastIdx)
9891 if (DoBothBroadcast())
9892 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, VT, V1, V2, Mask,
9895 // If the inputs all stem from a single 128-bit lane of each input, then we
9896 // split them rather than blending because the split will decompose to
9897 // unusually few instructions.
9898 int LaneCount = VT.getSizeInBits() / 128;
9899 int LaneSize = Size / LaneCount;
9900 SmallBitVector LaneInputs[2];
9901 LaneInputs[0].resize(LaneCount, false);
9902 LaneInputs[1].resize(LaneCount, false);
9903 for (int i = 0; i < Size; ++i)
9905 LaneInputs[Mask[i] / Size][(Mask[i] % Size) / LaneSize] = true;
9906 if (LaneInputs[0].count() <= 1 && LaneInputs[1].count() <= 1)
9907 return splitAndLowerVectorShuffle(DL, VT, V1, V2, Mask, DAG);
9909 // Otherwise, just fall back to decomposed shuffles and a blend. This requires
9910 // that the decomposed single-input shuffles don't end up here.
9911 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, VT, V1, V2, Mask, DAG);
9914 /// \brief Lower a vector shuffle crossing multiple 128-bit lanes as
9915 /// a permutation and blend of those lanes.
9917 /// This essentially blends the out-of-lane inputs to each lane into the lane
9918 /// from a permuted copy of the vector. This lowering strategy results in four
9919 /// instructions in the worst case for a single-input cross lane shuffle which
9920 /// is lower than any other fully general cross-lane shuffle strategy I'm aware
9921 /// of. Special cases for each particular shuffle pattern should be handled
9922 /// prior to trying this lowering.
9923 static SDValue lowerVectorShuffleAsLanePermuteAndBlend(SDLoc DL, MVT VT,
9924 SDValue V1, SDValue V2,
9926 SelectionDAG &DAG) {
9927 // FIXME: This should probably be generalized for 512-bit vectors as well.
9928 assert(VT.getSizeInBits() == 256 && "Only for 256-bit vector shuffles!");
9929 int LaneSize = Mask.size() / 2;
9931 // If there are only inputs from one 128-bit lane, splitting will in fact be
9932 // less expensive. The flags track wether the given lane contains an element
9933 // that crosses to another lane.
9934 bool LaneCrossing[2] = {false, false};
9935 for (int i = 0, Size = Mask.size(); i < Size; ++i)
9936 if (Mask[i] >= 0 && (Mask[i] % Size) / LaneSize != i / LaneSize)
9937 LaneCrossing[(Mask[i] % Size) / LaneSize] = true;
9938 if (!LaneCrossing[0] || !LaneCrossing[1])
9939 return splitAndLowerVectorShuffle(DL, VT, V1, V2, Mask, DAG);
9941 if (isSingleInputShuffleMask(Mask)) {
9942 SmallVector<int, 32> FlippedBlendMask;
9943 for (int i = 0, Size = Mask.size(); i < Size; ++i)
9944 FlippedBlendMask.push_back(
9945 Mask[i] < 0 ? -1 : (((Mask[i] % Size) / LaneSize == i / LaneSize)
9947 : Mask[i] % LaneSize +
9948 (i / LaneSize) * LaneSize + Size));
9950 // Flip the vector, and blend the results which should now be in-lane. The
9951 // VPERM2X128 mask uses the low 2 bits for the low source and bits 4 and
9952 // 5 for the high source. The value 3 selects the high half of source 2 and
9953 // the value 2 selects the low half of source 2. We only use source 2 to
9954 // allow folding it into a memory operand.
9955 unsigned PERMMask = 3 | 2 << 4;
9956 SDValue Flipped = DAG.getNode(X86ISD::VPERM2X128, DL, VT, DAG.getUNDEF(VT),
9957 V1, DAG.getConstant(PERMMask, MVT::i8));
9958 return DAG.getVectorShuffle(VT, DL, V1, Flipped, FlippedBlendMask);
9961 // This now reduces to two single-input shuffles of V1 and V2 which at worst
9962 // will be handled by the above logic and a blend of the results, much like
9963 // other patterns in AVX.
9964 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, VT, V1, V2, Mask, DAG);
9967 /// \brief Handle lowering 2-lane 128-bit shuffles.
9968 static SDValue lowerV2X128VectorShuffle(SDLoc DL, MVT VT, SDValue V1,
9969 SDValue V2, ArrayRef<int> Mask,
9970 const X86Subtarget *Subtarget,
9971 SelectionDAG &DAG) {
9972 // Blends are faster and handle all the non-lane-crossing cases.
9973 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, VT, V1, V2, Mask,
9977 MVT SubVT = MVT::getVectorVT(VT.getVectorElementType(),
9978 VT.getVectorNumElements() / 2);
9979 // Check for patterns which can be matched with a single insert of a 128-bit
9981 if (isShuffleEquivalent(Mask, 0, 1, 0, 1) ||
9982 isShuffleEquivalent(Mask, 0, 1, 4, 5)) {
9983 SDValue LoV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SubVT, V1,
9984 DAG.getIntPtrConstant(0));
9985 SDValue HiV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SubVT,
9986 Mask[2] < 4 ? V1 : V2, DAG.getIntPtrConstant(0));
9987 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, LoV, HiV);
9989 if (isShuffleEquivalent(Mask, 0, 1, 6, 7)) {
9990 SDValue LoV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SubVT, V1,
9991 DAG.getIntPtrConstant(0));
9992 SDValue HiV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SubVT, V2,
9993 DAG.getIntPtrConstant(2));
9994 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, LoV, HiV);
9997 // Otherwise form a 128-bit permutation.
9998 // FIXME: Detect zero-vector inputs and use the VPERM2X128 to zero that half.
9999 unsigned PermMask = Mask[0] / 2 | (Mask[2] / 2) << 4;
10000 return DAG.getNode(X86ISD::VPERM2X128, DL, VT, V1, V2,
10001 DAG.getConstant(PermMask, MVT::i8));
10004 /// \brief Lower a vector shuffle by first fixing the 128-bit lanes and then
10005 /// shuffling each lane.
10007 /// This will only succeed when the result of fixing the 128-bit lanes results
10008 /// in a single-input non-lane-crossing shuffle with a repeating shuffle mask in
10009 /// each 128-bit lanes. This handles many cases where we can quickly blend away
10010 /// the lane crosses early and then use simpler shuffles within each lane.
10012 /// FIXME: It might be worthwhile at some point to support this without
10013 /// requiring the 128-bit lane-relative shuffles to be repeating, but currently
10014 /// in x86 only floating point has interesting non-repeating shuffles, and even
10015 /// those are still *marginally* more expensive.
10016 static SDValue lowerVectorShuffleByMerging128BitLanes(
10017 SDLoc DL, MVT VT, SDValue V1, SDValue V2, ArrayRef<int> Mask,
10018 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
10019 assert(!isSingleInputShuffleMask(Mask) &&
10020 "This is only useful with multiple inputs.");
10022 int Size = Mask.size();
10023 int LaneSize = 128 / VT.getScalarSizeInBits();
10024 int NumLanes = Size / LaneSize;
10025 assert(NumLanes > 1 && "Only handles 256-bit and wider shuffles.");
10027 // See if we can build a hypothetical 128-bit lane-fixing shuffle mask. Also
10028 // check whether the in-128-bit lane shuffles share a repeating pattern.
10029 SmallVector<int, 4> Lanes;
10030 Lanes.resize(NumLanes, -1);
10031 SmallVector<int, 4> InLaneMask;
10032 InLaneMask.resize(LaneSize, -1);
10033 for (int i = 0; i < Size; ++i) {
10037 int j = i / LaneSize;
10039 if (Lanes[j] < 0) {
10040 // First entry we've seen for this lane.
10041 Lanes[j] = Mask[i] / LaneSize;
10042 } else if (Lanes[j] != Mask[i] / LaneSize) {
10043 // This doesn't match the lane selected previously!
10047 // Check that within each lane we have a consistent shuffle mask.
10048 int k = i % LaneSize;
10049 if (InLaneMask[k] < 0) {
10050 InLaneMask[k] = Mask[i] % LaneSize;
10051 } else if (InLaneMask[k] != Mask[i] % LaneSize) {
10052 // This doesn't fit a repeating in-lane mask.
10057 // First shuffle the lanes into place.
10058 MVT LaneVT = MVT::getVectorVT(VT.isFloatingPoint() ? MVT::f64 : MVT::i64,
10059 VT.getSizeInBits() / 64);
10060 SmallVector<int, 8> LaneMask;
10061 LaneMask.resize(NumLanes * 2, -1);
10062 for (int i = 0; i < NumLanes; ++i)
10063 if (Lanes[i] >= 0) {
10064 LaneMask[2 * i + 0] = 2*Lanes[i] + 0;
10065 LaneMask[2 * i + 1] = 2*Lanes[i] + 1;
10068 V1 = DAG.getNode(ISD::BITCAST, DL, LaneVT, V1);
10069 V2 = DAG.getNode(ISD::BITCAST, DL, LaneVT, V2);
10070 SDValue LaneShuffle = DAG.getVectorShuffle(LaneVT, DL, V1, V2, LaneMask);
10072 // Cast it back to the type we actually want.
10073 LaneShuffle = DAG.getNode(ISD::BITCAST, DL, VT, LaneShuffle);
10075 // Now do a simple shuffle that isn't lane crossing.
10076 SmallVector<int, 8> NewMask;
10077 NewMask.resize(Size, -1);
10078 for (int i = 0; i < Size; ++i)
10080 NewMask[i] = (i / LaneSize) * LaneSize + Mask[i] % LaneSize;
10081 assert(!is128BitLaneCrossingShuffleMask(VT, NewMask) &&
10082 "Must not introduce lane crosses at this point!");
10084 return DAG.getVectorShuffle(VT, DL, LaneShuffle, DAG.getUNDEF(VT), NewMask);
10087 /// \brief Test whether the specified input (0 or 1) is in-place blended by the
10090 /// This returns true if the elements from a particular input are already in the
10091 /// slot required by the given mask and require no permutation.
10092 static bool isShuffleMaskInputInPlace(int Input, ArrayRef<int> Mask) {
10093 assert((Input == 0 || Input == 1) && "Only two inputs to shuffles.");
10094 int Size = Mask.size();
10095 for (int i = 0; i < Size; ++i)
10096 if (Mask[i] >= 0 && Mask[i] / Size == Input && Mask[i] % Size != i)
10102 /// \brief Handle lowering of 4-lane 64-bit floating point shuffles.
10104 /// Also ends up handling lowering of 4-lane 64-bit integer shuffles when AVX2
10105 /// isn't available.
10106 static SDValue lowerV4F64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10107 const X86Subtarget *Subtarget,
10108 SelectionDAG &DAG) {
10110 assert(V1.getSimpleValueType() == MVT::v4f64 && "Bad operand type!");
10111 assert(V2.getSimpleValueType() == MVT::v4f64 && "Bad operand type!");
10112 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10113 ArrayRef<int> Mask = SVOp->getMask();
10114 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
10116 SmallVector<int, 4> WidenedMask;
10117 if (canWidenShuffleElements(Mask, WidenedMask))
10118 return lowerV2X128VectorShuffle(DL, MVT::v4f64, V1, V2, Mask, Subtarget,
10121 if (isSingleInputShuffleMask(Mask)) {
10122 // Check for being able to broadcast a single element.
10123 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v4f64, DL, V1,
10124 Mask, Subtarget, DAG))
10127 if (!is128BitLaneCrossingShuffleMask(MVT::v4f64, Mask)) {
10128 // Non-half-crossing single input shuffles can be lowerid with an
10129 // interleaved permutation.
10130 unsigned VPERMILPMask = (Mask[0] == 1) | ((Mask[1] == 1) << 1) |
10131 ((Mask[2] == 3) << 2) | ((Mask[3] == 3) << 3);
10132 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v4f64, V1,
10133 DAG.getConstant(VPERMILPMask, MVT::i8));
10136 // With AVX2 we have direct support for this permutation.
10137 if (Subtarget->hasAVX2())
10138 return DAG.getNode(X86ISD::VPERMI, DL, MVT::v4f64, V1,
10139 getV4X86ShuffleImm8ForMask(Mask, DAG));
10141 // Otherwise, fall back.
10142 return lowerVectorShuffleAsLanePermuteAndBlend(DL, MVT::v4f64, V1, V2, Mask,
10146 // X86 has dedicated unpack instructions that can handle specific blend
10147 // operations: UNPCKH and UNPCKL.
10148 if (isShuffleEquivalent(Mask, 0, 4, 2, 6))
10149 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4f64, V1, V2);
10150 if (isShuffleEquivalent(Mask, 1, 5, 3, 7))
10151 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4f64, V1, V2);
10153 // If we have a single input to the zero element, insert that into V1 if we
10154 // can do so cheaply.
10155 int NumV2Elements =
10156 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; });
10157 if (NumV2Elements == 1 && Mask[0] >= 4)
10158 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
10159 MVT::v4f64, DL, V1, V2, Mask, Subtarget, DAG))
10162 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4f64, V1, V2, Mask,
10166 // Check if the blend happens to exactly fit that of SHUFPD.
10167 if ((Mask[0] == -1 || Mask[0] < 2) &&
10168 (Mask[1] == -1 || (Mask[1] >= 4 && Mask[1] < 6)) &&
10169 (Mask[2] == -1 || (Mask[2] >= 2 && Mask[2] < 4)) &&
10170 (Mask[3] == -1 || Mask[3] >= 6)) {
10171 unsigned SHUFPDMask = (Mask[0] == 1) | ((Mask[1] == 5) << 1) |
10172 ((Mask[2] == 3) << 2) | ((Mask[3] == 7) << 3);
10173 return DAG.getNode(X86ISD::SHUFP, DL, MVT::v4f64, V1, V2,
10174 DAG.getConstant(SHUFPDMask, MVT::i8));
10176 if ((Mask[0] == -1 || (Mask[0] >= 4 && Mask[0] < 6)) &&
10177 (Mask[1] == -1 || Mask[1] < 2) &&
10178 (Mask[2] == -1 || Mask[2] >= 6) &&
10179 (Mask[3] == -1 || (Mask[3] >= 2 && Mask[3] < 4))) {
10180 unsigned SHUFPDMask = (Mask[0] == 5) | ((Mask[1] == 1) << 1) |
10181 ((Mask[2] == 7) << 2) | ((Mask[3] == 3) << 3);
10182 return DAG.getNode(X86ISD::SHUFP, DL, MVT::v4f64, V2, V1,
10183 DAG.getConstant(SHUFPDMask, MVT::i8));
10186 // Try to simplify this by merging 128-bit lanes to enable a lane-based
10187 // shuffle. However, if we have AVX2 and either inputs are already in place,
10188 // we will be able to shuffle even across lanes the other input in a single
10189 // instruction so skip this pattern.
10190 if (!(Subtarget->hasAVX2() && (isShuffleMaskInputInPlace(0, Mask) ||
10191 isShuffleMaskInputInPlace(1, Mask))))
10192 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
10193 DL, MVT::v4f64, V1, V2, Mask, Subtarget, DAG))
10196 // If we have AVX2 then we always want to lower with a blend because an v4 we
10197 // can fully permute the elements.
10198 if (Subtarget->hasAVX2())
10199 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v4f64, V1, V2,
10202 // Otherwise fall back on generic lowering.
10203 return lowerVectorShuffleAsSplitOrBlend(DL, MVT::v4f64, V1, V2, Mask, DAG);
10206 /// \brief Handle lowering of 4-lane 64-bit integer shuffles.
10208 /// This routine is only called when we have AVX2 and thus a reasonable
10209 /// instruction set for v4i64 shuffling..
10210 static SDValue lowerV4I64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10211 const X86Subtarget *Subtarget,
10212 SelectionDAG &DAG) {
10214 assert(V1.getSimpleValueType() == MVT::v4i64 && "Bad operand type!");
10215 assert(V2.getSimpleValueType() == MVT::v4i64 && "Bad operand type!");
10216 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10217 ArrayRef<int> Mask = SVOp->getMask();
10218 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
10219 assert(Subtarget->hasAVX2() && "We can only lower v4i64 with AVX2!");
10221 SmallVector<int, 4> WidenedMask;
10222 if (canWidenShuffleElements(Mask, WidenedMask))
10223 return lowerV2X128VectorShuffle(DL, MVT::v4i64, V1, V2, Mask, Subtarget,
10226 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4i64, V1, V2, Mask,
10230 // Check for being able to broadcast a single element.
10231 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v4i64, DL, V1,
10232 Mask, Subtarget, DAG))
10235 // When the shuffle is mirrored between the 128-bit lanes of the unit, we can
10236 // use lower latency instructions that will operate on both 128-bit lanes.
10237 SmallVector<int, 2> RepeatedMask;
10238 if (is128BitLaneRepeatedShuffleMask(MVT::v4i64, Mask, RepeatedMask)) {
10239 if (isSingleInputShuffleMask(Mask)) {
10240 int PSHUFDMask[] = {-1, -1, -1, -1};
10241 for (int i = 0; i < 2; ++i)
10242 if (RepeatedMask[i] >= 0) {
10243 PSHUFDMask[2 * i] = 2 * RepeatedMask[i];
10244 PSHUFDMask[2 * i + 1] = 2 * RepeatedMask[i] + 1;
10246 return DAG.getNode(
10247 ISD::BITCAST, DL, MVT::v4i64,
10248 DAG.getNode(X86ISD::PSHUFD, DL, MVT::v8i32,
10249 DAG.getNode(ISD::BITCAST, DL, MVT::v8i32, V1),
10250 getV4X86ShuffleImm8ForMask(PSHUFDMask, DAG)));
10253 // Use dedicated unpack instructions for masks that match their pattern.
10254 if (isShuffleEquivalent(Mask, 0, 4, 2, 6))
10255 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4i64, V1, V2);
10256 if (isShuffleEquivalent(Mask, 1, 5, 3, 7))
10257 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4i64, V1, V2);
10260 // AVX2 provides a direct instruction for permuting a single input across
10262 if (isSingleInputShuffleMask(Mask))
10263 return DAG.getNode(X86ISD::VPERMI, DL, MVT::v4i64, V1,
10264 getV4X86ShuffleImm8ForMask(Mask, DAG));
10266 // Try to simplify this by merging 128-bit lanes to enable a lane-based
10267 // shuffle. However, if we have AVX2 and either inputs are already in place,
10268 // we will be able to shuffle even across lanes the other input in a single
10269 // instruction so skip this pattern.
10270 if (!(Subtarget->hasAVX2() && (isShuffleMaskInputInPlace(0, Mask) ||
10271 isShuffleMaskInputInPlace(1, Mask))))
10272 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
10273 DL, MVT::v4i64, V1, V2, Mask, Subtarget, DAG))
10276 // Otherwise fall back on generic blend lowering.
10277 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v4i64, V1, V2,
10281 /// \brief Handle lowering of 8-lane 32-bit floating point shuffles.
10283 /// Also ends up handling lowering of 8-lane 32-bit integer shuffles when AVX2
10284 /// isn't available.
10285 static SDValue lowerV8F32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10286 const X86Subtarget *Subtarget,
10287 SelectionDAG &DAG) {
10289 assert(V1.getSimpleValueType() == MVT::v8f32 && "Bad operand type!");
10290 assert(V2.getSimpleValueType() == MVT::v8f32 && "Bad operand type!");
10291 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10292 ArrayRef<int> Mask = SVOp->getMask();
10293 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
10295 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v8f32, V1, V2, Mask,
10299 // Check for being able to broadcast a single element.
10300 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v8f32, DL, V1,
10301 Mask, Subtarget, DAG))
10304 // If the shuffle mask is repeated in each 128-bit lane, we have many more
10305 // options to efficiently lower the shuffle.
10306 SmallVector<int, 4> RepeatedMask;
10307 if (is128BitLaneRepeatedShuffleMask(MVT::v8f32, Mask, RepeatedMask)) {
10308 assert(RepeatedMask.size() == 4 &&
10309 "Repeated masks must be half the mask width!");
10310 if (isSingleInputShuffleMask(Mask))
10311 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v8f32, V1,
10312 getV4X86ShuffleImm8ForMask(RepeatedMask, DAG));
10314 // Use dedicated unpack instructions for masks that match their pattern.
10315 if (isShuffleEquivalent(Mask, 0, 8, 1, 9, 4, 12, 5, 13))
10316 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8f32, V1, V2);
10317 if (isShuffleEquivalent(Mask, 2, 10, 3, 11, 6, 14, 7, 15))
10318 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8f32, V1, V2);
10320 // Otherwise, fall back to a SHUFPS sequence. Here it is important that we
10321 // have already handled any direct blends. We also need to squash the
10322 // repeated mask into a simulated v4f32 mask.
10323 for (int i = 0; i < 4; ++i)
10324 if (RepeatedMask[i] >= 8)
10325 RepeatedMask[i] -= 4;
10326 return lowerVectorShuffleWithSHUFPS(DL, MVT::v8f32, RepeatedMask, V1, V2, DAG);
10329 // If we have a single input shuffle with different shuffle patterns in the
10330 // two 128-bit lanes use the variable mask to VPERMILPS.
10331 if (isSingleInputShuffleMask(Mask)) {
10332 SDValue VPermMask[8];
10333 for (int i = 0; i < 8; ++i)
10334 VPermMask[i] = Mask[i] < 0 ? DAG.getUNDEF(MVT::i32)
10335 : DAG.getConstant(Mask[i], MVT::i32);
10336 if (!is128BitLaneCrossingShuffleMask(MVT::v8f32, Mask))
10337 return DAG.getNode(
10338 X86ISD::VPERMILPV, DL, MVT::v8f32, V1,
10339 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v8i32, VPermMask));
10341 if (Subtarget->hasAVX2())
10342 return DAG.getNode(X86ISD::VPERMV, DL, MVT::v8f32,
10343 DAG.getNode(ISD::BITCAST, DL, MVT::v8f32,
10344 DAG.getNode(ISD::BUILD_VECTOR, DL,
10345 MVT::v8i32, VPermMask)),
10348 // Otherwise, fall back.
10349 return lowerVectorShuffleAsLanePermuteAndBlend(DL, MVT::v8f32, V1, V2, Mask,
10353 // Try to simplify this by merging 128-bit lanes to enable a lane-based
10355 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
10356 DL, MVT::v8f32, V1, V2, Mask, Subtarget, DAG))
10359 // If we have AVX2 then we always want to lower with a blend because at v8 we
10360 // can fully permute the elements.
10361 if (Subtarget->hasAVX2())
10362 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v8f32, V1, V2,
10365 // Otherwise fall back on generic lowering.
10366 return lowerVectorShuffleAsSplitOrBlend(DL, MVT::v8f32, V1, V2, Mask, DAG);
10369 /// \brief Handle lowering of 8-lane 32-bit integer shuffles.
10371 /// This routine is only called when we have AVX2 and thus a reasonable
10372 /// instruction set for v8i32 shuffling..
10373 static SDValue lowerV8I32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10374 const X86Subtarget *Subtarget,
10375 SelectionDAG &DAG) {
10377 assert(V1.getSimpleValueType() == MVT::v8i32 && "Bad operand type!");
10378 assert(V2.getSimpleValueType() == MVT::v8i32 && "Bad operand type!");
10379 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10380 ArrayRef<int> Mask = SVOp->getMask();
10381 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
10382 assert(Subtarget->hasAVX2() && "We can only lower v8i32 with AVX2!");
10384 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v8i32, V1, V2, Mask,
10388 // Check for being able to broadcast a single element.
10389 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v8i32, DL, V1,
10390 Mask, Subtarget, DAG))
10393 // If the shuffle mask is repeated in each 128-bit lane we can use more
10394 // efficient instructions that mirror the shuffles across the two 128-bit
10396 SmallVector<int, 4> RepeatedMask;
10397 if (is128BitLaneRepeatedShuffleMask(MVT::v8i32, Mask, RepeatedMask)) {
10398 assert(RepeatedMask.size() == 4 && "Unexpected repeated mask size!");
10399 if (isSingleInputShuffleMask(Mask))
10400 return DAG.getNode(X86ISD::PSHUFD, DL, MVT::v8i32, V1,
10401 getV4X86ShuffleImm8ForMask(RepeatedMask, DAG));
10403 // Use dedicated unpack instructions for masks that match their pattern.
10404 if (isShuffleEquivalent(Mask, 0, 8, 1, 9, 4, 12, 5, 13))
10405 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8i32, V1, V2);
10406 if (isShuffleEquivalent(Mask, 2, 10, 3, 11, 6, 14, 7, 15))
10407 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8i32, V1, V2);
10410 // If the shuffle patterns aren't repeated but it is a single input, directly
10411 // generate a cross-lane VPERMD instruction.
10412 if (isSingleInputShuffleMask(Mask)) {
10413 SDValue VPermMask[8];
10414 for (int i = 0; i < 8; ++i)
10415 VPermMask[i] = Mask[i] < 0 ? DAG.getUNDEF(MVT::i32)
10416 : DAG.getConstant(Mask[i], MVT::i32);
10417 return DAG.getNode(
10418 X86ISD::VPERMV, DL, MVT::v8i32,
10419 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v8i32, VPermMask), V1);
10422 // Try to simplify this by merging 128-bit lanes to enable a lane-based
10424 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
10425 DL, MVT::v8i32, V1, V2, Mask, Subtarget, DAG))
10428 // Otherwise fall back on generic blend lowering.
10429 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v8i32, V1, V2,
10433 /// \brief Handle lowering of 16-lane 16-bit integer shuffles.
10435 /// This routine is only called when we have AVX2 and thus a reasonable
10436 /// instruction set for v16i16 shuffling..
10437 static SDValue lowerV16I16VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10438 const X86Subtarget *Subtarget,
10439 SelectionDAG &DAG) {
10441 assert(V1.getSimpleValueType() == MVT::v16i16 && "Bad operand type!");
10442 assert(V2.getSimpleValueType() == MVT::v16i16 && "Bad operand type!");
10443 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10444 ArrayRef<int> Mask = SVOp->getMask();
10445 assert(Mask.size() == 16 && "Unexpected mask size for v16 shuffle!");
10446 assert(Subtarget->hasAVX2() && "We can only lower v16i16 with AVX2!");
10448 // Check for being able to broadcast a single element.
10449 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v16i16, DL, V1,
10450 Mask, Subtarget, DAG))
10453 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v16i16, V1, V2, Mask,
10457 // Use dedicated unpack instructions for masks that match their pattern.
10458 if (isShuffleEquivalent(Mask,
10459 // First 128-bit lane:
10460 0, 16, 1, 17, 2, 18, 3, 19,
10461 // Second 128-bit lane:
10462 8, 24, 9, 25, 10, 26, 11, 27))
10463 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v16i16, V1, V2);
10464 if (isShuffleEquivalent(Mask,
10465 // First 128-bit lane:
10466 4, 20, 5, 21, 6, 22, 7, 23,
10467 // Second 128-bit lane:
10468 12, 28, 13, 29, 14, 30, 15, 31))
10469 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v16i16, V1, V2);
10471 if (isSingleInputShuffleMask(Mask)) {
10472 // There are no generalized cross-lane shuffle operations available on i16
10474 if (is128BitLaneCrossingShuffleMask(MVT::v16i16, Mask))
10475 return lowerVectorShuffleAsLanePermuteAndBlend(DL, MVT::v16i16, V1, V2,
10478 SDValue PSHUFBMask[32];
10479 for (int i = 0; i < 16; ++i) {
10480 if (Mask[i] == -1) {
10481 PSHUFBMask[2 * i] = PSHUFBMask[2 * i + 1] = DAG.getUNDEF(MVT::i8);
10485 int M = i < 8 ? Mask[i] : Mask[i] - 8;
10486 assert(M >= 0 && M < 8 && "Invalid single-input mask!");
10487 PSHUFBMask[2 * i] = DAG.getConstant(2 * M, MVT::i8);
10488 PSHUFBMask[2 * i + 1] = DAG.getConstant(2 * M + 1, MVT::i8);
10490 return DAG.getNode(
10491 ISD::BITCAST, DL, MVT::v16i16,
10493 X86ISD::PSHUFB, DL, MVT::v32i8,
10494 DAG.getNode(ISD::BITCAST, DL, MVT::v32i8, V1),
10495 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v32i8, PSHUFBMask)));
10498 // Try to simplify this by merging 128-bit lanes to enable a lane-based
10500 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
10501 DL, MVT::v16i16, V1, V2, Mask, Subtarget, DAG))
10504 // Otherwise fall back on generic lowering.
10505 return lowerVectorShuffleAsSplitOrBlend(DL, MVT::v16i16, V1, V2, Mask, DAG);
10508 /// \brief Handle lowering of 32-lane 8-bit integer shuffles.
10510 /// This routine is only called when we have AVX2 and thus a reasonable
10511 /// instruction set for v32i8 shuffling..
10512 static SDValue lowerV32I8VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10513 const X86Subtarget *Subtarget,
10514 SelectionDAG &DAG) {
10516 assert(V1.getSimpleValueType() == MVT::v32i8 && "Bad operand type!");
10517 assert(V2.getSimpleValueType() == MVT::v32i8 && "Bad operand type!");
10518 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10519 ArrayRef<int> Mask = SVOp->getMask();
10520 assert(Mask.size() == 32 && "Unexpected mask size for v32 shuffle!");
10521 assert(Subtarget->hasAVX2() && "We can only lower v32i8 with AVX2!");
10523 // Check for being able to broadcast a single element.
10524 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v32i8, DL, V1,
10525 Mask, Subtarget, DAG))
10528 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v32i8, V1, V2, Mask,
10532 // Use dedicated unpack instructions for masks that match their pattern.
10533 // Note that these are repeated 128-bit lane unpacks, not unpacks across all
10535 if (isShuffleEquivalent(
10537 // First 128-bit lane:
10538 0, 32, 1, 33, 2, 34, 3, 35, 4, 36, 5, 37, 6, 38, 7, 39,
10539 // Second 128-bit lane:
10540 16, 48, 17, 49, 18, 50, 19, 51, 20, 52, 21, 53, 22, 54, 23, 55))
10541 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v32i8, V1, V2);
10542 if (isShuffleEquivalent(
10544 // First 128-bit lane:
10545 8, 40, 9, 41, 10, 42, 11, 43, 12, 44, 13, 45, 14, 46, 15, 47,
10546 // Second 128-bit lane:
10547 24, 56, 25, 57, 26, 58, 27, 59, 28, 60, 29, 61, 30, 62, 31, 63))
10548 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v32i8, V1, V2);
10550 if (isSingleInputShuffleMask(Mask)) {
10551 // There are no generalized cross-lane shuffle operations available on i8
10553 if (is128BitLaneCrossingShuffleMask(MVT::v32i8, Mask))
10554 return lowerVectorShuffleAsLanePermuteAndBlend(DL, MVT::v32i8, V1, V2,
10557 SDValue PSHUFBMask[32];
10558 for (int i = 0; i < 32; ++i)
10561 ? DAG.getUNDEF(MVT::i8)
10562 : DAG.getConstant(Mask[i] < 16 ? Mask[i] : Mask[i] - 16, MVT::i8);
10564 return DAG.getNode(
10565 X86ISD::PSHUFB, DL, MVT::v32i8, V1,
10566 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v32i8, PSHUFBMask));
10569 // Try to simplify this by merging 128-bit lanes to enable a lane-based
10571 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
10572 DL, MVT::v32i8, V1, V2, Mask, Subtarget, DAG))
10575 // Otherwise fall back on generic lowering.
10576 return lowerVectorShuffleAsSplitOrBlend(DL, MVT::v32i8, V1, V2, Mask, DAG);
10579 /// \brief High-level routine to lower various 256-bit x86 vector shuffles.
10581 /// This routine either breaks down the specific type of a 256-bit x86 vector
10582 /// shuffle or splits it into two 128-bit shuffles and fuses the results back
10583 /// together based on the available instructions.
10584 static SDValue lower256BitVectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10585 MVT VT, const X86Subtarget *Subtarget,
10586 SelectionDAG &DAG) {
10588 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10589 ArrayRef<int> Mask = SVOp->getMask();
10591 // There is a really nice hard cut-over between AVX1 and AVX2 that means we can
10592 // check for those subtargets here and avoid much of the subtarget querying in
10593 // the per-vector-type lowering routines. With AVX1 we have essentially *zero*
10594 // ability to manipulate a 256-bit vector with integer types. Since we'll use
10595 // floating point types there eventually, just immediately cast everything to
10596 // a float and operate entirely in that domain.
10597 if (VT.isInteger() && !Subtarget->hasAVX2()) {
10598 int ElementBits = VT.getScalarSizeInBits();
10599 if (ElementBits < 32)
10600 // No floating point type available, decompose into 128-bit vectors.
10601 return splitAndLowerVectorShuffle(DL, VT, V1, V2, Mask, DAG);
10603 MVT FpVT = MVT::getVectorVT(MVT::getFloatingPointVT(ElementBits),
10604 VT.getVectorNumElements());
10605 V1 = DAG.getNode(ISD::BITCAST, DL, FpVT, V1);
10606 V2 = DAG.getNode(ISD::BITCAST, DL, FpVT, V2);
10607 return DAG.getNode(ISD::BITCAST, DL, VT,
10608 DAG.getVectorShuffle(FpVT, DL, V1, V2, Mask));
10611 switch (VT.SimpleTy) {
10613 return lowerV4F64VectorShuffle(Op, V1, V2, Subtarget, DAG);
10615 return lowerV4I64VectorShuffle(Op, V1, V2, Subtarget, DAG);
10617 return lowerV8F32VectorShuffle(Op, V1, V2, Subtarget, DAG);
10619 return lowerV8I32VectorShuffle(Op, V1, V2, Subtarget, DAG);
10621 return lowerV16I16VectorShuffle(Op, V1, V2, Subtarget, DAG);
10623 return lowerV32I8VectorShuffle(Op, V1, V2, Subtarget, DAG);
10626 llvm_unreachable("Not a valid 256-bit x86 vector type!");
10630 /// \brief Handle lowering of 8-lane 64-bit floating point shuffles.
10631 static SDValue lowerV8F64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10632 const X86Subtarget *Subtarget,
10633 SelectionDAG &DAG) {
10635 assert(V1.getSimpleValueType() == MVT::v8f64 && "Bad operand type!");
10636 assert(V2.getSimpleValueType() == MVT::v8f64 && "Bad operand type!");
10637 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10638 ArrayRef<int> Mask = SVOp->getMask();
10639 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
10641 // FIXME: Implement direct support for this type!
10642 return splitAndLowerVectorShuffle(DL, MVT::v8f64, V1, V2, Mask, DAG);
10645 /// \brief Handle lowering of 16-lane 32-bit floating point shuffles.
10646 static SDValue lowerV16F32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10647 const X86Subtarget *Subtarget,
10648 SelectionDAG &DAG) {
10650 assert(V1.getSimpleValueType() == MVT::v16f32 && "Bad operand type!");
10651 assert(V2.getSimpleValueType() == MVT::v16f32 && "Bad operand type!");
10652 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10653 ArrayRef<int> Mask = SVOp->getMask();
10654 assert(Mask.size() == 16 && "Unexpected mask size for v16 shuffle!");
10656 // FIXME: Implement direct support for this type!
10657 return splitAndLowerVectorShuffle(DL, MVT::v16f32, V1, V2, Mask, DAG);
10660 /// \brief Handle lowering of 8-lane 64-bit integer shuffles.
10661 static SDValue lowerV8I64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10662 const X86Subtarget *Subtarget,
10663 SelectionDAG &DAG) {
10665 assert(V1.getSimpleValueType() == MVT::v8i64 && "Bad operand type!");
10666 assert(V2.getSimpleValueType() == MVT::v8i64 && "Bad operand type!");
10667 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10668 ArrayRef<int> Mask = SVOp->getMask();
10669 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
10671 // FIXME: Implement direct support for this type!
10672 return splitAndLowerVectorShuffle(DL, MVT::v8i64, V1, V2, Mask, DAG);
10675 /// \brief Handle lowering of 16-lane 32-bit integer shuffles.
10676 static SDValue lowerV16I32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10677 const X86Subtarget *Subtarget,
10678 SelectionDAG &DAG) {
10680 assert(V1.getSimpleValueType() == MVT::v16i32 && "Bad operand type!");
10681 assert(V2.getSimpleValueType() == MVT::v16i32 && "Bad operand type!");
10682 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10683 ArrayRef<int> Mask = SVOp->getMask();
10684 assert(Mask.size() == 16 && "Unexpected mask size for v16 shuffle!");
10686 // FIXME: Implement direct support for this type!
10687 return splitAndLowerVectorShuffle(DL, MVT::v16i32, V1, V2, Mask, DAG);
10690 /// \brief Handle lowering of 32-lane 16-bit integer shuffles.
10691 static SDValue lowerV32I16VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10692 const X86Subtarget *Subtarget,
10693 SelectionDAG &DAG) {
10695 assert(V1.getSimpleValueType() == MVT::v32i16 && "Bad operand type!");
10696 assert(V2.getSimpleValueType() == MVT::v32i16 && "Bad operand type!");
10697 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10698 ArrayRef<int> Mask = SVOp->getMask();
10699 assert(Mask.size() == 32 && "Unexpected mask size for v32 shuffle!");
10700 assert(Subtarget->hasBWI() && "We can only lower v32i16 with AVX-512-BWI!");
10702 // FIXME: Implement direct support for this type!
10703 return splitAndLowerVectorShuffle(DL, MVT::v32i16, V1, V2, Mask, DAG);
10706 /// \brief Handle lowering of 64-lane 8-bit integer shuffles.
10707 static SDValue lowerV64I8VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10708 const X86Subtarget *Subtarget,
10709 SelectionDAG &DAG) {
10711 assert(V1.getSimpleValueType() == MVT::v64i8 && "Bad operand type!");
10712 assert(V2.getSimpleValueType() == MVT::v64i8 && "Bad operand type!");
10713 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10714 ArrayRef<int> Mask = SVOp->getMask();
10715 assert(Mask.size() == 64 && "Unexpected mask size for v64 shuffle!");
10716 assert(Subtarget->hasBWI() && "We can only lower v64i8 with AVX-512-BWI!");
10718 // FIXME: Implement direct support for this type!
10719 return splitAndLowerVectorShuffle(DL, MVT::v64i8, V1, V2, Mask, DAG);
10722 /// \brief High-level routine to lower various 512-bit x86 vector shuffles.
10724 /// This routine either breaks down the specific type of a 512-bit x86 vector
10725 /// shuffle or splits it into two 256-bit shuffles and fuses the results back
10726 /// together based on the available instructions.
10727 static SDValue lower512BitVectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10728 MVT VT, const X86Subtarget *Subtarget,
10729 SelectionDAG &DAG) {
10731 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10732 ArrayRef<int> Mask = SVOp->getMask();
10733 assert(Subtarget->hasAVX512() &&
10734 "Cannot lower 512-bit vectors w/ basic ISA!");
10736 // Check for being able to broadcast a single element.
10737 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(VT.SimpleTy, DL, V1,
10738 Mask, Subtarget, DAG))
10741 // Dispatch to each element type for lowering. If we don't have supprot for
10742 // specific element type shuffles at 512 bits, immediately split them and
10743 // lower them. Each lowering routine of a given type is allowed to assume that
10744 // the requisite ISA extensions for that element type are available.
10745 switch (VT.SimpleTy) {
10747 return lowerV8F64VectorShuffle(Op, V1, V2, Subtarget, DAG);
10749 return lowerV16F32VectorShuffle(Op, V1, V2, Subtarget, DAG);
10751 return lowerV8I64VectorShuffle(Op, V1, V2, Subtarget, DAG);
10753 return lowerV16I32VectorShuffle(Op, V1, V2, Subtarget, DAG);
10755 if (Subtarget->hasBWI())
10756 return lowerV32I16VectorShuffle(Op, V1, V2, Subtarget, DAG);
10759 if (Subtarget->hasBWI())
10760 return lowerV64I8VectorShuffle(Op, V1, V2, Subtarget, DAG);
10764 llvm_unreachable("Not a valid 512-bit x86 vector type!");
10767 // Otherwise fall back on splitting.
10768 return splitAndLowerVectorShuffle(DL, VT, V1, V2, Mask, DAG);
10771 /// \brief Top-level lowering for x86 vector shuffles.
10773 /// This handles decomposition, canonicalization, and lowering of all x86
10774 /// vector shuffles. Most of the specific lowering strategies are encapsulated
10775 /// above in helper routines. The canonicalization attempts to widen shuffles
10776 /// to involve fewer lanes of wider elements, consolidate symmetric patterns
10777 /// s.t. only one of the two inputs needs to be tested, etc.
10778 static SDValue lowerVectorShuffle(SDValue Op, const X86Subtarget *Subtarget,
10779 SelectionDAG &DAG) {
10780 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10781 ArrayRef<int> Mask = SVOp->getMask();
10782 SDValue V1 = Op.getOperand(0);
10783 SDValue V2 = Op.getOperand(1);
10784 MVT VT = Op.getSimpleValueType();
10785 int NumElements = VT.getVectorNumElements();
10788 assert(VT.getSizeInBits() != 64 && "Can't lower MMX shuffles");
10790 bool V1IsUndef = V1.getOpcode() == ISD::UNDEF;
10791 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
10792 if (V1IsUndef && V2IsUndef)
10793 return DAG.getUNDEF(VT);
10795 // When we create a shuffle node we put the UNDEF node to second operand,
10796 // but in some cases the first operand may be transformed to UNDEF.
10797 // In this case we should just commute the node.
10799 return DAG.getCommutedVectorShuffle(*SVOp);
10801 // Check for non-undef masks pointing at an undef vector and make the masks
10802 // undef as well. This makes it easier to match the shuffle based solely on
10806 if (M >= NumElements) {
10807 SmallVector<int, 8> NewMask(Mask.begin(), Mask.end());
10808 for (int &M : NewMask)
10809 if (M >= NumElements)
10811 return DAG.getVectorShuffle(VT, dl, V1, V2, NewMask);
10814 // Try to collapse shuffles into using a vector type with fewer elements but
10815 // wider element types. We cap this to not form integers or floating point
10816 // elements wider than 64 bits, but it might be interesting to form i128
10817 // integers to handle flipping the low and high halves of AVX 256-bit vectors.
10818 SmallVector<int, 16> WidenedMask;
10819 if (VT.getScalarSizeInBits() < 64 &&
10820 canWidenShuffleElements(Mask, WidenedMask)) {
10821 MVT NewEltVT = VT.isFloatingPoint()
10822 ? MVT::getFloatingPointVT(VT.getScalarSizeInBits() * 2)
10823 : MVT::getIntegerVT(VT.getScalarSizeInBits() * 2);
10824 MVT NewVT = MVT::getVectorVT(NewEltVT, VT.getVectorNumElements() / 2);
10825 // Make sure that the new vector type is legal. For example, v2f64 isn't
10827 if (DAG.getTargetLoweringInfo().isTypeLegal(NewVT)) {
10828 V1 = DAG.getNode(ISD::BITCAST, dl, NewVT, V1);
10829 V2 = DAG.getNode(ISD::BITCAST, dl, NewVT, V2);
10830 return DAG.getNode(ISD::BITCAST, dl, VT,
10831 DAG.getVectorShuffle(NewVT, dl, V1, V2, WidenedMask));
10835 int NumV1Elements = 0, NumUndefElements = 0, NumV2Elements = 0;
10836 for (int M : SVOp->getMask())
10838 ++NumUndefElements;
10839 else if (M < NumElements)
10844 // Commute the shuffle as needed such that more elements come from V1 than
10845 // V2. This allows us to match the shuffle pattern strictly on how many
10846 // elements come from V1 without handling the symmetric cases.
10847 if (NumV2Elements > NumV1Elements)
10848 return DAG.getCommutedVectorShuffle(*SVOp);
10850 // When the number of V1 and V2 elements are the same, try to minimize the
10851 // number of uses of V2 in the low half of the vector. When that is tied,
10852 // ensure that the sum of indices for V1 is equal to or lower than the sum
10853 // indices for V2. When those are equal, try to ensure that the number of odd
10854 // indices for V1 is lower than the number of odd indices for V2.
10855 if (NumV1Elements == NumV2Elements) {
10856 int LowV1Elements = 0, LowV2Elements = 0;
10857 for (int M : SVOp->getMask().slice(0, NumElements / 2))
10858 if (M >= NumElements)
10862 if (LowV2Elements > LowV1Elements) {
10863 return DAG.getCommutedVectorShuffle(*SVOp);
10864 } else if (LowV2Elements == LowV1Elements) {
10865 int SumV1Indices = 0, SumV2Indices = 0;
10866 for (int i = 0, Size = SVOp->getMask().size(); i < Size; ++i)
10867 if (SVOp->getMask()[i] >= NumElements)
10869 else if (SVOp->getMask()[i] >= 0)
10871 if (SumV2Indices < SumV1Indices) {
10872 return DAG.getCommutedVectorShuffle(*SVOp);
10873 } else if (SumV2Indices == SumV1Indices) {
10874 int NumV1OddIndices = 0, NumV2OddIndices = 0;
10875 for (int i = 0, Size = SVOp->getMask().size(); i < Size; ++i)
10876 if (SVOp->getMask()[i] >= NumElements)
10877 NumV2OddIndices += i % 2;
10878 else if (SVOp->getMask()[i] >= 0)
10879 NumV1OddIndices += i % 2;
10880 if (NumV2OddIndices < NumV1OddIndices)
10881 return DAG.getCommutedVectorShuffle(*SVOp);
10886 // For each vector width, delegate to a specialized lowering routine.
10887 if (VT.getSizeInBits() == 128)
10888 return lower128BitVectorShuffle(Op, V1, V2, VT, Subtarget, DAG);
10890 if (VT.getSizeInBits() == 256)
10891 return lower256BitVectorShuffle(Op, V1, V2, VT, Subtarget, DAG);
10893 // Force AVX-512 vectors to be scalarized for now.
10894 // FIXME: Implement AVX-512 support!
10895 if (VT.getSizeInBits() == 512)
10896 return lower512BitVectorShuffle(Op, V1, V2, VT, Subtarget, DAG);
10898 llvm_unreachable("Unimplemented!");
10902 //===----------------------------------------------------------------------===//
10903 // Legacy vector shuffle lowering
10905 // This code is the legacy code handling vector shuffles until the above
10906 // replaces its functionality and performance.
10907 //===----------------------------------------------------------------------===//
10909 static bool isBlendMask(ArrayRef<int> MaskVals, MVT VT, bool hasSSE41,
10910 bool hasInt256, unsigned *MaskOut = nullptr) {
10911 MVT EltVT = VT.getVectorElementType();
10913 // There is no blend with immediate in AVX-512.
10914 if (VT.is512BitVector())
10917 if (!hasSSE41 || EltVT == MVT::i8)
10919 if (!hasInt256 && VT == MVT::v16i16)
10922 unsigned MaskValue = 0;
10923 unsigned NumElems = VT.getVectorNumElements();
10924 // There are 2 lanes if (NumElems > 8), and 1 lane otherwise.
10925 unsigned NumLanes = (NumElems - 1) / 8 + 1;
10926 unsigned NumElemsInLane = NumElems / NumLanes;
10928 // Blend for v16i16 should be symetric for the both lanes.
10929 for (unsigned i = 0; i < NumElemsInLane; ++i) {
10931 int SndLaneEltIdx = (NumLanes == 2) ? MaskVals[i + NumElemsInLane] : -1;
10932 int EltIdx = MaskVals[i];
10934 if ((EltIdx < 0 || EltIdx == (int)i) &&
10935 (SndLaneEltIdx < 0 || SndLaneEltIdx == (int)(i + NumElemsInLane)))
10938 if (((unsigned)EltIdx == (i + NumElems)) &&
10939 (SndLaneEltIdx < 0 ||
10940 (unsigned)SndLaneEltIdx == i + NumElems + NumElemsInLane))
10941 MaskValue |= (1 << i);
10947 *MaskOut = MaskValue;
10951 // Try to lower a shuffle node into a simple blend instruction.
10952 // This function assumes isBlendMask returns true for this
10953 // SuffleVectorSDNode
10954 static SDValue LowerVECTOR_SHUFFLEtoBlend(ShuffleVectorSDNode *SVOp,
10955 unsigned MaskValue,
10956 const X86Subtarget *Subtarget,
10957 SelectionDAG &DAG) {
10958 MVT VT = SVOp->getSimpleValueType(0);
10959 MVT EltVT = VT.getVectorElementType();
10960 assert(isBlendMask(SVOp->getMask(), VT, Subtarget->hasSSE41(),
10961 Subtarget->hasInt256() && "Trying to lower a "
10962 "VECTOR_SHUFFLE to a Blend but "
10963 "with the wrong mask"));
10964 SDValue V1 = SVOp->getOperand(0);
10965 SDValue V2 = SVOp->getOperand(1);
10967 unsigned NumElems = VT.getVectorNumElements();
10969 // Convert i32 vectors to floating point if it is not AVX2.
10970 // AVX2 introduced VPBLENDD instruction for 128 and 256-bit vectors.
10972 if (EltVT == MVT::i64 || (EltVT == MVT::i32 && !Subtarget->hasInt256())) {
10973 BlendVT = MVT::getVectorVT(MVT::getFloatingPointVT(EltVT.getSizeInBits()),
10975 V1 = DAG.getNode(ISD::BITCAST, dl, VT, V1);
10976 V2 = DAG.getNode(ISD::BITCAST, dl, VT, V2);
10979 SDValue Ret = DAG.getNode(X86ISD::BLENDI, dl, BlendVT, V1, V2,
10980 DAG.getConstant(MaskValue, MVT::i32));
10981 return DAG.getNode(ISD::BITCAST, dl, VT, Ret);
10984 /// In vector type \p VT, return true if the element at index \p InputIdx
10985 /// falls on a different 128-bit lane than \p OutputIdx.
10986 static bool ShuffleCrosses128bitLane(MVT VT, unsigned InputIdx,
10987 unsigned OutputIdx) {
10988 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
10989 return InputIdx * EltSize / 128 != OutputIdx * EltSize / 128;
10992 /// Generate a PSHUFB if possible. Selects elements from \p V1 according to
10993 /// \p MaskVals. MaskVals[OutputIdx] = InputIdx specifies that we want to
10994 /// shuffle the element at InputIdx in V1 to OutputIdx in the result. If \p
10995 /// MaskVals refers to elements outside of \p V1 or is undef (-1), insert a
10997 static SDValue getPSHUFB(ArrayRef<int> MaskVals, SDValue V1, SDLoc &dl,
10998 SelectionDAG &DAG) {
10999 MVT VT = V1.getSimpleValueType();
11000 assert(VT.is128BitVector() || VT.is256BitVector());
11002 MVT EltVT = VT.getVectorElementType();
11003 unsigned EltSizeInBytes = EltVT.getSizeInBits() / 8;
11004 unsigned NumElts = VT.getVectorNumElements();
11006 SmallVector<SDValue, 32> PshufbMask;
11007 for (unsigned OutputIdx = 0; OutputIdx < NumElts; ++OutputIdx) {
11008 int InputIdx = MaskVals[OutputIdx];
11009 unsigned InputByteIdx;
11011 if (InputIdx < 0 || NumElts <= (unsigned)InputIdx)
11012 InputByteIdx = 0x80;
11014 // Cross lane is not allowed.
11015 if (ShuffleCrosses128bitLane(VT, InputIdx, OutputIdx))
11017 InputByteIdx = InputIdx * EltSizeInBytes;
11018 // Index is an byte offset within the 128-bit lane.
11019 InputByteIdx &= 0xf;
11022 for (unsigned j = 0; j < EltSizeInBytes; ++j) {
11023 PshufbMask.push_back(DAG.getConstant(InputByteIdx, MVT::i8));
11024 if (InputByteIdx != 0x80)
11029 MVT ShufVT = MVT::getVectorVT(MVT::i8, PshufbMask.size());
11031 V1 = DAG.getNode(ISD::BITCAST, dl, ShufVT, V1);
11032 return DAG.getNode(X86ISD::PSHUFB, dl, ShufVT, V1,
11033 DAG.getNode(ISD::BUILD_VECTOR, dl, ShufVT, PshufbMask));
11036 // v8i16 shuffles - Prefer shuffles in the following order:
11037 // 1. [all] pshuflw, pshufhw, optional move
11038 // 2. [ssse3] 1 x pshufb
11039 // 3. [ssse3] 2 x pshufb + 1 x por
11040 // 4. [all] mov + pshuflw + pshufhw + N x (pextrw + pinsrw)
11042 LowerVECTOR_SHUFFLEv8i16(SDValue Op, const X86Subtarget *Subtarget,
11043 SelectionDAG &DAG) {
11044 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
11045 SDValue V1 = SVOp->getOperand(0);
11046 SDValue V2 = SVOp->getOperand(1);
11048 SmallVector<int, 8> MaskVals;
11050 // Determine if more than 1 of the words in each of the low and high quadwords
11051 // of the result come from the same quadword of one of the two inputs. Undef
11052 // mask values count as coming from any quadword, for better codegen.
11054 // Lo/HiQuad[i] = j indicates how many words from the ith quad of the input
11055 // feeds this quad. For i, 0 and 1 refer to V1, 2 and 3 refer to V2.
11056 unsigned LoQuad[] = { 0, 0, 0, 0 };
11057 unsigned HiQuad[] = { 0, 0, 0, 0 };
11058 // Indices of quads used.
11059 std::bitset<4> InputQuads;
11060 for (unsigned i = 0; i < 8; ++i) {
11061 unsigned *Quad = i < 4 ? LoQuad : HiQuad;
11062 int EltIdx = SVOp->getMaskElt(i);
11063 MaskVals.push_back(EltIdx);
11071 ++Quad[EltIdx / 4];
11072 InputQuads.set(EltIdx / 4);
11075 int BestLoQuad = -1;
11076 unsigned MaxQuad = 1;
11077 for (unsigned i = 0; i < 4; ++i) {
11078 if (LoQuad[i] > MaxQuad) {
11080 MaxQuad = LoQuad[i];
11084 int BestHiQuad = -1;
11086 for (unsigned i = 0; i < 4; ++i) {
11087 if (HiQuad[i] > MaxQuad) {
11089 MaxQuad = HiQuad[i];
11093 // For SSSE3, If all 8 words of the result come from only 1 quadword of each
11094 // of the two input vectors, shuffle them into one input vector so only a
11095 // single pshufb instruction is necessary. If there are more than 2 input
11096 // quads, disable the next transformation since it does not help SSSE3.
11097 bool V1Used = InputQuads[0] || InputQuads[1];
11098 bool V2Used = InputQuads[2] || InputQuads[3];
11099 if (Subtarget->hasSSSE3()) {
11100 if (InputQuads.count() == 2 && V1Used && V2Used) {
11101 BestLoQuad = InputQuads[0] ? 0 : 1;
11102 BestHiQuad = InputQuads[2] ? 2 : 3;
11104 if (InputQuads.count() > 2) {
11110 // If BestLoQuad or BestHiQuad are set, shuffle the quads together and update
11111 // the shuffle mask. If a quad is scored as -1, that means that it contains
11112 // words from all 4 input quadwords.
11114 if (BestLoQuad >= 0 || BestHiQuad >= 0) {
11116 BestLoQuad < 0 ? 0 : BestLoQuad,
11117 BestHiQuad < 0 ? 1 : BestHiQuad
11119 NewV = DAG.getVectorShuffle(MVT::v2i64, dl,
11120 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, V1),
11121 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, V2), &MaskV[0]);
11122 NewV = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, NewV);
11124 // Rewrite the MaskVals and assign NewV to V1 if NewV now contains all the
11125 // source words for the shuffle, to aid later transformations.
11126 bool AllWordsInNewV = true;
11127 bool InOrder[2] = { true, true };
11128 for (unsigned i = 0; i != 8; ++i) {
11129 int idx = MaskVals[i];
11131 InOrder[i/4] = false;
11132 if (idx < 0 || (idx/4) == BestLoQuad || (idx/4) == BestHiQuad)
11134 AllWordsInNewV = false;
11138 bool pshuflw = AllWordsInNewV, pshufhw = AllWordsInNewV;
11139 if (AllWordsInNewV) {
11140 for (int i = 0; i != 8; ++i) {
11141 int idx = MaskVals[i];
11144 idx = MaskVals[i] = (idx / 4) == BestLoQuad ? (idx & 3) : (idx & 3) + 4;
11145 if ((idx != i) && idx < 4)
11147 if ((idx != i) && idx > 3)
11156 // If we've eliminated the use of V2, and the new mask is a pshuflw or
11157 // pshufhw, that's as cheap as it gets. Return the new shuffle.
11158 if ((pshufhw && InOrder[0]) || (pshuflw && InOrder[1])) {
11159 unsigned Opc = pshufhw ? X86ISD::PSHUFHW : X86ISD::PSHUFLW;
11160 unsigned TargetMask = 0;
11161 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV,
11162 DAG.getUNDEF(MVT::v8i16), &MaskVals[0]);
11163 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode());
11164 TargetMask = pshufhw ? getShufflePSHUFHWImmediate(SVOp):
11165 getShufflePSHUFLWImmediate(SVOp);
11166 V1 = NewV.getOperand(0);
11167 return getTargetShuffleNode(Opc, dl, MVT::v8i16, V1, TargetMask, DAG);
11171 // Promote splats to a larger type which usually leads to more efficient code.
11172 // FIXME: Is this true if pshufb is available?
11173 if (SVOp->isSplat())
11174 return PromoteSplat(SVOp, DAG);
11176 // If we have SSSE3, and all words of the result are from 1 input vector,
11177 // case 2 is generated, otherwise case 3 is generated. If no SSSE3
11178 // is present, fall back to case 4.
11179 if (Subtarget->hasSSSE3()) {
11180 SmallVector<SDValue,16> pshufbMask;
11182 // If we have elements from both input vectors, set the high bit of the
11183 // shuffle mask element to zero out elements that come from V2 in the V1
11184 // mask, and elements that come from V1 in the V2 mask, so that the two
11185 // results can be OR'd together.
11186 bool TwoInputs = V1Used && V2Used;
11187 V1 = getPSHUFB(MaskVals, V1, dl, DAG);
11189 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
11191 // Calculate the shuffle mask for the second input, shuffle it, and
11192 // OR it with the first shuffled input.
11193 CommuteVectorShuffleMask(MaskVals, 8);
11194 V2 = getPSHUFB(MaskVals, V2, dl, DAG);
11195 V1 = DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
11196 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
11199 // If BestLoQuad >= 0, generate a pshuflw to put the low elements in order,
11200 // and update MaskVals with new element order.
11201 std::bitset<8> InOrder;
11202 if (BestLoQuad >= 0) {
11203 int MaskV[] = { -1, -1, -1, -1, 4, 5, 6, 7 };
11204 for (int i = 0; i != 4; ++i) {
11205 int idx = MaskVals[i];
11208 } else if ((idx / 4) == BestLoQuad) {
11209 MaskV[i] = idx & 3;
11213 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16),
11216 if (NewV.getOpcode() == ISD::VECTOR_SHUFFLE && Subtarget->hasSSE2()) {
11217 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode());
11218 NewV = getTargetShuffleNode(X86ISD::PSHUFLW, dl, MVT::v8i16,
11219 NewV.getOperand(0),
11220 getShufflePSHUFLWImmediate(SVOp), DAG);
11224 // If BestHi >= 0, generate a pshufhw to put the high elements in order,
11225 // and update MaskVals with the new element order.
11226 if (BestHiQuad >= 0) {
11227 int MaskV[] = { 0, 1, 2, 3, -1, -1, -1, -1 };
11228 for (unsigned i = 4; i != 8; ++i) {
11229 int idx = MaskVals[i];
11232 } else if ((idx / 4) == BestHiQuad) {
11233 MaskV[i] = (idx & 3) + 4;
11237 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16),
11240 if (NewV.getOpcode() == ISD::VECTOR_SHUFFLE && Subtarget->hasSSE2()) {
11241 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode());
11242 NewV = getTargetShuffleNode(X86ISD::PSHUFHW, dl, MVT::v8i16,
11243 NewV.getOperand(0),
11244 getShufflePSHUFHWImmediate(SVOp), DAG);
11248 // In case BestHi & BestLo were both -1, which means each quadword has a word
11249 // from each of the four input quadwords, calculate the InOrder bitvector now
11250 // before falling through to the insert/extract cleanup.
11251 if (BestLoQuad == -1 && BestHiQuad == -1) {
11253 for (int i = 0; i != 8; ++i)
11254 if (MaskVals[i] < 0 || MaskVals[i] == i)
11258 // The other elements are put in the right place using pextrw and pinsrw.
11259 for (unsigned i = 0; i != 8; ++i) {
11262 int EltIdx = MaskVals[i];
11265 SDValue ExtOp = (EltIdx < 8) ?
11266 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V1,
11267 DAG.getIntPtrConstant(EltIdx)) :
11268 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V2,
11269 DAG.getIntPtrConstant(EltIdx - 8));
11270 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, ExtOp,
11271 DAG.getIntPtrConstant(i));
11276 /// \brief v16i16 shuffles
11278 /// FIXME: We only support generation of a single pshufb currently. We can
11279 /// generalize the other applicable cases from LowerVECTOR_SHUFFLEv8i16 as
11280 /// well (e.g 2 x pshufb + 1 x por).
11282 LowerVECTOR_SHUFFLEv16i16(SDValue Op, SelectionDAG &DAG) {
11283 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
11284 SDValue V1 = SVOp->getOperand(0);
11285 SDValue V2 = SVOp->getOperand(1);
11288 if (V2.getOpcode() != ISD::UNDEF)
11291 SmallVector<int, 16> MaskVals(SVOp->getMask().begin(), SVOp->getMask().end());
11292 return getPSHUFB(MaskVals, V1, dl, DAG);
11295 // v16i8 shuffles - Prefer shuffles in the following order:
11296 // 1. [ssse3] 1 x pshufb
11297 // 2. [ssse3] 2 x pshufb + 1 x por
11298 // 3. [all] v8i16 shuffle + N x pextrw + rotate + pinsrw
11299 static SDValue LowerVECTOR_SHUFFLEv16i8(ShuffleVectorSDNode *SVOp,
11300 const X86Subtarget* Subtarget,
11301 SelectionDAG &DAG) {
11302 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
11303 SDValue V1 = SVOp->getOperand(0);
11304 SDValue V2 = SVOp->getOperand(1);
11306 ArrayRef<int> MaskVals = SVOp->getMask();
11308 // Promote splats to a larger type which usually leads to more efficient code.
11309 // FIXME: Is this true if pshufb is available?
11310 if (SVOp->isSplat())
11311 return PromoteSplat(SVOp, DAG);
11313 // If we have SSSE3, case 1 is generated when all result bytes come from
11314 // one of the inputs. Otherwise, case 2 is generated. If no SSSE3 is
11315 // present, fall back to case 3.
11317 // If SSSE3, use 1 pshufb instruction per vector with elements in the result.
11318 if (Subtarget->hasSSSE3()) {
11319 SmallVector<SDValue,16> pshufbMask;
11321 // If all result elements are from one input vector, then only translate
11322 // undef mask values to 0x80 (zero out result) in the pshufb mask.
11324 // Otherwise, we have elements from both input vectors, and must zero out
11325 // elements that come from V2 in the first mask, and V1 in the second mask
11326 // so that we can OR them together.
11327 for (unsigned i = 0; i != 16; ++i) {
11328 int EltIdx = MaskVals[i];
11329 if (EltIdx < 0 || EltIdx >= 16)
11331 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
11333 V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1,
11334 DAG.getNode(ISD::BUILD_VECTOR, dl,
11335 MVT::v16i8, pshufbMask));
11337 // As PSHUFB will zero elements with negative indices, it's safe to ignore
11338 // the 2nd operand if it's undefined or zero.
11339 if (V2.getOpcode() == ISD::UNDEF ||
11340 ISD::isBuildVectorAllZeros(V2.getNode()))
11343 // Calculate the shuffle mask for the second input, shuffle it, and
11344 // OR it with the first shuffled input.
11345 pshufbMask.clear();
11346 for (unsigned i = 0; i != 16; ++i) {
11347 int EltIdx = MaskVals[i];
11348 EltIdx = (EltIdx < 16) ? 0x80 : EltIdx - 16;
11349 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
11351 V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2,
11352 DAG.getNode(ISD::BUILD_VECTOR, dl,
11353 MVT::v16i8, pshufbMask));
11354 return DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
11357 // No SSSE3 - Calculate in place words and then fix all out of place words
11358 // With 0-16 extracts & inserts. Worst case is 16 bytes out of order from
11359 // the 16 different words that comprise the two doublequadword input vectors.
11360 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
11361 V2 = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V2);
11363 for (int i = 0; i != 8; ++i) {
11364 int Elt0 = MaskVals[i*2];
11365 int Elt1 = MaskVals[i*2+1];
11367 // This word of the result is all undef, skip it.
11368 if (Elt0 < 0 && Elt1 < 0)
11371 // This word of the result is already in the correct place, skip it.
11372 if ((Elt0 == i*2) && (Elt1 == i*2+1))
11375 SDValue Elt0Src = Elt0 < 16 ? V1 : V2;
11376 SDValue Elt1Src = Elt1 < 16 ? V1 : V2;
11379 // If Elt0 and Elt1 are defined, are consecutive, and can be load
11380 // using a single extract together, load it and store it.
11381 if ((Elt0 >= 0) && ((Elt0 + 1) == Elt1) && ((Elt0 & 1) == 0)) {
11382 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src,
11383 DAG.getIntPtrConstant(Elt1 / 2));
11384 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt,
11385 DAG.getIntPtrConstant(i));
11389 // If Elt1 is defined, extract it from the appropriate source. If the
11390 // source byte is not also odd, shift the extracted word left 8 bits
11391 // otherwise clear the bottom 8 bits if we need to do an or.
11393 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src,
11394 DAG.getIntPtrConstant(Elt1 / 2));
11395 if ((Elt1 & 1) == 0)
11396 InsElt = DAG.getNode(ISD::SHL, dl, MVT::i16, InsElt,
11398 TLI.getShiftAmountTy(InsElt.getValueType())));
11399 else if (Elt0 >= 0)
11400 InsElt = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt,
11401 DAG.getConstant(0xFF00, MVT::i16));
11403 // If Elt0 is defined, extract it from the appropriate source. If the
11404 // source byte is not also even, shift the extracted word right 8 bits. If
11405 // Elt1 was also defined, OR the extracted values together before
11406 // inserting them in the result.
11408 SDValue InsElt0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16,
11409 Elt0Src, DAG.getIntPtrConstant(Elt0 / 2));
11410 if ((Elt0 & 1) != 0)
11411 InsElt0 = DAG.getNode(ISD::SRL, dl, MVT::i16, InsElt0,
11413 TLI.getShiftAmountTy(InsElt0.getValueType())));
11414 else if (Elt1 >= 0)
11415 InsElt0 = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt0,
11416 DAG.getConstant(0x00FF, MVT::i16));
11417 InsElt = Elt1 >= 0 ? DAG.getNode(ISD::OR, dl, MVT::i16, InsElt, InsElt0)
11420 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt,
11421 DAG.getIntPtrConstant(i));
11423 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, NewV);
11426 // v32i8 shuffles - Translate to VPSHUFB if possible.
11428 SDValue LowerVECTOR_SHUFFLEv32i8(ShuffleVectorSDNode *SVOp,
11429 const X86Subtarget *Subtarget,
11430 SelectionDAG &DAG) {
11431 MVT VT = SVOp->getSimpleValueType(0);
11432 SDValue V1 = SVOp->getOperand(0);
11433 SDValue V2 = SVOp->getOperand(1);
11435 SmallVector<int, 32> MaskVals(SVOp->getMask().begin(), SVOp->getMask().end());
11437 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
11438 bool V1IsAllZero = ISD::isBuildVectorAllZeros(V1.getNode());
11439 bool V2IsAllZero = ISD::isBuildVectorAllZeros(V2.getNode());
11441 // VPSHUFB may be generated if
11442 // (1) one of input vector is undefined or zeroinitializer.
11443 // The mask value 0x80 puts 0 in the corresponding slot of the vector.
11444 // And (2) the mask indexes don't cross the 128-bit lane.
11445 if (VT != MVT::v32i8 || !Subtarget->hasInt256() ||
11446 (!V2IsUndef && !V2IsAllZero && !V1IsAllZero))
11449 if (V1IsAllZero && !V2IsAllZero) {
11450 CommuteVectorShuffleMask(MaskVals, 32);
11453 return getPSHUFB(MaskVals, V1, dl, DAG);
11456 /// RewriteAsNarrowerShuffle - Try rewriting v8i16 and v16i8 shuffles as 4 wide
11457 /// ones, or rewriting v4i32 / v4f32 as 2 wide ones if possible. This can be
11458 /// done when every pair / quad of shuffle mask elements point to elements in
11459 /// the right sequence. e.g.
11460 /// vector_shuffle X, Y, <2, 3, | 10, 11, | 0, 1, | 14, 15>
11462 SDValue RewriteAsNarrowerShuffle(ShuffleVectorSDNode *SVOp,
11463 SelectionDAG &DAG) {
11464 MVT VT = SVOp->getSimpleValueType(0);
11466 unsigned NumElems = VT.getVectorNumElements();
11469 switch (VT.SimpleTy) {
11470 default: llvm_unreachable("Unexpected!");
11473 return SDValue(SVOp, 0);
11474 case MVT::v4f32: NewVT = MVT::v2f64; Scale = 2; break;
11475 case MVT::v4i32: NewVT = MVT::v2i64; Scale = 2; break;
11476 case MVT::v8i16: NewVT = MVT::v4i32; Scale = 2; break;
11477 case MVT::v16i8: NewVT = MVT::v4i32; Scale = 4; break;
11478 case MVT::v16i16: NewVT = MVT::v8i32; Scale = 2; break;
11479 case MVT::v32i8: NewVT = MVT::v8i32; Scale = 4; break;
11482 SmallVector<int, 8> MaskVec;
11483 for (unsigned i = 0; i != NumElems; i += Scale) {
11485 for (unsigned j = 0; j != Scale; ++j) {
11486 int EltIdx = SVOp->getMaskElt(i+j);
11490 StartIdx = (EltIdx / Scale);
11491 if (EltIdx != (int)(StartIdx*Scale + j))
11494 MaskVec.push_back(StartIdx);
11497 SDValue V1 = DAG.getNode(ISD::BITCAST, dl, NewVT, SVOp->getOperand(0));
11498 SDValue V2 = DAG.getNode(ISD::BITCAST, dl, NewVT, SVOp->getOperand(1));
11499 return DAG.getVectorShuffle(NewVT, dl, V1, V2, &MaskVec[0]);
11502 /// getVZextMovL - Return a zero-extending vector move low node.
11504 static SDValue getVZextMovL(MVT VT, MVT OpVT,
11505 SDValue SrcOp, SelectionDAG &DAG,
11506 const X86Subtarget *Subtarget, SDLoc dl) {
11507 if (VT == MVT::v2f64 || VT == MVT::v4f32) {
11508 LoadSDNode *LD = nullptr;
11509 if (!isScalarLoadToVector(SrcOp.getNode(), &LD))
11510 LD = dyn_cast<LoadSDNode>(SrcOp);
11512 // movssrr and movsdrr do not clear top bits. Try to use movd, movq
11514 MVT ExtVT = (OpVT == MVT::v2f64) ? MVT::i64 : MVT::i32;
11515 if ((ExtVT != MVT::i64 || Subtarget->is64Bit()) &&
11516 SrcOp.getOpcode() == ISD::SCALAR_TO_VECTOR &&
11517 SrcOp.getOperand(0).getOpcode() == ISD::BITCAST &&
11518 SrcOp.getOperand(0).getOperand(0).getValueType() == ExtVT) {
11520 OpVT = (OpVT == MVT::v2f64) ? MVT::v2i64 : MVT::v4i32;
11521 return DAG.getNode(ISD::BITCAST, dl, VT,
11522 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT,
11523 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
11525 SrcOp.getOperand(0)
11531 return DAG.getNode(ISD::BITCAST, dl, VT,
11532 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT,
11533 DAG.getNode(ISD::BITCAST, dl,
11537 /// LowerVECTOR_SHUFFLE_256 - Handle all 256-bit wide vectors shuffles
11538 /// which could not be matched by any known target speficic shuffle
11540 LowerVECTOR_SHUFFLE_256(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
11542 SDValue NewOp = Compact8x32ShuffleNode(SVOp, DAG);
11543 if (NewOp.getNode())
11546 MVT VT = SVOp->getSimpleValueType(0);
11548 unsigned NumElems = VT.getVectorNumElements();
11549 unsigned NumLaneElems = NumElems / 2;
11552 MVT EltVT = VT.getVectorElementType();
11553 MVT NVT = MVT::getVectorVT(EltVT, NumLaneElems);
11556 SmallVector<int, 16> Mask;
11557 for (unsigned l = 0; l < 2; ++l) {
11558 // Build a shuffle mask for the output, discovering on the fly which
11559 // input vectors to use as shuffle operands (recorded in InputUsed).
11560 // If building a suitable shuffle vector proves too hard, then bail
11561 // out with UseBuildVector set.
11562 bool UseBuildVector = false;
11563 int InputUsed[2] = { -1, -1 }; // Not yet discovered.
11564 unsigned LaneStart = l * NumLaneElems;
11565 for (unsigned i = 0; i != NumLaneElems; ++i) {
11566 // The mask element. This indexes into the input.
11567 int Idx = SVOp->getMaskElt(i+LaneStart);
11569 // the mask element does not index into any input vector.
11570 Mask.push_back(-1);
11574 // The input vector this mask element indexes into.
11575 int Input = Idx / NumLaneElems;
11577 // Turn the index into an offset from the start of the input vector.
11578 Idx -= Input * NumLaneElems;
11580 // Find or create a shuffle vector operand to hold this input.
11582 for (OpNo = 0; OpNo < array_lengthof(InputUsed); ++OpNo) {
11583 if (InputUsed[OpNo] == Input)
11584 // This input vector is already an operand.
11586 if (InputUsed[OpNo] < 0) {
11587 // Create a new operand for this input vector.
11588 InputUsed[OpNo] = Input;
11593 if (OpNo >= array_lengthof(InputUsed)) {
11594 // More than two input vectors used! Give up on trying to create a
11595 // shuffle vector. Insert all elements into a BUILD_VECTOR instead.
11596 UseBuildVector = true;
11600 // Add the mask index for the new shuffle vector.
11601 Mask.push_back(Idx + OpNo * NumLaneElems);
11604 if (UseBuildVector) {
11605 SmallVector<SDValue, 16> SVOps;
11606 for (unsigned i = 0; i != NumLaneElems; ++i) {
11607 // The mask element. This indexes into the input.
11608 int Idx = SVOp->getMaskElt(i+LaneStart);
11610 SVOps.push_back(DAG.getUNDEF(EltVT));
11614 // The input vector this mask element indexes into.
11615 int Input = Idx / NumElems;
11617 // Turn the index into an offset from the start of the input vector.
11618 Idx -= Input * NumElems;
11620 // Extract the vector element by hand.
11621 SVOps.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT,
11622 SVOp->getOperand(Input),
11623 DAG.getIntPtrConstant(Idx)));
11626 // Construct the output using a BUILD_VECTOR.
11627 Output[l] = DAG.getNode(ISD::BUILD_VECTOR, dl, NVT, SVOps);
11628 } else if (InputUsed[0] < 0) {
11629 // No input vectors were used! The result is undefined.
11630 Output[l] = DAG.getUNDEF(NVT);
11632 SDValue Op0 = Extract128BitVector(SVOp->getOperand(InputUsed[0] / 2),
11633 (InputUsed[0] % 2) * NumLaneElems,
11635 // If only one input was used, use an undefined vector for the other.
11636 SDValue Op1 = (InputUsed[1] < 0) ? DAG.getUNDEF(NVT) :
11637 Extract128BitVector(SVOp->getOperand(InputUsed[1] / 2),
11638 (InputUsed[1] % 2) * NumLaneElems, DAG, dl);
11639 // At least one input vector was used. Create a new shuffle vector.
11640 Output[l] = DAG.getVectorShuffle(NVT, dl, Op0, Op1, &Mask[0]);
11646 // Concatenate the result back
11647 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, Output[0], Output[1]);
11650 /// LowerVECTOR_SHUFFLE_128v4 - Handle all 128-bit wide vectors with
11651 /// 4 elements, and match them with several different shuffle types.
11653 LowerVECTOR_SHUFFLE_128v4(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
11654 SDValue V1 = SVOp->getOperand(0);
11655 SDValue V2 = SVOp->getOperand(1);
11657 MVT VT = SVOp->getSimpleValueType(0);
11659 assert(VT.is128BitVector() && "Unsupported vector size");
11661 std::pair<int, int> Locs[4];
11662 int Mask1[] = { -1, -1, -1, -1 };
11663 SmallVector<int, 8> PermMask(SVOp->getMask().begin(), SVOp->getMask().end());
11665 unsigned NumHi = 0;
11666 unsigned NumLo = 0;
11667 for (unsigned i = 0; i != 4; ++i) {
11668 int Idx = PermMask[i];
11670 Locs[i] = std::make_pair(-1, -1);
11672 assert(Idx < 8 && "Invalid VECTOR_SHUFFLE index!");
11674 Locs[i] = std::make_pair(0, NumLo);
11675 Mask1[NumLo] = Idx;
11678 Locs[i] = std::make_pair(1, NumHi);
11680 Mask1[2+NumHi] = Idx;
11686 if (NumLo <= 2 && NumHi <= 2) {
11687 // If no more than two elements come from either vector. This can be
11688 // implemented with two shuffles. First shuffle gather the elements.
11689 // The second shuffle, which takes the first shuffle as both of its
11690 // vector operands, put the elements into the right order.
11691 V1 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
11693 int Mask2[] = { -1, -1, -1, -1 };
11695 for (unsigned i = 0; i != 4; ++i)
11696 if (Locs[i].first != -1) {
11697 unsigned Idx = (i < 2) ? 0 : 4;
11698 Idx += Locs[i].first * 2 + Locs[i].second;
11702 return DAG.getVectorShuffle(VT, dl, V1, V1, &Mask2[0]);
11705 if (NumLo == 3 || NumHi == 3) {
11706 // Otherwise, we must have three elements from one vector, call it X, and
11707 // one element from the other, call it Y. First, use a shufps to build an
11708 // intermediate vector with the one element from Y and the element from X
11709 // that will be in the same half in the final destination (the indexes don't
11710 // matter). Then, use a shufps to build the final vector, taking the half
11711 // containing the element from Y from the intermediate, and the other half
11714 // Normalize it so the 3 elements come from V1.
11715 CommuteVectorShuffleMask(PermMask, 4);
11719 // Find the element from V2.
11721 for (HiIndex = 0; HiIndex < 3; ++HiIndex) {
11722 int Val = PermMask[HiIndex];
11729 Mask1[0] = PermMask[HiIndex];
11731 Mask1[2] = PermMask[HiIndex^1];
11733 V2 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
11735 if (HiIndex >= 2) {
11736 Mask1[0] = PermMask[0];
11737 Mask1[1] = PermMask[1];
11738 Mask1[2] = HiIndex & 1 ? 6 : 4;
11739 Mask1[3] = HiIndex & 1 ? 4 : 6;
11740 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
11743 Mask1[0] = HiIndex & 1 ? 2 : 0;
11744 Mask1[1] = HiIndex & 1 ? 0 : 2;
11745 Mask1[2] = PermMask[2];
11746 Mask1[3] = PermMask[3];
11751 return DAG.getVectorShuffle(VT, dl, V2, V1, &Mask1[0]);
11754 // Break it into (shuffle shuffle_hi, shuffle_lo).
11755 int LoMask[] = { -1, -1, -1, -1 };
11756 int HiMask[] = { -1, -1, -1, -1 };
11758 int *MaskPtr = LoMask;
11759 unsigned MaskIdx = 0;
11760 unsigned LoIdx = 0;
11761 unsigned HiIdx = 2;
11762 for (unsigned i = 0; i != 4; ++i) {
11769 int Idx = PermMask[i];
11771 Locs[i] = std::make_pair(-1, -1);
11772 } else if (Idx < 4) {
11773 Locs[i] = std::make_pair(MaskIdx, LoIdx);
11774 MaskPtr[LoIdx] = Idx;
11777 Locs[i] = std::make_pair(MaskIdx, HiIdx);
11778 MaskPtr[HiIdx] = Idx;
11783 SDValue LoShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &LoMask[0]);
11784 SDValue HiShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &HiMask[0]);
11785 int MaskOps[] = { -1, -1, -1, -1 };
11786 for (unsigned i = 0; i != 4; ++i)
11787 if (Locs[i].first != -1)
11788 MaskOps[i] = Locs[i].first * 4 + Locs[i].second;
11789 return DAG.getVectorShuffle(VT, dl, LoShuffle, HiShuffle, &MaskOps[0]);
11792 static bool MayFoldVectorLoad(SDValue V) {
11793 while (V.hasOneUse() && V.getOpcode() == ISD::BITCAST)
11794 V = V.getOperand(0);
11796 if (V.hasOneUse() && V.getOpcode() == ISD::SCALAR_TO_VECTOR)
11797 V = V.getOperand(0);
11798 if (V.hasOneUse() && V.getOpcode() == ISD::BUILD_VECTOR &&
11799 V.getNumOperands() == 2 && V.getOperand(1).getOpcode() == ISD::UNDEF)
11800 // BUILD_VECTOR (load), undef
11801 V = V.getOperand(0);
11803 return MayFoldLoad(V);
11807 SDValue getMOVDDup(SDValue &Op, SDLoc &dl, SDValue V1, SelectionDAG &DAG) {
11808 MVT VT = Op.getSimpleValueType();
11810 // Canonizalize to v2f64.
11811 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, V1);
11812 return DAG.getNode(ISD::BITCAST, dl, VT,
11813 getTargetShuffleNode(X86ISD::MOVDDUP, dl, MVT::v2f64,
11818 SDValue getMOVLowToHigh(SDValue &Op, SDLoc &dl, SelectionDAG &DAG,
11820 SDValue V1 = Op.getOperand(0);
11821 SDValue V2 = Op.getOperand(1);
11822 MVT VT = Op.getSimpleValueType();
11824 assert(VT != MVT::v2i64 && "unsupported shuffle type");
11826 if (HasSSE2 && VT == MVT::v2f64)
11827 return getTargetShuffleNode(X86ISD::MOVLHPD, dl, VT, V1, V2, DAG);
11829 // v4f32 or v4i32: canonizalized to v4f32 (which is legal for SSE1)
11830 return DAG.getNode(ISD::BITCAST, dl, VT,
11831 getTargetShuffleNode(X86ISD::MOVLHPS, dl, MVT::v4f32,
11832 DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V1),
11833 DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V2), DAG));
11837 SDValue getMOVHighToLow(SDValue &Op, SDLoc &dl, SelectionDAG &DAG) {
11838 SDValue V1 = Op.getOperand(0);
11839 SDValue V2 = Op.getOperand(1);
11840 MVT VT = Op.getSimpleValueType();
11842 assert((VT == MVT::v4i32 || VT == MVT::v4f32) &&
11843 "unsupported shuffle type");
11845 if (V2.getOpcode() == ISD::UNDEF)
11849 return getTargetShuffleNode(X86ISD::MOVHLPS, dl, VT, V1, V2, DAG);
11853 SDValue getMOVLP(SDValue &Op, SDLoc &dl, SelectionDAG &DAG, bool HasSSE2) {
11854 SDValue V1 = Op.getOperand(0);
11855 SDValue V2 = Op.getOperand(1);
11856 MVT VT = Op.getSimpleValueType();
11857 unsigned NumElems = VT.getVectorNumElements();
11859 // Use MOVLPS and MOVLPD in case V1 or V2 are loads. During isel, the second
11860 // operand of these instructions is only memory, so check if there's a
11861 // potencial load folding here, otherwise use SHUFPS or MOVSD to match the
11863 bool CanFoldLoad = false;
11865 // Trivial case, when V2 comes from a load.
11866 if (MayFoldVectorLoad(V2))
11867 CanFoldLoad = true;
11869 // When V1 is a load, it can be folded later into a store in isel, example:
11870 // (store (v4f32 (X86Movlps (load addr:$src1), VR128:$src2)), addr:$src1)
11872 // (MOVLPSmr addr:$src1, VR128:$src2)
11873 // So, recognize this potential and also use MOVLPS or MOVLPD
11874 else if (MayFoldVectorLoad(V1) && MayFoldIntoStore(Op))
11875 CanFoldLoad = true;
11877 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
11879 if (HasSSE2 && NumElems == 2)
11880 return getTargetShuffleNode(X86ISD::MOVLPD, dl, VT, V1, V2, DAG);
11883 // If we don't care about the second element, proceed to use movss.
11884 if (SVOp->getMaskElt(1) != -1)
11885 return getTargetShuffleNode(X86ISD::MOVLPS, dl, VT, V1, V2, DAG);
11888 // movl and movlp will both match v2i64, but v2i64 is never matched by
11889 // movl earlier because we make it strict to avoid messing with the movlp load
11890 // folding logic (see the code above getMOVLP call). Match it here then,
11891 // this is horrible, but will stay like this until we move all shuffle
11892 // matching to x86 specific nodes. Note that for the 1st condition all
11893 // types are matched with movsd.
11895 // FIXME: isMOVLMask should be checked and matched before getMOVLP,
11896 // as to remove this logic from here, as much as possible
11897 if (NumElems == 2 || !isMOVLMask(SVOp->getMask(), VT))
11898 return getTargetShuffleNode(X86ISD::MOVSD, dl, VT, V1, V2, DAG);
11899 return getTargetShuffleNode(X86ISD::MOVSS, dl, VT, V1, V2, DAG);
11902 assert(VT != MVT::v4i32 && "unsupported shuffle type");
11904 // Invert the operand order and use SHUFPS to match it.
11905 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V2, V1,
11906 getShuffleSHUFImmediate(SVOp), DAG);
11909 static SDValue NarrowVectorLoadToElement(LoadSDNode *Load, unsigned Index,
11910 SelectionDAG &DAG) {
11912 MVT VT = Load->getSimpleValueType(0);
11913 MVT EVT = VT.getVectorElementType();
11914 SDValue Addr = Load->getOperand(1);
11915 SDValue NewAddr = DAG.getNode(
11916 ISD::ADD, dl, Addr.getSimpleValueType(), Addr,
11917 DAG.getConstant(Index * EVT.getStoreSize(), Addr.getSimpleValueType()));
11920 DAG.getLoad(EVT, dl, Load->getChain(), NewAddr,
11921 DAG.getMachineFunction().getMachineMemOperand(
11922 Load->getMemOperand(), 0, EVT.getStoreSize()));
11926 // It is only safe to call this function if isINSERTPSMask is true for
11927 // this shufflevector mask.
11928 static SDValue getINSERTPS(ShuffleVectorSDNode *SVOp, SDLoc &dl,
11929 SelectionDAG &DAG) {
11930 // Generate an insertps instruction when inserting an f32 from memory onto a
11931 // v4f32 or when copying a member from one v4f32 to another.
11932 // We also use it for transferring i32 from one register to another,
11933 // since it simply copies the same bits.
11934 // If we're transferring an i32 from memory to a specific element in a
11935 // register, we output a generic DAG that will match the PINSRD
11937 MVT VT = SVOp->getSimpleValueType(0);
11938 MVT EVT = VT.getVectorElementType();
11939 SDValue V1 = SVOp->getOperand(0);
11940 SDValue V2 = SVOp->getOperand(1);
11941 auto Mask = SVOp->getMask();
11942 assert((VT == MVT::v4f32 || VT == MVT::v4i32) &&
11943 "unsupported vector type for insertps/pinsrd");
11945 auto FromV1Predicate = [](const int &i) { return i < 4 && i > -1; };
11946 auto FromV2Predicate = [](const int &i) { return i >= 4; };
11947 int FromV1 = std::count_if(Mask.begin(), Mask.end(), FromV1Predicate);
11951 unsigned DestIndex;
11955 DestIndex = std::find_if(Mask.begin(), Mask.end(), FromV1Predicate) -
11958 // If we have 1 element from each vector, we have to check if we're
11959 // changing V1's element's place. If so, we're done. Otherwise, we
11960 // should assume we're changing V2's element's place and behave
11962 int FromV2 = std::count_if(Mask.begin(), Mask.end(), FromV2Predicate);
11963 assert(DestIndex <= INT32_MAX && "truncated destination index");
11964 if (FromV1 == FromV2 &&
11965 static_cast<int>(DestIndex) == Mask[DestIndex] % 4) {
11969 std::find_if(Mask.begin(), Mask.end(), FromV2Predicate) - Mask.begin();
11972 assert(std::count_if(Mask.begin(), Mask.end(), FromV2Predicate) == 1 &&
11973 "More than one element from V1 and from V2, or no elements from one "
11974 "of the vectors. This case should not have returned true from "
11979 std::find_if(Mask.begin(), Mask.end(), FromV2Predicate) - Mask.begin();
11982 // Get an index into the source vector in the range [0,4) (the mask is
11983 // in the range [0,8) because it can address V1 and V2)
11984 unsigned SrcIndex = Mask[DestIndex] % 4;
11985 if (MayFoldLoad(From)) {
11986 // Trivial case, when From comes from a load and is only used by the
11987 // shuffle. Make it use insertps from the vector that we need from that
11990 NarrowVectorLoadToElement(cast<LoadSDNode>(From), SrcIndex, DAG);
11991 if (!NewLoad.getNode())
11994 if (EVT == MVT::f32) {
11995 // Create this as a scalar to vector to match the instruction pattern.
11996 SDValue LoadScalarToVector =
11997 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, NewLoad);
11998 SDValue InsertpsMask = DAG.getIntPtrConstant(DestIndex << 4);
11999 return DAG.getNode(X86ISD::INSERTPS, dl, VT, To, LoadScalarToVector,
12001 } else { // EVT == MVT::i32
12002 // If we're getting an i32 from memory, use an INSERT_VECTOR_ELT
12003 // instruction, to match the PINSRD instruction, which loads an i32 to a
12004 // certain vector element.
12005 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, To, NewLoad,
12006 DAG.getConstant(DestIndex, MVT::i32));
12010 // Vector-element-to-vector
12011 SDValue InsertpsMask = DAG.getIntPtrConstant(DestIndex << 4 | SrcIndex << 6);
12012 return DAG.getNode(X86ISD::INSERTPS, dl, VT, To, From, InsertpsMask);
12015 // Reduce a vector shuffle to zext.
12016 static SDValue LowerVectorIntExtend(SDValue Op, const X86Subtarget *Subtarget,
12017 SelectionDAG &DAG) {
12018 // PMOVZX is only available from SSE41.
12019 if (!Subtarget->hasSSE41())
12022 MVT VT = Op.getSimpleValueType();
12024 // Only AVX2 support 256-bit vector integer extending.
12025 if (!Subtarget->hasInt256() && VT.is256BitVector())
12028 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
12030 SDValue V1 = Op.getOperand(0);
12031 SDValue V2 = Op.getOperand(1);
12032 unsigned NumElems = VT.getVectorNumElements();
12034 // Extending is an unary operation and the element type of the source vector
12035 // won't be equal to or larger than i64.
12036 if (V2.getOpcode() != ISD::UNDEF || !VT.isInteger() ||
12037 VT.getVectorElementType() == MVT::i64)
12040 // Find the expansion ratio, e.g. expanding from i8 to i32 has a ratio of 4.
12041 unsigned Shift = 1; // Start from 2, i.e. 1 << 1.
12042 while ((1U << Shift) < NumElems) {
12043 if (SVOp->getMaskElt(1U << Shift) == 1)
12046 // The maximal ratio is 8, i.e. from i8 to i64.
12051 // Check the shuffle mask.
12052 unsigned Mask = (1U << Shift) - 1;
12053 for (unsigned i = 0; i != NumElems; ++i) {
12054 int EltIdx = SVOp->getMaskElt(i);
12055 if ((i & Mask) != 0 && EltIdx != -1)
12057 if ((i & Mask) == 0 && (unsigned)EltIdx != (i >> Shift))
12061 unsigned NBits = VT.getVectorElementType().getSizeInBits() << Shift;
12062 MVT NeVT = MVT::getIntegerVT(NBits);
12063 MVT NVT = MVT::getVectorVT(NeVT, NumElems >> Shift);
12065 if (!DAG.getTargetLoweringInfo().isTypeLegal(NVT))
12068 return DAG.getNode(ISD::BITCAST, DL, VT,
12069 DAG.getNode(X86ISD::VZEXT, DL, NVT, V1));
12072 static SDValue NormalizeVectorShuffle(SDValue Op, const X86Subtarget *Subtarget,
12073 SelectionDAG &DAG) {
12074 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
12075 MVT VT = Op.getSimpleValueType();
12077 SDValue V1 = Op.getOperand(0);
12078 SDValue V2 = Op.getOperand(1);
12080 if (isZeroShuffle(SVOp))
12081 return getZeroVector(VT, Subtarget, DAG, dl);
12083 // Handle splat operations
12084 if (SVOp->isSplat()) {
12085 // Use vbroadcast whenever the splat comes from a foldable load
12086 SDValue Broadcast = LowerVectorBroadcast(Op, Subtarget, DAG);
12087 if (Broadcast.getNode())
12091 // Check integer expanding shuffles.
12092 SDValue NewOp = LowerVectorIntExtend(Op, Subtarget, DAG);
12093 if (NewOp.getNode())
12096 // If the shuffle can be profitably rewritten as a narrower shuffle, then
12098 if (VT == MVT::v8i16 || VT == MVT::v16i8 || VT == MVT::v16i16 ||
12099 VT == MVT::v32i8) {
12100 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG);
12101 if (NewOp.getNode())
12102 return DAG.getNode(ISD::BITCAST, dl, VT, NewOp);
12103 } else if (VT.is128BitVector() && Subtarget->hasSSE2()) {
12104 // FIXME: Figure out a cleaner way to do this.
12105 if (ISD::isBuildVectorAllZeros(V2.getNode())) {
12106 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG);
12107 if (NewOp.getNode()) {
12108 MVT NewVT = NewOp.getSimpleValueType();
12109 if (isCommutedMOVLMask(cast<ShuffleVectorSDNode>(NewOp)->getMask(),
12110 NewVT, true, false))
12111 return getVZextMovL(VT, NewVT, NewOp.getOperand(0), DAG, Subtarget,
12114 } else if (ISD::isBuildVectorAllZeros(V1.getNode())) {
12115 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG);
12116 if (NewOp.getNode()) {
12117 MVT NewVT = NewOp.getSimpleValueType();
12118 if (isMOVLMask(cast<ShuffleVectorSDNode>(NewOp)->getMask(), NewVT))
12119 return getVZextMovL(VT, NewVT, NewOp.getOperand(1), DAG, Subtarget,
12128 X86TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const {
12129 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
12130 SDValue V1 = Op.getOperand(0);
12131 SDValue V2 = Op.getOperand(1);
12132 MVT VT = Op.getSimpleValueType();
12134 unsigned NumElems = VT.getVectorNumElements();
12135 bool V1IsUndef = V1.getOpcode() == ISD::UNDEF;
12136 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
12137 bool V1IsSplat = false;
12138 bool V2IsSplat = false;
12139 bool HasSSE2 = Subtarget->hasSSE2();
12140 bool HasFp256 = Subtarget->hasFp256();
12141 bool HasInt256 = Subtarget->hasInt256();
12142 MachineFunction &MF = DAG.getMachineFunction();
12143 bool OptForSize = MF.getFunction()->getAttributes().
12144 hasAttribute(AttributeSet::FunctionIndex, Attribute::OptimizeForSize);
12146 // Check if we should use the experimental vector shuffle lowering. If so,
12147 // delegate completely to that code path.
12148 if (ExperimentalVectorShuffleLowering)
12149 return lowerVectorShuffle(Op, Subtarget, DAG);
12151 assert(VT.getSizeInBits() != 64 && "Can't lower MMX shuffles");
12153 if (V1IsUndef && V2IsUndef)
12154 return DAG.getUNDEF(VT);
12156 // When we create a shuffle node we put the UNDEF node to second operand,
12157 // but in some cases the first operand may be transformed to UNDEF.
12158 // In this case we should just commute the node.
12160 return DAG.getCommutedVectorShuffle(*SVOp);
12162 // Vector shuffle lowering takes 3 steps:
12164 // 1) Normalize the input vectors. Here splats, zeroed vectors, profitable
12165 // narrowing and commutation of operands should be handled.
12166 // 2) Matching of shuffles with known shuffle masks to x86 target specific
12168 // 3) Rewriting of unmatched masks into new generic shuffle operations,
12169 // so the shuffle can be broken into other shuffles and the legalizer can
12170 // try the lowering again.
12172 // The general idea is that no vector_shuffle operation should be left to
12173 // be matched during isel, all of them must be converted to a target specific
12176 // Normalize the input vectors. Here splats, zeroed vectors, profitable
12177 // narrowing and commutation of operands should be handled. The actual code
12178 // doesn't include all of those, work in progress...
12179 SDValue NewOp = NormalizeVectorShuffle(Op, Subtarget, DAG);
12180 if (NewOp.getNode())
12183 SmallVector<int, 8> M(SVOp->getMask().begin(), SVOp->getMask().end());
12185 // NOTE: isPSHUFDMask can also match both masks below (unpckl_undef and
12186 // unpckh_undef). Only use pshufd if speed is more important than size.
12187 if (OptForSize && isUNPCKL_v_undef_Mask(M, VT, HasInt256))
12188 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
12189 if (OptForSize && isUNPCKH_v_undef_Mask(M, VT, HasInt256))
12190 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
12192 if (isMOVDDUPMask(M, VT) && Subtarget->hasSSE3() &&
12193 V2IsUndef && MayFoldVectorLoad(V1))
12194 return getMOVDDup(Op, dl, V1, DAG);
12196 if (isMOVHLPS_v_undef_Mask(M, VT))
12197 return getMOVHighToLow(Op, dl, DAG);
12199 // Use to match splats
12200 if (HasSSE2 && isUNPCKHMask(M, VT, HasInt256) && V2IsUndef &&
12201 (VT == MVT::v2f64 || VT == MVT::v2i64))
12202 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
12204 if (isPSHUFDMask(M, VT)) {
12205 // The actual implementation will match the mask in the if above and then
12206 // during isel it can match several different instructions, not only pshufd
12207 // as its name says, sad but true, emulate the behavior for now...
12208 if (isMOVDDUPMask(M, VT) && ((VT == MVT::v4f32 || VT == MVT::v2i64)))
12209 return getTargetShuffleNode(X86ISD::MOVLHPS, dl, VT, V1, V1, DAG);
12211 unsigned TargetMask = getShuffleSHUFImmediate(SVOp);
12213 if (HasSSE2 && (VT == MVT::v4f32 || VT == MVT::v4i32))
12214 return getTargetShuffleNode(X86ISD::PSHUFD, dl, VT, V1, TargetMask, DAG);
12216 if (HasFp256 && (VT == MVT::v4f32 || VT == MVT::v2f64))
12217 return getTargetShuffleNode(X86ISD::VPERMILPI, dl, VT, V1, TargetMask,
12220 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V1, V1,
12224 if (isPALIGNRMask(M, VT, Subtarget))
12225 return getTargetShuffleNode(X86ISD::PALIGNR, dl, VT, V1, V2,
12226 getShufflePALIGNRImmediate(SVOp),
12229 if (isVALIGNMask(M, VT, Subtarget))
12230 return getTargetShuffleNode(X86ISD::VALIGN, dl, VT, V1, V2,
12231 getShuffleVALIGNImmediate(SVOp),
12234 // Check if this can be converted into a logical shift.
12235 bool isLeft = false;
12236 unsigned ShAmt = 0;
12238 bool isShift = HasSSE2 && isVectorShift(SVOp, DAG, isLeft, ShVal, ShAmt);
12239 if (isShift && ShVal.hasOneUse()) {
12240 // If the shifted value has multiple uses, it may be cheaper to use
12241 // v_set0 + movlhps or movhlps, etc.
12242 MVT EltVT = VT.getVectorElementType();
12243 ShAmt *= EltVT.getSizeInBits();
12244 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl);
12247 if (isMOVLMask(M, VT)) {
12248 if (ISD::isBuildVectorAllZeros(V1.getNode()))
12249 return getVZextMovL(VT, VT, V2, DAG, Subtarget, dl);
12250 if (!isMOVLPMask(M, VT)) {
12251 if (HasSSE2 && (VT == MVT::v2i64 || VT == MVT::v2f64))
12252 return getTargetShuffleNode(X86ISD::MOVSD, dl, VT, V1, V2, DAG);
12254 if (VT == MVT::v4i32 || VT == MVT::v4f32)
12255 return getTargetShuffleNode(X86ISD::MOVSS, dl, VT, V1, V2, DAG);
12259 // FIXME: fold these into legal mask.
12260 if (isMOVLHPSMask(M, VT) && !isUNPCKLMask(M, VT, HasInt256))
12261 return getMOVLowToHigh(Op, dl, DAG, HasSSE2);
12263 if (isMOVHLPSMask(M, VT))
12264 return getMOVHighToLow(Op, dl, DAG);
12266 if (V2IsUndef && isMOVSHDUPMask(M, VT, Subtarget))
12267 return getTargetShuffleNode(X86ISD::MOVSHDUP, dl, VT, V1, DAG);
12269 if (V2IsUndef && isMOVSLDUPMask(M, VT, Subtarget))
12270 return getTargetShuffleNode(X86ISD::MOVSLDUP, dl, VT, V1, DAG);
12272 if (isMOVLPMask(M, VT))
12273 return getMOVLP(Op, dl, DAG, HasSSE2);
12275 if (ShouldXformToMOVHLPS(M, VT) ||
12276 ShouldXformToMOVLP(V1.getNode(), V2.getNode(), M, VT))
12277 return DAG.getCommutedVectorShuffle(*SVOp);
12280 // No better options. Use a vshldq / vsrldq.
12281 MVT EltVT = VT.getVectorElementType();
12282 ShAmt *= EltVT.getSizeInBits();
12283 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl);
12286 bool Commuted = false;
12287 // FIXME: This should also accept a bitcast of a splat? Be careful, not
12288 // 1,1,1,1 -> v8i16 though.
12289 BitVector UndefElements;
12290 if (auto *BVOp = dyn_cast<BuildVectorSDNode>(V1.getNode()))
12291 if (BVOp->getConstantSplatNode(&UndefElements) && UndefElements.none())
12293 if (auto *BVOp = dyn_cast<BuildVectorSDNode>(V2.getNode()))
12294 if (BVOp->getConstantSplatNode(&UndefElements) && UndefElements.none())
12297 // Canonicalize the splat or undef, if present, to be on the RHS.
12298 if (!V2IsUndef && V1IsSplat && !V2IsSplat) {
12299 CommuteVectorShuffleMask(M, NumElems);
12301 std::swap(V1IsSplat, V2IsSplat);
12305 if (isCommutedMOVLMask(M, VT, V2IsSplat, V2IsUndef)) {
12306 // Shuffling low element of v1 into undef, just return v1.
12309 // If V2 is a splat, the mask may be malformed such as <4,3,3,3>, which
12310 // the instruction selector will not match, so get a canonical MOVL with
12311 // swapped operands to undo the commute.
12312 return getMOVL(DAG, dl, VT, V2, V1);
12315 if (isUNPCKLMask(M, VT, HasInt256))
12316 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG);
12318 if (isUNPCKHMask(M, VT, HasInt256))
12319 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG);
12322 // Normalize mask so all entries that point to V2 points to its first
12323 // element then try to match unpck{h|l} again. If match, return a
12324 // new vector_shuffle with the corrected mask.p
12325 SmallVector<int, 8> NewMask(M.begin(), M.end());
12326 NormalizeMask(NewMask, NumElems);
12327 if (isUNPCKLMask(NewMask, VT, HasInt256, true))
12328 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG);
12329 if (isUNPCKHMask(NewMask, VT, HasInt256, true))
12330 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG);
12334 // Commute is back and try unpck* again.
12335 // FIXME: this seems wrong.
12336 CommuteVectorShuffleMask(M, NumElems);
12338 std::swap(V1IsSplat, V2IsSplat);
12340 if (isUNPCKLMask(M, VT, HasInt256))
12341 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG);
12343 if (isUNPCKHMask(M, VT, HasInt256))
12344 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG);
12347 // Normalize the node to match x86 shuffle ops if needed
12348 if (!V2IsUndef && (isSHUFPMask(M, VT, /* Commuted */ true)))
12349 return DAG.getCommutedVectorShuffle(*SVOp);
12351 // The checks below are all present in isShuffleMaskLegal, but they are
12352 // inlined here right now to enable us to directly emit target specific
12353 // nodes, and remove one by one until they don't return Op anymore.
12355 if (ShuffleVectorSDNode::isSplatMask(&M[0], VT) &&
12356 SVOp->getSplatIndex() == 0 && V2IsUndef) {
12357 if (VT == MVT::v2f64 || VT == MVT::v2i64)
12358 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
12361 if (isPSHUFHWMask(M, VT, HasInt256))
12362 return getTargetShuffleNode(X86ISD::PSHUFHW, dl, VT, V1,
12363 getShufflePSHUFHWImmediate(SVOp),
12366 if (isPSHUFLWMask(M, VT, HasInt256))
12367 return getTargetShuffleNode(X86ISD::PSHUFLW, dl, VT, V1,
12368 getShufflePSHUFLWImmediate(SVOp),
12371 unsigned MaskValue;
12372 if (isBlendMask(M, VT, Subtarget->hasSSE41(), Subtarget->hasInt256(),
12374 return LowerVECTOR_SHUFFLEtoBlend(SVOp, MaskValue, Subtarget, DAG);
12376 if (isSHUFPMask(M, VT))
12377 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V1, V2,
12378 getShuffleSHUFImmediate(SVOp), DAG);
12380 if (isUNPCKL_v_undef_Mask(M, VT, HasInt256))
12381 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
12382 if (isUNPCKH_v_undef_Mask(M, VT, HasInt256))
12383 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
12385 //===--------------------------------------------------------------------===//
12386 // Generate target specific nodes for 128 or 256-bit shuffles only
12387 // supported in the AVX instruction set.
12390 // Handle VMOVDDUPY permutations
12391 if (V2IsUndef && isMOVDDUPYMask(M, VT, HasFp256))
12392 return getTargetShuffleNode(X86ISD::MOVDDUP, dl, VT, V1, DAG);
12394 // Handle VPERMILPS/D* permutations
12395 if (isVPERMILPMask(M, VT)) {
12396 if ((HasInt256 && VT == MVT::v8i32) || VT == MVT::v16i32)
12397 return getTargetShuffleNode(X86ISD::PSHUFD, dl, VT, V1,
12398 getShuffleSHUFImmediate(SVOp), DAG);
12399 return getTargetShuffleNode(X86ISD::VPERMILPI, dl, VT, V1,
12400 getShuffleSHUFImmediate(SVOp), DAG);
12404 if (VT.is512BitVector() && isINSERT64x4Mask(M, VT, &Idx))
12405 return Insert256BitVector(V1, Extract256BitVector(V2, 0, DAG, dl),
12406 Idx*(NumElems/2), DAG, dl);
12408 // Handle VPERM2F128/VPERM2I128 permutations
12409 if (isVPERM2X128Mask(M, VT, HasFp256))
12410 return getTargetShuffleNode(X86ISD::VPERM2X128, dl, VT, V1,
12411 V2, getShuffleVPERM2X128Immediate(SVOp), DAG);
12413 if (Subtarget->hasSSE41() && isINSERTPSMask(M, VT))
12414 return getINSERTPS(SVOp, dl, DAG);
12417 if (V2IsUndef && HasInt256 && isPermImmMask(M, VT, Imm8))
12418 return getTargetShuffleNode(X86ISD::VPERMI, dl, VT, V1, Imm8, DAG);
12420 if ((V2IsUndef && HasInt256 && VT.is256BitVector() && NumElems == 8) ||
12421 VT.is512BitVector()) {
12422 MVT MaskEltVT = MVT::getIntegerVT(VT.getVectorElementType().getSizeInBits());
12423 MVT MaskVectorVT = MVT::getVectorVT(MaskEltVT, NumElems);
12424 SmallVector<SDValue, 16> permclMask;
12425 for (unsigned i = 0; i != NumElems; ++i) {
12426 permclMask.push_back(DAG.getConstant((M[i]>=0) ? M[i] : 0, MaskEltVT));
12429 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, MaskVectorVT, permclMask);
12431 // Bitcast is for VPERMPS since mask is v8i32 but node takes v8f32
12432 return DAG.getNode(X86ISD::VPERMV, dl, VT,
12433 DAG.getNode(ISD::BITCAST, dl, VT, Mask), V1);
12434 return DAG.getNode(X86ISD::VPERMV3, dl, VT, V1,
12435 DAG.getNode(ISD::BITCAST, dl, VT, Mask), V2);
12438 //===--------------------------------------------------------------------===//
12439 // Since no target specific shuffle was selected for this generic one,
12440 // lower it into other known shuffles. FIXME: this isn't true yet, but
12441 // this is the plan.
12444 // Handle v8i16 specifically since SSE can do byte extraction and insertion.
12445 if (VT == MVT::v8i16) {
12446 SDValue NewOp = LowerVECTOR_SHUFFLEv8i16(Op, Subtarget, DAG);
12447 if (NewOp.getNode())
12451 if (VT == MVT::v16i16 && Subtarget->hasInt256()) {
12452 SDValue NewOp = LowerVECTOR_SHUFFLEv16i16(Op, DAG);
12453 if (NewOp.getNode())
12457 if (VT == MVT::v16i8) {
12458 SDValue NewOp = LowerVECTOR_SHUFFLEv16i8(SVOp, Subtarget, DAG);
12459 if (NewOp.getNode())
12463 if (VT == MVT::v32i8) {
12464 SDValue NewOp = LowerVECTOR_SHUFFLEv32i8(SVOp, Subtarget, DAG);
12465 if (NewOp.getNode())
12469 // Handle all 128-bit wide vectors with 4 elements, and match them with
12470 // several different shuffle types.
12471 if (NumElems == 4 && VT.is128BitVector())
12472 return LowerVECTOR_SHUFFLE_128v4(SVOp, DAG);
12474 // Handle general 256-bit shuffles
12475 if (VT.is256BitVector())
12476 return LowerVECTOR_SHUFFLE_256(SVOp, DAG);
12481 // This function assumes its argument is a BUILD_VECTOR of constants or
12482 // undef SDNodes. i.e: ISD::isBuildVectorOfConstantSDNodes(BuildVector) is
12484 static bool BUILD_VECTORtoBlendMask(BuildVectorSDNode *BuildVector,
12485 unsigned &MaskValue) {
12487 unsigned NumElems = BuildVector->getNumOperands();
12488 // There are 2 lanes if (NumElems > 8), and 1 lane otherwise.
12489 unsigned NumLanes = (NumElems - 1) / 8 + 1;
12490 unsigned NumElemsInLane = NumElems / NumLanes;
12492 // Blend for v16i16 should be symetric for the both lanes.
12493 for (unsigned i = 0; i < NumElemsInLane; ++i) {
12494 SDValue EltCond = BuildVector->getOperand(i);
12495 SDValue SndLaneEltCond =
12496 (NumLanes == 2) ? BuildVector->getOperand(i + NumElemsInLane) : EltCond;
12498 int Lane1Cond = -1, Lane2Cond = -1;
12499 if (isa<ConstantSDNode>(EltCond))
12500 Lane1Cond = !isZero(EltCond);
12501 if (isa<ConstantSDNode>(SndLaneEltCond))
12502 Lane2Cond = !isZero(SndLaneEltCond);
12504 if (Lane1Cond == Lane2Cond || Lane2Cond < 0)
12505 // Lane1Cond != 0, means we want the first argument.
12506 // Lane1Cond == 0, means we want the second argument.
12507 // The encoding of this argument is 0 for the first argument, 1
12508 // for the second. Therefore, invert the condition.
12509 MaskValue |= !Lane1Cond << i;
12510 else if (Lane1Cond < 0)
12511 MaskValue |= !Lane2Cond << i;
12518 /// \brief Try to lower a VSELECT instruction to an immediate-controlled blend
12520 static SDValue lowerVSELECTtoBLENDI(SDValue Op, const X86Subtarget *Subtarget,
12521 SelectionDAG &DAG) {
12522 SDValue Cond = Op.getOperand(0);
12523 SDValue LHS = Op.getOperand(1);
12524 SDValue RHS = Op.getOperand(2);
12526 MVT VT = Op.getSimpleValueType();
12527 MVT EltVT = VT.getVectorElementType();
12528 unsigned NumElems = VT.getVectorNumElements();
12530 // There is no blend with immediate in AVX-512.
12531 if (VT.is512BitVector())
12534 if (!Subtarget->hasSSE41() || EltVT == MVT::i8)
12536 if (!Subtarget->hasInt256() && VT == MVT::v16i16)
12539 if (!ISD::isBuildVectorOfConstantSDNodes(Cond.getNode()))
12542 // Check the mask for BLEND and build the value.
12543 unsigned MaskValue = 0;
12544 if (!BUILD_VECTORtoBlendMask(cast<BuildVectorSDNode>(Cond), MaskValue))
12547 // Convert i32 vectors to floating point if it is not AVX2.
12548 // AVX2 introduced VPBLENDD instruction for 128 and 256-bit vectors.
12550 if (EltVT == MVT::i64 || (EltVT == MVT::i32 && !Subtarget->hasInt256())) {
12551 BlendVT = MVT::getVectorVT(MVT::getFloatingPointVT(EltVT.getSizeInBits()),
12553 LHS = DAG.getNode(ISD::BITCAST, dl, VT, LHS);
12554 RHS = DAG.getNode(ISD::BITCAST, dl, VT, RHS);
12557 SDValue Ret = DAG.getNode(X86ISD::BLENDI, dl, BlendVT, LHS, RHS,
12558 DAG.getConstant(MaskValue, MVT::i32));
12559 return DAG.getNode(ISD::BITCAST, dl, VT, Ret);
12562 SDValue X86TargetLowering::LowerVSELECT(SDValue Op, SelectionDAG &DAG) const {
12563 // A vselect where all conditions and data are constants can be optimized into
12564 // a single vector load by SelectionDAGLegalize::ExpandBUILD_VECTOR().
12565 if (ISD::isBuildVectorOfConstantSDNodes(Op.getOperand(0).getNode()) &&
12566 ISD::isBuildVectorOfConstantSDNodes(Op.getOperand(1).getNode()) &&
12567 ISD::isBuildVectorOfConstantSDNodes(Op.getOperand(2).getNode()))
12570 SDValue BlendOp = lowerVSELECTtoBLENDI(Op, Subtarget, DAG);
12571 if (BlendOp.getNode())
12574 // Some types for vselect were previously set to Expand, not Legal or
12575 // Custom. Return an empty SDValue so we fall-through to Expand, after
12576 // the Custom lowering phase.
12577 MVT VT = Op.getSimpleValueType();
12578 switch (VT.SimpleTy) {
12583 if (Subtarget->hasBWI() && Subtarget->hasVLX())
12588 // We couldn't create a "Blend with immediate" node.
12589 // This node should still be legal, but we'll have to emit a blendv*
12594 static SDValue LowerEXTRACT_VECTOR_ELT_SSE4(SDValue Op, SelectionDAG &DAG) {
12595 MVT VT = Op.getSimpleValueType();
12598 if (!Op.getOperand(0).getSimpleValueType().is128BitVector())
12601 if (VT.getSizeInBits() == 8) {
12602 SDValue Extract = DAG.getNode(X86ISD::PEXTRB, dl, MVT::i32,
12603 Op.getOperand(0), Op.getOperand(1));
12604 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
12605 DAG.getValueType(VT));
12606 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
12609 if (VT.getSizeInBits() == 16) {
12610 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
12611 // If Idx is 0, it's cheaper to do a move instead of a pextrw.
12613 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
12614 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
12615 DAG.getNode(ISD::BITCAST, dl,
12618 Op.getOperand(1)));
12619 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, MVT::i32,
12620 Op.getOperand(0), Op.getOperand(1));
12621 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
12622 DAG.getValueType(VT));
12623 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
12626 if (VT == MVT::f32) {
12627 // EXTRACTPS outputs to a GPR32 register which will require a movd to copy
12628 // the result back to FR32 register. It's only worth matching if the
12629 // result has a single use which is a store or a bitcast to i32. And in
12630 // the case of a store, it's not worth it if the index is a constant 0,
12631 // because a MOVSSmr can be used instead, which is smaller and faster.
12632 if (!Op.hasOneUse())
12634 SDNode *User = *Op.getNode()->use_begin();
12635 if ((User->getOpcode() != ISD::STORE ||
12636 (isa<ConstantSDNode>(Op.getOperand(1)) &&
12637 cast<ConstantSDNode>(Op.getOperand(1))->isNullValue())) &&
12638 (User->getOpcode() != ISD::BITCAST ||
12639 User->getValueType(0) != MVT::i32))
12641 SDValue Extract = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
12642 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32,
12645 return DAG.getNode(ISD::BITCAST, dl, MVT::f32, Extract);
12648 if (VT == MVT::i32 || VT == MVT::i64) {
12649 // ExtractPS/pextrq works with constant index.
12650 if (isa<ConstantSDNode>(Op.getOperand(1)))
12656 /// Extract one bit from mask vector, like v16i1 or v8i1.
12657 /// AVX-512 feature.
12659 X86TargetLowering::ExtractBitFromMaskVector(SDValue Op, SelectionDAG &DAG) const {
12660 SDValue Vec = Op.getOperand(0);
12662 MVT VecVT = Vec.getSimpleValueType();
12663 SDValue Idx = Op.getOperand(1);
12664 MVT EltVT = Op.getSimpleValueType();
12666 assert((EltVT == MVT::i1) && "Unexpected operands in ExtractBitFromMaskVector");
12668 // variable index can't be handled in mask registers,
12669 // extend vector to VR512
12670 if (!isa<ConstantSDNode>(Idx)) {
12671 MVT ExtVT = (VecVT == MVT::v8i1 ? MVT::v8i64 : MVT::v16i32);
12672 SDValue Ext = DAG.getNode(ISD::ZERO_EXTEND, dl, ExtVT, Vec);
12673 SDValue Elt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
12674 ExtVT.getVectorElementType(), Ext, Idx);
12675 return DAG.getNode(ISD::TRUNCATE, dl, EltVT, Elt);
12678 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
12679 const TargetRegisterClass* rc = getRegClassFor(VecVT);
12680 unsigned MaxSift = rc->getSize()*8 - 1;
12681 Vec = DAG.getNode(X86ISD::VSHLI, dl, VecVT, Vec,
12682 DAG.getConstant(MaxSift - IdxVal, MVT::i8));
12683 Vec = DAG.getNode(X86ISD::VSRLI, dl, VecVT, Vec,
12684 DAG.getConstant(MaxSift, MVT::i8));
12685 return DAG.getNode(X86ISD::VEXTRACT, dl, MVT::i1, Vec,
12686 DAG.getIntPtrConstant(0));
12690 X86TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op,
12691 SelectionDAG &DAG) const {
12693 SDValue Vec = Op.getOperand(0);
12694 MVT VecVT = Vec.getSimpleValueType();
12695 SDValue Idx = Op.getOperand(1);
12697 if (Op.getSimpleValueType() == MVT::i1)
12698 return ExtractBitFromMaskVector(Op, DAG);
12700 if (!isa<ConstantSDNode>(Idx)) {
12701 if (VecVT.is512BitVector() ||
12702 (VecVT.is256BitVector() && Subtarget->hasInt256() &&
12703 VecVT.getVectorElementType().getSizeInBits() == 32)) {
12706 MVT::getIntegerVT(VecVT.getVectorElementType().getSizeInBits());
12707 MVT MaskVT = MVT::getVectorVT(MaskEltVT, VecVT.getSizeInBits() /
12708 MaskEltVT.getSizeInBits());
12710 Idx = DAG.getZExtOrTrunc(Idx, dl, MaskEltVT);
12711 SDValue Mask = DAG.getNode(X86ISD::VINSERT, dl, MaskVT,
12712 getZeroVector(MaskVT, Subtarget, DAG, dl),
12713 Idx, DAG.getConstant(0, getPointerTy()));
12714 SDValue Perm = DAG.getNode(X86ISD::VPERMV, dl, VecVT, Mask, Vec);
12715 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, Op.getValueType(),
12716 Perm, DAG.getConstant(0, getPointerTy()));
12721 // If this is a 256-bit vector result, first extract the 128-bit vector and
12722 // then extract the element from the 128-bit vector.
12723 if (VecVT.is256BitVector() || VecVT.is512BitVector()) {
12725 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
12726 // Get the 128-bit vector.
12727 Vec = Extract128BitVector(Vec, IdxVal, DAG, dl);
12728 MVT EltVT = VecVT.getVectorElementType();
12730 unsigned ElemsPerChunk = 128 / EltVT.getSizeInBits();
12732 //if (IdxVal >= NumElems/2)
12733 // IdxVal -= NumElems/2;
12734 IdxVal -= (IdxVal/ElemsPerChunk)*ElemsPerChunk;
12735 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, Op.getValueType(), Vec,
12736 DAG.getConstant(IdxVal, MVT::i32));
12739 assert(VecVT.is128BitVector() && "Unexpected vector length");
12741 if (Subtarget->hasSSE41()) {
12742 SDValue Res = LowerEXTRACT_VECTOR_ELT_SSE4(Op, DAG);
12747 MVT VT = Op.getSimpleValueType();
12748 // TODO: handle v16i8.
12749 if (VT.getSizeInBits() == 16) {
12750 SDValue Vec = Op.getOperand(0);
12751 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
12753 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
12754 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
12755 DAG.getNode(ISD::BITCAST, dl,
12757 Op.getOperand(1)));
12758 // Transform it so it match pextrw which produces a 32-bit result.
12759 MVT EltVT = MVT::i32;
12760 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, EltVT,
12761 Op.getOperand(0), Op.getOperand(1));
12762 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, EltVT, Extract,
12763 DAG.getValueType(VT));
12764 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
12767 if (VT.getSizeInBits() == 32) {
12768 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
12772 // SHUFPS the element to the lowest double word, then movss.
12773 int Mask[4] = { static_cast<int>(Idx), -1, -1, -1 };
12774 MVT VVT = Op.getOperand(0).getSimpleValueType();
12775 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
12776 DAG.getUNDEF(VVT), Mask);
12777 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
12778 DAG.getIntPtrConstant(0));
12781 if (VT.getSizeInBits() == 64) {
12782 // FIXME: .td only matches this for <2 x f64>, not <2 x i64> on 32b
12783 // FIXME: seems like this should be unnecessary if mov{h,l}pd were taught
12784 // to match extract_elt for f64.
12785 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
12789 // UNPCKHPD the element to the lowest double word, then movsd.
12790 // Note if the lower 64 bits of the result of the UNPCKHPD is then stored
12791 // to a f64mem, the whole operation is folded into a single MOVHPDmr.
12792 int Mask[2] = { 1, -1 };
12793 MVT VVT = Op.getOperand(0).getSimpleValueType();
12794 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
12795 DAG.getUNDEF(VVT), Mask);
12796 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
12797 DAG.getIntPtrConstant(0));
12803 /// Insert one bit to mask vector, like v16i1 or v8i1.
12804 /// AVX-512 feature.
12806 X86TargetLowering::InsertBitToMaskVector(SDValue Op, SelectionDAG &DAG) const {
12808 SDValue Vec = Op.getOperand(0);
12809 SDValue Elt = Op.getOperand(1);
12810 SDValue Idx = Op.getOperand(2);
12811 MVT VecVT = Vec.getSimpleValueType();
12813 if (!isa<ConstantSDNode>(Idx)) {
12814 // Non constant index. Extend source and destination,
12815 // insert element and then truncate the result.
12816 MVT ExtVecVT = (VecVT == MVT::v8i1 ? MVT::v8i64 : MVT::v16i32);
12817 MVT ExtEltVT = (VecVT == MVT::v8i1 ? MVT::i64 : MVT::i32);
12818 SDValue ExtOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, ExtVecVT,
12819 DAG.getNode(ISD::ZERO_EXTEND, dl, ExtVecVT, Vec),
12820 DAG.getNode(ISD::ZERO_EXTEND, dl, ExtEltVT, Elt), Idx);
12821 return DAG.getNode(ISD::TRUNCATE, dl, VecVT, ExtOp);
12824 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
12825 SDValue EltInVec = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Elt);
12826 if (Vec.getOpcode() == ISD::UNDEF)
12827 return DAG.getNode(X86ISD::VSHLI, dl, VecVT, EltInVec,
12828 DAG.getConstant(IdxVal, MVT::i8));
12829 const TargetRegisterClass* rc = getRegClassFor(VecVT);
12830 unsigned MaxSift = rc->getSize()*8 - 1;
12831 EltInVec = DAG.getNode(X86ISD::VSHLI, dl, VecVT, EltInVec,
12832 DAG.getConstant(MaxSift, MVT::i8));
12833 EltInVec = DAG.getNode(X86ISD::VSRLI, dl, VecVT, EltInVec,
12834 DAG.getConstant(MaxSift - IdxVal, MVT::i8));
12835 return DAG.getNode(ISD::OR, dl, VecVT, Vec, EltInVec);
12838 SDValue X86TargetLowering::LowerINSERT_VECTOR_ELT(SDValue Op,
12839 SelectionDAG &DAG) const {
12840 MVT VT = Op.getSimpleValueType();
12841 MVT EltVT = VT.getVectorElementType();
12843 if (EltVT == MVT::i1)
12844 return InsertBitToMaskVector(Op, DAG);
12847 SDValue N0 = Op.getOperand(0);
12848 SDValue N1 = Op.getOperand(1);
12849 SDValue N2 = Op.getOperand(2);
12850 if (!isa<ConstantSDNode>(N2))
12852 auto *N2C = cast<ConstantSDNode>(N2);
12853 unsigned IdxVal = N2C->getZExtValue();
12855 // If the vector is wider than 128 bits, extract the 128-bit subvector, insert
12856 // into that, and then insert the subvector back into the result.
12857 if (VT.is256BitVector() || VT.is512BitVector()) {
12858 // Get the desired 128-bit vector half.
12859 SDValue V = Extract128BitVector(N0, IdxVal, DAG, dl);
12861 // Insert the element into the desired half.
12862 unsigned NumEltsIn128 = 128 / EltVT.getSizeInBits();
12863 unsigned IdxIn128 = IdxVal - (IdxVal / NumEltsIn128) * NumEltsIn128;
12865 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, V.getValueType(), V, N1,
12866 DAG.getConstant(IdxIn128, MVT::i32));
12868 // Insert the changed part back to the 256-bit vector
12869 return Insert128BitVector(N0, V, IdxVal, DAG, dl);
12871 assert(VT.is128BitVector() && "Only 128-bit vector types should be left!");
12873 if (Subtarget->hasSSE41()) {
12874 if (EltVT.getSizeInBits() == 8 || EltVT.getSizeInBits() == 16) {
12876 if (VT == MVT::v8i16) {
12877 Opc = X86ISD::PINSRW;
12879 assert(VT == MVT::v16i8);
12880 Opc = X86ISD::PINSRB;
12883 // Transform it so it match pinsr{b,w} which expects a GR32 as its second
12885 if (N1.getValueType() != MVT::i32)
12886 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
12887 if (N2.getValueType() != MVT::i32)
12888 N2 = DAG.getIntPtrConstant(IdxVal);
12889 return DAG.getNode(Opc, dl, VT, N0, N1, N2);
12892 if (EltVT == MVT::f32) {
12893 // Bits [7:6] of the constant are the source select. This will always be
12894 // zero here. The DAG Combiner may combine an extract_elt index into
12896 // bits. For example (insert (extract, 3), 2) could be matched by
12898 // the '3' into bits [7:6] of X86ISD::INSERTPS.
12899 // Bits [5:4] of the constant are the destination select. This is the
12900 // value of the incoming immediate.
12901 // Bits [3:0] of the constant are the zero mask. The DAG Combiner may
12902 // combine either bitwise AND or insert of float 0.0 to set these bits.
12903 N2 = DAG.getIntPtrConstant(IdxVal << 4);
12904 // Create this as a scalar to vector..
12905 N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4f32, N1);
12906 return DAG.getNode(X86ISD::INSERTPS, dl, VT, N0, N1, N2);
12909 if (EltVT == MVT::i32 || EltVT == MVT::i64) {
12910 // PINSR* works with constant index.
12915 if (EltVT == MVT::i8)
12918 if (EltVT.getSizeInBits() == 16) {
12919 // Transform it so it match pinsrw which expects a 16-bit value in a GR32
12920 // as its second argument.
12921 if (N1.getValueType() != MVT::i32)
12922 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
12923 if (N2.getValueType() != MVT::i32)
12924 N2 = DAG.getIntPtrConstant(IdxVal);
12925 return DAG.getNode(X86ISD::PINSRW, dl, VT, N0, N1, N2);
12930 static SDValue LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) {
12932 MVT OpVT = Op.getSimpleValueType();
12934 // If this is a 256-bit vector result, first insert into a 128-bit
12935 // vector and then insert into the 256-bit vector.
12936 if (!OpVT.is128BitVector()) {
12937 // Insert into a 128-bit vector.
12938 unsigned SizeFactor = OpVT.getSizeInBits()/128;
12939 MVT VT128 = MVT::getVectorVT(OpVT.getVectorElementType(),
12940 OpVT.getVectorNumElements() / SizeFactor);
12942 Op = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT128, Op.getOperand(0));
12944 // Insert the 128-bit vector.
12945 return Insert128BitVector(DAG.getUNDEF(OpVT), Op, 0, DAG, dl);
12948 if (OpVT == MVT::v1i64 &&
12949 Op.getOperand(0).getValueType() == MVT::i64)
12950 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v1i64, Op.getOperand(0));
12952 SDValue AnyExt = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, Op.getOperand(0));
12953 assert(OpVT.is128BitVector() && "Expected an SSE type!");
12954 return DAG.getNode(ISD::BITCAST, dl, OpVT,
12955 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,AnyExt));
12958 // Lower a node with an EXTRACT_SUBVECTOR opcode. This may result in
12959 // a simple subregister reference or explicit instructions to grab
12960 // upper bits of a vector.
12961 static SDValue LowerEXTRACT_SUBVECTOR(SDValue Op, const X86Subtarget *Subtarget,
12962 SelectionDAG &DAG) {
12964 SDValue In = Op.getOperand(0);
12965 SDValue Idx = Op.getOperand(1);
12966 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
12967 MVT ResVT = Op.getSimpleValueType();
12968 MVT InVT = In.getSimpleValueType();
12970 if (Subtarget->hasFp256()) {
12971 if (ResVT.is128BitVector() &&
12972 (InVT.is256BitVector() || InVT.is512BitVector()) &&
12973 isa<ConstantSDNode>(Idx)) {
12974 return Extract128BitVector(In, IdxVal, DAG, dl);
12976 if (ResVT.is256BitVector() && InVT.is512BitVector() &&
12977 isa<ConstantSDNode>(Idx)) {
12978 return Extract256BitVector(In, IdxVal, DAG, dl);
12984 // Lower a node with an INSERT_SUBVECTOR opcode. This may result in a
12985 // simple superregister reference or explicit instructions to insert
12986 // the upper bits of a vector.
12987 static SDValue LowerINSERT_SUBVECTOR(SDValue Op, const X86Subtarget *Subtarget,
12988 SelectionDAG &DAG) {
12989 if (Subtarget->hasFp256()) {
12990 SDLoc dl(Op.getNode());
12991 SDValue Vec = Op.getNode()->getOperand(0);
12992 SDValue SubVec = Op.getNode()->getOperand(1);
12993 SDValue Idx = Op.getNode()->getOperand(2);
12995 if ((Op.getNode()->getSimpleValueType(0).is256BitVector() ||
12996 Op.getNode()->getSimpleValueType(0).is512BitVector()) &&
12997 SubVec.getNode()->getSimpleValueType(0).is128BitVector() &&
12998 isa<ConstantSDNode>(Idx)) {
12999 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
13000 return Insert128BitVector(Vec, SubVec, IdxVal, DAG, dl);
13003 if (Op.getNode()->getSimpleValueType(0).is512BitVector() &&
13004 SubVec.getNode()->getSimpleValueType(0).is256BitVector() &&
13005 isa<ConstantSDNode>(Idx)) {
13006 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
13007 return Insert256BitVector(Vec, SubVec, IdxVal, DAG, dl);
13013 // ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as
13014 // their target countpart wrapped in the X86ISD::Wrapper node. Suppose N is
13015 // one of the above mentioned nodes. It has to be wrapped because otherwise
13016 // Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only
13017 // be used to form addressing mode. These wrapped nodes will be selected
13020 X86TargetLowering::LowerConstantPool(SDValue Op, SelectionDAG &DAG) const {
13021 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
13023 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
13024 // global base reg.
13025 unsigned char OpFlag = 0;
13026 unsigned WrapperKind = X86ISD::Wrapper;
13027 CodeModel::Model M = DAG.getTarget().getCodeModel();
13029 if (Subtarget->isPICStyleRIPRel() &&
13030 (M == CodeModel::Small || M == CodeModel::Kernel))
13031 WrapperKind = X86ISD::WrapperRIP;
13032 else if (Subtarget->isPICStyleGOT())
13033 OpFlag = X86II::MO_GOTOFF;
13034 else if (Subtarget->isPICStyleStubPIC())
13035 OpFlag = X86II::MO_PIC_BASE_OFFSET;
13037 SDValue Result = DAG.getTargetConstantPool(CP->getConstVal(), getPointerTy(),
13038 CP->getAlignment(),
13039 CP->getOffset(), OpFlag);
13041 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
13042 // With PIC, the address is actually $g + Offset.
13044 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
13045 DAG.getNode(X86ISD::GlobalBaseReg,
13046 SDLoc(), getPointerTy()),
13053 SDValue X86TargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) const {
13054 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
13056 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
13057 // global base reg.
13058 unsigned char OpFlag = 0;
13059 unsigned WrapperKind = X86ISD::Wrapper;
13060 CodeModel::Model M = DAG.getTarget().getCodeModel();
13062 if (Subtarget->isPICStyleRIPRel() &&
13063 (M == CodeModel::Small || M == CodeModel::Kernel))
13064 WrapperKind = X86ISD::WrapperRIP;
13065 else if (Subtarget->isPICStyleGOT())
13066 OpFlag = X86II::MO_GOTOFF;
13067 else if (Subtarget->isPICStyleStubPIC())
13068 OpFlag = X86II::MO_PIC_BASE_OFFSET;
13070 SDValue Result = DAG.getTargetJumpTable(JT->getIndex(), getPointerTy(),
13073 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
13075 // With PIC, the address is actually $g + Offset.
13077 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
13078 DAG.getNode(X86ISD::GlobalBaseReg,
13079 SDLoc(), getPointerTy()),
13086 X86TargetLowering::LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) const {
13087 const char *Sym = cast<ExternalSymbolSDNode>(Op)->getSymbol();
13089 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
13090 // global base reg.
13091 unsigned char OpFlag = 0;
13092 unsigned WrapperKind = X86ISD::Wrapper;
13093 CodeModel::Model M = DAG.getTarget().getCodeModel();
13095 if (Subtarget->isPICStyleRIPRel() &&
13096 (M == CodeModel::Small || M == CodeModel::Kernel)) {
13097 if (Subtarget->isTargetDarwin() || Subtarget->isTargetELF())
13098 OpFlag = X86II::MO_GOTPCREL;
13099 WrapperKind = X86ISD::WrapperRIP;
13100 } else if (Subtarget->isPICStyleGOT()) {
13101 OpFlag = X86II::MO_GOT;
13102 } else if (Subtarget->isPICStyleStubPIC()) {
13103 OpFlag = X86II::MO_DARWIN_NONLAZY_PIC_BASE;
13104 } else if (Subtarget->isPICStyleStubNoDynamic()) {
13105 OpFlag = X86II::MO_DARWIN_NONLAZY;
13108 SDValue Result = DAG.getTargetExternalSymbol(Sym, getPointerTy(), OpFlag);
13111 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
13113 // With PIC, the address is actually $g + Offset.
13114 if (DAG.getTarget().getRelocationModel() == Reloc::PIC_ &&
13115 !Subtarget->is64Bit()) {
13116 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
13117 DAG.getNode(X86ISD::GlobalBaseReg,
13118 SDLoc(), getPointerTy()),
13122 // For symbols that require a load from a stub to get the address, emit the
13124 if (isGlobalStubReference(OpFlag))
13125 Result = DAG.getLoad(getPointerTy(), DL, DAG.getEntryNode(), Result,
13126 MachinePointerInfo::getGOT(), false, false, false, 0);
13132 X86TargetLowering::LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const {
13133 // Create the TargetBlockAddressAddress node.
13134 unsigned char OpFlags =
13135 Subtarget->ClassifyBlockAddressReference();
13136 CodeModel::Model M = DAG.getTarget().getCodeModel();
13137 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
13138 int64_t Offset = cast<BlockAddressSDNode>(Op)->getOffset();
13140 SDValue Result = DAG.getTargetBlockAddress(BA, getPointerTy(), Offset,
13143 if (Subtarget->isPICStyleRIPRel() &&
13144 (M == CodeModel::Small || M == CodeModel::Kernel))
13145 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
13147 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
13149 // With PIC, the address is actually $g + Offset.
13150 if (isGlobalRelativeToPICBase(OpFlags)) {
13151 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
13152 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
13160 X86TargetLowering::LowerGlobalAddress(const GlobalValue *GV, SDLoc dl,
13161 int64_t Offset, SelectionDAG &DAG) const {
13162 // Create the TargetGlobalAddress node, folding in the constant
13163 // offset if it is legal.
13164 unsigned char OpFlags =
13165 Subtarget->ClassifyGlobalReference(GV, DAG.getTarget());
13166 CodeModel::Model M = DAG.getTarget().getCodeModel();
13168 if (OpFlags == X86II::MO_NO_FLAG &&
13169 X86::isOffsetSuitableForCodeModel(Offset, M)) {
13170 // A direct static reference to a global.
13171 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), Offset);
13174 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), 0, OpFlags);
13177 if (Subtarget->isPICStyleRIPRel() &&
13178 (M == CodeModel::Small || M == CodeModel::Kernel))
13179 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
13181 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
13183 // With PIC, the address is actually $g + Offset.
13184 if (isGlobalRelativeToPICBase(OpFlags)) {
13185 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
13186 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
13190 // For globals that require a load from a stub to get the address, emit the
13192 if (isGlobalStubReference(OpFlags))
13193 Result = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Result,
13194 MachinePointerInfo::getGOT(), false, false, false, 0);
13196 // If there was a non-zero offset that we didn't fold, create an explicit
13197 // addition for it.
13199 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(), Result,
13200 DAG.getConstant(Offset, getPointerTy()));
13206 X86TargetLowering::LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const {
13207 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
13208 int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset();
13209 return LowerGlobalAddress(GV, SDLoc(Op), Offset, DAG);
13213 GetTLSADDR(SelectionDAG &DAG, SDValue Chain, GlobalAddressSDNode *GA,
13214 SDValue *InFlag, const EVT PtrVT, unsigned ReturnReg,
13215 unsigned char OperandFlags, bool LocalDynamic = false) {
13216 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
13217 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
13219 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
13220 GA->getValueType(0),
13224 X86ISD::NodeType CallType = LocalDynamic ? X86ISD::TLSBASEADDR
13228 SDValue Ops[] = { Chain, TGA, *InFlag };
13229 Chain = DAG.getNode(CallType, dl, NodeTys, Ops);
13231 SDValue Ops[] = { Chain, TGA };
13232 Chain = DAG.getNode(CallType, dl, NodeTys, Ops);
13235 // TLSADDR will be codegen'ed as call. Inform MFI that function has calls.
13236 MFI->setAdjustsStack(true);
13237 MFI->setHasCalls(true);
13239 SDValue Flag = Chain.getValue(1);
13240 return DAG.getCopyFromReg(Chain, dl, ReturnReg, PtrVT, Flag);
13243 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 32 bit
13245 LowerToTLSGeneralDynamicModel32(GlobalAddressSDNode *GA, SelectionDAG &DAG,
13248 SDLoc dl(GA); // ? function entry point might be better
13249 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
13250 DAG.getNode(X86ISD::GlobalBaseReg,
13251 SDLoc(), PtrVT), InFlag);
13252 InFlag = Chain.getValue(1);
13254 return GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX, X86II::MO_TLSGD);
13257 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 64 bit
13259 LowerToTLSGeneralDynamicModel64(GlobalAddressSDNode *GA, SelectionDAG &DAG,
13261 return GetTLSADDR(DAG, DAG.getEntryNode(), GA, nullptr, PtrVT,
13262 X86::RAX, X86II::MO_TLSGD);
13265 static SDValue LowerToTLSLocalDynamicModel(GlobalAddressSDNode *GA,
13271 // Get the start address of the TLS block for this module.
13272 X86MachineFunctionInfo* MFI = DAG.getMachineFunction()
13273 .getInfo<X86MachineFunctionInfo>();
13274 MFI->incNumLocalDynamicTLSAccesses();
13278 Base = GetTLSADDR(DAG, DAG.getEntryNode(), GA, nullptr, PtrVT, X86::RAX,
13279 X86II::MO_TLSLD, /*LocalDynamic=*/true);
13282 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
13283 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT), InFlag);
13284 InFlag = Chain.getValue(1);
13285 Base = GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX,
13286 X86II::MO_TLSLDM, /*LocalDynamic=*/true);
13289 // Note: the CleanupLocalDynamicTLSPass will remove redundant computations
13293 unsigned char OperandFlags = X86II::MO_DTPOFF;
13294 unsigned WrapperKind = X86ISD::Wrapper;
13295 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
13296 GA->getValueType(0),
13297 GA->getOffset(), OperandFlags);
13298 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
13300 // Add x@dtpoff with the base.
13301 return DAG.getNode(ISD::ADD, dl, PtrVT, Offset, Base);
13304 // Lower ISD::GlobalTLSAddress using the "initial exec" or "local exec" model.
13305 static SDValue LowerToTLSExecModel(GlobalAddressSDNode *GA, SelectionDAG &DAG,
13306 const EVT PtrVT, TLSModel::Model model,
13307 bool is64Bit, bool isPIC) {
13310 // Get the Thread Pointer, which is %gs:0 (32-bit) or %fs:0 (64-bit).
13311 Value *Ptr = Constant::getNullValue(Type::getInt8PtrTy(*DAG.getContext(),
13312 is64Bit ? 257 : 256));
13314 SDValue ThreadPointer =
13315 DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), DAG.getIntPtrConstant(0),
13316 MachinePointerInfo(Ptr), false, false, false, 0);
13318 unsigned char OperandFlags = 0;
13319 // Most TLS accesses are not RIP relative, even on x86-64. One exception is
13321 unsigned WrapperKind = X86ISD::Wrapper;
13322 if (model == TLSModel::LocalExec) {
13323 OperandFlags = is64Bit ? X86II::MO_TPOFF : X86II::MO_NTPOFF;
13324 } else if (model == TLSModel::InitialExec) {
13326 OperandFlags = X86II::MO_GOTTPOFF;
13327 WrapperKind = X86ISD::WrapperRIP;
13329 OperandFlags = isPIC ? X86II::MO_GOTNTPOFF : X86II::MO_INDNTPOFF;
13332 llvm_unreachable("Unexpected model");
13335 // emit "addl x@ntpoff,%eax" (local exec)
13336 // or "addl x@indntpoff,%eax" (initial exec)
13337 // or "addl x@gotntpoff(%ebx) ,%eax" (initial exec, 32-bit pic)
13339 DAG.getTargetGlobalAddress(GA->getGlobal(), dl, GA->getValueType(0),
13340 GA->getOffset(), OperandFlags);
13341 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
13343 if (model == TLSModel::InitialExec) {
13344 if (isPIC && !is64Bit) {
13345 Offset = DAG.getNode(ISD::ADD, dl, PtrVT,
13346 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT),
13350 Offset = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Offset,
13351 MachinePointerInfo::getGOT(), false, false, false, 0);
13354 // The address of the thread local variable is the add of the thread
13355 // pointer with the offset of the variable.
13356 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset);
13360 X86TargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const {
13362 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
13363 const GlobalValue *GV = GA->getGlobal();
13365 if (Subtarget->isTargetELF()) {
13366 TLSModel::Model model = DAG.getTarget().getTLSModel(GV);
13369 case TLSModel::GeneralDynamic:
13370 if (Subtarget->is64Bit())
13371 return LowerToTLSGeneralDynamicModel64(GA, DAG, getPointerTy());
13372 return LowerToTLSGeneralDynamicModel32(GA, DAG, getPointerTy());
13373 case TLSModel::LocalDynamic:
13374 return LowerToTLSLocalDynamicModel(GA, DAG, getPointerTy(),
13375 Subtarget->is64Bit());
13376 case TLSModel::InitialExec:
13377 case TLSModel::LocalExec:
13378 return LowerToTLSExecModel(
13379 GA, DAG, getPointerTy(), model, Subtarget->is64Bit(),
13380 DAG.getTarget().getRelocationModel() == Reloc::PIC_);
13382 llvm_unreachable("Unknown TLS model.");
13385 if (Subtarget->isTargetDarwin()) {
13386 // Darwin only has one model of TLS. Lower to that.
13387 unsigned char OpFlag = 0;
13388 unsigned WrapperKind = Subtarget->isPICStyleRIPRel() ?
13389 X86ISD::WrapperRIP : X86ISD::Wrapper;
13391 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
13392 // global base reg.
13393 bool PIC32 = (DAG.getTarget().getRelocationModel() == Reloc::PIC_) &&
13394 !Subtarget->is64Bit();
13396 OpFlag = X86II::MO_TLVP_PIC_BASE;
13398 OpFlag = X86II::MO_TLVP;
13400 SDValue Result = DAG.getTargetGlobalAddress(GA->getGlobal(), DL,
13401 GA->getValueType(0),
13402 GA->getOffset(), OpFlag);
13403 SDValue Offset = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
13405 // With PIC32, the address is actually $g + Offset.
13407 Offset = DAG.getNode(ISD::ADD, DL, getPointerTy(),
13408 DAG.getNode(X86ISD::GlobalBaseReg,
13409 SDLoc(), getPointerTy()),
13412 // Lowering the machine isd will make sure everything is in the right
13414 SDValue Chain = DAG.getEntryNode();
13415 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
13416 SDValue Args[] = { Chain, Offset };
13417 Chain = DAG.getNode(X86ISD::TLSCALL, DL, NodeTys, Args);
13419 // TLSCALL will be codegen'ed as call. Inform MFI that function has calls.
13420 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
13421 MFI->setAdjustsStack(true);
13423 // And our return value (tls address) is in the standard call return value
13425 unsigned Reg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
13426 return DAG.getCopyFromReg(Chain, DL, Reg, getPointerTy(),
13427 Chain.getValue(1));
13430 if (Subtarget->isTargetKnownWindowsMSVC() ||
13431 Subtarget->isTargetWindowsGNU()) {
13432 // Just use the implicit TLS architecture
13433 // Need to generate someting similar to:
13434 // mov rdx, qword [gs:abs 58H]; Load pointer to ThreadLocalStorage
13436 // mov ecx, dword [rel _tls_index]: Load index (from C runtime)
13437 // mov rcx, qword [rdx+rcx*8]
13438 // mov eax, .tls$:tlsvar
13439 // [rax+rcx] contains the address
13440 // Windows 64bit: gs:0x58
13441 // Windows 32bit: fs:__tls_array
13444 SDValue Chain = DAG.getEntryNode();
13446 // Get the Thread Pointer, which is %fs:__tls_array (32-bit) or
13447 // %gs:0x58 (64-bit). On MinGW, __tls_array is not available, so directly
13448 // use its literal value of 0x2C.
13449 Value *Ptr = Constant::getNullValue(Subtarget->is64Bit()
13450 ? Type::getInt8PtrTy(*DAG.getContext(),
13452 : Type::getInt32PtrTy(*DAG.getContext(),
13456 Subtarget->is64Bit()
13457 ? DAG.getIntPtrConstant(0x58)
13458 : (Subtarget->isTargetWindowsGNU()
13459 ? DAG.getIntPtrConstant(0x2C)
13460 : DAG.getExternalSymbol("_tls_array", getPointerTy()));
13462 SDValue ThreadPointer =
13463 DAG.getLoad(getPointerTy(), dl, Chain, TlsArray,
13464 MachinePointerInfo(Ptr), false, false, false, 0);
13466 // Load the _tls_index variable
13467 SDValue IDX = DAG.getExternalSymbol("_tls_index", getPointerTy());
13468 if (Subtarget->is64Bit())
13469 IDX = DAG.getExtLoad(ISD::ZEXTLOAD, dl, getPointerTy(), Chain,
13470 IDX, MachinePointerInfo(), MVT::i32,
13471 false, false, false, 0);
13473 IDX = DAG.getLoad(getPointerTy(), dl, Chain, IDX, MachinePointerInfo(),
13474 false, false, false, 0);
13476 SDValue Scale = DAG.getConstant(Log2_64_Ceil(TD->getPointerSize()),
13478 IDX = DAG.getNode(ISD::SHL, dl, getPointerTy(), IDX, Scale);
13480 SDValue res = DAG.getNode(ISD::ADD, dl, getPointerTy(), ThreadPointer, IDX);
13481 res = DAG.getLoad(getPointerTy(), dl, Chain, res, MachinePointerInfo(),
13482 false, false, false, 0);
13484 // Get the offset of start of .tls section
13485 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
13486 GA->getValueType(0),
13487 GA->getOffset(), X86II::MO_SECREL);
13488 SDValue Offset = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), TGA);
13490 // The address of the thread local variable is the add of the thread
13491 // pointer with the offset of the variable.
13492 return DAG.getNode(ISD::ADD, dl, getPointerTy(), res, Offset);
13495 llvm_unreachable("TLS not implemented for this target.");
13498 /// LowerShiftParts - Lower SRA_PARTS and friends, which return two i32 values
13499 /// and take a 2 x i32 value to shift plus a shift amount.
13500 static SDValue LowerShiftParts(SDValue Op, SelectionDAG &DAG) {
13501 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
13502 MVT VT = Op.getSimpleValueType();
13503 unsigned VTBits = VT.getSizeInBits();
13505 bool isSRA = Op.getOpcode() == ISD::SRA_PARTS;
13506 SDValue ShOpLo = Op.getOperand(0);
13507 SDValue ShOpHi = Op.getOperand(1);
13508 SDValue ShAmt = Op.getOperand(2);
13509 // X86ISD::SHLD and X86ISD::SHRD have defined overflow behavior but the
13510 // generic ISD nodes haven't. Insert an AND to be safe, it's optimized away
13512 SDValue SafeShAmt = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt,
13513 DAG.getConstant(VTBits - 1, MVT::i8));
13514 SDValue Tmp1 = isSRA ? DAG.getNode(ISD::SRA, dl, VT, ShOpHi,
13515 DAG.getConstant(VTBits - 1, MVT::i8))
13516 : DAG.getConstant(0, VT);
13518 SDValue Tmp2, Tmp3;
13519 if (Op.getOpcode() == ISD::SHL_PARTS) {
13520 Tmp2 = DAG.getNode(X86ISD::SHLD, dl, VT, ShOpHi, ShOpLo, ShAmt);
13521 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, SafeShAmt);
13523 Tmp2 = DAG.getNode(X86ISD::SHRD, dl, VT, ShOpLo, ShOpHi, ShAmt);
13524 Tmp3 = DAG.getNode(isSRA ? ISD::SRA : ISD::SRL, dl, VT, ShOpHi, SafeShAmt);
13527 // If the shift amount is larger or equal than the width of a part we can't
13528 // rely on the results of shld/shrd. Insert a test and select the appropriate
13529 // values for large shift amounts.
13530 SDValue AndNode = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt,
13531 DAG.getConstant(VTBits, MVT::i8));
13532 SDValue Cond = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
13533 AndNode, DAG.getConstant(0, MVT::i8));
13536 SDValue CC = DAG.getConstant(X86::COND_NE, MVT::i8);
13537 SDValue Ops0[4] = { Tmp2, Tmp3, CC, Cond };
13538 SDValue Ops1[4] = { Tmp3, Tmp1, CC, Cond };
13540 if (Op.getOpcode() == ISD::SHL_PARTS) {
13541 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0);
13542 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1);
13544 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0);
13545 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1);
13548 SDValue Ops[2] = { Lo, Hi };
13549 return DAG.getMergeValues(Ops, dl);
13552 SDValue X86TargetLowering::LowerSINT_TO_FP(SDValue Op,
13553 SelectionDAG &DAG) const {
13554 MVT SrcVT = Op.getOperand(0).getSimpleValueType();
13557 if (SrcVT.isVector()) {
13558 if (SrcVT.getVectorElementType() == MVT::i1) {
13559 MVT IntegerVT = MVT::getVectorVT(MVT::i32, SrcVT.getVectorNumElements());
13560 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(),
13561 DAG.getNode(ISD::SIGN_EXTEND, dl, IntegerVT,
13562 Op.getOperand(0)));
13567 assert(SrcVT <= MVT::i64 && SrcVT >= MVT::i16 &&
13568 "Unknown SINT_TO_FP to lower!");
13570 // These are really Legal; return the operand so the caller accepts it as
13572 if (SrcVT == MVT::i32 && isScalarFPTypeInSSEReg(Op.getValueType()))
13574 if (SrcVT == MVT::i64 && isScalarFPTypeInSSEReg(Op.getValueType()) &&
13575 Subtarget->is64Bit()) {
13579 unsigned Size = SrcVT.getSizeInBits()/8;
13580 MachineFunction &MF = DAG.getMachineFunction();
13581 int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size, false);
13582 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
13583 SDValue Chain = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
13585 MachinePointerInfo::getFixedStack(SSFI),
13587 return BuildFILD(Op, SrcVT, Chain, StackSlot, DAG);
13590 SDValue X86TargetLowering::BuildFILD(SDValue Op, EVT SrcVT, SDValue Chain,
13592 SelectionDAG &DAG) const {
13596 bool useSSE = isScalarFPTypeInSSEReg(Op.getValueType());
13598 Tys = DAG.getVTList(MVT::f64, MVT::Other, MVT::Glue);
13600 Tys = DAG.getVTList(Op.getValueType(), MVT::Other);
13602 unsigned ByteSize = SrcVT.getSizeInBits()/8;
13604 FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(StackSlot);
13605 MachineMemOperand *MMO;
13607 int SSFI = FI->getIndex();
13609 DAG.getMachineFunction()
13610 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
13611 MachineMemOperand::MOLoad, ByteSize, ByteSize);
13613 MMO = cast<LoadSDNode>(StackSlot)->getMemOperand();
13614 StackSlot = StackSlot.getOperand(1);
13616 SDValue Ops[] = { Chain, StackSlot, DAG.getValueType(SrcVT) };
13617 SDValue Result = DAG.getMemIntrinsicNode(useSSE ? X86ISD::FILD_FLAG :
13619 Tys, Ops, SrcVT, MMO);
13622 Chain = Result.getValue(1);
13623 SDValue InFlag = Result.getValue(2);
13625 // FIXME: Currently the FST is flagged to the FILD_FLAG. This
13626 // shouldn't be necessary except that RFP cannot be live across
13627 // multiple blocks. When stackifier is fixed, they can be uncoupled.
13628 MachineFunction &MF = DAG.getMachineFunction();
13629 unsigned SSFISize = Op.getValueType().getSizeInBits()/8;
13630 int SSFI = MF.getFrameInfo()->CreateStackObject(SSFISize, SSFISize, false);
13631 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
13632 Tys = DAG.getVTList(MVT::Other);
13634 Chain, Result, StackSlot, DAG.getValueType(Op.getValueType()), InFlag
13636 MachineMemOperand *MMO =
13637 DAG.getMachineFunction()
13638 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
13639 MachineMemOperand::MOStore, SSFISize, SSFISize);
13641 Chain = DAG.getMemIntrinsicNode(X86ISD::FST, DL, Tys,
13642 Ops, Op.getValueType(), MMO);
13643 Result = DAG.getLoad(Op.getValueType(), DL, Chain, StackSlot,
13644 MachinePointerInfo::getFixedStack(SSFI),
13645 false, false, false, 0);
13651 // LowerUINT_TO_FP_i64 - 64-bit unsigned integer to double expansion.
13652 SDValue X86TargetLowering::LowerUINT_TO_FP_i64(SDValue Op,
13653 SelectionDAG &DAG) const {
13654 // This algorithm is not obvious. Here it is what we're trying to output:
13657 punpckldq (c0), %xmm0 // c0: (uint4){ 0x43300000U, 0x45300000U, 0U, 0U }
13658 subpd (c1), %xmm0 // c1: (double2){ 0x1.0p52, 0x1.0p52 * 0x1.0p32 }
13660 haddpd %xmm0, %xmm0
13662 pshufd $0x4e, %xmm0, %xmm1
13668 LLVMContext *Context = DAG.getContext();
13670 // Build some magic constants.
13671 static const uint32_t CV0[] = { 0x43300000, 0x45300000, 0, 0 };
13672 Constant *C0 = ConstantDataVector::get(*Context, CV0);
13673 SDValue CPIdx0 = DAG.getConstantPool(C0, getPointerTy(), 16);
13675 SmallVector<Constant*,2> CV1;
13677 ConstantFP::get(*Context, APFloat(APFloat::IEEEdouble,
13678 APInt(64, 0x4330000000000000ULL))));
13680 ConstantFP::get(*Context, APFloat(APFloat::IEEEdouble,
13681 APInt(64, 0x4530000000000000ULL))));
13682 Constant *C1 = ConstantVector::get(CV1);
13683 SDValue CPIdx1 = DAG.getConstantPool(C1, getPointerTy(), 16);
13685 // Load the 64-bit value into an XMM register.
13686 SDValue XR1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
13688 SDValue CLod0 = DAG.getLoad(MVT::v4i32, dl, DAG.getEntryNode(), CPIdx0,
13689 MachinePointerInfo::getConstantPool(),
13690 false, false, false, 16);
13691 SDValue Unpck1 = getUnpackl(DAG, dl, MVT::v4i32,
13692 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, XR1),
13695 SDValue CLod1 = DAG.getLoad(MVT::v2f64, dl, CLod0.getValue(1), CPIdx1,
13696 MachinePointerInfo::getConstantPool(),
13697 false, false, false, 16);
13698 SDValue XR2F = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Unpck1);
13699 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, XR2F, CLod1);
13702 if (Subtarget->hasSSE3()) {
13703 // FIXME: The 'haddpd' instruction may be slower than 'movhlps + addsd'.
13704 Result = DAG.getNode(X86ISD::FHADD, dl, MVT::v2f64, Sub, Sub);
13706 SDValue S2F = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Sub);
13707 SDValue Shuffle = getTargetShuffleNode(X86ISD::PSHUFD, dl, MVT::v4i32,
13709 Result = DAG.getNode(ISD::FADD, dl, MVT::v2f64,
13710 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Shuffle),
13714 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Result,
13715 DAG.getIntPtrConstant(0));
13718 // LowerUINT_TO_FP_i32 - 32-bit unsigned integer to float expansion.
13719 SDValue X86TargetLowering::LowerUINT_TO_FP_i32(SDValue Op,
13720 SelectionDAG &DAG) const {
13722 // FP constant to bias correct the final result.
13723 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL),
13726 // Load the 32-bit value into an XMM register.
13727 SDValue Load = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,
13730 // Zero out the upper parts of the register.
13731 Load = getShuffleVectorZeroOrUndef(Load, 0, true, Subtarget, DAG);
13733 Load = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
13734 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Load),
13735 DAG.getIntPtrConstant(0));
13737 // Or the load with the bias.
13738 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64,
13739 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
13740 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
13741 MVT::v2f64, Load)),
13742 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
13743 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
13744 MVT::v2f64, Bias)));
13745 Or = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
13746 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Or),
13747 DAG.getIntPtrConstant(0));
13749 // Subtract the bias.
13750 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Or, Bias);
13752 // Handle final rounding.
13753 EVT DestVT = Op.getValueType();
13755 if (DestVT.bitsLT(MVT::f64))
13756 return DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub,
13757 DAG.getIntPtrConstant(0));
13758 if (DestVT.bitsGT(MVT::f64))
13759 return DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub);
13761 // Handle final rounding.
13765 static SDValue lowerUINT_TO_FP_vXi32(SDValue Op, SelectionDAG &DAG,
13766 const X86Subtarget &Subtarget) {
13767 // The algorithm is the following:
13768 // #ifdef __SSE4_1__
13769 // uint4 lo = _mm_blend_epi16( v, (uint4) 0x4b000000, 0xaa);
13770 // uint4 hi = _mm_blend_epi16( _mm_srli_epi32(v,16),
13771 // (uint4) 0x53000000, 0xaa);
13773 // uint4 lo = (v & (uint4) 0xffff) | (uint4) 0x4b000000;
13774 // uint4 hi = (v >> 16) | (uint4) 0x53000000;
13776 // float4 fhi = (float4) hi - (0x1.0p39f + 0x1.0p23f);
13777 // return (float4) lo + fhi;
13780 SDValue V = Op->getOperand(0);
13781 EVT VecIntVT = V.getValueType();
13782 bool Is128 = VecIntVT == MVT::v4i32;
13783 EVT VecFloatVT = Is128 ? MVT::v4f32 : MVT::v8f32;
13784 // If we convert to something else than the supported type, e.g., to v4f64,
13786 if (VecFloatVT != Op->getValueType(0))
13789 unsigned NumElts = VecIntVT.getVectorNumElements();
13790 assert((VecIntVT == MVT::v4i32 || VecIntVT == MVT::v8i32) &&
13791 "Unsupported custom type");
13792 assert(NumElts <= 8 && "The size of the constant array must be fixed");
13794 // In the #idef/#else code, we have in common:
13795 // - The vector of constants:
13801 // Create the splat vector for 0x4b000000.
13802 SDValue CstLow = DAG.getConstant(0x4b000000, MVT::i32);
13803 SDValue CstLowArray[] = {CstLow, CstLow, CstLow, CstLow,
13804 CstLow, CstLow, CstLow, CstLow};
13805 SDValue VecCstLow = DAG.getNode(ISD::BUILD_VECTOR, DL, VecIntVT,
13806 makeArrayRef(&CstLowArray[0], NumElts));
13807 // Create the splat vector for 0x53000000.
13808 SDValue CstHigh = DAG.getConstant(0x53000000, MVT::i32);
13809 SDValue CstHighArray[] = {CstHigh, CstHigh, CstHigh, CstHigh,
13810 CstHigh, CstHigh, CstHigh, CstHigh};
13811 SDValue VecCstHigh = DAG.getNode(ISD::BUILD_VECTOR, DL, VecIntVT,
13812 makeArrayRef(&CstHighArray[0], NumElts));
13814 // Create the right shift.
13815 SDValue CstShift = DAG.getConstant(16, MVT::i32);
13816 SDValue CstShiftArray[] = {CstShift, CstShift, CstShift, CstShift,
13817 CstShift, CstShift, CstShift, CstShift};
13818 SDValue VecCstShift = DAG.getNode(ISD::BUILD_VECTOR, DL, VecIntVT,
13819 makeArrayRef(&CstShiftArray[0], NumElts));
13820 SDValue HighShift = DAG.getNode(ISD::SRL, DL, VecIntVT, V, VecCstShift);
13823 if (Subtarget.hasSSE41()) {
13824 EVT VecI16VT = Is128 ? MVT::v8i16 : MVT::v16i16;
13825 // uint4 lo = _mm_blend_epi16( v, (uint4) 0x4b000000, 0xaa);
13826 SDValue VecCstLowBitcast =
13827 DAG.getNode(ISD::BITCAST, DL, VecI16VT, VecCstLow);
13828 SDValue VecBitcast = DAG.getNode(ISD::BITCAST, DL, VecI16VT, V);
13829 // Low will be bitcasted right away, so do not bother bitcasting back to its
13831 Low = DAG.getNode(X86ISD::BLENDI, DL, VecI16VT, VecBitcast,
13832 VecCstLowBitcast, DAG.getConstant(0xaa, MVT::i32));
13833 // uint4 hi = _mm_blend_epi16( _mm_srli_epi32(v,16),
13834 // (uint4) 0x53000000, 0xaa);
13835 SDValue VecCstHighBitcast =
13836 DAG.getNode(ISD::BITCAST, DL, VecI16VT, VecCstHigh);
13837 SDValue VecShiftBitcast =
13838 DAG.getNode(ISD::BITCAST, DL, VecI16VT, HighShift);
13839 // High will be bitcasted right away, so do not bother bitcasting back to
13840 // its original type.
13841 High = DAG.getNode(X86ISD::BLENDI, DL, VecI16VT, VecShiftBitcast,
13842 VecCstHighBitcast, DAG.getConstant(0xaa, MVT::i32));
13844 SDValue CstMask = DAG.getConstant(0xffff, MVT::i32);
13845 SDValue VecCstMask = DAG.getNode(ISD::BUILD_VECTOR, DL, VecIntVT, CstMask,
13846 CstMask, CstMask, CstMask);
13847 // uint4 lo = (v & (uint4) 0xffff) | (uint4) 0x4b000000;
13848 SDValue LowAnd = DAG.getNode(ISD::AND, DL, VecIntVT, V, VecCstMask);
13849 Low = DAG.getNode(ISD::OR, DL, VecIntVT, LowAnd, VecCstLow);
13851 // uint4 hi = (v >> 16) | (uint4) 0x53000000;
13852 High = DAG.getNode(ISD::OR, DL, VecIntVT, HighShift, VecCstHigh);
13855 // Create the vector constant for -(0x1.0p39f + 0x1.0p23f).
13856 SDValue CstFAdd = DAG.getConstantFP(
13857 APFloat(APFloat::IEEEsingle, APInt(32, 0xD3000080)), MVT::f32);
13858 SDValue CstFAddArray[] = {CstFAdd, CstFAdd, CstFAdd, CstFAdd,
13859 CstFAdd, CstFAdd, CstFAdd, CstFAdd};
13860 SDValue VecCstFAdd = DAG.getNode(ISD::BUILD_VECTOR, DL, VecFloatVT,
13861 makeArrayRef(&CstFAddArray[0], NumElts));
13863 // float4 fhi = (float4) hi - (0x1.0p39f + 0x1.0p23f);
13864 SDValue HighBitcast = DAG.getNode(ISD::BITCAST, DL, VecFloatVT, High);
13866 DAG.getNode(ISD::FADD, DL, VecFloatVT, HighBitcast, VecCstFAdd);
13867 // return (float4) lo + fhi;
13868 SDValue LowBitcast = DAG.getNode(ISD::BITCAST, DL, VecFloatVT, Low);
13869 return DAG.getNode(ISD::FADD, DL, VecFloatVT, LowBitcast, FHigh);
13872 SDValue X86TargetLowering::lowerUINT_TO_FP_vec(SDValue Op,
13873 SelectionDAG &DAG) const {
13874 SDValue N0 = Op.getOperand(0);
13875 MVT SVT = N0.getSimpleValueType();
13878 switch (SVT.SimpleTy) {
13880 llvm_unreachable("Custom UINT_TO_FP is not supported!");
13885 MVT NVT = MVT::getVectorVT(MVT::i32, SVT.getVectorNumElements());
13886 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(),
13887 DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, N0));
13891 return lowerUINT_TO_FP_vXi32(Op, DAG, *Subtarget);
13893 llvm_unreachable(nullptr);
13896 SDValue X86TargetLowering::LowerUINT_TO_FP(SDValue Op,
13897 SelectionDAG &DAG) const {
13898 SDValue N0 = Op.getOperand(0);
13901 if (Op.getValueType().isVector())
13902 return lowerUINT_TO_FP_vec(Op, DAG);
13904 // Since UINT_TO_FP is legal (it's marked custom), dag combiner won't
13905 // optimize it to a SINT_TO_FP when the sign bit is known zero. Perform
13906 // the optimization here.
13907 if (DAG.SignBitIsZero(N0))
13908 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(), N0);
13910 MVT SrcVT = N0.getSimpleValueType();
13911 MVT DstVT = Op.getSimpleValueType();
13912 if (SrcVT == MVT::i64 && DstVT == MVT::f64 && X86ScalarSSEf64)
13913 return LowerUINT_TO_FP_i64(Op, DAG);
13914 if (SrcVT == MVT::i32 && X86ScalarSSEf64)
13915 return LowerUINT_TO_FP_i32(Op, DAG);
13916 if (Subtarget->is64Bit() && SrcVT == MVT::i64 && DstVT == MVT::f32)
13919 // Make a 64-bit buffer, and use it to build an FILD.
13920 SDValue StackSlot = DAG.CreateStackTemporary(MVT::i64);
13921 if (SrcVT == MVT::i32) {
13922 SDValue WordOff = DAG.getConstant(4, getPointerTy());
13923 SDValue OffsetSlot = DAG.getNode(ISD::ADD, dl,
13924 getPointerTy(), StackSlot, WordOff);
13925 SDValue Store1 = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
13926 StackSlot, MachinePointerInfo(),
13928 SDValue Store2 = DAG.getStore(Store1, dl, DAG.getConstant(0, MVT::i32),
13929 OffsetSlot, MachinePointerInfo(),
13931 SDValue Fild = BuildFILD(Op, MVT::i64, Store2, StackSlot, DAG);
13935 assert(SrcVT == MVT::i64 && "Unexpected type in UINT_TO_FP");
13936 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
13937 StackSlot, MachinePointerInfo(),
13939 // For i64 source, we need to add the appropriate power of 2 if the input
13940 // was negative. This is the same as the optimization in
13941 // DAGTypeLegalizer::ExpandIntOp_UNIT_TO_FP, and for it to be safe here,
13942 // we must be careful to do the computation in x87 extended precision, not
13943 // in SSE. (The generic code can't know it's OK to do this, or how to.)
13944 int SSFI = cast<FrameIndexSDNode>(StackSlot)->getIndex();
13945 MachineMemOperand *MMO =
13946 DAG.getMachineFunction()
13947 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
13948 MachineMemOperand::MOLoad, 8, 8);
13950 SDVTList Tys = DAG.getVTList(MVT::f80, MVT::Other);
13951 SDValue Ops[] = { Store, StackSlot, DAG.getValueType(MVT::i64) };
13952 SDValue Fild = DAG.getMemIntrinsicNode(X86ISD::FILD, dl, Tys, Ops,
13955 APInt FF(32, 0x5F800000ULL);
13957 // Check whether the sign bit is set.
13958 SDValue SignSet = DAG.getSetCC(dl,
13959 getSetCCResultType(*DAG.getContext(), MVT::i64),
13960 Op.getOperand(0), DAG.getConstant(0, MVT::i64),
13963 // Build a 64 bit pair (0, FF) in the constant pool, with FF in the lo bits.
13964 SDValue FudgePtr = DAG.getConstantPool(
13965 ConstantInt::get(*DAG.getContext(), FF.zext(64)),
13968 // Get a pointer to FF if the sign bit was set, or to 0 otherwise.
13969 SDValue Zero = DAG.getIntPtrConstant(0);
13970 SDValue Four = DAG.getIntPtrConstant(4);
13971 SDValue Offset = DAG.getNode(ISD::SELECT, dl, Zero.getValueType(), SignSet,
13973 FudgePtr = DAG.getNode(ISD::ADD, dl, getPointerTy(), FudgePtr, Offset);
13975 // Load the value out, extending it from f32 to f80.
13976 // FIXME: Avoid the extend by constructing the right constant pool?
13977 SDValue Fudge = DAG.getExtLoad(ISD::EXTLOAD, dl, MVT::f80, DAG.getEntryNode(),
13978 FudgePtr, MachinePointerInfo::getConstantPool(),
13979 MVT::f32, false, false, false, 4);
13980 // Extend everything to 80 bits to force it to be done on x87.
13981 SDValue Add = DAG.getNode(ISD::FADD, dl, MVT::f80, Fild, Fudge);
13982 return DAG.getNode(ISD::FP_ROUND, dl, DstVT, Add, DAG.getIntPtrConstant(0));
13985 std::pair<SDValue,SDValue>
13986 X86TargetLowering:: FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG,
13987 bool IsSigned, bool IsReplace) const {
13990 EVT DstTy = Op.getValueType();
13992 if (!IsSigned && !isIntegerTypeFTOL(DstTy)) {
13993 assert(DstTy == MVT::i32 && "Unexpected FP_TO_UINT");
13997 assert(DstTy.getSimpleVT() <= MVT::i64 &&
13998 DstTy.getSimpleVT() >= MVT::i16 &&
13999 "Unknown FP_TO_INT to lower!");
14001 // These are really Legal.
14002 if (DstTy == MVT::i32 &&
14003 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
14004 return std::make_pair(SDValue(), SDValue());
14005 if (Subtarget->is64Bit() &&
14006 DstTy == MVT::i64 &&
14007 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
14008 return std::make_pair(SDValue(), SDValue());
14010 // We lower FP->int64 either into FISTP64 followed by a load from a temporary
14011 // stack slot, or into the FTOL runtime function.
14012 MachineFunction &MF = DAG.getMachineFunction();
14013 unsigned MemSize = DstTy.getSizeInBits()/8;
14014 int SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
14015 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
14018 if (!IsSigned && isIntegerTypeFTOL(DstTy))
14019 Opc = X86ISD::WIN_FTOL;
14021 switch (DstTy.getSimpleVT().SimpleTy) {
14022 default: llvm_unreachable("Invalid FP_TO_SINT to lower!");
14023 case MVT::i16: Opc = X86ISD::FP_TO_INT16_IN_MEM; break;
14024 case MVT::i32: Opc = X86ISD::FP_TO_INT32_IN_MEM; break;
14025 case MVT::i64: Opc = X86ISD::FP_TO_INT64_IN_MEM; break;
14028 SDValue Chain = DAG.getEntryNode();
14029 SDValue Value = Op.getOperand(0);
14030 EVT TheVT = Op.getOperand(0).getValueType();
14031 // FIXME This causes a redundant load/store if the SSE-class value is already
14032 // in memory, such as if it is on the callstack.
14033 if (isScalarFPTypeInSSEReg(TheVT)) {
14034 assert(DstTy == MVT::i64 && "Invalid FP_TO_SINT to lower!");
14035 Chain = DAG.getStore(Chain, DL, Value, StackSlot,
14036 MachinePointerInfo::getFixedStack(SSFI),
14038 SDVTList Tys = DAG.getVTList(Op.getOperand(0).getValueType(), MVT::Other);
14040 Chain, StackSlot, DAG.getValueType(TheVT)
14043 MachineMemOperand *MMO =
14044 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
14045 MachineMemOperand::MOLoad, MemSize, MemSize);
14046 Value = DAG.getMemIntrinsicNode(X86ISD::FLD, DL, Tys, Ops, DstTy, MMO);
14047 Chain = Value.getValue(1);
14048 SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
14049 StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
14052 MachineMemOperand *MMO =
14053 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
14054 MachineMemOperand::MOStore, MemSize, MemSize);
14056 if (Opc != X86ISD::WIN_FTOL) {
14057 // Build the FP_TO_INT*_IN_MEM
14058 SDValue Ops[] = { Chain, Value, StackSlot };
14059 SDValue FIST = DAG.getMemIntrinsicNode(Opc, DL, DAG.getVTList(MVT::Other),
14061 return std::make_pair(FIST, StackSlot);
14063 SDValue ftol = DAG.getNode(X86ISD::WIN_FTOL, DL,
14064 DAG.getVTList(MVT::Other, MVT::Glue),
14066 SDValue eax = DAG.getCopyFromReg(ftol, DL, X86::EAX,
14067 MVT::i32, ftol.getValue(1));
14068 SDValue edx = DAG.getCopyFromReg(eax.getValue(1), DL, X86::EDX,
14069 MVT::i32, eax.getValue(2));
14070 SDValue Ops[] = { eax, edx };
14071 SDValue pair = IsReplace
14072 ? DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops)
14073 : DAG.getMergeValues(Ops, DL);
14074 return std::make_pair(pair, SDValue());
14078 static SDValue LowerAVXExtend(SDValue Op, SelectionDAG &DAG,
14079 const X86Subtarget *Subtarget) {
14080 MVT VT = Op->getSimpleValueType(0);
14081 SDValue In = Op->getOperand(0);
14082 MVT InVT = In.getSimpleValueType();
14085 // Optimize vectors in AVX mode:
14088 // Use vpunpcklwd for 4 lower elements v8i16 -> v4i32.
14089 // Use vpunpckhwd for 4 upper elements v8i16 -> v4i32.
14090 // Concat upper and lower parts.
14093 // Use vpunpckldq for 4 lower elements v4i32 -> v2i64.
14094 // Use vpunpckhdq for 4 upper elements v4i32 -> v2i64.
14095 // Concat upper and lower parts.
14098 if (((VT != MVT::v16i16) || (InVT != MVT::v16i8)) &&
14099 ((VT != MVT::v8i32) || (InVT != MVT::v8i16)) &&
14100 ((VT != MVT::v4i64) || (InVT != MVT::v4i32)))
14103 if (Subtarget->hasInt256())
14104 return DAG.getNode(X86ISD::VZEXT, dl, VT, In);
14106 SDValue ZeroVec = getZeroVector(InVT, Subtarget, DAG, dl);
14107 SDValue Undef = DAG.getUNDEF(InVT);
14108 bool NeedZero = Op.getOpcode() == ISD::ZERO_EXTEND;
14109 SDValue OpLo = getUnpackl(DAG, dl, InVT, In, NeedZero ? ZeroVec : Undef);
14110 SDValue OpHi = getUnpackh(DAG, dl, InVT, In, NeedZero ? ZeroVec : Undef);
14112 MVT HVT = MVT::getVectorVT(VT.getVectorElementType(),
14113 VT.getVectorNumElements()/2);
14115 OpLo = DAG.getNode(ISD::BITCAST, dl, HVT, OpLo);
14116 OpHi = DAG.getNode(ISD::BITCAST, dl, HVT, OpHi);
14118 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi);
14121 static SDValue LowerZERO_EXTEND_AVX512(SDValue Op,
14122 SelectionDAG &DAG) {
14123 MVT VT = Op->getSimpleValueType(0);
14124 SDValue In = Op->getOperand(0);
14125 MVT InVT = In.getSimpleValueType();
14127 unsigned int NumElts = VT.getVectorNumElements();
14128 if (NumElts != 8 && NumElts != 16)
14131 if (VT.is512BitVector() && InVT.getVectorElementType() != MVT::i1)
14132 return DAG.getNode(X86ISD::VZEXT, DL, VT, In);
14134 EVT ExtVT = (NumElts == 8)? MVT::v8i64 : MVT::v16i32;
14135 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
14136 // Now we have only mask extension
14137 assert(InVT.getVectorElementType() == MVT::i1);
14138 SDValue Cst = DAG.getTargetConstant(1, ExtVT.getScalarType());
14139 const Constant *C = (dyn_cast<ConstantSDNode>(Cst))->getConstantIntValue();
14140 SDValue CP = DAG.getConstantPool(C, TLI.getPointerTy());
14141 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
14142 SDValue Ld = DAG.getLoad(Cst.getValueType(), DL, DAG.getEntryNode(), CP,
14143 MachinePointerInfo::getConstantPool(),
14144 false, false, false, Alignment);
14146 SDValue Brcst = DAG.getNode(X86ISD::VBROADCASTM, DL, ExtVT, In, Ld);
14147 if (VT.is512BitVector())
14149 return DAG.getNode(X86ISD::VTRUNC, DL, VT, Brcst);
14152 static SDValue LowerANY_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
14153 SelectionDAG &DAG) {
14154 if (Subtarget->hasFp256()) {
14155 SDValue Res = LowerAVXExtend(Op, DAG, Subtarget);
14163 static SDValue LowerZERO_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
14164 SelectionDAG &DAG) {
14166 MVT VT = Op.getSimpleValueType();
14167 SDValue In = Op.getOperand(0);
14168 MVT SVT = In.getSimpleValueType();
14170 if (VT.is512BitVector() || SVT.getVectorElementType() == MVT::i1)
14171 return LowerZERO_EXTEND_AVX512(Op, DAG);
14173 if (Subtarget->hasFp256()) {
14174 SDValue Res = LowerAVXExtend(Op, DAG, Subtarget);
14179 assert(!VT.is256BitVector() || !SVT.is128BitVector() ||
14180 VT.getVectorNumElements() != SVT.getVectorNumElements());
14184 SDValue X86TargetLowering::LowerTRUNCATE(SDValue Op, SelectionDAG &DAG) const {
14186 MVT VT = Op.getSimpleValueType();
14187 SDValue In = Op.getOperand(0);
14188 MVT InVT = In.getSimpleValueType();
14190 if (VT == MVT::i1) {
14191 assert((InVT.isInteger() && (InVT.getSizeInBits() <= 64)) &&
14192 "Invalid scalar TRUNCATE operation");
14193 if (InVT.getSizeInBits() >= 32)
14195 In = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i32, In);
14196 return DAG.getNode(ISD::TRUNCATE, DL, VT, In);
14198 assert(VT.getVectorNumElements() == InVT.getVectorNumElements() &&
14199 "Invalid TRUNCATE operation");
14201 if (InVT.is512BitVector() || VT.getVectorElementType() == MVT::i1) {
14202 if (VT.getVectorElementType().getSizeInBits() >=8)
14203 return DAG.getNode(X86ISD::VTRUNC, DL, VT, In);
14205 assert(VT.getVectorElementType() == MVT::i1 && "Unexpected vector type");
14206 unsigned NumElts = InVT.getVectorNumElements();
14207 assert ((NumElts == 8 || NumElts == 16) && "Unexpected vector type");
14208 if (InVT.getSizeInBits() < 512) {
14209 MVT ExtVT = (NumElts == 16)? MVT::v16i32 : MVT::v8i64;
14210 In = DAG.getNode(ISD::SIGN_EXTEND, DL, ExtVT, In);
14214 SDValue Cst = DAG.getTargetConstant(1, InVT.getVectorElementType());
14215 const Constant *C = (dyn_cast<ConstantSDNode>(Cst))->getConstantIntValue();
14216 SDValue CP = DAG.getConstantPool(C, getPointerTy());
14217 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
14218 SDValue Ld = DAG.getLoad(Cst.getValueType(), DL, DAG.getEntryNode(), CP,
14219 MachinePointerInfo::getConstantPool(),
14220 false, false, false, Alignment);
14221 SDValue OneV = DAG.getNode(X86ISD::VBROADCAST, DL, InVT, Ld);
14222 SDValue And = DAG.getNode(ISD::AND, DL, InVT, OneV, In);
14223 return DAG.getNode(X86ISD::TESTM, DL, VT, And, And);
14226 if ((VT == MVT::v4i32) && (InVT == MVT::v4i64)) {
14227 // On AVX2, v4i64 -> v4i32 becomes VPERMD.
14228 if (Subtarget->hasInt256()) {
14229 static const int ShufMask[] = {0, 2, 4, 6, -1, -1, -1, -1};
14230 In = DAG.getNode(ISD::BITCAST, DL, MVT::v8i32, In);
14231 In = DAG.getVectorShuffle(MVT::v8i32, DL, In, DAG.getUNDEF(MVT::v8i32),
14233 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, In,
14234 DAG.getIntPtrConstant(0));
14237 SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
14238 DAG.getIntPtrConstant(0));
14239 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
14240 DAG.getIntPtrConstant(2));
14241 OpLo = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpLo);
14242 OpHi = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpHi);
14243 static const int ShufMask[] = {0, 2, 4, 6};
14244 return DAG.getVectorShuffle(VT, DL, OpLo, OpHi, ShufMask);
14247 if ((VT == MVT::v8i16) && (InVT == MVT::v8i32)) {
14248 // On AVX2, v8i32 -> v8i16 becomed PSHUFB.
14249 if (Subtarget->hasInt256()) {
14250 In = DAG.getNode(ISD::BITCAST, DL, MVT::v32i8, In);
14252 SmallVector<SDValue,32> pshufbMask;
14253 for (unsigned i = 0; i < 2; ++i) {
14254 pshufbMask.push_back(DAG.getConstant(0x0, MVT::i8));
14255 pshufbMask.push_back(DAG.getConstant(0x1, MVT::i8));
14256 pshufbMask.push_back(DAG.getConstant(0x4, MVT::i8));
14257 pshufbMask.push_back(DAG.getConstant(0x5, MVT::i8));
14258 pshufbMask.push_back(DAG.getConstant(0x8, MVT::i8));
14259 pshufbMask.push_back(DAG.getConstant(0x9, MVT::i8));
14260 pshufbMask.push_back(DAG.getConstant(0xc, MVT::i8));
14261 pshufbMask.push_back(DAG.getConstant(0xd, MVT::i8));
14262 for (unsigned j = 0; j < 8; ++j)
14263 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
14265 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v32i8, pshufbMask);
14266 In = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v32i8, In, BV);
14267 In = DAG.getNode(ISD::BITCAST, DL, MVT::v4i64, In);
14269 static const int ShufMask[] = {0, 2, -1, -1};
14270 In = DAG.getVectorShuffle(MVT::v4i64, DL, In, DAG.getUNDEF(MVT::v4i64),
14272 In = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
14273 DAG.getIntPtrConstant(0));
14274 return DAG.getNode(ISD::BITCAST, DL, VT, In);
14277 SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v4i32, In,
14278 DAG.getIntPtrConstant(0));
14280 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v4i32, In,
14281 DAG.getIntPtrConstant(4));
14283 OpLo = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, OpLo);
14284 OpHi = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, OpHi);
14286 // The PSHUFB mask:
14287 static const int ShufMask1[] = {0, 1, 4, 5, 8, 9, 12, 13,
14288 -1, -1, -1, -1, -1, -1, -1, -1};
14290 SDValue Undef = DAG.getUNDEF(MVT::v16i8);
14291 OpLo = DAG.getVectorShuffle(MVT::v16i8, DL, OpLo, Undef, ShufMask1);
14292 OpHi = DAG.getVectorShuffle(MVT::v16i8, DL, OpHi, Undef, ShufMask1);
14294 OpLo = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpLo);
14295 OpHi = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpHi);
14297 // The MOVLHPS Mask:
14298 static const int ShufMask2[] = {0, 1, 4, 5};
14299 SDValue res = DAG.getVectorShuffle(MVT::v4i32, DL, OpLo, OpHi, ShufMask2);
14300 return DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, res);
14303 // Handle truncation of V256 to V128 using shuffles.
14304 if (!VT.is128BitVector() || !InVT.is256BitVector())
14307 assert(Subtarget->hasFp256() && "256-bit vector without AVX!");
14309 unsigned NumElems = VT.getVectorNumElements();
14310 MVT NVT = MVT::getVectorVT(VT.getVectorElementType(), NumElems * 2);
14312 SmallVector<int, 16> MaskVec(NumElems * 2, -1);
14313 // Prepare truncation shuffle mask
14314 for (unsigned i = 0; i != NumElems; ++i)
14315 MaskVec[i] = i * 2;
14316 SDValue V = DAG.getVectorShuffle(NVT, DL,
14317 DAG.getNode(ISD::BITCAST, DL, NVT, In),
14318 DAG.getUNDEF(NVT), &MaskVec[0]);
14319 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, V,
14320 DAG.getIntPtrConstant(0));
14323 SDValue X86TargetLowering::LowerFP_TO_SINT(SDValue Op,
14324 SelectionDAG &DAG) const {
14325 assert(!Op.getSimpleValueType().isVector());
14327 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG,
14328 /*IsSigned=*/ true, /*IsReplace=*/ false);
14329 SDValue FIST = Vals.first, StackSlot = Vals.second;
14330 // If FP_TO_INTHelper failed, the node is actually supposed to be Legal.
14331 if (!FIST.getNode()) return Op;
14333 if (StackSlot.getNode())
14334 // Load the result.
14335 return DAG.getLoad(Op.getValueType(), SDLoc(Op),
14336 FIST, StackSlot, MachinePointerInfo(),
14337 false, false, false, 0);
14339 // The node is the result.
14343 SDValue X86TargetLowering::LowerFP_TO_UINT(SDValue Op,
14344 SelectionDAG &DAG) const {
14345 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG,
14346 /*IsSigned=*/ false, /*IsReplace=*/ false);
14347 SDValue FIST = Vals.first, StackSlot = Vals.second;
14348 assert(FIST.getNode() && "Unexpected failure");
14350 if (StackSlot.getNode())
14351 // Load the result.
14352 return DAG.getLoad(Op.getValueType(), SDLoc(Op),
14353 FIST, StackSlot, MachinePointerInfo(),
14354 false, false, false, 0);
14356 // The node is the result.
14360 static SDValue LowerFP_EXTEND(SDValue Op, SelectionDAG &DAG) {
14362 MVT VT = Op.getSimpleValueType();
14363 SDValue In = Op.getOperand(0);
14364 MVT SVT = In.getSimpleValueType();
14366 assert(SVT == MVT::v2f32 && "Only customize MVT::v2f32 type legalization!");
14368 return DAG.getNode(X86ISD::VFPEXT, DL, VT,
14369 DAG.getNode(ISD::CONCAT_VECTORS, DL, MVT::v4f32,
14370 In, DAG.getUNDEF(SVT)));
14373 /// The only differences between FABS and FNEG are the mask and the logic op.
14374 /// FNEG also has a folding opportunity for FNEG(FABS(x)).
14375 static SDValue LowerFABSorFNEG(SDValue Op, SelectionDAG &DAG) {
14376 assert((Op.getOpcode() == ISD::FABS || Op.getOpcode() == ISD::FNEG) &&
14377 "Wrong opcode for lowering FABS or FNEG.");
14379 bool IsFABS = (Op.getOpcode() == ISD::FABS);
14381 // If this is a FABS and it has an FNEG user, bail out to fold the combination
14382 // into an FNABS. We'll lower the FABS after that if it is still in use.
14384 for (SDNode *User : Op->uses())
14385 if (User->getOpcode() == ISD::FNEG)
14388 SDValue Op0 = Op.getOperand(0);
14389 bool IsFNABS = !IsFABS && (Op0.getOpcode() == ISD::FABS);
14392 MVT VT = Op.getSimpleValueType();
14393 // Assume scalar op for initialization; update for vector if needed.
14394 // Note that there are no scalar bitwise logical SSE/AVX instructions, so we
14395 // generate a 16-byte vector constant and logic op even for the scalar case.
14396 // Using a 16-byte mask allows folding the load of the mask with
14397 // the logic op, so it can save (~4 bytes) on code size.
14399 unsigned NumElts = VT == MVT::f64 ? 2 : 4;
14400 // FIXME: Use function attribute "OptimizeForSize" and/or CodeGenOpt::Level to
14401 // decide if we should generate a 16-byte constant mask when we only need 4 or
14402 // 8 bytes for the scalar case.
14403 if (VT.isVector()) {
14404 EltVT = VT.getVectorElementType();
14405 NumElts = VT.getVectorNumElements();
14408 unsigned EltBits = EltVT.getSizeInBits();
14409 LLVMContext *Context = DAG.getContext();
14410 // For FABS, mask is 0x7f...; for FNEG, mask is 0x80...
14412 IsFABS ? APInt::getSignedMaxValue(EltBits) : APInt::getSignBit(EltBits);
14413 Constant *C = ConstantInt::get(*Context, MaskElt);
14414 C = ConstantVector::getSplat(NumElts, C);
14415 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
14416 SDValue CPIdx = DAG.getConstantPool(C, TLI.getPointerTy());
14417 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
14418 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
14419 MachinePointerInfo::getConstantPool(),
14420 false, false, false, Alignment);
14422 if (VT.isVector()) {
14423 // For a vector, cast operands to a vector type, perform the logic op,
14424 // and cast the result back to the original value type.
14425 MVT VecVT = MVT::getVectorVT(MVT::i64, VT.getSizeInBits() / 64);
14426 SDValue MaskCasted = DAG.getNode(ISD::BITCAST, dl, VecVT, Mask);
14427 SDValue Operand = IsFNABS ?
14428 DAG.getNode(ISD::BITCAST, dl, VecVT, Op0.getOperand(0)) :
14429 DAG.getNode(ISD::BITCAST, dl, VecVT, Op0);
14430 unsigned BitOp = IsFABS ? ISD::AND : IsFNABS ? ISD::OR : ISD::XOR;
14431 return DAG.getNode(ISD::BITCAST, dl, VT,
14432 DAG.getNode(BitOp, dl, VecVT, Operand, MaskCasted));
14435 // If not vector, then scalar.
14436 unsigned BitOp = IsFABS ? X86ISD::FAND : IsFNABS ? X86ISD::FOR : X86ISD::FXOR;
14437 SDValue Operand = IsFNABS ? Op0.getOperand(0) : Op0;
14438 return DAG.getNode(BitOp, dl, VT, Operand, Mask);
14441 static SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) {
14442 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
14443 LLVMContext *Context = DAG.getContext();
14444 SDValue Op0 = Op.getOperand(0);
14445 SDValue Op1 = Op.getOperand(1);
14447 MVT VT = Op.getSimpleValueType();
14448 MVT SrcVT = Op1.getSimpleValueType();
14450 // If second operand is smaller, extend it first.
14451 if (SrcVT.bitsLT(VT)) {
14452 Op1 = DAG.getNode(ISD::FP_EXTEND, dl, VT, Op1);
14455 // And if it is bigger, shrink it first.
14456 if (SrcVT.bitsGT(VT)) {
14457 Op1 = DAG.getNode(ISD::FP_ROUND, dl, VT, Op1, DAG.getIntPtrConstant(1));
14461 // At this point the operands and the result should have the same
14462 // type, and that won't be f80 since that is not custom lowered.
14464 // First get the sign bit of second operand.
14465 SmallVector<Constant*,4> CV;
14466 if (SrcVT == MVT::f64) {
14467 const fltSemantics &Sem = APFloat::IEEEdouble;
14468 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(64, 1ULL << 63))));
14469 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(64, 0))));
14471 const fltSemantics &Sem = APFloat::IEEEsingle;
14472 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 1U << 31))));
14473 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
14474 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
14475 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
14477 Constant *C = ConstantVector::get(CV);
14478 SDValue CPIdx = DAG.getConstantPool(C, TLI.getPointerTy(), 16);
14479 SDValue Mask1 = DAG.getLoad(SrcVT, dl, DAG.getEntryNode(), CPIdx,
14480 MachinePointerInfo::getConstantPool(),
14481 false, false, false, 16);
14482 SDValue SignBit = DAG.getNode(X86ISD::FAND, dl, SrcVT, Op1, Mask1);
14484 // Shift sign bit right or left if the two operands have different types.
14485 if (SrcVT.bitsGT(VT)) {
14486 // Op0 is MVT::f32, Op1 is MVT::f64.
14487 SignBit = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f64, SignBit);
14488 SignBit = DAG.getNode(X86ISD::FSRL, dl, MVT::v2f64, SignBit,
14489 DAG.getConstant(32, MVT::i32));
14490 SignBit = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, SignBit);
14491 SignBit = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f32, SignBit,
14492 DAG.getIntPtrConstant(0));
14495 // Clear first operand sign bit.
14497 if (VT == MVT::f64) {
14498 const fltSemantics &Sem = APFloat::IEEEdouble;
14499 CV.push_back(ConstantFP::get(*Context, APFloat(Sem,
14500 APInt(64, ~(1ULL << 63)))));
14501 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(64, 0))));
14503 const fltSemantics &Sem = APFloat::IEEEsingle;
14504 CV.push_back(ConstantFP::get(*Context, APFloat(Sem,
14505 APInt(32, ~(1U << 31)))));
14506 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
14507 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
14508 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
14510 C = ConstantVector::get(CV);
14511 CPIdx = DAG.getConstantPool(C, TLI.getPointerTy(), 16);
14512 SDValue Mask2 = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
14513 MachinePointerInfo::getConstantPool(),
14514 false, false, false, 16);
14515 SDValue Val = DAG.getNode(X86ISD::FAND, dl, VT, Op0, Mask2);
14517 // Or the value with the sign bit.
14518 return DAG.getNode(X86ISD::FOR, dl, VT, Val, SignBit);
14521 static SDValue LowerFGETSIGN(SDValue Op, SelectionDAG &DAG) {
14522 SDValue N0 = Op.getOperand(0);
14524 MVT VT = Op.getSimpleValueType();
14526 // Lower ISD::FGETSIGN to (AND (X86ISD::FGETSIGNx86 ...) 1).
14527 SDValue xFGETSIGN = DAG.getNode(X86ISD::FGETSIGNx86, dl, VT, N0,
14528 DAG.getConstant(1, VT));
14529 return DAG.getNode(ISD::AND, dl, VT, xFGETSIGN, DAG.getConstant(1, VT));
14532 // Check whether an OR'd tree is PTEST-able.
14533 static SDValue LowerVectorAllZeroTest(SDValue Op, const X86Subtarget *Subtarget,
14534 SelectionDAG &DAG) {
14535 assert(Op.getOpcode() == ISD::OR && "Only check OR'd tree.");
14537 if (!Subtarget->hasSSE41())
14540 if (!Op->hasOneUse())
14543 SDNode *N = Op.getNode();
14546 SmallVector<SDValue, 8> Opnds;
14547 DenseMap<SDValue, unsigned> VecInMap;
14548 SmallVector<SDValue, 8> VecIns;
14549 EVT VT = MVT::Other;
14551 // Recognize a special case where a vector is casted into wide integer to
14553 Opnds.push_back(N->getOperand(0));
14554 Opnds.push_back(N->getOperand(1));
14556 for (unsigned Slot = 0, e = Opnds.size(); Slot < e; ++Slot) {
14557 SmallVectorImpl<SDValue>::const_iterator I = Opnds.begin() + Slot;
14558 // BFS traverse all OR'd operands.
14559 if (I->getOpcode() == ISD::OR) {
14560 Opnds.push_back(I->getOperand(0));
14561 Opnds.push_back(I->getOperand(1));
14562 // Re-evaluate the number of nodes to be traversed.
14563 e += 2; // 2 more nodes (LHS and RHS) are pushed.
14567 // Quit if a non-EXTRACT_VECTOR_ELT
14568 if (I->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
14571 // Quit if without a constant index.
14572 SDValue Idx = I->getOperand(1);
14573 if (!isa<ConstantSDNode>(Idx))
14576 SDValue ExtractedFromVec = I->getOperand(0);
14577 DenseMap<SDValue, unsigned>::iterator M = VecInMap.find(ExtractedFromVec);
14578 if (M == VecInMap.end()) {
14579 VT = ExtractedFromVec.getValueType();
14580 // Quit if not 128/256-bit vector.
14581 if (!VT.is128BitVector() && !VT.is256BitVector())
14583 // Quit if not the same type.
14584 if (VecInMap.begin() != VecInMap.end() &&
14585 VT != VecInMap.begin()->first.getValueType())
14587 M = VecInMap.insert(std::make_pair(ExtractedFromVec, 0)).first;
14588 VecIns.push_back(ExtractedFromVec);
14590 M->second |= 1U << cast<ConstantSDNode>(Idx)->getZExtValue();
14593 assert((VT.is128BitVector() || VT.is256BitVector()) &&
14594 "Not extracted from 128-/256-bit vector.");
14596 unsigned FullMask = (1U << VT.getVectorNumElements()) - 1U;
14598 for (DenseMap<SDValue, unsigned>::const_iterator
14599 I = VecInMap.begin(), E = VecInMap.end(); I != E; ++I) {
14600 // Quit if not all elements are used.
14601 if (I->second != FullMask)
14605 EVT TestVT = VT.is128BitVector() ? MVT::v2i64 : MVT::v4i64;
14607 // Cast all vectors into TestVT for PTEST.
14608 for (unsigned i = 0, e = VecIns.size(); i < e; ++i)
14609 VecIns[i] = DAG.getNode(ISD::BITCAST, DL, TestVT, VecIns[i]);
14611 // If more than one full vectors are evaluated, OR them first before PTEST.
14612 for (unsigned Slot = 0, e = VecIns.size(); e - Slot > 1; Slot += 2, e += 1) {
14613 // Each iteration will OR 2 nodes and append the result until there is only
14614 // 1 node left, i.e. the final OR'd value of all vectors.
14615 SDValue LHS = VecIns[Slot];
14616 SDValue RHS = VecIns[Slot + 1];
14617 VecIns.push_back(DAG.getNode(ISD::OR, DL, TestVT, LHS, RHS));
14620 return DAG.getNode(X86ISD::PTEST, DL, MVT::i32,
14621 VecIns.back(), VecIns.back());
14624 /// \brief return true if \c Op has a use that doesn't just read flags.
14625 static bool hasNonFlagsUse(SDValue Op) {
14626 for (SDNode::use_iterator UI = Op->use_begin(), UE = Op->use_end(); UI != UE;
14628 SDNode *User = *UI;
14629 unsigned UOpNo = UI.getOperandNo();
14630 if (User->getOpcode() == ISD::TRUNCATE && User->hasOneUse()) {
14631 // Look pass truncate.
14632 UOpNo = User->use_begin().getOperandNo();
14633 User = *User->use_begin();
14636 if (User->getOpcode() != ISD::BRCOND && User->getOpcode() != ISD::SETCC &&
14637 !(User->getOpcode() == ISD::SELECT && UOpNo == 0))
14643 /// Emit nodes that will be selected as "test Op0,Op0", or something
14645 SDValue X86TargetLowering::EmitTest(SDValue Op, unsigned X86CC, SDLoc dl,
14646 SelectionDAG &DAG) const {
14647 if (Op.getValueType() == MVT::i1)
14648 // KORTEST instruction should be selected
14649 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
14650 DAG.getConstant(0, Op.getValueType()));
14652 // CF and OF aren't always set the way we want. Determine which
14653 // of these we need.
14654 bool NeedCF = false;
14655 bool NeedOF = false;
14658 case X86::COND_A: case X86::COND_AE:
14659 case X86::COND_B: case X86::COND_BE:
14662 case X86::COND_G: case X86::COND_GE:
14663 case X86::COND_L: case X86::COND_LE:
14664 case X86::COND_O: case X86::COND_NO: {
14665 // Check if we really need to set the
14666 // Overflow flag. If NoSignedWrap is present
14667 // that is not actually needed.
14668 switch (Op->getOpcode()) {
14673 const BinaryWithFlagsSDNode *BinNode =
14674 cast<BinaryWithFlagsSDNode>(Op.getNode());
14675 if (BinNode->hasNoSignedWrap())
14685 // See if we can use the EFLAGS value from the operand instead of
14686 // doing a separate TEST. TEST always sets OF and CF to 0, so unless
14687 // we prove that the arithmetic won't overflow, we can't use OF or CF.
14688 if (Op.getResNo() != 0 || NeedOF || NeedCF) {
14689 // Emit a CMP with 0, which is the TEST pattern.
14690 //if (Op.getValueType() == MVT::i1)
14691 // return DAG.getNode(X86ISD::CMP, dl, MVT::i1, Op,
14692 // DAG.getConstant(0, MVT::i1));
14693 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
14694 DAG.getConstant(0, Op.getValueType()));
14696 unsigned Opcode = 0;
14697 unsigned NumOperands = 0;
14699 // Truncate operations may prevent the merge of the SETCC instruction
14700 // and the arithmetic instruction before it. Attempt to truncate the operands
14701 // of the arithmetic instruction and use a reduced bit-width instruction.
14702 bool NeedTruncation = false;
14703 SDValue ArithOp = Op;
14704 if (Op->getOpcode() == ISD::TRUNCATE && Op->hasOneUse()) {
14705 SDValue Arith = Op->getOperand(0);
14706 // Both the trunc and the arithmetic op need to have one user each.
14707 if (Arith->hasOneUse())
14708 switch (Arith.getOpcode()) {
14715 NeedTruncation = true;
14721 // NOTICE: In the code below we use ArithOp to hold the arithmetic operation
14722 // which may be the result of a CAST. We use the variable 'Op', which is the
14723 // non-casted variable when we check for possible users.
14724 switch (ArithOp.getOpcode()) {
14726 // Due to an isel shortcoming, be conservative if this add is likely to be
14727 // selected as part of a load-modify-store instruction. When the root node
14728 // in a match is a store, isel doesn't know how to remap non-chain non-flag
14729 // uses of other nodes in the match, such as the ADD in this case. This
14730 // leads to the ADD being left around and reselected, with the result being
14731 // two adds in the output. Alas, even if none our users are stores, that
14732 // doesn't prove we're O.K. Ergo, if we have any parents that aren't
14733 // CopyToReg or SETCC, eschew INC/DEC. A better fix seems to require
14734 // climbing the DAG back to the root, and it doesn't seem to be worth the
14736 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
14737 UE = Op.getNode()->use_end(); UI != UE; ++UI)
14738 if (UI->getOpcode() != ISD::CopyToReg &&
14739 UI->getOpcode() != ISD::SETCC &&
14740 UI->getOpcode() != ISD::STORE)
14743 if (ConstantSDNode *C =
14744 dyn_cast<ConstantSDNode>(ArithOp.getNode()->getOperand(1))) {
14745 // An add of one will be selected as an INC.
14746 if (C->getAPIntValue() == 1 && !Subtarget->slowIncDec()) {
14747 Opcode = X86ISD::INC;
14752 // An add of negative one (subtract of one) will be selected as a DEC.
14753 if (C->getAPIntValue().isAllOnesValue() && !Subtarget->slowIncDec()) {
14754 Opcode = X86ISD::DEC;
14760 // Otherwise use a regular EFLAGS-setting add.
14761 Opcode = X86ISD::ADD;
14766 // If we have a constant logical shift that's only used in a comparison
14767 // against zero turn it into an equivalent AND. This allows turning it into
14768 // a TEST instruction later.
14769 if ((X86CC == X86::COND_E || X86CC == X86::COND_NE) && Op->hasOneUse() &&
14770 isa<ConstantSDNode>(Op->getOperand(1)) && !hasNonFlagsUse(Op)) {
14771 EVT VT = Op.getValueType();
14772 unsigned BitWidth = VT.getSizeInBits();
14773 unsigned ShAmt = Op->getConstantOperandVal(1);
14774 if (ShAmt >= BitWidth) // Avoid undefined shifts.
14776 APInt Mask = ArithOp.getOpcode() == ISD::SRL
14777 ? APInt::getHighBitsSet(BitWidth, BitWidth - ShAmt)
14778 : APInt::getLowBitsSet(BitWidth, BitWidth - ShAmt);
14779 if (!Mask.isSignedIntN(32)) // Avoid large immediates.
14781 SDValue New = DAG.getNode(ISD::AND, dl, VT, Op->getOperand(0),
14782 DAG.getConstant(Mask, VT));
14783 DAG.ReplaceAllUsesWith(Op, New);
14789 // If the primary and result isn't used, don't bother using X86ISD::AND,
14790 // because a TEST instruction will be better.
14791 if (!hasNonFlagsUse(Op))
14797 // Due to the ISEL shortcoming noted above, be conservative if this op is
14798 // likely to be selected as part of a load-modify-store instruction.
14799 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
14800 UE = Op.getNode()->use_end(); UI != UE; ++UI)
14801 if (UI->getOpcode() == ISD::STORE)
14804 // Otherwise use a regular EFLAGS-setting instruction.
14805 switch (ArithOp.getOpcode()) {
14806 default: llvm_unreachable("unexpected operator!");
14807 case ISD::SUB: Opcode = X86ISD::SUB; break;
14808 case ISD::XOR: Opcode = X86ISD::XOR; break;
14809 case ISD::AND: Opcode = X86ISD::AND; break;
14811 if (!NeedTruncation && (X86CC == X86::COND_E || X86CC == X86::COND_NE)) {
14812 SDValue EFLAGS = LowerVectorAllZeroTest(Op, Subtarget, DAG);
14813 if (EFLAGS.getNode())
14816 Opcode = X86ISD::OR;
14830 return SDValue(Op.getNode(), 1);
14836 // If we found that truncation is beneficial, perform the truncation and
14838 if (NeedTruncation) {
14839 EVT VT = Op.getValueType();
14840 SDValue WideVal = Op->getOperand(0);
14841 EVT WideVT = WideVal.getValueType();
14842 unsigned ConvertedOp = 0;
14843 // Use a target machine opcode to prevent further DAGCombine
14844 // optimizations that may separate the arithmetic operations
14845 // from the setcc node.
14846 switch (WideVal.getOpcode()) {
14848 case ISD::ADD: ConvertedOp = X86ISD::ADD; break;
14849 case ISD::SUB: ConvertedOp = X86ISD::SUB; break;
14850 case ISD::AND: ConvertedOp = X86ISD::AND; break;
14851 case ISD::OR: ConvertedOp = X86ISD::OR; break;
14852 case ISD::XOR: ConvertedOp = X86ISD::XOR; break;
14856 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
14857 if (TLI.isOperationLegal(WideVal.getOpcode(), WideVT)) {
14858 SDValue V0 = DAG.getNode(ISD::TRUNCATE, dl, VT, WideVal.getOperand(0));
14859 SDValue V1 = DAG.getNode(ISD::TRUNCATE, dl, VT, WideVal.getOperand(1));
14860 Op = DAG.getNode(ConvertedOp, dl, VT, V0, V1);
14866 // Emit a CMP with 0, which is the TEST pattern.
14867 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
14868 DAG.getConstant(0, Op.getValueType()));
14870 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
14871 SmallVector<SDValue, 4> Ops;
14872 for (unsigned i = 0; i != NumOperands; ++i)
14873 Ops.push_back(Op.getOperand(i));
14875 SDValue New = DAG.getNode(Opcode, dl, VTs, Ops);
14876 DAG.ReplaceAllUsesWith(Op, New);
14877 return SDValue(New.getNode(), 1);
14880 /// Emit nodes that will be selected as "cmp Op0,Op1", or something
14882 SDValue X86TargetLowering::EmitCmp(SDValue Op0, SDValue Op1, unsigned X86CC,
14883 SDLoc dl, SelectionDAG &DAG) const {
14884 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op1)) {
14885 if (C->getAPIntValue() == 0)
14886 return EmitTest(Op0, X86CC, dl, DAG);
14888 if (Op0.getValueType() == MVT::i1)
14889 llvm_unreachable("Unexpected comparison operation for MVT::i1 operands");
14892 if ((Op0.getValueType() == MVT::i8 || Op0.getValueType() == MVT::i16 ||
14893 Op0.getValueType() == MVT::i32 || Op0.getValueType() == MVT::i64)) {
14894 // Do the comparison at i32 if it's smaller, besides the Atom case.
14895 // This avoids subregister aliasing issues. Keep the smaller reference
14896 // if we're optimizing for size, however, as that'll allow better folding
14897 // of memory operations.
14898 if (Op0.getValueType() != MVT::i32 && Op0.getValueType() != MVT::i64 &&
14899 !DAG.getMachineFunction().getFunction()->getAttributes().hasAttribute(
14900 AttributeSet::FunctionIndex, Attribute::MinSize) &&
14901 !Subtarget->isAtom()) {
14902 unsigned ExtendOp =
14903 isX86CCUnsigned(X86CC) ? ISD::ZERO_EXTEND : ISD::SIGN_EXTEND;
14904 Op0 = DAG.getNode(ExtendOp, dl, MVT::i32, Op0);
14905 Op1 = DAG.getNode(ExtendOp, dl, MVT::i32, Op1);
14907 // Use SUB instead of CMP to enable CSE between SUB and CMP.
14908 SDVTList VTs = DAG.getVTList(Op0.getValueType(), MVT::i32);
14909 SDValue Sub = DAG.getNode(X86ISD::SUB, dl, VTs,
14911 return SDValue(Sub.getNode(), 1);
14913 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op0, Op1);
14916 /// Convert a comparison if required by the subtarget.
14917 SDValue X86TargetLowering::ConvertCmpIfNecessary(SDValue Cmp,
14918 SelectionDAG &DAG) const {
14919 // If the subtarget does not support the FUCOMI instruction, floating-point
14920 // comparisons have to be converted.
14921 if (Subtarget->hasCMov() ||
14922 Cmp.getOpcode() != X86ISD::CMP ||
14923 !Cmp.getOperand(0).getValueType().isFloatingPoint() ||
14924 !Cmp.getOperand(1).getValueType().isFloatingPoint())
14927 // The instruction selector will select an FUCOM instruction instead of
14928 // FUCOMI, which writes the comparison result to FPSW instead of EFLAGS. Hence
14929 // build an SDNode sequence that transfers the result from FPSW into EFLAGS:
14930 // (X86sahf (trunc (srl (X86fp_stsw (trunc (X86cmp ...)), 8))))
14932 SDValue TruncFPSW = DAG.getNode(ISD::TRUNCATE, dl, MVT::i16, Cmp);
14933 SDValue FNStSW = DAG.getNode(X86ISD::FNSTSW16r, dl, MVT::i16, TruncFPSW);
14934 SDValue Srl = DAG.getNode(ISD::SRL, dl, MVT::i16, FNStSW,
14935 DAG.getConstant(8, MVT::i8));
14936 SDValue TruncSrl = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Srl);
14937 return DAG.getNode(X86ISD::SAHF, dl, MVT::i32, TruncSrl);
14940 /// The minimum architected relative accuracy is 2^-12. We need one
14941 /// Newton-Raphson step to have a good float result (24 bits of precision).
14942 SDValue X86TargetLowering::getRsqrtEstimate(SDValue Op,
14943 DAGCombinerInfo &DCI,
14944 unsigned &RefinementSteps,
14945 bool &UseOneConstNR) const {
14946 // FIXME: We should use instruction latency models to calculate the cost of
14947 // each potential sequence, but this is very hard to do reliably because
14948 // at least Intel's Core* chips have variable timing based on the number of
14949 // significant digits in the divisor and/or sqrt operand.
14950 if (!Subtarget->useSqrtEst())
14953 EVT VT = Op.getValueType();
14955 // SSE1 has rsqrtss and rsqrtps.
14956 // TODO: Add support for AVX512 (v16f32).
14957 // It is likely not profitable to do this for f64 because a double-precision
14958 // rsqrt estimate with refinement on x86 prior to FMA requires at least 16
14959 // instructions: convert to single, rsqrtss, convert back to double, refine
14960 // (3 steps = at least 13 insts). If an 'rsqrtsd' variant was added to the ISA
14961 // along with FMA, this could be a throughput win.
14962 if ((Subtarget->hasSSE1() && (VT == MVT::f32 || VT == MVT::v4f32)) ||
14963 (Subtarget->hasAVX() && VT == MVT::v8f32)) {
14964 RefinementSteps = 1;
14965 UseOneConstNR = false;
14966 return DCI.DAG.getNode(X86ISD::FRSQRT, SDLoc(Op), VT, Op);
14971 /// The minimum architected relative accuracy is 2^-12. We need one
14972 /// Newton-Raphson step to have a good float result (24 bits of precision).
14973 SDValue X86TargetLowering::getRecipEstimate(SDValue Op,
14974 DAGCombinerInfo &DCI,
14975 unsigned &RefinementSteps) const {
14976 // FIXME: We should use instruction latency models to calculate the cost of
14977 // each potential sequence, but this is very hard to do reliably because
14978 // at least Intel's Core* chips have variable timing based on the number of
14979 // significant digits in the divisor.
14980 if (!Subtarget->useReciprocalEst())
14983 EVT VT = Op.getValueType();
14985 // SSE1 has rcpss and rcpps. AVX adds a 256-bit variant for rcpps.
14986 // TODO: Add support for AVX512 (v16f32).
14987 // It is likely not profitable to do this for f64 because a double-precision
14988 // reciprocal estimate with refinement on x86 prior to FMA requires
14989 // 15 instructions: convert to single, rcpss, convert back to double, refine
14990 // (3 steps = 12 insts). If an 'rcpsd' variant was added to the ISA
14991 // along with FMA, this could be a throughput win.
14992 if ((Subtarget->hasSSE1() && (VT == MVT::f32 || VT == MVT::v4f32)) ||
14993 (Subtarget->hasAVX() && VT == MVT::v8f32)) {
14994 RefinementSteps = ReciprocalEstimateRefinementSteps;
14995 return DCI.DAG.getNode(X86ISD::FRCP, SDLoc(Op), VT, Op);
15000 static bool isAllOnes(SDValue V) {
15001 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V);
15002 return C && C->isAllOnesValue();
15005 /// LowerToBT - Result of 'and' is compared against zero. Turn it into a BT node
15006 /// if it's possible.
15007 SDValue X86TargetLowering::LowerToBT(SDValue And, ISD::CondCode CC,
15008 SDLoc dl, SelectionDAG &DAG) const {
15009 SDValue Op0 = And.getOperand(0);
15010 SDValue Op1 = And.getOperand(1);
15011 if (Op0.getOpcode() == ISD::TRUNCATE)
15012 Op0 = Op0.getOperand(0);
15013 if (Op1.getOpcode() == ISD::TRUNCATE)
15014 Op1 = Op1.getOperand(0);
15017 if (Op1.getOpcode() == ISD::SHL)
15018 std::swap(Op0, Op1);
15019 if (Op0.getOpcode() == ISD::SHL) {
15020 if (ConstantSDNode *And00C = dyn_cast<ConstantSDNode>(Op0.getOperand(0)))
15021 if (And00C->getZExtValue() == 1) {
15022 // If we looked past a truncate, check that it's only truncating away
15024 unsigned BitWidth = Op0.getValueSizeInBits();
15025 unsigned AndBitWidth = And.getValueSizeInBits();
15026 if (BitWidth > AndBitWidth) {
15028 DAG.computeKnownBits(Op0, Zeros, Ones);
15029 if (Zeros.countLeadingOnes() < BitWidth - AndBitWidth)
15033 RHS = Op0.getOperand(1);
15035 } else if (Op1.getOpcode() == ISD::Constant) {
15036 ConstantSDNode *AndRHS = cast<ConstantSDNode>(Op1);
15037 uint64_t AndRHSVal = AndRHS->getZExtValue();
15038 SDValue AndLHS = Op0;
15040 if (AndRHSVal == 1 && AndLHS.getOpcode() == ISD::SRL) {
15041 LHS = AndLHS.getOperand(0);
15042 RHS = AndLHS.getOperand(1);
15045 // Use BT if the immediate can't be encoded in a TEST instruction.
15046 if (!isUInt<32>(AndRHSVal) && isPowerOf2_64(AndRHSVal)) {
15048 RHS = DAG.getConstant(Log2_64_Ceil(AndRHSVal), LHS.getValueType());
15052 if (LHS.getNode()) {
15053 // If LHS is i8, promote it to i32 with any_extend. There is no i8 BT
15054 // instruction. Since the shift amount is in-range-or-undefined, we know
15055 // that doing a bittest on the i32 value is ok. We extend to i32 because
15056 // the encoding for the i16 version is larger than the i32 version.
15057 // Also promote i16 to i32 for performance / code size reason.
15058 if (LHS.getValueType() == MVT::i8 ||
15059 LHS.getValueType() == MVT::i16)
15060 LHS = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, LHS);
15062 // If the operand types disagree, extend the shift amount to match. Since
15063 // BT ignores high bits (like shifts) we can use anyextend.
15064 if (LHS.getValueType() != RHS.getValueType())
15065 RHS = DAG.getNode(ISD::ANY_EXTEND, dl, LHS.getValueType(), RHS);
15067 SDValue BT = DAG.getNode(X86ISD::BT, dl, MVT::i32, LHS, RHS);
15068 X86::CondCode Cond = CC == ISD::SETEQ ? X86::COND_AE : X86::COND_B;
15069 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
15070 DAG.getConstant(Cond, MVT::i8), BT);
15076 /// \brief - Turns an ISD::CondCode into a value suitable for SSE floating point
15078 static int translateX86FSETCC(ISD::CondCode SetCCOpcode, SDValue &Op0,
15083 // SSE Condition code mapping:
15092 switch (SetCCOpcode) {
15093 default: llvm_unreachable("Unexpected SETCC condition");
15095 case ISD::SETEQ: SSECC = 0; break;
15097 case ISD::SETGT: Swap = true; // Fallthrough
15099 case ISD::SETOLT: SSECC = 1; break;
15101 case ISD::SETGE: Swap = true; // Fallthrough
15103 case ISD::SETOLE: SSECC = 2; break;
15104 case ISD::SETUO: SSECC = 3; break;
15106 case ISD::SETNE: SSECC = 4; break;
15107 case ISD::SETULE: Swap = true; // Fallthrough
15108 case ISD::SETUGE: SSECC = 5; break;
15109 case ISD::SETULT: Swap = true; // Fallthrough
15110 case ISD::SETUGT: SSECC = 6; break;
15111 case ISD::SETO: SSECC = 7; break;
15113 case ISD::SETONE: SSECC = 8; break;
15116 std::swap(Op0, Op1);
15121 // Lower256IntVSETCC - Break a VSETCC 256-bit integer VSETCC into two new 128
15122 // ones, and then concatenate the result back.
15123 static SDValue Lower256IntVSETCC(SDValue Op, SelectionDAG &DAG) {
15124 MVT VT = Op.getSimpleValueType();
15126 assert(VT.is256BitVector() && Op.getOpcode() == ISD::SETCC &&
15127 "Unsupported value type for operation");
15129 unsigned NumElems = VT.getVectorNumElements();
15131 SDValue CC = Op.getOperand(2);
15133 // Extract the LHS vectors
15134 SDValue LHS = Op.getOperand(0);
15135 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
15136 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
15138 // Extract the RHS vectors
15139 SDValue RHS = Op.getOperand(1);
15140 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, dl);
15141 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, dl);
15143 // Issue the operation on the smaller types and concatenate the result back
15144 MVT EltVT = VT.getVectorElementType();
15145 MVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
15146 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
15147 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1, CC),
15148 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2, CC));
15151 static SDValue LowerIntVSETCC_AVX512(SDValue Op, SelectionDAG &DAG,
15152 const X86Subtarget *Subtarget) {
15153 SDValue Op0 = Op.getOperand(0);
15154 SDValue Op1 = Op.getOperand(1);
15155 SDValue CC = Op.getOperand(2);
15156 MVT VT = Op.getSimpleValueType();
15159 assert(Op0.getValueType().getVectorElementType().getSizeInBits() >= 8 &&
15160 Op.getValueType().getScalarType() == MVT::i1 &&
15161 "Cannot set masked compare for this operation");
15163 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
15165 bool Unsigned = false;
15168 switch (SetCCOpcode) {
15169 default: llvm_unreachable("Unexpected SETCC condition");
15170 case ISD::SETNE: SSECC = 4; break;
15171 case ISD::SETEQ: Opc = X86ISD::PCMPEQM; break;
15172 case ISD::SETUGT: SSECC = 6; Unsigned = true; break;
15173 case ISD::SETLT: Swap = true; //fall-through
15174 case ISD::SETGT: Opc = X86ISD::PCMPGTM; break;
15175 case ISD::SETULT: SSECC = 1; Unsigned = true; break;
15176 case ISD::SETUGE: SSECC = 5; Unsigned = true; break; //NLT
15177 case ISD::SETGE: Swap = true; SSECC = 2; break; // LE + swap
15178 case ISD::SETULE: Unsigned = true; //fall-through
15179 case ISD::SETLE: SSECC = 2; break;
15183 std::swap(Op0, Op1);
15185 return DAG.getNode(Opc, dl, VT, Op0, Op1);
15186 Opc = Unsigned ? X86ISD::CMPMU: X86ISD::CMPM;
15187 return DAG.getNode(Opc, dl, VT, Op0, Op1,
15188 DAG.getConstant(SSECC, MVT::i8));
15191 /// \brief Try to turn a VSETULT into a VSETULE by modifying its second
15192 /// operand \p Op1. If non-trivial (for example because it's not constant)
15193 /// return an empty value.
15194 static SDValue ChangeVSETULTtoVSETULE(SDLoc dl, SDValue Op1, SelectionDAG &DAG)
15196 BuildVectorSDNode *BV = dyn_cast<BuildVectorSDNode>(Op1.getNode());
15200 MVT VT = Op1.getSimpleValueType();
15201 MVT EVT = VT.getVectorElementType();
15202 unsigned n = VT.getVectorNumElements();
15203 SmallVector<SDValue, 8> ULTOp1;
15205 for (unsigned i = 0; i < n; ++i) {
15206 ConstantSDNode *Elt = dyn_cast<ConstantSDNode>(BV->getOperand(i));
15207 if (!Elt || Elt->isOpaque() || Elt->getValueType(0) != EVT)
15210 // Avoid underflow.
15211 APInt Val = Elt->getAPIntValue();
15215 ULTOp1.push_back(DAG.getConstant(Val - 1, EVT));
15218 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, ULTOp1);
15221 static SDValue LowerVSETCC(SDValue Op, const X86Subtarget *Subtarget,
15222 SelectionDAG &DAG) {
15223 SDValue Op0 = Op.getOperand(0);
15224 SDValue Op1 = Op.getOperand(1);
15225 SDValue CC = Op.getOperand(2);
15226 MVT VT = Op.getSimpleValueType();
15227 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
15228 bool isFP = Op.getOperand(1).getSimpleValueType().isFloatingPoint();
15233 MVT EltVT = Op0.getSimpleValueType().getVectorElementType();
15234 assert(EltVT == MVT::f32 || EltVT == MVT::f64);
15237 unsigned SSECC = translateX86FSETCC(SetCCOpcode, Op0, Op1);
15238 unsigned Opc = X86ISD::CMPP;
15239 if (Subtarget->hasAVX512() && VT.getVectorElementType() == MVT::i1) {
15240 assert(VT.getVectorNumElements() <= 16);
15241 Opc = X86ISD::CMPM;
15243 // In the two special cases we can't handle, emit two comparisons.
15246 unsigned CombineOpc;
15247 if (SetCCOpcode == ISD::SETUEQ) {
15248 CC0 = 3; CC1 = 0; CombineOpc = ISD::OR;
15250 assert(SetCCOpcode == ISD::SETONE);
15251 CC0 = 7; CC1 = 4; CombineOpc = ISD::AND;
15254 SDValue Cmp0 = DAG.getNode(Opc, dl, VT, Op0, Op1,
15255 DAG.getConstant(CC0, MVT::i8));
15256 SDValue Cmp1 = DAG.getNode(Opc, dl, VT, Op0, Op1,
15257 DAG.getConstant(CC1, MVT::i8));
15258 return DAG.getNode(CombineOpc, dl, VT, Cmp0, Cmp1);
15260 // Handle all other FP comparisons here.
15261 return DAG.getNode(Opc, dl, VT, Op0, Op1,
15262 DAG.getConstant(SSECC, MVT::i8));
15265 // Break 256-bit integer vector compare into smaller ones.
15266 if (VT.is256BitVector() && !Subtarget->hasInt256())
15267 return Lower256IntVSETCC(Op, DAG);
15269 bool MaskResult = (VT.getVectorElementType() == MVT::i1);
15270 EVT OpVT = Op1.getValueType();
15271 if (Subtarget->hasAVX512()) {
15272 if (Op1.getValueType().is512BitVector() ||
15273 (Subtarget->hasBWI() && Subtarget->hasVLX()) ||
15274 (MaskResult && OpVT.getVectorElementType().getSizeInBits() >= 32))
15275 return LowerIntVSETCC_AVX512(Op, DAG, Subtarget);
15277 // In AVX-512 architecture setcc returns mask with i1 elements,
15278 // But there is no compare instruction for i8 and i16 elements in KNL.
15279 // We are not talking about 512-bit operands in this case, these
15280 // types are illegal.
15282 (OpVT.getVectorElementType().getSizeInBits() < 32 &&
15283 OpVT.getVectorElementType().getSizeInBits() >= 8))
15284 return DAG.getNode(ISD::TRUNCATE, dl, VT,
15285 DAG.getNode(ISD::SETCC, dl, OpVT, Op0, Op1, CC));
15288 // We are handling one of the integer comparisons here. Since SSE only has
15289 // GT and EQ comparisons for integer, swapping operands and multiple
15290 // operations may be required for some comparisons.
15292 bool Swap = false, Invert = false, FlipSigns = false, MinMax = false;
15293 bool Subus = false;
15295 switch (SetCCOpcode) {
15296 default: llvm_unreachable("Unexpected SETCC condition");
15297 case ISD::SETNE: Invert = true;
15298 case ISD::SETEQ: Opc = X86ISD::PCMPEQ; break;
15299 case ISD::SETLT: Swap = true;
15300 case ISD::SETGT: Opc = X86ISD::PCMPGT; break;
15301 case ISD::SETGE: Swap = true;
15302 case ISD::SETLE: Opc = X86ISD::PCMPGT;
15303 Invert = true; break;
15304 case ISD::SETULT: Swap = true;
15305 case ISD::SETUGT: Opc = X86ISD::PCMPGT;
15306 FlipSigns = true; break;
15307 case ISD::SETUGE: Swap = true;
15308 case ISD::SETULE: Opc = X86ISD::PCMPGT;
15309 FlipSigns = true; Invert = true; break;
15312 // Special case: Use min/max operations for SETULE/SETUGE
15313 MVT VET = VT.getVectorElementType();
15315 (Subtarget->hasSSE41() && (VET >= MVT::i8 && VET <= MVT::i32))
15316 || (Subtarget->hasSSE2() && (VET == MVT::i8));
15319 switch (SetCCOpcode) {
15321 case ISD::SETULE: Opc = X86ISD::UMIN; MinMax = true; break;
15322 case ISD::SETUGE: Opc = X86ISD::UMAX; MinMax = true; break;
15325 if (MinMax) { Swap = false; Invert = false; FlipSigns = false; }
15328 bool hasSubus = Subtarget->hasSSE2() && (VET == MVT::i8 || VET == MVT::i16);
15329 if (!MinMax && hasSubus) {
15330 // As another special case, use PSUBUS[BW] when it's profitable. E.g. for
15332 // t = psubus Op0, Op1
15333 // pcmpeq t, <0..0>
15334 switch (SetCCOpcode) {
15336 case ISD::SETULT: {
15337 // If the comparison is against a constant we can turn this into a
15338 // setule. With psubus, setule does not require a swap. This is
15339 // beneficial because the constant in the register is no longer
15340 // destructed as the destination so it can be hoisted out of a loop.
15341 // Only do this pre-AVX since vpcmp* is no longer destructive.
15342 if (Subtarget->hasAVX())
15344 SDValue ULEOp1 = ChangeVSETULTtoVSETULE(dl, Op1, DAG);
15345 if (ULEOp1.getNode()) {
15347 Subus = true; Invert = false; Swap = false;
15351 // Psubus is better than flip-sign because it requires no inversion.
15352 case ISD::SETUGE: Subus = true; Invert = false; Swap = true; break;
15353 case ISD::SETULE: Subus = true; Invert = false; Swap = false; break;
15357 Opc = X86ISD::SUBUS;
15363 std::swap(Op0, Op1);
15365 // Check that the operation in question is available (most are plain SSE2,
15366 // but PCMPGTQ and PCMPEQQ have different requirements).
15367 if (VT == MVT::v2i64) {
15368 if (Opc == X86ISD::PCMPGT && !Subtarget->hasSSE42()) {
15369 assert(Subtarget->hasSSE2() && "Don't know how to lower!");
15371 // First cast everything to the right type.
15372 Op0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op0);
15373 Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op1);
15375 // Since SSE has no unsigned integer comparisons, we need to flip the sign
15376 // bits of the inputs before performing those operations. The lower
15377 // compare is always unsigned.
15380 SB = DAG.getConstant(0x80000000U, MVT::v4i32);
15382 SDValue Sign = DAG.getConstant(0x80000000U, MVT::i32);
15383 SDValue Zero = DAG.getConstant(0x00000000U, MVT::i32);
15384 SB = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32,
15385 Sign, Zero, Sign, Zero);
15387 Op0 = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Op0, SB);
15388 Op1 = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Op1, SB);
15390 // Emulate PCMPGTQ with (hi1 > hi2) | ((hi1 == hi2) & (lo1 > lo2))
15391 SDValue GT = DAG.getNode(X86ISD::PCMPGT, dl, MVT::v4i32, Op0, Op1);
15392 SDValue EQ = DAG.getNode(X86ISD::PCMPEQ, dl, MVT::v4i32, Op0, Op1);
15394 // Create masks for only the low parts/high parts of the 64 bit integers.
15395 static const int MaskHi[] = { 1, 1, 3, 3 };
15396 static const int MaskLo[] = { 0, 0, 2, 2 };
15397 SDValue EQHi = DAG.getVectorShuffle(MVT::v4i32, dl, EQ, EQ, MaskHi);
15398 SDValue GTLo = DAG.getVectorShuffle(MVT::v4i32, dl, GT, GT, MaskLo);
15399 SDValue GTHi = DAG.getVectorShuffle(MVT::v4i32, dl, GT, GT, MaskHi);
15401 SDValue Result = DAG.getNode(ISD::AND, dl, MVT::v4i32, EQHi, GTLo);
15402 Result = DAG.getNode(ISD::OR, dl, MVT::v4i32, Result, GTHi);
15405 Result = DAG.getNOT(dl, Result, MVT::v4i32);
15407 return DAG.getNode(ISD::BITCAST, dl, VT, Result);
15410 if (Opc == X86ISD::PCMPEQ && !Subtarget->hasSSE41()) {
15411 // If pcmpeqq is missing but pcmpeqd is available synthesize pcmpeqq with
15412 // pcmpeqd + pshufd + pand.
15413 assert(Subtarget->hasSSE2() && !FlipSigns && "Don't know how to lower!");
15415 // First cast everything to the right type.
15416 Op0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op0);
15417 Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op1);
15420 SDValue Result = DAG.getNode(Opc, dl, MVT::v4i32, Op0, Op1);
15422 // Make sure the lower and upper halves are both all-ones.
15423 static const int Mask[] = { 1, 0, 3, 2 };
15424 SDValue Shuf = DAG.getVectorShuffle(MVT::v4i32, dl, Result, Result, Mask);
15425 Result = DAG.getNode(ISD::AND, dl, MVT::v4i32, Result, Shuf);
15428 Result = DAG.getNOT(dl, Result, MVT::v4i32);
15430 return DAG.getNode(ISD::BITCAST, dl, VT, Result);
15434 // Since SSE has no unsigned integer comparisons, we need to flip the sign
15435 // bits of the inputs before performing those operations.
15437 EVT EltVT = VT.getVectorElementType();
15438 SDValue SB = DAG.getConstant(APInt::getSignBit(EltVT.getSizeInBits()), VT);
15439 Op0 = DAG.getNode(ISD::XOR, dl, VT, Op0, SB);
15440 Op1 = DAG.getNode(ISD::XOR, dl, VT, Op1, SB);
15443 SDValue Result = DAG.getNode(Opc, dl, VT, Op0, Op1);
15445 // If the logical-not of the result is required, perform that now.
15447 Result = DAG.getNOT(dl, Result, VT);
15450 Result = DAG.getNode(X86ISD::PCMPEQ, dl, VT, Op0, Result);
15453 Result = DAG.getNode(X86ISD::PCMPEQ, dl, VT, Result,
15454 getZeroVector(VT, Subtarget, DAG, dl));
15459 SDValue X86TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
15461 MVT VT = Op.getSimpleValueType();
15463 if (VT.isVector()) return LowerVSETCC(Op, Subtarget, DAG);
15465 assert(((!Subtarget->hasAVX512() && VT == MVT::i8) || (VT == MVT::i1))
15466 && "SetCC type must be 8-bit or 1-bit integer");
15467 SDValue Op0 = Op.getOperand(0);
15468 SDValue Op1 = Op.getOperand(1);
15470 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
15472 // Optimize to BT if possible.
15473 // Lower (X & (1 << N)) == 0 to BT(X, N).
15474 // Lower ((X >>u N) & 1) != 0 to BT(X, N).
15475 // Lower ((X >>s N) & 1) != 0 to BT(X, N).
15476 if (Op0.getOpcode() == ISD::AND && Op0.hasOneUse() &&
15477 Op1.getOpcode() == ISD::Constant &&
15478 cast<ConstantSDNode>(Op1)->isNullValue() &&
15479 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
15480 SDValue NewSetCC = LowerToBT(Op0, CC, dl, DAG);
15481 if (NewSetCC.getNode())
15485 // Look for X == 0, X == 1, X != 0, or X != 1. We can simplify some forms of
15487 if (Op1.getOpcode() == ISD::Constant &&
15488 (cast<ConstantSDNode>(Op1)->getZExtValue() == 1 ||
15489 cast<ConstantSDNode>(Op1)->isNullValue()) &&
15490 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
15492 // If the input is a setcc, then reuse the input setcc or use a new one with
15493 // the inverted condition.
15494 if (Op0.getOpcode() == X86ISD::SETCC) {
15495 X86::CondCode CCode = (X86::CondCode)Op0.getConstantOperandVal(0);
15496 bool Invert = (CC == ISD::SETNE) ^
15497 cast<ConstantSDNode>(Op1)->isNullValue();
15501 CCode = X86::GetOppositeBranchCondition(CCode);
15502 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
15503 DAG.getConstant(CCode, MVT::i8),
15504 Op0.getOperand(1));
15506 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, SetCC);
15510 if ((Op0.getValueType() == MVT::i1) && (Op1.getOpcode() == ISD::Constant) &&
15511 (cast<ConstantSDNode>(Op1)->getZExtValue() == 1) &&
15512 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
15514 ISD::CondCode NewCC = ISD::getSetCCInverse(CC, true);
15515 return DAG.getSetCC(dl, VT, Op0, DAG.getConstant(0, MVT::i1), NewCC);
15518 bool isFP = Op1.getSimpleValueType().isFloatingPoint();
15519 unsigned X86CC = TranslateX86CC(CC, isFP, Op0, Op1, DAG);
15520 if (X86CC == X86::COND_INVALID)
15523 SDValue EFLAGS = EmitCmp(Op0, Op1, X86CC, dl, DAG);
15524 EFLAGS = ConvertCmpIfNecessary(EFLAGS, DAG);
15525 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
15526 DAG.getConstant(X86CC, MVT::i8), EFLAGS);
15528 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, SetCC);
15532 // isX86LogicalCmp - Return true if opcode is a X86 logical comparison.
15533 static bool isX86LogicalCmp(SDValue Op) {
15534 unsigned Opc = Op.getNode()->getOpcode();
15535 if (Opc == X86ISD::CMP || Opc == X86ISD::COMI || Opc == X86ISD::UCOMI ||
15536 Opc == X86ISD::SAHF)
15538 if (Op.getResNo() == 1 &&
15539 (Opc == X86ISD::ADD ||
15540 Opc == X86ISD::SUB ||
15541 Opc == X86ISD::ADC ||
15542 Opc == X86ISD::SBB ||
15543 Opc == X86ISD::SMUL ||
15544 Opc == X86ISD::UMUL ||
15545 Opc == X86ISD::INC ||
15546 Opc == X86ISD::DEC ||
15547 Opc == X86ISD::OR ||
15548 Opc == X86ISD::XOR ||
15549 Opc == X86ISD::AND))
15552 if (Op.getResNo() == 2 && Opc == X86ISD::UMUL)
15558 static bool isTruncWithZeroHighBitsInput(SDValue V, SelectionDAG &DAG) {
15559 if (V.getOpcode() != ISD::TRUNCATE)
15562 SDValue VOp0 = V.getOperand(0);
15563 unsigned InBits = VOp0.getValueSizeInBits();
15564 unsigned Bits = V.getValueSizeInBits();
15565 return DAG.MaskedValueIsZero(VOp0, APInt::getHighBitsSet(InBits,InBits-Bits));
15568 SDValue X86TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {
15569 bool addTest = true;
15570 SDValue Cond = Op.getOperand(0);
15571 SDValue Op1 = Op.getOperand(1);
15572 SDValue Op2 = Op.getOperand(2);
15574 EVT VT = Op1.getValueType();
15577 // Lower fp selects into a CMP/AND/ANDN/OR sequence when the necessary SSE ops
15578 // are available. Otherwise fp cmovs get lowered into a less efficient branch
15579 // sequence later on.
15580 if (Cond.getOpcode() == ISD::SETCC &&
15581 ((Subtarget->hasSSE2() && (VT == MVT::f32 || VT == MVT::f64)) ||
15582 (Subtarget->hasSSE1() && VT == MVT::f32)) &&
15583 VT == Cond.getOperand(0).getValueType() && Cond->hasOneUse()) {
15584 SDValue CondOp0 = Cond.getOperand(0), CondOp1 = Cond.getOperand(1);
15585 int SSECC = translateX86FSETCC(
15586 cast<CondCodeSDNode>(Cond.getOperand(2))->get(), CondOp0, CondOp1);
15589 if (Subtarget->hasAVX512()) {
15590 SDValue Cmp = DAG.getNode(X86ISD::FSETCC, DL, MVT::i1, CondOp0, CondOp1,
15591 DAG.getConstant(SSECC, MVT::i8));
15592 return DAG.getNode(X86ISD::SELECT, DL, VT, Cmp, Op1, Op2);
15594 SDValue Cmp = DAG.getNode(X86ISD::FSETCC, DL, VT, CondOp0, CondOp1,
15595 DAG.getConstant(SSECC, MVT::i8));
15596 SDValue AndN = DAG.getNode(X86ISD::FANDN, DL, VT, Cmp, Op2);
15597 SDValue And = DAG.getNode(X86ISD::FAND, DL, VT, Cmp, Op1);
15598 return DAG.getNode(X86ISD::FOR, DL, VT, AndN, And);
15602 if (Cond.getOpcode() == ISD::SETCC) {
15603 SDValue NewCond = LowerSETCC(Cond, DAG);
15604 if (NewCond.getNode())
15608 // (select (x == 0), -1, y) -> (sign_bit (x - 1)) | y
15609 // (select (x == 0), y, -1) -> ~(sign_bit (x - 1)) | y
15610 // (select (x != 0), y, -1) -> (sign_bit (x - 1)) | y
15611 // (select (x != 0), -1, y) -> ~(sign_bit (x - 1)) | y
15612 if (Cond.getOpcode() == X86ISD::SETCC &&
15613 Cond.getOperand(1).getOpcode() == X86ISD::CMP &&
15614 isZero(Cond.getOperand(1).getOperand(1))) {
15615 SDValue Cmp = Cond.getOperand(1);
15617 unsigned CondCode =cast<ConstantSDNode>(Cond.getOperand(0))->getZExtValue();
15619 if ((isAllOnes(Op1) || isAllOnes(Op2)) &&
15620 (CondCode == X86::COND_E || CondCode == X86::COND_NE)) {
15621 SDValue Y = isAllOnes(Op2) ? Op1 : Op2;
15623 SDValue CmpOp0 = Cmp.getOperand(0);
15624 // Apply further optimizations for special cases
15625 // (select (x != 0), -1, 0) -> neg & sbb
15626 // (select (x == 0), 0, -1) -> neg & sbb
15627 if (ConstantSDNode *YC = dyn_cast<ConstantSDNode>(Y))
15628 if (YC->isNullValue() &&
15629 (isAllOnes(Op1) == (CondCode == X86::COND_NE))) {
15630 SDVTList VTs = DAG.getVTList(CmpOp0.getValueType(), MVT::i32);
15631 SDValue Neg = DAG.getNode(X86ISD::SUB, DL, VTs,
15632 DAG.getConstant(0, CmpOp0.getValueType()),
15634 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
15635 DAG.getConstant(X86::COND_B, MVT::i8),
15636 SDValue(Neg.getNode(), 1));
15640 Cmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32,
15641 CmpOp0, DAG.getConstant(1, CmpOp0.getValueType()));
15642 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
15644 SDValue Res = // Res = 0 or -1.
15645 DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
15646 DAG.getConstant(X86::COND_B, MVT::i8), Cmp);
15648 if (isAllOnes(Op1) != (CondCode == X86::COND_E))
15649 Res = DAG.getNOT(DL, Res, Res.getValueType());
15651 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(Op2);
15652 if (!N2C || !N2C->isNullValue())
15653 Res = DAG.getNode(ISD::OR, DL, Res.getValueType(), Res, Y);
15658 // Look past (and (setcc_carry (cmp ...)), 1).
15659 if (Cond.getOpcode() == ISD::AND &&
15660 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
15661 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
15662 if (C && C->getAPIntValue() == 1)
15663 Cond = Cond.getOperand(0);
15666 // If condition flag is set by a X86ISD::CMP, then use it as the condition
15667 // setting operand in place of the X86ISD::SETCC.
15668 unsigned CondOpcode = Cond.getOpcode();
15669 if (CondOpcode == X86ISD::SETCC ||
15670 CondOpcode == X86ISD::SETCC_CARRY) {
15671 CC = Cond.getOperand(0);
15673 SDValue Cmp = Cond.getOperand(1);
15674 unsigned Opc = Cmp.getOpcode();
15675 MVT VT = Op.getSimpleValueType();
15677 bool IllegalFPCMov = false;
15678 if (VT.isFloatingPoint() && !VT.isVector() &&
15679 !isScalarFPTypeInSSEReg(VT)) // FPStack?
15680 IllegalFPCMov = !hasFPCMov(cast<ConstantSDNode>(CC)->getSExtValue());
15682 if ((isX86LogicalCmp(Cmp) && !IllegalFPCMov) ||
15683 Opc == X86ISD::BT) { // FIXME
15687 } else if (CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO ||
15688 CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO ||
15689 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) &&
15690 Cond.getOperand(0).getValueType() != MVT::i8)) {
15691 SDValue LHS = Cond.getOperand(0);
15692 SDValue RHS = Cond.getOperand(1);
15693 unsigned X86Opcode;
15696 switch (CondOpcode) {
15697 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break;
15698 case ISD::SADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break;
15699 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break;
15700 case ISD::SSUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break;
15701 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break;
15702 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break;
15703 default: llvm_unreachable("unexpected overflowing operator");
15705 if (CondOpcode == ISD::UMULO)
15706 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(),
15709 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
15711 SDValue X86Op = DAG.getNode(X86Opcode, DL, VTs, LHS, RHS);
15713 if (CondOpcode == ISD::UMULO)
15714 Cond = X86Op.getValue(2);
15716 Cond = X86Op.getValue(1);
15718 CC = DAG.getConstant(X86Cond, MVT::i8);
15723 // Look pass the truncate if the high bits are known zero.
15724 if (isTruncWithZeroHighBitsInput(Cond, DAG))
15725 Cond = Cond.getOperand(0);
15727 // We know the result of AND is compared against zero. Try to match
15729 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
15730 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, DL, DAG);
15731 if (NewSetCC.getNode()) {
15732 CC = NewSetCC.getOperand(0);
15733 Cond = NewSetCC.getOperand(1);
15740 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
15741 Cond = EmitTest(Cond, X86::COND_NE, DL, DAG);
15744 // a < b ? -1 : 0 -> RES = ~setcc_carry
15745 // a < b ? 0 : -1 -> RES = setcc_carry
15746 // a >= b ? -1 : 0 -> RES = setcc_carry
15747 // a >= b ? 0 : -1 -> RES = ~setcc_carry
15748 if (Cond.getOpcode() == X86ISD::SUB) {
15749 Cond = ConvertCmpIfNecessary(Cond, DAG);
15750 unsigned CondCode = cast<ConstantSDNode>(CC)->getZExtValue();
15752 if ((CondCode == X86::COND_AE || CondCode == X86::COND_B) &&
15753 (isAllOnes(Op1) || isAllOnes(Op2)) && (isZero(Op1) || isZero(Op2))) {
15754 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
15755 DAG.getConstant(X86::COND_B, MVT::i8), Cond);
15756 if (isAllOnes(Op1) != (CondCode == X86::COND_B))
15757 return DAG.getNOT(DL, Res, Res.getValueType());
15762 // X86 doesn't have an i8 cmov. If both operands are the result of a truncate
15763 // widen the cmov and push the truncate through. This avoids introducing a new
15764 // branch during isel and doesn't add any extensions.
15765 if (Op.getValueType() == MVT::i8 &&
15766 Op1.getOpcode() == ISD::TRUNCATE && Op2.getOpcode() == ISD::TRUNCATE) {
15767 SDValue T1 = Op1.getOperand(0), T2 = Op2.getOperand(0);
15768 if (T1.getValueType() == T2.getValueType() &&
15769 // Blacklist CopyFromReg to avoid partial register stalls.
15770 T1.getOpcode() != ISD::CopyFromReg && T2.getOpcode()!=ISD::CopyFromReg){
15771 SDVTList VTs = DAG.getVTList(T1.getValueType(), MVT::Glue);
15772 SDValue Cmov = DAG.getNode(X86ISD::CMOV, DL, VTs, T2, T1, CC, Cond);
15773 return DAG.getNode(ISD::TRUNCATE, DL, Op.getValueType(), Cmov);
15777 // X86ISD::CMOV means set the result (which is operand 1) to the RHS if
15778 // condition is true.
15779 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue);
15780 SDValue Ops[] = { Op2, Op1, CC, Cond };
15781 return DAG.getNode(X86ISD::CMOV, DL, VTs, Ops);
15784 static SDValue LowerSIGN_EXTEND_AVX512(SDValue Op, const X86Subtarget *Subtarget,
15785 SelectionDAG &DAG) {
15786 MVT VT = Op->getSimpleValueType(0);
15787 SDValue In = Op->getOperand(0);
15788 MVT InVT = In.getSimpleValueType();
15789 MVT VTElt = VT.getVectorElementType();
15790 MVT InVTElt = InVT.getVectorElementType();
15794 if ((InVTElt == MVT::i1) &&
15795 (((Subtarget->hasBWI() && Subtarget->hasVLX() &&
15796 VT.getSizeInBits() <= 256 && VTElt.getSizeInBits() <= 16)) ||
15798 ((Subtarget->hasBWI() && VT.is512BitVector() &&
15799 VTElt.getSizeInBits() <= 16)) ||
15801 ((Subtarget->hasDQI() && Subtarget->hasVLX() &&
15802 VT.getSizeInBits() <= 256 && VTElt.getSizeInBits() >= 32)) ||
15804 ((Subtarget->hasDQI() && VT.is512BitVector() &&
15805 VTElt.getSizeInBits() >= 32))))
15806 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
15808 unsigned int NumElts = VT.getVectorNumElements();
15810 if (NumElts != 8 && NumElts != 16)
15813 if (VT.is512BitVector() && InVT.getVectorElementType() != MVT::i1) {
15814 if (In.getOpcode() == X86ISD::VSEXT || In.getOpcode() == X86ISD::VZEXT)
15815 return DAG.getNode(In.getOpcode(), dl, VT, In.getOperand(0));
15816 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
15819 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
15820 assert (InVT.getVectorElementType() == MVT::i1 && "Unexpected vector type");
15822 MVT ExtVT = (NumElts == 8) ? MVT::v8i64 : MVT::v16i32;
15823 Constant *C = ConstantInt::get(*DAG.getContext(),
15824 APInt::getAllOnesValue(ExtVT.getScalarType().getSizeInBits()));
15826 SDValue CP = DAG.getConstantPool(C, TLI.getPointerTy());
15827 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
15828 SDValue Ld = DAG.getLoad(ExtVT.getScalarType(), dl, DAG.getEntryNode(), CP,
15829 MachinePointerInfo::getConstantPool(),
15830 false, false, false, Alignment);
15831 SDValue Brcst = DAG.getNode(X86ISD::VBROADCASTM, dl, ExtVT, In, Ld);
15832 if (VT.is512BitVector())
15834 return DAG.getNode(X86ISD::VTRUNC, dl, VT, Brcst);
15837 static SDValue LowerSIGN_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
15838 SelectionDAG &DAG) {
15839 MVT VT = Op->getSimpleValueType(0);
15840 SDValue In = Op->getOperand(0);
15841 MVT InVT = In.getSimpleValueType();
15844 if (VT.is512BitVector() || InVT.getVectorElementType() == MVT::i1)
15845 return LowerSIGN_EXTEND_AVX512(Op, Subtarget, DAG);
15847 if ((VT != MVT::v4i64 || InVT != MVT::v4i32) &&
15848 (VT != MVT::v8i32 || InVT != MVT::v8i16) &&
15849 (VT != MVT::v16i16 || InVT != MVT::v16i8))
15852 if (Subtarget->hasInt256())
15853 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
15855 // Optimize vectors in AVX mode
15856 // Sign extend v8i16 to v8i32 and
15859 // Divide input vector into two parts
15860 // for v4i32 the shuffle mask will be { 0, 1, -1, -1} {2, 3, -1, -1}
15861 // use vpmovsx instruction to extend v4i32 -> v2i64; v8i16 -> v4i32
15862 // concat the vectors to original VT
15864 unsigned NumElems = InVT.getVectorNumElements();
15865 SDValue Undef = DAG.getUNDEF(InVT);
15867 SmallVector<int,8> ShufMask1(NumElems, -1);
15868 for (unsigned i = 0; i != NumElems/2; ++i)
15871 SDValue OpLo = DAG.getVectorShuffle(InVT, dl, In, Undef, &ShufMask1[0]);
15873 SmallVector<int,8> ShufMask2(NumElems, -1);
15874 for (unsigned i = 0; i != NumElems/2; ++i)
15875 ShufMask2[i] = i + NumElems/2;
15877 SDValue OpHi = DAG.getVectorShuffle(InVT, dl, In, Undef, &ShufMask2[0]);
15879 MVT HalfVT = MVT::getVectorVT(VT.getScalarType(),
15880 VT.getVectorNumElements()/2);
15882 OpLo = DAG.getNode(X86ISD::VSEXT, dl, HalfVT, OpLo);
15883 OpHi = DAG.getNode(X86ISD::VSEXT, dl, HalfVT, OpHi);
15885 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi);
15888 // Lower vector extended loads using a shuffle. If SSSE3 is not available we
15889 // may emit an illegal shuffle but the expansion is still better than scalar
15890 // code. We generate X86ISD::VSEXT for SEXTLOADs if it's available, otherwise
15891 // we'll emit a shuffle and a arithmetic shift.
15892 // TODO: It is possible to support ZExt by zeroing the undef values during
15893 // the shuffle phase or after the shuffle.
15894 static SDValue LowerExtendedLoad(SDValue Op, const X86Subtarget *Subtarget,
15895 SelectionDAG &DAG) {
15896 MVT RegVT = Op.getSimpleValueType();
15897 assert(RegVT.isVector() && "We only custom lower vector sext loads.");
15898 assert(RegVT.isInteger() &&
15899 "We only custom lower integer vector sext loads.");
15901 // Nothing useful we can do without SSE2 shuffles.
15902 assert(Subtarget->hasSSE2() && "We only custom lower sext loads with SSE2.");
15904 LoadSDNode *Ld = cast<LoadSDNode>(Op.getNode());
15906 EVT MemVT = Ld->getMemoryVT();
15907 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
15908 unsigned RegSz = RegVT.getSizeInBits();
15910 ISD::LoadExtType Ext = Ld->getExtensionType();
15912 assert((Ext == ISD::EXTLOAD || Ext == ISD::SEXTLOAD)
15913 && "Only anyext and sext are currently implemented.");
15914 assert(MemVT != RegVT && "Cannot extend to the same type");
15915 assert(MemVT.isVector() && "Must load a vector from memory");
15917 unsigned NumElems = RegVT.getVectorNumElements();
15918 unsigned MemSz = MemVT.getSizeInBits();
15919 assert(RegSz > MemSz && "Register size must be greater than the mem size");
15921 if (Ext == ISD::SEXTLOAD && RegSz == 256 && !Subtarget->hasInt256()) {
15922 // The only way in which we have a legal 256-bit vector result but not the
15923 // integer 256-bit operations needed to directly lower a sextload is if we
15924 // have AVX1 but not AVX2. In that case, we can always emit a sextload to
15925 // a 128-bit vector and a normal sign_extend to 256-bits that should get
15926 // correctly legalized. We do this late to allow the canonical form of
15927 // sextload to persist throughout the rest of the DAG combiner -- it wants
15928 // to fold together any extensions it can, and so will fuse a sign_extend
15929 // of an sextload into a sextload targeting a wider value.
15931 if (MemSz == 128) {
15932 // Just switch this to a normal load.
15933 assert(TLI.isTypeLegal(MemVT) && "If the memory type is a 128-bit type, "
15934 "it must be a legal 128-bit vector "
15936 Load = DAG.getLoad(MemVT, dl, Ld->getChain(), Ld->getBasePtr(),
15937 Ld->getPointerInfo(), Ld->isVolatile(), Ld->isNonTemporal(),
15938 Ld->isInvariant(), Ld->getAlignment());
15940 assert(MemSz < 128 &&
15941 "Can't extend a type wider than 128 bits to a 256 bit vector!");
15942 // Do an sext load to a 128-bit vector type. We want to use the same
15943 // number of elements, but elements half as wide. This will end up being
15944 // recursively lowered by this routine, but will succeed as we definitely
15945 // have all the necessary features if we're using AVX1.
15947 EVT::getIntegerVT(*DAG.getContext(), RegVT.getScalarSizeInBits() / 2);
15948 EVT HalfVecVT = EVT::getVectorVT(*DAG.getContext(), HalfEltVT, NumElems);
15950 DAG.getExtLoad(Ext, dl, HalfVecVT, Ld->getChain(), Ld->getBasePtr(),
15951 Ld->getPointerInfo(), MemVT, Ld->isVolatile(),
15952 Ld->isNonTemporal(), Ld->isInvariant(),
15953 Ld->getAlignment());
15956 // Replace chain users with the new chain.
15957 assert(Load->getNumValues() == 2 && "Loads must carry a chain!");
15958 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), Load.getValue(1));
15960 // Finally, do a normal sign-extend to the desired register.
15961 return DAG.getSExtOrTrunc(Load, dl, RegVT);
15964 // All sizes must be a power of two.
15965 assert(isPowerOf2_32(RegSz * MemSz * NumElems) &&
15966 "Non-power-of-two elements are not custom lowered!");
15968 // Attempt to load the original value using scalar loads.
15969 // Find the largest scalar type that divides the total loaded size.
15970 MVT SclrLoadTy = MVT::i8;
15971 for (unsigned tp = MVT::FIRST_INTEGER_VALUETYPE;
15972 tp < MVT::LAST_INTEGER_VALUETYPE; ++tp) {
15973 MVT Tp = (MVT::SimpleValueType)tp;
15974 if (TLI.isTypeLegal(Tp) && ((MemSz % Tp.getSizeInBits()) == 0)) {
15979 // On 32bit systems, we can't save 64bit integers. Try bitcasting to F64.
15980 if (TLI.isTypeLegal(MVT::f64) && SclrLoadTy.getSizeInBits() < 64 &&
15982 SclrLoadTy = MVT::f64;
15984 // Calculate the number of scalar loads that we need to perform
15985 // in order to load our vector from memory.
15986 unsigned NumLoads = MemSz / SclrLoadTy.getSizeInBits();
15988 assert((Ext != ISD::SEXTLOAD || NumLoads == 1) &&
15989 "Can only lower sext loads with a single scalar load!");
15991 unsigned loadRegZize = RegSz;
15992 if (Ext == ISD::SEXTLOAD && RegSz == 256)
15995 // Represent our vector as a sequence of elements which are the
15996 // largest scalar that we can load.
15997 EVT LoadUnitVecVT = EVT::getVectorVT(
15998 *DAG.getContext(), SclrLoadTy, loadRegZize / SclrLoadTy.getSizeInBits());
16000 // Represent the data using the same element type that is stored in
16001 // memory. In practice, we ''widen'' MemVT.
16003 EVT::getVectorVT(*DAG.getContext(), MemVT.getScalarType(),
16004 loadRegZize / MemVT.getScalarType().getSizeInBits());
16006 assert(WideVecVT.getSizeInBits() == LoadUnitVecVT.getSizeInBits() &&
16007 "Invalid vector type");
16009 // We can't shuffle using an illegal type.
16010 assert(TLI.isTypeLegal(WideVecVT) &&
16011 "We only lower types that form legal widened vector types");
16013 SmallVector<SDValue, 8> Chains;
16014 SDValue Ptr = Ld->getBasePtr();
16015 SDValue Increment =
16016 DAG.getConstant(SclrLoadTy.getSizeInBits() / 8, TLI.getPointerTy());
16017 SDValue Res = DAG.getUNDEF(LoadUnitVecVT);
16019 for (unsigned i = 0; i < NumLoads; ++i) {
16020 // Perform a single load.
16021 SDValue ScalarLoad =
16022 DAG.getLoad(SclrLoadTy, dl, Ld->getChain(), Ptr, Ld->getPointerInfo(),
16023 Ld->isVolatile(), Ld->isNonTemporal(), Ld->isInvariant(),
16024 Ld->getAlignment());
16025 Chains.push_back(ScalarLoad.getValue(1));
16026 // Create the first element type using SCALAR_TO_VECTOR in order to avoid
16027 // another round of DAGCombining.
16029 Res = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, LoadUnitVecVT, ScalarLoad);
16031 Res = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, LoadUnitVecVT, Res,
16032 ScalarLoad, DAG.getIntPtrConstant(i));
16034 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
16037 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Chains);
16039 // Bitcast the loaded value to a vector of the original element type, in
16040 // the size of the target vector type.
16041 SDValue SlicedVec = DAG.getNode(ISD::BITCAST, dl, WideVecVT, Res);
16042 unsigned SizeRatio = RegSz / MemSz;
16044 if (Ext == ISD::SEXTLOAD) {
16045 // If we have SSE4.1, we can directly emit a VSEXT node.
16046 if (Subtarget->hasSSE41()) {
16047 SDValue Sext = DAG.getNode(X86ISD::VSEXT, dl, RegVT, SlicedVec);
16048 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), TF);
16052 // Otherwise we'll shuffle the small elements in the high bits of the
16053 // larger type and perform an arithmetic shift. If the shift is not legal
16054 // it's better to scalarize.
16055 assert(TLI.isOperationLegalOrCustom(ISD::SRA, RegVT) &&
16056 "We can't implement a sext load without an arithmetic right shift!");
16058 // Redistribute the loaded elements into the different locations.
16059 SmallVector<int, 16> ShuffleVec(NumElems * SizeRatio, -1);
16060 for (unsigned i = 0; i != NumElems; ++i)
16061 ShuffleVec[i * SizeRatio + SizeRatio - 1] = i;
16063 SDValue Shuff = DAG.getVectorShuffle(
16064 WideVecVT, dl, SlicedVec, DAG.getUNDEF(WideVecVT), &ShuffleVec[0]);
16066 Shuff = DAG.getNode(ISD::BITCAST, dl, RegVT, Shuff);
16068 // Build the arithmetic shift.
16069 unsigned Amt = RegVT.getVectorElementType().getSizeInBits() -
16070 MemVT.getVectorElementType().getSizeInBits();
16072 DAG.getNode(ISD::SRA, dl, RegVT, Shuff, DAG.getConstant(Amt, RegVT));
16074 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), TF);
16078 // Redistribute the loaded elements into the different locations.
16079 SmallVector<int, 16> ShuffleVec(NumElems * SizeRatio, -1);
16080 for (unsigned i = 0; i != NumElems; ++i)
16081 ShuffleVec[i * SizeRatio] = i;
16083 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, SlicedVec,
16084 DAG.getUNDEF(WideVecVT), &ShuffleVec[0]);
16086 // Bitcast to the requested type.
16087 Shuff = DAG.getNode(ISD::BITCAST, dl, RegVT, Shuff);
16088 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), TF);
16092 // isAndOrOfSingleUseSetCCs - Return true if node is an ISD::AND or
16093 // ISD::OR of two X86ISD::SETCC nodes each of which has no other use apart
16094 // from the AND / OR.
16095 static bool isAndOrOfSetCCs(SDValue Op, unsigned &Opc) {
16096 Opc = Op.getOpcode();
16097 if (Opc != ISD::OR && Opc != ISD::AND)
16099 return (Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
16100 Op.getOperand(0).hasOneUse() &&
16101 Op.getOperand(1).getOpcode() == X86ISD::SETCC &&
16102 Op.getOperand(1).hasOneUse());
16105 // isXor1OfSetCC - Return true if node is an ISD::XOR of a X86ISD::SETCC and
16106 // 1 and that the SETCC node has a single use.
16107 static bool isXor1OfSetCC(SDValue Op) {
16108 if (Op.getOpcode() != ISD::XOR)
16110 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
16111 if (N1C && N1C->getAPIntValue() == 1) {
16112 return Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
16113 Op.getOperand(0).hasOneUse();
16118 SDValue X86TargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) const {
16119 bool addTest = true;
16120 SDValue Chain = Op.getOperand(0);
16121 SDValue Cond = Op.getOperand(1);
16122 SDValue Dest = Op.getOperand(2);
16125 bool Inverted = false;
16127 if (Cond.getOpcode() == ISD::SETCC) {
16128 // Check for setcc([su]{add,sub,mul}o == 0).
16129 if (cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETEQ &&
16130 isa<ConstantSDNode>(Cond.getOperand(1)) &&
16131 cast<ConstantSDNode>(Cond.getOperand(1))->isNullValue() &&
16132 Cond.getOperand(0).getResNo() == 1 &&
16133 (Cond.getOperand(0).getOpcode() == ISD::SADDO ||
16134 Cond.getOperand(0).getOpcode() == ISD::UADDO ||
16135 Cond.getOperand(0).getOpcode() == ISD::SSUBO ||
16136 Cond.getOperand(0).getOpcode() == ISD::USUBO ||
16137 Cond.getOperand(0).getOpcode() == ISD::SMULO ||
16138 Cond.getOperand(0).getOpcode() == ISD::UMULO)) {
16140 Cond = Cond.getOperand(0);
16142 SDValue NewCond = LowerSETCC(Cond, DAG);
16143 if (NewCond.getNode())
16148 // FIXME: LowerXALUO doesn't handle these!!
16149 else if (Cond.getOpcode() == X86ISD::ADD ||
16150 Cond.getOpcode() == X86ISD::SUB ||
16151 Cond.getOpcode() == X86ISD::SMUL ||
16152 Cond.getOpcode() == X86ISD::UMUL)
16153 Cond = LowerXALUO(Cond, DAG);
16156 // Look pass (and (setcc_carry (cmp ...)), 1).
16157 if (Cond.getOpcode() == ISD::AND &&
16158 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
16159 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
16160 if (C && C->getAPIntValue() == 1)
16161 Cond = Cond.getOperand(0);
16164 // If condition flag is set by a X86ISD::CMP, then use it as the condition
16165 // setting operand in place of the X86ISD::SETCC.
16166 unsigned CondOpcode = Cond.getOpcode();
16167 if (CondOpcode == X86ISD::SETCC ||
16168 CondOpcode == X86ISD::SETCC_CARRY) {
16169 CC = Cond.getOperand(0);
16171 SDValue Cmp = Cond.getOperand(1);
16172 unsigned Opc = Cmp.getOpcode();
16173 // FIXME: WHY THE SPECIAL CASING OF LogicalCmp??
16174 if (isX86LogicalCmp(Cmp) || Opc == X86ISD::BT) {
16178 switch (cast<ConstantSDNode>(CC)->getZExtValue()) {
16182 // These can only come from an arithmetic instruction with overflow,
16183 // e.g. SADDO, UADDO.
16184 Cond = Cond.getNode()->getOperand(1);
16190 CondOpcode = Cond.getOpcode();
16191 if (CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO ||
16192 CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO ||
16193 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) &&
16194 Cond.getOperand(0).getValueType() != MVT::i8)) {
16195 SDValue LHS = Cond.getOperand(0);
16196 SDValue RHS = Cond.getOperand(1);
16197 unsigned X86Opcode;
16200 // Keep this in sync with LowerXALUO, otherwise we might create redundant
16201 // instructions that can't be removed afterwards (i.e. X86ISD::ADD and
16203 switch (CondOpcode) {
16204 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break;
16206 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
16208 X86Opcode = X86ISD::INC; X86Cond = X86::COND_O;
16211 X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break;
16212 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break;
16214 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
16216 X86Opcode = X86ISD::DEC; X86Cond = X86::COND_O;
16219 X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break;
16220 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break;
16221 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break;
16222 default: llvm_unreachable("unexpected overflowing operator");
16225 X86Cond = X86::GetOppositeBranchCondition((X86::CondCode)X86Cond);
16226 if (CondOpcode == ISD::UMULO)
16227 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(),
16230 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
16232 SDValue X86Op = DAG.getNode(X86Opcode, dl, VTs, LHS, RHS);
16234 if (CondOpcode == ISD::UMULO)
16235 Cond = X86Op.getValue(2);
16237 Cond = X86Op.getValue(1);
16239 CC = DAG.getConstant(X86Cond, MVT::i8);
16243 if (Cond.hasOneUse() && isAndOrOfSetCCs(Cond, CondOpc)) {
16244 SDValue Cmp = Cond.getOperand(0).getOperand(1);
16245 if (CondOpc == ISD::OR) {
16246 // Also, recognize the pattern generated by an FCMP_UNE. We can emit
16247 // two branches instead of an explicit OR instruction with a
16249 if (Cmp == Cond.getOperand(1).getOperand(1) &&
16250 isX86LogicalCmp(Cmp)) {
16251 CC = Cond.getOperand(0).getOperand(0);
16252 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
16253 Chain, Dest, CC, Cmp);
16254 CC = Cond.getOperand(1).getOperand(0);
16258 } else { // ISD::AND
16259 // Also, recognize the pattern generated by an FCMP_OEQ. We can emit
16260 // two branches instead of an explicit AND instruction with a
16261 // separate test. However, we only do this if this block doesn't
16262 // have a fall-through edge, because this requires an explicit
16263 // jmp when the condition is false.
16264 if (Cmp == Cond.getOperand(1).getOperand(1) &&
16265 isX86LogicalCmp(Cmp) &&
16266 Op.getNode()->hasOneUse()) {
16267 X86::CondCode CCode =
16268 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
16269 CCode = X86::GetOppositeBranchCondition(CCode);
16270 CC = DAG.getConstant(CCode, MVT::i8);
16271 SDNode *User = *Op.getNode()->use_begin();
16272 // Look for an unconditional branch following this conditional branch.
16273 // We need this because we need to reverse the successors in order
16274 // to implement FCMP_OEQ.
16275 if (User->getOpcode() == ISD::BR) {
16276 SDValue FalseBB = User->getOperand(1);
16278 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
16279 assert(NewBR == User);
16283 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
16284 Chain, Dest, CC, Cmp);
16285 X86::CondCode CCode =
16286 (X86::CondCode)Cond.getOperand(1).getConstantOperandVal(0);
16287 CCode = X86::GetOppositeBranchCondition(CCode);
16288 CC = DAG.getConstant(CCode, MVT::i8);
16294 } else if (Cond.hasOneUse() && isXor1OfSetCC(Cond)) {
16295 // Recognize for xorb (setcc), 1 patterns. The xor inverts the condition.
16296 // It should be transformed during dag combiner except when the condition
16297 // is set by a arithmetics with overflow node.
16298 X86::CondCode CCode =
16299 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
16300 CCode = X86::GetOppositeBranchCondition(CCode);
16301 CC = DAG.getConstant(CCode, MVT::i8);
16302 Cond = Cond.getOperand(0).getOperand(1);
16304 } else if (Cond.getOpcode() == ISD::SETCC &&
16305 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETOEQ) {
16306 // For FCMP_OEQ, we can emit
16307 // two branches instead of an explicit AND instruction with a
16308 // separate test. However, we only do this if this block doesn't
16309 // have a fall-through edge, because this requires an explicit
16310 // jmp when the condition is false.
16311 if (Op.getNode()->hasOneUse()) {
16312 SDNode *User = *Op.getNode()->use_begin();
16313 // Look for an unconditional branch following this conditional branch.
16314 // We need this because we need to reverse the successors in order
16315 // to implement FCMP_OEQ.
16316 if (User->getOpcode() == ISD::BR) {
16317 SDValue FalseBB = User->getOperand(1);
16319 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
16320 assert(NewBR == User);
16324 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
16325 Cond.getOperand(0), Cond.getOperand(1));
16326 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
16327 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
16328 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
16329 Chain, Dest, CC, Cmp);
16330 CC = DAG.getConstant(X86::COND_P, MVT::i8);
16335 } else if (Cond.getOpcode() == ISD::SETCC &&
16336 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETUNE) {
16337 // For FCMP_UNE, we can emit
16338 // two branches instead of an explicit AND instruction with a
16339 // separate test. However, we only do this if this block doesn't
16340 // have a fall-through edge, because this requires an explicit
16341 // jmp when the condition is false.
16342 if (Op.getNode()->hasOneUse()) {
16343 SDNode *User = *Op.getNode()->use_begin();
16344 // Look for an unconditional branch following this conditional branch.
16345 // We need this because we need to reverse the successors in order
16346 // to implement FCMP_UNE.
16347 if (User->getOpcode() == ISD::BR) {
16348 SDValue FalseBB = User->getOperand(1);
16350 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
16351 assert(NewBR == User);
16354 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
16355 Cond.getOperand(0), Cond.getOperand(1));
16356 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
16357 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
16358 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
16359 Chain, Dest, CC, Cmp);
16360 CC = DAG.getConstant(X86::COND_NP, MVT::i8);
16370 // Look pass the truncate if the high bits are known zero.
16371 if (isTruncWithZeroHighBitsInput(Cond, DAG))
16372 Cond = Cond.getOperand(0);
16374 // We know the result of AND is compared against zero. Try to match
16376 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
16377 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, dl, DAG);
16378 if (NewSetCC.getNode()) {
16379 CC = NewSetCC.getOperand(0);
16380 Cond = NewSetCC.getOperand(1);
16387 X86::CondCode X86Cond = Inverted ? X86::COND_E : X86::COND_NE;
16388 CC = DAG.getConstant(X86Cond, MVT::i8);
16389 Cond = EmitTest(Cond, X86Cond, dl, DAG);
16391 Cond = ConvertCmpIfNecessary(Cond, DAG);
16392 return DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
16393 Chain, Dest, CC, Cond);
16396 // Lower dynamic stack allocation to _alloca call for Cygwin/Mingw targets.
16397 // Calls to _alloca are needed to probe the stack when allocating more than 4k
16398 // bytes in one go. Touching the stack at 4K increments is necessary to ensure
16399 // that the guard pages used by the OS virtual memory manager are allocated in
16400 // correct sequence.
16402 X86TargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
16403 SelectionDAG &DAG) const {
16404 MachineFunction &MF = DAG.getMachineFunction();
16405 bool SplitStack = MF.shouldSplitStack();
16406 bool Lower = (Subtarget->isOSWindows() && !Subtarget->isTargetMacho()) ||
16411 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
16412 SDNode* Node = Op.getNode();
16414 unsigned SPReg = TLI.getStackPointerRegisterToSaveRestore();
16415 assert(SPReg && "Target cannot require DYNAMIC_STACKALLOC expansion and"
16416 " not tell us which reg is the stack pointer!");
16417 EVT VT = Node->getValueType(0);
16418 SDValue Tmp1 = SDValue(Node, 0);
16419 SDValue Tmp2 = SDValue(Node, 1);
16420 SDValue Tmp3 = Node->getOperand(2);
16421 SDValue Chain = Tmp1.getOperand(0);
16423 // Chain the dynamic stack allocation so that it doesn't modify the stack
16424 // pointer when other instructions are using the stack.
16425 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(0, true),
16428 SDValue Size = Tmp2.getOperand(1);
16429 SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, VT);
16430 Chain = SP.getValue(1);
16431 unsigned Align = cast<ConstantSDNode>(Tmp3)->getZExtValue();
16432 const TargetFrameLowering &TFI = *DAG.getSubtarget().getFrameLowering();
16433 unsigned StackAlign = TFI.getStackAlignment();
16434 Tmp1 = DAG.getNode(ISD::SUB, dl, VT, SP, Size); // Value
16435 if (Align > StackAlign)
16436 Tmp1 = DAG.getNode(ISD::AND, dl, VT, Tmp1,
16437 DAG.getConstant(-(uint64_t)Align, VT));
16438 Chain = DAG.getCopyToReg(Chain, dl, SPReg, Tmp1); // Output chain
16440 Tmp2 = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(0, true),
16441 DAG.getIntPtrConstant(0, true), SDValue(),
16444 SDValue Ops[2] = { Tmp1, Tmp2 };
16445 return DAG.getMergeValues(Ops, dl);
16449 SDValue Chain = Op.getOperand(0);
16450 SDValue Size = Op.getOperand(1);
16451 unsigned Align = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue();
16452 EVT VT = Op.getNode()->getValueType(0);
16454 bool Is64Bit = Subtarget->is64Bit();
16455 EVT SPTy = getPointerTy();
16458 MachineRegisterInfo &MRI = MF.getRegInfo();
16461 // The 64 bit implementation of segmented stacks needs to clobber both r10
16462 // r11. This makes it impossible to use it along with nested parameters.
16463 const Function *F = MF.getFunction();
16465 for (Function::const_arg_iterator I = F->arg_begin(), E = F->arg_end();
16467 if (I->hasNestAttr())
16468 report_fatal_error("Cannot use segmented stacks with functions that "
16469 "have nested arguments.");
16472 const TargetRegisterClass *AddrRegClass =
16473 getRegClassFor(getPointerTy());
16474 unsigned Vreg = MRI.createVirtualRegister(AddrRegClass);
16475 Chain = DAG.getCopyToReg(Chain, dl, Vreg, Size);
16476 SDValue Value = DAG.getNode(X86ISD::SEG_ALLOCA, dl, SPTy, Chain,
16477 DAG.getRegister(Vreg, SPTy));
16478 SDValue Ops1[2] = { Value, Chain };
16479 return DAG.getMergeValues(Ops1, dl);
16482 const unsigned Reg = (Subtarget->isTarget64BitLP64() ? X86::RAX : X86::EAX);
16484 Chain = DAG.getCopyToReg(Chain, dl, Reg, Size, Flag);
16485 Flag = Chain.getValue(1);
16486 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
16488 Chain = DAG.getNode(X86ISD::WIN_ALLOCA, dl, NodeTys, Chain, Flag);
16490 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
16491 DAG.getSubtarget().getRegisterInfo());
16492 unsigned SPReg = RegInfo->getStackRegister();
16493 SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, SPTy);
16494 Chain = SP.getValue(1);
16497 SP = DAG.getNode(ISD::AND, dl, VT, SP.getValue(0),
16498 DAG.getConstant(-(uint64_t)Align, VT));
16499 Chain = DAG.getCopyToReg(Chain, dl, SPReg, SP);
16502 SDValue Ops1[2] = { SP, Chain };
16503 return DAG.getMergeValues(Ops1, dl);
16507 SDValue X86TargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const {
16508 MachineFunction &MF = DAG.getMachineFunction();
16509 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
16511 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
16514 if (!Subtarget->is64Bit() || Subtarget->isTargetWin64()) {
16515 // vastart just stores the address of the VarArgsFrameIndex slot into the
16516 // memory location argument.
16517 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
16519 return DAG.getStore(Op.getOperand(0), DL, FR, Op.getOperand(1),
16520 MachinePointerInfo(SV), false, false, 0);
16524 // gp_offset (0 - 6 * 8)
16525 // fp_offset (48 - 48 + 8 * 16)
16526 // overflow_arg_area (point to parameters coming in memory).
16528 SmallVector<SDValue, 8> MemOps;
16529 SDValue FIN = Op.getOperand(1);
16531 SDValue Store = DAG.getStore(Op.getOperand(0), DL,
16532 DAG.getConstant(FuncInfo->getVarArgsGPOffset(),
16534 FIN, MachinePointerInfo(SV), false, false, 0);
16535 MemOps.push_back(Store);
16538 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
16539 FIN, DAG.getIntPtrConstant(4));
16540 Store = DAG.getStore(Op.getOperand(0), DL,
16541 DAG.getConstant(FuncInfo->getVarArgsFPOffset(),
16543 FIN, MachinePointerInfo(SV, 4), false, false, 0);
16544 MemOps.push_back(Store);
16546 // Store ptr to overflow_arg_area
16547 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
16548 FIN, DAG.getIntPtrConstant(4));
16549 SDValue OVFIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
16551 Store = DAG.getStore(Op.getOperand(0), DL, OVFIN, FIN,
16552 MachinePointerInfo(SV, 8),
16554 MemOps.push_back(Store);
16556 // Store ptr to reg_save_area.
16557 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
16558 FIN, DAG.getIntPtrConstant(8));
16559 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
16561 Store = DAG.getStore(Op.getOperand(0), DL, RSFIN, FIN,
16562 MachinePointerInfo(SV, 16), false, false, 0);
16563 MemOps.push_back(Store);
16564 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOps);
16567 SDValue X86TargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG) const {
16568 assert(Subtarget->is64Bit() &&
16569 "LowerVAARG only handles 64-bit va_arg!");
16570 assert((Subtarget->isTargetLinux() ||
16571 Subtarget->isTargetDarwin()) &&
16572 "Unhandled target in LowerVAARG");
16573 assert(Op.getNode()->getNumOperands() == 4);
16574 SDValue Chain = Op.getOperand(0);
16575 SDValue SrcPtr = Op.getOperand(1);
16576 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
16577 unsigned Align = Op.getConstantOperandVal(3);
16580 EVT ArgVT = Op.getNode()->getValueType(0);
16581 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
16582 uint32_t ArgSize = getDataLayout()->getTypeAllocSize(ArgTy);
16585 // Decide which area this value should be read from.
16586 // TODO: Implement the AMD64 ABI in its entirety. This simple
16587 // selection mechanism works only for the basic types.
16588 if (ArgVT == MVT::f80) {
16589 llvm_unreachable("va_arg for f80 not yet implemented");
16590 } else if (ArgVT.isFloatingPoint() && ArgSize <= 16 /*bytes*/) {
16591 ArgMode = 2; // Argument passed in XMM register. Use fp_offset.
16592 } else if (ArgVT.isInteger() && ArgSize <= 32 /*bytes*/) {
16593 ArgMode = 1; // Argument passed in GPR64 register(s). Use gp_offset.
16595 llvm_unreachable("Unhandled argument type in LowerVAARG");
16598 if (ArgMode == 2) {
16599 // Sanity Check: Make sure using fp_offset makes sense.
16600 assert(!DAG.getTarget().Options.UseSoftFloat &&
16601 !(DAG.getMachineFunction()
16602 .getFunction()->getAttributes()
16603 .hasAttribute(AttributeSet::FunctionIndex,
16604 Attribute::NoImplicitFloat)) &&
16605 Subtarget->hasSSE1());
16608 // Insert VAARG_64 node into the DAG
16609 // VAARG_64 returns two values: Variable Argument Address, Chain
16610 SmallVector<SDValue, 11> InstOps;
16611 InstOps.push_back(Chain);
16612 InstOps.push_back(SrcPtr);
16613 InstOps.push_back(DAG.getConstant(ArgSize, MVT::i32));
16614 InstOps.push_back(DAG.getConstant(ArgMode, MVT::i8));
16615 InstOps.push_back(DAG.getConstant(Align, MVT::i32));
16616 SDVTList VTs = DAG.getVTList(getPointerTy(), MVT::Other);
16617 SDValue VAARG = DAG.getMemIntrinsicNode(X86ISD::VAARG_64, dl,
16618 VTs, InstOps, MVT::i64,
16619 MachinePointerInfo(SV),
16621 /*Volatile=*/false,
16623 /*WriteMem=*/true);
16624 Chain = VAARG.getValue(1);
16626 // Load the next argument and return it
16627 return DAG.getLoad(ArgVT, dl,
16630 MachinePointerInfo(),
16631 false, false, false, 0);
16634 static SDValue LowerVACOPY(SDValue Op, const X86Subtarget *Subtarget,
16635 SelectionDAG &DAG) {
16636 // X86-64 va_list is a struct { i32, i32, i8*, i8* }.
16637 assert(Subtarget->is64Bit() && "This code only handles 64-bit va_copy!");
16638 SDValue Chain = Op.getOperand(0);
16639 SDValue DstPtr = Op.getOperand(1);
16640 SDValue SrcPtr = Op.getOperand(2);
16641 const Value *DstSV = cast<SrcValueSDNode>(Op.getOperand(3))->getValue();
16642 const Value *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
16645 return DAG.getMemcpy(Chain, DL, DstPtr, SrcPtr,
16646 DAG.getIntPtrConstant(24), 8, /*isVolatile*/false,
16648 MachinePointerInfo(DstSV), MachinePointerInfo(SrcSV));
16651 // getTargetVShiftByConstNode - Handle vector element shifts where the shift
16652 // amount is a constant. Takes immediate version of shift as input.
16653 static SDValue getTargetVShiftByConstNode(unsigned Opc, SDLoc dl, MVT VT,
16654 SDValue SrcOp, uint64_t ShiftAmt,
16655 SelectionDAG &DAG) {
16656 MVT ElementType = VT.getVectorElementType();
16658 // Fold this packed shift into its first operand if ShiftAmt is 0.
16662 // Check for ShiftAmt >= element width
16663 if (ShiftAmt >= ElementType.getSizeInBits()) {
16664 if (Opc == X86ISD::VSRAI)
16665 ShiftAmt = ElementType.getSizeInBits() - 1;
16667 return DAG.getConstant(0, VT);
16670 assert((Opc == X86ISD::VSHLI || Opc == X86ISD::VSRLI || Opc == X86ISD::VSRAI)
16671 && "Unknown target vector shift-by-constant node");
16673 // Fold this packed vector shift into a build vector if SrcOp is a
16674 // vector of Constants or UNDEFs, and SrcOp valuetype is the same as VT.
16675 if (VT == SrcOp.getSimpleValueType() &&
16676 ISD::isBuildVectorOfConstantSDNodes(SrcOp.getNode())) {
16677 SmallVector<SDValue, 8> Elts;
16678 unsigned NumElts = SrcOp->getNumOperands();
16679 ConstantSDNode *ND;
16682 default: llvm_unreachable(nullptr);
16683 case X86ISD::VSHLI:
16684 for (unsigned i=0; i!=NumElts; ++i) {
16685 SDValue CurrentOp = SrcOp->getOperand(i);
16686 if (CurrentOp->getOpcode() == ISD::UNDEF) {
16687 Elts.push_back(CurrentOp);
16690 ND = cast<ConstantSDNode>(CurrentOp);
16691 const APInt &C = ND->getAPIntValue();
16692 Elts.push_back(DAG.getConstant(C.shl(ShiftAmt), ElementType));
16695 case X86ISD::VSRLI:
16696 for (unsigned i=0; i!=NumElts; ++i) {
16697 SDValue CurrentOp = SrcOp->getOperand(i);
16698 if (CurrentOp->getOpcode() == ISD::UNDEF) {
16699 Elts.push_back(CurrentOp);
16702 ND = cast<ConstantSDNode>(CurrentOp);
16703 const APInt &C = ND->getAPIntValue();
16704 Elts.push_back(DAG.getConstant(C.lshr(ShiftAmt), ElementType));
16707 case X86ISD::VSRAI:
16708 for (unsigned i=0; i!=NumElts; ++i) {
16709 SDValue CurrentOp = SrcOp->getOperand(i);
16710 if (CurrentOp->getOpcode() == ISD::UNDEF) {
16711 Elts.push_back(CurrentOp);
16714 ND = cast<ConstantSDNode>(CurrentOp);
16715 const APInt &C = ND->getAPIntValue();
16716 Elts.push_back(DAG.getConstant(C.ashr(ShiftAmt), ElementType));
16721 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Elts);
16724 return DAG.getNode(Opc, dl, VT, SrcOp, DAG.getConstant(ShiftAmt, MVT::i8));
16727 // getTargetVShiftNode - Handle vector element shifts where the shift amount
16728 // may or may not be a constant. Takes immediate version of shift as input.
16729 static SDValue getTargetVShiftNode(unsigned Opc, SDLoc dl, MVT VT,
16730 SDValue SrcOp, SDValue ShAmt,
16731 SelectionDAG &DAG) {
16732 assert(ShAmt.getValueType() == MVT::i32 && "ShAmt is not i32");
16734 // Catch shift-by-constant.
16735 if (ConstantSDNode *CShAmt = dyn_cast<ConstantSDNode>(ShAmt))
16736 return getTargetVShiftByConstNode(Opc, dl, VT, SrcOp,
16737 CShAmt->getZExtValue(), DAG);
16739 // Change opcode to non-immediate version
16741 default: llvm_unreachable("Unknown target vector shift node");
16742 case X86ISD::VSHLI: Opc = X86ISD::VSHL; break;
16743 case X86ISD::VSRLI: Opc = X86ISD::VSRL; break;
16744 case X86ISD::VSRAI: Opc = X86ISD::VSRA; break;
16747 // Need to build a vector containing shift amount
16748 // Shift amount is 32-bits, but SSE instructions read 64-bit, so fill with 0
16751 ShOps[1] = DAG.getConstant(0, MVT::i32);
16752 ShOps[2] = ShOps[3] = DAG.getUNDEF(MVT::i32);
16753 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, ShOps);
16755 // The return type has to be a 128-bit type with the same element
16756 // type as the input type.
16757 MVT EltVT = VT.getVectorElementType();
16758 EVT ShVT = MVT::getVectorVT(EltVT, 128/EltVT.getSizeInBits());
16760 ShAmt = DAG.getNode(ISD::BITCAST, dl, ShVT, ShAmt);
16761 return DAG.getNode(Opc, dl, VT, SrcOp, ShAmt);
16764 /// \brief Return (and \p Op, \p Mask) for compare instructions or
16765 /// (vselect \p Mask, \p Op, \p PreservedSrc) for others along with the
16766 /// necessary casting for \p Mask when lowering masking intrinsics.
16767 static SDValue getVectorMaskingNode(SDValue Op, SDValue Mask,
16768 SDValue PreservedSrc,
16769 const X86Subtarget *Subtarget,
16770 SelectionDAG &DAG) {
16771 EVT VT = Op.getValueType();
16772 EVT MaskVT = EVT::getVectorVT(*DAG.getContext(),
16773 MVT::i1, VT.getVectorNumElements());
16774 EVT BitcastVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
16775 Mask.getValueType().getSizeInBits());
16778 assert(MaskVT.isSimple() && "invalid mask type");
16780 if (isAllOnes(Mask))
16783 // In case when MaskVT equals v2i1 or v4i1, low 2 or 4 elements
16784 // are extracted by EXTRACT_SUBVECTOR.
16785 SDValue VMask = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MaskVT,
16786 DAG.getNode(ISD::BITCAST, dl, BitcastVT, Mask),
16787 DAG.getIntPtrConstant(0));
16789 switch (Op.getOpcode()) {
16791 case X86ISD::PCMPEQM:
16792 case X86ISD::PCMPGTM:
16794 case X86ISD::CMPMU:
16795 return DAG.getNode(ISD::AND, dl, VT, Op, VMask);
16797 if (PreservedSrc.getOpcode() == ISD::UNDEF)
16798 PreservedSrc = getZeroVector(VT, Subtarget, DAG, dl);
16799 return DAG.getNode(ISD::VSELECT, dl, VT, VMask, Op, PreservedSrc);
16802 static unsigned getOpcodeForFMAIntrinsic(unsigned IntNo) {
16804 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
16805 case Intrinsic::x86_fma_vfmadd_ps:
16806 case Intrinsic::x86_fma_vfmadd_pd:
16807 case Intrinsic::x86_fma_vfmadd_ps_256:
16808 case Intrinsic::x86_fma_vfmadd_pd_256:
16809 case Intrinsic::x86_fma_mask_vfmadd_ps_512:
16810 case Intrinsic::x86_fma_mask_vfmadd_pd_512:
16811 return X86ISD::FMADD;
16812 case Intrinsic::x86_fma_vfmsub_ps:
16813 case Intrinsic::x86_fma_vfmsub_pd:
16814 case Intrinsic::x86_fma_vfmsub_ps_256:
16815 case Intrinsic::x86_fma_vfmsub_pd_256:
16816 case Intrinsic::x86_fma_mask_vfmsub_ps_512:
16817 case Intrinsic::x86_fma_mask_vfmsub_pd_512:
16818 return X86ISD::FMSUB;
16819 case Intrinsic::x86_fma_vfnmadd_ps:
16820 case Intrinsic::x86_fma_vfnmadd_pd:
16821 case Intrinsic::x86_fma_vfnmadd_ps_256:
16822 case Intrinsic::x86_fma_vfnmadd_pd_256:
16823 case Intrinsic::x86_fma_mask_vfnmadd_ps_512:
16824 case Intrinsic::x86_fma_mask_vfnmadd_pd_512:
16825 return X86ISD::FNMADD;
16826 case Intrinsic::x86_fma_vfnmsub_ps:
16827 case Intrinsic::x86_fma_vfnmsub_pd:
16828 case Intrinsic::x86_fma_vfnmsub_ps_256:
16829 case Intrinsic::x86_fma_vfnmsub_pd_256:
16830 case Intrinsic::x86_fma_mask_vfnmsub_ps_512:
16831 case Intrinsic::x86_fma_mask_vfnmsub_pd_512:
16832 return X86ISD::FNMSUB;
16833 case Intrinsic::x86_fma_vfmaddsub_ps:
16834 case Intrinsic::x86_fma_vfmaddsub_pd:
16835 case Intrinsic::x86_fma_vfmaddsub_ps_256:
16836 case Intrinsic::x86_fma_vfmaddsub_pd_256:
16837 case Intrinsic::x86_fma_mask_vfmaddsub_ps_512:
16838 case Intrinsic::x86_fma_mask_vfmaddsub_pd_512:
16839 return X86ISD::FMADDSUB;
16840 case Intrinsic::x86_fma_vfmsubadd_ps:
16841 case Intrinsic::x86_fma_vfmsubadd_pd:
16842 case Intrinsic::x86_fma_vfmsubadd_ps_256:
16843 case Intrinsic::x86_fma_vfmsubadd_pd_256:
16844 case Intrinsic::x86_fma_mask_vfmsubadd_ps_512:
16845 case Intrinsic::x86_fma_mask_vfmsubadd_pd_512:
16846 return X86ISD::FMSUBADD;
16850 static SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, const X86Subtarget *Subtarget,
16851 SelectionDAG &DAG) {
16853 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
16854 EVT VT = Op.getValueType();
16855 const IntrinsicData* IntrData = getIntrinsicWithoutChain(IntNo);
16857 switch(IntrData->Type) {
16858 case INTR_TYPE_1OP:
16859 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1));
16860 case INTR_TYPE_2OP:
16861 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1),
16863 case INTR_TYPE_3OP:
16864 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1),
16865 Op.getOperand(2), Op.getOperand(3));
16866 case INTR_TYPE_1OP_MASK_RM: {
16867 SDValue Src = Op.getOperand(1);
16868 SDValue Src0 = Op.getOperand(2);
16869 SDValue Mask = Op.getOperand(3);
16870 SDValue RoundingMode = Op.getOperand(4);
16871 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT, Src,
16873 Mask, Src0, Subtarget, DAG);
16875 case INTR_TYPE_2OP_MASK: {
16876 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT, Op.getOperand(1),
16878 Op.getOperand(4), Op.getOperand(3), Subtarget, DAG);
16881 case CMP_MASK_CC: {
16882 // Comparison intrinsics with masks.
16883 // Example of transformation:
16884 // (i8 (int_x86_avx512_mask_pcmpeq_q_128
16885 // (v2i64 %a), (v2i64 %b), (i8 %mask))) ->
16887 // (v8i1 (insert_subvector undef,
16888 // (v2i1 (and (PCMPEQM %a, %b),
16889 // (extract_subvector
16890 // (v8i1 (bitcast %mask)), 0))), 0))))
16891 EVT VT = Op.getOperand(1).getValueType();
16892 EVT MaskVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
16893 VT.getVectorNumElements());
16894 SDValue Mask = Op.getOperand((IntrData->Type == CMP_MASK_CC) ? 4 : 3);
16895 EVT BitcastVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
16896 Mask.getValueType().getSizeInBits());
16898 if (IntrData->Type == CMP_MASK_CC) {
16899 Cmp = DAG.getNode(IntrData->Opc0, dl, MaskVT, Op.getOperand(1),
16900 Op.getOperand(2), Op.getOperand(3));
16902 assert(IntrData->Type == CMP_MASK && "Unexpected intrinsic type!");
16903 Cmp = DAG.getNode(IntrData->Opc0, dl, MaskVT, Op.getOperand(1),
16906 SDValue CmpMask = getVectorMaskingNode(Cmp, Mask,
16907 DAG.getTargetConstant(0, MaskVT),
16909 SDValue Res = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, BitcastVT,
16910 DAG.getUNDEF(BitcastVT), CmpMask,
16911 DAG.getIntPtrConstant(0));
16912 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
16914 case COMI: { // Comparison intrinsics
16915 ISD::CondCode CC = (ISD::CondCode)IntrData->Opc1;
16916 SDValue LHS = Op.getOperand(1);
16917 SDValue RHS = Op.getOperand(2);
16918 unsigned X86CC = TranslateX86CC(CC, true, LHS, RHS, DAG);
16919 assert(X86CC != X86::COND_INVALID && "Unexpected illegal condition!");
16920 SDValue Cond = DAG.getNode(IntrData->Opc0, dl, MVT::i32, LHS, RHS);
16921 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
16922 DAG.getConstant(X86CC, MVT::i8), Cond);
16923 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
16926 return getTargetVShiftNode(IntrData->Opc0, dl, Op.getSimpleValueType(),
16927 Op.getOperand(1), Op.getOperand(2), DAG);
16929 return getVectorMaskingNode(getTargetVShiftNode(IntrData->Opc0, dl, Op.getSimpleValueType(),
16930 Op.getOperand(1), Op.getOperand(2), DAG),
16931 Op.getOperand(4), Op.getOperand(3), Subtarget, DAG);
16938 default: return SDValue(); // Don't custom lower most intrinsics.
16940 // Arithmetic intrinsics.
16941 case Intrinsic::x86_sse2_pmulu_dq:
16942 case Intrinsic::x86_avx2_pmulu_dq:
16943 return DAG.getNode(X86ISD::PMULUDQ, dl, Op.getValueType(),
16944 Op.getOperand(1), Op.getOperand(2));
16946 case Intrinsic::x86_sse41_pmuldq:
16947 case Intrinsic::x86_avx2_pmul_dq:
16948 return DAG.getNode(X86ISD::PMULDQ, dl, Op.getValueType(),
16949 Op.getOperand(1), Op.getOperand(2));
16951 case Intrinsic::x86_sse2_pmulhu_w:
16952 case Intrinsic::x86_avx2_pmulhu_w:
16953 return DAG.getNode(ISD::MULHU, dl, Op.getValueType(),
16954 Op.getOperand(1), Op.getOperand(2));
16956 case Intrinsic::x86_sse2_pmulh_w:
16957 case Intrinsic::x86_avx2_pmulh_w:
16958 return DAG.getNode(ISD::MULHS, dl, Op.getValueType(),
16959 Op.getOperand(1), Op.getOperand(2));
16961 // SSE/SSE2/AVX floating point max/min intrinsics.
16962 case Intrinsic::x86_sse_max_ps:
16963 case Intrinsic::x86_sse2_max_pd:
16964 case Intrinsic::x86_avx_max_ps_256:
16965 case Intrinsic::x86_avx_max_pd_256:
16966 case Intrinsic::x86_sse_min_ps:
16967 case Intrinsic::x86_sse2_min_pd:
16968 case Intrinsic::x86_avx_min_ps_256:
16969 case Intrinsic::x86_avx_min_pd_256: {
16972 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
16973 case Intrinsic::x86_sse_max_ps:
16974 case Intrinsic::x86_sse2_max_pd:
16975 case Intrinsic::x86_avx_max_ps_256:
16976 case Intrinsic::x86_avx_max_pd_256:
16977 Opcode = X86ISD::FMAX;
16979 case Intrinsic::x86_sse_min_ps:
16980 case Intrinsic::x86_sse2_min_pd:
16981 case Intrinsic::x86_avx_min_ps_256:
16982 case Intrinsic::x86_avx_min_pd_256:
16983 Opcode = X86ISD::FMIN;
16986 return DAG.getNode(Opcode, dl, Op.getValueType(),
16987 Op.getOperand(1), Op.getOperand(2));
16990 // AVX2 variable shift intrinsics
16991 case Intrinsic::x86_avx2_psllv_d:
16992 case Intrinsic::x86_avx2_psllv_q:
16993 case Intrinsic::x86_avx2_psllv_d_256:
16994 case Intrinsic::x86_avx2_psllv_q_256:
16995 case Intrinsic::x86_avx2_psrlv_d:
16996 case Intrinsic::x86_avx2_psrlv_q:
16997 case Intrinsic::x86_avx2_psrlv_d_256:
16998 case Intrinsic::x86_avx2_psrlv_q_256:
16999 case Intrinsic::x86_avx2_psrav_d:
17000 case Intrinsic::x86_avx2_psrav_d_256: {
17003 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
17004 case Intrinsic::x86_avx2_psllv_d:
17005 case Intrinsic::x86_avx2_psllv_q:
17006 case Intrinsic::x86_avx2_psllv_d_256:
17007 case Intrinsic::x86_avx2_psllv_q_256:
17010 case Intrinsic::x86_avx2_psrlv_d:
17011 case Intrinsic::x86_avx2_psrlv_q:
17012 case Intrinsic::x86_avx2_psrlv_d_256:
17013 case Intrinsic::x86_avx2_psrlv_q_256:
17016 case Intrinsic::x86_avx2_psrav_d:
17017 case Intrinsic::x86_avx2_psrav_d_256:
17021 return DAG.getNode(Opcode, dl, Op.getValueType(),
17022 Op.getOperand(1), Op.getOperand(2));
17025 case Intrinsic::x86_sse2_packssdw_128:
17026 case Intrinsic::x86_sse2_packsswb_128:
17027 case Intrinsic::x86_avx2_packssdw:
17028 case Intrinsic::x86_avx2_packsswb:
17029 return DAG.getNode(X86ISD::PACKSS, dl, Op.getValueType(),
17030 Op.getOperand(1), Op.getOperand(2));
17032 case Intrinsic::x86_sse2_packuswb_128:
17033 case Intrinsic::x86_sse41_packusdw:
17034 case Intrinsic::x86_avx2_packuswb:
17035 case Intrinsic::x86_avx2_packusdw:
17036 return DAG.getNode(X86ISD::PACKUS, dl, Op.getValueType(),
17037 Op.getOperand(1), Op.getOperand(2));
17039 case Intrinsic::x86_ssse3_pshuf_b_128:
17040 case Intrinsic::x86_avx2_pshuf_b:
17041 return DAG.getNode(X86ISD::PSHUFB, dl, Op.getValueType(),
17042 Op.getOperand(1), Op.getOperand(2));
17044 case Intrinsic::x86_sse2_pshuf_d:
17045 return DAG.getNode(X86ISD::PSHUFD, dl, Op.getValueType(),
17046 Op.getOperand(1), Op.getOperand(2));
17048 case Intrinsic::x86_sse2_pshufl_w:
17049 return DAG.getNode(X86ISD::PSHUFLW, dl, Op.getValueType(),
17050 Op.getOperand(1), Op.getOperand(2));
17052 case Intrinsic::x86_sse2_pshufh_w:
17053 return DAG.getNode(X86ISD::PSHUFHW, dl, Op.getValueType(),
17054 Op.getOperand(1), Op.getOperand(2));
17056 case Intrinsic::x86_ssse3_psign_b_128:
17057 case Intrinsic::x86_ssse3_psign_w_128:
17058 case Intrinsic::x86_ssse3_psign_d_128:
17059 case Intrinsic::x86_avx2_psign_b:
17060 case Intrinsic::x86_avx2_psign_w:
17061 case Intrinsic::x86_avx2_psign_d:
17062 return DAG.getNode(X86ISD::PSIGN, dl, Op.getValueType(),
17063 Op.getOperand(1), Op.getOperand(2));
17065 case Intrinsic::x86_avx2_permd:
17066 case Intrinsic::x86_avx2_permps:
17067 // Operands intentionally swapped. Mask is last operand to intrinsic,
17068 // but second operand for node/instruction.
17069 return DAG.getNode(X86ISD::VPERMV, dl, Op.getValueType(),
17070 Op.getOperand(2), Op.getOperand(1));
17072 case Intrinsic::x86_avx512_mask_valign_q_512:
17073 case Intrinsic::x86_avx512_mask_valign_d_512:
17074 // Vector source operands are swapped.
17075 return getVectorMaskingNode(DAG.getNode(X86ISD::VALIGN, dl,
17076 Op.getValueType(), Op.getOperand(2),
17079 Op.getOperand(5), Op.getOperand(4),
17082 // ptest and testp intrinsics. The intrinsic these come from are designed to
17083 // return an integer value, not just an instruction so lower it to the ptest
17084 // or testp pattern and a setcc for the result.
17085 case Intrinsic::x86_sse41_ptestz:
17086 case Intrinsic::x86_sse41_ptestc:
17087 case Intrinsic::x86_sse41_ptestnzc:
17088 case Intrinsic::x86_avx_ptestz_256:
17089 case Intrinsic::x86_avx_ptestc_256:
17090 case Intrinsic::x86_avx_ptestnzc_256:
17091 case Intrinsic::x86_avx_vtestz_ps:
17092 case Intrinsic::x86_avx_vtestc_ps:
17093 case Intrinsic::x86_avx_vtestnzc_ps:
17094 case Intrinsic::x86_avx_vtestz_pd:
17095 case Intrinsic::x86_avx_vtestc_pd:
17096 case Intrinsic::x86_avx_vtestnzc_pd:
17097 case Intrinsic::x86_avx_vtestz_ps_256:
17098 case Intrinsic::x86_avx_vtestc_ps_256:
17099 case Intrinsic::x86_avx_vtestnzc_ps_256:
17100 case Intrinsic::x86_avx_vtestz_pd_256:
17101 case Intrinsic::x86_avx_vtestc_pd_256:
17102 case Intrinsic::x86_avx_vtestnzc_pd_256: {
17103 bool IsTestPacked = false;
17106 default: llvm_unreachable("Bad fallthrough in Intrinsic lowering.");
17107 case Intrinsic::x86_avx_vtestz_ps:
17108 case Intrinsic::x86_avx_vtestz_pd:
17109 case Intrinsic::x86_avx_vtestz_ps_256:
17110 case Intrinsic::x86_avx_vtestz_pd_256:
17111 IsTestPacked = true; // Fallthrough
17112 case Intrinsic::x86_sse41_ptestz:
17113 case Intrinsic::x86_avx_ptestz_256:
17115 X86CC = X86::COND_E;
17117 case Intrinsic::x86_avx_vtestc_ps:
17118 case Intrinsic::x86_avx_vtestc_pd:
17119 case Intrinsic::x86_avx_vtestc_ps_256:
17120 case Intrinsic::x86_avx_vtestc_pd_256:
17121 IsTestPacked = true; // Fallthrough
17122 case Intrinsic::x86_sse41_ptestc:
17123 case Intrinsic::x86_avx_ptestc_256:
17125 X86CC = X86::COND_B;
17127 case Intrinsic::x86_avx_vtestnzc_ps:
17128 case Intrinsic::x86_avx_vtestnzc_pd:
17129 case Intrinsic::x86_avx_vtestnzc_ps_256:
17130 case Intrinsic::x86_avx_vtestnzc_pd_256:
17131 IsTestPacked = true; // Fallthrough
17132 case Intrinsic::x86_sse41_ptestnzc:
17133 case Intrinsic::x86_avx_ptestnzc_256:
17135 X86CC = X86::COND_A;
17139 SDValue LHS = Op.getOperand(1);
17140 SDValue RHS = Op.getOperand(2);
17141 unsigned TestOpc = IsTestPacked ? X86ISD::TESTP : X86ISD::PTEST;
17142 SDValue Test = DAG.getNode(TestOpc, dl, MVT::i32, LHS, RHS);
17143 SDValue CC = DAG.getConstant(X86CC, MVT::i8);
17144 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8, CC, Test);
17145 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
17147 case Intrinsic::x86_avx512_kortestz_w:
17148 case Intrinsic::x86_avx512_kortestc_w: {
17149 unsigned X86CC = (IntNo == Intrinsic::x86_avx512_kortestz_w)? X86::COND_E: X86::COND_B;
17150 SDValue LHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i1, Op.getOperand(1));
17151 SDValue RHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i1, Op.getOperand(2));
17152 SDValue CC = DAG.getConstant(X86CC, MVT::i8);
17153 SDValue Test = DAG.getNode(X86ISD::KORTEST, dl, MVT::i32, LHS, RHS);
17154 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i1, CC, Test);
17155 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
17158 case Intrinsic::x86_sse42_pcmpistria128:
17159 case Intrinsic::x86_sse42_pcmpestria128:
17160 case Intrinsic::x86_sse42_pcmpistric128:
17161 case Intrinsic::x86_sse42_pcmpestric128:
17162 case Intrinsic::x86_sse42_pcmpistrio128:
17163 case Intrinsic::x86_sse42_pcmpestrio128:
17164 case Intrinsic::x86_sse42_pcmpistris128:
17165 case Intrinsic::x86_sse42_pcmpestris128:
17166 case Intrinsic::x86_sse42_pcmpistriz128:
17167 case Intrinsic::x86_sse42_pcmpestriz128: {
17171 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
17172 case Intrinsic::x86_sse42_pcmpistria128:
17173 Opcode = X86ISD::PCMPISTRI;
17174 X86CC = X86::COND_A;
17176 case Intrinsic::x86_sse42_pcmpestria128:
17177 Opcode = X86ISD::PCMPESTRI;
17178 X86CC = X86::COND_A;
17180 case Intrinsic::x86_sse42_pcmpistric128:
17181 Opcode = X86ISD::PCMPISTRI;
17182 X86CC = X86::COND_B;
17184 case Intrinsic::x86_sse42_pcmpestric128:
17185 Opcode = X86ISD::PCMPESTRI;
17186 X86CC = X86::COND_B;
17188 case Intrinsic::x86_sse42_pcmpistrio128:
17189 Opcode = X86ISD::PCMPISTRI;
17190 X86CC = X86::COND_O;
17192 case Intrinsic::x86_sse42_pcmpestrio128:
17193 Opcode = X86ISD::PCMPESTRI;
17194 X86CC = X86::COND_O;
17196 case Intrinsic::x86_sse42_pcmpistris128:
17197 Opcode = X86ISD::PCMPISTRI;
17198 X86CC = X86::COND_S;
17200 case Intrinsic::x86_sse42_pcmpestris128:
17201 Opcode = X86ISD::PCMPESTRI;
17202 X86CC = X86::COND_S;
17204 case Intrinsic::x86_sse42_pcmpistriz128:
17205 Opcode = X86ISD::PCMPISTRI;
17206 X86CC = X86::COND_E;
17208 case Intrinsic::x86_sse42_pcmpestriz128:
17209 Opcode = X86ISD::PCMPESTRI;
17210 X86CC = X86::COND_E;
17213 SmallVector<SDValue, 5> NewOps(Op->op_begin()+1, Op->op_end());
17214 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
17215 SDValue PCMP = DAG.getNode(Opcode, dl, VTs, NewOps);
17216 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
17217 DAG.getConstant(X86CC, MVT::i8),
17218 SDValue(PCMP.getNode(), 1));
17219 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
17222 case Intrinsic::x86_sse42_pcmpistri128:
17223 case Intrinsic::x86_sse42_pcmpestri128: {
17225 if (IntNo == Intrinsic::x86_sse42_pcmpistri128)
17226 Opcode = X86ISD::PCMPISTRI;
17228 Opcode = X86ISD::PCMPESTRI;
17230 SmallVector<SDValue, 5> NewOps(Op->op_begin()+1, Op->op_end());
17231 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
17232 return DAG.getNode(Opcode, dl, VTs, NewOps);
17235 case Intrinsic::x86_fma_mask_vfmadd_ps_512:
17236 case Intrinsic::x86_fma_mask_vfmadd_pd_512:
17237 case Intrinsic::x86_fma_mask_vfmsub_ps_512:
17238 case Intrinsic::x86_fma_mask_vfmsub_pd_512:
17239 case Intrinsic::x86_fma_mask_vfnmadd_ps_512:
17240 case Intrinsic::x86_fma_mask_vfnmadd_pd_512:
17241 case Intrinsic::x86_fma_mask_vfnmsub_ps_512:
17242 case Intrinsic::x86_fma_mask_vfnmsub_pd_512:
17243 case Intrinsic::x86_fma_mask_vfmaddsub_ps_512:
17244 case Intrinsic::x86_fma_mask_vfmaddsub_pd_512:
17245 case Intrinsic::x86_fma_mask_vfmsubadd_ps_512:
17246 case Intrinsic::x86_fma_mask_vfmsubadd_pd_512: {
17247 auto *SAE = cast<ConstantSDNode>(Op.getOperand(5));
17248 if (SAE->getZExtValue() == X86::STATIC_ROUNDING::CUR_DIRECTION)
17249 return getVectorMaskingNode(DAG.getNode(getOpcodeForFMAIntrinsic(IntNo),
17250 dl, Op.getValueType(),
17254 Op.getOperand(4), Op.getOperand(1),
17260 case Intrinsic::x86_fma_vfmadd_ps:
17261 case Intrinsic::x86_fma_vfmadd_pd:
17262 case Intrinsic::x86_fma_vfmsub_ps:
17263 case Intrinsic::x86_fma_vfmsub_pd:
17264 case Intrinsic::x86_fma_vfnmadd_ps:
17265 case Intrinsic::x86_fma_vfnmadd_pd:
17266 case Intrinsic::x86_fma_vfnmsub_ps:
17267 case Intrinsic::x86_fma_vfnmsub_pd:
17268 case Intrinsic::x86_fma_vfmaddsub_ps:
17269 case Intrinsic::x86_fma_vfmaddsub_pd:
17270 case Intrinsic::x86_fma_vfmsubadd_ps:
17271 case Intrinsic::x86_fma_vfmsubadd_pd:
17272 case Intrinsic::x86_fma_vfmadd_ps_256:
17273 case Intrinsic::x86_fma_vfmadd_pd_256:
17274 case Intrinsic::x86_fma_vfmsub_ps_256:
17275 case Intrinsic::x86_fma_vfmsub_pd_256:
17276 case Intrinsic::x86_fma_vfnmadd_ps_256:
17277 case Intrinsic::x86_fma_vfnmadd_pd_256:
17278 case Intrinsic::x86_fma_vfnmsub_ps_256:
17279 case Intrinsic::x86_fma_vfnmsub_pd_256:
17280 case Intrinsic::x86_fma_vfmaddsub_ps_256:
17281 case Intrinsic::x86_fma_vfmaddsub_pd_256:
17282 case Intrinsic::x86_fma_vfmsubadd_ps_256:
17283 case Intrinsic::x86_fma_vfmsubadd_pd_256:
17284 return DAG.getNode(getOpcodeForFMAIntrinsic(IntNo), dl, Op.getValueType(),
17285 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
17289 static SDValue getGatherNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
17290 SDValue Src, SDValue Mask, SDValue Base,
17291 SDValue Index, SDValue ScaleOp, SDValue Chain,
17292 const X86Subtarget * Subtarget) {
17294 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
17295 assert(C && "Invalid scale type");
17296 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), MVT::i8);
17297 EVT MaskVT = MVT::getVectorVT(MVT::i1,
17298 Index.getSimpleValueType().getVectorNumElements());
17300 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(Mask);
17302 MaskInReg = DAG.getTargetConstant(MaskC->getSExtValue(), MaskVT);
17304 MaskInReg = DAG.getNode(ISD::BITCAST, dl, MaskVT, Mask);
17305 SDVTList VTs = DAG.getVTList(Op.getValueType(), MaskVT, MVT::Other);
17306 SDValue Disp = DAG.getTargetConstant(0, MVT::i32);
17307 SDValue Segment = DAG.getRegister(0, MVT::i32);
17308 if (Src.getOpcode() == ISD::UNDEF)
17309 Src = getZeroVector(Op.getValueType(), Subtarget, DAG, dl);
17310 SDValue Ops[] = {Src, MaskInReg, Base, Scale, Index, Disp, Segment, Chain};
17311 SDNode *Res = DAG.getMachineNode(Opc, dl, VTs, Ops);
17312 SDValue RetOps[] = { SDValue(Res, 0), SDValue(Res, 2) };
17313 return DAG.getMergeValues(RetOps, dl);
17316 static SDValue getScatterNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
17317 SDValue Src, SDValue Mask, SDValue Base,
17318 SDValue Index, SDValue ScaleOp, SDValue Chain) {
17320 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
17321 assert(C && "Invalid scale type");
17322 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), MVT::i8);
17323 SDValue Disp = DAG.getTargetConstant(0, MVT::i32);
17324 SDValue Segment = DAG.getRegister(0, MVT::i32);
17325 EVT MaskVT = MVT::getVectorVT(MVT::i1,
17326 Index.getSimpleValueType().getVectorNumElements());
17328 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(Mask);
17330 MaskInReg = DAG.getTargetConstant(MaskC->getSExtValue(), MaskVT);
17332 MaskInReg = DAG.getNode(ISD::BITCAST, dl, MaskVT, Mask);
17333 SDVTList VTs = DAG.getVTList(MaskVT, MVT::Other);
17334 SDValue Ops[] = {Base, Scale, Index, Disp, Segment, MaskInReg, Src, Chain};
17335 SDNode *Res = DAG.getMachineNode(Opc, dl, VTs, Ops);
17336 return SDValue(Res, 1);
17339 static SDValue getPrefetchNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
17340 SDValue Mask, SDValue Base, SDValue Index,
17341 SDValue ScaleOp, SDValue Chain) {
17343 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
17344 assert(C && "Invalid scale type");
17345 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), MVT::i8);
17346 SDValue Disp = DAG.getTargetConstant(0, MVT::i32);
17347 SDValue Segment = DAG.getRegister(0, MVT::i32);
17349 MVT::getVectorVT(MVT::i1, Index.getSimpleValueType().getVectorNumElements());
17351 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(Mask);
17353 MaskInReg = DAG.getTargetConstant(MaskC->getSExtValue(), MaskVT);
17355 MaskInReg = DAG.getNode(ISD::BITCAST, dl, MaskVT, Mask);
17356 //SDVTList VTs = DAG.getVTList(MVT::Other);
17357 SDValue Ops[] = {MaskInReg, Base, Scale, Index, Disp, Segment, Chain};
17358 SDNode *Res = DAG.getMachineNode(Opc, dl, MVT::Other, Ops);
17359 return SDValue(Res, 0);
17362 // getReadPerformanceCounter - Handles the lowering of builtin intrinsics that
17363 // read performance monitor counters (x86_rdpmc).
17364 static void getReadPerformanceCounter(SDNode *N, SDLoc DL,
17365 SelectionDAG &DAG, const X86Subtarget *Subtarget,
17366 SmallVectorImpl<SDValue> &Results) {
17367 assert(N->getNumOperands() == 3 && "Unexpected number of operands!");
17368 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
17371 // The ECX register is used to select the index of the performance counter
17373 SDValue Chain = DAG.getCopyToReg(N->getOperand(0), DL, X86::ECX,
17375 SDValue rd = DAG.getNode(X86ISD::RDPMC_DAG, DL, Tys, Chain);
17377 // Reads the content of a 64-bit performance counter and returns it in the
17378 // registers EDX:EAX.
17379 if (Subtarget->is64Bit()) {
17380 LO = DAG.getCopyFromReg(rd, DL, X86::RAX, MVT::i64, rd.getValue(1));
17381 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::RDX, MVT::i64,
17384 LO = DAG.getCopyFromReg(rd, DL, X86::EAX, MVT::i32, rd.getValue(1));
17385 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::EDX, MVT::i32,
17388 Chain = HI.getValue(1);
17390 if (Subtarget->is64Bit()) {
17391 // The EAX register is loaded with the low-order 32 bits. The EDX register
17392 // is loaded with the supported high-order bits of the counter.
17393 SDValue Tmp = DAG.getNode(ISD::SHL, DL, MVT::i64, HI,
17394 DAG.getConstant(32, MVT::i8));
17395 Results.push_back(DAG.getNode(ISD::OR, DL, MVT::i64, LO, Tmp));
17396 Results.push_back(Chain);
17400 // Use a buildpair to merge the two 32-bit values into a 64-bit one.
17401 SDValue Ops[] = { LO, HI };
17402 SDValue Pair = DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops);
17403 Results.push_back(Pair);
17404 Results.push_back(Chain);
17407 // getReadTimeStampCounter - Handles the lowering of builtin intrinsics that
17408 // read the time stamp counter (x86_rdtsc and x86_rdtscp). This function is
17409 // also used to custom lower READCYCLECOUNTER nodes.
17410 static void getReadTimeStampCounter(SDNode *N, SDLoc DL, unsigned Opcode,
17411 SelectionDAG &DAG, const X86Subtarget *Subtarget,
17412 SmallVectorImpl<SDValue> &Results) {
17413 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
17414 SDValue rd = DAG.getNode(Opcode, DL, Tys, N->getOperand(0));
17417 // The processor's time-stamp counter (a 64-bit MSR) is stored into the
17418 // EDX:EAX registers. EDX is loaded with the high-order 32 bits of the MSR
17419 // and the EAX register is loaded with the low-order 32 bits.
17420 if (Subtarget->is64Bit()) {
17421 LO = DAG.getCopyFromReg(rd, DL, X86::RAX, MVT::i64, rd.getValue(1));
17422 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::RDX, MVT::i64,
17425 LO = DAG.getCopyFromReg(rd, DL, X86::EAX, MVT::i32, rd.getValue(1));
17426 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::EDX, MVT::i32,
17429 SDValue Chain = HI.getValue(1);
17431 if (Opcode == X86ISD::RDTSCP_DAG) {
17432 assert(N->getNumOperands() == 3 && "Unexpected number of operands!");
17434 // Instruction RDTSCP loads the IA32:TSC_AUX_MSR (address C000_0103H) into
17435 // the ECX register. Add 'ecx' explicitly to the chain.
17436 SDValue ecx = DAG.getCopyFromReg(Chain, DL, X86::ECX, MVT::i32,
17438 // Explicitly store the content of ECX at the location passed in input
17439 // to the 'rdtscp' intrinsic.
17440 Chain = DAG.getStore(ecx.getValue(1), DL, ecx, N->getOperand(2),
17441 MachinePointerInfo(), false, false, 0);
17444 if (Subtarget->is64Bit()) {
17445 // The EDX register is loaded with the high-order 32 bits of the MSR, and
17446 // the EAX register is loaded with the low-order 32 bits.
17447 SDValue Tmp = DAG.getNode(ISD::SHL, DL, MVT::i64, HI,
17448 DAG.getConstant(32, MVT::i8));
17449 Results.push_back(DAG.getNode(ISD::OR, DL, MVT::i64, LO, Tmp));
17450 Results.push_back(Chain);
17454 // Use a buildpair to merge the two 32-bit values into a 64-bit one.
17455 SDValue Ops[] = { LO, HI };
17456 SDValue Pair = DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops);
17457 Results.push_back(Pair);
17458 Results.push_back(Chain);
17461 static SDValue LowerREADCYCLECOUNTER(SDValue Op, const X86Subtarget *Subtarget,
17462 SelectionDAG &DAG) {
17463 SmallVector<SDValue, 2> Results;
17465 getReadTimeStampCounter(Op.getNode(), DL, X86ISD::RDTSC_DAG, DAG, Subtarget,
17467 return DAG.getMergeValues(Results, DL);
17471 static SDValue LowerINTRINSIC_W_CHAIN(SDValue Op, const X86Subtarget *Subtarget,
17472 SelectionDAG &DAG) {
17473 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
17475 const IntrinsicData* IntrData = getIntrinsicWithChain(IntNo);
17480 switch(IntrData->Type) {
17482 llvm_unreachable("Unknown Intrinsic Type");
17486 // Emit the node with the right value type.
17487 SDVTList VTs = DAG.getVTList(Op->getValueType(0), MVT::Glue, MVT::Other);
17488 SDValue Result = DAG.getNode(IntrData->Opc0, dl, VTs, Op.getOperand(0));
17490 // If the value returned by RDRAND/RDSEED was valid (CF=1), return 1.
17491 // Otherwise return the value from Rand, which is always 0, casted to i32.
17492 SDValue Ops[] = { DAG.getZExtOrTrunc(Result, dl, Op->getValueType(1)),
17493 DAG.getConstant(1, Op->getValueType(1)),
17494 DAG.getConstant(X86::COND_B, MVT::i32),
17495 SDValue(Result.getNode(), 1) };
17496 SDValue isValid = DAG.getNode(X86ISD::CMOV, dl,
17497 DAG.getVTList(Op->getValueType(1), MVT::Glue),
17500 // Return { result, isValid, chain }.
17501 return DAG.getNode(ISD::MERGE_VALUES, dl, Op->getVTList(), Result, isValid,
17502 SDValue(Result.getNode(), 2));
17505 //gather(v1, mask, index, base, scale);
17506 SDValue Chain = Op.getOperand(0);
17507 SDValue Src = Op.getOperand(2);
17508 SDValue Base = Op.getOperand(3);
17509 SDValue Index = Op.getOperand(4);
17510 SDValue Mask = Op.getOperand(5);
17511 SDValue Scale = Op.getOperand(6);
17512 return getGatherNode(IntrData->Opc0, Op, DAG, Src, Mask, Base, Index, Scale, Chain,
17516 //scatter(base, mask, index, v1, scale);
17517 SDValue Chain = Op.getOperand(0);
17518 SDValue Base = Op.getOperand(2);
17519 SDValue Mask = Op.getOperand(3);
17520 SDValue Index = Op.getOperand(4);
17521 SDValue Src = Op.getOperand(5);
17522 SDValue Scale = Op.getOperand(6);
17523 return getScatterNode(IntrData->Opc0, Op, DAG, Src, Mask, Base, Index, Scale, Chain);
17526 SDValue Hint = Op.getOperand(6);
17528 if (dyn_cast<ConstantSDNode> (Hint) == nullptr ||
17529 (HintVal = dyn_cast<ConstantSDNode> (Hint)->getZExtValue()) > 1)
17530 llvm_unreachable("Wrong prefetch hint in intrinsic: should be 0 or 1");
17531 unsigned Opcode = (HintVal ? IntrData->Opc1 : IntrData->Opc0);
17532 SDValue Chain = Op.getOperand(0);
17533 SDValue Mask = Op.getOperand(2);
17534 SDValue Index = Op.getOperand(3);
17535 SDValue Base = Op.getOperand(4);
17536 SDValue Scale = Op.getOperand(5);
17537 return getPrefetchNode(Opcode, Op, DAG, Mask, Base, Index, Scale, Chain);
17539 // Read Time Stamp Counter (RDTSC) and Processor ID (RDTSCP).
17541 SmallVector<SDValue, 2> Results;
17542 getReadTimeStampCounter(Op.getNode(), dl, IntrData->Opc0, DAG, Subtarget, Results);
17543 return DAG.getMergeValues(Results, dl);
17545 // Read Performance Monitoring Counters.
17547 SmallVector<SDValue, 2> Results;
17548 getReadPerformanceCounter(Op.getNode(), dl, DAG, Subtarget, Results);
17549 return DAG.getMergeValues(Results, dl);
17551 // XTEST intrinsics.
17553 SDVTList VTs = DAG.getVTList(Op->getValueType(0), MVT::Other);
17554 SDValue InTrans = DAG.getNode(IntrData->Opc0, dl, VTs, Op.getOperand(0));
17555 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
17556 DAG.getConstant(X86::COND_NE, MVT::i8),
17558 SDValue Ret = DAG.getNode(ISD::ZERO_EXTEND, dl, Op->getValueType(0), SetCC);
17559 return DAG.getNode(ISD::MERGE_VALUES, dl, Op->getVTList(),
17560 Ret, SDValue(InTrans.getNode(), 1));
17564 SmallVector<SDValue, 2> Results;
17565 SDVTList CFVTs = DAG.getVTList(Op->getValueType(0), MVT::Other);
17566 SDVTList VTs = DAG.getVTList(Op.getOperand(3)->getValueType(0), MVT::Other);
17567 SDValue GenCF = DAG.getNode(X86ISD::ADD, dl, CFVTs, Op.getOperand(2),
17568 DAG.getConstant(-1, MVT::i8));
17569 SDValue Res = DAG.getNode(IntrData->Opc0, dl, VTs, Op.getOperand(3),
17570 Op.getOperand(4), GenCF.getValue(1));
17571 SDValue Store = DAG.getStore(Op.getOperand(0), dl, Res.getValue(0),
17572 Op.getOperand(5), MachinePointerInfo(),
17574 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
17575 DAG.getConstant(X86::COND_B, MVT::i8),
17577 Results.push_back(SetCC);
17578 Results.push_back(Store);
17579 return DAG.getMergeValues(Results, dl);
17584 SDValue X86TargetLowering::LowerRETURNADDR(SDValue Op,
17585 SelectionDAG &DAG) const {
17586 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
17587 MFI->setReturnAddressIsTaken(true);
17589 if (verifyReturnAddressArgumentIsConstant(Op, DAG))
17592 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
17594 EVT PtrVT = getPointerTy();
17597 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
17598 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
17599 DAG.getSubtarget().getRegisterInfo());
17600 SDValue Offset = DAG.getConstant(RegInfo->getSlotSize(), PtrVT);
17601 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
17602 DAG.getNode(ISD::ADD, dl, PtrVT,
17603 FrameAddr, Offset),
17604 MachinePointerInfo(), false, false, false, 0);
17607 // Just load the return address.
17608 SDValue RetAddrFI = getReturnAddressFrameIndex(DAG);
17609 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
17610 RetAddrFI, MachinePointerInfo(), false, false, false, 0);
17613 SDValue X86TargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {
17614 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
17615 MFI->setFrameAddressIsTaken(true);
17617 EVT VT = Op.getValueType();
17618 SDLoc dl(Op); // FIXME probably not meaningful
17619 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
17620 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
17621 DAG.getSubtarget().getRegisterInfo());
17622 unsigned FrameReg = RegInfo->getFrameRegister(DAG.getMachineFunction());
17623 assert(((FrameReg == X86::RBP && VT == MVT::i64) ||
17624 (FrameReg == X86::EBP && VT == MVT::i32)) &&
17625 "Invalid Frame Register!");
17626 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT);
17628 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr,
17629 MachinePointerInfo(),
17630 false, false, false, 0);
17634 // FIXME? Maybe this could be a TableGen attribute on some registers and
17635 // this table could be generated automatically from RegInfo.
17636 unsigned X86TargetLowering::getRegisterByName(const char* RegName,
17638 unsigned Reg = StringSwitch<unsigned>(RegName)
17639 .Case("esp", X86::ESP)
17640 .Case("rsp", X86::RSP)
17644 report_fatal_error("Invalid register name global variable");
17647 SDValue X86TargetLowering::LowerFRAME_TO_ARGS_OFFSET(SDValue Op,
17648 SelectionDAG &DAG) const {
17649 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
17650 DAG.getSubtarget().getRegisterInfo());
17651 return DAG.getIntPtrConstant(2 * RegInfo->getSlotSize());
17654 SDValue X86TargetLowering::LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const {
17655 SDValue Chain = Op.getOperand(0);
17656 SDValue Offset = Op.getOperand(1);
17657 SDValue Handler = Op.getOperand(2);
17660 EVT PtrVT = getPointerTy();
17661 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
17662 DAG.getSubtarget().getRegisterInfo());
17663 unsigned FrameReg = RegInfo->getFrameRegister(DAG.getMachineFunction());
17664 assert(((FrameReg == X86::RBP && PtrVT == MVT::i64) ||
17665 (FrameReg == X86::EBP && PtrVT == MVT::i32)) &&
17666 "Invalid Frame Register!");
17667 SDValue Frame = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, PtrVT);
17668 unsigned StoreAddrReg = (PtrVT == MVT::i64) ? X86::RCX : X86::ECX;
17670 SDValue StoreAddr = DAG.getNode(ISD::ADD, dl, PtrVT, Frame,
17671 DAG.getIntPtrConstant(RegInfo->getSlotSize()));
17672 StoreAddr = DAG.getNode(ISD::ADD, dl, PtrVT, StoreAddr, Offset);
17673 Chain = DAG.getStore(Chain, dl, Handler, StoreAddr, MachinePointerInfo(),
17675 Chain = DAG.getCopyToReg(Chain, dl, StoreAddrReg, StoreAddr);
17677 return DAG.getNode(X86ISD::EH_RETURN, dl, MVT::Other, Chain,
17678 DAG.getRegister(StoreAddrReg, PtrVT));
17681 SDValue X86TargetLowering::lowerEH_SJLJ_SETJMP(SDValue Op,
17682 SelectionDAG &DAG) const {
17684 return DAG.getNode(X86ISD::EH_SJLJ_SETJMP, DL,
17685 DAG.getVTList(MVT::i32, MVT::Other),
17686 Op.getOperand(0), Op.getOperand(1));
17689 SDValue X86TargetLowering::lowerEH_SJLJ_LONGJMP(SDValue Op,
17690 SelectionDAG &DAG) const {
17692 return DAG.getNode(X86ISD::EH_SJLJ_LONGJMP, DL, MVT::Other,
17693 Op.getOperand(0), Op.getOperand(1));
17696 static SDValue LowerADJUST_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) {
17697 return Op.getOperand(0);
17700 SDValue X86TargetLowering::LowerINIT_TRAMPOLINE(SDValue Op,
17701 SelectionDAG &DAG) const {
17702 SDValue Root = Op.getOperand(0);
17703 SDValue Trmp = Op.getOperand(1); // trampoline
17704 SDValue FPtr = Op.getOperand(2); // nested function
17705 SDValue Nest = Op.getOperand(3); // 'nest' parameter value
17708 const Value *TrmpAddr = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
17709 const TargetRegisterInfo *TRI = DAG.getSubtarget().getRegisterInfo();
17711 if (Subtarget->is64Bit()) {
17712 SDValue OutChains[6];
17714 // Large code-model.
17715 const unsigned char JMP64r = 0xFF; // 64-bit jmp through register opcode.
17716 const unsigned char MOV64ri = 0xB8; // X86::MOV64ri opcode.
17718 const unsigned char N86R10 = TRI->getEncodingValue(X86::R10) & 0x7;
17719 const unsigned char N86R11 = TRI->getEncodingValue(X86::R11) & 0x7;
17721 const unsigned char REX_WB = 0x40 | 0x08 | 0x01; // REX prefix
17723 // Load the pointer to the nested function into R11.
17724 unsigned OpCode = ((MOV64ri | N86R11) << 8) | REX_WB; // movabsq r11
17725 SDValue Addr = Trmp;
17726 OutChains[0] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
17727 Addr, MachinePointerInfo(TrmpAddr),
17730 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
17731 DAG.getConstant(2, MVT::i64));
17732 OutChains[1] = DAG.getStore(Root, dl, FPtr, Addr,
17733 MachinePointerInfo(TrmpAddr, 2),
17736 // Load the 'nest' parameter value into R10.
17737 // R10 is specified in X86CallingConv.td
17738 OpCode = ((MOV64ri | N86R10) << 8) | REX_WB; // movabsq r10
17739 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
17740 DAG.getConstant(10, MVT::i64));
17741 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
17742 Addr, MachinePointerInfo(TrmpAddr, 10),
17745 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
17746 DAG.getConstant(12, MVT::i64));
17747 OutChains[3] = DAG.getStore(Root, dl, Nest, Addr,
17748 MachinePointerInfo(TrmpAddr, 12),
17751 // Jump to the nested function.
17752 OpCode = (JMP64r << 8) | REX_WB; // jmpq *...
17753 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
17754 DAG.getConstant(20, MVT::i64));
17755 OutChains[4] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
17756 Addr, MachinePointerInfo(TrmpAddr, 20),
17759 unsigned char ModRM = N86R11 | (4 << 3) | (3 << 6); // ...r11
17760 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
17761 DAG.getConstant(22, MVT::i64));
17762 OutChains[5] = DAG.getStore(Root, dl, DAG.getConstant(ModRM, MVT::i8), Addr,
17763 MachinePointerInfo(TrmpAddr, 22),
17766 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains);
17768 const Function *Func =
17769 cast<Function>(cast<SrcValueSDNode>(Op.getOperand(5))->getValue());
17770 CallingConv::ID CC = Func->getCallingConv();
17775 llvm_unreachable("Unsupported calling convention");
17776 case CallingConv::C:
17777 case CallingConv::X86_StdCall: {
17778 // Pass 'nest' parameter in ECX.
17779 // Must be kept in sync with X86CallingConv.td
17780 NestReg = X86::ECX;
17782 // Check that ECX wasn't needed by an 'inreg' parameter.
17783 FunctionType *FTy = Func->getFunctionType();
17784 const AttributeSet &Attrs = Func->getAttributes();
17786 if (!Attrs.isEmpty() && !Func->isVarArg()) {
17787 unsigned InRegCount = 0;
17790 for (FunctionType::param_iterator I = FTy->param_begin(),
17791 E = FTy->param_end(); I != E; ++I, ++Idx)
17792 if (Attrs.hasAttribute(Idx, Attribute::InReg))
17793 // FIXME: should only count parameters that are lowered to integers.
17794 InRegCount += (TD->getTypeSizeInBits(*I) + 31) / 32;
17796 if (InRegCount > 2) {
17797 report_fatal_error("Nest register in use - reduce number of inreg"
17803 case CallingConv::X86_FastCall:
17804 case CallingConv::X86_ThisCall:
17805 case CallingConv::Fast:
17806 // Pass 'nest' parameter in EAX.
17807 // Must be kept in sync with X86CallingConv.td
17808 NestReg = X86::EAX;
17812 SDValue OutChains[4];
17813 SDValue Addr, Disp;
17815 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
17816 DAG.getConstant(10, MVT::i32));
17817 Disp = DAG.getNode(ISD::SUB, dl, MVT::i32, FPtr, Addr);
17819 // This is storing the opcode for MOV32ri.
17820 const unsigned char MOV32ri = 0xB8; // X86::MOV32ri's opcode byte.
17821 const unsigned char N86Reg = TRI->getEncodingValue(NestReg) & 0x7;
17822 OutChains[0] = DAG.getStore(Root, dl,
17823 DAG.getConstant(MOV32ri|N86Reg, MVT::i8),
17824 Trmp, MachinePointerInfo(TrmpAddr),
17827 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
17828 DAG.getConstant(1, MVT::i32));
17829 OutChains[1] = DAG.getStore(Root, dl, Nest, Addr,
17830 MachinePointerInfo(TrmpAddr, 1),
17833 const unsigned char JMP = 0xE9; // jmp <32bit dst> opcode.
17834 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
17835 DAG.getConstant(5, MVT::i32));
17836 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(JMP, MVT::i8), Addr,
17837 MachinePointerInfo(TrmpAddr, 5),
17840 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
17841 DAG.getConstant(6, MVT::i32));
17842 OutChains[3] = DAG.getStore(Root, dl, Disp, Addr,
17843 MachinePointerInfo(TrmpAddr, 6),
17846 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains);
17850 SDValue X86TargetLowering::LowerFLT_ROUNDS_(SDValue Op,
17851 SelectionDAG &DAG) const {
17853 The rounding mode is in bits 11:10 of FPSR, and has the following
17855 00 Round to nearest
17860 FLT_ROUNDS, on the other hand, expects the following:
17867 To perform the conversion, we do:
17868 (((((FPSR & 0x800) >> 11) | ((FPSR & 0x400) >> 9)) + 1) & 3)
17871 MachineFunction &MF = DAG.getMachineFunction();
17872 const TargetMachine &TM = MF.getTarget();
17873 const TargetFrameLowering &TFI = *TM.getSubtargetImpl()->getFrameLowering();
17874 unsigned StackAlignment = TFI.getStackAlignment();
17875 MVT VT = Op.getSimpleValueType();
17878 // Save FP Control Word to stack slot
17879 int SSFI = MF.getFrameInfo()->CreateStackObject(2, StackAlignment, false);
17880 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
17882 MachineMemOperand *MMO =
17883 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
17884 MachineMemOperand::MOStore, 2, 2);
17886 SDValue Ops[] = { DAG.getEntryNode(), StackSlot };
17887 SDValue Chain = DAG.getMemIntrinsicNode(X86ISD::FNSTCW16m, DL,
17888 DAG.getVTList(MVT::Other),
17889 Ops, MVT::i16, MMO);
17891 // Load FP Control Word from stack slot
17892 SDValue CWD = DAG.getLoad(MVT::i16, DL, Chain, StackSlot,
17893 MachinePointerInfo(), false, false, false, 0);
17895 // Transform as necessary
17897 DAG.getNode(ISD::SRL, DL, MVT::i16,
17898 DAG.getNode(ISD::AND, DL, MVT::i16,
17899 CWD, DAG.getConstant(0x800, MVT::i16)),
17900 DAG.getConstant(11, MVT::i8));
17902 DAG.getNode(ISD::SRL, DL, MVT::i16,
17903 DAG.getNode(ISD::AND, DL, MVT::i16,
17904 CWD, DAG.getConstant(0x400, MVT::i16)),
17905 DAG.getConstant(9, MVT::i8));
17908 DAG.getNode(ISD::AND, DL, MVT::i16,
17909 DAG.getNode(ISD::ADD, DL, MVT::i16,
17910 DAG.getNode(ISD::OR, DL, MVT::i16, CWD1, CWD2),
17911 DAG.getConstant(1, MVT::i16)),
17912 DAG.getConstant(3, MVT::i16));
17914 return DAG.getNode((VT.getSizeInBits() < 16 ?
17915 ISD::TRUNCATE : ISD::ZERO_EXTEND), DL, VT, RetVal);
17918 static SDValue LowerCTLZ(SDValue Op, SelectionDAG &DAG) {
17919 MVT VT = Op.getSimpleValueType();
17921 unsigned NumBits = VT.getSizeInBits();
17924 Op = Op.getOperand(0);
17925 if (VT == MVT::i8) {
17926 // Zero extend to i32 since there is not an i8 bsr.
17928 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
17931 // Issue a bsr (scan bits in reverse) which also sets EFLAGS.
17932 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
17933 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
17935 // If src is zero (i.e. bsr sets ZF), returns NumBits.
17938 DAG.getConstant(NumBits+NumBits-1, OpVT),
17939 DAG.getConstant(X86::COND_E, MVT::i8),
17942 Op = DAG.getNode(X86ISD::CMOV, dl, OpVT, Ops);
17944 // Finally xor with NumBits-1.
17945 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT));
17948 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
17952 static SDValue LowerCTLZ_ZERO_UNDEF(SDValue Op, SelectionDAG &DAG) {
17953 MVT VT = Op.getSimpleValueType();
17955 unsigned NumBits = VT.getSizeInBits();
17958 Op = Op.getOperand(0);
17959 if (VT == MVT::i8) {
17960 // Zero extend to i32 since there is not an i8 bsr.
17962 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
17965 // Issue a bsr (scan bits in reverse).
17966 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
17967 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
17969 // And xor with NumBits-1.
17970 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT));
17973 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
17977 static SDValue LowerCTTZ(SDValue Op, SelectionDAG &DAG) {
17978 MVT VT = Op.getSimpleValueType();
17979 unsigned NumBits = VT.getSizeInBits();
17981 Op = Op.getOperand(0);
17983 // Issue a bsf (scan bits forward) which also sets EFLAGS.
17984 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
17985 Op = DAG.getNode(X86ISD::BSF, dl, VTs, Op);
17987 // If src is zero (i.e. bsf sets ZF), returns NumBits.
17990 DAG.getConstant(NumBits, VT),
17991 DAG.getConstant(X86::COND_E, MVT::i8),
17994 return DAG.getNode(X86ISD::CMOV, dl, VT, Ops);
17997 // Lower256IntArith - Break a 256-bit integer operation into two new 128-bit
17998 // ones, and then concatenate the result back.
17999 static SDValue Lower256IntArith(SDValue Op, SelectionDAG &DAG) {
18000 MVT VT = Op.getSimpleValueType();
18002 assert(VT.is256BitVector() && VT.isInteger() &&
18003 "Unsupported value type for operation");
18005 unsigned NumElems = VT.getVectorNumElements();
18008 // Extract the LHS vectors
18009 SDValue LHS = Op.getOperand(0);
18010 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
18011 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
18013 // Extract the RHS vectors
18014 SDValue RHS = Op.getOperand(1);
18015 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, dl);
18016 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, dl);
18018 MVT EltVT = VT.getVectorElementType();
18019 MVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
18021 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
18022 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1),
18023 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2));
18026 static SDValue LowerADD(SDValue Op, SelectionDAG &DAG) {
18027 assert(Op.getSimpleValueType().is256BitVector() &&
18028 Op.getSimpleValueType().isInteger() &&
18029 "Only handle AVX 256-bit vector integer operation");
18030 return Lower256IntArith(Op, DAG);
18033 static SDValue LowerSUB(SDValue Op, SelectionDAG &DAG) {
18034 assert(Op.getSimpleValueType().is256BitVector() &&
18035 Op.getSimpleValueType().isInteger() &&
18036 "Only handle AVX 256-bit vector integer operation");
18037 return Lower256IntArith(Op, DAG);
18040 static SDValue LowerMUL(SDValue Op, const X86Subtarget *Subtarget,
18041 SelectionDAG &DAG) {
18043 MVT VT = Op.getSimpleValueType();
18045 // Decompose 256-bit ops into smaller 128-bit ops.
18046 if (VT.is256BitVector() && !Subtarget->hasInt256())
18047 return Lower256IntArith(Op, DAG);
18049 SDValue A = Op.getOperand(0);
18050 SDValue B = Op.getOperand(1);
18052 // Lower v4i32 mul as 2x shuffle, 2x pmuludq, 2x shuffle.
18053 if (VT == MVT::v4i32) {
18054 assert(Subtarget->hasSSE2() && !Subtarget->hasSSE41() &&
18055 "Should not custom lower when pmuldq is available!");
18057 // Extract the odd parts.
18058 static const int UnpackMask[] = { 1, -1, 3, -1 };
18059 SDValue Aodds = DAG.getVectorShuffle(VT, dl, A, A, UnpackMask);
18060 SDValue Bodds = DAG.getVectorShuffle(VT, dl, B, B, UnpackMask);
18062 // Multiply the even parts.
18063 SDValue Evens = DAG.getNode(X86ISD::PMULUDQ, dl, MVT::v2i64, A, B);
18064 // Now multiply odd parts.
18065 SDValue Odds = DAG.getNode(X86ISD::PMULUDQ, dl, MVT::v2i64, Aodds, Bodds);
18067 Evens = DAG.getNode(ISD::BITCAST, dl, VT, Evens);
18068 Odds = DAG.getNode(ISD::BITCAST, dl, VT, Odds);
18070 // Merge the two vectors back together with a shuffle. This expands into 2
18072 static const int ShufMask[] = { 0, 4, 2, 6 };
18073 return DAG.getVectorShuffle(VT, dl, Evens, Odds, ShufMask);
18076 assert((VT == MVT::v2i64 || VT == MVT::v4i64 || VT == MVT::v8i64) &&
18077 "Only know how to lower V2I64/V4I64/V8I64 multiply");
18079 // Ahi = psrlqi(a, 32);
18080 // Bhi = psrlqi(b, 32);
18082 // AloBlo = pmuludq(a, b);
18083 // AloBhi = pmuludq(a, Bhi);
18084 // AhiBlo = pmuludq(Ahi, b);
18086 // AloBhi = psllqi(AloBhi, 32);
18087 // AhiBlo = psllqi(AhiBlo, 32);
18088 // return AloBlo + AloBhi + AhiBlo;
18090 SDValue Ahi = getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, A, 32, DAG);
18091 SDValue Bhi = getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, B, 32, DAG);
18093 // Bit cast to 32-bit vectors for MULUDQ
18094 EVT MulVT = (VT == MVT::v2i64) ? MVT::v4i32 :
18095 (VT == MVT::v4i64) ? MVT::v8i32 : MVT::v16i32;
18096 A = DAG.getNode(ISD::BITCAST, dl, MulVT, A);
18097 B = DAG.getNode(ISD::BITCAST, dl, MulVT, B);
18098 Ahi = DAG.getNode(ISD::BITCAST, dl, MulVT, Ahi);
18099 Bhi = DAG.getNode(ISD::BITCAST, dl, MulVT, Bhi);
18101 SDValue AloBlo = DAG.getNode(X86ISD::PMULUDQ, dl, VT, A, B);
18102 SDValue AloBhi = DAG.getNode(X86ISD::PMULUDQ, dl, VT, A, Bhi);
18103 SDValue AhiBlo = DAG.getNode(X86ISD::PMULUDQ, dl, VT, Ahi, B);
18105 AloBhi = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, AloBhi, 32, DAG);
18106 AhiBlo = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, AhiBlo, 32, DAG);
18108 SDValue Res = DAG.getNode(ISD::ADD, dl, VT, AloBlo, AloBhi);
18109 return DAG.getNode(ISD::ADD, dl, VT, Res, AhiBlo);
18112 SDValue X86TargetLowering::LowerWin64_i128OP(SDValue Op, SelectionDAG &DAG) const {
18113 assert(Subtarget->isTargetWin64() && "Unexpected target");
18114 EVT VT = Op.getValueType();
18115 assert(VT.isInteger() && VT.getSizeInBits() == 128 &&
18116 "Unexpected return type for lowering");
18120 switch (Op->getOpcode()) {
18121 default: llvm_unreachable("Unexpected request for libcall!");
18122 case ISD::SDIV: isSigned = true; LC = RTLIB::SDIV_I128; break;
18123 case ISD::UDIV: isSigned = false; LC = RTLIB::UDIV_I128; break;
18124 case ISD::SREM: isSigned = true; LC = RTLIB::SREM_I128; break;
18125 case ISD::UREM: isSigned = false; LC = RTLIB::UREM_I128; break;
18126 case ISD::SDIVREM: isSigned = true; LC = RTLIB::SDIVREM_I128; break;
18127 case ISD::UDIVREM: isSigned = false; LC = RTLIB::UDIVREM_I128; break;
18131 SDValue InChain = DAG.getEntryNode();
18133 TargetLowering::ArgListTy Args;
18134 TargetLowering::ArgListEntry Entry;
18135 for (unsigned i = 0, e = Op->getNumOperands(); i != e; ++i) {
18136 EVT ArgVT = Op->getOperand(i).getValueType();
18137 assert(ArgVT.isInteger() && ArgVT.getSizeInBits() == 128 &&
18138 "Unexpected argument type for lowering");
18139 SDValue StackPtr = DAG.CreateStackTemporary(ArgVT, 16);
18140 Entry.Node = StackPtr;
18141 InChain = DAG.getStore(InChain, dl, Op->getOperand(i), StackPtr, MachinePointerInfo(),
18143 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
18144 Entry.Ty = PointerType::get(ArgTy,0);
18145 Entry.isSExt = false;
18146 Entry.isZExt = false;
18147 Args.push_back(Entry);
18150 SDValue Callee = DAG.getExternalSymbol(getLibcallName(LC),
18153 TargetLowering::CallLoweringInfo CLI(DAG);
18154 CLI.setDebugLoc(dl).setChain(InChain)
18155 .setCallee(getLibcallCallingConv(LC),
18156 static_cast<EVT>(MVT::v2i64).getTypeForEVT(*DAG.getContext()),
18157 Callee, std::move(Args), 0)
18158 .setInRegister().setSExtResult(isSigned).setZExtResult(!isSigned);
18160 std::pair<SDValue, SDValue> CallInfo = LowerCallTo(CLI);
18161 return DAG.getNode(ISD::BITCAST, dl, VT, CallInfo.first);
18164 static SDValue LowerMUL_LOHI(SDValue Op, const X86Subtarget *Subtarget,
18165 SelectionDAG &DAG) {
18166 SDValue Op0 = Op.getOperand(0), Op1 = Op.getOperand(1);
18167 EVT VT = Op0.getValueType();
18170 assert((VT == MVT::v4i32 && Subtarget->hasSSE2()) ||
18171 (VT == MVT::v8i32 && Subtarget->hasInt256()));
18173 // PMULxD operations multiply each even value (starting at 0) of LHS with
18174 // the related value of RHS and produce a widen result.
18175 // E.g., PMULUDQ <4 x i32> <a|b|c|d>, <4 x i32> <e|f|g|h>
18176 // => <2 x i64> <ae|cg>
18178 // In other word, to have all the results, we need to perform two PMULxD:
18179 // 1. one with the even values.
18180 // 2. one with the odd values.
18181 // To achieve #2, with need to place the odd values at an even position.
18183 // Place the odd value at an even position (basically, shift all values 1
18184 // step to the left):
18185 const int Mask[] = {1, -1, 3, -1, 5, -1, 7, -1};
18186 // <a|b|c|d> => <b|undef|d|undef>
18187 SDValue Odd0 = DAG.getVectorShuffle(VT, dl, Op0, Op0, Mask);
18188 // <e|f|g|h> => <f|undef|h|undef>
18189 SDValue Odd1 = DAG.getVectorShuffle(VT, dl, Op1, Op1, Mask);
18191 // Emit two multiplies, one for the lower 2 ints and one for the higher 2
18193 MVT MulVT = VT == MVT::v4i32 ? MVT::v2i64 : MVT::v4i64;
18194 bool IsSigned = Op->getOpcode() == ISD::SMUL_LOHI;
18196 (!IsSigned || !Subtarget->hasSSE41()) ? X86ISD::PMULUDQ : X86ISD::PMULDQ;
18197 // PMULUDQ <4 x i32> <a|b|c|d>, <4 x i32> <e|f|g|h>
18198 // => <2 x i64> <ae|cg>
18199 SDValue Mul1 = DAG.getNode(ISD::BITCAST, dl, VT,
18200 DAG.getNode(Opcode, dl, MulVT, Op0, Op1));
18201 // PMULUDQ <4 x i32> <b|undef|d|undef>, <4 x i32> <f|undef|h|undef>
18202 // => <2 x i64> <bf|dh>
18203 SDValue Mul2 = DAG.getNode(ISD::BITCAST, dl, VT,
18204 DAG.getNode(Opcode, dl, MulVT, Odd0, Odd1));
18206 // Shuffle it back into the right order.
18207 SDValue Highs, Lows;
18208 if (VT == MVT::v8i32) {
18209 const int HighMask[] = {1, 9, 3, 11, 5, 13, 7, 15};
18210 Highs = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, HighMask);
18211 const int LowMask[] = {0, 8, 2, 10, 4, 12, 6, 14};
18212 Lows = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, LowMask);
18214 const int HighMask[] = {1, 5, 3, 7};
18215 Highs = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, HighMask);
18216 const int LowMask[] = {0, 4, 2, 6};
18217 Lows = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, LowMask);
18220 // If we have a signed multiply but no PMULDQ fix up the high parts of a
18221 // unsigned multiply.
18222 if (IsSigned && !Subtarget->hasSSE41()) {
18224 DAG.getConstant(31, DAG.getTargetLoweringInfo().getShiftAmountTy(VT));
18225 SDValue T1 = DAG.getNode(ISD::AND, dl, VT,
18226 DAG.getNode(ISD::SRA, dl, VT, Op0, ShAmt), Op1);
18227 SDValue T2 = DAG.getNode(ISD::AND, dl, VT,
18228 DAG.getNode(ISD::SRA, dl, VT, Op1, ShAmt), Op0);
18230 SDValue Fixup = DAG.getNode(ISD::ADD, dl, VT, T1, T2);
18231 Highs = DAG.getNode(ISD::SUB, dl, VT, Highs, Fixup);
18234 // The first result of MUL_LOHI is actually the low value, followed by the
18236 SDValue Ops[] = {Lows, Highs};
18237 return DAG.getMergeValues(Ops, dl);
18240 static SDValue LowerScalarImmediateShift(SDValue Op, SelectionDAG &DAG,
18241 const X86Subtarget *Subtarget) {
18242 MVT VT = Op.getSimpleValueType();
18244 SDValue R = Op.getOperand(0);
18245 SDValue Amt = Op.getOperand(1);
18247 // Optimize shl/srl/sra with constant shift amount.
18248 if (auto *BVAmt = dyn_cast<BuildVectorSDNode>(Amt)) {
18249 if (auto *ShiftConst = BVAmt->getConstantSplatNode()) {
18250 uint64_t ShiftAmt = ShiftConst->getZExtValue();
18252 if (VT == MVT::v2i64 || VT == MVT::v4i32 || VT == MVT::v8i16 ||
18253 (Subtarget->hasInt256() &&
18254 (VT == MVT::v4i64 || VT == MVT::v8i32 || VT == MVT::v16i16)) ||
18255 (Subtarget->hasAVX512() &&
18256 (VT == MVT::v8i64 || VT == MVT::v16i32))) {
18257 if (Op.getOpcode() == ISD::SHL)
18258 return getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, R, ShiftAmt,
18260 if (Op.getOpcode() == ISD::SRL)
18261 return getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, R, ShiftAmt,
18263 if (Op.getOpcode() == ISD::SRA && VT != MVT::v2i64 && VT != MVT::v4i64)
18264 return getTargetVShiftByConstNode(X86ISD::VSRAI, dl, VT, R, ShiftAmt,
18268 if (VT == MVT::v16i8) {
18269 if (Op.getOpcode() == ISD::SHL) {
18270 // Make a large shift.
18271 SDValue SHL = getTargetVShiftByConstNode(X86ISD::VSHLI, dl,
18272 MVT::v8i16, R, ShiftAmt,
18274 SHL = DAG.getNode(ISD::BITCAST, dl, VT, SHL);
18275 // Zero out the rightmost bits.
18276 SmallVector<SDValue, 16> V(16,
18277 DAG.getConstant(uint8_t(-1U << ShiftAmt),
18279 return DAG.getNode(ISD::AND, dl, VT, SHL,
18280 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V));
18282 if (Op.getOpcode() == ISD::SRL) {
18283 // Make a large shift.
18284 SDValue SRL = getTargetVShiftByConstNode(X86ISD::VSRLI, dl,
18285 MVT::v8i16, R, ShiftAmt,
18287 SRL = DAG.getNode(ISD::BITCAST, dl, VT, SRL);
18288 // Zero out the leftmost bits.
18289 SmallVector<SDValue, 16> V(16,
18290 DAG.getConstant(uint8_t(-1U) >> ShiftAmt,
18292 return DAG.getNode(ISD::AND, dl, VT, SRL,
18293 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V));
18295 if (Op.getOpcode() == ISD::SRA) {
18296 if (ShiftAmt == 7) {
18297 // R s>> 7 === R s< 0
18298 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
18299 return DAG.getNode(X86ISD::PCMPGT, dl, VT, Zeros, R);
18302 // R s>> a === ((R u>> a) ^ m) - m
18303 SDValue Res = DAG.getNode(ISD::SRL, dl, VT, R, Amt);
18304 SmallVector<SDValue, 16> V(16, DAG.getConstant(128 >> ShiftAmt,
18306 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V);
18307 Res = DAG.getNode(ISD::XOR, dl, VT, Res, Mask);
18308 Res = DAG.getNode(ISD::SUB, dl, VT, Res, Mask);
18311 llvm_unreachable("Unknown shift opcode.");
18314 if (Subtarget->hasInt256() && VT == MVT::v32i8) {
18315 if (Op.getOpcode() == ISD::SHL) {
18316 // Make a large shift.
18317 SDValue SHL = getTargetVShiftByConstNode(X86ISD::VSHLI, dl,
18318 MVT::v16i16, R, ShiftAmt,
18320 SHL = DAG.getNode(ISD::BITCAST, dl, VT, SHL);
18321 // Zero out the rightmost bits.
18322 SmallVector<SDValue, 32> V(32,
18323 DAG.getConstant(uint8_t(-1U << ShiftAmt),
18325 return DAG.getNode(ISD::AND, dl, VT, SHL,
18326 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V));
18328 if (Op.getOpcode() == ISD::SRL) {
18329 // Make a large shift.
18330 SDValue SRL = getTargetVShiftByConstNode(X86ISD::VSRLI, dl,
18331 MVT::v16i16, R, ShiftAmt,
18333 SRL = DAG.getNode(ISD::BITCAST, dl, VT, SRL);
18334 // Zero out the leftmost bits.
18335 SmallVector<SDValue, 32> V(32,
18336 DAG.getConstant(uint8_t(-1U) >> ShiftAmt,
18338 return DAG.getNode(ISD::AND, dl, VT, SRL,
18339 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V));
18341 if (Op.getOpcode() == ISD::SRA) {
18342 if (ShiftAmt == 7) {
18343 // R s>> 7 === R s< 0
18344 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
18345 return DAG.getNode(X86ISD::PCMPGT, dl, VT, Zeros, R);
18348 // R s>> a === ((R u>> a) ^ m) - m
18349 SDValue Res = DAG.getNode(ISD::SRL, dl, VT, R, Amt);
18350 SmallVector<SDValue, 32> V(32, DAG.getConstant(128 >> ShiftAmt,
18352 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V);
18353 Res = DAG.getNode(ISD::XOR, dl, VT, Res, Mask);
18354 Res = DAG.getNode(ISD::SUB, dl, VT, Res, Mask);
18357 llvm_unreachable("Unknown shift opcode.");
18362 // Special case in 32-bit mode, where i64 is expanded into high and low parts.
18363 if (!Subtarget->is64Bit() &&
18364 (VT == MVT::v2i64 || (Subtarget->hasInt256() && VT == MVT::v4i64)) &&
18365 Amt.getOpcode() == ISD::BITCAST &&
18366 Amt.getOperand(0).getOpcode() == ISD::BUILD_VECTOR) {
18367 Amt = Amt.getOperand(0);
18368 unsigned Ratio = Amt.getSimpleValueType().getVectorNumElements() /
18369 VT.getVectorNumElements();
18370 unsigned RatioInLog2 = Log2_32_Ceil(Ratio);
18371 uint64_t ShiftAmt = 0;
18372 for (unsigned i = 0; i != Ratio; ++i) {
18373 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Amt.getOperand(i));
18377 ShiftAmt |= C->getZExtValue() << (i * (1 << (6 - RatioInLog2)));
18379 // Check remaining shift amounts.
18380 for (unsigned i = Ratio; i != Amt.getNumOperands(); i += Ratio) {
18381 uint64_t ShAmt = 0;
18382 for (unsigned j = 0; j != Ratio; ++j) {
18383 ConstantSDNode *C =
18384 dyn_cast<ConstantSDNode>(Amt.getOperand(i + j));
18388 ShAmt |= C->getZExtValue() << (j * (1 << (6 - RatioInLog2)));
18390 if (ShAmt != ShiftAmt)
18393 switch (Op.getOpcode()) {
18395 llvm_unreachable("Unknown shift opcode!");
18397 return getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, R, ShiftAmt,
18400 return getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, R, ShiftAmt,
18403 return getTargetVShiftByConstNode(X86ISD::VSRAI, dl, VT, R, ShiftAmt,
18411 static SDValue LowerScalarVariableShift(SDValue Op, SelectionDAG &DAG,
18412 const X86Subtarget* Subtarget) {
18413 MVT VT = Op.getSimpleValueType();
18415 SDValue R = Op.getOperand(0);
18416 SDValue Amt = Op.getOperand(1);
18418 if ((VT == MVT::v2i64 && Op.getOpcode() != ISD::SRA) ||
18419 VT == MVT::v4i32 || VT == MVT::v8i16 ||
18420 (Subtarget->hasInt256() &&
18421 ((VT == MVT::v4i64 && Op.getOpcode() != ISD::SRA) ||
18422 VT == MVT::v8i32 || VT == MVT::v16i16)) ||
18423 (Subtarget->hasAVX512() && (VT == MVT::v8i64 || VT == MVT::v16i32))) {
18425 EVT EltVT = VT.getVectorElementType();
18427 if (Amt.getOpcode() == ISD::BUILD_VECTOR) {
18428 unsigned NumElts = VT.getVectorNumElements();
18430 for (i = 0; i != NumElts; ++i) {
18431 if (Amt.getOperand(i).getOpcode() == ISD::UNDEF)
18435 for (j = i; j != NumElts; ++j) {
18436 SDValue Arg = Amt.getOperand(j);
18437 if (Arg.getOpcode() == ISD::UNDEF) continue;
18438 if (Arg != Amt.getOperand(i))
18441 if (i != NumElts && j == NumElts)
18442 BaseShAmt = Amt.getOperand(i);
18444 if (Amt.getOpcode() == ISD::EXTRACT_SUBVECTOR)
18445 Amt = Amt.getOperand(0);
18446 if (Amt.getOpcode() == ISD::VECTOR_SHUFFLE &&
18447 cast<ShuffleVectorSDNode>(Amt)->isSplat()) {
18448 SDValue InVec = Amt.getOperand(0);
18449 if (InVec.getOpcode() == ISD::BUILD_VECTOR) {
18450 unsigned NumElts = InVec.getValueType().getVectorNumElements();
18452 for (; i != NumElts; ++i) {
18453 SDValue Arg = InVec.getOperand(i);
18454 if (Arg.getOpcode() == ISD::UNDEF) continue;
18458 } else if (InVec.getOpcode() == ISD::INSERT_VECTOR_ELT) {
18459 if (ConstantSDNode *C =
18460 dyn_cast<ConstantSDNode>(InVec.getOperand(2))) {
18461 unsigned SplatIdx =
18462 cast<ShuffleVectorSDNode>(Amt)->getSplatIndex();
18463 if (C->getZExtValue() == SplatIdx)
18464 BaseShAmt = InVec.getOperand(1);
18467 if (!BaseShAmt.getNode())
18468 BaseShAmt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, Amt,
18469 DAG.getIntPtrConstant(0));
18473 if (BaseShAmt.getNode()) {
18474 if (EltVT.bitsGT(MVT::i32))
18475 BaseShAmt = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, BaseShAmt);
18476 else if (EltVT.bitsLT(MVT::i32))
18477 BaseShAmt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, BaseShAmt);
18479 switch (Op.getOpcode()) {
18481 llvm_unreachable("Unknown shift opcode!");
18483 switch (VT.SimpleTy) {
18484 default: return SDValue();
18493 return getTargetVShiftNode(X86ISD::VSHLI, dl, VT, R, BaseShAmt, DAG);
18496 switch (VT.SimpleTy) {
18497 default: return SDValue();
18504 return getTargetVShiftNode(X86ISD::VSRAI, dl, VT, R, BaseShAmt, DAG);
18507 switch (VT.SimpleTy) {
18508 default: return SDValue();
18517 return getTargetVShiftNode(X86ISD::VSRLI, dl, VT, R, BaseShAmt, DAG);
18523 // Special case in 32-bit mode, where i64 is expanded into high and low parts.
18524 if (!Subtarget->is64Bit() &&
18525 (VT == MVT::v2i64 || (Subtarget->hasInt256() && VT == MVT::v4i64) ||
18526 (Subtarget->hasAVX512() && VT == MVT::v8i64)) &&
18527 Amt.getOpcode() == ISD::BITCAST &&
18528 Amt.getOperand(0).getOpcode() == ISD::BUILD_VECTOR) {
18529 Amt = Amt.getOperand(0);
18530 unsigned Ratio = Amt.getSimpleValueType().getVectorNumElements() /
18531 VT.getVectorNumElements();
18532 std::vector<SDValue> Vals(Ratio);
18533 for (unsigned i = 0; i != Ratio; ++i)
18534 Vals[i] = Amt.getOperand(i);
18535 for (unsigned i = Ratio; i != Amt.getNumOperands(); i += Ratio) {
18536 for (unsigned j = 0; j != Ratio; ++j)
18537 if (Vals[j] != Amt.getOperand(i + j))
18540 switch (Op.getOpcode()) {
18542 llvm_unreachable("Unknown shift opcode!");
18544 return DAG.getNode(X86ISD::VSHL, dl, VT, R, Op.getOperand(1));
18546 return DAG.getNode(X86ISD::VSRL, dl, VT, R, Op.getOperand(1));
18548 return DAG.getNode(X86ISD::VSRA, dl, VT, R, Op.getOperand(1));
18555 static SDValue LowerShift(SDValue Op, const X86Subtarget* Subtarget,
18556 SelectionDAG &DAG) {
18557 MVT VT = Op.getSimpleValueType();
18559 SDValue R = Op.getOperand(0);
18560 SDValue Amt = Op.getOperand(1);
18563 assert(VT.isVector() && "Custom lowering only for vector shifts!");
18564 assert(Subtarget->hasSSE2() && "Only custom lower when we have SSE2!");
18566 V = LowerScalarImmediateShift(Op, DAG, Subtarget);
18570 V = LowerScalarVariableShift(Op, DAG, Subtarget);
18574 if (Subtarget->hasAVX512() && (VT == MVT::v16i32 || VT == MVT::v8i64))
18576 // AVX2 has VPSLLV/VPSRAV/VPSRLV.
18577 if (Subtarget->hasInt256()) {
18578 if (Op.getOpcode() == ISD::SRL &&
18579 (VT == MVT::v2i64 || VT == MVT::v4i32 ||
18580 VT == MVT::v4i64 || VT == MVT::v8i32))
18582 if (Op.getOpcode() == ISD::SHL &&
18583 (VT == MVT::v2i64 || VT == MVT::v4i32 ||
18584 VT == MVT::v4i64 || VT == MVT::v8i32))
18586 if (Op.getOpcode() == ISD::SRA && (VT == MVT::v4i32 || VT == MVT::v8i32))
18590 // If possible, lower this packed shift into a vector multiply instead of
18591 // expanding it into a sequence of scalar shifts.
18592 // Do this only if the vector shift count is a constant build_vector.
18593 if (Op.getOpcode() == ISD::SHL &&
18594 (VT == MVT::v8i16 || VT == MVT::v4i32 ||
18595 (Subtarget->hasInt256() && VT == MVT::v16i16)) &&
18596 ISD::isBuildVectorOfConstantSDNodes(Amt.getNode())) {
18597 SmallVector<SDValue, 8> Elts;
18598 EVT SVT = VT.getScalarType();
18599 unsigned SVTBits = SVT.getSizeInBits();
18600 const APInt &One = APInt(SVTBits, 1);
18601 unsigned NumElems = VT.getVectorNumElements();
18603 for (unsigned i=0; i !=NumElems; ++i) {
18604 SDValue Op = Amt->getOperand(i);
18605 if (Op->getOpcode() == ISD::UNDEF) {
18606 Elts.push_back(Op);
18610 ConstantSDNode *ND = cast<ConstantSDNode>(Op);
18611 const APInt &C = APInt(SVTBits, ND->getAPIntValue().getZExtValue());
18612 uint64_t ShAmt = C.getZExtValue();
18613 if (ShAmt >= SVTBits) {
18614 Elts.push_back(DAG.getUNDEF(SVT));
18617 Elts.push_back(DAG.getConstant(One.shl(ShAmt), SVT));
18619 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Elts);
18620 return DAG.getNode(ISD::MUL, dl, VT, R, BV);
18623 // Lower SHL with variable shift amount.
18624 if (VT == MVT::v4i32 && Op->getOpcode() == ISD::SHL) {
18625 Op = DAG.getNode(ISD::SHL, dl, VT, Amt, DAG.getConstant(23, VT));
18627 Op = DAG.getNode(ISD::ADD, dl, VT, Op, DAG.getConstant(0x3f800000U, VT));
18628 Op = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, Op);
18629 Op = DAG.getNode(ISD::FP_TO_SINT, dl, VT, Op);
18630 return DAG.getNode(ISD::MUL, dl, VT, Op, R);
18633 // If possible, lower this shift as a sequence of two shifts by
18634 // constant plus a MOVSS/MOVSD instead of scalarizing it.
18636 // (v4i32 (srl A, (build_vector < X, Y, Y, Y>)))
18638 // Could be rewritten as:
18639 // (v4i32 (MOVSS (srl A, <Y,Y,Y,Y>), (srl A, <X,X,X,X>)))
18641 // The advantage is that the two shifts from the example would be
18642 // lowered as X86ISD::VSRLI nodes. This would be cheaper than scalarizing
18643 // the vector shift into four scalar shifts plus four pairs of vector
18645 if ((VT == MVT::v8i16 || VT == MVT::v4i32) &&
18646 ISD::isBuildVectorOfConstantSDNodes(Amt.getNode())) {
18647 unsigned TargetOpcode = X86ISD::MOVSS;
18648 bool CanBeSimplified;
18649 // The splat value for the first packed shift (the 'X' from the example).
18650 SDValue Amt1 = Amt->getOperand(0);
18651 // The splat value for the second packed shift (the 'Y' from the example).
18652 SDValue Amt2 = (VT == MVT::v4i32) ? Amt->getOperand(1) :
18653 Amt->getOperand(2);
18655 // See if it is possible to replace this node with a sequence of
18656 // two shifts followed by a MOVSS/MOVSD
18657 if (VT == MVT::v4i32) {
18658 // Check if it is legal to use a MOVSS.
18659 CanBeSimplified = Amt2 == Amt->getOperand(2) &&
18660 Amt2 == Amt->getOperand(3);
18661 if (!CanBeSimplified) {
18662 // Otherwise, check if we can still simplify this node using a MOVSD.
18663 CanBeSimplified = Amt1 == Amt->getOperand(1) &&
18664 Amt->getOperand(2) == Amt->getOperand(3);
18665 TargetOpcode = X86ISD::MOVSD;
18666 Amt2 = Amt->getOperand(2);
18669 // Do similar checks for the case where the machine value type
18671 CanBeSimplified = Amt1 == Amt->getOperand(1);
18672 for (unsigned i=3; i != 8 && CanBeSimplified; ++i)
18673 CanBeSimplified = Amt2 == Amt->getOperand(i);
18675 if (!CanBeSimplified) {
18676 TargetOpcode = X86ISD::MOVSD;
18677 CanBeSimplified = true;
18678 Amt2 = Amt->getOperand(4);
18679 for (unsigned i=0; i != 4 && CanBeSimplified; ++i)
18680 CanBeSimplified = Amt1 == Amt->getOperand(i);
18681 for (unsigned j=4; j != 8 && CanBeSimplified; ++j)
18682 CanBeSimplified = Amt2 == Amt->getOperand(j);
18686 if (CanBeSimplified && isa<ConstantSDNode>(Amt1) &&
18687 isa<ConstantSDNode>(Amt2)) {
18688 // Replace this node with two shifts followed by a MOVSS/MOVSD.
18689 EVT CastVT = MVT::v4i32;
18691 DAG.getConstant(cast<ConstantSDNode>(Amt1)->getAPIntValue(), VT);
18692 SDValue Shift1 = DAG.getNode(Op->getOpcode(), dl, VT, R, Splat1);
18694 DAG.getConstant(cast<ConstantSDNode>(Amt2)->getAPIntValue(), VT);
18695 SDValue Shift2 = DAG.getNode(Op->getOpcode(), dl, VT, R, Splat2);
18696 if (TargetOpcode == X86ISD::MOVSD)
18697 CastVT = MVT::v2i64;
18698 SDValue BitCast1 = DAG.getNode(ISD::BITCAST, dl, CastVT, Shift1);
18699 SDValue BitCast2 = DAG.getNode(ISD::BITCAST, dl, CastVT, Shift2);
18700 SDValue Result = getTargetShuffleNode(TargetOpcode, dl, CastVT, BitCast2,
18702 return DAG.getNode(ISD::BITCAST, dl, VT, Result);
18706 if (VT == MVT::v16i8 && Op->getOpcode() == ISD::SHL) {
18707 assert(Subtarget->hasSSE2() && "Need SSE2 for pslli/pcmpeq.");
18710 Op = DAG.getNode(ISD::SHL, dl, VT, Amt, DAG.getConstant(5, VT));
18711 Op = DAG.getNode(ISD::BITCAST, dl, VT, Op);
18713 // Turn 'a' into a mask suitable for VSELECT
18714 SDValue VSelM = DAG.getConstant(0x80, VT);
18715 SDValue OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
18716 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
18718 SDValue CM1 = DAG.getConstant(0x0f, VT);
18719 SDValue CM2 = DAG.getConstant(0x3f, VT);
18721 // r = VSELECT(r, psllw(r & (char16)15, 4), a);
18722 SDValue M = DAG.getNode(ISD::AND, dl, VT, R, CM1);
18723 M = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, MVT::v8i16, M, 4, DAG);
18724 M = DAG.getNode(ISD::BITCAST, dl, VT, M);
18725 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel, M, R);
18728 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op);
18729 OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
18730 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
18732 // r = VSELECT(r, psllw(r & (char16)63, 2), a);
18733 M = DAG.getNode(ISD::AND, dl, VT, R, CM2);
18734 M = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, MVT::v8i16, M, 2, DAG);
18735 M = DAG.getNode(ISD::BITCAST, dl, VT, M);
18736 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel, M, R);
18739 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op);
18740 OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
18741 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
18743 // return VSELECT(r, r+r, a);
18744 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel,
18745 DAG.getNode(ISD::ADD, dl, VT, R, R), R);
18749 // It's worth extending once and using the v8i32 shifts for 16-bit types, but
18750 // the extra overheads to get from v16i8 to v8i32 make the existing SSE
18751 // solution better.
18752 if (Subtarget->hasInt256() && VT == MVT::v8i16) {
18753 MVT NewVT = VT == MVT::v8i16 ? MVT::v8i32 : MVT::v16i16;
18755 Op.getOpcode() == ISD::SRA ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
18756 R = DAG.getNode(ExtOpc, dl, NewVT, R);
18757 Amt = DAG.getNode(ISD::ANY_EXTEND, dl, NewVT, Amt);
18758 return DAG.getNode(ISD::TRUNCATE, dl, VT,
18759 DAG.getNode(Op.getOpcode(), dl, NewVT, R, Amt));
18762 // Decompose 256-bit shifts into smaller 128-bit shifts.
18763 if (VT.is256BitVector()) {
18764 unsigned NumElems = VT.getVectorNumElements();
18765 MVT EltVT = VT.getVectorElementType();
18766 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
18768 // Extract the two vectors
18769 SDValue V1 = Extract128BitVector(R, 0, DAG, dl);
18770 SDValue V2 = Extract128BitVector(R, NumElems/2, DAG, dl);
18772 // Recreate the shift amount vectors
18773 SDValue Amt1, Amt2;
18774 if (Amt.getOpcode() == ISD::BUILD_VECTOR) {
18775 // Constant shift amount
18776 SmallVector<SDValue, 4> Amt1Csts;
18777 SmallVector<SDValue, 4> Amt2Csts;
18778 for (unsigned i = 0; i != NumElems/2; ++i)
18779 Amt1Csts.push_back(Amt->getOperand(i));
18780 for (unsigned i = NumElems/2; i != NumElems; ++i)
18781 Amt2Csts.push_back(Amt->getOperand(i));
18783 Amt1 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, Amt1Csts);
18784 Amt2 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, Amt2Csts);
18786 // Variable shift amount
18787 Amt1 = Extract128BitVector(Amt, 0, DAG, dl);
18788 Amt2 = Extract128BitVector(Amt, NumElems/2, DAG, dl);
18791 // Issue new vector shifts for the smaller types
18792 V1 = DAG.getNode(Op.getOpcode(), dl, NewVT, V1, Amt1);
18793 V2 = DAG.getNode(Op.getOpcode(), dl, NewVT, V2, Amt2);
18795 // Concatenate the result back
18796 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, V1, V2);
18802 static SDValue LowerXALUO(SDValue Op, SelectionDAG &DAG) {
18803 // Lower the "add/sub/mul with overflow" instruction into a regular ins plus
18804 // a "setcc" instruction that checks the overflow flag. The "brcond" lowering
18805 // looks for this combo and may remove the "setcc" instruction if the "setcc"
18806 // has only one use.
18807 SDNode *N = Op.getNode();
18808 SDValue LHS = N->getOperand(0);
18809 SDValue RHS = N->getOperand(1);
18810 unsigned BaseOp = 0;
18813 switch (Op.getOpcode()) {
18814 default: llvm_unreachable("Unknown ovf instruction!");
18816 // A subtract of one will be selected as a INC. Note that INC doesn't
18817 // set CF, so we can't do this for UADDO.
18818 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
18820 BaseOp = X86ISD::INC;
18821 Cond = X86::COND_O;
18824 BaseOp = X86ISD::ADD;
18825 Cond = X86::COND_O;
18828 BaseOp = X86ISD::ADD;
18829 Cond = X86::COND_B;
18832 // A subtract of one will be selected as a DEC. Note that DEC doesn't
18833 // set CF, so we can't do this for USUBO.
18834 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
18836 BaseOp = X86ISD::DEC;
18837 Cond = X86::COND_O;
18840 BaseOp = X86ISD::SUB;
18841 Cond = X86::COND_O;
18844 BaseOp = X86ISD::SUB;
18845 Cond = X86::COND_B;
18848 BaseOp = N->getValueType(0) == MVT::i8 ? X86ISD::SMUL8 : X86ISD::SMUL;
18849 Cond = X86::COND_O;
18851 case ISD::UMULO: { // i64, i8 = umulo lhs, rhs --> i64, i64, i32 umul lhs,rhs
18852 if (N->getValueType(0) == MVT::i8) {
18853 BaseOp = X86ISD::UMUL8;
18854 Cond = X86::COND_O;
18857 SDVTList VTs = DAG.getVTList(N->getValueType(0), N->getValueType(0),
18859 SDValue Sum = DAG.getNode(X86ISD::UMUL, DL, VTs, LHS, RHS);
18862 DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
18863 DAG.getConstant(X86::COND_O, MVT::i32),
18864 SDValue(Sum.getNode(), 2));
18866 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
18870 // Also sets EFLAGS.
18871 SDVTList VTs = DAG.getVTList(N->getValueType(0), MVT::i32);
18872 SDValue Sum = DAG.getNode(BaseOp, DL, VTs, LHS, RHS);
18875 DAG.getNode(X86ISD::SETCC, DL, N->getValueType(1),
18876 DAG.getConstant(Cond, MVT::i32),
18877 SDValue(Sum.getNode(), 1));
18879 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
18882 // Sign extension of the low part of vector elements. This may be used either
18883 // when sign extend instructions are not available or if the vector element
18884 // sizes already match the sign-extended size. If the vector elements are in
18885 // their pre-extended size and sign extend instructions are available, that will
18886 // be handled by LowerSIGN_EXTEND.
18887 SDValue X86TargetLowering::LowerSIGN_EXTEND_INREG(SDValue Op,
18888 SelectionDAG &DAG) const {
18890 EVT ExtraVT = cast<VTSDNode>(Op.getOperand(1))->getVT();
18891 MVT VT = Op.getSimpleValueType();
18893 if (!Subtarget->hasSSE2() || !VT.isVector())
18896 unsigned BitsDiff = VT.getScalarType().getSizeInBits() -
18897 ExtraVT.getScalarType().getSizeInBits();
18899 switch (VT.SimpleTy) {
18900 default: return SDValue();
18903 if (!Subtarget->hasFp256())
18905 if (!Subtarget->hasInt256()) {
18906 // needs to be split
18907 unsigned NumElems = VT.getVectorNumElements();
18909 // Extract the LHS vectors
18910 SDValue LHS = Op.getOperand(0);
18911 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
18912 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
18914 MVT EltVT = VT.getVectorElementType();
18915 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
18917 EVT ExtraEltVT = ExtraVT.getVectorElementType();
18918 unsigned ExtraNumElems = ExtraVT.getVectorNumElements();
18919 ExtraVT = EVT::getVectorVT(*DAG.getContext(), ExtraEltVT,
18921 SDValue Extra = DAG.getValueType(ExtraVT);
18923 LHS1 = DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, Extra);
18924 LHS2 = DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, Extra);
18926 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, LHS1, LHS2);
18931 SDValue Op0 = Op.getOperand(0);
18933 // This is a sign extension of some low part of vector elements without
18934 // changing the size of the vector elements themselves:
18935 // Shift-Left + Shift-Right-Algebraic.
18936 SDValue Shl = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, Op0,
18938 return getTargetVShiftByConstNode(X86ISD::VSRAI, dl, VT, Shl, BitsDiff,
18944 /// Returns true if the operand type is exactly twice the native width, and
18945 /// the corresponding cmpxchg8b or cmpxchg16b instruction is available.
18946 /// Used to know whether to use cmpxchg8/16b when expanding atomic operations
18947 /// (otherwise we leave them alone to become __sync_fetch_and_... calls).
18948 bool X86TargetLowering::needsCmpXchgNb(const Type *MemType) const {
18949 const X86Subtarget &Subtarget =
18950 getTargetMachine().getSubtarget<X86Subtarget>();
18951 unsigned OpWidth = MemType->getPrimitiveSizeInBits();
18954 return !Subtarget.is64Bit(); // FIXME this should be Subtarget.hasCmpxchg8b
18955 else if (OpWidth == 128)
18956 return Subtarget.hasCmpxchg16b();
18961 bool X86TargetLowering::shouldExpandAtomicStoreInIR(StoreInst *SI) const {
18962 return needsCmpXchgNb(SI->getValueOperand()->getType());
18965 // Note: this turns large loads into lock cmpxchg8b/16b.
18966 // FIXME: On 32 bits x86, fild/movq might be faster than lock cmpxchg8b.
18967 bool X86TargetLowering::shouldExpandAtomicLoadInIR(LoadInst *LI) const {
18968 auto PTy = cast<PointerType>(LI->getPointerOperand()->getType());
18969 return needsCmpXchgNb(PTy->getElementType());
18972 bool X86TargetLowering::shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const {
18973 const X86Subtarget &Subtarget =
18974 getTargetMachine().getSubtarget<X86Subtarget>();
18975 unsigned NativeWidth = Subtarget.is64Bit() ? 64 : 32;
18976 const Type *MemType = AI->getType();
18978 // If the operand is too big, we must see if cmpxchg8/16b is available
18979 // and default to library calls otherwise.
18980 if (MemType->getPrimitiveSizeInBits() > NativeWidth)
18981 return needsCmpXchgNb(MemType);
18983 AtomicRMWInst::BinOp Op = AI->getOperation();
18986 llvm_unreachable("Unknown atomic operation");
18987 case AtomicRMWInst::Xchg:
18988 case AtomicRMWInst::Add:
18989 case AtomicRMWInst::Sub:
18990 // It's better to use xadd, xsub or xchg for these in all cases.
18992 case AtomicRMWInst::Or:
18993 case AtomicRMWInst::And:
18994 case AtomicRMWInst::Xor:
18995 // If the atomicrmw's result isn't actually used, we can just add a "lock"
18996 // prefix to a normal instruction for these operations.
18997 return !AI->use_empty();
18998 case AtomicRMWInst::Nand:
18999 case AtomicRMWInst::Max:
19000 case AtomicRMWInst::Min:
19001 case AtomicRMWInst::UMax:
19002 case AtomicRMWInst::UMin:
19003 // These always require a non-trivial set of data operations on x86. We must
19004 // use a cmpxchg loop.
19009 static bool hasMFENCE(const X86Subtarget& Subtarget) {
19010 // Use mfence if we have SSE2 or we're on x86-64 (even if we asked for
19011 // no-sse2). There isn't any reason to disable it if the target processor
19013 return Subtarget.hasSSE2() || Subtarget.is64Bit();
19017 X86TargetLowering::lowerIdempotentRMWIntoFencedLoad(AtomicRMWInst *AI) const {
19018 const X86Subtarget &Subtarget =
19019 getTargetMachine().getSubtarget<X86Subtarget>();
19020 unsigned NativeWidth = Subtarget.is64Bit() ? 64 : 32;
19021 const Type *MemType = AI->getType();
19022 // Accesses larger than the native width are turned into cmpxchg/libcalls, so
19023 // there is no benefit in turning such RMWs into loads, and it is actually
19024 // harmful as it introduces a mfence.
19025 if (MemType->getPrimitiveSizeInBits() > NativeWidth)
19028 auto Builder = IRBuilder<>(AI);
19029 Module *M = Builder.GetInsertBlock()->getParent()->getParent();
19030 auto SynchScope = AI->getSynchScope();
19031 // We must restrict the ordering to avoid generating loads with Release or
19032 // ReleaseAcquire orderings.
19033 auto Order = AtomicCmpXchgInst::getStrongestFailureOrdering(AI->getOrdering());
19034 auto Ptr = AI->getPointerOperand();
19036 // Before the load we need a fence. Here is an example lifted from
19037 // http://www.hpl.hp.com/techreports/2012/HPL-2012-68.pdf showing why a fence
19040 // x.store(1, relaxed);
19041 // r1 = y.fetch_add(0, release);
19043 // y.fetch_add(42, acquire);
19044 // r2 = x.load(relaxed);
19045 // r1 = r2 = 0 is impossible, but becomes possible if the idempotent rmw is
19046 // lowered to just a load without a fence. A mfence flushes the store buffer,
19047 // making the optimization clearly correct.
19048 // FIXME: it is required if isAtLeastRelease(Order) but it is not clear
19049 // otherwise, we might be able to be more agressive on relaxed idempotent
19050 // rmw. In practice, they do not look useful, so we don't try to be
19051 // especially clever.
19052 if (SynchScope == SingleThread) {
19053 // FIXME: we could just insert an X86ISD::MEMBARRIER here, except we are at
19054 // the IR level, so we must wrap it in an intrinsic.
19056 } else if (hasMFENCE(Subtarget)) {
19057 Function *MFence = llvm::Intrinsic::getDeclaration(M,
19058 Intrinsic::x86_sse2_mfence);
19059 Builder.CreateCall(MFence);
19061 // FIXME: it might make sense to use a locked operation here but on a
19062 // different cache-line to prevent cache-line bouncing. In practice it
19063 // is probably a small win, and x86 processors without mfence are rare
19064 // enough that we do not bother.
19068 // Finally we can emit the atomic load.
19069 LoadInst *Loaded = Builder.CreateAlignedLoad(Ptr,
19070 AI->getType()->getPrimitiveSizeInBits());
19071 Loaded->setAtomic(Order, SynchScope);
19072 AI->replaceAllUsesWith(Loaded);
19073 AI->eraseFromParent();
19077 static SDValue LowerATOMIC_FENCE(SDValue Op, const X86Subtarget *Subtarget,
19078 SelectionDAG &DAG) {
19080 AtomicOrdering FenceOrdering = static_cast<AtomicOrdering>(
19081 cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue());
19082 SynchronizationScope FenceScope = static_cast<SynchronizationScope>(
19083 cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue());
19085 // The only fence that needs an instruction is a sequentially-consistent
19086 // cross-thread fence.
19087 if (FenceOrdering == SequentiallyConsistent && FenceScope == CrossThread) {
19088 if (hasMFENCE(*Subtarget))
19089 return DAG.getNode(X86ISD::MFENCE, dl, MVT::Other, Op.getOperand(0));
19091 SDValue Chain = Op.getOperand(0);
19092 SDValue Zero = DAG.getConstant(0, MVT::i32);
19094 DAG.getRegister(X86::ESP, MVT::i32), // Base
19095 DAG.getTargetConstant(1, MVT::i8), // Scale
19096 DAG.getRegister(0, MVT::i32), // Index
19097 DAG.getTargetConstant(0, MVT::i32), // Disp
19098 DAG.getRegister(0, MVT::i32), // Segment.
19102 SDNode *Res = DAG.getMachineNode(X86::OR32mrLocked, dl, MVT::Other, Ops);
19103 return SDValue(Res, 0);
19106 // MEMBARRIER is a compiler barrier; it codegens to a no-op.
19107 return DAG.getNode(X86ISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0));
19110 static SDValue LowerCMP_SWAP(SDValue Op, const X86Subtarget *Subtarget,
19111 SelectionDAG &DAG) {
19112 MVT T = Op.getSimpleValueType();
19116 switch(T.SimpleTy) {
19117 default: llvm_unreachable("Invalid value type!");
19118 case MVT::i8: Reg = X86::AL; size = 1; break;
19119 case MVT::i16: Reg = X86::AX; size = 2; break;
19120 case MVT::i32: Reg = X86::EAX; size = 4; break;
19122 assert(Subtarget->is64Bit() && "Node not type legal!");
19123 Reg = X86::RAX; size = 8;
19126 SDValue cpIn = DAG.getCopyToReg(Op.getOperand(0), DL, Reg,
19127 Op.getOperand(2), SDValue());
19128 SDValue Ops[] = { cpIn.getValue(0),
19131 DAG.getTargetConstant(size, MVT::i8),
19132 cpIn.getValue(1) };
19133 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
19134 MachineMemOperand *MMO = cast<AtomicSDNode>(Op)->getMemOperand();
19135 SDValue Result = DAG.getMemIntrinsicNode(X86ISD::LCMPXCHG_DAG, DL, Tys,
19139 DAG.getCopyFromReg(Result.getValue(0), DL, Reg, T, Result.getValue(1));
19140 SDValue EFLAGS = DAG.getCopyFromReg(cpOut.getValue(1), DL, X86::EFLAGS,
19141 MVT::i32, cpOut.getValue(2));
19142 SDValue Success = DAG.getNode(X86ISD::SETCC, DL, Op->getValueType(1),
19143 DAG.getConstant(X86::COND_E, MVT::i8), EFLAGS);
19145 DAG.ReplaceAllUsesOfValueWith(Op.getValue(0), cpOut);
19146 DAG.ReplaceAllUsesOfValueWith(Op.getValue(1), Success);
19147 DAG.ReplaceAllUsesOfValueWith(Op.getValue(2), EFLAGS.getValue(1));
19151 static SDValue LowerBITCAST(SDValue Op, const X86Subtarget *Subtarget,
19152 SelectionDAG &DAG) {
19153 MVT SrcVT = Op.getOperand(0).getSimpleValueType();
19154 MVT DstVT = Op.getSimpleValueType();
19156 if (SrcVT == MVT::v2i32 || SrcVT == MVT::v4i16 || SrcVT == MVT::v8i8) {
19157 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
19158 if (DstVT != MVT::f64)
19159 // This conversion needs to be expanded.
19162 SDValue InVec = Op->getOperand(0);
19164 unsigned NumElts = SrcVT.getVectorNumElements();
19165 EVT SVT = SrcVT.getVectorElementType();
19167 // Widen the vector in input in the case of MVT::v2i32.
19168 // Example: from MVT::v2i32 to MVT::v4i32.
19169 SmallVector<SDValue, 16> Elts;
19170 for (unsigned i = 0, e = NumElts; i != e; ++i)
19171 Elts.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, SVT, InVec,
19172 DAG.getIntPtrConstant(i)));
19174 // Explicitly mark the extra elements as Undef.
19175 SDValue Undef = DAG.getUNDEF(SVT);
19176 for (unsigned i = NumElts, e = NumElts * 2; i != e; ++i)
19177 Elts.push_back(Undef);
19179 EVT NewVT = EVT::getVectorVT(*DAG.getContext(), SVT, NumElts * 2);
19180 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, Elts);
19181 SDValue ToV2F64 = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, BV);
19182 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, ToV2F64,
19183 DAG.getIntPtrConstant(0));
19186 assert(Subtarget->is64Bit() && !Subtarget->hasSSE2() &&
19187 Subtarget->hasMMX() && "Unexpected custom BITCAST");
19188 assert((DstVT == MVT::i64 ||
19189 (DstVT.isVector() && DstVT.getSizeInBits()==64)) &&
19190 "Unexpected custom BITCAST");
19191 // i64 <=> MMX conversions are Legal.
19192 if (SrcVT==MVT::i64 && DstVT.isVector())
19194 if (DstVT==MVT::i64 && SrcVT.isVector())
19196 // MMX <=> MMX conversions are Legal.
19197 if (SrcVT.isVector() && DstVT.isVector())
19199 // All other conversions need to be expanded.
19203 static SDValue LowerLOAD_SUB(SDValue Op, SelectionDAG &DAG) {
19204 SDNode *Node = Op.getNode();
19206 EVT T = Node->getValueType(0);
19207 SDValue negOp = DAG.getNode(ISD::SUB, dl, T,
19208 DAG.getConstant(0, T), Node->getOperand(2));
19209 return DAG.getAtomic(ISD::ATOMIC_LOAD_ADD, dl,
19210 cast<AtomicSDNode>(Node)->getMemoryVT(),
19211 Node->getOperand(0),
19212 Node->getOperand(1), negOp,
19213 cast<AtomicSDNode>(Node)->getMemOperand(),
19214 cast<AtomicSDNode>(Node)->getOrdering(),
19215 cast<AtomicSDNode>(Node)->getSynchScope());
19218 static SDValue LowerATOMIC_STORE(SDValue Op, SelectionDAG &DAG) {
19219 SDNode *Node = Op.getNode();
19221 EVT VT = cast<AtomicSDNode>(Node)->getMemoryVT();
19223 // Convert seq_cst store -> xchg
19224 // Convert wide store -> swap (-> cmpxchg8b/cmpxchg16b)
19225 // FIXME: On 32-bit, store -> fist or movq would be more efficient
19226 // (The only way to get a 16-byte store is cmpxchg16b)
19227 // FIXME: 16-byte ATOMIC_SWAP isn't actually hooked up at the moment.
19228 if (cast<AtomicSDNode>(Node)->getOrdering() == SequentiallyConsistent ||
19229 !DAG.getTargetLoweringInfo().isTypeLegal(VT)) {
19230 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_SWAP, dl,
19231 cast<AtomicSDNode>(Node)->getMemoryVT(),
19232 Node->getOperand(0),
19233 Node->getOperand(1), Node->getOperand(2),
19234 cast<AtomicSDNode>(Node)->getMemOperand(),
19235 cast<AtomicSDNode>(Node)->getOrdering(),
19236 cast<AtomicSDNode>(Node)->getSynchScope());
19237 return Swap.getValue(1);
19239 // Other atomic stores have a simple pattern.
19243 static SDValue LowerADDC_ADDE_SUBC_SUBE(SDValue Op, SelectionDAG &DAG) {
19244 EVT VT = Op.getNode()->getSimpleValueType(0);
19246 // Let legalize expand this if it isn't a legal type yet.
19247 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
19250 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
19253 bool ExtraOp = false;
19254 switch (Op.getOpcode()) {
19255 default: llvm_unreachable("Invalid code");
19256 case ISD::ADDC: Opc = X86ISD::ADD; break;
19257 case ISD::ADDE: Opc = X86ISD::ADC; ExtraOp = true; break;
19258 case ISD::SUBC: Opc = X86ISD::SUB; break;
19259 case ISD::SUBE: Opc = X86ISD::SBB; ExtraOp = true; break;
19263 return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0),
19265 return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0),
19266 Op.getOperand(1), Op.getOperand(2));
19269 static SDValue LowerFSINCOS(SDValue Op, const X86Subtarget *Subtarget,
19270 SelectionDAG &DAG) {
19271 assert(Subtarget->isTargetDarwin() && Subtarget->is64Bit());
19273 // For MacOSX, we want to call an alternative entry point: __sincos_stret,
19274 // which returns the values as { float, float } (in XMM0) or
19275 // { double, double } (which is returned in XMM0, XMM1).
19277 SDValue Arg = Op.getOperand(0);
19278 EVT ArgVT = Arg.getValueType();
19279 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
19281 TargetLowering::ArgListTy Args;
19282 TargetLowering::ArgListEntry Entry;
19286 Entry.isSExt = false;
19287 Entry.isZExt = false;
19288 Args.push_back(Entry);
19290 bool isF64 = ArgVT == MVT::f64;
19291 // Only optimize x86_64 for now. i386 is a bit messy. For f32,
19292 // the small struct {f32, f32} is returned in (eax, edx). For f64,
19293 // the results are returned via SRet in memory.
19294 const char *LibcallName = isF64 ? "__sincos_stret" : "__sincosf_stret";
19295 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
19296 SDValue Callee = DAG.getExternalSymbol(LibcallName, TLI.getPointerTy());
19298 Type *RetTy = isF64
19299 ? (Type*)StructType::get(ArgTy, ArgTy, nullptr)
19300 : (Type*)VectorType::get(ArgTy, 4);
19302 TargetLowering::CallLoweringInfo CLI(DAG);
19303 CLI.setDebugLoc(dl).setChain(DAG.getEntryNode())
19304 .setCallee(CallingConv::C, RetTy, Callee, std::move(Args), 0);
19306 std::pair<SDValue, SDValue> CallResult = TLI.LowerCallTo(CLI);
19309 // Returned in xmm0 and xmm1.
19310 return CallResult.first;
19312 // Returned in bits 0:31 and 32:64 xmm0.
19313 SDValue SinVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ArgVT,
19314 CallResult.first, DAG.getIntPtrConstant(0));
19315 SDValue CosVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ArgVT,
19316 CallResult.first, DAG.getIntPtrConstant(1));
19317 SDVTList Tys = DAG.getVTList(ArgVT, ArgVT);
19318 return DAG.getNode(ISD::MERGE_VALUES, dl, Tys, SinVal, CosVal);
19321 /// LowerOperation - Provide custom lowering hooks for some operations.
19323 SDValue X86TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
19324 switch (Op.getOpcode()) {
19325 default: llvm_unreachable("Should not custom lower this!");
19326 case ISD::SIGN_EXTEND_INREG: return LowerSIGN_EXTEND_INREG(Op,DAG);
19327 case ISD::ATOMIC_FENCE: return LowerATOMIC_FENCE(Op, Subtarget, DAG);
19328 case ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS:
19329 return LowerCMP_SWAP(Op, Subtarget, DAG);
19330 case ISD::ATOMIC_LOAD_SUB: return LowerLOAD_SUB(Op,DAG);
19331 case ISD::ATOMIC_STORE: return LowerATOMIC_STORE(Op,DAG);
19332 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
19333 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG);
19334 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
19335 case ISD::VSELECT: return LowerVSELECT(Op, DAG);
19336 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
19337 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG);
19338 case ISD::EXTRACT_SUBVECTOR: return LowerEXTRACT_SUBVECTOR(Op,Subtarget,DAG);
19339 case ISD::INSERT_SUBVECTOR: return LowerINSERT_SUBVECTOR(Op, Subtarget,DAG);
19340 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
19341 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
19342 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
19343 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
19344 case ISD::ExternalSymbol: return LowerExternalSymbol(Op, DAG);
19345 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
19346 case ISD::SHL_PARTS:
19347 case ISD::SRA_PARTS:
19348 case ISD::SRL_PARTS: return LowerShiftParts(Op, DAG);
19349 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG);
19350 case ISD::UINT_TO_FP: return LowerUINT_TO_FP(Op, DAG);
19351 case ISD::TRUNCATE: return LowerTRUNCATE(Op, DAG);
19352 case ISD::ZERO_EXTEND: return LowerZERO_EXTEND(Op, Subtarget, DAG);
19353 case ISD::SIGN_EXTEND: return LowerSIGN_EXTEND(Op, Subtarget, DAG);
19354 case ISD::ANY_EXTEND: return LowerANY_EXTEND(Op, Subtarget, DAG);
19355 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG);
19356 case ISD::FP_TO_UINT: return LowerFP_TO_UINT(Op, DAG);
19357 case ISD::FP_EXTEND: return LowerFP_EXTEND(Op, DAG);
19358 case ISD::LOAD: return LowerExtendedLoad(Op, Subtarget, DAG);
19360 case ISD::FNEG: return LowerFABSorFNEG(Op, DAG);
19361 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG);
19362 case ISD::FGETSIGN: return LowerFGETSIGN(Op, DAG);
19363 case ISD::SETCC: return LowerSETCC(Op, DAG);
19364 case ISD::SELECT: return LowerSELECT(Op, DAG);
19365 case ISD::BRCOND: return LowerBRCOND(Op, DAG);
19366 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
19367 case ISD::VASTART: return LowerVASTART(Op, DAG);
19368 case ISD::VAARG: return LowerVAARG(Op, DAG);
19369 case ISD::VACOPY: return LowerVACOPY(Op, Subtarget, DAG);
19370 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, Subtarget, DAG);
19371 case ISD::INTRINSIC_VOID:
19372 case ISD::INTRINSIC_W_CHAIN: return LowerINTRINSIC_W_CHAIN(Op, Subtarget, DAG);
19373 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
19374 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
19375 case ISD::FRAME_TO_ARGS_OFFSET:
19376 return LowerFRAME_TO_ARGS_OFFSET(Op, DAG);
19377 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
19378 case ISD::EH_RETURN: return LowerEH_RETURN(Op, DAG);
19379 case ISD::EH_SJLJ_SETJMP: return lowerEH_SJLJ_SETJMP(Op, DAG);
19380 case ISD::EH_SJLJ_LONGJMP: return lowerEH_SJLJ_LONGJMP(Op, DAG);
19381 case ISD::INIT_TRAMPOLINE: return LowerINIT_TRAMPOLINE(Op, DAG);
19382 case ISD::ADJUST_TRAMPOLINE: return LowerADJUST_TRAMPOLINE(Op, DAG);
19383 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
19384 case ISD::CTLZ: return LowerCTLZ(Op, DAG);
19385 case ISD::CTLZ_ZERO_UNDEF: return LowerCTLZ_ZERO_UNDEF(Op, DAG);
19386 case ISD::CTTZ: return LowerCTTZ(Op, DAG);
19387 case ISD::MUL: return LowerMUL(Op, Subtarget, DAG);
19388 case ISD::UMUL_LOHI:
19389 case ISD::SMUL_LOHI: return LowerMUL_LOHI(Op, Subtarget, DAG);
19392 case ISD::SHL: return LowerShift(Op, Subtarget, DAG);
19398 case ISD::UMULO: return LowerXALUO(Op, DAG);
19399 case ISD::READCYCLECOUNTER: return LowerREADCYCLECOUNTER(Op, Subtarget,DAG);
19400 case ISD::BITCAST: return LowerBITCAST(Op, Subtarget, DAG);
19404 case ISD::SUBE: return LowerADDC_ADDE_SUBC_SUBE(Op, DAG);
19405 case ISD::ADD: return LowerADD(Op, DAG);
19406 case ISD::SUB: return LowerSUB(Op, DAG);
19407 case ISD::FSINCOS: return LowerFSINCOS(Op, Subtarget, DAG);
19411 /// ReplaceNodeResults - Replace a node with an illegal result type
19412 /// with a new node built out of custom code.
19413 void X86TargetLowering::ReplaceNodeResults(SDNode *N,
19414 SmallVectorImpl<SDValue>&Results,
19415 SelectionDAG &DAG) const {
19417 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
19418 switch (N->getOpcode()) {
19420 llvm_unreachable("Do not know how to custom type legalize this operation!");
19421 case ISD::SIGN_EXTEND_INREG:
19426 // We don't want to expand or promote these.
19433 case ISD::UDIVREM: {
19434 SDValue V = LowerWin64_i128OP(SDValue(N,0), DAG);
19435 Results.push_back(V);
19438 case ISD::FP_TO_SINT:
19439 case ISD::FP_TO_UINT: {
19440 bool IsSigned = N->getOpcode() == ISD::FP_TO_SINT;
19442 if (!IsSigned && !isIntegerTypeFTOL(SDValue(N, 0).getValueType()))
19445 std::pair<SDValue,SDValue> Vals =
19446 FP_TO_INTHelper(SDValue(N, 0), DAG, IsSigned, /*IsReplace=*/ true);
19447 SDValue FIST = Vals.first, StackSlot = Vals.second;
19448 if (FIST.getNode()) {
19449 EVT VT = N->getValueType(0);
19450 // Return a load from the stack slot.
19451 if (StackSlot.getNode())
19452 Results.push_back(DAG.getLoad(VT, dl, FIST, StackSlot,
19453 MachinePointerInfo(),
19454 false, false, false, 0));
19456 Results.push_back(FIST);
19460 case ISD::UINT_TO_FP: {
19461 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
19462 if (N->getOperand(0).getValueType() != MVT::v2i32 ||
19463 N->getValueType(0) != MVT::v2f32)
19465 SDValue ZExtIn = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v2i64,
19467 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL),
19469 SDValue VBias = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2f64, Bias, Bias);
19470 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64, ZExtIn,
19471 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, VBias));
19472 Or = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Or);
19473 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, Or, VBias);
19474 Results.push_back(DAG.getNode(X86ISD::VFPROUND, dl, MVT::v4f32, Sub));
19477 case ISD::FP_ROUND: {
19478 if (!TLI.isTypeLegal(N->getOperand(0).getValueType()))
19480 SDValue V = DAG.getNode(X86ISD::VFPROUND, dl, MVT::v4f32, N->getOperand(0));
19481 Results.push_back(V);
19484 case ISD::INTRINSIC_W_CHAIN: {
19485 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
19487 default : llvm_unreachable("Do not know how to custom type "
19488 "legalize this intrinsic operation!");
19489 case Intrinsic::x86_rdtsc:
19490 return getReadTimeStampCounter(N, dl, X86ISD::RDTSC_DAG, DAG, Subtarget,
19492 case Intrinsic::x86_rdtscp:
19493 return getReadTimeStampCounter(N, dl, X86ISD::RDTSCP_DAG, DAG, Subtarget,
19495 case Intrinsic::x86_rdpmc:
19496 return getReadPerformanceCounter(N, dl, DAG, Subtarget, Results);
19499 case ISD::READCYCLECOUNTER: {
19500 return getReadTimeStampCounter(N, dl, X86ISD::RDTSC_DAG, DAG, Subtarget,
19503 case ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS: {
19504 EVT T = N->getValueType(0);
19505 assert((T == MVT::i64 || T == MVT::i128) && "can only expand cmpxchg pair");
19506 bool Regs64bit = T == MVT::i128;
19507 EVT HalfT = Regs64bit ? MVT::i64 : MVT::i32;
19508 SDValue cpInL, cpInH;
19509 cpInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2),
19510 DAG.getConstant(0, HalfT));
19511 cpInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2),
19512 DAG.getConstant(1, HalfT));
19513 cpInL = DAG.getCopyToReg(N->getOperand(0), dl,
19514 Regs64bit ? X86::RAX : X86::EAX,
19516 cpInH = DAG.getCopyToReg(cpInL.getValue(0), dl,
19517 Regs64bit ? X86::RDX : X86::EDX,
19518 cpInH, cpInL.getValue(1));
19519 SDValue swapInL, swapInH;
19520 swapInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3),
19521 DAG.getConstant(0, HalfT));
19522 swapInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3),
19523 DAG.getConstant(1, HalfT));
19524 swapInL = DAG.getCopyToReg(cpInH.getValue(0), dl,
19525 Regs64bit ? X86::RBX : X86::EBX,
19526 swapInL, cpInH.getValue(1));
19527 swapInH = DAG.getCopyToReg(swapInL.getValue(0), dl,
19528 Regs64bit ? X86::RCX : X86::ECX,
19529 swapInH, swapInL.getValue(1));
19530 SDValue Ops[] = { swapInH.getValue(0),
19532 swapInH.getValue(1) };
19533 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
19534 MachineMemOperand *MMO = cast<AtomicSDNode>(N)->getMemOperand();
19535 unsigned Opcode = Regs64bit ? X86ISD::LCMPXCHG16_DAG :
19536 X86ISD::LCMPXCHG8_DAG;
19537 SDValue Result = DAG.getMemIntrinsicNode(Opcode, dl, Tys, Ops, T, MMO);
19538 SDValue cpOutL = DAG.getCopyFromReg(Result.getValue(0), dl,
19539 Regs64bit ? X86::RAX : X86::EAX,
19540 HalfT, Result.getValue(1));
19541 SDValue cpOutH = DAG.getCopyFromReg(cpOutL.getValue(1), dl,
19542 Regs64bit ? X86::RDX : X86::EDX,
19543 HalfT, cpOutL.getValue(2));
19544 SDValue OpsF[] = { cpOutL.getValue(0), cpOutH.getValue(0)};
19546 SDValue EFLAGS = DAG.getCopyFromReg(cpOutH.getValue(1), dl, X86::EFLAGS,
19547 MVT::i32, cpOutH.getValue(2));
19549 DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
19550 DAG.getConstant(X86::COND_E, MVT::i8), EFLAGS);
19551 Success = DAG.getZExtOrTrunc(Success, dl, N->getValueType(1));
19553 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, T, OpsF));
19554 Results.push_back(Success);
19555 Results.push_back(EFLAGS.getValue(1));
19558 case ISD::ATOMIC_SWAP:
19559 case ISD::ATOMIC_LOAD_ADD:
19560 case ISD::ATOMIC_LOAD_SUB:
19561 case ISD::ATOMIC_LOAD_AND:
19562 case ISD::ATOMIC_LOAD_OR:
19563 case ISD::ATOMIC_LOAD_XOR:
19564 case ISD::ATOMIC_LOAD_NAND:
19565 case ISD::ATOMIC_LOAD_MIN:
19566 case ISD::ATOMIC_LOAD_MAX:
19567 case ISD::ATOMIC_LOAD_UMIN:
19568 case ISD::ATOMIC_LOAD_UMAX:
19569 case ISD::ATOMIC_LOAD: {
19570 // Delegate to generic TypeLegalization. Situations we can really handle
19571 // should have already been dealt with by AtomicExpandPass.cpp.
19574 case ISD::BITCAST: {
19575 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
19576 EVT DstVT = N->getValueType(0);
19577 EVT SrcVT = N->getOperand(0)->getValueType(0);
19579 if (SrcVT != MVT::f64 ||
19580 (DstVT != MVT::v2i32 && DstVT != MVT::v4i16 && DstVT != MVT::v8i8))
19583 unsigned NumElts = DstVT.getVectorNumElements();
19584 EVT SVT = DstVT.getVectorElementType();
19585 EVT WiderVT = EVT::getVectorVT(*DAG.getContext(), SVT, NumElts * 2);
19586 SDValue Expanded = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
19587 MVT::v2f64, N->getOperand(0));
19588 SDValue ToVecInt = DAG.getNode(ISD::BITCAST, dl, WiderVT, Expanded);
19590 if (ExperimentalVectorWideningLegalization) {
19591 // If we are legalizing vectors by widening, we already have the desired
19592 // legal vector type, just return it.
19593 Results.push_back(ToVecInt);
19597 SmallVector<SDValue, 8> Elts;
19598 for (unsigned i = 0, e = NumElts; i != e; ++i)
19599 Elts.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, SVT,
19600 ToVecInt, DAG.getIntPtrConstant(i)));
19602 Results.push_back(DAG.getNode(ISD::BUILD_VECTOR, dl, DstVT, Elts));
19607 const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
19609 default: return nullptr;
19610 case X86ISD::BSF: return "X86ISD::BSF";
19611 case X86ISD::BSR: return "X86ISD::BSR";
19612 case X86ISD::SHLD: return "X86ISD::SHLD";
19613 case X86ISD::SHRD: return "X86ISD::SHRD";
19614 case X86ISD::FAND: return "X86ISD::FAND";
19615 case X86ISD::FANDN: return "X86ISD::FANDN";
19616 case X86ISD::FOR: return "X86ISD::FOR";
19617 case X86ISD::FXOR: return "X86ISD::FXOR";
19618 case X86ISD::FSRL: return "X86ISD::FSRL";
19619 case X86ISD::FILD: return "X86ISD::FILD";
19620 case X86ISD::FILD_FLAG: return "X86ISD::FILD_FLAG";
19621 case X86ISD::FP_TO_INT16_IN_MEM: return "X86ISD::FP_TO_INT16_IN_MEM";
19622 case X86ISD::FP_TO_INT32_IN_MEM: return "X86ISD::FP_TO_INT32_IN_MEM";
19623 case X86ISD::FP_TO_INT64_IN_MEM: return "X86ISD::FP_TO_INT64_IN_MEM";
19624 case X86ISD::FLD: return "X86ISD::FLD";
19625 case X86ISD::FST: return "X86ISD::FST";
19626 case X86ISD::CALL: return "X86ISD::CALL";
19627 case X86ISD::RDTSC_DAG: return "X86ISD::RDTSC_DAG";
19628 case X86ISD::RDTSCP_DAG: return "X86ISD::RDTSCP_DAG";
19629 case X86ISD::RDPMC_DAG: return "X86ISD::RDPMC_DAG";
19630 case X86ISD::BT: return "X86ISD::BT";
19631 case X86ISD::CMP: return "X86ISD::CMP";
19632 case X86ISD::COMI: return "X86ISD::COMI";
19633 case X86ISD::UCOMI: return "X86ISD::UCOMI";
19634 case X86ISD::CMPM: return "X86ISD::CMPM";
19635 case X86ISD::CMPMU: return "X86ISD::CMPMU";
19636 case X86ISD::SETCC: return "X86ISD::SETCC";
19637 case X86ISD::SETCC_CARRY: return "X86ISD::SETCC_CARRY";
19638 case X86ISD::FSETCC: return "X86ISD::FSETCC";
19639 case X86ISD::CMOV: return "X86ISD::CMOV";
19640 case X86ISD::BRCOND: return "X86ISD::BRCOND";
19641 case X86ISD::RET_FLAG: return "X86ISD::RET_FLAG";
19642 case X86ISD::REP_STOS: return "X86ISD::REP_STOS";
19643 case X86ISD::REP_MOVS: return "X86ISD::REP_MOVS";
19644 case X86ISD::GlobalBaseReg: return "X86ISD::GlobalBaseReg";
19645 case X86ISD::Wrapper: return "X86ISD::Wrapper";
19646 case X86ISD::WrapperRIP: return "X86ISD::WrapperRIP";
19647 case X86ISD::PEXTRB: return "X86ISD::PEXTRB";
19648 case X86ISD::PEXTRW: return "X86ISD::PEXTRW";
19649 case X86ISD::INSERTPS: return "X86ISD::INSERTPS";
19650 case X86ISD::PINSRB: return "X86ISD::PINSRB";
19651 case X86ISD::PINSRW: return "X86ISD::PINSRW";
19652 case X86ISD::PSHUFB: return "X86ISD::PSHUFB";
19653 case X86ISD::ANDNP: return "X86ISD::ANDNP";
19654 case X86ISD::PSIGN: return "X86ISD::PSIGN";
19655 case X86ISD::BLENDI: return "X86ISD::BLENDI";
19656 case X86ISD::SHRUNKBLEND: return "X86ISD::SHRUNKBLEND";
19657 case X86ISD::SUBUS: return "X86ISD::SUBUS";
19658 case X86ISD::HADD: return "X86ISD::HADD";
19659 case X86ISD::HSUB: return "X86ISD::HSUB";
19660 case X86ISD::FHADD: return "X86ISD::FHADD";
19661 case X86ISD::FHSUB: return "X86ISD::FHSUB";
19662 case X86ISD::UMAX: return "X86ISD::UMAX";
19663 case X86ISD::UMIN: return "X86ISD::UMIN";
19664 case X86ISD::SMAX: return "X86ISD::SMAX";
19665 case X86ISD::SMIN: return "X86ISD::SMIN";
19666 case X86ISD::FMAX: return "X86ISD::FMAX";
19667 case X86ISD::FMIN: return "X86ISD::FMIN";
19668 case X86ISD::FMAXC: return "X86ISD::FMAXC";
19669 case X86ISD::FMINC: return "X86ISD::FMINC";
19670 case X86ISD::FRSQRT: return "X86ISD::FRSQRT";
19671 case X86ISD::FRCP: return "X86ISD::FRCP";
19672 case X86ISD::TLSADDR: return "X86ISD::TLSADDR";
19673 case X86ISD::TLSBASEADDR: return "X86ISD::TLSBASEADDR";
19674 case X86ISD::TLSCALL: return "X86ISD::TLSCALL";
19675 case X86ISD::EH_SJLJ_SETJMP: return "X86ISD::EH_SJLJ_SETJMP";
19676 case X86ISD::EH_SJLJ_LONGJMP: return "X86ISD::EH_SJLJ_LONGJMP";
19677 case X86ISD::EH_RETURN: return "X86ISD::EH_RETURN";
19678 case X86ISD::TC_RETURN: return "X86ISD::TC_RETURN";
19679 case X86ISD::FNSTCW16m: return "X86ISD::FNSTCW16m";
19680 case X86ISD::FNSTSW16r: return "X86ISD::FNSTSW16r";
19681 case X86ISD::LCMPXCHG_DAG: return "X86ISD::LCMPXCHG_DAG";
19682 case X86ISD::LCMPXCHG8_DAG: return "X86ISD::LCMPXCHG8_DAG";
19683 case X86ISD::LCMPXCHG16_DAG: return "X86ISD::LCMPXCHG16_DAG";
19684 case X86ISD::VZEXT_MOVL: return "X86ISD::VZEXT_MOVL";
19685 case X86ISD::VZEXT_LOAD: return "X86ISD::VZEXT_LOAD";
19686 case X86ISD::VZEXT: return "X86ISD::VZEXT";
19687 case X86ISD::VSEXT: return "X86ISD::VSEXT";
19688 case X86ISD::VTRUNC: return "X86ISD::VTRUNC";
19689 case X86ISD::VTRUNCM: return "X86ISD::VTRUNCM";
19690 case X86ISD::VINSERT: return "X86ISD::VINSERT";
19691 case X86ISD::VFPEXT: return "X86ISD::VFPEXT";
19692 case X86ISD::VFPROUND: return "X86ISD::VFPROUND";
19693 case X86ISD::VSHLDQ: return "X86ISD::VSHLDQ";
19694 case X86ISD::VSRLDQ: return "X86ISD::VSRLDQ";
19695 case X86ISD::VSHL: return "X86ISD::VSHL";
19696 case X86ISD::VSRL: return "X86ISD::VSRL";
19697 case X86ISD::VSRA: return "X86ISD::VSRA";
19698 case X86ISD::VSHLI: return "X86ISD::VSHLI";
19699 case X86ISD::VSRLI: return "X86ISD::VSRLI";
19700 case X86ISD::VSRAI: return "X86ISD::VSRAI";
19701 case X86ISD::CMPP: return "X86ISD::CMPP";
19702 case X86ISD::PCMPEQ: return "X86ISD::PCMPEQ";
19703 case X86ISD::PCMPGT: return "X86ISD::PCMPGT";
19704 case X86ISD::PCMPEQM: return "X86ISD::PCMPEQM";
19705 case X86ISD::PCMPGTM: return "X86ISD::PCMPGTM";
19706 case X86ISD::ADD: return "X86ISD::ADD";
19707 case X86ISD::SUB: return "X86ISD::SUB";
19708 case X86ISD::ADC: return "X86ISD::ADC";
19709 case X86ISD::SBB: return "X86ISD::SBB";
19710 case X86ISD::SMUL: return "X86ISD::SMUL";
19711 case X86ISD::UMUL: return "X86ISD::UMUL";
19712 case X86ISD::SMUL8: return "X86ISD::SMUL8";
19713 case X86ISD::UMUL8: return "X86ISD::UMUL8";
19714 case X86ISD::SDIVREM8_SEXT_HREG: return "X86ISD::SDIVREM8_SEXT_HREG";
19715 case X86ISD::UDIVREM8_ZEXT_HREG: return "X86ISD::UDIVREM8_ZEXT_HREG";
19716 case X86ISD::INC: return "X86ISD::INC";
19717 case X86ISD::DEC: return "X86ISD::DEC";
19718 case X86ISD::OR: return "X86ISD::OR";
19719 case X86ISD::XOR: return "X86ISD::XOR";
19720 case X86ISD::AND: return "X86ISD::AND";
19721 case X86ISD::BEXTR: return "X86ISD::BEXTR";
19722 case X86ISD::MUL_IMM: return "X86ISD::MUL_IMM";
19723 case X86ISD::PTEST: return "X86ISD::PTEST";
19724 case X86ISD::TESTP: return "X86ISD::TESTP";
19725 case X86ISD::TESTM: return "X86ISD::TESTM";
19726 case X86ISD::TESTNM: return "X86ISD::TESTNM";
19727 case X86ISD::KORTEST: return "X86ISD::KORTEST";
19728 case X86ISD::PACKSS: return "X86ISD::PACKSS";
19729 case X86ISD::PACKUS: return "X86ISD::PACKUS";
19730 case X86ISD::PALIGNR: return "X86ISD::PALIGNR";
19731 case X86ISD::VALIGN: return "X86ISD::VALIGN";
19732 case X86ISD::PSHUFD: return "X86ISD::PSHUFD";
19733 case X86ISD::PSHUFHW: return "X86ISD::PSHUFHW";
19734 case X86ISD::PSHUFLW: return "X86ISD::PSHUFLW";
19735 case X86ISD::SHUFP: return "X86ISD::SHUFP";
19736 case X86ISD::MOVLHPS: return "X86ISD::MOVLHPS";
19737 case X86ISD::MOVLHPD: return "X86ISD::MOVLHPD";
19738 case X86ISD::MOVHLPS: return "X86ISD::MOVHLPS";
19739 case X86ISD::MOVLPS: return "X86ISD::MOVLPS";
19740 case X86ISD::MOVLPD: return "X86ISD::MOVLPD";
19741 case X86ISD::MOVDDUP: return "X86ISD::MOVDDUP";
19742 case X86ISD::MOVSHDUP: return "X86ISD::MOVSHDUP";
19743 case X86ISD::MOVSLDUP: return "X86ISD::MOVSLDUP";
19744 case X86ISD::MOVSD: return "X86ISD::MOVSD";
19745 case X86ISD::MOVSS: return "X86ISD::MOVSS";
19746 case X86ISD::UNPCKL: return "X86ISD::UNPCKL";
19747 case X86ISD::UNPCKH: return "X86ISD::UNPCKH";
19748 case X86ISD::VBROADCAST: return "X86ISD::VBROADCAST";
19749 case X86ISD::VBROADCASTM: return "X86ISD::VBROADCASTM";
19750 case X86ISD::VEXTRACT: return "X86ISD::VEXTRACT";
19751 case X86ISD::VPERMILPI: return "X86ISD::VPERMILPI";
19752 case X86ISD::VPERM2X128: return "X86ISD::VPERM2X128";
19753 case X86ISD::VPERMV: return "X86ISD::VPERMV";
19754 case X86ISD::VPERMV3: return "X86ISD::VPERMV3";
19755 case X86ISD::VPERMIV3: return "X86ISD::VPERMIV3";
19756 case X86ISD::VPERMI: return "X86ISD::VPERMI";
19757 case X86ISD::PMULUDQ: return "X86ISD::PMULUDQ";
19758 case X86ISD::PMULDQ: return "X86ISD::PMULDQ";
19759 case X86ISD::VASTART_SAVE_XMM_REGS: return "X86ISD::VASTART_SAVE_XMM_REGS";
19760 case X86ISD::VAARG_64: return "X86ISD::VAARG_64";
19761 case X86ISD::WIN_ALLOCA: return "X86ISD::WIN_ALLOCA";
19762 case X86ISD::MEMBARRIER: return "X86ISD::MEMBARRIER";
19763 case X86ISD::SEG_ALLOCA: return "X86ISD::SEG_ALLOCA";
19764 case X86ISD::WIN_FTOL: return "X86ISD::WIN_FTOL";
19765 case X86ISD::SAHF: return "X86ISD::SAHF";
19766 case X86ISD::RDRAND: return "X86ISD::RDRAND";
19767 case X86ISD::RDSEED: return "X86ISD::RDSEED";
19768 case X86ISD::FMADD: return "X86ISD::FMADD";
19769 case X86ISD::FMSUB: return "X86ISD::FMSUB";
19770 case X86ISD::FNMADD: return "X86ISD::FNMADD";
19771 case X86ISD::FNMSUB: return "X86ISD::FNMSUB";
19772 case X86ISD::FMADDSUB: return "X86ISD::FMADDSUB";
19773 case X86ISD::FMSUBADD: return "X86ISD::FMSUBADD";
19774 case X86ISD::PCMPESTRI: return "X86ISD::PCMPESTRI";
19775 case X86ISD::PCMPISTRI: return "X86ISD::PCMPISTRI";
19776 case X86ISD::XTEST: return "X86ISD::XTEST";
19780 // isLegalAddressingMode - Return true if the addressing mode represented
19781 // by AM is legal for this target, for a load/store of the specified type.
19782 bool X86TargetLowering::isLegalAddressingMode(const AddrMode &AM,
19784 // X86 supports extremely general addressing modes.
19785 CodeModel::Model M = getTargetMachine().getCodeModel();
19786 Reloc::Model R = getTargetMachine().getRelocationModel();
19788 // X86 allows a sign-extended 32-bit immediate field as a displacement.
19789 if (!X86::isOffsetSuitableForCodeModel(AM.BaseOffs, M, AM.BaseGV != nullptr))
19794 Subtarget->ClassifyGlobalReference(AM.BaseGV, getTargetMachine());
19796 // If a reference to this global requires an extra load, we can't fold it.
19797 if (isGlobalStubReference(GVFlags))
19800 // If BaseGV requires a register for the PIC base, we cannot also have a
19801 // BaseReg specified.
19802 if (AM.HasBaseReg && isGlobalRelativeToPICBase(GVFlags))
19805 // If lower 4G is not available, then we must use rip-relative addressing.
19806 if ((M != CodeModel::Small || R != Reloc::Static) &&
19807 Subtarget->is64Bit() && (AM.BaseOffs || AM.Scale > 1))
19811 switch (AM.Scale) {
19817 // These scales always work.
19822 // These scales are formed with basereg+scalereg. Only accept if there is
19827 default: // Other stuff never works.
19834 bool X86TargetLowering::isVectorShiftByScalarCheap(Type *Ty) const {
19835 unsigned Bits = Ty->getScalarSizeInBits();
19837 // 8-bit shifts are always expensive, but versions with a scalar amount aren't
19838 // particularly cheaper than those without.
19842 // On AVX2 there are new vpsllv[dq] instructions (and other shifts), that make
19843 // variable shifts just as cheap as scalar ones.
19844 if (Subtarget->hasInt256() && (Bits == 32 || Bits == 64))
19847 // Otherwise, it's significantly cheaper to shift by a scalar amount than by a
19848 // fully general vector.
19852 bool X86TargetLowering::isTruncateFree(Type *Ty1, Type *Ty2) const {
19853 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
19855 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits();
19856 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits();
19857 return NumBits1 > NumBits2;
19860 bool X86TargetLowering::allowTruncateForTailCall(Type *Ty1, Type *Ty2) const {
19861 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
19864 if (!isTypeLegal(EVT::getEVT(Ty1)))
19867 assert(Ty1->getPrimitiveSizeInBits() <= 64 && "i128 is probably not a noop");
19869 // Assuming the caller doesn't have a zeroext or signext return parameter,
19870 // truncation all the way down to i1 is valid.
19874 bool X86TargetLowering::isLegalICmpImmediate(int64_t Imm) const {
19875 return isInt<32>(Imm);
19878 bool X86TargetLowering::isLegalAddImmediate(int64_t Imm) const {
19879 // Can also use sub to handle negated immediates.
19880 return isInt<32>(Imm);
19883 bool X86TargetLowering::isTruncateFree(EVT VT1, EVT VT2) const {
19884 if (!VT1.isInteger() || !VT2.isInteger())
19886 unsigned NumBits1 = VT1.getSizeInBits();
19887 unsigned NumBits2 = VT2.getSizeInBits();
19888 return NumBits1 > NumBits2;
19891 bool X86TargetLowering::isZExtFree(Type *Ty1, Type *Ty2) const {
19892 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
19893 return Ty1->isIntegerTy(32) && Ty2->isIntegerTy(64) && Subtarget->is64Bit();
19896 bool X86TargetLowering::isZExtFree(EVT VT1, EVT VT2) const {
19897 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
19898 return VT1 == MVT::i32 && VT2 == MVT::i64 && Subtarget->is64Bit();
19901 bool X86TargetLowering::isZExtFree(SDValue Val, EVT VT2) const {
19902 EVT VT1 = Val.getValueType();
19903 if (isZExtFree(VT1, VT2))
19906 if (Val.getOpcode() != ISD::LOAD)
19909 if (!VT1.isSimple() || !VT1.isInteger() ||
19910 !VT2.isSimple() || !VT2.isInteger())
19913 switch (VT1.getSimpleVT().SimpleTy) {
19918 // X86 has 8, 16, and 32-bit zero-extending loads.
19926 X86TargetLowering::isFMAFasterThanFMulAndFAdd(EVT VT) const {
19927 if (!(Subtarget->hasFMA() || Subtarget->hasFMA4()))
19930 VT = VT.getScalarType();
19932 if (!VT.isSimple())
19935 switch (VT.getSimpleVT().SimpleTy) {
19946 bool X86TargetLowering::isNarrowingProfitable(EVT VT1, EVT VT2) const {
19947 // i16 instructions are longer (0x66 prefix) and potentially slower.
19948 return !(VT1 == MVT::i32 && VT2 == MVT::i16);
19951 /// isShuffleMaskLegal - Targets can use this to indicate that they only
19952 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
19953 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
19954 /// are assumed to be legal.
19956 X86TargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M,
19958 if (!VT.isSimple())
19961 MVT SVT = VT.getSimpleVT();
19963 // Very little shuffling can be done for 64-bit vectors right now.
19964 if (VT.getSizeInBits() == 64)
19967 // If this is a single-input shuffle with no 128 bit lane crossings we can
19968 // lower it into pshufb.
19969 if ((SVT.is128BitVector() && Subtarget->hasSSSE3()) ||
19970 (SVT.is256BitVector() && Subtarget->hasInt256())) {
19971 bool isLegal = true;
19972 for (unsigned I = 0, E = M.size(); I != E; ++I) {
19973 if (M[I] >= (int)SVT.getVectorNumElements() ||
19974 ShuffleCrosses128bitLane(SVT, I, M[I])) {
19983 // FIXME: blends, shifts.
19984 return (SVT.getVectorNumElements() == 2 ||
19985 ShuffleVectorSDNode::isSplatMask(&M[0], VT) ||
19986 isMOVLMask(M, SVT) ||
19987 isCommutedMOVLMask(M, SVT) ||
19988 isMOVHLPSMask(M, SVT) ||
19989 isSHUFPMask(M, SVT) ||
19990 isSHUFPMask(M, SVT, /* Commuted */ true) ||
19991 isPSHUFDMask(M, SVT) ||
19992 isPSHUFDMask(M, SVT, /* SecondOperand */ true) ||
19993 isPSHUFHWMask(M, SVT, Subtarget->hasInt256()) ||
19994 isPSHUFLWMask(M, SVT, Subtarget->hasInt256()) ||
19995 isPALIGNRMask(M, SVT, Subtarget) ||
19996 isUNPCKLMask(M, SVT, Subtarget->hasInt256()) ||
19997 isUNPCKHMask(M, SVT, Subtarget->hasInt256()) ||
19998 isUNPCKL_v_undef_Mask(M, SVT, Subtarget->hasInt256()) ||
19999 isUNPCKH_v_undef_Mask(M, SVT, Subtarget->hasInt256()) ||
20000 isBlendMask(M, SVT, Subtarget->hasSSE41(), Subtarget->hasInt256()) ||
20001 (Subtarget->hasSSE41() && isINSERTPSMask(M, SVT)));
20005 X86TargetLowering::isVectorClearMaskLegal(const SmallVectorImpl<int> &Mask,
20007 if (!VT.isSimple())
20010 MVT SVT = VT.getSimpleVT();
20011 unsigned NumElts = SVT.getVectorNumElements();
20012 // FIXME: This collection of masks seems suspect.
20015 if (NumElts == 4 && SVT.is128BitVector()) {
20016 return (isMOVLMask(Mask, SVT) ||
20017 isCommutedMOVLMask(Mask, SVT, true) ||
20018 isSHUFPMask(Mask, SVT) ||
20019 isSHUFPMask(Mask, SVT, /* Commuted */ true) ||
20020 isBlendMask(Mask, SVT, Subtarget->hasSSE41(),
20021 Subtarget->hasInt256()));
20026 //===----------------------------------------------------------------------===//
20027 // X86 Scheduler Hooks
20028 //===----------------------------------------------------------------------===//
20030 /// Utility function to emit xbegin specifying the start of an RTM region.
20031 static MachineBasicBlock *EmitXBegin(MachineInstr *MI, MachineBasicBlock *MBB,
20032 const TargetInstrInfo *TII) {
20033 DebugLoc DL = MI->getDebugLoc();
20035 const BasicBlock *BB = MBB->getBasicBlock();
20036 MachineFunction::iterator I = MBB;
20039 // For the v = xbegin(), we generate
20050 MachineBasicBlock *thisMBB = MBB;
20051 MachineFunction *MF = MBB->getParent();
20052 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
20053 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
20054 MF->insert(I, mainMBB);
20055 MF->insert(I, sinkMBB);
20057 // Transfer the remainder of BB and its successor edges to sinkMBB.
20058 sinkMBB->splice(sinkMBB->begin(), MBB,
20059 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
20060 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
20064 // # fallthrough to mainMBB
20065 // # abortion to sinkMBB
20066 BuildMI(thisMBB, DL, TII->get(X86::XBEGIN_4)).addMBB(sinkMBB);
20067 thisMBB->addSuccessor(mainMBB);
20068 thisMBB->addSuccessor(sinkMBB);
20072 BuildMI(mainMBB, DL, TII->get(X86::MOV32ri), X86::EAX).addImm(-1);
20073 mainMBB->addSuccessor(sinkMBB);
20076 // EAX is live into the sinkMBB
20077 sinkMBB->addLiveIn(X86::EAX);
20078 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
20079 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
20082 MI->eraseFromParent();
20086 // FIXME: When we get size specific XMM0 registers, i.e. XMM0_V16I8
20087 // or XMM0_V32I8 in AVX all of this code can be replaced with that
20088 // in the .td file.
20089 static MachineBasicBlock *EmitPCMPSTRM(MachineInstr *MI, MachineBasicBlock *BB,
20090 const TargetInstrInfo *TII) {
20092 switch (MI->getOpcode()) {
20093 default: llvm_unreachable("illegal opcode!");
20094 case X86::PCMPISTRM128REG: Opc = X86::PCMPISTRM128rr; break;
20095 case X86::VPCMPISTRM128REG: Opc = X86::VPCMPISTRM128rr; break;
20096 case X86::PCMPISTRM128MEM: Opc = X86::PCMPISTRM128rm; break;
20097 case X86::VPCMPISTRM128MEM: Opc = X86::VPCMPISTRM128rm; break;
20098 case X86::PCMPESTRM128REG: Opc = X86::PCMPESTRM128rr; break;
20099 case X86::VPCMPESTRM128REG: Opc = X86::VPCMPESTRM128rr; break;
20100 case X86::PCMPESTRM128MEM: Opc = X86::PCMPESTRM128rm; break;
20101 case X86::VPCMPESTRM128MEM: Opc = X86::VPCMPESTRM128rm; break;
20104 DebugLoc dl = MI->getDebugLoc();
20105 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(Opc));
20107 unsigned NumArgs = MI->getNumOperands();
20108 for (unsigned i = 1; i < NumArgs; ++i) {
20109 MachineOperand &Op = MI->getOperand(i);
20110 if (!(Op.isReg() && Op.isImplicit()))
20111 MIB.addOperand(Op);
20113 if (MI->hasOneMemOperand())
20114 MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
20116 BuildMI(*BB, MI, dl,
20117 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
20118 .addReg(X86::XMM0);
20120 MI->eraseFromParent();
20124 // FIXME: Custom handling because TableGen doesn't support multiple implicit
20125 // defs in an instruction pattern
20126 static MachineBasicBlock *EmitPCMPSTRI(MachineInstr *MI, MachineBasicBlock *BB,
20127 const TargetInstrInfo *TII) {
20129 switch (MI->getOpcode()) {
20130 default: llvm_unreachable("illegal opcode!");
20131 case X86::PCMPISTRIREG: Opc = X86::PCMPISTRIrr; break;
20132 case X86::VPCMPISTRIREG: Opc = X86::VPCMPISTRIrr; break;
20133 case X86::PCMPISTRIMEM: Opc = X86::PCMPISTRIrm; break;
20134 case X86::VPCMPISTRIMEM: Opc = X86::VPCMPISTRIrm; break;
20135 case X86::PCMPESTRIREG: Opc = X86::PCMPESTRIrr; break;
20136 case X86::VPCMPESTRIREG: Opc = X86::VPCMPESTRIrr; break;
20137 case X86::PCMPESTRIMEM: Opc = X86::PCMPESTRIrm; break;
20138 case X86::VPCMPESTRIMEM: Opc = X86::VPCMPESTRIrm; break;
20141 DebugLoc dl = MI->getDebugLoc();
20142 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(Opc));
20144 unsigned NumArgs = MI->getNumOperands(); // remove the results
20145 for (unsigned i = 1; i < NumArgs; ++i) {
20146 MachineOperand &Op = MI->getOperand(i);
20147 if (!(Op.isReg() && Op.isImplicit()))
20148 MIB.addOperand(Op);
20150 if (MI->hasOneMemOperand())
20151 MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
20153 BuildMI(*BB, MI, dl,
20154 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
20157 MI->eraseFromParent();
20161 static MachineBasicBlock * EmitMonitor(MachineInstr *MI, MachineBasicBlock *BB,
20162 const TargetInstrInfo *TII,
20163 const X86Subtarget* Subtarget) {
20164 DebugLoc dl = MI->getDebugLoc();
20166 // Address into RAX/EAX, other two args into ECX, EDX.
20167 unsigned MemOpc = Subtarget->is64Bit() ? X86::LEA64r : X86::LEA32r;
20168 unsigned MemReg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
20169 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(MemOpc), MemReg);
20170 for (int i = 0; i < X86::AddrNumOperands; ++i)
20171 MIB.addOperand(MI->getOperand(i));
20173 unsigned ValOps = X86::AddrNumOperands;
20174 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::ECX)
20175 .addReg(MI->getOperand(ValOps).getReg());
20176 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::EDX)
20177 .addReg(MI->getOperand(ValOps+1).getReg());
20179 // The instruction doesn't actually take any operands though.
20180 BuildMI(*BB, MI, dl, TII->get(X86::MONITORrrr));
20182 MI->eraseFromParent(); // The pseudo is gone now.
20186 MachineBasicBlock *
20187 X86TargetLowering::EmitVAARG64WithCustomInserter(
20189 MachineBasicBlock *MBB) const {
20190 // Emit va_arg instruction on X86-64.
20192 // Operands to this pseudo-instruction:
20193 // 0 ) Output : destination address (reg)
20194 // 1-5) Input : va_list address (addr, i64mem)
20195 // 6 ) ArgSize : Size (in bytes) of vararg type
20196 // 7 ) ArgMode : 0=overflow only, 1=use gp_offset, 2=use fp_offset
20197 // 8 ) Align : Alignment of type
20198 // 9 ) EFLAGS (implicit-def)
20200 assert(MI->getNumOperands() == 10 && "VAARG_64 should have 10 operands!");
20201 assert(X86::AddrNumOperands == 5 && "VAARG_64 assumes 5 address operands");
20203 unsigned DestReg = MI->getOperand(0).getReg();
20204 MachineOperand &Base = MI->getOperand(1);
20205 MachineOperand &Scale = MI->getOperand(2);
20206 MachineOperand &Index = MI->getOperand(3);
20207 MachineOperand &Disp = MI->getOperand(4);
20208 MachineOperand &Segment = MI->getOperand(5);
20209 unsigned ArgSize = MI->getOperand(6).getImm();
20210 unsigned ArgMode = MI->getOperand(7).getImm();
20211 unsigned Align = MI->getOperand(8).getImm();
20213 // Memory Reference
20214 assert(MI->hasOneMemOperand() && "Expected VAARG_64 to have one memoperand");
20215 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
20216 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
20218 // Machine Information
20219 const TargetInstrInfo *TII = MBB->getParent()->getSubtarget().getInstrInfo();
20220 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
20221 const TargetRegisterClass *AddrRegClass = getRegClassFor(MVT::i64);
20222 const TargetRegisterClass *OffsetRegClass = getRegClassFor(MVT::i32);
20223 DebugLoc DL = MI->getDebugLoc();
20225 // struct va_list {
20228 // i64 overflow_area (address)
20229 // i64 reg_save_area (address)
20231 // sizeof(va_list) = 24
20232 // alignment(va_list) = 8
20234 unsigned TotalNumIntRegs = 6;
20235 unsigned TotalNumXMMRegs = 8;
20236 bool UseGPOffset = (ArgMode == 1);
20237 bool UseFPOffset = (ArgMode == 2);
20238 unsigned MaxOffset = TotalNumIntRegs * 8 +
20239 (UseFPOffset ? TotalNumXMMRegs * 16 : 0);
20241 /* Align ArgSize to a multiple of 8 */
20242 unsigned ArgSizeA8 = (ArgSize + 7) & ~7;
20243 bool NeedsAlign = (Align > 8);
20245 MachineBasicBlock *thisMBB = MBB;
20246 MachineBasicBlock *overflowMBB;
20247 MachineBasicBlock *offsetMBB;
20248 MachineBasicBlock *endMBB;
20250 unsigned OffsetDestReg = 0; // Argument address computed by offsetMBB
20251 unsigned OverflowDestReg = 0; // Argument address computed by overflowMBB
20252 unsigned OffsetReg = 0;
20254 if (!UseGPOffset && !UseFPOffset) {
20255 // If we only pull from the overflow region, we don't create a branch.
20256 // We don't need to alter control flow.
20257 OffsetDestReg = 0; // unused
20258 OverflowDestReg = DestReg;
20260 offsetMBB = nullptr;
20261 overflowMBB = thisMBB;
20264 // First emit code to check if gp_offset (or fp_offset) is below the bound.
20265 // If so, pull the argument from reg_save_area. (branch to offsetMBB)
20266 // If not, pull from overflow_area. (branch to overflowMBB)
20271 // offsetMBB overflowMBB
20276 // Registers for the PHI in endMBB
20277 OffsetDestReg = MRI.createVirtualRegister(AddrRegClass);
20278 OverflowDestReg = MRI.createVirtualRegister(AddrRegClass);
20280 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
20281 MachineFunction *MF = MBB->getParent();
20282 overflowMBB = MF->CreateMachineBasicBlock(LLVM_BB);
20283 offsetMBB = MF->CreateMachineBasicBlock(LLVM_BB);
20284 endMBB = MF->CreateMachineBasicBlock(LLVM_BB);
20286 MachineFunction::iterator MBBIter = MBB;
20289 // Insert the new basic blocks
20290 MF->insert(MBBIter, offsetMBB);
20291 MF->insert(MBBIter, overflowMBB);
20292 MF->insert(MBBIter, endMBB);
20294 // Transfer the remainder of MBB and its successor edges to endMBB.
20295 endMBB->splice(endMBB->begin(), thisMBB,
20296 std::next(MachineBasicBlock::iterator(MI)), thisMBB->end());
20297 endMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
20299 // Make offsetMBB and overflowMBB successors of thisMBB
20300 thisMBB->addSuccessor(offsetMBB);
20301 thisMBB->addSuccessor(overflowMBB);
20303 // endMBB is a successor of both offsetMBB and overflowMBB
20304 offsetMBB->addSuccessor(endMBB);
20305 overflowMBB->addSuccessor(endMBB);
20307 // Load the offset value into a register
20308 OffsetReg = MRI.createVirtualRegister(OffsetRegClass);
20309 BuildMI(thisMBB, DL, TII->get(X86::MOV32rm), OffsetReg)
20313 .addDisp(Disp, UseFPOffset ? 4 : 0)
20314 .addOperand(Segment)
20315 .setMemRefs(MMOBegin, MMOEnd);
20317 // Check if there is enough room left to pull this argument.
20318 BuildMI(thisMBB, DL, TII->get(X86::CMP32ri))
20320 .addImm(MaxOffset + 8 - ArgSizeA8);
20322 // Branch to "overflowMBB" if offset >= max
20323 // Fall through to "offsetMBB" otherwise
20324 BuildMI(thisMBB, DL, TII->get(X86::GetCondBranchFromCond(X86::COND_AE)))
20325 .addMBB(overflowMBB);
20328 // In offsetMBB, emit code to use the reg_save_area.
20330 assert(OffsetReg != 0);
20332 // Read the reg_save_area address.
20333 unsigned RegSaveReg = MRI.createVirtualRegister(AddrRegClass);
20334 BuildMI(offsetMBB, DL, TII->get(X86::MOV64rm), RegSaveReg)
20339 .addOperand(Segment)
20340 .setMemRefs(MMOBegin, MMOEnd);
20342 // Zero-extend the offset
20343 unsigned OffsetReg64 = MRI.createVirtualRegister(AddrRegClass);
20344 BuildMI(offsetMBB, DL, TII->get(X86::SUBREG_TO_REG), OffsetReg64)
20347 .addImm(X86::sub_32bit);
20349 // Add the offset to the reg_save_area to get the final address.
20350 BuildMI(offsetMBB, DL, TII->get(X86::ADD64rr), OffsetDestReg)
20351 .addReg(OffsetReg64)
20352 .addReg(RegSaveReg);
20354 // Compute the offset for the next argument
20355 unsigned NextOffsetReg = MRI.createVirtualRegister(OffsetRegClass);
20356 BuildMI(offsetMBB, DL, TII->get(X86::ADD32ri), NextOffsetReg)
20358 .addImm(UseFPOffset ? 16 : 8);
20360 // Store it back into the va_list.
20361 BuildMI(offsetMBB, DL, TII->get(X86::MOV32mr))
20365 .addDisp(Disp, UseFPOffset ? 4 : 0)
20366 .addOperand(Segment)
20367 .addReg(NextOffsetReg)
20368 .setMemRefs(MMOBegin, MMOEnd);
20371 BuildMI(offsetMBB, DL, TII->get(X86::JMP_4))
20376 // Emit code to use overflow area
20379 // Load the overflow_area address into a register.
20380 unsigned OverflowAddrReg = MRI.createVirtualRegister(AddrRegClass);
20381 BuildMI(overflowMBB, DL, TII->get(X86::MOV64rm), OverflowAddrReg)
20386 .addOperand(Segment)
20387 .setMemRefs(MMOBegin, MMOEnd);
20389 // If we need to align it, do so. Otherwise, just copy the address
20390 // to OverflowDestReg.
20392 // Align the overflow address
20393 assert((Align & (Align-1)) == 0 && "Alignment must be a power of 2");
20394 unsigned TmpReg = MRI.createVirtualRegister(AddrRegClass);
20396 // aligned_addr = (addr + (align-1)) & ~(align-1)
20397 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), TmpReg)
20398 .addReg(OverflowAddrReg)
20401 BuildMI(overflowMBB, DL, TII->get(X86::AND64ri32), OverflowDestReg)
20403 .addImm(~(uint64_t)(Align-1));
20405 BuildMI(overflowMBB, DL, TII->get(TargetOpcode::COPY), OverflowDestReg)
20406 .addReg(OverflowAddrReg);
20409 // Compute the next overflow address after this argument.
20410 // (the overflow address should be kept 8-byte aligned)
20411 unsigned NextAddrReg = MRI.createVirtualRegister(AddrRegClass);
20412 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), NextAddrReg)
20413 .addReg(OverflowDestReg)
20414 .addImm(ArgSizeA8);
20416 // Store the new overflow address.
20417 BuildMI(overflowMBB, DL, TII->get(X86::MOV64mr))
20422 .addOperand(Segment)
20423 .addReg(NextAddrReg)
20424 .setMemRefs(MMOBegin, MMOEnd);
20426 // If we branched, emit the PHI to the front of endMBB.
20428 BuildMI(*endMBB, endMBB->begin(), DL,
20429 TII->get(X86::PHI), DestReg)
20430 .addReg(OffsetDestReg).addMBB(offsetMBB)
20431 .addReg(OverflowDestReg).addMBB(overflowMBB);
20434 // Erase the pseudo instruction
20435 MI->eraseFromParent();
20440 MachineBasicBlock *
20441 X86TargetLowering::EmitVAStartSaveXMMRegsWithCustomInserter(
20443 MachineBasicBlock *MBB) const {
20444 // Emit code to save XMM registers to the stack. The ABI says that the
20445 // number of registers to save is given in %al, so it's theoretically
20446 // possible to do an indirect jump trick to avoid saving all of them,
20447 // however this code takes a simpler approach and just executes all
20448 // of the stores if %al is non-zero. It's less code, and it's probably
20449 // easier on the hardware branch predictor, and stores aren't all that
20450 // expensive anyway.
20452 // Create the new basic blocks. One block contains all the XMM stores,
20453 // and one block is the final destination regardless of whether any
20454 // stores were performed.
20455 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
20456 MachineFunction *F = MBB->getParent();
20457 MachineFunction::iterator MBBIter = MBB;
20459 MachineBasicBlock *XMMSaveMBB = F->CreateMachineBasicBlock(LLVM_BB);
20460 MachineBasicBlock *EndMBB = F->CreateMachineBasicBlock(LLVM_BB);
20461 F->insert(MBBIter, XMMSaveMBB);
20462 F->insert(MBBIter, EndMBB);
20464 // Transfer the remainder of MBB and its successor edges to EndMBB.
20465 EndMBB->splice(EndMBB->begin(), MBB,
20466 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
20467 EndMBB->transferSuccessorsAndUpdatePHIs(MBB);
20469 // The original block will now fall through to the XMM save block.
20470 MBB->addSuccessor(XMMSaveMBB);
20471 // The XMMSaveMBB will fall through to the end block.
20472 XMMSaveMBB->addSuccessor(EndMBB);
20474 // Now add the instructions.
20475 const TargetInstrInfo *TII = MBB->getParent()->getSubtarget().getInstrInfo();
20476 DebugLoc DL = MI->getDebugLoc();
20478 unsigned CountReg = MI->getOperand(0).getReg();
20479 int64_t RegSaveFrameIndex = MI->getOperand(1).getImm();
20480 int64_t VarArgsFPOffset = MI->getOperand(2).getImm();
20482 if (!Subtarget->isTargetWin64()) {
20483 // If %al is 0, branch around the XMM save block.
20484 BuildMI(MBB, DL, TII->get(X86::TEST8rr)).addReg(CountReg).addReg(CountReg);
20485 BuildMI(MBB, DL, TII->get(X86::JE_4)).addMBB(EndMBB);
20486 MBB->addSuccessor(EndMBB);
20489 // Make sure the last operand is EFLAGS, which gets clobbered by the branch
20490 // that was just emitted, but clearly shouldn't be "saved".
20491 assert((MI->getNumOperands() <= 3 ||
20492 !MI->getOperand(MI->getNumOperands() - 1).isReg() ||
20493 MI->getOperand(MI->getNumOperands() - 1).getReg() == X86::EFLAGS)
20494 && "Expected last argument to be EFLAGS");
20495 unsigned MOVOpc = Subtarget->hasFp256() ? X86::VMOVAPSmr : X86::MOVAPSmr;
20496 // In the XMM save block, save all the XMM argument registers.
20497 for (int i = 3, e = MI->getNumOperands() - 1; i != e; ++i) {
20498 int64_t Offset = (i - 3) * 16 + VarArgsFPOffset;
20499 MachineMemOperand *MMO =
20500 F->getMachineMemOperand(
20501 MachinePointerInfo::getFixedStack(RegSaveFrameIndex, Offset),
20502 MachineMemOperand::MOStore,
20503 /*Size=*/16, /*Align=*/16);
20504 BuildMI(XMMSaveMBB, DL, TII->get(MOVOpc))
20505 .addFrameIndex(RegSaveFrameIndex)
20506 .addImm(/*Scale=*/1)
20507 .addReg(/*IndexReg=*/0)
20508 .addImm(/*Disp=*/Offset)
20509 .addReg(/*Segment=*/0)
20510 .addReg(MI->getOperand(i).getReg())
20511 .addMemOperand(MMO);
20514 MI->eraseFromParent(); // The pseudo instruction is gone now.
20519 // The EFLAGS operand of SelectItr might be missing a kill marker
20520 // because there were multiple uses of EFLAGS, and ISel didn't know
20521 // which to mark. Figure out whether SelectItr should have had a
20522 // kill marker, and set it if it should. Returns the correct kill
20524 static bool checkAndUpdateEFLAGSKill(MachineBasicBlock::iterator SelectItr,
20525 MachineBasicBlock* BB,
20526 const TargetRegisterInfo* TRI) {
20527 // Scan forward through BB for a use/def of EFLAGS.
20528 MachineBasicBlock::iterator miI(std::next(SelectItr));
20529 for (MachineBasicBlock::iterator miE = BB->end(); miI != miE; ++miI) {
20530 const MachineInstr& mi = *miI;
20531 if (mi.readsRegister(X86::EFLAGS))
20533 if (mi.definesRegister(X86::EFLAGS))
20534 break; // Should have kill-flag - update below.
20537 // If we hit the end of the block, check whether EFLAGS is live into a
20539 if (miI == BB->end()) {
20540 for (MachineBasicBlock::succ_iterator sItr = BB->succ_begin(),
20541 sEnd = BB->succ_end();
20542 sItr != sEnd; ++sItr) {
20543 MachineBasicBlock* succ = *sItr;
20544 if (succ->isLiveIn(X86::EFLAGS))
20549 // We found a def, or hit the end of the basic block and EFLAGS wasn't live
20550 // out. SelectMI should have a kill flag on EFLAGS.
20551 SelectItr->addRegisterKilled(X86::EFLAGS, TRI);
20555 MachineBasicBlock *
20556 X86TargetLowering::EmitLoweredSelect(MachineInstr *MI,
20557 MachineBasicBlock *BB) const {
20558 const TargetInstrInfo *TII = BB->getParent()->getSubtarget().getInstrInfo();
20559 DebugLoc DL = MI->getDebugLoc();
20561 // To "insert" a SELECT_CC instruction, we actually have to insert the
20562 // diamond control-flow pattern. The incoming instruction knows the
20563 // destination vreg to set, the condition code register to branch on, the
20564 // true/false values to select between, and a branch opcode to use.
20565 const BasicBlock *LLVM_BB = BB->getBasicBlock();
20566 MachineFunction::iterator It = BB;
20572 // cmpTY ccX, r1, r2
20574 // fallthrough --> copy0MBB
20575 MachineBasicBlock *thisMBB = BB;
20576 MachineFunction *F = BB->getParent();
20577 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
20578 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
20579 F->insert(It, copy0MBB);
20580 F->insert(It, sinkMBB);
20582 // If the EFLAGS register isn't dead in the terminator, then claim that it's
20583 // live into the sink and copy blocks.
20584 const TargetRegisterInfo *TRI =
20585 BB->getParent()->getSubtarget().getRegisterInfo();
20586 if (!MI->killsRegister(X86::EFLAGS) &&
20587 !checkAndUpdateEFLAGSKill(MI, BB, TRI)) {
20588 copy0MBB->addLiveIn(X86::EFLAGS);
20589 sinkMBB->addLiveIn(X86::EFLAGS);
20592 // Transfer the remainder of BB and its successor edges to sinkMBB.
20593 sinkMBB->splice(sinkMBB->begin(), BB,
20594 std::next(MachineBasicBlock::iterator(MI)), BB->end());
20595 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
20597 // Add the true and fallthrough blocks as its successors.
20598 BB->addSuccessor(copy0MBB);
20599 BB->addSuccessor(sinkMBB);
20601 // Create the conditional branch instruction.
20603 X86::GetCondBranchFromCond((X86::CondCode)MI->getOperand(3).getImm());
20604 BuildMI(BB, DL, TII->get(Opc)).addMBB(sinkMBB);
20607 // %FalseValue = ...
20608 // # fallthrough to sinkMBB
20609 copy0MBB->addSuccessor(sinkMBB);
20612 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
20614 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
20615 TII->get(X86::PHI), MI->getOperand(0).getReg())
20616 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB)
20617 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
20619 MI->eraseFromParent(); // The pseudo instruction is gone now.
20623 MachineBasicBlock *
20624 X86TargetLowering::EmitLoweredSegAlloca(MachineInstr *MI,
20625 MachineBasicBlock *BB) const {
20626 MachineFunction *MF = BB->getParent();
20627 const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo();
20628 DebugLoc DL = MI->getDebugLoc();
20629 const BasicBlock *LLVM_BB = BB->getBasicBlock();
20631 assert(MF->shouldSplitStack());
20633 const bool Is64Bit = Subtarget->is64Bit();
20634 const bool IsLP64 = Subtarget->isTarget64BitLP64();
20636 const unsigned TlsReg = Is64Bit ? X86::FS : X86::GS;
20637 const unsigned TlsOffset = IsLP64 ? 0x70 : Is64Bit ? 0x40 : 0x30;
20640 // ... [Till the alloca]
20641 // If stacklet is not large enough, jump to mallocMBB
20644 // Allocate by subtracting from RSP
20645 // Jump to continueMBB
20648 // Allocate by call to runtime
20652 // [rest of original BB]
20655 MachineBasicBlock *mallocMBB = MF->CreateMachineBasicBlock(LLVM_BB);
20656 MachineBasicBlock *bumpMBB = MF->CreateMachineBasicBlock(LLVM_BB);
20657 MachineBasicBlock *continueMBB = MF->CreateMachineBasicBlock(LLVM_BB);
20659 MachineRegisterInfo &MRI = MF->getRegInfo();
20660 const TargetRegisterClass *AddrRegClass =
20661 getRegClassFor(getPointerTy());
20663 unsigned mallocPtrVReg = MRI.createVirtualRegister(AddrRegClass),
20664 bumpSPPtrVReg = MRI.createVirtualRegister(AddrRegClass),
20665 tmpSPVReg = MRI.createVirtualRegister(AddrRegClass),
20666 SPLimitVReg = MRI.createVirtualRegister(AddrRegClass),
20667 sizeVReg = MI->getOperand(1).getReg(),
20668 physSPReg = IsLP64 || Subtarget->isTargetNaCl64() ? X86::RSP : X86::ESP;
20670 MachineFunction::iterator MBBIter = BB;
20673 MF->insert(MBBIter, bumpMBB);
20674 MF->insert(MBBIter, mallocMBB);
20675 MF->insert(MBBIter, continueMBB);
20677 continueMBB->splice(continueMBB->begin(), BB,
20678 std::next(MachineBasicBlock::iterator(MI)), BB->end());
20679 continueMBB->transferSuccessorsAndUpdatePHIs(BB);
20681 // Add code to the main basic block to check if the stack limit has been hit,
20682 // and if so, jump to mallocMBB otherwise to bumpMBB.
20683 BuildMI(BB, DL, TII->get(TargetOpcode::COPY), tmpSPVReg).addReg(physSPReg);
20684 BuildMI(BB, DL, TII->get(IsLP64 ? X86::SUB64rr:X86::SUB32rr), SPLimitVReg)
20685 .addReg(tmpSPVReg).addReg(sizeVReg);
20686 BuildMI(BB, DL, TII->get(IsLP64 ? X86::CMP64mr:X86::CMP32mr))
20687 .addReg(0).addImm(1).addReg(0).addImm(TlsOffset).addReg(TlsReg)
20688 .addReg(SPLimitVReg);
20689 BuildMI(BB, DL, TII->get(X86::JG_4)).addMBB(mallocMBB);
20691 // bumpMBB simply decreases the stack pointer, since we know the current
20692 // stacklet has enough space.
20693 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), physSPReg)
20694 .addReg(SPLimitVReg);
20695 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), bumpSPPtrVReg)
20696 .addReg(SPLimitVReg);
20697 BuildMI(bumpMBB, DL, TII->get(X86::JMP_4)).addMBB(continueMBB);
20699 // Calls into a routine in libgcc to allocate more space from the heap.
20700 const uint32_t *RegMask = MF->getTarget()
20701 .getSubtargetImpl()
20702 ->getRegisterInfo()
20703 ->getCallPreservedMask(CallingConv::C);
20705 BuildMI(mallocMBB, DL, TII->get(X86::MOV64rr), X86::RDI)
20707 BuildMI(mallocMBB, DL, TII->get(X86::CALL64pcrel32))
20708 .addExternalSymbol("__morestack_allocate_stack_space")
20709 .addRegMask(RegMask)
20710 .addReg(X86::RDI, RegState::Implicit)
20711 .addReg(X86::RAX, RegState::ImplicitDefine);
20712 } else if (Is64Bit) {
20713 BuildMI(mallocMBB, DL, TII->get(X86::MOV32rr), X86::EDI)
20715 BuildMI(mallocMBB, DL, TII->get(X86::CALL64pcrel32))
20716 .addExternalSymbol("__morestack_allocate_stack_space")
20717 .addRegMask(RegMask)
20718 .addReg(X86::EDI, RegState::Implicit)
20719 .addReg(X86::EAX, RegState::ImplicitDefine);
20721 BuildMI(mallocMBB, DL, TII->get(X86::SUB32ri), physSPReg).addReg(physSPReg)
20723 BuildMI(mallocMBB, DL, TII->get(X86::PUSH32r)).addReg(sizeVReg);
20724 BuildMI(mallocMBB, DL, TII->get(X86::CALLpcrel32))
20725 .addExternalSymbol("__morestack_allocate_stack_space")
20726 .addRegMask(RegMask)
20727 .addReg(X86::EAX, RegState::ImplicitDefine);
20731 BuildMI(mallocMBB, DL, TII->get(X86::ADD32ri), physSPReg).addReg(physSPReg)
20734 BuildMI(mallocMBB, DL, TII->get(TargetOpcode::COPY), mallocPtrVReg)
20735 .addReg(IsLP64 ? X86::RAX : X86::EAX);
20736 BuildMI(mallocMBB, DL, TII->get(X86::JMP_4)).addMBB(continueMBB);
20738 // Set up the CFG correctly.
20739 BB->addSuccessor(bumpMBB);
20740 BB->addSuccessor(mallocMBB);
20741 mallocMBB->addSuccessor(continueMBB);
20742 bumpMBB->addSuccessor(continueMBB);
20744 // Take care of the PHI nodes.
20745 BuildMI(*continueMBB, continueMBB->begin(), DL, TII->get(X86::PHI),
20746 MI->getOperand(0).getReg())
20747 .addReg(mallocPtrVReg).addMBB(mallocMBB)
20748 .addReg(bumpSPPtrVReg).addMBB(bumpMBB);
20750 // Delete the original pseudo instruction.
20751 MI->eraseFromParent();
20754 return continueMBB;
20757 MachineBasicBlock *
20758 X86TargetLowering::EmitLoweredWinAlloca(MachineInstr *MI,
20759 MachineBasicBlock *BB) const {
20760 const TargetInstrInfo *TII = BB->getParent()->getSubtarget().getInstrInfo();
20761 DebugLoc DL = MI->getDebugLoc();
20763 assert(!Subtarget->isTargetMacho());
20765 // The lowering is pretty easy: we're just emitting the call to _alloca. The
20766 // non-trivial part is impdef of ESP.
20768 if (Subtarget->isTargetWin64()) {
20769 if (Subtarget->isTargetCygMing()) {
20770 // ___chkstk(Mingw64):
20771 // Clobbers R10, R11, RAX and EFLAGS.
20773 BuildMI(*BB, MI, DL, TII->get(X86::W64ALLOCA))
20774 .addExternalSymbol("___chkstk")
20775 .addReg(X86::RAX, RegState::Implicit)
20776 .addReg(X86::RSP, RegState::Implicit)
20777 .addReg(X86::RAX, RegState::Define | RegState::Implicit)
20778 .addReg(X86::RSP, RegState::Define | RegState::Implicit)
20779 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
20781 // __chkstk(MSVCRT): does not update stack pointer.
20782 // Clobbers R10, R11 and EFLAGS.
20783 BuildMI(*BB, MI, DL, TII->get(X86::W64ALLOCA))
20784 .addExternalSymbol("__chkstk")
20785 .addReg(X86::RAX, RegState::Implicit)
20786 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
20787 // RAX has the offset to be subtracted from RSP.
20788 BuildMI(*BB, MI, DL, TII->get(X86::SUB64rr), X86::RSP)
20793 const char *StackProbeSymbol = (Subtarget->isTargetKnownWindowsMSVC() ||
20794 Subtarget->isTargetWindowsItanium())
20798 BuildMI(*BB, MI, DL, TII->get(X86::CALLpcrel32))
20799 .addExternalSymbol(StackProbeSymbol)
20800 .addReg(X86::EAX, RegState::Implicit)
20801 .addReg(X86::ESP, RegState::Implicit)
20802 .addReg(X86::EAX, RegState::Define | RegState::Implicit)
20803 .addReg(X86::ESP, RegState::Define | RegState::Implicit)
20804 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
20807 MI->eraseFromParent(); // The pseudo instruction is gone now.
20811 MachineBasicBlock *
20812 X86TargetLowering::EmitLoweredTLSCall(MachineInstr *MI,
20813 MachineBasicBlock *BB) const {
20814 // This is pretty easy. We're taking the value that we received from
20815 // our load from the relocation, sticking it in either RDI (x86-64)
20816 // or EAX and doing an indirect call. The return value will then
20817 // be in the normal return register.
20818 MachineFunction *F = BB->getParent();
20819 const X86InstrInfo *TII =
20820 static_cast<const X86InstrInfo *>(F->getSubtarget().getInstrInfo());
20821 DebugLoc DL = MI->getDebugLoc();
20823 assert(Subtarget->isTargetDarwin() && "Darwin only instr emitted?");
20824 assert(MI->getOperand(3).isGlobal() && "This should be a global");
20826 // Get a register mask for the lowered call.
20827 // FIXME: The 32-bit calls have non-standard calling conventions. Use a
20828 // proper register mask.
20829 const uint32_t *RegMask = F->getTarget()
20830 .getSubtargetImpl()
20831 ->getRegisterInfo()
20832 ->getCallPreservedMask(CallingConv::C);
20833 if (Subtarget->is64Bit()) {
20834 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
20835 TII->get(X86::MOV64rm), X86::RDI)
20837 .addImm(0).addReg(0)
20838 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
20839 MI->getOperand(3).getTargetFlags())
20841 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL64m));
20842 addDirectMem(MIB, X86::RDI);
20843 MIB.addReg(X86::RAX, RegState::ImplicitDefine).addRegMask(RegMask);
20844 } else if (F->getTarget().getRelocationModel() != Reloc::PIC_) {
20845 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
20846 TII->get(X86::MOV32rm), X86::EAX)
20848 .addImm(0).addReg(0)
20849 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
20850 MI->getOperand(3).getTargetFlags())
20852 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
20853 addDirectMem(MIB, X86::EAX);
20854 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask);
20856 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
20857 TII->get(X86::MOV32rm), X86::EAX)
20858 .addReg(TII->getGlobalBaseReg(F))
20859 .addImm(0).addReg(0)
20860 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
20861 MI->getOperand(3).getTargetFlags())
20863 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
20864 addDirectMem(MIB, X86::EAX);
20865 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask);
20868 MI->eraseFromParent(); // The pseudo instruction is gone now.
20872 MachineBasicBlock *
20873 X86TargetLowering::emitEHSjLjSetJmp(MachineInstr *MI,
20874 MachineBasicBlock *MBB) const {
20875 DebugLoc DL = MI->getDebugLoc();
20876 MachineFunction *MF = MBB->getParent();
20877 const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo();
20878 MachineRegisterInfo &MRI = MF->getRegInfo();
20880 const BasicBlock *BB = MBB->getBasicBlock();
20881 MachineFunction::iterator I = MBB;
20884 // Memory Reference
20885 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
20886 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
20889 unsigned MemOpndSlot = 0;
20891 unsigned CurOp = 0;
20893 DstReg = MI->getOperand(CurOp++).getReg();
20894 const TargetRegisterClass *RC = MRI.getRegClass(DstReg);
20895 assert(RC->hasType(MVT::i32) && "Invalid destination!");
20896 unsigned mainDstReg = MRI.createVirtualRegister(RC);
20897 unsigned restoreDstReg = MRI.createVirtualRegister(RC);
20899 MemOpndSlot = CurOp;
20901 MVT PVT = getPointerTy();
20902 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
20903 "Invalid Pointer Size!");
20905 // For v = setjmp(buf), we generate
20908 // buf[LabelOffset] = restoreMBB
20909 // SjLjSetup restoreMBB
20915 // v = phi(main, restore)
20920 MachineBasicBlock *thisMBB = MBB;
20921 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
20922 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
20923 MachineBasicBlock *restoreMBB = MF->CreateMachineBasicBlock(BB);
20924 MF->insert(I, mainMBB);
20925 MF->insert(I, sinkMBB);
20926 MF->push_back(restoreMBB);
20928 MachineInstrBuilder MIB;
20930 // Transfer the remainder of BB and its successor edges to sinkMBB.
20931 sinkMBB->splice(sinkMBB->begin(), MBB,
20932 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
20933 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
20936 unsigned PtrStoreOpc = 0;
20937 unsigned LabelReg = 0;
20938 const int64_t LabelOffset = 1 * PVT.getStoreSize();
20939 Reloc::Model RM = MF->getTarget().getRelocationModel();
20940 bool UseImmLabel = (MF->getTarget().getCodeModel() == CodeModel::Small) &&
20941 (RM == Reloc::Static || RM == Reloc::DynamicNoPIC);
20943 // Prepare IP either in reg or imm.
20944 if (!UseImmLabel) {
20945 PtrStoreOpc = (PVT == MVT::i64) ? X86::MOV64mr : X86::MOV32mr;
20946 const TargetRegisterClass *PtrRC = getRegClassFor(PVT);
20947 LabelReg = MRI.createVirtualRegister(PtrRC);
20948 if (Subtarget->is64Bit()) {
20949 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::LEA64r), LabelReg)
20953 .addMBB(restoreMBB)
20956 const X86InstrInfo *XII = static_cast<const X86InstrInfo*>(TII);
20957 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::LEA32r), LabelReg)
20958 .addReg(XII->getGlobalBaseReg(MF))
20961 .addMBB(restoreMBB, Subtarget->ClassifyBlockAddressReference())
20965 PtrStoreOpc = (PVT == MVT::i64) ? X86::MOV64mi32 : X86::MOV32mi;
20967 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PtrStoreOpc));
20968 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
20969 if (i == X86::AddrDisp)
20970 MIB.addDisp(MI->getOperand(MemOpndSlot + i), LabelOffset);
20972 MIB.addOperand(MI->getOperand(MemOpndSlot + i));
20975 MIB.addReg(LabelReg);
20977 MIB.addMBB(restoreMBB);
20978 MIB.setMemRefs(MMOBegin, MMOEnd);
20980 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::EH_SjLj_Setup))
20981 .addMBB(restoreMBB);
20983 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
20984 MF->getSubtarget().getRegisterInfo());
20985 MIB.addRegMask(RegInfo->getNoPreservedMask());
20986 thisMBB->addSuccessor(mainMBB);
20987 thisMBB->addSuccessor(restoreMBB);
20991 BuildMI(mainMBB, DL, TII->get(X86::MOV32r0), mainDstReg);
20992 mainMBB->addSuccessor(sinkMBB);
20995 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
20996 TII->get(X86::PHI), DstReg)
20997 .addReg(mainDstReg).addMBB(mainMBB)
20998 .addReg(restoreDstReg).addMBB(restoreMBB);
21001 BuildMI(restoreMBB, DL, TII->get(X86::MOV32ri), restoreDstReg).addImm(1);
21002 BuildMI(restoreMBB, DL, TII->get(X86::JMP_4)).addMBB(sinkMBB);
21003 restoreMBB->addSuccessor(sinkMBB);
21005 MI->eraseFromParent();
21009 MachineBasicBlock *
21010 X86TargetLowering::emitEHSjLjLongJmp(MachineInstr *MI,
21011 MachineBasicBlock *MBB) const {
21012 DebugLoc DL = MI->getDebugLoc();
21013 MachineFunction *MF = MBB->getParent();
21014 const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo();
21015 MachineRegisterInfo &MRI = MF->getRegInfo();
21017 // Memory Reference
21018 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
21019 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
21021 MVT PVT = getPointerTy();
21022 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
21023 "Invalid Pointer Size!");
21025 const TargetRegisterClass *RC =
21026 (PVT == MVT::i64) ? &X86::GR64RegClass : &X86::GR32RegClass;
21027 unsigned Tmp = MRI.createVirtualRegister(RC);
21028 // Since FP is only updated here but NOT referenced, it's treated as GPR.
21029 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
21030 MF->getSubtarget().getRegisterInfo());
21031 unsigned FP = (PVT == MVT::i64) ? X86::RBP : X86::EBP;
21032 unsigned SP = RegInfo->getStackRegister();
21034 MachineInstrBuilder MIB;
21036 const int64_t LabelOffset = 1 * PVT.getStoreSize();
21037 const int64_t SPOffset = 2 * PVT.getStoreSize();
21039 unsigned PtrLoadOpc = (PVT == MVT::i64) ? X86::MOV64rm : X86::MOV32rm;
21040 unsigned IJmpOpc = (PVT == MVT::i64) ? X86::JMP64r : X86::JMP32r;
21043 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), FP);
21044 for (unsigned i = 0; i < X86::AddrNumOperands; ++i)
21045 MIB.addOperand(MI->getOperand(i));
21046 MIB.setMemRefs(MMOBegin, MMOEnd);
21048 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), Tmp);
21049 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
21050 if (i == X86::AddrDisp)
21051 MIB.addDisp(MI->getOperand(i), LabelOffset);
21053 MIB.addOperand(MI->getOperand(i));
21055 MIB.setMemRefs(MMOBegin, MMOEnd);
21057 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), SP);
21058 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
21059 if (i == X86::AddrDisp)
21060 MIB.addDisp(MI->getOperand(i), SPOffset);
21062 MIB.addOperand(MI->getOperand(i));
21064 MIB.setMemRefs(MMOBegin, MMOEnd);
21066 BuildMI(*MBB, MI, DL, TII->get(IJmpOpc)).addReg(Tmp);
21068 MI->eraseFromParent();
21072 // Replace 213-type (isel default) FMA3 instructions with 231-type for
21073 // accumulator loops. Writing back to the accumulator allows the coalescer
21074 // to remove extra copies in the loop.
21075 MachineBasicBlock *
21076 X86TargetLowering::emitFMA3Instr(MachineInstr *MI,
21077 MachineBasicBlock *MBB) const {
21078 MachineOperand &AddendOp = MI->getOperand(3);
21080 // Bail out early if the addend isn't a register - we can't switch these.
21081 if (!AddendOp.isReg())
21084 MachineFunction &MF = *MBB->getParent();
21085 MachineRegisterInfo &MRI = MF.getRegInfo();
21087 // Check whether the addend is defined by a PHI:
21088 assert(MRI.hasOneDef(AddendOp.getReg()) && "Multiple defs in SSA?");
21089 MachineInstr &AddendDef = *MRI.def_instr_begin(AddendOp.getReg());
21090 if (!AddendDef.isPHI())
21093 // Look for the following pattern:
21095 // %addend = phi [%entry, 0], [%loop, %result]
21097 // %result<tied1> = FMA213 %m2<tied0>, %m1, %addend
21101 // %addend = phi [%entry, 0], [%loop, %result]
21103 // %result<tied1> = FMA231 %addend<tied0>, %m1, %m2
21105 for (unsigned i = 1, e = AddendDef.getNumOperands(); i < e; i += 2) {
21106 assert(AddendDef.getOperand(i).isReg());
21107 MachineOperand PHISrcOp = AddendDef.getOperand(i);
21108 MachineInstr &PHISrcInst = *MRI.def_instr_begin(PHISrcOp.getReg());
21109 if (&PHISrcInst == MI) {
21110 // Found a matching instruction.
21111 unsigned NewFMAOpc = 0;
21112 switch (MI->getOpcode()) {
21113 case X86::VFMADDPDr213r: NewFMAOpc = X86::VFMADDPDr231r; break;
21114 case X86::VFMADDPSr213r: NewFMAOpc = X86::VFMADDPSr231r; break;
21115 case X86::VFMADDSDr213r: NewFMAOpc = X86::VFMADDSDr231r; break;
21116 case X86::VFMADDSSr213r: NewFMAOpc = X86::VFMADDSSr231r; break;
21117 case X86::VFMSUBPDr213r: NewFMAOpc = X86::VFMSUBPDr231r; break;
21118 case X86::VFMSUBPSr213r: NewFMAOpc = X86::VFMSUBPSr231r; break;
21119 case X86::VFMSUBSDr213r: NewFMAOpc = X86::VFMSUBSDr231r; break;
21120 case X86::VFMSUBSSr213r: NewFMAOpc = X86::VFMSUBSSr231r; break;
21121 case X86::VFNMADDPDr213r: NewFMAOpc = X86::VFNMADDPDr231r; break;
21122 case X86::VFNMADDPSr213r: NewFMAOpc = X86::VFNMADDPSr231r; break;
21123 case X86::VFNMADDSDr213r: NewFMAOpc = X86::VFNMADDSDr231r; break;
21124 case X86::VFNMADDSSr213r: NewFMAOpc = X86::VFNMADDSSr231r; break;
21125 case X86::VFNMSUBPDr213r: NewFMAOpc = X86::VFNMSUBPDr231r; break;
21126 case X86::VFNMSUBPSr213r: NewFMAOpc = X86::VFNMSUBPSr231r; break;
21127 case X86::VFNMSUBSDr213r: NewFMAOpc = X86::VFNMSUBSDr231r; break;
21128 case X86::VFNMSUBSSr213r: NewFMAOpc = X86::VFNMSUBSSr231r; break;
21129 case X86::VFMADDSUBPDr213r: NewFMAOpc = X86::VFMADDSUBPDr231r; break;
21130 case X86::VFMADDSUBPSr213r: NewFMAOpc = X86::VFMADDSUBPSr231r; break;
21131 case X86::VFMSUBADDPDr213r: NewFMAOpc = X86::VFMSUBADDPDr231r; break;
21132 case X86::VFMSUBADDPSr213r: NewFMAOpc = X86::VFMSUBADDPSr231r; break;
21134 case X86::VFMADDPDr213rY: NewFMAOpc = X86::VFMADDPDr231rY; break;
21135 case X86::VFMADDPSr213rY: NewFMAOpc = X86::VFMADDPSr231rY; break;
21136 case X86::VFMSUBPDr213rY: NewFMAOpc = X86::VFMSUBPDr231rY; break;
21137 case X86::VFMSUBPSr213rY: NewFMAOpc = X86::VFMSUBPSr231rY; break;
21138 case X86::VFNMADDPDr213rY: NewFMAOpc = X86::VFNMADDPDr231rY; break;
21139 case X86::VFNMADDPSr213rY: NewFMAOpc = X86::VFNMADDPSr231rY; break;
21140 case X86::VFNMSUBPDr213rY: NewFMAOpc = X86::VFNMSUBPDr231rY; break;
21141 case X86::VFNMSUBPSr213rY: NewFMAOpc = X86::VFNMSUBPSr231rY; break;
21142 case X86::VFMADDSUBPDr213rY: NewFMAOpc = X86::VFMADDSUBPDr231rY; break;
21143 case X86::VFMADDSUBPSr213rY: NewFMAOpc = X86::VFMADDSUBPSr231rY; break;
21144 case X86::VFMSUBADDPDr213rY: NewFMAOpc = X86::VFMSUBADDPDr231rY; break;
21145 case X86::VFMSUBADDPSr213rY: NewFMAOpc = X86::VFMSUBADDPSr231rY; break;
21146 default: llvm_unreachable("Unrecognized FMA variant.");
21149 const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo();
21150 MachineInstrBuilder MIB =
21151 BuildMI(MF, MI->getDebugLoc(), TII.get(NewFMAOpc))
21152 .addOperand(MI->getOperand(0))
21153 .addOperand(MI->getOperand(3))
21154 .addOperand(MI->getOperand(2))
21155 .addOperand(MI->getOperand(1));
21156 MBB->insert(MachineBasicBlock::iterator(MI), MIB);
21157 MI->eraseFromParent();
21164 MachineBasicBlock *
21165 X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
21166 MachineBasicBlock *BB) const {
21167 switch (MI->getOpcode()) {
21168 default: llvm_unreachable("Unexpected instr type to insert");
21169 case X86::TAILJMPd64:
21170 case X86::TAILJMPr64:
21171 case X86::TAILJMPm64:
21172 llvm_unreachable("TAILJMP64 would not be touched here.");
21173 case X86::TCRETURNdi64:
21174 case X86::TCRETURNri64:
21175 case X86::TCRETURNmi64:
21177 case X86::WIN_ALLOCA:
21178 return EmitLoweredWinAlloca(MI, BB);
21179 case X86::SEG_ALLOCA_32:
21180 case X86::SEG_ALLOCA_64:
21181 return EmitLoweredSegAlloca(MI, BB);
21182 case X86::TLSCall_32:
21183 case X86::TLSCall_64:
21184 return EmitLoweredTLSCall(MI, BB);
21185 case X86::CMOV_GR8:
21186 case X86::CMOV_FR32:
21187 case X86::CMOV_FR64:
21188 case X86::CMOV_V4F32:
21189 case X86::CMOV_V2F64:
21190 case X86::CMOV_V2I64:
21191 case X86::CMOV_V8F32:
21192 case X86::CMOV_V4F64:
21193 case X86::CMOV_V4I64:
21194 case X86::CMOV_V16F32:
21195 case X86::CMOV_V8F64:
21196 case X86::CMOV_V8I64:
21197 case X86::CMOV_GR16:
21198 case X86::CMOV_GR32:
21199 case X86::CMOV_RFP32:
21200 case X86::CMOV_RFP64:
21201 case X86::CMOV_RFP80:
21202 return EmitLoweredSelect(MI, BB);
21204 case X86::FP32_TO_INT16_IN_MEM:
21205 case X86::FP32_TO_INT32_IN_MEM:
21206 case X86::FP32_TO_INT64_IN_MEM:
21207 case X86::FP64_TO_INT16_IN_MEM:
21208 case X86::FP64_TO_INT32_IN_MEM:
21209 case X86::FP64_TO_INT64_IN_MEM:
21210 case X86::FP80_TO_INT16_IN_MEM:
21211 case X86::FP80_TO_INT32_IN_MEM:
21212 case X86::FP80_TO_INT64_IN_MEM: {
21213 MachineFunction *F = BB->getParent();
21214 const TargetInstrInfo *TII = F->getSubtarget().getInstrInfo();
21215 DebugLoc DL = MI->getDebugLoc();
21217 // Change the floating point control register to use "round towards zero"
21218 // mode when truncating to an integer value.
21219 int CWFrameIdx = F->getFrameInfo()->CreateStackObject(2, 2, false);
21220 addFrameReference(BuildMI(*BB, MI, DL,
21221 TII->get(X86::FNSTCW16m)), CWFrameIdx);
21223 // Load the old value of the high byte of the control word...
21225 F->getRegInfo().createVirtualRegister(&X86::GR16RegClass);
21226 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16rm), OldCW),
21229 // Set the high part to be round to zero...
21230 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mi)), CWFrameIdx)
21233 // Reload the modified control word now...
21234 addFrameReference(BuildMI(*BB, MI, DL,
21235 TII->get(X86::FLDCW16m)), CWFrameIdx);
21237 // Restore the memory image of control word to original value
21238 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mr)), CWFrameIdx)
21241 // Get the X86 opcode to use.
21243 switch (MI->getOpcode()) {
21244 default: llvm_unreachable("illegal opcode!");
21245 case X86::FP32_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m32; break;
21246 case X86::FP32_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m32; break;
21247 case X86::FP32_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m32; break;
21248 case X86::FP64_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m64; break;
21249 case X86::FP64_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m64; break;
21250 case X86::FP64_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m64; break;
21251 case X86::FP80_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m80; break;
21252 case X86::FP80_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m80; break;
21253 case X86::FP80_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m80; break;
21257 MachineOperand &Op = MI->getOperand(0);
21259 AM.BaseType = X86AddressMode::RegBase;
21260 AM.Base.Reg = Op.getReg();
21262 AM.BaseType = X86AddressMode::FrameIndexBase;
21263 AM.Base.FrameIndex = Op.getIndex();
21265 Op = MI->getOperand(1);
21267 AM.Scale = Op.getImm();
21268 Op = MI->getOperand(2);
21270 AM.IndexReg = Op.getImm();
21271 Op = MI->getOperand(3);
21272 if (Op.isGlobal()) {
21273 AM.GV = Op.getGlobal();
21275 AM.Disp = Op.getImm();
21277 addFullAddress(BuildMI(*BB, MI, DL, TII->get(Opc)), AM)
21278 .addReg(MI->getOperand(X86::AddrNumOperands).getReg());
21280 // Reload the original control word now.
21281 addFrameReference(BuildMI(*BB, MI, DL,
21282 TII->get(X86::FLDCW16m)), CWFrameIdx);
21284 MI->eraseFromParent(); // The pseudo instruction is gone now.
21287 // String/text processing lowering.
21288 case X86::PCMPISTRM128REG:
21289 case X86::VPCMPISTRM128REG:
21290 case X86::PCMPISTRM128MEM:
21291 case X86::VPCMPISTRM128MEM:
21292 case X86::PCMPESTRM128REG:
21293 case X86::VPCMPESTRM128REG:
21294 case X86::PCMPESTRM128MEM:
21295 case X86::VPCMPESTRM128MEM:
21296 assert(Subtarget->hasSSE42() &&
21297 "Target must have SSE4.2 or AVX features enabled");
21298 return EmitPCMPSTRM(MI, BB, BB->getParent()->getSubtarget().getInstrInfo());
21300 // String/text processing lowering.
21301 case X86::PCMPISTRIREG:
21302 case X86::VPCMPISTRIREG:
21303 case X86::PCMPISTRIMEM:
21304 case X86::VPCMPISTRIMEM:
21305 case X86::PCMPESTRIREG:
21306 case X86::VPCMPESTRIREG:
21307 case X86::PCMPESTRIMEM:
21308 case X86::VPCMPESTRIMEM:
21309 assert(Subtarget->hasSSE42() &&
21310 "Target must have SSE4.2 or AVX features enabled");
21311 return EmitPCMPSTRI(MI, BB, BB->getParent()->getSubtarget().getInstrInfo());
21313 // Thread synchronization.
21315 return EmitMonitor(MI, BB, BB->getParent()->getSubtarget().getInstrInfo(),
21320 return EmitXBegin(MI, BB, BB->getParent()->getSubtarget().getInstrInfo());
21322 case X86::VASTART_SAVE_XMM_REGS:
21323 return EmitVAStartSaveXMMRegsWithCustomInserter(MI, BB);
21325 case X86::VAARG_64:
21326 return EmitVAARG64WithCustomInserter(MI, BB);
21328 case X86::EH_SjLj_SetJmp32:
21329 case X86::EH_SjLj_SetJmp64:
21330 return emitEHSjLjSetJmp(MI, BB);
21332 case X86::EH_SjLj_LongJmp32:
21333 case X86::EH_SjLj_LongJmp64:
21334 return emitEHSjLjLongJmp(MI, BB);
21336 case TargetOpcode::STACKMAP:
21337 case TargetOpcode::PATCHPOINT:
21338 return emitPatchPoint(MI, BB);
21340 case X86::VFMADDPDr213r:
21341 case X86::VFMADDPSr213r:
21342 case X86::VFMADDSDr213r:
21343 case X86::VFMADDSSr213r:
21344 case X86::VFMSUBPDr213r:
21345 case X86::VFMSUBPSr213r:
21346 case X86::VFMSUBSDr213r:
21347 case X86::VFMSUBSSr213r:
21348 case X86::VFNMADDPDr213r:
21349 case X86::VFNMADDPSr213r:
21350 case X86::VFNMADDSDr213r:
21351 case X86::VFNMADDSSr213r:
21352 case X86::VFNMSUBPDr213r:
21353 case X86::VFNMSUBPSr213r:
21354 case X86::VFNMSUBSDr213r:
21355 case X86::VFNMSUBSSr213r:
21356 case X86::VFMADDSUBPDr213r:
21357 case X86::VFMADDSUBPSr213r:
21358 case X86::VFMSUBADDPDr213r:
21359 case X86::VFMSUBADDPSr213r:
21360 case X86::VFMADDPDr213rY:
21361 case X86::VFMADDPSr213rY:
21362 case X86::VFMSUBPDr213rY:
21363 case X86::VFMSUBPSr213rY:
21364 case X86::VFNMADDPDr213rY:
21365 case X86::VFNMADDPSr213rY:
21366 case X86::VFNMSUBPDr213rY:
21367 case X86::VFNMSUBPSr213rY:
21368 case X86::VFMADDSUBPDr213rY:
21369 case X86::VFMADDSUBPSr213rY:
21370 case X86::VFMSUBADDPDr213rY:
21371 case X86::VFMSUBADDPSr213rY:
21372 return emitFMA3Instr(MI, BB);
21376 //===----------------------------------------------------------------------===//
21377 // X86 Optimization Hooks
21378 //===----------------------------------------------------------------------===//
21380 void X86TargetLowering::computeKnownBitsForTargetNode(const SDValue Op,
21383 const SelectionDAG &DAG,
21384 unsigned Depth) const {
21385 unsigned BitWidth = KnownZero.getBitWidth();
21386 unsigned Opc = Op.getOpcode();
21387 assert((Opc >= ISD::BUILTIN_OP_END ||
21388 Opc == ISD::INTRINSIC_WO_CHAIN ||
21389 Opc == ISD::INTRINSIC_W_CHAIN ||
21390 Opc == ISD::INTRINSIC_VOID) &&
21391 "Should use MaskedValueIsZero if you don't know whether Op"
21392 " is a target node!");
21394 KnownZero = KnownOne = APInt(BitWidth, 0); // Don't know anything.
21408 // These nodes' second result is a boolean.
21409 if (Op.getResNo() == 0)
21412 case X86ISD::SETCC:
21413 KnownZero |= APInt::getHighBitsSet(BitWidth, BitWidth - 1);
21415 case ISD::INTRINSIC_WO_CHAIN: {
21416 unsigned IntId = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
21417 unsigned NumLoBits = 0;
21420 case Intrinsic::x86_sse_movmsk_ps:
21421 case Intrinsic::x86_avx_movmsk_ps_256:
21422 case Intrinsic::x86_sse2_movmsk_pd:
21423 case Intrinsic::x86_avx_movmsk_pd_256:
21424 case Intrinsic::x86_mmx_pmovmskb:
21425 case Intrinsic::x86_sse2_pmovmskb_128:
21426 case Intrinsic::x86_avx2_pmovmskb: {
21427 // High bits of movmskp{s|d}, pmovmskb are known zero.
21429 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
21430 case Intrinsic::x86_sse_movmsk_ps: NumLoBits = 4; break;
21431 case Intrinsic::x86_avx_movmsk_ps_256: NumLoBits = 8; break;
21432 case Intrinsic::x86_sse2_movmsk_pd: NumLoBits = 2; break;
21433 case Intrinsic::x86_avx_movmsk_pd_256: NumLoBits = 4; break;
21434 case Intrinsic::x86_mmx_pmovmskb: NumLoBits = 8; break;
21435 case Intrinsic::x86_sse2_pmovmskb_128: NumLoBits = 16; break;
21436 case Intrinsic::x86_avx2_pmovmskb: NumLoBits = 32; break;
21438 KnownZero = APInt::getHighBitsSet(BitWidth, BitWidth - NumLoBits);
21447 unsigned X86TargetLowering::ComputeNumSignBitsForTargetNode(
21449 const SelectionDAG &,
21450 unsigned Depth) const {
21451 // SETCC_CARRY sets the dest to ~0 for true or 0 for false.
21452 if (Op.getOpcode() == X86ISD::SETCC_CARRY)
21453 return Op.getValueType().getScalarType().getSizeInBits();
21459 /// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the
21460 /// node is a GlobalAddress + offset.
21461 bool X86TargetLowering::isGAPlusOffset(SDNode *N,
21462 const GlobalValue* &GA,
21463 int64_t &Offset) const {
21464 if (N->getOpcode() == X86ISD::Wrapper) {
21465 if (isa<GlobalAddressSDNode>(N->getOperand(0))) {
21466 GA = cast<GlobalAddressSDNode>(N->getOperand(0))->getGlobal();
21467 Offset = cast<GlobalAddressSDNode>(N->getOperand(0))->getOffset();
21471 return TargetLowering::isGAPlusOffset(N, GA, Offset);
21474 /// isShuffleHigh128VectorInsertLow - Checks whether the shuffle node is the
21475 /// same as extracting the high 128-bit part of 256-bit vector and then
21476 /// inserting the result into the low part of a new 256-bit vector
21477 static bool isShuffleHigh128VectorInsertLow(ShuffleVectorSDNode *SVOp) {
21478 EVT VT = SVOp->getValueType(0);
21479 unsigned NumElems = VT.getVectorNumElements();
21481 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
21482 for (unsigned i = 0, j = NumElems/2; i != NumElems/2; ++i, ++j)
21483 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) ||
21484 SVOp->getMaskElt(j) >= 0)
21490 /// isShuffleLow128VectorInsertHigh - Checks whether the shuffle node is the
21491 /// same as extracting the low 128-bit part of 256-bit vector and then
21492 /// inserting the result into the high part of a new 256-bit vector
21493 static bool isShuffleLow128VectorInsertHigh(ShuffleVectorSDNode *SVOp) {
21494 EVT VT = SVOp->getValueType(0);
21495 unsigned NumElems = VT.getVectorNumElements();
21497 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
21498 for (unsigned i = NumElems/2, j = 0; i != NumElems; ++i, ++j)
21499 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) ||
21500 SVOp->getMaskElt(j) >= 0)
21506 /// PerformShuffleCombine256 - Performs shuffle combines for 256-bit vectors.
21507 static SDValue PerformShuffleCombine256(SDNode *N, SelectionDAG &DAG,
21508 TargetLowering::DAGCombinerInfo &DCI,
21509 const X86Subtarget* Subtarget) {
21511 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
21512 SDValue V1 = SVOp->getOperand(0);
21513 SDValue V2 = SVOp->getOperand(1);
21514 EVT VT = SVOp->getValueType(0);
21515 unsigned NumElems = VT.getVectorNumElements();
21517 if (V1.getOpcode() == ISD::CONCAT_VECTORS &&
21518 V2.getOpcode() == ISD::CONCAT_VECTORS) {
21522 // V UNDEF BUILD_VECTOR UNDEF
21524 // CONCAT_VECTOR CONCAT_VECTOR
21527 // RESULT: V + zero extended
21529 if (V2.getOperand(0).getOpcode() != ISD::BUILD_VECTOR ||
21530 V2.getOperand(1).getOpcode() != ISD::UNDEF ||
21531 V1.getOperand(1).getOpcode() != ISD::UNDEF)
21534 if (!ISD::isBuildVectorAllZeros(V2.getOperand(0).getNode()))
21537 // To match the shuffle mask, the first half of the mask should
21538 // be exactly the first vector, and all the rest a splat with the
21539 // first element of the second one.
21540 for (unsigned i = 0; i != NumElems/2; ++i)
21541 if (!isUndefOrEqual(SVOp->getMaskElt(i), i) ||
21542 !isUndefOrEqual(SVOp->getMaskElt(i+NumElems/2), NumElems))
21545 // If V1 is coming from a vector load then just fold to a VZEXT_LOAD.
21546 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(V1.getOperand(0))) {
21547 if (Ld->hasNUsesOfValue(1, 0)) {
21548 SDVTList Tys = DAG.getVTList(MVT::v4i64, MVT::Other);
21549 SDValue Ops[] = { Ld->getChain(), Ld->getBasePtr() };
21551 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, dl, Tys, Ops,
21553 Ld->getPointerInfo(),
21554 Ld->getAlignment(),
21555 false/*isVolatile*/, true/*ReadMem*/,
21556 false/*WriteMem*/);
21558 // Make sure the newly-created LOAD is in the same position as Ld in
21559 // terms of dependency. We create a TokenFactor for Ld and ResNode,
21560 // and update uses of Ld's output chain to use the TokenFactor.
21561 if (Ld->hasAnyUseOfValue(1)) {
21562 SDValue NewChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
21563 SDValue(Ld, 1), SDValue(ResNode.getNode(), 1));
21564 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), NewChain);
21565 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(Ld, 1),
21566 SDValue(ResNode.getNode(), 1));
21569 return DAG.getNode(ISD::BITCAST, dl, VT, ResNode);
21573 // Emit a zeroed vector and insert the desired subvector on its
21575 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
21576 SDValue InsV = Insert128BitVector(Zeros, V1.getOperand(0), 0, DAG, dl);
21577 return DCI.CombineTo(N, InsV);
21580 //===--------------------------------------------------------------------===//
21581 // Combine some shuffles into subvector extracts and inserts:
21584 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
21585 if (isShuffleHigh128VectorInsertLow(SVOp)) {
21586 SDValue V = Extract128BitVector(V1, NumElems/2, DAG, dl);
21587 SDValue InsV = Insert128BitVector(DAG.getUNDEF(VT), V, 0, DAG, dl);
21588 return DCI.CombineTo(N, InsV);
21591 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
21592 if (isShuffleLow128VectorInsertHigh(SVOp)) {
21593 SDValue V = Extract128BitVector(V1, 0, DAG, dl);
21594 SDValue InsV = Insert128BitVector(DAG.getUNDEF(VT), V, NumElems/2, DAG, dl);
21595 return DCI.CombineTo(N, InsV);
21601 /// \brief Combine an arbitrary chain of shuffles into a single instruction if
21604 /// This is the leaf of the recursive combinine below. When we have found some
21605 /// chain of single-use x86 shuffle instructions and accumulated the combined
21606 /// shuffle mask represented by them, this will try to pattern match that mask
21607 /// into either a single instruction if there is a special purpose instruction
21608 /// for this operation, or into a PSHUFB instruction which is a fully general
21609 /// instruction but should only be used to replace chains over a certain depth.
21610 static bool combineX86ShuffleChain(SDValue Op, SDValue Root, ArrayRef<int> Mask,
21611 int Depth, bool HasPSHUFB, SelectionDAG &DAG,
21612 TargetLowering::DAGCombinerInfo &DCI,
21613 const X86Subtarget *Subtarget) {
21614 assert(!Mask.empty() && "Cannot combine an empty shuffle mask!");
21616 // Find the operand that enters the chain. Note that multiple uses are OK
21617 // here, we're not going to remove the operand we find.
21618 SDValue Input = Op.getOperand(0);
21619 while (Input.getOpcode() == ISD::BITCAST)
21620 Input = Input.getOperand(0);
21622 MVT VT = Input.getSimpleValueType();
21623 MVT RootVT = Root.getSimpleValueType();
21626 // Just remove no-op shuffle masks.
21627 if (Mask.size() == 1) {
21628 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Input),
21633 // Use the float domain if the operand type is a floating point type.
21634 bool FloatDomain = VT.isFloatingPoint();
21636 // For floating point shuffles, we don't have free copies in the shuffle
21637 // instructions or the ability to load as part of the instruction, so
21638 // canonicalize their shuffles to UNPCK or MOV variants.
21640 // Note that even with AVX we prefer the PSHUFD form of shuffle for integer
21641 // vectors because it can have a load folded into it that UNPCK cannot. This
21642 // doesn't preclude something switching to the shorter encoding post-RA.
21644 if (Mask.equals(0, 0) || Mask.equals(1, 1)) {
21645 bool Lo = Mask.equals(0, 0);
21648 // Check if we have SSE3 which will let us use MOVDDUP. That instruction
21649 // is no slower than UNPCKLPD but has the option to fold the input operand
21650 // into even an unaligned memory load.
21651 if (Lo && Subtarget->hasSSE3()) {
21652 Shuffle = X86ISD::MOVDDUP;
21653 ShuffleVT = MVT::v2f64;
21655 // We have MOVLHPS and MOVHLPS throughout SSE and they encode smaller
21656 // than the UNPCK variants.
21657 Shuffle = Lo ? X86ISD::MOVLHPS : X86ISD::MOVHLPS;
21658 ShuffleVT = MVT::v4f32;
21660 if (Depth == 1 && Root->getOpcode() == Shuffle)
21661 return false; // Nothing to do!
21662 Op = DAG.getNode(ISD::BITCAST, DL, ShuffleVT, Input);
21663 DCI.AddToWorklist(Op.getNode());
21664 if (Shuffle == X86ISD::MOVDDUP)
21665 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op);
21667 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op, Op);
21668 DCI.AddToWorklist(Op.getNode());
21669 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Op),
21673 if (Subtarget->hasSSE3() &&
21674 (Mask.equals(0, 0, 2, 2) || Mask.equals(1, 1, 3, 3))) {
21675 bool Lo = Mask.equals(0, 0, 2, 2);
21676 unsigned Shuffle = Lo ? X86ISD::MOVSLDUP : X86ISD::MOVSHDUP;
21677 MVT ShuffleVT = MVT::v4f32;
21678 if (Depth == 1 && Root->getOpcode() == Shuffle)
21679 return false; // Nothing to do!
21680 Op = DAG.getNode(ISD::BITCAST, DL, ShuffleVT, Input);
21681 DCI.AddToWorklist(Op.getNode());
21682 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op);
21683 DCI.AddToWorklist(Op.getNode());
21684 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Op),
21688 if (Mask.equals(0, 0, 1, 1) || Mask.equals(2, 2, 3, 3)) {
21689 bool Lo = Mask.equals(0, 0, 1, 1);
21690 unsigned Shuffle = Lo ? X86ISD::UNPCKL : X86ISD::UNPCKH;
21691 MVT ShuffleVT = MVT::v4f32;
21692 if (Depth == 1 && Root->getOpcode() == Shuffle)
21693 return false; // Nothing to do!
21694 Op = DAG.getNode(ISD::BITCAST, DL, ShuffleVT, Input);
21695 DCI.AddToWorklist(Op.getNode());
21696 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op, Op);
21697 DCI.AddToWorklist(Op.getNode());
21698 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Op),
21704 // We always canonicalize the 8 x i16 and 16 x i8 shuffles into their UNPCK
21705 // variants as none of these have single-instruction variants that are
21706 // superior to the UNPCK formulation.
21707 if (!FloatDomain &&
21708 (Mask.equals(0, 0, 1, 1, 2, 2, 3, 3) ||
21709 Mask.equals(4, 4, 5, 5, 6, 6, 7, 7) ||
21710 Mask.equals(0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7) ||
21711 Mask.equals(8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15,
21713 bool Lo = Mask[0] == 0;
21714 unsigned Shuffle = Lo ? X86ISD::UNPCKL : X86ISD::UNPCKH;
21715 if (Depth == 1 && Root->getOpcode() == Shuffle)
21716 return false; // Nothing to do!
21718 switch (Mask.size()) {
21720 ShuffleVT = MVT::v8i16;
21723 ShuffleVT = MVT::v16i8;
21726 llvm_unreachable("Impossible mask size!");
21728 Op = DAG.getNode(ISD::BITCAST, DL, ShuffleVT, Input);
21729 DCI.AddToWorklist(Op.getNode());
21730 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op, Op);
21731 DCI.AddToWorklist(Op.getNode());
21732 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Op),
21737 // Don't try to re-form single instruction chains under any circumstances now
21738 // that we've done encoding canonicalization for them.
21742 // If we have 3 or more shuffle instructions or a chain involving PSHUFB, we
21743 // can replace them with a single PSHUFB instruction profitably. Intel's
21744 // manuals suggest only using PSHUFB if doing so replacing 5 instructions, but
21745 // in practice PSHUFB tends to be *very* fast so we're more aggressive.
21746 if ((Depth >= 3 || HasPSHUFB) && Subtarget->hasSSSE3()) {
21747 SmallVector<SDValue, 16> PSHUFBMask;
21748 assert(Mask.size() <= 16 && "Can't shuffle elements smaller than bytes!");
21749 int Ratio = 16 / Mask.size();
21750 for (unsigned i = 0; i < 16; ++i) {
21751 if (Mask[i / Ratio] == SM_SentinelUndef) {
21752 PSHUFBMask.push_back(DAG.getUNDEF(MVT::i8));
21755 int M = Mask[i / Ratio] != SM_SentinelZero
21756 ? Ratio * Mask[i / Ratio] + i % Ratio
21758 PSHUFBMask.push_back(DAG.getConstant(M, MVT::i8));
21760 Op = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, Input);
21761 DCI.AddToWorklist(Op.getNode());
21762 SDValue PSHUFBMaskOp =
21763 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v16i8, PSHUFBMask);
21764 DCI.AddToWorklist(PSHUFBMaskOp.getNode());
21765 Op = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8, Op, PSHUFBMaskOp);
21766 DCI.AddToWorklist(Op.getNode());
21767 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Op),
21772 // Failed to find any combines.
21776 /// \brief Fully generic combining of x86 shuffle instructions.
21778 /// This should be the last combine run over the x86 shuffle instructions. Once
21779 /// they have been fully optimized, this will recursively consider all chains
21780 /// of single-use shuffle instructions, build a generic model of the cumulative
21781 /// shuffle operation, and check for simpler instructions which implement this
21782 /// operation. We use this primarily for two purposes:
21784 /// 1) Collapse generic shuffles to specialized single instructions when
21785 /// equivalent. In most cases, this is just an encoding size win, but
21786 /// sometimes we will collapse multiple generic shuffles into a single
21787 /// special-purpose shuffle.
21788 /// 2) Look for sequences of shuffle instructions with 3 or more total
21789 /// instructions, and replace them with the slightly more expensive SSSE3
21790 /// PSHUFB instruction if available. We do this as the last combining step
21791 /// to ensure we avoid using PSHUFB if we can implement the shuffle with
21792 /// a suitable short sequence of other instructions. The PHUFB will either
21793 /// use a register or have to read from memory and so is slightly (but only
21794 /// slightly) more expensive than the other shuffle instructions.
21796 /// Because this is inherently a quadratic operation (for each shuffle in
21797 /// a chain, we recurse up the chain), the depth is limited to 8 instructions.
21798 /// This should never be an issue in practice as the shuffle lowering doesn't
21799 /// produce sequences of more than 8 instructions.
21801 /// FIXME: We will currently miss some cases where the redundant shuffling
21802 /// would simplify under the threshold for PSHUFB formation because of
21803 /// combine-ordering. To fix this, we should do the redundant instruction
21804 /// combining in this recursive walk.
21805 static bool combineX86ShufflesRecursively(SDValue Op, SDValue Root,
21806 ArrayRef<int> RootMask,
21807 int Depth, bool HasPSHUFB,
21809 TargetLowering::DAGCombinerInfo &DCI,
21810 const X86Subtarget *Subtarget) {
21811 // Bound the depth of our recursive combine because this is ultimately
21812 // quadratic in nature.
21816 // Directly rip through bitcasts to find the underlying operand.
21817 while (Op.getOpcode() == ISD::BITCAST && Op.getOperand(0).hasOneUse())
21818 Op = Op.getOperand(0);
21820 MVT VT = Op.getSimpleValueType();
21821 if (!VT.isVector())
21822 return false; // Bail if we hit a non-vector.
21823 // FIXME: This routine should be taught about 256-bit shuffles, or a 256-bit
21824 // version should be added.
21825 if (VT.getSizeInBits() != 128)
21828 assert(Root.getSimpleValueType().isVector() &&
21829 "Shuffles operate on vector types!");
21830 assert(VT.getSizeInBits() == Root.getSimpleValueType().getSizeInBits() &&
21831 "Can only combine shuffles of the same vector register size.");
21833 if (!isTargetShuffle(Op.getOpcode()))
21835 SmallVector<int, 16> OpMask;
21837 bool HaveMask = getTargetShuffleMask(Op.getNode(), VT, OpMask, IsUnary);
21838 // We only can combine unary shuffles which we can decode the mask for.
21839 if (!HaveMask || !IsUnary)
21842 assert(VT.getVectorNumElements() == OpMask.size() &&
21843 "Different mask size from vector size!");
21844 assert(((RootMask.size() > OpMask.size() &&
21845 RootMask.size() % OpMask.size() == 0) ||
21846 (OpMask.size() > RootMask.size() &&
21847 OpMask.size() % RootMask.size() == 0) ||
21848 OpMask.size() == RootMask.size()) &&
21849 "The smaller number of elements must divide the larger.");
21850 int RootRatio = std::max<int>(1, OpMask.size() / RootMask.size());
21851 int OpRatio = std::max<int>(1, RootMask.size() / OpMask.size());
21852 assert(((RootRatio == 1 && OpRatio == 1) ||
21853 (RootRatio == 1) != (OpRatio == 1)) &&
21854 "Must not have a ratio for both incoming and op masks!");
21856 SmallVector<int, 16> Mask;
21857 Mask.reserve(std::max(OpMask.size(), RootMask.size()));
21859 // Merge this shuffle operation's mask into our accumulated mask. Note that
21860 // this shuffle's mask will be the first applied to the input, followed by the
21861 // root mask to get us all the way to the root value arrangement. The reason
21862 // for this order is that we are recursing up the operation chain.
21863 for (int i = 0, e = std::max(OpMask.size(), RootMask.size()); i < e; ++i) {
21864 int RootIdx = i / RootRatio;
21865 if (RootMask[RootIdx] < 0) {
21866 // This is a zero or undef lane, we're done.
21867 Mask.push_back(RootMask[RootIdx]);
21871 int RootMaskedIdx = RootMask[RootIdx] * RootRatio + i % RootRatio;
21872 int OpIdx = RootMaskedIdx / OpRatio;
21873 if (OpMask[OpIdx] < 0) {
21874 // The incoming lanes are zero or undef, it doesn't matter which ones we
21876 Mask.push_back(OpMask[OpIdx]);
21880 // Ok, we have non-zero lanes, map them through.
21881 Mask.push_back(OpMask[OpIdx] * OpRatio +
21882 RootMaskedIdx % OpRatio);
21885 // See if we can recurse into the operand to combine more things.
21886 switch (Op.getOpcode()) {
21887 case X86ISD::PSHUFB:
21889 case X86ISD::PSHUFD:
21890 case X86ISD::PSHUFHW:
21891 case X86ISD::PSHUFLW:
21892 if (Op.getOperand(0).hasOneUse() &&
21893 combineX86ShufflesRecursively(Op.getOperand(0), Root, Mask, Depth + 1,
21894 HasPSHUFB, DAG, DCI, Subtarget))
21898 case X86ISD::UNPCKL:
21899 case X86ISD::UNPCKH:
21900 assert(Op.getOperand(0) == Op.getOperand(1) && "We only combine unary shuffles!");
21901 // We can't check for single use, we have to check that this shuffle is the only user.
21902 if (Op->isOnlyUserOf(Op.getOperand(0).getNode()) &&
21903 combineX86ShufflesRecursively(Op.getOperand(0), Root, Mask, Depth + 1,
21904 HasPSHUFB, DAG, DCI, Subtarget))
21909 // Minor canonicalization of the accumulated shuffle mask to make it easier
21910 // to match below. All this does is detect masks with squential pairs of
21911 // elements, and shrink them to the half-width mask. It does this in a loop
21912 // so it will reduce the size of the mask to the minimal width mask which
21913 // performs an equivalent shuffle.
21914 SmallVector<int, 16> WidenedMask;
21915 while (Mask.size() > 1 && canWidenShuffleElements(Mask, WidenedMask)) {
21916 Mask = std::move(WidenedMask);
21917 WidenedMask.clear();
21920 return combineX86ShuffleChain(Op, Root, Mask, Depth, HasPSHUFB, DAG, DCI,
21924 /// \brief Get the PSHUF-style mask from PSHUF node.
21926 /// This is a very minor wrapper around getTargetShuffleMask to easy forming v4
21927 /// PSHUF-style masks that can be reused with such instructions.
21928 static SmallVector<int, 4> getPSHUFShuffleMask(SDValue N) {
21929 SmallVector<int, 4> Mask;
21931 bool HaveMask = getTargetShuffleMask(N.getNode(), N.getSimpleValueType(), Mask, IsUnary);
21935 switch (N.getOpcode()) {
21936 case X86ISD::PSHUFD:
21938 case X86ISD::PSHUFLW:
21941 case X86ISD::PSHUFHW:
21942 Mask.erase(Mask.begin(), Mask.begin() + 4);
21943 for (int &M : Mask)
21947 llvm_unreachable("No valid shuffle instruction found!");
21951 /// \brief Search for a combinable shuffle across a chain ending in pshufd.
21953 /// We walk up the chain and look for a combinable shuffle, skipping over
21954 /// shuffles that we could hoist this shuffle's transformation past without
21955 /// altering anything.
21957 combineRedundantDWordShuffle(SDValue N, MutableArrayRef<int> Mask,
21959 TargetLowering::DAGCombinerInfo &DCI) {
21960 assert(N.getOpcode() == X86ISD::PSHUFD &&
21961 "Called with something other than an x86 128-bit half shuffle!");
21964 // Walk up a single-use chain looking for a combinable shuffle. Keep a stack
21965 // of the shuffles in the chain so that we can form a fresh chain to replace
21967 SmallVector<SDValue, 8> Chain;
21968 SDValue V = N.getOperand(0);
21969 for (; V.hasOneUse(); V = V.getOperand(0)) {
21970 switch (V.getOpcode()) {
21972 return SDValue(); // Nothing combined!
21975 // Skip bitcasts as we always know the type for the target specific
21979 case X86ISD::PSHUFD:
21980 // Found another dword shuffle.
21983 case X86ISD::PSHUFLW:
21984 // Check that the low words (being shuffled) are the identity in the
21985 // dword shuffle, and the high words are self-contained.
21986 if (Mask[0] != 0 || Mask[1] != 1 ||
21987 !(Mask[2] >= 2 && Mask[2] < 4 && Mask[3] >= 2 && Mask[3] < 4))
21990 Chain.push_back(V);
21993 case X86ISD::PSHUFHW:
21994 // Check that the high words (being shuffled) are the identity in the
21995 // dword shuffle, and the low words are self-contained.
21996 if (Mask[2] != 2 || Mask[3] != 3 ||
21997 !(Mask[0] >= 0 && Mask[0] < 2 && Mask[1] >= 0 && Mask[1] < 2))
22000 Chain.push_back(V);
22003 case X86ISD::UNPCKL:
22004 case X86ISD::UNPCKH:
22005 // For either i8 -> i16 or i16 -> i32 unpacks, we can combine a dword
22006 // shuffle into a preceding word shuffle.
22007 if (V.getValueType() != MVT::v16i8 && V.getValueType() != MVT::v8i16)
22010 // Search for a half-shuffle which we can combine with.
22011 unsigned CombineOp =
22012 V.getOpcode() == X86ISD::UNPCKL ? X86ISD::PSHUFLW : X86ISD::PSHUFHW;
22013 if (V.getOperand(0) != V.getOperand(1) ||
22014 !V->isOnlyUserOf(V.getOperand(0).getNode()))
22016 Chain.push_back(V);
22017 V = V.getOperand(0);
22019 switch (V.getOpcode()) {
22021 return SDValue(); // Nothing to combine.
22023 case X86ISD::PSHUFLW:
22024 case X86ISD::PSHUFHW:
22025 if (V.getOpcode() == CombineOp)
22028 Chain.push_back(V);
22032 V = V.getOperand(0);
22036 } while (V.hasOneUse());
22039 // Break out of the loop if we break out of the switch.
22043 if (!V.hasOneUse())
22044 // We fell out of the loop without finding a viable combining instruction.
22047 // Merge this node's mask and our incoming mask.
22048 SmallVector<int, 4> VMask = getPSHUFShuffleMask(V);
22049 for (int &M : Mask)
22051 V = DAG.getNode(V.getOpcode(), DL, V.getValueType(), V.getOperand(0),
22052 getV4X86ShuffleImm8ForMask(Mask, DAG));
22054 // Rebuild the chain around this new shuffle.
22055 while (!Chain.empty()) {
22056 SDValue W = Chain.pop_back_val();
22058 if (V.getValueType() != W.getOperand(0).getValueType())
22059 V = DAG.getNode(ISD::BITCAST, DL, W.getOperand(0).getValueType(), V);
22061 switch (W.getOpcode()) {
22063 llvm_unreachable("Only PSHUF and UNPCK instructions get here!");
22065 case X86ISD::UNPCKL:
22066 case X86ISD::UNPCKH:
22067 V = DAG.getNode(W.getOpcode(), DL, W.getValueType(), V, V);
22070 case X86ISD::PSHUFD:
22071 case X86ISD::PSHUFLW:
22072 case X86ISD::PSHUFHW:
22073 V = DAG.getNode(W.getOpcode(), DL, W.getValueType(), V, W.getOperand(1));
22077 if (V.getValueType() != N.getValueType())
22078 V = DAG.getNode(ISD::BITCAST, DL, N.getValueType(), V);
22080 // Return the new chain to replace N.
22084 /// \brief Search for a combinable shuffle across a chain ending in pshuflw or pshufhw.
22086 /// We walk up the chain, skipping shuffles of the other half and looking
22087 /// through shuffles which switch halves trying to find a shuffle of the same
22088 /// pair of dwords.
22089 static bool combineRedundantHalfShuffle(SDValue N, MutableArrayRef<int> Mask,
22091 TargetLowering::DAGCombinerInfo &DCI) {
22093 (N.getOpcode() == X86ISD::PSHUFLW || N.getOpcode() == X86ISD::PSHUFHW) &&
22094 "Called with something other than an x86 128-bit half shuffle!");
22096 unsigned CombineOpcode = N.getOpcode();
22098 // Walk up a single-use chain looking for a combinable shuffle.
22099 SDValue V = N.getOperand(0);
22100 for (; V.hasOneUse(); V = V.getOperand(0)) {
22101 switch (V.getOpcode()) {
22103 return false; // Nothing combined!
22106 // Skip bitcasts as we always know the type for the target specific
22110 case X86ISD::PSHUFLW:
22111 case X86ISD::PSHUFHW:
22112 if (V.getOpcode() == CombineOpcode)
22115 // Other-half shuffles are no-ops.
22118 // Break out of the loop if we break out of the switch.
22122 if (!V.hasOneUse())
22123 // We fell out of the loop without finding a viable combining instruction.
22126 // Combine away the bottom node as its shuffle will be accumulated into
22127 // a preceding shuffle.
22128 DCI.CombineTo(N.getNode(), N.getOperand(0), /*AddTo*/ true);
22130 // Record the old value.
22133 // Merge this node's mask and our incoming mask (adjusted to account for all
22134 // the pshufd instructions encountered).
22135 SmallVector<int, 4> VMask = getPSHUFShuffleMask(V);
22136 for (int &M : Mask)
22138 V = DAG.getNode(V.getOpcode(), DL, MVT::v8i16, V.getOperand(0),
22139 getV4X86ShuffleImm8ForMask(Mask, DAG));
22141 // Check that the shuffles didn't cancel each other out. If not, we need to
22142 // combine to the new one.
22144 // Replace the combinable shuffle with the combined one, updating all users
22145 // so that we re-evaluate the chain here.
22146 DCI.CombineTo(Old.getNode(), V, /*AddTo*/ true);
22151 /// \brief Try to combine x86 target specific shuffles.
22152 static SDValue PerformTargetShuffleCombine(SDValue N, SelectionDAG &DAG,
22153 TargetLowering::DAGCombinerInfo &DCI,
22154 const X86Subtarget *Subtarget) {
22156 MVT VT = N.getSimpleValueType();
22157 SmallVector<int, 4> Mask;
22159 switch (N.getOpcode()) {
22160 case X86ISD::PSHUFD:
22161 case X86ISD::PSHUFLW:
22162 case X86ISD::PSHUFHW:
22163 Mask = getPSHUFShuffleMask(N);
22164 assert(Mask.size() == 4);
22170 // Nuke no-op shuffles that show up after combining.
22171 if (isNoopShuffleMask(Mask))
22172 return DCI.CombineTo(N.getNode(), N.getOperand(0), /*AddTo*/ true);
22174 // Look for simplifications involving one or two shuffle instructions.
22175 SDValue V = N.getOperand(0);
22176 switch (N.getOpcode()) {
22179 case X86ISD::PSHUFLW:
22180 case X86ISD::PSHUFHW:
22181 assert(VT == MVT::v8i16);
22184 if (combineRedundantHalfShuffle(N, Mask, DAG, DCI))
22185 return SDValue(); // We combined away this shuffle, so we're done.
22187 // See if this reduces to a PSHUFD which is no more expensive and can
22188 // combine with more operations. Note that it has to at least flip the
22189 // dwords as otherwise it would have been removed as a no-op.
22190 if (Mask[0] == 2 && Mask[1] == 3 && Mask[2] == 0 && Mask[3] == 1) {
22191 int DMask[] = {0, 1, 2, 3};
22192 int DOffset = N.getOpcode() == X86ISD::PSHUFLW ? 0 : 2;
22193 DMask[DOffset + 0] = DOffset + 1;
22194 DMask[DOffset + 1] = DOffset + 0;
22195 V = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, V);
22196 DCI.AddToWorklist(V.getNode());
22197 V = DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32, V,
22198 getV4X86ShuffleImm8ForMask(DMask, DAG));
22199 DCI.AddToWorklist(V.getNode());
22200 return DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V);
22203 // Look for shuffle patterns which can be implemented as a single unpack.
22204 // FIXME: This doesn't handle the location of the PSHUFD generically, and
22205 // only works when we have a PSHUFD followed by two half-shuffles.
22206 if (Mask[0] == Mask[1] && Mask[2] == Mask[3] &&
22207 (V.getOpcode() == X86ISD::PSHUFLW ||
22208 V.getOpcode() == X86ISD::PSHUFHW) &&
22209 V.getOpcode() != N.getOpcode() &&
22211 SDValue D = V.getOperand(0);
22212 while (D.getOpcode() == ISD::BITCAST && D.hasOneUse())
22213 D = D.getOperand(0);
22214 if (D.getOpcode() == X86ISD::PSHUFD && D.hasOneUse()) {
22215 SmallVector<int, 4> VMask = getPSHUFShuffleMask(V);
22216 SmallVector<int, 4> DMask = getPSHUFShuffleMask(D);
22217 int NOffset = N.getOpcode() == X86ISD::PSHUFLW ? 0 : 4;
22218 int VOffset = V.getOpcode() == X86ISD::PSHUFLW ? 0 : 4;
22220 for (int i = 0; i < 4; ++i) {
22221 WordMask[i + NOffset] = Mask[i] + NOffset;
22222 WordMask[i + VOffset] = VMask[i] + VOffset;
22224 // Map the word mask through the DWord mask.
22226 for (int i = 0; i < 8; ++i)
22227 MappedMask[i] = 2 * DMask[WordMask[i] / 2] + WordMask[i] % 2;
22228 const int UnpackLoMask[] = {0, 0, 1, 1, 2, 2, 3, 3};
22229 const int UnpackHiMask[] = {4, 4, 5, 5, 6, 6, 7, 7};
22230 if (std::equal(std::begin(MappedMask), std::end(MappedMask),
22231 std::begin(UnpackLoMask)) ||
22232 std::equal(std::begin(MappedMask), std::end(MappedMask),
22233 std::begin(UnpackHiMask))) {
22234 // We can replace all three shuffles with an unpack.
22235 V = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, D.getOperand(0));
22236 DCI.AddToWorklist(V.getNode());
22237 return DAG.getNode(MappedMask[0] == 0 ? X86ISD::UNPCKL
22239 DL, MVT::v8i16, V, V);
22246 case X86ISD::PSHUFD:
22247 if (SDValue NewN = combineRedundantDWordShuffle(N, Mask, DAG, DCI))
22256 /// \brief Try to combine a shuffle into a target-specific add-sub node.
22258 /// We combine this directly on the abstract vector shuffle nodes so it is
22259 /// easier to generically match. We also insert dummy vector shuffle nodes for
22260 /// the operands which explicitly discard the lanes which are unused by this
22261 /// operation to try to flow through the rest of the combiner the fact that
22262 /// they're unused.
22263 static SDValue combineShuffleToAddSub(SDNode *N, SelectionDAG &DAG) {
22265 EVT VT = N->getValueType(0);
22267 // We only handle target-independent shuffles.
22268 // FIXME: It would be easy and harmless to use the target shuffle mask
22269 // extraction tool to support more.
22270 if (N->getOpcode() != ISD::VECTOR_SHUFFLE)
22273 auto *SVN = cast<ShuffleVectorSDNode>(N);
22274 ArrayRef<int> Mask = SVN->getMask();
22275 SDValue V1 = N->getOperand(0);
22276 SDValue V2 = N->getOperand(1);
22278 // We require the first shuffle operand to be the SUB node, and the second to
22279 // be the ADD node.
22280 // FIXME: We should support the commuted patterns.
22281 if (V1->getOpcode() != ISD::FSUB || V2->getOpcode() != ISD::FADD)
22284 // If there are other uses of these operations we can't fold them.
22285 if (!V1->hasOneUse() || !V2->hasOneUse())
22288 // Ensure that both operations have the same operands. Note that we can
22289 // commute the FADD operands.
22290 SDValue LHS = V1->getOperand(0), RHS = V1->getOperand(1);
22291 if ((V2->getOperand(0) != LHS || V2->getOperand(1) != RHS) &&
22292 (V2->getOperand(0) != RHS || V2->getOperand(1) != LHS))
22295 // We're looking for blends between FADD and FSUB nodes. We insist on these
22296 // nodes being lined up in a specific expected pattern.
22297 if (!(isShuffleEquivalent(Mask, 0, 3) ||
22298 isShuffleEquivalent(Mask, 0, 5, 2, 7) ||
22299 isShuffleEquivalent(Mask, 0, 9, 2, 11, 4, 13, 6, 15)))
22302 // Only specific types are legal at this point, assert so we notice if and
22303 // when these change.
22304 assert((VT == MVT::v4f32 || VT == MVT::v2f64 || VT == MVT::v8f32 ||
22305 VT == MVT::v4f64) &&
22306 "Unknown vector type encountered!");
22308 return DAG.getNode(X86ISD::ADDSUB, DL, VT, LHS, RHS);
22311 /// PerformShuffleCombine - Performs several different shuffle combines.
22312 static SDValue PerformShuffleCombine(SDNode *N, SelectionDAG &DAG,
22313 TargetLowering::DAGCombinerInfo &DCI,
22314 const X86Subtarget *Subtarget) {
22316 SDValue N0 = N->getOperand(0);
22317 SDValue N1 = N->getOperand(1);
22318 EVT VT = N->getValueType(0);
22320 // Don't create instructions with illegal types after legalize types has run.
22321 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
22322 if (!DCI.isBeforeLegalize() && !TLI.isTypeLegal(VT.getVectorElementType()))
22325 // If we have legalized the vector types, look for blends of FADD and FSUB
22326 // nodes that we can fuse into an ADDSUB node.
22327 if (TLI.isTypeLegal(VT) && Subtarget->hasSSE3())
22328 if (SDValue AddSub = combineShuffleToAddSub(N, DAG))
22331 // Combine 256-bit vector shuffles. This is only profitable when in AVX mode
22332 if (Subtarget->hasFp256() && VT.is256BitVector() &&
22333 N->getOpcode() == ISD::VECTOR_SHUFFLE)
22334 return PerformShuffleCombine256(N, DAG, DCI, Subtarget);
22336 // During Type Legalization, when promoting illegal vector types,
22337 // the backend might introduce new shuffle dag nodes and bitcasts.
22339 // This code performs the following transformation:
22340 // fold: (shuffle (bitcast (BINOP A, B)), Undef, <Mask>) ->
22341 // (shuffle (BINOP (bitcast A), (bitcast B)), Undef, <Mask>)
22343 // We do this only if both the bitcast and the BINOP dag nodes have
22344 // one use. Also, perform this transformation only if the new binary
22345 // operation is legal. This is to avoid introducing dag nodes that
22346 // potentially need to be further expanded (or custom lowered) into a
22347 // less optimal sequence of dag nodes.
22348 if (!DCI.isBeforeLegalize() && DCI.isBeforeLegalizeOps() &&
22349 N1.getOpcode() == ISD::UNDEF && N0.hasOneUse() &&
22350 N0.getOpcode() == ISD::BITCAST) {
22351 SDValue BC0 = N0.getOperand(0);
22352 EVT SVT = BC0.getValueType();
22353 unsigned Opcode = BC0.getOpcode();
22354 unsigned NumElts = VT.getVectorNumElements();
22356 if (BC0.hasOneUse() && SVT.isVector() &&
22357 SVT.getVectorNumElements() * 2 == NumElts &&
22358 TLI.isOperationLegal(Opcode, VT)) {
22359 bool CanFold = false;
22371 unsigned SVTNumElts = SVT.getVectorNumElements();
22372 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
22373 for (unsigned i = 0, e = SVTNumElts; i != e && CanFold; ++i)
22374 CanFold = SVOp->getMaskElt(i) == (int)(i * 2);
22375 for (unsigned i = SVTNumElts, e = NumElts; i != e && CanFold; ++i)
22376 CanFold = SVOp->getMaskElt(i) < 0;
22379 SDValue BC00 = DAG.getNode(ISD::BITCAST, dl, VT, BC0.getOperand(0));
22380 SDValue BC01 = DAG.getNode(ISD::BITCAST, dl, VT, BC0.getOperand(1));
22381 SDValue NewBinOp = DAG.getNode(BC0.getOpcode(), dl, VT, BC00, BC01);
22382 return DAG.getVectorShuffle(VT, dl, NewBinOp, N1, &SVOp->getMask()[0]);
22387 // Only handle 128 wide vector from here on.
22388 if (!VT.is128BitVector())
22391 // Combine a vector_shuffle that is equal to build_vector load1, load2, load3,
22392 // load4, <0, 1, 2, 3> into a 128-bit load if the load addresses are
22393 // consecutive, non-overlapping, and in the right order.
22394 SmallVector<SDValue, 16> Elts;
22395 for (unsigned i = 0, e = VT.getVectorNumElements(); i != e; ++i)
22396 Elts.push_back(getShuffleScalarElt(N, i, DAG, 0));
22398 SDValue LD = EltsFromConsecutiveLoads(VT, Elts, dl, DAG, true);
22402 if (isTargetShuffle(N->getOpcode())) {
22404 PerformTargetShuffleCombine(SDValue(N, 0), DAG, DCI, Subtarget);
22405 if (Shuffle.getNode())
22408 // Try recursively combining arbitrary sequences of x86 shuffle
22409 // instructions into higher-order shuffles. We do this after combining
22410 // specific PSHUF instruction sequences into their minimal form so that we
22411 // can evaluate how many specialized shuffle instructions are involved in
22412 // a particular chain.
22413 SmallVector<int, 1> NonceMask; // Just a placeholder.
22414 NonceMask.push_back(0);
22415 if (combineX86ShufflesRecursively(SDValue(N, 0), SDValue(N, 0), NonceMask,
22416 /*Depth*/ 1, /*HasPSHUFB*/ false, DAG,
22418 return SDValue(); // This routine will use CombineTo to replace N.
22424 /// PerformTruncateCombine - Converts truncate operation to
22425 /// a sequence of vector shuffle operations.
22426 /// It is possible when we truncate 256-bit vector to 128-bit vector
22427 static SDValue PerformTruncateCombine(SDNode *N, SelectionDAG &DAG,
22428 TargetLowering::DAGCombinerInfo &DCI,
22429 const X86Subtarget *Subtarget) {
22433 /// XFormVExtractWithShuffleIntoLoad - Check if a vector extract from a target
22434 /// specific shuffle of a load can be folded into a single element load.
22435 /// Similar handling for VECTOR_SHUFFLE is performed by DAGCombiner, but
22436 /// shuffles have been custom lowered so we need to handle those here.
22437 static SDValue XFormVExtractWithShuffleIntoLoad(SDNode *N, SelectionDAG &DAG,
22438 TargetLowering::DAGCombinerInfo &DCI) {
22439 if (DCI.isBeforeLegalizeOps())
22442 SDValue InVec = N->getOperand(0);
22443 SDValue EltNo = N->getOperand(1);
22445 if (!isa<ConstantSDNode>(EltNo))
22448 EVT OriginalVT = InVec.getValueType();
22450 if (InVec.getOpcode() == ISD::BITCAST) {
22451 // Don't duplicate a load with other uses.
22452 if (!InVec.hasOneUse())
22454 EVT BCVT = InVec.getOperand(0).getValueType();
22455 if (BCVT.getVectorNumElements() != OriginalVT.getVectorNumElements())
22457 InVec = InVec.getOperand(0);
22460 EVT CurrentVT = InVec.getValueType();
22462 if (!isTargetShuffle(InVec.getOpcode()))
22465 // Don't duplicate a load with other uses.
22466 if (!InVec.hasOneUse())
22469 SmallVector<int, 16> ShuffleMask;
22471 if (!getTargetShuffleMask(InVec.getNode(), CurrentVT.getSimpleVT(),
22472 ShuffleMask, UnaryShuffle))
22475 // Select the input vector, guarding against out of range extract vector.
22476 unsigned NumElems = CurrentVT.getVectorNumElements();
22477 int Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();
22478 int Idx = (Elt > (int)NumElems) ? -1 : ShuffleMask[Elt];
22479 SDValue LdNode = (Idx < (int)NumElems) ? InVec.getOperand(0)
22480 : InVec.getOperand(1);
22482 // If inputs to shuffle are the same for both ops, then allow 2 uses
22483 unsigned AllowedUses = InVec.getOperand(0) == InVec.getOperand(1) ? 2 : 1;
22485 if (LdNode.getOpcode() == ISD::BITCAST) {
22486 // Don't duplicate a load with other uses.
22487 if (!LdNode.getNode()->hasNUsesOfValue(AllowedUses, 0))
22490 AllowedUses = 1; // only allow 1 load use if we have a bitcast
22491 LdNode = LdNode.getOperand(0);
22494 if (!ISD::isNormalLoad(LdNode.getNode()))
22497 LoadSDNode *LN0 = cast<LoadSDNode>(LdNode);
22499 if (!LN0 ||!LN0->hasNUsesOfValue(AllowedUses, 0) || LN0->isVolatile())
22502 EVT EltVT = N->getValueType(0);
22503 // If there's a bitcast before the shuffle, check if the load type and
22504 // alignment is valid.
22505 unsigned Align = LN0->getAlignment();
22506 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
22507 unsigned NewAlign = TLI.getDataLayout()->getABITypeAlignment(
22508 EltVT.getTypeForEVT(*DAG.getContext()));
22510 if (NewAlign > Align || !TLI.isOperationLegalOrCustom(ISD::LOAD, EltVT))
22513 // All checks match so transform back to vector_shuffle so that DAG combiner
22514 // can finish the job
22517 // Create shuffle node taking into account the case that its a unary shuffle
22518 SDValue Shuffle = (UnaryShuffle) ? DAG.getUNDEF(CurrentVT)
22519 : InVec.getOperand(1);
22520 Shuffle = DAG.getVectorShuffle(CurrentVT, dl,
22521 InVec.getOperand(0), Shuffle,
22523 Shuffle = DAG.getNode(ISD::BITCAST, dl, OriginalVT, Shuffle);
22524 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, N->getValueType(0), Shuffle,
22528 /// PerformEXTRACT_VECTOR_ELTCombine - Detect vector gather/scatter index
22529 /// generation and convert it from being a bunch of shuffles and extracts
22530 /// to a simple store and scalar loads to extract the elements.
22531 static SDValue PerformEXTRACT_VECTOR_ELTCombine(SDNode *N, SelectionDAG &DAG,
22532 TargetLowering::DAGCombinerInfo &DCI) {
22533 SDValue NewOp = XFormVExtractWithShuffleIntoLoad(N, DAG, DCI);
22534 if (NewOp.getNode())
22537 SDValue InputVector = N->getOperand(0);
22539 // Detect whether we are trying to convert from mmx to i32 and the bitcast
22540 // from mmx to v2i32 has a single usage.
22541 if (InputVector.getNode()->getOpcode() == llvm::ISD::BITCAST &&
22542 InputVector.getNode()->getOperand(0).getValueType() == MVT::x86mmx &&
22543 InputVector.hasOneUse() && N->getValueType(0) == MVT::i32)
22544 return DAG.getNode(X86ISD::MMX_MOVD2W, SDLoc(InputVector),
22545 N->getValueType(0),
22546 InputVector.getNode()->getOperand(0));
22548 // Only operate on vectors of 4 elements, where the alternative shuffling
22549 // gets to be more expensive.
22550 if (InputVector.getValueType() != MVT::v4i32)
22553 // Check whether every use of InputVector is an EXTRACT_VECTOR_ELT with a
22554 // single use which is a sign-extend or zero-extend, and all elements are
22556 SmallVector<SDNode *, 4> Uses;
22557 unsigned ExtractedElements = 0;
22558 for (SDNode::use_iterator UI = InputVector.getNode()->use_begin(),
22559 UE = InputVector.getNode()->use_end(); UI != UE; ++UI) {
22560 if (UI.getUse().getResNo() != InputVector.getResNo())
22563 SDNode *Extract = *UI;
22564 if (Extract->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
22567 if (Extract->getValueType(0) != MVT::i32)
22569 if (!Extract->hasOneUse())
22571 if (Extract->use_begin()->getOpcode() != ISD::SIGN_EXTEND &&
22572 Extract->use_begin()->getOpcode() != ISD::ZERO_EXTEND)
22574 if (!isa<ConstantSDNode>(Extract->getOperand(1)))
22577 // Record which element was extracted.
22578 ExtractedElements |=
22579 1 << cast<ConstantSDNode>(Extract->getOperand(1))->getZExtValue();
22581 Uses.push_back(Extract);
22584 // If not all the elements were used, this may not be worthwhile.
22585 if (ExtractedElements != 15)
22588 // Ok, we've now decided to do the transformation.
22589 SDLoc dl(InputVector);
22591 // Store the value to a temporary stack slot.
22592 SDValue StackPtr = DAG.CreateStackTemporary(InputVector.getValueType());
22593 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, InputVector, StackPtr,
22594 MachinePointerInfo(), false, false, 0);
22596 // Replace each use (extract) with a load of the appropriate element.
22597 for (SmallVectorImpl<SDNode *>::iterator UI = Uses.begin(),
22598 UE = Uses.end(); UI != UE; ++UI) {
22599 SDNode *Extract = *UI;
22601 // cOMpute the element's address.
22602 SDValue Idx = Extract->getOperand(1);
22604 InputVector.getValueType().getVectorElementType().getSizeInBits()/8;
22605 uint64_t Offset = EltSize * cast<ConstantSDNode>(Idx)->getZExtValue();
22606 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
22607 SDValue OffsetVal = DAG.getConstant(Offset, TLI.getPointerTy());
22609 SDValue ScalarAddr = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(),
22610 StackPtr, OffsetVal);
22612 // Load the scalar.
22613 SDValue LoadScalar = DAG.getLoad(Extract->getValueType(0), dl, Ch,
22614 ScalarAddr, MachinePointerInfo(),
22615 false, false, false, 0);
22617 // Replace the exact with the load.
22618 DAG.ReplaceAllUsesOfValueWith(SDValue(Extract, 0), LoadScalar);
22621 // The replacement was made in place; don't return anything.
22625 /// \brief Matches a VSELECT onto min/max or return 0 if the node doesn't match.
22626 static std::pair<unsigned, bool>
22627 matchIntegerMINMAX(SDValue Cond, EVT VT, SDValue LHS, SDValue RHS,
22628 SelectionDAG &DAG, const X86Subtarget *Subtarget) {
22629 if (!VT.isVector())
22630 return std::make_pair(0, false);
22632 bool NeedSplit = false;
22633 switch (VT.getSimpleVT().SimpleTy) {
22634 default: return std::make_pair(0, false);
22638 if (!Subtarget->hasAVX2())
22640 if (!Subtarget->hasAVX())
22641 return std::make_pair(0, false);
22646 if (!Subtarget->hasSSE2())
22647 return std::make_pair(0, false);
22650 // SSE2 has only a small subset of the operations.
22651 bool hasUnsigned = Subtarget->hasSSE41() ||
22652 (Subtarget->hasSSE2() && VT == MVT::v16i8);
22653 bool hasSigned = Subtarget->hasSSE41() ||
22654 (Subtarget->hasSSE2() && VT == MVT::v8i16);
22656 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
22659 // Check for x CC y ? x : y.
22660 if (DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
22661 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
22666 Opc = hasUnsigned ? X86ISD::UMIN : 0; break;
22669 Opc = hasUnsigned ? X86ISD::UMAX : 0; break;
22672 Opc = hasSigned ? X86ISD::SMIN : 0; break;
22675 Opc = hasSigned ? X86ISD::SMAX : 0; break;
22677 // Check for x CC y ? y : x -- a min/max with reversed arms.
22678 } else if (DAG.isEqualTo(LHS, Cond.getOperand(1)) &&
22679 DAG.isEqualTo(RHS, Cond.getOperand(0))) {
22684 Opc = hasUnsigned ? X86ISD::UMAX : 0; break;
22687 Opc = hasUnsigned ? X86ISD::UMIN : 0; break;
22690 Opc = hasSigned ? X86ISD::SMAX : 0; break;
22693 Opc = hasSigned ? X86ISD::SMIN : 0; break;
22697 return std::make_pair(Opc, NeedSplit);
22701 transformVSELECTtoBlendVECTOR_SHUFFLE(SDNode *N, SelectionDAG &DAG,
22702 const X86Subtarget *Subtarget) {
22704 SDValue Cond = N->getOperand(0);
22705 SDValue LHS = N->getOperand(1);
22706 SDValue RHS = N->getOperand(2);
22708 if (Cond.getOpcode() == ISD::SIGN_EXTEND) {
22709 SDValue CondSrc = Cond->getOperand(0);
22710 if (CondSrc->getOpcode() == ISD::SIGN_EXTEND_INREG)
22711 Cond = CondSrc->getOperand(0);
22714 if (!ISD::isBuildVectorOfConstantSDNodes(Cond.getNode()))
22717 // A vselect where all conditions and data are constants can be optimized into
22718 // a single vector load by SelectionDAGLegalize::ExpandBUILD_VECTOR().
22719 if (ISD::isBuildVectorOfConstantSDNodes(LHS.getNode()) &&
22720 ISD::isBuildVectorOfConstantSDNodes(RHS.getNode()))
22723 unsigned MaskValue = 0;
22724 if (!BUILD_VECTORtoBlendMask(cast<BuildVectorSDNode>(Cond), MaskValue))
22727 MVT VT = N->getSimpleValueType(0);
22728 unsigned NumElems = VT.getVectorNumElements();
22729 SmallVector<int, 8> ShuffleMask(NumElems, -1);
22730 for (unsigned i = 0; i < NumElems; ++i) {
22731 // Be sure we emit undef where we can.
22732 if (Cond.getOperand(i)->getOpcode() == ISD::UNDEF)
22733 ShuffleMask[i] = -1;
22735 ShuffleMask[i] = i + NumElems * ((MaskValue >> i) & 1);
22738 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
22739 if (!TLI.isShuffleMaskLegal(ShuffleMask, VT))
22741 return DAG.getVectorShuffle(VT, dl, LHS, RHS, &ShuffleMask[0]);
22744 /// PerformSELECTCombine - Do target-specific dag combines on SELECT and VSELECT
22746 static SDValue PerformSELECTCombine(SDNode *N, SelectionDAG &DAG,
22747 TargetLowering::DAGCombinerInfo &DCI,
22748 const X86Subtarget *Subtarget) {
22750 SDValue Cond = N->getOperand(0);
22751 // Get the LHS/RHS of the select.
22752 SDValue LHS = N->getOperand(1);
22753 SDValue RHS = N->getOperand(2);
22754 EVT VT = LHS.getValueType();
22755 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
22757 // If we have SSE[12] support, try to form min/max nodes. SSE min/max
22758 // instructions match the semantics of the common C idiom x<y?x:y but not
22759 // x<=y?x:y, because of how they handle negative zero (which can be
22760 // ignored in unsafe-math mode).
22761 if (Cond.getOpcode() == ISD::SETCC && VT.isFloatingPoint() &&
22762 VT != MVT::f80 && TLI.isTypeLegal(VT) &&
22763 (Subtarget->hasSSE2() ||
22764 (Subtarget->hasSSE1() && VT.getScalarType() == MVT::f32))) {
22765 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
22767 unsigned Opcode = 0;
22768 // Check for x CC y ? x : y.
22769 if (DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
22770 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
22774 // Converting this to a min would handle NaNs incorrectly, and swapping
22775 // the operands would cause it to handle comparisons between positive
22776 // and negative zero incorrectly.
22777 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
22778 if (!DAG.getTarget().Options.UnsafeFPMath &&
22779 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
22781 std::swap(LHS, RHS);
22783 Opcode = X86ISD::FMIN;
22786 // Converting this to a min would handle comparisons between positive
22787 // and negative zero incorrectly.
22788 if (!DAG.getTarget().Options.UnsafeFPMath &&
22789 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
22791 Opcode = X86ISD::FMIN;
22794 // Converting this to a min would handle both negative zeros and NaNs
22795 // incorrectly, but we can swap the operands to fix both.
22796 std::swap(LHS, RHS);
22800 Opcode = X86ISD::FMIN;
22804 // Converting this to a max would handle comparisons between positive
22805 // and negative zero incorrectly.
22806 if (!DAG.getTarget().Options.UnsafeFPMath &&
22807 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
22809 Opcode = X86ISD::FMAX;
22812 // Converting this to a max would handle NaNs incorrectly, and swapping
22813 // the operands would cause it to handle comparisons between positive
22814 // and negative zero incorrectly.
22815 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
22816 if (!DAG.getTarget().Options.UnsafeFPMath &&
22817 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
22819 std::swap(LHS, RHS);
22821 Opcode = X86ISD::FMAX;
22824 // Converting this to a max would handle both negative zeros and NaNs
22825 // incorrectly, but we can swap the operands to fix both.
22826 std::swap(LHS, RHS);
22830 Opcode = X86ISD::FMAX;
22833 // Check for x CC y ? y : x -- a min/max with reversed arms.
22834 } else if (DAG.isEqualTo(LHS, Cond.getOperand(1)) &&
22835 DAG.isEqualTo(RHS, Cond.getOperand(0))) {
22839 // Converting this to a min would handle comparisons between positive
22840 // and negative zero incorrectly, and swapping the operands would
22841 // cause it to handle NaNs incorrectly.
22842 if (!DAG.getTarget().Options.UnsafeFPMath &&
22843 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS))) {
22844 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
22846 std::swap(LHS, RHS);
22848 Opcode = X86ISD::FMIN;
22851 // Converting this to a min would handle NaNs incorrectly.
22852 if (!DAG.getTarget().Options.UnsafeFPMath &&
22853 (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)))
22855 Opcode = X86ISD::FMIN;
22858 // Converting this to a min would handle both negative zeros and NaNs
22859 // incorrectly, but we can swap the operands to fix both.
22860 std::swap(LHS, RHS);
22864 Opcode = X86ISD::FMIN;
22868 // Converting this to a max would handle NaNs incorrectly.
22869 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
22871 Opcode = X86ISD::FMAX;
22874 // Converting this to a max would handle comparisons between positive
22875 // and negative zero incorrectly, and swapping the operands would
22876 // cause it to handle NaNs incorrectly.
22877 if (!DAG.getTarget().Options.UnsafeFPMath &&
22878 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS)) {
22879 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
22881 std::swap(LHS, RHS);
22883 Opcode = X86ISD::FMAX;
22886 // Converting this to a max would handle both negative zeros and NaNs
22887 // incorrectly, but we can swap the operands to fix both.
22888 std::swap(LHS, RHS);
22892 Opcode = X86ISD::FMAX;
22898 return DAG.getNode(Opcode, DL, N->getValueType(0), LHS, RHS);
22901 EVT CondVT = Cond.getValueType();
22902 if (Subtarget->hasAVX512() && VT.isVector() && CondVT.isVector() &&
22903 CondVT.getVectorElementType() == MVT::i1) {
22904 // v16i8 (select v16i1, v16i8, v16i8) does not have a proper
22905 // lowering on KNL. In this case we convert it to
22906 // v16i8 (select v16i8, v16i8, v16i8) and use AVX instruction.
22907 // The same situation for all 128 and 256-bit vectors of i8 and i16.
22908 // Since SKX these selects have a proper lowering.
22909 EVT OpVT = LHS.getValueType();
22910 if ((OpVT.is128BitVector() || OpVT.is256BitVector()) &&
22911 (OpVT.getVectorElementType() == MVT::i8 ||
22912 OpVT.getVectorElementType() == MVT::i16) &&
22913 !(Subtarget->hasBWI() && Subtarget->hasVLX())) {
22914 Cond = DAG.getNode(ISD::SIGN_EXTEND, DL, OpVT, Cond);
22915 DCI.AddToWorklist(Cond.getNode());
22916 return DAG.getNode(N->getOpcode(), DL, OpVT, Cond, LHS, RHS);
22919 // If this is a select between two integer constants, try to do some
22921 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(LHS)) {
22922 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(RHS))
22923 // Don't do this for crazy integer types.
22924 if (DAG.getTargetLoweringInfo().isTypeLegal(LHS.getValueType())) {
22925 // If this is efficiently invertible, canonicalize the LHSC/RHSC values
22926 // so that TrueC (the true value) is larger than FalseC.
22927 bool NeedsCondInvert = false;
22929 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue()) &&
22930 // Efficiently invertible.
22931 (Cond.getOpcode() == ISD::SETCC || // setcc -> invertible.
22932 (Cond.getOpcode() == ISD::XOR && // xor(X, C) -> invertible.
22933 isa<ConstantSDNode>(Cond.getOperand(1))))) {
22934 NeedsCondInvert = true;
22935 std::swap(TrueC, FalseC);
22938 // Optimize C ? 8 : 0 -> zext(C) << 3. Likewise for any pow2/0.
22939 if (FalseC->getAPIntValue() == 0 &&
22940 TrueC->getAPIntValue().isPowerOf2()) {
22941 if (NeedsCondInvert) // Invert the condition if needed.
22942 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
22943 DAG.getConstant(1, Cond.getValueType()));
22945 // Zero extend the condition if needed.
22946 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, LHS.getValueType(), Cond);
22948 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
22949 return DAG.getNode(ISD::SHL, DL, LHS.getValueType(), Cond,
22950 DAG.getConstant(ShAmt, MVT::i8));
22953 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst.
22954 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
22955 if (NeedsCondInvert) // Invert the condition if needed.
22956 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
22957 DAG.getConstant(1, Cond.getValueType()));
22959 // Zero extend the condition if needed.
22960 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
22961 FalseC->getValueType(0), Cond);
22962 return DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
22963 SDValue(FalseC, 0));
22966 // Optimize cases that will turn into an LEA instruction. This requires
22967 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
22968 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
22969 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
22970 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
22972 bool isFastMultiplier = false;
22974 switch ((unsigned char)Diff) {
22976 case 1: // result = add base, cond
22977 case 2: // result = lea base( , cond*2)
22978 case 3: // result = lea base(cond, cond*2)
22979 case 4: // result = lea base( , cond*4)
22980 case 5: // result = lea base(cond, cond*4)
22981 case 8: // result = lea base( , cond*8)
22982 case 9: // result = lea base(cond, cond*8)
22983 isFastMultiplier = true;
22988 if (isFastMultiplier) {
22989 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
22990 if (NeedsCondInvert) // Invert the condition if needed.
22991 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
22992 DAG.getConstant(1, Cond.getValueType()));
22994 // Zero extend the condition if needed.
22995 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
22997 // Scale the condition by the difference.
22999 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
23000 DAG.getConstant(Diff, Cond.getValueType()));
23002 // Add the base if non-zero.
23003 if (FalseC->getAPIntValue() != 0)
23004 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
23005 SDValue(FalseC, 0));
23012 // Canonicalize max and min:
23013 // (x > y) ? x : y -> (x >= y) ? x : y
23014 // (x < y) ? x : y -> (x <= y) ? x : y
23015 // This allows use of COND_S / COND_NS (see TranslateX86CC) which eliminates
23016 // the need for an extra compare
23017 // against zero. e.g.
23018 // (x - y) > 0 : (x - y) ? 0 -> (x - y) >= 0 : (x - y) ? 0
23020 // testl %edi, %edi
23022 // cmovgl %edi, %eax
23026 // cmovsl %eax, %edi
23027 if (N->getOpcode() == ISD::SELECT && Cond.getOpcode() == ISD::SETCC &&
23028 DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
23029 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
23030 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
23035 ISD::CondCode NewCC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGE;
23036 Cond = DAG.getSetCC(SDLoc(Cond), Cond.getValueType(),
23037 Cond.getOperand(0), Cond.getOperand(1), NewCC);
23038 return DAG.getNode(ISD::SELECT, DL, VT, Cond, LHS, RHS);
23043 // Early exit check
23044 if (!TLI.isTypeLegal(VT))
23047 // Match VSELECTs into subs with unsigned saturation.
23048 if (N->getOpcode() == ISD::VSELECT && Cond.getOpcode() == ISD::SETCC &&
23049 // psubus is available in SSE2 and AVX2 for i8 and i16 vectors.
23050 ((Subtarget->hasSSE2() && (VT == MVT::v16i8 || VT == MVT::v8i16)) ||
23051 (Subtarget->hasAVX2() && (VT == MVT::v32i8 || VT == MVT::v16i16)))) {
23052 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
23054 // Check if one of the arms of the VSELECT is a zero vector. If it's on the
23055 // left side invert the predicate to simplify logic below.
23057 if (ISD::isBuildVectorAllZeros(LHS.getNode())) {
23059 CC = ISD::getSetCCInverse(CC, true);
23060 } else if (ISD::isBuildVectorAllZeros(RHS.getNode())) {
23064 if (Other.getNode() && Other->getNumOperands() == 2 &&
23065 DAG.isEqualTo(Other->getOperand(0), Cond.getOperand(0))) {
23066 SDValue OpLHS = Other->getOperand(0), OpRHS = Other->getOperand(1);
23067 SDValue CondRHS = Cond->getOperand(1);
23069 // Look for a general sub with unsigned saturation first.
23070 // x >= y ? x-y : 0 --> subus x, y
23071 // x > y ? x-y : 0 --> subus x, y
23072 if ((CC == ISD::SETUGE || CC == ISD::SETUGT) &&
23073 Other->getOpcode() == ISD::SUB && DAG.isEqualTo(OpRHS, CondRHS))
23074 return DAG.getNode(X86ISD::SUBUS, DL, VT, OpLHS, OpRHS);
23076 if (auto *OpRHSBV = dyn_cast<BuildVectorSDNode>(OpRHS))
23077 if (auto *OpRHSConst = OpRHSBV->getConstantSplatNode()) {
23078 if (auto *CondRHSBV = dyn_cast<BuildVectorSDNode>(CondRHS))
23079 if (auto *CondRHSConst = CondRHSBV->getConstantSplatNode())
23080 // If the RHS is a constant we have to reverse the const
23081 // canonicalization.
23082 // x > C-1 ? x+-C : 0 --> subus x, C
23083 if (CC == ISD::SETUGT && Other->getOpcode() == ISD::ADD &&
23084 CondRHSConst->getAPIntValue() ==
23085 (-OpRHSConst->getAPIntValue() - 1))
23086 return DAG.getNode(
23087 X86ISD::SUBUS, DL, VT, OpLHS,
23088 DAG.getConstant(-OpRHSConst->getAPIntValue(), VT));
23090 // Another special case: If C was a sign bit, the sub has been
23091 // canonicalized into a xor.
23092 // FIXME: Would it be better to use computeKnownBits to determine
23093 // whether it's safe to decanonicalize the xor?
23094 // x s< 0 ? x^C : 0 --> subus x, C
23095 if (CC == ISD::SETLT && Other->getOpcode() == ISD::XOR &&
23096 ISD::isBuildVectorAllZeros(CondRHS.getNode()) &&
23097 OpRHSConst->getAPIntValue().isSignBit())
23098 // Note that we have to rebuild the RHS constant here to ensure we
23099 // don't rely on particular values of undef lanes.
23100 return DAG.getNode(
23101 X86ISD::SUBUS, DL, VT, OpLHS,
23102 DAG.getConstant(OpRHSConst->getAPIntValue(), VT));
23107 // Try to match a min/max vector operation.
23108 if (N->getOpcode() == ISD::VSELECT && Cond.getOpcode() == ISD::SETCC) {
23109 std::pair<unsigned, bool> ret = matchIntegerMINMAX(Cond, VT, LHS, RHS, DAG, Subtarget);
23110 unsigned Opc = ret.first;
23111 bool NeedSplit = ret.second;
23113 if (Opc && NeedSplit) {
23114 unsigned NumElems = VT.getVectorNumElements();
23115 // Extract the LHS vectors
23116 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, DL);
23117 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, DL);
23119 // Extract the RHS vectors
23120 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, DL);
23121 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, DL);
23123 // Create min/max for each subvector
23124 LHS = DAG.getNode(Opc, DL, LHS1.getValueType(), LHS1, RHS1);
23125 RHS = DAG.getNode(Opc, DL, LHS2.getValueType(), LHS2, RHS2);
23127 // Merge the result
23128 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, LHS, RHS);
23130 return DAG.getNode(Opc, DL, VT, LHS, RHS);
23133 // Simplify vector selection if condition value type matches vselect
23135 if (N->getOpcode() == ISD::VSELECT && CondVT == VT) {
23136 assert(Cond.getValueType().isVector() &&
23137 "vector select expects a vector selector!");
23139 bool TValIsAllOnes = ISD::isBuildVectorAllOnes(LHS.getNode());
23140 bool FValIsAllZeros = ISD::isBuildVectorAllZeros(RHS.getNode());
23142 // Try invert the condition if true value is not all 1s and false value
23144 if (!TValIsAllOnes && !FValIsAllZeros &&
23145 // Check if the selector will be produced by CMPP*/PCMP*
23146 Cond.getOpcode() == ISD::SETCC &&
23147 // Check if SETCC has already been promoted
23148 TLI.getSetCCResultType(*DAG.getContext(), VT) == CondVT) {
23149 bool TValIsAllZeros = ISD::isBuildVectorAllZeros(LHS.getNode());
23150 bool FValIsAllOnes = ISD::isBuildVectorAllOnes(RHS.getNode());
23152 if (TValIsAllZeros || FValIsAllOnes) {
23153 SDValue CC = Cond.getOperand(2);
23154 ISD::CondCode NewCC =
23155 ISD::getSetCCInverse(cast<CondCodeSDNode>(CC)->get(),
23156 Cond.getOperand(0).getValueType().isInteger());
23157 Cond = DAG.getSetCC(DL, CondVT, Cond.getOperand(0), Cond.getOperand(1), NewCC);
23158 std::swap(LHS, RHS);
23159 TValIsAllOnes = FValIsAllOnes;
23160 FValIsAllZeros = TValIsAllZeros;
23164 if (TValIsAllOnes || FValIsAllZeros) {
23167 if (TValIsAllOnes && FValIsAllZeros)
23169 else if (TValIsAllOnes)
23170 Ret = DAG.getNode(ISD::OR, DL, CondVT, Cond,
23171 DAG.getNode(ISD::BITCAST, DL, CondVT, RHS));
23172 else if (FValIsAllZeros)
23173 Ret = DAG.getNode(ISD::AND, DL, CondVT, Cond,
23174 DAG.getNode(ISD::BITCAST, DL, CondVT, LHS));
23176 return DAG.getNode(ISD::BITCAST, DL, VT, Ret);
23180 // If we know that this node is legal then we know that it is going to be
23181 // matched by one of the SSE/AVX BLEND instructions. These instructions only
23182 // depend on the highest bit in each word. Try to use SimplifyDemandedBits
23183 // to simplify previous instructions.
23184 if (N->getOpcode() == ISD::VSELECT && DCI.isBeforeLegalizeOps() &&
23185 !DCI.isBeforeLegalize() &&
23186 // We explicitly check against v8i16 and v16i16 because, although
23187 // they're marked as Custom, they might only be legal when Cond is a
23188 // build_vector of constants. This will be taken care in a later
23190 (TLI.isOperationLegalOrCustom(ISD::VSELECT, VT) && VT != MVT::v16i16 &&
23191 VT != MVT::v8i16) &&
23192 // Don't optimize vector of constants. Those are handled by
23193 // the generic code and all the bits must be properly set for
23194 // the generic optimizer.
23195 !ISD::isBuildVectorOfConstantSDNodes(Cond.getNode())) {
23196 unsigned BitWidth = Cond.getValueType().getScalarType().getSizeInBits();
23198 // Don't optimize vector selects that map to mask-registers.
23202 assert(BitWidth >= 8 && BitWidth <= 64 && "Invalid mask size");
23203 APInt DemandedMask = APInt::getHighBitsSet(BitWidth, 1);
23205 APInt KnownZero, KnownOne;
23206 TargetLowering::TargetLoweringOpt TLO(DAG, DCI.isBeforeLegalize(),
23207 DCI.isBeforeLegalizeOps());
23208 if (TLO.ShrinkDemandedConstant(Cond, DemandedMask) ||
23209 TLI.SimplifyDemandedBits(Cond, DemandedMask, KnownZero, KnownOne,
23211 // If we changed the computation somewhere in the DAG, this change
23212 // will affect all users of Cond.
23213 // Make sure it is fine and update all the nodes so that we do not
23214 // use the generic VSELECT anymore. Otherwise, we may perform
23215 // wrong optimizations as we messed up with the actual expectation
23216 // for the vector boolean values.
23217 if (Cond != TLO.Old) {
23218 // Check all uses of that condition operand to check whether it will be
23219 // consumed by non-BLEND instructions, which may depend on all bits are
23221 for (SDNode::use_iterator I = Cond->use_begin(), E = Cond->use_end();
23223 if (I->getOpcode() != ISD::VSELECT)
23224 // TODO: Add other opcodes eventually lowered into BLEND.
23227 // Update all the users of the condition, before committing the change,
23228 // so that the VSELECT optimizations that expect the correct vector
23229 // boolean value will not be triggered.
23230 for (SDNode::use_iterator I = Cond->use_begin(), E = Cond->use_end();
23232 DAG.ReplaceAllUsesOfValueWith(
23234 DAG.getNode(X86ISD::SHRUNKBLEND, SDLoc(*I), I->getValueType(0),
23235 Cond, I->getOperand(1), I->getOperand(2)));
23236 DCI.CommitTargetLoweringOpt(TLO);
23239 // At this point, only Cond is changed. Change the condition
23240 // just for N to keep the opportunity to optimize all other
23241 // users their own way.
23242 DAG.ReplaceAllUsesOfValueWith(
23244 DAG.getNode(X86ISD::SHRUNKBLEND, SDLoc(N), N->getValueType(0),
23245 TLO.New, N->getOperand(1), N->getOperand(2)));
23250 // We should generate an X86ISD::BLENDI from a vselect if its argument
23251 // is a sign_extend_inreg of an any_extend of a BUILD_VECTOR of
23252 // constants. This specific pattern gets generated when we split a
23253 // selector for a 512 bit vector in a machine without AVX512 (but with
23254 // 256-bit vectors), during legalization:
23256 // (vselect (sign_extend (any_extend (BUILD_VECTOR)) i1) LHS RHS)
23258 // Iff we find this pattern and the build_vectors are built from
23259 // constants, we translate the vselect into a shuffle_vector that we
23260 // know will be matched by LowerVECTOR_SHUFFLEtoBlend.
23261 if ((N->getOpcode() == ISD::VSELECT ||
23262 N->getOpcode() == X86ISD::SHRUNKBLEND) &&
23263 !DCI.isBeforeLegalize()) {
23264 SDValue Shuffle = transformVSELECTtoBlendVECTOR_SHUFFLE(N, DAG, Subtarget);
23265 if (Shuffle.getNode())
23272 // Check whether a boolean test is testing a boolean value generated by
23273 // X86ISD::SETCC. If so, return the operand of that SETCC and proper condition
23276 // Simplify the following patterns:
23277 // (Op (CMP (SETCC Cond EFLAGS) 1) EQ) or
23278 // (Op (CMP (SETCC Cond EFLAGS) 0) NEQ)
23279 // to (Op EFLAGS Cond)
23281 // (Op (CMP (SETCC Cond EFLAGS) 0) EQ) or
23282 // (Op (CMP (SETCC Cond EFLAGS) 1) NEQ)
23283 // to (Op EFLAGS !Cond)
23285 // where Op could be BRCOND or CMOV.
23287 static SDValue checkBoolTestSetCCCombine(SDValue Cmp, X86::CondCode &CC) {
23288 // Quit if not CMP and SUB with its value result used.
23289 if (Cmp.getOpcode() != X86ISD::CMP &&
23290 (Cmp.getOpcode() != X86ISD::SUB || Cmp.getNode()->hasAnyUseOfValue(0)))
23293 // Quit if not used as a boolean value.
23294 if (CC != X86::COND_E && CC != X86::COND_NE)
23297 // Check CMP operands. One of them should be 0 or 1 and the other should be
23298 // an SetCC or extended from it.
23299 SDValue Op1 = Cmp.getOperand(0);
23300 SDValue Op2 = Cmp.getOperand(1);
23303 const ConstantSDNode* C = nullptr;
23304 bool needOppositeCond = (CC == X86::COND_E);
23305 bool checkAgainstTrue = false; // Is it a comparison against 1?
23307 if ((C = dyn_cast<ConstantSDNode>(Op1)))
23309 else if ((C = dyn_cast<ConstantSDNode>(Op2)))
23311 else // Quit if all operands are not constants.
23314 if (C->getZExtValue() == 1) {
23315 needOppositeCond = !needOppositeCond;
23316 checkAgainstTrue = true;
23317 } else if (C->getZExtValue() != 0)
23318 // Quit if the constant is neither 0 or 1.
23321 bool truncatedToBoolWithAnd = false;
23322 // Skip (zext $x), (trunc $x), or (and $x, 1) node.
23323 while (SetCC.getOpcode() == ISD::ZERO_EXTEND ||
23324 SetCC.getOpcode() == ISD::TRUNCATE ||
23325 SetCC.getOpcode() == ISD::AND) {
23326 if (SetCC.getOpcode() == ISD::AND) {
23328 ConstantSDNode *CS;
23329 if ((CS = dyn_cast<ConstantSDNode>(SetCC.getOperand(0))) &&
23330 CS->getZExtValue() == 1)
23332 if ((CS = dyn_cast<ConstantSDNode>(SetCC.getOperand(1))) &&
23333 CS->getZExtValue() == 1)
23337 SetCC = SetCC.getOperand(OpIdx);
23338 truncatedToBoolWithAnd = true;
23340 SetCC = SetCC.getOperand(0);
23343 switch (SetCC.getOpcode()) {
23344 case X86ISD::SETCC_CARRY:
23345 // Since SETCC_CARRY gives output based on R = CF ? ~0 : 0, it's unsafe to
23346 // simplify it if the result of SETCC_CARRY is not canonicalized to 0 or 1,
23347 // i.e. it's a comparison against true but the result of SETCC_CARRY is not
23348 // truncated to i1 using 'and'.
23349 if (checkAgainstTrue && !truncatedToBoolWithAnd)
23351 assert(X86::CondCode(SetCC.getConstantOperandVal(0)) == X86::COND_B &&
23352 "Invalid use of SETCC_CARRY!");
23354 case X86ISD::SETCC:
23355 // Set the condition code or opposite one if necessary.
23356 CC = X86::CondCode(SetCC.getConstantOperandVal(0));
23357 if (needOppositeCond)
23358 CC = X86::GetOppositeBranchCondition(CC);
23359 return SetCC.getOperand(1);
23360 case X86ISD::CMOV: {
23361 // Check whether false/true value has canonical one, i.e. 0 or 1.
23362 ConstantSDNode *FVal = dyn_cast<ConstantSDNode>(SetCC.getOperand(0));
23363 ConstantSDNode *TVal = dyn_cast<ConstantSDNode>(SetCC.getOperand(1));
23364 // Quit if true value is not a constant.
23367 // Quit if false value is not a constant.
23369 SDValue Op = SetCC.getOperand(0);
23370 // Skip 'zext' or 'trunc' node.
23371 if (Op.getOpcode() == ISD::ZERO_EXTEND ||
23372 Op.getOpcode() == ISD::TRUNCATE)
23373 Op = Op.getOperand(0);
23374 // A special case for rdrand/rdseed, where 0 is set if false cond is
23376 if ((Op.getOpcode() != X86ISD::RDRAND &&
23377 Op.getOpcode() != X86ISD::RDSEED) || Op.getResNo() != 0)
23380 // Quit if false value is not the constant 0 or 1.
23381 bool FValIsFalse = true;
23382 if (FVal && FVal->getZExtValue() != 0) {
23383 if (FVal->getZExtValue() != 1)
23385 // If FVal is 1, opposite cond is needed.
23386 needOppositeCond = !needOppositeCond;
23387 FValIsFalse = false;
23389 // Quit if TVal is not the constant opposite of FVal.
23390 if (FValIsFalse && TVal->getZExtValue() != 1)
23392 if (!FValIsFalse && TVal->getZExtValue() != 0)
23394 CC = X86::CondCode(SetCC.getConstantOperandVal(2));
23395 if (needOppositeCond)
23396 CC = X86::GetOppositeBranchCondition(CC);
23397 return SetCC.getOperand(3);
23404 /// Optimize X86ISD::CMOV [LHS, RHS, CONDCODE (e.g. X86::COND_NE), CONDVAL]
23405 static SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG,
23406 TargetLowering::DAGCombinerInfo &DCI,
23407 const X86Subtarget *Subtarget) {
23410 // If the flag operand isn't dead, don't touch this CMOV.
23411 if (N->getNumValues() == 2 && !SDValue(N, 1).use_empty())
23414 SDValue FalseOp = N->getOperand(0);
23415 SDValue TrueOp = N->getOperand(1);
23416 X86::CondCode CC = (X86::CondCode)N->getConstantOperandVal(2);
23417 SDValue Cond = N->getOperand(3);
23419 if (CC == X86::COND_E || CC == X86::COND_NE) {
23420 switch (Cond.getOpcode()) {
23424 // If operand of BSR / BSF are proven never zero, then ZF cannot be set.
23425 if (DAG.isKnownNeverZero(Cond.getOperand(0)))
23426 return (CC == X86::COND_E) ? FalseOp : TrueOp;
23432 Flags = checkBoolTestSetCCCombine(Cond, CC);
23433 if (Flags.getNode() &&
23434 // Extra check as FCMOV only supports a subset of X86 cond.
23435 (FalseOp.getValueType() != MVT::f80 || hasFPCMov(CC))) {
23436 SDValue Ops[] = { FalseOp, TrueOp,
23437 DAG.getConstant(CC, MVT::i8), Flags };
23438 return DAG.getNode(X86ISD::CMOV, DL, N->getVTList(), Ops);
23441 // If this is a select between two integer constants, try to do some
23442 // optimizations. Note that the operands are ordered the opposite of SELECT
23444 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(TrueOp)) {
23445 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(FalseOp)) {
23446 // Canonicalize the TrueC/FalseC values so that TrueC (the true value) is
23447 // larger than FalseC (the false value).
23448 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue())) {
23449 CC = X86::GetOppositeBranchCondition(CC);
23450 std::swap(TrueC, FalseC);
23451 std::swap(TrueOp, FalseOp);
23454 // Optimize C ? 8 : 0 -> zext(setcc(C)) << 3. Likewise for any pow2/0.
23455 // This is efficient for any integer data type (including i8/i16) and
23457 if (FalseC->getAPIntValue() == 0 && TrueC->getAPIntValue().isPowerOf2()) {
23458 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
23459 DAG.getConstant(CC, MVT::i8), Cond);
23461 // Zero extend the condition if needed.
23462 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, TrueC->getValueType(0), Cond);
23464 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
23465 Cond = DAG.getNode(ISD::SHL, DL, Cond.getValueType(), Cond,
23466 DAG.getConstant(ShAmt, MVT::i8));
23467 if (N->getNumValues() == 2) // Dead flag value?
23468 return DCI.CombineTo(N, Cond, SDValue());
23472 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst. This is efficient
23473 // for any integer data type, including i8/i16.
23474 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
23475 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
23476 DAG.getConstant(CC, MVT::i8), Cond);
23478 // Zero extend the condition if needed.
23479 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
23480 FalseC->getValueType(0), Cond);
23481 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
23482 SDValue(FalseC, 0));
23484 if (N->getNumValues() == 2) // Dead flag value?
23485 return DCI.CombineTo(N, Cond, SDValue());
23489 // Optimize cases that will turn into an LEA instruction. This requires
23490 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
23491 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
23492 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
23493 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
23495 bool isFastMultiplier = false;
23497 switch ((unsigned char)Diff) {
23499 case 1: // result = add base, cond
23500 case 2: // result = lea base( , cond*2)
23501 case 3: // result = lea base(cond, cond*2)
23502 case 4: // result = lea base( , cond*4)
23503 case 5: // result = lea base(cond, cond*4)
23504 case 8: // result = lea base( , cond*8)
23505 case 9: // result = lea base(cond, cond*8)
23506 isFastMultiplier = true;
23511 if (isFastMultiplier) {
23512 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
23513 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
23514 DAG.getConstant(CC, MVT::i8), Cond);
23515 // Zero extend the condition if needed.
23516 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
23518 // Scale the condition by the difference.
23520 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
23521 DAG.getConstant(Diff, Cond.getValueType()));
23523 // Add the base if non-zero.
23524 if (FalseC->getAPIntValue() != 0)
23525 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
23526 SDValue(FalseC, 0));
23527 if (N->getNumValues() == 2) // Dead flag value?
23528 return DCI.CombineTo(N, Cond, SDValue());
23535 // Handle these cases:
23536 // (select (x != c), e, c) -> select (x != c), e, x),
23537 // (select (x == c), c, e) -> select (x == c), x, e)
23538 // where the c is an integer constant, and the "select" is the combination
23539 // of CMOV and CMP.
23541 // The rationale for this change is that the conditional-move from a constant
23542 // needs two instructions, however, conditional-move from a register needs
23543 // only one instruction.
23545 // CAVEAT: By replacing a constant with a symbolic value, it may obscure
23546 // some instruction-combining opportunities. This opt needs to be
23547 // postponed as late as possible.
23549 if (!DCI.isBeforeLegalize() && !DCI.isBeforeLegalizeOps()) {
23550 // the DCI.xxxx conditions are provided to postpone the optimization as
23551 // late as possible.
23553 ConstantSDNode *CmpAgainst = nullptr;
23554 if ((Cond.getOpcode() == X86ISD::CMP || Cond.getOpcode() == X86ISD::SUB) &&
23555 (CmpAgainst = dyn_cast<ConstantSDNode>(Cond.getOperand(1))) &&
23556 !isa<ConstantSDNode>(Cond.getOperand(0))) {
23558 if (CC == X86::COND_NE &&
23559 CmpAgainst == dyn_cast<ConstantSDNode>(FalseOp)) {
23560 CC = X86::GetOppositeBranchCondition(CC);
23561 std::swap(TrueOp, FalseOp);
23564 if (CC == X86::COND_E &&
23565 CmpAgainst == dyn_cast<ConstantSDNode>(TrueOp)) {
23566 SDValue Ops[] = { FalseOp, Cond.getOperand(0),
23567 DAG.getConstant(CC, MVT::i8), Cond };
23568 return DAG.getNode(X86ISD::CMOV, DL, N->getVTList (), Ops);
23576 static SDValue PerformINTRINSIC_WO_CHAINCombine(SDNode *N, SelectionDAG &DAG,
23577 const X86Subtarget *Subtarget) {
23578 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(0))->getZExtValue();
23580 default: return SDValue();
23581 // SSE/AVX/AVX2 blend intrinsics.
23582 case Intrinsic::x86_avx2_pblendvb:
23583 case Intrinsic::x86_avx2_pblendw:
23584 case Intrinsic::x86_avx2_pblendd_128:
23585 case Intrinsic::x86_avx2_pblendd_256:
23586 // Don't try to simplify this intrinsic if we don't have AVX2.
23587 if (!Subtarget->hasAVX2())
23590 case Intrinsic::x86_avx_blend_pd_256:
23591 case Intrinsic::x86_avx_blend_ps_256:
23592 case Intrinsic::x86_avx_blendv_pd_256:
23593 case Intrinsic::x86_avx_blendv_ps_256:
23594 // Don't try to simplify this intrinsic if we don't have AVX.
23595 if (!Subtarget->hasAVX())
23598 case Intrinsic::x86_sse41_pblendw:
23599 case Intrinsic::x86_sse41_blendpd:
23600 case Intrinsic::x86_sse41_blendps:
23601 case Intrinsic::x86_sse41_blendvps:
23602 case Intrinsic::x86_sse41_blendvpd:
23603 case Intrinsic::x86_sse41_pblendvb: {
23604 SDValue Op0 = N->getOperand(1);
23605 SDValue Op1 = N->getOperand(2);
23606 SDValue Mask = N->getOperand(3);
23608 // Don't try to simplify this intrinsic if we don't have SSE4.1.
23609 if (!Subtarget->hasSSE41())
23612 // fold (blend A, A, Mask) -> A
23615 // fold (blend A, B, allZeros) -> A
23616 if (ISD::isBuildVectorAllZeros(Mask.getNode()))
23618 // fold (blend A, B, allOnes) -> B
23619 if (ISD::isBuildVectorAllOnes(Mask.getNode()))
23622 // Simplify the case where the mask is a constant i32 value.
23623 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Mask)) {
23624 if (C->isNullValue())
23626 if (C->isAllOnesValue())
23633 // Packed SSE2/AVX2 arithmetic shift immediate intrinsics.
23634 case Intrinsic::x86_sse2_psrai_w:
23635 case Intrinsic::x86_sse2_psrai_d:
23636 case Intrinsic::x86_avx2_psrai_w:
23637 case Intrinsic::x86_avx2_psrai_d:
23638 case Intrinsic::x86_sse2_psra_w:
23639 case Intrinsic::x86_sse2_psra_d:
23640 case Intrinsic::x86_avx2_psra_w:
23641 case Intrinsic::x86_avx2_psra_d: {
23642 SDValue Op0 = N->getOperand(1);
23643 SDValue Op1 = N->getOperand(2);
23644 EVT VT = Op0.getValueType();
23645 assert(VT.isVector() && "Expected a vector type!");
23647 if (isa<BuildVectorSDNode>(Op1))
23648 Op1 = Op1.getOperand(0);
23650 if (!isa<ConstantSDNode>(Op1))
23653 EVT SVT = VT.getVectorElementType();
23654 unsigned SVTBits = SVT.getSizeInBits();
23656 ConstantSDNode *CND = cast<ConstantSDNode>(Op1);
23657 const APInt &C = APInt(SVTBits, CND->getAPIntValue().getZExtValue());
23658 uint64_t ShAmt = C.getZExtValue();
23660 // Don't try to convert this shift into a ISD::SRA if the shift
23661 // count is bigger than or equal to the element size.
23662 if (ShAmt >= SVTBits)
23665 // Trivial case: if the shift count is zero, then fold this
23666 // into the first operand.
23670 // Replace this packed shift intrinsic with a target independent
23672 SDValue Splat = DAG.getConstant(C, VT);
23673 return DAG.getNode(ISD::SRA, SDLoc(N), VT, Op0, Splat);
23678 /// PerformMulCombine - Optimize a single multiply with constant into two
23679 /// in order to implement it with two cheaper instructions, e.g.
23680 /// LEA + SHL, LEA + LEA.
23681 static SDValue PerformMulCombine(SDNode *N, SelectionDAG &DAG,
23682 TargetLowering::DAGCombinerInfo &DCI) {
23683 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer())
23686 EVT VT = N->getValueType(0);
23687 if (VT != MVT::i64)
23690 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
23693 uint64_t MulAmt = C->getZExtValue();
23694 if (isPowerOf2_64(MulAmt) || MulAmt == 3 || MulAmt == 5 || MulAmt == 9)
23697 uint64_t MulAmt1 = 0;
23698 uint64_t MulAmt2 = 0;
23699 if ((MulAmt % 9) == 0) {
23701 MulAmt2 = MulAmt / 9;
23702 } else if ((MulAmt % 5) == 0) {
23704 MulAmt2 = MulAmt / 5;
23705 } else if ((MulAmt % 3) == 0) {
23707 MulAmt2 = MulAmt / 3;
23710 (isPowerOf2_64(MulAmt2) || MulAmt2 == 3 || MulAmt2 == 5 || MulAmt2 == 9)){
23713 if (isPowerOf2_64(MulAmt2) &&
23714 !(N->hasOneUse() && N->use_begin()->getOpcode() == ISD::ADD))
23715 // If second multiplifer is pow2, issue it first. We want the multiply by
23716 // 3, 5, or 9 to be folded into the addressing mode unless the lone use
23718 std::swap(MulAmt1, MulAmt2);
23721 if (isPowerOf2_64(MulAmt1))
23722 NewMul = DAG.getNode(ISD::SHL, DL, VT, N->getOperand(0),
23723 DAG.getConstant(Log2_64(MulAmt1), MVT::i8));
23725 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, N->getOperand(0),
23726 DAG.getConstant(MulAmt1, VT));
23728 if (isPowerOf2_64(MulAmt2))
23729 NewMul = DAG.getNode(ISD::SHL, DL, VT, NewMul,
23730 DAG.getConstant(Log2_64(MulAmt2), MVT::i8));
23732 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, NewMul,
23733 DAG.getConstant(MulAmt2, VT));
23735 // Do not add new nodes to DAG combiner worklist.
23736 DCI.CombineTo(N, NewMul, false);
23741 static SDValue PerformSHLCombine(SDNode *N, SelectionDAG &DAG) {
23742 SDValue N0 = N->getOperand(0);
23743 SDValue N1 = N->getOperand(1);
23744 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
23745 EVT VT = N0.getValueType();
23747 // fold (shl (and (setcc_c), c1), c2) -> (and setcc_c, (c1 << c2))
23748 // since the result of setcc_c is all zero's or all ones.
23749 if (VT.isInteger() && !VT.isVector() &&
23750 N1C && N0.getOpcode() == ISD::AND &&
23751 N0.getOperand(1).getOpcode() == ISD::Constant) {
23752 SDValue N00 = N0.getOperand(0);
23753 if (N00.getOpcode() == X86ISD::SETCC_CARRY ||
23754 ((N00.getOpcode() == ISD::ANY_EXTEND ||
23755 N00.getOpcode() == ISD::ZERO_EXTEND) &&
23756 N00.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY)) {
23757 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
23758 APInt ShAmt = N1C->getAPIntValue();
23759 Mask = Mask.shl(ShAmt);
23761 return DAG.getNode(ISD::AND, SDLoc(N), VT,
23762 N00, DAG.getConstant(Mask, VT));
23766 // Hardware support for vector shifts is sparse which makes us scalarize the
23767 // vector operations in many cases. Also, on sandybridge ADD is faster than
23769 // (shl V, 1) -> add V,V
23770 if (auto *N1BV = dyn_cast<BuildVectorSDNode>(N1))
23771 if (auto *N1SplatC = N1BV->getConstantSplatNode()) {
23772 assert(N0.getValueType().isVector() && "Invalid vector shift type");
23773 // We shift all of the values by one. In many cases we do not have
23774 // hardware support for this operation. This is better expressed as an ADD
23776 if (N1SplatC->getZExtValue() == 1)
23777 return DAG.getNode(ISD::ADD, SDLoc(N), VT, N0, N0);
23783 /// \brief Returns a vector of 0s if the node in input is a vector logical
23784 /// shift by a constant amount which is known to be bigger than or equal
23785 /// to the vector element size in bits.
23786 static SDValue performShiftToAllZeros(SDNode *N, SelectionDAG &DAG,
23787 const X86Subtarget *Subtarget) {
23788 EVT VT = N->getValueType(0);
23790 if (VT != MVT::v2i64 && VT != MVT::v4i32 && VT != MVT::v8i16 &&
23791 (!Subtarget->hasInt256() ||
23792 (VT != MVT::v4i64 && VT != MVT::v8i32 && VT != MVT::v16i16)))
23795 SDValue Amt = N->getOperand(1);
23797 if (auto *AmtBV = dyn_cast<BuildVectorSDNode>(Amt))
23798 if (auto *AmtSplat = AmtBV->getConstantSplatNode()) {
23799 APInt ShiftAmt = AmtSplat->getAPIntValue();
23800 unsigned MaxAmount = VT.getVectorElementType().getSizeInBits();
23802 // SSE2/AVX2 logical shifts always return a vector of 0s
23803 // if the shift amount is bigger than or equal to
23804 // the element size. The constant shift amount will be
23805 // encoded as a 8-bit immediate.
23806 if (ShiftAmt.trunc(8).uge(MaxAmount))
23807 return getZeroVector(VT, Subtarget, DAG, DL);
23813 /// PerformShiftCombine - Combine shifts.
23814 static SDValue PerformShiftCombine(SDNode* N, SelectionDAG &DAG,
23815 TargetLowering::DAGCombinerInfo &DCI,
23816 const X86Subtarget *Subtarget) {
23817 if (N->getOpcode() == ISD::SHL) {
23818 SDValue V = PerformSHLCombine(N, DAG);
23819 if (V.getNode()) return V;
23822 if (N->getOpcode() != ISD::SRA) {
23823 // Try to fold this logical shift into a zero vector.
23824 SDValue V = performShiftToAllZeros(N, DAG, Subtarget);
23825 if (V.getNode()) return V;
23831 // CMPEQCombine - Recognize the distinctive (AND (setcc ...) (setcc ..))
23832 // where both setccs reference the same FP CMP, and rewrite for CMPEQSS
23833 // and friends. Likewise for OR -> CMPNEQSS.
23834 static SDValue CMPEQCombine(SDNode *N, SelectionDAG &DAG,
23835 TargetLowering::DAGCombinerInfo &DCI,
23836 const X86Subtarget *Subtarget) {
23839 // SSE1 supports CMP{eq|ne}SS, and SSE2 added CMP{eq|ne}SD, but
23840 // we're requiring SSE2 for both.
23841 if (Subtarget->hasSSE2() && isAndOrOfSetCCs(SDValue(N, 0U), opcode)) {
23842 SDValue N0 = N->getOperand(0);
23843 SDValue N1 = N->getOperand(1);
23844 SDValue CMP0 = N0->getOperand(1);
23845 SDValue CMP1 = N1->getOperand(1);
23848 // The SETCCs should both refer to the same CMP.
23849 if (CMP0.getOpcode() != X86ISD::CMP || CMP0 != CMP1)
23852 SDValue CMP00 = CMP0->getOperand(0);
23853 SDValue CMP01 = CMP0->getOperand(1);
23854 EVT VT = CMP00.getValueType();
23856 if (VT == MVT::f32 || VT == MVT::f64) {
23857 bool ExpectingFlags = false;
23858 // Check for any users that want flags:
23859 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end();
23860 !ExpectingFlags && UI != UE; ++UI)
23861 switch (UI->getOpcode()) {
23866 ExpectingFlags = true;
23868 case ISD::CopyToReg:
23869 case ISD::SIGN_EXTEND:
23870 case ISD::ZERO_EXTEND:
23871 case ISD::ANY_EXTEND:
23875 if (!ExpectingFlags) {
23876 enum X86::CondCode cc0 = (enum X86::CondCode)N0.getConstantOperandVal(0);
23877 enum X86::CondCode cc1 = (enum X86::CondCode)N1.getConstantOperandVal(0);
23879 if (cc1 == X86::COND_E || cc1 == X86::COND_NE) {
23880 X86::CondCode tmp = cc0;
23885 if ((cc0 == X86::COND_E && cc1 == X86::COND_NP) ||
23886 (cc0 == X86::COND_NE && cc1 == X86::COND_P)) {
23887 // FIXME: need symbolic constants for these magic numbers.
23888 // See X86ATTInstPrinter.cpp:printSSECC().
23889 unsigned x86cc = (cc0 == X86::COND_E) ? 0 : 4;
23890 if (Subtarget->hasAVX512()) {
23891 SDValue FSetCC = DAG.getNode(X86ISD::FSETCC, DL, MVT::i1, CMP00,
23892 CMP01, DAG.getConstant(x86cc, MVT::i8));
23893 if (N->getValueType(0) != MVT::i1)
23894 return DAG.getNode(ISD::ZERO_EXTEND, DL, N->getValueType(0),
23898 SDValue OnesOrZeroesF = DAG.getNode(X86ISD::FSETCC, DL,
23899 CMP00.getValueType(), CMP00, CMP01,
23900 DAG.getConstant(x86cc, MVT::i8));
23902 bool is64BitFP = (CMP00.getValueType() == MVT::f64);
23903 MVT IntVT = is64BitFP ? MVT::i64 : MVT::i32;
23905 if (is64BitFP && !Subtarget->is64Bit()) {
23906 // On a 32-bit target, we cannot bitcast the 64-bit float to a
23907 // 64-bit integer, since that's not a legal type. Since
23908 // OnesOrZeroesF is all ones of all zeroes, we don't need all the
23909 // bits, but can do this little dance to extract the lowest 32 bits
23910 // and work with those going forward.
23911 SDValue Vector64 = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, MVT::v2f64,
23913 SDValue Vector32 = DAG.getNode(ISD::BITCAST, DL, MVT::v4f32,
23915 OnesOrZeroesF = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32,
23916 Vector32, DAG.getIntPtrConstant(0));
23920 SDValue OnesOrZeroesI = DAG.getNode(ISD::BITCAST, DL, IntVT, OnesOrZeroesF);
23921 SDValue ANDed = DAG.getNode(ISD::AND, DL, IntVT, OnesOrZeroesI,
23922 DAG.getConstant(1, IntVT));
23923 SDValue OneBitOfTruth = DAG.getNode(ISD::TRUNCATE, DL, MVT::i8, ANDed);
23924 return OneBitOfTruth;
23932 /// CanFoldXORWithAllOnes - Test whether the XOR operand is a AllOnes vector
23933 /// so it can be folded inside ANDNP.
23934 static bool CanFoldXORWithAllOnes(const SDNode *N) {
23935 EVT VT = N->getValueType(0);
23937 // Match direct AllOnes for 128 and 256-bit vectors
23938 if (ISD::isBuildVectorAllOnes(N))
23941 // Look through a bit convert.
23942 if (N->getOpcode() == ISD::BITCAST)
23943 N = N->getOperand(0).getNode();
23945 // Sometimes the operand may come from a insert_subvector building a 256-bit
23947 if (VT.is256BitVector() &&
23948 N->getOpcode() == ISD::INSERT_SUBVECTOR) {
23949 SDValue V1 = N->getOperand(0);
23950 SDValue V2 = N->getOperand(1);
23952 if (V1.getOpcode() == ISD::INSERT_SUBVECTOR &&
23953 V1.getOperand(0).getOpcode() == ISD::UNDEF &&
23954 ISD::isBuildVectorAllOnes(V1.getOperand(1).getNode()) &&
23955 ISD::isBuildVectorAllOnes(V2.getNode()))
23962 // On AVX/AVX2 the type v8i1 is legalized to v8i16, which is an XMM sized
23963 // register. In most cases we actually compare or select YMM-sized registers
23964 // and mixing the two types creates horrible code. This method optimizes
23965 // some of the transition sequences.
23966 static SDValue WidenMaskArithmetic(SDNode *N, SelectionDAG &DAG,
23967 TargetLowering::DAGCombinerInfo &DCI,
23968 const X86Subtarget *Subtarget) {
23969 EVT VT = N->getValueType(0);
23970 if (!VT.is256BitVector())
23973 assert((N->getOpcode() == ISD::ANY_EXTEND ||
23974 N->getOpcode() == ISD::ZERO_EXTEND ||
23975 N->getOpcode() == ISD::SIGN_EXTEND) && "Invalid Node");
23977 SDValue Narrow = N->getOperand(0);
23978 EVT NarrowVT = Narrow->getValueType(0);
23979 if (!NarrowVT.is128BitVector())
23982 if (Narrow->getOpcode() != ISD::XOR &&
23983 Narrow->getOpcode() != ISD::AND &&
23984 Narrow->getOpcode() != ISD::OR)
23987 SDValue N0 = Narrow->getOperand(0);
23988 SDValue N1 = Narrow->getOperand(1);
23991 // The Left side has to be a trunc.
23992 if (N0.getOpcode() != ISD::TRUNCATE)
23995 // The type of the truncated inputs.
23996 EVT WideVT = N0->getOperand(0)->getValueType(0);
24000 // The right side has to be a 'trunc' or a constant vector.
24001 bool RHSTrunc = N1.getOpcode() == ISD::TRUNCATE;
24002 ConstantSDNode *RHSConstSplat = nullptr;
24003 if (auto *RHSBV = dyn_cast<BuildVectorSDNode>(N1))
24004 RHSConstSplat = RHSBV->getConstantSplatNode();
24005 if (!RHSTrunc && !RHSConstSplat)
24008 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
24010 if (!TLI.isOperationLegalOrPromote(Narrow->getOpcode(), WideVT))
24013 // Set N0 and N1 to hold the inputs to the new wide operation.
24014 N0 = N0->getOperand(0);
24015 if (RHSConstSplat) {
24016 N1 = DAG.getNode(ISD::ZERO_EXTEND, DL, WideVT.getScalarType(),
24017 SDValue(RHSConstSplat, 0));
24018 SmallVector<SDValue, 8> C(WideVT.getVectorNumElements(), N1);
24019 N1 = DAG.getNode(ISD::BUILD_VECTOR, DL, WideVT, C);
24020 } else if (RHSTrunc) {
24021 N1 = N1->getOperand(0);
24024 // Generate the wide operation.
24025 SDValue Op = DAG.getNode(Narrow->getOpcode(), DL, WideVT, N0, N1);
24026 unsigned Opcode = N->getOpcode();
24028 case ISD::ANY_EXTEND:
24030 case ISD::ZERO_EXTEND: {
24031 unsigned InBits = NarrowVT.getScalarType().getSizeInBits();
24032 APInt Mask = APInt::getAllOnesValue(InBits);
24033 Mask = Mask.zext(VT.getScalarType().getSizeInBits());
24034 return DAG.getNode(ISD::AND, DL, VT,
24035 Op, DAG.getConstant(Mask, VT));
24037 case ISD::SIGN_EXTEND:
24038 return DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, VT,
24039 Op, DAG.getValueType(NarrowVT));
24041 llvm_unreachable("Unexpected opcode");
24045 static SDValue PerformAndCombine(SDNode *N, SelectionDAG &DAG,
24046 TargetLowering::DAGCombinerInfo &DCI,
24047 const X86Subtarget *Subtarget) {
24048 EVT VT = N->getValueType(0);
24049 if (DCI.isBeforeLegalizeOps())
24052 SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget);
24056 // Create BEXTR instructions
24057 // BEXTR is ((X >> imm) & (2**size-1))
24058 if (VT == MVT::i32 || VT == MVT::i64) {
24059 SDValue N0 = N->getOperand(0);
24060 SDValue N1 = N->getOperand(1);
24063 // Check for BEXTR.
24064 if ((Subtarget->hasBMI() || Subtarget->hasTBM()) &&
24065 (N0.getOpcode() == ISD::SRA || N0.getOpcode() == ISD::SRL)) {
24066 ConstantSDNode *MaskNode = dyn_cast<ConstantSDNode>(N1);
24067 ConstantSDNode *ShiftNode = dyn_cast<ConstantSDNode>(N0.getOperand(1));
24068 if (MaskNode && ShiftNode) {
24069 uint64_t Mask = MaskNode->getZExtValue();
24070 uint64_t Shift = ShiftNode->getZExtValue();
24071 if (isMask_64(Mask)) {
24072 uint64_t MaskSize = CountPopulation_64(Mask);
24073 if (Shift + MaskSize <= VT.getSizeInBits())
24074 return DAG.getNode(X86ISD::BEXTR, DL, VT, N0.getOperand(0),
24075 DAG.getConstant(Shift | (MaskSize << 8), VT));
24083 // Want to form ANDNP nodes:
24084 // 1) In the hopes of then easily combining them with OR and AND nodes
24085 // to form PBLEND/PSIGN.
24086 // 2) To match ANDN packed intrinsics
24087 if (VT != MVT::v2i64 && VT != MVT::v4i64)
24090 SDValue N0 = N->getOperand(0);
24091 SDValue N1 = N->getOperand(1);
24094 // Check LHS for vnot
24095 if (N0.getOpcode() == ISD::XOR &&
24096 //ISD::isBuildVectorAllOnes(N0.getOperand(1).getNode()))
24097 CanFoldXORWithAllOnes(N0.getOperand(1).getNode()))
24098 return DAG.getNode(X86ISD::ANDNP, DL, VT, N0.getOperand(0), N1);
24100 // Check RHS for vnot
24101 if (N1.getOpcode() == ISD::XOR &&
24102 //ISD::isBuildVectorAllOnes(N1.getOperand(1).getNode()))
24103 CanFoldXORWithAllOnes(N1.getOperand(1).getNode()))
24104 return DAG.getNode(X86ISD::ANDNP, DL, VT, N1.getOperand(0), N0);
24109 static SDValue PerformOrCombine(SDNode *N, SelectionDAG &DAG,
24110 TargetLowering::DAGCombinerInfo &DCI,
24111 const X86Subtarget *Subtarget) {
24112 if (DCI.isBeforeLegalizeOps())
24115 SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget);
24119 SDValue N0 = N->getOperand(0);
24120 SDValue N1 = N->getOperand(1);
24121 EVT VT = N->getValueType(0);
24123 // look for psign/blend
24124 if (VT == MVT::v2i64 || VT == MVT::v4i64) {
24125 if (!Subtarget->hasSSSE3() ||
24126 (VT == MVT::v4i64 && !Subtarget->hasInt256()))
24129 // Canonicalize pandn to RHS
24130 if (N0.getOpcode() == X86ISD::ANDNP)
24132 // or (and (m, y), (pandn m, x))
24133 if (N0.getOpcode() == ISD::AND && N1.getOpcode() == X86ISD::ANDNP) {
24134 SDValue Mask = N1.getOperand(0);
24135 SDValue X = N1.getOperand(1);
24137 if (N0.getOperand(0) == Mask)
24138 Y = N0.getOperand(1);
24139 if (N0.getOperand(1) == Mask)
24140 Y = N0.getOperand(0);
24142 // Check to see if the mask appeared in both the AND and ANDNP and
24146 // Validate that X, Y, and Mask are BIT_CONVERTS, and see through them.
24147 // Look through mask bitcast.
24148 if (Mask.getOpcode() == ISD::BITCAST)
24149 Mask = Mask.getOperand(0);
24150 if (X.getOpcode() == ISD::BITCAST)
24151 X = X.getOperand(0);
24152 if (Y.getOpcode() == ISD::BITCAST)
24153 Y = Y.getOperand(0);
24155 EVT MaskVT = Mask.getValueType();
24157 // Validate that the Mask operand is a vector sra node.
24158 // FIXME: what to do for bytes, since there is a psignb/pblendvb, but
24159 // there is no psrai.b
24160 unsigned EltBits = MaskVT.getVectorElementType().getSizeInBits();
24161 unsigned SraAmt = ~0;
24162 if (Mask.getOpcode() == ISD::SRA) {
24163 if (auto *AmtBV = dyn_cast<BuildVectorSDNode>(Mask.getOperand(1)))
24164 if (auto *AmtConst = AmtBV->getConstantSplatNode())
24165 SraAmt = AmtConst->getZExtValue();
24166 } else if (Mask.getOpcode() == X86ISD::VSRAI) {
24167 SDValue SraC = Mask.getOperand(1);
24168 SraAmt = cast<ConstantSDNode>(SraC)->getZExtValue();
24170 if ((SraAmt + 1) != EltBits)
24175 // Now we know we at least have a plendvb with the mask val. See if
24176 // we can form a psignb/w/d.
24177 // psign = x.type == y.type == mask.type && y = sub(0, x);
24178 if (Y.getOpcode() == ISD::SUB && Y.getOperand(1) == X &&
24179 ISD::isBuildVectorAllZeros(Y.getOperand(0).getNode()) &&
24180 X.getValueType() == MaskVT && Y.getValueType() == MaskVT) {
24181 assert((EltBits == 8 || EltBits == 16 || EltBits == 32) &&
24182 "Unsupported VT for PSIGN");
24183 Mask = DAG.getNode(X86ISD::PSIGN, DL, MaskVT, X, Mask.getOperand(0));
24184 return DAG.getNode(ISD::BITCAST, DL, VT, Mask);
24186 // PBLENDVB only available on SSE 4.1
24187 if (!Subtarget->hasSSE41())
24190 EVT BlendVT = (VT == MVT::v4i64) ? MVT::v32i8 : MVT::v16i8;
24192 X = DAG.getNode(ISD::BITCAST, DL, BlendVT, X);
24193 Y = DAG.getNode(ISD::BITCAST, DL, BlendVT, Y);
24194 Mask = DAG.getNode(ISD::BITCAST, DL, BlendVT, Mask);
24195 Mask = DAG.getNode(ISD::VSELECT, DL, BlendVT, Mask, Y, X);
24196 return DAG.getNode(ISD::BITCAST, DL, VT, Mask);
24200 if (VT != MVT::i16 && VT != MVT::i32 && VT != MVT::i64)
24203 // fold (or (x << c) | (y >> (64 - c))) ==> (shld64 x, y, c)
24204 MachineFunction &MF = DAG.getMachineFunction();
24205 bool OptForSize = MF.getFunction()->getAttributes().
24206 hasAttribute(AttributeSet::FunctionIndex, Attribute::OptimizeForSize);
24208 // SHLD/SHRD instructions have lower register pressure, but on some
24209 // platforms they have higher latency than the equivalent
24210 // series of shifts/or that would otherwise be generated.
24211 // Don't fold (or (x << c) | (y >> (64 - c))) if SHLD/SHRD instructions
24212 // have higher latencies and we are not optimizing for size.
24213 if (!OptForSize && Subtarget->isSHLDSlow())
24216 if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL)
24218 if (N0.getOpcode() != ISD::SHL || N1.getOpcode() != ISD::SRL)
24220 if (!N0.hasOneUse() || !N1.hasOneUse())
24223 SDValue ShAmt0 = N0.getOperand(1);
24224 if (ShAmt0.getValueType() != MVT::i8)
24226 SDValue ShAmt1 = N1.getOperand(1);
24227 if (ShAmt1.getValueType() != MVT::i8)
24229 if (ShAmt0.getOpcode() == ISD::TRUNCATE)
24230 ShAmt0 = ShAmt0.getOperand(0);
24231 if (ShAmt1.getOpcode() == ISD::TRUNCATE)
24232 ShAmt1 = ShAmt1.getOperand(0);
24235 unsigned Opc = X86ISD::SHLD;
24236 SDValue Op0 = N0.getOperand(0);
24237 SDValue Op1 = N1.getOperand(0);
24238 if (ShAmt0.getOpcode() == ISD::SUB) {
24239 Opc = X86ISD::SHRD;
24240 std::swap(Op0, Op1);
24241 std::swap(ShAmt0, ShAmt1);
24244 unsigned Bits = VT.getSizeInBits();
24245 if (ShAmt1.getOpcode() == ISD::SUB) {
24246 SDValue Sum = ShAmt1.getOperand(0);
24247 if (ConstantSDNode *SumC = dyn_cast<ConstantSDNode>(Sum)) {
24248 SDValue ShAmt1Op1 = ShAmt1.getOperand(1);
24249 if (ShAmt1Op1.getNode()->getOpcode() == ISD::TRUNCATE)
24250 ShAmt1Op1 = ShAmt1Op1.getOperand(0);
24251 if (SumC->getSExtValue() == Bits && ShAmt1Op1 == ShAmt0)
24252 return DAG.getNode(Opc, DL, VT,
24254 DAG.getNode(ISD::TRUNCATE, DL,
24257 } else if (ConstantSDNode *ShAmt1C = dyn_cast<ConstantSDNode>(ShAmt1)) {
24258 ConstantSDNode *ShAmt0C = dyn_cast<ConstantSDNode>(ShAmt0);
24260 ShAmt0C->getSExtValue() + ShAmt1C->getSExtValue() == Bits)
24261 return DAG.getNode(Opc, DL, VT,
24262 N0.getOperand(0), N1.getOperand(0),
24263 DAG.getNode(ISD::TRUNCATE, DL,
24270 // Generate NEG and CMOV for integer abs.
24271 static SDValue performIntegerAbsCombine(SDNode *N, SelectionDAG &DAG) {
24272 EVT VT = N->getValueType(0);
24274 // Since X86 does not have CMOV for 8-bit integer, we don't convert
24275 // 8-bit integer abs to NEG and CMOV.
24276 if (VT.isInteger() && VT.getSizeInBits() == 8)
24279 SDValue N0 = N->getOperand(0);
24280 SDValue N1 = N->getOperand(1);
24283 // Check pattern of XOR(ADD(X,Y), Y) where Y is SRA(X, size(X)-1)
24284 // and change it to SUB and CMOV.
24285 if (VT.isInteger() && N->getOpcode() == ISD::XOR &&
24286 N0.getOpcode() == ISD::ADD &&
24287 N0.getOperand(1) == N1 &&
24288 N1.getOpcode() == ISD::SRA &&
24289 N1.getOperand(0) == N0.getOperand(0))
24290 if (ConstantSDNode *Y1C = dyn_cast<ConstantSDNode>(N1.getOperand(1)))
24291 if (Y1C->getAPIntValue() == VT.getSizeInBits()-1) {
24292 // Generate SUB & CMOV.
24293 SDValue Neg = DAG.getNode(X86ISD::SUB, DL, DAG.getVTList(VT, MVT::i32),
24294 DAG.getConstant(0, VT), N0.getOperand(0));
24296 SDValue Ops[] = { N0.getOperand(0), Neg,
24297 DAG.getConstant(X86::COND_GE, MVT::i8),
24298 SDValue(Neg.getNode(), 1) };
24299 return DAG.getNode(X86ISD::CMOV, DL, DAG.getVTList(VT, MVT::Glue), Ops);
24304 // PerformXorCombine - Attempts to turn XOR nodes into BLSMSK nodes
24305 static SDValue PerformXorCombine(SDNode *N, SelectionDAG &DAG,
24306 TargetLowering::DAGCombinerInfo &DCI,
24307 const X86Subtarget *Subtarget) {
24308 if (DCI.isBeforeLegalizeOps())
24311 if (Subtarget->hasCMov()) {
24312 SDValue RV = performIntegerAbsCombine(N, DAG);
24320 /// PerformLOADCombine - Do target-specific dag combines on LOAD nodes.
24321 static SDValue PerformLOADCombine(SDNode *N, SelectionDAG &DAG,
24322 TargetLowering::DAGCombinerInfo &DCI,
24323 const X86Subtarget *Subtarget) {
24324 LoadSDNode *Ld = cast<LoadSDNode>(N);
24325 EVT RegVT = Ld->getValueType(0);
24326 EVT MemVT = Ld->getMemoryVT();
24328 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
24330 // For chips with slow 32-byte unaligned loads, break the 32-byte operation
24331 // into two 16-byte operations.
24332 ISD::LoadExtType Ext = Ld->getExtensionType();
24333 unsigned Alignment = Ld->getAlignment();
24334 bool IsAligned = Alignment == 0 || Alignment >= MemVT.getSizeInBits()/8;
24335 if (RegVT.is256BitVector() && Subtarget->isUnalignedMem32Slow() &&
24336 !DCI.isBeforeLegalizeOps() && !IsAligned && Ext == ISD::NON_EXTLOAD) {
24337 unsigned NumElems = RegVT.getVectorNumElements();
24341 SDValue Ptr = Ld->getBasePtr();
24342 SDValue Increment = DAG.getConstant(16, TLI.getPointerTy());
24344 EVT HalfVT = EVT::getVectorVT(*DAG.getContext(), MemVT.getScalarType(),
24346 SDValue Load1 = DAG.getLoad(HalfVT, dl, Ld->getChain(), Ptr,
24347 Ld->getPointerInfo(), Ld->isVolatile(),
24348 Ld->isNonTemporal(), Ld->isInvariant(),
24350 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
24351 SDValue Load2 = DAG.getLoad(HalfVT, dl, Ld->getChain(), Ptr,
24352 Ld->getPointerInfo(), Ld->isVolatile(),
24353 Ld->isNonTemporal(), Ld->isInvariant(),
24354 std::min(16U, Alignment));
24355 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
24357 Load2.getValue(1));
24359 SDValue NewVec = DAG.getUNDEF(RegVT);
24360 NewVec = Insert128BitVector(NewVec, Load1, 0, DAG, dl);
24361 NewVec = Insert128BitVector(NewVec, Load2, NumElems/2, DAG, dl);
24362 return DCI.CombineTo(N, NewVec, TF, true);
24368 /// PerformSTORECombine - Do target-specific dag combines on STORE nodes.
24369 static SDValue PerformSTORECombine(SDNode *N, SelectionDAG &DAG,
24370 const X86Subtarget *Subtarget) {
24371 StoreSDNode *St = cast<StoreSDNode>(N);
24372 EVT VT = St->getValue().getValueType();
24373 EVT StVT = St->getMemoryVT();
24375 SDValue StoredVal = St->getOperand(1);
24376 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
24378 // If we are saving a concatenation of two XMM registers and 32-byte stores
24379 // are slow, such as on Sandy Bridge, perform two 16-byte stores.
24380 unsigned Alignment = St->getAlignment();
24381 bool IsAligned = Alignment == 0 || Alignment >= VT.getSizeInBits()/8;
24382 if (VT.is256BitVector() && Subtarget->isUnalignedMem32Slow() &&
24383 StVT == VT && !IsAligned) {
24384 unsigned NumElems = VT.getVectorNumElements();
24388 SDValue Value0 = Extract128BitVector(StoredVal, 0, DAG, dl);
24389 SDValue Value1 = Extract128BitVector(StoredVal, NumElems/2, DAG, dl);
24391 SDValue Stride = DAG.getConstant(16, TLI.getPointerTy());
24392 SDValue Ptr0 = St->getBasePtr();
24393 SDValue Ptr1 = DAG.getNode(ISD::ADD, dl, Ptr0.getValueType(), Ptr0, Stride);
24395 SDValue Ch0 = DAG.getStore(St->getChain(), dl, Value0, Ptr0,
24396 St->getPointerInfo(), St->isVolatile(),
24397 St->isNonTemporal(), Alignment);
24398 SDValue Ch1 = DAG.getStore(St->getChain(), dl, Value1, Ptr1,
24399 St->getPointerInfo(), St->isVolatile(),
24400 St->isNonTemporal(),
24401 std::min(16U, Alignment));
24402 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Ch0, Ch1);
24405 // Optimize trunc store (of multiple scalars) to shuffle and store.
24406 // First, pack all of the elements in one place. Next, store to memory
24407 // in fewer chunks.
24408 if (St->isTruncatingStore() && VT.isVector()) {
24409 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
24410 unsigned NumElems = VT.getVectorNumElements();
24411 assert(StVT != VT && "Cannot truncate to the same type");
24412 unsigned FromSz = VT.getVectorElementType().getSizeInBits();
24413 unsigned ToSz = StVT.getVectorElementType().getSizeInBits();
24415 // From, To sizes and ElemCount must be pow of two
24416 if (!isPowerOf2_32(NumElems * FromSz * ToSz)) return SDValue();
24417 // We are going to use the original vector elt for storing.
24418 // Accumulated smaller vector elements must be a multiple of the store size.
24419 if (0 != (NumElems * FromSz) % ToSz) return SDValue();
24421 unsigned SizeRatio = FromSz / ToSz;
24423 assert(SizeRatio * NumElems * ToSz == VT.getSizeInBits());
24425 // Create a type on which we perform the shuffle
24426 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(),
24427 StVT.getScalarType(), NumElems*SizeRatio);
24429 assert(WideVecVT.getSizeInBits() == VT.getSizeInBits());
24431 SDValue WideVec = DAG.getNode(ISD::BITCAST, dl, WideVecVT, St->getValue());
24432 SmallVector<int, 8> ShuffleVec(NumElems * SizeRatio, -1);
24433 for (unsigned i = 0; i != NumElems; ++i)
24434 ShuffleVec[i] = i * SizeRatio;
24436 // Can't shuffle using an illegal type.
24437 if (!TLI.isTypeLegal(WideVecVT))
24440 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, WideVec,
24441 DAG.getUNDEF(WideVecVT),
24443 // At this point all of the data is stored at the bottom of the
24444 // register. We now need to save it to mem.
24446 // Find the largest store unit
24447 MVT StoreType = MVT::i8;
24448 for (unsigned tp = MVT::FIRST_INTEGER_VALUETYPE;
24449 tp < MVT::LAST_INTEGER_VALUETYPE; ++tp) {
24450 MVT Tp = (MVT::SimpleValueType)tp;
24451 if (TLI.isTypeLegal(Tp) && Tp.getSizeInBits() <= NumElems * ToSz)
24455 // On 32bit systems, we can't save 64bit integers. Try bitcasting to F64.
24456 if (TLI.isTypeLegal(MVT::f64) && StoreType.getSizeInBits() < 64 &&
24457 (64 <= NumElems * ToSz))
24458 StoreType = MVT::f64;
24460 // Bitcast the original vector into a vector of store-size units
24461 EVT StoreVecVT = EVT::getVectorVT(*DAG.getContext(),
24462 StoreType, VT.getSizeInBits()/StoreType.getSizeInBits());
24463 assert(StoreVecVT.getSizeInBits() == VT.getSizeInBits());
24464 SDValue ShuffWide = DAG.getNode(ISD::BITCAST, dl, StoreVecVT, Shuff);
24465 SmallVector<SDValue, 8> Chains;
24466 SDValue Increment = DAG.getConstant(StoreType.getSizeInBits()/8,
24467 TLI.getPointerTy());
24468 SDValue Ptr = St->getBasePtr();
24470 // Perform one or more big stores into memory.
24471 for (unsigned i=0, e=(ToSz*NumElems)/StoreType.getSizeInBits(); i!=e; ++i) {
24472 SDValue SubVec = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
24473 StoreType, ShuffWide,
24474 DAG.getIntPtrConstant(i));
24475 SDValue Ch = DAG.getStore(St->getChain(), dl, SubVec, Ptr,
24476 St->getPointerInfo(), St->isVolatile(),
24477 St->isNonTemporal(), St->getAlignment());
24478 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
24479 Chains.push_back(Ch);
24482 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Chains);
24485 // Turn load->store of MMX types into GPR load/stores. This avoids clobbering
24486 // the FP state in cases where an emms may be missing.
24487 // A preferable solution to the general problem is to figure out the right
24488 // places to insert EMMS. This qualifies as a quick hack.
24490 // Similarly, turn load->store of i64 into double load/stores in 32-bit mode.
24491 if (VT.getSizeInBits() != 64)
24494 const Function *F = DAG.getMachineFunction().getFunction();
24495 bool NoImplicitFloatOps = F->getAttributes().
24496 hasAttribute(AttributeSet::FunctionIndex, Attribute::NoImplicitFloat);
24497 bool F64IsLegal = !DAG.getTarget().Options.UseSoftFloat && !NoImplicitFloatOps
24498 && Subtarget->hasSSE2();
24499 if ((VT.isVector() ||
24500 (VT == MVT::i64 && F64IsLegal && !Subtarget->is64Bit())) &&
24501 isa<LoadSDNode>(St->getValue()) &&
24502 !cast<LoadSDNode>(St->getValue())->isVolatile() &&
24503 St->getChain().hasOneUse() && !St->isVolatile()) {
24504 SDNode* LdVal = St->getValue().getNode();
24505 LoadSDNode *Ld = nullptr;
24506 int TokenFactorIndex = -1;
24507 SmallVector<SDValue, 8> Ops;
24508 SDNode* ChainVal = St->getChain().getNode();
24509 // Must be a store of a load. We currently handle two cases: the load
24510 // is a direct child, and it's under an intervening TokenFactor. It is
24511 // possible to dig deeper under nested TokenFactors.
24512 if (ChainVal == LdVal)
24513 Ld = cast<LoadSDNode>(St->getChain());
24514 else if (St->getValue().hasOneUse() &&
24515 ChainVal->getOpcode() == ISD::TokenFactor) {
24516 for (unsigned i = 0, e = ChainVal->getNumOperands(); i != e; ++i) {
24517 if (ChainVal->getOperand(i).getNode() == LdVal) {
24518 TokenFactorIndex = i;
24519 Ld = cast<LoadSDNode>(St->getValue());
24521 Ops.push_back(ChainVal->getOperand(i));
24525 if (!Ld || !ISD::isNormalLoad(Ld))
24528 // If this is not the MMX case, i.e. we are just turning i64 load/store
24529 // into f64 load/store, avoid the transformation if there are multiple
24530 // uses of the loaded value.
24531 if (!VT.isVector() && !Ld->hasNUsesOfValue(1, 0))
24536 // If we are a 64-bit capable x86, lower to a single movq load/store pair.
24537 // Otherwise, if it's legal to use f64 SSE instructions, use f64 load/store
24539 if (Subtarget->is64Bit() || F64IsLegal) {
24540 EVT LdVT = Subtarget->is64Bit() ? MVT::i64 : MVT::f64;
24541 SDValue NewLd = DAG.getLoad(LdVT, LdDL, Ld->getChain(), Ld->getBasePtr(),
24542 Ld->getPointerInfo(), Ld->isVolatile(),
24543 Ld->isNonTemporal(), Ld->isInvariant(),
24544 Ld->getAlignment());
24545 SDValue NewChain = NewLd.getValue(1);
24546 if (TokenFactorIndex != -1) {
24547 Ops.push_back(NewChain);
24548 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, Ops);
24550 return DAG.getStore(NewChain, StDL, NewLd, St->getBasePtr(),
24551 St->getPointerInfo(),
24552 St->isVolatile(), St->isNonTemporal(),
24553 St->getAlignment());
24556 // Otherwise, lower to two pairs of 32-bit loads / stores.
24557 SDValue LoAddr = Ld->getBasePtr();
24558 SDValue HiAddr = DAG.getNode(ISD::ADD, LdDL, MVT::i32, LoAddr,
24559 DAG.getConstant(4, MVT::i32));
24561 SDValue LoLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), LoAddr,
24562 Ld->getPointerInfo(),
24563 Ld->isVolatile(), Ld->isNonTemporal(),
24564 Ld->isInvariant(), Ld->getAlignment());
24565 SDValue HiLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), HiAddr,
24566 Ld->getPointerInfo().getWithOffset(4),
24567 Ld->isVolatile(), Ld->isNonTemporal(),
24569 MinAlign(Ld->getAlignment(), 4));
24571 SDValue NewChain = LoLd.getValue(1);
24572 if (TokenFactorIndex != -1) {
24573 Ops.push_back(LoLd);
24574 Ops.push_back(HiLd);
24575 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, Ops);
24578 LoAddr = St->getBasePtr();
24579 HiAddr = DAG.getNode(ISD::ADD, StDL, MVT::i32, LoAddr,
24580 DAG.getConstant(4, MVT::i32));
24582 SDValue LoSt = DAG.getStore(NewChain, StDL, LoLd, LoAddr,
24583 St->getPointerInfo(),
24584 St->isVolatile(), St->isNonTemporal(),
24585 St->getAlignment());
24586 SDValue HiSt = DAG.getStore(NewChain, StDL, HiLd, HiAddr,
24587 St->getPointerInfo().getWithOffset(4),
24589 St->isNonTemporal(),
24590 MinAlign(St->getAlignment(), 4));
24591 return DAG.getNode(ISD::TokenFactor, StDL, MVT::Other, LoSt, HiSt);
24596 /// isHorizontalBinOp - Return 'true' if this vector operation is "horizontal"
24597 /// and return the operands for the horizontal operation in LHS and RHS. A
24598 /// horizontal operation performs the binary operation on successive elements
24599 /// of its first operand, then on successive elements of its second operand,
24600 /// returning the resulting values in a vector. For example, if
24601 /// A = < float a0, float a1, float a2, float a3 >
24603 /// B = < float b0, float b1, float b2, float b3 >
24604 /// then the result of doing a horizontal operation on A and B is
24605 /// A horizontal-op B = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >.
24606 /// In short, LHS and RHS are inspected to see if LHS op RHS is of the form
24607 /// A horizontal-op B, for some already available A and B, and if so then LHS is
24608 /// set to A, RHS to B, and the routine returns 'true'.
24609 /// Note that the binary operation should have the property that if one of the
24610 /// operands is UNDEF then the result is UNDEF.
24611 static bool isHorizontalBinOp(SDValue &LHS, SDValue &RHS, bool IsCommutative) {
24612 // Look for the following pattern: if
24613 // A = < float a0, float a1, float a2, float a3 >
24614 // B = < float b0, float b1, float b2, float b3 >
24616 // LHS = VECTOR_SHUFFLE A, B, <0, 2, 4, 6>
24617 // RHS = VECTOR_SHUFFLE A, B, <1, 3, 5, 7>
24618 // then LHS op RHS = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >
24619 // which is A horizontal-op B.
24621 // At least one of the operands should be a vector shuffle.
24622 if (LHS.getOpcode() != ISD::VECTOR_SHUFFLE &&
24623 RHS.getOpcode() != ISD::VECTOR_SHUFFLE)
24626 MVT VT = LHS.getSimpleValueType();
24628 assert((VT.is128BitVector() || VT.is256BitVector()) &&
24629 "Unsupported vector type for horizontal add/sub");
24631 // Handle 128 and 256-bit vector lengths. AVX defines horizontal add/sub to
24632 // operate independently on 128-bit lanes.
24633 unsigned NumElts = VT.getVectorNumElements();
24634 unsigned NumLanes = VT.getSizeInBits()/128;
24635 unsigned NumLaneElts = NumElts / NumLanes;
24636 assert((NumLaneElts % 2 == 0) &&
24637 "Vector type should have an even number of elements in each lane");
24638 unsigned HalfLaneElts = NumLaneElts/2;
24640 // View LHS in the form
24641 // LHS = VECTOR_SHUFFLE A, B, LMask
24642 // If LHS is not a shuffle then pretend it is the shuffle
24643 // LHS = VECTOR_SHUFFLE LHS, undef, <0, 1, ..., N-1>
24644 // NOTE: in what follows a default initialized SDValue represents an UNDEF of
24647 SmallVector<int, 16> LMask(NumElts);
24648 if (LHS.getOpcode() == ISD::VECTOR_SHUFFLE) {
24649 if (LHS.getOperand(0).getOpcode() != ISD::UNDEF)
24650 A = LHS.getOperand(0);
24651 if (LHS.getOperand(1).getOpcode() != ISD::UNDEF)
24652 B = LHS.getOperand(1);
24653 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(LHS.getNode())->getMask();
24654 std::copy(Mask.begin(), Mask.end(), LMask.begin());
24656 if (LHS.getOpcode() != ISD::UNDEF)
24658 for (unsigned i = 0; i != NumElts; ++i)
24662 // Likewise, view RHS in the form
24663 // RHS = VECTOR_SHUFFLE C, D, RMask
24665 SmallVector<int, 16> RMask(NumElts);
24666 if (RHS.getOpcode() == ISD::VECTOR_SHUFFLE) {
24667 if (RHS.getOperand(0).getOpcode() != ISD::UNDEF)
24668 C = RHS.getOperand(0);
24669 if (RHS.getOperand(1).getOpcode() != ISD::UNDEF)
24670 D = RHS.getOperand(1);
24671 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(RHS.getNode())->getMask();
24672 std::copy(Mask.begin(), Mask.end(), RMask.begin());
24674 if (RHS.getOpcode() != ISD::UNDEF)
24676 for (unsigned i = 0; i != NumElts; ++i)
24680 // Check that the shuffles are both shuffling the same vectors.
24681 if (!(A == C && B == D) && !(A == D && B == C))
24684 // If everything is UNDEF then bail out: it would be better to fold to UNDEF.
24685 if (!A.getNode() && !B.getNode())
24688 // If A and B occur in reverse order in RHS, then "swap" them (which means
24689 // rewriting the mask).
24691 CommuteVectorShuffleMask(RMask, NumElts);
24693 // At this point LHS and RHS are equivalent to
24694 // LHS = VECTOR_SHUFFLE A, B, LMask
24695 // RHS = VECTOR_SHUFFLE A, B, RMask
24696 // Check that the masks correspond to performing a horizontal operation.
24697 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
24698 for (unsigned i = 0; i != NumLaneElts; ++i) {
24699 int LIdx = LMask[i+l], RIdx = RMask[i+l];
24701 // Ignore any UNDEF components.
24702 if (LIdx < 0 || RIdx < 0 ||
24703 (!A.getNode() && (LIdx < (int)NumElts || RIdx < (int)NumElts)) ||
24704 (!B.getNode() && (LIdx >= (int)NumElts || RIdx >= (int)NumElts)))
24707 // Check that successive elements are being operated on. If not, this is
24708 // not a horizontal operation.
24709 unsigned Src = (i/HalfLaneElts); // each lane is split between srcs
24710 int Index = 2*(i%HalfLaneElts) + NumElts*Src + l;
24711 if (!(LIdx == Index && RIdx == Index + 1) &&
24712 !(IsCommutative && LIdx == Index + 1 && RIdx == Index))
24717 LHS = A.getNode() ? A : B; // If A is 'UNDEF', use B for it.
24718 RHS = B.getNode() ? B : A; // If B is 'UNDEF', use A for it.
24722 /// PerformFADDCombine - Do target-specific dag combines on floating point adds.
24723 static SDValue PerformFADDCombine(SDNode *N, SelectionDAG &DAG,
24724 const X86Subtarget *Subtarget) {
24725 EVT VT = N->getValueType(0);
24726 SDValue LHS = N->getOperand(0);
24727 SDValue RHS = N->getOperand(1);
24729 // Try to synthesize horizontal adds from adds of shuffles.
24730 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
24731 (Subtarget->hasFp256() && (VT == MVT::v8f32 || VT == MVT::v4f64))) &&
24732 isHorizontalBinOp(LHS, RHS, true))
24733 return DAG.getNode(X86ISD::FHADD, SDLoc(N), VT, LHS, RHS);
24737 /// PerformFSUBCombine - Do target-specific dag combines on floating point subs.
24738 static SDValue PerformFSUBCombine(SDNode *N, SelectionDAG &DAG,
24739 const X86Subtarget *Subtarget) {
24740 EVT VT = N->getValueType(0);
24741 SDValue LHS = N->getOperand(0);
24742 SDValue RHS = N->getOperand(1);
24744 // Try to synthesize horizontal subs from subs of shuffles.
24745 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
24746 (Subtarget->hasFp256() && (VT == MVT::v8f32 || VT == MVT::v4f64))) &&
24747 isHorizontalBinOp(LHS, RHS, false))
24748 return DAG.getNode(X86ISD::FHSUB, SDLoc(N), VT, LHS, RHS);
24752 /// PerformFORCombine - Do target-specific dag combines on X86ISD::FOR and
24753 /// X86ISD::FXOR nodes.
24754 static SDValue PerformFORCombine(SDNode *N, SelectionDAG &DAG) {
24755 assert(N->getOpcode() == X86ISD::FOR || N->getOpcode() == X86ISD::FXOR);
24756 // F[X]OR(0.0, x) -> x
24757 // F[X]OR(x, 0.0) -> x
24758 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
24759 if (C->getValueAPF().isPosZero())
24760 return N->getOperand(1);
24761 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
24762 if (C->getValueAPF().isPosZero())
24763 return N->getOperand(0);
24767 /// PerformFMinFMaxCombine - Do target-specific dag combines on X86ISD::FMIN and
24768 /// X86ISD::FMAX nodes.
24769 static SDValue PerformFMinFMaxCombine(SDNode *N, SelectionDAG &DAG) {
24770 assert(N->getOpcode() == X86ISD::FMIN || N->getOpcode() == X86ISD::FMAX);
24772 // Only perform optimizations if UnsafeMath is used.
24773 if (!DAG.getTarget().Options.UnsafeFPMath)
24776 // If we run in unsafe-math mode, then convert the FMAX and FMIN nodes
24777 // into FMINC and FMAXC, which are Commutative operations.
24778 unsigned NewOp = 0;
24779 switch (N->getOpcode()) {
24780 default: llvm_unreachable("unknown opcode");
24781 case X86ISD::FMIN: NewOp = X86ISD::FMINC; break;
24782 case X86ISD::FMAX: NewOp = X86ISD::FMAXC; break;
24785 return DAG.getNode(NewOp, SDLoc(N), N->getValueType(0),
24786 N->getOperand(0), N->getOperand(1));
24789 /// PerformFANDCombine - Do target-specific dag combines on X86ISD::FAND nodes.
24790 static SDValue PerformFANDCombine(SDNode *N, SelectionDAG &DAG) {
24791 // FAND(0.0, x) -> 0.0
24792 // FAND(x, 0.0) -> 0.0
24793 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
24794 if (C->getValueAPF().isPosZero())
24795 return N->getOperand(0);
24796 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
24797 if (C->getValueAPF().isPosZero())
24798 return N->getOperand(1);
24802 /// PerformFANDNCombine - Do target-specific dag combines on X86ISD::FANDN nodes
24803 static SDValue PerformFANDNCombine(SDNode *N, SelectionDAG &DAG) {
24804 // FANDN(x, 0.0) -> 0.0
24805 // FANDN(0.0, x) -> x
24806 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
24807 if (C->getValueAPF().isPosZero())
24808 return N->getOperand(1);
24809 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
24810 if (C->getValueAPF().isPosZero())
24811 return N->getOperand(1);
24815 static SDValue PerformBTCombine(SDNode *N,
24817 TargetLowering::DAGCombinerInfo &DCI) {
24818 // BT ignores high bits in the bit index operand.
24819 SDValue Op1 = N->getOperand(1);
24820 if (Op1.hasOneUse()) {
24821 unsigned BitWidth = Op1.getValueSizeInBits();
24822 APInt DemandedMask = APInt::getLowBitsSet(BitWidth, Log2_32(BitWidth));
24823 APInt KnownZero, KnownOne;
24824 TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(),
24825 !DCI.isBeforeLegalizeOps());
24826 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
24827 if (TLO.ShrinkDemandedConstant(Op1, DemandedMask) ||
24828 TLI.SimplifyDemandedBits(Op1, DemandedMask, KnownZero, KnownOne, TLO))
24829 DCI.CommitTargetLoweringOpt(TLO);
24834 static SDValue PerformVZEXT_MOVLCombine(SDNode *N, SelectionDAG &DAG) {
24835 SDValue Op = N->getOperand(0);
24836 if (Op.getOpcode() == ISD::BITCAST)
24837 Op = Op.getOperand(0);
24838 EVT VT = N->getValueType(0), OpVT = Op.getValueType();
24839 if (Op.getOpcode() == X86ISD::VZEXT_LOAD &&
24840 VT.getVectorElementType().getSizeInBits() ==
24841 OpVT.getVectorElementType().getSizeInBits()) {
24842 return DAG.getNode(ISD::BITCAST, SDLoc(N), VT, Op);
24847 static SDValue PerformSIGN_EXTEND_INREGCombine(SDNode *N, SelectionDAG &DAG,
24848 const X86Subtarget *Subtarget) {
24849 EVT VT = N->getValueType(0);
24850 if (!VT.isVector())
24853 SDValue N0 = N->getOperand(0);
24854 SDValue N1 = N->getOperand(1);
24855 EVT ExtraVT = cast<VTSDNode>(N1)->getVT();
24858 // The SIGN_EXTEND_INREG to v4i64 is expensive operation on the
24859 // both SSE and AVX2 since there is no sign-extended shift right
24860 // operation on a vector with 64-bit elements.
24861 //(sext_in_reg (v4i64 anyext (v4i32 x )), ExtraVT) ->
24862 // (v4i64 sext (v4i32 sext_in_reg (v4i32 x , ExtraVT)))
24863 if (VT == MVT::v4i64 && (N0.getOpcode() == ISD::ANY_EXTEND ||
24864 N0.getOpcode() == ISD::SIGN_EXTEND)) {
24865 SDValue N00 = N0.getOperand(0);
24867 // EXTLOAD has a better solution on AVX2,
24868 // it may be replaced with X86ISD::VSEXT node.
24869 if (N00.getOpcode() == ISD::LOAD && Subtarget->hasInt256())
24870 if (!ISD::isNormalLoad(N00.getNode()))
24873 if (N00.getValueType() == MVT::v4i32 && ExtraVT.getSizeInBits() < 128) {
24874 SDValue Tmp = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, MVT::v4i32,
24876 return DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v4i64, Tmp);
24882 static SDValue PerformSExtCombine(SDNode *N, SelectionDAG &DAG,
24883 TargetLowering::DAGCombinerInfo &DCI,
24884 const X86Subtarget *Subtarget) {
24885 SDValue N0 = N->getOperand(0);
24886 EVT VT = N->getValueType(0);
24888 // (i8,i32 sext (sdivrem (i8 x, i8 y)) ->
24889 // (i8,i32 (sdivrem_sext_hreg (i8 x, i8 y)
24890 // This exposes the sext to the sdivrem lowering, so that it directly extends
24891 // from AH (which we otherwise need to do contortions to access).
24892 if (N0.getOpcode() == ISD::SDIVREM && N0.getResNo() == 1 &&
24893 N0.getValueType() == MVT::i8 && VT == MVT::i32) {
24895 SDVTList NodeTys = DAG.getVTList(MVT::i8, VT);
24896 SDValue R = DAG.getNode(X86ISD::SDIVREM8_SEXT_HREG, dl, NodeTys,
24897 N0.getOperand(0), N0.getOperand(1));
24898 DAG.ReplaceAllUsesOfValueWith(N0.getValue(0), R.getValue(0));
24899 return R.getValue(1);
24902 if (!DCI.isBeforeLegalizeOps())
24905 if (!Subtarget->hasFp256())
24908 if (VT.isVector() && VT.getSizeInBits() == 256) {
24909 SDValue R = WidenMaskArithmetic(N, DAG, DCI, Subtarget);
24917 static SDValue PerformFMACombine(SDNode *N, SelectionDAG &DAG,
24918 const X86Subtarget* Subtarget) {
24920 EVT VT = N->getValueType(0);
24922 // Let legalize expand this if it isn't a legal type yet.
24923 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
24926 EVT ScalarVT = VT.getScalarType();
24927 if ((ScalarVT != MVT::f32 && ScalarVT != MVT::f64) ||
24928 (!Subtarget->hasFMA() && !Subtarget->hasFMA4()))
24931 SDValue A = N->getOperand(0);
24932 SDValue B = N->getOperand(1);
24933 SDValue C = N->getOperand(2);
24935 bool NegA = (A.getOpcode() == ISD::FNEG);
24936 bool NegB = (B.getOpcode() == ISD::FNEG);
24937 bool NegC = (C.getOpcode() == ISD::FNEG);
24939 // Negative multiplication when NegA xor NegB
24940 bool NegMul = (NegA != NegB);
24942 A = A.getOperand(0);
24944 B = B.getOperand(0);
24946 C = C.getOperand(0);
24950 Opcode = (!NegC) ? X86ISD::FMADD : X86ISD::FMSUB;
24952 Opcode = (!NegC) ? X86ISD::FNMADD : X86ISD::FNMSUB;
24954 return DAG.getNode(Opcode, dl, VT, A, B, C);
24957 static SDValue PerformZExtCombine(SDNode *N, SelectionDAG &DAG,
24958 TargetLowering::DAGCombinerInfo &DCI,
24959 const X86Subtarget *Subtarget) {
24960 // (i32 zext (and (i8 x86isd::setcc_carry), 1)) ->
24961 // (and (i32 x86isd::setcc_carry), 1)
24962 // This eliminates the zext. This transformation is necessary because
24963 // ISD::SETCC is always legalized to i8.
24965 SDValue N0 = N->getOperand(0);
24966 EVT VT = N->getValueType(0);
24968 if (N0.getOpcode() == ISD::AND &&
24970 N0.getOperand(0).hasOneUse()) {
24971 SDValue N00 = N0.getOperand(0);
24972 if (N00.getOpcode() == X86ISD::SETCC_CARRY) {
24973 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
24974 if (!C || C->getZExtValue() != 1)
24976 return DAG.getNode(ISD::AND, dl, VT,
24977 DAG.getNode(X86ISD::SETCC_CARRY, dl, VT,
24978 N00.getOperand(0), N00.getOperand(1)),
24979 DAG.getConstant(1, VT));
24983 if (N0.getOpcode() == ISD::TRUNCATE &&
24985 N0.getOperand(0).hasOneUse()) {
24986 SDValue N00 = N0.getOperand(0);
24987 if (N00.getOpcode() == X86ISD::SETCC_CARRY) {
24988 return DAG.getNode(ISD::AND, dl, VT,
24989 DAG.getNode(X86ISD::SETCC_CARRY, dl, VT,
24990 N00.getOperand(0), N00.getOperand(1)),
24991 DAG.getConstant(1, VT));
24994 if (VT.is256BitVector()) {
24995 SDValue R = WidenMaskArithmetic(N, DAG, DCI, Subtarget);
25000 // (i8,i32 zext (udivrem (i8 x, i8 y)) ->
25001 // (i8,i32 (udivrem_zext_hreg (i8 x, i8 y)
25002 // This exposes the zext to the udivrem lowering, so that it directly extends
25003 // from AH (which we otherwise need to do contortions to access).
25004 if (N0.getOpcode() == ISD::UDIVREM &&
25005 N0.getResNo() == 1 && N0.getValueType() == MVT::i8 &&
25006 (VT == MVT::i32 || VT == MVT::i64)) {
25007 SDVTList NodeTys = DAG.getVTList(MVT::i8, VT);
25008 SDValue R = DAG.getNode(X86ISD::UDIVREM8_ZEXT_HREG, dl, NodeTys,
25009 N0.getOperand(0), N0.getOperand(1));
25010 DAG.ReplaceAllUsesOfValueWith(N0.getValue(0), R.getValue(0));
25011 return R.getValue(1);
25017 // Optimize x == -y --> x+y == 0
25018 // x != -y --> x+y != 0
25019 static SDValue PerformISDSETCCCombine(SDNode *N, SelectionDAG &DAG,
25020 const X86Subtarget* Subtarget) {
25021 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(2))->get();
25022 SDValue LHS = N->getOperand(0);
25023 SDValue RHS = N->getOperand(1);
25024 EVT VT = N->getValueType(0);
25027 if ((CC == ISD::SETNE || CC == ISD::SETEQ) && LHS.getOpcode() == ISD::SUB)
25028 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(LHS.getOperand(0)))
25029 if (C->getAPIntValue() == 0 && LHS.hasOneUse()) {
25030 SDValue addV = DAG.getNode(ISD::ADD, SDLoc(N),
25031 LHS.getValueType(), RHS, LHS.getOperand(1));
25032 return DAG.getSetCC(SDLoc(N), N->getValueType(0),
25033 addV, DAG.getConstant(0, addV.getValueType()), CC);
25035 if ((CC == ISD::SETNE || CC == ISD::SETEQ) && RHS.getOpcode() == ISD::SUB)
25036 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS.getOperand(0)))
25037 if (C->getAPIntValue() == 0 && RHS.hasOneUse()) {
25038 SDValue addV = DAG.getNode(ISD::ADD, SDLoc(N),
25039 RHS.getValueType(), LHS, RHS.getOperand(1));
25040 return DAG.getSetCC(SDLoc(N), N->getValueType(0),
25041 addV, DAG.getConstant(0, addV.getValueType()), CC);
25044 if (VT.getScalarType() == MVT::i1) {
25045 bool IsSEXT0 = (LHS.getOpcode() == ISD::SIGN_EXTEND) &&
25046 (LHS.getOperand(0).getValueType().getScalarType() == MVT::i1);
25047 bool IsVZero0 = ISD::isBuildVectorAllZeros(LHS.getNode());
25048 if (!IsSEXT0 && !IsVZero0)
25050 bool IsSEXT1 = (RHS.getOpcode() == ISD::SIGN_EXTEND) &&
25051 (RHS.getOperand(0).getValueType().getScalarType() == MVT::i1);
25052 bool IsVZero1 = ISD::isBuildVectorAllZeros(RHS.getNode());
25054 if (!IsSEXT1 && !IsVZero1)
25057 if (IsSEXT0 && IsVZero1) {
25058 assert(VT == LHS.getOperand(0).getValueType() && "Uexpected operand type");
25059 if (CC == ISD::SETEQ)
25060 return DAG.getNOT(DL, LHS.getOperand(0), VT);
25061 return LHS.getOperand(0);
25063 if (IsSEXT1 && IsVZero0) {
25064 assert(VT == RHS.getOperand(0).getValueType() && "Uexpected operand type");
25065 if (CC == ISD::SETEQ)
25066 return DAG.getNOT(DL, RHS.getOperand(0), VT);
25067 return RHS.getOperand(0);
25074 static SDValue PerformINSERTPSCombine(SDNode *N, SelectionDAG &DAG,
25075 const X86Subtarget *Subtarget) {
25077 MVT VT = N->getOperand(1)->getSimpleValueType(0);
25078 assert((VT == MVT::v4f32 || VT == MVT::v4i32) &&
25079 "X86insertps is only defined for v4x32");
25081 SDValue Ld = N->getOperand(1);
25082 if (MayFoldLoad(Ld)) {
25083 // Extract the countS bits from the immediate so we can get the proper
25084 // address when narrowing the vector load to a specific element.
25085 // When the second source op is a memory address, interps doesn't use
25086 // countS and just gets an f32 from that address.
25087 unsigned DestIndex =
25088 cast<ConstantSDNode>(N->getOperand(2))->getZExtValue() >> 6;
25089 Ld = NarrowVectorLoadToElement(cast<LoadSDNode>(Ld), DestIndex, DAG);
25093 // Create this as a scalar to vector to match the instruction pattern.
25094 SDValue LoadScalarToVector = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Ld);
25095 // countS bits are ignored when loading from memory on insertps, which
25096 // means we don't need to explicitly set them to 0.
25097 return DAG.getNode(X86ISD::INSERTPS, dl, VT, N->getOperand(0),
25098 LoadScalarToVector, N->getOperand(2));
25101 // Helper function of PerformSETCCCombine. It is to materialize "setb reg"
25102 // as "sbb reg,reg", since it can be extended without zext and produces
25103 // an all-ones bit which is more useful than 0/1 in some cases.
25104 static SDValue MaterializeSETB(SDLoc DL, SDValue EFLAGS, SelectionDAG &DAG,
25107 return DAG.getNode(ISD::AND, DL, VT,
25108 DAG.getNode(X86ISD::SETCC_CARRY, DL, MVT::i8,
25109 DAG.getConstant(X86::COND_B, MVT::i8), EFLAGS),
25110 DAG.getConstant(1, VT));
25111 assert (VT == MVT::i1 && "Unexpected type for SECCC node");
25112 return DAG.getNode(ISD::TRUNCATE, DL, MVT::i1,
25113 DAG.getNode(X86ISD::SETCC_CARRY, DL, MVT::i8,
25114 DAG.getConstant(X86::COND_B, MVT::i8), EFLAGS));
25117 // Optimize RES = X86ISD::SETCC CONDCODE, EFLAG_INPUT
25118 static SDValue PerformSETCCCombine(SDNode *N, SelectionDAG &DAG,
25119 TargetLowering::DAGCombinerInfo &DCI,
25120 const X86Subtarget *Subtarget) {
25122 X86::CondCode CC = X86::CondCode(N->getConstantOperandVal(0));
25123 SDValue EFLAGS = N->getOperand(1);
25125 if (CC == X86::COND_A) {
25126 // Try to convert COND_A into COND_B in an attempt to facilitate
25127 // materializing "setb reg".
25129 // Do not flip "e > c", where "c" is a constant, because Cmp instruction
25130 // cannot take an immediate as its first operand.
25132 if (EFLAGS.getOpcode() == X86ISD::SUB && EFLAGS.hasOneUse() &&
25133 EFLAGS.getValueType().isInteger() &&
25134 !isa<ConstantSDNode>(EFLAGS.getOperand(1))) {
25135 SDValue NewSub = DAG.getNode(X86ISD::SUB, SDLoc(EFLAGS),
25136 EFLAGS.getNode()->getVTList(),
25137 EFLAGS.getOperand(1), EFLAGS.getOperand(0));
25138 SDValue NewEFLAGS = SDValue(NewSub.getNode(), EFLAGS.getResNo());
25139 return MaterializeSETB(DL, NewEFLAGS, DAG, N->getSimpleValueType(0));
25143 // Materialize "setb reg" as "sbb reg,reg", since it can be extended without
25144 // a zext and produces an all-ones bit which is more useful than 0/1 in some
25146 if (CC == X86::COND_B)
25147 return MaterializeSETB(DL, EFLAGS, DAG, N->getSimpleValueType(0));
25151 Flags = checkBoolTestSetCCCombine(EFLAGS, CC);
25152 if (Flags.getNode()) {
25153 SDValue Cond = DAG.getConstant(CC, MVT::i8);
25154 return DAG.getNode(X86ISD::SETCC, DL, N->getVTList(), Cond, Flags);
25160 // Optimize branch condition evaluation.
25162 static SDValue PerformBrCondCombine(SDNode *N, SelectionDAG &DAG,
25163 TargetLowering::DAGCombinerInfo &DCI,
25164 const X86Subtarget *Subtarget) {
25166 SDValue Chain = N->getOperand(0);
25167 SDValue Dest = N->getOperand(1);
25168 SDValue EFLAGS = N->getOperand(3);
25169 X86::CondCode CC = X86::CondCode(N->getConstantOperandVal(2));
25173 Flags = checkBoolTestSetCCCombine(EFLAGS, CC);
25174 if (Flags.getNode()) {
25175 SDValue Cond = DAG.getConstant(CC, MVT::i8);
25176 return DAG.getNode(X86ISD::BRCOND, DL, N->getVTList(), Chain, Dest, Cond,
25183 static SDValue performVectorCompareAndMaskUnaryOpCombine(SDNode *N,
25184 SelectionDAG &DAG) {
25185 // Take advantage of vector comparisons producing 0 or -1 in each lane to
25186 // optimize away operation when it's from a constant.
25188 // The general transformation is:
25189 // UNARYOP(AND(VECTOR_CMP(x,y), constant)) -->
25190 // AND(VECTOR_CMP(x,y), constant2)
25191 // constant2 = UNARYOP(constant)
25193 // Early exit if this isn't a vector operation, the operand of the
25194 // unary operation isn't a bitwise AND, or if the sizes of the operations
25195 // aren't the same.
25196 EVT VT = N->getValueType(0);
25197 if (!VT.isVector() || N->getOperand(0)->getOpcode() != ISD::AND ||
25198 N->getOperand(0)->getOperand(0)->getOpcode() != ISD::SETCC ||
25199 VT.getSizeInBits() != N->getOperand(0)->getValueType(0).getSizeInBits())
25202 // Now check that the other operand of the AND is a constant. We could
25203 // make the transformation for non-constant splats as well, but it's unclear
25204 // that would be a benefit as it would not eliminate any operations, just
25205 // perform one more step in scalar code before moving to the vector unit.
25206 if (BuildVectorSDNode *BV =
25207 dyn_cast<BuildVectorSDNode>(N->getOperand(0)->getOperand(1))) {
25208 // Bail out if the vector isn't a constant.
25209 if (!BV->isConstant())
25212 // Everything checks out. Build up the new and improved node.
25214 EVT IntVT = BV->getValueType(0);
25215 // Create a new constant of the appropriate type for the transformed
25217 SDValue SourceConst = DAG.getNode(N->getOpcode(), DL, VT, SDValue(BV, 0));
25218 // The AND node needs bitcasts to/from an integer vector type around it.
25219 SDValue MaskConst = DAG.getNode(ISD::BITCAST, DL, IntVT, SourceConst);
25220 SDValue NewAnd = DAG.getNode(ISD::AND, DL, IntVT,
25221 N->getOperand(0)->getOperand(0), MaskConst);
25222 SDValue Res = DAG.getNode(ISD::BITCAST, DL, VT, NewAnd);
25229 static SDValue PerformSINT_TO_FPCombine(SDNode *N, SelectionDAG &DAG,
25230 const X86TargetLowering *XTLI) {
25231 // First try to optimize away the conversion entirely when it's
25232 // conditionally from a constant. Vectors only.
25233 SDValue Res = performVectorCompareAndMaskUnaryOpCombine(N, DAG);
25234 if (Res != SDValue())
25237 // Now move on to more general possibilities.
25238 SDValue Op0 = N->getOperand(0);
25239 EVT InVT = Op0->getValueType(0);
25241 // SINT_TO_FP(v4i8) -> SINT_TO_FP(SEXT(v4i8 to v4i32))
25242 if (InVT == MVT::v8i8 || InVT == MVT::v4i8) {
25244 MVT DstVT = InVT == MVT::v4i8 ? MVT::v4i32 : MVT::v8i32;
25245 SDValue P = DAG.getNode(ISD::SIGN_EXTEND, dl, DstVT, Op0);
25246 return DAG.getNode(ISD::SINT_TO_FP, dl, N->getValueType(0), P);
25249 // Transform (SINT_TO_FP (i64 ...)) into an x87 operation if we have
25250 // a 32-bit target where SSE doesn't support i64->FP operations.
25251 if (Op0.getOpcode() == ISD::LOAD) {
25252 LoadSDNode *Ld = cast<LoadSDNode>(Op0.getNode());
25253 EVT VT = Ld->getValueType(0);
25254 if (!Ld->isVolatile() && !N->getValueType(0).isVector() &&
25255 ISD::isNON_EXTLoad(Op0.getNode()) && Op0.hasOneUse() &&
25256 !XTLI->getSubtarget()->is64Bit() &&
25258 SDValue FILDChain = XTLI->BuildFILD(SDValue(N, 0), Ld->getValueType(0),
25259 Ld->getChain(), Op0, DAG);
25260 DAG.ReplaceAllUsesOfValueWith(Op0.getValue(1), FILDChain.getValue(1));
25267 // Optimize RES, EFLAGS = X86ISD::ADC LHS, RHS, EFLAGS
25268 static SDValue PerformADCCombine(SDNode *N, SelectionDAG &DAG,
25269 X86TargetLowering::DAGCombinerInfo &DCI) {
25270 // If the LHS and RHS of the ADC node are zero, then it can't overflow and
25271 // the result is either zero or one (depending on the input carry bit).
25272 // Strength reduce this down to a "set on carry" aka SETCC_CARRY&1.
25273 if (X86::isZeroNode(N->getOperand(0)) &&
25274 X86::isZeroNode(N->getOperand(1)) &&
25275 // We don't have a good way to replace an EFLAGS use, so only do this when
25277 SDValue(N, 1).use_empty()) {
25279 EVT VT = N->getValueType(0);
25280 SDValue CarryOut = DAG.getConstant(0, N->getValueType(1));
25281 SDValue Res1 = DAG.getNode(ISD::AND, DL, VT,
25282 DAG.getNode(X86ISD::SETCC_CARRY, DL, VT,
25283 DAG.getConstant(X86::COND_B,MVT::i8),
25285 DAG.getConstant(1, VT));
25286 return DCI.CombineTo(N, Res1, CarryOut);
25292 // fold (add Y, (sete X, 0)) -> adc 0, Y
25293 // (add Y, (setne X, 0)) -> sbb -1, Y
25294 // (sub (sete X, 0), Y) -> sbb 0, Y
25295 // (sub (setne X, 0), Y) -> adc -1, Y
25296 static SDValue OptimizeConditionalInDecrement(SDNode *N, SelectionDAG &DAG) {
25299 // Look through ZExts.
25300 SDValue Ext = N->getOperand(N->getOpcode() == ISD::SUB ? 1 : 0);
25301 if (Ext.getOpcode() != ISD::ZERO_EXTEND || !Ext.hasOneUse())
25304 SDValue SetCC = Ext.getOperand(0);
25305 if (SetCC.getOpcode() != X86ISD::SETCC || !SetCC.hasOneUse())
25308 X86::CondCode CC = (X86::CondCode)SetCC.getConstantOperandVal(0);
25309 if (CC != X86::COND_E && CC != X86::COND_NE)
25312 SDValue Cmp = SetCC.getOperand(1);
25313 if (Cmp.getOpcode() != X86ISD::CMP || !Cmp.hasOneUse() ||
25314 !X86::isZeroNode(Cmp.getOperand(1)) ||
25315 !Cmp.getOperand(0).getValueType().isInteger())
25318 SDValue CmpOp0 = Cmp.getOperand(0);
25319 SDValue NewCmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32, CmpOp0,
25320 DAG.getConstant(1, CmpOp0.getValueType()));
25322 SDValue OtherVal = N->getOperand(N->getOpcode() == ISD::SUB ? 0 : 1);
25323 if (CC == X86::COND_NE)
25324 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::ADC : X86ISD::SBB,
25325 DL, OtherVal.getValueType(), OtherVal,
25326 DAG.getConstant(-1ULL, OtherVal.getValueType()), NewCmp);
25327 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::SBB : X86ISD::ADC,
25328 DL, OtherVal.getValueType(), OtherVal,
25329 DAG.getConstant(0, OtherVal.getValueType()), NewCmp);
25332 /// PerformADDCombine - Do target-specific dag combines on integer adds.
25333 static SDValue PerformAddCombine(SDNode *N, SelectionDAG &DAG,
25334 const X86Subtarget *Subtarget) {
25335 EVT VT = N->getValueType(0);
25336 SDValue Op0 = N->getOperand(0);
25337 SDValue Op1 = N->getOperand(1);
25339 // Try to synthesize horizontal adds from adds of shuffles.
25340 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) ||
25341 (Subtarget->hasInt256() && (VT == MVT::v16i16 || VT == MVT::v8i32))) &&
25342 isHorizontalBinOp(Op0, Op1, true))
25343 return DAG.getNode(X86ISD::HADD, SDLoc(N), VT, Op0, Op1);
25345 return OptimizeConditionalInDecrement(N, DAG);
25348 static SDValue PerformSubCombine(SDNode *N, SelectionDAG &DAG,
25349 const X86Subtarget *Subtarget) {
25350 SDValue Op0 = N->getOperand(0);
25351 SDValue Op1 = N->getOperand(1);
25353 // X86 can't encode an immediate LHS of a sub. See if we can push the
25354 // negation into a preceding instruction.
25355 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op0)) {
25356 // If the RHS of the sub is a XOR with one use and a constant, invert the
25357 // immediate. Then add one to the LHS of the sub so we can turn
25358 // X-Y -> X+~Y+1, saving one register.
25359 if (Op1->hasOneUse() && Op1.getOpcode() == ISD::XOR &&
25360 isa<ConstantSDNode>(Op1.getOperand(1))) {
25361 APInt XorC = cast<ConstantSDNode>(Op1.getOperand(1))->getAPIntValue();
25362 EVT VT = Op0.getValueType();
25363 SDValue NewXor = DAG.getNode(ISD::XOR, SDLoc(Op1), VT,
25365 DAG.getConstant(~XorC, VT));
25366 return DAG.getNode(ISD::ADD, SDLoc(N), VT, NewXor,
25367 DAG.getConstant(C->getAPIntValue()+1, VT));
25371 // Try to synthesize horizontal adds from adds of shuffles.
25372 EVT VT = N->getValueType(0);
25373 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) ||
25374 (Subtarget->hasInt256() && (VT == MVT::v16i16 || VT == MVT::v8i32))) &&
25375 isHorizontalBinOp(Op0, Op1, true))
25376 return DAG.getNode(X86ISD::HSUB, SDLoc(N), VT, Op0, Op1);
25378 return OptimizeConditionalInDecrement(N, DAG);
25381 /// performVZEXTCombine - Performs build vector combines
25382 static SDValue performVZEXTCombine(SDNode *N, SelectionDAG &DAG,
25383 TargetLowering::DAGCombinerInfo &DCI,
25384 const X86Subtarget *Subtarget) {
25386 MVT VT = N->getSimpleValueType(0);
25387 SDValue Op = N->getOperand(0);
25388 MVT OpVT = Op.getSimpleValueType();
25389 MVT OpEltVT = OpVT.getVectorElementType();
25390 unsigned InputBits = OpEltVT.getSizeInBits() * VT.getVectorNumElements();
25392 // (vzext (bitcast (vzext (x)) -> (vzext x)
25394 while (V.getOpcode() == ISD::BITCAST)
25395 V = V.getOperand(0);
25397 if (V != Op && V.getOpcode() == X86ISD::VZEXT) {
25398 MVT InnerVT = V.getSimpleValueType();
25399 MVT InnerEltVT = InnerVT.getVectorElementType();
25401 // If the element sizes match exactly, we can just do one larger vzext. This
25402 // is always an exact type match as vzext operates on integer types.
25403 if (OpEltVT == InnerEltVT) {
25404 assert(OpVT == InnerVT && "Types must match for vzext!");
25405 return DAG.getNode(X86ISD::VZEXT, DL, VT, V.getOperand(0));
25408 // The only other way we can combine them is if only a single element of the
25409 // inner vzext is used in the input to the outer vzext.
25410 if (InnerEltVT.getSizeInBits() < InputBits)
25413 // In this case, the inner vzext is completely dead because we're going to
25414 // only look at bits inside of the low element. Just do the outer vzext on
25415 // a bitcast of the input to the inner.
25416 return DAG.getNode(X86ISD::VZEXT, DL, VT,
25417 DAG.getNode(ISD::BITCAST, DL, OpVT, V));
25420 // Check if we can bypass extracting and re-inserting an element of an input
25421 // vector. Essentialy:
25422 // (bitcast (sclr2vec (ext_vec_elt x))) -> (bitcast x)
25423 if (V.getOpcode() == ISD::SCALAR_TO_VECTOR &&
25424 V.getOperand(0).getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
25425 V.getOperand(0).getSimpleValueType().getSizeInBits() == InputBits) {
25426 SDValue ExtractedV = V.getOperand(0);
25427 SDValue OrigV = ExtractedV.getOperand(0);
25428 if (auto *ExtractIdx = dyn_cast<ConstantSDNode>(ExtractedV.getOperand(1)))
25429 if (ExtractIdx->getZExtValue() == 0) {
25430 MVT OrigVT = OrigV.getSimpleValueType();
25431 // Extract a subvector if necessary...
25432 if (OrigVT.getSizeInBits() > OpVT.getSizeInBits()) {
25433 int Ratio = OrigVT.getSizeInBits() / OpVT.getSizeInBits();
25434 OrigVT = MVT::getVectorVT(OrigVT.getVectorElementType(),
25435 OrigVT.getVectorNumElements() / Ratio);
25436 OrigV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, OrigVT, OrigV,
25437 DAG.getIntPtrConstant(0));
25439 Op = DAG.getNode(ISD::BITCAST, DL, OpVT, OrigV);
25440 return DAG.getNode(X86ISD::VZEXT, DL, VT, Op);
25447 SDValue X86TargetLowering::PerformDAGCombine(SDNode *N,
25448 DAGCombinerInfo &DCI) const {
25449 SelectionDAG &DAG = DCI.DAG;
25450 switch (N->getOpcode()) {
25452 case ISD::EXTRACT_VECTOR_ELT:
25453 return PerformEXTRACT_VECTOR_ELTCombine(N, DAG, DCI);
25456 case X86ISD::SHRUNKBLEND:
25457 return PerformSELECTCombine(N, DAG, DCI, Subtarget);
25458 case X86ISD::CMOV: return PerformCMOVCombine(N, DAG, DCI, Subtarget);
25459 case ISD::ADD: return PerformAddCombine(N, DAG, Subtarget);
25460 case ISD::SUB: return PerformSubCombine(N, DAG, Subtarget);
25461 case X86ISD::ADC: return PerformADCCombine(N, DAG, DCI);
25462 case ISD::MUL: return PerformMulCombine(N, DAG, DCI);
25465 case ISD::SRL: return PerformShiftCombine(N, DAG, DCI, Subtarget);
25466 case ISD::AND: return PerformAndCombine(N, DAG, DCI, Subtarget);
25467 case ISD::OR: return PerformOrCombine(N, DAG, DCI, Subtarget);
25468 case ISD::XOR: return PerformXorCombine(N, DAG, DCI, Subtarget);
25469 case ISD::LOAD: return PerformLOADCombine(N, DAG, DCI, Subtarget);
25470 case ISD::STORE: return PerformSTORECombine(N, DAG, Subtarget);
25471 case ISD::SINT_TO_FP: return PerformSINT_TO_FPCombine(N, DAG, this);
25472 case ISD::FADD: return PerformFADDCombine(N, DAG, Subtarget);
25473 case ISD::FSUB: return PerformFSUBCombine(N, DAG, Subtarget);
25475 case X86ISD::FOR: return PerformFORCombine(N, DAG);
25477 case X86ISD::FMAX: return PerformFMinFMaxCombine(N, DAG);
25478 case X86ISD::FAND: return PerformFANDCombine(N, DAG);
25479 case X86ISD::FANDN: return PerformFANDNCombine(N, DAG);
25480 case X86ISD::BT: return PerformBTCombine(N, DAG, DCI);
25481 case X86ISD::VZEXT_MOVL: return PerformVZEXT_MOVLCombine(N, DAG);
25482 case ISD::ANY_EXTEND:
25483 case ISD::ZERO_EXTEND: return PerformZExtCombine(N, DAG, DCI, Subtarget);
25484 case ISD::SIGN_EXTEND: return PerformSExtCombine(N, DAG, DCI, Subtarget);
25485 case ISD::SIGN_EXTEND_INREG:
25486 return PerformSIGN_EXTEND_INREGCombine(N, DAG, Subtarget);
25487 case ISD::TRUNCATE: return PerformTruncateCombine(N, DAG,DCI,Subtarget);
25488 case ISD::SETCC: return PerformISDSETCCCombine(N, DAG, Subtarget);
25489 case X86ISD::SETCC: return PerformSETCCCombine(N, DAG, DCI, Subtarget);
25490 case X86ISD::BRCOND: return PerformBrCondCombine(N, DAG, DCI, Subtarget);
25491 case X86ISD::VZEXT: return performVZEXTCombine(N, DAG, DCI, Subtarget);
25492 case X86ISD::SHUFP: // Handle all target specific shuffles
25493 case X86ISD::PALIGNR:
25494 case X86ISD::UNPCKH:
25495 case X86ISD::UNPCKL:
25496 case X86ISD::MOVHLPS:
25497 case X86ISD::MOVLHPS:
25498 case X86ISD::PSHUFB:
25499 case X86ISD::PSHUFD:
25500 case X86ISD::PSHUFHW:
25501 case X86ISD::PSHUFLW:
25502 case X86ISD::MOVSS:
25503 case X86ISD::MOVSD:
25504 case X86ISD::VPERMILPI:
25505 case X86ISD::VPERM2X128:
25506 case ISD::VECTOR_SHUFFLE: return PerformShuffleCombine(N, DAG, DCI,Subtarget);
25507 case ISD::FMA: return PerformFMACombine(N, DAG, Subtarget);
25508 case ISD::INTRINSIC_WO_CHAIN:
25509 return PerformINTRINSIC_WO_CHAINCombine(N, DAG, Subtarget);
25510 case X86ISD::INSERTPS:
25511 return PerformINSERTPSCombine(N, DAG, Subtarget);
25512 case ISD::BUILD_VECTOR: return PerformBUILD_VECTORCombine(N, DAG, Subtarget);
25518 /// isTypeDesirableForOp - Return true if the target has native support for
25519 /// the specified value type and it is 'desirable' to use the type for the
25520 /// given node type. e.g. On x86 i16 is legal, but undesirable since i16
25521 /// instruction encodings are longer and some i16 instructions are slow.
25522 bool X86TargetLowering::isTypeDesirableForOp(unsigned Opc, EVT VT) const {
25523 if (!isTypeLegal(VT))
25525 if (VT != MVT::i16)
25532 case ISD::SIGN_EXTEND:
25533 case ISD::ZERO_EXTEND:
25534 case ISD::ANY_EXTEND:
25547 /// IsDesirableToPromoteOp - This method query the target whether it is
25548 /// beneficial for dag combiner to promote the specified node. If true, it
25549 /// should return the desired promotion type by reference.
25550 bool X86TargetLowering::IsDesirableToPromoteOp(SDValue Op, EVT &PVT) const {
25551 EVT VT = Op.getValueType();
25552 if (VT != MVT::i16)
25555 bool Promote = false;
25556 bool Commute = false;
25557 switch (Op.getOpcode()) {
25560 LoadSDNode *LD = cast<LoadSDNode>(Op);
25561 // If the non-extending load has a single use and it's not live out, then it
25562 // might be folded.
25563 if (LD->getExtensionType() == ISD::NON_EXTLOAD /*&&
25564 Op.hasOneUse()*/) {
25565 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
25566 UE = Op.getNode()->use_end(); UI != UE; ++UI) {
25567 // The only case where we'd want to promote LOAD (rather then it being
25568 // promoted as an operand is when it's only use is liveout.
25569 if (UI->getOpcode() != ISD::CopyToReg)
25576 case ISD::SIGN_EXTEND:
25577 case ISD::ZERO_EXTEND:
25578 case ISD::ANY_EXTEND:
25583 SDValue N0 = Op.getOperand(0);
25584 // Look out for (store (shl (load), x)).
25585 if (MayFoldLoad(N0) && MayFoldIntoStore(Op))
25598 SDValue N0 = Op.getOperand(0);
25599 SDValue N1 = Op.getOperand(1);
25600 if (!Commute && MayFoldLoad(N1))
25602 // Avoid disabling potential load folding opportunities.
25603 if (MayFoldLoad(N0) && (!isa<ConstantSDNode>(N1) || MayFoldIntoStore(Op)))
25605 if (MayFoldLoad(N1) && (!isa<ConstantSDNode>(N0) || MayFoldIntoStore(Op)))
25615 //===----------------------------------------------------------------------===//
25616 // X86 Inline Assembly Support
25617 //===----------------------------------------------------------------------===//
25620 // Helper to match a string separated by whitespace.
25621 bool matchAsmImpl(StringRef s, ArrayRef<const StringRef *> args) {
25622 s = s.substr(s.find_first_not_of(" \t")); // Skip leading whitespace.
25624 for (unsigned i = 0, e = args.size(); i != e; ++i) {
25625 StringRef piece(*args[i]);
25626 if (!s.startswith(piece)) // Check if the piece matches.
25629 s = s.substr(piece.size());
25630 StringRef::size_type pos = s.find_first_not_of(" \t");
25631 if (pos == 0) // We matched a prefix.
25639 const VariadicFunction1<bool, StringRef, StringRef, matchAsmImpl> matchAsm={};
25642 static bool clobbersFlagRegisters(const SmallVector<StringRef, 4> &AsmPieces) {
25644 if (AsmPieces.size() == 3 || AsmPieces.size() == 4) {
25645 if (std::count(AsmPieces.begin(), AsmPieces.end(), "~{cc}") &&
25646 std::count(AsmPieces.begin(), AsmPieces.end(), "~{flags}") &&
25647 std::count(AsmPieces.begin(), AsmPieces.end(), "~{fpsr}")) {
25649 if (AsmPieces.size() == 3)
25651 else if (std::count(AsmPieces.begin(), AsmPieces.end(), "~{dirflag}"))
25658 bool X86TargetLowering::ExpandInlineAsm(CallInst *CI) const {
25659 InlineAsm *IA = cast<InlineAsm>(CI->getCalledValue());
25661 std::string AsmStr = IA->getAsmString();
25663 IntegerType *Ty = dyn_cast<IntegerType>(CI->getType());
25664 if (!Ty || Ty->getBitWidth() % 16 != 0)
25667 // TODO: should remove alternatives from the asmstring: "foo {a|b}" -> "foo a"
25668 SmallVector<StringRef, 4> AsmPieces;
25669 SplitString(AsmStr, AsmPieces, ";\n");
25671 switch (AsmPieces.size()) {
25672 default: return false;
25674 // FIXME: this should verify that we are targeting a 486 or better. If not,
25675 // we will turn this bswap into something that will be lowered to logical
25676 // ops instead of emitting the bswap asm. For now, we don't support 486 or
25677 // lower so don't worry about this.
25679 if (matchAsm(AsmPieces[0], "bswap", "$0") ||
25680 matchAsm(AsmPieces[0], "bswapl", "$0") ||
25681 matchAsm(AsmPieces[0], "bswapq", "$0") ||
25682 matchAsm(AsmPieces[0], "bswap", "${0:q}") ||
25683 matchAsm(AsmPieces[0], "bswapl", "${0:q}") ||
25684 matchAsm(AsmPieces[0], "bswapq", "${0:q}")) {
25685 // No need to check constraints, nothing other than the equivalent of
25686 // "=r,0" would be valid here.
25687 return IntrinsicLowering::LowerToByteSwap(CI);
25690 // rorw $$8, ${0:w} --> llvm.bswap.i16
25691 if (CI->getType()->isIntegerTy(16) &&
25692 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 &&
25693 (matchAsm(AsmPieces[0], "rorw", "$$8,", "${0:w}") ||
25694 matchAsm(AsmPieces[0], "rolw", "$$8,", "${0:w}"))) {
25696 const std::string &ConstraintsStr = IA->getConstraintString();
25697 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
25698 array_pod_sort(AsmPieces.begin(), AsmPieces.end());
25699 if (clobbersFlagRegisters(AsmPieces))
25700 return IntrinsicLowering::LowerToByteSwap(CI);
25704 if (CI->getType()->isIntegerTy(32) &&
25705 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 &&
25706 matchAsm(AsmPieces[0], "rorw", "$$8,", "${0:w}") &&
25707 matchAsm(AsmPieces[1], "rorl", "$$16,", "$0") &&
25708 matchAsm(AsmPieces[2], "rorw", "$$8,", "${0:w}")) {
25710 const std::string &ConstraintsStr = IA->getConstraintString();
25711 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
25712 array_pod_sort(AsmPieces.begin(), AsmPieces.end());
25713 if (clobbersFlagRegisters(AsmPieces))
25714 return IntrinsicLowering::LowerToByteSwap(CI);
25717 if (CI->getType()->isIntegerTy(64)) {
25718 InlineAsm::ConstraintInfoVector Constraints = IA->ParseConstraints();
25719 if (Constraints.size() >= 2 &&
25720 Constraints[0].Codes.size() == 1 && Constraints[0].Codes[0] == "A" &&
25721 Constraints[1].Codes.size() == 1 && Constraints[1].Codes[0] == "0") {
25722 // bswap %eax / bswap %edx / xchgl %eax, %edx -> llvm.bswap.i64
25723 if (matchAsm(AsmPieces[0], "bswap", "%eax") &&
25724 matchAsm(AsmPieces[1], "bswap", "%edx") &&
25725 matchAsm(AsmPieces[2], "xchgl", "%eax,", "%edx"))
25726 return IntrinsicLowering::LowerToByteSwap(CI);
25734 /// getConstraintType - Given a constraint letter, return the type of
25735 /// constraint it is for this target.
25736 X86TargetLowering::ConstraintType
25737 X86TargetLowering::getConstraintType(const std::string &Constraint) const {
25738 if (Constraint.size() == 1) {
25739 switch (Constraint[0]) {
25750 return C_RegisterClass;
25774 return TargetLowering::getConstraintType(Constraint);
25777 /// Examine constraint type and operand type and determine a weight value.
25778 /// This object must already have been set up with the operand type
25779 /// and the current alternative constraint selected.
25780 TargetLowering::ConstraintWeight
25781 X86TargetLowering::getSingleConstraintMatchWeight(
25782 AsmOperandInfo &info, const char *constraint) const {
25783 ConstraintWeight weight = CW_Invalid;
25784 Value *CallOperandVal = info.CallOperandVal;
25785 // If we don't have a value, we can't do a match,
25786 // but allow it at the lowest weight.
25787 if (!CallOperandVal)
25789 Type *type = CallOperandVal->getType();
25790 // Look at the constraint type.
25791 switch (*constraint) {
25793 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
25804 if (CallOperandVal->getType()->isIntegerTy())
25805 weight = CW_SpecificReg;
25810 if (type->isFloatingPointTy())
25811 weight = CW_SpecificReg;
25814 if (type->isX86_MMXTy() && Subtarget->hasMMX())
25815 weight = CW_SpecificReg;
25819 if (((type->getPrimitiveSizeInBits() == 128) && Subtarget->hasSSE1()) ||
25820 ((type->getPrimitiveSizeInBits() == 256) && Subtarget->hasFp256()))
25821 weight = CW_Register;
25824 if (ConstantInt *C = dyn_cast<ConstantInt>(info.CallOperandVal)) {
25825 if (C->getZExtValue() <= 31)
25826 weight = CW_Constant;
25830 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
25831 if (C->getZExtValue() <= 63)
25832 weight = CW_Constant;
25836 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
25837 if ((C->getSExtValue() >= -0x80) && (C->getSExtValue() <= 0x7f))
25838 weight = CW_Constant;
25842 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
25843 if ((C->getZExtValue() == 0xff) || (C->getZExtValue() == 0xffff))
25844 weight = CW_Constant;
25848 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
25849 if (C->getZExtValue() <= 3)
25850 weight = CW_Constant;
25854 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
25855 if (C->getZExtValue() <= 0xff)
25856 weight = CW_Constant;
25861 if (dyn_cast<ConstantFP>(CallOperandVal)) {
25862 weight = CW_Constant;
25866 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
25867 if ((C->getSExtValue() >= -0x80000000LL) &&
25868 (C->getSExtValue() <= 0x7fffffffLL))
25869 weight = CW_Constant;
25873 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
25874 if (C->getZExtValue() <= 0xffffffff)
25875 weight = CW_Constant;
25882 /// LowerXConstraint - try to replace an X constraint, which matches anything,
25883 /// with another that has more specific requirements based on the type of the
25884 /// corresponding operand.
25885 const char *X86TargetLowering::
25886 LowerXConstraint(EVT ConstraintVT) const {
25887 // FP X constraints get lowered to SSE1/2 registers if available, otherwise
25888 // 'f' like normal targets.
25889 if (ConstraintVT.isFloatingPoint()) {
25890 if (Subtarget->hasSSE2())
25892 if (Subtarget->hasSSE1())
25896 return TargetLowering::LowerXConstraint(ConstraintVT);
25899 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
25900 /// vector. If it is invalid, don't add anything to Ops.
25901 void X86TargetLowering::LowerAsmOperandForConstraint(SDValue Op,
25902 std::string &Constraint,
25903 std::vector<SDValue>&Ops,
25904 SelectionDAG &DAG) const {
25907 // Only support length 1 constraints for now.
25908 if (Constraint.length() > 1) return;
25910 char ConstraintLetter = Constraint[0];
25911 switch (ConstraintLetter) {
25914 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
25915 if (C->getZExtValue() <= 31) {
25916 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
25922 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
25923 if (C->getZExtValue() <= 63) {
25924 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
25930 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
25931 if (isInt<8>(C->getSExtValue())) {
25932 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
25938 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
25939 if (C->getZExtValue() <= 255) {
25940 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
25946 // 32-bit signed value
25947 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
25948 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
25949 C->getSExtValue())) {
25950 // Widen to 64 bits here to get it sign extended.
25951 Result = DAG.getTargetConstant(C->getSExtValue(), MVT::i64);
25954 // FIXME gcc accepts some relocatable values here too, but only in certain
25955 // memory models; it's complicated.
25960 // 32-bit unsigned value
25961 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
25962 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
25963 C->getZExtValue())) {
25964 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
25968 // FIXME gcc accepts some relocatable values here too, but only in certain
25969 // memory models; it's complicated.
25973 // Literal immediates are always ok.
25974 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op)) {
25975 // Widen to 64 bits here to get it sign extended.
25976 Result = DAG.getTargetConstant(CST->getSExtValue(), MVT::i64);
25980 // In any sort of PIC mode addresses need to be computed at runtime by
25981 // adding in a register or some sort of table lookup. These can't
25982 // be used as immediates.
25983 if (Subtarget->isPICStyleGOT() || Subtarget->isPICStyleStubPIC())
25986 // If we are in non-pic codegen mode, we allow the address of a global (with
25987 // an optional displacement) to be used with 'i'.
25988 GlobalAddressSDNode *GA = nullptr;
25989 int64_t Offset = 0;
25991 // Match either (GA), (GA+C), (GA+C1+C2), etc.
25993 if ((GA = dyn_cast<GlobalAddressSDNode>(Op))) {
25994 Offset += GA->getOffset();
25996 } else if (Op.getOpcode() == ISD::ADD) {
25997 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
25998 Offset += C->getZExtValue();
25999 Op = Op.getOperand(0);
26002 } else if (Op.getOpcode() == ISD::SUB) {
26003 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
26004 Offset += -C->getZExtValue();
26005 Op = Op.getOperand(0);
26010 // Otherwise, this isn't something we can handle, reject it.
26014 const GlobalValue *GV = GA->getGlobal();
26015 // If we require an extra load to get this address, as in PIC mode, we
26016 // can't accept it.
26017 if (isGlobalStubReference(
26018 Subtarget->ClassifyGlobalReference(GV, DAG.getTarget())))
26021 Result = DAG.getTargetGlobalAddress(GV, SDLoc(Op),
26022 GA->getValueType(0), Offset);
26027 if (Result.getNode()) {
26028 Ops.push_back(Result);
26031 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
26034 std::pair<unsigned, const TargetRegisterClass*>
26035 X86TargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
26037 // First, see if this is a constraint that directly corresponds to an LLVM
26039 if (Constraint.size() == 1) {
26040 // GCC Constraint Letters
26041 switch (Constraint[0]) {
26043 // TODO: Slight differences here in allocation order and leaving
26044 // RIP in the class. Do they matter any more here than they do
26045 // in the normal allocation?
26046 case 'q': // GENERAL_REGS in 64-bit mode, Q_REGS in 32-bit mode.
26047 if (Subtarget->is64Bit()) {
26048 if (VT == MVT::i32 || VT == MVT::f32)
26049 return std::make_pair(0U, &X86::GR32RegClass);
26050 if (VT == MVT::i16)
26051 return std::make_pair(0U, &X86::GR16RegClass);
26052 if (VT == MVT::i8 || VT == MVT::i1)
26053 return std::make_pair(0U, &X86::GR8RegClass);
26054 if (VT == MVT::i64 || VT == MVT::f64)
26055 return std::make_pair(0U, &X86::GR64RegClass);
26058 // 32-bit fallthrough
26059 case 'Q': // Q_REGS
26060 if (VT == MVT::i32 || VT == MVT::f32)
26061 return std::make_pair(0U, &X86::GR32_ABCDRegClass);
26062 if (VT == MVT::i16)
26063 return std::make_pair(0U, &X86::GR16_ABCDRegClass);
26064 if (VT == MVT::i8 || VT == MVT::i1)
26065 return std::make_pair(0U, &X86::GR8_ABCD_LRegClass);
26066 if (VT == MVT::i64)
26067 return std::make_pair(0U, &X86::GR64_ABCDRegClass);
26069 case 'r': // GENERAL_REGS
26070 case 'l': // INDEX_REGS
26071 if (VT == MVT::i8 || VT == MVT::i1)
26072 return std::make_pair(0U, &X86::GR8RegClass);
26073 if (VT == MVT::i16)
26074 return std::make_pair(0U, &X86::GR16RegClass);
26075 if (VT == MVT::i32 || VT == MVT::f32 || !Subtarget->is64Bit())
26076 return std::make_pair(0U, &X86::GR32RegClass);
26077 return std::make_pair(0U, &X86::GR64RegClass);
26078 case 'R': // LEGACY_REGS
26079 if (VT == MVT::i8 || VT == MVT::i1)
26080 return std::make_pair(0U, &X86::GR8_NOREXRegClass);
26081 if (VT == MVT::i16)
26082 return std::make_pair(0U, &X86::GR16_NOREXRegClass);
26083 if (VT == MVT::i32 || !Subtarget->is64Bit())
26084 return std::make_pair(0U, &X86::GR32_NOREXRegClass);
26085 return std::make_pair(0U, &X86::GR64_NOREXRegClass);
26086 case 'f': // FP Stack registers.
26087 // If SSE is enabled for this VT, use f80 to ensure the isel moves the
26088 // value to the correct fpstack register class.
26089 if (VT == MVT::f32 && !isScalarFPTypeInSSEReg(VT))
26090 return std::make_pair(0U, &X86::RFP32RegClass);
26091 if (VT == MVT::f64 && !isScalarFPTypeInSSEReg(VT))
26092 return std::make_pair(0U, &X86::RFP64RegClass);
26093 return std::make_pair(0U, &X86::RFP80RegClass);
26094 case 'y': // MMX_REGS if MMX allowed.
26095 if (!Subtarget->hasMMX()) break;
26096 return std::make_pair(0U, &X86::VR64RegClass);
26097 case 'Y': // SSE_REGS if SSE2 allowed
26098 if (!Subtarget->hasSSE2()) break;
26100 case 'x': // SSE_REGS if SSE1 allowed or AVX_REGS if AVX allowed
26101 if (!Subtarget->hasSSE1()) break;
26103 switch (VT.SimpleTy) {
26105 // Scalar SSE types.
26108 return std::make_pair(0U, &X86::FR32RegClass);
26111 return std::make_pair(0U, &X86::FR64RegClass);
26119 return std::make_pair(0U, &X86::VR128RegClass);
26127 return std::make_pair(0U, &X86::VR256RegClass);
26132 return std::make_pair(0U, &X86::VR512RegClass);
26138 // Use the default implementation in TargetLowering to convert the register
26139 // constraint into a member of a register class.
26140 std::pair<unsigned, const TargetRegisterClass*> Res;
26141 Res = TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
26143 // Not found as a standard register?
26145 // Map st(0) -> st(7) -> ST0
26146 if (Constraint.size() == 7 && Constraint[0] == '{' &&
26147 tolower(Constraint[1]) == 's' &&
26148 tolower(Constraint[2]) == 't' &&
26149 Constraint[3] == '(' &&
26150 (Constraint[4] >= '0' && Constraint[4] <= '7') &&
26151 Constraint[5] == ')' &&
26152 Constraint[6] == '}') {
26154 Res.first = X86::FP0+Constraint[4]-'0';
26155 Res.second = &X86::RFP80RegClass;
26159 // GCC allows "st(0)" to be called just plain "st".
26160 if (StringRef("{st}").equals_lower(Constraint)) {
26161 Res.first = X86::FP0;
26162 Res.second = &X86::RFP80RegClass;
26167 if (StringRef("{flags}").equals_lower(Constraint)) {
26168 Res.first = X86::EFLAGS;
26169 Res.second = &X86::CCRRegClass;
26173 // 'A' means EAX + EDX.
26174 if (Constraint == "A") {
26175 Res.first = X86::EAX;
26176 Res.second = &X86::GR32_ADRegClass;
26182 // Otherwise, check to see if this is a register class of the wrong value
26183 // type. For example, we want to map "{ax},i32" -> {eax}, we don't want it to
26184 // turn into {ax},{dx}.
26185 if (Res.second->hasType(VT))
26186 return Res; // Correct type already, nothing to do.
26188 // All of the single-register GCC register classes map their values onto
26189 // 16-bit register pieces "ax","dx","cx","bx","si","di","bp","sp". If we
26190 // really want an 8-bit or 32-bit register, map to the appropriate register
26191 // class and return the appropriate register.
26192 if (Res.second == &X86::GR16RegClass) {
26193 if (VT == MVT::i8 || VT == MVT::i1) {
26194 unsigned DestReg = 0;
26195 switch (Res.first) {
26197 case X86::AX: DestReg = X86::AL; break;
26198 case X86::DX: DestReg = X86::DL; break;
26199 case X86::CX: DestReg = X86::CL; break;
26200 case X86::BX: DestReg = X86::BL; break;
26203 Res.first = DestReg;
26204 Res.second = &X86::GR8RegClass;
26206 } else if (VT == MVT::i32 || VT == MVT::f32) {
26207 unsigned DestReg = 0;
26208 switch (Res.first) {
26210 case X86::AX: DestReg = X86::EAX; break;
26211 case X86::DX: DestReg = X86::EDX; break;
26212 case X86::CX: DestReg = X86::ECX; break;
26213 case X86::BX: DestReg = X86::EBX; break;
26214 case X86::SI: DestReg = X86::ESI; break;
26215 case X86::DI: DestReg = X86::EDI; break;
26216 case X86::BP: DestReg = X86::EBP; break;
26217 case X86::SP: DestReg = X86::ESP; break;
26220 Res.first = DestReg;
26221 Res.second = &X86::GR32RegClass;
26223 } else if (VT == MVT::i64 || VT == MVT::f64) {
26224 unsigned DestReg = 0;
26225 switch (Res.first) {
26227 case X86::AX: DestReg = X86::RAX; break;
26228 case X86::DX: DestReg = X86::RDX; break;
26229 case X86::CX: DestReg = X86::RCX; break;
26230 case X86::BX: DestReg = X86::RBX; break;
26231 case X86::SI: DestReg = X86::RSI; break;
26232 case X86::DI: DestReg = X86::RDI; break;
26233 case X86::BP: DestReg = X86::RBP; break;
26234 case X86::SP: DestReg = X86::RSP; break;
26237 Res.first = DestReg;
26238 Res.second = &X86::GR64RegClass;
26241 } else if (Res.second == &X86::FR32RegClass ||
26242 Res.second == &X86::FR64RegClass ||
26243 Res.second == &X86::VR128RegClass ||
26244 Res.second == &X86::VR256RegClass ||
26245 Res.second == &X86::FR32XRegClass ||
26246 Res.second == &X86::FR64XRegClass ||
26247 Res.second == &X86::VR128XRegClass ||
26248 Res.second == &X86::VR256XRegClass ||
26249 Res.second == &X86::VR512RegClass) {
26250 // Handle references to XMM physical registers that got mapped into the
26251 // wrong class. This can happen with constraints like {xmm0} where the
26252 // target independent register mapper will just pick the first match it can
26253 // find, ignoring the required type.
26255 if (VT == MVT::f32 || VT == MVT::i32)
26256 Res.second = &X86::FR32RegClass;
26257 else if (VT == MVT::f64 || VT == MVT::i64)
26258 Res.second = &X86::FR64RegClass;
26259 else if (X86::VR128RegClass.hasType(VT))
26260 Res.second = &X86::VR128RegClass;
26261 else if (X86::VR256RegClass.hasType(VT))
26262 Res.second = &X86::VR256RegClass;
26263 else if (X86::VR512RegClass.hasType(VT))
26264 Res.second = &X86::VR512RegClass;
26270 int X86TargetLowering::getScalingFactorCost(const AddrMode &AM,
26272 // Scaling factors are not free at all.
26273 // An indexed folded instruction, i.e., inst (reg1, reg2, scale),
26274 // will take 2 allocations in the out of order engine instead of 1
26275 // for plain addressing mode, i.e. inst (reg1).
26277 // vaddps (%rsi,%drx), %ymm0, %ymm1
26278 // Requires two allocations (one for the load, one for the computation)
26280 // vaddps (%rsi), %ymm0, %ymm1
26281 // Requires just 1 allocation, i.e., freeing allocations for other operations
26282 // and having less micro operations to execute.
26284 // For some X86 architectures, this is even worse because for instance for
26285 // stores, the complex addressing mode forces the instruction to use the
26286 // "load" ports instead of the dedicated "store" port.
26287 // E.g., on Haswell:
26288 // vmovaps %ymm1, (%r8, %rdi) can use port 2 or 3.
26289 // vmovaps %ymm1, (%r8) can use port 2, 3, or 7.
26290 if (isLegalAddressingMode(AM, Ty))
26291 // Scale represents reg2 * scale, thus account for 1
26292 // as soon as we use a second register.
26293 return AM.Scale != 0;
26297 bool X86TargetLowering::isTargetFTOL() const {
26298 return Subtarget->isTargetKnownWindowsMSVC() && !Subtarget->is64Bit();