1 //===-- X86ISelLowering.cpp - X86 DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that X86 uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "x86-isel"
16 #include "X86ISelLowering.h"
18 #include "X86InstrBuilder.h"
19 #include "X86TargetMachine.h"
20 #include "X86TargetObjectFile.h"
21 #include "Utils/X86ShuffleDecode.h"
22 #include "llvm/CallingConv.h"
23 #include "llvm/Constants.h"
24 #include "llvm/DerivedTypes.h"
25 #include "llvm/GlobalAlias.h"
26 #include "llvm/GlobalVariable.h"
27 #include "llvm/Function.h"
28 #include "llvm/Instructions.h"
29 #include "llvm/Intrinsics.h"
30 #include "llvm/LLVMContext.h"
31 #include "llvm/CodeGen/IntrinsicLowering.h"
32 #include "llvm/CodeGen/MachineFrameInfo.h"
33 #include "llvm/CodeGen/MachineFunction.h"
34 #include "llvm/CodeGen/MachineInstrBuilder.h"
35 #include "llvm/CodeGen/MachineJumpTableInfo.h"
36 #include "llvm/CodeGen/MachineModuleInfo.h"
37 #include "llvm/CodeGen/MachineRegisterInfo.h"
38 #include "llvm/MC/MCAsmInfo.h"
39 #include "llvm/MC/MCContext.h"
40 #include "llvm/MC/MCExpr.h"
41 #include "llvm/MC/MCSymbol.h"
42 #include "llvm/ADT/SmallSet.h"
43 #include "llvm/ADT/Statistic.h"
44 #include "llvm/ADT/StringExtras.h"
45 #include "llvm/ADT/VariadicFunction.h"
46 #include "llvm/Support/CallSite.h"
47 #include "llvm/Support/Debug.h"
48 #include "llvm/Support/ErrorHandling.h"
49 #include "llvm/Support/MathExtras.h"
50 #include "llvm/Target/TargetOptions.h"
54 STATISTIC(NumTailCalls, "Number of tail calls");
56 // Forward declarations.
57 static SDValue getMOVL(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1,
60 /// Generate a DAG to grab 128-bits from a vector > 128 bits. This
61 /// sets things up to match to an AVX VEXTRACTF128 instruction or a
62 /// simple subregister reference. Idx is an index in the 128 bits we
63 /// want. It need not be aligned to a 128-bit bounday. That makes
64 /// lowering EXTRACT_VECTOR_ELT operations easier.
65 static SDValue Extract128BitVector(SDValue Vec,
69 EVT VT = Vec.getValueType();
70 assert(VT.getSizeInBits() == 256 && "Unexpected vector size!");
71 EVT ElVT = VT.getVectorElementType();
72 int Factor = VT.getSizeInBits()/128;
73 EVT ResultVT = EVT::getVectorVT(*DAG.getContext(), ElVT,
74 VT.getVectorNumElements()/Factor);
76 // Extract from UNDEF is UNDEF.
77 if (Vec.getOpcode() == ISD::UNDEF)
78 return DAG.getNode(ISD::UNDEF, dl, ResultVT);
80 if (isa<ConstantSDNode>(Idx)) {
81 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
83 // Extract the relevant 128 bits. Generate an EXTRACT_SUBVECTOR
84 // we can match to VEXTRACTF128.
85 unsigned ElemsPerChunk = 128 / ElVT.getSizeInBits();
87 // This is the index of the first element of the 128-bit chunk
89 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits()) / 128)
92 SDValue VecIdx = DAG.getConstant(NormalizedIdxVal, MVT::i32);
93 SDValue Result = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, ResultVT, Vec,
102 /// Generate a DAG to put 128-bits into a vector > 128 bits. This
103 /// sets things up to match to an AVX VINSERTF128 instruction or a
104 /// simple superregister reference. Idx is an index in the 128 bits
105 /// we want. It need not be aligned to a 128-bit bounday. That makes
106 /// lowering INSERT_VECTOR_ELT operations easier.
107 static SDValue Insert128BitVector(SDValue Result,
112 if (isa<ConstantSDNode>(Idx)) {
113 EVT VT = Vec.getValueType();
114 assert(VT.getSizeInBits() == 128 && "Unexpected vector size!");
116 EVT ElVT = VT.getVectorElementType();
117 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
118 EVT ResultVT = Result.getValueType();
120 // Insert the relevant 128 bits.
121 unsigned ElemsPerChunk = 128/ElVT.getSizeInBits();
123 // This is the index of the first element of the 128-bit chunk
125 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits())/128)
128 SDValue VecIdx = DAG.getConstant(NormalizedIdxVal, MVT::i32);
129 Result = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResultVT, Result, Vec,
137 static TargetLoweringObjectFile *createTLOF(X86TargetMachine &TM) {
138 const X86Subtarget *Subtarget = &TM.getSubtarget<X86Subtarget>();
139 bool is64Bit = Subtarget->is64Bit();
141 if (Subtarget->isTargetEnvMacho()) {
143 return new X8664_MachoTargetObjectFile();
144 return new TargetLoweringObjectFileMachO();
147 if (Subtarget->isTargetELF())
148 return new TargetLoweringObjectFileELF();
149 if (Subtarget->isTargetCOFF() && !Subtarget->isTargetEnvMacho())
150 return new TargetLoweringObjectFileCOFF();
151 llvm_unreachable("unknown subtarget type");
154 X86TargetLowering::X86TargetLowering(X86TargetMachine &TM)
155 : TargetLowering(TM, createTLOF(TM)) {
156 Subtarget = &TM.getSubtarget<X86Subtarget>();
157 X86ScalarSSEf64 = Subtarget->hasSSE2();
158 X86ScalarSSEf32 = Subtarget->hasSSE1();
159 X86StackPtr = Subtarget->is64Bit() ? X86::RSP : X86::ESP;
161 RegInfo = TM.getRegisterInfo();
162 TD = getTargetData();
164 // Set up the TargetLowering object.
165 static const MVT IntVTs[] = { MVT::i8, MVT::i16, MVT::i32, MVT::i64 };
167 // X86 is weird, it always uses i8 for shift amounts and setcc results.
168 setBooleanContents(ZeroOrOneBooleanContent);
169 // X86-SSE is even stranger. It uses -1 or 0 for vector masks.
170 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
172 // For 64-bit since we have so many registers use the ILP scheduler, for
173 // 32-bit code use the register pressure specific scheduling.
174 // For 32 bit Atom, use Hybrid (register pressure + latency) scheduling.
175 if (Subtarget->is64Bit())
176 setSchedulingPreference(Sched::ILP);
177 else if (Subtarget->isAtom())
178 setSchedulingPreference(Sched::Hybrid);
180 setSchedulingPreference(Sched::RegPressure);
181 setStackPointerRegisterToSaveRestore(X86StackPtr);
183 if (Subtarget->isTargetWindows() && !Subtarget->isTargetCygMing()) {
184 // Setup Windows compiler runtime calls.
185 setLibcallName(RTLIB::SDIV_I64, "_alldiv");
186 setLibcallName(RTLIB::UDIV_I64, "_aulldiv");
187 setLibcallName(RTLIB::SREM_I64, "_allrem");
188 setLibcallName(RTLIB::UREM_I64, "_aullrem");
189 setLibcallName(RTLIB::MUL_I64, "_allmul");
190 setLibcallCallingConv(RTLIB::SDIV_I64, CallingConv::X86_StdCall);
191 setLibcallCallingConv(RTLIB::UDIV_I64, CallingConv::X86_StdCall);
192 setLibcallCallingConv(RTLIB::SREM_I64, CallingConv::X86_StdCall);
193 setLibcallCallingConv(RTLIB::UREM_I64, CallingConv::X86_StdCall);
194 setLibcallCallingConv(RTLIB::MUL_I64, CallingConv::X86_StdCall);
196 // The _ftol2 runtime function has an unusual calling conv, which
197 // is modeled by a special pseudo-instruction.
198 setLibcallName(RTLIB::FPTOUINT_F64_I64, 0);
199 setLibcallName(RTLIB::FPTOUINT_F32_I64, 0);
200 setLibcallName(RTLIB::FPTOUINT_F64_I32, 0);
201 setLibcallName(RTLIB::FPTOUINT_F32_I32, 0);
204 if (Subtarget->isTargetDarwin()) {
205 // Darwin should use _setjmp/_longjmp instead of setjmp/longjmp.
206 setUseUnderscoreSetJmp(false);
207 setUseUnderscoreLongJmp(false);
208 } else if (Subtarget->isTargetMingw()) {
209 // MS runtime is weird: it exports _setjmp, but longjmp!
210 setUseUnderscoreSetJmp(true);
211 setUseUnderscoreLongJmp(false);
213 setUseUnderscoreSetJmp(true);
214 setUseUnderscoreLongJmp(true);
217 // Set up the register classes.
218 addRegisterClass(MVT::i8, &X86::GR8RegClass);
219 addRegisterClass(MVT::i16, &X86::GR16RegClass);
220 addRegisterClass(MVT::i32, &X86::GR32RegClass);
221 if (Subtarget->is64Bit())
222 addRegisterClass(MVT::i64, &X86::GR64RegClass);
224 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
226 // We don't accept any truncstore of integer registers.
227 setTruncStoreAction(MVT::i64, MVT::i32, Expand);
228 setTruncStoreAction(MVT::i64, MVT::i16, Expand);
229 setTruncStoreAction(MVT::i64, MVT::i8 , Expand);
230 setTruncStoreAction(MVT::i32, MVT::i16, Expand);
231 setTruncStoreAction(MVT::i32, MVT::i8 , Expand);
232 setTruncStoreAction(MVT::i16, MVT::i8, Expand);
234 // SETOEQ and SETUNE require checking two conditions.
235 setCondCodeAction(ISD::SETOEQ, MVT::f32, Expand);
236 setCondCodeAction(ISD::SETOEQ, MVT::f64, Expand);
237 setCondCodeAction(ISD::SETOEQ, MVT::f80, Expand);
238 setCondCodeAction(ISD::SETUNE, MVT::f32, Expand);
239 setCondCodeAction(ISD::SETUNE, MVT::f64, Expand);
240 setCondCodeAction(ISD::SETUNE, MVT::f80, Expand);
242 // Promote all UINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have this
244 setOperationAction(ISD::UINT_TO_FP , MVT::i1 , Promote);
245 setOperationAction(ISD::UINT_TO_FP , MVT::i8 , Promote);
246 setOperationAction(ISD::UINT_TO_FP , MVT::i16 , Promote);
248 if (Subtarget->is64Bit()) {
249 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote);
250 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
251 } else if (!TM.Options.UseSoftFloat) {
252 // We have an algorithm for SSE2->double, and we turn this into a
253 // 64-bit FILD followed by conditional FADD for other targets.
254 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
255 // We have an algorithm for SSE2, and we turn this into a 64-bit
256 // FILD for other targets.
257 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Custom);
260 // Promote i1/i8 SINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have
262 setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote);
263 setOperationAction(ISD::SINT_TO_FP , MVT::i8 , Promote);
265 if (!TM.Options.UseSoftFloat) {
266 // SSE has no i16 to fp conversion, only i32
267 if (X86ScalarSSEf32) {
268 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
269 // f32 and f64 cases are Legal, f80 case is not
270 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
272 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Custom);
273 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
276 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
277 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Promote);
280 // In 32-bit mode these are custom lowered. In 64-bit mode F32 and F64
281 // are Legal, f80 is custom lowered.
282 setOperationAction(ISD::FP_TO_SINT , MVT::i64 , Custom);
283 setOperationAction(ISD::SINT_TO_FP , MVT::i64 , Custom);
285 // Promote i1/i8 FP_TO_SINT to larger FP_TO_SINTS's, as X86 doesn't have
287 setOperationAction(ISD::FP_TO_SINT , MVT::i1 , Promote);
288 setOperationAction(ISD::FP_TO_SINT , MVT::i8 , Promote);
290 if (X86ScalarSSEf32) {
291 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Promote);
292 // f32 and f64 cases are Legal, f80 case is not
293 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
295 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Custom);
296 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
299 // Handle FP_TO_UINT by promoting the destination to a larger signed
301 setOperationAction(ISD::FP_TO_UINT , MVT::i1 , Promote);
302 setOperationAction(ISD::FP_TO_UINT , MVT::i8 , Promote);
303 setOperationAction(ISD::FP_TO_UINT , MVT::i16 , Promote);
305 if (Subtarget->is64Bit()) {
306 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Expand);
307 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote);
308 } else if (!TM.Options.UseSoftFloat) {
309 // Since AVX is a superset of SSE3, only check for SSE here.
310 if (Subtarget->hasSSE1() && !Subtarget->hasSSE3())
311 // Expand FP_TO_UINT into a select.
312 // FIXME: We would like to use a Custom expander here eventually to do
313 // the optimal thing for SSE vs. the default expansion in the legalizer.
314 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Expand);
316 // With SSE3 we can use fisttpll to convert to a signed i64; without
317 // SSE, we're stuck with a fistpll.
318 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Custom);
321 if (isTargetFTOL()) {
322 // Use the _ftol2 runtime function, which has a pseudo-instruction
323 // to handle its weird calling convention.
324 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Custom);
327 // TODO: when we have SSE, these could be more efficient, by using movd/movq.
328 if (!X86ScalarSSEf64) {
329 setOperationAction(ISD::BITCAST , MVT::f32 , Expand);
330 setOperationAction(ISD::BITCAST , MVT::i32 , Expand);
331 if (Subtarget->is64Bit()) {
332 setOperationAction(ISD::BITCAST , MVT::f64 , Expand);
333 // Without SSE, i64->f64 goes through memory.
334 setOperationAction(ISD::BITCAST , MVT::i64 , Expand);
338 // Scalar integer divide and remainder are lowered to use operations that
339 // produce two results, to match the available instructions. This exposes
340 // the two-result form to trivial CSE, which is able to combine x/y and x%y
341 // into a single instruction.
343 // Scalar integer multiply-high is also lowered to use two-result
344 // operations, to match the available instructions. However, plain multiply
345 // (low) operations are left as Legal, as there are single-result
346 // instructions for this in x86. Using the two-result multiply instructions
347 // when both high and low results are needed must be arranged by dagcombine.
348 for (unsigned i = 0; i != array_lengthof(IntVTs); ++i) {
350 setOperationAction(ISD::MULHS, VT, Expand);
351 setOperationAction(ISD::MULHU, VT, Expand);
352 setOperationAction(ISD::SDIV, VT, Expand);
353 setOperationAction(ISD::UDIV, VT, Expand);
354 setOperationAction(ISD::SREM, VT, Expand);
355 setOperationAction(ISD::UREM, VT, Expand);
357 // Add/Sub overflow ops with MVT::Glues are lowered to EFLAGS dependences.
358 setOperationAction(ISD::ADDC, VT, Custom);
359 setOperationAction(ISD::ADDE, VT, Custom);
360 setOperationAction(ISD::SUBC, VT, Custom);
361 setOperationAction(ISD::SUBE, VT, Custom);
364 setOperationAction(ISD::BR_JT , MVT::Other, Expand);
365 setOperationAction(ISD::BRCOND , MVT::Other, Custom);
366 setOperationAction(ISD::BR_CC , MVT::Other, Expand);
367 setOperationAction(ISD::SELECT_CC , MVT::Other, Expand);
368 if (Subtarget->is64Bit())
369 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal);
370 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Legal);
371 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Legal);
372 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
373 setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand);
374 setOperationAction(ISD::FREM , MVT::f32 , Expand);
375 setOperationAction(ISD::FREM , MVT::f64 , Expand);
376 setOperationAction(ISD::FREM , MVT::f80 , Expand);
377 setOperationAction(ISD::FLT_ROUNDS_ , MVT::i32 , Custom);
379 // Promote the i8 variants and force them on up to i32 which has a shorter
381 setOperationAction(ISD::CTTZ , MVT::i8 , Promote);
382 AddPromotedToType (ISD::CTTZ , MVT::i8 , MVT::i32);
383 setOperationAction(ISD::CTTZ_ZERO_UNDEF , MVT::i8 , Promote);
384 AddPromotedToType (ISD::CTTZ_ZERO_UNDEF , MVT::i8 , MVT::i32);
385 if (Subtarget->hasBMI()) {
386 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i16 , Expand);
387 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32 , Expand);
388 if (Subtarget->is64Bit())
389 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand);
391 setOperationAction(ISD::CTTZ , MVT::i16 , Custom);
392 setOperationAction(ISD::CTTZ , MVT::i32 , Custom);
393 if (Subtarget->is64Bit())
394 setOperationAction(ISD::CTTZ , MVT::i64 , Custom);
397 if (Subtarget->hasLZCNT()) {
398 // When promoting the i8 variants, force them to i32 for a shorter
400 setOperationAction(ISD::CTLZ , MVT::i8 , Promote);
401 AddPromotedToType (ISD::CTLZ , MVT::i8 , MVT::i32);
402 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Promote);
403 AddPromotedToType (ISD::CTLZ_ZERO_UNDEF, MVT::i8 , MVT::i32);
404 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Expand);
405 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Expand);
406 if (Subtarget->is64Bit())
407 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Expand);
409 setOperationAction(ISD::CTLZ , MVT::i8 , Custom);
410 setOperationAction(ISD::CTLZ , MVT::i16 , Custom);
411 setOperationAction(ISD::CTLZ , MVT::i32 , Custom);
412 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Custom);
413 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Custom);
414 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Custom);
415 if (Subtarget->is64Bit()) {
416 setOperationAction(ISD::CTLZ , MVT::i64 , Custom);
417 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Custom);
421 if (Subtarget->hasPOPCNT()) {
422 setOperationAction(ISD::CTPOP , MVT::i8 , Promote);
424 setOperationAction(ISD::CTPOP , MVT::i8 , Expand);
425 setOperationAction(ISD::CTPOP , MVT::i16 , Expand);
426 setOperationAction(ISD::CTPOP , MVT::i32 , Expand);
427 if (Subtarget->is64Bit())
428 setOperationAction(ISD::CTPOP , MVT::i64 , Expand);
431 setOperationAction(ISD::READCYCLECOUNTER , MVT::i64 , Custom);
432 setOperationAction(ISD::BSWAP , MVT::i16 , Expand);
434 // These should be promoted to a larger select which is supported.
435 setOperationAction(ISD::SELECT , MVT::i1 , Promote);
436 // X86 wants to expand cmov itself.
437 setOperationAction(ISD::SELECT , MVT::i8 , Custom);
438 setOperationAction(ISD::SELECT , MVT::i16 , Custom);
439 setOperationAction(ISD::SELECT , MVT::i32 , Custom);
440 setOperationAction(ISD::SELECT , MVT::f32 , Custom);
441 setOperationAction(ISD::SELECT , MVT::f64 , Custom);
442 setOperationAction(ISD::SELECT , MVT::f80 , Custom);
443 setOperationAction(ISD::SETCC , MVT::i8 , Custom);
444 setOperationAction(ISD::SETCC , MVT::i16 , Custom);
445 setOperationAction(ISD::SETCC , MVT::i32 , Custom);
446 setOperationAction(ISD::SETCC , MVT::f32 , Custom);
447 setOperationAction(ISD::SETCC , MVT::f64 , Custom);
448 setOperationAction(ISD::SETCC , MVT::f80 , Custom);
449 if (Subtarget->is64Bit()) {
450 setOperationAction(ISD::SELECT , MVT::i64 , Custom);
451 setOperationAction(ISD::SETCC , MVT::i64 , Custom);
453 setOperationAction(ISD::EH_RETURN , MVT::Other, Custom);
456 setOperationAction(ISD::ConstantPool , MVT::i32 , Custom);
457 setOperationAction(ISD::JumpTable , MVT::i32 , Custom);
458 setOperationAction(ISD::GlobalAddress , MVT::i32 , Custom);
459 setOperationAction(ISD::GlobalTLSAddress, MVT::i32 , Custom);
460 if (Subtarget->is64Bit())
461 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
462 setOperationAction(ISD::ExternalSymbol , MVT::i32 , Custom);
463 setOperationAction(ISD::BlockAddress , MVT::i32 , Custom);
464 if (Subtarget->is64Bit()) {
465 setOperationAction(ISD::ConstantPool , MVT::i64 , Custom);
466 setOperationAction(ISD::JumpTable , MVT::i64 , Custom);
467 setOperationAction(ISD::GlobalAddress , MVT::i64 , Custom);
468 setOperationAction(ISD::ExternalSymbol, MVT::i64 , Custom);
469 setOperationAction(ISD::BlockAddress , MVT::i64 , Custom);
471 // 64-bit addm sub, shl, sra, srl (iff 32-bit x86)
472 setOperationAction(ISD::SHL_PARTS , MVT::i32 , Custom);
473 setOperationAction(ISD::SRA_PARTS , MVT::i32 , Custom);
474 setOperationAction(ISD::SRL_PARTS , MVT::i32 , Custom);
475 if (Subtarget->is64Bit()) {
476 setOperationAction(ISD::SHL_PARTS , MVT::i64 , Custom);
477 setOperationAction(ISD::SRA_PARTS , MVT::i64 , Custom);
478 setOperationAction(ISD::SRL_PARTS , MVT::i64 , Custom);
481 if (Subtarget->hasSSE1())
482 setOperationAction(ISD::PREFETCH , MVT::Other, Legal);
484 setOperationAction(ISD::MEMBARRIER , MVT::Other, Custom);
485 setOperationAction(ISD::ATOMIC_FENCE , MVT::Other, Custom);
487 // On X86 and X86-64, atomic operations are lowered to locked instructions.
488 // Locked instructions, in turn, have implicit fence semantics (all memory
489 // operations are flushed before issuing the locked instruction, and they
490 // are not buffered), so we can fold away the common pattern of
491 // fence-atomic-fence.
492 setShouldFoldAtomicFences(true);
494 // Expand certain atomics
495 for (unsigned i = 0; i != array_lengthof(IntVTs); ++i) {
497 setOperationAction(ISD::ATOMIC_CMP_SWAP, VT, Custom);
498 setOperationAction(ISD::ATOMIC_LOAD_SUB, VT, Custom);
499 setOperationAction(ISD::ATOMIC_STORE, VT, Custom);
502 if (!Subtarget->is64Bit()) {
503 setOperationAction(ISD::ATOMIC_LOAD, MVT::i64, Custom);
504 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i64, Custom);
505 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i64, Custom);
506 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i64, Custom);
507 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i64, Custom);
508 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i64, Custom);
509 setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i64, Custom);
510 setOperationAction(ISD::ATOMIC_SWAP, MVT::i64, Custom);
513 if (Subtarget->hasCmpxchg16b()) {
514 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i128, Custom);
517 // FIXME - use subtarget debug flags
518 if (!Subtarget->isTargetDarwin() &&
519 !Subtarget->isTargetELF() &&
520 !Subtarget->isTargetCygMing()) {
521 setOperationAction(ISD::EH_LABEL, MVT::Other, Expand);
524 setOperationAction(ISD::EXCEPTIONADDR, MVT::i64, Expand);
525 setOperationAction(ISD::EHSELECTION, MVT::i64, Expand);
526 setOperationAction(ISD::EXCEPTIONADDR, MVT::i32, Expand);
527 setOperationAction(ISD::EHSELECTION, MVT::i32, Expand);
528 if (Subtarget->is64Bit()) {
529 setExceptionPointerRegister(X86::RAX);
530 setExceptionSelectorRegister(X86::RDX);
532 setExceptionPointerRegister(X86::EAX);
533 setExceptionSelectorRegister(X86::EDX);
535 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i32, Custom);
536 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i64, Custom);
538 setOperationAction(ISD::INIT_TRAMPOLINE, MVT::Other, Custom);
539 setOperationAction(ISD::ADJUST_TRAMPOLINE, MVT::Other, Custom);
541 setOperationAction(ISD::TRAP, MVT::Other, Legal);
543 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
544 setOperationAction(ISD::VASTART , MVT::Other, Custom);
545 setOperationAction(ISD::VAEND , MVT::Other, Expand);
546 if (Subtarget->is64Bit()) {
547 setOperationAction(ISD::VAARG , MVT::Other, Custom);
548 setOperationAction(ISD::VACOPY , MVT::Other, Custom);
550 setOperationAction(ISD::VAARG , MVT::Other, Expand);
551 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
554 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
555 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
557 if (Subtarget->isTargetCOFF() && !Subtarget->isTargetEnvMacho())
558 setOperationAction(ISD::DYNAMIC_STACKALLOC, Subtarget->is64Bit() ?
559 MVT::i64 : MVT::i32, Custom);
560 else if (TM.Options.EnableSegmentedStacks)
561 setOperationAction(ISD::DYNAMIC_STACKALLOC, Subtarget->is64Bit() ?
562 MVT::i64 : MVT::i32, Custom);
564 setOperationAction(ISD::DYNAMIC_STACKALLOC, Subtarget->is64Bit() ?
565 MVT::i64 : MVT::i32, Expand);
567 if (!TM.Options.UseSoftFloat && X86ScalarSSEf64) {
568 // f32 and f64 use SSE.
569 // Set up the FP register classes.
570 addRegisterClass(MVT::f32, &X86::FR32RegClass);
571 addRegisterClass(MVT::f64, &X86::FR64RegClass);
573 // Use ANDPD to simulate FABS.
574 setOperationAction(ISD::FABS , MVT::f64, Custom);
575 setOperationAction(ISD::FABS , MVT::f32, Custom);
577 // Use XORP to simulate FNEG.
578 setOperationAction(ISD::FNEG , MVT::f64, Custom);
579 setOperationAction(ISD::FNEG , MVT::f32, Custom);
581 // Use ANDPD and ORPD to simulate FCOPYSIGN.
582 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
583 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
585 // Lower this to FGETSIGNx86 plus an AND.
586 setOperationAction(ISD::FGETSIGN, MVT::i64, Custom);
587 setOperationAction(ISD::FGETSIGN, MVT::i32, Custom);
589 // We don't support sin/cos/fmod
590 setOperationAction(ISD::FSIN , MVT::f64, Expand);
591 setOperationAction(ISD::FCOS , MVT::f64, Expand);
592 setOperationAction(ISD::FSIN , MVT::f32, Expand);
593 setOperationAction(ISD::FCOS , MVT::f32, Expand);
595 // Expand FP immediates into loads from the stack, except for the special
597 addLegalFPImmediate(APFloat(+0.0)); // xorpd
598 addLegalFPImmediate(APFloat(+0.0f)); // xorps
599 } else if (!TM.Options.UseSoftFloat && X86ScalarSSEf32) {
600 // Use SSE for f32, x87 for f64.
601 // Set up the FP register classes.
602 addRegisterClass(MVT::f32, &X86::FR32RegClass);
603 addRegisterClass(MVT::f64, &X86::RFP64RegClass);
605 // Use ANDPS to simulate FABS.
606 setOperationAction(ISD::FABS , MVT::f32, Custom);
608 // Use XORP to simulate FNEG.
609 setOperationAction(ISD::FNEG , MVT::f32, Custom);
611 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
613 // Use ANDPS and ORPS to simulate FCOPYSIGN.
614 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
615 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
617 // We don't support sin/cos/fmod
618 setOperationAction(ISD::FSIN , MVT::f32, Expand);
619 setOperationAction(ISD::FCOS , MVT::f32, Expand);
621 // Special cases we handle for FP constants.
622 addLegalFPImmediate(APFloat(+0.0f)); // xorps
623 addLegalFPImmediate(APFloat(+0.0)); // FLD0
624 addLegalFPImmediate(APFloat(+1.0)); // FLD1
625 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
626 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
628 if (!TM.Options.UnsafeFPMath) {
629 setOperationAction(ISD::FSIN , MVT::f64 , Expand);
630 setOperationAction(ISD::FCOS , MVT::f64 , Expand);
632 } else if (!TM.Options.UseSoftFloat) {
633 // f32 and f64 in x87.
634 // Set up the FP register classes.
635 addRegisterClass(MVT::f64, &X86::RFP64RegClass);
636 addRegisterClass(MVT::f32, &X86::RFP32RegClass);
638 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
639 setOperationAction(ISD::UNDEF, MVT::f32, Expand);
640 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
641 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
643 if (!TM.Options.UnsafeFPMath) {
644 setOperationAction(ISD::FSIN , MVT::f64 , Expand);
645 setOperationAction(ISD::FCOS , MVT::f64 , Expand);
647 addLegalFPImmediate(APFloat(+0.0)); // FLD0
648 addLegalFPImmediate(APFloat(+1.0)); // FLD1
649 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
650 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
651 addLegalFPImmediate(APFloat(+0.0f)); // FLD0
652 addLegalFPImmediate(APFloat(+1.0f)); // FLD1
653 addLegalFPImmediate(APFloat(-0.0f)); // FLD0/FCHS
654 addLegalFPImmediate(APFloat(-1.0f)); // FLD1/FCHS
657 // We don't support FMA.
658 setOperationAction(ISD::FMA, MVT::f64, Expand);
659 setOperationAction(ISD::FMA, MVT::f32, Expand);
661 // Long double always uses X87.
662 if (!TM.Options.UseSoftFloat) {
663 addRegisterClass(MVT::f80, &X86::RFP80RegClass);
664 setOperationAction(ISD::UNDEF, MVT::f80, Expand);
665 setOperationAction(ISD::FCOPYSIGN, MVT::f80, Expand);
667 APFloat TmpFlt = APFloat::getZero(APFloat::x87DoubleExtended);
668 addLegalFPImmediate(TmpFlt); // FLD0
670 addLegalFPImmediate(TmpFlt); // FLD0/FCHS
673 APFloat TmpFlt2(+1.0);
674 TmpFlt2.convert(APFloat::x87DoubleExtended, APFloat::rmNearestTiesToEven,
676 addLegalFPImmediate(TmpFlt2); // FLD1
677 TmpFlt2.changeSign();
678 addLegalFPImmediate(TmpFlt2); // FLD1/FCHS
681 if (!TM.Options.UnsafeFPMath) {
682 setOperationAction(ISD::FSIN , MVT::f80 , Expand);
683 setOperationAction(ISD::FCOS , MVT::f80 , Expand);
686 setOperationAction(ISD::FFLOOR, MVT::f80, Expand);
687 setOperationAction(ISD::FCEIL, MVT::f80, Expand);
688 setOperationAction(ISD::FTRUNC, MVT::f80, Expand);
689 setOperationAction(ISD::FRINT, MVT::f80, Expand);
690 setOperationAction(ISD::FNEARBYINT, MVT::f80, Expand);
691 setOperationAction(ISD::FMA, MVT::f80, Expand);
694 // Always use a library call for pow.
695 setOperationAction(ISD::FPOW , MVT::f32 , Expand);
696 setOperationAction(ISD::FPOW , MVT::f64 , Expand);
697 setOperationAction(ISD::FPOW , MVT::f80 , Expand);
699 setOperationAction(ISD::FLOG, MVT::f80, Expand);
700 setOperationAction(ISD::FLOG2, MVT::f80, Expand);
701 setOperationAction(ISD::FLOG10, MVT::f80, Expand);
702 setOperationAction(ISD::FEXP, MVT::f80, Expand);
703 setOperationAction(ISD::FEXP2, MVT::f80, Expand);
705 // First set operation action for all vector types to either promote
706 // (for widening) or expand (for scalarization). Then we will selectively
707 // turn on ones that can be effectively codegen'd.
708 for (unsigned VT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
709 VT <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++VT) {
710 setOperationAction(ISD::ADD , (MVT::SimpleValueType)VT, Expand);
711 setOperationAction(ISD::SUB , (MVT::SimpleValueType)VT, Expand);
712 setOperationAction(ISD::FADD, (MVT::SimpleValueType)VT, Expand);
713 setOperationAction(ISD::FNEG, (MVT::SimpleValueType)VT, Expand);
714 setOperationAction(ISD::FSUB, (MVT::SimpleValueType)VT, Expand);
715 setOperationAction(ISD::MUL , (MVT::SimpleValueType)VT, Expand);
716 setOperationAction(ISD::FMUL, (MVT::SimpleValueType)VT, Expand);
717 setOperationAction(ISD::SDIV, (MVT::SimpleValueType)VT, Expand);
718 setOperationAction(ISD::UDIV, (MVT::SimpleValueType)VT, Expand);
719 setOperationAction(ISD::FDIV, (MVT::SimpleValueType)VT, Expand);
720 setOperationAction(ISD::SREM, (MVT::SimpleValueType)VT, Expand);
721 setOperationAction(ISD::UREM, (MVT::SimpleValueType)VT, Expand);
722 setOperationAction(ISD::LOAD, (MVT::SimpleValueType)VT, Expand);
723 setOperationAction(ISD::VECTOR_SHUFFLE, (MVT::SimpleValueType)VT, Expand);
724 setOperationAction(ISD::EXTRACT_VECTOR_ELT,(MVT::SimpleValueType)VT,Expand);
725 setOperationAction(ISD::INSERT_VECTOR_ELT,(MVT::SimpleValueType)VT, Expand);
726 setOperationAction(ISD::EXTRACT_SUBVECTOR,(MVT::SimpleValueType)VT,Expand);
727 setOperationAction(ISD::INSERT_SUBVECTOR,(MVT::SimpleValueType)VT,Expand);
728 setOperationAction(ISD::FABS, (MVT::SimpleValueType)VT, Expand);
729 setOperationAction(ISD::FSIN, (MVT::SimpleValueType)VT, Expand);
730 setOperationAction(ISD::FCOS, (MVT::SimpleValueType)VT, Expand);
731 setOperationAction(ISD::FREM, (MVT::SimpleValueType)VT, Expand);
732 setOperationAction(ISD::FPOWI, (MVT::SimpleValueType)VT, Expand);
733 setOperationAction(ISD::FSQRT, (MVT::SimpleValueType)VT, Expand);
734 setOperationAction(ISD::FCOPYSIGN, (MVT::SimpleValueType)VT, Expand);
735 setOperationAction(ISD::SMUL_LOHI, (MVT::SimpleValueType)VT, Expand);
736 setOperationAction(ISD::UMUL_LOHI, (MVT::SimpleValueType)VT, Expand);
737 setOperationAction(ISD::SDIVREM, (MVT::SimpleValueType)VT, Expand);
738 setOperationAction(ISD::UDIVREM, (MVT::SimpleValueType)VT, Expand);
739 setOperationAction(ISD::FPOW, (MVT::SimpleValueType)VT, Expand);
740 setOperationAction(ISD::CTPOP, (MVT::SimpleValueType)VT, Expand);
741 setOperationAction(ISD::CTTZ, (MVT::SimpleValueType)VT, Expand);
742 setOperationAction(ISD::CTTZ_ZERO_UNDEF, (MVT::SimpleValueType)VT, Expand);
743 setOperationAction(ISD::CTLZ, (MVT::SimpleValueType)VT, Expand);
744 setOperationAction(ISD::CTLZ_ZERO_UNDEF, (MVT::SimpleValueType)VT, Expand);
745 setOperationAction(ISD::SHL, (MVT::SimpleValueType)VT, Expand);
746 setOperationAction(ISD::SRA, (MVT::SimpleValueType)VT, Expand);
747 setOperationAction(ISD::SRL, (MVT::SimpleValueType)VT, Expand);
748 setOperationAction(ISD::ROTL, (MVT::SimpleValueType)VT, Expand);
749 setOperationAction(ISD::ROTR, (MVT::SimpleValueType)VT, Expand);
750 setOperationAction(ISD::BSWAP, (MVT::SimpleValueType)VT, Expand);
751 setOperationAction(ISD::SETCC, (MVT::SimpleValueType)VT, Expand);
752 setOperationAction(ISD::FLOG, (MVT::SimpleValueType)VT, Expand);
753 setOperationAction(ISD::FLOG2, (MVT::SimpleValueType)VT, Expand);
754 setOperationAction(ISD::FLOG10, (MVT::SimpleValueType)VT, Expand);
755 setOperationAction(ISD::FEXP, (MVT::SimpleValueType)VT, Expand);
756 setOperationAction(ISD::FEXP2, (MVT::SimpleValueType)VT, Expand);
757 setOperationAction(ISD::FP_TO_UINT, (MVT::SimpleValueType)VT, Expand);
758 setOperationAction(ISD::FP_TO_SINT, (MVT::SimpleValueType)VT, Expand);
759 setOperationAction(ISD::UINT_TO_FP, (MVT::SimpleValueType)VT, Expand);
760 setOperationAction(ISD::SINT_TO_FP, (MVT::SimpleValueType)VT, Expand);
761 setOperationAction(ISD::SIGN_EXTEND_INREG, (MVT::SimpleValueType)VT,Expand);
762 setOperationAction(ISD::TRUNCATE, (MVT::SimpleValueType)VT, Expand);
763 setOperationAction(ISD::SIGN_EXTEND, (MVT::SimpleValueType)VT, Expand);
764 setOperationAction(ISD::ZERO_EXTEND, (MVT::SimpleValueType)VT, Expand);
765 setOperationAction(ISD::ANY_EXTEND, (MVT::SimpleValueType)VT, Expand);
766 setOperationAction(ISD::VSELECT, (MVT::SimpleValueType)VT, Expand);
767 for (unsigned InnerVT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
768 InnerVT <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++InnerVT)
769 setTruncStoreAction((MVT::SimpleValueType)VT,
770 (MVT::SimpleValueType)InnerVT, Expand);
771 setLoadExtAction(ISD::SEXTLOAD, (MVT::SimpleValueType)VT, Expand);
772 setLoadExtAction(ISD::ZEXTLOAD, (MVT::SimpleValueType)VT, Expand);
773 setLoadExtAction(ISD::EXTLOAD, (MVT::SimpleValueType)VT, Expand);
776 // FIXME: In order to prevent SSE instructions being expanded to MMX ones
777 // with -msoft-float, disable use of MMX as well.
778 if (!TM.Options.UseSoftFloat && Subtarget->hasMMX()) {
779 addRegisterClass(MVT::x86mmx, &X86::VR64RegClass);
780 // No operations on x86mmx supported, everything uses intrinsics.
783 // MMX-sized vectors (other than x86mmx) are expected to be expanded
784 // into smaller operations.
785 setOperationAction(ISD::MULHS, MVT::v8i8, Expand);
786 setOperationAction(ISD::MULHS, MVT::v4i16, Expand);
787 setOperationAction(ISD::MULHS, MVT::v2i32, Expand);
788 setOperationAction(ISD::MULHS, MVT::v1i64, Expand);
789 setOperationAction(ISD::AND, MVT::v8i8, Expand);
790 setOperationAction(ISD::AND, MVT::v4i16, Expand);
791 setOperationAction(ISD::AND, MVT::v2i32, Expand);
792 setOperationAction(ISD::AND, MVT::v1i64, Expand);
793 setOperationAction(ISD::OR, MVT::v8i8, Expand);
794 setOperationAction(ISD::OR, MVT::v4i16, Expand);
795 setOperationAction(ISD::OR, MVT::v2i32, Expand);
796 setOperationAction(ISD::OR, MVT::v1i64, Expand);
797 setOperationAction(ISD::XOR, MVT::v8i8, Expand);
798 setOperationAction(ISD::XOR, MVT::v4i16, Expand);
799 setOperationAction(ISD::XOR, MVT::v2i32, Expand);
800 setOperationAction(ISD::XOR, MVT::v1i64, Expand);
801 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i8, Expand);
802 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i16, Expand);
803 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2i32, Expand);
804 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v1i64, Expand);
805 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v1i64, Expand);
806 setOperationAction(ISD::SELECT, MVT::v8i8, Expand);
807 setOperationAction(ISD::SELECT, MVT::v4i16, Expand);
808 setOperationAction(ISD::SELECT, MVT::v2i32, Expand);
809 setOperationAction(ISD::SELECT, MVT::v1i64, Expand);
810 setOperationAction(ISD::BITCAST, MVT::v8i8, Expand);
811 setOperationAction(ISD::BITCAST, MVT::v4i16, Expand);
812 setOperationAction(ISD::BITCAST, MVT::v2i32, Expand);
813 setOperationAction(ISD::BITCAST, MVT::v1i64, Expand);
815 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE1()) {
816 addRegisterClass(MVT::v4f32, &X86::VR128RegClass);
818 setOperationAction(ISD::FADD, MVT::v4f32, Legal);
819 setOperationAction(ISD::FSUB, MVT::v4f32, Legal);
820 setOperationAction(ISD::FMUL, MVT::v4f32, Legal);
821 setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
822 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal);
823 setOperationAction(ISD::FNEG, MVT::v4f32, Custom);
824 setOperationAction(ISD::LOAD, MVT::v4f32, Legal);
825 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
826 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f32, Custom);
827 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
828 setOperationAction(ISD::SELECT, MVT::v4f32, Custom);
829 setOperationAction(ISD::SETCC, MVT::v4f32, Custom);
832 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE2()) {
833 addRegisterClass(MVT::v2f64, &X86::VR128RegClass);
835 // FIXME: Unfortunately -soft-float and -no-implicit-float means XMM
836 // registers cannot be used even for integer operations.
837 addRegisterClass(MVT::v16i8, &X86::VR128RegClass);
838 addRegisterClass(MVT::v8i16, &X86::VR128RegClass);
839 addRegisterClass(MVT::v4i32, &X86::VR128RegClass);
840 addRegisterClass(MVT::v2i64, &X86::VR128RegClass);
842 setOperationAction(ISD::ADD, MVT::v16i8, Legal);
843 setOperationAction(ISD::ADD, MVT::v8i16, Legal);
844 setOperationAction(ISD::ADD, MVT::v4i32, Legal);
845 setOperationAction(ISD::ADD, MVT::v2i64, Legal);
846 setOperationAction(ISD::MUL, MVT::v2i64, Custom);
847 setOperationAction(ISD::SUB, MVT::v16i8, Legal);
848 setOperationAction(ISD::SUB, MVT::v8i16, Legal);
849 setOperationAction(ISD::SUB, MVT::v4i32, Legal);
850 setOperationAction(ISD::SUB, MVT::v2i64, Legal);
851 setOperationAction(ISD::MUL, MVT::v8i16, Legal);
852 setOperationAction(ISD::FADD, MVT::v2f64, Legal);
853 setOperationAction(ISD::FSUB, MVT::v2f64, Legal);
854 setOperationAction(ISD::FMUL, MVT::v2f64, Legal);
855 setOperationAction(ISD::FDIV, MVT::v2f64, Legal);
856 setOperationAction(ISD::FSQRT, MVT::v2f64, Legal);
857 setOperationAction(ISD::FNEG, MVT::v2f64, Custom);
859 setOperationAction(ISD::SETCC, MVT::v2i64, Custom);
860 setOperationAction(ISD::SETCC, MVT::v16i8, Custom);
861 setOperationAction(ISD::SETCC, MVT::v8i16, Custom);
862 setOperationAction(ISD::SETCC, MVT::v4i32, Custom);
864 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Custom);
865 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Custom);
866 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
867 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
868 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
870 setOperationAction(ISD::CONCAT_VECTORS, MVT::v2f64, Custom);
871 setOperationAction(ISD::CONCAT_VECTORS, MVT::v2i64, Custom);
872 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i8, Custom);
873 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i16, Custom);
874 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4i32, Custom);
876 // Custom lower build_vector, vector_shuffle, and extract_vector_elt.
877 for (unsigned i = (unsigned)MVT::v16i8; i != (unsigned)MVT::v2i64; ++i) {
878 EVT VT = (MVT::SimpleValueType)i;
879 // Do not attempt to custom lower non-power-of-2 vectors
880 if (!isPowerOf2_32(VT.getVectorNumElements()))
882 // Do not attempt to custom lower non-128-bit vectors
883 if (!VT.is128BitVector())
885 setOperationAction(ISD::BUILD_VECTOR,
886 VT.getSimpleVT().SimpleTy, Custom);
887 setOperationAction(ISD::VECTOR_SHUFFLE,
888 VT.getSimpleVT().SimpleTy, Custom);
889 setOperationAction(ISD::EXTRACT_VECTOR_ELT,
890 VT.getSimpleVT().SimpleTy, Custom);
893 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f64, Custom);
894 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i64, Custom);
895 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Custom);
896 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Custom);
897 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f64, Custom);
898 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Custom);
900 if (Subtarget->is64Bit()) {
901 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
902 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
905 // Promote v16i8, v8i16, v4i32 load, select, and, or, xor to v2i64.
906 for (unsigned i = (unsigned)MVT::v16i8; i != (unsigned)MVT::v2i64; i++) {
907 MVT::SimpleValueType SVT = (MVT::SimpleValueType)i;
910 // Do not attempt to promote non-128-bit vectors
911 if (!VT.is128BitVector())
914 setOperationAction(ISD::AND, SVT, Promote);
915 AddPromotedToType (ISD::AND, SVT, MVT::v2i64);
916 setOperationAction(ISD::OR, SVT, Promote);
917 AddPromotedToType (ISD::OR, SVT, MVT::v2i64);
918 setOperationAction(ISD::XOR, SVT, Promote);
919 AddPromotedToType (ISD::XOR, SVT, MVT::v2i64);
920 setOperationAction(ISD::LOAD, SVT, Promote);
921 AddPromotedToType (ISD::LOAD, SVT, MVT::v2i64);
922 setOperationAction(ISD::SELECT, SVT, Promote);
923 AddPromotedToType (ISD::SELECT, SVT, MVT::v2i64);
926 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
928 // Custom lower v2i64 and v2f64 selects.
929 setOperationAction(ISD::LOAD, MVT::v2f64, Legal);
930 setOperationAction(ISD::LOAD, MVT::v2i64, Legal);
931 setOperationAction(ISD::SELECT, MVT::v2f64, Custom);
932 setOperationAction(ISD::SELECT, MVT::v2i64, Custom);
934 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal);
935 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal);
938 if (Subtarget->hasSSE41()) {
939 setOperationAction(ISD::FFLOOR, MVT::f32, Legal);
940 setOperationAction(ISD::FCEIL, MVT::f32, Legal);
941 setOperationAction(ISD::FTRUNC, MVT::f32, Legal);
942 setOperationAction(ISD::FRINT, MVT::f32, Legal);
943 setOperationAction(ISD::FNEARBYINT, MVT::f32, Legal);
944 setOperationAction(ISD::FFLOOR, MVT::f64, Legal);
945 setOperationAction(ISD::FCEIL, MVT::f64, Legal);
946 setOperationAction(ISD::FTRUNC, MVT::f64, Legal);
947 setOperationAction(ISD::FRINT, MVT::f64, Legal);
948 setOperationAction(ISD::FNEARBYINT, MVT::f64, Legal);
950 // FIXME: Do we need to handle scalar-to-vector here?
951 setOperationAction(ISD::MUL, MVT::v4i32, Legal);
953 setOperationAction(ISD::VSELECT, MVT::v2f64, Legal);
954 setOperationAction(ISD::VSELECT, MVT::v2i64, Legal);
955 setOperationAction(ISD::VSELECT, MVT::v16i8, Legal);
956 setOperationAction(ISD::VSELECT, MVT::v4i32, Legal);
957 setOperationAction(ISD::VSELECT, MVT::v4f32, Legal);
959 // i8 and i16 vectors are custom , because the source register and source
960 // source memory operand types are not the same width. f32 vectors are
961 // custom since the immediate controlling the insert encodes additional
963 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i8, Custom);
964 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
965 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
966 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
968 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i8, Custom);
969 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i16, Custom);
970 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i32, Custom);
971 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
973 // FIXME: these should be Legal but thats only for the case where
974 // the index is constant. For now custom expand to deal with that.
975 if (Subtarget->is64Bit()) {
976 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
977 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
981 if (Subtarget->hasSSE2()) {
982 setOperationAction(ISD::SRL, MVT::v8i16, Custom);
983 setOperationAction(ISD::SRL, MVT::v16i8, Custom);
985 setOperationAction(ISD::SHL, MVT::v8i16, Custom);
986 setOperationAction(ISD::SHL, MVT::v16i8, Custom);
988 setOperationAction(ISD::SRA, MVT::v8i16, Custom);
989 setOperationAction(ISD::SRA, MVT::v16i8, Custom);
991 if (Subtarget->hasAVX2()) {
992 setOperationAction(ISD::SRL, MVT::v2i64, Legal);
993 setOperationAction(ISD::SRL, MVT::v4i32, Legal);
995 setOperationAction(ISD::SHL, MVT::v2i64, Legal);
996 setOperationAction(ISD::SHL, MVT::v4i32, Legal);
998 setOperationAction(ISD::SRA, MVT::v4i32, Legal);
1000 setOperationAction(ISD::SRL, MVT::v2i64, Custom);
1001 setOperationAction(ISD::SRL, MVT::v4i32, Custom);
1003 setOperationAction(ISD::SHL, MVT::v2i64, Custom);
1004 setOperationAction(ISD::SHL, MVT::v4i32, Custom);
1006 setOperationAction(ISD::SRA, MVT::v4i32, Custom);
1010 if (Subtarget->hasSSE42())
1011 setOperationAction(ISD::SETCC, MVT::v2i64, Custom);
1013 if (!TM.Options.UseSoftFloat && Subtarget->hasAVX()) {
1014 addRegisterClass(MVT::v32i8, &X86::VR256RegClass);
1015 addRegisterClass(MVT::v16i16, &X86::VR256RegClass);
1016 addRegisterClass(MVT::v8i32, &X86::VR256RegClass);
1017 addRegisterClass(MVT::v8f32, &X86::VR256RegClass);
1018 addRegisterClass(MVT::v4i64, &X86::VR256RegClass);
1019 addRegisterClass(MVT::v4f64, &X86::VR256RegClass);
1021 setOperationAction(ISD::LOAD, MVT::v8f32, Legal);
1022 setOperationAction(ISD::LOAD, MVT::v4f64, Legal);
1023 setOperationAction(ISD::LOAD, MVT::v4i64, Legal);
1025 setOperationAction(ISD::FADD, MVT::v8f32, Legal);
1026 setOperationAction(ISD::FSUB, MVT::v8f32, Legal);
1027 setOperationAction(ISD::FMUL, MVT::v8f32, Legal);
1028 setOperationAction(ISD::FDIV, MVT::v8f32, Legal);
1029 setOperationAction(ISD::FSQRT, MVT::v8f32, Legal);
1030 setOperationAction(ISD::FNEG, MVT::v8f32, Custom);
1032 setOperationAction(ISD::FADD, MVT::v4f64, Legal);
1033 setOperationAction(ISD::FSUB, MVT::v4f64, Legal);
1034 setOperationAction(ISD::FMUL, MVT::v4f64, Legal);
1035 setOperationAction(ISD::FDIV, MVT::v4f64, Legal);
1036 setOperationAction(ISD::FSQRT, MVT::v4f64, Legal);
1037 setOperationAction(ISD::FNEG, MVT::v4f64, Custom);
1039 setOperationAction(ISD::FP_TO_SINT, MVT::v8i32, Legal);
1040 setOperationAction(ISD::SINT_TO_FP, MVT::v8i32, Legal);
1041 setOperationAction(ISD::FP_ROUND, MVT::v4f32, Legal);
1043 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4f64, Custom);
1044 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4i64, Custom);
1045 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8f32, Custom);
1046 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i32, Custom);
1047 setOperationAction(ISD::CONCAT_VECTORS, MVT::v32i8, Custom);
1048 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i16, Custom);
1050 setOperationAction(ISD::SRL, MVT::v16i16, Custom);
1051 setOperationAction(ISD::SRL, MVT::v32i8, Custom);
1053 setOperationAction(ISD::SHL, MVT::v16i16, Custom);
1054 setOperationAction(ISD::SHL, MVT::v32i8, Custom);
1056 setOperationAction(ISD::SRA, MVT::v16i16, Custom);
1057 setOperationAction(ISD::SRA, MVT::v32i8, Custom);
1059 setOperationAction(ISD::SETCC, MVT::v32i8, Custom);
1060 setOperationAction(ISD::SETCC, MVT::v16i16, Custom);
1061 setOperationAction(ISD::SETCC, MVT::v8i32, Custom);
1062 setOperationAction(ISD::SETCC, MVT::v4i64, Custom);
1064 setOperationAction(ISD::SELECT, MVT::v4f64, Custom);
1065 setOperationAction(ISD::SELECT, MVT::v4i64, Custom);
1066 setOperationAction(ISD::SELECT, MVT::v8f32, Custom);
1068 setOperationAction(ISD::VSELECT, MVT::v4f64, Legal);
1069 setOperationAction(ISD::VSELECT, MVT::v4i64, Legal);
1070 setOperationAction(ISD::VSELECT, MVT::v8i32, Legal);
1071 setOperationAction(ISD::VSELECT, MVT::v8f32, Legal);
1073 if (Subtarget->hasAVX2()) {
1074 setOperationAction(ISD::ADD, MVT::v4i64, Legal);
1075 setOperationAction(ISD::ADD, MVT::v8i32, Legal);
1076 setOperationAction(ISD::ADD, MVT::v16i16, Legal);
1077 setOperationAction(ISD::ADD, MVT::v32i8, Legal);
1079 setOperationAction(ISD::SUB, MVT::v4i64, Legal);
1080 setOperationAction(ISD::SUB, MVT::v8i32, Legal);
1081 setOperationAction(ISD::SUB, MVT::v16i16, Legal);
1082 setOperationAction(ISD::SUB, MVT::v32i8, Legal);
1084 setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1085 setOperationAction(ISD::MUL, MVT::v8i32, Legal);
1086 setOperationAction(ISD::MUL, MVT::v16i16, Legal);
1087 // Don't lower v32i8 because there is no 128-bit byte mul
1089 setOperationAction(ISD::VSELECT, MVT::v32i8, Legal);
1091 setOperationAction(ISD::SRL, MVT::v4i64, Legal);
1092 setOperationAction(ISD::SRL, MVT::v8i32, Legal);
1094 setOperationAction(ISD::SHL, MVT::v4i64, Legal);
1095 setOperationAction(ISD::SHL, MVT::v8i32, Legal);
1097 setOperationAction(ISD::SRA, MVT::v8i32, Legal);
1099 setOperationAction(ISD::ADD, MVT::v4i64, Custom);
1100 setOperationAction(ISD::ADD, MVT::v8i32, Custom);
1101 setOperationAction(ISD::ADD, MVT::v16i16, Custom);
1102 setOperationAction(ISD::ADD, MVT::v32i8, Custom);
1104 setOperationAction(ISD::SUB, MVT::v4i64, Custom);
1105 setOperationAction(ISD::SUB, MVT::v8i32, Custom);
1106 setOperationAction(ISD::SUB, MVT::v16i16, Custom);
1107 setOperationAction(ISD::SUB, MVT::v32i8, Custom);
1109 setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1110 setOperationAction(ISD::MUL, MVT::v8i32, Custom);
1111 setOperationAction(ISD::MUL, MVT::v16i16, Custom);
1112 // Don't lower v32i8 because there is no 128-bit byte mul
1114 setOperationAction(ISD::SRL, MVT::v4i64, Custom);
1115 setOperationAction(ISD::SRL, MVT::v8i32, Custom);
1117 setOperationAction(ISD::SHL, MVT::v4i64, Custom);
1118 setOperationAction(ISD::SHL, MVT::v8i32, Custom);
1120 setOperationAction(ISD::SRA, MVT::v8i32, Custom);
1123 // Custom lower several nodes for 256-bit types.
1124 for (unsigned i = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
1125 i <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++i) {
1126 MVT::SimpleValueType SVT = (MVT::SimpleValueType)i;
1129 // Extract subvector is special because the value type
1130 // (result) is 128-bit but the source is 256-bit wide.
1131 if (VT.is128BitVector())
1132 setOperationAction(ISD::EXTRACT_SUBVECTOR, SVT, Custom);
1134 // Do not attempt to custom lower other non-256-bit vectors
1135 if (!VT.is256BitVector())
1138 setOperationAction(ISD::BUILD_VECTOR, SVT, Custom);
1139 setOperationAction(ISD::VECTOR_SHUFFLE, SVT, Custom);
1140 setOperationAction(ISD::INSERT_VECTOR_ELT, SVT, Custom);
1141 setOperationAction(ISD::EXTRACT_VECTOR_ELT, SVT, Custom);
1142 setOperationAction(ISD::SCALAR_TO_VECTOR, SVT, Custom);
1143 setOperationAction(ISD::INSERT_SUBVECTOR, SVT, Custom);
1146 // Promote v32i8, v16i16, v8i32 select, and, or, xor to v4i64.
1147 for (unsigned i = (unsigned)MVT::v32i8; i != (unsigned)MVT::v4i64; ++i) {
1148 MVT::SimpleValueType SVT = (MVT::SimpleValueType)i;
1151 // Do not attempt to promote non-256-bit vectors
1152 if (!VT.is256BitVector())
1155 setOperationAction(ISD::AND, SVT, Promote);
1156 AddPromotedToType (ISD::AND, SVT, MVT::v4i64);
1157 setOperationAction(ISD::OR, SVT, Promote);
1158 AddPromotedToType (ISD::OR, SVT, MVT::v4i64);
1159 setOperationAction(ISD::XOR, SVT, Promote);
1160 AddPromotedToType (ISD::XOR, SVT, MVT::v4i64);
1161 setOperationAction(ISD::LOAD, SVT, Promote);
1162 AddPromotedToType (ISD::LOAD, SVT, MVT::v4i64);
1163 setOperationAction(ISD::SELECT, SVT, Promote);
1164 AddPromotedToType (ISD::SELECT, SVT, MVT::v4i64);
1168 // SIGN_EXTEND_INREGs are evaluated by the extend type. Handle the expansion
1169 // of this type with custom code.
1170 for (unsigned VT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
1171 VT != (unsigned)MVT::LAST_VECTOR_VALUETYPE; VT++) {
1172 setOperationAction(ISD::SIGN_EXTEND_INREG, (MVT::SimpleValueType)VT,
1176 // We want to custom lower some of our intrinsics.
1177 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
1180 // Only custom-lower 64-bit SADDO and friends on 64-bit because we don't
1181 // handle type legalization for these operations here.
1183 // FIXME: We really should do custom legalization for addition and
1184 // subtraction on x86-32 once PR3203 is fixed. We really can't do much better
1185 // than generic legalization for 64-bit multiplication-with-overflow, though.
1186 for (unsigned i = 0, e = 3+Subtarget->is64Bit(); i != e; ++i) {
1187 // Add/Sub/Mul with overflow operations are custom lowered.
1189 setOperationAction(ISD::SADDO, VT, Custom);
1190 setOperationAction(ISD::UADDO, VT, Custom);
1191 setOperationAction(ISD::SSUBO, VT, Custom);
1192 setOperationAction(ISD::USUBO, VT, Custom);
1193 setOperationAction(ISD::SMULO, VT, Custom);
1194 setOperationAction(ISD::UMULO, VT, Custom);
1197 // There are no 8-bit 3-address imul/mul instructions
1198 setOperationAction(ISD::SMULO, MVT::i8, Expand);
1199 setOperationAction(ISD::UMULO, MVT::i8, Expand);
1201 if (!Subtarget->is64Bit()) {
1202 // These libcalls are not available in 32-bit.
1203 setLibcallName(RTLIB::SHL_I128, 0);
1204 setLibcallName(RTLIB::SRL_I128, 0);
1205 setLibcallName(RTLIB::SRA_I128, 0);
1208 // We have target-specific dag combine patterns for the following nodes:
1209 setTargetDAGCombine(ISD::VECTOR_SHUFFLE);
1210 setTargetDAGCombine(ISD::EXTRACT_VECTOR_ELT);
1211 setTargetDAGCombine(ISD::VSELECT);
1212 setTargetDAGCombine(ISD::SELECT);
1213 setTargetDAGCombine(ISD::SHL);
1214 setTargetDAGCombine(ISD::SRA);
1215 setTargetDAGCombine(ISD::SRL);
1216 setTargetDAGCombine(ISD::OR);
1217 setTargetDAGCombine(ISD::AND);
1218 setTargetDAGCombine(ISD::ADD);
1219 setTargetDAGCombine(ISD::FADD);
1220 setTargetDAGCombine(ISD::FSUB);
1221 setTargetDAGCombine(ISD::SUB);
1222 setTargetDAGCombine(ISD::LOAD);
1223 setTargetDAGCombine(ISD::STORE);
1224 setTargetDAGCombine(ISD::ZERO_EXTEND);
1225 setTargetDAGCombine(ISD::ANY_EXTEND);
1226 setTargetDAGCombine(ISD::SIGN_EXTEND);
1227 setTargetDAGCombine(ISD::TRUNCATE);
1228 setTargetDAGCombine(ISD::SINT_TO_FP);
1229 if (Subtarget->is64Bit())
1230 setTargetDAGCombine(ISD::MUL);
1231 if (Subtarget->hasBMI())
1232 setTargetDAGCombine(ISD::XOR);
1234 computeRegisterProperties();
1236 // On Darwin, -Os means optimize for size without hurting performance,
1237 // do not reduce the limit.
1238 maxStoresPerMemset = 16; // For @llvm.memset -> sequence of stores
1239 maxStoresPerMemsetOptSize = Subtarget->isTargetDarwin() ? 16 : 8;
1240 maxStoresPerMemcpy = 8; // For @llvm.memcpy -> sequence of stores
1241 maxStoresPerMemcpyOptSize = Subtarget->isTargetDarwin() ? 8 : 4;
1242 maxStoresPerMemmove = 8; // For @llvm.memmove -> sequence of stores
1243 maxStoresPerMemmoveOptSize = Subtarget->isTargetDarwin() ? 8 : 4;
1244 setPrefLoopAlignment(4); // 2^4 bytes.
1245 benefitFromCodePlacementOpt = true;
1247 setPrefFunctionAlignment(4); // 2^4 bytes.
1251 EVT X86TargetLowering::getSetCCResultType(EVT VT) const {
1252 if (!VT.isVector()) return MVT::i8;
1253 return VT.changeVectorElementTypeToInteger();
1257 /// getMaxByValAlign - Helper for getByValTypeAlignment to determine
1258 /// the desired ByVal argument alignment.
1259 static void getMaxByValAlign(Type *Ty, unsigned &MaxAlign) {
1262 if (VectorType *VTy = dyn_cast<VectorType>(Ty)) {
1263 if (VTy->getBitWidth() == 128)
1265 } else if (ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
1266 unsigned EltAlign = 0;
1267 getMaxByValAlign(ATy->getElementType(), EltAlign);
1268 if (EltAlign > MaxAlign)
1269 MaxAlign = EltAlign;
1270 } else if (StructType *STy = dyn_cast<StructType>(Ty)) {
1271 for (unsigned i = 0, e = STy->getNumElements(); i != e; ++i) {
1272 unsigned EltAlign = 0;
1273 getMaxByValAlign(STy->getElementType(i), EltAlign);
1274 if (EltAlign > MaxAlign)
1275 MaxAlign = EltAlign;
1283 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
1284 /// function arguments in the caller parameter area. For X86, aggregates
1285 /// that contain SSE vectors are placed at 16-byte boundaries while the rest
1286 /// are at 4-byte boundaries.
1287 unsigned X86TargetLowering::getByValTypeAlignment(Type *Ty) const {
1288 if (Subtarget->is64Bit()) {
1289 // Max of 8 and alignment of type.
1290 unsigned TyAlign = TD->getABITypeAlignment(Ty);
1297 if (Subtarget->hasSSE1())
1298 getMaxByValAlign(Ty, Align);
1302 /// getOptimalMemOpType - Returns the target specific optimal type for load
1303 /// and store operations as a result of memset, memcpy, and memmove
1304 /// lowering. If DstAlign is zero that means it's safe to destination
1305 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
1306 /// means there isn't a need to check it against alignment requirement,
1307 /// probably because the source does not need to be loaded. If
1308 /// 'IsZeroVal' is true, that means it's safe to return a
1309 /// non-scalar-integer type, e.g. empty string source, constant, or loaded
1310 /// from memory. 'MemcpyStrSrc' indicates whether the memcpy source is
1311 /// constant so it does not need to be loaded.
1312 /// It returns EVT::Other if the type should be determined using generic
1313 /// target-independent logic.
1315 X86TargetLowering::getOptimalMemOpType(uint64_t Size,
1316 unsigned DstAlign, unsigned SrcAlign,
1319 MachineFunction &MF) const {
1320 // FIXME: This turns off use of xmm stores for memset/memcpy on targets like
1321 // linux. This is because the stack realignment code can't handle certain
1322 // cases like PR2962. This should be removed when PR2962 is fixed.
1323 const Function *F = MF.getFunction();
1325 !F->hasFnAttr(Attribute::NoImplicitFloat)) {
1327 (Subtarget->isUnalignedMemAccessFast() ||
1328 ((DstAlign == 0 || DstAlign >= 16) &&
1329 (SrcAlign == 0 || SrcAlign >= 16))) &&
1330 Subtarget->getStackAlignment() >= 16) {
1331 if (Subtarget->getStackAlignment() >= 32) {
1332 if (Subtarget->hasAVX2())
1334 if (Subtarget->hasAVX())
1337 if (Subtarget->hasSSE2())
1339 if (Subtarget->hasSSE1())
1341 } else if (!MemcpyStrSrc && Size >= 8 &&
1342 !Subtarget->is64Bit() &&
1343 Subtarget->getStackAlignment() >= 8 &&
1344 Subtarget->hasSSE2()) {
1345 // Do not use f64 to lower memcpy if source is string constant. It's
1346 // better to use i32 to avoid the loads.
1350 if (Subtarget->is64Bit() && Size >= 8)
1355 /// getJumpTableEncoding - Return the entry encoding for a jump table in the
1356 /// current function. The returned value is a member of the
1357 /// MachineJumpTableInfo::JTEntryKind enum.
1358 unsigned X86TargetLowering::getJumpTableEncoding() const {
1359 // In GOT pic mode, each entry in the jump table is emitted as a @GOTOFF
1361 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1362 Subtarget->isPICStyleGOT())
1363 return MachineJumpTableInfo::EK_Custom32;
1365 // Otherwise, use the normal jump table encoding heuristics.
1366 return TargetLowering::getJumpTableEncoding();
1370 X86TargetLowering::LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI,
1371 const MachineBasicBlock *MBB,
1372 unsigned uid,MCContext &Ctx) const{
1373 assert(getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1374 Subtarget->isPICStyleGOT());
1375 // In 32-bit ELF systems, our jump table entries are formed with @GOTOFF
1377 return MCSymbolRefExpr::Create(MBB->getSymbol(),
1378 MCSymbolRefExpr::VK_GOTOFF, Ctx);
1381 /// getPICJumpTableRelocaBase - Returns relocation base for the given PIC
1383 SDValue X86TargetLowering::getPICJumpTableRelocBase(SDValue Table,
1384 SelectionDAG &DAG) const {
1385 if (!Subtarget->is64Bit())
1386 // This doesn't have DebugLoc associated with it, but is not really the
1387 // same as a Register.
1388 return DAG.getNode(X86ISD::GlobalBaseReg, DebugLoc(), getPointerTy());
1392 /// getPICJumpTableRelocBaseExpr - This returns the relocation base for the
1393 /// given PIC jumptable, the same as getPICJumpTableRelocBase, but as an
1395 const MCExpr *X86TargetLowering::
1396 getPICJumpTableRelocBaseExpr(const MachineFunction *MF, unsigned JTI,
1397 MCContext &Ctx) const {
1398 // X86-64 uses RIP relative addressing based on the jump table label.
1399 if (Subtarget->isPICStyleRIPRel())
1400 return TargetLowering::getPICJumpTableRelocBaseExpr(MF, JTI, Ctx);
1402 // Otherwise, the reference is relative to the PIC base.
1403 return MCSymbolRefExpr::Create(MF->getPICBaseSymbol(), Ctx);
1406 // FIXME: Why this routine is here? Move to RegInfo!
1407 std::pair<const TargetRegisterClass*, uint8_t>
1408 X86TargetLowering::findRepresentativeClass(EVT VT) const{
1409 const TargetRegisterClass *RRC = 0;
1411 switch (VT.getSimpleVT().SimpleTy) {
1413 return TargetLowering::findRepresentativeClass(VT);
1414 case MVT::i8: case MVT::i16: case MVT::i32: case MVT::i64:
1415 RRC = Subtarget->is64Bit() ?
1416 (const TargetRegisterClass*)&X86::GR64RegClass :
1417 (const TargetRegisterClass*)&X86::GR32RegClass;
1420 RRC = &X86::VR64RegClass;
1422 case MVT::f32: case MVT::f64:
1423 case MVT::v16i8: case MVT::v8i16: case MVT::v4i32: case MVT::v2i64:
1424 case MVT::v4f32: case MVT::v2f64:
1425 case MVT::v32i8: case MVT::v8i32: case MVT::v4i64: case MVT::v8f32:
1427 RRC = &X86::VR128RegClass;
1430 return std::make_pair(RRC, Cost);
1433 bool X86TargetLowering::getStackCookieLocation(unsigned &AddressSpace,
1434 unsigned &Offset) const {
1435 if (!Subtarget->isTargetLinux())
1438 if (Subtarget->is64Bit()) {
1439 // %fs:0x28, unless we're using a Kernel code model, in which case it's %gs:
1441 if (getTargetMachine().getCodeModel() == CodeModel::Kernel)
1454 //===----------------------------------------------------------------------===//
1455 // Return Value Calling Convention Implementation
1456 //===----------------------------------------------------------------------===//
1458 #include "X86GenCallingConv.inc"
1461 X86TargetLowering::CanLowerReturn(CallingConv::ID CallConv,
1462 MachineFunction &MF, bool isVarArg,
1463 const SmallVectorImpl<ISD::OutputArg> &Outs,
1464 LLVMContext &Context) const {
1465 SmallVector<CCValAssign, 16> RVLocs;
1466 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(),
1468 return CCInfo.CheckReturn(Outs, RetCC_X86);
1472 X86TargetLowering::LowerReturn(SDValue Chain,
1473 CallingConv::ID CallConv, bool isVarArg,
1474 const SmallVectorImpl<ISD::OutputArg> &Outs,
1475 const SmallVectorImpl<SDValue> &OutVals,
1476 DebugLoc dl, SelectionDAG &DAG) const {
1477 MachineFunction &MF = DAG.getMachineFunction();
1478 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1480 SmallVector<CCValAssign, 16> RVLocs;
1481 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(),
1482 RVLocs, *DAG.getContext());
1483 CCInfo.AnalyzeReturn(Outs, RetCC_X86);
1485 // Add the regs to the liveout set for the function.
1486 MachineRegisterInfo &MRI = DAG.getMachineFunction().getRegInfo();
1487 for (unsigned i = 0; i != RVLocs.size(); ++i)
1488 if (RVLocs[i].isRegLoc() && !MRI.isLiveOut(RVLocs[i].getLocReg()))
1489 MRI.addLiveOut(RVLocs[i].getLocReg());
1493 SmallVector<SDValue, 6> RetOps;
1494 RetOps.push_back(Chain); // Operand #0 = Chain (updated below)
1495 // Operand #1 = Bytes To Pop
1496 RetOps.push_back(DAG.getTargetConstant(FuncInfo->getBytesToPopOnReturn(),
1499 // Copy the result values into the output registers.
1500 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1501 CCValAssign &VA = RVLocs[i];
1502 assert(VA.isRegLoc() && "Can only return in registers!");
1503 SDValue ValToCopy = OutVals[i];
1504 EVT ValVT = ValToCopy.getValueType();
1506 // If this is x86-64, and we disabled SSE, we can't return FP values,
1507 // or SSE or MMX vectors.
1508 if ((ValVT == MVT::f32 || ValVT == MVT::f64 ||
1509 VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) &&
1510 (Subtarget->is64Bit() && !Subtarget->hasSSE1())) {
1511 report_fatal_error("SSE register return with SSE disabled");
1513 // Likewise we can't return F64 values with SSE1 only. gcc does so, but
1514 // llvm-gcc has never done it right and no one has noticed, so this
1515 // should be OK for now.
1516 if (ValVT == MVT::f64 &&
1517 (Subtarget->is64Bit() && !Subtarget->hasSSE2()))
1518 report_fatal_error("SSE2 register return with SSE2 disabled");
1520 // Returns in ST0/ST1 are handled specially: these are pushed as operands to
1521 // the RET instruction and handled by the FP Stackifier.
1522 if (VA.getLocReg() == X86::ST0 ||
1523 VA.getLocReg() == X86::ST1) {
1524 // If this is a copy from an xmm register to ST(0), use an FPExtend to
1525 // change the value to the FP stack register class.
1526 if (isScalarFPTypeInSSEReg(VA.getValVT()))
1527 ValToCopy = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f80, ValToCopy);
1528 RetOps.push_back(ValToCopy);
1529 // Don't emit a copytoreg.
1533 // 64-bit vector (MMX) values are returned in XMM0 / XMM1 except for v1i64
1534 // which is returned in RAX / RDX.
1535 if (Subtarget->is64Bit()) {
1536 if (ValVT == MVT::x86mmx) {
1537 if (VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) {
1538 ValToCopy = DAG.getNode(ISD::BITCAST, dl, MVT::i64, ValToCopy);
1539 ValToCopy = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
1541 // If we don't have SSE2 available, convert to v4f32 so the generated
1542 // register is legal.
1543 if (!Subtarget->hasSSE2())
1544 ValToCopy = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32,ValToCopy);
1549 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), ValToCopy, Flag);
1550 Flag = Chain.getValue(1);
1553 // The x86-64 ABI for returning structs by value requires that we copy
1554 // the sret argument into %rax for the return. We saved the argument into
1555 // a virtual register in the entry block, so now we copy the value out
1557 if (Subtarget->is64Bit() &&
1558 DAG.getMachineFunction().getFunction()->hasStructRetAttr()) {
1559 MachineFunction &MF = DAG.getMachineFunction();
1560 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1561 unsigned Reg = FuncInfo->getSRetReturnReg();
1563 "SRetReturnReg should have been set in LowerFormalArguments().");
1564 SDValue Val = DAG.getCopyFromReg(Chain, dl, Reg, getPointerTy());
1566 Chain = DAG.getCopyToReg(Chain, dl, X86::RAX, Val, Flag);
1567 Flag = Chain.getValue(1);
1569 // RAX now acts like a return value.
1570 MRI.addLiveOut(X86::RAX);
1573 RetOps[0] = Chain; // Update chain.
1575 // Add the flag if we have it.
1577 RetOps.push_back(Flag);
1579 return DAG.getNode(X86ISD::RET_FLAG, dl,
1580 MVT::Other, &RetOps[0], RetOps.size());
1583 bool X86TargetLowering::isUsedByReturnOnly(SDNode *N, SDValue &Chain) const {
1584 if (N->getNumValues() != 1)
1586 if (!N->hasNUsesOfValue(1, 0))
1589 SDValue TCChain = Chain;
1590 SDNode *Copy = *N->use_begin();
1591 if (Copy->getOpcode() == ISD::CopyToReg) {
1592 // If the copy has a glue operand, we conservatively assume it isn't safe to
1593 // perform a tail call.
1594 if (Copy->getOperand(Copy->getNumOperands()-1).getValueType() == MVT::Glue)
1596 TCChain = Copy->getOperand(0);
1597 } else if (Copy->getOpcode() != ISD::FP_EXTEND)
1600 bool HasRet = false;
1601 for (SDNode::use_iterator UI = Copy->use_begin(), UE = Copy->use_end();
1603 if (UI->getOpcode() != X86ISD::RET_FLAG)
1616 X86TargetLowering::getTypeForExtArgOrReturn(LLVMContext &Context, EVT VT,
1617 ISD::NodeType ExtendKind) const {
1619 // TODO: Is this also valid on 32-bit?
1620 if (Subtarget->is64Bit() && VT == MVT::i1 && ExtendKind == ISD::ZERO_EXTEND)
1621 ReturnMVT = MVT::i8;
1623 ReturnMVT = MVT::i32;
1625 EVT MinVT = getRegisterType(Context, ReturnMVT);
1626 return VT.bitsLT(MinVT) ? MinVT : VT;
1629 /// LowerCallResult - Lower the result values of a call into the
1630 /// appropriate copies out of appropriate physical registers.
1633 X86TargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
1634 CallingConv::ID CallConv, bool isVarArg,
1635 const SmallVectorImpl<ISD::InputArg> &Ins,
1636 DebugLoc dl, SelectionDAG &DAG,
1637 SmallVectorImpl<SDValue> &InVals) const {
1639 // Assign locations to each value returned by this call.
1640 SmallVector<CCValAssign, 16> RVLocs;
1641 bool Is64Bit = Subtarget->is64Bit();
1642 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
1643 getTargetMachine(), RVLocs, *DAG.getContext());
1644 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
1646 // Copy all of the result registers out of their specified physreg.
1647 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1648 CCValAssign &VA = RVLocs[i];
1649 EVT CopyVT = VA.getValVT();
1651 // If this is x86-64, and we disabled SSE, we can't return FP values
1652 if ((CopyVT == MVT::f32 || CopyVT == MVT::f64) &&
1653 ((Is64Bit || Ins[i].Flags.isInReg()) && !Subtarget->hasSSE1())) {
1654 report_fatal_error("SSE register return with SSE disabled");
1659 // If this is a call to a function that returns an fp value on the floating
1660 // point stack, we must guarantee the the value is popped from the stack, so
1661 // a CopyFromReg is not good enough - the copy instruction may be eliminated
1662 // if the return value is not used. We use the FpPOP_RETVAL instruction
1664 if (VA.getLocReg() == X86::ST0 || VA.getLocReg() == X86::ST1) {
1665 // If we prefer to use the value in xmm registers, copy it out as f80 and
1666 // use a truncate to move it from fp stack reg to xmm reg.
1667 if (isScalarFPTypeInSSEReg(VA.getValVT())) CopyVT = MVT::f80;
1668 SDValue Ops[] = { Chain, InFlag };
1669 Chain = SDValue(DAG.getMachineNode(X86::FpPOP_RETVAL, dl, CopyVT,
1670 MVT::Other, MVT::Glue, Ops, 2), 1);
1671 Val = Chain.getValue(0);
1673 // Round the f80 to the right size, which also moves it to the appropriate
1675 if (CopyVT != VA.getValVT())
1676 Val = DAG.getNode(ISD::FP_ROUND, dl, VA.getValVT(), Val,
1677 // This truncation won't change the value.
1678 DAG.getIntPtrConstant(1));
1680 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(),
1681 CopyVT, InFlag).getValue(1);
1682 Val = Chain.getValue(0);
1684 InFlag = Chain.getValue(2);
1685 InVals.push_back(Val);
1692 //===----------------------------------------------------------------------===//
1693 // C & StdCall & Fast Calling Convention implementation
1694 //===----------------------------------------------------------------------===//
1695 // StdCall calling convention seems to be standard for many Windows' API
1696 // routines and around. It differs from C calling convention just a little:
1697 // callee should clean up the stack, not caller. Symbols should be also
1698 // decorated in some fancy way :) It doesn't support any vector arguments.
1699 // For info on fast calling convention see Fast Calling Convention (tail call)
1700 // implementation LowerX86_32FastCCCallTo.
1702 /// CallIsStructReturn - Determines whether a call uses struct return
1704 static bool CallIsStructReturn(const SmallVectorImpl<ISD::OutputArg> &Outs) {
1708 return Outs[0].Flags.isSRet();
1711 /// ArgsAreStructReturn - Determines whether a function uses struct
1712 /// return semantics.
1714 ArgsAreStructReturn(const SmallVectorImpl<ISD::InputArg> &Ins) {
1718 return Ins[0].Flags.isSRet();
1721 /// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified
1722 /// by "Src" to address "Dst" with size and alignment information specified by
1723 /// the specific parameter attribute. The copy will be passed as a byval
1724 /// function parameter.
1726 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
1727 ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
1729 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32);
1731 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
1732 /*isVolatile*/false, /*AlwaysInline=*/true,
1733 MachinePointerInfo(), MachinePointerInfo());
1736 /// IsTailCallConvention - Return true if the calling convention is one that
1737 /// supports tail call optimization.
1738 static bool IsTailCallConvention(CallingConv::ID CC) {
1739 return (CC == CallingConv::Fast || CC == CallingConv::GHC);
1742 bool X86TargetLowering::mayBeEmittedAsTailCall(CallInst *CI) const {
1743 if (!CI->isTailCall() || getTargetMachine().Options.DisableTailCalls)
1747 CallingConv::ID CalleeCC = CS.getCallingConv();
1748 if (!IsTailCallConvention(CalleeCC) && CalleeCC != CallingConv::C)
1754 /// FuncIsMadeTailCallSafe - Return true if the function is being made into
1755 /// a tailcall target by changing its ABI.
1756 static bool FuncIsMadeTailCallSafe(CallingConv::ID CC,
1757 bool GuaranteedTailCallOpt) {
1758 return GuaranteedTailCallOpt && IsTailCallConvention(CC);
1762 X86TargetLowering::LowerMemArgument(SDValue Chain,
1763 CallingConv::ID CallConv,
1764 const SmallVectorImpl<ISD::InputArg> &Ins,
1765 DebugLoc dl, SelectionDAG &DAG,
1766 const CCValAssign &VA,
1767 MachineFrameInfo *MFI,
1769 // Create the nodes corresponding to a load from this parameter slot.
1770 ISD::ArgFlagsTy Flags = Ins[i].Flags;
1771 bool AlwaysUseMutable = FuncIsMadeTailCallSafe(CallConv,
1772 getTargetMachine().Options.GuaranteedTailCallOpt);
1773 bool isImmutable = !AlwaysUseMutable && !Flags.isByVal();
1776 // If value is passed by pointer we have address passed instead of the value
1778 if (VA.getLocInfo() == CCValAssign::Indirect)
1779 ValVT = VA.getLocVT();
1781 ValVT = VA.getValVT();
1783 // FIXME: For now, all byval parameter objects are marked mutable. This can be
1784 // changed with more analysis.
1785 // In case of tail call optimization mark all arguments mutable. Since they
1786 // could be overwritten by lowering of arguments in case of a tail call.
1787 if (Flags.isByVal()) {
1788 unsigned Bytes = Flags.getByValSize();
1789 if (Bytes == 0) Bytes = 1; // Don't create zero-sized stack objects.
1790 int FI = MFI->CreateFixedObject(Bytes, VA.getLocMemOffset(), isImmutable);
1791 return DAG.getFrameIndex(FI, getPointerTy());
1793 int FI = MFI->CreateFixedObject(ValVT.getSizeInBits()/8,
1794 VA.getLocMemOffset(), isImmutable);
1795 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
1796 return DAG.getLoad(ValVT, dl, Chain, FIN,
1797 MachinePointerInfo::getFixedStack(FI),
1798 false, false, false, 0);
1803 X86TargetLowering::LowerFormalArguments(SDValue Chain,
1804 CallingConv::ID CallConv,
1806 const SmallVectorImpl<ISD::InputArg> &Ins,
1809 SmallVectorImpl<SDValue> &InVals)
1811 MachineFunction &MF = DAG.getMachineFunction();
1812 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1814 const Function* Fn = MF.getFunction();
1815 if (Fn->hasExternalLinkage() &&
1816 Subtarget->isTargetCygMing() &&
1817 Fn->getName() == "main")
1818 FuncInfo->setForceFramePointer(true);
1820 MachineFrameInfo *MFI = MF.getFrameInfo();
1821 bool Is64Bit = Subtarget->is64Bit();
1822 bool IsWindows = Subtarget->isTargetWindows();
1823 bool IsWin64 = Subtarget->isTargetWin64();
1825 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
1826 "Var args not supported with calling convention fastcc or ghc");
1828 // Assign locations to all of the incoming arguments.
1829 SmallVector<CCValAssign, 16> ArgLocs;
1830 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(),
1831 ArgLocs, *DAG.getContext());
1833 // Allocate shadow area for Win64
1835 CCInfo.AllocateStack(32, 8);
1838 CCInfo.AnalyzeFormalArguments(Ins, CC_X86);
1840 unsigned LastVal = ~0U;
1842 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1843 CCValAssign &VA = ArgLocs[i];
1844 // TODO: If an arg is passed in two places (e.g. reg and stack), skip later
1846 assert(VA.getValNo() != LastVal &&
1847 "Don't support value assigned to multiple locs yet");
1849 LastVal = VA.getValNo();
1851 if (VA.isRegLoc()) {
1852 EVT RegVT = VA.getLocVT();
1853 const TargetRegisterClass *RC;
1854 if (RegVT == MVT::i32)
1855 RC = &X86::GR32RegClass;
1856 else if (Is64Bit && RegVT == MVT::i64)
1857 RC = &X86::GR64RegClass;
1858 else if (RegVT == MVT::f32)
1859 RC = &X86::FR32RegClass;
1860 else if (RegVT == MVT::f64)
1861 RC = &X86::FR64RegClass;
1862 else if (RegVT.isVector() && RegVT.getSizeInBits() == 256)
1863 RC = &X86::VR256RegClass;
1864 else if (RegVT.isVector() && RegVT.getSizeInBits() == 128)
1865 RC = &X86::VR128RegClass;
1866 else if (RegVT == MVT::x86mmx)
1867 RC = &X86::VR64RegClass;
1869 llvm_unreachable("Unknown argument type!");
1871 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
1872 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
1874 // If this is an 8 or 16-bit value, it is really passed promoted to 32
1875 // bits. Insert an assert[sz]ext to capture this, then truncate to the
1877 if (VA.getLocInfo() == CCValAssign::SExt)
1878 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
1879 DAG.getValueType(VA.getValVT()));
1880 else if (VA.getLocInfo() == CCValAssign::ZExt)
1881 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
1882 DAG.getValueType(VA.getValVT()));
1883 else if (VA.getLocInfo() == CCValAssign::BCvt)
1884 ArgValue = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), ArgValue);
1886 if (VA.isExtInLoc()) {
1887 // Handle MMX values passed in XMM regs.
1888 if (RegVT.isVector()) {
1889 ArgValue = DAG.getNode(X86ISD::MOVDQ2Q, dl, VA.getValVT(),
1892 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
1895 assert(VA.isMemLoc());
1896 ArgValue = LowerMemArgument(Chain, CallConv, Ins, dl, DAG, VA, MFI, i);
1899 // If value is passed via pointer - do a load.
1900 if (VA.getLocInfo() == CCValAssign::Indirect)
1901 ArgValue = DAG.getLoad(VA.getValVT(), dl, Chain, ArgValue,
1902 MachinePointerInfo(), false, false, false, 0);
1904 InVals.push_back(ArgValue);
1907 // The x86-64 ABI for returning structs by value requires that we copy
1908 // the sret argument into %rax for the return. Save the argument into
1909 // a virtual register so that we can access it from the return points.
1910 if (Is64Bit && MF.getFunction()->hasStructRetAttr()) {
1911 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1912 unsigned Reg = FuncInfo->getSRetReturnReg();
1914 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(MVT::i64));
1915 FuncInfo->setSRetReturnReg(Reg);
1917 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, InVals[0]);
1918 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain);
1921 unsigned StackSize = CCInfo.getNextStackOffset();
1922 // Align stack specially for tail calls.
1923 if (FuncIsMadeTailCallSafe(CallConv,
1924 MF.getTarget().Options.GuaranteedTailCallOpt))
1925 StackSize = GetAlignedArgumentStackSize(StackSize, DAG);
1927 // If the function takes variable number of arguments, make a frame index for
1928 // the start of the first vararg value... for expansion of llvm.va_start.
1930 if (Is64Bit || (CallConv != CallingConv::X86_FastCall &&
1931 CallConv != CallingConv::X86_ThisCall)) {
1932 FuncInfo->setVarArgsFrameIndex(MFI->CreateFixedObject(1, StackSize,true));
1935 unsigned TotalNumIntRegs = 0, TotalNumXMMRegs = 0;
1937 // FIXME: We should really autogenerate these arrays
1938 static const uint16_t GPR64ArgRegsWin64[] = {
1939 X86::RCX, X86::RDX, X86::R8, X86::R9
1941 static const uint16_t GPR64ArgRegs64Bit[] = {
1942 X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9
1944 static const uint16_t XMMArgRegs64Bit[] = {
1945 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
1946 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
1948 const uint16_t *GPR64ArgRegs;
1949 unsigned NumXMMRegs = 0;
1952 // The XMM registers which might contain var arg parameters are shadowed
1953 // in their paired GPR. So we only need to save the GPR to their home
1955 TotalNumIntRegs = 4;
1956 GPR64ArgRegs = GPR64ArgRegsWin64;
1958 TotalNumIntRegs = 6; TotalNumXMMRegs = 8;
1959 GPR64ArgRegs = GPR64ArgRegs64Bit;
1961 NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs64Bit,
1964 unsigned NumIntRegs = CCInfo.getFirstUnallocated(GPR64ArgRegs,
1967 bool NoImplicitFloatOps = Fn->hasFnAttr(Attribute::NoImplicitFloat);
1968 assert(!(NumXMMRegs && !Subtarget->hasSSE1()) &&
1969 "SSE register cannot be used when SSE is disabled!");
1970 assert(!(NumXMMRegs && MF.getTarget().Options.UseSoftFloat &&
1971 NoImplicitFloatOps) &&
1972 "SSE register cannot be used when SSE is disabled!");
1973 if (MF.getTarget().Options.UseSoftFloat || NoImplicitFloatOps ||
1974 !Subtarget->hasSSE1())
1975 // Kernel mode asks for SSE to be disabled, so don't push them
1977 TotalNumXMMRegs = 0;
1980 const TargetFrameLowering &TFI = *getTargetMachine().getFrameLowering();
1981 // Get to the caller-allocated home save location. Add 8 to account
1982 // for the return address.
1983 int HomeOffset = TFI.getOffsetOfLocalArea() + 8;
1984 FuncInfo->setRegSaveFrameIndex(
1985 MFI->CreateFixedObject(1, NumIntRegs * 8 + HomeOffset, false));
1986 // Fixup to set vararg frame on shadow area (4 x i64).
1988 FuncInfo->setVarArgsFrameIndex(FuncInfo->getRegSaveFrameIndex());
1990 // For X86-64, if there are vararg parameters that are passed via
1991 // registers, then we must store them to their spots on the stack so
1992 // they may be loaded by deferencing the result of va_next.
1993 FuncInfo->setVarArgsGPOffset(NumIntRegs * 8);
1994 FuncInfo->setVarArgsFPOffset(TotalNumIntRegs * 8 + NumXMMRegs * 16);
1995 FuncInfo->setRegSaveFrameIndex(
1996 MFI->CreateStackObject(TotalNumIntRegs * 8 + TotalNumXMMRegs * 16, 16,
2000 // Store the integer parameter registers.
2001 SmallVector<SDValue, 8> MemOps;
2002 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
2004 unsigned Offset = FuncInfo->getVarArgsGPOffset();
2005 for (; NumIntRegs != TotalNumIntRegs; ++NumIntRegs) {
2006 SDValue FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), RSFIN,
2007 DAG.getIntPtrConstant(Offset));
2008 unsigned VReg = MF.addLiveIn(GPR64ArgRegs[NumIntRegs],
2009 &X86::GR64RegClass);
2010 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64);
2012 DAG.getStore(Val.getValue(1), dl, Val, FIN,
2013 MachinePointerInfo::getFixedStack(
2014 FuncInfo->getRegSaveFrameIndex(), Offset),
2016 MemOps.push_back(Store);
2020 if (TotalNumXMMRegs != 0 && NumXMMRegs != TotalNumXMMRegs) {
2021 // Now store the XMM (fp + vector) parameter registers.
2022 SmallVector<SDValue, 11> SaveXMMOps;
2023 SaveXMMOps.push_back(Chain);
2025 unsigned AL = MF.addLiveIn(X86::AL, &X86::GR8RegClass);
2026 SDValue ALVal = DAG.getCopyFromReg(DAG.getEntryNode(), dl, AL, MVT::i8);
2027 SaveXMMOps.push_back(ALVal);
2029 SaveXMMOps.push_back(DAG.getIntPtrConstant(
2030 FuncInfo->getRegSaveFrameIndex()));
2031 SaveXMMOps.push_back(DAG.getIntPtrConstant(
2032 FuncInfo->getVarArgsFPOffset()));
2034 for (; NumXMMRegs != TotalNumXMMRegs; ++NumXMMRegs) {
2035 unsigned VReg = MF.addLiveIn(XMMArgRegs64Bit[NumXMMRegs],
2036 &X86::VR128RegClass);
2037 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::v4f32);
2038 SaveXMMOps.push_back(Val);
2040 MemOps.push_back(DAG.getNode(X86ISD::VASTART_SAVE_XMM_REGS, dl,
2042 &SaveXMMOps[0], SaveXMMOps.size()));
2045 if (!MemOps.empty())
2046 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
2047 &MemOps[0], MemOps.size());
2051 // Some CCs need callee pop.
2052 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg,
2053 MF.getTarget().Options.GuaranteedTailCallOpt)) {
2054 FuncInfo->setBytesToPopOnReturn(StackSize); // Callee pops everything.
2056 FuncInfo->setBytesToPopOnReturn(0); // Callee pops nothing.
2057 // If this is an sret function, the return should pop the hidden pointer.
2058 if (!Is64Bit && !IsTailCallConvention(CallConv) && !IsWindows &&
2059 ArgsAreStructReturn(Ins))
2060 FuncInfo->setBytesToPopOnReturn(4);
2064 // RegSaveFrameIndex is X86-64 only.
2065 FuncInfo->setRegSaveFrameIndex(0xAAAAAAA);
2066 if (CallConv == CallingConv::X86_FastCall ||
2067 CallConv == CallingConv::X86_ThisCall)
2068 // fastcc functions can't have varargs.
2069 FuncInfo->setVarArgsFrameIndex(0xAAAAAAA);
2072 FuncInfo->setArgumentStackSize(StackSize);
2078 X86TargetLowering::LowerMemOpCallTo(SDValue Chain,
2079 SDValue StackPtr, SDValue Arg,
2080 DebugLoc dl, SelectionDAG &DAG,
2081 const CCValAssign &VA,
2082 ISD::ArgFlagsTy Flags) const {
2083 unsigned LocMemOffset = VA.getLocMemOffset();
2084 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
2085 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
2086 if (Flags.isByVal())
2087 return CreateCopyOfByValArgument(Arg, PtrOff, Chain, Flags, DAG, dl);
2089 return DAG.getStore(Chain, dl, Arg, PtrOff,
2090 MachinePointerInfo::getStack(LocMemOffset),
2094 /// EmitTailCallLoadRetAddr - Emit a load of return address if tail call
2095 /// optimization is performed and it is required.
2097 X86TargetLowering::EmitTailCallLoadRetAddr(SelectionDAG &DAG,
2098 SDValue &OutRetAddr, SDValue Chain,
2099 bool IsTailCall, bool Is64Bit,
2100 int FPDiff, DebugLoc dl) const {
2101 // Adjust the Return address stack slot.
2102 EVT VT = getPointerTy();
2103 OutRetAddr = getReturnAddressFrameIndex(DAG);
2105 // Load the "old" Return address.
2106 OutRetAddr = DAG.getLoad(VT, dl, Chain, OutRetAddr, MachinePointerInfo(),
2107 false, false, false, 0);
2108 return SDValue(OutRetAddr.getNode(), 1);
2111 /// EmitTailCallStoreRetAddr - Emit a store of the return address if tail call
2112 /// optimization is performed and it is required (FPDiff!=0).
2114 EmitTailCallStoreRetAddr(SelectionDAG & DAG, MachineFunction &MF,
2115 SDValue Chain, SDValue RetAddrFrIdx,
2116 bool Is64Bit, int FPDiff, DebugLoc dl) {
2117 // Store the return address to the appropriate stack slot.
2118 if (!FPDiff) return Chain;
2119 // Calculate the new stack slot for the return address.
2120 int SlotSize = Is64Bit ? 8 : 4;
2121 int NewReturnAddrFI =
2122 MF.getFrameInfo()->CreateFixedObject(SlotSize, FPDiff-SlotSize, false);
2123 EVT VT = Is64Bit ? MVT::i64 : MVT::i32;
2124 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewReturnAddrFI, VT);
2125 Chain = DAG.getStore(Chain, dl, RetAddrFrIdx, NewRetAddrFrIdx,
2126 MachinePointerInfo::getFixedStack(NewReturnAddrFI),
2132 X86TargetLowering::LowerCall(SDValue Chain, SDValue Callee,
2133 CallingConv::ID CallConv, bool isVarArg,
2134 bool doesNotRet, bool &isTailCall,
2135 const SmallVectorImpl<ISD::OutputArg> &Outs,
2136 const SmallVectorImpl<SDValue> &OutVals,
2137 const SmallVectorImpl<ISD::InputArg> &Ins,
2138 DebugLoc dl, SelectionDAG &DAG,
2139 SmallVectorImpl<SDValue> &InVals) const {
2140 MachineFunction &MF = DAG.getMachineFunction();
2141 bool Is64Bit = Subtarget->is64Bit();
2142 bool IsWin64 = Subtarget->isTargetWin64();
2143 bool IsWindows = Subtarget->isTargetWindows();
2144 bool IsStructRet = CallIsStructReturn(Outs);
2145 bool IsSibcall = false;
2147 if (MF.getTarget().Options.DisableTailCalls)
2151 // Check if it's really possible to do a tail call.
2152 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv,
2153 isVarArg, IsStructRet, MF.getFunction()->hasStructRetAttr(),
2154 Outs, OutVals, Ins, DAG);
2156 // Sibcalls are automatically detected tailcalls which do not require
2158 if (!MF.getTarget().Options.GuaranteedTailCallOpt && isTailCall)
2165 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
2166 "Var args not supported with calling convention fastcc or ghc");
2168 // Analyze operands of the call, assigning locations to each operand.
2169 SmallVector<CCValAssign, 16> ArgLocs;
2170 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(),
2171 ArgLocs, *DAG.getContext());
2173 // Allocate shadow area for Win64
2175 CCInfo.AllocateStack(32, 8);
2178 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
2180 // Get a count of how many bytes are to be pushed on the stack.
2181 unsigned NumBytes = CCInfo.getNextStackOffset();
2183 // This is a sibcall. The memory operands are available in caller's
2184 // own caller's stack.
2186 else if (getTargetMachine().Options.GuaranteedTailCallOpt &&
2187 IsTailCallConvention(CallConv))
2188 NumBytes = GetAlignedArgumentStackSize(NumBytes, DAG);
2191 if (isTailCall && !IsSibcall) {
2192 // Lower arguments at fp - stackoffset + fpdiff.
2193 unsigned NumBytesCallerPushed =
2194 MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn();
2195 FPDiff = NumBytesCallerPushed - NumBytes;
2197 // Set the delta of movement of the returnaddr stackslot.
2198 // But only set if delta is greater than previous delta.
2199 if (FPDiff < (MF.getInfo<X86MachineFunctionInfo>()->getTCReturnAddrDelta()))
2200 MF.getInfo<X86MachineFunctionInfo>()->setTCReturnAddrDelta(FPDiff);
2204 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true));
2206 SDValue RetAddrFrIdx;
2207 // Load return address for tail calls.
2208 if (isTailCall && FPDiff)
2209 Chain = EmitTailCallLoadRetAddr(DAG, RetAddrFrIdx, Chain, isTailCall,
2210 Is64Bit, FPDiff, dl);
2212 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
2213 SmallVector<SDValue, 8> MemOpChains;
2216 // Walk the register/memloc assignments, inserting copies/loads. In the case
2217 // of tail call optimization arguments are handle later.
2218 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2219 CCValAssign &VA = ArgLocs[i];
2220 EVT RegVT = VA.getLocVT();
2221 SDValue Arg = OutVals[i];
2222 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2223 bool isByVal = Flags.isByVal();
2225 // Promote the value if needed.
2226 switch (VA.getLocInfo()) {
2227 default: llvm_unreachable("Unknown loc info!");
2228 case CCValAssign::Full: break;
2229 case CCValAssign::SExt:
2230 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, RegVT, Arg);
2232 case CCValAssign::ZExt:
2233 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, RegVT, Arg);
2235 case CCValAssign::AExt:
2236 if (RegVT.isVector() && RegVT.getSizeInBits() == 128) {
2237 // Special case: passing MMX values in XMM registers.
2238 Arg = DAG.getNode(ISD::BITCAST, dl, MVT::i64, Arg);
2239 Arg = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, Arg);
2240 Arg = getMOVL(DAG, dl, MVT::v2i64, DAG.getUNDEF(MVT::v2i64), Arg);
2242 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, RegVT, Arg);
2244 case CCValAssign::BCvt:
2245 Arg = DAG.getNode(ISD::BITCAST, dl, RegVT, Arg);
2247 case CCValAssign::Indirect: {
2248 // Store the argument.
2249 SDValue SpillSlot = DAG.CreateStackTemporary(VA.getValVT());
2250 int FI = cast<FrameIndexSDNode>(SpillSlot)->getIndex();
2251 Chain = DAG.getStore(Chain, dl, Arg, SpillSlot,
2252 MachinePointerInfo::getFixedStack(FI),
2259 if (VA.isRegLoc()) {
2260 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
2261 if (isVarArg && IsWin64) {
2262 // Win64 ABI requires argument XMM reg to be copied to the corresponding
2263 // shadow reg if callee is a varargs function.
2264 unsigned ShadowReg = 0;
2265 switch (VA.getLocReg()) {
2266 case X86::XMM0: ShadowReg = X86::RCX; break;
2267 case X86::XMM1: ShadowReg = X86::RDX; break;
2268 case X86::XMM2: ShadowReg = X86::R8; break;
2269 case X86::XMM3: ShadowReg = X86::R9; break;
2272 RegsToPass.push_back(std::make_pair(ShadowReg, Arg));
2274 } else if (!IsSibcall && (!isTailCall || isByVal)) {
2275 assert(VA.isMemLoc());
2276 if (StackPtr.getNode() == 0)
2277 StackPtr = DAG.getCopyFromReg(Chain, dl, X86StackPtr, getPointerTy());
2278 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Arg,
2279 dl, DAG, VA, Flags));
2283 if (!MemOpChains.empty())
2284 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
2285 &MemOpChains[0], MemOpChains.size());
2287 // Build a sequence of copy-to-reg nodes chained together with token chain
2288 // and flag operands which copy the outgoing args into registers.
2290 // Tail call byval lowering might overwrite argument registers so in case of
2291 // tail call optimization the copies to registers are lowered later.
2293 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
2294 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
2295 RegsToPass[i].second, InFlag);
2296 InFlag = Chain.getValue(1);
2299 if (Subtarget->isPICStyleGOT()) {
2300 // ELF / PIC requires GOT in the EBX register before function calls via PLT
2303 Chain = DAG.getCopyToReg(Chain, dl, X86::EBX,
2304 DAG.getNode(X86ISD::GlobalBaseReg,
2305 DebugLoc(), getPointerTy()),
2307 InFlag = Chain.getValue(1);
2309 // If we are tail calling and generating PIC/GOT style code load the
2310 // address of the callee into ECX. The value in ecx is used as target of
2311 // the tail jump. This is done to circumvent the ebx/callee-saved problem
2312 // for tail calls on PIC/GOT architectures. Normally we would just put the
2313 // address of GOT into ebx and then call target@PLT. But for tail calls
2314 // ebx would be restored (since ebx is callee saved) before jumping to the
2317 // Note: The actual moving to ECX is done further down.
2318 GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee);
2319 if (G && !G->getGlobal()->hasHiddenVisibility() &&
2320 !G->getGlobal()->hasProtectedVisibility())
2321 Callee = LowerGlobalAddress(Callee, DAG);
2322 else if (isa<ExternalSymbolSDNode>(Callee))
2323 Callee = LowerExternalSymbol(Callee, DAG);
2327 if (Is64Bit && isVarArg && !IsWin64) {
2328 // From AMD64 ABI document:
2329 // For calls that may call functions that use varargs or stdargs
2330 // (prototype-less calls or calls to functions containing ellipsis (...) in
2331 // the declaration) %al is used as hidden argument to specify the number
2332 // of SSE registers used. The contents of %al do not need to match exactly
2333 // the number of registers, but must be an ubound on the number of SSE
2334 // registers used and is in the range 0 - 8 inclusive.
2336 // Count the number of XMM registers allocated.
2337 static const uint16_t XMMArgRegs[] = {
2338 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
2339 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
2341 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs, 8);
2342 assert((Subtarget->hasSSE1() || !NumXMMRegs)
2343 && "SSE registers cannot be used when SSE is disabled");
2345 Chain = DAG.getCopyToReg(Chain, dl, X86::AL,
2346 DAG.getConstant(NumXMMRegs, MVT::i8), InFlag);
2347 InFlag = Chain.getValue(1);
2351 // For tail calls lower the arguments to the 'real' stack slot.
2353 // Force all the incoming stack arguments to be loaded from the stack
2354 // before any new outgoing arguments are stored to the stack, because the
2355 // outgoing stack slots may alias the incoming argument stack slots, and
2356 // the alias isn't otherwise explicit. This is slightly more conservative
2357 // than necessary, because it means that each store effectively depends
2358 // on every argument instead of just those arguments it would clobber.
2359 SDValue ArgChain = DAG.getStackArgumentTokenFactor(Chain);
2361 SmallVector<SDValue, 8> MemOpChains2;
2364 // Do not flag preceding copytoreg stuff together with the following stuff.
2366 if (getTargetMachine().Options.GuaranteedTailCallOpt) {
2367 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2368 CCValAssign &VA = ArgLocs[i];
2371 assert(VA.isMemLoc());
2372 SDValue Arg = OutVals[i];
2373 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2374 // Create frame index.
2375 int32_t Offset = VA.getLocMemOffset()+FPDiff;
2376 uint32_t OpSize = (VA.getLocVT().getSizeInBits()+7)/8;
2377 FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true);
2378 FIN = DAG.getFrameIndex(FI, getPointerTy());
2380 if (Flags.isByVal()) {
2381 // Copy relative to framepointer.
2382 SDValue Source = DAG.getIntPtrConstant(VA.getLocMemOffset());
2383 if (StackPtr.getNode() == 0)
2384 StackPtr = DAG.getCopyFromReg(Chain, dl, X86StackPtr,
2386 Source = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, Source);
2388 MemOpChains2.push_back(CreateCopyOfByValArgument(Source, FIN,
2392 // Store relative to framepointer.
2393 MemOpChains2.push_back(
2394 DAG.getStore(ArgChain, dl, Arg, FIN,
2395 MachinePointerInfo::getFixedStack(FI),
2401 if (!MemOpChains2.empty())
2402 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
2403 &MemOpChains2[0], MemOpChains2.size());
2405 // Copy arguments to their registers.
2406 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
2407 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
2408 RegsToPass[i].second, InFlag);
2409 InFlag = Chain.getValue(1);
2413 // Store the return address to the appropriate stack slot.
2414 Chain = EmitTailCallStoreRetAddr(DAG, MF, Chain, RetAddrFrIdx, Is64Bit,
2418 if (getTargetMachine().getCodeModel() == CodeModel::Large) {
2419 assert(Is64Bit && "Large code model is only legal in 64-bit mode.");
2420 // In the 64-bit large code model, we have to make all calls
2421 // through a register, since the call instruction's 32-bit
2422 // pc-relative offset may not be large enough to hold the whole
2424 } else if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
2425 // If the callee is a GlobalAddress node (quite common, every direct call
2426 // is) turn it into a TargetGlobalAddress node so that legalize doesn't hack
2429 // We should use extra load for direct calls to dllimported functions in
2431 const GlobalValue *GV = G->getGlobal();
2432 if (!GV->hasDLLImportLinkage()) {
2433 unsigned char OpFlags = 0;
2434 bool ExtraLoad = false;
2435 unsigned WrapperKind = ISD::DELETED_NODE;
2437 // On ELF targets, in both X86-64 and X86-32 mode, direct calls to
2438 // external symbols most go through the PLT in PIC mode. If the symbol
2439 // has hidden or protected visibility, or if it is static or local, then
2440 // we don't need to use the PLT - we can directly call it.
2441 if (Subtarget->isTargetELF() &&
2442 getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
2443 GV->hasDefaultVisibility() && !GV->hasLocalLinkage()) {
2444 OpFlags = X86II::MO_PLT;
2445 } else if (Subtarget->isPICStyleStubAny() &&
2446 (GV->isDeclaration() || GV->isWeakForLinker()) &&
2447 (!Subtarget->getTargetTriple().isMacOSX() ||
2448 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
2449 // PC-relative references to external symbols should go through $stub,
2450 // unless we're building with the leopard linker or later, which
2451 // automatically synthesizes these stubs.
2452 OpFlags = X86II::MO_DARWIN_STUB;
2453 } else if (Subtarget->isPICStyleRIPRel() &&
2454 isa<Function>(GV) &&
2455 cast<Function>(GV)->hasFnAttr(Attribute::NonLazyBind)) {
2456 // If the function is marked as non-lazy, generate an indirect call
2457 // which loads from the GOT directly. This avoids runtime overhead
2458 // at the cost of eager binding (and one extra byte of encoding).
2459 OpFlags = X86II::MO_GOTPCREL;
2460 WrapperKind = X86ISD::WrapperRIP;
2464 Callee = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(),
2465 G->getOffset(), OpFlags);
2467 // Add a wrapper if needed.
2468 if (WrapperKind != ISD::DELETED_NODE)
2469 Callee = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Callee);
2470 // Add extra indirection if needed.
2472 Callee = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Callee,
2473 MachinePointerInfo::getGOT(),
2474 false, false, false, 0);
2476 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
2477 unsigned char OpFlags = 0;
2479 // On ELF targets, in either X86-64 or X86-32 mode, direct calls to
2480 // external symbols should go through the PLT.
2481 if (Subtarget->isTargetELF() &&
2482 getTargetMachine().getRelocationModel() == Reloc::PIC_) {
2483 OpFlags = X86II::MO_PLT;
2484 } else if (Subtarget->isPICStyleStubAny() &&
2485 (!Subtarget->getTargetTriple().isMacOSX() ||
2486 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
2487 // PC-relative references to external symbols should go through $stub,
2488 // unless we're building with the leopard linker or later, which
2489 // automatically synthesizes these stubs.
2490 OpFlags = X86II::MO_DARWIN_STUB;
2493 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy(),
2497 // Returns a chain & a flag for retval copy to use.
2498 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
2499 SmallVector<SDValue, 8> Ops;
2501 if (!IsSibcall && isTailCall) {
2502 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
2503 DAG.getIntPtrConstant(0, true), InFlag);
2504 InFlag = Chain.getValue(1);
2507 Ops.push_back(Chain);
2508 Ops.push_back(Callee);
2511 Ops.push_back(DAG.getConstant(FPDiff, MVT::i32));
2513 // Add argument registers to the end of the list so that they are known live
2515 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
2516 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
2517 RegsToPass[i].second.getValueType()));
2519 // Add an implicit use GOT pointer in EBX.
2520 if (!isTailCall && Subtarget->isPICStyleGOT())
2521 Ops.push_back(DAG.getRegister(X86::EBX, getPointerTy()));
2523 // Add an implicit use of AL for non-Windows x86 64-bit vararg functions.
2524 if (Is64Bit && isVarArg && !IsWin64)
2525 Ops.push_back(DAG.getRegister(X86::AL, MVT::i8));
2527 // Add a register mask operand representing the call-preserved registers.
2528 const TargetRegisterInfo *TRI = getTargetMachine().getRegisterInfo();
2529 const uint32_t *Mask = TRI->getCallPreservedMask(CallConv);
2530 assert(Mask && "Missing call preserved mask for calling convention");
2531 Ops.push_back(DAG.getRegisterMask(Mask));
2533 if (InFlag.getNode())
2534 Ops.push_back(InFlag);
2538 //// If this is the first return lowered for this function, add the regs
2539 //// to the liveout set for the function.
2540 // This isn't right, although it's probably harmless on x86; liveouts
2541 // should be computed from returns not tail calls. Consider a void
2542 // function making a tail call to a function returning int.
2543 return DAG.getNode(X86ISD::TC_RETURN, dl,
2544 NodeTys, &Ops[0], Ops.size());
2547 Chain = DAG.getNode(X86ISD::CALL, dl, NodeTys, &Ops[0], Ops.size());
2548 InFlag = Chain.getValue(1);
2550 // Create the CALLSEQ_END node.
2551 unsigned NumBytesForCalleeToPush;
2552 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg,
2553 getTargetMachine().Options.GuaranteedTailCallOpt))
2554 NumBytesForCalleeToPush = NumBytes; // Callee pops everything
2555 else if (!Is64Bit && !IsTailCallConvention(CallConv) && !IsWindows &&
2557 // If this is a call to a struct-return function, the callee
2558 // pops the hidden struct pointer, so we have to push it back.
2559 // This is common for Darwin/X86, Linux & Mingw32 targets.
2560 // For MSVC Win32 targets, the caller pops the hidden struct pointer.
2561 NumBytesForCalleeToPush = 4;
2563 NumBytesForCalleeToPush = 0; // Callee pops nothing.
2565 // Returns a flag for retval copy to use.
2567 Chain = DAG.getCALLSEQ_END(Chain,
2568 DAG.getIntPtrConstant(NumBytes, true),
2569 DAG.getIntPtrConstant(NumBytesForCalleeToPush,
2572 InFlag = Chain.getValue(1);
2575 // Handle result values, copying them out of physregs into vregs that we
2577 return LowerCallResult(Chain, InFlag, CallConv, isVarArg,
2578 Ins, dl, DAG, InVals);
2582 //===----------------------------------------------------------------------===//
2583 // Fast Calling Convention (tail call) implementation
2584 //===----------------------------------------------------------------------===//
2586 // Like std call, callee cleans arguments, convention except that ECX is
2587 // reserved for storing the tail called function address. Only 2 registers are
2588 // free for argument passing (inreg). Tail call optimization is performed
2590 // * tailcallopt is enabled
2591 // * caller/callee are fastcc
2592 // On X86_64 architecture with GOT-style position independent code only local
2593 // (within module) calls are supported at the moment.
2594 // To keep the stack aligned according to platform abi the function
2595 // GetAlignedArgumentStackSize ensures that argument delta is always multiples
2596 // of stack alignment. (Dynamic linkers need this - darwin's dyld for example)
2597 // If a tail called function callee has more arguments than the caller the
2598 // caller needs to make sure that there is room to move the RETADDR to. This is
2599 // achieved by reserving an area the size of the argument delta right after the
2600 // original REtADDR, but before the saved framepointer or the spilled registers
2601 // e.g. caller(arg1, arg2) calls callee(arg1, arg2,arg3,arg4)
2613 /// GetAlignedArgumentStackSize - Make the stack size align e.g 16n + 12 aligned
2614 /// for a 16 byte align requirement.
2616 X86TargetLowering::GetAlignedArgumentStackSize(unsigned StackSize,
2617 SelectionDAG& DAG) const {
2618 MachineFunction &MF = DAG.getMachineFunction();
2619 const TargetMachine &TM = MF.getTarget();
2620 const TargetFrameLowering &TFI = *TM.getFrameLowering();
2621 unsigned StackAlignment = TFI.getStackAlignment();
2622 uint64_t AlignMask = StackAlignment - 1;
2623 int64_t Offset = StackSize;
2624 uint64_t SlotSize = TD->getPointerSize();
2625 if ( (Offset & AlignMask) <= (StackAlignment - SlotSize) ) {
2626 // Number smaller than 12 so just add the difference.
2627 Offset += ((StackAlignment - SlotSize) - (Offset & AlignMask));
2629 // Mask out lower bits, add stackalignment once plus the 12 bytes.
2630 Offset = ((~AlignMask) & Offset) + StackAlignment +
2631 (StackAlignment-SlotSize);
2636 /// MatchingStackOffset - Return true if the given stack call argument is
2637 /// already available in the same position (relatively) of the caller's
2638 /// incoming argument stack.
2640 bool MatchingStackOffset(SDValue Arg, unsigned Offset, ISD::ArgFlagsTy Flags,
2641 MachineFrameInfo *MFI, const MachineRegisterInfo *MRI,
2642 const X86InstrInfo *TII) {
2643 unsigned Bytes = Arg.getValueType().getSizeInBits() / 8;
2645 if (Arg.getOpcode() == ISD::CopyFromReg) {
2646 unsigned VR = cast<RegisterSDNode>(Arg.getOperand(1))->getReg();
2647 if (!TargetRegisterInfo::isVirtualRegister(VR))
2649 MachineInstr *Def = MRI->getVRegDef(VR);
2652 if (!Flags.isByVal()) {
2653 if (!TII->isLoadFromStackSlot(Def, FI))
2656 unsigned Opcode = Def->getOpcode();
2657 if ((Opcode == X86::LEA32r || Opcode == X86::LEA64r) &&
2658 Def->getOperand(1).isFI()) {
2659 FI = Def->getOperand(1).getIndex();
2660 Bytes = Flags.getByValSize();
2664 } else if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Arg)) {
2665 if (Flags.isByVal())
2666 // ByVal argument is passed in as a pointer but it's now being
2667 // dereferenced. e.g.
2668 // define @foo(%struct.X* %A) {
2669 // tail call @bar(%struct.X* byval %A)
2672 SDValue Ptr = Ld->getBasePtr();
2673 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr);
2676 FI = FINode->getIndex();
2677 } else if (Arg.getOpcode() == ISD::FrameIndex && Flags.isByVal()) {
2678 FrameIndexSDNode *FINode = cast<FrameIndexSDNode>(Arg);
2679 FI = FINode->getIndex();
2680 Bytes = Flags.getByValSize();
2684 assert(FI != INT_MAX);
2685 if (!MFI->isFixedObjectIndex(FI))
2687 return Offset == MFI->getObjectOffset(FI) && Bytes == MFI->getObjectSize(FI);
2690 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
2691 /// for tail call optimization. Targets which want to do tail call
2692 /// optimization should implement this function.
2694 X86TargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
2695 CallingConv::ID CalleeCC,
2697 bool isCalleeStructRet,
2698 bool isCallerStructRet,
2699 const SmallVectorImpl<ISD::OutputArg> &Outs,
2700 const SmallVectorImpl<SDValue> &OutVals,
2701 const SmallVectorImpl<ISD::InputArg> &Ins,
2702 SelectionDAG& DAG) const {
2703 if (!IsTailCallConvention(CalleeCC) &&
2704 CalleeCC != CallingConv::C)
2707 // If -tailcallopt is specified, make fastcc functions tail-callable.
2708 const MachineFunction &MF = DAG.getMachineFunction();
2709 const Function *CallerF = DAG.getMachineFunction().getFunction();
2710 CallingConv::ID CallerCC = CallerF->getCallingConv();
2711 bool CCMatch = CallerCC == CalleeCC;
2713 if (getTargetMachine().Options.GuaranteedTailCallOpt) {
2714 if (IsTailCallConvention(CalleeCC) && CCMatch)
2719 // Look for obvious safe cases to perform tail call optimization that do not
2720 // require ABI changes. This is what gcc calls sibcall.
2722 // Can't do sibcall if stack needs to be dynamically re-aligned. PEI needs to
2723 // emit a special epilogue.
2724 if (RegInfo->needsStackRealignment(MF))
2727 // Also avoid sibcall optimization if either caller or callee uses struct
2728 // return semantics.
2729 if (isCalleeStructRet || isCallerStructRet)
2732 // An stdcall caller is expected to clean up its arguments; the callee
2733 // isn't going to do that.
2734 if (!CCMatch && CallerCC==CallingConv::X86_StdCall)
2737 // Do not sibcall optimize vararg calls unless all arguments are passed via
2739 if (isVarArg && !Outs.empty()) {
2741 // Optimizing for varargs on Win64 is unlikely to be safe without
2742 // additional testing.
2743 if (Subtarget->isTargetWin64())
2746 SmallVector<CCValAssign, 16> ArgLocs;
2747 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(),
2748 getTargetMachine(), ArgLocs, *DAG.getContext());
2750 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
2751 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i)
2752 if (!ArgLocs[i].isRegLoc())
2756 // If the call result is in ST0 / ST1, it needs to be popped off the x87
2757 // stack. Therefore, if it's not used by the call it is not safe to optimize
2758 // this into a sibcall.
2759 bool Unused = false;
2760 for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
2767 SmallVector<CCValAssign, 16> RVLocs;
2768 CCState CCInfo(CalleeCC, false, DAG.getMachineFunction(),
2769 getTargetMachine(), RVLocs, *DAG.getContext());
2770 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
2771 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
2772 CCValAssign &VA = RVLocs[i];
2773 if (VA.getLocReg() == X86::ST0 || VA.getLocReg() == X86::ST1)
2778 // If the calling conventions do not match, then we'd better make sure the
2779 // results are returned in the same way as what the caller expects.
2781 SmallVector<CCValAssign, 16> RVLocs1;
2782 CCState CCInfo1(CalleeCC, false, DAG.getMachineFunction(),
2783 getTargetMachine(), RVLocs1, *DAG.getContext());
2784 CCInfo1.AnalyzeCallResult(Ins, RetCC_X86);
2786 SmallVector<CCValAssign, 16> RVLocs2;
2787 CCState CCInfo2(CallerCC, false, DAG.getMachineFunction(),
2788 getTargetMachine(), RVLocs2, *DAG.getContext());
2789 CCInfo2.AnalyzeCallResult(Ins, RetCC_X86);
2791 if (RVLocs1.size() != RVLocs2.size())
2793 for (unsigned i = 0, e = RVLocs1.size(); i != e; ++i) {
2794 if (RVLocs1[i].isRegLoc() != RVLocs2[i].isRegLoc())
2796 if (RVLocs1[i].getLocInfo() != RVLocs2[i].getLocInfo())
2798 if (RVLocs1[i].isRegLoc()) {
2799 if (RVLocs1[i].getLocReg() != RVLocs2[i].getLocReg())
2802 if (RVLocs1[i].getLocMemOffset() != RVLocs2[i].getLocMemOffset())
2808 // If the callee takes no arguments then go on to check the results of the
2810 if (!Outs.empty()) {
2811 // Check if stack adjustment is needed. For now, do not do this if any
2812 // argument is passed on the stack.
2813 SmallVector<CCValAssign, 16> ArgLocs;
2814 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(),
2815 getTargetMachine(), ArgLocs, *DAG.getContext());
2817 // Allocate shadow area for Win64
2818 if (Subtarget->isTargetWin64()) {
2819 CCInfo.AllocateStack(32, 8);
2822 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
2823 if (CCInfo.getNextStackOffset()) {
2824 MachineFunction &MF = DAG.getMachineFunction();
2825 if (MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn())
2828 // Check if the arguments are already laid out in the right way as
2829 // the caller's fixed stack objects.
2830 MachineFrameInfo *MFI = MF.getFrameInfo();
2831 const MachineRegisterInfo *MRI = &MF.getRegInfo();
2832 const X86InstrInfo *TII =
2833 ((X86TargetMachine&)getTargetMachine()).getInstrInfo();
2834 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2835 CCValAssign &VA = ArgLocs[i];
2836 SDValue Arg = OutVals[i];
2837 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2838 if (VA.getLocInfo() == CCValAssign::Indirect)
2840 if (!VA.isRegLoc()) {
2841 if (!MatchingStackOffset(Arg, VA.getLocMemOffset(), Flags,
2848 // If the tailcall address may be in a register, then make sure it's
2849 // possible to register allocate for it. In 32-bit, the call address can
2850 // only target EAX, EDX, or ECX since the tail call must be scheduled after
2851 // callee-saved registers are restored. These happen to be the same
2852 // registers used to pass 'inreg' arguments so watch out for those.
2853 if (!Subtarget->is64Bit() &&
2854 !isa<GlobalAddressSDNode>(Callee) &&
2855 !isa<ExternalSymbolSDNode>(Callee)) {
2856 unsigned NumInRegs = 0;
2857 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2858 CCValAssign &VA = ArgLocs[i];
2861 unsigned Reg = VA.getLocReg();
2864 case X86::EAX: case X86::EDX: case X86::ECX:
2865 if (++NumInRegs == 3)
2877 X86TargetLowering::createFastISel(FunctionLoweringInfo &funcInfo) const {
2878 return X86::createFastISel(funcInfo);
2882 //===----------------------------------------------------------------------===//
2883 // Other Lowering Hooks
2884 //===----------------------------------------------------------------------===//
2886 static bool MayFoldLoad(SDValue Op) {
2887 return Op.hasOneUse() && ISD::isNormalLoad(Op.getNode());
2890 static bool MayFoldIntoStore(SDValue Op) {
2891 return Op.hasOneUse() && ISD::isNormalStore(*Op.getNode()->use_begin());
2894 static bool isTargetShuffle(unsigned Opcode) {
2896 default: return false;
2897 case X86ISD::PSHUFD:
2898 case X86ISD::PSHUFHW:
2899 case X86ISD::PSHUFLW:
2901 case X86ISD::PALIGN:
2902 case X86ISD::MOVLHPS:
2903 case X86ISD::MOVLHPD:
2904 case X86ISD::MOVHLPS:
2905 case X86ISD::MOVLPS:
2906 case X86ISD::MOVLPD:
2907 case X86ISD::MOVSHDUP:
2908 case X86ISD::MOVSLDUP:
2909 case X86ISD::MOVDDUP:
2912 case X86ISD::UNPCKL:
2913 case X86ISD::UNPCKH:
2914 case X86ISD::VPERMILP:
2915 case X86ISD::VPERM2X128:
2920 static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT,
2921 SDValue V1, SelectionDAG &DAG) {
2923 default: llvm_unreachable("Unknown x86 shuffle node");
2924 case X86ISD::MOVSHDUP:
2925 case X86ISD::MOVSLDUP:
2926 case X86ISD::MOVDDUP:
2927 return DAG.getNode(Opc, dl, VT, V1);
2931 static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT,
2932 SDValue V1, unsigned TargetMask,
2933 SelectionDAG &DAG) {
2935 default: llvm_unreachable("Unknown x86 shuffle node");
2936 case X86ISD::PSHUFD:
2937 case X86ISD::PSHUFHW:
2938 case X86ISD::PSHUFLW:
2939 case X86ISD::VPERMILP:
2940 case X86ISD::VPERMI:
2941 return DAG.getNode(Opc, dl, VT, V1, DAG.getConstant(TargetMask, MVT::i8));
2945 static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT,
2946 SDValue V1, SDValue V2, unsigned TargetMask,
2947 SelectionDAG &DAG) {
2949 default: llvm_unreachable("Unknown x86 shuffle node");
2950 case X86ISD::PALIGN:
2952 case X86ISD::VPERM2X128:
2953 return DAG.getNode(Opc, dl, VT, V1, V2,
2954 DAG.getConstant(TargetMask, MVT::i8));
2958 static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT,
2959 SDValue V1, SDValue V2, SelectionDAG &DAG) {
2961 default: llvm_unreachable("Unknown x86 shuffle node");
2962 case X86ISD::MOVLHPS:
2963 case X86ISD::MOVLHPD:
2964 case X86ISD::MOVHLPS:
2965 case X86ISD::MOVLPS:
2966 case X86ISD::MOVLPD:
2969 case X86ISD::UNPCKL:
2970 case X86ISD::UNPCKH:
2971 return DAG.getNode(Opc, dl, VT, V1, V2);
2975 SDValue X86TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) const {
2976 MachineFunction &MF = DAG.getMachineFunction();
2977 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
2978 int ReturnAddrIndex = FuncInfo->getRAIndex();
2980 if (ReturnAddrIndex == 0) {
2981 // Set up a frame object for the return address.
2982 uint64_t SlotSize = TD->getPointerSize();
2983 ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(SlotSize, -SlotSize,
2985 FuncInfo->setRAIndex(ReturnAddrIndex);
2988 return DAG.getFrameIndex(ReturnAddrIndex, getPointerTy());
2992 bool X86::isOffsetSuitableForCodeModel(int64_t Offset, CodeModel::Model M,
2993 bool hasSymbolicDisplacement) {
2994 // Offset should fit into 32 bit immediate field.
2995 if (!isInt<32>(Offset))
2998 // If we don't have a symbolic displacement - we don't have any extra
3000 if (!hasSymbolicDisplacement)
3003 // FIXME: Some tweaks might be needed for medium code model.
3004 if (M != CodeModel::Small && M != CodeModel::Kernel)
3007 // For small code model we assume that latest object is 16MB before end of 31
3008 // bits boundary. We may also accept pretty large negative constants knowing
3009 // that all objects are in the positive half of address space.
3010 if (M == CodeModel::Small && Offset < 16*1024*1024)
3013 // For kernel code model we know that all object resist in the negative half
3014 // of 32bits address space. We may not accept negative offsets, since they may
3015 // be just off and we may accept pretty large positive ones.
3016 if (M == CodeModel::Kernel && Offset > 0)
3022 /// isCalleePop - Determines whether the callee is required to pop its
3023 /// own arguments. Callee pop is necessary to support tail calls.
3024 bool X86::isCalleePop(CallingConv::ID CallingConv,
3025 bool is64Bit, bool IsVarArg, bool TailCallOpt) {
3029 switch (CallingConv) {
3032 case CallingConv::X86_StdCall:
3034 case CallingConv::X86_FastCall:
3036 case CallingConv::X86_ThisCall:
3038 case CallingConv::Fast:
3040 case CallingConv::GHC:
3045 /// TranslateX86CC - do a one to one translation of a ISD::CondCode to the X86
3046 /// specific condition code, returning the condition code and the LHS/RHS of the
3047 /// comparison to make.
3048 static unsigned TranslateX86CC(ISD::CondCode SetCCOpcode, bool isFP,
3049 SDValue &LHS, SDValue &RHS, SelectionDAG &DAG) {
3051 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
3052 if (SetCCOpcode == ISD::SETGT && RHSC->isAllOnesValue()) {
3053 // X > -1 -> X == 0, jump !sign.
3054 RHS = DAG.getConstant(0, RHS.getValueType());
3055 return X86::COND_NS;
3056 } else if (SetCCOpcode == ISD::SETLT && RHSC->isNullValue()) {
3057 // X < 0 -> X == 0, jump on sign.
3059 } else if (SetCCOpcode == ISD::SETLT && RHSC->getZExtValue() == 1) {
3061 RHS = DAG.getConstant(0, RHS.getValueType());
3062 return X86::COND_LE;
3066 switch (SetCCOpcode) {
3067 default: llvm_unreachable("Invalid integer condition!");
3068 case ISD::SETEQ: return X86::COND_E;
3069 case ISD::SETGT: return X86::COND_G;
3070 case ISD::SETGE: return X86::COND_GE;
3071 case ISD::SETLT: return X86::COND_L;
3072 case ISD::SETLE: return X86::COND_LE;
3073 case ISD::SETNE: return X86::COND_NE;
3074 case ISD::SETULT: return X86::COND_B;
3075 case ISD::SETUGT: return X86::COND_A;
3076 case ISD::SETULE: return X86::COND_BE;
3077 case ISD::SETUGE: return X86::COND_AE;
3081 // First determine if it is required or is profitable to flip the operands.
3083 // If LHS is a foldable load, but RHS is not, flip the condition.
3084 if (ISD::isNON_EXTLoad(LHS.getNode()) &&
3085 !ISD::isNON_EXTLoad(RHS.getNode())) {
3086 SetCCOpcode = getSetCCSwappedOperands(SetCCOpcode);
3087 std::swap(LHS, RHS);
3090 switch (SetCCOpcode) {
3096 std::swap(LHS, RHS);
3100 // On a floating point condition, the flags are set as follows:
3102 // 0 | 0 | 0 | X > Y
3103 // 0 | 0 | 1 | X < Y
3104 // 1 | 0 | 0 | X == Y
3105 // 1 | 1 | 1 | unordered
3106 switch (SetCCOpcode) {
3107 default: llvm_unreachable("Condcode should be pre-legalized away");
3109 case ISD::SETEQ: return X86::COND_E;
3110 case ISD::SETOLT: // flipped
3112 case ISD::SETGT: return X86::COND_A;
3113 case ISD::SETOLE: // flipped
3115 case ISD::SETGE: return X86::COND_AE;
3116 case ISD::SETUGT: // flipped
3118 case ISD::SETLT: return X86::COND_B;
3119 case ISD::SETUGE: // flipped
3121 case ISD::SETLE: return X86::COND_BE;
3123 case ISD::SETNE: return X86::COND_NE;
3124 case ISD::SETUO: return X86::COND_P;
3125 case ISD::SETO: return X86::COND_NP;
3127 case ISD::SETUNE: return X86::COND_INVALID;
3131 /// hasFPCMov - is there a floating point cmov for the specific X86 condition
3132 /// code. Current x86 isa includes the following FP cmov instructions:
3133 /// fcmovb, fcomvbe, fcomve, fcmovu, fcmovae, fcmova, fcmovne, fcmovnu.
3134 static bool hasFPCMov(unsigned X86CC) {
3150 /// isFPImmLegal - Returns true if the target can instruction select the
3151 /// specified FP immediate natively. If false, the legalizer will
3152 /// materialize the FP immediate as a load from a constant pool.
3153 bool X86TargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
3154 for (unsigned i = 0, e = LegalFPImmediates.size(); i != e; ++i) {
3155 if (Imm.bitwiseIsEqual(LegalFPImmediates[i]))
3161 /// isUndefOrInRange - Return true if Val is undef or if its value falls within
3162 /// the specified range (L, H].
3163 static bool isUndefOrInRange(int Val, int Low, int Hi) {
3164 return (Val < 0) || (Val >= Low && Val < Hi);
3167 /// isUndefOrEqual - Val is either less than zero (undef) or equal to the
3168 /// specified value.
3169 static bool isUndefOrEqual(int Val, int CmpVal) {
3170 if (Val < 0 || Val == CmpVal)
3175 /// isSequentialOrUndefInRange - Return true if every element in Mask, begining
3176 /// from position Pos and ending in Pos+Size, falls within the specified
3177 /// sequential range (L, L+Pos]. or is undef.
3178 static bool isSequentialOrUndefInRange(ArrayRef<int> Mask,
3179 int Pos, int Size, int Low) {
3180 for (int i = Pos, e = Pos+Size; i != e; ++i, ++Low)
3181 if (!isUndefOrEqual(Mask[i], Low))
3186 /// isPSHUFDMask - Return true if the node specifies a shuffle of elements that
3187 /// is suitable for input to PSHUFD or PSHUFW. That is, it doesn't reference
3188 /// the second operand.
3189 static bool isPSHUFDMask(ArrayRef<int> Mask, EVT VT) {
3190 if (VT == MVT::v4f32 || VT == MVT::v4i32 )
3191 return (Mask[0] < 4 && Mask[1] < 4 && Mask[2] < 4 && Mask[3] < 4);
3192 if (VT == MVT::v2f64 || VT == MVT::v2i64)
3193 return (Mask[0] < 2 && Mask[1] < 2);
3197 /// isPSHUFHWMask - Return true if the node specifies a shuffle of elements that
3198 /// is suitable for input to PSHUFHW.
3199 static bool isPSHUFHWMask(ArrayRef<int> Mask, EVT VT) {
3200 if (VT != MVT::v8i16)
3203 // Lower quadword copied in order or undef.
3204 if (!isSequentialOrUndefInRange(Mask, 0, 4, 0))
3207 // Upper quadword shuffled.
3208 for (unsigned i = 4; i != 8; ++i)
3209 if (Mask[i] >= 0 && (Mask[i] < 4 || Mask[i] > 7))
3215 /// isPSHUFLWMask - Return true if the node specifies a shuffle of elements that
3216 /// is suitable for input to PSHUFLW.
3217 static bool isPSHUFLWMask(ArrayRef<int> Mask, EVT VT) {
3218 if (VT != MVT::v8i16)
3221 // Upper quadword copied in order.
3222 if (!isSequentialOrUndefInRange(Mask, 4, 4, 4))
3225 // Lower quadword shuffled.
3226 for (unsigned i = 0; i != 4; ++i)
3233 /// isPALIGNRMask - Return true if the node specifies a shuffle of elements that
3234 /// is suitable for input to PALIGNR.
3235 static bool isPALIGNRMask(ArrayRef<int> Mask, EVT VT,
3236 const X86Subtarget *Subtarget) {
3237 if ((VT.getSizeInBits() == 128 && !Subtarget->hasSSSE3()) ||
3238 (VT.getSizeInBits() == 256 && !Subtarget->hasAVX2()))
3241 unsigned NumElts = VT.getVectorNumElements();
3242 unsigned NumLanes = VT.getSizeInBits()/128;
3243 unsigned NumLaneElts = NumElts/NumLanes;
3245 // Do not handle 64-bit element shuffles with palignr.
3246 if (NumLaneElts == 2)
3249 for (unsigned l = 0; l != NumElts; l+=NumLaneElts) {
3251 for (i = 0; i != NumLaneElts; ++i) {
3256 // Lane is all undef, go to next lane
3257 if (i == NumLaneElts)
3260 int Start = Mask[i+l];
3262 // Make sure its in this lane in one of the sources
3263 if (!isUndefOrInRange(Start, l, l+NumLaneElts) &&
3264 !isUndefOrInRange(Start, l+NumElts, l+NumElts+NumLaneElts))
3267 // If not lane 0, then we must match lane 0
3268 if (l != 0 && Mask[i] >= 0 && !isUndefOrEqual(Start, Mask[i]+l))
3271 // Correct second source to be contiguous with first source
3272 if (Start >= (int)NumElts)
3273 Start -= NumElts - NumLaneElts;
3275 // Make sure we're shifting in the right direction.
3276 if (Start <= (int)(i+l))
3281 // Check the rest of the elements to see if they are consecutive.
3282 for (++i; i != NumLaneElts; ++i) {
3283 int Idx = Mask[i+l];
3285 // Make sure its in this lane
3286 if (!isUndefOrInRange(Idx, l, l+NumLaneElts) &&
3287 !isUndefOrInRange(Idx, l+NumElts, l+NumElts+NumLaneElts))
3290 // If not lane 0, then we must match lane 0
3291 if (l != 0 && Mask[i] >= 0 && !isUndefOrEqual(Idx, Mask[i]+l))
3294 if (Idx >= (int)NumElts)
3295 Idx -= NumElts - NumLaneElts;
3297 if (!isUndefOrEqual(Idx, Start+i))
3306 /// CommuteVectorShuffleMask - Change values in a shuffle permute mask assuming
3307 /// the two vector operands have swapped position.
3308 static void CommuteVectorShuffleMask(SmallVectorImpl<int> &Mask,
3309 unsigned NumElems) {
3310 for (unsigned i = 0; i != NumElems; ++i) {
3314 else if (idx < (int)NumElems)
3315 Mask[i] = idx + NumElems;
3317 Mask[i] = idx - NumElems;
3321 /// isSHUFPMask - Return true if the specified VECTOR_SHUFFLE operand
3322 /// specifies a shuffle of elements that is suitable for input to 128/256-bit
3323 /// SHUFPS and SHUFPD. If Commuted is true, then it checks for sources to be
3324 /// reverse of what x86 shuffles want.
3325 static bool isSHUFPMask(ArrayRef<int> Mask, EVT VT, bool HasAVX,
3326 bool Commuted = false) {
3327 if (!HasAVX && VT.getSizeInBits() == 256)
3330 unsigned NumElems = VT.getVectorNumElements();
3331 unsigned NumLanes = VT.getSizeInBits()/128;
3332 unsigned NumLaneElems = NumElems/NumLanes;
3334 if (NumLaneElems != 2 && NumLaneElems != 4)
3337 // VSHUFPSY divides the resulting vector into 4 chunks.
3338 // The sources are also splitted into 4 chunks, and each destination
3339 // chunk must come from a different source chunk.
3341 // SRC1 => X7 X6 X5 X4 X3 X2 X1 X0
3342 // SRC2 => Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y9
3344 // DST => Y7..Y4, Y7..Y4, X7..X4, X7..X4,
3345 // Y3..Y0, Y3..Y0, X3..X0, X3..X0
3347 // VSHUFPDY divides the resulting vector into 4 chunks.
3348 // The sources are also splitted into 4 chunks, and each destination
3349 // chunk must come from a different source chunk.
3351 // SRC1 => X3 X2 X1 X0
3352 // SRC2 => Y3 Y2 Y1 Y0
3354 // DST => Y3..Y2, X3..X2, Y1..Y0, X1..X0
3356 unsigned HalfLaneElems = NumLaneElems/2;
3357 for (unsigned l = 0; l != NumElems; l += NumLaneElems) {
3358 for (unsigned i = 0; i != NumLaneElems; ++i) {
3359 int Idx = Mask[i+l];
3360 unsigned RngStart = l + ((Commuted == (i<HalfLaneElems)) ? NumElems : 0);
3361 if (!isUndefOrInRange(Idx, RngStart, RngStart+NumLaneElems))
3363 // For VSHUFPSY, the mask of the second half must be the same as the
3364 // first but with the appropriate offsets. This works in the same way as
3365 // VPERMILPS works with masks.
3366 if (NumElems != 8 || l == 0 || Mask[i] < 0)
3368 if (!isUndefOrEqual(Idx, Mask[i]+l))
3376 /// isMOVHLPSMask - Return true if the specified VECTOR_SHUFFLE operand
3377 /// specifies a shuffle of elements that is suitable for input to MOVHLPS.
3378 static bool isMOVHLPSMask(ArrayRef<int> Mask, EVT VT) {
3379 unsigned NumElems = VT.getVectorNumElements();
3381 if (VT.getSizeInBits() != 128)
3387 // Expect bit0 == 6, bit1 == 7, bit2 == 2, bit3 == 3
3388 return isUndefOrEqual(Mask[0], 6) &&
3389 isUndefOrEqual(Mask[1], 7) &&
3390 isUndefOrEqual(Mask[2], 2) &&
3391 isUndefOrEqual(Mask[3], 3);
3394 /// isMOVHLPS_v_undef_Mask - Special case of isMOVHLPSMask for canonical form
3395 /// of vector_shuffle v, v, <2, 3, 2, 3>, i.e. vector_shuffle v, undef,
3397 static bool isMOVHLPS_v_undef_Mask(ArrayRef<int> Mask, EVT VT) {
3398 unsigned NumElems = VT.getVectorNumElements();
3400 if (VT.getSizeInBits() != 128)
3406 return isUndefOrEqual(Mask[0], 2) &&
3407 isUndefOrEqual(Mask[1], 3) &&
3408 isUndefOrEqual(Mask[2], 2) &&
3409 isUndefOrEqual(Mask[3], 3);
3412 /// isMOVLPMask - Return true if the specified VECTOR_SHUFFLE operand
3413 /// specifies a shuffle of elements that is suitable for input to MOVLP{S|D}.
3414 static bool isMOVLPMask(ArrayRef<int> Mask, EVT VT) {
3415 if (VT.getSizeInBits() != 128)
3418 unsigned NumElems = VT.getVectorNumElements();
3420 if (NumElems != 2 && NumElems != 4)
3423 for (unsigned i = 0; i != NumElems/2; ++i)
3424 if (!isUndefOrEqual(Mask[i], i + NumElems))
3427 for (unsigned i = NumElems/2; i != NumElems; ++i)
3428 if (!isUndefOrEqual(Mask[i], i))
3434 /// isMOVLHPSMask - Return true if the specified VECTOR_SHUFFLE operand
3435 /// specifies a shuffle of elements that is suitable for input to MOVLHPS.
3436 static bool isMOVLHPSMask(ArrayRef<int> Mask, EVT VT) {
3437 unsigned NumElems = VT.getVectorNumElements();
3439 if ((NumElems != 2 && NumElems != 4)
3440 || VT.getSizeInBits() > 128)
3443 for (unsigned i = 0; i != NumElems/2; ++i)
3444 if (!isUndefOrEqual(Mask[i], i))
3447 for (unsigned i = 0; i != NumElems/2; ++i)
3448 if (!isUndefOrEqual(Mask[i + NumElems/2], i + NumElems))
3454 /// isUNPCKLMask - Return true if the specified VECTOR_SHUFFLE operand
3455 /// specifies a shuffle of elements that is suitable for input to UNPCKL.
3456 static bool isUNPCKLMask(ArrayRef<int> Mask, EVT VT,
3457 bool HasAVX2, bool V2IsSplat = false) {
3458 unsigned NumElts = VT.getVectorNumElements();
3460 assert((VT.is128BitVector() || VT.is256BitVector()) &&
3461 "Unsupported vector type for unpckh");
3463 if (VT.getSizeInBits() == 256 && NumElts != 4 && NumElts != 8 &&
3464 (!HasAVX2 || (NumElts != 16 && NumElts != 32)))
3467 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
3468 // independently on 128-bit lanes.
3469 unsigned NumLanes = VT.getSizeInBits()/128;
3470 unsigned NumLaneElts = NumElts/NumLanes;
3472 for (unsigned l = 0; l != NumLanes; ++l) {
3473 for (unsigned i = l*NumLaneElts, j = l*NumLaneElts;
3474 i != (l+1)*NumLaneElts;
3477 int BitI1 = Mask[i+1];
3478 if (!isUndefOrEqual(BitI, j))
3481 if (!isUndefOrEqual(BitI1, NumElts))
3484 if (!isUndefOrEqual(BitI1, j + NumElts))
3493 /// isUNPCKHMask - Return true if the specified VECTOR_SHUFFLE operand
3494 /// specifies a shuffle of elements that is suitable for input to UNPCKH.
3495 static bool isUNPCKHMask(ArrayRef<int> Mask, EVT VT,
3496 bool HasAVX2, bool V2IsSplat = false) {
3497 unsigned NumElts = VT.getVectorNumElements();
3499 assert((VT.is128BitVector() || VT.is256BitVector()) &&
3500 "Unsupported vector type for unpckh");
3502 if (VT.getSizeInBits() == 256 && NumElts != 4 && NumElts != 8 &&
3503 (!HasAVX2 || (NumElts != 16 && NumElts != 32)))
3506 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
3507 // independently on 128-bit lanes.
3508 unsigned NumLanes = VT.getSizeInBits()/128;
3509 unsigned NumLaneElts = NumElts/NumLanes;
3511 for (unsigned l = 0; l != NumLanes; ++l) {
3512 for (unsigned i = l*NumLaneElts, j = (l*NumLaneElts)+NumLaneElts/2;
3513 i != (l+1)*NumLaneElts; i += 2, ++j) {
3515 int BitI1 = Mask[i+1];
3516 if (!isUndefOrEqual(BitI, j))
3519 if (isUndefOrEqual(BitI1, NumElts))
3522 if (!isUndefOrEqual(BitI1, j+NumElts))
3530 /// isUNPCKL_v_undef_Mask - Special case of isUNPCKLMask for canonical form
3531 /// of vector_shuffle v, v, <0, 4, 1, 5>, i.e. vector_shuffle v, undef,
3533 static bool isUNPCKL_v_undef_Mask(ArrayRef<int> Mask, EVT VT,
3535 unsigned NumElts = VT.getVectorNumElements();
3537 assert((VT.is128BitVector() || VT.is256BitVector()) &&
3538 "Unsupported vector type for unpckh");
3540 if (VT.getSizeInBits() == 256 && NumElts != 4 && NumElts != 8 &&
3541 (!HasAVX2 || (NumElts != 16 && NumElts != 32)))
3544 // For 256-bit i64/f64, use MOVDDUPY instead, so reject the matching pattern
3545 // FIXME: Need a better way to get rid of this, there's no latency difference
3546 // between UNPCKLPD and MOVDDUP, the later should always be checked first and
3547 // the former later. We should also remove the "_undef" special mask.
3548 if (NumElts == 4 && VT.getSizeInBits() == 256)
3551 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
3552 // independently on 128-bit lanes.
3553 unsigned NumLanes = VT.getSizeInBits()/128;
3554 unsigned NumLaneElts = NumElts/NumLanes;
3556 for (unsigned l = 0; l != NumLanes; ++l) {
3557 for (unsigned i = l*NumLaneElts, j = l*NumLaneElts;
3558 i != (l+1)*NumLaneElts;
3561 int BitI1 = Mask[i+1];
3563 if (!isUndefOrEqual(BitI, j))
3565 if (!isUndefOrEqual(BitI1, j))
3573 /// isUNPCKH_v_undef_Mask - Special case of isUNPCKHMask for canonical form
3574 /// of vector_shuffle v, v, <2, 6, 3, 7>, i.e. vector_shuffle v, undef,
3576 static bool isUNPCKH_v_undef_Mask(ArrayRef<int> Mask, EVT VT, bool HasAVX2) {
3577 unsigned NumElts = VT.getVectorNumElements();
3579 assert((VT.is128BitVector() || VT.is256BitVector()) &&
3580 "Unsupported vector type for unpckh");
3582 if (VT.getSizeInBits() == 256 && NumElts != 4 && NumElts != 8 &&
3583 (!HasAVX2 || (NumElts != 16 && NumElts != 32)))
3586 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
3587 // independently on 128-bit lanes.
3588 unsigned NumLanes = VT.getSizeInBits()/128;
3589 unsigned NumLaneElts = NumElts/NumLanes;
3591 for (unsigned l = 0; l != NumLanes; ++l) {
3592 for (unsigned i = l*NumLaneElts, j = (l*NumLaneElts)+NumLaneElts/2;
3593 i != (l+1)*NumLaneElts; i += 2, ++j) {
3595 int BitI1 = Mask[i+1];
3596 if (!isUndefOrEqual(BitI, j))
3598 if (!isUndefOrEqual(BitI1, j))
3605 /// isMOVLMask - Return true if the specified VECTOR_SHUFFLE operand
3606 /// specifies a shuffle of elements that is suitable for input to MOVSS,
3607 /// MOVSD, and MOVD, i.e. setting the lowest element.
3608 static bool isMOVLMask(ArrayRef<int> Mask, EVT VT) {
3609 if (VT.getVectorElementType().getSizeInBits() < 32)
3611 if (VT.getSizeInBits() == 256)
3614 unsigned NumElts = VT.getVectorNumElements();
3616 if (!isUndefOrEqual(Mask[0], NumElts))
3619 for (unsigned i = 1; i != NumElts; ++i)
3620 if (!isUndefOrEqual(Mask[i], i))
3626 /// isVPERM2X128Mask - Match 256-bit shuffles where the elements are considered
3627 /// as permutations between 128-bit chunks or halves. As an example: this
3629 /// vector_shuffle <4, 5, 6, 7, 12, 13, 14, 15>
3630 /// The first half comes from the second half of V1 and the second half from the
3631 /// the second half of V2.
3632 static bool isVPERM2X128Mask(ArrayRef<int> Mask, EVT VT, bool HasAVX) {
3633 if (!HasAVX || VT.getSizeInBits() != 256)
3636 // The shuffle result is divided into half A and half B. In total the two
3637 // sources have 4 halves, namely: C, D, E, F. The final values of A and
3638 // B must come from C, D, E or F.
3639 unsigned HalfSize = VT.getVectorNumElements()/2;
3640 bool MatchA = false, MatchB = false;
3642 // Check if A comes from one of C, D, E, F.
3643 for (unsigned Half = 0; Half != 4; ++Half) {
3644 if (isSequentialOrUndefInRange(Mask, 0, HalfSize, Half*HalfSize)) {
3650 // Check if B comes from one of C, D, E, F.
3651 for (unsigned Half = 0; Half != 4; ++Half) {
3652 if (isSequentialOrUndefInRange(Mask, HalfSize, HalfSize, Half*HalfSize)) {
3658 return MatchA && MatchB;
3661 /// getShuffleVPERM2X128Immediate - Return the appropriate immediate to shuffle
3662 /// the specified VECTOR_MASK mask with VPERM2F128/VPERM2I128 instructions.
3663 static unsigned getShuffleVPERM2X128Immediate(ShuffleVectorSDNode *SVOp) {
3664 EVT VT = SVOp->getValueType(0);
3666 unsigned HalfSize = VT.getVectorNumElements()/2;
3668 unsigned FstHalf = 0, SndHalf = 0;
3669 for (unsigned i = 0; i < HalfSize; ++i) {
3670 if (SVOp->getMaskElt(i) > 0) {
3671 FstHalf = SVOp->getMaskElt(i)/HalfSize;
3675 for (unsigned i = HalfSize; i < HalfSize*2; ++i) {
3676 if (SVOp->getMaskElt(i) > 0) {
3677 SndHalf = SVOp->getMaskElt(i)/HalfSize;
3682 return (FstHalf | (SndHalf << 4));
3685 /// isVPERMILPMask - Return true if the specified VECTOR_SHUFFLE operand
3686 /// specifies a shuffle of elements that is suitable for input to VPERMILPD*.
3687 /// Note that VPERMIL mask matching is different depending whether theunderlying
3688 /// type is 32 or 64. In the VPERMILPS the high half of the mask should point
3689 /// to the same elements of the low, but to the higher half of the source.
3690 /// In VPERMILPD the two lanes could be shuffled independently of each other
3691 /// with the same restriction that lanes can't be crossed. Also handles PSHUFDY.
3692 static bool isVPERMILPMask(ArrayRef<int> Mask, EVT VT, bool HasAVX) {
3696 unsigned NumElts = VT.getVectorNumElements();
3697 // Only match 256-bit with 32/64-bit types
3698 if (VT.getSizeInBits() != 256 || (NumElts != 4 && NumElts != 8))
3701 unsigned NumLanes = VT.getSizeInBits()/128;
3702 unsigned LaneSize = NumElts/NumLanes;
3703 for (unsigned l = 0; l != NumElts; l += LaneSize) {
3704 for (unsigned i = 0; i != LaneSize; ++i) {
3705 if (!isUndefOrInRange(Mask[i+l], l, l+LaneSize))
3707 if (NumElts != 8 || l == 0)
3709 // VPERMILPS handling
3712 if (!isUndefOrEqual(Mask[i+l], Mask[i]+l))
3720 /// isCommutedMOVLMask - Returns true if the shuffle mask is except the reverse
3721 /// of what x86 movss want. X86 movs requires the lowest element to be lowest
3722 /// element of vector 2 and the other elements to come from vector 1 in order.
3723 static bool isCommutedMOVLMask(ArrayRef<int> Mask, EVT VT,
3724 bool V2IsSplat = false, bool V2IsUndef = false) {
3725 unsigned NumOps = VT.getVectorNumElements();
3726 if (VT.getSizeInBits() == 256)
3728 if (NumOps != 2 && NumOps != 4 && NumOps != 8 && NumOps != 16)
3731 if (!isUndefOrEqual(Mask[0], 0))
3734 for (unsigned i = 1; i != NumOps; ++i)
3735 if (!(isUndefOrEqual(Mask[i], i+NumOps) ||
3736 (V2IsUndef && isUndefOrInRange(Mask[i], NumOps, NumOps*2)) ||
3737 (V2IsSplat && isUndefOrEqual(Mask[i], NumOps))))
3743 /// isMOVSHDUPMask - Return true if the specified VECTOR_SHUFFLE operand
3744 /// specifies a shuffle of elements that is suitable for input to MOVSHDUP.
3745 /// Masks to match: <1, 1, 3, 3> or <1, 1, 3, 3, 5, 5, 7, 7>
3746 static bool isMOVSHDUPMask(ArrayRef<int> Mask, EVT VT,
3747 const X86Subtarget *Subtarget) {
3748 if (!Subtarget->hasSSE3())
3751 unsigned NumElems = VT.getVectorNumElements();
3753 if ((VT.getSizeInBits() == 128 && NumElems != 4) ||
3754 (VT.getSizeInBits() == 256 && NumElems != 8))
3757 // "i+1" is the value the indexed mask element must have
3758 for (unsigned i = 0; i != NumElems; i += 2)
3759 if (!isUndefOrEqual(Mask[i], i+1) ||
3760 !isUndefOrEqual(Mask[i+1], i+1))
3766 /// isMOVSLDUPMask - Return true if the specified VECTOR_SHUFFLE operand
3767 /// specifies a shuffle of elements that is suitable for input to MOVSLDUP.
3768 /// Masks to match: <0, 0, 2, 2> or <0, 0, 2, 2, 4, 4, 6, 6>
3769 static bool isMOVSLDUPMask(ArrayRef<int> Mask, EVT VT,
3770 const X86Subtarget *Subtarget) {
3771 if (!Subtarget->hasSSE3())
3774 unsigned NumElems = VT.getVectorNumElements();
3776 if ((VT.getSizeInBits() == 128 && NumElems != 4) ||
3777 (VT.getSizeInBits() == 256 && NumElems != 8))
3780 // "i" is the value the indexed mask element must have
3781 for (unsigned i = 0; i != NumElems; i += 2)
3782 if (!isUndefOrEqual(Mask[i], i) ||
3783 !isUndefOrEqual(Mask[i+1], i))
3789 /// isMOVDDUPYMask - Return true if the specified VECTOR_SHUFFLE operand
3790 /// specifies a shuffle of elements that is suitable for input to 256-bit
3791 /// version of MOVDDUP.
3792 static bool isMOVDDUPYMask(ArrayRef<int> Mask, EVT VT, bool HasAVX) {
3793 unsigned NumElts = VT.getVectorNumElements();
3795 if (!HasAVX || VT.getSizeInBits() != 256 || NumElts != 4)
3798 for (unsigned i = 0; i != NumElts/2; ++i)
3799 if (!isUndefOrEqual(Mask[i], 0))
3801 for (unsigned i = NumElts/2; i != NumElts; ++i)
3802 if (!isUndefOrEqual(Mask[i], NumElts/2))
3807 /// isMOVDDUPMask - Return true if the specified VECTOR_SHUFFLE operand
3808 /// specifies a shuffle of elements that is suitable for input to 128-bit
3809 /// version of MOVDDUP.
3810 static bool isMOVDDUPMask(ArrayRef<int> Mask, EVT VT) {
3811 if (VT.getSizeInBits() != 128)
3814 unsigned e = VT.getVectorNumElements() / 2;
3815 for (unsigned i = 0; i != e; ++i)
3816 if (!isUndefOrEqual(Mask[i], i))
3818 for (unsigned i = 0; i != e; ++i)
3819 if (!isUndefOrEqual(Mask[e+i], i))
3824 /// isVEXTRACTF128Index - Return true if the specified
3825 /// EXTRACT_SUBVECTOR operand specifies a vector extract that is
3826 /// suitable for input to VEXTRACTF128.
3827 bool X86::isVEXTRACTF128Index(SDNode *N) {
3828 if (!isa<ConstantSDNode>(N->getOperand(1).getNode()))
3831 // The index should be aligned on a 128-bit boundary.
3833 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
3835 unsigned VL = N->getValueType(0).getVectorNumElements();
3836 unsigned VBits = N->getValueType(0).getSizeInBits();
3837 unsigned ElSize = VBits / VL;
3838 bool Result = (Index * ElSize) % 128 == 0;
3843 /// isVINSERTF128Index - Return true if the specified INSERT_SUBVECTOR
3844 /// operand specifies a subvector insert that is suitable for input to
3846 bool X86::isVINSERTF128Index(SDNode *N) {
3847 if (!isa<ConstantSDNode>(N->getOperand(2).getNode()))
3850 // The index should be aligned on a 128-bit boundary.
3852 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
3854 unsigned VL = N->getValueType(0).getVectorNumElements();
3855 unsigned VBits = N->getValueType(0).getSizeInBits();
3856 unsigned ElSize = VBits / VL;
3857 bool Result = (Index * ElSize) % 128 == 0;
3862 /// getShuffleSHUFImmediate - Return the appropriate immediate to shuffle
3863 /// the specified VECTOR_SHUFFLE mask with PSHUF* and SHUFP* instructions.
3864 /// Handles 128-bit and 256-bit.
3865 static unsigned getShuffleSHUFImmediate(ShuffleVectorSDNode *N) {
3866 EVT VT = N->getValueType(0);
3868 assert((VT.is128BitVector() || VT.is256BitVector()) &&
3869 "Unsupported vector type for PSHUF/SHUFP");
3871 // Handle 128 and 256-bit vector lengths. AVX defines PSHUF/SHUFP to operate
3872 // independently on 128-bit lanes.
3873 unsigned NumElts = VT.getVectorNumElements();
3874 unsigned NumLanes = VT.getSizeInBits()/128;
3875 unsigned NumLaneElts = NumElts/NumLanes;
3877 assert((NumLaneElts == 2 || NumLaneElts == 4) &&
3878 "Only supports 2 or 4 elements per lane");
3880 unsigned Shift = (NumLaneElts == 4) ? 1 : 0;
3882 for (unsigned i = 0; i != NumElts; ++i) {
3883 int Elt = N->getMaskElt(i);
3884 if (Elt < 0) continue;
3886 unsigned ShAmt = i << Shift;
3887 if (ShAmt >= 8) ShAmt -= 8;
3888 Mask |= Elt << ShAmt;
3894 /// getShufflePSHUFHWImmediate - Return the appropriate immediate to shuffle
3895 /// the specified VECTOR_SHUFFLE mask with the PSHUFHW instruction.
3896 static unsigned getShufflePSHUFHWImmediate(ShuffleVectorSDNode *N) {
3898 // 8 nodes, but we only care about the last 4.
3899 for (unsigned i = 7; i >= 4; --i) {
3900 int Val = N->getMaskElt(i);
3909 /// getShufflePSHUFLWImmediate - Return the appropriate immediate to shuffle
3910 /// the specified VECTOR_SHUFFLE mask with the PSHUFLW instruction.
3911 static unsigned getShufflePSHUFLWImmediate(ShuffleVectorSDNode *N) {
3913 // 8 nodes, but we only care about the first 4.
3914 for (int i = 3; i >= 0; --i) {
3915 int Val = N->getMaskElt(i);
3924 /// getShufflePALIGNRImmediate - Return the appropriate immediate to shuffle
3925 /// the specified VECTOR_SHUFFLE mask with the PALIGNR instruction.
3926 static unsigned getShufflePALIGNRImmediate(ShuffleVectorSDNode *SVOp) {
3927 EVT VT = SVOp->getValueType(0);
3928 unsigned EltSize = VT.getVectorElementType().getSizeInBits() >> 3;
3930 unsigned NumElts = VT.getVectorNumElements();
3931 unsigned NumLanes = VT.getSizeInBits()/128;
3932 unsigned NumLaneElts = NumElts/NumLanes;
3936 for (i = 0; i != NumElts; ++i) {
3937 Val = SVOp->getMaskElt(i);
3941 if (Val >= (int)NumElts)
3942 Val -= NumElts - NumLaneElts;
3944 assert(Val - i > 0 && "PALIGNR imm should be positive");
3945 return (Val - i) * EltSize;
3948 /// getExtractVEXTRACTF128Immediate - Return the appropriate immediate
3949 /// to extract the specified EXTRACT_SUBVECTOR index with VEXTRACTF128
3951 unsigned X86::getExtractVEXTRACTF128Immediate(SDNode *N) {
3952 if (!isa<ConstantSDNode>(N->getOperand(1).getNode()))
3953 llvm_unreachable("Illegal extract subvector for VEXTRACTF128");
3956 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
3958 EVT VecVT = N->getOperand(0).getValueType();
3959 EVT ElVT = VecVT.getVectorElementType();
3961 unsigned NumElemsPerChunk = 128 / ElVT.getSizeInBits();
3962 return Index / NumElemsPerChunk;
3965 /// getInsertVINSERTF128Immediate - Return the appropriate immediate
3966 /// to insert at the specified INSERT_SUBVECTOR index with VINSERTF128
3968 unsigned X86::getInsertVINSERTF128Immediate(SDNode *N) {
3969 if (!isa<ConstantSDNode>(N->getOperand(2).getNode()))
3970 llvm_unreachable("Illegal insert subvector for VINSERTF128");
3973 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
3975 EVT VecVT = N->getValueType(0);
3976 EVT ElVT = VecVT.getVectorElementType();
3978 unsigned NumElemsPerChunk = 128 / ElVT.getSizeInBits();
3979 return Index / NumElemsPerChunk;
3982 /// getShuffleCLImmediate - Return the appropriate immediate to shuffle
3983 /// the specified VECTOR_SHUFFLE mask with VPERMQ and VPERMPD instructions.
3984 /// Handles 256-bit.
3985 static unsigned getShuffleCLImmediate(ShuffleVectorSDNode *N) {
3986 EVT VT = N->getValueType(0);
3988 unsigned NumElts = VT.getVectorNumElements();
3990 assert((VT.is256BitVector() && NumElts == 4) &&
3991 "Unsupported vector type for VPERMQ/VPERMPD");
3994 for (unsigned i = 0; i != NumElts; ++i) {
3995 int Elt = N->getMaskElt(i);
3998 Mask |= Elt << (i*2);
4003 /// isZeroNode - Returns true if Elt is a constant zero or a floating point
4005 bool X86::isZeroNode(SDValue Elt) {
4006 return ((isa<ConstantSDNode>(Elt) &&
4007 cast<ConstantSDNode>(Elt)->isNullValue()) ||
4008 (isa<ConstantFPSDNode>(Elt) &&
4009 cast<ConstantFPSDNode>(Elt)->getValueAPF().isPosZero()));
4012 /// CommuteVectorShuffle - Swap vector_shuffle operands as well as values in
4013 /// their permute mask.
4014 static SDValue CommuteVectorShuffle(ShuffleVectorSDNode *SVOp,
4015 SelectionDAG &DAG) {
4016 EVT VT = SVOp->getValueType(0);
4017 unsigned NumElems = VT.getVectorNumElements();
4018 SmallVector<int, 8> MaskVec;
4020 for (unsigned i = 0; i != NumElems; ++i) {
4021 int idx = SVOp->getMaskElt(i);
4023 MaskVec.push_back(idx);
4024 else if (idx < (int)NumElems)
4025 MaskVec.push_back(idx + NumElems);
4027 MaskVec.push_back(idx - NumElems);
4029 return DAG.getVectorShuffle(VT, SVOp->getDebugLoc(), SVOp->getOperand(1),
4030 SVOp->getOperand(0), &MaskVec[0]);
4033 /// ShouldXformToMOVHLPS - Return true if the node should be transformed to
4034 /// match movhlps. The lower half elements should come from upper half of
4035 /// V1 (and in order), and the upper half elements should come from the upper
4036 /// half of V2 (and in order).
4037 static bool ShouldXformToMOVHLPS(ArrayRef<int> Mask, EVT VT) {
4038 if (VT.getSizeInBits() != 128)
4040 if (VT.getVectorNumElements() != 4)
4042 for (unsigned i = 0, e = 2; i != e; ++i)
4043 if (!isUndefOrEqual(Mask[i], i+2))
4045 for (unsigned i = 2; i != 4; ++i)
4046 if (!isUndefOrEqual(Mask[i], i+4))
4051 /// isScalarLoadToVector - Returns true if the node is a scalar load that
4052 /// is promoted to a vector. It also returns the LoadSDNode by reference if
4054 static bool isScalarLoadToVector(SDNode *N, LoadSDNode **LD = NULL) {
4055 if (N->getOpcode() != ISD::SCALAR_TO_VECTOR)
4057 N = N->getOperand(0).getNode();
4058 if (!ISD::isNON_EXTLoad(N))
4061 *LD = cast<LoadSDNode>(N);
4065 // Test whether the given value is a vector value which will be legalized
4067 static bool WillBeConstantPoolLoad(SDNode *N) {
4068 if (N->getOpcode() != ISD::BUILD_VECTOR)
4071 // Check for any non-constant elements.
4072 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
4073 switch (N->getOperand(i).getNode()->getOpcode()) {
4075 case ISD::ConstantFP:
4082 // Vectors of all-zeros and all-ones are materialized with special
4083 // instructions rather than being loaded.
4084 return !ISD::isBuildVectorAllZeros(N) &&
4085 !ISD::isBuildVectorAllOnes(N);
4088 /// ShouldXformToMOVLP{S|D} - Return true if the node should be transformed to
4089 /// match movlp{s|d}. The lower half elements should come from lower half of
4090 /// V1 (and in order), and the upper half elements should come from the upper
4091 /// half of V2 (and in order). And since V1 will become the source of the
4092 /// MOVLP, it must be either a vector load or a scalar load to vector.
4093 static bool ShouldXformToMOVLP(SDNode *V1, SDNode *V2,
4094 ArrayRef<int> Mask, EVT VT) {
4095 if (VT.getSizeInBits() != 128)
4098 if (!ISD::isNON_EXTLoad(V1) && !isScalarLoadToVector(V1))
4100 // Is V2 is a vector load, don't do this transformation. We will try to use
4101 // load folding shufps op.
4102 if (ISD::isNON_EXTLoad(V2) || WillBeConstantPoolLoad(V2))
4105 unsigned NumElems = VT.getVectorNumElements();
4107 if (NumElems != 2 && NumElems != 4)
4109 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
4110 if (!isUndefOrEqual(Mask[i], i))
4112 for (unsigned i = NumElems/2; i != NumElems; ++i)
4113 if (!isUndefOrEqual(Mask[i], i+NumElems))
4118 /// isSplatVector - Returns true if N is a BUILD_VECTOR node whose elements are
4120 static bool isSplatVector(SDNode *N) {
4121 if (N->getOpcode() != ISD::BUILD_VECTOR)
4124 SDValue SplatValue = N->getOperand(0);
4125 for (unsigned i = 1, e = N->getNumOperands(); i != e; ++i)
4126 if (N->getOperand(i) != SplatValue)
4131 /// isZeroShuffle - Returns true if N is a VECTOR_SHUFFLE that can be resolved
4132 /// to an zero vector.
4133 /// FIXME: move to dag combiner / method on ShuffleVectorSDNode
4134 static bool isZeroShuffle(ShuffleVectorSDNode *N) {
4135 SDValue V1 = N->getOperand(0);
4136 SDValue V2 = N->getOperand(1);
4137 unsigned NumElems = N->getValueType(0).getVectorNumElements();
4138 for (unsigned i = 0; i != NumElems; ++i) {
4139 int Idx = N->getMaskElt(i);
4140 if (Idx >= (int)NumElems) {
4141 unsigned Opc = V2.getOpcode();
4142 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V2.getNode()))
4144 if (Opc != ISD::BUILD_VECTOR ||
4145 !X86::isZeroNode(V2.getOperand(Idx-NumElems)))
4147 } else if (Idx >= 0) {
4148 unsigned Opc = V1.getOpcode();
4149 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V1.getNode()))
4151 if (Opc != ISD::BUILD_VECTOR ||
4152 !X86::isZeroNode(V1.getOperand(Idx)))
4159 /// getZeroVector - Returns a vector of specified type with all zero elements.
4161 static SDValue getZeroVector(EVT VT, const X86Subtarget *Subtarget,
4162 SelectionDAG &DAG, DebugLoc dl) {
4163 assert(VT.isVector() && "Expected a vector type");
4165 // Always build SSE zero vectors as <4 x i32> bitcasted
4166 // to their dest type. This ensures they get CSE'd.
4168 if (VT.getSizeInBits() == 128) { // SSE
4169 if (Subtarget->hasSSE2()) { // SSE2
4170 SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
4171 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4173 SDValue Cst = DAG.getTargetConstantFP(+0.0, MVT::f32);
4174 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4f32, Cst, Cst, Cst, Cst);
4176 } else if (VT.getSizeInBits() == 256) { // AVX
4177 if (Subtarget->hasAVX2()) { // AVX2
4178 SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
4179 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4180 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops, 8);
4182 // 256-bit logic and arithmetic instructions in AVX are all
4183 // floating-point, no support for integer ops. Emit fp zeroed vectors.
4184 SDValue Cst = DAG.getTargetConstantFP(+0.0, MVT::f32);
4185 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4186 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8f32, Ops, 8);
4189 return DAG.getNode(ISD::BITCAST, dl, VT, Vec);
4192 /// getOnesVector - Returns a vector of specified type with all bits set.
4193 /// Always build ones vectors as <4 x i32> or <8 x i32>. For 256-bit types with
4194 /// no AVX2 supprt, use two <4 x i32> inserted in a <8 x i32> appropriately.
4195 /// Then bitcast to their original type, ensuring they get CSE'd.
4196 static SDValue getOnesVector(EVT VT, bool HasAVX2, SelectionDAG &DAG,
4198 assert(VT.isVector() && "Expected a vector type");
4199 assert((VT.is128BitVector() || VT.is256BitVector())
4200 && "Expected a 128-bit or 256-bit vector type");
4202 SDValue Cst = DAG.getTargetConstant(~0U, MVT::i32);
4204 if (VT.getSizeInBits() == 256) {
4205 if (HasAVX2) { // AVX2
4206 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4207 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops, 8);
4209 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4210 SDValue InsV = Insert128BitVector(DAG.getNode(ISD::UNDEF, dl, MVT::v8i32),
4211 Vec, DAG.getConstant(0, MVT::i32), DAG, dl);
4212 Vec = Insert128BitVector(InsV, Vec,
4213 DAG.getConstant(4 /* NumElems/2 */, MVT::i32), DAG, dl);
4216 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4219 return DAG.getNode(ISD::BITCAST, dl, VT, Vec);
4222 /// NormalizeMask - V2 is a splat, modify the mask (if needed) so all elements
4223 /// that point to V2 points to its first element.
4224 static void NormalizeMask(SmallVectorImpl<int> &Mask, unsigned NumElems) {
4225 for (unsigned i = 0; i != NumElems; ++i) {
4226 if (Mask[i] > (int)NumElems) {
4232 /// getMOVLMask - Returns a vector_shuffle mask for an movs{s|d}, movd
4233 /// operation of specified width.
4234 static SDValue getMOVL(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1,
4236 unsigned NumElems = VT.getVectorNumElements();
4237 SmallVector<int, 8> Mask;
4238 Mask.push_back(NumElems);
4239 for (unsigned i = 1; i != NumElems; ++i)
4241 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
4244 /// getUnpackl - Returns a vector_shuffle node for an unpackl operation.
4245 static SDValue getUnpackl(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1,
4247 unsigned NumElems = VT.getVectorNumElements();
4248 SmallVector<int, 8> Mask;
4249 for (unsigned i = 0, e = NumElems/2; i != e; ++i) {
4251 Mask.push_back(i + NumElems);
4253 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
4256 /// getUnpackh - Returns a vector_shuffle node for an unpackh operation.
4257 static SDValue getUnpackh(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1,
4259 unsigned NumElems = VT.getVectorNumElements();
4260 unsigned Half = NumElems/2;
4261 SmallVector<int, 8> Mask;
4262 for (unsigned i = 0; i != Half; ++i) {
4263 Mask.push_back(i + Half);
4264 Mask.push_back(i + NumElems + Half);
4266 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
4269 // PromoteSplati8i16 - All i16 and i8 vector types can't be used directly by
4270 // a generic shuffle instruction because the target has no such instructions.
4271 // Generate shuffles which repeat i16 and i8 several times until they can be
4272 // represented by v4f32 and then be manipulated by target suported shuffles.
4273 static SDValue PromoteSplati8i16(SDValue V, SelectionDAG &DAG, int &EltNo) {
4274 EVT VT = V.getValueType();
4275 int NumElems = VT.getVectorNumElements();
4276 DebugLoc dl = V.getDebugLoc();
4278 while (NumElems > 4) {
4279 if (EltNo < NumElems/2) {
4280 V = getUnpackl(DAG, dl, VT, V, V);
4282 V = getUnpackh(DAG, dl, VT, V, V);
4283 EltNo -= NumElems/2;
4290 /// getLegalSplat - Generate a legal splat with supported x86 shuffles
4291 static SDValue getLegalSplat(SelectionDAG &DAG, SDValue V, int EltNo) {
4292 EVT VT = V.getValueType();
4293 DebugLoc dl = V.getDebugLoc();
4294 assert((VT.getSizeInBits() == 128 || VT.getSizeInBits() == 256)
4295 && "Vector size not supported");
4297 if (VT.getSizeInBits() == 128) {
4298 V = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V);
4299 int SplatMask[4] = { EltNo, EltNo, EltNo, EltNo };
4300 V = DAG.getVectorShuffle(MVT::v4f32, dl, V, DAG.getUNDEF(MVT::v4f32),
4303 // To use VPERMILPS to splat scalars, the second half of indicies must
4304 // refer to the higher part, which is a duplication of the lower one,
4305 // because VPERMILPS can only handle in-lane permutations.
4306 int SplatMask[8] = { EltNo, EltNo, EltNo, EltNo,
4307 EltNo+4, EltNo+4, EltNo+4, EltNo+4 };
4309 V = DAG.getNode(ISD::BITCAST, dl, MVT::v8f32, V);
4310 V = DAG.getVectorShuffle(MVT::v8f32, dl, V, DAG.getUNDEF(MVT::v8f32),
4314 return DAG.getNode(ISD::BITCAST, dl, VT, V);
4317 /// PromoteSplat - Splat is promoted to target supported vector shuffles.
4318 static SDValue PromoteSplat(ShuffleVectorSDNode *SV, SelectionDAG &DAG) {
4319 EVT SrcVT = SV->getValueType(0);
4320 SDValue V1 = SV->getOperand(0);
4321 DebugLoc dl = SV->getDebugLoc();
4323 int EltNo = SV->getSplatIndex();
4324 int NumElems = SrcVT.getVectorNumElements();
4325 unsigned Size = SrcVT.getSizeInBits();
4327 assert(((Size == 128 && NumElems > 4) || Size == 256) &&
4328 "Unknown how to promote splat for type");
4330 // Extract the 128-bit part containing the splat element and update
4331 // the splat element index when it refers to the higher register.
4333 unsigned Idx = (EltNo >= NumElems/2) ? NumElems/2 : 0;
4334 V1 = Extract128BitVector(V1, DAG.getConstant(Idx, MVT::i32), DAG, dl);
4336 EltNo -= NumElems/2;
4339 // All i16 and i8 vector types can't be used directly by a generic shuffle
4340 // instruction because the target has no such instruction. Generate shuffles
4341 // which repeat i16 and i8 several times until they fit in i32, and then can
4342 // be manipulated by target suported shuffles.
4343 EVT EltVT = SrcVT.getVectorElementType();
4344 if (EltVT == MVT::i8 || EltVT == MVT::i16)
4345 V1 = PromoteSplati8i16(V1, DAG, EltNo);
4347 // Recreate the 256-bit vector and place the same 128-bit vector
4348 // into the low and high part. This is necessary because we want
4349 // to use VPERM* to shuffle the vectors
4351 SDValue InsV = Insert128BitVector(DAG.getUNDEF(SrcVT), V1,
4352 DAG.getConstant(0, MVT::i32), DAG, dl);
4353 V1 = Insert128BitVector(InsV, V1,
4354 DAG.getConstant(NumElems/2, MVT::i32), DAG, dl);
4357 return getLegalSplat(DAG, V1, EltNo);
4360 /// getShuffleVectorZeroOrUndef - Return a vector_shuffle of the specified
4361 /// vector of zero or undef vector. This produces a shuffle where the low
4362 /// element of V2 is swizzled into the zero/undef vector, landing at element
4363 /// Idx. This produces a shuffle mask like 4,1,2,3 (idx=0) or 0,1,2,4 (idx=3).
4364 static SDValue getShuffleVectorZeroOrUndef(SDValue V2, unsigned Idx,
4366 const X86Subtarget *Subtarget,
4367 SelectionDAG &DAG) {
4368 EVT VT = V2.getValueType();
4370 ? getZeroVector(VT, Subtarget, DAG, V2.getDebugLoc()) : DAG.getUNDEF(VT);
4371 unsigned NumElems = VT.getVectorNumElements();
4372 SmallVector<int, 16> MaskVec;
4373 for (unsigned i = 0; i != NumElems; ++i)
4374 // If this is the insertion idx, put the low elt of V2 here.
4375 MaskVec.push_back(i == Idx ? NumElems : i);
4376 return DAG.getVectorShuffle(VT, V2.getDebugLoc(), V1, V2, &MaskVec[0]);
4379 /// getTargetShuffleMask - Calculates the shuffle mask corresponding to the
4380 /// target specific opcode. Returns true if the Mask could be calculated.
4381 /// Sets IsUnary to true if only uses one source.
4382 static bool getTargetShuffleMask(SDNode *N, EVT VT,
4383 SmallVectorImpl<int> &Mask, bool &IsUnary) {
4384 unsigned NumElems = VT.getVectorNumElements();
4388 switch(N->getOpcode()) {
4390 ImmN = N->getOperand(N->getNumOperands()-1);
4391 DecodeSHUFPMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4393 case X86ISD::UNPCKH:
4394 DecodeUNPCKHMask(VT, Mask);
4396 case X86ISD::UNPCKL:
4397 DecodeUNPCKLMask(VT, Mask);
4399 case X86ISD::MOVHLPS:
4400 DecodeMOVHLPSMask(NumElems, Mask);
4402 case X86ISD::MOVLHPS:
4403 DecodeMOVLHPSMask(NumElems, Mask);
4405 case X86ISD::PSHUFD:
4406 case X86ISD::VPERMILP:
4407 ImmN = N->getOperand(N->getNumOperands()-1);
4408 DecodePSHUFMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4411 case X86ISD::PSHUFHW:
4412 ImmN = N->getOperand(N->getNumOperands()-1);
4413 DecodePSHUFHWMask(cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4416 case X86ISD::PSHUFLW:
4417 ImmN = N->getOperand(N->getNumOperands()-1);
4418 DecodePSHUFLWMask(cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4422 case X86ISD::MOVSD: {
4423 // The index 0 always comes from the first element of the second source,
4424 // this is why MOVSS and MOVSD are used in the first place. The other
4425 // elements come from the other positions of the first source vector
4426 Mask.push_back(NumElems);
4427 for (unsigned i = 1; i != NumElems; ++i) {
4432 case X86ISD::VPERM2X128:
4433 ImmN = N->getOperand(N->getNumOperands()-1);
4434 DecodeVPERM2X128Mask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4435 if (Mask.empty()) return false;
4437 case X86ISD::MOVDDUP:
4438 case X86ISD::MOVLHPD:
4439 case X86ISD::MOVLPD:
4440 case X86ISD::MOVLPS:
4441 case X86ISD::MOVSHDUP:
4442 case X86ISD::MOVSLDUP:
4443 case X86ISD::PALIGN:
4444 // Not yet implemented
4446 default: llvm_unreachable("unknown target shuffle node");
4452 /// getShuffleScalarElt - Returns the scalar element that will make up the ith
4453 /// element of the result of the vector shuffle.
4454 static SDValue getShuffleScalarElt(SDNode *N, unsigned Index, SelectionDAG &DAG,
4457 return SDValue(); // Limit search depth.
4459 SDValue V = SDValue(N, 0);
4460 EVT VT = V.getValueType();
4461 unsigned Opcode = V.getOpcode();
4463 // Recurse into ISD::VECTOR_SHUFFLE node to find scalars.
4464 if (const ShuffleVectorSDNode *SV = dyn_cast<ShuffleVectorSDNode>(N)) {
4465 int Elt = SV->getMaskElt(Index);
4468 return DAG.getUNDEF(VT.getVectorElementType());
4470 unsigned NumElems = VT.getVectorNumElements();
4471 SDValue NewV = (Elt < (int)NumElems) ? SV->getOperand(0)
4472 : SV->getOperand(1);
4473 return getShuffleScalarElt(NewV.getNode(), Elt % NumElems, DAG, Depth+1);
4476 // Recurse into target specific vector shuffles to find scalars.
4477 if (isTargetShuffle(Opcode)) {
4478 unsigned NumElems = VT.getVectorNumElements();
4479 SmallVector<int, 16> ShuffleMask;
4483 if (!getTargetShuffleMask(N, VT, ShuffleMask, IsUnary))
4486 int Elt = ShuffleMask[Index];
4488 return DAG.getUNDEF(VT.getVectorElementType());
4490 SDValue NewV = (Elt < (int)NumElems) ? N->getOperand(0)
4492 return getShuffleScalarElt(NewV.getNode(), Elt % NumElems, DAG,
4496 // Actual nodes that may contain scalar elements
4497 if (Opcode == ISD::BITCAST) {
4498 V = V.getOperand(0);
4499 EVT SrcVT = V.getValueType();
4500 unsigned NumElems = VT.getVectorNumElements();
4502 if (!SrcVT.isVector() || SrcVT.getVectorNumElements() != NumElems)
4506 if (V.getOpcode() == ISD::SCALAR_TO_VECTOR)
4507 return (Index == 0) ? V.getOperand(0)
4508 : DAG.getUNDEF(VT.getVectorElementType());
4510 if (V.getOpcode() == ISD::BUILD_VECTOR)
4511 return V.getOperand(Index);
4516 /// getNumOfConsecutiveZeros - Return the number of elements of a vector
4517 /// shuffle operation which come from a consecutively from a zero. The
4518 /// search can start in two different directions, from left or right.
4520 unsigned getNumOfConsecutiveZeros(ShuffleVectorSDNode *SVOp, unsigned NumElems,
4521 bool ZerosFromLeft, SelectionDAG &DAG) {
4523 for (i = 0; i != NumElems; ++i) {
4524 unsigned Index = ZerosFromLeft ? i : NumElems-i-1;
4525 SDValue Elt = getShuffleScalarElt(SVOp, Index, DAG, 0);
4526 if (!(Elt.getNode() &&
4527 (Elt.getOpcode() == ISD::UNDEF || X86::isZeroNode(Elt))))
4534 /// isShuffleMaskConsecutive - Check if the shuffle mask indicies [MaskI, MaskE)
4535 /// correspond consecutively to elements from one of the vector operands,
4536 /// starting from its index OpIdx. Also tell OpNum which source vector operand.
4538 bool isShuffleMaskConsecutive(ShuffleVectorSDNode *SVOp,
4539 unsigned MaskI, unsigned MaskE, unsigned OpIdx,
4540 unsigned NumElems, unsigned &OpNum) {
4541 bool SeenV1 = false;
4542 bool SeenV2 = false;
4544 for (unsigned i = MaskI; i != MaskE; ++i, ++OpIdx) {
4545 int Idx = SVOp->getMaskElt(i);
4546 // Ignore undef indicies
4550 if (Idx < (int)NumElems)
4555 // Only accept consecutive elements from the same vector
4556 if ((Idx % NumElems != OpIdx) || (SeenV1 && SeenV2))
4560 OpNum = SeenV1 ? 0 : 1;
4564 /// isVectorShiftRight - Returns true if the shuffle can be implemented as a
4565 /// logical left shift of a vector.
4566 static bool isVectorShiftRight(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
4567 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
4568 unsigned NumElems = SVOp->getValueType(0).getVectorNumElements();
4569 unsigned NumZeros = getNumOfConsecutiveZeros(SVOp, NumElems,
4570 false /* check zeros from right */, DAG);
4576 // Considering the elements in the mask that are not consecutive zeros,
4577 // check if they consecutively come from only one of the source vectors.
4579 // V1 = {X, A, B, C} 0
4581 // vector_shuffle V1, V2 <1, 2, 3, X>
4583 if (!isShuffleMaskConsecutive(SVOp,
4584 0, // Mask Start Index
4585 NumElems-NumZeros, // Mask End Index(exclusive)
4586 NumZeros, // Where to start looking in the src vector
4587 NumElems, // Number of elements in vector
4588 OpSrc)) // Which source operand ?
4593 ShVal = SVOp->getOperand(OpSrc);
4597 /// isVectorShiftLeft - Returns true if the shuffle can be implemented as a
4598 /// logical left shift of a vector.
4599 static bool isVectorShiftLeft(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
4600 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
4601 unsigned NumElems = SVOp->getValueType(0).getVectorNumElements();
4602 unsigned NumZeros = getNumOfConsecutiveZeros(SVOp, NumElems,
4603 true /* check zeros from left */, DAG);
4609 // Considering the elements in the mask that are not consecutive zeros,
4610 // check if they consecutively come from only one of the source vectors.
4612 // 0 { A, B, X, X } = V2
4614 // vector_shuffle V1, V2 <X, X, 4, 5>
4616 if (!isShuffleMaskConsecutive(SVOp,
4617 NumZeros, // Mask Start Index
4618 NumElems, // Mask End Index(exclusive)
4619 0, // Where to start looking in the src vector
4620 NumElems, // Number of elements in vector
4621 OpSrc)) // Which source operand ?
4626 ShVal = SVOp->getOperand(OpSrc);
4630 /// isVectorShift - Returns true if the shuffle can be implemented as a
4631 /// logical left or right shift of a vector.
4632 static bool isVectorShift(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
4633 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
4634 // Although the logic below support any bitwidth size, there are no
4635 // shift instructions which handle more than 128-bit vectors.
4636 if (SVOp->getValueType(0).getSizeInBits() > 128)
4639 if (isVectorShiftLeft(SVOp, DAG, isLeft, ShVal, ShAmt) ||
4640 isVectorShiftRight(SVOp, DAG, isLeft, ShVal, ShAmt))
4646 /// LowerBuildVectorv16i8 - Custom lower build_vector of v16i8.
4648 static SDValue LowerBuildVectorv16i8(SDValue Op, unsigned NonZeros,
4649 unsigned NumNonZero, unsigned NumZero,
4651 const X86Subtarget* Subtarget,
4652 const TargetLowering &TLI) {
4656 DebugLoc dl = Op.getDebugLoc();
4659 for (unsigned i = 0; i < 16; ++i) {
4660 bool ThisIsNonZero = (NonZeros & (1 << i)) != 0;
4661 if (ThisIsNonZero && First) {
4663 V = getZeroVector(MVT::v8i16, Subtarget, DAG, dl);
4665 V = DAG.getUNDEF(MVT::v8i16);
4670 SDValue ThisElt(0, 0), LastElt(0, 0);
4671 bool LastIsNonZero = (NonZeros & (1 << (i-1))) != 0;
4672 if (LastIsNonZero) {
4673 LastElt = DAG.getNode(ISD::ZERO_EXTEND, dl,
4674 MVT::i16, Op.getOperand(i-1));
4676 if (ThisIsNonZero) {
4677 ThisElt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, Op.getOperand(i));
4678 ThisElt = DAG.getNode(ISD::SHL, dl, MVT::i16,
4679 ThisElt, DAG.getConstant(8, MVT::i8));
4681 ThisElt = DAG.getNode(ISD::OR, dl, MVT::i16, ThisElt, LastElt);
4685 if (ThisElt.getNode())
4686 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, V, ThisElt,
4687 DAG.getIntPtrConstant(i/2));
4691 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V);
4694 /// LowerBuildVectorv8i16 - Custom lower build_vector of v8i16.
4696 static SDValue LowerBuildVectorv8i16(SDValue Op, unsigned NonZeros,
4697 unsigned NumNonZero, unsigned NumZero,
4699 const X86Subtarget* Subtarget,
4700 const TargetLowering &TLI) {
4704 DebugLoc dl = Op.getDebugLoc();
4707 for (unsigned i = 0; i < 8; ++i) {
4708 bool isNonZero = (NonZeros & (1 << i)) != 0;
4712 V = getZeroVector(MVT::v8i16, Subtarget, DAG, dl);
4714 V = DAG.getUNDEF(MVT::v8i16);
4717 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl,
4718 MVT::v8i16, V, Op.getOperand(i),
4719 DAG.getIntPtrConstant(i));
4726 /// getVShift - Return a vector logical shift node.
4728 static SDValue getVShift(bool isLeft, EVT VT, SDValue SrcOp,
4729 unsigned NumBits, SelectionDAG &DAG,
4730 const TargetLowering &TLI, DebugLoc dl) {
4731 assert(VT.getSizeInBits() == 128 && "Unknown type for VShift");
4732 EVT ShVT = MVT::v2i64;
4733 unsigned Opc = isLeft ? X86ISD::VSHLDQ : X86ISD::VSRLDQ;
4734 SrcOp = DAG.getNode(ISD::BITCAST, dl, ShVT, SrcOp);
4735 return DAG.getNode(ISD::BITCAST, dl, VT,
4736 DAG.getNode(Opc, dl, ShVT, SrcOp,
4737 DAG.getConstant(NumBits,
4738 TLI.getShiftAmountTy(SrcOp.getValueType()))));
4742 X86TargetLowering::LowerAsSplatVectorLoad(SDValue SrcOp, EVT VT, DebugLoc dl,
4743 SelectionDAG &DAG) const {
4745 // Check if the scalar load can be widened into a vector load. And if
4746 // the address is "base + cst" see if the cst can be "absorbed" into
4747 // the shuffle mask.
4748 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(SrcOp)) {
4749 SDValue Ptr = LD->getBasePtr();
4750 if (!ISD::isNormalLoad(LD) || LD->isVolatile())
4752 EVT PVT = LD->getValueType(0);
4753 if (PVT != MVT::i32 && PVT != MVT::f32)
4758 if (FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr)) {
4759 FI = FINode->getIndex();
4761 } else if (DAG.isBaseWithConstantOffset(Ptr) &&
4762 isa<FrameIndexSDNode>(Ptr.getOperand(0))) {
4763 FI = cast<FrameIndexSDNode>(Ptr.getOperand(0))->getIndex();
4764 Offset = Ptr.getConstantOperandVal(1);
4765 Ptr = Ptr.getOperand(0);
4770 // FIXME: 256-bit vector instructions don't require a strict alignment,
4771 // improve this code to support it better.
4772 unsigned RequiredAlign = VT.getSizeInBits()/8;
4773 SDValue Chain = LD->getChain();
4774 // Make sure the stack object alignment is at least 16 or 32.
4775 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
4776 if (DAG.InferPtrAlignment(Ptr) < RequiredAlign) {
4777 if (MFI->isFixedObjectIndex(FI)) {
4778 // Can't change the alignment. FIXME: It's possible to compute
4779 // the exact stack offset and reference FI + adjust offset instead.
4780 // If someone *really* cares about this. That's the way to implement it.
4783 MFI->setObjectAlignment(FI, RequiredAlign);
4787 // (Offset % 16 or 32) must be multiple of 4. Then address is then
4788 // Ptr + (Offset & ~15).
4791 if ((Offset % RequiredAlign) & 3)
4793 int64_t StartOffset = Offset & ~(RequiredAlign-1);
4795 Ptr = DAG.getNode(ISD::ADD, Ptr.getDebugLoc(), Ptr.getValueType(),
4796 Ptr,DAG.getConstant(StartOffset, Ptr.getValueType()));
4798 int EltNo = (Offset - StartOffset) >> 2;
4799 int NumElems = VT.getVectorNumElements();
4801 EVT NVT = EVT::getVectorVT(*DAG.getContext(), PVT, NumElems);
4802 SDValue V1 = DAG.getLoad(NVT, dl, Chain, Ptr,
4803 LD->getPointerInfo().getWithOffset(StartOffset),
4804 false, false, false, 0);
4806 SmallVector<int, 8> Mask;
4807 for (int i = 0; i < NumElems; ++i)
4808 Mask.push_back(EltNo);
4810 return DAG.getVectorShuffle(NVT, dl, V1, DAG.getUNDEF(NVT), &Mask[0]);
4816 /// EltsFromConsecutiveLoads - Given the initializing elements 'Elts' of a
4817 /// vector of type 'VT', see if the elements can be replaced by a single large
4818 /// load which has the same value as a build_vector whose operands are 'elts'.
4820 /// Example: <load i32 *a, load i32 *a+4, undef, undef> -> zextload a
4822 /// FIXME: we'd also like to handle the case where the last elements are zero
4823 /// rather than undef via VZEXT_LOAD, but we do not detect that case today.
4824 /// There's even a handy isZeroNode for that purpose.
4825 static SDValue EltsFromConsecutiveLoads(EVT VT, SmallVectorImpl<SDValue> &Elts,
4826 DebugLoc &DL, SelectionDAG &DAG) {
4827 EVT EltVT = VT.getVectorElementType();
4828 unsigned NumElems = Elts.size();
4830 LoadSDNode *LDBase = NULL;
4831 unsigned LastLoadedElt = -1U;
4833 // For each element in the initializer, see if we've found a load or an undef.
4834 // If we don't find an initial load element, or later load elements are
4835 // non-consecutive, bail out.
4836 for (unsigned i = 0; i < NumElems; ++i) {
4837 SDValue Elt = Elts[i];
4839 if (!Elt.getNode() ||
4840 (Elt.getOpcode() != ISD::UNDEF && !ISD::isNON_EXTLoad(Elt.getNode())))
4843 if (Elt.getNode()->getOpcode() == ISD::UNDEF)
4845 LDBase = cast<LoadSDNode>(Elt.getNode());
4849 if (Elt.getOpcode() == ISD::UNDEF)
4852 LoadSDNode *LD = cast<LoadSDNode>(Elt);
4853 if (!DAG.isConsecutiveLoad(LD, LDBase, EltVT.getSizeInBits()/8, i))
4858 // If we have found an entire vector of loads and undefs, then return a large
4859 // load of the entire vector width starting at the base pointer. If we found
4860 // consecutive loads for the low half, generate a vzext_load node.
4861 if (LastLoadedElt == NumElems - 1) {
4862 if (DAG.InferPtrAlignment(LDBase->getBasePtr()) >= 16)
4863 return DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(),
4864 LDBase->getPointerInfo(),
4865 LDBase->isVolatile(), LDBase->isNonTemporal(),
4866 LDBase->isInvariant(), 0);
4867 return DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(),
4868 LDBase->getPointerInfo(),
4869 LDBase->isVolatile(), LDBase->isNonTemporal(),
4870 LDBase->isInvariant(), LDBase->getAlignment());
4871 } else if (NumElems == 4 && LastLoadedElt == 1 &&
4872 DAG.getTargetLoweringInfo().isTypeLegal(MVT::v2i64)) {
4873 SDVTList Tys = DAG.getVTList(MVT::v2i64, MVT::Other);
4874 SDValue Ops[] = { LDBase->getChain(), LDBase->getBasePtr() };
4876 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, DL, Tys, Ops, 2, MVT::i64,
4877 LDBase->getPointerInfo(),
4878 LDBase->getAlignment(),
4879 false/*isVolatile*/, true/*ReadMem*/,
4881 return DAG.getNode(ISD::BITCAST, DL, VT, ResNode);
4886 /// LowerVectorBroadcast - Attempt to use the vbroadcast instruction
4887 /// to generate a splat value for the following cases:
4888 /// 1. A splat BUILD_VECTOR which uses a single scalar load, or a constant.
4889 /// 2. A splat shuffle which uses a scalar_to_vector node which comes from
4890 /// a scalar load, or a constant.
4891 /// The VBROADCAST node is returned when a pattern is found,
4892 /// or SDValue() otherwise.
4894 X86TargetLowering::LowerVectorBroadcast(SDValue &Op, SelectionDAG &DAG) const {
4895 if (!Subtarget->hasAVX())
4898 EVT VT = Op.getValueType();
4899 DebugLoc dl = Op.getDebugLoc();
4904 switch (Op.getOpcode()) {
4906 // Unknown pattern found.
4909 case ISD::BUILD_VECTOR: {
4910 // The BUILD_VECTOR node must be a splat.
4911 if (!isSplatVector(Op.getNode()))
4914 Ld = Op.getOperand(0);
4915 ConstSplatVal = (Ld.getOpcode() == ISD::Constant ||
4916 Ld.getOpcode() == ISD::ConstantFP);
4918 // The suspected load node has several users. Make sure that all
4919 // of its users are from the BUILD_VECTOR node.
4920 // Constants may have multiple users.
4921 if (!ConstSplatVal && !Ld->hasNUsesOfValue(VT.getVectorNumElements(), 0))
4926 case ISD::VECTOR_SHUFFLE: {
4927 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
4929 // Shuffles must have a splat mask where the first element is
4931 if ((!SVOp->isSplat()) || SVOp->getMaskElt(0) != 0)
4934 SDValue Sc = Op.getOperand(0);
4935 if (Sc.getOpcode() != ISD::SCALAR_TO_VECTOR)
4938 Ld = Sc.getOperand(0);
4939 ConstSplatVal = (Ld.getOpcode() == ISD::Constant ||
4940 Ld.getOpcode() == ISD::ConstantFP);
4942 // The scalar_to_vector node and the suspected
4943 // load node must have exactly one user.
4944 // Constants may have multiple users.
4945 if (!ConstSplatVal && (!Sc.hasOneUse() || !Ld.hasOneUse()))
4951 bool Is256 = VT.getSizeInBits() == 256;
4952 bool Is128 = VT.getSizeInBits() == 128;
4954 // Handle the broadcasting a single constant scalar from the constant pool
4955 // into a vector. On Sandybridge it is still better to load a constant vector
4956 // from the constant pool and not to broadcast it from a scalar.
4957 if (ConstSplatVal && Subtarget->hasAVX2()) {
4958 EVT CVT = Ld.getValueType();
4959 assert(!CVT.isVector() && "Must not broadcast a vector type");
4960 unsigned ScalarSize = CVT.getSizeInBits();
4962 if ((Is256 && (ScalarSize == 32 || ScalarSize == 64)) ||
4963 (Is128 && (ScalarSize == 32))) {
4965 const Constant *C = 0;
4966 if (ConstantSDNode *CI = dyn_cast<ConstantSDNode>(Ld))
4967 C = CI->getConstantIntValue();
4968 else if (ConstantFPSDNode *CF = dyn_cast<ConstantFPSDNode>(Ld))
4969 C = CF->getConstantFPValue();
4971 assert(C && "Invalid constant type");
4973 SDValue CP = DAG.getConstantPool(C, getPointerTy());
4974 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
4975 Ld = DAG.getLoad(CVT, dl, DAG.getEntryNode(), CP,
4976 MachinePointerInfo::getConstantPool(),
4977 false, false, false, Alignment);
4979 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
4983 // The scalar source must be a normal load.
4984 if (!ISD::isNormalLoad(Ld.getNode()))
4987 // Reject loads that have uses of the chain result
4988 if (Ld->hasAnyUseOfValue(1))
4991 unsigned ScalarSize = Ld.getValueType().getSizeInBits();
4993 // VBroadcast to YMM
4994 if (Is256 && (ScalarSize == 32 || ScalarSize == 64))
4995 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
4997 // VBroadcast to XMM
4998 if (Is128 && (ScalarSize == 32))
4999 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5001 // The integer check is needed for the 64-bit into 128-bit so it doesn't match
5002 // double since there is vbroadcastsd xmm
5003 if (Subtarget->hasAVX2() && Ld.getValueType().isInteger()) {
5004 // VBroadcast to YMM
5005 if (Is256 && (ScalarSize == 8 || ScalarSize == 16))
5006 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5008 // VBroadcast to XMM
5009 if (Is128 && (ScalarSize == 8 || ScalarSize == 16 || ScalarSize == 64))
5010 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5013 // Unsupported broadcast.
5018 X86TargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const {
5019 DebugLoc dl = Op.getDebugLoc();
5021 EVT VT = Op.getValueType();
5022 EVT ExtVT = VT.getVectorElementType();
5023 unsigned NumElems = Op.getNumOperands();
5025 // Vectors containing all zeros can be matched by pxor and xorps later
5026 if (ISD::isBuildVectorAllZeros(Op.getNode())) {
5027 // Canonicalize this to <4 x i32> to 1) ensure the zero vectors are CSE'd
5028 // and 2) ensure that i64 scalars are eliminated on x86-32 hosts.
5029 if (VT == MVT::v4i32 || VT == MVT::v8i32)
5032 return getZeroVector(VT, Subtarget, DAG, dl);
5035 // Vectors containing all ones can be matched by pcmpeqd on 128-bit width
5036 // vectors or broken into v4i32 operations on 256-bit vectors. AVX2 can use
5037 // vpcmpeqd on 256-bit vectors.
5038 if (ISD::isBuildVectorAllOnes(Op.getNode())) {
5039 if (VT == MVT::v4i32 || (VT == MVT::v8i32 && Subtarget->hasAVX2()))
5042 return getOnesVector(VT, Subtarget->hasAVX2(), DAG, dl);
5045 SDValue Broadcast = LowerVectorBroadcast(Op, DAG);
5046 if (Broadcast.getNode())
5049 unsigned EVTBits = ExtVT.getSizeInBits();
5051 unsigned NumZero = 0;
5052 unsigned NumNonZero = 0;
5053 unsigned NonZeros = 0;
5054 bool IsAllConstants = true;
5055 SmallSet<SDValue, 8> Values;
5056 for (unsigned i = 0; i < NumElems; ++i) {
5057 SDValue Elt = Op.getOperand(i);
5058 if (Elt.getOpcode() == ISD::UNDEF)
5061 if (Elt.getOpcode() != ISD::Constant &&
5062 Elt.getOpcode() != ISD::ConstantFP)
5063 IsAllConstants = false;
5064 if (X86::isZeroNode(Elt))
5067 NonZeros |= (1 << i);
5072 // All undef vector. Return an UNDEF. All zero vectors were handled above.
5073 if (NumNonZero == 0)
5074 return DAG.getUNDEF(VT);
5076 // Special case for single non-zero, non-undef, element.
5077 if (NumNonZero == 1) {
5078 unsigned Idx = CountTrailingZeros_32(NonZeros);
5079 SDValue Item = Op.getOperand(Idx);
5081 // If this is an insertion of an i64 value on x86-32, and if the top bits of
5082 // the value are obviously zero, truncate the value to i32 and do the
5083 // insertion that way. Only do this if the value is non-constant or if the
5084 // value is a constant being inserted into element 0. It is cheaper to do
5085 // a constant pool load than it is to do a movd + shuffle.
5086 if (ExtVT == MVT::i64 && !Subtarget->is64Bit() &&
5087 (!IsAllConstants || Idx == 0)) {
5088 if (DAG.MaskedValueIsZero(Item, APInt::getBitsSet(64, 32, 64))) {
5090 assert(VT == MVT::v2i64 && "Expected an SSE value type!");
5091 EVT VecVT = MVT::v4i32;
5092 unsigned VecElts = 4;
5094 // Truncate the value (which may itself be a constant) to i32, and
5095 // convert it to a vector with movd (S2V+shuffle to zero extend).
5096 Item = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Item);
5097 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Item);
5098 Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
5100 // Now we have our 32-bit value zero extended in the low element of
5101 // a vector. If Idx != 0, swizzle it into place.
5103 SmallVector<int, 4> Mask;
5104 Mask.push_back(Idx);
5105 for (unsigned i = 1; i != VecElts; ++i)
5107 Item = DAG.getVectorShuffle(VecVT, dl, Item,
5108 DAG.getUNDEF(Item.getValueType()),
5111 return DAG.getNode(ISD::BITCAST, dl, VT, Item);
5115 // If we have a constant or non-constant insertion into the low element of
5116 // a vector, we can do this with SCALAR_TO_VECTOR + shuffle of zero into
5117 // the rest of the elements. This will be matched as movd/movq/movss/movsd
5118 // depending on what the source datatype is.
5121 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
5123 if (ExtVT == MVT::i32 || ExtVT == MVT::f32 || ExtVT == MVT::f64 ||
5124 (ExtVT == MVT::i64 && Subtarget->is64Bit())) {
5125 if (VT.getSizeInBits() == 256) {
5126 SDValue ZeroVec = getZeroVector(VT, Subtarget, DAG, dl);
5127 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, ZeroVec,
5128 Item, DAG.getIntPtrConstant(0));
5130 assert(VT.getSizeInBits() == 128 && "Expected an SSE value type!");
5131 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
5132 // Turn it into a MOVL (i.e. movss, movsd, or movd) to a zero vector.
5133 return getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
5136 if (ExtVT == MVT::i16 || ExtVT == MVT::i8) {
5137 Item = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Item);
5138 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, Item);
5139 if (VT.getSizeInBits() == 256) {
5140 SDValue ZeroVec = getZeroVector(MVT::v8i32, Subtarget, DAG, dl);
5141 Item = Insert128BitVector(ZeroVec, Item, DAG.getConstant(0, MVT::i32),
5144 assert(VT.getSizeInBits() == 128 && "Expected an SSE value type!");
5145 Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
5147 return DAG.getNode(ISD::BITCAST, dl, VT, Item);
5151 // Is it a vector logical left shift?
5152 if (NumElems == 2 && Idx == 1 &&
5153 X86::isZeroNode(Op.getOperand(0)) &&
5154 !X86::isZeroNode(Op.getOperand(1))) {
5155 unsigned NumBits = VT.getSizeInBits();
5156 return getVShift(true, VT,
5157 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
5158 VT, Op.getOperand(1)),
5159 NumBits/2, DAG, *this, dl);
5162 if (IsAllConstants) // Otherwise, it's better to do a constpool load.
5165 // Otherwise, if this is a vector with i32 or f32 elements, and the element
5166 // is a non-constant being inserted into an element other than the low one,
5167 // we can't use a constant pool load. Instead, use SCALAR_TO_VECTOR (aka
5168 // movd/movss) to move this into the low element, then shuffle it into
5170 if (EVTBits == 32) {
5171 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
5173 // Turn it into a shuffle of zero and zero-extended scalar to vector.
5174 Item = getShuffleVectorZeroOrUndef(Item, 0, NumZero > 0, Subtarget, DAG);
5175 SmallVector<int, 8> MaskVec;
5176 for (unsigned i = 0; i < NumElems; i++)
5177 MaskVec.push_back(i == Idx ? 0 : 1);
5178 return DAG.getVectorShuffle(VT, dl, Item, DAG.getUNDEF(VT), &MaskVec[0]);
5182 // Splat is obviously ok. Let legalizer expand it to a shuffle.
5183 if (Values.size() == 1) {
5184 if (EVTBits == 32) {
5185 // Instead of a shuffle like this:
5186 // shuffle (scalar_to_vector (load (ptr + 4))), undef, <0, 0, 0, 0>
5187 // Check if it's possible to issue this instead.
5188 // shuffle (vload ptr)), undef, <1, 1, 1, 1>
5189 unsigned Idx = CountTrailingZeros_32(NonZeros);
5190 SDValue Item = Op.getOperand(Idx);
5191 if (Op.getNode()->isOnlyUserOf(Item.getNode()))
5192 return LowerAsSplatVectorLoad(Item, VT, dl, DAG);
5197 // A vector full of immediates; various special cases are already
5198 // handled, so this is best done with a single constant-pool load.
5202 // For AVX-length vectors, build the individual 128-bit pieces and use
5203 // shuffles to put them in place.
5204 if (VT.getSizeInBits() == 256) {
5205 SmallVector<SDValue, 32> V;
5206 for (unsigned i = 0; i != NumElems; ++i)
5207 V.push_back(Op.getOperand(i));
5209 EVT HVT = EVT::getVectorVT(*DAG.getContext(), ExtVT, NumElems/2);
5211 // Build both the lower and upper subvector.
5212 SDValue Lower = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT, &V[0], NumElems/2);
5213 SDValue Upper = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT, &V[NumElems / 2],
5216 // Recreate the wider vector with the lower and upper part.
5217 SDValue Vec = Insert128BitVector(DAG.getNode(ISD::UNDEF, dl, VT), Lower,
5218 DAG.getConstant(0, MVT::i32), DAG, dl);
5219 return Insert128BitVector(Vec, Upper, DAG.getConstant(NumElems/2, MVT::i32),
5223 // Let legalizer expand 2-wide build_vectors.
5224 if (EVTBits == 64) {
5225 if (NumNonZero == 1) {
5226 // One half is zero or undef.
5227 unsigned Idx = CountTrailingZeros_32(NonZeros);
5228 SDValue V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT,
5229 Op.getOperand(Idx));
5230 return getShuffleVectorZeroOrUndef(V2, Idx, true, Subtarget, DAG);
5235 // If element VT is < 32 bits, convert it to inserts into a zero vector.
5236 if (EVTBits == 8 && NumElems == 16) {
5237 SDValue V = LowerBuildVectorv16i8(Op, NonZeros,NumNonZero,NumZero, DAG,
5239 if (V.getNode()) return V;
5242 if (EVTBits == 16 && NumElems == 8) {
5243 SDValue V = LowerBuildVectorv8i16(Op, NonZeros,NumNonZero,NumZero, DAG,
5245 if (V.getNode()) return V;
5248 // If element VT is == 32 bits, turn it into a number of shuffles.
5249 SmallVector<SDValue, 8> V(NumElems);
5250 if (NumElems == 4 && NumZero > 0) {
5251 for (unsigned i = 0; i < 4; ++i) {
5252 bool isZero = !(NonZeros & (1 << i));
5254 V[i] = getZeroVector(VT, Subtarget, DAG, dl);
5256 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
5259 for (unsigned i = 0; i < 2; ++i) {
5260 switch ((NonZeros & (0x3 << i*2)) >> (i*2)) {
5263 V[i] = V[i*2]; // Must be a zero vector.
5266 V[i] = getMOVL(DAG, dl, VT, V[i*2+1], V[i*2]);
5269 V[i] = getMOVL(DAG, dl, VT, V[i*2], V[i*2+1]);
5272 V[i] = getUnpackl(DAG, dl, VT, V[i*2], V[i*2+1]);
5277 bool Reverse1 = (NonZeros & 0x3) == 2;
5278 bool Reverse2 = ((NonZeros & (0x3 << 2)) >> 2) == 2;
5282 static_cast<int>(Reverse2 ? NumElems+1 : NumElems),
5283 static_cast<int>(Reverse2 ? NumElems : NumElems+1)
5285 return DAG.getVectorShuffle(VT, dl, V[0], V[1], &MaskVec[0]);
5288 if (Values.size() > 1 && VT.getSizeInBits() == 128) {
5289 // Check for a build vector of consecutive loads.
5290 for (unsigned i = 0; i < NumElems; ++i)
5291 V[i] = Op.getOperand(i);
5293 // Check for elements which are consecutive loads.
5294 SDValue LD = EltsFromConsecutiveLoads(VT, V, dl, DAG);
5298 // For SSE 4.1, use insertps to put the high elements into the low element.
5299 if (getSubtarget()->hasSSE41()) {
5301 if (Op.getOperand(0).getOpcode() != ISD::UNDEF)
5302 Result = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(0));
5304 Result = DAG.getUNDEF(VT);
5306 for (unsigned i = 1; i < NumElems; ++i) {
5307 if (Op.getOperand(i).getOpcode() == ISD::UNDEF) continue;
5308 Result = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Result,
5309 Op.getOperand(i), DAG.getIntPtrConstant(i));
5314 // Otherwise, expand into a number of unpckl*, start by extending each of
5315 // our (non-undef) elements to the full vector width with the element in the
5316 // bottom slot of the vector (which generates no code for SSE).
5317 for (unsigned i = 0; i < NumElems; ++i) {
5318 if (Op.getOperand(i).getOpcode() != ISD::UNDEF)
5319 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
5321 V[i] = DAG.getUNDEF(VT);
5324 // Next, we iteratively mix elements, e.g. for v4f32:
5325 // Step 1: unpcklps 0, 2 ==> X: <?, ?, 2, 0>
5326 // : unpcklps 1, 3 ==> Y: <?, ?, 3, 1>
5327 // Step 2: unpcklps X, Y ==> <3, 2, 1, 0>
5328 unsigned EltStride = NumElems >> 1;
5329 while (EltStride != 0) {
5330 for (unsigned i = 0; i < EltStride; ++i) {
5331 // If V[i+EltStride] is undef and this is the first round of mixing,
5332 // then it is safe to just drop this shuffle: V[i] is already in the
5333 // right place, the one element (since it's the first round) being
5334 // inserted as undef can be dropped. This isn't safe for successive
5335 // rounds because they will permute elements within both vectors.
5336 if (V[i+EltStride].getOpcode() == ISD::UNDEF &&
5337 EltStride == NumElems/2)
5340 V[i] = getUnpackl(DAG, dl, VT, V[i], V[i + EltStride]);
5349 // LowerMMXCONCAT_VECTORS - We support concatenate two MMX registers and place
5350 // them in a MMX register. This is better than doing a stack convert.
5351 static SDValue LowerMMXCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
5352 DebugLoc dl = Op.getDebugLoc();
5353 EVT ResVT = Op.getValueType();
5355 assert(ResVT == MVT::v2i64 || ResVT == MVT::v4i32 ||
5356 ResVT == MVT::v8i16 || ResVT == MVT::v16i8);
5358 SDValue InVec = DAG.getNode(ISD::BITCAST,dl, MVT::v1i64, Op.getOperand(0));
5359 SDValue VecOp = DAG.getNode(X86ISD::MOVQ2DQ, dl, MVT::v2i64, InVec);
5360 InVec = Op.getOperand(1);
5361 if (InVec.getOpcode() == ISD::SCALAR_TO_VECTOR) {
5362 unsigned NumElts = ResVT.getVectorNumElements();
5363 VecOp = DAG.getNode(ISD::BITCAST, dl, ResVT, VecOp);
5364 VecOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, ResVT, VecOp,
5365 InVec.getOperand(0), DAG.getIntPtrConstant(NumElts/2+1));
5367 InVec = DAG.getNode(ISD::BITCAST, dl, MVT::v1i64, InVec);
5368 SDValue VecOp2 = DAG.getNode(X86ISD::MOVQ2DQ, dl, MVT::v2i64, InVec);
5369 Mask[0] = 0; Mask[1] = 2;
5370 VecOp = DAG.getVectorShuffle(MVT::v2i64, dl, VecOp, VecOp2, Mask);
5372 return DAG.getNode(ISD::BITCAST, dl, ResVT, VecOp);
5375 // LowerAVXCONCAT_VECTORS - 256-bit AVX can use the vinsertf128 instruction
5376 // to create 256-bit vectors from two other 128-bit ones.
5377 static SDValue LowerAVXCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
5378 DebugLoc dl = Op.getDebugLoc();
5379 EVT ResVT = Op.getValueType();
5381 assert(ResVT.getSizeInBits() == 256 && "Value type must be 256-bit wide");
5383 SDValue V1 = Op.getOperand(0);
5384 SDValue V2 = Op.getOperand(1);
5385 unsigned NumElems = ResVT.getVectorNumElements();
5387 SDValue V = Insert128BitVector(DAG.getNode(ISD::UNDEF, dl, ResVT), V1,
5388 DAG.getConstant(0, MVT::i32), DAG, dl);
5389 return Insert128BitVector(V, V2, DAG.getConstant(NumElems/2, MVT::i32),
5394 X86TargetLowering::LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) const {
5395 EVT ResVT = Op.getValueType();
5397 assert(Op.getNumOperands() == 2);
5398 assert((ResVT.getSizeInBits() == 128 || ResVT.getSizeInBits() == 256) &&
5399 "Unsupported CONCAT_VECTORS for value type");
5401 // We support concatenate two MMX registers and place them in a MMX register.
5402 // This is better than doing a stack convert.
5403 if (ResVT.is128BitVector())
5404 return LowerMMXCONCAT_VECTORS(Op, DAG);
5406 // 256-bit AVX can use the vinsertf128 instruction to create 256-bit vectors
5407 // from two other 128-bit ones.
5408 return LowerAVXCONCAT_VECTORS(Op, DAG);
5411 // Try to lower a shuffle node into a simple blend instruction.
5412 static SDValue LowerVECTOR_SHUFFLEtoBlend(SDValue Op,
5413 const X86Subtarget *Subtarget,
5414 SelectionDAG &DAG) {
5415 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
5416 SDValue V1 = SVOp->getOperand(0);
5417 SDValue V2 = SVOp->getOperand(1);
5418 DebugLoc dl = SVOp->getDebugLoc();
5419 EVT VT = Op.getValueType();
5420 EVT InVT = V1.getValueType();
5421 int MaskSize = VT.getVectorNumElements();
5422 int InSize = InVT.getVectorNumElements();
5424 if (!Subtarget->hasSSE41())
5427 if (MaskSize != InSize)
5433 switch (VT.getSimpleVT().SimpleTy) {
5434 default: return SDValue();
5436 ISDNo = X86ISD::BLENDPW;
5441 ISDNo = X86ISD::BLENDPS;
5446 ISDNo = X86ISD::BLENDPD;
5451 if (!Subtarget->hasAVX())
5453 ISDNo = X86ISD::BLENDPS;
5458 if (!Subtarget->hasAVX())
5460 ISDNo = X86ISD::BLENDPD;
5464 if (!Subtarget->hasAVX2())
5466 ISDNo = X86ISD::BLENDPW;
5470 assert(ISDNo && "Invalid Op Number");
5472 unsigned MaskVals = 0;
5474 for (int i = 0; i < MaskSize; ++i) {
5475 int EltIdx = SVOp->getMaskElt(i);
5476 if (EltIdx == i || EltIdx == -1)
5478 else if (EltIdx == (i + MaskSize))
5479 continue; // Bit is set to zero;
5480 else return SDValue();
5483 V1 = DAG.getNode(ISD::BITCAST, dl, OpTy, V1);
5484 V2 = DAG.getNode(ISD::BITCAST, dl, OpTy, V2);
5485 SDValue Ret = DAG.getNode(ISDNo, dl, OpTy, V1, V2,
5486 DAG.getConstant(MaskVals, MVT::i32));
5487 return DAG.getNode(ISD::BITCAST, dl, VT, Ret);
5490 // v8i16 shuffles - Prefer shuffles in the following order:
5491 // 1. [all] pshuflw, pshufhw, optional move
5492 // 2. [ssse3] 1 x pshufb
5493 // 3. [ssse3] 2 x pshufb + 1 x por
5494 // 4. [all] mov + pshuflw + pshufhw + N x (pextrw + pinsrw)
5496 X86TargetLowering::LowerVECTOR_SHUFFLEv8i16(SDValue Op,
5497 SelectionDAG &DAG) const {
5498 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
5499 SDValue V1 = SVOp->getOperand(0);
5500 SDValue V2 = SVOp->getOperand(1);
5501 DebugLoc dl = SVOp->getDebugLoc();
5502 SmallVector<int, 8> MaskVals;
5504 // Determine if more than 1 of the words in each of the low and high quadwords
5505 // of the result come from the same quadword of one of the two inputs. Undef
5506 // mask values count as coming from any quadword, for better codegen.
5507 unsigned LoQuad[] = { 0, 0, 0, 0 };
5508 unsigned HiQuad[] = { 0, 0, 0, 0 };
5509 std::bitset<4> InputQuads;
5510 for (unsigned i = 0; i < 8; ++i) {
5511 unsigned *Quad = i < 4 ? LoQuad : HiQuad;
5512 int EltIdx = SVOp->getMaskElt(i);
5513 MaskVals.push_back(EltIdx);
5522 InputQuads.set(EltIdx / 4);
5525 int BestLoQuad = -1;
5526 unsigned MaxQuad = 1;
5527 for (unsigned i = 0; i < 4; ++i) {
5528 if (LoQuad[i] > MaxQuad) {
5530 MaxQuad = LoQuad[i];
5534 int BestHiQuad = -1;
5536 for (unsigned i = 0; i < 4; ++i) {
5537 if (HiQuad[i] > MaxQuad) {
5539 MaxQuad = HiQuad[i];
5543 // For SSSE3, If all 8 words of the result come from only 1 quadword of each
5544 // of the two input vectors, shuffle them into one input vector so only a
5545 // single pshufb instruction is necessary. If There are more than 2 input
5546 // quads, disable the next transformation since it does not help SSSE3.
5547 bool V1Used = InputQuads[0] || InputQuads[1];
5548 bool V2Used = InputQuads[2] || InputQuads[3];
5549 if (Subtarget->hasSSSE3()) {
5550 if (InputQuads.count() == 2 && V1Used && V2Used) {
5551 BestLoQuad = InputQuads[0] ? 0 : 1;
5552 BestHiQuad = InputQuads[2] ? 2 : 3;
5554 if (InputQuads.count() > 2) {
5560 // If BestLoQuad or BestHiQuad are set, shuffle the quads together and update
5561 // the shuffle mask. If a quad is scored as -1, that means that it contains
5562 // words from all 4 input quadwords.
5564 if (BestLoQuad >= 0 || BestHiQuad >= 0) {
5566 BestLoQuad < 0 ? 0 : BestLoQuad,
5567 BestHiQuad < 0 ? 1 : BestHiQuad
5569 NewV = DAG.getVectorShuffle(MVT::v2i64, dl,
5570 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, V1),
5571 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, V2), &MaskV[0]);
5572 NewV = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, NewV);
5574 // Rewrite the MaskVals and assign NewV to V1 if NewV now contains all the
5575 // source words for the shuffle, to aid later transformations.
5576 bool AllWordsInNewV = true;
5577 bool InOrder[2] = { true, true };
5578 for (unsigned i = 0; i != 8; ++i) {
5579 int idx = MaskVals[i];
5581 InOrder[i/4] = false;
5582 if (idx < 0 || (idx/4) == BestLoQuad || (idx/4) == BestHiQuad)
5584 AllWordsInNewV = false;
5588 bool pshuflw = AllWordsInNewV, pshufhw = AllWordsInNewV;
5589 if (AllWordsInNewV) {
5590 for (int i = 0; i != 8; ++i) {
5591 int idx = MaskVals[i];
5594 idx = MaskVals[i] = (idx / 4) == BestLoQuad ? (idx & 3) : (idx & 3) + 4;
5595 if ((idx != i) && idx < 4)
5597 if ((idx != i) && idx > 3)
5606 // If we've eliminated the use of V2, and the new mask is a pshuflw or
5607 // pshufhw, that's as cheap as it gets. Return the new shuffle.
5608 if ((pshufhw && InOrder[0]) || (pshuflw && InOrder[1])) {
5609 unsigned Opc = pshufhw ? X86ISD::PSHUFHW : X86ISD::PSHUFLW;
5610 unsigned TargetMask = 0;
5611 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV,
5612 DAG.getUNDEF(MVT::v8i16), &MaskVals[0]);
5613 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode());
5614 TargetMask = pshufhw ? getShufflePSHUFHWImmediate(SVOp):
5615 getShufflePSHUFLWImmediate(SVOp);
5616 V1 = NewV.getOperand(0);
5617 return getTargetShuffleNode(Opc, dl, MVT::v8i16, V1, TargetMask, DAG);
5621 // If we have SSSE3, and all words of the result are from 1 input vector,
5622 // case 2 is generated, otherwise case 3 is generated. If no SSSE3
5623 // is present, fall back to case 4.
5624 if (Subtarget->hasSSSE3()) {
5625 SmallVector<SDValue,16> pshufbMask;
5627 // If we have elements from both input vectors, set the high bit of the
5628 // shuffle mask element to zero out elements that come from V2 in the V1
5629 // mask, and elements that come from V1 in the V2 mask, so that the two
5630 // results can be OR'd together.
5631 bool TwoInputs = V1Used && V2Used;
5632 for (unsigned i = 0; i != 8; ++i) {
5633 int EltIdx = MaskVals[i] * 2;
5634 if (TwoInputs && (EltIdx >= 16)) {
5635 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
5636 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
5639 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
5640 pshufbMask.push_back(DAG.getConstant(EltIdx+1, MVT::i8));
5642 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V1);
5643 V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1,
5644 DAG.getNode(ISD::BUILD_VECTOR, dl,
5645 MVT::v16i8, &pshufbMask[0], 16));
5647 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
5649 // Calculate the shuffle mask for the second input, shuffle it, and
5650 // OR it with the first shuffled input.
5652 for (unsigned i = 0; i != 8; ++i) {
5653 int EltIdx = MaskVals[i] * 2;
5655 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
5656 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
5659 pshufbMask.push_back(DAG.getConstant(EltIdx - 16, MVT::i8));
5660 pshufbMask.push_back(DAG.getConstant(EltIdx - 15, MVT::i8));
5662 V2 = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V2);
5663 V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2,
5664 DAG.getNode(ISD::BUILD_VECTOR, dl,
5665 MVT::v16i8, &pshufbMask[0], 16));
5666 V1 = DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
5667 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
5670 // If BestLoQuad >= 0, generate a pshuflw to put the low elements in order,
5671 // and update MaskVals with new element order.
5672 std::bitset<8> InOrder;
5673 if (BestLoQuad >= 0) {
5674 int MaskV[] = { -1, -1, -1, -1, 4, 5, 6, 7 };
5675 for (int i = 0; i != 4; ++i) {
5676 int idx = MaskVals[i];
5679 } else if ((idx / 4) == BestLoQuad) {
5684 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16),
5687 if (NewV.getOpcode() == ISD::VECTOR_SHUFFLE && Subtarget->hasSSSE3()) {
5688 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode());
5689 NewV = getTargetShuffleNode(X86ISD::PSHUFLW, dl, MVT::v8i16,
5691 getShufflePSHUFLWImmediate(SVOp), DAG);
5695 // If BestHi >= 0, generate a pshufhw to put the high elements in order,
5696 // and update MaskVals with the new element order.
5697 if (BestHiQuad >= 0) {
5698 int MaskV[] = { 0, 1, 2, 3, -1, -1, -1, -1 };
5699 for (unsigned i = 4; i != 8; ++i) {
5700 int idx = MaskVals[i];
5703 } else if ((idx / 4) == BestHiQuad) {
5704 MaskV[i] = (idx & 3) + 4;
5708 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16),
5711 if (NewV.getOpcode() == ISD::VECTOR_SHUFFLE && Subtarget->hasSSSE3()) {
5712 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode());
5713 NewV = getTargetShuffleNode(X86ISD::PSHUFHW, dl, MVT::v8i16,
5715 getShufflePSHUFHWImmediate(SVOp), DAG);
5719 // In case BestHi & BestLo were both -1, which means each quadword has a word
5720 // from each of the four input quadwords, calculate the InOrder bitvector now
5721 // before falling through to the insert/extract cleanup.
5722 if (BestLoQuad == -1 && BestHiQuad == -1) {
5724 for (int i = 0; i != 8; ++i)
5725 if (MaskVals[i] < 0 || MaskVals[i] == i)
5729 // The other elements are put in the right place using pextrw and pinsrw.
5730 for (unsigned i = 0; i != 8; ++i) {
5733 int EltIdx = MaskVals[i];
5736 SDValue ExtOp = (EltIdx < 8)
5737 ? DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V1,
5738 DAG.getIntPtrConstant(EltIdx))
5739 : DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V2,
5740 DAG.getIntPtrConstant(EltIdx - 8));
5741 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, ExtOp,
5742 DAG.getIntPtrConstant(i));
5747 // v16i8 shuffles - Prefer shuffles in the following order:
5748 // 1. [ssse3] 1 x pshufb
5749 // 2. [ssse3] 2 x pshufb + 1 x por
5750 // 3. [all] v8i16 shuffle + N x pextrw + rotate + pinsrw
5752 SDValue LowerVECTOR_SHUFFLEv16i8(ShuffleVectorSDNode *SVOp,
5754 const X86TargetLowering &TLI) {
5755 SDValue V1 = SVOp->getOperand(0);
5756 SDValue V2 = SVOp->getOperand(1);
5757 DebugLoc dl = SVOp->getDebugLoc();
5758 ArrayRef<int> MaskVals = SVOp->getMask();
5760 // If we have SSSE3, case 1 is generated when all result bytes come from
5761 // one of the inputs. Otherwise, case 2 is generated. If no SSSE3 is
5762 // present, fall back to case 3.
5763 // FIXME: kill V2Only once shuffles are canonizalized by getNode.
5766 for (unsigned i = 0; i < 16; ++i) {
5767 int EltIdx = MaskVals[i];
5776 // If SSSE3, use 1 pshufb instruction per vector with elements in the result.
5777 if (TLI.getSubtarget()->hasSSSE3()) {
5778 SmallVector<SDValue,16> pshufbMask;
5780 // If all result elements are from one input vector, then only translate
5781 // undef mask values to 0x80 (zero out result) in the pshufb mask.
5783 // Otherwise, we have elements from both input vectors, and must zero out
5784 // elements that come from V2 in the first mask, and V1 in the second mask
5785 // so that we can OR them together.
5786 bool TwoInputs = !(V1Only || V2Only);
5787 for (unsigned i = 0; i != 16; ++i) {
5788 int EltIdx = MaskVals[i];
5789 if (EltIdx < 0 || (TwoInputs && EltIdx >= 16)) {
5790 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
5793 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
5795 // If all the elements are from V2, assign it to V1 and return after
5796 // building the first pshufb.
5799 V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1,
5800 DAG.getNode(ISD::BUILD_VECTOR, dl,
5801 MVT::v16i8, &pshufbMask[0], 16));
5805 // Calculate the shuffle mask for the second input, shuffle it, and
5806 // OR it with the first shuffled input.
5808 for (unsigned i = 0; i != 16; ++i) {
5809 int EltIdx = MaskVals[i];
5811 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
5814 pshufbMask.push_back(DAG.getConstant(EltIdx - 16, MVT::i8));
5816 V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2,
5817 DAG.getNode(ISD::BUILD_VECTOR, dl,
5818 MVT::v16i8, &pshufbMask[0], 16));
5819 return DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
5822 // No SSSE3 - Calculate in place words and then fix all out of place words
5823 // With 0-16 extracts & inserts. Worst case is 16 bytes out of order from
5824 // the 16 different words that comprise the two doublequadword input vectors.
5825 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
5826 V2 = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V2);
5827 SDValue NewV = V2Only ? V2 : V1;
5828 for (int i = 0; i != 8; ++i) {
5829 int Elt0 = MaskVals[i*2];
5830 int Elt1 = MaskVals[i*2+1];
5832 // This word of the result is all undef, skip it.
5833 if (Elt0 < 0 && Elt1 < 0)
5836 // This word of the result is already in the correct place, skip it.
5837 if (V1Only && (Elt0 == i*2) && (Elt1 == i*2+1))
5839 if (V2Only && (Elt0 == i*2+16) && (Elt1 == i*2+17))
5842 SDValue Elt0Src = Elt0 < 16 ? V1 : V2;
5843 SDValue Elt1Src = Elt1 < 16 ? V1 : V2;
5846 // If Elt0 and Elt1 are defined, are consecutive, and can be load
5847 // using a single extract together, load it and store it.
5848 if ((Elt0 >= 0) && ((Elt0 + 1) == Elt1) && ((Elt0 & 1) == 0)) {
5849 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src,
5850 DAG.getIntPtrConstant(Elt1 / 2));
5851 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt,
5852 DAG.getIntPtrConstant(i));
5856 // If Elt1 is defined, extract it from the appropriate source. If the
5857 // source byte is not also odd, shift the extracted word left 8 bits
5858 // otherwise clear the bottom 8 bits if we need to do an or.
5860 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src,
5861 DAG.getIntPtrConstant(Elt1 / 2));
5862 if ((Elt1 & 1) == 0)
5863 InsElt = DAG.getNode(ISD::SHL, dl, MVT::i16, InsElt,
5865 TLI.getShiftAmountTy(InsElt.getValueType())));
5867 InsElt = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt,
5868 DAG.getConstant(0xFF00, MVT::i16));
5870 // If Elt0 is defined, extract it from the appropriate source. If the
5871 // source byte is not also even, shift the extracted word right 8 bits. If
5872 // Elt1 was also defined, OR the extracted values together before
5873 // inserting them in the result.
5875 SDValue InsElt0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16,
5876 Elt0Src, DAG.getIntPtrConstant(Elt0 / 2));
5877 if ((Elt0 & 1) != 0)
5878 InsElt0 = DAG.getNode(ISD::SRL, dl, MVT::i16, InsElt0,
5880 TLI.getShiftAmountTy(InsElt0.getValueType())));
5882 InsElt0 = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt0,
5883 DAG.getConstant(0x00FF, MVT::i16));
5884 InsElt = Elt1 >= 0 ? DAG.getNode(ISD::OR, dl, MVT::i16, InsElt, InsElt0)
5887 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt,
5888 DAG.getIntPtrConstant(i));
5890 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, NewV);
5893 /// RewriteAsNarrowerShuffle - Try rewriting v8i16 and v16i8 shuffles as 4 wide
5894 /// ones, or rewriting v4i32 / v4f32 as 2 wide ones if possible. This can be
5895 /// done when every pair / quad of shuffle mask elements point to elements in
5896 /// the right sequence. e.g.
5897 /// vector_shuffle X, Y, <2, 3, | 10, 11, | 0, 1, | 14, 15>
5899 SDValue RewriteAsNarrowerShuffle(ShuffleVectorSDNode *SVOp,
5900 SelectionDAG &DAG, DebugLoc dl) {
5901 EVT VT = SVOp->getValueType(0);
5902 SDValue V1 = SVOp->getOperand(0);
5903 SDValue V2 = SVOp->getOperand(1);
5904 unsigned NumElems = VT.getVectorNumElements();
5905 unsigned NewWidth = (NumElems == 4) ? 2 : 4;
5907 switch (VT.getSimpleVT().SimpleTy) {
5908 default: llvm_unreachable("Unexpected!");
5909 case MVT::v4f32: NewVT = MVT::v2f64; break;
5910 case MVT::v4i32: NewVT = MVT::v2i64; break;
5911 case MVT::v8i16: NewVT = MVT::v4i32; break;
5912 case MVT::v16i8: NewVT = MVT::v4i32; break;
5915 int Scale = NumElems / NewWidth;
5916 SmallVector<int, 8> MaskVec;
5917 for (unsigned i = 0; i < NumElems; i += Scale) {
5919 for (int j = 0; j < Scale; ++j) {
5920 int EltIdx = SVOp->getMaskElt(i+j);
5924 StartIdx = EltIdx - (EltIdx % Scale);
5925 if (EltIdx != StartIdx + j)
5929 MaskVec.push_back(-1);
5931 MaskVec.push_back(StartIdx / Scale);
5934 V1 = DAG.getNode(ISD::BITCAST, dl, NewVT, V1);
5935 V2 = DAG.getNode(ISD::BITCAST, dl, NewVT, V2);
5936 return DAG.getVectorShuffle(NewVT, dl, V1, V2, &MaskVec[0]);
5939 /// getVZextMovL - Return a zero-extending vector move low node.
5941 static SDValue getVZextMovL(EVT VT, EVT OpVT,
5942 SDValue SrcOp, SelectionDAG &DAG,
5943 const X86Subtarget *Subtarget, DebugLoc dl) {
5944 if (VT == MVT::v2f64 || VT == MVT::v4f32) {
5945 LoadSDNode *LD = NULL;
5946 if (!isScalarLoadToVector(SrcOp.getNode(), &LD))
5947 LD = dyn_cast<LoadSDNode>(SrcOp);
5949 // movssrr and movsdrr do not clear top bits. Try to use movd, movq
5951 MVT ExtVT = (OpVT == MVT::v2f64) ? MVT::i64 : MVT::i32;
5952 if ((ExtVT != MVT::i64 || Subtarget->is64Bit()) &&
5953 SrcOp.getOpcode() == ISD::SCALAR_TO_VECTOR &&
5954 SrcOp.getOperand(0).getOpcode() == ISD::BITCAST &&
5955 SrcOp.getOperand(0).getOperand(0).getValueType() == ExtVT) {
5957 OpVT = (OpVT == MVT::v2f64) ? MVT::v2i64 : MVT::v4i32;
5958 return DAG.getNode(ISD::BITCAST, dl, VT,
5959 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT,
5960 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
5968 return DAG.getNode(ISD::BITCAST, dl, VT,
5969 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT,
5970 DAG.getNode(ISD::BITCAST, dl,
5974 /// LowerVECTOR_SHUFFLE_256 - Handle all 256-bit wide vectors shuffles
5975 /// which could not be matched by any known target speficic shuffle
5977 LowerVECTOR_SHUFFLE_256(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
5978 EVT VT = SVOp->getValueType(0);
5980 unsigned NumElems = VT.getVectorNumElements();
5981 unsigned NumLaneElems = NumElems / 2;
5983 DebugLoc dl = SVOp->getDebugLoc();
5984 MVT EltVT = VT.getVectorElementType().getSimpleVT();
5985 EVT NVT = MVT::getVectorVT(EltVT, NumLaneElems);
5988 SmallVector<int, 16> Mask;
5989 for (unsigned l = 0; l < 2; ++l) {
5990 // Build a shuffle mask for the output, discovering on the fly which
5991 // input vectors to use as shuffle operands (recorded in InputUsed).
5992 // If building a suitable shuffle vector proves too hard, then bail
5993 // out with useBuildVector set.
5994 int InputUsed[2] = { -1, -1 }; // Not yet discovered.
5995 unsigned LaneStart = l * NumLaneElems;
5996 for (unsigned i = 0; i != NumLaneElems; ++i) {
5997 // The mask element. This indexes into the input.
5998 int Idx = SVOp->getMaskElt(i+LaneStart);
6000 // the mask element does not index into any input vector.
6005 // The input vector this mask element indexes into.
6006 int Input = Idx / NumLaneElems;
6008 // Turn the index into an offset from the start of the input vector.
6009 Idx -= Input * NumLaneElems;
6011 // Find or create a shuffle vector operand to hold this input.
6013 for (OpNo = 0; OpNo < array_lengthof(InputUsed); ++OpNo) {
6014 if (InputUsed[OpNo] == Input)
6015 // This input vector is already an operand.
6017 if (InputUsed[OpNo] < 0) {
6018 // Create a new operand for this input vector.
6019 InputUsed[OpNo] = Input;
6024 if (OpNo >= array_lengthof(InputUsed)) {
6025 // More than two input vectors used! Give up.
6029 // Add the mask index for the new shuffle vector.
6030 Mask.push_back(Idx + OpNo * NumLaneElems);
6033 if (InputUsed[0] < 0) {
6034 // No input vectors were used! The result is undefined.
6035 Shufs[l] = DAG.getUNDEF(NVT);
6037 SDValue Op0 = Extract128BitVector(SVOp->getOperand(InputUsed[0] / 2),
6038 DAG.getConstant((InputUsed[0] % 2) * NumLaneElems, MVT::i32),
6040 // If only one input was used, use an undefined vector for the other.
6041 SDValue Op1 = (InputUsed[1] < 0) ? DAG.getUNDEF(NVT) :
6042 Extract128BitVector(SVOp->getOperand(InputUsed[1] / 2),
6043 DAG.getConstant((InputUsed[1] % 2) * NumLaneElems, MVT::i32),
6045 // At least one input vector was used. Create a new shuffle vector.
6046 Shufs[l] = DAG.getVectorShuffle(NVT, dl, Op0, Op1, &Mask[0]);
6052 // Concatenate the result back
6053 SDValue V = Insert128BitVector(DAG.getNode(ISD::UNDEF, dl, VT), Shufs[0],
6054 DAG.getConstant(0, MVT::i32), DAG, dl);
6055 return Insert128BitVector(V, Shufs[1],DAG.getConstant(NumLaneElems, MVT::i32),
6059 /// LowerVECTOR_SHUFFLE_128v4 - Handle all 128-bit wide vectors with
6060 /// 4 elements, and match them with several different shuffle types.
6062 LowerVECTOR_SHUFFLE_128v4(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
6063 SDValue V1 = SVOp->getOperand(0);
6064 SDValue V2 = SVOp->getOperand(1);
6065 DebugLoc dl = SVOp->getDebugLoc();
6066 EVT VT = SVOp->getValueType(0);
6068 assert(VT.getSizeInBits() == 128 && "Unsupported vector size");
6070 std::pair<int, int> Locs[4];
6071 int Mask1[] = { -1, -1, -1, -1 };
6072 SmallVector<int, 8> PermMask(SVOp->getMask().begin(), SVOp->getMask().end());
6076 for (unsigned i = 0; i != 4; ++i) {
6077 int Idx = PermMask[i];
6079 Locs[i] = std::make_pair(-1, -1);
6081 assert(Idx < 8 && "Invalid VECTOR_SHUFFLE index!");
6083 Locs[i] = std::make_pair(0, NumLo);
6087 Locs[i] = std::make_pair(1, NumHi);
6089 Mask1[2+NumHi] = Idx;
6095 if (NumLo <= 2 && NumHi <= 2) {
6096 // If no more than two elements come from either vector. This can be
6097 // implemented with two shuffles. First shuffle gather the elements.
6098 // The second shuffle, which takes the first shuffle as both of its
6099 // vector operands, put the elements into the right order.
6100 V1 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
6102 int Mask2[] = { -1, -1, -1, -1 };
6104 for (unsigned i = 0; i != 4; ++i)
6105 if (Locs[i].first != -1) {
6106 unsigned Idx = (i < 2) ? 0 : 4;
6107 Idx += Locs[i].first * 2 + Locs[i].second;
6111 return DAG.getVectorShuffle(VT, dl, V1, V1, &Mask2[0]);
6112 } else if (NumLo == 3 || NumHi == 3) {
6113 // Otherwise, we must have three elements from one vector, call it X, and
6114 // one element from the other, call it Y. First, use a shufps to build an
6115 // intermediate vector with the one element from Y and the element from X
6116 // that will be in the same half in the final destination (the indexes don't
6117 // matter). Then, use a shufps to build the final vector, taking the half
6118 // containing the element from Y from the intermediate, and the other half
6121 // Normalize it so the 3 elements come from V1.
6122 CommuteVectorShuffleMask(PermMask, 4);
6126 // Find the element from V2.
6128 for (HiIndex = 0; HiIndex < 3; ++HiIndex) {
6129 int Val = PermMask[HiIndex];
6136 Mask1[0] = PermMask[HiIndex];
6138 Mask1[2] = PermMask[HiIndex^1];
6140 V2 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
6143 Mask1[0] = PermMask[0];
6144 Mask1[1] = PermMask[1];
6145 Mask1[2] = HiIndex & 1 ? 6 : 4;
6146 Mask1[3] = HiIndex & 1 ? 4 : 6;
6147 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
6149 Mask1[0] = HiIndex & 1 ? 2 : 0;
6150 Mask1[1] = HiIndex & 1 ? 0 : 2;
6151 Mask1[2] = PermMask[2];
6152 Mask1[3] = PermMask[3];
6157 return DAG.getVectorShuffle(VT, dl, V2, V1, &Mask1[0]);
6161 // Break it into (shuffle shuffle_hi, shuffle_lo).
6162 int LoMask[] = { -1, -1, -1, -1 };
6163 int HiMask[] = { -1, -1, -1, -1 };
6165 int *MaskPtr = LoMask;
6166 unsigned MaskIdx = 0;
6169 for (unsigned i = 0; i != 4; ++i) {
6176 int Idx = PermMask[i];
6178 Locs[i] = std::make_pair(-1, -1);
6179 } else if (Idx < 4) {
6180 Locs[i] = std::make_pair(MaskIdx, LoIdx);
6181 MaskPtr[LoIdx] = Idx;
6184 Locs[i] = std::make_pair(MaskIdx, HiIdx);
6185 MaskPtr[HiIdx] = Idx;
6190 SDValue LoShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &LoMask[0]);
6191 SDValue HiShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &HiMask[0]);
6192 int MaskOps[] = { -1, -1, -1, -1 };
6193 for (unsigned i = 0; i != 4; ++i)
6194 if (Locs[i].first != -1)
6195 MaskOps[i] = Locs[i].first * 4 + Locs[i].second;
6196 return DAG.getVectorShuffle(VT, dl, LoShuffle, HiShuffle, &MaskOps[0]);
6199 static bool MayFoldVectorLoad(SDValue V) {
6200 if (V.hasOneUse() && V.getOpcode() == ISD::BITCAST)
6201 V = V.getOperand(0);
6202 if (V.hasOneUse() && V.getOpcode() == ISD::SCALAR_TO_VECTOR)
6203 V = V.getOperand(0);
6204 if (V.hasOneUse() && V.getOpcode() == ISD::BUILD_VECTOR &&
6205 V.getNumOperands() == 2 && V.getOperand(1).getOpcode() == ISD::UNDEF)
6206 // BUILD_VECTOR (load), undef
6207 V = V.getOperand(0);
6213 // FIXME: the version above should always be used. Since there's
6214 // a bug where several vector shuffles can't be folded because the
6215 // DAG is not updated during lowering and a node claims to have two
6216 // uses while it only has one, use this version, and let isel match
6217 // another instruction if the load really happens to have more than
6218 // one use. Remove this version after this bug get fixed.
6219 // rdar://8434668, PR8156
6220 static bool RelaxedMayFoldVectorLoad(SDValue V) {
6221 if (V.hasOneUse() && V.getOpcode() == ISD::BITCAST)
6222 V = V.getOperand(0);
6223 if (V.hasOneUse() && V.getOpcode() == ISD::SCALAR_TO_VECTOR)
6224 V = V.getOperand(0);
6225 if (ISD::isNormalLoad(V.getNode()))
6231 SDValue getMOVDDup(SDValue &Op, DebugLoc &dl, SDValue V1, SelectionDAG &DAG) {
6232 EVT VT = Op.getValueType();
6234 // Canonizalize to v2f64.
6235 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, V1);
6236 return DAG.getNode(ISD::BITCAST, dl, VT,
6237 getTargetShuffleNode(X86ISD::MOVDDUP, dl, MVT::v2f64,
6242 SDValue getMOVLowToHigh(SDValue &Op, DebugLoc &dl, SelectionDAG &DAG,
6244 SDValue V1 = Op.getOperand(0);
6245 SDValue V2 = Op.getOperand(1);
6246 EVT VT = Op.getValueType();
6248 assert(VT != MVT::v2i64 && "unsupported shuffle type");
6250 if (HasSSE2 && VT == MVT::v2f64)
6251 return getTargetShuffleNode(X86ISD::MOVLHPD, dl, VT, V1, V2, DAG);
6253 // v4f32 or v4i32: canonizalized to v4f32 (which is legal for SSE1)
6254 return DAG.getNode(ISD::BITCAST, dl, VT,
6255 getTargetShuffleNode(X86ISD::MOVLHPS, dl, MVT::v4f32,
6256 DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V1),
6257 DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V2), DAG));
6261 SDValue getMOVHighToLow(SDValue &Op, DebugLoc &dl, SelectionDAG &DAG) {
6262 SDValue V1 = Op.getOperand(0);
6263 SDValue V2 = Op.getOperand(1);
6264 EVT VT = Op.getValueType();
6266 assert((VT == MVT::v4i32 || VT == MVT::v4f32) &&
6267 "unsupported shuffle type");
6269 if (V2.getOpcode() == ISD::UNDEF)
6273 return getTargetShuffleNode(X86ISD::MOVHLPS, dl, VT, V1, V2, DAG);
6277 SDValue getMOVLP(SDValue &Op, DebugLoc &dl, SelectionDAG &DAG, bool HasSSE2) {
6278 SDValue V1 = Op.getOperand(0);
6279 SDValue V2 = Op.getOperand(1);
6280 EVT VT = Op.getValueType();
6281 unsigned NumElems = VT.getVectorNumElements();
6283 // Use MOVLPS and MOVLPD in case V1 or V2 are loads. During isel, the second
6284 // operand of these instructions is only memory, so check if there's a
6285 // potencial load folding here, otherwise use SHUFPS or MOVSD to match the
6287 bool CanFoldLoad = false;
6289 // Trivial case, when V2 comes from a load.
6290 if (MayFoldVectorLoad(V2))
6293 // When V1 is a load, it can be folded later into a store in isel, example:
6294 // (store (v4f32 (X86Movlps (load addr:$src1), VR128:$src2)), addr:$src1)
6296 // (MOVLPSmr addr:$src1, VR128:$src2)
6297 // So, recognize this potential and also use MOVLPS or MOVLPD
6298 else if (MayFoldVectorLoad(V1) && MayFoldIntoStore(Op))
6301 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
6303 if (HasSSE2 && NumElems == 2)
6304 return getTargetShuffleNode(X86ISD::MOVLPD, dl, VT, V1, V2, DAG);
6307 // If we don't care about the second element, procede to use movss.
6308 if (SVOp->getMaskElt(1) != -1)
6309 return getTargetShuffleNode(X86ISD::MOVLPS, dl, VT, V1, V2, DAG);
6312 // movl and movlp will both match v2i64, but v2i64 is never matched by
6313 // movl earlier because we make it strict to avoid messing with the movlp load
6314 // folding logic (see the code above getMOVLP call). Match it here then,
6315 // this is horrible, but will stay like this until we move all shuffle
6316 // matching to x86 specific nodes. Note that for the 1st condition all
6317 // types are matched with movsd.
6319 // FIXME: isMOVLMask should be checked and matched before getMOVLP,
6320 // as to remove this logic from here, as much as possible
6321 if (NumElems == 2 || !isMOVLMask(SVOp->getMask(), VT))
6322 return getTargetShuffleNode(X86ISD::MOVSD, dl, VT, V1, V2, DAG);
6323 return getTargetShuffleNode(X86ISD::MOVSS, dl, VT, V1, V2, DAG);
6326 assert(VT != MVT::v4i32 && "unsupported shuffle type");
6328 // Invert the operand order and use SHUFPS to match it.
6329 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V2, V1,
6330 getShuffleSHUFImmediate(SVOp), DAG);
6334 X86TargetLowering::NormalizeVectorShuffle(SDValue Op, SelectionDAG &DAG) const {
6335 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
6336 EVT VT = Op.getValueType();
6337 DebugLoc dl = Op.getDebugLoc();
6338 SDValue V1 = Op.getOperand(0);
6339 SDValue V2 = Op.getOperand(1);
6341 if (isZeroShuffle(SVOp))
6342 return getZeroVector(VT, Subtarget, DAG, dl);
6344 // Handle splat operations
6345 if (SVOp->isSplat()) {
6346 unsigned NumElem = VT.getVectorNumElements();
6347 int Size = VT.getSizeInBits();
6349 // Use vbroadcast whenever the splat comes from a foldable load
6350 SDValue Broadcast = LowerVectorBroadcast(Op, DAG);
6351 if (Broadcast.getNode())
6354 // Handle splats by matching through known shuffle masks
6355 if ((Size == 128 && NumElem <= 4) ||
6356 (Size == 256 && NumElem < 8))
6359 // All remaning splats are promoted to target supported vector shuffles.
6360 return PromoteSplat(SVOp, DAG);
6363 // If the shuffle can be profitably rewritten as a narrower shuffle, then
6365 if (VT == MVT::v8i16 || VT == MVT::v16i8) {
6366 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG, dl);
6367 if (NewOp.getNode())
6368 return DAG.getNode(ISD::BITCAST, dl, VT, NewOp);
6369 } else if ((VT == MVT::v4i32 ||
6370 (VT == MVT::v4f32 && Subtarget->hasSSE2()))) {
6371 // FIXME: Figure out a cleaner way to do this.
6372 // Try to make use of movq to zero out the top part.
6373 if (ISD::isBuildVectorAllZeros(V2.getNode())) {
6374 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG, dl);
6375 if (NewOp.getNode()) {
6376 EVT NewVT = NewOp.getValueType();
6377 if (isCommutedMOVLMask(cast<ShuffleVectorSDNode>(NewOp)->getMask(),
6378 NewVT, true, false))
6379 return getVZextMovL(VT, NewVT, NewOp.getOperand(0),
6380 DAG, Subtarget, dl);
6382 } else if (ISD::isBuildVectorAllZeros(V1.getNode())) {
6383 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG, dl);
6384 if (NewOp.getNode()) {
6385 EVT NewVT = NewOp.getValueType();
6386 if (isMOVLMask(cast<ShuffleVectorSDNode>(NewOp)->getMask(), NewVT))
6387 return getVZextMovL(VT, NewVT, NewOp.getOperand(1),
6388 DAG, Subtarget, dl);
6396 X86TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const {
6397 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
6398 SDValue V1 = Op.getOperand(0);
6399 SDValue V2 = Op.getOperand(1);
6400 EVT VT = Op.getValueType();
6401 DebugLoc dl = Op.getDebugLoc();
6402 unsigned NumElems = VT.getVectorNumElements();
6403 bool V1IsUndef = V1.getOpcode() == ISD::UNDEF;
6404 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
6405 bool V1IsSplat = false;
6406 bool V2IsSplat = false;
6407 bool HasSSE2 = Subtarget->hasSSE2();
6408 bool HasAVX = Subtarget->hasAVX();
6409 bool HasAVX2 = Subtarget->hasAVX2();
6410 MachineFunction &MF = DAG.getMachineFunction();
6411 bool OptForSize = MF.getFunction()->hasFnAttr(Attribute::OptimizeForSize);
6413 assert(VT.getSizeInBits() != 64 && "Can't lower MMX shuffles");
6415 if (V1IsUndef && V2IsUndef)
6416 return DAG.getUNDEF(VT);
6418 assert(!V1IsUndef && "Op 1 of shuffle should not be undef");
6420 // Vector shuffle lowering takes 3 steps:
6422 // 1) Normalize the input vectors. Here splats, zeroed vectors, profitable
6423 // narrowing and commutation of operands should be handled.
6424 // 2) Matching of shuffles with known shuffle masks to x86 target specific
6426 // 3) Rewriting of unmatched masks into new generic shuffle operations,
6427 // so the shuffle can be broken into other shuffles and the legalizer can
6428 // try the lowering again.
6430 // The general idea is that no vector_shuffle operation should be left to
6431 // be matched during isel, all of them must be converted to a target specific
6434 // Normalize the input vectors. Here splats, zeroed vectors, profitable
6435 // narrowing and commutation of operands should be handled. The actual code
6436 // doesn't include all of those, work in progress...
6437 SDValue NewOp = NormalizeVectorShuffle(Op, DAG);
6438 if (NewOp.getNode())
6441 SmallVector<int, 8> M(SVOp->getMask().begin(), SVOp->getMask().end());
6443 // NOTE: isPSHUFDMask can also match both masks below (unpckl_undef and
6444 // unpckh_undef). Only use pshufd if speed is more important than size.
6445 if (OptForSize && isUNPCKL_v_undef_Mask(M, VT, HasAVX2))
6446 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
6447 if (OptForSize && isUNPCKH_v_undef_Mask(M, VT, HasAVX2))
6448 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
6450 if (isMOVDDUPMask(M, VT) && Subtarget->hasSSE3() &&
6451 V2IsUndef && RelaxedMayFoldVectorLoad(V1))
6452 return getMOVDDup(Op, dl, V1, DAG);
6454 if (isMOVHLPS_v_undef_Mask(M, VT))
6455 return getMOVHighToLow(Op, dl, DAG);
6457 // Use to match splats
6458 if (HasSSE2 && isUNPCKHMask(M, VT, HasAVX2) && V2IsUndef &&
6459 (VT == MVT::v2f64 || VT == MVT::v2i64))
6460 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
6462 if (isPSHUFDMask(M, VT)) {
6463 // The actual implementation will match the mask in the if above and then
6464 // during isel it can match several different instructions, not only pshufd
6465 // as its name says, sad but true, emulate the behavior for now...
6466 if (isMOVDDUPMask(M, VT) && ((VT == MVT::v4f32 || VT == MVT::v2i64)))
6467 return getTargetShuffleNode(X86ISD::MOVLHPS, dl, VT, V1, V1, DAG);
6469 unsigned TargetMask = getShuffleSHUFImmediate(SVOp);
6471 if (HasAVX && (VT == MVT::v4f32 || VT == MVT::v2f64))
6472 return getTargetShuffleNode(X86ISD::VPERMILP, dl, VT, V1, TargetMask, DAG);
6474 if (HasSSE2 && (VT == MVT::v4f32 || VT == MVT::v4i32))
6475 return getTargetShuffleNode(X86ISD::PSHUFD, dl, VT, V1, TargetMask, DAG);
6477 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V1, V1,
6481 // Check if this can be converted into a logical shift.
6482 bool isLeft = false;
6485 bool isShift = HasSSE2 && isVectorShift(SVOp, DAG, isLeft, ShVal, ShAmt);
6486 if (isShift && ShVal.hasOneUse()) {
6487 // If the shifted value has multiple uses, it may be cheaper to use
6488 // v_set0 + movlhps or movhlps, etc.
6489 EVT EltVT = VT.getVectorElementType();
6490 ShAmt *= EltVT.getSizeInBits();
6491 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl);
6494 if (isMOVLMask(M, VT)) {
6495 if (ISD::isBuildVectorAllZeros(V1.getNode()))
6496 return getVZextMovL(VT, VT, V2, DAG, Subtarget, dl);
6497 if (!isMOVLPMask(M, VT)) {
6498 if (HasSSE2 && (VT == MVT::v2i64 || VT == MVT::v2f64))
6499 return getTargetShuffleNode(X86ISD::MOVSD, dl, VT, V1, V2, DAG);
6501 if (VT == MVT::v4i32 || VT == MVT::v4f32)
6502 return getTargetShuffleNode(X86ISD::MOVSS, dl, VT, V1, V2, DAG);
6506 // FIXME: fold these into legal mask.
6507 if (isMOVLHPSMask(M, VT) && !isUNPCKLMask(M, VT, HasAVX2))
6508 return getMOVLowToHigh(Op, dl, DAG, HasSSE2);
6510 if (isMOVHLPSMask(M, VT))
6511 return getMOVHighToLow(Op, dl, DAG);
6513 if (V2IsUndef && isMOVSHDUPMask(M, VT, Subtarget))
6514 return getTargetShuffleNode(X86ISD::MOVSHDUP, dl, VT, V1, DAG);
6516 if (V2IsUndef && isMOVSLDUPMask(M, VT, Subtarget))
6517 return getTargetShuffleNode(X86ISD::MOVSLDUP, dl, VT, V1, DAG);
6519 if (isMOVLPMask(M, VT))
6520 return getMOVLP(Op, dl, DAG, HasSSE2);
6522 if (ShouldXformToMOVHLPS(M, VT) ||
6523 ShouldXformToMOVLP(V1.getNode(), V2.getNode(), M, VT))
6524 return CommuteVectorShuffle(SVOp, DAG);
6527 // No better options. Use a vshldq / vsrldq.
6528 EVT EltVT = VT.getVectorElementType();
6529 ShAmt *= EltVT.getSizeInBits();
6530 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl);
6533 bool Commuted = false;
6534 // FIXME: This should also accept a bitcast of a splat? Be careful, not
6535 // 1,1,1,1 -> v8i16 though.
6536 V1IsSplat = isSplatVector(V1.getNode());
6537 V2IsSplat = isSplatVector(V2.getNode());
6539 // Canonicalize the splat or undef, if present, to be on the RHS.
6540 if (!V2IsUndef && V1IsSplat && !V2IsSplat) {
6541 CommuteVectorShuffleMask(M, NumElems);
6543 std::swap(V1IsSplat, V2IsSplat);
6547 if (isCommutedMOVLMask(M, VT, V2IsSplat, V2IsUndef)) {
6548 // Shuffling low element of v1 into undef, just return v1.
6551 // If V2 is a splat, the mask may be malformed such as <4,3,3,3>, which
6552 // the instruction selector will not match, so get a canonical MOVL with
6553 // swapped operands to undo the commute.
6554 return getMOVL(DAG, dl, VT, V2, V1);
6557 if (isUNPCKLMask(M, VT, HasAVX2))
6558 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG);
6560 if (isUNPCKHMask(M, VT, HasAVX2))
6561 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG);
6564 // Normalize mask so all entries that point to V2 points to its first
6565 // element then try to match unpck{h|l} again. If match, return a
6566 // new vector_shuffle with the corrected mask.p
6567 SmallVector<int, 8> NewMask(M.begin(), M.end());
6568 NormalizeMask(NewMask, NumElems);
6569 if (isUNPCKLMask(NewMask, VT, HasAVX2, true)) {
6570 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG);
6571 } else if (isUNPCKHMask(NewMask, VT, HasAVX2, true)) {
6572 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG);
6577 // Commute is back and try unpck* again.
6578 // FIXME: this seems wrong.
6579 CommuteVectorShuffleMask(M, NumElems);
6581 std::swap(V1IsSplat, V2IsSplat);
6584 if (isUNPCKLMask(M, VT, HasAVX2))
6585 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG);
6587 if (isUNPCKHMask(M, VT, HasAVX2))
6588 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG);
6591 // Normalize the node to match x86 shuffle ops if needed
6592 if (!V2IsUndef && (isSHUFPMask(M, VT, HasAVX, /* Commuted */ true)))
6593 return CommuteVectorShuffle(SVOp, DAG);
6595 // The checks below are all present in isShuffleMaskLegal, but they are
6596 // inlined here right now to enable us to directly emit target specific
6597 // nodes, and remove one by one until they don't return Op anymore.
6599 if (isPALIGNRMask(M, VT, Subtarget))
6600 return getTargetShuffleNode(X86ISD::PALIGN, dl, VT, V1, V2,
6601 getShufflePALIGNRImmediate(SVOp),
6604 if (ShuffleVectorSDNode::isSplatMask(&M[0], VT) &&
6605 SVOp->getSplatIndex() == 0 && V2IsUndef) {
6606 if (VT == MVT::v2f64 || VT == MVT::v2i64)
6607 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
6610 if (isPSHUFHWMask(M, VT))
6611 return getTargetShuffleNode(X86ISD::PSHUFHW, dl, VT, V1,
6612 getShufflePSHUFHWImmediate(SVOp),
6615 if (isPSHUFLWMask(M, VT))
6616 return getTargetShuffleNode(X86ISD::PSHUFLW, dl, VT, V1,
6617 getShufflePSHUFLWImmediate(SVOp),
6620 if (isSHUFPMask(M, VT, HasAVX))
6621 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V1, V2,
6622 getShuffleSHUFImmediate(SVOp), DAG);
6624 if (isUNPCKL_v_undef_Mask(M, VT, HasAVX2))
6625 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
6626 if (isUNPCKH_v_undef_Mask(M, VT, HasAVX2))
6627 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
6629 //===--------------------------------------------------------------------===//
6630 // Generate target specific nodes for 128 or 256-bit shuffles only
6631 // supported in the AVX instruction set.
6634 // Handle VMOVDDUPY permutations
6635 if (V2IsUndef && isMOVDDUPYMask(M, VT, HasAVX))
6636 return getTargetShuffleNode(X86ISD::MOVDDUP, dl, VT, V1, DAG);
6638 // Handle VPERMILPS/D* permutations
6639 if (isVPERMILPMask(M, VT, HasAVX)) {
6640 if (HasAVX2 && VT == MVT::v8i32)
6641 return getTargetShuffleNode(X86ISD::PSHUFD, dl, VT, V1,
6642 getShuffleSHUFImmediate(SVOp), DAG);
6643 return getTargetShuffleNode(X86ISD::VPERMILP, dl, VT, V1,
6644 getShuffleSHUFImmediate(SVOp), DAG);
6647 // Handle VPERM2F128/VPERM2I128 permutations
6648 if (isVPERM2X128Mask(M, VT, HasAVX))
6649 return getTargetShuffleNode(X86ISD::VPERM2X128, dl, VT, V1,
6650 V2, getShuffleVPERM2X128Immediate(SVOp), DAG);
6652 SDValue BlendOp = LowerVECTOR_SHUFFLEtoBlend(Op, Subtarget, DAG);
6653 if (BlendOp.getNode())
6656 if (V2IsUndef && HasAVX2 && (VT == MVT::v8i32 || VT == MVT::v8f32)) {
6657 SmallVector<SDValue, 8> permclMask;
6658 for (unsigned i = 0; i != 8; ++i) {
6659 permclMask.push_back(DAG.getConstant((M[i]>=0) ? M[i] : 0, MVT::i32));
6661 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32,
6663 // Bitcast is for VPERMPS since mask is v8i32 but node takes v8f32
6664 return DAG.getNode(X86ISD::VPERMV, dl, VT,
6665 DAG.getNode(ISD::BITCAST, dl, VT, Mask), V1);
6668 if (V2IsUndef && HasAVX2 && (VT == MVT::v4i64 || VT == MVT::v4f64))
6669 return getTargetShuffleNode(X86ISD::VPERMI, dl, VT, V1,
6670 getShuffleCLImmediate(SVOp), DAG);
6673 //===--------------------------------------------------------------------===//
6674 // Since no target specific shuffle was selected for this generic one,
6675 // lower it into other known shuffles. FIXME: this isn't true yet, but
6676 // this is the plan.
6679 // Handle v8i16 specifically since SSE can do byte extraction and insertion.
6680 if (VT == MVT::v8i16) {
6681 SDValue NewOp = LowerVECTOR_SHUFFLEv8i16(Op, DAG);
6682 if (NewOp.getNode())
6686 if (VT == MVT::v16i8) {
6687 SDValue NewOp = LowerVECTOR_SHUFFLEv16i8(SVOp, DAG, *this);
6688 if (NewOp.getNode())
6692 // Handle all 128-bit wide vectors with 4 elements, and match them with
6693 // several different shuffle types.
6694 if (NumElems == 4 && VT.getSizeInBits() == 128)
6695 return LowerVECTOR_SHUFFLE_128v4(SVOp, DAG);
6697 // Handle general 256-bit shuffles
6698 if (VT.is256BitVector())
6699 return LowerVECTOR_SHUFFLE_256(SVOp, DAG);
6705 X86TargetLowering::LowerEXTRACT_VECTOR_ELT_SSE4(SDValue Op,
6706 SelectionDAG &DAG) const {
6707 EVT VT = Op.getValueType();
6708 DebugLoc dl = Op.getDebugLoc();
6710 if (Op.getOperand(0).getValueType().getSizeInBits() != 128)
6713 if (VT.getSizeInBits() == 8) {
6714 SDValue Extract = DAG.getNode(X86ISD::PEXTRB, dl, MVT::i32,
6715 Op.getOperand(0), Op.getOperand(1));
6716 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
6717 DAG.getValueType(VT));
6718 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
6719 } else if (VT.getSizeInBits() == 16) {
6720 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
6721 // If Idx is 0, it's cheaper to do a move instead of a pextrw.
6723 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
6724 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
6725 DAG.getNode(ISD::BITCAST, dl,
6729 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, MVT::i32,
6730 Op.getOperand(0), Op.getOperand(1));
6731 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
6732 DAG.getValueType(VT));
6733 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
6734 } else if (VT == MVT::f32) {
6735 // EXTRACTPS outputs to a GPR32 register which will require a movd to copy
6736 // the result back to FR32 register. It's only worth matching if the
6737 // result has a single use which is a store or a bitcast to i32. And in
6738 // the case of a store, it's not worth it if the index is a constant 0,
6739 // because a MOVSSmr can be used instead, which is smaller and faster.
6740 if (!Op.hasOneUse())
6742 SDNode *User = *Op.getNode()->use_begin();
6743 if ((User->getOpcode() != ISD::STORE ||
6744 (isa<ConstantSDNode>(Op.getOperand(1)) &&
6745 cast<ConstantSDNode>(Op.getOperand(1))->isNullValue())) &&
6746 (User->getOpcode() != ISD::BITCAST ||
6747 User->getValueType(0) != MVT::i32))
6749 SDValue Extract = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
6750 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32,
6753 return DAG.getNode(ISD::BITCAST, dl, MVT::f32, Extract);
6754 } else if (VT == MVT::i32 || VT == MVT::i64) {
6755 // ExtractPS/pextrq works with constant index.
6756 if (isa<ConstantSDNode>(Op.getOperand(1)))
6764 X86TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op,
6765 SelectionDAG &DAG) const {
6766 if (!isa<ConstantSDNode>(Op.getOperand(1)))
6769 SDValue Vec = Op.getOperand(0);
6770 EVT VecVT = Vec.getValueType();
6772 // If this is a 256-bit vector result, first extract the 128-bit vector and
6773 // then extract the element from the 128-bit vector.
6774 if (VecVT.getSizeInBits() == 256) {
6775 DebugLoc dl = Op.getNode()->getDebugLoc();
6776 unsigned NumElems = VecVT.getVectorNumElements();
6777 SDValue Idx = Op.getOperand(1);
6778 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
6780 // Get the 128-bit vector.
6781 bool Upper = IdxVal >= NumElems/2;
6782 Vec = Extract128BitVector(Vec,
6783 DAG.getConstant(Upper ? NumElems/2 : 0, MVT::i32), DAG, dl);
6785 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, Op.getValueType(), Vec,
6786 Upper ? DAG.getConstant(IdxVal-NumElems/2, MVT::i32) : Idx);
6789 assert(Vec.getValueSizeInBits() <= 128 && "Unexpected vector length");
6791 if (Subtarget->hasSSE41()) {
6792 SDValue Res = LowerEXTRACT_VECTOR_ELT_SSE4(Op, DAG);
6797 EVT VT = Op.getValueType();
6798 DebugLoc dl = Op.getDebugLoc();
6799 // TODO: handle v16i8.
6800 if (VT.getSizeInBits() == 16) {
6801 SDValue Vec = Op.getOperand(0);
6802 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
6804 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
6805 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
6806 DAG.getNode(ISD::BITCAST, dl,
6809 // Transform it so it match pextrw which produces a 32-bit result.
6810 EVT EltVT = MVT::i32;
6811 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, EltVT,
6812 Op.getOperand(0), Op.getOperand(1));
6813 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, EltVT, Extract,
6814 DAG.getValueType(VT));
6815 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
6816 } else if (VT.getSizeInBits() == 32) {
6817 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
6821 // SHUFPS the element to the lowest double word, then movss.
6822 int Mask[4] = { static_cast<int>(Idx), -1, -1, -1 };
6823 EVT VVT = Op.getOperand(0).getValueType();
6824 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
6825 DAG.getUNDEF(VVT), Mask);
6826 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
6827 DAG.getIntPtrConstant(0));
6828 } else if (VT.getSizeInBits() == 64) {
6829 // FIXME: .td only matches this for <2 x f64>, not <2 x i64> on 32b
6830 // FIXME: seems like this should be unnecessary if mov{h,l}pd were taught
6831 // to match extract_elt for f64.
6832 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
6836 // UNPCKHPD the element to the lowest double word, then movsd.
6837 // Note if the lower 64 bits of the result of the UNPCKHPD is then stored
6838 // to a f64mem, the whole operation is folded into a single MOVHPDmr.
6839 int Mask[2] = { 1, -1 };
6840 EVT VVT = Op.getOperand(0).getValueType();
6841 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
6842 DAG.getUNDEF(VVT), Mask);
6843 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
6844 DAG.getIntPtrConstant(0));
6851 X86TargetLowering::LowerINSERT_VECTOR_ELT_SSE4(SDValue Op,
6852 SelectionDAG &DAG) const {
6853 EVT VT = Op.getValueType();
6854 EVT EltVT = VT.getVectorElementType();
6855 DebugLoc dl = Op.getDebugLoc();
6857 SDValue N0 = Op.getOperand(0);
6858 SDValue N1 = Op.getOperand(1);
6859 SDValue N2 = Op.getOperand(2);
6861 if (VT.getSizeInBits() == 256)
6864 if ((EltVT.getSizeInBits() == 8 || EltVT.getSizeInBits() == 16) &&
6865 isa<ConstantSDNode>(N2)) {
6867 if (VT == MVT::v8i16)
6868 Opc = X86ISD::PINSRW;
6869 else if (VT == MVT::v16i8)
6870 Opc = X86ISD::PINSRB;
6872 Opc = X86ISD::PINSRB;
6874 // Transform it so it match pinsr{b,w} which expects a GR32 as its second
6876 if (N1.getValueType() != MVT::i32)
6877 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
6878 if (N2.getValueType() != MVT::i32)
6879 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue());
6880 return DAG.getNode(Opc, dl, VT, N0, N1, N2);
6881 } else if (EltVT == MVT::f32 && isa<ConstantSDNode>(N2)) {
6882 // Bits [7:6] of the constant are the source select. This will always be
6883 // zero here. The DAG Combiner may combine an extract_elt index into these
6884 // bits. For example (insert (extract, 3), 2) could be matched by putting
6885 // the '3' into bits [7:6] of X86ISD::INSERTPS.
6886 // Bits [5:4] of the constant are the destination select. This is the
6887 // value of the incoming immediate.
6888 // Bits [3:0] of the constant are the zero mask. The DAG Combiner may
6889 // combine either bitwise AND or insert of float 0.0 to set these bits.
6890 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue() << 4);
6891 // Create this as a scalar to vector..
6892 N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4f32, N1);
6893 return DAG.getNode(X86ISD::INSERTPS, dl, VT, N0, N1, N2);
6894 } else if ((EltVT == MVT::i32 || EltVT == MVT::i64) &&
6895 isa<ConstantSDNode>(N2)) {
6896 // PINSR* works with constant index.
6903 X86TargetLowering::LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const {
6904 EVT VT = Op.getValueType();
6905 EVT EltVT = VT.getVectorElementType();
6907 DebugLoc dl = Op.getDebugLoc();
6908 SDValue N0 = Op.getOperand(0);
6909 SDValue N1 = Op.getOperand(1);
6910 SDValue N2 = Op.getOperand(2);
6912 // If this is a 256-bit vector result, first extract the 128-bit vector,
6913 // insert the element into the extracted half and then place it back.
6914 if (VT.getSizeInBits() == 256) {
6915 if (!isa<ConstantSDNode>(N2))
6918 // Get the desired 128-bit vector half.
6919 unsigned NumElems = VT.getVectorNumElements();
6920 unsigned IdxVal = cast<ConstantSDNode>(N2)->getZExtValue();
6921 bool Upper = IdxVal >= NumElems/2;
6922 SDValue Ins128Idx = DAG.getConstant(Upper ? NumElems/2 : 0, MVT::i32);
6923 SDValue V = Extract128BitVector(N0, Ins128Idx, DAG, dl);
6925 // Insert the element into the desired half.
6926 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, V.getValueType(), V,
6927 N1, Upper ? DAG.getConstant(IdxVal-NumElems/2, MVT::i32) : N2);
6929 // Insert the changed part back to the 256-bit vector
6930 return Insert128BitVector(N0, V, Ins128Idx, DAG, dl);
6933 if (Subtarget->hasSSE41())
6934 return LowerINSERT_VECTOR_ELT_SSE4(Op, DAG);
6936 if (EltVT == MVT::i8)
6939 if (EltVT.getSizeInBits() == 16 && isa<ConstantSDNode>(N2)) {
6940 // Transform it so it match pinsrw which expects a 16-bit value in a GR32
6941 // as its second argument.
6942 if (N1.getValueType() != MVT::i32)
6943 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
6944 if (N2.getValueType() != MVT::i32)
6945 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue());
6946 return DAG.getNode(X86ISD::PINSRW, dl, VT, N0, N1, N2);
6952 X86TargetLowering::LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) const {
6953 LLVMContext *Context = DAG.getContext();
6954 DebugLoc dl = Op.getDebugLoc();
6955 EVT OpVT = Op.getValueType();
6957 // If this is a 256-bit vector result, first insert into a 128-bit
6958 // vector and then insert into the 256-bit vector.
6959 if (OpVT.getSizeInBits() > 128) {
6960 // Insert into a 128-bit vector.
6961 EVT VT128 = EVT::getVectorVT(*Context,
6962 OpVT.getVectorElementType(),
6963 OpVT.getVectorNumElements() / 2);
6965 Op = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT128, Op.getOperand(0));
6967 // Insert the 128-bit vector.
6968 return Insert128BitVector(DAG.getNode(ISD::UNDEF, dl, OpVT), Op,
6969 DAG.getConstant(0, MVT::i32),
6973 if (Op.getValueType() == MVT::v1i64 &&
6974 Op.getOperand(0).getValueType() == MVT::i64)
6975 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v1i64, Op.getOperand(0));
6977 SDValue AnyExt = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, Op.getOperand(0));
6978 assert(Op.getValueType().getSimpleVT().getSizeInBits() == 128 &&
6979 "Expected an SSE type!");
6980 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(),
6981 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,AnyExt));
6984 // Lower a node with an EXTRACT_SUBVECTOR opcode. This may result in
6985 // a simple subregister reference or explicit instructions to grab
6986 // upper bits of a vector.
6988 X86TargetLowering::LowerEXTRACT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const {
6989 if (Subtarget->hasAVX()) {
6990 DebugLoc dl = Op.getNode()->getDebugLoc();
6991 SDValue Vec = Op.getNode()->getOperand(0);
6992 SDValue Idx = Op.getNode()->getOperand(1);
6994 if (Op.getNode()->getValueType(0).getSizeInBits() == 128
6995 && Vec.getNode()->getValueType(0).getSizeInBits() == 256) {
6996 return Extract128BitVector(Vec, Idx, DAG, dl);
7002 // Lower a node with an INSERT_SUBVECTOR opcode. This may result in a
7003 // simple superregister reference or explicit instructions to insert
7004 // the upper bits of a vector.
7006 X86TargetLowering::LowerINSERT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const {
7007 if (Subtarget->hasAVX()) {
7008 DebugLoc dl = Op.getNode()->getDebugLoc();
7009 SDValue Vec = Op.getNode()->getOperand(0);
7010 SDValue SubVec = Op.getNode()->getOperand(1);
7011 SDValue Idx = Op.getNode()->getOperand(2);
7013 if (Op.getNode()->getValueType(0).getSizeInBits() == 256
7014 && SubVec.getNode()->getValueType(0).getSizeInBits() == 128) {
7015 return Insert128BitVector(Vec, SubVec, Idx, DAG, dl);
7021 // ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as
7022 // their target countpart wrapped in the X86ISD::Wrapper node. Suppose N is
7023 // one of the above mentioned nodes. It has to be wrapped because otherwise
7024 // Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only
7025 // be used to form addressing mode. These wrapped nodes will be selected
7028 X86TargetLowering::LowerConstantPool(SDValue Op, SelectionDAG &DAG) const {
7029 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
7031 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
7033 unsigned char OpFlag = 0;
7034 unsigned WrapperKind = X86ISD::Wrapper;
7035 CodeModel::Model M = getTargetMachine().getCodeModel();
7037 if (Subtarget->isPICStyleRIPRel() &&
7038 (M == CodeModel::Small || M == CodeModel::Kernel))
7039 WrapperKind = X86ISD::WrapperRIP;
7040 else if (Subtarget->isPICStyleGOT())
7041 OpFlag = X86II::MO_GOTOFF;
7042 else if (Subtarget->isPICStyleStubPIC())
7043 OpFlag = X86II::MO_PIC_BASE_OFFSET;
7045 SDValue Result = DAG.getTargetConstantPool(CP->getConstVal(), getPointerTy(),
7047 CP->getOffset(), OpFlag);
7048 DebugLoc DL = CP->getDebugLoc();
7049 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
7050 // With PIC, the address is actually $g + Offset.
7052 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
7053 DAG.getNode(X86ISD::GlobalBaseReg,
7054 DebugLoc(), getPointerTy()),
7061 SDValue X86TargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) const {
7062 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
7064 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
7066 unsigned char OpFlag = 0;
7067 unsigned WrapperKind = X86ISD::Wrapper;
7068 CodeModel::Model M = getTargetMachine().getCodeModel();
7070 if (Subtarget->isPICStyleRIPRel() &&
7071 (M == CodeModel::Small || M == CodeModel::Kernel))
7072 WrapperKind = X86ISD::WrapperRIP;
7073 else if (Subtarget->isPICStyleGOT())
7074 OpFlag = X86II::MO_GOTOFF;
7075 else if (Subtarget->isPICStyleStubPIC())
7076 OpFlag = X86II::MO_PIC_BASE_OFFSET;
7078 SDValue Result = DAG.getTargetJumpTable(JT->getIndex(), getPointerTy(),
7080 DebugLoc DL = JT->getDebugLoc();
7081 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
7083 // With PIC, the address is actually $g + Offset.
7085 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
7086 DAG.getNode(X86ISD::GlobalBaseReg,
7087 DebugLoc(), getPointerTy()),
7094 X86TargetLowering::LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) const {
7095 const char *Sym = cast<ExternalSymbolSDNode>(Op)->getSymbol();
7097 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
7099 unsigned char OpFlag = 0;
7100 unsigned WrapperKind = X86ISD::Wrapper;
7101 CodeModel::Model M = getTargetMachine().getCodeModel();
7103 if (Subtarget->isPICStyleRIPRel() &&
7104 (M == CodeModel::Small || M == CodeModel::Kernel)) {
7105 if (Subtarget->isTargetDarwin() || Subtarget->isTargetELF())
7106 OpFlag = X86II::MO_GOTPCREL;
7107 WrapperKind = X86ISD::WrapperRIP;
7108 } else if (Subtarget->isPICStyleGOT()) {
7109 OpFlag = X86II::MO_GOT;
7110 } else if (Subtarget->isPICStyleStubPIC()) {
7111 OpFlag = X86II::MO_DARWIN_NONLAZY_PIC_BASE;
7112 } else if (Subtarget->isPICStyleStubNoDynamic()) {
7113 OpFlag = X86II::MO_DARWIN_NONLAZY;
7116 SDValue Result = DAG.getTargetExternalSymbol(Sym, getPointerTy(), OpFlag);
7118 DebugLoc DL = Op.getDebugLoc();
7119 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
7122 // With PIC, the address is actually $g + Offset.
7123 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
7124 !Subtarget->is64Bit()) {
7125 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
7126 DAG.getNode(X86ISD::GlobalBaseReg,
7127 DebugLoc(), getPointerTy()),
7131 // For symbols that require a load from a stub to get the address, emit the
7133 if (isGlobalStubReference(OpFlag))
7134 Result = DAG.getLoad(getPointerTy(), DL, DAG.getEntryNode(), Result,
7135 MachinePointerInfo::getGOT(), false, false, false, 0);
7141 X86TargetLowering::LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const {
7142 // Create the TargetBlockAddressAddress node.
7143 unsigned char OpFlags =
7144 Subtarget->ClassifyBlockAddressReference();
7145 CodeModel::Model M = getTargetMachine().getCodeModel();
7146 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
7147 DebugLoc dl = Op.getDebugLoc();
7148 SDValue Result = DAG.getBlockAddress(BA, getPointerTy(),
7149 /*isTarget=*/true, OpFlags);
7151 if (Subtarget->isPICStyleRIPRel() &&
7152 (M == CodeModel::Small || M == CodeModel::Kernel))
7153 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
7155 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
7157 // With PIC, the address is actually $g + Offset.
7158 if (isGlobalRelativeToPICBase(OpFlags)) {
7159 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
7160 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
7168 X86TargetLowering::LowerGlobalAddress(const GlobalValue *GV, DebugLoc dl,
7170 SelectionDAG &DAG) const {
7171 // Create the TargetGlobalAddress node, folding in the constant
7172 // offset if it is legal.
7173 unsigned char OpFlags =
7174 Subtarget->ClassifyGlobalReference(GV, getTargetMachine());
7175 CodeModel::Model M = getTargetMachine().getCodeModel();
7177 if (OpFlags == X86II::MO_NO_FLAG &&
7178 X86::isOffsetSuitableForCodeModel(Offset, M)) {
7179 // A direct static reference to a global.
7180 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), Offset);
7183 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), 0, OpFlags);
7186 if (Subtarget->isPICStyleRIPRel() &&
7187 (M == CodeModel::Small || M == CodeModel::Kernel))
7188 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
7190 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
7192 // With PIC, the address is actually $g + Offset.
7193 if (isGlobalRelativeToPICBase(OpFlags)) {
7194 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
7195 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
7199 // For globals that require a load from a stub to get the address, emit the
7201 if (isGlobalStubReference(OpFlags))
7202 Result = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Result,
7203 MachinePointerInfo::getGOT(), false, false, false, 0);
7205 // If there was a non-zero offset that we didn't fold, create an explicit
7208 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(), Result,
7209 DAG.getConstant(Offset, getPointerTy()));
7215 X86TargetLowering::LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const {
7216 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
7217 int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset();
7218 return LowerGlobalAddress(GV, Op.getDebugLoc(), Offset, DAG);
7222 GetTLSADDR(SelectionDAG &DAG, SDValue Chain, GlobalAddressSDNode *GA,
7223 SDValue *InFlag, const EVT PtrVT, unsigned ReturnReg,
7224 unsigned char OperandFlags) {
7225 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
7226 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
7227 DebugLoc dl = GA->getDebugLoc();
7228 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
7229 GA->getValueType(0),
7233 SDValue Ops[] = { Chain, TGA, *InFlag };
7234 Chain = DAG.getNode(X86ISD::TLSADDR, dl, NodeTys, Ops, 3);
7236 SDValue Ops[] = { Chain, TGA };
7237 Chain = DAG.getNode(X86ISD::TLSADDR, dl, NodeTys, Ops, 2);
7240 // TLSADDR will be codegen'ed as call. Inform MFI that function has calls.
7241 MFI->setAdjustsStack(true);
7243 SDValue Flag = Chain.getValue(1);
7244 return DAG.getCopyFromReg(Chain, dl, ReturnReg, PtrVT, Flag);
7247 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 32 bit
7249 LowerToTLSGeneralDynamicModel32(GlobalAddressSDNode *GA, SelectionDAG &DAG,
7252 DebugLoc dl = GA->getDebugLoc(); // ? function entry point might be better
7253 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
7254 DAG.getNode(X86ISD::GlobalBaseReg,
7255 DebugLoc(), PtrVT), InFlag);
7256 InFlag = Chain.getValue(1);
7258 return GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX, X86II::MO_TLSGD);
7261 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 64 bit
7263 LowerToTLSGeneralDynamicModel64(GlobalAddressSDNode *GA, SelectionDAG &DAG,
7265 return GetTLSADDR(DAG, DAG.getEntryNode(), GA, NULL, PtrVT,
7266 X86::RAX, X86II::MO_TLSGD);
7269 // Lower ISD::GlobalTLSAddress using the "initial exec" (for no-pic) or
7270 // "local exec" model.
7271 static SDValue LowerToTLSExecModel(GlobalAddressSDNode *GA, SelectionDAG &DAG,
7272 const EVT PtrVT, TLSModel::Model model,
7274 DebugLoc dl = GA->getDebugLoc();
7276 // Get the Thread Pointer, which is %gs:0 (32-bit) or %fs:0 (64-bit).
7277 Value *Ptr = Constant::getNullValue(Type::getInt8PtrTy(*DAG.getContext(),
7278 is64Bit ? 257 : 256));
7280 SDValue ThreadPointer = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
7281 DAG.getIntPtrConstant(0),
7282 MachinePointerInfo(Ptr),
7283 false, false, false, 0);
7285 unsigned char OperandFlags = 0;
7286 // Most TLS accesses are not RIP relative, even on x86-64. One exception is
7288 unsigned WrapperKind = X86ISD::Wrapper;
7289 if (model == TLSModel::LocalExec) {
7290 OperandFlags = is64Bit ? X86II::MO_TPOFF : X86II::MO_NTPOFF;
7291 } else if (is64Bit) {
7292 assert(model == TLSModel::InitialExec);
7293 OperandFlags = X86II::MO_GOTTPOFF;
7294 WrapperKind = X86ISD::WrapperRIP;
7296 assert(model == TLSModel::InitialExec);
7297 OperandFlags = X86II::MO_INDNTPOFF;
7300 // emit "addl x@ntpoff,%eax" (local exec) or "addl x@indntpoff,%eax" (initial
7302 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
7303 GA->getValueType(0),
7304 GA->getOffset(), OperandFlags);
7305 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
7307 if (model == TLSModel::InitialExec)
7308 Offset = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Offset,
7309 MachinePointerInfo::getGOT(), false, false, false, 0);
7311 // The address of the thread local variable is the add of the thread
7312 // pointer with the offset of the variable.
7313 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset);
7317 X86TargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const {
7319 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
7320 const GlobalValue *GV = GA->getGlobal();
7322 if (Subtarget->isTargetELF()) {
7323 // TODO: implement the "local dynamic" model
7324 // TODO: implement the "initial exec"model for pic executables
7326 // If GV is an alias then use the aliasee for determining
7327 // thread-localness.
7328 if (const GlobalAlias *GA = dyn_cast<GlobalAlias>(GV))
7329 GV = GA->resolveAliasedGlobal(false);
7331 TLSModel::Model model = getTargetMachine().getTLSModel(GV);
7334 case TLSModel::GeneralDynamic:
7335 case TLSModel::LocalDynamic: // not implemented
7336 if (Subtarget->is64Bit())
7337 return LowerToTLSGeneralDynamicModel64(GA, DAG, getPointerTy());
7338 return LowerToTLSGeneralDynamicModel32(GA, DAG, getPointerTy());
7340 case TLSModel::InitialExec:
7341 case TLSModel::LocalExec:
7342 return LowerToTLSExecModel(GA, DAG, getPointerTy(), model,
7343 Subtarget->is64Bit());
7345 } else if (Subtarget->isTargetDarwin()) {
7346 // Darwin only has one model of TLS. Lower to that.
7347 unsigned char OpFlag = 0;
7348 unsigned WrapperKind = Subtarget->isPICStyleRIPRel() ?
7349 X86ISD::WrapperRIP : X86ISD::Wrapper;
7351 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
7353 bool PIC32 = (getTargetMachine().getRelocationModel() == Reloc::PIC_) &&
7354 !Subtarget->is64Bit();
7356 OpFlag = X86II::MO_TLVP_PIC_BASE;
7358 OpFlag = X86II::MO_TLVP;
7359 DebugLoc DL = Op.getDebugLoc();
7360 SDValue Result = DAG.getTargetGlobalAddress(GA->getGlobal(), DL,
7361 GA->getValueType(0),
7362 GA->getOffset(), OpFlag);
7363 SDValue Offset = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
7365 // With PIC32, the address is actually $g + Offset.
7367 Offset = DAG.getNode(ISD::ADD, DL, getPointerTy(),
7368 DAG.getNode(X86ISD::GlobalBaseReg,
7369 DebugLoc(), getPointerTy()),
7372 // Lowering the machine isd will make sure everything is in the right
7374 SDValue Chain = DAG.getEntryNode();
7375 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
7376 SDValue Args[] = { Chain, Offset };
7377 Chain = DAG.getNode(X86ISD::TLSCALL, DL, NodeTys, Args, 2);
7379 // TLSCALL will be codegen'ed as call. Inform MFI that function has calls.
7380 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
7381 MFI->setAdjustsStack(true);
7383 // And our return value (tls address) is in the standard call return value
7385 unsigned Reg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
7386 return DAG.getCopyFromReg(Chain, DL, Reg, getPointerTy(),
7388 } else if (Subtarget->isTargetWindows()) {
7389 // Just use the implicit TLS architecture
7390 // Need to generate someting similar to:
7391 // mov rdx, qword [gs:abs 58H]; Load pointer to ThreadLocalStorage
7393 // mov ecx, dword [rel _tls_index]: Load index (from C runtime)
7394 // mov rcx, qword [rdx+rcx*8]
7395 // mov eax, .tls$:tlsvar
7396 // [rax+rcx] contains the address
7397 // Windows 64bit: gs:0x58
7398 // Windows 32bit: fs:__tls_array
7400 // If GV is an alias then use the aliasee for determining
7401 // thread-localness.
7402 if (const GlobalAlias *GA = dyn_cast<GlobalAlias>(GV))
7403 GV = GA->resolveAliasedGlobal(false);
7404 DebugLoc dl = GA->getDebugLoc();
7405 SDValue Chain = DAG.getEntryNode();
7407 // Get the Thread Pointer, which is %fs:__tls_array (32-bit) or
7408 // %gs:0x58 (64-bit).
7409 Value *Ptr = Constant::getNullValue(Subtarget->is64Bit()
7410 ? Type::getInt8PtrTy(*DAG.getContext(),
7412 : Type::getInt32PtrTy(*DAG.getContext(),
7415 SDValue ThreadPointer = DAG.getLoad(getPointerTy(), dl, Chain,
7416 Subtarget->is64Bit()
7417 ? DAG.getIntPtrConstant(0x58)
7418 : DAG.getExternalSymbol("_tls_array",
7420 MachinePointerInfo(Ptr),
7421 false, false, false, 0);
7423 // Load the _tls_index variable
7424 SDValue IDX = DAG.getExternalSymbol("_tls_index", getPointerTy());
7425 if (Subtarget->is64Bit())
7426 IDX = DAG.getExtLoad(ISD::ZEXTLOAD, dl, getPointerTy(), Chain,
7427 IDX, MachinePointerInfo(), MVT::i32,
7430 IDX = DAG.getLoad(getPointerTy(), dl, Chain, IDX, MachinePointerInfo(),
7431 false, false, false, 0);
7433 SDValue Scale = DAG.getConstant(Log2_64_Ceil(TD->getPointerSize()),
7435 IDX = DAG.getNode(ISD::SHL, dl, getPointerTy(), IDX, Scale);
7437 SDValue res = DAG.getNode(ISD::ADD, dl, getPointerTy(), ThreadPointer, IDX);
7438 res = DAG.getLoad(getPointerTy(), dl, Chain, res, MachinePointerInfo(),
7439 false, false, false, 0);
7441 // Get the offset of start of .tls section
7442 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
7443 GA->getValueType(0),
7444 GA->getOffset(), X86II::MO_SECREL);
7445 SDValue Offset = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), TGA);
7447 // The address of the thread local variable is the add of the thread
7448 // pointer with the offset of the variable.
7449 return DAG.getNode(ISD::ADD, dl, getPointerTy(), res, Offset);
7452 llvm_unreachable("TLS not implemented for this target.");
7456 /// LowerShiftParts - Lower SRA_PARTS and friends, which return two i32 values
7457 /// and take a 2 x i32 value to shift plus a shift amount.
7458 SDValue X86TargetLowering::LowerShiftParts(SDValue Op, SelectionDAG &DAG) const{
7459 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
7460 EVT VT = Op.getValueType();
7461 unsigned VTBits = VT.getSizeInBits();
7462 DebugLoc dl = Op.getDebugLoc();
7463 bool isSRA = Op.getOpcode() == ISD::SRA_PARTS;
7464 SDValue ShOpLo = Op.getOperand(0);
7465 SDValue ShOpHi = Op.getOperand(1);
7466 SDValue ShAmt = Op.getOperand(2);
7467 SDValue Tmp1 = isSRA ? DAG.getNode(ISD::SRA, dl, VT, ShOpHi,
7468 DAG.getConstant(VTBits - 1, MVT::i8))
7469 : DAG.getConstant(0, VT);
7472 if (Op.getOpcode() == ISD::SHL_PARTS) {
7473 Tmp2 = DAG.getNode(X86ISD::SHLD, dl, VT, ShOpHi, ShOpLo, ShAmt);
7474 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ShAmt);
7476 Tmp2 = DAG.getNode(X86ISD::SHRD, dl, VT, ShOpLo, ShOpHi, ShAmt);
7477 Tmp3 = DAG.getNode(isSRA ? ISD::SRA : ISD::SRL, dl, VT, ShOpHi, ShAmt);
7480 SDValue AndNode = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt,
7481 DAG.getConstant(VTBits, MVT::i8));
7482 SDValue Cond = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
7483 AndNode, DAG.getConstant(0, MVT::i8));
7486 SDValue CC = DAG.getConstant(X86::COND_NE, MVT::i8);
7487 SDValue Ops0[4] = { Tmp2, Tmp3, CC, Cond };
7488 SDValue Ops1[4] = { Tmp3, Tmp1, CC, Cond };
7490 if (Op.getOpcode() == ISD::SHL_PARTS) {
7491 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0, 4);
7492 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1, 4);
7494 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0, 4);
7495 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1, 4);
7498 SDValue Ops[2] = { Lo, Hi };
7499 return DAG.getMergeValues(Ops, 2, dl);
7502 SDValue X86TargetLowering::LowerSINT_TO_FP(SDValue Op,
7503 SelectionDAG &DAG) const {
7504 EVT SrcVT = Op.getOperand(0).getValueType();
7506 if (SrcVT.isVector())
7509 assert(SrcVT.getSimpleVT() <= MVT::i64 && SrcVT.getSimpleVT() >= MVT::i16 &&
7510 "Unknown SINT_TO_FP to lower!");
7512 // These are really Legal; return the operand so the caller accepts it as
7514 if (SrcVT == MVT::i32 && isScalarFPTypeInSSEReg(Op.getValueType()))
7516 if (SrcVT == MVT::i64 && isScalarFPTypeInSSEReg(Op.getValueType()) &&
7517 Subtarget->is64Bit()) {
7521 DebugLoc dl = Op.getDebugLoc();
7522 unsigned Size = SrcVT.getSizeInBits()/8;
7523 MachineFunction &MF = DAG.getMachineFunction();
7524 int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size, false);
7525 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
7526 SDValue Chain = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
7528 MachinePointerInfo::getFixedStack(SSFI),
7530 return BuildFILD(Op, SrcVT, Chain, StackSlot, DAG);
7533 SDValue X86TargetLowering::BuildFILD(SDValue Op, EVT SrcVT, SDValue Chain,
7535 SelectionDAG &DAG) const {
7537 DebugLoc DL = Op.getDebugLoc();
7539 bool useSSE = isScalarFPTypeInSSEReg(Op.getValueType());
7541 Tys = DAG.getVTList(MVT::f64, MVT::Other, MVT::Glue);
7543 Tys = DAG.getVTList(Op.getValueType(), MVT::Other);
7545 unsigned ByteSize = SrcVT.getSizeInBits()/8;
7547 FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(StackSlot);
7548 MachineMemOperand *MMO;
7550 int SSFI = FI->getIndex();
7552 DAG.getMachineFunction()
7553 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
7554 MachineMemOperand::MOLoad, ByteSize, ByteSize);
7556 MMO = cast<LoadSDNode>(StackSlot)->getMemOperand();
7557 StackSlot = StackSlot.getOperand(1);
7559 SDValue Ops[] = { Chain, StackSlot, DAG.getValueType(SrcVT) };
7560 SDValue Result = DAG.getMemIntrinsicNode(useSSE ? X86ISD::FILD_FLAG :
7562 Tys, Ops, array_lengthof(Ops),
7566 Chain = Result.getValue(1);
7567 SDValue InFlag = Result.getValue(2);
7569 // FIXME: Currently the FST is flagged to the FILD_FLAG. This
7570 // shouldn't be necessary except that RFP cannot be live across
7571 // multiple blocks. When stackifier is fixed, they can be uncoupled.
7572 MachineFunction &MF = DAG.getMachineFunction();
7573 unsigned SSFISize = Op.getValueType().getSizeInBits()/8;
7574 int SSFI = MF.getFrameInfo()->CreateStackObject(SSFISize, SSFISize, false);
7575 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
7576 Tys = DAG.getVTList(MVT::Other);
7578 Chain, Result, StackSlot, DAG.getValueType(Op.getValueType()), InFlag
7580 MachineMemOperand *MMO =
7581 DAG.getMachineFunction()
7582 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
7583 MachineMemOperand::MOStore, SSFISize, SSFISize);
7585 Chain = DAG.getMemIntrinsicNode(X86ISD::FST, DL, Tys,
7586 Ops, array_lengthof(Ops),
7587 Op.getValueType(), MMO);
7588 Result = DAG.getLoad(Op.getValueType(), DL, Chain, StackSlot,
7589 MachinePointerInfo::getFixedStack(SSFI),
7590 false, false, false, 0);
7596 // LowerUINT_TO_FP_i64 - 64-bit unsigned integer to double expansion.
7597 SDValue X86TargetLowering::LowerUINT_TO_FP_i64(SDValue Op,
7598 SelectionDAG &DAG) const {
7599 // This algorithm is not obvious. Here it is what we're trying to output:
7602 punpckldq (c0), %xmm0 // c0: (uint4){ 0x43300000U, 0x45300000U, 0U, 0U }
7603 subpd (c1), %xmm0 // c1: (double2){ 0x1.0p52, 0x1.0p52 * 0x1.0p32 }
7607 pshufd $0x4e, %xmm0, %xmm1
7612 DebugLoc dl = Op.getDebugLoc();
7613 LLVMContext *Context = DAG.getContext();
7615 // Build some magic constants.
7616 const uint32_t CV0[] = { 0x43300000, 0x45300000, 0, 0 };
7617 Constant *C0 = ConstantDataVector::get(*Context, CV0);
7618 SDValue CPIdx0 = DAG.getConstantPool(C0, getPointerTy(), 16);
7620 SmallVector<Constant*,2> CV1;
7622 ConstantFP::get(*Context, APFloat(APInt(64, 0x4330000000000000ULL))));
7624 ConstantFP::get(*Context, APFloat(APInt(64, 0x4530000000000000ULL))));
7625 Constant *C1 = ConstantVector::get(CV1);
7626 SDValue CPIdx1 = DAG.getConstantPool(C1, getPointerTy(), 16);
7628 // Load the 64-bit value into an XMM register.
7629 SDValue XR1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
7631 SDValue CLod0 = DAG.getLoad(MVT::v4i32, dl, DAG.getEntryNode(), CPIdx0,
7632 MachinePointerInfo::getConstantPool(),
7633 false, false, false, 16);
7634 SDValue Unpck1 = getUnpackl(DAG, dl, MVT::v4i32,
7635 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, XR1),
7638 SDValue CLod1 = DAG.getLoad(MVT::v2f64, dl, CLod0.getValue(1), CPIdx1,
7639 MachinePointerInfo::getConstantPool(),
7640 false, false, false, 16);
7641 SDValue XR2F = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Unpck1);
7642 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, XR2F, CLod1);
7645 if (Subtarget->hasSSE3()) {
7646 // FIXME: The 'haddpd' instruction may be slower than 'movhlps + addsd'.
7647 Result = DAG.getNode(X86ISD::FHADD, dl, MVT::v2f64, Sub, Sub);
7649 SDValue S2F = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Sub);
7650 SDValue Shuffle = getTargetShuffleNode(X86ISD::PSHUFD, dl, MVT::v4i32,
7652 Result = DAG.getNode(ISD::FADD, dl, MVT::v2f64,
7653 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Shuffle),
7657 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Result,
7658 DAG.getIntPtrConstant(0));
7661 // LowerUINT_TO_FP_i32 - 32-bit unsigned integer to float expansion.
7662 SDValue X86TargetLowering::LowerUINT_TO_FP_i32(SDValue Op,
7663 SelectionDAG &DAG) const {
7664 DebugLoc dl = Op.getDebugLoc();
7665 // FP constant to bias correct the final result.
7666 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL),
7669 // Load the 32-bit value into an XMM register.
7670 SDValue Load = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,
7673 // Zero out the upper parts of the register.
7674 Load = getShuffleVectorZeroOrUndef(Load, 0, true, Subtarget, DAG);
7676 Load = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
7677 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Load),
7678 DAG.getIntPtrConstant(0));
7680 // Or the load with the bias.
7681 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64,
7682 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
7683 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
7685 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
7686 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
7687 MVT::v2f64, Bias)));
7688 Or = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
7689 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Or),
7690 DAG.getIntPtrConstant(0));
7692 // Subtract the bias.
7693 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Or, Bias);
7695 // Handle final rounding.
7696 EVT DestVT = Op.getValueType();
7698 if (DestVT.bitsLT(MVT::f64)) {
7699 return DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub,
7700 DAG.getIntPtrConstant(0));
7701 } else if (DestVT.bitsGT(MVT::f64)) {
7702 return DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub);
7705 // Handle final rounding.
7709 SDValue X86TargetLowering::LowerUINT_TO_FP(SDValue Op,
7710 SelectionDAG &DAG) const {
7711 SDValue N0 = Op.getOperand(0);
7712 DebugLoc dl = Op.getDebugLoc();
7714 // Since UINT_TO_FP is legal (it's marked custom), dag combiner won't
7715 // optimize it to a SINT_TO_FP when the sign bit is known zero. Perform
7716 // the optimization here.
7717 if (DAG.SignBitIsZero(N0))
7718 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(), N0);
7720 EVT SrcVT = N0.getValueType();
7721 EVT DstVT = Op.getValueType();
7722 if (SrcVT == MVT::i64 && DstVT == MVT::f64 && X86ScalarSSEf64)
7723 return LowerUINT_TO_FP_i64(Op, DAG);
7724 else if (SrcVT == MVT::i32 && X86ScalarSSEf64)
7725 return LowerUINT_TO_FP_i32(Op, DAG);
7726 else if (Subtarget->is64Bit() &&
7727 SrcVT == MVT::i64 && DstVT == MVT::f32)
7730 // Make a 64-bit buffer, and use it to build an FILD.
7731 SDValue StackSlot = DAG.CreateStackTemporary(MVT::i64);
7732 if (SrcVT == MVT::i32) {
7733 SDValue WordOff = DAG.getConstant(4, getPointerTy());
7734 SDValue OffsetSlot = DAG.getNode(ISD::ADD, dl,
7735 getPointerTy(), StackSlot, WordOff);
7736 SDValue Store1 = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
7737 StackSlot, MachinePointerInfo(),
7739 SDValue Store2 = DAG.getStore(Store1, dl, DAG.getConstant(0, MVT::i32),
7740 OffsetSlot, MachinePointerInfo(),
7742 SDValue Fild = BuildFILD(Op, MVT::i64, Store2, StackSlot, DAG);
7746 assert(SrcVT == MVT::i64 && "Unexpected type in UINT_TO_FP");
7747 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
7748 StackSlot, MachinePointerInfo(),
7750 // For i64 source, we need to add the appropriate power of 2 if the input
7751 // was negative. This is the same as the optimization in
7752 // DAGTypeLegalizer::ExpandIntOp_UNIT_TO_FP, and for it to be safe here,
7753 // we must be careful to do the computation in x87 extended precision, not
7754 // in SSE. (The generic code can't know it's OK to do this, or how to.)
7755 int SSFI = cast<FrameIndexSDNode>(StackSlot)->getIndex();
7756 MachineMemOperand *MMO =
7757 DAG.getMachineFunction()
7758 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
7759 MachineMemOperand::MOLoad, 8, 8);
7761 SDVTList Tys = DAG.getVTList(MVT::f80, MVT::Other);
7762 SDValue Ops[] = { Store, StackSlot, DAG.getValueType(MVT::i64) };
7763 SDValue Fild = DAG.getMemIntrinsicNode(X86ISD::FILD, dl, Tys, Ops, 3,
7766 APInt FF(32, 0x5F800000ULL);
7768 // Check whether the sign bit is set.
7769 SDValue SignSet = DAG.getSetCC(dl, getSetCCResultType(MVT::i64),
7770 Op.getOperand(0), DAG.getConstant(0, MVT::i64),
7773 // Build a 64 bit pair (0, FF) in the constant pool, with FF in the lo bits.
7774 SDValue FudgePtr = DAG.getConstantPool(
7775 ConstantInt::get(*DAG.getContext(), FF.zext(64)),
7778 // Get a pointer to FF if the sign bit was set, or to 0 otherwise.
7779 SDValue Zero = DAG.getIntPtrConstant(0);
7780 SDValue Four = DAG.getIntPtrConstant(4);
7781 SDValue Offset = DAG.getNode(ISD::SELECT, dl, Zero.getValueType(), SignSet,
7783 FudgePtr = DAG.getNode(ISD::ADD, dl, getPointerTy(), FudgePtr, Offset);
7785 // Load the value out, extending it from f32 to f80.
7786 // FIXME: Avoid the extend by constructing the right constant pool?
7787 SDValue Fudge = DAG.getExtLoad(ISD::EXTLOAD, dl, MVT::f80, DAG.getEntryNode(),
7788 FudgePtr, MachinePointerInfo::getConstantPool(),
7789 MVT::f32, false, false, 4);
7790 // Extend everything to 80 bits to force it to be done on x87.
7791 SDValue Add = DAG.getNode(ISD::FADD, dl, MVT::f80, Fild, Fudge);
7792 return DAG.getNode(ISD::FP_ROUND, dl, DstVT, Add, DAG.getIntPtrConstant(0));
7795 std::pair<SDValue,SDValue> X86TargetLowering::
7796 FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG, bool IsSigned, bool IsReplace) const {
7797 DebugLoc DL = Op.getDebugLoc();
7799 EVT DstTy = Op.getValueType();
7801 if (!IsSigned && !isIntegerTypeFTOL(DstTy)) {
7802 assert(DstTy == MVT::i32 && "Unexpected FP_TO_UINT");
7806 assert(DstTy.getSimpleVT() <= MVT::i64 &&
7807 DstTy.getSimpleVT() >= MVT::i16 &&
7808 "Unknown FP_TO_INT to lower!");
7810 // These are really Legal.
7811 if (DstTy == MVT::i32 &&
7812 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
7813 return std::make_pair(SDValue(), SDValue());
7814 if (Subtarget->is64Bit() &&
7815 DstTy == MVT::i64 &&
7816 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
7817 return std::make_pair(SDValue(), SDValue());
7819 // We lower FP->int64 either into FISTP64 followed by a load from a temporary
7820 // stack slot, or into the FTOL runtime function.
7821 MachineFunction &MF = DAG.getMachineFunction();
7822 unsigned MemSize = DstTy.getSizeInBits()/8;
7823 int SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
7824 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
7827 if (!IsSigned && isIntegerTypeFTOL(DstTy))
7828 Opc = X86ISD::WIN_FTOL;
7830 switch (DstTy.getSimpleVT().SimpleTy) {
7831 default: llvm_unreachable("Invalid FP_TO_SINT to lower!");
7832 case MVT::i16: Opc = X86ISD::FP_TO_INT16_IN_MEM; break;
7833 case MVT::i32: Opc = X86ISD::FP_TO_INT32_IN_MEM; break;
7834 case MVT::i64: Opc = X86ISD::FP_TO_INT64_IN_MEM; break;
7837 SDValue Chain = DAG.getEntryNode();
7838 SDValue Value = Op.getOperand(0);
7839 EVT TheVT = Op.getOperand(0).getValueType();
7840 // FIXME This causes a redundant load/store if the SSE-class value is already
7841 // in memory, such as if it is on the callstack.
7842 if (isScalarFPTypeInSSEReg(TheVT)) {
7843 assert(DstTy == MVT::i64 && "Invalid FP_TO_SINT to lower!");
7844 Chain = DAG.getStore(Chain, DL, Value, StackSlot,
7845 MachinePointerInfo::getFixedStack(SSFI),
7847 SDVTList Tys = DAG.getVTList(Op.getOperand(0).getValueType(), MVT::Other);
7849 Chain, StackSlot, DAG.getValueType(TheVT)
7852 MachineMemOperand *MMO =
7853 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
7854 MachineMemOperand::MOLoad, MemSize, MemSize);
7855 Value = DAG.getMemIntrinsicNode(X86ISD::FLD, DL, Tys, Ops, 3,
7857 Chain = Value.getValue(1);
7858 SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
7859 StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
7862 MachineMemOperand *MMO =
7863 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
7864 MachineMemOperand::MOStore, MemSize, MemSize);
7866 if (Opc != X86ISD::WIN_FTOL) {
7867 // Build the FP_TO_INT*_IN_MEM
7868 SDValue Ops[] = { Chain, Value, StackSlot };
7869 SDValue FIST = DAG.getMemIntrinsicNode(Opc, DL, DAG.getVTList(MVT::Other),
7870 Ops, 3, DstTy, MMO);
7871 return std::make_pair(FIST, StackSlot);
7873 SDValue ftol = DAG.getNode(X86ISD::WIN_FTOL, DL,
7874 DAG.getVTList(MVT::Other, MVT::Glue),
7876 SDValue eax = DAG.getCopyFromReg(ftol, DL, X86::EAX,
7877 MVT::i32, ftol.getValue(1));
7878 SDValue edx = DAG.getCopyFromReg(eax.getValue(1), DL, X86::EDX,
7879 MVT::i32, eax.getValue(2));
7880 SDValue Ops[] = { eax, edx };
7881 SDValue pair = IsReplace
7882 ? DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops, 2)
7883 : DAG.getMergeValues(Ops, 2, DL);
7884 return std::make_pair(pair, SDValue());
7888 SDValue X86TargetLowering::LowerFP_TO_SINT(SDValue Op,
7889 SelectionDAG &DAG) const {
7890 if (Op.getValueType().isVector())
7893 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG,
7894 /*IsSigned=*/ true, /*IsReplace=*/ false);
7895 SDValue FIST = Vals.first, StackSlot = Vals.second;
7896 // If FP_TO_INTHelper failed, the node is actually supposed to be Legal.
7897 if (FIST.getNode() == 0) return Op;
7899 if (StackSlot.getNode())
7901 return DAG.getLoad(Op.getValueType(), Op.getDebugLoc(),
7902 FIST, StackSlot, MachinePointerInfo(),
7903 false, false, false, 0);
7905 // The node is the result.
7909 SDValue X86TargetLowering::LowerFP_TO_UINT(SDValue Op,
7910 SelectionDAG &DAG) const {
7911 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG,
7912 /*IsSigned=*/ false, /*IsReplace=*/ false);
7913 SDValue FIST = Vals.first, StackSlot = Vals.second;
7914 assert(FIST.getNode() && "Unexpected failure");
7916 if (StackSlot.getNode())
7918 return DAG.getLoad(Op.getValueType(), Op.getDebugLoc(),
7919 FIST, StackSlot, MachinePointerInfo(),
7920 false, false, false, 0);
7922 // The node is the result.
7926 SDValue X86TargetLowering::LowerFABS(SDValue Op,
7927 SelectionDAG &DAG) const {
7928 LLVMContext *Context = DAG.getContext();
7929 DebugLoc dl = Op.getDebugLoc();
7930 EVT VT = Op.getValueType();
7933 EltVT = VT.getVectorElementType();
7935 if (EltVT == MVT::f64) {
7936 C = ConstantVector::getSplat(2,
7937 ConstantFP::get(*Context, APFloat(APInt(64, ~(1ULL << 63)))));
7939 C = ConstantVector::getSplat(4,
7940 ConstantFP::get(*Context, APFloat(APInt(32, ~(1U << 31)))));
7942 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
7943 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
7944 MachinePointerInfo::getConstantPool(),
7945 false, false, false, 16);
7946 return DAG.getNode(X86ISD::FAND, dl, VT, Op.getOperand(0), Mask);
7949 SDValue X86TargetLowering::LowerFNEG(SDValue Op, SelectionDAG &DAG) const {
7950 LLVMContext *Context = DAG.getContext();
7951 DebugLoc dl = Op.getDebugLoc();
7952 EVT VT = Op.getValueType();
7954 unsigned NumElts = VT == MVT::f64 ? 2 : 4;
7955 if (VT.isVector()) {
7956 EltVT = VT.getVectorElementType();
7957 NumElts = VT.getVectorNumElements();
7960 if (EltVT == MVT::f64)
7961 C = ConstantFP::get(*Context, APFloat(APInt(64, 1ULL << 63)));
7963 C = ConstantFP::get(*Context, APFloat(APInt(32, 1U << 31)));
7964 C = ConstantVector::getSplat(NumElts, C);
7965 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
7966 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
7967 MachinePointerInfo::getConstantPool(),
7968 false, false, false, 16);
7969 if (VT.isVector()) {
7970 MVT XORVT = VT.getSizeInBits() == 128 ? MVT::v2i64 : MVT::v4i64;
7971 return DAG.getNode(ISD::BITCAST, dl, VT,
7972 DAG.getNode(ISD::XOR, dl, XORVT,
7973 DAG.getNode(ISD::BITCAST, dl, XORVT,
7975 DAG.getNode(ISD::BITCAST, dl, XORVT, Mask)));
7977 return DAG.getNode(X86ISD::FXOR, dl, VT, Op.getOperand(0), Mask);
7981 SDValue X86TargetLowering::LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const {
7982 LLVMContext *Context = DAG.getContext();
7983 SDValue Op0 = Op.getOperand(0);
7984 SDValue Op1 = Op.getOperand(1);
7985 DebugLoc dl = Op.getDebugLoc();
7986 EVT VT = Op.getValueType();
7987 EVT SrcVT = Op1.getValueType();
7989 // If second operand is smaller, extend it first.
7990 if (SrcVT.bitsLT(VT)) {
7991 Op1 = DAG.getNode(ISD::FP_EXTEND, dl, VT, Op1);
7994 // And if it is bigger, shrink it first.
7995 if (SrcVT.bitsGT(VT)) {
7996 Op1 = DAG.getNode(ISD::FP_ROUND, dl, VT, Op1, DAG.getIntPtrConstant(1));
8000 // At this point the operands and the result should have the same
8001 // type, and that won't be f80 since that is not custom lowered.
8003 // First get the sign bit of second operand.
8004 SmallVector<Constant*,4> CV;
8005 if (SrcVT == MVT::f64) {
8006 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, 1ULL << 63))));
8007 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, 0))));
8009 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 1U << 31))));
8010 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
8011 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
8012 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
8014 Constant *C = ConstantVector::get(CV);
8015 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
8016 SDValue Mask1 = DAG.getLoad(SrcVT, dl, DAG.getEntryNode(), CPIdx,
8017 MachinePointerInfo::getConstantPool(),
8018 false, false, false, 16);
8019 SDValue SignBit = DAG.getNode(X86ISD::FAND, dl, SrcVT, Op1, Mask1);
8021 // Shift sign bit right or left if the two operands have different types.
8022 if (SrcVT.bitsGT(VT)) {
8023 // Op0 is MVT::f32, Op1 is MVT::f64.
8024 SignBit = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f64, SignBit);
8025 SignBit = DAG.getNode(X86ISD::FSRL, dl, MVT::v2f64, SignBit,
8026 DAG.getConstant(32, MVT::i32));
8027 SignBit = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, SignBit);
8028 SignBit = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f32, SignBit,
8029 DAG.getIntPtrConstant(0));
8032 // Clear first operand sign bit.
8034 if (VT == MVT::f64) {
8035 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, ~(1ULL << 63)))));
8036 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, 0))));
8038 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, ~(1U << 31)))));
8039 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
8040 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
8041 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
8043 C = ConstantVector::get(CV);
8044 CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
8045 SDValue Mask2 = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
8046 MachinePointerInfo::getConstantPool(),
8047 false, false, false, 16);
8048 SDValue Val = DAG.getNode(X86ISD::FAND, dl, VT, Op0, Mask2);
8050 // Or the value with the sign bit.
8051 return DAG.getNode(X86ISD::FOR, dl, VT, Val, SignBit);
8054 SDValue X86TargetLowering::LowerFGETSIGN(SDValue Op, SelectionDAG &DAG) const {
8055 SDValue N0 = Op.getOperand(0);
8056 DebugLoc dl = Op.getDebugLoc();
8057 EVT VT = Op.getValueType();
8059 // Lower ISD::FGETSIGN to (AND (X86ISD::FGETSIGNx86 ...) 1).
8060 SDValue xFGETSIGN = DAG.getNode(X86ISD::FGETSIGNx86, dl, VT, N0,
8061 DAG.getConstant(1, VT));
8062 return DAG.getNode(ISD::AND, dl, VT, xFGETSIGN, DAG.getConstant(1, VT));
8065 /// Emit nodes that will be selected as "test Op0,Op0", or something
8067 SDValue X86TargetLowering::EmitTest(SDValue Op, unsigned X86CC,
8068 SelectionDAG &DAG) const {
8069 DebugLoc dl = Op.getDebugLoc();
8071 // CF and OF aren't always set the way we want. Determine which
8072 // of these we need.
8073 bool NeedCF = false;
8074 bool NeedOF = false;
8077 case X86::COND_A: case X86::COND_AE:
8078 case X86::COND_B: case X86::COND_BE:
8081 case X86::COND_G: case X86::COND_GE:
8082 case X86::COND_L: case X86::COND_LE:
8083 case X86::COND_O: case X86::COND_NO:
8088 // See if we can use the EFLAGS value from the operand instead of
8089 // doing a separate TEST. TEST always sets OF and CF to 0, so unless
8090 // we prove that the arithmetic won't overflow, we can't use OF or CF.
8091 if (Op.getResNo() != 0 || NeedOF || NeedCF)
8092 // Emit a CMP with 0, which is the TEST pattern.
8093 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
8094 DAG.getConstant(0, Op.getValueType()));
8096 unsigned Opcode = 0;
8097 unsigned NumOperands = 0;
8098 switch (Op.getNode()->getOpcode()) {
8100 // Due to an isel shortcoming, be conservative if this add is likely to be
8101 // selected as part of a load-modify-store instruction. When the root node
8102 // in a match is a store, isel doesn't know how to remap non-chain non-flag
8103 // uses of other nodes in the match, such as the ADD in this case. This
8104 // leads to the ADD being left around and reselected, with the result being
8105 // two adds in the output. Alas, even if none our users are stores, that
8106 // doesn't prove we're O.K. Ergo, if we have any parents that aren't
8107 // CopyToReg or SETCC, eschew INC/DEC. A better fix seems to require
8108 // climbing the DAG back to the root, and it doesn't seem to be worth the
8110 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
8111 UE = Op.getNode()->use_end(); UI != UE; ++UI)
8112 if (UI->getOpcode() != ISD::CopyToReg &&
8113 UI->getOpcode() != ISD::SETCC &&
8114 UI->getOpcode() != ISD::STORE)
8117 if (ConstantSDNode *C =
8118 dyn_cast<ConstantSDNode>(Op.getNode()->getOperand(1))) {
8119 // An add of one will be selected as an INC.
8120 if (C->getAPIntValue() == 1) {
8121 Opcode = X86ISD::INC;
8126 // An add of negative one (subtract of one) will be selected as a DEC.
8127 if (C->getAPIntValue().isAllOnesValue()) {
8128 Opcode = X86ISD::DEC;
8134 // Otherwise use a regular EFLAGS-setting add.
8135 Opcode = X86ISD::ADD;
8139 // If the primary and result isn't used, don't bother using X86ISD::AND,
8140 // because a TEST instruction will be better.
8141 bool NonFlagUse = false;
8142 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
8143 UE = Op.getNode()->use_end(); UI != UE; ++UI) {
8145 unsigned UOpNo = UI.getOperandNo();
8146 if (User->getOpcode() == ISD::TRUNCATE && User->hasOneUse()) {
8147 // Look pass truncate.
8148 UOpNo = User->use_begin().getOperandNo();
8149 User = *User->use_begin();
8152 if (User->getOpcode() != ISD::BRCOND &&
8153 User->getOpcode() != ISD::SETCC &&
8154 (User->getOpcode() != ISD::SELECT || UOpNo != 0)) {
8167 // Due to the ISEL shortcoming noted above, be conservative if this op is
8168 // likely to be selected as part of a load-modify-store instruction.
8169 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
8170 UE = Op.getNode()->use_end(); UI != UE; ++UI)
8171 if (UI->getOpcode() == ISD::STORE)
8174 // Otherwise use a regular EFLAGS-setting instruction.
8175 switch (Op.getNode()->getOpcode()) {
8176 default: llvm_unreachable("unexpected operator!");
8177 case ISD::SUB: Opcode = X86ISD::SUB; break;
8178 case ISD::OR: Opcode = X86ISD::OR; break;
8179 case ISD::XOR: Opcode = X86ISD::XOR; break;
8180 case ISD::AND: Opcode = X86ISD::AND; break;
8192 return SDValue(Op.getNode(), 1);
8199 // Emit a CMP with 0, which is the TEST pattern.
8200 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
8201 DAG.getConstant(0, Op.getValueType()));
8203 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
8204 SmallVector<SDValue, 4> Ops;
8205 for (unsigned i = 0; i != NumOperands; ++i)
8206 Ops.push_back(Op.getOperand(i));
8208 SDValue New = DAG.getNode(Opcode, dl, VTs, &Ops[0], NumOperands);
8209 DAG.ReplaceAllUsesWith(Op, New);
8210 return SDValue(New.getNode(), 1);
8213 /// Emit nodes that will be selected as "cmp Op0,Op1", or something
8215 SDValue X86TargetLowering::EmitCmp(SDValue Op0, SDValue Op1, unsigned X86CC,
8216 SelectionDAG &DAG) const {
8217 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op1))
8218 if (C->getAPIntValue() == 0)
8219 return EmitTest(Op0, X86CC, DAG);
8221 DebugLoc dl = Op0.getDebugLoc();
8222 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op0, Op1);
8225 /// LowerToBT - Result of 'and' is compared against zero. Turn it into a BT node
8226 /// if it's possible.
8227 SDValue X86TargetLowering::LowerToBT(SDValue And, ISD::CondCode CC,
8228 DebugLoc dl, SelectionDAG &DAG) const {
8229 SDValue Op0 = And.getOperand(0);
8230 SDValue Op1 = And.getOperand(1);
8231 if (Op0.getOpcode() == ISD::TRUNCATE)
8232 Op0 = Op0.getOperand(0);
8233 if (Op1.getOpcode() == ISD::TRUNCATE)
8234 Op1 = Op1.getOperand(0);
8237 if (Op1.getOpcode() == ISD::SHL)
8238 std::swap(Op0, Op1);
8239 if (Op0.getOpcode() == ISD::SHL) {
8240 if (ConstantSDNode *And00C = dyn_cast<ConstantSDNode>(Op0.getOperand(0)))
8241 if (And00C->getZExtValue() == 1) {
8242 // If we looked past a truncate, check that it's only truncating away
8244 unsigned BitWidth = Op0.getValueSizeInBits();
8245 unsigned AndBitWidth = And.getValueSizeInBits();
8246 if (BitWidth > AndBitWidth) {
8248 DAG.ComputeMaskedBits(Op0, Zeros, Ones);
8249 if (Zeros.countLeadingOnes() < BitWidth - AndBitWidth)
8253 RHS = Op0.getOperand(1);
8255 } else if (Op1.getOpcode() == ISD::Constant) {
8256 ConstantSDNode *AndRHS = cast<ConstantSDNode>(Op1);
8257 uint64_t AndRHSVal = AndRHS->getZExtValue();
8258 SDValue AndLHS = Op0;
8260 if (AndRHSVal == 1 && AndLHS.getOpcode() == ISD::SRL) {
8261 LHS = AndLHS.getOperand(0);
8262 RHS = AndLHS.getOperand(1);
8265 // Use BT if the immediate can't be encoded in a TEST instruction.
8266 if (!isUInt<32>(AndRHSVal) && isPowerOf2_64(AndRHSVal)) {
8268 RHS = DAG.getConstant(Log2_64_Ceil(AndRHSVal), LHS.getValueType());
8272 if (LHS.getNode()) {
8273 // If LHS is i8, promote it to i32 with any_extend. There is no i8 BT
8274 // instruction. Since the shift amount is in-range-or-undefined, we know
8275 // that doing a bittest on the i32 value is ok. We extend to i32 because
8276 // the encoding for the i16 version is larger than the i32 version.
8277 // Also promote i16 to i32 for performance / code size reason.
8278 if (LHS.getValueType() == MVT::i8 ||
8279 LHS.getValueType() == MVT::i16)
8280 LHS = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, LHS);
8282 // If the operand types disagree, extend the shift amount to match. Since
8283 // BT ignores high bits (like shifts) we can use anyextend.
8284 if (LHS.getValueType() != RHS.getValueType())
8285 RHS = DAG.getNode(ISD::ANY_EXTEND, dl, LHS.getValueType(), RHS);
8287 SDValue BT = DAG.getNode(X86ISD::BT, dl, MVT::i32, LHS, RHS);
8288 unsigned Cond = CC == ISD::SETEQ ? X86::COND_AE : X86::COND_B;
8289 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
8290 DAG.getConstant(Cond, MVT::i8), BT);
8296 SDValue X86TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
8298 if (Op.getValueType().isVector()) return LowerVSETCC(Op, DAG);
8300 assert(Op.getValueType() == MVT::i8 && "SetCC type must be 8-bit integer");
8301 SDValue Op0 = Op.getOperand(0);
8302 SDValue Op1 = Op.getOperand(1);
8303 DebugLoc dl = Op.getDebugLoc();
8304 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
8306 // Optimize to BT if possible.
8307 // Lower (X & (1 << N)) == 0 to BT(X, N).
8308 // Lower ((X >>u N) & 1) != 0 to BT(X, N).
8309 // Lower ((X >>s N) & 1) != 0 to BT(X, N).
8310 if (Op0.getOpcode() == ISD::AND && Op0.hasOneUse() &&
8311 Op1.getOpcode() == ISD::Constant &&
8312 cast<ConstantSDNode>(Op1)->isNullValue() &&
8313 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
8314 SDValue NewSetCC = LowerToBT(Op0, CC, dl, DAG);
8315 if (NewSetCC.getNode())
8319 // Look for X == 0, X == 1, X != 0, or X != 1. We can simplify some forms of
8321 if (Op1.getOpcode() == ISD::Constant &&
8322 (cast<ConstantSDNode>(Op1)->getZExtValue() == 1 ||
8323 cast<ConstantSDNode>(Op1)->isNullValue()) &&
8324 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
8326 // If the input is a setcc, then reuse the input setcc or use a new one with
8327 // the inverted condition.
8328 if (Op0.getOpcode() == X86ISD::SETCC) {
8329 X86::CondCode CCode = (X86::CondCode)Op0.getConstantOperandVal(0);
8330 bool Invert = (CC == ISD::SETNE) ^
8331 cast<ConstantSDNode>(Op1)->isNullValue();
8332 if (!Invert) return Op0;
8334 CCode = X86::GetOppositeBranchCondition(CCode);
8335 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
8336 DAG.getConstant(CCode, MVT::i8), Op0.getOperand(1));
8340 bool isFP = Op1.getValueType().isFloatingPoint();
8341 unsigned X86CC = TranslateX86CC(CC, isFP, Op0, Op1, DAG);
8342 if (X86CC == X86::COND_INVALID)
8345 SDValue EFLAGS = EmitCmp(Op0, Op1, X86CC, DAG);
8346 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
8347 DAG.getConstant(X86CC, MVT::i8), EFLAGS);
8350 // Lower256IntVSETCC - Break a VSETCC 256-bit integer VSETCC into two new 128
8351 // ones, and then concatenate the result back.
8352 static SDValue Lower256IntVSETCC(SDValue Op, SelectionDAG &DAG) {
8353 EVT VT = Op.getValueType();
8355 assert(VT.getSizeInBits() == 256 && Op.getOpcode() == ISD::SETCC &&
8356 "Unsupported value type for operation");
8358 int NumElems = VT.getVectorNumElements();
8359 DebugLoc dl = Op.getDebugLoc();
8360 SDValue CC = Op.getOperand(2);
8361 SDValue Idx0 = DAG.getConstant(0, MVT::i32);
8362 SDValue Idx1 = DAG.getConstant(NumElems/2, MVT::i32);
8364 // Extract the LHS vectors
8365 SDValue LHS = Op.getOperand(0);
8366 SDValue LHS1 = Extract128BitVector(LHS, Idx0, DAG, dl);
8367 SDValue LHS2 = Extract128BitVector(LHS, Idx1, DAG, dl);
8369 // Extract the RHS vectors
8370 SDValue RHS = Op.getOperand(1);
8371 SDValue RHS1 = Extract128BitVector(RHS, Idx0, DAG, dl);
8372 SDValue RHS2 = Extract128BitVector(RHS, Idx1, DAG, dl);
8374 // Issue the operation on the smaller types and concatenate the result back
8375 MVT EltVT = VT.getVectorElementType().getSimpleVT();
8376 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
8377 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
8378 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1, CC),
8379 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2, CC));
8383 SDValue X86TargetLowering::LowerVSETCC(SDValue Op, SelectionDAG &DAG) const {
8385 SDValue Op0 = Op.getOperand(0);
8386 SDValue Op1 = Op.getOperand(1);
8387 SDValue CC = Op.getOperand(2);
8388 EVT VT = Op.getValueType();
8389 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
8390 bool isFP = Op.getOperand(1).getValueType().isFloatingPoint();
8391 DebugLoc dl = Op.getDebugLoc();
8395 EVT EltVT = Op0.getValueType().getVectorElementType();
8396 assert(EltVT == MVT::f32 || EltVT == MVT::f64); (void)EltVT;
8400 // SSE Condition code mapping:
8409 switch (SetCCOpcode) {
8412 case ISD::SETEQ: SSECC = 0; break;
8414 case ISD::SETGT: Swap = true; // Fallthrough
8416 case ISD::SETOLT: SSECC = 1; break;
8418 case ISD::SETGE: Swap = true; // Fallthrough
8420 case ISD::SETOLE: SSECC = 2; break;
8421 case ISD::SETUO: SSECC = 3; break;
8423 case ISD::SETNE: SSECC = 4; break;
8424 case ISD::SETULE: Swap = true;
8425 case ISD::SETUGE: SSECC = 5; break;
8426 case ISD::SETULT: Swap = true;
8427 case ISD::SETUGT: SSECC = 6; break;
8428 case ISD::SETO: SSECC = 7; break;
8431 std::swap(Op0, Op1);
8433 // In the two special cases we can't handle, emit two comparisons.
8435 if (SetCCOpcode == ISD::SETUEQ) {
8437 UNORD = DAG.getNode(X86ISD::CMPP, dl, VT, Op0, Op1,
8438 DAG.getConstant(3, MVT::i8));
8439 EQ = DAG.getNode(X86ISD::CMPP, dl, VT, Op0, Op1,
8440 DAG.getConstant(0, MVT::i8));
8441 return DAG.getNode(ISD::OR, dl, VT, UNORD, EQ);
8442 } else if (SetCCOpcode == ISD::SETONE) {
8444 ORD = DAG.getNode(X86ISD::CMPP, dl, VT, Op0, Op1,
8445 DAG.getConstant(7, MVT::i8));
8446 NEQ = DAG.getNode(X86ISD::CMPP, dl, VT, Op0, Op1,
8447 DAG.getConstant(4, MVT::i8));
8448 return DAG.getNode(ISD::AND, dl, VT, ORD, NEQ);
8450 llvm_unreachable("Illegal FP comparison");
8452 // Handle all other FP comparisons here.
8453 return DAG.getNode(X86ISD::CMPP, dl, VT, Op0, Op1,
8454 DAG.getConstant(SSECC, MVT::i8));
8457 // Break 256-bit integer vector compare into smaller ones.
8458 if (VT.getSizeInBits() == 256 && !Subtarget->hasAVX2())
8459 return Lower256IntVSETCC(Op, DAG);
8461 // We are handling one of the integer comparisons here. Since SSE only has
8462 // GT and EQ comparisons for integer, swapping operands and multiple
8463 // operations may be required for some comparisons.
8465 bool Swap = false, Invert = false, FlipSigns = false;
8467 switch (SetCCOpcode) {
8469 case ISD::SETNE: Invert = true;
8470 case ISD::SETEQ: Opc = X86ISD::PCMPEQ; break;
8471 case ISD::SETLT: Swap = true;
8472 case ISD::SETGT: Opc = X86ISD::PCMPGT; break;
8473 case ISD::SETGE: Swap = true;
8474 case ISD::SETLE: Opc = X86ISD::PCMPGT; Invert = true; break;
8475 case ISD::SETULT: Swap = true;
8476 case ISD::SETUGT: Opc = X86ISD::PCMPGT; FlipSigns = true; break;
8477 case ISD::SETUGE: Swap = true;
8478 case ISD::SETULE: Opc = X86ISD::PCMPGT; FlipSigns = true; Invert = true; break;
8481 std::swap(Op0, Op1);
8483 // Check that the operation in question is available (most are plain SSE2,
8484 // but PCMPGTQ and PCMPEQQ have different requirements).
8485 if (Opc == X86ISD::PCMPGT && VT == MVT::v2i64 && !Subtarget->hasSSE42())
8487 if (Opc == X86ISD::PCMPEQ && VT == MVT::v2i64 && !Subtarget->hasSSE41())
8490 // Since SSE has no unsigned integer comparisons, we need to flip the sign
8491 // bits of the inputs before performing those operations.
8493 EVT EltVT = VT.getVectorElementType();
8494 SDValue SignBit = DAG.getConstant(APInt::getSignBit(EltVT.getSizeInBits()),
8496 std::vector<SDValue> SignBits(VT.getVectorNumElements(), SignBit);
8497 SDValue SignVec = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &SignBits[0],
8499 Op0 = DAG.getNode(ISD::XOR, dl, VT, Op0, SignVec);
8500 Op1 = DAG.getNode(ISD::XOR, dl, VT, Op1, SignVec);
8503 SDValue Result = DAG.getNode(Opc, dl, VT, Op0, Op1);
8505 // If the logical-not of the result is required, perform that now.
8507 Result = DAG.getNOT(dl, Result, VT);
8512 // isX86LogicalCmp - Return true if opcode is a X86 logical comparison.
8513 static bool isX86LogicalCmp(SDValue Op) {
8514 unsigned Opc = Op.getNode()->getOpcode();
8515 if (Opc == X86ISD::CMP || Opc == X86ISD::COMI || Opc == X86ISD::UCOMI)
8517 if (Op.getResNo() == 1 &&
8518 (Opc == X86ISD::ADD ||
8519 Opc == X86ISD::SUB ||
8520 Opc == X86ISD::ADC ||
8521 Opc == X86ISD::SBB ||
8522 Opc == X86ISD::SMUL ||
8523 Opc == X86ISD::UMUL ||
8524 Opc == X86ISD::INC ||
8525 Opc == X86ISD::DEC ||
8526 Opc == X86ISD::OR ||
8527 Opc == X86ISD::XOR ||
8528 Opc == X86ISD::AND))
8531 if (Op.getResNo() == 2 && Opc == X86ISD::UMUL)
8537 static bool isZero(SDValue V) {
8538 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V);
8539 return C && C->isNullValue();
8542 static bool isAllOnes(SDValue V) {
8543 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V);
8544 return C && C->isAllOnesValue();
8547 SDValue X86TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {
8548 bool addTest = true;
8549 SDValue Cond = Op.getOperand(0);
8550 SDValue Op1 = Op.getOperand(1);
8551 SDValue Op2 = Op.getOperand(2);
8552 DebugLoc DL = Op.getDebugLoc();
8555 if (Cond.getOpcode() == ISD::SETCC) {
8556 SDValue NewCond = LowerSETCC(Cond, DAG);
8557 if (NewCond.getNode())
8561 // (select (x == 0), -1, y) -> (sign_bit (x - 1)) | y
8562 // (select (x == 0), y, -1) -> ~(sign_bit (x - 1)) | y
8563 // (select (x != 0), y, -1) -> (sign_bit (x - 1)) | y
8564 // (select (x != 0), -1, y) -> ~(sign_bit (x - 1)) | y
8565 if (Cond.getOpcode() == X86ISD::SETCC &&
8566 Cond.getOperand(1).getOpcode() == X86ISD::CMP &&
8567 isZero(Cond.getOperand(1).getOperand(1))) {
8568 SDValue Cmp = Cond.getOperand(1);
8570 unsigned CondCode =cast<ConstantSDNode>(Cond.getOperand(0))->getZExtValue();
8572 if ((isAllOnes(Op1) || isAllOnes(Op2)) &&
8573 (CondCode == X86::COND_E || CondCode == X86::COND_NE)) {
8574 SDValue Y = isAllOnes(Op2) ? Op1 : Op2;
8576 SDValue CmpOp0 = Cmp.getOperand(0);
8577 Cmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32,
8578 CmpOp0, DAG.getConstant(1, CmpOp0.getValueType()));
8580 SDValue Res = // Res = 0 or -1.
8581 DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
8582 DAG.getConstant(X86::COND_B, MVT::i8), Cmp);
8584 if (isAllOnes(Op1) != (CondCode == X86::COND_E))
8585 Res = DAG.getNOT(DL, Res, Res.getValueType());
8587 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(Op2);
8588 if (N2C == 0 || !N2C->isNullValue())
8589 Res = DAG.getNode(ISD::OR, DL, Res.getValueType(), Res, Y);
8594 // Look past (and (setcc_carry (cmp ...)), 1).
8595 if (Cond.getOpcode() == ISD::AND &&
8596 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
8597 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
8598 if (C && C->getAPIntValue() == 1)
8599 Cond = Cond.getOperand(0);
8602 // If condition flag is set by a X86ISD::CMP, then use it as the condition
8603 // setting operand in place of the X86ISD::SETCC.
8604 unsigned CondOpcode = Cond.getOpcode();
8605 if (CondOpcode == X86ISD::SETCC ||
8606 CondOpcode == X86ISD::SETCC_CARRY) {
8607 CC = Cond.getOperand(0);
8609 SDValue Cmp = Cond.getOperand(1);
8610 unsigned Opc = Cmp.getOpcode();
8611 EVT VT = Op.getValueType();
8613 bool IllegalFPCMov = false;
8614 if (VT.isFloatingPoint() && !VT.isVector() &&
8615 !isScalarFPTypeInSSEReg(VT)) // FPStack?
8616 IllegalFPCMov = !hasFPCMov(cast<ConstantSDNode>(CC)->getSExtValue());
8618 if ((isX86LogicalCmp(Cmp) && !IllegalFPCMov) ||
8619 Opc == X86ISD::BT) { // FIXME
8623 } else if (CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO ||
8624 CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO ||
8625 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) &&
8626 Cond.getOperand(0).getValueType() != MVT::i8)) {
8627 SDValue LHS = Cond.getOperand(0);
8628 SDValue RHS = Cond.getOperand(1);
8632 switch (CondOpcode) {
8633 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break;
8634 case ISD::SADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break;
8635 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break;
8636 case ISD::SSUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break;
8637 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break;
8638 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break;
8639 default: llvm_unreachable("unexpected overflowing operator");
8641 if (CondOpcode == ISD::UMULO)
8642 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(),
8645 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
8647 SDValue X86Op = DAG.getNode(X86Opcode, DL, VTs, LHS, RHS);
8649 if (CondOpcode == ISD::UMULO)
8650 Cond = X86Op.getValue(2);
8652 Cond = X86Op.getValue(1);
8654 CC = DAG.getConstant(X86Cond, MVT::i8);
8659 // Look pass the truncate.
8660 if (Cond.getOpcode() == ISD::TRUNCATE)
8661 Cond = Cond.getOperand(0);
8663 // We know the result of AND is compared against zero. Try to match
8665 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
8666 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, DL, DAG);
8667 if (NewSetCC.getNode()) {
8668 CC = NewSetCC.getOperand(0);
8669 Cond = NewSetCC.getOperand(1);
8676 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
8677 Cond = EmitTest(Cond, X86::COND_NE, DAG);
8680 // a < b ? -1 : 0 -> RES = ~setcc_carry
8681 // a < b ? 0 : -1 -> RES = setcc_carry
8682 // a >= b ? -1 : 0 -> RES = setcc_carry
8683 // a >= b ? 0 : -1 -> RES = ~setcc_carry
8684 if (Cond.getOpcode() == X86ISD::CMP) {
8685 unsigned CondCode = cast<ConstantSDNode>(CC)->getZExtValue();
8687 if ((CondCode == X86::COND_AE || CondCode == X86::COND_B) &&
8688 (isAllOnes(Op1) || isAllOnes(Op2)) && (isZero(Op1) || isZero(Op2))) {
8689 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
8690 DAG.getConstant(X86::COND_B, MVT::i8), Cond);
8691 if (isAllOnes(Op1) != (CondCode == X86::COND_B))
8692 return DAG.getNOT(DL, Res, Res.getValueType());
8697 // X86ISD::CMOV means set the result (which is operand 1) to the RHS if
8698 // condition is true.
8699 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue);
8700 SDValue Ops[] = { Op2, Op1, CC, Cond };
8701 return DAG.getNode(X86ISD::CMOV, DL, VTs, Ops, array_lengthof(Ops));
8704 // isAndOrOfSingleUseSetCCs - Return true if node is an ISD::AND or
8705 // ISD::OR of two X86ISD::SETCC nodes each of which has no other use apart
8706 // from the AND / OR.
8707 static bool isAndOrOfSetCCs(SDValue Op, unsigned &Opc) {
8708 Opc = Op.getOpcode();
8709 if (Opc != ISD::OR && Opc != ISD::AND)
8711 return (Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
8712 Op.getOperand(0).hasOneUse() &&
8713 Op.getOperand(1).getOpcode() == X86ISD::SETCC &&
8714 Op.getOperand(1).hasOneUse());
8717 // isXor1OfSetCC - Return true if node is an ISD::XOR of a X86ISD::SETCC and
8718 // 1 and that the SETCC node has a single use.
8719 static bool isXor1OfSetCC(SDValue Op) {
8720 if (Op.getOpcode() != ISD::XOR)
8722 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
8723 if (N1C && N1C->getAPIntValue() == 1) {
8724 return Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
8725 Op.getOperand(0).hasOneUse();
8730 SDValue X86TargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) const {
8731 bool addTest = true;
8732 SDValue Chain = Op.getOperand(0);
8733 SDValue Cond = Op.getOperand(1);
8734 SDValue Dest = Op.getOperand(2);
8735 DebugLoc dl = Op.getDebugLoc();
8737 bool Inverted = false;
8739 if (Cond.getOpcode() == ISD::SETCC) {
8740 // Check for setcc([su]{add,sub,mul}o == 0).
8741 if (cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETEQ &&
8742 isa<ConstantSDNode>(Cond.getOperand(1)) &&
8743 cast<ConstantSDNode>(Cond.getOperand(1))->isNullValue() &&
8744 Cond.getOperand(0).getResNo() == 1 &&
8745 (Cond.getOperand(0).getOpcode() == ISD::SADDO ||
8746 Cond.getOperand(0).getOpcode() == ISD::UADDO ||
8747 Cond.getOperand(0).getOpcode() == ISD::SSUBO ||
8748 Cond.getOperand(0).getOpcode() == ISD::USUBO ||
8749 Cond.getOperand(0).getOpcode() == ISD::SMULO ||
8750 Cond.getOperand(0).getOpcode() == ISD::UMULO)) {
8752 Cond = Cond.getOperand(0);
8754 SDValue NewCond = LowerSETCC(Cond, DAG);
8755 if (NewCond.getNode())
8760 // FIXME: LowerXALUO doesn't handle these!!
8761 else if (Cond.getOpcode() == X86ISD::ADD ||
8762 Cond.getOpcode() == X86ISD::SUB ||
8763 Cond.getOpcode() == X86ISD::SMUL ||
8764 Cond.getOpcode() == X86ISD::UMUL)
8765 Cond = LowerXALUO(Cond, DAG);
8768 // Look pass (and (setcc_carry (cmp ...)), 1).
8769 if (Cond.getOpcode() == ISD::AND &&
8770 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
8771 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
8772 if (C && C->getAPIntValue() == 1)
8773 Cond = Cond.getOperand(0);
8776 // If condition flag is set by a X86ISD::CMP, then use it as the condition
8777 // setting operand in place of the X86ISD::SETCC.
8778 unsigned CondOpcode = Cond.getOpcode();
8779 if (CondOpcode == X86ISD::SETCC ||
8780 CondOpcode == X86ISD::SETCC_CARRY) {
8781 CC = Cond.getOperand(0);
8783 SDValue Cmp = Cond.getOperand(1);
8784 unsigned Opc = Cmp.getOpcode();
8785 // FIXME: WHY THE SPECIAL CASING OF LogicalCmp??
8786 if (isX86LogicalCmp(Cmp) || Opc == X86ISD::BT) {
8790 switch (cast<ConstantSDNode>(CC)->getZExtValue()) {
8794 // These can only come from an arithmetic instruction with overflow,
8795 // e.g. SADDO, UADDO.
8796 Cond = Cond.getNode()->getOperand(1);
8802 CondOpcode = Cond.getOpcode();
8803 if (CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO ||
8804 CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO ||
8805 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) &&
8806 Cond.getOperand(0).getValueType() != MVT::i8)) {
8807 SDValue LHS = Cond.getOperand(0);
8808 SDValue RHS = Cond.getOperand(1);
8812 switch (CondOpcode) {
8813 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break;
8814 case ISD::SADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break;
8815 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break;
8816 case ISD::SSUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break;
8817 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break;
8818 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break;
8819 default: llvm_unreachable("unexpected overflowing operator");
8822 X86Cond = X86::GetOppositeBranchCondition((X86::CondCode)X86Cond);
8823 if (CondOpcode == ISD::UMULO)
8824 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(),
8827 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
8829 SDValue X86Op = DAG.getNode(X86Opcode, dl, VTs, LHS, RHS);
8831 if (CondOpcode == ISD::UMULO)
8832 Cond = X86Op.getValue(2);
8834 Cond = X86Op.getValue(1);
8836 CC = DAG.getConstant(X86Cond, MVT::i8);
8840 if (Cond.hasOneUse() && isAndOrOfSetCCs(Cond, CondOpc)) {
8841 SDValue Cmp = Cond.getOperand(0).getOperand(1);
8842 if (CondOpc == ISD::OR) {
8843 // Also, recognize the pattern generated by an FCMP_UNE. We can emit
8844 // two branches instead of an explicit OR instruction with a
8846 if (Cmp == Cond.getOperand(1).getOperand(1) &&
8847 isX86LogicalCmp(Cmp)) {
8848 CC = Cond.getOperand(0).getOperand(0);
8849 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
8850 Chain, Dest, CC, Cmp);
8851 CC = Cond.getOperand(1).getOperand(0);
8855 } else { // ISD::AND
8856 // Also, recognize the pattern generated by an FCMP_OEQ. We can emit
8857 // two branches instead of an explicit AND instruction with a
8858 // separate test. However, we only do this if this block doesn't
8859 // have a fall-through edge, because this requires an explicit
8860 // jmp when the condition is false.
8861 if (Cmp == Cond.getOperand(1).getOperand(1) &&
8862 isX86LogicalCmp(Cmp) &&
8863 Op.getNode()->hasOneUse()) {
8864 X86::CondCode CCode =
8865 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
8866 CCode = X86::GetOppositeBranchCondition(CCode);
8867 CC = DAG.getConstant(CCode, MVT::i8);
8868 SDNode *User = *Op.getNode()->use_begin();
8869 // Look for an unconditional branch following this conditional branch.
8870 // We need this because we need to reverse the successors in order
8871 // to implement FCMP_OEQ.
8872 if (User->getOpcode() == ISD::BR) {
8873 SDValue FalseBB = User->getOperand(1);
8875 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
8876 assert(NewBR == User);
8880 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
8881 Chain, Dest, CC, Cmp);
8882 X86::CondCode CCode =
8883 (X86::CondCode)Cond.getOperand(1).getConstantOperandVal(0);
8884 CCode = X86::GetOppositeBranchCondition(CCode);
8885 CC = DAG.getConstant(CCode, MVT::i8);
8891 } else if (Cond.hasOneUse() && isXor1OfSetCC(Cond)) {
8892 // Recognize for xorb (setcc), 1 patterns. The xor inverts the condition.
8893 // It should be transformed during dag combiner except when the condition
8894 // is set by a arithmetics with overflow node.
8895 X86::CondCode CCode =
8896 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
8897 CCode = X86::GetOppositeBranchCondition(CCode);
8898 CC = DAG.getConstant(CCode, MVT::i8);
8899 Cond = Cond.getOperand(0).getOperand(1);
8901 } else if (Cond.getOpcode() == ISD::SETCC &&
8902 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETOEQ) {
8903 // For FCMP_OEQ, we can emit
8904 // two branches instead of an explicit AND instruction with a
8905 // separate test. However, we only do this if this block doesn't
8906 // have a fall-through edge, because this requires an explicit
8907 // jmp when the condition is false.
8908 if (Op.getNode()->hasOneUse()) {
8909 SDNode *User = *Op.getNode()->use_begin();
8910 // Look for an unconditional branch following this conditional branch.
8911 // We need this because we need to reverse the successors in order
8912 // to implement FCMP_OEQ.
8913 if (User->getOpcode() == ISD::BR) {
8914 SDValue FalseBB = User->getOperand(1);
8916 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
8917 assert(NewBR == User);
8921 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
8922 Cond.getOperand(0), Cond.getOperand(1));
8923 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
8924 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
8925 Chain, Dest, CC, Cmp);
8926 CC = DAG.getConstant(X86::COND_P, MVT::i8);
8931 } else if (Cond.getOpcode() == ISD::SETCC &&
8932 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETUNE) {
8933 // For FCMP_UNE, we can emit
8934 // two branches instead of an explicit AND instruction with a
8935 // separate test. However, we only do this if this block doesn't
8936 // have a fall-through edge, because this requires an explicit
8937 // jmp when the condition is false.
8938 if (Op.getNode()->hasOneUse()) {
8939 SDNode *User = *Op.getNode()->use_begin();
8940 // Look for an unconditional branch following this conditional branch.
8941 // We need this because we need to reverse the successors in order
8942 // to implement FCMP_UNE.
8943 if (User->getOpcode() == ISD::BR) {
8944 SDValue FalseBB = User->getOperand(1);
8946 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
8947 assert(NewBR == User);
8950 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
8951 Cond.getOperand(0), Cond.getOperand(1));
8952 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
8953 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
8954 Chain, Dest, CC, Cmp);
8955 CC = DAG.getConstant(X86::COND_NP, MVT::i8);
8965 // Look pass the truncate.
8966 if (Cond.getOpcode() == ISD::TRUNCATE)
8967 Cond = Cond.getOperand(0);
8969 // We know the result of AND is compared against zero. Try to match
8971 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
8972 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, dl, DAG);
8973 if (NewSetCC.getNode()) {
8974 CC = NewSetCC.getOperand(0);
8975 Cond = NewSetCC.getOperand(1);
8982 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
8983 Cond = EmitTest(Cond, X86::COND_NE, DAG);
8985 return DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
8986 Chain, Dest, CC, Cond);
8990 // Lower dynamic stack allocation to _alloca call for Cygwin/Mingw targets.
8991 // Calls to _alloca is needed to probe the stack when allocating more than 4k
8992 // bytes in one go. Touching the stack at 4K increments is necessary to ensure
8993 // that the guard pages used by the OS virtual memory manager are allocated in
8994 // correct sequence.
8996 X86TargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
8997 SelectionDAG &DAG) const {
8998 assert((Subtarget->isTargetCygMing() || Subtarget->isTargetWindows() ||
8999 getTargetMachine().Options.EnableSegmentedStacks) &&
9000 "This should be used only on Windows targets or when segmented stacks "
9002 assert(!Subtarget->isTargetEnvMacho() && "Not implemented");
9003 DebugLoc dl = Op.getDebugLoc();
9006 SDValue Chain = Op.getOperand(0);
9007 SDValue Size = Op.getOperand(1);
9008 // FIXME: Ensure alignment here
9010 bool Is64Bit = Subtarget->is64Bit();
9011 EVT SPTy = Is64Bit ? MVT::i64 : MVT::i32;
9013 if (getTargetMachine().Options.EnableSegmentedStacks) {
9014 MachineFunction &MF = DAG.getMachineFunction();
9015 MachineRegisterInfo &MRI = MF.getRegInfo();
9018 // The 64 bit implementation of segmented stacks needs to clobber both r10
9019 // r11. This makes it impossible to use it along with nested parameters.
9020 const Function *F = MF.getFunction();
9022 for (Function::const_arg_iterator I = F->arg_begin(), E = F->arg_end();
9024 if (I->hasNestAttr())
9025 report_fatal_error("Cannot use segmented stacks with functions that "
9026 "have nested arguments.");
9029 const TargetRegisterClass *AddrRegClass =
9030 getRegClassFor(Subtarget->is64Bit() ? MVT::i64:MVT::i32);
9031 unsigned Vreg = MRI.createVirtualRegister(AddrRegClass);
9032 Chain = DAG.getCopyToReg(Chain, dl, Vreg, Size);
9033 SDValue Value = DAG.getNode(X86ISD::SEG_ALLOCA, dl, SPTy, Chain,
9034 DAG.getRegister(Vreg, SPTy));
9035 SDValue Ops1[2] = { Value, Chain };
9036 return DAG.getMergeValues(Ops1, 2, dl);
9039 unsigned Reg = (Subtarget->is64Bit() ? X86::RAX : X86::EAX);
9041 Chain = DAG.getCopyToReg(Chain, dl, Reg, Size, Flag);
9042 Flag = Chain.getValue(1);
9043 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
9045 Chain = DAG.getNode(X86ISD::WIN_ALLOCA, dl, NodeTys, Chain, Flag);
9046 Flag = Chain.getValue(1);
9048 Chain = DAG.getCopyFromReg(Chain, dl, X86StackPtr, SPTy).getValue(1);
9050 SDValue Ops1[2] = { Chain.getValue(0), Chain };
9051 return DAG.getMergeValues(Ops1, 2, dl);
9055 SDValue X86TargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const {
9056 MachineFunction &MF = DAG.getMachineFunction();
9057 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
9059 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
9060 DebugLoc DL = Op.getDebugLoc();
9062 if (!Subtarget->is64Bit() || Subtarget->isTargetWin64()) {
9063 // vastart just stores the address of the VarArgsFrameIndex slot into the
9064 // memory location argument.
9065 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
9067 return DAG.getStore(Op.getOperand(0), DL, FR, Op.getOperand(1),
9068 MachinePointerInfo(SV), false, false, 0);
9072 // gp_offset (0 - 6 * 8)
9073 // fp_offset (48 - 48 + 8 * 16)
9074 // overflow_arg_area (point to parameters coming in memory).
9076 SmallVector<SDValue, 8> MemOps;
9077 SDValue FIN = Op.getOperand(1);
9079 SDValue Store = DAG.getStore(Op.getOperand(0), DL,
9080 DAG.getConstant(FuncInfo->getVarArgsGPOffset(),
9082 FIN, MachinePointerInfo(SV), false, false, 0);
9083 MemOps.push_back(Store);
9086 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
9087 FIN, DAG.getIntPtrConstant(4));
9088 Store = DAG.getStore(Op.getOperand(0), DL,
9089 DAG.getConstant(FuncInfo->getVarArgsFPOffset(),
9091 FIN, MachinePointerInfo(SV, 4), false, false, 0);
9092 MemOps.push_back(Store);
9094 // Store ptr to overflow_arg_area
9095 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
9096 FIN, DAG.getIntPtrConstant(4));
9097 SDValue OVFIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
9099 Store = DAG.getStore(Op.getOperand(0), DL, OVFIN, FIN,
9100 MachinePointerInfo(SV, 8),
9102 MemOps.push_back(Store);
9104 // Store ptr to reg_save_area.
9105 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
9106 FIN, DAG.getIntPtrConstant(8));
9107 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
9109 Store = DAG.getStore(Op.getOperand(0), DL, RSFIN, FIN,
9110 MachinePointerInfo(SV, 16), false, false, 0);
9111 MemOps.push_back(Store);
9112 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
9113 &MemOps[0], MemOps.size());
9116 SDValue X86TargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG) const {
9117 assert(Subtarget->is64Bit() &&
9118 "LowerVAARG only handles 64-bit va_arg!");
9119 assert((Subtarget->isTargetLinux() ||
9120 Subtarget->isTargetDarwin()) &&
9121 "Unhandled target in LowerVAARG");
9122 assert(Op.getNode()->getNumOperands() == 4);
9123 SDValue Chain = Op.getOperand(0);
9124 SDValue SrcPtr = Op.getOperand(1);
9125 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
9126 unsigned Align = Op.getConstantOperandVal(3);
9127 DebugLoc dl = Op.getDebugLoc();
9129 EVT ArgVT = Op.getNode()->getValueType(0);
9130 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
9131 uint32_t ArgSize = getTargetData()->getTypeAllocSize(ArgTy);
9134 // Decide which area this value should be read from.
9135 // TODO: Implement the AMD64 ABI in its entirety. This simple
9136 // selection mechanism works only for the basic types.
9137 if (ArgVT == MVT::f80) {
9138 llvm_unreachable("va_arg for f80 not yet implemented");
9139 } else if (ArgVT.isFloatingPoint() && ArgSize <= 16 /*bytes*/) {
9140 ArgMode = 2; // Argument passed in XMM register. Use fp_offset.
9141 } else if (ArgVT.isInteger() && ArgSize <= 32 /*bytes*/) {
9142 ArgMode = 1; // Argument passed in GPR64 register(s). Use gp_offset.
9144 llvm_unreachable("Unhandled argument type in LowerVAARG");
9148 // Sanity Check: Make sure using fp_offset makes sense.
9149 assert(!getTargetMachine().Options.UseSoftFloat &&
9150 !(DAG.getMachineFunction()
9151 .getFunction()->hasFnAttr(Attribute::NoImplicitFloat)) &&
9152 Subtarget->hasSSE1());
9155 // Insert VAARG_64 node into the DAG
9156 // VAARG_64 returns two values: Variable Argument Address, Chain
9157 SmallVector<SDValue, 11> InstOps;
9158 InstOps.push_back(Chain);
9159 InstOps.push_back(SrcPtr);
9160 InstOps.push_back(DAG.getConstant(ArgSize, MVT::i32));
9161 InstOps.push_back(DAG.getConstant(ArgMode, MVT::i8));
9162 InstOps.push_back(DAG.getConstant(Align, MVT::i32));
9163 SDVTList VTs = DAG.getVTList(getPointerTy(), MVT::Other);
9164 SDValue VAARG = DAG.getMemIntrinsicNode(X86ISD::VAARG_64, dl,
9165 VTs, &InstOps[0], InstOps.size(),
9167 MachinePointerInfo(SV),
9172 Chain = VAARG.getValue(1);
9174 // Load the next argument and return it
9175 return DAG.getLoad(ArgVT, dl,
9178 MachinePointerInfo(),
9179 false, false, false, 0);
9182 SDValue X86TargetLowering::LowerVACOPY(SDValue Op, SelectionDAG &DAG) const {
9183 // X86-64 va_list is a struct { i32, i32, i8*, i8* }.
9184 assert(Subtarget->is64Bit() && "This code only handles 64-bit va_copy!");
9185 SDValue Chain = Op.getOperand(0);
9186 SDValue DstPtr = Op.getOperand(1);
9187 SDValue SrcPtr = Op.getOperand(2);
9188 const Value *DstSV = cast<SrcValueSDNode>(Op.getOperand(3))->getValue();
9189 const Value *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
9190 DebugLoc DL = Op.getDebugLoc();
9192 return DAG.getMemcpy(Chain, DL, DstPtr, SrcPtr,
9193 DAG.getIntPtrConstant(24), 8, /*isVolatile*/false,
9195 MachinePointerInfo(DstSV), MachinePointerInfo(SrcSV));
9198 // getTargetVShiftNOde - Handle vector element shifts where the shift amount
9199 // may or may not be a constant. Takes immediate version of shift as input.
9200 static SDValue getTargetVShiftNode(unsigned Opc, DebugLoc dl, EVT VT,
9201 SDValue SrcOp, SDValue ShAmt,
9202 SelectionDAG &DAG) {
9203 assert(ShAmt.getValueType() == MVT::i32 && "ShAmt is not i32");
9205 if (isa<ConstantSDNode>(ShAmt)) {
9207 default: llvm_unreachable("Unknown target vector shift node");
9211 return DAG.getNode(Opc, dl, VT, SrcOp, ShAmt);
9215 // Change opcode to non-immediate version
9217 default: llvm_unreachable("Unknown target vector shift node");
9218 case X86ISD::VSHLI: Opc = X86ISD::VSHL; break;
9219 case X86ISD::VSRLI: Opc = X86ISD::VSRL; break;
9220 case X86ISD::VSRAI: Opc = X86ISD::VSRA; break;
9223 // Need to build a vector containing shift amount
9224 // Shift amount is 32-bits, but SSE instructions read 64-bit, so fill with 0
9227 ShOps[1] = DAG.getConstant(0, MVT::i32);
9228 ShOps[2] = DAG.getUNDEF(MVT::i32);
9229 ShOps[3] = DAG.getUNDEF(MVT::i32);
9230 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, &ShOps[0], 4);
9231 ShAmt = DAG.getNode(ISD::BITCAST, dl, VT, ShAmt);
9232 return DAG.getNode(Opc, dl, VT, SrcOp, ShAmt);
9236 X86TargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const {
9237 DebugLoc dl = Op.getDebugLoc();
9238 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
9240 default: return SDValue(); // Don't custom lower most intrinsics.
9241 // Comparison intrinsics.
9242 case Intrinsic::x86_sse_comieq_ss:
9243 case Intrinsic::x86_sse_comilt_ss:
9244 case Intrinsic::x86_sse_comile_ss:
9245 case Intrinsic::x86_sse_comigt_ss:
9246 case Intrinsic::x86_sse_comige_ss:
9247 case Intrinsic::x86_sse_comineq_ss:
9248 case Intrinsic::x86_sse_ucomieq_ss:
9249 case Intrinsic::x86_sse_ucomilt_ss:
9250 case Intrinsic::x86_sse_ucomile_ss:
9251 case Intrinsic::x86_sse_ucomigt_ss:
9252 case Intrinsic::x86_sse_ucomige_ss:
9253 case Intrinsic::x86_sse_ucomineq_ss:
9254 case Intrinsic::x86_sse2_comieq_sd:
9255 case Intrinsic::x86_sse2_comilt_sd:
9256 case Intrinsic::x86_sse2_comile_sd:
9257 case Intrinsic::x86_sse2_comigt_sd:
9258 case Intrinsic::x86_sse2_comige_sd:
9259 case Intrinsic::x86_sse2_comineq_sd:
9260 case Intrinsic::x86_sse2_ucomieq_sd:
9261 case Intrinsic::x86_sse2_ucomilt_sd:
9262 case Intrinsic::x86_sse2_ucomile_sd:
9263 case Intrinsic::x86_sse2_ucomigt_sd:
9264 case Intrinsic::x86_sse2_ucomige_sd:
9265 case Intrinsic::x86_sse2_ucomineq_sd: {
9267 ISD::CondCode CC = ISD::SETCC_INVALID;
9269 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
9270 case Intrinsic::x86_sse_comieq_ss:
9271 case Intrinsic::x86_sse2_comieq_sd:
9275 case Intrinsic::x86_sse_comilt_ss:
9276 case Intrinsic::x86_sse2_comilt_sd:
9280 case Intrinsic::x86_sse_comile_ss:
9281 case Intrinsic::x86_sse2_comile_sd:
9285 case Intrinsic::x86_sse_comigt_ss:
9286 case Intrinsic::x86_sse2_comigt_sd:
9290 case Intrinsic::x86_sse_comige_ss:
9291 case Intrinsic::x86_sse2_comige_sd:
9295 case Intrinsic::x86_sse_comineq_ss:
9296 case Intrinsic::x86_sse2_comineq_sd:
9300 case Intrinsic::x86_sse_ucomieq_ss:
9301 case Intrinsic::x86_sse2_ucomieq_sd:
9302 Opc = X86ISD::UCOMI;
9305 case Intrinsic::x86_sse_ucomilt_ss:
9306 case Intrinsic::x86_sse2_ucomilt_sd:
9307 Opc = X86ISD::UCOMI;
9310 case Intrinsic::x86_sse_ucomile_ss:
9311 case Intrinsic::x86_sse2_ucomile_sd:
9312 Opc = X86ISD::UCOMI;
9315 case Intrinsic::x86_sse_ucomigt_ss:
9316 case Intrinsic::x86_sse2_ucomigt_sd:
9317 Opc = X86ISD::UCOMI;
9320 case Intrinsic::x86_sse_ucomige_ss:
9321 case Intrinsic::x86_sse2_ucomige_sd:
9322 Opc = X86ISD::UCOMI;
9325 case Intrinsic::x86_sse_ucomineq_ss:
9326 case Intrinsic::x86_sse2_ucomineq_sd:
9327 Opc = X86ISD::UCOMI;
9332 SDValue LHS = Op.getOperand(1);
9333 SDValue RHS = Op.getOperand(2);
9334 unsigned X86CC = TranslateX86CC(CC, true, LHS, RHS, DAG);
9335 assert(X86CC != X86::COND_INVALID && "Unexpected illegal condition!");
9336 SDValue Cond = DAG.getNode(Opc, dl, MVT::i32, LHS, RHS);
9337 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
9338 DAG.getConstant(X86CC, MVT::i8), Cond);
9339 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
9341 // XOP comparison intrinsics
9342 case Intrinsic::x86_xop_vpcomltb:
9343 case Intrinsic::x86_xop_vpcomltw:
9344 case Intrinsic::x86_xop_vpcomltd:
9345 case Intrinsic::x86_xop_vpcomltq:
9346 case Intrinsic::x86_xop_vpcomltub:
9347 case Intrinsic::x86_xop_vpcomltuw:
9348 case Intrinsic::x86_xop_vpcomltud:
9349 case Intrinsic::x86_xop_vpcomltuq:
9350 case Intrinsic::x86_xop_vpcomleb:
9351 case Intrinsic::x86_xop_vpcomlew:
9352 case Intrinsic::x86_xop_vpcomled:
9353 case Intrinsic::x86_xop_vpcomleq:
9354 case Intrinsic::x86_xop_vpcomleub:
9355 case Intrinsic::x86_xop_vpcomleuw:
9356 case Intrinsic::x86_xop_vpcomleud:
9357 case Intrinsic::x86_xop_vpcomleuq:
9358 case Intrinsic::x86_xop_vpcomgtb:
9359 case Intrinsic::x86_xop_vpcomgtw:
9360 case Intrinsic::x86_xop_vpcomgtd:
9361 case Intrinsic::x86_xop_vpcomgtq:
9362 case Intrinsic::x86_xop_vpcomgtub:
9363 case Intrinsic::x86_xop_vpcomgtuw:
9364 case Intrinsic::x86_xop_vpcomgtud:
9365 case Intrinsic::x86_xop_vpcomgtuq:
9366 case Intrinsic::x86_xop_vpcomgeb:
9367 case Intrinsic::x86_xop_vpcomgew:
9368 case Intrinsic::x86_xop_vpcomged:
9369 case Intrinsic::x86_xop_vpcomgeq:
9370 case Intrinsic::x86_xop_vpcomgeub:
9371 case Intrinsic::x86_xop_vpcomgeuw:
9372 case Intrinsic::x86_xop_vpcomgeud:
9373 case Intrinsic::x86_xop_vpcomgeuq:
9374 case Intrinsic::x86_xop_vpcomeqb:
9375 case Intrinsic::x86_xop_vpcomeqw:
9376 case Intrinsic::x86_xop_vpcomeqd:
9377 case Intrinsic::x86_xop_vpcomeqq:
9378 case Intrinsic::x86_xop_vpcomequb:
9379 case Intrinsic::x86_xop_vpcomequw:
9380 case Intrinsic::x86_xop_vpcomequd:
9381 case Intrinsic::x86_xop_vpcomequq:
9382 case Intrinsic::x86_xop_vpcomneb:
9383 case Intrinsic::x86_xop_vpcomnew:
9384 case Intrinsic::x86_xop_vpcomned:
9385 case Intrinsic::x86_xop_vpcomneq:
9386 case Intrinsic::x86_xop_vpcomneub:
9387 case Intrinsic::x86_xop_vpcomneuw:
9388 case Intrinsic::x86_xop_vpcomneud:
9389 case Intrinsic::x86_xop_vpcomneuq:
9390 case Intrinsic::x86_xop_vpcomfalseb:
9391 case Intrinsic::x86_xop_vpcomfalsew:
9392 case Intrinsic::x86_xop_vpcomfalsed:
9393 case Intrinsic::x86_xop_vpcomfalseq:
9394 case Intrinsic::x86_xop_vpcomfalseub:
9395 case Intrinsic::x86_xop_vpcomfalseuw:
9396 case Intrinsic::x86_xop_vpcomfalseud:
9397 case Intrinsic::x86_xop_vpcomfalseuq:
9398 case Intrinsic::x86_xop_vpcomtrueb:
9399 case Intrinsic::x86_xop_vpcomtruew:
9400 case Intrinsic::x86_xop_vpcomtrued:
9401 case Intrinsic::x86_xop_vpcomtrueq:
9402 case Intrinsic::x86_xop_vpcomtrueub:
9403 case Intrinsic::x86_xop_vpcomtrueuw:
9404 case Intrinsic::x86_xop_vpcomtrueud:
9405 case Intrinsic::x86_xop_vpcomtrueuq: {
9410 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
9411 case Intrinsic::x86_xop_vpcomltb:
9412 case Intrinsic::x86_xop_vpcomltw:
9413 case Intrinsic::x86_xop_vpcomltd:
9414 case Intrinsic::x86_xop_vpcomltq:
9416 Opc = X86ISD::VPCOM;
9418 case Intrinsic::x86_xop_vpcomltub:
9419 case Intrinsic::x86_xop_vpcomltuw:
9420 case Intrinsic::x86_xop_vpcomltud:
9421 case Intrinsic::x86_xop_vpcomltuq:
9423 Opc = X86ISD::VPCOMU;
9425 case Intrinsic::x86_xop_vpcomleb:
9426 case Intrinsic::x86_xop_vpcomlew:
9427 case Intrinsic::x86_xop_vpcomled:
9428 case Intrinsic::x86_xop_vpcomleq:
9430 Opc = X86ISD::VPCOM;
9432 case Intrinsic::x86_xop_vpcomleub:
9433 case Intrinsic::x86_xop_vpcomleuw:
9434 case Intrinsic::x86_xop_vpcomleud:
9435 case Intrinsic::x86_xop_vpcomleuq:
9437 Opc = X86ISD::VPCOMU;
9439 case Intrinsic::x86_xop_vpcomgtb:
9440 case Intrinsic::x86_xop_vpcomgtw:
9441 case Intrinsic::x86_xop_vpcomgtd:
9442 case Intrinsic::x86_xop_vpcomgtq:
9444 Opc = X86ISD::VPCOM;
9446 case Intrinsic::x86_xop_vpcomgtub:
9447 case Intrinsic::x86_xop_vpcomgtuw:
9448 case Intrinsic::x86_xop_vpcomgtud:
9449 case Intrinsic::x86_xop_vpcomgtuq:
9451 Opc = X86ISD::VPCOMU;
9453 case Intrinsic::x86_xop_vpcomgeb:
9454 case Intrinsic::x86_xop_vpcomgew:
9455 case Intrinsic::x86_xop_vpcomged:
9456 case Intrinsic::x86_xop_vpcomgeq:
9458 Opc = X86ISD::VPCOM;
9460 case Intrinsic::x86_xop_vpcomgeub:
9461 case Intrinsic::x86_xop_vpcomgeuw:
9462 case Intrinsic::x86_xop_vpcomgeud:
9463 case Intrinsic::x86_xop_vpcomgeuq:
9465 Opc = X86ISD::VPCOMU;
9467 case Intrinsic::x86_xop_vpcomeqb:
9468 case Intrinsic::x86_xop_vpcomeqw:
9469 case Intrinsic::x86_xop_vpcomeqd:
9470 case Intrinsic::x86_xop_vpcomeqq:
9472 Opc = X86ISD::VPCOM;
9474 case Intrinsic::x86_xop_vpcomequb:
9475 case Intrinsic::x86_xop_vpcomequw:
9476 case Intrinsic::x86_xop_vpcomequd:
9477 case Intrinsic::x86_xop_vpcomequq:
9479 Opc = X86ISD::VPCOMU;
9481 case Intrinsic::x86_xop_vpcomneb:
9482 case Intrinsic::x86_xop_vpcomnew:
9483 case Intrinsic::x86_xop_vpcomned:
9484 case Intrinsic::x86_xop_vpcomneq:
9486 Opc = X86ISD::VPCOM;
9488 case Intrinsic::x86_xop_vpcomneub:
9489 case Intrinsic::x86_xop_vpcomneuw:
9490 case Intrinsic::x86_xop_vpcomneud:
9491 case Intrinsic::x86_xop_vpcomneuq:
9493 Opc = X86ISD::VPCOMU;
9495 case Intrinsic::x86_xop_vpcomfalseb:
9496 case Intrinsic::x86_xop_vpcomfalsew:
9497 case Intrinsic::x86_xop_vpcomfalsed:
9498 case Intrinsic::x86_xop_vpcomfalseq:
9500 Opc = X86ISD::VPCOM;
9502 case Intrinsic::x86_xop_vpcomfalseub:
9503 case Intrinsic::x86_xop_vpcomfalseuw:
9504 case Intrinsic::x86_xop_vpcomfalseud:
9505 case Intrinsic::x86_xop_vpcomfalseuq:
9507 Opc = X86ISD::VPCOMU;
9509 case Intrinsic::x86_xop_vpcomtrueb:
9510 case Intrinsic::x86_xop_vpcomtruew:
9511 case Intrinsic::x86_xop_vpcomtrued:
9512 case Intrinsic::x86_xop_vpcomtrueq:
9514 Opc = X86ISD::VPCOM;
9516 case Intrinsic::x86_xop_vpcomtrueub:
9517 case Intrinsic::x86_xop_vpcomtrueuw:
9518 case Intrinsic::x86_xop_vpcomtrueud:
9519 case Intrinsic::x86_xop_vpcomtrueuq:
9521 Opc = X86ISD::VPCOMU;
9525 SDValue LHS = Op.getOperand(1);
9526 SDValue RHS = Op.getOperand(2);
9527 return DAG.getNode(Opc, dl, Op.getValueType(), LHS, RHS,
9528 DAG.getConstant(CC, MVT::i8));
9531 // Arithmetic intrinsics.
9532 case Intrinsic::x86_sse2_pmulu_dq:
9533 case Intrinsic::x86_avx2_pmulu_dq:
9534 return DAG.getNode(X86ISD::PMULUDQ, dl, Op.getValueType(),
9535 Op.getOperand(1), Op.getOperand(2));
9536 case Intrinsic::x86_sse3_hadd_ps:
9537 case Intrinsic::x86_sse3_hadd_pd:
9538 case Intrinsic::x86_avx_hadd_ps_256:
9539 case Intrinsic::x86_avx_hadd_pd_256:
9540 return DAG.getNode(X86ISD::FHADD, dl, Op.getValueType(),
9541 Op.getOperand(1), Op.getOperand(2));
9542 case Intrinsic::x86_sse3_hsub_ps:
9543 case Intrinsic::x86_sse3_hsub_pd:
9544 case Intrinsic::x86_avx_hsub_ps_256:
9545 case Intrinsic::x86_avx_hsub_pd_256:
9546 return DAG.getNode(X86ISD::FHSUB, dl, Op.getValueType(),
9547 Op.getOperand(1), Op.getOperand(2));
9548 case Intrinsic::x86_ssse3_phadd_w_128:
9549 case Intrinsic::x86_ssse3_phadd_d_128:
9550 case Intrinsic::x86_avx2_phadd_w:
9551 case Intrinsic::x86_avx2_phadd_d:
9552 return DAG.getNode(X86ISD::HADD, dl, Op.getValueType(),
9553 Op.getOperand(1), Op.getOperand(2));
9554 case Intrinsic::x86_ssse3_phsub_w_128:
9555 case Intrinsic::x86_ssse3_phsub_d_128:
9556 case Intrinsic::x86_avx2_phsub_w:
9557 case Intrinsic::x86_avx2_phsub_d:
9558 return DAG.getNode(X86ISD::HSUB, dl, Op.getValueType(),
9559 Op.getOperand(1), Op.getOperand(2));
9560 case Intrinsic::x86_avx2_psllv_d:
9561 case Intrinsic::x86_avx2_psllv_q:
9562 case Intrinsic::x86_avx2_psllv_d_256:
9563 case Intrinsic::x86_avx2_psllv_q_256:
9564 return DAG.getNode(ISD::SHL, dl, Op.getValueType(),
9565 Op.getOperand(1), Op.getOperand(2));
9566 case Intrinsic::x86_avx2_psrlv_d:
9567 case Intrinsic::x86_avx2_psrlv_q:
9568 case Intrinsic::x86_avx2_psrlv_d_256:
9569 case Intrinsic::x86_avx2_psrlv_q_256:
9570 return DAG.getNode(ISD::SRL, dl, Op.getValueType(),
9571 Op.getOperand(1), Op.getOperand(2));
9572 case Intrinsic::x86_avx2_psrav_d:
9573 case Intrinsic::x86_avx2_psrav_d_256:
9574 return DAG.getNode(ISD::SRA, dl, Op.getValueType(),
9575 Op.getOperand(1), Op.getOperand(2));
9576 case Intrinsic::x86_ssse3_pshuf_b_128:
9577 case Intrinsic::x86_avx2_pshuf_b:
9578 return DAG.getNode(X86ISD::PSHUFB, dl, Op.getValueType(),
9579 Op.getOperand(1), Op.getOperand(2));
9580 case Intrinsic::x86_ssse3_psign_b_128:
9581 case Intrinsic::x86_ssse3_psign_w_128:
9582 case Intrinsic::x86_ssse3_psign_d_128:
9583 case Intrinsic::x86_avx2_psign_b:
9584 case Intrinsic::x86_avx2_psign_w:
9585 case Intrinsic::x86_avx2_psign_d:
9586 return DAG.getNode(X86ISD::PSIGN, dl, Op.getValueType(),
9587 Op.getOperand(1), Op.getOperand(2));
9588 case Intrinsic::x86_sse41_insertps:
9589 return DAG.getNode(X86ISD::INSERTPS, dl, Op.getValueType(),
9590 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
9591 case Intrinsic::x86_avx_vperm2f128_ps_256:
9592 case Intrinsic::x86_avx_vperm2f128_pd_256:
9593 case Intrinsic::x86_avx_vperm2f128_si_256:
9594 case Intrinsic::x86_avx2_vperm2i128:
9595 return DAG.getNode(X86ISD::VPERM2X128, dl, Op.getValueType(),
9596 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
9597 case Intrinsic::x86_avx2_permd:
9598 case Intrinsic::x86_avx2_permps:
9599 // Operands intentionally swapped. Mask is last operand to intrinsic,
9600 // but second operand for node/intruction.
9601 return DAG.getNode(X86ISD::VPERMV, dl, Op.getValueType(),
9602 Op.getOperand(2), Op.getOperand(1));
9604 // ptest and testp intrinsics. The intrinsic these come from are designed to
9605 // return an integer value, not just an instruction so lower it to the ptest
9606 // or testp pattern and a setcc for the result.
9607 case Intrinsic::x86_sse41_ptestz:
9608 case Intrinsic::x86_sse41_ptestc:
9609 case Intrinsic::x86_sse41_ptestnzc:
9610 case Intrinsic::x86_avx_ptestz_256:
9611 case Intrinsic::x86_avx_ptestc_256:
9612 case Intrinsic::x86_avx_ptestnzc_256:
9613 case Intrinsic::x86_avx_vtestz_ps:
9614 case Intrinsic::x86_avx_vtestc_ps:
9615 case Intrinsic::x86_avx_vtestnzc_ps:
9616 case Intrinsic::x86_avx_vtestz_pd:
9617 case Intrinsic::x86_avx_vtestc_pd:
9618 case Intrinsic::x86_avx_vtestnzc_pd:
9619 case Intrinsic::x86_avx_vtestz_ps_256:
9620 case Intrinsic::x86_avx_vtestc_ps_256:
9621 case Intrinsic::x86_avx_vtestnzc_ps_256:
9622 case Intrinsic::x86_avx_vtestz_pd_256:
9623 case Intrinsic::x86_avx_vtestc_pd_256:
9624 case Intrinsic::x86_avx_vtestnzc_pd_256: {
9625 bool IsTestPacked = false;
9628 default: llvm_unreachable("Bad fallthrough in Intrinsic lowering.");
9629 case Intrinsic::x86_avx_vtestz_ps:
9630 case Intrinsic::x86_avx_vtestz_pd:
9631 case Intrinsic::x86_avx_vtestz_ps_256:
9632 case Intrinsic::x86_avx_vtestz_pd_256:
9633 IsTestPacked = true; // Fallthrough
9634 case Intrinsic::x86_sse41_ptestz:
9635 case Intrinsic::x86_avx_ptestz_256:
9637 X86CC = X86::COND_E;
9639 case Intrinsic::x86_avx_vtestc_ps:
9640 case Intrinsic::x86_avx_vtestc_pd:
9641 case Intrinsic::x86_avx_vtestc_ps_256:
9642 case Intrinsic::x86_avx_vtestc_pd_256:
9643 IsTestPacked = true; // Fallthrough
9644 case Intrinsic::x86_sse41_ptestc:
9645 case Intrinsic::x86_avx_ptestc_256:
9647 X86CC = X86::COND_B;
9649 case Intrinsic::x86_avx_vtestnzc_ps:
9650 case Intrinsic::x86_avx_vtestnzc_pd:
9651 case Intrinsic::x86_avx_vtestnzc_ps_256:
9652 case Intrinsic::x86_avx_vtestnzc_pd_256:
9653 IsTestPacked = true; // Fallthrough
9654 case Intrinsic::x86_sse41_ptestnzc:
9655 case Intrinsic::x86_avx_ptestnzc_256:
9657 X86CC = X86::COND_A;
9661 SDValue LHS = Op.getOperand(1);
9662 SDValue RHS = Op.getOperand(2);
9663 unsigned TestOpc = IsTestPacked ? X86ISD::TESTP : X86ISD::PTEST;
9664 SDValue Test = DAG.getNode(TestOpc, dl, MVT::i32, LHS, RHS);
9665 SDValue CC = DAG.getConstant(X86CC, MVT::i8);
9666 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8, CC, Test);
9667 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
9670 // SSE/AVX shift intrinsics
9671 case Intrinsic::x86_sse2_psll_w:
9672 case Intrinsic::x86_sse2_psll_d:
9673 case Intrinsic::x86_sse2_psll_q:
9674 case Intrinsic::x86_avx2_psll_w:
9675 case Intrinsic::x86_avx2_psll_d:
9676 case Intrinsic::x86_avx2_psll_q:
9677 return DAG.getNode(X86ISD::VSHL, dl, Op.getValueType(),
9678 Op.getOperand(1), Op.getOperand(2));
9679 case Intrinsic::x86_sse2_psrl_w:
9680 case Intrinsic::x86_sse2_psrl_d:
9681 case Intrinsic::x86_sse2_psrl_q:
9682 case Intrinsic::x86_avx2_psrl_w:
9683 case Intrinsic::x86_avx2_psrl_d:
9684 case Intrinsic::x86_avx2_psrl_q:
9685 return DAG.getNode(X86ISD::VSRL, dl, Op.getValueType(),
9686 Op.getOperand(1), Op.getOperand(2));
9687 case Intrinsic::x86_sse2_psra_w:
9688 case Intrinsic::x86_sse2_psra_d:
9689 case Intrinsic::x86_avx2_psra_w:
9690 case Intrinsic::x86_avx2_psra_d:
9691 return DAG.getNode(X86ISD::VSRA, dl, Op.getValueType(),
9692 Op.getOperand(1), Op.getOperand(2));
9693 case Intrinsic::x86_sse2_pslli_w:
9694 case Intrinsic::x86_sse2_pslli_d:
9695 case Intrinsic::x86_sse2_pslli_q:
9696 case Intrinsic::x86_avx2_pslli_w:
9697 case Intrinsic::x86_avx2_pslli_d:
9698 case Intrinsic::x86_avx2_pslli_q:
9699 return getTargetVShiftNode(X86ISD::VSHLI, dl, Op.getValueType(),
9700 Op.getOperand(1), Op.getOperand(2), DAG);
9701 case Intrinsic::x86_sse2_psrli_w:
9702 case Intrinsic::x86_sse2_psrli_d:
9703 case Intrinsic::x86_sse2_psrli_q:
9704 case Intrinsic::x86_avx2_psrli_w:
9705 case Intrinsic::x86_avx2_psrli_d:
9706 case Intrinsic::x86_avx2_psrli_q:
9707 return getTargetVShiftNode(X86ISD::VSRLI, dl, Op.getValueType(),
9708 Op.getOperand(1), Op.getOperand(2), DAG);
9709 case Intrinsic::x86_sse2_psrai_w:
9710 case Intrinsic::x86_sse2_psrai_d:
9711 case Intrinsic::x86_avx2_psrai_w:
9712 case Intrinsic::x86_avx2_psrai_d:
9713 return getTargetVShiftNode(X86ISD::VSRAI, dl, Op.getValueType(),
9714 Op.getOperand(1), Op.getOperand(2), DAG);
9715 // Fix vector shift instructions where the last operand is a non-immediate
9717 case Intrinsic::x86_mmx_pslli_w:
9718 case Intrinsic::x86_mmx_pslli_d:
9719 case Intrinsic::x86_mmx_pslli_q:
9720 case Intrinsic::x86_mmx_psrli_w:
9721 case Intrinsic::x86_mmx_psrli_d:
9722 case Intrinsic::x86_mmx_psrli_q:
9723 case Intrinsic::x86_mmx_psrai_w:
9724 case Intrinsic::x86_mmx_psrai_d: {
9725 SDValue ShAmt = Op.getOperand(2);
9726 if (isa<ConstantSDNode>(ShAmt))
9729 unsigned NewIntNo = 0;
9731 case Intrinsic::x86_mmx_pslli_w:
9732 NewIntNo = Intrinsic::x86_mmx_psll_w;
9734 case Intrinsic::x86_mmx_pslli_d:
9735 NewIntNo = Intrinsic::x86_mmx_psll_d;
9737 case Intrinsic::x86_mmx_pslli_q:
9738 NewIntNo = Intrinsic::x86_mmx_psll_q;
9740 case Intrinsic::x86_mmx_psrli_w:
9741 NewIntNo = Intrinsic::x86_mmx_psrl_w;
9743 case Intrinsic::x86_mmx_psrli_d:
9744 NewIntNo = Intrinsic::x86_mmx_psrl_d;
9746 case Intrinsic::x86_mmx_psrli_q:
9747 NewIntNo = Intrinsic::x86_mmx_psrl_q;
9749 case Intrinsic::x86_mmx_psrai_w:
9750 NewIntNo = Intrinsic::x86_mmx_psra_w;
9752 case Intrinsic::x86_mmx_psrai_d:
9753 NewIntNo = Intrinsic::x86_mmx_psra_d;
9755 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
9758 // The vector shift intrinsics with scalars uses 32b shift amounts but
9759 // the sse2/mmx shift instructions reads 64 bits. Set the upper 32 bits
9761 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2i32, ShAmt,
9762 DAG.getConstant(0, MVT::i32));
9763 // FIXME this must be lowered to get rid of the invalid type.
9765 EVT VT = Op.getValueType();
9766 ShAmt = DAG.getNode(ISD::BITCAST, dl, VT, ShAmt);
9767 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
9768 DAG.getConstant(NewIntNo, MVT::i32),
9769 Op.getOperand(1), ShAmt);
9774 SDValue X86TargetLowering::LowerRETURNADDR(SDValue Op,
9775 SelectionDAG &DAG) const {
9776 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
9777 MFI->setReturnAddressIsTaken(true);
9779 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
9780 DebugLoc dl = Op.getDebugLoc();
9783 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
9785 DAG.getConstant(TD->getPointerSize(),
9786 Subtarget->is64Bit() ? MVT::i64 : MVT::i32);
9787 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(),
9788 DAG.getNode(ISD::ADD, dl, getPointerTy(),
9790 MachinePointerInfo(), false, false, false, 0);
9793 // Just load the return address.
9794 SDValue RetAddrFI = getReturnAddressFrameIndex(DAG);
9795 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(),
9796 RetAddrFI, MachinePointerInfo(), false, false, false, 0);
9799 SDValue X86TargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {
9800 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
9801 MFI->setFrameAddressIsTaken(true);
9803 EVT VT = Op.getValueType();
9804 DebugLoc dl = Op.getDebugLoc(); // FIXME probably not meaningful
9805 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
9806 unsigned FrameReg = Subtarget->is64Bit() ? X86::RBP : X86::EBP;
9807 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT);
9809 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr,
9810 MachinePointerInfo(),
9811 false, false, false, 0);
9815 SDValue X86TargetLowering::LowerFRAME_TO_ARGS_OFFSET(SDValue Op,
9816 SelectionDAG &DAG) const {
9817 return DAG.getIntPtrConstant(2*TD->getPointerSize());
9820 SDValue X86TargetLowering::LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const {
9821 MachineFunction &MF = DAG.getMachineFunction();
9822 SDValue Chain = Op.getOperand(0);
9823 SDValue Offset = Op.getOperand(1);
9824 SDValue Handler = Op.getOperand(2);
9825 DebugLoc dl = Op.getDebugLoc();
9827 SDValue Frame = DAG.getCopyFromReg(DAG.getEntryNode(), dl,
9828 Subtarget->is64Bit() ? X86::RBP : X86::EBP,
9830 unsigned StoreAddrReg = (Subtarget->is64Bit() ? X86::RCX : X86::ECX);
9832 SDValue StoreAddr = DAG.getNode(ISD::ADD, dl, getPointerTy(), Frame,
9833 DAG.getIntPtrConstant(TD->getPointerSize()));
9834 StoreAddr = DAG.getNode(ISD::ADD, dl, getPointerTy(), StoreAddr, Offset);
9835 Chain = DAG.getStore(Chain, dl, Handler, StoreAddr, MachinePointerInfo(),
9837 Chain = DAG.getCopyToReg(Chain, dl, StoreAddrReg, StoreAddr);
9838 MF.getRegInfo().addLiveOut(StoreAddrReg);
9840 return DAG.getNode(X86ISD::EH_RETURN, dl,
9842 Chain, DAG.getRegister(StoreAddrReg, getPointerTy()));
9845 SDValue X86TargetLowering::LowerADJUST_TRAMPOLINE(SDValue Op,
9846 SelectionDAG &DAG) const {
9847 return Op.getOperand(0);
9850 SDValue X86TargetLowering::LowerINIT_TRAMPOLINE(SDValue Op,
9851 SelectionDAG &DAG) const {
9852 SDValue Root = Op.getOperand(0);
9853 SDValue Trmp = Op.getOperand(1); // trampoline
9854 SDValue FPtr = Op.getOperand(2); // nested function
9855 SDValue Nest = Op.getOperand(3); // 'nest' parameter value
9856 DebugLoc dl = Op.getDebugLoc();
9858 const Value *TrmpAddr = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
9860 if (Subtarget->is64Bit()) {
9861 SDValue OutChains[6];
9863 // Large code-model.
9864 const unsigned char JMP64r = 0xFF; // 64-bit jmp through register opcode.
9865 const unsigned char MOV64ri = 0xB8; // X86::MOV64ri opcode.
9867 const unsigned char N86R10 = X86_MC::getX86RegNum(X86::R10);
9868 const unsigned char N86R11 = X86_MC::getX86RegNum(X86::R11);
9870 const unsigned char REX_WB = 0x40 | 0x08 | 0x01; // REX prefix
9872 // Load the pointer to the nested function into R11.
9873 unsigned OpCode = ((MOV64ri | N86R11) << 8) | REX_WB; // movabsq r11
9874 SDValue Addr = Trmp;
9875 OutChains[0] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
9876 Addr, MachinePointerInfo(TrmpAddr),
9879 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
9880 DAG.getConstant(2, MVT::i64));
9881 OutChains[1] = DAG.getStore(Root, dl, FPtr, Addr,
9882 MachinePointerInfo(TrmpAddr, 2),
9885 // Load the 'nest' parameter value into R10.
9886 // R10 is specified in X86CallingConv.td
9887 OpCode = ((MOV64ri | N86R10) << 8) | REX_WB; // movabsq r10
9888 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
9889 DAG.getConstant(10, MVT::i64));
9890 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
9891 Addr, MachinePointerInfo(TrmpAddr, 10),
9894 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
9895 DAG.getConstant(12, MVT::i64));
9896 OutChains[3] = DAG.getStore(Root, dl, Nest, Addr,
9897 MachinePointerInfo(TrmpAddr, 12),
9900 // Jump to the nested function.
9901 OpCode = (JMP64r << 8) | REX_WB; // jmpq *...
9902 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
9903 DAG.getConstant(20, MVT::i64));
9904 OutChains[4] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
9905 Addr, MachinePointerInfo(TrmpAddr, 20),
9908 unsigned char ModRM = N86R11 | (4 << 3) | (3 << 6); // ...r11
9909 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
9910 DAG.getConstant(22, MVT::i64));
9911 OutChains[5] = DAG.getStore(Root, dl, DAG.getConstant(ModRM, MVT::i8), Addr,
9912 MachinePointerInfo(TrmpAddr, 22),
9915 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains, 6);
9917 const Function *Func =
9918 cast<Function>(cast<SrcValueSDNode>(Op.getOperand(5))->getValue());
9919 CallingConv::ID CC = Func->getCallingConv();
9924 llvm_unreachable("Unsupported calling convention");
9925 case CallingConv::C:
9926 case CallingConv::X86_StdCall: {
9927 // Pass 'nest' parameter in ECX.
9928 // Must be kept in sync with X86CallingConv.td
9931 // Check that ECX wasn't needed by an 'inreg' parameter.
9932 FunctionType *FTy = Func->getFunctionType();
9933 const AttrListPtr &Attrs = Func->getAttributes();
9935 if (!Attrs.isEmpty() && !Func->isVarArg()) {
9936 unsigned InRegCount = 0;
9939 for (FunctionType::param_iterator I = FTy->param_begin(),
9940 E = FTy->param_end(); I != E; ++I, ++Idx)
9941 if (Attrs.paramHasAttr(Idx, Attribute::InReg))
9942 // FIXME: should only count parameters that are lowered to integers.
9943 InRegCount += (TD->getTypeSizeInBits(*I) + 31) / 32;
9945 if (InRegCount > 2) {
9946 report_fatal_error("Nest register in use - reduce number of inreg"
9952 case CallingConv::X86_FastCall:
9953 case CallingConv::X86_ThisCall:
9954 case CallingConv::Fast:
9955 // Pass 'nest' parameter in EAX.
9956 // Must be kept in sync with X86CallingConv.td
9961 SDValue OutChains[4];
9964 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
9965 DAG.getConstant(10, MVT::i32));
9966 Disp = DAG.getNode(ISD::SUB, dl, MVT::i32, FPtr, Addr);
9968 // This is storing the opcode for MOV32ri.
9969 const unsigned char MOV32ri = 0xB8; // X86::MOV32ri's opcode byte.
9970 const unsigned char N86Reg = X86_MC::getX86RegNum(NestReg);
9971 OutChains[0] = DAG.getStore(Root, dl,
9972 DAG.getConstant(MOV32ri|N86Reg, MVT::i8),
9973 Trmp, MachinePointerInfo(TrmpAddr),
9976 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
9977 DAG.getConstant(1, MVT::i32));
9978 OutChains[1] = DAG.getStore(Root, dl, Nest, Addr,
9979 MachinePointerInfo(TrmpAddr, 1),
9982 const unsigned char JMP = 0xE9; // jmp <32bit dst> opcode.
9983 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
9984 DAG.getConstant(5, MVT::i32));
9985 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(JMP, MVT::i8), Addr,
9986 MachinePointerInfo(TrmpAddr, 5),
9989 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
9990 DAG.getConstant(6, MVT::i32));
9991 OutChains[3] = DAG.getStore(Root, dl, Disp, Addr,
9992 MachinePointerInfo(TrmpAddr, 6),
9995 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains, 4);
9999 SDValue X86TargetLowering::LowerFLT_ROUNDS_(SDValue Op,
10000 SelectionDAG &DAG) const {
10002 The rounding mode is in bits 11:10 of FPSR, and has the following
10004 00 Round to nearest
10009 FLT_ROUNDS, on the other hand, expects the following:
10016 To perform the conversion, we do:
10017 (((((FPSR & 0x800) >> 11) | ((FPSR & 0x400) >> 9)) + 1) & 3)
10020 MachineFunction &MF = DAG.getMachineFunction();
10021 const TargetMachine &TM = MF.getTarget();
10022 const TargetFrameLowering &TFI = *TM.getFrameLowering();
10023 unsigned StackAlignment = TFI.getStackAlignment();
10024 EVT VT = Op.getValueType();
10025 DebugLoc DL = Op.getDebugLoc();
10027 // Save FP Control Word to stack slot
10028 int SSFI = MF.getFrameInfo()->CreateStackObject(2, StackAlignment, false);
10029 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
10032 MachineMemOperand *MMO =
10033 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
10034 MachineMemOperand::MOStore, 2, 2);
10036 SDValue Ops[] = { DAG.getEntryNode(), StackSlot };
10037 SDValue Chain = DAG.getMemIntrinsicNode(X86ISD::FNSTCW16m, DL,
10038 DAG.getVTList(MVT::Other),
10039 Ops, 2, MVT::i16, MMO);
10041 // Load FP Control Word from stack slot
10042 SDValue CWD = DAG.getLoad(MVT::i16, DL, Chain, StackSlot,
10043 MachinePointerInfo(), false, false, false, 0);
10045 // Transform as necessary
10047 DAG.getNode(ISD::SRL, DL, MVT::i16,
10048 DAG.getNode(ISD::AND, DL, MVT::i16,
10049 CWD, DAG.getConstant(0x800, MVT::i16)),
10050 DAG.getConstant(11, MVT::i8));
10052 DAG.getNode(ISD::SRL, DL, MVT::i16,
10053 DAG.getNode(ISD::AND, DL, MVT::i16,
10054 CWD, DAG.getConstant(0x400, MVT::i16)),
10055 DAG.getConstant(9, MVT::i8));
10058 DAG.getNode(ISD::AND, DL, MVT::i16,
10059 DAG.getNode(ISD::ADD, DL, MVT::i16,
10060 DAG.getNode(ISD::OR, DL, MVT::i16, CWD1, CWD2),
10061 DAG.getConstant(1, MVT::i16)),
10062 DAG.getConstant(3, MVT::i16));
10065 return DAG.getNode((VT.getSizeInBits() < 16 ?
10066 ISD::TRUNCATE : ISD::ZERO_EXTEND), DL, VT, RetVal);
10069 SDValue X86TargetLowering::LowerCTLZ(SDValue Op, SelectionDAG &DAG) const {
10070 EVT VT = Op.getValueType();
10072 unsigned NumBits = VT.getSizeInBits();
10073 DebugLoc dl = Op.getDebugLoc();
10075 Op = Op.getOperand(0);
10076 if (VT == MVT::i8) {
10077 // Zero extend to i32 since there is not an i8 bsr.
10079 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
10082 // Issue a bsr (scan bits in reverse) which also sets EFLAGS.
10083 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
10084 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
10086 // If src is zero (i.e. bsr sets ZF), returns NumBits.
10089 DAG.getConstant(NumBits+NumBits-1, OpVT),
10090 DAG.getConstant(X86::COND_E, MVT::i8),
10093 Op = DAG.getNode(X86ISD::CMOV, dl, OpVT, Ops, array_lengthof(Ops));
10095 // Finally xor with NumBits-1.
10096 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT));
10099 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
10103 SDValue X86TargetLowering::LowerCTLZ_ZERO_UNDEF(SDValue Op,
10104 SelectionDAG &DAG) const {
10105 EVT VT = Op.getValueType();
10107 unsigned NumBits = VT.getSizeInBits();
10108 DebugLoc dl = Op.getDebugLoc();
10110 Op = Op.getOperand(0);
10111 if (VT == MVT::i8) {
10112 // Zero extend to i32 since there is not an i8 bsr.
10114 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
10117 // Issue a bsr (scan bits in reverse).
10118 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
10119 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
10121 // And xor with NumBits-1.
10122 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT));
10125 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
10129 SDValue X86TargetLowering::LowerCTTZ(SDValue Op, SelectionDAG &DAG) const {
10130 EVT VT = Op.getValueType();
10131 unsigned NumBits = VT.getSizeInBits();
10132 DebugLoc dl = Op.getDebugLoc();
10133 Op = Op.getOperand(0);
10135 // Issue a bsf (scan bits forward) which also sets EFLAGS.
10136 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
10137 Op = DAG.getNode(X86ISD::BSF, dl, VTs, Op);
10139 // If src is zero (i.e. bsf sets ZF), returns NumBits.
10142 DAG.getConstant(NumBits, VT),
10143 DAG.getConstant(X86::COND_E, MVT::i8),
10146 return DAG.getNode(X86ISD::CMOV, dl, VT, Ops, array_lengthof(Ops));
10149 // Lower256IntArith - Break a 256-bit integer operation into two new 128-bit
10150 // ones, and then concatenate the result back.
10151 static SDValue Lower256IntArith(SDValue Op, SelectionDAG &DAG) {
10152 EVT VT = Op.getValueType();
10154 assert(VT.getSizeInBits() == 256 && VT.isInteger() &&
10155 "Unsupported value type for operation");
10157 int NumElems = VT.getVectorNumElements();
10158 DebugLoc dl = Op.getDebugLoc();
10159 SDValue Idx0 = DAG.getConstant(0, MVT::i32);
10160 SDValue Idx1 = DAG.getConstant(NumElems/2, MVT::i32);
10162 // Extract the LHS vectors
10163 SDValue LHS = Op.getOperand(0);
10164 SDValue LHS1 = Extract128BitVector(LHS, Idx0, DAG, dl);
10165 SDValue LHS2 = Extract128BitVector(LHS, Idx1, DAG, dl);
10167 // Extract the RHS vectors
10168 SDValue RHS = Op.getOperand(1);
10169 SDValue RHS1 = Extract128BitVector(RHS, Idx0, DAG, dl);
10170 SDValue RHS2 = Extract128BitVector(RHS, Idx1, DAG, dl);
10172 MVT EltVT = VT.getVectorElementType().getSimpleVT();
10173 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
10175 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
10176 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1),
10177 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2));
10180 SDValue X86TargetLowering::LowerADD(SDValue Op, SelectionDAG &DAG) const {
10181 assert(Op.getValueType().getSizeInBits() == 256 &&
10182 Op.getValueType().isInteger() &&
10183 "Only handle AVX 256-bit vector integer operation");
10184 return Lower256IntArith(Op, DAG);
10187 SDValue X86TargetLowering::LowerSUB(SDValue Op, SelectionDAG &DAG) const {
10188 assert(Op.getValueType().getSizeInBits() == 256 &&
10189 Op.getValueType().isInteger() &&
10190 "Only handle AVX 256-bit vector integer operation");
10191 return Lower256IntArith(Op, DAG);
10194 SDValue X86TargetLowering::LowerMUL(SDValue Op, SelectionDAG &DAG) const {
10195 EVT VT = Op.getValueType();
10197 // Decompose 256-bit ops into smaller 128-bit ops.
10198 if (VT.getSizeInBits() == 256 && !Subtarget->hasAVX2())
10199 return Lower256IntArith(Op, DAG);
10201 assert((VT == MVT::v2i64 || VT == MVT::v4i64) &&
10202 "Only know how to lower V2I64/V4I64 multiply");
10204 DebugLoc dl = Op.getDebugLoc();
10206 // Ahi = psrlqi(a, 32);
10207 // Bhi = psrlqi(b, 32);
10209 // AloBlo = pmuludq(a, b);
10210 // AloBhi = pmuludq(a, Bhi);
10211 // AhiBlo = pmuludq(Ahi, b);
10213 // AloBhi = psllqi(AloBhi, 32);
10214 // AhiBlo = psllqi(AhiBlo, 32);
10215 // return AloBlo + AloBhi + AhiBlo;
10217 SDValue A = Op.getOperand(0);
10218 SDValue B = Op.getOperand(1);
10220 SDValue ShAmt = DAG.getConstant(32, MVT::i32);
10222 SDValue Ahi = DAG.getNode(X86ISD::VSRLI, dl, VT, A, ShAmt);
10223 SDValue Bhi = DAG.getNode(X86ISD::VSRLI, dl, VT, B, ShAmt);
10225 // Bit cast to 32-bit vectors for MULUDQ
10226 EVT MulVT = (VT == MVT::v2i64) ? MVT::v4i32 : MVT::v8i32;
10227 A = DAG.getNode(ISD::BITCAST, dl, MulVT, A);
10228 B = DAG.getNode(ISD::BITCAST, dl, MulVT, B);
10229 Ahi = DAG.getNode(ISD::BITCAST, dl, MulVT, Ahi);
10230 Bhi = DAG.getNode(ISD::BITCAST, dl, MulVT, Bhi);
10232 SDValue AloBlo = DAG.getNode(X86ISD::PMULUDQ, dl, VT, A, B);
10233 SDValue AloBhi = DAG.getNode(X86ISD::PMULUDQ, dl, VT, A, Bhi);
10234 SDValue AhiBlo = DAG.getNode(X86ISD::PMULUDQ, dl, VT, Ahi, B);
10236 AloBhi = DAG.getNode(X86ISD::VSHLI, dl, VT, AloBhi, ShAmt);
10237 AhiBlo = DAG.getNode(X86ISD::VSHLI, dl, VT, AhiBlo, ShAmt);
10239 SDValue Res = DAG.getNode(ISD::ADD, dl, VT, AloBlo, AloBhi);
10240 return DAG.getNode(ISD::ADD, dl, VT, Res, AhiBlo);
10243 SDValue X86TargetLowering::LowerShift(SDValue Op, SelectionDAG &DAG) const {
10245 EVT VT = Op.getValueType();
10246 DebugLoc dl = Op.getDebugLoc();
10247 SDValue R = Op.getOperand(0);
10248 SDValue Amt = Op.getOperand(1);
10249 LLVMContext *Context = DAG.getContext();
10251 if (!Subtarget->hasSSE2())
10254 // Optimize shl/srl/sra with constant shift amount.
10255 if (isSplatVector(Amt.getNode())) {
10256 SDValue SclrAmt = Amt->getOperand(0);
10257 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(SclrAmt)) {
10258 uint64_t ShiftAmt = C->getZExtValue();
10260 if (VT == MVT::v2i64 || VT == MVT::v4i32 || VT == MVT::v8i16 ||
10261 (Subtarget->hasAVX2() &&
10262 (VT == MVT::v4i64 || VT == MVT::v8i32 || VT == MVT::v16i16))) {
10263 if (Op.getOpcode() == ISD::SHL)
10264 return DAG.getNode(X86ISD::VSHLI, dl, VT, R,
10265 DAG.getConstant(ShiftAmt, MVT::i32));
10266 if (Op.getOpcode() == ISD::SRL)
10267 return DAG.getNode(X86ISD::VSRLI, dl, VT, R,
10268 DAG.getConstant(ShiftAmt, MVT::i32));
10269 if (Op.getOpcode() == ISD::SRA && VT != MVT::v2i64 && VT != MVT::v4i64)
10270 return DAG.getNode(X86ISD::VSRAI, dl, VT, R,
10271 DAG.getConstant(ShiftAmt, MVT::i32));
10274 if (VT == MVT::v16i8) {
10275 if (Op.getOpcode() == ISD::SHL) {
10276 // Make a large shift.
10277 SDValue SHL = DAG.getNode(X86ISD::VSHLI, dl, MVT::v8i16, R,
10278 DAG.getConstant(ShiftAmt, MVT::i32));
10279 SHL = DAG.getNode(ISD::BITCAST, dl, VT, SHL);
10280 // Zero out the rightmost bits.
10281 SmallVector<SDValue, 16> V(16,
10282 DAG.getConstant(uint8_t(-1U << ShiftAmt),
10284 return DAG.getNode(ISD::AND, dl, VT, SHL,
10285 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 16));
10287 if (Op.getOpcode() == ISD::SRL) {
10288 // Make a large shift.
10289 SDValue SRL = DAG.getNode(X86ISD::VSRLI, dl, MVT::v8i16, R,
10290 DAG.getConstant(ShiftAmt, MVT::i32));
10291 SRL = DAG.getNode(ISD::BITCAST, dl, VT, SRL);
10292 // Zero out the leftmost bits.
10293 SmallVector<SDValue, 16> V(16,
10294 DAG.getConstant(uint8_t(-1U) >> ShiftAmt,
10296 return DAG.getNode(ISD::AND, dl, VT, SRL,
10297 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 16));
10299 if (Op.getOpcode() == ISD::SRA) {
10300 if (ShiftAmt == 7) {
10301 // R s>> 7 === R s< 0
10302 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
10303 return DAG.getNode(X86ISD::PCMPGT, dl, VT, Zeros, R);
10306 // R s>> a === ((R u>> a) ^ m) - m
10307 SDValue Res = DAG.getNode(ISD::SRL, dl, VT, R, Amt);
10308 SmallVector<SDValue, 16> V(16, DAG.getConstant(128 >> ShiftAmt,
10310 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 16);
10311 Res = DAG.getNode(ISD::XOR, dl, VT, Res, Mask);
10312 Res = DAG.getNode(ISD::SUB, dl, VT, Res, Mask);
10317 if (Subtarget->hasAVX2() && VT == MVT::v32i8) {
10318 if (Op.getOpcode() == ISD::SHL) {
10319 // Make a large shift.
10320 SDValue SHL = DAG.getNode(X86ISD::VSHLI, dl, MVT::v16i16, R,
10321 DAG.getConstant(ShiftAmt, MVT::i32));
10322 SHL = DAG.getNode(ISD::BITCAST, dl, VT, SHL);
10323 // Zero out the rightmost bits.
10324 SmallVector<SDValue, 32> V(32,
10325 DAG.getConstant(uint8_t(-1U << ShiftAmt),
10327 return DAG.getNode(ISD::AND, dl, VT, SHL,
10328 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 32));
10330 if (Op.getOpcode() == ISD::SRL) {
10331 // Make a large shift.
10332 SDValue SRL = DAG.getNode(X86ISD::VSRLI, dl, MVT::v16i16, R,
10333 DAG.getConstant(ShiftAmt, MVT::i32));
10334 SRL = DAG.getNode(ISD::BITCAST, dl, VT, SRL);
10335 // Zero out the leftmost bits.
10336 SmallVector<SDValue, 32> V(32,
10337 DAG.getConstant(uint8_t(-1U) >> ShiftAmt,
10339 return DAG.getNode(ISD::AND, dl, VT, SRL,
10340 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 32));
10342 if (Op.getOpcode() == ISD::SRA) {
10343 if (ShiftAmt == 7) {
10344 // R s>> 7 === R s< 0
10345 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
10346 return DAG.getNode(X86ISD::PCMPGT, dl, VT, Zeros, R);
10349 // R s>> a === ((R u>> a) ^ m) - m
10350 SDValue Res = DAG.getNode(ISD::SRL, dl, VT, R, Amt);
10351 SmallVector<SDValue, 32> V(32, DAG.getConstant(128 >> ShiftAmt,
10353 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 32);
10354 Res = DAG.getNode(ISD::XOR, dl, VT, Res, Mask);
10355 Res = DAG.getNode(ISD::SUB, dl, VT, Res, Mask);
10362 // Lower SHL with variable shift amount.
10363 if (VT == MVT::v4i32 && Op->getOpcode() == ISD::SHL) {
10364 Op = DAG.getNode(X86ISD::VSHLI, dl, VT, Op.getOperand(1),
10365 DAG.getConstant(23, MVT::i32));
10367 const uint32_t CV[] = { 0x3f800000U, 0x3f800000U, 0x3f800000U, 0x3f800000U};
10368 Constant *C = ConstantDataVector::get(*Context, CV);
10369 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
10370 SDValue Addend = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
10371 MachinePointerInfo::getConstantPool(),
10372 false, false, false, 16);
10374 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Addend);
10375 Op = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, Op);
10376 Op = DAG.getNode(ISD::FP_TO_SINT, dl, VT, Op);
10377 return DAG.getNode(ISD::MUL, dl, VT, Op, R);
10379 if (VT == MVT::v16i8 && Op->getOpcode() == ISD::SHL) {
10380 assert(Subtarget->hasSSE2() && "Need SSE2 for pslli/pcmpeq.");
10383 Op = DAG.getNode(X86ISD::VSHLI, dl, MVT::v8i16, Op.getOperand(1),
10384 DAG.getConstant(5, MVT::i32));
10385 Op = DAG.getNode(ISD::BITCAST, dl, VT, Op);
10387 // Turn 'a' into a mask suitable for VSELECT
10388 SDValue VSelM = DAG.getConstant(0x80, VT);
10389 SDValue OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
10390 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
10392 SDValue CM1 = DAG.getConstant(0x0f, VT);
10393 SDValue CM2 = DAG.getConstant(0x3f, VT);
10395 // r = VSELECT(r, psllw(r & (char16)15, 4), a);
10396 SDValue M = DAG.getNode(ISD::AND, dl, VT, R, CM1);
10397 M = getTargetVShiftNode(X86ISD::VSHLI, dl, MVT::v8i16, M,
10398 DAG.getConstant(4, MVT::i32), DAG);
10399 M = DAG.getNode(ISD::BITCAST, dl, VT, M);
10400 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel, M, R);
10403 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op);
10404 OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
10405 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
10407 // r = VSELECT(r, psllw(r & (char16)63, 2), a);
10408 M = DAG.getNode(ISD::AND, dl, VT, R, CM2);
10409 M = getTargetVShiftNode(X86ISD::VSHLI, dl, MVT::v8i16, M,
10410 DAG.getConstant(2, MVT::i32), DAG);
10411 M = DAG.getNode(ISD::BITCAST, dl, VT, M);
10412 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel, M, R);
10415 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op);
10416 OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
10417 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
10419 // return VSELECT(r, r+r, a);
10420 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel,
10421 DAG.getNode(ISD::ADD, dl, VT, R, R), R);
10425 // Decompose 256-bit shifts into smaller 128-bit shifts.
10426 if (VT.getSizeInBits() == 256) {
10427 unsigned NumElems = VT.getVectorNumElements();
10428 MVT EltVT = VT.getVectorElementType().getSimpleVT();
10429 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
10431 // Extract the two vectors
10432 SDValue V1 = Extract128BitVector(R, DAG.getConstant(0, MVT::i32), DAG, dl);
10433 SDValue V2 = Extract128BitVector(R, DAG.getConstant(NumElems/2, MVT::i32),
10436 // Recreate the shift amount vectors
10437 SDValue Amt1, Amt2;
10438 if (Amt.getOpcode() == ISD::BUILD_VECTOR) {
10439 // Constant shift amount
10440 SmallVector<SDValue, 4> Amt1Csts;
10441 SmallVector<SDValue, 4> Amt2Csts;
10442 for (unsigned i = 0; i != NumElems/2; ++i)
10443 Amt1Csts.push_back(Amt->getOperand(i));
10444 for (unsigned i = NumElems/2; i != NumElems; ++i)
10445 Amt2Csts.push_back(Amt->getOperand(i));
10447 Amt1 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT,
10448 &Amt1Csts[0], NumElems/2);
10449 Amt2 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT,
10450 &Amt2Csts[0], NumElems/2);
10452 // Variable shift amount
10453 Amt1 = Extract128BitVector(Amt, DAG.getConstant(0, MVT::i32), DAG, dl);
10454 Amt2 = Extract128BitVector(Amt, DAG.getConstant(NumElems/2, MVT::i32),
10458 // Issue new vector shifts for the smaller types
10459 V1 = DAG.getNode(Op.getOpcode(), dl, NewVT, V1, Amt1);
10460 V2 = DAG.getNode(Op.getOpcode(), dl, NewVT, V2, Amt2);
10462 // Concatenate the result back
10463 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, V1, V2);
10469 SDValue X86TargetLowering::LowerXALUO(SDValue Op, SelectionDAG &DAG) const {
10470 // Lower the "add/sub/mul with overflow" instruction into a regular ins plus
10471 // a "setcc" instruction that checks the overflow flag. The "brcond" lowering
10472 // looks for this combo and may remove the "setcc" instruction if the "setcc"
10473 // has only one use.
10474 SDNode *N = Op.getNode();
10475 SDValue LHS = N->getOperand(0);
10476 SDValue RHS = N->getOperand(1);
10477 unsigned BaseOp = 0;
10479 DebugLoc DL = Op.getDebugLoc();
10480 switch (Op.getOpcode()) {
10481 default: llvm_unreachable("Unknown ovf instruction!");
10483 // A subtract of one will be selected as a INC. Note that INC doesn't
10484 // set CF, so we can't do this for UADDO.
10485 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
10487 BaseOp = X86ISD::INC;
10488 Cond = X86::COND_O;
10491 BaseOp = X86ISD::ADD;
10492 Cond = X86::COND_O;
10495 BaseOp = X86ISD::ADD;
10496 Cond = X86::COND_B;
10499 // A subtract of one will be selected as a DEC. Note that DEC doesn't
10500 // set CF, so we can't do this for USUBO.
10501 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
10503 BaseOp = X86ISD::DEC;
10504 Cond = X86::COND_O;
10507 BaseOp = X86ISD::SUB;
10508 Cond = X86::COND_O;
10511 BaseOp = X86ISD::SUB;
10512 Cond = X86::COND_B;
10515 BaseOp = X86ISD::SMUL;
10516 Cond = X86::COND_O;
10518 case ISD::UMULO: { // i64, i8 = umulo lhs, rhs --> i64, i64, i32 umul lhs,rhs
10519 SDVTList VTs = DAG.getVTList(N->getValueType(0), N->getValueType(0),
10521 SDValue Sum = DAG.getNode(X86ISD::UMUL, DL, VTs, LHS, RHS);
10524 DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
10525 DAG.getConstant(X86::COND_O, MVT::i32),
10526 SDValue(Sum.getNode(), 2));
10528 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
10532 // Also sets EFLAGS.
10533 SDVTList VTs = DAG.getVTList(N->getValueType(0), MVT::i32);
10534 SDValue Sum = DAG.getNode(BaseOp, DL, VTs, LHS, RHS);
10537 DAG.getNode(X86ISD::SETCC, DL, N->getValueType(1),
10538 DAG.getConstant(Cond, MVT::i32),
10539 SDValue(Sum.getNode(), 1));
10541 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
10544 SDValue X86TargetLowering::LowerSIGN_EXTEND_INREG(SDValue Op,
10545 SelectionDAG &DAG) const {
10546 DebugLoc dl = Op.getDebugLoc();
10547 EVT ExtraVT = cast<VTSDNode>(Op.getOperand(1))->getVT();
10548 EVT VT = Op.getValueType();
10550 if (!Subtarget->hasSSE2() || !VT.isVector())
10553 unsigned BitsDiff = VT.getScalarType().getSizeInBits() -
10554 ExtraVT.getScalarType().getSizeInBits();
10555 SDValue ShAmt = DAG.getConstant(BitsDiff, MVT::i32);
10557 switch (VT.getSimpleVT().SimpleTy) {
10558 default: return SDValue();
10561 if (!Subtarget->hasAVX())
10563 if (!Subtarget->hasAVX2()) {
10564 // needs to be split
10565 int NumElems = VT.getVectorNumElements();
10566 SDValue Idx0 = DAG.getConstant(0, MVT::i32);
10567 SDValue Idx1 = DAG.getConstant(NumElems/2, MVT::i32);
10569 // Extract the LHS vectors
10570 SDValue LHS = Op.getOperand(0);
10571 SDValue LHS1 = Extract128BitVector(LHS, Idx0, DAG, dl);
10572 SDValue LHS2 = Extract128BitVector(LHS, Idx1, DAG, dl);
10574 MVT EltVT = VT.getVectorElementType().getSimpleVT();
10575 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
10577 EVT ExtraEltVT = ExtraVT.getVectorElementType();
10578 int ExtraNumElems = ExtraVT.getVectorNumElements();
10579 ExtraVT = EVT::getVectorVT(*DAG.getContext(), ExtraEltVT,
10581 SDValue Extra = DAG.getValueType(ExtraVT);
10583 LHS1 = DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, Extra);
10584 LHS2 = DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, Extra);
10586 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, LHS1, LHS2);;
10591 SDValue Tmp1 = getTargetVShiftNode(X86ISD::VSHLI, dl, VT,
10592 Op.getOperand(0), ShAmt, DAG);
10593 return getTargetVShiftNode(X86ISD::VSRAI, dl, VT, Tmp1, ShAmt, DAG);
10599 SDValue X86TargetLowering::LowerMEMBARRIER(SDValue Op, SelectionDAG &DAG) const{
10600 DebugLoc dl = Op.getDebugLoc();
10602 // Go ahead and emit the fence on x86-64 even if we asked for no-sse2.
10603 // There isn't any reason to disable it if the target processor supports it.
10604 if (!Subtarget->hasSSE2() && !Subtarget->is64Bit()) {
10605 SDValue Chain = Op.getOperand(0);
10606 SDValue Zero = DAG.getConstant(0, MVT::i32);
10608 DAG.getRegister(X86::ESP, MVT::i32), // Base
10609 DAG.getTargetConstant(1, MVT::i8), // Scale
10610 DAG.getRegister(0, MVT::i32), // Index
10611 DAG.getTargetConstant(0, MVT::i32), // Disp
10612 DAG.getRegister(0, MVT::i32), // Segment.
10617 DAG.getMachineNode(X86::OR32mrLocked, dl, MVT::Other, Ops,
10618 array_lengthof(Ops));
10619 return SDValue(Res, 0);
10622 unsigned isDev = cast<ConstantSDNode>(Op.getOperand(5))->getZExtValue();
10624 return DAG.getNode(X86ISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0));
10626 unsigned Op1 = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
10627 unsigned Op2 = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue();
10628 unsigned Op3 = cast<ConstantSDNode>(Op.getOperand(3))->getZExtValue();
10629 unsigned Op4 = cast<ConstantSDNode>(Op.getOperand(4))->getZExtValue();
10631 // def : Pat<(membarrier (i8 0), (i8 0), (i8 0), (i8 1), (i8 1)), (SFENCE)>;
10632 if (!Op1 && !Op2 && !Op3 && Op4)
10633 return DAG.getNode(X86ISD::SFENCE, dl, MVT::Other, Op.getOperand(0));
10635 // def : Pat<(membarrier (i8 1), (i8 0), (i8 0), (i8 0), (i8 1)), (LFENCE)>;
10636 if (Op1 && !Op2 && !Op3 && !Op4)
10637 return DAG.getNode(X86ISD::LFENCE, dl, MVT::Other, Op.getOperand(0));
10639 // def : Pat<(membarrier (i8 imm), (i8 imm), (i8 imm), (i8 imm), (i8 1)),
10641 return DAG.getNode(X86ISD::MFENCE, dl, MVT::Other, Op.getOperand(0));
10644 SDValue X86TargetLowering::LowerATOMIC_FENCE(SDValue Op,
10645 SelectionDAG &DAG) const {
10646 DebugLoc dl = Op.getDebugLoc();
10647 AtomicOrdering FenceOrdering = static_cast<AtomicOrdering>(
10648 cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue());
10649 SynchronizationScope FenceScope = static_cast<SynchronizationScope>(
10650 cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue());
10652 // The only fence that needs an instruction is a sequentially-consistent
10653 // cross-thread fence.
10654 if (FenceOrdering == SequentiallyConsistent && FenceScope == CrossThread) {
10655 // Use mfence if we have SSE2 or we're on x86-64 (even if we asked for
10656 // no-sse2). There isn't any reason to disable it if the target processor
10658 if (Subtarget->hasSSE2() || Subtarget->is64Bit())
10659 return DAG.getNode(X86ISD::MFENCE, dl, MVT::Other, Op.getOperand(0));
10661 SDValue Chain = Op.getOperand(0);
10662 SDValue Zero = DAG.getConstant(0, MVT::i32);
10664 DAG.getRegister(X86::ESP, MVT::i32), // Base
10665 DAG.getTargetConstant(1, MVT::i8), // Scale
10666 DAG.getRegister(0, MVT::i32), // Index
10667 DAG.getTargetConstant(0, MVT::i32), // Disp
10668 DAG.getRegister(0, MVT::i32), // Segment.
10673 DAG.getMachineNode(X86::OR32mrLocked, dl, MVT::Other, Ops,
10674 array_lengthof(Ops));
10675 return SDValue(Res, 0);
10678 // MEMBARRIER is a compiler barrier; it codegens to a no-op.
10679 return DAG.getNode(X86ISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0));
10683 SDValue X86TargetLowering::LowerCMP_SWAP(SDValue Op, SelectionDAG &DAG) const {
10684 EVT T = Op.getValueType();
10685 DebugLoc DL = Op.getDebugLoc();
10688 switch(T.getSimpleVT().SimpleTy) {
10689 default: llvm_unreachable("Invalid value type!");
10690 case MVT::i8: Reg = X86::AL; size = 1; break;
10691 case MVT::i16: Reg = X86::AX; size = 2; break;
10692 case MVT::i32: Reg = X86::EAX; size = 4; break;
10694 assert(Subtarget->is64Bit() && "Node not type legal!");
10695 Reg = X86::RAX; size = 8;
10698 SDValue cpIn = DAG.getCopyToReg(Op.getOperand(0), DL, Reg,
10699 Op.getOperand(2), SDValue());
10700 SDValue Ops[] = { cpIn.getValue(0),
10703 DAG.getTargetConstant(size, MVT::i8),
10704 cpIn.getValue(1) };
10705 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
10706 MachineMemOperand *MMO = cast<AtomicSDNode>(Op)->getMemOperand();
10707 SDValue Result = DAG.getMemIntrinsicNode(X86ISD::LCMPXCHG_DAG, DL, Tys,
10710 DAG.getCopyFromReg(Result.getValue(0), DL, Reg, T, Result.getValue(1));
10714 SDValue X86TargetLowering::LowerREADCYCLECOUNTER(SDValue Op,
10715 SelectionDAG &DAG) const {
10716 assert(Subtarget->is64Bit() && "Result not type legalized?");
10717 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
10718 SDValue TheChain = Op.getOperand(0);
10719 DebugLoc dl = Op.getDebugLoc();
10720 SDValue rd = DAG.getNode(X86ISD::RDTSC_DAG, dl, Tys, &TheChain, 1);
10721 SDValue rax = DAG.getCopyFromReg(rd, dl, X86::RAX, MVT::i64, rd.getValue(1));
10722 SDValue rdx = DAG.getCopyFromReg(rax.getValue(1), dl, X86::RDX, MVT::i64,
10724 SDValue Tmp = DAG.getNode(ISD::SHL, dl, MVT::i64, rdx,
10725 DAG.getConstant(32, MVT::i8));
10727 DAG.getNode(ISD::OR, dl, MVT::i64, rax, Tmp),
10730 return DAG.getMergeValues(Ops, 2, dl);
10733 SDValue X86TargetLowering::LowerBITCAST(SDValue Op,
10734 SelectionDAG &DAG) const {
10735 EVT SrcVT = Op.getOperand(0).getValueType();
10736 EVT DstVT = Op.getValueType();
10737 assert(Subtarget->is64Bit() && !Subtarget->hasSSE2() &&
10738 Subtarget->hasMMX() && "Unexpected custom BITCAST");
10739 assert((DstVT == MVT::i64 ||
10740 (DstVT.isVector() && DstVT.getSizeInBits()==64)) &&
10741 "Unexpected custom BITCAST");
10742 // i64 <=> MMX conversions are Legal.
10743 if (SrcVT==MVT::i64 && DstVT.isVector())
10745 if (DstVT==MVT::i64 && SrcVT.isVector())
10747 // MMX <=> MMX conversions are Legal.
10748 if (SrcVT.isVector() && DstVT.isVector())
10750 // All other conversions need to be expanded.
10754 SDValue X86TargetLowering::LowerLOAD_SUB(SDValue Op, SelectionDAG &DAG) const {
10755 SDNode *Node = Op.getNode();
10756 DebugLoc dl = Node->getDebugLoc();
10757 EVT T = Node->getValueType(0);
10758 SDValue negOp = DAG.getNode(ISD::SUB, dl, T,
10759 DAG.getConstant(0, T), Node->getOperand(2));
10760 return DAG.getAtomic(ISD::ATOMIC_LOAD_ADD, dl,
10761 cast<AtomicSDNode>(Node)->getMemoryVT(),
10762 Node->getOperand(0),
10763 Node->getOperand(1), negOp,
10764 cast<AtomicSDNode>(Node)->getSrcValue(),
10765 cast<AtomicSDNode>(Node)->getAlignment(),
10766 cast<AtomicSDNode>(Node)->getOrdering(),
10767 cast<AtomicSDNode>(Node)->getSynchScope());
10770 static SDValue LowerATOMIC_STORE(SDValue Op, SelectionDAG &DAG) {
10771 SDNode *Node = Op.getNode();
10772 DebugLoc dl = Node->getDebugLoc();
10773 EVT VT = cast<AtomicSDNode>(Node)->getMemoryVT();
10775 // Convert seq_cst store -> xchg
10776 // Convert wide store -> swap (-> cmpxchg8b/cmpxchg16b)
10777 // FIXME: On 32-bit, store -> fist or movq would be more efficient
10778 // (The only way to get a 16-byte store is cmpxchg16b)
10779 // FIXME: 16-byte ATOMIC_SWAP isn't actually hooked up at the moment.
10780 if (cast<AtomicSDNode>(Node)->getOrdering() == SequentiallyConsistent ||
10781 !DAG.getTargetLoweringInfo().isTypeLegal(VT)) {
10782 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_SWAP, dl,
10783 cast<AtomicSDNode>(Node)->getMemoryVT(),
10784 Node->getOperand(0),
10785 Node->getOperand(1), Node->getOperand(2),
10786 cast<AtomicSDNode>(Node)->getMemOperand(),
10787 cast<AtomicSDNode>(Node)->getOrdering(),
10788 cast<AtomicSDNode>(Node)->getSynchScope());
10789 return Swap.getValue(1);
10791 // Other atomic stores have a simple pattern.
10795 static SDValue LowerADDC_ADDE_SUBC_SUBE(SDValue Op, SelectionDAG &DAG) {
10796 EVT VT = Op.getNode()->getValueType(0);
10798 // Let legalize expand this if it isn't a legal type yet.
10799 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
10802 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
10805 bool ExtraOp = false;
10806 switch (Op.getOpcode()) {
10807 default: llvm_unreachable("Invalid code");
10808 case ISD::ADDC: Opc = X86ISD::ADD; break;
10809 case ISD::ADDE: Opc = X86ISD::ADC; ExtraOp = true; break;
10810 case ISD::SUBC: Opc = X86ISD::SUB; break;
10811 case ISD::SUBE: Opc = X86ISD::SBB; ExtraOp = true; break;
10815 return DAG.getNode(Opc, Op->getDebugLoc(), VTs, Op.getOperand(0),
10817 return DAG.getNode(Opc, Op->getDebugLoc(), VTs, Op.getOperand(0),
10818 Op.getOperand(1), Op.getOperand(2));
10821 /// LowerOperation - Provide custom lowering hooks for some operations.
10823 SDValue X86TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
10824 switch (Op.getOpcode()) {
10825 default: llvm_unreachable("Should not custom lower this!");
10826 case ISD::SIGN_EXTEND_INREG: return LowerSIGN_EXTEND_INREG(Op,DAG);
10827 case ISD::MEMBARRIER: return LowerMEMBARRIER(Op,DAG);
10828 case ISD::ATOMIC_FENCE: return LowerATOMIC_FENCE(Op,DAG);
10829 case ISD::ATOMIC_CMP_SWAP: return LowerCMP_SWAP(Op,DAG);
10830 case ISD::ATOMIC_LOAD_SUB: return LowerLOAD_SUB(Op,DAG);
10831 case ISD::ATOMIC_STORE: return LowerATOMIC_STORE(Op,DAG);
10832 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
10833 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG);
10834 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
10835 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
10836 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG);
10837 case ISD::EXTRACT_SUBVECTOR: return LowerEXTRACT_SUBVECTOR(Op, DAG);
10838 case ISD::INSERT_SUBVECTOR: return LowerINSERT_SUBVECTOR(Op, DAG);
10839 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
10840 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
10841 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
10842 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
10843 case ISD::ExternalSymbol: return LowerExternalSymbol(Op, DAG);
10844 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
10845 case ISD::SHL_PARTS:
10846 case ISD::SRA_PARTS:
10847 case ISD::SRL_PARTS: return LowerShiftParts(Op, DAG);
10848 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG);
10849 case ISD::UINT_TO_FP: return LowerUINT_TO_FP(Op, DAG);
10850 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG);
10851 case ISD::FP_TO_UINT: return LowerFP_TO_UINT(Op, DAG);
10852 case ISD::FABS: return LowerFABS(Op, DAG);
10853 case ISD::FNEG: return LowerFNEG(Op, DAG);
10854 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG);
10855 case ISD::FGETSIGN: return LowerFGETSIGN(Op, DAG);
10856 case ISD::SETCC: return LowerSETCC(Op, DAG);
10857 case ISD::SELECT: return LowerSELECT(Op, DAG);
10858 case ISD::BRCOND: return LowerBRCOND(Op, DAG);
10859 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
10860 case ISD::VASTART: return LowerVASTART(Op, DAG);
10861 case ISD::VAARG: return LowerVAARG(Op, DAG);
10862 case ISD::VACOPY: return LowerVACOPY(Op, DAG);
10863 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
10864 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
10865 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
10866 case ISD::FRAME_TO_ARGS_OFFSET:
10867 return LowerFRAME_TO_ARGS_OFFSET(Op, DAG);
10868 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
10869 case ISD::EH_RETURN: return LowerEH_RETURN(Op, DAG);
10870 case ISD::INIT_TRAMPOLINE: return LowerINIT_TRAMPOLINE(Op, DAG);
10871 case ISD::ADJUST_TRAMPOLINE: return LowerADJUST_TRAMPOLINE(Op, DAG);
10872 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
10873 case ISD::CTLZ: return LowerCTLZ(Op, DAG);
10874 case ISD::CTLZ_ZERO_UNDEF: return LowerCTLZ_ZERO_UNDEF(Op, DAG);
10875 case ISD::CTTZ: return LowerCTTZ(Op, DAG);
10876 case ISD::MUL: return LowerMUL(Op, DAG);
10879 case ISD::SHL: return LowerShift(Op, DAG);
10885 case ISD::UMULO: return LowerXALUO(Op, DAG);
10886 case ISD::READCYCLECOUNTER: return LowerREADCYCLECOUNTER(Op, DAG);
10887 case ISD::BITCAST: return LowerBITCAST(Op, DAG);
10891 case ISD::SUBE: return LowerADDC_ADDE_SUBC_SUBE(Op, DAG);
10892 case ISD::ADD: return LowerADD(Op, DAG);
10893 case ISD::SUB: return LowerSUB(Op, DAG);
10897 static void ReplaceATOMIC_LOAD(SDNode *Node,
10898 SmallVectorImpl<SDValue> &Results,
10899 SelectionDAG &DAG) {
10900 DebugLoc dl = Node->getDebugLoc();
10901 EVT VT = cast<AtomicSDNode>(Node)->getMemoryVT();
10903 // Convert wide load -> cmpxchg8b/cmpxchg16b
10904 // FIXME: On 32-bit, load -> fild or movq would be more efficient
10905 // (The only way to get a 16-byte load is cmpxchg16b)
10906 // FIXME: 16-byte ATOMIC_CMP_SWAP isn't actually hooked up at the moment.
10907 SDValue Zero = DAG.getConstant(0, VT);
10908 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_CMP_SWAP, dl, VT,
10909 Node->getOperand(0),
10910 Node->getOperand(1), Zero, Zero,
10911 cast<AtomicSDNode>(Node)->getMemOperand(),
10912 cast<AtomicSDNode>(Node)->getOrdering(),
10913 cast<AtomicSDNode>(Node)->getSynchScope());
10914 Results.push_back(Swap.getValue(0));
10915 Results.push_back(Swap.getValue(1));
10918 void X86TargetLowering::
10919 ReplaceATOMIC_BINARY_64(SDNode *Node, SmallVectorImpl<SDValue>&Results,
10920 SelectionDAG &DAG, unsigned NewOp) const {
10921 DebugLoc dl = Node->getDebugLoc();
10922 assert (Node->getValueType(0) == MVT::i64 &&
10923 "Only know how to expand i64 atomics");
10925 SDValue Chain = Node->getOperand(0);
10926 SDValue In1 = Node->getOperand(1);
10927 SDValue In2L = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
10928 Node->getOperand(2), DAG.getIntPtrConstant(0));
10929 SDValue In2H = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
10930 Node->getOperand(2), DAG.getIntPtrConstant(1));
10931 SDValue Ops[] = { Chain, In1, In2L, In2H };
10932 SDVTList Tys = DAG.getVTList(MVT::i32, MVT::i32, MVT::Other);
10934 DAG.getMemIntrinsicNode(NewOp, dl, Tys, Ops, 4, MVT::i64,
10935 cast<MemSDNode>(Node)->getMemOperand());
10936 SDValue OpsF[] = { Result.getValue(0), Result.getValue(1)};
10937 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, OpsF, 2));
10938 Results.push_back(Result.getValue(2));
10941 /// ReplaceNodeResults - Replace a node with an illegal result type
10942 /// with a new node built out of custom code.
10943 void X86TargetLowering::ReplaceNodeResults(SDNode *N,
10944 SmallVectorImpl<SDValue>&Results,
10945 SelectionDAG &DAG) const {
10946 DebugLoc dl = N->getDebugLoc();
10947 switch (N->getOpcode()) {
10949 llvm_unreachable("Do not know how to custom type legalize this operation!");
10950 case ISD::SIGN_EXTEND_INREG:
10955 // We don't want to expand or promote these.
10957 case ISD::FP_TO_SINT:
10958 case ISD::FP_TO_UINT: {
10959 bool IsSigned = N->getOpcode() == ISD::FP_TO_SINT;
10961 if (!IsSigned && !isIntegerTypeFTOL(SDValue(N, 0).getValueType()))
10964 std::pair<SDValue,SDValue> Vals =
10965 FP_TO_INTHelper(SDValue(N, 0), DAG, IsSigned, /*IsReplace=*/ true);
10966 SDValue FIST = Vals.first, StackSlot = Vals.second;
10967 if (FIST.getNode() != 0) {
10968 EVT VT = N->getValueType(0);
10969 // Return a load from the stack slot.
10970 if (StackSlot.getNode() != 0)
10971 Results.push_back(DAG.getLoad(VT, dl, FIST, StackSlot,
10972 MachinePointerInfo(),
10973 false, false, false, 0));
10975 Results.push_back(FIST);
10979 case ISD::READCYCLECOUNTER: {
10980 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
10981 SDValue TheChain = N->getOperand(0);
10982 SDValue rd = DAG.getNode(X86ISD::RDTSC_DAG, dl, Tys, &TheChain, 1);
10983 SDValue eax = DAG.getCopyFromReg(rd, dl, X86::EAX, MVT::i32,
10985 SDValue edx = DAG.getCopyFromReg(eax.getValue(1), dl, X86::EDX, MVT::i32,
10987 // Use a buildpair to merge the two 32-bit values into a 64-bit one.
10988 SDValue Ops[] = { eax, edx };
10989 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Ops, 2));
10990 Results.push_back(edx.getValue(1));
10993 case ISD::ATOMIC_CMP_SWAP: {
10994 EVT T = N->getValueType(0);
10995 assert((T == MVT::i64 || T == MVT::i128) && "can only expand cmpxchg pair");
10996 bool Regs64bit = T == MVT::i128;
10997 EVT HalfT = Regs64bit ? MVT::i64 : MVT::i32;
10998 SDValue cpInL, cpInH;
10999 cpInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2),
11000 DAG.getConstant(0, HalfT));
11001 cpInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2),
11002 DAG.getConstant(1, HalfT));
11003 cpInL = DAG.getCopyToReg(N->getOperand(0), dl,
11004 Regs64bit ? X86::RAX : X86::EAX,
11006 cpInH = DAG.getCopyToReg(cpInL.getValue(0), dl,
11007 Regs64bit ? X86::RDX : X86::EDX,
11008 cpInH, cpInL.getValue(1));
11009 SDValue swapInL, swapInH;
11010 swapInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3),
11011 DAG.getConstant(0, HalfT));
11012 swapInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3),
11013 DAG.getConstant(1, HalfT));
11014 swapInL = DAG.getCopyToReg(cpInH.getValue(0), dl,
11015 Regs64bit ? X86::RBX : X86::EBX,
11016 swapInL, cpInH.getValue(1));
11017 swapInH = DAG.getCopyToReg(swapInL.getValue(0), dl,
11018 Regs64bit ? X86::RCX : X86::ECX,
11019 swapInH, swapInL.getValue(1));
11020 SDValue Ops[] = { swapInH.getValue(0),
11022 swapInH.getValue(1) };
11023 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
11024 MachineMemOperand *MMO = cast<AtomicSDNode>(N)->getMemOperand();
11025 unsigned Opcode = Regs64bit ? X86ISD::LCMPXCHG16_DAG :
11026 X86ISD::LCMPXCHG8_DAG;
11027 SDValue Result = DAG.getMemIntrinsicNode(Opcode, dl, Tys,
11029 SDValue cpOutL = DAG.getCopyFromReg(Result.getValue(0), dl,
11030 Regs64bit ? X86::RAX : X86::EAX,
11031 HalfT, Result.getValue(1));
11032 SDValue cpOutH = DAG.getCopyFromReg(cpOutL.getValue(1), dl,
11033 Regs64bit ? X86::RDX : X86::EDX,
11034 HalfT, cpOutL.getValue(2));
11035 SDValue OpsF[] = { cpOutL.getValue(0), cpOutH.getValue(0)};
11036 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, T, OpsF, 2));
11037 Results.push_back(cpOutH.getValue(1));
11040 case ISD::ATOMIC_LOAD_ADD:
11041 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMADD64_DAG);
11043 case ISD::ATOMIC_LOAD_AND:
11044 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMAND64_DAG);
11046 case ISD::ATOMIC_LOAD_NAND:
11047 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMNAND64_DAG);
11049 case ISD::ATOMIC_LOAD_OR:
11050 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMOR64_DAG);
11052 case ISD::ATOMIC_LOAD_SUB:
11053 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMSUB64_DAG);
11055 case ISD::ATOMIC_LOAD_XOR:
11056 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMXOR64_DAG);
11058 case ISD::ATOMIC_SWAP:
11059 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMSWAP64_DAG);
11061 case ISD::ATOMIC_LOAD:
11062 ReplaceATOMIC_LOAD(N, Results, DAG);
11066 const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
11068 default: return NULL;
11069 case X86ISD::BSF: return "X86ISD::BSF";
11070 case X86ISD::BSR: return "X86ISD::BSR";
11071 case X86ISD::SHLD: return "X86ISD::SHLD";
11072 case X86ISD::SHRD: return "X86ISD::SHRD";
11073 case X86ISD::FAND: return "X86ISD::FAND";
11074 case X86ISD::FOR: return "X86ISD::FOR";
11075 case X86ISD::FXOR: return "X86ISD::FXOR";
11076 case X86ISD::FSRL: return "X86ISD::FSRL";
11077 case X86ISD::FILD: return "X86ISD::FILD";
11078 case X86ISD::FILD_FLAG: return "X86ISD::FILD_FLAG";
11079 case X86ISD::FP_TO_INT16_IN_MEM: return "X86ISD::FP_TO_INT16_IN_MEM";
11080 case X86ISD::FP_TO_INT32_IN_MEM: return "X86ISD::FP_TO_INT32_IN_MEM";
11081 case X86ISD::FP_TO_INT64_IN_MEM: return "X86ISD::FP_TO_INT64_IN_MEM";
11082 case X86ISD::FLD: return "X86ISD::FLD";
11083 case X86ISD::FST: return "X86ISD::FST";
11084 case X86ISD::CALL: return "X86ISD::CALL";
11085 case X86ISD::RDTSC_DAG: return "X86ISD::RDTSC_DAG";
11086 case X86ISD::BT: return "X86ISD::BT";
11087 case X86ISD::CMP: return "X86ISD::CMP";
11088 case X86ISD::COMI: return "X86ISD::COMI";
11089 case X86ISD::UCOMI: return "X86ISD::UCOMI";
11090 case X86ISD::SETCC: return "X86ISD::SETCC";
11091 case X86ISD::SETCC_CARRY: return "X86ISD::SETCC_CARRY";
11092 case X86ISD::FSETCCsd: return "X86ISD::FSETCCsd";
11093 case X86ISD::FSETCCss: return "X86ISD::FSETCCss";
11094 case X86ISD::CMOV: return "X86ISD::CMOV";
11095 case X86ISD::BRCOND: return "X86ISD::BRCOND";
11096 case X86ISD::RET_FLAG: return "X86ISD::RET_FLAG";
11097 case X86ISD::REP_STOS: return "X86ISD::REP_STOS";
11098 case X86ISD::REP_MOVS: return "X86ISD::REP_MOVS";
11099 case X86ISD::GlobalBaseReg: return "X86ISD::GlobalBaseReg";
11100 case X86ISD::Wrapper: return "X86ISD::Wrapper";
11101 case X86ISD::WrapperRIP: return "X86ISD::WrapperRIP";
11102 case X86ISD::PEXTRB: return "X86ISD::PEXTRB";
11103 case X86ISD::PEXTRW: return "X86ISD::PEXTRW";
11104 case X86ISD::INSERTPS: return "X86ISD::INSERTPS";
11105 case X86ISD::PINSRB: return "X86ISD::PINSRB";
11106 case X86ISD::PINSRW: return "X86ISD::PINSRW";
11107 case X86ISD::PSHUFB: return "X86ISD::PSHUFB";
11108 case X86ISD::ANDNP: return "X86ISD::ANDNP";
11109 case X86ISD::PSIGN: return "X86ISD::PSIGN";
11110 case X86ISD::BLENDV: return "X86ISD::BLENDV";
11111 case X86ISD::BLENDPW: return "X86ISD::BLENDPW";
11112 case X86ISD::BLENDPS: return "X86ISD::BLENDPS";
11113 case X86ISD::BLENDPD: return "X86ISD::BLENDPD";
11114 case X86ISD::HADD: return "X86ISD::HADD";
11115 case X86ISD::HSUB: return "X86ISD::HSUB";
11116 case X86ISD::FHADD: return "X86ISD::FHADD";
11117 case X86ISD::FHSUB: return "X86ISD::FHSUB";
11118 case X86ISD::FMAX: return "X86ISD::FMAX";
11119 case X86ISD::FMIN: return "X86ISD::FMIN";
11120 case X86ISD::FRSQRT: return "X86ISD::FRSQRT";
11121 case X86ISD::FRCP: return "X86ISD::FRCP";
11122 case X86ISD::TLSADDR: return "X86ISD::TLSADDR";
11123 case X86ISD::TLSCALL: return "X86ISD::TLSCALL";
11124 case X86ISD::EH_RETURN: return "X86ISD::EH_RETURN";
11125 case X86ISD::TC_RETURN: return "X86ISD::TC_RETURN";
11126 case X86ISD::FNSTCW16m: return "X86ISD::FNSTCW16m";
11127 case X86ISD::LCMPXCHG_DAG: return "X86ISD::LCMPXCHG_DAG";
11128 case X86ISD::LCMPXCHG8_DAG: return "X86ISD::LCMPXCHG8_DAG";
11129 case X86ISD::ATOMADD64_DAG: return "X86ISD::ATOMADD64_DAG";
11130 case X86ISD::ATOMSUB64_DAG: return "X86ISD::ATOMSUB64_DAG";
11131 case X86ISD::ATOMOR64_DAG: return "X86ISD::ATOMOR64_DAG";
11132 case X86ISD::ATOMXOR64_DAG: return "X86ISD::ATOMXOR64_DAG";
11133 case X86ISD::ATOMAND64_DAG: return "X86ISD::ATOMAND64_DAG";
11134 case X86ISD::ATOMNAND64_DAG: return "X86ISD::ATOMNAND64_DAG";
11135 case X86ISD::VZEXT_MOVL: return "X86ISD::VZEXT_MOVL";
11136 case X86ISD::VZEXT_LOAD: return "X86ISD::VZEXT_LOAD";
11137 case X86ISD::VSHLDQ: return "X86ISD::VSHLDQ";
11138 case X86ISD::VSRLDQ: return "X86ISD::VSRLDQ";
11139 case X86ISD::VSHL: return "X86ISD::VSHL";
11140 case X86ISD::VSRL: return "X86ISD::VSRL";
11141 case X86ISD::VSRA: return "X86ISD::VSRA";
11142 case X86ISD::VSHLI: return "X86ISD::VSHLI";
11143 case X86ISD::VSRLI: return "X86ISD::VSRLI";
11144 case X86ISD::VSRAI: return "X86ISD::VSRAI";
11145 case X86ISD::CMPP: return "X86ISD::CMPP";
11146 case X86ISD::PCMPEQ: return "X86ISD::PCMPEQ";
11147 case X86ISD::PCMPGT: return "X86ISD::PCMPGT";
11148 case X86ISD::ADD: return "X86ISD::ADD";
11149 case X86ISD::SUB: return "X86ISD::SUB";
11150 case X86ISD::ADC: return "X86ISD::ADC";
11151 case X86ISD::SBB: return "X86ISD::SBB";
11152 case X86ISD::SMUL: return "X86ISD::SMUL";
11153 case X86ISD::UMUL: return "X86ISD::UMUL";
11154 case X86ISD::INC: return "X86ISD::INC";
11155 case X86ISD::DEC: return "X86ISD::DEC";
11156 case X86ISD::OR: return "X86ISD::OR";
11157 case X86ISD::XOR: return "X86ISD::XOR";
11158 case X86ISD::AND: return "X86ISD::AND";
11159 case X86ISD::ANDN: return "X86ISD::ANDN";
11160 case X86ISD::BLSI: return "X86ISD::BLSI";
11161 case X86ISD::BLSMSK: return "X86ISD::BLSMSK";
11162 case X86ISD::BLSR: return "X86ISD::BLSR";
11163 case X86ISD::MUL_IMM: return "X86ISD::MUL_IMM";
11164 case X86ISD::PTEST: return "X86ISD::PTEST";
11165 case X86ISD::TESTP: return "X86ISD::TESTP";
11166 case X86ISD::PALIGN: return "X86ISD::PALIGN";
11167 case X86ISD::PSHUFD: return "X86ISD::PSHUFD";
11168 case X86ISD::PSHUFHW: return "X86ISD::PSHUFHW";
11169 case X86ISD::PSHUFLW: return "X86ISD::PSHUFLW";
11170 case X86ISD::SHUFP: return "X86ISD::SHUFP";
11171 case X86ISD::MOVLHPS: return "X86ISD::MOVLHPS";
11172 case X86ISD::MOVLHPD: return "X86ISD::MOVLHPD";
11173 case X86ISD::MOVHLPS: return "X86ISD::MOVHLPS";
11174 case X86ISD::MOVLPS: return "X86ISD::MOVLPS";
11175 case X86ISD::MOVLPD: return "X86ISD::MOVLPD";
11176 case X86ISD::MOVDDUP: return "X86ISD::MOVDDUP";
11177 case X86ISD::MOVSHDUP: return "X86ISD::MOVSHDUP";
11178 case X86ISD::MOVSLDUP: return "X86ISD::MOVSLDUP";
11179 case X86ISD::MOVSD: return "X86ISD::MOVSD";
11180 case X86ISD::MOVSS: return "X86ISD::MOVSS";
11181 case X86ISD::UNPCKL: return "X86ISD::UNPCKL";
11182 case X86ISD::UNPCKH: return "X86ISD::UNPCKH";
11183 case X86ISD::VBROADCAST: return "X86ISD::VBROADCAST";
11184 case X86ISD::VPERMILP: return "X86ISD::VPERMILP";
11185 case X86ISD::VPERM2X128: return "X86ISD::VPERM2X128";
11186 case X86ISD::VPERMV: return "X86ISD::VPERMV";
11187 case X86ISD::VPERMI: return "X86ISD::VPERMI";
11188 case X86ISD::PMULUDQ: return "X86ISD::PMULUDQ";
11189 case X86ISD::VASTART_SAVE_XMM_REGS: return "X86ISD::VASTART_SAVE_XMM_REGS";
11190 case X86ISD::VAARG_64: return "X86ISD::VAARG_64";
11191 case X86ISD::WIN_ALLOCA: return "X86ISD::WIN_ALLOCA";
11192 case X86ISD::MEMBARRIER: return "X86ISD::MEMBARRIER";
11193 case X86ISD::SEG_ALLOCA: return "X86ISD::SEG_ALLOCA";
11194 case X86ISD::WIN_FTOL: return "X86ISD::WIN_FTOL";
11198 // isLegalAddressingMode - Return true if the addressing mode represented
11199 // by AM is legal for this target, for a load/store of the specified type.
11200 bool X86TargetLowering::isLegalAddressingMode(const AddrMode &AM,
11202 // X86 supports extremely general addressing modes.
11203 CodeModel::Model M = getTargetMachine().getCodeModel();
11204 Reloc::Model R = getTargetMachine().getRelocationModel();
11206 // X86 allows a sign-extended 32-bit immediate field as a displacement.
11207 if (!X86::isOffsetSuitableForCodeModel(AM.BaseOffs, M, AM.BaseGV != NULL))
11212 Subtarget->ClassifyGlobalReference(AM.BaseGV, getTargetMachine());
11214 // If a reference to this global requires an extra load, we can't fold it.
11215 if (isGlobalStubReference(GVFlags))
11218 // If BaseGV requires a register for the PIC base, we cannot also have a
11219 // BaseReg specified.
11220 if (AM.HasBaseReg && isGlobalRelativeToPICBase(GVFlags))
11223 // If lower 4G is not available, then we must use rip-relative addressing.
11224 if ((M != CodeModel::Small || R != Reloc::Static) &&
11225 Subtarget->is64Bit() && (AM.BaseOffs || AM.Scale > 1))
11229 switch (AM.Scale) {
11235 // These scales always work.
11240 // These scales are formed with basereg+scalereg. Only accept if there is
11245 default: // Other stuff never works.
11253 bool X86TargetLowering::isTruncateFree(Type *Ty1, Type *Ty2) const {
11254 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
11256 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits();
11257 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits();
11258 if (NumBits1 <= NumBits2)
11263 bool X86TargetLowering::isTruncateFree(EVT VT1, EVT VT2) const {
11264 if (!VT1.isInteger() || !VT2.isInteger())
11266 unsigned NumBits1 = VT1.getSizeInBits();
11267 unsigned NumBits2 = VT2.getSizeInBits();
11268 if (NumBits1 <= NumBits2)
11273 bool X86TargetLowering::isZExtFree(Type *Ty1, Type *Ty2) const {
11274 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
11275 return Ty1->isIntegerTy(32) && Ty2->isIntegerTy(64) && Subtarget->is64Bit();
11278 bool X86TargetLowering::isZExtFree(EVT VT1, EVT VT2) const {
11279 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
11280 return VT1 == MVT::i32 && VT2 == MVT::i64 && Subtarget->is64Bit();
11283 bool X86TargetLowering::isNarrowingProfitable(EVT VT1, EVT VT2) const {
11284 // i16 instructions are longer (0x66 prefix) and potentially slower.
11285 return !(VT1 == MVT::i32 && VT2 == MVT::i16);
11288 /// isShuffleMaskLegal - Targets can use this to indicate that they only
11289 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
11290 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
11291 /// are assumed to be legal.
11293 X86TargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M,
11295 // Very little shuffling can be done for 64-bit vectors right now.
11296 if (VT.getSizeInBits() == 64)
11299 // FIXME: pshufb, blends, shifts.
11300 return (VT.getVectorNumElements() == 2 ||
11301 ShuffleVectorSDNode::isSplatMask(&M[0], VT) ||
11302 isMOVLMask(M, VT) ||
11303 isSHUFPMask(M, VT, Subtarget->hasAVX()) ||
11304 isPSHUFDMask(M, VT) ||
11305 isPSHUFHWMask(M, VT) ||
11306 isPSHUFLWMask(M, VT) ||
11307 isPALIGNRMask(M, VT, Subtarget) ||
11308 isUNPCKLMask(M, VT, Subtarget->hasAVX2()) ||
11309 isUNPCKHMask(M, VT, Subtarget->hasAVX2()) ||
11310 isUNPCKL_v_undef_Mask(M, VT, Subtarget->hasAVX2()) ||
11311 isUNPCKH_v_undef_Mask(M, VT, Subtarget->hasAVX2()));
11315 X86TargetLowering::isVectorClearMaskLegal(const SmallVectorImpl<int> &Mask,
11317 unsigned NumElts = VT.getVectorNumElements();
11318 // FIXME: This collection of masks seems suspect.
11321 if (NumElts == 4 && VT.getSizeInBits() == 128) {
11322 return (isMOVLMask(Mask, VT) ||
11323 isCommutedMOVLMask(Mask, VT, true) ||
11324 isSHUFPMask(Mask, VT, Subtarget->hasAVX()) ||
11325 isSHUFPMask(Mask, VT, Subtarget->hasAVX(), /* Commuted */ true));
11330 //===----------------------------------------------------------------------===//
11331 // X86 Scheduler Hooks
11332 //===----------------------------------------------------------------------===//
11334 // private utility function
11335 MachineBasicBlock *
11336 X86TargetLowering::EmitAtomicBitwiseWithCustomInserter(MachineInstr *bInstr,
11337 MachineBasicBlock *MBB,
11344 const TargetRegisterClass *RC,
11345 bool Invert) const {
11346 // For the atomic bitwise operator, we generate
11349 // ld t1 = [bitinstr.addr]
11350 // op t2 = t1, [bitinstr.val]
11351 // not t3 = t2 (if Invert)
11353 // lcs dest = [bitinstr.addr], t3 [EAX is implicit]
11355 // fallthrough -->nextMBB
11356 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
11357 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
11358 MachineFunction::iterator MBBIter = MBB;
11361 /// First build the CFG
11362 MachineFunction *F = MBB->getParent();
11363 MachineBasicBlock *thisMBB = MBB;
11364 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB);
11365 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB);
11366 F->insert(MBBIter, newMBB);
11367 F->insert(MBBIter, nextMBB);
11369 // Transfer the remainder of thisMBB and its successor edges to nextMBB.
11370 nextMBB->splice(nextMBB->begin(), thisMBB,
11371 llvm::next(MachineBasicBlock::iterator(bInstr)),
11373 nextMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
11375 // Update thisMBB to fall through to newMBB
11376 thisMBB->addSuccessor(newMBB);
11378 // newMBB jumps to itself and fall through to nextMBB
11379 newMBB->addSuccessor(nextMBB);
11380 newMBB->addSuccessor(newMBB);
11382 // Insert instructions into newMBB based on incoming instruction
11383 assert(bInstr->getNumOperands() < X86::AddrNumOperands + 4 &&
11384 "unexpected number of operands");
11385 DebugLoc dl = bInstr->getDebugLoc();
11386 MachineOperand& destOper = bInstr->getOperand(0);
11387 MachineOperand* argOpers[2 + X86::AddrNumOperands];
11388 int numArgs = bInstr->getNumOperands() - 1;
11389 for (int i=0; i < numArgs; ++i)
11390 argOpers[i] = &bInstr->getOperand(i+1);
11392 // x86 address has 4 operands: base, index, scale, and displacement
11393 int lastAddrIndx = X86::AddrNumOperands - 1; // [0,3]
11394 int valArgIndx = lastAddrIndx + 1;
11396 unsigned t1 = F->getRegInfo().createVirtualRegister(RC);
11397 MachineInstrBuilder MIB = BuildMI(newMBB, dl, TII->get(LoadOpc), t1);
11398 for (int i=0; i <= lastAddrIndx; ++i)
11399 (*MIB).addOperand(*argOpers[i]);
11401 unsigned t2 = F->getRegInfo().createVirtualRegister(RC);
11402 assert((argOpers[valArgIndx]->isReg() ||
11403 argOpers[valArgIndx]->isImm()) &&
11404 "invalid operand");
11405 if (argOpers[valArgIndx]->isReg())
11406 MIB = BuildMI(newMBB, dl, TII->get(regOpc), t2);
11408 MIB = BuildMI(newMBB, dl, TII->get(immOpc), t2);
11410 (*MIB).addOperand(*argOpers[valArgIndx]);
11412 unsigned t3 = F->getRegInfo().createVirtualRegister(RC);
11414 MIB = BuildMI(newMBB, dl, TII->get(notOpc), t3).addReg(t2);
11419 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), EAXreg);
11422 MIB = BuildMI(newMBB, dl, TII->get(CXchgOpc));
11423 for (int i=0; i <= lastAddrIndx; ++i)
11424 (*MIB).addOperand(*argOpers[i]);
11426 assert(bInstr->hasOneMemOperand() && "Unexpected number of memoperand");
11427 (*MIB).setMemRefs(bInstr->memoperands_begin(),
11428 bInstr->memoperands_end());
11430 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), destOper.getReg());
11431 MIB.addReg(EAXreg);
11434 BuildMI(newMBB, dl, TII->get(X86::JNE_4)).addMBB(newMBB);
11436 bInstr->eraseFromParent(); // The pseudo instruction is gone now.
11440 // private utility function: 64 bit atomics on 32 bit host.
11441 MachineBasicBlock *
11442 X86TargetLowering::EmitAtomicBit6432WithCustomInserter(MachineInstr *bInstr,
11443 MachineBasicBlock *MBB,
11448 bool Invert) const {
11449 // For the atomic bitwise operator, we generate
11450 // thisMBB (instructions are in pairs, except cmpxchg8b)
11451 // ld t1,t2 = [bitinstr.addr]
11453 // out1, out2 = phi (thisMBB, t1/t2) (newMBB, t3/t4)
11454 // op t5, t6 <- out1, out2, [bitinstr.val]
11455 // (for SWAP, substitute: mov t5, t6 <- [bitinstr.val])
11456 // neg t7, t8 < t5, t6 (if Invert)
11457 // mov ECX, EBX <- t5, t6
11458 // mov EAX, EDX <- t1, t2
11459 // cmpxchg8b [bitinstr.addr] [EAX, EDX, EBX, ECX implicit]
11460 // mov t3, t4 <- EAX, EDX
11462 // result in out1, out2
11463 // fallthrough -->nextMBB
11465 const TargetRegisterClass *RC = &X86::GR32RegClass;
11466 const unsigned LoadOpc = X86::MOV32rm;
11467 const unsigned NotOpc = X86::NOT32r;
11468 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
11469 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
11470 MachineFunction::iterator MBBIter = MBB;
11473 /// First build the CFG
11474 MachineFunction *F = MBB->getParent();
11475 MachineBasicBlock *thisMBB = MBB;
11476 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB);
11477 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB);
11478 F->insert(MBBIter, newMBB);
11479 F->insert(MBBIter, nextMBB);
11481 // Transfer the remainder of thisMBB and its successor edges to nextMBB.
11482 nextMBB->splice(nextMBB->begin(), thisMBB,
11483 llvm::next(MachineBasicBlock::iterator(bInstr)),
11485 nextMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
11487 // Update thisMBB to fall through to newMBB
11488 thisMBB->addSuccessor(newMBB);
11490 // newMBB jumps to itself and fall through to nextMBB
11491 newMBB->addSuccessor(nextMBB);
11492 newMBB->addSuccessor(newMBB);
11494 DebugLoc dl = bInstr->getDebugLoc();
11495 // Insert instructions into newMBB based on incoming instruction
11496 // There are 8 "real" operands plus 9 implicit def/uses, ignored here.
11497 assert(bInstr->getNumOperands() < X86::AddrNumOperands + 14 &&
11498 "unexpected number of operands");
11499 MachineOperand& dest1Oper = bInstr->getOperand(0);
11500 MachineOperand& dest2Oper = bInstr->getOperand(1);
11501 MachineOperand* argOpers[2 + X86::AddrNumOperands];
11502 for (int i=0; i < 2 + X86::AddrNumOperands; ++i) {
11503 argOpers[i] = &bInstr->getOperand(i+2);
11505 // We use some of the operands multiple times, so conservatively just
11506 // clear any kill flags that might be present.
11507 if (argOpers[i]->isReg() && argOpers[i]->isUse())
11508 argOpers[i]->setIsKill(false);
11511 // x86 address has 5 operands: base, index, scale, displacement, and segment.
11512 int lastAddrIndx = X86::AddrNumOperands - 1; // [0,3]
11514 unsigned t1 = F->getRegInfo().createVirtualRegister(RC);
11515 MachineInstrBuilder MIB = BuildMI(thisMBB, dl, TII->get(LoadOpc), t1);
11516 for (int i=0; i <= lastAddrIndx; ++i)
11517 (*MIB).addOperand(*argOpers[i]);
11518 unsigned t2 = F->getRegInfo().createVirtualRegister(RC);
11519 MIB = BuildMI(thisMBB, dl, TII->get(LoadOpc), t2);
11520 // add 4 to displacement.
11521 for (int i=0; i <= lastAddrIndx-2; ++i)
11522 (*MIB).addOperand(*argOpers[i]);
11523 MachineOperand newOp3 = *(argOpers[3]);
11524 if (newOp3.isImm())
11525 newOp3.setImm(newOp3.getImm()+4);
11527 newOp3.setOffset(newOp3.getOffset()+4);
11528 (*MIB).addOperand(newOp3);
11529 (*MIB).addOperand(*argOpers[lastAddrIndx]);
11531 // t3/4 are defined later, at the bottom of the loop
11532 unsigned t3 = F->getRegInfo().createVirtualRegister(RC);
11533 unsigned t4 = F->getRegInfo().createVirtualRegister(RC);
11534 BuildMI(newMBB, dl, TII->get(X86::PHI), dest1Oper.getReg())
11535 .addReg(t1).addMBB(thisMBB).addReg(t3).addMBB(newMBB);
11536 BuildMI(newMBB, dl, TII->get(X86::PHI), dest2Oper.getReg())
11537 .addReg(t2).addMBB(thisMBB).addReg(t4).addMBB(newMBB);
11539 // The subsequent operations should be using the destination registers of
11540 // the PHI instructions.
11541 t1 = dest1Oper.getReg();
11542 t2 = dest2Oper.getReg();
11544 int valArgIndx = lastAddrIndx + 1;
11545 assert((argOpers[valArgIndx]->isReg() ||
11546 argOpers[valArgIndx]->isImm()) &&
11547 "invalid operand");
11548 unsigned t5 = F->getRegInfo().createVirtualRegister(RC);
11549 unsigned t6 = F->getRegInfo().createVirtualRegister(RC);
11550 if (argOpers[valArgIndx]->isReg())
11551 MIB = BuildMI(newMBB, dl, TII->get(regOpcL), t5);
11553 MIB = BuildMI(newMBB, dl, TII->get(immOpcL), t5);
11554 if (regOpcL != X86::MOV32rr)
11556 (*MIB).addOperand(*argOpers[valArgIndx]);
11557 assert(argOpers[valArgIndx + 1]->isReg() ==
11558 argOpers[valArgIndx]->isReg());
11559 assert(argOpers[valArgIndx + 1]->isImm() ==
11560 argOpers[valArgIndx]->isImm());
11561 if (argOpers[valArgIndx + 1]->isReg())
11562 MIB = BuildMI(newMBB, dl, TII->get(regOpcH), t6);
11564 MIB = BuildMI(newMBB, dl, TII->get(immOpcH), t6);
11565 if (regOpcH != X86::MOV32rr)
11567 (*MIB).addOperand(*argOpers[valArgIndx + 1]);
11571 t7 = F->getRegInfo().createVirtualRegister(RC);
11572 t8 = F->getRegInfo().createVirtualRegister(RC);
11573 MIB = BuildMI(newMBB, dl, TII->get(NotOpc), t7).addReg(t5);
11574 MIB = BuildMI(newMBB, dl, TII->get(NotOpc), t8).addReg(t6);
11580 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::EAX);
11582 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::EDX);
11585 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::EBX);
11587 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::ECX);
11590 MIB = BuildMI(newMBB, dl, TII->get(X86::LCMPXCHG8B));
11591 for (int i=0; i <= lastAddrIndx; ++i)
11592 (*MIB).addOperand(*argOpers[i]);
11594 assert(bInstr->hasOneMemOperand() && "Unexpected number of memoperand");
11595 (*MIB).setMemRefs(bInstr->memoperands_begin(),
11596 bInstr->memoperands_end());
11598 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), t3);
11599 MIB.addReg(X86::EAX);
11600 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), t4);
11601 MIB.addReg(X86::EDX);
11604 BuildMI(newMBB, dl, TII->get(X86::JNE_4)).addMBB(newMBB);
11606 bInstr->eraseFromParent(); // The pseudo instruction is gone now.
11610 // private utility function
11611 MachineBasicBlock *
11612 X86TargetLowering::EmitAtomicMinMaxWithCustomInserter(MachineInstr *mInstr,
11613 MachineBasicBlock *MBB,
11614 unsigned cmovOpc) const {
11615 // For the atomic min/max operator, we generate
11618 // ld t1 = [min/max.addr]
11619 // mov t2 = [min/max.val]
11621 // cmov[cond] t2 = t1
11623 // lcs dest = [bitinstr.addr], t2 [EAX is implicit]
11625 // fallthrough -->nextMBB
11627 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
11628 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
11629 MachineFunction::iterator MBBIter = MBB;
11632 /// First build the CFG
11633 MachineFunction *F = MBB->getParent();
11634 MachineBasicBlock *thisMBB = MBB;
11635 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB);
11636 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB);
11637 F->insert(MBBIter, newMBB);
11638 F->insert(MBBIter, nextMBB);
11640 // Transfer the remainder of thisMBB and its successor edges to nextMBB.
11641 nextMBB->splice(nextMBB->begin(), thisMBB,
11642 llvm::next(MachineBasicBlock::iterator(mInstr)),
11644 nextMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
11646 // Update thisMBB to fall through to newMBB
11647 thisMBB->addSuccessor(newMBB);
11649 // newMBB jumps to newMBB and fall through to nextMBB
11650 newMBB->addSuccessor(nextMBB);
11651 newMBB->addSuccessor(newMBB);
11653 DebugLoc dl = mInstr->getDebugLoc();
11654 // Insert instructions into newMBB based on incoming instruction
11655 assert(mInstr->getNumOperands() < X86::AddrNumOperands + 4 &&
11656 "unexpected number of operands");
11657 MachineOperand& destOper = mInstr->getOperand(0);
11658 MachineOperand* argOpers[2 + X86::AddrNumOperands];
11659 int numArgs = mInstr->getNumOperands() - 1;
11660 for (int i=0; i < numArgs; ++i)
11661 argOpers[i] = &mInstr->getOperand(i+1);
11663 // x86 address has 4 operands: base, index, scale, and displacement
11664 int lastAddrIndx = X86::AddrNumOperands - 1; // [0,3]
11665 int valArgIndx = lastAddrIndx + 1;
11667 unsigned t1 = F->getRegInfo().createVirtualRegister(&X86::GR32RegClass);
11668 MachineInstrBuilder MIB = BuildMI(newMBB, dl, TII->get(X86::MOV32rm), t1);
11669 for (int i=0; i <= lastAddrIndx; ++i)
11670 (*MIB).addOperand(*argOpers[i]);
11672 // We only support register and immediate values
11673 assert((argOpers[valArgIndx]->isReg() ||
11674 argOpers[valArgIndx]->isImm()) &&
11675 "invalid operand");
11677 unsigned t2 = F->getRegInfo().createVirtualRegister(&X86::GR32RegClass);
11678 if (argOpers[valArgIndx]->isReg())
11679 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), t2);
11681 MIB = BuildMI(newMBB, dl, TII->get(X86::MOV32rr), t2);
11682 (*MIB).addOperand(*argOpers[valArgIndx]);
11684 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::EAX);
11687 MIB = BuildMI(newMBB, dl, TII->get(X86::CMP32rr));
11692 unsigned t3 = F->getRegInfo().createVirtualRegister(&X86::GR32RegClass);
11693 MIB = BuildMI(newMBB, dl, TII->get(cmovOpc),t3);
11697 // Cmp and exchange if none has modified the memory location
11698 MIB = BuildMI(newMBB, dl, TII->get(X86::LCMPXCHG32));
11699 for (int i=0; i <= lastAddrIndx; ++i)
11700 (*MIB).addOperand(*argOpers[i]);
11702 assert(mInstr->hasOneMemOperand() && "Unexpected number of memoperand");
11703 (*MIB).setMemRefs(mInstr->memoperands_begin(),
11704 mInstr->memoperands_end());
11706 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), destOper.getReg());
11707 MIB.addReg(X86::EAX);
11710 BuildMI(newMBB, dl, TII->get(X86::JNE_4)).addMBB(newMBB);
11712 mInstr->eraseFromParent(); // The pseudo instruction is gone now.
11716 // FIXME: When we get size specific XMM0 registers, i.e. XMM0_V16I8
11717 // or XMM0_V32I8 in AVX all of this code can be replaced with that
11718 // in the .td file.
11719 MachineBasicBlock *
11720 X86TargetLowering::EmitPCMP(MachineInstr *MI, MachineBasicBlock *BB,
11721 unsigned numArgs, bool memArg) const {
11722 assert(Subtarget->hasSSE42() &&
11723 "Target must have SSE4.2 or AVX features enabled");
11725 DebugLoc dl = MI->getDebugLoc();
11726 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
11728 if (!Subtarget->hasAVX()) {
11730 Opc = numArgs == 3 ? X86::PCMPISTRM128rm : X86::PCMPESTRM128rm;
11732 Opc = numArgs == 3 ? X86::PCMPISTRM128rr : X86::PCMPESTRM128rr;
11735 Opc = numArgs == 3 ? X86::VPCMPISTRM128rm : X86::VPCMPESTRM128rm;
11737 Opc = numArgs == 3 ? X86::VPCMPISTRM128rr : X86::VPCMPESTRM128rr;
11740 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(Opc));
11741 for (unsigned i = 0; i < numArgs; ++i) {
11742 MachineOperand &Op = MI->getOperand(i+1);
11743 if (!(Op.isReg() && Op.isImplicit()))
11744 MIB.addOperand(Op);
11746 BuildMI(*BB, MI, dl,
11747 TII->get(Subtarget->hasAVX() ? X86::VMOVAPSrr : X86::MOVAPSrr),
11748 MI->getOperand(0).getReg())
11749 .addReg(X86::XMM0);
11751 MI->eraseFromParent();
11755 MachineBasicBlock *
11756 X86TargetLowering::EmitMonitor(MachineInstr *MI, MachineBasicBlock *BB) const {
11757 DebugLoc dl = MI->getDebugLoc();
11758 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
11760 // Address into RAX/EAX, other two args into ECX, EDX.
11761 unsigned MemOpc = Subtarget->is64Bit() ? X86::LEA64r : X86::LEA32r;
11762 unsigned MemReg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
11763 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(MemOpc), MemReg);
11764 for (int i = 0; i < X86::AddrNumOperands; ++i)
11765 MIB.addOperand(MI->getOperand(i));
11767 unsigned ValOps = X86::AddrNumOperands;
11768 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::ECX)
11769 .addReg(MI->getOperand(ValOps).getReg());
11770 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::EDX)
11771 .addReg(MI->getOperand(ValOps+1).getReg());
11773 // The instruction doesn't actually take any operands though.
11774 BuildMI(*BB, MI, dl, TII->get(X86::MONITORrrr));
11776 MI->eraseFromParent(); // The pseudo is gone now.
11780 MachineBasicBlock *
11781 X86TargetLowering::EmitMwait(MachineInstr *MI, MachineBasicBlock *BB) const {
11782 DebugLoc dl = MI->getDebugLoc();
11783 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
11785 // First arg in ECX, the second in EAX.
11786 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::ECX)
11787 .addReg(MI->getOperand(0).getReg());
11788 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::EAX)
11789 .addReg(MI->getOperand(1).getReg());
11791 // The instruction doesn't actually take any operands though.
11792 BuildMI(*BB, MI, dl, TII->get(X86::MWAITrr));
11794 MI->eraseFromParent(); // The pseudo is gone now.
11798 MachineBasicBlock *
11799 X86TargetLowering::EmitVAARG64WithCustomInserter(
11801 MachineBasicBlock *MBB) const {
11802 // Emit va_arg instruction on X86-64.
11804 // Operands to this pseudo-instruction:
11805 // 0 ) Output : destination address (reg)
11806 // 1-5) Input : va_list address (addr, i64mem)
11807 // 6 ) ArgSize : Size (in bytes) of vararg type
11808 // 7 ) ArgMode : 0=overflow only, 1=use gp_offset, 2=use fp_offset
11809 // 8 ) Align : Alignment of type
11810 // 9 ) EFLAGS (implicit-def)
11812 assert(MI->getNumOperands() == 10 && "VAARG_64 should have 10 operands!");
11813 assert(X86::AddrNumOperands == 5 && "VAARG_64 assumes 5 address operands");
11815 unsigned DestReg = MI->getOperand(0).getReg();
11816 MachineOperand &Base = MI->getOperand(1);
11817 MachineOperand &Scale = MI->getOperand(2);
11818 MachineOperand &Index = MI->getOperand(3);
11819 MachineOperand &Disp = MI->getOperand(4);
11820 MachineOperand &Segment = MI->getOperand(5);
11821 unsigned ArgSize = MI->getOperand(6).getImm();
11822 unsigned ArgMode = MI->getOperand(7).getImm();
11823 unsigned Align = MI->getOperand(8).getImm();
11825 // Memory Reference
11826 assert(MI->hasOneMemOperand() && "Expected VAARG_64 to have one memoperand");
11827 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
11828 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
11830 // Machine Information
11831 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
11832 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
11833 const TargetRegisterClass *AddrRegClass = getRegClassFor(MVT::i64);
11834 const TargetRegisterClass *OffsetRegClass = getRegClassFor(MVT::i32);
11835 DebugLoc DL = MI->getDebugLoc();
11837 // struct va_list {
11840 // i64 overflow_area (address)
11841 // i64 reg_save_area (address)
11843 // sizeof(va_list) = 24
11844 // alignment(va_list) = 8
11846 unsigned TotalNumIntRegs = 6;
11847 unsigned TotalNumXMMRegs = 8;
11848 bool UseGPOffset = (ArgMode == 1);
11849 bool UseFPOffset = (ArgMode == 2);
11850 unsigned MaxOffset = TotalNumIntRegs * 8 +
11851 (UseFPOffset ? TotalNumXMMRegs * 16 : 0);
11853 /* Align ArgSize to a multiple of 8 */
11854 unsigned ArgSizeA8 = (ArgSize + 7) & ~7;
11855 bool NeedsAlign = (Align > 8);
11857 MachineBasicBlock *thisMBB = MBB;
11858 MachineBasicBlock *overflowMBB;
11859 MachineBasicBlock *offsetMBB;
11860 MachineBasicBlock *endMBB;
11862 unsigned OffsetDestReg = 0; // Argument address computed by offsetMBB
11863 unsigned OverflowDestReg = 0; // Argument address computed by overflowMBB
11864 unsigned OffsetReg = 0;
11866 if (!UseGPOffset && !UseFPOffset) {
11867 // If we only pull from the overflow region, we don't create a branch.
11868 // We don't need to alter control flow.
11869 OffsetDestReg = 0; // unused
11870 OverflowDestReg = DestReg;
11873 overflowMBB = thisMBB;
11876 // First emit code to check if gp_offset (or fp_offset) is below the bound.
11877 // If so, pull the argument from reg_save_area. (branch to offsetMBB)
11878 // If not, pull from overflow_area. (branch to overflowMBB)
11883 // offsetMBB overflowMBB
11888 // Registers for the PHI in endMBB
11889 OffsetDestReg = MRI.createVirtualRegister(AddrRegClass);
11890 OverflowDestReg = MRI.createVirtualRegister(AddrRegClass);
11892 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
11893 MachineFunction *MF = MBB->getParent();
11894 overflowMBB = MF->CreateMachineBasicBlock(LLVM_BB);
11895 offsetMBB = MF->CreateMachineBasicBlock(LLVM_BB);
11896 endMBB = MF->CreateMachineBasicBlock(LLVM_BB);
11898 MachineFunction::iterator MBBIter = MBB;
11901 // Insert the new basic blocks
11902 MF->insert(MBBIter, offsetMBB);
11903 MF->insert(MBBIter, overflowMBB);
11904 MF->insert(MBBIter, endMBB);
11906 // Transfer the remainder of MBB and its successor edges to endMBB.
11907 endMBB->splice(endMBB->begin(), thisMBB,
11908 llvm::next(MachineBasicBlock::iterator(MI)),
11910 endMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
11912 // Make offsetMBB and overflowMBB successors of thisMBB
11913 thisMBB->addSuccessor(offsetMBB);
11914 thisMBB->addSuccessor(overflowMBB);
11916 // endMBB is a successor of both offsetMBB and overflowMBB
11917 offsetMBB->addSuccessor(endMBB);
11918 overflowMBB->addSuccessor(endMBB);
11920 // Load the offset value into a register
11921 OffsetReg = MRI.createVirtualRegister(OffsetRegClass);
11922 BuildMI(thisMBB, DL, TII->get(X86::MOV32rm), OffsetReg)
11926 .addDisp(Disp, UseFPOffset ? 4 : 0)
11927 .addOperand(Segment)
11928 .setMemRefs(MMOBegin, MMOEnd);
11930 // Check if there is enough room left to pull this argument.
11931 BuildMI(thisMBB, DL, TII->get(X86::CMP32ri))
11933 .addImm(MaxOffset + 8 - ArgSizeA8);
11935 // Branch to "overflowMBB" if offset >= max
11936 // Fall through to "offsetMBB" otherwise
11937 BuildMI(thisMBB, DL, TII->get(X86::GetCondBranchFromCond(X86::COND_AE)))
11938 .addMBB(overflowMBB);
11941 // In offsetMBB, emit code to use the reg_save_area.
11943 assert(OffsetReg != 0);
11945 // Read the reg_save_area address.
11946 unsigned RegSaveReg = MRI.createVirtualRegister(AddrRegClass);
11947 BuildMI(offsetMBB, DL, TII->get(X86::MOV64rm), RegSaveReg)
11952 .addOperand(Segment)
11953 .setMemRefs(MMOBegin, MMOEnd);
11955 // Zero-extend the offset
11956 unsigned OffsetReg64 = MRI.createVirtualRegister(AddrRegClass);
11957 BuildMI(offsetMBB, DL, TII->get(X86::SUBREG_TO_REG), OffsetReg64)
11960 .addImm(X86::sub_32bit);
11962 // Add the offset to the reg_save_area to get the final address.
11963 BuildMI(offsetMBB, DL, TII->get(X86::ADD64rr), OffsetDestReg)
11964 .addReg(OffsetReg64)
11965 .addReg(RegSaveReg);
11967 // Compute the offset for the next argument
11968 unsigned NextOffsetReg = MRI.createVirtualRegister(OffsetRegClass);
11969 BuildMI(offsetMBB, DL, TII->get(X86::ADD32ri), NextOffsetReg)
11971 .addImm(UseFPOffset ? 16 : 8);
11973 // Store it back into the va_list.
11974 BuildMI(offsetMBB, DL, TII->get(X86::MOV32mr))
11978 .addDisp(Disp, UseFPOffset ? 4 : 0)
11979 .addOperand(Segment)
11980 .addReg(NextOffsetReg)
11981 .setMemRefs(MMOBegin, MMOEnd);
11984 BuildMI(offsetMBB, DL, TII->get(X86::JMP_4))
11989 // Emit code to use overflow area
11992 // Load the overflow_area address into a register.
11993 unsigned OverflowAddrReg = MRI.createVirtualRegister(AddrRegClass);
11994 BuildMI(overflowMBB, DL, TII->get(X86::MOV64rm), OverflowAddrReg)
11999 .addOperand(Segment)
12000 .setMemRefs(MMOBegin, MMOEnd);
12002 // If we need to align it, do so. Otherwise, just copy the address
12003 // to OverflowDestReg.
12005 // Align the overflow address
12006 assert((Align & (Align-1)) == 0 && "Alignment must be a power of 2");
12007 unsigned TmpReg = MRI.createVirtualRegister(AddrRegClass);
12009 // aligned_addr = (addr + (align-1)) & ~(align-1)
12010 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), TmpReg)
12011 .addReg(OverflowAddrReg)
12014 BuildMI(overflowMBB, DL, TII->get(X86::AND64ri32), OverflowDestReg)
12016 .addImm(~(uint64_t)(Align-1));
12018 BuildMI(overflowMBB, DL, TII->get(TargetOpcode::COPY), OverflowDestReg)
12019 .addReg(OverflowAddrReg);
12022 // Compute the next overflow address after this argument.
12023 // (the overflow address should be kept 8-byte aligned)
12024 unsigned NextAddrReg = MRI.createVirtualRegister(AddrRegClass);
12025 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), NextAddrReg)
12026 .addReg(OverflowDestReg)
12027 .addImm(ArgSizeA8);
12029 // Store the new overflow address.
12030 BuildMI(overflowMBB, DL, TII->get(X86::MOV64mr))
12035 .addOperand(Segment)
12036 .addReg(NextAddrReg)
12037 .setMemRefs(MMOBegin, MMOEnd);
12039 // If we branched, emit the PHI to the front of endMBB.
12041 BuildMI(*endMBB, endMBB->begin(), DL,
12042 TII->get(X86::PHI), DestReg)
12043 .addReg(OffsetDestReg).addMBB(offsetMBB)
12044 .addReg(OverflowDestReg).addMBB(overflowMBB);
12047 // Erase the pseudo instruction
12048 MI->eraseFromParent();
12053 MachineBasicBlock *
12054 X86TargetLowering::EmitVAStartSaveXMMRegsWithCustomInserter(
12056 MachineBasicBlock *MBB) const {
12057 // Emit code to save XMM registers to the stack. The ABI says that the
12058 // number of registers to save is given in %al, so it's theoretically
12059 // possible to do an indirect jump trick to avoid saving all of them,
12060 // however this code takes a simpler approach and just executes all
12061 // of the stores if %al is non-zero. It's less code, and it's probably
12062 // easier on the hardware branch predictor, and stores aren't all that
12063 // expensive anyway.
12065 // Create the new basic blocks. One block contains all the XMM stores,
12066 // and one block is the final destination regardless of whether any
12067 // stores were performed.
12068 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
12069 MachineFunction *F = MBB->getParent();
12070 MachineFunction::iterator MBBIter = MBB;
12072 MachineBasicBlock *XMMSaveMBB = F->CreateMachineBasicBlock(LLVM_BB);
12073 MachineBasicBlock *EndMBB = F->CreateMachineBasicBlock(LLVM_BB);
12074 F->insert(MBBIter, XMMSaveMBB);
12075 F->insert(MBBIter, EndMBB);
12077 // Transfer the remainder of MBB and its successor edges to EndMBB.
12078 EndMBB->splice(EndMBB->begin(), MBB,
12079 llvm::next(MachineBasicBlock::iterator(MI)),
12081 EndMBB->transferSuccessorsAndUpdatePHIs(MBB);
12083 // The original block will now fall through to the XMM save block.
12084 MBB->addSuccessor(XMMSaveMBB);
12085 // The XMMSaveMBB will fall through to the end block.
12086 XMMSaveMBB->addSuccessor(EndMBB);
12088 // Now add the instructions.
12089 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
12090 DebugLoc DL = MI->getDebugLoc();
12092 unsigned CountReg = MI->getOperand(0).getReg();
12093 int64_t RegSaveFrameIndex = MI->getOperand(1).getImm();
12094 int64_t VarArgsFPOffset = MI->getOperand(2).getImm();
12096 if (!Subtarget->isTargetWin64()) {
12097 // If %al is 0, branch around the XMM save block.
12098 BuildMI(MBB, DL, TII->get(X86::TEST8rr)).addReg(CountReg).addReg(CountReg);
12099 BuildMI(MBB, DL, TII->get(X86::JE_4)).addMBB(EndMBB);
12100 MBB->addSuccessor(EndMBB);
12103 unsigned MOVOpc = Subtarget->hasAVX() ? X86::VMOVAPSmr : X86::MOVAPSmr;
12104 // In the XMM save block, save all the XMM argument registers.
12105 for (int i = 3, e = MI->getNumOperands(); i != e; ++i) {
12106 int64_t Offset = (i - 3) * 16 + VarArgsFPOffset;
12107 MachineMemOperand *MMO =
12108 F->getMachineMemOperand(
12109 MachinePointerInfo::getFixedStack(RegSaveFrameIndex, Offset),
12110 MachineMemOperand::MOStore,
12111 /*Size=*/16, /*Align=*/16);
12112 BuildMI(XMMSaveMBB, DL, TII->get(MOVOpc))
12113 .addFrameIndex(RegSaveFrameIndex)
12114 .addImm(/*Scale=*/1)
12115 .addReg(/*IndexReg=*/0)
12116 .addImm(/*Disp=*/Offset)
12117 .addReg(/*Segment=*/0)
12118 .addReg(MI->getOperand(i).getReg())
12119 .addMemOperand(MMO);
12122 MI->eraseFromParent(); // The pseudo instruction is gone now.
12127 // The EFLAGS operand of SelectItr might be missing a kill marker
12128 // because there were multiple uses of EFLAGS, and ISel didn't know
12129 // which to mark. Figure out whether SelectItr should have had a
12130 // kill marker, and set it if it should. Returns the correct kill
12132 static bool checkAndUpdateEFLAGSKill(MachineBasicBlock::iterator SelectItr,
12133 MachineBasicBlock* BB,
12134 const TargetRegisterInfo* TRI) {
12135 // Scan forward through BB for a use/def of EFLAGS.
12136 MachineBasicBlock::iterator miI(llvm::next(SelectItr));
12137 for (MachineBasicBlock::iterator miE = BB->end(); miI != miE; ++miI) {
12138 const MachineInstr& mi = *miI;
12139 if (mi.readsRegister(X86::EFLAGS))
12141 if (mi.definesRegister(X86::EFLAGS))
12142 break; // Should have kill-flag - update below.
12145 // If we hit the end of the block, check whether EFLAGS is live into a
12147 if (miI == BB->end()) {
12148 for (MachineBasicBlock::succ_iterator sItr = BB->succ_begin(),
12149 sEnd = BB->succ_end();
12150 sItr != sEnd; ++sItr) {
12151 MachineBasicBlock* succ = *sItr;
12152 if (succ->isLiveIn(X86::EFLAGS))
12157 // We found a def, or hit the end of the basic block and EFLAGS wasn't live
12158 // out. SelectMI should have a kill flag on EFLAGS.
12159 SelectItr->addRegisterKilled(X86::EFLAGS, TRI);
12163 MachineBasicBlock *
12164 X86TargetLowering::EmitLoweredSelect(MachineInstr *MI,
12165 MachineBasicBlock *BB) const {
12166 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
12167 DebugLoc DL = MI->getDebugLoc();
12169 // To "insert" a SELECT_CC instruction, we actually have to insert the
12170 // diamond control-flow pattern. The incoming instruction knows the
12171 // destination vreg to set, the condition code register to branch on, the
12172 // true/false values to select between, and a branch opcode to use.
12173 const BasicBlock *LLVM_BB = BB->getBasicBlock();
12174 MachineFunction::iterator It = BB;
12180 // cmpTY ccX, r1, r2
12182 // fallthrough --> copy0MBB
12183 MachineBasicBlock *thisMBB = BB;
12184 MachineFunction *F = BB->getParent();
12185 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
12186 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
12187 F->insert(It, copy0MBB);
12188 F->insert(It, sinkMBB);
12190 // If the EFLAGS register isn't dead in the terminator, then claim that it's
12191 // live into the sink and copy blocks.
12192 const TargetRegisterInfo* TRI = getTargetMachine().getRegisterInfo();
12193 if (!MI->killsRegister(X86::EFLAGS) &&
12194 !checkAndUpdateEFLAGSKill(MI, BB, TRI)) {
12195 copy0MBB->addLiveIn(X86::EFLAGS);
12196 sinkMBB->addLiveIn(X86::EFLAGS);
12199 // Transfer the remainder of BB and its successor edges to sinkMBB.
12200 sinkMBB->splice(sinkMBB->begin(), BB,
12201 llvm::next(MachineBasicBlock::iterator(MI)),
12203 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
12205 // Add the true and fallthrough blocks as its successors.
12206 BB->addSuccessor(copy0MBB);
12207 BB->addSuccessor(sinkMBB);
12209 // Create the conditional branch instruction.
12211 X86::GetCondBranchFromCond((X86::CondCode)MI->getOperand(3).getImm());
12212 BuildMI(BB, DL, TII->get(Opc)).addMBB(sinkMBB);
12215 // %FalseValue = ...
12216 // # fallthrough to sinkMBB
12217 copy0MBB->addSuccessor(sinkMBB);
12220 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
12222 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
12223 TII->get(X86::PHI), MI->getOperand(0).getReg())
12224 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB)
12225 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
12227 MI->eraseFromParent(); // The pseudo instruction is gone now.
12231 MachineBasicBlock *
12232 X86TargetLowering::EmitLoweredSegAlloca(MachineInstr *MI, MachineBasicBlock *BB,
12233 bool Is64Bit) const {
12234 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
12235 DebugLoc DL = MI->getDebugLoc();
12236 MachineFunction *MF = BB->getParent();
12237 const BasicBlock *LLVM_BB = BB->getBasicBlock();
12239 assert(getTargetMachine().Options.EnableSegmentedStacks);
12241 unsigned TlsReg = Is64Bit ? X86::FS : X86::GS;
12242 unsigned TlsOffset = Is64Bit ? 0x70 : 0x30;
12245 // ... [Till the alloca]
12246 // If stacklet is not large enough, jump to mallocMBB
12249 // Allocate by subtracting from RSP
12250 // Jump to continueMBB
12253 // Allocate by call to runtime
12257 // [rest of original BB]
12260 MachineBasicBlock *mallocMBB = MF->CreateMachineBasicBlock(LLVM_BB);
12261 MachineBasicBlock *bumpMBB = MF->CreateMachineBasicBlock(LLVM_BB);
12262 MachineBasicBlock *continueMBB = MF->CreateMachineBasicBlock(LLVM_BB);
12264 MachineRegisterInfo &MRI = MF->getRegInfo();
12265 const TargetRegisterClass *AddrRegClass =
12266 getRegClassFor(Is64Bit ? MVT::i64:MVT::i32);
12268 unsigned mallocPtrVReg = MRI.createVirtualRegister(AddrRegClass),
12269 bumpSPPtrVReg = MRI.createVirtualRegister(AddrRegClass),
12270 tmpSPVReg = MRI.createVirtualRegister(AddrRegClass),
12271 SPLimitVReg = MRI.createVirtualRegister(AddrRegClass),
12272 sizeVReg = MI->getOperand(1).getReg(),
12273 physSPReg = Is64Bit ? X86::RSP : X86::ESP;
12275 MachineFunction::iterator MBBIter = BB;
12278 MF->insert(MBBIter, bumpMBB);
12279 MF->insert(MBBIter, mallocMBB);
12280 MF->insert(MBBIter, continueMBB);
12282 continueMBB->splice(continueMBB->begin(), BB, llvm::next
12283 (MachineBasicBlock::iterator(MI)), BB->end());
12284 continueMBB->transferSuccessorsAndUpdatePHIs(BB);
12286 // Add code to the main basic block to check if the stack limit has been hit,
12287 // and if so, jump to mallocMBB otherwise to bumpMBB.
12288 BuildMI(BB, DL, TII->get(TargetOpcode::COPY), tmpSPVReg).addReg(physSPReg);
12289 BuildMI(BB, DL, TII->get(Is64Bit ? X86::SUB64rr:X86::SUB32rr), SPLimitVReg)
12290 .addReg(tmpSPVReg).addReg(sizeVReg);
12291 BuildMI(BB, DL, TII->get(Is64Bit ? X86::CMP64mr:X86::CMP32mr))
12292 .addReg(0).addImm(1).addReg(0).addImm(TlsOffset).addReg(TlsReg)
12293 .addReg(SPLimitVReg);
12294 BuildMI(BB, DL, TII->get(X86::JG_4)).addMBB(mallocMBB);
12296 // bumpMBB simply decreases the stack pointer, since we know the current
12297 // stacklet has enough space.
12298 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), physSPReg)
12299 .addReg(SPLimitVReg);
12300 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), bumpSPPtrVReg)
12301 .addReg(SPLimitVReg);
12302 BuildMI(bumpMBB, DL, TII->get(X86::JMP_4)).addMBB(continueMBB);
12304 // Calls into a routine in libgcc to allocate more space from the heap.
12305 const uint32_t *RegMask =
12306 getTargetMachine().getRegisterInfo()->getCallPreservedMask(CallingConv::C);
12308 BuildMI(mallocMBB, DL, TII->get(X86::MOV64rr), X86::RDI)
12310 BuildMI(mallocMBB, DL, TII->get(X86::CALL64pcrel32))
12311 .addExternalSymbol("__morestack_allocate_stack_space").addReg(X86::RDI)
12312 .addRegMask(RegMask)
12313 .addReg(X86::RAX, RegState::ImplicitDefine);
12315 BuildMI(mallocMBB, DL, TII->get(X86::SUB32ri), physSPReg).addReg(physSPReg)
12317 BuildMI(mallocMBB, DL, TII->get(X86::PUSH32r)).addReg(sizeVReg);
12318 BuildMI(mallocMBB, DL, TII->get(X86::CALLpcrel32))
12319 .addExternalSymbol("__morestack_allocate_stack_space")
12320 .addRegMask(RegMask)
12321 .addReg(X86::EAX, RegState::ImplicitDefine);
12325 BuildMI(mallocMBB, DL, TII->get(X86::ADD32ri), physSPReg).addReg(physSPReg)
12328 BuildMI(mallocMBB, DL, TII->get(TargetOpcode::COPY), mallocPtrVReg)
12329 .addReg(Is64Bit ? X86::RAX : X86::EAX);
12330 BuildMI(mallocMBB, DL, TII->get(X86::JMP_4)).addMBB(continueMBB);
12332 // Set up the CFG correctly.
12333 BB->addSuccessor(bumpMBB);
12334 BB->addSuccessor(mallocMBB);
12335 mallocMBB->addSuccessor(continueMBB);
12336 bumpMBB->addSuccessor(continueMBB);
12338 // Take care of the PHI nodes.
12339 BuildMI(*continueMBB, continueMBB->begin(), DL, TII->get(X86::PHI),
12340 MI->getOperand(0).getReg())
12341 .addReg(mallocPtrVReg).addMBB(mallocMBB)
12342 .addReg(bumpSPPtrVReg).addMBB(bumpMBB);
12344 // Delete the original pseudo instruction.
12345 MI->eraseFromParent();
12348 return continueMBB;
12351 MachineBasicBlock *
12352 X86TargetLowering::EmitLoweredWinAlloca(MachineInstr *MI,
12353 MachineBasicBlock *BB) const {
12354 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
12355 DebugLoc DL = MI->getDebugLoc();
12357 assert(!Subtarget->isTargetEnvMacho());
12359 // The lowering is pretty easy: we're just emitting the call to _alloca. The
12360 // non-trivial part is impdef of ESP.
12362 if (Subtarget->isTargetWin64()) {
12363 if (Subtarget->isTargetCygMing()) {
12364 // ___chkstk(Mingw64):
12365 // Clobbers R10, R11, RAX and EFLAGS.
12367 BuildMI(*BB, MI, DL, TII->get(X86::W64ALLOCA))
12368 .addExternalSymbol("___chkstk")
12369 .addReg(X86::RAX, RegState::Implicit)
12370 .addReg(X86::RSP, RegState::Implicit)
12371 .addReg(X86::RAX, RegState::Define | RegState::Implicit)
12372 .addReg(X86::RSP, RegState::Define | RegState::Implicit)
12373 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
12375 // __chkstk(MSVCRT): does not update stack pointer.
12376 // Clobbers R10, R11 and EFLAGS.
12377 // FIXME: RAX(allocated size) might be reused and not killed.
12378 BuildMI(*BB, MI, DL, TII->get(X86::W64ALLOCA))
12379 .addExternalSymbol("__chkstk")
12380 .addReg(X86::RAX, RegState::Implicit)
12381 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
12382 // RAX has the offset to subtracted from RSP.
12383 BuildMI(*BB, MI, DL, TII->get(X86::SUB64rr), X86::RSP)
12388 const char *StackProbeSymbol =
12389 Subtarget->isTargetWindows() ? "_chkstk" : "_alloca";
12391 BuildMI(*BB, MI, DL, TII->get(X86::CALLpcrel32))
12392 .addExternalSymbol(StackProbeSymbol)
12393 .addReg(X86::EAX, RegState::Implicit)
12394 .addReg(X86::ESP, RegState::Implicit)
12395 .addReg(X86::EAX, RegState::Define | RegState::Implicit)
12396 .addReg(X86::ESP, RegState::Define | RegState::Implicit)
12397 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
12400 MI->eraseFromParent(); // The pseudo instruction is gone now.
12404 MachineBasicBlock *
12405 X86TargetLowering::EmitLoweredTLSCall(MachineInstr *MI,
12406 MachineBasicBlock *BB) const {
12407 // This is pretty easy. We're taking the value that we received from
12408 // our load from the relocation, sticking it in either RDI (x86-64)
12409 // or EAX and doing an indirect call. The return value will then
12410 // be in the normal return register.
12411 const X86InstrInfo *TII
12412 = static_cast<const X86InstrInfo*>(getTargetMachine().getInstrInfo());
12413 DebugLoc DL = MI->getDebugLoc();
12414 MachineFunction *F = BB->getParent();
12416 assert(Subtarget->isTargetDarwin() && "Darwin only instr emitted?");
12417 assert(MI->getOperand(3).isGlobal() && "This should be a global");
12419 // Get a register mask for the lowered call.
12420 // FIXME: The 32-bit calls have non-standard calling conventions. Use a
12421 // proper register mask.
12422 const uint32_t *RegMask =
12423 getTargetMachine().getRegisterInfo()->getCallPreservedMask(CallingConv::C);
12424 if (Subtarget->is64Bit()) {
12425 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
12426 TII->get(X86::MOV64rm), X86::RDI)
12428 .addImm(0).addReg(0)
12429 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
12430 MI->getOperand(3).getTargetFlags())
12432 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL64m));
12433 addDirectMem(MIB, X86::RDI);
12434 MIB.addReg(X86::RAX, RegState::ImplicitDefine).addRegMask(RegMask);
12435 } else if (getTargetMachine().getRelocationModel() != Reloc::PIC_) {
12436 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
12437 TII->get(X86::MOV32rm), X86::EAX)
12439 .addImm(0).addReg(0)
12440 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
12441 MI->getOperand(3).getTargetFlags())
12443 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
12444 addDirectMem(MIB, X86::EAX);
12445 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask);
12447 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
12448 TII->get(X86::MOV32rm), X86::EAX)
12449 .addReg(TII->getGlobalBaseReg(F))
12450 .addImm(0).addReg(0)
12451 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
12452 MI->getOperand(3).getTargetFlags())
12454 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
12455 addDirectMem(MIB, X86::EAX);
12456 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask);
12459 MI->eraseFromParent(); // The pseudo instruction is gone now.
12463 MachineBasicBlock *
12464 X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
12465 MachineBasicBlock *BB) const {
12466 switch (MI->getOpcode()) {
12467 default: llvm_unreachable("Unexpected instr type to insert");
12468 case X86::TAILJMPd64:
12469 case X86::TAILJMPr64:
12470 case X86::TAILJMPm64:
12471 llvm_unreachable("TAILJMP64 would not be touched here.");
12472 case X86::TCRETURNdi64:
12473 case X86::TCRETURNri64:
12474 case X86::TCRETURNmi64:
12476 case X86::WIN_ALLOCA:
12477 return EmitLoweredWinAlloca(MI, BB);
12478 case X86::SEG_ALLOCA_32:
12479 return EmitLoweredSegAlloca(MI, BB, false);
12480 case X86::SEG_ALLOCA_64:
12481 return EmitLoweredSegAlloca(MI, BB, true);
12482 case X86::TLSCall_32:
12483 case X86::TLSCall_64:
12484 return EmitLoweredTLSCall(MI, BB);
12485 case X86::CMOV_GR8:
12486 case X86::CMOV_FR32:
12487 case X86::CMOV_FR64:
12488 case X86::CMOV_V4F32:
12489 case X86::CMOV_V2F64:
12490 case X86::CMOV_V2I64:
12491 case X86::CMOV_V8F32:
12492 case X86::CMOV_V4F64:
12493 case X86::CMOV_V4I64:
12494 case X86::CMOV_GR16:
12495 case X86::CMOV_GR32:
12496 case X86::CMOV_RFP32:
12497 case X86::CMOV_RFP64:
12498 case X86::CMOV_RFP80:
12499 return EmitLoweredSelect(MI, BB);
12501 case X86::FP32_TO_INT16_IN_MEM:
12502 case X86::FP32_TO_INT32_IN_MEM:
12503 case X86::FP32_TO_INT64_IN_MEM:
12504 case X86::FP64_TO_INT16_IN_MEM:
12505 case X86::FP64_TO_INT32_IN_MEM:
12506 case X86::FP64_TO_INT64_IN_MEM:
12507 case X86::FP80_TO_INT16_IN_MEM:
12508 case X86::FP80_TO_INT32_IN_MEM:
12509 case X86::FP80_TO_INT64_IN_MEM: {
12510 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
12511 DebugLoc DL = MI->getDebugLoc();
12513 // Change the floating point control register to use "round towards zero"
12514 // mode when truncating to an integer value.
12515 MachineFunction *F = BB->getParent();
12516 int CWFrameIdx = F->getFrameInfo()->CreateStackObject(2, 2, false);
12517 addFrameReference(BuildMI(*BB, MI, DL,
12518 TII->get(X86::FNSTCW16m)), CWFrameIdx);
12520 // Load the old value of the high byte of the control word...
12522 F->getRegInfo().createVirtualRegister(&X86::GR16RegClass);
12523 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16rm), OldCW),
12526 // Set the high part to be round to zero...
12527 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mi)), CWFrameIdx)
12530 // Reload the modified control word now...
12531 addFrameReference(BuildMI(*BB, MI, DL,
12532 TII->get(X86::FLDCW16m)), CWFrameIdx);
12534 // Restore the memory image of control word to original value
12535 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mr)), CWFrameIdx)
12538 // Get the X86 opcode to use.
12540 switch (MI->getOpcode()) {
12541 default: llvm_unreachable("illegal opcode!");
12542 case X86::FP32_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m32; break;
12543 case X86::FP32_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m32; break;
12544 case X86::FP32_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m32; break;
12545 case X86::FP64_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m64; break;
12546 case X86::FP64_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m64; break;
12547 case X86::FP64_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m64; break;
12548 case X86::FP80_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m80; break;
12549 case X86::FP80_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m80; break;
12550 case X86::FP80_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m80; break;
12554 MachineOperand &Op = MI->getOperand(0);
12556 AM.BaseType = X86AddressMode::RegBase;
12557 AM.Base.Reg = Op.getReg();
12559 AM.BaseType = X86AddressMode::FrameIndexBase;
12560 AM.Base.FrameIndex = Op.getIndex();
12562 Op = MI->getOperand(1);
12564 AM.Scale = Op.getImm();
12565 Op = MI->getOperand(2);
12567 AM.IndexReg = Op.getImm();
12568 Op = MI->getOperand(3);
12569 if (Op.isGlobal()) {
12570 AM.GV = Op.getGlobal();
12572 AM.Disp = Op.getImm();
12574 addFullAddress(BuildMI(*BB, MI, DL, TII->get(Opc)), AM)
12575 .addReg(MI->getOperand(X86::AddrNumOperands).getReg());
12577 // Reload the original control word now.
12578 addFrameReference(BuildMI(*BB, MI, DL,
12579 TII->get(X86::FLDCW16m)), CWFrameIdx);
12581 MI->eraseFromParent(); // The pseudo instruction is gone now.
12584 // String/text processing lowering.
12585 case X86::PCMPISTRM128REG:
12586 case X86::VPCMPISTRM128REG:
12587 return EmitPCMP(MI, BB, 3, false /* in-mem */);
12588 case X86::PCMPISTRM128MEM:
12589 case X86::VPCMPISTRM128MEM:
12590 return EmitPCMP(MI, BB, 3, true /* in-mem */);
12591 case X86::PCMPESTRM128REG:
12592 case X86::VPCMPESTRM128REG:
12593 return EmitPCMP(MI, BB, 5, false /* in mem */);
12594 case X86::PCMPESTRM128MEM:
12595 case X86::VPCMPESTRM128MEM:
12596 return EmitPCMP(MI, BB, 5, true /* in mem */);
12598 // Thread synchronization.
12600 return EmitMonitor(MI, BB);
12602 return EmitMwait(MI, BB);
12604 // Atomic Lowering.
12605 case X86::ATOMAND32:
12606 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND32rr,
12607 X86::AND32ri, X86::MOV32rm,
12609 X86::NOT32r, X86::EAX,
12610 &X86::GR32RegClass);
12611 case X86::ATOMOR32:
12612 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR32rr,
12613 X86::OR32ri, X86::MOV32rm,
12615 X86::NOT32r, X86::EAX,
12616 &X86::GR32RegClass);
12617 case X86::ATOMXOR32:
12618 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR32rr,
12619 X86::XOR32ri, X86::MOV32rm,
12621 X86::NOT32r, X86::EAX,
12622 &X86::GR32RegClass);
12623 case X86::ATOMNAND32:
12624 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND32rr,
12625 X86::AND32ri, X86::MOV32rm,
12627 X86::NOT32r, X86::EAX,
12628 &X86::GR32RegClass, true);
12629 case X86::ATOMMIN32:
12630 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL32rr);
12631 case X86::ATOMMAX32:
12632 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG32rr);
12633 case X86::ATOMUMIN32:
12634 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB32rr);
12635 case X86::ATOMUMAX32:
12636 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA32rr);
12638 case X86::ATOMAND16:
12639 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND16rr,
12640 X86::AND16ri, X86::MOV16rm,
12642 X86::NOT16r, X86::AX,
12643 &X86::GR16RegClass);
12644 case X86::ATOMOR16:
12645 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR16rr,
12646 X86::OR16ri, X86::MOV16rm,
12648 X86::NOT16r, X86::AX,
12649 &X86::GR16RegClass);
12650 case X86::ATOMXOR16:
12651 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR16rr,
12652 X86::XOR16ri, X86::MOV16rm,
12654 X86::NOT16r, X86::AX,
12655 &X86::GR16RegClass);
12656 case X86::ATOMNAND16:
12657 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND16rr,
12658 X86::AND16ri, X86::MOV16rm,
12660 X86::NOT16r, X86::AX,
12661 &X86::GR16RegClass, true);
12662 case X86::ATOMMIN16:
12663 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL16rr);
12664 case X86::ATOMMAX16:
12665 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG16rr);
12666 case X86::ATOMUMIN16:
12667 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB16rr);
12668 case X86::ATOMUMAX16:
12669 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA16rr);
12671 case X86::ATOMAND8:
12672 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND8rr,
12673 X86::AND8ri, X86::MOV8rm,
12675 X86::NOT8r, X86::AL,
12676 &X86::GR8RegClass);
12678 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR8rr,
12679 X86::OR8ri, X86::MOV8rm,
12681 X86::NOT8r, X86::AL,
12682 &X86::GR8RegClass);
12683 case X86::ATOMXOR8:
12684 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR8rr,
12685 X86::XOR8ri, X86::MOV8rm,
12687 X86::NOT8r, X86::AL,
12688 &X86::GR8RegClass);
12689 case X86::ATOMNAND8:
12690 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND8rr,
12691 X86::AND8ri, X86::MOV8rm,
12693 X86::NOT8r, X86::AL,
12694 &X86::GR8RegClass, true);
12695 // FIXME: There are no CMOV8 instructions; MIN/MAX need some other way.
12696 // This group is for 64-bit host.
12697 case X86::ATOMAND64:
12698 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND64rr,
12699 X86::AND64ri32, X86::MOV64rm,
12701 X86::NOT64r, X86::RAX,
12702 &X86::GR64RegClass);
12703 case X86::ATOMOR64:
12704 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR64rr,
12705 X86::OR64ri32, X86::MOV64rm,
12707 X86::NOT64r, X86::RAX,
12708 &X86::GR64RegClass);
12709 case X86::ATOMXOR64:
12710 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR64rr,
12711 X86::XOR64ri32, X86::MOV64rm,
12713 X86::NOT64r, X86::RAX,
12714 &X86::GR64RegClass);
12715 case X86::ATOMNAND64:
12716 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND64rr,
12717 X86::AND64ri32, X86::MOV64rm,
12719 X86::NOT64r, X86::RAX,
12720 &X86::GR64RegClass, true);
12721 case X86::ATOMMIN64:
12722 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL64rr);
12723 case X86::ATOMMAX64:
12724 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG64rr);
12725 case X86::ATOMUMIN64:
12726 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB64rr);
12727 case X86::ATOMUMAX64:
12728 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA64rr);
12730 // This group does 64-bit operations on a 32-bit host.
12731 case X86::ATOMAND6432:
12732 return EmitAtomicBit6432WithCustomInserter(MI, BB,
12733 X86::AND32rr, X86::AND32rr,
12734 X86::AND32ri, X86::AND32ri,
12736 case X86::ATOMOR6432:
12737 return EmitAtomicBit6432WithCustomInserter(MI, BB,
12738 X86::OR32rr, X86::OR32rr,
12739 X86::OR32ri, X86::OR32ri,
12741 case X86::ATOMXOR6432:
12742 return EmitAtomicBit6432WithCustomInserter(MI, BB,
12743 X86::XOR32rr, X86::XOR32rr,
12744 X86::XOR32ri, X86::XOR32ri,
12746 case X86::ATOMNAND6432:
12747 return EmitAtomicBit6432WithCustomInserter(MI, BB,
12748 X86::AND32rr, X86::AND32rr,
12749 X86::AND32ri, X86::AND32ri,
12751 case X86::ATOMADD6432:
12752 return EmitAtomicBit6432WithCustomInserter(MI, BB,
12753 X86::ADD32rr, X86::ADC32rr,
12754 X86::ADD32ri, X86::ADC32ri,
12756 case X86::ATOMSUB6432:
12757 return EmitAtomicBit6432WithCustomInserter(MI, BB,
12758 X86::SUB32rr, X86::SBB32rr,
12759 X86::SUB32ri, X86::SBB32ri,
12761 case X86::ATOMSWAP6432:
12762 return EmitAtomicBit6432WithCustomInserter(MI, BB,
12763 X86::MOV32rr, X86::MOV32rr,
12764 X86::MOV32ri, X86::MOV32ri,
12766 case X86::VASTART_SAVE_XMM_REGS:
12767 return EmitVAStartSaveXMMRegsWithCustomInserter(MI, BB);
12769 case X86::VAARG_64:
12770 return EmitVAARG64WithCustomInserter(MI, BB);
12774 //===----------------------------------------------------------------------===//
12775 // X86 Optimization Hooks
12776 //===----------------------------------------------------------------------===//
12778 void X86TargetLowering::computeMaskedBitsForTargetNode(const SDValue Op,
12781 const SelectionDAG &DAG,
12782 unsigned Depth) const {
12783 unsigned BitWidth = KnownZero.getBitWidth();
12784 unsigned Opc = Op.getOpcode();
12785 assert((Opc >= ISD::BUILTIN_OP_END ||
12786 Opc == ISD::INTRINSIC_WO_CHAIN ||
12787 Opc == ISD::INTRINSIC_W_CHAIN ||
12788 Opc == ISD::INTRINSIC_VOID) &&
12789 "Should use MaskedValueIsZero if you don't know whether Op"
12790 " is a target node!");
12792 KnownZero = KnownOne = APInt(BitWidth, 0); // Don't know anything.
12806 // These nodes' second result is a boolean.
12807 if (Op.getResNo() == 0)
12810 case X86ISD::SETCC:
12811 KnownZero |= APInt::getHighBitsSet(BitWidth, BitWidth - 1);
12813 case ISD::INTRINSIC_WO_CHAIN: {
12814 unsigned IntId = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
12815 unsigned NumLoBits = 0;
12818 case Intrinsic::x86_sse_movmsk_ps:
12819 case Intrinsic::x86_avx_movmsk_ps_256:
12820 case Intrinsic::x86_sse2_movmsk_pd:
12821 case Intrinsic::x86_avx_movmsk_pd_256:
12822 case Intrinsic::x86_mmx_pmovmskb:
12823 case Intrinsic::x86_sse2_pmovmskb_128:
12824 case Intrinsic::x86_avx2_pmovmskb: {
12825 // High bits of movmskp{s|d}, pmovmskb are known zero.
12827 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
12828 case Intrinsic::x86_sse_movmsk_ps: NumLoBits = 4; break;
12829 case Intrinsic::x86_avx_movmsk_ps_256: NumLoBits = 8; break;
12830 case Intrinsic::x86_sse2_movmsk_pd: NumLoBits = 2; break;
12831 case Intrinsic::x86_avx_movmsk_pd_256: NumLoBits = 4; break;
12832 case Intrinsic::x86_mmx_pmovmskb: NumLoBits = 8; break;
12833 case Intrinsic::x86_sse2_pmovmskb_128: NumLoBits = 16; break;
12834 case Intrinsic::x86_avx2_pmovmskb: NumLoBits = 32; break;
12836 KnownZero = APInt::getHighBitsSet(BitWidth, BitWidth - NumLoBits);
12845 unsigned X86TargetLowering::ComputeNumSignBitsForTargetNode(SDValue Op,
12846 unsigned Depth) const {
12847 // SETCC_CARRY sets the dest to ~0 for true or 0 for false.
12848 if (Op.getOpcode() == X86ISD::SETCC_CARRY)
12849 return Op.getValueType().getScalarType().getSizeInBits();
12855 /// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the
12856 /// node is a GlobalAddress + offset.
12857 bool X86TargetLowering::isGAPlusOffset(SDNode *N,
12858 const GlobalValue* &GA,
12859 int64_t &Offset) const {
12860 if (N->getOpcode() == X86ISD::Wrapper) {
12861 if (isa<GlobalAddressSDNode>(N->getOperand(0))) {
12862 GA = cast<GlobalAddressSDNode>(N->getOperand(0))->getGlobal();
12863 Offset = cast<GlobalAddressSDNode>(N->getOperand(0))->getOffset();
12867 return TargetLowering::isGAPlusOffset(N, GA, Offset);
12870 /// isShuffleHigh128VectorInsertLow - Checks whether the shuffle node is the
12871 /// same as extracting the high 128-bit part of 256-bit vector and then
12872 /// inserting the result into the low part of a new 256-bit vector
12873 static bool isShuffleHigh128VectorInsertLow(ShuffleVectorSDNode *SVOp) {
12874 EVT VT = SVOp->getValueType(0);
12875 int NumElems = VT.getVectorNumElements();
12877 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
12878 for (int i = 0, j = NumElems/2; i < NumElems/2; ++i, ++j)
12879 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) ||
12880 SVOp->getMaskElt(j) >= 0)
12886 /// isShuffleLow128VectorInsertHigh - Checks whether the shuffle node is the
12887 /// same as extracting the low 128-bit part of 256-bit vector and then
12888 /// inserting the result into the high part of a new 256-bit vector
12889 static bool isShuffleLow128VectorInsertHigh(ShuffleVectorSDNode *SVOp) {
12890 EVT VT = SVOp->getValueType(0);
12891 int NumElems = VT.getVectorNumElements();
12893 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
12894 for (int i = NumElems/2, j = 0; i < NumElems; ++i, ++j)
12895 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) ||
12896 SVOp->getMaskElt(j) >= 0)
12902 /// PerformShuffleCombine256 - Performs shuffle combines for 256-bit vectors.
12903 static SDValue PerformShuffleCombine256(SDNode *N, SelectionDAG &DAG,
12904 TargetLowering::DAGCombinerInfo &DCI,
12905 const X86Subtarget* Subtarget) {
12906 DebugLoc dl = N->getDebugLoc();
12907 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
12908 SDValue V1 = SVOp->getOperand(0);
12909 SDValue V2 = SVOp->getOperand(1);
12910 EVT VT = SVOp->getValueType(0);
12911 int NumElems = VT.getVectorNumElements();
12913 if (V1.getOpcode() == ISD::CONCAT_VECTORS &&
12914 V2.getOpcode() == ISD::CONCAT_VECTORS) {
12918 // V UNDEF BUILD_VECTOR UNDEF
12920 // CONCAT_VECTOR CONCAT_VECTOR
12923 // RESULT: V + zero extended
12925 if (V2.getOperand(0).getOpcode() != ISD::BUILD_VECTOR ||
12926 V2.getOperand(1).getOpcode() != ISD::UNDEF ||
12927 V1.getOperand(1).getOpcode() != ISD::UNDEF)
12930 if (!ISD::isBuildVectorAllZeros(V2.getOperand(0).getNode()))
12933 // To match the shuffle mask, the first half of the mask should
12934 // be exactly the first vector, and all the rest a splat with the
12935 // first element of the second one.
12936 for (int i = 0; i < NumElems/2; ++i)
12937 if (!isUndefOrEqual(SVOp->getMaskElt(i), i) ||
12938 !isUndefOrEqual(SVOp->getMaskElt(i+NumElems/2), NumElems))
12941 // If V1 is coming from a vector load then just fold to a VZEXT_LOAD.
12942 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(V1.getOperand(0))) {
12943 SDVTList Tys = DAG.getVTList(MVT::v4i64, MVT::Other);
12944 SDValue Ops[] = { Ld->getChain(), Ld->getBasePtr() };
12946 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, dl, Tys, Ops, 2,
12948 Ld->getPointerInfo(),
12949 Ld->getAlignment(),
12950 false/*isVolatile*/, true/*ReadMem*/,
12951 false/*WriteMem*/);
12952 return DAG.getNode(ISD::BITCAST, dl, VT, ResNode);
12955 // Emit a zeroed vector and insert the desired subvector on its
12957 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
12958 SDValue InsV = Insert128BitVector(Zeros, V1.getOperand(0),
12959 DAG.getConstant(0, MVT::i32), DAG, dl);
12960 return DCI.CombineTo(N, InsV);
12963 //===--------------------------------------------------------------------===//
12964 // Combine some shuffles into subvector extracts and inserts:
12967 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
12968 if (isShuffleHigh128VectorInsertLow(SVOp)) {
12969 SDValue V = Extract128BitVector(V1, DAG.getConstant(NumElems/2, MVT::i32),
12971 SDValue InsV = Insert128BitVector(DAG.getNode(ISD::UNDEF, dl, VT),
12972 V, DAG.getConstant(0, MVT::i32), DAG, dl);
12973 return DCI.CombineTo(N, InsV);
12976 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
12977 if (isShuffleLow128VectorInsertHigh(SVOp)) {
12978 SDValue V = Extract128BitVector(V1, DAG.getConstant(0, MVT::i32), DAG, dl);
12979 SDValue InsV = Insert128BitVector(DAG.getNode(ISD::UNDEF, dl, VT),
12980 V, DAG.getConstant(NumElems/2, MVT::i32), DAG, dl);
12981 return DCI.CombineTo(N, InsV);
12987 /// PerformShuffleCombine - Performs several different shuffle combines.
12988 static SDValue PerformShuffleCombine(SDNode *N, SelectionDAG &DAG,
12989 TargetLowering::DAGCombinerInfo &DCI,
12990 const X86Subtarget *Subtarget) {
12991 DebugLoc dl = N->getDebugLoc();
12992 EVT VT = N->getValueType(0);
12994 // Don't create instructions with illegal types after legalize types has run.
12995 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
12996 if (!DCI.isBeforeLegalize() && !TLI.isTypeLegal(VT.getVectorElementType()))
12999 // Combine 256-bit vector shuffles. This is only profitable when in AVX mode
13000 if (Subtarget->hasAVX() && VT.getSizeInBits() == 256 &&
13001 N->getOpcode() == ISD::VECTOR_SHUFFLE)
13002 return PerformShuffleCombine256(N, DAG, DCI, Subtarget);
13004 // Only handle 128 wide vector from here on.
13005 if (VT.getSizeInBits() != 128)
13008 // Combine a vector_shuffle that is equal to build_vector load1, load2, load3,
13009 // load4, <0, 1, 2, 3> into a 128-bit load if the load addresses are
13010 // consecutive, non-overlapping, and in the right order.
13011 SmallVector<SDValue, 16> Elts;
13012 for (unsigned i = 0, e = VT.getVectorNumElements(); i != e; ++i)
13013 Elts.push_back(getShuffleScalarElt(N, i, DAG, 0));
13015 return EltsFromConsecutiveLoads(VT, Elts, dl, DAG);
13019 /// PerformTruncateCombine - Converts truncate operation to
13020 /// a sequence of vector shuffle operations.
13021 /// It is possible when we truncate 256-bit vector to 128-bit vector
13023 SDValue X86TargetLowering::PerformTruncateCombine(SDNode *N, SelectionDAG &DAG,
13024 DAGCombinerInfo &DCI) const {
13025 if (!DCI.isBeforeLegalizeOps())
13028 if (!Subtarget->hasAVX()) return SDValue();
13030 EVT VT = N->getValueType(0);
13031 SDValue Op = N->getOperand(0);
13032 EVT OpVT = Op.getValueType();
13033 DebugLoc dl = N->getDebugLoc();
13035 if ((VT == MVT::v4i32) && (OpVT == MVT::v4i64)) {
13037 if (Subtarget->hasAVX2()) {
13038 // AVX2: v4i64 -> v4i32
13041 static const int ShufMask[] = {0, 2, 4, 6, -1, -1, -1, -1};
13043 Op = DAG.getNode(ISD::BITCAST, dl, MVT::v8i32, Op);
13044 Op = DAG.getVectorShuffle(MVT::v8i32, dl, Op, DAG.getUNDEF(MVT::v8i32),
13047 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, Op, DAG.getIntPtrConstant(0));
13050 // AVX: v4i64 -> v4i32
13051 SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v2i64, Op,
13052 DAG.getIntPtrConstant(0));
13054 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v2i64, Op,
13055 DAG.getIntPtrConstant(2));
13057 OpLo = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, OpLo);
13058 OpHi = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, OpHi);
13061 static const int ShufMask1[] = {0, 2, 0, 0};
13063 OpLo = DAG.getVectorShuffle(VT, dl, OpLo, DAG.getUNDEF(VT),
13065 OpHi = DAG.getVectorShuffle(VT, dl, OpHi, DAG.getUNDEF(VT),
13069 static const int ShufMask2[] = {0, 1, 4, 5};
13071 return DAG.getVectorShuffle(VT, dl, OpLo, OpHi, ShufMask2);
13073 if ((VT == MVT::v8i16) && (OpVT == MVT::v8i32)) {
13075 if (Subtarget->hasAVX2()) {
13076 // AVX2: v8i32 -> v8i16
13078 Op = DAG.getNode(ISD::BITCAST, dl, MVT::v32i8, Op);
13080 SmallVector<SDValue,32> pshufbMask;
13081 for (unsigned i = 0; i < 2; ++i) {
13082 pshufbMask.push_back(DAG.getConstant(0x0, MVT::i8));
13083 pshufbMask.push_back(DAG.getConstant(0x1, MVT::i8));
13084 pshufbMask.push_back(DAG.getConstant(0x4, MVT::i8));
13085 pshufbMask.push_back(DAG.getConstant(0x5, MVT::i8));
13086 pshufbMask.push_back(DAG.getConstant(0x8, MVT::i8));
13087 pshufbMask.push_back(DAG.getConstant(0x9, MVT::i8));
13088 pshufbMask.push_back(DAG.getConstant(0xc, MVT::i8));
13089 pshufbMask.push_back(DAG.getConstant(0xd, MVT::i8));
13090 for (unsigned j = 0; j < 8; ++j)
13091 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
13093 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v32i8, &pshufbMask[0],
13095 Op = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v32i8, Op, BV);
13097 Op = DAG.getNode(ISD::BITCAST, dl, MVT::v4i64, Op);
13099 static const int ShufMask[] = {0, 2, -1, -1};
13100 Op = DAG.getVectorShuffle(MVT::v4i64, dl, Op, DAG.getUNDEF(MVT::v4i64),
13103 Op = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v2i64, Op,
13104 DAG.getIntPtrConstant(0));
13106 return DAG.getNode(ISD::BITCAST, dl, VT, Op);
13109 SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i32, Op,
13110 DAG.getIntPtrConstant(0));
13112 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i32, Op,
13113 DAG.getIntPtrConstant(4));
13115 OpLo = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, OpLo);
13116 OpHi = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, OpHi);
13119 static const int ShufMask1[] = {0, 1, 4, 5, 8, 9, 12, 13,
13120 -1, -1, -1, -1, -1, -1, -1, -1};
13122 OpLo = DAG.getVectorShuffle(MVT::v16i8, dl, OpLo,
13123 DAG.getUNDEF(MVT::v16i8),
13125 OpHi = DAG.getVectorShuffle(MVT::v16i8, dl, OpHi,
13126 DAG.getUNDEF(MVT::v16i8),
13129 OpLo = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, OpLo);
13130 OpHi = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, OpHi);
13133 static const int ShufMask2[] = {0, 1, 4, 5};
13135 SDValue res = DAG.getVectorShuffle(MVT::v4i32, dl, OpLo, OpHi, ShufMask2);
13136 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, res);
13142 /// XFormVExtractWithShuffleIntoLoad - Check if a vector extract from a target
13143 /// specific shuffle of a load can be folded into a single element load.
13144 /// Similar handling for VECTOR_SHUFFLE is performed by DAGCombiner, but
13145 /// shuffles have been customed lowered so we need to handle those here.
13146 static SDValue XFormVExtractWithShuffleIntoLoad(SDNode *N, SelectionDAG &DAG,
13147 TargetLowering::DAGCombinerInfo &DCI) {
13148 if (DCI.isBeforeLegalizeOps())
13151 SDValue InVec = N->getOperand(0);
13152 SDValue EltNo = N->getOperand(1);
13154 if (!isa<ConstantSDNode>(EltNo))
13157 EVT VT = InVec.getValueType();
13159 bool HasShuffleIntoBitcast = false;
13160 if (InVec.getOpcode() == ISD::BITCAST) {
13161 // Don't duplicate a load with other uses.
13162 if (!InVec.hasOneUse())
13164 EVT BCVT = InVec.getOperand(0).getValueType();
13165 if (BCVT.getVectorNumElements() != VT.getVectorNumElements())
13167 InVec = InVec.getOperand(0);
13168 HasShuffleIntoBitcast = true;
13171 if (!isTargetShuffle(InVec.getOpcode()))
13174 // Don't duplicate a load with other uses.
13175 if (!InVec.hasOneUse())
13178 SmallVector<int, 16> ShuffleMask;
13180 if (!getTargetShuffleMask(InVec.getNode(), VT, ShuffleMask, UnaryShuffle))
13183 // Select the input vector, guarding against out of range extract vector.
13184 unsigned NumElems = VT.getVectorNumElements();
13185 int Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();
13186 int Idx = (Elt > (int)NumElems) ? -1 : ShuffleMask[Elt];
13187 SDValue LdNode = (Idx < (int)NumElems) ? InVec.getOperand(0)
13188 : InVec.getOperand(1);
13190 // If inputs to shuffle are the same for both ops, then allow 2 uses
13191 unsigned AllowedUses = InVec.getOperand(0) == InVec.getOperand(1) ? 2 : 1;
13193 if (LdNode.getOpcode() == ISD::BITCAST) {
13194 // Don't duplicate a load with other uses.
13195 if (!LdNode.getNode()->hasNUsesOfValue(AllowedUses, 0))
13198 AllowedUses = 1; // only allow 1 load use if we have a bitcast
13199 LdNode = LdNode.getOperand(0);
13202 if (!ISD::isNormalLoad(LdNode.getNode()))
13205 LoadSDNode *LN0 = cast<LoadSDNode>(LdNode);
13207 if (!LN0 ||!LN0->hasNUsesOfValue(AllowedUses, 0) || LN0->isVolatile())
13210 if (HasShuffleIntoBitcast) {
13211 // If there's a bitcast before the shuffle, check if the load type and
13212 // alignment is valid.
13213 unsigned Align = LN0->getAlignment();
13214 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
13215 unsigned NewAlign = TLI.getTargetData()->
13216 getABITypeAlignment(VT.getTypeForEVT(*DAG.getContext()));
13218 if (NewAlign > Align || !TLI.isOperationLegalOrCustom(ISD::LOAD, VT))
13222 // All checks match so transform back to vector_shuffle so that DAG combiner
13223 // can finish the job
13224 DebugLoc dl = N->getDebugLoc();
13226 // Create shuffle node taking into account the case that its a unary shuffle
13227 SDValue Shuffle = (UnaryShuffle) ? DAG.getUNDEF(VT) : InVec.getOperand(1);
13228 Shuffle = DAG.getVectorShuffle(InVec.getValueType(), dl,
13229 InVec.getOperand(0), Shuffle,
13231 Shuffle = DAG.getNode(ISD::BITCAST, dl, VT, Shuffle);
13232 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, N->getValueType(0), Shuffle,
13236 /// PerformEXTRACT_VECTOR_ELTCombine - Detect vector gather/scatter index
13237 /// generation and convert it from being a bunch of shuffles and extracts
13238 /// to a simple store and scalar loads to extract the elements.
13239 static SDValue PerformEXTRACT_VECTOR_ELTCombine(SDNode *N, SelectionDAG &DAG,
13240 TargetLowering::DAGCombinerInfo &DCI) {
13241 SDValue NewOp = XFormVExtractWithShuffleIntoLoad(N, DAG, DCI);
13242 if (NewOp.getNode())
13245 SDValue InputVector = N->getOperand(0);
13247 // Only operate on vectors of 4 elements, where the alternative shuffling
13248 // gets to be more expensive.
13249 if (InputVector.getValueType() != MVT::v4i32)
13252 // Check whether every use of InputVector is an EXTRACT_VECTOR_ELT with a
13253 // single use which is a sign-extend or zero-extend, and all elements are
13255 SmallVector<SDNode *, 4> Uses;
13256 unsigned ExtractedElements = 0;
13257 for (SDNode::use_iterator UI = InputVector.getNode()->use_begin(),
13258 UE = InputVector.getNode()->use_end(); UI != UE; ++UI) {
13259 if (UI.getUse().getResNo() != InputVector.getResNo())
13262 SDNode *Extract = *UI;
13263 if (Extract->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
13266 if (Extract->getValueType(0) != MVT::i32)
13268 if (!Extract->hasOneUse())
13270 if (Extract->use_begin()->getOpcode() != ISD::SIGN_EXTEND &&
13271 Extract->use_begin()->getOpcode() != ISD::ZERO_EXTEND)
13273 if (!isa<ConstantSDNode>(Extract->getOperand(1)))
13276 // Record which element was extracted.
13277 ExtractedElements |=
13278 1 << cast<ConstantSDNode>(Extract->getOperand(1))->getZExtValue();
13280 Uses.push_back(Extract);
13283 // If not all the elements were used, this may not be worthwhile.
13284 if (ExtractedElements != 15)
13287 // Ok, we've now decided to do the transformation.
13288 DebugLoc dl = InputVector.getDebugLoc();
13290 // Store the value to a temporary stack slot.
13291 SDValue StackPtr = DAG.CreateStackTemporary(InputVector.getValueType());
13292 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, InputVector, StackPtr,
13293 MachinePointerInfo(), false, false, 0);
13295 // Replace each use (extract) with a load of the appropriate element.
13296 for (SmallVectorImpl<SDNode *>::iterator UI = Uses.begin(),
13297 UE = Uses.end(); UI != UE; ++UI) {
13298 SDNode *Extract = *UI;
13300 // cOMpute the element's address.
13301 SDValue Idx = Extract->getOperand(1);
13303 InputVector.getValueType().getVectorElementType().getSizeInBits()/8;
13304 uint64_t Offset = EltSize * cast<ConstantSDNode>(Idx)->getZExtValue();
13305 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
13306 SDValue OffsetVal = DAG.getConstant(Offset, TLI.getPointerTy());
13308 SDValue ScalarAddr = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(),
13309 StackPtr, OffsetVal);
13311 // Load the scalar.
13312 SDValue LoadScalar = DAG.getLoad(Extract->getValueType(0), dl, Ch,
13313 ScalarAddr, MachinePointerInfo(),
13314 false, false, false, 0);
13316 // Replace the exact with the load.
13317 DAG.ReplaceAllUsesOfValueWith(SDValue(Extract, 0), LoadScalar);
13320 // The replacement was made in place; don't return anything.
13324 /// PerformSELECTCombine - Do target-specific dag combines on SELECT and VSELECT
13326 static SDValue PerformSELECTCombine(SDNode *N, SelectionDAG &DAG,
13327 TargetLowering::DAGCombinerInfo &DCI,
13328 const X86Subtarget *Subtarget) {
13331 DebugLoc DL = N->getDebugLoc();
13332 SDValue Cond = N->getOperand(0);
13333 // Get the LHS/RHS of the select.
13334 SDValue LHS = N->getOperand(1);
13335 SDValue RHS = N->getOperand(2);
13336 EVT VT = LHS.getValueType();
13338 // If we have SSE[12] support, try to form min/max nodes. SSE min/max
13339 // instructions match the semantics of the common C idiom x<y?x:y but not
13340 // x<=y?x:y, because of how they handle negative zero (which can be
13341 // ignored in unsafe-math mode).
13342 if (Cond.getOpcode() == ISD::SETCC && VT.isFloatingPoint() &&
13343 VT != MVT::f80 && DAG.getTargetLoweringInfo().isTypeLegal(VT) &&
13344 (Subtarget->hasSSE2() ||
13345 (Subtarget->hasSSE1() && VT.getScalarType() == MVT::f32))) {
13346 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
13348 unsigned Opcode = 0;
13349 // Check for x CC y ? x : y.
13350 if (DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
13351 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
13355 // Converting this to a min would handle NaNs incorrectly, and swapping
13356 // the operands would cause it to handle comparisons between positive
13357 // and negative zero incorrectly.
13358 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
13359 if (!DAG.getTarget().Options.UnsafeFPMath &&
13360 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
13362 std::swap(LHS, RHS);
13364 Opcode = X86ISD::FMIN;
13367 // Converting this to a min would handle comparisons between positive
13368 // and negative zero incorrectly.
13369 if (!DAG.getTarget().Options.UnsafeFPMath &&
13370 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
13372 Opcode = X86ISD::FMIN;
13375 // Converting this to a min would handle both negative zeros and NaNs
13376 // incorrectly, but we can swap the operands to fix both.
13377 std::swap(LHS, RHS);
13381 Opcode = X86ISD::FMIN;
13385 // Converting this to a max would handle comparisons between positive
13386 // and negative zero incorrectly.
13387 if (!DAG.getTarget().Options.UnsafeFPMath &&
13388 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
13390 Opcode = X86ISD::FMAX;
13393 // Converting this to a max would handle NaNs incorrectly, and swapping
13394 // the operands would cause it to handle comparisons between positive
13395 // and negative zero incorrectly.
13396 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
13397 if (!DAG.getTarget().Options.UnsafeFPMath &&
13398 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
13400 std::swap(LHS, RHS);
13402 Opcode = X86ISD::FMAX;
13405 // Converting this to a max would handle both negative zeros and NaNs
13406 // incorrectly, but we can swap the operands to fix both.
13407 std::swap(LHS, RHS);
13411 Opcode = X86ISD::FMAX;
13414 // Check for x CC y ? y : x -- a min/max with reversed arms.
13415 } else if (DAG.isEqualTo(LHS, Cond.getOperand(1)) &&
13416 DAG.isEqualTo(RHS, Cond.getOperand(0))) {
13420 // Converting this to a min would handle comparisons between positive
13421 // and negative zero incorrectly, and swapping the operands would
13422 // cause it to handle NaNs incorrectly.
13423 if (!DAG.getTarget().Options.UnsafeFPMath &&
13424 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS))) {
13425 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
13427 std::swap(LHS, RHS);
13429 Opcode = X86ISD::FMIN;
13432 // Converting this to a min would handle NaNs incorrectly.
13433 if (!DAG.getTarget().Options.UnsafeFPMath &&
13434 (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)))
13436 Opcode = X86ISD::FMIN;
13439 // Converting this to a min would handle both negative zeros and NaNs
13440 // incorrectly, but we can swap the operands to fix both.
13441 std::swap(LHS, RHS);
13445 Opcode = X86ISD::FMIN;
13449 // Converting this to a max would handle NaNs incorrectly.
13450 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
13452 Opcode = X86ISD::FMAX;
13455 // Converting this to a max would handle comparisons between positive
13456 // and negative zero incorrectly, and swapping the operands would
13457 // cause it to handle NaNs incorrectly.
13458 if (!DAG.getTarget().Options.UnsafeFPMath &&
13459 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS)) {
13460 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
13462 std::swap(LHS, RHS);
13464 Opcode = X86ISD::FMAX;
13467 // Converting this to a max would handle both negative zeros and NaNs
13468 // incorrectly, but we can swap the operands to fix both.
13469 std::swap(LHS, RHS);
13473 Opcode = X86ISD::FMAX;
13479 return DAG.getNode(Opcode, DL, N->getValueType(0), LHS, RHS);
13482 // If this is a select between two integer constants, try to do some
13484 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(LHS)) {
13485 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(RHS))
13486 // Don't do this for crazy integer types.
13487 if (DAG.getTargetLoweringInfo().isTypeLegal(LHS.getValueType())) {
13488 // If this is efficiently invertible, canonicalize the LHSC/RHSC values
13489 // so that TrueC (the true value) is larger than FalseC.
13490 bool NeedsCondInvert = false;
13492 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue()) &&
13493 // Efficiently invertible.
13494 (Cond.getOpcode() == ISD::SETCC || // setcc -> invertible.
13495 (Cond.getOpcode() == ISD::XOR && // xor(X, C) -> invertible.
13496 isa<ConstantSDNode>(Cond.getOperand(1))))) {
13497 NeedsCondInvert = true;
13498 std::swap(TrueC, FalseC);
13501 // Optimize C ? 8 : 0 -> zext(C) << 3. Likewise for any pow2/0.
13502 if (FalseC->getAPIntValue() == 0 &&
13503 TrueC->getAPIntValue().isPowerOf2()) {
13504 if (NeedsCondInvert) // Invert the condition if needed.
13505 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
13506 DAG.getConstant(1, Cond.getValueType()));
13508 // Zero extend the condition if needed.
13509 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, LHS.getValueType(), Cond);
13511 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
13512 return DAG.getNode(ISD::SHL, DL, LHS.getValueType(), Cond,
13513 DAG.getConstant(ShAmt, MVT::i8));
13516 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst.
13517 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
13518 if (NeedsCondInvert) // Invert the condition if needed.
13519 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
13520 DAG.getConstant(1, Cond.getValueType()));
13522 // Zero extend the condition if needed.
13523 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
13524 FalseC->getValueType(0), Cond);
13525 return DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
13526 SDValue(FalseC, 0));
13529 // Optimize cases that will turn into an LEA instruction. This requires
13530 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
13531 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
13532 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
13533 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
13535 bool isFastMultiplier = false;
13537 switch ((unsigned char)Diff) {
13539 case 1: // result = add base, cond
13540 case 2: // result = lea base( , cond*2)
13541 case 3: // result = lea base(cond, cond*2)
13542 case 4: // result = lea base( , cond*4)
13543 case 5: // result = lea base(cond, cond*4)
13544 case 8: // result = lea base( , cond*8)
13545 case 9: // result = lea base(cond, cond*8)
13546 isFastMultiplier = true;
13551 if (isFastMultiplier) {
13552 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
13553 if (NeedsCondInvert) // Invert the condition if needed.
13554 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
13555 DAG.getConstant(1, Cond.getValueType()));
13557 // Zero extend the condition if needed.
13558 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
13560 // Scale the condition by the difference.
13562 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
13563 DAG.getConstant(Diff, Cond.getValueType()));
13565 // Add the base if non-zero.
13566 if (FalseC->getAPIntValue() != 0)
13567 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
13568 SDValue(FalseC, 0));
13575 // Canonicalize max and min:
13576 // (x > y) ? x : y -> (x >= y) ? x : y
13577 // (x < y) ? x : y -> (x <= y) ? x : y
13578 // This allows use of COND_S / COND_NS (see TranslateX86CC) which eliminates
13579 // the need for an extra compare
13580 // against zero. e.g.
13581 // (x - y) > 0 : (x - y) ? 0 -> (x - y) >= 0 : (x - y) ? 0
13583 // testl %edi, %edi
13585 // cmovgl %edi, %eax
13589 // cmovsl %eax, %edi
13590 if (N->getOpcode() == ISD::SELECT && Cond.getOpcode() == ISD::SETCC &&
13591 DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
13592 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
13593 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
13598 ISD::CondCode NewCC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGE;
13599 Cond = DAG.getSetCC(Cond.getDebugLoc(), Cond.getValueType(),
13600 Cond.getOperand(0), Cond.getOperand(1), NewCC);
13601 return DAG.getNode(ISD::SELECT, DL, VT, Cond, LHS, RHS);
13606 // If we know that this node is legal then we know that it is going to be
13607 // matched by one of the SSE/AVX BLEND instructions. These instructions only
13608 // depend on the highest bit in each word. Try to use SimplifyDemandedBits
13609 // to simplify previous instructions.
13610 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
13611 if (N->getOpcode() == ISD::VSELECT && DCI.isBeforeLegalizeOps() &&
13612 !DCI.isBeforeLegalize() &&
13613 TLI.isOperationLegal(ISD::VSELECT, VT)) {
13614 unsigned BitWidth = Cond.getValueType().getScalarType().getSizeInBits();
13615 assert(BitWidth >= 8 && BitWidth <= 64 && "Invalid mask size");
13616 APInt DemandedMask = APInt::getHighBitsSet(BitWidth, 1);
13618 APInt KnownZero, KnownOne;
13619 TargetLowering::TargetLoweringOpt TLO(DAG, DCI.isBeforeLegalize(),
13620 DCI.isBeforeLegalizeOps());
13621 if (TLO.ShrinkDemandedConstant(Cond, DemandedMask) ||
13622 TLI.SimplifyDemandedBits(Cond, DemandedMask, KnownZero, KnownOne, TLO))
13623 DCI.CommitTargetLoweringOpt(TLO);
13629 /// Optimize X86ISD::CMOV [LHS, RHS, CONDCODE (e.g. X86::COND_NE), CONDVAL]
13630 static SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG,
13631 TargetLowering::DAGCombinerInfo &DCI) {
13632 DebugLoc DL = N->getDebugLoc();
13634 // If the flag operand isn't dead, don't touch this CMOV.
13635 if (N->getNumValues() == 2 && !SDValue(N, 1).use_empty())
13638 SDValue FalseOp = N->getOperand(0);
13639 SDValue TrueOp = N->getOperand(1);
13640 X86::CondCode CC = (X86::CondCode)N->getConstantOperandVal(2);
13641 SDValue Cond = N->getOperand(3);
13642 if (CC == X86::COND_E || CC == X86::COND_NE) {
13643 switch (Cond.getOpcode()) {
13647 // If operand of BSR / BSF are proven never zero, then ZF cannot be set.
13648 if (DAG.isKnownNeverZero(Cond.getOperand(0)))
13649 return (CC == X86::COND_E) ? FalseOp : TrueOp;
13653 // If this is a select between two integer constants, try to do some
13654 // optimizations. Note that the operands are ordered the opposite of SELECT
13656 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(TrueOp)) {
13657 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(FalseOp)) {
13658 // Canonicalize the TrueC/FalseC values so that TrueC (the true value) is
13659 // larger than FalseC (the false value).
13660 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue())) {
13661 CC = X86::GetOppositeBranchCondition(CC);
13662 std::swap(TrueC, FalseC);
13665 // Optimize C ? 8 : 0 -> zext(setcc(C)) << 3. Likewise for any pow2/0.
13666 // This is efficient for any integer data type (including i8/i16) and
13668 if (FalseC->getAPIntValue() == 0 && TrueC->getAPIntValue().isPowerOf2()) {
13669 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
13670 DAG.getConstant(CC, MVT::i8), Cond);
13672 // Zero extend the condition if needed.
13673 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, TrueC->getValueType(0), Cond);
13675 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
13676 Cond = DAG.getNode(ISD::SHL, DL, Cond.getValueType(), Cond,
13677 DAG.getConstant(ShAmt, MVT::i8));
13678 if (N->getNumValues() == 2) // Dead flag value?
13679 return DCI.CombineTo(N, Cond, SDValue());
13683 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst. This is efficient
13684 // for any integer data type, including i8/i16.
13685 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
13686 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
13687 DAG.getConstant(CC, MVT::i8), Cond);
13689 // Zero extend the condition if needed.
13690 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
13691 FalseC->getValueType(0), Cond);
13692 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
13693 SDValue(FalseC, 0));
13695 if (N->getNumValues() == 2) // Dead flag value?
13696 return DCI.CombineTo(N, Cond, SDValue());
13700 // Optimize cases that will turn into an LEA instruction. This requires
13701 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
13702 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
13703 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
13704 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
13706 bool isFastMultiplier = false;
13708 switch ((unsigned char)Diff) {
13710 case 1: // result = add base, cond
13711 case 2: // result = lea base( , cond*2)
13712 case 3: // result = lea base(cond, cond*2)
13713 case 4: // result = lea base( , cond*4)
13714 case 5: // result = lea base(cond, cond*4)
13715 case 8: // result = lea base( , cond*8)
13716 case 9: // result = lea base(cond, cond*8)
13717 isFastMultiplier = true;
13722 if (isFastMultiplier) {
13723 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
13724 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
13725 DAG.getConstant(CC, MVT::i8), Cond);
13726 // Zero extend the condition if needed.
13727 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
13729 // Scale the condition by the difference.
13731 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
13732 DAG.getConstant(Diff, Cond.getValueType()));
13734 // Add the base if non-zero.
13735 if (FalseC->getAPIntValue() != 0)
13736 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
13737 SDValue(FalseC, 0));
13738 if (N->getNumValues() == 2) // Dead flag value?
13739 return DCI.CombineTo(N, Cond, SDValue());
13749 /// PerformMulCombine - Optimize a single multiply with constant into two
13750 /// in order to implement it with two cheaper instructions, e.g.
13751 /// LEA + SHL, LEA + LEA.
13752 static SDValue PerformMulCombine(SDNode *N, SelectionDAG &DAG,
13753 TargetLowering::DAGCombinerInfo &DCI) {
13754 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer())
13757 EVT VT = N->getValueType(0);
13758 if (VT != MVT::i64)
13761 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
13764 uint64_t MulAmt = C->getZExtValue();
13765 if (isPowerOf2_64(MulAmt) || MulAmt == 3 || MulAmt == 5 || MulAmt == 9)
13768 uint64_t MulAmt1 = 0;
13769 uint64_t MulAmt2 = 0;
13770 if ((MulAmt % 9) == 0) {
13772 MulAmt2 = MulAmt / 9;
13773 } else if ((MulAmt % 5) == 0) {
13775 MulAmt2 = MulAmt / 5;
13776 } else if ((MulAmt % 3) == 0) {
13778 MulAmt2 = MulAmt / 3;
13781 (isPowerOf2_64(MulAmt2) || MulAmt2 == 3 || MulAmt2 == 5 || MulAmt2 == 9)){
13782 DebugLoc DL = N->getDebugLoc();
13784 if (isPowerOf2_64(MulAmt2) &&
13785 !(N->hasOneUse() && N->use_begin()->getOpcode() == ISD::ADD))
13786 // If second multiplifer is pow2, issue it first. We want the multiply by
13787 // 3, 5, or 9 to be folded into the addressing mode unless the lone use
13789 std::swap(MulAmt1, MulAmt2);
13792 if (isPowerOf2_64(MulAmt1))
13793 NewMul = DAG.getNode(ISD::SHL, DL, VT, N->getOperand(0),
13794 DAG.getConstant(Log2_64(MulAmt1), MVT::i8));
13796 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, N->getOperand(0),
13797 DAG.getConstant(MulAmt1, VT));
13799 if (isPowerOf2_64(MulAmt2))
13800 NewMul = DAG.getNode(ISD::SHL, DL, VT, NewMul,
13801 DAG.getConstant(Log2_64(MulAmt2), MVT::i8));
13803 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, NewMul,
13804 DAG.getConstant(MulAmt2, VT));
13806 // Do not add new nodes to DAG combiner worklist.
13807 DCI.CombineTo(N, NewMul, false);
13812 static SDValue PerformSHLCombine(SDNode *N, SelectionDAG &DAG) {
13813 SDValue N0 = N->getOperand(0);
13814 SDValue N1 = N->getOperand(1);
13815 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
13816 EVT VT = N0.getValueType();
13818 // fold (shl (and (setcc_c), c1), c2) -> (and setcc_c, (c1 << c2))
13819 // since the result of setcc_c is all zero's or all ones.
13820 if (VT.isInteger() && !VT.isVector() &&
13821 N1C && N0.getOpcode() == ISD::AND &&
13822 N0.getOperand(1).getOpcode() == ISD::Constant) {
13823 SDValue N00 = N0.getOperand(0);
13824 if (N00.getOpcode() == X86ISD::SETCC_CARRY ||
13825 ((N00.getOpcode() == ISD::ANY_EXTEND ||
13826 N00.getOpcode() == ISD::ZERO_EXTEND) &&
13827 N00.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY)) {
13828 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
13829 APInt ShAmt = N1C->getAPIntValue();
13830 Mask = Mask.shl(ShAmt);
13832 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT,
13833 N00, DAG.getConstant(Mask, VT));
13838 // Hardware support for vector shifts is sparse which makes us scalarize the
13839 // vector operations in many cases. Also, on sandybridge ADD is faster than
13841 // (shl V, 1) -> add V,V
13842 if (isSplatVector(N1.getNode())) {
13843 assert(N0.getValueType().isVector() && "Invalid vector shift type");
13844 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1->getOperand(0));
13845 // We shift all of the values by one. In many cases we do not have
13846 // hardware support for this operation. This is better expressed as an ADD
13848 if (N1C && (1 == N1C->getZExtValue())) {
13849 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N0, N0);
13856 /// PerformShiftCombine - Transforms vector shift nodes to use vector shifts
13858 static SDValue PerformShiftCombine(SDNode* N, SelectionDAG &DAG,
13859 TargetLowering::DAGCombinerInfo &DCI,
13860 const X86Subtarget *Subtarget) {
13861 EVT VT = N->getValueType(0);
13862 if (N->getOpcode() == ISD::SHL) {
13863 SDValue V = PerformSHLCombine(N, DAG);
13864 if (V.getNode()) return V;
13867 // On X86 with SSE2 support, we can transform this to a vector shift if
13868 // all elements are shifted by the same amount. We can't do this in legalize
13869 // because the a constant vector is typically transformed to a constant pool
13870 // so we have no knowledge of the shift amount.
13871 if (!Subtarget->hasSSE2())
13874 if (VT != MVT::v2i64 && VT != MVT::v4i32 && VT != MVT::v8i16 &&
13875 (!Subtarget->hasAVX2() ||
13876 (VT != MVT::v4i64 && VT != MVT::v8i32 && VT != MVT::v16i16)))
13879 SDValue ShAmtOp = N->getOperand(1);
13880 EVT EltVT = VT.getVectorElementType();
13881 DebugLoc DL = N->getDebugLoc();
13882 SDValue BaseShAmt = SDValue();
13883 if (ShAmtOp.getOpcode() == ISD::BUILD_VECTOR) {
13884 unsigned NumElts = VT.getVectorNumElements();
13886 for (; i != NumElts; ++i) {
13887 SDValue Arg = ShAmtOp.getOperand(i);
13888 if (Arg.getOpcode() == ISD::UNDEF) continue;
13892 // Handle the case where the build_vector is all undef
13893 // FIXME: Should DAG allow this?
13897 for (; i != NumElts; ++i) {
13898 SDValue Arg = ShAmtOp.getOperand(i);
13899 if (Arg.getOpcode() == ISD::UNDEF) continue;
13900 if (Arg != BaseShAmt) {
13904 } else if (ShAmtOp.getOpcode() == ISD::VECTOR_SHUFFLE &&
13905 cast<ShuffleVectorSDNode>(ShAmtOp)->isSplat()) {
13906 SDValue InVec = ShAmtOp.getOperand(0);
13907 if (InVec.getOpcode() == ISD::BUILD_VECTOR) {
13908 unsigned NumElts = InVec.getValueType().getVectorNumElements();
13910 for (; i != NumElts; ++i) {
13911 SDValue Arg = InVec.getOperand(i);
13912 if (Arg.getOpcode() == ISD::UNDEF) continue;
13916 } else if (InVec.getOpcode() == ISD::INSERT_VECTOR_ELT) {
13917 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(InVec.getOperand(2))) {
13918 unsigned SplatIdx= cast<ShuffleVectorSDNode>(ShAmtOp)->getSplatIndex();
13919 if (C->getZExtValue() == SplatIdx)
13920 BaseShAmt = InVec.getOperand(1);
13923 if (BaseShAmt.getNode() == 0) {
13924 // Don't create instructions with illegal types after legalize
13926 if (!DAG.getTargetLoweringInfo().isTypeLegal(EltVT) &&
13927 !DCI.isBeforeLegalize())
13930 BaseShAmt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, EltVT, ShAmtOp,
13931 DAG.getIntPtrConstant(0));
13936 // The shift amount is an i32.
13937 if (EltVT.bitsGT(MVT::i32))
13938 BaseShAmt = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, BaseShAmt);
13939 else if (EltVT.bitsLT(MVT::i32))
13940 BaseShAmt = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i32, BaseShAmt);
13942 // The shift amount is identical so we can do a vector shift.
13943 SDValue ValOp = N->getOperand(0);
13944 switch (N->getOpcode()) {
13946 llvm_unreachable("Unknown shift opcode!");
13948 switch (VT.getSimpleVT().SimpleTy) {
13949 default: return SDValue();
13956 return getTargetVShiftNode(X86ISD::VSHLI, DL, VT, ValOp, BaseShAmt, DAG);
13959 switch (VT.getSimpleVT().SimpleTy) {
13960 default: return SDValue();
13965 return getTargetVShiftNode(X86ISD::VSRAI, DL, VT, ValOp, BaseShAmt, DAG);
13968 switch (VT.getSimpleVT().SimpleTy) {
13969 default: return SDValue();
13976 return getTargetVShiftNode(X86ISD::VSRLI, DL, VT, ValOp, BaseShAmt, DAG);
13982 // CMPEQCombine - Recognize the distinctive (AND (setcc ...) (setcc ..))
13983 // where both setccs reference the same FP CMP, and rewrite for CMPEQSS
13984 // and friends. Likewise for OR -> CMPNEQSS.
13985 static SDValue CMPEQCombine(SDNode *N, SelectionDAG &DAG,
13986 TargetLowering::DAGCombinerInfo &DCI,
13987 const X86Subtarget *Subtarget) {
13990 // SSE1 supports CMP{eq|ne}SS, and SSE2 added CMP{eq|ne}SD, but
13991 // we're requiring SSE2 for both.
13992 if (Subtarget->hasSSE2() && isAndOrOfSetCCs(SDValue(N, 0U), opcode)) {
13993 SDValue N0 = N->getOperand(0);
13994 SDValue N1 = N->getOperand(1);
13995 SDValue CMP0 = N0->getOperand(1);
13996 SDValue CMP1 = N1->getOperand(1);
13997 DebugLoc DL = N->getDebugLoc();
13999 // The SETCCs should both refer to the same CMP.
14000 if (CMP0.getOpcode() != X86ISD::CMP || CMP0 != CMP1)
14003 SDValue CMP00 = CMP0->getOperand(0);
14004 SDValue CMP01 = CMP0->getOperand(1);
14005 EVT VT = CMP00.getValueType();
14007 if (VT == MVT::f32 || VT == MVT::f64) {
14008 bool ExpectingFlags = false;
14009 // Check for any users that want flags:
14010 for (SDNode::use_iterator UI = N->use_begin(),
14012 !ExpectingFlags && UI != UE; ++UI)
14013 switch (UI->getOpcode()) {
14018 ExpectingFlags = true;
14020 case ISD::CopyToReg:
14021 case ISD::SIGN_EXTEND:
14022 case ISD::ZERO_EXTEND:
14023 case ISD::ANY_EXTEND:
14027 if (!ExpectingFlags) {
14028 enum X86::CondCode cc0 = (enum X86::CondCode)N0.getConstantOperandVal(0);
14029 enum X86::CondCode cc1 = (enum X86::CondCode)N1.getConstantOperandVal(0);
14031 if (cc1 == X86::COND_E || cc1 == X86::COND_NE) {
14032 X86::CondCode tmp = cc0;
14037 if ((cc0 == X86::COND_E && cc1 == X86::COND_NP) ||
14038 (cc0 == X86::COND_NE && cc1 == X86::COND_P)) {
14039 bool is64BitFP = (CMP00.getValueType() == MVT::f64);
14040 X86ISD::NodeType NTOperator = is64BitFP ?
14041 X86ISD::FSETCCsd : X86ISD::FSETCCss;
14042 // FIXME: need symbolic constants for these magic numbers.
14043 // See X86ATTInstPrinter.cpp:printSSECC().
14044 unsigned x86cc = (cc0 == X86::COND_E) ? 0 : 4;
14045 SDValue OnesOrZeroesF = DAG.getNode(NTOperator, DL, MVT::f32, CMP00, CMP01,
14046 DAG.getConstant(x86cc, MVT::i8));
14047 SDValue OnesOrZeroesI = DAG.getNode(ISD::BITCAST, DL, MVT::i32,
14049 SDValue ANDed = DAG.getNode(ISD::AND, DL, MVT::i32, OnesOrZeroesI,
14050 DAG.getConstant(1, MVT::i32));
14051 SDValue OneBitOfTruth = DAG.getNode(ISD::TRUNCATE, DL, MVT::i8, ANDed);
14052 return OneBitOfTruth;
14060 /// CanFoldXORWithAllOnes - Test whether the XOR operand is a AllOnes vector
14061 /// so it can be folded inside ANDNP.
14062 static bool CanFoldXORWithAllOnes(const SDNode *N) {
14063 EVT VT = N->getValueType(0);
14065 // Match direct AllOnes for 128 and 256-bit vectors
14066 if (ISD::isBuildVectorAllOnes(N))
14069 // Look through a bit convert.
14070 if (N->getOpcode() == ISD::BITCAST)
14071 N = N->getOperand(0).getNode();
14073 // Sometimes the operand may come from a insert_subvector building a 256-bit
14075 if (VT.getSizeInBits() == 256 &&
14076 N->getOpcode() == ISD::INSERT_SUBVECTOR) {
14077 SDValue V1 = N->getOperand(0);
14078 SDValue V2 = N->getOperand(1);
14080 if (V1.getOpcode() == ISD::INSERT_SUBVECTOR &&
14081 V1.getOperand(0).getOpcode() == ISD::UNDEF &&
14082 ISD::isBuildVectorAllOnes(V1.getOperand(1).getNode()) &&
14083 ISD::isBuildVectorAllOnes(V2.getNode()))
14090 static SDValue PerformAndCombine(SDNode *N, SelectionDAG &DAG,
14091 TargetLowering::DAGCombinerInfo &DCI,
14092 const X86Subtarget *Subtarget) {
14093 if (DCI.isBeforeLegalizeOps())
14096 SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget);
14100 EVT VT = N->getValueType(0);
14102 // Create ANDN, BLSI, and BLSR instructions
14103 // BLSI is X & (-X)
14104 // BLSR is X & (X-1)
14105 if (Subtarget->hasBMI() && (VT == MVT::i32 || VT == MVT::i64)) {
14106 SDValue N0 = N->getOperand(0);
14107 SDValue N1 = N->getOperand(1);
14108 DebugLoc DL = N->getDebugLoc();
14110 // Check LHS for not
14111 if (N0.getOpcode() == ISD::XOR && isAllOnes(N0.getOperand(1)))
14112 return DAG.getNode(X86ISD::ANDN, DL, VT, N0.getOperand(0), N1);
14113 // Check RHS for not
14114 if (N1.getOpcode() == ISD::XOR && isAllOnes(N1.getOperand(1)))
14115 return DAG.getNode(X86ISD::ANDN, DL, VT, N1.getOperand(0), N0);
14117 // Check LHS for neg
14118 if (N0.getOpcode() == ISD::SUB && N0.getOperand(1) == N1 &&
14119 isZero(N0.getOperand(0)))
14120 return DAG.getNode(X86ISD::BLSI, DL, VT, N1);
14122 // Check RHS for neg
14123 if (N1.getOpcode() == ISD::SUB && N1.getOperand(1) == N0 &&
14124 isZero(N1.getOperand(0)))
14125 return DAG.getNode(X86ISD::BLSI, DL, VT, N0);
14127 // Check LHS for X-1
14128 if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1 &&
14129 isAllOnes(N0.getOperand(1)))
14130 return DAG.getNode(X86ISD::BLSR, DL, VT, N1);
14132 // Check RHS for X-1
14133 if (N1.getOpcode() == ISD::ADD && N1.getOperand(0) == N0 &&
14134 isAllOnes(N1.getOperand(1)))
14135 return DAG.getNode(X86ISD::BLSR, DL, VT, N0);
14140 // Want to form ANDNP nodes:
14141 // 1) In the hopes of then easily combining them with OR and AND nodes
14142 // to form PBLEND/PSIGN.
14143 // 2) To match ANDN packed intrinsics
14144 if (VT != MVT::v2i64 && VT != MVT::v4i64)
14147 SDValue N0 = N->getOperand(0);
14148 SDValue N1 = N->getOperand(1);
14149 DebugLoc DL = N->getDebugLoc();
14151 // Check LHS for vnot
14152 if (N0.getOpcode() == ISD::XOR &&
14153 //ISD::isBuildVectorAllOnes(N0.getOperand(1).getNode()))
14154 CanFoldXORWithAllOnes(N0.getOperand(1).getNode()))
14155 return DAG.getNode(X86ISD::ANDNP, DL, VT, N0.getOperand(0), N1);
14157 // Check RHS for vnot
14158 if (N1.getOpcode() == ISD::XOR &&
14159 //ISD::isBuildVectorAllOnes(N1.getOperand(1).getNode()))
14160 CanFoldXORWithAllOnes(N1.getOperand(1).getNode()))
14161 return DAG.getNode(X86ISD::ANDNP, DL, VT, N1.getOperand(0), N0);
14166 static SDValue PerformOrCombine(SDNode *N, SelectionDAG &DAG,
14167 TargetLowering::DAGCombinerInfo &DCI,
14168 const X86Subtarget *Subtarget) {
14169 if (DCI.isBeforeLegalizeOps())
14172 SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget);
14176 EVT VT = N->getValueType(0);
14178 SDValue N0 = N->getOperand(0);
14179 SDValue N1 = N->getOperand(1);
14181 // look for psign/blend
14182 if (VT == MVT::v2i64 || VT == MVT::v4i64) {
14183 if (!Subtarget->hasSSSE3() ||
14184 (VT == MVT::v4i64 && !Subtarget->hasAVX2()))
14187 // Canonicalize pandn to RHS
14188 if (N0.getOpcode() == X86ISD::ANDNP)
14190 // or (and (m, y), (pandn m, x))
14191 if (N0.getOpcode() == ISD::AND && N1.getOpcode() == X86ISD::ANDNP) {
14192 SDValue Mask = N1.getOperand(0);
14193 SDValue X = N1.getOperand(1);
14195 if (N0.getOperand(0) == Mask)
14196 Y = N0.getOperand(1);
14197 if (N0.getOperand(1) == Mask)
14198 Y = N0.getOperand(0);
14200 // Check to see if the mask appeared in both the AND and ANDNP and
14204 // Validate that X, Y, and Mask are BIT_CONVERTS, and see through them.
14205 // Look through mask bitcast.
14206 if (Mask.getOpcode() == ISD::BITCAST)
14207 Mask = Mask.getOperand(0);
14208 if (X.getOpcode() == ISD::BITCAST)
14209 X = X.getOperand(0);
14210 if (Y.getOpcode() == ISD::BITCAST)
14211 Y = Y.getOperand(0);
14213 EVT MaskVT = Mask.getValueType();
14215 // Validate that the Mask operand is a vector sra node.
14216 // FIXME: what to do for bytes, since there is a psignb/pblendvb, but
14217 // there is no psrai.b
14218 if (Mask.getOpcode() != X86ISD::VSRAI)
14221 // Check that the SRA is all signbits.
14222 SDValue SraC = Mask.getOperand(1);
14223 unsigned SraAmt = cast<ConstantSDNode>(SraC)->getZExtValue();
14224 unsigned EltBits = MaskVT.getVectorElementType().getSizeInBits();
14225 if ((SraAmt + 1) != EltBits)
14228 DebugLoc DL = N->getDebugLoc();
14230 // Now we know we at least have a plendvb with the mask val. See if
14231 // we can form a psignb/w/d.
14232 // psign = x.type == y.type == mask.type && y = sub(0, x);
14233 if (Y.getOpcode() == ISD::SUB && Y.getOperand(1) == X &&
14234 ISD::isBuildVectorAllZeros(Y.getOperand(0).getNode()) &&
14235 X.getValueType() == MaskVT && Y.getValueType() == MaskVT) {
14236 assert((EltBits == 8 || EltBits == 16 || EltBits == 32) &&
14237 "Unsupported VT for PSIGN");
14238 Mask = DAG.getNode(X86ISD::PSIGN, DL, MaskVT, X, Mask.getOperand(0));
14239 return DAG.getNode(ISD::BITCAST, DL, VT, Mask);
14241 // PBLENDVB only available on SSE 4.1
14242 if (!Subtarget->hasSSE41())
14245 EVT BlendVT = (VT == MVT::v4i64) ? MVT::v32i8 : MVT::v16i8;
14247 X = DAG.getNode(ISD::BITCAST, DL, BlendVT, X);
14248 Y = DAG.getNode(ISD::BITCAST, DL, BlendVT, Y);
14249 Mask = DAG.getNode(ISD::BITCAST, DL, BlendVT, Mask);
14250 Mask = DAG.getNode(ISD::VSELECT, DL, BlendVT, Mask, Y, X);
14251 return DAG.getNode(ISD::BITCAST, DL, VT, Mask);
14255 if (VT != MVT::i16 && VT != MVT::i32 && VT != MVT::i64)
14258 // fold (or (x << c) | (y >> (64 - c))) ==> (shld64 x, y, c)
14259 if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL)
14261 if (N0.getOpcode() != ISD::SHL || N1.getOpcode() != ISD::SRL)
14263 if (!N0.hasOneUse() || !N1.hasOneUse())
14266 SDValue ShAmt0 = N0.getOperand(1);
14267 if (ShAmt0.getValueType() != MVT::i8)
14269 SDValue ShAmt1 = N1.getOperand(1);
14270 if (ShAmt1.getValueType() != MVT::i8)
14272 if (ShAmt0.getOpcode() == ISD::TRUNCATE)
14273 ShAmt0 = ShAmt0.getOperand(0);
14274 if (ShAmt1.getOpcode() == ISD::TRUNCATE)
14275 ShAmt1 = ShAmt1.getOperand(0);
14277 DebugLoc DL = N->getDebugLoc();
14278 unsigned Opc = X86ISD::SHLD;
14279 SDValue Op0 = N0.getOperand(0);
14280 SDValue Op1 = N1.getOperand(0);
14281 if (ShAmt0.getOpcode() == ISD::SUB) {
14282 Opc = X86ISD::SHRD;
14283 std::swap(Op0, Op1);
14284 std::swap(ShAmt0, ShAmt1);
14287 unsigned Bits = VT.getSizeInBits();
14288 if (ShAmt1.getOpcode() == ISD::SUB) {
14289 SDValue Sum = ShAmt1.getOperand(0);
14290 if (ConstantSDNode *SumC = dyn_cast<ConstantSDNode>(Sum)) {
14291 SDValue ShAmt1Op1 = ShAmt1.getOperand(1);
14292 if (ShAmt1Op1.getNode()->getOpcode() == ISD::TRUNCATE)
14293 ShAmt1Op1 = ShAmt1Op1.getOperand(0);
14294 if (SumC->getSExtValue() == Bits && ShAmt1Op1 == ShAmt0)
14295 return DAG.getNode(Opc, DL, VT,
14297 DAG.getNode(ISD::TRUNCATE, DL,
14300 } else if (ConstantSDNode *ShAmt1C = dyn_cast<ConstantSDNode>(ShAmt1)) {
14301 ConstantSDNode *ShAmt0C = dyn_cast<ConstantSDNode>(ShAmt0);
14303 ShAmt0C->getSExtValue() + ShAmt1C->getSExtValue() == Bits)
14304 return DAG.getNode(Opc, DL, VT,
14305 N0.getOperand(0), N1.getOperand(0),
14306 DAG.getNode(ISD::TRUNCATE, DL,
14313 // PerformXorCombine - Attempts to turn XOR nodes into BLSMSK nodes
14314 static SDValue PerformXorCombine(SDNode *N, SelectionDAG &DAG,
14315 TargetLowering::DAGCombinerInfo &DCI,
14316 const X86Subtarget *Subtarget) {
14317 if (DCI.isBeforeLegalizeOps())
14320 EVT VT = N->getValueType(0);
14322 if (VT != MVT::i32 && VT != MVT::i64)
14325 assert(Subtarget->hasBMI() && "Creating BLSMSK requires BMI instructions");
14327 // Create BLSMSK instructions by finding X ^ (X-1)
14328 SDValue N0 = N->getOperand(0);
14329 SDValue N1 = N->getOperand(1);
14330 DebugLoc DL = N->getDebugLoc();
14332 if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1 &&
14333 isAllOnes(N0.getOperand(1)))
14334 return DAG.getNode(X86ISD::BLSMSK, DL, VT, N1);
14336 if (N1.getOpcode() == ISD::ADD && N1.getOperand(0) == N0 &&
14337 isAllOnes(N1.getOperand(1)))
14338 return DAG.getNode(X86ISD::BLSMSK, DL, VT, N0);
14343 /// PerformLOADCombine - Do target-specific dag combines on LOAD nodes.
14344 static SDValue PerformLOADCombine(SDNode *N, SelectionDAG &DAG,
14345 const X86Subtarget *Subtarget) {
14346 LoadSDNode *Ld = cast<LoadSDNode>(N);
14347 EVT RegVT = Ld->getValueType(0);
14348 EVT MemVT = Ld->getMemoryVT();
14349 DebugLoc dl = Ld->getDebugLoc();
14350 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
14352 ISD::LoadExtType Ext = Ld->getExtensionType();
14354 // If this is a vector EXT Load then attempt to optimize it using a
14355 // shuffle. We need SSE4 for the shuffles.
14356 // TODO: It is possible to support ZExt by zeroing the undef values
14357 // during the shuffle phase or after the shuffle.
14358 if (RegVT.isVector() && RegVT.isInteger() &&
14359 Ext == ISD::EXTLOAD && Subtarget->hasSSE41()) {
14360 assert(MemVT != RegVT && "Cannot extend to the same type");
14361 assert(MemVT.isVector() && "Must load a vector from memory");
14363 unsigned NumElems = RegVT.getVectorNumElements();
14364 unsigned RegSz = RegVT.getSizeInBits();
14365 unsigned MemSz = MemVT.getSizeInBits();
14366 assert(RegSz > MemSz && "Register size must be greater than the mem size");
14367 // All sizes must be a power of two
14368 if (!isPowerOf2_32(RegSz * MemSz * NumElems)) return SDValue();
14370 // Attempt to load the original value using a single load op.
14371 // Find a scalar type which is equal to the loaded word size.
14372 MVT SclrLoadTy = MVT::i8;
14373 for (unsigned tp = MVT::FIRST_INTEGER_VALUETYPE;
14374 tp < MVT::LAST_INTEGER_VALUETYPE; ++tp) {
14375 MVT Tp = (MVT::SimpleValueType)tp;
14376 if (TLI.isTypeLegal(Tp) && Tp.getSizeInBits() == MemSz) {
14382 // Proceed if a load word is found.
14383 if (SclrLoadTy.getSizeInBits() != MemSz) return SDValue();
14385 EVT LoadUnitVecVT = EVT::getVectorVT(*DAG.getContext(), SclrLoadTy,
14386 RegSz/SclrLoadTy.getSizeInBits());
14388 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(), MemVT.getScalarType(),
14389 RegSz/MemVT.getScalarType().getSizeInBits());
14390 // Can't shuffle using an illegal type.
14391 if (!TLI.isTypeLegal(WideVecVT)) return SDValue();
14393 // Perform a single load.
14394 SDValue ScalarLoad = DAG.getLoad(SclrLoadTy, dl, Ld->getChain(),
14396 Ld->getPointerInfo(), Ld->isVolatile(),
14397 Ld->isNonTemporal(), Ld->isInvariant(),
14398 Ld->getAlignment());
14400 // Insert the word loaded into a vector.
14401 SDValue ScalarInVector = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
14402 LoadUnitVecVT, ScalarLoad);
14404 // Bitcast the loaded value to a vector of the original element type, in
14405 // the size of the target vector type.
14406 SDValue SlicedVec = DAG.getNode(ISD::BITCAST, dl, WideVecVT,
14408 unsigned SizeRatio = RegSz/MemSz;
14410 // Redistribute the loaded elements into the different locations.
14411 SmallVector<int, 8> ShuffleVec(NumElems * SizeRatio, -1);
14412 for (unsigned i = 0; i < NumElems; i++) ShuffleVec[i*SizeRatio] = i;
14414 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, SlicedVec,
14415 DAG.getUNDEF(SlicedVec.getValueType()),
14416 ShuffleVec.data());
14418 // Bitcast to the requested type.
14419 Shuff = DAG.getNode(ISD::BITCAST, dl, RegVT, Shuff);
14420 // Replace the original load with the new sequence
14421 // and return the new chain.
14422 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Shuff);
14423 return SDValue(ScalarLoad.getNode(), 1);
14429 /// PerformSTORECombine - Do target-specific dag combines on STORE nodes.
14430 static SDValue PerformSTORECombine(SDNode *N, SelectionDAG &DAG,
14431 const X86Subtarget *Subtarget) {
14432 StoreSDNode *St = cast<StoreSDNode>(N);
14433 EVT VT = St->getValue().getValueType();
14434 EVT StVT = St->getMemoryVT();
14435 DebugLoc dl = St->getDebugLoc();
14436 SDValue StoredVal = St->getOperand(1);
14437 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
14439 // If we are saving a concatenation of two XMM registers, perform two stores.
14440 // This is better in Sandy Bridge cause one 256-bit mem op is done via two
14441 // 128-bit ones. If in the future the cost becomes only one memory access the
14442 // first version would be better.
14443 if (VT.getSizeInBits() == 256 &&
14444 StoredVal.getNode()->getOpcode() == ISD::CONCAT_VECTORS &&
14445 StoredVal.getNumOperands() == 2) {
14447 SDValue Value0 = StoredVal.getOperand(0);
14448 SDValue Value1 = StoredVal.getOperand(1);
14450 SDValue Stride = DAG.getConstant(16, TLI.getPointerTy());
14451 SDValue Ptr0 = St->getBasePtr();
14452 SDValue Ptr1 = DAG.getNode(ISD::ADD, dl, Ptr0.getValueType(), Ptr0, Stride);
14454 SDValue Ch0 = DAG.getStore(St->getChain(), dl, Value0, Ptr0,
14455 St->getPointerInfo(), St->isVolatile(),
14456 St->isNonTemporal(), St->getAlignment());
14457 SDValue Ch1 = DAG.getStore(St->getChain(), dl, Value1, Ptr1,
14458 St->getPointerInfo(), St->isVolatile(),
14459 St->isNonTemporal(), St->getAlignment());
14460 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Ch0, Ch1);
14463 // Optimize trunc store (of multiple scalars) to shuffle and store.
14464 // First, pack all of the elements in one place. Next, store to memory
14465 // in fewer chunks.
14466 if (St->isTruncatingStore() && VT.isVector()) {
14467 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
14468 unsigned NumElems = VT.getVectorNumElements();
14469 assert(StVT != VT && "Cannot truncate to the same type");
14470 unsigned FromSz = VT.getVectorElementType().getSizeInBits();
14471 unsigned ToSz = StVT.getVectorElementType().getSizeInBits();
14473 // From, To sizes and ElemCount must be pow of two
14474 if (!isPowerOf2_32(NumElems * FromSz * ToSz)) return SDValue();
14475 // We are going to use the original vector elt for storing.
14476 // Accumulated smaller vector elements must be a multiple of the store size.
14477 if (0 != (NumElems * FromSz) % ToSz) return SDValue();
14479 unsigned SizeRatio = FromSz / ToSz;
14481 assert(SizeRatio * NumElems * ToSz == VT.getSizeInBits());
14483 // Create a type on which we perform the shuffle
14484 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(),
14485 StVT.getScalarType(), NumElems*SizeRatio);
14487 assert(WideVecVT.getSizeInBits() == VT.getSizeInBits());
14489 SDValue WideVec = DAG.getNode(ISD::BITCAST, dl, WideVecVT, St->getValue());
14490 SmallVector<int, 8> ShuffleVec(NumElems * SizeRatio, -1);
14491 for (unsigned i = 0; i < NumElems; i++ ) ShuffleVec[i] = i * SizeRatio;
14493 // Can't shuffle using an illegal type
14494 if (!TLI.isTypeLegal(WideVecVT)) return SDValue();
14496 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, WideVec,
14497 DAG.getUNDEF(WideVec.getValueType()),
14498 ShuffleVec.data());
14499 // At this point all of the data is stored at the bottom of the
14500 // register. We now need to save it to mem.
14502 // Find the largest store unit
14503 MVT StoreType = MVT::i8;
14504 for (unsigned tp = MVT::FIRST_INTEGER_VALUETYPE;
14505 tp < MVT::LAST_INTEGER_VALUETYPE; ++tp) {
14506 MVT Tp = (MVT::SimpleValueType)tp;
14507 if (TLI.isTypeLegal(Tp) && StoreType.getSizeInBits() < NumElems * ToSz)
14511 // Bitcast the original vector into a vector of store-size units
14512 EVT StoreVecVT = EVT::getVectorVT(*DAG.getContext(),
14513 StoreType, VT.getSizeInBits()/EVT(StoreType).getSizeInBits());
14514 assert(StoreVecVT.getSizeInBits() == VT.getSizeInBits());
14515 SDValue ShuffWide = DAG.getNode(ISD::BITCAST, dl, StoreVecVT, Shuff);
14516 SmallVector<SDValue, 8> Chains;
14517 SDValue Increment = DAG.getConstant(StoreType.getSizeInBits()/8,
14518 TLI.getPointerTy());
14519 SDValue Ptr = St->getBasePtr();
14521 // Perform one or more big stores into memory.
14522 for (unsigned i = 0; i < (ToSz*NumElems)/StoreType.getSizeInBits() ; i++) {
14523 SDValue SubVec = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
14524 StoreType, ShuffWide,
14525 DAG.getIntPtrConstant(i));
14526 SDValue Ch = DAG.getStore(St->getChain(), dl, SubVec, Ptr,
14527 St->getPointerInfo(), St->isVolatile(),
14528 St->isNonTemporal(), St->getAlignment());
14529 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
14530 Chains.push_back(Ch);
14533 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Chains[0],
14538 // Turn load->store of MMX types into GPR load/stores. This avoids clobbering
14539 // the FP state in cases where an emms may be missing.
14540 // A preferable solution to the general problem is to figure out the right
14541 // places to insert EMMS. This qualifies as a quick hack.
14543 // Similarly, turn load->store of i64 into double load/stores in 32-bit mode.
14544 if (VT.getSizeInBits() != 64)
14547 const Function *F = DAG.getMachineFunction().getFunction();
14548 bool NoImplicitFloatOps = F->hasFnAttr(Attribute::NoImplicitFloat);
14549 bool F64IsLegal = !DAG.getTarget().Options.UseSoftFloat && !NoImplicitFloatOps
14550 && Subtarget->hasSSE2();
14551 if ((VT.isVector() ||
14552 (VT == MVT::i64 && F64IsLegal && !Subtarget->is64Bit())) &&
14553 isa<LoadSDNode>(St->getValue()) &&
14554 !cast<LoadSDNode>(St->getValue())->isVolatile() &&
14555 St->getChain().hasOneUse() && !St->isVolatile()) {
14556 SDNode* LdVal = St->getValue().getNode();
14557 LoadSDNode *Ld = 0;
14558 int TokenFactorIndex = -1;
14559 SmallVector<SDValue, 8> Ops;
14560 SDNode* ChainVal = St->getChain().getNode();
14561 // Must be a store of a load. We currently handle two cases: the load
14562 // is a direct child, and it's under an intervening TokenFactor. It is
14563 // possible to dig deeper under nested TokenFactors.
14564 if (ChainVal == LdVal)
14565 Ld = cast<LoadSDNode>(St->getChain());
14566 else if (St->getValue().hasOneUse() &&
14567 ChainVal->getOpcode() == ISD::TokenFactor) {
14568 for (unsigned i = 0, e = ChainVal->getNumOperands(); i != e; ++i) {
14569 if (ChainVal->getOperand(i).getNode() == LdVal) {
14570 TokenFactorIndex = i;
14571 Ld = cast<LoadSDNode>(St->getValue());
14573 Ops.push_back(ChainVal->getOperand(i));
14577 if (!Ld || !ISD::isNormalLoad(Ld))
14580 // If this is not the MMX case, i.e. we are just turning i64 load/store
14581 // into f64 load/store, avoid the transformation if there are multiple
14582 // uses of the loaded value.
14583 if (!VT.isVector() && !Ld->hasNUsesOfValue(1, 0))
14586 DebugLoc LdDL = Ld->getDebugLoc();
14587 DebugLoc StDL = N->getDebugLoc();
14588 // If we are a 64-bit capable x86, lower to a single movq load/store pair.
14589 // Otherwise, if it's legal to use f64 SSE instructions, use f64 load/store
14591 if (Subtarget->is64Bit() || F64IsLegal) {
14592 EVT LdVT = Subtarget->is64Bit() ? MVT::i64 : MVT::f64;
14593 SDValue NewLd = DAG.getLoad(LdVT, LdDL, Ld->getChain(), Ld->getBasePtr(),
14594 Ld->getPointerInfo(), Ld->isVolatile(),
14595 Ld->isNonTemporal(), Ld->isInvariant(),
14596 Ld->getAlignment());
14597 SDValue NewChain = NewLd.getValue(1);
14598 if (TokenFactorIndex != -1) {
14599 Ops.push_back(NewChain);
14600 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, &Ops[0],
14603 return DAG.getStore(NewChain, StDL, NewLd, St->getBasePtr(),
14604 St->getPointerInfo(),
14605 St->isVolatile(), St->isNonTemporal(),
14606 St->getAlignment());
14609 // Otherwise, lower to two pairs of 32-bit loads / stores.
14610 SDValue LoAddr = Ld->getBasePtr();
14611 SDValue HiAddr = DAG.getNode(ISD::ADD, LdDL, MVT::i32, LoAddr,
14612 DAG.getConstant(4, MVT::i32));
14614 SDValue LoLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), LoAddr,
14615 Ld->getPointerInfo(),
14616 Ld->isVolatile(), Ld->isNonTemporal(),
14617 Ld->isInvariant(), Ld->getAlignment());
14618 SDValue HiLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), HiAddr,
14619 Ld->getPointerInfo().getWithOffset(4),
14620 Ld->isVolatile(), Ld->isNonTemporal(),
14622 MinAlign(Ld->getAlignment(), 4));
14624 SDValue NewChain = LoLd.getValue(1);
14625 if (TokenFactorIndex != -1) {
14626 Ops.push_back(LoLd);
14627 Ops.push_back(HiLd);
14628 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, &Ops[0],
14632 LoAddr = St->getBasePtr();
14633 HiAddr = DAG.getNode(ISD::ADD, StDL, MVT::i32, LoAddr,
14634 DAG.getConstant(4, MVT::i32));
14636 SDValue LoSt = DAG.getStore(NewChain, StDL, LoLd, LoAddr,
14637 St->getPointerInfo(),
14638 St->isVolatile(), St->isNonTemporal(),
14639 St->getAlignment());
14640 SDValue HiSt = DAG.getStore(NewChain, StDL, HiLd, HiAddr,
14641 St->getPointerInfo().getWithOffset(4),
14643 St->isNonTemporal(),
14644 MinAlign(St->getAlignment(), 4));
14645 return DAG.getNode(ISD::TokenFactor, StDL, MVT::Other, LoSt, HiSt);
14650 /// isHorizontalBinOp - Return 'true' if this vector operation is "horizontal"
14651 /// and return the operands for the horizontal operation in LHS and RHS. A
14652 /// horizontal operation performs the binary operation on successive elements
14653 /// of its first operand, then on successive elements of its second operand,
14654 /// returning the resulting values in a vector. For example, if
14655 /// A = < float a0, float a1, float a2, float a3 >
14657 /// B = < float b0, float b1, float b2, float b3 >
14658 /// then the result of doing a horizontal operation on A and B is
14659 /// A horizontal-op B = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >.
14660 /// In short, LHS and RHS are inspected to see if LHS op RHS is of the form
14661 /// A horizontal-op B, for some already available A and B, and if so then LHS is
14662 /// set to A, RHS to B, and the routine returns 'true'.
14663 /// Note that the binary operation should have the property that if one of the
14664 /// operands is UNDEF then the result is UNDEF.
14665 static bool isHorizontalBinOp(SDValue &LHS, SDValue &RHS, bool IsCommutative) {
14666 // Look for the following pattern: if
14667 // A = < float a0, float a1, float a2, float a3 >
14668 // B = < float b0, float b1, float b2, float b3 >
14670 // LHS = VECTOR_SHUFFLE A, B, <0, 2, 4, 6>
14671 // RHS = VECTOR_SHUFFLE A, B, <1, 3, 5, 7>
14672 // then LHS op RHS = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >
14673 // which is A horizontal-op B.
14675 // At least one of the operands should be a vector shuffle.
14676 if (LHS.getOpcode() != ISD::VECTOR_SHUFFLE &&
14677 RHS.getOpcode() != ISD::VECTOR_SHUFFLE)
14680 EVT VT = LHS.getValueType();
14682 assert((VT.is128BitVector() || VT.is256BitVector()) &&
14683 "Unsupported vector type for horizontal add/sub");
14685 // Handle 128 and 256-bit vector lengths. AVX defines horizontal add/sub to
14686 // operate independently on 128-bit lanes.
14687 unsigned NumElts = VT.getVectorNumElements();
14688 unsigned NumLanes = VT.getSizeInBits()/128;
14689 unsigned NumLaneElts = NumElts / NumLanes;
14690 assert((NumLaneElts % 2 == 0) &&
14691 "Vector type should have an even number of elements in each lane");
14692 unsigned HalfLaneElts = NumLaneElts/2;
14694 // View LHS in the form
14695 // LHS = VECTOR_SHUFFLE A, B, LMask
14696 // If LHS is not a shuffle then pretend it is the shuffle
14697 // LHS = VECTOR_SHUFFLE LHS, undef, <0, 1, ..., N-1>
14698 // NOTE: in what follows a default initialized SDValue represents an UNDEF of
14701 SmallVector<int, 16> LMask(NumElts);
14702 if (LHS.getOpcode() == ISD::VECTOR_SHUFFLE) {
14703 if (LHS.getOperand(0).getOpcode() != ISD::UNDEF)
14704 A = LHS.getOperand(0);
14705 if (LHS.getOperand(1).getOpcode() != ISD::UNDEF)
14706 B = LHS.getOperand(1);
14707 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(LHS.getNode())->getMask();
14708 std::copy(Mask.begin(), Mask.end(), LMask.begin());
14710 if (LHS.getOpcode() != ISD::UNDEF)
14712 for (unsigned i = 0; i != NumElts; ++i)
14716 // Likewise, view RHS in the form
14717 // RHS = VECTOR_SHUFFLE C, D, RMask
14719 SmallVector<int, 16> RMask(NumElts);
14720 if (RHS.getOpcode() == ISD::VECTOR_SHUFFLE) {
14721 if (RHS.getOperand(0).getOpcode() != ISD::UNDEF)
14722 C = RHS.getOperand(0);
14723 if (RHS.getOperand(1).getOpcode() != ISD::UNDEF)
14724 D = RHS.getOperand(1);
14725 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(RHS.getNode())->getMask();
14726 std::copy(Mask.begin(), Mask.end(), RMask.begin());
14728 if (RHS.getOpcode() != ISD::UNDEF)
14730 for (unsigned i = 0; i != NumElts; ++i)
14734 // Check that the shuffles are both shuffling the same vectors.
14735 if (!(A == C && B == D) && !(A == D && B == C))
14738 // If everything is UNDEF then bail out: it would be better to fold to UNDEF.
14739 if (!A.getNode() && !B.getNode())
14742 // If A and B occur in reverse order in RHS, then "swap" them (which means
14743 // rewriting the mask).
14745 CommuteVectorShuffleMask(RMask, NumElts);
14747 // At this point LHS and RHS are equivalent to
14748 // LHS = VECTOR_SHUFFLE A, B, LMask
14749 // RHS = VECTOR_SHUFFLE A, B, RMask
14750 // Check that the masks correspond to performing a horizontal operation.
14751 for (unsigned i = 0; i != NumElts; ++i) {
14752 int LIdx = LMask[i], RIdx = RMask[i];
14754 // Ignore any UNDEF components.
14755 if (LIdx < 0 || RIdx < 0 ||
14756 (!A.getNode() && (LIdx < (int)NumElts || RIdx < (int)NumElts)) ||
14757 (!B.getNode() && (LIdx >= (int)NumElts || RIdx >= (int)NumElts)))
14760 // Check that successive elements are being operated on. If not, this is
14761 // not a horizontal operation.
14762 unsigned Src = (i/HalfLaneElts) % 2; // each lane is split between srcs
14763 unsigned LaneStart = (i/NumLaneElts) * NumLaneElts;
14764 int Index = 2*(i%HalfLaneElts) + NumElts*Src + LaneStart;
14765 if (!(LIdx == Index && RIdx == Index + 1) &&
14766 !(IsCommutative && LIdx == Index + 1 && RIdx == Index))
14770 LHS = A.getNode() ? A : B; // If A is 'UNDEF', use B for it.
14771 RHS = B.getNode() ? B : A; // If B is 'UNDEF', use A for it.
14775 /// PerformFADDCombine - Do target-specific dag combines on floating point adds.
14776 static SDValue PerformFADDCombine(SDNode *N, SelectionDAG &DAG,
14777 const X86Subtarget *Subtarget) {
14778 EVT VT = N->getValueType(0);
14779 SDValue LHS = N->getOperand(0);
14780 SDValue RHS = N->getOperand(1);
14782 // Try to synthesize horizontal adds from adds of shuffles.
14783 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
14784 (Subtarget->hasAVX() && (VT == MVT::v8f32 || VT == MVT::v4f64))) &&
14785 isHorizontalBinOp(LHS, RHS, true))
14786 return DAG.getNode(X86ISD::FHADD, N->getDebugLoc(), VT, LHS, RHS);
14790 /// PerformFSUBCombine - Do target-specific dag combines on floating point subs.
14791 static SDValue PerformFSUBCombine(SDNode *N, SelectionDAG &DAG,
14792 const X86Subtarget *Subtarget) {
14793 EVT VT = N->getValueType(0);
14794 SDValue LHS = N->getOperand(0);
14795 SDValue RHS = N->getOperand(1);
14797 // Try to synthesize horizontal subs from subs of shuffles.
14798 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
14799 (Subtarget->hasAVX() && (VT == MVT::v8f32 || VT == MVT::v4f64))) &&
14800 isHorizontalBinOp(LHS, RHS, false))
14801 return DAG.getNode(X86ISD::FHSUB, N->getDebugLoc(), VT, LHS, RHS);
14805 /// PerformFORCombine - Do target-specific dag combines on X86ISD::FOR and
14806 /// X86ISD::FXOR nodes.
14807 static SDValue PerformFORCombine(SDNode *N, SelectionDAG &DAG) {
14808 assert(N->getOpcode() == X86ISD::FOR || N->getOpcode() == X86ISD::FXOR);
14809 // F[X]OR(0.0, x) -> x
14810 // F[X]OR(x, 0.0) -> x
14811 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
14812 if (C->getValueAPF().isPosZero())
14813 return N->getOperand(1);
14814 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
14815 if (C->getValueAPF().isPosZero())
14816 return N->getOperand(0);
14820 /// PerformFANDCombine - Do target-specific dag combines on X86ISD::FAND nodes.
14821 static SDValue PerformFANDCombine(SDNode *N, SelectionDAG &DAG) {
14822 // FAND(0.0, x) -> 0.0
14823 // FAND(x, 0.0) -> 0.0
14824 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
14825 if (C->getValueAPF().isPosZero())
14826 return N->getOperand(0);
14827 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
14828 if (C->getValueAPF().isPosZero())
14829 return N->getOperand(1);
14833 static SDValue PerformBTCombine(SDNode *N,
14835 TargetLowering::DAGCombinerInfo &DCI) {
14836 // BT ignores high bits in the bit index operand.
14837 SDValue Op1 = N->getOperand(1);
14838 if (Op1.hasOneUse()) {
14839 unsigned BitWidth = Op1.getValueSizeInBits();
14840 APInt DemandedMask = APInt::getLowBitsSet(BitWidth, Log2_32(BitWidth));
14841 APInt KnownZero, KnownOne;
14842 TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(),
14843 !DCI.isBeforeLegalizeOps());
14844 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
14845 if (TLO.ShrinkDemandedConstant(Op1, DemandedMask) ||
14846 TLI.SimplifyDemandedBits(Op1, DemandedMask, KnownZero, KnownOne, TLO))
14847 DCI.CommitTargetLoweringOpt(TLO);
14852 static SDValue PerformVZEXT_MOVLCombine(SDNode *N, SelectionDAG &DAG) {
14853 SDValue Op = N->getOperand(0);
14854 if (Op.getOpcode() == ISD::BITCAST)
14855 Op = Op.getOperand(0);
14856 EVT VT = N->getValueType(0), OpVT = Op.getValueType();
14857 if (Op.getOpcode() == X86ISD::VZEXT_LOAD &&
14858 VT.getVectorElementType().getSizeInBits() ==
14859 OpVT.getVectorElementType().getSizeInBits()) {
14860 return DAG.getNode(ISD::BITCAST, N->getDebugLoc(), VT, Op);
14865 static SDValue PerformSExtCombine(SDNode *N, SelectionDAG &DAG,
14866 TargetLowering::DAGCombinerInfo &DCI,
14867 const X86Subtarget *Subtarget) {
14868 if (!DCI.isBeforeLegalizeOps())
14871 if (!Subtarget->hasAVX())
14874 EVT VT = N->getValueType(0);
14875 SDValue Op = N->getOperand(0);
14876 EVT OpVT = Op.getValueType();
14877 DebugLoc dl = N->getDebugLoc();
14879 if ((VT == MVT::v4i64 && OpVT == MVT::v4i32) ||
14880 (VT == MVT::v8i32 && OpVT == MVT::v8i16)) {
14882 if (Subtarget->hasAVX2()) {
14883 return DAG.getNode(X86ISD::VSEXT_MOVL, dl, VT, Op);
14886 // Optimize vectors in AVX mode
14887 // Sign extend v8i16 to v8i32 and
14890 // Divide input vector into two parts
14891 // for v4i32 the shuffle mask will be { 0, 1, -1, -1} {2, 3, -1, -1}
14892 // use vpmovsx instruction to extend v4i32 -> v2i64; v8i16 -> v4i32
14893 // concat the vectors to original VT
14895 unsigned NumElems = OpVT.getVectorNumElements();
14896 SmallVector<int,8> ShufMask1(NumElems, -1);
14897 for (unsigned i = 0; i < NumElems/2; i++) ShufMask1[i] = i;
14899 SDValue OpLo = DAG.getVectorShuffle(OpVT, dl, Op, DAG.getUNDEF(OpVT),
14902 SmallVector<int,8> ShufMask2(NumElems, -1);
14903 for (unsigned i = 0; i < NumElems/2; i++) ShufMask2[i] = i + NumElems/2;
14905 SDValue OpHi = DAG.getVectorShuffle(OpVT, dl, Op, DAG.getUNDEF(OpVT),
14908 EVT HalfVT = EVT::getVectorVT(*DAG.getContext(), VT.getScalarType(),
14909 VT.getVectorNumElements()/2);
14911 OpLo = DAG.getNode(X86ISD::VSEXT_MOVL, dl, HalfVT, OpLo);
14912 OpHi = DAG.getNode(X86ISD::VSEXT_MOVL, dl, HalfVT, OpHi);
14914 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi);
14919 static SDValue PerformZExtCombine(SDNode *N, SelectionDAG &DAG,
14920 const X86Subtarget *Subtarget) {
14921 // (i32 zext (and (i8 x86isd::setcc_carry), 1)) ->
14922 // (and (i32 x86isd::setcc_carry), 1)
14923 // This eliminates the zext. This transformation is necessary because
14924 // ISD::SETCC is always legalized to i8.
14925 DebugLoc dl = N->getDebugLoc();
14926 SDValue N0 = N->getOperand(0);
14927 EVT VT = N->getValueType(0);
14928 EVT OpVT = N0.getValueType();
14930 if (N0.getOpcode() == ISD::AND &&
14932 N0.getOperand(0).hasOneUse()) {
14933 SDValue N00 = N0.getOperand(0);
14934 if (N00.getOpcode() != X86ISD::SETCC_CARRY)
14936 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
14937 if (!C || C->getZExtValue() != 1)
14939 return DAG.getNode(ISD::AND, dl, VT,
14940 DAG.getNode(X86ISD::SETCC_CARRY, dl, VT,
14941 N00.getOperand(0), N00.getOperand(1)),
14942 DAG.getConstant(1, VT));
14945 // Optimize vectors in AVX mode:
14948 // Use vpunpcklwd for 4 lower elements v8i16 -> v4i32.
14949 // Use vpunpckhwd for 4 upper elements v8i16 -> v4i32.
14950 // Concat upper and lower parts.
14953 // Use vpunpckldq for 4 lower elements v4i32 -> v2i64.
14954 // Use vpunpckhdq for 4 upper elements v4i32 -> v2i64.
14955 // Concat upper and lower parts.
14957 if (Subtarget->hasAVX()) {
14959 if (((VT == MVT::v8i32) && (OpVT == MVT::v8i16)) ||
14960 ((VT == MVT::v4i64) && (OpVT == MVT::v4i32))) {
14962 if (Subtarget->hasAVX2())
14963 return DAG.getNode(X86ISD::VZEXT_MOVL, dl, VT, N0);
14965 SDValue ZeroVec = getZeroVector(OpVT, Subtarget, DAG, dl);
14966 SDValue OpLo = getTargetShuffleNode(X86ISD::UNPCKL, dl, OpVT, N0, ZeroVec,
14968 SDValue OpHi = getTargetShuffleNode(X86ISD::UNPCKH, dl, OpVT, N0, ZeroVec,
14971 EVT HVT = EVT::getVectorVT(*DAG.getContext(), VT.getVectorElementType(),
14972 VT.getVectorNumElements()/2);
14974 OpLo = DAG.getNode(ISD::BITCAST, dl, HVT, OpLo);
14975 OpHi = DAG.getNode(ISD::BITCAST, dl, HVT, OpHi);
14977 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi);
14984 // Optimize RES = X86ISD::SETCC CONDCODE, EFLAG_INPUT
14985 static SDValue PerformSETCCCombine(SDNode *N, SelectionDAG &DAG) {
14986 unsigned X86CC = N->getConstantOperandVal(0);
14987 SDValue EFLAG = N->getOperand(1);
14988 DebugLoc DL = N->getDebugLoc();
14990 // Materialize "setb reg" as "sbb reg,reg", since it can be extended without
14991 // a zext and produces an all-ones bit which is more useful than 0/1 in some
14993 if (X86CC == X86::COND_B)
14994 return DAG.getNode(ISD::AND, DL, MVT::i8,
14995 DAG.getNode(X86ISD::SETCC_CARRY, DL, MVT::i8,
14996 DAG.getConstant(X86CC, MVT::i8), EFLAG),
14997 DAG.getConstant(1, MVT::i8));
15002 static SDValue PerformSINT_TO_FPCombine(SDNode *N, SelectionDAG &DAG,
15003 const X86TargetLowering *XTLI) {
15004 SDValue Op0 = N->getOperand(0);
15005 // Transform (SINT_TO_FP (i64 ...)) into an x87 operation if we have
15006 // a 32-bit target where SSE doesn't support i64->FP operations.
15007 if (Op0.getOpcode() == ISD::LOAD) {
15008 LoadSDNode *Ld = cast<LoadSDNode>(Op0.getNode());
15009 EVT VT = Ld->getValueType(0);
15010 if (!Ld->isVolatile() && !N->getValueType(0).isVector() &&
15011 ISD::isNON_EXTLoad(Op0.getNode()) && Op0.hasOneUse() &&
15012 !XTLI->getSubtarget()->is64Bit() &&
15013 !DAG.getTargetLoweringInfo().isTypeLegal(VT)) {
15014 SDValue FILDChain = XTLI->BuildFILD(SDValue(N, 0), Ld->getValueType(0),
15015 Ld->getChain(), Op0, DAG);
15016 DAG.ReplaceAllUsesOfValueWith(Op0.getValue(1), FILDChain.getValue(1));
15023 // Optimize RES, EFLAGS = X86ISD::ADC LHS, RHS, EFLAGS
15024 static SDValue PerformADCCombine(SDNode *N, SelectionDAG &DAG,
15025 X86TargetLowering::DAGCombinerInfo &DCI) {
15026 // If the LHS and RHS of the ADC node are zero, then it can't overflow and
15027 // the result is either zero or one (depending on the input carry bit).
15028 // Strength reduce this down to a "set on carry" aka SETCC_CARRY&1.
15029 if (X86::isZeroNode(N->getOperand(0)) &&
15030 X86::isZeroNode(N->getOperand(1)) &&
15031 // We don't have a good way to replace an EFLAGS use, so only do this when
15033 SDValue(N, 1).use_empty()) {
15034 DebugLoc DL = N->getDebugLoc();
15035 EVT VT = N->getValueType(0);
15036 SDValue CarryOut = DAG.getConstant(0, N->getValueType(1));
15037 SDValue Res1 = DAG.getNode(ISD::AND, DL, VT,
15038 DAG.getNode(X86ISD::SETCC_CARRY, DL, VT,
15039 DAG.getConstant(X86::COND_B,MVT::i8),
15041 DAG.getConstant(1, VT));
15042 return DCI.CombineTo(N, Res1, CarryOut);
15048 // fold (add Y, (sete X, 0)) -> adc 0, Y
15049 // (add Y, (setne X, 0)) -> sbb -1, Y
15050 // (sub (sete X, 0), Y) -> sbb 0, Y
15051 // (sub (setne X, 0), Y) -> adc -1, Y
15052 static SDValue OptimizeConditionalInDecrement(SDNode *N, SelectionDAG &DAG) {
15053 DebugLoc DL = N->getDebugLoc();
15055 // Look through ZExts.
15056 SDValue Ext = N->getOperand(N->getOpcode() == ISD::SUB ? 1 : 0);
15057 if (Ext.getOpcode() != ISD::ZERO_EXTEND || !Ext.hasOneUse())
15060 SDValue SetCC = Ext.getOperand(0);
15061 if (SetCC.getOpcode() != X86ISD::SETCC || !SetCC.hasOneUse())
15064 X86::CondCode CC = (X86::CondCode)SetCC.getConstantOperandVal(0);
15065 if (CC != X86::COND_E && CC != X86::COND_NE)
15068 SDValue Cmp = SetCC.getOperand(1);
15069 if (Cmp.getOpcode() != X86ISD::CMP || !Cmp.hasOneUse() ||
15070 !X86::isZeroNode(Cmp.getOperand(1)) ||
15071 !Cmp.getOperand(0).getValueType().isInteger())
15074 SDValue CmpOp0 = Cmp.getOperand(0);
15075 SDValue NewCmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32, CmpOp0,
15076 DAG.getConstant(1, CmpOp0.getValueType()));
15078 SDValue OtherVal = N->getOperand(N->getOpcode() == ISD::SUB ? 0 : 1);
15079 if (CC == X86::COND_NE)
15080 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::ADC : X86ISD::SBB,
15081 DL, OtherVal.getValueType(), OtherVal,
15082 DAG.getConstant(-1ULL, OtherVal.getValueType()), NewCmp);
15083 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::SBB : X86ISD::ADC,
15084 DL, OtherVal.getValueType(), OtherVal,
15085 DAG.getConstant(0, OtherVal.getValueType()), NewCmp);
15088 /// PerformADDCombine - Do target-specific dag combines on integer adds.
15089 static SDValue PerformAddCombine(SDNode *N, SelectionDAG &DAG,
15090 const X86Subtarget *Subtarget) {
15091 EVT VT = N->getValueType(0);
15092 SDValue Op0 = N->getOperand(0);
15093 SDValue Op1 = N->getOperand(1);
15095 // Try to synthesize horizontal adds from adds of shuffles.
15096 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) ||
15097 (Subtarget->hasAVX2() && (VT == MVT::v16i16 || VT == MVT::v8i32))) &&
15098 isHorizontalBinOp(Op0, Op1, true))
15099 return DAG.getNode(X86ISD::HADD, N->getDebugLoc(), VT, Op0, Op1);
15101 return OptimizeConditionalInDecrement(N, DAG);
15104 static SDValue PerformSubCombine(SDNode *N, SelectionDAG &DAG,
15105 const X86Subtarget *Subtarget) {
15106 SDValue Op0 = N->getOperand(0);
15107 SDValue Op1 = N->getOperand(1);
15109 // X86 can't encode an immediate LHS of a sub. See if we can push the
15110 // negation into a preceding instruction.
15111 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op0)) {
15112 // If the RHS of the sub is a XOR with one use and a constant, invert the
15113 // immediate. Then add one to the LHS of the sub so we can turn
15114 // X-Y -> X+~Y+1, saving one register.
15115 if (Op1->hasOneUse() && Op1.getOpcode() == ISD::XOR &&
15116 isa<ConstantSDNode>(Op1.getOperand(1))) {
15117 APInt XorC = cast<ConstantSDNode>(Op1.getOperand(1))->getAPIntValue();
15118 EVT VT = Op0.getValueType();
15119 SDValue NewXor = DAG.getNode(ISD::XOR, Op1.getDebugLoc(), VT,
15121 DAG.getConstant(~XorC, VT));
15122 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, NewXor,
15123 DAG.getConstant(C->getAPIntValue()+1, VT));
15127 // Try to synthesize horizontal adds from adds of shuffles.
15128 EVT VT = N->getValueType(0);
15129 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) ||
15130 (Subtarget->hasAVX2() && (VT == MVT::v16i16 || VT == MVT::v8i32))) &&
15131 isHorizontalBinOp(Op0, Op1, true))
15132 return DAG.getNode(X86ISD::HSUB, N->getDebugLoc(), VT, Op0, Op1);
15134 return OptimizeConditionalInDecrement(N, DAG);
15137 SDValue X86TargetLowering::PerformDAGCombine(SDNode *N,
15138 DAGCombinerInfo &DCI) const {
15139 SelectionDAG &DAG = DCI.DAG;
15140 switch (N->getOpcode()) {
15142 case ISD::EXTRACT_VECTOR_ELT:
15143 return PerformEXTRACT_VECTOR_ELTCombine(N, DAG, DCI);
15145 case ISD::SELECT: return PerformSELECTCombine(N, DAG, DCI, Subtarget);
15146 case X86ISD::CMOV: return PerformCMOVCombine(N, DAG, DCI);
15147 case ISD::ADD: return PerformAddCombine(N, DAG, Subtarget);
15148 case ISD::SUB: return PerformSubCombine(N, DAG, Subtarget);
15149 case X86ISD::ADC: return PerformADCCombine(N, DAG, DCI);
15150 case ISD::MUL: return PerformMulCombine(N, DAG, DCI);
15153 case ISD::SRL: return PerformShiftCombine(N, DAG, DCI, Subtarget);
15154 case ISD::AND: return PerformAndCombine(N, DAG, DCI, Subtarget);
15155 case ISD::OR: return PerformOrCombine(N, DAG, DCI, Subtarget);
15156 case ISD::XOR: return PerformXorCombine(N, DAG, DCI, Subtarget);
15157 case ISD::LOAD: return PerformLOADCombine(N, DAG, Subtarget);
15158 case ISD::STORE: return PerformSTORECombine(N, DAG, Subtarget);
15159 case ISD::SINT_TO_FP: return PerformSINT_TO_FPCombine(N, DAG, this);
15160 case ISD::FADD: return PerformFADDCombine(N, DAG, Subtarget);
15161 case ISD::FSUB: return PerformFSUBCombine(N, DAG, Subtarget);
15163 case X86ISD::FOR: return PerformFORCombine(N, DAG);
15164 case X86ISD::FAND: return PerformFANDCombine(N, DAG);
15165 case X86ISD::BT: return PerformBTCombine(N, DAG, DCI);
15166 case X86ISD::VZEXT_MOVL: return PerformVZEXT_MOVLCombine(N, DAG);
15167 case ISD::ANY_EXTEND:
15168 case ISD::ZERO_EXTEND: return PerformZExtCombine(N, DAG, Subtarget);
15169 case ISD::SIGN_EXTEND: return PerformSExtCombine(N, DAG, DCI, Subtarget);
15170 case ISD::TRUNCATE: return PerformTruncateCombine(N, DAG, DCI);
15171 case X86ISD::SETCC: return PerformSETCCCombine(N, DAG);
15172 case X86ISD::SHUFP: // Handle all target specific shuffles
15173 case X86ISD::PALIGN:
15174 case X86ISD::UNPCKH:
15175 case X86ISD::UNPCKL:
15176 case X86ISD::MOVHLPS:
15177 case X86ISD::MOVLHPS:
15178 case X86ISD::PSHUFD:
15179 case X86ISD::PSHUFHW:
15180 case X86ISD::PSHUFLW:
15181 case X86ISD::MOVSS:
15182 case X86ISD::MOVSD:
15183 case X86ISD::VPERMILP:
15184 case X86ISD::VPERM2X128:
15185 case ISD::VECTOR_SHUFFLE: return PerformShuffleCombine(N, DAG, DCI,Subtarget);
15191 /// isTypeDesirableForOp - Return true if the target has native support for
15192 /// the specified value type and it is 'desirable' to use the type for the
15193 /// given node type. e.g. On x86 i16 is legal, but undesirable since i16
15194 /// instruction encodings are longer and some i16 instructions are slow.
15195 bool X86TargetLowering::isTypeDesirableForOp(unsigned Opc, EVT VT) const {
15196 if (!isTypeLegal(VT))
15198 if (VT != MVT::i16)
15205 case ISD::SIGN_EXTEND:
15206 case ISD::ZERO_EXTEND:
15207 case ISD::ANY_EXTEND:
15220 /// IsDesirableToPromoteOp - This method query the target whether it is
15221 /// beneficial for dag combiner to promote the specified node. If true, it
15222 /// should return the desired promotion type by reference.
15223 bool X86TargetLowering::IsDesirableToPromoteOp(SDValue Op, EVT &PVT) const {
15224 EVT VT = Op.getValueType();
15225 if (VT != MVT::i16)
15228 bool Promote = false;
15229 bool Commute = false;
15230 switch (Op.getOpcode()) {
15233 LoadSDNode *LD = cast<LoadSDNode>(Op);
15234 // If the non-extending load has a single use and it's not live out, then it
15235 // might be folded.
15236 if (LD->getExtensionType() == ISD::NON_EXTLOAD /*&&
15237 Op.hasOneUse()*/) {
15238 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
15239 UE = Op.getNode()->use_end(); UI != UE; ++UI) {
15240 // The only case where we'd want to promote LOAD (rather then it being
15241 // promoted as an operand is when it's only use is liveout.
15242 if (UI->getOpcode() != ISD::CopyToReg)
15249 case ISD::SIGN_EXTEND:
15250 case ISD::ZERO_EXTEND:
15251 case ISD::ANY_EXTEND:
15256 SDValue N0 = Op.getOperand(0);
15257 // Look out for (store (shl (load), x)).
15258 if (MayFoldLoad(N0) && MayFoldIntoStore(Op))
15271 SDValue N0 = Op.getOperand(0);
15272 SDValue N1 = Op.getOperand(1);
15273 if (!Commute && MayFoldLoad(N1))
15275 // Avoid disabling potential load folding opportunities.
15276 if (MayFoldLoad(N0) && (!isa<ConstantSDNode>(N1) || MayFoldIntoStore(Op)))
15278 if (MayFoldLoad(N1) && (!isa<ConstantSDNode>(N0) || MayFoldIntoStore(Op)))
15288 //===----------------------------------------------------------------------===//
15289 // X86 Inline Assembly Support
15290 //===----------------------------------------------------------------------===//
15293 // Helper to match a string separated by whitespace.
15294 bool matchAsmImpl(StringRef s, ArrayRef<const StringRef *> args) {
15295 s = s.substr(s.find_first_not_of(" \t")); // Skip leading whitespace.
15297 for (unsigned i = 0, e = args.size(); i != e; ++i) {
15298 StringRef piece(*args[i]);
15299 if (!s.startswith(piece)) // Check if the piece matches.
15302 s = s.substr(piece.size());
15303 StringRef::size_type pos = s.find_first_not_of(" \t");
15304 if (pos == 0) // We matched a prefix.
15312 const VariadicFunction1<bool, StringRef, StringRef, matchAsmImpl> matchAsm={};
15315 bool X86TargetLowering::ExpandInlineAsm(CallInst *CI) const {
15316 InlineAsm *IA = cast<InlineAsm>(CI->getCalledValue());
15318 std::string AsmStr = IA->getAsmString();
15320 IntegerType *Ty = dyn_cast<IntegerType>(CI->getType());
15321 if (!Ty || Ty->getBitWidth() % 16 != 0)
15324 // TODO: should remove alternatives from the asmstring: "foo {a|b}" -> "foo a"
15325 SmallVector<StringRef, 4> AsmPieces;
15326 SplitString(AsmStr, AsmPieces, ";\n");
15328 switch (AsmPieces.size()) {
15329 default: return false;
15331 // FIXME: this should verify that we are targeting a 486 or better. If not,
15332 // we will turn this bswap into something that will be lowered to logical
15333 // ops instead of emitting the bswap asm. For now, we don't support 486 or
15334 // lower so don't worry about this.
15336 if (matchAsm(AsmPieces[0], "bswap", "$0") ||
15337 matchAsm(AsmPieces[0], "bswapl", "$0") ||
15338 matchAsm(AsmPieces[0], "bswapq", "$0") ||
15339 matchAsm(AsmPieces[0], "bswap", "${0:q}") ||
15340 matchAsm(AsmPieces[0], "bswapl", "${0:q}") ||
15341 matchAsm(AsmPieces[0], "bswapq", "${0:q}")) {
15342 // No need to check constraints, nothing other than the equivalent of
15343 // "=r,0" would be valid here.
15344 return IntrinsicLowering::LowerToByteSwap(CI);
15347 // rorw $$8, ${0:w} --> llvm.bswap.i16
15348 if (CI->getType()->isIntegerTy(16) &&
15349 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 &&
15350 (matchAsm(AsmPieces[0], "rorw", "$$8,", "${0:w}") ||
15351 matchAsm(AsmPieces[0], "rolw", "$$8,", "${0:w}"))) {
15353 const std::string &ConstraintsStr = IA->getConstraintString();
15354 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
15355 std::sort(AsmPieces.begin(), AsmPieces.end());
15356 if (AsmPieces.size() == 4 &&
15357 AsmPieces[0] == "~{cc}" &&
15358 AsmPieces[1] == "~{dirflag}" &&
15359 AsmPieces[2] == "~{flags}" &&
15360 AsmPieces[3] == "~{fpsr}")
15361 return IntrinsicLowering::LowerToByteSwap(CI);
15365 if (CI->getType()->isIntegerTy(32) &&
15366 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 &&
15367 matchAsm(AsmPieces[0], "rorw", "$$8,", "${0:w}") &&
15368 matchAsm(AsmPieces[1], "rorl", "$$16,", "$0") &&
15369 matchAsm(AsmPieces[2], "rorw", "$$8,", "${0:w}")) {
15371 const std::string &ConstraintsStr = IA->getConstraintString();
15372 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
15373 std::sort(AsmPieces.begin(), AsmPieces.end());
15374 if (AsmPieces.size() == 4 &&
15375 AsmPieces[0] == "~{cc}" &&
15376 AsmPieces[1] == "~{dirflag}" &&
15377 AsmPieces[2] == "~{flags}" &&
15378 AsmPieces[3] == "~{fpsr}")
15379 return IntrinsicLowering::LowerToByteSwap(CI);
15382 if (CI->getType()->isIntegerTy(64)) {
15383 InlineAsm::ConstraintInfoVector Constraints = IA->ParseConstraints();
15384 if (Constraints.size() >= 2 &&
15385 Constraints[0].Codes.size() == 1 && Constraints[0].Codes[0] == "A" &&
15386 Constraints[1].Codes.size() == 1 && Constraints[1].Codes[0] == "0") {
15387 // bswap %eax / bswap %edx / xchgl %eax, %edx -> llvm.bswap.i64
15388 if (matchAsm(AsmPieces[0], "bswap", "%eax") &&
15389 matchAsm(AsmPieces[1], "bswap", "%edx") &&
15390 matchAsm(AsmPieces[2], "xchgl", "%eax,", "%edx"))
15391 return IntrinsicLowering::LowerToByteSwap(CI);
15401 /// getConstraintType - Given a constraint letter, return the type of
15402 /// constraint it is for this target.
15403 X86TargetLowering::ConstraintType
15404 X86TargetLowering::getConstraintType(const std::string &Constraint) const {
15405 if (Constraint.size() == 1) {
15406 switch (Constraint[0]) {
15417 return C_RegisterClass;
15441 return TargetLowering::getConstraintType(Constraint);
15444 /// Examine constraint type and operand type and determine a weight value.
15445 /// This object must already have been set up with the operand type
15446 /// and the current alternative constraint selected.
15447 TargetLowering::ConstraintWeight
15448 X86TargetLowering::getSingleConstraintMatchWeight(
15449 AsmOperandInfo &info, const char *constraint) const {
15450 ConstraintWeight weight = CW_Invalid;
15451 Value *CallOperandVal = info.CallOperandVal;
15452 // If we don't have a value, we can't do a match,
15453 // but allow it at the lowest weight.
15454 if (CallOperandVal == NULL)
15456 Type *type = CallOperandVal->getType();
15457 // Look at the constraint type.
15458 switch (*constraint) {
15460 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
15471 if (CallOperandVal->getType()->isIntegerTy())
15472 weight = CW_SpecificReg;
15477 if (type->isFloatingPointTy())
15478 weight = CW_SpecificReg;
15481 if (type->isX86_MMXTy() && Subtarget->hasMMX())
15482 weight = CW_SpecificReg;
15486 if (((type->getPrimitiveSizeInBits() == 128) && Subtarget->hasSSE1()) ||
15487 ((type->getPrimitiveSizeInBits() == 256) && Subtarget->hasAVX()))
15488 weight = CW_Register;
15491 if (ConstantInt *C = dyn_cast<ConstantInt>(info.CallOperandVal)) {
15492 if (C->getZExtValue() <= 31)
15493 weight = CW_Constant;
15497 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
15498 if (C->getZExtValue() <= 63)
15499 weight = CW_Constant;
15503 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
15504 if ((C->getSExtValue() >= -0x80) && (C->getSExtValue() <= 0x7f))
15505 weight = CW_Constant;
15509 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
15510 if ((C->getZExtValue() == 0xff) || (C->getZExtValue() == 0xffff))
15511 weight = CW_Constant;
15515 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
15516 if (C->getZExtValue() <= 3)
15517 weight = CW_Constant;
15521 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
15522 if (C->getZExtValue() <= 0xff)
15523 weight = CW_Constant;
15528 if (dyn_cast<ConstantFP>(CallOperandVal)) {
15529 weight = CW_Constant;
15533 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
15534 if ((C->getSExtValue() >= -0x80000000LL) &&
15535 (C->getSExtValue() <= 0x7fffffffLL))
15536 weight = CW_Constant;
15540 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
15541 if (C->getZExtValue() <= 0xffffffff)
15542 weight = CW_Constant;
15549 /// LowerXConstraint - try to replace an X constraint, which matches anything,
15550 /// with another that has more specific requirements based on the type of the
15551 /// corresponding operand.
15552 const char *X86TargetLowering::
15553 LowerXConstraint(EVT ConstraintVT) const {
15554 // FP X constraints get lowered to SSE1/2 registers if available, otherwise
15555 // 'f' like normal targets.
15556 if (ConstraintVT.isFloatingPoint()) {
15557 if (Subtarget->hasSSE2())
15559 if (Subtarget->hasSSE1())
15563 return TargetLowering::LowerXConstraint(ConstraintVT);
15566 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
15567 /// vector. If it is invalid, don't add anything to Ops.
15568 void X86TargetLowering::LowerAsmOperandForConstraint(SDValue Op,
15569 std::string &Constraint,
15570 std::vector<SDValue>&Ops,
15571 SelectionDAG &DAG) const {
15572 SDValue Result(0, 0);
15574 // Only support length 1 constraints for now.
15575 if (Constraint.length() > 1) return;
15577 char ConstraintLetter = Constraint[0];
15578 switch (ConstraintLetter) {
15581 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
15582 if (C->getZExtValue() <= 31) {
15583 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
15589 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
15590 if (C->getZExtValue() <= 63) {
15591 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
15597 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
15598 if ((int8_t)C->getSExtValue() == C->getSExtValue()) {
15599 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
15605 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
15606 if (C->getZExtValue() <= 255) {
15607 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
15613 // 32-bit signed value
15614 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
15615 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
15616 C->getSExtValue())) {
15617 // Widen to 64 bits here to get it sign extended.
15618 Result = DAG.getTargetConstant(C->getSExtValue(), MVT::i64);
15621 // FIXME gcc accepts some relocatable values here too, but only in certain
15622 // memory models; it's complicated.
15627 // 32-bit unsigned value
15628 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
15629 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
15630 C->getZExtValue())) {
15631 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
15635 // FIXME gcc accepts some relocatable values here too, but only in certain
15636 // memory models; it's complicated.
15640 // Literal immediates are always ok.
15641 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op)) {
15642 // Widen to 64 bits here to get it sign extended.
15643 Result = DAG.getTargetConstant(CST->getSExtValue(), MVT::i64);
15647 // In any sort of PIC mode addresses need to be computed at runtime by
15648 // adding in a register or some sort of table lookup. These can't
15649 // be used as immediates.
15650 if (Subtarget->isPICStyleGOT() || Subtarget->isPICStyleStubPIC())
15653 // If we are in non-pic codegen mode, we allow the address of a global (with
15654 // an optional displacement) to be used with 'i'.
15655 GlobalAddressSDNode *GA = 0;
15656 int64_t Offset = 0;
15658 // Match either (GA), (GA+C), (GA+C1+C2), etc.
15660 if ((GA = dyn_cast<GlobalAddressSDNode>(Op))) {
15661 Offset += GA->getOffset();
15663 } else if (Op.getOpcode() == ISD::ADD) {
15664 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
15665 Offset += C->getZExtValue();
15666 Op = Op.getOperand(0);
15669 } else if (Op.getOpcode() == ISD::SUB) {
15670 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
15671 Offset += -C->getZExtValue();
15672 Op = Op.getOperand(0);
15677 // Otherwise, this isn't something we can handle, reject it.
15681 const GlobalValue *GV = GA->getGlobal();
15682 // If we require an extra load to get this address, as in PIC mode, we
15683 // can't accept it.
15684 if (isGlobalStubReference(Subtarget->ClassifyGlobalReference(GV,
15685 getTargetMachine())))
15688 Result = DAG.getTargetGlobalAddress(GV, Op.getDebugLoc(),
15689 GA->getValueType(0), Offset);
15694 if (Result.getNode()) {
15695 Ops.push_back(Result);
15698 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
15701 std::pair<unsigned, const TargetRegisterClass*>
15702 X86TargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
15704 // First, see if this is a constraint that directly corresponds to an LLVM
15706 if (Constraint.size() == 1) {
15707 // GCC Constraint Letters
15708 switch (Constraint[0]) {
15710 // TODO: Slight differences here in allocation order and leaving
15711 // RIP in the class. Do they matter any more here than they do
15712 // in the normal allocation?
15713 case 'q': // GENERAL_REGS in 64-bit mode, Q_REGS in 32-bit mode.
15714 if (Subtarget->is64Bit()) {
15715 if (VT == MVT::i32 || VT == MVT::f32)
15716 return std::make_pair(0U, &X86::GR32RegClass);
15717 if (VT == MVT::i16)
15718 return std::make_pair(0U, &X86::GR16RegClass);
15719 if (VT == MVT::i8 || VT == MVT::i1)
15720 return std::make_pair(0U, &X86::GR8RegClass);
15721 if (VT == MVT::i64 || VT == MVT::f64)
15722 return std::make_pair(0U, &X86::GR64RegClass);
15725 // 32-bit fallthrough
15726 case 'Q': // Q_REGS
15727 if (VT == MVT::i32 || VT == MVT::f32)
15728 return std::make_pair(0U, &X86::GR32_ABCDRegClass);
15729 if (VT == MVT::i16)
15730 return std::make_pair(0U, &X86::GR16_ABCDRegClass);
15731 if (VT == MVT::i8 || VT == MVT::i1)
15732 return std::make_pair(0U, &X86::GR8_ABCD_LRegClass);
15733 if (VT == MVT::i64)
15734 return std::make_pair(0U, &X86::GR64_ABCDRegClass);
15736 case 'r': // GENERAL_REGS
15737 case 'l': // INDEX_REGS
15738 if (VT == MVT::i8 || VT == MVT::i1)
15739 return std::make_pair(0U, &X86::GR8RegClass);
15740 if (VT == MVT::i16)
15741 return std::make_pair(0U, &X86::GR16RegClass);
15742 if (VT == MVT::i32 || VT == MVT::f32 || !Subtarget->is64Bit())
15743 return std::make_pair(0U, &X86::GR32RegClass);
15744 return std::make_pair(0U, &X86::GR64RegClass);
15745 case 'R': // LEGACY_REGS
15746 if (VT == MVT::i8 || VT == MVT::i1)
15747 return std::make_pair(0U, &X86::GR8_NOREXRegClass);
15748 if (VT == MVT::i16)
15749 return std::make_pair(0U, &X86::GR16_NOREXRegClass);
15750 if (VT == MVT::i32 || !Subtarget->is64Bit())
15751 return std::make_pair(0U, &X86::GR32_NOREXRegClass);
15752 return std::make_pair(0U, &X86::GR64_NOREXRegClass);
15753 case 'f': // FP Stack registers.
15754 // If SSE is enabled for this VT, use f80 to ensure the isel moves the
15755 // value to the correct fpstack register class.
15756 if (VT == MVT::f32 && !isScalarFPTypeInSSEReg(VT))
15757 return std::make_pair(0U, &X86::RFP32RegClass);
15758 if (VT == MVT::f64 && !isScalarFPTypeInSSEReg(VT))
15759 return std::make_pair(0U, &X86::RFP64RegClass);
15760 return std::make_pair(0U, &X86::RFP80RegClass);
15761 case 'y': // MMX_REGS if MMX allowed.
15762 if (!Subtarget->hasMMX()) break;
15763 return std::make_pair(0U, &X86::VR64RegClass);
15764 case 'Y': // SSE_REGS if SSE2 allowed
15765 if (!Subtarget->hasSSE2()) break;
15767 case 'x': // SSE_REGS if SSE1 allowed or AVX_REGS if AVX allowed
15768 if (!Subtarget->hasSSE1()) break;
15770 switch (VT.getSimpleVT().SimpleTy) {
15772 // Scalar SSE types.
15775 return std::make_pair(0U, &X86::FR32RegClass);
15778 return std::make_pair(0U, &X86::FR64RegClass);
15786 return std::make_pair(0U, &X86::VR128RegClass);
15794 return std::make_pair(0U, &X86::VR256RegClass);
15800 // Use the default implementation in TargetLowering to convert the register
15801 // constraint into a member of a register class.
15802 std::pair<unsigned, const TargetRegisterClass*> Res;
15803 Res = TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
15805 // Not found as a standard register?
15806 if (Res.second == 0) {
15807 // Map st(0) -> st(7) -> ST0
15808 if (Constraint.size() == 7 && Constraint[0] == '{' &&
15809 tolower(Constraint[1]) == 's' &&
15810 tolower(Constraint[2]) == 't' &&
15811 Constraint[3] == '(' &&
15812 (Constraint[4] >= '0' && Constraint[4] <= '7') &&
15813 Constraint[5] == ')' &&
15814 Constraint[6] == '}') {
15816 Res.first = X86::ST0+Constraint[4]-'0';
15817 Res.second = &X86::RFP80RegClass;
15821 // GCC allows "st(0)" to be called just plain "st".
15822 if (StringRef("{st}").equals_lower(Constraint)) {
15823 Res.first = X86::ST0;
15824 Res.second = &X86::RFP80RegClass;
15829 if (StringRef("{flags}").equals_lower(Constraint)) {
15830 Res.first = X86::EFLAGS;
15831 Res.second = &X86::CCRRegClass;
15835 // 'A' means EAX + EDX.
15836 if (Constraint == "A") {
15837 Res.first = X86::EAX;
15838 Res.second = &X86::GR32_ADRegClass;
15844 // Otherwise, check to see if this is a register class of the wrong value
15845 // type. For example, we want to map "{ax},i32" -> {eax}, we don't want it to
15846 // turn into {ax},{dx}.
15847 if (Res.second->hasType(VT))
15848 return Res; // Correct type already, nothing to do.
15850 // All of the single-register GCC register classes map their values onto
15851 // 16-bit register pieces "ax","dx","cx","bx","si","di","bp","sp". If we
15852 // really want an 8-bit or 32-bit register, map to the appropriate register
15853 // class and return the appropriate register.
15854 if (Res.second == &X86::GR16RegClass) {
15855 if (VT == MVT::i8) {
15856 unsigned DestReg = 0;
15857 switch (Res.first) {
15859 case X86::AX: DestReg = X86::AL; break;
15860 case X86::DX: DestReg = X86::DL; break;
15861 case X86::CX: DestReg = X86::CL; break;
15862 case X86::BX: DestReg = X86::BL; break;
15865 Res.first = DestReg;
15866 Res.second = &X86::GR8RegClass;
15868 } else if (VT == MVT::i32) {
15869 unsigned DestReg = 0;
15870 switch (Res.first) {
15872 case X86::AX: DestReg = X86::EAX; break;
15873 case X86::DX: DestReg = X86::EDX; break;
15874 case X86::CX: DestReg = X86::ECX; break;
15875 case X86::BX: DestReg = X86::EBX; break;
15876 case X86::SI: DestReg = X86::ESI; break;
15877 case X86::DI: DestReg = X86::EDI; break;
15878 case X86::BP: DestReg = X86::EBP; break;
15879 case X86::SP: DestReg = X86::ESP; break;
15882 Res.first = DestReg;
15883 Res.second = &X86::GR32RegClass;
15885 } else if (VT == MVT::i64) {
15886 unsigned DestReg = 0;
15887 switch (Res.first) {
15889 case X86::AX: DestReg = X86::RAX; break;
15890 case X86::DX: DestReg = X86::RDX; break;
15891 case X86::CX: DestReg = X86::RCX; break;
15892 case X86::BX: DestReg = X86::RBX; break;
15893 case X86::SI: DestReg = X86::RSI; break;
15894 case X86::DI: DestReg = X86::RDI; break;
15895 case X86::BP: DestReg = X86::RBP; break;
15896 case X86::SP: DestReg = X86::RSP; break;
15899 Res.first = DestReg;
15900 Res.second = &X86::GR64RegClass;
15903 } else if (Res.second == &X86::FR32RegClass ||
15904 Res.second == &X86::FR64RegClass ||
15905 Res.second == &X86::VR128RegClass) {
15906 // Handle references to XMM physical registers that got mapped into the
15907 // wrong class. This can happen with constraints like {xmm0} where the
15908 // target independent register mapper will just pick the first match it can
15909 // find, ignoring the required type.
15910 if (VT == MVT::f32)
15911 Res.second = &X86::FR32RegClass;
15912 else if (VT == MVT::f64)
15913 Res.second = &X86::FR64RegClass;
15914 else if (X86::VR128RegClass.hasType(VT))
15915 Res.second = &X86::VR128RegClass;