1 //===-- X86ISelLowering.cpp - X86 DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that X86 uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "x86-isel"
17 #include "X86InstrBuilder.h"
18 #include "X86ISelLowering.h"
19 #include "X86TargetMachine.h"
20 #include "X86TargetObjectFile.h"
21 #include "Utils/X86ShuffleDecode.h"
22 #include "llvm/CallingConv.h"
23 #include "llvm/Constants.h"
24 #include "llvm/DerivedTypes.h"
25 #include "llvm/GlobalAlias.h"
26 #include "llvm/GlobalVariable.h"
27 #include "llvm/Function.h"
28 #include "llvm/Instructions.h"
29 #include "llvm/Intrinsics.h"
30 #include "llvm/LLVMContext.h"
31 #include "llvm/CodeGen/IntrinsicLowering.h"
32 #include "llvm/CodeGen/MachineFrameInfo.h"
33 #include "llvm/CodeGen/MachineFunction.h"
34 #include "llvm/CodeGen/MachineInstrBuilder.h"
35 #include "llvm/CodeGen/MachineJumpTableInfo.h"
36 #include "llvm/CodeGen/MachineModuleInfo.h"
37 #include "llvm/CodeGen/MachineRegisterInfo.h"
38 #include "llvm/MC/MCAsmInfo.h"
39 #include "llvm/MC/MCContext.h"
40 #include "llvm/MC/MCExpr.h"
41 #include "llvm/MC/MCSymbol.h"
42 #include "llvm/ADT/BitVector.h"
43 #include "llvm/ADT/SmallSet.h"
44 #include "llvm/ADT/Statistic.h"
45 #include "llvm/ADT/StringExtras.h"
46 #include "llvm/ADT/VariadicFunction.h"
47 #include "llvm/Support/CallSite.h"
48 #include "llvm/Support/CommandLine.h"
49 #include "llvm/Support/Debug.h"
50 #include "llvm/Support/Dwarf.h"
51 #include "llvm/Support/ErrorHandling.h"
52 #include "llvm/Support/MathExtras.h"
53 #include "llvm/Support/raw_ostream.h"
54 #include "llvm/Target/TargetOptions.h"
57 using namespace dwarf;
59 STATISTIC(NumTailCalls, "Number of tail calls");
61 static cl::opt<bool> UseRegMask("x86-use-regmask",
62 cl::desc("Use register masks for x86 calls"));
64 // Forward declarations.
65 static SDValue getMOVL(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1,
68 /// Generate a DAG to grab 128-bits from a vector > 128 bits. This
69 /// sets things up to match to an AVX VEXTRACTF128 instruction or a
70 /// simple subregister reference. Idx is an index in the 128 bits we
71 /// want. It need not be aligned to a 128-bit bounday. That makes
72 /// lowering EXTRACT_VECTOR_ELT operations easier.
73 static SDValue Extract128BitVector(SDValue Vec,
77 EVT VT = Vec.getValueType();
78 assert(VT.getSizeInBits() == 256 && "Unexpected vector size!");
79 EVT ElVT = VT.getVectorElementType();
80 int Factor = VT.getSizeInBits()/128;
81 EVT ResultVT = EVT::getVectorVT(*DAG.getContext(), ElVT,
82 VT.getVectorNumElements()/Factor);
84 // Extract from UNDEF is UNDEF.
85 if (Vec.getOpcode() == ISD::UNDEF)
86 return DAG.getNode(ISD::UNDEF, dl, ResultVT);
88 if (isa<ConstantSDNode>(Idx)) {
89 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
91 // Extract the relevant 128 bits. Generate an EXTRACT_SUBVECTOR
92 // we can match to VEXTRACTF128.
93 unsigned ElemsPerChunk = 128 / ElVT.getSizeInBits();
95 // This is the index of the first element of the 128-bit chunk
97 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits()) / 128)
100 SDValue VecIdx = DAG.getConstant(NormalizedIdxVal, MVT::i32);
101 SDValue Result = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, ResultVT, Vec,
110 /// Generate a DAG to put 128-bits into a vector > 128 bits. This
111 /// sets things up to match to an AVX VINSERTF128 instruction or a
112 /// simple superregister reference. Idx is an index in the 128 bits
113 /// we want. It need not be aligned to a 128-bit bounday. That makes
114 /// lowering INSERT_VECTOR_ELT operations easier.
115 static SDValue Insert128BitVector(SDValue Result,
120 if (isa<ConstantSDNode>(Idx)) {
121 EVT VT = Vec.getValueType();
122 assert(VT.getSizeInBits() == 128 && "Unexpected vector size!");
124 EVT ElVT = VT.getVectorElementType();
125 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
126 EVT ResultVT = Result.getValueType();
128 // Insert the relevant 128 bits.
129 unsigned ElemsPerChunk = 128/ElVT.getSizeInBits();
131 // This is the index of the first element of the 128-bit chunk
133 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits())/128)
136 SDValue VecIdx = DAG.getConstant(NormalizedIdxVal, MVT::i32);
137 Result = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResultVT, Result, Vec,
145 static TargetLoweringObjectFile *createTLOF(X86TargetMachine &TM) {
146 const X86Subtarget *Subtarget = &TM.getSubtarget<X86Subtarget>();
147 bool is64Bit = Subtarget->is64Bit();
149 if (Subtarget->isTargetEnvMacho()) {
151 return new X8664_MachoTargetObjectFile();
152 return new TargetLoweringObjectFileMachO();
155 if (Subtarget->isTargetELF())
156 return new TargetLoweringObjectFileELF();
157 if (Subtarget->isTargetCOFF() && !Subtarget->isTargetEnvMacho())
158 return new TargetLoweringObjectFileCOFF();
159 llvm_unreachable("unknown subtarget type");
162 X86TargetLowering::X86TargetLowering(X86TargetMachine &TM)
163 : TargetLowering(TM, createTLOF(TM)) {
164 Subtarget = &TM.getSubtarget<X86Subtarget>();
165 X86ScalarSSEf64 = Subtarget->hasSSE2();
166 X86ScalarSSEf32 = Subtarget->hasSSE1();
167 X86StackPtr = Subtarget->is64Bit() ? X86::RSP : X86::ESP;
169 RegInfo = TM.getRegisterInfo();
170 TD = getTargetData();
172 // Set up the TargetLowering object.
173 static MVT IntVTs[] = { MVT::i8, MVT::i16, MVT::i32, MVT::i64 };
175 // X86 is weird, it always uses i8 for shift amounts and setcc results.
176 setBooleanContents(ZeroOrOneBooleanContent);
177 // X86-SSE is even stranger. It uses -1 or 0 for vector masks.
178 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
180 // For 64-bit since we have so many registers use the ILP scheduler, for
181 // 32-bit code use the register pressure specific scheduling.
182 // For 32 bit Atom, use Hybrid (register pressure + latency) scheduling.
183 if (Subtarget->is64Bit())
184 setSchedulingPreference(Sched::ILP);
185 else if (Subtarget->isAtom())
186 setSchedulingPreference(Sched::Hybrid);
188 setSchedulingPreference(Sched::RegPressure);
189 setStackPointerRegisterToSaveRestore(X86StackPtr);
191 if (Subtarget->isTargetWindows() && !Subtarget->isTargetCygMing()) {
192 // Setup Windows compiler runtime calls.
193 setLibcallName(RTLIB::SDIV_I64, "_alldiv");
194 setLibcallName(RTLIB::UDIV_I64, "_aulldiv");
195 setLibcallName(RTLIB::SREM_I64, "_allrem");
196 setLibcallName(RTLIB::UREM_I64, "_aullrem");
197 setLibcallName(RTLIB::MUL_I64, "_allmul");
198 setLibcallName(RTLIB::FPTOUINT_F64_I64, "_ftol2");
199 setLibcallName(RTLIB::FPTOUINT_F32_I64, "_ftol2");
200 setLibcallCallingConv(RTLIB::SDIV_I64, CallingConv::X86_StdCall);
201 setLibcallCallingConv(RTLIB::UDIV_I64, CallingConv::X86_StdCall);
202 setLibcallCallingConv(RTLIB::SREM_I64, CallingConv::X86_StdCall);
203 setLibcallCallingConv(RTLIB::UREM_I64, CallingConv::X86_StdCall);
204 setLibcallCallingConv(RTLIB::MUL_I64, CallingConv::X86_StdCall);
205 setLibcallCallingConv(RTLIB::FPTOUINT_F64_I64, CallingConv::C);
206 setLibcallCallingConv(RTLIB::FPTOUINT_F32_I64, CallingConv::C);
209 if (Subtarget->isTargetDarwin()) {
210 // Darwin should use _setjmp/_longjmp instead of setjmp/longjmp.
211 setUseUnderscoreSetJmp(false);
212 setUseUnderscoreLongJmp(false);
213 } else if (Subtarget->isTargetMingw()) {
214 // MS runtime is weird: it exports _setjmp, but longjmp!
215 setUseUnderscoreSetJmp(true);
216 setUseUnderscoreLongJmp(false);
218 setUseUnderscoreSetJmp(true);
219 setUseUnderscoreLongJmp(true);
222 // Set up the register classes.
223 addRegisterClass(MVT::i8, X86::GR8RegisterClass);
224 addRegisterClass(MVT::i16, X86::GR16RegisterClass);
225 addRegisterClass(MVT::i32, X86::GR32RegisterClass);
226 if (Subtarget->is64Bit())
227 addRegisterClass(MVT::i64, X86::GR64RegisterClass);
229 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
231 // We don't accept any truncstore of integer registers.
232 setTruncStoreAction(MVT::i64, MVT::i32, Expand);
233 setTruncStoreAction(MVT::i64, MVT::i16, Expand);
234 setTruncStoreAction(MVT::i64, MVT::i8 , Expand);
235 setTruncStoreAction(MVT::i32, MVT::i16, Expand);
236 setTruncStoreAction(MVT::i32, MVT::i8 , Expand);
237 setTruncStoreAction(MVT::i16, MVT::i8, Expand);
239 // SETOEQ and SETUNE require checking two conditions.
240 setCondCodeAction(ISD::SETOEQ, MVT::f32, Expand);
241 setCondCodeAction(ISD::SETOEQ, MVT::f64, Expand);
242 setCondCodeAction(ISD::SETOEQ, MVT::f80, Expand);
243 setCondCodeAction(ISD::SETUNE, MVT::f32, Expand);
244 setCondCodeAction(ISD::SETUNE, MVT::f64, Expand);
245 setCondCodeAction(ISD::SETUNE, MVT::f80, Expand);
247 // Promote all UINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have this
249 setOperationAction(ISD::UINT_TO_FP , MVT::i1 , Promote);
250 setOperationAction(ISD::UINT_TO_FP , MVT::i8 , Promote);
251 setOperationAction(ISD::UINT_TO_FP , MVT::i16 , Promote);
253 if (Subtarget->is64Bit()) {
254 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote);
255 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
256 } else if (!TM.Options.UseSoftFloat) {
257 // We have an algorithm for SSE2->double, and we turn this into a
258 // 64-bit FILD followed by conditional FADD for other targets.
259 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
260 // We have an algorithm for SSE2, and we turn this into a 64-bit
261 // FILD for other targets.
262 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Custom);
265 // Promote i1/i8 SINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have
267 setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote);
268 setOperationAction(ISD::SINT_TO_FP , MVT::i8 , Promote);
270 if (!TM.Options.UseSoftFloat) {
271 // SSE has no i16 to fp conversion, only i32
272 if (X86ScalarSSEf32) {
273 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
274 // f32 and f64 cases are Legal, f80 case is not
275 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
277 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Custom);
278 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
281 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
282 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Promote);
285 // In 32-bit mode these are custom lowered. In 64-bit mode F32 and F64
286 // are Legal, f80 is custom lowered.
287 setOperationAction(ISD::FP_TO_SINT , MVT::i64 , Custom);
288 setOperationAction(ISD::SINT_TO_FP , MVT::i64 , Custom);
290 // Promote i1/i8 FP_TO_SINT to larger FP_TO_SINTS's, as X86 doesn't have
292 setOperationAction(ISD::FP_TO_SINT , MVT::i1 , Promote);
293 setOperationAction(ISD::FP_TO_SINT , MVT::i8 , Promote);
295 if (X86ScalarSSEf32) {
296 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Promote);
297 // f32 and f64 cases are Legal, f80 case is not
298 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
300 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Custom);
301 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
304 // Handle FP_TO_UINT by promoting the destination to a larger signed
306 setOperationAction(ISD::FP_TO_UINT , MVT::i1 , Promote);
307 setOperationAction(ISD::FP_TO_UINT , MVT::i8 , Promote);
308 setOperationAction(ISD::FP_TO_UINT , MVT::i16 , Promote);
310 if (Subtarget->is64Bit()) {
311 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Expand);
312 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote);
313 } else if (!TM.Options.UseSoftFloat) {
314 // Since AVX is a superset of SSE3, only check for SSE here.
315 if (Subtarget->hasSSE1() && !Subtarget->hasSSE3())
316 // Expand FP_TO_UINT into a select.
317 // FIXME: We would like to use a Custom expander here eventually to do
318 // the optimal thing for SSE vs. the default expansion in the legalizer.
319 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Expand);
321 // With SSE3 we can use fisttpll to convert to a signed i64; without
322 // SSE, we're stuck with a fistpll.
323 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Custom);
326 // TODO: when we have SSE, these could be more efficient, by using movd/movq.
327 if (!X86ScalarSSEf64) {
328 setOperationAction(ISD::BITCAST , MVT::f32 , Expand);
329 setOperationAction(ISD::BITCAST , MVT::i32 , Expand);
330 if (Subtarget->is64Bit()) {
331 setOperationAction(ISD::BITCAST , MVT::f64 , Expand);
332 // Without SSE, i64->f64 goes through memory.
333 setOperationAction(ISD::BITCAST , MVT::i64 , Expand);
337 // Scalar integer divide and remainder are lowered to use operations that
338 // produce two results, to match the available instructions. This exposes
339 // the two-result form to trivial CSE, which is able to combine x/y and x%y
340 // into a single instruction.
342 // Scalar integer multiply-high is also lowered to use two-result
343 // operations, to match the available instructions. However, plain multiply
344 // (low) operations are left as Legal, as there are single-result
345 // instructions for this in x86. Using the two-result multiply instructions
346 // when both high and low results are needed must be arranged by dagcombine.
347 for (unsigned i = 0, e = 4; i != e; ++i) {
349 setOperationAction(ISD::MULHS, VT, Expand);
350 setOperationAction(ISD::MULHU, VT, Expand);
351 setOperationAction(ISD::SDIV, VT, Expand);
352 setOperationAction(ISD::UDIV, VT, Expand);
353 setOperationAction(ISD::SREM, VT, Expand);
354 setOperationAction(ISD::UREM, VT, Expand);
356 // Add/Sub overflow ops with MVT::Glues are lowered to EFLAGS dependences.
357 setOperationAction(ISD::ADDC, VT, Custom);
358 setOperationAction(ISD::ADDE, VT, Custom);
359 setOperationAction(ISD::SUBC, VT, Custom);
360 setOperationAction(ISD::SUBE, VT, Custom);
363 setOperationAction(ISD::BR_JT , MVT::Other, Expand);
364 setOperationAction(ISD::BRCOND , MVT::Other, Custom);
365 setOperationAction(ISD::BR_CC , MVT::Other, Expand);
366 setOperationAction(ISD::SELECT_CC , MVT::Other, Expand);
367 if (Subtarget->is64Bit())
368 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal);
369 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Legal);
370 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Legal);
371 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
372 setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand);
373 setOperationAction(ISD::FREM , MVT::f32 , Expand);
374 setOperationAction(ISD::FREM , MVT::f64 , Expand);
375 setOperationAction(ISD::FREM , MVT::f80 , Expand);
376 setOperationAction(ISD::FLT_ROUNDS_ , MVT::i32 , Custom);
378 // Promote the i8 variants and force them on up to i32 which has a shorter
380 setOperationAction(ISD::CTTZ , MVT::i8 , Promote);
381 AddPromotedToType (ISD::CTTZ , MVT::i8 , MVT::i32);
382 setOperationAction(ISD::CTTZ_ZERO_UNDEF , MVT::i8 , Promote);
383 AddPromotedToType (ISD::CTTZ_ZERO_UNDEF , MVT::i8 , MVT::i32);
384 if (Subtarget->hasBMI()) {
385 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i16 , Expand);
386 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32 , Expand);
387 if (Subtarget->is64Bit())
388 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand);
390 setOperationAction(ISD::CTTZ , MVT::i16 , Custom);
391 setOperationAction(ISD::CTTZ , MVT::i32 , Custom);
392 if (Subtarget->is64Bit())
393 setOperationAction(ISD::CTTZ , MVT::i64 , Custom);
396 if (Subtarget->hasLZCNT()) {
397 // When promoting the i8 variants, force them to i32 for a shorter
399 setOperationAction(ISD::CTLZ , MVT::i8 , Promote);
400 AddPromotedToType (ISD::CTLZ , MVT::i8 , MVT::i32);
401 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Promote);
402 AddPromotedToType (ISD::CTLZ_ZERO_UNDEF, MVT::i8 , MVT::i32);
403 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Expand);
404 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Expand);
405 if (Subtarget->is64Bit())
406 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Expand);
408 setOperationAction(ISD::CTLZ , MVT::i8 , Custom);
409 setOperationAction(ISD::CTLZ , MVT::i16 , Custom);
410 setOperationAction(ISD::CTLZ , MVT::i32 , Custom);
411 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Custom);
412 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Custom);
413 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Custom);
414 if (Subtarget->is64Bit()) {
415 setOperationAction(ISD::CTLZ , MVT::i64 , Custom);
416 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Custom);
420 if (Subtarget->hasPOPCNT()) {
421 setOperationAction(ISD::CTPOP , MVT::i8 , Promote);
423 setOperationAction(ISD::CTPOP , MVT::i8 , Expand);
424 setOperationAction(ISD::CTPOP , MVT::i16 , Expand);
425 setOperationAction(ISD::CTPOP , MVT::i32 , Expand);
426 if (Subtarget->is64Bit())
427 setOperationAction(ISD::CTPOP , MVT::i64 , Expand);
430 setOperationAction(ISD::READCYCLECOUNTER , MVT::i64 , Custom);
431 setOperationAction(ISD::BSWAP , MVT::i16 , Expand);
433 // These should be promoted to a larger select which is supported.
434 setOperationAction(ISD::SELECT , MVT::i1 , Promote);
435 // X86 wants to expand cmov itself.
436 setOperationAction(ISD::SELECT , MVT::i8 , Custom);
437 setOperationAction(ISD::SELECT , MVT::i16 , Custom);
438 setOperationAction(ISD::SELECT , MVT::i32 , Custom);
439 setOperationAction(ISD::SELECT , MVT::f32 , Custom);
440 setOperationAction(ISD::SELECT , MVT::f64 , Custom);
441 setOperationAction(ISD::SELECT , MVT::f80 , Custom);
442 setOperationAction(ISD::SETCC , MVT::i8 , Custom);
443 setOperationAction(ISD::SETCC , MVT::i16 , Custom);
444 setOperationAction(ISD::SETCC , MVT::i32 , Custom);
445 setOperationAction(ISD::SETCC , MVT::f32 , Custom);
446 setOperationAction(ISD::SETCC , MVT::f64 , Custom);
447 setOperationAction(ISD::SETCC , MVT::f80 , Custom);
448 if (Subtarget->is64Bit()) {
449 setOperationAction(ISD::SELECT , MVT::i64 , Custom);
450 setOperationAction(ISD::SETCC , MVT::i64 , Custom);
452 setOperationAction(ISD::EH_RETURN , MVT::Other, Custom);
455 setOperationAction(ISD::ConstantPool , MVT::i32 , Custom);
456 setOperationAction(ISD::JumpTable , MVT::i32 , Custom);
457 setOperationAction(ISD::GlobalAddress , MVT::i32 , Custom);
458 setOperationAction(ISD::GlobalTLSAddress, MVT::i32 , Custom);
459 if (Subtarget->is64Bit())
460 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
461 setOperationAction(ISD::ExternalSymbol , MVT::i32 , Custom);
462 setOperationAction(ISD::BlockAddress , MVT::i32 , Custom);
463 if (Subtarget->is64Bit()) {
464 setOperationAction(ISD::ConstantPool , MVT::i64 , Custom);
465 setOperationAction(ISD::JumpTable , MVT::i64 , Custom);
466 setOperationAction(ISD::GlobalAddress , MVT::i64 , Custom);
467 setOperationAction(ISD::ExternalSymbol, MVT::i64 , Custom);
468 setOperationAction(ISD::BlockAddress , MVT::i64 , Custom);
470 // 64-bit addm sub, shl, sra, srl (iff 32-bit x86)
471 setOperationAction(ISD::SHL_PARTS , MVT::i32 , Custom);
472 setOperationAction(ISD::SRA_PARTS , MVT::i32 , Custom);
473 setOperationAction(ISD::SRL_PARTS , MVT::i32 , Custom);
474 if (Subtarget->is64Bit()) {
475 setOperationAction(ISD::SHL_PARTS , MVT::i64 , Custom);
476 setOperationAction(ISD::SRA_PARTS , MVT::i64 , Custom);
477 setOperationAction(ISD::SRL_PARTS , MVT::i64 , Custom);
480 if (Subtarget->hasSSE1())
481 setOperationAction(ISD::PREFETCH , MVT::Other, Legal);
483 setOperationAction(ISD::MEMBARRIER , MVT::Other, Custom);
484 setOperationAction(ISD::ATOMIC_FENCE , MVT::Other, Custom);
486 // On X86 and X86-64, atomic operations are lowered to locked instructions.
487 // Locked instructions, in turn, have implicit fence semantics (all memory
488 // operations are flushed before issuing the locked instruction, and they
489 // are not buffered), so we can fold away the common pattern of
490 // fence-atomic-fence.
491 setShouldFoldAtomicFences(true);
493 // Expand certain atomics
494 for (unsigned i = 0, e = 4; i != e; ++i) {
496 setOperationAction(ISD::ATOMIC_CMP_SWAP, VT, Custom);
497 setOperationAction(ISD::ATOMIC_LOAD_SUB, VT, Custom);
498 setOperationAction(ISD::ATOMIC_STORE, VT, Custom);
501 if (!Subtarget->is64Bit()) {
502 setOperationAction(ISD::ATOMIC_LOAD, MVT::i64, Custom);
503 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i64, Custom);
504 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i64, Custom);
505 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i64, Custom);
506 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i64, Custom);
507 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i64, Custom);
508 setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i64, Custom);
509 setOperationAction(ISD::ATOMIC_SWAP, MVT::i64, Custom);
512 if (Subtarget->hasCmpxchg16b()) {
513 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i128, Custom);
516 // FIXME - use subtarget debug flags
517 if (!Subtarget->isTargetDarwin() &&
518 !Subtarget->isTargetELF() &&
519 !Subtarget->isTargetCygMing()) {
520 setOperationAction(ISD::EH_LABEL, MVT::Other, Expand);
523 setOperationAction(ISD::EXCEPTIONADDR, MVT::i64, Expand);
524 setOperationAction(ISD::EHSELECTION, MVT::i64, Expand);
525 setOperationAction(ISD::EXCEPTIONADDR, MVT::i32, Expand);
526 setOperationAction(ISD::EHSELECTION, MVT::i32, Expand);
527 if (Subtarget->is64Bit()) {
528 setExceptionPointerRegister(X86::RAX);
529 setExceptionSelectorRegister(X86::RDX);
531 setExceptionPointerRegister(X86::EAX);
532 setExceptionSelectorRegister(X86::EDX);
534 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i32, Custom);
535 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i64, Custom);
537 setOperationAction(ISD::INIT_TRAMPOLINE, MVT::Other, Custom);
538 setOperationAction(ISD::ADJUST_TRAMPOLINE, MVT::Other, Custom);
540 setOperationAction(ISD::TRAP, MVT::Other, Legal);
542 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
543 setOperationAction(ISD::VASTART , MVT::Other, Custom);
544 setOperationAction(ISD::VAEND , MVT::Other, Expand);
545 if (Subtarget->is64Bit()) {
546 setOperationAction(ISD::VAARG , MVT::Other, Custom);
547 setOperationAction(ISD::VACOPY , MVT::Other, Custom);
549 setOperationAction(ISD::VAARG , MVT::Other, Expand);
550 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
553 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
554 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
556 if (Subtarget->isTargetCOFF() && !Subtarget->isTargetEnvMacho())
557 setOperationAction(ISD::DYNAMIC_STACKALLOC, Subtarget->is64Bit() ?
558 MVT::i64 : MVT::i32, Custom);
559 else if (TM.Options.EnableSegmentedStacks)
560 setOperationAction(ISD::DYNAMIC_STACKALLOC, Subtarget->is64Bit() ?
561 MVT::i64 : MVT::i32, Custom);
563 setOperationAction(ISD::DYNAMIC_STACKALLOC, Subtarget->is64Bit() ?
564 MVT::i64 : MVT::i32, Expand);
566 if (!TM.Options.UseSoftFloat && X86ScalarSSEf64) {
567 // f32 and f64 use SSE.
568 // Set up the FP register classes.
569 addRegisterClass(MVT::f32, X86::FR32RegisterClass);
570 addRegisterClass(MVT::f64, X86::FR64RegisterClass);
572 // Use ANDPD to simulate FABS.
573 setOperationAction(ISD::FABS , MVT::f64, Custom);
574 setOperationAction(ISD::FABS , MVT::f32, Custom);
576 // Use XORP to simulate FNEG.
577 setOperationAction(ISD::FNEG , MVT::f64, Custom);
578 setOperationAction(ISD::FNEG , MVT::f32, Custom);
580 // Use ANDPD and ORPD to simulate FCOPYSIGN.
581 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
582 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
584 // Lower this to FGETSIGNx86 plus an AND.
585 setOperationAction(ISD::FGETSIGN, MVT::i64, Custom);
586 setOperationAction(ISD::FGETSIGN, MVT::i32, Custom);
588 // We don't support sin/cos/fmod
589 setOperationAction(ISD::FSIN , MVT::f64, Expand);
590 setOperationAction(ISD::FCOS , MVT::f64, Expand);
591 setOperationAction(ISD::FSIN , MVT::f32, Expand);
592 setOperationAction(ISD::FCOS , MVT::f32, Expand);
594 // Expand FP immediates into loads from the stack, except for the special
596 addLegalFPImmediate(APFloat(+0.0)); // xorpd
597 addLegalFPImmediate(APFloat(+0.0f)); // xorps
598 } else if (!TM.Options.UseSoftFloat && X86ScalarSSEf32) {
599 // Use SSE for f32, x87 for f64.
600 // Set up the FP register classes.
601 addRegisterClass(MVT::f32, X86::FR32RegisterClass);
602 addRegisterClass(MVT::f64, X86::RFP64RegisterClass);
604 // Use ANDPS to simulate FABS.
605 setOperationAction(ISD::FABS , MVT::f32, Custom);
607 // Use XORP to simulate FNEG.
608 setOperationAction(ISD::FNEG , MVT::f32, Custom);
610 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
612 // Use ANDPS and ORPS to simulate FCOPYSIGN.
613 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
614 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
616 // We don't support sin/cos/fmod
617 setOperationAction(ISD::FSIN , MVT::f32, Expand);
618 setOperationAction(ISD::FCOS , MVT::f32, Expand);
620 // Special cases we handle for FP constants.
621 addLegalFPImmediate(APFloat(+0.0f)); // xorps
622 addLegalFPImmediate(APFloat(+0.0)); // FLD0
623 addLegalFPImmediate(APFloat(+1.0)); // FLD1
624 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
625 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
627 if (!TM.Options.UnsafeFPMath) {
628 setOperationAction(ISD::FSIN , MVT::f64 , Expand);
629 setOperationAction(ISD::FCOS , MVT::f64 , Expand);
631 } else if (!TM.Options.UseSoftFloat) {
632 // f32 and f64 in x87.
633 // Set up the FP register classes.
634 addRegisterClass(MVT::f64, X86::RFP64RegisterClass);
635 addRegisterClass(MVT::f32, X86::RFP32RegisterClass);
637 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
638 setOperationAction(ISD::UNDEF, MVT::f32, Expand);
639 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
640 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
642 if (!TM.Options.UnsafeFPMath) {
643 setOperationAction(ISD::FSIN , MVT::f64 , Expand);
644 setOperationAction(ISD::FCOS , MVT::f64 , Expand);
646 addLegalFPImmediate(APFloat(+0.0)); // FLD0
647 addLegalFPImmediate(APFloat(+1.0)); // FLD1
648 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
649 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
650 addLegalFPImmediate(APFloat(+0.0f)); // FLD0
651 addLegalFPImmediate(APFloat(+1.0f)); // FLD1
652 addLegalFPImmediate(APFloat(-0.0f)); // FLD0/FCHS
653 addLegalFPImmediate(APFloat(-1.0f)); // FLD1/FCHS
656 // We don't support FMA.
657 setOperationAction(ISD::FMA, MVT::f64, Expand);
658 setOperationAction(ISD::FMA, MVT::f32, Expand);
660 // Long double always uses X87.
661 if (!TM.Options.UseSoftFloat) {
662 addRegisterClass(MVT::f80, X86::RFP80RegisterClass);
663 setOperationAction(ISD::UNDEF, MVT::f80, Expand);
664 setOperationAction(ISD::FCOPYSIGN, MVT::f80, Expand);
666 APFloat TmpFlt = APFloat::getZero(APFloat::x87DoubleExtended);
667 addLegalFPImmediate(TmpFlt); // FLD0
669 addLegalFPImmediate(TmpFlt); // FLD0/FCHS
672 APFloat TmpFlt2(+1.0);
673 TmpFlt2.convert(APFloat::x87DoubleExtended, APFloat::rmNearestTiesToEven,
675 addLegalFPImmediate(TmpFlt2); // FLD1
676 TmpFlt2.changeSign();
677 addLegalFPImmediate(TmpFlt2); // FLD1/FCHS
680 if (!TM.Options.UnsafeFPMath) {
681 setOperationAction(ISD::FSIN , MVT::f80 , Expand);
682 setOperationAction(ISD::FCOS , MVT::f80 , Expand);
685 setOperationAction(ISD::FFLOOR, MVT::f80, Expand);
686 setOperationAction(ISD::FCEIL, MVT::f80, Expand);
687 setOperationAction(ISD::FTRUNC, MVT::f80, Expand);
688 setOperationAction(ISD::FRINT, MVT::f80, Expand);
689 setOperationAction(ISD::FNEARBYINT, MVT::f80, Expand);
690 setOperationAction(ISD::FMA, MVT::f80, Expand);
693 // Always use a library call for pow.
694 setOperationAction(ISD::FPOW , MVT::f32 , Expand);
695 setOperationAction(ISD::FPOW , MVT::f64 , Expand);
696 setOperationAction(ISD::FPOW , MVT::f80 , Expand);
698 setOperationAction(ISD::FLOG, MVT::f80, Expand);
699 setOperationAction(ISD::FLOG2, MVT::f80, Expand);
700 setOperationAction(ISD::FLOG10, MVT::f80, Expand);
701 setOperationAction(ISD::FEXP, MVT::f80, Expand);
702 setOperationAction(ISD::FEXP2, MVT::f80, Expand);
704 // First set operation action for all vector types to either promote
705 // (for widening) or expand (for scalarization). Then we will selectively
706 // turn on ones that can be effectively codegen'd.
707 for (unsigned VT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
708 VT <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++VT) {
709 setOperationAction(ISD::ADD , (MVT::SimpleValueType)VT, Expand);
710 setOperationAction(ISD::SUB , (MVT::SimpleValueType)VT, Expand);
711 setOperationAction(ISD::FADD, (MVT::SimpleValueType)VT, Expand);
712 setOperationAction(ISD::FNEG, (MVT::SimpleValueType)VT, Expand);
713 setOperationAction(ISD::FSUB, (MVT::SimpleValueType)VT, Expand);
714 setOperationAction(ISD::MUL , (MVT::SimpleValueType)VT, Expand);
715 setOperationAction(ISD::FMUL, (MVT::SimpleValueType)VT, Expand);
716 setOperationAction(ISD::SDIV, (MVT::SimpleValueType)VT, Expand);
717 setOperationAction(ISD::UDIV, (MVT::SimpleValueType)VT, Expand);
718 setOperationAction(ISD::FDIV, (MVT::SimpleValueType)VT, Expand);
719 setOperationAction(ISD::SREM, (MVT::SimpleValueType)VT, Expand);
720 setOperationAction(ISD::UREM, (MVT::SimpleValueType)VT, Expand);
721 setOperationAction(ISD::LOAD, (MVT::SimpleValueType)VT, Expand);
722 setOperationAction(ISD::VECTOR_SHUFFLE, (MVT::SimpleValueType)VT, Expand);
723 setOperationAction(ISD::EXTRACT_VECTOR_ELT,(MVT::SimpleValueType)VT,Expand);
724 setOperationAction(ISD::INSERT_VECTOR_ELT,(MVT::SimpleValueType)VT, Expand);
725 setOperationAction(ISD::EXTRACT_SUBVECTOR,(MVT::SimpleValueType)VT,Expand);
726 setOperationAction(ISD::INSERT_SUBVECTOR,(MVT::SimpleValueType)VT,Expand);
727 setOperationAction(ISD::FABS, (MVT::SimpleValueType)VT, Expand);
728 setOperationAction(ISD::FSIN, (MVT::SimpleValueType)VT, Expand);
729 setOperationAction(ISD::FCOS, (MVT::SimpleValueType)VT, Expand);
730 setOperationAction(ISD::FREM, (MVT::SimpleValueType)VT, Expand);
731 setOperationAction(ISD::FPOWI, (MVT::SimpleValueType)VT, Expand);
732 setOperationAction(ISD::FSQRT, (MVT::SimpleValueType)VT, Expand);
733 setOperationAction(ISD::FCOPYSIGN, (MVT::SimpleValueType)VT, Expand);
734 setOperationAction(ISD::SMUL_LOHI, (MVT::SimpleValueType)VT, Expand);
735 setOperationAction(ISD::UMUL_LOHI, (MVT::SimpleValueType)VT, Expand);
736 setOperationAction(ISD::SDIVREM, (MVT::SimpleValueType)VT, Expand);
737 setOperationAction(ISD::UDIVREM, (MVT::SimpleValueType)VT, Expand);
738 setOperationAction(ISD::FPOW, (MVT::SimpleValueType)VT, Expand);
739 setOperationAction(ISD::CTPOP, (MVT::SimpleValueType)VT, Expand);
740 setOperationAction(ISD::CTTZ, (MVT::SimpleValueType)VT, Expand);
741 setOperationAction(ISD::CTTZ_ZERO_UNDEF, (MVT::SimpleValueType)VT, Expand);
742 setOperationAction(ISD::CTLZ, (MVT::SimpleValueType)VT, Expand);
743 setOperationAction(ISD::CTLZ_ZERO_UNDEF, (MVT::SimpleValueType)VT, Expand);
744 setOperationAction(ISD::SHL, (MVT::SimpleValueType)VT, Expand);
745 setOperationAction(ISD::SRA, (MVT::SimpleValueType)VT, Expand);
746 setOperationAction(ISD::SRL, (MVT::SimpleValueType)VT, Expand);
747 setOperationAction(ISD::ROTL, (MVT::SimpleValueType)VT, Expand);
748 setOperationAction(ISD::ROTR, (MVT::SimpleValueType)VT, Expand);
749 setOperationAction(ISD::BSWAP, (MVT::SimpleValueType)VT, Expand);
750 setOperationAction(ISD::SETCC, (MVT::SimpleValueType)VT, Expand);
751 setOperationAction(ISD::FLOG, (MVT::SimpleValueType)VT, Expand);
752 setOperationAction(ISD::FLOG2, (MVT::SimpleValueType)VT, Expand);
753 setOperationAction(ISD::FLOG10, (MVT::SimpleValueType)VT, Expand);
754 setOperationAction(ISD::FEXP, (MVT::SimpleValueType)VT, Expand);
755 setOperationAction(ISD::FEXP2, (MVT::SimpleValueType)VT, Expand);
756 setOperationAction(ISD::FP_TO_UINT, (MVT::SimpleValueType)VT, Expand);
757 setOperationAction(ISD::FP_TO_SINT, (MVT::SimpleValueType)VT, Expand);
758 setOperationAction(ISD::UINT_TO_FP, (MVT::SimpleValueType)VT, Expand);
759 setOperationAction(ISD::SINT_TO_FP, (MVT::SimpleValueType)VT, Expand);
760 setOperationAction(ISD::SIGN_EXTEND_INREG, (MVT::SimpleValueType)VT,Expand);
761 setOperationAction(ISD::TRUNCATE, (MVT::SimpleValueType)VT, Expand);
762 setOperationAction(ISD::SIGN_EXTEND, (MVT::SimpleValueType)VT, Expand);
763 setOperationAction(ISD::ZERO_EXTEND, (MVT::SimpleValueType)VT, Expand);
764 setOperationAction(ISD::ANY_EXTEND, (MVT::SimpleValueType)VT, Expand);
765 setOperationAction(ISD::VSELECT, (MVT::SimpleValueType)VT, Expand);
766 for (unsigned InnerVT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
767 InnerVT <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++InnerVT)
768 setTruncStoreAction((MVT::SimpleValueType)VT,
769 (MVT::SimpleValueType)InnerVT, Expand);
770 setLoadExtAction(ISD::SEXTLOAD, (MVT::SimpleValueType)VT, Expand);
771 setLoadExtAction(ISD::ZEXTLOAD, (MVT::SimpleValueType)VT, Expand);
772 setLoadExtAction(ISD::EXTLOAD, (MVT::SimpleValueType)VT, Expand);
775 // FIXME: In order to prevent SSE instructions being expanded to MMX ones
776 // with -msoft-float, disable use of MMX as well.
777 if (!TM.Options.UseSoftFloat && Subtarget->hasMMX()) {
778 addRegisterClass(MVT::x86mmx, X86::VR64RegisterClass);
779 // No operations on x86mmx supported, everything uses intrinsics.
782 // MMX-sized vectors (other than x86mmx) are expected to be expanded
783 // into smaller operations.
784 setOperationAction(ISD::MULHS, MVT::v8i8, Expand);
785 setOperationAction(ISD::MULHS, MVT::v4i16, Expand);
786 setOperationAction(ISD::MULHS, MVT::v2i32, Expand);
787 setOperationAction(ISD::MULHS, MVT::v1i64, Expand);
788 setOperationAction(ISD::AND, MVT::v8i8, Expand);
789 setOperationAction(ISD::AND, MVT::v4i16, Expand);
790 setOperationAction(ISD::AND, MVT::v2i32, Expand);
791 setOperationAction(ISD::AND, MVT::v1i64, Expand);
792 setOperationAction(ISD::OR, MVT::v8i8, Expand);
793 setOperationAction(ISD::OR, MVT::v4i16, Expand);
794 setOperationAction(ISD::OR, MVT::v2i32, Expand);
795 setOperationAction(ISD::OR, MVT::v1i64, Expand);
796 setOperationAction(ISD::XOR, MVT::v8i8, Expand);
797 setOperationAction(ISD::XOR, MVT::v4i16, Expand);
798 setOperationAction(ISD::XOR, MVT::v2i32, Expand);
799 setOperationAction(ISD::XOR, MVT::v1i64, Expand);
800 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i8, Expand);
801 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i16, Expand);
802 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2i32, Expand);
803 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v1i64, Expand);
804 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v1i64, Expand);
805 setOperationAction(ISD::SELECT, MVT::v8i8, Expand);
806 setOperationAction(ISD::SELECT, MVT::v4i16, Expand);
807 setOperationAction(ISD::SELECT, MVT::v2i32, Expand);
808 setOperationAction(ISD::SELECT, MVT::v1i64, Expand);
809 setOperationAction(ISD::BITCAST, MVT::v8i8, Expand);
810 setOperationAction(ISD::BITCAST, MVT::v4i16, Expand);
811 setOperationAction(ISD::BITCAST, MVT::v2i32, Expand);
812 setOperationAction(ISD::BITCAST, MVT::v1i64, Expand);
814 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE1()) {
815 addRegisterClass(MVT::v4f32, X86::VR128RegisterClass);
817 setOperationAction(ISD::FADD, MVT::v4f32, Legal);
818 setOperationAction(ISD::FSUB, MVT::v4f32, Legal);
819 setOperationAction(ISD::FMUL, MVT::v4f32, Legal);
820 setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
821 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal);
822 setOperationAction(ISD::FNEG, MVT::v4f32, Custom);
823 setOperationAction(ISD::LOAD, MVT::v4f32, Legal);
824 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
825 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f32, Custom);
826 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
827 setOperationAction(ISD::SELECT, MVT::v4f32, Custom);
828 setOperationAction(ISD::SETCC, MVT::v4f32, Custom);
831 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE2()) {
832 addRegisterClass(MVT::v2f64, X86::VR128RegisterClass);
834 // FIXME: Unfortunately -soft-float and -no-implicit-float means XMM
835 // registers cannot be used even for integer operations.
836 addRegisterClass(MVT::v16i8, X86::VR128RegisterClass);
837 addRegisterClass(MVT::v8i16, X86::VR128RegisterClass);
838 addRegisterClass(MVT::v4i32, X86::VR128RegisterClass);
839 addRegisterClass(MVT::v2i64, X86::VR128RegisterClass);
841 setOperationAction(ISD::ADD, MVT::v16i8, Legal);
842 setOperationAction(ISD::ADD, MVT::v8i16, Legal);
843 setOperationAction(ISD::ADD, MVT::v4i32, Legal);
844 setOperationAction(ISD::ADD, MVT::v2i64, Legal);
845 setOperationAction(ISD::MUL, MVT::v2i64, Custom);
846 setOperationAction(ISD::SUB, MVT::v16i8, Legal);
847 setOperationAction(ISD::SUB, MVT::v8i16, Legal);
848 setOperationAction(ISD::SUB, MVT::v4i32, Legal);
849 setOperationAction(ISD::SUB, MVT::v2i64, Legal);
850 setOperationAction(ISD::MUL, MVT::v8i16, Legal);
851 setOperationAction(ISD::FADD, MVT::v2f64, Legal);
852 setOperationAction(ISD::FSUB, MVT::v2f64, Legal);
853 setOperationAction(ISD::FMUL, MVT::v2f64, Legal);
854 setOperationAction(ISD::FDIV, MVT::v2f64, Legal);
855 setOperationAction(ISD::FSQRT, MVT::v2f64, Legal);
856 setOperationAction(ISD::FNEG, MVT::v2f64, Custom);
858 setOperationAction(ISD::SETCC, MVT::v2i64, Custom);
859 setOperationAction(ISD::SETCC, MVT::v16i8, Custom);
860 setOperationAction(ISD::SETCC, MVT::v8i16, Custom);
861 setOperationAction(ISD::SETCC, MVT::v4i32, Custom);
863 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Custom);
864 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Custom);
865 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
866 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
867 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
869 setOperationAction(ISD::CONCAT_VECTORS, MVT::v2f64, Custom);
870 setOperationAction(ISD::CONCAT_VECTORS, MVT::v2i64, Custom);
871 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i8, Custom);
872 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i16, Custom);
873 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4i32, Custom);
875 // Custom lower build_vector, vector_shuffle, and extract_vector_elt.
876 for (unsigned i = (unsigned)MVT::v16i8; i != (unsigned)MVT::v2i64; ++i) {
877 EVT VT = (MVT::SimpleValueType)i;
878 // Do not attempt to custom lower non-power-of-2 vectors
879 if (!isPowerOf2_32(VT.getVectorNumElements()))
881 // Do not attempt to custom lower non-128-bit vectors
882 if (!VT.is128BitVector())
884 setOperationAction(ISD::BUILD_VECTOR,
885 VT.getSimpleVT().SimpleTy, Custom);
886 setOperationAction(ISD::VECTOR_SHUFFLE,
887 VT.getSimpleVT().SimpleTy, Custom);
888 setOperationAction(ISD::EXTRACT_VECTOR_ELT,
889 VT.getSimpleVT().SimpleTy, Custom);
892 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f64, Custom);
893 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i64, Custom);
894 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Custom);
895 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Custom);
896 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f64, Custom);
897 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Custom);
899 if (Subtarget->is64Bit()) {
900 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
901 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
904 // Promote v16i8, v8i16, v4i32 load, select, and, or, xor to v2i64.
905 for (unsigned i = (unsigned)MVT::v16i8; i != (unsigned)MVT::v2i64; i++) {
906 MVT::SimpleValueType SVT = (MVT::SimpleValueType)i;
909 // Do not attempt to promote non-128-bit vectors
910 if (!VT.is128BitVector())
913 setOperationAction(ISD::AND, SVT, Promote);
914 AddPromotedToType (ISD::AND, SVT, MVT::v2i64);
915 setOperationAction(ISD::OR, SVT, Promote);
916 AddPromotedToType (ISD::OR, SVT, MVT::v2i64);
917 setOperationAction(ISD::XOR, SVT, Promote);
918 AddPromotedToType (ISD::XOR, SVT, MVT::v2i64);
919 setOperationAction(ISD::LOAD, SVT, Promote);
920 AddPromotedToType (ISD::LOAD, SVT, MVT::v2i64);
921 setOperationAction(ISD::SELECT, SVT, Promote);
922 AddPromotedToType (ISD::SELECT, SVT, MVT::v2i64);
925 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
927 // Custom lower v2i64 and v2f64 selects.
928 setOperationAction(ISD::LOAD, MVT::v2f64, Legal);
929 setOperationAction(ISD::LOAD, MVT::v2i64, Legal);
930 setOperationAction(ISD::SELECT, MVT::v2f64, Custom);
931 setOperationAction(ISD::SELECT, MVT::v2i64, Custom);
933 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal);
934 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal);
937 if (Subtarget->hasSSE41()) {
938 setOperationAction(ISD::FFLOOR, MVT::f32, Legal);
939 setOperationAction(ISD::FCEIL, MVT::f32, Legal);
940 setOperationAction(ISD::FTRUNC, MVT::f32, Legal);
941 setOperationAction(ISD::FRINT, MVT::f32, Legal);
942 setOperationAction(ISD::FNEARBYINT, MVT::f32, Legal);
943 setOperationAction(ISD::FFLOOR, MVT::f64, Legal);
944 setOperationAction(ISD::FCEIL, MVT::f64, Legal);
945 setOperationAction(ISD::FTRUNC, MVT::f64, Legal);
946 setOperationAction(ISD::FRINT, MVT::f64, Legal);
947 setOperationAction(ISD::FNEARBYINT, MVT::f64, Legal);
949 // FIXME: Do we need to handle scalar-to-vector here?
950 setOperationAction(ISD::MUL, MVT::v4i32, Legal);
952 setOperationAction(ISD::VSELECT, MVT::v2f64, Legal);
953 setOperationAction(ISD::VSELECT, MVT::v2i64, Legal);
954 setOperationAction(ISD::VSELECT, MVT::v16i8, Legal);
955 setOperationAction(ISD::VSELECT, MVT::v4i32, Legal);
956 setOperationAction(ISD::VSELECT, MVT::v4f32, Legal);
958 // i8 and i16 vectors are custom , because the source register and source
959 // source memory operand types are not the same width. f32 vectors are
960 // custom since the immediate controlling the insert encodes additional
962 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i8, Custom);
963 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
964 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
965 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
967 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i8, Custom);
968 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i16, Custom);
969 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i32, Custom);
970 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
972 // FIXME: these should be Legal but thats only for the case where
973 // the index is constant. For now custom expand to deal with that.
974 if (Subtarget->is64Bit()) {
975 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
976 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
980 if (Subtarget->hasSSE2()) {
981 setOperationAction(ISD::SRL, MVT::v8i16, Custom);
982 setOperationAction(ISD::SRL, MVT::v16i8, Custom);
984 setOperationAction(ISD::SHL, MVT::v8i16, Custom);
985 setOperationAction(ISD::SHL, MVT::v16i8, Custom);
987 setOperationAction(ISD::SRA, MVT::v8i16, Custom);
988 setOperationAction(ISD::SRA, MVT::v16i8, Custom);
990 if (Subtarget->hasAVX2()) {
991 setOperationAction(ISD::SRL, MVT::v2i64, Legal);
992 setOperationAction(ISD::SRL, MVT::v4i32, Legal);
994 setOperationAction(ISD::SHL, MVT::v2i64, Legal);
995 setOperationAction(ISD::SHL, MVT::v4i32, Legal);
997 setOperationAction(ISD::SRA, MVT::v4i32, Legal);
999 setOperationAction(ISD::SRL, MVT::v2i64, Custom);
1000 setOperationAction(ISD::SRL, MVT::v4i32, Custom);
1002 setOperationAction(ISD::SHL, MVT::v2i64, Custom);
1003 setOperationAction(ISD::SHL, MVT::v4i32, Custom);
1005 setOperationAction(ISD::SRA, MVT::v4i32, Custom);
1009 if (Subtarget->hasSSE42())
1010 setOperationAction(ISD::SETCC, MVT::v2i64, Custom);
1012 if (!TM.Options.UseSoftFloat && Subtarget->hasAVX()) {
1013 addRegisterClass(MVT::v32i8, X86::VR256RegisterClass);
1014 addRegisterClass(MVT::v16i16, X86::VR256RegisterClass);
1015 addRegisterClass(MVT::v8i32, X86::VR256RegisterClass);
1016 addRegisterClass(MVT::v8f32, X86::VR256RegisterClass);
1017 addRegisterClass(MVT::v4i64, X86::VR256RegisterClass);
1018 addRegisterClass(MVT::v4f64, X86::VR256RegisterClass);
1020 setOperationAction(ISD::LOAD, MVT::v8f32, Legal);
1021 setOperationAction(ISD::LOAD, MVT::v4f64, Legal);
1022 setOperationAction(ISD::LOAD, MVT::v4i64, Legal);
1024 setOperationAction(ISD::FADD, MVT::v8f32, Legal);
1025 setOperationAction(ISD::FSUB, MVT::v8f32, Legal);
1026 setOperationAction(ISD::FMUL, MVT::v8f32, Legal);
1027 setOperationAction(ISD::FDIV, MVT::v8f32, Legal);
1028 setOperationAction(ISD::FSQRT, MVT::v8f32, Legal);
1029 setOperationAction(ISD::FNEG, MVT::v8f32, Custom);
1031 setOperationAction(ISD::FADD, MVT::v4f64, Legal);
1032 setOperationAction(ISD::FSUB, MVT::v4f64, Legal);
1033 setOperationAction(ISD::FMUL, MVT::v4f64, Legal);
1034 setOperationAction(ISD::FDIV, MVT::v4f64, Legal);
1035 setOperationAction(ISD::FSQRT, MVT::v4f64, Legal);
1036 setOperationAction(ISD::FNEG, MVT::v4f64, Custom);
1038 setOperationAction(ISD::FP_TO_SINT, MVT::v8i32, Legal);
1039 setOperationAction(ISD::SINT_TO_FP, MVT::v8i32, Legal);
1040 setOperationAction(ISD::FP_ROUND, MVT::v4f32, Legal);
1042 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4f64, Custom);
1043 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4i64, Custom);
1044 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8f32, Custom);
1045 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i32, Custom);
1046 setOperationAction(ISD::CONCAT_VECTORS, MVT::v32i8, Custom);
1047 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i16, Custom);
1049 setOperationAction(ISD::SRL, MVT::v16i16, Custom);
1050 setOperationAction(ISD::SRL, MVT::v32i8, Custom);
1052 setOperationAction(ISD::SHL, MVT::v16i16, Custom);
1053 setOperationAction(ISD::SHL, MVT::v32i8, Custom);
1055 setOperationAction(ISD::SRA, MVT::v16i16, Custom);
1056 setOperationAction(ISD::SRA, MVT::v32i8, Custom);
1058 setOperationAction(ISD::SETCC, MVT::v32i8, Custom);
1059 setOperationAction(ISD::SETCC, MVT::v16i16, Custom);
1060 setOperationAction(ISD::SETCC, MVT::v8i32, Custom);
1061 setOperationAction(ISD::SETCC, MVT::v4i64, Custom);
1063 setOperationAction(ISD::SELECT, MVT::v4f64, Custom);
1064 setOperationAction(ISD::SELECT, MVT::v4i64, Custom);
1065 setOperationAction(ISD::SELECT, MVT::v8f32, Custom);
1067 setOperationAction(ISD::VSELECT, MVT::v4f64, Legal);
1068 setOperationAction(ISD::VSELECT, MVT::v4i64, Legal);
1069 setOperationAction(ISD::VSELECT, MVT::v8i32, Legal);
1070 setOperationAction(ISD::VSELECT, MVT::v8f32, Legal);
1072 if (Subtarget->hasAVX2()) {
1073 setOperationAction(ISD::ADD, MVT::v4i64, Legal);
1074 setOperationAction(ISD::ADD, MVT::v8i32, Legal);
1075 setOperationAction(ISD::ADD, MVT::v16i16, Legal);
1076 setOperationAction(ISD::ADD, MVT::v32i8, Legal);
1078 setOperationAction(ISD::SUB, MVT::v4i64, Legal);
1079 setOperationAction(ISD::SUB, MVT::v8i32, Legal);
1080 setOperationAction(ISD::SUB, MVT::v16i16, Legal);
1081 setOperationAction(ISD::SUB, MVT::v32i8, Legal);
1083 setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1084 setOperationAction(ISD::MUL, MVT::v8i32, Legal);
1085 setOperationAction(ISD::MUL, MVT::v16i16, Legal);
1086 // Don't lower v32i8 because there is no 128-bit byte mul
1088 setOperationAction(ISD::VSELECT, MVT::v32i8, Legal);
1090 setOperationAction(ISD::SRL, MVT::v4i64, Legal);
1091 setOperationAction(ISD::SRL, MVT::v8i32, Legal);
1093 setOperationAction(ISD::SHL, MVT::v4i64, Legal);
1094 setOperationAction(ISD::SHL, MVT::v8i32, Legal);
1096 setOperationAction(ISD::SRA, MVT::v8i32, Legal);
1098 setOperationAction(ISD::ADD, MVT::v4i64, Custom);
1099 setOperationAction(ISD::ADD, MVT::v8i32, Custom);
1100 setOperationAction(ISD::ADD, MVT::v16i16, Custom);
1101 setOperationAction(ISD::ADD, MVT::v32i8, Custom);
1103 setOperationAction(ISD::SUB, MVT::v4i64, Custom);
1104 setOperationAction(ISD::SUB, MVT::v8i32, Custom);
1105 setOperationAction(ISD::SUB, MVT::v16i16, Custom);
1106 setOperationAction(ISD::SUB, MVT::v32i8, Custom);
1108 setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1109 setOperationAction(ISD::MUL, MVT::v8i32, Custom);
1110 setOperationAction(ISD::MUL, MVT::v16i16, Custom);
1111 // Don't lower v32i8 because there is no 128-bit byte mul
1113 setOperationAction(ISD::SRL, MVT::v4i64, Custom);
1114 setOperationAction(ISD::SRL, MVT::v8i32, Custom);
1116 setOperationAction(ISD::SHL, MVT::v4i64, Custom);
1117 setOperationAction(ISD::SHL, MVT::v8i32, Custom);
1119 setOperationAction(ISD::SRA, MVT::v8i32, Custom);
1122 // Custom lower several nodes for 256-bit types.
1123 for (unsigned i = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
1124 i <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++i) {
1125 MVT::SimpleValueType SVT = (MVT::SimpleValueType)i;
1128 // Extract subvector is special because the value type
1129 // (result) is 128-bit but the source is 256-bit wide.
1130 if (VT.is128BitVector())
1131 setOperationAction(ISD::EXTRACT_SUBVECTOR, SVT, Custom);
1133 // Do not attempt to custom lower other non-256-bit vectors
1134 if (!VT.is256BitVector())
1137 setOperationAction(ISD::BUILD_VECTOR, SVT, Custom);
1138 setOperationAction(ISD::VECTOR_SHUFFLE, SVT, Custom);
1139 setOperationAction(ISD::INSERT_VECTOR_ELT, SVT, Custom);
1140 setOperationAction(ISD::EXTRACT_VECTOR_ELT, SVT, Custom);
1141 setOperationAction(ISD::SCALAR_TO_VECTOR, SVT, Custom);
1142 setOperationAction(ISD::INSERT_SUBVECTOR, SVT, Custom);
1145 // Promote v32i8, v16i16, v8i32 select, and, or, xor to v4i64.
1146 for (unsigned i = (unsigned)MVT::v32i8; i != (unsigned)MVT::v4i64; ++i) {
1147 MVT::SimpleValueType SVT = (MVT::SimpleValueType)i;
1150 // Do not attempt to promote non-256-bit vectors
1151 if (!VT.is256BitVector())
1154 setOperationAction(ISD::AND, SVT, Promote);
1155 AddPromotedToType (ISD::AND, SVT, MVT::v4i64);
1156 setOperationAction(ISD::OR, SVT, Promote);
1157 AddPromotedToType (ISD::OR, SVT, MVT::v4i64);
1158 setOperationAction(ISD::XOR, SVT, Promote);
1159 AddPromotedToType (ISD::XOR, SVT, MVT::v4i64);
1160 setOperationAction(ISD::LOAD, SVT, Promote);
1161 AddPromotedToType (ISD::LOAD, SVT, MVT::v4i64);
1162 setOperationAction(ISD::SELECT, SVT, Promote);
1163 AddPromotedToType (ISD::SELECT, SVT, MVT::v4i64);
1167 // SIGN_EXTEND_INREGs are evaluated by the extend type. Handle the expansion
1168 // of this type with custom code.
1169 for (unsigned VT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
1170 VT != (unsigned)MVT::LAST_VECTOR_VALUETYPE; VT++) {
1171 setOperationAction(ISD::SIGN_EXTEND_INREG, (MVT::SimpleValueType)VT,
1175 // We want to custom lower some of our intrinsics.
1176 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
1179 // Only custom-lower 64-bit SADDO and friends on 64-bit because we don't
1180 // handle type legalization for these operations here.
1182 // FIXME: We really should do custom legalization for addition and
1183 // subtraction on x86-32 once PR3203 is fixed. We really can't do much better
1184 // than generic legalization for 64-bit multiplication-with-overflow, though.
1185 for (unsigned i = 0, e = 3+Subtarget->is64Bit(); i != e; ++i) {
1186 // Add/Sub/Mul with overflow operations are custom lowered.
1188 setOperationAction(ISD::SADDO, VT, Custom);
1189 setOperationAction(ISD::UADDO, VT, Custom);
1190 setOperationAction(ISD::SSUBO, VT, Custom);
1191 setOperationAction(ISD::USUBO, VT, Custom);
1192 setOperationAction(ISD::SMULO, VT, Custom);
1193 setOperationAction(ISD::UMULO, VT, Custom);
1196 // There are no 8-bit 3-address imul/mul instructions
1197 setOperationAction(ISD::SMULO, MVT::i8, Expand);
1198 setOperationAction(ISD::UMULO, MVT::i8, Expand);
1200 if (!Subtarget->is64Bit()) {
1201 // These libcalls are not available in 32-bit.
1202 setLibcallName(RTLIB::SHL_I128, 0);
1203 setLibcallName(RTLIB::SRL_I128, 0);
1204 setLibcallName(RTLIB::SRA_I128, 0);
1207 // We have target-specific dag combine patterns for the following nodes:
1208 setTargetDAGCombine(ISD::VECTOR_SHUFFLE);
1209 setTargetDAGCombine(ISD::EXTRACT_VECTOR_ELT);
1210 setTargetDAGCombine(ISD::VSELECT);
1211 setTargetDAGCombine(ISD::SELECT);
1212 setTargetDAGCombine(ISD::SHL);
1213 setTargetDAGCombine(ISD::SRA);
1214 setTargetDAGCombine(ISD::SRL);
1215 setTargetDAGCombine(ISD::OR);
1216 setTargetDAGCombine(ISD::AND);
1217 setTargetDAGCombine(ISD::ADD);
1218 setTargetDAGCombine(ISD::FADD);
1219 setTargetDAGCombine(ISD::FSUB);
1220 setTargetDAGCombine(ISD::SUB);
1221 setTargetDAGCombine(ISD::LOAD);
1222 setTargetDAGCombine(ISD::STORE);
1223 setTargetDAGCombine(ISD::ZERO_EXTEND);
1224 setTargetDAGCombine(ISD::SIGN_EXTEND);
1225 setTargetDAGCombine(ISD::TRUNCATE);
1226 setTargetDAGCombine(ISD::SINT_TO_FP);
1227 if (Subtarget->is64Bit())
1228 setTargetDAGCombine(ISD::MUL);
1229 if (Subtarget->hasBMI())
1230 setTargetDAGCombine(ISD::XOR);
1232 computeRegisterProperties();
1234 // On Darwin, -Os means optimize for size without hurting performance,
1235 // do not reduce the limit.
1236 maxStoresPerMemset = 16; // For @llvm.memset -> sequence of stores
1237 maxStoresPerMemsetOptSize = Subtarget->isTargetDarwin() ? 16 : 8;
1238 maxStoresPerMemcpy = 8; // For @llvm.memcpy -> sequence of stores
1239 maxStoresPerMemcpyOptSize = Subtarget->isTargetDarwin() ? 8 : 4;
1240 maxStoresPerMemmove = 8; // For @llvm.memmove -> sequence of stores
1241 maxStoresPerMemmoveOptSize = Subtarget->isTargetDarwin() ? 8 : 4;
1242 setPrefLoopAlignment(4); // 2^4 bytes.
1243 benefitFromCodePlacementOpt = true;
1245 setPrefFunctionAlignment(4); // 2^4 bytes.
1249 EVT X86TargetLowering::getSetCCResultType(EVT VT) const {
1250 if (!VT.isVector()) return MVT::i8;
1251 return VT.changeVectorElementTypeToInteger();
1255 /// getMaxByValAlign - Helper for getByValTypeAlignment to determine
1256 /// the desired ByVal argument alignment.
1257 static void getMaxByValAlign(Type *Ty, unsigned &MaxAlign) {
1260 if (VectorType *VTy = dyn_cast<VectorType>(Ty)) {
1261 if (VTy->getBitWidth() == 128)
1263 } else if (ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
1264 unsigned EltAlign = 0;
1265 getMaxByValAlign(ATy->getElementType(), EltAlign);
1266 if (EltAlign > MaxAlign)
1267 MaxAlign = EltAlign;
1268 } else if (StructType *STy = dyn_cast<StructType>(Ty)) {
1269 for (unsigned i = 0, e = STy->getNumElements(); i != e; ++i) {
1270 unsigned EltAlign = 0;
1271 getMaxByValAlign(STy->getElementType(i), EltAlign);
1272 if (EltAlign > MaxAlign)
1273 MaxAlign = EltAlign;
1281 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
1282 /// function arguments in the caller parameter area. For X86, aggregates
1283 /// that contain SSE vectors are placed at 16-byte boundaries while the rest
1284 /// are at 4-byte boundaries.
1285 unsigned X86TargetLowering::getByValTypeAlignment(Type *Ty) const {
1286 if (Subtarget->is64Bit()) {
1287 // Max of 8 and alignment of type.
1288 unsigned TyAlign = TD->getABITypeAlignment(Ty);
1295 if (Subtarget->hasSSE1())
1296 getMaxByValAlign(Ty, Align);
1300 /// getOptimalMemOpType - Returns the target specific optimal type for load
1301 /// and store operations as a result of memset, memcpy, and memmove
1302 /// lowering. If DstAlign is zero that means it's safe to destination
1303 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
1304 /// means there isn't a need to check it against alignment requirement,
1305 /// probably because the source does not need to be loaded. If
1306 /// 'IsZeroVal' is true, that means it's safe to return a
1307 /// non-scalar-integer type, e.g. empty string source, constant, or loaded
1308 /// from memory. 'MemcpyStrSrc' indicates whether the memcpy source is
1309 /// constant so it does not need to be loaded.
1310 /// It returns EVT::Other if the type should be determined using generic
1311 /// target-independent logic.
1313 X86TargetLowering::getOptimalMemOpType(uint64_t Size,
1314 unsigned DstAlign, unsigned SrcAlign,
1317 MachineFunction &MF) const {
1318 // FIXME: This turns off use of xmm stores for memset/memcpy on targets like
1319 // linux. This is because the stack realignment code can't handle certain
1320 // cases like PR2962. This should be removed when PR2962 is fixed.
1321 const Function *F = MF.getFunction();
1323 !F->hasFnAttr(Attribute::NoImplicitFloat)) {
1325 (Subtarget->isUnalignedMemAccessFast() ||
1326 ((DstAlign == 0 || DstAlign >= 16) &&
1327 (SrcAlign == 0 || SrcAlign >= 16))) &&
1328 Subtarget->getStackAlignment() >= 16) {
1329 if (Subtarget->getStackAlignment() >= 32) {
1330 if (Subtarget->hasAVX2())
1332 if (Subtarget->hasAVX())
1335 if (Subtarget->hasSSE2())
1337 if (Subtarget->hasSSE1())
1339 } else if (!MemcpyStrSrc && Size >= 8 &&
1340 !Subtarget->is64Bit() &&
1341 Subtarget->getStackAlignment() >= 8 &&
1342 Subtarget->hasSSE2()) {
1343 // Do not use f64 to lower memcpy if source is string constant. It's
1344 // better to use i32 to avoid the loads.
1348 if (Subtarget->is64Bit() && Size >= 8)
1353 /// getJumpTableEncoding - Return the entry encoding for a jump table in the
1354 /// current function. The returned value is a member of the
1355 /// MachineJumpTableInfo::JTEntryKind enum.
1356 unsigned X86TargetLowering::getJumpTableEncoding() const {
1357 // In GOT pic mode, each entry in the jump table is emitted as a @GOTOFF
1359 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1360 Subtarget->isPICStyleGOT())
1361 return MachineJumpTableInfo::EK_Custom32;
1363 // Otherwise, use the normal jump table encoding heuristics.
1364 return TargetLowering::getJumpTableEncoding();
1368 X86TargetLowering::LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI,
1369 const MachineBasicBlock *MBB,
1370 unsigned uid,MCContext &Ctx) const{
1371 assert(getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1372 Subtarget->isPICStyleGOT());
1373 // In 32-bit ELF systems, our jump table entries are formed with @GOTOFF
1375 return MCSymbolRefExpr::Create(MBB->getSymbol(),
1376 MCSymbolRefExpr::VK_GOTOFF, Ctx);
1379 /// getPICJumpTableRelocaBase - Returns relocation base for the given PIC
1381 SDValue X86TargetLowering::getPICJumpTableRelocBase(SDValue Table,
1382 SelectionDAG &DAG) const {
1383 if (!Subtarget->is64Bit())
1384 // This doesn't have DebugLoc associated with it, but is not really the
1385 // same as a Register.
1386 return DAG.getNode(X86ISD::GlobalBaseReg, DebugLoc(), getPointerTy());
1390 /// getPICJumpTableRelocBaseExpr - This returns the relocation base for the
1391 /// given PIC jumptable, the same as getPICJumpTableRelocBase, but as an
1393 const MCExpr *X86TargetLowering::
1394 getPICJumpTableRelocBaseExpr(const MachineFunction *MF, unsigned JTI,
1395 MCContext &Ctx) const {
1396 // X86-64 uses RIP relative addressing based on the jump table label.
1397 if (Subtarget->isPICStyleRIPRel())
1398 return TargetLowering::getPICJumpTableRelocBaseExpr(MF, JTI, Ctx);
1400 // Otherwise, the reference is relative to the PIC base.
1401 return MCSymbolRefExpr::Create(MF->getPICBaseSymbol(), Ctx);
1404 // FIXME: Why this routine is here? Move to RegInfo!
1405 std::pair<const TargetRegisterClass*, uint8_t>
1406 X86TargetLowering::findRepresentativeClass(EVT VT) const{
1407 const TargetRegisterClass *RRC = 0;
1409 switch (VT.getSimpleVT().SimpleTy) {
1411 return TargetLowering::findRepresentativeClass(VT);
1412 case MVT::i8: case MVT::i16: case MVT::i32: case MVT::i64:
1413 RRC = (Subtarget->is64Bit()
1414 ? X86::GR64RegisterClass : X86::GR32RegisterClass);
1417 RRC = X86::VR64RegisterClass;
1419 case MVT::f32: case MVT::f64:
1420 case MVT::v16i8: case MVT::v8i16: case MVT::v4i32: case MVT::v2i64:
1421 case MVT::v4f32: case MVT::v2f64:
1422 case MVT::v32i8: case MVT::v8i32: case MVT::v4i64: case MVT::v8f32:
1424 RRC = X86::VR128RegisterClass;
1427 return std::make_pair(RRC, Cost);
1430 bool X86TargetLowering::getStackCookieLocation(unsigned &AddressSpace,
1431 unsigned &Offset) const {
1432 if (!Subtarget->isTargetLinux())
1435 if (Subtarget->is64Bit()) {
1436 // %fs:0x28, unless we're using a Kernel code model, in which case it's %gs:
1438 if (getTargetMachine().getCodeModel() == CodeModel::Kernel)
1451 //===----------------------------------------------------------------------===//
1452 // Return Value Calling Convention Implementation
1453 //===----------------------------------------------------------------------===//
1455 #include "X86GenCallingConv.inc"
1458 X86TargetLowering::CanLowerReturn(CallingConv::ID CallConv,
1459 MachineFunction &MF, bool isVarArg,
1460 const SmallVectorImpl<ISD::OutputArg> &Outs,
1461 LLVMContext &Context) const {
1462 SmallVector<CCValAssign, 16> RVLocs;
1463 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(),
1465 return CCInfo.CheckReturn(Outs, RetCC_X86);
1469 X86TargetLowering::LowerReturn(SDValue Chain,
1470 CallingConv::ID CallConv, bool isVarArg,
1471 const SmallVectorImpl<ISD::OutputArg> &Outs,
1472 const SmallVectorImpl<SDValue> &OutVals,
1473 DebugLoc dl, SelectionDAG &DAG) const {
1474 MachineFunction &MF = DAG.getMachineFunction();
1475 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1477 SmallVector<CCValAssign, 16> RVLocs;
1478 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(),
1479 RVLocs, *DAG.getContext());
1480 CCInfo.AnalyzeReturn(Outs, RetCC_X86);
1482 // Add the regs to the liveout set for the function.
1483 MachineRegisterInfo &MRI = DAG.getMachineFunction().getRegInfo();
1484 for (unsigned i = 0; i != RVLocs.size(); ++i)
1485 if (RVLocs[i].isRegLoc() && !MRI.isLiveOut(RVLocs[i].getLocReg()))
1486 MRI.addLiveOut(RVLocs[i].getLocReg());
1490 SmallVector<SDValue, 6> RetOps;
1491 RetOps.push_back(Chain); // Operand #0 = Chain (updated below)
1492 // Operand #1 = Bytes To Pop
1493 RetOps.push_back(DAG.getTargetConstant(FuncInfo->getBytesToPopOnReturn(),
1496 // Copy the result values into the output registers.
1497 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1498 CCValAssign &VA = RVLocs[i];
1499 assert(VA.isRegLoc() && "Can only return in registers!");
1500 SDValue ValToCopy = OutVals[i];
1501 EVT ValVT = ValToCopy.getValueType();
1503 // If this is x86-64, and we disabled SSE, we can't return FP values,
1504 // or SSE or MMX vectors.
1505 if ((ValVT == MVT::f32 || ValVT == MVT::f64 ||
1506 VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) &&
1507 (Subtarget->is64Bit() && !Subtarget->hasSSE1())) {
1508 report_fatal_error("SSE register return with SSE disabled");
1510 // Likewise we can't return F64 values with SSE1 only. gcc does so, but
1511 // llvm-gcc has never done it right and no one has noticed, so this
1512 // should be OK for now.
1513 if (ValVT == MVT::f64 &&
1514 (Subtarget->is64Bit() && !Subtarget->hasSSE2()))
1515 report_fatal_error("SSE2 register return with SSE2 disabled");
1517 // Returns in ST0/ST1 are handled specially: these are pushed as operands to
1518 // the RET instruction and handled by the FP Stackifier.
1519 if (VA.getLocReg() == X86::ST0 ||
1520 VA.getLocReg() == X86::ST1) {
1521 // If this is a copy from an xmm register to ST(0), use an FPExtend to
1522 // change the value to the FP stack register class.
1523 if (isScalarFPTypeInSSEReg(VA.getValVT()))
1524 ValToCopy = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f80, ValToCopy);
1525 RetOps.push_back(ValToCopy);
1526 // Don't emit a copytoreg.
1530 // 64-bit vector (MMX) values are returned in XMM0 / XMM1 except for v1i64
1531 // which is returned in RAX / RDX.
1532 if (Subtarget->is64Bit()) {
1533 if (ValVT == MVT::x86mmx) {
1534 if (VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) {
1535 ValToCopy = DAG.getNode(ISD::BITCAST, dl, MVT::i64, ValToCopy);
1536 ValToCopy = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
1538 // If we don't have SSE2 available, convert to v4f32 so the generated
1539 // register is legal.
1540 if (!Subtarget->hasSSE2())
1541 ValToCopy = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32,ValToCopy);
1546 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), ValToCopy, Flag);
1547 Flag = Chain.getValue(1);
1550 // The x86-64 ABI for returning structs by value requires that we copy
1551 // the sret argument into %rax for the return. We saved the argument into
1552 // a virtual register in the entry block, so now we copy the value out
1554 if (Subtarget->is64Bit() &&
1555 DAG.getMachineFunction().getFunction()->hasStructRetAttr()) {
1556 MachineFunction &MF = DAG.getMachineFunction();
1557 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1558 unsigned Reg = FuncInfo->getSRetReturnReg();
1560 "SRetReturnReg should have been set in LowerFormalArguments().");
1561 SDValue Val = DAG.getCopyFromReg(Chain, dl, Reg, getPointerTy());
1563 Chain = DAG.getCopyToReg(Chain, dl, X86::RAX, Val, Flag);
1564 Flag = Chain.getValue(1);
1566 // RAX now acts like a return value.
1567 MRI.addLiveOut(X86::RAX);
1570 RetOps[0] = Chain; // Update chain.
1572 // Add the flag if we have it.
1574 RetOps.push_back(Flag);
1576 return DAG.getNode(X86ISD::RET_FLAG, dl,
1577 MVT::Other, &RetOps[0], RetOps.size());
1580 bool X86TargetLowering::isUsedByReturnOnly(SDNode *N) const {
1581 if (N->getNumValues() != 1)
1583 if (!N->hasNUsesOfValue(1, 0))
1586 SDNode *Copy = *N->use_begin();
1587 if (Copy->getOpcode() != ISD::CopyToReg &&
1588 Copy->getOpcode() != ISD::FP_EXTEND)
1591 bool HasRet = false;
1592 for (SDNode::use_iterator UI = Copy->use_begin(), UE = Copy->use_end();
1594 if (UI->getOpcode() != X86ISD::RET_FLAG)
1603 X86TargetLowering::getTypeForExtArgOrReturn(LLVMContext &Context, EVT VT,
1604 ISD::NodeType ExtendKind) const {
1606 // TODO: Is this also valid on 32-bit?
1607 if (Subtarget->is64Bit() && VT == MVT::i1 && ExtendKind == ISD::ZERO_EXTEND)
1608 ReturnMVT = MVT::i8;
1610 ReturnMVT = MVT::i32;
1612 EVT MinVT = getRegisterType(Context, ReturnMVT);
1613 return VT.bitsLT(MinVT) ? MinVT : VT;
1616 /// LowerCallResult - Lower the result values of a call into the
1617 /// appropriate copies out of appropriate physical registers.
1620 X86TargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
1621 CallingConv::ID CallConv, bool isVarArg,
1622 const SmallVectorImpl<ISD::InputArg> &Ins,
1623 DebugLoc dl, SelectionDAG &DAG,
1624 SmallVectorImpl<SDValue> &InVals) const {
1626 // Assign locations to each value returned by this call.
1627 SmallVector<CCValAssign, 16> RVLocs;
1628 bool Is64Bit = Subtarget->is64Bit();
1629 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
1630 getTargetMachine(), RVLocs, *DAG.getContext());
1631 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
1633 // Copy all of the result registers out of their specified physreg.
1634 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1635 CCValAssign &VA = RVLocs[i];
1636 EVT CopyVT = VA.getValVT();
1638 // If this is x86-64, and we disabled SSE, we can't return FP values
1639 if ((CopyVT == MVT::f32 || CopyVT == MVT::f64) &&
1640 ((Is64Bit || Ins[i].Flags.isInReg()) && !Subtarget->hasSSE1())) {
1641 report_fatal_error("SSE register return with SSE disabled");
1646 // If this is a call to a function that returns an fp value on the floating
1647 // point stack, we must guarantee the the value is popped from the stack, so
1648 // a CopyFromReg is not good enough - the copy instruction may be eliminated
1649 // if the return value is not used. We use the FpPOP_RETVAL instruction
1651 if (VA.getLocReg() == X86::ST0 || VA.getLocReg() == X86::ST1) {
1652 // If we prefer to use the value in xmm registers, copy it out as f80 and
1653 // use a truncate to move it from fp stack reg to xmm reg.
1654 if (isScalarFPTypeInSSEReg(VA.getValVT())) CopyVT = MVT::f80;
1655 SDValue Ops[] = { Chain, InFlag };
1656 Chain = SDValue(DAG.getMachineNode(X86::FpPOP_RETVAL, dl, CopyVT,
1657 MVT::Other, MVT::Glue, Ops, 2), 1);
1658 Val = Chain.getValue(0);
1660 // Round the f80 to the right size, which also moves it to the appropriate
1662 if (CopyVT != VA.getValVT())
1663 Val = DAG.getNode(ISD::FP_ROUND, dl, VA.getValVT(), Val,
1664 // This truncation won't change the value.
1665 DAG.getIntPtrConstant(1));
1667 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(),
1668 CopyVT, InFlag).getValue(1);
1669 Val = Chain.getValue(0);
1671 InFlag = Chain.getValue(2);
1672 InVals.push_back(Val);
1679 //===----------------------------------------------------------------------===//
1680 // C & StdCall & Fast Calling Convention implementation
1681 //===----------------------------------------------------------------------===//
1682 // StdCall calling convention seems to be standard for many Windows' API
1683 // routines and around. It differs from C calling convention just a little:
1684 // callee should clean up the stack, not caller. Symbols should be also
1685 // decorated in some fancy way :) It doesn't support any vector arguments.
1686 // For info on fast calling convention see Fast Calling Convention (tail call)
1687 // implementation LowerX86_32FastCCCallTo.
1689 /// CallIsStructReturn - Determines whether a call uses struct return
1691 static bool CallIsStructReturn(const SmallVectorImpl<ISD::OutputArg> &Outs) {
1695 return Outs[0].Flags.isSRet();
1698 /// ArgsAreStructReturn - Determines whether a function uses struct
1699 /// return semantics.
1701 ArgsAreStructReturn(const SmallVectorImpl<ISD::InputArg> &Ins) {
1705 return Ins[0].Flags.isSRet();
1708 /// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified
1709 /// by "Src" to address "Dst" with size and alignment information specified by
1710 /// the specific parameter attribute. The copy will be passed as a byval
1711 /// function parameter.
1713 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
1714 ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
1716 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32);
1718 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
1719 /*isVolatile*/false, /*AlwaysInline=*/true,
1720 MachinePointerInfo(), MachinePointerInfo());
1723 /// IsTailCallConvention - Return true if the calling convention is one that
1724 /// supports tail call optimization.
1725 static bool IsTailCallConvention(CallingConv::ID CC) {
1726 return (CC == CallingConv::Fast || CC == CallingConv::GHC);
1729 bool X86TargetLowering::mayBeEmittedAsTailCall(CallInst *CI) const {
1730 if (!CI->isTailCall() || getTargetMachine().Options.DisableTailCalls)
1734 CallingConv::ID CalleeCC = CS.getCallingConv();
1735 if (!IsTailCallConvention(CalleeCC) && CalleeCC != CallingConv::C)
1741 /// FuncIsMadeTailCallSafe - Return true if the function is being made into
1742 /// a tailcall target by changing its ABI.
1743 static bool FuncIsMadeTailCallSafe(CallingConv::ID CC,
1744 bool GuaranteedTailCallOpt) {
1745 return GuaranteedTailCallOpt && IsTailCallConvention(CC);
1749 X86TargetLowering::LowerMemArgument(SDValue Chain,
1750 CallingConv::ID CallConv,
1751 const SmallVectorImpl<ISD::InputArg> &Ins,
1752 DebugLoc dl, SelectionDAG &DAG,
1753 const CCValAssign &VA,
1754 MachineFrameInfo *MFI,
1756 // Create the nodes corresponding to a load from this parameter slot.
1757 ISD::ArgFlagsTy Flags = Ins[i].Flags;
1758 bool AlwaysUseMutable = FuncIsMadeTailCallSafe(CallConv,
1759 getTargetMachine().Options.GuaranteedTailCallOpt);
1760 bool isImmutable = !AlwaysUseMutable && !Flags.isByVal();
1763 // If value is passed by pointer we have address passed instead of the value
1765 if (VA.getLocInfo() == CCValAssign::Indirect)
1766 ValVT = VA.getLocVT();
1768 ValVT = VA.getValVT();
1770 // FIXME: For now, all byval parameter objects are marked mutable. This can be
1771 // changed with more analysis.
1772 // In case of tail call optimization mark all arguments mutable. Since they
1773 // could be overwritten by lowering of arguments in case of a tail call.
1774 if (Flags.isByVal()) {
1775 unsigned Bytes = Flags.getByValSize();
1776 if (Bytes == 0) Bytes = 1; // Don't create zero-sized stack objects.
1777 int FI = MFI->CreateFixedObject(Bytes, VA.getLocMemOffset(), isImmutable);
1778 return DAG.getFrameIndex(FI, getPointerTy());
1780 int FI = MFI->CreateFixedObject(ValVT.getSizeInBits()/8,
1781 VA.getLocMemOffset(), isImmutable);
1782 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
1783 return DAG.getLoad(ValVT, dl, Chain, FIN,
1784 MachinePointerInfo::getFixedStack(FI),
1785 false, false, false, 0);
1790 X86TargetLowering::LowerFormalArguments(SDValue Chain,
1791 CallingConv::ID CallConv,
1793 const SmallVectorImpl<ISD::InputArg> &Ins,
1796 SmallVectorImpl<SDValue> &InVals)
1798 MachineFunction &MF = DAG.getMachineFunction();
1799 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1801 const Function* Fn = MF.getFunction();
1802 if (Fn->hasExternalLinkage() &&
1803 Subtarget->isTargetCygMing() &&
1804 Fn->getName() == "main")
1805 FuncInfo->setForceFramePointer(true);
1807 MachineFrameInfo *MFI = MF.getFrameInfo();
1808 bool Is64Bit = Subtarget->is64Bit();
1809 bool IsWindows = Subtarget->isTargetWindows();
1810 bool IsWin64 = Subtarget->isTargetWin64();
1812 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
1813 "Var args not supported with calling convention fastcc or ghc");
1815 // Assign locations to all of the incoming arguments.
1816 SmallVector<CCValAssign, 16> ArgLocs;
1817 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(),
1818 ArgLocs, *DAG.getContext());
1820 // Allocate shadow area for Win64
1822 CCInfo.AllocateStack(32, 8);
1825 CCInfo.AnalyzeFormalArguments(Ins, CC_X86);
1827 unsigned LastVal = ~0U;
1829 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1830 CCValAssign &VA = ArgLocs[i];
1831 // TODO: If an arg is passed in two places (e.g. reg and stack), skip later
1833 assert(VA.getValNo() != LastVal &&
1834 "Don't support value assigned to multiple locs yet");
1836 LastVal = VA.getValNo();
1838 if (VA.isRegLoc()) {
1839 EVT RegVT = VA.getLocVT();
1840 TargetRegisterClass *RC = NULL;
1841 if (RegVT == MVT::i32)
1842 RC = X86::GR32RegisterClass;
1843 else if (Is64Bit && RegVT == MVT::i64)
1844 RC = X86::GR64RegisterClass;
1845 else if (RegVT == MVT::f32)
1846 RC = X86::FR32RegisterClass;
1847 else if (RegVT == MVT::f64)
1848 RC = X86::FR64RegisterClass;
1849 else if (RegVT.isVector() && RegVT.getSizeInBits() == 256)
1850 RC = X86::VR256RegisterClass;
1851 else if (RegVT.isVector() && RegVT.getSizeInBits() == 128)
1852 RC = X86::VR128RegisterClass;
1853 else if (RegVT == MVT::x86mmx)
1854 RC = X86::VR64RegisterClass;
1856 llvm_unreachable("Unknown argument type!");
1858 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
1859 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
1861 // If this is an 8 or 16-bit value, it is really passed promoted to 32
1862 // bits. Insert an assert[sz]ext to capture this, then truncate to the
1864 if (VA.getLocInfo() == CCValAssign::SExt)
1865 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
1866 DAG.getValueType(VA.getValVT()));
1867 else if (VA.getLocInfo() == CCValAssign::ZExt)
1868 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
1869 DAG.getValueType(VA.getValVT()));
1870 else if (VA.getLocInfo() == CCValAssign::BCvt)
1871 ArgValue = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), ArgValue);
1873 if (VA.isExtInLoc()) {
1874 // Handle MMX values passed in XMM regs.
1875 if (RegVT.isVector()) {
1876 ArgValue = DAG.getNode(X86ISD::MOVDQ2Q, dl, VA.getValVT(),
1879 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
1882 assert(VA.isMemLoc());
1883 ArgValue = LowerMemArgument(Chain, CallConv, Ins, dl, DAG, VA, MFI, i);
1886 // If value is passed via pointer - do a load.
1887 if (VA.getLocInfo() == CCValAssign::Indirect)
1888 ArgValue = DAG.getLoad(VA.getValVT(), dl, Chain, ArgValue,
1889 MachinePointerInfo(), false, false, false, 0);
1891 InVals.push_back(ArgValue);
1894 // The x86-64 ABI for returning structs by value requires that we copy
1895 // the sret argument into %rax for the return. Save the argument into
1896 // a virtual register so that we can access it from the return points.
1897 if (Is64Bit && MF.getFunction()->hasStructRetAttr()) {
1898 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1899 unsigned Reg = FuncInfo->getSRetReturnReg();
1901 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(MVT::i64));
1902 FuncInfo->setSRetReturnReg(Reg);
1904 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, InVals[0]);
1905 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain);
1908 unsigned StackSize = CCInfo.getNextStackOffset();
1909 // Align stack specially for tail calls.
1910 if (FuncIsMadeTailCallSafe(CallConv,
1911 MF.getTarget().Options.GuaranteedTailCallOpt))
1912 StackSize = GetAlignedArgumentStackSize(StackSize, DAG);
1914 // If the function takes variable number of arguments, make a frame index for
1915 // the start of the first vararg value... for expansion of llvm.va_start.
1917 if (Is64Bit || (CallConv != CallingConv::X86_FastCall &&
1918 CallConv != CallingConv::X86_ThisCall)) {
1919 FuncInfo->setVarArgsFrameIndex(MFI->CreateFixedObject(1, StackSize,true));
1922 unsigned TotalNumIntRegs = 0, TotalNumXMMRegs = 0;
1924 // FIXME: We should really autogenerate these arrays
1925 static const unsigned GPR64ArgRegsWin64[] = {
1926 X86::RCX, X86::RDX, X86::R8, X86::R9
1928 static const unsigned GPR64ArgRegs64Bit[] = {
1929 X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9
1931 static const unsigned XMMArgRegs64Bit[] = {
1932 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
1933 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
1935 const unsigned *GPR64ArgRegs;
1936 unsigned NumXMMRegs = 0;
1939 // The XMM registers which might contain var arg parameters are shadowed
1940 // in their paired GPR. So we only need to save the GPR to their home
1942 TotalNumIntRegs = 4;
1943 GPR64ArgRegs = GPR64ArgRegsWin64;
1945 TotalNumIntRegs = 6; TotalNumXMMRegs = 8;
1946 GPR64ArgRegs = GPR64ArgRegs64Bit;
1948 NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs64Bit,
1951 unsigned NumIntRegs = CCInfo.getFirstUnallocated(GPR64ArgRegs,
1954 bool NoImplicitFloatOps = Fn->hasFnAttr(Attribute::NoImplicitFloat);
1955 assert(!(NumXMMRegs && !Subtarget->hasSSE1()) &&
1956 "SSE register cannot be used when SSE is disabled!");
1957 assert(!(NumXMMRegs && MF.getTarget().Options.UseSoftFloat &&
1958 NoImplicitFloatOps) &&
1959 "SSE register cannot be used when SSE is disabled!");
1960 if (MF.getTarget().Options.UseSoftFloat || NoImplicitFloatOps ||
1961 !Subtarget->hasSSE1())
1962 // Kernel mode asks for SSE to be disabled, so don't push them
1964 TotalNumXMMRegs = 0;
1967 const TargetFrameLowering &TFI = *getTargetMachine().getFrameLowering();
1968 // Get to the caller-allocated home save location. Add 8 to account
1969 // for the return address.
1970 int HomeOffset = TFI.getOffsetOfLocalArea() + 8;
1971 FuncInfo->setRegSaveFrameIndex(
1972 MFI->CreateFixedObject(1, NumIntRegs * 8 + HomeOffset, false));
1973 // Fixup to set vararg frame on shadow area (4 x i64).
1975 FuncInfo->setVarArgsFrameIndex(FuncInfo->getRegSaveFrameIndex());
1977 // For X86-64, if there are vararg parameters that are passed via
1978 // registers, then we must store them to their spots on the stack so
1979 // they may be loaded by deferencing the result of va_next.
1980 FuncInfo->setVarArgsGPOffset(NumIntRegs * 8);
1981 FuncInfo->setVarArgsFPOffset(TotalNumIntRegs * 8 + NumXMMRegs * 16);
1982 FuncInfo->setRegSaveFrameIndex(
1983 MFI->CreateStackObject(TotalNumIntRegs * 8 + TotalNumXMMRegs * 16, 16,
1987 // Store the integer parameter registers.
1988 SmallVector<SDValue, 8> MemOps;
1989 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
1991 unsigned Offset = FuncInfo->getVarArgsGPOffset();
1992 for (; NumIntRegs != TotalNumIntRegs; ++NumIntRegs) {
1993 SDValue FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), RSFIN,
1994 DAG.getIntPtrConstant(Offset));
1995 unsigned VReg = MF.addLiveIn(GPR64ArgRegs[NumIntRegs],
1996 X86::GR64RegisterClass);
1997 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64);
1999 DAG.getStore(Val.getValue(1), dl, Val, FIN,
2000 MachinePointerInfo::getFixedStack(
2001 FuncInfo->getRegSaveFrameIndex(), Offset),
2003 MemOps.push_back(Store);
2007 if (TotalNumXMMRegs != 0 && NumXMMRegs != TotalNumXMMRegs) {
2008 // Now store the XMM (fp + vector) parameter registers.
2009 SmallVector<SDValue, 11> SaveXMMOps;
2010 SaveXMMOps.push_back(Chain);
2012 unsigned AL = MF.addLiveIn(X86::AL, X86::GR8RegisterClass);
2013 SDValue ALVal = DAG.getCopyFromReg(DAG.getEntryNode(), dl, AL, MVT::i8);
2014 SaveXMMOps.push_back(ALVal);
2016 SaveXMMOps.push_back(DAG.getIntPtrConstant(
2017 FuncInfo->getRegSaveFrameIndex()));
2018 SaveXMMOps.push_back(DAG.getIntPtrConstant(
2019 FuncInfo->getVarArgsFPOffset()));
2021 for (; NumXMMRegs != TotalNumXMMRegs; ++NumXMMRegs) {
2022 unsigned VReg = MF.addLiveIn(XMMArgRegs64Bit[NumXMMRegs],
2023 X86::VR128RegisterClass);
2024 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::v4f32);
2025 SaveXMMOps.push_back(Val);
2027 MemOps.push_back(DAG.getNode(X86ISD::VASTART_SAVE_XMM_REGS, dl,
2029 &SaveXMMOps[0], SaveXMMOps.size()));
2032 if (!MemOps.empty())
2033 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
2034 &MemOps[0], MemOps.size());
2038 // Some CCs need callee pop.
2039 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg,
2040 MF.getTarget().Options.GuaranteedTailCallOpt)) {
2041 FuncInfo->setBytesToPopOnReturn(StackSize); // Callee pops everything.
2043 FuncInfo->setBytesToPopOnReturn(0); // Callee pops nothing.
2044 // If this is an sret function, the return should pop the hidden pointer.
2045 if (!Is64Bit && !IsTailCallConvention(CallConv) && !IsWindows &&
2046 ArgsAreStructReturn(Ins))
2047 FuncInfo->setBytesToPopOnReturn(4);
2051 // RegSaveFrameIndex is X86-64 only.
2052 FuncInfo->setRegSaveFrameIndex(0xAAAAAAA);
2053 if (CallConv == CallingConv::X86_FastCall ||
2054 CallConv == CallingConv::X86_ThisCall)
2055 // fastcc functions can't have varargs.
2056 FuncInfo->setVarArgsFrameIndex(0xAAAAAAA);
2059 FuncInfo->setArgumentStackSize(StackSize);
2065 X86TargetLowering::LowerMemOpCallTo(SDValue Chain,
2066 SDValue StackPtr, SDValue Arg,
2067 DebugLoc dl, SelectionDAG &DAG,
2068 const CCValAssign &VA,
2069 ISD::ArgFlagsTy Flags) const {
2070 unsigned LocMemOffset = VA.getLocMemOffset();
2071 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
2072 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
2073 if (Flags.isByVal())
2074 return CreateCopyOfByValArgument(Arg, PtrOff, Chain, Flags, DAG, dl);
2076 return DAG.getStore(Chain, dl, Arg, PtrOff,
2077 MachinePointerInfo::getStack(LocMemOffset),
2081 /// EmitTailCallLoadRetAddr - Emit a load of return address if tail call
2082 /// optimization is performed and it is required.
2084 X86TargetLowering::EmitTailCallLoadRetAddr(SelectionDAG &DAG,
2085 SDValue &OutRetAddr, SDValue Chain,
2086 bool IsTailCall, bool Is64Bit,
2087 int FPDiff, DebugLoc dl) const {
2088 // Adjust the Return address stack slot.
2089 EVT VT = getPointerTy();
2090 OutRetAddr = getReturnAddressFrameIndex(DAG);
2092 // Load the "old" Return address.
2093 OutRetAddr = DAG.getLoad(VT, dl, Chain, OutRetAddr, MachinePointerInfo(),
2094 false, false, false, 0);
2095 return SDValue(OutRetAddr.getNode(), 1);
2098 /// EmitTailCallStoreRetAddr - Emit a store of the return address if tail call
2099 /// optimization is performed and it is required (FPDiff!=0).
2101 EmitTailCallStoreRetAddr(SelectionDAG & DAG, MachineFunction &MF,
2102 SDValue Chain, SDValue RetAddrFrIdx,
2103 bool Is64Bit, int FPDiff, DebugLoc dl) {
2104 // Store the return address to the appropriate stack slot.
2105 if (!FPDiff) return Chain;
2106 // Calculate the new stack slot for the return address.
2107 int SlotSize = Is64Bit ? 8 : 4;
2108 int NewReturnAddrFI =
2109 MF.getFrameInfo()->CreateFixedObject(SlotSize, FPDiff-SlotSize, false);
2110 EVT VT = Is64Bit ? MVT::i64 : MVT::i32;
2111 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewReturnAddrFI, VT);
2112 Chain = DAG.getStore(Chain, dl, RetAddrFrIdx, NewRetAddrFrIdx,
2113 MachinePointerInfo::getFixedStack(NewReturnAddrFI),
2119 X86TargetLowering::LowerCall(SDValue Chain, SDValue Callee,
2120 CallingConv::ID CallConv, bool isVarArg,
2122 const SmallVectorImpl<ISD::OutputArg> &Outs,
2123 const SmallVectorImpl<SDValue> &OutVals,
2124 const SmallVectorImpl<ISD::InputArg> &Ins,
2125 DebugLoc dl, SelectionDAG &DAG,
2126 SmallVectorImpl<SDValue> &InVals) const {
2127 MachineFunction &MF = DAG.getMachineFunction();
2128 bool Is64Bit = Subtarget->is64Bit();
2129 bool IsWin64 = Subtarget->isTargetWin64();
2130 bool IsWindows = Subtarget->isTargetWindows();
2131 bool IsStructRet = CallIsStructReturn(Outs);
2132 bool IsSibcall = false;
2134 if (MF.getTarget().Options.DisableTailCalls)
2138 // Check if it's really possible to do a tail call.
2139 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv,
2140 isVarArg, IsStructRet, MF.getFunction()->hasStructRetAttr(),
2141 Outs, OutVals, Ins, DAG);
2143 // Sibcalls are automatically detected tailcalls which do not require
2145 if (!MF.getTarget().Options.GuaranteedTailCallOpt && isTailCall)
2152 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
2153 "Var args not supported with calling convention fastcc or ghc");
2155 // Analyze operands of the call, assigning locations to each operand.
2156 SmallVector<CCValAssign, 16> ArgLocs;
2157 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(),
2158 ArgLocs, *DAG.getContext());
2160 // Allocate shadow area for Win64
2162 CCInfo.AllocateStack(32, 8);
2165 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
2167 // Get a count of how many bytes are to be pushed on the stack.
2168 unsigned NumBytes = CCInfo.getNextStackOffset();
2170 // This is a sibcall. The memory operands are available in caller's
2171 // own caller's stack.
2173 else if (getTargetMachine().Options.GuaranteedTailCallOpt &&
2174 IsTailCallConvention(CallConv))
2175 NumBytes = GetAlignedArgumentStackSize(NumBytes, DAG);
2178 if (isTailCall && !IsSibcall) {
2179 // Lower arguments at fp - stackoffset + fpdiff.
2180 unsigned NumBytesCallerPushed =
2181 MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn();
2182 FPDiff = NumBytesCallerPushed - NumBytes;
2184 // Set the delta of movement of the returnaddr stackslot.
2185 // But only set if delta is greater than previous delta.
2186 if (FPDiff < (MF.getInfo<X86MachineFunctionInfo>()->getTCReturnAddrDelta()))
2187 MF.getInfo<X86MachineFunctionInfo>()->setTCReturnAddrDelta(FPDiff);
2191 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true));
2193 SDValue RetAddrFrIdx;
2194 // Load return address for tail calls.
2195 if (isTailCall && FPDiff)
2196 Chain = EmitTailCallLoadRetAddr(DAG, RetAddrFrIdx, Chain, isTailCall,
2197 Is64Bit, FPDiff, dl);
2199 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
2200 SmallVector<SDValue, 8> MemOpChains;
2203 // Walk the register/memloc assignments, inserting copies/loads. In the case
2204 // of tail call optimization arguments are handle later.
2205 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2206 CCValAssign &VA = ArgLocs[i];
2207 EVT RegVT = VA.getLocVT();
2208 SDValue Arg = OutVals[i];
2209 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2210 bool isByVal = Flags.isByVal();
2212 // Promote the value if needed.
2213 switch (VA.getLocInfo()) {
2214 default: llvm_unreachable("Unknown loc info!");
2215 case CCValAssign::Full: break;
2216 case CCValAssign::SExt:
2217 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, RegVT, Arg);
2219 case CCValAssign::ZExt:
2220 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, RegVT, Arg);
2222 case CCValAssign::AExt:
2223 if (RegVT.isVector() && RegVT.getSizeInBits() == 128) {
2224 // Special case: passing MMX values in XMM registers.
2225 Arg = DAG.getNode(ISD::BITCAST, dl, MVT::i64, Arg);
2226 Arg = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, Arg);
2227 Arg = getMOVL(DAG, dl, MVT::v2i64, DAG.getUNDEF(MVT::v2i64), Arg);
2229 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, RegVT, Arg);
2231 case CCValAssign::BCvt:
2232 Arg = DAG.getNode(ISD::BITCAST, dl, RegVT, Arg);
2234 case CCValAssign::Indirect: {
2235 // Store the argument.
2236 SDValue SpillSlot = DAG.CreateStackTemporary(VA.getValVT());
2237 int FI = cast<FrameIndexSDNode>(SpillSlot)->getIndex();
2238 Chain = DAG.getStore(Chain, dl, Arg, SpillSlot,
2239 MachinePointerInfo::getFixedStack(FI),
2246 if (VA.isRegLoc()) {
2247 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
2248 if (isVarArg && IsWin64) {
2249 // Win64 ABI requires argument XMM reg to be copied to the corresponding
2250 // shadow reg if callee is a varargs function.
2251 unsigned ShadowReg = 0;
2252 switch (VA.getLocReg()) {
2253 case X86::XMM0: ShadowReg = X86::RCX; break;
2254 case X86::XMM1: ShadowReg = X86::RDX; break;
2255 case X86::XMM2: ShadowReg = X86::R8; break;
2256 case X86::XMM3: ShadowReg = X86::R9; break;
2259 RegsToPass.push_back(std::make_pair(ShadowReg, Arg));
2261 } else if (!IsSibcall && (!isTailCall || isByVal)) {
2262 assert(VA.isMemLoc());
2263 if (StackPtr.getNode() == 0)
2264 StackPtr = DAG.getCopyFromReg(Chain, dl, X86StackPtr, getPointerTy());
2265 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Arg,
2266 dl, DAG, VA, Flags));
2270 if (!MemOpChains.empty())
2271 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
2272 &MemOpChains[0], MemOpChains.size());
2274 // Build a sequence of copy-to-reg nodes chained together with token chain
2275 // and flag operands which copy the outgoing args into registers.
2277 // Tail call byval lowering might overwrite argument registers so in case of
2278 // tail call optimization the copies to registers are lowered later.
2280 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
2281 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
2282 RegsToPass[i].second, InFlag);
2283 InFlag = Chain.getValue(1);
2286 if (Subtarget->isPICStyleGOT()) {
2287 // ELF / PIC requires GOT in the EBX register before function calls via PLT
2290 Chain = DAG.getCopyToReg(Chain, dl, X86::EBX,
2291 DAG.getNode(X86ISD::GlobalBaseReg,
2292 DebugLoc(), getPointerTy()),
2294 InFlag = Chain.getValue(1);
2296 // If we are tail calling and generating PIC/GOT style code load the
2297 // address of the callee into ECX. The value in ecx is used as target of
2298 // the tail jump. This is done to circumvent the ebx/callee-saved problem
2299 // for tail calls on PIC/GOT architectures. Normally we would just put the
2300 // address of GOT into ebx and then call target@PLT. But for tail calls
2301 // ebx would be restored (since ebx is callee saved) before jumping to the
2304 // Note: The actual moving to ECX is done further down.
2305 GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee);
2306 if (G && !G->getGlobal()->hasHiddenVisibility() &&
2307 !G->getGlobal()->hasProtectedVisibility())
2308 Callee = LowerGlobalAddress(Callee, DAG);
2309 else if (isa<ExternalSymbolSDNode>(Callee))
2310 Callee = LowerExternalSymbol(Callee, DAG);
2314 if (Is64Bit && isVarArg && !IsWin64) {
2315 // From AMD64 ABI document:
2316 // For calls that may call functions that use varargs or stdargs
2317 // (prototype-less calls or calls to functions containing ellipsis (...) in
2318 // the declaration) %al is used as hidden argument to specify the number
2319 // of SSE registers used. The contents of %al do not need to match exactly
2320 // the number of registers, but must be an ubound on the number of SSE
2321 // registers used and is in the range 0 - 8 inclusive.
2323 // Count the number of XMM registers allocated.
2324 static const unsigned XMMArgRegs[] = {
2325 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
2326 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
2328 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs, 8);
2329 assert((Subtarget->hasSSE1() || !NumXMMRegs)
2330 && "SSE registers cannot be used when SSE is disabled");
2332 Chain = DAG.getCopyToReg(Chain, dl, X86::AL,
2333 DAG.getConstant(NumXMMRegs, MVT::i8), InFlag);
2334 InFlag = Chain.getValue(1);
2338 // For tail calls lower the arguments to the 'real' stack slot.
2340 // Force all the incoming stack arguments to be loaded from the stack
2341 // before any new outgoing arguments are stored to the stack, because the
2342 // outgoing stack slots may alias the incoming argument stack slots, and
2343 // the alias isn't otherwise explicit. This is slightly more conservative
2344 // than necessary, because it means that each store effectively depends
2345 // on every argument instead of just those arguments it would clobber.
2346 SDValue ArgChain = DAG.getStackArgumentTokenFactor(Chain);
2348 SmallVector<SDValue, 8> MemOpChains2;
2351 // Do not flag preceding copytoreg stuff together with the following stuff.
2353 if (getTargetMachine().Options.GuaranteedTailCallOpt) {
2354 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2355 CCValAssign &VA = ArgLocs[i];
2358 assert(VA.isMemLoc());
2359 SDValue Arg = OutVals[i];
2360 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2361 // Create frame index.
2362 int32_t Offset = VA.getLocMemOffset()+FPDiff;
2363 uint32_t OpSize = (VA.getLocVT().getSizeInBits()+7)/8;
2364 FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true);
2365 FIN = DAG.getFrameIndex(FI, getPointerTy());
2367 if (Flags.isByVal()) {
2368 // Copy relative to framepointer.
2369 SDValue Source = DAG.getIntPtrConstant(VA.getLocMemOffset());
2370 if (StackPtr.getNode() == 0)
2371 StackPtr = DAG.getCopyFromReg(Chain, dl, X86StackPtr,
2373 Source = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, Source);
2375 MemOpChains2.push_back(CreateCopyOfByValArgument(Source, FIN,
2379 // Store relative to framepointer.
2380 MemOpChains2.push_back(
2381 DAG.getStore(ArgChain, dl, Arg, FIN,
2382 MachinePointerInfo::getFixedStack(FI),
2388 if (!MemOpChains2.empty())
2389 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
2390 &MemOpChains2[0], MemOpChains2.size());
2392 // Copy arguments to their registers.
2393 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
2394 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
2395 RegsToPass[i].second, InFlag);
2396 InFlag = Chain.getValue(1);
2400 // Store the return address to the appropriate stack slot.
2401 Chain = EmitTailCallStoreRetAddr(DAG, MF, Chain, RetAddrFrIdx, Is64Bit,
2405 if (getTargetMachine().getCodeModel() == CodeModel::Large) {
2406 assert(Is64Bit && "Large code model is only legal in 64-bit mode.");
2407 // In the 64-bit large code model, we have to make all calls
2408 // through a register, since the call instruction's 32-bit
2409 // pc-relative offset may not be large enough to hold the whole
2411 } else if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
2412 // If the callee is a GlobalAddress node (quite common, every direct call
2413 // is) turn it into a TargetGlobalAddress node so that legalize doesn't hack
2416 // We should use extra load for direct calls to dllimported functions in
2418 const GlobalValue *GV = G->getGlobal();
2419 if (!GV->hasDLLImportLinkage()) {
2420 unsigned char OpFlags = 0;
2421 bool ExtraLoad = false;
2422 unsigned WrapperKind = ISD::DELETED_NODE;
2424 // On ELF targets, in both X86-64 and X86-32 mode, direct calls to
2425 // external symbols most go through the PLT in PIC mode. If the symbol
2426 // has hidden or protected visibility, or if it is static or local, then
2427 // we don't need to use the PLT - we can directly call it.
2428 if (Subtarget->isTargetELF() &&
2429 getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
2430 GV->hasDefaultVisibility() && !GV->hasLocalLinkage()) {
2431 OpFlags = X86II::MO_PLT;
2432 } else if (Subtarget->isPICStyleStubAny() &&
2433 (GV->isDeclaration() || GV->isWeakForLinker()) &&
2434 (!Subtarget->getTargetTriple().isMacOSX() ||
2435 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
2436 // PC-relative references to external symbols should go through $stub,
2437 // unless we're building with the leopard linker or later, which
2438 // automatically synthesizes these stubs.
2439 OpFlags = X86II::MO_DARWIN_STUB;
2440 } else if (Subtarget->isPICStyleRIPRel() &&
2441 isa<Function>(GV) &&
2442 cast<Function>(GV)->hasFnAttr(Attribute::NonLazyBind)) {
2443 // If the function is marked as non-lazy, generate an indirect call
2444 // which loads from the GOT directly. This avoids runtime overhead
2445 // at the cost of eager binding (and one extra byte of encoding).
2446 OpFlags = X86II::MO_GOTPCREL;
2447 WrapperKind = X86ISD::WrapperRIP;
2451 Callee = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(),
2452 G->getOffset(), OpFlags);
2454 // Add a wrapper if needed.
2455 if (WrapperKind != ISD::DELETED_NODE)
2456 Callee = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Callee);
2457 // Add extra indirection if needed.
2459 Callee = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Callee,
2460 MachinePointerInfo::getGOT(),
2461 false, false, false, 0);
2463 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
2464 unsigned char OpFlags = 0;
2466 // On ELF targets, in either X86-64 or X86-32 mode, direct calls to
2467 // external symbols should go through the PLT.
2468 if (Subtarget->isTargetELF() &&
2469 getTargetMachine().getRelocationModel() == Reloc::PIC_) {
2470 OpFlags = X86II::MO_PLT;
2471 } else if (Subtarget->isPICStyleStubAny() &&
2472 (!Subtarget->getTargetTriple().isMacOSX() ||
2473 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
2474 // PC-relative references to external symbols should go through $stub,
2475 // unless we're building with the leopard linker or later, which
2476 // automatically synthesizes these stubs.
2477 OpFlags = X86II::MO_DARWIN_STUB;
2480 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy(),
2484 // Returns a chain & a flag for retval copy to use.
2485 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
2486 SmallVector<SDValue, 8> Ops;
2488 if (!IsSibcall && isTailCall) {
2489 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
2490 DAG.getIntPtrConstant(0, true), InFlag);
2491 InFlag = Chain.getValue(1);
2494 Ops.push_back(Chain);
2495 Ops.push_back(Callee);
2498 Ops.push_back(DAG.getConstant(FPDiff, MVT::i32));
2500 // Add argument registers to the end of the list so that they are known live
2502 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
2503 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
2504 RegsToPass[i].second.getValueType()));
2506 // Add an implicit use GOT pointer in EBX.
2507 if (!isTailCall && Subtarget->isPICStyleGOT())
2508 Ops.push_back(DAG.getRegister(X86::EBX, getPointerTy()));
2510 // Add an implicit use of AL for non-Windows x86 64-bit vararg functions.
2511 if (Is64Bit && isVarArg && !IsWin64)
2512 Ops.push_back(DAG.getRegister(X86::AL, MVT::i8));
2514 // Experimental: Add a register mask operand representing the call-preserved
2517 const TargetRegisterInfo *TRI = getTargetMachine().getRegisterInfo();
2518 const uint32_t *Mask = TRI->getCallPreservedMask(CallConv);
2519 Ops.push_back(DAG.getRegisterMask(Mask));
2522 if (InFlag.getNode())
2523 Ops.push_back(InFlag);
2527 //// If this is the first return lowered for this function, add the regs
2528 //// to the liveout set for the function.
2529 // This isn't right, although it's probably harmless on x86; liveouts
2530 // should be computed from returns not tail calls. Consider a void
2531 // function making a tail call to a function returning int.
2532 return DAG.getNode(X86ISD::TC_RETURN, dl,
2533 NodeTys, &Ops[0], Ops.size());
2536 Chain = DAG.getNode(X86ISD::CALL, dl, NodeTys, &Ops[0], Ops.size());
2537 InFlag = Chain.getValue(1);
2539 // Create the CALLSEQ_END node.
2540 unsigned NumBytesForCalleeToPush;
2541 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg,
2542 getTargetMachine().Options.GuaranteedTailCallOpt))
2543 NumBytesForCalleeToPush = NumBytes; // Callee pops everything
2544 else if (!Is64Bit && !IsTailCallConvention(CallConv) && !IsWindows &&
2546 // If this is a call to a struct-return function, the callee
2547 // pops the hidden struct pointer, so we have to push it back.
2548 // This is common for Darwin/X86, Linux & Mingw32 targets.
2549 // For MSVC Win32 targets, the caller pops the hidden struct pointer.
2550 NumBytesForCalleeToPush = 4;
2552 NumBytesForCalleeToPush = 0; // Callee pops nothing.
2554 // Returns a flag for retval copy to use.
2556 Chain = DAG.getCALLSEQ_END(Chain,
2557 DAG.getIntPtrConstant(NumBytes, true),
2558 DAG.getIntPtrConstant(NumBytesForCalleeToPush,
2561 InFlag = Chain.getValue(1);
2564 // Handle result values, copying them out of physregs into vregs that we
2566 return LowerCallResult(Chain, InFlag, CallConv, isVarArg,
2567 Ins, dl, DAG, InVals);
2571 //===----------------------------------------------------------------------===//
2572 // Fast Calling Convention (tail call) implementation
2573 //===----------------------------------------------------------------------===//
2575 // Like std call, callee cleans arguments, convention except that ECX is
2576 // reserved for storing the tail called function address. Only 2 registers are
2577 // free for argument passing (inreg). Tail call optimization is performed
2579 // * tailcallopt is enabled
2580 // * caller/callee are fastcc
2581 // On X86_64 architecture with GOT-style position independent code only local
2582 // (within module) calls are supported at the moment.
2583 // To keep the stack aligned according to platform abi the function
2584 // GetAlignedArgumentStackSize ensures that argument delta is always multiples
2585 // of stack alignment. (Dynamic linkers need this - darwin's dyld for example)
2586 // If a tail called function callee has more arguments than the caller the
2587 // caller needs to make sure that there is room to move the RETADDR to. This is
2588 // achieved by reserving an area the size of the argument delta right after the
2589 // original REtADDR, but before the saved framepointer or the spilled registers
2590 // e.g. caller(arg1, arg2) calls callee(arg1, arg2,arg3,arg4)
2602 /// GetAlignedArgumentStackSize - Make the stack size align e.g 16n + 12 aligned
2603 /// for a 16 byte align requirement.
2605 X86TargetLowering::GetAlignedArgumentStackSize(unsigned StackSize,
2606 SelectionDAG& DAG) const {
2607 MachineFunction &MF = DAG.getMachineFunction();
2608 const TargetMachine &TM = MF.getTarget();
2609 const TargetFrameLowering &TFI = *TM.getFrameLowering();
2610 unsigned StackAlignment = TFI.getStackAlignment();
2611 uint64_t AlignMask = StackAlignment - 1;
2612 int64_t Offset = StackSize;
2613 uint64_t SlotSize = TD->getPointerSize();
2614 if ( (Offset & AlignMask) <= (StackAlignment - SlotSize) ) {
2615 // Number smaller than 12 so just add the difference.
2616 Offset += ((StackAlignment - SlotSize) - (Offset & AlignMask));
2618 // Mask out lower bits, add stackalignment once plus the 12 bytes.
2619 Offset = ((~AlignMask) & Offset) + StackAlignment +
2620 (StackAlignment-SlotSize);
2625 /// MatchingStackOffset - Return true if the given stack call argument is
2626 /// already available in the same position (relatively) of the caller's
2627 /// incoming argument stack.
2629 bool MatchingStackOffset(SDValue Arg, unsigned Offset, ISD::ArgFlagsTy Flags,
2630 MachineFrameInfo *MFI, const MachineRegisterInfo *MRI,
2631 const X86InstrInfo *TII) {
2632 unsigned Bytes = Arg.getValueType().getSizeInBits() / 8;
2634 if (Arg.getOpcode() == ISD::CopyFromReg) {
2635 unsigned VR = cast<RegisterSDNode>(Arg.getOperand(1))->getReg();
2636 if (!TargetRegisterInfo::isVirtualRegister(VR))
2638 MachineInstr *Def = MRI->getVRegDef(VR);
2641 if (!Flags.isByVal()) {
2642 if (!TII->isLoadFromStackSlot(Def, FI))
2645 unsigned Opcode = Def->getOpcode();
2646 if ((Opcode == X86::LEA32r || Opcode == X86::LEA64r) &&
2647 Def->getOperand(1).isFI()) {
2648 FI = Def->getOperand(1).getIndex();
2649 Bytes = Flags.getByValSize();
2653 } else if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Arg)) {
2654 if (Flags.isByVal())
2655 // ByVal argument is passed in as a pointer but it's now being
2656 // dereferenced. e.g.
2657 // define @foo(%struct.X* %A) {
2658 // tail call @bar(%struct.X* byval %A)
2661 SDValue Ptr = Ld->getBasePtr();
2662 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr);
2665 FI = FINode->getIndex();
2666 } else if (Arg.getOpcode() == ISD::FrameIndex && Flags.isByVal()) {
2667 FrameIndexSDNode *FINode = cast<FrameIndexSDNode>(Arg);
2668 FI = FINode->getIndex();
2669 Bytes = Flags.getByValSize();
2673 assert(FI != INT_MAX);
2674 if (!MFI->isFixedObjectIndex(FI))
2676 return Offset == MFI->getObjectOffset(FI) && Bytes == MFI->getObjectSize(FI);
2679 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
2680 /// for tail call optimization. Targets which want to do tail call
2681 /// optimization should implement this function.
2683 X86TargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
2684 CallingConv::ID CalleeCC,
2686 bool isCalleeStructRet,
2687 bool isCallerStructRet,
2688 const SmallVectorImpl<ISD::OutputArg> &Outs,
2689 const SmallVectorImpl<SDValue> &OutVals,
2690 const SmallVectorImpl<ISD::InputArg> &Ins,
2691 SelectionDAG& DAG) const {
2692 if (!IsTailCallConvention(CalleeCC) &&
2693 CalleeCC != CallingConv::C)
2696 // If -tailcallopt is specified, make fastcc functions tail-callable.
2697 const MachineFunction &MF = DAG.getMachineFunction();
2698 const Function *CallerF = DAG.getMachineFunction().getFunction();
2699 CallingConv::ID CallerCC = CallerF->getCallingConv();
2700 bool CCMatch = CallerCC == CalleeCC;
2702 if (getTargetMachine().Options.GuaranteedTailCallOpt) {
2703 if (IsTailCallConvention(CalleeCC) && CCMatch)
2708 // Look for obvious safe cases to perform tail call optimization that do not
2709 // require ABI changes. This is what gcc calls sibcall.
2711 // Can't do sibcall if stack needs to be dynamically re-aligned. PEI needs to
2712 // emit a special epilogue.
2713 if (RegInfo->needsStackRealignment(MF))
2716 // Also avoid sibcall optimization if either caller or callee uses struct
2717 // return semantics.
2718 if (isCalleeStructRet || isCallerStructRet)
2721 // An stdcall caller is expected to clean up its arguments; the callee
2722 // isn't going to do that.
2723 if (!CCMatch && CallerCC==CallingConv::X86_StdCall)
2726 // Do not sibcall optimize vararg calls unless all arguments are passed via
2728 if (isVarArg && !Outs.empty()) {
2730 // Optimizing for varargs on Win64 is unlikely to be safe without
2731 // additional testing.
2732 if (Subtarget->isTargetWin64())
2735 SmallVector<CCValAssign, 16> ArgLocs;
2736 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(),
2737 getTargetMachine(), ArgLocs, *DAG.getContext());
2739 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
2740 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i)
2741 if (!ArgLocs[i].isRegLoc())
2745 // If the call result is in ST0 / ST1, it needs to be popped off the x87
2746 // stack. Therefore, if it's not used by the call it is not safe to optimize
2747 // this into a sibcall.
2748 bool Unused = false;
2749 for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
2756 SmallVector<CCValAssign, 16> RVLocs;
2757 CCState CCInfo(CalleeCC, false, DAG.getMachineFunction(),
2758 getTargetMachine(), RVLocs, *DAG.getContext());
2759 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
2760 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
2761 CCValAssign &VA = RVLocs[i];
2762 if (VA.getLocReg() == X86::ST0 || VA.getLocReg() == X86::ST1)
2767 // If the calling conventions do not match, then we'd better make sure the
2768 // results are returned in the same way as what the caller expects.
2770 SmallVector<CCValAssign, 16> RVLocs1;
2771 CCState CCInfo1(CalleeCC, false, DAG.getMachineFunction(),
2772 getTargetMachine(), RVLocs1, *DAG.getContext());
2773 CCInfo1.AnalyzeCallResult(Ins, RetCC_X86);
2775 SmallVector<CCValAssign, 16> RVLocs2;
2776 CCState CCInfo2(CallerCC, false, DAG.getMachineFunction(),
2777 getTargetMachine(), RVLocs2, *DAG.getContext());
2778 CCInfo2.AnalyzeCallResult(Ins, RetCC_X86);
2780 if (RVLocs1.size() != RVLocs2.size())
2782 for (unsigned i = 0, e = RVLocs1.size(); i != e; ++i) {
2783 if (RVLocs1[i].isRegLoc() != RVLocs2[i].isRegLoc())
2785 if (RVLocs1[i].getLocInfo() != RVLocs2[i].getLocInfo())
2787 if (RVLocs1[i].isRegLoc()) {
2788 if (RVLocs1[i].getLocReg() != RVLocs2[i].getLocReg())
2791 if (RVLocs1[i].getLocMemOffset() != RVLocs2[i].getLocMemOffset())
2797 // If the callee takes no arguments then go on to check the results of the
2799 if (!Outs.empty()) {
2800 // Check if stack adjustment is needed. For now, do not do this if any
2801 // argument is passed on the stack.
2802 SmallVector<CCValAssign, 16> ArgLocs;
2803 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(),
2804 getTargetMachine(), ArgLocs, *DAG.getContext());
2806 // Allocate shadow area for Win64
2807 if (Subtarget->isTargetWin64()) {
2808 CCInfo.AllocateStack(32, 8);
2811 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
2812 if (CCInfo.getNextStackOffset()) {
2813 MachineFunction &MF = DAG.getMachineFunction();
2814 if (MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn())
2817 // Check if the arguments are already laid out in the right way as
2818 // the caller's fixed stack objects.
2819 MachineFrameInfo *MFI = MF.getFrameInfo();
2820 const MachineRegisterInfo *MRI = &MF.getRegInfo();
2821 const X86InstrInfo *TII =
2822 ((X86TargetMachine&)getTargetMachine()).getInstrInfo();
2823 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2824 CCValAssign &VA = ArgLocs[i];
2825 SDValue Arg = OutVals[i];
2826 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2827 if (VA.getLocInfo() == CCValAssign::Indirect)
2829 if (!VA.isRegLoc()) {
2830 if (!MatchingStackOffset(Arg, VA.getLocMemOffset(), Flags,
2837 // If the tailcall address may be in a register, then make sure it's
2838 // possible to register allocate for it. In 32-bit, the call address can
2839 // only target EAX, EDX, or ECX since the tail call must be scheduled after
2840 // callee-saved registers are restored. These happen to be the same
2841 // registers used to pass 'inreg' arguments so watch out for those.
2842 if (!Subtarget->is64Bit() &&
2843 !isa<GlobalAddressSDNode>(Callee) &&
2844 !isa<ExternalSymbolSDNode>(Callee)) {
2845 unsigned NumInRegs = 0;
2846 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2847 CCValAssign &VA = ArgLocs[i];
2850 unsigned Reg = VA.getLocReg();
2853 case X86::EAX: case X86::EDX: case X86::ECX:
2854 if (++NumInRegs == 3)
2866 X86TargetLowering::createFastISel(FunctionLoweringInfo &funcInfo) const {
2867 return X86::createFastISel(funcInfo);
2871 //===----------------------------------------------------------------------===//
2872 // Other Lowering Hooks
2873 //===----------------------------------------------------------------------===//
2875 static bool MayFoldLoad(SDValue Op) {
2876 return Op.hasOneUse() && ISD::isNormalLoad(Op.getNode());
2879 static bool MayFoldIntoStore(SDValue Op) {
2880 return Op.hasOneUse() && ISD::isNormalStore(*Op.getNode()->use_begin());
2883 static bool isTargetShuffle(unsigned Opcode) {
2885 default: return false;
2886 case X86ISD::PSHUFD:
2887 case X86ISD::PSHUFHW:
2888 case X86ISD::PSHUFLW:
2890 case X86ISD::PALIGN:
2891 case X86ISD::MOVLHPS:
2892 case X86ISD::MOVLHPD:
2893 case X86ISD::MOVHLPS:
2894 case X86ISD::MOVLPS:
2895 case X86ISD::MOVLPD:
2896 case X86ISD::MOVSHDUP:
2897 case X86ISD::MOVSLDUP:
2898 case X86ISD::MOVDDUP:
2901 case X86ISD::UNPCKL:
2902 case X86ISD::UNPCKH:
2903 case X86ISD::VPERMILP:
2904 case X86ISD::VPERM2X128:
2909 static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT,
2910 SDValue V1, SelectionDAG &DAG) {
2912 default: llvm_unreachable("Unknown x86 shuffle node");
2913 case X86ISD::MOVSHDUP:
2914 case X86ISD::MOVSLDUP:
2915 case X86ISD::MOVDDUP:
2916 return DAG.getNode(Opc, dl, VT, V1);
2920 static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT,
2921 SDValue V1, unsigned TargetMask, SelectionDAG &DAG) {
2923 default: llvm_unreachable("Unknown x86 shuffle node");
2924 case X86ISD::PSHUFD:
2925 case X86ISD::PSHUFHW:
2926 case X86ISD::PSHUFLW:
2927 case X86ISD::VPERMILP:
2928 return DAG.getNode(Opc, dl, VT, V1, DAG.getConstant(TargetMask, MVT::i8));
2932 static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT,
2933 SDValue V1, SDValue V2, unsigned TargetMask, SelectionDAG &DAG) {
2935 default: llvm_unreachable("Unknown x86 shuffle node");
2936 case X86ISD::PALIGN:
2938 case X86ISD::VPERM2X128:
2939 return DAG.getNode(Opc, dl, VT, V1, V2,
2940 DAG.getConstant(TargetMask, MVT::i8));
2944 static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT,
2945 SDValue V1, SDValue V2, SelectionDAG &DAG) {
2947 default: llvm_unreachable("Unknown x86 shuffle node");
2948 case X86ISD::MOVLHPS:
2949 case X86ISD::MOVLHPD:
2950 case X86ISD::MOVHLPS:
2951 case X86ISD::MOVLPS:
2952 case X86ISD::MOVLPD:
2955 case X86ISD::UNPCKL:
2956 case X86ISD::UNPCKH:
2957 return DAG.getNode(Opc, dl, VT, V1, V2);
2961 SDValue X86TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) const {
2962 MachineFunction &MF = DAG.getMachineFunction();
2963 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
2964 int ReturnAddrIndex = FuncInfo->getRAIndex();
2966 if (ReturnAddrIndex == 0) {
2967 // Set up a frame object for the return address.
2968 uint64_t SlotSize = TD->getPointerSize();
2969 ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(SlotSize, -SlotSize,
2971 FuncInfo->setRAIndex(ReturnAddrIndex);
2974 return DAG.getFrameIndex(ReturnAddrIndex, getPointerTy());
2978 bool X86::isOffsetSuitableForCodeModel(int64_t Offset, CodeModel::Model M,
2979 bool hasSymbolicDisplacement) {
2980 // Offset should fit into 32 bit immediate field.
2981 if (!isInt<32>(Offset))
2984 // If we don't have a symbolic displacement - we don't have any extra
2986 if (!hasSymbolicDisplacement)
2989 // FIXME: Some tweaks might be needed for medium code model.
2990 if (M != CodeModel::Small && M != CodeModel::Kernel)
2993 // For small code model we assume that latest object is 16MB before end of 31
2994 // bits boundary. We may also accept pretty large negative constants knowing
2995 // that all objects are in the positive half of address space.
2996 if (M == CodeModel::Small && Offset < 16*1024*1024)
2999 // For kernel code model we know that all object resist in the negative half
3000 // of 32bits address space. We may not accept negative offsets, since they may
3001 // be just off and we may accept pretty large positive ones.
3002 if (M == CodeModel::Kernel && Offset > 0)
3008 /// isCalleePop - Determines whether the callee is required to pop its
3009 /// own arguments. Callee pop is necessary to support tail calls.
3010 bool X86::isCalleePop(CallingConv::ID CallingConv,
3011 bool is64Bit, bool IsVarArg, bool TailCallOpt) {
3015 switch (CallingConv) {
3018 case CallingConv::X86_StdCall:
3020 case CallingConv::X86_FastCall:
3022 case CallingConv::X86_ThisCall:
3024 case CallingConv::Fast:
3026 case CallingConv::GHC:
3031 /// TranslateX86CC - do a one to one translation of a ISD::CondCode to the X86
3032 /// specific condition code, returning the condition code and the LHS/RHS of the
3033 /// comparison to make.
3034 static unsigned TranslateX86CC(ISD::CondCode SetCCOpcode, bool isFP,
3035 SDValue &LHS, SDValue &RHS, SelectionDAG &DAG) {
3037 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
3038 if (SetCCOpcode == ISD::SETGT && RHSC->isAllOnesValue()) {
3039 // X > -1 -> X == 0, jump !sign.
3040 RHS = DAG.getConstant(0, RHS.getValueType());
3041 return X86::COND_NS;
3042 } else if (SetCCOpcode == ISD::SETLT && RHSC->isNullValue()) {
3043 // X < 0 -> X == 0, jump on sign.
3045 } else if (SetCCOpcode == ISD::SETLT && RHSC->getZExtValue() == 1) {
3047 RHS = DAG.getConstant(0, RHS.getValueType());
3048 return X86::COND_LE;
3052 switch (SetCCOpcode) {
3053 default: llvm_unreachable("Invalid integer condition!");
3054 case ISD::SETEQ: return X86::COND_E;
3055 case ISD::SETGT: return X86::COND_G;
3056 case ISD::SETGE: return X86::COND_GE;
3057 case ISD::SETLT: return X86::COND_L;
3058 case ISD::SETLE: return X86::COND_LE;
3059 case ISD::SETNE: return X86::COND_NE;
3060 case ISD::SETULT: return X86::COND_B;
3061 case ISD::SETUGT: return X86::COND_A;
3062 case ISD::SETULE: return X86::COND_BE;
3063 case ISD::SETUGE: return X86::COND_AE;
3067 // First determine if it is required or is profitable to flip the operands.
3069 // If LHS is a foldable load, but RHS is not, flip the condition.
3070 if (ISD::isNON_EXTLoad(LHS.getNode()) &&
3071 !ISD::isNON_EXTLoad(RHS.getNode())) {
3072 SetCCOpcode = getSetCCSwappedOperands(SetCCOpcode);
3073 std::swap(LHS, RHS);
3076 switch (SetCCOpcode) {
3082 std::swap(LHS, RHS);
3086 // On a floating point condition, the flags are set as follows:
3088 // 0 | 0 | 0 | X > Y
3089 // 0 | 0 | 1 | X < Y
3090 // 1 | 0 | 0 | X == Y
3091 // 1 | 1 | 1 | unordered
3092 switch (SetCCOpcode) {
3093 default: llvm_unreachable("Condcode should be pre-legalized away");
3095 case ISD::SETEQ: return X86::COND_E;
3096 case ISD::SETOLT: // flipped
3098 case ISD::SETGT: return X86::COND_A;
3099 case ISD::SETOLE: // flipped
3101 case ISD::SETGE: return X86::COND_AE;
3102 case ISD::SETUGT: // flipped
3104 case ISD::SETLT: return X86::COND_B;
3105 case ISD::SETUGE: // flipped
3107 case ISD::SETLE: return X86::COND_BE;
3109 case ISD::SETNE: return X86::COND_NE;
3110 case ISD::SETUO: return X86::COND_P;
3111 case ISD::SETO: return X86::COND_NP;
3113 case ISD::SETUNE: return X86::COND_INVALID;
3117 /// hasFPCMov - is there a floating point cmov for the specific X86 condition
3118 /// code. Current x86 isa includes the following FP cmov instructions:
3119 /// fcmovb, fcomvbe, fcomve, fcmovu, fcmovae, fcmova, fcmovne, fcmovnu.
3120 static bool hasFPCMov(unsigned X86CC) {
3136 /// isFPImmLegal - Returns true if the target can instruction select the
3137 /// specified FP immediate natively. If false, the legalizer will
3138 /// materialize the FP immediate as a load from a constant pool.
3139 bool X86TargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
3140 for (unsigned i = 0, e = LegalFPImmediates.size(); i != e; ++i) {
3141 if (Imm.bitwiseIsEqual(LegalFPImmediates[i]))
3147 /// isUndefOrInRange - Return true if Val is undef or if its value falls within
3148 /// the specified range (L, H].
3149 static bool isUndefOrInRange(int Val, int Low, int Hi) {
3150 return (Val < 0) || (Val >= Low && Val < Hi);
3153 /// isUndefOrEqual - Val is either less than zero (undef) or equal to the
3154 /// specified value.
3155 static bool isUndefOrEqual(int Val, int CmpVal) {
3156 if (Val < 0 || Val == CmpVal)
3161 /// isSequentialOrUndefInRange - Return true if every element in Mask, begining
3162 /// from position Pos and ending in Pos+Size, falls within the specified
3163 /// sequential range (L, L+Pos]. or is undef.
3164 static bool isSequentialOrUndefInRange(ArrayRef<int> Mask,
3165 int Pos, int Size, int Low) {
3166 for (int i = Pos, e = Pos+Size; i != e; ++i, ++Low)
3167 if (!isUndefOrEqual(Mask[i], Low))
3172 /// isPSHUFDMask - Return true if the node specifies a shuffle of elements that
3173 /// is suitable for input to PSHUFD or PSHUFW. That is, it doesn't reference
3174 /// the second operand.
3175 static bool isPSHUFDMask(ArrayRef<int> Mask, EVT VT) {
3176 if (VT == MVT::v4f32 || VT == MVT::v4i32 )
3177 return (Mask[0] < 4 && Mask[1] < 4 && Mask[2] < 4 && Mask[3] < 4);
3178 if (VT == MVT::v2f64 || VT == MVT::v2i64)
3179 return (Mask[0] < 2 && Mask[1] < 2);
3183 bool X86::isPSHUFDMask(ShuffleVectorSDNode *N) {
3184 return ::isPSHUFDMask(N->getMask(), N->getValueType(0));
3187 /// isPSHUFHWMask - Return true if the node specifies a shuffle of elements that
3188 /// is suitable for input to PSHUFHW.
3189 static bool isPSHUFHWMask(ArrayRef<int> Mask, EVT VT) {
3190 if (VT != MVT::v8i16)
3193 // Lower quadword copied in order or undef.
3194 if (!isSequentialOrUndefInRange(Mask, 0, 4, 0))
3197 // Upper quadword shuffled.
3198 for (unsigned i = 4; i != 8; ++i)
3199 if (Mask[i] >= 0 && (Mask[i] < 4 || Mask[i] > 7))
3205 bool X86::isPSHUFHWMask(ShuffleVectorSDNode *N) {
3206 return ::isPSHUFHWMask(N->getMask(), N->getValueType(0));
3209 /// isPSHUFLWMask - Return true if the node specifies a shuffle of elements that
3210 /// is suitable for input to PSHUFLW.
3211 static bool isPSHUFLWMask(ArrayRef<int> Mask, EVT VT) {
3212 if (VT != MVT::v8i16)
3215 // Upper quadword copied in order.
3216 if (!isSequentialOrUndefInRange(Mask, 4, 4, 4))
3219 // Lower quadword shuffled.
3220 for (unsigned i = 0; i != 4; ++i)
3227 bool X86::isPSHUFLWMask(ShuffleVectorSDNode *N) {
3228 return ::isPSHUFLWMask(N->getMask(), N->getValueType(0));
3231 /// isPALIGNRMask - Return true if the node specifies a shuffle of elements that
3232 /// is suitable for input to PALIGNR.
3233 static bool isPALIGNRMask(ArrayRef<int> Mask, EVT VT,
3234 const X86Subtarget *Subtarget) {
3235 if ((VT.getSizeInBits() == 128 && !Subtarget->hasSSSE3()) ||
3236 (VT.getSizeInBits() == 256 && !Subtarget->hasAVX2()))
3239 unsigned NumElts = VT.getVectorNumElements();
3240 unsigned NumLanes = VT.getSizeInBits()/128;
3241 unsigned NumLaneElts = NumElts/NumLanes;
3243 // Do not handle 64-bit element shuffles with palignr.
3244 if (NumLaneElts == 2)
3247 for (unsigned l = 0; l != NumElts; l+=NumLaneElts) {
3249 for (i = 0; i != NumLaneElts; ++i) {
3254 // Lane is all undef, go to next lane
3255 if (i == NumLaneElts)
3258 int Start = Mask[i+l];
3260 // Make sure its in this lane in one of the sources
3261 if (!isUndefOrInRange(Start, l, l+NumLaneElts) &&
3262 !isUndefOrInRange(Start, l+NumElts, l+NumElts+NumLaneElts))
3265 // If not lane 0, then we must match lane 0
3266 if (l != 0 && Mask[i] >= 0 && !isUndefOrEqual(Start, Mask[i]+l))
3269 // Correct second source to be contiguous with first source
3270 if (Start >= (int)NumElts)
3271 Start -= NumElts - NumLaneElts;
3273 // Make sure we're shifting in the right direction.
3274 if (Start <= (int)(i+l))
3279 // Check the rest of the elements to see if they are consecutive.
3280 for (++i; i != NumLaneElts; ++i) {
3281 int Idx = Mask[i+l];
3283 // Make sure its in this lane
3284 if (!isUndefOrInRange(Idx, l, l+NumLaneElts) &&
3285 !isUndefOrInRange(Idx, l+NumElts, l+NumElts+NumLaneElts))
3288 // If not lane 0, then we must match lane 0
3289 if (l != 0 && Mask[i] >= 0 && !isUndefOrEqual(Idx, Mask[i]+l))
3292 if (Idx >= (int)NumElts)
3293 Idx -= NumElts - NumLaneElts;
3295 if (!isUndefOrEqual(Idx, Start+i))
3304 /// CommuteVectorShuffleMask - Change values in a shuffle permute mask assuming
3305 /// the two vector operands have swapped position.
3306 static void CommuteVectorShuffleMask(SmallVectorImpl<int> &Mask,
3307 unsigned NumElems) {
3308 for (unsigned i = 0; i != NumElems; ++i) {
3312 else if (idx < (int)NumElems)
3313 Mask[i] = idx + NumElems;
3315 Mask[i] = idx - NumElems;
3319 /// isSHUFPMask - Return true if the specified VECTOR_SHUFFLE operand
3320 /// specifies a shuffle of elements that is suitable for input to 128/256-bit
3321 /// SHUFPS and SHUFPD. If Commuted is true, then it checks for sources to be
3322 /// reverse of what x86 shuffles want.
3323 static bool isSHUFPMask(ArrayRef<int> Mask, EVT VT, bool HasAVX,
3324 bool Commuted = false) {
3325 if (!HasAVX && VT.getSizeInBits() == 256)
3328 unsigned NumElems = VT.getVectorNumElements();
3329 unsigned NumLanes = VT.getSizeInBits()/128;
3330 unsigned NumLaneElems = NumElems/NumLanes;
3332 if (NumLaneElems != 2 && NumLaneElems != 4)
3335 // VSHUFPSY divides the resulting vector into 4 chunks.
3336 // The sources are also splitted into 4 chunks, and each destination
3337 // chunk must come from a different source chunk.
3339 // SRC1 => X7 X6 X5 X4 X3 X2 X1 X0
3340 // SRC2 => Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y9
3342 // DST => Y7..Y4, Y7..Y4, X7..X4, X7..X4,
3343 // Y3..Y0, Y3..Y0, X3..X0, X3..X0
3345 // VSHUFPDY divides the resulting vector into 4 chunks.
3346 // The sources are also splitted into 4 chunks, and each destination
3347 // chunk must come from a different source chunk.
3349 // SRC1 => X3 X2 X1 X0
3350 // SRC2 => Y3 Y2 Y1 Y0
3352 // DST => Y3..Y2, X3..X2, Y1..Y0, X1..X0
3354 unsigned HalfLaneElems = NumLaneElems/2;
3355 for (unsigned l = 0; l != NumElems; l += NumLaneElems) {
3356 for (unsigned i = 0; i != NumLaneElems; ++i) {
3357 int Idx = Mask[i+l];
3358 unsigned RngStart = l + ((Commuted == (i<HalfLaneElems)) ? NumElems : 0);
3359 if (!isUndefOrInRange(Idx, RngStart, RngStart+NumLaneElems))
3361 // For VSHUFPSY, the mask of the second half must be the same as the
3362 // first but with the appropriate offsets. This works in the same way as
3363 // VPERMILPS works with masks.
3364 if (NumElems != 8 || l == 0 || Mask[i] < 0)
3366 if (!isUndefOrEqual(Idx, Mask[i]+l))
3374 bool X86::isSHUFPMask(ShuffleVectorSDNode *N, bool HasAVX) {
3375 return ::isSHUFPMask(N->getMask(), N->getValueType(0), HasAVX);
3378 /// isMOVHLPSMask - Return true if the specified VECTOR_SHUFFLE operand
3379 /// specifies a shuffle of elements that is suitable for input to MOVHLPS.
3380 bool X86::isMOVHLPSMask(ShuffleVectorSDNode *N) {
3381 EVT VT = N->getValueType(0);
3382 unsigned NumElems = VT.getVectorNumElements();
3384 if (VT.getSizeInBits() != 128)
3390 // Expect bit0 == 6, bit1 == 7, bit2 == 2, bit3 == 3
3391 return isUndefOrEqual(N->getMaskElt(0), 6) &&
3392 isUndefOrEqual(N->getMaskElt(1), 7) &&
3393 isUndefOrEqual(N->getMaskElt(2), 2) &&
3394 isUndefOrEqual(N->getMaskElt(3), 3);
3397 /// isMOVHLPS_v_undef_Mask - Special case of isMOVHLPSMask for canonical form
3398 /// of vector_shuffle v, v, <2, 3, 2, 3>, i.e. vector_shuffle v, undef,
3400 bool X86::isMOVHLPS_v_undef_Mask(ShuffleVectorSDNode *N) {
3401 EVT VT = N->getValueType(0);
3402 unsigned NumElems = VT.getVectorNumElements();
3404 if (VT.getSizeInBits() != 128)
3410 return isUndefOrEqual(N->getMaskElt(0), 2) &&
3411 isUndefOrEqual(N->getMaskElt(1), 3) &&
3412 isUndefOrEqual(N->getMaskElt(2), 2) &&
3413 isUndefOrEqual(N->getMaskElt(3), 3);
3416 /// isMOVLPMask - Return true if the specified VECTOR_SHUFFLE operand
3417 /// specifies a shuffle of elements that is suitable for input to MOVLP{S|D}.
3418 bool X86::isMOVLPMask(ShuffleVectorSDNode *N) {
3419 EVT VT = N->getValueType(0);
3421 if (VT.getSizeInBits() != 128)
3424 unsigned NumElems = N->getValueType(0).getVectorNumElements();
3426 if (NumElems != 2 && NumElems != 4)
3429 for (unsigned i = 0; i < NumElems/2; ++i)
3430 if (!isUndefOrEqual(N->getMaskElt(i), i + NumElems))
3433 for (unsigned i = NumElems/2; i < NumElems; ++i)
3434 if (!isUndefOrEqual(N->getMaskElt(i), i))
3440 /// isMOVLHPSMask - Return true if the specified VECTOR_SHUFFLE operand
3441 /// specifies a shuffle of elements that is suitable for input to MOVLHPS.
3442 bool X86::isMOVLHPSMask(ShuffleVectorSDNode *N) {
3443 unsigned NumElems = N->getValueType(0).getVectorNumElements();
3445 if ((NumElems != 2 && NumElems != 4)
3446 || N->getValueType(0).getSizeInBits() > 128)
3449 for (unsigned i = 0; i < NumElems/2; ++i)
3450 if (!isUndefOrEqual(N->getMaskElt(i), i))
3453 for (unsigned i = 0; i < NumElems/2; ++i)
3454 if (!isUndefOrEqual(N->getMaskElt(i + NumElems/2), i + NumElems))
3460 /// isUNPCKLMask - Return true if the specified VECTOR_SHUFFLE operand
3461 /// specifies a shuffle of elements that is suitable for input to UNPCKL.
3462 static bool isUNPCKLMask(ArrayRef<int> Mask, EVT VT,
3463 bool HasAVX2, bool V2IsSplat = false) {
3464 unsigned NumElts = VT.getVectorNumElements();
3466 assert((VT.is128BitVector() || VT.is256BitVector()) &&
3467 "Unsupported vector type for unpckh");
3469 if (VT.getSizeInBits() == 256 && NumElts != 4 && NumElts != 8 &&
3470 (!HasAVX2 || (NumElts != 16 && NumElts != 32)))
3473 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
3474 // independently on 128-bit lanes.
3475 unsigned NumLanes = VT.getSizeInBits()/128;
3476 unsigned NumLaneElts = NumElts/NumLanes;
3478 for (unsigned l = 0; l != NumLanes; ++l) {
3479 for (unsigned i = l*NumLaneElts, j = l*NumLaneElts;
3480 i != (l+1)*NumLaneElts;
3483 int BitI1 = Mask[i+1];
3484 if (!isUndefOrEqual(BitI, j))
3487 if (!isUndefOrEqual(BitI1, NumElts))
3490 if (!isUndefOrEqual(BitI1, j + NumElts))
3499 bool X86::isUNPCKLMask(ShuffleVectorSDNode *N, bool HasAVX2, bool V2IsSplat) {
3500 return ::isUNPCKLMask(N->getMask(), N->getValueType(0), HasAVX2, V2IsSplat);
3503 /// isUNPCKHMask - Return true if the specified VECTOR_SHUFFLE operand
3504 /// specifies a shuffle of elements that is suitable for input to UNPCKH.
3505 static bool isUNPCKHMask(ArrayRef<int> Mask, EVT VT,
3506 bool HasAVX2, bool V2IsSplat = false) {
3507 unsigned NumElts = VT.getVectorNumElements();
3509 assert((VT.is128BitVector() || VT.is256BitVector()) &&
3510 "Unsupported vector type for unpckh");
3512 if (VT.getSizeInBits() == 256 && NumElts != 4 && NumElts != 8 &&
3513 (!HasAVX2 || (NumElts != 16 && NumElts != 32)))
3516 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
3517 // independently on 128-bit lanes.
3518 unsigned NumLanes = VT.getSizeInBits()/128;
3519 unsigned NumLaneElts = NumElts/NumLanes;
3521 for (unsigned l = 0; l != NumLanes; ++l) {
3522 for (unsigned i = l*NumLaneElts, j = (l*NumLaneElts)+NumLaneElts/2;
3523 i != (l+1)*NumLaneElts; i += 2, ++j) {
3525 int BitI1 = Mask[i+1];
3526 if (!isUndefOrEqual(BitI, j))
3529 if (isUndefOrEqual(BitI1, NumElts))
3532 if (!isUndefOrEqual(BitI1, j+NumElts))
3540 bool X86::isUNPCKHMask(ShuffleVectorSDNode *N, bool HasAVX2, bool V2IsSplat) {
3541 return ::isUNPCKHMask(N->getMask(), N->getValueType(0), HasAVX2, V2IsSplat);
3544 /// isUNPCKL_v_undef_Mask - Special case of isUNPCKLMask for canonical form
3545 /// of vector_shuffle v, v, <0, 4, 1, 5>, i.e. vector_shuffle v, undef,
3547 static bool isUNPCKL_v_undef_Mask(ArrayRef<int> Mask, EVT VT,
3549 unsigned NumElts = VT.getVectorNumElements();
3551 assert((VT.is128BitVector() || VT.is256BitVector()) &&
3552 "Unsupported vector type for unpckh");
3554 if (VT.getSizeInBits() == 256 && NumElts != 4 && NumElts != 8 &&
3555 (!HasAVX2 || (NumElts != 16 && NumElts != 32)))
3558 // For 256-bit i64/f64, use MOVDDUPY instead, so reject the matching pattern
3559 // FIXME: Need a better way to get rid of this, there's no latency difference
3560 // between UNPCKLPD and MOVDDUP, the later should always be checked first and
3561 // the former later. We should also remove the "_undef" special mask.
3562 if (NumElts == 4 && VT.getSizeInBits() == 256)
3565 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
3566 // independently on 128-bit lanes.
3567 unsigned NumLanes = VT.getSizeInBits()/128;
3568 unsigned NumLaneElts = NumElts/NumLanes;
3570 for (unsigned l = 0; l != NumLanes; ++l) {
3571 for (unsigned i = l*NumLaneElts, j = l*NumLaneElts;
3572 i != (l+1)*NumLaneElts;
3575 int BitI1 = Mask[i+1];
3577 if (!isUndefOrEqual(BitI, j))
3579 if (!isUndefOrEqual(BitI1, j))
3587 bool X86::isUNPCKL_v_undef_Mask(ShuffleVectorSDNode *N, bool HasAVX2) {
3588 return ::isUNPCKL_v_undef_Mask(N->getMask(), N->getValueType(0), HasAVX2);
3591 /// isUNPCKH_v_undef_Mask - Special case of isUNPCKHMask for canonical form
3592 /// of vector_shuffle v, v, <2, 6, 3, 7>, i.e. vector_shuffle v, undef,
3594 static bool isUNPCKH_v_undef_Mask(ArrayRef<int> Mask, EVT VT, bool HasAVX2) {
3595 unsigned NumElts = VT.getVectorNumElements();
3597 assert((VT.is128BitVector() || VT.is256BitVector()) &&
3598 "Unsupported vector type for unpckh");
3600 if (VT.getSizeInBits() == 256 && NumElts != 4 && NumElts != 8 &&
3601 (!HasAVX2 || (NumElts != 16 && NumElts != 32)))
3604 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
3605 // independently on 128-bit lanes.
3606 unsigned NumLanes = VT.getSizeInBits()/128;
3607 unsigned NumLaneElts = NumElts/NumLanes;
3609 for (unsigned l = 0; l != NumLanes; ++l) {
3610 for (unsigned i = l*NumLaneElts, j = (l*NumLaneElts)+NumLaneElts/2;
3611 i != (l+1)*NumLaneElts; i += 2, ++j) {
3613 int BitI1 = Mask[i+1];
3614 if (!isUndefOrEqual(BitI, j))
3616 if (!isUndefOrEqual(BitI1, j))
3623 bool X86::isUNPCKH_v_undef_Mask(ShuffleVectorSDNode *N, bool HasAVX2) {
3624 return ::isUNPCKH_v_undef_Mask(N->getMask(), N->getValueType(0), HasAVX2);
3627 /// isMOVLMask - Return true if the specified VECTOR_SHUFFLE operand
3628 /// specifies a shuffle of elements that is suitable for input to MOVSS,
3629 /// MOVSD, and MOVD, i.e. setting the lowest element.
3630 static bool isMOVLMask(ArrayRef<int> Mask, EVT VT) {
3631 if (VT.getVectorElementType().getSizeInBits() < 32)
3633 if (VT.getSizeInBits() == 256)
3636 unsigned NumElts = VT.getVectorNumElements();
3638 if (!isUndefOrEqual(Mask[0], NumElts))
3641 for (unsigned i = 1; i != NumElts; ++i)
3642 if (!isUndefOrEqual(Mask[i], i))
3648 bool X86::isMOVLMask(ShuffleVectorSDNode *N) {
3649 return ::isMOVLMask(N->getMask(), N->getValueType(0));
3652 /// isVPERM2X128Mask - Match 256-bit shuffles where the elements are considered
3653 /// as permutations between 128-bit chunks or halves. As an example: this
3655 /// vector_shuffle <4, 5, 6, 7, 12, 13, 14, 15>
3656 /// The first half comes from the second half of V1 and the second half from the
3657 /// the second half of V2.
3658 static bool isVPERM2X128Mask(ArrayRef<int> Mask, EVT VT, bool HasAVX) {
3659 if (!HasAVX || VT.getSizeInBits() != 256)
3662 // The shuffle result is divided into half A and half B. In total the two
3663 // sources have 4 halves, namely: C, D, E, F. The final values of A and
3664 // B must come from C, D, E or F.
3665 unsigned HalfSize = VT.getVectorNumElements()/2;
3666 bool MatchA = false, MatchB = false;
3668 // Check if A comes from one of C, D, E, F.
3669 for (unsigned Half = 0; Half != 4; ++Half) {
3670 if (isSequentialOrUndefInRange(Mask, 0, HalfSize, Half*HalfSize)) {
3676 // Check if B comes from one of C, D, E, F.
3677 for (unsigned Half = 0; Half != 4; ++Half) {
3678 if (isSequentialOrUndefInRange(Mask, HalfSize, HalfSize, Half*HalfSize)) {
3684 return MatchA && MatchB;
3687 /// getShuffleVPERM2X128Immediate - Return the appropriate immediate to shuffle
3688 /// the specified VECTOR_MASK mask with VPERM2F128/VPERM2I128 instructions.
3689 static unsigned getShuffleVPERM2X128Immediate(ShuffleVectorSDNode *SVOp) {
3690 EVT VT = SVOp->getValueType(0);
3692 unsigned HalfSize = VT.getVectorNumElements()/2;
3694 unsigned FstHalf = 0, SndHalf = 0;
3695 for (unsigned i = 0; i < HalfSize; ++i) {
3696 if (SVOp->getMaskElt(i) > 0) {
3697 FstHalf = SVOp->getMaskElt(i)/HalfSize;
3701 for (unsigned i = HalfSize; i < HalfSize*2; ++i) {
3702 if (SVOp->getMaskElt(i) > 0) {
3703 SndHalf = SVOp->getMaskElt(i)/HalfSize;
3708 return (FstHalf | (SndHalf << 4));
3711 /// isVPERMILPMask - Return true if the specified VECTOR_SHUFFLE operand
3712 /// specifies a shuffle of elements that is suitable for input to VPERMILPD*.
3713 /// Note that VPERMIL mask matching is different depending whether theunderlying
3714 /// type is 32 or 64. In the VPERMILPS the high half of the mask should point
3715 /// to the same elements of the low, but to the higher half of the source.
3716 /// In VPERMILPD the two lanes could be shuffled independently of each other
3717 /// with the same restriction that lanes can't be crossed.
3718 static bool isVPERMILPMask(ArrayRef<int> Mask, EVT VT, bool HasAVX) {
3722 unsigned NumElts = VT.getVectorNumElements();
3723 // Only match 256-bit with 32/64-bit types
3724 if (VT.getSizeInBits() != 256 || (NumElts != 4 && NumElts != 8))
3727 unsigned NumLanes = VT.getSizeInBits()/128;
3728 unsigned LaneSize = NumElts/NumLanes;
3729 for (unsigned l = 0; l != NumElts; l += LaneSize) {
3730 for (unsigned i = 0; i != LaneSize; ++i) {
3731 if (!isUndefOrInRange(Mask[i+l], l, l+LaneSize))
3733 if (NumElts != 8 || l == 0)
3735 // VPERMILPS handling
3738 if (!isUndefOrEqual(Mask[i+l], Mask[i]+l))
3746 /// getShuffleVPERMILPImmediate - Return the appropriate immediate to shuffle
3747 /// the specified VECTOR_MASK mask with VPERMILPS/D* instructions.
3748 static unsigned getShuffleVPERMILPImmediate(ShuffleVectorSDNode *SVOp) {
3749 EVT VT = SVOp->getValueType(0);
3751 unsigned NumElts = VT.getVectorNumElements();
3752 unsigned NumLanes = VT.getSizeInBits()/128;
3753 unsigned LaneSize = NumElts/NumLanes;
3755 // Although the mask is equal for both lanes do it twice to get the cases
3756 // where a mask will match because the same mask element is undef on the
3757 // first half but valid on the second. This would get pathological cases
3758 // such as: shuffle <u, 0, 1, 2, 4, 4, 5, 6>, which is completely valid.
3759 unsigned Shift = (LaneSize == 4) ? 2 : 1;
3761 for (unsigned i = 0; i != NumElts; ++i) {
3762 int MaskElt = SVOp->getMaskElt(i);
3765 MaskElt %= LaneSize;
3767 // VPERMILPSY, the mask of the first half must be equal to the second one
3768 if (NumElts == 8) Shamt %= LaneSize;
3769 Mask |= MaskElt << (Shamt*Shift);
3775 /// isCommutedMOVL - Returns true if the shuffle mask is except the reverse
3776 /// of what x86 movss want. X86 movs requires the lowest element to be lowest
3777 /// element of vector 2 and the other elements to come from vector 1 in order.
3778 static bool isCommutedMOVLMask(ArrayRef<int> Mask, EVT VT,
3779 bool V2IsSplat = false, bool V2IsUndef = false) {
3780 unsigned NumOps = VT.getVectorNumElements();
3781 if (NumOps != 2 && NumOps != 4 && NumOps != 8 && NumOps != 16)
3784 if (!isUndefOrEqual(Mask[0], 0))
3787 for (unsigned i = 1; i != NumOps; ++i)
3788 if (!(isUndefOrEqual(Mask[i], i+NumOps) ||
3789 (V2IsUndef && isUndefOrInRange(Mask[i], NumOps, NumOps*2)) ||
3790 (V2IsSplat && isUndefOrEqual(Mask[i], NumOps))))
3796 static bool isCommutedMOVL(ShuffleVectorSDNode *N, bool V2IsSplat = false,
3797 bool V2IsUndef = false) {
3798 return isCommutedMOVLMask(N->getMask(), N->getValueType(0),
3799 V2IsSplat, V2IsUndef);
3802 /// isMOVSHDUPMask - Return true if the specified VECTOR_SHUFFLE operand
3803 /// specifies a shuffle of elements that is suitable for input to MOVSHDUP.
3804 /// Masks to match: <1, 1, 3, 3> or <1, 1, 3, 3, 5, 5, 7, 7>
3805 bool X86::isMOVSHDUPMask(ShuffleVectorSDNode *N,
3806 const X86Subtarget *Subtarget) {
3807 if (!Subtarget->hasSSE3())
3810 // The second vector must be undef
3811 if (N->getOperand(1).getOpcode() != ISD::UNDEF)
3814 EVT VT = N->getValueType(0);
3815 unsigned NumElems = VT.getVectorNumElements();
3817 if ((VT.getSizeInBits() == 128 && NumElems != 4) ||
3818 (VT.getSizeInBits() == 256 && NumElems != 8))
3821 // "i+1" is the value the indexed mask element must have
3822 for (unsigned i = 0; i < NumElems; i += 2)
3823 if (!isUndefOrEqual(N->getMaskElt(i), i+1) ||
3824 !isUndefOrEqual(N->getMaskElt(i+1), i+1))
3830 /// isMOVSLDUPMask - Return true if the specified VECTOR_SHUFFLE operand
3831 /// specifies a shuffle of elements that is suitable for input to MOVSLDUP.
3832 /// Masks to match: <0, 0, 2, 2> or <0, 0, 2, 2, 4, 4, 6, 6>
3833 bool X86::isMOVSLDUPMask(ShuffleVectorSDNode *N,
3834 const X86Subtarget *Subtarget) {
3835 if (!Subtarget->hasSSE3())
3838 // The second vector must be undef
3839 if (N->getOperand(1).getOpcode() != ISD::UNDEF)
3842 EVT VT = N->getValueType(0);
3843 unsigned NumElems = VT.getVectorNumElements();
3845 if ((VT.getSizeInBits() == 128 && NumElems != 4) ||
3846 (VT.getSizeInBits() == 256 && NumElems != 8))
3849 // "i" is the value the indexed mask element must have
3850 for (unsigned i = 0; i != NumElems; i += 2)
3851 if (!isUndefOrEqual(N->getMaskElt(i), i) ||
3852 !isUndefOrEqual(N->getMaskElt(i+1), i))
3858 /// isMOVDDUPYMask - Return true if the specified VECTOR_SHUFFLE operand
3859 /// specifies a shuffle of elements that is suitable for input to 256-bit
3860 /// version of MOVDDUP.
3861 static bool isMOVDDUPYMask(ArrayRef<int> Mask, EVT VT, bool HasAVX) {
3862 unsigned NumElts = VT.getVectorNumElements();
3864 if (!HasAVX || VT.getSizeInBits() != 256 || NumElts != 4)
3867 for (unsigned i = 0; i != NumElts/2; ++i)
3868 if (!isUndefOrEqual(Mask[i], 0))
3870 for (unsigned i = NumElts/2; i != NumElts; ++i)
3871 if (!isUndefOrEqual(Mask[i], NumElts/2))
3876 /// isMOVDDUPMask - Return true if the specified VECTOR_SHUFFLE operand
3877 /// specifies a shuffle of elements that is suitable for input to 128-bit
3878 /// version of MOVDDUP.
3879 bool X86::isMOVDDUPMask(ShuffleVectorSDNode *N) {
3880 EVT VT = N->getValueType(0);
3882 if (VT.getSizeInBits() != 128)
3885 unsigned e = VT.getVectorNumElements() / 2;
3886 for (unsigned i = 0; i != e; ++i)
3887 if (!isUndefOrEqual(N->getMaskElt(i), i))
3889 for (unsigned i = 0; i != e; ++i)
3890 if (!isUndefOrEqual(N->getMaskElt(e+i), i))
3895 /// isVEXTRACTF128Index - Return true if the specified
3896 /// EXTRACT_SUBVECTOR operand specifies a vector extract that is
3897 /// suitable for input to VEXTRACTF128.
3898 bool X86::isVEXTRACTF128Index(SDNode *N) {
3899 if (!isa<ConstantSDNode>(N->getOperand(1).getNode()))
3902 // The index should be aligned on a 128-bit boundary.
3904 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
3906 unsigned VL = N->getValueType(0).getVectorNumElements();
3907 unsigned VBits = N->getValueType(0).getSizeInBits();
3908 unsigned ElSize = VBits / VL;
3909 bool Result = (Index * ElSize) % 128 == 0;
3914 /// isVINSERTF128Index - Return true if the specified INSERT_SUBVECTOR
3915 /// operand specifies a subvector insert that is suitable for input to
3917 bool X86::isVINSERTF128Index(SDNode *N) {
3918 if (!isa<ConstantSDNode>(N->getOperand(2).getNode()))
3921 // The index should be aligned on a 128-bit boundary.
3923 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
3925 unsigned VL = N->getValueType(0).getVectorNumElements();
3926 unsigned VBits = N->getValueType(0).getSizeInBits();
3927 unsigned ElSize = VBits / VL;
3928 bool Result = (Index * ElSize) % 128 == 0;
3933 /// getShuffleSHUFImmediate - Return the appropriate immediate to shuffle
3934 /// the specified VECTOR_SHUFFLE mask with PSHUF* and SHUFP* instructions.
3935 /// Handles 128-bit and 256-bit.
3936 unsigned X86::getShuffleSHUFImmediate(ShuffleVectorSDNode *N) {
3937 EVT VT = N->getValueType(0);
3939 assert((VT.is128BitVector() || VT.is256BitVector()) &&
3940 "Unsupported vector type for PSHUF/SHUFP");
3942 // Handle 128 and 256-bit vector lengths. AVX defines PSHUF/SHUFP to operate
3943 // independently on 128-bit lanes.
3944 unsigned NumElts = VT.getVectorNumElements();
3945 unsigned NumLanes = VT.getSizeInBits()/128;
3946 unsigned NumLaneElts = NumElts/NumLanes;
3948 assert((NumLaneElts == 2 || NumLaneElts == 4) &&
3949 "Only supports 2 or 4 elements per lane");
3951 unsigned Shift = (NumLaneElts == 4) ? 1 : 0;
3953 for (unsigned i = 0; i != NumElts; ++i) {
3954 int Elt = N->getMaskElt(i);
3955 if (Elt < 0) continue;
3957 unsigned ShAmt = i << Shift;
3958 if (ShAmt >= 8) ShAmt -= 8;
3959 Mask |= Elt << ShAmt;
3965 /// getShufflePSHUFHWImmediate - Return the appropriate immediate to shuffle
3966 /// the specified VECTOR_SHUFFLE mask with the PSHUFHW instruction.
3967 unsigned X86::getShufflePSHUFHWImmediate(SDNode *N) {
3968 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
3970 // 8 nodes, but we only care about the last 4.
3971 for (unsigned i = 7; i >= 4; --i) {
3972 int Val = SVOp->getMaskElt(i);
3981 /// getShufflePSHUFLWImmediate - Return the appropriate immediate to shuffle
3982 /// the specified VECTOR_SHUFFLE mask with the PSHUFLW instruction.
3983 unsigned X86::getShufflePSHUFLWImmediate(SDNode *N) {
3984 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
3986 // 8 nodes, but we only care about the first 4.
3987 for (int i = 3; i >= 0; --i) {
3988 int Val = SVOp->getMaskElt(i);
3997 /// getShufflePALIGNRImmediate - Return the appropriate immediate to shuffle
3998 /// the specified VECTOR_SHUFFLE mask with the PALIGNR instruction.
3999 static unsigned getShufflePALIGNRImmediate(ShuffleVectorSDNode *SVOp) {
4000 EVT VT = SVOp->getValueType(0);
4001 unsigned EltSize = VT.getVectorElementType().getSizeInBits() >> 3;
4003 unsigned NumElts = VT.getVectorNumElements();
4004 unsigned NumLanes = VT.getSizeInBits()/128;
4005 unsigned NumLaneElts = NumElts/NumLanes;
4009 for (i = 0; i != NumElts; ++i) {
4010 Val = SVOp->getMaskElt(i);
4014 if (Val >= (int)NumElts)
4015 Val -= NumElts - NumLaneElts;
4017 assert(Val - i > 0 && "PALIGNR imm should be positive");
4018 return (Val - i) * EltSize;
4021 /// getExtractVEXTRACTF128Immediate - Return the appropriate immediate
4022 /// to extract the specified EXTRACT_SUBVECTOR index with VEXTRACTF128
4024 unsigned X86::getExtractVEXTRACTF128Immediate(SDNode *N) {
4025 if (!isa<ConstantSDNode>(N->getOperand(1).getNode()))
4026 llvm_unreachable("Illegal extract subvector for VEXTRACTF128");
4029 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
4031 EVT VecVT = N->getOperand(0).getValueType();
4032 EVT ElVT = VecVT.getVectorElementType();
4034 unsigned NumElemsPerChunk = 128 / ElVT.getSizeInBits();
4035 return Index / NumElemsPerChunk;
4038 /// getInsertVINSERTF128Immediate - Return the appropriate immediate
4039 /// to insert at the specified INSERT_SUBVECTOR index with VINSERTF128
4041 unsigned X86::getInsertVINSERTF128Immediate(SDNode *N) {
4042 if (!isa<ConstantSDNode>(N->getOperand(2).getNode()))
4043 llvm_unreachable("Illegal insert subvector for VINSERTF128");
4046 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
4048 EVT VecVT = N->getValueType(0);
4049 EVT ElVT = VecVT.getVectorElementType();
4051 unsigned NumElemsPerChunk = 128 / ElVT.getSizeInBits();
4052 return Index / NumElemsPerChunk;
4055 /// isZeroNode - Returns true if Elt is a constant zero or a floating point
4057 bool X86::isZeroNode(SDValue Elt) {
4058 return ((isa<ConstantSDNode>(Elt) &&
4059 cast<ConstantSDNode>(Elt)->isNullValue()) ||
4060 (isa<ConstantFPSDNode>(Elt) &&
4061 cast<ConstantFPSDNode>(Elt)->getValueAPF().isPosZero()));
4064 /// CommuteVectorShuffle - Swap vector_shuffle operands as well as values in
4065 /// their permute mask.
4066 static SDValue CommuteVectorShuffle(ShuffleVectorSDNode *SVOp,
4067 SelectionDAG &DAG) {
4068 EVT VT = SVOp->getValueType(0);
4069 unsigned NumElems = VT.getVectorNumElements();
4070 SmallVector<int, 8> MaskVec;
4072 for (unsigned i = 0; i != NumElems; ++i) {
4073 int idx = SVOp->getMaskElt(i);
4075 MaskVec.push_back(idx);
4076 else if (idx < (int)NumElems)
4077 MaskVec.push_back(idx + NumElems);
4079 MaskVec.push_back(idx - NumElems);
4081 return DAG.getVectorShuffle(VT, SVOp->getDebugLoc(), SVOp->getOperand(1),
4082 SVOp->getOperand(0), &MaskVec[0]);
4085 /// ShouldXformToMOVHLPS - Return true if the node should be transformed to
4086 /// match movhlps. The lower half elements should come from upper half of
4087 /// V1 (and in order), and the upper half elements should come from the upper
4088 /// half of V2 (and in order).
4089 static bool ShouldXformToMOVHLPS(ShuffleVectorSDNode *Op) {
4090 EVT VT = Op->getValueType(0);
4091 if (VT.getSizeInBits() != 128)
4093 if (VT.getVectorNumElements() != 4)
4095 for (unsigned i = 0, e = 2; i != e; ++i)
4096 if (!isUndefOrEqual(Op->getMaskElt(i), i+2))
4098 for (unsigned i = 2; i != 4; ++i)
4099 if (!isUndefOrEqual(Op->getMaskElt(i), i+4))
4104 /// isScalarLoadToVector - Returns true if the node is a scalar load that
4105 /// is promoted to a vector. It also returns the LoadSDNode by reference if
4107 static bool isScalarLoadToVector(SDNode *N, LoadSDNode **LD = NULL) {
4108 if (N->getOpcode() != ISD::SCALAR_TO_VECTOR)
4110 N = N->getOperand(0).getNode();
4111 if (!ISD::isNON_EXTLoad(N))
4114 *LD = cast<LoadSDNode>(N);
4118 // Test whether the given value is a vector value which will be legalized
4120 static bool WillBeConstantPoolLoad(SDNode *N) {
4121 if (N->getOpcode() != ISD::BUILD_VECTOR)
4124 // Check for any non-constant elements.
4125 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
4126 switch (N->getOperand(i).getNode()->getOpcode()) {
4128 case ISD::ConstantFP:
4135 // Vectors of all-zeros and all-ones are materialized with special
4136 // instructions rather than being loaded.
4137 return !ISD::isBuildVectorAllZeros(N) &&
4138 !ISD::isBuildVectorAllOnes(N);
4141 /// ShouldXformToMOVLP{S|D} - Return true if the node should be transformed to
4142 /// match movlp{s|d}. The lower half elements should come from lower half of
4143 /// V1 (and in order), and the upper half elements should come from the upper
4144 /// half of V2 (and in order). And since V1 will become the source of the
4145 /// MOVLP, it must be either a vector load or a scalar load to vector.
4146 static bool ShouldXformToMOVLP(SDNode *V1, SDNode *V2,
4147 ShuffleVectorSDNode *Op) {
4148 EVT VT = Op->getValueType(0);
4149 if (VT.getSizeInBits() != 128)
4152 if (!ISD::isNON_EXTLoad(V1) && !isScalarLoadToVector(V1))
4154 // Is V2 is a vector load, don't do this transformation. We will try to use
4155 // load folding shufps op.
4156 if (ISD::isNON_EXTLoad(V2) || WillBeConstantPoolLoad(V2))
4159 unsigned NumElems = VT.getVectorNumElements();
4161 if (NumElems != 2 && NumElems != 4)
4163 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
4164 if (!isUndefOrEqual(Op->getMaskElt(i), i))
4166 for (unsigned i = NumElems/2; i != NumElems; ++i)
4167 if (!isUndefOrEqual(Op->getMaskElt(i), i+NumElems))
4172 /// isSplatVector - Returns true if N is a BUILD_VECTOR node whose elements are
4174 static bool isSplatVector(SDNode *N) {
4175 if (N->getOpcode() != ISD::BUILD_VECTOR)
4178 SDValue SplatValue = N->getOperand(0);
4179 for (unsigned i = 1, e = N->getNumOperands(); i != e; ++i)
4180 if (N->getOperand(i) != SplatValue)
4185 /// isZeroShuffle - Returns true if N is a VECTOR_SHUFFLE that can be resolved
4186 /// to an zero vector.
4187 /// FIXME: move to dag combiner / method on ShuffleVectorSDNode
4188 static bool isZeroShuffle(ShuffleVectorSDNode *N) {
4189 SDValue V1 = N->getOperand(0);
4190 SDValue V2 = N->getOperand(1);
4191 unsigned NumElems = N->getValueType(0).getVectorNumElements();
4192 for (unsigned i = 0; i != NumElems; ++i) {
4193 int Idx = N->getMaskElt(i);
4194 if (Idx >= (int)NumElems) {
4195 unsigned Opc = V2.getOpcode();
4196 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V2.getNode()))
4198 if (Opc != ISD::BUILD_VECTOR ||
4199 !X86::isZeroNode(V2.getOperand(Idx-NumElems)))
4201 } else if (Idx >= 0) {
4202 unsigned Opc = V1.getOpcode();
4203 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V1.getNode()))
4205 if (Opc != ISD::BUILD_VECTOR ||
4206 !X86::isZeroNode(V1.getOperand(Idx)))
4213 /// getZeroVector - Returns a vector of specified type with all zero elements.
4215 static SDValue getZeroVector(EVT VT, const X86Subtarget *Subtarget,
4216 SelectionDAG &DAG, DebugLoc dl) {
4217 assert(VT.isVector() && "Expected a vector type");
4219 // Always build SSE zero vectors as <4 x i32> bitcasted
4220 // to their dest type. This ensures they get CSE'd.
4222 if (VT.getSizeInBits() == 128) { // SSE
4223 if (Subtarget->hasSSE2()) { // SSE2
4224 SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
4225 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4227 SDValue Cst = DAG.getTargetConstantFP(+0.0, MVT::f32);
4228 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4f32, Cst, Cst, Cst, Cst);
4230 } else if (VT.getSizeInBits() == 256) { // AVX
4231 if (Subtarget->hasAVX2()) { // AVX2
4232 SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
4233 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4234 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops, 8);
4236 // 256-bit logic and arithmetic instructions in AVX are all
4237 // floating-point, no support for integer ops. Emit fp zeroed vectors.
4238 SDValue Cst = DAG.getTargetConstantFP(+0.0, MVT::f32);
4239 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4240 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8f32, Ops, 8);
4243 return DAG.getNode(ISD::BITCAST, dl, VT, Vec);
4246 /// getOnesVector - Returns a vector of specified type with all bits set.
4247 /// Always build ones vectors as <4 x i32> or <8 x i32>. For 256-bit types with
4248 /// no AVX2 supprt, use two <4 x i32> inserted in a <8 x i32> appropriately.
4249 /// Then bitcast to their original type, ensuring they get CSE'd.
4250 static SDValue getOnesVector(EVT VT, bool HasAVX2, SelectionDAG &DAG,
4252 assert(VT.isVector() && "Expected a vector type");
4253 assert((VT.is128BitVector() || VT.is256BitVector())
4254 && "Expected a 128-bit or 256-bit vector type");
4256 SDValue Cst = DAG.getTargetConstant(~0U, MVT::i32);
4258 if (VT.getSizeInBits() == 256) {
4259 if (HasAVX2) { // AVX2
4260 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4261 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops, 8);
4263 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4264 SDValue InsV = Insert128BitVector(DAG.getNode(ISD::UNDEF, dl, MVT::v8i32),
4265 Vec, DAG.getConstant(0, MVT::i32), DAG, dl);
4266 Vec = Insert128BitVector(InsV, Vec,
4267 DAG.getConstant(4 /* NumElems/2 */, MVT::i32), DAG, dl);
4270 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4273 return DAG.getNode(ISD::BITCAST, dl, VT, Vec);
4276 /// NormalizeMask - V2 is a splat, modify the mask (if needed) so all elements
4277 /// that point to V2 points to its first element.
4278 static SDValue NormalizeMask(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
4279 EVT VT = SVOp->getValueType(0);
4280 unsigned NumElems = VT.getVectorNumElements();
4282 bool Changed = false;
4283 SmallVector<int, 8> MaskVec(SVOp->getMask().begin(), SVOp->getMask().end());
4285 for (unsigned i = 0; i != NumElems; ++i) {
4286 if (MaskVec[i] > (int)NumElems) {
4287 MaskVec[i] = NumElems;
4292 return DAG.getVectorShuffle(VT, SVOp->getDebugLoc(), SVOp->getOperand(0),
4293 SVOp->getOperand(1), &MaskVec[0]);
4294 return SDValue(SVOp, 0);
4297 /// getMOVLMask - Returns a vector_shuffle mask for an movs{s|d}, movd
4298 /// operation of specified width.
4299 static SDValue getMOVL(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1,
4301 unsigned NumElems = VT.getVectorNumElements();
4302 SmallVector<int, 8> Mask;
4303 Mask.push_back(NumElems);
4304 for (unsigned i = 1; i != NumElems; ++i)
4306 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
4309 /// getUnpackl - Returns a vector_shuffle node for an unpackl operation.
4310 static SDValue getUnpackl(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1,
4312 unsigned NumElems = VT.getVectorNumElements();
4313 SmallVector<int, 8> Mask;
4314 for (unsigned i = 0, e = NumElems/2; i != e; ++i) {
4316 Mask.push_back(i + NumElems);
4318 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
4321 /// getUnpackh - Returns a vector_shuffle node for an unpackh operation.
4322 static SDValue getUnpackh(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1,
4324 unsigned NumElems = VT.getVectorNumElements();
4325 unsigned Half = NumElems/2;
4326 SmallVector<int, 8> Mask;
4327 for (unsigned i = 0; i != Half; ++i) {
4328 Mask.push_back(i + Half);
4329 Mask.push_back(i + NumElems + Half);
4331 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
4334 // PromoteSplati8i16 - All i16 and i8 vector types can't be used directly by
4335 // a generic shuffle instruction because the target has no such instructions.
4336 // Generate shuffles which repeat i16 and i8 several times until they can be
4337 // represented by v4f32 and then be manipulated by target suported shuffles.
4338 static SDValue PromoteSplati8i16(SDValue V, SelectionDAG &DAG, int &EltNo) {
4339 EVT VT = V.getValueType();
4340 int NumElems = VT.getVectorNumElements();
4341 DebugLoc dl = V.getDebugLoc();
4343 while (NumElems > 4) {
4344 if (EltNo < NumElems/2) {
4345 V = getUnpackl(DAG, dl, VT, V, V);
4347 V = getUnpackh(DAG, dl, VT, V, V);
4348 EltNo -= NumElems/2;
4355 /// getLegalSplat - Generate a legal splat with supported x86 shuffles
4356 static SDValue getLegalSplat(SelectionDAG &DAG, SDValue V, int EltNo) {
4357 EVT VT = V.getValueType();
4358 DebugLoc dl = V.getDebugLoc();
4359 assert((VT.getSizeInBits() == 128 || VT.getSizeInBits() == 256)
4360 && "Vector size not supported");
4362 if (VT.getSizeInBits() == 128) {
4363 V = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V);
4364 int SplatMask[4] = { EltNo, EltNo, EltNo, EltNo };
4365 V = DAG.getVectorShuffle(MVT::v4f32, dl, V, DAG.getUNDEF(MVT::v4f32),
4368 // To use VPERMILPS to splat scalars, the second half of indicies must
4369 // refer to the higher part, which is a duplication of the lower one,
4370 // because VPERMILPS can only handle in-lane permutations.
4371 int SplatMask[8] = { EltNo, EltNo, EltNo, EltNo,
4372 EltNo+4, EltNo+4, EltNo+4, EltNo+4 };
4374 V = DAG.getNode(ISD::BITCAST, dl, MVT::v8f32, V);
4375 V = DAG.getVectorShuffle(MVT::v8f32, dl, V, DAG.getUNDEF(MVT::v8f32),
4379 return DAG.getNode(ISD::BITCAST, dl, VT, V);
4382 /// PromoteSplat - Splat is promoted to target supported vector shuffles.
4383 static SDValue PromoteSplat(ShuffleVectorSDNode *SV, SelectionDAG &DAG) {
4384 EVT SrcVT = SV->getValueType(0);
4385 SDValue V1 = SV->getOperand(0);
4386 DebugLoc dl = SV->getDebugLoc();
4388 int EltNo = SV->getSplatIndex();
4389 int NumElems = SrcVT.getVectorNumElements();
4390 unsigned Size = SrcVT.getSizeInBits();
4392 assert(((Size == 128 && NumElems > 4) || Size == 256) &&
4393 "Unknown how to promote splat for type");
4395 // Extract the 128-bit part containing the splat element and update
4396 // the splat element index when it refers to the higher register.
4398 unsigned Idx = (EltNo >= NumElems/2) ? NumElems/2 : 0;
4399 V1 = Extract128BitVector(V1, DAG.getConstant(Idx, MVT::i32), DAG, dl);
4401 EltNo -= NumElems/2;
4404 // All i16 and i8 vector types can't be used directly by a generic shuffle
4405 // instruction because the target has no such instruction. Generate shuffles
4406 // which repeat i16 and i8 several times until they fit in i32, and then can
4407 // be manipulated by target suported shuffles.
4408 EVT EltVT = SrcVT.getVectorElementType();
4409 if (EltVT == MVT::i8 || EltVT == MVT::i16)
4410 V1 = PromoteSplati8i16(V1, DAG, EltNo);
4412 // Recreate the 256-bit vector and place the same 128-bit vector
4413 // into the low and high part. This is necessary because we want
4414 // to use VPERM* to shuffle the vectors
4416 SDValue InsV = Insert128BitVector(DAG.getUNDEF(SrcVT), V1,
4417 DAG.getConstant(0, MVT::i32), DAG, dl);
4418 V1 = Insert128BitVector(InsV, V1,
4419 DAG.getConstant(NumElems/2, MVT::i32), DAG, dl);
4422 return getLegalSplat(DAG, V1, EltNo);
4425 /// getShuffleVectorZeroOrUndef - Return a vector_shuffle of the specified
4426 /// vector of zero or undef vector. This produces a shuffle where the low
4427 /// element of V2 is swizzled into the zero/undef vector, landing at element
4428 /// Idx. This produces a shuffle mask like 4,1,2,3 (idx=0) or 0,1,2,4 (idx=3).
4429 static SDValue getShuffleVectorZeroOrUndef(SDValue V2, unsigned Idx,
4431 const X86Subtarget *Subtarget,
4432 SelectionDAG &DAG) {
4433 EVT VT = V2.getValueType();
4435 ? getZeroVector(VT, Subtarget, DAG, V2.getDebugLoc()) : DAG.getUNDEF(VT);
4436 unsigned NumElems = VT.getVectorNumElements();
4437 SmallVector<int, 16> MaskVec;
4438 for (unsigned i = 0; i != NumElems; ++i)
4439 // If this is the insertion idx, put the low elt of V2 here.
4440 MaskVec.push_back(i == Idx ? NumElems : i);
4441 return DAG.getVectorShuffle(VT, V2.getDebugLoc(), V1, V2, &MaskVec[0]);
4444 /// getShuffleScalarElt - Returns the scalar element that will make up the ith
4445 /// element of the result of the vector shuffle.
4446 static SDValue getShuffleScalarElt(SDNode *N, int Index, SelectionDAG &DAG,
4449 return SDValue(); // Limit search depth.
4451 SDValue V = SDValue(N, 0);
4452 EVT VT = V.getValueType();
4453 unsigned Opcode = V.getOpcode();
4455 // Recurse into ISD::VECTOR_SHUFFLE node to find scalars.
4456 if (const ShuffleVectorSDNode *SV = dyn_cast<ShuffleVectorSDNode>(N)) {
4457 Index = SV->getMaskElt(Index);
4460 return DAG.getUNDEF(VT.getVectorElementType());
4462 int NumElems = VT.getVectorNumElements();
4463 SDValue NewV = (Index < NumElems) ? SV->getOperand(0) : SV->getOperand(1);
4464 return getShuffleScalarElt(NewV.getNode(), Index % NumElems, DAG, Depth+1);
4467 // Recurse into target specific vector shuffles to find scalars.
4468 if (isTargetShuffle(Opcode)) {
4469 int NumElems = VT.getVectorNumElements();
4470 SmallVector<unsigned, 16> ShuffleMask;
4475 ImmN = N->getOperand(N->getNumOperands()-1);
4476 DecodeSHUFPMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(),
4479 case X86ISD::UNPCKH:
4480 DecodeUNPCKHMask(VT, ShuffleMask);
4482 case X86ISD::UNPCKL:
4483 DecodeUNPCKLMask(VT, ShuffleMask);
4485 case X86ISD::MOVHLPS:
4486 DecodeMOVHLPSMask(NumElems, ShuffleMask);
4488 case X86ISD::MOVLHPS:
4489 DecodeMOVLHPSMask(NumElems, ShuffleMask);
4491 case X86ISD::PSHUFD:
4492 ImmN = N->getOperand(N->getNumOperands()-1);
4493 DecodePSHUFMask(NumElems,
4494 cast<ConstantSDNode>(ImmN)->getZExtValue(),
4497 case X86ISD::PSHUFHW:
4498 ImmN = N->getOperand(N->getNumOperands()-1);
4499 DecodePSHUFHWMask(cast<ConstantSDNode>(ImmN)->getZExtValue(),
4502 case X86ISD::PSHUFLW:
4503 ImmN = N->getOperand(N->getNumOperands()-1);
4504 DecodePSHUFLWMask(cast<ConstantSDNode>(ImmN)->getZExtValue(),
4508 case X86ISD::MOVSD: {
4509 // The index 0 always comes from the first element of the second source,
4510 // this is why MOVSS and MOVSD are used in the first place. The other
4511 // elements come from the other positions of the first source vector.
4512 unsigned OpNum = (Index == 0) ? 1 : 0;
4513 return getShuffleScalarElt(V.getOperand(OpNum).getNode(), Index, DAG,
4516 case X86ISD::VPERMILP:
4517 ImmN = N->getOperand(N->getNumOperands()-1);
4518 DecodeVPERMILPMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(),
4521 case X86ISD::VPERM2X128:
4522 ImmN = N->getOperand(N->getNumOperands()-1);
4523 DecodeVPERM2F128Mask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(),
4526 case X86ISD::MOVDDUP:
4527 case X86ISD::MOVLHPD:
4528 case X86ISD::MOVLPD:
4529 case X86ISD::MOVLPS:
4530 case X86ISD::MOVSHDUP:
4531 case X86ISD::MOVSLDUP:
4532 case X86ISD::PALIGN:
4533 return SDValue(); // Not yet implemented.
4535 assert(0 && "unknown target shuffle node");
4539 Index = ShuffleMask[Index];
4541 return DAG.getUNDEF(VT.getVectorElementType());
4543 SDValue NewV = (Index < NumElems) ? N->getOperand(0) : N->getOperand(1);
4544 return getShuffleScalarElt(NewV.getNode(), Index % NumElems, DAG,
4548 // Actual nodes that may contain scalar elements
4549 if (Opcode == ISD::BITCAST) {
4550 V = V.getOperand(0);
4551 EVT SrcVT = V.getValueType();
4552 unsigned NumElems = VT.getVectorNumElements();
4554 if (!SrcVT.isVector() || SrcVT.getVectorNumElements() != NumElems)
4558 if (V.getOpcode() == ISD::SCALAR_TO_VECTOR)
4559 return (Index == 0) ? V.getOperand(0)
4560 : DAG.getUNDEF(VT.getVectorElementType());
4562 if (V.getOpcode() == ISD::BUILD_VECTOR)
4563 return V.getOperand(Index);
4568 /// getNumOfConsecutiveZeros - Return the number of elements of a vector
4569 /// shuffle operation which come from a consecutively from a zero. The
4570 /// search can start in two different directions, from left or right.
4572 unsigned getNumOfConsecutiveZeros(SDNode *N, int NumElems,
4573 bool ZerosFromLeft, SelectionDAG &DAG) {
4576 while (i < NumElems) {
4577 unsigned Index = ZerosFromLeft ? i : NumElems-i-1;
4578 SDValue Elt = getShuffleScalarElt(N, Index, DAG, 0);
4579 if (!(Elt.getNode() &&
4580 (Elt.getOpcode() == ISD::UNDEF || X86::isZeroNode(Elt))))
4588 /// isShuffleMaskConsecutive - Check if the shuffle mask indicies from MaskI to
4589 /// MaskE correspond consecutively to elements from one of the vector operands,
4590 /// starting from its index OpIdx. Also tell OpNum which source vector operand.
4592 bool isShuffleMaskConsecutive(ShuffleVectorSDNode *SVOp, int MaskI, int MaskE,
4593 int OpIdx, int NumElems, unsigned &OpNum) {
4594 bool SeenV1 = false;
4595 bool SeenV2 = false;
4597 for (int i = MaskI; i <= MaskE; ++i, ++OpIdx) {
4598 int Idx = SVOp->getMaskElt(i);
4599 // Ignore undef indicies
4608 // Only accept consecutive elements from the same vector
4609 if ((Idx % NumElems != OpIdx) || (SeenV1 && SeenV2))
4613 OpNum = SeenV1 ? 0 : 1;
4617 /// isVectorShiftRight - Returns true if the shuffle can be implemented as a
4618 /// logical left shift of a vector.
4619 static bool isVectorShiftRight(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
4620 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
4621 unsigned NumElems = SVOp->getValueType(0).getVectorNumElements();
4622 unsigned NumZeros = getNumOfConsecutiveZeros(SVOp, NumElems,
4623 false /* check zeros from right */, DAG);
4629 // Considering the elements in the mask that are not consecutive zeros,
4630 // check if they consecutively come from only one of the source vectors.
4632 // V1 = {X, A, B, C} 0
4634 // vector_shuffle V1, V2 <1, 2, 3, X>
4636 if (!isShuffleMaskConsecutive(SVOp,
4637 0, // Mask Start Index
4638 NumElems-NumZeros-1, // Mask End Index
4639 NumZeros, // Where to start looking in the src vector
4640 NumElems, // Number of elements in vector
4641 OpSrc)) // Which source operand ?
4646 ShVal = SVOp->getOperand(OpSrc);
4650 /// isVectorShiftLeft - Returns true if the shuffle can be implemented as a
4651 /// logical left shift of a vector.
4652 static bool isVectorShiftLeft(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
4653 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
4654 unsigned NumElems = SVOp->getValueType(0).getVectorNumElements();
4655 unsigned NumZeros = getNumOfConsecutiveZeros(SVOp, NumElems,
4656 true /* check zeros from left */, DAG);
4662 // Considering the elements in the mask that are not consecutive zeros,
4663 // check if they consecutively come from only one of the source vectors.
4665 // 0 { A, B, X, X } = V2
4667 // vector_shuffle V1, V2 <X, X, 4, 5>
4669 if (!isShuffleMaskConsecutive(SVOp,
4670 NumZeros, // Mask Start Index
4671 NumElems-1, // Mask End Index
4672 0, // Where to start looking in the src vector
4673 NumElems, // Number of elements in vector
4674 OpSrc)) // Which source operand ?
4679 ShVal = SVOp->getOperand(OpSrc);
4683 /// isVectorShift - Returns true if the shuffle can be implemented as a
4684 /// logical left or right shift of a vector.
4685 static bool isVectorShift(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
4686 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
4687 // Although the logic below support any bitwidth size, there are no
4688 // shift instructions which handle more than 128-bit vectors.
4689 if (SVOp->getValueType(0).getSizeInBits() > 128)
4692 if (isVectorShiftLeft(SVOp, DAG, isLeft, ShVal, ShAmt) ||
4693 isVectorShiftRight(SVOp, DAG, isLeft, ShVal, ShAmt))
4699 /// LowerBuildVectorv16i8 - Custom lower build_vector of v16i8.
4701 static SDValue LowerBuildVectorv16i8(SDValue Op, unsigned NonZeros,
4702 unsigned NumNonZero, unsigned NumZero,
4704 const X86Subtarget* Subtarget,
4705 const TargetLowering &TLI) {
4709 DebugLoc dl = Op.getDebugLoc();
4712 for (unsigned i = 0; i < 16; ++i) {
4713 bool ThisIsNonZero = (NonZeros & (1 << i)) != 0;
4714 if (ThisIsNonZero && First) {
4716 V = getZeroVector(MVT::v8i16, Subtarget, DAG, dl);
4718 V = DAG.getUNDEF(MVT::v8i16);
4723 SDValue ThisElt(0, 0), LastElt(0, 0);
4724 bool LastIsNonZero = (NonZeros & (1 << (i-1))) != 0;
4725 if (LastIsNonZero) {
4726 LastElt = DAG.getNode(ISD::ZERO_EXTEND, dl,
4727 MVT::i16, Op.getOperand(i-1));
4729 if (ThisIsNonZero) {
4730 ThisElt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, Op.getOperand(i));
4731 ThisElt = DAG.getNode(ISD::SHL, dl, MVT::i16,
4732 ThisElt, DAG.getConstant(8, MVT::i8));
4734 ThisElt = DAG.getNode(ISD::OR, dl, MVT::i16, ThisElt, LastElt);
4738 if (ThisElt.getNode())
4739 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, V, ThisElt,
4740 DAG.getIntPtrConstant(i/2));
4744 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V);
4747 /// LowerBuildVectorv8i16 - Custom lower build_vector of v8i16.
4749 static SDValue LowerBuildVectorv8i16(SDValue Op, unsigned NonZeros,
4750 unsigned NumNonZero, unsigned NumZero,
4752 const X86Subtarget* Subtarget,
4753 const TargetLowering &TLI) {
4757 DebugLoc dl = Op.getDebugLoc();
4760 for (unsigned i = 0; i < 8; ++i) {
4761 bool isNonZero = (NonZeros & (1 << i)) != 0;
4765 V = getZeroVector(MVT::v8i16, Subtarget, DAG, dl);
4767 V = DAG.getUNDEF(MVT::v8i16);
4770 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl,
4771 MVT::v8i16, V, Op.getOperand(i),
4772 DAG.getIntPtrConstant(i));
4779 /// getVShift - Return a vector logical shift node.
4781 static SDValue getVShift(bool isLeft, EVT VT, SDValue SrcOp,
4782 unsigned NumBits, SelectionDAG &DAG,
4783 const TargetLowering &TLI, DebugLoc dl) {
4784 assert(VT.getSizeInBits() == 128 && "Unknown type for VShift");
4785 EVT ShVT = MVT::v2i64;
4786 unsigned Opc = isLeft ? X86ISD::VSHLDQ : X86ISD::VSRLDQ;
4787 SrcOp = DAG.getNode(ISD::BITCAST, dl, ShVT, SrcOp);
4788 return DAG.getNode(ISD::BITCAST, dl, VT,
4789 DAG.getNode(Opc, dl, ShVT, SrcOp,
4790 DAG.getConstant(NumBits,
4791 TLI.getShiftAmountTy(SrcOp.getValueType()))));
4795 X86TargetLowering::LowerAsSplatVectorLoad(SDValue SrcOp, EVT VT, DebugLoc dl,
4796 SelectionDAG &DAG) const {
4798 // Check if the scalar load can be widened into a vector load. And if
4799 // the address is "base + cst" see if the cst can be "absorbed" into
4800 // the shuffle mask.
4801 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(SrcOp)) {
4802 SDValue Ptr = LD->getBasePtr();
4803 if (!ISD::isNormalLoad(LD) || LD->isVolatile())
4805 EVT PVT = LD->getValueType(0);
4806 if (PVT != MVT::i32 && PVT != MVT::f32)
4811 if (FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr)) {
4812 FI = FINode->getIndex();
4814 } else if (DAG.isBaseWithConstantOffset(Ptr) &&
4815 isa<FrameIndexSDNode>(Ptr.getOperand(0))) {
4816 FI = cast<FrameIndexSDNode>(Ptr.getOperand(0))->getIndex();
4817 Offset = Ptr.getConstantOperandVal(1);
4818 Ptr = Ptr.getOperand(0);
4823 // FIXME: 256-bit vector instructions don't require a strict alignment,
4824 // improve this code to support it better.
4825 unsigned RequiredAlign = VT.getSizeInBits()/8;
4826 SDValue Chain = LD->getChain();
4827 // Make sure the stack object alignment is at least 16 or 32.
4828 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
4829 if (DAG.InferPtrAlignment(Ptr) < RequiredAlign) {
4830 if (MFI->isFixedObjectIndex(FI)) {
4831 // Can't change the alignment. FIXME: It's possible to compute
4832 // the exact stack offset and reference FI + adjust offset instead.
4833 // If someone *really* cares about this. That's the way to implement it.
4836 MFI->setObjectAlignment(FI, RequiredAlign);
4840 // (Offset % 16 or 32) must be multiple of 4. Then address is then
4841 // Ptr + (Offset & ~15).
4844 if ((Offset % RequiredAlign) & 3)
4846 int64_t StartOffset = Offset & ~(RequiredAlign-1);
4848 Ptr = DAG.getNode(ISD::ADD, Ptr.getDebugLoc(), Ptr.getValueType(),
4849 Ptr,DAG.getConstant(StartOffset, Ptr.getValueType()));
4851 int EltNo = (Offset - StartOffset) >> 2;
4852 int NumElems = VT.getVectorNumElements();
4854 EVT NVT = EVT::getVectorVT(*DAG.getContext(), PVT, NumElems);
4855 SDValue V1 = DAG.getLoad(NVT, dl, Chain, Ptr,
4856 LD->getPointerInfo().getWithOffset(StartOffset),
4857 false, false, false, 0);
4859 SmallVector<int, 8> Mask;
4860 for (int i = 0; i < NumElems; ++i)
4861 Mask.push_back(EltNo);
4863 return DAG.getVectorShuffle(NVT, dl, V1, DAG.getUNDEF(NVT), &Mask[0]);
4869 /// EltsFromConsecutiveLoads - Given the initializing elements 'Elts' of a
4870 /// vector of type 'VT', see if the elements can be replaced by a single large
4871 /// load which has the same value as a build_vector whose operands are 'elts'.
4873 /// Example: <load i32 *a, load i32 *a+4, undef, undef> -> zextload a
4875 /// FIXME: we'd also like to handle the case where the last elements are zero
4876 /// rather than undef via VZEXT_LOAD, but we do not detect that case today.
4877 /// There's even a handy isZeroNode for that purpose.
4878 static SDValue EltsFromConsecutiveLoads(EVT VT, SmallVectorImpl<SDValue> &Elts,
4879 DebugLoc &DL, SelectionDAG &DAG) {
4880 EVT EltVT = VT.getVectorElementType();
4881 unsigned NumElems = Elts.size();
4883 LoadSDNode *LDBase = NULL;
4884 unsigned LastLoadedElt = -1U;
4886 // For each element in the initializer, see if we've found a load or an undef.
4887 // If we don't find an initial load element, or later load elements are
4888 // non-consecutive, bail out.
4889 for (unsigned i = 0; i < NumElems; ++i) {
4890 SDValue Elt = Elts[i];
4892 if (!Elt.getNode() ||
4893 (Elt.getOpcode() != ISD::UNDEF && !ISD::isNON_EXTLoad(Elt.getNode())))
4896 if (Elt.getNode()->getOpcode() == ISD::UNDEF)
4898 LDBase = cast<LoadSDNode>(Elt.getNode());
4902 if (Elt.getOpcode() == ISD::UNDEF)
4905 LoadSDNode *LD = cast<LoadSDNode>(Elt);
4906 if (!DAG.isConsecutiveLoad(LD, LDBase, EltVT.getSizeInBits()/8, i))
4911 // If we have found an entire vector of loads and undefs, then return a large
4912 // load of the entire vector width starting at the base pointer. If we found
4913 // consecutive loads for the low half, generate a vzext_load node.
4914 if (LastLoadedElt == NumElems - 1) {
4915 if (DAG.InferPtrAlignment(LDBase->getBasePtr()) >= 16)
4916 return DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(),
4917 LDBase->getPointerInfo(),
4918 LDBase->isVolatile(), LDBase->isNonTemporal(),
4919 LDBase->isInvariant(), 0);
4920 return DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(),
4921 LDBase->getPointerInfo(),
4922 LDBase->isVolatile(), LDBase->isNonTemporal(),
4923 LDBase->isInvariant(), LDBase->getAlignment());
4924 } else if (NumElems == 4 && LastLoadedElt == 1 &&
4925 DAG.getTargetLoweringInfo().isTypeLegal(MVT::v2i64)) {
4926 SDVTList Tys = DAG.getVTList(MVT::v2i64, MVT::Other);
4927 SDValue Ops[] = { LDBase->getChain(), LDBase->getBasePtr() };
4929 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, DL, Tys, Ops, 2, MVT::i64,
4930 LDBase->getPointerInfo(),
4931 LDBase->getAlignment(),
4932 false/*isVolatile*/, true/*ReadMem*/,
4934 return DAG.getNode(ISD::BITCAST, DL, VT, ResNode);
4939 /// isVectorBroadcast - Check if the node chain is suitable to be xformed to
4940 /// a vbroadcast node. We support two patterns:
4941 /// 1. A splat BUILD_VECTOR which uses a single scalar load.
4942 /// 2. A splat shuffle which uses a scalar_to_vector node which comes from
4944 /// The scalar load node is returned when a pattern is found,
4945 /// or SDValue() otherwise.
4946 static SDValue isVectorBroadcast(SDValue &Op, const X86Subtarget *Subtarget) {
4947 if (!Subtarget->hasAVX())
4950 EVT VT = Op.getValueType();
4953 if (V.hasOneUse() && V.getOpcode() == ISD::BITCAST)
4954 V = V.getOperand(0);
4956 //A suspected load to be broadcasted.
4959 switch (V.getOpcode()) {
4961 // Unknown pattern found.
4964 case ISD::BUILD_VECTOR: {
4965 // The BUILD_VECTOR node must be a splat.
4966 if (!isSplatVector(V.getNode()))
4969 Ld = V.getOperand(0);
4971 // The suspected load node has several users. Make sure that all
4972 // of its users are from the BUILD_VECTOR node.
4973 if (!Ld->hasNUsesOfValue(VT.getVectorNumElements(), 0))
4978 case ISD::VECTOR_SHUFFLE: {
4979 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
4981 // Shuffles must have a splat mask where the first element is
4983 if ((!SVOp->isSplat()) || SVOp->getMaskElt(0) != 0)
4986 SDValue Sc = Op.getOperand(0);
4987 if (Sc.getOpcode() != ISD::SCALAR_TO_VECTOR)
4990 Ld = Sc.getOperand(0);
4992 // The scalar_to_vector node and the suspected
4993 // load node must have exactly one user.
4994 if (!Sc.hasOneUse() || !Ld.hasOneUse())
5000 // The scalar source must be a normal load.
5001 if (!ISD::isNormalLoad(Ld.getNode()))
5004 // Reject loads that have uses of the chain result
5005 if (Ld->hasAnyUseOfValue(1))
5008 bool Is256 = VT.getSizeInBits() == 256;
5009 bool Is128 = VT.getSizeInBits() == 128;
5010 unsigned ScalarSize = Ld.getValueType().getSizeInBits();
5012 // VBroadcast to YMM
5013 if (Is256 && (ScalarSize == 32 || ScalarSize == 64))
5016 // VBroadcast to XMM
5017 if (Is128 && (ScalarSize == 32))
5020 // The integer check is needed for the 64-bit into 128-bit so it doesn't match
5021 // double since there is vbroadcastsd xmm
5022 if (Subtarget->hasAVX2() && Ld.getValueType().isInteger()) {
5023 // VBroadcast to YMM
5024 if (Is256 && (ScalarSize == 8 || ScalarSize == 16))
5027 // VBroadcast to XMM
5028 if (Is128 && (ScalarSize == 8 || ScalarSize == 16 || ScalarSize == 64))
5032 // Unsupported broadcast.
5037 X86TargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const {
5038 DebugLoc dl = Op.getDebugLoc();
5040 EVT VT = Op.getValueType();
5041 EVT ExtVT = VT.getVectorElementType();
5042 unsigned NumElems = Op.getNumOperands();
5044 // Vectors containing all zeros can be matched by pxor and xorps later
5045 if (ISD::isBuildVectorAllZeros(Op.getNode())) {
5046 // Canonicalize this to <4 x i32> to 1) ensure the zero vectors are CSE'd
5047 // and 2) ensure that i64 scalars are eliminated on x86-32 hosts.
5048 if (VT == MVT::v4i32 || VT == MVT::v8i32)
5051 return getZeroVector(VT, Subtarget, DAG, dl);
5054 // Vectors containing all ones can be matched by pcmpeqd on 128-bit width
5055 // vectors or broken into v4i32 operations on 256-bit vectors. AVX2 can use
5056 // vpcmpeqd on 256-bit vectors.
5057 if (ISD::isBuildVectorAllOnes(Op.getNode())) {
5058 if (VT == MVT::v4i32 || (VT == MVT::v8i32 && Subtarget->hasAVX2()))
5061 return getOnesVector(VT, Subtarget->hasAVX2(), DAG, dl);
5064 SDValue LD = isVectorBroadcast(Op, Subtarget);
5066 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, LD);
5068 unsigned EVTBits = ExtVT.getSizeInBits();
5070 unsigned NumZero = 0;
5071 unsigned NumNonZero = 0;
5072 unsigned NonZeros = 0;
5073 bool IsAllConstants = true;
5074 SmallSet<SDValue, 8> Values;
5075 for (unsigned i = 0; i < NumElems; ++i) {
5076 SDValue Elt = Op.getOperand(i);
5077 if (Elt.getOpcode() == ISD::UNDEF)
5080 if (Elt.getOpcode() != ISD::Constant &&
5081 Elt.getOpcode() != ISD::ConstantFP)
5082 IsAllConstants = false;
5083 if (X86::isZeroNode(Elt))
5086 NonZeros |= (1 << i);
5091 // All undef vector. Return an UNDEF. All zero vectors were handled above.
5092 if (NumNonZero == 0)
5093 return DAG.getUNDEF(VT);
5095 // Special case for single non-zero, non-undef, element.
5096 if (NumNonZero == 1) {
5097 unsigned Idx = CountTrailingZeros_32(NonZeros);
5098 SDValue Item = Op.getOperand(Idx);
5100 // If this is an insertion of an i64 value on x86-32, and if the top bits of
5101 // the value are obviously zero, truncate the value to i32 and do the
5102 // insertion that way. Only do this if the value is non-constant or if the
5103 // value is a constant being inserted into element 0. It is cheaper to do
5104 // a constant pool load than it is to do a movd + shuffle.
5105 if (ExtVT == MVT::i64 && !Subtarget->is64Bit() &&
5106 (!IsAllConstants || Idx == 0)) {
5107 if (DAG.MaskedValueIsZero(Item, APInt::getBitsSet(64, 32, 64))) {
5109 assert(VT == MVT::v2i64 && "Expected an SSE value type!");
5110 EVT VecVT = MVT::v4i32;
5111 unsigned VecElts = 4;
5113 // Truncate the value (which may itself be a constant) to i32, and
5114 // convert it to a vector with movd (S2V+shuffle to zero extend).
5115 Item = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Item);
5116 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Item);
5117 Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
5119 // Now we have our 32-bit value zero extended in the low element of
5120 // a vector. If Idx != 0, swizzle it into place.
5122 SmallVector<int, 4> Mask;
5123 Mask.push_back(Idx);
5124 for (unsigned i = 1; i != VecElts; ++i)
5126 Item = DAG.getVectorShuffle(VecVT, dl, Item,
5127 DAG.getUNDEF(Item.getValueType()),
5130 return DAG.getNode(ISD::BITCAST, dl, VT, Item);
5134 // If we have a constant or non-constant insertion into the low element of
5135 // a vector, we can do this with SCALAR_TO_VECTOR + shuffle of zero into
5136 // the rest of the elements. This will be matched as movd/movq/movss/movsd
5137 // depending on what the source datatype is.
5140 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
5142 if (ExtVT == MVT::i32 || ExtVT == MVT::f32 || ExtVT == MVT::f64 ||
5143 (ExtVT == MVT::i64 && Subtarget->is64Bit())) {
5144 if (VT.getSizeInBits() == 256) {
5145 SDValue ZeroVec = getZeroVector(VT, Subtarget, DAG, dl);
5146 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, ZeroVec,
5147 Item, DAG.getIntPtrConstant(0));
5149 assert(VT.getSizeInBits() == 128 && "Expected an SSE value type!");
5150 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
5151 // Turn it into a MOVL (i.e. movss, movsd, or movd) to a zero vector.
5152 return getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
5155 if (ExtVT == MVT::i16 || ExtVT == MVT::i8) {
5156 Item = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Item);
5157 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, Item);
5158 if (VT.getSizeInBits() == 256) {
5159 SDValue ZeroVec = getZeroVector(MVT::v8i32, Subtarget, DAG, dl);
5160 Item = Insert128BitVector(ZeroVec, Item, DAG.getConstant(0, MVT::i32),
5163 assert(VT.getSizeInBits() == 128 && "Expected an SSE value type!");
5164 Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
5166 return DAG.getNode(ISD::BITCAST, dl, VT, Item);
5170 // Is it a vector logical left shift?
5171 if (NumElems == 2 && Idx == 1 &&
5172 X86::isZeroNode(Op.getOperand(0)) &&
5173 !X86::isZeroNode(Op.getOperand(1))) {
5174 unsigned NumBits = VT.getSizeInBits();
5175 return getVShift(true, VT,
5176 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
5177 VT, Op.getOperand(1)),
5178 NumBits/2, DAG, *this, dl);
5181 if (IsAllConstants) // Otherwise, it's better to do a constpool load.
5184 // Otherwise, if this is a vector with i32 or f32 elements, and the element
5185 // is a non-constant being inserted into an element other than the low one,
5186 // we can't use a constant pool load. Instead, use SCALAR_TO_VECTOR (aka
5187 // movd/movss) to move this into the low element, then shuffle it into
5189 if (EVTBits == 32) {
5190 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
5192 // Turn it into a shuffle of zero and zero-extended scalar to vector.
5193 Item = getShuffleVectorZeroOrUndef(Item, 0, NumZero > 0, Subtarget, DAG);
5194 SmallVector<int, 8> MaskVec;
5195 for (unsigned i = 0; i < NumElems; i++)
5196 MaskVec.push_back(i == Idx ? 0 : 1);
5197 return DAG.getVectorShuffle(VT, dl, Item, DAG.getUNDEF(VT), &MaskVec[0]);
5201 // Splat is obviously ok. Let legalizer expand it to a shuffle.
5202 if (Values.size() == 1) {
5203 if (EVTBits == 32) {
5204 // Instead of a shuffle like this:
5205 // shuffle (scalar_to_vector (load (ptr + 4))), undef, <0, 0, 0, 0>
5206 // Check if it's possible to issue this instead.
5207 // shuffle (vload ptr)), undef, <1, 1, 1, 1>
5208 unsigned Idx = CountTrailingZeros_32(NonZeros);
5209 SDValue Item = Op.getOperand(Idx);
5210 if (Op.getNode()->isOnlyUserOf(Item.getNode()))
5211 return LowerAsSplatVectorLoad(Item, VT, dl, DAG);
5216 // A vector full of immediates; various special cases are already
5217 // handled, so this is best done with a single constant-pool load.
5221 // For AVX-length vectors, build the individual 128-bit pieces and use
5222 // shuffles to put them in place.
5223 if (VT.getSizeInBits() == 256 && !ISD::isBuildVectorAllZeros(Op.getNode())) {
5224 SmallVector<SDValue, 32> V;
5225 for (unsigned i = 0; i < NumElems; ++i)
5226 V.push_back(Op.getOperand(i));
5228 EVT HVT = EVT::getVectorVT(*DAG.getContext(), ExtVT, NumElems/2);
5230 // Build both the lower and upper subvector.
5231 SDValue Lower = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT, &V[0], NumElems/2);
5232 SDValue Upper = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT, &V[NumElems / 2],
5235 // Recreate the wider vector with the lower and upper part.
5236 SDValue Vec = Insert128BitVector(DAG.getNode(ISD::UNDEF, dl, VT), Lower,
5237 DAG.getConstant(0, MVT::i32), DAG, dl);
5238 return Insert128BitVector(Vec, Upper, DAG.getConstant(NumElems/2, MVT::i32),
5242 // Let legalizer expand 2-wide build_vectors.
5243 if (EVTBits == 64) {
5244 if (NumNonZero == 1) {
5245 // One half is zero or undef.
5246 unsigned Idx = CountTrailingZeros_32(NonZeros);
5247 SDValue V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT,
5248 Op.getOperand(Idx));
5249 return getShuffleVectorZeroOrUndef(V2, Idx, true, Subtarget, DAG);
5254 // If element VT is < 32 bits, convert it to inserts into a zero vector.
5255 if (EVTBits == 8 && NumElems == 16) {
5256 SDValue V = LowerBuildVectorv16i8(Op, NonZeros,NumNonZero,NumZero, DAG,
5258 if (V.getNode()) return V;
5261 if (EVTBits == 16 && NumElems == 8) {
5262 SDValue V = LowerBuildVectorv8i16(Op, NonZeros,NumNonZero,NumZero, DAG,
5264 if (V.getNode()) return V;
5267 // If element VT is == 32 bits, turn it into a number of shuffles.
5268 SmallVector<SDValue, 8> V(NumElems);
5269 if (NumElems == 4 && NumZero > 0) {
5270 for (unsigned i = 0; i < 4; ++i) {
5271 bool isZero = !(NonZeros & (1 << i));
5273 V[i] = getZeroVector(VT, Subtarget, DAG, dl);
5275 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
5278 for (unsigned i = 0; i < 2; ++i) {
5279 switch ((NonZeros & (0x3 << i*2)) >> (i*2)) {
5282 V[i] = V[i*2]; // Must be a zero vector.
5285 V[i] = getMOVL(DAG, dl, VT, V[i*2+1], V[i*2]);
5288 V[i] = getMOVL(DAG, dl, VT, V[i*2], V[i*2+1]);
5291 V[i] = getUnpackl(DAG, dl, VT, V[i*2], V[i*2+1]);
5296 bool Reverse1 = (NonZeros & 0x3) == 2;
5297 bool Reverse2 = ((NonZeros & (0x3 << 2)) >> 2) == 2;
5301 static_cast<int>(Reverse2 ? NumElems+1 : NumElems),
5302 static_cast<int>(Reverse2 ? NumElems : NumElems+1)
5304 return DAG.getVectorShuffle(VT, dl, V[0], V[1], &MaskVec[0]);
5307 if (Values.size() > 1 && VT.getSizeInBits() == 128) {
5308 // Check for a build vector of consecutive loads.
5309 for (unsigned i = 0; i < NumElems; ++i)
5310 V[i] = Op.getOperand(i);
5312 // Check for elements which are consecutive loads.
5313 SDValue LD = EltsFromConsecutiveLoads(VT, V, dl, DAG);
5317 // For SSE 4.1, use insertps to put the high elements into the low element.
5318 if (getSubtarget()->hasSSE41()) {
5320 if (Op.getOperand(0).getOpcode() != ISD::UNDEF)
5321 Result = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(0));
5323 Result = DAG.getUNDEF(VT);
5325 for (unsigned i = 1; i < NumElems; ++i) {
5326 if (Op.getOperand(i).getOpcode() == ISD::UNDEF) continue;
5327 Result = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Result,
5328 Op.getOperand(i), DAG.getIntPtrConstant(i));
5333 // Otherwise, expand into a number of unpckl*, start by extending each of
5334 // our (non-undef) elements to the full vector width with the element in the
5335 // bottom slot of the vector (which generates no code for SSE).
5336 for (unsigned i = 0; i < NumElems; ++i) {
5337 if (Op.getOperand(i).getOpcode() != ISD::UNDEF)
5338 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
5340 V[i] = DAG.getUNDEF(VT);
5343 // Next, we iteratively mix elements, e.g. for v4f32:
5344 // Step 1: unpcklps 0, 2 ==> X: <?, ?, 2, 0>
5345 // : unpcklps 1, 3 ==> Y: <?, ?, 3, 1>
5346 // Step 2: unpcklps X, Y ==> <3, 2, 1, 0>
5347 unsigned EltStride = NumElems >> 1;
5348 while (EltStride != 0) {
5349 for (unsigned i = 0; i < EltStride; ++i) {
5350 // If V[i+EltStride] is undef and this is the first round of mixing,
5351 // then it is safe to just drop this shuffle: V[i] is already in the
5352 // right place, the one element (since it's the first round) being
5353 // inserted as undef can be dropped. This isn't safe for successive
5354 // rounds because they will permute elements within both vectors.
5355 if (V[i+EltStride].getOpcode() == ISD::UNDEF &&
5356 EltStride == NumElems/2)
5359 V[i] = getUnpackl(DAG, dl, VT, V[i], V[i + EltStride]);
5368 // LowerMMXCONCAT_VECTORS - We support concatenate two MMX registers and place
5369 // them in a MMX register. This is better than doing a stack convert.
5370 static SDValue LowerMMXCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
5371 DebugLoc dl = Op.getDebugLoc();
5372 EVT ResVT = Op.getValueType();
5374 assert(ResVT == MVT::v2i64 || ResVT == MVT::v4i32 ||
5375 ResVT == MVT::v8i16 || ResVT == MVT::v16i8);
5377 SDValue InVec = DAG.getNode(ISD::BITCAST,dl, MVT::v1i64, Op.getOperand(0));
5378 SDValue VecOp = DAG.getNode(X86ISD::MOVQ2DQ, dl, MVT::v2i64, InVec);
5379 InVec = Op.getOperand(1);
5380 if (InVec.getOpcode() == ISD::SCALAR_TO_VECTOR) {
5381 unsigned NumElts = ResVT.getVectorNumElements();
5382 VecOp = DAG.getNode(ISD::BITCAST, dl, ResVT, VecOp);
5383 VecOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, ResVT, VecOp,
5384 InVec.getOperand(0), DAG.getIntPtrConstant(NumElts/2+1));
5386 InVec = DAG.getNode(ISD::BITCAST, dl, MVT::v1i64, InVec);
5387 SDValue VecOp2 = DAG.getNode(X86ISD::MOVQ2DQ, dl, MVT::v2i64, InVec);
5388 Mask[0] = 0; Mask[1] = 2;
5389 VecOp = DAG.getVectorShuffle(MVT::v2i64, dl, VecOp, VecOp2, Mask);
5391 return DAG.getNode(ISD::BITCAST, dl, ResVT, VecOp);
5394 // LowerAVXCONCAT_VECTORS - 256-bit AVX can use the vinsertf128 instruction
5395 // to create 256-bit vectors from two other 128-bit ones.
5396 static SDValue LowerAVXCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
5397 DebugLoc dl = Op.getDebugLoc();
5398 EVT ResVT = Op.getValueType();
5400 assert(ResVT.getSizeInBits() == 256 && "Value type must be 256-bit wide");
5402 SDValue V1 = Op.getOperand(0);
5403 SDValue V2 = Op.getOperand(1);
5404 unsigned NumElems = ResVT.getVectorNumElements();
5406 SDValue V = Insert128BitVector(DAG.getNode(ISD::UNDEF, dl, ResVT), V1,
5407 DAG.getConstant(0, MVT::i32), DAG, dl);
5408 return Insert128BitVector(V, V2, DAG.getConstant(NumElems/2, MVT::i32),
5413 X86TargetLowering::LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) const {
5414 EVT ResVT = Op.getValueType();
5416 assert(Op.getNumOperands() == 2);
5417 assert((ResVT.getSizeInBits() == 128 || ResVT.getSizeInBits() == 256) &&
5418 "Unsupported CONCAT_VECTORS for value type");
5420 // We support concatenate two MMX registers and place them in a MMX register.
5421 // This is better than doing a stack convert.
5422 if (ResVT.is128BitVector())
5423 return LowerMMXCONCAT_VECTORS(Op, DAG);
5425 // 256-bit AVX can use the vinsertf128 instruction to create 256-bit vectors
5426 // from two other 128-bit ones.
5427 return LowerAVXCONCAT_VECTORS(Op, DAG);
5430 // v8i16 shuffles - Prefer shuffles in the following order:
5431 // 1. [all] pshuflw, pshufhw, optional move
5432 // 2. [ssse3] 1 x pshufb
5433 // 3. [ssse3] 2 x pshufb + 1 x por
5434 // 4. [all] mov + pshuflw + pshufhw + N x (pextrw + pinsrw)
5436 X86TargetLowering::LowerVECTOR_SHUFFLEv8i16(SDValue Op,
5437 SelectionDAG &DAG) const {
5438 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
5439 SDValue V1 = SVOp->getOperand(0);
5440 SDValue V2 = SVOp->getOperand(1);
5441 DebugLoc dl = SVOp->getDebugLoc();
5442 SmallVector<int, 8> MaskVals;
5444 // Determine if more than 1 of the words in each of the low and high quadwords
5445 // of the result come from the same quadword of one of the two inputs. Undef
5446 // mask values count as coming from any quadword, for better codegen.
5447 unsigned LoQuad[] = { 0, 0, 0, 0 };
5448 unsigned HiQuad[] = { 0, 0, 0, 0 };
5449 BitVector InputQuads(4);
5450 for (unsigned i = 0; i < 8; ++i) {
5451 unsigned *Quad = i < 4 ? LoQuad : HiQuad;
5452 int EltIdx = SVOp->getMaskElt(i);
5453 MaskVals.push_back(EltIdx);
5462 InputQuads.set(EltIdx / 4);
5465 int BestLoQuad = -1;
5466 unsigned MaxQuad = 1;
5467 for (unsigned i = 0; i < 4; ++i) {
5468 if (LoQuad[i] > MaxQuad) {
5470 MaxQuad = LoQuad[i];
5474 int BestHiQuad = -1;
5476 for (unsigned i = 0; i < 4; ++i) {
5477 if (HiQuad[i] > MaxQuad) {
5479 MaxQuad = HiQuad[i];
5483 // For SSSE3, If all 8 words of the result come from only 1 quadword of each
5484 // of the two input vectors, shuffle them into one input vector so only a
5485 // single pshufb instruction is necessary. If There are more than 2 input
5486 // quads, disable the next transformation since it does not help SSSE3.
5487 bool V1Used = InputQuads[0] || InputQuads[1];
5488 bool V2Used = InputQuads[2] || InputQuads[3];
5489 if (Subtarget->hasSSSE3()) {
5490 if (InputQuads.count() == 2 && V1Used && V2Used) {
5491 BestLoQuad = InputQuads.find_first();
5492 BestHiQuad = InputQuads.find_next(BestLoQuad);
5494 if (InputQuads.count() > 2) {
5500 // If BestLoQuad or BestHiQuad are set, shuffle the quads together and update
5501 // the shuffle mask. If a quad is scored as -1, that means that it contains
5502 // words from all 4 input quadwords.
5504 if (BestLoQuad >= 0 || BestHiQuad >= 0) {
5506 BestLoQuad < 0 ? 0 : BestLoQuad,
5507 BestHiQuad < 0 ? 1 : BestHiQuad
5509 NewV = DAG.getVectorShuffle(MVT::v2i64, dl,
5510 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, V1),
5511 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, V2), &MaskV[0]);
5512 NewV = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, NewV);
5514 // Rewrite the MaskVals and assign NewV to V1 if NewV now contains all the
5515 // source words for the shuffle, to aid later transformations.
5516 bool AllWordsInNewV = true;
5517 bool InOrder[2] = { true, true };
5518 for (unsigned i = 0; i != 8; ++i) {
5519 int idx = MaskVals[i];
5521 InOrder[i/4] = false;
5522 if (idx < 0 || (idx/4) == BestLoQuad || (idx/4) == BestHiQuad)
5524 AllWordsInNewV = false;
5528 bool pshuflw = AllWordsInNewV, pshufhw = AllWordsInNewV;
5529 if (AllWordsInNewV) {
5530 for (int i = 0; i != 8; ++i) {
5531 int idx = MaskVals[i];
5534 idx = MaskVals[i] = (idx / 4) == BestLoQuad ? (idx & 3) : (idx & 3) + 4;
5535 if ((idx != i) && idx < 4)
5537 if ((idx != i) && idx > 3)
5546 // If we've eliminated the use of V2, and the new mask is a pshuflw or
5547 // pshufhw, that's as cheap as it gets. Return the new shuffle.
5548 if ((pshufhw && InOrder[0]) || (pshuflw && InOrder[1])) {
5549 unsigned Opc = pshufhw ? X86ISD::PSHUFHW : X86ISD::PSHUFLW;
5550 unsigned TargetMask = 0;
5551 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV,
5552 DAG.getUNDEF(MVT::v8i16), &MaskVals[0]);
5553 TargetMask = pshufhw ? X86::getShufflePSHUFHWImmediate(NewV.getNode()):
5554 X86::getShufflePSHUFLWImmediate(NewV.getNode());
5555 V1 = NewV.getOperand(0);
5556 return getTargetShuffleNode(Opc, dl, MVT::v8i16, V1, TargetMask, DAG);
5560 // If we have SSSE3, and all words of the result are from 1 input vector,
5561 // case 2 is generated, otherwise case 3 is generated. If no SSSE3
5562 // is present, fall back to case 4.
5563 if (Subtarget->hasSSSE3()) {
5564 SmallVector<SDValue,16> pshufbMask;
5566 // If we have elements from both input vectors, set the high bit of the
5567 // shuffle mask element to zero out elements that come from V2 in the V1
5568 // mask, and elements that come from V1 in the V2 mask, so that the two
5569 // results can be OR'd together.
5570 bool TwoInputs = V1Used && V2Used;
5571 for (unsigned i = 0; i != 8; ++i) {
5572 int EltIdx = MaskVals[i] * 2;
5573 if (TwoInputs && (EltIdx >= 16)) {
5574 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
5575 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
5578 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
5579 pshufbMask.push_back(DAG.getConstant(EltIdx+1, MVT::i8));
5581 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V1);
5582 V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1,
5583 DAG.getNode(ISD::BUILD_VECTOR, dl,
5584 MVT::v16i8, &pshufbMask[0], 16));
5586 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
5588 // Calculate the shuffle mask for the second input, shuffle it, and
5589 // OR it with the first shuffled input.
5591 for (unsigned i = 0; i != 8; ++i) {
5592 int EltIdx = MaskVals[i] * 2;
5594 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
5595 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
5598 pshufbMask.push_back(DAG.getConstant(EltIdx - 16, MVT::i8));
5599 pshufbMask.push_back(DAG.getConstant(EltIdx - 15, MVT::i8));
5601 V2 = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V2);
5602 V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2,
5603 DAG.getNode(ISD::BUILD_VECTOR, dl,
5604 MVT::v16i8, &pshufbMask[0], 16));
5605 V1 = DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
5606 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
5609 // If BestLoQuad >= 0, generate a pshuflw to put the low elements in order,
5610 // and update MaskVals with new element order.
5611 std::bitset<8> InOrder;
5612 if (BestLoQuad >= 0) {
5613 int MaskV[] = { -1, -1, -1, -1, 4, 5, 6, 7 };
5614 for (int i = 0; i != 4; ++i) {
5615 int idx = MaskVals[i];
5618 } else if ((idx / 4) == BestLoQuad) {
5623 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16),
5626 if (NewV.getOpcode() == ISD::VECTOR_SHUFFLE && Subtarget->hasSSSE3())
5627 NewV = getTargetShuffleNode(X86ISD::PSHUFLW, dl, MVT::v8i16,
5629 X86::getShufflePSHUFLWImmediate(NewV.getNode()),
5633 // If BestHi >= 0, generate a pshufhw to put the high elements in order,
5634 // and update MaskVals with the new element order.
5635 if (BestHiQuad >= 0) {
5636 int MaskV[] = { 0, 1, 2, 3, -1, -1, -1, -1 };
5637 for (unsigned i = 4; i != 8; ++i) {
5638 int idx = MaskVals[i];
5641 } else if ((idx / 4) == BestHiQuad) {
5642 MaskV[i] = (idx & 3) + 4;
5646 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16),
5649 if (NewV.getOpcode() == ISD::VECTOR_SHUFFLE && Subtarget->hasSSSE3())
5650 NewV = getTargetShuffleNode(X86ISD::PSHUFHW, dl, MVT::v8i16,
5652 X86::getShufflePSHUFHWImmediate(NewV.getNode()),
5656 // In case BestHi & BestLo were both -1, which means each quadword has a word
5657 // from each of the four input quadwords, calculate the InOrder bitvector now
5658 // before falling through to the insert/extract cleanup.
5659 if (BestLoQuad == -1 && BestHiQuad == -1) {
5661 for (int i = 0; i != 8; ++i)
5662 if (MaskVals[i] < 0 || MaskVals[i] == i)
5666 // The other elements are put in the right place using pextrw and pinsrw.
5667 for (unsigned i = 0; i != 8; ++i) {
5670 int EltIdx = MaskVals[i];
5673 SDValue ExtOp = (EltIdx < 8)
5674 ? DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V1,
5675 DAG.getIntPtrConstant(EltIdx))
5676 : DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V2,
5677 DAG.getIntPtrConstant(EltIdx - 8));
5678 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, ExtOp,
5679 DAG.getIntPtrConstant(i));
5684 // v16i8 shuffles - Prefer shuffles in the following order:
5685 // 1. [ssse3] 1 x pshufb
5686 // 2. [ssse3] 2 x pshufb + 1 x por
5687 // 3. [all] v8i16 shuffle + N x pextrw + rotate + pinsrw
5689 SDValue LowerVECTOR_SHUFFLEv16i8(ShuffleVectorSDNode *SVOp,
5691 const X86TargetLowering &TLI) {
5692 SDValue V1 = SVOp->getOperand(0);
5693 SDValue V2 = SVOp->getOperand(1);
5694 DebugLoc dl = SVOp->getDebugLoc();
5695 ArrayRef<int> MaskVals = SVOp->getMask();
5697 // If we have SSSE3, case 1 is generated when all result bytes come from
5698 // one of the inputs. Otherwise, case 2 is generated. If no SSSE3 is
5699 // present, fall back to case 3.
5700 // FIXME: kill V2Only once shuffles are canonizalized by getNode.
5703 for (unsigned i = 0; i < 16; ++i) {
5704 int EltIdx = MaskVals[i];
5713 // If SSSE3, use 1 pshufb instruction per vector with elements in the result.
5714 if (TLI.getSubtarget()->hasSSSE3()) {
5715 SmallVector<SDValue,16> pshufbMask;
5717 // If all result elements are from one input vector, then only translate
5718 // undef mask values to 0x80 (zero out result) in the pshufb mask.
5720 // Otherwise, we have elements from both input vectors, and must zero out
5721 // elements that come from V2 in the first mask, and V1 in the second mask
5722 // so that we can OR them together.
5723 bool TwoInputs = !(V1Only || V2Only);
5724 for (unsigned i = 0; i != 16; ++i) {
5725 int EltIdx = MaskVals[i];
5726 if (EltIdx < 0 || (TwoInputs && EltIdx >= 16)) {
5727 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
5730 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
5732 // If all the elements are from V2, assign it to V1 and return after
5733 // building the first pshufb.
5736 V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1,
5737 DAG.getNode(ISD::BUILD_VECTOR, dl,
5738 MVT::v16i8, &pshufbMask[0], 16));
5742 // Calculate the shuffle mask for the second input, shuffle it, and
5743 // OR it with the first shuffled input.
5745 for (unsigned i = 0; i != 16; ++i) {
5746 int EltIdx = MaskVals[i];
5748 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
5751 pshufbMask.push_back(DAG.getConstant(EltIdx - 16, MVT::i8));
5753 V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2,
5754 DAG.getNode(ISD::BUILD_VECTOR, dl,
5755 MVT::v16i8, &pshufbMask[0], 16));
5756 return DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
5759 // No SSSE3 - Calculate in place words and then fix all out of place words
5760 // With 0-16 extracts & inserts. Worst case is 16 bytes out of order from
5761 // the 16 different words that comprise the two doublequadword input vectors.
5762 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
5763 V2 = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V2);
5764 SDValue NewV = V2Only ? V2 : V1;
5765 for (int i = 0; i != 8; ++i) {
5766 int Elt0 = MaskVals[i*2];
5767 int Elt1 = MaskVals[i*2+1];
5769 // This word of the result is all undef, skip it.
5770 if (Elt0 < 0 && Elt1 < 0)
5773 // This word of the result is already in the correct place, skip it.
5774 if (V1Only && (Elt0 == i*2) && (Elt1 == i*2+1))
5776 if (V2Only && (Elt0 == i*2+16) && (Elt1 == i*2+17))
5779 SDValue Elt0Src = Elt0 < 16 ? V1 : V2;
5780 SDValue Elt1Src = Elt1 < 16 ? V1 : V2;
5783 // If Elt0 and Elt1 are defined, are consecutive, and can be load
5784 // using a single extract together, load it and store it.
5785 if ((Elt0 >= 0) && ((Elt0 + 1) == Elt1) && ((Elt0 & 1) == 0)) {
5786 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src,
5787 DAG.getIntPtrConstant(Elt1 / 2));
5788 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt,
5789 DAG.getIntPtrConstant(i));
5793 // If Elt1 is defined, extract it from the appropriate source. If the
5794 // source byte is not also odd, shift the extracted word left 8 bits
5795 // otherwise clear the bottom 8 bits if we need to do an or.
5797 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src,
5798 DAG.getIntPtrConstant(Elt1 / 2));
5799 if ((Elt1 & 1) == 0)
5800 InsElt = DAG.getNode(ISD::SHL, dl, MVT::i16, InsElt,
5802 TLI.getShiftAmountTy(InsElt.getValueType())));
5804 InsElt = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt,
5805 DAG.getConstant(0xFF00, MVT::i16));
5807 // If Elt0 is defined, extract it from the appropriate source. If the
5808 // source byte is not also even, shift the extracted word right 8 bits. If
5809 // Elt1 was also defined, OR the extracted values together before
5810 // inserting them in the result.
5812 SDValue InsElt0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16,
5813 Elt0Src, DAG.getIntPtrConstant(Elt0 / 2));
5814 if ((Elt0 & 1) != 0)
5815 InsElt0 = DAG.getNode(ISD::SRL, dl, MVT::i16, InsElt0,
5817 TLI.getShiftAmountTy(InsElt0.getValueType())));
5819 InsElt0 = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt0,
5820 DAG.getConstant(0x00FF, MVT::i16));
5821 InsElt = Elt1 >= 0 ? DAG.getNode(ISD::OR, dl, MVT::i16, InsElt, InsElt0)
5824 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt,
5825 DAG.getIntPtrConstant(i));
5827 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, NewV);
5830 /// RewriteAsNarrowerShuffle - Try rewriting v8i16 and v16i8 shuffles as 4 wide
5831 /// ones, or rewriting v4i32 / v4f32 as 2 wide ones if possible. This can be
5832 /// done when every pair / quad of shuffle mask elements point to elements in
5833 /// the right sequence. e.g.
5834 /// vector_shuffle X, Y, <2, 3, | 10, 11, | 0, 1, | 14, 15>
5836 SDValue RewriteAsNarrowerShuffle(ShuffleVectorSDNode *SVOp,
5837 SelectionDAG &DAG, DebugLoc dl) {
5838 EVT VT = SVOp->getValueType(0);
5839 SDValue V1 = SVOp->getOperand(0);
5840 SDValue V2 = SVOp->getOperand(1);
5841 unsigned NumElems = VT.getVectorNumElements();
5842 unsigned NewWidth = (NumElems == 4) ? 2 : 4;
5844 switch (VT.getSimpleVT().SimpleTy) {
5845 default: assert(false && "Unexpected!");
5846 case MVT::v4f32: NewVT = MVT::v2f64; break;
5847 case MVT::v4i32: NewVT = MVT::v2i64; break;
5848 case MVT::v8i16: NewVT = MVT::v4i32; break;
5849 case MVT::v16i8: NewVT = MVT::v4i32; break;
5852 int Scale = NumElems / NewWidth;
5853 SmallVector<int, 8> MaskVec;
5854 for (unsigned i = 0; i < NumElems; i += Scale) {
5856 for (int j = 0; j < Scale; ++j) {
5857 int EltIdx = SVOp->getMaskElt(i+j);
5861 StartIdx = EltIdx - (EltIdx % Scale);
5862 if (EltIdx != StartIdx + j)
5866 MaskVec.push_back(-1);
5868 MaskVec.push_back(StartIdx / Scale);
5871 V1 = DAG.getNode(ISD::BITCAST, dl, NewVT, V1);
5872 V2 = DAG.getNode(ISD::BITCAST, dl, NewVT, V2);
5873 return DAG.getVectorShuffle(NewVT, dl, V1, V2, &MaskVec[0]);
5876 /// getVZextMovL - Return a zero-extending vector move low node.
5878 static SDValue getVZextMovL(EVT VT, EVT OpVT,
5879 SDValue SrcOp, SelectionDAG &DAG,
5880 const X86Subtarget *Subtarget, DebugLoc dl) {
5881 if (VT == MVT::v2f64 || VT == MVT::v4f32) {
5882 LoadSDNode *LD = NULL;
5883 if (!isScalarLoadToVector(SrcOp.getNode(), &LD))
5884 LD = dyn_cast<LoadSDNode>(SrcOp);
5886 // movssrr and movsdrr do not clear top bits. Try to use movd, movq
5888 MVT ExtVT = (OpVT == MVT::v2f64) ? MVT::i64 : MVT::i32;
5889 if ((ExtVT != MVT::i64 || Subtarget->is64Bit()) &&
5890 SrcOp.getOpcode() == ISD::SCALAR_TO_VECTOR &&
5891 SrcOp.getOperand(0).getOpcode() == ISD::BITCAST &&
5892 SrcOp.getOperand(0).getOperand(0).getValueType() == ExtVT) {
5894 OpVT = (OpVT == MVT::v2f64) ? MVT::v2i64 : MVT::v4i32;
5895 return DAG.getNode(ISD::BITCAST, dl, VT,
5896 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT,
5897 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
5905 return DAG.getNode(ISD::BITCAST, dl, VT,
5906 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT,
5907 DAG.getNode(ISD::BITCAST, dl,
5911 /// LowerVECTOR_SHUFFLE_256 - Handle all 256-bit wide vectors shuffles
5912 /// which could not be matched by any known target speficic shuffle
5914 LowerVECTOR_SHUFFLE_256(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
5915 EVT VT = SVOp->getValueType(0);
5917 unsigned NumElems = VT.getVectorNumElements();
5918 unsigned NumLaneElems = NumElems / 2;
5920 int MinRange[2][2] = { { static_cast<int>(NumElems),
5921 static_cast<int>(NumElems) },
5922 { static_cast<int>(NumElems),
5923 static_cast<int>(NumElems) } };
5924 int MaxRange[2][2] = { { -1, -1 }, { -1, -1 } };
5926 // Collect used ranges for each source in each lane
5927 for (unsigned l = 0; l < 2; ++l) {
5928 unsigned LaneStart = l*NumLaneElems;
5929 for (unsigned i = 0; i != NumLaneElems; ++i) {
5930 int Idx = SVOp->getMaskElt(i+LaneStart);
5935 if (Idx >= (int)NumElems) {
5940 if (Idx > MaxRange[l][Input])
5941 MaxRange[l][Input] = Idx;
5942 if (Idx < MinRange[l][Input])
5943 MinRange[l][Input] = Idx;
5947 // Make sure each range is 128-bits
5948 int ExtractIdx[2][2] = { { -1, -1 }, { -1, -1 } };
5949 for (unsigned l = 0; l < 2; ++l) {
5950 for (unsigned Input = 0; Input < 2; ++Input) {
5951 if (MinRange[l][Input] == (int)NumElems && MaxRange[l][Input] < 0)
5954 if (MinRange[l][Input] >= 0 && MaxRange[l][Input] < (int)NumLaneElems)
5955 ExtractIdx[l][Input] = 0;
5956 else if (MinRange[l][Input] >= (int)NumLaneElems &&
5957 MaxRange[l][Input] < (int)NumElems)
5958 ExtractIdx[l][Input] = NumLaneElems;
5964 DebugLoc dl = SVOp->getDebugLoc();
5965 MVT EltVT = VT.getVectorElementType().getSimpleVT();
5966 EVT NVT = MVT::getVectorVT(EltVT, NumElems/2);
5969 for (unsigned l = 0; l < 2; ++l) {
5970 for (unsigned Input = 0; Input < 2; ++Input) {
5971 if (ExtractIdx[l][Input] >= 0)
5972 Ops[l][Input] = Extract128BitVector(SVOp->getOperand(Input),
5973 DAG.getConstant(ExtractIdx[l][Input], MVT::i32),
5976 Ops[l][Input] = DAG.getUNDEF(NVT);
5980 // Generate 128-bit shuffles
5981 SmallVector<int, 16> Mask1, Mask2;
5982 for (unsigned i = 0; i != NumLaneElems; ++i) {
5983 int Elt = SVOp->getMaskElt(i);
5984 if (Elt >= (int)NumElems) {
5985 Elt %= NumLaneElems;
5986 Elt += NumLaneElems;
5987 } else if (Elt >= 0) {
5988 Elt %= NumLaneElems;
5990 Mask1.push_back(Elt);
5992 for (unsigned i = NumLaneElems; i != NumElems; ++i) {
5993 int Elt = SVOp->getMaskElt(i);
5994 if (Elt >= (int)NumElems) {
5995 Elt %= NumLaneElems;
5996 Elt += NumLaneElems;
5997 } else if (Elt >= 0) {
5998 Elt %= NumLaneElems;
6000 Mask2.push_back(Elt);
6003 SDValue Shuf1 = DAG.getVectorShuffle(NVT, dl, Ops[0][0], Ops[0][1], &Mask1[0]);
6004 SDValue Shuf2 = DAG.getVectorShuffle(NVT, dl, Ops[1][0], Ops[1][1], &Mask2[0]);
6006 // Concatenate the result back
6007 SDValue V = Insert128BitVector(DAG.getNode(ISD::UNDEF, dl, VT), Shuf1,
6008 DAG.getConstant(0, MVT::i32), DAG, dl);
6009 return Insert128BitVector(V, Shuf2, DAG.getConstant(NumElems/2, MVT::i32),
6013 /// LowerVECTOR_SHUFFLE_128v4 - Handle all 128-bit wide vectors with
6014 /// 4 elements, and match them with several different shuffle types.
6016 LowerVECTOR_SHUFFLE_128v4(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
6017 SDValue V1 = SVOp->getOperand(0);
6018 SDValue V2 = SVOp->getOperand(1);
6019 DebugLoc dl = SVOp->getDebugLoc();
6020 EVT VT = SVOp->getValueType(0);
6022 assert(VT.getSizeInBits() == 128 && "Unsupported vector size");
6024 std::pair<int, int> Locs[4];
6025 int Mask1[] = { -1, -1, -1, -1 };
6026 SmallVector<int, 8> PermMask(SVOp->getMask().begin(), SVOp->getMask().end());
6030 for (unsigned i = 0; i != 4; ++i) {
6031 int Idx = PermMask[i];
6033 Locs[i] = std::make_pair(-1, -1);
6035 assert(Idx < 8 && "Invalid VECTOR_SHUFFLE index!");
6037 Locs[i] = std::make_pair(0, NumLo);
6041 Locs[i] = std::make_pair(1, NumHi);
6043 Mask1[2+NumHi] = Idx;
6049 if (NumLo <= 2 && NumHi <= 2) {
6050 // If no more than two elements come from either vector. This can be
6051 // implemented with two shuffles. First shuffle gather the elements.
6052 // The second shuffle, which takes the first shuffle as both of its
6053 // vector operands, put the elements into the right order.
6054 V1 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
6056 int Mask2[] = { -1, -1, -1, -1 };
6058 for (unsigned i = 0; i != 4; ++i)
6059 if (Locs[i].first != -1) {
6060 unsigned Idx = (i < 2) ? 0 : 4;
6061 Idx += Locs[i].first * 2 + Locs[i].second;
6065 return DAG.getVectorShuffle(VT, dl, V1, V1, &Mask2[0]);
6066 } else if (NumLo == 3 || NumHi == 3) {
6067 // Otherwise, we must have three elements from one vector, call it X, and
6068 // one element from the other, call it Y. First, use a shufps to build an
6069 // intermediate vector with the one element from Y and the element from X
6070 // that will be in the same half in the final destination (the indexes don't
6071 // matter). Then, use a shufps to build the final vector, taking the half
6072 // containing the element from Y from the intermediate, and the other half
6075 // Normalize it so the 3 elements come from V1.
6076 CommuteVectorShuffleMask(PermMask, 4);
6080 // Find the element from V2.
6082 for (HiIndex = 0; HiIndex < 3; ++HiIndex) {
6083 int Val = PermMask[HiIndex];
6090 Mask1[0] = PermMask[HiIndex];
6092 Mask1[2] = PermMask[HiIndex^1];
6094 V2 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
6097 Mask1[0] = PermMask[0];
6098 Mask1[1] = PermMask[1];
6099 Mask1[2] = HiIndex & 1 ? 6 : 4;
6100 Mask1[3] = HiIndex & 1 ? 4 : 6;
6101 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
6103 Mask1[0] = HiIndex & 1 ? 2 : 0;
6104 Mask1[1] = HiIndex & 1 ? 0 : 2;
6105 Mask1[2] = PermMask[2];
6106 Mask1[3] = PermMask[3];
6111 return DAG.getVectorShuffle(VT, dl, V2, V1, &Mask1[0]);
6115 // Break it into (shuffle shuffle_hi, shuffle_lo).
6116 int LoMask[] = { -1, -1, -1, -1 };
6117 int HiMask[] = { -1, -1, -1, -1 };
6119 int *MaskPtr = LoMask;
6120 unsigned MaskIdx = 0;
6123 for (unsigned i = 0; i != 4; ++i) {
6130 int Idx = PermMask[i];
6132 Locs[i] = std::make_pair(-1, -1);
6133 } else if (Idx < 4) {
6134 Locs[i] = std::make_pair(MaskIdx, LoIdx);
6135 MaskPtr[LoIdx] = Idx;
6138 Locs[i] = std::make_pair(MaskIdx, HiIdx);
6139 MaskPtr[HiIdx] = Idx;
6144 SDValue LoShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &LoMask[0]);
6145 SDValue HiShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &HiMask[0]);
6146 int MaskOps[] = { -1, -1, -1, -1 };
6147 for (unsigned i = 0; i != 4; ++i)
6148 if (Locs[i].first != -1)
6149 MaskOps[i] = Locs[i].first * 4 + Locs[i].second;
6150 return DAG.getVectorShuffle(VT, dl, LoShuffle, HiShuffle, &MaskOps[0]);
6153 static bool MayFoldVectorLoad(SDValue V) {
6154 if (V.hasOneUse() && V.getOpcode() == ISD::BITCAST)
6155 V = V.getOperand(0);
6156 if (V.hasOneUse() && V.getOpcode() == ISD::SCALAR_TO_VECTOR)
6157 V = V.getOperand(0);
6158 if (V.hasOneUse() && V.getOpcode() == ISD::BUILD_VECTOR &&
6159 V.getNumOperands() == 2 && V.getOperand(1).getOpcode() == ISD::UNDEF)
6160 // BUILD_VECTOR (load), undef
6161 V = V.getOperand(0);
6167 // FIXME: the version above should always be used. Since there's
6168 // a bug where several vector shuffles can't be folded because the
6169 // DAG is not updated during lowering and a node claims to have two
6170 // uses while it only has one, use this version, and let isel match
6171 // another instruction if the load really happens to have more than
6172 // one use. Remove this version after this bug get fixed.
6173 // rdar://8434668, PR8156
6174 static bool RelaxedMayFoldVectorLoad(SDValue V) {
6175 if (V.hasOneUse() && V.getOpcode() == ISD::BITCAST)
6176 V = V.getOperand(0);
6177 if (V.hasOneUse() && V.getOpcode() == ISD::SCALAR_TO_VECTOR)
6178 V = V.getOperand(0);
6179 if (ISD::isNormalLoad(V.getNode()))
6184 /// CanFoldShuffleIntoVExtract - Check if the current shuffle is used by
6185 /// a vector extract, and if both can be later optimized into a single load.
6186 /// This is done in visitEXTRACT_VECTOR_ELT and the conditions are checked
6187 /// here because otherwise a target specific shuffle node is going to be
6188 /// emitted for this shuffle, and the optimization not done.
6189 /// FIXME: This is probably not the best approach, but fix the problem
6190 /// until the right path is decided.
6192 bool CanXFormVExtractWithShuffleIntoLoad(SDValue V, SelectionDAG &DAG,
6193 const TargetLowering &TLI) {
6194 EVT VT = V.getValueType();
6195 ShuffleVectorSDNode *SVOp = dyn_cast<ShuffleVectorSDNode>(V);
6197 // Be sure that the vector shuffle is present in a pattern like this:
6198 // (vextract (v4f32 shuffle (load $addr), <1,u,u,u>), c) -> (f32 load $addr)
6202 SDNode *N = *V.getNode()->use_begin();
6203 if (N->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
6206 SDValue EltNo = N->getOperand(1);
6207 if (!isa<ConstantSDNode>(EltNo))
6210 // If the bit convert changed the number of elements, it is unsafe
6211 // to examine the mask.
6212 bool HasShuffleIntoBitcast = false;
6213 if (V.getOpcode() == ISD::BITCAST) {
6214 EVT SrcVT = V.getOperand(0).getValueType();
6215 if (SrcVT.getVectorNumElements() != VT.getVectorNumElements())
6217 V = V.getOperand(0);
6218 HasShuffleIntoBitcast = true;
6221 // Select the input vector, guarding against out of range extract vector.
6222 unsigned NumElems = VT.getVectorNumElements();
6223 unsigned Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();
6224 int Idx = (Elt > NumElems) ? -1 : SVOp->getMaskElt(Elt);
6225 V = (Idx < (int)NumElems) ? V.getOperand(0) : V.getOperand(1);
6227 // If we are accessing the upper part of a YMM register
6228 // then the EXTRACT_VECTOR_ELT is likely to be legalized to a sequence of
6229 // EXTRACT_SUBVECTOR + EXTRACT_VECTOR_ELT, which are not detected at this point
6230 // because the legalization of N did not happen yet.
6231 if (Idx >= (int)NumElems/2 && VT.getSizeInBits() == 256)
6234 // Skip one more bit_convert if necessary
6235 if (V.getOpcode() == ISD::BITCAST)
6236 V = V.getOperand(0);
6238 if (!ISD::isNormalLoad(V.getNode()))
6241 // Is the original load suitable?
6242 LoadSDNode *LN0 = cast<LoadSDNode>(V);
6244 if (!LN0 || !LN0->hasNUsesOfValue(1,0) || LN0->isVolatile())
6247 if (!HasShuffleIntoBitcast)
6250 // If there's a bitcast before the shuffle, check if the load type and
6251 // alignment is valid.
6252 unsigned Align = LN0->getAlignment();
6254 TLI.getTargetData()->getABITypeAlignment(
6255 VT.getTypeForEVT(*DAG.getContext()));
6257 if (NewAlign > Align || !TLI.isOperationLegalOrCustom(ISD::LOAD, VT))
6264 SDValue getMOVDDup(SDValue &Op, DebugLoc &dl, SDValue V1, SelectionDAG &DAG) {
6265 EVT VT = Op.getValueType();
6267 // Canonizalize to v2f64.
6268 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, V1);
6269 return DAG.getNode(ISD::BITCAST, dl, VT,
6270 getTargetShuffleNode(X86ISD::MOVDDUP, dl, MVT::v2f64,
6275 SDValue getMOVLowToHigh(SDValue &Op, DebugLoc &dl, SelectionDAG &DAG,
6277 SDValue V1 = Op.getOperand(0);
6278 SDValue V2 = Op.getOperand(1);
6279 EVT VT = Op.getValueType();
6281 assert(VT != MVT::v2i64 && "unsupported shuffle type");
6283 if (HasSSE2 && VT == MVT::v2f64)
6284 return getTargetShuffleNode(X86ISD::MOVLHPD, dl, VT, V1, V2, DAG);
6286 // v4f32 or v4i32: canonizalized to v4f32 (which is legal for SSE1)
6287 return DAG.getNode(ISD::BITCAST, dl, VT,
6288 getTargetShuffleNode(X86ISD::MOVLHPS, dl, MVT::v4f32,
6289 DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V1),
6290 DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V2), DAG));
6294 SDValue getMOVHighToLow(SDValue &Op, DebugLoc &dl, SelectionDAG &DAG) {
6295 SDValue V1 = Op.getOperand(0);
6296 SDValue V2 = Op.getOperand(1);
6297 EVT VT = Op.getValueType();
6299 assert((VT == MVT::v4i32 || VT == MVT::v4f32) &&
6300 "unsupported shuffle type");
6302 if (V2.getOpcode() == ISD::UNDEF)
6306 return getTargetShuffleNode(X86ISD::MOVHLPS, dl, VT, V1, V2, DAG);
6310 SDValue getMOVLP(SDValue &Op, DebugLoc &dl, SelectionDAG &DAG, bool HasSSE2) {
6311 SDValue V1 = Op.getOperand(0);
6312 SDValue V2 = Op.getOperand(1);
6313 EVT VT = Op.getValueType();
6314 unsigned NumElems = VT.getVectorNumElements();
6316 // Use MOVLPS and MOVLPD in case V1 or V2 are loads. During isel, the second
6317 // operand of these instructions is only memory, so check if there's a
6318 // potencial load folding here, otherwise use SHUFPS or MOVSD to match the
6320 bool CanFoldLoad = false;
6322 // Trivial case, when V2 comes from a load.
6323 if (MayFoldVectorLoad(V2))
6326 // When V1 is a load, it can be folded later into a store in isel, example:
6327 // (store (v4f32 (X86Movlps (load addr:$src1), VR128:$src2)), addr:$src1)
6329 // (MOVLPSmr addr:$src1, VR128:$src2)
6330 // So, recognize this potential and also use MOVLPS or MOVLPD
6331 else if (MayFoldVectorLoad(V1) && MayFoldIntoStore(Op))
6334 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
6336 if (HasSSE2 && NumElems == 2)
6337 return getTargetShuffleNode(X86ISD::MOVLPD, dl, VT, V1, V2, DAG);
6340 // If we don't care about the second element, procede to use movss.
6341 if (SVOp->getMaskElt(1) != -1)
6342 return getTargetShuffleNode(X86ISD::MOVLPS, dl, VT, V1, V2, DAG);
6345 // movl and movlp will both match v2i64, but v2i64 is never matched by
6346 // movl earlier because we make it strict to avoid messing with the movlp load
6347 // folding logic (see the code above getMOVLP call). Match it here then,
6348 // this is horrible, but will stay like this until we move all shuffle
6349 // matching to x86 specific nodes. Note that for the 1st condition all
6350 // types are matched with movsd.
6352 // FIXME: isMOVLMask should be checked and matched before getMOVLP,
6353 // as to remove this logic from here, as much as possible
6354 if (NumElems == 2 || !X86::isMOVLMask(SVOp))
6355 return getTargetShuffleNode(X86ISD::MOVSD, dl, VT, V1, V2, DAG);
6356 return getTargetShuffleNode(X86ISD::MOVSS, dl, VT, V1, V2, DAG);
6359 assert(VT != MVT::v4i32 && "unsupported shuffle type");
6361 // Invert the operand order and use SHUFPS to match it.
6362 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V2, V1,
6363 X86::getShuffleSHUFImmediate(SVOp), DAG);
6367 SDValue NormalizeVectorShuffle(SDValue Op, SelectionDAG &DAG,
6368 const TargetLowering &TLI,
6369 const X86Subtarget *Subtarget) {
6370 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
6371 EVT VT = Op.getValueType();
6372 DebugLoc dl = Op.getDebugLoc();
6373 SDValue V1 = Op.getOperand(0);
6374 SDValue V2 = Op.getOperand(1);
6376 if (isZeroShuffle(SVOp))
6377 return getZeroVector(VT, Subtarget, DAG, dl);
6379 // Handle splat operations
6380 if (SVOp->isSplat()) {
6381 unsigned NumElem = VT.getVectorNumElements();
6382 int Size = VT.getSizeInBits();
6383 // Special case, this is the only place now where it's allowed to return
6384 // a vector_shuffle operation without using a target specific node, because
6385 // *hopefully* it will be optimized away by the dag combiner. FIXME: should
6386 // this be moved to DAGCombine instead?
6387 if (NumElem <= 4 && CanXFormVExtractWithShuffleIntoLoad(Op, DAG, TLI))
6390 // Use vbroadcast whenever the splat comes from a foldable load
6391 SDValue LD = isVectorBroadcast(Op, Subtarget);
6393 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, LD);
6395 // Handle splats by matching through known shuffle masks
6396 if ((Size == 128 && NumElem <= 4) ||
6397 (Size == 256 && NumElem < 8))
6400 // All remaning splats are promoted to target supported vector shuffles.
6401 return PromoteSplat(SVOp, DAG);
6404 // If the shuffle can be profitably rewritten as a narrower shuffle, then
6406 if (VT == MVT::v8i16 || VT == MVT::v16i8) {
6407 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG, dl);
6408 if (NewOp.getNode())
6409 return DAG.getNode(ISD::BITCAST, dl, VT, NewOp);
6410 } else if ((VT == MVT::v4i32 ||
6411 (VT == MVT::v4f32 && Subtarget->hasSSE2()))) {
6412 // FIXME: Figure out a cleaner way to do this.
6413 // Try to make use of movq to zero out the top part.
6414 if (ISD::isBuildVectorAllZeros(V2.getNode())) {
6415 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG, dl);
6416 if (NewOp.getNode()) {
6417 if (isCommutedMOVL(cast<ShuffleVectorSDNode>(NewOp), true, false))
6418 return getVZextMovL(VT, NewOp.getValueType(), NewOp.getOperand(0),
6419 DAG, Subtarget, dl);
6421 } else if (ISD::isBuildVectorAllZeros(V1.getNode())) {
6422 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG, dl);
6423 if (NewOp.getNode() && X86::isMOVLMask(cast<ShuffleVectorSDNode>(NewOp)))
6424 return getVZextMovL(VT, NewOp.getValueType(), NewOp.getOperand(1),
6425 DAG, Subtarget, dl);
6432 X86TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const {
6433 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
6434 SDValue V1 = Op.getOperand(0);
6435 SDValue V2 = Op.getOperand(1);
6436 EVT VT = Op.getValueType();
6437 DebugLoc dl = Op.getDebugLoc();
6438 unsigned NumElems = VT.getVectorNumElements();
6439 bool V1IsUndef = V1.getOpcode() == ISD::UNDEF;
6440 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
6441 bool V1IsSplat = false;
6442 bool V2IsSplat = false;
6443 bool HasSSE2 = Subtarget->hasSSE2();
6444 bool HasAVX = Subtarget->hasAVX();
6445 bool HasAVX2 = Subtarget->hasAVX2();
6446 MachineFunction &MF = DAG.getMachineFunction();
6447 bool OptForSize = MF.getFunction()->hasFnAttr(Attribute::OptimizeForSize);
6449 assert(VT.getSizeInBits() != 64 && "Can't lower MMX shuffles");
6451 if (V1IsUndef && V2IsUndef)
6452 return DAG.getUNDEF(VT);
6454 assert(!V1IsUndef && "Op 1 of shuffle should not be undef");
6456 // Vector shuffle lowering takes 3 steps:
6458 // 1) Normalize the input vectors. Here splats, zeroed vectors, profitable
6459 // narrowing and commutation of operands should be handled.
6460 // 2) Matching of shuffles with known shuffle masks to x86 target specific
6462 // 3) Rewriting of unmatched masks into new generic shuffle operations,
6463 // so the shuffle can be broken into other shuffles and the legalizer can
6464 // try the lowering again.
6466 // The general idea is that no vector_shuffle operation should be left to
6467 // be matched during isel, all of them must be converted to a target specific
6470 // Normalize the input vectors. Here splats, zeroed vectors, profitable
6471 // narrowing and commutation of operands should be handled. The actual code
6472 // doesn't include all of those, work in progress...
6473 SDValue NewOp = NormalizeVectorShuffle(Op, DAG, *this, Subtarget);
6474 if (NewOp.getNode())
6477 // NOTE: isPSHUFDMask can also match both masks below (unpckl_undef and
6478 // unpckh_undef). Only use pshufd if speed is more important than size.
6479 if (OptForSize && X86::isUNPCKL_v_undef_Mask(SVOp, HasAVX2))
6480 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
6481 if (OptForSize && X86::isUNPCKH_v_undef_Mask(SVOp, HasAVX2))
6482 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
6484 if (X86::isMOVDDUPMask(SVOp) && Subtarget->hasSSE3() &&
6485 V2IsUndef && RelaxedMayFoldVectorLoad(V1))
6486 return getMOVDDup(Op, dl, V1, DAG);
6488 if (X86::isMOVHLPS_v_undef_Mask(SVOp))
6489 return getMOVHighToLow(Op, dl, DAG);
6491 // Use to match splats
6492 if (HasSSE2 && X86::isUNPCKHMask(SVOp, HasAVX2) && V2IsUndef &&
6493 (VT == MVT::v2f64 || VT == MVT::v2i64))
6494 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
6496 if (X86::isPSHUFDMask(SVOp)) {
6497 // The actual implementation will match the mask in the if above and then
6498 // during isel it can match several different instructions, not only pshufd
6499 // as its name says, sad but true, emulate the behavior for now...
6500 if (X86::isMOVDDUPMask(SVOp) && ((VT == MVT::v4f32 || VT == MVT::v2i64)))
6501 return getTargetShuffleNode(X86ISD::MOVLHPS, dl, VT, V1, V1, DAG);
6503 unsigned TargetMask = X86::getShuffleSHUFImmediate(SVOp);
6505 if (HasSSE2 && (VT == MVT::v4f32 || VT == MVT::v4i32))
6506 return getTargetShuffleNode(X86ISD::PSHUFD, dl, VT, V1, TargetMask, DAG);
6508 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V1, V1,
6512 // Check if this can be converted into a logical shift.
6513 bool isLeft = false;
6516 bool isShift = HasSSE2 && isVectorShift(SVOp, DAG, isLeft, ShVal, ShAmt);
6517 if (isShift && ShVal.hasOneUse()) {
6518 // If the shifted value has multiple uses, it may be cheaper to use
6519 // v_set0 + movlhps or movhlps, etc.
6520 EVT EltVT = VT.getVectorElementType();
6521 ShAmt *= EltVT.getSizeInBits();
6522 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl);
6525 if (X86::isMOVLMask(SVOp)) {
6526 if (ISD::isBuildVectorAllZeros(V1.getNode()))
6527 return getVZextMovL(VT, VT, V2, DAG, Subtarget, dl);
6528 if (!X86::isMOVLPMask(SVOp)) {
6529 if (HasSSE2 && (VT == MVT::v2i64 || VT == MVT::v2f64))
6530 return getTargetShuffleNode(X86ISD::MOVSD, dl, VT, V1, V2, DAG);
6532 if (VT == MVT::v4i32 || VT == MVT::v4f32)
6533 return getTargetShuffleNode(X86ISD::MOVSS, dl, VT, V1, V2, DAG);
6537 // FIXME: fold these into legal mask.
6538 if (X86::isMOVLHPSMask(SVOp) && !X86::isUNPCKLMask(SVOp, HasAVX2))
6539 return getMOVLowToHigh(Op, dl, DAG, HasSSE2);
6541 if (X86::isMOVHLPSMask(SVOp))
6542 return getMOVHighToLow(Op, dl, DAG);
6544 if (X86::isMOVSHDUPMask(SVOp, Subtarget))
6545 return getTargetShuffleNode(X86ISD::MOVSHDUP, dl, VT, V1, DAG);
6547 if (X86::isMOVSLDUPMask(SVOp, Subtarget))
6548 return getTargetShuffleNode(X86ISD::MOVSLDUP, dl, VT, V1, DAG);
6550 if (X86::isMOVLPMask(SVOp))
6551 return getMOVLP(Op, dl, DAG, HasSSE2);
6553 if (ShouldXformToMOVHLPS(SVOp) ||
6554 ShouldXformToMOVLP(V1.getNode(), V2.getNode(), SVOp))
6555 return CommuteVectorShuffle(SVOp, DAG);
6558 // No better options. Use a vshldq / vsrldq.
6559 EVT EltVT = VT.getVectorElementType();
6560 ShAmt *= EltVT.getSizeInBits();
6561 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl);
6564 bool Commuted = false;
6565 // FIXME: This should also accept a bitcast of a splat? Be careful, not
6566 // 1,1,1,1 -> v8i16 though.
6567 V1IsSplat = isSplatVector(V1.getNode());
6568 V2IsSplat = isSplatVector(V2.getNode());
6570 // Canonicalize the splat or undef, if present, to be on the RHS.
6571 if (V1IsSplat && !V2IsSplat) {
6572 Op = CommuteVectorShuffle(SVOp, DAG);
6573 SVOp = cast<ShuffleVectorSDNode>(Op);
6574 V1 = SVOp->getOperand(0);
6575 V2 = SVOp->getOperand(1);
6576 std::swap(V1IsSplat, V2IsSplat);
6580 ArrayRef<int> M = SVOp->getMask();
6582 if (isCommutedMOVLMask(M, VT, V2IsSplat, V2IsUndef)) {
6583 // Shuffling low element of v1 into undef, just return v1.
6586 // If V2 is a splat, the mask may be malformed such as <4,3,3,3>, which
6587 // the instruction selector will not match, so get a canonical MOVL with
6588 // swapped operands to undo the commute.
6589 return getMOVL(DAG, dl, VT, V2, V1);
6592 if (isUNPCKLMask(M, VT, HasAVX2))
6593 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG);
6595 if (isUNPCKHMask(M, VT, HasAVX2))
6596 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG);
6599 // Normalize mask so all entries that point to V2 points to its first
6600 // element then try to match unpck{h|l} again. If match, return a
6601 // new vector_shuffle with the corrected mask.
6602 SDValue NewMask = NormalizeMask(SVOp, DAG);
6603 ShuffleVectorSDNode *NSVOp = cast<ShuffleVectorSDNode>(NewMask);
6604 if (NSVOp != SVOp) {
6605 if (X86::isUNPCKLMask(NSVOp, HasAVX2, true)) {
6607 } else if (X86::isUNPCKHMask(NSVOp, HasAVX2, true)) {
6614 // Commute is back and try unpck* again.
6615 // FIXME: this seems wrong.
6616 SDValue NewOp = CommuteVectorShuffle(SVOp, DAG);
6617 ShuffleVectorSDNode *NewSVOp = cast<ShuffleVectorSDNode>(NewOp);
6619 if (X86::isUNPCKLMask(NewSVOp, HasAVX2))
6620 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V2, V1, DAG);
6622 if (X86::isUNPCKHMask(NewSVOp, HasAVX2))
6623 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V2, V1, DAG);
6626 // Normalize the node to match x86 shuffle ops if needed
6627 if (!V2IsUndef && (isSHUFPMask(M, VT, HasAVX, /* Commuted */ true)))
6628 return CommuteVectorShuffle(SVOp, DAG);
6630 // The checks below are all present in isShuffleMaskLegal, but they are
6631 // inlined here right now to enable us to directly emit target specific
6632 // nodes, and remove one by one until they don't return Op anymore.
6634 if (isPALIGNRMask(M, VT, Subtarget))
6635 return getTargetShuffleNode(X86ISD::PALIGN, dl, VT, V1, V2,
6636 getShufflePALIGNRImmediate(SVOp),
6639 if (ShuffleVectorSDNode::isSplatMask(&M[0], VT) &&
6640 SVOp->getSplatIndex() == 0 && V2IsUndef) {
6641 if (VT == MVT::v2f64 || VT == MVT::v2i64)
6642 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
6645 if (isPSHUFHWMask(M, VT))
6646 return getTargetShuffleNode(X86ISD::PSHUFHW, dl, VT, V1,
6647 X86::getShufflePSHUFHWImmediate(SVOp),
6650 if (isPSHUFLWMask(M, VT))
6651 return getTargetShuffleNode(X86ISD::PSHUFLW, dl, VT, V1,
6652 X86::getShufflePSHUFLWImmediate(SVOp),
6655 if (isSHUFPMask(M, VT, HasAVX))
6656 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V1, V2,
6657 X86::getShuffleSHUFImmediate(SVOp), DAG);
6659 if (isUNPCKL_v_undef_Mask(M, VT, HasAVX2))
6660 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
6661 if (isUNPCKH_v_undef_Mask(M, VT, HasAVX2))
6662 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
6664 //===--------------------------------------------------------------------===//
6665 // Generate target specific nodes for 128 or 256-bit shuffles only
6666 // supported in the AVX instruction set.
6669 // Handle VMOVDDUPY permutations
6670 if (V2IsUndef && isMOVDDUPYMask(M, VT, HasAVX))
6671 return getTargetShuffleNode(X86ISD::MOVDDUP, dl, VT, V1, DAG);
6673 // Handle VPERMILPS/D* permutations
6674 if (isVPERMILPMask(M, VT, HasAVX))
6675 return getTargetShuffleNode(X86ISD::VPERMILP, dl, VT, V1,
6676 getShuffleVPERMILPImmediate(SVOp), DAG);
6678 // Handle VPERM2F128/VPERM2I128 permutations
6679 if (isVPERM2X128Mask(M, VT, HasAVX))
6680 return getTargetShuffleNode(X86ISD::VPERM2X128, dl, VT, V1,
6681 V2, getShuffleVPERM2X128Immediate(SVOp), DAG);
6683 //===--------------------------------------------------------------------===//
6684 // Since no target specific shuffle was selected for this generic one,
6685 // lower it into other known shuffles. FIXME: this isn't true yet, but
6686 // this is the plan.
6689 // Handle v8i16 specifically since SSE can do byte extraction and insertion.
6690 if (VT == MVT::v8i16) {
6691 SDValue NewOp = LowerVECTOR_SHUFFLEv8i16(Op, DAG);
6692 if (NewOp.getNode())
6696 if (VT == MVT::v16i8) {
6697 SDValue NewOp = LowerVECTOR_SHUFFLEv16i8(SVOp, DAG, *this);
6698 if (NewOp.getNode())
6702 // Handle all 128-bit wide vectors with 4 elements, and match them with
6703 // several different shuffle types.
6704 if (NumElems == 4 && VT.getSizeInBits() == 128)
6705 return LowerVECTOR_SHUFFLE_128v4(SVOp, DAG);
6707 // Handle general 256-bit shuffles
6708 if (VT.is256BitVector())
6709 return LowerVECTOR_SHUFFLE_256(SVOp, DAG);
6715 X86TargetLowering::LowerEXTRACT_VECTOR_ELT_SSE4(SDValue Op,
6716 SelectionDAG &DAG) const {
6717 EVT VT = Op.getValueType();
6718 DebugLoc dl = Op.getDebugLoc();
6720 if (Op.getOperand(0).getValueType().getSizeInBits() != 128)
6723 if (VT.getSizeInBits() == 8) {
6724 SDValue Extract = DAG.getNode(X86ISD::PEXTRB, dl, MVT::i32,
6725 Op.getOperand(0), Op.getOperand(1));
6726 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
6727 DAG.getValueType(VT));
6728 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
6729 } else if (VT.getSizeInBits() == 16) {
6730 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
6731 // If Idx is 0, it's cheaper to do a move instead of a pextrw.
6733 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
6734 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
6735 DAG.getNode(ISD::BITCAST, dl,
6739 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, MVT::i32,
6740 Op.getOperand(0), Op.getOperand(1));
6741 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
6742 DAG.getValueType(VT));
6743 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
6744 } else if (VT == MVT::f32) {
6745 // EXTRACTPS outputs to a GPR32 register which will require a movd to copy
6746 // the result back to FR32 register. It's only worth matching if the
6747 // result has a single use which is a store or a bitcast to i32. And in
6748 // the case of a store, it's not worth it if the index is a constant 0,
6749 // because a MOVSSmr can be used instead, which is smaller and faster.
6750 if (!Op.hasOneUse())
6752 SDNode *User = *Op.getNode()->use_begin();
6753 if ((User->getOpcode() != ISD::STORE ||
6754 (isa<ConstantSDNode>(Op.getOperand(1)) &&
6755 cast<ConstantSDNode>(Op.getOperand(1))->isNullValue())) &&
6756 (User->getOpcode() != ISD::BITCAST ||
6757 User->getValueType(0) != MVT::i32))
6759 SDValue Extract = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
6760 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32,
6763 return DAG.getNode(ISD::BITCAST, dl, MVT::f32, Extract);
6764 } else if (VT == MVT::i32 || VT == MVT::i64) {
6765 // ExtractPS/pextrq works with constant index.
6766 if (isa<ConstantSDNode>(Op.getOperand(1)))
6774 X86TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op,
6775 SelectionDAG &DAG) const {
6776 if (!isa<ConstantSDNode>(Op.getOperand(1)))
6779 SDValue Vec = Op.getOperand(0);
6780 EVT VecVT = Vec.getValueType();
6782 // If this is a 256-bit vector result, first extract the 128-bit vector and
6783 // then extract the element from the 128-bit vector.
6784 if (VecVT.getSizeInBits() == 256) {
6785 DebugLoc dl = Op.getNode()->getDebugLoc();
6786 unsigned NumElems = VecVT.getVectorNumElements();
6787 SDValue Idx = Op.getOperand(1);
6788 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
6790 // Get the 128-bit vector.
6791 bool Upper = IdxVal >= NumElems/2;
6792 Vec = Extract128BitVector(Vec,
6793 DAG.getConstant(Upper ? NumElems/2 : 0, MVT::i32), DAG, dl);
6795 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, Op.getValueType(), Vec,
6796 Upper ? DAG.getConstant(IdxVal-NumElems/2, MVT::i32) : Idx);
6799 assert(Vec.getValueSizeInBits() <= 128 && "Unexpected vector length");
6801 if (Subtarget->hasSSE41()) {
6802 SDValue Res = LowerEXTRACT_VECTOR_ELT_SSE4(Op, DAG);
6807 EVT VT = Op.getValueType();
6808 DebugLoc dl = Op.getDebugLoc();
6809 // TODO: handle v16i8.
6810 if (VT.getSizeInBits() == 16) {
6811 SDValue Vec = Op.getOperand(0);
6812 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
6814 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
6815 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
6816 DAG.getNode(ISD::BITCAST, dl,
6819 // Transform it so it match pextrw which produces a 32-bit result.
6820 EVT EltVT = MVT::i32;
6821 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, EltVT,
6822 Op.getOperand(0), Op.getOperand(1));
6823 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, EltVT, Extract,
6824 DAG.getValueType(VT));
6825 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
6826 } else if (VT.getSizeInBits() == 32) {
6827 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
6831 // SHUFPS the element to the lowest double word, then movss.
6832 int Mask[4] = { static_cast<int>(Idx), -1, -1, -1 };
6833 EVT VVT = Op.getOperand(0).getValueType();
6834 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
6835 DAG.getUNDEF(VVT), Mask);
6836 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
6837 DAG.getIntPtrConstant(0));
6838 } else if (VT.getSizeInBits() == 64) {
6839 // FIXME: .td only matches this for <2 x f64>, not <2 x i64> on 32b
6840 // FIXME: seems like this should be unnecessary if mov{h,l}pd were taught
6841 // to match extract_elt for f64.
6842 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
6846 // UNPCKHPD the element to the lowest double word, then movsd.
6847 // Note if the lower 64 bits of the result of the UNPCKHPD is then stored
6848 // to a f64mem, the whole operation is folded into a single MOVHPDmr.
6849 int Mask[2] = { 1, -1 };
6850 EVT VVT = Op.getOperand(0).getValueType();
6851 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
6852 DAG.getUNDEF(VVT), Mask);
6853 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
6854 DAG.getIntPtrConstant(0));
6861 X86TargetLowering::LowerINSERT_VECTOR_ELT_SSE4(SDValue Op,
6862 SelectionDAG &DAG) const {
6863 EVT VT = Op.getValueType();
6864 EVT EltVT = VT.getVectorElementType();
6865 DebugLoc dl = Op.getDebugLoc();
6867 SDValue N0 = Op.getOperand(0);
6868 SDValue N1 = Op.getOperand(1);
6869 SDValue N2 = Op.getOperand(2);
6871 if (VT.getSizeInBits() == 256)
6874 if ((EltVT.getSizeInBits() == 8 || EltVT.getSizeInBits() == 16) &&
6875 isa<ConstantSDNode>(N2)) {
6877 if (VT == MVT::v8i16)
6878 Opc = X86ISD::PINSRW;
6879 else if (VT == MVT::v16i8)
6880 Opc = X86ISD::PINSRB;
6882 Opc = X86ISD::PINSRB;
6884 // Transform it so it match pinsr{b,w} which expects a GR32 as its second
6886 if (N1.getValueType() != MVT::i32)
6887 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
6888 if (N2.getValueType() != MVT::i32)
6889 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue());
6890 return DAG.getNode(Opc, dl, VT, N0, N1, N2);
6891 } else if (EltVT == MVT::f32 && isa<ConstantSDNode>(N2)) {
6892 // Bits [7:6] of the constant are the source select. This will always be
6893 // zero here. The DAG Combiner may combine an extract_elt index into these
6894 // bits. For example (insert (extract, 3), 2) could be matched by putting
6895 // the '3' into bits [7:6] of X86ISD::INSERTPS.
6896 // Bits [5:4] of the constant are the destination select. This is the
6897 // value of the incoming immediate.
6898 // Bits [3:0] of the constant are the zero mask. The DAG Combiner may
6899 // combine either bitwise AND or insert of float 0.0 to set these bits.
6900 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue() << 4);
6901 // Create this as a scalar to vector..
6902 N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4f32, N1);
6903 return DAG.getNode(X86ISD::INSERTPS, dl, VT, N0, N1, N2);
6904 } else if ((EltVT == MVT::i32 || EltVT == MVT::i64) &&
6905 isa<ConstantSDNode>(N2)) {
6906 // PINSR* works with constant index.
6913 X86TargetLowering::LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const {
6914 EVT VT = Op.getValueType();
6915 EVT EltVT = VT.getVectorElementType();
6917 DebugLoc dl = Op.getDebugLoc();
6918 SDValue N0 = Op.getOperand(0);
6919 SDValue N1 = Op.getOperand(1);
6920 SDValue N2 = Op.getOperand(2);
6922 // If this is a 256-bit vector result, first extract the 128-bit vector,
6923 // insert the element into the extracted half and then place it back.
6924 if (VT.getSizeInBits() == 256) {
6925 if (!isa<ConstantSDNode>(N2))
6928 // Get the desired 128-bit vector half.
6929 unsigned NumElems = VT.getVectorNumElements();
6930 unsigned IdxVal = cast<ConstantSDNode>(N2)->getZExtValue();
6931 bool Upper = IdxVal >= NumElems/2;
6932 SDValue Ins128Idx = DAG.getConstant(Upper ? NumElems/2 : 0, MVT::i32);
6933 SDValue V = Extract128BitVector(N0, Ins128Idx, DAG, dl);
6935 // Insert the element into the desired half.
6936 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, V.getValueType(), V,
6937 N1, Upper ? DAG.getConstant(IdxVal-NumElems/2, MVT::i32) : N2);
6939 // Insert the changed part back to the 256-bit vector
6940 return Insert128BitVector(N0, V, Ins128Idx, DAG, dl);
6943 if (Subtarget->hasSSE41())
6944 return LowerINSERT_VECTOR_ELT_SSE4(Op, DAG);
6946 if (EltVT == MVT::i8)
6949 if (EltVT.getSizeInBits() == 16 && isa<ConstantSDNode>(N2)) {
6950 // Transform it so it match pinsrw which expects a 16-bit value in a GR32
6951 // as its second argument.
6952 if (N1.getValueType() != MVT::i32)
6953 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
6954 if (N2.getValueType() != MVT::i32)
6955 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue());
6956 return DAG.getNode(X86ISD::PINSRW, dl, VT, N0, N1, N2);
6962 X86TargetLowering::LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) const {
6963 LLVMContext *Context = DAG.getContext();
6964 DebugLoc dl = Op.getDebugLoc();
6965 EVT OpVT = Op.getValueType();
6967 // If this is a 256-bit vector result, first insert into a 128-bit
6968 // vector and then insert into the 256-bit vector.
6969 if (OpVT.getSizeInBits() > 128) {
6970 // Insert into a 128-bit vector.
6971 EVT VT128 = EVT::getVectorVT(*Context,
6972 OpVT.getVectorElementType(),
6973 OpVT.getVectorNumElements() / 2);
6975 Op = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT128, Op.getOperand(0));
6977 // Insert the 128-bit vector.
6978 return Insert128BitVector(DAG.getNode(ISD::UNDEF, dl, OpVT), Op,
6979 DAG.getConstant(0, MVT::i32),
6983 if (Op.getValueType() == MVT::v1i64 &&
6984 Op.getOperand(0).getValueType() == MVT::i64)
6985 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v1i64, Op.getOperand(0));
6987 SDValue AnyExt = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, Op.getOperand(0));
6988 assert(Op.getValueType().getSimpleVT().getSizeInBits() == 128 &&
6989 "Expected an SSE type!");
6990 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(),
6991 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,AnyExt));
6994 // Lower a node with an EXTRACT_SUBVECTOR opcode. This may result in
6995 // a simple subregister reference or explicit instructions to grab
6996 // upper bits of a vector.
6998 X86TargetLowering::LowerEXTRACT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const {
6999 if (Subtarget->hasAVX()) {
7000 DebugLoc dl = Op.getNode()->getDebugLoc();
7001 SDValue Vec = Op.getNode()->getOperand(0);
7002 SDValue Idx = Op.getNode()->getOperand(1);
7004 if (Op.getNode()->getValueType(0).getSizeInBits() == 128
7005 && Vec.getNode()->getValueType(0).getSizeInBits() == 256) {
7006 return Extract128BitVector(Vec, Idx, DAG, dl);
7012 // Lower a node with an INSERT_SUBVECTOR opcode. This may result in a
7013 // simple superregister reference or explicit instructions to insert
7014 // the upper bits of a vector.
7016 X86TargetLowering::LowerINSERT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const {
7017 if (Subtarget->hasAVX()) {
7018 DebugLoc dl = Op.getNode()->getDebugLoc();
7019 SDValue Vec = Op.getNode()->getOperand(0);
7020 SDValue SubVec = Op.getNode()->getOperand(1);
7021 SDValue Idx = Op.getNode()->getOperand(2);
7023 if (Op.getNode()->getValueType(0).getSizeInBits() == 256
7024 && SubVec.getNode()->getValueType(0).getSizeInBits() == 128) {
7025 return Insert128BitVector(Vec, SubVec, Idx, DAG, dl);
7031 // ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as
7032 // their target countpart wrapped in the X86ISD::Wrapper node. Suppose N is
7033 // one of the above mentioned nodes. It has to be wrapped because otherwise
7034 // Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only
7035 // be used to form addressing mode. These wrapped nodes will be selected
7038 X86TargetLowering::LowerConstantPool(SDValue Op, SelectionDAG &DAG) const {
7039 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
7041 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
7043 unsigned char OpFlag = 0;
7044 unsigned WrapperKind = X86ISD::Wrapper;
7045 CodeModel::Model M = getTargetMachine().getCodeModel();
7047 if (Subtarget->isPICStyleRIPRel() &&
7048 (M == CodeModel::Small || M == CodeModel::Kernel))
7049 WrapperKind = X86ISD::WrapperRIP;
7050 else if (Subtarget->isPICStyleGOT())
7051 OpFlag = X86II::MO_GOTOFF;
7052 else if (Subtarget->isPICStyleStubPIC())
7053 OpFlag = X86II::MO_PIC_BASE_OFFSET;
7055 SDValue Result = DAG.getTargetConstantPool(CP->getConstVal(), getPointerTy(),
7057 CP->getOffset(), OpFlag);
7058 DebugLoc DL = CP->getDebugLoc();
7059 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
7060 // With PIC, the address is actually $g + Offset.
7062 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
7063 DAG.getNode(X86ISD::GlobalBaseReg,
7064 DebugLoc(), getPointerTy()),
7071 SDValue X86TargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) const {
7072 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
7074 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
7076 unsigned char OpFlag = 0;
7077 unsigned WrapperKind = X86ISD::Wrapper;
7078 CodeModel::Model M = getTargetMachine().getCodeModel();
7080 if (Subtarget->isPICStyleRIPRel() &&
7081 (M == CodeModel::Small || M == CodeModel::Kernel))
7082 WrapperKind = X86ISD::WrapperRIP;
7083 else if (Subtarget->isPICStyleGOT())
7084 OpFlag = X86II::MO_GOTOFF;
7085 else if (Subtarget->isPICStyleStubPIC())
7086 OpFlag = X86II::MO_PIC_BASE_OFFSET;
7088 SDValue Result = DAG.getTargetJumpTable(JT->getIndex(), getPointerTy(),
7090 DebugLoc DL = JT->getDebugLoc();
7091 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
7093 // With PIC, the address is actually $g + Offset.
7095 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
7096 DAG.getNode(X86ISD::GlobalBaseReg,
7097 DebugLoc(), getPointerTy()),
7104 X86TargetLowering::LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) const {
7105 const char *Sym = cast<ExternalSymbolSDNode>(Op)->getSymbol();
7107 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
7109 unsigned char OpFlag = 0;
7110 unsigned WrapperKind = X86ISD::Wrapper;
7111 CodeModel::Model M = getTargetMachine().getCodeModel();
7113 if (Subtarget->isPICStyleRIPRel() &&
7114 (M == CodeModel::Small || M == CodeModel::Kernel)) {
7115 if (Subtarget->isTargetDarwin() || Subtarget->isTargetELF())
7116 OpFlag = X86II::MO_GOTPCREL;
7117 WrapperKind = X86ISD::WrapperRIP;
7118 } else if (Subtarget->isPICStyleGOT()) {
7119 OpFlag = X86II::MO_GOT;
7120 } else if (Subtarget->isPICStyleStubPIC()) {
7121 OpFlag = X86II::MO_DARWIN_NONLAZY_PIC_BASE;
7122 } else if (Subtarget->isPICStyleStubNoDynamic()) {
7123 OpFlag = X86II::MO_DARWIN_NONLAZY;
7126 SDValue Result = DAG.getTargetExternalSymbol(Sym, getPointerTy(), OpFlag);
7128 DebugLoc DL = Op.getDebugLoc();
7129 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
7132 // With PIC, the address is actually $g + Offset.
7133 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
7134 !Subtarget->is64Bit()) {
7135 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
7136 DAG.getNode(X86ISD::GlobalBaseReg,
7137 DebugLoc(), getPointerTy()),
7141 // For symbols that require a load from a stub to get the address, emit the
7143 if (isGlobalStubReference(OpFlag))
7144 Result = DAG.getLoad(getPointerTy(), DL, DAG.getEntryNode(), Result,
7145 MachinePointerInfo::getGOT(), false, false, false, 0);
7151 X86TargetLowering::LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const {
7152 // Create the TargetBlockAddressAddress node.
7153 unsigned char OpFlags =
7154 Subtarget->ClassifyBlockAddressReference();
7155 CodeModel::Model M = getTargetMachine().getCodeModel();
7156 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
7157 DebugLoc dl = Op.getDebugLoc();
7158 SDValue Result = DAG.getBlockAddress(BA, getPointerTy(),
7159 /*isTarget=*/true, OpFlags);
7161 if (Subtarget->isPICStyleRIPRel() &&
7162 (M == CodeModel::Small || M == CodeModel::Kernel))
7163 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
7165 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
7167 // With PIC, the address is actually $g + Offset.
7168 if (isGlobalRelativeToPICBase(OpFlags)) {
7169 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
7170 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
7178 X86TargetLowering::LowerGlobalAddress(const GlobalValue *GV, DebugLoc dl,
7180 SelectionDAG &DAG) const {
7181 // Create the TargetGlobalAddress node, folding in the constant
7182 // offset if it is legal.
7183 unsigned char OpFlags =
7184 Subtarget->ClassifyGlobalReference(GV, getTargetMachine());
7185 CodeModel::Model M = getTargetMachine().getCodeModel();
7187 if (OpFlags == X86II::MO_NO_FLAG &&
7188 X86::isOffsetSuitableForCodeModel(Offset, M)) {
7189 // A direct static reference to a global.
7190 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), Offset);
7193 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), 0, OpFlags);
7196 if (Subtarget->isPICStyleRIPRel() &&
7197 (M == CodeModel::Small || M == CodeModel::Kernel))
7198 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
7200 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
7202 // With PIC, the address is actually $g + Offset.
7203 if (isGlobalRelativeToPICBase(OpFlags)) {
7204 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
7205 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
7209 // For globals that require a load from a stub to get the address, emit the
7211 if (isGlobalStubReference(OpFlags))
7212 Result = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Result,
7213 MachinePointerInfo::getGOT(), false, false, false, 0);
7215 // If there was a non-zero offset that we didn't fold, create an explicit
7218 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(), Result,
7219 DAG.getConstant(Offset, getPointerTy()));
7225 X86TargetLowering::LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const {
7226 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
7227 int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset();
7228 return LowerGlobalAddress(GV, Op.getDebugLoc(), Offset, DAG);
7232 GetTLSADDR(SelectionDAG &DAG, SDValue Chain, GlobalAddressSDNode *GA,
7233 SDValue *InFlag, const EVT PtrVT, unsigned ReturnReg,
7234 unsigned char OperandFlags) {
7235 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
7236 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
7237 DebugLoc dl = GA->getDebugLoc();
7238 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
7239 GA->getValueType(0),
7243 SDValue Ops[] = { Chain, TGA, *InFlag };
7244 Chain = DAG.getNode(X86ISD::TLSADDR, dl, NodeTys, Ops, 3);
7246 SDValue Ops[] = { Chain, TGA };
7247 Chain = DAG.getNode(X86ISD::TLSADDR, dl, NodeTys, Ops, 2);
7250 // TLSADDR will be codegen'ed as call. Inform MFI that function has calls.
7251 MFI->setAdjustsStack(true);
7253 SDValue Flag = Chain.getValue(1);
7254 return DAG.getCopyFromReg(Chain, dl, ReturnReg, PtrVT, Flag);
7257 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 32 bit
7259 LowerToTLSGeneralDynamicModel32(GlobalAddressSDNode *GA, SelectionDAG &DAG,
7262 DebugLoc dl = GA->getDebugLoc(); // ? function entry point might be better
7263 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
7264 DAG.getNode(X86ISD::GlobalBaseReg,
7265 DebugLoc(), PtrVT), InFlag);
7266 InFlag = Chain.getValue(1);
7268 return GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX, X86II::MO_TLSGD);
7271 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 64 bit
7273 LowerToTLSGeneralDynamicModel64(GlobalAddressSDNode *GA, SelectionDAG &DAG,
7275 return GetTLSADDR(DAG, DAG.getEntryNode(), GA, NULL, PtrVT,
7276 X86::RAX, X86II::MO_TLSGD);
7279 // Lower ISD::GlobalTLSAddress using the "initial exec" (for no-pic) or
7280 // "local exec" model.
7281 static SDValue LowerToTLSExecModel(GlobalAddressSDNode *GA, SelectionDAG &DAG,
7282 const EVT PtrVT, TLSModel::Model model,
7284 DebugLoc dl = GA->getDebugLoc();
7286 // Get the Thread Pointer, which is %gs:0 (32-bit) or %fs:0 (64-bit).
7287 Value *Ptr = Constant::getNullValue(Type::getInt8PtrTy(*DAG.getContext(),
7288 is64Bit ? 257 : 256));
7290 SDValue ThreadPointer = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
7291 DAG.getIntPtrConstant(0),
7292 MachinePointerInfo(Ptr),
7293 false, false, false, 0);
7295 unsigned char OperandFlags = 0;
7296 // Most TLS accesses are not RIP relative, even on x86-64. One exception is
7298 unsigned WrapperKind = X86ISD::Wrapper;
7299 if (model == TLSModel::LocalExec) {
7300 OperandFlags = is64Bit ? X86II::MO_TPOFF : X86II::MO_NTPOFF;
7301 } else if (is64Bit) {
7302 assert(model == TLSModel::InitialExec);
7303 OperandFlags = X86II::MO_GOTTPOFF;
7304 WrapperKind = X86ISD::WrapperRIP;
7306 assert(model == TLSModel::InitialExec);
7307 OperandFlags = X86II::MO_INDNTPOFF;
7310 // emit "addl x@ntpoff,%eax" (local exec) or "addl x@indntpoff,%eax" (initial
7312 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
7313 GA->getValueType(0),
7314 GA->getOffset(), OperandFlags);
7315 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
7317 if (model == TLSModel::InitialExec)
7318 Offset = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Offset,
7319 MachinePointerInfo::getGOT(), false, false, false, 0);
7321 // The address of the thread local variable is the add of the thread
7322 // pointer with the offset of the variable.
7323 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset);
7327 X86TargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const {
7329 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
7330 const GlobalValue *GV = GA->getGlobal();
7332 if (Subtarget->isTargetELF()) {
7333 // TODO: implement the "local dynamic" model
7334 // TODO: implement the "initial exec"model for pic executables
7336 // If GV is an alias then use the aliasee for determining
7337 // thread-localness.
7338 if (const GlobalAlias *GA = dyn_cast<GlobalAlias>(GV))
7339 GV = GA->resolveAliasedGlobal(false);
7341 TLSModel::Model model
7342 = getTLSModel(GV, getTargetMachine().getRelocationModel());
7345 case TLSModel::GeneralDynamic:
7346 case TLSModel::LocalDynamic: // not implemented
7347 if (Subtarget->is64Bit())
7348 return LowerToTLSGeneralDynamicModel64(GA, DAG, getPointerTy());
7349 return LowerToTLSGeneralDynamicModel32(GA, DAG, getPointerTy());
7351 case TLSModel::InitialExec:
7352 case TLSModel::LocalExec:
7353 return LowerToTLSExecModel(GA, DAG, getPointerTy(), model,
7354 Subtarget->is64Bit());
7356 } else if (Subtarget->isTargetDarwin()) {
7357 // Darwin only has one model of TLS. Lower to that.
7358 unsigned char OpFlag = 0;
7359 unsigned WrapperKind = Subtarget->isPICStyleRIPRel() ?
7360 X86ISD::WrapperRIP : X86ISD::Wrapper;
7362 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
7364 bool PIC32 = (getTargetMachine().getRelocationModel() == Reloc::PIC_) &&
7365 !Subtarget->is64Bit();
7367 OpFlag = X86II::MO_TLVP_PIC_BASE;
7369 OpFlag = X86II::MO_TLVP;
7370 DebugLoc DL = Op.getDebugLoc();
7371 SDValue Result = DAG.getTargetGlobalAddress(GA->getGlobal(), DL,
7372 GA->getValueType(0),
7373 GA->getOffset(), OpFlag);
7374 SDValue Offset = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
7376 // With PIC32, the address is actually $g + Offset.
7378 Offset = DAG.getNode(ISD::ADD, DL, getPointerTy(),
7379 DAG.getNode(X86ISD::GlobalBaseReg,
7380 DebugLoc(), getPointerTy()),
7383 // Lowering the machine isd will make sure everything is in the right
7385 SDValue Chain = DAG.getEntryNode();
7386 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
7387 SDValue Args[] = { Chain, Offset };
7388 Chain = DAG.getNode(X86ISD::TLSCALL, DL, NodeTys, Args, 2);
7390 // TLSCALL will be codegen'ed as call. Inform MFI that function has calls.
7391 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
7392 MFI->setAdjustsStack(true);
7394 // And our return value (tls address) is in the standard call return value
7396 unsigned Reg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
7397 return DAG.getCopyFromReg(Chain, DL, Reg, getPointerTy(),
7401 llvm_unreachable("TLS not implemented for this target.");
7405 /// LowerShiftParts - Lower SRA_PARTS and friends, which return two i32 values
7406 /// and take a 2 x i32 value to shift plus a shift amount.
7407 SDValue X86TargetLowering::LowerShiftParts(SDValue Op, SelectionDAG &DAG) const{
7408 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
7409 EVT VT = Op.getValueType();
7410 unsigned VTBits = VT.getSizeInBits();
7411 DebugLoc dl = Op.getDebugLoc();
7412 bool isSRA = Op.getOpcode() == ISD::SRA_PARTS;
7413 SDValue ShOpLo = Op.getOperand(0);
7414 SDValue ShOpHi = Op.getOperand(1);
7415 SDValue ShAmt = Op.getOperand(2);
7416 SDValue Tmp1 = isSRA ? DAG.getNode(ISD::SRA, dl, VT, ShOpHi,
7417 DAG.getConstant(VTBits - 1, MVT::i8))
7418 : DAG.getConstant(0, VT);
7421 if (Op.getOpcode() == ISD::SHL_PARTS) {
7422 Tmp2 = DAG.getNode(X86ISD::SHLD, dl, VT, ShOpHi, ShOpLo, ShAmt);
7423 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ShAmt);
7425 Tmp2 = DAG.getNode(X86ISD::SHRD, dl, VT, ShOpLo, ShOpHi, ShAmt);
7426 Tmp3 = DAG.getNode(isSRA ? ISD::SRA : ISD::SRL, dl, VT, ShOpHi, ShAmt);
7429 SDValue AndNode = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt,
7430 DAG.getConstant(VTBits, MVT::i8));
7431 SDValue Cond = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
7432 AndNode, DAG.getConstant(0, MVT::i8));
7435 SDValue CC = DAG.getConstant(X86::COND_NE, MVT::i8);
7436 SDValue Ops0[4] = { Tmp2, Tmp3, CC, Cond };
7437 SDValue Ops1[4] = { Tmp3, Tmp1, CC, Cond };
7439 if (Op.getOpcode() == ISD::SHL_PARTS) {
7440 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0, 4);
7441 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1, 4);
7443 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0, 4);
7444 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1, 4);
7447 SDValue Ops[2] = { Lo, Hi };
7448 return DAG.getMergeValues(Ops, 2, dl);
7451 SDValue X86TargetLowering::LowerSINT_TO_FP(SDValue Op,
7452 SelectionDAG &DAG) const {
7453 EVT SrcVT = Op.getOperand(0).getValueType();
7455 if (SrcVT.isVector())
7458 assert(SrcVT.getSimpleVT() <= MVT::i64 && SrcVT.getSimpleVT() >= MVT::i16 &&
7459 "Unknown SINT_TO_FP to lower!");
7461 // These are really Legal; return the operand so the caller accepts it as
7463 if (SrcVT == MVT::i32 && isScalarFPTypeInSSEReg(Op.getValueType()))
7465 if (SrcVT == MVT::i64 && isScalarFPTypeInSSEReg(Op.getValueType()) &&
7466 Subtarget->is64Bit()) {
7470 DebugLoc dl = Op.getDebugLoc();
7471 unsigned Size = SrcVT.getSizeInBits()/8;
7472 MachineFunction &MF = DAG.getMachineFunction();
7473 int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size, false);
7474 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
7475 SDValue Chain = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
7477 MachinePointerInfo::getFixedStack(SSFI),
7479 return BuildFILD(Op, SrcVT, Chain, StackSlot, DAG);
7482 SDValue X86TargetLowering::BuildFILD(SDValue Op, EVT SrcVT, SDValue Chain,
7484 SelectionDAG &DAG) const {
7486 DebugLoc DL = Op.getDebugLoc();
7488 bool useSSE = isScalarFPTypeInSSEReg(Op.getValueType());
7490 Tys = DAG.getVTList(MVT::f64, MVT::Other, MVT::Glue);
7492 Tys = DAG.getVTList(Op.getValueType(), MVT::Other);
7494 unsigned ByteSize = SrcVT.getSizeInBits()/8;
7496 FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(StackSlot);
7497 MachineMemOperand *MMO;
7499 int SSFI = FI->getIndex();
7501 DAG.getMachineFunction()
7502 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
7503 MachineMemOperand::MOLoad, ByteSize, ByteSize);
7505 MMO = cast<LoadSDNode>(StackSlot)->getMemOperand();
7506 StackSlot = StackSlot.getOperand(1);
7508 SDValue Ops[] = { Chain, StackSlot, DAG.getValueType(SrcVT) };
7509 SDValue Result = DAG.getMemIntrinsicNode(useSSE ? X86ISD::FILD_FLAG :
7511 Tys, Ops, array_lengthof(Ops),
7515 Chain = Result.getValue(1);
7516 SDValue InFlag = Result.getValue(2);
7518 // FIXME: Currently the FST is flagged to the FILD_FLAG. This
7519 // shouldn't be necessary except that RFP cannot be live across
7520 // multiple blocks. When stackifier is fixed, they can be uncoupled.
7521 MachineFunction &MF = DAG.getMachineFunction();
7522 unsigned SSFISize = Op.getValueType().getSizeInBits()/8;
7523 int SSFI = MF.getFrameInfo()->CreateStackObject(SSFISize, SSFISize, false);
7524 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
7525 Tys = DAG.getVTList(MVT::Other);
7527 Chain, Result, StackSlot, DAG.getValueType(Op.getValueType()), InFlag
7529 MachineMemOperand *MMO =
7530 DAG.getMachineFunction()
7531 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
7532 MachineMemOperand::MOStore, SSFISize, SSFISize);
7534 Chain = DAG.getMemIntrinsicNode(X86ISD::FST, DL, Tys,
7535 Ops, array_lengthof(Ops),
7536 Op.getValueType(), MMO);
7537 Result = DAG.getLoad(Op.getValueType(), DL, Chain, StackSlot,
7538 MachinePointerInfo::getFixedStack(SSFI),
7539 false, false, false, 0);
7545 // LowerUINT_TO_FP_i64 - 64-bit unsigned integer to double expansion.
7546 SDValue X86TargetLowering::LowerUINT_TO_FP_i64(SDValue Op,
7547 SelectionDAG &DAG) const {
7548 // This algorithm is not obvious. Here it is what we're trying to output:
7551 punpckldq (c0), %xmm0 // c0: (uint4){ 0x43300000U, 0x45300000U, 0U, 0U }
7552 subpd (c1), %xmm0 // c1: (double2){ 0x1.0p52, 0x1.0p52 * 0x1.0p32 }
7556 pshufd $0x4e, %xmm0, %xmm1
7561 DebugLoc dl = Op.getDebugLoc();
7562 LLVMContext *Context = DAG.getContext();
7564 // Build some magic constants.
7565 SmallVector<Constant*,4> CV0;
7566 CV0.push_back(ConstantInt::get(*Context, APInt(32, 0x43300000)));
7567 CV0.push_back(ConstantInt::get(*Context, APInt(32, 0x45300000)));
7568 CV0.push_back(ConstantInt::get(*Context, APInt(32, 0)));
7569 CV0.push_back(ConstantInt::get(*Context, APInt(32, 0)));
7570 Constant *C0 = ConstantVector::get(CV0);
7571 SDValue CPIdx0 = DAG.getConstantPool(C0, getPointerTy(), 16);
7573 SmallVector<Constant*,2> CV1;
7575 ConstantFP::get(*Context, APFloat(APInt(64, 0x4330000000000000ULL))));
7577 ConstantFP::get(*Context, APFloat(APInt(64, 0x4530000000000000ULL))));
7578 Constant *C1 = ConstantVector::get(CV1);
7579 SDValue CPIdx1 = DAG.getConstantPool(C1, getPointerTy(), 16);
7581 // Load the 64-bit value into an XMM register.
7582 SDValue XR1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
7584 SDValue CLod0 = DAG.getLoad(MVT::v4i32, dl, DAG.getEntryNode(), CPIdx0,
7585 MachinePointerInfo::getConstantPool(),
7586 false, false, false, 16);
7587 SDValue Unpck1 = getUnpackl(DAG, dl, MVT::v4i32,
7588 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, XR1),
7591 SDValue CLod1 = DAG.getLoad(MVT::v2f64, dl, CLod0.getValue(1), CPIdx1,
7592 MachinePointerInfo::getConstantPool(),
7593 false, false, false, 16);
7594 SDValue XR2F = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Unpck1);
7595 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, XR2F, CLod1);
7598 if (Subtarget->hasSSE3()) {
7599 // FIXME: The 'haddpd' instruction may be slower than 'movhlps + addsd'.
7600 Result = DAG.getNode(X86ISD::FHADD, dl, MVT::v2f64, Sub, Sub);
7602 SDValue S2F = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Sub);
7603 SDValue Shuffle = getTargetShuffleNode(X86ISD::PSHUFD, dl, MVT::v4i32,
7605 Result = DAG.getNode(ISD::FADD, dl, MVT::v2f64,
7606 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Shuffle),
7610 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Result,
7611 DAG.getIntPtrConstant(0));
7614 // LowerUINT_TO_FP_i32 - 32-bit unsigned integer to float expansion.
7615 SDValue X86TargetLowering::LowerUINT_TO_FP_i32(SDValue Op,
7616 SelectionDAG &DAG) const {
7617 DebugLoc dl = Op.getDebugLoc();
7618 // FP constant to bias correct the final result.
7619 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL),
7622 // Load the 32-bit value into an XMM register.
7623 SDValue Load = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,
7626 // Zero out the upper parts of the register.
7627 Load = getShuffleVectorZeroOrUndef(Load, 0, true, Subtarget, DAG);
7629 Load = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
7630 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Load),
7631 DAG.getIntPtrConstant(0));
7633 // Or the load with the bias.
7634 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64,
7635 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
7636 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
7638 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
7639 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
7640 MVT::v2f64, Bias)));
7641 Or = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
7642 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Or),
7643 DAG.getIntPtrConstant(0));
7645 // Subtract the bias.
7646 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Or, Bias);
7648 // Handle final rounding.
7649 EVT DestVT = Op.getValueType();
7651 if (DestVT.bitsLT(MVT::f64)) {
7652 return DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub,
7653 DAG.getIntPtrConstant(0));
7654 } else if (DestVT.bitsGT(MVT::f64)) {
7655 return DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub);
7658 // Handle final rounding.
7662 SDValue X86TargetLowering::LowerUINT_TO_FP(SDValue Op,
7663 SelectionDAG &DAG) const {
7664 SDValue N0 = Op.getOperand(0);
7665 DebugLoc dl = Op.getDebugLoc();
7667 // Since UINT_TO_FP is legal (it's marked custom), dag combiner won't
7668 // optimize it to a SINT_TO_FP when the sign bit is known zero. Perform
7669 // the optimization here.
7670 if (DAG.SignBitIsZero(N0))
7671 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(), N0);
7673 EVT SrcVT = N0.getValueType();
7674 EVT DstVT = Op.getValueType();
7675 if (SrcVT == MVT::i64 && DstVT == MVT::f64 && X86ScalarSSEf64)
7676 return LowerUINT_TO_FP_i64(Op, DAG);
7677 else if (SrcVT == MVT::i32 && X86ScalarSSEf64)
7678 return LowerUINT_TO_FP_i32(Op, DAG);
7679 else if (Subtarget->is64Bit() &&
7680 SrcVT == MVT::i64 && DstVT == MVT::f32)
7683 // Make a 64-bit buffer, and use it to build an FILD.
7684 SDValue StackSlot = DAG.CreateStackTemporary(MVT::i64);
7685 if (SrcVT == MVT::i32) {
7686 SDValue WordOff = DAG.getConstant(4, getPointerTy());
7687 SDValue OffsetSlot = DAG.getNode(ISD::ADD, dl,
7688 getPointerTy(), StackSlot, WordOff);
7689 SDValue Store1 = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
7690 StackSlot, MachinePointerInfo(),
7692 SDValue Store2 = DAG.getStore(Store1, dl, DAG.getConstant(0, MVT::i32),
7693 OffsetSlot, MachinePointerInfo(),
7695 SDValue Fild = BuildFILD(Op, MVT::i64, Store2, StackSlot, DAG);
7699 assert(SrcVT == MVT::i64 && "Unexpected type in UINT_TO_FP");
7700 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
7701 StackSlot, MachinePointerInfo(),
7703 // For i64 source, we need to add the appropriate power of 2 if the input
7704 // was negative. This is the same as the optimization in
7705 // DAGTypeLegalizer::ExpandIntOp_UNIT_TO_FP, and for it to be safe here,
7706 // we must be careful to do the computation in x87 extended precision, not
7707 // in SSE. (The generic code can't know it's OK to do this, or how to.)
7708 int SSFI = cast<FrameIndexSDNode>(StackSlot)->getIndex();
7709 MachineMemOperand *MMO =
7710 DAG.getMachineFunction()
7711 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
7712 MachineMemOperand::MOLoad, 8, 8);
7714 SDVTList Tys = DAG.getVTList(MVT::f80, MVT::Other);
7715 SDValue Ops[] = { Store, StackSlot, DAG.getValueType(MVT::i64) };
7716 SDValue Fild = DAG.getMemIntrinsicNode(X86ISD::FILD, dl, Tys, Ops, 3,
7719 APInt FF(32, 0x5F800000ULL);
7721 // Check whether the sign bit is set.
7722 SDValue SignSet = DAG.getSetCC(dl, getSetCCResultType(MVT::i64),
7723 Op.getOperand(0), DAG.getConstant(0, MVT::i64),
7726 // Build a 64 bit pair (0, FF) in the constant pool, with FF in the lo bits.
7727 SDValue FudgePtr = DAG.getConstantPool(
7728 ConstantInt::get(*DAG.getContext(), FF.zext(64)),
7731 // Get a pointer to FF if the sign bit was set, or to 0 otherwise.
7732 SDValue Zero = DAG.getIntPtrConstant(0);
7733 SDValue Four = DAG.getIntPtrConstant(4);
7734 SDValue Offset = DAG.getNode(ISD::SELECT, dl, Zero.getValueType(), SignSet,
7736 FudgePtr = DAG.getNode(ISD::ADD, dl, getPointerTy(), FudgePtr, Offset);
7738 // Load the value out, extending it from f32 to f80.
7739 // FIXME: Avoid the extend by constructing the right constant pool?
7740 SDValue Fudge = DAG.getExtLoad(ISD::EXTLOAD, dl, MVT::f80, DAG.getEntryNode(),
7741 FudgePtr, MachinePointerInfo::getConstantPool(),
7742 MVT::f32, false, false, 4);
7743 // Extend everything to 80 bits to force it to be done on x87.
7744 SDValue Add = DAG.getNode(ISD::FADD, dl, MVT::f80, Fild, Fudge);
7745 return DAG.getNode(ISD::FP_ROUND, dl, DstVT, Add, DAG.getIntPtrConstant(0));
7748 std::pair<SDValue,SDValue> X86TargetLowering::
7749 FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG, bool IsSigned) const {
7750 DebugLoc DL = Op.getDebugLoc();
7752 EVT DstTy = Op.getValueType();
7755 assert(DstTy == MVT::i32 && "Unexpected FP_TO_UINT");
7759 assert(DstTy.getSimpleVT() <= MVT::i64 &&
7760 DstTy.getSimpleVT() >= MVT::i16 &&
7761 "Unknown FP_TO_SINT to lower!");
7763 // These are really Legal.
7764 if (DstTy == MVT::i32 &&
7765 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
7766 return std::make_pair(SDValue(), SDValue());
7767 if (Subtarget->is64Bit() &&
7768 DstTy == MVT::i64 &&
7769 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
7770 return std::make_pair(SDValue(), SDValue());
7772 // We lower FP->sint64 into FISTP64, followed by a load, all to a temporary
7774 MachineFunction &MF = DAG.getMachineFunction();
7775 unsigned MemSize = DstTy.getSizeInBits()/8;
7776 int SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
7777 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
7782 switch (DstTy.getSimpleVT().SimpleTy) {
7783 default: llvm_unreachable("Invalid FP_TO_SINT to lower!");
7784 case MVT::i16: Opc = X86ISD::FP_TO_INT16_IN_MEM; break;
7785 case MVT::i32: Opc = X86ISD::FP_TO_INT32_IN_MEM; break;
7786 case MVT::i64: Opc = X86ISD::FP_TO_INT64_IN_MEM; break;
7789 SDValue Chain = DAG.getEntryNode();
7790 SDValue Value = Op.getOperand(0);
7791 EVT TheVT = Op.getOperand(0).getValueType();
7792 if (isScalarFPTypeInSSEReg(TheVT)) {
7793 assert(DstTy == MVT::i64 && "Invalid FP_TO_SINT to lower!");
7794 Chain = DAG.getStore(Chain, DL, Value, StackSlot,
7795 MachinePointerInfo::getFixedStack(SSFI),
7797 SDVTList Tys = DAG.getVTList(Op.getOperand(0).getValueType(), MVT::Other);
7799 Chain, StackSlot, DAG.getValueType(TheVT)
7802 MachineMemOperand *MMO =
7803 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
7804 MachineMemOperand::MOLoad, MemSize, MemSize);
7805 Value = DAG.getMemIntrinsicNode(X86ISD::FLD, DL, Tys, Ops, 3,
7807 Chain = Value.getValue(1);
7808 SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
7809 StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
7812 MachineMemOperand *MMO =
7813 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
7814 MachineMemOperand::MOStore, MemSize, MemSize);
7816 // Build the FP_TO_INT*_IN_MEM
7817 SDValue Ops[] = { Chain, Value, StackSlot };
7818 SDValue FIST = DAG.getMemIntrinsicNode(Opc, DL, DAG.getVTList(MVT::Other),
7819 Ops, 3, DstTy, MMO);
7821 return std::make_pair(FIST, StackSlot);
7824 SDValue X86TargetLowering::LowerFP_TO_SINT(SDValue Op,
7825 SelectionDAG &DAG) const {
7826 if (Op.getValueType().isVector())
7829 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG, true);
7830 SDValue FIST = Vals.first, StackSlot = Vals.second;
7831 // If FP_TO_INTHelper failed, the node is actually supposed to be Legal.
7832 if (FIST.getNode() == 0) return Op;
7835 return DAG.getLoad(Op.getValueType(), Op.getDebugLoc(),
7836 FIST, StackSlot, MachinePointerInfo(),
7837 false, false, false, 0);
7840 SDValue X86TargetLowering::LowerFP_TO_UINT(SDValue Op,
7841 SelectionDAG &DAG) const {
7842 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG, false);
7843 SDValue FIST = Vals.first, StackSlot = Vals.second;
7844 assert(FIST.getNode() && "Unexpected failure");
7847 return DAG.getLoad(Op.getValueType(), Op.getDebugLoc(),
7848 FIST, StackSlot, MachinePointerInfo(),
7849 false, false, false, 0);
7852 SDValue X86TargetLowering::LowerFABS(SDValue Op,
7853 SelectionDAG &DAG) const {
7854 LLVMContext *Context = DAG.getContext();
7855 DebugLoc dl = Op.getDebugLoc();
7856 EVT VT = Op.getValueType();
7859 EltVT = VT.getVectorElementType();
7861 if (EltVT == MVT::f64) {
7862 C = ConstantVector::getSplat(2,
7863 ConstantFP::get(*Context, APFloat(APInt(64, ~(1ULL << 63)))));
7865 C = ConstantVector::getSplat(4,
7866 ConstantFP::get(*Context, APFloat(APInt(32, ~(1U << 31)))));
7868 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
7869 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
7870 MachinePointerInfo::getConstantPool(),
7871 false, false, false, 16);
7872 return DAG.getNode(X86ISD::FAND, dl, VT, Op.getOperand(0), Mask);
7875 SDValue X86TargetLowering::LowerFNEG(SDValue Op, SelectionDAG &DAG) const {
7876 LLVMContext *Context = DAG.getContext();
7877 DebugLoc dl = Op.getDebugLoc();
7878 EVT VT = Op.getValueType();
7880 unsigned NumElts = VT == MVT::f64 ? 2 : 4;
7881 if (VT.isVector()) {
7882 EltVT = VT.getVectorElementType();
7883 NumElts = VT.getVectorNumElements();
7886 if (EltVT == MVT::f64)
7887 C = ConstantFP::get(*Context, APFloat(APInt(64, 1ULL << 63)));
7889 C = ConstantFP::get(*Context, APFloat(APInt(32, 1U << 31)));
7890 C = ConstantVector::getSplat(NumElts, C);
7891 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
7892 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
7893 MachinePointerInfo::getConstantPool(),
7894 false, false, false, 16);
7895 if (VT.isVector()) {
7896 MVT XORVT = VT.getSizeInBits() == 128 ? MVT::v2i64 : MVT::v4i64;
7897 return DAG.getNode(ISD::BITCAST, dl, VT,
7898 DAG.getNode(ISD::XOR, dl, XORVT,
7899 DAG.getNode(ISD::BITCAST, dl, XORVT,
7901 DAG.getNode(ISD::BITCAST, dl, XORVT, Mask)));
7903 return DAG.getNode(X86ISD::FXOR, dl, VT, Op.getOperand(0), Mask);
7907 SDValue X86TargetLowering::LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const {
7908 LLVMContext *Context = DAG.getContext();
7909 SDValue Op0 = Op.getOperand(0);
7910 SDValue Op1 = Op.getOperand(1);
7911 DebugLoc dl = Op.getDebugLoc();
7912 EVT VT = Op.getValueType();
7913 EVT SrcVT = Op1.getValueType();
7915 // If second operand is smaller, extend it first.
7916 if (SrcVT.bitsLT(VT)) {
7917 Op1 = DAG.getNode(ISD::FP_EXTEND, dl, VT, Op1);
7920 // And if it is bigger, shrink it first.
7921 if (SrcVT.bitsGT(VT)) {
7922 Op1 = DAG.getNode(ISD::FP_ROUND, dl, VT, Op1, DAG.getIntPtrConstant(1));
7926 // At this point the operands and the result should have the same
7927 // type, and that won't be f80 since that is not custom lowered.
7929 // First get the sign bit of second operand.
7930 SmallVector<Constant*,4> CV;
7931 if (SrcVT == MVT::f64) {
7932 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, 1ULL << 63))));
7933 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, 0))));
7935 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 1U << 31))));
7936 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
7937 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
7938 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
7940 Constant *C = ConstantVector::get(CV);
7941 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
7942 SDValue Mask1 = DAG.getLoad(SrcVT, dl, DAG.getEntryNode(), CPIdx,
7943 MachinePointerInfo::getConstantPool(),
7944 false, false, false, 16);
7945 SDValue SignBit = DAG.getNode(X86ISD::FAND, dl, SrcVT, Op1, Mask1);
7947 // Shift sign bit right or left if the two operands have different types.
7948 if (SrcVT.bitsGT(VT)) {
7949 // Op0 is MVT::f32, Op1 is MVT::f64.
7950 SignBit = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f64, SignBit);
7951 SignBit = DAG.getNode(X86ISD::FSRL, dl, MVT::v2f64, SignBit,
7952 DAG.getConstant(32, MVT::i32));
7953 SignBit = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, SignBit);
7954 SignBit = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f32, SignBit,
7955 DAG.getIntPtrConstant(0));
7958 // Clear first operand sign bit.
7960 if (VT == MVT::f64) {
7961 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, ~(1ULL << 63)))));
7962 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, 0))));
7964 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, ~(1U << 31)))));
7965 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
7966 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
7967 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
7969 C = ConstantVector::get(CV);
7970 CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
7971 SDValue Mask2 = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
7972 MachinePointerInfo::getConstantPool(),
7973 false, false, false, 16);
7974 SDValue Val = DAG.getNode(X86ISD::FAND, dl, VT, Op0, Mask2);
7976 // Or the value with the sign bit.
7977 return DAG.getNode(X86ISD::FOR, dl, VT, Val, SignBit);
7980 SDValue X86TargetLowering::LowerFGETSIGN(SDValue Op, SelectionDAG &DAG) const {
7981 SDValue N0 = Op.getOperand(0);
7982 DebugLoc dl = Op.getDebugLoc();
7983 EVT VT = Op.getValueType();
7985 // Lower ISD::FGETSIGN to (AND (X86ISD::FGETSIGNx86 ...) 1).
7986 SDValue xFGETSIGN = DAG.getNode(X86ISD::FGETSIGNx86, dl, VT, N0,
7987 DAG.getConstant(1, VT));
7988 return DAG.getNode(ISD::AND, dl, VT, xFGETSIGN, DAG.getConstant(1, VT));
7991 /// Emit nodes that will be selected as "test Op0,Op0", or something
7993 SDValue X86TargetLowering::EmitTest(SDValue Op, unsigned X86CC,
7994 SelectionDAG &DAG) const {
7995 DebugLoc dl = Op.getDebugLoc();
7997 // CF and OF aren't always set the way we want. Determine which
7998 // of these we need.
7999 bool NeedCF = false;
8000 bool NeedOF = false;
8003 case X86::COND_A: case X86::COND_AE:
8004 case X86::COND_B: case X86::COND_BE:
8007 case X86::COND_G: case X86::COND_GE:
8008 case X86::COND_L: case X86::COND_LE:
8009 case X86::COND_O: case X86::COND_NO:
8014 // See if we can use the EFLAGS value from the operand instead of
8015 // doing a separate TEST. TEST always sets OF and CF to 0, so unless
8016 // we prove that the arithmetic won't overflow, we can't use OF or CF.
8017 if (Op.getResNo() != 0 || NeedOF || NeedCF)
8018 // Emit a CMP with 0, which is the TEST pattern.
8019 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
8020 DAG.getConstant(0, Op.getValueType()));
8022 unsigned Opcode = 0;
8023 unsigned NumOperands = 0;
8024 switch (Op.getNode()->getOpcode()) {
8026 // Due to an isel shortcoming, be conservative if this add is likely to be
8027 // selected as part of a load-modify-store instruction. When the root node
8028 // in a match is a store, isel doesn't know how to remap non-chain non-flag
8029 // uses of other nodes in the match, such as the ADD in this case. This
8030 // leads to the ADD being left around and reselected, with the result being
8031 // two adds in the output. Alas, even if none our users are stores, that
8032 // doesn't prove we're O.K. Ergo, if we have any parents that aren't
8033 // CopyToReg or SETCC, eschew INC/DEC. A better fix seems to require
8034 // climbing the DAG back to the root, and it doesn't seem to be worth the
8036 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
8037 UE = Op.getNode()->use_end(); UI != UE; ++UI)
8038 if (UI->getOpcode() != ISD::CopyToReg &&
8039 UI->getOpcode() != ISD::SETCC &&
8040 UI->getOpcode() != ISD::STORE)
8043 if (ConstantSDNode *C =
8044 dyn_cast<ConstantSDNode>(Op.getNode()->getOperand(1))) {
8045 // An add of one will be selected as an INC.
8046 if (C->getAPIntValue() == 1) {
8047 Opcode = X86ISD::INC;
8052 // An add of negative one (subtract of one) will be selected as a DEC.
8053 if (C->getAPIntValue().isAllOnesValue()) {
8054 Opcode = X86ISD::DEC;
8060 // Otherwise use a regular EFLAGS-setting add.
8061 Opcode = X86ISD::ADD;
8065 // If the primary and result isn't used, don't bother using X86ISD::AND,
8066 // because a TEST instruction will be better.
8067 bool NonFlagUse = false;
8068 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
8069 UE = Op.getNode()->use_end(); UI != UE; ++UI) {
8071 unsigned UOpNo = UI.getOperandNo();
8072 if (User->getOpcode() == ISD::TRUNCATE && User->hasOneUse()) {
8073 // Look pass truncate.
8074 UOpNo = User->use_begin().getOperandNo();
8075 User = *User->use_begin();
8078 if (User->getOpcode() != ISD::BRCOND &&
8079 User->getOpcode() != ISD::SETCC &&
8080 (User->getOpcode() != ISD::SELECT || UOpNo != 0)) {
8093 // Due to the ISEL shortcoming noted above, be conservative if this op is
8094 // likely to be selected as part of a load-modify-store instruction.
8095 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
8096 UE = Op.getNode()->use_end(); UI != UE; ++UI)
8097 if (UI->getOpcode() == ISD::STORE)
8100 // Otherwise use a regular EFLAGS-setting instruction.
8101 switch (Op.getNode()->getOpcode()) {
8102 default: llvm_unreachable("unexpected operator!");
8103 case ISD::SUB: Opcode = X86ISD::SUB; break;
8104 case ISD::OR: Opcode = X86ISD::OR; break;
8105 case ISD::XOR: Opcode = X86ISD::XOR; break;
8106 case ISD::AND: Opcode = X86ISD::AND; break;
8118 return SDValue(Op.getNode(), 1);
8125 // Emit a CMP with 0, which is the TEST pattern.
8126 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
8127 DAG.getConstant(0, Op.getValueType()));
8129 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
8130 SmallVector<SDValue, 4> Ops;
8131 for (unsigned i = 0; i != NumOperands; ++i)
8132 Ops.push_back(Op.getOperand(i));
8134 SDValue New = DAG.getNode(Opcode, dl, VTs, &Ops[0], NumOperands);
8135 DAG.ReplaceAllUsesWith(Op, New);
8136 return SDValue(New.getNode(), 1);
8139 /// Emit nodes that will be selected as "cmp Op0,Op1", or something
8141 SDValue X86TargetLowering::EmitCmp(SDValue Op0, SDValue Op1, unsigned X86CC,
8142 SelectionDAG &DAG) const {
8143 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op1))
8144 if (C->getAPIntValue() == 0)
8145 return EmitTest(Op0, X86CC, DAG);
8147 DebugLoc dl = Op0.getDebugLoc();
8148 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op0, Op1);
8151 /// LowerToBT - Result of 'and' is compared against zero. Turn it into a BT node
8152 /// if it's possible.
8153 SDValue X86TargetLowering::LowerToBT(SDValue And, ISD::CondCode CC,
8154 DebugLoc dl, SelectionDAG &DAG) const {
8155 SDValue Op0 = And.getOperand(0);
8156 SDValue Op1 = And.getOperand(1);
8157 if (Op0.getOpcode() == ISD::TRUNCATE)
8158 Op0 = Op0.getOperand(0);
8159 if (Op1.getOpcode() == ISD::TRUNCATE)
8160 Op1 = Op1.getOperand(0);
8163 if (Op1.getOpcode() == ISD::SHL)
8164 std::swap(Op0, Op1);
8165 if (Op0.getOpcode() == ISD::SHL) {
8166 if (ConstantSDNode *And00C = dyn_cast<ConstantSDNode>(Op0.getOperand(0)))
8167 if (And00C->getZExtValue() == 1) {
8168 // If we looked past a truncate, check that it's only truncating away
8170 unsigned BitWidth = Op0.getValueSizeInBits();
8171 unsigned AndBitWidth = And.getValueSizeInBits();
8172 if (BitWidth > AndBitWidth) {
8173 APInt Mask = APInt::getAllOnesValue(BitWidth), Zeros, Ones;
8174 DAG.ComputeMaskedBits(Op0, Mask, Zeros, Ones);
8175 if (Zeros.countLeadingOnes() < BitWidth - AndBitWidth)
8179 RHS = Op0.getOperand(1);
8181 } else if (Op1.getOpcode() == ISD::Constant) {
8182 ConstantSDNode *AndRHS = cast<ConstantSDNode>(Op1);
8183 uint64_t AndRHSVal = AndRHS->getZExtValue();
8184 SDValue AndLHS = Op0;
8186 if (AndRHSVal == 1 && AndLHS.getOpcode() == ISD::SRL) {
8187 LHS = AndLHS.getOperand(0);
8188 RHS = AndLHS.getOperand(1);
8191 // Use BT if the immediate can't be encoded in a TEST instruction.
8192 if (!isUInt<32>(AndRHSVal) && isPowerOf2_64(AndRHSVal)) {
8194 RHS = DAG.getConstant(Log2_64_Ceil(AndRHSVal), LHS.getValueType());
8198 if (LHS.getNode()) {
8199 // If LHS is i8, promote it to i32 with any_extend. There is no i8 BT
8200 // instruction. Since the shift amount is in-range-or-undefined, we know
8201 // that doing a bittest on the i32 value is ok. We extend to i32 because
8202 // the encoding for the i16 version is larger than the i32 version.
8203 // Also promote i16 to i32 for performance / code size reason.
8204 if (LHS.getValueType() == MVT::i8 ||
8205 LHS.getValueType() == MVT::i16)
8206 LHS = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, LHS);
8208 // If the operand types disagree, extend the shift amount to match. Since
8209 // BT ignores high bits (like shifts) we can use anyextend.
8210 if (LHS.getValueType() != RHS.getValueType())
8211 RHS = DAG.getNode(ISD::ANY_EXTEND, dl, LHS.getValueType(), RHS);
8213 SDValue BT = DAG.getNode(X86ISD::BT, dl, MVT::i32, LHS, RHS);
8214 unsigned Cond = CC == ISD::SETEQ ? X86::COND_AE : X86::COND_B;
8215 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
8216 DAG.getConstant(Cond, MVT::i8), BT);
8222 SDValue X86TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
8224 if (Op.getValueType().isVector()) return LowerVSETCC(Op, DAG);
8226 assert(Op.getValueType() == MVT::i8 && "SetCC type must be 8-bit integer");
8227 SDValue Op0 = Op.getOperand(0);
8228 SDValue Op1 = Op.getOperand(1);
8229 DebugLoc dl = Op.getDebugLoc();
8230 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
8232 // Optimize to BT if possible.
8233 // Lower (X & (1 << N)) == 0 to BT(X, N).
8234 // Lower ((X >>u N) & 1) != 0 to BT(X, N).
8235 // Lower ((X >>s N) & 1) != 0 to BT(X, N).
8236 if (Op0.getOpcode() == ISD::AND && Op0.hasOneUse() &&
8237 Op1.getOpcode() == ISD::Constant &&
8238 cast<ConstantSDNode>(Op1)->isNullValue() &&
8239 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
8240 SDValue NewSetCC = LowerToBT(Op0, CC, dl, DAG);
8241 if (NewSetCC.getNode())
8245 // Look for X == 0, X == 1, X != 0, or X != 1. We can simplify some forms of
8247 if (Op1.getOpcode() == ISD::Constant &&
8248 (cast<ConstantSDNode>(Op1)->getZExtValue() == 1 ||
8249 cast<ConstantSDNode>(Op1)->isNullValue()) &&
8250 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
8252 // If the input is a setcc, then reuse the input setcc or use a new one with
8253 // the inverted condition.
8254 if (Op0.getOpcode() == X86ISD::SETCC) {
8255 X86::CondCode CCode = (X86::CondCode)Op0.getConstantOperandVal(0);
8256 bool Invert = (CC == ISD::SETNE) ^
8257 cast<ConstantSDNode>(Op1)->isNullValue();
8258 if (!Invert) return Op0;
8260 CCode = X86::GetOppositeBranchCondition(CCode);
8261 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
8262 DAG.getConstant(CCode, MVT::i8), Op0.getOperand(1));
8266 bool isFP = Op1.getValueType().isFloatingPoint();
8267 unsigned X86CC = TranslateX86CC(CC, isFP, Op0, Op1, DAG);
8268 if (X86CC == X86::COND_INVALID)
8271 SDValue EFLAGS = EmitCmp(Op0, Op1, X86CC, DAG);
8272 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
8273 DAG.getConstant(X86CC, MVT::i8), EFLAGS);
8276 // Lower256IntVSETCC - Break a VSETCC 256-bit integer VSETCC into two new 128
8277 // ones, and then concatenate the result back.
8278 static SDValue Lower256IntVSETCC(SDValue Op, SelectionDAG &DAG) {
8279 EVT VT = Op.getValueType();
8281 assert(VT.getSizeInBits() == 256 && Op.getOpcode() == ISD::SETCC &&
8282 "Unsupported value type for operation");
8284 int NumElems = VT.getVectorNumElements();
8285 DebugLoc dl = Op.getDebugLoc();
8286 SDValue CC = Op.getOperand(2);
8287 SDValue Idx0 = DAG.getConstant(0, MVT::i32);
8288 SDValue Idx1 = DAG.getConstant(NumElems/2, MVT::i32);
8290 // Extract the LHS vectors
8291 SDValue LHS = Op.getOperand(0);
8292 SDValue LHS1 = Extract128BitVector(LHS, Idx0, DAG, dl);
8293 SDValue LHS2 = Extract128BitVector(LHS, Idx1, DAG, dl);
8295 // Extract the RHS vectors
8296 SDValue RHS = Op.getOperand(1);
8297 SDValue RHS1 = Extract128BitVector(RHS, Idx0, DAG, dl);
8298 SDValue RHS2 = Extract128BitVector(RHS, Idx1, DAG, dl);
8300 // Issue the operation on the smaller types and concatenate the result back
8301 MVT EltVT = VT.getVectorElementType().getSimpleVT();
8302 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
8303 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
8304 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1, CC),
8305 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2, CC));
8309 SDValue X86TargetLowering::LowerVSETCC(SDValue Op, SelectionDAG &DAG) const {
8311 SDValue Op0 = Op.getOperand(0);
8312 SDValue Op1 = Op.getOperand(1);
8313 SDValue CC = Op.getOperand(2);
8314 EVT VT = Op.getValueType();
8315 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
8316 bool isFP = Op.getOperand(1).getValueType().isFloatingPoint();
8317 DebugLoc dl = Op.getDebugLoc();
8321 EVT EltVT = Op0.getValueType().getVectorElementType();
8322 assert(EltVT == MVT::f32 || EltVT == MVT::f64);
8326 // SSE Condition code mapping:
8335 switch (SetCCOpcode) {
8338 case ISD::SETEQ: SSECC = 0; break;
8340 case ISD::SETGT: Swap = true; // Fallthrough
8342 case ISD::SETOLT: SSECC = 1; break;
8344 case ISD::SETGE: Swap = true; // Fallthrough
8346 case ISD::SETOLE: SSECC = 2; break;
8347 case ISD::SETUO: SSECC = 3; break;
8349 case ISD::SETNE: SSECC = 4; break;
8350 case ISD::SETULE: Swap = true;
8351 case ISD::SETUGE: SSECC = 5; break;
8352 case ISD::SETULT: Swap = true;
8353 case ISD::SETUGT: SSECC = 6; break;
8354 case ISD::SETO: SSECC = 7; break;
8357 std::swap(Op0, Op1);
8359 // In the two special cases we can't handle, emit two comparisons.
8361 if (SetCCOpcode == ISD::SETUEQ) {
8363 UNORD = DAG.getNode(X86ISD::CMPP, dl, VT, Op0, Op1,
8364 DAG.getConstant(3, MVT::i8));
8365 EQ = DAG.getNode(X86ISD::CMPP, dl, VT, Op0, Op1,
8366 DAG.getConstant(0, MVT::i8));
8367 return DAG.getNode(ISD::OR, dl, VT, UNORD, EQ);
8368 } else if (SetCCOpcode == ISD::SETONE) {
8370 ORD = DAG.getNode(X86ISD::CMPP, dl, VT, Op0, Op1,
8371 DAG.getConstant(7, MVT::i8));
8372 NEQ = DAG.getNode(X86ISD::CMPP, dl, VT, Op0, Op1,
8373 DAG.getConstant(4, MVT::i8));
8374 return DAG.getNode(ISD::AND, dl, VT, ORD, NEQ);
8376 llvm_unreachable("Illegal FP comparison");
8378 // Handle all other FP comparisons here.
8379 return DAG.getNode(X86ISD::CMPP, dl, VT, Op0, Op1,
8380 DAG.getConstant(SSECC, MVT::i8));
8383 // Break 256-bit integer vector compare into smaller ones.
8384 if (VT.getSizeInBits() == 256 && !Subtarget->hasAVX2())
8385 return Lower256IntVSETCC(Op, DAG);
8387 // We are handling one of the integer comparisons here. Since SSE only has
8388 // GT and EQ comparisons for integer, swapping operands and multiple
8389 // operations may be required for some comparisons.
8391 bool Swap = false, Invert = false, FlipSigns = false;
8393 switch (SetCCOpcode) {
8395 case ISD::SETNE: Invert = true;
8396 case ISD::SETEQ: Opc = X86ISD::PCMPEQ; break;
8397 case ISD::SETLT: Swap = true;
8398 case ISD::SETGT: Opc = X86ISD::PCMPGT; break;
8399 case ISD::SETGE: Swap = true;
8400 case ISD::SETLE: Opc = X86ISD::PCMPGT; Invert = true; break;
8401 case ISD::SETULT: Swap = true;
8402 case ISD::SETUGT: Opc = X86ISD::PCMPGT; FlipSigns = true; break;
8403 case ISD::SETUGE: Swap = true;
8404 case ISD::SETULE: Opc = X86ISD::PCMPGT; FlipSigns = true; Invert = true; break;
8407 std::swap(Op0, Op1);
8409 // Check that the operation in question is available (most are plain SSE2,
8410 // but PCMPGTQ and PCMPEQQ have different requirements).
8411 if (Opc == X86ISD::PCMPGT && VT == MVT::v2i64 && !Subtarget->hasSSE42())
8413 if (Opc == X86ISD::PCMPEQ && VT == MVT::v2i64 && !Subtarget->hasSSE41())
8416 // Since SSE has no unsigned integer comparisons, we need to flip the sign
8417 // bits of the inputs before performing those operations.
8419 EVT EltVT = VT.getVectorElementType();
8420 SDValue SignBit = DAG.getConstant(APInt::getSignBit(EltVT.getSizeInBits()),
8422 std::vector<SDValue> SignBits(VT.getVectorNumElements(), SignBit);
8423 SDValue SignVec = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &SignBits[0],
8425 Op0 = DAG.getNode(ISD::XOR, dl, VT, Op0, SignVec);
8426 Op1 = DAG.getNode(ISD::XOR, dl, VT, Op1, SignVec);
8429 SDValue Result = DAG.getNode(Opc, dl, VT, Op0, Op1);
8431 // If the logical-not of the result is required, perform that now.
8433 Result = DAG.getNOT(dl, Result, VT);
8438 // isX86LogicalCmp - Return true if opcode is a X86 logical comparison.
8439 static bool isX86LogicalCmp(SDValue Op) {
8440 unsigned Opc = Op.getNode()->getOpcode();
8441 if (Opc == X86ISD::CMP || Opc == X86ISD::COMI || Opc == X86ISD::UCOMI)
8443 if (Op.getResNo() == 1 &&
8444 (Opc == X86ISD::ADD ||
8445 Opc == X86ISD::SUB ||
8446 Opc == X86ISD::ADC ||
8447 Opc == X86ISD::SBB ||
8448 Opc == X86ISD::SMUL ||
8449 Opc == X86ISD::UMUL ||
8450 Opc == X86ISD::INC ||
8451 Opc == X86ISD::DEC ||
8452 Opc == X86ISD::OR ||
8453 Opc == X86ISD::XOR ||
8454 Opc == X86ISD::AND))
8457 if (Op.getResNo() == 2 && Opc == X86ISD::UMUL)
8463 static bool isZero(SDValue V) {
8464 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V);
8465 return C && C->isNullValue();
8468 static bool isAllOnes(SDValue V) {
8469 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V);
8470 return C && C->isAllOnesValue();
8473 SDValue X86TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {
8474 bool addTest = true;
8475 SDValue Cond = Op.getOperand(0);
8476 SDValue Op1 = Op.getOperand(1);
8477 SDValue Op2 = Op.getOperand(2);
8478 DebugLoc DL = Op.getDebugLoc();
8481 if (Cond.getOpcode() == ISD::SETCC) {
8482 SDValue NewCond = LowerSETCC(Cond, DAG);
8483 if (NewCond.getNode())
8487 // (select (x == 0), -1, y) -> (sign_bit (x - 1)) | y
8488 // (select (x == 0), y, -1) -> ~(sign_bit (x - 1)) | y
8489 // (select (x != 0), y, -1) -> (sign_bit (x - 1)) | y
8490 // (select (x != 0), -1, y) -> ~(sign_bit (x - 1)) | y
8491 if (Cond.getOpcode() == X86ISD::SETCC &&
8492 Cond.getOperand(1).getOpcode() == X86ISD::CMP &&
8493 isZero(Cond.getOperand(1).getOperand(1))) {
8494 SDValue Cmp = Cond.getOperand(1);
8496 unsigned CondCode =cast<ConstantSDNode>(Cond.getOperand(0))->getZExtValue();
8498 if ((isAllOnes(Op1) || isAllOnes(Op2)) &&
8499 (CondCode == X86::COND_E || CondCode == X86::COND_NE)) {
8500 SDValue Y = isAllOnes(Op2) ? Op1 : Op2;
8502 SDValue CmpOp0 = Cmp.getOperand(0);
8503 Cmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32,
8504 CmpOp0, DAG.getConstant(1, CmpOp0.getValueType()));
8506 SDValue Res = // Res = 0 or -1.
8507 DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
8508 DAG.getConstant(X86::COND_B, MVT::i8), Cmp);
8510 if (isAllOnes(Op1) != (CondCode == X86::COND_E))
8511 Res = DAG.getNOT(DL, Res, Res.getValueType());
8513 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(Op2);
8514 if (N2C == 0 || !N2C->isNullValue())
8515 Res = DAG.getNode(ISD::OR, DL, Res.getValueType(), Res, Y);
8520 // Look past (and (setcc_carry (cmp ...)), 1).
8521 if (Cond.getOpcode() == ISD::AND &&
8522 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
8523 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
8524 if (C && C->getAPIntValue() == 1)
8525 Cond = Cond.getOperand(0);
8528 // If condition flag is set by a X86ISD::CMP, then use it as the condition
8529 // setting operand in place of the X86ISD::SETCC.
8530 unsigned CondOpcode = Cond.getOpcode();
8531 if (CondOpcode == X86ISD::SETCC ||
8532 CondOpcode == X86ISD::SETCC_CARRY) {
8533 CC = Cond.getOperand(0);
8535 SDValue Cmp = Cond.getOperand(1);
8536 unsigned Opc = Cmp.getOpcode();
8537 EVT VT = Op.getValueType();
8539 bool IllegalFPCMov = false;
8540 if (VT.isFloatingPoint() && !VT.isVector() &&
8541 !isScalarFPTypeInSSEReg(VT)) // FPStack?
8542 IllegalFPCMov = !hasFPCMov(cast<ConstantSDNode>(CC)->getSExtValue());
8544 if ((isX86LogicalCmp(Cmp) && !IllegalFPCMov) ||
8545 Opc == X86ISD::BT) { // FIXME
8549 } else if (CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO ||
8550 CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO ||
8551 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) &&
8552 Cond.getOperand(0).getValueType() != MVT::i8)) {
8553 SDValue LHS = Cond.getOperand(0);
8554 SDValue RHS = Cond.getOperand(1);
8558 switch (CondOpcode) {
8559 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break;
8560 case ISD::SADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break;
8561 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break;
8562 case ISD::SSUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break;
8563 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break;
8564 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break;
8565 default: llvm_unreachable("unexpected overflowing operator");
8567 if (CondOpcode == ISD::UMULO)
8568 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(),
8571 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
8573 SDValue X86Op = DAG.getNode(X86Opcode, DL, VTs, LHS, RHS);
8575 if (CondOpcode == ISD::UMULO)
8576 Cond = X86Op.getValue(2);
8578 Cond = X86Op.getValue(1);
8580 CC = DAG.getConstant(X86Cond, MVT::i8);
8585 // Look pass the truncate.
8586 if (Cond.getOpcode() == ISD::TRUNCATE)
8587 Cond = Cond.getOperand(0);
8589 // We know the result of AND is compared against zero. Try to match
8591 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
8592 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, DL, DAG);
8593 if (NewSetCC.getNode()) {
8594 CC = NewSetCC.getOperand(0);
8595 Cond = NewSetCC.getOperand(1);
8602 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
8603 Cond = EmitTest(Cond, X86::COND_NE, DAG);
8606 // a < b ? -1 : 0 -> RES = ~setcc_carry
8607 // a < b ? 0 : -1 -> RES = setcc_carry
8608 // a >= b ? -1 : 0 -> RES = setcc_carry
8609 // a >= b ? 0 : -1 -> RES = ~setcc_carry
8610 if (Cond.getOpcode() == X86ISD::CMP) {
8611 unsigned CondCode = cast<ConstantSDNode>(CC)->getZExtValue();
8613 if ((CondCode == X86::COND_AE || CondCode == X86::COND_B) &&
8614 (isAllOnes(Op1) || isAllOnes(Op2)) && (isZero(Op1) || isZero(Op2))) {
8615 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
8616 DAG.getConstant(X86::COND_B, MVT::i8), Cond);
8617 if (isAllOnes(Op1) != (CondCode == X86::COND_B))
8618 return DAG.getNOT(DL, Res, Res.getValueType());
8623 // X86ISD::CMOV means set the result (which is operand 1) to the RHS if
8624 // condition is true.
8625 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue);
8626 SDValue Ops[] = { Op2, Op1, CC, Cond };
8627 return DAG.getNode(X86ISD::CMOV, DL, VTs, Ops, array_lengthof(Ops));
8630 // isAndOrOfSingleUseSetCCs - Return true if node is an ISD::AND or
8631 // ISD::OR of two X86ISD::SETCC nodes each of which has no other use apart
8632 // from the AND / OR.
8633 static bool isAndOrOfSetCCs(SDValue Op, unsigned &Opc) {
8634 Opc = Op.getOpcode();
8635 if (Opc != ISD::OR && Opc != ISD::AND)
8637 return (Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
8638 Op.getOperand(0).hasOneUse() &&
8639 Op.getOperand(1).getOpcode() == X86ISD::SETCC &&
8640 Op.getOperand(1).hasOneUse());
8643 // isXor1OfSetCC - Return true if node is an ISD::XOR of a X86ISD::SETCC and
8644 // 1 and that the SETCC node has a single use.
8645 static bool isXor1OfSetCC(SDValue Op) {
8646 if (Op.getOpcode() != ISD::XOR)
8648 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
8649 if (N1C && N1C->getAPIntValue() == 1) {
8650 return Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
8651 Op.getOperand(0).hasOneUse();
8656 SDValue X86TargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) const {
8657 bool addTest = true;
8658 SDValue Chain = Op.getOperand(0);
8659 SDValue Cond = Op.getOperand(1);
8660 SDValue Dest = Op.getOperand(2);
8661 DebugLoc dl = Op.getDebugLoc();
8663 bool Inverted = false;
8665 if (Cond.getOpcode() == ISD::SETCC) {
8666 // Check for setcc([su]{add,sub,mul}o == 0).
8667 if (cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETEQ &&
8668 isa<ConstantSDNode>(Cond.getOperand(1)) &&
8669 cast<ConstantSDNode>(Cond.getOperand(1))->isNullValue() &&
8670 Cond.getOperand(0).getResNo() == 1 &&
8671 (Cond.getOperand(0).getOpcode() == ISD::SADDO ||
8672 Cond.getOperand(0).getOpcode() == ISD::UADDO ||
8673 Cond.getOperand(0).getOpcode() == ISD::SSUBO ||
8674 Cond.getOperand(0).getOpcode() == ISD::USUBO ||
8675 Cond.getOperand(0).getOpcode() == ISD::SMULO ||
8676 Cond.getOperand(0).getOpcode() == ISD::UMULO)) {
8678 Cond = Cond.getOperand(0);
8680 SDValue NewCond = LowerSETCC(Cond, DAG);
8681 if (NewCond.getNode())
8686 // FIXME: LowerXALUO doesn't handle these!!
8687 else if (Cond.getOpcode() == X86ISD::ADD ||
8688 Cond.getOpcode() == X86ISD::SUB ||
8689 Cond.getOpcode() == X86ISD::SMUL ||
8690 Cond.getOpcode() == X86ISD::UMUL)
8691 Cond = LowerXALUO(Cond, DAG);
8694 // Look pass (and (setcc_carry (cmp ...)), 1).
8695 if (Cond.getOpcode() == ISD::AND &&
8696 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
8697 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
8698 if (C && C->getAPIntValue() == 1)
8699 Cond = Cond.getOperand(0);
8702 // If condition flag is set by a X86ISD::CMP, then use it as the condition
8703 // setting operand in place of the X86ISD::SETCC.
8704 unsigned CondOpcode = Cond.getOpcode();
8705 if (CondOpcode == X86ISD::SETCC ||
8706 CondOpcode == X86ISD::SETCC_CARRY) {
8707 CC = Cond.getOperand(0);
8709 SDValue Cmp = Cond.getOperand(1);
8710 unsigned Opc = Cmp.getOpcode();
8711 // FIXME: WHY THE SPECIAL CASING OF LogicalCmp??
8712 if (isX86LogicalCmp(Cmp) || Opc == X86ISD::BT) {
8716 switch (cast<ConstantSDNode>(CC)->getZExtValue()) {
8720 // These can only come from an arithmetic instruction with overflow,
8721 // e.g. SADDO, UADDO.
8722 Cond = Cond.getNode()->getOperand(1);
8728 CondOpcode = Cond.getOpcode();
8729 if (CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO ||
8730 CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO ||
8731 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) &&
8732 Cond.getOperand(0).getValueType() != MVT::i8)) {
8733 SDValue LHS = Cond.getOperand(0);
8734 SDValue RHS = Cond.getOperand(1);
8738 switch (CondOpcode) {
8739 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break;
8740 case ISD::SADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break;
8741 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break;
8742 case ISD::SSUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break;
8743 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break;
8744 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break;
8745 default: llvm_unreachable("unexpected overflowing operator");
8748 X86Cond = X86::GetOppositeBranchCondition((X86::CondCode)X86Cond);
8749 if (CondOpcode == ISD::UMULO)
8750 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(),
8753 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
8755 SDValue X86Op = DAG.getNode(X86Opcode, dl, VTs, LHS, RHS);
8757 if (CondOpcode == ISD::UMULO)
8758 Cond = X86Op.getValue(2);
8760 Cond = X86Op.getValue(1);
8762 CC = DAG.getConstant(X86Cond, MVT::i8);
8766 if (Cond.hasOneUse() && isAndOrOfSetCCs(Cond, CondOpc)) {
8767 SDValue Cmp = Cond.getOperand(0).getOperand(1);
8768 if (CondOpc == ISD::OR) {
8769 // Also, recognize the pattern generated by an FCMP_UNE. We can emit
8770 // two branches instead of an explicit OR instruction with a
8772 if (Cmp == Cond.getOperand(1).getOperand(1) &&
8773 isX86LogicalCmp(Cmp)) {
8774 CC = Cond.getOperand(0).getOperand(0);
8775 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
8776 Chain, Dest, CC, Cmp);
8777 CC = Cond.getOperand(1).getOperand(0);
8781 } else { // ISD::AND
8782 // Also, recognize the pattern generated by an FCMP_OEQ. We can emit
8783 // two branches instead of an explicit AND instruction with a
8784 // separate test. However, we only do this if this block doesn't
8785 // have a fall-through edge, because this requires an explicit
8786 // jmp when the condition is false.
8787 if (Cmp == Cond.getOperand(1).getOperand(1) &&
8788 isX86LogicalCmp(Cmp) &&
8789 Op.getNode()->hasOneUse()) {
8790 X86::CondCode CCode =
8791 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
8792 CCode = X86::GetOppositeBranchCondition(CCode);
8793 CC = DAG.getConstant(CCode, MVT::i8);
8794 SDNode *User = *Op.getNode()->use_begin();
8795 // Look for an unconditional branch following this conditional branch.
8796 // We need this because we need to reverse the successors in order
8797 // to implement FCMP_OEQ.
8798 if (User->getOpcode() == ISD::BR) {
8799 SDValue FalseBB = User->getOperand(1);
8801 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
8802 assert(NewBR == User);
8806 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
8807 Chain, Dest, CC, Cmp);
8808 X86::CondCode CCode =
8809 (X86::CondCode)Cond.getOperand(1).getConstantOperandVal(0);
8810 CCode = X86::GetOppositeBranchCondition(CCode);
8811 CC = DAG.getConstant(CCode, MVT::i8);
8817 } else if (Cond.hasOneUse() && isXor1OfSetCC(Cond)) {
8818 // Recognize for xorb (setcc), 1 patterns. The xor inverts the condition.
8819 // It should be transformed during dag combiner except when the condition
8820 // is set by a arithmetics with overflow node.
8821 X86::CondCode CCode =
8822 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
8823 CCode = X86::GetOppositeBranchCondition(CCode);
8824 CC = DAG.getConstant(CCode, MVT::i8);
8825 Cond = Cond.getOperand(0).getOperand(1);
8827 } else if (Cond.getOpcode() == ISD::SETCC &&
8828 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETOEQ) {
8829 // For FCMP_OEQ, we can emit
8830 // two branches instead of an explicit AND instruction with a
8831 // separate test. However, we only do this if this block doesn't
8832 // have a fall-through edge, because this requires an explicit
8833 // jmp when the condition is false.
8834 if (Op.getNode()->hasOneUse()) {
8835 SDNode *User = *Op.getNode()->use_begin();
8836 // Look for an unconditional branch following this conditional branch.
8837 // We need this because we need to reverse the successors in order
8838 // to implement FCMP_OEQ.
8839 if (User->getOpcode() == ISD::BR) {
8840 SDValue FalseBB = User->getOperand(1);
8842 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
8843 assert(NewBR == User);
8847 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
8848 Cond.getOperand(0), Cond.getOperand(1));
8849 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
8850 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
8851 Chain, Dest, CC, Cmp);
8852 CC = DAG.getConstant(X86::COND_P, MVT::i8);
8857 } else if (Cond.getOpcode() == ISD::SETCC &&
8858 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETUNE) {
8859 // For FCMP_UNE, we can emit
8860 // two branches instead of an explicit AND instruction with a
8861 // separate test. However, we only do this if this block doesn't
8862 // have a fall-through edge, because this requires an explicit
8863 // jmp when the condition is false.
8864 if (Op.getNode()->hasOneUse()) {
8865 SDNode *User = *Op.getNode()->use_begin();
8866 // Look for an unconditional branch following this conditional branch.
8867 // We need this because we need to reverse the successors in order
8868 // to implement FCMP_UNE.
8869 if (User->getOpcode() == ISD::BR) {
8870 SDValue FalseBB = User->getOperand(1);
8872 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
8873 assert(NewBR == User);
8876 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
8877 Cond.getOperand(0), Cond.getOperand(1));
8878 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
8879 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
8880 Chain, Dest, CC, Cmp);
8881 CC = DAG.getConstant(X86::COND_NP, MVT::i8);
8891 // Look pass the truncate.
8892 if (Cond.getOpcode() == ISD::TRUNCATE)
8893 Cond = Cond.getOperand(0);
8895 // We know the result of AND is compared against zero. Try to match
8897 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
8898 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, dl, DAG);
8899 if (NewSetCC.getNode()) {
8900 CC = NewSetCC.getOperand(0);
8901 Cond = NewSetCC.getOperand(1);
8908 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
8909 Cond = EmitTest(Cond, X86::COND_NE, DAG);
8911 return DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
8912 Chain, Dest, CC, Cond);
8916 // Lower dynamic stack allocation to _alloca call for Cygwin/Mingw targets.
8917 // Calls to _alloca is needed to probe the stack when allocating more than 4k
8918 // bytes in one go. Touching the stack at 4K increments is necessary to ensure
8919 // that the guard pages used by the OS virtual memory manager are allocated in
8920 // correct sequence.
8922 X86TargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
8923 SelectionDAG &DAG) const {
8924 assert((Subtarget->isTargetCygMing() || Subtarget->isTargetWindows() ||
8925 getTargetMachine().Options.EnableSegmentedStacks) &&
8926 "This should be used only on Windows targets or when segmented stacks "
8928 assert(!Subtarget->isTargetEnvMacho() && "Not implemented");
8929 DebugLoc dl = Op.getDebugLoc();
8932 SDValue Chain = Op.getOperand(0);
8933 SDValue Size = Op.getOperand(1);
8934 // FIXME: Ensure alignment here
8936 bool Is64Bit = Subtarget->is64Bit();
8937 EVT SPTy = Is64Bit ? MVT::i64 : MVT::i32;
8939 if (getTargetMachine().Options.EnableSegmentedStacks) {
8940 MachineFunction &MF = DAG.getMachineFunction();
8941 MachineRegisterInfo &MRI = MF.getRegInfo();
8944 // The 64 bit implementation of segmented stacks needs to clobber both r10
8945 // r11. This makes it impossible to use it along with nested parameters.
8946 const Function *F = MF.getFunction();
8948 for (Function::const_arg_iterator I = F->arg_begin(), E = F->arg_end();
8950 if (I->hasNestAttr())
8951 report_fatal_error("Cannot use segmented stacks with functions that "
8952 "have nested arguments.");
8955 const TargetRegisterClass *AddrRegClass =
8956 getRegClassFor(Subtarget->is64Bit() ? MVT::i64:MVT::i32);
8957 unsigned Vreg = MRI.createVirtualRegister(AddrRegClass);
8958 Chain = DAG.getCopyToReg(Chain, dl, Vreg, Size);
8959 SDValue Value = DAG.getNode(X86ISD::SEG_ALLOCA, dl, SPTy, Chain,
8960 DAG.getRegister(Vreg, SPTy));
8961 SDValue Ops1[2] = { Value, Chain };
8962 return DAG.getMergeValues(Ops1, 2, dl);
8965 unsigned Reg = (Subtarget->is64Bit() ? X86::RAX : X86::EAX);
8967 Chain = DAG.getCopyToReg(Chain, dl, Reg, Size, Flag);
8968 Flag = Chain.getValue(1);
8969 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
8971 Chain = DAG.getNode(X86ISD::WIN_ALLOCA, dl, NodeTys, Chain, Flag);
8972 Flag = Chain.getValue(1);
8974 Chain = DAG.getCopyFromReg(Chain, dl, X86StackPtr, SPTy).getValue(1);
8976 SDValue Ops1[2] = { Chain.getValue(0), Chain };
8977 return DAG.getMergeValues(Ops1, 2, dl);
8981 SDValue X86TargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const {
8982 MachineFunction &MF = DAG.getMachineFunction();
8983 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
8985 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
8986 DebugLoc DL = Op.getDebugLoc();
8988 if (!Subtarget->is64Bit() || Subtarget->isTargetWin64()) {
8989 // vastart just stores the address of the VarArgsFrameIndex slot into the
8990 // memory location argument.
8991 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
8993 return DAG.getStore(Op.getOperand(0), DL, FR, Op.getOperand(1),
8994 MachinePointerInfo(SV), false, false, 0);
8998 // gp_offset (0 - 6 * 8)
8999 // fp_offset (48 - 48 + 8 * 16)
9000 // overflow_arg_area (point to parameters coming in memory).
9002 SmallVector<SDValue, 8> MemOps;
9003 SDValue FIN = Op.getOperand(1);
9005 SDValue Store = DAG.getStore(Op.getOperand(0), DL,
9006 DAG.getConstant(FuncInfo->getVarArgsGPOffset(),
9008 FIN, MachinePointerInfo(SV), false, false, 0);
9009 MemOps.push_back(Store);
9012 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
9013 FIN, DAG.getIntPtrConstant(4));
9014 Store = DAG.getStore(Op.getOperand(0), DL,
9015 DAG.getConstant(FuncInfo->getVarArgsFPOffset(),
9017 FIN, MachinePointerInfo(SV, 4), false, false, 0);
9018 MemOps.push_back(Store);
9020 // Store ptr to overflow_arg_area
9021 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
9022 FIN, DAG.getIntPtrConstant(4));
9023 SDValue OVFIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
9025 Store = DAG.getStore(Op.getOperand(0), DL, OVFIN, FIN,
9026 MachinePointerInfo(SV, 8),
9028 MemOps.push_back(Store);
9030 // Store ptr to reg_save_area.
9031 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
9032 FIN, DAG.getIntPtrConstant(8));
9033 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
9035 Store = DAG.getStore(Op.getOperand(0), DL, RSFIN, FIN,
9036 MachinePointerInfo(SV, 16), false, false, 0);
9037 MemOps.push_back(Store);
9038 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
9039 &MemOps[0], MemOps.size());
9042 SDValue X86TargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG) const {
9043 assert(Subtarget->is64Bit() &&
9044 "LowerVAARG only handles 64-bit va_arg!");
9045 assert((Subtarget->isTargetLinux() ||
9046 Subtarget->isTargetDarwin()) &&
9047 "Unhandled target in LowerVAARG");
9048 assert(Op.getNode()->getNumOperands() == 4);
9049 SDValue Chain = Op.getOperand(0);
9050 SDValue SrcPtr = Op.getOperand(1);
9051 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
9052 unsigned Align = Op.getConstantOperandVal(3);
9053 DebugLoc dl = Op.getDebugLoc();
9055 EVT ArgVT = Op.getNode()->getValueType(0);
9056 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
9057 uint32_t ArgSize = getTargetData()->getTypeAllocSize(ArgTy);
9060 // Decide which area this value should be read from.
9061 // TODO: Implement the AMD64 ABI in its entirety. This simple
9062 // selection mechanism works only for the basic types.
9063 if (ArgVT == MVT::f80) {
9064 llvm_unreachable("va_arg for f80 not yet implemented");
9065 } else if (ArgVT.isFloatingPoint() && ArgSize <= 16 /*bytes*/) {
9066 ArgMode = 2; // Argument passed in XMM register. Use fp_offset.
9067 } else if (ArgVT.isInteger() && ArgSize <= 32 /*bytes*/) {
9068 ArgMode = 1; // Argument passed in GPR64 register(s). Use gp_offset.
9070 llvm_unreachable("Unhandled argument type in LowerVAARG");
9074 // Sanity Check: Make sure using fp_offset makes sense.
9075 assert(!getTargetMachine().Options.UseSoftFloat &&
9076 !(DAG.getMachineFunction()
9077 .getFunction()->hasFnAttr(Attribute::NoImplicitFloat)) &&
9078 Subtarget->hasSSE1());
9081 // Insert VAARG_64 node into the DAG
9082 // VAARG_64 returns two values: Variable Argument Address, Chain
9083 SmallVector<SDValue, 11> InstOps;
9084 InstOps.push_back(Chain);
9085 InstOps.push_back(SrcPtr);
9086 InstOps.push_back(DAG.getConstant(ArgSize, MVT::i32));
9087 InstOps.push_back(DAG.getConstant(ArgMode, MVT::i8));
9088 InstOps.push_back(DAG.getConstant(Align, MVT::i32));
9089 SDVTList VTs = DAG.getVTList(getPointerTy(), MVT::Other);
9090 SDValue VAARG = DAG.getMemIntrinsicNode(X86ISD::VAARG_64, dl,
9091 VTs, &InstOps[0], InstOps.size(),
9093 MachinePointerInfo(SV),
9098 Chain = VAARG.getValue(1);
9100 // Load the next argument and return it
9101 return DAG.getLoad(ArgVT, dl,
9104 MachinePointerInfo(),
9105 false, false, false, 0);
9108 SDValue X86TargetLowering::LowerVACOPY(SDValue Op, SelectionDAG &DAG) const {
9109 // X86-64 va_list is a struct { i32, i32, i8*, i8* }.
9110 assert(Subtarget->is64Bit() && "This code only handles 64-bit va_copy!");
9111 SDValue Chain = Op.getOperand(0);
9112 SDValue DstPtr = Op.getOperand(1);
9113 SDValue SrcPtr = Op.getOperand(2);
9114 const Value *DstSV = cast<SrcValueSDNode>(Op.getOperand(3))->getValue();
9115 const Value *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
9116 DebugLoc DL = Op.getDebugLoc();
9118 return DAG.getMemcpy(Chain, DL, DstPtr, SrcPtr,
9119 DAG.getIntPtrConstant(24), 8, /*isVolatile*/false,
9121 MachinePointerInfo(DstSV), MachinePointerInfo(SrcSV));
9124 // getTargetVShiftNOde - Handle vector element shifts where the shift amount
9125 // may or may not be a constant. Takes immediate version of shift as input.
9126 static SDValue getTargetVShiftNode(unsigned Opc, DebugLoc dl, EVT VT,
9127 SDValue SrcOp, SDValue ShAmt,
9128 SelectionDAG &DAG) {
9129 assert(ShAmt.getValueType() == MVT::i32 && "ShAmt is not i32");
9131 if (isa<ConstantSDNode>(ShAmt)) {
9133 default: llvm_unreachable("Unknown target vector shift node");
9137 return DAG.getNode(Opc, dl, VT, SrcOp, ShAmt);
9141 // Change opcode to non-immediate version
9143 default: llvm_unreachable("Unknown target vector shift node");
9144 case X86ISD::VSHLI: Opc = X86ISD::VSHL; break;
9145 case X86ISD::VSRLI: Opc = X86ISD::VSRL; break;
9146 case X86ISD::VSRAI: Opc = X86ISD::VSRA; break;
9149 // Need to build a vector containing shift amount
9150 // Shift amount is 32-bits, but SSE instructions read 64-bit, so fill with 0
9153 ShOps[1] = DAG.getConstant(0, MVT::i32);
9154 ShOps[2] = DAG.getUNDEF(MVT::i32);
9155 ShOps[3] = DAG.getUNDEF(MVT::i32);
9156 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, &ShOps[0], 4);
9157 ShAmt = DAG.getNode(ISD::BITCAST, dl, VT, ShAmt);
9158 return DAG.getNode(Opc, dl, VT, SrcOp, ShAmt);
9162 X86TargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const {
9163 DebugLoc dl = Op.getDebugLoc();
9164 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
9166 default: return SDValue(); // Don't custom lower most intrinsics.
9167 // Comparison intrinsics.
9168 case Intrinsic::x86_sse_comieq_ss:
9169 case Intrinsic::x86_sse_comilt_ss:
9170 case Intrinsic::x86_sse_comile_ss:
9171 case Intrinsic::x86_sse_comigt_ss:
9172 case Intrinsic::x86_sse_comige_ss:
9173 case Intrinsic::x86_sse_comineq_ss:
9174 case Intrinsic::x86_sse_ucomieq_ss:
9175 case Intrinsic::x86_sse_ucomilt_ss:
9176 case Intrinsic::x86_sse_ucomile_ss:
9177 case Intrinsic::x86_sse_ucomigt_ss:
9178 case Intrinsic::x86_sse_ucomige_ss:
9179 case Intrinsic::x86_sse_ucomineq_ss:
9180 case Intrinsic::x86_sse2_comieq_sd:
9181 case Intrinsic::x86_sse2_comilt_sd:
9182 case Intrinsic::x86_sse2_comile_sd:
9183 case Intrinsic::x86_sse2_comigt_sd:
9184 case Intrinsic::x86_sse2_comige_sd:
9185 case Intrinsic::x86_sse2_comineq_sd:
9186 case Intrinsic::x86_sse2_ucomieq_sd:
9187 case Intrinsic::x86_sse2_ucomilt_sd:
9188 case Intrinsic::x86_sse2_ucomile_sd:
9189 case Intrinsic::x86_sse2_ucomigt_sd:
9190 case Intrinsic::x86_sse2_ucomige_sd:
9191 case Intrinsic::x86_sse2_ucomineq_sd: {
9193 ISD::CondCode CC = ISD::SETCC_INVALID;
9195 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
9196 case Intrinsic::x86_sse_comieq_ss:
9197 case Intrinsic::x86_sse2_comieq_sd:
9201 case Intrinsic::x86_sse_comilt_ss:
9202 case Intrinsic::x86_sse2_comilt_sd:
9206 case Intrinsic::x86_sse_comile_ss:
9207 case Intrinsic::x86_sse2_comile_sd:
9211 case Intrinsic::x86_sse_comigt_ss:
9212 case Intrinsic::x86_sse2_comigt_sd:
9216 case Intrinsic::x86_sse_comige_ss:
9217 case Intrinsic::x86_sse2_comige_sd:
9221 case Intrinsic::x86_sse_comineq_ss:
9222 case Intrinsic::x86_sse2_comineq_sd:
9226 case Intrinsic::x86_sse_ucomieq_ss:
9227 case Intrinsic::x86_sse2_ucomieq_sd:
9228 Opc = X86ISD::UCOMI;
9231 case Intrinsic::x86_sse_ucomilt_ss:
9232 case Intrinsic::x86_sse2_ucomilt_sd:
9233 Opc = X86ISD::UCOMI;
9236 case Intrinsic::x86_sse_ucomile_ss:
9237 case Intrinsic::x86_sse2_ucomile_sd:
9238 Opc = X86ISD::UCOMI;
9241 case Intrinsic::x86_sse_ucomigt_ss:
9242 case Intrinsic::x86_sse2_ucomigt_sd:
9243 Opc = X86ISD::UCOMI;
9246 case Intrinsic::x86_sse_ucomige_ss:
9247 case Intrinsic::x86_sse2_ucomige_sd:
9248 Opc = X86ISD::UCOMI;
9251 case Intrinsic::x86_sse_ucomineq_ss:
9252 case Intrinsic::x86_sse2_ucomineq_sd:
9253 Opc = X86ISD::UCOMI;
9258 SDValue LHS = Op.getOperand(1);
9259 SDValue RHS = Op.getOperand(2);
9260 unsigned X86CC = TranslateX86CC(CC, true, LHS, RHS, DAG);
9261 assert(X86CC != X86::COND_INVALID && "Unexpected illegal condition!");
9262 SDValue Cond = DAG.getNode(Opc, dl, MVT::i32, LHS, RHS);
9263 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
9264 DAG.getConstant(X86CC, MVT::i8), Cond);
9265 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
9267 // XOP comparison intrinsics
9268 case Intrinsic::x86_xop_vpcomltb:
9269 case Intrinsic::x86_xop_vpcomltw:
9270 case Intrinsic::x86_xop_vpcomltd:
9271 case Intrinsic::x86_xop_vpcomltq:
9272 case Intrinsic::x86_xop_vpcomltub:
9273 case Intrinsic::x86_xop_vpcomltuw:
9274 case Intrinsic::x86_xop_vpcomltud:
9275 case Intrinsic::x86_xop_vpcomltuq:
9276 case Intrinsic::x86_xop_vpcomleb:
9277 case Intrinsic::x86_xop_vpcomlew:
9278 case Intrinsic::x86_xop_vpcomled:
9279 case Intrinsic::x86_xop_vpcomleq:
9280 case Intrinsic::x86_xop_vpcomleub:
9281 case Intrinsic::x86_xop_vpcomleuw:
9282 case Intrinsic::x86_xop_vpcomleud:
9283 case Intrinsic::x86_xop_vpcomleuq:
9284 case Intrinsic::x86_xop_vpcomgtb:
9285 case Intrinsic::x86_xop_vpcomgtw:
9286 case Intrinsic::x86_xop_vpcomgtd:
9287 case Intrinsic::x86_xop_vpcomgtq:
9288 case Intrinsic::x86_xop_vpcomgtub:
9289 case Intrinsic::x86_xop_vpcomgtuw:
9290 case Intrinsic::x86_xop_vpcomgtud:
9291 case Intrinsic::x86_xop_vpcomgtuq:
9292 case Intrinsic::x86_xop_vpcomgeb:
9293 case Intrinsic::x86_xop_vpcomgew:
9294 case Intrinsic::x86_xop_vpcomged:
9295 case Intrinsic::x86_xop_vpcomgeq:
9296 case Intrinsic::x86_xop_vpcomgeub:
9297 case Intrinsic::x86_xop_vpcomgeuw:
9298 case Intrinsic::x86_xop_vpcomgeud:
9299 case Intrinsic::x86_xop_vpcomgeuq:
9300 case Intrinsic::x86_xop_vpcomeqb:
9301 case Intrinsic::x86_xop_vpcomeqw:
9302 case Intrinsic::x86_xop_vpcomeqd:
9303 case Intrinsic::x86_xop_vpcomeqq:
9304 case Intrinsic::x86_xop_vpcomequb:
9305 case Intrinsic::x86_xop_vpcomequw:
9306 case Intrinsic::x86_xop_vpcomequd:
9307 case Intrinsic::x86_xop_vpcomequq:
9308 case Intrinsic::x86_xop_vpcomneb:
9309 case Intrinsic::x86_xop_vpcomnew:
9310 case Intrinsic::x86_xop_vpcomned:
9311 case Intrinsic::x86_xop_vpcomneq:
9312 case Intrinsic::x86_xop_vpcomneub:
9313 case Intrinsic::x86_xop_vpcomneuw:
9314 case Intrinsic::x86_xop_vpcomneud:
9315 case Intrinsic::x86_xop_vpcomneuq:
9316 case Intrinsic::x86_xop_vpcomfalseb:
9317 case Intrinsic::x86_xop_vpcomfalsew:
9318 case Intrinsic::x86_xop_vpcomfalsed:
9319 case Intrinsic::x86_xop_vpcomfalseq:
9320 case Intrinsic::x86_xop_vpcomfalseub:
9321 case Intrinsic::x86_xop_vpcomfalseuw:
9322 case Intrinsic::x86_xop_vpcomfalseud:
9323 case Intrinsic::x86_xop_vpcomfalseuq:
9324 case Intrinsic::x86_xop_vpcomtrueb:
9325 case Intrinsic::x86_xop_vpcomtruew:
9326 case Intrinsic::x86_xop_vpcomtrued:
9327 case Intrinsic::x86_xop_vpcomtrueq:
9328 case Intrinsic::x86_xop_vpcomtrueub:
9329 case Intrinsic::x86_xop_vpcomtrueuw:
9330 case Intrinsic::x86_xop_vpcomtrueud:
9331 case Intrinsic::x86_xop_vpcomtrueuq: {
9336 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
9337 case Intrinsic::x86_xop_vpcomltb:
9338 case Intrinsic::x86_xop_vpcomltw:
9339 case Intrinsic::x86_xop_vpcomltd:
9340 case Intrinsic::x86_xop_vpcomltq:
9342 Opc = X86ISD::VPCOM;
9344 case Intrinsic::x86_xop_vpcomltub:
9345 case Intrinsic::x86_xop_vpcomltuw:
9346 case Intrinsic::x86_xop_vpcomltud:
9347 case Intrinsic::x86_xop_vpcomltuq:
9349 Opc = X86ISD::VPCOMU;
9351 case Intrinsic::x86_xop_vpcomleb:
9352 case Intrinsic::x86_xop_vpcomlew:
9353 case Intrinsic::x86_xop_vpcomled:
9354 case Intrinsic::x86_xop_vpcomleq:
9356 Opc = X86ISD::VPCOM;
9358 case Intrinsic::x86_xop_vpcomleub:
9359 case Intrinsic::x86_xop_vpcomleuw:
9360 case Intrinsic::x86_xop_vpcomleud:
9361 case Intrinsic::x86_xop_vpcomleuq:
9363 Opc = X86ISD::VPCOMU;
9365 case Intrinsic::x86_xop_vpcomgtb:
9366 case Intrinsic::x86_xop_vpcomgtw:
9367 case Intrinsic::x86_xop_vpcomgtd:
9368 case Intrinsic::x86_xop_vpcomgtq:
9370 Opc = X86ISD::VPCOM;
9372 case Intrinsic::x86_xop_vpcomgtub:
9373 case Intrinsic::x86_xop_vpcomgtuw:
9374 case Intrinsic::x86_xop_vpcomgtud:
9375 case Intrinsic::x86_xop_vpcomgtuq:
9377 Opc = X86ISD::VPCOMU;
9379 case Intrinsic::x86_xop_vpcomgeb:
9380 case Intrinsic::x86_xop_vpcomgew:
9381 case Intrinsic::x86_xop_vpcomged:
9382 case Intrinsic::x86_xop_vpcomgeq:
9384 Opc = X86ISD::VPCOM;
9386 case Intrinsic::x86_xop_vpcomgeub:
9387 case Intrinsic::x86_xop_vpcomgeuw:
9388 case Intrinsic::x86_xop_vpcomgeud:
9389 case Intrinsic::x86_xop_vpcomgeuq:
9391 Opc = X86ISD::VPCOMU;
9393 case Intrinsic::x86_xop_vpcomeqb:
9394 case Intrinsic::x86_xop_vpcomeqw:
9395 case Intrinsic::x86_xop_vpcomeqd:
9396 case Intrinsic::x86_xop_vpcomeqq:
9398 Opc = X86ISD::VPCOM;
9400 case Intrinsic::x86_xop_vpcomequb:
9401 case Intrinsic::x86_xop_vpcomequw:
9402 case Intrinsic::x86_xop_vpcomequd:
9403 case Intrinsic::x86_xop_vpcomequq:
9405 Opc = X86ISD::VPCOMU;
9407 case Intrinsic::x86_xop_vpcomneb:
9408 case Intrinsic::x86_xop_vpcomnew:
9409 case Intrinsic::x86_xop_vpcomned:
9410 case Intrinsic::x86_xop_vpcomneq:
9412 Opc = X86ISD::VPCOM;
9414 case Intrinsic::x86_xop_vpcomneub:
9415 case Intrinsic::x86_xop_vpcomneuw:
9416 case Intrinsic::x86_xop_vpcomneud:
9417 case Intrinsic::x86_xop_vpcomneuq:
9419 Opc = X86ISD::VPCOMU;
9421 case Intrinsic::x86_xop_vpcomfalseb:
9422 case Intrinsic::x86_xop_vpcomfalsew:
9423 case Intrinsic::x86_xop_vpcomfalsed:
9424 case Intrinsic::x86_xop_vpcomfalseq:
9426 Opc = X86ISD::VPCOM;
9428 case Intrinsic::x86_xop_vpcomfalseub:
9429 case Intrinsic::x86_xop_vpcomfalseuw:
9430 case Intrinsic::x86_xop_vpcomfalseud:
9431 case Intrinsic::x86_xop_vpcomfalseuq:
9433 Opc = X86ISD::VPCOMU;
9435 case Intrinsic::x86_xop_vpcomtrueb:
9436 case Intrinsic::x86_xop_vpcomtruew:
9437 case Intrinsic::x86_xop_vpcomtrued:
9438 case Intrinsic::x86_xop_vpcomtrueq:
9440 Opc = X86ISD::VPCOM;
9442 case Intrinsic::x86_xop_vpcomtrueub:
9443 case Intrinsic::x86_xop_vpcomtrueuw:
9444 case Intrinsic::x86_xop_vpcomtrueud:
9445 case Intrinsic::x86_xop_vpcomtrueuq:
9447 Opc = X86ISD::VPCOMU;
9451 SDValue LHS = Op.getOperand(1);
9452 SDValue RHS = Op.getOperand(2);
9453 return DAG.getNode(Opc, dl, Op.getValueType(), LHS, RHS,
9454 DAG.getConstant(CC, MVT::i8));
9457 // Arithmetic intrinsics.
9458 case Intrinsic::x86_sse3_hadd_ps:
9459 case Intrinsic::x86_sse3_hadd_pd:
9460 case Intrinsic::x86_avx_hadd_ps_256:
9461 case Intrinsic::x86_avx_hadd_pd_256:
9462 return DAG.getNode(X86ISD::FHADD, dl, Op.getValueType(),
9463 Op.getOperand(1), Op.getOperand(2));
9464 case Intrinsic::x86_sse3_hsub_ps:
9465 case Intrinsic::x86_sse3_hsub_pd:
9466 case Intrinsic::x86_avx_hsub_ps_256:
9467 case Intrinsic::x86_avx_hsub_pd_256:
9468 return DAG.getNode(X86ISD::FHSUB, dl, Op.getValueType(),
9469 Op.getOperand(1), Op.getOperand(2));
9470 case Intrinsic::x86_ssse3_phadd_w_128:
9471 case Intrinsic::x86_ssse3_phadd_d_128:
9472 case Intrinsic::x86_avx2_phadd_w:
9473 case Intrinsic::x86_avx2_phadd_d:
9474 return DAG.getNode(X86ISD::HADD, dl, Op.getValueType(),
9475 Op.getOperand(1), Op.getOperand(2));
9476 case Intrinsic::x86_ssse3_phsub_w_128:
9477 case Intrinsic::x86_ssse3_phsub_d_128:
9478 case Intrinsic::x86_avx2_phsub_w:
9479 case Intrinsic::x86_avx2_phsub_d:
9480 return DAG.getNode(X86ISD::HSUB, dl, Op.getValueType(),
9481 Op.getOperand(1), Op.getOperand(2));
9482 case Intrinsic::x86_avx2_psllv_d:
9483 case Intrinsic::x86_avx2_psllv_q:
9484 case Intrinsic::x86_avx2_psllv_d_256:
9485 case Intrinsic::x86_avx2_psllv_q_256:
9486 return DAG.getNode(ISD::SHL, dl, Op.getValueType(),
9487 Op.getOperand(1), Op.getOperand(2));
9488 case Intrinsic::x86_avx2_psrlv_d:
9489 case Intrinsic::x86_avx2_psrlv_q:
9490 case Intrinsic::x86_avx2_psrlv_d_256:
9491 case Intrinsic::x86_avx2_psrlv_q_256:
9492 return DAG.getNode(ISD::SRL, dl, Op.getValueType(),
9493 Op.getOperand(1), Op.getOperand(2));
9494 case Intrinsic::x86_avx2_psrav_d:
9495 case Intrinsic::x86_avx2_psrav_d_256:
9496 return DAG.getNode(ISD::SRA, dl, Op.getValueType(),
9497 Op.getOperand(1), Op.getOperand(2));
9498 case Intrinsic::x86_ssse3_pshuf_b_128:
9499 case Intrinsic::x86_avx2_pshuf_b:
9500 return DAG.getNode(X86ISD::PSHUFB, dl, Op.getValueType(),
9501 Op.getOperand(1), Op.getOperand(2));
9502 case Intrinsic::x86_ssse3_psign_b_128:
9503 case Intrinsic::x86_ssse3_psign_w_128:
9504 case Intrinsic::x86_ssse3_psign_d_128:
9505 case Intrinsic::x86_avx2_psign_b:
9506 case Intrinsic::x86_avx2_psign_w:
9507 case Intrinsic::x86_avx2_psign_d:
9508 return DAG.getNode(X86ISD::PSIGN, dl, Op.getValueType(),
9509 Op.getOperand(1), Op.getOperand(2));
9510 case Intrinsic::x86_sse41_insertps:
9511 return DAG.getNode(X86ISD::INSERTPS, dl, Op.getValueType(),
9512 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
9513 case Intrinsic::x86_avx_vperm2f128_ps_256:
9514 case Intrinsic::x86_avx_vperm2f128_pd_256:
9515 case Intrinsic::x86_avx_vperm2f128_si_256:
9516 case Intrinsic::x86_avx2_vperm2i128:
9517 return DAG.getNode(X86ISD::VPERM2X128, dl, Op.getValueType(),
9518 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
9520 // ptest and testp intrinsics. The intrinsic these come from are designed to
9521 // return an integer value, not just an instruction so lower it to the ptest
9522 // or testp pattern and a setcc for the result.
9523 case Intrinsic::x86_sse41_ptestz:
9524 case Intrinsic::x86_sse41_ptestc:
9525 case Intrinsic::x86_sse41_ptestnzc:
9526 case Intrinsic::x86_avx_ptestz_256:
9527 case Intrinsic::x86_avx_ptestc_256:
9528 case Intrinsic::x86_avx_ptestnzc_256:
9529 case Intrinsic::x86_avx_vtestz_ps:
9530 case Intrinsic::x86_avx_vtestc_ps:
9531 case Intrinsic::x86_avx_vtestnzc_ps:
9532 case Intrinsic::x86_avx_vtestz_pd:
9533 case Intrinsic::x86_avx_vtestc_pd:
9534 case Intrinsic::x86_avx_vtestnzc_pd:
9535 case Intrinsic::x86_avx_vtestz_ps_256:
9536 case Intrinsic::x86_avx_vtestc_ps_256:
9537 case Intrinsic::x86_avx_vtestnzc_ps_256:
9538 case Intrinsic::x86_avx_vtestz_pd_256:
9539 case Intrinsic::x86_avx_vtestc_pd_256:
9540 case Intrinsic::x86_avx_vtestnzc_pd_256: {
9541 bool IsTestPacked = false;
9544 default: llvm_unreachable("Bad fallthrough in Intrinsic lowering.");
9545 case Intrinsic::x86_avx_vtestz_ps:
9546 case Intrinsic::x86_avx_vtestz_pd:
9547 case Intrinsic::x86_avx_vtestz_ps_256:
9548 case Intrinsic::x86_avx_vtestz_pd_256:
9549 IsTestPacked = true; // Fallthrough
9550 case Intrinsic::x86_sse41_ptestz:
9551 case Intrinsic::x86_avx_ptestz_256:
9553 X86CC = X86::COND_E;
9555 case Intrinsic::x86_avx_vtestc_ps:
9556 case Intrinsic::x86_avx_vtestc_pd:
9557 case Intrinsic::x86_avx_vtestc_ps_256:
9558 case Intrinsic::x86_avx_vtestc_pd_256:
9559 IsTestPacked = true; // Fallthrough
9560 case Intrinsic::x86_sse41_ptestc:
9561 case Intrinsic::x86_avx_ptestc_256:
9563 X86CC = X86::COND_B;
9565 case Intrinsic::x86_avx_vtestnzc_ps:
9566 case Intrinsic::x86_avx_vtestnzc_pd:
9567 case Intrinsic::x86_avx_vtestnzc_ps_256:
9568 case Intrinsic::x86_avx_vtestnzc_pd_256:
9569 IsTestPacked = true; // Fallthrough
9570 case Intrinsic::x86_sse41_ptestnzc:
9571 case Intrinsic::x86_avx_ptestnzc_256:
9573 X86CC = X86::COND_A;
9577 SDValue LHS = Op.getOperand(1);
9578 SDValue RHS = Op.getOperand(2);
9579 unsigned TestOpc = IsTestPacked ? X86ISD::TESTP : X86ISD::PTEST;
9580 SDValue Test = DAG.getNode(TestOpc, dl, MVT::i32, LHS, RHS);
9581 SDValue CC = DAG.getConstant(X86CC, MVT::i8);
9582 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8, CC, Test);
9583 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
9586 // SSE/AVX shift intrinsics
9587 case Intrinsic::x86_sse2_psll_w:
9588 case Intrinsic::x86_sse2_psll_d:
9589 case Intrinsic::x86_sse2_psll_q:
9590 case Intrinsic::x86_avx2_psll_w:
9591 case Intrinsic::x86_avx2_psll_d:
9592 case Intrinsic::x86_avx2_psll_q:
9593 return DAG.getNode(X86ISD::VSHL, dl, Op.getValueType(),
9594 Op.getOperand(1), Op.getOperand(2));
9595 case Intrinsic::x86_sse2_psrl_w:
9596 case Intrinsic::x86_sse2_psrl_d:
9597 case Intrinsic::x86_sse2_psrl_q:
9598 case Intrinsic::x86_avx2_psrl_w:
9599 case Intrinsic::x86_avx2_psrl_d:
9600 case Intrinsic::x86_avx2_psrl_q:
9601 return DAG.getNode(X86ISD::VSRL, dl, Op.getValueType(),
9602 Op.getOperand(1), Op.getOperand(2));
9603 case Intrinsic::x86_sse2_psra_w:
9604 case Intrinsic::x86_sse2_psra_d:
9605 case Intrinsic::x86_avx2_psra_w:
9606 case Intrinsic::x86_avx2_psra_d:
9607 return DAG.getNode(X86ISD::VSRA, dl, Op.getValueType(),
9608 Op.getOperand(1), Op.getOperand(2));
9609 case Intrinsic::x86_sse2_pslli_w:
9610 case Intrinsic::x86_sse2_pslli_d:
9611 case Intrinsic::x86_sse2_pslli_q:
9612 case Intrinsic::x86_avx2_pslli_w:
9613 case Intrinsic::x86_avx2_pslli_d:
9614 case Intrinsic::x86_avx2_pslli_q:
9615 return getTargetVShiftNode(X86ISD::VSHLI, dl, Op.getValueType(),
9616 Op.getOperand(1), Op.getOperand(2), DAG);
9617 case Intrinsic::x86_sse2_psrli_w:
9618 case Intrinsic::x86_sse2_psrli_d:
9619 case Intrinsic::x86_sse2_psrli_q:
9620 case Intrinsic::x86_avx2_psrli_w:
9621 case Intrinsic::x86_avx2_psrli_d:
9622 case Intrinsic::x86_avx2_psrli_q:
9623 return getTargetVShiftNode(X86ISD::VSRLI, dl, Op.getValueType(),
9624 Op.getOperand(1), Op.getOperand(2), DAG);
9625 case Intrinsic::x86_sse2_psrai_w:
9626 case Intrinsic::x86_sse2_psrai_d:
9627 case Intrinsic::x86_avx2_psrai_w:
9628 case Intrinsic::x86_avx2_psrai_d:
9629 return getTargetVShiftNode(X86ISD::VSRAI, dl, Op.getValueType(),
9630 Op.getOperand(1), Op.getOperand(2), DAG);
9631 // Fix vector shift instructions where the last operand is a non-immediate
9633 case Intrinsic::x86_mmx_pslli_w:
9634 case Intrinsic::x86_mmx_pslli_d:
9635 case Intrinsic::x86_mmx_pslli_q:
9636 case Intrinsic::x86_mmx_psrli_w:
9637 case Intrinsic::x86_mmx_psrli_d:
9638 case Intrinsic::x86_mmx_psrli_q:
9639 case Intrinsic::x86_mmx_psrai_w:
9640 case Intrinsic::x86_mmx_psrai_d: {
9641 SDValue ShAmt = Op.getOperand(2);
9642 if (isa<ConstantSDNode>(ShAmt))
9645 unsigned NewIntNo = 0;
9647 case Intrinsic::x86_mmx_pslli_w:
9648 NewIntNo = Intrinsic::x86_mmx_psll_w;
9650 case Intrinsic::x86_mmx_pslli_d:
9651 NewIntNo = Intrinsic::x86_mmx_psll_d;
9653 case Intrinsic::x86_mmx_pslli_q:
9654 NewIntNo = Intrinsic::x86_mmx_psll_q;
9656 case Intrinsic::x86_mmx_psrli_w:
9657 NewIntNo = Intrinsic::x86_mmx_psrl_w;
9659 case Intrinsic::x86_mmx_psrli_d:
9660 NewIntNo = Intrinsic::x86_mmx_psrl_d;
9662 case Intrinsic::x86_mmx_psrli_q:
9663 NewIntNo = Intrinsic::x86_mmx_psrl_q;
9665 case Intrinsic::x86_mmx_psrai_w:
9666 NewIntNo = Intrinsic::x86_mmx_psra_w;
9668 case Intrinsic::x86_mmx_psrai_d:
9669 NewIntNo = Intrinsic::x86_mmx_psra_d;
9671 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
9674 // The vector shift intrinsics with scalars uses 32b shift amounts but
9675 // the sse2/mmx shift instructions reads 64 bits. Set the upper 32 bits
9677 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2i32, ShAmt,
9678 DAG.getConstant(0, MVT::i32));
9679 // FIXME this must be lowered to get rid of the invalid type.
9681 EVT VT = Op.getValueType();
9682 ShAmt = DAG.getNode(ISD::BITCAST, dl, VT, ShAmt);
9683 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
9684 DAG.getConstant(NewIntNo, MVT::i32),
9685 Op.getOperand(1), ShAmt);
9690 SDValue X86TargetLowering::LowerRETURNADDR(SDValue Op,
9691 SelectionDAG &DAG) const {
9692 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
9693 MFI->setReturnAddressIsTaken(true);
9695 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
9696 DebugLoc dl = Op.getDebugLoc();
9699 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
9701 DAG.getConstant(TD->getPointerSize(),
9702 Subtarget->is64Bit() ? MVT::i64 : MVT::i32);
9703 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(),
9704 DAG.getNode(ISD::ADD, dl, getPointerTy(),
9706 MachinePointerInfo(), false, false, false, 0);
9709 // Just load the return address.
9710 SDValue RetAddrFI = getReturnAddressFrameIndex(DAG);
9711 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(),
9712 RetAddrFI, MachinePointerInfo(), false, false, false, 0);
9715 SDValue X86TargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {
9716 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
9717 MFI->setFrameAddressIsTaken(true);
9719 EVT VT = Op.getValueType();
9720 DebugLoc dl = Op.getDebugLoc(); // FIXME probably not meaningful
9721 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
9722 unsigned FrameReg = Subtarget->is64Bit() ? X86::RBP : X86::EBP;
9723 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT);
9725 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr,
9726 MachinePointerInfo(),
9727 false, false, false, 0);
9731 SDValue X86TargetLowering::LowerFRAME_TO_ARGS_OFFSET(SDValue Op,
9732 SelectionDAG &DAG) const {
9733 return DAG.getIntPtrConstant(2*TD->getPointerSize());
9736 SDValue X86TargetLowering::LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const {
9737 MachineFunction &MF = DAG.getMachineFunction();
9738 SDValue Chain = Op.getOperand(0);
9739 SDValue Offset = Op.getOperand(1);
9740 SDValue Handler = Op.getOperand(2);
9741 DebugLoc dl = Op.getDebugLoc();
9743 SDValue Frame = DAG.getCopyFromReg(DAG.getEntryNode(), dl,
9744 Subtarget->is64Bit() ? X86::RBP : X86::EBP,
9746 unsigned StoreAddrReg = (Subtarget->is64Bit() ? X86::RCX : X86::ECX);
9748 SDValue StoreAddr = DAG.getNode(ISD::ADD, dl, getPointerTy(), Frame,
9749 DAG.getIntPtrConstant(TD->getPointerSize()));
9750 StoreAddr = DAG.getNode(ISD::ADD, dl, getPointerTy(), StoreAddr, Offset);
9751 Chain = DAG.getStore(Chain, dl, Handler, StoreAddr, MachinePointerInfo(),
9753 Chain = DAG.getCopyToReg(Chain, dl, StoreAddrReg, StoreAddr);
9754 MF.getRegInfo().addLiveOut(StoreAddrReg);
9756 return DAG.getNode(X86ISD::EH_RETURN, dl,
9758 Chain, DAG.getRegister(StoreAddrReg, getPointerTy()));
9761 SDValue X86TargetLowering::LowerADJUST_TRAMPOLINE(SDValue Op,
9762 SelectionDAG &DAG) const {
9763 return Op.getOperand(0);
9766 SDValue X86TargetLowering::LowerINIT_TRAMPOLINE(SDValue Op,
9767 SelectionDAG &DAG) const {
9768 SDValue Root = Op.getOperand(0);
9769 SDValue Trmp = Op.getOperand(1); // trampoline
9770 SDValue FPtr = Op.getOperand(2); // nested function
9771 SDValue Nest = Op.getOperand(3); // 'nest' parameter value
9772 DebugLoc dl = Op.getDebugLoc();
9774 const Value *TrmpAddr = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
9776 if (Subtarget->is64Bit()) {
9777 SDValue OutChains[6];
9779 // Large code-model.
9780 const unsigned char JMP64r = 0xFF; // 64-bit jmp through register opcode.
9781 const unsigned char MOV64ri = 0xB8; // X86::MOV64ri opcode.
9783 const unsigned char N86R10 = X86_MC::getX86RegNum(X86::R10);
9784 const unsigned char N86R11 = X86_MC::getX86RegNum(X86::R11);
9786 const unsigned char REX_WB = 0x40 | 0x08 | 0x01; // REX prefix
9788 // Load the pointer to the nested function into R11.
9789 unsigned OpCode = ((MOV64ri | N86R11) << 8) | REX_WB; // movabsq r11
9790 SDValue Addr = Trmp;
9791 OutChains[0] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
9792 Addr, MachinePointerInfo(TrmpAddr),
9795 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
9796 DAG.getConstant(2, MVT::i64));
9797 OutChains[1] = DAG.getStore(Root, dl, FPtr, Addr,
9798 MachinePointerInfo(TrmpAddr, 2),
9801 // Load the 'nest' parameter value into R10.
9802 // R10 is specified in X86CallingConv.td
9803 OpCode = ((MOV64ri | N86R10) << 8) | REX_WB; // movabsq r10
9804 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
9805 DAG.getConstant(10, MVT::i64));
9806 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
9807 Addr, MachinePointerInfo(TrmpAddr, 10),
9810 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
9811 DAG.getConstant(12, MVT::i64));
9812 OutChains[3] = DAG.getStore(Root, dl, Nest, Addr,
9813 MachinePointerInfo(TrmpAddr, 12),
9816 // Jump to the nested function.
9817 OpCode = (JMP64r << 8) | REX_WB; // jmpq *...
9818 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
9819 DAG.getConstant(20, MVT::i64));
9820 OutChains[4] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
9821 Addr, MachinePointerInfo(TrmpAddr, 20),
9824 unsigned char ModRM = N86R11 | (4 << 3) | (3 << 6); // ...r11
9825 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
9826 DAG.getConstant(22, MVT::i64));
9827 OutChains[5] = DAG.getStore(Root, dl, DAG.getConstant(ModRM, MVT::i8), Addr,
9828 MachinePointerInfo(TrmpAddr, 22),
9831 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains, 6);
9833 const Function *Func =
9834 cast<Function>(cast<SrcValueSDNode>(Op.getOperand(5))->getValue());
9835 CallingConv::ID CC = Func->getCallingConv();
9840 llvm_unreachable("Unsupported calling convention");
9841 case CallingConv::C:
9842 case CallingConv::X86_StdCall: {
9843 // Pass 'nest' parameter in ECX.
9844 // Must be kept in sync with X86CallingConv.td
9847 // Check that ECX wasn't needed by an 'inreg' parameter.
9848 FunctionType *FTy = Func->getFunctionType();
9849 const AttrListPtr &Attrs = Func->getAttributes();
9851 if (!Attrs.isEmpty() && !Func->isVarArg()) {
9852 unsigned InRegCount = 0;
9855 for (FunctionType::param_iterator I = FTy->param_begin(),
9856 E = FTy->param_end(); I != E; ++I, ++Idx)
9857 if (Attrs.paramHasAttr(Idx, Attribute::InReg))
9858 // FIXME: should only count parameters that are lowered to integers.
9859 InRegCount += (TD->getTypeSizeInBits(*I) + 31) / 32;
9861 if (InRegCount > 2) {
9862 report_fatal_error("Nest register in use - reduce number of inreg"
9868 case CallingConv::X86_FastCall:
9869 case CallingConv::X86_ThisCall:
9870 case CallingConv::Fast:
9871 // Pass 'nest' parameter in EAX.
9872 // Must be kept in sync with X86CallingConv.td
9877 SDValue OutChains[4];
9880 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
9881 DAG.getConstant(10, MVT::i32));
9882 Disp = DAG.getNode(ISD::SUB, dl, MVT::i32, FPtr, Addr);
9884 // This is storing the opcode for MOV32ri.
9885 const unsigned char MOV32ri = 0xB8; // X86::MOV32ri's opcode byte.
9886 const unsigned char N86Reg = X86_MC::getX86RegNum(NestReg);
9887 OutChains[0] = DAG.getStore(Root, dl,
9888 DAG.getConstant(MOV32ri|N86Reg, MVT::i8),
9889 Trmp, MachinePointerInfo(TrmpAddr),
9892 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
9893 DAG.getConstant(1, MVT::i32));
9894 OutChains[1] = DAG.getStore(Root, dl, Nest, Addr,
9895 MachinePointerInfo(TrmpAddr, 1),
9898 const unsigned char JMP = 0xE9; // jmp <32bit dst> opcode.
9899 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
9900 DAG.getConstant(5, MVT::i32));
9901 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(JMP, MVT::i8), Addr,
9902 MachinePointerInfo(TrmpAddr, 5),
9905 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
9906 DAG.getConstant(6, MVT::i32));
9907 OutChains[3] = DAG.getStore(Root, dl, Disp, Addr,
9908 MachinePointerInfo(TrmpAddr, 6),
9911 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains, 4);
9915 SDValue X86TargetLowering::LowerFLT_ROUNDS_(SDValue Op,
9916 SelectionDAG &DAG) const {
9918 The rounding mode is in bits 11:10 of FPSR, and has the following
9925 FLT_ROUNDS, on the other hand, expects the following:
9932 To perform the conversion, we do:
9933 (((((FPSR & 0x800) >> 11) | ((FPSR & 0x400) >> 9)) + 1) & 3)
9936 MachineFunction &MF = DAG.getMachineFunction();
9937 const TargetMachine &TM = MF.getTarget();
9938 const TargetFrameLowering &TFI = *TM.getFrameLowering();
9939 unsigned StackAlignment = TFI.getStackAlignment();
9940 EVT VT = Op.getValueType();
9941 DebugLoc DL = Op.getDebugLoc();
9943 // Save FP Control Word to stack slot
9944 int SSFI = MF.getFrameInfo()->CreateStackObject(2, StackAlignment, false);
9945 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
9948 MachineMemOperand *MMO =
9949 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
9950 MachineMemOperand::MOStore, 2, 2);
9952 SDValue Ops[] = { DAG.getEntryNode(), StackSlot };
9953 SDValue Chain = DAG.getMemIntrinsicNode(X86ISD::FNSTCW16m, DL,
9954 DAG.getVTList(MVT::Other),
9955 Ops, 2, MVT::i16, MMO);
9957 // Load FP Control Word from stack slot
9958 SDValue CWD = DAG.getLoad(MVT::i16, DL, Chain, StackSlot,
9959 MachinePointerInfo(), false, false, false, 0);
9961 // Transform as necessary
9963 DAG.getNode(ISD::SRL, DL, MVT::i16,
9964 DAG.getNode(ISD::AND, DL, MVT::i16,
9965 CWD, DAG.getConstant(0x800, MVT::i16)),
9966 DAG.getConstant(11, MVT::i8));
9968 DAG.getNode(ISD::SRL, DL, MVT::i16,
9969 DAG.getNode(ISD::AND, DL, MVT::i16,
9970 CWD, DAG.getConstant(0x400, MVT::i16)),
9971 DAG.getConstant(9, MVT::i8));
9974 DAG.getNode(ISD::AND, DL, MVT::i16,
9975 DAG.getNode(ISD::ADD, DL, MVT::i16,
9976 DAG.getNode(ISD::OR, DL, MVT::i16, CWD1, CWD2),
9977 DAG.getConstant(1, MVT::i16)),
9978 DAG.getConstant(3, MVT::i16));
9981 return DAG.getNode((VT.getSizeInBits() < 16 ?
9982 ISD::TRUNCATE : ISD::ZERO_EXTEND), DL, VT, RetVal);
9985 SDValue X86TargetLowering::LowerCTLZ(SDValue Op, SelectionDAG &DAG) const {
9986 EVT VT = Op.getValueType();
9988 unsigned NumBits = VT.getSizeInBits();
9989 DebugLoc dl = Op.getDebugLoc();
9991 Op = Op.getOperand(0);
9992 if (VT == MVT::i8) {
9993 // Zero extend to i32 since there is not an i8 bsr.
9995 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
9998 // Issue a bsr (scan bits in reverse) which also sets EFLAGS.
9999 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
10000 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
10002 // If src is zero (i.e. bsr sets ZF), returns NumBits.
10005 DAG.getConstant(NumBits+NumBits-1, OpVT),
10006 DAG.getConstant(X86::COND_E, MVT::i8),
10009 Op = DAG.getNode(X86ISD::CMOV, dl, OpVT, Ops, array_lengthof(Ops));
10011 // Finally xor with NumBits-1.
10012 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT));
10015 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
10019 SDValue X86TargetLowering::LowerCTLZ_ZERO_UNDEF(SDValue Op,
10020 SelectionDAG &DAG) const {
10021 EVT VT = Op.getValueType();
10023 unsigned NumBits = VT.getSizeInBits();
10024 DebugLoc dl = Op.getDebugLoc();
10026 Op = Op.getOperand(0);
10027 if (VT == MVT::i8) {
10028 // Zero extend to i32 since there is not an i8 bsr.
10030 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
10033 // Issue a bsr (scan bits in reverse).
10034 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
10035 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
10037 // And xor with NumBits-1.
10038 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT));
10041 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
10045 SDValue X86TargetLowering::LowerCTTZ(SDValue Op, SelectionDAG &DAG) const {
10046 EVT VT = Op.getValueType();
10047 unsigned NumBits = VT.getSizeInBits();
10048 DebugLoc dl = Op.getDebugLoc();
10049 Op = Op.getOperand(0);
10051 // Issue a bsf (scan bits forward) which also sets EFLAGS.
10052 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
10053 Op = DAG.getNode(X86ISD::BSF, dl, VTs, Op);
10055 // If src is zero (i.e. bsf sets ZF), returns NumBits.
10058 DAG.getConstant(NumBits, VT),
10059 DAG.getConstant(X86::COND_E, MVT::i8),
10062 return DAG.getNode(X86ISD::CMOV, dl, VT, Ops, array_lengthof(Ops));
10065 // Lower256IntArith - Break a 256-bit integer operation into two new 128-bit
10066 // ones, and then concatenate the result back.
10067 static SDValue Lower256IntArith(SDValue Op, SelectionDAG &DAG) {
10068 EVT VT = Op.getValueType();
10070 assert(VT.getSizeInBits() == 256 && VT.isInteger() &&
10071 "Unsupported value type for operation");
10073 int NumElems = VT.getVectorNumElements();
10074 DebugLoc dl = Op.getDebugLoc();
10075 SDValue Idx0 = DAG.getConstant(0, MVT::i32);
10076 SDValue Idx1 = DAG.getConstant(NumElems/2, MVT::i32);
10078 // Extract the LHS vectors
10079 SDValue LHS = Op.getOperand(0);
10080 SDValue LHS1 = Extract128BitVector(LHS, Idx0, DAG, dl);
10081 SDValue LHS2 = Extract128BitVector(LHS, Idx1, DAG, dl);
10083 // Extract the RHS vectors
10084 SDValue RHS = Op.getOperand(1);
10085 SDValue RHS1 = Extract128BitVector(RHS, Idx0, DAG, dl);
10086 SDValue RHS2 = Extract128BitVector(RHS, Idx1, DAG, dl);
10088 MVT EltVT = VT.getVectorElementType().getSimpleVT();
10089 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
10091 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
10092 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1),
10093 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2));
10096 SDValue X86TargetLowering::LowerADD(SDValue Op, SelectionDAG &DAG) const {
10097 assert(Op.getValueType().getSizeInBits() == 256 &&
10098 Op.getValueType().isInteger() &&
10099 "Only handle AVX 256-bit vector integer operation");
10100 return Lower256IntArith(Op, DAG);
10103 SDValue X86TargetLowering::LowerSUB(SDValue Op, SelectionDAG &DAG) const {
10104 assert(Op.getValueType().getSizeInBits() == 256 &&
10105 Op.getValueType().isInteger() &&
10106 "Only handle AVX 256-bit vector integer operation");
10107 return Lower256IntArith(Op, DAG);
10110 SDValue X86TargetLowering::LowerMUL(SDValue Op, SelectionDAG &DAG) const {
10111 EVT VT = Op.getValueType();
10113 // Decompose 256-bit ops into smaller 128-bit ops.
10114 if (VT.getSizeInBits() == 256 && !Subtarget->hasAVX2())
10115 return Lower256IntArith(Op, DAG);
10117 DebugLoc dl = Op.getDebugLoc();
10119 SDValue A = Op.getOperand(0);
10120 SDValue B = Op.getOperand(1);
10122 if (VT == MVT::v4i64) {
10123 assert(Subtarget->hasAVX2() && "Lowering v4i64 multiply requires AVX2");
10125 // ulong2 Ahi = __builtin_ia32_psrlqi256( a, 32);
10126 // ulong2 Bhi = __builtin_ia32_psrlqi256( b, 32);
10127 // ulong2 AloBlo = __builtin_ia32_pmuludq256( a, b );
10128 // ulong2 AloBhi = __builtin_ia32_pmuludq256( a, Bhi );
10129 // ulong2 AhiBlo = __builtin_ia32_pmuludq256( Ahi, b );
10131 // AloBhi = __builtin_ia32_psllqi256( AloBhi, 32 );
10132 // AhiBlo = __builtin_ia32_psllqi256( AhiBlo, 32 );
10133 // return AloBlo + AloBhi + AhiBlo;
10135 SDValue Ahi = DAG.getNode(X86ISD::VSRLI, dl, VT, A,
10136 DAG.getConstant(32, MVT::i32));
10137 SDValue Bhi = DAG.getNode(X86ISD::VSRLI, dl, VT, B,
10138 DAG.getConstant(32, MVT::i32));
10139 SDValue AloBlo = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
10140 DAG.getConstant(Intrinsic::x86_avx2_pmulu_dq, MVT::i32),
10142 SDValue AloBhi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
10143 DAG.getConstant(Intrinsic::x86_avx2_pmulu_dq, MVT::i32),
10145 SDValue AhiBlo = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
10146 DAG.getConstant(Intrinsic::x86_avx2_pmulu_dq, MVT::i32),
10148 AloBhi = DAG.getNode(X86ISD::VSHLI, dl, VT, AloBhi,
10149 DAG.getConstant(32, MVT::i32));
10150 AhiBlo = DAG.getNode(X86ISD::VSHLI, dl, VT, AhiBlo,
10151 DAG.getConstant(32, MVT::i32));
10152 SDValue Res = DAG.getNode(ISD::ADD, dl, VT, AloBlo, AloBhi);
10153 Res = DAG.getNode(ISD::ADD, dl, VT, Res, AhiBlo);
10157 assert(VT == MVT::v2i64 && "Only know how to lower V2I64 multiply");
10159 // ulong2 Ahi = __builtin_ia32_psrlqi128( a, 32);
10160 // ulong2 Bhi = __builtin_ia32_psrlqi128( b, 32);
10161 // ulong2 AloBlo = __builtin_ia32_pmuludq128( a, b );
10162 // ulong2 AloBhi = __builtin_ia32_pmuludq128( a, Bhi );
10163 // ulong2 AhiBlo = __builtin_ia32_pmuludq128( Ahi, b );
10165 // AloBhi = __builtin_ia32_psllqi128( AloBhi, 32 );
10166 // AhiBlo = __builtin_ia32_psllqi128( AhiBlo, 32 );
10167 // return AloBlo + AloBhi + AhiBlo;
10169 SDValue Ahi = DAG.getNode(X86ISD::VSRLI, dl, VT, A,
10170 DAG.getConstant(32, MVT::i32));
10171 SDValue Bhi = DAG.getNode(X86ISD::VSRLI, dl, VT, B,
10172 DAG.getConstant(32, MVT::i32));
10173 SDValue AloBlo = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
10174 DAG.getConstant(Intrinsic::x86_sse2_pmulu_dq, MVT::i32),
10176 SDValue AloBhi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
10177 DAG.getConstant(Intrinsic::x86_sse2_pmulu_dq, MVT::i32),
10179 SDValue AhiBlo = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
10180 DAG.getConstant(Intrinsic::x86_sse2_pmulu_dq, MVT::i32),
10182 AloBhi = DAG.getNode(X86ISD::VSHLI, dl, VT, AloBhi,
10183 DAG.getConstant(32, MVT::i32));
10184 AhiBlo = DAG.getNode(X86ISD::VSHLI, dl, VT, AhiBlo,
10185 DAG.getConstant(32, MVT::i32));
10186 SDValue Res = DAG.getNode(ISD::ADD, dl, VT, AloBlo, AloBhi);
10187 Res = DAG.getNode(ISD::ADD, dl, VT, Res, AhiBlo);
10191 SDValue X86TargetLowering::LowerShift(SDValue Op, SelectionDAG &DAG) const {
10193 EVT VT = Op.getValueType();
10194 DebugLoc dl = Op.getDebugLoc();
10195 SDValue R = Op.getOperand(0);
10196 SDValue Amt = Op.getOperand(1);
10197 LLVMContext *Context = DAG.getContext();
10199 if (!Subtarget->hasSSE2())
10202 // Optimize shl/srl/sra with constant shift amount.
10203 if (isSplatVector(Amt.getNode())) {
10204 SDValue SclrAmt = Amt->getOperand(0);
10205 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(SclrAmt)) {
10206 uint64_t ShiftAmt = C->getZExtValue();
10208 if (VT == MVT::v2i64 || VT == MVT::v4i32 || VT == MVT::v8i16 ||
10209 (Subtarget->hasAVX2() &&
10210 (VT == MVT::v4i64 || VT == MVT::v8i32 || VT == MVT::v16i16))) {
10211 if (Op.getOpcode() == ISD::SHL)
10212 return DAG.getNode(X86ISD::VSHLI, dl, VT, R,
10213 DAG.getConstant(ShiftAmt, MVT::i32));
10214 if (Op.getOpcode() == ISD::SRL)
10215 return DAG.getNode(X86ISD::VSRLI, dl, VT, R,
10216 DAG.getConstant(ShiftAmt, MVT::i32));
10217 if (Op.getOpcode() == ISD::SRA && VT != MVT::v2i64 && VT != MVT::v4i64)
10218 return DAG.getNode(X86ISD::VSRAI, dl, VT, R,
10219 DAG.getConstant(ShiftAmt, MVT::i32));
10222 if (VT == MVT::v16i8) {
10223 if (Op.getOpcode() == ISD::SHL) {
10224 // Make a large shift.
10225 SDValue SHL = DAG.getNode(X86ISD::VSHLI, dl, MVT::v8i16, R,
10226 DAG.getConstant(ShiftAmt, MVT::i32));
10227 SHL = DAG.getNode(ISD::BITCAST, dl, VT, SHL);
10228 // Zero out the rightmost bits.
10229 SmallVector<SDValue, 16> V(16,
10230 DAG.getConstant(uint8_t(-1U << ShiftAmt),
10232 return DAG.getNode(ISD::AND, dl, VT, SHL,
10233 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 16));
10235 if (Op.getOpcode() == ISD::SRL) {
10236 // Make a large shift.
10237 SDValue SRL = DAG.getNode(X86ISD::VSRLI, dl, MVT::v8i16, R,
10238 DAG.getConstant(ShiftAmt, MVT::i32));
10239 SRL = DAG.getNode(ISD::BITCAST, dl, VT, SRL);
10240 // Zero out the leftmost bits.
10241 SmallVector<SDValue, 16> V(16,
10242 DAG.getConstant(uint8_t(-1U) >> ShiftAmt,
10244 return DAG.getNode(ISD::AND, dl, VT, SRL,
10245 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 16));
10247 if (Op.getOpcode() == ISD::SRA) {
10248 if (ShiftAmt == 7) {
10249 // R s>> 7 === R s< 0
10250 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
10251 return DAG.getNode(X86ISD::PCMPGT, dl, VT, Zeros, R);
10254 // R s>> a === ((R u>> a) ^ m) - m
10255 SDValue Res = DAG.getNode(ISD::SRL, dl, VT, R, Amt);
10256 SmallVector<SDValue, 16> V(16, DAG.getConstant(128 >> ShiftAmt,
10258 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 16);
10259 Res = DAG.getNode(ISD::XOR, dl, VT, Res, Mask);
10260 Res = DAG.getNode(ISD::SUB, dl, VT, Res, Mask);
10265 if (Subtarget->hasAVX2() && VT == MVT::v32i8) {
10266 if (Op.getOpcode() == ISD::SHL) {
10267 // Make a large shift.
10268 SDValue SHL = DAG.getNode(X86ISD::VSHLI, dl, MVT::v16i16, R,
10269 DAG.getConstant(ShiftAmt, MVT::i32));
10270 SHL = DAG.getNode(ISD::BITCAST, dl, VT, SHL);
10271 // Zero out the rightmost bits.
10272 SmallVector<SDValue, 32> V(32,
10273 DAG.getConstant(uint8_t(-1U << ShiftAmt),
10275 return DAG.getNode(ISD::AND, dl, VT, SHL,
10276 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 32));
10278 if (Op.getOpcode() == ISD::SRL) {
10279 // Make a large shift.
10280 SDValue SRL = DAG.getNode(X86ISD::VSRLI, dl, MVT::v16i16, R,
10281 DAG.getConstant(ShiftAmt, MVT::i32));
10282 SRL = DAG.getNode(ISD::BITCAST, dl, VT, SRL);
10283 // Zero out the leftmost bits.
10284 SmallVector<SDValue, 32> V(32,
10285 DAG.getConstant(uint8_t(-1U) >> ShiftAmt,
10287 return DAG.getNode(ISD::AND, dl, VT, SRL,
10288 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 32));
10290 if (Op.getOpcode() == ISD::SRA) {
10291 if (ShiftAmt == 7) {
10292 // R s>> 7 === R s< 0
10293 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
10294 return DAG.getNode(X86ISD::PCMPGT, dl, VT, Zeros, R);
10297 // R s>> a === ((R u>> a) ^ m) - m
10298 SDValue Res = DAG.getNode(ISD::SRL, dl, VT, R, Amt);
10299 SmallVector<SDValue, 32> V(32, DAG.getConstant(128 >> ShiftAmt,
10301 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 32);
10302 Res = DAG.getNode(ISD::XOR, dl, VT, Res, Mask);
10303 Res = DAG.getNode(ISD::SUB, dl, VT, Res, Mask);
10310 // Lower SHL with variable shift amount.
10311 if (VT == MVT::v4i32 && Op->getOpcode() == ISD::SHL) {
10312 Op = DAG.getNode(X86ISD::VSHLI, dl, VT, Op.getOperand(1),
10313 DAG.getConstant(23, MVT::i32));
10315 ConstantInt *CI = ConstantInt::get(*Context, APInt(32, 0x3f800000U));
10316 Constant *C = ConstantVector::getSplat(4, CI);
10317 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
10318 SDValue Addend = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
10319 MachinePointerInfo::getConstantPool(),
10320 false, false, false, 16);
10322 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Addend);
10323 Op = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, Op);
10324 Op = DAG.getNode(ISD::FP_TO_SINT, dl, VT, Op);
10325 return DAG.getNode(ISD::MUL, dl, VT, Op, R);
10327 if (VT == MVT::v16i8 && Op->getOpcode() == ISD::SHL) {
10328 assert(Subtarget->hasSSE2() && "Need SSE2 for pslli/pcmpeq.");
10331 Op = DAG.getNode(X86ISD::VSHLI, dl, MVT::v8i16, Op.getOperand(1),
10332 DAG.getConstant(5, MVT::i32));
10333 Op = DAG.getNode(ISD::BITCAST, dl, VT, Op);
10335 // Turn 'a' into a mask suitable for VSELECT
10336 SDValue VSelM = DAG.getConstant(0x80, VT);
10337 SDValue OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
10338 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
10340 SDValue CM1 = DAG.getConstant(0x0f, VT);
10341 SDValue CM2 = DAG.getConstant(0x3f, VT);
10343 // r = VSELECT(r, psllw(r & (char16)15, 4), a);
10344 SDValue M = DAG.getNode(ISD::AND, dl, VT, R, CM1);
10345 M = getTargetVShiftNode(X86ISD::VSHLI, dl, MVT::v8i16, M,
10346 DAG.getConstant(4, MVT::i32), DAG);
10347 M = DAG.getNode(ISD::BITCAST, dl, VT, M);
10348 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel, M, R);
10351 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op);
10352 OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
10353 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
10355 // r = VSELECT(r, psllw(r & (char16)63, 2), a);
10356 M = DAG.getNode(ISD::AND, dl, VT, R, CM2);
10357 M = getTargetVShiftNode(X86ISD::VSHLI, dl, MVT::v8i16, M,
10358 DAG.getConstant(2, MVT::i32), DAG);
10359 M = DAG.getNode(ISD::BITCAST, dl, VT, M);
10360 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel, M, R);
10363 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op);
10364 OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
10365 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
10367 // return VSELECT(r, r+r, a);
10368 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel,
10369 DAG.getNode(ISD::ADD, dl, VT, R, R), R);
10373 // Decompose 256-bit shifts into smaller 128-bit shifts.
10374 if (VT.getSizeInBits() == 256) {
10375 unsigned NumElems = VT.getVectorNumElements();
10376 MVT EltVT = VT.getVectorElementType().getSimpleVT();
10377 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
10379 // Extract the two vectors
10380 SDValue V1 = Extract128BitVector(R, DAG.getConstant(0, MVT::i32), DAG, dl);
10381 SDValue V2 = Extract128BitVector(R, DAG.getConstant(NumElems/2, MVT::i32),
10384 // Recreate the shift amount vectors
10385 SDValue Amt1, Amt2;
10386 if (Amt.getOpcode() == ISD::BUILD_VECTOR) {
10387 // Constant shift amount
10388 SmallVector<SDValue, 4> Amt1Csts;
10389 SmallVector<SDValue, 4> Amt2Csts;
10390 for (unsigned i = 0; i != NumElems/2; ++i)
10391 Amt1Csts.push_back(Amt->getOperand(i));
10392 for (unsigned i = NumElems/2; i != NumElems; ++i)
10393 Amt2Csts.push_back(Amt->getOperand(i));
10395 Amt1 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT,
10396 &Amt1Csts[0], NumElems/2);
10397 Amt2 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT,
10398 &Amt2Csts[0], NumElems/2);
10400 // Variable shift amount
10401 Amt1 = Extract128BitVector(Amt, DAG.getConstant(0, MVT::i32), DAG, dl);
10402 Amt2 = Extract128BitVector(Amt, DAG.getConstant(NumElems/2, MVT::i32),
10406 // Issue new vector shifts for the smaller types
10407 V1 = DAG.getNode(Op.getOpcode(), dl, NewVT, V1, Amt1);
10408 V2 = DAG.getNode(Op.getOpcode(), dl, NewVT, V2, Amt2);
10410 // Concatenate the result back
10411 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, V1, V2);
10417 SDValue X86TargetLowering::LowerXALUO(SDValue Op, SelectionDAG &DAG) const {
10418 // Lower the "add/sub/mul with overflow" instruction into a regular ins plus
10419 // a "setcc" instruction that checks the overflow flag. The "brcond" lowering
10420 // looks for this combo and may remove the "setcc" instruction if the "setcc"
10421 // has only one use.
10422 SDNode *N = Op.getNode();
10423 SDValue LHS = N->getOperand(0);
10424 SDValue RHS = N->getOperand(1);
10425 unsigned BaseOp = 0;
10427 DebugLoc DL = Op.getDebugLoc();
10428 switch (Op.getOpcode()) {
10429 default: llvm_unreachable("Unknown ovf instruction!");
10431 // A subtract of one will be selected as a INC. Note that INC doesn't
10432 // set CF, so we can't do this for UADDO.
10433 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
10435 BaseOp = X86ISD::INC;
10436 Cond = X86::COND_O;
10439 BaseOp = X86ISD::ADD;
10440 Cond = X86::COND_O;
10443 BaseOp = X86ISD::ADD;
10444 Cond = X86::COND_B;
10447 // A subtract of one will be selected as a DEC. Note that DEC doesn't
10448 // set CF, so we can't do this for USUBO.
10449 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
10451 BaseOp = X86ISD::DEC;
10452 Cond = X86::COND_O;
10455 BaseOp = X86ISD::SUB;
10456 Cond = X86::COND_O;
10459 BaseOp = X86ISD::SUB;
10460 Cond = X86::COND_B;
10463 BaseOp = X86ISD::SMUL;
10464 Cond = X86::COND_O;
10466 case ISD::UMULO: { // i64, i8 = umulo lhs, rhs --> i64, i64, i32 umul lhs,rhs
10467 SDVTList VTs = DAG.getVTList(N->getValueType(0), N->getValueType(0),
10469 SDValue Sum = DAG.getNode(X86ISD::UMUL, DL, VTs, LHS, RHS);
10472 DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
10473 DAG.getConstant(X86::COND_O, MVT::i32),
10474 SDValue(Sum.getNode(), 2));
10476 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
10480 // Also sets EFLAGS.
10481 SDVTList VTs = DAG.getVTList(N->getValueType(0), MVT::i32);
10482 SDValue Sum = DAG.getNode(BaseOp, DL, VTs, LHS, RHS);
10485 DAG.getNode(X86ISD::SETCC, DL, N->getValueType(1),
10486 DAG.getConstant(Cond, MVT::i32),
10487 SDValue(Sum.getNode(), 1));
10489 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
10492 SDValue X86TargetLowering::LowerSIGN_EXTEND_INREG(SDValue Op,
10493 SelectionDAG &DAG) const {
10494 DebugLoc dl = Op.getDebugLoc();
10495 EVT ExtraVT = cast<VTSDNode>(Op.getOperand(1))->getVT();
10496 EVT VT = Op.getValueType();
10498 if (!Subtarget->hasSSE2() || !VT.isVector())
10501 unsigned BitsDiff = VT.getScalarType().getSizeInBits() -
10502 ExtraVT.getScalarType().getSizeInBits();
10503 SDValue ShAmt = DAG.getConstant(BitsDiff, MVT::i32);
10505 switch (VT.getSimpleVT().SimpleTy) {
10506 default: return SDValue();
10509 if (!Subtarget->hasAVX())
10511 if (!Subtarget->hasAVX2()) {
10512 // needs to be split
10513 int NumElems = VT.getVectorNumElements();
10514 SDValue Idx0 = DAG.getConstant(0, MVT::i32);
10515 SDValue Idx1 = DAG.getConstant(NumElems/2, MVT::i32);
10517 // Extract the LHS vectors
10518 SDValue LHS = Op.getOperand(0);
10519 SDValue LHS1 = Extract128BitVector(LHS, Idx0, DAG, dl);
10520 SDValue LHS2 = Extract128BitVector(LHS, Idx1, DAG, dl);
10522 MVT EltVT = VT.getVectorElementType().getSimpleVT();
10523 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
10525 EVT ExtraEltVT = ExtraVT.getVectorElementType();
10526 int ExtraNumElems = ExtraVT.getVectorNumElements();
10527 ExtraVT = EVT::getVectorVT(*DAG.getContext(), ExtraEltVT,
10529 SDValue Extra = DAG.getValueType(ExtraVT);
10531 LHS1 = DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, Extra);
10532 LHS2 = DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, Extra);
10534 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, LHS1, LHS2);;
10539 SDValue Tmp1 = getTargetVShiftNode(X86ISD::VSHLI, dl, VT,
10540 Op.getOperand(0), ShAmt, DAG);
10541 return getTargetVShiftNode(X86ISD::VSRAI, dl, VT, Tmp1, ShAmt, DAG);
10547 SDValue X86TargetLowering::LowerMEMBARRIER(SDValue Op, SelectionDAG &DAG) const{
10548 DebugLoc dl = Op.getDebugLoc();
10550 // Go ahead and emit the fence on x86-64 even if we asked for no-sse2.
10551 // There isn't any reason to disable it if the target processor supports it.
10552 if (!Subtarget->hasSSE2() && !Subtarget->is64Bit()) {
10553 SDValue Chain = Op.getOperand(0);
10554 SDValue Zero = DAG.getConstant(0, MVT::i32);
10556 DAG.getRegister(X86::ESP, MVT::i32), // Base
10557 DAG.getTargetConstant(1, MVT::i8), // Scale
10558 DAG.getRegister(0, MVT::i32), // Index
10559 DAG.getTargetConstant(0, MVT::i32), // Disp
10560 DAG.getRegister(0, MVT::i32), // Segment.
10565 DAG.getMachineNode(X86::OR32mrLocked, dl, MVT::Other, Ops,
10566 array_lengthof(Ops));
10567 return SDValue(Res, 0);
10570 unsigned isDev = cast<ConstantSDNode>(Op.getOperand(5))->getZExtValue();
10572 return DAG.getNode(X86ISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0));
10574 unsigned Op1 = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
10575 unsigned Op2 = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue();
10576 unsigned Op3 = cast<ConstantSDNode>(Op.getOperand(3))->getZExtValue();
10577 unsigned Op4 = cast<ConstantSDNode>(Op.getOperand(4))->getZExtValue();
10579 // def : Pat<(membarrier (i8 0), (i8 0), (i8 0), (i8 1), (i8 1)), (SFENCE)>;
10580 if (!Op1 && !Op2 && !Op3 && Op4)
10581 return DAG.getNode(X86ISD::SFENCE, dl, MVT::Other, Op.getOperand(0));
10583 // def : Pat<(membarrier (i8 1), (i8 0), (i8 0), (i8 0), (i8 1)), (LFENCE)>;
10584 if (Op1 && !Op2 && !Op3 && !Op4)
10585 return DAG.getNode(X86ISD::LFENCE, dl, MVT::Other, Op.getOperand(0));
10587 // def : Pat<(membarrier (i8 imm), (i8 imm), (i8 imm), (i8 imm), (i8 1)),
10589 return DAG.getNode(X86ISD::MFENCE, dl, MVT::Other, Op.getOperand(0));
10592 SDValue X86TargetLowering::LowerATOMIC_FENCE(SDValue Op,
10593 SelectionDAG &DAG) const {
10594 DebugLoc dl = Op.getDebugLoc();
10595 AtomicOrdering FenceOrdering = static_cast<AtomicOrdering>(
10596 cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue());
10597 SynchronizationScope FenceScope = static_cast<SynchronizationScope>(
10598 cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue());
10600 // The only fence that needs an instruction is a sequentially-consistent
10601 // cross-thread fence.
10602 if (FenceOrdering == SequentiallyConsistent && FenceScope == CrossThread) {
10603 // Use mfence if we have SSE2 or we're on x86-64 (even if we asked for
10604 // no-sse2). There isn't any reason to disable it if the target processor
10606 if (Subtarget->hasSSE2() || Subtarget->is64Bit())
10607 return DAG.getNode(X86ISD::MFENCE, dl, MVT::Other, Op.getOperand(0));
10609 SDValue Chain = Op.getOperand(0);
10610 SDValue Zero = DAG.getConstant(0, MVT::i32);
10612 DAG.getRegister(X86::ESP, MVT::i32), // Base
10613 DAG.getTargetConstant(1, MVT::i8), // Scale
10614 DAG.getRegister(0, MVT::i32), // Index
10615 DAG.getTargetConstant(0, MVT::i32), // Disp
10616 DAG.getRegister(0, MVT::i32), // Segment.
10621 DAG.getMachineNode(X86::OR32mrLocked, dl, MVT::Other, Ops,
10622 array_lengthof(Ops));
10623 return SDValue(Res, 0);
10626 // MEMBARRIER is a compiler barrier; it codegens to a no-op.
10627 return DAG.getNode(X86ISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0));
10631 SDValue X86TargetLowering::LowerCMP_SWAP(SDValue Op, SelectionDAG &DAG) const {
10632 EVT T = Op.getValueType();
10633 DebugLoc DL = Op.getDebugLoc();
10636 switch(T.getSimpleVT().SimpleTy) {
10638 assert(false && "Invalid value type!");
10639 case MVT::i8: Reg = X86::AL; size = 1; break;
10640 case MVT::i16: Reg = X86::AX; size = 2; break;
10641 case MVT::i32: Reg = X86::EAX; size = 4; break;
10643 assert(Subtarget->is64Bit() && "Node not type legal!");
10644 Reg = X86::RAX; size = 8;
10647 SDValue cpIn = DAG.getCopyToReg(Op.getOperand(0), DL, Reg,
10648 Op.getOperand(2), SDValue());
10649 SDValue Ops[] = { cpIn.getValue(0),
10652 DAG.getTargetConstant(size, MVT::i8),
10653 cpIn.getValue(1) };
10654 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
10655 MachineMemOperand *MMO = cast<AtomicSDNode>(Op)->getMemOperand();
10656 SDValue Result = DAG.getMemIntrinsicNode(X86ISD::LCMPXCHG_DAG, DL, Tys,
10659 DAG.getCopyFromReg(Result.getValue(0), DL, Reg, T, Result.getValue(1));
10663 SDValue X86TargetLowering::LowerREADCYCLECOUNTER(SDValue Op,
10664 SelectionDAG &DAG) const {
10665 assert(Subtarget->is64Bit() && "Result not type legalized?");
10666 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
10667 SDValue TheChain = Op.getOperand(0);
10668 DebugLoc dl = Op.getDebugLoc();
10669 SDValue rd = DAG.getNode(X86ISD::RDTSC_DAG, dl, Tys, &TheChain, 1);
10670 SDValue rax = DAG.getCopyFromReg(rd, dl, X86::RAX, MVT::i64, rd.getValue(1));
10671 SDValue rdx = DAG.getCopyFromReg(rax.getValue(1), dl, X86::RDX, MVT::i64,
10673 SDValue Tmp = DAG.getNode(ISD::SHL, dl, MVT::i64, rdx,
10674 DAG.getConstant(32, MVT::i8));
10676 DAG.getNode(ISD::OR, dl, MVT::i64, rax, Tmp),
10679 return DAG.getMergeValues(Ops, 2, dl);
10682 SDValue X86TargetLowering::LowerBITCAST(SDValue Op,
10683 SelectionDAG &DAG) const {
10684 EVT SrcVT = Op.getOperand(0).getValueType();
10685 EVT DstVT = Op.getValueType();
10686 assert(Subtarget->is64Bit() && !Subtarget->hasSSE2() &&
10687 Subtarget->hasMMX() && "Unexpected custom BITCAST");
10688 assert((DstVT == MVT::i64 ||
10689 (DstVT.isVector() && DstVT.getSizeInBits()==64)) &&
10690 "Unexpected custom BITCAST");
10691 // i64 <=> MMX conversions are Legal.
10692 if (SrcVT==MVT::i64 && DstVT.isVector())
10694 if (DstVT==MVT::i64 && SrcVT.isVector())
10696 // MMX <=> MMX conversions are Legal.
10697 if (SrcVT.isVector() && DstVT.isVector())
10699 // All other conversions need to be expanded.
10703 SDValue X86TargetLowering::LowerLOAD_SUB(SDValue Op, SelectionDAG &DAG) const {
10704 SDNode *Node = Op.getNode();
10705 DebugLoc dl = Node->getDebugLoc();
10706 EVT T = Node->getValueType(0);
10707 SDValue negOp = DAG.getNode(ISD::SUB, dl, T,
10708 DAG.getConstant(0, T), Node->getOperand(2));
10709 return DAG.getAtomic(ISD::ATOMIC_LOAD_ADD, dl,
10710 cast<AtomicSDNode>(Node)->getMemoryVT(),
10711 Node->getOperand(0),
10712 Node->getOperand(1), negOp,
10713 cast<AtomicSDNode>(Node)->getSrcValue(),
10714 cast<AtomicSDNode>(Node)->getAlignment(),
10715 cast<AtomicSDNode>(Node)->getOrdering(),
10716 cast<AtomicSDNode>(Node)->getSynchScope());
10719 static SDValue LowerATOMIC_STORE(SDValue Op, SelectionDAG &DAG) {
10720 SDNode *Node = Op.getNode();
10721 DebugLoc dl = Node->getDebugLoc();
10722 EVT VT = cast<AtomicSDNode>(Node)->getMemoryVT();
10724 // Convert seq_cst store -> xchg
10725 // Convert wide store -> swap (-> cmpxchg8b/cmpxchg16b)
10726 // FIXME: On 32-bit, store -> fist or movq would be more efficient
10727 // (The only way to get a 16-byte store is cmpxchg16b)
10728 // FIXME: 16-byte ATOMIC_SWAP isn't actually hooked up at the moment.
10729 if (cast<AtomicSDNode>(Node)->getOrdering() == SequentiallyConsistent ||
10730 !DAG.getTargetLoweringInfo().isTypeLegal(VT)) {
10731 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_SWAP, dl,
10732 cast<AtomicSDNode>(Node)->getMemoryVT(),
10733 Node->getOperand(0),
10734 Node->getOperand(1), Node->getOperand(2),
10735 cast<AtomicSDNode>(Node)->getMemOperand(),
10736 cast<AtomicSDNode>(Node)->getOrdering(),
10737 cast<AtomicSDNode>(Node)->getSynchScope());
10738 return Swap.getValue(1);
10740 // Other atomic stores have a simple pattern.
10744 static SDValue LowerADDC_ADDE_SUBC_SUBE(SDValue Op, SelectionDAG &DAG) {
10745 EVT VT = Op.getNode()->getValueType(0);
10747 // Let legalize expand this if it isn't a legal type yet.
10748 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
10751 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
10754 bool ExtraOp = false;
10755 switch (Op.getOpcode()) {
10756 default: assert(0 && "Invalid code");
10757 case ISD::ADDC: Opc = X86ISD::ADD; break;
10758 case ISD::ADDE: Opc = X86ISD::ADC; ExtraOp = true; break;
10759 case ISD::SUBC: Opc = X86ISD::SUB; break;
10760 case ISD::SUBE: Opc = X86ISD::SBB; ExtraOp = true; break;
10764 return DAG.getNode(Opc, Op->getDebugLoc(), VTs, Op.getOperand(0),
10766 return DAG.getNode(Opc, Op->getDebugLoc(), VTs, Op.getOperand(0),
10767 Op.getOperand(1), Op.getOperand(2));
10770 /// LowerOperation - Provide custom lowering hooks for some operations.
10772 SDValue X86TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
10773 switch (Op.getOpcode()) {
10774 default: llvm_unreachable("Should not custom lower this!");
10775 case ISD::SIGN_EXTEND_INREG: return LowerSIGN_EXTEND_INREG(Op,DAG);
10776 case ISD::MEMBARRIER: return LowerMEMBARRIER(Op,DAG);
10777 case ISD::ATOMIC_FENCE: return LowerATOMIC_FENCE(Op,DAG);
10778 case ISD::ATOMIC_CMP_SWAP: return LowerCMP_SWAP(Op,DAG);
10779 case ISD::ATOMIC_LOAD_SUB: return LowerLOAD_SUB(Op,DAG);
10780 case ISD::ATOMIC_STORE: return LowerATOMIC_STORE(Op,DAG);
10781 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
10782 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG);
10783 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
10784 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
10785 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG);
10786 case ISD::EXTRACT_SUBVECTOR: return LowerEXTRACT_SUBVECTOR(Op, DAG);
10787 case ISD::INSERT_SUBVECTOR: return LowerINSERT_SUBVECTOR(Op, DAG);
10788 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
10789 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
10790 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
10791 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
10792 case ISD::ExternalSymbol: return LowerExternalSymbol(Op, DAG);
10793 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
10794 case ISD::SHL_PARTS:
10795 case ISD::SRA_PARTS:
10796 case ISD::SRL_PARTS: return LowerShiftParts(Op, DAG);
10797 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG);
10798 case ISD::UINT_TO_FP: return LowerUINT_TO_FP(Op, DAG);
10799 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG);
10800 case ISD::FP_TO_UINT: return LowerFP_TO_UINT(Op, DAG);
10801 case ISD::FABS: return LowerFABS(Op, DAG);
10802 case ISD::FNEG: return LowerFNEG(Op, DAG);
10803 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG);
10804 case ISD::FGETSIGN: return LowerFGETSIGN(Op, DAG);
10805 case ISD::SETCC: return LowerSETCC(Op, DAG);
10806 case ISD::SELECT: return LowerSELECT(Op, DAG);
10807 case ISD::BRCOND: return LowerBRCOND(Op, DAG);
10808 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
10809 case ISD::VASTART: return LowerVASTART(Op, DAG);
10810 case ISD::VAARG: return LowerVAARG(Op, DAG);
10811 case ISD::VACOPY: return LowerVACOPY(Op, DAG);
10812 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
10813 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
10814 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
10815 case ISD::FRAME_TO_ARGS_OFFSET:
10816 return LowerFRAME_TO_ARGS_OFFSET(Op, DAG);
10817 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
10818 case ISD::EH_RETURN: return LowerEH_RETURN(Op, DAG);
10819 case ISD::INIT_TRAMPOLINE: return LowerINIT_TRAMPOLINE(Op, DAG);
10820 case ISD::ADJUST_TRAMPOLINE: return LowerADJUST_TRAMPOLINE(Op, DAG);
10821 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
10822 case ISD::CTLZ: return LowerCTLZ(Op, DAG);
10823 case ISD::CTLZ_ZERO_UNDEF: return LowerCTLZ_ZERO_UNDEF(Op, DAG);
10824 case ISD::CTTZ: return LowerCTTZ(Op, DAG);
10825 case ISD::MUL: return LowerMUL(Op, DAG);
10828 case ISD::SHL: return LowerShift(Op, DAG);
10834 case ISD::UMULO: return LowerXALUO(Op, DAG);
10835 case ISD::READCYCLECOUNTER: return LowerREADCYCLECOUNTER(Op, DAG);
10836 case ISD::BITCAST: return LowerBITCAST(Op, DAG);
10840 case ISD::SUBE: return LowerADDC_ADDE_SUBC_SUBE(Op, DAG);
10841 case ISD::ADD: return LowerADD(Op, DAG);
10842 case ISD::SUB: return LowerSUB(Op, DAG);
10846 static void ReplaceATOMIC_LOAD(SDNode *Node,
10847 SmallVectorImpl<SDValue> &Results,
10848 SelectionDAG &DAG) {
10849 DebugLoc dl = Node->getDebugLoc();
10850 EVT VT = cast<AtomicSDNode>(Node)->getMemoryVT();
10852 // Convert wide load -> cmpxchg8b/cmpxchg16b
10853 // FIXME: On 32-bit, load -> fild or movq would be more efficient
10854 // (The only way to get a 16-byte load is cmpxchg16b)
10855 // FIXME: 16-byte ATOMIC_CMP_SWAP isn't actually hooked up at the moment.
10856 SDValue Zero = DAG.getConstant(0, VT);
10857 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_CMP_SWAP, dl, VT,
10858 Node->getOperand(0),
10859 Node->getOperand(1), Zero, Zero,
10860 cast<AtomicSDNode>(Node)->getMemOperand(),
10861 cast<AtomicSDNode>(Node)->getOrdering(),
10862 cast<AtomicSDNode>(Node)->getSynchScope());
10863 Results.push_back(Swap.getValue(0));
10864 Results.push_back(Swap.getValue(1));
10867 void X86TargetLowering::
10868 ReplaceATOMIC_BINARY_64(SDNode *Node, SmallVectorImpl<SDValue>&Results,
10869 SelectionDAG &DAG, unsigned NewOp) const {
10870 DebugLoc dl = Node->getDebugLoc();
10871 assert (Node->getValueType(0) == MVT::i64 &&
10872 "Only know how to expand i64 atomics");
10874 SDValue Chain = Node->getOperand(0);
10875 SDValue In1 = Node->getOperand(1);
10876 SDValue In2L = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
10877 Node->getOperand(2), DAG.getIntPtrConstant(0));
10878 SDValue In2H = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
10879 Node->getOperand(2), DAG.getIntPtrConstant(1));
10880 SDValue Ops[] = { Chain, In1, In2L, In2H };
10881 SDVTList Tys = DAG.getVTList(MVT::i32, MVT::i32, MVT::Other);
10883 DAG.getMemIntrinsicNode(NewOp, dl, Tys, Ops, 4, MVT::i64,
10884 cast<MemSDNode>(Node)->getMemOperand());
10885 SDValue OpsF[] = { Result.getValue(0), Result.getValue(1)};
10886 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, OpsF, 2));
10887 Results.push_back(Result.getValue(2));
10890 /// ReplaceNodeResults - Replace a node with an illegal result type
10891 /// with a new node built out of custom code.
10892 void X86TargetLowering::ReplaceNodeResults(SDNode *N,
10893 SmallVectorImpl<SDValue>&Results,
10894 SelectionDAG &DAG) const {
10895 DebugLoc dl = N->getDebugLoc();
10896 switch (N->getOpcode()) {
10898 assert(false && "Do not know how to custom type legalize this operation!");
10900 case ISD::SIGN_EXTEND_INREG:
10905 // We don't want to expand or promote these.
10907 case ISD::FP_TO_SINT: {
10908 std::pair<SDValue,SDValue> Vals =
10909 FP_TO_INTHelper(SDValue(N, 0), DAG, true);
10910 SDValue FIST = Vals.first, StackSlot = Vals.second;
10911 if (FIST.getNode() != 0) {
10912 EVT VT = N->getValueType(0);
10913 // Return a load from the stack slot.
10914 Results.push_back(DAG.getLoad(VT, dl, FIST, StackSlot,
10915 MachinePointerInfo(),
10916 false, false, false, 0));
10920 case ISD::READCYCLECOUNTER: {
10921 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
10922 SDValue TheChain = N->getOperand(0);
10923 SDValue rd = DAG.getNode(X86ISD::RDTSC_DAG, dl, Tys, &TheChain, 1);
10924 SDValue eax = DAG.getCopyFromReg(rd, dl, X86::EAX, MVT::i32,
10926 SDValue edx = DAG.getCopyFromReg(eax.getValue(1), dl, X86::EDX, MVT::i32,
10928 // Use a buildpair to merge the two 32-bit values into a 64-bit one.
10929 SDValue Ops[] = { eax, edx };
10930 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Ops, 2));
10931 Results.push_back(edx.getValue(1));
10934 case ISD::ATOMIC_CMP_SWAP: {
10935 EVT T = N->getValueType(0);
10936 assert((T == MVT::i64 || T == MVT::i128) && "can only expand cmpxchg pair");
10937 bool Regs64bit = T == MVT::i128;
10938 EVT HalfT = Regs64bit ? MVT::i64 : MVT::i32;
10939 SDValue cpInL, cpInH;
10940 cpInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2),
10941 DAG.getConstant(0, HalfT));
10942 cpInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2),
10943 DAG.getConstant(1, HalfT));
10944 cpInL = DAG.getCopyToReg(N->getOperand(0), dl,
10945 Regs64bit ? X86::RAX : X86::EAX,
10947 cpInH = DAG.getCopyToReg(cpInL.getValue(0), dl,
10948 Regs64bit ? X86::RDX : X86::EDX,
10949 cpInH, cpInL.getValue(1));
10950 SDValue swapInL, swapInH;
10951 swapInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3),
10952 DAG.getConstant(0, HalfT));
10953 swapInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3),
10954 DAG.getConstant(1, HalfT));
10955 swapInL = DAG.getCopyToReg(cpInH.getValue(0), dl,
10956 Regs64bit ? X86::RBX : X86::EBX,
10957 swapInL, cpInH.getValue(1));
10958 swapInH = DAG.getCopyToReg(swapInL.getValue(0), dl,
10959 Regs64bit ? X86::RCX : X86::ECX,
10960 swapInH, swapInL.getValue(1));
10961 SDValue Ops[] = { swapInH.getValue(0),
10963 swapInH.getValue(1) };
10964 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
10965 MachineMemOperand *MMO = cast<AtomicSDNode>(N)->getMemOperand();
10966 unsigned Opcode = Regs64bit ? X86ISD::LCMPXCHG16_DAG :
10967 X86ISD::LCMPXCHG8_DAG;
10968 SDValue Result = DAG.getMemIntrinsicNode(Opcode, dl, Tys,
10970 SDValue cpOutL = DAG.getCopyFromReg(Result.getValue(0), dl,
10971 Regs64bit ? X86::RAX : X86::EAX,
10972 HalfT, Result.getValue(1));
10973 SDValue cpOutH = DAG.getCopyFromReg(cpOutL.getValue(1), dl,
10974 Regs64bit ? X86::RDX : X86::EDX,
10975 HalfT, cpOutL.getValue(2));
10976 SDValue OpsF[] = { cpOutL.getValue(0), cpOutH.getValue(0)};
10977 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, T, OpsF, 2));
10978 Results.push_back(cpOutH.getValue(1));
10981 case ISD::ATOMIC_LOAD_ADD:
10982 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMADD64_DAG);
10984 case ISD::ATOMIC_LOAD_AND:
10985 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMAND64_DAG);
10987 case ISD::ATOMIC_LOAD_NAND:
10988 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMNAND64_DAG);
10990 case ISD::ATOMIC_LOAD_OR:
10991 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMOR64_DAG);
10993 case ISD::ATOMIC_LOAD_SUB:
10994 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMSUB64_DAG);
10996 case ISD::ATOMIC_LOAD_XOR:
10997 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMXOR64_DAG);
10999 case ISD::ATOMIC_SWAP:
11000 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMSWAP64_DAG);
11002 case ISD::ATOMIC_LOAD:
11003 ReplaceATOMIC_LOAD(N, Results, DAG);
11007 const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
11009 default: return NULL;
11010 case X86ISD::BSF: return "X86ISD::BSF";
11011 case X86ISD::BSR: return "X86ISD::BSR";
11012 case X86ISD::SHLD: return "X86ISD::SHLD";
11013 case X86ISD::SHRD: return "X86ISD::SHRD";
11014 case X86ISD::FAND: return "X86ISD::FAND";
11015 case X86ISD::FOR: return "X86ISD::FOR";
11016 case X86ISD::FXOR: return "X86ISD::FXOR";
11017 case X86ISD::FSRL: return "X86ISD::FSRL";
11018 case X86ISD::FILD: return "X86ISD::FILD";
11019 case X86ISD::FILD_FLAG: return "X86ISD::FILD_FLAG";
11020 case X86ISD::FP_TO_INT16_IN_MEM: return "X86ISD::FP_TO_INT16_IN_MEM";
11021 case X86ISD::FP_TO_INT32_IN_MEM: return "X86ISD::FP_TO_INT32_IN_MEM";
11022 case X86ISD::FP_TO_INT64_IN_MEM: return "X86ISD::FP_TO_INT64_IN_MEM";
11023 case X86ISD::FLD: return "X86ISD::FLD";
11024 case X86ISD::FST: return "X86ISD::FST";
11025 case X86ISD::CALL: return "X86ISD::CALL";
11026 case X86ISD::RDTSC_DAG: return "X86ISD::RDTSC_DAG";
11027 case X86ISD::BT: return "X86ISD::BT";
11028 case X86ISD::CMP: return "X86ISD::CMP";
11029 case X86ISD::COMI: return "X86ISD::COMI";
11030 case X86ISD::UCOMI: return "X86ISD::UCOMI";
11031 case X86ISD::SETCC: return "X86ISD::SETCC";
11032 case X86ISD::SETCC_CARRY: return "X86ISD::SETCC_CARRY";
11033 case X86ISD::FSETCCsd: return "X86ISD::FSETCCsd";
11034 case X86ISD::FSETCCss: return "X86ISD::FSETCCss";
11035 case X86ISD::CMOV: return "X86ISD::CMOV";
11036 case X86ISD::BRCOND: return "X86ISD::BRCOND";
11037 case X86ISD::RET_FLAG: return "X86ISD::RET_FLAG";
11038 case X86ISD::REP_STOS: return "X86ISD::REP_STOS";
11039 case X86ISD::REP_MOVS: return "X86ISD::REP_MOVS";
11040 case X86ISD::GlobalBaseReg: return "X86ISD::GlobalBaseReg";
11041 case X86ISD::Wrapper: return "X86ISD::Wrapper";
11042 case X86ISD::WrapperRIP: return "X86ISD::WrapperRIP";
11043 case X86ISD::PEXTRB: return "X86ISD::PEXTRB";
11044 case X86ISD::PEXTRW: return "X86ISD::PEXTRW";
11045 case X86ISD::INSERTPS: return "X86ISD::INSERTPS";
11046 case X86ISD::PINSRB: return "X86ISD::PINSRB";
11047 case X86ISD::PINSRW: return "X86ISD::PINSRW";
11048 case X86ISD::PSHUFB: return "X86ISD::PSHUFB";
11049 case X86ISD::ANDNP: return "X86ISD::ANDNP";
11050 case X86ISD::PSIGN: return "X86ISD::PSIGN";
11051 case X86ISD::BLENDV: return "X86ISD::BLENDV";
11052 case X86ISD::HADD: return "X86ISD::HADD";
11053 case X86ISD::HSUB: return "X86ISD::HSUB";
11054 case X86ISD::FHADD: return "X86ISD::FHADD";
11055 case X86ISD::FHSUB: return "X86ISD::FHSUB";
11056 case X86ISD::FMAX: return "X86ISD::FMAX";
11057 case X86ISD::FMIN: return "X86ISD::FMIN";
11058 case X86ISD::FRSQRT: return "X86ISD::FRSQRT";
11059 case X86ISD::FRCP: return "X86ISD::FRCP";
11060 case X86ISD::TLSADDR: return "X86ISD::TLSADDR";
11061 case X86ISD::TLSCALL: return "X86ISD::TLSCALL";
11062 case X86ISD::EH_RETURN: return "X86ISD::EH_RETURN";
11063 case X86ISD::TC_RETURN: return "X86ISD::TC_RETURN";
11064 case X86ISD::FNSTCW16m: return "X86ISD::FNSTCW16m";
11065 case X86ISD::LCMPXCHG_DAG: return "X86ISD::LCMPXCHG_DAG";
11066 case X86ISD::LCMPXCHG8_DAG: return "X86ISD::LCMPXCHG8_DAG";
11067 case X86ISD::ATOMADD64_DAG: return "X86ISD::ATOMADD64_DAG";
11068 case X86ISD::ATOMSUB64_DAG: return "X86ISD::ATOMSUB64_DAG";
11069 case X86ISD::ATOMOR64_DAG: return "X86ISD::ATOMOR64_DAG";
11070 case X86ISD::ATOMXOR64_DAG: return "X86ISD::ATOMXOR64_DAG";
11071 case X86ISD::ATOMAND64_DAG: return "X86ISD::ATOMAND64_DAG";
11072 case X86ISD::ATOMNAND64_DAG: return "X86ISD::ATOMNAND64_DAG";
11073 case X86ISD::VZEXT_MOVL: return "X86ISD::VZEXT_MOVL";
11074 case X86ISD::VZEXT_LOAD: return "X86ISD::VZEXT_LOAD";
11075 case X86ISD::VSHLDQ: return "X86ISD::VSHLDQ";
11076 case X86ISD::VSRLDQ: return "X86ISD::VSRLDQ";
11077 case X86ISD::VSHL: return "X86ISD::VSHL";
11078 case X86ISD::VSRL: return "X86ISD::VSRL";
11079 case X86ISD::VSRA: return "X86ISD::VSRA";
11080 case X86ISD::VSHLI: return "X86ISD::VSHLI";
11081 case X86ISD::VSRLI: return "X86ISD::VSRLI";
11082 case X86ISD::VSRAI: return "X86ISD::VSRAI";
11083 case X86ISD::CMPP: return "X86ISD::CMPP";
11084 case X86ISD::PCMPEQ: return "X86ISD::PCMPEQ";
11085 case X86ISD::PCMPGT: return "X86ISD::PCMPGT";
11086 case X86ISD::ADD: return "X86ISD::ADD";
11087 case X86ISD::SUB: return "X86ISD::SUB";
11088 case X86ISD::ADC: return "X86ISD::ADC";
11089 case X86ISD::SBB: return "X86ISD::SBB";
11090 case X86ISD::SMUL: return "X86ISD::SMUL";
11091 case X86ISD::UMUL: return "X86ISD::UMUL";
11092 case X86ISD::INC: return "X86ISD::INC";
11093 case X86ISD::DEC: return "X86ISD::DEC";
11094 case X86ISD::OR: return "X86ISD::OR";
11095 case X86ISD::XOR: return "X86ISD::XOR";
11096 case X86ISD::AND: return "X86ISD::AND";
11097 case X86ISD::ANDN: return "X86ISD::ANDN";
11098 case X86ISD::BLSI: return "X86ISD::BLSI";
11099 case X86ISD::BLSMSK: return "X86ISD::BLSMSK";
11100 case X86ISD::BLSR: return "X86ISD::BLSR";
11101 case X86ISD::MUL_IMM: return "X86ISD::MUL_IMM";
11102 case X86ISD::PTEST: return "X86ISD::PTEST";
11103 case X86ISD::TESTP: return "X86ISD::TESTP";
11104 case X86ISD::PALIGN: return "X86ISD::PALIGN";
11105 case X86ISD::PSHUFD: return "X86ISD::PSHUFD";
11106 case X86ISD::PSHUFHW: return "X86ISD::PSHUFHW";
11107 case X86ISD::PSHUFLW: return "X86ISD::PSHUFLW";
11108 case X86ISD::SHUFP: return "X86ISD::SHUFP";
11109 case X86ISD::MOVLHPS: return "X86ISD::MOVLHPS";
11110 case X86ISD::MOVLHPD: return "X86ISD::MOVLHPD";
11111 case X86ISD::MOVHLPS: return "X86ISD::MOVHLPS";
11112 case X86ISD::MOVLPS: return "X86ISD::MOVLPS";
11113 case X86ISD::MOVLPD: return "X86ISD::MOVLPD";
11114 case X86ISD::MOVDDUP: return "X86ISD::MOVDDUP";
11115 case X86ISD::MOVSHDUP: return "X86ISD::MOVSHDUP";
11116 case X86ISD::MOVSLDUP: return "X86ISD::MOVSLDUP";
11117 case X86ISD::MOVSD: return "X86ISD::MOVSD";
11118 case X86ISD::MOVSS: return "X86ISD::MOVSS";
11119 case X86ISD::UNPCKL: return "X86ISD::UNPCKL";
11120 case X86ISD::UNPCKH: return "X86ISD::UNPCKH";
11121 case X86ISD::VBROADCAST: return "X86ISD::VBROADCAST";
11122 case X86ISD::VPERMILP: return "X86ISD::VPERMILP";
11123 case X86ISD::VPERM2X128: return "X86ISD::VPERM2X128";
11124 case X86ISD::VASTART_SAVE_XMM_REGS: return "X86ISD::VASTART_SAVE_XMM_REGS";
11125 case X86ISD::VAARG_64: return "X86ISD::VAARG_64";
11126 case X86ISD::WIN_ALLOCA: return "X86ISD::WIN_ALLOCA";
11127 case X86ISD::MEMBARRIER: return "X86ISD::MEMBARRIER";
11128 case X86ISD::SEG_ALLOCA: return "X86ISD::SEG_ALLOCA";
11132 // isLegalAddressingMode - Return true if the addressing mode represented
11133 // by AM is legal for this target, for a load/store of the specified type.
11134 bool X86TargetLowering::isLegalAddressingMode(const AddrMode &AM,
11136 // X86 supports extremely general addressing modes.
11137 CodeModel::Model M = getTargetMachine().getCodeModel();
11138 Reloc::Model R = getTargetMachine().getRelocationModel();
11140 // X86 allows a sign-extended 32-bit immediate field as a displacement.
11141 if (!X86::isOffsetSuitableForCodeModel(AM.BaseOffs, M, AM.BaseGV != NULL))
11146 Subtarget->ClassifyGlobalReference(AM.BaseGV, getTargetMachine());
11148 // If a reference to this global requires an extra load, we can't fold it.
11149 if (isGlobalStubReference(GVFlags))
11152 // If BaseGV requires a register for the PIC base, we cannot also have a
11153 // BaseReg specified.
11154 if (AM.HasBaseReg && isGlobalRelativeToPICBase(GVFlags))
11157 // If lower 4G is not available, then we must use rip-relative addressing.
11158 if ((M != CodeModel::Small || R != Reloc::Static) &&
11159 Subtarget->is64Bit() && (AM.BaseOffs || AM.Scale > 1))
11163 switch (AM.Scale) {
11169 // These scales always work.
11174 // These scales are formed with basereg+scalereg. Only accept if there is
11179 default: // Other stuff never works.
11187 bool X86TargetLowering::isTruncateFree(Type *Ty1, Type *Ty2) const {
11188 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
11190 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits();
11191 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits();
11192 if (NumBits1 <= NumBits2)
11197 bool X86TargetLowering::isTruncateFree(EVT VT1, EVT VT2) const {
11198 if (!VT1.isInteger() || !VT2.isInteger())
11200 unsigned NumBits1 = VT1.getSizeInBits();
11201 unsigned NumBits2 = VT2.getSizeInBits();
11202 if (NumBits1 <= NumBits2)
11207 bool X86TargetLowering::isZExtFree(Type *Ty1, Type *Ty2) const {
11208 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
11209 return Ty1->isIntegerTy(32) && Ty2->isIntegerTy(64) && Subtarget->is64Bit();
11212 bool X86TargetLowering::isZExtFree(EVT VT1, EVT VT2) const {
11213 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
11214 return VT1 == MVT::i32 && VT2 == MVT::i64 && Subtarget->is64Bit();
11217 bool X86TargetLowering::isNarrowingProfitable(EVT VT1, EVT VT2) const {
11218 // i16 instructions are longer (0x66 prefix) and potentially slower.
11219 return !(VT1 == MVT::i32 && VT2 == MVT::i16);
11222 /// isShuffleMaskLegal - Targets can use this to indicate that they only
11223 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
11224 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
11225 /// are assumed to be legal.
11227 X86TargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M,
11229 // Very little shuffling can be done for 64-bit vectors right now.
11230 if (VT.getSizeInBits() == 64)
11233 // FIXME: pshufb, blends, shifts.
11234 return (VT.getVectorNumElements() == 2 ||
11235 ShuffleVectorSDNode::isSplatMask(&M[0], VT) ||
11236 isMOVLMask(M, VT) ||
11237 isSHUFPMask(M, VT, Subtarget->hasAVX()) ||
11238 isPSHUFDMask(M, VT) ||
11239 isPSHUFHWMask(M, VT) ||
11240 isPSHUFLWMask(M, VT) ||
11241 isPALIGNRMask(M, VT, Subtarget) ||
11242 isUNPCKLMask(M, VT, Subtarget->hasAVX2()) ||
11243 isUNPCKHMask(M, VT, Subtarget->hasAVX2()) ||
11244 isUNPCKL_v_undef_Mask(M, VT, Subtarget->hasAVX2()) ||
11245 isUNPCKH_v_undef_Mask(M, VT, Subtarget->hasAVX2()));
11249 X86TargetLowering::isVectorClearMaskLegal(const SmallVectorImpl<int> &Mask,
11251 unsigned NumElts = VT.getVectorNumElements();
11252 // FIXME: This collection of masks seems suspect.
11255 if (NumElts == 4 && VT.getSizeInBits() == 128) {
11256 return (isMOVLMask(Mask, VT) ||
11257 isCommutedMOVLMask(Mask, VT, true) ||
11258 isSHUFPMask(Mask, VT, Subtarget->hasAVX()) ||
11259 isSHUFPMask(Mask, VT, Subtarget->hasAVX(), /* Commuted */ true));
11264 //===----------------------------------------------------------------------===//
11265 // X86 Scheduler Hooks
11266 //===----------------------------------------------------------------------===//
11268 // private utility function
11269 MachineBasicBlock *
11270 X86TargetLowering::EmitAtomicBitwiseWithCustomInserter(MachineInstr *bInstr,
11271 MachineBasicBlock *MBB,
11278 TargetRegisterClass *RC,
11279 bool invSrc) const {
11280 // For the atomic bitwise operator, we generate
11283 // ld t1 = [bitinstr.addr]
11284 // op t2 = t1, [bitinstr.val]
11286 // lcs dest = [bitinstr.addr], t2 [EAX is implicit]
11288 // fallthrough -->nextMBB
11289 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
11290 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
11291 MachineFunction::iterator MBBIter = MBB;
11294 /// First build the CFG
11295 MachineFunction *F = MBB->getParent();
11296 MachineBasicBlock *thisMBB = MBB;
11297 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB);
11298 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB);
11299 F->insert(MBBIter, newMBB);
11300 F->insert(MBBIter, nextMBB);
11302 // Transfer the remainder of thisMBB and its successor edges to nextMBB.
11303 nextMBB->splice(nextMBB->begin(), thisMBB,
11304 llvm::next(MachineBasicBlock::iterator(bInstr)),
11306 nextMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
11308 // Update thisMBB to fall through to newMBB
11309 thisMBB->addSuccessor(newMBB);
11311 // newMBB jumps to itself and fall through to nextMBB
11312 newMBB->addSuccessor(nextMBB);
11313 newMBB->addSuccessor(newMBB);
11315 // Insert instructions into newMBB based on incoming instruction
11316 assert(bInstr->getNumOperands() < X86::AddrNumOperands + 4 &&
11317 "unexpected number of operands");
11318 DebugLoc dl = bInstr->getDebugLoc();
11319 MachineOperand& destOper = bInstr->getOperand(0);
11320 MachineOperand* argOpers[2 + X86::AddrNumOperands];
11321 int numArgs = bInstr->getNumOperands() - 1;
11322 for (int i=0; i < numArgs; ++i)
11323 argOpers[i] = &bInstr->getOperand(i+1);
11325 // x86 address has 4 operands: base, index, scale, and displacement
11326 int lastAddrIndx = X86::AddrNumOperands - 1; // [0,3]
11327 int valArgIndx = lastAddrIndx + 1;
11329 unsigned t1 = F->getRegInfo().createVirtualRegister(RC);
11330 MachineInstrBuilder MIB = BuildMI(newMBB, dl, TII->get(LoadOpc), t1);
11331 for (int i=0; i <= lastAddrIndx; ++i)
11332 (*MIB).addOperand(*argOpers[i]);
11334 unsigned tt = F->getRegInfo().createVirtualRegister(RC);
11336 MIB = BuildMI(newMBB, dl, TII->get(notOpc), tt).addReg(t1);
11341 unsigned t2 = F->getRegInfo().createVirtualRegister(RC);
11342 assert((argOpers[valArgIndx]->isReg() ||
11343 argOpers[valArgIndx]->isImm()) &&
11344 "invalid operand");
11345 if (argOpers[valArgIndx]->isReg())
11346 MIB = BuildMI(newMBB, dl, TII->get(regOpc), t2);
11348 MIB = BuildMI(newMBB, dl, TII->get(immOpc), t2);
11350 (*MIB).addOperand(*argOpers[valArgIndx]);
11352 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), EAXreg);
11355 MIB = BuildMI(newMBB, dl, TII->get(CXchgOpc));
11356 for (int i=0; i <= lastAddrIndx; ++i)
11357 (*MIB).addOperand(*argOpers[i]);
11359 assert(bInstr->hasOneMemOperand() && "Unexpected number of memoperand");
11360 (*MIB).setMemRefs(bInstr->memoperands_begin(),
11361 bInstr->memoperands_end());
11363 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), destOper.getReg());
11364 MIB.addReg(EAXreg);
11367 BuildMI(newMBB, dl, TII->get(X86::JNE_4)).addMBB(newMBB);
11369 bInstr->eraseFromParent(); // The pseudo instruction is gone now.
11373 // private utility function: 64 bit atomics on 32 bit host.
11374 MachineBasicBlock *
11375 X86TargetLowering::EmitAtomicBit6432WithCustomInserter(MachineInstr *bInstr,
11376 MachineBasicBlock *MBB,
11381 bool invSrc) const {
11382 // For the atomic bitwise operator, we generate
11383 // thisMBB (instructions are in pairs, except cmpxchg8b)
11384 // ld t1,t2 = [bitinstr.addr]
11386 // out1, out2 = phi (thisMBB, t1/t2) (newMBB, t3/t4)
11387 // op t5, t6 <- out1, out2, [bitinstr.val]
11388 // (for SWAP, substitute: mov t5, t6 <- [bitinstr.val])
11389 // mov ECX, EBX <- t5, t6
11390 // mov EAX, EDX <- t1, t2
11391 // cmpxchg8b [bitinstr.addr] [EAX, EDX, EBX, ECX implicit]
11392 // mov t3, t4 <- EAX, EDX
11394 // result in out1, out2
11395 // fallthrough -->nextMBB
11397 const TargetRegisterClass *RC = X86::GR32RegisterClass;
11398 const unsigned LoadOpc = X86::MOV32rm;
11399 const unsigned NotOpc = X86::NOT32r;
11400 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
11401 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
11402 MachineFunction::iterator MBBIter = MBB;
11405 /// First build the CFG
11406 MachineFunction *F = MBB->getParent();
11407 MachineBasicBlock *thisMBB = MBB;
11408 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB);
11409 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB);
11410 F->insert(MBBIter, newMBB);
11411 F->insert(MBBIter, nextMBB);
11413 // Transfer the remainder of thisMBB and its successor edges to nextMBB.
11414 nextMBB->splice(nextMBB->begin(), thisMBB,
11415 llvm::next(MachineBasicBlock::iterator(bInstr)),
11417 nextMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
11419 // Update thisMBB to fall through to newMBB
11420 thisMBB->addSuccessor(newMBB);
11422 // newMBB jumps to itself and fall through to nextMBB
11423 newMBB->addSuccessor(nextMBB);
11424 newMBB->addSuccessor(newMBB);
11426 DebugLoc dl = bInstr->getDebugLoc();
11427 // Insert instructions into newMBB based on incoming instruction
11428 // There are 8 "real" operands plus 9 implicit def/uses, ignored here.
11429 assert(bInstr->getNumOperands() < X86::AddrNumOperands + 14 &&
11430 "unexpected number of operands");
11431 MachineOperand& dest1Oper = bInstr->getOperand(0);
11432 MachineOperand& dest2Oper = bInstr->getOperand(1);
11433 MachineOperand* argOpers[2 + X86::AddrNumOperands];
11434 for (int i=0; i < 2 + X86::AddrNumOperands; ++i) {
11435 argOpers[i] = &bInstr->getOperand(i+2);
11437 // We use some of the operands multiple times, so conservatively just
11438 // clear any kill flags that might be present.
11439 if (argOpers[i]->isReg() && argOpers[i]->isUse())
11440 argOpers[i]->setIsKill(false);
11443 // x86 address has 5 operands: base, index, scale, displacement, and segment.
11444 int lastAddrIndx = X86::AddrNumOperands - 1; // [0,3]
11446 unsigned t1 = F->getRegInfo().createVirtualRegister(RC);
11447 MachineInstrBuilder MIB = BuildMI(thisMBB, dl, TII->get(LoadOpc), t1);
11448 for (int i=0; i <= lastAddrIndx; ++i)
11449 (*MIB).addOperand(*argOpers[i]);
11450 unsigned t2 = F->getRegInfo().createVirtualRegister(RC);
11451 MIB = BuildMI(thisMBB, dl, TII->get(LoadOpc), t2);
11452 // add 4 to displacement.
11453 for (int i=0; i <= lastAddrIndx-2; ++i)
11454 (*MIB).addOperand(*argOpers[i]);
11455 MachineOperand newOp3 = *(argOpers[3]);
11456 if (newOp3.isImm())
11457 newOp3.setImm(newOp3.getImm()+4);
11459 newOp3.setOffset(newOp3.getOffset()+4);
11460 (*MIB).addOperand(newOp3);
11461 (*MIB).addOperand(*argOpers[lastAddrIndx]);
11463 // t3/4 are defined later, at the bottom of the loop
11464 unsigned t3 = F->getRegInfo().createVirtualRegister(RC);
11465 unsigned t4 = F->getRegInfo().createVirtualRegister(RC);
11466 BuildMI(newMBB, dl, TII->get(X86::PHI), dest1Oper.getReg())
11467 .addReg(t1).addMBB(thisMBB).addReg(t3).addMBB(newMBB);
11468 BuildMI(newMBB, dl, TII->get(X86::PHI), dest2Oper.getReg())
11469 .addReg(t2).addMBB(thisMBB).addReg(t4).addMBB(newMBB);
11471 // The subsequent operations should be using the destination registers of
11472 //the PHI instructions.
11474 t1 = F->getRegInfo().createVirtualRegister(RC);
11475 t2 = F->getRegInfo().createVirtualRegister(RC);
11476 MIB = BuildMI(newMBB, dl, TII->get(NotOpc), t1).addReg(dest1Oper.getReg());
11477 MIB = BuildMI(newMBB, dl, TII->get(NotOpc), t2).addReg(dest2Oper.getReg());
11479 t1 = dest1Oper.getReg();
11480 t2 = dest2Oper.getReg();
11483 int valArgIndx = lastAddrIndx + 1;
11484 assert((argOpers[valArgIndx]->isReg() ||
11485 argOpers[valArgIndx]->isImm()) &&
11486 "invalid operand");
11487 unsigned t5 = F->getRegInfo().createVirtualRegister(RC);
11488 unsigned t6 = F->getRegInfo().createVirtualRegister(RC);
11489 if (argOpers[valArgIndx]->isReg())
11490 MIB = BuildMI(newMBB, dl, TII->get(regOpcL), t5);
11492 MIB = BuildMI(newMBB, dl, TII->get(immOpcL), t5);
11493 if (regOpcL != X86::MOV32rr)
11495 (*MIB).addOperand(*argOpers[valArgIndx]);
11496 assert(argOpers[valArgIndx + 1]->isReg() ==
11497 argOpers[valArgIndx]->isReg());
11498 assert(argOpers[valArgIndx + 1]->isImm() ==
11499 argOpers[valArgIndx]->isImm());
11500 if (argOpers[valArgIndx + 1]->isReg())
11501 MIB = BuildMI(newMBB, dl, TII->get(regOpcH), t6);
11503 MIB = BuildMI(newMBB, dl, TII->get(immOpcH), t6);
11504 if (regOpcH != X86::MOV32rr)
11506 (*MIB).addOperand(*argOpers[valArgIndx + 1]);
11508 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::EAX);
11510 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::EDX);
11513 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::EBX);
11515 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::ECX);
11518 MIB = BuildMI(newMBB, dl, TII->get(X86::LCMPXCHG8B));
11519 for (int i=0; i <= lastAddrIndx; ++i)
11520 (*MIB).addOperand(*argOpers[i]);
11522 assert(bInstr->hasOneMemOperand() && "Unexpected number of memoperand");
11523 (*MIB).setMemRefs(bInstr->memoperands_begin(),
11524 bInstr->memoperands_end());
11526 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), t3);
11527 MIB.addReg(X86::EAX);
11528 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), t4);
11529 MIB.addReg(X86::EDX);
11532 BuildMI(newMBB, dl, TII->get(X86::JNE_4)).addMBB(newMBB);
11534 bInstr->eraseFromParent(); // The pseudo instruction is gone now.
11538 // private utility function
11539 MachineBasicBlock *
11540 X86TargetLowering::EmitAtomicMinMaxWithCustomInserter(MachineInstr *mInstr,
11541 MachineBasicBlock *MBB,
11542 unsigned cmovOpc) const {
11543 // For the atomic min/max operator, we generate
11546 // ld t1 = [min/max.addr]
11547 // mov t2 = [min/max.val]
11549 // cmov[cond] t2 = t1
11551 // lcs dest = [bitinstr.addr], t2 [EAX is implicit]
11553 // fallthrough -->nextMBB
11555 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
11556 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
11557 MachineFunction::iterator MBBIter = MBB;
11560 /// First build the CFG
11561 MachineFunction *F = MBB->getParent();
11562 MachineBasicBlock *thisMBB = MBB;
11563 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB);
11564 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB);
11565 F->insert(MBBIter, newMBB);
11566 F->insert(MBBIter, nextMBB);
11568 // Transfer the remainder of thisMBB and its successor edges to nextMBB.
11569 nextMBB->splice(nextMBB->begin(), thisMBB,
11570 llvm::next(MachineBasicBlock::iterator(mInstr)),
11572 nextMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
11574 // Update thisMBB to fall through to newMBB
11575 thisMBB->addSuccessor(newMBB);
11577 // newMBB jumps to newMBB and fall through to nextMBB
11578 newMBB->addSuccessor(nextMBB);
11579 newMBB->addSuccessor(newMBB);
11581 DebugLoc dl = mInstr->getDebugLoc();
11582 // Insert instructions into newMBB based on incoming instruction
11583 assert(mInstr->getNumOperands() < X86::AddrNumOperands + 4 &&
11584 "unexpected number of operands");
11585 MachineOperand& destOper = mInstr->getOperand(0);
11586 MachineOperand* argOpers[2 + X86::AddrNumOperands];
11587 int numArgs = mInstr->getNumOperands() - 1;
11588 for (int i=0; i < numArgs; ++i)
11589 argOpers[i] = &mInstr->getOperand(i+1);
11591 // x86 address has 4 operands: base, index, scale, and displacement
11592 int lastAddrIndx = X86::AddrNumOperands - 1; // [0,3]
11593 int valArgIndx = lastAddrIndx + 1;
11595 unsigned t1 = F->getRegInfo().createVirtualRegister(X86::GR32RegisterClass);
11596 MachineInstrBuilder MIB = BuildMI(newMBB, dl, TII->get(X86::MOV32rm), t1);
11597 for (int i=0; i <= lastAddrIndx; ++i)
11598 (*MIB).addOperand(*argOpers[i]);
11600 // We only support register and immediate values
11601 assert((argOpers[valArgIndx]->isReg() ||
11602 argOpers[valArgIndx]->isImm()) &&
11603 "invalid operand");
11605 unsigned t2 = F->getRegInfo().createVirtualRegister(X86::GR32RegisterClass);
11606 if (argOpers[valArgIndx]->isReg())
11607 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), t2);
11609 MIB = BuildMI(newMBB, dl, TII->get(X86::MOV32rr), t2);
11610 (*MIB).addOperand(*argOpers[valArgIndx]);
11612 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::EAX);
11615 MIB = BuildMI(newMBB, dl, TII->get(X86::CMP32rr));
11620 unsigned t3 = F->getRegInfo().createVirtualRegister(X86::GR32RegisterClass);
11621 MIB = BuildMI(newMBB, dl, TII->get(cmovOpc),t3);
11625 // Cmp and exchange if none has modified the memory location
11626 MIB = BuildMI(newMBB, dl, TII->get(X86::LCMPXCHG32));
11627 for (int i=0; i <= lastAddrIndx; ++i)
11628 (*MIB).addOperand(*argOpers[i]);
11630 assert(mInstr->hasOneMemOperand() && "Unexpected number of memoperand");
11631 (*MIB).setMemRefs(mInstr->memoperands_begin(),
11632 mInstr->memoperands_end());
11634 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), destOper.getReg());
11635 MIB.addReg(X86::EAX);
11638 BuildMI(newMBB, dl, TII->get(X86::JNE_4)).addMBB(newMBB);
11640 mInstr->eraseFromParent(); // The pseudo instruction is gone now.
11644 // FIXME: When we get size specific XMM0 registers, i.e. XMM0_V16I8
11645 // or XMM0_V32I8 in AVX all of this code can be replaced with that
11646 // in the .td file.
11647 MachineBasicBlock *
11648 X86TargetLowering::EmitPCMP(MachineInstr *MI, MachineBasicBlock *BB,
11649 unsigned numArgs, bool memArg) const {
11650 assert(Subtarget->hasSSE42() &&
11651 "Target must have SSE4.2 or AVX features enabled");
11653 DebugLoc dl = MI->getDebugLoc();
11654 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
11656 if (!Subtarget->hasAVX()) {
11658 Opc = numArgs == 3 ? X86::PCMPISTRM128rm : X86::PCMPESTRM128rm;
11660 Opc = numArgs == 3 ? X86::PCMPISTRM128rr : X86::PCMPESTRM128rr;
11663 Opc = numArgs == 3 ? X86::VPCMPISTRM128rm : X86::VPCMPESTRM128rm;
11665 Opc = numArgs == 3 ? X86::VPCMPISTRM128rr : X86::VPCMPESTRM128rr;
11668 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(Opc));
11669 for (unsigned i = 0; i < numArgs; ++i) {
11670 MachineOperand &Op = MI->getOperand(i+1);
11671 if (!(Op.isReg() && Op.isImplicit()))
11672 MIB.addOperand(Op);
11674 BuildMI(*BB, MI, dl,
11675 TII->get(Subtarget->hasAVX() ? X86::VMOVAPSrr : X86::MOVAPSrr),
11676 MI->getOperand(0).getReg())
11677 .addReg(X86::XMM0);
11679 MI->eraseFromParent();
11683 MachineBasicBlock *
11684 X86TargetLowering::EmitMonitor(MachineInstr *MI, MachineBasicBlock *BB) const {
11685 DebugLoc dl = MI->getDebugLoc();
11686 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
11688 // Address into RAX/EAX, other two args into ECX, EDX.
11689 unsigned MemOpc = Subtarget->is64Bit() ? X86::LEA64r : X86::LEA32r;
11690 unsigned MemReg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
11691 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(MemOpc), MemReg);
11692 for (int i = 0; i < X86::AddrNumOperands; ++i)
11693 MIB.addOperand(MI->getOperand(i));
11695 unsigned ValOps = X86::AddrNumOperands;
11696 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::ECX)
11697 .addReg(MI->getOperand(ValOps).getReg());
11698 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::EDX)
11699 .addReg(MI->getOperand(ValOps+1).getReg());
11701 // The instruction doesn't actually take any operands though.
11702 BuildMI(*BB, MI, dl, TII->get(X86::MONITORrrr));
11704 MI->eraseFromParent(); // The pseudo is gone now.
11708 MachineBasicBlock *
11709 X86TargetLowering::EmitMwait(MachineInstr *MI, MachineBasicBlock *BB) const {
11710 DebugLoc dl = MI->getDebugLoc();
11711 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
11713 // First arg in ECX, the second in EAX.
11714 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::ECX)
11715 .addReg(MI->getOperand(0).getReg());
11716 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::EAX)
11717 .addReg(MI->getOperand(1).getReg());
11719 // The instruction doesn't actually take any operands though.
11720 BuildMI(*BB, MI, dl, TII->get(X86::MWAITrr));
11722 MI->eraseFromParent(); // The pseudo is gone now.
11726 MachineBasicBlock *
11727 X86TargetLowering::EmitVAARG64WithCustomInserter(
11729 MachineBasicBlock *MBB) const {
11730 // Emit va_arg instruction on X86-64.
11732 // Operands to this pseudo-instruction:
11733 // 0 ) Output : destination address (reg)
11734 // 1-5) Input : va_list address (addr, i64mem)
11735 // 6 ) ArgSize : Size (in bytes) of vararg type
11736 // 7 ) ArgMode : 0=overflow only, 1=use gp_offset, 2=use fp_offset
11737 // 8 ) Align : Alignment of type
11738 // 9 ) EFLAGS (implicit-def)
11740 assert(MI->getNumOperands() == 10 && "VAARG_64 should have 10 operands!");
11741 assert(X86::AddrNumOperands == 5 && "VAARG_64 assumes 5 address operands");
11743 unsigned DestReg = MI->getOperand(0).getReg();
11744 MachineOperand &Base = MI->getOperand(1);
11745 MachineOperand &Scale = MI->getOperand(2);
11746 MachineOperand &Index = MI->getOperand(3);
11747 MachineOperand &Disp = MI->getOperand(4);
11748 MachineOperand &Segment = MI->getOperand(5);
11749 unsigned ArgSize = MI->getOperand(6).getImm();
11750 unsigned ArgMode = MI->getOperand(7).getImm();
11751 unsigned Align = MI->getOperand(8).getImm();
11753 // Memory Reference
11754 assert(MI->hasOneMemOperand() && "Expected VAARG_64 to have one memoperand");
11755 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
11756 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
11758 // Machine Information
11759 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
11760 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
11761 const TargetRegisterClass *AddrRegClass = getRegClassFor(MVT::i64);
11762 const TargetRegisterClass *OffsetRegClass = getRegClassFor(MVT::i32);
11763 DebugLoc DL = MI->getDebugLoc();
11765 // struct va_list {
11768 // i64 overflow_area (address)
11769 // i64 reg_save_area (address)
11771 // sizeof(va_list) = 24
11772 // alignment(va_list) = 8
11774 unsigned TotalNumIntRegs = 6;
11775 unsigned TotalNumXMMRegs = 8;
11776 bool UseGPOffset = (ArgMode == 1);
11777 bool UseFPOffset = (ArgMode == 2);
11778 unsigned MaxOffset = TotalNumIntRegs * 8 +
11779 (UseFPOffset ? TotalNumXMMRegs * 16 : 0);
11781 /* Align ArgSize to a multiple of 8 */
11782 unsigned ArgSizeA8 = (ArgSize + 7) & ~7;
11783 bool NeedsAlign = (Align > 8);
11785 MachineBasicBlock *thisMBB = MBB;
11786 MachineBasicBlock *overflowMBB;
11787 MachineBasicBlock *offsetMBB;
11788 MachineBasicBlock *endMBB;
11790 unsigned OffsetDestReg = 0; // Argument address computed by offsetMBB
11791 unsigned OverflowDestReg = 0; // Argument address computed by overflowMBB
11792 unsigned OffsetReg = 0;
11794 if (!UseGPOffset && !UseFPOffset) {
11795 // If we only pull from the overflow region, we don't create a branch.
11796 // We don't need to alter control flow.
11797 OffsetDestReg = 0; // unused
11798 OverflowDestReg = DestReg;
11801 overflowMBB = thisMBB;
11804 // First emit code to check if gp_offset (or fp_offset) is below the bound.
11805 // If so, pull the argument from reg_save_area. (branch to offsetMBB)
11806 // If not, pull from overflow_area. (branch to overflowMBB)
11811 // offsetMBB overflowMBB
11816 // Registers for the PHI in endMBB
11817 OffsetDestReg = MRI.createVirtualRegister(AddrRegClass);
11818 OverflowDestReg = MRI.createVirtualRegister(AddrRegClass);
11820 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
11821 MachineFunction *MF = MBB->getParent();
11822 overflowMBB = MF->CreateMachineBasicBlock(LLVM_BB);
11823 offsetMBB = MF->CreateMachineBasicBlock(LLVM_BB);
11824 endMBB = MF->CreateMachineBasicBlock(LLVM_BB);
11826 MachineFunction::iterator MBBIter = MBB;
11829 // Insert the new basic blocks
11830 MF->insert(MBBIter, offsetMBB);
11831 MF->insert(MBBIter, overflowMBB);
11832 MF->insert(MBBIter, endMBB);
11834 // Transfer the remainder of MBB and its successor edges to endMBB.
11835 endMBB->splice(endMBB->begin(), thisMBB,
11836 llvm::next(MachineBasicBlock::iterator(MI)),
11838 endMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
11840 // Make offsetMBB and overflowMBB successors of thisMBB
11841 thisMBB->addSuccessor(offsetMBB);
11842 thisMBB->addSuccessor(overflowMBB);
11844 // endMBB is a successor of both offsetMBB and overflowMBB
11845 offsetMBB->addSuccessor(endMBB);
11846 overflowMBB->addSuccessor(endMBB);
11848 // Load the offset value into a register
11849 OffsetReg = MRI.createVirtualRegister(OffsetRegClass);
11850 BuildMI(thisMBB, DL, TII->get(X86::MOV32rm), OffsetReg)
11854 .addDisp(Disp, UseFPOffset ? 4 : 0)
11855 .addOperand(Segment)
11856 .setMemRefs(MMOBegin, MMOEnd);
11858 // Check if there is enough room left to pull this argument.
11859 BuildMI(thisMBB, DL, TII->get(X86::CMP32ri))
11861 .addImm(MaxOffset + 8 - ArgSizeA8);
11863 // Branch to "overflowMBB" if offset >= max
11864 // Fall through to "offsetMBB" otherwise
11865 BuildMI(thisMBB, DL, TII->get(X86::GetCondBranchFromCond(X86::COND_AE)))
11866 .addMBB(overflowMBB);
11869 // In offsetMBB, emit code to use the reg_save_area.
11871 assert(OffsetReg != 0);
11873 // Read the reg_save_area address.
11874 unsigned RegSaveReg = MRI.createVirtualRegister(AddrRegClass);
11875 BuildMI(offsetMBB, DL, TII->get(X86::MOV64rm), RegSaveReg)
11880 .addOperand(Segment)
11881 .setMemRefs(MMOBegin, MMOEnd);
11883 // Zero-extend the offset
11884 unsigned OffsetReg64 = MRI.createVirtualRegister(AddrRegClass);
11885 BuildMI(offsetMBB, DL, TII->get(X86::SUBREG_TO_REG), OffsetReg64)
11888 .addImm(X86::sub_32bit);
11890 // Add the offset to the reg_save_area to get the final address.
11891 BuildMI(offsetMBB, DL, TII->get(X86::ADD64rr), OffsetDestReg)
11892 .addReg(OffsetReg64)
11893 .addReg(RegSaveReg);
11895 // Compute the offset for the next argument
11896 unsigned NextOffsetReg = MRI.createVirtualRegister(OffsetRegClass);
11897 BuildMI(offsetMBB, DL, TII->get(X86::ADD32ri), NextOffsetReg)
11899 .addImm(UseFPOffset ? 16 : 8);
11901 // Store it back into the va_list.
11902 BuildMI(offsetMBB, DL, TII->get(X86::MOV32mr))
11906 .addDisp(Disp, UseFPOffset ? 4 : 0)
11907 .addOperand(Segment)
11908 .addReg(NextOffsetReg)
11909 .setMemRefs(MMOBegin, MMOEnd);
11912 BuildMI(offsetMBB, DL, TII->get(X86::JMP_4))
11917 // Emit code to use overflow area
11920 // Load the overflow_area address into a register.
11921 unsigned OverflowAddrReg = MRI.createVirtualRegister(AddrRegClass);
11922 BuildMI(overflowMBB, DL, TII->get(X86::MOV64rm), OverflowAddrReg)
11927 .addOperand(Segment)
11928 .setMemRefs(MMOBegin, MMOEnd);
11930 // If we need to align it, do so. Otherwise, just copy the address
11931 // to OverflowDestReg.
11933 // Align the overflow address
11934 assert((Align & (Align-1)) == 0 && "Alignment must be a power of 2");
11935 unsigned TmpReg = MRI.createVirtualRegister(AddrRegClass);
11937 // aligned_addr = (addr + (align-1)) & ~(align-1)
11938 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), TmpReg)
11939 .addReg(OverflowAddrReg)
11942 BuildMI(overflowMBB, DL, TII->get(X86::AND64ri32), OverflowDestReg)
11944 .addImm(~(uint64_t)(Align-1));
11946 BuildMI(overflowMBB, DL, TII->get(TargetOpcode::COPY), OverflowDestReg)
11947 .addReg(OverflowAddrReg);
11950 // Compute the next overflow address after this argument.
11951 // (the overflow address should be kept 8-byte aligned)
11952 unsigned NextAddrReg = MRI.createVirtualRegister(AddrRegClass);
11953 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), NextAddrReg)
11954 .addReg(OverflowDestReg)
11955 .addImm(ArgSizeA8);
11957 // Store the new overflow address.
11958 BuildMI(overflowMBB, DL, TII->get(X86::MOV64mr))
11963 .addOperand(Segment)
11964 .addReg(NextAddrReg)
11965 .setMemRefs(MMOBegin, MMOEnd);
11967 // If we branched, emit the PHI to the front of endMBB.
11969 BuildMI(*endMBB, endMBB->begin(), DL,
11970 TII->get(X86::PHI), DestReg)
11971 .addReg(OffsetDestReg).addMBB(offsetMBB)
11972 .addReg(OverflowDestReg).addMBB(overflowMBB);
11975 // Erase the pseudo instruction
11976 MI->eraseFromParent();
11981 MachineBasicBlock *
11982 X86TargetLowering::EmitVAStartSaveXMMRegsWithCustomInserter(
11984 MachineBasicBlock *MBB) const {
11985 // Emit code to save XMM registers to the stack. The ABI says that the
11986 // number of registers to save is given in %al, so it's theoretically
11987 // possible to do an indirect jump trick to avoid saving all of them,
11988 // however this code takes a simpler approach and just executes all
11989 // of the stores if %al is non-zero. It's less code, and it's probably
11990 // easier on the hardware branch predictor, and stores aren't all that
11991 // expensive anyway.
11993 // Create the new basic blocks. One block contains all the XMM stores,
11994 // and one block is the final destination regardless of whether any
11995 // stores were performed.
11996 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
11997 MachineFunction *F = MBB->getParent();
11998 MachineFunction::iterator MBBIter = MBB;
12000 MachineBasicBlock *XMMSaveMBB = F->CreateMachineBasicBlock(LLVM_BB);
12001 MachineBasicBlock *EndMBB = F->CreateMachineBasicBlock(LLVM_BB);
12002 F->insert(MBBIter, XMMSaveMBB);
12003 F->insert(MBBIter, EndMBB);
12005 // Transfer the remainder of MBB and its successor edges to EndMBB.
12006 EndMBB->splice(EndMBB->begin(), MBB,
12007 llvm::next(MachineBasicBlock::iterator(MI)),
12009 EndMBB->transferSuccessorsAndUpdatePHIs(MBB);
12011 // The original block will now fall through to the XMM save block.
12012 MBB->addSuccessor(XMMSaveMBB);
12013 // The XMMSaveMBB will fall through to the end block.
12014 XMMSaveMBB->addSuccessor(EndMBB);
12016 // Now add the instructions.
12017 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
12018 DebugLoc DL = MI->getDebugLoc();
12020 unsigned CountReg = MI->getOperand(0).getReg();
12021 int64_t RegSaveFrameIndex = MI->getOperand(1).getImm();
12022 int64_t VarArgsFPOffset = MI->getOperand(2).getImm();
12024 if (!Subtarget->isTargetWin64()) {
12025 // If %al is 0, branch around the XMM save block.
12026 BuildMI(MBB, DL, TII->get(X86::TEST8rr)).addReg(CountReg).addReg(CountReg);
12027 BuildMI(MBB, DL, TII->get(X86::JE_4)).addMBB(EndMBB);
12028 MBB->addSuccessor(EndMBB);
12031 unsigned MOVOpc = Subtarget->hasAVX() ? X86::VMOVAPSmr : X86::MOVAPSmr;
12032 // In the XMM save block, save all the XMM argument registers.
12033 for (int i = 3, e = MI->getNumOperands(); i != e; ++i) {
12034 int64_t Offset = (i - 3) * 16 + VarArgsFPOffset;
12035 MachineMemOperand *MMO =
12036 F->getMachineMemOperand(
12037 MachinePointerInfo::getFixedStack(RegSaveFrameIndex, Offset),
12038 MachineMemOperand::MOStore,
12039 /*Size=*/16, /*Align=*/16);
12040 BuildMI(XMMSaveMBB, DL, TII->get(MOVOpc))
12041 .addFrameIndex(RegSaveFrameIndex)
12042 .addImm(/*Scale=*/1)
12043 .addReg(/*IndexReg=*/0)
12044 .addImm(/*Disp=*/Offset)
12045 .addReg(/*Segment=*/0)
12046 .addReg(MI->getOperand(i).getReg())
12047 .addMemOperand(MMO);
12050 MI->eraseFromParent(); // The pseudo instruction is gone now.
12055 // Check whether the given instruction should have had a kill marker on
12056 // the EFLAGS operand.
12057 static bool shouldHaveEFlagsKill(MachineBasicBlock::iterator SelectItr,
12058 MachineBasicBlock* BB) {
12059 for (MachineBasicBlock::iterator miI(llvm::next(SelectItr)), miE = BB->end();
12060 miI != miE; ++miI) {
12061 const MachineInstr& mi = *miI;
12062 if (mi.readsRegister(X86::EFLAGS)) {
12065 if (mi.definesRegister(X86::EFLAGS)) {
12066 // Should have kill-flag - update below.
12071 // We found a def, or hit the end of the basic block. SelectMI should have a
12072 // kill flag on EFLAGS.
12073 MachineInstr& SelectMI = *SelectItr;
12074 MachineOperand* EFlagsOp = SelectMI.findRegisterUseOperand(X86::EFLAGS);
12075 assert(EFlagsOp != 0 && "No EFLAGS operand on select instruction?");
12076 EFlagsOp->setIsKill();
12080 MachineBasicBlock *
12081 X86TargetLowering::EmitLoweredSelect(MachineInstr *MI,
12082 MachineBasicBlock *BB) const {
12083 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
12084 DebugLoc DL = MI->getDebugLoc();
12086 // To "insert" a SELECT_CC instruction, we actually have to insert the
12087 // diamond control-flow pattern. The incoming instruction knows the
12088 // destination vreg to set, the condition code register to branch on, the
12089 // true/false values to select between, and a branch opcode to use.
12090 const BasicBlock *LLVM_BB = BB->getBasicBlock();
12091 MachineFunction::iterator It = BB;
12097 // cmpTY ccX, r1, r2
12099 // fallthrough --> copy0MBB
12100 MachineBasicBlock *thisMBB = BB;
12101 MachineFunction *F = BB->getParent();
12102 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
12103 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
12104 F->insert(It, copy0MBB);
12105 F->insert(It, sinkMBB);
12107 // If the EFLAGS register isn't dead in the terminator, then claim that it's
12108 // live into the sink and copy blocks.
12109 if (!MI->killsRegister(X86::EFLAGS)) {
12110 if (!shouldHaveEFlagsKill(MI, BB)) {
12111 copy0MBB->addLiveIn(X86::EFLAGS);
12112 sinkMBB->addLiveIn(X86::EFLAGS);
12116 // Transfer the remainder of BB and its successor edges to sinkMBB.
12117 sinkMBB->splice(sinkMBB->begin(), BB,
12118 llvm::next(MachineBasicBlock::iterator(MI)),
12120 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
12122 // Add the true and fallthrough blocks as its successors.
12123 BB->addSuccessor(copy0MBB);
12124 BB->addSuccessor(sinkMBB);
12126 // Create the conditional branch instruction.
12128 X86::GetCondBranchFromCond((X86::CondCode)MI->getOperand(3).getImm());
12129 BuildMI(BB, DL, TII->get(Opc)).addMBB(sinkMBB);
12132 // %FalseValue = ...
12133 // # fallthrough to sinkMBB
12134 copy0MBB->addSuccessor(sinkMBB);
12137 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
12139 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
12140 TII->get(X86::PHI), MI->getOperand(0).getReg())
12141 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB)
12142 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
12144 MI->eraseFromParent(); // The pseudo instruction is gone now.
12148 MachineBasicBlock *
12149 X86TargetLowering::EmitLoweredSegAlloca(MachineInstr *MI, MachineBasicBlock *BB,
12150 bool Is64Bit) const {
12151 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
12152 DebugLoc DL = MI->getDebugLoc();
12153 MachineFunction *MF = BB->getParent();
12154 const BasicBlock *LLVM_BB = BB->getBasicBlock();
12156 assert(getTargetMachine().Options.EnableSegmentedStacks);
12158 unsigned TlsReg = Is64Bit ? X86::FS : X86::GS;
12159 unsigned TlsOffset = Is64Bit ? 0x70 : 0x30;
12162 // ... [Till the alloca]
12163 // If stacklet is not large enough, jump to mallocMBB
12166 // Allocate by subtracting from RSP
12167 // Jump to continueMBB
12170 // Allocate by call to runtime
12174 // [rest of original BB]
12177 MachineBasicBlock *mallocMBB = MF->CreateMachineBasicBlock(LLVM_BB);
12178 MachineBasicBlock *bumpMBB = MF->CreateMachineBasicBlock(LLVM_BB);
12179 MachineBasicBlock *continueMBB = MF->CreateMachineBasicBlock(LLVM_BB);
12181 MachineRegisterInfo &MRI = MF->getRegInfo();
12182 const TargetRegisterClass *AddrRegClass =
12183 getRegClassFor(Is64Bit ? MVT::i64:MVT::i32);
12185 unsigned mallocPtrVReg = MRI.createVirtualRegister(AddrRegClass),
12186 bumpSPPtrVReg = MRI.createVirtualRegister(AddrRegClass),
12187 tmpSPVReg = MRI.createVirtualRegister(AddrRegClass),
12188 SPLimitVReg = MRI.createVirtualRegister(AddrRegClass),
12189 sizeVReg = MI->getOperand(1).getReg(),
12190 physSPReg = Is64Bit ? X86::RSP : X86::ESP;
12192 MachineFunction::iterator MBBIter = BB;
12195 MF->insert(MBBIter, bumpMBB);
12196 MF->insert(MBBIter, mallocMBB);
12197 MF->insert(MBBIter, continueMBB);
12199 continueMBB->splice(continueMBB->begin(), BB, llvm::next
12200 (MachineBasicBlock::iterator(MI)), BB->end());
12201 continueMBB->transferSuccessorsAndUpdatePHIs(BB);
12203 // Add code to the main basic block to check if the stack limit has been hit,
12204 // and if so, jump to mallocMBB otherwise to bumpMBB.
12205 BuildMI(BB, DL, TII->get(TargetOpcode::COPY), tmpSPVReg).addReg(physSPReg);
12206 BuildMI(BB, DL, TII->get(Is64Bit ? X86::SUB64rr:X86::SUB32rr), SPLimitVReg)
12207 .addReg(tmpSPVReg).addReg(sizeVReg);
12208 BuildMI(BB, DL, TII->get(Is64Bit ? X86::CMP64mr:X86::CMP32mr))
12209 .addReg(0).addImm(1).addReg(0).addImm(TlsOffset).addReg(TlsReg)
12210 .addReg(SPLimitVReg);
12211 BuildMI(BB, DL, TII->get(X86::JG_4)).addMBB(mallocMBB);
12213 // bumpMBB simply decreases the stack pointer, since we know the current
12214 // stacklet has enough space.
12215 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), physSPReg)
12216 .addReg(SPLimitVReg);
12217 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), bumpSPPtrVReg)
12218 .addReg(SPLimitVReg);
12219 BuildMI(bumpMBB, DL, TII->get(X86::JMP_4)).addMBB(continueMBB);
12221 // Calls into a routine in libgcc to allocate more space from the heap.
12223 BuildMI(mallocMBB, DL, TII->get(X86::MOV64rr), X86::RDI)
12225 BuildMI(mallocMBB, DL, TII->get(X86::CALL64pcrel32))
12226 .addExternalSymbol("__morestack_allocate_stack_space").addReg(X86::RDI);
12228 BuildMI(mallocMBB, DL, TII->get(X86::SUB32ri), physSPReg).addReg(physSPReg)
12230 BuildMI(mallocMBB, DL, TII->get(X86::PUSH32r)).addReg(sizeVReg);
12231 BuildMI(mallocMBB, DL, TII->get(X86::CALLpcrel32))
12232 .addExternalSymbol("__morestack_allocate_stack_space");
12236 BuildMI(mallocMBB, DL, TII->get(X86::ADD32ri), physSPReg).addReg(physSPReg)
12239 BuildMI(mallocMBB, DL, TII->get(TargetOpcode::COPY), mallocPtrVReg)
12240 .addReg(Is64Bit ? X86::RAX : X86::EAX);
12241 BuildMI(mallocMBB, DL, TII->get(X86::JMP_4)).addMBB(continueMBB);
12243 // Set up the CFG correctly.
12244 BB->addSuccessor(bumpMBB);
12245 BB->addSuccessor(mallocMBB);
12246 mallocMBB->addSuccessor(continueMBB);
12247 bumpMBB->addSuccessor(continueMBB);
12249 // Take care of the PHI nodes.
12250 BuildMI(*continueMBB, continueMBB->begin(), DL, TII->get(X86::PHI),
12251 MI->getOperand(0).getReg())
12252 .addReg(mallocPtrVReg).addMBB(mallocMBB)
12253 .addReg(bumpSPPtrVReg).addMBB(bumpMBB);
12255 // Delete the original pseudo instruction.
12256 MI->eraseFromParent();
12259 return continueMBB;
12262 MachineBasicBlock *
12263 X86TargetLowering::EmitLoweredWinAlloca(MachineInstr *MI,
12264 MachineBasicBlock *BB) const {
12265 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
12266 DebugLoc DL = MI->getDebugLoc();
12268 assert(!Subtarget->isTargetEnvMacho());
12270 // The lowering is pretty easy: we're just emitting the call to _alloca. The
12271 // non-trivial part is impdef of ESP.
12273 if (Subtarget->isTargetWin64()) {
12274 if (Subtarget->isTargetCygMing()) {
12275 // ___chkstk(Mingw64):
12276 // Clobbers R10, R11, RAX and EFLAGS.
12278 BuildMI(*BB, MI, DL, TII->get(X86::W64ALLOCA))
12279 .addExternalSymbol("___chkstk")
12280 .addReg(X86::RAX, RegState::Implicit)
12281 .addReg(X86::RSP, RegState::Implicit)
12282 .addReg(X86::RAX, RegState::Define | RegState::Implicit)
12283 .addReg(X86::RSP, RegState::Define | RegState::Implicit)
12284 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
12286 // __chkstk(MSVCRT): does not update stack pointer.
12287 // Clobbers R10, R11 and EFLAGS.
12288 // FIXME: RAX(allocated size) might be reused and not killed.
12289 BuildMI(*BB, MI, DL, TII->get(X86::W64ALLOCA))
12290 .addExternalSymbol("__chkstk")
12291 .addReg(X86::RAX, RegState::Implicit)
12292 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
12293 // RAX has the offset to subtracted from RSP.
12294 BuildMI(*BB, MI, DL, TII->get(X86::SUB64rr), X86::RSP)
12299 const char *StackProbeSymbol =
12300 Subtarget->isTargetWindows() ? "_chkstk" : "_alloca";
12302 BuildMI(*BB, MI, DL, TII->get(X86::CALLpcrel32))
12303 .addExternalSymbol(StackProbeSymbol)
12304 .addReg(X86::EAX, RegState::Implicit)
12305 .addReg(X86::ESP, RegState::Implicit)
12306 .addReg(X86::EAX, RegState::Define | RegState::Implicit)
12307 .addReg(X86::ESP, RegState::Define | RegState::Implicit)
12308 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
12311 MI->eraseFromParent(); // The pseudo instruction is gone now.
12315 MachineBasicBlock *
12316 X86TargetLowering::EmitLoweredTLSCall(MachineInstr *MI,
12317 MachineBasicBlock *BB) const {
12318 // This is pretty easy. We're taking the value that we received from
12319 // our load from the relocation, sticking it in either RDI (x86-64)
12320 // or EAX and doing an indirect call. The return value will then
12321 // be in the normal return register.
12322 const X86InstrInfo *TII
12323 = static_cast<const X86InstrInfo*>(getTargetMachine().getInstrInfo());
12324 DebugLoc DL = MI->getDebugLoc();
12325 MachineFunction *F = BB->getParent();
12327 assert(Subtarget->isTargetDarwin() && "Darwin only instr emitted?");
12328 assert(MI->getOperand(3).isGlobal() && "This should be a global");
12330 if (Subtarget->is64Bit()) {
12331 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
12332 TII->get(X86::MOV64rm), X86::RDI)
12334 .addImm(0).addReg(0)
12335 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
12336 MI->getOperand(3).getTargetFlags())
12338 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL64m));
12339 addDirectMem(MIB, X86::RDI);
12340 } else if (getTargetMachine().getRelocationModel() != Reloc::PIC_) {
12341 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
12342 TII->get(X86::MOV32rm), X86::EAX)
12344 .addImm(0).addReg(0)
12345 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
12346 MI->getOperand(3).getTargetFlags())
12348 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
12349 addDirectMem(MIB, X86::EAX);
12351 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
12352 TII->get(X86::MOV32rm), X86::EAX)
12353 .addReg(TII->getGlobalBaseReg(F))
12354 .addImm(0).addReg(0)
12355 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
12356 MI->getOperand(3).getTargetFlags())
12358 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
12359 addDirectMem(MIB, X86::EAX);
12362 MI->eraseFromParent(); // The pseudo instruction is gone now.
12366 MachineBasicBlock *
12367 X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
12368 MachineBasicBlock *BB) const {
12369 switch (MI->getOpcode()) {
12370 default: assert(0 && "Unexpected instr type to insert");
12371 case X86::TAILJMPd64:
12372 case X86::TAILJMPr64:
12373 case X86::TAILJMPm64:
12374 assert(0 && "TAILJMP64 would not be touched here.");
12375 case X86::TCRETURNdi64:
12376 case X86::TCRETURNri64:
12377 case X86::TCRETURNmi64:
12378 // Defs of TCRETURNxx64 has Win64's callee-saved registers, as subset.
12379 // On AMD64, additional defs should be added before register allocation.
12380 if (!Subtarget->isTargetWin64()) {
12381 MI->addRegisterDefined(X86::RSI);
12382 MI->addRegisterDefined(X86::RDI);
12383 MI->addRegisterDefined(X86::XMM6);
12384 MI->addRegisterDefined(X86::XMM7);
12385 MI->addRegisterDefined(X86::XMM8);
12386 MI->addRegisterDefined(X86::XMM9);
12387 MI->addRegisterDefined(X86::XMM10);
12388 MI->addRegisterDefined(X86::XMM11);
12389 MI->addRegisterDefined(X86::XMM12);
12390 MI->addRegisterDefined(X86::XMM13);
12391 MI->addRegisterDefined(X86::XMM14);
12392 MI->addRegisterDefined(X86::XMM15);
12395 case X86::WIN_ALLOCA:
12396 return EmitLoweredWinAlloca(MI, BB);
12397 case X86::SEG_ALLOCA_32:
12398 return EmitLoweredSegAlloca(MI, BB, false);
12399 case X86::SEG_ALLOCA_64:
12400 return EmitLoweredSegAlloca(MI, BB, true);
12401 case X86::TLSCall_32:
12402 case X86::TLSCall_64:
12403 return EmitLoweredTLSCall(MI, BB);
12404 case X86::CMOV_GR8:
12405 case X86::CMOV_FR32:
12406 case X86::CMOV_FR64:
12407 case X86::CMOV_V4F32:
12408 case X86::CMOV_V2F64:
12409 case X86::CMOV_V2I64:
12410 case X86::CMOV_V8F32:
12411 case X86::CMOV_V4F64:
12412 case X86::CMOV_V4I64:
12413 case X86::CMOV_GR16:
12414 case X86::CMOV_GR32:
12415 case X86::CMOV_RFP32:
12416 case X86::CMOV_RFP64:
12417 case X86::CMOV_RFP80:
12418 return EmitLoweredSelect(MI, BB);
12420 case X86::FP32_TO_INT16_IN_MEM:
12421 case X86::FP32_TO_INT32_IN_MEM:
12422 case X86::FP32_TO_INT64_IN_MEM:
12423 case X86::FP64_TO_INT16_IN_MEM:
12424 case X86::FP64_TO_INT32_IN_MEM:
12425 case X86::FP64_TO_INT64_IN_MEM:
12426 case X86::FP80_TO_INT16_IN_MEM:
12427 case X86::FP80_TO_INT32_IN_MEM:
12428 case X86::FP80_TO_INT64_IN_MEM: {
12429 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
12430 DebugLoc DL = MI->getDebugLoc();
12432 // Change the floating point control register to use "round towards zero"
12433 // mode when truncating to an integer value.
12434 MachineFunction *F = BB->getParent();
12435 int CWFrameIdx = F->getFrameInfo()->CreateStackObject(2, 2, false);
12436 addFrameReference(BuildMI(*BB, MI, DL,
12437 TII->get(X86::FNSTCW16m)), CWFrameIdx);
12439 // Load the old value of the high byte of the control word...
12441 F->getRegInfo().createVirtualRegister(X86::GR16RegisterClass);
12442 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16rm), OldCW),
12445 // Set the high part to be round to zero...
12446 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mi)), CWFrameIdx)
12449 // Reload the modified control word now...
12450 addFrameReference(BuildMI(*BB, MI, DL,
12451 TII->get(X86::FLDCW16m)), CWFrameIdx);
12453 // Restore the memory image of control word to original value
12454 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mr)), CWFrameIdx)
12457 // Get the X86 opcode to use.
12459 switch (MI->getOpcode()) {
12460 default: llvm_unreachable("illegal opcode!");
12461 case X86::FP32_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m32; break;
12462 case X86::FP32_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m32; break;
12463 case X86::FP32_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m32; break;
12464 case X86::FP64_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m64; break;
12465 case X86::FP64_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m64; break;
12466 case X86::FP64_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m64; break;
12467 case X86::FP80_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m80; break;
12468 case X86::FP80_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m80; break;
12469 case X86::FP80_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m80; break;
12473 MachineOperand &Op = MI->getOperand(0);
12475 AM.BaseType = X86AddressMode::RegBase;
12476 AM.Base.Reg = Op.getReg();
12478 AM.BaseType = X86AddressMode::FrameIndexBase;
12479 AM.Base.FrameIndex = Op.getIndex();
12481 Op = MI->getOperand(1);
12483 AM.Scale = Op.getImm();
12484 Op = MI->getOperand(2);
12486 AM.IndexReg = Op.getImm();
12487 Op = MI->getOperand(3);
12488 if (Op.isGlobal()) {
12489 AM.GV = Op.getGlobal();
12491 AM.Disp = Op.getImm();
12493 addFullAddress(BuildMI(*BB, MI, DL, TII->get(Opc)), AM)
12494 .addReg(MI->getOperand(X86::AddrNumOperands).getReg());
12496 // Reload the original control word now.
12497 addFrameReference(BuildMI(*BB, MI, DL,
12498 TII->get(X86::FLDCW16m)), CWFrameIdx);
12500 MI->eraseFromParent(); // The pseudo instruction is gone now.
12503 // String/text processing lowering.
12504 case X86::PCMPISTRM128REG:
12505 case X86::VPCMPISTRM128REG:
12506 return EmitPCMP(MI, BB, 3, false /* in-mem */);
12507 case X86::PCMPISTRM128MEM:
12508 case X86::VPCMPISTRM128MEM:
12509 return EmitPCMP(MI, BB, 3, true /* in-mem */);
12510 case X86::PCMPESTRM128REG:
12511 case X86::VPCMPESTRM128REG:
12512 return EmitPCMP(MI, BB, 5, false /* in mem */);
12513 case X86::PCMPESTRM128MEM:
12514 case X86::VPCMPESTRM128MEM:
12515 return EmitPCMP(MI, BB, 5, true /* in mem */);
12517 // Thread synchronization.
12519 return EmitMonitor(MI, BB);
12521 return EmitMwait(MI, BB);
12523 // Atomic Lowering.
12524 case X86::ATOMAND32:
12525 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND32rr,
12526 X86::AND32ri, X86::MOV32rm,
12528 X86::NOT32r, X86::EAX,
12529 X86::GR32RegisterClass);
12530 case X86::ATOMOR32:
12531 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR32rr,
12532 X86::OR32ri, X86::MOV32rm,
12534 X86::NOT32r, X86::EAX,
12535 X86::GR32RegisterClass);
12536 case X86::ATOMXOR32:
12537 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR32rr,
12538 X86::XOR32ri, X86::MOV32rm,
12540 X86::NOT32r, X86::EAX,
12541 X86::GR32RegisterClass);
12542 case X86::ATOMNAND32:
12543 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND32rr,
12544 X86::AND32ri, X86::MOV32rm,
12546 X86::NOT32r, X86::EAX,
12547 X86::GR32RegisterClass, true);
12548 case X86::ATOMMIN32:
12549 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL32rr);
12550 case X86::ATOMMAX32:
12551 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG32rr);
12552 case X86::ATOMUMIN32:
12553 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB32rr);
12554 case X86::ATOMUMAX32:
12555 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA32rr);
12557 case X86::ATOMAND16:
12558 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND16rr,
12559 X86::AND16ri, X86::MOV16rm,
12561 X86::NOT16r, X86::AX,
12562 X86::GR16RegisterClass);
12563 case X86::ATOMOR16:
12564 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR16rr,
12565 X86::OR16ri, X86::MOV16rm,
12567 X86::NOT16r, X86::AX,
12568 X86::GR16RegisterClass);
12569 case X86::ATOMXOR16:
12570 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR16rr,
12571 X86::XOR16ri, X86::MOV16rm,
12573 X86::NOT16r, X86::AX,
12574 X86::GR16RegisterClass);
12575 case X86::ATOMNAND16:
12576 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND16rr,
12577 X86::AND16ri, X86::MOV16rm,
12579 X86::NOT16r, X86::AX,
12580 X86::GR16RegisterClass, true);
12581 case X86::ATOMMIN16:
12582 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL16rr);
12583 case X86::ATOMMAX16:
12584 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG16rr);
12585 case X86::ATOMUMIN16:
12586 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB16rr);
12587 case X86::ATOMUMAX16:
12588 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA16rr);
12590 case X86::ATOMAND8:
12591 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND8rr,
12592 X86::AND8ri, X86::MOV8rm,
12594 X86::NOT8r, X86::AL,
12595 X86::GR8RegisterClass);
12597 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR8rr,
12598 X86::OR8ri, X86::MOV8rm,
12600 X86::NOT8r, X86::AL,
12601 X86::GR8RegisterClass);
12602 case X86::ATOMXOR8:
12603 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR8rr,
12604 X86::XOR8ri, X86::MOV8rm,
12606 X86::NOT8r, X86::AL,
12607 X86::GR8RegisterClass);
12608 case X86::ATOMNAND8:
12609 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND8rr,
12610 X86::AND8ri, X86::MOV8rm,
12612 X86::NOT8r, X86::AL,
12613 X86::GR8RegisterClass, true);
12614 // FIXME: There are no CMOV8 instructions; MIN/MAX need some other way.
12615 // This group is for 64-bit host.
12616 case X86::ATOMAND64:
12617 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND64rr,
12618 X86::AND64ri32, X86::MOV64rm,
12620 X86::NOT64r, X86::RAX,
12621 X86::GR64RegisterClass);
12622 case X86::ATOMOR64:
12623 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR64rr,
12624 X86::OR64ri32, X86::MOV64rm,
12626 X86::NOT64r, X86::RAX,
12627 X86::GR64RegisterClass);
12628 case X86::ATOMXOR64:
12629 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR64rr,
12630 X86::XOR64ri32, X86::MOV64rm,
12632 X86::NOT64r, X86::RAX,
12633 X86::GR64RegisterClass);
12634 case X86::ATOMNAND64:
12635 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND64rr,
12636 X86::AND64ri32, X86::MOV64rm,
12638 X86::NOT64r, X86::RAX,
12639 X86::GR64RegisterClass, true);
12640 case X86::ATOMMIN64:
12641 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL64rr);
12642 case X86::ATOMMAX64:
12643 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG64rr);
12644 case X86::ATOMUMIN64:
12645 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB64rr);
12646 case X86::ATOMUMAX64:
12647 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA64rr);
12649 // This group does 64-bit operations on a 32-bit host.
12650 case X86::ATOMAND6432:
12651 return EmitAtomicBit6432WithCustomInserter(MI, BB,
12652 X86::AND32rr, X86::AND32rr,
12653 X86::AND32ri, X86::AND32ri,
12655 case X86::ATOMOR6432:
12656 return EmitAtomicBit6432WithCustomInserter(MI, BB,
12657 X86::OR32rr, X86::OR32rr,
12658 X86::OR32ri, X86::OR32ri,
12660 case X86::ATOMXOR6432:
12661 return EmitAtomicBit6432WithCustomInserter(MI, BB,
12662 X86::XOR32rr, X86::XOR32rr,
12663 X86::XOR32ri, X86::XOR32ri,
12665 case X86::ATOMNAND6432:
12666 return EmitAtomicBit6432WithCustomInserter(MI, BB,
12667 X86::AND32rr, X86::AND32rr,
12668 X86::AND32ri, X86::AND32ri,
12670 case X86::ATOMADD6432:
12671 return EmitAtomicBit6432WithCustomInserter(MI, BB,
12672 X86::ADD32rr, X86::ADC32rr,
12673 X86::ADD32ri, X86::ADC32ri,
12675 case X86::ATOMSUB6432:
12676 return EmitAtomicBit6432WithCustomInserter(MI, BB,
12677 X86::SUB32rr, X86::SBB32rr,
12678 X86::SUB32ri, X86::SBB32ri,
12680 case X86::ATOMSWAP6432:
12681 return EmitAtomicBit6432WithCustomInserter(MI, BB,
12682 X86::MOV32rr, X86::MOV32rr,
12683 X86::MOV32ri, X86::MOV32ri,
12685 case X86::VASTART_SAVE_XMM_REGS:
12686 return EmitVAStartSaveXMMRegsWithCustomInserter(MI, BB);
12688 case X86::VAARG_64:
12689 return EmitVAARG64WithCustomInserter(MI, BB);
12693 //===----------------------------------------------------------------------===//
12694 // X86 Optimization Hooks
12695 //===----------------------------------------------------------------------===//
12697 void X86TargetLowering::computeMaskedBitsForTargetNode(const SDValue Op,
12701 const SelectionDAG &DAG,
12702 unsigned Depth) const {
12703 unsigned Opc = Op.getOpcode();
12704 assert((Opc >= ISD::BUILTIN_OP_END ||
12705 Opc == ISD::INTRINSIC_WO_CHAIN ||
12706 Opc == ISD::INTRINSIC_W_CHAIN ||
12707 Opc == ISD::INTRINSIC_VOID) &&
12708 "Should use MaskedValueIsZero if you don't know whether Op"
12709 " is a target node!");
12711 KnownZero = KnownOne = APInt(Mask.getBitWidth(), 0); // Don't know anything.
12725 // These nodes' second result is a boolean.
12726 if (Op.getResNo() == 0)
12729 case X86ISD::SETCC:
12730 KnownZero |= APInt::getHighBitsSet(Mask.getBitWidth(),
12731 Mask.getBitWidth() - 1);
12733 case ISD::INTRINSIC_WO_CHAIN: {
12734 unsigned IntId = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
12735 unsigned NumLoBits = 0;
12738 case Intrinsic::x86_sse_movmsk_ps:
12739 case Intrinsic::x86_avx_movmsk_ps_256:
12740 case Intrinsic::x86_sse2_movmsk_pd:
12741 case Intrinsic::x86_avx_movmsk_pd_256:
12742 case Intrinsic::x86_mmx_pmovmskb:
12743 case Intrinsic::x86_sse2_pmovmskb_128:
12744 case Intrinsic::x86_avx2_pmovmskb: {
12745 // High bits of movmskp{s|d}, pmovmskb are known zero.
12747 case Intrinsic::x86_sse_movmsk_ps: NumLoBits = 4; break;
12748 case Intrinsic::x86_avx_movmsk_ps_256: NumLoBits = 8; break;
12749 case Intrinsic::x86_sse2_movmsk_pd: NumLoBits = 2; break;
12750 case Intrinsic::x86_avx_movmsk_pd_256: NumLoBits = 4; break;
12751 case Intrinsic::x86_mmx_pmovmskb: NumLoBits = 8; break;
12752 case Intrinsic::x86_sse2_pmovmskb_128: NumLoBits = 16; break;
12753 case Intrinsic::x86_avx2_pmovmskb: NumLoBits = 32; break;
12755 KnownZero = APInt::getHighBitsSet(Mask.getBitWidth(),
12756 Mask.getBitWidth() - NumLoBits);
12765 unsigned X86TargetLowering::ComputeNumSignBitsForTargetNode(SDValue Op,
12766 unsigned Depth) const {
12767 // SETCC_CARRY sets the dest to ~0 for true or 0 for false.
12768 if (Op.getOpcode() == X86ISD::SETCC_CARRY)
12769 return Op.getValueType().getScalarType().getSizeInBits();
12775 /// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the
12776 /// node is a GlobalAddress + offset.
12777 bool X86TargetLowering::isGAPlusOffset(SDNode *N,
12778 const GlobalValue* &GA,
12779 int64_t &Offset) const {
12780 if (N->getOpcode() == X86ISD::Wrapper) {
12781 if (isa<GlobalAddressSDNode>(N->getOperand(0))) {
12782 GA = cast<GlobalAddressSDNode>(N->getOperand(0))->getGlobal();
12783 Offset = cast<GlobalAddressSDNode>(N->getOperand(0))->getOffset();
12787 return TargetLowering::isGAPlusOffset(N, GA, Offset);
12790 /// isShuffleHigh128VectorInsertLow - Checks whether the shuffle node is the
12791 /// same as extracting the high 128-bit part of 256-bit vector and then
12792 /// inserting the result into the low part of a new 256-bit vector
12793 static bool isShuffleHigh128VectorInsertLow(ShuffleVectorSDNode *SVOp) {
12794 EVT VT = SVOp->getValueType(0);
12795 int NumElems = VT.getVectorNumElements();
12797 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
12798 for (int i = 0, j = NumElems/2; i < NumElems/2; ++i, ++j)
12799 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) ||
12800 SVOp->getMaskElt(j) >= 0)
12806 /// isShuffleLow128VectorInsertHigh - Checks whether the shuffle node is the
12807 /// same as extracting the low 128-bit part of 256-bit vector and then
12808 /// inserting the result into the high part of a new 256-bit vector
12809 static bool isShuffleLow128VectorInsertHigh(ShuffleVectorSDNode *SVOp) {
12810 EVT VT = SVOp->getValueType(0);
12811 int NumElems = VT.getVectorNumElements();
12813 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
12814 for (int i = NumElems/2, j = 0; i < NumElems; ++i, ++j)
12815 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) ||
12816 SVOp->getMaskElt(j) >= 0)
12822 /// PerformShuffleCombine256 - Performs shuffle combines for 256-bit vectors.
12823 static SDValue PerformShuffleCombine256(SDNode *N, SelectionDAG &DAG,
12824 TargetLowering::DAGCombinerInfo &DCI,
12825 const X86Subtarget* Subtarget) {
12826 DebugLoc dl = N->getDebugLoc();
12827 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
12828 SDValue V1 = SVOp->getOperand(0);
12829 SDValue V2 = SVOp->getOperand(1);
12830 EVT VT = SVOp->getValueType(0);
12831 int NumElems = VT.getVectorNumElements();
12833 if (V1.getOpcode() == ISD::CONCAT_VECTORS &&
12834 V2.getOpcode() == ISD::CONCAT_VECTORS) {
12838 // V UNDEF BUILD_VECTOR UNDEF
12840 // CONCAT_VECTOR CONCAT_VECTOR
12843 // RESULT: V + zero extended
12845 if (V2.getOperand(0).getOpcode() != ISD::BUILD_VECTOR ||
12846 V2.getOperand(1).getOpcode() != ISD::UNDEF ||
12847 V1.getOperand(1).getOpcode() != ISD::UNDEF)
12850 if (!ISD::isBuildVectorAllZeros(V2.getOperand(0).getNode()))
12853 // To match the shuffle mask, the first half of the mask should
12854 // be exactly the first vector, and all the rest a splat with the
12855 // first element of the second one.
12856 for (int i = 0; i < NumElems/2; ++i)
12857 if (!isUndefOrEqual(SVOp->getMaskElt(i), i) ||
12858 !isUndefOrEqual(SVOp->getMaskElt(i+NumElems/2), NumElems))
12861 // If V1 is coming from a vector load then just fold to a VZEXT_LOAD.
12862 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(V1.getOperand(0))) {
12863 SDVTList Tys = DAG.getVTList(MVT::v4i64, MVT::Other);
12864 SDValue Ops[] = { Ld->getChain(), Ld->getBasePtr() };
12866 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, dl, Tys, Ops, 2,
12868 Ld->getPointerInfo(),
12869 Ld->getAlignment(),
12870 false/*isVolatile*/, true/*ReadMem*/,
12871 false/*WriteMem*/);
12872 return DAG.getNode(ISD::BITCAST, dl, VT, ResNode);
12875 // Emit a zeroed vector and insert the desired subvector on its
12877 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
12878 SDValue InsV = Insert128BitVector(Zeros, V1.getOperand(0),
12879 DAG.getConstant(0, MVT::i32), DAG, dl);
12880 return DCI.CombineTo(N, InsV);
12883 //===--------------------------------------------------------------------===//
12884 // Combine some shuffles into subvector extracts and inserts:
12887 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
12888 if (isShuffleHigh128VectorInsertLow(SVOp)) {
12889 SDValue V = Extract128BitVector(V1, DAG.getConstant(NumElems/2, MVT::i32),
12891 SDValue InsV = Insert128BitVector(DAG.getNode(ISD::UNDEF, dl, VT),
12892 V, DAG.getConstant(0, MVT::i32), DAG, dl);
12893 return DCI.CombineTo(N, InsV);
12896 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
12897 if (isShuffleLow128VectorInsertHigh(SVOp)) {
12898 SDValue V = Extract128BitVector(V1, DAG.getConstant(0, MVT::i32), DAG, dl);
12899 SDValue InsV = Insert128BitVector(DAG.getNode(ISD::UNDEF, dl, VT),
12900 V, DAG.getConstant(NumElems/2, MVT::i32), DAG, dl);
12901 return DCI.CombineTo(N, InsV);
12907 /// PerformShuffleCombine - Performs several different shuffle combines.
12908 static SDValue PerformShuffleCombine(SDNode *N, SelectionDAG &DAG,
12909 TargetLowering::DAGCombinerInfo &DCI,
12910 const X86Subtarget *Subtarget) {
12911 DebugLoc dl = N->getDebugLoc();
12912 EVT VT = N->getValueType(0);
12914 // Don't create instructions with illegal types after legalize types has run.
12915 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
12916 if (!DCI.isBeforeLegalize() && !TLI.isTypeLegal(VT.getVectorElementType()))
12919 // Combine 256-bit vector shuffles. This is only profitable when in AVX mode
12920 if (Subtarget->hasAVX() && VT.getSizeInBits() == 256 &&
12921 N->getOpcode() == ISD::VECTOR_SHUFFLE)
12922 return PerformShuffleCombine256(N, DAG, DCI, Subtarget);
12924 // Only handle 128 wide vector from here on.
12925 if (VT.getSizeInBits() != 128)
12928 // Combine a vector_shuffle that is equal to build_vector load1, load2, load3,
12929 // load4, <0, 1, 2, 3> into a 128-bit load if the load addresses are
12930 // consecutive, non-overlapping, and in the right order.
12931 SmallVector<SDValue, 16> Elts;
12932 for (unsigned i = 0, e = VT.getVectorNumElements(); i != e; ++i)
12933 Elts.push_back(getShuffleScalarElt(N, i, DAG, 0));
12935 return EltsFromConsecutiveLoads(VT, Elts, dl, DAG);
12939 /// PerformTruncateCombine - Converts truncate operation to
12940 /// a sequence of vector shuffle operations.
12941 /// It is possible when we truncate 256-bit vector to 128-bit vector
12943 SDValue X86TargetLowering::PerformTruncateCombine(SDNode *N, SelectionDAG &DAG,
12944 DAGCombinerInfo &DCI) const {
12945 if (!DCI.isBeforeLegalizeOps())
12948 if (!Subtarget->hasAVX()) return SDValue();
12950 EVT VT = N->getValueType(0);
12951 SDValue Op = N->getOperand(0);
12952 EVT OpVT = Op.getValueType();
12953 DebugLoc dl = N->getDebugLoc();
12955 if ((VT == MVT::v4i32) && (OpVT == MVT::v4i64)) {
12957 SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v2i64, Op,
12958 DAG.getIntPtrConstant(0));
12960 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v2i64, Op,
12961 DAG.getIntPtrConstant(2));
12963 OpLo = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, OpLo);
12964 OpHi = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, OpHi);
12967 int ShufMask1[] = {0, 2, 0, 0};
12969 OpLo = DAG.getVectorShuffle(VT, dl, OpLo, DAG.getUNDEF(VT),
12971 OpHi = DAG.getVectorShuffle(VT, dl, OpHi, DAG.getUNDEF(VT),
12975 int ShufMask2[] = {0, 1, 4, 5};
12977 return DAG.getVectorShuffle(VT, dl, OpLo, OpHi, ShufMask2);
12979 if ((VT == MVT::v8i16) && (OpVT == MVT::v8i32)) {
12981 SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i32, Op,
12982 DAG.getIntPtrConstant(0));
12984 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i32, Op,
12985 DAG.getIntPtrConstant(4));
12987 OpLo = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, OpLo);
12988 OpHi = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, OpHi);
12991 int ShufMask1[] = {0, 1, 4, 5, 8, 9, 12, 13,
12992 -1, -1, -1, -1, -1, -1, -1, -1};
12994 OpLo = DAG.getVectorShuffle(MVT::v16i8, dl, OpLo,
12995 DAG.getUNDEF(MVT::v16i8),
12997 OpHi = DAG.getVectorShuffle(MVT::v16i8, dl, OpHi,
12998 DAG.getUNDEF(MVT::v16i8),
13001 OpLo = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, OpLo);
13002 OpHi = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, OpHi);
13005 int ShufMask2[] = {0, 1, 4, 5};
13007 SDValue res = DAG.getVectorShuffle(MVT::v4i32, dl, OpLo, OpHi, ShufMask2);
13008 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, res);
13014 /// PerformEXTRACT_VECTOR_ELTCombine - Detect vector gather/scatter index
13015 /// generation and convert it from being a bunch of shuffles and extracts
13016 /// to a simple store and scalar loads to extract the elements.
13017 static SDValue PerformEXTRACT_VECTOR_ELTCombine(SDNode *N, SelectionDAG &DAG,
13018 const TargetLowering &TLI) {
13019 SDValue InputVector = N->getOperand(0);
13021 // Only operate on vectors of 4 elements, where the alternative shuffling
13022 // gets to be more expensive.
13023 if (InputVector.getValueType() != MVT::v4i32)
13026 // Check whether every use of InputVector is an EXTRACT_VECTOR_ELT with a
13027 // single use which is a sign-extend or zero-extend, and all elements are
13029 SmallVector<SDNode *, 4> Uses;
13030 unsigned ExtractedElements = 0;
13031 for (SDNode::use_iterator UI = InputVector.getNode()->use_begin(),
13032 UE = InputVector.getNode()->use_end(); UI != UE; ++UI) {
13033 if (UI.getUse().getResNo() != InputVector.getResNo())
13036 SDNode *Extract = *UI;
13037 if (Extract->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
13040 if (Extract->getValueType(0) != MVT::i32)
13042 if (!Extract->hasOneUse())
13044 if (Extract->use_begin()->getOpcode() != ISD::SIGN_EXTEND &&
13045 Extract->use_begin()->getOpcode() != ISD::ZERO_EXTEND)
13047 if (!isa<ConstantSDNode>(Extract->getOperand(1)))
13050 // Record which element was extracted.
13051 ExtractedElements |=
13052 1 << cast<ConstantSDNode>(Extract->getOperand(1))->getZExtValue();
13054 Uses.push_back(Extract);
13057 // If not all the elements were used, this may not be worthwhile.
13058 if (ExtractedElements != 15)
13061 // Ok, we've now decided to do the transformation.
13062 DebugLoc dl = InputVector.getDebugLoc();
13064 // Store the value to a temporary stack slot.
13065 SDValue StackPtr = DAG.CreateStackTemporary(InputVector.getValueType());
13066 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, InputVector, StackPtr,
13067 MachinePointerInfo(), false, false, 0);
13069 // Replace each use (extract) with a load of the appropriate element.
13070 for (SmallVectorImpl<SDNode *>::iterator UI = Uses.begin(),
13071 UE = Uses.end(); UI != UE; ++UI) {
13072 SDNode *Extract = *UI;
13074 // cOMpute the element's address.
13075 SDValue Idx = Extract->getOperand(1);
13077 InputVector.getValueType().getVectorElementType().getSizeInBits()/8;
13078 uint64_t Offset = EltSize * cast<ConstantSDNode>(Idx)->getZExtValue();
13079 SDValue OffsetVal = DAG.getConstant(Offset, TLI.getPointerTy());
13081 SDValue ScalarAddr = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(),
13082 StackPtr, OffsetVal);
13084 // Load the scalar.
13085 SDValue LoadScalar = DAG.getLoad(Extract->getValueType(0), dl, Ch,
13086 ScalarAddr, MachinePointerInfo(),
13087 false, false, false, 0);
13089 // Replace the exact with the load.
13090 DAG.ReplaceAllUsesOfValueWith(SDValue(Extract, 0), LoadScalar);
13093 // The replacement was made in place; don't return anything.
13097 /// PerformSELECTCombine - Do target-specific dag combines on SELECT and VSELECT
13099 static SDValue PerformSELECTCombine(SDNode *N, SelectionDAG &DAG,
13100 TargetLowering::DAGCombinerInfo &DCI,
13101 const X86Subtarget *Subtarget) {
13102 DebugLoc DL = N->getDebugLoc();
13103 SDValue Cond = N->getOperand(0);
13104 // Get the LHS/RHS of the select.
13105 SDValue LHS = N->getOperand(1);
13106 SDValue RHS = N->getOperand(2);
13107 EVT VT = LHS.getValueType();
13109 // If we have SSE[12] support, try to form min/max nodes. SSE min/max
13110 // instructions match the semantics of the common C idiom x<y?x:y but not
13111 // x<=y?x:y, because of how they handle negative zero (which can be
13112 // ignored in unsafe-math mode).
13113 if (Cond.getOpcode() == ISD::SETCC && VT.isFloatingPoint() &&
13114 VT != MVT::f80 && DAG.getTargetLoweringInfo().isTypeLegal(VT) &&
13115 (Subtarget->hasSSE2() ||
13116 (Subtarget->hasSSE1() && VT.getScalarType() == MVT::f32))) {
13117 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
13119 unsigned Opcode = 0;
13120 // Check for x CC y ? x : y.
13121 if (DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
13122 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
13126 // Converting this to a min would handle NaNs incorrectly, and swapping
13127 // the operands would cause it to handle comparisons between positive
13128 // and negative zero incorrectly.
13129 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
13130 if (!DAG.getTarget().Options.UnsafeFPMath &&
13131 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
13133 std::swap(LHS, RHS);
13135 Opcode = X86ISD::FMIN;
13138 // Converting this to a min would handle comparisons between positive
13139 // and negative zero incorrectly.
13140 if (!DAG.getTarget().Options.UnsafeFPMath &&
13141 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
13143 Opcode = X86ISD::FMIN;
13146 // Converting this to a min would handle both negative zeros and NaNs
13147 // incorrectly, but we can swap the operands to fix both.
13148 std::swap(LHS, RHS);
13152 Opcode = X86ISD::FMIN;
13156 // Converting this to a max would handle comparisons between positive
13157 // and negative zero incorrectly.
13158 if (!DAG.getTarget().Options.UnsafeFPMath &&
13159 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
13161 Opcode = X86ISD::FMAX;
13164 // Converting this to a max would handle NaNs incorrectly, and swapping
13165 // the operands would cause it to handle comparisons between positive
13166 // and negative zero incorrectly.
13167 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
13168 if (!DAG.getTarget().Options.UnsafeFPMath &&
13169 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
13171 std::swap(LHS, RHS);
13173 Opcode = X86ISD::FMAX;
13176 // Converting this to a max would handle both negative zeros and NaNs
13177 // incorrectly, but we can swap the operands to fix both.
13178 std::swap(LHS, RHS);
13182 Opcode = X86ISD::FMAX;
13185 // Check for x CC y ? y : x -- a min/max with reversed arms.
13186 } else if (DAG.isEqualTo(LHS, Cond.getOperand(1)) &&
13187 DAG.isEqualTo(RHS, Cond.getOperand(0))) {
13191 // Converting this to a min would handle comparisons between positive
13192 // and negative zero incorrectly, and swapping the operands would
13193 // cause it to handle NaNs incorrectly.
13194 if (!DAG.getTarget().Options.UnsafeFPMath &&
13195 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS))) {
13196 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
13198 std::swap(LHS, RHS);
13200 Opcode = X86ISD::FMIN;
13203 // Converting this to a min would handle NaNs incorrectly.
13204 if (!DAG.getTarget().Options.UnsafeFPMath &&
13205 (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)))
13207 Opcode = X86ISD::FMIN;
13210 // Converting this to a min would handle both negative zeros and NaNs
13211 // incorrectly, but we can swap the operands to fix both.
13212 std::swap(LHS, RHS);
13216 Opcode = X86ISD::FMIN;
13220 // Converting this to a max would handle NaNs incorrectly.
13221 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
13223 Opcode = X86ISD::FMAX;
13226 // Converting this to a max would handle comparisons between positive
13227 // and negative zero incorrectly, and swapping the operands would
13228 // cause it to handle NaNs incorrectly.
13229 if (!DAG.getTarget().Options.UnsafeFPMath &&
13230 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS)) {
13231 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
13233 std::swap(LHS, RHS);
13235 Opcode = X86ISD::FMAX;
13238 // Converting this to a max would handle both negative zeros and NaNs
13239 // incorrectly, but we can swap the operands to fix both.
13240 std::swap(LHS, RHS);
13244 Opcode = X86ISD::FMAX;
13250 return DAG.getNode(Opcode, DL, N->getValueType(0), LHS, RHS);
13253 // If this is a select between two integer constants, try to do some
13255 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(LHS)) {
13256 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(RHS))
13257 // Don't do this for crazy integer types.
13258 if (DAG.getTargetLoweringInfo().isTypeLegal(LHS.getValueType())) {
13259 // If this is efficiently invertible, canonicalize the LHSC/RHSC values
13260 // so that TrueC (the true value) is larger than FalseC.
13261 bool NeedsCondInvert = false;
13263 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue()) &&
13264 // Efficiently invertible.
13265 (Cond.getOpcode() == ISD::SETCC || // setcc -> invertible.
13266 (Cond.getOpcode() == ISD::XOR && // xor(X, C) -> invertible.
13267 isa<ConstantSDNode>(Cond.getOperand(1))))) {
13268 NeedsCondInvert = true;
13269 std::swap(TrueC, FalseC);
13272 // Optimize C ? 8 : 0 -> zext(C) << 3. Likewise for any pow2/0.
13273 if (FalseC->getAPIntValue() == 0 &&
13274 TrueC->getAPIntValue().isPowerOf2()) {
13275 if (NeedsCondInvert) // Invert the condition if needed.
13276 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
13277 DAG.getConstant(1, Cond.getValueType()));
13279 // Zero extend the condition if needed.
13280 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, LHS.getValueType(), Cond);
13282 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
13283 return DAG.getNode(ISD::SHL, DL, LHS.getValueType(), Cond,
13284 DAG.getConstant(ShAmt, MVT::i8));
13287 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst.
13288 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
13289 if (NeedsCondInvert) // Invert the condition if needed.
13290 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
13291 DAG.getConstant(1, Cond.getValueType()));
13293 // Zero extend the condition if needed.
13294 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
13295 FalseC->getValueType(0), Cond);
13296 return DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
13297 SDValue(FalseC, 0));
13300 // Optimize cases that will turn into an LEA instruction. This requires
13301 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
13302 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
13303 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
13304 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
13306 bool isFastMultiplier = false;
13308 switch ((unsigned char)Diff) {
13310 case 1: // result = add base, cond
13311 case 2: // result = lea base( , cond*2)
13312 case 3: // result = lea base(cond, cond*2)
13313 case 4: // result = lea base( , cond*4)
13314 case 5: // result = lea base(cond, cond*4)
13315 case 8: // result = lea base( , cond*8)
13316 case 9: // result = lea base(cond, cond*8)
13317 isFastMultiplier = true;
13322 if (isFastMultiplier) {
13323 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
13324 if (NeedsCondInvert) // Invert the condition if needed.
13325 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
13326 DAG.getConstant(1, Cond.getValueType()));
13328 // Zero extend the condition if needed.
13329 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
13331 // Scale the condition by the difference.
13333 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
13334 DAG.getConstant(Diff, Cond.getValueType()));
13336 // Add the base if non-zero.
13337 if (FalseC->getAPIntValue() != 0)
13338 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
13339 SDValue(FalseC, 0));
13346 // Canonicalize max and min:
13347 // (x > y) ? x : y -> (x >= y) ? x : y
13348 // (x < y) ? x : y -> (x <= y) ? x : y
13349 // This allows use of COND_S / COND_NS (see TranslateX86CC) which eliminates
13350 // the need for an extra compare
13351 // against zero. e.g.
13352 // (x - y) > 0 : (x - y) ? 0 -> (x - y) >= 0 : (x - y) ? 0
13354 // testl %edi, %edi
13356 // cmovgl %edi, %eax
13360 // cmovsl %eax, %edi
13361 if (N->getOpcode() == ISD::SELECT && Cond.getOpcode() == ISD::SETCC &&
13362 DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
13363 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
13364 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
13369 ISD::CondCode NewCC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGE;
13370 Cond = DAG.getSetCC(Cond.getDebugLoc(), Cond.getValueType(),
13371 Cond.getOperand(0), Cond.getOperand(1), NewCC);
13372 return DAG.getNode(ISD::SELECT, DL, VT, Cond, LHS, RHS);
13377 // If we know that this node is legal then we know that it is going to be
13378 // matched by one of the SSE/AVX BLEND instructions. These instructions only
13379 // depend on the highest bit in each word. Try to use SimplifyDemandedBits
13380 // to simplify previous instructions.
13381 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
13382 if (N->getOpcode() == ISD::VSELECT && DCI.isBeforeLegalizeOps() &&
13383 !DCI.isBeforeLegalize() &&
13384 TLI.isOperationLegal(ISD::VSELECT, VT)) {
13385 unsigned BitWidth = Cond.getValueType().getScalarType().getSizeInBits();
13386 assert(BitWidth >= 8 && BitWidth <= 64 && "Invalid mask size");
13387 APInt DemandedMask = APInt::getHighBitsSet(BitWidth, 1);
13389 APInt KnownZero, KnownOne;
13390 TargetLowering::TargetLoweringOpt TLO(DAG, DCI.isBeforeLegalize(),
13391 DCI.isBeforeLegalizeOps());
13392 if (TLO.ShrinkDemandedConstant(Cond, DemandedMask) ||
13393 TLI.SimplifyDemandedBits(Cond, DemandedMask, KnownZero, KnownOne, TLO))
13394 DCI.CommitTargetLoweringOpt(TLO);
13400 /// Optimize X86ISD::CMOV [LHS, RHS, CONDCODE (e.g. X86::COND_NE), CONDVAL]
13401 static SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG,
13402 TargetLowering::DAGCombinerInfo &DCI) {
13403 DebugLoc DL = N->getDebugLoc();
13405 // If the flag operand isn't dead, don't touch this CMOV.
13406 if (N->getNumValues() == 2 && !SDValue(N, 1).use_empty())
13409 SDValue FalseOp = N->getOperand(0);
13410 SDValue TrueOp = N->getOperand(1);
13411 X86::CondCode CC = (X86::CondCode)N->getConstantOperandVal(2);
13412 SDValue Cond = N->getOperand(3);
13413 if (CC == X86::COND_E || CC == X86::COND_NE) {
13414 switch (Cond.getOpcode()) {
13418 // If operand of BSR / BSF are proven never zero, then ZF cannot be set.
13419 if (DAG.isKnownNeverZero(Cond.getOperand(0)))
13420 return (CC == X86::COND_E) ? FalseOp : TrueOp;
13424 // If this is a select between two integer constants, try to do some
13425 // optimizations. Note that the operands are ordered the opposite of SELECT
13427 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(TrueOp)) {
13428 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(FalseOp)) {
13429 // Canonicalize the TrueC/FalseC values so that TrueC (the true value) is
13430 // larger than FalseC (the false value).
13431 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue())) {
13432 CC = X86::GetOppositeBranchCondition(CC);
13433 std::swap(TrueC, FalseC);
13436 // Optimize C ? 8 : 0 -> zext(setcc(C)) << 3. Likewise for any pow2/0.
13437 // This is efficient for any integer data type (including i8/i16) and
13439 if (FalseC->getAPIntValue() == 0 && TrueC->getAPIntValue().isPowerOf2()) {
13440 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
13441 DAG.getConstant(CC, MVT::i8), Cond);
13443 // Zero extend the condition if needed.
13444 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, TrueC->getValueType(0), Cond);
13446 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
13447 Cond = DAG.getNode(ISD::SHL, DL, Cond.getValueType(), Cond,
13448 DAG.getConstant(ShAmt, MVT::i8));
13449 if (N->getNumValues() == 2) // Dead flag value?
13450 return DCI.CombineTo(N, Cond, SDValue());
13454 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst. This is efficient
13455 // for any integer data type, including i8/i16.
13456 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
13457 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
13458 DAG.getConstant(CC, MVT::i8), Cond);
13460 // Zero extend the condition if needed.
13461 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
13462 FalseC->getValueType(0), Cond);
13463 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
13464 SDValue(FalseC, 0));
13466 if (N->getNumValues() == 2) // Dead flag value?
13467 return DCI.CombineTo(N, Cond, SDValue());
13471 // Optimize cases that will turn into an LEA instruction. This requires
13472 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
13473 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
13474 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
13475 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
13477 bool isFastMultiplier = false;
13479 switch ((unsigned char)Diff) {
13481 case 1: // result = add base, cond
13482 case 2: // result = lea base( , cond*2)
13483 case 3: // result = lea base(cond, cond*2)
13484 case 4: // result = lea base( , cond*4)
13485 case 5: // result = lea base(cond, cond*4)
13486 case 8: // result = lea base( , cond*8)
13487 case 9: // result = lea base(cond, cond*8)
13488 isFastMultiplier = true;
13493 if (isFastMultiplier) {
13494 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
13495 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
13496 DAG.getConstant(CC, MVT::i8), Cond);
13497 // Zero extend the condition if needed.
13498 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
13500 // Scale the condition by the difference.
13502 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
13503 DAG.getConstant(Diff, Cond.getValueType()));
13505 // Add the base if non-zero.
13506 if (FalseC->getAPIntValue() != 0)
13507 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
13508 SDValue(FalseC, 0));
13509 if (N->getNumValues() == 2) // Dead flag value?
13510 return DCI.CombineTo(N, Cond, SDValue());
13520 /// PerformMulCombine - Optimize a single multiply with constant into two
13521 /// in order to implement it with two cheaper instructions, e.g.
13522 /// LEA + SHL, LEA + LEA.
13523 static SDValue PerformMulCombine(SDNode *N, SelectionDAG &DAG,
13524 TargetLowering::DAGCombinerInfo &DCI) {
13525 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer())
13528 EVT VT = N->getValueType(0);
13529 if (VT != MVT::i64)
13532 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
13535 uint64_t MulAmt = C->getZExtValue();
13536 if (isPowerOf2_64(MulAmt) || MulAmt == 3 || MulAmt == 5 || MulAmt == 9)
13539 uint64_t MulAmt1 = 0;
13540 uint64_t MulAmt2 = 0;
13541 if ((MulAmt % 9) == 0) {
13543 MulAmt2 = MulAmt / 9;
13544 } else if ((MulAmt % 5) == 0) {
13546 MulAmt2 = MulAmt / 5;
13547 } else if ((MulAmt % 3) == 0) {
13549 MulAmt2 = MulAmt / 3;
13552 (isPowerOf2_64(MulAmt2) || MulAmt2 == 3 || MulAmt2 == 5 || MulAmt2 == 9)){
13553 DebugLoc DL = N->getDebugLoc();
13555 if (isPowerOf2_64(MulAmt2) &&
13556 !(N->hasOneUse() && N->use_begin()->getOpcode() == ISD::ADD))
13557 // If second multiplifer is pow2, issue it first. We want the multiply by
13558 // 3, 5, or 9 to be folded into the addressing mode unless the lone use
13560 std::swap(MulAmt1, MulAmt2);
13563 if (isPowerOf2_64(MulAmt1))
13564 NewMul = DAG.getNode(ISD::SHL, DL, VT, N->getOperand(0),
13565 DAG.getConstant(Log2_64(MulAmt1), MVT::i8));
13567 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, N->getOperand(0),
13568 DAG.getConstant(MulAmt1, VT));
13570 if (isPowerOf2_64(MulAmt2))
13571 NewMul = DAG.getNode(ISD::SHL, DL, VT, NewMul,
13572 DAG.getConstant(Log2_64(MulAmt2), MVT::i8));
13574 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, NewMul,
13575 DAG.getConstant(MulAmt2, VT));
13577 // Do not add new nodes to DAG combiner worklist.
13578 DCI.CombineTo(N, NewMul, false);
13583 static SDValue PerformSHLCombine(SDNode *N, SelectionDAG &DAG) {
13584 SDValue N0 = N->getOperand(0);
13585 SDValue N1 = N->getOperand(1);
13586 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
13587 EVT VT = N0.getValueType();
13589 // fold (shl (and (setcc_c), c1), c2) -> (and setcc_c, (c1 << c2))
13590 // since the result of setcc_c is all zero's or all ones.
13591 if (VT.isInteger() && !VT.isVector() &&
13592 N1C && N0.getOpcode() == ISD::AND &&
13593 N0.getOperand(1).getOpcode() == ISD::Constant) {
13594 SDValue N00 = N0.getOperand(0);
13595 if (N00.getOpcode() == X86ISD::SETCC_CARRY ||
13596 ((N00.getOpcode() == ISD::ANY_EXTEND ||
13597 N00.getOpcode() == ISD::ZERO_EXTEND) &&
13598 N00.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY)) {
13599 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
13600 APInt ShAmt = N1C->getAPIntValue();
13601 Mask = Mask.shl(ShAmt);
13603 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT,
13604 N00, DAG.getConstant(Mask, VT));
13609 // Hardware support for vector shifts is sparse which makes us scalarize the
13610 // vector operations in many cases. Also, on sandybridge ADD is faster than
13612 // (shl V, 1) -> add V,V
13613 if (isSplatVector(N1.getNode())) {
13614 assert(N0.getValueType().isVector() && "Invalid vector shift type");
13615 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1->getOperand(0));
13616 // We shift all of the values by one. In many cases we do not have
13617 // hardware support for this operation. This is better expressed as an ADD
13619 if (N1C && (1 == N1C->getZExtValue())) {
13620 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N0, N0);
13627 /// PerformShiftCombine - Transforms vector shift nodes to use vector shifts
13629 static SDValue PerformShiftCombine(SDNode* N, SelectionDAG &DAG,
13630 TargetLowering::DAGCombinerInfo &DCI,
13631 const X86Subtarget *Subtarget) {
13632 EVT VT = N->getValueType(0);
13633 if (N->getOpcode() == ISD::SHL) {
13634 SDValue V = PerformSHLCombine(N, DAG);
13635 if (V.getNode()) return V;
13638 // On X86 with SSE2 support, we can transform this to a vector shift if
13639 // all elements are shifted by the same amount. We can't do this in legalize
13640 // because the a constant vector is typically transformed to a constant pool
13641 // so we have no knowledge of the shift amount.
13642 if (!Subtarget->hasSSE2())
13645 if (VT != MVT::v2i64 && VT != MVT::v4i32 && VT != MVT::v8i16 &&
13646 (!Subtarget->hasAVX2() ||
13647 (VT != MVT::v4i64 && VT != MVT::v8i32 && VT != MVT::v16i16)))
13650 SDValue ShAmtOp = N->getOperand(1);
13651 EVT EltVT = VT.getVectorElementType();
13652 DebugLoc DL = N->getDebugLoc();
13653 SDValue BaseShAmt = SDValue();
13654 if (ShAmtOp.getOpcode() == ISD::BUILD_VECTOR) {
13655 unsigned NumElts = VT.getVectorNumElements();
13657 for (; i != NumElts; ++i) {
13658 SDValue Arg = ShAmtOp.getOperand(i);
13659 if (Arg.getOpcode() == ISD::UNDEF) continue;
13663 // Handle the case where the build_vector is all undef
13664 // FIXME: Should DAG allow this?
13668 for (; i != NumElts; ++i) {
13669 SDValue Arg = ShAmtOp.getOperand(i);
13670 if (Arg.getOpcode() == ISD::UNDEF) continue;
13671 if (Arg != BaseShAmt) {
13675 } else if (ShAmtOp.getOpcode() == ISD::VECTOR_SHUFFLE &&
13676 cast<ShuffleVectorSDNode>(ShAmtOp)->isSplat()) {
13677 SDValue InVec = ShAmtOp.getOperand(0);
13678 if (InVec.getOpcode() == ISD::BUILD_VECTOR) {
13679 unsigned NumElts = InVec.getValueType().getVectorNumElements();
13681 for (; i != NumElts; ++i) {
13682 SDValue Arg = InVec.getOperand(i);
13683 if (Arg.getOpcode() == ISD::UNDEF) continue;
13687 } else if (InVec.getOpcode() == ISD::INSERT_VECTOR_ELT) {
13688 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(InVec.getOperand(2))) {
13689 unsigned SplatIdx= cast<ShuffleVectorSDNode>(ShAmtOp)->getSplatIndex();
13690 if (C->getZExtValue() == SplatIdx)
13691 BaseShAmt = InVec.getOperand(1);
13694 if (BaseShAmt.getNode() == 0) {
13695 // Don't create instructions with illegal types after legalize
13697 if (!DAG.getTargetLoweringInfo().isTypeLegal(EltVT) &&
13698 !DCI.isBeforeLegalize())
13701 BaseShAmt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, EltVT, ShAmtOp,
13702 DAG.getIntPtrConstant(0));
13707 // The shift amount is an i32.
13708 if (EltVT.bitsGT(MVT::i32))
13709 BaseShAmt = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, BaseShAmt);
13710 else if (EltVT.bitsLT(MVT::i32))
13711 BaseShAmt = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i32, BaseShAmt);
13713 // The shift amount is identical so we can do a vector shift.
13714 SDValue ValOp = N->getOperand(0);
13715 switch (N->getOpcode()) {
13717 llvm_unreachable("Unknown shift opcode!");
13719 switch (VT.getSimpleVT().SimpleTy) {
13720 default: return SDValue();
13727 return getTargetVShiftNode(X86ISD::VSHLI, DL, VT, ValOp, BaseShAmt, DAG);
13730 switch (VT.getSimpleVT().SimpleTy) {
13731 default: return SDValue();
13736 return getTargetVShiftNode(X86ISD::VSRAI, DL, VT, ValOp, BaseShAmt, DAG);
13739 switch (VT.getSimpleVT().SimpleTy) {
13740 default: return SDValue();
13747 return getTargetVShiftNode(X86ISD::VSRLI, DL, VT, ValOp, BaseShAmt, DAG);
13753 // CMPEQCombine - Recognize the distinctive (AND (setcc ...) (setcc ..))
13754 // where both setccs reference the same FP CMP, and rewrite for CMPEQSS
13755 // and friends. Likewise for OR -> CMPNEQSS.
13756 static SDValue CMPEQCombine(SDNode *N, SelectionDAG &DAG,
13757 TargetLowering::DAGCombinerInfo &DCI,
13758 const X86Subtarget *Subtarget) {
13761 // SSE1 supports CMP{eq|ne}SS, and SSE2 added CMP{eq|ne}SD, but
13762 // we're requiring SSE2 for both.
13763 if (Subtarget->hasSSE2() && isAndOrOfSetCCs(SDValue(N, 0U), opcode)) {
13764 SDValue N0 = N->getOperand(0);
13765 SDValue N1 = N->getOperand(1);
13766 SDValue CMP0 = N0->getOperand(1);
13767 SDValue CMP1 = N1->getOperand(1);
13768 DebugLoc DL = N->getDebugLoc();
13770 // The SETCCs should both refer to the same CMP.
13771 if (CMP0.getOpcode() != X86ISD::CMP || CMP0 != CMP1)
13774 SDValue CMP00 = CMP0->getOperand(0);
13775 SDValue CMP01 = CMP0->getOperand(1);
13776 EVT VT = CMP00.getValueType();
13778 if (VT == MVT::f32 || VT == MVT::f64) {
13779 bool ExpectingFlags = false;
13780 // Check for any users that want flags:
13781 for (SDNode::use_iterator UI = N->use_begin(),
13783 !ExpectingFlags && UI != UE; ++UI)
13784 switch (UI->getOpcode()) {
13789 ExpectingFlags = true;
13791 case ISD::CopyToReg:
13792 case ISD::SIGN_EXTEND:
13793 case ISD::ZERO_EXTEND:
13794 case ISD::ANY_EXTEND:
13798 if (!ExpectingFlags) {
13799 enum X86::CondCode cc0 = (enum X86::CondCode)N0.getConstantOperandVal(0);
13800 enum X86::CondCode cc1 = (enum X86::CondCode)N1.getConstantOperandVal(0);
13802 if (cc1 == X86::COND_E || cc1 == X86::COND_NE) {
13803 X86::CondCode tmp = cc0;
13808 if ((cc0 == X86::COND_E && cc1 == X86::COND_NP) ||
13809 (cc0 == X86::COND_NE && cc1 == X86::COND_P)) {
13810 bool is64BitFP = (CMP00.getValueType() == MVT::f64);
13811 X86ISD::NodeType NTOperator = is64BitFP ?
13812 X86ISD::FSETCCsd : X86ISD::FSETCCss;
13813 // FIXME: need symbolic constants for these magic numbers.
13814 // See X86ATTInstPrinter.cpp:printSSECC().
13815 unsigned x86cc = (cc0 == X86::COND_E) ? 0 : 4;
13816 SDValue OnesOrZeroesF = DAG.getNode(NTOperator, DL, MVT::f32, CMP00, CMP01,
13817 DAG.getConstant(x86cc, MVT::i8));
13818 SDValue OnesOrZeroesI = DAG.getNode(ISD::BITCAST, DL, MVT::i32,
13820 SDValue ANDed = DAG.getNode(ISD::AND, DL, MVT::i32, OnesOrZeroesI,
13821 DAG.getConstant(1, MVT::i32));
13822 SDValue OneBitOfTruth = DAG.getNode(ISD::TRUNCATE, DL, MVT::i8, ANDed);
13823 return OneBitOfTruth;
13831 /// CanFoldXORWithAllOnes - Test whether the XOR operand is a AllOnes vector
13832 /// so it can be folded inside ANDNP.
13833 static bool CanFoldXORWithAllOnes(const SDNode *N) {
13834 EVT VT = N->getValueType(0);
13836 // Match direct AllOnes for 128 and 256-bit vectors
13837 if (ISD::isBuildVectorAllOnes(N))
13840 // Look through a bit convert.
13841 if (N->getOpcode() == ISD::BITCAST)
13842 N = N->getOperand(0).getNode();
13844 // Sometimes the operand may come from a insert_subvector building a 256-bit
13846 if (VT.getSizeInBits() == 256 &&
13847 N->getOpcode() == ISD::INSERT_SUBVECTOR) {
13848 SDValue V1 = N->getOperand(0);
13849 SDValue V2 = N->getOperand(1);
13851 if (V1.getOpcode() == ISD::INSERT_SUBVECTOR &&
13852 V1.getOperand(0).getOpcode() == ISD::UNDEF &&
13853 ISD::isBuildVectorAllOnes(V1.getOperand(1).getNode()) &&
13854 ISD::isBuildVectorAllOnes(V2.getNode()))
13861 static SDValue PerformAndCombine(SDNode *N, SelectionDAG &DAG,
13862 TargetLowering::DAGCombinerInfo &DCI,
13863 const X86Subtarget *Subtarget) {
13864 if (DCI.isBeforeLegalizeOps())
13867 SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget);
13871 EVT VT = N->getValueType(0);
13873 // Create ANDN, BLSI, and BLSR instructions
13874 // BLSI is X & (-X)
13875 // BLSR is X & (X-1)
13876 if (Subtarget->hasBMI() && (VT == MVT::i32 || VT == MVT::i64)) {
13877 SDValue N0 = N->getOperand(0);
13878 SDValue N1 = N->getOperand(1);
13879 DebugLoc DL = N->getDebugLoc();
13881 // Check LHS for not
13882 if (N0.getOpcode() == ISD::XOR && isAllOnes(N0.getOperand(1)))
13883 return DAG.getNode(X86ISD::ANDN, DL, VT, N0.getOperand(0), N1);
13884 // Check RHS for not
13885 if (N1.getOpcode() == ISD::XOR && isAllOnes(N1.getOperand(1)))
13886 return DAG.getNode(X86ISD::ANDN, DL, VT, N1.getOperand(0), N0);
13888 // Check LHS for neg
13889 if (N0.getOpcode() == ISD::SUB && N0.getOperand(1) == N1 &&
13890 isZero(N0.getOperand(0)))
13891 return DAG.getNode(X86ISD::BLSI, DL, VT, N1);
13893 // Check RHS for neg
13894 if (N1.getOpcode() == ISD::SUB && N1.getOperand(1) == N0 &&
13895 isZero(N1.getOperand(0)))
13896 return DAG.getNode(X86ISD::BLSI, DL, VT, N0);
13898 // Check LHS for X-1
13899 if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1 &&
13900 isAllOnes(N0.getOperand(1)))
13901 return DAG.getNode(X86ISD::BLSR, DL, VT, N1);
13903 // Check RHS for X-1
13904 if (N1.getOpcode() == ISD::ADD && N1.getOperand(0) == N0 &&
13905 isAllOnes(N1.getOperand(1)))
13906 return DAG.getNode(X86ISD::BLSR, DL, VT, N0);
13911 // Want to form ANDNP nodes:
13912 // 1) In the hopes of then easily combining them with OR and AND nodes
13913 // to form PBLEND/PSIGN.
13914 // 2) To match ANDN packed intrinsics
13915 if (VT != MVT::v2i64 && VT != MVT::v4i64)
13918 SDValue N0 = N->getOperand(0);
13919 SDValue N1 = N->getOperand(1);
13920 DebugLoc DL = N->getDebugLoc();
13922 // Check LHS for vnot
13923 if (N0.getOpcode() == ISD::XOR &&
13924 //ISD::isBuildVectorAllOnes(N0.getOperand(1).getNode()))
13925 CanFoldXORWithAllOnes(N0.getOperand(1).getNode()))
13926 return DAG.getNode(X86ISD::ANDNP, DL, VT, N0.getOperand(0), N1);
13928 // Check RHS for vnot
13929 if (N1.getOpcode() == ISD::XOR &&
13930 //ISD::isBuildVectorAllOnes(N1.getOperand(1).getNode()))
13931 CanFoldXORWithAllOnes(N1.getOperand(1).getNode()))
13932 return DAG.getNode(X86ISD::ANDNP, DL, VT, N1.getOperand(0), N0);
13937 static SDValue PerformOrCombine(SDNode *N, SelectionDAG &DAG,
13938 TargetLowering::DAGCombinerInfo &DCI,
13939 const X86Subtarget *Subtarget) {
13940 if (DCI.isBeforeLegalizeOps())
13943 SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget);
13947 EVT VT = N->getValueType(0);
13949 SDValue N0 = N->getOperand(0);
13950 SDValue N1 = N->getOperand(1);
13952 // look for psign/blend
13953 if (VT == MVT::v2i64 || VT == MVT::v4i64) {
13954 if (!Subtarget->hasSSSE3() ||
13955 (VT == MVT::v4i64 && !Subtarget->hasAVX2()))
13958 // Canonicalize pandn to RHS
13959 if (N0.getOpcode() == X86ISD::ANDNP)
13961 // or (and (m, y), (pandn m, x))
13962 if (N0.getOpcode() == ISD::AND && N1.getOpcode() == X86ISD::ANDNP) {
13963 SDValue Mask = N1.getOperand(0);
13964 SDValue X = N1.getOperand(1);
13966 if (N0.getOperand(0) == Mask)
13967 Y = N0.getOperand(1);
13968 if (N0.getOperand(1) == Mask)
13969 Y = N0.getOperand(0);
13971 // Check to see if the mask appeared in both the AND and ANDNP and
13975 // Validate that X, Y, and Mask are BIT_CONVERTS, and see through them.
13976 if (Mask.getOpcode() != ISD::BITCAST ||
13977 X.getOpcode() != ISD::BITCAST ||
13978 Y.getOpcode() != ISD::BITCAST)
13981 // Look through mask bitcast.
13982 Mask = Mask.getOperand(0);
13983 EVT MaskVT = Mask.getValueType();
13985 // Validate that the Mask operand is a vector sra node.
13986 // FIXME: what to do for bytes, since there is a psignb/pblendvb, but
13987 // there is no psrai.b
13988 if (Mask.getOpcode() != X86ISD::VSRAI)
13991 // Check that the SRA is all signbits.
13992 SDValue SraC = Mask.getOperand(1);
13993 unsigned SraAmt = cast<ConstantSDNode>(SraC)->getZExtValue();
13994 unsigned EltBits = MaskVT.getVectorElementType().getSizeInBits();
13995 if ((SraAmt + 1) != EltBits)
13998 DebugLoc DL = N->getDebugLoc();
14000 // Now we know we at least have a plendvb with the mask val. See if
14001 // we can form a psignb/w/d.
14002 // psign = x.type == y.type == mask.type && y = sub(0, x);
14003 X = X.getOperand(0);
14004 Y = Y.getOperand(0);
14005 if (Y.getOpcode() == ISD::SUB && Y.getOperand(1) == X &&
14006 ISD::isBuildVectorAllZeros(Y.getOperand(0).getNode()) &&
14007 X.getValueType() == MaskVT && Y.getValueType() == MaskVT) {
14008 assert((EltBits == 8 || EltBits == 16 || EltBits == 32) &&
14009 "Unsupported VT for PSIGN");
14010 Mask = DAG.getNode(X86ISD::PSIGN, DL, MaskVT, X, Mask.getOperand(0));
14011 return DAG.getNode(ISD::BITCAST, DL, VT, Mask);
14013 // PBLENDVB only available on SSE 4.1
14014 if (!Subtarget->hasSSE41())
14017 EVT BlendVT = (VT == MVT::v4i64) ? MVT::v32i8 : MVT::v16i8;
14019 X = DAG.getNode(ISD::BITCAST, DL, BlendVT, X);
14020 Y = DAG.getNode(ISD::BITCAST, DL, BlendVT, Y);
14021 Mask = DAG.getNode(ISD::BITCAST, DL, BlendVT, Mask);
14022 Mask = DAG.getNode(ISD::VSELECT, DL, BlendVT, Mask, Y, X);
14023 return DAG.getNode(ISD::BITCAST, DL, VT, Mask);
14027 if (VT != MVT::i16 && VT != MVT::i32 && VT != MVT::i64)
14030 // fold (or (x << c) | (y >> (64 - c))) ==> (shld64 x, y, c)
14031 if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL)
14033 if (N0.getOpcode() != ISD::SHL || N1.getOpcode() != ISD::SRL)
14035 if (!N0.hasOneUse() || !N1.hasOneUse())
14038 SDValue ShAmt0 = N0.getOperand(1);
14039 if (ShAmt0.getValueType() != MVT::i8)
14041 SDValue ShAmt1 = N1.getOperand(1);
14042 if (ShAmt1.getValueType() != MVT::i8)
14044 if (ShAmt0.getOpcode() == ISD::TRUNCATE)
14045 ShAmt0 = ShAmt0.getOperand(0);
14046 if (ShAmt1.getOpcode() == ISD::TRUNCATE)
14047 ShAmt1 = ShAmt1.getOperand(0);
14049 DebugLoc DL = N->getDebugLoc();
14050 unsigned Opc = X86ISD::SHLD;
14051 SDValue Op0 = N0.getOperand(0);
14052 SDValue Op1 = N1.getOperand(0);
14053 if (ShAmt0.getOpcode() == ISD::SUB) {
14054 Opc = X86ISD::SHRD;
14055 std::swap(Op0, Op1);
14056 std::swap(ShAmt0, ShAmt1);
14059 unsigned Bits = VT.getSizeInBits();
14060 if (ShAmt1.getOpcode() == ISD::SUB) {
14061 SDValue Sum = ShAmt1.getOperand(0);
14062 if (ConstantSDNode *SumC = dyn_cast<ConstantSDNode>(Sum)) {
14063 SDValue ShAmt1Op1 = ShAmt1.getOperand(1);
14064 if (ShAmt1Op1.getNode()->getOpcode() == ISD::TRUNCATE)
14065 ShAmt1Op1 = ShAmt1Op1.getOperand(0);
14066 if (SumC->getSExtValue() == Bits && ShAmt1Op1 == ShAmt0)
14067 return DAG.getNode(Opc, DL, VT,
14069 DAG.getNode(ISD::TRUNCATE, DL,
14072 } else if (ConstantSDNode *ShAmt1C = dyn_cast<ConstantSDNode>(ShAmt1)) {
14073 ConstantSDNode *ShAmt0C = dyn_cast<ConstantSDNode>(ShAmt0);
14075 ShAmt0C->getSExtValue() + ShAmt1C->getSExtValue() == Bits)
14076 return DAG.getNode(Opc, DL, VT,
14077 N0.getOperand(0), N1.getOperand(0),
14078 DAG.getNode(ISD::TRUNCATE, DL,
14085 // PerformXorCombine - Attempts to turn XOR nodes into BLSMSK nodes
14086 static SDValue PerformXorCombine(SDNode *N, SelectionDAG &DAG,
14087 TargetLowering::DAGCombinerInfo &DCI,
14088 const X86Subtarget *Subtarget) {
14089 if (DCI.isBeforeLegalizeOps())
14092 EVT VT = N->getValueType(0);
14094 if (VT != MVT::i32 && VT != MVT::i64)
14097 assert(Subtarget->hasBMI() && "Creating BLSMSK requires BMI instructions");
14099 // Create BLSMSK instructions by finding X ^ (X-1)
14100 SDValue N0 = N->getOperand(0);
14101 SDValue N1 = N->getOperand(1);
14102 DebugLoc DL = N->getDebugLoc();
14104 if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1 &&
14105 isAllOnes(N0.getOperand(1)))
14106 return DAG.getNode(X86ISD::BLSMSK, DL, VT, N1);
14108 if (N1.getOpcode() == ISD::ADD && N1.getOperand(0) == N0 &&
14109 isAllOnes(N1.getOperand(1)))
14110 return DAG.getNode(X86ISD::BLSMSK, DL, VT, N0);
14115 /// PerformLOADCombine - Do target-specific dag combines on LOAD nodes.
14116 static SDValue PerformLOADCombine(SDNode *N, SelectionDAG &DAG,
14117 const X86Subtarget *Subtarget) {
14118 LoadSDNode *Ld = cast<LoadSDNode>(N);
14119 EVT RegVT = Ld->getValueType(0);
14120 EVT MemVT = Ld->getMemoryVT();
14121 DebugLoc dl = Ld->getDebugLoc();
14122 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
14124 ISD::LoadExtType Ext = Ld->getExtensionType();
14126 // If this is a vector EXT Load then attempt to optimize it using a
14127 // shuffle. We need SSE4 for the shuffles.
14128 // TODO: It is possible to support ZExt by zeroing the undef values
14129 // during the shuffle phase or after the shuffle.
14130 if (RegVT.isVector() && RegVT.isInteger() &&
14131 Ext == ISD::EXTLOAD && Subtarget->hasSSE41()) {
14132 assert(MemVT != RegVT && "Cannot extend to the same type");
14133 assert(MemVT.isVector() && "Must load a vector from memory");
14135 unsigned NumElems = RegVT.getVectorNumElements();
14136 unsigned RegSz = RegVT.getSizeInBits();
14137 unsigned MemSz = MemVT.getSizeInBits();
14138 assert(RegSz > MemSz && "Register size must be greater than the mem size");
14139 // All sizes must be a power of two
14140 if (!isPowerOf2_32(RegSz * MemSz * NumElems)) return SDValue();
14142 // Attempt to load the original value using a single load op.
14143 // Find a scalar type which is equal to the loaded word size.
14144 MVT SclrLoadTy = MVT::i8;
14145 for (unsigned tp = MVT::FIRST_INTEGER_VALUETYPE;
14146 tp < MVT::LAST_INTEGER_VALUETYPE; ++tp) {
14147 MVT Tp = (MVT::SimpleValueType)tp;
14148 if (TLI.isTypeLegal(Tp) && Tp.getSizeInBits() == MemSz) {
14154 // Proceed if a load word is found.
14155 if (SclrLoadTy.getSizeInBits() != MemSz) return SDValue();
14157 EVT LoadUnitVecVT = EVT::getVectorVT(*DAG.getContext(), SclrLoadTy,
14158 RegSz/SclrLoadTy.getSizeInBits());
14160 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(), MemVT.getScalarType(),
14161 RegSz/MemVT.getScalarType().getSizeInBits());
14162 // Can't shuffle using an illegal type.
14163 if (!TLI.isTypeLegal(WideVecVT)) return SDValue();
14165 // Perform a single load.
14166 SDValue ScalarLoad = DAG.getLoad(SclrLoadTy, dl, Ld->getChain(),
14168 Ld->getPointerInfo(), Ld->isVolatile(),
14169 Ld->isNonTemporal(), Ld->isInvariant(),
14170 Ld->getAlignment());
14172 // Insert the word loaded into a vector.
14173 SDValue ScalarInVector = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
14174 LoadUnitVecVT, ScalarLoad);
14176 // Bitcast the loaded value to a vector of the original element type, in
14177 // the size of the target vector type.
14178 SDValue SlicedVec = DAG.getNode(ISD::BITCAST, dl, WideVecVT,
14180 unsigned SizeRatio = RegSz/MemSz;
14182 // Redistribute the loaded elements into the different locations.
14183 SmallVector<int, 8> ShuffleVec(NumElems * SizeRatio, -1);
14184 for (unsigned i = 0; i < NumElems; i++) ShuffleVec[i*SizeRatio] = i;
14186 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, SlicedVec,
14187 DAG.getUNDEF(SlicedVec.getValueType()),
14188 ShuffleVec.data());
14190 // Bitcast to the requested type.
14191 Shuff = DAG.getNode(ISD::BITCAST, dl, RegVT, Shuff);
14192 // Replace the original load with the new sequence
14193 // and return the new chain.
14194 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Shuff);
14195 return SDValue(ScalarLoad.getNode(), 1);
14201 /// PerformSTORECombine - Do target-specific dag combines on STORE nodes.
14202 static SDValue PerformSTORECombine(SDNode *N, SelectionDAG &DAG,
14203 const X86Subtarget *Subtarget) {
14204 StoreSDNode *St = cast<StoreSDNode>(N);
14205 EVT VT = St->getValue().getValueType();
14206 EVT StVT = St->getMemoryVT();
14207 DebugLoc dl = St->getDebugLoc();
14208 SDValue StoredVal = St->getOperand(1);
14209 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
14211 // If we are saving a concatenation of two XMM registers, perform two stores.
14212 // This is better in Sandy Bridge cause one 256-bit mem op is done via two
14213 // 128-bit ones. If in the future the cost becomes only one memory access the
14214 // first version would be better.
14215 if (VT.getSizeInBits() == 256 &&
14216 StoredVal.getNode()->getOpcode() == ISD::CONCAT_VECTORS &&
14217 StoredVal.getNumOperands() == 2) {
14219 SDValue Value0 = StoredVal.getOperand(0);
14220 SDValue Value1 = StoredVal.getOperand(1);
14222 SDValue Stride = DAG.getConstant(16, TLI.getPointerTy());
14223 SDValue Ptr0 = St->getBasePtr();
14224 SDValue Ptr1 = DAG.getNode(ISD::ADD, dl, Ptr0.getValueType(), Ptr0, Stride);
14226 SDValue Ch0 = DAG.getStore(St->getChain(), dl, Value0, Ptr0,
14227 St->getPointerInfo(), St->isVolatile(),
14228 St->isNonTemporal(), St->getAlignment());
14229 SDValue Ch1 = DAG.getStore(St->getChain(), dl, Value1, Ptr1,
14230 St->getPointerInfo(), St->isVolatile(),
14231 St->isNonTemporal(), St->getAlignment());
14232 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Ch0, Ch1);
14235 // Optimize trunc store (of multiple scalars) to shuffle and store.
14236 // First, pack all of the elements in one place. Next, store to memory
14237 // in fewer chunks.
14238 if (St->isTruncatingStore() && VT.isVector()) {
14239 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
14240 unsigned NumElems = VT.getVectorNumElements();
14241 assert(StVT != VT && "Cannot truncate to the same type");
14242 unsigned FromSz = VT.getVectorElementType().getSizeInBits();
14243 unsigned ToSz = StVT.getVectorElementType().getSizeInBits();
14245 // From, To sizes and ElemCount must be pow of two
14246 if (!isPowerOf2_32(NumElems * FromSz * ToSz)) return SDValue();
14247 // We are going to use the original vector elt for storing.
14248 // Accumulated smaller vector elements must be a multiple of the store size.
14249 if (0 != (NumElems * FromSz) % ToSz) return SDValue();
14251 unsigned SizeRatio = FromSz / ToSz;
14253 assert(SizeRatio * NumElems * ToSz == VT.getSizeInBits());
14255 // Create a type on which we perform the shuffle
14256 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(),
14257 StVT.getScalarType(), NumElems*SizeRatio);
14259 assert(WideVecVT.getSizeInBits() == VT.getSizeInBits());
14261 SDValue WideVec = DAG.getNode(ISD::BITCAST, dl, WideVecVT, St->getValue());
14262 SmallVector<int, 8> ShuffleVec(NumElems * SizeRatio, -1);
14263 for (unsigned i = 0; i < NumElems; i++ ) ShuffleVec[i] = i * SizeRatio;
14265 // Can't shuffle using an illegal type
14266 if (!TLI.isTypeLegal(WideVecVT)) return SDValue();
14268 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, WideVec,
14269 DAG.getUNDEF(WideVec.getValueType()),
14270 ShuffleVec.data());
14271 // At this point all of the data is stored at the bottom of the
14272 // register. We now need to save it to mem.
14274 // Find the largest store unit
14275 MVT StoreType = MVT::i8;
14276 for (unsigned tp = MVT::FIRST_INTEGER_VALUETYPE;
14277 tp < MVT::LAST_INTEGER_VALUETYPE; ++tp) {
14278 MVT Tp = (MVT::SimpleValueType)tp;
14279 if (TLI.isTypeLegal(Tp) && StoreType.getSizeInBits() < NumElems * ToSz)
14283 // Bitcast the original vector into a vector of store-size units
14284 EVT StoreVecVT = EVT::getVectorVT(*DAG.getContext(),
14285 StoreType, VT.getSizeInBits()/EVT(StoreType).getSizeInBits());
14286 assert(StoreVecVT.getSizeInBits() == VT.getSizeInBits());
14287 SDValue ShuffWide = DAG.getNode(ISD::BITCAST, dl, StoreVecVT, Shuff);
14288 SmallVector<SDValue, 8> Chains;
14289 SDValue Increment = DAG.getConstant(StoreType.getSizeInBits()/8,
14290 TLI.getPointerTy());
14291 SDValue Ptr = St->getBasePtr();
14293 // Perform one or more big stores into memory.
14294 for (unsigned i = 0; i < (ToSz*NumElems)/StoreType.getSizeInBits() ; i++) {
14295 SDValue SubVec = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
14296 StoreType, ShuffWide,
14297 DAG.getIntPtrConstant(i));
14298 SDValue Ch = DAG.getStore(St->getChain(), dl, SubVec, Ptr,
14299 St->getPointerInfo(), St->isVolatile(),
14300 St->isNonTemporal(), St->getAlignment());
14301 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
14302 Chains.push_back(Ch);
14305 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Chains[0],
14310 // Turn load->store of MMX types into GPR load/stores. This avoids clobbering
14311 // the FP state in cases where an emms may be missing.
14312 // A preferable solution to the general problem is to figure out the right
14313 // places to insert EMMS. This qualifies as a quick hack.
14315 // Similarly, turn load->store of i64 into double load/stores in 32-bit mode.
14316 if (VT.getSizeInBits() != 64)
14319 const Function *F = DAG.getMachineFunction().getFunction();
14320 bool NoImplicitFloatOps = F->hasFnAttr(Attribute::NoImplicitFloat);
14321 bool F64IsLegal = !DAG.getTarget().Options.UseSoftFloat && !NoImplicitFloatOps
14322 && Subtarget->hasSSE2();
14323 if ((VT.isVector() ||
14324 (VT == MVT::i64 && F64IsLegal && !Subtarget->is64Bit())) &&
14325 isa<LoadSDNode>(St->getValue()) &&
14326 !cast<LoadSDNode>(St->getValue())->isVolatile() &&
14327 St->getChain().hasOneUse() && !St->isVolatile()) {
14328 SDNode* LdVal = St->getValue().getNode();
14329 LoadSDNode *Ld = 0;
14330 int TokenFactorIndex = -1;
14331 SmallVector<SDValue, 8> Ops;
14332 SDNode* ChainVal = St->getChain().getNode();
14333 // Must be a store of a load. We currently handle two cases: the load
14334 // is a direct child, and it's under an intervening TokenFactor. It is
14335 // possible to dig deeper under nested TokenFactors.
14336 if (ChainVal == LdVal)
14337 Ld = cast<LoadSDNode>(St->getChain());
14338 else if (St->getValue().hasOneUse() &&
14339 ChainVal->getOpcode() == ISD::TokenFactor) {
14340 for (unsigned i = 0, e = ChainVal->getNumOperands(); i != e; ++i) {
14341 if (ChainVal->getOperand(i).getNode() == LdVal) {
14342 TokenFactorIndex = i;
14343 Ld = cast<LoadSDNode>(St->getValue());
14345 Ops.push_back(ChainVal->getOperand(i));
14349 if (!Ld || !ISD::isNormalLoad(Ld))
14352 // If this is not the MMX case, i.e. we are just turning i64 load/store
14353 // into f64 load/store, avoid the transformation if there are multiple
14354 // uses of the loaded value.
14355 if (!VT.isVector() && !Ld->hasNUsesOfValue(1, 0))
14358 DebugLoc LdDL = Ld->getDebugLoc();
14359 DebugLoc StDL = N->getDebugLoc();
14360 // If we are a 64-bit capable x86, lower to a single movq load/store pair.
14361 // Otherwise, if it's legal to use f64 SSE instructions, use f64 load/store
14363 if (Subtarget->is64Bit() || F64IsLegal) {
14364 EVT LdVT = Subtarget->is64Bit() ? MVT::i64 : MVT::f64;
14365 SDValue NewLd = DAG.getLoad(LdVT, LdDL, Ld->getChain(), Ld->getBasePtr(),
14366 Ld->getPointerInfo(), Ld->isVolatile(),
14367 Ld->isNonTemporal(), Ld->isInvariant(),
14368 Ld->getAlignment());
14369 SDValue NewChain = NewLd.getValue(1);
14370 if (TokenFactorIndex != -1) {
14371 Ops.push_back(NewChain);
14372 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, &Ops[0],
14375 return DAG.getStore(NewChain, StDL, NewLd, St->getBasePtr(),
14376 St->getPointerInfo(),
14377 St->isVolatile(), St->isNonTemporal(),
14378 St->getAlignment());
14381 // Otherwise, lower to two pairs of 32-bit loads / stores.
14382 SDValue LoAddr = Ld->getBasePtr();
14383 SDValue HiAddr = DAG.getNode(ISD::ADD, LdDL, MVT::i32, LoAddr,
14384 DAG.getConstant(4, MVT::i32));
14386 SDValue LoLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), LoAddr,
14387 Ld->getPointerInfo(),
14388 Ld->isVolatile(), Ld->isNonTemporal(),
14389 Ld->isInvariant(), Ld->getAlignment());
14390 SDValue HiLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), HiAddr,
14391 Ld->getPointerInfo().getWithOffset(4),
14392 Ld->isVolatile(), Ld->isNonTemporal(),
14394 MinAlign(Ld->getAlignment(), 4));
14396 SDValue NewChain = LoLd.getValue(1);
14397 if (TokenFactorIndex != -1) {
14398 Ops.push_back(LoLd);
14399 Ops.push_back(HiLd);
14400 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, &Ops[0],
14404 LoAddr = St->getBasePtr();
14405 HiAddr = DAG.getNode(ISD::ADD, StDL, MVT::i32, LoAddr,
14406 DAG.getConstant(4, MVT::i32));
14408 SDValue LoSt = DAG.getStore(NewChain, StDL, LoLd, LoAddr,
14409 St->getPointerInfo(),
14410 St->isVolatile(), St->isNonTemporal(),
14411 St->getAlignment());
14412 SDValue HiSt = DAG.getStore(NewChain, StDL, HiLd, HiAddr,
14413 St->getPointerInfo().getWithOffset(4),
14415 St->isNonTemporal(),
14416 MinAlign(St->getAlignment(), 4));
14417 return DAG.getNode(ISD::TokenFactor, StDL, MVT::Other, LoSt, HiSt);
14422 /// isHorizontalBinOp - Return 'true' if this vector operation is "horizontal"
14423 /// and return the operands for the horizontal operation in LHS and RHS. A
14424 /// horizontal operation performs the binary operation on successive elements
14425 /// of its first operand, then on successive elements of its second operand,
14426 /// returning the resulting values in a vector. For example, if
14427 /// A = < float a0, float a1, float a2, float a3 >
14429 /// B = < float b0, float b1, float b2, float b3 >
14430 /// then the result of doing a horizontal operation on A and B is
14431 /// A horizontal-op B = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >.
14432 /// In short, LHS and RHS are inspected to see if LHS op RHS is of the form
14433 /// A horizontal-op B, for some already available A and B, and if so then LHS is
14434 /// set to A, RHS to B, and the routine returns 'true'.
14435 /// Note that the binary operation should have the property that if one of the
14436 /// operands is UNDEF then the result is UNDEF.
14437 static bool isHorizontalBinOp(SDValue &LHS, SDValue &RHS, bool IsCommutative) {
14438 // Look for the following pattern: if
14439 // A = < float a0, float a1, float a2, float a3 >
14440 // B = < float b0, float b1, float b2, float b3 >
14442 // LHS = VECTOR_SHUFFLE A, B, <0, 2, 4, 6>
14443 // RHS = VECTOR_SHUFFLE A, B, <1, 3, 5, 7>
14444 // then LHS op RHS = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >
14445 // which is A horizontal-op B.
14447 // At least one of the operands should be a vector shuffle.
14448 if (LHS.getOpcode() != ISD::VECTOR_SHUFFLE &&
14449 RHS.getOpcode() != ISD::VECTOR_SHUFFLE)
14452 EVT VT = LHS.getValueType();
14454 assert((VT.is128BitVector() || VT.is256BitVector()) &&
14455 "Unsupported vector type for horizontal add/sub");
14457 // Handle 128 and 256-bit vector lengths. AVX defines horizontal add/sub to
14458 // operate independently on 128-bit lanes.
14459 unsigned NumElts = VT.getVectorNumElements();
14460 unsigned NumLanes = VT.getSizeInBits()/128;
14461 unsigned NumLaneElts = NumElts / NumLanes;
14462 assert((NumLaneElts % 2 == 0) &&
14463 "Vector type should have an even number of elements in each lane");
14464 unsigned HalfLaneElts = NumLaneElts/2;
14466 // View LHS in the form
14467 // LHS = VECTOR_SHUFFLE A, B, LMask
14468 // If LHS is not a shuffle then pretend it is the shuffle
14469 // LHS = VECTOR_SHUFFLE LHS, undef, <0, 1, ..., N-1>
14470 // NOTE: in what follows a default initialized SDValue represents an UNDEF of
14473 SmallVector<int, 16> LMask(NumElts);
14474 if (LHS.getOpcode() == ISD::VECTOR_SHUFFLE) {
14475 if (LHS.getOperand(0).getOpcode() != ISD::UNDEF)
14476 A = LHS.getOperand(0);
14477 if (LHS.getOperand(1).getOpcode() != ISD::UNDEF)
14478 B = LHS.getOperand(1);
14479 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(LHS.getNode())->getMask();
14480 std::copy(Mask.begin(), Mask.end(), LMask.begin());
14482 if (LHS.getOpcode() != ISD::UNDEF)
14484 for (unsigned i = 0; i != NumElts; ++i)
14488 // Likewise, view RHS in the form
14489 // RHS = VECTOR_SHUFFLE C, D, RMask
14491 SmallVector<int, 16> RMask(NumElts);
14492 if (RHS.getOpcode() == ISD::VECTOR_SHUFFLE) {
14493 if (RHS.getOperand(0).getOpcode() != ISD::UNDEF)
14494 C = RHS.getOperand(0);
14495 if (RHS.getOperand(1).getOpcode() != ISD::UNDEF)
14496 D = RHS.getOperand(1);
14497 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(RHS.getNode())->getMask();
14498 std::copy(Mask.begin(), Mask.end(), RMask.begin());
14500 if (RHS.getOpcode() != ISD::UNDEF)
14502 for (unsigned i = 0; i != NumElts; ++i)
14506 // Check that the shuffles are both shuffling the same vectors.
14507 if (!(A == C && B == D) && !(A == D && B == C))
14510 // If everything is UNDEF then bail out: it would be better to fold to UNDEF.
14511 if (!A.getNode() && !B.getNode())
14514 // If A and B occur in reverse order in RHS, then "swap" them (which means
14515 // rewriting the mask).
14517 CommuteVectorShuffleMask(RMask, NumElts);
14519 // At this point LHS and RHS are equivalent to
14520 // LHS = VECTOR_SHUFFLE A, B, LMask
14521 // RHS = VECTOR_SHUFFLE A, B, RMask
14522 // Check that the masks correspond to performing a horizontal operation.
14523 for (unsigned i = 0; i != NumElts; ++i) {
14524 int LIdx = LMask[i], RIdx = RMask[i];
14526 // Ignore any UNDEF components.
14527 if (LIdx < 0 || RIdx < 0 ||
14528 (!A.getNode() && (LIdx < (int)NumElts || RIdx < (int)NumElts)) ||
14529 (!B.getNode() && (LIdx >= (int)NumElts || RIdx >= (int)NumElts)))
14532 // Check that successive elements are being operated on. If not, this is
14533 // not a horizontal operation.
14534 unsigned Src = (i/HalfLaneElts) % 2; // each lane is split between srcs
14535 unsigned LaneStart = (i/NumLaneElts) * NumLaneElts;
14536 int Index = 2*(i%HalfLaneElts) + NumElts*Src + LaneStart;
14537 if (!(LIdx == Index && RIdx == Index + 1) &&
14538 !(IsCommutative && LIdx == Index + 1 && RIdx == Index))
14542 LHS = A.getNode() ? A : B; // If A is 'UNDEF', use B for it.
14543 RHS = B.getNode() ? B : A; // If B is 'UNDEF', use A for it.
14547 /// PerformFADDCombine - Do target-specific dag combines on floating point adds.
14548 static SDValue PerformFADDCombine(SDNode *N, SelectionDAG &DAG,
14549 const X86Subtarget *Subtarget) {
14550 EVT VT = N->getValueType(0);
14551 SDValue LHS = N->getOperand(0);
14552 SDValue RHS = N->getOperand(1);
14554 // Try to synthesize horizontal adds from adds of shuffles.
14555 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
14556 (Subtarget->hasAVX() && (VT == MVT::v8f32 || VT == MVT::v4f64))) &&
14557 isHorizontalBinOp(LHS, RHS, true))
14558 return DAG.getNode(X86ISD::FHADD, N->getDebugLoc(), VT, LHS, RHS);
14562 /// PerformFSUBCombine - Do target-specific dag combines on floating point subs.
14563 static SDValue PerformFSUBCombine(SDNode *N, SelectionDAG &DAG,
14564 const X86Subtarget *Subtarget) {
14565 EVT VT = N->getValueType(0);
14566 SDValue LHS = N->getOperand(0);
14567 SDValue RHS = N->getOperand(1);
14569 // Try to synthesize horizontal subs from subs of shuffles.
14570 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
14571 (Subtarget->hasAVX() && (VT == MVT::v8f32 || VT == MVT::v4f64))) &&
14572 isHorizontalBinOp(LHS, RHS, false))
14573 return DAG.getNode(X86ISD::FHSUB, N->getDebugLoc(), VT, LHS, RHS);
14577 /// PerformFORCombine - Do target-specific dag combines on X86ISD::FOR and
14578 /// X86ISD::FXOR nodes.
14579 static SDValue PerformFORCombine(SDNode *N, SelectionDAG &DAG) {
14580 assert(N->getOpcode() == X86ISD::FOR || N->getOpcode() == X86ISD::FXOR);
14581 // F[X]OR(0.0, x) -> x
14582 // F[X]OR(x, 0.0) -> x
14583 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
14584 if (C->getValueAPF().isPosZero())
14585 return N->getOperand(1);
14586 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
14587 if (C->getValueAPF().isPosZero())
14588 return N->getOperand(0);
14592 /// PerformFANDCombine - Do target-specific dag combines on X86ISD::FAND nodes.
14593 static SDValue PerformFANDCombine(SDNode *N, SelectionDAG &DAG) {
14594 // FAND(0.0, x) -> 0.0
14595 // FAND(x, 0.0) -> 0.0
14596 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
14597 if (C->getValueAPF().isPosZero())
14598 return N->getOperand(0);
14599 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
14600 if (C->getValueAPF().isPosZero())
14601 return N->getOperand(1);
14605 static SDValue PerformBTCombine(SDNode *N,
14607 TargetLowering::DAGCombinerInfo &DCI) {
14608 // BT ignores high bits in the bit index operand.
14609 SDValue Op1 = N->getOperand(1);
14610 if (Op1.hasOneUse()) {
14611 unsigned BitWidth = Op1.getValueSizeInBits();
14612 APInt DemandedMask = APInt::getLowBitsSet(BitWidth, Log2_32(BitWidth));
14613 APInt KnownZero, KnownOne;
14614 TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(),
14615 !DCI.isBeforeLegalizeOps());
14616 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
14617 if (TLO.ShrinkDemandedConstant(Op1, DemandedMask) ||
14618 TLI.SimplifyDemandedBits(Op1, DemandedMask, KnownZero, KnownOne, TLO))
14619 DCI.CommitTargetLoweringOpt(TLO);
14624 static SDValue PerformVZEXT_MOVLCombine(SDNode *N, SelectionDAG &DAG) {
14625 SDValue Op = N->getOperand(0);
14626 if (Op.getOpcode() == ISD::BITCAST)
14627 Op = Op.getOperand(0);
14628 EVT VT = N->getValueType(0), OpVT = Op.getValueType();
14629 if (Op.getOpcode() == X86ISD::VZEXT_LOAD &&
14630 VT.getVectorElementType().getSizeInBits() ==
14631 OpVT.getVectorElementType().getSizeInBits()) {
14632 return DAG.getNode(ISD::BITCAST, N->getDebugLoc(), VT, Op);
14637 static SDValue PerformSExtCombine(SDNode *N, SelectionDAG &DAG,
14638 TargetLowering::DAGCombinerInfo &DCI,
14639 const X86Subtarget *Subtarget) {
14640 if (!DCI.isBeforeLegalizeOps())
14643 if (!Subtarget->hasAVX()) return SDValue();
14645 // Optimize vectors in AVX mode
14646 // Sign extend v8i16 to v8i32 and
14649 // Divide input vector into two parts
14650 // for v4i32 the shuffle mask will be { 0, 1, -1, -1} {2, 3, -1, -1}
14651 // use vpmovsx instruction to extend v4i32 -> v2i64; v8i16 -> v4i32
14652 // concat the vectors to original VT
14654 EVT VT = N->getValueType(0);
14655 SDValue Op = N->getOperand(0);
14656 EVT OpVT = Op.getValueType();
14657 DebugLoc dl = N->getDebugLoc();
14659 if (((VT == MVT::v4i64) && (OpVT == MVT::v4i32)) ||
14660 ((VT == MVT::v8i32) && (OpVT == MVT::v8i16))) {
14662 unsigned NumElems = OpVT.getVectorNumElements();
14663 SmallVector<int,8> ShufMask1(NumElems, -1);
14664 for (unsigned i=0; i< NumElems/2; i++) ShufMask1[i] = i;
14666 SDValue OpLo = DAG.getVectorShuffle(OpVT, dl, Op, DAG.getUNDEF(OpVT),
14669 SmallVector<int,8> ShufMask2(NumElems, -1);
14670 for (unsigned i=0; i< NumElems/2; i++) ShufMask2[i] = i+NumElems/2;
14672 SDValue OpHi = DAG.getVectorShuffle(OpVT, dl, Op, DAG.getUNDEF(OpVT),
14675 EVT HalfVT = EVT::getVectorVT(*DAG.getContext(), VT.getScalarType(),
14676 VT.getVectorNumElements()/2);
14678 OpLo = DAG.getNode(X86ISD::VSEXT_MOVL, dl, HalfVT, OpLo);
14679 OpHi = DAG.getNode(X86ISD::VSEXT_MOVL, dl, HalfVT, OpHi);
14681 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi);
14686 static SDValue PerformZExtCombine(SDNode *N, SelectionDAG &DAG,
14687 const X86Subtarget *Subtarget) {
14688 // (i32 zext (and (i8 x86isd::setcc_carry), 1)) ->
14689 // (and (i32 x86isd::setcc_carry), 1)
14690 // This eliminates the zext. This transformation is necessary because
14691 // ISD::SETCC is always legalized to i8.
14692 DebugLoc dl = N->getDebugLoc();
14693 SDValue N0 = N->getOperand(0);
14694 EVT VT = N->getValueType(0);
14695 EVT OpVT = N0.getValueType();
14697 if (N0.getOpcode() == ISD::AND &&
14699 N0.getOperand(0).hasOneUse()) {
14700 SDValue N00 = N0.getOperand(0);
14701 if (N00.getOpcode() != X86ISD::SETCC_CARRY)
14703 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
14704 if (!C || C->getZExtValue() != 1)
14706 return DAG.getNode(ISD::AND, dl, VT,
14707 DAG.getNode(X86ISD::SETCC_CARRY, dl, VT,
14708 N00.getOperand(0), N00.getOperand(1)),
14709 DAG.getConstant(1, VT));
14711 // Optimize vectors in AVX mode:
14714 // Use vpunpcklwd for 4 lower elements v8i16 -> v4i32.
14715 // Use vpunpckhwd for 4 upper elements v8i16 -> v4i32.
14716 // Concat upper and lower parts.
14719 // Use vpunpckldq for 4 lower elements v4i32 -> v2i64.
14720 // Use vpunpckhdq for 4 upper elements v4i32 -> v2i64.
14721 // Concat upper and lower parts.
14723 if (Subtarget->hasAVX()) {
14725 if (((VT == MVT::v8i32) && (OpVT == MVT::v8i16)) ||
14726 ((VT == MVT::v4i64) && (OpVT == MVT::v4i32))) {
14728 SDValue ZeroVec = getZeroVector(OpVT, Subtarget, DAG, dl);
14729 SDValue OpLo = getTargetShuffleNode(X86ISD::UNPCKL, dl, OpVT, N0, ZeroVec, DAG);
14730 SDValue OpHi = getTargetShuffleNode(X86ISD::UNPCKH, dl, OpVT, N0, ZeroVec, DAG);
14732 EVT HVT = EVT::getVectorVT(*DAG.getContext(), VT.getVectorElementType(),
14733 VT.getVectorNumElements()/2);
14735 OpLo = DAG.getNode(ISD::BITCAST, dl, HVT, OpLo);
14736 OpHi = DAG.getNode(ISD::BITCAST, dl, HVT, OpHi);
14738 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi);
14746 // Optimize RES = X86ISD::SETCC CONDCODE, EFLAG_INPUT
14747 static SDValue PerformSETCCCombine(SDNode *N, SelectionDAG &DAG) {
14748 unsigned X86CC = N->getConstantOperandVal(0);
14749 SDValue EFLAG = N->getOperand(1);
14750 DebugLoc DL = N->getDebugLoc();
14752 // Materialize "setb reg" as "sbb reg,reg", since it can be extended without
14753 // a zext and produces an all-ones bit which is more useful than 0/1 in some
14755 if (X86CC == X86::COND_B)
14756 return DAG.getNode(ISD::AND, DL, MVT::i8,
14757 DAG.getNode(X86ISD::SETCC_CARRY, DL, MVT::i8,
14758 DAG.getConstant(X86CC, MVT::i8), EFLAG),
14759 DAG.getConstant(1, MVT::i8));
14764 static SDValue PerformSINT_TO_FPCombine(SDNode *N, SelectionDAG &DAG,
14765 const X86TargetLowering *XTLI) {
14766 SDValue Op0 = N->getOperand(0);
14767 // Transform (SINT_TO_FP (i64 ...)) into an x87 operation if we have
14768 // a 32-bit target where SSE doesn't support i64->FP operations.
14769 if (Op0.getOpcode() == ISD::LOAD) {
14770 LoadSDNode *Ld = cast<LoadSDNode>(Op0.getNode());
14771 EVT VT = Ld->getValueType(0);
14772 if (!Ld->isVolatile() && !N->getValueType(0).isVector() &&
14773 ISD::isNON_EXTLoad(Op0.getNode()) && Op0.hasOneUse() &&
14774 !XTLI->getSubtarget()->is64Bit() &&
14775 !DAG.getTargetLoweringInfo().isTypeLegal(VT)) {
14776 SDValue FILDChain = XTLI->BuildFILD(SDValue(N, 0), Ld->getValueType(0),
14777 Ld->getChain(), Op0, DAG);
14778 DAG.ReplaceAllUsesOfValueWith(Op0.getValue(1), FILDChain.getValue(1));
14785 // Optimize RES, EFLAGS = X86ISD::ADC LHS, RHS, EFLAGS
14786 static SDValue PerformADCCombine(SDNode *N, SelectionDAG &DAG,
14787 X86TargetLowering::DAGCombinerInfo &DCI) {
14788 // If the LHS and RHS of the ADC node are zero, then it can't overflow and
14789 // the result is either zero or one (depending on the input carry bit).
14790 // Strength reduce this down to a "set on carry" aka SETCC_CARRY&1.
14791 if (X86::isZeroNode(N->getOperand(0)) &&
14792 X86::isZeroNode(N->getOperand(1)) &&
14793 // We don't have a good way to replace an EFLAGS use, so only do this when
14795 SDValue(N, 1).use_empty()) {
14796 DebugLoc DL = N->getDebugLoc();
14797 EVT VT = N->getValueType(0);
14798 SDValue CarryOut = DAG.getConstant(0, N->getValueType(1));
14799 SDValue Res1 = DAG.getNode(ISD::AND, DL, VT,
14800 DAG.getNode(X86ISD::SETCC_CARRY, DL, VT,
14801 DAG.getConstant(X86::COND_B,MVT::i8),
14803 DAG.getConstant(1, VT));
14804 return DCI.CombineTo(N, Res1, CarryOut);
14810 // fold (add Y, (sete X, 0)) -> adc 0, Y
14811 // (add Y, (setne X, 0)) -> sbb -1, Y
14812 // (sub (sete X, 0), Y) -> sbb 0, Y
14813 // (sub (setne X, 0), Y) -> adc -1, Y
14814 static SDValue OptimizeConditionalInDecrement(SDNode *N, SelectionDAG &DAG) {
14815 DebugLoc DL = N->getDebugLoc();
14817 // Look through ZExts.
14818 SDValue Ext = N->getOperand(N->getOpcode() == ISD::SUB ? 1 : 0);
14819 if (Ext.getOpcode() != ISD::ZERO_EXTEND || !Ext.hasOneUse())
14822 SDValue SetCC = Ext.getOperand(0);
14823 if (SetCC.getOpcode() != X86ISD::SETCC || !SetCC.hasOneUse())
14826 X86::CondCode CC = (X86::CondCode)SetCC.getConstantOperandVal(0);
14827 if (CC != X86::COND_E && CC != X86::COND_NE)
14830 SDValue Cmp = SetCC.getOperand(1);
14831 if (Cmp.getOpcode() != X86ISD::CMP || !Cmp.hasOneUse() ||
14832 !X86::isZeroNode(Cmp.getOperand(1)) ||
14833 !Cmp.getOperand(0).getValueType().isInteger())
14836 SDValue CmpOp0 = Cmp.getOperand(0);
14837 SDValue NewCmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32, CmpOp0,
14838 DAG.getConstant(1, CmpOp0.getValueType()));
14840 SDValue OtherVal = N->getOperand(N->getOpcode() == ISD::SUB ? 0 : 1);
14841 if (CC == X86::COND_NE)
14842 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::ADC : X86ISD::SBB,
14843 DL, OtherVal.getValueType(), OtherVal,
14844 DAG.getConstant(-1ULL, OtherVal.getValueType()), NewCmp);
14845 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::SBB : X86ISD::ADC,
14846 DL, OtherVal.getValueType(), OtherVal,
14847 DAG.getConstant(0, OtherVal.getValueType()), NewCmp);
14850 /// PerformADDCombine - Do target-specific dag combines on integer adds.
14851 static SDValue PerformAddCombine(SDNode *N, SelectionDAG &DAG,
14852 const X86Subtarget *Subtarget) {
14853 EVT VT = N->getValueType(0);
14854 SDValue Op0 = N->getOperand(0);
14855 SDValue Op1 = N->getOperand(1);
14857 // Try to synthesize horizontal adds from adds of shuffles.
14858 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) ||
14859 (Subtarget->hasAVX2() && (VT == MVT::v16i16 || VT == MVT::v8i32))) &&
14860 isHorizontalBinOp(Op0, Op1, true))
14861 return DAG.getNode(X86ISD::HADD, N->getDebugLoc(), VT, Op0, Op1);
14863 return OptimizeConditionalInDecrement(N, DAG);
14866 static SDValue PerformSubCombine(SDNode *N, SelectionDAG &DAG,
14867 const X86Subtarget *Subtarget) {
14868 SDValue Op0 = N->getOperand(0);
14869 SDValue Op1 = N->getOperand(1);
14871 // X86 can't encode an immediate LHS of a sub. See if we can push the
14872 // negation into a preceding instruction.
14873 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op0)) {
14874 // If the RHS of the sub is a XOR with one use and a constant, invert the
14875 // immediate. Then add one to the LHS of the sub so we can turn
14876 // X-Y -> X+~Y+1, saving one register.
14877 if (Op1->hasOneUse() && Op1.getOpcode() == ISD::XOR &&
14878 isa<ConstantSDNode>(Op1.getOperand(1))) {
14879 APInt XorC = cast<ConstantSDNode>(Op1.getOperand(1))->getAPIntValue();
14880 EVT VT = Op0.getValueType();
14881 SDValue NewXor = DAG.getNode(ISD::XOR, Op1.getDebugLoc(), VT,
14883 DAG.getConstant(~XorC, VT));
14884 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, NewXor,
14885 DAG.getConstant(C->getAPIntValue()+1, VT));
14889 // Try to synthesize horizontal adds from adds of shuffles.
14890 EVT VT = N->getValueType(0);
14891 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) ||
14892 (Subtarget->hasAVX2() && (VT == MVT::v16i16 || VT == MVT::v8i32))) &&
14893 isHorizontalBinOp(Op0, Op1, true))
14894 return DAG.getNode(X86ISD::HSUB, N->getDebugLoc(), VT, Op0, Op1);
14896 return OptimizeConditionalInDecrement(N, DAG);
14899 SDValue X86TargetLowering::PerformDAGCombine(SDNode *N,
14900 DAGCombinerInfo &DCI) const {
14901 SelectionDAG &DAG = DCI.DAG;
14902 switch (N->getOpcode()) {
14904 case ISD::EXTRACT_VECTOR_ELT:
14905 return PerformEXTRACT_VECTOR_ELTCombine(N, DAG, *this);
14907 case ISD::SELECT: return PerformSELECTCombine(N, DAG, DCI, Subtarget);
14908 case X86ISD::CMOV: return PerformCMOVCombine(N, DAG, DCI);
14909 case ISD::ADD: return PerformAddCombine(N, DAG, Subtarget);
14910 case ISD::SUB: return PerformSubCombine(N, DAG, Subtarget);
14911 case X86ISD::ADC: return PerformADCCombine(N, DAG, DCI);
14912 case ISD::MUL: return PerformMulCombine(N, DAG, DCI);
14915 case ISD::SRL: return PerformShiftCombine(N, DAG, DCI, Subtarget);
14916 case ISD::AND: return PerformAndCombine(N, DAG, DCI, Subtarget);
14917 case ISD::OR: return PerformOrCombine(N, DAG, DCI, Subtarget);
14918 case ISD::XOR: return PerformXorCombine(N, DAG, DCI, Subtarget);
14919 case ISD::LOAD: return PerformLOADCombine(N, DAG, Subtarget);
14920 case ISD::STORE: return PerformSTORECombine(N, DAG, Subtarget);
14921 case ISD::SINT_TO_FP: return PerformSINT_TO_FPCombine(N, DAG, this);
14922 case ISD::FADD: return PerformFADDCombine(N, DAG, Subtarget);
14923 case ISD::FSUB: return PerformFSUBCombine(N, DAG, Subtarget);
14925 case X86ISD::FOR: return PerformFORCombine(N, DAG);
14926 case X86ISD::FAND: return PerformFANDCombine(N, DAG);
14927 case X86ISD::BT: return PerformBTCombine(N, DAG, DCI);
14928 case X86ISD::VZEXT_MOVL: return PerformVZEXT_MOVLCombine(N, DAG);
14929 case ISD::ZERO_EXTEND: return PerformZExtCombine(N, DAG, Subtarget);
14930 case ISD::SIGN_EXTEND: return PerformSExtCombine(N, DAG, DCI, Subtarget);
14931 case ISD::TRUNCATE: return PerformTruncateCombine(N, DAG, DCI);
14932 case X86ISD::SETCC: return PerformSETCCCombine(N, DAG);
14933 case X86ISD::SHUFP: // Handle all target specific shuffles
14934 case X86ISD::PALIGN:
14935 case X86ISD::UNPCKH:
14936 case X86ISD::UNPCKL:
14937 case X86ISD::MOVHLPS:
14938 case X86ISD::MOVLHPS:
14939 case X86ISD::PSHUFD:
14940 case X86ISD::PSHUFHW:
14941 case X86ISD::PSHUFLW:
14942 case X86ISD::MOVSS:
14943 case X86ISD::MOVSD:
14944 case X86ISD::VPERMILP:
14945 case X86ISD::VPERM2X128:
14946 case ISD::VECTOR_SHUFFLE: return PerformShuffleCombine(N, DAG, DCI,Subtarget);
14952 /// isTypeDesirableForOp - Return true if the target has native support for
14953 /// the specified value type and it is 'desirable' to use the type for the
14954 /// given node type. e.g. On x86 i16 is legal, but undesirable since i16
14955 /// instruction encodings are longer and some i16 instructions are slow.
14956 bool X86TargetLowering::isTypeDesirableForOp(unsigned Opc, EVT VT) const {
14957 if (!isTypeLegal(VT))
14959 if (VT != MVT::i16)
14966 case ISD::SIGN_EXTEND:
14967 case ISD::ZERO_EXTEND:
14968 case ISD::ANY_EXTEND:
14981 /// IsDesirableToPromoteOp - This method query the target whether it is
14982 /// beneficial for dag combiner to promote the specified node. If true, it
14983 /// should return the desired promotion type by reference.
14984 bool X86TargetLowering::IsDesirableToPromoteOp(SDValue Op, EVT &PVT) const {
14985 EVT VT = Op.getValueType();
14986 if (VT != MVT::i16)
14989 bool Promote = false;
14990 bool Commute = false;
14991 switch (Op.getOpcode()) {
14994 LoadSDNode *LD = cast<LoadSDNode>(Op);
14995 // If the non-extending load has a single use and it's not live out, then it
14996 // might be folded.
14997 if (LD->getExtensionType() == ISD::NON_EXTLOAD /*&&
14998 Op.hasOneUse()*/) {
14999 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
15000 UE = Op.getNode()->use_end(); UI != UE; ++UI) {
15001 // The only case where we'd want to promote LOAD (rather then it being
15002 // promoted as an operand is when it's only use is liveout.
15003 if (UI->getOpcode() != ISD::CopyToReg)
15010 case ISD::SIGN_EXTEND:
15011 case ISD::ZERO_EXTEND:
15012 case ISD::ANY_EXTEND:
15017 SDValue N0 = Op.getOperand(0);
15018 // Look out for (store (shl (load), x)).
15019 if (MayFoldLoad(N0) && MayFoldIntoStore(Op))
15032 SDValue N0 = Op.getOperand(0);
15033 SDValue N1 = Op.getOperand(1);
15034 if (!Commute && MayFoldLoad(N1))
15036 // Avoid disabling potential load folding opportunities.
15037 if (MayFoldLoad(N0) && (!isa<ConstantSDNode>(N1) || MayFoldIntoStore(Op)))
15039 if (MayFoldLoad(N1) && (!isa<ConstantSDNode>(N0) || MayFoldIntoStore(Op)))
15049 //===----------------------------------------------------------------------===//
15050 // X86 Inline Assembly Support
15051 //===----------------------------------------------------------------------===//
15054 // Helper to match a string separated by whitespace.
15055 bool matchAsmImpl(StringRef s, ArrayRef<const StringRef *> args) {
15056 s = s.substr(s.find_first_not_of(" \t")); // Skip leading whitespace.
15058 for (unsigned i = 0, e = args.size(); i != e; ++i) {
15059 StringRef piece(*args[i]);
15060 if (!s.startswith(piece)) // Check if the piece matches.
15063 s = s.substr(piece.size());
15064 StringRef::size_type pos = s.find_first_not_of(" \t");
15065 if (pos == 0) // We matched a prefix.
15073 const VariadicFunction1<bool, StringRef, StringRef, matchAsmImpl> matchAsm={};
15076 bool X86TargetLowering::ExpandInlineAsm(CallInst *CI) const {
15077 InlineAsm *IA = cast<InlineAsm>(CI->getCalledValue());
15079 std::string AsmStr = IA->getAsmString();
15081 IntegerType *Ty = dyn_cast<IntegerType>(CI->getType());
15082 if (!Ty || Ty->getBitWidth() % 16 != 0)
15085 // TODO: should remove alternatives from the asmstring: "foo {a|b}" -> "foo a"
15086 SmallVector<StringRef, 4> AsmPieces;
15087 SplitString(AsmStr, AsmPieces, ";\n");
15089 switch (AsmPieces.size()) {
15090 default: return false;
15092 // FIXME: this should verify that we are targeting a 486 or better. If not,
15093 // we will turn this bswap into something that will be lowered to logical
15094 // ops instead of emitting the bswap asm. For now, we don't support 486 or
15095 // lower so don't worry about this.
15097 if (matchAsm(AsmPieces[0], "bswap", "$0") ||
15098 matchAsm(AsmPieces[0], "bswapl", "$0") ||
15099 matchAsm(AsmPieces[0], "bswapq", "$0") ||
15100 matchAsm(AsmPieces[0], "bswap", "${0:q}") ||
15101 matchAsm(AsmPieces[0], "bswapl", "${0:q}") ||
15102 matchAsm(AsmPieces[0], "bswapq", "${0:q}")) {
15103 // No need to check constraints, nothing other than the equivalent of
15104 // "=r,0" would be valid here.
15105 return IntrinsicLowering::LowerToByteSwap(CI);
15108 // rorw $$8, ${0:w} --> llvm.bswap.i16
15109 if (CI->getType()->isIntegerTy(16) &&
15110 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 &&
15111 (matchAsm(AsmPieces[0], "rorw", "$$8,", "${0:w}") ||
15112 matchAsm(AsmPieces[0], "rolw", "$$8,", "${0:w}"))) {
15114 const std::string &ConstraintsStr = IA->getConstraintString();
15115 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
15116 std::sort(AsmPieces.begin(), AsmPieces.end());
15117 if (AsmPieces.size() == 4 &&
15118 AsmPieces[0] == "~{cc}" &&
15119 AsmPieces[1] == "~{dirflag}" &&
15120 AsmPieces[2] == "~{flags}" &&
15121 AsmPieces[3] == "~{fpsr}")
15122 return IntrinsicLowering::LowerToByteSwap(CI);
15126 if (CI->getType()->isIntegerTy(32) &&
15127 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 &&
15128 matchAsm(AsmPieces[0], "rorw", "$$8,", "${0:w}") &&
15129 matchAsm(AsmPieces[1], "rorl", "$$16,", "$0") &&
15130 matchAsm(AsmPieces[2], "rorw", "$$8,", "${0:w}")) {
15132 const std::string &ConstraintsStr = IA->getConstraintString();
15133 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
15134 std::sort(AsmPieces.begin(), AsmPieces.end());
15135 if (AsmPieces.size() == 4 &&
15136 AsmPieces[0] == "~{cc}" &&
15137 AsmPieces[1] == "~{dirflag}" &&
15138 AsmPieces[2] == "~{flags}" &&
15139 AsmPieces[3] == "~{fpsr}")
15140 return IntrinsicLowering::LowerToByteSwap(CI);
15143 if (CI->getType()->isIntegerTy(64)) {
15144 InlineAsm::ConstraintInfoVector Constraints = IA->ParseConstraints();
15145 if (Constraints.size() >= 2 &&
15146 Constraints[0].Codes.size() == 1 && Constraints[0].Codes[0] == "A" &&
15147 Constraints[1].Codes.size() == 1 && Constraints[1].Codes[0] == "0") {
15148 // bswap %eax / bswap %edx / xchgl %eax, %edx -> llvm.bswap.i64
15149 if (matchAsm(AsmPieces[0], "bswap", "%eax") &&
15150 matchAsm(AsmPieces[1], "bswap", "%edx") &&
15151 matchAsm(AsmPieces[2], "xchgl", "%eax,", "%edx"))
15152 return IntrinsicLowering::LowerToByteSwap(CI);
15162 /// getConstraintType - Given a constraint letter, return the type of
15163 /// constraint it is for this target.
15164 X86TargetLowering::ConstraintType
15165 X86TargetLowering::getConstraintType(const std::string &Constraint) const {
15166 if (Constraint.size() == 1) {
15167 switch (Constraint[0]) {
15178 return C_RegisterClass;
15202 return TargetLowering::getConstraintType(Constraint);
15205 /// Examine constraint type and operand type and determine a weight value.
15206 /// This object must already have been set up with the operand type
15207 /// and the current alternative constraint selected.
15208 TargetLowering::ConstraintWeight
15209 X86TargetLowering::getSingleConstraintMatchWeight(
15210 AsmOperandInfo &info, const char *constraint) const {
15211 ConstraintWeight weight = CW_Invalid;
15212 Value *CallOperandVal = info.CallOperandVal;
15213 // If we don't have a value, we can't do a match,
15214 // but allow it at the lowest weight.
15215 if (CallOperandVal == NULL)
15217 Type *type = CallOperandVal->getType();
15218 // Look at the constraint type.
15219 switch (*constraint) {
15221 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
15232 if (CallOperandVal->getType()->isIntegerTy())
15233 weight = CW_SpecificReg;
15238 if (type->isFloatingPointTy())
15239 weight = CW_SpecificReg;
15242 if (type->isX86_MMXTy() && Subtarget->hasMMX())
15243 weight = CW_SpecificReg;
15247 if (((type->getPrimitiveSizeInBits() == 128) && Subtarget->hasSSE1()) ||
15248 ((type->getPrimitiveSizeInBits() == 256) && Subtarget->hasAVX()))
15249 weight = CW_Register;
15252 if (ConstantInt *C = dyn_cast<ConstantInt>(info.CallOperandVal)) {
15253 if (C->getZExtValue() <= 31)
15254 weight = CW_Constant;
15258 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
15259 if (C->getZExtValue() <= 63)
15260 weight = CW_Constant;
15264 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
15265 if ((C->getSExtValue() >= -0x80) && (C->getSExtValue() <= 0x7f))
15266 weight = CW_Constant;
15270 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
15271 if ((C->getZExtValue() == 0xff) || (C->getZExtValue() == 0xffff))
15272 weight = CW_Constant;
15276 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
15277 if (C->getZExtValue() <= 3)
15278 weight = CW_Constant;
15282 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
15283 if (C->getZExtValue() <= 0xff)
15284 weight = CW_Constant;
15289 if (dyn_cast<ConstantFP>(CallOperandVal)) {
15290 weight = CW_Constant;
15294 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
15295 if ((C->getSExtValue() >= -0x80000000LL) &&
15296 (C->getSExtValue() <= 0x7fffffffLL))
15297 weight = CW_Constant;
15301 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
15302 if (C->getZExtValue() <= 0xffffffff)
15303 weight = CW_Constant;
15310 /// LowerXConstraint - try to replace an X constraint, which matches anything,
15311 /// with another that has more specific requirements based on the type of the
15312 /// corresponding operand.
15313 const char *X86TargetLowering::
15314 LowerXConstraint(EVT ConstraintVT) const {
15315 // FP X constraints get lowered to SSE1/2 registers if available, otherwise
15316 // 'f' like normal targets.
15317 if (ConstraintVT.isFloatingPoint()) {
15318 if (Subtarget->hasSSE2())
15320 if (Subtarget->hasSSE1())
15324 return TargetLowering::LowerXConstraint(ConstraintVT);
15327 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
15328 /// vector. If it is invalid, don't add anything to Ops.
15329 void X86TargetLowering::LowerAsmOperandForConstraint(SDValue Op,
15330 std::string &Constraint,
15331 std::vector<SDValue>&Ops,
15332 SelectionDAG &DAG) const {
15333 SDValue Result(0, 0);
15335 // Only support length 1 constraints for now.
15336 if (Constraint.length() > 1) return;
15338 char ConstraintLetter = Constraint[0];
15339 switch (ConstraintLetter) {
15342 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
15343 if (C->getZExtValue() <= 31) {
15344 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
15350 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
15351 if (C->getZExtValue() <= 63) {
15352 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
15358 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
15359 if ((int8_t)C->getSExtValue() == C->getSExtValue()) {
15360 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
15366 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
15367 if (C->getZExtValue() <= 255) {
15368 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
15374 // 32-bit signed value
15375 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
15376 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
15377 C->getSExtValue())) {
15378 // Widen to 64 bits here to get it sign extended.
15379 Result = DAG.getTargetConstant(C->getSExtValue(), MVT::i64);
15382 // FIXME gcc accepts some relocatable values here too, but only in certain
15383 // memory models; it's complicated.
15388 // 32-bit unsigned value
15389 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
15390 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
15391 C->getZExtValue())) {
15392 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
15396 // FIXME gcc accepts some relocatable values here too, but only in certain
15397 // memory models; it's complicated.
15401 // Literal immediates are always ok.
15402 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op)) {
15403 // Widen to 64 bits here to get it sign extended.
15404 Result = DAG.getTargetConstant(CST->getSExtValue(), MVT::i64);
15408 // In any sort of PIC mode addresses need to be computed at runtime by
15409 // adding in a register or some sort of table lookup. These can't
15410 // be used as immediates.
15411 if (Subtarget->isPICStyleGOT() || Subtarget->isPICStyleStubPIC())
15414 // If we are in non-pic codegen mode, we allow the address of a global (with
15415 // an optional displacement) to be used with 'i'.
15416 GlobalAddressSDNode *GA = 0;
15417 int64_t Offset = 0;
15419 // Match either (GA), (GA+C), (GA+C1+C2), etc.
15421 if ((GA = dyn_cast<GlobalAddressSDNode>(Op))) {
15422 Offset += GA->getOffset();
15424 } else if (Op.getOpcode() == ISD::ADD) {
15425 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
15426 Offset += C->getZExtValue();
15427 Op = Op.getOperand(0);
15430 } else if (Op.getOpcode() == ISD::SUB) {
15431 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
15432 Offset += -C->getZExtValue();
15433 Op = Op.getOperand(0);
15438 // Otherwise, this isn't something we can handle, reject it.
15442 const GlobalValue *GV = GA->getGlobal();
15443 // If we require an extra load to get this address, as in PIC mode, we
15444 // can't accept it.
15445 if (isGlobalStubReference(Subtarget->ClassifyGlobalReference(GV,
15446 getTargetMachine())))
15449 Result = DAG.getTargetGlobalAddress(GV, Op.getDebugLoc(),
15450 GA->getValueType(0), Offset);
15455 if (Result.getNode()) {
15456 Ops.push_back(Result);
15459 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
15462 std::pair<unsigned, const TargetRegisterClass*>
15463 X86TargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
15465 // First, see if this is a constraint that directly corresponds to an LLVM
15467 if (Constraint.size() == 1) {
15468 // GCC Constraint Letters
15469 switch (Constraint[0]) {
15471 // TODO: Slight differences here in allocation order and leaving
15472 // RIP in the class. Do they matter any more here than they do
15473 // in the normal allocation?
15474 case 'q': // GENERAL_REGS in 64-bit mode, Q_REGS in 32-bit mode.
15475 if (Subtarget->is64Bit()) {
15476 if (VT == MVT::i32 || VT == MVT::f32)
15477 return std::make_pair(0U, X86::GR32RegisterClass);
15478 else if (VT == MVT::i16)
15479 return std::make_pair(0U, X86::GR16RegisterClass);
15480 else if (VT == MVT::i8 || VT == MVT::i1)
15481 return std::make_pair(0U, X86::GR8RegisterClass);
15482 else if (VT == MVT::i64 || VT == MVT::f64)
15483 return std::make_pair(0U, X86::GR64RegisterClass);
15486 // 32-bit fallthrough
15487 case 'Q': // Q_REGS
15488 if (VT == MVT::i32 || VT == MVT::f32)
15489 return std::make_pair(0U, X86::GR32_ABCDRegisterClass);
15490 else if (VT == MVT::i16)
15491 return std::make_pair(0U, X86::GR16_ABCDRegisterClass);
15492 else if (VT == MVT::i8 || VT == MVT::i1)
15493 return std::make_pair(0U, X86::GR8_ABCD_LRegisterClass);
15494 else if (VT == MVT::i64)
15495 return std::make_pair(0U, X86::GR64_ABCDRegisterClass);
15497 case 'r': // GENERAL_REGS
15498 case 'l': // INDEX_REGS
15499 if (VT == MVT::i8 || VT == MVT::i1)
15500 return std::make_pair(0U, X86::GR8RegisterClass);
15501 if (VT == MVT::i16)
15502 return std::make_pair(0U, X86::GR16RegisterClass);
15503 if (VT == MVT::i32 || VT == MVT::f32 || !Subtarget->is64Bit())
15504 return std::make_pair(0U, X86::GR32RegisterClass);
15505 return std::make_pair(0U, X86::GR64RegisterClass);
15506 case 'R': // LEGACY_REGS
15507 if (VT == MVT::i8 || VT == MVT::i1)
15508 return std::make_pair(0U, X86::GR8_NOREXRegisterClass);
15509 if (VT == MVT::i16)
15510 return std::make_pair(0U, X86::GR16_NOREXRegisterClass);
15511 if (VT == MVT::i32 || !Subtarget->is64Bit())
15512 return std::make_pair(0U, X86::GR32_NOREXRegisterClass);
15513 return std::make_pair(0U, X86::GR64_NOREXRegisterClass);
15514 case 'f': // FP Stack registers.
15515 // If SSE is enabled for this VT, use f80 to ensure the isel moves the
15516 // value to the correct fpstack register class.
15517 if (VT == MVT::f32 && !isScalarFPTypeInSSEReg(VT))
15518 return std::make_pair(0U, X86::RFP32RegisterClass);
15519 if (VT == MVT::f64 && !isScalarFPTypeInSSEReg(VT))
15520 return std::make_pair(0U, X86::RFP64RegisterClass);
15521 return std::make_pair(0U, X86::RFP80RegisterClass);
15522 case 'y': // MMX_REGS if MMX allowed.
15523 if (!Subtarget->hasMMX()) break;
15524 return std::make_pair(0U, X86::VR64RegisterClass);
15525 case 'Y': // SSE_REGS if SSE2 allowed
15526 if (!Subtarget->hasSSE2()) break;
15528 case 'x': // SSE_REGS if SSE1 allowed or AVX_REGS if AVX allowed
15529 if (!Subtarget->hasSSE1()) break;
15531 switch (VT.getSimpleVT().SimpleTy) {
15533 // Scalar SSE types.
15536 return std::make_pair(0U, X86::FR32RegisterClass);
15539 return std::make_pair(0U, X86::FR64RegisterClass);
15547 return std::make_pair(0U, X86::VR128RegisterClass);
15555 return std::make_pair(0U, X86::VR256RegisterClass);
15562 // Use the default implementation in TargetLowering to convert the register
15563 // constraint into a member of a register class.
15564 std::pair<unsigned, const TargetRegisterClass*> Res;
15565 Res = TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
15567 // Not found as a standard register?
15568 if (Res.second == 0) {
15569 // Map st(0) -> st(7) -> ST0
15570 if (Constraint.size() == 7 && Constraint[0] == '{' &&
15571 tolower(Constraint[1]) == 's' &&
15572 tolower(Constraint[2]) == 't' &&
15573 Constraint[3] == '(' &&
15574 (Constraint[4] >= '0' && Constraint[4] <= '7') &&
15575 Constraint[5] == ')' &&
15576 Constraint[6] == '}') {
15578 Res.first = X86::ST0+Constraint[4]-'0';
15579 Res.second = X86::RFP80RegisterClass;
15583 // GCC allows "st(0)" to be called just plain "st".
15584 if (StringRef("{st}").equals_lower(Constraint)) {
15585 Res.first = X86::ST0;
15586 Res.second = X86::RFP80RegisterClass;
15591 if (StringRef("{flags}").equals_lower(Constraint)) {
15592 Res.first = X86::EFLAGS;
15593 Res.second = X86::CCRRegisterClass;
15597 // 'A' means EAX + EDX.
15598 if (Constraint == "A") {
15599 Res.first = X86::EAX;
15600 Res.second = X86::GR32_ADRegisterClass;
15606 // Otherwise, check to see if this is a register class of the wrong value
15607 // type. For example, we want to map "{ax},i32" -> {eax}, we don't want it to
15608 // turn into {ax},{dx}.
15609 if (Res.second->hasType(VT))
15610 return Res; // Correct type already, nothing to do.
15612 // All of the single-register GCC register classes map their values onto
15613 // 16-bit register pieces "ax","dx","cx","bx","si","di","bp","sp". If we
15614 // really want an 8-bit or 32-bit register, map to the appropriate register
15615 // class and return the appropriate register.
15616 if (Res.second == X86::GR16RegisterClass) {
15617 if (VT == MVT::i8) {
15618 unsigned DestReg = 0;
15619 switch (Res.first) {
15621 case X86::AX: DestReg = X86::AL; break;
15622 case X86::DX: DestReg = X86::DL; break;
15623 case X86::CX: DestReg = X86::CL; break;
15624 case X86::BX: DestReg = X86::BL; break;
15627 Res.first = DestReg;
15628 Res.second = X86::GR8RegisterClass;
15630 } else if (VT == MVT::i32) {
15631 unsigned DestReg = 0;
15632 switch (Res.first) {
15634 case X86::AX: DestReg = X86::EAX; break;
15635 case X86::DX: DestReg = X86::EDX; break;
15636 case X86::CX: DestReg = X86::ECX; break;
15637 case X86::BX: DestReg = X86::EBX; break;
15638 case X86::SI: DestReg = X86::ESI; break;
15639 case X86::DI: DestReg = X86::EDI; break;
15640 case X86::BP: DestReg = X86::EBP; break;
15641 case X86::SP: DestReg = X86::ESP; break;
15644 Res.first = DestReg;
15645 Res.second = X86::GR32RegisterClass;
15647 } else if (VT == MVT::i64) {
15648 unsigned DestReg = 0;
15649 switch (Res.first) {
15651 case X86::AX: DestReg = X86::RAX; break;
15652 case X86::DX: DestReg = X86::RDX; break;
15653 case X86::CX: DestReg = X86::RCX; break;
15654 case X86::BX: DestReg = X86::RBX; break;
15655 case X86::SI: DestReg = X86::RSI; break;
15656 case X86::DI: DestReg = X86::RDI; break;
15657 case X86::BP: DestReg = X86::RBP; break;
15658 case X86::SP: DestReg = X86::RSP; break;
15661 Res.first = DestReg;
15662 Res.second = X86::GR64RegisterClass;
15665 } else if (Res.second == X86::FR32RegisterClass ||
15666 Res.second == X86::FR64RegisterClass ||
15667 Res.second == X86::VR128RegisterClass) {
15668 // Handle references to XMM physical registers that got mapped into the
15669 // wrong class. This can happen with constraints like {xmm0} where the
15670 // target independent register mapper will just pick the first match it can
15671 // find, ignoring the required type.
15672 if (VT == MVT::f32)
15673 Res.second = X86::FR32RegisterClass;
15674 else if (VT == MVT::f64)
15675 Res.second = X86::FR64RegisterClass;
15676 else if (X86::VR128RegisterClass->hasType(VT))
15677 Res.second = X86::VR128RegisterClass;