1 //===-- X86ISelLowering.cpp - X86 DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that X86 uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "x86-isel"
16 #include "X86ISelLowering.h"
18 #include "X86InstrBuilder.h"
19 #include "X86TargetMachine.h"
20 #include "X86TargetObjectFile.h"
21 #include "Utils/X86ShuffleDecode.h"
22 #include "llvm/CallingConv.h"
23 #include "llvm/Constants.h"
24 #include "llvm/DerivedTypes.h"
25 #include "llvm/GlobalAlias.h"
26 #include "llvm/GlobalVariable.h"
27 #include "llvm/Function.h"
28 #include "llvm/Instructions.h"
29 #include "llvm/Intrinsics.h"
30 #include "llvm/LLVMContext.h"
31 #include "llvm/CodeGen/IntrinsicLowering.h"
32 #include "llvm/CodeGen/MachineFrameInfo.h"
33 #include "llvm/CodeGen/MachineFunction.h"
34 #include "llvm/CodeGen/MachineInstrBuilder.h"
35 #include "llvm/CodeGen/MachineJumpTableInfo.h"
36 #include "llvm/CodeGen/MachineModuleInfo.h"
37 #include "llvm/CodeGen/MachineRegisterInfo.h"
38 #include "llvm/MC/MCAsmInfo.h"
39 #include "llvm/MC/MCContext.h"
40 #include "llvm/MC/MCExpr.h"
41 #include "llvm/MC/MCSymbol.h"
42 #include "llvm/ADT/SmallSet.h"
43 #include "llvm/ADT/Statistic.h"
44 #include "llvm/ADT/StringExtras.h"
45 #include "llvm/ADT/VariadicFunction.h"
46 #include "llvm/Support/CallSite.h"
47 #include "llvm/Support/Debug.h"
48 #include "llvm/Support/ErrorHandling.h"
49 #include "llvm/Support/MathExtras.h"
50 #include "llvm/Target/TargetOptions.h"
54 STATISTIC(NumTailCalls, "Number of tail calls");
56 // Forward declarations.
57 static SDValue getMOVL(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1,
60 /// Generate a DAG to grab 128-bits from a vector > 128 bits. This
61 /// sets things up to match to an AVX VEXTRACTF128 instruction or a
62 /// simple subregister reference. Idx is an index in the 128 bits we
63 /// want. It need not be aligned to a 128-bit bounday. That makes
64 /// lowering EXTRACT_VECTOR_ELT operations easier.
65 static SDValue Extract128BitVector(SDValue Vec, unsigned IdxVal,
66 SelectionDAG &DAG, DebugLoc dl) {
67 EVT VT = Vec.getValueType();
68 assert(VT.getSizeInBits() == 256 && "Unexpected vector size!");
69 EVT ElVT = VT.getVectorElementType();
70 unsigned Factor = VT.getSizeInBits()/128;
71 EVT ResultVT = EVT::getVectorVT(*DAG.getContext(), ElVT,
72 VT.getVectorNumElements()/Factor);
74 // Extract from UNDEF is UNDEF.
75 if (Vec.getOpcode() == ISD::UNDEF)
76 return DAG.getUNDEF(ResultVT);
78 // Extract the relevant 128 bits. Generate an EXTRACT_SUBVECTOR
79 // we can match to VEXTRACTF128.
80 unsigned ElemsPerChunk = 128 / ElVT.getSizeInBits();
82 // This is the index of the first element of the 128-bit chunk
84 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits()) / 128)
87 SDValue VecIdx = DAG.getConstant(NormalizedIdxVal, MVT::i32);
88 SDValue Result = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, ResultVT, Vec,
94 /// Generate a DAG to put 128-bits into a vector > 128 bits. This
95 /// sets things up to match to an AVX VINSERTF128 instruction or a
96 /// simple superregister reference. Idx is an index in the 128 bits
97 /// we want. It need not be aligned to a 128-bit bounday. That makes
98 /// lowering INSERT_VECTOR_ELT operations easier.
99 static SDValue Insert128BitVector(SDValue Result, SDValue Vec,
100 unsigned IdxVal, SelectionDAG &DAG,
102 EVT VT = Vec.getValueType();
103 assert(VT.getSizeInBits() == 128 && "Unexpected vector size!");
105 EVT ElVT = VT.getVectorElementType();
106 EVT ResultVT = Result.getValueType();
108 // Insert the relevant 128 bits.
109 unsigned ElemsPerChunk = 128/ElVT.getSizeInBits();
111 // This is the index of the first element of the 128-bit chunk
113 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits())/128)
116 SDValue VecIdx = DAG.getConstant(NormalizedIdxVal, MVT::i32);
117 Result = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResultVT, Result, Vec,
122 /// Concat two 128-bit vectors into a 256 bit vector using VINSERTF128
123 /// instructions. This is used because creating CONCAT_VECTOR nodes of
124 /// BUILD_VECTORS returns a larger BUILD_VECTOR while we're trying to lower
125 /// large BUILD_VECTORS.
126 static SDValue Concat128BitVectors(SDValue V1, SDValue V2, EVT VT,
127 unsigned NumElems, SelectionDAG &DAG,
129 SDValue V = Insert128BitVector(DAG.getUNDEF(VT), V1, 0, DAG, dl);
130 return Insert128BitVector(V, V2, NumElems/2, DAG, dl);
133 static TargetLoweringObjectFile *createTLOF(X86TargetMachine &TM) {
134 const X86Subtarget *Subtarget = &TM.getSubtarget<X86Subtarget>();
135 bool is64Bit = Subtarget->is64Bit();
137 if (Subtarget->isTargetEnvMacho()) {
139 return new X8664_MachoTargetObjectFile();
140 return new TargetLoweringObjectFileMachO();
143 if (Subtarget->isTargetELF())
144 return new TargetLoweringObjectFileELF();
145 if (Subtarget->isTargetCOFF() && !Subtarget->isTargetEnvMacho())
146 return new TargetLoweringObjectFileCOFF();
147 llvm_unreachable("unknown subtarget type");
150 X86TargetLowering::X86TargetLowering(X86TargetMachine &TM)
151 : TargetLowering(TM, createTLOF(TM)) {
152 Subtarget = &TM.getSubtarget<X86Subtarget>();
153 X86ScalarSSEf64 = Subtarget->hasSSE2();
154 X86ScalarSSEf32 = Subtarget->hasSSE1();
155 X86StackPtr = Subtarget->is64Bit() ? X86::RSP : X86::ESP;
157 RegInfo = TM.getRegisterInfo();
158 TD = getTargetData();
160 // Set up the TargetLowering object.
161 static const MVT IntVTs[] = { MVT::i8, MVT::i16, MVT::i32, MVT::i64 };
163 // X86 is weird, it always uses i8 for shift amounts and setcc results.
164 setBooleanContents(ZeroOrOneBooleanContent);
165 // X86-SSE is even stranger. It uses -1 or 0 for vector masks.
166 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
168 // For 64-bit since we have so many registers use the ILP scheduler, for
169 // 32-bit code use the register pressure specific scheduling.
170 // For Atom, always use ILP scheduling.
171 if (Subtarget->isAtom())
172 setSchedulingPreference(Sched::ILP);
173 else if (Subtarget->is64Bit())
174 setSchedulingPreference(Sched::ILP);
176 setSchedulingPreference(Sched::RegPressure);
177 setStackPointerRegisterToSaveRestore(X86StackPtr);
179 if (Subtarget->isTargetWindows() && !Subtarget->isTargetCygMing()) {
180 // Setup Windows compiler runtime calls.
181 setLibcallName(RTLIB::SDIV_I64, "_alldiv");
182 setLibcallName(RTLIB::UDIV_I64, "_aulldiv");
183 setLibcallName(RTLIB::SREM_I64, "_allrem");
184 setLibcallName(RTLIB::UREM_I64, "_aullrem");
185 setLibcallName(RTLIB::MUL_I64, "_allmul");
186 setLibcallCallingConv(RTLIB::SDIV_I64, CallingConv::X86_StdCall);
187 setLibcallCallingConv(RTLIB::UDIV_I64, CallingConv::X86_StdCall);
188 setLibcallCallingConv(RTLIB::SREM_I64, CallingConv::X86_StdCall);
189 setLibcallCallingConv(RTLIB::UREM_I64, CallingConv::X86_StdCall);
190 setLibcallCallingConv(RTLIB::MUL_I64, CallingConv::X86_StdCall);
192 // The _ftol2 runtime function has an unusual calling conv, which
193 // is modeled by a special pseudo-instruction.
194 setLibcallName(RTLIB::FPTOUINT_F64_I64, 0);
195 setLibcallName(RTLIB::FPTOUINT_F32_I64, 0);
196 setLibcallName(RTLIB::FPTOUINT_F64_I32, 0);
197 setLibcallName(RTLIB::FPTOUINT_F32_I32, 0);
200 if (Subtarget->isTargetDarwin()) {
201 // Darwin should use _setjmp/_longjmp instead of setjmp/longjmp.
202 setUseUnderscoreSetJmp(false);
203 setUseUnderscoreLongJmp(false);
204 } else if (Subtarget->isTargetMingw()) {
205 // MS runtime is weird: it exports _setjmp, but longjmp!
206 setUseUnderscoreSetJmp(true);
207 setUseUnderscoreLongJmp(false);
209 setUseUnderscoreSetJmp(true);
210 setUseUnderscoreLongJmp(true);
213 // Set up the register classes.
214 addRegisterClass(MVT::i8, &X86::GR8RegClass);
215 addRegisterClass(MVT::i16, &X86::GR16RegClass);
216 addRegisterClass(MVT::i32, &X86::GR32RegClass);
217 if (Subtarget->is64Bit())
218 addRegisterClass(MVT::i64, &X86::GR64RegClass);
220 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
222 // We don't accept any truncstore of integer registers.
223 setTruncStoreAction(MVT::i64, MVT::i32, Expand);
224 setTruncStoreAction(MVT::i64, MVT::i16, Expand);
225 setTruncStoreAction(MVT::i64, MVT::i8 , Expand);
226 setTruncStoreAction(MVT::i32, MVT::i16, Expand);
227 setTruncStoreAction(MVT::i32, MVT::i8 , Expand);
228 setTruncStoreAction(MVT::i16, MVT::i8, Expand);
230 // SETOEQ and SETUNE require checking two conditions.
231 setCondCodeAction(ISD::SETOEQ, MVT::f32, Expand);
232 setCondCodeAction(ISD::SETOEQ, MVT::f64, Expand);
233 setCondCodeAction(ISD::SETOEQ, MVT::f80, Expand);
234 setCondCodeAction(ISD::SETUNE, MVT::f32, Expand);
235 setCondCodeAction(ISD::SETUNE, MVT::f64, Expand);
236 setCondCodeAction(ISD::SETUNE, MVT::f80, Expand);
238 // Promote all UINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have this
240 setOperationAction(ISD::UINT_TO_FP , MVT::i1 , Promote);
241 setOperationAction(ISD::UINT_TO_FP , MVT::i8 , Promote);
242 setOperationAction(ISD::UINT_TO_FP , MVT::i16 , Promote);
244 if (Subtarget->is64Bit()) {
245 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote);
246 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
247 } else if (!TM.Options.UseSoftFloat) {
248 // We have an algorithm for SSE2->double, and we turn this into a
249 // 64-bit FILD followed by conditional FADD for other targets.
250 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
251 // We have an algorithm for SSE2, and we turn this into a 64-bit
252 // FILD for other targets.
253 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Custom);
256 // Promote i1/i8 SINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have
258 setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote);
259 setOperationAction(ISD::SINT_TO_FP , MVT::i8 , Promote);
261 if (!TM.Options.UseSoftFloat) {
262 // SSE has no i16 to fp conversion, only i32
263 if (X86ScalarSSEf32) {
264 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
265 // f32 and f64 cases are Legal, f80 case is not
266 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
268 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Custom);
269 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
272 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
273 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Promote);
276 // In 32-bit mode these are custom lowered. In 64-bit mode F32 and F64
277 // are Legal, f80 is custom lowered.
278 setOperationAction(ISD::FP_TO_SINT , MVT::i64 , Custom);
279 setOperationAction(ISD::SINT_TO_FP , MVT::i64 , Custom);
281 // Promote i1/i8 FP_TO_SINT to larger FP_TO_SINTS's, as X86 doesn't have
283 setOperationAction(ISD::FP_TO_SINT , MVT::i1 , Promote);
284 setOperationAction(ISD::FP_TO_SINT , MVT::i8 , Promote);
286 if (X86ScalarSSEf32) {
287 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Promote);
288 // f32 and f64 cases are Legal, f80 case is not
289 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
291 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Custom);
292 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
295 // Handle FP_TO_UINT by promoting the destination to a larger signed
297 setOperationAction(ISD::FP_TO_UINT , MVT::i1 , Promote);
298 setOperationAction(ISD::FP_TO_UINT , MVT::i8 , Promote);
299 setOperationAction(ISD::FP_TO_UINT , MVT::i16 , Promote);
301 if (Subtarget->is64Bit()) {
302 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Expand);
303 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote);
304 } else if (!TM.Options.UseSoftFloat) {
305 // Since AVX is a superset of SSE3, only check for SSE here.
306 if (Subtarget->hasSSE1() && !Subtarget->hasSSE3())
307 // Expand FP_TO_UINT into a select.
308 // FIXME: We would like to use a Custom expander here eventually to do
309 // the optimal thing for SSE vs. the default expansion in the legalizer.
310 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Expand);
312 // With SSE3 we can use fisttpll to convert to a signed i64; without
313 // SSE, we're stuck with a fistpll.
314 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Custom);
317 if (isTargetFTOL()) {
318 // Use the _ftol2 runtime function, which has a pseudo-instruction
319 // to handle its weird calling convention.
320 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Custom);
323 // TODO: when we have SSE, these could be more efficient, by using movd/movq.
324 if (!X86ScalarSSEf64) {
325 setOperationAction(ISD::BITCAST , MVT::f32 , Expand);
326 setOperationAction(ISD::BITCAST , MVT::i32 , Expand);
327 if (Subtarget->is64Bit()) {
328 setOperationAction(ISD::BITCAST , MVT::f64 , Expand);
329 // Without SSE, i64->f64 goes through memory.
330 setOperationAction(ISD::BITCAST , MVT::i64 , Expand);
334 // Scalar integer divide and remainder are lowered to use operations that
335 // produce two results, to match the available instructions. This exposes
336 // the two-result form to trivial CSE, which is able to combine x/y and x%y
337 // into a single instruction.
339 // Scalar integer multiply-high is also lowered to use two-result
340 // operations, to match the available instructions. However, plain multiply
341 // (low) operations are left as Legal, as there are single-result
342 // instructions for this in x86. Using the two-result multiply instructions
343 // when both high and low results are needed must be arranged by dagcombine.
344 for (unsigned i = 0; i != array_lengthof(IntVTs); ++i) {
346 setOperationAction(ISD::MULHS, VT, Expand);
347 setOperationAction(ISD::MULHU, VT, Expand);
348 setOperationAction(ISD::SDIV, VT, Expand);
349 setOperationAction(ISD::UDIV, VT, Expand);
350 setOperationAction(ISD::SREM, VT, Expand);
351 setOperationAction(ISD::UREM, VT, Expand);
353 // Add/Sub overflow ops with MVT::Glues are lowered to EFLAGS dependences.
354 setOperationAction(ISD::ADDC, VT, Custom);
355 setOperationAction(ISD::ADDE, VT, Custom);
356 setOperationAction(ISD::SUBC, VT, Custom);
357 setOperationAction(ISD::SUBE, VT, Custom);
360 setOperationAction(ISD::BR_JT , MVT::Other, Expand);
361 setOperationAction(ISD::BRCOND , MVT::Other, Custom);
362 setOperationAction(ISD::BR_CC , MVT::Other, Expand);
363 setOperationAction(ISD::SELECT_CC , MVT::Other, Expand);
364 if (Subtarget->is64Bit())
365 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal);
366 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Legal);
367 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Legal);
368 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
369 setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand);
370 setOperationAction(ISD::FREM , MVT::f32 , Expand);
371 setOperationAction(ISD::FREM , MVT::f64 , Expand);
372 setOperationAction(ISD::FREM , MVT::f80 , Expand);
373 setOperationAction(ISD::FLT_ROUNDS_ , MVT::i32 , Custom);
375 // Promote the i8 variants and force them on up to i32 which has a shorter
377 setOperationAction(ISD::CTTZ , MVT::i8 , Promote);
378 AddPromotedToType (ISD::CTTZ , MVT::i8 , MVT::i32);
379 setOperationAction(ISD::CTTZ_ZERO_UNDEF , MVT::i8 , Promote);
380 AddPromotedToType (ISD::CTTZ_ZERO_UNDEF , MVT::i8 , MVT::i32);
381 if (Subtarget->hasBMI()) {
382 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i16 , Expand);
383 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32 , Expand);
384 if (Subtarget->is64Bit())
385 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand);
387 setOperationAction(ISD::CTTZ , MVT::i16 , Custom);
388 setOperationAction(ISD::CTTZ , MVT::i32 , Custom);
389 if (Subtarget->is64Bit())
390 setOperationAction(ISD::CTTZ , MVT::i64 , Custom);
393 if (Subtarget->hasLZCNT()) {
394 // When promoting the i8 variants, force them to i32 for a shorter
396 setOperationAction(ISD::CTLZ , MVT::i8 , Promote);
397 AddPromotedToType (ISD::CTLZ , MVT::i8 , MVT::i32);
398 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Promote);
399 AddPromotedToType (ISD::CTLZ_ZERO_UNDEF, MVT::i8 , MVT::i32);
400 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Expand);
401 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Expand);
402 if (Subtarget->is64Bit())
403 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Expand);
405 setOperationAction(ISD::CTLZ , MVT::i8 , Custom);
406 setOperationAction(ISD::CTLZ , MVT::i16 , Custom);
407 setOperationAction(ISD::CTLZ , MVT::i32 , Custom);
408 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Custom);
409 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Custom);
410 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Custom);
411 if (Subtarget->is64Bit()) {
412 setOperationAction(ISD::CTLZ , MVT::i64 , Custom);
413 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Custom);
417 if (Subtarget->hasPOPCNT()) {
418 setOperationAction(ISD::CTPOP , MVT::i8 , Promote);
420 setOperationAction(ISD::CTPOP , MVT::i8 , Expand);
421 setOperationAction(ISD::CTPOP , MVT::i16 , Expand);
422 setOperationAction(ISD::CTPOP , MVT::i32 , Expand);
423 if (Subtarget->is64Bit())
424 setOperationAction(ISD::CTPOP , MVT::i64 , Expand);
427 setOperationAction(ISD::READCYCLECOUNTER , MVT::i64 , Custom);
428 setOperationAction(ISD::BSWAP , MVT::i16 , Expand);
430 // These should be promoted to a larger select which is supported.
431 setOperationAction(ISD::SELECT , MVT::i1 , Promote);
432 // X86 wants to expand cmov itself.
433 setOperationAction(ISD::SELECT , MVT::i8 , Custom);
434 setOperationAction(ISD::SELECT , MVT::i16 , Custom);
435 setOperationAction(ISD::SELECT , MVT::i32 , Custom);
436 setOperationAction(ISD::SELECT , MVT::f32 , Custom);
437 setOperationAction(ISD::SELECT , MVT::f64 , Custom);
438 setOperationAction(ISD::SELECT , MVT::f80 , Custom);
439 setOperationAction(ISD::SETCC , MVT::i8 , Custom);
440 setOperationAction(ISD::SETCC , MVT::i16 , Custom);
441 setOperationAction(ISD::SETCC , MVT::i32 , Custom);
442 setOperationAction(ISD::SETCC , MVT::f32 , Custom);
443 setOperationAction(ISD::SETCC , MVT::f64 , Custom);
444 setOperationAction(ISD::SETCC , MVT::f80 , Custom);
445 if (Subtarget->is64Bit()) {
446 setOperationAction(ISD::SELECT , MVT::i64 , Custom);
447 setOperationAction(ISD::SETCC , MVT::i64 , Custom);
449 setOperationAction(ISD::EH_RETURN , MVT::Other, Custom);
452 setOperationAction(ISD::ConstantPool , MVT::i32 , Custom);
453 setOperationAction(ISD::JumpTable , MVT::i32 , Custom);
454 setOperationAction(ISD::GlobalAddress , MVT::i32 , Custom);
455 setOperationAction(ISD::GlobalTLSAddress, MVT::i32 , Custom);
456 if (Subtarget->is64Bit())
457 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
458 setOperationAction(ISD::ExternalSymbol , MVT::i32 , Custom);
459 setOperationAction(ISD::BlockAddress , MVT::i32 , Custom);
460 if (Subtarget->is64Bit()) {
461 setOperationAction(ISD::ConstantPool , MVT::i64 , Custom);
462 setOperationAction(ISD::JumpTable , MVT::i64 , Custom);
463 setOperationAction(ISD::GlobalAddress , MVT::i64 , Custom);
464 setOperationAction(ISD::ExternalSymbol, MVT::i64 , Custom);
465 setOperationAction(ISD::BlockAddress , MVT::i64 , Custom);
467 // 64-bit addm sub, shl, sra, srl (iff 32-bit x86)
468 setOperationAction(ISD::SHL_PARTS , MVT::i32 , Custom);
469 setOperationAction(ISD::SRA_PARTS , MVT::i32 , Custom);
470 setOperationAction(ISD::SRL_PARTS , MVT::i32 , Custom);
471 if (Subtarget->is64Bit()) {
472 setOperationAction(ISD::SHL_PARTS , MVT::i64 , Custom);
473 setOperationAction(ISD::SRA_PARTS , MVT::i64 , Custom);
474 setOperationAction(ISD::SRL_PARTS , MVT::i64 , Custom);
477 if (Subtarget->hasSSE1())
478 setOperationAction(ISD::PREFETCH , MVT::Other, Legal);
480 setOperationAction(ISD::MEMBARRIER , MVT::Other, Custom);
481 setOperationAction(ISD::ATOMIC_FENCE , MVT::Other, Custom);
483 // On X86 and X86-64, atomic operations are lowered to locked instructions.
484 // Locked instructions, in turn, have implicit fence semantics (all memory
485 // operations are flushed before issuing the locked instruction, and they
486 // are not buffered), so we can fold away the common pattern of
487 // fence-atomic-fence.
488 setShouldFoldAtomicFences(true);
490 // Expand certain atomics
491 for (unsigned i = 0; i != array_lengthof(IntVTs); ++i) {
493 setOperationAction(ISD::ATOMIC_CMP_SWAP, VT, Custom);
494 setOperationAction(ISD::ATOMIC_LOAD_SUB, VT, Custom);
495 setOperationAction(ISD::ATOMIC_STORE, VT, Custom);
498 if (!Subtarget->is64Bit()) {
499 setOperationAction(ISD::ATOMIC_LOAD, MVT::i64, Custom);
500 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i64, Custom);
501 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i64, Custom);
502 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i64, Custom);
503 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i64, Custom);
504 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i64, Custom);
505 setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i64, Custom);
506 setOperationAction(ISD::ATOMIC_SWAP, MVT::i64, Custom);
509 if (Subtarget->hasCmpxchg16b()) {
510 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i128, Custom);
513 // FIXME - use subtarget debug flags
514 if (!Subtarget->isTargetDarwin() &&
515 !Subtarget->isTargetELF() &&
516 !Subtarget->isTargetCygMing()) {
517 setOperationAction(ISD::EH_LABEL, MVT::Other, Expand);
520 setOperationAction(ISD::EXCEPTIONADDR, MVT::i64, Expand);
521 setOperationAction(ISD::EHSELECTION, MVT::i64, Expand);
522 setOperationAction(ISD::EXCEPTIONADDR, MVT::i32, Expand);
523 setOperationAction(ISD::EHSELECTION, MVT::i32, Expand);
524 if (Subtarget->is64Bit()) {
525 setExceptionPointerRegister(X86::RAX);
526 setExceptionSelectorRegister(X86::RDX);
528 setExceptionPointerRegister(X86::EAX);
529 setExceptionSelectorRegister(X86::EDX);
531 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i32, Custom);
532 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i64, Custom);
534 setOperationAction(ISD::INIT_TRAMPOLINE, MVT::Other, Custom);
535 setOperationAction(ISD::ADJUST_TRAMPOLINE, MVT::Other, Custom);
537 setOperationAction(ISD::TRAP, MVT::Other, Legal);
539 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
540 setOperationAction(ISD::VASTART , MVT::Other, Custom);
541 setOperationAction(ISD::VAEND , MVT::Other, Expand);
542 if (Subtarget->is64Bit()) {
543 setOperationAction(ISD::VAARG , MVT::Other, Custom);
544 setOperationAction(ISD::VACOPY , MVT::Other, Custom);
546 setOperationAction(ISD::VAARG , MVT::Other, Expand);
547 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
550 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
551 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
553 if (Subtarget->isTargetCOFF() && !Subtarget->isTargetEnvMacho())
554 setOperationAction(ISD::DYNAMIC_STACKALLOC, Subtarget->is64Bit() ?
555 MVT::i64 : MVT::i32, Custom);
556 else if (TM.Options.EnableSegmentedStacks)
557 setOperationAction(ISD::DYNAMIC_STACKALLOC, Subtarget->is64Bit() ?
558 MVT::i64 : MVT::i32, Custom);
560 setOperationAction(ISD::DYNAMIC_STACKALLOC, Subtarget->is64Bit() ?
561 MVT::i64 : MVT::i32, Expand);
563 if (!TM.Options.UseSoftFloat && X86ScalarSSEf64) {
564 // f32 and f64 use SSE.
565 // Set up the FP register classes.
566 addRegisterClass(MVT::f32, &X86::FR32RegClass);
567 addRegisterClass(MVT::f64, &X86::FR64RegClass);
569 // Use ANDPD to simulate FABS.
570 setOperationAction(ISD::FABS , MVT::f64, Custom);
571 setOperationAction(ISD::FABS , MVT::f32, Custom);
573 // Use XORP to simulate FNEG.
574 setOperationAction(ISD::FNEG , MVT::f64, Custom);
575 setOperationAction(ISD::FNEG , MVT::f32, Custom);
577 // Use ANDPD and ORPD to simulate FCOPYSIGN.
578 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
579 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
581 // Lower this to FGETSIGNx86 plus an AND.
582 setOperationAction(ISD::FGETSIGN, MVT::i64, Custom);
583 setOperationAction(ISD::FGETSIGN, MVT::i32, Custom);
585 // We don't support sin/cos/fmod
586 setOperationAction(ISD::FSIN , MVT::f64, Expand);
587 setOperationAction(ISD::FCOS , MVT::f64, Expand);
588 setOperationAction(ISD::FSIN , MVT::f32, Expand);
589 setOperationAction(ISD::FCOS , MVT::f32, Expand);
591 // Expand FP immediates into loads from the stack, except for the special
593 addLegalFPImmediate(APFloat(+0.0)); // xorpd
594 addLegalFPImmediate(APFloat(+0.0f)); // xorps
595 } else if (!TM.Options.UseSoftFloat && X86ScalarSSEf32) {
596 // Use SSE for f32, x87 for f64.
597 // Set up the FP register classes.
598 addRegisterClass(MVT::f32, &X86::FR32RegClass);
599 addRegisterClass(MVT::f64, &X86::RFP64RegClass);
601 // Use ANDPS to simulate FABS.
602 setOperationAction(ISD::FABS , MVT::f32, Custom);
604 // Use XORP to simulate FNEG.
605 setOperationAction(ISD::FNEG , MVT::f32, Custom);
607 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
609 // Use ANDPS and ORPS to simulate FCOPYSIGN.
610 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
611 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
613 // We don't support sin/cos/fmod
614 setOperationAction(ISD::FSIN , MVT::f32, Expand);
615 setOperationAction(ISD::FCOS , MVT::f32, Expand);
617 // Special cases we handle for FP constants.
618 addLegalFPImmediate(APFloat(+0.0f)); // xorps
619 addLegalFPImmediate(APFloat(+0.0)); // FLD0
620 addLegalFPImmediate(APFloat(+1.0)); // FLD1
621 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
622 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
624 if (!TM.Options.UnsafeFPMath) {
625 setOperationAction(ISD::FSIN , MVT::f64 , Expand);
626 setOperationAction(ISD::FCOS , MVT::f64 , Expand);
628 } else if (!TM.Options.UseSoftFloat) {
629 // f32 and f64 in x87.
630 // Set up the FP register classes.
631 addRegisterClass(MVT::f64, &X86::RFP64RegClass);
632 addRegisterClass(MVT::f32, &X86::RFP32RegClass);
634 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
635 setOperationAction(ISD::UNDEF, MVT::f32, Expand);
636 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
637 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
639 if (!TM.Options.UnsafeFPMath) {
640 setOperationAction(ISD::FSIN , MVT::f64 , Expand);
641 setOperationAction(ISD::FCOS , MVT::f64 , Expand);
643 addLegalFPImmediate(APFloat(+0.0)); // FLD0
644 addLegalFPImmediate(APFloat(+1.0)); // FLD1
645 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
646 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
647 addLegalFPImmediate(APFloat(+0.0f)); // FLD0
648 addLegalFPImmediate(APFloat(+1.0f)); // FLD1
649 addLegalFPImmediate(APFloat(-0.0f)); // FLD0/FCHS
650 addLegalFPImmediate(APFloat(-1.0f)); // FLD1/FCHS
653 // We don't support FMA.
654 setOperationAction(ISD::FMA, MVT::f64, Expand);
655 setOperationAction(ISD::FMA, MVT::f32, Expand);
657 // Long double always uses X87.
658 if (!TM.Options.UseSoftFloat) {
659 addRegisterClass(MVT::f80, &X86::RFP80RegClass);
660 setOperationAction(ISD::UNDEF, MVT::f80, Expand);
661 setOperationAction(ISD::FCOPYSIGN, MVT::f80, Expand);
663 APFloat TmpFlt = APFloat::getZero(APFloat::x87DoubleExtended);
664 addLegalFPImmediate(TmpFlt); // FLD0
666 addLegalFPImmediate(TmpFlt); // FLD0/FCHS
669 APFloat TmpFlt2(+1.0);
670 TmpFlt2.convert(APFloat::x87DoubleExtended, APFloat::rmNearestTiesToEven,
672 addLegalFPImmediate(TmpFlt2); // FLD1
673 TmpFlt2.changeSign();
674 addLegalFPImmediate(TmpFlt2); // FLD1/FCHS
677 if (!TM.Options.UnsafeFPMath) {
678 setOperationAction(ISD::FSIN , MVT::f80 , Expand);
679 setOperationAction(ISD::FCOS , MVT::f80 , Expand);
682 setOperationAction(ISD::FFLOOR, MVT::f80, Expand);
683 setOperationAction(ISD::FCEIL, MVT::f80, Expand);
684 setOperationAction(ISD::FTRUNC, MVT::f80, Expand);
685 setOperationAction(ISD::FRINT, MVT::f80, Expand);
686 setOperationAction(ISD::FNEARBYINT, MVT::f80, Expand);
687 setOperationAction(ISD::FMA, MVT::f80, Expand);
690 // Always use a library call for pow.
691 setOperationAction(ISD::FPOW , MVT::f32 , Expand);
692 setOperationAction(ISD::FPOW , MVT::f64 , Expand);
693 setOperationAction(ISD::FPOW , MVT::f80 , Expand);
695 setOperationAction(ISD::FLOG, MVT::f80, Expand);
696 setOperationAction(ISD::FLOG2, MVT::f80, Expand);
697 setOperationAction(ISD::FLOG10, MVT::f80, Expand);
698 setOperationAction(ISD::FEXP, MVT::f80, Expand);
699 setOperationAction(ISD::FEXP2, MVT::f80, Expand);
701 // First set operation action for all vector types to either promote
702 // (for widening) or expand (for scalarization). Then we will selectively
703 // turn on ones that can be effectively codegen'd.
704 for (int VT = MVT::FIRST_VECTOR_VALUETYPE;
705 VT <= MVT::LAST_VECTOR_VALUETYPE; ++VT) {
706 setOperationAction(ISD::ADD , (MVT::SimpleValueType)VT, Expand);
707 setOperationAction(ISD::SUB , (MVT::SimpleValueType)VT, Expand);
708 setOperationAction(ISD::FADD, (MVT::SimpleValueType)VT, Expand);
709 setOperationAction(ISD::FNEG, (MVT::SimpleValueType)VT, Expand);
710 setOperationAction(ISD::FSUB, (MVT::SimpleValueType)VT, Expand);
711 setOperationAction(ISD::MUL , (MVT::SimpleValueType)VT, Expand);
712 setOperationAction(ISD::FMUL, (MVT::SimpleValueType)VT, Expand);
713 setOperationAction(ISD::SDIV, (MVT::SimpleValueType)VT, Expand);
714 setOperationAction(ISD::UDIV, (MVT::SimpleValueType)VT, Expand);
715 setOperationAction(ISD::FDIV, (MVT::SimpleValueType)VT, Expand);
716 setOperationAction(ISD::SREM, (MVT::SimpleValueType)VT, Expand);
717 setOperationAction(ISD::UREM, (MVT::SimpleValueType)VT, Expand);
718 setOperationAction(ISD::LOAD, (MVT::SimpleValueType)VT, Expand);
719 setOperationAction(ISD::VECTOR_SHUFFLE, (MVT::SimpleValueType)VT, Expand);
720 setOperationAction(ISD::EXTRACT_VECTOR_ELT,(MVT::SimpleValueType)VT,Expand);
721 setOperationAction(ISD::INSERT_VECTOR_ELT,(MVT::SimpleValueType)VT, Expand);
722 setOperationAction(ISD::EXTRACT_SUBVECTOR,(MVT::SimpleValueType)VT,Expand);
723 setOperationAction(ISD::INSERT_SUBVECTOR,(MVT::SimpleValueType)VT,Expand);
724 setOperationAction(ISD::FABS, (MVT::SimpleValueType)VT, Expand);
725 setOperationAction(ISD::FSIN, (MVT::SimpleValueType)VT, Expand);
726 setOperationAction(ISD::FCOS, (MVT::SimpleValueType)VT, Expand);
727 setOperationAction(ISD::FREM, (MVT::SimpleValueType)VT, Expand);
728 setOperationAction(ISD::FPOWI, (MVT::SimpleValueType)VT, Expand);
729 setOperationAction(ISD::FSQRT, (MVT::SimpleValueType)VT, Expand);
730 setOperationAction(ISD::FCOPYSIGN, (MVT::SimpleValueType)VT, Expand);
731 setOperationAction(ISD::SMUL_LOHI, (MVT::SimpleValueType)VT, Expand);
732 setOperationAction(ISD::UMUL_LOHI, (MVT::SimpleValueType)VT, Expand);
733 setOperationAction(ISD::SDIVREM, (MVT::SimpleValueType)VT, Expand);
734 setOperationAction(ISD::UDIVREM, (MVT::SimpleValueType)VT, Expand);
735 setOperationAction(ISD::FPOW, (MVT::SimpleValueType)VT, Expand);
736 setOperationAction(ISD::CTPOP, (MVT::SimpleValueType)VT, Expand);
737 setOperationAction(ISD::CTTZ, (MVT::SimpleValueType)VT, Expand);
738 setOperationAction(ISD::CTTZ_ZERO_UNDEF, (MVT::SimpleValueType)VT, Expand);
739 setOperationAction(ISD::CTLZ, (MVT::SimpleValueType)VT, Expand);
740 setOperationAction(ISD::CTLZ_ZERO_UNDEF, (MVT::SimpleValueType)VT, Expand);
741 setOperationAction(ISD::SHL, (MVT::SimpleValueType)VT, Expand);
742 setOperationAction(ISD::SRA, (MVT::SimpleValueType)VT, Expand);
743 setOperationAction(ISD::SRL, (MVT::SimpleValueType)VT, Expand);
744 setOperationAction(ISD::ROTL, (MVT::SimpleValueType)VT, Expand);
745 setOperationAction(ISD::ROTR, (MVT::SimpleValueType)VT, Expand);
746 setOperationAction(ISD::BSWAP, (MVT::SimpleValueType)VT, Expand);
747 setOperationAction(ISD::SETCC, (MVT::SimpleValueType)VT, Expand);
748 setOperationAction(ISD::FLOG, (MVT::SimpleValueType)VT, Expand);
749 setOperationAction(ISD::FLOG2, (MVT::SimpleValueType)VT, Expand);
750 setOperationAction(ISD::FLOG10, (MVT::SimpleValueType)VT, Expand);
751 setOperationAction(ISD::FEXP, (MVT::SimpleValueType)VT, Expand);
752 setOperationAction(ISD::FEXP2, (MVT::SimpleValueType)VT, Expand);
753 setOperationAction(ISD::FP_TO_UINT, (MVT::SimpleValueType)VT, Expand);
754 setOperationAction(ISD::FP_TO_SINT, (MVT::SimpleValueType)VT, Expand);
755 setOperationAction(ISD::UINT_TO_FP, (MVT::SimpleValueType)VT, Expand);
756 setOperationAction(ISD::SINT_TO_FP, (MVT::SimpleValueType)VT, Expand);
757 setOperationAction(ISD::SIGN_EXTEND_INREG, (MVT::SimpleValueType)VT,Expand);
758 setOperationAction(ISD::TRUNCATE, (MVT::SimpleValueType)VT, Expand);
759 setOperationAction(ISD::SIGN_EXTEND, (MVT::SimpleValueType)VT, Expand);
760 setOperationAction(ISD::ZERO_EXTEND, (MVT::SimpleValueType)VT, Expand);
761 setOperationAction(ISD::ANY_EXTEND, (MVT::SimpleValueType)VT, Expand);
762 setOperationAction(ISD::VSELECT, (MVT::SimpleValueType)VT, Expand);
763 for (int InnerVT = MVT::FIRST_VECTOR_VALUETYPE;
764 InnerVT <= MVT::LAST_VECTOR_VALUETYPE; ++InnerVT)
765 setTruncStoreAction((MVT::SimpleValueType)VT,
766 (MVT::SimpleValueType)InnerVT, Expand);
767 setLoadExtAction(ISD::SEXTLOAD, (MVT::SimpleValueType)VT, Expand);
768 setLoadExtAction(ISD::ZEXTLOAD, (MVT::SimpleValueType)VT, Expand);
769 setLoadExtAction(ISD::EXTLOAD, (MVT::SimpleValueType)VT, Expand);
772 // FIXME: In order to prevent SSE instructions being expanded to MMX ones
773 // with -msoft-float, disable use of MMX as well.
774 if (!TM.Options.UseSoftFloat && Subtarget->hasMMX()) {
775 addRegisterClass(MVT::x86mmx, &X86::VR64RegClass);
776 // No operations on x86mmx supported, everything uses intrinsics.
779 // MMX-sized vectors (other than x86mmx) are expected to be expanded
780 // into smaller operations.
781 setOperationAction(ISD::MULHS, MVT::v8i8, Expand);
782 setOperationAction(ISD::MULHS, MVT::v4i16, Expand);
783 setOperationAction(ISD::MULHS, MVT::v2i32, Expand);
784 setOperationAction(ISD::MULHS, MVT::v1i64, Expand);
785 setOperationAction(ISD::AND, MVT::v8i8, Expand);
786 setOperationAction(ISD::AND, MVT::v4i16, Expand);
787 setOperationAction(ISD::AND, MVT::v2i32, Expand);
788 setOperationAction(ISD::AND, MVT::v1i64, Expand);
789 setOperationAction(ISD::OR, MVT::v8i8, Expand);
790 setOperationAction(ISD::OR, MVT::v4i16, Expand);
791 setOperationAction(ISD::OR, MVT::v2i32, Expand);
792 setOperationAction(ISD::OR, MVT::v1i64, Expand);
793 setOperationAction(ISD::XOR, MVT::v8i8, Expand);
794 setOperationAction(ISD::XOR, MVT::v4i16, Expand);
795 setOperationAction(ISD::XOR, MVT::v2i32, Expand);
796 setOperationAction(ISD::XOR, MVT::v1i64, Expand);
797 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i8, Expand);
798 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i16, Expand);
799 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2i32, Expand);
800 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v1i64, Expand);
801 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v1i64, Expand);
802 setOperationAction(ISD::SELECT, MVT::v8i8, Expand);
803 setOperationAction(ISD::SELECT, MVT::v4i16, Expand);
804 setOperationAction(ISD::SELECT, MVT::v2i32, Expand);
805 setOperationAction(ISD::SELECT, MVT::v1i64, Expand);
806 setOperationAction(ISD::BITCAST, MVT::v8i8, Expand);
807 setOperationAction(ISD::BITCAST, MVT::v4i16, Expand);
808 setOperationAction(ISD::BITCAST, MVT::v2i32, Expand);
809 setOperationAction(ISD::BITCAST, MVT::v1i64, Expand);
811 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE1()) {
812 addRegisterClass(MVT::v4f32, &X86::VR128RegClass);
814 setOperationAction(ISD::FADD, MVT::v4f32, Legal);
815 setOperationAction(ISD::FSUB, MVT::v4f32, Legal);
816 setOperationAction(ISD::FMUL, MVT::v4f32, Legal);
817 setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
818 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal);
819 setOperationAction(ISD::FNEG, MVT::v4f32, Custom);
820 setOperationAction(ISD::LOAD, MVT::v4f32, Legal);
821 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
822 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f32, Custom);
823 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
824 setOperationAction(ISD::SELECT, MVT::v4f32, Custom);
825 setOperationAction(ISD::SETCC, MVT::v4f32, Custom);
828 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE2()) {
829 addRegisterClass(MVT::v2f64, &X86::VR128RegClass);
831 // FIXME: Unfortunately -soft-float and -no-implicit-float means XMM
832 // registers cannot be used even for integer operations.
833 addRegisterClass(MVT::v16i8, &X86::VR128RegClass);
834 addRegisterClass(MVT::v8i16, &X86::VR128RegClass);
835 addRegisterClass(MVT::v4i32, &X86::VR128RegClass);
836 addRegisterClass(MVT::v2i64, &X86::VR128RegClass);
838 setOperationAction(ISD::ADD, MVT::v16i8, Legal);
839 setOperationAction(ISD::ADD, MVT::v8i16, Legal);
840 setOperationAction(ISD::ADD, MVT::v4i32, Legal);
841 setOperationAction(ISD::ADD, MVT::v2i64, Legal);
842 setOperationAction(ISD::MUL, MVT::v2i64, Custom);
843 setOperationAction(ISD::SUB, MVT::v16i8, Legal);
844 setOperationAction(ISD::SUB, MVT::v8i16, Legal);
845 setOperationAction(ISD::SUB, MVT::v4i32, Legal);
846 setOperationAction(ISD::SUB, MVT::v2i64, Legal);
847 setOperationAction(ISD::MUL, MVT::v8i16, Legal);
848 setOperationAction(ISD::FADD, MVT::v2f64, Legal);
849 setOperationAction(ISD::FSUB, MVT::v2f64, Legal);
850 setOperationAction(ISD::FMUL, MVT::v2f64, Legal);
851 setOperationAction(ISD::FDIV, MVT::v2f64, Legal);
852 setOperationAction(ISD::FSQRT, MVT::v2f64, Legal);
853 setOperationAction(ISD::FNEG, MVT::v2f64, Custom);
855 setOperationAction(ISD::SETCC, MVT::v2i64, Custom);
856 setOperationAction(ISD::SETCC, MVT::v16i8, Custom);
857 setOperationAction(ISD::SETCC, MVT::v8i16, Custom);
858 setOperationAction(ISD::SETCC, MVT::v4i32, Custom);
860 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Custom);
861 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Custom);
862 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
863 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
864 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
866 setOperationAction(ISD::CONCAT_VECTORS, MVT::v2f64, Custom);
867 setOperationAction(ISD::CONCAT_VECTORS, MVT::v2i64, Custom);
868 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i8, Custom);
869 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i16, Custom);
870 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4i32, Custom);
872 // Custom lower build_vector, vector_shuffle, and extract_vector_elt.
873 for (int i = MVT::v16i8; i != MVT::v2i64; ++i) {
874 EVT VT = (MVT::SimpleValueType)i;
875 // Do not attempt to custom lower non-power-of-2 vectors
876 if (!isPowerOf2_32(VT.getVectorNumElements()))
878 // Do not attempt to custom lower non-128-bit vectors
879 if (!VT.is128BitVector())
881 setOperationAction(ISD::BUILD_VECTOR,
882 VT.getSimpleVT().SimpleTy, Custom);
883 setOperationAction(ISD::VECTOR_SHUFFLE,
884 VT.getSimpleVT().SimpleTy, Custom);
885 setOperationAction(ISD::EXTRACT_VECTOR_ELT,
886 VT.getSimpleVT().SimpleTy, Custom);
889 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f64, Custom);
890 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i64, Custom);
891 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Custom);
892 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Custom);
893 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f64, Custom);
894 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Custom);
896 if (Subtarget->is64Bit()) {
897 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
898 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
901 // Promote v16i8, v8i16, v4i32 load, select, and, or, xor to v2i64.
902 for (int i = MVT::v16i8; i != MVT::v2i64; ++i) {
903 MVT::SimpleValueType SVT = (MVT::SimpleValueType)i;
906 // Do not attempt to promote non-128-bit vectors
907 if (!VT.is128BitVector())
910 setOperationAction(ISD::AND, SVT, Promote);
911 AddPromotedToType (ISD::AND, SVT, MVT::v2i64);
912 setOperationAction(ISD::OR, SVT, Promote);
913 AddPromotedToType (ISD::OR, SVT, MVT::v2i64);
914 setOperationAction(ISD::XOR, SVT, Promote);
915 AddPromotedToType (ISD::XOR, SVT, MVT::v2i64);
916 setOperationAction(ISD::LOAD, SVT, Promote);
917 AddPromotedToType (ISD::LOAD, SVT, MVT::v2i64);
918 setOperationAction(ISD::SELECT, SVT, Promote);
919 AddPromotedToType (ISD::SELECT, SVT, MVT::v2i64);
922 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
924 // Custom lower v2i64 and v2f64 selects.
925 setOperationAction(ISD::LOAD, MVT::v2f64, Legal);
926 setOperationAction(ISD::LOAD, MVT::v2i64, Legal);
927 setOperationAction(ISD::SELECT, MVT::v2f64, Custom);
928 setOperationAction(ISD::SELECT, MVT::v2i64, Custom);
930 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal);
931 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal);
934 if (Subtarget->hasSSE41()) {
935 setOperationAction(ISD::FFLOOR, MVT::f32, Legal);
936 setOperationAction(ISD::FCEIL, MVT::f32, Legal);
937 setOperationAction(ISD::FTRUNC, MVT::f32, Legal);
938 setOperationAction(ISD::FRINT, MVT::f32, Legal);
939 setOperationAction(ISD::FNEARBYINT, MVT::f32, Legal);
940 setOperationAction(ISD::FFLOOR, MVT::f64, Legal);
941 setOperationAction(ISD::FCEIL, MVT::f64, Legal);
942 setOperationAction(ISD::FTRUNC, MVT::f64, Legal);
943 setOperationAction(ISD::FRINT, MVT::f64, Legal);
944 setOperationAction(ISD::FNEARBYINT, MVT::f64, Legal);
946 // FIXME: Do we need to handle scalar-to-vector here?
947 setOperationAction(ISD::MUL, MVT::v4i32, Legal);
949 setOperationAction(ISD::VSELECT, MVT::v2f64, Legal);
950 setOperationAction(ISD::VSELECT, MVT::v2i64, Legal);
951 setOperationAction(ISD::VSELECT, MVT::v16i8, Legal);
952 setOperationAction(ISD::VSELECT, MVT::v4i32, Legal);
953 setOperationAction(ISD::VSELECT, MVT::v4f32, Legal);
955 // i8 and i16 vectors are custom , because the source register and source
956 // source memory operand types are not the same width. f32 vectors are
957 // custom since the immediate controlling the insert encodes additional
959 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i8, Custom);
960 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
961 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
962 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
964 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i8, Custom);
965 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i16, Custom);
966 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i32, Custom);
967 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
969 // FIXME: these should be Legal but thats only for the case where
970 // the index is constant. For now custom expand to deal with that.
971 if (Subtarget->is64Bit()) {
972 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
973 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
977 if (Subtarget->hasSSE2()) {
978 setOperationAction(ISD::SRL, MVT::v8i16, Custom);
979 setOperationAction(ISD::SRL, MVT::v16i8, Custom);
981 setOperationAction(ISD::SHL, MVT::v8i16, Custom);
982 setOperationAction(ISD::SHL, MVT::v16i8, Custom);
984 setOperationAction(ISD::SRA, MVT::v8i16, Custom);
985 setOperationAction(ISD::SRA, MVT::v16i8, Custom);
987 if (Subtarget->hasAVX2()) {
988 setOperationAction(ISD::SRL, MVT::v2i64, Legal);
989 setOperationAction(ISD::SRL, MVT::v4i32, Legal);
991 setOperationAction(ISD::SHL, MVT::v2i64, Legal);
992 setOperationAction(ISD::SHL, MVT::v4i32, Legal);
994 setOperationAction(ISD::SRA, MVT::v4i32, Legal);
996 setOperationAction(ISD::SRL, MVT::v2i64, Custom);
997 setOperationAction(ISD::SRL, MVT::v4i32, Custom);
999 setOperationAction(ISD::SHL, MVT::v2i64, Custom);
1000 setOperationAction(ISD::SHL, MVT::v4i32, Custom);
1002 setOperationAction(ISD::SRA, MVT::v4i32, Custom);
1006 if (Subtarget->hasSSE42())
1007 setOperationAction(ISD::SETCC, MVT::v2i64, Custom);
1009 if (!TM.Options.UseSoftFloat && Subtarget->hasAVX()) {
1010 addRegisterClass(MVT::v32i8, &X86::VR256RegClass);
1011 addRegisterClass(MVT::v16i16, &X86::VR256RegClass);
1012 addRegisterClass(MVT::v8i32, &X86::VR256RegClass);
1013 addRegisterClass(MVT::v8f32, &X86::VR256RegClass);
1014 addRegisterClass(MVT::v4i64, &X86::VR256RegClass);
1015 addRegisterClass(MVT::v4f64, &X86::VR256RegClass);
1017 setOperationAction(ISD::LOAD, MVT::v8f32, Legal);
1018 setOperationAction(ISD::LOAD, MVT::v4f64, Legal);
1019 setOperationAction(ISD::LOAD, MVT::v4i64, Legal);
1021 setOperationAction(ISD::FADD, MVT::v8f32, Legal);
1022 setOperationAction(ISD::FSUB, MVT::v8f32, Legal);
1023 setOperationAction(ISD::FMUL, MVT::v8f32, Legal);
1024 setOperationAction(ISD::FDIV, MVT::v8f32, Legal);
1025 setOperationAction(ISD::FSQRT, MVT::v8f32, Legal);
1026 setOperationAction(ISD::FNEG, MVT::v8f32, Custom);
1028 setOperationAction(ISD::FADD, MVT::v4f64, Legal);
1029 setOperationAction(ISD::FSUB, MVT::v4f64, Legal);
1030 setOperationAction(ISD::FMUL, MVT::v4f64, Legal);
1031 setOperationAction(ISD::FDIV, MVT::v4f64, Legal);
1032 setOperationAction(ISD::FSQRT, MVT::v4f64, Legal);
1033 setOperationAction(ISD::FNEG, MVT::v4f64, Custom);
1035 setOperationAction(ISD::FP_TO_SINT, MVT::v8i32, Legal);
1036 setOperationAction(ISD::SINT_TO_FP, MVT::v8i32, Legal);
1037 setOperationAction(ISD::FP_ROUND, MVT::v4f32, Legal);
1039 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4f64, Custom);
1040 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4i64, Custom);
1041 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8f32, Custom);
1042 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i32, Custom);
1043 setOperationAction(ISD::CONCAT_VECTORS, MVT::v32i8, Custom);
1044 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i16, Custom);
1046 setOperationAction(ISD::SRL, MVT::v16i16, Custom);
1047 setOperationAction(ISD::SRL, MVT::v32i8, Custom);
1049 setOperationAction(ISD::SHL, MVT::v16i16, Custom);
1050 setOperationAction(ISD::SHL, MVT::v32i8, Custom);
1052 setOperationAction(ISD::SRA, MVT::v16i16, Custom);
1053 setOperationAction(ISD::SRA, MVT::v32i8, Custom);
1055 setOperationAction(ISD::SETCC, MVT::v32i8, Custom);
1056 setOperationAction(ISD::SETCC, MVT::v16i16, Custom);
1057 setOperationAction(ISD::SETCC, MVT::v8i32, Custom);
1058 setOperationAction(ISD::SETCC, MVT::v4i64, Custom);
1060 setOperationAction(ISD::SELECT, MVT::v4f64, Custom);
1061 setOperationAction(ISD::SELECT, MVT::v4i64, Custom);
1062 setOperationAction(ISD::SELECT, MVT::v8f32, Custom);
1064 setOperationAction(ISD::VSELECT, MVT::v4f64, Legal);
1065 setOperationAction(ISD::VSELECT, MVT::v4i64, Legal);
1066 setOperationAction(ISD::VSELECT, MVT::v8i32, Legal);
1067 setOperationAction(ISD::VSELECT, MVT::v8f32, Legal);
1069 if (Subtarget->hasAVX2()) {
1070 setOperationAction(ISD::ADD, MVT::v4i64, Legal);
1071 setOperationAction(ISD::ADD, MVT::v8i32, Legal);
1072 setOperationAction(ISD::ADD, MVT::v16i16, Legal);
1073 setOperationAction(ISD::ADD, MVT::v32i8, Legal);
1075 setOperationAction(ISD::SUB, MVT::v4i64, Legal);
1076 setOperationAction(ISD::SUB, MVT::v8i32, Legal);
1077 setOperationAction(ISD::SUB, MVT::v16i16, Legal);
1078 setOperationAction(ISD::SUB, MVT::v32i8, Legal);
1080 setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1081 setOperationAction(ISD::MUL, MVT::v8i32, Legal);
1082 setOperationAction(ISD::MUL, MVT::v16i16, Legal);
1083 // Don't lower v32i8 because there is no 128-bit byte mul
1085 setOperationAction(ISD::VSELECT, MVT::v32i8, Legal);
1087 setOperationAction(ISD::SRL, MVT::v4i64, Legal);
1088 setOperationAction(ISD::SRL, MVT::v8i32, Legal);
1090 setOperationAction(ISD::SHL, MVT::v4i64, Legal);
1091 setOperationAction(ISD::SHL, MVT::v8i32, Legal);
1093 setOperationAction(ISD::SRA, MVT::v8i32, Legal);
1095 setOperationAction(ISD::ADD, MVT::v4i64, Custom);
1096 setOperationAction(ISD::ADD, MVT::v8i32, Custom);
1097 setOperationAction(ISD::ADD, MVT::v16i16, Custom);
1098 setOperationAction(ISD::ADD, MVT::v32i8, Custom);
1100 setOperationAction(ISD::SUB, MVT::v4i64, Custom);
1101 setOperationAction(ISD::SUB, MVT::v8i32, Custom);
1102 setOperationAction(ISD::SUB, MVT::v16i16, Custom);
1103 setOperationAction(ISD::SUB, MVT::v32i8, Custom);
1105 setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1106 setOperationAction(ISD::MUL, MVT::v8i32, Custom);
1107 setOperationAction(ISD::MUL, MVT::v16i16, Custom);
1108 // Don't lower v32i8 because there is no 128-bit byte mul
1110 setOperationAction(ISD::SRL, MVT::v4i64, Custom);
1111 setOperationAction(ISD::SRL, MVT::v8i32, Custom);
1113 setOperationAction(ISD::SHL, MVT::v4i64, Custom);
1114 setOperationAction(ISD::SHL, MVT::v8i32, Custom);
1116 setOperationAction(ISD::SRA, MVT::v8i32, Custom);
1119 // Custom lower several nodes for 256-bit types.
1120 for (int i = MVT::FIRST_VECTOR_VALUETYPE;
1121 i <= MVT::LAST_VECTOR_VALUETYPE; ++i) {
1122 MVT::SimpleValueType SVT = (MVT::SimpleValueType)i;
1125 // Extract subvector is special because the value type
1126 // (result) is 128-bit but the source is 256-bit wide.
1127 if (VT.is128BitVector())
1128 setOperationAction(ISD::EXTRACT_SUBVECTOR, SVT, Custom);
1130 // Do not attempt to custom lower other non-256-bit vectors
1131 if (!VT.is256BitVector())
1134 setOperationAction(ISD::BUILD_VECTOR, SVT, Custom);
1135 setOperationAction(ISD::VECTOR_SHUFFLE, SVT, Custom);
1136 setOperationAction(ISD::INSERT_VECTOR_ELT, SVT, Custom);
1137 setOperationAction(ISD::EXTRACT_VECTOR_ELT, SVT, Custom);
1138 setOperationAction(ISD::SCALAR_TO_VECTOR, SVT, Custom);
1139 setOperationAction(ISD::INSERT_SUBVECTOR, SVT, Custom);
1142 // Promote v32i8, v16i16, v8i32 select, and, or, xor to v4i64.
1143 for (int i = MVT::v32i8; i != MVT::v4i64; ++i) {
1144 MVT::SimpleValueType SVT = (MVT::SimpleValueType)i;
1147 // Do not attempt to promote non-256-bit vectors
1148 if (!VT.is256BitVector())
1151 setOperationAction(ISD::AND, SVT, Promote);
1152 AddPromotedToType (ISD::AND, SVT, MVT::v4i64);
1153 setOperationAction(ISD::OR, SVT, Promote);
1154 AddPromotedToType (ISD::OR, SVT, MVT::v4i64);
1155 setOperationAction(ISD::XOR, SVT, Promote);
1156 AddPromotedToType (ISD::XOR, SVT, MVT::v4i64);
1157 setOperationAction(ISD::LOAD, SVT, Promote);
1158 AddPromotedToType (ISD::LOAD, SVT, MVT::v4i64);
1159 setOperationAction(ISD::SELECT, SVT, Promote);
1160 AddPromotedToType (ISD::SELECT, SVT, MVT::v4i64);
1164 // SIGN_EXTEND_INREGs are evaluated by the extend type. Handle the expansion
1165 // of this type with custom code.
1166 for (int VT = MVT::FIRST_VECTOR_VALUETYPE;
1167 VT != MVT::LAST_VECTOR_VALUETYPE; VT++) {
1168 setOperationAction(ISD::SIGN_EXTEND_INREG, (MVT::SimpleValueType)VT,
1172 // We want to custom lower some of our intrinsics.
1173 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
1176 // Only custom-lower 64-bit SADDO and friends on 64-bit because we don't
1177 // handle type legalization for these operations here.
1179 // FIXME: We really should do custom legalization for addition and
1180 // subtraction on x86-32 once PR3203 is fixed. We really can't do much better
1181 // than generic legalization for 64-bit multiplication-with-overflow, though.
1182 for (unsigned i = 0, e = 3+Subtarget->is64Bit(); i != e; ++i) {
1183 // Add/Sub/Mul with overflow operations are custom lowered.
1185 setOperationAction(ISD::SADDO, VT, Custom);
1186 setOperationAction(ISD::UADDO, VT, Custom);
1187 setOperationAction(ISD::SSUBO, VT, Custom);
1188 setOperationAction(ISD::USUBO, VT, Custom);
1189 setOperationAction(ISD::SMULO, VT, Custom);
1190 setOperationAction(ISD::UMULO, VT, Custom);
1193 // There are no 8-bit 3-address imul/mul instructions
1194 setOperationAction(ISD::SMULO, MVT::i8, Expand);
1195 setOperationAction(ISD::UMULO, MVT::i8, Expand);
1197 if (!Subtarget->is64Bit()) {
1198 // These libcalls are not available in 32-bit.
1199 setLibcallName(RTLIB::SHL_I128, 0);
1200 setLibcallName(RTLIB::SRL_I128, 0);
1201 setLibcallName(RTLIB::SRA_I128, 0);
1204 // We have target-specific dag combine patterns for the following nodes:
1205 setTargetDAGCombine(ISD::VECTOR_SHUFFLE);
1206 setTargetDAGCombine(ISD::EXTRACT_VECTOR_ELT);
1207 setTargetDAGCombine(ISD::VSELECT);
1208 setTargetDAGCombine(ISD::SELECT);
1209 setTargetDAGCombine(ISD::SHL);
1210 setTargetDAGCombine(ISD::SRA);
1211 setTargetDAGCombine(ISD::SRL);
1212 setTargetDAGCombine(ISD::OR);
1213 setTargetDAGCombine(ISD::AND);
1214 setTargetDAGCombine(ISD::ADD);
1215 setTargetDAGCombine(ISD::FADD);
1216 setTargetDAGCombine(ISD::FSUB);
1217 setTargetDAGCombine(ISD::SUB);
1218 setTargetDAGCombine(ISD::LOAD);
1219 setTargetDAGCombine(ISD::STORE);
1220 setTargetDAGCombine(ISD::ZERO_EXTEND);
1221 setTargetDAGCombine(ISD::ANY_EXTEND);
1222 setTargetDAGCombine(ISD::SIGN_EXTEND);
1223 setTargetDAGCombine(ISD::TRUNCATE);
1224 setTargetDAGCombine(ISD::UINT_TO_FP);
1225 setTargetDAGCombine(ISD::SINT_TO_FP);
1226 setTargetDAGCombine(ISD::SETCC);
1227 setTargetDAGCombine(ISD::FP_TO_SINT);
1228 if (Subtarget->is64Bit())
1229 setTargetDAGCombine(ISD::MUL);
1230 if (Subtarget->hasBMI())
1231 setTargetDAGCombine(ISD::XOR);
1233 computeRegisterProperties();
1235 // On Darwin, -Os means optimize for size without hurting performance,
1236 // do not reduce the limit.
1237 maxStoresPerMemset = 16; // For @llvm.memset -> sequence of stores
1238 maxStoresPerMemsetOptSize = Subtarget->isTargetDarwin() ? 16 : 8;
1239 maxStoresPerMemcpy = 8; // For @llvm.memcpy -> sequence of stores
1240 maxStoresPerMemcpyOptSize = Subtarget->isTargetDarwin() ? 8 : 4;
1241 maxStoresPerMemmove = 8; // For @llvm.memmove -> sequence of stores
1242 maxStoresPerMemmoveOptSize = Subtarget->isTargetDarwin() ? 8 : 4;
1243 setPrefLoopAlignment(4); // 2^4 bytes.
1244 benefitFromCodePlacementOpt = true;
1246 // Predictable cmov don't hurt on atom because it's in-order.
1247 predictableSelectIsExpensive = !Subtarget->isAtom();
1249 setPrefFunctionAlignment(4); // 2^4 bytes.
1253 EVT X86TargetLowering::getSetCCResultType(EVT VT) const {
1254 if (!VT.isVector()) return MVT::i8;
1255 return VT.changeVectorElementTypeToInteger();
1259 /// getMaxByValAlign - Helper for getByValTypeAlignment to determine
1260 /// the desired ByVal argument alignment.
1261 static void getMaxByValAlign(Type *Ty, unsigned &MaxAlign) {
1264 if (VectorType *VTy = dyn_cast<VectorType>(Ty)) {
1265 if (VTy->getBitWidth() == 128)
1267 } else if (ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
1268 unsigned EltAlign = 0;
1269 getMaxByValAlign(ATy->getElementType(), EltAlign);
1270 if (EltAlign > MaxAlign)
1271 MaxAlign = EltAlign;
1272 } else if (StructType *STy = dyn_cast<StructType>(Ty)) {
1273 for (unsigned i = 0, e = STy->getNumElements(); i != e; ++i) {
1274 unsigned EltAlign = 0;
1275 getMaxByValAlign(STy->getElementType(i), EltAlign);
1276 if (EltAlign > MaxAlign)
1277 MaxAlign = EltAlign;
1284 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
1285 /// function arguments in the caller parameter area. For X86, aggregates
1286 /// that contain SSE vectors are placed at 16-byte boundaries while the rest
1287 /// are at 4-byte boundaries.
1288 unsigned X86TargetLowering::getByValTypeAlignment(Type *Ty) const {
1289 if (Subtarget->is64Bit()) {
1290 // Max of 8 and alignment of type.
1291 unsigned TyAlign = TD->getABITypeAlignment(Ty);
1298 if (Subtarget->hasSSE1())
1299 getMaxByValAlign(Ty, Align);
1303 /// getOptimalMemOpType - Returns the target specific optimal type for load
1304 /// and store operations as a result of memset, memcpy, and memmove
1305 /// lowering. If DstAlign is zero that means it's safe to destination
1306 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
1307 /// means there isn't a need to check it against alignment requirement,
1308 /// probably because the source does not need to be loaded. If
1309 /// 'IsZeroVal' is true, that means it's safe to return a
1310 /// non-scalar-integer type, e.g. empty string source, constant, or loaded
1311 /// from memory. 'MemcpyStrSrc' indicates whether the memcpy source is
1312 /// constant so it does not need to be loaded.
1313 /// It returns EVT::Other if the type should be determined using generic
1314 /// target-independent logic.
1316 X86TargetLowering::getOptimalMemOpType(uint64_t Size,
1317 unsigned DstAlign, unsigned SrcAlign,
1320 MachineFunction &MF) const {
1321 // FIXME: This turns off use of xmm stores for memset/memcpy on targets like
1322 // linux. This is because the stack realignment code can't handle certain
1323 // cases like PR2962. This should be removed when PR2962 is fixed.
1324 const Function *F = MF.getFunction();
1326 !F->hasFnAttr(Attribute::NoImplicitFloat)) {
1328 (Subtarget->isUnalignedMemAccessFast() ||
1329 ((DstAlign == 0 || DstAlign >= 16) &&
1330 (SrcAlign == 0 || SrcAlign >= 16))) &&
1331 Subtarget->getStackAlignment() >= 16) {
1332 if (Subtarget->getStackAlignment() >= 32) {
1333 if (Subtarget->hasAVX2())
1335 if (Subtarget->hasAVX())
1338 if (Subtarget->hasSSE2())
1340 if (Subtarget->hasSSE1())
1342 } else if (!MemcpyStrSrc && Size >= 8 &&
1343 !Subtarget->is64Bit() &&
1344 Subtarget->getStackAlignment() >= 8 &&
1345 Subtarget->hasSSE2()) {
1346 // Do not use f64 to lower memcpy if source is string constant. It's
1347 // better to use i32 to avoid the loads.
1351 if (Subtarget->is64Bit() && Size >= 8)
1356 /// getJumpTableEncoding - Return the entry encoding for a jump table in the
1357 /// current function. The returned value is a member of the
1358 /// MachineJumpTableInfo::JTEntryKind enum.
1359 unsigned X86TargetLowering::getJumpTableEncoding() const {
1360 // In GOT pic mode, each entry in the jump table is emitted as a @GOTOFF
1362 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1363 Subtarget->isPICStyleGOT())
1364 return MachineJumpTableInfo::EK_Custom32;
1366 // Otherwise, use the normal jump table encoding heuristics.
1367 return TargetLowering::getJumpTableEncoding();
1371 X86TargetLowering::LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI,
1372 const MachineBasicBlock *MBB,
1373 unsigned uid,MCContext &Ctx) const{
1374 assert(getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1375 Subtarget->isPICStyleGOT());
1376 // In 32-bit ELF systems, our jump table entries are formed with @GOTOFF
1378 return MCSymbolRefExpr::Create(MBB->getSymbol(),
1379 MCSymbolRefExpr::VK_GOTOFF, Ctx);
1382 /// getPICJumpTableRelocaBase - Returns relocation base for the given PIC
1384 SDValue X86TargetLowering::getPICJumpTableRelocBase(SDValue Table,
1385 SelectionDAG &DAG) const {
1386 if (!Subtarget->is64Bit())
1387 // This doesn't have DebugLoc associated with it, but is not really the
1388 // same as a Register.
1389 return DAG.getNode(X86ISD::GlobalBaseReg, DebugLoc(), getPointerTy());
1393 /// getPICJumpTableRelocBaseExpr - This returns the relocation base for the
1394 /// given PIC jumptable, the same as getPICJumpTableRelocBase, but as an
1396 const MCExpr *X86TargetLowering::
1397 getPICJumpTableRelocBaseExpr(const MachineFunction *MF, unsigned JTI,
1398 MCContext &Ctx) const {
1399 // X86-64 uses RIP relative addressing based on the jump table label.
1400 if (Subtarget->isPICStyleRIPRel())
1401 return TargetLowering::getPICJumpTableRelocBaseExpr(MF, JTI, Ctx);
1403 // Otherwise, the reference is relative to the PIC base.
1404 return MCSymbolRefExpr::Create(MF->getPICBaseSymbol(), Ctx);
1407 // FIXME: Why this routine is here? Move to RegInfo!
1408 std::pair<const TargetRegisterClass*, uint8_t>
1409 X86TargetLowering::findRepresentativeClass(EVT VT) const{
1410 const TargetRegisterClass *RRC = 0;
1412 switch (VT.getSimpleVT().SimpleTy) {
1414 return TargetLowering::findRepresentativeClass(VT);
1415 case MVT::i8: case MVT::i16: case MVT::i32: case MVT::i64:
1416 RRC = Subtarget->is64Bit() ?
1417 (const TargetRegisterClass*)&X86::GR64RegClass :
1418 (const TargetRegisterClass*)&X86::GR32RegClass;
1421 RRC = &X86::VR64RegClass;
1423 case MVT::f32: case MVT::f64:
1424 case MVT::v16i8: case MVT::v8i16: case MVT::v4i32: case MVT::v2i64:
1425 case MVT::v4f32: case MVT::v2f64:
1426 case MVT::v32i8: case MVT::v8i32: case MVT::v4i64: case MVT::v8f32:
1428 RRC = &X86::VR128RegClass;
1431 return std::make_pair(RRC, Cost);
1434 bool X86TargetLowering::getStackCookieLocation(unsigned &AddressSpace,
1435 unsigned &Offset) const {
1436 if (!Subtarget->isTargetLinux())
1439 if (Subtarget->is64Bit()) {
1440 // %fs:0x28, unless we're using a Kernel code model, in which case it's %gs:
1442 if (getTargetMachine().getCodeModel() == CodeModel::Kernel)
1455 //===----------------------------------------------------------------------===//
1456 // Return Value Calling Convention Implementation
1457 //===----------------------------------------------------------------------===//
1459 #include "X86GenCallingConv.inc"
1462 X86TargetLowering::CanLowerReturn(CallingConv::ID CallConv,
1463 MachineFunction &MF, bool isVarArg,
1464 const SmallVectorImpl<ISD::OutputArg> &Outs,
1465 LLVMContext &Context) const {
1466 SmallVector<CCValAssign, 16> RVLocs;
1467 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(),
1469 return CCInfo.CheckReturn(Outs, RetCC_X86);
1473 X86TargetLowering::LowerReturn(SDValue Chain,
1474 CallingConv::ID CallConv, bool isVarArg,
1475 const SmallVectorImpl<ISD::OutputArg> &Outs,
1476 const SmallVectorImpl<SDValue> &OutVals,
1477 DebugLoc dl, SelectionDAG &DAG) const {
1478 MachineFunction &MF = DAG.getMachineFunction();
1479 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1481 SmallVector<CCValAssign, 16> RVLocs;
1482 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(),
1483 RVLocs, *DAG.getContext());
1484 CCInfo.AnalyzeReturn(Outs, RetCC_X86);
1486 // Add the regs to the liveout set for the function.
1487 MachineRegisterInfo &MRI = DAG.getMachineFunction().getRegInfo();
1488 for (unsigned i = 0; i != RVLocs.size(); ++i)
1489 if (RVLocs[i].isRegLoc() && !MRI.isLiveOut(RVLocs[i].getLocReg()))
1490 MRI.addLiveOut(RVLocs[i].getLocReg());
1494 SmallVector<SDValue, 6> RetOps;
1495 RetOps.push_back(Chain); // Operand #0 = Chain (updated below)
1496 // Operand #1 = Bytes To Pop
1497 RetOps.push_back(DAG.getTargetConstant(FuncInfo->getBytesToPopOnReturn(),
1500 // Copy the result values into the output registers.
1501 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1502 CCValAssign &VA = RVLocs[i];
1503 assert(VA.isRegLoc() && "Can only return in registers!");
1504 SDValue ValToCopy = OutVals[i];
1505 EVT ValVT = ValToCopy.getValueType();
1507 // If this is x86-64, and we disabled SSE, we can't return FP values,
1508 // or SSE or MMX vectors.
1509 if ((ValVT == MVT::f32 || ValVT == MVT::f64 ||
1510 VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) &&
1511 (Subtarget->is64Bit() && !Subtarget->hasSSE1())) {
1512 report_fatal_error("SSE register return with SSE disabled");
1514 // Likewise we can't return F64 values with SSE1 only. gcc does so, but
1515 // llvm-gcc has never done it right and no one has noticed, so this
1516 // should be OK for now.
1517 if (ValVT == MVT::f64 &&
1518 (Subtarget->is64Bit() && !Subtarget->hasSSE2()))
1519 report_fatal_error("SSE2 register return with SSE2 disabled");
1521 // Returns in ST0/ST1 are handled specially: these are pushed as operands to
1522 // the RET instruction and handled by the FP Stackifier.
1523 if (VA.getLocReg() == X86::ST0 ||
1524 VA.getLocReg() == X86::ST1) {
1525 // If this is a copy from an xmm register to ST(0), use an FPExtend to
1526 // change the value to the FP stack register class.
1527 if (isScalarFPTypeInSSEReg(VA.getValVT()))
1528 ValToCopy = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f80, ValToCopy);
1529 RetOps.push_back(ValToCopy);
1530 // Don't emit a copytoreg.
1534 // 64-bit vector (MMX) values are returned in XMM0 / XMM1 except for v1i64
1535 // which is returned in RAX / RDX.
1536 if (Subtarget->is64Bit()) {
1537 if (ValVT == MVT::x86mmx) {
1538 if (VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) {
1539 ValToCopy = DAG.getNode(ISD::BITCAST, dl, MVT::i64, ValToCopy);
1540 ValToCopy = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
1542 // If we don't have SSE2 available, convert to v4f32 so the generated
1543 // register is legal.
1544 if (!Subtarget->hasSSE2())
1545 ValToCopy = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32,ValToCopy);
1550 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), ValToCopy, Flag);
1551 Flag = Chain.getValue(1);
1554 // The x86-64 ABI for returning structs by value requires that we copy
1555 // the sret argument into %rax for the return. We saved the argument into
1556 // a virtual register in the entry block, so now we copy the value out
1558 if (Subtarget->is64Bit() &&
1559 DAG.getMachineFunction().getFunction()->hasStructRetAttr()) {
1560 MachineFunction &MF = DAG.getMachineFunction();
1561 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1562 unsigned Reg = FuncInfo->getSRetReturnReg();
1564 "SRetReturnReg should have been set in LowerFormalArguments().");
1565 SDValue Val = DAG.getCopyFromReg(Chain, dl, Reg, getPointerTy());
1567 Chain = DAG.getCopyToReg(Chain, dl, X86::RAX, Val, Flag);
1568 Flag = Chain.getValue(1);
1570 // RAX now acts like a return value.
1571 MRI.addLiveOut(X86::RAX);
1574 RetOps[0] = Chain; // Update chain.
1576 // Add the flag if we have it.
1578 RetOps.push_back(Flag);
1580 return DAG.getNode(X86ISD::RET_FLAG, dl,
1581 MVT::Other, &RetOps[0], RetOps.size());
1584 bool X86TargetLowering::isUsedByReturnOnly(SDNode *N, SDValue &Chain) const {
1585 if (N->getNumValues() != 1)
1587 if (!N->hasNUsesOfValue(1, 0))
1590 SDValue TCChain = Chain;
1591 SDNode *Copy = *N->use_begin();
1592 if (Copy->getOpcode() == ISD::CopyToReg) {
1593 // If the copy has a glue operand, we conservatively assume it isn't safe to
1594 // perform a tail call.
1595 if (Copy->getOperand(Copy->getNumOperands()-1).getValueType() == MVT::Glue)
1597 TCChain = Copy->getOperand(0);
1598 } else if (Copy->getOpcode() != ISD::FP_EXTEND)
1601 bool HasRet = false;
1602 for (SDNode::use_iterator UI = Copy->use_begin(), UE = Copy->use_end();
1604 if (UI->getOpcode() != X86ISD::RET_FLAG)
1617 X86TargetLowering::getTypeForExtArgOrReturn(LLVMContext &Context, EVT VT,
1618 ISD::NodeType ExtendKind) const {
1620 // TODO: Is this also valid on 32-bit?
1621 if (Subtarget->is64Bit() && VT == MVT::i1 && ExtendKind == ISD::ZERO_EXTEND)
1622 ReturnMVT = MVT::i8;
1624 ReturnMVT = MVT::i32;
1626 EVT MinVT = getRegisterType(Context, ReturnMVT);
1627 return VT.bitsLT(MinVT) ? MinVT : VT;
1630 /// LowerCallResult - Lower the result values of a call into the
1631 /// appropriate copies out of appropriate physical registers.
1634 X86TargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
1635 CallingConv::ID CallConv, bool isVarArg,
1636 const SmallVectorImpl<ISD::InputArg> &Ins,
1637 DebugLoc dl, SelectionDAG &DAG,
1638 SmallVectorImpl<SDValue> &InVals) const {
1640 // Assign locations to each value returned by this call.
1641 SmallVector<CCValAssign, 16> RVLocs;
1642 bool Is64Bit = Subtarget->is64Bit();
1643 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
1644 getTargetMachine(), RVLocs, *DAG.getContext());
1645 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
1647 // Copy all of the result registers out of their specified physreg.
1648 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1649 CCValAssign &VA = RVLocs[i];
1650 EVT CopyVT = VA.getValVT();
1652 // If this is x86-64, and we disabled SSE, we can't return FP values
1653 if ((CopyVT == MVT::f32 || CopyVT == MVT::f64) &&
1654 ((Is64Bit || Ins[i].Flags.isInReg()) && !Subtarget->hasSSE1())) {
1655 report_fatal_error("SSE register return with SSE disabled");
1660 // If this is a call to a function that returns an fp value on the floating
1661 // point stack, we must guarantee the the value is popped from the stack, so
1662 // a CopyFromReg is not good enough - the copy instruction may be eliminated
1663 // if the return value is not used. We use the FpPOP_RETVAL instruction
1665 if (VA.getLocReg() == X86::ST0 || VA.getLocReg() == X86::ST1) {
1666 // If we prefer to use the value in xmm registers, copy it out as f80 and
1667 // use a truncate to move it from fp stack reg to xmm reg.
1668 if (isScalarFPTypeInSSEReg(VA.getValVT())) CopyVT = MVT::f80;
1669 SDValue Ops[] = { Chain, InFlag };
1670 Chain = SDValue(DAG.getMachineNode(X86::FpPOP_RETVAL, dl, CopyVT,
1671 MVT::Other, MVT::Glue, Ops, 2), 1);
1672 Val = Chain.getValue(0);
1674 // Round the f80 to the right size, which also moves it to the appropriate
1676 if (CopyVT != VA.getValVT())
1677 Val = DAG.getNode(ISD::FP_ROUND, dl, VA.getValVT(), Val,
1678 // This truncation won't change the value.
1679 DAG.getIntPtrConstant(1));
1681 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(),
1682 CopyVT, InFlag).getValue(1);
1683 Val = Chain.getValue(0);
1685 InFlag = Chain.getValue(2);
1686 InVals.push_back(Val);
1693 //===----------------------------------------------------------------------===//
1694 // C & StdCall & Fast Calling Convention implementation
1695 //===----------------------------------------------------------------------===//
1696 // StdCall calling convention seems to be standard for many Windows' API
1697 // routines and around. It differs from C calling convention just a little:
1698 // callee should clean up the stack, not caller. Symbols should be also
1699 // decorated in some fancy way :) It doesn't support any vector arguments.
1700 // For info on fast calling convention see Fast Calling Convention (tail call)
1701 // implementation LowerX86_32FastCCCallTo.
1703 /// CallIsStructReturn - Determines whether a call uses struct return
1705 static bool CallIsStructReturn(const SmallVectorImpl<ISD::OutputArg> &Outs) {
1709 return Outs[0].Flags.isSRet();
1712 /// ArgsAreStructReturn - Determines whether a function uses struct
1713 /// return semantics.
1715 ArgsAreStructReturn(const SmallVectorImpl<ISD::InputArg> &Ins) {
1719 return Ins[0].Flags.isSRet();
1722 /// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified
1723 /// by "Src" to address "Dst" with size and alignment information specified by
1724 /// the specific parameter attribute. The copy will be passed as a byval
1725 /// function parameter.
1727 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
1728 ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
1730 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32);
1732 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
1733 /*isVolatile*/false, /*AlwaysInline=*/true,
1734 MachinePointerInfo(), MachinePointerInfo());
1737 /// IsTailCallConvention - Return true if the calling convention is one that
1738 /// supports tail call optimization.
1739 static bool IsTailCallConvention(CallingConv::ID CC) {
1740 return (CC == CallingConv::Fast || CC == CallingConv::GHC);
1743 bool X86TargetLowering::mayBeEmittedAsTailCall(CallInst *CI) const {
1744 if (!CI->isTailCall() || getTargetMachine().Options.DisableTailCalls)
1748 CallingConv::ID CalleeCC = CS.getCallingConv();
1749 if (!IsTailCallConvention(CalleeCC) && CalleeCC != CallingConv::C)
1755 /// FuncIsMadeTailCallSafe - Return true if the function is being made into
1756 /// a tailcall target by changing its ABI.
1757 static bool FuncIsMadeTailCallSafe(CallingConv::ID CC,
1758 bool GuaranteedTailCallOpt) {
1759 return GuaranteedTailCallOpt && IsTailCallConvention(CC);
1763 X86TargetLowering::LowerMemArgument(SDValue Chain,
1764 CallingConv::ID CallConv,
1765 const SmallVectorImpl<ISD::InputArg> &Ins,
1766 DebugLoc dl, SelectionDAG &DAG,
1767 const CCValAssign &VA,
1768 MachineFrameInfo *MFI,
1770 // Create the nodes corresponding to a load from this parameter slot.
1771 ISD::ArgFlagsTy Flags = Ins[i].Flags;
1772 bool AlwaysUseMutable = FuncIsMadeTailCallSafe(CallConv,
1773 getTargetMachine().Options.GuaranteedTailCallOpt);
1774 bool isImmutable = !AlwaysUseMutable && !Flags.isByVal();
1777 // If value is passed by pointer we have address passed instead of the value
1779 if (VA.getLocInfo() == CCValAssign::Indirect)
1780 ValVT = VA.getLocVT();
1782 ValVT = VA.getValVT();
1784 // FIXME: For now, all byval parameter objects are marked mutable. This can be
1785 // changed with more analysis.
1786 // In case of tail call optimization mark all arguments mutable. Since they
1787 // could be overwritten by lowering of arguments in case of a tail call.
1788 if (Flags.isByVal()) {
1789 unsigned Bytes = Flags.getByValSize();
1790 if (Bytes == 0) Bytes = 1; // Don't create zero-sized stack objects.
1791 int FI = MFI->CreateFixedObject(Bytes, VA.getLocMemOffset(), isImmutable);
1792 return DAG.getFrameIndex(FI, getPointerTy());
1794 int FI = MFI->CreateFixedObject(ValVT.getSizeInBits()/8,
1795 VA.getLocMemOffset(), isImmutable);
1796 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
1797 return DAG.getLoad(ValVT, dl, Chain, FIN,
1798 MachinePointerInfo::getFixedStack(FI),
1799 false, false, false, 0);
1804 X86TargetLowering::LowerFormalArguments(SDValue Chain,
1805 CallingConv::ID CallConv,
1807 const SmallVectorImpl<ISD::InputArg> &Ins,
1810 SmallVectorImpl<SDValue> &InVals)
1812 MachineFunction &MF = DAG.getMachineFunction();
1813 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1815 const Function* Fn = MF.getFunction();
1816 if (Fn->hasExternalLinkage() &&
1817 Subtarget->isTargetCygMing() &&
1818 Fn->getName() == "main")
1819 FuncInfo->setForceFramePointer(true);
1821 MachineFrameInfo *MFI = MF.getFrameInfo();
1822 bool Is64Bit = Subtarget->is64Bit();
1823 bool IsWindows = Subtarget->isTargetWindows();
1824 bool IsWin64 = Subtarget->isTargetWin64();
1826 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
1827 "Var args not supported with calling convention fastcc or ghc");
1829 // Assign locations to all of the incoming arguments.
1830 SmallVector<CCValAssign, 16> ArgLocs;
1831 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(),
1832 ArgLocs, *DAG.getContext());
1834 // Allocate shadow area for Win64
1836 CCInfo.AllocateStack(32, 8);
1839 CCInfo.AnalyzeFormalArguments(Ins, CC_X86);
1841 unsigned LastVal = ~0U;
1843 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1844 CCValAssign &VA = ArgLocs[i];
1845 // TODO: If an arg is passed in two places (e.g. reg and stack), skip later
1847 assert(VA.getValNo() != LastVal &&
1848 "Don't support value assigned to multiple locs yet");
1850 LastVal = VA.getValNo();
1852 if (VA.isRegLoc()) {
1853 EVT RegVT = VA.getLocVT();
1854 const TargetRegisterClass *RC;
1855 if (RegVT == MVT::i32)
1856 RC = &X86::GR32RegClass;
1857 else if (Is64Bit && RegVT == MVT::i64)
1858 RC = &X86::GR64RegClass;
1859 else if (RegVT == MVT::f32)
1860 RC = &X86::FR32RegClass;
1861 else if (RegVT == MVT::f64)
1862 RC = &X86::FR64RegClass;
1863 else if (RegVT.isVector() && RegVT.getSizeInBits() == 256)
1864 RC = &X86::VR256RegClass;
1865 else if (RegVT.isVector() && RegVT.getSizeInBits() == 128)
1866 RC = &X86::VR128RegClass;
1867 else if (RegVT == MVT::x86mmx)
1868 RC = &X86::VR64RegClass;
1870 llvm_unreachable("Unknown argument type!");
1872 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
1873 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
1875 // If this is an 8 or 16-bit value, it is really passed promoted to 32
1876 // bits. Insert an assert[sz]ext to capture this, then truncate to the
1878 if (VA.getLocInfo() == CCValAssign::SExt)
1879 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
1880 DAG.getValueType(VA.getValVT()));
1881 else if (VA.getLocInfo() == CCValAssign::ZExt)
1882 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
1883 DAG.getValueType(VA.getValVT()));
1884 else if (VA.getLocInfo() == CCValAssign::BCvt)
1885 ArgValue = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), ArgValue);
1887 if (VA.isExtInLoc()) {
1888 // Handle MMX values passed in XMM regs.
1889 if (RegVT.isVector()) {
1890 ArgValue = DAG.getNode(X86ISD::MOVDQ2Q, dl, VA.getValVT(),
1893 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
1896 assert(VA.isMemLoc());
1897 ArgValue = LowerMemArgument(Chain, CallConv, Ins, dl, DAG, VA, MFI, i);
1900 // If value is passed via pointer - do a load.
1901 if (VA.getLocInfo() == CCValAssign::Indirect)
1902 ArgValue = DAG.getLoad(VA.getValVT(), dl, Chain, ArgValue,
1903 MachinePointerInfo(), false, false, false, 0);
1905 InVals.push_back(ArgValue);
1908 // The x86-64 ABI for returning structs by value requires that we copy
1909 // the sret argument into %rax for the return. Save the argument into
1910 // a virtual register so that we can access it from the return points.
1911 if (Is64Bit && MF.getFunction()->hasStructRetAttr()) {
1912 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1913 unsigned Reg = FuncInfo->getSRetReturnReg();
1915 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(MVT::i64));
1916 FuncInfo->setSRetReturnReg(Reg);
1918 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, InVals[0]);
1919 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain);
1922 unsigned StackSize = CCInfo.getNextStackOffset();
1923 // Align stack specially for tail calls.
1924 if (FuncIsMadeTailCallSafe(CallConv,
1925 MF.getTarget().Options.GuaranteedTailCallOpt))
1926 StackSize = GetAlignedArgumentStackSize(StackSize, DAG);
1928 // If the function takes variable number of arguments, make a frame index for
1929 // the start of the first vararg value... for expansion of llvm.va_start.
1931 if (Is64Bit || (CallConv != CallingConv::X86_FastCall &&
1932 CallConv != CallingConv::X86_ThisCall)) {
1933 FuncInfo->setVarArgsFrameIndex(MFI->CreateFixedObject(1, StackSize,true));
1936 unsigned TotalNumIntRegs = 0, TotalNumXMMRegs = 0;
1938 // FIXME: We should really autogenerate these arrays
1939 static const uint16_t GPR64ArgRegsWin64[] = {
1940 X86::RCX, X86::RDX, X86::R8, X86::R9
1942 static const uint16_t GPR64ArgRegs64Bit[] = {
1943 X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9
1945 static const uint16_t XMMArgRegs64Bit[] = {
1946 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
1947 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
1949 const uint16_t *GPR64ArgRegs;
1950 unsigned NumXMMRegs = 0;
1953 // The XMM registers which might contain var arg parameters are shadowed
1954 // in their paired GPR. So we only need to save the GPR to their home
1956 TotalNumIntRegs = 4;
1957 GPR64ArgRegs = GPR64ArgRegsWin64;
1959 TotalNumIntRegs = 6; TotalNumXMMRegs = 8;
1960 GPR64ArgRegs = GPR64ArgRegs64Bit;
1962 NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs64Bit,
1965 unsigned NumIntRegs = CCInfo.getFirstUnallocated(GPR64ArgRegs,
1968 bool NoImplicitFloatOps = Fn->hasFnAttr(Attribute::NoImplicitFloat);
1969 assert(!(NumXMMRegs && !Subtarget->hasSSE1()) &&
1970 "SSE register cannot be used when SSE is disabled!");
1971 assert(!(NumXMMRegs && MF.getTarget().Options.UseSoftFloat &&
1972 NoImplicitFloatOps) &&
1973 "SSE register cannot be used when SSE is disabled!");
1974 if (MF.getTarget().Options.UseSoftFloat || NoImplicitFloatOps ||
1975 !Subtarget->hasSSE1())
1976 // Kernel mode asks for SSE to be disabled, so don't push them
1978 TotalNumXMMRegs = 0;
1981 const TargetFrameLowering &TFI = *getTargetMachine().getFrameLowering();
1982 // Get to the caller-allocated home save location. Add 8 to account
1983 // for the return address.
1984 int HomeOffset = TFI.getOffsetOfLocalArea() + 8;
1985 FuncInfo->setRegSaveFrameIndex(
1986 MFI->CreateFixedObject(1, NumIntRegs * 8 + HomeOffset, false));
1987 // Fixup to set vararg frame on shadow area (4 x i64).
1989 FuncInfo->setVarArgsFrameIndex(FuncInfo->getRegSaveFrameIndex());
1991 // For X86-64, if there are vararg parameters that are passed via
1992 // registers, then we must store them to their spots on the stack so
1993 // they may be loaded by deferencing the result of va_next.
1994 FuncInfo->setVarArgsGPOffset(NumIntRegs * 8);
1995 FuncInfo->setVarArgsFPOffset(TotalNumIntRegs * 8 + NumXMMRegs * 16);
1996 FuncInfo->setRegSaveFrameIndex(
1997 MFI->CreateStackObject(TotalNumIntRegs * 8 + TotalNumXMMRegs * 16, 16,
2001 // Store the integer parameter registers.
2002 SmallVector<SDValue, 8> MemOps;
2003 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
2005 unsigned Offset = FuncInfo->getVarArgsGPOffset();
2006 for (; NumIntRegs != TotalNumIntRegs; ++NumIntRegs) {
2007 SDValue FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), RSFIN,
2008 DAG.getIntPtrConstant(Offset));
2009 unsigned VReg = MF.addLiveIn(GPR64ArgRegs[NumIntRegs],
2010 &X86::GR64RegClass);
2011 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64);
2013 DAG.getStore(Val.getValue(1), dl, Val, FIN,
2014 MachinePointerInfo::getFixedStack(
2015 FuncInfo->getRegSaveFrameIndex(), Offset),
2017 MemOps.push_back(Store);
2021 if (TotalNumXMMRegs != 0 && NumXMMRegs != TotalNumXMMRegs) {
2022 // Now store the XMM (fp + vector) parameter registers.
2023 SmallVector<SDValue, 11> SaveXMMOps;
2024 SaveXMMOps.push_back(Chain);
2026 unsigned AL = MF.addLiveIn(X86::AL, &X86::GR8RegClass);
2027 SDValue ALVal = DAG.getCopyFromReg(DAG.getEntryNode(), dl, AL, MVT::i8);
2028 SaveXMMOps.push_back(ALVal);
2030 SaveXMMOps.push_back(DAG.getIntPtrConstant(
2031 FuncInfo->getRegSaveFrameIndex()));
2032 SaveXMMOps.push_back(DAG.getIntPtrConstant(
2033 FuncInfo->getVarArgsFPOffset()));
2035 for (; NumXMMRegs != TotalNumXMMRegs; ++NumXMMRegs) {
2036 unsigned VReg = MF.addLiveIn(XMMArgRegs64Bit[NumXMMRegs],
2037 &X86::VR128RegClass);
2038 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::v4f32);
2039 SaveXMMOps.push_back(Val);
2041 MemOps.push_back(DAG.getNode(X86ISD::VASTART_SAVE_XMM_REGS, dl,
2043 &SaveXMMOps[0], SaveXMMOps.size()));
2046 if (!MemOps.empty())
2047 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
2048 &MemOps[0], MemOps.size());
2052 // Some CCs need callee pop.
2053 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg,
2054 MF.getTarget().Options.GuaranteedTailCallOpt)) {
2055 FuncInfo->setBytesToPopOnReturn(StackSize); // Callee pops everything.
2057 FuncInfo->setBytesToPopOnReturn(0); // Callee pops nothing.
2058 // If this is an sret function, the return should pop the hidden pointer.
2059 if (!Is64Bit && !IsTailCallConvention(CallConv) && !IsWindows &&
2060 ArgsAreStructReturn(Ins))
2061 FuncInfo->setBytesToPopOnReturn(4);
2065 // RegSaveFrameIndex is X86-64 only.
2066 FuncInfo->setRegSaveFrameIndex(0xAAAAAAA);
2067 if (CallConv == CallingConv::X86_FastCall ||
2068 CallConv == CallingConv::X86_ThisCall)
2069 // fastcc functions can't have varargs.
2070 FuncInfo->setVarArgsFrameIndex(0xAAAAAAA);
2073 FuncInfo->setArgumentStackSize(StackSize);
2079 X86TargetLowering::LowerMemOpCallTo(SDValue Chain,
2080 SDValue StackPtr, SDValue Arg,
2081 DebugLoc dl, SelectionDAG &DAG,
2082 const CCValAssign &VA,
2083 ISD::ArgFlagsTy Flags) const {
2084 unsigned LocMemOffset = VA.getLocMemOffset();
2085 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
2086 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
2087 if (Flags.isByVal())
2088 return CreateCopyOfByValArgument(Arg, PtrOff, Chain, Flags, DAG, dl);
2090 return DAG.getStore(Chain, dl, Arg, PtrOff,
2091 MachinePointerInfo::getStack(LocMemOffset),
2095 /// EmitTailCallLoadRetAddr - Emit a load of return address if tail call
2096 /// optimization is performed and it is required.
2098 X86TargetLowering::EmitTailCallLoadRetAddr(SelectionDAG &DAG,
2099 SDValue &OutRetAddr, SDValue Chain,
2100 bool IsTailCall, bool Is64Bit,
2101 int FPDiff, DebugLoc dl) const {
2102 // Adjust the Return address stack slot.
2103 EVT VT = getPointerTy();
2104 OutRetAddr = getReturnAddressFrameIndex(DAG);
2106 // Load the "old" Return address.
2107 OutRetAddr = DAG.getLoad(VT, dl, Chain, OutRetAddr, MachinePointerInfo(),
2108 false, false, false, 0);
2109 return SDValue(OutRetAddr.getNode(), 1);
2112 /// EmitTailCallStoreRetAddr - Emit a store of the return address if tail call
2113 /// optimization is performed and it is required (FPDiff!=0).
2115 EmitTailCallStoreRetAddr(SelectionDAG & DAG, MachineFunction &MF,
2116 SDValue Chain, SDValue RetAddrFrIdx,
2117 bool Is64Bit, int FPDiff, DebugLoc dl) {
2118 // Store the return address to the appropriate stack slot.
2119 if (!FPDiff) return Chain;
2120 // Calculate the new stack slot for the return address.
2121 int SlotSize = Is64Bit ? 8 : 4;
2122 int NewReturnAddrFI =
2123 MF.getFrameInfo()->CreateFixedObject(SlotSize, FPDiff-SlotSize, false);
2124 EVT VT = Is64Bit ? MVT::i64 : MVT::i32;
2125 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewReturnAddrFI, VT);
2126 Chain = DAG.getStore(Chain, dl, RetAddrFrIdx, NewRetAddrFrIdx,
2127 MachinePointerInfo::getFixedStack(NewReturnAddrFI),
2133 X86TargetLowering::LowerCall(SDValue Chain, SDValue Callee,
2134 CallingConv::ID CallConv, bool isVarArg,
2135 bool doesNotRet, bool &isTailCall,
2136 const SmallVectorImpl<ISD::OutputArg> &Outs,
2137 const SmallVectorImpl<SDValue> &OutVals,
2138 const SmallVectorImpl<ISD::InputArg> &Ins,
2139 DebugLoc dl, SelectionDAG &DAG,
2140 SmallVectorImpl<SDValue> &InVals) const {
2141 MachineFunction &MF = DAG.getMachineFunction();
2142 bool Is64Bit = Subtarget->is64Bit();
2143 bool IsWin64 = Subtarget->isTargetWin64();
2144 bool IsWindows = Subtarget->isTargetWindows();
2145 bool IsStructRet = CallIsStructReturn(Outs);
2146 bool IsSibcall = false;
2148 if (MF.getTarget().Options.DisableTailCalls)
2152 // Check if it's really possible to do a tail call.
2153 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv,
2154 isVarArg, IsStructRet, MF.getFunction()->hasStructRetAttr(),
2155 Outs, OutVals, Ins, DAG);
2157 // Sibcalls are automatically detected tailcalls which do not require
2159 if (!MF.getTarget().Options.GuaranteedTailCallOpt && isTailCall)
2166 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
2167 "Var args not supported with calling convention fastcc or ghc");
2169 // Analyze operands of the call, assigning locations to each operand.
2170 SmallVector<CCValAssign, 16> ArgLocs;
2171 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(),
2172 ArgLocs, *DAG.getContext());
2174 // Allocate shadow area for Win64
2176 CCInfo.AllocateStack(32, 8);
2179 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
2181 // Get a count of how many bytes are to be pushed on the stack.
2182 unsigned NumBytes = CCInfo.getNextStackOffset();
2184 // This is a sibcall. The memory operands are available in caller's
2185 // own caller's stack.
2187 else if (getTargetMachine().Options.GuaranteedTailCallOpt &&
2188 IsTailCallConvention(CallConv))
2189 NumBytes = GetAlignedArgumentStackSize(NumBytes, DAG);
2192 if (isTailCall && !IsSibcall) {
2193 // Lower arguments at fp - stackoffset + fpdiff.
2194 unsigned NumBytesCallerPushed =
2195 MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn();
2196 FPDiff = NumBytesCallerPushed - NumBytes;
2198 // Set the delta of movement of the returnaddr stackslot.
2199 // But only set if delta is greater than previous delta.
2200 if (FPDiff < (MF.getInfo<X86MachineFunctionInfo>()->getTCReturnAddrDelta()))
2201 MF.getInfo<X86MachineFunctionInfo>()->setTCReturnAddrDelta(FPDiff);
2205 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true));
2207 SDValue RetAddrFrIdx;
2208 // Load return address for tail calls.
2209 if (isTailCall && FPDiff)
2210 Chain = EmitTailCallLoadRetAddr(DAG, RetAddrFrIdx, Chain, isTailCall,
2211 Is64Bit, FPDiff, dl);
2213 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
2214 SmallVector<SDValue, 8> MemOpChains;
2217 // Walk the register/memloc assignments, inserting copies/loads. In the case
2218 // of tail call optimization arguments are handle later.
2219 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2220 CCValAssign &VA = ArgLocs[i];
2221 EVT RegVT = VA.getLocVT();
2222 SDValue Arg = OutVals[i];
2223 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2224 bool isByVal = Flags.isByVal();
2226 // Promote the value if needed.
2227 switch (VA.getLocInfo()) {
2228 default: llvm_unreachable("Unknown loc info!");
2229 case CCValAssign::Full: break;
2230 case CCValAssign::SExt:
2231 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, RegVT, Arg);
2233 case CCValAssign::ZExt:
2234 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, RegVT, Arg);
2236 case CCValAssign::AExt:
2237 if (RegVT.isVector() && RegVT.getSizeInBits() == 128) {
2238 // Special case: passing MMX values in XMM registers.
2239 Arg = DAG.getNode(ISD::BITCAST, dl, MVT::i64, Arg);
2240 Arg = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, Arg);
2241 Arg = getMOVL(DAG, dl, MVT::v2i64, DAG.getUNDEF(MVT::v2i64), Arg);
2243 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, RegVT, Arg);
2245 case CCValAssign::BCvt:
2246 Arg = DAG.getNode(ISD::BITCAST, dl, RegVT, Arg);
2248 case CCValAssign::Indirect: {
2249 // Store the argument.
2250 SDValue SpillSlot = DAG.CreateStackTemporary(VA.getValVT());
2251 int FI = cast<FrameIndexSDNode>(SpillSlot)->getIndex();
2252 Chain = DAG.getStore(Chain, dl, Arg, SpillSlot,
2253 MachinePointerInfo::getFixedStack(FI),
2260 if (VA.isRegLoc()) {
2261 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
2262 if (isVarArg && IsWin64) {
2263 // Win64 ABI requires argument XMM reg to be copied to the corresponding
2264 // shadow reg if callee is a varargs function.
2265 unsigned ShadowReg = 0;
2266 switch (VA.getLocReg()) {
2267 case X86::XMM0: ShadowReg = X86::RCX; break;
2268 case X86::XMM1: ShadowReg = X86::RDX; break;
2269 case X86::XMM2: ShadowReg = X86::R8; break;
2270 case X86::XMM3: ShadowReg = X86::R9; break;
2273 RegsToPass.push_back(std::make_pair(ShadowReg, Arg));
2275 } else if (!IsSibcall && (!isTailCall || isByVal)) {
2276 assert(VA.isMemLoc());
2277 if (StackPtr.getNode() == 0)
2278 StackPtr = DAG.getCopyFromReg(Chain, dl, X86StackPtr, getPointerTy());
2279 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Arg,
2280 dl, DAG, VA, Flags));
2284 if (!MemOpChains.empty())
2285 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
2286 &MemOpChains[0], MemOpChains.size());
2288 // Build a sequence of copy-to-reg nodes chained together with token chain
2289 // and flag operands which copy the outgoing args into registers.
2291 // Tail call byval lowering might overwrite argument registers so in case of
2292 // tail call optimization the copies to registers are lowered later.
2294 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
2295 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
2296 RegsToPass[i].second, InFlag);
2297 InFlag = Chain.getValue(1);
2300 if (Subtarget->isPICStyleGOT()) {
2301 // ELF / PIC requires GOT in the EBX register before function calls via PLT
2304 Chain = DAG.getCopyToReg(Chain, dl, X86::EBX,
2305 DAG.getNode(X86ISD::GlobalBaseReg,
2306 DebugLoc(), getPointerTy()),
2308 InFlag = Chain.getValue(1);
2310 // If we are tail calling and generating PIC/GOT style code load the
2311 // address of the callee into ECX. The value in ecx is used as target of
2312 // the tail jump. This is done to circumvent the ebx/callee-saved problem
2313 // for tail calls on PIC/GOT architectures. Normally we would just put the
2314 // address of GOT into ebx and then call target@PLT. But for tail calls
2315 // ebx would be restored (since ebx is callee saved) before jumping to the
2318 // Note: The actual moving to ECX is done further down.
2319 GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee);
2320 if (G && !G->getGlobal()->hasHiddenVisibility() &&
2321 !G->getGlobal()->hasProtectedVisibility())
2322 Callee = LowerGlobalAddress(Callee, DAG);
2323 else if (isa<ExternalSymbolSDNode>(Callee))
2324 Callee = LowerExternalSymbol(Callee, DAG);
2328 if (Is64Bit && isVarArg && !IsWin64) {
2329 // From AMD64 ABI document:
2330 // For calls that may call functions that use varargs or stdargs
2331 // (prototype-less calls or calls to functions containing ellipsis (...) in
2332 // the declaration) %al is used as hidden argument to specify the number
2333 // of SSE registers used. The contents of %al do not need to match exactly
2334 // the number of registers, but must be an ubound on the number of SSE
2335 // registers used and is in the range 0 - 8 inclusive.
2337 // Count the number of XMM registers allocated.
2338 static const uint16_t XMMArgRegs[] = {
2339 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
2340 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
2342 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs, 8);
2343 assert((Subtarget->hasSSE1() || !NumXMMRegs)
2344 && "SSE registers cannot be used when SSE is disabled");
2346 Chain = DAG.getCopyToReg(Chain, dl, X86::AL,
2347 DAG.getConstant(NumXMMRegs, MVT::i8), InFlag);
2348 InFlag = Chain.getValue(1);
2352 // For tail calls lower the arguments to the 'real' stack slot.
2354 // Force all the incoming stack arguments to be loaded from the stack
2355 // before any new outgoing arguments are stored to the stack, because the
2356 // outgoing stack slots may alias the incoming argument stack slots, and
2357 // the alias isn't otherwise explicit. This is slightly more conservative
2358 // than necessary, because it means that each store effectively depends
2359 // on every argument instead of just those arguments it would clobber.
2360 SDValue ArgChain = DAG.getStackArgumentTokenFactor(Chain);
2362 SmallVector<SDValue, 8> MemOpChains2;
2365 // Do not flag preceding copytoreg stuff together with the following stuff.
2367 if (getTargetMachine().Options.GuaranteedTailCallOpt) {
2368 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2369 CCValAssign &VA = ArgLocs[i];
2372 assert(VA.isMemLoc());
2373 SDValue Arg = OutVals[i];
2374 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2375 // Create frame index.
2376 int32_t Offset = VA.getLocMemOffset()+FPDiff;
2377 uint32_t OpSize = (VA.getLocVT().getSizeInBits()+7)/8;
2378 FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true);
2379 FIN = DAG.getFrameIndex(FI, getPointerTy());
2381 if (Flags.isByVal()) {
2382 // Copy relative to framepointer.
2383 SDValue Source = DAG.getIntPtrConstant(VA.getLocMemOffset());
2384 if (StackPtr.getNode() == 0)
2385 StackPtr = DAG.getCopyFromReg(Chain, dl, X86StackPtr,
2387 Source = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, Source);
2389 MemOpChains2.push_back(CreateCopyOfByValArgument(Source, FIN,
2393 // Store relative to framepointer.
2394 MemOpChains2.push_back(
2395 DAG.getStore(ArgChain, dl, Arg, FIN,
2396 MachinePointerInfo::getFixedStack(FI),
2402 if (!MemOpChains2.empty())
2403 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
2404 &MemOpChains2[0], MemOpChains2.size());
2406 // Copy arguments to their registers.
2407 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
2408 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
2409 RegsToPass[i].second, InFlag);
2410 InFlag = Chain.getValue(1);
2414 // Store the return address to the appropriate stack slot.
2415 Chain = EmitTailCallStoreRetAddr(DAG, MF, Chain, RetAddrFrIdx, Is64Bit,
2419 if (getTargetMachine().getCodeModel() == CodeModel::Large) {
2420 assert(Is64Bit && "Large code model is only legal in 64-bit mode.");
2421 // In the 64-bit large code model, we have to make all calls
2422 // through a register, since the call instruction's 32-bit
2423 // pc-relative offset may not be large enough to hold the whole
2425 } else if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
2426 // If the callee is a GlobalAddress node (quite common, every direct call
2427 // is) turn it into a TargetGlobalAddress node so that legalize doesn't hack
2430 // We should use extra load for direct calls to dllimported functions in
2432 const GlobalValue *GV = G->getGlobal();
2433 if (!GV->hasDLLImportLinkage()) {
2434 unsigned char OpFlags = 0;
2435 bool ExtraLoad = false;
2436 unsigned WrapperKind = ISD::DELETED_NODE;
2438 // On ELF targets, in both X86-64 and X86-32 mode, direct calls to
2439 // external symbols most go through the PLT in PIC mode. If the symbol
2440 // has hidden or protected visibility, or if it is static or local, then
2441 // we don't need to use the PLT - we can directly call it.
2442 if (Subtarget->isTargetELF() &&
2443 getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
2444 GV->hasDefaultVisibility() && !GV->hasLocalLinkage()) {
2445 OpFlags = X86II::MO_PLT;
2446 } else if (Subtarget->isPICStyleStubAny() &&
2447 (GV->isDeclaration() || GV->isWeakForLinker()) &&
2448 (!Subtarget->getTargetTriple().isMacOSX() ||
2449 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
2450 // PC-relative references to external symbols should go through $stub,
2451 // unless we're building with the leopard linker or later, which
2452 // automatically synthesizes these stubs.
2453 OpFlags = X86II::MO_DARWIN_STUB;
2454 } else if (Subtarget->isPICStyleRIPRel() &&
2455 isa<Function>(GV) &&
2456 cast<Function>(GV)->hasFnAttr(Attribute::NonLazyBind)) {
2457 // If the function is marked as non-lazy, generate an indirect call
2458 // which loads from the GOT directly. This avoids runtime overhead
2459 // at the cost of eager binding (and one extra byte of encoding).
2460 OpFlags = X86II::MO_GOTPCREL;
2461 WrapperKind = X86ISD::WrapperRIP;
2465 Callee = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(),
2466 G->getOffset(), OpFlags);
2468 // Add a wrapper if needed.
2469 if (WrapperKind != ISD::DELETED_NODE)
2470 Callee = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Callee);
2471 // Add extra indirection if needed.
2473 Callee = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Callee,
2474 MachinePointerInfo::getGOT(),
2475 false, false, false, 0);
2477 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
2478 unsigned char OpFlags = 0;
2480 // On ELF targets, in either X86-64 or X86-32 mode, direct calls to
2481 // external symbols should go through the PLT.
2482 if (Subtarget->isTargetELF() &&
2483 getTargetMachine().getRelocationModel() == Reloc::PIC_) {
2484 OpFlags = X86II::MO_PLT;
2485 } else if (Subtarget->isPICStyleStubAny() &&
2486 (!Subtarget->getTargetTriple().isMacOSX() ||
2487 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
2488 // PC-relative references to external symbols should go through $stub,
2489 // unless we're building with the leopard linker or later, which
2490 // automatically synthesizes these stubs.
2491 OpFlags = X86II::MO_DARWIN_STUB;
2494 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy(),
2498 // Returns a chain & a flag for retval copy to use.
2499 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
2500 SmallVector<SDValue, 8> Ops;
2502 if (!IsSibcall && isTailCall) {
2503 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
2504 DAG.getIntPtrConstant(0, true), InFlag);
2505 InFlag = Chain.getValue(1);
2508 Ops.push_back(Chain);
2509 Ops.push_back(Callee);
2512 Ops.push_back(DAG.getConstant(FPDiff, MVT::i32));
2514 // Add argument registers to the end of the list so that they are known live
2516 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
2517 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
2518 RegsToPass[i].second.getValueType()));
2520 // Add an implicit use GOT pointer in EBX.
2521 if (!isTailCall && Subtarget->isPICStyleGOT())
2522 Ops.push_back(DAG.getRegister(X86::EBX, getPointerTy()));
2524 // Add an implicit use of AL for non-Windows x86 64-bit vararg functions.
2525 if (Is64Bit && isVarArg && !IsWin64)
2526 Ops.push_back(DAG.getRegister(X86::AL, MVT::i8));
2528 // Add a register mask operand representing the call-preserved registers.
2529 const TargetRegisterInfo *TRI = getTargetMachine().getRegisterInfo();
2530 const uint32_t *Mask = TRI->getCallPreservedMask(CallConv);
2531 assert(Mask && "Missing call preserved mask for calling convention");
2532 Ops.push_back(DAG.getRegisterMask(Mask));
2534 if (InFlag.getNode())
2535 Ops.push_back(InFlag);
2539 //// If this is the first return lowered for this function, add the regs
2540 //// to the liveout set for the function.
2541 // This isn't right, although it's probably harmless on x86; liveouts
2542 // should be computed from returns not tail calls. Consider a void
2543 // function making a tail call to a function returning int.
2544 return DAG.getNode(X86ISD::TC_RETURN, dl,
2545 NodeTys, &Ops[0], Ops.size());
2548 Chain = DAG.getNode(X86ISD::CALL, dl, NodeTys, &Ops[0], Ops.size());
2549 InFlag = Chain.getValue(1);
2551 // Create the CALLSEQ_END node.
2552 unsigned NumBytesForCalleeToPush;
2553 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg,
2554 getTargetMachine().Options.GuaranteedTailCallOpt))
2555 NumBytesForCalleeToPush = NumBytes; // Callee pops everything
2556 else if (!Is64Bit && !IsTailCallConvention(CallConv) && !IsWindows &&
2558 // If this is a call to a struct-return function, the callee
2559 // pops the hidden struct pointer, so we have to push it back.
2560 // This is common for Darwin/X86, Linux & Mingw32 targets.
2561 // For MSVC Win32 targets, the caller pops the hidden struct pointer.
2562 NumBytesForCalleeToPush = 4;
2564 NumBytesForCalleeToPush = 0; // Callee pops nothing.
2566 // Returns a flag for retval copy to use.
2568 Chain = DAG.getCALLSEQ_END(Chain,
2569 DAG.getIntPtrConstant(NumBytes, true),
2570 DAG.getIntPtrConstant(NumBytesForCalleeToPush,
2573 InFlag = Chain.getValue(1);
2576 // Handle result values, copying them out of physregs into vregs that we
2578 return LowerCallResult(Chain, InFlag, CallConv, isVarArg,
2579 Ins, dl, DAG, InVals);
2583 //===----------------------------------------------------------------------===//
2584 // Fast Calling Convention (tail call) implementation
2585 //===----------------------------------------------------------------------===//
2587 // Like std call, callee cleans arguments, convention except that ECX is
2588 // reserved for storing the tail called function address. Only 2 registers are
2589 // free for argument passing (inreg). Tail call optimization is performed
2591 // * tailcallopt is enabled
2592 // * caller/callee are fastcc
2593 // On X86_64 architecture with GOT-style position independent code only local
2594 // (within module) calls are supported at the moment.
2595 // To keep the stack aligned according to platform abi the function
2596 // GetAlignedArgumentStackSize ensures that argument delta is always multiples
2597 // of stack alignment. (Dynamic linkers need this - darwin's dyld for example)
2598 // If a tail called function callee has more arguments than the caller the
2599 // caller needs to make sure that there is room to move the RETADDR to. This is
2600 // achieved by reserving an area the size of the argument delta right after the
2601 // original REtADDR, but before the saved framepointer or the spilled registers
2602 // e.g. caller(arg1, arg2) calls callee(arg1, arg2,arg3,arg4)
2614 /// GetAlignedArgumentStackSize - Make the stack size align e.g 16n + 12 aligned
2615 /// for a 16 byte align requirement.
2617 X86TargetLowering::GetAlignedArgumentStackSize(unsigned StackSize,
2618 SelectionDAG& DAG) const {
2619 MachineFunction &MF = DAG.getMachineFunction();
2620 const TargetMachine &TM = MF.getTarget();
2621 const TargetFrameLowering &TFI = *TM.getFrameLowering();
2622 unsigned StackAlignment = TFI.getStackAlignment();
2623 uint64_t AlignMask = StackAlignment - 1;
2624 int64_t Offset = StackSize;
2625 uint64_t SlotSize = TD->getPointerSize();
2626 if ( (Offset & AlignMask) <= (StackAlignment - SlotSize) ) {
2627 // Number smaller than 12 so just add the difference.
2628 Offset += ((StackAlignment - SlotSize) - (Offset & AlignMask));
2630 // Mask out lower bits, add stackalignment once plus the 12 bytes.
2631 Offset = ((~AlignMask) & Offset) + StackAlignment +
2632 (StackAlignment-SlotSize);
2637 /// MatchingStackOffset - Return true if the given stack call argument is
2638 /// already available in the same position (relatively) of the caller's
2639 /// incoming argument stack.
2641 bool MatchingStackOffset(SDValue Arg, unsigned Offset, ISD::ArgFlagsTy Flags,
2642 MachineFrameInfo *MFI, const MachineRegisterInfo *MRI,
2643 const X86InstrInfo *TII) {
2644 unsigned Bytes = Arg.getValueType().getSizeInBits() / 8;
2646 if (Arg.getOpcode() == ISD::CopyFromReg) {
2647 unsigned VR = cast<RegisterSDNode>(Arg.getOperand(1))->getReg();
2648 if (!TargetRegisterInfo::isVirtualRegister(VR))
2650 MachineInstr *Def = MRI->getVRegDef(VR);
2653 if (!Flags.isByVal()) {
2654 if (!TII->isLoadFromStackSlot(Def, FI))
2657 unsigned Opcode = Def->getOpcode();
2658 if ((Opcode == X86::LEA32r || Opcode == X86::LEA64r) &&
2659 Def->getOperand(1).isFI()) {
2660 FI = Def->getOperand(1).getIndex();
2661 Bytes = Flags.getByValSize();
2665 } else if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Arg)) {
2666 if (Flags.isByVal())
2667 // ByVal argument is passed in as a pointer but it's now being
2668 // dereferenced. e.g.
2669 // define @foo(%struct.X* %A) {
2670 // tail call @bar(%struct.X* byval %A)
2673 SDValue Ptr = Ld->getBasePtr();
2674 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr);
2677 FI = FINode->getIndex();
2678 } else if (Arg.getOpcode() == ISD::FrameIndex && Flags.isByVal()) {
2679 FrameIndexSDNode *FINode = cast<FrameIndexSDNode>(Arg);
2680 FI = FINode->getIndex();
2681 Bytes = Flags.getByValSize();
2685 assert(FI != INT_MAX);
2686 if (!MFI->isFixedObjectIndex(FI))
2688 return Offset == MFI->getObjectOffset(FI) && Bytes == MFI->getObjectSize(FI);
2691 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
2692 /// for tail call optimization. Targets which want to do tail call
2693 /// optimization should implement this function.
2695 X86TargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
2696 CallingConv::ID CalleeCC,
2698 bool isCalleeStructRet,
2699 bool isCallerStructRet,
2700 const SmallVectorImpl<ISD::OutputArg> &Outs,
2701 const SmallVectorImpl<SDValue> &OutVals,
2702 const SmallVectorImpl<ISD::InputArg> &Ins,
2703 SelectionDAG& DAG) const {
2704 if (!IsTailCallConvention(CalleeCC) &&
2705 CalleeCC != CallingConv::C)
2708 // If -tailcallopt is specified, make fastcc functions tail-callable.
2709 const MachineFunction &MF = DAG.getMachineFunction();
2710 const Function *CallerF = DAG.getMachineFunction().getFunction();
2711 CallingConv::ID CallerCC = CallerF->getCallingConv();
2712 bool CCMatch = CallerCC == CalleeCC;
2714 if (getTargetMachine().Options.GuaranteedTailCallOpt) {
2715 if (IsTailCallConvention(CalleeCC) && CCMatch)
2720 // Look for obvious safe cases to perform tail call optimization that do not
2721 // require ABI changes. This is what gcc calls sibcall.
2723 // Can't do sibcall if stack needs to be dynamically re-aligned. PEI needs to
2724 // emit a special epilogue.
2725 if (RegInfo->needsStackRealignment(MF))
2728 // Also avoid sibcall optimization if either caller or callee uses struct
2729 // return semantics.
2730 if (isCalleeStructRet || isCallerStructRet)
2733 // An stdcall caller is expected to clean up its arguments; the callee
2734 // isn't going to do that.
2735 if (!CCMatch && CallerCC==CallingConv::X86_StdCall)
2738 // Do not sibcall optimize vararg calls unless all arguments are passed via
2740 if (isVarArg && !Outs.empty()) {
2742 // Optimizing for varargs on Win64 is unlikely to be safe without
2743 // additional testing.
2744 if (Subtarget->isTargetWin64())
2747 SmallVector<CCValAssign, 16> ArgLocs;
2748 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(),
2749 getTargetMachine(), ArgLocs, *DAG.getContext());
2751 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
2752 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i)
2753 if (!ArgLocs[i].isRegLoc())
2757 // If the call result is in ST0 / ST1, it needs to be popped off the x87
2758 // stack. Therefore, if it's not used by the call it is not safe to optimize
2759 // this into a sibcall.
2760 bool Unused = false;
2761 for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
2768 SmallVector<CCValAssign, 16> RVLocs;
2769 CCState CCInfo(CalleeCC, false, DAG.getMachineFunction(),
2770 getTargetMachine(), RVLocs, *DAG.getContext());
2771 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
2772 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
2773 CCValAssign &VA = RVLocs[i];
2774 if (VA.getLocReg() == X86::ST0 || VA.getLocReg() == X86::ST1)
2779 // If the calling conventions do not match, then we'd better make sure the
2780 // results are returned in the same way as what the caller expects.
2782 SmallVector<CCValAssign, 16> RVLocs1;
2783 CCState CCInfo1(CalleeCC, false, DAG.getMachineFunction(),
2784 getTargetMachine(), RVLocs1, *DAG.getContext());
2785 CCInfo1.AnalyzeCallResult(Ins, RetCC_X86);
2787 SmallVector<CCValAssign, 16> RVLocs2;
2788 CCState CCInfo2(CallerCC, false, DAG.getMachineFunction(),
2789 getTargetMachine(), RVLocs2, *DAG.getContext());
2790 CCInfo2.AnalyzeCallResult(Ins, RetCC_X86);
2792 if (RVLocs1.size() != RVLocs2.size())
2794 for (unsigned i = 0, e = RVLocs1.size(); i != e; ++i) {
2795 if (RVLocs1[i].isRegLoc() != RVLocs2[i].isRegLoc())
2797 if (RVLocs1[i].getLocInfo() != RVLocs2[i].getLocInfo())
2799 if (RVLocs1[i].isRegLoc()) {
2800 if (RVLocs1[i].getLocReg() != RVLocs2[i].getLocReg())
2803 if (RVLocs1[i].getLocMemOffset() != RVLocs2[i].getLocMemOffset())
2809 // If the callee takes no arguments then go on to check the results of the
2811 if (!Outs.empty()) {
2812 // Check if stack adjustment is needed. For now, do not do this if any
2813 // argument is passed on the stack.
2814 SmallVector<CCValAssign, 16> ArgLocs;
2815 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(),
2816 getTargetMachine(), ArgLocs, *DAG.getContext());
2818 // Allocate shadow area for Win64
2819 if (Subtarget->isTargetWin64()) {
2820 CCInfo.AllocateStack(32, 8);
2823 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
2824 if (CCInfo.getNextStackOffset()) {
2825 MachineFunction &MF = DAG.getMachineFunction();
2826 if (MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn())
2829 // Check if the arguments are already laid out in the right way as
2830 // the caller's fixed stack objects.
2831 MachineFrameInfo *MFI = MF.getFrameInfo();
2832 const MachineRegisterInfo *MRI = &MF.getRegInfo();
2833 const X86InstrInfo *TII =
2834 ((X86TargetMachine&)getTargetMachine()).getInstrInfo();
2835 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2836 CCValAssign &VA = ArgLocs[i];
2837 SDValue Arg = OutVals[i];
2838 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2839 if (VA.getLocInfo() == CCValAssign::Indirect)
2841 if (!VA.isRegLoc()) {
2842 if (!MatchingStackOffset(Arg, VA.getLocMemOffset(), Flags,
2849 // If the tailcall address may be in a register, then make sure it's
2850 // possible to register allocate for it. In 32-bit, the call address can
2851 // only target EAX, EDX, or ECX since the tail call must be scheduled after
2852 // callee-saved registers are restored. These happen to be the same
2853 // registers used to pass 'inreg' arguments so watch out for those.
2854 if (!Subtarget->is64Bit() &&
2855 !isa<GlobalAddressSDNode>(Callee) &&
2856 !isa<ExternalSymbolSDNode>(Callee)) {
2857 unsigned NumInRegs = 0;
2858 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2859 CCValAssign &VA = ArgLocs[i];
2862 unsigned Reg = VA.getLocReg();
2865 case X86::EAX: case X86::EDX: case X86::ECX:
2866 if (++NumInRegs == 3)
2878 X86TargetLowering::createFastISel(FunctionLoweringInfo &funcInfo) const {
2879 return X86::createFastISel(funcInfo);
2883 //===----------------------------------------------------------------------===//
2884 // Other Lowering Hooks
2885 //===----------------------------------------------------------------------===//
2887 static bool MayFoldLoad(SDValue Op) {
2888 return Op.hasOneUse() && ISD::isNormalLoad(Op.getNode());
2891 static bool MayFoldIntoStore(SDValue Op) {
2892 return Op.hasOneUse() && ISD::isNormalStore(*Op.getNode()->use_begin());
2895 static bool isTargetShuffle(unsigned Opcode) {
2897 default: return false;
2898 case X86ISD::PSHUFD:
2899 case X86ISD::PSHUFHW:
2900 case X86ISD::PSHUFLW:
2902 case X86ISD::PALIGN:
2903 case X86ISD::MOVLHPS:
2904 case X86ISD::MOVLHPD:
2905 case X86ISD::MOVHLPS:
2906 case X86ISD::MOVLPS:
2907 case X86ISD::MOVLPD:
2908 case X86ISD::MOVSHDUP:
2909 case X86ISD::MOVSLDUP:
2910 case X86ISD::MOVDDUP:
2913 case X86ISD::UNPCKL:
2914 case X86ISD::UNPCKH:
2915 case X86ISD::VPERMILP:
2916 case X86ISD::VPERM2X128:
2917 case X86ISD::VPERMI:
2922 static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT,
2923 SDValue V1, SelectionDAG &DAG) {
2925 default: llvm_unreachable("Unknown x86 shuffle node");
2926 case X86ISD::MOVSHDUP:
2927 case X86ISD::MOVSLDUP:
2928 case X86ISD::MOVDDUP:
2929 return DAG.getNode(Opc, dl, VT, V1);
2933 static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT,
2934 SDValue V1, unsigned TargetMask,
2935 SelectionDAG &DAG) {
2937 default: llvm_unreachable("Unknown x86 shuffle node");
2938 case X86ISD::PSHUFD:
2939 case X86ISD::PSHUFHW:
2940 case X86ISD::PSHUFLW:
2941 case X86ISD::VPERMILP:
2942 case X86ISD::VPERMI:
2943 return DAG.getNode(Opc, dl, VT, V1, DAG.getConstant(TargetMask, MVT::i8));
2947 static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT,
2948 SDValue V1, SDValue V2, unsigned TargetMask,
2949 SelectionDAG &DAG) {
2951 default: llvm_unreachable("Unknown x86 shuffle node");
2952 case X86ISD::PALIGN:
2954 case X86ISD::VPERM2X128:
2955 return DAG.getNode(Opc, dl, VT, V1, V2,
2956 DAG.getConstant(TargetMask, MVT::i8));
2960 static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT,
2961 SDValue V1, SDValue V2, SelectionDAG &DAG) {
2963 default: llvm_unreachable("Unknown x86 shuffle node");
2964 case X86ISD::MOVLHPS:
2965 case X86ISD::MOVLHPD:
2966 case X86ISD::MOVHLPS:
2967 case X86ISD::MOVLPS:
2968 case X86ISD::MOVLPD:
2971 case X86ISD::UNPCKL:
2972 case X86ISD::UNPCKH:
2973 return DAG.getNode(Opc, dl, VT, V1, V2);
2977 SDValue X86TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) const {
2978 MachineFunction &MF = DAG.getMachineFunction();
2979 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
2980 int ReturnAddrIndex = FuncInfo->getRAIndex();
2982 if (ReturnAddrIndex == 0) {
2983 // Set up a frame object for the return address.
2984 uint64_t SlotSize = TD->getPointerSize();
2985 ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(SlotSize, -SlotSize,
2987 FuncInfo->setRAIndex(ReturnAddrIndex);
2990 return DAG.getFrameIndex(ReturnAddrIndex, getPointerTy());
2994 bool X86::isOffsetSuitableForCodeModel(int64_t Offset, CodeModel::Model M,
2995 bool hasSymbolicDisplacement) {
2996 // Offset should fit into 32 bit immediate field.
2997 if (!isInt<32>(Offset))
3000 // If we don't have a symbolic displacement - we don't have any extra
3002 if (!hasSymbolicDisplacement)
3005 // FIXME: Some tweaks might be needed for medium code model.
3006 if (M != CodeModel::Small && M != CodeModel::Kernel)
3009 // For small code model we assume that latest object is 16MB before end of 31
3010 // bits boundary. We may also accept pretty large negative constants knowing
3011 // that all objects are in the positive half of address space.
3012 if (M == CodeModel::Small && Offset < 16*1024*1024)
3015 // For kernel code model we know that all object resist in the negative half
3016 // of 32bits address space. We may not accept negative offsets, since they may
3017 // be just off and we may accept pretty large positive ones.
3018 if (M == CodeModel::Kernel && Offset > 0)
3024 /// isCalleePop - Determines whether the callee is required to pop its
3025 /// own arguments. Callee pop is necessary to support tail calls.
3026 bool X86::isCalleePop(CallingConv::ID CallingConv,
3027 bool is64Bit, bool IsVarArg, bool TailCallOpt) {
3031 switch (CallingConv) {
3034 case CallingConv::X86_StdCall:
3036 case CallingConv::X86_FastCall:
3038 case CallingConv::X86_ThisCall:
3040 case CallingConv::Fast:
3042 case CallingConv::GHC:
3047 /// TranslateX86CC - do a one to one translation of a ISD::CondCode to the X86
3048 /// specific condition code, returning the condition code and the LHS/RHS of the
3049 /// comparison to make.
3050 static unsigned TranslateX86CC(ISD::CondCode SetCCOpcode, bool isFP,
3051 SDValue &LHS, SDValue &RHS, SelectionDAG &DAG) {
3053 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
3054 if (SetCCOpcode == ISD::SETGT && RHSC->isAllOnesValue()) {
3055 // X > -1 -> X == 0, jump !sign.
3056 RHS = DAG.getConstant(0, RHS.getValueType());
3057 return X86::COND_NS;
3059 if (SetCCOpcode == ISD::SETLT && RHSC->isNullValue()) {
3060 // X < 0 -> X == 0, jump on sign.
3063 if (SetCCOpcode == ISD::SETLT && RHSC->getZExtValue() == 1) {
3065 RHS = DAG.getConstant(0, RHS.getValueType());
3066 return X86::COND_LE;
3070 switch (SetCCOpcode) {
3071 default: llvm_unreachable("Invalid integer condition!");
3072 case ISD::SETEQ: return X86::COND_E;
3073 case ISD::SETGT: return X86::COND_G;
3074 case ISD::SETGE: return X86::COND_GE;
3075 case ISD::SETLT: return X86::COND_L;
3076 case ISD::SETLE: return X86::COND_LE;
3077 case ISD::SETNE: return X86::COND_NE;
3078 case ISD::SETULT: return X86::COND_B;
3079 case ISD::SETUGT: return X86::COND_A;
3080 case ISD::SETULE: return X86::COND_BE;
3081 case ISD::SETUGE: return X86::COND_AE;
3085 // First determine if it is required or is profitable to flip the operands.
3087 // If LHS is a foldable load, but RHS is not, flip the condition.
3088 if (ISD::isNON_EXTLoad(LHS.getNode()) &&
3089 !ISD::isNON_EXTLoad(RHS.getNode())) {
3090 SetCCOpcode = getSetCCSwappedOperands(SetCCOpcode);
3091 std::swap(LHS, RHS);
3094 switch (SetCCOpcode) {
3100 std::swap(LHS, RHS);
3104 // On a floating point condition, the flags are set as follows:
3106 // 0 | 0 | 0 | X > Y
3107 // 0 | 0 | 1 | X < Y
3108 // 1 | 0 | 0 | X == Y
3109 // 1 | 1 | 1 | unordered
3110 switch (SetCCOpcode) {
3111 default: llvm_unreachable("Condcode should be pre-legalized away");
3113 case ISD::SETEQ: return X86::COND_E;
3114 case ISD::SETOLT: // flipped
3116 case ISD::SETGT: return X86::COND_A;
3117 case ISD::SETOLE: // flipped
3119 case ISD::SETGE: return X86::COND_AE;
3120 case ISD::SETUGT: // flipped
3122 case ISD::SETLT: return X86::COND_B;
3123 case ISD::SETUGE: // flipped
3125 case ISD::SETLE: return X86::COND_BE;
3127 case ISD::SETNE: return X86::COND_NE;
3128 case ISD::SETUO: return X86::COND_P;
3129 case ISD::SETO: return X86::COND_NP;
3131 case ISD::SETUNE: return X86::COND_INVALID;
3135 /// hasFPCMov - is there a floating point cmov for the specific X86 condition
3136 /// code. Current x86 isa includes the following FP cmov instructions:
3137 /// fcmovb, fcomvbe, fcomve, fcmovu, fcmovae, fcmova, fcmovne, fcmovnu.
3138 static bool hasFPCMov(unsigned X86CC) {
3154 /// isFPImmLegal - Returns true if the target can instruction select the
3155 /// specified FP immediate natively. If false, the legalizer will
3156 /// materialize the FP immediate as a load from a constant pool.
3157 bool X86TargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
3158 for (unsigned i = 0, e = LegalFPImmediates.size(); i != e; ++i) {
3159 if (Imm.bitwiseIsEqual(LegalFPImmediates[i]))
3165 /// isUndefOrInRange - Return true if Val is undef or if its value falls within
3166 /// the specified range (L, H].
3167 static bool isUndefOrInRange(int Val, int Low, int Hi) {
3168 return (Val < 0) || (Val >= Low && Val < Hi);
3171 /// isUndefOrEqual - Val is either less than zero (undef) or equal to the
3172 /// specified value.
3173 static bool isUndefOrEqual(int Val, int CmpVal) {
3174 if (Val < 0 || Val == CmpVal)
3179 /// isSequentialOrUndefInRange - Return true if every element in Mask, begining
3180 /// from position Pos and ending in Pos+Size, falls within the specified
3181 /// sequential range (L, L+Pos]. or is undef.
3182 static bool isSequentialOrUndefInRange(ArrayRef<int> Mask,
3183 unsigned Pos, unsigned Size, int Low) {
3184 for (unsigned i = Pos, e = Pos+Size; i != e; ++i, ++Low)
3185 if (!isUndefOrEqual(Mask[i], Low))
3190 /// isPSHUFDMask - Return true if the node specifies a shuffle of elements that
3191 /// is suitable for input to PSHUFD or PSHUFW. That is, it doesn't reference
3192 /// the second operand.
3193 static bool isPSHUFDMask(ArrayRef<int> Mask, EVT VT) {
3194 if (VT == MVT::v4f32 || VT == MVT::v4i32 )
3195 return (Mask[0] < 4 && Mask[1] < 4 && Mask[2] < 4 && Mask[3] < 4);
3196 if (VT == MVT::v2f64 || VT == MVT::v2i64)
3197 return (Mask[0] < 2 && Mask[1] < 2);
3201 /// isPSHUFHWMask - Return true if the node specifies a shuffle of elements that
3202 /// is suitable for input to PSHUFHW.
3203 static bool isPSHUFHWMask(ArrayRef<int> Mask, EVT VT, bool HasAVX2) {
3204 if (VT != MVT::v8i16 && (!HasAVX2 || VT != MVT::v16i16))
3207 // Lower quadword copied in order or undef.
3208 if (!isSequentialOrUndefInRange(Mask, 0, 4, 0))
3211 // Upper quadword shuffled.
3212 for (unsigned i = 4; i != 8; ++i)
3213 if (!isUndefOrInRange(Mask[i], 4, 8))
3216 if (VT == MVT::v16i16) {
3217 // Lower quadword copied in order or undef.
3218 if (!isSequentialOrUndefInRange(Mask, 8, 4, 8))
3221 // Upper quadword shuffled.
3222 for (unsigned i = 12; i != 16; ++i)
3223 if (!isUndefOrInRange(Mask[i], 12, 16))
3230 /// isPSHUFLWMask - Return true if the node specifies a shuffle of elements that
3231 /// is suitable for input to PSHUFLW.
3232 static bool isPSHUFLWMask(ArrayRef<int> Mask, EVT VT, bool HasAVX2) {
3233 if (VT != MVT::v8i16 && (!HasAVX2 || VT != MVT::v16i16))
3236 // Upper quadword copied in order.
3237 if (!isSequentialOrUndefInRange(Mask, 4, 4, 4))
3240 // Lower quadword shuffled.
3241 for (unsigned i = 0; i != 4; ++i)
3242 if (!isUndefOrInRange(Mask[i], 0, 4))
3245 if (VT == MVT::v16i16) {
3246 // Upper quadword copied in order.
3247 if (!isSequentialOrUndefInRange(Mask, 12, 4, 12))
3250 // Lower quadword shuffled.
3251 for (unsigned i = 8; i != 12; ++i)
3252 if (!isUndefOrInRange(Mask[i], 8, 12))
3259 /// isPALIGNRMask - Return true if the node specifies a shuffle of elements that
3260 /// is suitable for input to PALIGNR.
3261 static bool isPALIGNRMask(ArrayRef<int> Mask, EVT VT,
3262 const X86Subtarget *Subtarget) {
3263 if ((VT.getSizeInBits() == 128 && !Subtarget->hasSSSE3()) ||
3264 (VT.getSizeInBits() == 256 && !Subtarget->hasAVX2()))
3267 unsigned NumElts = VT.getVectorNumElements();
3268 unsigned NumLanes = VT.getSizeInBits()/128;
3269 unsigned NumLaneElts = NumElts/NumLanes;
3271 // Do not handle 64-bit element shuffles with palignr.
3272 if (NumLaneElts == 2)
3275 for (unsigned l = 0; l != NumElts; l+=NumLaneElts) {
3277 for (i = 0; i != NumLaneElts; ++i) {
3282 // Lane is all undef, go to next lane
3283 if (i == NumLaneElts)
3286 int Start = Mask[i+l];
3288 // Make sure its in this lane in one of the sources
3289 if (!isUndefOrInRange(Start, l, l+NumLaneElts) &&
3290 !isUndefOrInRange(Start, l+NumElts, l+NumElts+NumLaneElts))
3293 // If not lane 0, then we must match lane 0
3294 if (l != 0 && Mask[i] >= 0 && !isUndefOrEqual(Start, Mask[i]+l))
3297 // Correct second source to be contiguous with first source
3298 if (Start >= (int)NumElts)
3299 Start -= NumElts - NumLaneElts;
3301 // Make sure we're shifting in the right direction.
3302 if (Start <= (int)(i+l))
3307 // Check the rest of the elements to see if they are consecutive.
3308 for (++i; i != NumLaneElts; ++i) {
3309 int Idx = Mask[i+l];
3311 // Make sure its in this lane
3312 if (!isUndefOrInRange(Idx, l, l+NumLaneElts) &&
3313 !isUndefOrInRange(Idx, l+NumElts, l+NumElts+NumLaneElts))
3316 // If not lane 0, then we must match lane 0
3317 if (l != 0 && Mask[i] >= 0 && !isUndefOrEqual(Idx, Mask[i]+l))
3320 if (Idx >= (int)NumElts)
3321 Idx -= NumElts - NumLaneElts;
3323 if (!isUndefOrEqual(Idx, Start+i))
3332 /// CommuteVectorShuffleMask - Change values in a shuffle permute mask assuming
3333 /// the two vector operands have swapped position.
3334 static void CommuteVectorShuffleMask(SmallVectorImpl<int> &Mask,
3335 unsigned NumElems) {
3336 for (unsigned i = 0; i != NumElems; ++i) {
3340 else if (idx < (int)NumElems)
3341 Mask[i] = idx + NumElems;
3343 Mask[i] = idx - NumElems;
3347 /// isSHUFPMask - Return true if the specified VECTOR_SHUFFLE operand
3348 /// specifies a shuffle of elements that is suitable for input to 128/256-bit
3349 /// SHUFPS and SHUFPD. If Commuted is true, then it checks for sources to be
3350 /// reverse of what x86 shuffles want.
3351 static bool isSHUFPMask(ArrayRef<int> Mask, EVT VT, bool HasAVX,
3352 bool Commuted = false) {
3353 if (!HasAVX && VT.getSizeInBits() == 256)
3356 unsigned NumElems = VT.getVectorNumElements();
3357 unsigned NumLanes = VT.getSizeInBits()/128;
3358 unsigned NumLaneElems = NumElems/NumLanes;
3360 if (NumLaneElems != 2 && NumLaneElems != 4)
3363 // VSHUFPSY divides the resulting vector into 4 chunks.
3364 // The sources are also splitted into 4 chunks, and each destination
3365 // chunk must come from a different source chunk.
3367 // SRC1 => X7 X6 X5 X4 X3 X2 X1 X0
3368 // SRC2 => Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y9
3370 // DST => Y7..Y4, Y7..Y4, X7..X4, X7..X4,
3371 // Y3..Y0, Y3..Y0, X3..X0, X3..X0
3373 // VSHUFPDY divides the resulting vector into 4 chunks.
3374 // The sources are also splitted into 4 chunks, and each destination
3375 // chunk must come from a different source chunk.
3377 // SRC1 => X3 X2 X1 X0
3378 // SRC2 => Y3 Y2 Y1 Y0
3380 // DST => Y3..Y2, X3..X2, Y1..Y0, X1..X0
3382 unsigned HalfLaneElems = NumLaneElems/2;
3383 for (unsigned l = 0; l != NumElems; l += NumLaneElems) {
3384 for (unsigned i = 0; i != NumLaneElems; ++i) {
3385 int Idx = Mask[i+l];
3386 unsigned RngStart = l + ((Commuted == (i<HalfLaneElems)) ? NumElems : 0);
3387 if (!isUndefOrInRange(Idx, RngStart, RngStart+NumLaneElems))
3389 // For VSHUFPSY, the mask of the second half must be the same as the
3390 // first but with the appropriate offsets. This works in the same way as
3391 // VPERMILPS works with masks.
3392 if (NumElems != 8 || l == 0 || Mask[i] < 0)
3394 if (!isUndefOrEqual(Idx, Mask[i]+l))
3402 /// isMOVHLPSMask - Return true if the specified VECTOR_SHUFFLE operand
3403 /// specifies a shuffle of elements that is suitable for input to MOVHLPS.
3404 static bool isMOVHLPSMask(ArrayRef<int> Mask, EVT VT) {
3405 unsigned NumElems = VT.getVectorNumElements();
3407 if (VT.getSizeInBits() != 128)
3413 // Expect bit0 == 6, bit1 == 7, bit2 == 2, bit3 == 3
3414 return isUndefOrEqual(Mask[0], 6) &&
3415 isUndefOrEqual(Mask[1], 7) &&
3416 isUndefOrEqual(Mask[2], 2) &&
3417 isUndefOrEqual(Mask[3], 3);
3420 /// isMOVHLPS_v_undef_Mask - Special case of isMOVHLPSMask for canonical form
3421 /// of vector_shuffle v, v, <2, 3, 2, 3>, i.e. vector_shuffle v, undef,
3423 static bool isMOVHLPS_v_undef_Mask(ArrayRef<int> Mask, EVT VT) {
3424 unsigned NumElems = VT.getVectorNumElements();
3426 if (VT.getSizeInBits() != 128)
3432 return isUndefOrEqual(Mask[0], 2) &&
3433 isUndefOrEqual(Mask[1], 3) &&
3434 isUndefOrEqual(Mask[2], 2) &&
3435 isUndefOrEqual(Mask[3], 3);
3438 /// isMOVLPMask - Return true if the specified VECTOR_SHUFFLE operand
3439 /// specifies a shuffle of elements that is suitable for input to MOVLP{S|D}.
3440 static bool isMOVLPMask(ArrayRef<int> Mask, EVT VT) {
3441 if (VT.getSizeInBits() != 128)
3444 unsigned NumElems = VT.getVectorNumElements();
3446 if (NumElems != 2 && NumElems != 4)
3449 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
3450 if (!isUndefOrEqual(Mask[i], i + NumElems))
3453 for (unsigned i = NumElems/2, e = NumElems; i != e; ++i)
3454 if (!isUndefOrEqual(Mask[i], i))
3460 /// isMOVLHPSMask - Return true if the specified VECTOR_SHUFFLE operand
3461 /// specifies a shuffle of elements that is suitable for input to MOVLHPS.
3462 static bool isMOVLHPSMask(ArrayRef<int> Mask, EVT VT) {
3463 unsigned NumElems = VT.getVectorNumElements();
3465 if ((NumElems != 2 && NumElems != 4)
3466 || VT.getSizeInBits() > 128)
3469 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
3470 if (!isUndefOrEqual(Mask[i], i))
3473 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
3474 if (!isUndefOrEqual(Mask[i + e], i + NumElems))
3480 /// isUNPCKLMask - Return true if the specified VECTOR_SHUFFLE operand
3481 /// specifies a shuffle of elements that is suitable for input to UNPCKL.
3482 static bool isUNPCKLMask(ArrayRef<int> Mask, EVT VT,
3483 bool HasAVX2, bool V2IsSplat = false) {
3484 unsigned NumElts = VT.getVectorNumElements();
3486 assert((VT.is128BitVector() || VT.is256BitVector()) &&
3487 "Unsupported vector type for unpckh");
3489 if (VT.getSizeInBits() == 256 && NumElts != 4 && NumElts != 8 &&
3490 (!HasAVX2 || (NumElts != 16 && NumElts != 32)))
3493 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
3494 // independently on 128-bit lanes.
3495 unsigned NumLanes = VT.getSizeInBits()/128;
3496 unsigned NumLaneElts = NumElts/NumLanes;
3498 for (unsigned l = 0; l != NumLanes; ++l) {
3499 for (unsigned i = l*NumLaneElts, j = l*NumLaneElts;
3500 i != (l+1)*NumLaneElts;
3503 int BitI1 = Mask[i+1];
3504 if (!isUndefOrEqual(BitI, j))
3507 if (!isUndefOrEqual(BitI1, NumElts))
3510 if (!isUndefOrEqual(BitI1, j + NumElts))
3519 /// isUNPCKHMask - Return true if the specified VECTOR_SHUFFLE operand
3520 /// specifies a shuffle of elements that is suitable for input to UNPCKH.
3521 static bool isUNPCKHMask(ArrayRef<int> Mask, EVT VT,
3522 bool HasAVX2, bool V2IsSplat = false) {
3523 unsigned NumElts = VT.getVectorNumElements();
3525 assert((VT.is128BitVector() || VT.is256BitVector()) &&
3526 "Unsupported vector type for unpckh");
3528 if (VT.getSizeInBits() == 256 && NumElts != 4 && NumElts != 8 &&
3529 (!HasAVX2 || (NumElts != 16 && NumElts != 32)))
3532 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
3533 // independently on 128-bit lanes.
3534 unsigned NumLanes = VT.getSizeInBits()/128;
3535 unsigned NumLaneElts = NumElts/NumLanes;
3537 for (unsigned l = 0; l != NumLanes; ++l) {
3538 for (unsigned i = l*NumLaneElts, j = (l*NumLaneElts)+NumLaneElts/2;
3539 i != (l+1)*NumLaneElts; i += 2, ++j) {
3541 int BitI1 = Mask[i+1];
3542 if (!isUndefOrEqual(BitI, j))
3545 if (isUndefOrEqual(BitI1, NumElts))
3548 if (!isUndefOrEqual(BitI1, j+NumElts))
3556 /// isUNPCKL_v_undef_Mask - Special case of isUNPCKLMask for canonical form
3557 /// of vector_shuffle v, v, <0, 4, 1, 5>, i.e. vector_shuffle v, undef,
3559 static bool isUNPCKL_v_undef_Mask(ArrayRef<int> Mask, EVT VT,
3561 unsigned NumElts = VT.getVectorNumElements();
3563 assert((VT.is128BitVector() || VT.is256BitVector()) &&
3564 "Unsupported vector type for unpckh");
3566 if (VT.getSizeInBits() == 256 && NumElts != 4 && NumElts != 8 &&
3567 (!HasAVX2 || (NumElts != 16 && NumElts != 32)))
3570 // For 256-bit i64/f64, use MOVDDUPY instead, so reject the matching pattern
3571 // FIXME: Need a better way to get rid of this, there's no latency difference
3572 // between UNPCKLPD and MOVDDUP, the later should always be checked first and
3573 // the former later. We should also remove the "_undef" special mask.
3574 if (NumElts == 4 && VT.getSizeInBits() == 256)
3577 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
3578 // independently on 128-bit lanes.
3579 unsigned NumLanes = VT.getSizeInBits()/128;
3580 unsigned NumLaneElts = NumElts/NumLanes;
3582 for (unsigned l = 0; l != NumLanes; ++l) {
3583 for (unsigned i = l*NumLaneElts, j = l*NumLaneElts;
3584 i != (l+1)*NumLaneElts;
3587 int BitI1 = Mask[i+1];
3589 if (!isUndefOrEqual(BitI, j))
3591 if (!isUndefOrEqual(BitI1, j))
3599 /// isUNPCKH_v_undef_Mask - Special case of isUNPCKHMask for canonical form
3600 /// of vector_shuffle v, v, <2, 6, 3, 7>, i.e. vector_shuffle v, undef,
3602 static bool isUNPCKH_v_undef_Mask(ArrayRef<int> Mask, EVT VT, bool HasAVX2) {
3603 unsigned NumElts = VT.getVectorNumElements();
3605 assert((VT.is128BitVector() || VT.is256BitVector()) &&
3606 "Unsupported vector type for unpckh");
3608 if (VT.getSizeInBits() == 256 && NumElts != 4 && NumElts != 8 &&
3609 (!HasAVX2 || (NumElts != 16 && NumElts != 32)))
3612 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
3613 // independently on 128-bit lanes.
3614 unsigned NumLanes = VT.getSizeInBits()/128;
3615 unsigned NumLaneElts = NumElts/NumLanes;
3617 for (unsigned l = 0; l != NumLanes; ++l) {
3618 for (unsigned i = l*NumLaneElts, j = (l*NumLaneElts)+NumLaneElts/2;
3619 i != (l+1)*NumLaneElts; i += 2, ++j) {
3621 int BitI1 = Mask[i+1];
3622 if (!isUndefOrEqual(BitI, j))
3624 if (!isUndefOrEqual(BitI1, j))
3631 /// isMOVLMask - Return true if the specified VECTOR_SHUFFLE operand
3632 /// specifies a shuffle of elements that is suitable for input to MOVSS,
3633 /// MOVSD, and MOVD, i.e. setting the lowest element.
3634 static bool isMOVLMask(ArrayRef<int> Mask, EVT VT) {
3635 if (VT.getVectorElementType().getSizeInBits() < 32)
3637 if (VT.getSizeInBits() == 256)
3640 unsigned NumElts = VT.getVectorNumElements();
3642 if (!isUndefOrEqual(Mask[0], NumElts))
3645 for (unsigned i = 1; i != NumElts; ++i)
3646 if (!isUndefOrEqual(Mask[i], i))
3652 /// isVPERM2X128Mask - Match 256-bit shuffles where the elements are considered
3653 /// as permutations between 128-bit chunks or halves. As an example: this
3655 /// vector_shuffle <4, 5, 6, 7, 12, 13, 14, 15>
3656 /// The first half comes from the second half of V1 and the second half from the
3657 /// the second half of V2.
3658 static bool isVPERM2X128Mask(ArrayRef<int> Mask, EVT VT, bool HasAVX) {
3659 if (!HasAVX || VT.getSizeInBits() != 256)
3662 // The shuffle result is divided into half A and half B. In total the two
3663 // sources have 4 halves, namely: C, D, E, F. The final values of A and
3664 // B must come from C, D, E or F.
3665 unsigned HalfSize = VT.getVectorNumElements()/2;
3666 bool MatchA = false, MatchB = false;
3668 // Check if A comes from one of C, D, E, F.
3669 for (unsigned Half = 0; Half != 4; ++Half) {
3670 if (isSequentialOrUndefInRange(Mask, 0, HalfSize, Half*HalfSize)) {
3676 // Check if B comes from one of C, D, E, F.
3677 for (unsigned Half = 0; Half != 4; ++Half) {
3678 if (isSequentialOrUndefInRange(Mask, HalfSize, HalfSize, Half*HalfSize)) {
3684 return MatchA && MatchB;
3687 /// getShuffleVPERM2X128Immediate - Return the appropriate immediate to shuffle
3688 /// the specified VECTOR_MASK mask with VPERM2F128/VPERM2I128 instructions.
3689 static unsigned getShuffleVPERM2X128Immediate(ShuffleVectorSDNode *SVOp) {
3690 EVT VT = SVOp->getValueType(0);
3692 unsigned HalfSize = VT.getVectorNumElements()/2;
3694 unsigned FstHalf = 0, SndHalf = 0;
3695 for (unsigned i = 0; i < HalfSize; ++i) {
3696 if (SVOp->getMaskElt(i) > 0) {
3697 FstHalf = SVOp->getMaskElt(i)/HalfSize;
3701 for (unsigned i = HalfSize; i < HalfSize*2; ++i) {
3702 if (SVOp->getMaskElt(i) > 0) {
3703 SndHalf = SVOp->getMaskElt(i)/HalfSize;
3708 return (FstHalf | (SndHalf << 4));
3711 /// isVPERMILPMask - Return true if the specified VECTOR_SHUFFLE operand
3712 /// specifies a shuffle of elements that is suitable for input to VPERMILPD*.
3713 /// Note that VPERMIL mask matching is different depending whether theunderlying
3714 /// type is 32 or 64. In the VPERMILPS the high half of the mask should point
3715 /// to the same elements of the low, but to the higher half of the source.
3716 /// In VPERMILPD the two lanes could be shuffled independently of each other
3717 /// with the same restriction that lanes can't be crossed. Also handles PSHUFDY.
3718 static bool isVPERMILPMask(ArrayRef<int> Mask, EVT VT, bool HasAVX) {
3722 unsigned NumElts = VT.getVectorNumElements();
3723 // Only match 256-bit with 32/64-bit types
3724 if (VT.getSizeInBits() != 256 || (NumElts != 4 && NumElts != 8))
3727 unsigned NumLanes = VT.getSizeInBits()/128;
3728 unsigned LaneSize = NumElts/NumLanes;
3729 for (unsigned l = 0; l != NumElts; l += LaneSize) {
3730 for (unsigned i = 0; i != LaneSize; ++i) {
3731 if (!isUndefOrInRange(Mask[i+l], l, l+LaneSize))
3733 if (NumElts != 8 || l == 0)
3735 // VPERMILPS handling
3738 if (!isUndefOrEqual(Mask[i+l], Mask[i]+l))
3746 /// isCommutedMOVLMask - Returns true if the shuffle mask is except the reverse
3747 /// of what x86 movss want. X86 movs requires the lowest element to be lowest
3748 /// element of vector 2 and the other elements to come from vector 1 in order.
3749 static bool isCommutedMOVLMask(ArrayRef<int> Mask, EVT VT,
3750 bool V2IsSplat = false, bool V2IsUndef = false) {
3751 unsigned NumOps = VT.getVectorNumElements();
3752 if (VT.getSizeInBits() == 256)
3754 if (NumOps != 2 && NumOps != 4 && NumOps != 8 && NumOps != 16)
3757 if (!isUndefOrEqual(Mask[0], 0))
3760 for (unsigned i = 1; i != NumOps; ++i)
3761 if (!(isUndefOrEqual(Mask[i], i+NumOps) ||
3762 (V2IsUndef && isUndefOrInRange(Mask[i], NumOps, NumOps*2)) ||
3763 (V2IsSplat && isUndefOrEqual(Mask[i], NumOps))))
3769 /// isMOVSHDUPMask - Return true if the specified VECTOR_SHUFFLE operand
3770 /// specifies a shuffle of elements that is suitable for input to MOVSHDUP.
3771 /// Masks to match: <1, 1, 3, 3> or <1, 1, 3, 3, 5, 5, 7, 7>
3772 static bool isMOVSHDUPMask(ArrayRef<int> Mask, EVT VT,
3773 const X86Subtarget *Subtarget) {
3774 if (!Subtarget->hasSSE3())
3777 unsigned NumElems = VT.getVectorNumElements();
3779 if ((VT.getSizeInBits() == 128 && NumElems != 4) ||
3780 (VT.getSizeInBits() == 256 && NumElems != 8))
3783 // "i+1" is the value the indexed mask element must have
3784 for (unsigned i = 0; i != NumElems; i += 2)
3785 if (!isUndefOrEqual(Mask[i], i+1) ||
3786 !isUndefOrEqual(Mask[i+1], i+1))
3792 /// isMOVSLDUPMask - Return true if the specified VECTOR_SHUFFLE operand
3793 /// specifies a shuffle of elements that is suitable for input to MOVSLDUP.
3794 /// Masks to match: <0, 0, 2, 2> or <0, 0, 2, 2, 4, 4, 6, 6>
3795 static bool isMOVSLDUPMask(ArrayRef<int> Mask, EVT VT,
3796 const X86Subtarget *Subtarget) {
3797 if (!Subtarget->hasSSE3())
3800 unsigned NumElems = VT.getVectorNumElements();
3802 if ((VT.getSizeInBits() == 128 && NumElems != 4) ||
3803 (VT.getSizeInBits() == 256 && NumElems != 8))
3806 // "i" is the value the indexed mask element must have
3807 for (unsigned i = 0; i != NumElems; i += 2)
3808 if (!isUndefOrEqual(Mask[i], i) ||
3809 !isUndefOrEqual(Mask[i+1], i))
3815 /// isMOVDDUPYMask - Return true if the specified VECTOR_SHUFFLE operand
3816 /// specifies a shuffle of elements that is suitable for input to 256-bit
3817 /// version of MOVDDUP.
3818 static bool isMOVDDUPYMask(ArrayRef<int> Mask, EVT VT, bool HasAVX) {
3819 unsigned NumElts = VT.getVectorNumElements();
3821 if (!HasAVX || VT.getSizeInBits() != 256 || NumElts != 4)
3824 for (unsigned i = 0; i != NumElts/2; ++i)
3825 if (!isUndefOrEqual(Mask[i], 0))
3827 for (unsigned i = NumElts/2; i != NumElts; ++i)
3828 if (!isUndefOrEqual(Mask[i], NumElts/2))
3833 /// isMOVDDUPMask - Return true if the specified VECTOR_SHUFFLE operand
3834 /// specifies a shuffle of elements that is suitable for input to 128-bit
3835 /// version of MOVDDUP.
3836 static bool isMOVDDUPMask(ArrayRef<int> Mask, EVT VT) {
3837 if (VT.getSizeInBits() != 128)
3840 unsigned e = VT.getVectorNumElements() / 2;
3841 for (unsigned i = 0; i != e; ++i)
3842 if (!isUndefOrEqual(Mask[i], i))
3844 for (unsigned i = 0; i != e; ++i)
3845 if (!isUndefOrEqual(Mask[e+i], i))
3850 /// isVEXTRACTF128Index - Return true if the specified
3851 /// EXTRACT_SUBVECTOR operand specifies a vector extract that is
3852 /// suitable for input to VEXTRACTF128.
3853 bool X86::isVEXTRACTF128Index(SDNode *N) {
3854 if (!isa<ConstantSDNode>(N->getOperand(1).getNode()))
3857 // The index should be aligned on a 128-bit boundary.
3859 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
3861 unsigned VL = N->getValueType(0).getVectorNumElements();
3862 unsigned VBits = N->getValueType(0).getSizeInBits();
3863 unsigned ElSize = VBits / VL;
3864 bool Result = (Index * ElSize) % 128 == 0;
3869 /// isVINSERTF128Index - Return true if the specified INSERT_SUBVECTOR
3870 /// operand specifies a subvector insert that is suitable for input to
3872 bool X86::isVINSERTF128Index(SDNode *N) {
3873 if (!isa<ConstantSDNode>(N->getOperand(2).getNode()))
3876 // The index should be aligned on a 128-bit boundary.
3878 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
3880 unsigned VL = N->getValueType(0).getVectorNumElements();
3881 unsigned VBits = N->getValueType(0).getSizeInBits();
3882 unsigned ElSize = VBits / VL;
3883 bool Result = (Index * ElSize) % 128 == 0;
3888 /// getShuffleSHUFImmediate - Return the appropriate immediate to shuffle
3889 /// the specified VECTOR_SHUFFLE mask with PSHUF* and SHUFP* instructions.
3890 /// Handles 128-bit and 256-bit.
3891 static unsigned getShuffleSHUFImmediate(ShuffleVectorSDNode *N) {
3892 EVT VT = N->getValueType(0);
3894 assert((VT.is128BitVector() || VT.is256BitVector()) &&
3895 "Unsupported vector type for PSHUF/SHUFP");
3897 // Handle 128 and 256-bit vector lengths. AVX defines PSHUF/SHUFP to operate
3898 // independently on 128-bit lanes.
3899 unsigned NumElts = VT.getVectorNumElements();
3900 unsigned NumLanes = VT.getSizeInBits()/128;
3901 unsigned NumLaneElts = NumElts/NumLanes;
3903 assert((NumLaneElts == 2 || NumLaneElts == 4) &&
3904 "Only supports 2 or 4 elements per lane");
3906 unsigned Shift = (NumLaneElts == 4) ? 1 : 0;
3908 for (unsigned i = 0; i != NumElts; ++i) {
3909 int Elt = N->getMaskElt(i);
3910 if (Elt < 0) continue;
3911 Elt &= NumLaneElts - 1;
3912 unsigned ShAmt = (i << Shift) % 8;
3913 Mask |= Elt << ShAmt;
3919 /// getShufflePSHUFHWImmediate - Return the appropriate immediate to shuffle
3920 /// the specified VECTOR_SHUFFLE mask with the PSHUFHW instruction.
3921 static unsigned getShufflePSHUFHWImmediate(ShuffleVectorSDNode *N) {
3922 EVT VT = N->getValueType(0);
3924 assert((VT == MVT::v8i16 || VT == MVT::v16i16) &&
3925 "Unsupported vector type for PSHUFHW");
3927 unsigned NumElts = VT.getVectorNumElements();
3930 for (unsigned l = 0; l != NumElts; l += 8) {
3931 // 8 nodes per lane, but we only care about the last 4.
3932 for (unsigned i = 0; i < 4; ++i) {
3933 int Elt = N->getMaskElt(l+i+4);
3934 if (Elt < 0) continue;
3935 Elt &= 0x3; // only 2-bits.
3936 Mask |= Elt << (i * 2);
3943 /// getShufflePSHUFLWImmediate - Return the appropriate immediate to shuffle
3944 /// the specified VECTOR_SHUFFLE mask with the PSHUFLW instruction.
3945 static unsigned getShufflePSHUFLWImmediate(ShuffleVectorSDNode *N) {
3946 EVT VT = N->getValueType(0);
3948 assert((VT == MVT::v8i16 || VT == MVT::v16i16) &&
3949 "Unsupported vector type for PSHUFHW");
3951 unsigned NumElts = VT.getVectorNumElements();
3954 for (unsigned l = 0; l != NumElts; l += 8) {
3955 // 8 nodes per lane, but we only care about the first 4.
3956 for (unsigned i = 0; i < 4; ++i) {
3957 int Elt = N->getMaskElt(l+i);
3958 if (Elt < 0) continue;
3959 Elt &= 0x3; // only 2-bits
3960 Mask |= Elt << (i * 2);
3967 /// getShufflePALIGNRImmediate - Return the appropriate immediate to shuffle
3968 /// the specified VECTOR_SHUFFLE mask with the PALIGNR instruction.
3969 static unsigned getShufflePALIGNRImmediate(ShuffleVectorSDNode *SVOp) {
3970 EVT VT = SVOp->getValueType(0);
3971 unsigned EltSize = VT.getVectorElementType().getSizeInBits() >> 3;
3973 unsigned NumElts = VT.getVectorNumElements();
3974 unsigned NumLanes = VT.getSizeInBits()/128;
3975 unsigned NumLaneElts = NumElts/NumLanes;
3979 for (i = 0; i != NumElts; ++i) {
3980 Val = SVOp->getMaskElt(i);
3984 if (Val >= (int)NumElts)
3985 Val -= NumElts - NumLaneElts;
3987 assert(Val - i > 0 && "PALIGNR imm should be positive");
3988 return (Val - i) * EltSize;
3991 /// getExtractVEXTRACTF128Immediate - Return the appropriate immediate
3992 /// to extract the specified EXTRACT_SUBVECTOR index with VEXTRACTF128
3994 unsigned X86::getExtractVEXTRACTF128Immediate(SDNode *N) {
3995 if (!isa<ConstantSDNode>(N->getOperand(1).getNode()))
3996 llvm_unreachable("Illegal extract subvector for VEXTRACTF128");
3999 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
4001 EVT VecVT = N->getOperand(0).getValueType();
4002 EVT ElVT = VecVT.getVectorElementType();
4004 unsigned NumElemsPerChunk = 128 / ElVT.getSizeInBits();
4005 return Index / NumElemsPerChunk;
4008 /// getInsertVINSERTF128Immediate - Return the appropriate immediate
4009 /// to insert at the specified INSERT_SUBVECTOR index with VINSERTF128
4011 unsigned X86::getInsertVINSERTF128Immediate(SDNode *N) {
4012 if (!isa<ConstantSDNode>(N->getOperand(2).getNode()))
4013 llvm_unreachable("Illegal insert subvector for VINSERTF128");
4016 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
4018 EVT VecVT = N->getValueType(0);
4019 EVT ElVT = VecVT.getVectorElementType();
4021 unsigned NumElemsPerChunk = 128 / ElVT.getSizeInBits();
4022 return Index / NumElemsPerChunk;
4025 /// getShuffleCLImmediate - Return the appropriate immediate to shuffle
4026 /// the specified VECTOR_SHUFFLE mask with VPERMQ and VPERMPD instructions.
4027 /// Handles 256-bit.
4028 static unsigned getShuffleCLImmediate(ShuffleVectorSDNode *N) {
4029 EVT VT = N->getValueType(0);
4031 unsigned NumElts = VT.getVectorNumElements();
4033 assert((VT.is256BitVector() && NumElts == 4) &&
4034 "Unsupported vector type for VPERMQ/VPERMPD");
4037 for (unsigned i = 0; i != NumElts; ++i) {
4038 int Elt = N->getMaskElt(i);
4041 Mask |= Elt << (i*2);
4046 /// isZeroNode - Returns true if Elt is a constant zero or a floating point
4048 bool X86::isZeroNode(SDValue Elt) {
4049 return ((isa<ConstantSDNode>(Elt) &&
4050 cast<ConstantSDNode>(Elt)->isNullValue()) ||
4051 (isa<ConstantFPSDNode>(Elt) &&
4052 cast<ConstantFPSDNode>(Elt)->getValueAPF().isPosZero()));
4055 /// CommuteVectorShuffle - Swap vector_shuffle operands as well as values in
4056 /// their permute mask.
4057 static SDValue CommuteVectorShuffle(ShuffleVectorSDNode *SVOp,
4058 SelectionDAG &DAG) {
4059 EVT VT = SVOp->getValueType(0);
4060 unsigned NumElems = VT.getVectorNumElements();
4061 SmallVector<int, 8> MaskVec;
4063 for (unsigned i = 0; i != NumElems; ++i) {
4064 int Idx = SVOp->getMaskElt(i);
4066 if (Idx < (int)NumElems)
4071 MaskVec.push_back(Idx);
4073 return DAG.getVectorShuffle(VT, SVOp->getDebugLoc(), SVOp->getOperand(1),
4074 SVOp->getOperand(0), &MaskVec[0]);
4077 /// ShouldXformToMOVHLPS - Return true if the node should be transformed to
4078 /// match movhlps. The lower half elements should come from upper half of
4079 /// V1 (and in order), and the upper half elements should come from the upper
4080 /// half of V2 (and in order).
4081 static bool ShouldXformToMOVHLPS(ArrayRef<int> Mask, EVT VT) {
4082 if (VT.getSizeInBits() != 128)
4084 if (VT.getVectorNumElements() != 4)
4086 for (unsigned i = 0, e = 2; i != e; ++i)
4087 if (!isUndefOrEqual(Mask[i], i+2))
4089 for (unsigned i = 2; i != 4; ++i)
4090 if (!isUndefOrEqual(Mask[i], i+4))
4095 /// isScalarLoadToVector - Returns true if the node is a scalar load that
4096 /// is promoted to a vector. It also returns the LoadSDNode by reference if
4098 static bool isScalarLoadToVector(SDNode *N, LoadSDNode **LD = NULL) {
4099 if (N->getOpcode() != ISD::SCALAR_TO_VECTOR)
4101 N = N->getOperand(0).getNode();
4102 if (!ISD::isNON_EXTLoad(N))
4105 *LD = cast<LoadSDNode>(N);
4109 // Test whether the given value is a vector value which will be legalized
4111 static bool WillBeConstantPoolLoad(SDNode *N) {
4112 if (N->getOpcode() != ISD::BUILD_VECTOR)
4115 // Check for any non-constant elements.
4116 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
4117 switch (N->getOperand(i).getNode()->getOpcode()) {
4119 case ISD::ConstantFP:
4126 // Vectors of all-zeros and all-ones are materialized with special
4127 // instructions rather than being loaded.
4128 return !ISD::isBuildVectorAllZeros(N) &&
4129 !ISD::isBuildVectorAllOnes(N);
4132 /// ShouldXformToMOVLP{S|D} - Return true if the node should be transformed to
4133 /// match movlp{s|d}. The lower half elements should come from lower half of
4134 /// V1 (and in order), and the upper half elements should come from the upper
4135 /// half of V2 (and in order). And since V1 will become the source of the
4136 /// MOVLP, it must be either a vector load or a scalar load to vector.
4137 static bool ShouldXformToMOVLP(SDNode *V1, SDNode *V2,
4138 ArrayRef<int> Mask, EVT VT) {
4139 if (VT.getSizeInBits() != 128)
4142 if (!ISD::isNON_EXTLoad(V1) && !isScalarLoadToVector(V1))
4144 // Is V2 is a vector load, don't do this transformation. We will try to use
4145 // load folding shufps op.
4146 if (ISD::isNON_EXTLoad(V2) || WillBeConstantPoolLoad(V2))
4149 unsigned NumElems = VT.getVectorNumElements();
4151 if (NumElems != 2 && NumElems != 4)
4153 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
4154 if (!isUndefOrEqual(Mask[i], i))
4156 for (unsigned i = NumElems/2, e = NumElems; i != e; ++i)
4157 if (!isUndefOrEqual(Mask[i], i+NumElems))
4162 /// isSplatVector - Returns true if N is a BUILD_VECTOR node whose elements are
4164 static bool isSplatVector(SDNode *N) {
4165 if (N->getOpcode() != ISD::BUILD_VECTOR)
4168 SDValue SplatValue = N->getOperand(0);
4169 for (unsigned i = 1, e = N->getNumOperands(); i != e; ++i)
4170 if (N->getOperand(i) != SplatValue)
4175 /// isZeroShuffle - Returns true if N is a VECTOR_SHUFFLE that can be resolved
4176 /// to an zero vector.
4177 /// FIXME: move to dag combiner / method on ShuffleVectorSDNode
4178 static bool isZeroShuffle(ShuffleVectorSDNode *N) {
4179 SDValue V1 = N->getOperand(0);
4180 SDValue V2 = N->getOperand(1);
4181 unsigned NumElems = N->getValueType(0).getVectorNumElements();
4182 for (unsigned i = 0; i != NumElems; ++i) {
4183 int Idx = N->getMaskElt(i);
4184 if (Idx >= (int)NumElems) {
4185 unsigned Opc = V2.getOpcode();
4186 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V2.getNode()))
4188 if (Opc != ISD::BUILD_VECTOR ||
4189 !X86::isZeroNode(V2.getOperand(Idx-NumElems)))
4191 } else if (Idx >= 0) {
4192 unsigned Opc = V1.getOpcode();
4193 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V1.getNode()))
4195 if (Opc != ISD::BUILD_VECTOR ||
4196 !X86::isZeroNode(V1.getOperand(Idx)))
4203 /// getZeroVector - Returns a vector of specified type with all zero elements.
4205 static SDValue getZeroVector(EVT VT, const X86Subtarget *Subtarget,
4206 SelectionDAG &DAG, DebugLoc dl) {
4207 assert(VT.isVector() && "Expected a vector type");
4208 unsigned Size = VT.getSizeInBits();
4210 // Always build SSE zero vectors as <4 x i32> bitcasted
4211 // to their dest type. This ensures they get CSE'd.
4213 if (Size == 128) { // SSE
4214 if (Subtarget->hasSSE2()) { // SSE2
4215 SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
4216 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4218 SDValue Cst = DAG.getTargetConstantFP(+0.0, MVT::f32);
4219 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4f32, Cst, Cst, Cst, Cst);
4221 } else if (Size == 256) { // AVX
4222 if (Subtarget->hasAVX2()) { // AVX2
4223 SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
4224 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4225 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops, 8);
4227 // 256-bit logic and arithmetic instructions in AVX are all
4228 // floating-point, no support for integer ops. Emit fp zeroed vectors.
4229 SDValue Cst = DAG.getTargetConstantFP(+0.0, MVT::f32);
4230 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4231 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8f32, Ops, 8);
4234 llvm_unreachable("Unexpected vector type");
4236 return DAG.getNode(ISD::BITCAST, dl, VT, Vec);
4239 /// getOnesVector - Returns a vector of specified type with all bits set.
4240 /// Always build ones vectors as <4 x i32> or <8 x i32>. For 256-bit types with
4241 /// no AVX2 supprt, use two <4 x i32> inserted in a <8 x i32> appropriately.
4242 /// Then bitcast to their original type, ensuring they get CSE'd.
4243 static SDValue getOnesVector(EVT VT, bool HasAVX2, SelectionDAG &DAG,
4245 assert(VT.isVector() && "Expected a vector type");
4246 unsigned Size = VT.getSizeInBits();
4248 SDValue Cst = DAG.getTargetConstant(~0U, MVT::i32);
4251 if (HasAVX2) { // AVX2
4252 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4253 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops, 8);
4255 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4256 Vec = Concat128BitVectors(Vec, Vec, MVT::v8i32, 8, DAG, dl);
4258 } else if (Size == 128) {
4259 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4261 llvm_unreachable("Unexpected vector type");
4263 return DAG.getNode(ISD::BITCAST, dl, VT, Vec);
4266 /// NormalizeMask - V2 is a splat, modify the mask (if needed) so all elements
4267 /// that point to V2 points to its first element.
4268 static void NormalizeMask(SmallVectorImpl<int> &Mask, unsigned NumElems) {
4269 for (unsigned i = 0; i != NumElems; ++i) {
4270 if (Mask[i] > (int)NumElems) {
4276 /// getMOVLMask - Returns a vector_shuffle mask for an movs{s|d}, movd
4277 /// operation of specified width.
4278 static SDValue getMOVL(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1,
4280 unsigned NumElems = VT.getVectorNumElements();
4281 SmallVector<int, 8> Mask;
4282 Mask.push_back(NumElems);
4283 for (unsigned i = 1; i != NumElems; ++i)
4285 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
4288 /// getUnpackl - Returns a vector_shuffle node for an unpackl operation.
4289 static SDValue getUnpackl(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1,
4291 unsigned NumElems = VT.getVectorNumElements();
4292 SmallVector<int, 8> Mask;
4293 for (unsigned i = 0, e = NumElems/2; i != e; ++i) {
4295 Mask.push_back(i + NumElems);
4297 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
4300 /// getUnpackh - Returns a vector_shuffle node for an unpackh operation.
4301 static SDValue getUnpackh(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1,
4303 unsigned NumElems = VT.getVectorNumElements();
4304 SmallVector<int, 8> Mask;
4305 for (unsigned i = 0, Half = NumElems/2; i != Half; ++i) {
4306 Mask.push_back(i + Half);
4307 Mask.push_back(i + NumElems + Half);
4309 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
4312 // PromoteSplati8i16 - All i16 and i8 vector types can't be used directly by
4313 // a generic shuffle instruction because the target has no such instructions.
4314 // Generate shuffles which repeat i16 and i8 several times until they can be
4315 // represented by v4f32 and then be manipulated by target suported shuffles.
4316 static SDValue PromoteSplati8i16(SDValue V, SelectionDAG &DAG, int &EltNo) {
4317 EVT VT = V.getValueType();
4318 int NumElems = VT.getVectorNumElements();
4319 DebugLoc dl = V.getDebugLoc();
4321 while (NumElems > 4) {
4322 if (EltNo < NumElems/2) {
4323 V = getUnpackl(DAG, dl, VT, V, V);
4325 V = getUnpackh(DAG, dl, VT, V, V);
4326 EltNo -= NumElems/2;
4333 /// getLegalSplat - Generate a legal splat with supported x86 shuffles
4334 static SDValue getLegalSplat(SelectionDAG &DAG, SDValue V, int EltNo) {
4335 EVT VT = V.getValueType();
4336 DebugLoc dl = V.getDebugLoc();
4337 unsigned Size = VT.getSizeInBits();
4340 V = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V);
4341 int SplatMask[4] = { EltNo, EltNo, EltNo, EltNo };
4342 V = DAG.getVectorShuffle(MVT::v4f32, dl, V, DAG.getUNDEF(MVT::v4f32),
4344 } else if (Size == 256) {
4345 // To use VPERMILPS to splat scalars, the second half of indicies must
4346 // refer to the higher part, which is a duplication of the lower one,
4347 // because VPERMILPS can only handle in-lane permutations.
4348 int SplatMask[8] = { EltNo, EltNo, EltNo, EltNo,
4349 EltNo+4, EltNo+4, EltNo+4, EltNo+4 };
4351 V = DAG.getNode(ISD::BITCAST, dl, MVT::v8f32, V);
4352 V = DAG.getVectorShuffle(MVT::v8f32, dl, V, DAG.getUNDEF(MVT::v8f32),
4355 llvm_unreachable("Vector size not supported");
4357 return DAG.getNode(ISD::BITCAST, dl, VT, V);
4360 /// PromoteSplat - Splat is promoted to target supported vector shuffles.
4361 static SDValue PromoteSplat(ShuffleVectorSDNode *SV, SelectionDAG &DAG) {
4362 EVT SrcVT = SV->getValueType(0);
4363 SDValue V1 = SV->getOperand(0);
4364 DebugLoc dl = SV->getDebugLoc();
4366 int EltNo = SV->getSplatIndex();
4367 int NumElems = SrcVT.getVectorNumElements();
4368 unsigned Size = SrcVT.getSizeInBits();
4370 assert(((Size == 128 && NumElems > 4) || Size == 256) &&
4371 "Unknown how to promote splat for type");
4373 // Extract the 128-bit part containing the splat element and update
4374 // the splat element index when it refers to the higher register.
4376 V1 = Extract128BitVector(V1, EltNo, DAG, dl);
4377 if (EltNo >= NumElems/2)
4378 EltNo -= NumElems/2;
4381 // All i16 and i8 vector types can't be used directly by a generic shuffle
4382 // instruction because the target has no such instruction. Generate shuffles
4383 // which repeat i16 and i8 several times until they fit in i32, and then can
4384 // be manipulated by target suported shuffles.
4385 EVT EltVT = SrcVT.getVectorElementType();
4386 if (EltVT == MVT::i8 || EltVT == MVT::i16)
4387 V1 = PromoteSplati8i16(V1, DAG, EltNo);
4389 // Recreate the 256-bit vector and place the same 128-bit vector
4390 // into the low and high part. This is necessary because we want
4391 // to use VPERM* to shuffle the vectors
4393 V1 = DAG.getNode(ISD::CONCAT_VECTORS, dl, SrcVT, V1, V1);
4396 return getLegalSplat(DAG, V1, EltNo);
4399 /// getShuffleVectorZeroOrUndef - Return a vector_shuffle of the specified
4400 /// vector of zero or undef vector. This produces a shuffle where the low
4401 /// element of V2 is swizzled into the zero/undef vector, landing at element
4402 /// Idx. This produces a shuffle mask like 4,1,2,3 (idx=0) or 0,1,2,4 (idx=3).
4403 static SDValue getShuffleVectorZeroOrUndef(SDValue V2, unsigned Idx,
4405 const X86Subtarget *Subtarget,
4406 SelectionDAG &DAG) {
4407 EVT VT = V2.getValueType();
4409 ? getZeroVector(VT, Subtarget, DAG, V2.getDebugLoc()) : DAG.getUNDEF(VT);
4410 unsigned NumElems = VT.getVectorNumElements();
4411 SmallVector<int, 16> MaskVec;
4412 for (unsigned i = 0; i != NumElems; ++i)
4413 // If this is the insertion idx, put the low elt of V2 here.
4414 MaskVec.push_back(i == Idx ? NumElems : i);
4415 return DAG.getVectorShuffle(VT, V2.getDebugLoc(), V1, V2, &MaskVec[0]);
4418 /// getTargetShuffleMask - Calculates the shuffle mask corresponding to the
4419 /// target specific opcode. Returns true if the Mask could be calculated.
4420 /// Sets IsUnary to true if only uses one source.
4421 static bool getTargetShuffleMask(SDNode *N, MVT VT,
4422 SmallVectorImpl<int> &Mask, bool &IsUnary) {
4423 unsigned NumElems = VT.getVectorNumElements();
4427 switch(N->getOpcode()) {
4429 ImmN = N->getOperand(N->getNumOperands()-1);
4430 DecodeSHUFPMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4432 case X86ISD::UNPCKH:
4433 DecodeUNPCKHMask(VT, Mask);
4435 case X86ISD::UNPCKL:
4436 DecodeUNPCKLMask(VT, Mask);
4438 case X86ISD::MOVHLPS:
4439 DecodeMOVHLPSMask(NumElems, Mask);
4441 case X86ISD::MOVLHPS:
4442 DecodeMOVLHPSMask(NumElems, Mask);
4444 case X86ISD::PSHUFD:
4445 case X86ISD::VPERMILP:
4446 ImmN = N->getOperand(N->getNumOperands()-1);
4447 DecodePSHUFMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4450 case X86ISD::PSHUFHW:
4451 ImmN = N->getOperand(N->getNumOperands()-1);
4452 DecodePSHUFHWMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4455 case X86ISD::PSHUFLW:
4456 ImmN = N->getOperand(N->getNumOperands()-1);
4457 DecodePSHUFLWMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4460 case X86ISD::VPERMI:
4461 ImmN = N->getOperand(N->getNumOperands()-1);
4462 DecodeVPERMMask(cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4466 case X86ISD::MOVSD: {
4467 // The index 0 always comes from the first element of the second source,
4468 // this is why MOVSS and MOVSD are used in the first place. The other
4469 // elements come from the other positions of the first source vector
4470 Mask.push_back(NumElems);
4471 for (unsigned i = 1; i != NumElems; ++i) {
4476 case X86ISD::VPERM2X128:
4477 ImmN = N->getOperand(N->getNumOperands()-1);
4478 DecodeVPERM2X128Mask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4479 if (Mask.empty()) return false;
4481 case X86ISD::MOVDDUP:
4482 case X86ISD::MOVLHPD:
4483 case X86ISD::MOVLPD:
4484 case X86ISD::MOVLPS:
4485 case X86ISD::MOVSHDUP:
4486 case X86ISD::MOVSLDUP:
4487 case X86ISD::PALIGN:
4488 // Not yet implemented
4490 default: llvm_unreachable("unknown target shuffle node");
4496 /// getShuffleScalarElt - Returns the scalar element that will make up the ith
4497 /// element of the result of the vector shuffle.
4498 static SDValue getShuffleScalarElt(SDNode *N, unsigned Index, SelectionDAG &DAG,
4501 return SDValue(); // Limit search depth.
4503 SDValue V = SDValue(N, 0);
4504 EVT VT = V.getValueType();
4505 unsigned Opcode = V.getOpcode();
4507 // Recurse into ISD::VECTOR_SHUFFLE node to find scalars.
4508 if (const ShuffleVectorSDNode *SV = dyn_cast<ShuffleVectorSDNode>(N)) {
4509 int Elt = SV->getMaskElt(Index);
4512 return DAG.getUNDEF(VT.getVectorElementType());
4514 unsigned NumElems = VT.getVectorNumElements();
4515 SDValue NewV = (Elt < (int)NumElems) ? SV->getOperand(0)
4516 : SV->getOperand(1);
4517 return getShuffleScalarElt(NewV.getNode(), Elt % NumElems, DAG, Depth+1);
4520 // Recurse into target specific vector shuffles to find scalars.
4521 if (isTargetShuffle(Opcode)) {
4522 MVT ShufVT = V.getValueType().getSimpleVT();
4523 unsigned NumElems = ShufVT.getVectorNumElements();
4524 SmallVector<int, 16> ShuffleMask;
4528 if (!getTargetShuffleMask(N, ShufVT, ShuffleMask, IsUnary))
4531 int Elt = ShuffleMask[Index];
4533 return DAG.getUNDEF(ShufVT.getVectorElementType());
4535 SDValue NewV = (Elt < (int)NumElems) ? N->getOperand(0)
4537 return getShuffleScalarElt(NewV.getNode(), Elt % NumElems, DAG,
4541 // Actual nodes that may contain scalar elements
4542 if (Opcode == ISD::BITCAST) {
4543 V = V.getOperand(0);
4544 EVT SrcVT = V.getValueType();
4545 unsigned NumElems = VT.getVectorNumElements();
4547 if (!SrcVT.isVector() || SrcVT.getVectorNumElements() != NumElems)
4551 if (V.getOpcode() == ISD::SCALAR_TO_VECTOR)
4552 return (Index == 0) ? V.getOperand(0)
4553 : DAG.getUNDEF(VT.getVectorElementType());
4555 if (V.getOpcode() == ISD::BUILD_VECTOR)
4556 return V.getOperand(Index);
4561 /// getNumOfConsecutiveZeros - Return the number of elements of a vector
4562 /// shuffle operation which come from a consecutively from a zero. The
4563 /// search can start in two different directions, from left or right.
4565 unsigned getNumOfConsecutiveZeros(ShuffleVectorSDNode *SVOp, unsigned NumElems,
4566 bool ZerosFromLeft, SelectionDAG &DAG) {
4568 for (i = 0; i != NumElems; ++i) {
4569 unsigned Index = ZerosFromLeft ? i : NumElems-i-1;
4570 SDValue Elt = getShuffleScalarElt(SVOp, Index, DAG, 0);
4571 if (!(Elt.getNode() &&
4572 (Elt.getOpcode() == ISD::UNDEF || X86::isZeroNode(Elt))))
4579 /// isShuffleMaskConsecutive - Check if the shuffle mask indicies [MaskI, MaskE)
4580 /// correspond consecutively to elements from one of the vector operands,
4581 /// starting from its index OpIdx. Also tell OpNum which source vector operand.
4583 bool isShuffleMaskConsecutive(ShuffleVectorSDNode *SVOp,
4584 unsigned MaskI, unsigned MaskE, unsigned OpIdx,
4585 unsigned NumElems, unsigned &OpNum) {
4586 bool SeenV1 = false;
4587 bool SeenV2 = false;
4589 for (unsigned i = MaskI; i != MaskE; ++i, ++OpIdx) {
4590 int Idx = SVOp->getMaskElt(i);
4591 // Ignore undef indicies
4595 if (Idx < (int)NumElems)
4600 // Only accept consecutive elements from the same vector
4601 if ((Idx % NumElems != OpIdx) || (SeenV1 && SeenV2))
4605 OpNum = SeenV1 ? 0 : 1;
4609 /// isVectorShiftRight - Returns true if the shuffle can be implemented as a
4610 /// logical left shift of a vector.
4611 static bool isVectorShiftRight(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
4612 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
4613 unsigned NumElems = SVOp->getValueType(0).getVectorNumElements();
4614 unsigned NumZeros = getNumOfConsecutiveZeros(SVOp, NumElems,
4615 false /* check zeros from right */, DAG);
4621 // Considering the elements in the mask that are not consecutive zeros,
4622 // check if they consecutively come from only one of the source vectors.
4624 // V1 = {X, A, B, C} 0
4626 // vector_shuffle V1, V2 <1, 2, 3, X>
4628 if (!isShuffleMaskConsecutive(SVOp,
4629 0, // Mask Start Index
4630 NumElems-NumZeros, // Mask End Index(exclusive)
4631 NumZeros, // Where to start looking in the src vector
4632 NumElems, // Number of elements in vector
4633 OpSrc)) // Which source operand ?
4638 ShVal = SVOp->getOperand(OpSrc);
4642 /// isVectorShiftLeft - Returns true if the shuffle can be implemented as a
4643 /// logical left shift of a vector.
4644 static bool isVectorShiftLeft(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
4645 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
4646 unsigned NumElems = SVOp->getValueType(0).getVectorNumElements();
4647 unsigned NumZeros = getNumOfConsecutiveZeros(SVOp, NumElems,
4648 true /* check zeros from left */, DAG);
4654 // Considering the elements in the mask that are not consecutive zeros,
4655 // check if they consecutively come from only one of the source vectors.
4657 // 0 { A, B, X, X } = V2
4659 // vector_shuffle V1, V2 <X, X, 4, 5>
4661 if (!isShuffleMaskConsecutive(SVOp,
4662 NumZeros, // Mask Start Index
4663 NumElems, // Mask End Index(exclusive)
4664 0, // Where to start looking in the src vector
4665 NumElems, // Number of elements in vector
4666 OpSrc)) // Which source operand ?
4671 ShVal = SVOp->getOperand(OpSrc);
4675 /// isVectorShift - Returns true if the shuffle can be implemented as a
4676 /// logical left or right shift of a vector.
4677 static bool isVectorShift(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
4678 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
4679 // Although the logic below support any bitwidth size, there are no
4680 // shift instructions which handle more than 128-bit vectors.
4681 if (SVOp->getValueType(0).getSizeInBits() > 128)
4684 if (isVectorShiftLeft(SVOp, DAG, isLeft, ShVal, ShAmt) ||
4685 isVectorShiftRight(SVOp, DAG, isLeft, ShVal, ShAmt))
4691 /// LowerBuildVectorv16i8 - Custom lower build_vector of v16i8.
4693 static SDValue LowerBuildVectorv16i8(SDValue Op, unsigned NonZeros,
4694 unsigned NumNonZero, unsigned NumZero,
4696 const X86Subtarget* Subtarget,
4697 const TargetLowering &TLI) {
4701 DebugLoc dl = Op.getDebugLoc();
4704 for (unsigned i = 0; i < 16; ++i) {
4705 bool ThisIsNonZero = (NonZeros & (1 << i)) != 0;
4706 if (ThisIsNonZero && First) {
4708 V = getZeroVector(MVT::v8i16, Subtarget, DAG, dl);
4710 V = DAG.getUNDEF(MVT::v8i16);
4715 SDValue ThisElt(0, 0), LastElt(0, 0);
4716 bool LastIsNonZero = (NonZeros & (1 << (i-1))) != 0;
4717 if (LastIsNonZero) {
4718 LastElt = DAG.getNode(ISD::ZERO_EXTEND, dl,
4719 MVT::i16, Op.getOperand(i-1));
4721 if (ThisIsNonZero) {
4722 ThisElt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, Op.getOperand(i));
4723 ThisElt = DAG.getNode(ISD::SHL, dl, MVT::i16,
4724 ThisElt, DAG.getConstant(8, MVT::i8));
4726 ThisElt = DAG.getNode(ISD::OR, dl, MVT::i16, ThisElt, LastElt);
4730 if (ThisElt.getNode())
4731 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, V, ThisElt,
4732 DAG.getIntPtrConstant(i/2));
4736 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V);
4739 /// LowerBuildVectorv8i16 - Custom lower build_vector of v8i16.
4741 static SDValue LowerBuildVectorv8i16(SDValue Op, unsigned NonZeros,
4742 unsigned NumNonZero, unsigned NumZero,
4744 const X86Subtarget* Subtarget,
4745 const TargetLowering &TLI) {
4749 DebugLoc dl = Op.getDebugLoc();
4752 for (unsigned i = 0; i < 8; ++i) {
4753 bool isNonZero = (NonZeros & (1 << i)) != 0;
4757 V = getZeroVector(MVT::v8i16, Subtarget, DAG, dl);
4759 V = DAG.getUNDEF(MVT::v8i16);
4762 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl,
4763 MVT::v8i16, V, Op.getOperand(i),
4764 DAG.getIntPtrConstant(i));
4771 /// getVShift - Return a vector logical shift node.
4773 static SDValue getVShift(bool isLeft, EVT VT, SDValue SrcOp,
4774 unsigned NumBits, SelectionDAG &DAG,
4775 const TargetLowering &TLI, DebugLoc dl) {
4776 assert(VT.getSizeInBits() == 128 && "Unknown type for VShift");
4777 EVT ShVT = MVT::v2i64;
4778 unsigned Opc = isLeft ? X86ISD::VSHLDQ : X86ISD::VSRLDQ;
4779 SrcOp = DAG.getNode(ISD::BITCAST, dl, ShVT, SrcOp);
4780 return DAG.getNode(ISD::BITCAST, dl, VT,
4781 DAG.getNode(Opc, dl, ShVT, SrcOp,
4782 DAG.getConstant(NumBits,
4783 TLI.getShiftAmountTy(SrcOp.getValueType()))));
4787 X86TargetLowering::LowerAsSplatVectorLoad(SDValue SrcOp, EVT VT, DebugLoc dl,
4788 SelectionDAG &DAG) const {
4790 // Check if the scalar load can be widened into a vector load. And if
4791 // the address is "base + cst" see if the cst can be "absorbed" into
4792 // the shuffle mask.
4793 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(SrcOp)) {
4794 SDValue Ptr = LD->getBasePtr();
4795 if (!ISD::isNormalLoad(LD) || LD->isVolatile())
4797 EVT PVT = LD->getValueType(0);
4798 if (PVT != MVT::i32 && PVT != MVT::f32)
4803 if (FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr)) {
4804 FI = FINode->getIndex();
4806 } else if (DAG.isBaseWithConstantOffset(Ptr) &&
4807 isa<FrameIndexSDNode>(Ptr.getOperand(0))) {
4808 FI = cast<FrameIndexSDNode>(Ptr.getOperand(0))->getIndex();
4809 Offset = Ptr.getConstantOperandVal(1);
4810 Ptr = Ptr.getOperand(0);
4815 // FIXME: 256-bit vector instructions don't require a strict alignment,
4816 // improve this code to support it better.
4817 unsigned RequiredAlign = VT.getSizeInBits()/8;
4818 SDValue Chain = LD->getChain();
4819 // Make sure the stack object alignment is at least 16 or 32.
4820 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
4821 if (DAG.InferPtrAlignment(Ptr) < RequiredAlign) {
4822 if (MFI->isFixedObjectIndex(FI)) {
4823 // Can't change the alignment. FIXME: It's possible to compute
4824 // the exact stack offset and reference FI + adjust offset instead.
4825 // If someone *really* cares about this. That's the way to implement it.
4828 MFI->setObjectAlignment(FI, RequiredAlign);
4832 // (Offset % 16 or 32) must be multiple of 4. Then address is then
4833 // Ptr + (Offset & ~15).
4836 if ((Offset % RequiredAlign) & 3)
4838 int64_t StartOffset = Offset & ~(RequiredAlign-1);
4840 Ptr = DAG.getNode(ISD::ADD, Ptr.getDebugLoc(), Ptr.getValueType(),
4841 Ptr,DAG.getConstant(StartOffset, Ptr.getValueType()));
4843 int EltNo = (Offset - StartOffset) >> 2;
4844 unsigned NumElems = VT.getVectorNumElements();
4846 EVT NVT = EVT::getVectorVT(*DAG.getContext(), PVT, NumElems);
4847 SDValue V1 = DAG.getLoad(NVT, dl, Chain, Ptr,
4848 LD->getPointerInfo().getWithOffset(StartOffset),
4849 false, false, false, 0);
4851 SmallVector<int, 8> Mask;
4852 for (unsigned i = 0; i != NumElems; ++i)
4853 Mask.push_back(EltNo);
4855 return DAG.getVectorShuffle(NVT, dl, V1, DAG.getUNDEF(NVT), &Mask[0]);
4861 /// EltsFromConsecutiveLoads - Given the initializing elements 'Elts' of a
4862 /// vector of type 'VT', see if the elements can be replaced by a single large
4863 /// load which has the same value as a build_vector whose operands are 'elts'.
4865 /// Example: <load i32 *a, load i32 *a+4, undef, undef> -> zextload a
4867 /// FIXME: we'd also like to handle the case where the last elements are zero
4868 /// rather than undef via VZEXT_LOAD, but we do not detect that case today.
4869 /// There's even a handy isZeroNode for that purpose.
4870 static SDValue EltsFromConsecutiveLoads(EVT VT, SmallVectorImpl<SDValue> &Elts,
4871 DebugLoc &DL, SelectionDAG &DAG) {
4872 EVT EltVT = VT.getVectorElementType();
4873 unsigned NumElems = Elts.size();
4875 LoadSDNode *LDBase = NULL;
4876 unsigned LastLoadedElt = -1U;
4878 // For each element in the initializer, see if we've found a load or an undef.
4879 // If we don't find an initial load element, or later load elements are
4880 // non-consecutive, bail out.
4881 for (unsigned i = 0; i < NumElems; ++i) {
4882 SDValue Elt = Elts[i];
4884 if (!Elt.getNode() ||
4885 (Elt.getOpcode() != ISD::UNDEF && !ISD::isNON_EXTLoad(Elt.getNode())))
4888 if (Elt.getNode()->getOpcode() == ISD::UNDEF)
4890 LDBase = cast<LoadSDNode>(Elt.getNode());
4894 if (Elt.getOpcode() == ISD::UNDEF)
4897 LoadSDNode *LD = cast<LoadSDNode>(Elt);
4898 if (!DAG.isConsecutiveLoad(LD, LDBase, EltVT.getSizeInBits()/8, i))
4903 // If we have found an entire vector of loads and undefs, then return a large
4904 // load of the entire vector width starting at the base pointer. If we found
4905 // consecutive loads for the low half, generate a vzext_load node.
4906 if (LastLoadedElt == NumElems - 1) {
4907 if (DAG.InferPtrAlignment(LDBase->getBasePtr()) >= 16)
4908 return DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(),
4909 LDBase->getPointerInfo(),
4910 LDBase->isVolatile(), LDBase->isNonTemporal(),
4911 LDBase->isInvariant(), 0);
4912 return DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(),
4913 LDBase->getPointerInfo(),
4914 LDBase->isVolatile(), LDBase->isNonTemporal(),
4915 LDBase->isInvariant(), LDBase->getAlignment());
4917 if (NumElems == 4 && LastLoadedElt == 1 &&
4918 DAG.getTargetLoweringInfo().isTypeLegal(MVT::v2i64)) {
4919 SDVTList Tys = DAG.getVTList(MVT::v2i64, MVT::Other);
4920 SDValue Ops[] = { LDBase->getChain(), LDBase->getBasePtr() };
4922 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, DL, Tys, Ops, 2, MVT::i64,
4923 LDBase->getPointerInfo(),
4924 LDBase->getAlignment(),
4925 false/*isVolatile*/, true/*ReadMem*/,
4927 return DAG.getNode(ISD::BITCAST, DL, VT, ResNode);
4932 /// LowerVectorBroadcast - Attempt to use the vbroadcast instruction
4933 /// to generate a splat value for the following cases:
4934 /// 1. A splat BUILD_VECTOR which uses a single scalar load, or a constant.
4935 /// 2. A splat shuffle which uses a scalar_to_vector node which comes from
4936 /// a scalar load, or a constant.
4937 /// The VBROADCAST node is returned when a pattern is found,
4938 /// or SDValue() otherwise.
4940 X86TargetLowering::LowerVectorBroadcast(SDValue &Op, SelectionDAG &DAG) const {
4941 if (!Subtarget->hasAVX())
4944 EVT VT = Op.getValueType();
4945 DebugLoc dl = Op.getDebugLoc();
4947 assert((VT.is128BitVector() || VT.is256BitVector()) &&
4948 "Unsupported vector type for broadcast.");
4953 switch (Op.getOpcode()) {
4955 // Unknown pattern found.
4958 case ISD::BUILD_VECTOR: {
4959 // The BUILD_VECTOR node must be a splat.
4960 if (!isSplatVector(Op.getNode()))
4963 Ld = Op.getOperand(0);
4964 ConstSplatVal = (Ld.getOpcode() == ISD::Constant ||
4965 Ld.getOpcode() == ISD::ConstantFP);
4967 // The suspected load node has several users. Make sure that all
4968 // of its users are from the BUILD_VECTOR node.
4969 // Constants may have multiple users.
4970 if (!ConstSplatVal && !Ld->hasNUsesOfValue(VT.getVectorNumElements(), 0))
4975 case ISD::VECTOR_SHUFFLE: {
4976 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
4978 // Shuffles must have a splat mask where the first element is
4980 if ((!SVOp->isSplat()) || SVOp->getMaskElt(0) != 0)
4983 SDValue Sc = Op.getOperand(0);
4984 if (Sc.getOpcode() != ISD::SCALAR_TO_VECTOR &&
4985 Sc.getOpcode() != ISD::BUILD_VECTOR)
4988 Ld = Sc.getOperand(0);
4989 ConstSplatVal = (Ld.getOpcode() == ISD::Constant ||
4990 Ld.getOpcode() == ISD::ConstantFP);
4992 // The scalar_to_vector node and the suspected
4993 // load node must have exactly one user.
4994 // Constants may have multiple users.
4995 if (!ConstSplatVal && (!Sc.hasOneUse() || !Ld.hasOneUse()))
5001 bool Is256 = VT.getSizeInBits() == 256;
5003 // Handle the broadcasting a single constant scalar from the constant pool
5004 // into a vector. On Sandybridge it is still better to load a constant vector
5005 // from the constant pool and not to broadcast it from a scalar.
5006 if (ConstSplatVal && Subtarget->hasAVX2()) {
5007 EVT CVT = Ld.getValueType();
5008 assert(!CVT.isVector() && "Must not broadcast a vector type");
5009 unsigned ScalarSize = CVT.getSizeInBits();
5011 if (ScalarSize == 32 || (Is256 && ScalarSize == 64)) {
5012 const Constant *C = 0;
5013 if (ConstantSDNode *CI = dyn_cast<ConstantSDNode>(Ld))
5014 C = CI->getConstantIntValue();
5015 else if (ConstantFPSDNode *CF = dyn_cast<ConstantFPSDNode>(Ld))
5016 C = CF->getConstantFPValue();
5018 assert(C && "Invalid constant type");
5020 SDValue CP = DAG.getConstantPool(C, getPointerTy());
5021 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
5022 Ld = DAG.getLoad(CVT, dl, DAG.getEntryNode(), CP,
5023 MachinePointerInfo::getConstantPool(),
5024 false, false, false, Alignment);
5026 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5030 bool IsLoad = ISD::isNormalLoad(Ld.getNode());
5031 unsigned ScalarSize = Ld.getValueType().getSizeInBits();
5033 // Handle AVX2 in-register broadcasts.
5034 if (!IsLoad && Subtarget->hasAVX2() &&
5035 (ScalarSize == 32 || (Is256 && ScalarSize == 64)))
5036 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5038 // The scalar source must be a normal load.
5042 if (ScalarSize == 32 || (Is256 && ScalarSize == 64))
5043 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5045 // The integer check is needed for the 64-bit into 128-bit so it doesn't match
5046 // double since there is no vbroadcastsd xmm
5047 if (Subtarget->hasAVX2() && Ld.getValueType().isInteger()) {
5048 if (ScalarSize == 8 || ScalarSize == 16 || ScalarSize == 64)
5049 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5052 // Unsupported broadcast.
5057 X86TargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const {
5058 DebugLoc dl = Op.getDebugLoc();
5060 EVT VT = Op.getValueType();
5061 EVT ExtVT = VT.getVectorElementType();
5062 unsigned NumElems = Op.getNumOperands();
5064 // Vectors containing all zeros can be matched by pxor and xorps later
5065 if (ISD::isBuildVectorAllZeros(Op.getNode())) {
5066 // Canonicalize this to <4 x i32> to 1) ensure the zero vectors are CSE'd
5067 // and 2) ensure that i64 scalars are eliminated on x86-32 hosts.
5068 if (VT == MVT::v4i32 || VT == MVT::v8i32)
5071 return getZeroVector(VT, Subtarget, DAG, dl);
5074 // Vectors containing all ones can be matched by pcmpeqd on 128-bit width
5075 // vectors or broken into v4i32 operations on 256-bit vectors. AVX2 can use
5076 // vpcmpeqd on 256-bit vectors.
5077 if (ISD::isBuildVectorAllOnes(Op.getNode())) {
5078 if (VT == MVT::v4i32 || (VT == MVT::v8i32 && Subtarget->hasAVX2()))
5081 return getOnesVector(VT, Subtarget->hasAVX2(), DAG, dl);
5084 SDValue Broadcast = LowerVectorBroadcast(Op, DAG);
5085 if (Broadcast.getNode())
5088 unsigned EVTBits = ExtVT.getSizeInBits();
5090 unsigned NumZero = 0;
5091 unsigned NumNonZero = 0;
5092 unsigned NonZeros = 0;
5093 bool IsAllConstants = true;
5094 SmallSet<SDValue, 8> Values;
5095 for (unsigned i = 0; i < NumElems; ++i) {
5096 SDValue Elt = Op.getOperand(i);
5097 if (Elt.getOpcode() == ISD::UNDEF)
5100 if (Elt.getOpcode() != ISD::Constant &&
5101 Elt.getOpcode() != ISD::ConstantFP)
5102 IsAllConstants = false;
5103 if (X86::isZeroNode(Elt))
5106 NonZeros |= (1 << i);
5111 // All undef vector. Return an UNDEF. All zero vectors were handled above.
5112 if (NumNonZero == 0)
5113 return DAG.getUNDEF(VT);
5115 // Special case for single non-zero, non-undef, element.
5116 if (NumNonZero == 1) {
5117 unsigned Idx = CountTrailingZeros_32(NonZeros);
5118 SDValue Item = Op.getOperand(Idx);
5120 // If this is an insertion of an i64 value on x86-32, and if the top bits of
5121 // the value are obviously zero, truncate the value to i32 and do the
5122 // insertion that way. Only do this if the value is non-constant or if the
5123 // value is a constant being inserted into element 0. It is cheaper to do
5124 // a constant pool load than it is to do a movd + shuffle.
5125 if (ExtVT == MVT::i64 && !Subtarget->is64Bit() &&
5126 (!IsAllConstants || Idx == 0)) {
5127 if (DAG.MaskedValueIsZero(Item, APInt::getBitsSet(64, 32, 64))) {
5129 assert(VT == MVT::v2i64 && "Expected an SSE value type!");
5130 EVT VecVT = MVT::v4i32;
5131 unsigned VecElts = 4;
5133 // Truncate the value (which may itself be a constant) to i32, and
5134 // convert it to a vector with movd (S2V+shuffle to zero extend).
5135 Item = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Item);
5136 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Item);
5137 Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
5139 // Now we have our 32-bit value zero extended in the low element of
5140 // a vector. If Idx != 0, swizzle it into place.
5142 SmallVector<int, 4> Mask;
5143 Mask.push_back(Idx);
5144 for (unsigned i = 1; i != VecElts; ++i)
5146 Item = DAG.getVectorShuffle(VecVT, dl, Item, DAG.getUNDEF(VecVT),
5149 return DAG.getNode(ISD::BITCAST, dl, VT, Item);
5153 // If we have a constant or non-constant insertion into the low element of
5154 // a vector, we can do this with SCALAR_TO_VECTOR + shuffle of zero into
5155 // the rest of the elements. This will be matched as movd/movq/movss/movsd
5156 // depending on what the source datatype is.
5159 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
5161 if (ExtVT == MVT::i32 || ExtVT == MVT::f32 || ExtVT == MVT::f64 ||
5162 (ExtVT == MVT::i64 && Subtarget->is64Bit())) {
5163 if (VT.getSizeInBits() == 256) {
5164 SDValue ZeroVec = getZeroVector(VT, Subtarget, DAG, dl);
5165 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, ZeroVec,
5166 Item, DAG.getIntPtrConstant(0));
5168 assert(VT.getSizeInBits() == 128 && "Expected an SSE value type!");
5169 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
5170 // Turn it into a MOVL (i.e. movss, movsd, or movd) to a zero vector.
5171 return getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
5174 if (ExtVT == MVT::i16 || ExtVT == MVT::i8) {
5175 Item = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Item);
5176 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, Item);
5177 if (VT.getSizeInBits() == 256) {
5178 SDValue ZeroVec = getZeroVector(MVT::v8i32, Subtarget, DAG, dl);
5179 Item = Insert128BitVector(ZeroVec, Item, 0, DAG, dl);
5181 assert(VT.getSizeInBits() == 128 && "Expected an SSE value type!");
5182 Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
5184 return DAG.getNode(ISD::BITCAST, dl, VT, Item);
5188 // Is it a vector logical left shift?
5189 if (NumElems == 2 && Idx == 1 &&
5190 X86::isZeroNode(Op.getOperand(0)) &&
5191 !X86::isZeroNode(Op.getOperand(1))) {
5192 unsigned NumBits = VT.getSizeInBits();
5193 return getVShift(true, VT,
5194 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
5195 VT, Op.getOperand(1)),
5196 NumBits/2, DAG, *this, dl);
5199 if (IsAllConstants) // Otherwise, it's better to do a constpool load.
5202 // Otherwise, if this is a vector with i32 or f32 elements, and the element
5203 // is a non-constant being inserted into an element other than the low one,
5204 // we can't use a constant pool load. Instead, use SCALAR_TO_VECTOR (aka
5205 // movd/movss) to move this into the low element, then shuffle it into
5207 if (EVTBits == 32) {
5208 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
5210 // Turn it into a shuffle of zero and zero-extended scalar to vector.
5211 Item = getShuffleVectorZeroOrUndef(Item, 0, NumZero > 0, Subtarget, DAG);
5212 SmallVector<int, 8> MaskVec;
5213 for (unsigned i = 0; i != NumElems; ++i)
5214 MaskVec.push_back(i == Idx ? 0 : 1);
5215 return DAG.getVectorShuffle(VT, dl, Item, DAG.getUNDEF(VT), &MaskVec[0]);
5219 // Splat is obviously ok. Let legalizer expand it to a shuffle.
5220 if (Values.size() == 1) {
5221 if (EVTBits == 32) {
5222 // Instead of a shuffle like this:
5223 // shuffle (scalar_to_vector (load (ptr + 4))), undef, <0, 0, 0, 0>
5224 // Check if it's possible to issue this instead.
5225 // shuffle (vload ptr)), undef, <1, 1, 1, 1>
5226 unsigned Idx = CountTrailingZeros_32(NonZeros);
5227 SDValue Item = Op.getOperand(Idx);
5228 if (Op.getNode()->isOnlyUserOf(Item.getNode()))
5229 return LowerAsSplatVectorLoad(Item, VT, dl, DAG);
5234 // A vector full of immediates; various special cases are already
5235 // handled, so this is best done with a single constant-pool load.
5239 // For AVX-length vectors, build the individual 128-bit pieces and use
5240 // shuffles to put them in place.
5241 if (VT.getSizeInBits() == 256) {
5242 SmallVector<SDValue, 32> V;
5243 for (unsigned i = 0; i != NumElems; ++i)
5244 V.push_back(Op.getOperand(i));
5246 EVT HVT = EVT::getVectorVT(*DAG.getContext(), ExtVT, NumElems/2);
5248 // Build both the lower and upper subvector.
5249 SDValue Lower = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT, &V[0], NumElems/2);
5250 SDValue Upper = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT, &V[NumElems / 2],
5253 // Recreate the wider vector with the lower and upper part.
5254 return Concat128BitVectors(Lower, Upper, VT, NumElems, DAG, dl);
5257 // Let legalizer expand 2-wide build_vectors.
5258 if (EVTBits == 64) {
5259 if (NumNonZero == 1) {
5260 // One half is zero or undef.
5261 unsigned Idx = CountTrailingZeros_32(NonZeros);
5262 SDValue V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT,
5263 Op.getOperand(Idx));
5264 return getShuffleVectorZeroOrUndef(V2, Idx, true, Subtarget, DAG);
5269 // If element VT is < 32 bits, convert it to inserts into a zero vector.
5270 if (EVTBits == 8 && NumElems == 16) {
5271 SDValue V = LowerBuildVectorv16i8(Op, NonZeros,NumNonZero,NumZero, DAG,
5273 if (V.getNode()) return V;
5276 if (EVTBits == 16 && NumElems == 8) {
5277 SDValue V = LowerBuildVectorv8i16(Op, NonZeros,NumNonZero,NumZero, DAG,
5279 if (V.getNode()) return V;
5282 // If element VT is == 32 bits, turn it into a number of shuffles.
5283 SmallVector<SDValue, 8> V(NumElems);
5284 if (NumElems == 4 && NumZero > 0) {
5285 for (unsigned i = 0; i < 4; ++i) {
5286 bool isZero = !(NonZeros & (1 << i));
5288 V[i] = getZeroVector(VT, Subtarget, DAG, dl);
5290 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
5293 for (unsigned i = 0; i < 2; ++i) {
5294 switch ((NonZeros & (0x3 << i*2)) >> (i*2)) {
5297 V[i] = V[i*2]; // Must be a zero vector.
5300 V[i] = getMOVL(DAG, dl, VT, V[i*2+1], V[i*2]);
5303 V[i] = getMOVL(DAG, dl, VT, V[i*2], V[i*2+1]);
5306 V[i] = getUnpackl(DAG, dl, VT, V[i*2], V[i*2+1]);
5311 bool Reverse1 = (NonZeros & 0x3) == 2;
5312 bool Reverse2 = ((NonZeros & (0x3 << 2)) >> 2) == 2;
5316 static_cast<int>(Reverse2 ? NumElems+1 : NumElems),
5317 static_cast<int>(Reverse2 ? NumElems : NumElems+1)
5319 return DAG.getVectorShuffle(VT, dl, V[0], V[1], &MaskVec[0]);
5322 if (Values.size() > 1 && VT.getSizeInBits() == 128) {
5323 // Check for a build vector of consecutive loads.
5324 for (unsigned i = 0; i < NumElems; ++i)
5325 V[i] = Op.getOperand(i);
5327 // Check for elements which are consecutive loads.
5328 SDValue LD = EltsFromConsecutiveLoads(VT, V, dl, DAG);
5332 // For SSE 4.1, use insertps to put the high elements into the low element.
5333 if (getSubtarget()->hasSSE41()) {
5335 if (Op.getOperand(0).getOpcode() != ISD::UNDEF)
5336 Result = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(0));
5338 Result = DAG.getUNDEF(VT);
5340 for (unsigned i = 1; i < NumElems; ++i) {
5341 if (Op.getOperand(i).getOpcode() == ISD::UNDEF) continue;
5342 Result = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Result,
5343 Op.getOperand(i), DAG.getIntPtrConstant(i));
5348 // Otherwise, expand into a number of unpckl*, start by extending each of
5349 // our (non-undef) elements to the full vector width with the element in the
5350 // bottom slot of the vector (which generates no code for SSE).
5351 for (unsigned i = 0; i < NumElems; ++i) {
5352 if (Op.getOperand(i).getOpcode() != ISD::UNDEF)
5353 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
5355 V[i] = DAG.getUNDEF(VT);
5358 // Next, we iteratively mix elements, e.g. for v4f32:
5359 // Step 1: unpcklps 0, 2 ==> X: <?, ?, 2, 0>
5360 // : unpcklps 1, 3 ==> Y: <?, ?, 3, 1>
5361 // Step 2: unpcklps X, Y ==> <3, 2, 1, 0>
5362 unsigned EltStride = NumElems >> 1;
5363 while (EltStride != 0) {
5364 for (unsigned i = 0; i < EltStride; ++i) {
5365 // If V[i+EltStride] is undef and this is the first round of mixing,
5366 // then it is safe to just drop this shuffle: V[i] is already in the
5367 // right place, the one element (since it's the first round) being
5368 // inserted as undef can be dropped. This isn't safe for successive
5369 // rounds because they will permute elements within both vectors.
5370 if (V[i+EltStride].getOpcode() == ISD::UNDEF &&
5371 EltStride == NumElems/2)
5374 V[i] = getUnpackl(DAG, dl, VT, V[i], V[i + EltStride]);
5383 // LowerMMXCONCAT_VECTORS - We support concatenate two MMX registers and place
5384 // them in a MMX register. This is better than doing a stack convert.
5385 static SDValue LowerMMXCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
5386 DebugLoc dl = Op.getDebugLoc();
5387 EVT ResVT = Op.getValueType();
5389 assert(ResVT == MVT::v2i64 || ResVT == MVT::v4i32 ||
5390 ResVT == MVT::v8i16 || ResVT == MVT::v16i8);
5392 SDValue InVec = DAG.getNode(ISD::BITCAST,dl, MVT::v1i64, Op.getOperand(0));
5393 SDValue VecOp = DAG.getNode(X86ISD::MOVQ2DQ, dl, MVT::v2i64, InVec);
5394 InVec = Op.getOperand(1);
5395 if (InVec.getOpcode() == ISD::SCALAR_TO_VECTOR) {
5396 unsigned NumElts = ResVT.getVectorNumElements();
5397 VecOp = DAG.getNode(ISD::BITCAST, dl, ResVT, VecOp);
5398 VecOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, ResVT, VecOp,
5399 InVec.getOperand(0), DAG.getIntPtrConstant(NumElts/2+1));
5401 InVec = DAG.getNode(ISD::BITCAST, dl, MVT::v1i64, InVec);
5402 SDValue VecOp2 = DAG.getNode(X86ISD::MOVQ2DQ, dl, MVT::v2i64, InVec);
5403 Mask[0] = 0; Mask[1] = 2;
5404 VecOp = DAG.getVectorShuffle(MVT::v2i64, dl, VecOp, VecOp2, Mask);
5406 return DAG.getNode(ISD::BITCAST, dl, ResVT, VecOp);
5409 // LowerAVXCONCAT_VECTORS - 256-bit AVX can use the vinsertf128 instruction
5410 // to create 256-bit vectors from two other 128-bit ones.
5411 static SDValue LowerAVXCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
5412 DebugLoc dl = Op.getDebugLoc();
5413 EVT ResVT = Op.getValueType();
5415 assert(ResVT.getSizeInBits() == 256 && "Value type must be 256-bit wide");
5417 SDValue V1 = Op.getOperand(0);
5418 SDValue V2 = Op.getOperand(1);
5419 unsigned NumElems = ResVT.getVectorNumElements();
5421 return Concat128BitVectors(V1, V2, ResVT, NumElems, DAG, dl);
5425 X86TargetLowering::LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) const {
5426 EVT ResVT = Op.getValueType();
5428 assert(Op.getNumOperands() == 2);
5429 assert((ResVT.getSizeInBits() == 128 || ResVT.getSizeInBits() == 256) &&
5430 "Unsupported CONCAT_VECTORS for value type");
5432 // We support concatenate two MMX registers and place them in a MMX register.
5433 // This is better than doing a stack convert.
5434 if (ResVT.is128BitVector())
5435 return LowerMMXCONCAT_VECTORS(Op, DAG);
5437 // 256-bit AVX can use the vinsertf128 instruction to create 256-bit vectors
5438 // from two other 128-bit ones.
5439 return LowerAVXCONCAT_VECTORS(Op, DAG);
5442 // Try to lower a shuffle node into a simple blend instruction.
5443 static SDValue LowerVECTOR_SHUFFLEtoBlend(ShuffleVectorSDNode *SVOp,
5444 const X86Subtarget *Subtarget,
5445 SelectionDAG &DAG) {
5446 SDValue V1 = SVOp->getOperand(0);
5447 SDValue V2 = SVOp->getOperand(1);
5448 DebugLoc dl = SVOp->getDebugLoc();
5449 MVT VT = SVOp->getValueType(0).getSimpleVT();
5450 unsigned NumElems = VT.getVectorNumElements();
5452 if (!Subtarget->hasSSE41())
5458 switch (VT.SimpleTy) {
5459 default: return SDValue();
5461 ISDNo = X86ISD::BLENDPW;
5466 ISDNo = X86ISD::BLENDPS;
5471 ISDNo = X86ISD::BLENDPD;
5476 if (!Subtarget->hasAVX())
5478 ISDNo = X86ISD::BLENDPS;
5483 if (!Subtarget->hasAVX())
5485 ISDNo = X86ISD::BLENDPD;
5489 assert(ISDNo && "Invalid Op Number");
5491 unsigned MaskVals = 0;
5493 for (unsigned i = 0; i != NumElems; ++i) {
5494 int EltIdx = SVOp->getMaskElt(i);
5495 if (EltIdx == (int)i || EltIdx < 0)
5497 else if (EltIdx == (int)(i + NumElems))
5498 continue; // Bit is set to zero;
5503 V1 = DAG.getNode(ISD::BITCAST, dl, OpTy, V1);
5504 V2 = DAG.getNode(ISD::BITCAST, dl, OpTy, V2);
5505 SDValue Ret = DAG.getNode(ISDNo, dl, OpTy, V1, V2,
5506 DAG.getConstant(MaskVals, MVT::i32));
5507 return DAG.getNode(ISD::BITCAST, dl, VT, Ret);
5510 // v8i16 shuffles - Prefer shuffles in the following order:
5511 // 1. [all] pshuflw, pshufhw, optional move
5512 // 2. [ssse3] 1 x pshufb
5513 // 3. [ssse3] 2 x pshufb + 1 x por
5514 // 4. [all] mov + pshuflw + pshufhw + N x (pextrw + pinsrw)
5516 X86TargetLowering::LowerVECTOR_SHUFFLEv8i16(SDValue Op,
5517 SelectionDAG &DAG) const {
5518 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
5519 SDValue V1 = SVOp->getOperand(0);
5520 SDValue V2 = SVOp->getOperand(1);
5521 DebugLoc dl = SVOp->getDebugLoc();
5522 SmallVector<int, 8> MaskVals;
5524 // Determine if more than 1 of the words in each of the low and high quadwords
5525 // of the result come from the same quadword of one of the two inputs. Undef
5526 // mask values count as coming from any quadword, for better codegen.
5527 unsigned LoQuad[] = { 0, 0, 0, 0 };
5528 unsigned HiQuad[] = { 0, 0, 0, 0 };
5529 std::bitset<4> InputQuads;
5530 for (unsigned i = 0; i < 8; ++i) {
5531 unsigned *Quad = i < 4 ? LoQuad : HiQuad;
5532 int EltIdx = SVOp->getMaskElt(i);
5533 MaskVals.push_back(EltIdx);
5542 InputQuads.set(EltIdx / 4);
5545 int BestLoQuad = -1;
5546 unsigned MaxQuad = 1;
5547 for (unsigned i = 0; i < 4; ++i) {
5548 if (LoQuad[i] > MaxQuad) {
5550 MaxQuad = LoQuad[i];
5554 int BestHiQuad = -1;
5556 for (unsigned i = 0; i < 4; ++i) {
5557 if (HiQuad[i] > MaxQuad) {
5559 MaxQuad = HiQuad[i];
5563 // For SSSE3, If all 8 words of the result come from only 1 quadword of each
5564 // of the two input vectors, shuffle them into one input vector so only a
5565 // single pshufb instruction is necessary. If There are more than 2 input
5566 // quads, disable the next transformation since it does not help SSSE3.
5567 bool V1Used = InputQuads[0] || InputQuads[1];
5568 bool V2Used = InputQuads[2] || InputQuads[3];
5569 if (Subtarget->hasSSSE3()) {
5570 if (InputQuads.count() == 2 && V1Used && V2Used) {
5571 BestLoQuad = InputQuads[0] ? 0 : 1;
5572 BestHiQuad = InputQuads[2] ? 2 : 3;
5574 if (InputQuads.count() > 2) {
5580 // If BestLoQuad or BestHiQuad are set, shuffle the quads together and update
5581 // the shuffle mask. If a quad is scored as -1, that means that it contains
5582 // words from all 4 input quadwords.
5584 if (BestLoQuad >= 0 || BestHiQuad >= 0) {
5586 BestLoQuad < 0 ? 0 : BestLoQuad,
5587 BestHiQuad < 0 ? 1 : BestHiQuad
5589 NewV = DAG.getVectorShuffle(MVT::v2i64, dl,
5590 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, V1),
5591 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, V2), &MaskV[0]);
5592 NewV = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, NewV);
5594 // Rewrite the MaskVals and assign NewV to V1 if NewV now contains all the
5595 // source words for the shuffle, to aid later transformations.
5596 bool AllWordsInNewV = true;
5597 bool InOrder[2] = { true, true };
5598 for (unsigned i = 0; i != 8; ++i) {
5599 int idx = MaskVals[i];
5601 InOrder[i/4] = false;
5602 if (idx < 0 || (idx/4) == BestLoQuad || (idx/4) == BestHiQuad)
5604 AllWordsInNewV = false;
5608 bool pshuflw = AllWordsInNewV, pshufhw = AllWordsInNewV;
5609 if (AllWordsInNewV) {
5610 for (int i = 0; i != 8; ++i) {
5611 int idx = MaskVals[i];
5614 idx = MaskVals[i] = (idx / 4) == BestLoQuad ? (idx & 3) : (idx & 3) + 4;
5615 if ((idx != i) && idx < 4)
5617 if ((idx != i) && idx > 3)
5626 // If we've eliminated the use of V2, and the new mask is a pshuflw or
5627 // pshufhw, that's as cheap as it gets. Return the new shuffle.
5628 if ((pshufhw && InOrder[0]) || (pshuflw && InOrder[1])) {
5629 unsigned Opc = pshufhw ? X86ISD::PSHUFHW : X86ISD::PSHUFLW;
5630 unsigned TargetMask = 0;
5631 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV,
5632 DAG.getUNDEF(MVT::v8i16), &MaskVals[0]);
5633 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode());
5634 TargetMask = pshufhw ? getShufflePSHUFHWImmediate(SVOp):
5635 getShufflePSHUFLWImmediate(SVOp);
5636 V1 = NewV.getOperand(0);
5637 return getTargetShuffleNode(Opc, dl, MVT::v8i16, V1, TargetMask, DAG);
5641 // If we have SSSE3, and all words of the result are from 1 input vector,
5642 // case 2 is generated, otherwise case 3 is generated. If no SSSE3
5643 // is present, fall back to case 4.
5644 if (Subtarget->hasSSSE3()) {
5645 SmallVector<SDValue,16> pshufbMask;
5647 // If we have elements from both input vectors, set the high bit of the
5648 // shuffle mask element to zero out elements that come from V2 in the V1
5649 // mask, and elements that come from V1 in the V2 mask, so that the two
5650 // results can be OR'd together.
5651 bool TwoInputs = V1Used && V2Used;
5652 for (unsigned i = 0; i != 8; ++i) {
5653 int EltIdx = MaskVals[i] * 2;
5654 int Idx0 = (TwoInputs && (EltIdx >= 16)) ? 0x80 : EltIdx;
5655 int Idx1 = (TwoInputs && (EltIdx >= 16)) ? 0x80 : EltIdx+1;
5656 pshufbMask.push_back(DAG.getConstant(Idx0, MVT::i8));
5657 pshufbMask.push_back(DAG.getConstant(Idx1, MVT::i8));
5659 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V1);
5660 V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1,
5661 DAG.getNode(ISD::BUILD_VECTOR, dl,
5662 MVT::v16i8, &pshufbMask[0], 16));
5664 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
5666 // Calculate the shuffle mask for the second input, shuffle it, and
5667 // OR it with the first shuffled input.
5669 for (unsigned i = 0; i != 8; ++i) {
5670 int EltIdx = MaskVals[i] * 2;
5671 int Idx0 = (EltIdx < 16) ? 0x80 : EltIdx - 16;
5672 int Idx1 = (EltIdx < 16) ? 0x80 : EltIdx - 15;
5673 pshufbMask.push_back(DAG.getConstant(Idx0, MVT::i8));
5674 pshufbMask.push_back(DAG.getConstant(Idx1, MVT::i8));
5676 V2 = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V2);
5677 V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2,
5678 DAG.getNode(ISD::BUILD_VECTOR, dl,
5679 MVT::v16i8, &pshufbMask[0], 16));
5680 V1 = DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
5681 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
5684 // If BestLoQuad >= 0, generate a pshuflw to put the low elements in order,
5685 // and update MaskVals with new element order.
5686 std::bitset<8> InOrder;
5687 if (BestLoQuad >= 0) {
5688 int MaskV[] = { -1, -1, -1, -1, 4, 5, 6, 7 };
5689 for (int i = 0; i != 4; ++i) {
5690 int idx = MaskVals[i];
5693 } else if ((idx / 4) == BestLoQuad) {
5698 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16),
5701 if (NewV.getOpcode() == ISD::VECTOR_SHUFFLE && Subtarget->hasSSSE3()) {
5702 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode());
5703 NewV = getTargetShuffleNode(X86ISD::PSHUFLW, dl, MVT::v8i16,
5705 getShufflePSHUFLWImmediate(SVOp), DAG);
5709 // If BestHi >= 0, generate a pshufhw to put the high elements in order,
5710 // and update MaskVals with the new element order.
5711 if (BestHiQuad >= 0) {
5712 int MaskV[] = { 0, 1, 2, 3, -1, -1, -1, -1 };
5713 for (unsigned i = 4; i != 8; ++i) {
5714 int idx = MaskVals[i];
5717 } else if ((idx / 4) == BestHiQuad) {
5718 MaskV[i] = (idx & 3) + 4;
5722 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16),
5725 if (NewV.getOpcode() == ISD::VECTOR_SHUFFLE && Subtarget->hasSSSE3()) {
5726 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode());
5727 NewV = getTargetShuffleNode(X86ISD::PSHUFHW, dl, MVT::v8i16,
5729 getShufflePSHUFHWImmediate(SVOp), DAG);
5733 // In case BestHi & BestLo were both -1, which means each quadword has a word
5734 // from each of the four input quadwords, calculate the InOrder bitvector now
5735 // before falling through to the insert/extract cleanup.
5736 if (BestLoQuad == -1 && BestHiQuad == -1) {
5738 for (int i = 0; i != 8; ++i)
5739 if (MaskVals[i] < 0 || MaskVals[i] == i)
5743 // The other elements are put in the right place using pextrw and pinsrw.
5744 for (unsigned i = 0; i != 8; ++i) {
5747 int EltIdx = MaskVals[i];
5750 SDValue ExtOp = (EltIdx < 8) ?
5751 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V1,
5752 DAG.getIntPtrConstant(EltIdx)) :
5753 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V2,
5754 DAG.getIntPtrConstant(EltIdx - 8));
5755 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, ExtOp,
5756 DAG.getIntPtrConstant(i));
5761 // v16i8 shuffles - Prefer shuffles in the following order:
5762 // 1. [ssse3] 1 x pshufb
5763 // 2. [ssse3] 2 x pshufb + 1 x por
5764 // 3. [all] v8i16 shuffle + N x pextrw + rotate + pinsrw
5766 SDValue LowerVECTOR_SHUFFLEv16i8(ShuffleVectorSDNode *SVOp,
5768 const X86TargetLowering &TLI) {
5769 SDValue V1 = SVOp->getOperand(0);
5770 SDValue V2 = SVOp->getOperand(1);
5771 DebugLoc dl = SVOp->getDebugLoc();
5772 ArrayRef<int> MaskVals = SVOp->getMask();
5774 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
5776 // If we have SSSE3, case 1 is generated when all result bytes come from
5777 // one of the inputs. Otherwise, case 2 is generated. If no SSSE3 is
5778 // present, fall back to case 3.
5780 // If SSSE3, use 1 pshufb instruction per vector with elements in the result.
5781 if (TLI.getSubtarget()->hasSSSE3()) {
5782 SmallVector<SDValue,16> pshufbMask;
5784 // If all result elements are from one input vector, then only translate
5785 // undef mask values to 0x80 (zero out result) in the pshufb mask.
5787 // Otherwise, we have elements from both input vectors, and must zero out
5788 // elements that come from V2 in the first mask, and V1 in the second mask
5789 // so that we can OR them together.
5790 for (unsigned i = 0; i != 16; ++i) {
5791 int EltIdx = MaskVals[i];
5792 if (EltIdx < 0 || EltIdx >= 16)
5794 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
5796 V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1,
5797 DAG.getNode(ISD::BUILD_VECTOR, dl,
5798 MVT::v16i8, &pshufbMask[0], 16));
5802 // Calculate the shuffle mask for the second input, shuffle it, and
5803 // OR it with the first shuffled input.
5805 for (unsigned i = 0; i != 16; ++i) {
5806 int EltIdx = MaskVals[i];
5807 EltIdx = (EltIdx < 16) ? 0x80 : EltIdx - 16;
5808 pshufbMask.push_back(DAG.getConstant(EltIdx - 16, MVT::i8));
5810 V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2,
5811 DAG.getNode(ISD::BUILD_VECTOR, dl,
5812 MVT::v16i8, &pshufbMask[0], 16));
5813 return DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
5816 // No SSSE3 - Calculate in place words and then fix all out of place words
5817 // With 0-16 extracts & inserts. Worst case is 16 bytes out of order from
5818 // the 16 different words that comprise the two doublequadword input vectors.
5819 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
5820 V2 = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V2);
5822 for (int i = 0; i != 8; ++i) {
5823 int Elt0 = MaskVals[i*2];
5824 int Elt1 = MaskVals[i*2+1];
5826 // This word of the result is all undef, skip it.
5827 if (Elt0 < 0 && Elt1 < 0)
5830 // This word of the result is already in the correct place, skip it.
5831 if ((Elt0 == i*2) && (Elt1 == i*2+1))
5834 SDValue Elt0Src = Elt0 < 16 ? V1 : V2;
5835 SDValue Elt1Src = Elt1 < 16 ? V1 : V2;
5838 // If Elt0 and Elt1 are defined, are consecutive, and can be load
5839 // using a single extract together, load it and store it.
5840 if ((Elt0 >= 0) && ((Elt0 + 1) == Elt1) && ((Elt0 & 1) == 0)) {
5841 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src,
5842 DAG.getIntPtrConstant(Elt1 / 2));
5843 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt,
5844 DAG.getIntPtrConstant(i));
5848 // If Elt1 is defined, extract it from the appropriate source. If the
5849 // source byte is not also odd, shift the extracted word left 8 bits
5850 // otherwise clear the bottom 8 bits if we need to do an or.
5852 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src,
5853 DAG.getIntPtrConstant(Elt1 / 2));
5854 if ((Elt1 & 1) == 0)
5855 InsElt = DAG.getNode(ISD::SHL, dl, MVT::i16, InsElt,
5857 TLI.getShiftAmountTy(InsElt.getValueType())));
5859 InsElt = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt,
5860 DAG.getConstant(0xFF00, MVT::i16));
5862 // If Elt0 is defined, extract it from the appropriate source. If the
5863 // source byte is not also even, shift the extracted word right 8 bits. If
5864 // Elt1 was also defined, OR the extracted values together before
5865 // inserting them in the result.
5867 SDValue InsElt0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16,
5868 Elt0Src, DAG.getIntPtrConstant(Elt0 / 2));
5869 if ((Elt0 & 1) != 0)
5870 InsElt0 = DAG.getNode(ISD::SRL, dl, MVT::i16, InsElt0,
5872 TLI.getShiftAmountTy(InsElt0.getValueType())));
5874 InsElt0 = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt0,
5875 DAG.getConstant(0x00FF, MVT::i16));
5876 InsElt = Elt1 >= 0 ? DAG.getNode(ISD::OR, dl, MVT::i16, InsElt, InsElt0)
5879 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt,
5880 DAG.getIntPtrConstant(i));
5882 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, NewV);
5885 /// RewriteAsNarrowerShuffle - Try rewriting v8i16 and v16i8 shuffles as 4 wide
5886 /// ones, or rewriting v4i32 / v4f32 as 2 wide ones if possible. This can be
5887 /// done when every pair / quad of shuffle mask elements point to elements in
5888 /// the right sequence. e.g.
5889 /// vector_shuffle X, Y, <2, 3, | 10, 11, | 0, 1, | 14, 15>
5891 SDValue RewriteAsNarrowerShuffle(ShuffleVectorSDNode *SVOp,
5892 SelectionDAG &DAG, DebugLoc dl) {
5893 MVT VT = SVOp->getValueType(0).getSimpleVT();
5894 unsigned NumElems = VT.getVectorNumElements();
5897 switch (VT.SimpleTy) {
5898 default: llvm_unreachable("Unexpected!");
5899 case MVT::v4f32: NewVT = MVT::v2f64; Scale = 2; break;
5900 case MVT::v4i32: NewVT = MVT::v2i64; Scale = 2; break;
5901 case MVT::v8i16: NewVT = MVT::v4i32; Scale = 2; break;
5902 case MVT::v16i8: NewVT = MVT::v4i32; Scale = 4; break;
5903 case MVT::v16i16: NewVT = MVT::v8i32; Scale = 2; break;
5904 case MVT::v32i8: NewVT = MVT::v8i32; Scale = 4; break;
5907 SmallVector<int, 8> MaskVec;
5908 for (unsigned i = 0; i != NumElems; i += Scale) {
5910 for (unsigned j = 0; j != Scale; ++j) {
5911 int EltIdx = SVOp->getMaskElt(i+j);
5915 StartIdx = (EltIdx / Scale);
5916 if (EltIdx != (int)(StartIdx*Scale + j))
5919 MaskVec.push_back(StartIdx);
5922 SDValue V1 = DAG.getNode(ISD::BITCAST, dl, NewVT, SVOp->getOperand(0));
5923 SDValue V2 = DAG.getNode(ISD::BITCAST, dl, NewVT, SVOp->getOperand(1));
5924 return DAG.getVectorShuffle(NewVT, dl, V1, V2, &MaskVec[0]);
5927 /// getVZextMovL - Return a zero-extending vector move low node.
5929 static SDValue getVZextMovL(EVT VT, EVT OpVT,
5930 SDValue SrcOp, SelectionDAG &DAG,
5931 const X86Subtarget *Subtarget, DebugLoc dl) {
5932 if (VT == MVT::v2f64 || VT == MVT::v4f32) {
5933 LoadSDNode *LD = NULL;
5934 if (!isScalarLoadToVector(SrcOp.getNode(), &LD))
5935 LD = dyn_cast<LoadSDNode>(SrcOp);
5937 // movssrr and movsdrr do not clear top bits. Try to use movd, movq
5939 MVT ExtVT = (OpVT == MVT::v2f64) ? MVT::i64 : MVT::i32;
5940 if ((ExtVT != MVT::i64 || Subtarget->is64Bit()) &&
5941 SrcOp.getOpcode() == ISD::SCALAR_TO_VECTOR &&
5942 SrcOp.getOperand(0).getOpcode() == ISD::BITCAST &&
5943 SrcOp.getOperand(0).getOperand(0).getValueType() == ExtVT) {
5945 OpVT = (OpVT == MVT::v2f64) ? MVT::v2i64 : MVT::v4i32;
5946 return DAG.getNode(ISD::BITCAST, dl, VT,
5947 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT,
5948 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
5956 return DAG.getNode(ISD::BITCAST, dl, VT,
5957 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT,
5958 DAG.getNode(ISD::BITCAST, dl,
5962 /// LowerVECTOR_SHUFFLE_256 - Handle all 256-bit wide vectors shuffles
5963 /// which could not be matched by any known target speficic shuffle
5965 LowerVECTOR_SHUFFLE_256(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
5966 EVT VT = SVOp->getValueType(0);
5968 unsigned NumElems = VT.getVectorNumElements();
5969 unsigned NumLaneElems = NumElems / 2;
5971 DebugLoc dl = SVOp->getDebugLoc();
5972 MVT EltVT = VT.getVectorElementType().getSimpleVT();
5973 EVT NVT = MVT::getVectorVT(EltVT, NumLaneElems);
5976 SmallVector<int, 16> Mask;
5977 for (unsigned l = 0; l < 2; ++l) {
5978 // Build a shuffle mask for the output, discovering on the fly which
5979 // input vectors to use as shuffle operands (recorded in InputUsed).
5980 // If building a suitable shuffle vector proves too hard, then bail
5981 // out with UseBuildVector set.
5982 bool UseBuildVector = false;
5983 int InputUsed[2] = { -1, -1 }; // Not yet discovered.
5984 unsigned LaneStart = l * NumLaneElems;
5985 for (unsigned i = 0; i != NumLaneElems; ++i) {
5986 // The mask element. This indexes into the input.
5987 int Idx = SVOp->getMaskElt(i+LaneStart);
5989 // the mask element does not index into any input vector.
5994 // The input vector this mask element indexes into.
5995 int Input = Idx / NumLaneElems;
5997 // Turn the index into an offset from the start of the input vector.
5998 Idx -= Input * NumLaneElems;
6000 // Find or create a shuffle vector operand to hold this input.
6002 for (OpNo = 0; OpNo < array_lengthof(InputUsed); ++OpNo) {
6003 if (InputUsed[OpNo] == Input)
6004 // This input vector is already an operand.
6006 if (InputUsed[OpNo] < 0) {
6007 // Create a new operand for this input vector.
6008 InputUsed[OpNo] = Input;
6013 if (OpNo >= array_lengthof(InputUsed)) {
6014 // More than two input vectors used! Give up on trying to create a
6015 // shuffle vector. Insert all elements into a BUILD_VECTOR instead.
6016 UseBuildVector = true;
6020 // Add the mask index for the new shuffle vector.
6021 Mask.push_back(Idx + OpNo * NumLaneElems);
6024 if (UseBuildVector) {
6025 SmallVector<SDValue, 16> SVOps;
6026 for (unsigned i = 0; i != NumLaneElems; ++i) {
6027 // The mask element. This indexes into the input.
6028 int Idx = SVOp->getMaskElt(i+LaneStart);
6030 SVOps.push_back(DAG.getUNDEF(EltVT));
6034 // The input vector this mask element indexes into.
6035 int Input = Idx / NumElems;
6037 // Turn the index into an offset from the start of the input vector.
6038 Idx -= Input * NumElems;
6040 // Extract the vector element by hand.
6041 SVOps.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT,
6042 SVOp->getOperand(Input),
6043 DAG.getIntPtrConstant(Idx)));
6046 // Construct the output using a BUILD_VECTOR.
6047 Output[l] = DAG.getNode(ISD::BUILD_VECTOR, dl, NVT, &SVOps[0],
6049 } else if (InputUsed[0] < 0) {
6050 // No input vectors were used! The result is undefined.
6051 Output[l] = DAG.getUNDEF(NVT);
6053 SDValue Op0 = Extract128BitVector(SVOp->getOperand(InputUsed[0] / 2),
6054 (InputUsed[0] % 2) * NumLaneElems,
6056 // If only one input was used, use an undefined vector for the other.
6057 SDValue Op1 = (InputUsed[1] < 0) ? DAG.getUNDEF(NVT) :
6058 Extract128BitVector(SVOp->getOperand(InputUsed[1] / 2),
6059 (InputUsed[1] % 2) * NumLaneElems, DAG, dl);
6060 // At least one input vector was used. Create a new shuffle vector.
6061 Output[l] = DAG.getVectorShuffle(NVT, dl, Op0, Op1, &Mask[0]);
6067 // Concatenate the result back
6068 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, Output[0], Output[1]);
6071 /// LowerVECTOR_SHUFFLE_128v4 - Handle all 128-bit wide vectors with
6072 /// 4 elements, and match them with several different shuffle types.
6074 LowerVECTOR_SHUFFLE_128v4(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
6075 SDValue V1 = SVOp->getOperand(0);
6076 SDValue V2 = SVOp->getOperand(1);
6077 DebugLoc dl = SVOp->getDebugLoc();
6078 EVT VT = SVOp->getValueType(0);
6080 assert(VT.getSizeInBits() == 128 && "Unsupported vector size");
6082 std::pair<int, int> Locs[4];
6083 int Mask1[] = { -1, -1, -1, -1 };
6084 SmallVector<int, 8> PermMask(SVOp->getMask().begin(), SVOp->getMask().end());
6088 for (unsigned i = 0; i != 4; ++i) {
6089 int Idx = PermMask[i];
6091 Locs[i] = std::make_pair(-1, -1);
6093 assert(Idx < 8 && "Invalid VECTOR_SHUFFLE index!");
6095 Locs[i] = std::make_pair(0, NumLo);
6099 Locs[i] = std::make_pair(1, NumHi);
6101 Mask1[2+NumHi] = Idx;
6107 if (NumLo <= 2 && NumHi <= 2) {
6108 // If no more than two elements come from either vector. This can be
6109 // implemented with two shuffles. First shuffle gather the elements.
6110 // The second shuffle, which takes the first shuffle as both of its
6111 // vector operands, put the elements into the right order.
6112 V1 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
6114 int Mask2[] = { -1, -1, -1, -1 };
6116 for (unsigned i = 0; i != 4; ++i)
6117 if (Locs[i].first != -1) {
6118 unsigned Idx = (i < 2) ? 0 : 4;
6119 Idx += Locs[i].first * 2 + Locs[i].second;
6123 return DAG.getVectorShuffle(VT, dl, V1, V1, &Mask2[0]);
6126 if (NumLo == 3 || NumHi == 3) {
6127 // Otherwise, we must have three elements from one vector, call it X, and
6128 // one element from the other, call it Y. First, use a shufps to build an
6129 // intermediate vector with the one element from Y and the element from X
6130 // that will be in the same half in the final destination (the indexes don't
6131 // matter). Then, use a shufps to build the final vector, taking the half
6132 // containing the element from Y from the intermediate, and the other half
6135 // Normalize it so the 3 elements come from V1.
6136 CommuteVectorShuffleMask(PermMask, 4);
6140 // Find the element from V2.
6142 for (HiIndex = 0; HiIndex < 3; ++HiIndex) {
6143 int Val = PermMask[HiIndex];
6150 Mask1[0] = PermMask[HiIndex];
6152 Mask1[2] = PermMask[HiIndex^1];
6154 V2 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
6157 Mask1[0] = PermMask[0];
6158 Mask1[1] = PermMask[1];
6159 Mask1[2] = HiIndex & 1 ? 6 : 4;
6160 Mask1[3] = HiIndex & 1 ? 4 : 6;
6161 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
6164 Mask1[0] = HiIndex & 1 ? 2 : 0;
6165 Mask1[1] = HiIndex & 1 ? 0 : 2;
6166 Mask1[2] = PermMask[2];
6167 Mask1[3] = PermMask[3];
6172 return DAG.getVectorShuffle(VT, dl, V2, V1, &Mask1[0]);
6175 // Break it into (shuffle shuffle_hi, shuffle_lo).
6176 int LoMask[] = { -1, -1, -1, -1 };
6177 int HiMask[] = { -1, -1, -1, -1 };
6179 int *MaskPtr = LoMask;
6180 unsigned MaskIdx = 0;
6183 for (unsigned i = 0; i != 4; ++i) {
6190 int Idx = PermMask[i];
6192 Locs[i] = std::make_pair(-1, -1);
6193 } else if (Idx < 4) {
6194 Locs[i] = std::make_pair(MaskIdx, LoIdx);
6195 MaskPtr[LoIdx] = Idx;
6198 Locs[i] = std::make_pair(MaskIdx, HiIdx);
6199 MaskPtr[HiIdx] = Idx;
6204 SDValue LoShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &LoMask[0]);
6205 SDValue HiShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &HiMask[0]);
6206 int MaskOps[] = { -1, -1, -1, -1 };
6207 for (unsigned i = 0; i != 4; ++i)
6208 if (Locs[i].first != -1)
6209 MaskOps[i] = Locs[i].first * 4 + Locs[i].second;
6210 return DAG.getVectorShuffle(VT, dl, LoShuffle, HiShuffle, &MaskOps[0]);
6213 static bool MayFoldVectorLoad(SDValue V) {
6214 if (V.hasOneUse() && V.getOpcode() == ISD::BITCAST)
6215 V = V.getOperand(0);
6216 if (V.hasOneUse() && V.getOpcode() == ISD::SCALAR_TO_VECTOR)
6217 V = V.getOperand(0);
6218 if (V.hasOneUse() && V.getOpcode() == ISD::BUILD_VECTOR &&
6219 V.getNumOperands() == 2 && V.getOperand(1).getOpcode() == ISD::UNDEF)
6220 // BUILD_VECTOR (load), undef
6221 V = V.getOperand(0);
6227 // FIXME: the version above should always be used. Since there's
6228 // a bug where several vector shuffles can't be folded because the
6229 // DAG is not updated during lowering and a node claims to have two
6230 // uses while it only has one, use this version, and let isel match
6231 // another instruction if the load really happens to have more than
6232 // one use. Remove this version after this bug get fixed.
6233 // rdar://8434668, PR8156
6234 static bool RelaxedMayFoldVectorLoad(SDValue V) {
6235 if (V.hasOneUse() && V.getOpcode() == ISD::BITCAST)
6236 V = V.getOperand(0);
6237 if (V.hasOneUse() && V.getOpcode() == ISD::SCALAR_TO_VECTOR)
6238 V = V.getOperand(0);
6239 if (ISD::isNormalLoad(V.getNode()))
6245 SDValue getMOVDDup(SDValue &Op, DebugLoc &dl, SDValue V1, SelectionDAG &DAG) {
6246 EVT VT = Op.getValueType();
6248 // Canonizalize to v2f64.
6249 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, V1);
6250 return DAG.getNode(ISD::BITCAST, dl, VT,
6251 getTargetShuffleNode(X86ISD::MOVDDUP, dl, MVT::v2f64,
6256 SDValue getMOVLowToHigh(SDValue &Op, DebugLoc &dl, SelectionDAG &DAG,
6258 SDValue V1 = Op.getOperand(0);
6259 SDValue V2 = Op.getOperand(1);
6260 EVT VT = Op.getValueType();
6262 assert(VT != MVT::v2i64 && "unsupported shuffle type");
6264 if (HasSSE2 && VT == MVT::v2f64)
6265 return getTargetShuffleNode(X86ISD::MOVLHPD, dl, VT, V1, V2, DAG);
6267 // v4f32 or v4i32: canonizalized to v4f32 (which is legal for SSE1)
6268 return DAG.getNode(ISD::BITCAST, dl, VT,
6269 getTargetShuffleNode(X86ISD::MOVLHPS, dl, MVT::v4f32,
6270 DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V1),
6271 DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V2), DAG));
6275 SDValue getMOVHighToLow(SDValue &Op, DebugLoc &dl, SelectionDAG &DAG) {
6276 SDValue V1 = Op.getOperand(0);
6277 SDValue V2 = Op.getOperand(1);
6278 EVT VT = Op.getValueType();
6280 assert((VT == MVT::v4i32 || VT == MVT::v4f32) &&
6281 "unsupported shuffle type");
6283 if (V2.getOpcode() == ISD::UNDEF)
6287 return getTargetShuffleNode(X86ISD::MOVHLPS, dl, VT, V1, V2, DAG);
6291 SDValue getMOVLP(SDValue &Op, DebugLoc &dl, SelectionDAG &DAG, bool HasSSE2) {
6292 SDValue V1 = Op.getOperand(0);
6293 SDValue V2 = Op.getOperand(1);
6294 EVT VT = Op.getValueType();
6295 unsigned NumElems = VT.getVectorNumElements();
6297 // Use MOVLPS and MOVLPD in case V1 or V2 are loads. During isel, the second
6298 // operand of these instructions is only memory, so check if there's a
6299 // potencial load folding here, otherwise use SHUFPS or MOVSD to match the
6301 bool CanFoldLoad = false;
6303 // Trivial case, when V2 comes from a load.
6304 if (MayFoldVectorLoad(V2))
6307 // When V1 is a load, it can be folded later into a store in isel, example:
6308 // (store (v4f32 (X86Movlps (load addr:$src1), VR128:$src2)), addr:$src1)
6310 // (MOVLPSmr addr:$src1, VR128:$src2)
6311 // So, recognize this potential and also use MOVLPS or MOVLPD
6312 else if (MayFoldVectorLoad(V1) && MayFoldIntoStore(Op))
6315 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
6317 if (HasSSE2 && NumElems == 2)
6318 return getTargetShuffleNode(X86ISD::MOVLPD, dl, VT, V1, V2, DAG);
6321 // If we don't care about the second element, procede to use movss.
6322 if (SVOp->getMaskElt(1) != -1)
6323 return getTargetShuffleNode(X86ISD::MOVLPS, dl, VT, V1, V2, DAG);
6326 // movl and movlp will both match v2i64, but v2i64 is never matched by
6327 // movl earlier because we make it strict to avoid messing with the movlp load
6328 // folding logic (see the code above getMOVLP call). Match it here then,
6329 // this is horrible, but will stay like this until we move all shuffle
6330 // matching to x86 specific nodes. Note that for the 1st condition all
6331 // types are matched with movsd.
6333 // FIXME: isMOVLMask should be checked and matched before getMOVLP,
6334 // as to remove this logic from here, as much as possible
6335 if (NumElems == 2 || !isMOVLMask(SVOp->getMask(), VT))
6336 return getTargetShuffleNode(X86ISD::MOVSD, dl, VT, V1, V2, DAG);
6337 return getTargetShuffleNode(X86ISD::MOVSS, dl, VT, V1, V2, DAG);
6340 assert(VT != MVT::v4i32 && "unsupported shuffle type");
6342 // Invert the operand order and use SHUFPS to match it.
6343 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V2, V1,
6344 getShuffleSHUFImmediate(SVOp), DAG);
6348 X86TargetLowering::NormalizeVectorShuffle(SDValue Op, SelectionDAG &DAG) const {
6349 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
6350 EVT VT = Op.getValueType();
6351 DebugLoc dl = Op.getDebugLoc();
6352 SDValue V1 = Op.getOperand(0);
6353 SDValue V2 = Op.getOperand(1);
6355 if (isZeroShuffle(SVOp))
6356 return getZeroVector(VT, Subtarget, DAG, dl);
6358 // Handle splat operations
6359 if (SVOp->isSplat()) {
6360 unsigned NumElem = VT.getVectorNumElements();
6361 int Size = VT.getSizeInBits();
6363 // Use vbroadcast whenever the splat comes from a foldable load
6364 SDValue Broadcast = LowerVectorBroadcast(Op, DAG);
6365 if (Broadcast.getNode())
6368 // Handle splats by matching through known shuffle masks
6369 if ((Size == 128 && NumElem <= 4) ||
6370 (Size == 256 && NumElem < 8))
6373 // All remaning splats are promoted to target supported vector shuffles.
6374 return PromoteSplat(SVOp, DAG);
6377 // If the shuffle can be profitably rewritten as a narrower shuffle, then
6379 if (VT == MVT::v8i16 || VT == MVT::v16i8 ||
6380 VT == MVT::v16i16 || VT == MVT::v32i8) {
6381 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG, dl);
6382 if (NewOp.getNode())
6383 return DAG.getNode(ISD::BITCAST, dl, VT, NewOp);
6384 } else if ((VT == MVT::v4i32 ||
6385 (VT == MVT::v4f32 && Subtarget->hasSSE2()))) {
6386 // FIXME: Figure out a cleaner way to do this.
6387 // Try to make use of movq to zero out the top part.
6388 if (ISD::isBuildVectorAllZeros(V2.getNode())) {
6389 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG, dl);
6390 if (NewOp.getNode()) {
6391 EVT NewVT = NewOp.getValueType();
6392 if (isCommutedMOVLMask(cast<ShuffleVectorSDNode>(NewOp)->getMask(),
6393 NewVT, true, false))
6394 return getVZextMovL(VT, NewVT, NewOp.getOperand(0),
6395 DAG, Subtarget, dl);
6397 } else if (ISD::isBuildVectorAllZeros(V1.getNode())) {
6398 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG, dl);
6399 if (NewOp.getNode()) {
6400 EVT NewVT = NewOp.getValueType();
6401 if (isMOVLMask(cast<ShuffleVectorSDNode>(NewOp)->getMask(), NewVT))
6402 return getVZextMovL(VT, NewVT, NewOp.getOperand(1),
6403 DAG, Subtarget, dl);
6411 X86TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const {
6412 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
6413 SDValue V1 = Op.getOperand(0);
6414 SDValue V2 = Op.getOperand(1);
6415 EVT VT = Op.getValueType();
6416 DebugLoc dl = Op.getDebugLoc();
6417 unsigned NumElems = VT.getVectorNumElements();
6418 bool V1IsUndef = V1.getOpcode() == ISD::UNDEF;
6419 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
6420 bool V1IsSplat = false;
6421 bool V2IsSplat = false;
6422 bool HasSSE2 = Subtarget->hasSSE2();
6423 bool HasAVX = Subtarget->hasAVX();
6424 bool HasAVX2 = Subtarget->hasAVX2();
6425 MachineFunction &MF = DAG.getMachineFunction();
6426 bool OptForSize = MF.getFunction()->hasFnAttr(Attribute::OptimizeForSize);
6428 assert(VT.getSizeInBits() != 64 && "Can't lower MMX shuffles");
6430 if (V1IsUndef && V2IsUndef)
6431 return DAG.getUNDEF(VT);
6433 assert(!V1IsUndef && "Op 1 of shuffle should not be undef");
6435 // Vector shuffle lowering takes 3 steps:
6437 // 1) Normalize the input vectors. Here splats, zeroed vectors, profitable
6438 // narrowing and commutation of operands should be handled.
6439 // 2) Matching of shuffles with known shuffle masks to x86 target specific
6441 // 3) Rewriting of unmatched masks into new generic shuffle operations,
6442 // so the shuffle can be broken into other shuffles and the legalizer can
6443 // try the lowering again.
6445 // The general idea is that no vector_shuffle operation should be left to
6446 // be matched during isel, all of them must be converted to a target specific
6449 // Normalize the input vectors. Here splats, zeroed vectors, profitable
6450 // narrowing and commutation of operands should be handled. The actual code
6451 // doesn't include all of those, work in progress...
6452 SDValue NewOp = NormalizeVectorShuffle(Op, DAG);
6453 if (NewOp.getNode())
6456 SmallVector<int, 8> M(SVOp->getMask().begin(), SVOp->getMask().end());
6458 // NOTE: isPSHUFDMask can also match both masks below (unpckl_undef and
6459 // unpckh_undef). Only use pshufd if speed is more important than size.
6460 if (OptForSize && isUNPCKL_v_undef_Mask(M, VT, HasAVX2))
6461 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
6462 if (OptForSize && isUNPCKH_v_undef_Mask(M, VT, HasAVX2))
6463 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
6465 if (isMOVDDUPMask(M, VT) && Subtarget->hasSSE3() &&
6466 V2IsUndef && RelaxedMayFoldVectorLoad(V1))
6467 return getMOVDDup(Op, dl, V1, DAG);
6469 if (isMOVHLPS_v_undef_Mask(M, VT))
6470 return getMOVHighToLow(Op, dl, DAG);
6472 // Use to match splats
6473 if (HasSSE2 && isUNPCKHMask(M, VT, HasAVX2) && V2IsUndef &&
6474 (VT == MVT::v2f64 || VT == MVT::v2i64))
6475 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
6477 if (isPSHUFDMask(M, VT)) {
6478 // The actual implementation will match the mask in the if above and then
6479 // during isel it can match several different instructions, not only pshufd
6480 // as its name says, sad but true, emulate the behavior for now...
6481 if (isMOVDDUPMask(M, VT) && ((VT == MVT::v4f32 || VT == MVT::v2i64)))
6482 return getTargetShuffleNode(X86ISD::MOVLHPS, dl, VT, V1, V1, DAG);
6484 unsigned TargetMask = getShuffleSHUFImmediate(SVOp);
6486 if (HasAVX && (VT == MVT::v4f32 || VT == MVT::v2f64))
6487 return getTargetShuffleNode(X86ISD::VPERMILP, dl, VT, V1, TargetMask, DAG);
6489 if (HasSSE2 && (VT == MVT::v4f32 || VT == MVT::v4i32))
6490 return getTargetShuffleNode(X86ISD::PSHUFD, dl, VT, V1, TargetMask, DAG);
6492 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V1, V1,
6496 // Check if this can be converted into a logical shift.
6497 bool isLeft = false;
6500 bool isShift = HasSSE2 && isVectorShift(SVOp, DAG, isLeft, ShVal, ShAmt);
6501 if (isShift && ShVal.hasOneUse()) {
6502 // If the shifted value has multiple uses, it may be cheaper to use
6503 // v_set0 + movlhps or movhlps, etc.
6504 EVT EltVT = VT.getVectorElementType();
6505 ShAmt *= EltVT.getSizeInBits();
6506 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl);
6509 if (isMOVLMask(M, VT)) {
6510 if (ISD::isBuildVectorAllZeros(V1.getNode()))
6511 return getVZextMovL(VT, VT, V2, DAG, Subtarget, dl);
6512 if (!isMOVLPMask(M, VT)) {
6513 if (HasSSE2 && (VT == MVT::v2i64 || VT == MVT::v2f64))
6514 return getTargetShuffleNode(X86ISD::MOVSD, dl, VT, V1, V2, DAG);
6516 if (VT == MVT::v4i32 || VT == MVT::v4f32)
6517 return getTargetShuffleNode(X86ISD::MOVSS, dl, VT, V1, V2, DAG);
6521 // FIXME: fold these into legal mask.
6522 if (isMOVLHPSMask(M, VT) && !isUNPCKLMask(M, VT, HasAVX2))
6523 return getMOVLowToHigh(Op, dl, DAG, HasSSE2);
6525 if (isMOVHLPSMask(M, VT))
6526 return getMOVHighToLow(Op, dl, DAG);
6528 if (V2IsUndef && isMOVSHDUPMask(M, VT, Subtarget))
6529 return getTargetShuffleNode(X86ISD::MOVSHDUP, dl, VT, V1, DAG);
6531 if (V2IsUndef && isMOVSLDUPMask(M, VT, Subtarget))
6532 return getTargetShuffleNode(X86ISD::MOVSLDUP, dl, VT, V1, DAG);
6534 if (isMOVLPMask(M, VT))
6535 return getMOVLP(Op, dl, DAG, HasSSE2);
6537 if (ShouldXformToMOVHLPS(M, VT) ||
6538 ShouldXformToMOVLP(V1.getNode(), V2.getNode(), M, VT))
6539 return CommuteVectorShuffle(SVOp, DAG);
6542 // No better options. Use a vshldq / vsrldq.
6543 EVT EltVT = VT.getVectorElementType();
6544 ShAmt *= EltVT.getSizeInBits();
6545 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl);
6548 bool Commuted = false;
6549 // FIXME: This should also accept a bitcast of a splat? Be careful, not
6550 // 1,1,1,1 -> v8i16 though.
6551 V1IsSplat = isSplatVector(V1.getNode());
6552 V2IsSplat = isSplatVector(V2.getNode());
6554 // Canonicalize the splat or undef, if present, to be on the RHS.
6555 if (!V2IsUndef && V1IsSplat && !V2IsSplat) {
6556 CommuteVectorShuffleMask(M, NumElems);
6558 std::swap(V1IsSplat, V2IsSplat);
6562 if (isCommutedMOVLMask(M, VT, V2IsSplat, V2IsUndef)) {
6563 // Shuffling low element of v1 into undef, just return v1.
6566 // If V2 is a splat, the mask may be malformed such as <4,3,3,3>, which
6567 // the instruction selector will not match, so get a canonical MOVL with
6568 // swapped operands to undo the commute.
6569 return getMOVL(DAG, dl, VT, V2, V1);
6572 if (isUNPCKLMask(M, VT, HasAVX2))
6573 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG);
6575 if (isUNPCKHMask(M, VT, HasAVX2))
6576 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG);
6579 // Normalize mask so all entries that point to V2 points to its first
6580 // element then try to match unpck{h|l} again. If match, return a
6581 // new vector_shuffle with the corrected mask.p
6582 SmallVector<int, 8> NewMask(M.begin(), M.end());
6583 NormalizeMask(NewMask, NumElems);
6584 if (isUNPCKLMask(NewMask, VT, HasAVX2, true))
6585 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG);
6586 if (isUNPCKHMask(NewMask, VT, HasAVX2, true))
6587 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG);
6591 // Commute is back and try unpck* again.
6592 // FIXME: this seems wrong.
6593 CommuteVectorShuffleMask(M, NumElems);
6595 std::swap(V1IsSplat, V2IsSplat);
6598 if (isUNPCKLMask(M, VT, HasAVX2))
6599 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG);
6601 if (isUNPCKHMask(M, VT, HasAVX2))
6602 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG);
6605 // Normalize the node to match x86 shuffle ops if needed
6606 if (!V2IsUndef && (isSHUFPMask(M, VT, HasAVX, /* Commuted */ true)))
6607 return CommuteVectorShuffle(SVOp, DAG);
6609 // The checks below are all present in isShuffleMaskLegal, but they are
6610 // inlined here right now to enable us to directly emit target specific
6611 // nodes, and remove one by one until they don't return Op anymore.
6613 if (isPALIGNRMask(M, VT, Subtarget))
6614 return getTargetShuffleNode(X86ISD::PALIGN, dl, VT, V1, V2,
6615 getShufflePALIGNRImmediate(SVOp),
6618 if (ShuffleVectorSDNode::isSplatMask(&M[0], VT) &&
6619 SVOp->getSplatIndex() == 0 && V2IsUndef) {
6620 if (VT == MVT::v2f64 || VT == MVT::v2i64)
6621 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
6624 if (isPSHUFHWMask(M, VT, HasAVX2))
6625 return getTargetShuffleNode(X86ISD::PSHUFHW, dl, VT, V1,
6626 getShufflePSHUFHWImmediate(SVOp),
6629 if (isPSHUFLWMask(M, VT, HasAVX2))
6630 return getTargetShuffleNode(X86ISD::PSHUFLW, dl, VT, V1,
6631 getShufflePSHUFLWImmediate(SVOp),
6634 if (isSHUFPMask(M, VT, HasAVX))
6635 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V1, V2,
6636 getShuffleSHUFImmediate(SVOp), DAG);
6638 if (isUNPCKL_v_undef_Mask(M, VT, HasAVX2))
6639 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
6640 if (isUNPCKH_v_undef_Mask(M, VT, HasAVX2))
6641 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
6643 //===--------------------------------------------------------------------===//
6644 // Generate target specific nodes for 128 or 256-bit shuffles only
6645 // supported in the AVX instruction set.
6648 // Handle VMOVDDUPY permutations
6649 if (V2IsUndef && isMOVDDUPYMask(M, VT, HasAVX))
6650 return getTargetShuffleNode(X86ISD::MOVDDUP, dl, VT, V1, DAG);
6652 // Handle VPERMILPS/D* permutations
6653 if (isVPERMILPMask(M, VT, HasAVX)) {
6654 if (HasAVX2 && VT == MVT::v8i32)
6655 return getTargetShuffleNode(X86ISD::PSHUFD, dl, VT, V1,
6656 getShuffleSHUFImmediate(SVOp), DAG);
6657 return getTargetShuffleNode(X86ISD::VPERMILP, dl, VT, V1,
6658 getShuffleSHUFImmediate(SVOp), DAG);
6661 // Handle VPERM2F128/VPERM2I128 permutations
6662 if (isVPERM2X128Mask(M, VT, HasAVX))
6663 return getTargetShuffleNode(X86ISD::VPERM2X128, dl, VT, V1,
6664 V2, getShuffleVPERM2X128Immediate(SVOp), DAG);
6666 SDValue BlendOp = LowerVECTOR_SHUFFLEtoBlend(SVOp, Subtarget, DAG);
6667 if (BlendOp.getNode())
6670 if (V2IsUndef && HasAVX2 && (VT == MVT::v8i32 || VT == MVT::v8f32)) {
6671 SmallVector<SDValue, 8> permclMask;
6672 for (unsigned i = 0; i != 8; ++i) {
6673 permclMask.push_back(DAG.getConstant((M[i]>=0) ? M[i] : 0, MVT::i32));
6675 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32,
6677 // Bitcast is for VPERMPS since mask is v8i32 but node takes v8f32
6678 return DAG.getNode(X86ISD::VPERMV, dl, VT,
6679 DAG.getNode(ISD::BITCAST, dl, VT, Mask), V1);
6682 if (V2IsUndef && HasAVX2 && (VT == MVT::v4i64 || VT == MVT::v4f64))
6683 return getTargetShuffleNode(X86ISD::VPERMI, dl, VT, V1,
6684 getShuffleCLImmediate(SVOp), DAG);
6687 //===--------------------------------------------------------------------===//
6688 // Since no target specific shuffle was selected for this generic one,
6689 // lower it into other known shuffles. FIXME: this isn't true yet, but
6690 // this is the plan.
6693 // Handle v8i16 specifically since SSE can do byte extraction and insertion.
6694 if (VT == MVT::v8i16) {
6695 SDValue NewOp = LowerVECTOR_SHUFFLEv8i16(Op, DAG);
6696 if (NewOp.getNode())
6700 if (VT == MVT::v16i8) {
6701 SDValue NewOp = LowerVECTOR_SHUFFLEv16i8(SVOp, DAG, *this);
6702 if (NewOp.getNode())
6706 // Handle all 128-bit wide vectors with 4 elements, and match them with
6707 // several different shuffle types.
6708 if (NumElems == 4 && VT.getSizeInBits() == 128)
6709 return LowerVECTOR_SHUFFLE_128v4(SVOp, DAG);
6711 // Handle general 256-bit shuffles
6712 if (VT.is256BitVector())
6713 return LowerVECTOR_SHUFFLE_256(SVOp, DAG);
6719 X86TargetLowering::LowerEXTRACT_VECTOR_ELT_SSE4(SDValue Op,
6720 SelectionDAG &DAG) const {
6721 EVT VT = Op.getValueType();
6722 DebugLoc dl = Op.getDebugLoc();
6724 if (Op.getOperand(0).getValueType().getSizeInBits() != 128)
6727 if (VT.getSizeInBits() == 8) {
6728 SDValue Extract = DAG.getNode(X86ISD::PEXTRB, dl, MVT::i32,
6729 Op.getOperand(0), Op.getOperand(1));
6730 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
6731 DAG.getValueType(VT));
6732 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
6735 if (VT.getSizeInBits() == 16) {
6736 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
6737 // If Idx is 0, it's cheaper to do a move instead of a pextrw.
6739 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
6740 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
6741 DAG.getNode(ISD::BITCAST, dl,
6745 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, MVT::i32,
6746 Op.getOperand(0), Op.getOperand(1));
6747 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
6748 DAG.getValueType(VT));
6749 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
6752 if (VT == MVT::f32) {
6753 // EXTRACTPS outputs to a GPR32 register which will require a movd to copy
6754 // the result back to FR32 register. It's only worth matching if the
6755 // result has a single use which is a store or a bitcast to i32. And in
6756 // the case of a store, it's not worth it if the index is a constant 0,
6757 // because a MOVSSmr can be used instead, which is smaller and faster.
6758 if (!Op.hasOneUse())
6760 SDNode *User = *Op.getNode()->use_begin();
6761 if ((User->getOpcode() != ISD::STORE ||
6762 (isa<ConstantSDNode>(Op.getOperand(1)) &&
6763 cast<ConstantSDNode>(Op.getOperand(1))->isNullValue())) &&
6764 (User->getOpcode() != ISD::BITCAST ||
6765 User->getValueType(0) != MVT::i32))
6767 SDValue Extract = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
6768 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32,
6771 return DAG.getNode(ISD::BITCAST, dl, MVT::f32, Extract);
6774 if (VT == MVT::i32 || VT == MVT::i64) {
6775 // ExtractPS/pextrq works with constant index.
6776 if (isa<ConstantSDNode>(Op.getOperand(1)))
6784 X86TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op,
6785 SelectionDAG &DAG) const {
6786 if (!isa<ConstantSDNode>(Op.getOperand(1)))
6789 SDValue Vec = Op.getOperand(0);
6790 EVT VecVT = Vec.getValueType();
6792 // If this is a 256-bit vector result, first extract the 128-bit vector and
6793 // then extract the element from the 128-bit vector.
6794 if (VecVT.getSizeInBits() == 256) {
6795 DebugLoc dl = Op.getNode()->getDebugLoc();
6796 unsigned NumElems = VecVT.getVectorNumElements();
6797 SDValue Idx = Op.getOperand(1);
6798 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
6800 // Get the 128-bit vector.
6801 Vec = Extract128BitVector(Vec, IdxVal, DAG, dl);
6803 if (IdxVal >= NumElems/2)
6804 IdxVal -= NumElems/2;
6805 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, Op.getValueType(), Vec,
6806 DAG.getConstant(IdxVal, MVT::i32));
6809 assert(Vec.getValueSizeInBits() <= 128 && "Unexpected vector length");
6811 if (Subtarget->hasSSE41()) {
6812 SDValue Res = LowerEXTRACT_VECTOR_ELT_SSE4(Op, DAG);
6817 EVT VT = Op.getValueType();
6818 DebugLoc dl = Op.getDebugLoc();
6819 // TODO: handle v16i8.
6820 if (VT.getSizeInBits() == 16) {
6821 SDValue Vec = Op.getOperand(0);
6822 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
6824 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
6825 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
6826 DAG.getNode(ISD::BITCAST, dl,
6829 // Transform it so it match pextrw which produces a 32-bit result.
6830 EVT EltVT = MVT::i32;
6831 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, EltVT,
6832 Op.getOperand(0), Op.getOperand(1));
6833 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, EltVT, Extract,
6834 DAG.getValueType(VT));
6835 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
6838 if (VT.getSizeInBits() == 32) {
6839 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
6843 // SHUFPS the element to the lowest double word, then movss.
6844 int Mask[4] = { static_cast<int>(Idx), -1, -1, -1 };
6845 EVT VVT = Op.getOperand(0).getValueType();
6846 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
6847 DAG.getUNDEF(VVT), Mask);
6848 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
6849 DAG.getIntPtrConstant(0));
6852 if (VT.getSizeInBits() == 64) {
6853 // FIXME: .td only matches this for <2 x f64>, not <2 x i64> on 32b
6854 // FIXME: seems like this should be unnecessary if mov{h,l}pd were taught
6855 // to match extract_elt for f64.
6856 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
6860 // UNPCKHPD the element to the lowest double word, then movsd.
6861 // Note if the lower 64 bits of the result of the UNPCKHPD is then stored
6862 // to a f64mem, the whole operation is folded into a single MOVHPDmr.
6863 int Mask[2] = { 1, -1 };
6864 EVT VVT = Op.getOperand(0).getValueType();
6865 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
6866 DAG.getUNDEF(VVT), Mask);
6867 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
6868 DAG.getIntPtrConstant(0));
6875 X86TargetLowering::LowerINSERT_VECTOR_ELT_SSE4(SDValue Op,
6876 SelectionDAG &DAG) const {
6877 EVT VT = Op.getValueType();
6878 EVT EltVT = VT.getVectorElementType();
6879 DebugLoc dl = Op.getDebugLoc();
6881 SDValue N0 = Op.getOperand(0);
6882 SDValue N1 = Op.getOperand(1);
6883 SDValue N2 = Op.getOperand(2);
6885 if (VT.getSizeInBits() == 256)
6888 if ((EltVT.getSizeInBits() == 8 || EltVT.getSizeInBits() == 16) &&
6889 isa<ConstantSDNode>(N2)) {
6891 if (VT == MVT::v8i16)
6892 Opc = X86ISD::PINSRW;
6893 else if (VT == MVT::v16i8)
6894 Opc = X86ISD::PINSRB;
6896 Opc = X86ISD::PINSRB;
6898 // Transform it so it match pinsr{b,w} which expects a GR32 as its second
6900 if (N1.getValueType() != MVT::i32)
6901 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
6902 if (N2.getValueType() != MVT::i32)
6903 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue());
6904 return DAG.getNode(Opc, dl, VT, N0, N1, N2);
6907 if (EltVT == MVT::f32 && isa<ConstantSDNode>(N2)) {
6908 // Bits [7:6] of the constant are the source select. This will always be
6909 // zero here. The DAG Combiner may combine an extract_elt index into these
6910 // bits. For example (insert (extract, 3), 2) could be matched by putting
6911 // the '3' into bits [7:6] of X86ISD::INSERTPS.
6912 // Bits [5:4] of the constant are the destination select. This is the
6913 // value of the incoming immediate.
6914 // Bits [3:0] of the constant are the zero mask. The DAG Combiner may
6915 // combine either bitwise AND or insert of float 0.0 to set these bits.
6916 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue() << 4);
6917 // Create this as a scalar to vector..
6918 N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4f32, N1);
6919 return DAG.getNode(X86ISD::INSERTPS, dl, VT, N0, N1, N2);
6922 if ((EltVT == MVT::i32 || EltVT == MVT::i64) && isa<ConstantSDNode>(N2)) {
6923 // PINSR* works with constant index.
6930 X86TargetLowering::LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const {
6931 EVT VT = Op.getValueType();
6932 EVT EltVT = VT.getVectorElementType();
6934 DebugLoc dl = Op.getDebugLoc();
6935 SDValue N0 = Op.getOperand(0);
6936 SDValue N1 = Op.getOperand(1);
6937 SDValue N2 = Op.getOperand(2);
6939 // If this is a 256-bit vector result, first extract the 128-bit vector,
6940 // insert the element into the extracted half and then place it back.
6941 if (VT.getSizeInBits() == 256) {
6942 if (!isa<ConstantSDNode>(N2))
6945 // Get the desired 128-bit vector half.
6946 unsigned NumElems = VT.getVectorNumElements();
6947 unsigned IdxVal = cast<ConstantSDNode>(N2)->getZExtValue();
6948 SDValue V = Extract128BitVector(N0, IdxVal, DAG, dl);
6950 // Insert the element into the desired half.
6951 bool Upper = IdxVal >= NumElems/2;
6952 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, V.getValueType(), V, N1,
6953 DAG.getConstant(Upper ? IdxVal-NumElems/2 : IdxVal, MVT::i32));
6955 // Insert the changed part back to the 256-bit vector
6956 return Insert128BitVector(N0, V, IdxVal, DAG, dl);
6959 if (Subtarget->hasSSE41())
6960 return LowerINSERT_VECTOR_ELT_SSE4(Op, DAG);
6962 if (EltVT == MVT::i8)
6965 if (EltVT.getSizeInBits() == 16 && isa<ConstantSDNode>(N2)) {
6966 // Transform it so it match pinsrw which expects a 16-bit value in a GR32
6967 // as its second argument.
6968 if (N1.getValueType() != MVT::i32)
6969 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
6970 if (N2.getValueType() != MVT::i32)
6971 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue());
6972 return DAG.getNode(X86ISD::PINSRW, dl, VT, N0, N1, N2);
6978 X86TargetLowering::LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) const {
6979 LLVMContext *Context = DAG.getContext();
6980 DebugLoc dl = Op.getDebugLoc();
6981 EVT OpVT = Op.getValueType();
6983 // If this is a 256-bit vector result, first insert into a 128-bit
6984 // vector and then insert into the 256-bit vector.
6985 if (OpVT.getSizeInBits() > 128) {
6986 // Insert into a 128-bit vector.
6987 EVT VT128 = EVT::getVectorVT(*Context,
6988 OpVT.getVectorElementType(),
6989 OpVT.getVectorNumElements() / 2);
6991 Op = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT128, Op.getOperand(0));
6993 // Insert the 128-bit vector.
6994 return Insert128BitVector(DAG.getUNDEF(OpVT), Op, 0, DAG, dl);
6997 if (OpVT == MVT::v1i64 &&
6998 Op.getOperand(0).getValueType() == MVT::i64)
6999 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v1i64, Op.getOperand(0));
7001 SDValue AnyExt = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, Op.getOperand(0));
7002 assert(OpVT.getSizeInBits() == 128 && "Expected an SSE type!");
7003 return DAG.getNode(ISD::BITCAST, dl, OpVT,
7004 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,AnyExt));
7007 // Lower a node with an EXTRACT_SUBVECTOR opcode. This may result in
7008 // a simple subregister reference or explicit instructions to grab
7009 // upper bits of a vector.
7011 X86TargetLowering::LowerEXTRACT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const {
7012 if (Subtarget->hasAVX()) {
7013 DebugLoc dl = Op.getNode()->getDebugLoc();
7014 SDValue Vec = Op.getNode()->getOperand(0);
7015 SDValue Idx = Op.getNode()->getOperand(1);
7017 if (Op.getNode()->getValueType(0).getSizeInBits() == 128 &&
7018 Vec.getNode()->getValueType(0).getSizeInBits() == 256 &&
7019 isa<ConstantSDNode>(Idx)) {
7020 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
7021 return Extract128BitVector(Vec, IdxVal, DAG, dl);
7027 // Lower a node with an INSERT_SUBVECTOR opcode. This may result in a
7028 // simple superregister reference or explicit instructions to insert
7029 // the upper bits of a vector.
7031 X86TargetLowering::LowerINSERT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const {
7032 if (Subtarget->hasAVX()) {
7033 DebugLoc dl = Op.getNode()->getDebugLoc();
7034 SDValue Vec = Op.getNode()->getOperand(0);
7035 SDValue SubVec = Op.getNode()->getOperand(1);
7036 SDValue Idx = Op.getNode()->getOperand(2);
7038 if (Op.getNode()->getValueType(0).getSizeInBits() == 256 &&
7039 SubVec.getNode()->getValueType(0).getSizeInBits() == 128 &&
7040 isa<ConstantSDNode>(Idx)) {
7041 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
7042 return Insert128BitVector(Vec, SubVec, IdxVal, DAG, dl);
7048 // ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as
7049 // their target countpart wrapped in the X86ISD::Wrapper node. Suppose N is
7050 // one of the above mentioned nodes. It has to be wrapped because otherwise
7051 // Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only
7052 // be used to form addressing mode. These wrapped nodes will be selected
7055 X86TargetLowering::LowerConstantPool(SDValue Op, SelectionDAG &DAG) const {
7056 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
7058 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
7060 unsigned char OpFlag = 0;
7061 unsigned WrapperKind = X86ISD::Wrapper;
7062 CodeModel::Model M = getTargetMachine().getCodeModel();
7064 if (Subtarget->isPICStyleRIPRel() &&
7065 (M == CodeModel::Small || M == CodeModel::Kernel))
7066 WrapperKind = X86ISD::WrapperRIP;
7067 else if (Subtarget->isPICStyleGOT())
7068 OpFlag = X86II::MO_GOTOFF;
7069 else if (Subtarget->isPICStyleStubPIC())
7070 OpFlag = X86II::MO_PIC_BASE_OFFSET;
7072 SDValue Result = DAG.getTargetConstantPool(CP->getConstVal(), getPointerTy(),
7074 CP->getOffset(), OpFlag);
7075 DebugLoc DL = CP->getDebugLoc();
7076 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
7077 // With PIC, the address is actually $g + Offset.
7079 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
7080 DAG.getNode(X86ISD::GlobalBaseReg,
7081 DebugLoc(), getPointerTy()),
7088 SDValue X86TargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) const {
7089 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
7091 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
7093 unsigned char OpFlag = 0;
7094 unsigned WrapperKind = X86ISD::Wrapper;
7095 CodeModel::Model M = getTargetMachine().getCodeModel();
7097 if (Subtarget->isPICStyleRIPRel() &&
7098 (M == CodeModel::Small || M == CodeModel::Kernel))
7099 WrapperKind = X86ISD::WrapperRIP;
7100 else if (Subtarget->isPICStyleGOT())
7101 OpFlag = X86II::MO_GOTOFF;
7102 else if (Subtarget->isPICStyleStubPIC())
7103 OpFlag = X86II::MO_PIC_BASE_OFFSET;
7105 SDValue Result = DAG.getTargetJumpTable(JT->getIndex(), getPointerTy(),
7107 DebugLoc DL = JT->getDebugLoc();
7108 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
7110 // With PIC, the address is actually $g + Offset.
7112 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
7113 DAG.getNode(X86ISD::GlobalBaseReg,
7114 DebugLoc(), getPointerTy()),
7121 X86TargetLowering::LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) const {
7122 const char *Sym = cast<ExternalSymbolSDNode>(Op)->getSymbol();
7124 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
7126 unsigned char OpFlag = 0;
7127 unsigned WrapperKind = X86ISD::Wrapper;
7128 CodeModel::Model M = getTargetMachine().getCodeModel();
7130 if (Subtarget->isPICStyleRIPRel() &&
7131 (M == CodeModel::Small || M == CodeModel::Kernel)) {
7132 if (Subtarget->isTargetDarwin() || Subtarget->isTargetELF())
7133 OpFlag = X86II::MO_GOTPCREL;
7134 WrapperKind = X86ISD::WrapperRIP;
7135 } else if (Subtarget->isPICStyleGOT()) {
7136 OpFlag = X86II::MO_GOT;
7137 } else if (Subtarget->isPICStyleStubPIC()) {
7138 OpFlag = X86II::MO_DARWIN_NONLAZY_PIC_BASE;
7139 } else if (Subtarget->isPICStyleStubNoDynamic()) {
7140 OpFlag = X86II::MO_DARWIN_NONLAZY;
7143 SDValue Result = DAG.getTargetExternalSymbol(Sym, getPointerTy(), OpFlag);
7145 DebugLoc DL = Op.getDebugLoc();
7146 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
7149 // With PIC, the address is actually $g + Offset.
7150 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
7151 !Subtarget->is64Bit()) {
7152 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
7153 DAG.getNode(X86ISD::GlobalBaseReg,
7154 DebugLoc(), getPointerTy()),
7158 // For symbols that require a load from a stub to get the address, emit the
7160 if (isGlobalStubReference(OpFlag))
7161 Result = DAG.getLoad(getPointerTy(), DL, DAG.getEntryNode(), Result,
7162 MachinePointerInfo::getGOT(), false, false, false, 0);
7168 X86TargetLowering::LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const {
7169 // Create the TargetBlockAddressAddress node.
7170 unsigned char OpFlags =
7171 Subtarget->ClassifyBlockAddressReference();
7172 CodeModel::Model M = getTargetMachine().getCodeModel();
7173 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
7174 DebugLoc dl = Op.getDebugLoc();
7175 SDValue Result = DAG.getBlockAddress(BA, getPointerTy(),
7176 /*isTarget=*/true, OpFlags);
7178 if (Subtarget->isPICStyleRIPRel() &&
7179 (M == CodeModel::Small || M == CodeModel::Kernel))
7180 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
7182 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
7184 // With PIC, the address is actually $g + Offset.
7185 if (isGlobalRelativeToPICBase(OpFlags)) {
7186 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
7187 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
7195 X86TargetLowering::LowerGlobalAddress(const GlobalValue *GV, DebugLoc dl,
7197 SelectionDAG &DAG) const {
7198 // Create the TargetGlobalAddress node, folding in the constant
7199 // offset if it is legal.
7200 unsigned char OpFlags =
7201 Subtarget->ClassifyGlobalReference(GV, getTargetMachine());
7202 CodeModel::Model M = getTargetMachine().getCodeModel();
7204 if (OpFlags == X86II::MO_NO_FLAG &&
7205 X86::isOffsetSuitableForCodeModel(Offset, M)) {
7206 // A direct static reference to a global.
7207 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), Offset);
7210 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), 0, OpFlags);
7213 if (Subtarget->isPICStyleRIPRel() &&
7214 (M == CodeModel::Small || M == CodeModel::Kernel))
7215 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
7217 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
7219 // With PIC, the address is actually $g + Offset.
7220 if (isGlobalRelativeToPICBase(OpFlags)) {
7221 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
7222 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
7226 // For globals that require a load from a stub to get the address, emit the
7228 if (isGlobalStubReference(OpFlags))
7229 Result = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Result,
7230 MachinePointerInfo::getGOT(), false, false, false, 0);
7232 // If there was a non-zero offset that we didn't fold, create an explicit
7235 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(), Result,
7236 DAG.getConstant(Offset, getPointerTy()));
7242 X86TargetLowering::LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const {
7243 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
7244 int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset();
7245 return LowerGlobalAddress(GV, Op.getDebugLoc(), Offset, DAG);
7249 GetTLSADDR(SelectionDAG &DAG, SDValue Chain, GlobalAddressSDNode *GA,
7250 SDValue *InFlag, const EVT PtrVT, unsigned ReturnReg,
7251 unsigned char OperandFlags) {
7252 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
7253 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
7254 DebugLoc dl = GA->getDebugLoc();
7255 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
7256 GA->getValueType(0),
7260 SDValue Ops[] = { Chain, TGA, *InFlag };
7261 Chain = DAG.getNode(X86ISD::TLSADDR, dl, NodeTys, Ops, 3);
7263 SDValue Ops[] = { Chain, TGA };
7264 Chain = DAG.getNode(X86ISD::TLSADDR, dl, NodeTys, Ops, 2);
7267 // TLSADDR will be codegen'ed as call. Inform MFI that function has calls.
7268 MFI->setAdjustsStack(true);
7270 SDValue Flag = Chain.getValue(1);
7271 return DAG.getCopyFromReg(Chain, dl, ReturnReg, PtrVT, Flag);
7274 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 32 bit
7276 LowerToTLSGeneralDynamicModel32(GlobalAddressSDNode *GA, SelectionDAG &DAG,
7279 DebugLoc dl = GA->getDebugLoc(); // ? function entry point might be better
7280 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
7281 DAG.getNode(X86ISD::GlobalBaseReg,
7282 DebugLoc(), PtrVT), InFlag);
7283 InFlag = Chain.getValue(1);
7285 return GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX, X86II::MO_TLSGD);
7288 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 64 bit
7290 LowerToTLSGeneralDynamicModel64(GlobalAddressSDNode *GA, SelectionDAG &DAG,
7292 return GetTLSADDR(DAG, DAG.getEntryNode(), GA, NULL, PtrVT,
7293 X86::RAX, X86II::MO_TLSGD);
7296 // Lower ISD::GlobalTLSAddress using the "initial exec" or "local exec" model.
7297 static SDValue LowerToTLSExecModel(GlobalAddressSDNode *GA, SelectionDAG &DAG,
7298 const EVT PtrVT, TLSModel::Model model,
7299 bool is64Bit, bool isPIC) {
7300 DebugLoc dl = GA->getDebugLoc();
7302 // Get the Thread Pointer, which is %gs:0 (32-bit) or %fs:0 (64-bit).
7303 Value *Ptr = Constant::getNullValue(Type::getInt8PtrTy(*DAG.getContext(),
7304 is64Bit ? 257 : 256));
7306 SDValue ThreadPointer = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
7307 DAG.getIntPtrConstant(0),
7308 MachinePointerInfo(Ptr),
7309 false, false, false, 0);
7311 unsigned char OperandFlags = 0;
7312 // Most TLS accesses are not RIP relative, even on x86-64. One exception is
7314 unsigned WrapperKind = X86ISD::Wrapper;
7315 if (model == TLSModel::LocalExec) {
7316 OperandFlags = is64Bit ? X86II::MO_TPOFF : X86II::MO_NTPOFF;
7317 } else if (model == TLSModel::InitialExec) {
7319 OperandFlags = X86II::MO_GOTTPOFF;
7320 WrapperKind = X86ISD::WrapperRIP;
7322 OperandFlags = isPIC ? X86II::MO_GOTNTPOFF : X86II::MO_INDNTPOFF;
7325 llvm_unreachable("Unexpected model");
7328 // emit "addl x@ntpoff,%eax" (local exec)
7329 // or "addl x@indntpoff,%eax" (initial exec)
7330 // or "addl x@gotntpoff(%ebx) ,%eax" (initial exec, 32-bit pic)
7331 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
7332 GA->getValueType(0),
7333 GA->getOffset(), OperandFlags);
7334 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
7336 if (model == TLSModel::InitialExec) {
7337 if (isPIC && !is64Bit) {
7338 Offset = DAG.getNode(ISD::ADD, dl, PtrVT,
7339 DAG.getNode(X86ISD::GlobalBaseReg, DebugLoc(), PtrVT),
7342 Offset = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Offset,
7343 MachinePointerInfo::getGOT(), false, false, false,
7348 // The address of the thread local variable is the add of the thread
7349 // pointer with the offset of the variable.
7350 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset);
7354 X86TargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const {
7356 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
7357 const GlobalValue *GV = GA->getGlobal();
7359 if (Subtarget->isTargetELF()) {
7360 // TODO: implement the "local dynamic" model
7362 // If GV is an alias then use the aliasee for determining
7363 // thread-localness.
7364 if (const GlobalAlias *GA = dyn_cast<GlobalAlias>(GV))
7365 GV = GA->resolveAliasedGlobal(false);
7367 TLSModel::Model model = getTargetMachine().getTLSModel(GV);
7370 case TLSModel::GeneralDynamic:
7371 case TLSModel::LocalDynamic: // not implemented
7372 if (Subtarget->is64Bit())
7373 return LowerToTLSGeneralDynamicModel64(GA, DAG, getPointerTy());
7374 return LowerToTLSGeneralDynamicModel32(GA, DAG, getPointerTy());
7376 case TLSModel::InitialExec:
7377 case TLSModel::LocalExec:
7378 return LowerToTLSExecModel(GA, DAG, getPointerTy(), model,
7379 Subtarget->is64Bit(),
7380 getTargetMachine().getRelocationModel() == Reloc::PIC_);
7382 llvm_unreachable("Unknown TLS model.");
7385 if (Subtarget->isTargetDarwin()) {
7386 // Darwin only has one model of TLS. Lower to that.
7387 unsigned char OpFlag = 0;
7388 unsigned WrapperKind = Subtarget->isPICStyleRIPRel() ?
7389 X86ISD::WrapperRIP : X86ISD::Wrapper;
7391 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
7393 bool PIC32 = (getTargetMachine().getRelocationModel() == Reloc::PIC_) &&
7394 !Subtarget->is64Bit();
7396 OpFlag = X86II::MO_TLVP_PIC_BASE;
7398 OpFlag = X86II::MO_TLVP;
7399 DebugLoc DL = Op.getDebugLoc();
7400 SDValue Result = DAG.getTargetGlobalAddress(GA->getGlobal(), DL,
7401 GA->getValueType(0),
7402 GA->getOffset(), OpFlag);
7403 SDValue Offset = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
7405 // With PIC32, the address is actually $g + Offset.
7407 Offset = DAG.getNode(ISD::ADD, DL, getPointerTy(),
7408 DAG.getNode(X86ISD::GlobalBaseReg,
7409 DebugLoc(), getPointerTy()),
7412 // Lowering the machine isd will make sure everything is in the right
7414 SDValue Chain = DAG.getEntryNode();
7415 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
7416 SDValue Args[] = { Chain, Offset };
7417 Chain = DAG.getNode(X86ISD::TLSCALL, DL, NodeTys, Args, 2);
7419 // TLSCALL will be codegen'ed as call. Inform MFI that function has calls.
7420 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
7421 MFI->setAdjustsStack(true);
7423 // And our return value (tls address) is in the standard call return value
7425 unsigned Reg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
7426 return DAG.getCopyFromReg(Chain, DL, Reg, getPointerTy(),
7430 if (Subtarget->isTargetWindows()) {
7431 // Just use the implicit TLS architecture
7432 // Need to generate someting similar to:
7433 // mov rdx, qword [gs:abs 58H]; Load pointer to ThreadLocalStorage
7435 // mov ecx, dword [rel _tls_index]: Load index (from C runtime)
7436 // mov rcx, qword [rdx+rcx*8]
7437 // mov eax, .tls$:tlsvar
7438 // [rax+rcx] contains the address
7439 // Windows 64bit: gs:0x58
7440 // Windows 32bit: fs:__tls_array
7442 // If GV is an alias then use the aliasee for determining
7443 // thread-localness.
7444 if (const GlobalAlias *GA = dyn_cast<GlobalAlias>(GV))
7445 GV = GA->resolveAliasedGlobal(false);
7446 DebugLoc dl = GA->getDebugLoc();
7447 SDValue Chain = DAG.getEntryNode();
7449 // Get the Thread Pointer, which is %fs:__tls_array (32-bit) or
7450 // %gs:0x58 (64-bit).
7451 Value *Ptr = Constant::getNullValue(Subtarget->is64Bit()
7452 ? Type::getInt8PtrTy(*DAG.getContext(),
7454 : Type::getInt32PtrTy(*DAG.getContext(),
7457 SDValue ThreadPointer = DAG.getLoad(getPointerTy(), dl, Chain,
7458 Subtarget->is64Bit()
7459 ? DAG.getIntPtrConstant(0x58)
7460 : DAG.getExternalSymbol("_tls_array",
7462 MachinePointerInfo(Ptr),
7463 false, false, false, 0);
7465 // Load the _tls_index variable
7466 SDValue IDX = DAG.getExternalSymbol("_tls_index", getPointerTy());
7467 if (Subtarget->is64Bit())
7468 IDX = DAG.getExtLoad(ISD::ZEXTLOAD, dl, getPointerTy(), Chain,
7469 IDX, MachinePointerInfo(), MVT::i32,
7472 IDX = DAG.getLoad(getPointerTy(), dl, Chain, IDX, MachinePointerInfo(),
7473 false, false, false, 0);
7475 SDValue Scale = DAG.getConstant(Log2_64_Ceil(TD->getPointerSize()),
7477 IDX = DAG.getNode(ISD::SHL, dl, getPointerTy(), IDX, Scale);
7479 SDValue res = DAG.getNode(ISD::ADD, dl, getPointerTy(), ThreadPointer, IDX);
7480 res = DAG.getLoad(getPointerTy(), dl, Chain, res, MachinePointerInfo(),
7481 false, false, false, 0);
7483 // Get the offset of start of .tls section
7484 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
7485 GA->getValueType(0),
7486 GA->getOffset(), X86II::MO_SECREL);
7487 SDValue Offset = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), TGA);
7489 // The address of the thread local variable is the add of the thread
7490 // pointer with the offset of the variable.
7491 return DAG.getNode(ISD::ADD, dl, getPointerTy(), res, Offset);
7494 llvm_unreachable("TLS not implemented for this target.");
7498 /// LowerShiftParts - Lower SRA_PARTS and friends, which return two i32 values
7499 /// and take a 2 x i32 value to shift plus a shift amount.
7500 SDValue X86TargetLowering::LowerShiftParts(SDValue Op, SelectionDAG &DAG) const{
7501 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
7502 EVT VT = Op.getValueType();
7503 unsigned VTBits = VT.getSizeInBits();
7504 DebugLoc dl = Op.getDebugLoc();
7505 bool isSRA = Op.getOpcode() == ISD::SRA_PARTS;
7506 SDValue ShOpLo = Op.getOperand(0);
7507 SDValue ShOpHi = Op.getOperand(1);
7508 SDValue ShAmt = Op.getOperand(2);
7509 SDValue Tmp1 = isSRA ? DAG.getNode(ISD::SRA, dl, VT, ShOpHi,
7510 DAG.getConstant(VTBits - 1, MVT::i8))
7511 : DAG.getConstant(0, VT);
7514 if (Op.getOpcode() == ISD::SHL_PARTS) {
7515 Tmp2 = DAG.getNode(X86ISD::SHLD, dl, VT, ShOpHi, ShOpLo, ShAmt);
7516 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ShAmt);
7518 Tmp2 = DAG.getNode(X86ISD::SHRD, dl, VT, ShOpLo, ShOpHi, ShAmt);
7519 Tmp3 = DAG.getNode(isSRA ? ISD::SRA : ISD::SRL, dl, VT, ShOpHi, ShAmt);
7522 SDValue AndNode = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt,
7523 DAG.getConstant(VTBits, MVT::i8));
7524 SDValue Cond = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
7525 AndNode, DAG.getConstant(0, MVT::i8));
7528 SDValue CC = DAG.getConstant(X86::COND_NE, MVT::i8);
7529 SDValue Ops0[4] = { Tmp2, Tmp3, CC, Cond };
7530 SDValue Ops1[4] = { Tmp3, Tmp1, CC, Cond };
7532 if (Op.getOpcode() == ISD::SHL_PARTS) {
7533 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0, 4);
7534 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1, 4);
7536 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0, 4);
7537 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1, 4);
7540 SDValue Ops[2] = { Lo, Hi };
7541 return DAG.getMergeValues(Ops, 2, dl);
7544 SDValue X86TargetLowering::LowerSINT_TO_FP(SDValue Op,
7545 SelectionDAG &DAG) const {
7546 EVT SrcVT = Op.getOperand(0).getValueType();
7548 if (SrcVT.isVector())
7551 assert(SrcVT.getSimpleVT() <= MVT::i64 && SrcVT.getSimpleVT() >= MVT::i16 &&
7552 "Unknown SINT_TO_FP to lower!");
7554 // These are really Legal; return the operand so the caller accepts it as
7556 if (SrcVT == MVT::i32 && isScalarFPTypeInSSEReg(Op.getValueType()))
7558 if (SrcVT == MVT::i64 && isScalarFPTypeInSSEReg(Op.getValueType()) &&
7559 Subtarget->is64Bit()) {
7563 DebugLoc dl = Op.getDebugLoc();
7564 unsigned Size = SrcVT.getSizeInBits()/8;
7565 MachineFunction &MF = DAG.getMachineFunction();
7566 int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size, false);
7567 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
7568 SDValue Chain = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
7570 MachinePointerInfo::getFixedStack(SSFI),
7572 return BuildFILD(Op, SrcVT, Chain, StackSlot, DAG);
7575 SDValue X86TargetLowering::BuildFILD(SDValue Op, EVT SrcVT, SDValue Chain,
7577 SelectionDAG &DAG) const {
7579 DebugLoc DL = Op.getDebugLoc();
7581 bool useSSE = isScalarFPTypeInSSEReg(Op.getValueType());
7583 Tys = DAG.getVTList(MVT::f64, MVT::Other, MVT::Glue);
7585 Tys = DAG.getVTList(Op.getValueType(), MVT::Other);
7587 unsigned ByteSize = SrcVT.getSizeInBits()/8;
7589 FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(StackSlot);
7590 MachineMemOperand *MMO;
7592 int SSFI = FI->getIndex();
7594 DAG.getMachineFunction()
7595 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
7596 MachineMemOperand::MOLoad, ByteSize, ByteSize);
7598 MMO = cast<LoadSDNode>(StackSlot)->getMemOperand();
7599 StackSlot = StackSlot.getOperand(1);
7601 SDValue Ops[] = { Chain, StackSlot, DAG.getValueType(SrcVT) };
7602 SDValue Result = DAG.getMemIntrinsicNode(useSSE ? X86ISD::FILD_FLAG :
7604 Tys, Ops, array_lengthof(Ops),
7608 Chain = Result.getValue(1);
7609 SDValue InFlag = Result.getValue(2);
7611 // FIXME: Currently the FST is flagged to the FILD_FLAG. This
7612 // shouldn't be necessary except that RFP cannot be live across
7613 // multiple blocks. When stackifier is fixed, they can be uncoupled.
7614 MachineFunction &MF = DAG.getMachineFunction();
7615 unsigned SSFISize = Op.getValueType().getSizeInBits()/8;
7616 int SSFI = MF.getFrameInfo()->CreateStackObject(SSFISize, SSFISize, false);
7617 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
7618 Tys = DAG.getVTList(MVT::Other);
7620 Chain, Result, StackSlot, DAG.getValueType(Op.getValueType()), InFlag
7622 MachineMemOperand *MMO =
7623 DAG.getMachineFunction()
7624 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
7625 MachineMemOperand::MOStore, SSFISize, SSFISize);
7627 Chain = DAG.getMemIntrinsicNode(X86ISD::FST, DL, Tys,
7628 Ops, array_lengthof(Ops),
7629 Op.getValueType(), MMO);
7630 Result = DAG.getLoad(Op.getValueType(), DL, Chain, StackSlot,
7631 MachinePointerInfo::getFixedStack(SSFI),
7632 false, false, false, 0);
7638 // LowerUINT_TO_FP_i64 - 64-bit unsigned integer to double expansion.
7639 SDValue X86TargetLowering::LowerUINT_TO_FP_i64(SDValue Op,
7640 SelectionDAG &DAG) const {
7641 // This algorithm is not obvious. Here it is what we're trying to output:
7644 punpckldq (c0), %xmm0 // c0: (uint4){ 0x43300000U, 0x45300000U, 0U, 0U }
7645 subpd (c1), %xmm0 // c1: (double2){ 0x1.0p52, 0x1.0p52 * 0x1.0p32 }
7649 pshufd $0x4e, %xmm0, %xmm1
7654 DebugLoc dl = Op.getDebugLoc();
7655 LLVMContext *Context = DAG.getContext();
7657 // Build some magic constants.
7658 const uint32_t CV0[] = { 0x43300000, 0x45300000, 0, 0 };
7659 Constant *C0 = ConstantDataVector::get(*Context, CV0);
7660 SDValue CPIdx0 = DAG.getConstantPool(C0, getPointerTy(), 16);
7662 SmallVector<Constant*,2> CV1;
7664 ConstantFP::get(*Context, APFloat(APInt(64, 0x4330000000000000ULL))));
7666 ConstantFP::get(*Context, APFloat(APInt(64, 0x4530000000000000ULL))));
7667 Constant *C1 = ConstantVector::get(CV1);
7668 SDValue CPIdx1 = DAG.getConstantPool(C1, getPointerTy(), 16);
7670 // Load the 64-bit value into an XMM register.
7671 SDValue XR1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
7673 SDValue CLod0 = DAG.getLoad(MVT::v4i32, dl, DAG.getEntryNode(), CPIdx0,
7674 MachinePointerInfo::getConstantPool(),
7675 false, false, false, 16);
7676 SDValue Unpck1 = getUnpackl(DAG, dl, MVT::v4i32,
7677 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, XR1),
7680 SDValue CLod1 = DAG.getLoad(MVT::v2f64, dl, CLod0.getValue(1), CPIdx1,
7681 MachinePointerInfo::getConstantPool(),
7682 false, false, false, 16);
7683 SDValue XR2F = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Unpck1);
7684 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, XR2F, CLod1);
7687 if (Subtarget->hasSSE3()) {
7688 // FIXME: The 'haddpd' instruction may be slower than 'movhlps + addsd'.
7689 Result = DAG.getNode(X86ISD::FHADD, dl, MVT::v2f64, Sub, Sub);
7691 SDValue S2F = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Sub);
7692 SDValue Shuffle = getTargetShuffleNode(X86ISD::PSHUFD, dl, MVT::v4i32,
7694 Result = DAG.getNode(ISD::FADD, dl, MVT::v2f64,
7695 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Shuffle),
7699 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Result,
7700 DAG.getIntPtrConstant(0));
7703 // LowerUINT_TO_FP_i32 - 32-bit unsigned integer to float expansion.
7704 SDValue X86TargetLowering::LowerUINT_TO_FP_i32(SDValue Op,
7705 SelectionDAG &DAG) const {
7706 DebugLoc dl = Op.getDebugLoc();
7707 // FP constant to bias correct the final result.
7708 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL),
7711 // Load the 32-bit value into an XMM register.
7712 SDValue Load = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,
7715 // Zero out the upper parts of the register.
7716 Load = getShuffleVectorZeroOrUndef(Load, 0, true, Subtarget, DAG);
7718 Load = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
7719 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Load),
7720 DAG.getIntPtrConstant(0));
7722 // Or the load with the bias.
7723 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64,
7724 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
7725 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
7727 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
7728 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
7729 MVT::v2f64, Bias)));
7730 Or = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
7731 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Or),
7732 DAG.getIntPtrConstant(0));
7734 // Subtract the bias.
7735 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Or, Bias);
7737 // Handle final rounding.
7738 EVT DestVT = Op.getValueType();
7740 if (DestVT.bitsLT(MVT::f64))
7741 return DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub,
7742 DAG.getIntPtrConstant(0));
7743 if (DestVT.bitsGT(MVT::f64))
7744 return DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub);
7746 // Handle final rounding.
7750 SDValue X86TargetLowering::LowerUINT_TO_FP(SDValue Op,
7751 SelectionDAG &DAG) const {
7752 SDValue N0 = Op.getOperand(0);
7753 DebugLoc dl = Op.getDebugLoc();
7755 // Since UINT_TO_FP is legal (it's marked custom), dag combiner won't
7756 // optimize it to a SINT_TO_FP when the sign bit is known zero. Perform
7757 // the optimization here.
7758 if (DAG.SignBitIsZero(N0))
7759 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(), N0);
7761 EVT SrcVT = N0.getValueType();
7762 EVT DstVT = Op.getValueType();
7763 if (SrcVT == MVT::i64 && DstVT == MVT::f64 && X86ScalarSSEf64)
7764 return LowerUINT_TO_FP_i64(Op, DAG);
7765 if (SrcVT == MVT::i32 && X86ScalarSSEf64)
7766 return LowerUINT_TO_FP_i32(Op, DAG);
7767 if (Subtarget->is64Bit() && SrcVT == MVT::i64 && DstVT == MVT::f32)
7770 // Make a 64-bit buffer, and use it to build an FILD.
7771 SDValue StackSlot = DAG.CreateStackTemporary(MVT::i64);
7772 if (SrcVT == MVT::i32) {
7773 SDValue WordOff = DAG.getConstant(4, getPointerTy());
7774 SDValue OffsetSlot = DAG.getNode(ISD::ADD, dl,
7775 getPointerTy(), StackSlot, WordOff);
7776 SDValue Store1 = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
7777 StackSlot, MachinePointerInfo(),
7779 SDValue Store2 = DAG.getStore(Store1, dl, DAG.getConstant(0, MVT::i32),
7780 OffsetSlot, MachinePointerInfo(),
7782 SDValue Fild = BuildFILD(Op, MVT::i64, Store2, StackSlot, DAG);
7786 assert(SrcVT == MVT::i64 && "Unexpected type in UINT_TO_FP");
7787 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
7788 StackSlot, MachinePointerInfo(),
7790 // For i64 source, we need to add the appropriate power of 2 if the input
7791 // was negative. This is the same as the optimization in
7792 // DAGTypeLegalizer::ExpandIntOp_UNIT_TO_FP, and for it to be safe here,
7793 // we must be careful to do the computation in x87 extended precision, not
7794 // in SSE. (The generic code can't know it's OK to do this, or how to.)
7795 int SSFI = cast<FrameIndexSDNode>(StackSlot)->getIndex();
7796 MachineMemOperand *MMO =
7797 DAG.getMachineFunction()
7798 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
7799 MachineMemOperand::MOLoad, 8, 8);
7801 SDVTList Tys = DAG.getVTList(MVT::f80, MVT::Other);
7802 SDValue Ops[] = { Store, StackSlot, DAG.getValueType(MVT::i64) };
7803 SDValue Fild = DAG.getMemIntrinsicNode(X86ISD::FILD, dl, Tys, Ops, 3,
7806 APInt FF(32, 0x5F800000ULL);
7808 // Check whether the sign bit is set.
7809 SDValue SignSet = DAG.getSetCC(dl, getSetCCResultType(MVT::i64),
7810 Op.getOperand(0), DAG.getConstant(0, MVT::i64),
7813 // Build a 64 bit pair (0, FF) in the constant pool, with FF in the lo bits.
7814 SDValue FudgePtr = DAG.getConstantPool(
7815 ConstantInt::get(*DAG.getContext(), FF.zext(64)),
7818 // Get a pointer to FF if the sign bit was set, or to 0 otherwise.
7819 SDValue Zero = DAG.getIntPtrConstant(0);
7820 SDValue Four = DAG.getIntPtrConstant(4);
7821 SDValue Offset = DAG.getNode(ISD::SELECT, dl, Zero.getValueType(), SignSet,
7823 FudgePtr = DAG.getNode(ISD::ADD, dl, getPointerTy(), FudgePtr, Offset);
7825 // Load the value out, extending it from f32 to f80.
7826 // FIXME: Avoid the extend by constructing the right constant pool?
7827 SDValue Fudge = DAG.getExtLoad(ISD::EXTLOAD, dl, MVT::f80, DAG.getEntryNode(),
7828 FudgePtr, MachinePointerInfo::getConstantPool(),
7829 MVT::f32, false, false, 4);
7830 // Extend everything to 80 bits to force it to be done on x87.
7831 SDValue Add = DAG.getNode(ISD::FADD, dl, MVT::f80, Fild, Fudge);
7832 return DAG.getNode(ISD::FP_ROUND, dl, DstVT, Add, DAG.getIntPtrConstant(0));
7835 std::pair<SDValue,SDValue> X86TargetLowering::
7836 FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG, bool IsSigned, bool IsReplace) const {
7837 DebugLoc DL = Op.getDebugLoc();
7839 EVT DstTy = Op.getValueType();
7841 if (!IsSigned && !isIntegerTypeFTOL(DstTy)) {
7842 assert(DstTy == MVT::i32 && "Unexpected FP_TO_UINT");
7846 assert(DstTy.getSimpleVT() <= MVT::i64 &&
7847 DstTy.getSimpleVT() >= MVT::i16 &&
7848 "Unknown FP_TO_INT to lower!");
7850 // These are really Legal.
7851 if (DstTy == MVT::i32 &&
7852 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
7853 return std::make_pair(SDValue(), SDValue());
7854 if (Subtarget->is64Bit() &&
7855 DstTy == MVT::i64 &&
7856 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
7857 return std::make_pair(SDValue(), SDValue());
7859 // We lower FP->int64 either into FISTP64 followed by a load from a temporary
7860 // stack slot, or into the FTOL runtime function.
7861 MachineFunction &MF = DAG.getMachineFunction();
7862 unsigned MemSize = DstTy.getSizeInBits()/8;
7863 int SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
7864 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
7867 if (!IsSigned && isIntegerTypeFTOL(DstTy))
7868 Opc = X86ISD::WIN_FTOL;
7870 switch (DstTy.getSimpleVT().SimpleTy) {
7871 default: llvm_unreachable("Invalid FP_TO_SINT to lower!");
7872 case MVT::i16: Opc = X86ISD::FP_TO_INT16_IN_MEM; break;
7873 case MVT::i32: Opc = X86ISD::FP_TO_INT32_IN_MEM; break;
7874 case MVT::i64: Opc = X86ISD::FP_TO_INT64_IN_MEM; break;
7877 SDValue Chain = DAG.getEntryNode();
7878 SDValue Value = Op.getOperand(0);
7879 EVT TheVT = Op.getOperand(0).getValueType();
7880 // FIXME This causes a redundant load/store if the SSE-class value is already
7881 // in memory, such as if it is on the callstack.
7882 if (isScalarFPTypeInSSEReg(TheVT)) {
7883 assert(DstTy == MVT::i64 && "Invalid FP_TO_SINT to lower!");
7884 Chain = DAG.getStore(Chain, DL, Value, StackSlot,
7885 MachinePointerInfo::getFixedStack(SSFI),
7887 SDVTList Tys = DAG.getVTList(Op.getOperand(0).getValueType(), MVT::Other);
7889 Chain, StackSlot, DAG.getValueType(TheVT)
7892 MachineMemOperand *MMO =
7893 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
7894 MachineMemOperand::MOLoad, MemSize, MemSize);
7895 Value = DAG.getMemIntrinsicNode(X86ISD::FLD, DL, Tys, Ops, 3,
7897 Chain = Value.getValue(1);
7898 SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
7899 StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
7902 MachineMemOperand *MMO =
7903 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
7904 MachineMemOperand::MOStore, MemSize, MemSize);
7906 if (Opc != X86ISD::WIN_FTOL) {
7907 // Build the FP_TO_INT*_IN_MEM
7908 SDValue Ops[] = { Chain, Value, StackSlot };
7909 SDValue FIST = DAG.getMemIntrinsicNode(Opc, DL, DAG.getVTList(MVT::Other),
7910 Ops, 3, DstTy, MMO);
7911 return std::make_pair(FIST, StackSlot);
7913 SDValue ftol = DAG.getNode(X86ISD::WIN_FTOL, DL,
7914 DAG.getVTList(MVT::Other, MVT::Glue),
7916 SDValue eax = DAG.getCopyFromReg(ftol, DL, X86::EAX,
7917 MVT::i32, ftol.getValue(1));
7918 SDValue edx = DAG.getCopyFromReg(eax.getValue(1), DL, X86::EDX,
7919 MVT::i32, eax.getValue(2));
7920 SDValue Ops[] = { eax, edx };
7921 SDValue pair = IsReplace
7922 ? DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops, 2)
7923 : DAG.getMergeValues(Ops, 2, DL);
7924 return std::make_pair(pair, SDValue());
7928 SDValue X86TargetLowering::LowerFP_TO_SINT(SDValue Op,
7929 SelectionDAG &DAG) const {
7930 if (Op.getValueType().isVector())
7933 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG,
7934 /*IsSigned=*/ true, /*IsReplace=*/ false);
7935 SDValue FIST = Vals.first, StackSlot = Vals.second;
7936 // If FP_TO_INTHelper failed, the node is actually supposed to be Legal.
7937 if (FIST.getNode() == 0) return Op;
7939 if (StackSlot.getNode())
7941 return DAG.getLoad(Op.getValueType(), Op.getDebugLoc(),
7942 FIST, StackSlot, MachinePointerInfo(),
7943 false, false, false, 0);
7945 // The node is the result.
7949 SDValue X86TargetLowering::LowerFP_TO_UINT(SDValue Op,
7950 SelectionDAG &DAG) const {
7951 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG,
7952 /*IsSigned=*/ false, /*IsReplace=*/ false);
7953 SDValue FIST = Vals.first, StackSlot = Vals.second;
7954 assert(FIST.getNode() && "Unexpected failure");
7956 if (StackSlot.getNode())
7958 return DAG.getLoad(Op.getValueType(), Op.getDebugLoc(),
7959 FIST, StackSlot, MachinePointerInfo(),
7960 false, false, false, 0);
7962 // The node is the result.
7966 SDValue X86TargetLowering::LowerFABS(SDValue Op,
7967 SelectionDAG &DAG) const {
7968 LLVMContext *Context = DAG.getContext();
7969 DebugLoc dl = Op.getDebugLoc();
7970 EVT VT = Op.getValueType();
7973 EltVT = VT.getVectorElementType();
7975 if (EltVT == MVT::f64) {
7976 C = ConstantVector::getSplat(2,
7977 ConstantFP::get(*Context, APFloat(APInt(64, ~(1ULL << 63)))));
7979 C = ConstantVector::getSplat(4,
7980 ConstantFP::get(*Context, APFloat(APInt(32, ~(1U << 31)))));
7982 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
7983 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
7984 MachinePointerInfo::getConstantPool(),
7985 false, false, false, 16);
7986 return DAG.getNode(X86ISD::FAND, dl, VT, Op.getOperand(0), Mask);
7989 SDValue X86TargetLowering::LowerFNEG(SDValue Op, SelectionDAG &DAG) const {
7990 LLVMContext *Context = DAG.getContext();
7991 DebugLoc dl = Op.getDebugLoc();
7992 EVT VT = Op.getValueType();
7994 unsigned NumElts = VT == MVT::f64 ? 2 : 4;
7995 if (VT.isVector()) {
7996 EltVT = VT.getVectorElementType();
7997 NumElts = VT.getVectorNumElements();
8000 if (EltVT == MVT::f64)
8001 C = ConstantFP::get(*Context, APFloat(APInt(64, 1ULL << 63)));
8003 C = ConstantFP::get(*Context, APFloat(APInt(32, 1U << 31)));
8004 C = ConstantVector::getSplat(NumElts, C);
8005 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
8006 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
8007 MachinePointerInfo::getConstantPool(),
8008 false, false, false, 16);
8009 if (VT.isVector()) {
8010 MVT XORVT = VT.getSizeInBits() == 128 ? MVT::v2i64 : MVT::v4i64;
8011 return DAG.getNode(ISD::BITCAST, dl, VT,
8012 DAG.getNode(ISD::XOR, dl, XORVT,
8013 DAG.getNode(ISD::BITCAST, dl, XORVT,
8015 DAG.getNode(ISD::BITCAST, dl, XORVT, Mask)));
8018 return DAG.getNode(X86ISD::FXOR, dl, VT, Op.getOperand(0), Mask);
8021 SDValue X86TargetLowering::LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const {
8022 LLVMContext *Context = DAG.getContext();
8023 SDValue Op0 = Op.getOperand(0);
8024 SDValue Op1 = Op.getOperand(1);
8025 DebugLoc dl = Op.getDebugLoc();
8026 EVT VT = Op.getValueType();
8027 EVT SrcVT = Op1.getValueType();
8029 // If second operand is smaller, extend it first.
8030 if (SrcVT.bitsLT(VT)) {
8031 Op1 = DAG.getNode(ISD::FP_EXTEND, dl, VT, Op1);
8034 // And if it is bigger, shrink it first.
8035 if (SrcVT.bitsGT(VT)) {
8036 Op1 = DAG.getNode(ISD::FP_ROUND, dl, VT, Op1, DAG.getIntPtrConstant(1));
8040 // At this point the operands and the result should have the same
8041 // type, and that won't be f80 since that is not custom lowered.
8043 // First get the sign bit of second operand.
8044 SmallVector<Constant*,4> CV;
8045 if (SrcVT == MVT::f64) {
8046 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, 1ULL << 63))));
8047 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, 0))));
8049 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 1U << 31))));
8050 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
8051 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
8052 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
8054 Constant *C = ConstantVector::get(CV);
8055 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
8056 SDValue Mask1 = DAG.getLoad(SrcVT, dl, DAG.getEntryNode(), CPIdx,
8057 MachinePointerInfo::getConstantPool(),
8058 false, false, false, 16);
8059 SDValue SignBit = DAG.getNode(X86ISD::FAND, dl, SrcVT, Op1, Mask1);
8061 // Shift sign bit right or left if the two operands have different types.
8062 if (SrcVT.bitsGT(VT)) {
8063 // Op0 is MVT::f32, Op1 is MVT::f64.
8064 SignBit = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f64, SignBit);
8065 SignBit = DAG.getNode(X86ISD::FSRL, dl, MVT::v2f64, SignBit,
8066 DAG.getConstant(32, MVT::i32));
8067 SignBit = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, SignBit);
8068 SignBit = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f32, SignBit,
8069 DAG.getIntPtrConstant(0));
8072 // Clear first operand sign bit.
8074 if (VT == MVT::f64) {
8075 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, ~(1ULL << 63)))));
8076 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, 0))));
8078 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, ~(1U << 31)))));
8079 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
8080 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
8081 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
8083 C = ConstantVector::get(CV);
8084 CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
8085 SDValue Mask2 = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
8086 MachinePointerInfo::getConstantPool(),
8087 false, false, false, 16);
8088 SDValue Val = DAG.getNode(X86ISD::FAND, dl, VT, Op0, Mask2);
8090 // Or the value with the sign bit.
8091 return DAG.getNode(X86ISD::FOR, dl, VT, Val, SignBit);
8094 SDValue X86TargetLowering::LowerFGETSIGN(SDValue Op, SelectionDAG &DAG) const {
8095 SDValue N0 = Op.getOperand(0);
8096 DebugLoc dl = Op.getDebugLoc();
8097 EVT VT = Op.getValueType();
8099 // Lower ISD::FGETSIGN to (AND (X86ISD::FGETSIGNx86 ...) 1).
8100 SDValue xFGETSIGN = DAG.getNode(X86ISD::FGETSIGNx86, dl, VT, N0,
8101 DAG.getConstant(1, VT));
8102 return DAG.getNode(ISD::AND, dl, VT, xFGETSIGN, DAG.getConstant(1, VT));
8105 /// Emit nodes that will be selected as "test Op0,Op0", or something
8107 SDValue X86TargetLowering::EmitTest(SDValue Op, unsigned X86CC,
8108 SelectionDAG &DAG) const {
8109 DebugLoc dl = Op.getDebugLoc();
8111 // CF and OF aren't always set the way we want. Determine which
8112 // of these we need.
8113 bool NeedCF = false;
8114 bool NeedOF = false;
8117 case X86::COND_A: case X86::COND_AE:
8118 case X86::COND_B: case X86::COND_BE:
8121 case X86::COND_G: case X86::COND_GE:
8122 case X86::COND_L: case X86::COND_LE:
8123 case X86::COND_O: case X86::COND_NO:
8128 // See if we can use the EFLAGS value from the operand instead of
8129 // doing a separate TEST. TEST always sets OF and CF to 0, so unless
8130 // we prove that the arithmetic won't overflow, we can't use OF or CF.
8131 if (Op.getResNo() != 0 || NeedOF || NeedCF)
8132 // Emit a CMP with 0, which is the TEST pattern.
8133 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
8134 DAG.getConstant(0, Op.getValueType()));
8136 unsigned Opcode = 0;
8137 unsigned NumOperands = 0;
8138 switch (Op.getNode()->getOpcode()) {
8140 // Due to an isel shortcoming, be conservative if this add is likely to be
8141 // selected as part of a load-modify-store instruction. When the root node
8142 // in a match is a store, isel doesn't know how to remap non-chain non-flag
8143 // uses of other nodes in the match, such as the ADD in this case. This
8144 // leads to the ADD being left around and reselected, with the result being
8145 // two adds in the output. Alas, even if none our users are stores, that
8146 // doesn't prove we're O.K. Ergo, if we have any parents that aren't
8147 // CopyToReg or SETCC, eschew INC/DEC. A better fix seems to require
8148 // climbing the DAG back to the root, and it doesn't seem to be worth the
8150 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
8151 UE = Op.getNode()->use_end(); UI != UE; ++UI)
8152 if (UI->getOpcode() != ISD::CopyToReg &&
8153 UI->getOpcode() != ISD::SETCC &&
8154 UI->getOpcode() != ISD::STORE)
8157 if (ConstantSDNode *C =
8158 dyn_cast<ConstantSDNode>(Op.getNode()->getOperand(1))) {
8159 // An add of one will be selected as an INC.
8160 if (C->getAPIntValue() == 1) {
8161 Opcode = X86ISD::INC;
8166 // An add of negative one (subtract of one) will be selected as a DEC.
8167 if (C->getAPIntValue().isAllOnesValue()) {
8168 Opcode = X86ISD::DEC;
8174 // Otherwise use a regular EFLAGS-setting add.
8175 Opcode = X86ISD::ADD;
8179 // If the primary and result isn't used, don't bother using X86ISD::AND,
8180 // because a TEST instruction will be better.
8181 bool NonFlagUse = false;
8182 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
8183 UE = Op.getNode()->use_end(); UI != UE; ++UI) {
8185 unsigned UOpNo = UI.getOperandNo();
8186 if (User->getOpcode() == ISD::TRUNCATE && User->hasOneUse()) {
8187 // Look pass truncate.
8188 UOpNo = User->use_begin().getOperandNo();
8189 User = *User->use_begin();
8192 if (User->getOpcode() != ISD::BRCOND &&
8193 User->getOpcode() != ISD::SETCC &&
8194 (User->getOpcode() != ISD::SELECT || UOpNo != 0)) {
8207 // Due to the ISEL shortcoming noted above, be conservative if this op is
8208 // likely to be selected as part of a load-modify-store instruction.
8209 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
8210 UE = Op.getNode()->use_end(); UI != UE; ++UI)
8211 if (UI->getOpcode() == ISD::STORE)
8214 // Otherwise use a regular EFLAGS-setting instruction.
8215 switch (Op.getNode()->getOpcode()) {
8216 default: llvm_unreachable("unexpected operator!");
8217 case ISD::SUB: Opcode = X86ISD::SUB; break;
8218 case ISD::OR: Opcode = X86ISD::OR; break;
8219 case ISD::XOR: Opcode = X86ISD::XOR; break;
8220 case ISD::AND: Opcode = X86ISD::AND; break;
8232 return SDValue(Op.getNode(), 1);
8239 // Emit a CMP with 0, which is the TEST pattern.
8240 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
8241 DAG.getConstant(0, Op.getValueType()));
8243 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
8244 SmallVector<SDValue, 4> Ops;
8245 for (unsigned i = 0; i != NumOperands; ++i)
8246 Ops.push_back(Op.getOperand(i));
8248 SDValue New = DAG.getNode(Opcode, dl, VTs, &Ops[0], NumOperands);
8249 DAG.ReplaceAllUsesWith(Op, New);
8250 return SDValue(New.getNode(), 1);
8253 /// Emit nodes that will be selected as "cmp Op0,Op1", or something
8255 SDValue X86TargetLowering::EmitCmp(SDValue Op0, SDValue Op1, unsigned X86CC,
8256 SelectionDAG &DAG) const {
8257 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op1))
8258 if (C->getAPIntValue() == 0)
8259 return EmitTest(Op0, X86CC, DAG);
8261 DebugLoc dl = Op0.getDebugLoc();
8262 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op0, Op1);
8265 /// Convert a comparison if required by the subtarget.
8266 SDValue X86TargetLowering::ConvertCmpIfNecessary(SDValue Cmp,
8267 SelectionDAG &DAG) const {
8268 // If the subtarget does not support the FUCOMI instruction, floating-point
8269 // comparisons have to be converted.
8270 if (Subtarget->hasCMov() ||
8271 Cmp.getOpcode() != X86ISD::CMP ||
8272 !Cmp.getOperand(0).getValueType().isFloatingPoint() ||
8273 !Cmp.getOperand(1).getValueType().isFloatingPoint())
8276 // The instruction selector will select an FUCOM instruction instead of
8277 // FUCOMI, which writes the comparison result to FPSW instead of EFLAGS. Hence
8278 // build an SDNode sequence that transfers the result from FPSW into EFLAGS:
8279 // (X86sahf (trunc (srl (X86fp_stsw (trunc (X86cmp ...)), 8))))
8280 DebugLoc dl = Cmp.getDebugLoc();
8281 SDValue TruncFPSW = DAG.getNode(ISD::TRUNCATE, dl, MVT::i16, Cmp);
8282 SDValue FNStSW = DAG.getNode(X86ISD::FNSTSW16r, dl, MVT::i16, TruncFPSW);
8283 SDValue Srl = DAG.getNode(ISD::SRL, dl, MVT::i16, FNStSW,
8284 DAG.getConstant(8, MVT::i8));
8285 SDValue TruncSrl = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Srl);
8286 return DAG.getNode(X86ISD::SAHF, dl, MVT::i32, TruncSrl);
8289 /// LowerToBT - Result of 'and' is compared against zero. Turn it into a BT node
8290 /// if it's possible.
8291 SDValue X86TargetLowering::LowerToBT(SDValue And, ISD::CondCode CC,
8292 DebugLoc dl, SelectionDAG &DAG) const {
8293 SDValue Op0 = And.getOperand(0);
8294 SDValue Op1 = And.getOperand(1);
8295 if (Op0.getOpcode() == ISD::TRUNCATE)
8296 Op0 = Op0.getOperand(0);
8297 if (Op1.getOpcode() == ISD::TRUNCATE)
8298 Op1 = Op1.getOperand(0);
8301 if (Op1.getOpcode() == ISD::SHL)
8302 std::swap(Op0, Op1);
8303 if (Op0.getOpcode() == ISD::SHL) {
8304 if (ConstantSDNode *And00C = dyn_cast<ConstantSDNode>(Op0.getOperand(0)))
8305 if (And00C->getZExtValue() == 1) {
8306 // If we looked past a truncate, check that it's only truncating away
8308 unsigned BitWidth = Op0.getValueSizeInBits();
8309 unsigned AndBitWidth = And.getValueSizeInBits();
8310 if (BitWidth > AndBitWidth) {
8312 DAG.ComputeMaskedBits(Op0, Zeros, Ones);
8313 if (Zeros.countLeadingOnes() < BitWidth - AndBitWidth)
8317 RHS = Op0.getOperand(1);
8319 } else if (Op1.getOpcode() == ISD::Constant) {
8320 ConstantSDNode *AndRHS = cast<ConstantSDNode>(Op1);
8321 uint64_t AndRHSVal = AndRHS->getZExtValue();
8322 SDValue AndLHS = Op0;
8324 if (AndRHSVal == 1 && AndLHS.getOpcode() == ISD::SRL) {
8325 LHS = AndLHS.getOperand(0);
8326 RHS = AndLHS.getOperand(1);
8329 // Use BT if the immediate can't be encoded in a TEST instruction.
8330 if (!isUInt<32>(AndRHSVal) && isPowerOf2_64(AndRHSVal)) {
8332 RHS = DAG.getConstant(Log2_64_Ceil(AndRHSVal), LHS.getValueType());
8336 if (LHS.getNode()) {
8337 // If LHS is i8, promote it to i32 with any_extend. There is no i8 BT
8338 // instruction. Since the shift amount is in-range-or-undefined, we know
8339 // that doing a bittest on the i32 value is ok. We extend to i32 because
8340 // the encoding for the i16 version is larger than the i32 version.
8341 // Also promote i16 to i32 for performance / code size reason.
8342 if (LHS.getValueType() == MVT::i8 ||
8343 LHS.getValueType() == MVT::i16)
8344 LHS = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, LHS);
8346 // If the operand types disagree, extend the shift amount to match. Since
8347 // BT ignores high bits (like shifts) we can use anyextend.
8348 if (LHS.getValueType() != RHS.getValueType())
8349 RHS = DAG.getNode(ISD::ANY_EXTEND, dl, LHS.getValueType(), RHS);
8351 SDValue BT = DAG.getNode(X86ISD::BT, dl, MVT::i32, LHS, RHS);
8352 unsigned Cond = CC == ISD::SETEQ ? X86::COND_AE : X86::COND_B;
8353 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
8354 DAG.getConstant(Cond, MVT::i8), BT);
8360 SDValue X86TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
8362 if (Op.getValueType().isVector()) return LowerVSETCC(Op, DAG);
8364 assert(Op.getValueType() == MVT::i8 && "SetCC type must be 8-bit integer");
8365 SDValue Op0 = Op.getOperand(0);
8366 SDValue Op1 = Op.getOperand(1);
8367 DebugLoc dl = Op.getDebugLoc();
8368 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
8370 // Optimize to BT if possible.
8371 // Lower (X & (1 << N)) == 0 to BT(X, N).
8372 // Lower ((X >>u N) & 1) != 0 to BT(X, N).
8373 // Lower ((X >>s N) & 1) != 0 to BT(X, N).
8374 if (Op0.getOpcode() == ISD::AND && Op0.hasOneUse() &&
8375 Op1.getOpcode() == ISD::Constant &&
8376 cast<ConstantSDNode>(Op1)->isNullValue() &&
8377 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
8378 SDValue NewSetCC = LowerToBT(Op0, CC, dl, DAG);
8379 if (NewSetCC.getNode())
8383 // Look for X == 0, X == 1, X != 0, or X != 1. We can simplify some forms of
8385 if (Op1.getOpcode() == ISD::Constant &&
8386 (cast<ConstantSDNode>(Op1)->getZExtValue() == 1 ||
8387 cast<ConstantSDNode>(Op1)->isNullValue()) &&
8388 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
8390 // If the input is a setcc, then reuse the input setcc or use a new one with
8391 // the inverted condition.
8392 if (Op0.getOpcode() == X86ISD::SETCC) {
8393 X86::CondCode CCode = (X86::CondCode)Op0.getConstantOperandVal(0);
8394 bool Invert = (CC == ISD::SETNE) ^
8395 cast<ConstantSDNode>(Op1)->isNullValue();
8396 if (!Invert) return Op0;
8398 CCode = X86::GetOppositeBranchCondition(CCode);
8399 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
8400 DAG.getConstant(CCode, MVT::i8), Op0.getOperand(1));
8404 bool isFP = Op1.getValueType().isFloatingPoint();
8405 unsigned X86CC = TranslateX86CC(CC, isFP, Op0, Op1, DAG);
8406 if (X86CC == X86::COND_INVALID)
8409 SDValue EFLAGS = EmitCmp(Op0, Op1, X86CC, DAG);
8410 EFLAGS = ConvertCmpIfNecessary(EFLAGS, DAG);
8411 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
8412 DAG.getConstant(X86CC, MVT::i8), EFLAGS);
8415 // Lower256IntVSETCC - Break a VSETCC 256-bit integer VSETCC into two new 128
8416 // ones, and then concatenate the result back.
8417 static SDValue Lower256IntVSETCC(SDValue Op, SelectionDAG &DAG) {
8418 EVT VT = Op.getValueType();
8420 assert(VT.getSizeInBits() == 256 && Op.getOpcode() == ISD::SETCC &&
8421 "Unsupported value type for operation");
8423 unsigned NumElems = VT.getVectorNumElements();
8424 DebugLoc dl = Op.getDebugLoc();
8425 SDValue CC = Op.getOperand(2);
8427 // Extract the LHS vectors
8428 SDValue LHS = Op.getOperand(0);
8429 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
8430 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
8432 // Extract the RHS vectors
8433 SDValue RHS = Op.getOperand(1);
8434 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, dl);
8435 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, dl);
8437 // Issue the operation on the smaller types and concatenate the result back
8438 MVT EltVT = VT.getVectorElementType().getSimpleVT();
8439 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
8440 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
8441 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1, CC),
8442 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2, CC));
8446 SDValue X86TargetLowering::LowerVSETCC(SDValue Op, SelectionDAG &DAG) const {
8448 SDValue Op0 = Op.getOperand(0);
8449 SDValue Op1 = Op.getOperand(1);
8450 SDValue CC = Op.getOperand(2);
8451 EVT VT = Op.getValueType();
8452 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
8453 bool isFP = Op.getOperand(1).getValueType().isFloatingPoint();
8454 DebugLoc dl = Op.getDebugLoc();
8458 EVT EltVT = Op0.getValueType().getVectorElementType();
8459 assert(EltVT == MVT::f32 || EltVT == MVT::f64); (void)EltVT;
8463 // SSE Condition code mapping:
8472 switch (SetCCOpcode) {
8475 case ISD::SETEQ: SSECC = 0; break;
8477 case ISD::SETGT: Swap = true; // Fallthrough
8479 case ISD::SETOLT: SSECC = 1; break;
8481 case ISD::SETGE: Swap = true; // Fallthrough
8483 case ISD::SETOLE: SSECC = 2; break;
8484 case ISD::SETUO: SSECC = 3; break;
8486 case ISD::SETNE: SSECC = 4; break;
8487 case ISD::SETULE: Swap = true;
8488 case ISD::SETUGE: SSECC = 5; break;
8489 case ISD::SETULT: Swap = true;
8490 case ISD::SETUGT: SSECC = 6; break;
8491 case ISD::SETO: SSECC = 7; break;
8494 std::swap(Op0, Op1);
8496 // In the two special cases we can't handle, emit two comparisons.
8498 if (SetCCOpcode == ISD::SETUEQ) {
8500 UNORD = DAG.getNode(X86ISD::CMPP, dl, VT, Op0, Op1,
8501 DAG.getConstant(3, MVT::i8));
8502 EQ = DAG.getNode(X86ISD::CMPP, dl, VT, Op0, Op1,
8503 DAG.getConstant(0, MVT::i8));
8504 return DAG.getNode(ISD::OR, dl, VT, UNORD, EQ);
8506 if (SetCCOpcode == ISD::SETONE) {
8508 ORD = DAG.getNode(X86ISD::CMPP, dl, VT, Op0, Op1,
8509 DAG.getConstant(7, MVT::i8));
8510 NEQ = DAG.getNode(X86ISD::CMPP, dl, VT, Op0, Op1,
8511 DAG.getConstant(4, MVT::i8));
8512 return DAG.getNode(ISD::AND, dl, VT, ORD, NEQ);
8514 llvm_unreachable("Illegal FP comparison");
8516 // Handle all other FP comparisons here.
8517 return DAG.getNode(X86ISD::CMPP, dl, VT, Op0, Op1,
8518 DAG.getConstant(SSECC, MVT::i8));
8521 // Break 256-bit integer vector compare into smaller ones.
8522 if (VT.getSizeInBits() == 256 && !Subtarget->hasAVX2())
8523 return Lower256IntVSETCC(Op, DAG);
8525 // We are handling one of the integer comparisons here. Since SSE only has
8526 // GT and EQ comparisons for integer, swapping operands and multiple
8527 // operations may be required for some comparisons.
8529 bool Swap = false, Invert = false, FlipSigns = false;
8531 switch (SetCCOpcode) {
8533 case ISD::SETNE: Invert = true;
8534 case ISD::SETEQ: Opc = X86ISD::PCMPEQ; break;
8535 case ISD::SETLT: Swap = true;
8536 case ISD::SETGT: Opc = X86ISD::PCMPGT; break;
8537 case ISD::SETGE: Swap = true;
8538 case ISD::SETLE: Opc = X86ISD::PCMPGT; Invert = true; break;
8539 case ISD::SETULT: Swap = true;
8540 case ISD::SETUGT: Opc = X86ISD::PCMPGT; FlipSigns = true; break;
8541 case ISD::SETUGE: Swap = true;
8542 case ISD::SETULE: Opc = X86ISD::PCMPGT; FlipSigns = true; Invert = true; break;
8545 std::swap(Op0, Op1);
8547 // Check that the operation in question is available (most are plain SSE2,
8548 // but PCMPGTQ and PCMPEQQ have different requirements).
8549 if (Opc == X86ISD::PCMPGT && VT == MVT::v2i64 && !Subtarget->hasSSE42())
8551 if (Opc == X86ISD::PCMPEQ && VT == MVT::v2i64 && !Subtarget->hasSSE41())
8554 // Since SSE has no unsigned integer comparisons, we need to flip the sign
8555 // bits of the inputs before performing those operations.
8557 EVT EltVT = VT.getVectorElementType();
8558 SDValue SignBit = DAG.getConstant(APInt::getSignBit(EltVT.getSizeInBits()),
8560 std::vector<SDValue> SignBits(VT.getVectorNumElements(), SignBit);
8561 SDValue SignVec = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &SignBits[0],
8563 Op0 = DAG.getNode(ISD::XOR, dl, VT, Op0, SignVec);
8564 Op1 = DAG.getNode(ISD::XOR, dl, VT, Op1, SignVec);
8567 SDValue Result = DAG.getNode(Opc, dl, VT, Op0, Op1);
8569 // If the logical-not of the result is required, perform that now.
8571 Result = DAG.getNOT(dl, Result, VT);
8576 // isX86LogicalCmp - Return true if opcode is a X86 logical comparison.
8577 static bool isX86LogicalCmp(SDValue Op) {
8578 unsigned Opc = Op.getNode()->getOpcode();
8579 if (Opc == X86ISD::CMP || Opc == X86ISD::COMI || Opc == X86ISD::UCOMI ||
8580 Opc == X86ISD::SAHF)
8582 if (Op.getResNo() == 1 &&
8583 (Opc == X86ISD::ADD ||
8584 Opc == X86ISD::SUB ||
8585 Opc == X86ISD::ADC ||
8586 Opc == X86ISD::SBB ||
8587 Opc == X86ISD::SMUL ||
8588 Opc == X86ISD::UMUL ||
8589 Opc == X86ISD::INC ||
8590 Opc == X86ISD::DEC ||
8591 Opc == X86ISD::OR ||
8592 Opc == X86ISD::XOR ||
8593 Opc == X86ISD::AND))
8596 if (Op.getResNo() == 2 && Opc == X86ISD::UMUL)
8602 static bool isZero(SDValue V) {
8603 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V);
8604 return C && C->isNullValue();
8607 static bool isAllOnes(SDValue V) {
8608 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V);
8609 return C && C->isAllOnesValue();
8612 SDValue X86TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {
8613 bool addTest = true;
8614 SDValue Cond = Op.getOperand(0);
8615 SDValue Op1 = Op.getOperand(1);
8616 SDValue Op2 = Op.getOperand(2);
8617 DebugLoc DL = Op.getDebugLoc();
8620 if (Cond.getOpcode() == ISD::SETCC) {
8621 SDValue NewCond = LowerSETCC(Cond, DAG);
8622 if (NewCond.getNode())
8626 // Handle the following cases related to max and min:
8627 // (a > b) ? (a-b) : 0
8628 // (a >= b) ? (a-b) : 0
8629 // (b < a) ? (a-b) : 0
8630 // (b <= a) ? (a-b) : 0
8631 // Comparison is removed to use EFLAGS from SUB.
8632 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op2))
8633 if (Cond.getOpcode() == X86ISD::SETCC &&
8634 Cond.getOperand(1).getOpcode() == X86ISD::CMP &&
8635 (Op1.getOpcode() == ISD::SUB || Op1.getOpcode() == X86ISD::SUB) &&
8636 C->getAPIntValue() == 0) {
8637 SDValue Cmp = Cond.getOperand(1);
8638 unsigned CC = cast<ConstantSDNode>(Cond.getOperand(0))->getZExtValue();
8639 if ((DAG.isEqualTo(Op1.getOperand(0), Cmp.getOperand(0)) &&
8640 DAG.isEqualTo(Op1.getOperand(1), Cmp.getOperand(1)) &&
8641 (CC == X86::COND_G || CC == X86::COND_GE ||
8642 CC == X86::COND_A || CC == X86::COND_AE)) ||
8643 (DAG.isEqualTo(Op1.getOperand(0), Cmp.getOperand(1)) &&
8644 DAG.isEqualTo(Op1.getOperand(1), Cmp.getOperand(0)) &&
8645 (CC == X86::COND_L || CC == X86::COND_LE ||
8646 CC == X86::COND_B || CC == X86::COND_BE))) {
8648 if (Op1.getOpcode() == ISD::SUB) {
8649 SDVTList VTs = DAG.getVTList(Op1.getValueType(), MVT::i32);
8650 SDValue New = DAG.getNode(X86ISD::SUB, DL, VTs,
8651 Op1.getOperand(0), Op1.getOperand(1));
8652 DAG.ReplaceAllUsesWith(Op1, New);
8656 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue);
8657 unsigned NewCC = (CC == X86::COND_G || CC == X86::COND_GE ||
8658 CC == X86::COND_L ||
8659 CC == X86::COND_LE) ? X86::COND_GE : X86::COND_AE;
8660 SDValue Ops[] = { Op2, Op1, DAG.getConstant(NewCC, MVT::i8),
8661 SDValue(Op1.getNode(), 1) };
8662 return DAG.getNode(X86ISD::CMOV, DL, VTs, Ops, array_lengthof(Ops));
8666 // (select (x == 0), -1, y) -> (sign_bit (x - 1)) | y
8667 // (select (x == 0), y, -1) -> ~(sign_bit (x - 1)) | y
8668 // (select (x != 0), y, -1) -> (sign_bit (x - 1)) | y
8669 // (select (x != 0), -1, y) -> ~(sign_bit (x - 1)) | y
8670 if (Cond.getOpcode() == X86ISD::SETCC &&
8671 Cond.getOperand(1).getOpcode() == X86ISD::CMP &&
8672 isZero(Cond.getOperand(1).getOperand(1))) {
8673 SDValue Cmp = Cond.getOperand(1);
8675 unsigned CondCode =cast<ConstantSDNode>(Cond.getOperand(0))->getZExtValue();
8677 if ((isAllOnes(Op1) || isAllOnes(Op2)) &&
8678 (CondCode == X86::COND_E || CondCode == X86::COND_NE)) {
8679 SDValue Y = isAllOnes(Op2) ? Op1 : Op2;
8681 SDValue CmpOp0 = Cmp.getOperand(0);
8682 // Apply further optimizations for special cases
8683 // (select (x != 0), -1, 0) -> neg & sbb
8684 // (select (x == 0), 0, -1) -> neg & sbb
8685 if (ConstantSDNode *YC = dyn_cast<ConstantSDNode>(Y))
8686 if (YC->isNullValue() &&
8687 (isAllOnes(Op1) == (CondCode == X86::COND_NE))) {
8688 SDVTList VTs = DAG.getVTList(CmpOp0.getValueType(), MVT::i32);
8689 SDValue Neg = DAG.getNode(X86ISD::SUB, DL, VTs,
8690 DAG.getConstant(0, CmpOp0.getValueType()),
8692 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
8693 DAG.getConstant(X86::COND_B, MVT::i8),
8694 SDValue(Neg.getNode(), 1));
8698 Cmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32,
8699 CmpOp0, DAG.getConstant(1, CmpOp0.getValueType()));
8700 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
8702 SDValue Res = // Res = 0 or -1.
8703 DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
8704 DAG.getConstant(X86::COND_B, MVT::i8), Cmp);
8706 if (isAllOnes(Op1) != (CondCode == X86::COND_E))
8707 Res = DAG.getNOT(DL, Res, Res.getValueType());
8709 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(Op2);
8710 if (N2C == 0 || !N2C->isNullValue())
8711 Res = DAG.getNode(ISD::OR, DL, Res.getValueType(), Res, Y);
8716 // Look past (and (setcc_carry (cmp ...)), 1).
8717 if (Cond.getOpcode() == ISD::AND &&
8718 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
8719 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
8720 if (C && C->getAPIntValue() == 1)
8721 Cond = Cond.getOperand(0);
8724 // If condition flag is set by a X86ISD::CMP, then use it as the condition
8725 // setting operand in place of the X86ISD::SETCC.
8726 unsigned CondOpcode = Cond.getOpcode();
8727 if (CondOpcode == X86ISD::SETCC ||
8728 CondOpcode == X86ISD::SETCC_CARRY) {
8729 CC = Cond.getOperand(0);
8731 SDValue Cmp = Cond.getOperand(1);
8732 unsigned Opc = Cmp.getOpcode();
8733 EVT VT = Op.getValueType();
8735 bool IllegalFPCMov = false;
8736 if (VT.isFloatingPoint() && !VT.isVector() &&
8737 !isScalarFPTypeInSSEReg(VT)) // FPStack?
8738 IllegalFPCMov = !hasFPCMov(cast<ConstantSDNode>(CC)->getSExtValue());
8740 if ((isX86LogicalCmp(Cmp) && !IllegalFPCMov) ||
8741 Opc == X86ISD::BT) { // FIXME
8745 } else if (CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO ||
8746 CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO ||
8747 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) &&
8748 Cond.getOperand(0).getValueType() != MVT::i8)) {
8749 SDValue LHS = Cond.getOperand(0);
8750 SDValue RHS = Cond.getOperand(1);
8754 switch (CondOpcode) {
8755 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break;
8756 case ISD::SADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break;
8757 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break;
8758 case ISD::SSUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break;
8759 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break;
8760 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break;
8761 default: llvm_unreachable("unexpected overflowing operator");
8763 if (CondOpcode == ISD::UMULO)
8764 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(),
8767 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
8769 SDValue X86Op = DAG.getNode(X86Opcode, DL, VTs, LHS, RHS);
8771 if (CondOpcode == ISD::UMULO)
8772 Cond = X86Op.getValue(2);
8774 Cond = X86Op.getValue(1);
8776 CC = DAG.getConstant(X86Cond, MVT::i8);
8781 // Look pass the truncate.
8782 if (Cond.getOpcode() == ISD::TRUNCATE)
8783 Cond = Cond.getOperand(0);
8785 // We know the result of AND is compared against zero. Try to match
8787 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
8788 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, DL, DAG);
8789 if (NewSetCC.getNode()) {
8790 CC = NewSetCC.getOperand(0);
8791 Cond = NewSetCC.getOperand(1);
8798 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
8799 Cond = EmitTest(Cond, X86::COND_NE, DAG);
8802 // a < b ? -1 : 0 -> RES = ~setcc_carry
8803 // a < b ? 0 : -1 -> RES = setcc_carry
8804 // a >= b ? -1 : 0 -> RES = setcc_carry
8805 // a >= b ? 0 : -1 -> RES = ~setcc_carry
8806 if (Cond.getOpcode() == X86ISD::CMP) {
8807 Cond = ConvertCmpIfNecessary(Cond, DAG);
8808 unsigned CondCode = cast<ConstantSDNode>(CC)->getZExtValue();
8810 if ((CondCode == X86::COND_AE || CondCode == X86::COND_B) &&
8811 (isAllOnes(Op1) || isAllOnes(Op2)) && (isZero(Op1) || isZero(Op2))) {
8812 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
8813 DAG.getConstant(X86::COND_B, MVT::i8), Cond);
8814 if (isAllOnes(Op1) != (CondCode == X86::COND_B))
8815 return DAG.getNOT(DL, Res, Res.getValueType());
8820 // X86ISD::CMOV means set the result (which is operand 1) to the RHS if
8821 // condition is true.
8822 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue);
8823 SDValue Ops[] = { Op2, Op1, CC, Cond };
8824 return DAG.getNode(X86ISD::CMOV, DL, VTs, Ops, array_lengthof(Ops));
8827 // isAndOrOfSingleUseSetCCs - Return true if node is an ISD::AND or
8828 // ISD::OR of two X86ISD::SETCC nodes each of which has no other use apart
8829 // from the AND / OR.
8830 static bool isAndOrOfSetCCs(SDValue Op, unsigned &Opc) {
8831 Opc = Op.getOpcode();
8832 if (Opc != ISD::OR && Opc != ISD::AND)
8834 return (Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
8835 Op.getOperand(0).hasOneUse() &&
8836 Op.getOperand(1).getOpcode() == X86ISD::SETCC &&
8837 Op.getOperand(1).hasOneUse());
8840 // isXor1OfSetCC - Return true if node is an ISD::XOR of a X86ISD::SETCC and
8841 // 1 and that the SETCC node has a single use.
8842 static bool isXor1OfSetCC(SDValue Op) {
8843 if (Op.getOpcode() != ISD::XOR)
8845 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
8846 if (N1C && N1C->getAPIntValue() == 1) {
8847 return Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
8848 Op.getOperand(0).hasOneUse();
8853 SDValue X86TargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) const {
8854 bool addTest = true;
8855 SDValue Chain = Op.getOperand(0);
8856 SDValue Cond = Op.getOperand(1);
8857 SDValue Dest = Op.getOperand(2);
8858 DebugLoc dl = Op.getDebugLoc();
8860 bool Inverted = false;
8862 if (Cond.getOpcode() == ISD::SETCC) {
8863 // Check for setcc([su]{add,sub,mul}o == 0).
8864 if (cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETEQ &&
8865 isa<ConstantSDNode>(Cond.getOperand(1)) &&
8866 cast<ConstantSDNode>(Cond.getOperand(1))->isNullValue() &&
8867 Cond.getOperand(0).getResNo() == 1 &&
8868 (Cond.getOperand(0).getOpcode() == ISD::SADDO ||
8869 Cond.getOperand(0).getOpcode() == ISD::UADDO ||
8870 Cond.getOperand(0).getOpcode() == ISD::SSUBO ||
8871 Cond.getOperand(0).getOpcode() == ISD::USUBO ||
8872 Cond.getOperand(0).getOpcode() == ISD::SMULO ||
8873 Cond.getOperand(0).getOpcode() == ISD::UMULO)) {
8875 Cond = Cond.getOperand(0);
8877 SDValue NewCond = LowerSETCC(Cond, DAG);
8878 if (NewCond.getNode())
8883 // FIXME: LowerXALUO doesn't handle these!!
8884 else if (Cond.getOpcode() == X86ISD::ADD ||
8885 Cond.getOpcode() == X86ISD::SUB ||
8886 Cond.getOpcode() == X86ISD::SMUL ||
8887 Cond.getOpcode() == X86ISD::UMUL)
8888 Cond = LowerXALUO(Cond, DAG);
8891 // Look pass (and (setcc_carry (cmp ...)), 1).
8892 if (Cond.getOpcode() == ISD::AND &&
8893 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
8894 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
8895 if (C && C->getAPIntValue() == 1)
8896 Cond = Cond.getOperand(0);
8899 // If condition flag is set by a X86ISD::CMP, then use it as the condition
8900 // setting operand in place of the X86ISD::SETCC.
8901 unsigned CondOpcode = Cond.getOpcode();
8902 if (CondOpcode == X86ISD::SETCC ||
8903 CondOpcode == X86ISD::SETCC_CARRY) {
8904 CC = Cond.getOperand(0);
8906 SDValue Cmp = Cond.getOperand(1);
8907 unsigned Opc = Cmp.getOpcode();
8908 // FIXME: WHY THE SPECIAL CASING OF LogicalCmp??
8909 if (isX86LogicalCmp(Cmp) || Opc == X86ISD::BT) {
8913 switch (cast<ConstantSDNode>(CC)->getZExtValue()) {
8917 // These can only come from an arithmetic instruction with overflow,
8918 // e.g. SADDO, UADDO.
8919 Cond = Cond.getNode()->getOperand(1);
8925 CondOpcode = Cond.getOpcode();
8926 if (CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO ||
8927 CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO ||
8928 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) &&
8929 Cond.getOperand(0).getValueType() != MVT::i8)) {
8930 SDValue LHS = Cond.getOperand(0);
8931 SDValue RHS = Cond.getOperand(1);
8935 switch (CondOpcode) {
8936 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break;
8937 case ISD::SADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break;
8938 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break;
8939 case ISD::SSUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break;
8940 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break;
8941 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break;
8942 default: llvm_unreachable("unexpected overflowing operator");
8945 X86Cond = X86::GetOppositeBranchCondition((X86::CondCode)X86Cond);
8946 if (CondOpcode == ISD::UMULO)
8947 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(),
8950 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
8952 SDValue X86Op = DAG.getNode(X86Opcode, dl, VTs, LHS, RHS);
8954 if (CondOpcode == ISD::UMULO)
8955 Cond = X86Op.getValue(2);
8957 Cond = X86Op.getValue(1);
8959 CC = DAG.getConstant(X86Cond, MVT::i8);
8963 if (Cond.hasOneUse() && isAndOrOfSetCCs(Cond, CondOpc)) {
8964 SDValue Cmp = Cond.getOperand(0).getOperand(1);
8965 if (CondOpc == ISD::OR) {
8966 // Also, recognize the pattern generated by an FCMP_UNE. We can emit
8967 // two branches instead of an explicit OR instruction with a
8969 if (Cmp == Cond.getOperand(1).getOperand(1) &&
8970 isX86LogicalCmp(Cmp)) {
8971 CC = Cond.getOperand(0).getOperand(0);
8972 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
8973 Chain, Dest, CC, Cmp);
8974 CC = Cond.getOperand(1).getOperand(0);
8978 } else { // ISD::AND
8979 // Also, recognize the pattern generated by an FCMP_OEQ. We can emit
8980 // two branches instead of an explicit AND instruction with a
8981 // separate test. However, we only do this if this block doesn't
8982 // have a fall-through edge, because this requires an explicit
8983 // jmp when the condition is false.
8984 if (Cmp == Cond.getOperand(1).getOperand(1) &&
8985 isX86LogicalCmp(Cmp) &&
8986 Op.getNode()->hasOneUse()) {
8987 X86::CondCode CCode =
8988 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
8989 CCode = X86::GetOppositeBranchCondition(CCode);
8990 CC = DAG.getConstant(CCode, MVT::i8);
8991 SDNode *User = *Op.getNode()->use_begin();
8992 // Look for an unconditional branch following this conditional branch.
8993 // We need this because we need to reverse the successors in order
8994 // to implement FCMP_OEQ.
8995 if (User->getOpcode() == ISD::BR) {
8996 SDValue FalseBB = User->getOperand(1);
8998 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
8999 assert(NewBR == User);
9003 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
9004 Chain, Dest, CC, Cmp);
9005 X86::CondCode CCode =
9006 (X86::CondCode)Cond.getOperand(1).getConstantOperandVal(0);
9007 CCode = X86::GetOppositeBranchCondition(CCode);
9008 CC = DAG.getConstant(CCode, MVT::i8);
9014 } else if (Cond.hasOneUse() && isXor1OfSetCC(Cond)) {
9015 // Recognize for xorb (setcc), 1 patterns. The xor inverts the condition.
9016 // It should be transformed during dag combiner except when the condition
9017 // is set by a arithmetics with overflow node.
9018 X86::CondCode CCode =
9019 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
9020 CCode = X86::GetOppositeBranchCondition(CCode);
9021 CC = DAG.getConstant(CCode, MVT::i8);
9022 Cond = Cond.getOperand(0).getOperand(1);
9024 } else if (Cond.getOpcode() == ISD::SETCC &&
9025 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETOEQ) {
9026 // For FCMP_OEQ, we can emit
9027 // two branches instead of an explicit AND instruction with a
9028 // separate test. However, we only do this if this block doesn't
9029 // have a fall-through edge, because this requires an explicit
9030 // jmp when the condition is false.
9031 if (Op.getNode()->hasOneUse()) {
9032 SDNode *User = *Op.getNode()->use_begin();
9033 // Look for an unconditional branch following this conditional branch.
9034 // We need this because we need to reverse the successors in order
9035 // to implement FCMP_OEQ.
9036 if (User->getOpcode() == ISD::BR) {
9037 SDValue FalseBB = User->getOperand(1);
9039 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
9040 assert(NewBR == User);
9044 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
9045 Cond.getOperand(0), Cond.getOperand(1));
9046 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
9047 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
9048 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
9049 Chain, Dest, CC, Cmp);
9050 CC = DAG.getConstant(X86::COND_P, MVT::i8);
9055 } else if (Cond.getOpcode() == ISD::SETCC &&
9056 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETUNE) {
9057 // For FCMP_UNE, we can emit
9058 // two branches instead of an explicit AND instruction with a
9059 // separate test. However, we only do this if this block doesn't
9060 // have a fall-through edge, because this requires an explicit
9061 // jmp when the condition is false.
9062 if (Op.getNode()->hasOneUse()) {
9063 SDNode *User = *Op.getNode()->use_begin();
9064 // Look for an unconditional branch following this conditional branch.
9065 // We need this because we need to reverse the successors in order
9066 // to implement FCMP_UNE.
9067 if (User->getOpcode() == ISD::BR) {
9068 SDValue FalseBB = User->getOperand(1);
9070 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
9071 assert(NewBR == User);
9074 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
9075 Cond.getOperand(0), Cond.getOperand(1));
9076 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
9077 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
9078 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
9079 Chain, Dest, CC, Cmp);
9080 CC = DAG.getConstant(X86::COND_NP, MVT::i8);
9090 // Look pass the truncate.
9091 if (Cond.getOpcode() == ISD::TRUNCATE)
9092 Cond = Cond.getOperand(0);
9094 // We know the result of AND is compared against zero. Try to match
9096 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
9097 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, dl, DAG);
9098 if (NewSetCC.getNode()) {
9099 CC = NewSetCC.getOperand(0);
9100 Cond = NewSetCC.getOperand(1);
9107 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
9108 Cond = EmitTest(Cond, X86::COND_NE, DAG);
9110 Cond = ConvertCmpIfNecessary(Cond, DAG);
9111 return DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
9112 Chain, Dest, CC, Cond);
9116 // Lower dynamic stack allocation to _alloca call for Cygwin/Mingw targets.
9117 // Calls to _alloca is needed to probe the stack when allocating more than 4k
9118 // bytes in one go. Touching the stack at 4K increments is necessary to ensure
9119 // that the guard pages used by the OS virtual memory manager are allocated in
9120 // correct sequence.
9122 X86TargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
9123 SelectionDAG &DAG) const {
9124 assert((Subtarget->isTargetCygMing() || Subtarget->isTargetWindows() ||
9125 getTargetMachine().Options.EnableSegmentedStacks) &&
9126 "This should be used only on Windows targets or when segmented stacks "
9128 assert(!Subtarget->isTargetEnvMacho() && "Not implemented");
9129 DebugLoc dl = Op.getDebugLoc();
9132 SDValue Chain = Op.getOperand(0);
9133 SDValue Size = Op.getOperand(1);
9134 // FIXME: Ensure alignment here
9136 bool Is64Bit = Subtarget->is64Bit();
9137 EVT SPTy = Is64Bit ? MVT::i64 : MVT::i32;
9139 if (getTargetMachine().Options.EnableSegmentedStacks) {
9140 MachineFunction &MF = DAG.getMachineFunction();
9141 MachineRegisterInfo &MRI = MF.getRegInfo();
9144 // The 64 bit implementation of segmented stacks needs to clobber both r10
9145 // r11. This makes it impossible to use it along with nested parameters.
9146 const Function *F = MF.getFunction();
9148 for (Function::const_arg_iterator I = F->arg_begin(), E = F->arg_end();
9150 if (I->hasNestAttr())
9151 report_fatal_error("Cannot use segmented stacks with functions that "
9152 "have nested arguments.");
9155 const TargetRegisterClass *AddrRegClass =
9156 getRegClassFor(Subtarget->is64Bit() ? MVT::i64:MVT::i32);
9157 unsigned Vreg = MRI.createVirtualRegister(AddrRegClass);
9158 Chain = DAG.getCopyToReg(Chain, dl, Vreg, Size);
9159 SDValue Value = DAG.getNode(X86ISD::SEG_ALLOCA, dl, SPTy, Chain,
9160 DAG.getRegister(Vreg, SPTy));
9161 SDValue Ops1[2] = { Value, Chain };
9162 return DAG.getMergeValues(Ops1, 2, dl);
9165 unsigned Reg = (Subtarget->is64Bit() ? X86::RAX : X86::EAX);
9167 Chain = DAG.getCopyToReg(Chain, dl, Reg, Size, Flag);
9168 Flag = Chain.getValue(1);
9169 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
9171 Chain = DAG.getNode(X86ISD::WIN_ALLOCA, dl, NodeTys, Chain, Flag);
9172 Flag = Chain.getValue(1);
9174 Chain = DAG.getCopyFromReg(Chain, dl, X86StackPtr, SPTy).getValue(1);
9176 SDValue Ops1[2] = { Chain.getValue(0), Chain };
9177 return DAG.getMergeValues(Ops1, 2, dl);
9181 SDValue X86TargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const {
9182 MachineFunction &MF = DAG.getMachineFunction();
9183 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
9185 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
9186 DebugLoc DL = Op.getDebugLoc();
9188 if (!Subtarget->is64Bit() || Subtarget->isTargetWin64()) {
9189 // vastart just stores the address of the VarArgsFrameIndex slot into the
9190 // memory location argument.
9191 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
9193 return DAG.getStore(Op.getOperand(0), DL, FR, Op.getOperand(1),
9194 MachinePointerInfo(SV), false, false, 0);
9198 // gp_offset (0 - 6 * 8)
9199 // fp_offset (48 - 48 + 8 * 16)
9200 // overflow_arg_area (point to parameters coming in memory).
9202 SmallVector<SDValue, 8> MemOps;
9203 SDValue FIN = Op.getOperand(1);
9205 SDValue Store = DAG.getStore(Op.getOperand(0), DL,
9206 DAG.getConstant(FuncInfo->getVarArgsGPOffset(),
9208 FIN, MachinePointerInfo(SV), false, false, 0);
9209 MemOps.push_back(Store);
9212 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
9213 FIN, DAG.getIntPtrConstant(4));
9214 Store = DAG.getStore(Op.getOperand(0), DL,
9215 DAG.getConstant(FuncInfo->getVarArgsFPOffset(),
9217 FIN, MachinePointerInfo(SV, 4), false, false, 0);
9218 MemOps.push_back(Store);
9220 // Store ptr to overflow_arg_area
9221 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
9222 FIN, DAG.getIntPtrConstant(4));
9223 SDValue OVFIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
9225 Store = DAG.getStore(Op.getOperand(0), DL, OVFIN, FIN,
9226 MachinePointerInfo(SV, 8),
9228 MemOps.push_back(Store);
9230 // Store ptr to reg_save_area.
9231 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
9232 FIN, DAG.getIntPtrConstant(8));
9233 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
9235 Store = DAG.getStore(Op.getOperand(0), DL, RSFIN, FIN,
9236 MachinePointerInfo(SV, 16), false, false, 0);
9237 MemOps.push_back(Store);
9238 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
9239 &MemOps[0], MemOps.size());
9242 SDValue X86TargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG) const {
9243 assert(Subtarget->is64Bit() &&
9244 "LowerVAARG only handles 64-bit va_arg!");
9245 assert((Subtarget->isTargetLinux() ||
9246 Subtarget->isTargetDarwin()) &&
9247 "Unhandled target in LowerVAARG");
9248 assert(Op.getNode()->getNumOperands() == 4);
9249 SDValue Chain = Op.getOperand(0);
9250 SDValue SrcPtr = Op.getOperand(1);
9251 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
9252 unsigned Align = Op.getConstantOperandVal(3);
9253 DebugLoc dl = Op.getDebugLoc();
9255 EVT ArgVT = Op.getNode()->getValueType(0);
9256 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
9257 uint32_t ArgSize = getTargetData()->getTypeAllocSize(ArgTy);
9260 // Decide which area this value should be read from.
9261 // TODO: Implement the AMD64 ABI in its entirety. This simple
9262 // selection mechanism works only for the basic types.
9263 if (ArgVT == MVT::f80) {
9264 llvm_unreachable("va_arg for f80 not yet implemented");
9265 } else if (ArgVT.isFloatingPoint() && ArgSize <= 16 /*bytes*/) {
9266 ArgMode = 2; // Argument passed in XMM register. Use fp_offset.
9267 } else if (ArgVT.isInteger() && ArgSize <= 32 /*bytes*/) {
9268 ArgMode = 1; // Argument passed in GPR64 register(s). Use gp_offset.
9270 llvm_unreachable("Unhandled argument type in LowerVAARG");
9274 // Sanity Check: Make sure using fp_offset makes sense.
9275 assert(!getTargetMachine().Options.UseSoftFloat &&
9276 !(DAG.getMachineFunction()
9277 .getFunction()->hasFnAttr(Attribute::NoImplicitFloat)) &&
9278 Subtarget->hasSSE1());
9281 // Insert VAARG_64 node into the DAG
9282 // VAARG_64 returns two values: Variable Argument Address, Chain
9283 SmallVector<SDValue, 11> InstOps;
9284 InstOps.push_back(Chain);
9285 InstOps.push_back(SrcPtr);
9286 InstOps.push_back(DAG.getConstant(ArgSize, MVT::i32));
9287 InstOps.push_back(DAG.getConstant(ArgMode, MVT::i8));
9288 InstOps.push_back(DAG.getConstant(Align, MVT::i32));
9289 SDVTList VTs = DAG.getVTList(getPointerTy(), MVT::Other);
9290 SDValue VAARG = DAG.getMemIntrinsicNode(X86ISD::VAARG_64, dl,
9291 VTs, &InstOps[0], InstOps.size(),
9293 MachinePointerInfo(SV),
9298 Chain = VAARG.getValue(1);
9300 // Load the next argument and return it
9301 return DAG.getLoad(ArgVT, dl,
9304 MachinePointerInfo(),
9305 false, false, false, 0);
9308 SDValue X86TargetLowering::LowerVACOPY(SDValue Op, SelectionDAG &DAG) const {
9309 // X86-64 va_list is a struct { i32, i32, i8*, i8* }.
9310 assert(Subtarget->is64Bit() && "This code only handles 64-bit va_copy!");
9311 SDValue Chain = Op.getOperand(0);
9312 SDValue DstPtr = Op.getOperand(1);
9313 SDValue SrcPtr = Op.getOperand(2);
9314 const Value *DstSV = cast<SrcValueSDNode>(Op.getOperand(3))->getValue();
9315 const Value *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
9316 DebugLoc DL = Op.getDebugLoc();
9318 return DAG.getMemcpy(Chain, DL, DstPtr, SrcPtr,
9319 DAG.getIntPtrConstant(24), 8, /*isVolatile*/false,
9321 MachinePointerInfo(DstSV), MachinePointerInfo(SrcSV));
9324 // getTargetVShiftNOde - Handle vector element shifts where the shift amount
9325 // may or may not be a constant. Takes immediate version of shift as input.
9326 static SDValue getTargetVShiftNode(unsigned Opc, DebugLoc dl, EVT VT,
9327 SDValue SrcOp, SDValue ShAmt,
9328 SelectionDAG &DAG) {
9329 assert(ShAmt.getValueType() == MVT::i32 && "ShAmt is not i32");
9331 if (isa<ConstantSDNode>(ShAmt)) {
9333 default: llvm_unreachable("Unknown target vector shift node");
9337 return DAG.getNode(Opc, dl, VT, SrcOp, ShAmt);
9341 // Change opcode to non-immediate version
9343 default: llvm_unreachable("Unknown target vector shift node");
9344 case X86ISD::VSHLI: Opc = X86ISD::VSHL; break;
9345 case X86ISD::VSRLI: Opc = X86ISD::VSRL; break;
9346 case X86ISD::VSRAI: Opc = X86ISD::VSRA; break;
9349 // Need to build a vector containing shift amount
9350 // Shift amount is 32-bits, but SSE instructions read 64-bit, so fill with 0
9353 ShOps[1] = DAG.getConstant(0, MVT::i32);
9354 ShOps[2] = DAG.getUNDEF(MVT::i32);
9355 ShOps[3] = DAG.getUNDEF(MVT::i32);
9356 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, &ShOps[0], 4);
9357 ShAmt = DAG.getNode(ISD::BITCAST, dl, VT, ShAmt);
9358 return DAG.getNode(Opc, dl, VT, SrcOp, ShAmt);
9362 X86TargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const {
9363 DebugLoc dl = Op.getDebugLoc();
9364 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
9366 default: return SDValue(); // Don't custom lower most intrinsics.
9367 // Comparison intrinsics.
9368 case Intrinsic::x86_sse_comieq_ss:
9369 case Intrinsic::x86_sse_comilt_ss:
9370 case Intrinsic::x86_sse_comile_ss:
9371 case Intrinsic::x86_sse_comigt_ss:
9372 case Intrinsic::x86_sse_comige_ss:
9373 case Intrinsic::x86_sse_comineq_ss:
9374 case Intrinsic::x86_sse_ucomieq_ss:
9375 case Intrinsic::x86_sse_ucomilt_ss:
9376 case Intrinsic::x86_sse_ucomile_ss:
9377 case Intrinsic::x86_sse_ucomigt_ss:
9378 case Intrinsic::x86_sse_ucomige_ss:
9379 case Intrinsic::x86_sse_ucomineq_ss:
9380 case Intrinsic::x86_sse2_comieq_sd:
9381 case Intrinsic::x86_sse2_comilt_sd:
9382 case Intrinsic::x86_sse2_comile_sd:
9383 case Intrinsic::x86_sse2_comigt_sd:
9384 case Intrinsic::x86_sse2_comige_sd:
9385 case Intrinsic::x86_sse2_comineq_sd:
9386 case Intrinsic::x86_sse2_ucomieq_sd:
9387 case Intrinsic::x86_sse2_ucomilt_sd:
9388 case Intrinsic::x86_sse2_ucomile_sd:
9389 case Intrinsic::x86_sse2_ucomigt_sd:
9390 case Intrinsic::x86_sse2_ucomige_sd:
9391 case Intrinsic::x86_sse2_ucomineq_sd: {
9393 ISD::CondCode CC = ISD::SETCC_INVALID;
9395 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
9396 case Intrinsic::x86_sse_comieq_ss:
9397 case Intrinsic::x86_sse2_comieq_sd:
9401 case Intrinsic::x86_sse_comilt_ss:
9402 case Intrinsic::x86_sse2_comilt_sd:
9406 case Intrinsic::x86_sse_comile_ss:
9407 case Intrinsic::x86_sse2_comile_sd:
9411 case Intrinsic::x86_sse_comigt_ss:
9412 case Intrinsic::x86_sse2_comigt_sd:
9416 case Intrinsic::x86_sse_comige_ss:
9417 case Intrinsic::x86_sse2_comige_sd:
9421 case Intrinsic::x86_sse_comineq_ss:
9422 case Intrinsic::x86_sse2_comineq_sd:
9426 case Intrinsic::x86_sse_ucomieq_ss:
9427 case Intrinsic::x86_sse2_ucomieq_sd:
9428 Opc = X86ISD::UCOMI;
9431 case Intrinsic::x86_sse_ucomilt_ss:
9432 case Intrinsic::x86_sse2_ucomilt_sd:
9433 Opc = X86ISD::UCOMI;
9436 case Intrinsic::x86_sse_ucomile_ss:
9437 case Intrinsic::x86_sse2_ucomile_sd:
9438 Opc = X86ISD::UCOMI;
9441 case Intrinsic::x86_sse_ucomigt_ss:
9442 case Intrinsic::x86_sse2_ucomigt_sd:
9443 Opc = X86ISD::UCOMI;
9446 case Intrinsic::x86_sse_ucomige_ss:
9447 case Intrinsic::x86_sse2_ucomige_sd:
9448 Opc = X86ISD::UCOMI;
9451 case Intrinsic::x86_sse_ucomineq_ss:
9452 case Intrinsic::x86_sse2_ucomineq_sd:
9453 Opc = X86ISD::UCOMI;
9458 SDValue LHS = Op.getOperand(1);
9459 SDValue RHS = Op.getOperand(2);
9460 unsigned X86CC = TranslateX86CC(CC, true, LHS, RHS, DAG);
9461 assert(X86CC != X86::COND_INVALID && "Unexpected illegal condition!");
9462 SDValue Cond = DAG.getNode(Opc, dl, MVT::i32, LHS, RHS);
9463 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
9464 DAG.getConstant(X86CC, MVT::i8), Cond);
9465 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
9467 // XOP comparison intrinsics
9468 case Intrinsic::x86_xop_vpcomltb:
9469 case Intrinsic::x86_xop_vpcomltw:
9470 case Intrinsic::x86_xop_vpcomltd:
9471 case Intrinsic::x86_xop_vpcomltq:
9472 case Intrinsic::x86_xop_vpcomltub:
9473 case Intrinsic::x86_xop_vpcomltuw:
9474 case Intrinsic::x86_xop_vpcomltud:
9475 case Intrinsic::x86_xop_vpcomltuq:
9476 case Intrinsic::x86_xop_vpcomleb:
9477 case Intrinsic::x86_xop_vpcomlew:
9478 case Intrinsic::x86_xop_vpcomled:
9479 case Intrinsic::x86_xop_vpcomleq:
9480 case Intrinsic::x86_xop_vpcomleub:
9481 case Intrinsic::x86_xop_vpcomleuw:
9482 case Intrinsic::x86_xop_vpcomleud:
9483 case Intrinsic::x86_xop_vpcomleuq:
9484 case Intrinsic::x86_xop_vpcomgtb:
9485 case Intrinsic::x86_xop_vpcomgtw:
9486 case Intrinsic::x86_xop_vpcomgtd:
9487 case Intrinsic::x86_xop_vpcomgtq:
9488 case Intrinsic::x86_xop_vpcomgtub:
9489 case Intrinsic::x86_xop_vpcomgtuw:
9490 case Intrinsic::x86_xop_vpcomgtud:
9491 case Intrinsic::x86_xop_vpcomgtuq:
9492 case Intrinsic::x86_xop_vpcomgeb:
9493 case Intrinsic::x86_xop_vpcomgew:
9494 case Intrinsic::x86_xop_vpcomged:
9495 case Intrinsic::x86_xop_vpcomgeq:
9496 case Intrinsic::x86_xop_vpcomgeub:
9497 case Intrinsic::x86_xop_vpcomgeuw:
9498 case Intrinsic::x86_xop_vpcomgeud:
9499 case Intrinsic::x86_xop_vpcomgeuq:
9500 case Intrinsic::x86_xop_vpcomeqb:
9501 case Intrinsic::x86_xop_vpcomeqw:
9502 case Intrinsic::x86_xop_vpcomeqd:
9503 case Intrinsic::x86_xop_vpcomeqq:
9504 case Intrinsic::x86_xop_vpcomequb:
9505 case Intrinsic::x86_xop_vpcomequw:
9506 case Intrinsic::x86_xop_vpcomequd:
9507 case Intrinsic::x86_xop_vpcomequq:
9508 case Intrinsic::x86_xop_vpcomneb:
9509 case Intrinsic::x86_xop_vpcomnew:
9510 case Intrinsic::x86_xop_vpcomned:
9511 case Intrinsic::x86_xop_vpcomneq:
9512 case Intrinsic::x86_xop_vpcomneub:
9513 case Intrinsic::x86_xop_vpcomneuw:
9514 case Intrinsic::x86_xop_vpcomneud:
9515 case Intrinsic::x86_xop_vpcomneuq:
9516 case Intrinsic::x86_xop_vpcomfalseb:
9517 case Intrinsic::x86_xop_vpcomfalsew:
9518 case Intrinsic::x86_xop_vpcomfalsed:
9519 case Intrinsic::x86_xop_vpcomfalseq:
9520 case Intrinsic::x86_xop_vpcomfalseub:
9521 case Intrinsic::x86_xop_vpcomfalseuw:
9522 case Intrinsic::x86_xop_vpcomfalseud:
9523 case Intrinsic::x86_xop_vpcomfalseuq:
9524 case Intrinsic::x86_xop_vpcomtrueb:
9525 case Intrinsic::x86_xop_vpcomtruew:
9526 case Intrinsic::x86_xop_vpcomtrued:
9527 case Intrinsic::x86_xop_vpcomtrueq:
9528 case Intrinsic::x86_xop_vpcomtrueub:
9529 case Intrinsic::x86_xop_vpcomtrueuw:
9530 case Intrinsic::x86_xop_vpcomtrueud:
9531 case Intrinsic::x86_xop_vpcomtrueuq: {
9536 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
9537 case Intrinsic::x86_xop_vpcomltb:
9538 case Intrinsic::x86_xop_vpcomltw:
9539 case Intrinsic::x86_xop_vpcomltd:
9540 case Intrinsic::x86_xop_vpcomltq:
9542 Opc = X86ISD::VPCOM;
9544 case Intrinsic::x86_xop_vpcomltub:
9545 case Intrinsic::x86_xop_vpcomltuw:
9546 case Intrinsic::x86_xop_vpcomltud:
9547 case Intrinsic::x86_xop_vpcomltuq:
9549 Opc = X86ISD::VPCOMU;
9551 case Intrinsic::x86_xop_vpcomleb:
9552 case Intrinsic::x86_xop_vpcomlew:
9553 case Intrinsic::x86_xop_vpcomled:
9554 case Intrinsic::x86_xop_vpcomleq:
9556 Opc = X86ISD::VPCOM;
9558 case Intrinsic::x86_xop_vpcomleub:
9559 case Intrinsic::x86_xop_vpcomleuw:
9560 case Intrinsic::x86_xop_vpcomleud:
9561 case Intrinsic::x86_xop_vpcomleuq:
9563 Opc = X86ISD::VPCOMU;
9565 case Intrinsic::x86_xop_vpcomgtb:
9566 case Intrinsic::x86_xop_vpcomgtw:
9567 case Intrinsic::x86_xop_vpcomgtd:
9568 case Intrinsic::x86_xop_vpcomgtq:
9570 Opc = X86ISD::VPCOM;
9572 case Intrinsic::x86_xop_vpcomgtub:
9573 case Intrinsic::x86_xop_vpcomgtuw:
9574 case Intrinsic::x86_xop_vpcomgtud:
9575 case Intrinsic::x86_xop_vpcomgtuq:
9577 Opc = X86ISD::VPCOMU;
9579 case Intrinsic::x86_xop_vpcomgeb:
9580 case Intrinsic::x86_xop_vpcomgew:
9581 case Intrinsic::x86_xop_vpcomged:
9582 case Intrinsic::x86_xop_vpcomgeq:
9584 Opc = X86ISD::VPCOM;
9586 case Intrinsic::x86_xop_vpcomgeub:
9587 case Intrinsic::x86_xop_vpcomgeuw:
9588 case Intrinsic::x86_xop_vpcomgeud:
9589 case Intrinsic::x86_xop_vpcomgeuq:
9591 Opc = X86ISD::VPCOMU;
9593 case Intrinsic::x86_xop_vpcomeqb:
9594 case Intrinsic::x86_xop_vpcomeqw:
9595 case Intrinsic::x86_xop_vpcomeqd:
9596 case Intrinsic::x86_xop_vpcomeqq:
9598 Opc = X86ISD::VPCOM;
9600 case Intrinsic::x86_xop_vpcomequb:
9601 case Intrinsic::x86_xop_vpcomequw:
9602 case Intrinsic::x86_xop_vpcomequd:
9603 case Intrinsic::x86_xop_vpcomequq:
9605 Opc = X86ISD::VPCOMU;
9607 case Intrinsic::x86_xop_vpcomneb:
9608 case Intrinsic::x86_xop_vpcomnew:
9609 case Intrinsic::x86_xop_vpcomned:
9610 case Intrinsic::x86_xop_vpcomneq:
9612 Opc = X86ISD::VPCOM;
9614 case Intrinsic::x86_xop_vpcomneub:
9615 case Intrinsic::x86_xop_vpcomneuw:
9616 case Intrinsic::x86_xop_vpcomneud:
9617 case Intrinsic::x86_xop_vpcomneuq:
9619 Opc = X86ISD::VPCOMU;
9621 case Intrinsic::x86_xop_vpcomfalseb:
9622 case Intrinsic::x86_xop_vpcomfalsew:
9623 case Intrinsic::x86_xop_vpcomfalsed:
9624 case Intrinsic::x86_xop_vpcomfalseq:
9626 Opc = X86ISD::VPCOM;
9628 case Intrinsic::x86_xop_vpcomfalseub:
9629 case Intrinsic::x86_xop_vpcomfalseuw:
9630 case Intrinsic::x86_xop_vpcomfalseud:
9631 case Intrinsic::x86_xop_vpcomfalseuq:
9633 Opc = X86ISD::VPCOMU;
9635 case Intrinsic::x86_xop_vpcomtrueb:
9636 case Intrinsic::x86_xop_vpcomtruew:
9637 case Intrinsic::x86_xop_vpcomtrued:
9638 case Intrinsic::x86_xop_vpcomtrueq:
9640 Opc = X86ISD::VPCOM;
9642 case Intrinsic::x86_xop_vpcomtrueub:
9643 case Intrinsic::x86_xop_vpcomtrueuw:
9644 case Intrinsic::x86_xop_vpcomtrueud:
9645 case Intrinsic::x86_xop_vpcomtrueuq:
9647 Opc = X86ISD::VPCOMU;
9651 SDValue LHS = Op.getOperand(1);
9652 SDValue RHS = Op.getOperand(2);
9653 return DAG.getNode(Opc, dl, Op.getValueType(), LHS, RHS,
9654 DAG.getConstant(CC, MVT::i8));
9657 // Arithmetic intrinsics.
9658 case Intrinsic::x86_sse2_pmulu_dq:
9659 case Intrinsic::x86_avx2_pmulu_dq:
9660 return DAG.getNode(X86ISD::PMULUDQ, dl, Op.getValueType(),
9661 Op.getOperand(1), Op.getOperand(2));
9662 case Intrinsic::x86_sse3_hadd_ps:
9663 case Intrinsic::x86_sse3_hadd_pd:
9664 case Intrinsic::x86_avx_hadd_ps_256:
9665 case Intrinsic::x86_avx_hadd_pd_256:
9666 return DAG.getNode(X86ISD::FHADD, dl, Op.getValueType(),
9667 Op.getOperand(1), Op.getOperand(2));
9668 case Intrinsic::x86_sse3_hsub_ps:
9669 case Intrinsic::x86_sse3_hsub_pd:
9670 case Intrinsic::x86_avx_hsub_ps_256:
9671 case Intrinsic::x86_avx_hsub_pd_256:
9672 return DAG.getNode(X86ISD::FHSUB, dl, Op.getValueType(),
9673 Op.getOperand(1), Op.getOperand(2));
9674 case Intrinsic::x86_ssse3_phadd_w_128:
9675 case Intrinsic::x86_ssse3_phadd_d_128:
9676 case Intrinsic::x86_avx2_phadd_w:
9677 case Intrinsic::x86_avx2_phadd_d:
9678 return DAG.getNode(X86ISD::HADD, dl, Op.getValueType(),
9679 Op.getOperand(1), Op.getOperand(2));
9680 case Intrinsic::x86_ssse3_phsub_w_128:
9681 case Intrinsic::x86_ssse3_phsub_d_128:
9682 case Intrinsic::x86_avx2_phsub_w:
9683 case Intrinsic::x86_avx2_phsub_d:
9684 return DAG.getNode(X86ISD::HSUB, dl, Op.getValueType(),
9685 Op.getOperand(1), Op.getOperand(2));
9686 case Intrinsic::x86_avx2_psllv_d:
9687 case Intrinsic::x86_avx2_psllv_q:
9688 case Intrinsic::x86_avx2_psllv_d_256:
9689 case Intrinsic::x86_avx2_psllv_q_256:
9690 return DAG.getNode(ISD::SHL, dl, Op.getValueType(),
9691 Op.getOperand(1), Op.getOperand(2));
9692 case Intrinsic::x86_avx2_psrlv_d:
9693 case Intrinsic::x86_avx2_psrlv_q:
9694 case Intrinsic::x86_avx2_psrlv_d_256:
9695 case Intrinsic::x86_avx2_psrlv_q_256:
9696 return DAG.getNode(ISD::SRL, dl, Op.getValueType(),
9697 Op.getOperand(1), Op.getOperand(2));
9698 case Intrinsic::x86_avx2_psrav_d:
9699 case Intrinsic::x86_avx2_psrav_d_256:
9700 return DAG.getNode(ISD::SRA, dl, Op.getValueType(),
9701 Op.getOperand(1), Op.getOperand(2));
9702 case Intrinsic::x86_ssse3_pshuf_b_128:
9703 case Intrinsic::x86_avx2_pshuf_b:
9704 return DAG.getNode(X86ISD::PSHUFB, dl, Op.getValueType(),
9705 Op.getOperand(1), Op.getOperand(2));
9706 case Intrinsic::x86_ssse3_psign_b_128:
9707 case Intrinsic::x86_ssse3_psign_w_128:
9708 case Intrinsic::x86_ssse3_psign_d_128:
9709 case Intrinsic::x86_avx2_psign_b:
9710 case Intrinsic::x86_avx2_psign_w:
9711 case Intrinsic::x86_avx2_psign_d:
9712 return DAG.getNode(X86ISD::PSIGN, dl, Op.getValueType(),
9713 Op.getOperand(1), Op.getOperand(2));
9714 case Intrinsic::x86_sse41_insertps:
9715 return DAG.getNode(X86ISD::INSERTPS, dl, Op.getValueType(),
9716 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
9717 case Intrinsic::x86_avx_vperm2f128_ps_256:
9718 case Intrinsic::x86_avx_vperm2f128_pd_256:
9719 case Intrinsic::x86_avx_vperm2f128_si_256:
9720 case Intrinsic::x86_avx2_vperm2i128:
9721 return DAG.getNode(X86ISD::VPERM2X128, dl, Op.getValueType(),
9722 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
9723 case Intrinsic::x86_avx2_permd:
9724 case Intrinsic::x86_avx2_permps:
9725 // Operands intentionally swapped. Mask is last operand to intrinsic,
9726 // but second operand for node/intruction.
9727 return DAG.getNode(X86ISD::VPERMV, dl, Op.getValueType(),
9728 Op.getOperand(2), Op.getOperand(1));
9730 // ptest and testp intrinsics. The intrinsic these come from are designed to
9731 // return an integer value, not just an instruction so lower it to the ptest
9732 // or testp pattern and a setcc for the result.
9733 case Intrinsic::x86_sse41_ptestz:
9734 case Intrinsic::x86_sse41_ptestc:
9735 case Intrinsic::x86_sse41_ptestnzc:
9736 case Intrinsic::x86_avx_ptestz_256:
9737 case Intrinsic::x86_avx_ptestc_256:
9738 case Intrinsic::x86_avx_ptestnzc_256:
9739 case Intrinsic::x86_avx_vtestz_ps:
9740 case Intrinsic::x86_avx_vtestc_ps:
9741 case Intrinsic::x86_avx_vtestnzc_ps:
9742 case Intrinsic::x86_avx_vtestz_pd:
9743 case Intrinsic::x86_avx_vtestc_pd:
9744 case Intrinsic::x86_avx_vtestnzc_pd:
9745 case Intrinsic::x86_avx_vtestz_ps_256:
9746 case Intrinsic::x86_avx_vtestc_ps_256:
9747 case Intrinsic::x86_avx_vtestnzc_ps_256:
9748 case Intrinsic::x86_avx_vtestz_pd_256:
9749 case Intrinsic::x86_avx_vtestc_pd_256:
9750 case Intrinsic::x86_avx_vtestnzc_pd_256: {
9751 bool IsTestPacked = false;
9754 default: llvm_unreachable("Bad fallthrough in Intrinsic lowering.");
9755 case Intrinsic::x86_avx_vtestz_ps:
9756 case Intrinsic::x86_avx_vtestz_pd:
9757 case Intrinsic::x86_avx_vtestz_ps_256:
9758 case Intrinsic::x86_avx_vtestz_pd_256:
9759 IsTestPacked = true; // Fallthrough
9760 case Intrinsic::x86_sse41_ptestz:
9761 case Intrinsic::x86_avx_ptestz_256:
9763 X86CC = X86::COND_E;
9765 case Intrinsic::x86_avx_vtestc_ps:
9766 case Intrinsic::x86_avx_vtestc_pd:
9767 case Intrinsic::x86_avx_vtestc_ps_256:
9768 case Intrinsic::x86_avx_vtestc_pd_256:
9769 IsTestPacked = true; // Fallthrough
9770 case Intrinsic::x86_sse41_ptestc:
9771 case Intrinsic::x86_avx_ptestc_256:
9773 X86CC = X86::COND_B;
9775 case Intrinsic::x86_avx_vtestnzc_ps:
9776 case Intrinsic::x86_avx_vtestnzc_pd:
9777 case Intrinsic::x86_avx_vtestnzc_ps_256:
9778 case Intrinsic::x86_avx_vtestnzc_pd_256:
9779 IsTestPacked = true; // Fallthrough
9780 case Intrinsic::x86_sse41_ptestnzc:
9781 case Intrinsic::x86_avx_ptestnzc_256:
9783 X86CC = X86::COND_A;
9787 SDValue LHS = Op.getOperand(1);
9788 SDValue RHS = Op.getOperand(2);
9789 unsigned TestOpc = IsTestPacked ? X86ISD::TESTP : X86ISD::PTEST;
9790 SDValue Test = DAG.getNode(TestOpc, dl, MVT::i32, LHS, RHS);
9791 SDValue CC = DAG.getConstant(X86CC, MVT::i8);
9792 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8, CC, Test);
9793 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
9796 // SSE/AVX shift intrinsics
9797 case Intrinsic::x86_sse2_psll_w:
9798 case Intrinsic::x86_sse2_psll_d:
9799 case Intrinsic::x86_sse2_psll_q:
9800 case Intrinsic::x86_avx2_psll_w:
9801 case Intrinsic::x86_avx2_psll_d:
9802 case Intrinsic::x86_avx2_psll_q:
9803 return DAG.getNode(X86ISD::VSHL, dl, Op.getValueType(),
9804 Op.getOperand(1), Op.getOperand(2));
9805 case Intrinsic::x86_sse2_psrl_w:
9806 case Intrinsic::x86_sse2_psrl_d:
9807 case Intrinsic::x86_sse2_psrl_q:
9808 case Intrinsic::x86_avx2_psrl_w:
9809 case Intrinsic::x86_avx2_psrl_d:
9810 case Intrinsic::x86_avx2_psrl_q:
9811 return DAG.getNode(X86ISD::VSRL, dl, Op.getValueType(),
9812 Op.getOperand(1), Op.getOperand(2));
9813 case Intrinsic::x86_sse2_psra_w:
9814 case Intrinsic::x86_sse2_psra_d:
9815 case Intrinsic::x86_avx2_psra_w:
9816 case Intrinsic::x86_avx2_psra_d:
9817 return DAG.getNode(X86ISD::VSRA, dl, Op.getValueType(),
9818 Op.getOperand(1), Op.getOperand(2));
9819 case Intrinsic::x86_sse2_pslli_w:
9820 case Intrinsic::x86_sse2_pslli_d:
9821 case Intrinsic::x86_sse2_pslli_q:
9822 case Intrinsic::x86_avx2_pslli_w:
9823 case Intrinsic::x86_avx2_pslli_d:
9824 case Intrinsic::x86_avx2_pslli_q:
9825 return getTargetVShiftNode(X86ISD::VSHLI, dl, Op.getValueType(),
9826 Op.getOperand(1), Op.getOperand(2), DAG);
9827 case Intrinsic::x86_sse2_psrli_w:
9828 case Intrinsic::x86_sse2_psrli_d:
9829 case Intrinsic::x86_sse2_psrli_q:
9830 case Intrinsic::x86_avx2_psrli_w:
9831 case Intrinsic::x86_avx2_psrli_d:
9832 case Intrinsic::x86_avx2_psrli_q:
9833 return getTargetVShiftNode(X86ISD::VSRLI, dl, Op.getValueType(),
9834 Op.getOperand(1), Op.getOperand(2), DAG);
9835 case Intrinsic::x86_sse2_psrai_w:
9836 case Intrinsic::x86_sse2_psrai_d:
9837 case Intrinsic::x86_avx2_psrai_w:
9838 case Intrinsic::x86_avx2_psrai_d:
9839 return getTargetVShiftNode(X86ISD::VSRAI, dl, Op.getValueType(),
9840 Op.getOperand(1), Op.getOperand(2), DAG);
9841 // Fix vector shift instructions where the last operand is a non-immediate
9843 case Intrinsic::x86_mmx_pslli_w:
9844 case Intrinsic::x86_mmx_pslli_d:
9845 case Intrinsic::x86_mmx_pslli_q:
9846 case Intrinsic::x86_mmx_psrli_w:
9847 case Intrinsic::x86_mmx_psrli_d:
9848 case Intrinsic::x86_mmx_psrli_q:
9849 case Intrinsic::x86_mmx_psrai_w:
9850 case Intrinsic::x86_mmx_psrai_d: {
9851 SDValue ShAmt = Op.getOperand(2);
9852 if (isa<ConstantSDNode>(ShAmt))
9855 unsigned NewIntNo = 0;
9857 case Intrinsic::x86_mmx_pslli_w:
9858 NewIntNo = Intrinsic::x86_mmx_psll_w;
9860 case Intrinsic::x86_mmx_pslli_d:
9861 NewIntNo = Intrinsic::x86_mmx_psll_d;
9863 case Intrinsic::x86_mmx_pslli_q:
9864 NewIntNo = Intrinsic::x86_mmx_psll_q;
9866 case Intrinsic::x86_mmx_psrli_w:
9867 NewIntNo = Intrinsic::x86_mmx_psrl_w;
9869 case Intrinsic::x86_mmx_psrli_d:
9870 NewIntNo = Intrinsic::x86_mmx_psrl_d;
9872 case Intrinsic::x86_mmx_psrli_q:
9873 NewIntNo = Intrinsic::x86_mmx_psrl_q;
9875 case Intrinsic::x86_mmx_psrai_w:
9876 NewIntNo = Intrinsic::x86_mmx_psra_w;
9878 case Intrinsic::x86_mmx_psrai_d:
9879 NewIntNo = Intrinsic::x86_mmx_psra_d;
9881 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
9884 // The vector shift intrinsics with scalars uses 32b shift amounts but
9885 // the sse2/mmx shift instructions reads 64 bits. Set the upper 32 bits
9887 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2i32, ShAmt,
9888 DAG.getConstant(0, MVT::i32));
9889 // FIXME this must be lowered to get rid of the invalid type.
9891 EVT VT = Op.getValueType();
9892 ShAmt = DAG.getNode(ISD::BITCAST, dl, VT, ShAmt);
9893 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
9894 DAG.getConstant(NewIntNo, MVT::i32),
9895 Op.getOperand(1), ShAmt);
9900 SDValue X86TargetLowering::LowerRETURNADDR(SDValue Op,
9901 SelectionDAG &DAG) const {
9902 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
9903 MFI->setReturnAddressIsTaken(true);
9905 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
9906 DebugLoc dl = Op.getDebugLoc();
9909 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
9911 DAG.getConstant(TD->getPointerSize(),
9912 Subtarget->is64Bit() ? MVT::i64 : MVT::i32);
9913 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(),
9914 DAG.getNode(ISD::ADD, dl, getPointerTy(),
9916 MachinePointerInfo(), false, false, false, 0);
9919 // Just load the return address.
9920 SDValue RetAddrFI = getReturnAddressFrameIndex(DAG);
9921 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(),
9922 RetAddrFI, MachinePointerInfo(), false, false, false, 0);
9925 SDValue X86TargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {
9926 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
9927 MFI->setFrameAddressIsTaken(true);
9929 EVT VT = Op.getValueType();
9930 DebugLoc dl = Op.getDebugLoc(); // FIXME probably not meaningful
9931 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
9932 unsigned FrameReg = Subtarget->is64Bit() ? X86::RBP : X86::EBP;
9933 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT);
9935 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr,
9936 MachinePointerInfo(),
9937 false, false, false, 0);
9941 SDValue X86TargetLowering::LowerFRAME_TO_ARGS_OFFSET(SDValue Op,
9942 SelectionDAG &DAG) const {
9943 return DAG.getIntPtrConstant(2*TD->getPointerSize());
9946 SDValue X86TargetLowering::LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const {
9947 MachineFunction &MF = DAG.getMachineFunction();
9948 SDValue Chain = Op.getOperand(0);
9949 SDValue Offset = Op.getOperand(1);
9950 SDValue Handler = Op.getOperand(2);
9951 DebugLoc dl = Op.getDebugLoc();
9953 SDValue Frame = DAG.getCopyFromReg(DAG.getEntryNode(), dl,
9954 Subtarget->is64Bit() ? X86::RBP : X86::EBP,
9956 unsigned StoreAddrReg = (Subtarget->is64Bit() ? X86::RCX : X86::ECX);
9958 SDValue StoreAddr = DAG.getNode(ISD::ADD, dl, getPointerTy(), Frame,
9959 DAG.getIntPtrConstant(TD->getPointerSize()));
9960 StoreAddr = DAG.getNode(ISD::ADD, dl, getPointerTy(), StoreAddr, Offset);
9961 Chain = DAG.getStore(Chain, dl, Handler, StoreAddr, MachinePointerInfo(),
9963 Chain = DAG.getCopyToReg(Chain, dl, StoreAddrReg, StoreAddr);
9964 MF.getRegInfo().addLiveOut(StoreAddrReg);
9966 return DAG.getNode(X86ISD::EH_RETURN, dl,
9968 Chain, DAG.getRegister(StoreAddrReg, getPointerTy()));
9971 SDValue X86TargetLowering::LowerADJUST_TRAMPOLINE(SDValue Op,
9972 SelectionDAG &DAG) const {
9973 return Op.getOperand(0);
9976 SDValue X86TargetLowering::LowerINIT_TRAMPOLINE(SDValue Op,
9977 SelectionDAG &DAG) const {
9978 SDValue Root = Op.getOperand(0);
9979 SDValue Trmp = Op.getOperand(1); // trampoline
9980 SDValue FPtr = Op.getOperand(2); // nested function
9981 SDValue Nest = Op.getOperand(3); // 'nest' parameter value
9982 DebugLoc dl = Op.getDebugLoc();
9984 const Value *TrmpAddr = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
9986 if (Subtarget->is64Bit()) {
9987 SDValue OutChains[6];
9989 // Large code-model.
9990 const unsigned char JMP64r = 0xFF; // 64-bit jmp through register opcode.
9991 const unsigned char MOV64ri = 0xB8; // X86::MOV64ri opcode.
9993 const unsigned char N86R10 = X86_MC::getX86RegNum(X86::R10);
9994 const unsigned char N86R11 = X86_MC::getX86RegNum(X86::R11);
9996 const unsigned char REX_WB = 0x40 | 0x08 | 0x01; // REX prefix
9998 // Load the pointer to the nested function into R11.
9999 unsigned OpCode = ((MOV64ri | N86R11) << 8) | REX_WB; // movabsq r11
10000 SDValue Addr = Trmp;
10001 OutChains[0] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
10002 Addr, MachinePointerInfo(TrmpAddr),
10005 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
10006 DAG.getConstant(2, MVT::i64));
10007 OutChains[1] = DAG.getStore(Root, dl, FPtr, Addr,
10008 MachinePointerInfo(TrmpAddr, 2),
10011 // Load the 'nest' parameter value into R10.
10012 // R10 is specified in X86CallingConv.td
10013 OpCode = ((MOV64ri | N86R10) << 8) | REX_WB; // movabsq r10
10014 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
10015 DAG.getConstant(10, MVT::i64));
10016 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
10017 Addr, MachinePointerInfo(TrmpAddr, 10),
10020 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
10021 DAG.getConstant(12, MVT::i64));
10022 OutChains[3] = DAG.getStore(Root, dl, Nest, Addr,
10023 MachinePointerInfo(TrmpAddr, 12),
10026 // Jump to the nested function.
10027 OpCode = (JMP64r << 8) | REX_WB; // jmpq *...
10028 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
10029 DAG.getConstant(20, MVT::i64));
10030 OutChains[4] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
10031 Addr, MachinePointerInfo(TrmpAddr, 20),
10034 unsigned char ModRM = N86R11 | (4 << 3) | (3 << 6); // ...r11
10035 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
10036 DAG.getConstant(22, MVT::i64));
10037 OutChains[5] = DAG.getStore(Root, dl, DAG.getConstant(ModRM, MVT::i8), Addr,
10038 MachinePointerInfo(TrmpAddr, 22),
10041 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains, 6);
10043 const Function *Func =
10044 cast<Function>(cast<SrcValueSDNode>(Op.getOperand(5))->getValue());
10045 CallingConv::ID CC = Func->getCallingConv();
10050 llvm_unreachable("Unsupported calling convention");
10051 case CallingConv::C:
10052 case CallingConv::X86_StdCall: {
10053 // Pass 'nest' parameter in ECX.
10054 // Must be kept in sync with X86CallingConv.td
10055 NestReg = X86::ECX;
10057 // Check that ECX wasn't needed by an 'inreg' parameter.
10058 FunctionType *FTy = Func->getFunctionType();
10059 const AttrListPtr &Attrs = Func->getAttributes();
10061 if (!Attrs.isEmpty() && !Func->isVarArg()) {
10062 unsigned InRegCount = 0;
10065 for (FunctionType::param_iterator I = FTy->param_begin(),
10066 E = FTy->param_end(); I != E; ++I, ++Idx)
10067 if (Attrs.paramHasAttr(Idx, Attribute::InReg))
10068 // FIXME: should only count parameters that are lowered to integers.
10069 InRegCount += (TD->getTypeSizeInBits(*I) + 31) / 32;
10071 if (InRegCount > 2) {
10072 report_fatal_error("Nest register in use - reduce number of inreg"
10078 case CallingConv::X86_FastCall:
10079 case CallingConv::X86_ThisCall:
10080 case CallingConv::Fast:
10081 // Pass 'nest' parameter in EAX.
10082 // Must be kept in sync with X86CallingConv.td
10083 NestReg = X86::EAX;
10087 SDValue OutChains[4];
10088 SDValue Addr, Disp;
10090 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
10091 DAG.getConstant(10, MVT::i32));
10092 Disp = DAG.getNode(ISD::SUB, dl, MVT::i32, FPtr, Addr);
10094 // This is storing the opcode for MOV32ri.
10095 const unsigned char MOV32ri = 0xB8; // X86::MOV32ri's opcode byte.
10096 const unsigned char N86Reg = X86_MC::getX86RegNum(NestReg);
10097 OutChains[0] = DAG.getStore(Root, dl,
10098 DAG.getConstant(MOV32ri|N86Reg, MVT::i8),
10099 Trmp, MachinePointerInfo(TrmpAddr),
10102 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
10103 DAG.getConstant(1, MVT::i32));
10104 OutChains[1] = DAG.getStore(Root, dl, Nest, Addr,
10105 MachinePointerInfo(TrmpAddr, 1),
10108 const unsigned char JMP = 0xE9; // jmp <32bit dst> opcode.
10109 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
10110 DAG.getConstant(5, MVT::i32));
10111 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(JMP, MVT::i8), Addr,
10112 MachinePointerInfo(TrmpAddr, 5),
10115 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
10116 DAG.getConstant(6, MVT::i32));
10117 OutChains[3] = DAG.getStore(Root, dl, Disp, Addr,
10118 MachinePointerInfo(TrmpAddr, 6),
10121 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains, 4);
10125 SDValue X86TargetLowering::LowerFLT_ROUNDS_(SDValue Op,
10126 SelectionDAG &DAG) const {
10128 The rounding mode is in bits 11:10 of FPSR, and has the following
10130 00 Round to nearest
10135 FLT_ROUNDS, on the other hand, expects the following:
10142 To perform the conversion, we do:
10143 (((((FPSR & 0x800) >> 11) | ((FPSR & 0x400) >> 9)) + 1) & 3)
10146 MachineFunction &MF = DAG.getMachineFunction();
10147 const TargetMachine &TM = MF.getTarget();
10148 const TargetFrameLowering &TFI = *TM.getFrameLowering();
10149 unsigned StackAlignment = TFI.getStackAlignment();
10150 EVT VT = Op.getValueType();
10151 DebugLoc DL = Op.getDebugLoc();
10153 // Save FP Control Word to stack slot
10154 int SSFI = MF.getFrameInfo()->CreateStackObject(2, StackAlignment, false);
10155 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
10158 MachineMemOperand *MMO =
10159 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
10160 MachineMemOperand::MOStore, 2, 2);
10162 SDValue Ops[] = { DAG.getEntryNode(), StackSlot };
10163 SDValue Chain = DAG.getMemIntrinsicNode(X86ISD::FNSTCW16m, DL,
10164 DAG.getVTList(MVT::Other),
10165 Ops, 2, MVT::i16, MMO);
10167 // Load FP Control Word from stack slot
10168 SDValue CWD = DAG.getLoad(MVT::i16, DL, Chain, StackSlot,
10169 MachinePointerInfo(), false, false, false, 0);
10171 // Transform as necessary
10173 DAG.getNode(ISD::SRL, DL, MVT::i16,
10174 DAG.getNode(ISD::AND, DL, MVT::i16,
10175 CWD, DAG.getConstant(0x800, MVT::i16)),
10176 DAG.getConstant(11, MVT::i8));
10178 DAG.getNode(ISD::SRL, DL, MVT::i16,
10179 DAG.getNode(ISD::AND, DL, MVT::i16,
10180 CWD, DAG.getConstant(0x400, MVT::i16)),
10181 DAG.getConstant(9, MVT::i8));
10184 DAG.getNode(ISD::AND, DL, MVT::i16,
10185 DAG.getNode(ISD::ADD, DL, MVT::i16,
10186 DAG.getNode(ISD::OR, DL, MVT::i16, CWD1, CWD2),
10187 DAG.getConstant(1, MVT::i16)),
10188 DAG.getConstant(3, MVT::i16));
10191 return DAG.getNode((VT.getSizeInBits() < 16 ?
10192 ISD::TRUNCATE : ISD::ZERO_EXTEND), DL, VT, RetVal);
10195 SDValue X86TargetLowering::LowerCTLZ(SDValue Op, SelectionDAG &DAG) const {
10196 EVT VT = Op.getValueType();
10198 unsigned NumBits = VT.getSizeInBits();
10199 DebugLoc dl = Op.getDebugLoc();
10201 Op = Op.getOperand(0);
10202 if (VT == MVT::i8) {
10203 // Zero extend to i32 since there is not an i8 bsr.
10205 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
10208 // Issue a bsr (scan bits in reverse) which also sets EFLAGS.
10209 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
10210 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
10212 // If src is zero (i.e. bsr sets ZF), returns NumBits.
10215 DAG.getConstant(NumBits+NumBits-1, OpVT),
10216 DAG.getConstant(X86::COND_E, MVT::i8),
10219 Op = DAG.getNode(X86ISD::CMOV, dl, OpVT, Ops, array_lengthof(Ops));
10221 // Finally xor with NumBits-1.
10222 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT));
10225 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
10229 SDValue X86TargetLowering::LowerCTLZ_ZERO_UNDEF(SDValue Op,
10230 SelectionDAG &DAG) const {
10231 EVT VT = Op.getValueType();
10233 unsigned NumBits = VT.getSizeInBits();
10234 DebugLoc dl = Op.getDebugLoc();
10236 Op = Op.getOperand(0);
10237 if (VT == MVT::i8) {
10238 // Zero extend to i32 since there is not an i8 bsr.
10240 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
10243 // Issue a bsr (scan bits in reverse).
10244 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
10245 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
10247 // And xor with NumBits-1.
10248 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT));
10251 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
10255 SDValue X86TargetLowering::LowerCTTZ(SDValue Op, SelectionDAG &DAG) const {
10256 EVT VT = Op.getValueType();
10257 unsigned NumBits = VT.getSizeInBits();
10258 DebugLoc dl = Op.getDebugLoc();
10259 Op = Op.getOperand(0);
10261 // Issue a bsf (scan bits forward) which also sets EFLAGS.
10262 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
10263 Op = DAG.getNode(X86ISD::BSF, dl, VTs, Op);
10265 // If src is zero (i.e. bsf sets ZF), returns NumBits.
10268 DAG.getConstant(NumBits, VT),
10269 DAG.getConstant(X86::COND_E, MVT::i8),
10272 return DAG.getNode(X86ISD::CMOV, dl, VT, Ops, array_lengthof(Ops));
10275 // Lower256IntArith - Break a 256-bit integer operation into two new 128-bit
10276 // ones, and then concatenate the result back.
10277 static SDValue Lower256IntArith(SDValue Op, SelectionDAG &DAG) {
10278 EVT VT = Op.getValueType();
10280 assert(VT.getSizeInBits() == 256 && VT.isInteger() &&
10281 "Unsupported value type for operation");
10283 unsigned NumElems = VT.getVectorNumElements();
10284 DebugLoc dl = Op.getDebugLoc();
10286 // Extract the LHS vectors
10287 SDValue LHS = Op.getOperand(0);
10288 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
10289 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
10291 // Extract the RHS vectors
10292 SDValue RHS = Op.getOperand(1);
10293 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, dl);
10294 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, dl);
10296 MVT EltVT = VT.getVectorElementType().getSimpleVT();
10297 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
10299 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
10300 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1),
10301 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2));
10304 SDValue X86TargetLowering::LowerADD(SDValue Op, SelectionDAG &DAG) const {
10305 assert(Op.getValueType().getSizeInBits() == 256 &&
10306 Op.getValueType().isInteger() &&
10307 "Only handle AVX 256-bit vector integer operation");
10308 return Lower256IntArith(Op, DAG);
10311 SDValue X86TargetLowering::LowerSUB(SDValue Op, SelectionDAG &DAG) const {
10312 assert(Op.getValueType().getSizeInBits() == 256 &&
10313 Op.getValueType().isInteger() &&
10314 "Only handle AVX 256-bit vector integer operation");
10315 return Lower256IntArith(Op, DAG);
10318 SDValue X86TargetLowering::LowerMUL(SDValue Op, SelectionDAG &DAG) const {
10319 EVT VT = Op.getValueType();
10321 // Decompose 256-bit ops into smaller 128-bit ops.
10322 if (VT.getSizeInBits() == 256 && !Subtarget->hasAVX2())
10323 return Lower256IntArith(Op, DAG);
10325 assert((VT == MVT::v2i64 || VT == MVT::v4i64) &&
10326 "Only know how to lower V2I64/V4I64 multiply");
10328 DebugLoc dl = Op.getDebugLoc();
10330 // Ahi = psrlqi(a, 32);
10331 // Bhi = psrlqi(b, 32);
10333 // AloBlo = pmuludq(a, b);
10334 // AloBhi = pmuludq(a, Bhi);
10335 // AhiBlo = pmuludq(Ahi, b);
10337 // AloBhi = psllqi(AloBhi, 32);
10338 // AhiBlo = psllqi(AhiBlo, 32);
10339 // return AloBlo + AloBhi + AhiBlo;
10341 SDValue A = Op.getOperand(0);
10342 SDValue B = Op.getOperand(1);
10344 SDValue ShAmt = DAG.getConstant(32, MVT::i32);
10346 SDValue Ahi = DAG.getNode(X86ISD::VSRLI, dl, VT, A, ShAmt);
10347 SDValue Bhi = DAG.getNode(X86ISD::VSRLI, dl, VT, B, ShAmt);
10349 // Bit cast to 32-bit vectors for MULUDQ
10350 EVT MulVT = (VT == MVT::v2i64) ? MVT::v4i32 : MVT::v8i32;
10351 A = DAG.getNode(ISD::BITCAST, dl, MulVT, A);
10352 B = DAG.getNode(ISD::BITCAST, dl, MulVT, B);
10353 Ahi = DAG.getNode(ISD::BITCAST, dl, MulVT, Ahi);
10354 Bhi = DAG.getNode(ISD::BITCAST, dl, MulVT, Bhi);
10356 SDValue AloBlo = DAG.getNode(X86ISD::PMULUDQ, dl, VT, A, B);
10357 SDValue AloBhi = DAG.getNode(X86ISD::PMULUDQ, dl, VT, A, Bhi);
10358 SDValue AhiBlo = DAG.getNode(X86ISD::PMULUDQ, dl, VT, Ahi, B);
10360 AloBhi = DAG.getNode(X86ISD::VSHLI, dl, VT, AloBhi, ShAmt);
10361 AhiBlo = DAG.getNode(X86ISD::VSHLI, dl, VT, AhiBlo, ShAmt);
10363 SDValue Res = DAG.getNode(ISD::ADD, dl, VT, AloBlo, AloBhi);
10364 return DAG.getNode(ISD::ADD, dl, VT, Res, AhiBlo);
10367 SDValue X86TargetLowering::LowerShift(SDValue Op, SelectionDAG &DAG) const {
10369 EVT VT = Op.getValueType();
10370 DebugLoc dl = Op.getDebugLoc();
10371 SDValue R = Op.getOperand(0);
10372 SDValue Amt = Op.getOperand(1);
10373 LLVMContext *Context = DAG.getContext();
10375 if (!Subtarget->hasSSE2())
10378 // Optimize shl/srl/sra with constant shift amount.
10379 if (isSplatVector(Amt.getNode())) {
10380 SDValue SclrAmt = Amt->getOperand(0);
10381 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(SclrAmt)) {
10382 uint64_t ShiftAmt = C->getZExtValue();
10384 if (VT == MVT::v2i64 || VT == MVT::v4i32 || VT == MVT::v8i16 ||
10385 (Subtarget->hasAVX2() &&
10386 (VT == MVT::v4i64 || VT == MVT::v8i32 || VT == MVT::v16i16))) {
10387 if (Op.getOpcode() == ISD::SHL)
10388 return DAG.getNode(X86ISD::VSHLI, dl, VT, R,
10389 DAG.getConstant(ShiftAmt, MVT::i32));
10390 if (Op.getOpcode() == ISD::SRL)
10391 return DAG.getNode(X86ISD::VSRLI, dl, VT, R,
10392 DAG.getConstant(ShiftAmt, MVT::i32));
10393 if (Op.getOpcode() == ISD::SRA && VT != MVT::v2i64 && VT != MVT::v4i64)
10394 return DAG.getNode(X86ISD::VSRAI, dl, VT, R,
10395 DAG.getConstant(ShiftAmt, MVT::i32));
10398 if (VT == MVT::v16i8) {
10399 if (Op.getOpcode() == ISD::SHL) {
10400 // Make a large shift.
10401 SDValue SHL = DAG.getNode(X86ISD::VSHLI, dl, MVT::v8i16, R,
10402 DAG.getConstant(ShiftAmt, MVT::i32));
10403 SHL = DAG.getNode(ISD::BITCAST, dl, VT, SHL);
10404 // Zero out the rightmost bits.
10405 SmallVector<SDValue, 16> V(16,
10406 DAG.getConstant(uint8_t(-1U << ShiftAmt),
10408 return DAG.getNode(ISD::AND, dl, VT, SHL,
10409 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 16));
10411 if (Op.getOpcode() == ISD::SRL) {
10412 // Make a large shift.
10413 SDValue SRL = DAG.getNode(X86ISD::VSRLI, dl, MVT::v8i16, R,
10414 DAG.getConstant(ShiftAmt, MVT::i32));
10415 SRL = DAG.getNode(ISD::BITCAST, dl, VT, SRL);
10416 // Zero out the leftmost bits.
10417 SmallVector<SDValue, 16> V(16,
10418 DAG.getConstant(uint8_t(-1U) >> ShiftAmt,
10420 return DAG.getNode(ISD::AND, dl, VT, SRL,
10421 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 16));
10423 if (Op.getOpcode() == ISD::SRA) {
10424 if (ShiftAmt == 7) {
10425 // R s>> 7 === R s< 0
10426 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
10427 return DAG.getNode(X86ISD::PCMPGT, dl, VT, Zeros, R);
10430 // R s>> a === ((R u>> a) ^ m) - m
10431 SDValue Res = DAG.getNode(ISD::SRL, dl, VT, R, Amt);
10432 SmallVector<SDValue, 16> V(16, DAG.getConstant(128 >> ShiftAmt,
10434 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 16);
10435 Res = DAG.getNode(ISD::XOR, dl, VT, Res, Mask);
10436 Res = DAG.getNode(ISD::SUB, dl, VT, Res, Mask);
10439 llvm_unreachable("Unknown shift opcode.");
10442 if (Subtarget->hasAVX2() && VT == MVT::v32i8) {
10443 if (Op.getOpcode() == ISD::SHL) {
10444 // Make a large shift.
10445 SDValue SHL = DAG.getNode(X86ISD::VSHLI, dl, MVT::v16i16, R,
10446 DAG.getConstant(ShiftAmt, MVT::i32));
10447 SHL = DAG.getNode(ISD::BITCAST, dl, VT, SHL);
10448 // Zero out the rightmost bits.
10449 SmallVector<SDValue, 32> V(32,
10450 DAG.getConstant(uint8_t(-1U << ShiftAmt),
10452 return DAG.getNode(ISD::AND, dl, VT, SHL,
10453 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 32));
10455 if (Op.getOpcode() == ISD::SRL) {
10456 // Make a large shift.
10457 SDValue SRL = DAG.getNode(X86ISD::VSRLI, dl, MVT::v16i16, R,
10458 DAG.getConstant(ShiftAmt, MVT::i32));
10459 SRL = DAG.getNode(ISD::BITCAST, dl, VT, SRL);
10460 // Zero out the leftmost bits.
10461 SmallVector<SDValue, 32> V(32,
10462 DAG.getConstant(uint8_t(-1U) >> ShiftAmt,
10464 return DAG.getNode(ISD::AND, dl, VT, SRL,
10465 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 32));
10467 if (Op.getOpcode() == ISD::SRA) {
10468 if (ShiftAmt == 7) {
10469 // R s>> 7 === R s< 0
10470 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
10471 return DAG.getNode(X86ISD::PCMPGT, dl, VT, Zeros, R);
10474 // R s>> a === ((R u>> a) ^ m) - m
10475 SDValue Res = DAG.getNode(ISD::SRL, dl, VT, R, Amt);
10476 SmallVector<SDValue, 32> V(32, DAG.getConstant(128 >> ShiftAmt,
10478 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 32);
10479 Res = DAG.getNode(ISD::XOR, dl, VT, Res, Mask);
10480 Res = DAG.getNode(ISD::SUB, dl, VT, Res, Mask);
10483 llvm_unreachable("Unknown shift opcode.");
10488 // Lower SHL with variable shift amount.
10489 if (VT == MVT::v4i32 && Op->getOpcode() == ISD::SHL) {
10490 Op = DAG.getNode(X86ISD::VSHLI, dl, VT, Op.getOperand(1),
10491 DAG.getConstant(23, MVT::i32));
10493 const uint32_t CV[] = { 0x3f800000U, 0x3f800000U, 0x3f800000U, 0x3f800000U};
10494 Constant *C = ConstantDataVector::get(*Context, CV);
10495 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
10496 SDValue Addend = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
10497 MachinePointerInfo::getConstantPool(),
10498 false, false, false, 16);
10500 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Addend);
10501 Op = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, Op);
10502 Op = DAG.getNode(ISD::FP_TO_SINT, dl, VT, Op);
10503 return DAG.getNode(ISD::MUL, dl, VT, Op, R);
10505 if (VT == MVT::v16i8 && Op->getOpcode() == ISD::SHL) {
10506 assert(Subtarget->hasSSE2() && "Need SSE2 for pslli/pcmpeq.");
10509 Op = DAG.getNode(X86ISD::VSHLI, dl, MVT::v8i16, Op.getOperand(1),
10510 DAG.getConstant(5, MVT::i32));
10511 Op = DAG.getNode(ISD::BITCAST, dl, VT, Op);
10513 // Turn 'a' into a mask suitable for VSELECT
10514 SDValue VSelM = DAG.getConstant(0x80, VT);
10515 SDValue OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
10516 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
10518 SDValue CM1 = DAG.getConstant(0x0f, VT);
10519 SDValue CM2 = DAG.getConstant(0x3f, VT);
10521 // r = VSELECT(r, psllw(r & (char16)15, 4), a);
10522 SDValue M = DAG.getNode(ISD::AND, dl, VT, R, CM1);
10523 M = getTargetVShiftNode(X86ISD::VSHLI, dl, MVT::v8i16, M,
10524 DAG.getConstant(4, MVT::i32), DAG);
10525 M = DAG.getNode(ISD::BITCAST, dl, VT, M);
10526 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel, M, R);
10529 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op);
10530 OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
10531 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
10533 // r = VSELECT(r, psllw(r & (char16)63, 2), a);
10534 M = DAG.getNode(ISD::AND, dl, VT, R, CM2);
10535 M = getTargetVShiftNode(X86ISD::VSHLI, dl, MVT::v8i16, M,
10536 DAG.getConstant(2, MVT::i32), DAG);
10537 M = DAG.getNode(ISD::BITCAST, dl, VT, M);
10538 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel, M, R);
10541 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op);
10542 OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
10543 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
10545 // return VSELECT(r, r+r, a);
10546 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel,
10547 DAG.getNode(ISD::ADD, dl, VT, R, R), R);
10551 // Decompose 256-bit shifts into smaller 128-bit shifts.
10552 if (VT.getSizeInBits() == 256) {
10553 unsigned NumElems = VT.getVectorNumElements();
10554 MVT EltVT = VT.getVectorElementType().getSimpleVT();
10555 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
10557 // Extract the two vectors
10558 SDValue V1 = Extract128BitVector(R, 0, DAG, dl);
10559 SDValue V2 = Extract128BitVector(R, NumElems/2, DAG, dl);
10561 // Recreate the shift amount vectors
10562 SDValue Amt1, Amt2;
10563 if (Amt.getOpcode() == ISD::BUILD_VECTOR) {
10564 // Constant shift amount
10565 SmallVector<SDValue, 4> Amt1Csts;
10566 SmallVector<SDValue, 4> Amt2Csts;
10567 for (unsigned i = 0; i != NumElems/2; ++i)
10568 Amt1Csts.push_back(Amt->getOperand(i));
10569 for (unsigned i = NumElems/2; i != NumElems; ++i)
10570 Amt2Csts.push_back(Amt->getOperand(i));
10572 Amt1 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT,
10573 &Amt1Csts[0], NumElems/2);
10574 Amt2 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT,
10575 &Amt2Csts[0], NumElems/2);
10577 // Variable shift amount
10578 Amt1 = Extract128BitVector(Amt, 0, DAG, dl);
10579 Amt2 = Extract128BitVector(Amt, NumElems/2, DAG, dl);
10582 // Issue new vector shifts for the smaller types
10583 V1 = DAG.getNode(Op.getOpcode(), dl, NewVT, V1, Amt1);
10584 V2 = DAG.getNode(Op.getOpcode(), dl, NewVT, V2, Amt2);
10586 // Concatenate the result back
10587 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, V1, V2);
10593 SDValue X86TargetLowering::LowerXALUO(SDValue Op, SelectionDAG &DAG) const {
10594 // Lower the "add/sub/mul with overflow" instruction into a regular ins plus
10595 // a "setcc" instruction that checks the overflow flag. The "brcond" lowering
10596 // looks for this combo and may remove the "setcc" instruction if the "setcc"
10597 // has only one use.
10598 SDNode *N = Op.getNode();
10599 SDValue LHS = N->getOperand(0);
10600 SDValue RHS = N->getOperand(1);
10601 unsigned BaseOp = 0;
10603 DebugLoc DL = Op.getDebugLoc();
10604 switch (Op.getOpcode()) {
10605 default: llvm_unreachable("Unknown ovf instruction!");
10607 // A subtract of one will be selected as a INC. Note that INC doesn't
10608 // set CF, so we can't do this for UADDO.
10609 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
10611 BaseOp = X86ISD::INC;
10612 Cond = X86::COND_O;
10615 BaseOp = X86ISD::ADD;
10616 Cond = X86::COND_O;
10619 BaseOp = X86ISD::ADD;
10620 Cond = X86::COND_B;
10623 // A subtract of one will be selected as a DEC. Note that DEC doesn't
10624 // set CF, so we can't do this for USUBO.
10625 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
10627 BaseOp = X86ISD::DEC;
10628 Cond = X86::COND_O;
10631 BaseOp = X86ISD::SUB;
10632 Cond = X86::COND_O;
10635 BaseOp = X86ISD::SUB;
10636 Cond = X86::COND_B;
10639 BaseOp = X86ISD::SMUL;
10640 Cond = X86::COND_O;
10642 case ISD::UMULO: { // i64, i8 = umulo lhs, rhs --> i64, i64, i32 umul lhs,rhs
10643 SDVTList VTs = DAG.getVTList(N->getValueType(0), N->getValueType(0),
10645 SDValue Sum = DAG.getNode(X86ISD::UMUL, DL, VTs, LHS, RHS);
10648 DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
10649 DAG.getConstant(X86::COND_O, MVT::i32),
10650 SDValue(Sum.getNode(), 2));
10652 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
10656 // Also sets EFLAGS.
10657 SDVTList VTs = DAG.getVTList(N->getValueType(0), MVT::i32);
10658 SDValue Sum = DAG.getNode(BaseOp, DL, VTs, LHS, RHS);
10661 DAG.getNode(X86ISD::SETCC, DL, N->getValueType(1),
10662 DAG.getConstant(Cond, MVT::i32),
10663 SDValue(Sum.getNode(), 1));
10665 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
10668 SDValue X86TargetLowering::LowerSIGN_EXTEND_INREG(SDValue Op,
10669 SelectionDAG &DAG) const {
10670 DebugLoc dl = Op.getDebugLoc();
10671 EVT ExtraVT = cast<VTSDNode>(Op.getOperand(1))->getVT();
10672 EVT VT = Op.getValueType();
10674 if (!Subtarget->hasSSE2() || !VT.isVector())
10677 unsigned BitsDiff = VT.getScalarType().getSizeInBits() -
10678 ExtraVT.getScalarType().getSizeInBits();
10679 SDValue ShAmt = DAG.getConstant(BitsDiff, MVT::i32);
10681 switch (VT.getSimpleVT().SimpleTy) {
10682 default: return SDValue();
10685 if (!Subtarget->hasAVX())
10687 if (!Subtarget->hasAVX2()) {
10688 // needs to be split
10689 unsigned NumElems = VT.getVectorNumElements();
10691 // Extract the LHS vectors
10692 SDValue LHS = Op.getOperand(0);
10693 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
10694 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
10696 MVT EltVT = VT.getVectorElementType().getSimpleVT();
10697 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
10699 EVT ExtraEltVT = ExtraVT.getVectorElementType();
10700 unsigned ExtraNumElems = ExtraVT.getVectorNumElements();
10701 ExtraVT = EVT::getVectorVT(*DAG.getContext(), ExtraEltVT,
10703 SDValue Extra = DAG.getValueType(ExtraVT);
10705 LHS1 = DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, Extra);
10706 LHS2 = DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, Extra);
10708 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, LHS1, LHS2);;
10713 SDValue Tmp1 = getTargetVShiftNode(X86ISD::VSHLI, dl, VT,
10714 Op.getOperand(0), ShAmt, DAG);
10715 return getTargetVShiftNode(X86ISD::VSRAI, dl, VT, Tmp1, ShAmt, DAG);
10721 SDValue X86TargetLowering::LowerMEMBARRIER(SDValue Op, SelectionDAG &DAG) const{
10722 DebugLoc dl = Op.getDebugLoc();
10724 // Go ahead and emit the fence on x86-64 even if we asked for no-sse2.
10725 // There isn't any reason to disable it if the target processor supports it.
10726 if (!Subtarget->hasSSE2() && !Subtarget->is64Bit()) {
10727 SDValue Chain = Op.getOperand(0);
10728 SDValue Zero = DAG.getConstant(0, MVT::i32);
10730 DAG.getRegister(X86::ESP, MVT::i32), // Base
10731 DAG.getTargetConstant(1, MVT::i8), // Scale
10732 DAG.getRegister(0, MVT::i32), // Index
10733 DAG.getTargetConstant(0, MVT::i32), // Disp
10734 DAG.getRegister(0, MVT::i32), // Segment.
10739 DAG.getMachineNode(X86::OR32mrLocked, dl, MVT::Other, Ops,
10740 array_lengthof(Ops));
10741 return SDValue(Res, 0);
10744 unsigned isDev = cast<ConstantSDNode>(Op.getOperand(5))->getZExtValue();
10746 return DAG.getNode(X86ISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0));
10748 unsigned Op1 = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
10749 unsigned Op2 = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue();
10750 unsigned Op3 = cast<ConstantSDNode>(Op.getOperand(3))->getZExtValue();
10751 unsigned Op4 = cast<ConstantSDNode>(Op.getOperand(4))->getZExtValue();
10753 // def : Pat<(membarrier (i8 0), (i8 0), (i8 0), (i8 1), (i8 1)), (SFENCE)>;
10754 if (!Op1 && !Op2 && !Op3 && Op4)
10755 return DAG.getNode(X86ISD::SFENCE, dl, MVT::Other, Op.getOperand(0));
10757 // def : Pat<(membarrier (i8 1), (i8 0), (i8 0), (i8 0), (i8 1)), (LFENCE)>;
10758 if (Op1 && !Op2 && !Op3 && !Op4)
10759 return DAG.getNode(X86ISD::LFENCE, dl, MVT::Other, Op.getOperand(0));
10761 // def : Pat<(membarrier (i8 imm), (i8 imm), (i8 imm), (i8 imm), (i8 1)),
10763 return DAG.getNode(X86ISD::MFENCE, dl, MVT::Other, Op.getOperand(0));
10766 SDValue X86TargetLowering::LowerATOMIC_FENCE(SDValue Op,
10767 SelectionDAG &DAG) const {
10768 DebugLoc dl = Op.getDebugLoc();
10769 AtomicOrdering FenceOrdering = static_cast<AtomicOrdering>(
10770 cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue());
10771 SynchronizationScope FenceScope = static_cast<SynchronizationScope>(
10772 cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue());
10774 // The only fence that needs an instruction is a sequentially-consistent
10775 // cross-thread fence.
10776 if (FenceOrdering == SequentiallyConsistent && FenceScope == CrossThread) {
10777 // Use mfence if we have SSE2 or we're on x86-64 (even if we asked for
10778 // no-sse2). There isn't any reason to disable it if the target processor
10780 if (Subtarget->hasSSE2() || Subtarget->is64Bit())
10781 return DAG.getNode(X86ISD::MFENCE, dl, MVT::Other, Op.getOperand(0));
10783 SDValue Chain = Op.getOperand(0);
10784 SDValue Zero = DAG.getConstant(0, MVT::i32);
10786 DAG.getRegister(X86::ESP, MVT::i32), // Base
10787 DAG.getTargetConstant(1, MVT::i8), // Scale
10788 DAG.getRegister(0, MVT::i32), // Index
10789 DAG.getTargetConstant(0, MVT::i32), // Disp
10790 DAG.getRegister(0, MVT::i32), // Segment.
10795 DAG.getMachineNode(X86::OR32mrLocked, dl, MVT::Other, Ops,
10796 array_lengthof(Ops));
10797 return SDValue(Res, 0);
10800 // MEMBARRIER is a compiler barrier; it codegens to a no-op.
10801 return DAG.getNode(X86ISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0));
10805 SDValue X86TargetLowering::LowerCMP_SWAP(SDValue Op, SelectionDAG &DAG) const {
10806 EVT T = Op.getValueType();
10807 DebugLoc DL = Op.getDebugLoc();
10810 switch(T.getSimpleVT().SimpleTy) {
10811 default: llvm_unreachable("Invalid value type!");
10812 case MVT::i8: Reg = X86::AL; size = 1; break;
10813 case MVT::i16: Reg = X86::AX; size = 2; break;
10814 case MVT::i32: Reg = X86::EAX; size = 4; break;
10816 assert(Subtarget->is64Bit() && "Node not type legal!");
10817 Reg = X86::RAX; size = 8;
10820 SDValue cpIn = DAG.getCopyToReg(Op.getOperand(0), DL, Reg,
10821 Op.getOperand(2), SDValue());
10822 SDValue Ops[] = { cpIn.getValue(0),
10825 DAG.getTargetConstant(size, MVT::i8),
10826 cpIn.getValue(1) };
10827 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
10828 MachineMemOperand *MMO = cast<AtomicSDNode>(Op)->getMemOperand();
10829 SDValue Result = DAG.getMemIntrinsicNode(X86ISD::LCMPXCHG_DAG, DL, Tys,
10832 DAG.getCopyFromReg(Result.getValue(0), DL, Reg, T, Result.getValue(1));
10836 SDValue X86TargetLowering::LowerREADCYCLECOUNTER(SDValue Op,
10837 SelectionDAG &DAG) const {
10838 assert(Subtarget->is64Bit() && "Result not type legalized?");
10839 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
10840 SDValue TheChain = Op.getOperand(0);
10841 DebugLoc dl = Op.getDebugLoc();
10842 SDValue rd = DAG.getNode(X86ISD::RDTSC_DAG, dl, Tys, &TheChain, 1);
10843 SDValue rax = DAG.getCopyFromReg(rd, dl, X86::RAX, MVT::i64, rd.getValue(1));
10844 SDValue rdx = DAG.getCopyFromReg(rax.getValue(1), dl, X86::RDX, MVT::i64,
10846 SDValue Tmp = DAG.getNode(ISD::SHL, dl, MVT::i64, rdx,
10847 DAG.getConstant(32, MVT::i8));
10849 DAG.getNode(ISD::OR, dl, MVT::i64, rax, Tmp),
10852 return DAG.getMergeValues(Ops, 2, dl);
10855 SDValue X86TargetLowering::LowerBITCAST(SDValue Op,
10856 SelectionDAG &DAG) const {
10857 EVT SrcVT = Op.getOperand(0).getValueType();
10858 EVT DstVT = Op.getValueType();
10859 assert(Subtarget->is64Bit() && !Subtarget->hasSSE2() &&
10860 Subtarget->hasMMX() && "Unexpected custom BITCAST");
10861 assert((DstVT == MVT::i64 ||
10862 (DstVT.isVector() && DstVT.getSizeInBits()==64)) &&
10863 "Unexpected custom BITCAST");
10864 // i64 <=> MMX conversions are Legal.
10865 if (SrcVT==MVT::i64 && DstVT.isVector())
10867 if (DstVT==MVT::i64 && SrcVT.isVector())
10869 // MMX <=> MMX conversions are Legal.
10870 if (SrcVT.isVector() && DstVT.isVector())
10872 // All other conversions need to be expanded.
10876 SDValue X86TargetLowering::LowerLOAD_SUB(SDValue Op, SelectionDAG &DAG) const {
10877 SDNode *Node = Op.getNode();
10878 DebugLoc dl = Node->getDebugLoc();
10879 EVT T = Node->getValueType(0);
10880 SDValue negOp = DAG.getNode(ISD::SUB, dl, T,
10881 DAG.getConstant(0, T), Node->getOperand(2));
10882 return DAG.getAtomic(ISD::ATOMIC_LOAD_ADD, dl,
10883 cast<AtomicSDNode>(Node)->getMemoryVT(),
10884 Node->getOperand(0),
10885 Node->getOperand(1), negOp,
10886 cast<AtomicSDNode>(Node)->getSrcValue(),
10887 cast<AtomicSDNode>(Node)->getAlignment(),
10888 cast<AtomicSDNode>(Node)->getOrdering(),
10889 cast<AtomicSDNode>(Node)->getSynchScope());
10892 static SDValue LowerATOMIC_STORE(SDValue Op, SelectionDAG &DAG) {
10893 SDNode *Node = Op.getNode();
10894 DebugLoc dl = Node->getDebugLoc();
10895 EVT VT = cast<AtomicSDNode>(Node)->getMemoryVT();
10897 // Convert seq_cst store -> xchg
10898 // Convert wide store -> swap (-> cmpxchg8b/cmpxchg16b)
10899 // FIXME: On 32-bit, store -> fist or movq would be more efficient
10900 // (The only way to get a 16-byte store is cmpxchg16b)
10901 // FIXME: 16-byte ATOMIC_SWAP isn't actually hooked up at the moment.
10902 if (cast<AtomicSDNode>(Node)->getOrdering() == SequentiallyConsistent ||
10903 !DAG.getTargetLoweringInfo().isTypeLegal(VT)) {
10904 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_SWAP, dl,
10905 cast<AtomicSDNode>(Node)->getMemoryVT(),
10906 Node->getOperand(0),
10907 Node->getOperand(1), Node->getOperand(2),
10908 cast<AtomicSDNode>(Node)->getMemOperand(),
10909 cast<AtomicSDNode>(Node)->getOrdering(),
10910 cast<AtomicSDNode>(Node)->getSynchScope());
10911 return Swap.getValue(1);
10913 // Other atomic stores have a simple pattern.
10917 static SDValue LowerADDC_ADDE_SUBC_SUBE(SDValue Op, SelectionDAG &DAG) {
10918 EVT VT = Op.getNode()->getValueType(0);
10920 // Let legalize expand this if it isn't a legal type yet.
10921 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
10924 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
10927 bool ExtraOp = false;
10928 switch (Op.getOpcode()) {
10929 default: llvm_unreachable("Invalid code");
10930 case ISD::ADDC: Opc = X86ISD::ADD; break;
10931 case ISD::ADDE: Opc = X86ISD::ADC; ExtraOp = true; break;
10932 case ISD::SUBC: Opc = X86ISD::SUB; break;
10933 case ISD::SUBE: Opc = X86ISD::SBB; ExtraOp = true; break;
10937 return DAG.getNode(Opc, Op->getDebugLoc(), VTs, Op.getOperand(0),
10939 return DAG.getNode(Opc, Op->getDebugLoc(), VTs, Op.getOperand(0),
10940 Op.getOperand(1), Op.getOperand(2));
10943 /// LowerOperation - Provide custom lowering hooks for some operations.
10945 SDValue X86TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
10946 switch (Op.getOpcode()) {
10947 default: llvm_unreachable("Should not custom lower this!");
10948 case ISD::SIGN_EXTEND_INREG: return LowerSIGN_EXTEND_INREG(Op,DAG);
10949 case ISD::MEMBARRIER: return LowerMEMBARRIER(Op,DAG);
10950 case ISD::ATOMIC_FENCE: return LowerATOMIC_FENCE(Op,DAG);
10951 case ISD::ATOMIC_CMP_SWAP: return LowerCMP_SWAP(Op,DAG);
10952 case ISD::ATOMIC_LOAD_SUB: return LowerLOAD_SUB(Op,DAG);
10953 case ISD::ATOMIC_STORE: return LowerATOMIC_STORE(Op,DAG);
10954 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
10955 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG);
10956 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
10957 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
10958 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG);
10959 case ISD::EXTRACT_SUBVECTOR: return LowerEXTRACT_SUBVECTOR(Op, DAG);
10960 case ISD::INSERT_SUBVECTOR: return LowerINSERT_SUBVECTOR(Op, DAG);
10961 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
10962 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
10963 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
10964 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
10965 case ISD::ExternalSymbol: return LowerExternalSymbol(Op, DAG);
10966 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
10967 case ISD::SHL_PARTS:
10968 case ISD::SRA_PARTS:
10969 case ISD::SRL_PARTS: return LowerShiftParts(Op, DAG);
10970 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG);
10971 case ISD::UINT_TO_FP: return LowerUINT_TO_FP(Op, DAG);
10972 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG);
10973 case ISD::FP_TO_UINT: return LowerFP_TO_UINT(Op, DAG);
10974 case ISD::FABS: return LowerFABS(Op, DAG);
10975 case ISD::FNEG: return LowerFNEG(Op, DAG);
10976 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG);
10977 case ISD::FGETSIGN: return LowerFGETSIGN(Op, DAG);
10978 case ISD::SETCC: return LowerSETCC(Op, DAG);
10979 case ISD::SELECT: return LowerSELECT(Op, DAG);
10980 case ISD::BRCOND: return LowerBRCOND(Op, DAG);
10981 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
10982 case ISD::VASTART: return LowerVASTART(Op, DAG);
10983 case ISD::VAARG: return LowerVAARG(Op, DAG);
10984 case ISD::VACOPY: return LowerVACOPY(Op, DAG);
10985 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
10986 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
10987 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
10988 case ISD::FRAME_TO_ARGS_OFFSET:
10989 return LowerFRAME_TO_ARGS_OFFSET(Op, DAG);
10990 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
10991 case ISD::EH_RETURN: return LowerEH_RETURN(Op, DAG);
10992 case ISD::INIT_TRAMPOLINE: return LowerINIT_TRAMPOLINE(Op, DAG);
10993 case ISD::ADJUST_TRAMPOLINE: return LowerADJUST_TRAMPOLINE(Op, DAG);
10994 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
10995 case ISD::CTLZ: return LowerCTLZ(Op, DAG);
10996 case ISD::CTLZ_ZERO_UNDEF: return LowerCTLZ_ZERO_UNDEF(Op, DAG);
10997 case ISD::CTTZ: return LowerCTTZ(Op, DAG);
10998 case ISD::MUL: return LowerMUL(Op, DAG);
11001 case ISD::SHL: return LowerShift(Op, DAG);
11007 case ISD::UMULO: return LowerXALUO(Op, DAG);
11008 case ISD::READCYCLECOUNTER: return LowerREADCYCLECOUNTER(Op, DAG);
11009 case ISD::BITCAST: return LowerBITCAST(Op, DAG);
11013 case ISD::SUBE: return LowerADDC_ADDE_SUBC_SUBE(Op, DAG);
11014 case ISD::ADD: return LowerADD(Op, DAG);
11015 case ISD::SUB: return LowerSUB(Op, DAG);
11019 static void ReplaceATOMIC_LOAD(SDNode *Node,
11020 SmallVectorImpl<SDValue> &Results,
11021 SelectionDAG &DAG) {
11022 DebugLoc dl = Node->getDebugLoc();
11023 EVT VT = cast<AtomicSDNode>(Node)->getMemoryVT();
11025 // Convert wide load -> cmpxchg8b/cmpxchg16b
11026 // FIXME: On 32-bit, load -> fild or movq would be more efficient
11027 // (The only way to get a 16-byte load is cmpxchg16b)
11028 // FIXME: 16-byte ATOMIC_CMP_SWAP isn't actually hooked up at the moment.
11029 SDValue Zero = DAG.getConstant(0, VT);
11030 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_CMP_SWAP, dl, VT,
11031 Node->getOperand(0),
11032 Node->getOperand(1), Zero, Zero,
11033 cast<AtomicSDNode>(Node)->getMemOperand(),
11034 cast<AtomicSDNode>(Node)->getOrdering(),
11035 cast<AtomicSDNode>(Node)->getSynchScope());
11036 Results.push_back(Swap.getValue(0));
11037 Results.push_back(Swap.getValue(1));
11040 void X86TargetLowering::
11041 ReplaceATOMIC_BINARY_64(SDNode *Node, SmallVectorImpl<SDValue>&Results,
11042 SelectionDAG &DAG, unsigned NewOp) const {
11043 DebugLoc dl = Node->getDebugLoc();
11044 assert (Node->getValueType(0) == MVT::i64 &&
11045 "Only know how to expand i64 atomics");
11047 SDValue Chain = Node->getOperand(0);
11048 SDValue In1 = Node->getOperand(1);
11049 SDValue In2L = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
11050 Node->getOperand(2), DAG.getIntPtrConstant(0));
11051 SDValue In2H = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
11052 Node->getOperand(2), DAG.getIntPtrConstant(1));
11053 SDValue Ops[] = { Chain, In1, In2L, In2H };
11054 SDVTList Tys = DAG.getVTList(MVT::i32, MVT::i32, MVT::Other);
11056 DAG.getMemIntrinsicNode(NewOp, dl, Tys, Ops, 4, MVT::i64,
11057 cast<MemSDNode>(Node)->getMemOperand());
11058 SDValue OpsF[] = { Result.getValue(0), Result.getValue(1)};
11059 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, OpsF, 2));
11060 Results.push_back(Result.getValue(2));
11063 /// ReplaceNodeResults - Replace a node with an illegal result type
11064 /// with a new node built out of custom code.
11065 void X86TargetLowering::ReplaceNodeResults(SDNode *N,
11066 SmallVectorImpl<SDValue>&Results,
11067 SelectionDAG &DAG) const {
11068 DebugLoc dl = N->getDebugLoc();
11069 switch (N->getOpcode()) {
11071 llvm_unreachable("Do not know how to custom type legalize this operation!");
11072 case ISD::SIGN_EXTEND_INREG:
11077 // We don't want to expand or promote these.
11079 case ISD::FP_TO_SINT:
11080 case ISD::FP_TO_UINT: {
11081 bool IsSigned = N->getOpcode() == ISD::FP_TO_SINT;
11083 if (!IsSigned && !isIntegerTypeFTOL(SDValue(N, 0).getValueType()))
11086 std::pair<SDValue,SDValue> Vals =
11087 FP_TO_INTHelper(SDValue(N, 0), DAG, IsSigned, /*IsReplace=*/ true);
11088 SDValue FIST = Vals.first, StackSlot = Vals.second;
11089 if (FIST.getNode() != 0) {
11090 EVT VT = N->getValueType(0);
11091 // Return a load from the stack slot.
11092 if (StackSlot.getNode() != 0)
11093 Results.push_back(DAG.getLoad(VT, dl, FIST, StackSlot,
11094 MachinePointerInfo(),
11095 false, false, false, 0));
11097 Results.push_back(FIST);
11101 case ISD::READCYCLECOUNTER: {
11102 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
11103 SDValue TheChain = N->getOperand(0);
11104 SDValue rd = DAG.getNode(X86ISD::RDTSC_DAG, dl, Tys, &TheChain, 1);
11105 SDValue eax = DAG.getCopyFromReg(rd, dl, X86::EAX, MVT::i32,
11107 SDValue edx = DAG.getCopyFromReg(eax.getValue(1), dl, X86::EDX, MVT::i32,
11109 // Use a buildpair to merge the two 32-bit values into a 64-bit one.
11110 SDValue Ops[] = { eax, edx };
11111 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Ops, 2));
11112 Results.push_back(edx.getValue(1));
11115 case ISD::ATOMIC_CMP_SWAP: {
11116 EVT T = N->getValueType(0);
11117 assert((T == MVT::i64 || T == MVT::i128) && "can only expand cmpxchg pair");
11118 bool Regs64bit = T == MVT::i128;
11119 EVT HalfT = Regs64bit ? MVT::i64 : MVT::i32;
11120 SDValue cpInL, cpInH;
11121 cpInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2),
11122 DAG.getConstant(0, HalfT));
11123 cpInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2),
11124 DAG.getConstant(1, HalfT));
11125 cpInL = DAG.getCopyToReg(N->getOperand(0), dl,
11126 Regs64bit ? X86::RAX : X86::EAX,
11128 cpInH = DAG.getCopyToReg(cpInL.getValue(0), dl,
11129 Regs64bit ? X86::RDX : X86::EDX,
11130 cpInH, cpInL.getValue(1));
11131 SDValue swapInL, swapInH;
11132 swapInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3),
11133 DAG.getConstant(0, HalfT));
11134 swapInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3),
11135 DAG.getConstant(1, HalfT));
11136 swapInL = DAG.getCopyToReg(cpInH.getValue(0), dl,
11137 Regs64bit ? X86::RBX : X86::EBX,
11138 swapInL, cpInH.getValue(1));
11139 swapInH = DAG.getCopyToReg(swapInL.getValue(0), dl,
11140 Regs64bit ? X86::RCX : X86::ECX,
11141 swapInH, swapInL.getValue(1));
11142 SDValue Ops[] = { swapInH.getValue(0),
11144 swapInH.getValue(1) };
11145 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
11146 MachineMemOperand *MMO = cast<AtomicSDNode>(N)->getMemOperand();
11147 unsigned Opcode = Regs64bit ? X86ISD::LCMPXCHG16_DAG :
11148 X86ISD::LCMPXCHG8_DAG;
11149 SDValue Result = DAG.getMemIntrinsicNode(Opcode, dl, Tys,
11151 SDValue cpOutL = DAG.getCopyFromReg(Result.getValue(0), dl,
11152 Regs64bit ? X86::RAX : X86::EAX,
11153 HalfT, Result.getValue(1));
11154 SDValue cpOutH = DAG.getCopyFromReg(cpOutL.getValue(1), dl,
11155 Regs64bit ? X86::RDX : X86::EDX,
11156 HalfT, cpOutL.getValue(2));
11157 SDValue OpsF[] = { cpOutL.getValue(0), cpOutH.getValue(0)};
11158 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, T, OpsF, 2));
11159 Results.push_back(cpOutH.getValue(1));
11162 case ISD::ATOMIC_LOAD_ADD:
11163 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMADD64_DAG);
11165 case ISD::ATOMIC_LOAD_AND:
11166 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMAND64_DAG);
11168 case ISD::ATOMIC_LOAD_NAND:
11169 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMNAND64_DAG);
11171 case ISD::ATOMIC_LOAD_OR:
11172 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMOR64_DAG);
11174 case ISD::ATOMIC_LOAD_SUB:
11175 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMSUB64_DAG);
11177 case ISD::ATOMIC_LOAD_XOR:
11178 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMXOR64_DAG);
11180 case ISD::ATOMIC_SWAP:
11181 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMSWAP64_DAG);
11183 case ISD::ATOMIC_LOAD:
11184 ReplaceATOMIC_LOAD(N, Results, DAG);
11188 const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
11190 default: return NULL;
11191 case X86ISD::BSF: return "X86ISD::BSF";
11192 case X86ISD::BSR: return "X86ISD::BSR";
11193 case X86ISD::SHLD: return "X86ISD::SHLD";
11194 case X86ISD::SHRD: return "X86ISD::SHRD";
11195 case X86ISD::FAND: return "X86ISD::FAND";
11196 case X86ISD::FOR: return "X86ISD::FOR";
11197 case X86ISD::FXOR: return "X86ISD::FXOR";
11198 case X86ISD::FSRL: return "X86ISD::FSRL";
11199 case X86ISD::FILD: return "X86ISD::FILD";
11200 case X86ISD::FILD_FLAG: return "X86ISD::FILD_FLAG";
11201 case X86ISD::FP_TO_INT16_IN_MEM: return "X86ISD::FP_TO_INT16_IN_MEM";
11202 case X86ISD::FP_TO_INT32_IN_MEM: return "X86ISD::FP_TO_INT32_IN_MEM";
11203 case X86ISD::FP_TO_INT64_IN_MEM: return "X86ISD::FP_TO_INT64_IN_MEM";
11204 case X86ISD::FLD: return "X86ISD::FLD";
11205 case X86ISD::FST: return "X86ISD::FST";
11206 case X86ISD::CALL: return "X86ISD::CALL";
11207 case X86ISD::RDTSC_DAG: return "X86ISD::RDTSC_DAG";
11208 case X86ISD::BT: return "X86ISD::BT";
11209 case X86ISD::CMP: return "X86ISD::CMP";
11210 case X86ISD::COMI: return "X86ISD::COMI";
11211 case X86ISD::UCOMI: return "X86ISD::UCOMI";
11212 case X86ISD::SETCC: return "X86ISD::SETCC";
11213 case X86ISD::SETCC_CARRY: return "X86ISD::SETCC_CARRY";
11214 case X86ISD::FSETCCsd: return "X86ISD::FSETCCsd";
11215 case X86ISD::FSETCCss: return "X86ISD::FSETCCss";
11216 case X86ISD::CMOV: return "X86ISD::CMOV";
11217 case X86ISD::BRCOND: return "X86ISD::BRCOND";
11218 case X86ISD::RET_FLAG: return "X86ISD::RET_FLAG";
11219 case X86ISD::REP_STOS: return "X86ISD::REP_STOS";
11220 case X86ISD::REP_MOVS: return "X86ISD::REP_MOVS";
11221 case X86ISD::GlobalBaseReg: return "X86ISD::GlobalBaseReg";
11222 case X86ISD::Wrapper: return "X86ISD::Wrapper";
11223 case X86ISD::WrapperRIP: return "X86ISD::WrapperRIP";
11224 case X86ISD::PEXTRB: return "X86ISD::PEXTRB";
11225 case X86ISD::PEXTRW: return "X86ISD::PEXTRW";
11226 case X86ISD::INSERTPS: return "X86ISD::INSERTPS";
11227 case X86ISD::PINSRB: return "X86ISD::PINSRB";
11228 case X86ISD::PINSRW: return "X86ISD::PINSRW";
11229 case X86ISD::PSHUFB: return "X86ISD::PSHUFB";
11230 case X86ISD::ANDNP: return "X86ISD::ANDNP";
11231 case X86ISD::PSIGN: return "X86ISD::PSIGN";
11232 case X86ISD::BLENDV: return "X86ISD::BLENDV";
11233 case X86ISD::BLENDPW: return "X86ISD::BLENDPW";
11234 case X86ISD::BLENDPS: return "X86ISD::BLENDPS";
11235 case X86ISD::BLENDPD: return "X86ISD::BLENDPD";
11236 case X86ISD::HADD: return "X86ISD::HADD";
11237 case X86ISD::HSUB: return "X86ISD::HSUB";
11238 case X86ISD::FHADD: return "X86ISD::FHADD";
11239 case X86ISD::FHSUB: return "X86ISD::FHSUB";
11240 case X86ISD::FMAX: return "X86ISD::FMAX";
11241 case X86ISD::FMIN: return "X86ISD::FMIN";
11242 case X86ISD::FRSQRT: return "X86ISD::FRSQRT";
11243 case X86ISD::FRCP: return "X86ISD::FRCP";
11244 case X86ISD::TLSADDR: return "X86ISD::TLSADDR";
11245 case X86ISD::TLSCALL: return "X86ISD::TLSCALL";
11246 case X86ISD::EH_RETURN: return "X86ISD::EH_RETURN";
11247 case X86ISD::TC_RETURN: return "X86ISD::TC_RETURN";
11248 case X86ISD::FNSTCW16m: return "X86ISD::FNSTCW16m";
11249 case X86ISD::FNSTSW16r: return "X86ISD::FNSTSW16r";
11250 case X86ISD::LCMPXCHG_DAG: return "X86ISD::LCMPXCHG_DAG";
11251 case X86ISD::LCMPXCHG8_DAG: return "X86ISD::LCMPXCHG8_DAG";
11252 case X86ISD::ATOMADD64_DAG: return "X86ISD::ATOMADD64_DAG";
11253 case X86ISD::ATOMSUB64_DAG: return "X86ISD::ATOMSUB64_DAG";
11254 case X86ISD::ATOMOR64_DAG: return "X86ISD::ATOMOR64_DAG";
11255 case X86ISD::ATOMXOR64_DAG: return "X86ISD::ATOMXOR64_DAG";
11256 case X86ISD::ATOMAND64_DAG: return "X86ISD::ATOMAND64_DAG";
11257 case X86ISD::ATOMNAND64_DAG: return "X86ISD::ATOMNAND64_DAG";
11258 case X86ISD::VZEXT_MOVL: return "X86ISD::VZEXT_MOVL";
11259 case X86ISD::VZEXT_LOAD: return "X86ISD::VZEXT_LOAD";
11260 case X86ISD::VSHLDQ: return "X86ISD::VSHLDQ";
11261 case X86ISD::VSRLDQ: return "X86ISD::VSRLDQ";
11262 case X86ISD::VSHL: return "X86ISD::VSHL";
11263 case X86ISD::VSRL: return "X86ISD::VSRL";
11264 case X86ISD::VSRA: return "X86ISD::VSRA";
11265 case X86ISD::VSHLI: return "X86ISD::VSHLI";
11266 case X86ISD::VSRLI: return "X86ISD::VSRLI";
11267 case X86ISD::VSRAI: return "X86ISD::VSRAI";
11268 case X86ISD::CMPP: return "X86ISD::CMPP";
11269 case X86ISD::PCMPEQ: return "X86ISD::PCMPEQ";
11270 case X86ISD::PCMPGT: return "X86ISD::PCMPGT";
11271 case X86ISD::ADD: return "X86ISD::ADD";
11272 case X86ISD::SUB: return "X86ISD::SUB";
11273 case X86ISD::ADC: return "X86ISD::ADC";
11274 case X86ISD::SBB: return "X86ISD::SBB";
11275 case X86ISD::SMUL: return "X86ISD::SMUL";
11276 case X86ISD::UMUL: return "X86ISD::UMUL";
11277 case X86ISD::INC: return "X86ISD::INC";
11278 case X86ISD::DEC: return "X86ISD::DEC";
11279 case X86ISD::OR: return "X86ISD::OR";
11280 case X86ISD::XOR: return "X86ISD::XOR";
11281 case X86ISD::AND: return "X86ISD::AND";
11282 case X86ISD::ANDN: return "X86ISD::ANDN";
11283 case X86ISD::BLSI: return "X86ISD::BLSI";
11284 case X86ISD::BLSMSK: return "X86ISD::BLSMSK";
11285 case X86ISD::BLSR: return "X86ISD::BLSR";
11286 case X86ISD::MUL_IMM: return "X86ISD::MUL_IMM";
11287 case X86ISD::PTEST: return "X86ISD::PTEST";
11288 case X86ISD::TESTP: return "X86ISD::TESTP";
11289 case X86ISD::PALIGN: return "X86ISD::PALIGN";
11290 case X86ISD::PSHUFD: return "X86ISD::PSHUFD";
11291 case X86ISD::PSHUFHW: return "X86ISD::PSHUFHW";
11292 case X86ISD::PSHUFLW: return "X86ISD::PSHUFLW";
11293 case X86ISD::SHUFP: return "X86ISD::SHUFP";
11294 case X86ISD::MOVLHPS: return "X86ISD::MOVLHPS";
11295 case X86ISD::MOVLHPD: return "X86ISD::MOVLHPD";
11296 case X86ISD::MOVHLPS: return "X86ISD::MOVHLPS";
11297 case X86ISD::MOVLPS: return "X86ISD::MOVLPS";
11298 case X86ISD::MOVLPD: return "X86ISD::MOVLPD";
11299 case X86ISD::MOVDDUP: return "X86ISD::MOVDDUP";
11300 case X86ISD::MOVSHDUP: return "X86ISD::MOVSHDUP";
11301 case X86ISD::MOVSLDUP: return "X86ISD::MOVSLDUP";
11302 case X86ISD::MOVSD: return "X86ISD::MOVSD";
11303 case X86ISD::MOVSS: return "X86ISD::MOVSS";
11304 case X86ISD::UNPCKL: return "X86ISD::UNPCKL";
11305 case X86ISD::UNPCKH: return "X86ISD::UNPCKH";
11306 case X86ISD::VBROADCAST: return "X86ISD::VBROADCAST";
11307 case X86ISD::VPERMILP: return "X86ISD::VPERMILP";
11308 case X86ISD::VPERM2X128: return "X86ISD::VPERM2X128";
11309 case X86ISD::VPERMV: return "X86ISD::VPERMV";
11310 case X86ISD::VPERMI: return "X86ISD::VPERMI";
11311 case X86ISD::PMULUDQ: return "X86ISD::PMULUDQ";
11312 case X86ISD::VASTART_SAVE_XMM_REGS: return "X86ISD::VASTART_SAVE_XMM_REGS";
11313 case X86ISD::VAARG_64: return "X86ISD::VAARG_64";
11314 case X86ISD::WIN_ALLOCA: return "X86ISD::WIN_ALLOCA";
11315 case X86ISD::MEMBARRIER: return "X86ISD::MEMBARRIER";
11316 case X86ISD::SEG_ALLOCA: return "X86ISD::SEG_ALLOCA";
11317 case X86ISD::WIN_FTOL: return "X86ISD::WIN_FTOL";
11318 case X86ISD::SAHF: return "X86ISD::SAHF";
11322 // isLegalAddressingMode - Return true if the addressing mode represented
11323 // by AM is legal for this target, for a load/store of the specified type.
11324 bool X86TargetLowering::isLegalAddressingMode(const AddrMode &AM,
11326 // X86 supports extremely general addressing modes.
11327 CodeModel::Model M = getTargetMachine().getCodeModel();
11328 Reloc::Model R = getTargetMachine().getRelocationModel();
11330 // X86 allows a sign-extended 32-bit immediate field as a displacement.
11331 if (!X86::isOffsetSuitableForCodeModel(AM.BaseOffs, M, AM.BaseGV != NULL))
11336 Subtarget->ClassifyGlobalReference(AM.BaseGV, getTargetMachine());
11338 // If a reference to this global requires an extra load, we can't fold it.
11339 if (isGlobalStubReference(GVFlags))
11342 // If BaseGV requires a register for the PIC base, we cannot also have a
11343 // BaseReg specified.
11344 if (AM.HasBaseReg && isGlobalRelativeToPICBase(GVFlags))
11347 // If lower 4G is not available, then we must use rip-relative addressing.
11348 if ((M != CodeModel::Small || R != Reloc::Static) &&
11349 Subtarget->is64Bit() && (AM.BaseOffs || AM.Scale > 1))
11353 switch (AM.Scale) {
11359 // These scales always work.
11364 // These scales are formed with basereg+scalereg. Only accept if there is
11369 default: // Other stuff never works.
11377 bool X86TargetLowering::isTruncateFree(Type *Ty1, Type *Ty2) const {
11378 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
11380 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits();
11381 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits();
11382 if (NumBits1 <= NumBits2)
11387 bool X86TargetLowering::isTruncateFree(EVT VT1, EVT VT2) const {
11388 if (!VT1.isInteger() || !VT2.isInteger())
11390 unsigned NumBits1 = VT1.getSizeInBits();
11391 unsigned NumBits2 = VT2.getSizeInBits();
11392 if (NumBits1 <= NumBits2)
11397 bool X86TargetLowering::isZExtFree(Type *Ty1, Type *Ty2) const {
11398 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
11399 return Ty1->isIntegerTy(32) && Ty2->isIntegerTy(64) && Subtarget->is64Bit();
11402 bool X86TargetLowering::isZExtFree(EVT VT1, EVT VT2) const {
11403 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
11404 return VT1 == MVT::i32 && VT2 == MVT::i64 && Subtarget->is64Bit();
11407 bool X86TargetLowering::isNarrowingProfitable(EVT VT1, EVT VT2) const {
11408 // i16 instructions are longer (0x66 prefix) and potentially slower.
11409 return !(VT1 == MVT::i32 && VT2 == MVT::i16);
11412 /// isShuffleMaskLegal - Targets can use this to indicate that they only
11413 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
11414 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
11415 /// are assumed to be legal.
11417 X86TargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M,
11419 // Very little shuffling can be done for 64-bit vectors right now.
11420 if (VT.getSizeInBits() == 64)
11423 // FIXME: pshufb, blends, shifts.
11424 return (VT.getVectorNumElements() == 2 ||
11425 ShuffleVectorSDNode::isSplatMask(&M[0], VT) ||
11426 isMOVLMask(M, VT) ||
11427 isSHUFPMask(M, VT, Subtarget->hasAVX()) ||
11428 isPSHUFDMask(M, VT) ||
11429 isPSHUFHWMask(M, VT, Subtarget->hasAVX2()) ||
11430 isPSHUFLWMask(M, VT, Subtarget->hasAVX2()) ||
11431 isPALIGNRMask(M, VT, Subtarget) ||
11432 isUNPCKLMask(M, VT, Subtarget->hasAVX2()) ||
11433 isUNPCKHMask(M, VT, Subtarget->hasAVX2()) ||
11434 isUNPCKL_v_undef_Mask(M, VT, Subtarget->hasAVX2()) ||
11435 isUNPCKH_v_undef_Mask(M, VT, Subtarget->hasAVX2()));
11439 X86TargetLowering::isVectorClearMaskLegal(const SmallVectorImpl<int> &Mask,
11441 unsigned NumElts = VT.getVectorNumElements();
11442 // FIXME: This collection of masks seems suspect.
11445 if (NumElts == 4 && VT.getSizeInBits() == 128) {
11446 return (isMOVLMask(Mask, VT) ||
11447 isCommutedMOVLMask(Mask, VT, true) ||
11448 isSHUFPMask(Mask, VT, Subtarget->hasAVX()) ||
11449 isSHUFPMask(Mask, VT, Subtarget->hasAVX(), /* Commuted */ true));
11454 //===----------------------------------------------------------------------===//
11455 // X86 Scheduler Hooks
11456 //===----------------------------------------------------------------------===//
11458 // private utility function
11459 MachineBasicBlock *
11460 X86TargetLowering::EmitAtomicBitwiseWithCustomInserter(MachineInstr *bInstr,
11461 MachineBasicBlock *MBB,
11468 const TargetRegisterClass *RC,
11469 bool Invert) const {
11470 // For the atomic bitwise operator, we generate
11473 // ld t1 = [bitinstr.addr]
11474 // op t2 = t1, [bitinstr.val]
11475 // not t3 = t2 (if Invert)
11477 // lcs dest = [bitinstr.addr], t3 [EAX is implicit]
11479 // fallthrough -->nextMBB
11480 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
11481 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
11482 MachineFunction::iterator MBBIter = MBB;
11485 /// First build the CFG
11486 MachineFunction *F = MBB->getParent();
11487 MachineBasicBlock *thisMBB = MBB;
11488 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB);
11489 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB);
11490 F->insert(MBBIter, newMBB);
11491 F->insert(MBBIter, nextMBB);
11493 // Transfer the remainder of thisMBB and its successor edges to nextMBB.
11494 nextMBB->splice(nextMBB->begin(), thisMBB,
11495 llvm::next(MachineBasicBlock::iterator(bInstr)),
11497 nextMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
11499 // Update thisMBB to fall through to newMBB
11500 thisMBB->addSuccessor(newMBB);
11502 // newMBB jumps to itself and fall through to nextMBB
11503 newMBB->addSuccessor(nextMBB);
11504 newMBB->addSuccessor(newMBB);
11506 // Insert instructions into newMBB based on incoming instruction
11507 assert(bInstr->getNumOperands() < X86::AddrNumOperands + 4 &&
11508 "unexpected number of operands");
11509 DebugLoc dl = bInstr->getDebugLoc();
11510 MachineOperand& destOper = bInstr->getOperand(0);
11511 MachineOperand* argOpers[2 + X86::AddrNumOperands];
11512 int numArgs = bInstr->getNumOperands() - 1;
11513 for (int i=0; i < numArgs; ++i)
11514 argOpers[i] = &bInstr->getOperand(i+1);
11516 // x86 address has 4 operands: base, index, scale, and displacement
11517 int lastAddrIndx = X86::AddrNumOperands - 1; // [0,3]
11518 int valArgIndx = lastAddrIndx + 1;
11520 unsigned t1 = F->getRegInfo().createVirtualRegister(RC);
11521 MachineInstrBuilder MIB = BuildMI(newMBB, dl, TII->get(LoadOpc), t1);
11522 for (int i=0; i <= lastAddrIndx; ++i)
11523 (*MIB).addOperand(*argOpers[i]);
11525 unsigned t2 = F->getRegInfo().createVirtualRegister(RC);
11526 assert((argOpers[valArgIndx]->isReg() ||
11527 argOpers[valArgIndx]->isImm()) &&
11528 "invalid operand");
11529 if (argOpers[valArgIndx]->isReg())
11530 MIB = BuildMI(newMBB, dl, TII->get(regOpc), t2);
11532 MIB = BuildMI(newMBB, dl, TII->get(immOpc), t2);
11534 (*MIB).addOperand(*argOpers[valArgIndx]);
11536 unsigned t3 = F->getRegInfo().createVirtualRegister(RC);
11538 MIB = BuildMI(newMBB, dl, TII->get(notOpc), t3).addReg(t2);
11543 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), EAXreg);
11546 MIB = BuildMI(newMBB, dl, TII->get(CXchgOpc));
11547 for (int i=0; i <= lastAddrIndx; ++i)
11548 (*MIB).addOperand(*argOpers[i]);
11550 assert(bInstr->hasOneMemOperand() && "Unexpected number of memoperand");
11551 (*MIB).setMemRefs(bInstr->memoperands_begin(),
11552 bInstr->memoperands_end());
11554 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), destOper.getReg());
11555 MIB.addReg(EAXreg);
11558 BuildMI(newMBB, dl, TII->get(X86::JNE_4)).addMBB(newMBB);
11560 bInstr->eraseFromParent(); // The pseudo instruction is gone now.
11564 // private utility function: 64 bit atomics on 32 bit host.
11565 MachineBasicBlock *
11566 X86TargetLowering::EmitAtomicBit6432WithCustomInserter(MachineInstr *bInstr,
11567 MachineBasicBlock *MBB,
11572 bool Invert) const {
11573 // For the atomic bitwise operator, we generate
11574 // thisMBB (instructions are in pairs, except cmpxchg8b)
11575 // ld t1,t2 = [bitinstr.addr]
11577 // out1, out2 = phi (thisMBB, t1/t2) (newMBB, t3/t4)
11578 // op t5, t6 <- out1, out2, [bitinstr.val]
11579 // (for SWAP, substitute: mov t5, t6 <- [bitinstr.val])
11580 // neg t7, t8 < t5, t6 (if Invert)
11581 // mov ECX, EBX <- t5, t6
11582 // mov EAX, EDX <- t1, t2
11583 // cmpxchg8b [bitinstr.addr] [EAX, EDX, EBX, ECX implicit]
11584 // mov t3, t4 <- EAX, EDX
11586 // result in out1, out2
11587 // fallthrough -->nextMBB
11589 const TargetRegisterClass *RC = &X86::GR32RegClass;
11590 const unsigned LoadOpc = X86::MOV32rm;
11591 const unsigned NotOpc = X86::NOT32r;
11592 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
11593 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
11594 MachineFunction::iterator MBBIter = MBB;
11597 /// First build the CFG
11598 MachineFunction *F = MBB->getParent();
11599 MachineBasicBlock *thisMBB = MBB;
11600 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB);
11601 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB);
11602 F->insert(MBBIter, newMBB);
11603 F->insert(MBBIter, nextMBB);
11605 // Transfer the remainder of thisMBB and its successor edges to nextMBB.
11606 nextMBB->splice(nextMBB->begin(), thisMBB,
11607 llvm::next(MachineBasicBlock::iterator(bInstr)),
11609 nextMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
11611 // Update thisMBB to fall through to newMBB
11612 thisMBB->addSuccessor(newMBB);
11614 // newMBB jumps to itself and fall through to nextMBB
11615 newMBB->addSuccessor(nextMBB);
11616 newMBB->addSuccessor(newMBB);
11618 DebugLoc dl = bInstr->getDebugLoc();
11619 // Insert instructions into newMBB based on incoming instruction
11620 // There are 8 "real" operands plus 9 implicit def/uses, ignored here.
11621 assert(bInstr->getNumOperands() < X86::AddrNumOperands + 14 &&
11622 "unexpected number of operands");
11623 MachineOperand& dest1Oper = bInstr->getOperand(0);
11624 MachineOperand& dest2Oper = bInstr->getOperand(1);
11625 MachineOperand* argOpers[2 + X86::AddrNumOperands];
11626 for (int i=0; i < 2 + X86::AddrNumOperands; ++i) {
11627 argOpers[i] = &bInstr->getOperand(i+2);
11629 // We use some of the operands multiple times, so conservatively just
11630 // clear any kill flags that might be present.
11631 if (argOpers[i]->isReg() && argOpers[i]->isUse())
11632 argOpers[i]->setIsKill(false);
11635 // x86 address has 5 operands: base, index, scale, displacement, and segment.
11636 int lastAddrIndx = X86::AddrNumOperands - 1; // [0,3]
11638 unsigned t1 = F->getRegInfo().createVirtualRegister(RC);
11639 MachineInstrBuilder MIB = BuildMI(thisMBB, dl, TII->get(LoadOpc), t1);
11640 for (int i=0; i <= lastAddrIndx; ++i)
11641 (*MIB).addOperand(*argOpers[i]);
11642 unsigned t2 = F->getRegInfo().createVirtualRegister(RC);
11643 MIB = BuildMI(thisMBB, dl, TII->get(LoadOpc), t2);
11644 // add 4 to displacement.
11645 for (int i=0; i <= lastAddrIndx-2; ++i)
11646 (*MIB).addOperand(*argOpers[i]);
11647 MachineOperand newOp3 = *(argOpers[3]);
11648 if (newOp3.isImm())
11649 newOp3.setImm(newOp3.getImm()+4);
11651 newOp3.setOffset(newOp3.getOffset()+4);
11652 (*MIB).addOperand(newOp3);
11653 (*MIB).addOperand(*argOpers[lastAddrIndx]);
11655 // t3/4 are defined later, at the bottom of the loop
11656 unsigned t3 = F->getRegInfo().createVirtualRegister(RC);
11657 unsigned t4 = F->getRegInfo().createVirtualRegister(RC);
11658 BuildMI(newMBB, dl, TII->get(X86::PHI), dest1Oper.getReg())
11659 .addReg(t1).addMBB(thisMBB).addReg(t3).addMBB(newMBB);
11660 BuildMI(newMBB, dl, TII->get(X86::PHI), dest2Oper.getReg())
11661 .addReg(t2).addMBB(thisMBB).addReg(t4).addMBB(newMBB);
11663 // The subsequent operations should be using the destination registers of
11664 // the PHI instructions.
11665 t1 = dest1Oper.getReg();
11666 t2 = dest2Oper.getReg();
11668 int valArgIndx = lastAddrIndx + 1;
11669 assert((argOpers[valArgIndx]->isReg() ||
11670 argOpers[valArgIndx]->isImm()) &&
11671 "invalid operand");
11672 unsigned t5 = F->getRegInfo().createVirtualRegister(RC);
11673 unsigned t6 = F->getRegInfo().createVirtualRegister(RC);
11674 if (argOpers[valArgIndx]->isReg())
11675 MIB = BuildMI(newMBB, dl, TII->get(regOpcL), t5);
11677 MIB = BuildMI(newMBB, dl, TII->get(immOpcL), t5);
11678 if (regOpcL != X86::MOV32rr)
11680 (*MIB).addOperand(*argOpers[valArgIndx]);
11681 assert(argOpers[valArgIndx + 1]->isReg() ==
11682 argOpers[valArgIndx]->isReg());
11683 assert(argOpers[valArgIndx + 1]->isImm() ==
11684 argOpers[valArgIndx]->isImm());
11685 if (argOpers[valArgIndx + 1]->isReg())
11686 MIB = BuildMI(newMBB, dl, TII->get(regOpcH), t6);
11688 MIB = BuildMI(newMBB, dl, TII->get(immOpcH), t6);
11689 if (regOpcH != X86::MOV32rr)
11691 (*MIB).addOperand(*argOpers[valArgIndx + 1]);
11695 t7 = F->getRegInfo().createVirtualRegister(RC);
11696 t8 = F->getRegInfo().createVirtualRegister(RC);
11697 MIB = BuildMI(newMBB, dl, TII->get(NotOpc), t7).addReg(t5);
11698 MIB = BuildMI(newMBB, dl, TII->get(NotOpc), t8).addReg(t6);
11704 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::EAX);
11706 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::EDX);
11709 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::EBX);
11711 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::ECX);
11714 MIB = BuildMI(newMBB, dl, TII->get(X86::LCMPXCHG8B));
11715 for (int i=0; i <= lastAddrIndx; ++i)
11716 (*MIB).addOperand(*argOpers[i]);
11718 assert(bInstr->hasOneMemOperand() && "Unexpected number of memoperand");
11719 (*MIB).setMemRefs(bInstr->memoperands_begin(),
11720 bInstr->memoperands_end());
11722 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), t3);
11723 MIB.addReg(X86::EAX);
11724 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), t4);
11725 MIB.addReg(X86::EDX);
11728 BuildMI(newMBB, dl, TII->get(X86::JNE_4)).addMBB(newMBB);
11730 bInstr->eraseFromParent(); // The pseudo instruction is gone now.
11734 // private utility function
11735 MachineBasicBlock *
11736 X86TargetLowering::EmitAtomicMinMaxWithCustomInserter(MachineInstr *mInstr,
11737 MachineBasicBlock *MBB,
11738 unsigned cmovOpc) const {
11739 // For the atomic min/max operator, we generate
11742 // ld t1 = [min/max.addr]
11743 // mov t2 = [min/max.val]
11745 // cmov[cond] t2 = t1
11747 // lcs dest = [bitinstr.addr], t2 [EAX is implicit]
11749 // fallthrough -->nextMBB
11751 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
11752 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
11753 MachineFunction::iterator MBBIter = MBB;
11756 /// First build the CFG
11757 MachineFunction *F = MBB->getParent();
11758 MachineBasicBlock *thisMBB = MBB;
11759 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB);
11760 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB);
11761 F->insert(MBBIter, newMBB);
11762 F->insert(MBBIter, nextMBB);
11764 // Transfer the remainder of thisMBB and its successor edges to nextMBB.
11765 nextMBB->splice(nextMBB->begin(), thisMBB,
11766 llvm::next(MachineBasicBlock::iterator(mInstr)),
11768 nextMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
11770 // Update thisMBB to fall through to newMBB
11771 thisMBB->addSuccessor(newMBB);
11773 // newMBB jumps to newMBB and fall through to nextMBB
11774 newMBB->addSuccessor(nextMBB);
11775 newMBB->addSuccessor(newMBB);
11777 DebugLoc dl = mInstr->getDebugLoc();
11778 // Insert instructions into newMBB based on incoming instruction
11779 assert(mInstr->getNumOperands() < X86::AddrNumOperands + 4 &&
11780 "unexpected number of operands");
11781 MachineOperand& destOper = mInstr->getOperand(0);
11782 MachineOperand* argOpers[2 + X86::AddrNumOperands];
11783 int numArgs = mInstr->getNumOperands() - 1;
11784 for (int i=0; i < numArgs; ++i)
11785 argOpers[i] = &mInstr->getOperand(i+1);
11787 // x86 address has 4 operands: base, index, scale, and displacement
11788 int lastAddrIndx = X86::AddrNumOperands - 1; // [0,3]
11789 int valArgIndx = lastAddrIndx + 1;
11791 unsigned t1 = F->getRegInfo().createVirtualRegister(&X86::GR32RegClass);
11792 MachineInstrBuilder MIB = BuildMI(newMBB, dl, TII->get(X86::MOV32rm), t1);
11793 for (int i=0; i <= lastAddrIndx; ++i)
11794 (*MIB).addOperand(*argOpers[i]);
11796 // We only support register and immediate values
11797 assert((argOpers[valArgIndx]->isReg() ||
11798 argOpers[valArgIndx]->isImm()) &&
11799 "invalid operand");
11801 unsigned t2 = F->getRegInfo().createVirtualRegister(&X86::GR32RegClass);
11802 if (argOpers[valArgIndx]->isReg())
11803 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), t2);
11805 MIB = BuildMI(newMBB, dl, TII->get(X86::MOV32rr), t2);
11806 (*MIB).addOperand(*argOpers[valArgIndx]);
11808 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::EAX);
11811 MIB = BuildMI(newMBB, dl, TII->get(X86::CMP32rr));
11816 unsigned t3 = F->getRegInfo().createVirtualRegister(&X86::GR32RegClass);
11817 MIB = BuildMI(newMBB, dl, TII->get(cmovOpc),t3);
11821 // Cmp and exchange if none has modified the memory location
11822 MIB = BuildMI(newMBB, dl, TII->get(X86::LCMPXCHG32));
11823 for (int i=0; i <= lastAddrIndx; ++i)
11824 (*MIB).addOperand(*argOpers[i]);
11826 assert(mInstr->hasOneMemOperand() && "Unexpected number of memoperand");
11827 (*MIB).setMemRefs(mInstr->memoperands_begin(),
11828 mInstr->memoperands_end());
11830 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), destOper.getReg());
11831 MIB.addReg(X86::EAX);
11834 BuildMI(newMBB, dl, TII->get(X86::JNE_4)).addMBB(newMBB);
11836 mInstr->eraseFromParent(); // The pseudo instruction is gone now.
11840 // FIXME: When we get size specific XMM0 registers, i.e. XMM0_V16I8
11841 // or XMM0_V32I8 in AVX all of this code can be replaced with that
11842 // in the .td file.
11843 MachineBasicBlock *
11844 X86TargetLowering::EmitPCMP(MachineInstr *MI, MachineBasicBlock *BB,
11845 unsigned numArgs, bool memArg) const {
11846 assert(Subtarget->hasSSE42() &&
11847 "Target must have SSE4.2 or AVX features enabled");
11849 DebugLoc dl = MI->getDebugLoc();
11850 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
11852 if (!Subtarget->hasAVX()) {
11854 Opc = numArgs == 3 ? X86::PCMPISTRM128rm : X86::PCMPESTRM128rm;
11856 Opc = numArgs == 3 ? X86::PCMPISTRM128rr : X86::PCMPESTRM128rr;
11859 Opc = numArgs == 3 ? X86::VPCMPISTRM128rm : X86::VPCMPESTRM128rm;
11861 Opc = numArgs == 3 ? X86::VPCMPISTRM128rr : X86::VPCMPESTRM128rr;
11864 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(Opc));
11865 for (unsigned i = 0; i < numArgs; ++i) {
11866 MachineOperand &Op = MI->getOperand(i+1);
11867 if (!(Op.isReg() && Op.isImplicit()))
11868 MIB.addOperand(Op);
11870 BuildMI(*BB, MI, dl,
11871 TII->get(Subtarget->hasAVX() ? X86::VMOVAPSrr : X86::MOVAPSrr),
11872 MI->getOperand(0).getReg())
11873 .addReg(X86::XMM0);
11875 MI->eraseFromParent();
11879 MachineBasicBlock *
11880 X86TargetLowering::EmitMonitor(MachineInstr *MI, MachineBasicBlock *BB) const {
11881 DebugLoc dl = MI->getDebugLoc();
11882 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
11884 // Address into RAX/EAX, other two args into ECX, EDX.
11885 unsigned MemOpc = Subtarget->is64Bit() ? X86::LEA64r : X86::LEA32r;
11886 unsigned MemReg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
11887 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(MemOpc), MemReg);
11888 for (int i = 0; i < X86::AddrNumOperands; ++i)
11889 MIB.addOperand(MI->getOperand(i));
11891 unsigned ValOps = X86::AddrNumOperands;
11892 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::ECX)
11893 .addReg(MI->getOperand(ValOps).getReg());
11894 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::EDX)
11895 .addReg(MI->getOperand(ValOps+1).getReg());
11897 // The instruction doesn't actually take any operands though.
11898 BuildMI(*BB, MI, dl, TII->get(X86::MONITORrrr));
11900 MI->eraseFromParent(); // The pseudo is gone now.
11904 MachineBasicBlock *
11905 X86TargetLowering::EmitMwait(MachineInstr *MI, MachineBasicBlock *BB) const {
11906 DebugLoc dl = MI->getDebugLoc();
11907 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
11909 // First arg in ECX, the second in EAX.
11910 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::ECX)
11911 .addReg(MI->getOperand(0).getReg());
11912 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::EAX)
11913 .addReg(MI->getOperand(1).getReg());
11915 // The instruction doesn't actually take any operands though.
11916 BuildMI(*BB, MI, dl, TII->get(X86::MWAITrr));
11918 MI->eraseFromParent(); // The pseudo is gone now.
11922 MachineBasicBlock *
11923 X86TargetLowering::EmitVAARG64WithCustomInserter(
11925 MachineBasicBlock *MBB) const {
11926 // Emit va_arg instruction on X86-64.
11928 // Operands to this pseudo-instruction:
11929 // 0 ) Output : destination address (reg)
11930 // 1-5) Input : va_list address (addr, i64mem)
11931 // 6 ) ArgSize : Size (in bytes) of vararg type
11932 // 7 ) ArgMode : 0=overflow only, 1=use gp_offset, 2=use fp_offset
11933 // 8 ) Align : Alignment of type
11934 // 9 ) EFLAGS (implicit-def)
11936 assert(MI->getNumOperands() == 10 && "VAARG_64 should have 10 operands!");
11937 assert(X86::AddrNumOperands == 5 && "VAARG_64 assumes 5 address operands");
11939 unsigned DestReg = MI->getOperand(0).getReg();
11940 MachineOperand &Base = MI->getOperand(1);
11941 MachineOperand &Scale = MI->getOperand(2);
11942 MachineOperand &Index = MI->getOperand(3);
11943 MachineOperand &Disp = MI->getOperand(4);
11944 MachineOperand &Segment = MI->getOperand(5);
11945 unsigned ArgSize = MI->getOperand(6).getImm();
11946 unsigned ArgMode = MI->getOperand(7).getImm();
11947 unsigned Align = MI->getOperand(8).getImm();
11949 // Memory Reference
11950 assert(MI->hasOneMemOperand() && "Expected VAARG_64 to have one memoperand");
11951 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
11952 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
11954 // Machine Information
11955 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
11956 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
11957 const TargetRegisterClass *AddrRegClass = getRegClassFor(MVT::i64);
11958 const TargetRegisterClass *OffsetRegClass = getRegClassFor(MVT::i32);
11959 DebugLoc DL = MI->getDebugLoc();
11961 // struct va_list {
11964 // i64 overflow_area (address)
11965 // i64 reg_save_area (address)
11967 // sizeof(va_list) = 24
11968 // alignment(va_list) = 8
11970 unsigned TotalNumIntRegs = 6;
11971 unsigned TotalNumXMMRegs = 8;
11972 bool UseGPOffset = (ArgMode == 1);
11973 bool UseFPOffset = (ArgMode == 2);
11974 unsigned MaxOffset = TotalNumIntRegs * 8 +
11975 (UseFPOffset ? TotalNumXMMRegs * 16 : 0);
11977 /* Align ArgSize to a multiple of 8 */
11978 unsigned ArgSizeA8 = (ArgSize + 7) & ~7;
11979 bool NeedsAlign = (Align > 8);
11981 MachineBasicBlock *thisMBB = MBB;
11982 MachineBasicBlock *overflowMBB;
11983 MachineBasicBlock *offsetMBB;
11984 MachineBasicBlock *endMBB;
11986 unsigned OffsetDestReg = 0; // Argument address computed by offsetMBB
11987 unsigned OverflowDestReg = 0; // Argument address computed by overflowMBB
11988 unsigned OffsetReg = 0;
11990 if (!UseGPOffset && !UseFPOffset) {
11991 // If we only pull from the overflow region, we don't create a branch.
11992 // We don't need to alter control flow.
11993 OffsetDestReg = 0; // unused
11994 OverflowDestReg = DestReg;
11997 overflowMBB = thisMBB;
12000 // First emit code to check if gp_offset (or fp_offset) is below the bound.
12001 // If so, pull the argument from reg_save_area. (branch to offsetMBB)
12002 // If not, pull from overflow_area. (branch to overflowMBB)
12007 // offsetMBB overflowMBB
12012 // Registers for the PHI in endMBB
12013 OffsetDestReg = MRI.createVirtualRegister(AddrRegClass);
12014 OverflowDestReg = MRI.createVirtualRegister(AddrRegClass);
12016 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
12017 MachineFunction *MF = MBB->getParent();
12018 overflowMBB = MF->CreateMachineBasicBlock(LLVM_BB);
12019 offsetMBB = MF->CreateMachineBasicBlock(LLVM_BB);
12020 endMBB = MF->CreateMachineBasicBlock(LLVM_BB);
12022 MachineFunction::iterator MBBIter = MBB;
12025 // Insert the new basic blocks
12026 MF->insert(MBBIter, offsetMBB);
12027 MF->insert(MBBIter, overflowMBB);
12028 MF->insert(MBBIter, endMBB);
12030 // Transfer the remainder of MBB and its successor edges to endMBB.
12031 endMBB->splice(endMBB->begin(), thisMBB,
12032 llvm::next(MachineBasicBlock::iterator(MI)),
12034 endMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
12036 // Make offsetMBB and overflowMBB successors of thisMBB
12037 thisMBB->addSuccessor(offsetMBB);
12038 thisMBB->addSuccessor(overflowMBB);
12040 // endMBB is a successor of both offsetMBB and overflowMBB
12041 offsetMBB->addSuccessor(endMBB);
12042 overflowMBB->addSuccessor(endMBB);
12044 // Load the offset value into a register
12045 OffsetReg = MRI.createVirtualRegister(OffsetRegClass);
12046 BuildMI(thisMBB, DL, TII->get(X86::MOV32rm), OffsetReg)
12050 .addDisp(Disp, UseFPOffset ? 4 : 0)
12051 .addOperand(Segment)
12052 .setMemRefs(MMOBegin, MMOEnd);
12054 // Check if there is enough room left to pull this argument.
12055 BuildMI(thisMBB, DL, TII->get(X86::CMP32ri))
12057 .addImm(MaxOffset + 8 - ArgSizeA8);
12059 // Branch to "overflowMBB" if offset >= max
12060 // Fall through to "offsetMBB" otherwise
12061 BuildMI(thisMBB, DL, TII->get(X86::GetCondBranchFromCond(X86::COND_AE)))
12062 .addMBB(overflowMBB);
12065 // In offsetMBB, emit code to use the reg_save_area.
12067 assert(OffsetReg != 0);
12069 // Read the reg_save_area address.
12070 unsigned RegSaveReg = MRI.createVirtualRegister(AddrRegClass);
12071 BuildMI(offsetMBB, DL, TII->get(X86::MOV64rm), RegSaveReg)
12076 .addOperand(Segment)
12077 .setMemRefs(MMOBegin, MMOEnd);
12079 // Zero-extend the offset
12080 unsigned OffsetReg64 = MRI.createVirtualRegister(AddrRegClass);
12081 BuildMI(offsetMBB, DL, TII->get(X86::SUBREG_TO_REG), OffsetReg64)
12084 .addImm(X86::sub_32bit);
12086 // Add the offset to the reg_save_area to get the final address.
12087 BuildMI(offsetMBB, DL, TII->get(X86::ADD64rr), OffsetDestReg)
12088 .addReg(OffsetReg64)
12089 .addReg(RegSaveReg);
12091 // Compute the offset for the next argument
12092 unsigned NextOffsetReg = MRI.createVirtualRegister(OffsetRegClass);
12093 BuildMI(offsetMBB, DL, TII->get(X86::ADD32ri), NextOffsetReg)
12095 .addImm(UseFPOffset ? 16 : 8);
12097 // Store it back into the va_list.
12098 BuildMI(offsetMBB, DL, TII->get(X86::MOV32mr))
12102 .addDisp(Disp, UseFPOffset ? 4 : 0)
12103 .addOperand(Segment)
12104 .addReg(NextOffsetReg)
12105 .setMemRefs(MMOBegin, MMOEnd);
12108 BuildMI(offsetMBB, DL, TII->get(X86::JMP_4))
12113 // Emit code to use overflow area
12116 // Load the overflow_area address into a register.
12117 unsigned OverflowAddrReg = MRI.createVirtualRegister(AddrRegClass);
12118 BuildMI(overflowMBB, DL, TII->get(X86::MOV64rm), OverflowAddrReg)
12123 .addOperand(Segment)
12124 .setMemRefs(MMOBegin, MMOEnd);
12126 // If we need to align it, do so. Otherwise, just copy the address
12127 // to OverflowDestReg.
12129 // Align the overflow address
12130 assert((Align & (Align-1)) == 0 && "Alignment must be a power of 2");
12131 unsigned TmpReg = MRI.createVirtualRegister(AddrRegClass);
12133 // aligned_addr = (addr + (align-1)) & ~(align-1)
12134 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), TmpReg)
12135 .addReg(OverflowAddrReg)
12138 BuildMI(overflowMBB, DL, TII->get(X86::AND64ri32), OverflowDestReg)
12140 .addImm(~(uint64_t)(Align-1));
12142 BuildMI(overflowMBB, DL, TII->get(TargetOpcode::COPY), OverflowDestReg)
12143 .addReg(OverflowAddrReg);
12146 // Compute the next overflow address after this argument.
12147 // (the overflow address should be kept 8-byte aligned)
12148 unsigned NextAddrReg = MRI.createVirtualRegister(AddrRegClass);
12149 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), NextAddrReg)
12150 .addReg(OverflowDestReg)
12151 .addImm(ArgSizeA8);
12153 // Store the new overflow address.
12154 BuildMI(overflowMBB, DL, TII->get(X86::MOV64mr))
12159 .addOperand(Segment)
12160 .addReg(NextAddrReg)
12161 .setMemRefs(MMOBegin, MMOEnd);
12163 // If we branched, emit the PHI to the front of endMBB.
12165 BuildMI(*endMBB, endMBB->begin(), DL,
12166 TII->get(X86::PHI), DestReg)
12167 .addReg(OffsetDestReg).addMBB(offsetMBB)
12168 .addReg(OverflowDestReg).addMBB(overflowMBB);
12171 // Erase the pseudo instruction
12172 MI->eraseFromParent();
12177 MachineBasicBlock *
12178 X86TargetLowering::EmitVAStartSaveXMMRegsWithCustomInserter(
12180 MachineBasicBlock *MBB) const {
12181 // Emit code to save XMM registers to the stack. The ABI says that the
12182 // number of registers to save is given in %al, so it's theoretically
12183 // possible to do an indirect jump trick to avoid saving all of them,
12184 // however this code takes a simpler approach and just executes all
12185 // of the stores if %al is non-zero. It's less code, and it's probably
12186 // easier on the hardware branch predictor, and stores aren't all that
12187 // expensive anyway.
12189 // Create the new basic blocks. One block contains all the XMM stores,
12190 // and one block is the final destination regardless of whether any
12191 // stores were performed.
12192 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
12193 MachineFunction *F = MBB->getParent();
12194 MachineFunction::iterator MBBIter = MBB;
12196 MachineBasicBlock *XMMSaveMBB = F->CreateMachineBasicBlock(LLVM_BB);
12197 MachineBasicBlock *EndMBB = F->CreateMachineBasicBlock(LLVM_BB);
12198 F->insert(MBBIter, XMMSaveMBB);
12199 F->insert(MBBIter, EndMBB);
12201 // Transfer the remainder of MBB and its successor edges to EndMBB.
12202 EndMBB->splice(EndMBB->begin(), MBB,
12203 llvm::next(MachineBasicBlock::iterator(MI)),
12205 EndMBB->transferSuccessorsAndUpdatePHIs(MBB);
12207 // The original block will now fall through to the XMM save block.
12208 MBB->addSuccessor(XMMSaveMBB);
12209 // The XMMSaveMBB will fall through to the end block.
12210 XMMSaveMBB->addSuccessor(EndMBB);
12212 // Now add the instructions.
12213 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
12214 DebugLoc DL = MI->getDebugLoc();
12216 unsigned CountReg = MI->getOperand(0).getReg();
12217 int64_t RegSaveFrameIndex = MI->getOperand(1).getImm();
12218 int64_t VarArgsFPOffset = MI->getOperand(2).getImm();
12220 if (!Subtarget->isTargetWin64()) {
12221 // If %al is 0, branch around the XMM save block.
12222 BuildMI(MBB, DL, TII->get(X86::TEST8rr)).addReg(CountReg).addReg(CountReg);
12223 BuildMI(MBB, DL, TII->get(X86::JE_4)).addMBB(EndMBB);
12224 MBB->addSuccessor(EndMBB);
12227 unsigned MOVOpc = Subtarget->hasAVX() ? X86::VMOVAPSmr : X86::MOVAPSmr;
12228 // In the XMM save block, save all the XMM argument registers.
12229 for (int i = 3, e = MI->getNumOperands(); i != e; ++i) {
12230 int64_t Offset = (i - 3) * 16 + VarArgsFPOffset;
12231 MachineMemOperand *MMO =
12232 F->getMachineMemOperand(
12233 MachinePointerInfo::getFixedStack(RegSaveFrameIndex, Offset),
12234 MachineMemOperand::MOStore,
12235 /*Size=*/16, /*Align=*/16);
12236 BuildMI(XMMSaveMBB, DL, TII->get(MOVOpc))
12237 .addFrameIndex(RegSaveFrameIndex)
12238 .addImm(/*Scale=*/1)
12239 .addReg(/*IndexReg=*/0)
12240 .addImm(/*Disp=*/Offset)
12241 .addReg(/*Segment=*/0)
12242 .addReg(MI->getOperand(i).getReg())
12243 .addMemOperand(MMO);
12246 MI->eraseFromParent(); // The pseudo instruction is gone now.
12251 // The EFLAGS operand of SelectItr might be missing a kill marker
12252 // because there were multiple uses of EFLAGS, and ISel didn't know
12253 // which to mark. Figure out whether SelectItr should have had a
12254 // kill marker, and set it if it should. Returns the correct kill
12256 static bool checkAndUpdateEFLAGSKill(MachineBasicBlock::iterator SelectItr,
12257 MachineBasicBlock* BB,
12258 const TargetRegisterInfo* TRI) {
12259 // Scan forward through BB for a use/def of EFLAGS.
12260 MachineBasicBlock::iterator miI(llvm::next(SelectItr));
12261 for (MachineBasicBlock::iterator miE = BB->end(); miI != miE; ++miI) {
12262 const MachineInstr& mi = *miI;
12263 if (mi.readsRegister(X86::EFLAGS))
12265 if (mi.definesRegister(X86::EFLAGS))
12266 break; // Should have kill-flag - update below.
12269 // If we hit the end of the block, check whether EFLAGS is live into a
12271 if (miI == BB->end()) {
12272 for (MachineBasicBlock::succ_iterator sItr = BB->succ_begin(),
12273 sEnd = BB->succ_end();
12274 sItr != sEnd; ++sItr) {
12275 MachineBasicBlock* succ = *sItr;
12276 if (succ->isLiveIn(X86::EFLAGS))
12281 // We found a def, or hit the end of the basic block and EFLAGS wasn't live
12282 // out. SelectMI should have a kill flag on EFLAGS.
12283 SelectItr->addRegisterKilled(X86::EFLAGS, TRI);
12287 MachineBasicBlock *
12288 X86TargetLowering::EmitLoweredSelect(MachineInstr *MI,
12289 MachineBasicBlock *BB) const {
12290 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
12291 DebugLoc DL = MI->getDebugLoc();
12293 // To "insert" a SELECT_CC instruction, we actually have to insert the
12294 // diamond control-flow pattern. The incoming instruction knows the
12295 // destination vreg to set, the condition code register to branch on, the
12296 // true/false values to select between, and a branch opcode to use.
12297 const BasicBlock *LLVM_BB = BB->getBasicBlock();
12298 MachineFunction::iterator It = BB;
12304 // cmpTY ccX, r1, r2
12306 // fallthrough --> copy0MBB
12307 MachineBasicBlock *thisMBB = BB;
12308 MachineFunction *F = BB->getParent();
12309 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
12310 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
12311 F->insert(It, copy0MBB);
12312 F->insert(It, sinkMBB);
12314 // If the EFLAGS register isn't dead in the terminator, then claim that it's
12315 // live into the sink and copy blocks.
12316 const TargetRegisterInfo* TRI = getTargetMachine().getRegisterInfo();
12317 if (!MI->killsRegister(X86::EFLAGS) &&
12318 !checkAndUpdateEFLAGSKill(MI, BB, TRI)) {
12319 copy0MBB->addLiveIn(X86::EFLAGS);
12320 sinkMBB->addLiveIn(X86::EFLAGS);
12323 // Transfer the remainder of BB and its successor edges to sinkMBB.
12324 sinkMBB->splice(sinkMBB->begin(), BB,
12325 llvm::next(MachineBasicBlock::iterator(MI)),
12327 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
12329 // Add the true and fallthrough blocks as its successors.
12330 BB->addSuccessor(copy0MBB);
12331 BB->addSuccessor(sinkMBB);
12333 // Create the conditional branch instruction.
12335 X86::GetCondBranchFromCond((X86::CondCode)MI->getOperand(3).getImm());
12336 BuildMI(BB, DL, TII->get(Opc)).addMBB(sinkMBB);
12339 // %FalseValue = ...
12340 // # fallthrough to sinkMBB
12341 copy0MBB->addSuccessor(sinkMBB);
12344 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
12346 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
12347 TII->get(X86::PHI), MI->getOperand(0).getReg())
12348 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB)
12349 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
12351 MI->eraseFromParent(); // The pseudo instruction is gone now.
12355 MachineBasicBlock *
12356 X86TargetLowering::EmitLoweredSegAlloca(MachineInstr *MI, MachineBasicBlock *BB,
12357 bool Is64Bit) const {
12358 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
12359 DebugLoc DL = MI->getDebugLoc();
12360 MachineFunction *MF = BB->getParent();
12361 const BasicBlock *LLVM_BB = BB->getBasicBlock();
12363 assert(getTargetMachine().Options.EnableSegmentedStacks);
12365 unsigned TlsReg = Is64Bit ? X86::FS : X86::GS;
12366 unsigned TlsOffset = Is64Bit ? 0x70 : 0x30;
12369 // ... [Till the alloca]
12370 // If stacklet is not large enough, jump to mallocMBB
12373 // Allocate by subtracting from RSP
12374 // Jump to continueMBB
12377 // Allocate by call to runtime
12381 // [rest of original BB]
12384 MachineBasicBlock *mallocMBB = MF->CreateMachineBasicBlock(LLVM_BB);
12385 MachineBasicBlock *bumpMBB = MF->CreateMachineBasicBlock(LLVM_BB);
12386 MachineBasicBlock *continueMBB = MF->CreateMachineBasicBlock(LLVM_BB);
12388 MachineRegisterInfo &MRI = MF->getRegInfo();
12389 const TargetRegisterClass *AddrRegClass =
12390 getRegClassFor(Is64Bit ? MVT::i64:MVT::i32);
12392 unsigned mallocPtrVReg = MRI.createVirtualRegister(AddrRegClass),
12393 bumpSPPtrVReg = MRI.createVirtualRegister(AddrRegClass),
12394 tmpSPVReg = MRI.createVirtualRegister(AddrRegClass),
12395 SPLimitVReg = MRI.createVirtualRegister(AddrRegClass),
12396 sizeVReg = MI->getOperand(1).getReg(),
12397 physSPReg = Is64Bit ? X86::RSP : X86::ESP;
12399 MachineFunction::iterator MBBIter = BB;
12402 MF->insert(MBBIter, bumpMBB);
12403 MF->insert(MBBIter, mallocMBB);
12404 MF->insert(MBBIter, continueMBB);
12406 continueMBB->splice(continueMBB->begin(), BB, llvm::next
12407 (MachineBasicBlock::iterator(MI)), BB->end());
12408 continueMBB->transferSuccessorsAndUpdatePHIs(BB);
12410 // Add code to the main basic block to check if the stack limit has been hit,
12411 // and if so, jump to mallocMBB otherwise to bumpMBB.
12412 BuildMI(BB, DL, TII->get(TargetOpcode::COPY), tmpSPVReg).addReg(physSPReg);
12413 BuildMI(BB, DL, TII->get(Is64Bit ? X86::SUB64rr:X86::SUB32rr), SPLimitVReg)
12414 .addReg(tmpSPVReg).addReg(sizeVReg);
12415 BuildMI(BB, DL, TII->get(Is64Bit ? X86::CMP64mr:X86::CMP32mr))
12416 .addReg(0).addImm(1).addReg(0).addImm(TlsOffset).addReg(TlsReg)
12417 .addReg(SPLimitVReg);
12418 BuildMI(BB, DL, TII->get(X86::JG_4)).addMBB(mallocMBB);
12420 // bumpMBB simply decreases the stack pointer, since we know the current
12421 // stacklet has enough space.
12422 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), physSPReg)
12423 .addReg(SPLimitVReg);
12424 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), bumpSPPtrVReg)
12425 .addReg(SPLimitVReg);
12426 BuildMI(bumpMBB, DL, TII->get(X86::JMP_4)).addMBB(continueMBB);
12428 // Calls into a routine in libgcc to allocate more space from the heap.
12429 const uint32_t *RegMask =
12430 getTargetMachine().getRegisterInfo()->getCallPreservedMask(CallingConv::C);
12432 BuildMI(mallocMBB, DL, TII->get(X86::MOV64rr), X86::RDI)
12434 BuildMI(mallocMBB, DL, TII->get(X86::CALL64pcrel32))
12435 .addExternalSymbol("__morestack_allocate_stack_space").addReg(X86::RDI)
12436 .addRegMask(RegMask)
12437 .addReg(X86::RAX, RegState::ImplicitDefine);
12439 BuildMI(mallocMBB, DL, TII->get(X86::SUB32ri), physSPReg).addReg(physSPReg)
12441 BuildMI(mallocMBB, DL, TII->get(X86::PUSH32r)).addReg(sizeVReg);
12442 BuildMI(mallocMBB, DL, TII->get(X86::CALLpcrel32))
12443 .addExternalSymbol("__morestack_allocate_stack_space")
12444 .addRegMask(RegMask)
12445 .addReg(X86::EAX, RegState::ImplicitDefine);
12449 BuildMI(mallocMBB, DL, TII->get(X86::ADD32ri), physSPReg).addReg(physSPReg)
12452 BuildMI(mallocMBB, DL, TII->get(TargetOpcode::COPY), mallocPtrVReg)
12453 .addReg(Is64Bit ? X86::RAX : X86::EAX);
12454 BuildMI(mallocMBB, DL, TII->get(X86::JMP_4)).addMBB(continueMBB);
12456 // Set up the CFG correctly.
12457 BB->addSuccessor(bumpMBB);
12458 BB->addSuccessor(mallocMBB);
12459 mallocMBB->addSuccessor(continueMBB);
12460 bumpMBB->addSuccessor(continueMBB);
12462 // Take care of the PHI nodes.
12463 BuildMI(*continueMBB, continueMBB->begin(), DL, TII->get(X86::PHI),
12464 MI->getOperand(0).getReg())
12465 .addReg(mallocPtrVReg).addMBB(mallocMBB)
12466 .addReg(bumpSPPtrVReg).addMBB(bumpMBB);
12468 // Delete the original pseudo instruction.
12469 MI->eraseFromParent();
12472 return continueMBB;
12475 MachineBasicBlock *
12476 X86TargetLowering::EmitLoweredWinAlloca(MachineInstr *MI,
12477 MachineBasicBlock *BB) const {
12478 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
12479 DebugLoc DL = MI->getDebugLoc();
12481 assert(!Subtarget->isTargetEnvMacho());
12483 // The lowering is pretty easy: we're just emitting the call to _alloca. The
12484 // non-trivial part is impdef of ESP.
12486 if (Subtarget->isTargetWin64()) {
12487 if (Subtarget->isTargetCygMing()) {
12488 // ___chkstk(Mingw64):
12489 // Clobbers R10, R11, RAX and EFLAGS.
12491 BuildMI(*BB, MI, DL, TII->get(X86::W64ALLOCA))
12492 .addExternalSymbol("___chkstk")
12493 .addReg(X86::RAX, RegState::Implicit)
12494 .addReg(X86::RSP, RegState::Implicit)
12495 .addReg(X86::RAX, RegState::Define | RegState::Implicit)
12496 .addReg(X86::RSP, RegState::Define | RegState::Implicit)
12497 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
12499 // __chkstk(MSVCRT): does not update stack pointer.
12500 // Clobbers R10, R11 and EFLAGS.
12501 // FIXME: RAX(allocated size) might be reused and not killed.
12502 BuildMI(*BB, MI, DL, TII->get(X86::W64ALLOCA))
12503 .addExternalSymbol("__chkstk")
12504 .addReg(X86::RAX, RegState::Implicit)
12505 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
12506 // RAX has the offset to subtracted from RSP.
12507 BuildMI(*BB, MI, DL, TII->get(X86::SUB64rr), X86::RSP)
12512 const char *StackProbeSymbol =
12513 Subtarget->isTargetWindows() ? "_chkstk" : "_alloca";
12515 BuildMI(*BB, MI, DL, TII->get(X86::CALLpcrel32))
12516 .addExternalSymbol(StackProbeSymbol)
12517 .addReg(X86::EAX, RegState::Implicit)
12518 .addReg(X86::ESP, RegState::Implicit)
12519 .addReg(X86::EAX, RegState::Define | RegState::Implicit)
12520 .addReg(X86::ESP, RegState::Define | RegState::Implicit)
12521 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
12524 MI->eraseFromParent(); // The pseudo instruction is gone now.
12528 MachineBasicBlock *
12529 X86TargetLowering::EmitLoweredTLSCall(MachineInstr *MI,
12530 MachineBasicBlock *BB) const {
12531 // This is pretty easy. We're taking the value that we received from
12532 // our load from the relocation, sticking it in either RDI (x86-64)
12533 // or EAX and doing an indirect call. The return value will then
12534 // be in the normal return register.
12535 const X86InstrInfo *TII
12536 = static_cast<const X86InstrInfo*>(getTargetMachine().getInstrInfo());
12537 DebugLoc DL = MI->getDebugLoc();
12538 MachineFunction *F = BB->getParent();
12540 assert(Subtarget->isTargetDarwin() && "Darwin only instr emitted?");
12541 assert(MI->getOperand(3).isGlobal() && "This should be a global");
12543 // Get a register mask for the lowered call.
12544 // FIXME: The 32-bit calls have non-standard calling conventions. Use a
12545 // proper register mask.
12546 const uint32_t *RegMask =
12547 getTargetMachine().getRegisterInfo()->getCallPreservedMask(CallingConv::C);
12548 if (Subtarget->is64Bit()) {
12549 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
12550 TII->get(X86::MOV64rm), X86::RDI)
12552 .addImm(0).addReg(0)
12553 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
12554 MI->getOperand(3).getTargetFlags())
12556 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL64m));
12557 addDirectMem(MIB, X86::RDI);
12558 MIB.addReg(X86::RAX, RegState::ImplicitDefine).addRegMask(RegMask);
12559 } else if (getTargetMachine().getRelocationModel() != Reloc::PIC_) {
12560 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
12561 TII->get(X86::MOV32rm), X86::EAX)
12563 .addImm(0).addReg(0)
12564 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
12565 MI->getOperand(3).getTargetFlags())
12567 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
12568 addDirectMem(MIB, X86::EAX);
12569 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask);
12571 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
12572 TII->get(X86::MOV32rm), X86::EAX)
12573 .addReg(TII->getGlobalBaseReg(F))
12574 .addImm(0).addReg(0)
12575 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
12576 MI->getOperand(3).getTargetFlags())
12578 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
12579 addDirectMem(MIB, X86::EAX);
12580 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask);
12583 MI->eraseFromParent(); // The pseudo instruction is gone now.
12587 MachineBasicBlock *
12588 X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
12589 MachineBasicBlock *BB) const {
12590 switch (MI->getOpcode()) {
12591 default: llvm_unreachable("Unexpected instr type to insert");
12592 case X86::TAILJMPd64:
12593 case X86::TAILJMPr64:
12594 case X86::TAILJMPm64:
12595 llvm_unreachable("TAILJMP64 would not be touched here.");
12596 case X86::TCRETURNdi64:
12597 case X86::TCRETURNri64:
12598 case X86::TCRETURNmi64:
12600 case X86::WIN_ALLOCA:
12601 return EmitLoweredWinAlloca(MI, BB);
12602 case X86::SEG_ALLOCA_32:
12603 return EmitLoweredSegAlloca(MI, BB, false);
12604 case X86::SEG_ALLOCA_64:
12605 return EmitLoweredSegAlloca(MI, BB, true);
12606 case X86::TLSCall_32:
12607 case X86::TLSCall_64:
12608 return EmitLoweredTLSCall(MI, BB);
12609 case X86::CMOV_GR8:
12610 case X86::CMOV_FR32:
12611 case X86::CMOV_FR64:
12612 case X86::CMOV_V4F32:
12613 case X86::CMOV_V2F64:
12614 case X86::CMOV_V2I64:
12615 case X86::CMOV_V8F32:
12616 case X86::CMOV_V4F64:
12617 case X86::CMOV_V4I64:
12618 case X86::CMOV_GR16:
12619 case X86::CMOV_GR32:
12620 case X86::CMOV_RFP32:
12621 case X86::CMOV_RFP64:
12622 case X86::CMOV_RFP80:
12623 return EmitLoweredSelect(MI, BB);
12625 case X86::FP32_TO_INT16_IN_MEM:
12626 case X86::FP32_TO_INT32_IN_MEM:
12627 case X86::FP32_TO_INT64_IN_MEM:
12628 case X86::FP64_TO_INT16_IN_MEM:
12629 case X86::FP64_TO_INT32_IN_MEM:
12630 case X86::FP64_TO_INT64_IN_MEM:
12631 case X86::FP80_TO_INT16_IN_MEM:
12632 case X86::FP80_TO_INT32_IN_MEM:
12633 case X86::FP80_TO_INT64_IN_MEM: {
12634 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
12635 DebugLoc DL = MI->getDebugLoc();
12637 // Change the floating point control register to use "round towards zero"
12638 // mode when truncating to an integer value.
12639 MachineFunction *F = BB->getParent();
12640 int CWFrameIdx = F->getFrameInfo()->CreateStackObject(2, 2, false);
12641 addFrameReference(BuildMI(*BB, MI, DL,
12642 TII->get(X86::FNSTCW16m)), CWFrameIdx);
12644 // Load the old value of the high byte of the control word...
12646 F->getRegInfo().createVirtualRegister(&X86::GR16RegClass);
12647 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16rm), OldCW),
12650 // Set the high part to be round to zero...
12651 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mi)), CWFrameIdx)
12654 // Reload the modified control word now...
12655 addFrameReference(BuildMI(*BB, MI, DL,
12656 TII->get(X86::FLDCW16m)), CWFrameIdx);
12658 // Restore the memory image of control word to original value
12659 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mr)), CWFrameIdx)
12662 // Get the X86 opcode to use.
12664 switch (MI->getOpcode()) {
12665 default: llvm_unreachable("illegal opcode!");
12666 case X86::FP32_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m32; break;
12667 case X86::FP32_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m32; break;
12668 case X86::FP32_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m32; break;
12669 case X86::FP64_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m64; break;
12670 case X86::FP64_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m64; break;
12671 case X86::FP64_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m64; break;
12672 case X86::FP80_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m80; break;
12673 case X86::FP80_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m80; break;
12674 case X86::FP80_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m80; break;
12678 MachineOperand &Op = MI->getOperand(0);
12680 AM.BaseType = X86AddressMode::RegBase;
12681 AM.Base.Reg = Op.getReg();
12683 AM.BaseType = X86AddressMode::FrameIndexBase;
12684 AM.Base.FrameIndex = Op.getIndex();
12686 Op = MI->getOperand(1);
12688 AM.Scale = Op.getImm();
12689 Op = MI->getOperand(2);
12691 AM.IndexReg = Op.getImm();
12692 Op = MI->getOperand(3);
12693 if (Op.isGlobal()) {
12694 AM.GV = Op.getGlobal();
12696 AM.Disp = Op.getImm();
12698 addFullAddress(BuildMI(*BB, MI, DL, TII->get(Opc)), AM)
12699 .addReg(MI->getOperand(X86::AddrNumOperands).getReg());
12701 // Reload the original control word now.
12702 addFrameReference(BuildMI(*BB, MI, DL,
12703 TII->get(X86::FLDCW16m)), CWFrameIdx);
12705 MI->eraseFromParent(); // The pseudo instruction is gone now.
12708 // String/text processing lowering.
12709 case X86::PCMPISTRM128REG:
12710 case X86::VPCMPISTRM128REG:
12711 return EmitPCMP(MI, BB, 3, false /* in-mem */);
12712 case X86::PCMPISTRM128MEM:
12713 case X86::VPCMPISTRM128MEM:
12714 return EmitPCMP(MI, BB, 3, true /* in-mem */);
12715 case X86::PCMPESTRM128REG:
12716 case X86::VPCMPESTRM128REG:
12717 return EmitPCMP(MI, BB, 5, false /* in mem */);
12718 case X86::PCMPESTRM128MEM:
12719 case X86::VPCMPESTRM128MEM:
12720 return EmitPCMP(MI, BB, 5, true /* in mem */);
12722 // Thread synchronization.
12724 return EmitMonitor(MI, BB);
12726 return EmitMwait(MI, BB);
12728 // Atomic Lowering.
12729 case X86::ATOMAND32:
12730 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND32rr,
12731 X86::AND32ri, X86::MOV32rm,
12733 X86::NOT32r, X86::EAX,
12734 &X86::GR32RegClass);
12735 case X86::ATOMOR32:
12736 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR32rr,
12737 X86::OR32ri, X86::MOV32rm,
12739 X86::NOT32r, X86::EAX,
12740 &X86::GR32RegClass);
12741 case X86::ATOMXOR32:
12742 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR32rr,
12743 X86::XOR32ri, X86::MOV32rm,
12745 X86::NOT32r, X86::EAX,
12746 &X86::GR32RegClass);
12747 case X86::ATOMNAND32:
12748 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND32rr,
12749 X86::AND32ri, X86::MOV32rm,
12751 X86::NOT32r, X86::EAX,
12752 &X86::GR32RegClass, true);
12753 case X86::ATOMMIN32:
12754 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL32rr);
12755 case X86::ATOMMAX32:
12756 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG32rr);
12757 case X86::ATOMUMIN32:
12758 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB32rr);
12759 case X86::ATOMUMAX32:
12760 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA32rr);
12762 case X86::ATOMAND16:
12763 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND16rr,
12764 X86::AND16ri, X86::MOV16rm,
12766 X86::NOT16r, X86::AX,
12767 &X86::GR16RegClass);
12768 case X86::ATOMOR16:
12769 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR16rr,
12770 X86::OR16ri, X86::MOV16rm,
12772 X86::NOT16r, X86::AX,
12773 &X86::GR16RegClass);
12774 case X86::ATOMXOR16:
12775 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR16rr,
12776 X86::XOR16ri, X86::MOV16rm,
12778 X86::NOT16r, X86::AX,
12779 &X86::GR16RegClass);
12780 case X86::ATOMNAND16:
12781 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND16rr,
12782 X86::AND16ri, X86::MOV16rm,
12784 X86::NOT16r, X86::AX,
12785 &X86::GR16RegClass, true);
12786 case X86::ATOMMIN16:
12787 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL16rr);
12788 case X86::ATOMMAX16:
12789 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG16rr);
12790 case X86::ATOMUMIN16:
12791 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB16rr);
12792 case X86::ATOMUMAX16:
12793 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA16rr);
12795 case X86::ATOMAND8:
12796 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND8rr,
12797 X86::AND8ri, X86::MOV8rm,
12799 X86::NOT8r, X86::AL,
12800 &X86::GR8RegClass);
12802 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR8rr,
12803 X86::OR8ri, X86::MOV8rm,
12805 X86::NOT8r, X86::AL,
12806 &X86::GR8RegClass);
12807 case X86::ATOMXOR8:
12808 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR8rr,
12809 X86::XOR8ri, X86::MOV8rm,
12811 X86::NOT8r, X86::AL,
12812 &X86::GR8RegClass);
12813 case X86::ATOMNAND8:
12814 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND8rr,
12815 X86::AND8ri, X86::MOV8rm,
12817 X86::NOT8r, X86::AL,
12818 &X86::GR8RegClass, true);
12819 // FIXME: There are no CMOV8 instructions; MIN/MAX need some other way.
12820 // This group is for 64-bit host.
12821 case X86::ATOMAND64:
12822 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND64rr,
12823 X86::AND64ri32, X86::MOV64rm,
12825 X86::NOT64r, X86::RAX,
12826 &X86::GR64RegClass);
12827 case X86::ATOMOR64:
12828 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR64rr,
12829 X86::OR64ri32, X86::MOV64rm,
12831 X86::NOT64r, X86::RAX,
12832 &X86::GR64RegClass);
12833 case X86::ATOMXOR64:
12834 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR64rr,
12835 X86::XOR64ri32, X86::MOV64rm,
12837 X86::NOT64r, X86::RAX,
12838 &X86::GR64RegClass);
12839 case X86::ATOMNAND64:
12840 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND64rr,
12841 X86::AND64ri32, X86::MOV64rm,
12843 X86::NOT64r, X86::RAX,
12844 &X86::GR64RegClass, true);
12845 case X86::ATOMMIN64:
12846 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL64rr);
12847 case X86::ATOMMAX64:
12848 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG64rr);
12849 case X86::ATOMUMIN64:
12850 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB64rr);
12851 case X86::ATOMUMAX64:
12852 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA64rr);
12854 // This group does 64-bit operations on a 32-bit host.
12855 case X86::ATOMAND6432:
12856 return EmitAtomicBit6432WithCustomInserter(MI, BB,
12857 X86::AND32rr, X86::AND32rr,
12858 X86::AND32ri, X86::AND32ri,
12860 case X86::ATOMOR6432:
12861 return EmitAtomicBit6432WithCustomInserter(MI, BB,
12862 X86::OR32rr, X86::OR32rr,
12863 X86::OR32ri, X86::OR32ri,
12865 case X86::ATOMXOR6432:
12866 return EmitAtomicBit6432WithCustomInserter(MI, BB,
12867 X86::XOR32rr, X86::XOR32rr,
12868 X86::XOR32ri, X86::XOR32ri,
12870 case X86::ATOMNAND6432:
12871 return EmitAtomicBit6432WithCustomInserter(MI, BB,
12872 X86::AND32rr, X86::AND32rr,
12873 X86::AND32ri, X86::AND32ri,
12875 case X86::ATOMADD6432:
12876 return EmitAtomicBit6432WithCustomInserter(MI, BB,
12877 X86::ADD32rr, X86::ADC32rr,
12878 X86::ADD32ri, X86::ADC32ri,
12880 case X86::ATOMSUB6432:
12881 return EmitAtomicBit6432WithCustomInserter(MI, BB,
12882 X86::SUB32rr, X86::SBB32rr,
12883 X86::SUB32ri, X86::SBB32ri,
12885 case X86::ATOMSWAP6432:
12886 return EmitAtomicBit6432WithCustomInserter(MI, BB,
12887 X86::MOV32rr, X86::MOV32rr,
12888 X86::MOV32ri, X86::MOV32ri,
12890 case X86::VASTART_SAVE_XMM_REGS:
12891 return EmitVAStartSaveXMMRegsWithCustomInserter(MI, BB);
12893 case X86::VAARG_64:
12894 return EmitVAARG64WithCustomInserter(MI, BB);
12898 //===----------------------------------------------------------------------===//
12899 // X86 Optimization Hooks
12900 //===----------------------------------------------------------------------===//
12902 void X86TargetLowering::computeMaskedBitsForTargetNode(const SDValue Op,
12905 const SelectionDAG &DAG,
12906 unsigned Depth) const {
12907 unsigned BitWidth = KnownZero.getBitWidth();
12908 unsigned Opc = Op.getOpcode();
12909 assert((Opc >= ISD::BUILTIN_OP_END ||
12910 Opc == ISD::INTRINSIC_WO_CHAIN ||
12911 Opc == ISD::INTRINSIC_W_CHAIN ||
12912 Opc == ISD::INTRINSIC_VOID) &&
12913 "Should use MaskedValueIsZero if you don't know whether Op"
12914 " is a target node!");
12916 KnownZero = KnownOne = APInt(BitWidth, 0); // Don't know anything.
12930 // These nodes' second result is a boolean.
12931 if (Op.getResNo() == 0)
12934 case X86ISD::SETCC:
12935 KnownZero |= APInt::getHighBitsSet(BitWidth, BitWidth - 1);
12937 case ISD::INTRINSIC_WO_CHAIN: {
12938 unsigned IntId = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
12939 unsigned NumLoBits = 0;
12942 case Intrinsic::x86_sse_movmsk_ps:
12943 case Intrinsic::x86_avx_movmsk_ps_256:
12944 case Intrinsic::x86_sse2_movmsk_pd:
12945 case Intrinsic::x86_avx_movmsk_pd_256:
12946 case Intrinsic::x86_mmx_pmovmskb:
12947 case Intrinsic::x86_sse2_pmovmskb_128:
12948 case Intrinsic::x86_avx2_pmovmskb: {
12949 // High bits of movmskp{s|d}, pmovmskb are known zero.
12951 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
12952 case Intrinsic::x86_sse_movmsk_ps: NumLoBits = 4; break;
12953 case Intrinsic::x86_avx_movmsk_ps_256: NumLoBits = 8; break;
12954 case Intrinsic::x86_sse2_movmsk_pd: NumLoBits = 2; break;
12955 case Intrinsic::x86_avx_movmsk_pd_256: NumLoBits = 4; break;
12956 case Intrinsic::x86_mmx_pmovmskb: NumLoBits = 8; break;
12957 case Intrinsic::x86_sse2_pmovmskb_128: NumLoBits = 16; break;
12958 case Intrinsic::x86_avx2_pmovmskb: NumLoBits = 32; break;
12960 KnownZero = APInt::getHighBitsSet(BitWidth, BitWidth - NumLoBits);
12969 unsigned X86TargetLowering::ComputeNumSignBitsForTargetNode(SDValue Op,
12970 unsigned Depth) const {
12971 // SETCC_CARRY sets the dest to ~0 for true or 0 for false.
12972 if (Op.getOpcode() == X86ISD::SETCC_CARRY)
12973 return Op.getValueType().getScalarType().getSizeInBits();
12979 /// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the
12980 /// node is a GlobalAddress + offset.
12981 bool X86TargetLowering::isGAPlusOffset(SDNode *N,
12982 const GlobalValue* &GA,
12983 int64_t &Offset) const {
12984 if (N->getOpcode() == X86ISD::Wrapper) {
12985 if (isa<GlobalAddressSDNode>(N->getOperand(0))) {
12986 GA = cast<GlobalAddressSDNode>(N->getOperand(0))->getGlobal();
12987 Offset = cast<GlobalAddressSDNode>(N->getOperand(0))->getOffset();
12991 return TargetLowering::isGAPlusOffset(N, GA, Offset);
12994 /// isShuffleHigh128VectorInsertLow - Checks whether the shuffle node is the
12995 /// same as extracting the high 128-bit part of 256-bit vector and then
12996 /// inserting the result into the low part of a new 256-bit vector
12997 static bool isShuffleHigh128VectorInsertLow(ShuffleVectorSDNode *SVOp) {
12998 EVT VT = SVOp->getValueType(0);
12999 unsigned NumElems = VT.getVectorNumElements();
13001 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
13002 for (unsigned i = 0, j = NumElems/2; i != NumElems/2; ++i, ++j)
13003 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) ||
13004 SVOp->getMaskElt(j) >= 0)
13010 /// isShuffleLow128VectorInsertHigh - Checks whether the shuffle node is the
13011 /// same as extracting the low 128-bit part of 256-bit vector and then
13012 /// inserting the result into the high part of a new 256-bit vector
13013 static bool isShuffleLow128VectorInsertHigh(ShuffleVectorSDNode *SVOp) {
13014 EVT VT = SVOp->getValueType(0);
13015 unsigned NumElems = VT.getVectorNumElements();
13017 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
13018 for (unsigned i = NumElems/2, j = 0; i != NumElems; ++i, ++j)
13019 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) ||
13020 SVOp->getMaskElt(j) >= 0)
13026 /// PerformShuffleCombine256 - Performs shuffle combines for 256-bit vectors.
13027 static SDValue PerformShuffleCombine256(SDNode *N, SelectionDAG &DAG,
13028 TargetLowering::DAGCombinerInfo &DCI,
13029 const X86Subtarget* Subtarget) {
13030 DebugLoc dl = N->getDebugLoc();
13031 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
13032 SDValue V1 = SVOp->getOperand(0);
13033 SDValue V2 = SVOp->getOperand(1);
13034 EVT VT = SVOp->getValueType(0);
13035 unsigned NumElems = VT.getVectorNumElements();
13037 if (V1.getOpcode() == ISD::CONCAT_VECTORS &&
13038 V2.getOpcode() == ISD::CONCAT_VECTORS) {
13042 // V UNDEF BUILD_VECTOR UNDEF
13044 // CONCAT_VECTOR CONCAT_VECTOR
13047 // RESULT: V + zero extended
13049 if (V2.getOperand(0).getOpcode() != ISD::BUILD_VECTOR ||
13050 V2.getOperand(1).getOpcode() != ISD::UNDEF ||
13051 V1.getOperand(1).getOpcode() != ISD::UNDEF)
13054 if (!ISD::isBuildVectorAllZeros(V2.getOperand(0).getNode()))
13057 // To match the shuffle mask, the first half of the mask should
13058 // be exactly the first vector, and all the rest a splat with the
13059 // first element of the second one.
13060 for (unsigned i = 0; i != NumElems/2; ++i)
13061 if (!isUndefOrEqual(SVOp->getMaskElt(i), i) ||
13062 !isUndefOrEqual(SVOp->getMaskElt(i+NumElems/2), NumElems))
13065 // If V1 is coming from a vector load then just fold to a VZEXT_LOAD.
13066 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(V1.getOperand(0))) {
13067 if (Ld->hasNUsesOfValue(1, 0)) {
13068 SDVTList Tys = DAG.getVTList(MVT::v4i64, MVT::Other);
13069 SDValue Ops[] = { Ld->getChain(), Ld->getBasePtr() };
13071 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, dl, Tys, Ops, 2,
13073 Ld->getPointerInfo(),
13074 Ld->getAlignment(),
13075 false/*isVolatile*/, true/*ReadMem*/,
13076 false/*WriteMem*/);
13077 return DAG.getNode(ISD::BITCAST, dl, VT, ResNode);
13081 // Emit a zeroed vector and insert the desired subvector on its
13083 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
13084 SDValue InsV = Insert128BitVector(Zeros, V1.getOperand(0), 0, DAG, dl);
13085 return DCI.CombineTo(N, InsV);
13088 //===--------------------------------------------------------------------===//
13089 // Combine some shuffles into subvector extracts and inserts:
13092 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
13093 if (isShuffleHigh128VectorInsertLow(SVOp)) {
13094 SDValue V = Extract128BitVector(V1, NumElems/2, DAG, dl);
13095 SDValue InsV = Insert128BitVector(DAG.getUNDEF(VT), V, 0, DAG, dl);
13096 return DCI.CombineTo(N, InsV);
13099 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
13100 if (isShuffleLow128VectorInsertHigh(SVOp)) {
13101 SDValue V = Extract128BitVector(V1, 0, DAG, dl);
13102 SDValue InsV = Insert128BitVector(DAG.getUNDEF(VT), V, NumElems/2, DAG, dl);
13103 return DCI.CombineTo(N, InsV);
13109 /// PerformShuffleCombine - Performs several different shuffle combines.
13110 static SDValue PerformShuffleCombine(SDNode *N, SelectionDAG &DAG,
13111 TargetLowering::DAGCombinerInfo &DCI,
13112 const X86Subtarget *Subtarget) {
13113 DebugLoc dl = N->getDebugLoc();
13114 EVT VT = N->getValueType(0);
13116 // Don't create instructions with illegal types after legalize types has run.
13117 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
13118 if (!DCI.isBeforeLegalize() && !TLI.isTypeLegal(VT.getVectorElementType()))
13121 // Combine 256-bit vector shuffles. This is only profitable when in AVX mode
13122 if (Subtarget->hasAVX() && VT.getSizeInBits() == 256 &&
13123 N->getOpcode() == ISD::VECTOR_SHUFFLE)
13124 return PerformShuffleCombine256(N, DAG, DCI, Subtarget);
13126 // Only handle 128 wide vector from here on.
13127 if (VT.getSizeInBits() != 128)
13130 // Combine a vector_shuffle that is equal to build_vector load1, load2, load3,
13131 // load4, <0, 1, 2, 3> into a 128-bit load if the load addresses are
13132 // consecutive, non-overlapping, and in the right order.
13133 SmallVector<SDValue, 16> Elts;
13134 for (unsigned i = 0, e = VT.getVectorNumElements(); i != e; ++i)
13135 Elts.push_back(getShuffleScalarElt(N, i, DAG, 0));
13137 return EltsFromConsecutiveLoads(VT, Elts, dl, DAG);
13141 /// DCI, PerformTruncateCombine - Converts truncate operation to
13142 /// a sequence of vector shuffle operations.
13143 /// It is possible when we truncate 256-bit vector to 128-bit vector
13145 SDValue X86TargetLowering::PerformTruncateCombine(SDNode *N, SelectionDAG &DAG,
13146 DAGCombinerInfo &DCI) const {
13147 if (!DCI.isBeforeLegalizeOps())
13150 if (!Subtarget->hasAVX())
13153 EVT VT = N->getValueType(0);
13154 SDValue Op = N->getOperand(0);
13155 EVT OpVT = Op.getValueType();
13156 DebugLoc dl = N->getDebugLoc();
13158 if ((VT == MVT::v4i32) && (OpVT == MVT::v4i64)) {
13160 if (Subtarget->hasAVX2()) {
13161 // AVX2: v4i64 -> v4i32
13164 static const int ShufMask[] = {0, 2, 4, 6, -1, -1, -1, -1};
13166 Op = DAG.getNode(ISD::BITCAST, dl, MVT::v8i32, Op);
13167 Op = DAG.getVectorShuffle(MVT::v8i32, dl, Op, DAG.getUNDEF(MVT::v8i32),
13170 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, Op,
13171 DAG.getIntPtrConstant(0));
13174 // AVX: v4i64 -> v4i32
13175 SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v2i64, Op,
13176 DAG.getIntPtrConstant(0));
13178 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v2i64, Op,
13179 DAG.getIntPtrConstant(2));
13181 OpLo = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, OpLo);
13182 OpHi = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, OpHi);
13185 static const int ShufMask1[] = {0, 2, 0, 0};
13187 OpLo = DAG.getVectorShuffle(VT, dl, OpLo, DAG.getUNDEF(VT), ShufMask1);
13188 OpHi = DAG.getVectorShuffle(VT, dl, OpHi, DAG.getUNDEF(VT), ShufMask1);
13191 static const int ShufMask2[] = {0, 1, 4, 5};
13193 return DAG.getVectorShuffle(VT, dl, OpLo, OpHi, ShufMask2);
13196 if ((VT == MVT::v8i16) && (OpVT == MVT::v8i32)) {
13198 if (Subtarget->hasAVX2()) {
13199 // AVX2: v8i32 -> v8i16
13201 Op = DAG.getNode(ISD::BITCAST, dl, MVT::v32i8, Op);
13204 SmallVector<SDValue,32> pshufbMask;
13205 for (unsigned i = 0; i < 2; ++i) {
13206 pshufbMask.push_back(DAG.getConstant(0x0, MVT::i8));
13207 pshufbMask.push_back(DAG.getConstant(0x1, MVT::i8));
13208 pshufbMask.push_back(DAG.getConstant(0x4, MVT::i8));
13209 pshufbMask.push_back(DAG.getConstant(0x5, MVT::i8));
13210 pshufbMask.push_back(DAG.getConstant(0x8, MVT::i8));
13211 pshufbMask.push_back(DAG.getConstant(0x9, MVT::i8));
13212 pshufbMask.push_back(DAG.getConstant(0xc, MVT::i8));
13213 pshufbMask.push_back(DAG.getConstant(0xd, MVT::i8));
13214 for (unsigned j = 0; j < 8; ++j)
13215 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
13217 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v32i8,
13218 &pshufbMask[0], 32);
13219 Op = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v32i8, Op, BV);
13221 Op = DAG.getNode(ISD::BITCAST, dl, MVT::v4i64, Op);
13223 static const int ShufMask[] = {0, 2, -1, -1};
13224 Op = DAG.getVectorShuffle(MVT::v4i64, dl, Op, DAG.getUNDEF(MVT::v4i64),
13227 Op = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v2i64, Op,
13228 DAG.getIntPtrConstant(0));
13230 return DAG.getNode(ISD::BITCAST, dl, VT, Op);
13233 SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i32, Op,
13234 DAG.getIntPtrConstant(0));
13236 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i32, Op,
13237 DAG.getIntPtrConstant(4));
13239 OpLo = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, OpLo);
13240 OpHi = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, OpHi);
13243 static const int ShufMask1[] = {0, 1, 4, 5, 8, 9, 12, 13,
13244 -1, -1, -1, -1, -1, -1, -1, -1};
13246 OpLo = DAG.getVectorShuffle(MVT::v16i8, dl, OpLo, DAG.getUNDEF(MVT::v16i8),
13248 OpHi = DAG.getVectorShuffle(MVT::v16i8, dl, OpHi, DAG.getUNDEF(MVT::v16i8),
13251 OpLo = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, OpLo);
13252 OpHi = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, OpHi);
13255 static const int ShufMask2[] = {0, 1, 4, 5};
13257 SDValue res = DAG.getVectorShuffle(MVT::v4i32, dl, OpLo, OpHi, ShufMask2);
13258 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, res);
13264 /// XFormVExtractWithShuffleIntoLoad - Check if a vector extract from a target
13265 /// specific shuffle of a load can be folded into a single element load.
13266 /// Similar handling for VECTOR_SHUFFLE is performed by DAGCombiner, but
13267 /// shuffles have been customed lowered so we need to handle those here.
13268 static SDValue XFormVExtractWithShuffleIntoLoad(SDNode *N, SelectionDAG &DAG,
13269 TargetLowering::DAGCombinerInfo &DCI) {
13270 if (DCI.isBeforeLegalizeOps())
13273 SDValue InVec = N->getOperand(0);
13274 SDValue EltNo = N->getOperand(1);
13276 if (!isa<ConstantSDNode>(EltNo))
13279 EVT VT = InVec.getValueType();
13281 bool HasShuffleIntoBitcast = false;
13282 if (InVec.getOpcode() == ISD::BITCAST) {
13283 // Don't duplicate a load with other uses.
13284 if (!InVec.hasOneUse())
13286 EVT BCVT = InVec.getOperand(0).getValueType();
13287 if (BCVT.getVectorNumElements() != VT.getVectorNumElements())
13289 InVec = InVec.getOperand(0);
13290 HasShuffleIntoBitcast = true;
13293 if (!isTargetShuffle(InVec.getOpcode()))
13296 // Don't duplicate a load with other uses.
13297 if (!InVec.hasOneUse())
13300 SmallVector<int, 16> ShuffleMask;
13302 if (!getTargetShuffleMask(InVec.getNode(), VT.getSimpleVT(), ShuffleMask,
13306 // Select the input vector, guarding against out of range extract vector.
13307 unsigned NumElems = VT.getVectorNumElements();
13308 int Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();
13309 int Idx = (Elt > (int)NumElems) ? -1 : ShuffleMask[Elt];
13310 SDValue LdNode = (Idx < (int)NumElems) ? InVec.getOperand(0)
13311 : InVec.getOperand(1);
13313 // If inputs to shuffle are the same for both ops, then allow 2 uses
13314 unsigned AllowedUses = InVec.getOperand(0) == InVec.getOperand(1) ? 2 : 1;
13316 if (LdNode.getOpcode() == ISD::BITCAST) {
13317 // Don't duplicate a load with other uses.
13318 if (!LdNode.getNode()->hasNUsesOfValue(AllowedUses, 0))
13321 AllowedUses = 1; // only allow 1 load use if we have a bitcast
13322 LdNode = LdNode.getOperand(0);
13325 if (!ISD::isNormalLoad(LdNode.getNode()))
13328 LoadSDNode *LN0 = cast<LoadSDNode>(LdNode);
13330 if (!LN0 ||!LN0->hasNUsesOfValue(AllowedUses, 0) || LN0->isVolatile())
13333 if (HasShuffleIntoBitcast) {
13334 // If there's a bitcast before the shuffle, check if the load type and
13335 // alignment is valid.
13336 unsigned Align = LN0->getAlignment();
13337 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
13338 unsigned NewAlign = TLI.getTargetData()->
13339 getABITypeAlignment(VT.getTypeForEVT(*DAG.getContext()));
13341 if (NewAlign > Align || !TLI.isOperationLegalOrCustom(ISD::LOAD, VT))
13345 // All checks match so transform back to vector_shuffle so that DAG combiner
13346 // can finish the job
13347 DebugLoc dl = N->getDebugLoc();
13349 // Create shuffle node taking into account the case that its a unary shuffle
13350 SDValue Shuffle = (UnaryShuffle) ? DAG.getUNDEF(VT) : InVec.getOperand(1);
13351 Shuffle = DAG.getVectorShuffle(InVec.getValueType(), dl,
13352 InVec.getOperand(0), Shuffle,
13354 Shuffle = DAG.getNode(ISD::BITCAST, dl, VT, Shuffle);
13355 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, N->getValueType(0), Shuffle,
13359 /// PerformEXTRACT_VECTOR_ELTCombine - Detect vector gather/scatter index
13360 /// generation and convert it from being a bunch of shuffles and extracts
13361 /// to a simple store and scalar loads to extract the elements.
13362 static SDValue PerformEXTRACT_VECTOR_ELTCombine(SDNode *N, SelectionDAG &DAG,
13363 TargetLowering::DAGCombinerInfo &DCI) {
13364 SDValue NewOp = XFormVExtractWithShuffleIntoLoad(N, DAG, DCI);
13365 if (NewOp.getNode())
13368 SDValue InputVector = N->getOperand(0);
13370 // Only operate on vectors of 4 elements, where the alternative shuffling
13371 // gets to be more expensive.
13372 if (InputVector.getValueType() != MVT::v4i32)
13375 // Check whether every use of InputVector is an EXTRACT_VECTOR_ELT with a
13376 // single use which is a sign-extend or zero-extend, and all elements are
13378 SmallVector<SDNode *, 4> Uses;
13379 unsigned ExtractedElements = 0;
13380 for (SDNode::use_iterator UI = InputVector.getNode()->use_begin(),
13381 UE = InputVector.getNode()->use_end(); UI != UE; ++UI) {
13382 if (UI.getUse().getResNo() != InputVector.getResNo())
13385 SDNode *Extract = *UI;
13386 if (Extract->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
13389 if (Extract->getValueType(0) != MVT::i32)
13391 if (!Extract->hasOneUse())
13393 if (Extract->use_begin()->getOpcode() != ISD::SIGN_EXTEND &&
13394 Extract->use_begin()->getOpcode() != ISD::ZERO_EXTEND)
13396 if (!isa<ConstantSDNode>(Extract->getOperand(1)))
13399 // Record which element was extracted.
13400 ExtractedElements |=
13401 1 << cast<ConstantSDNode>(Extract->getOperand(1))->getZExtValue();
13403 Uses.push_back(Extract);
13406 // If not all the elements were used, this may not be worthwhile.
13407 if (ExtractedElements != 15)
13410 // Ok, we've now decided to do the transformation.
13411 DebugLoc dl = InputVector.getDebugLoc();
13413 // Store the value to a temporary stack slot.
13414 SDValue StackPtr = DAG.CreateStackTemporary(InputVector.getValueType());
13415 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, InputVector, StackPtr,
13416 MachinePointerInfo(), false, false, 0);
13418 // Replace each use (extract) with a load of the appropriate element.
13419 for (SmallVectorImpl<SDNode *>::iterator UI = Uses.begin(),
13420 UE = Uses.end(); UI != UE; ++UI) {
13421 SDNode *Extract = *UI;
13423 // cOMpute the element's address.
13424 SDValue Idx = Extract->getOperand(1);
13426 InputVector.getValueType().getVectorElementType().getSizeInBits()/8;
13427 uint64_t Offset = EltSize * cast<ConstantSDNode>(Idx)->getZExtValue();
13428 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
13429 SDValue OffsetVal = DAG.getConstant(Offset, TLI.getPointerTy());
13431 SDValue ScalarAddr = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(),
13432 StackPtr, OffsetVal);
13434 // Load the scalar.
13435 SDValue LoadScalar = DAG.getLoad(Extract->getValueType(0), dl, Ch,
13436 ScalarAddr, MachinePointerInfo(),
13437 false, false, false, 0);
13439 // Replace the exact with the load.
13440 DAG.ReplaceAllUsesOfValueWith(SDValue(Extract, 0), LoadScalar);
13443 // The replacement was made in place; don't return anything.
13447 /// PerformSELECTCombine - Do target-specific dag combines on SELECT and VSELECT
13449 static SDValue PerformSELECTCombine(SDNode *N, SelectionDAG &DAG,
13450 TargetLowering::DAGCombinerInfo &DCI,
13451 const X86Subtarget *Subtarget) {
13454 DebugLoc DL = N->getDebugLoc();
13455 SDValue Cond = N->getOperand(0);
13456 // Get the LHS/RHS of the select.
13457 SDValue LHS = N->getOperand(1);
13458 SDValue RHS = N->getOperand(2);
13459 EVT VT = LHS.getValueType();
13461 // If we have SSE[12] support, try to form min/max nodes. SSE min/max
13462 // instructions match the semantics of the common C idiom x<y?x:y but not
13463 // x<=y?x:y, because of how they handle negative zero (which can be
13464 // ignored in unsafe-math mode).
13465 if (Cond.getOpcode() == ISD::SETCC && VT.isFloatingPoint() &&
13466 VT != MVT::f80 && DAG.getTargetLoweringInfo().isTypeLegal(VT) &&
13467 (Subtarget->hasSSE2() ||
13468 (Subtarget->hasSSE1() && VT.getScalarType() == MVT::f32))) {
13469 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
13471 unsigned Opcode = 0;
13472 // Check for x CC y ? x : y.
13473 if (DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
13474 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
13478 // Converting this to a min would handle NaNs incorrectly, and swapping
13479 // the operands would cause it to handle comparisons between positive
13480 // and negative zero incorrectly.
13481 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
13482 if (!DAG.getTarget().Options.UnsafeFPMath &&
13483 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
13485 std::swap(LHS, RHS);
13487 Opcode = X86ISD::FMIN;
13490 // Converting this to a min would handle comparisons between positive
13491 // and negative zero incorrectly.
13492 if (!DAG.getTarget().Options.UnsafeFPMath &&
13493 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
13495 Opcode = X86ISD::FMIN;
13498 // Converting this to a min would handle both negative zeros and NaNs
13499 // incorrectly, but we can swap the operands to fix both.
13500 std::swap(LHS, RHS);
13504 Opcode = X86ISD::FMIN;
13508 // Converting this to a max would handle comparisons between positive
13509 // and negative zero incorrectly.
13510 if (!DAG.getTarget().Options.UnsafeFPMath &&
13511 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
13513 Opcode = X86ISD::FMAX;
13516 // Converting this to a max would handle NaNs incorrectly, and swapping
13517 // the operands would cause it to handle comparisons between positive
13518 // and negative zero incorrectly.
13519 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
13520 if (!DAG.getTarget().Options.UnsafeFPMath &&
13521 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
13523 std::swap(LHS, RHS);
13525 Opcode = X86ISD::FMAX;
13528 // Converting this to a max would handle both negative zeros and NaNs
13529 // incorrectly, but we can swap the operands to fix both.
13530 std::swap(LHS, RHS);
13534 Opcode = X86ISD::FMAX;
13537 // Check for x CC y ? y : x -- a min/max with reversed arms.
13538 } else if (DAG.isEqualTo(LHS, Cond.getOperand(1)) &&
13539 DAG.isEqualTo(RHS, Cond.getOperand(0))) {
13543 // Converting this to a min would handle comparisons between positive
13544 // and negative zero incorrectly, and swapping the operands would
13545 // cause it to handle NaNs incorrectly.
13546 if (!DAG.getTarget().Options.UnsafeFPMath &&
13547 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS))) {
13548 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
13550 std::swap(LHS, RHS);
13552 Opcode = X86ISD::FMIN;
13555 // Converting this to a min would handle NaNs incorrectly.
13556 if (!DAG.getTarget().Options.UnsafeFPMath &&
13557 (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)))
13559 Opcode = X86ISD::FMIN;
13562 // Converting this to a min would handle both negative zeros and NaNs
13563 // incorrectly, but we can swap the operands to fix both.
13564 std::swap(LHS, RHS);
13568 Opcode = X86ISD::FMIN;
13572 // Converting this to a max would handle NaNs incorrectly.
13573 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
13575 Opcode = X86ISD::FMAX;
13578 // Converting this to a max would handle comparisons between positive
13579 // and negative zero incorrectly, and swapping the operands would
13580 // cause it to handle NaNs incorrectly.
13581 if (!DAG.getTarget().Options.UnsafeFPMath &&
13582 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS)) {
13583 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
13585 std::swap(LHS, RHS);
13587 Opcode = X86ISD::FMAX;
13590 // Converting this to a max would handle both negative zeros and NaNs
13591 // incorrectly, but we can swap the operands to fix both.
13592 std::swap(LHS, RHS);
13596 Opcode = X86ISD::FMAX;
13602 return DAG.getNode(Opcode, DL, N->getValueType(0), LHS, RHS);
13605 // If this is a select between two integer constants, try to do some
13607 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(LHS)) {
13608 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(RHS))
13609 // Don't do this for crazy integer types.
13610 if (DAG.getTargetLoweringInfo().isTypeLegal(LHS.getValueType())) {
13611 // If this is efficiently invertible, canonicalize the LHSC/RHSC values
13612 // so that TrueC (the true value) is larger than FalseC.
13613 bool NeedsCondInvert = false;
13615 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue()) &&
13616 // Efficiently invertible.
13617 (Cond.getOpcode() == ISD::SETCC || // setcc -> invertible.
13618 (Cond.getOpcode() == ISD::XOR && // xor(X, C) -> invertible.
13619 isa<ConstantSDNode>(Cond.getOperand(1))))) {
13620 NeedsCondInvert = true;
13621 std::swap(TrueC, FalseC);
13624 // Optimize C ? 8 : 0 -> zext(C) << 3. Likewise for any pow2/0.
13625 if (FalseC->getAPIntValue() == 0 &&
13626 TrueC->getAPIntValue().isPowerOf2()) {
13627 if (NeedsCondInvert) // Invert the condition if needed.
13628 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
13629 DAG.getConstant(1, Cond.getValueType()));
13631 // Zero extend the condition if needed.
13632 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, LHS.getValueType(), Cond);
13634 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
13635 return DAG.getNode(ISD::SHL, DL, LHS.getValueType(), Cond,
13636 DAG.getConstant(ShAmt, MVT::i8));
13639 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst.
13640 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
13641 if (NeedsCondInvert) // Invert the condition if needed.
13642 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
13643 DAG.getConstant(1, Cond.getValueType()));
13645 // Zero extend the condition if needed.
13646 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
13647 FalseC->getValueType(0), Cond);
13648 return DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
13649 SDValue(FalseC, 0));
13652 // Optimize cases that will turn into an LEA instruction. This requires
13653 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
13654 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
13655 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
13656 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
13658 bool isFastMultiplier = false;
13660 switch ((unsigned char)Diff) {
13662 case 1: // result = add base, cond
13663 case 2: // result = lea base( , cond*2)
13664 case 3: // result = lea base(cond, cond*2)
13665 case 4: // result = lea base( , cond*4)
13666 case 5: // result = lea base(cond, cond*4)
13667 case 8: // result = lea base( , cond*8)
13668 case 9: // result = lea base(cond, cond*8)
13669 isFastMultiplier = true;
13674 if (isFastMultiplier) {
13675 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
13676 if (NeedsCondInvert) // Invert the condition if needed.
13677 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
13678 DAG.getConstant(1, Cond.getValueType()));
13680 // Zero extend the condition if needed.
13681 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
13683 // Scale the condition by the difference.
13685 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
13686 DAG.getConstant(Diff, Cond.getValueType()));
13688 // Add the base if non-zero.
13689 if (FalseC->getAPIntValue() != 0)
13690 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
13691 SDValue(FalseC, 0));
13698 // Canonicalize max and min:
13699 // (x > y) ? x : y -> (x >= y) ? x : y
13700 // (x < y) ? x : y -> (x <= y) ? x : y
13701 // This allows use of COND_S / COND_NS (see TranslateX86CC) which eliminates
13702 // the need for an extra compare
13703 // against zero. e.g.
13704 // (x - y) > 0 : (x - y) ? 0 -> (x - y) >= 0 : (x - y) ? 0
13706 // testl %edi, %edi
13708 // cmovgl %edi, %eax
13712 // cmovsl %eax, %edi
13713 if (N->getOpcode() == ISD::SELECT && Cond.getOpcode() == ISD::SETCC &&
13714 DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
13715 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
13716 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
13721 ISD::CondCode NewCC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGE;
13722 Cond = DAG.getSetCC(Cond.getDebugLoc(), Cond.getValueType(),
13723 Cond.getOperand(0), Cond.getOperand(1), NewCC);
13724 return DAG.getNode(ISD::SELECT, DL, VT, Cond, LHS, RHS);
13729 // If we know that this node is legal then we know that it is going to be
13730 // matched by one of the SSE/AVX BLEND instructions. These instructions only
13731 // depend on the highest bit in each word. Try to use SimplifyDemandedBits
13732 // to simplify previous instructions.
13733 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
13734 if (N->getOpcode() == ISD::VSELECT && DCI.isBeforeLegalizeOps() &&
13735 !DCI.isBeforeLegalize() &&
13736 TLI.isOperationLegal(ISD::VSELECT, VT)) {
13737 unsigned BitWidth = Cond.getValueType().getScalarType().getSizeInBits();
13738 assert(BitWidth >= 8 && BitWidth <= 64 && "Invalid mask size");
13739 APInt DemandedMask = APInt::getHighBitsSet(BitWidth, 1);
13741 APInt KnownZero, KnownOne;
13742 TargetLowering::TargetLoweringOpt TLO(DAG, DCI.isBeforeLegalize(),
13743 DCI.isBeforeLegalizeOps());
13744 if (TLO.ShrinkDemandedConstant(Cond, DemandedMask) ||
13745 TLI.SimplifyDemandedBits(Cond, DemandedMask, KnownZero, KnownOne, TLO))
13746 DCI.CommitTargetLoweringOpt(TLO);
13752 /// Optimize X86ISD::CMOV [LHS, RHS, CONDCODE (e.g. X86::COND_NE), CONDVAL]
13753 static SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG,
13754 TargetLowering::DAGCombinerInfo &DCI) {
13755 DebugLoc DL = N->getDebugLoc();
13757 // If the flag operand isn't dead, don't touch this CMOV.
13758 if (N->getNumValues() == 2 && !SDValue(N, 1).use_empty())
13761 SDValue FalseOp = N->getOperand(0);
13762 SDValue TrueOp = N->getOperand(1);
13763 X86::CondCode CC = (X86::CondCode)N->getConstantOperandVal(2);
13764 SDValue Cond = N->getOperand(3);
13765 if (CC == X86::COND_E || CC == X86::COND_NE) {
13766 switch (Cond.getOpcode()) {
13770 // If operand of BSR / BSF are proven never zero, then ZF cannot be set.
13771 if (DAG.isKnownNeverZero(Cond.getOperand(0)))
13772 return (CC == X86::COND_E) ? FalseOp : TrueOp;
13776 // If this is a select between two integer constants, try to do some
13777 // optimizations. Note that the operands are ordered the opposite of SELECT
13779 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(TrueOp)) {
13780 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(FalseOp)) {
13781 // Canonicalize the TrueC/FalseC values so that TrueC (the true value) is
13782 // larger than FalseC (the false value).
13783 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue())) {
13784 CC = X86::GetOppositeBranchCondition(CC);
13785 std::swap(TrueC, FalseC);
13788 // Optimize C ? 8 : 0 -> zext(setcc(C)) << 3. Likewise for any pow2/0.
13789 // This is efficient for any integer data type (including i8/i16) and
13791 if (FalseC->getAPIntValue() == 0 && TrueC->getAPIntValue().isPowerOf2()) {
13792 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
13793 DAG.getConstant(CC, MVT::i8), Cond);
13795 // Zero extend the condition if needed.
13796 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, TrueC->getValueType(0), Cond);
13798 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
13799 Cond = DAG.getNode(ISD::SHL, DL, Cond.getValueType(), Cond,
13800 DAG.getConstant(ShAmt, MVT::i8));
13801 if (N->getNumValues() == 2) // Dead flag value?
13802 return DCI.CombineTo(N, Cond, SDValue());
13806 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst. This is efficient
13807 // for any integer data type, including i8/i16.
13808 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
13809 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
13810 DAG.getConstant(CC, MVT::i8), Cond);
13812 // Zero extend the condition if needed.
13813 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
13814 FalseC->getValueType(0), Cond);
13815 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
13816 SDValue(FalseC, 0));
13818 if (N->getNumValues() == 2) // Dead flag value?
13819 return DCI.CombineTo(N, Cond, SDValue());
13823 // Optimize cases that will turn into an LEA instruction. This requires
13824 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
13825 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
13826 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
13827 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
13829 bool isFastMultiplier = false;
13831 switch ((unsigned char)Diff) {
13833 case 1: // result = add base, cond
13834 case 2: // result = lea base( , cond*2)
13835 case 3: // result = lea base(cond, cond*2)
13836 case 4: // result = lea base( , cond*4)
13837 case 5: // result = lea base(cond, cond*4)
13838 case 8: // result = lea base( , cond*8)
13839 case 9: // result = lea base(cond, cond*8)
13840 isFastMultiplier = true;
13845 if (isFastMultiplier) {
13846 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
13847 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
13848 DAG.getConstant(CC, MVT::i8), Cond);
13849 // Zero extend the condition if needed.
13850 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
13852 // Scale the condition by the difference.
13854 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
13855 DAG.getConstant(Diff, Cond.getValueType()));
13857 // Add the base if non-zero.
13858 if (FalseC->getAPIntValue() != 0)
13859 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
13860 SDValue(FalseC, 0));
13861 if (N->getNumValues() == 2) // Dead flag value?
13862 return DCI.CombineTo(N, Cond, SDValue());
13872 /// PerformMulCombine - Optimize a single multiply with constant into two
13873 /// in order to implement it with two cheaper instructions, e.g.
13874 /// LEA + SHL, LEA + LEA.
13875 static SDValue PerformMulCombine(SDNode *N, SelectionDAG &DAG,
13876 TargetLowering::DAGCombinerInfo &DCI) {
13877 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer())
13880 EVT VT = N->getValueType(0);
13881 if (VT != MVT::i64)
13884 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
13887 uint64_t MulAmt = C->getZExtValue();
13888 if (isPowerOf2_64(MulAmt) || MulAmt == 3 || MulAmt == 5 || MulAmt == 9)
13891 uint64_t MulAmt1 = 0;
13892 uint64_t MulAmt2 = 0;
13893 if ((MulAmt % 9) == 0) {
13895 MulAmt2 = MulAmt / 9;
13896 } else if ((MulAmt % 5) == 0) {
13898 MulAmt2 = MulAmt / 5;
13899 } else if ((MulAmt % 3) == 0) {
13901 MulAmt2 = MulAmt / 3;
13904 (isPowerOf2_64(MulAmt2) || MulAmt2 == 3 || MulAmt2 == 5 || MulAmt2 == 9)){
13905 DebugLoc DL = N->getDebugLoc();
13907 if (isPowerOf2_64(MulAmt2) &&
13908 !(N->hasOneUse() && N->use_begin()->getOpcode() == ISD::ADD))
13909 // If second multiplifer is pow2, issue it first. We want the multiply by
13910 // 3, 5, or 9 to be folded into the addressing mode unless the lone use
13912 std::swap(MulAmt1, MulAmt2);
13915 if (isPowerOf2_64(MulAmt1))
13916 NewMul = DAG.getNode(ISD::SHL, DL, VT, N->getOperand(0),
13917 DAG.getConstant(Log2_64(MulAmt1), MVT::i8));
13919 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, N->getOperand(0),
13920 DAG.getConstant(MulAmt1, VT));
13922 if (isPowerOf2_64(MulAmt2))
13923 NewMul = DAG.getNode(ISD::SHL, DL, VT, NewMul,
13924 DAG.getConstant(Log2_64(MulAmt2), MVT::i8));
13926 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, NewMul,
13927 DAG.getConstant(MulAmt2, VT));
13929 // Do not add new nodes to DAG combiner worklist.
13930 DCI.CombineTo(N, NewMul, false);
13935 static SDValue PerformSHLCombine(SDNode *N, SelectionDAG &DAG) {
13936 SDValue N0 = N->getOperand(0);
13937 SDValue N1 = N->getOperand(1);
13938 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
13939 EVT VT = N0.getValueType();
13941 // fold (shl (and (setcc_c), c1), c2) -> (and setcc_c, (c1 << c2))
13942 // since the result of setcc_c is all zero's or all ones.
13943 if (VT.isInteger() && !VT.isVector() &&
13944 N1C && N0.getOpcode() == ISD::AND &&
13945 N0.getOperand(1).getOpcode() == ISD::Constant) {
13946 SDValue N00 = N0.getOperand(0);
13947 if (N00.getOpcode() == X86ISD::SETCC_CARRY ||
13948 ((N00.getOpcode() == ISD::ANY_EXTEND ||
13949 N00.getOpcode() == ISD::ZERO_EXTEND) &&
13950 N00.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY)) {
13951 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
13952 APInt ShAmt = N1C->getAPIntValue();
13953 Mask = Mask.shl(ShAmt);
13955 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT,
13956 N00, DAG.getConstant(Mask, VT));
13961 // Hardware support for vector shifts is sparse which makes us scalarize the
13962 // vector operations in many cases. Also, on sandybridge ADD is faster than
13964 // (shl V, 1) -> add V,V
13965 if (isSplatVector(N1.getNode())) {
13966 assert(N0.getValueType().isVector() && "Invalid vector shift type");
13967 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1->getOperand(0));
13968 // We shift all of the values by one. In many cases we do not have
13969 // hardware support for this operation. This is better expressed as an ADD
13971 if (N1C && (1 == N1C->getZExtValue())) {
13972 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N0, N0);
13979 /// PerformShiftCombine - Transforms vector shift nodes to use vector shifts
13981 static SDValue PerformShiftCombine(SDNode* N, SelectionDAG &DAG,
13982 TargetLowering::DAGCombinerInfo &DCI,
13983 const X86Subtarget *Subtarget) {
13984 EVT VT = N->getValueType(0);
13985 if (N->getOpcode() == ISD::SHL) {
13986 SDValue V = PerformSHLCombine(N, DAG);
13987 if (V.getNode()) return V;
13990 // On X86 with SSE2 support, we can transform this to a vector shift if
13991 // all elements are shifted by the same amount. We can't do this in legalize
13992 // because the a constant vector is typically transformed to a constant pool
13993 // so we have no knowledge of the shift amount.
13994 if (!Subtarget->hasSSE2())
13997 if (VT != MVT::v2i64 && VT != MVT::v4i32 && VT != MVT::v8i16 &&
13998 (!Subtarget->hasAVX2() ||
13999 (VT != MVT::v4i64 && VT != MVT::v8i32 && VT != MVT::v16i16)))
14002 SDValue ShAmtOp = N->getOperand(1);
14003 EVT EltVT = VT.getVectorElementType();
14004 DebugLoc DL = N->getDebugLoc();
14005 SDValue BaseShAmt = SDValue();
14006 if (ShAmtOp.getOpcode() == ISD::BUILD_VECTOR) {
14007 unsigned NumElts = VT.getVectorNumElements();
14009 for (; i != NumElts; ++i) {
14010 SDValue Arg = ShAmtOp.getOperand(i);
14011 if (Arg.getOpcode() == ISD::UNDEF) continue;
14015 // Handle the case where the build_vector is all undef
14016 // FIXME: Should DAG allow this?
14020 for (; i != NumElts; ++i) {
14021 SDValue Arg = ShAmtOp.getOperand(i);
14022 if (Arg.getOpcode() == ISD::UNDEF) continue;
14023 if (Arg != BaseShAmt) {
14027 } else if (ShAmtOp.getOpcode() == ISD::VECTOR_SHUFFLE &&
14028 cast<ShuffleVectorSDNode>(ShAmtOp)->isSplat()) {
14029 SDValue InVec = ShAmtOp.getOperand(0);
14030 if (InVec.getOpcode() == ISD::BUILD_VECTOR) {
14031 unsigned NumElts = InVec.getValueType().getVectorNumElements();
14033 for (; i != NumElts; ++i) {
14034 SDValue Arg = InVec.getOperand(i);
14035 if (Arg.getOpcode() == ISD::UNDEF) continue;
14039 } else if (InVec.getOpcode() == ISD::INSERT_VECTOR_ELT) {
14040 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(InVec.getOperand(2))) {
14041 unsigned SplatIdx= cast<ShuffleVectorSDNode>(ShAmtOp)->getSplatIndex();
14042 if (C->getZExtValue() == SplatIdx)
14043 BaseShAmt = InVec.getOperand(1);
14046 if (BaseShAmt.getNode() == 0) {
14047 // Don't create instructions with illegal types after legalize
14049 if (!DAG.getTargetLoweringInfo().isTypeLegal(EltVT) &&
14050 !DCI.isBeforeLegalize())
14053 BaseShAmt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, EltVT, ShAmtOp,
14054 DAG.getIntPtrConstant(0));
14059 // The shift amount is an i32.
14060 if (EltVT.bitsGT(MVT::i32))
14061 BaseShAmt = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, BaseShAmt);
14062 else if (EltVT.bitsLT(MVT::i32))
14063 BaseShAmt = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i32, BaseShAmt);
14065 // The shift amount is identical so we can do a vector shift.
14066 SDValue ValOp = N->getOperand(0);
14067 switch (N->getOpcode()) {
14069 llvm_unreachable("Unknown shift opcode!");
14071 switch (VT.getSimpleVT().SimpleTy) {
14072 default: return SDValue();
14079 return getTargetVShiftNode(X86ISD::VSHLI, DL, VT, ValOp, BaseShAmt, DAG);
14082 switch (VT.getSimpleVT().SimpleTy) {
14083 default: return SDValue();
14088 return getTargetVShiftNode(X86ISD::VSRAI, DL, VT, ValOp, BaseShAmt, DAG);
14091 switch (VT.getSimpleVT().SimpleTy) {
14092 default: return SDValue();
14099 return getTargetVShiftNode(X86ISD::VSRLI, DL, VT, ValOp, BaseShAmt, DAG);
14105 // CMPEQCombine - Recognize the distinctive (AND (setcc ...) (setcc ..))
14106 // where both setccs reference the same FP CMP, and rewrite for CMPEQSS
14107 // and friends. Likewise for OR -> CMPNEQSS.
14108 static SDValue CMPEQCombine(SDNode *N, SelectionDAG &DAG,
14109 TargetLowering::DAGCombinerInfo &DCI,
14110 const X86Subtarget *Subtarget) {
14113 // SSE1 supports CMP{eq|ne}SS, and SSE2 added CMP{eq|ne}SD, but
14114 // we're requiring SSE2 for both.
14115 if (Subtarget->hasSSE2() && isAndOrOfSetCCs(SDValue(N, 0U), opcode)) {
14116 SDValue N0 = N->getOperand(0);
14117 SDValue N1 = N->getOperand(1);
14118 SDValue CMP0 = N0->getOperand(1);
14119 SDValue CMP1 = N1->getOperand(1);
14120 DebugLoc DL = N->getDebugLoc();
14122 // The SETCCs should both refer to the same CMP.
14123 if (CMP0.getOpcode() != X86ISD::CMP || CMP0 != CMP1)
14126 SDValue CMP00 = CMP0->getOperand(0);
14127 SDValue CMP01 = CMP0->getOperand(1);
14128 EVT VT = CMP00.getValueType();
14130 if (VT == MVT::f32 || VT == MVT::f64) {
14131 bool ExpectingFlags = false;
14132 // Check for any users that want flags:
14133 for (SDNode::use_iterator UI = N->use_begin(),
14135 !ExpectingFlags && UI != UE; ++UI)
14136 switch (UI->getOpcode()) {
14141 ExpectingFlags = true;
14143 case ISD::CopyToReg:
14144 case ISD::SIGN_EXTEND:
14145 case ISD::ZERO_EXTEND:
14146 case ISD::ANY_EXTEND:
14150 if (!ExpectingFlags) {
14151 enum X86::CondCode cc0 = (enum X86::CondCode)N0.getConstantOperandVal(0);
14152 enum X86::CondCode cc1 = (enum X86::CondCode)N1.getConstantOperandVal(0);
14154 if (cc1 == X86::COND_E || cc1 == X86::COND_NE) {
14155 X86::CondCode tmp = cc0;
14160 if ((cc0 == X86::COND_E && cc1 == X86::COND_NP) ||
14161 (cc0 == X86::COND_NE && cc1 == X86::COND_P)) {
14162 bool is64BitFP = (CMP00.getValueType() == MVT::f64);
14163 X86ISD::NodeType NTOperator = is64BitFP ?
14164 X86ISD::FSETCCsd : X86ISD::FSETCCss;
14165 // FIXME: need symbolic constants for these magic numbers.
14166 // See X86ATTInstPrinter.cpp:printSSECC().
14167 unsigned x86cc = (cc0 == X86::COND_E) ? 0 : 4;
14168 SDValue OnesOrZeroesF = DAG.getNode(NTOperator, DL, MVT::f32, CMP00, CMP01,
14169 DAG.getConstant(x86cc, MVT::i8));
14170 SDValue OnesOrZeroesI = DAG.getNode(ISD::BITCAST, DL, MVT::i32,
14172 SDValue ANDed = DAG.getNode(ISD::AND, DL, MVT::i32, OnesOrZeroesI,
14173 DAG.getConstant(1, MVT::i32));
14174 SDValue OneBitOfTruth = DAG.getNode(ISD::TRUNCATE, DL, MVT::i8, ANDed);
14175 return OneBitOfTruth;
14183 /// CanFoldXORWithAllOnes - Test whether the XOR operand is a AllOnes vector
14184 /// so it can be folded inside ANDNP.
14185 static bool CanFoldXORWithAllOnes(const SDNode *N) {
14186 EVT VT = N->getValueType(0);
14188 // Match direct AllOnes for 128 and 256-bit vectors
14189 if (ISD::isBuildVectorAllOnes(N))
14192 // Look through a bit convert.
14193 if (N->getOpcode() == ISD::BITCAST)
14194 N = N->getOperand(0).getNode();
14196 // Sometimes the operand may come from a insert_subvector building a 256-bit
14198 if (VT.getSizeInBits() == 256 &&
14199 N->getOpcode() == ISD::INSERT_SUBVECTOR) {
14200 SDValue V1 = N->getOperand(0);
14201 SDValue V2 = N->getOperand(1);
14203 if (V1.getOpcode() == ISD::INSERT_SUBVECTOR &&
14204 V1.getOperand(0).getOpcode() == ISD::UNDEF &&
14205 ISD::isBuildVectorAllOnes(V1.getOperand(1).getNode()) &&
14206 ISD::isBuildVectorAllOnes(V2.getNode()))
14213 static SDValue PerformAndCombine(SDNode *N, SelectionDAG &DAG,
14214 TargetLowering::DAGCombinerInfo &DCI,
14215 const X86Subtarget *Subtarget) {
14216 if (DCI.isBeforeLegalizeOps())
14219 SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget);
14223 EVT VT = N->getValueType(0);
14225 // Create ANDN, BLSI, and BLSR instructions
14226 // BLSI is X & (-X)
14227 // BLSR is X & (X-1)
14228 if (Subtarget->hasBMI() && (VT == MVT::i32 || VT == MVT::i64)) {
14229 SDValue N0 = N->getOperand(0);
14230 SDValue N1 = N->getOperand(1);
14231 DebugLoc DL = N->getDebugLoc();
14233 // Check LHS for not
14234 if (N0.getOpcode() == ISD::XOR && isAllOnes(N0.getOperand(1)))
14235 return DAG.getNode(X86ISD::ANDN, DL, VT, N0.getOperand(0), N1);
14236 // Check RHS for not
14237 if (N1.getOpcode() == ISD::XOR && isAllOnes(N1.getOperand(1)))
14238 return DAG.getNode(X86ISD::ANDN, DL, VT, N1.getOperand(0), N0);
14240 // Check LHS for neg
14241 if (N0.getOpcode() == ISD::SUB && N0.getOperand(1) == N1 &&
14242 isZero(N0.getOperand(0)))
14243 return DAG.getNode(X86ISD::BLSI, DL, VT, N1);
14245 // Check RHS for neg
14246 if (N1.getOpcode() == ISD::SUB && N1.getOperand(1) == N0 &&
14247 isZero(N1.getOperand(0)))
14248 return DAG.getNode(X86ISD::BLSI, DL, VT, N0);
14250 // Check LHS for X-1
14251 if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1 &&
14252 isAllOnes(N0.getOperand(1)))
14253 return DAG.getNode(X86ISD::BLSR, DL, VT, N1);
14255 // Check RHS for X-1
14256 if (N1.getOpcode() == ISD::ADD && N1.getOperand(0) == N0 &&
14257 isAllOnes(N1.getOperand(1)))
14258 return DAG.getNode(X86ISD::BLSR, DL, VT, N0);
14263 // Want to form ANDNP nodes:
14264 // 1) In the hopes of then easily combining them with OR and AND nodes
14265 // to form PBLEND/PSIGN.
14266 // 2) To match ANDN packed intrinsics
14267 if (VT != MVT::v2i64 && VT != MVT::v4i64)
14270 SDValue N0 = N->getOperand(0);
14271 SDValue N1 = N->getOperand(1);
14272 DebugLoc DL = N->getDebugLoc();
14274 // Check LHS for vnot
14275 if (N0.getOpcode() == ISD::XOR &&
14276 //ISD::isBuildVectorAllOnes(N0.getOperand(1).getNode()))
14277 CanFoldXORWithAllOnes(N0.getOperand(1).getNode()))
14278 return DAG.getNode(X86ISD::ANDNP, DL, VT, N0.getOperand(0), N1);
14280 // Check RHS for vnot
14281 if (N1.getOpcode() == ISD::XOR &&
14282 //ISD::isBuildVectorAllOnes(N1.getOperand(1).getNode()))
14283 CanFoldXORWithAllOnes(N1.getOperand(1).getNode()))
14284 return DAG.getNode(X86ISD::ANDNP, DL, VT, N1.getOperand(0), N0);
14289 static SDValue PerformOrCombine(SDNode *N, SelectionDAG &DAG,
14290 TargetLowering::DAGCombinerInfo &DCI,
14291 const X86Subtarget *Subtarget) {
14292 if (DCI.isBeforeLegalizeOps())
14295 SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget);
14299 EVT VT = N->getValueType(0);
14301 SDValue N0 = N->getOperand(0);
14302 SDValue N1 = N->getOperand(1);
14304 // look for psign/blend
14305 if (VT == MVT::v2i64 || VT == MVT::v4i64) {
14306 if (!Subtarget->hasSSSE3() ||
14307 (VT == MVT::v4i64 && !Subtarget->hasAVX2()))
14310 // Canonicalize pandn to RHS
14311 if (N0.getOpcode() == X86ISD::ANDNP)
14313 // or (and (m, y), (pandn m, x))
14314 if (N0.getOpcode() == ISD::AND && N1.getOpcode() == X86ISD::ANDNP) {
14315 SDValue Mask = N1.getOperand(0);
14316 SDValue X = N1.getOperand(1);
14318 if (N0.getOperand(0) == Mask)
14319 Y = N0.getOperand(1);
14320 if (N0.getOperand(1) == Mask)
14321 Y = N0.getOperand(0);
14323 // Check to see if the mask appeared in both the AND and ANDNP and
14327 // Validate that X, Y, and Mask are BIT_CONVERTS, and see through them.
14328 // Look through mask bitcast.
14329 if (Mask.getOpcode() == ISD::BITCAST)
14330 Mask = Mask.getOperand(0);
14331 if (X.getOpcode() == ISD::BITCAST)
14332 X = X.getOperand(0);
14333 if (Y.getOpcode() == ISD::BITCAST)
14334 Y = Y.getOperand(0);
14336 EVT MaskVT = Mask.getValueType();
14338 // Validate that the Mask operand is a vector sra node.
14339 // FIXME: what to do for bytes, since there is a psignb/pblendvb, but
14340 // there is no psrai.b
14341 if (Mask.getOpcode() != X86ISD::VSRAI)
14344 // Check that the SRA is all signbits.
14345 SDValue SraC = Mask.getOperand(1);
14346 unsigned SraAmt = cast<ConstantSDNode>(SraC)->getZExtValue();
14347 unsigned EltBits = MaskVT.getVectorElementType().getSizeInBits();
14348 if ((SraAmt + 1) != EltBits)
14351 DebugLoc DL = N->getDebugLoc();
14353 // Now we know we at least have a plendvb with the mask val. See if
14354 // we can form a psignb/w/d.
14355 // psign = x.type == y.type == mask.type && y = sub(0, x);
14356 if (Y.getOpcode() == ISD::SUB && Y.getOperand(1) == X &&
14357 ISD::isBuildVectorAllZeros(Y.getOperand(0).getNode()) &&
14358 X.getValueType() == MaskVT && Y.getValueType() == MaskVT) {
14359 assert((EltBits == 8 || EltBits == 16 || EltBits == 32) &&
14360 "Unsupported VT for PSIGN");
14361 Mask = DAG.getNode(X86ISD::PSIGN, DL, MaskVT, X, Mask.getOperand(0));
14362 return DAG.getNode(ISD::BITCAST, DL, VT, Mask);
14364 // PBLENDVB only available on SSE 4.1
14365 if (!Subtarget->hasSSE41())
14368 EVT BlendVT = (VT == MVT::v4i64) ? MVT::v32i8 : MVT::v16i8;
14370 X = DAG.getNode(ISD::BITCAST, DL, BlendVT, X);
14371 Y = DAG.getNode(ISD::BITCAST, DL, BlendVT, Y);
14372 Mask = DAG.getNode(ISD::BITCAST, DL, BlendVT, Mask);
14373 Mask = DAG.getNode(ISD::VSELECT, DL, BlendVT, Mask, Y, X);
14374 return DAG.getNode(ISD::BITCAST, DL, VT, Mask);
14378 if (VT != MVT::i16 && VT != MVT::i32 && VT != MVT::i64)
14381 // fold (or (x << c) | (y >> (64 - c))) ==> (shld64 x, y, c)
14382 if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL)
14384 if (N0.getOpcode() != ISD::SHL || N1.getOpcode() != ISD::SRL)
14386 if (!N0.hasOneUse() || !N1.hasOneUse())
14389 SDValue ShAmt0 = N0.getOperand(1);
14390 if (ShAmt0.getValueType() != MVT::i8)
14392 SDValue ShAmt1 = N1.getOperand(1);
14393 if (ShAmt1.getValueType() != MVT::i8)
14395 if (ShAmt0.getOpcode() == ISD::TRUNCATE)
14396 ShAmt0 = ShAmt0.getOperand(0);
14397 if (ShAmt1.getOpcode() == ISD::TRUNCATE)
14398 ShAmt1 = ShAmt1.getOperand(0);
14400 DebugLoc DL = N->getDebugLoc();
14401 unsigned Opc = X86ISD::SHLD;
14402 SDValue Op0 = N0.getOperand(0);
14403 SDValue Op1 = N1.getOperand(0);
14404 if (ShAmt0.getOpcode() == ISD::SUB) {
14405 Opc = X86ISD::SHRD;
14406 std::swap(Op0, Op1);
14407 std::swap(ShAmt0, ShAmt1);
14410 unsigned Bits = VT.getSizeInBits();
14411 if (ShAmt1.getOpcode() == ISD::SUB) {
14412 SDValue Sum = ShAmt1.getOperand(0);
14413 if (ConstantSDNode *SumC = dyn_cast<ConstantSDNode>(Sum)) {
14414 SDValue ShAmt1Op1 = ShAmt1.getOperand(1);
14415 if (ShAmt1Op1.getNode()->getOpcode() == ISD::TRUNCATE)
14416 ShAmt1Op1 = ShAmt1Op1.getOperand(0);
14417 if (SumC->getSExtValue() == Bits && ShAmt1Op1 == ShAmt0)
14418 return DAG.getNode(Opc, DL, VT,
14420 DAG.getNode(ISD::TRUNCATE, DL,
14423 } else if (ConstantSDNode *ShAmt1C = dyn_cast<ConstantSDNode>(ShAmt1)) {
14424 ConstantSDNode *ShAmt0C = dyn_cast<ConstantSDNode>(ShAmt0);
14426 ShAmt0C->getSExtValue() + ShAmt1C->getSExtValue() == Bits)
14427 return DAG.getNode(Opc, DL, VT,
14428 N0.getOperand(0), N1.getOperand(0),
14429 DAG.getNode(ISD::TRUNCATE, DL,
14436 // PerformXorCombine - Attempts to turn XOR nodes into BLSMSK nodes
14437 static SDValue PerformXorCombine(SDNode *N, SelectionDAG &DAG,
14438 TargetLowering::DAGCombinerInfo &DCI,
14439 const X86Subtarget *Subtarget) {
14440 if (DCI.isBeforeLegalizeOps())
14443 EVT VT = N->getValueType(0);
14445 if (VT != MVT::i32 && VT != MVT::i64)
14448 assert(Subtarget->hasBMI() && "Creating BLSMSK requires BMI instructions");
14450 // Create BLSMSK instructions by finding X ^ (X-1)
14451 SDValue N0 = N->getOperand(0);
14452 SDValue N1 = N->getOperand(1);
14453 DebugLoc DL = N->getDebugLoc();
14455 if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1 &&
14456 isAllOnes(N0.getOperand(1)))
14457 return DAG.getNode(X86ISD::BLSMSK, DL, VT, N1);
14459 if (N1.getOpcode() == ISD::ADD && N1.getOperand(0) == N0 &&
14460 isAllOnes(N1.getOperand(1)))
14461 return DAG.getNode(X86ISD::BLSMSK, DL, VT, N0);
14466 /// PerformLOADCombine - Do target-specific dag combines on LOAD nodes.
14467 static SDValue PerformLOADCombine(SDNode *N, SelectionDAG &DAG,
14468 const X86Subtarget *Subtarget) {
14469 LoadSDNode *Ld = cast<LoadSDNode>(N);
14470 EVT RegVT = Ld->getValueType(0);
14471 EVT MemVT = Ld->getMemoryVT();
14472 DebugLoc dl = Ld->getDebugLoc();
14473 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
14475 ISD::LoadExtType Ext = Ld->getExtensionType();
14477 // If this is a vector EXT Load then attempt to optimize it using a
14478 // shuffle. We need SSE4 for the shuffles.
14479 // TODO: It is possible to support ZExt by zeroing the undef values
14480 // during the shuffle phase or after the shuffle.
14481 if (RegVT.isVector() && RegVT.isInteger() &&
14482 Ext == ISD::EXTLOAD && Subtarget->hasSSE41()) {
14483 assert(MemVT != RegVT && "Cannot extend to the same type");
14484 assert(MemVT.isVector() && "Must load a vector from memory");
14486 unsigned NumElems = RegVT.getVectorNumElements();
14487 unsigned RegSz = RegVT.getSizeInBits();
14488 unsigned MemSz = MemVT.getSizeInBits();
14489 assert(RegSz > MemSz && "Register size must be greater than the mem size");
14490 // All sizes must be a power of two
14491 if (!isPowerOf2_32(RegSz * MemSz * NumElems)) return SDValue();
14493 // Attempt to load the original value using a single load op.
14494 // Find a scalar type which is equal to the loaded word size.
14495 MVT SclrLoadTy = MVT::i8;
14496 for (unsigned tp = MVT::FIRST_INTEGER_VALUETYPE;
14497 tp < MVT::LAST_INTEGER_VALUETYPE; ++tp) {
14498 MVT Tp = (MVT::SimpleValueType)tp;
14499 if (TLI.isTypeLegal(Tp) && Tp.getSizeInBits() == MemSz) {
14505 // Proceed if a load word is found.
14506 if (SclrLoadTy.getSizeInBits() != MemSz) return SDValue();
14508 EVT LoadUnitVecVT = EVT::getVectorVT(*DAG.getContext(), SclrLoadTy,
14509 RegSz/SclrLoadTy.getSizeInBits());
14511 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(), MemVT.getScalarType(),
14512 RegSz/MemVT.getScalarType().getSizeInBits());
14513 // Can't shuffle using an illegal type.
14514 if (!TLI.isTypeLegal(WideVecVT)) return SDValue();
14516 // Perform a single load.
14517 SDValue ScalarLoad = DAG.getLoad(SclrLoadTy, dl, Ld->getChain(),
14519 Ld->getPointerInfo(), Ld->isVolatile(),
14520 Ld->isNonTemporal(), Ld->isInvariant(),
14521 Ld->getAlignment());
14523 // Insert the word loaded into a vector.
14524 SDValue ScalarInVector = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
14525 LoadUnitVecVT, ScalarLoad);
14527 // Bitcast the loaded value to a vector of the original element type, in
14528 // the size of the target vector type.
14529 SDValue SlicedVec = DAG.getNode(ISD::BITCAST, dl, WideVecVT,
14531 unsigned SizeRatio = RegSz/MemSz;
14533 // Redistribute the loaded elements into the different locations.
14534 SmallVector<int, 8> ShuffleVec(NumElems * SizeRatio, -1);
14535 for (unsigned i = 0; i != NumElems; ++i)
14536 ShuffleVec[i*SizeRatio] = i;
14538 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, SlicedVec,
14539 DAG.getUNDEF(WideVecVT),
14542 // Bitcast to the requested type.
14543 Shuff = DAG.getNode(ISD::BITCAST, dl, RegVT, Shuff);
14544 // Replace the original load with the new sequence
14545 // and return the new chain.
14546 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Shuff);
14547 return SDValue(ScalarLoad.getNode(), 1);
14553 /// PerformSTORECombine - Do target-specific dag combines on STORE nodes.
14554 static SDValue PerformSTORECombine(SDNode *N, SelectionDAG &DAG,
14555 const X86Subtarget *Subtarget) {
14556 StoreSDNode *St = cast<StoreSDNode>(N);
14557 EVT VT = St->getValue().getValueType();
14558 EVT StVT = St->getMemoryVT();
14559 DebugLoc dl = St->getDebugLoc();
14560 SDValue StoredVal = St->getOperand(1);
14561 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
14563 // If we are saving a concatenation of two XMM registers, perform two stores.
14564 // On Sandy Bridge, 256-bit memory operations are executed by two
14565 // 128-bit ports. However, on Haswell it is better to issue a single 256-bit
14566 // memory operation.
14567 if (VT.getSizeInBits() == 256 && !Subtarget->hasAVX2() &&
14568 StoredVal.getNode()->getOpcode() == ISD::CONCAT_VECTORS &&
14569 StoredVal.getNumOperands() == 2) {
14570 SDValue Value0 = StoredVal.getOperand(0);
14571 SDValue Value1 = StoredVal.getOperand(1);
14573 SDValue Stride = DAG.getConstant(16, TLI.getPointerTy());
14574 SDValue Ptr0 = St->getBasePtr();
14575 SDValue Ptr1 = DAG.getNode(ISD::ADD, dl, Ptr0.getValueType(), Ptr0, Stride);
14577 SDValue Ch0 = DAG.getStore(St->getChain(), dl, Value0, Ptr0,
14578 St->getPointerInfo(), St->isVolatile(),
14579 St->isNonTemporal(), St->getAlignment());
14580 SDValue Ch1 = DAG.getStore(St->getChain(), dl, Value1, Ptr1,
14581 St->getPointerInfo(), St->isVolatile(),
14582 St->isNonTemporal(), St->getAlignment());
14583 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Ch0, Ch1);
14586 // Optimize trunc store (of multiple scalars) to shuffle and store.
14587 // First, pack all of the elements in one place. Next, store to memory
14588 // in fewer chunks.
14589 if (St->isTruncatingStore() && VT.isVector()) {
14590 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
14591 unsigned NumElems = VT.getVectorNumElements();
14592 assert(StVT != VT && "Cannot truncate to the same type");
14593 unsigned FromSz = VT.getVectorElementType().getSizeInBits();
14594 unsigned ToSz = StVT.getVectorElementType().getSizeInBits();
14596 // From, To sizes and ElemCount must be pow of two
14597 if (!isPowerOf2_32(NumElems * FromSz * ToSz)) return SDValue();
14598 // We are going to use the original vector elt for storing.
14599 // Accumulated smaller vector elements must be a multiple of the store size.
14600 if (0 != (NumElems * FromSz) % ToSz) return SDValue();
14602 unsigned SizeRatio = FromSz / ToSz;
14604 assert(SizeRatio * NumElems * ToSz == VT.getSizeInBits());
14606 // Create a type on which we perform the shuffle
14607 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(),
14608 StVT.getScalarType(), NumElems*SizeRatio);
14610 assert(WideVecVT.getSizeInBits() == VT.getSizeInBits());
14612 SDValue WideVec = DAG.getNode(ISD::BITCAST, dl, WideVecVT, St->getValue());
14613 SmallVector<int, 8> ShuffleVec(NumElems * SizeRatio, -1);
14614 for (unsigned i = 0; i != NumElems; ++i)
14615 ShuffleVec[i] = i * SizeRatio;
14617 // Can't shuffle using an illegal type
14618 if (!TLI.isTypeLegal(WideVecVT)) return SDValue();
14620 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, WideVec,
14621 DAG.getUNDEF(WideVecVT),
14623 // At this point all of the data is stored at the bottom of the
14624 // register. We now need to save it to mem.
14626 // Find the largest store unit
14627 MVT StoreType = MVT::i8;
14628 for (unsigned tp = MVT::FIRST_INTEGER_VALUETYPE;
14629 tp < MVT::LAST_INTEGER_VALUETYPE; ++tp) {
14630 MVT Tp = (MVT::SimpleValueType)tp;
14631 if (TLI.isTypeLegal(Tp) && StoreType.getSizeInBits() < NumElems * ToSz)
14635 // Bitcast the original vector into a vector of store-size units
14636 EVT StoreVecVT = EVT::getVectorVT(*DAG.getContext(),
14637 StoreType, VT.getSizeInBits()/EVT(StoreType).getSizeInBits());
14638 assert(StoreVecVT.getSizeInBits() == VT.getSizeInBits());
14639 SDValue ShuffWide = DAG.getNode(ISD::BITCAST, dl, StoreVecVT, Shuff);
14640 SmallVector<SDValue, 8> Chains;
14641 SDValue Increment = DAG.getConstant(StoreType.getSizeInBits()/8,
14642 TLI.getPointerTy());
14643 SDValue Ptr = St->getBasePtr();
14645 // Perform one or more big stores into memory.
14646 for (unsigned i=0, e=(ToSz*NumElems)/StoreType.getSizeInBits(); i!=e; ++i) {
14647 SDValue SubVec = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
14648 StoreType, ShuffWide,
14649 DAG.getIntPtrConstant(i));
14650 SDValue Ch = DAG.getStore(St->getChain(), dl, SubVec, Ptr,
14651 St->getPointerInfo(), St->isVolatile(),
14652 St->isNonTemporal(), St->getAlignment());
14653 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
14654 Chains.push_back(Ch);
14657 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Chains[0],
14662 // Turn load->store of MMX types into GPR load/stores. This avoids clobbering
14663 // the FP state in cases where an emms may be missing.
14664 // A preferable solution to the general problem is to figure out the right
14665 // places to insert EMMS. This qualifies as a quick hack.
14667 // Similarly, turn load->store of i64 into double load/stores in 32-bit mode.
14668 if (VT.getSizeInBits() != 64)
14671 const Function *F = DAG.getMachineFunction().getFunction();
14672 bool NoImplicitFloatOps = F->hasFnAttr(Attribute::NoImplicitFloat);
14673 bool F64IsLegal = !DAG.getTarget().Options.UseSoftFloat && !NoImplicitFloatOps
14674 && Subtarget->hasSSE2();
14675 if ((VT.isVector() ||
14676 (VT == MVT::i64 && F64IsLegal && !Subtarget->is64Bit())) &&
14677 isa<LoadSDNode>(St->getValue()) &&
14678 !cast<LoadSDNode>(St->getValue())->isVolatile() &&
14679 St->getChain().hasOneUse() && !St->isVolatile()) {
14680 SDNode* LdVal = St->getValue().getNode();
14681 LoadSDNode *Ld = 0;
14682 int TokenFactorIndex = -1;
14683 SmallVector<SDValue, 8> Ops;
14684 SDNode* ChainVal = St->getChain().getNode();
14685 // Must be a store of a load. We currently handle two cases: the load
14686 // is a direct child, and it's under an intervening TokenFactor. It is
14687 // possible to dig deeper under nested TokenFactors.
14688 if (ChainVal == LdVal)
14689 Ld = cast<LoadSDNode>(St->getChain());
14690 else if (St->getValue().hasOneUse() &&
14691 ChainVal->getOpcode() == ISD::TokenFactor) {
14692 for (unsigned i = 0, e = ChainVal->getNumOperands(); i != e; ++i) {
14693 if (ChainVal->getOperand(i).getNode() == LdVal) {
14694 TokenFactorIndex = i;
14695 Ld = cast<LoadSDNode>(St->getValue());
14697 Ops.push_back(ChainVal->getOperand(i));
14701 if (!Ld || !ISD::isNormalLoad(Ld))
14704 // If this is not the MMX case, i.e. we are just turning i64 load/store
14705 // into f64 load/store, avoid the transformation if there are multiple
14706 // uses of the loaded value.
14707 if (!VT.isVector() && !Ld->hasNUsesOfValue(1, 0))
14710 DebugLoc LdDL = Ld->getDebugLoc();
14711 DebugLoc StDL = N->getDebugLoc();
14712 // If we are a 64-bit capable x86, lower to a single movq load/store pair.
14713 // Otherwise, if it's legal to use f64 SSE instructions, use f64 load/store
14715 if (Subtarget->is64Bit() || F64IsLegal) {
14716 EVT LdVT = Subtarget->is64Bit() ? MVT::i64 : MVT::f64;
14717 SDValue NewLd = DAG.getLoad(LdVT, LdDL, Ld->getChain(), Ld->getBasePtr(),
14718 Ld->getPointerInfo(), Ld->isVolatile(),
14719 Ld->isNonTemporal(), Ld->isInvariant(),
14720 Ld->getAlignment());
14721 SDValue NewChain = NewLd.getValue(1);
14722 if (TokenFactorIndex != -1) {
14723 Ops.push_back(NewChain);
14724 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, &Ops[0],
14727 return DAG.getStore(NewChain, StDL, NewLd, St->getBasePtr(),
14728 St->getPointerInfo(),
14729 St->isVolatile(), St->isNonTemporal(),
14730 St->getAlignment());
14733 // Otherwise, lower to two pairs of 32-bit loads / stores.
14734 SDValue LoAddr = Ld->getBasePtr();
14735 SDValue HiAddr = DAG.getNode(ISD::ADD, LdDL, MVT::i32, LoAddr,
14736 DAG.getConstant(4, MVT::i32));
14738 SDValue LoLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), LoAddr,
14739 Ld->getPointerInfo(),
14740 Ld->isVolatile(), Ld->isNonTemporal(),
14741 Ld->isInvariant(), Ld->getAlignment());
14742 SDValue HiLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), HiAddr,
14743 Ld->getPointerInfo().getWithOffset(4),
14744 Ld->isVolatile(), Ld->isNonTemporal(),
14746 MinAlign(Ld->getAlignment(), 4));
14748 SDValue NewChain = LoLd.getValue(1);
14749 if (TokenFactorIndex != -1) {
14750 Ops.push_back(LoLd);
14751 Ops.push_back(HiLd);
14752 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, &Ops[0],
14756 LoAddr = St->getBasePtr();
14757 HiAddr = DAG.getNode(ISD::ADD, StDL, MVT::i32, LoAddr,
14758 DAG.getConstant(4, MVT::i32));
14760 SDValue LoSt = DAG.getStore(NewChain, StDL, LoLd, LoAddr,
14761 St->getPointerInfo(),
14762 St->isVolatile(), St->isNonTemporal(),
14763 St->getAlignment());
14764 SDValue HiSt = DAG.getStore(NewChain, StDL, HiLd, HiAddr,
14765 St->getPointerInfo().getWithOffset(4),
14767 St->isNonTemporal(),
14768 MinAlign(St->getAlignment(), 4));
14769 return DAG.getNode(ISD::TokenFactor, StDL, MVT::Other, LoSt, HiSt);
14774 /// isHorizontalBinOp - Return 'true' if this vector operation is "horizontal"
14775 /// and return the operands for the horizontal operation in LHS and RHS. A
14776 /// horizontal operation performs the binary operation on successive elements
14777 /// of its first operand, then on successive elements of its second operand,
14778 /// returning the resulting values in a vector. For example, if
14779 /// A = < float a0, float a1, float a2, float a3 >
14781 /// B = < float b0, float b1, float b2, float b3 >
14782 /// then the result of doing a horizontal operation on A and B is
14783 /// A horizontal-op B = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >.
14784 /// In short, LHS and RHS are inspected to see if LHS op RHS is of the form
14785 /// A horizontal-op B, for some already available A and B, and if so then LHS is
14786 /// set to A, RHS to B, and the routine returns 'true'.
14787 /// Note that the binary operation should have the property that if one of the
14788 /// operands is UNDEF then the result is UNDEF.
14789 static bool isHorizontalBinOp(SDValue &LHS, SDValue &RHS, bool IsCommutative) {
14790 // Look for the following pattern: if
14791 // A = < float a0, float a1, float a2, float a3 >
14792 // B = < float b0, float b1, float b2, float b3 >
14794 // LHS = VECTOR_SHUFFLE A, B, <0, 2, 4, 6>
14795 // RHS = VECTOR_SHUFFLE A, B, <1, 3, 5, 7>
14796 // then LHS op RHS = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >
14797 // which is A horizontal-op B.
14799 // At least one of the operands should be a vector shuffle.
14800 if (LHS.getOpcode() != ISD::VECTOR_SHUFFLE &&
14801 RHS.getOpcode() != ISD::VECTOR_SHUFFLE)
14804 EVT VT = LHS.getValueType();
14806 assert((VT.is128BitVector() || VT.is256BitVector()) &&
14807 "Unsupported vector type for horizontal add/sub");
14809 // Handle 128 and 256-bit vector lengths. AVX defines horizontal add/sub to
14810 // operate independently on 128-bit lanes.
14811 unsigned NumElts = VT.getVectorNumElements();
14812 unsigned NumLanes = VT.getSizeInBits()/128;
14813 unsigned NumLaneElts = NumElts / NumLanes;
14814 assert((NumLaneElts % 2 == 0) &&
14815 "Vector type should have an even number of elements in each lane");
14816 unsigned HalfLaneElts = NumLaneElts/2;
14818 // View LHS in the form
14819 // LHS = VECTOR_SHUFFLE A, B, LMask
14820 // If LHS is not a shuffle then pretend it is the shuffle
14821 // LHS = VECTOR_SHUFFLE LHS, undef, <0, 1, ..., N-1>
14822 // NOTE: in what follows a default initialized SDValue represents an UNDEF of
14825 SmallVector<int, 16> LMask(NumElts);
14826 if (LHS.getOpcode() == ISD::VECTOR_SHUFFLE) {
14827 if (LHS.getOperand(0).getOpcode() != ISD::UNDEF)
14828 A = LHS.getOperand(0);
14829 if (LHS.getOperand(1).getOpcode() != ISD::UNDEF)
14830 B = LHS.getOperand(1);
14831 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(LHS.getNode())->getMask();
14832 std::copy(Mask.begin(), Mask.end(), LMask.begin());
14834 if (LHS.getOpcode() != ISD::UNDEF)
14836 for (unsigned i = 0; i != NumElts; ++i)
14840 // Likewise, view RHS in the form
14841 // RHS = VECTOR_SHUFFLE C, D, RMask
14843 SmallVector<int, 16> RMask(NumElts);
14844 if (RHS.getOpcode() == ISD::VECTOR_SHUFFLE) {
14845 if (RHS.getOperand(0).getOpcode() != ISD::UNDEF)
14846 C = RHS.getOperand(0);
14847 if (RHS.getOperand(1).getOpcode() != ISD::UNDEF)
14848 D = RHS.getOperand(1);
14849 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(RHS.getNode())->getMask();
14850 std::copy(Mask.begin(), Mask.end(), RMask.begin());
14852 if (RHS.getOpcode() != ISD::UNDEF)
14854 for (unsigned i = 0; i != NumElts; ++i)
14858 // Check that the shuffles are both shuffling the same vectors.
14859 if (!(A == C && B == D) && !(A == D && B == C))
14862 // If everything is UNDEF then bail out: it would be better to fold to UNDEF.
14863 if (!A.getNode() && !B.getNode())
14866 // If A and B occur in reverse order in RHS, then "swap" them (which means
14867 // rewriting the mask).
14869 CommuteVectorShuffleMask(RMask, NumElts);
14871 // At this point LHS and RHS are equivalent to
14872 // LHS = VECTOR_SHUFFLE A, B, LMask
14873 // RHS = VECTOR_SHUFFLE A, B, RMask
14874 // Check that the masks correspond to performing a horizontal operation.
14875 for (unsigned i = 0; i != NumElts; ++i) {
14876 int LIdx = LMask[i], RIdx = RMask[i];
14878 // Ignore any UNDEF components.
14879 if (LIdx < 0 || RIdx < 0 ||
14880 (!A.getNode() && (LIdx < (int)NumElts || RIdx < (int)NumElts)) ||
14881 (!B.getNode() && (LIdx >= (int)NumElts || RIdx >= (int)NumElts)))
14884 // Check that successive elements are being operated on. If not, this is
14885 // not a horizontal operation.
14886 unsigned Src = (i/HalfLaneElts) % 2; // each lane is split between srcs
14887 unsigned LaneStart = (i/NumLaneElts) * NumLaneElts;
14888 int Index = 2*(i%HalfLaneElts) + NumElts*Src + LaneStart;
14889 if (!(LIdx == Index && RIdx == Index + 1) &&
14890 !(IsCommutative && LIdx == Index + 1 && RIdx == Index))
14894 LHS = A.getNode() ? A : B; // If A is 'UNDEF', use B for it.
14895 RHS = B.getNode() ? B : A; // If B is 'UNDEF', use A for it.
14899 /// PerformFADDCombine - Do target-specific dag combines on floating point adds.
14900 static SDValue PerformFADDCombine(SDNode *N, SelectionDAG &DAG,
14901 const X86Subtarget *Subtarget) {
14902 EVT VT = N->getValueType(0);
14903 SDValue LHS = N->getOperand(0);
14904 SDValue RHS = N->getOperand(1);
14906 // Try to synthesize horizontal adds from adds of shuffles.
14907 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
14908 (Subtarget->hasAVX() && (VT == MVT::v8f32 || VT == MVT::v4f64))) &&
14909 isHorizontalBinOp(LHS, RHS, true))
14910 return DAG.getNode(X86ISD::FHADD, N->getDebugLoc(), VT, LHS, RHS);
14914 /// PerformFSUBCombine - Do target-specific dag combines on floating point subs.
14915 static SDValue PerformFSUBCombine(SDNode *N, SelectionDAG &DAG,
14916 const X86Subtarget *Subtarget) {
14917 EVT VT = N->getValueType(0);
14918 SDValue LHS = N->getOperand(0);
14919 SDValue RHS = N->getOperand(1);
14921 // Try to synthesize horizontal subs from subs of shuffles.
14922 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
14923 (Subtarget->hasAVX() && (VT == MVT::v8f32 || VT == MVT::v4f64))) &&
14924 isHorizontalBinOp(LHS, RHS, false))
14925 return DAG.getNode(X86ISD::FHSUB, N->getDebugLoc(), VT, LHS, RHS);
14929 /// PerformFORCombine - Do target-specific dag combines on X86ISD::FOR and
14930 /// X86ISD::FXOR nodes.
14931 static SDValue PerformFORCombine(SDNode *N, SelectionDAG &DAG) {
14932 assert(N->getOpcode() == X86ISD::FOR || N->getOpcode() == X86ISD::FXOR);
14933 // F[X]OR(0.0, x) -> x
14934 // F[X]OR(x, 0.0) -> x
14935 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
14936 if (C->getValueAPF().isPosZero())
14937 return N->getOperand(1);
14938 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
14939 if (C->getValueAPF().isPosZero())
14940 return N->getOperand(0);
14944 /// PerformFANDCombine - Do target-specific dag combines on X86ISD::FAND nodes.
14945 static SDValue PerformFANDCombine(SDNode *N, SelectionDAG &DAG) {
14946 // FAND(0.0, x) -> 0.0
14947 // FAND(x, 0.0) -> 0.0
14948 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
14949 if (C->getValueAPF().isPosZero())
14950 return N->getOperand(0);
14951 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
14952 if (C->getValueAPF().isPosZero())
14953 return N->getOperand(1);
14957 static SDValue PerformBTCombine(SDNode *N,
14959 TargetLowering::DAGCombinerInfo &DCI) {
14960 // BT ignores high bits in the bit index operand.
14961 SDValue Op1 = N->getOperand(1);
14962 if (Op1.hasOneUse()) {
14963 unsigned BitWidth = Op1.getValueSizeInBits();
14964 APInt DemandedMask = APInt::getLowBitsSet(BitWidth, Log2_32(BitWidth));
14965 APInt KnownZero, KnownOne;
14966 TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(),
14967 !DCI.isBeforeLegalizeOps());
14968 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
14969 if (TLO.ShrinkDemandedConstant(Op1, DemandedMask) ||
14970 TLI.SimplifyDemandedBits(Op1, DemandedMask, KnownZero, KnownOne, TLO))
14971 DCI.CommitTargetLoweringOpt(TLO);
14976 static SDValue PerformVZEXT_MOVLCombine(SDNode *N, SelectionDAG &DAG) {
14977 SDValue Op = N->getOperand(0);
14978 if (Op.getOpcode() == ISD::BITCAST)
14979 Op = Op.getOperand(0);
14980 EVT VT = N->getValueType(0), OpVT = Op.getValueType();
14981 if (Op.getOpcode() == X86ISD::VZEXT_LOAD &&
14982 VT.getVectorElementType().getSizeInBits() ==
14983 OpVT.getVectorElementType().getSizeInBits()) {
14984 return DAG.getNode(ISD::BITCAST, N->getDebugLoc(), VT, Op);
14989 static SDValue PerformSExtCombine(SDNode *N, SelectionDAG &DAG,
14990 TargetLowering::DAGCombinerInfo &DCI,
14991 const X86Subtarget *Subtarget) {
14992 if (!DCI.isBeforeLegalizeOps())
14995 if (!Subtarget->hasAVX())
14998 EVT VT = N->getValueType(0);
14999 SDValue Op = N->getOperand(0);
15000 EVT OpVT = Op.getValueType();
15001 DebugLoc dl = N->getDebugLoc();
15003 if ((VT == MVT::v4i64 && OpVT == MVT::v4i32) ||
15004 (VT == MVT::v8i32 && OpVT == MVT::v8i16)) {
15006 if (Subtarget->hasAVX2())
15007 return DAG.getNode(X86ISD::VSEXT_MOVL, dl, VT, Op);
15009 // Optimize vectors in AVX mode
15010 // Sign extend v8i16 to v8i32 and
15013 // Divide input vector into two parts
15014 // for v4i32 the shuffle mask will be { 0, 1, -1, -1} {2, 3, -1, -1}
15015 // use vpmovsx instruction to extend v4i32 -> v2i64; v8i16 -> v4i32
15016 // concat the vectors to original VT
15018 unsigned NumElems = OpVT.getVectorNumElements();
15019 SmallVector<int,8> ShufMask1(NumElems, -1);
15020 for (unsigned i = 0; i != NumElems/2; ++i)
15023 SDValue OpLo = DAG.getVectorShuffle(OpVT, dl, Op, DAG.getUNDEF(OpVT),
15026 SmallVector<int,8> ShufMask2(NumElems, -1);
15027 for (unsigned i = 0; i != NumElems/2; ++i)
15028 ShufMask2[i] = i + NumElems/2;
15030 SDValue OpHi = DAG.getVectorShuffle(OpVT, dl, Op, DAG.getUNDEF(OpVT),
15033 EVT HalfVT = EVT::getVectorVT(*DAG.getContext(), VT.getScalarType(),
15034 VT.getVectorNumElements()/2);
15036 OpLo = DAG.getNode(X86ISD::VSEXT_MOVL, dl, HalfVT, OpLo);
15037 OpHi = DAG.getNode(X86ISD::VSEXT_MOVL, dl, HalfVT, OpHi);
15039 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi);
15044 static SDValue PerformZExtCombine(SDNode *N, SelectionDAG &DAG,
15045 TargetLowering::DAGCombinerInfo &DCI,
15046 const X86Subtarget *Subtarget) {
15047 // (i32 zext (and (i8 x86isd::setcc_carry), 1)) ->
15048 // (and (i32 x86isd::setcc_carry), 1)
15049 // This eliminates the zext. This transformation is necessary because
15050 // ISD::SETCC is always legalized to i8.
15051 DebugLoc dl = N->getDebugLoc();
15052 SDValue N0 = N->getOperand(0);
15053 EVT VT = N->getValueType(0);
15054 EVT OpVT = N0.getValueType();
15056 if (N0.getOpcode() == ISD::AND &&
15058 N0.getOperand(0).hasOneUse()) {
15059 SDValue N00 = N0.getOperand(0);
15060 if (N00.getOpcode() != X86ISD::SETCC_CARRY)
15062 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
15063 if (!C || C->getZExtValue() != 1)
15065 return DAG.getNode(ISD::AND, dl, VT,
15066 DAG.getNode(X86ISD::SETCC_CARRY, dl, VT,
15067 N00.getOperand(0), N00.getOperand(1)),
15068 DAG.getConstant(1, VT));
15071 // Optimize vectors in AVX mode:
15074 // Use vpunpcklwd for 4 lower elements v8i16 -> v4i32.
15075 // Use vpunpckhwd for 4 upper elements v8i16 -> v4i32.
15076 // Concat upper and lower parts.
15079 // Use vpunpckldq for 4 lower elements v4i32 -> v2i64.
15080 // Use vpunpckhdq for 4 upper elements v4i32 -> v2i64.
15081 // Concat upper and lower parts.
15083 if (!DCI.isBeforeLegalizeOps())
15086 if (!Subtarget->hasAVX())
15089 if (((VT == MVT::v8i32) && (OpVT == MVT::v8i16)) ||
15090 ((VT == MVT::v4i64) && (OpVT == MVT::v4i32))) {
15092 if (Subtarget->hasAVX2())
15093 return DAG.getNode(X86ISD::VZEXT_MOVL, dl, VT, N0);
15095 SDValue ZeroVec = getZeroVector(OpVT, Subtarget, DAG, dl);
15096 SDValue OpLo = getUnpackl(DAG, dl, OpVT, N0, ZeroVec);
15097 SDValue OpHi = getUnpackh(DAG, dl, OpVT, N0, ZeroVec);
15099 EVT HVT = EVT::getVectorVT(*DAG.getContext(), VT.getVectorElementType(),
15100 VT.getVectorNumElements()/2);
15102 OpLo = DAG.getNode(ISD::BITCAST, dl, HVT, OpLo);
15103 OpHi = DAG.getNode(ISD::BITCAST, dl, HVT, OpHi);
15105 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi);
15111 // Optimize x == -y --> x+y == 0
15112 // x != -y --> x+y != 0
15113 static SDValue PerformISDSETCCCombine(SDNode *N, SelectionDAG &DAG) {
15114 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(2))->get();
15115 SDValue LHS = N->getOperand(0);
15116 SDValue RHS = N->getOperand(1);
15118 if ((CC == ISD::SETNE || CC == ISD::SETEQ) && LHS.getOpcode() == ISD::SUB)
15119 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(LHS.getOperand(0)))
15120 if (C->getAPIntValue() == 0 && LHS.hasOneUse()) {
15121 SDValue addV = DAG.getNode(ISD::ADD, N->getDebugLoc(),
15122 LHS.getValueType(), RHS, LHS.getOperand(1));
15123 return DAG.getSetCC(N->getDebugLoc(), N->getValueType(0),
15124 addV, DAG.getConstant(0, addV.getValueType()), CC);
15126 if ((CC == ISD::SETNE || CC == ISD::SETEQ) && RHS.getOpcode() == ISD::SUB)
15127 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS.getOperand(0)))
15128 if (C->getAPIntValue() == 0 && RHS.hasOneUse()) {
15129 SDValue addV = DAG.getNode(ISD::ADD, N->getDebugLoc(),
15130 RHS.getValueType(), LHS, RHS.getOperand(1));
15131 return DAG.getSetCC(N->getDebugLoc(), N->getValueType(0),
15132 addV, DAG.getConstant(0, addV.getValueType()), CC);
15137 // Optimize RES = X86ISD::SETCC CONDCODE, EFLAG_INPUT
15138 static SDValue PerformSETCCCombine(SDNode *N, SelectionDAG &DAG) {
15139 unsigned X86CC = N->getConstantOperandVal(0);
15140 SDValue EFLAG = N->getOperand(1);
15141 DebugLoc DL = N->getDebugLoc();
15143 // Materialize "setb reg" as "sbb reg,reg", since it can be extended without
15144 // a zext and produces an all-ones bit which is more useful than 0/1 in some
15146 if (X86CC == X86::COND_B)
15147 return DAG.getNode(ISD::AND, DL, MVT::i8,
15148 DAG.getNode(X86ISD::SETCC_CARRY, DL, MVT::i8,
15149 DAG.getConstant(X86CC, MVT::i8), EFLAG),
15150 DAG.getConstant(1, MVT::i8));
15155 static SDValue PerformUINT_TO_FPCombine(SDNode *N, SelectionDAG &DAG) {
15156 SDValue Op0 = N->getOperand(0);
15157 EVT InVT = Op0->getValueType(0);
15159 // UINT_TO_FP(v4i8) -> SINT_TO_FP(ZEXT(v4i8 to v4i32))
15160 if (InVT == MVT::v8i8 || InVT == MVT::v4i8) {
15161 DebugLoc dl = N->getDebugLoc();
15162 MVT DstVT = InVT == MVT::v4i8 ? MVT::v4i32 : MVT::v8i32;
15163 SDValue P = DAG.getNode(ISD::ZERO_EXTEND, dl, DstVT, Op0);
15164 // Notice that we use SINT_TO_FP because we know that the high bits
15165 // are zero and SINT_TO_FP is better supported by the hardware.
15166 return DAG.getNode(ISD::SINT_TO_FP, dl, N->getValueType(0), P);
15172 static SDValue PerformSINT_TO_FPCombine(SDNode *N, SelectionDAG &DAG,
15173 const X86TargetLowering *XTLI) {
15174 SDValue Op0 = N->getOperand(0);
15175 EVT InVT = Op0->getValueType(0);
15177 // SINT_TO_FP(v4i8) -> SINT_TO_FP(SEXT(v4i8 to v4i32))
15178 if (InVT == MVT::v8i8 || InVT == MVT::v4i8) {
15179 DebugLoc dl = N->getDebugLoc();
15180 MVT DstVT = InVT == MVT::v4i8 ? MVT::v4i32 : MVT::v8i32;
15181 SDValue P = DAG.getNode(ISD::SIGN_EXTEND, dl, DstVT, Op0);
15182 return DAG.getNode(ISD::SINT_TO_FP, dl, N->getValueType(0), P);
15185 // Transform (SINT_TO_FP (i64 ...)) into an x87 operation if we have
15186 // a 32-bit target where SSE doesn't support i64->FP operations.
15187 if (Op0.getOpcode() == ISD::LOAD) {
15188 LoadSDNode *Ld = cast<LoadSDNode>(Op0.getNode());
15189 EVT VT = Ld->getValueType(0);
15190 if (!Ld->isVolatile() && !N->getValueType(0).isVector() &&
15191 ISD::isNON_EXTLoad(Op0.getNode()) && Op0.hasOneUse() &&
15192 !XTLI->getSubtarget()->is64Bit() &&
15193 !DAG.getTargetLoweringInfo().isTypeLegal(VT)) {
15194 SDValue FILDChain = XTLI->BuildFILD(SDValue(N, 0), Ld->getValueType(0),
15195 Ld->getChain(), Op0, DAG);
15196 DAG.ReplaceAllUsesOfValueWith(Op0.getValue(1), FILDChain.getValue(1));
15203 static SDValue PerformFP_TO_SINTCombine(SDNode *N, SelectionDAG &DAG) {
15204 EVT VT = N->getValueType(0);
15206 // v4i8 = FP_TO_SINT() -> v4i8 = TRUNCATE (V4i32 = FP_TO_SINT()
15207 if (VT == MVT::v8i8 || VT == MVT::v4i8) {
15208 DebugLoc dl = N->getDebugLoc();
15209 MVT DstVT = VT == MVT::v4i8 ? MVT::v4i32 : MVT::v8i32;
15210 SDValue I = DAG.getNode(ISD::FP_TO_SINT, dl, DstVT, N->getOperand(0));
15211 return DAG.getNode(ISD::TRUNCATE, dl, VT, I);
15217 // Optimize RES, EFLAGS = X86ISD::ADC LHS, RHS, EFLAGS
15218 static SDValue PerformADCCombine(SDNode *N, SelectionDAG &DAG,
15219 X86TargetLowering::DAGCombinerInfo &DCI) {
15220 // If the LHS and RHS of the ADC node are zero, then it can't overflow and
15221 // the result is either zero or one (depending on the input carry bit).
15222 // Strength reduce this down to a "set on carry" aka SETCC_CARRY&1.
15223 if (X86::isZeroNode(N->getOperand(0)) &&
15224 X86::isZeroNode(N->getOperand(1)) &&
15225 // We don't have a good way to replace an EFLAGS use, so only do this when
15227 SDValue(N, 1).use_empty()) {
15228 DebugLoc DL = N->getDebugLoc();
15229 EVT VT = N->getValueType(0);
15230 SDValue CarryOut = DAG.getConstant(0, N->getValueType(1));
15231 SDValue Res1 = DAG.getNode(ISD::AND, DL, VT,
15232 DAG.getNode(X86ISD::SETCC_CARRY, DL, VT,
15233 DAG.getConstant(X86::COND_B,MVT::i8),
15235 DAG.getConstant(1, VT));
15236 return DCI.CombineTo(N, Res1, CarryOut);
15242 // fold (add Y, (sete X, 0)) -> adc 0, Y
15243 // (add Y, (setne X, 0)) -> sbb -1, Y
15244 // (sub (sete X, 0), Y) -> sbb 0, Y
15245 // (sub (setne X, 0), Y) -> adc -1, Y
15246 static SDValue OptimizeConditionalInDecrement(SDNode *N, SelectionDAG &DAG) {
15247 DebugLoc DL = N->getDebugLoc();
15249 // Look through ZExts.
15250 SDValue Ext = N->getOperand(N->getOpcode() == ISD::SUB ? 1 : 0);
15251 if (Ext.getOpcode() != ISD::ZERO_EXTEND || !Ext.hasOneUse())
15254 SDValue SetCC = Ext.getOperand(0);
15255 if (SetCC.getOpcode() != X86ISD::SETCC || !SetCC.hasOneUse())
15258 X86::CondCode CC = (X86::CondCode)SetCC.getConstantOperandVal(0);
15259 if (CC != X86::COND_E && CC != X86::COND_NE)
15262 SDValue Cmp = SetCC.getOperand(1);
15263 if (Cmp.getOpcode() != X86ISD::CMP || !Cmp.hasOneUse() ||
15264 !X86::isZeroNode(Cmp.getOperand(1)) ||
15265 !Cmp.getOperand(0).getValueType().isInteger())
15268 SDValue CmpOp0 = Cmp.getOperand(0);
15269 SDValue NewCmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32, CmpOp0,
15270 DAG.getConstant(1, CmpOp0.getValueType()));
15272 SDValue OtherVal = N->getOperand(N->getOpcode() == ISD::SUB ? 0 : 1);
15273 if (CC == X86::COND_NE)
15274 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::ADC : X86ISD::SBB,
15275 DL, OtherVal.getValueType(), OtherVal,
15276 DAG.getConstant(-1ULL, OtherVal.getValueType()), NewCmp);
15277 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::SBB : X86ISD::ADC,
15278 DL, OtherVal.getValueType(), OtherVal,
15279 DAG.getConstant(0, OtherVal.getValueType()), NewCmp);
15282 /// PerformADDCombine - Do target-specific dag combines on integer adds.
15283 static SDValue PerformAddCombine(SDNode *N, SelectionDAG &DAG,
15284 const X86Subtarget *Subtarget) {
15285 EVT VT = N->getValueType(0);
15286 SDValue Op0 = N->getOperand(0);
15287 SDValue Op1 = N->getOperand(1);
15289 // Try to synthesize horizontal adds from adds of shuffles.
15290 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) ||
15291 (Subtarget->hasAVX2() && (VT == MVT::v16i16 || VT == MVT::v8i32))) &&
15292 isHorizontalBinOp(Op0, Op1, true))
15293 return DAG.getNode(X86ISD::HADD, N->getDebugLoc(), VT, Op0, Op1);
15295 return OptimizeConditionalInDecrement(N, DAG);
15298 static SDValue PerformSubCombine(SDNode *N, SelectionDAG &DAG,
15299 const X86Subtarget *Subtarget) {
15300 SDValue Op0 = N->getOperand(0);
15301 SDValue Op1 = N->getOperand(1);
15303 // X86 can't encode an immediate LHS of a sub. See if we can push the
15304 // negation into a preceding instruction.
15305 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op0)) {
15306 // If the RHS of the sub is a XOR with one use and a constant, invert the
15307 // immediate. Then add one to the LHS of the sub so we can turn
15308 // X-Y -> X+~Y+1, saving one register.
15309 if (Op1->hasOneUse() && Op1.getOpcode() == ISD::XOR &&
15310 isa<ConstantSDNode>(Op1.getOperand(1))) {
15311 APInt XorC = cast<ConstantSDNode>(Op1.getOperand(1))->getAPIntValue();
15312 EVT VT = Op0.getValueType();
15313 SDValue NewXor = DAG.getNode(ISD::XOR, Op1.getDebugLoc(), VT,
15315 DAG.getConstant(~XorC, VT));
15316 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, NewXor,
15317 DAG.getConstant(C->getAPIntValue()+1, VT));
15321 // Try to synthesize horizontal adds from adds of shuffles.
15322 EVT VT = N->getValueType(0);
15323 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) ||
15324 (Subtarget->hasAVX2() && (VT == MVT::v16i16 || VT == MVT::v8i32))) &&
15325 isHorizontalBinOp(Op0, Op1, true))
15326 return DAG.getNode(X86ISD::HSUB, N->getDebugLoc(), VT, Op0, Op1);
15328 return OptimizeConditionalInDecrement(N, DAG);
15331 SDValue X86TargetLowering::PerformDAGCombine(SDNode *N,
15332 DAGCombinerInfo &DCI) const {
15333 SelectionDAG &DAG = DCI.DAG;
15334 switch (N->getOpcode()) {
15336 case ISD::EXTRACT_VECTOR_ELT:
15337 return PerformEXTRACT_VECTOR_ELTCombine(N, DAG, DCI);
15339 case ISD::SELECT: return PerformSELECTCombine(N, DAG, DCI, Subtarget);
15340 case X86ISD::CMOV: return PerformCMOVCombine(N, DAG, DCI);
15341 case ISD::ADD: return PerformAddCombine(N, DAG, Subtarget);
15342 case ISD::SUB: return PerformSubCombine(N, DAG, Subtarget);
15343 case X86ISD::ADC: return PerformADCCombine(N, DAG, DCI);
15344 case ISD::MUL: return PerformMulCombine(N, DAG, DCI);
15347 case ISD::SRL: return PerformShiftCombine(N, DAG, DCI, Subtarget);
15348 case ISD::AND: return PerformAndCombine(N, DAG, DCI, Subtarget);
15349 case ISD::OR: return PerformOrCombine(N, DAG, DCI, Subtarget);
15350 case ISD::XOR: return PerformXorCombine(N, DAG, DCI, Subtarget);
15351 case ISD::LOAD: return PerformLOADCombine(N, DAG, Subtarget);
15352 case ISD::STORE: return PerformSTORECombine(N, DAG, Subtarget);
15353 case ISD::UINT_TO_FP: return PerformUINT_TO_FPCombine(N, DAG);
15354 case ISD::SINT_TO_FP: return PerformSINT_TO_FPCombine(N, DAG, this);
15355 case ISD::FP_TO_SINT: return PerformFP_TO_SINTCombine(N, DAG);
15356 case ISD::FADD: return PerformFADDCombine(N, DAG, Subtarget);
15357 case ISD::FSUB: return PerformFSUBCombine(N, DAG, Subtarget);
15359 case X86ISD::FOR: return PerformFORCombine(N, DAG);
15360 case X86ISD::FAND: return PerformFANDCombine(N, DAG);
15361 case X86ISD::BT: return PerformBTCombine(N, DAG, DCI);
15362 case X86ISD::VZEXT_MOVL: return PerformVZEXT_MOVLCombine(N, DAG);
15363 case ISD::ANY_EXTEND:
15364 case ISD::ZERO_EXTEND: return PerformZExtCombine(N, DAG, DCI, Subtarget);
15365 case ISD::SIGN_EXTEND: return PerformSExtCombine(N, DAG, DCI, Subtarget);
15366 case ISD::TRUNCATE: return PerformTruncateCombine(N, DAG, DCI);
15367 case ISD::SETCC: return PerformISDSETCCCombine(N, DAG);
15368 case X86ISD::SETCC: return PerformSETCCCombine(N, DAG);
15369 case X86ISD::SHUFP: // Handle all target specific shuffles
15370 case X86ISD::PALIGN:
15371 case X86ISD::UNPCKH:
15372 case X86ISD::UNPCKL:
15373 case X86ISD::MOVHLPS:
15374 case X86ISD::MOVLHPS:
15375 case X86ISD::PSHUFD:
15376 case X86ISD::PSHUFHW:
15377 case X86ISD::PSHUFLW:
15378 case X86ISD::MOVSS:
15379 case X86ISD::MOVSD:
15380 case X86ISD::VPERMILP:
15381 case X86ISD::VPERM2X128:
15382 case ISD::VECTOR_SHUFFLE: return PerformShuffleCombine(N, DAG, DCI,Subtarget);
15388 /// isTypeDesirableForOp - Return true if the target has native support for
15389 /// the specified value type and it is 'desirable' to use the type for the
15390 /// given node type. e.g. On x86 i16 is legal, but undesirable since i16
15391 /// instruction encodings are longer and some i16 instructions are slow.
15392 bool X86TargetLowering::isTypeDesirableForOp(unsigned Opc, EVT VT) const {
15393 if (!isTypeLegal(VT))
15395 if (VT != MVT::i16)
15402 case ISD::SIGN_EXTEND:
15403 case ISD::ZERO_EXTEND:
15404 case ISD::ANY_EXTEND:
15417 /// IsDesirableToPromoteOp - This method query the target whether it is
15418 /// beneficial for dag combiner to promote the specified node. If true, it
15419 /// should return the desired promotion type by reference.
15420 bool X86TargetLowering::IsDesirableToPromoteOp(SDValue Op, EVT &PVT) const {
15421 EVT VT = Op.getValueType();
15422 if (VT != MVT::i16)
15425 bool Promote = false;
15426 bool Commute = false;
15427 switch (Op.getOpcode()) {
15430 LoadSDNode *LD = cast<LoadSDNode>(Op);
15431 // If the non-extending load has a single use and it's not live out, then it
15432 // might be folded.
15433 if (LD->getExtensionType() == ISD::NON_EXTLOAD /*&&
15434 Op.hasOneUse()*/) {
15435 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
15436 UE = Op.getNode()->use_end(); UI != UE; ++UI) {
15437 // The only case where we'd want to promote LOAD (rather then it being
15438 // promoted as an operand is when it's only use is liveout.
15439 if (UI->getOpcode() != ISD::CopyToReg)
15446 case ISD::SIGN_EXTEND:
15447 case ISD::ZERO_EXTEND:
15448 case ISD::ANY_EXTEND:
15453 SDValue N0 = Op.getOperand(0);
15454 // Look out for (store (shl (load), x)).
15455 if (MayFoldLoad(N0) && MayFoldIntoStore(Op))
15468 SDValue N0 = Op.getOperand(0);
15469 SDValue N1 = Op.getOperand(1);
15470 if (!Commute && MayFoldLoad(N1))
15472 // Avoid disabling potential load folding opportunities.
15473 if (MayFoldLoad(N0) && (!isa<ConstantSDNode>(N1) || MayFoldIntoStore(Op)))
15475 if (MayFoldLoad(N1) && (!isa<ConstantSDNode>(N0) || MayFoldIntoStore(Op)))
15485 //===----------------------------------------------------------------------===//
15486 // X86 Inline Assembly Support
15487 //===----------------------------------------------------------------------===//
15490 // Helper to match a string separated by whitespace.
15491 bool matchAsmImpl(StringRef s, ArrayRef<const StringRef *> args) {
15492 s = s.substr(s.find_first_not_of(" \t")); // Skip leading whitespace.
15494 for (unsigned i = 0, e = args.size(); i != e; ++i) {
15495 StringRef piece(*args[i]);
15496 if (!s.startswith(piece)) // Check if the piece matches.
15499 s = s.substr(piece.size());
15500 StringRef::size_type pos = s.find_first_not_of(" \t");
15501 if (pos == 0) // We matched a prefix.
15509 const VariadicFunction1<bool, StringRef, StringRef, matchAsmImpl> matchAsm={};
15512 bool X86TargetLowering::ExpandInlineAsm(CallInst *CI) const {
15513 InlineAsm *IA = cast<InlineAsm>(CI->getCalledValue());
15515 std::string AsmStr = IA->getAsmString();
15517 IntegerType *Ty = dyn_cast<IntegerType>(CI->getType());
15518 if (!Ty || Ty->getBitWidth() % 16 != 0)
15521 // TODO: should remove alternatives from the asmstring: "foo {a|b}" -> "foo a"
15522 SmallVector<StringRef, 4> AsmPieces;
15523 SplitString(AsmStr, AsmPieces, ";\n");
15525 switch (AsmPieces.size()) {
15526 default: return false;
15528 // FIXME: this should verify that we are targeting a 486 or better. If not,
15529 // we will turn this bswap into something that will be lowered to logical
15530 // ops instead of emitting the bswap asm. For now, we don't support 486 or
15531 // lower so don't worry about this.
15533 if (matchAsm(AsmPieces[0], "bswap", "$0") ||
15534 matchAsm(AsmPieces[0], "bswapl", "$0") ||
15535 matchAsm(AsmPieces[0], "bswapq", "$0") ||
15536 matchAsm(AsmPieces[0], "bswap", "${0:q}") ||
15537 matchAsm(AsmPieces[0], "bswapl", "${0:q}") ||
15538 matchAsm(AsmPieces[0], "bswapq", "${0:q}")) {
15539 // No need to check constraints, nothing other than the equivalent of
15540 // "=r,0" would be valid here.
15541 return IntrinsicLowering::LowerToByteSwap(CI);
15544 // rorw $$8, ${0:w} --> llvm.bswap.i16
15545 if (CI->getType()->isIntegerTy(16) &&
15546 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 &&
15547 (matchAsm(AsmPieces[0], "rorw", "$$8,", "${0:w}") ||
15548 matchAsm(AsmPieces[0], "rolw", "$$8,", "${0:w}"))) {
15550 const std::string &ConstraintsStr = IA->getConstraintString();
15551 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
15552 std::sort(AsmPieces.begin(), AsmPieces.end());
15553 if (AsmPieces.size() == 4 &&
15554 AsmPieces[0] == "~{cc}" &&
15555 AsmPieces[1] == "~{dirflag}" &&
15556 AsmPieces[2] == "~{flags}" &&
15557 AsmPieces[3] == "~{fpsr}")
15558 return IntrinsicLowering::LowerToByteSwap(CI);
15562 if (CI->getType()->isIntegerTy(32) &&
15563 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 &&
15564 matchAsm(AsmPieces[0], "rorw", "$$8,", "${0:w}") &&
15565 matchAsm(AsmPieces[1], "rorl", "$$16,", "$0") &&
15566 matchAsm(AsmPieces[2], "rorw", "$$8,", "${0:w}")) {
15568 const std::string &ConstraintsStr = IA->getConstraintString();
15569 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
15570 std::sort(AsmPieces.begin(), AsmPieces.end());
15571 if (AsmPieces.size() == 4 &&
15572 AsmPieces[0] == "~{cc}" &&
15573 AsmPieces[1] == "~{dirflag}" &&
15574 AsmPieces[2] == "~{flags}" &&
15575 AsmPieces[3] == "~{fpsr}")
15576 return IntrinsicLowering::LowerToByteSwap(CI);
15579 if (CI->getType()->isIntegerTy(64)) {
15580 InlineAsm::ConstraintInfoVector Constraints = IA->ParseConstraints();
15581 if (Constraints.size() >= 2 &&
15582 Constraints[0].Codes.size() == 1 && Constraints[0].Codes[0] == "A" &&
15583 Constraints[1].Codes.size() == 1 && Constraints[1].Codes[0] == "0") {
15584 // bswap %eax / bswap %edx / xchgl %eax, %edx -> llvm.bswap.i64
15585 if (matchAsm(AsmPieces[0], "bswap", "%eax") &&
15586 matchAsm(AsmPieces[1], "bswap", "%edx") &&
15587 matchAsm(AsmPieces[2], "xchgl", "%eax,", "%edx"))
15588 return IntrinsicLowering::LowerToByteSwap(CI);
15598 /// getConstraintType - Given a constraint letter, return the type of
15599 /// constraint it is for this target.
15600 X86TargetLowering::ConstraintType
15601 X86TargetLowering::getConstraintType(const std::string &Constraint) const {
15602 if (Constraint.size() == 1) {
15603 switch (Constraint[0]) {
15614 return C_RegisterClass;
15638 return TargetLowering::getConstraintType(Constraint);
15641 /// Examine constraint type and operand type and determine a weight value.
15642 /// This object must already have been set up with the operand type
15643 /// and the current alternative constraint selected.
15644 TargetLowering::ConstraintWeight
15645 X86TargetLowering::getSingleConstraintMatchWeight(
15646 AsmOperandInfo &info, const char *constraint) const {
15647 ConstraintWeight weight = CW_Invalid;
15648 Value *CallOperandVal = info.CallOperandVal;
15649 // If we don't have a value, we can't do a match,
15650 // but allow it at the lowest weight.
15651 if (CallOperandVal == NULL)
15653 Type *type = CallOperandVal->getType();
15654 // Look at the constraint type.
15655 switch (*constraint) {
15657 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
15668 if (CallOperandVal->getType()->isIntegerTy())
15669 weight = CW_SpecificReg;
15674 if (type->isFloatingPointTy())
15675 weight = CW_SpecificReg;
15678 if (type->isX86_MMXTy() && Subtarget->hasMMX())
15679 weight = CW_SpecificReg;
15683 if (((type->getPrimitiveSizeInBits() == 128) && Subtarget->hasSSE1()) ||
15684 ((type->getPrimitiveSizeInBits() == 256) && Subtarget->hasAVX()))
15685 weight = CW_Register;
15688 if (ConstantInt *C = dyn_cast<ConstantInt>(info.CallOperandVal)) {
15689 if (C->getZExtValue() <= 31)
15690 weight = CW_Constant;
15694 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
15695 if (C->getZExtValue() <= 63)
15696 weight = CW_Constant;
15700 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
15701 if ((C->getSExtValue() >= -0x80) && (C->getSExtValue() <= 0x7f))
15702 weight = CW_Constant;
15706 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
15707 if ((C->getZExtValue() == 0xff) || (C->getZExtValue() == 0xffff))
15708 weight = CW_Constant;
15712 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
15713 if (C->getZExtValue() <= 3)
15714 weight = CW_Constant;
15718 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
15719 if (C->getZExtValue() <= 0xff)
15720 weight = CW_Constant;
15725 if (dyn_cast<ConstantFP>(CallOperandVal)) {
15726 weight = CW_Constant;
15730 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
15731 if ((C->getSExtValue() >= -0x80000000LL) &&
15732 (C->getSExtValue() <= 0x7fffffffLL))
15733 weight = CW_Constant;
15737 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
15738 if (C->getZExtValue() <= 0xffffffff)
15739 weight = CW_Constant;
15746 /// LowerXConstraint - try to replace an X constraint, which matches anything,
15747 /// with another that has more specific requirements based on the type of the
15748 /// corresponding operand.
15749 const char *X86TargetLowering::
15750 LowerXConstraint(EVT ConstraintVT) const {
15751 // FP X constraints get lowered to SSE1/2 registers if available, otherwise
15752 // 'f' like normal targets.
15753 if (ConstraintVT.isFloatingPoint()) {
15754 if (Subtarget->hasSSE2())
15756 if (Subtarget->hasSSE1())
15760 return TargetLowering::LowerXConstraint(ConstraintVT);
15763 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
15764 /// vector. If it is invalid, don't add anything to Ops.
15765 void X86TargetLowering::LowerAsmOperandForConstraint(SDValue Op,
15766 std::string &Constraint,
15767 std::vector<SDValue>&Ops,
15768 SelectionDAG &DAG) const {
15769 SDValue Result(0, 0);
15771 // Only support length 1 constraints for now.
15772 if (Constraint.length() > 1) return;
15774 char ConstraintLetter = Constraint[0];
15775 switch (ConstraintLetter) {
15778 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
15779 if (C->getZExtValue() <= 31) {
15780 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
15786 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
15787 if (C->getZExtValue() <= 63) {
15788 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
15794 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
15795 if ((int8_t)C->getSExtValue() == C->getSExtValue()) {
15796 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
15802 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
15803 if (C->getZExtValue() <= 255) {
15804 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
15810 // 32-bit signed value
15811 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
15812 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
15813 C->getSExtValue())) {
15814 // Widen to 64 bits here to get it sign extended.
15815 Result = DAG.getTargetConstant(C->getSExtValue(), MVT::i64);
15818 // FIXME gcc accepts some relocatable values here too, but only in certain
15819 // memory models; it's complicated.
15824 // 32-bit unsigned value
15825 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
15826 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
15827 C->getZExtValue())) {
15828 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
15832 // FIXME gcc accepts some relocatable values here too, but only in certain
15833 // memory models; it's complicated.
15837 // Literal immediates are always ok.
15838 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op)) {
15839 // Widen to 64 bits here to get it sign extended.
15840 Result = DAG.getTargetConstant(CST->getSExtValue(), MVT::i64);
15844 // In any sort of PIC mode addresses need to be computed at runtime by
15845 // adding in a register or some sort of table lookup. These can't
15846 // be used as immediates.
15847 if (Subtarget->isPICStyleGOT() || Subtarget->isPICStyleStubPIC())
15850 // If we are in non-pic codegen mode, we allow the address of a global (with
15851 // an optional displacement) to be used with 'i'.
15852 GlobalAddressSDNode *GA = 0;
15853 int64_t Offset = 0;
15855 // Match either (GA), (GA+C), (GA+C1+C2), etc.
15857 if ((GA = dyn_cast<GlobalAddressSDNode>(Op))) {
15858 Offset += GA->getOffset();
15860 } else if (Op.getOpcode() == ISD::ADD) {
15861 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
15862 Offset += C->getZExtValue();
15863 Op = Op.getOperand(0);
15866 } else if (Op.getOpcode() == ISD::SUB) {
15867 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
15868 Offset += -C->getZExtValue();
15869 Op = Op.getOperand(0);
15874 // Otherwise, this isn't something we can handle, reject it.
15878 const GlobalValue *GV = GA->getGlobal();
15879 // If we require an extra load to get this address, as in PIC mode, we
15880 // can't accept it.
15881 if (isGlobalStubReference(Subtarget->ClassifyGlobalReference(GV,
15882 getTargetMachine())))
15885 Result = DAG.getTargetGlobalAddress(GV, Op.getDebugLoc(),
15886 GA->getValueType(0), Offset);
15891 if (Result.getNode()) {
15892 Ops.push_back(Result);
15895 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
15898 std::pair<unsigned, const TargetRegisterClass*>
15899 X86TargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
15901 // First, see if this is a constraint that directly corresponds to an LLVM
15903 if (Constraint.size() == 1) {
15904 // GCC Constraint Letters
15905 switch (Constraint[0]) {
15907 // TODO: Slight differences here in allocation order and leaving
15908 // RIP in the class. Do they matter any more here than they do
15909 // in the normal allocation?
15910 case 'q': // GENERAL_REGS in 64-bit mode, Q_REGS in 32-bit mode.
15911 if (Subtarget->is64Bit()) {
15912 if (VT == MVT::i32 || VT == MVT::f32)
15913 return std::make_pair(0U, &X86::GR32RegClass);
15914 if (VT == MVT::i16)
15915 return std::make_pair(0U, &X86::GR16RegClass);
15916 if (VT == MVT::i8 || VT == MVT::i1)
15917 return std::make_pair(0U, &X86::GR8RegClass);
15918 if (VT == MVT::i64 || VT == MVT::f64)
15919 return std::make_pair(0U, &X86::GR64RegClass);
15922 // 32-bit fallthrough
15923 case 'Q': // Q_REGS
15924 if (VT == MVT::i32 || VT == MVT::f32)
15925 return std::make_pair(0U, &X86::GR32_ABCDRegClass);
15926 if (VT == MVT::i16)
15927 return std::make_pair(0U, &X86::GR16_ABCDRegClass);
15928 if (VT == MVT::i8 || VT == MVT::i1)
15929 return std::make_pair(0U, &X86::GR8_ABCD_LRegClass);
15930 if (VT == MVT::i64)
15931 return std::make_pair(0U, &X86::GR64_ABCDRegClass);
15933 case 'r': // GENERAL_REGS
15934 case 'l': // INDEX_REGS
15935 if (VT == MVT::i8 || VT == MVT::i1)
15936 return std::make_pair(0U, &X86::GR8RegClass);
15937 if (VT == MVT::i16)
15938 return std::make_pair(0U, &X86::GR16RegClass);
15939 if (VT == MVT::i32 || VT == MVT::f32 || !Subtarget->is64Bit())
15940 return std::make_pair(0U, &X86::GR32RegClass);
15941 return std::make_pair(0U, &X86::GR64RegClass);
15942 case 'R': // LEGACY_REGS
15943 if (VT == MVT::i8 || VT == MVT::i1)
15944 return std::make_pair(0U, &X86::GR8_NOREXRegClass);
15945 if (VT == MVT::i16)
15946 return std::make_pair(0U, &X86::GR16_NOREXRegClass);
15947 if (VT == MVT::i32 || !Subtarget->is64Bit())
15948 return std::make_pair(0U, &X86::GR32_NOREXRegClass);
15949 return std::make_pair(0U, &X86::GR64_NOREXRegClass);
15950 case 'f': // FP Stack registers.
15951 // If SSE is enabled for this VT, use f80 to ensure the isel moves the
15952 // value to the correct fpstack register class.
15953 if (VT == MVT::f32 && !isScalarFPTypeInSSEReg(VT))
15954 return std::make_pair(0U, &X86::RFP32RegClass);
15955 if (VT == MVT::f64 && !isScalarFPTypeInSSEReg(VT))
15956 return std::make_pair(0U, &X86::RFP64RegClass);
15957 return std::make_pair(0U, &X86::RFP80RegClass);
15958 case 'y': // MMX_REGS if MMX allowed.
15959 if (!Subtarget->hasMMX()) break;
15960 return std::make_pair(0U, &X86::VR64RegClass);
15961 case 'Y': // SSE_REGS if SSE2 allowed
15962 if (!Subtarget->hasSSE2()) break;
15964 case 'x': // SSE_REGS if SSE1 allowed or AVX_REGS if AVX allowed
15965 if (!Subtarget->hasSSE1()) break;
15967 switch (VT.getSimpleVT().SimpleTy) {
15969 // Scalar SSE types.
15972 return std::make_pair(0U, &X86::FR32RegClass);
15975 return std::make_pair(0U, &X86::FR64RegClass);
15983 return std::make_pair(0U, &X86::VR128RegClass);
15991 return std::make_pair(0U, &X86::VR256RegClass);
15997 // Use the default implementation in TargetLowering to convert the register
15998 // constraint into a member of a register class.
15999 std::pair<unsigned, const TargetRegisterClass*> Res;
16000 Res = TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
16002 // Not found as a standard register?
16003 if (Res.second == 0) {
16004 // Map st(0) -> st(7) -> ST0
16005 if (Constraint.size() == 7 && Constraint[0] == '{' &&
16006 tolower(Constraint[1]) == 's' &&
16007 tolower(Constraint[2]) == 't' &&
16008 Constraint[3] == '(' &&
16009 (Constraint[4] >= '0' && Constraint[4] <= '7') &&
16010 Constraint[5] == ')' &&
16011 Constraint[6] == '}') {
16013 Res.first = X86::ST0+Constraint[4]-'0';
16014 Res.second = &X86::RFP80RegClass;
16018 // GCC allows "st(0)" to be called just plain "st".
16019 if (StringRef("{st}").equals_lower(Constraint)) {
16020 Res.first = X86::ST0;
16021 Res.second = &X86::RFP80RegClass;
16026 if (StringRef("{flags}").equals_lower(Constraint)) {
16027 Res.first = X86::EFLAGS;
16028 Res.second = &X86::CCRRegClass;
16032 // 'A' means EAX + EDX.
16033 if (Constraint == "A") {
16034 Res.first = X86::EAX;
16035 Res.second = &X86::GR32_ADRegClass;
16041 // Otherwise, check to see if this is a register class of the wrong value
16042 // type. For example, we want to map "{ax},i32" -> {eax}, we don't want it to
16043 // turn into {ax},{dx}.
16044 if (Res.second->hasType(VT))
16045 return Res; // Correct type already, nothing to do.
16047 // All of the single-register GCC register classes map their values onto
16048 // 16-bit register pieces "ax","dx","cx","bx","si","di","bp","sp". If we
16049 // really want an 8-bit or 32-bit register, map to the appropriate register
16050 // class and return the appropriate register.
16051 if (Res.second == &X86::GR16RegClass) {
16052 if (VT == MVT::i8) {
16053 unsigned DestReg = 0;
16054 switch (Res.first) {
16056 case X86::AX: DestReg = X86::AL; break;
16057 case X86::DX: DestReg = X86::DL; break;
16058 case X86::CX: DestReg = X86::CL; break;
16059 case X86::BX: DestReg = X86::BL; break;
16062 Res.first = DestReg;
16063 Res.second = &X86::GR8RegClass;
16065 } else if (VT == MVT::i32) {
16066 unsigned DestReg = 0;
16067 switch (Res.first) {
16069 case X86::AX: DestReg = X86::EAX; break;
16070 case X86::DX: DestReg = X86::EDX; break;
16071 case X86::CX: DestReg = X86::ECX; break;
16072 case X86::BX: DestReg = X86::EBX; break;
16073 case X86::SI: DestReg = X86::ESI; break;
16074 case X86::DI: DestReg = X86::EDI; break;
16075 case X86::BP: DestReg = X86::EBP; break;
16076 case X86::SP: DestReg = X86::ESP; break;
16079 Res.first = DestReg;
16080 Res.second = &X86::GR32RegClass;
16082 } else if (VT == MVT::i64) {
16083 unsigned DestReg = 0;
16084 switch (Res.first) {
16086 case X86::AX: DestReg = X86::RAX; break;
16087 case X86::DX: DestReg = X86::RDX; break;
16088 case X86::CX: DestReg = X86::RCX; break;
16089 case X86::BX: DestReg = X86::RBX; break;
16090 case X86::SI: DestReg = X86::RSI; break;
16091 case X86::DI: DestReg = X86::RDI; break;
16092 case X86::BP: DestReg = X86::RBP; break;
16093 case X86::SP: DestReg = X86::RSP; break;
16096 Res.first = DestReg;
16097 Res.second = &X86::GR64RegClass;
16100 } else if (Res.second == &X86::FR32RegClass ||
16101 Res.second == &X86::FR64RegClass ||
16102 Res.second == &X86::VR128RegClass) {
16103 // Handle references to XMM physical registers that got mapped into the
16104 // wrong class. This can happen with constraints like {xmm0} where the
16105 // target independent register mapper will just pick the first match it can
16106 // find, ignoring the required type.
16107 if (VT == MVT::f32)
16108 Res.second = &X86::FR32RegClass;
16109 else if (VT == MVT::f64)
16110 Res.second = &X86::FR64RegClass;
16111 else if (X86::VR128RegClass.hasType(VT))
16112 Res.second = &X86::VR128RegClass;