1 //===-- X86ISelLowering.cpp - X86 DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that X86 uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "x86-isel"
17 #include "X86InstrBuilder.h"
18 #include "X86ISelLowering.h"
19 #include "X86MCTargetExpr.h"
20 #include "X86TargetMachine.h"
21 #include "X86TargetObjectFile.h"
22 #include "llvm/CallingConv.h"
23 #include "llvm/Constants.h"
24 #include "llvm/DerivedTypes.h"
25 #include "llvm/GlobalAlias.h"
26 #include "llvm/GlobalVariable.h"
27 #include "llvm/Function.h"
28 #include "llvm/Instructions.h"
29 #include "llvm/Intrinsics.h"
30 #include "llvm/LLVMContext.h"
31 #include "llvm/CodeGen/MachineFrameInfo.h"
32 #include "llvm/CodeGen/MachineFunction.h"
33 #include "llvm/CodeGen/MachineInstrBuilder.h"
34 #include "llvm/CodeGen/MachineJumpTableInfo.h"
35 #include "llvm/CodeGen/MachineModuleInfo.h"
36 #include "llvm/CodeGen/MachineRegisterInfo.h"
37 #include "llvm/CodeGen/PseudoSourceValue.h"
38 #include "llvm/MC/MCAsmInfo.h"
39 #include "llvm/MC/MCContext.h"
40 #include "llvm/MC/MCSymbol.h"
41 #include "llvm/ADT/BitVector.h"
42 #include "llvm/ADT/SmallSet.h"
43 #include "llvm/ADT/Statistic.h"
44 #include "llvm/ADT/StringExtras.h"
45 #include "llvm/ADT/VectorExtras.h"
46 #include "llvm/Support/CommandLine.h"
47 #include "llvm/Support/Debug.h"
48 #include "llvm/Support/Dwarf.h"
49 #include "llvm/Support/ErrorHandling.h"
50 #include "llvm/Support/MathExtras.h"
51 #include "llvm/Support/raw_ostream.h"
53 using namespace dwarf;
55 STATISTIC(NumTailCalls, "Number of tail calls");
58 DisableMMX("disable-mmx", cl::Hidden, cl::desc("Disable use of MMX"));
60 // Disable16Bit - 16-bit operations typically have a larger encoding than
61 // corresponding 32-bit instructions, and 16-bit code is slow on some
62 // processors. This is an experimental flag to disable 16-bit operations
63 // (which forces them to be Legalized to 32-bit operations).
65 Disable16Bit("disable-16bit", cl::Hidden,
66 cl::desc("Disable use of 16-bit instructions"));
68 // Forward declarations.
69 static SDValue getMOVL(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1,
72 static TargetLoweringObjectFile *createTLOF(X86TargetMachine &TM) {
73 switch (TM.getSubtarget<X86Subtarget>().TargetType) {
74 default: llvm_unreachable("unknown subtarget type");
75 case X86Subtarget::isDarwin:
76 if (TM.getSubtarget<X86Subtarget>().is64Bit())
77 return new X8664_MachoTargetObjectFile();
78 return new TargetLoweringObjectFileMachO();
79 case X86Subtarget::isELF:
80 if (TM.getSubtarget<X86Subtarget>().is64Bit())
81 return new X8664_ELFTargetObjectFile(TM);
82 return new X8632_ELFTargetObjectFile(TM);
83 case X86Subtarget::isMingw:
84 case X86Subtarget::isCygwin:
85 case X86Subtarget::isWindows:
86 return new TargetLoweringObjectFileCOFF();
90 X86TargetLowering::X86TargetLowering(X86TargetMachine &TM)
91 : TargetLowering(TM, createTLOF(TM)) {
92 Subtarget = &TM.getSubtarget<X86Subtarget>();
93 X86ScalarSSEf64 = Subtarget->hasSSE2();
94 X86ScalarSSEf32 = Subtarget->hasSSE1();
95 X86StackPtr = Subtarget->is64Bit() ? X86::RSP : X86::ESP;
97 RegInfo = TM.getRegisterInfo();
100 // Set up the TargetLowering object.
102 // X86 is weird, it always uses i8 for shift amounts and setcc results.
103 setShiftAmountType(MVT::i8);
104 setBooleanContents(ZeroOrOneBooleanContent);
105 setSchedulingPreference(SchedulingForRegPressure);
106 setStackPointerRegisterToSaveRestore(X86StackPtr);
108 if (Subtarget->isTargetDarwin()) {
109 // Darwin should use _setjmp/_longjmp instead of setjmp/longjmp.
110 setUseUnderscoreSetJmp(false);
111 setUseUnderscoreLongJmp(false);
112 } else if (Subtarget->isTargetMingw()) {
113 // MS runtime is weird: it exports _setjmp, but longjmp!
114 setUseUnderscoreSetJmp(true);
115 setUseUnderscoreLongJmp(false);
117 setUseUnderscoreSetJmp(true);
118 setUseUnderscoreLongJmp(true);
121 // Set up the register classes.
122 addRegisterClass(MVT::i8, X86::GR8RegisterClass);
124 addRegisterClass(MVT::i16, X86::GR16RegisterClass);
125 addRegisterClass(MVT::i32, X86::GR32RegisterClass);
126 if (Subtarget->is64Bit())
127 addRegisterClass(MVT::i64, X86::GR64RegisterClass);
129 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
131 // We don't accept any truncstore of integer registers.
132 setTruncStoreAction(MVT::i64, MVT::i32, Expand);
134 setTruncStoreAction(MVT::i64, MVT::i16, Expand);
135 setTruncStoreAction(MVT::i64, MVT::i8 , Expand);
137 setTruncStoreAction(MVT::i32, MVT::i16, Expand);
138 setTruncStoreAction(MVT::i32, MVT::i8 , Expand);
139 setTruncStoreAction(MVT::i16, MVT::i8, Expand);
141 // SETOEQ and SETUNE require checking two conditions.
142 setCondCodeAction(ISD::SETOEQ, MVT::f32, Expand);
143 setCondCodeAction(ISD::SETOEQ, MVT::f64, Expand);
144 setCondCodeAction(ISD::SETOEQ, MVT::f80, Expand);
145 setCondCodeAction(ISD::SETUNE, MVT::f32, Expand);
146 setCondCodeAction(ISD::SETUNE, MVT::f64, Expand);
147 setCondCodeAction(ISD::SETUNE, MVT::f80, Expand);
149 // Promote all UINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have this
151 setOperationAction(ISD::UINT_TO_FP , MVT::i1 , Promote);
152 setOperationAction(ISD::UINT_TO_FP , MVT::i8 , Promote);
153 setOperationAction(ISD::UINT_TO_FP , MVT::i16 , Promote);
155 if (Subtarget->is64Bit()) {
156 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote);
157 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Expand);
158 } else if (!UseSoftFloat) {
159 if (X86ScalarSSEf64) {
160 // We have an impenetrably clever algorithm for ui64->double only.
161 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
163 // We have an algorithm for SSE2, and we turn this into a 64-bit
164 // FILD for other targets.
165 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Custom);
168 // Promote i1/i8 SINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have
170 setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote);
171 setOperationAction(ISD::SINT_TO_FP , MVT::i8 , Promote);
174 // SSE has no i16 to fp conversion, only i32
175 if (X86ScalarSSEf32) {
176 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
177 // f32 and f64 cases are Legal, f80 case is not
178 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
180 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Custom);
181 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
184 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
185 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Promote);
188 // In 32-bit mode these are custom lowered. In 64-bit mode F32 and F64
189 // are Legal, f80 is custom lowered.
190 setOperationAction(ISD::FP_TO_SINT , MVT::i64 , Custom);
191 setOperationAction(ISD::SINT_TO_FP , MVT::i64 , Custom);
193 // Promote i1/i8 FP_TO_SINT to larger FP_TO_SINTS's, as X86 doesn't have
195 setOperationAction(ISD::FP_TO_SINT , MVT::i1 , Promote);
196 setOperationAction(ISD::FP_TO_SINT , MVT::i8 , Promote);
198 if (X86ScalarSSEf32) {
199 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Promote);
200 // f32 and f64 cases are Legal, f80 case is not
201 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
203 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Custom);
204 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
207 // Handle FP_TO_UINT by promoting the destination to a larger signed
209 setOperationAction(ISD::FP_TO_UINT , MVT::i1 , Promote);
210 setOperationAction(ISD::FP_TO_UINT , MVT::i8 , Promote);
211 setOperationAction(ISD::FP_TO_UINT , MVT::i16 , Promote);
213 if (Subtarget->is64Bit()) {
214 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Expand);
215 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote);
216 } else if (!UseSoftFloat) {
217 if (X86ScalarSSEf32 && !Subtarget->hasSSE3())
218 // Expand FP_TO_UINT into a select.
219 // FIXME: We would like to use a Custom expander here eventually to do
220 // the optimal thing for SSE vs. the default expansion in the legalizer.
221 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Expand);
223 // With SSE3 we can use fisttpll to convert to a signed i64; without
224 // SSE, we're stuck with a fistpll.
225 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Custom);
228 // TODO: when we have SSE, these could be more efficient, by using movd/movq.
229 if (!X86ScalarSSEf64) {
230 setOperationAction(ISD::BIT_CONVERT , MVT::f32 , Expand);
231 setOperationAction(ISD::BIT_CONVERT , MVT::i32 , Expand);
234 // Scalar integer divide and remainder are lowered to use operations that
235 // produce two results, to match the available instructions. This exposes
236 // the two-result form to trivial CSE, which is able to combine x/y and x%y
237 // into a single instruction.
239 // Scalar integer multiply-high is also lowered to use two-result
240 // operations, to match the available instructions. However, plain multiply
241 // (low) operations are left as Legal, as there are single-result
242 // instructions for this in x86. Using the two-result multiply instructions
243 // when both high and low results are needed must be arranged by dagcombine.
244 setOperationAction(ISD::MULHS , MVT::i8 , Expand);
245 setOperationAction(ISD::MULHU , MVT::i8 , Expand);
246 setOperationAction(ISD::SDIV , MVT::i8 , Expand);
247 setOperationAction(ISD::UDIV , MVT::i8 , Expand);
248 setOperationAction(ISD::SREM , MVT::i8 , Expand);
249 setOperationAction(ISD::UREM , MVT::i8 , Expand);
250 setOperationAction(ISD::MULHS , MVT::i16 , Expand);
251 setOperationAction(ISD::MULHU , MVT::i16 , Expand);
252 setOperationAction(ISD::SDIV , MVT::i16 , Expand);
253 setOperationAction(ISD::UDIV , MVT::i16 , Expand);
254 setOperationAction(ISD::SREM , MVT::i16 , Expand);
255 setOperationAction(ISD::UREM , MVT::i16 , Expand);
256 setOperationAction(ISD::MULHS , MVT::i32 , Expand);
257 setOperationAction(ISD::MULHU , MVT::i32 , Expand);
258 setOperationAction(ISD::SDIV , MVT::i32 , Expand);
259 setOperationAction(ISD::UDIV , MVT::i32 , Expand);
260 setOperationAction(ISD::SREM , MVT::i32 , Expand);
261 setOperationAction(ISD::UREM , MVT::i32 , Expand);
262 setOperationAction(ISD::MULHS , MVT::i64 , Expand);
263 setOperationAction(ISD::MULHU , MVT::i64 , Expand);
264 setOperationAction(ISD::SDIV , MVT::i64 , Expand);
265 setOperationAction(ISD::UDIV , MVT::i64 , Expand);
266 setOperationAction(ISD::SREM , MVT::i64 , Expand);
267 setOperationAction(ISD::UREM , MVT::i64 , Expand);
269 setOperationAction(ISD::BR_JT , MVT::Other, Expand);
270 setOperationAction(ISD::BRCOND , MVT::Other, Custom);
271 setOperationAction(ISD::BR_CC , MVT::Other, Expand);
272 setOperationAction(ISD::SELECT_CC , MVT::Other, Expand);
273 if (Subtarget->is64Bit())
274 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal);
275 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Legal);
276 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Legal);
277 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
278 setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand);
279 setOperationAction(ISD::FREM , MVT::f32 , Expand);
280 setOperationAction(ISD::FREM , MVT::f64 , Expand);
281 setOperationAction(ISD::FREM , MVT::f80 , Expand);
282 setOperationAction(ISD::FLT_ROUNDS_ , MVT::i32 , Custom);
284 setOperationAction(ISD::CTPOP , MVT::i8 , Expand);
285 setOperationAction(ISD::CTTZ , MVT::i8 , Custom);
286 setOperationAction(ISD::CTLZ , MVT::i8 , Custom);
287 setOperationAction(ISD::CTPOP , MVT::i16 , Expand);
289 setOperationAction(ISD::CTTZ , MVT::i16 , Expand);
290 setOperationAction(ISD::CTLZ , MVT::i16 , Expand);
292 setOperationAction(ISD::CTTZ , MVT::i16 , Custom);
293 setOperationAction(ISD::CTLZ , MVT::i16 , Custom);
295 setOperationAction(ISD::CTPOP , MVT::i32 , Expand);
296 setOperationAction(ISD::CTTZ , MVT::i32 , Custom);
297 setOperationAction(ISD::CTLZ , MVT::i32 , Custom);
298 if (Subtarget->is64Bit()) {
299 setOperationAction(ISD::CTPOP , MVT::i64 , Expand);
300 setOperationAction(ISD::CTTZ , MVT::i64 , Custom);
301 setOperationAction(ISD::CTLZ , MVT::i64 , Custom);
304 setOperationAction(ISD::READCYCLECOUNTER , MVT::i64 , Custom);
305 setOperationAction(ISD::BSWAP , MVT::i16 , Expand);
307 // These should be promoted to a larger select which is supported.
308 setOperationAction(ISD::SELECT , MVT::i1 , Promote);
309 // X86 wants to expand cmov itself.
310 setOperationAction(ISD::SELECT , MVT::i8 , Custom);
312 setOperationAction(ISD::SELECT , MVT::i16 , Expand);
314 setOperationAction(ISD::SELECT , MVT::i16 , Custom);
315 setOperationAction(ISD::SELECT , MVT::i32 , Custom);
316 setOperationAction(ISD::SELECT , MVT::f32 , Custom);
317 setOperationAction(ISD::SELECT , MVT::f64 , Custom);
318 setOperationAction(ISD::SELECT , MVT::f80 , Custom);
319 setOperationAction(ISD::SETCC , MVT::i8 , Custom);
321 setOperationAction(ISD::SETCC , MVT::i16 , Expand);
323 setOperationAction(ISD::SETCC , MVT::i16 , Custom);
324 setOperationAction(ISD::SETCC , MVT::i32 , Custom);
325 setOperationAction(ISD::SETCC , MVT::f32 , Custom);
326 setOperationAction(ISD::SETCC , MVT::f64 , Custom);
327 setOperationAction(ISD::SETCC , MVT::f80 , Custom);
328 if (Subtarget->is64Bit()) {
329 setOperationAction(ISD::SELECT , MVT::i64 , Custom);
330 setOperationAction(ISD::SETCC , MVT::i64 , Custom);
332 setOperationAction(ISD::EH_RETURN , MVT::Other, Custom);
335 setOperationAction(ISD::ConstantPool , MVT::i32 , Custom);
336 setOperationAction(ISD::JumpTable , MVT::i32 , Custom);
337 setOperationAction(ISD::GlobalAddress , MVT::i32 , Custom);
338 setOperationAction(ISD::GlobalTLSAddress, MVT::i32 , Custom);
339 if (Subtarget->is64Bit())
340 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
341 setOperationAction(ISD::ExternalSymbol , MVT::i32 , Custom);
342 setOperationAction(ISD::BlockAddress , MVT::i32 , Custom);
343 if (Subtarget->is64Bit()) {
344 setOperationAction(ISD::ConstantPool , MVT::i64 , Custom);
345 setOperationAction(ISD::JumpTable , MVT::i64 , Custom);
346 setOperationAction(ISD::GlobalAddress , MVT::i64 , Custom);
347 setOperationAction(ISD::ExternalSymbol, MVT::i64 , Custom);
348 setOperationAction(ISD::BlockAddress , MVT::i64 , Custom);
350 // 64-bit addm sub, shl, sra, srl (iff 32-bit x86)
351 setOperationAction(ISD::SHL_PARTS , MVT::i32 , Custom);
352 setOperationAction(ISD::SRA_PARTS , MVT::i32 , Custom);
353 setOperationAction(ISD::SRL_PARTS , MVT::i32 , Custom);
354 if (Subtarget->is64Bit()) {
355 setOperationAction(ISD::SHL_PARTS , MVT::i64 , Custom);
356 setOperationAction(ISD::SRA_PARTS , MVT::i64 , Custom);
357 setOperationAction(ISD::SRL_PARTS , MVT::i64 , Custom);
360 if (Subtarget->hasSSE1())
361 setOperationAction(ISD::PREFETCH , MVT::Other, Legal);
363 if (!Subtarget->hasSSE2())
364 setOperationAction(ISD::MEMBARRIER , MVT::Other, Expand);
366 // Expand certain atomics
367 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i8, Custom);
368 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i16, Custom);
369 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i32, Custom);
370 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i64, Custom);
372 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i8, Custom);
373 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i16, Custom);
374 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i32, Custom);
375 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i64, Custom);
377 if (!Subtarget->is64Bit()) {
378 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i64, Custom);
379 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i64, Custom);
380 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i64, Custom);
381 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i64, Custom);
382 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i64, Custom);
383 setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i64, Custom);
384 setOperationAction(ISD::ATOMIC_SWAP, MVT::i64, Custom);
387 // FIXME - use subtarget debug flags
388 if (!Subtarget->isTargetDarwin() &&
389 !Subtarget->isTargetELF() &&
390 !Subtarget->isTargetCygMing()) {
391 setOperationAction(ISD::EH_LABEL, MVT::Other, Expand);
394 setOperationAction(ISD::EXCEPTIONADDR, MVT::i64, Expand);
395 setOperationAction(ISD::EHSELECTION, MVT::i64, Expand);
396 setOperationAction(ISD::EXCEPTIONADDR, MVT::i32, Expand);
397 setOperationAction(ISD::EHSELECTION, MVT::i32, Expand);
398 if (Subtarget->is64Bit()) {
399 setExceptionPointerRegister(X86::RAX);
400 setExceptionSelectorRegister(X86::RDX);
402 setExceptionPointerRegister(X86::EAX);
403 setExceptionSelectorRegister(X86::EDX);
405 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i32, Custom);
406 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i64, Custom);
408 setOperationAction(ISD::TRAMPOLINE, MVT::Other, Custom);
410 setOperationAction(ISD::TRAP, MVT::Other, Legal);
412 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
413 setOperationAction(ISD::VASTART , MVT::Other, Custom);
414 setOperationAction(ISD::VAEND , MVT::Other, Expand);
415 if (Subtarget->is64Bit()) {
416 setOperationAction(ISD::VAARG , MVT::Other, Custom);
417 setOperationAction(ISD::VACOPY , MVT::Other, Custom);
419 setOperationAction(ISD::VAARG , MVT::Other, Expand);
420 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
423 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
424 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
425 if (Subtarget->is64Bit())
426 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64, Expand);
427 if (Subtarget->isTargetCygMing())
428 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Custom);
430 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Expand);
432 if (!UseSoftFloat && X86ScalarSSEf64) {
433 // f32 and f64 use SSE.
434 // Set up the FP register classes.
435 addRegisterClass(MVT::f32, X86::FR32RegisterClass);
436 addRegisterClass(MVT::f64, X86::FR64RegisterClass);
438 // Use ANDPD to simulate FABS.
439 setOperationAction(ISD::FABS , MVT::f64, Custom);
440 setOperationAction(ISD::FABS , MVT::f32, Custom);
442 // Use XORP to simulate FNEG.
443 setOperationAction(ISD::FNEG , MVT::f64, Custom);
444 setOperationAction(ISD::FNEG , MVT::f32, Custom);
446 // Use ANDPD and ORPD to simulate FCOPYSIGN.
447 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
448 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
450 // We don't support sin/cos/fmod
451 setOperationAction(ISD::FSIN , MVT::f64, Expand);
452 setOperationAction(ISD::FCOS , MVT::f64, Expand);
453 setOperationAction(ISD::FSIN , MVT::f32, Expand);
454 setOperationAction(ISD::FCOS , MVT::f32, Expand);
456 // Expand FP immediates into loads from the stack, except for the special
458 addLegalFPImmediate(APFloat(+0.0)); // xorpd
459 addLegalFPImmediate(APFloat(+0.0f)); // xorps
460 } else if (!UseSoftFloat && X86ScalarSSEf32) {
461 // Use SSE for f32, x87 for f64.
462 // Set up the FP register classes.
463 addRegisterClass(MVT::f32, X86::FR32RegisterClass);
464 addRegisterClass(MVT::f64, X86::RFP64RegisterClass);
466 // Use ANDPS to simulate FABS.
467 setOperationAction(ISD::FABS , MVT::f32, Custom);
469 // Use XORP to simulate FNEG.
470 setOperationAction(ISD::FNEG , MVT::f32, Custom);
472 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
474 // Use ANDPS and ORPS to simulate FCOPYSIGN.
475 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
476 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
478 // We don't support sin/cos/fmod
479 setOperationAction(ISD::FSIN , MVT::f32, Expand);
480 setOperationAction(ISD::FCOS , MVT::f32, Expand);
482 // Special cases we handle for FP constants.
483 addLegalFPImmediate(APFloat(+0.0f)); // xorps
484 addLegalFPImmediate(APFloat(+0.0)); // FLD0
485 addLegalFPImmediate(APFloat(+1.0)); // FLD1
486 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
487 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
490 setOperationAction(ISD::FSIN , MVT::f64 , Expand);
491 setOperationAction(ISD::FCOS , MVT::f64 , Expand);
493 } else if (!UseSoftFloat) {
494 // f32 and f64 in x87.
495 // Set up the FP register classes.
496 addRegisterClass(MVT::f64, X86::RFP64RegisterClass);
497 addRegisterClass(MVT::f32, X86::RFP32RegisterClass);
499 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
500 setOperationAction(ISD::UNDEF, MVT::f32, Expand);
501 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
502 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
505 setOperationAction(ISD::FSIN , MVT::f64 , Expand);
506 setOperationAction(ISD::FCOS , MVT::f64 , Expand);
508 addLegalFPImmediate(APFloat(+0.0)); // FLD0
509 addLegalFPImmediate(APFloat(+1.0)); // FLD1
510 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
511 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
512 addLegalFPImmediate(APFloat(+0.0f)); // FLD0
513 addLegalFPImmediate(APFloat(+1.0f)); // FLD1
514 addLegalFPImmediate(APFloat(-0.0f)); // FLD0/FCHS
515 addLegalFPImmediate(APFloat(-1.0f)); // FLD1/FCHS
518 // Long double always uses X87.
520 addRegisterClass(MVT::f80, X86::RFP80RegisterClass);
521 setOperationAction(ISD::UNDEF, MVT::f80, Expand);
522 setOperationAction(ISD::FCOPYSIGN, MVT::f80, Expand);
525 APFloat TmpFlt(+0.0);
526 TmpFlt.convert(APFloat::x87DoubleExtended, APFloat::rmNearestTiesToEven,
528 addLegalFPImmediate(TmpFlt); // FLD0
530 addLegalFPImmediate(TmpFlt); // FLD0/FCHS
531 APFloat TmpFlt2(+1.0);
532 TmpFlt2.convert(APFloat::x87DoubleExtended, APFloat::rmNearestTiesToEven,
534 addLegalFPImmediate(TmpFlt2); // FLD1
535 TmpFlt2.changeSign();
536 addLegalFPImmediate(TmpFlt2); // FLD1/FCHS
540 setOperationAction(ISD::FSIN , MVT::f80 , Expand);
541 setOperationAction(ISD::FCOS , MVT::f80 , Expand);
545 // Always use a library call for pow.
546 setOperationAction(ISD::FPOW , MVT::f32 , Expand);
547 setOperationAction(ISD::FPOW , MVT::f64 , Expand);
548 setOperationAction(ISD::FPOW , MVT::f80 , Expand);
550 setOperationAction(ISD::FLOG, MVT::f80, Expand);
551 setOperationAction(ISD::FLOG2, MVT::f80, Expand);
552 setOperationAction(ISD::FLOG10, MVT::f80, Expand);
553 setOperationAction(ISD::FEXP, MVT::f80, Expand);
554 setOperationAction(ISD::FEXP2, MVT::f80, Expand);
556 // First set operation action for all vector types to either promote
557 // (for widening) or expand (for scalarization). Then we will selectively
558 // turn on ones that can be effectively codegen'd.
559 for (unsigned VT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
560 VT <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++VT) {
561 setOperationAction(ISD::ADD , (MVT::SimpleValueType)VT, Expand);
562 setOperationAction(ISD::SUB , (MVT::SimpleValueType)VT, Expand);
563 setOperationAction(ISD::FADD, (MVT::SimpleValueType)VT, Expand);
564 setOperationAction(ISD::FNEG, (MVT::SimpleValueType)VT, Expand);
565 setOperationAction(ISD::FSUB, (MVT::SimpleValueType)VT, Expand);
566 setOperationAction(ISD::MUL , (MVT::SimpleValueType)VT, Expand);
567 setOperationAction(ISD::FMUL, (MVT::SimpleValueType)VT, Expand);
568 setOperationAction(ISD::SDIV, (MVT::SimpleValueType)VT, Expand);
569 setOperationAction(ISD::UDIV, (MVT::SimpleValueType)VT, Expand);
570 setOperationAction(ISD::FDIV, (MVT::SimpleValueType)VT, Expand);
571 setOperationAction(ISD::SREM, (MVT::SimpleValueType)VT, Expand);
572 setOperationAction(ISD::UREM, (MVT::SimpleValueType)VT, Expand);
573 setOperationAction(ISD::LOAD, (MVT::SimpleValueType)VT, Expand);
574 setOperationAction(ISD::VECTOR_SHUFFLE, (MVT::SimpleValueType)VT, Expand);
575 setOperationAction(ISD::EXTRACT_VECTOR_ELT,(MVT::SimpleValueType)VT,Expand);
576 setOperationAction(ISD::EXTRACT_SUBVECTOR,(MVT::SimpleValueType)VT,Expand);
577 setOperationAction(ISD::INSERT_VECTOR_ELT,(MVT::SimpleValueType)VT, Expand);
578 setOperationAction(ISD::FABS, (MVT::SimpleValueType)VT, Expand);
579 setOperationAction(ISD::FSIN, (MVT::SimpleValueType)VT, Expand);
580 setOperationAction(ISD::FCOS, (MVT::SimpleValueType)VT, Expand);
581 setOperationAction(ISD::FREM, (MVT::SimpleValueType)VT, Expand);
582 setOperationAction(ISD::FPOWI, (MVT::SimpleValueType)VT, Expand);
583 setOperationAction(ISD::FSQRT, (MVT::SimpleValueType)VT, Expand);
584 setOperationAction(ISD::FCOPYSIGN, (MVT::SimpleValueType)VT, Expand);
585 setOperationAction(ISD::SMUL_LOHI, (MVT::SimpleValueType)VT, Expand);
586 setOperationAction(ISD::UMUL_LOHI, (MVT::SimpleValueType)VT, Expand);
587 setOperationAction(ISD::SDIVREM, (MVT::SimpleValueType)VT, Expand);
588 setOperationAction(ISD::UDIVREM, (MVT::SimpleValueType)VT, Expand);
589 setOperationAction(ISD::FPOW, (MVT::SimpleValueType)VT, Expand);
590 setOperationAction(ISD::CTPOP, (MVT::SimpleValueType)VT, Expand);
591 setOperationAction(ISD::CTTZ, (MVT::SimpleValueType)VT, Expand);
592 setOperationAction(ISD::CTLZ, (MVT::SimpleValueType)VT, Expand);
593 setOperationAction(ISD::SHL, (MVT::SimpleValueType)VT, Expand);
594 setOperationAction(ISD::SRA, (MVT::SimpleValueType)VT, Expand);
595 setOperationAction(ISD::SRL, (MVT::SimpleValueType)VT, Expand);
596 setOperationAction(ISD::ROTL, (MVT::SimpleValueType)VT, Expand);
597 setOperationAction(ISD::ROTR, (MVT::SimpleValueType)VT, Expand);
598 setOperationAction(ISD::BSWAP, (MVT::SimpleValueType)VT, Expand);
599 setOperationAction(ISD::VSETCC, (MVT::SimpleValueType)VT, Expand);
600 setOperationAction(ISD::FLOG, (MVT::SimpleValueType)VT, Expand);
601 setOperationAction(ISD::FLOG2, (MVT::SimpleValueType)VT, Expand);
602 setOperationAction(ISD::FLOG10, (MVT::SimpleValueType)VT, Expand);
603 setOperationAction(ISD::FEXP, (MVT::SimpleValueType)VT, Expand);
604 setOperationAction(ISD::FEXP2, (MVT::SimpleValueType)VT, Expand);
605 setOperationAction(ISD::FP_TO_UINT, (MVT::SimpleValueType)VT, Expand);
606 setOperationAction(ISD::FP_TO_SINT, (MVT::SimpleValueType)VT, Expand);
607 setOperationAction(ISD::UINT_TO_FP, (MVT::SimpleValueType)VT, Expand);
608 setOperationAction(ISD::SINT_TO_FP, (MVT::SimpleValueType)VT, Expand);
609 setOperationAction(ISD::SIGN_EXTEND_INREG, (MVT::SimpleValueType)VT,Expand);
610 setOperationAction(ISD::TRUNCATE, (MVT::SimpleValueType)VT, Expand);
611 setOperationAction(ISD::SIGN_EXTEND, (MVT::SimpleValueType)VT, Expand);
612 setOperationAction(ISD::ZERO_EXTEND, (MVT::SimpleValueType)VT, Expand);
613 setOperationAction(ISD::ANY_EXTEND, (MVT::SimpleValueType)VT, Expand);
614 for (unsigned InnerVT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
615 InnerVT <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++InnerVT)
616 setTruncStoreAction((MVT::SimpleValueType)VT,
617 (MVT::SimpleValueType)InnerVT, Expand);
618 setLoadExtAction(ISD::SEXTLOAD, (MVT::SimpleValueType)VT, Expand);
619 setLoadExtAction(ISD::ZEXTLOAD, (MVT::SimpleValueType)VT, Expand);
620 setLoadExtAction(ISD::EXTLOAD, (MVT::SimpleValueType)VT, Expand);
623 // FIXME: In order to prevent SSE instructions being expanded to MMX ones
624 // with -msoft-float, disable use of MMX as well.
625 if (!UseSoftFloat && !DisableMMX && Subtarget->hasMMX()) {
626 addRegisterClass(MVT::v8i8, X86::VR64RegisterClass);
627 addRegisterClass(MVT::v4i16, X86::VR64RegisterClass);
628 addRegisterClass(MVT::v2i32, X86::VR64RegisterClass);
629 addRegisterClass(MVT::v2f32, X86::VR64RegisterClass);
630 addRegisterClass(MVT::v1i64, X86::VR64RegisterClass);
632 setOperationAction(ISD::ADD, MVT::v8i8, Legal);
633 setOperationAction(ISD::ADD, MVT::v4i16, Legal);
634 setOperationAction(ISD::ADD, MVT::v2i32, Legal);
635 setOperationAction(ISD::ADD, MVT::v1i64, Legal);
637 setOperationAction(ISD::SUB, MVT::v8i8, Legal);
638 setOperationAction(ISD::SUB, MVT::v4i16, Legal);
639 setOperationAction(ISD::SUB, MVT::v2i32, Legal);
640 setOperationAction(ISD::SUB, MVT::v1i64, Legal);
642 setOperationAction(ISD::MULHS, MVT::v4i16, Legal);
643 setOperationAction(ISD::MUL, MVT::v4i16, Legal);
645 setOperationAction(ISD::AND, MVT::v8i8, Promote);
646 AddPromotedToType (ISD::AND, MVT::v8i8, MVT::v1i64);
647 setOperationAction(ISD::AND, MVT::v4i16, Promote);
648 AddPromotedToType (ISD::AND, MVT::v4i16, MVT::v1i64);
649 setOperationAction(ISD::AND, MVT::v2i32, Promote);
650 AddPromotedToType (ISD::AND, MVT::v2i32, MVT::v1i64);
651 setOperationAction(ISD::AND, MVT::v1i64, Legal);
653 setOperationAction(ISD::OR, MVT::v8i8, Promote);
654 AddPromotedToType (ISD::OR, MVT::v8i8, MVT::v1i64);
655 setOperationAction(ISD::OR, MVT::v4i16, Promote);
656 AddPromotedToType (ISD::OR, MVT::v4i16, MVT::v1i64);
657 setOperationAction(ISD::OR, MVT::v2i32, Promote);
658 AddPromotedToType (ISD::OR, MVT::v2i32, MVT::v1i64);
659 setOperationAction(ISD::OR, MVT::v1i64, Legal);
661 setOperationAction(ISD::XOR, MVT::v8i8, Promote);
662 AddPromotedToType (ISD::XOR, MVT::v8i8, MVT::v1i64);
663 setOperationAction(ISD::XOR, MVT::v4i16, Promote);
664 AddPromotedToType (ISD::XOR, MVT::v4i16, MVT::v1i64);
665 setOperationAction(ISD::XOR, MVT::v2i32, Promote);
666 AddPromotedToType (ISD::XOR, MVT::v2i32, MVT::v1i64);
667 setOperationAction(ISD::XOR, MVT::v1i64, Legal);
669 setOperationAction(ISD::LOAD, MVT::v8i8, Promote);
670 AddPromotedToType (ISD::LOAD, MVT::v8i8, MVT::v1i64);
671 setOperationAction(ISD::LOAD, MVT::v4i16, Promote);
672 AddPromotedToType (ISD::LOAD, MVT::v4i16, MVT::v1i64);
673 setOperationAction(ISD::LOAD, MVT::v2i32, Promote);
674 AddPromotedToType (ISD::LOAD, MVT::v2i32, MVT::v1i64);
675 setOperationAction(ISD::LOAD, MVT::v2f32, Promote);
676 AddPromotedToType (ISD::LOAD, MVT::v2f32, MVT::v1i64);
677 setOperationAction(ISD::LOAD, MVT::v1i64, Legal);
679 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i8, Custom);
680 setOperationAction(ISD::BUILD_VECTOR, MVT::v4i16, Custom);
681 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i32, Custom);
682 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f32, Custom);
683 setOperationAction(ISD::BUILD_VECTOR, MVT::v1i64, Custom);
685 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v8i8, Custom);
686 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4i16, Custom);
687 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i32, Custom);
688 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v1i64, Custom);
690 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2f32, Custom);
691 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i8, Custom);
692 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i16, Custom);
693 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v1i64, Custom);
695 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i16, Custom);
697 setOperationAction(ISD::SELECT, MVT::v8i8, Promote);
698 setOperationAction(ISD::SELECT, MVT::v4i16, Promote);
699 setOperationAction(ISD::SELECT, MVT::v2i32, Promote);
700 setOperationAction(ISD::SELECT, MVT::v1i64, Custom);
701 setOperationAction(ISD::VSETCC, MVT::v8i8, Custom);
702 setOperationAction(ISD::VSETCC, MVT::v4i16, Custom);
703 setOperationAction(ISD::VSETCC, MVT::v2i32, Custom);
706 if (!UseSoftFloat && Subtarget->hasSSE1()) {
707 addRegisterClass(MVT::v4f32, X86::VR128RegisterClass);
709 setOperationAction(ISD::FADD, MVT::v4f32, Legal);
710 setOperationAction(ISD::FSUB, MVT::v4f32, Legal);
711 setOperationAction(ISD::FMUL, MVT::v4f32, Legal);
712 setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
713 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal);
714 setOperationAction(ISD::FNEG, MVT::v4f32, Custom);
715 setOperationAction(ISD::LOAD, MVT::v4f32, Legal);
716 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
717 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f32, Custom);
718 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
719 setOperationAction(ISD::SELECT, MVT::v4f32, Custom);
720 setOperationAction(ISD::VSETCC, MVT::v4f32, Custom);
723 if (!UseSoftFloat && Subtarget->hasSSE2()) {
724 addRegisterClass(MVT::v2f64, X86::VR128RegisterClass);
726 // FIXME: Unfortunately -soft-float and -no-implicit-float means XMM
727 // registers cannot be used even for integer operations.
728 addRegisterClass(MVT::v16i8, X86::VR128RegisterClass);
729 addRegisterClass(MVT::v8i16, X86::VR128RegisterClass);
730 addRegisterClass(MVT::v4i32, X86::VR128RegisterClass);
731 addRegisterClass(MVT::v2i64, X86::VR128RegisterClass);
733 setOperationAction(ISD::ADD, MVT::v16i8, Legal);
734 setOperationAction(ISD::ADD, MVT::v8i16, Legal);
735 setOperationAction(ISD::ADD, MVT::v4i32, Legal);
736 setOperationAction(ISD::ADD, MVT::v2i64, Legal);
737 setOperationAction(ISD::MUL, MVT::v2i64, Custom);
738 setOperationAction(ISD::SUB, MVT::v16i8, Legal);
739 setOperationAction(ISD::SUB, MVT::v8i16, Legal);
740 setOperationAction(ISD::SUB, MVT::v4i32, Legal);
741 setOperationAction(ISD::SUB, MVT::v2i64, Legal);
742 setOperationAction(ISD::MUL, MVT::v8i16, Legal);
743 setOperationAction(ISD::FADD, MVT::v2f64, Legal);
744 setOperationAction(ISD::FSUB, MVT::v2f64, Legal);
745 setOperationAction(ISD::FMUL, MVT::v2f64, Legal);
746 setOperationAction(ISD::FDIV, MVT::v2f64, Legal);
747 setOperationAction(ISD::FSQRT, MVT::v2f64, Legal);
748 setOperationAction(ISD::FNEG, MVT::v2f64, Custom);
750 setOperationAction(ISD::VSETCC, MVT::v2f64, Custom);
751 setOperationAction(ISD::VSETCC, MVT::v16i8, Custom);
752 setOperationAction(ISD::VSETCC, MVT::v8i16, Custom);
753 setOperationAction(ISD::VSETCC, MVT::v4i32, Custom);
755 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Custom);
756 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Custom);
757 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
758 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
759 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
761 setOperationAction(ISD::CONCAT_VECTORS, MVT::v2f64, Custom);
762 setOperationAction(ISD::CONCAT_VECTORS, MVT::v2i64, Custom);
763 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i8, Custom);
764 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i16, Custom);
765 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4i32, Custom);
767 // Custom lower build_vector, vector_shuffle, and extract_vector_elt.
768 for (unsigned i = (unsigned)MVT::v16i8; i != (unsigned)MVT::v2i64; ++i) {
769 EVT VT = (MVT::SimpleValueType)i;
770 // Do not attempt to custom lower non-power-of-2 vectors
771 if (!isPowerOf2_32(VT.getVectorNumElements()))
773 // Do not attempt to custom lower non-128-bit vectors
774 if (!VT.is128BitVector())
776 setOperationAction(ISD::BUILD_VECTOR,
777 VT.getSimpleVT().SimpleTy, Custom);
778 setOperationAction(ISD::VECTOR_SHUFFLE,
779 VT.getSimpleVT().SimpleTy, Custom);
780 setOperationAction(ISD::EXTRACT_VECTOR_ELT,
781 VT.getSimpleVT().SimpleTy, Custom);
784 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f64, Custom);
785 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i64, Custom);
786 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Custom);
787 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Custom);
788 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f64, Custom);
789 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Custom);
791 if (Subtarget->is64Bit()) {
792 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
793 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
796 // Promote v16i8, v8i16, v4i32 load, select, and, or, xor to v2i64.
797 for (unsigned i = (unsigned)MVT::v16i8; i != (unsigned)MVT::v2i64; i++) {
798 MVT::SimpleValueType SVT = (MVT::SimpleValueType)i;
801 // Do not attempt to promote non-128-bit vectors
802 if (!VT.is128BitVector()) {
805 setOperationAction(ISD::AND, SVT, Promote);
806 AddPromotedToType (ISD::AND, SVT, MVT::v2i64);
807 setOperationAction(ISD::OR, SVT, Promote);
808 AddPromotedToType (ISD::OR, SVT, MVT::v2i64);
809 setOperationAction(ISD::XOR, SVT, Promote);
810 AddPromotedToType (ISD::XOR, SVT, MVT::v2i64);
811 setOperationAction(ISD::LOAD, SVT, Promote);
812 AddPromotedToType (ISD::LOAD, SVT, MVT::v2i64);
813 setOperationAction(ISD::SELECT, SVT, Promote);
814 AddPromotedToType (ISD::SELECT, SVT, MVT::v2i64);
817 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
819 // Custom lower v2i64 and v2f64 selects.
820 setOperationAction(ISD::LOAD, MVT::v2f64, Legal);
821 setOperationAction(ISD::LOAD, MVT::v2i64, Legal);
822 setOperationAction(ISD::SELECT, MVT::v2f64, Custom);
823 setOperationAction(ISD::SELECT, MVT::v2i64, Custom);
825 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal);
826 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal);
827 if (!DisableMMX && Subtarget->hasMMX()) {
828 setOperationAction(ISD::FP_TO_SINT, MVT::v2i32, Custom);
829 setOperationAction(ISD::SINT_TO_FP, MVT::v2i32, Custom);
833 if (Subtarget->hasSSE41()) {
834 // FIXME: Do we need to handle scalar-to-vector here?
835 setOperationAction(ISD::MUL, MVT::v4i32, Legal);
837 // i8 and i16 vectors are custom , because the source register and source
838 // source memory operand types are not the same width. f32 vectors are
839 // custom since the immediate controlling the insert encodes additional
841 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i8, Custom);
842 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
843 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
844 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
846 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i8, Custom);
847 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i16, Custom);
848 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i32, Custom);
849 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
851 if (Subtarget->is64Bit()) {
852 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Legal);
853 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Legal);
857 if (Subtarget->hasSSE42()) {
858 setOperationAction(ISD::VSETCC, MVT::v2i64, Custom);
861 if (!UseSoftFloat && Subtarget->hasAVX()) {
862 addRegisterClass(MVT::v8f32, X86::VR256RegisterClass);
863 addRegisterClass(MVT::v4f64, X86::VR256RegisterClass);
864 addRegisterClass(MVT::v8i32, X86::VR256RegisterClass);
865 addRegisterClass(MVT::v4i64, X86::VR256RegisterClass);
867 setOperationAction(ISD::LOAD, MVT::v8f32, Legal);
868 setOperationAction(ISD::LOAD, MVT::v8i32, Legal);
869 setOperationAction(ISD::LOAD, MVT::v4f64, Legal);
870 setOperationAction(ISD::LOAD, MVT::v4i64, Legal);
871 setOperationAction(ISD::FADD, MVT::v8f32, Legal);
872 setOperationAction(ISD::FSUB, MVT::v8f32, Legal);
873 setOperationAction(ISD::FMUL, MVT::v8f32, Legal);
874 setOperationAction(ISD::FDIV, MVT::v8f32, Legal);
875 setOperationAction(ISD::FSQRT, MVT::v8f32, Legal);
876 setOperationAction(ISD::FNEG, MVT::v8f32, Custom);
877 //setOperationAction(ISD::BUILD_VECTOR, MVT::v8f32, Custom);
878 //setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v8f32, Custom);
879 //setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8f32, Custom);
880 //setOperationAction(ISD::SELECT, MVT::v8f32, Custom);
881 //setOperationAction(ISD::VSETCC, MVT::v8f32, Custom);
883 // Operations to consider commented out -v16i16 v32i8
884 //setOperationAction(ISD::ADD, MVT::v16i16, Legal);
885 setOperationAction(ISD::ADD, MVT::v8i32, Custom);
886 setOperationAction(ISD::ADD, MVT::v4i64, Custom);
887 //setOperationAction(ISD::SUB, MVT::v32i8, Legal);
888 //setOperationAction(ISD::SUB, MVT::v16i16, Legal);
889 setOperationAction(ISD::SUB, MVT::v8i32, Custom);
890 setOperationAction(ISD::SUB, MVT::v4i64, Custom);
891 //setOperationAction(ISD::MUL, MVT::v16i16, Legal);
892 setOperationAction(ISD::FADD, MVT::v4f64, Legal);
893 setOperationAction(ISD::FSUB, MVT::v4f64, Legal);
894 setOperationAction(ISD::FMUL, MVT::v4f64, Legal);
895 setOperationAction(ISD::FDIV, MVT::v4f64, Legal);
896 setOperationAction(ISD::FSQRT, MVT::v4f64, Legal);
897 setOperationAction(ISD::FNEG, MVT::v4f64, Custom);
899 setOperationAction(ISD::VSETCC, MVT::v4f64, Custom);
900 // setOperationAction(ISD::VSETCC, MVT::v32i8, Custom);
901 // setOperationAction(ISD::VSETCC, MVT::v16i16, Custom);
902 setOperationAction(ISD::VSETCC, MVT::v8i32, Custom);
904 // setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v32i8, Custom);
905 // setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i16, Custom);
906 // setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i16, Custom);
907 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i32, Custom);
908 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8f32, Custom);
910 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f64, Custom);
911 setOperationAction(ISD::BUILD_VECTOR, MVT::v4i64, Custom);
912 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f64, Custom);
913 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4i64, Custom);
914 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f64, Custom);
915 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f64, Custom);
918 // Not sure we want to do this since there are no 256-bit integer
921 // Custom lower build_vector, vector_shuffle, and extract_vector_elt.
922 // This includes 256-bit vectors
923 for (unsigned i = (unsigned)MVT::v16i8; i != (unsigned)MVT::v4i64; ++i) {
924 EVT VT = (MVT::SimpleValueType)i;
926 // Do not attempt to custom lower non-power-of-2 vectors
927 if (!isPowerOf2_32(VT.getVectorNumElements()))
930 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
931 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
932 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
935 if (Subtarget->is64Bit()) {
936 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i64, Custom);
937 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i64, Custom);
942 // Not sure we want to do this since there are no 256-bit integer
945 // Promote v32i8, v16i16, v8i32 load, select, and, or, xor to v4i64.
946 // Including 256-bit vectors
947 for (unsigned i = (unsigned)MVT::v16i8; i != (unsigned)MVT::v4i64; i++) {
948 EVT VT = (MVT::SimpleValueType)i;
950 if (!VT.is256BitVector()) {
953 setOperationAction(ISD::AND, VT, Promote);
954 AddPromotedToType (ISD::AND, VT, MVT::v4i64);
955 setOperationAction(ISD::OR, VT, Promote);
956 AddPromotedToType (ISD::OR, VT, MVT::v4i64);
957 setOperationAction(ISD::XOR, VT, Promote);
958 AddPromotedToType (ISD::XOR, VT, MVT::v4i64);
959 setOperationAction(ISD::LOAD, VT, Promote);
960 AddPromotedToType (ISD::LOAD, VT, MVT::v4i64);
961 setOperationAction(ISD::SELECT, VT, Promote);
962 AddPromotedToType (ISD::SELECT, VT, MVT::v4i64);
965 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
969 // We want to custom lower some of our intrinsics.
970 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
972 // Add/Sub/Mul with overflow operations are custom lowered.
973 setOperationAction(ISD::SADDO, MVT::i32, Custom);
974 setOperationAction(ISD::SADDO, MVT::i64, Custom);
975 setOperationAction(ISD::UADDO, MVT::i32, Custom);
976 setOperationAction(ISD::UADDO, MVT::i64, Custom);
977 setOperationAction(ISD::SSUBO, MVT::i32, Custom);
978 setOperationAction(ISD::SSUBO, MVT::i64, Custom);
979 setOperationAction(ISD::USUBO, MVT::i32, Custom);
980 setOperationAction(ISD::USUBO, MVT::i64, Custom);
981 setOperationAction(ISD::SMULO, MVT::i32, Custom);
982 setOperationAction(ISD::SMULO, MVT::i64, Custom);
984 if (!Subtarget->is64Bit()) {
985 // These libcalls are not available in 32-bit.
986 setLibcallName(RTLIB::SHL_I128, 0);
987 setLibcallName(RTLIB::SRL_I128, 0);
988 setLibcallName(RTLIB::SRA_I128, 0);
991 // We have target-specific dag combine patterns for the following nodes:
992 setTargetDAGCombine(ISD::VECTOR_SHUFFLE);
993 setTargetDAGCombine(ISD::BUILD_VECTOR);
994 setTargetDAGCombine(ISD::SELECT);
995 setTargetDAGCombine(ISD::SHL);
996 setTargetDAGCombine(ISD::SRA);
997 setTargetDAGCombine(ISD::SRL);
998 setTargetDAGCombine(ISD::OR);
999 setTargetDAGCombine(ISD::STORE);
1000 setTargetDAGCombine(ISD::MEMBARRIER);
1001 setTargetDAGCombine(ISD::ZERO_EXTEND);
1002 if (Subtarget->is64Bit())
1003 setTargetDAGCombine(ISD::MUL);
1005 computeRegisterProperties();
1007 // FIXME: These should be based on subtarget info. Plus, the values should
1008 // be smaller when we are in optimizing for size mode.
1009 maxStoresPerMemset = 16; // For @llvm.memset -> sequence of stores
1010 maxStoresPerMemcpy = 16; // For @llvm.memcpy -> sequence of stores
1011 maxStoresPerMemmove = 3; // For @llvm.memmove -> sequence of stores
1012 setPrefLoopAlignment(16);
1013 benefitFromCodePlacementOpt = true;
1017 MVT::SimpleValueType X86TargetLowering::getSetCCResultType(EVT VT) const {
1022 /// getMaxByValAlign - Helper for getByValTypeAlignment to determine
1023 /// the desired ByVal argument alignment.
1024 static void getMaxByValAlign(const Type *Ty, unsigned &MaxAlign) {
1027 if (const VectorType *VTy = dyn_cast<VectorType>(Ty)) {
1028 if (VTy->getBitWidth() == 128)
1030 } else if (const ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
1031 unsigned EltAlign = 0;
1032 getMaxByValAlign(ATy->getElementType(), EltAlign);
1033 if (EltAlign > MaxAlign)
1034 MaxAlign = EltAlign;
1035 } else if (const StructType *STy = dyn_cast<StructType>(Ty)) {
1036 for (unsigned i = 0, e = STy->getNumElements(); i != e; ++i) {
1037 unsigned EltAlign = 0;
1038 getMaxByValAlign(STy->getElementType(i), EltAlign);
1039 if (EltAlign > MaxAlign)
1040 MaxAlign = EltAlign;
1048 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
1049 /// function arguments in the caller parameter area. For X86, aggregates
1050 /// that contain SSE vectors are placed at 16-byte boundaries while the rest
1051 /// are at 4-byte boundaries.
1052 unsigned X86TargetLowering::getByValTypeAlignment(const Type *Ty) const {
1053 if (Subtarget->is64Bit()) {
1054 // Max of 8 and alignment of type.
1055 unsigned TyAlign = TD->getABITypeAlignment(Ty);
1062 if (Subtarget->hasSSE1())
1063 getMaxByValAlign(Ty, Align);
1067 /// getOptimalMemOpType - Returns the target specific optimal type for load
1068 /// and store operations as a result of memset, memcpy, and memmove
1069 /// lowering. It returns MVT::iAny if SelectionDAG should be responsible for
1072 X86TargetLowering::getOptimalMemOpType(uint64_t Size, unsigned Align,
1073 bool isSrcConst, bool isSrcStr,
1074 SelectionDAG &DAG) const {
1075 // FIXME: This turns off use of xmm stores for memset/memcpy on targets like
1076 // linux. This is because the stack realignment code can't handle certain
1077 // cases like PR2962. This should be removed when PR2962 is fixed.
1078 const Function *F = DAG.getMachineFunction().getFunction();
1079 bool NoImplicitFloatOps = F->hasFnAttr(Attribute::NoImplicitFloat);
1080 if (!NoImplicitFloatOps && Subtarget->getStackAlignment() >= 16) {
1081 if ((isSrcConst || isSrcStr) && Subtarget->hasSSE2() && Size >= 16)
1083 if ((isSrcConst || isSrcStr) && Subtarget->hasSSE1() && Size >= 16)
1086 if (Subtarget->is64Bit() && Size >= 8)
1091 /// getJumpTableEncoding - Return the entry encoding for a jump table in the
1092 /// current function. The returned value is a member of the
1093 /// MachineJumpTableInfo::JTEntryKind enum.
1094 unsigned X86TargetLowering::getJumpTableEncoding() const {
1095 // In GOT pic mode, each entry in the jump table is emitted as a @GOTOFF
1097 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1098 Subtarget->isPICStyleGOT())
1099 return MachineJumpTableInfo::EK_Custom32;
1101 // Otherwise, use the normal jump table encoding heuristics.
1102 return TargetLowering::getJumpTableEncoding();
1105 /// getPICBaseSymbol - Return the X86-32 PIC base.
1107 X86TargetLowering::getPICBaseSymbol(const MachineFunction *MF,
1108 MCContext &Ctx) const {
1109 const MCAsmInfo &MAI = *getTargetMachine().getMCAsmInfo();
1110 return Ctx.GetOrCreateTemporarySymbol(Twine(MAI.getPrivateGlobalPrefix())+
1111 Twine(MF->getFunctionNumber())+"$pb");
1116 X86TargetLowering::LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI,
1117 const MachineBasicBlock *MBB,
1118 unsigned uid,MCContext &Ctx) const{
1119 assert(getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1120 Subtarget->isPICStyleGOT());
1121 // In 32-bit ELF systems, our jump table entries are formed with @GOTOFF
1123 return X86MCTargetExpr::Create(MBB->getSymbol(),
1124 X86MCTargetExpr::GOTOFF, Ctx);
1127 /// getPICJumpTableRelocaBase - Returns relocation base for the given PIC
1129 SDValue X86TargetLowering::getPICJumpTableRelocBase(SDValue Table,
1130 SelectionDAG &DAG) const {
1131 if (!Subtarget->is64Bit())
1132 // This doesn't have DebugLoc associated with it, but is not really the
1133 // same as a Register.
1134 return DAG.getNode(X86ISD::GlobalBaseReg, DebugLoc::getUnknownLoc(),
1139 /// getPICJumpTableRelocBaseExpr - This returns the relocation base for the
1140 /// given PIC jumptable, the same as getPICJumpTableRelocBase, but as an
1142 const MCExpr *X86TargetLowering::
1143 getPICJumpTableRelocBaseExpr(const MachineFunction *MF, unsigned JTI,
1144 MCContext &Ctx) const {
1145 // X86-64 uses RIP relative addressing based on the jump table label.
1146 if (Subtarget->isPICStyleRIPRel())
1147 return TargetLowering::getPICJumpTableRelocBaseExpr(MF, JTI, Ctx);
1149 // Otherwise, the reference is relative to the PIC base.
1150 return MCSymbolRefExpr::Create(getPICBaseSymbol(MF, Ctx), Ctx);
1153 /// getFunctionAlignment - Return the Log2 alignment of this function.
1154 unsigned X86TargetLowering::getFunctionAlignment(const Function *F) const {
1155 return F->hasFnAttr(Attribute::OptimizeForSize) ? 0 : 4;
1158 //===----------------------------------------------------------------------===//
1159 // Return Value Calling Convention Implementation
1160 //===----------------------------------------------------------------------===//
1162 #include "X86GenCallingConv.inc"
1165 X86TargetLowering::CanLowerReturn(CallingConv::ID CallConv, bool isVarArg,
1166 const SmallVectorImpl<EVT> &OutTys,
1167 const SmallVectorImpl<ISD::ArgFlagsTy> &ArgsFlags,
1168 SelectionDAG &DAG) {
1169 SmallVector<CCValAssign, 16> RVLocs;
1170 CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
1171 RVLocs, *DAG.getContext());
1172 return CCInfo.CheckReturn(OutTys, ArgsFlags, RetCC_X86);
1176 X86TargetLowering::LowerReturn(SDValue Chain,
1177 CallingConv::ID CallConv, bool isVarArg,
1178 const SmallVectorImpl<ISD::OutputArg> &Outs,
1179 DebugLoc dl, SelectionDAG &DAG) {
1181 SmallVector<CCValAssign, 16> RVLocs;
1182 CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
1183 RVLocs, *DAG.getContext());
1184 CCInfo.AnalyzeReturn(Outs, RetCC_X86);
1186 // Add the regs to the liveout set for the function.
1187 MachineRegisterInfo &MRI = DAG.getMachineFunction().getRegInfo();
1188 for (unsigned i = 0; i != RVLocs.size(); ++i)
1189 if (RVLocs[i].isRegLoc() && !MRI.isLiveOut(RVLocs[i].getLocReg()))
1190 MRI.addLiveOut(RVLocs[i].getLocReg());
1194 SmallVector<SDValue, 6> RetOps;
1195 RetOps.push_back(Chain); // Operand #0 = Chain (updated below)
1196 // Operand #1 = Bytes To Pop
1197 RetOps.push_back(DAG.getTargetConstant(getBytesToPopOnReturn(), MVT::i16));
1199 // Copy the result values into the output registers.
1200 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1201 CCValAssign &VA = RVLocs[i];
1202 assert(VA.isRegLoc() && "Can only return in registers!");
1203 SDValue ValToCopy = Outs[i].Val;
1205 // Returns in ST0/ST1 are handled specially: these are pushed as operands to
1206 // the RET instruction and handled by the FP Stackifier.
1207 if (VA.getLocReg() == X86::ST0 ||
1208 VA.getLocReg() == X86::ST1) {
1209 // If this is a copy from an xmm register to ST(0), use an FPExtend to
1210 // change the value to the FP stack register class.
1211 if (isScalarFPTypeInSSEReg(VA.getValVT()))
1212 ValToCopy = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f80, ValToCopy);
1213 RetOps.push_back(ValToCopy);
1214 // Don't emit a copytoreg.
1218 // 64-bit vector (MMX) values are returned in XMM0 / XMM1 except for v1i64
1219 // which is returned in RAX / RDX.
1220 if (Subtarget->is64Bit()) {
1221 EVT ValVT = ValToCopy.getValueType();
1222 if (ValVT.isVector() && ValVT.getSizeInBits() == 64) {
1223 ValToCopy = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i64, ValToCopy);
1224 if (VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1)
1225 ValToCopy = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, ValToCopy);
1229 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), ValToCopy, Flag);
1230 Flag = Chain.getValue(1);
1233 // The x86-64 ABI for returning structs by value requires that we copy
1234 // the sret argument into %rax for the return. We saved the argument into
1235 // a virtual register in the entry block, so now we copy the value out
1237 if (Subtarget->is64Bit() &&
1238 DAG.getMachineFunction().getFunction()->hasStructRetAttr()) {
1239 MachineFunction &MF = DAG.getMachineFunction();
1240 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1241 unsigned Reg = FuncInfo->getSRetReturnReg();
1243 Reg = MRI.createVirtualRegister(getRegClassFor(MVT::i64));
1244 FuncInfo->setSRetReturnReg(Reg);
1246 SDValue Val = DAG.getCopyFromReg(Chain, dl, Reg, getPointerTy());
1248 Chain = DAG.getCopyToReg(Chain, dl, X86::RAX, Val, Flag);
1249 Flag = Chain.getValue(1);
1251 // RAX now acts like a return value.
1252 MRI.addLiveOut(X86::RAX);
1255 RetOps[0] = Chain; // Update chain.
1257 // Add the flag if we have it.
1259 RetOps.push_back(Flag);
1261 return DAG.getNode(X86ISD::RET_FLAG, dl,
1262 MVT::Other, &RetOps[0], RetOps.size());
1265 /// LowerCallResult - Lower the result values of a call into the
1266 /// appropriate copies out of appropriate physical registers.
1269 X86TargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
1270 CallingConv::ID CallConv, bool isVarArg,
1271 const SmallVectorImpl<ISD::InputArg> &Ins,
1272 DebugLoc dl, SelectionDAG &DAG,
1273 SmallVectorImpl<SDValue> &InVals) {
1275 // Assign locations to each value returned by this call.
1276 SmallVector<CCValAssign, 16> RVLocs;
1277 bool Is64Bit = Subtarget->is64Bit();
1278 CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
1279 RVLocs, *DAG.getContext());
1280 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
1282 // Copy all of the result registers out of their specified physreg.
1283 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1284 CCValAssign &VA = RVLocs[i];
1285 EVT CopyVT = VA.getValVT();
1287 // If this is x86-64, and we disabled SSE, we can't return FP values
1288 if ((CopyVT == MVT::f32 || CopyVT == MVT::f64) &&
1289 ((Is64Bit || Ins[i].Flags.isInReg()) && !Subtarget->hasSSE1())) {
1290 llvm_report_error("SSE register return with SSE disabled");
1293 // If this is a call to a function that returns an fp value on the floating
1294 // point stack, but where we prefer to use the value in xmm registers, copy
1295 // it out as F80 and use a truncate to move it from fp stack reg to xmm reg.
1296 if ((VA.getLocReg() == X86::ST0 ||
1297 VA.getLocReg() == X86::ST1) &&
1298 isScalarFPTypeInSSEReg(VA.getValVT())) {
1303 if (Is64Bit && CopyVT.isVector() && CopyVT.getSizeInBits() == 64) {
1304 // For x86-64, MMX values are returned in XMM0 / XMM1 except for v1i64.
1305 if (VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) {
1306 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(),
1307 MVT::v2i64, InFlag).getValue(1);
1308 Val = Chain.getValue(0);
1309 Val = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i64,
1310 Val, DAG.getConstant(0, MVT::i64));
1312 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(),
1313 MVT::i64, InFlag).getValue(1);
1314 Val = Chain.getValue(0);
1316 Val = DAG.getNode(ISD::BIT_CONVERT, dl, CopyVT, Val);
1318 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(),
1319 CopyVT, InFlag).getValue(1);
1320 Val = Chain.getValue(0);
1322 InFlag = Chain.getValue(2);
1324 if (CopyVT != VA.getValVT()) {
1325 // Round the F80 the right size, which also moves to the appropriate xmm
1327 Val = DAG.getNode(ISD::FP_ROUND, dl, VA.getValVT(), Val,
1328 // This truncation won't change the value.
1329 DAG.getIntPtrConstant(1));
1332 InVals.push_back(Val);
1339 //===----------------------------------------------------------------------===//
1340 // C & StdCall & Fast Calling Convention implementation
1341 //===----------------------------------------------------------------------===//
1342 // StdCall calling convention seems to be standard for many Windows' API
1343 // routines and around. It differs from C calling convention just a little:
1344 // callee should clean up the stack, not caller. Symbols should be also
1345 // decorated in some fancy way :) It doesn't support any vector arguments.
1346 // For info on fast calling convention see Fast Calling Convention (tail call)
1347 // implementation LowerX86_32FastCCCallTo.
1349 /// CallIsStructReturn - Determines whether a call uses struct return
1351 static bool CallIsStructReturn(const SmallVectorImpl<ISD::OutputArg> &Outs) {
1355 return Outs[0].Flags.isSRet();
1358 /// ArgsAreStructReturn - Determines whether a function uses struct
1359 /// return semantics.
1361 ArgsAreStructReturn(const SmallVectorImpl<ISD::InputArg> &Ins) {
1365 return Ins[0].Flags.isSRet();
1368 /// IsCalleePop - Determines whether the callee is required to pop its
1369 /// own arguments. Callee pop is necessary to support tail calls.
1370 bool X86TargetLowering::IsCalleePop(bool IsVarArg, CallingConv::ID CallingConv){
1374 switch (CallingConv) {
1377 case CallingConv::X86_StdCall:
1378 return !Subtarget->is64Bit();
1379 case CallingConv::X86_FastCall:
1380 return !Subtarget->is64Bit();
1381 case CallingConv::Fast:
1382 return GuaranteedTailCallOpt;
1383 case CallingConv::GHC:
1384 return GuaranteedTailCallOpt;
1388 /// CCAssignFnForNode - Selects the correct CCAssignFn for a the
1389 /// given CallingConvention value.
1390 CCAssignFn *X86TargetLowering::CCAssignFnForNode(CallingConv::ID CC) const {
1391 if (Subtarget->is64Bit()) {
1392 if (CC == CallingConv::GHC)
1393 return CC_X86_64_GHC;
1394 else if (Subtarget->isTargetWin64())
1395 return CC_X86_Win64_C;
1400 if (CC == CallingConv::X86_FastCall)
1401 return CC_X86_32_FastCall;
1402 else if (CC == CallingConv::Fast)
1403 return CC_X86_32_FastCC;
1404 else if (CC == CallingConv::GHC)
1405 return CC_X86_32_GHC;
1410 /// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified
1411 /// by "Src" to address "Dst" with size and alignment information specified by
1412 /// the specific parameter attribute. The copy will be passed as a byval
1413 /// function parameter.
1415 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
1416 ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
1418 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32);
1419 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
1420 /*AlwaysInline=*/true, NULL, 0, NULL, 0);
1423 /// IsTailCallConvention - Return true if the calling convention is one that
1424 /// supports tail call optimization.
1425 static bool IsTailCallConvention(CallingConv::ID CC) {
1426 return (CC == CallingConv::Fast || CC == CallingConv::GHC);
1429 /// FuncIsMadeTailCallSafe - Return true if the function is being made into
1430 /// a tailcall target by changing its ABI.
1431 static bool FuncIsMadeTailCallSafe(CallingConv::ID CC) {
1432 return GuaranteedTailCallOpt && IsTailCallConvention(CC);
1436 X86TargetLowering::LowerMemArgument(SDValue Chain,
1437 CallingConv::ID CallConv,
1438 const SmallVectorImpl<ISD::InputArg> &Ins,
1439 DebugLoc dl, SelectionDAG &DAG,
1440 const CCValAssign &VA,
1441 MachineFrameInfo *MFI,
1443 // Create the nodes corresponding to a load from this parameter slot.
1444 ISD::ArgFlagsTy Flags = Ins[i].Flags;
1445 bool AlwaysUseMutable = FuncIsMadeTailCallSafe(CallConv);
1446 bool isImmutable = !AlwaysUseMutable && !Flags.isByVal();
1449 // If value is passed by pointer we have address passed instead of the value
1451 if (VA.getLocInfo() == CCValAssign::Indirect)
1452 ValVT = VA.getLocVT();
1454 ValVT = VA.getValVT();
1456 // FIXME: For now, all byval parameter objects are marked mutable. This can be
1457 // changed with more analysis.
1458 // In case of tail call optimization mark all arguments mutable. Since they
1459 // could be overwritten by lowering of arguments in case of a tail call.
1460 if (Flags.isByVal()) {
1461 int FI = MFI->CreateFixedObject(Flags.getByValSize(),
1462 VA.getLocMemOffset(), isImmutable, false);
1463 return DAG.getFrameIndex(FI, getPointerTy());
1465 int FI = MFI->CreateFixedObject(ValVT.getSizeInBits()/8,
1466 VA.getLocMemOffset(), isImmutable, false);
1467 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
1468 return DAG.getLoad(ValVT, dl, Chain, FIN,
1469 PseudoSourceValue::getFixedStack(FI), 0,
1475 X86TargetLowering::LowerFormalArguments(SDValue Chain,
1476 CallingConv::ID CallConv,
1478 const SmallVectorImpl<ISD::InputArg> &Ins,
1481 SmallVectorImpl<SDValue> &InVals) {
1482 MachineFunction &MF = DAG.getMachineFunction();
1483 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1485 const Function* Fn = MF.getFunction();
1486 if (Fn->hasExternalLinkage() &&
1487 Subtarget->isTargetCygMing() &&
1488 Fn->getName() == "main")
1489 FuncInfo->setForceFramePointer(true);
1491 MachineFrameInfo *MFI = MF.getFrameInfo();
1492 bool Is64Bit = Subtarget->is64Bit();
1493 bool IsWin64 = Subtarget->isTargetWin64();
1495 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
1496 "Var args not supported with calling convention fastcc or ghc");
1498 // Assign locations to all of the incoming arguments.
1499 SmallVector<CCValAssign, 16> ArgLocs;
1500 CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
1501 ArgLocs, *DAG.getContext());
1502 CCInfo.AnalyzeFormalArguments(Ins, CCAssignFnForNode(CallConv));
1504 unsigned LastVal = ~0U;
1506 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1507 CCValAssign &VA = ArgLocs[i];
1508 // TODO: If an arg is passed in two places (e.g. reg and stack), skip later
1510 assert(VA.getValNo() != LastVal &&
1511 "Don't support value assigned to multiple locs yet");
1512 LastVal = VA.getValNo();
1514 if (VA.isRegLoc()) {
1515 EVT RegVT = VA.getLocVT();
1516 TargetRegisterClass *RC = NULL;
1517 if (RegVT == MVT::i32)
1518 RC = X86::GR32RegisterClass;
1519 else if (Is64Bit && RegVT == MVT::i64)
1520 RC = X86::GR64RegisterClass;
1521 else if (RegVT == MVT::f32)
1522 RC = X86::FR32RegisterClass;
1523 else if (RegVT == MVT::f64)
1524 RC = X86::FR64RegisterClass;
1525 else if (RegVT.isVector() && RegVT.getSizeInBits() == 128)
1526 RC = X86::VR128RegisterClass;
1527 else if (RegVT.isVector() && RegVT.getSizeInBits() == 64)
1528 RC = X86::VR64RegisterClass;
1530 llvm_unreachable("Unknown argument type!");
1532 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
1533 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
1535 // If this is an 8 or 16-bit value, it is really passed promoted to 32
1536 // bits. Insert an assert[sz]ext to capture this, then truncate to the
1538 if (VA.getLocInfo() == CCValAssign::SExt)
1539 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
1540 DAG.getValueType(VA.getValVT()));
1541 else if (VA.getLocInfo() == CCValAssign::ZExt)
1542 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
1543 DAG.getValueType(VA.getValVT()));
1544 else if (VA.getLocInfo() == CCValAssign::BCvt)
1545 ArgValue = DAG.getNode(ISD::BIT_CONVERT, dl, VA.getValVT(), ArgValue);
1547 if (VA.isExtInLoc()) {
1548 // Handle MMX values passed in XMM regs.
1549 if (RegVT.isVector()) {
1550 ArgValue = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i64,
1551 ArgValue, DAG.getConstant(0, MVT::i64));
1552 ArgValue = DAG.getNode(ISD::BIT_CONVERT, dl, VA.getValVT(), ArgValue);
1554 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
1557 assert(VA.isMemLoc());
1558 ArgValue = LowerMemArgument(Chain, CallConv, Ins, dl, DAG, VA, MFI, i);
1561 // If value is passed via pointer - do a load.
1562 if (VA.getLocInfo() == CCValAssign::Indirect)
1563 ArgValue = DAG.getLoad(VA.getValVT(), dl, Chain, ArgValue, NULL, 0,
1566 InVals.push_back(ArgValue);
1569 // The x86-64 ABI for returning structs by value requires that we copy
1570 // the sret argument into %rax for the return. Save the argument into
1571 // a virtual register so that we can access it from the return points.
1572 if (Is64Bit && MF.getFunction()->hasStructRetAttr()) {
1573 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1574 unsigned Reg = FuncInfo->getSRetReturnReg();
1576 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(MVT::i64));
1577 FuncInfo->setSRetReturnReg(Reg);
1579 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, InVals[0]);
1580 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain);
1583 unsigned StackSize = CCInfo.getNextStackOffset();
1584 // Align stack specially for tail calls.
1585 if (FuncIsMadeTailCallSafe(CallConv))
1586 StackSize = GetAlignedArgumentStackSize(StackSize, DAG);
1588 // If the function takes variable number of arguments, make a frame index for
1589 // the start of the first vararg value... for expansion of llvm.va_start.
1591 if (Is64Bit || CallConv != CallingConv::X86_FastCall) {
1592 VarArgsFrameIndex = MFI->CreateFixedObject(1, StackSize, true, false);
1595 unsigned TotalNumIntRegs = 0, TotalNumXMMRegs = 0;
1597 // FIXME: We should really autogenerate these arrays
1598 static const unsigned GPR64ArgRegsWin64[] = {
1599 X86::RCX, X86::RDX, X86::R8, X86::R9
1601 static const unsigned XMMArgRegsWin64[] = {
1602 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3
1604 static const unsigned GPR64ArgRegs64Bit[] = {
1605 X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9
1607 static const unsigned XMMArgRegs64Bit[] = {
1608 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
1609 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
1611 const unsigned *GPR64ArgRegs, *XMMArgRegs;
1614 TotalNumIntRegs = 4; TotalNumXMMRegs = 4;
1615 GPR64ArgRegs = GPR64ArgRegsWin64;
1616 XMMArgRegs = XMMArgRegsWin64;
1618 TotalNumIntRegs = 6; TotalNumXMMRegs = 8;
1619 GPR64ArgRegs = GPR64ArgRegs64Bit;
1620 XMMArgRegs = XMMArgRegs64Bit;
1622 unsigned NumIntRegs = CCInfo.getFirstUnallocated(GPR64ArgRegs,
1624 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs,
1627 bool NoImplicitFloatOps = Fn->hasFnAttr(Attribute::NoImplicitFloat);
1628 assert(!(NumXMMRegs && !Subtarget->hasSSE1()) &&
1629 "SSE register cannot be used when SSE is disabled!");
1630 assert(!(NumXMMRegs && UseSoftFloat && NoImplicitFloatOps) &&
1631 "SSE register cannot be used when SSE is disabled!");
1632 if (UseSoftFloat || NoImplicitFloatOps || !Subtarget->hasSSE1())
1633 // Kernel mode asks for SSE to be disabled, so don't push them
1635 TotalNumXMMRegs = 0;
1637 // For X86-64, if there are vararg parameters that are passed via
1638 // registers, then we must store them to their spots on the stack so they
1639 // may be loaded by deferencing the result of va_next.
1640 VarArgsGPOffset = NumIntRegs * 8;
1641 VarArgsFPOffset = TotalNumIntRegs * 8 + NumXMMRegs * 16;
1642 RegSaveFrameIndex = MFI->CreateStackObject(TotalNumIntRegs * 8 +
1643 TotalNumXMMRegs * 16, 16,
1646 // Store the integer parameter registers.
1647 SmallVector<SDValue, 8> MemOps;
1648 SDValue RSFIN = DAG.getFrameIndex(RegSaveFrameIndex, getPointerTy());
1649 unsigned Offset = VarArgsGPOffset;
1650 for (; NumIntRegs != TotalNumIntRegs; ++NumIntRegs) {
1651 SDValue FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), RSFIN,
1652 DAG.getIntPtrConstant(Offset));
1653 unsigned VReg = MF.addLiveIn(GPR64ArgRegs[NumIntRegs],
1654 X86::GR64RegisterClass);
1655 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64);
1657 DAG.getStore(Val.getValue(1), dl, Val, FIN,
1658 PseudoSourceValue::getFixedStack(RegSaveFrameIndex),
1659 Offset, false, false, 0);
1660 MemOps.push_back(Store);
1664 if (TotalNumXMMRegs != 0 && NumXMMRegs != TotalNumXMMRegs) {
1665 // Now store the XMM (fp + vector) parameter registers.
1666 SmallVector<SDValue, 11> SaveXMMOps;
1667 SaveXMMOps.push_back(Chain);
1669 unsigned AL = MF.addLiveIn(X86::AL, X86::GR8RegisterClass);
1670 SDValue ALVal = DAG.getCopyFromReg(DAG.getEntryNode(), dl, AL, MVT::i8);
1671 SaveXMMOps.push_back(ALVal);
1673 SaveXMMOps.push_back(DAG.getIntPtrConstant(RegSaveFrameIndex));
1674 SaveXMMOps.push_back(DAG.getIntPtrConstant(VarArgsFPOffset));
1676 for (; NumXMMRegs != TotalNumXMMRegs; ++NumXMMRegs) {
1677 unsigned VReg = MF.addLiveIn(XMMArgRegs[NumXMMRegs],
1678 X86::VR128RegisterClass);
1679 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::v4f32);
1680 SaveXMMOps.push_back(Val);
1682 MemOps.push_back(DAG.getNode(X86ISD::VASTART_SAVE_XMM_REGS, dl,
1684 &SaveXMMOps[0], SaveXMMOps.size()));
1687 if (!MemOps.empty())
1688 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
1689 &MemOps[0], MemOps.size());
1693 // Some CCs need callee pop.
1694 if (IsCalleePop(isVarArg, CallConv)) {
1695 BytesToPopOnReturn = StackSize; // Callee pops everything.
1697 BytesToPopOnReturn = 0; // Callee pops nothing.
1698 // If this is an sret function, the return should pop the hidden pointer.
1699 if (!Is64Bit && !IsTailCallConvention(CallConv) && ArgsAreStructReturn(Ins))
1700 BytesToPopOnReturn = 4;
1704 RegSaveFrameIndex = 0xAAAAAAA; // RegSaveFrameIndex is X86-64 only.
1705 if (CallConv == CallingConv::X86_FastCall)
1706 VarArgsFrameIndex = 0xAAAAAAA; // fastcc functions can't have varargs.
1709 FuncInfo->setBytesToPopOnReturn(BytesToPopOnReturn);
1715 X86TargetLowering::LowerMemOpCallTo(SDValue Chain,
1716 SDValue StackPtr, SDValue Arg,
1717 DebugLoc dl, SelectionDAG &DAG,
1718 const CCValAssign &VA,
1719 ISD::ArgFlagsTy Flags) {
1720 const unsigned FirstStackArgOffset = (Subtarget->isTargetWin64() ? 32 : 0);
1721 unsigned LocMemOffset = FirstStackArgOffset + VA.getLocMemOffset();
1722 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
1723 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
1724 if (Flags.isByVal()) {
1725 return CreateCopyOfByValArgument(Arg, PtrOff, Chain, Flags, DAG, dl);
1727 return DAG.getStore(Chain, dl, Arg, PtrOff,
1728 PseudoSourceValue::getStack(), LocMemOffset,
1732 /// EmitTailCallLoadRetAddr - Emit a load of return address if tail call
1733 /// optimization is performed and it is required.
1735 X86TargetLowering::EmitTailCallLoadRetAddr(SelectionDAG &DAG,
1736 SDValue &OutRetAddr, SDValue Chain,
1737 bool IsTailCall, bool Is64Bit,
1738 int FPDiff, DebugLoc dl) {
1739 // Adjust the Return address stack slot.
1740 EVT VT = getPointerTy();
1741 OutRetAddr = getReturnAddressFrameIndex(DAG);
1743 // Load the "old" Return address.
1744 OutRetAddr = DAG.getLoad(VT, dl, Chain, OutRetAddr, NULL, 0, false, false, 0);
1745 return SDValue(OutRetAddr.getNode(), 1);
1748 /// EmitTailCallStoreRetAddr - Emit a store of the return adress if tail call
1749 /// optimization is performed and it is required (FPDiff!=0).
1751 EmitTailCallStoreRetAddr(SelectionDAG & DAG, MachineFunction &MF,
1752 SDValue Chain, SDValue RetAddrFrIdx,
1753 bool Is64Bit, int FPDiff, DebugLoc dl) {
1754 // Store the return address to the appropriate stack slot.
1755 if (!FPDiff) return Chain;
1756 // Calculate the new stack slot for the return address.
1757 int SlotSize = Is64Bit ? 8 : 4;
1758 int NewReturnAddrFI =
1759 MF.getFrameInfo()->CreateFixedObject(SlotSize, FPDiff-SlotSize, false, false);
1760 EVT VT = Is64Bit ? MVT::i64 : MVT::i32;
1761 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewReturnAddrFI, VT);
1762 Chain = DAG.getStore(Chain, dl, RetAddrFrIdx, NewRetAddrFrIdx,
1763 PseudoSourceValue::getFixedStack(NewReturnAddrFI), 0,
1769 X86TargetLowering::LowerCall(SDValue Chain, SDValue Callee,
1770 CallingConv::ID CallConv, bool isVarArg,
1772 const SmallVectorImpl<ISD::OutputArg> &Outs,
1773 const SmallVectorImpl<ISD::InputArg> &Ins,
1774 DebugLoc dl, SelectionDAG &DAG,
1775 SmallVectorImpl<SDValue> &InVals) {
1776 MachineFunction &MF = DAG.getMachineFunction();
1777 bool Is64Bit = Subtarget->is64Bit();
1778 bool IsStructRet = CallIsStructReturn(Outs);
1779 bool IsSibcall = false;
1782 // Check if it's really possible to do a tail call.
1783 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv,
1784 isVarArg, IsStructRet, MF.getFunction()->hasStructRetAttr(),
1787 // Sibcalls are automatically detected tailcalls which do not require
1789 if (!GuaranteedTailCallOpt && isTailCall)
1796 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
1797 "Var args not supported with calling convention fastcc or ghc");
1799 // Analyze operands of the call, assigning locations to each operand.
1800 SmallVector<CCValAssign, 16> ArgLocs;
1801 CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
1802 ArgLocs, *DAG.getContext());
1803 CCInfo.AnalyzeCallOperands(Outs, CCAssignFnForNode(CallConv));
1805 // Get a count of how many bytes are to be pushed on the stack.
1806 unsigned NumBytes = CCInfo.getNextStackOffset();
1808 // This is a sibcall. The memory operands are available in caller's
1809 // own caller's stack.
1811 else if (GuaranteedTailCallOpt && IsTailCallConvention(CallConv))
1812 NumBytes = GetAlignedArgumentStackSize(NumBytes, DAG);
1815 if (isTailCall && !IsSibcall) {
1816 // Lower arguments at fp - stackoffset + fpdiff.
1817 unsigned NumBytesCallerPushed =
1818 MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn();
1819 FPDiff = NumBytesCallerPushed - NumBytes;
1821 // Set the delta of movement of the returnaddr stackslot.
1822 // But only set if delta is greater than previous delta.
1823 if (FPDiff < (MF.getInfo<X86MachineFunctionInfo>()->getTCReturnAddrDelta()))
1824 MF.getInfo<X86MachineFunctionInfo>()->setTCReturnAddrDelta(FPDiff);
1828 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true));
1830 SDValue RetAddrFrIdx;
1831 // Load return adress for tail calls.
1832 if (isTailCall && FPDiff)
1833 Chain = EmitTailCallLoadRetAddr(DAG, RetAddrFrIdx, Chain, isTailCall,
1834 Is64Bit, FPDiff, dl);
1836 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
1837 SmallVector<SDValue, 8> MemOpChains;
1840 // Walk the register/memloc assignments, inserting copies/loads. In the case
1841 // of tail call optimization arguments are handle later.
1842 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1843 CCValAssign &VA = ArgLocs[i];
1844 EVT RegVT = VA.getLocVT();
1845 SDValue Arg = Outs[i].Val;
1846 ISD::ArgFlagsTy Flags = Outs[i].Flags;
1847 bool isByVal = Flags.isByVal();
1849 // Promote the value if needed.
1850 switch (VA.getLocInfo()) {
1851 default: llvm_unreachable("Unknown loc info!");
1852 case CCValAssign::Full: break;
1853 case CCValAssign::SExt:
1854 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, RegVT, Arg);
1856 case CCValAssign::ZExt:
1857 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, RegVT, Arg);
1859 case CCValAssign::AExt:
1860 if (RegVT.isVector() && RegVT.getSizeInBits() == 128) {
1861 // Special case: passing MMX values in XMM registers.
1862 Arg = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i64, Arg);
1863 Arg = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, Arg);
1864 Arg = getMOVL(DAG, dl, MVT::v2i64, DAG.getUNDEF(MVT::v2i64), Arg);
1866 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, RegVT, Arg);
1868 case CCValAssign::BCvt:
1869 Arg = DAG.getNode(ISD::BIT_CONVERT, dl, RegVT, Arg);
1871 case CCValAssign::Indirect: {
1872 // Store the argument.
1873 SDValue SpillSlot = DAG.CreateStackTemporary(VA.getValVT());
1874 int FI = cast<FrameIndexSDNode>(SpillSlot)->getIndex();
1875 Chain = DAG.getStore(Chain, dl, Arg, SpillSlot,
1876 PseudoSourceValue::getFixedStack(FI), 0,
1883 if (VA.isRegLoc()) {
1884 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
1885 } else if (!IsSibcall && (!isTailCall || isByVal)) {
1886 assert(VA.isMemLoc());
1887 if (StackPtr.getNode() == 0)
1888 StackPtr = DAG.getCopyFromReg(Chain, dl, X86StackPtr, getPointerTy());
1889 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Arg,
1890 dl, DAG, VA, Flags));
1894 if (!MemOpChains.empty())
1895 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
1896 &MemOpChains[0], MemOpChains.size());
1898 // Build a sequence of copy-to-reg nodes chained together with token chain
1899 // and flag operands which copy the outgoing args into registers.
1901 // Tail call byval lowering might overwrite argument registers so in case of
1902 // tail call optimization the copies to registers are lowered later.
1904 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
1905 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
1906 RegsToPass[i].second, InFlag);
1907 InFlag = Chain.getValue(1);
1910 if (Subtarget->isPICStyleGOT()) {
1911 // ELF / PIC requires GOT in the EBX register before function calls via PLT
1914 Chain = DAG.getCopyToReg(Chain, dl, X86::EBX,
1915 DAG.getNode(X86ISD::GlobalBaseReg,
1916 DebugLoc::getUnknownLoc(),
1919 InFlag = Chain.getValue(1);
1921 // If we are tail calling and generating PIC/GOT style code load the
1922 // address of the callee into ECX. The value in ecx is used as target of
1923 // the tail jump. This is done to circumvent the ebx/callee-saved problem
1924 // for tail calls on PIC/GOT architectures. Normally we would just put the
1925 // address of GOT into ebx and then call target@PLT. But for tail calls
1926 // ebx would be restored (since ebx is callee saved) before jumping to the
1929 // Note: The actual moving to ECX is done further down.
1930 GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee);
1931 if (G && !G->getGlobal()->hasHiddenVisibility() &&
1932 !G->getGlobal()->hasProtectedVisibility())
1933 Callee = LowerGlobalAddress(Callee, DAG);
1934 else if (isa<ExternalSymbolSDNode>(Callee))
1935 Callee = LowerExternalSymbol(Callee, DAG);
1939 if (Is64Bit && isVarArg) {
1940 // From AMD64 ABI document:
1941 // For calls that may call functions that use varargs or stdargs
1942 // (prototype-less calls or calls to functions containing ellipsis (...) in
1943 // the declaration) %al is used as hidden argument to specify the number
1944 // of SSE registers used. The contents of %al do not need to match exactly
1945 // the number of registers, but must be an ubound on the number of SSE
1946 // registers used and is in the range 0 - 8 inclusive.
1948 // FIXME: Verify this on Win64
1949 // Count the number of XMM registers allocated.
1950 static const unsigned XMMArgRegs[] = {
1951 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
1952 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
1954 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs, 8);
1955 assert((Subtarget->hasSSE1() || !NumXMMRegs)
1956 && "SSE registers cannot be used when SSE is disabled");
1958 Chain = DAG.getCopyToReg(Chain, dl, X86::AL,
1959 DAG.getConstant(NumXMMRegs, MVT::i8), InFlag);
1960 InFlag = Chain.getValue(1);
1964 // For tail calls lower the arguments to the 'real' stack slot.
1966 // Force all the incoming stack arguments to be loaded from the stack
1967 // before any new outgoing arguments are stored to the stack, because the
1968 // outgoing stack slots may alias the incoming argument stack slots, and
1969 // the alias isn't otherwise explicit. This is slightly more conservative
1970 // than necessary, because it means that each store effectively depends
1971 // on every argument instead of just those arguments it would clobber.
1972 SDValue ArgChain = DAG.getStackArgumentTokenFactor(Chain);
1974 SmallVector<SDValue, 8> MemOpChains2;
1977 // Do not flag preceeding copytoreg stuff together with the following stuff.
1979 if (GuaranteedTailCallOpt) {
1980 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1981 CCValAssign &VA = ArgLocs[i];
1984 assert(VA.isMemLoc());
1985 SDValue Arg = Outs[i].Val;
1986 ISD::ArgFlagsTy Flags = Outs[i].Flags;
1987 // Create frame index.
1988 int32_t Offset = VA.getLocMemOffset()+FPDiff;
1989 uint32_t OpSize = (VA.getLocVT().getSizeInBits()+7)/8;
1990 FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true, false);
1991 FIN = DAG.getFrameIndex(FI, getPointerTy());
1993 if (Flags.isByVal()) {
1994 // Copy relative to framepointer.
1995 SDValue Source = DAG.getIntPtrConstant(VA.getLocMemOffset());
1996 if (StackPtr.getNode() == 0)
1997 StackPtr = DAG.getCopyFromReg(Chain, dl, X86StackPtr,
1999 Source = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, Source);
2001 MemOpChains2.push_back(CreateCopyOfByValArgument(Source, FIN,
2005 // Store relative to framepointer.
2006 MemOpChains2.push_back(
2007 DAG.getStore(ArgChain, dl, Arg, FIN,
2008 PseudoSourceValue::getFixedStack(FI), 0,
2014 if (!MemOpChains2.empty())
2015 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
2016 &MemOpChains2[0], MemOpChains2.size());
2018 // Copy arguments to their registers.
2019 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
2020 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
2021 RegsToPass[i].second, InFlag);
2022 InFlag = Chain.getValue(1);
2026 // Store the return address to the appropriate stack slot.
2027 Chain = EmitTailCallStoreRetAddr(DAG, MF, Chain, RetAddrFrIdx, Is64Bit,
2031 bool WasGlobalOrExternal = false;
2032 if (getTargetMachine().getCodeModel() == CodeModel::Large) {
2033 assert(Is64Bit && "Large code model is only legal in 64-bit mode.");
2034 // In the 64-bit large code model, we have to make all calls
2035 // through a register, since the call instruction's 32-bit
2036 // pc-relative offset may not be large enough to hold the whole
2038 } else if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
2039 WasGlobalOrExternal = true;
2040 // If the callee is a GlobalAddress node (quite common, every direct call
2041 // is) turn it into a TargetGlobalAddress node so that legalize doesn't hack
2044 // We should use extra load for direct calls to dllimported functions in
2046 GlobalValue *GV = G->getGlobal();
2047 if (!GV->hasDLLImportLinkage()) {
2048 unsigned char OpFlags = 0;
2050 // On ELF targets, in both X86-64 and X86-32 mode, direct calls to
2051 // external symbols most go through the PLT in PIC mode. If the symbol
2052 // has hidden or protected visibility, or if it is static or local, then
2053 // we don't need to use the PLT - we can directly call it.
2054 if (Subtarget->isTargetELF() &&
2055 getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
2056 GV->hasDefaultVisibility() && !GV->hasLocalLinkage()) {
2057 OpFlags = X86II::MO_PLT;
2058 } else if (Subtarget->isPICStyleStubAny() &&
2059 (GV->isDeclaration() || GV->isWeakForLinker()) &&
2060 Subtarget->getDarwinVers() < 9) {
2061 // PC-relative references to external symbols should go through $stub,
2062 // unless we're building with the leopard linker or later, which
2063 // automatically synthesizes these stubs.
2064 OpFlags = X86II::MO_DARWIN_STUB;
2067 Callee = DAG.getTargetGlobalAddress(GV, getPointerTy(),
2068 G->getOffset(), OpFlags);
2070 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
2071 WasGlobalOrExternal = true;
2072 unsigned char OpFlags = 0;
2074 // On ELF targets, in either X86-64 or X86-32 mode, direct calls to external
2075 // symbols should go through the PLT.
2076 if (Subtarget->isTargetELF() &&
2077 getTargetMachine().getRelocationModel() == Reloc::PIC_) {
2078 OpFlags = X86II::MO_PLT;
2079 } else if (Subtarget->isPICStyleStubAny() &&
2080 Subtarget->getDarwinVers() < 9) {
2081 // PC-relative references to external symbols should go through $stub,
2082 // unless we're building with the leopard linker or later, which
2083 // automatically synthesizes these stubs.
2084 OpFlags = X86II::MO_DARWIN_STUB;
2087 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy(),
2091 // Returns a chain & a flag for retval copy to use.
2092 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
2093 SmallVector<SDValue, 8> Ops;
2095 if (!IsSibcall && isTailCall) {
2096 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
2097 DAG.getIntPtrConstant(0, true), InFlag);
2098 InFlag = Chain.getValue(1);
2101 Ops.push_back(Chain);
2102 Ops.push_back(Callee);
2105 Ops.push_back(DAG.getConstant(FPDiff, MVT::i32));
2107 // Add argument registers to the end of the list so that they are known live
2109 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
2110 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
2111 RegsToPass[i].second.getValueType()));
2113 // Add an implicit use GOT pointer in EBX.
2114 if (!isTailCall && Subtarget->isPICStyleGOT())
2115 Ops.push_back(DAG.getRegister(X86::EBX, getPointerTy()));
2117 // Add an implicit use of AL for x86 vararg functions.
2118 if (Is64Bit && isVarArg)
2119 Ops.push_back(DAG.getRegister(X86::AL, MVT::i8));
2121 if (InFlag.getNode())
2122 Ops.push_back(InFlag);
2125 // If this is the first return lowered for this function, add the regs
2126 // to the liveout set for the function.
2127 if (MF.getRegInfo().liveout_empty()) {
2128 SmallVector<CCValAssign, 16> RVLocs;
2129 CCState CCInfo(CallConv, isVarArg, getTargetMachine(), RVLocs,
2131 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
2132 for (unsigned i = 0; i != RVLocs.size(); ++i)
2133 if (RVLocs[i].isRegLoc())
2134 MF.getRegInfo().addLiveOut(RVLocs[i].getLocReg());
2136 return DAG.getNode(X86ISD::TC_RETURN, dl,
2137 NodeTys, &Ops[0], Ops.size());
2140 Chain = DAG.getNode(X86ISD::CALL, dl, NodeTys, &Ops[0], Ops.size());
2141 InFlag = Chain.getValue(1);
2143 // Create the CALLSEQ_END node.
2144 unsigned NumBytesForCalleeToPush;
2145 if (IsCalleePop(isVarArg, CallConv))
2146 NumBytesForCalleeToPush = NumBytes; // Callee pops everything
2147 else if (!Is64Bit && !IsTailCallConvention(CallConv) && IsStructRet)
2148 // If this is a call to a struct-return function, the callee
2149 // pops the hidden struct pointer, so we have to push it back.
2150 // This is common for Darwin/X86, Linux & Mingw32 targets.
2151 NumBytesForCalleeToPush = 4;
2153 NumBytesForCalleeToPush = 0; // Callee pops nothing.
2155 // Returns a flag for retval copy to use.
2157 Chain = DAG.getCALLSEQ_END(Chain,
2158 DAG.getIntPtrConstant(NumBytes, true),
2159 DAG.getIntPtrConstant(NumBytesForCalleeToPush,
2162 InFlag = Chain.getValue(1);
2165 // Handle result values, copying them out of physregs into vregs that we
2167 return LowerCallResult(Chain, InFlag, CallConv, isVarArg,
2168 Ins, dl, DAG, InVals);
2172 //===----------------------------------------------------------------------===//
2173 // Fast Calling Convention (tail call) implementation
2174 //===----------------------------------------------------------------------===//
2176 // Like std call, callee cleans arguments, convention except that ECX is
2177 // reserved for storing the tail called function address. Only 2 registers are
2178 // free for argument passing (inreg). Tail call optimization is performed
2180 // * tailcallopt is enabled
2181 // * caller/callee are fastcc
2182 // On X86_64 architecture with GOT-style position independent code only local
2183 // (within module) calls are supported at the moment.
2184 // To keep the stack aligned according to platform abi the function
2185 // GetAlignedArgumentStackSize ensures that argument delta is always multiples
2186 // of stack alignment. (Dynamic linkers need this - darwin's dyld for example)
2187 // If a tail called function callee has more arguments than the caller the
2188 // caller needs to make sure that there is room to move the RETADDR to. This is
2189 // achieved by reserving an area the size of the argument delta right after the
2190 // original REtADDR, but before the saved framepointer or the spilled registers
2191 // e.g. caller(arg1, arg2) calls callee(arg1, arg2,arg3,arg4)
2203 /// GetAlignedArgumentStackSize - Make the stack size align e.g 16n + 12 aligned
2204 /// for a 16 byte align requirement.
2205 unsigned X86TargetLowering::GetAlignedArgumentStackSize(unsigned StackSize,
2206 SelectionDAG& DAG) {
2207 MachineFunction &MF = DAG.getMachineFunction();
2208 const TargetMachine &TM = MF.getTarget();
2209 const TargetFrameInfo &TFI = *TM.getFrameInfo();
2210 unsigned StackAlignment = TFI.getStackAlignment();
2211 uint64_t AlignMask = StackAlignment - 1;
2212 int64_t Offset = StackSize;
2213 uint64_t SlotSize = TD->getPointerSize();
2214 if ( (Offset & AlignMask) <= (StackAlignment - SlotSize) ) {
2215 // Number smaller than 12 so just add the difference.
2216 Offset += ((StackAlignment - SlotSize) - (Offset & AlignMask));
2218 // Mask out lower bits, add stackalignment once plus the 12 bytes.
2219 Offset = ((~AlignMask) & Offset) + StackAlignment +
2220 (StackAlignment-SlotSize);
2225 /// MatchingStackOffset - Return true if the given stack call argument is
2226 /// already available in the same position (relatively) of the caller's
2227 /// incoming argument stack.
2229 bool MatchingStackOffset(SDValue Arg, unsigned Offset, ISD::ArgFlagsTy Flags,
2230 MachineFrameInfo *MFI, const MachineRegisterInfo *MRI,
2231 const X86InstrInfo *TII) {
2232 unsigned Bytes = Arg.getValueType().getSizeInBits() / 8;
2234 if (Arg.getOpcode() == ISD::CopyFromReg) {
2235 unsigned VR = cast<RegisterSDNode>(Arg.getOperand(1))->getReg();
2236 if (!VR || TargetRegisterInfo::isPhysicalRegister(VR))
2238 MachineInstr *Def = MRI->getVRegDef(VR);
2241 if (!Flags.isByVal()) {
2242 if (!TII->isLoadFromStackSlot(Def, FI))
2245 unsigned Opcode = Def->getOpcode();
2246 if ((Opcode == X86::LEA32r || Opcode == X86::LEA64r) &&
2247 Def->getOperand(1).isFI()) {
2248 FI = Def->getOperand(1).getIndex();
2249 Bytes = Flags.getByValSize();
2253 } else if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Arg)) {
2254 if (Flags.isByVal())
2255 // ByVal argument is passed in as a pointer but it's now being
2256 // dereferenced. e.g.
2257 // define @foo(%struct.X* %A) {
2258 // tail call @bar(%struct.X* byval %A)
2261 SDValue Ptr = Ld->getBasePtr();
2262 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr);
2265 FI = FINode->getIndex();
2269 assert(FI != INT_MAX);
2270 if (!MFI->isFixedObjectIndex(FI))
2272 return Offset == MFI->getObjectOffset(FI) && Bytes == MFI->getObjectSize(FI);
2275 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
2276 /// for tail call optimization. Targets which want to do tail call
2277 /// optimization should implement this function.
2279 X86TargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
2280 CallingConv::ID CalleeCC,
2282 bool isCalleeStructRet,
2283 bool isCallerStructRet,
2284 const SmallVectorImpl<ISD::OutputArg> &Outs,
2285 const SmallVectorImpl<ISD::InputArg> &Ins,
2286 SelectionDAG& DAG) const {
2287 if (!IsTailCallConvention(CalleeCC) &&
2288 CalleeCC != CallingConv::C)
2291 // If -tailcallopt is specified, make fastcc functions tail-callable.
2292 const Function *CallerF = DAG.getMachineFunction().getFunction();
2293 if (GuaranteedTailCallOpt) {
2294 if (IsTailCallConvention(CalleeCC) &&
2295 CallerF->getCallingConv() == CalleeCC)
2300 // Look for obvious safe cases to perform tail call optimization that does not
2301 // requite ABI changes. This is what gcc calls sibcall.
2303 // Do not sibcall optimize vararg calls for now.
2307 // Also avoid sibcall optimization if either caller or callee uses struct
2308 // return semantics.
2309 if (isCalleeStructRet || isCallerStructRet)
2312 // If the callee takes no arguments then go on to check the results of the
2314 if (!Outs.empty()) {
2315 // Check if stack adjustment is needed. For now, do not do this if any
2316 // argument is passed on the stack.
2317 SmallVector<CCValAssign, 16> ArgLocs;
2318 CCState CCInfo(CalleeCC, isVarArg, getTargetMachine(),
2319 ArgLocs, *DAG.getContext());
2320 CCInfo.AnalyzeCallOperands(Outs, CCAssignFnForNode(CalleeCC));
2321 if (CCInfo.getNextStackOffset()) {
2322 MachineFunction &MF = DAG.getMachineFunction();
2323 if (MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn())
2325 if (Subtarget->isTargetWin64())
2326 // Win64 ABI has additional complications.
2329 // Check if the arguments are already laid out in the right way as
2330 // the caller's fixed stack objects.
2331 MachineFrameInfo *MFI = MF.getFrameInfo();
2332 const MachineRegisterInfo *MRI = &MF.getRegInfo();
2333 const X86InstrInfo *TII =
2334 ((X86TargetMachine&)getTargetMachine()).getInstrInfo();
2335 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2336 CCValAssign &VA = ArgLocs[i];
2337 EVT RegVT = VA.getLocVT();
2338 SDValue Arg = Outs[i].Val;
2339 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2340 if (VA.getLocInfo() == CCValAssign::Indirect)
2342 if (!VA.isRegLoc()) {
2343 if (!MatchingStackOffset(Arg, VA.getLocMemOffset(), Flags,
2355 X86TargetLowering::createFastISel(MachineFunction &mf, MachineModuleInfo *mmo,
2357 DenseMap<const Value *, unsigned> &vm,
2358 DenseMap<const BasicBlock*, MachineBasicBlock*> &bm,
2359 DenseMap<const AllocaInst *, int> &am
2361 , SmallSet<Instruction*, 8> &cil
2364 return X86::createFastISel(mf, mmo, dw, vm, bm, am
2372 //===----------------------------------------------------------------------===//
2373 // Other Lowering Hooks
2374 //===----------------------------------------------------------------------===//
2377 SDValue X86TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) {
2378 MachineFunction &MF = DAG.getMachineFunction();
2379 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
2380 int ReturnAddrIndex = FuncInfo->getRAIndex();
2382 if (ReturnAddrIndex == 0) {
2383 // Set up a frame object for the return address.
2384 uint64_t SlotSize = TD->getPointerSize();
2385 ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(SlotSize, -SlotSize,
2387 FuncInfo->setRAIndex(ReturnAddrIndex);
2390 return DAG.getFrameIndex(ReturnAddrIndex, getPointerTy());
2394 bool X86::isOffsetSuitableForCodeModel(int64_t Offset, CodeModel::Model M,
2395 bool hasSymbolicDisplacement) {
2396 // Offset should fit into 32 bit immediate field.
2397 if (!isInt32(Offset))
2400 // If we don't have a symbolic displacement - we don't have any extra
2402 if (!hasSymbolicDisplacement)
2405 // FIXME: Some tweaks might be needed for medium code model.
2406 if (M != CodeModel::Small && M != CodeModel::Kernel)
2409 // For small code model we assume that latest object is 16MB before end of 31
2410 // bits boundary. We may also accept pretty large negative constants knowing
2411 // that all objects are in the positive half of address space.
2412 if (M == CodeModel::Small && Offset < 16*1024*1024)
2415 // For kernel code model we know that all object resist in the negative half
2416 // of 32bits address space. We may not accept negative offsets, since they may
2417 // be just off and we may accept pretty large positive ones.
2418 if (M == CodeModel::Kernel && Offset > 0)
2424 /// TranslateX86CC - do a one to one translation of a ISD::CondCode to the X86
2425 /// specific condition code, returning the condition code and the LHS/RHS of the
2426 /// comparison to make.
2427 static unsigned TranslateX86CC(ISD::CondCode SetCCOpcode, bool isFP,
2428 SDValue &LHS, SDValue &RHS, SelectionDAG &DAG) {
2430 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
2431 if (SetCCOpcode == ISD::SETGT && RHSC->isAllOnesValue()) {
2432 // X > -1 -> X == 0, jump !sign.
2433 RHS = DAG.getConstant(0, RHS.getValueType());
2434 return X86::COND_NS;
2435 } else if (SetCCOpcode == ISD::SETLT && RHSC->isNullValue()) {
2436 // X < 0 -> X == 0, jump on sign.
2438 } else if (SetCCOpcode == ISD::SETLT && RHSC->getZExtValue() == 1) {
2440 RHS = DAG.getConstant(0, RHS.getValueType());
2441 return X86::COND_LE;
2445 switch (SetCCOpcode) {
2446 default: llvm_unreachable("Invalid integer condition!");
2447 case ISD::SETEQ: return X86::COND_E;
2448 case ISD::SETGT: return X86::COND_G;
2449 case ISD::SETGE: return X86::COND_GE;
2450 case ISD::SETLT: return X86::COND_L;
2451 case ISD::SETLE: return X86::COND_LE;
2452 case ISD::SETNE: return X86::COND_NE;
2453 case ISD::SETULT: return X86::COND_B;
2454 case ISD::SETUGT: return X86::COND_A;
2455 case ISD::SETULE: return X86::COND_BE;
2456 case ISD::SETUGE: return X86::COND_AE;
2460 // First determine if it is required or is profitable to flip the operands.
2462 // If LHS is a foldable load, but RHS is not, flip the condition.
2463 if ((ISD::isNON_EXTLoad(LHS.getNode()) && LHS.hasOneUse()) &&
2464 !(ISD::isNON_EXTLoad(RHS.getNode()) && RHS.hasOneUse())) {
2465 SetCCOpcode = getSetCCSwappedOperands(SetCCOpcode);
2466 std::swap(LHS, RHS);
2469 switch (SetCCOpcode) {
2475 std::swap(LHS, RHS);
2479 // On a floating point condition, the flags are set as follows:
2481 // 0 | 0 | 0 | X > Y
2482 // 0 | 0 | 1 | X < Y
2483 // 1 | 0 | 0 | X == Y
2484 // 1 | 1 | 1 | unordered
2485 switch (SetCCOpcode) {
2486 default: llvm_unreachable("Condcode should be pre-legalized away");
2488 case ISD::SETEQ: return X86::COND_E;
2489 case ISD::SETOLT: // flipped
2491 case ISD::SETGT: return X86::COND_A;
2492 case ISD::SETOLE: // flipped
2494 case ISD::SETGE: return X86::COND_AE;
2495 case ISD::SETUGT: // flipped
2497 case ISD::SETLT: return X86::COND_B;
2498 case ISD::SETUGE: // flipped
2500 case ISD::SETLE: return X86::COND_BE;
2502 case ISD::SETNE: return X86::COND_NE;
2503 case ISD::SETUO: return X86::COND_P;
2504 case ISD::SETO: return X86::COND_NP;
2506 case ISD::SETUNE: return X86::COND_INVALID;
2510 /// hasFPCMov - is there a floating point cmov for the specific X86 condition
2511 /// code. Current x86 isa includes the following FP cmov instructions:
2512 /// fcmovb, fcomvbe, fcomve, fcmovu, fcmovae, fcmova, fcmovne, fcmovnu.
2513 static bool hasFPCMov(unsigned X86CC) {
2529 /// isFPImmLegal - Returns true if the target can instruction select the
2530 /// specified FP immediate natively. If false, the legalizer will
2531 /// materialize the FP immediate as a load from a constant pool.
2532 bool X86TargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
2533 for (unsigned i = 0, e = LegalFPImmediates.size(); i != e; ++i) {
2534 if (Imm.bitwiseIsEqual(LegalFPImmediates[i]))
2540 /// isUndefOrInRange - Return true if Val is undef or if its value falls within
2541 /// the specified range (L, H].
2542 static bool isUndefOrInRange(int Val, int Low, int Hi) {
2543 return (Val < 0) || (Val >= Low && Val < Hi);
2546 /// isUndefOrEqual - Val is either less than zero (undef) or equal to the
2547 /// specified value.
2548 static bool isUndefOrEqual(int Val, int CmpVal) {
2549 if (Val < 0 || Val == CmpVal)
2554 /// isPSHUFDMask - Return true if the node specifies a shuffle of elements that
2555 /// is suitable for input to PSHUFD or PSHUFW. That is, it doesn't reference
2556 /// the second operand.
2557 static bool isPSHUFDMask(const SmallVectorImpl<int> &Mask, EVT VT) {
2558 if (VT == MVT::v4f32 || VT == MVT::v4i32 || VT == MVT::v4i16)
2559 return (Mask[0] < 4 && Mask[1] < 4 && Mask[2] < 4 && Mask[3] < 4);
2560 if (VT == MVT::v2f64 || VT == MVT::v2i64)
2561 return (Mask[0] < 2 && Mask[1] < 2);
2565 bool X86::isPSHUFDMask(ShuffleVectorSDNode *N) {
2566 SmallVector<int, 8> M;
2568 return ::isPSHUFDMask(M, N->getValueType(0));
2571 /// isPSHUFHWMask - Return true if the node specifies a shuffle of elements that
2572 /// is suitable for input to PSHUFHW.
2573 static bool isPSHUFHWMask(const SmallVectorImpl<int> &Mask, EVT VT) {
2574 if (VT != MVT::v8i16)
2577 // Lower quadword copied in order or undef.
2578 for (int i = 0; i != 4; ++i)
2579 if (Mask[i] >= 0 && Mask[i] != i)
2582 // Upper quadword shuffled.
2583 for (int i = 4; i != 8; ++i)
2584 if (Mask[i] >= 0 && (Mask[i] < 4 || Mask[i] > 7))
2590 bool X86::isPSHUFHWMask(ShuffleVectorSDNode *N) {
2591 SmallVector<int, 8> M;
2593 return ::isPSHUFHWMask(M, N->getValueType(0));
2596 /// isPSHUFLWMask - Return true if the node specifies a shuffle of elements that
2597 /// is suitable for input to PSHUFLW.
2598 static bool isPSHUFLWMask(const SmallVectorImpl<int> &Mask, EVT VT) {
2599 if (VT != MVT::v8i16)
2602 // Upper quadword copied in order.
2603 for (int i = 4; i != 8; ++i)
2604 if (Mask[i] >= 0 && Mask[i] != i)
2607 // Lower quadword shuffled.
2608 for (int i = 0; i != 4; ++i)
2615 bool X86::isPSHUFLWMask(ShuffleVectorSDNode *N) {
2616 SmallVector<int, 8> M;
2618 return ::isPSHUFLWMask(M, N->getValueType(0));
2621 /// isPALIGNRMask - Return true if the node specifies a shuffle of elements that
2622 /// is suitable for input to PALIGNR.
2623 static bool isPALIGNRMask(const SmallVectorImpl<int> &Mask, EVT VT,
2625 int i, e = VT.getVectorNumElements();
2627 // Do not handle v2i64 / v2f64 shuffles with palignr.
2628 if (e < 4 || !hasSSSE3)
2631 for (i = 0; i != e; ++i)
2635 // All undef, not a palignr.
2639 // Determine if it's ok to perform a palignr with only the LHS, since we
2640 // don't have access to the actual shuffle elements to see if RHS is undef.
2641 bool Unary = Mask[i] < (int)e;
2642 bool NeedsUnary = false;
2644 int s = Mask[i] - i;
2646 // Check the rest of the elements to see if they are consecutive.
2647 for (++i; i != e; ++i) {
2652 Unary = Unary && (m < (int)e);
2653 NeedsUnary = NeedsUnary || (m < s);
2655 if (NeedsUnary && !Unary)
2657 if (Unary && m != ((s+i) & (e-1)))
2659 if (!Unary && m != (s+i))
2665 bool X86::isPALIGNRMask(ShuffleVectorSDNode *N) {
2666 SmallVector<int, 8> M;
2668 return ::isPALIGNRMask(M, N->getValueType(0), true);
2671 /// isSHUFPMask - Return true if the specified VECTOR_SHUFFLE operand
2672 /// specifies a shuffle of elements that is suitable for input to SHUFP*.
2673 static bool isSHUFPMask(const SmallVectorImpl<int> &Mask, EVT VT) {
2674 int NumElems = VT.getVectorNumElements();
2675 if (NumElems != 2 && NumElems != 4)
2678 int Half = NumElems / 2;
2679 for (int i = 0; i < Half; ++i)
2680 if (!isUndefOrInRange(Mask[i], 0, NumElems))
2682 for (int i = Half; i < NumElems; ++i)
2683 if (!isUndefOrInRange(Mask[i], NumElems, NumElems*2))
2689 bool X86::isSHUFPMask(ShuffleVectorSDNode *N) {
2690 SmallVector<int, 8> M;
2692 return ::isSHUFPMask(M, N->getValueType(0));
2695 /// isCommutedSHUFP - Returns true if the shuffle mask is exactly
2696 /// the reverse of what x86 shuffles want. x86 shuffles requires the lower
2697 /// half elements to come from vector 1 (which would equal the dest.) and
2698 /// the upper half to come from vector 2.
2699 static bool isCommutedSHUFPMask(const SmallVectorImpl<int> &Mask, EVT VT) {
2700 int NumElems = VT.getVectorNumElements();
2702 if (NumElems != 2 && NumElems != 4)
2705 int Half = NumElems / 2;
2706 for (int i = 0; i < Half; ++i)
2707 if (!isUndefOrInRange(Mask[i], NumElems, NumElems*2))
2709 for (int i = Half; i < NumElems; ++i)
2710 if (!isUndefOrInRange(Mask[i], 0, NumElems))
2715 static bool isCommutedSHUFP(ShuffleVectorSDNode *N) {
2716 SmallVector<int, 8> M;
2718 return isCommutedSHUFPMask(M, N->getValueType(0));
2721 /// isMOVHLPSMask - Return true if the specified VECTOR_SHUFFLE operand
2722 /// specifies a shuffle of elements that is suitable for input to MOVHLPS.
2723 bool X86::isMOVHLPSMask(ShuffleVectorSDNode *N) {
2724 if (N->getValueType(0).getVectorNumElements() != 4)
2727 // Expect bit0 == 6, bit1 == 7, bit2 == 2, bit3 == 3
2728 return isUndefOrEqual(N->getMaskElt(0), 6) &&
2729 isUndefOrEqual(N->getMaskElt(1), 7) &&
2730 isUndefOrEqual(N->getMaskElt(2), 2) &&
2731 isUndefOrEqual(N->getMaskElt(3), 3);
2734 /// isMOVHLPS_v_undef_Mask - Special case of isMOVHLPSMask for canonical form
2735 /// of vector_shuffle v, v, <2, 3, 2, 3>, i.e. vector_shuffle v, undef,
2737 bool X86::isMOVHLPS_v_undef_Mask(ShuffleVectorSDNode *N) {
2738 unsigned NumElems = N->getValueType(0).getVectorNumElements();
2743 return isUndefOrEqual(N->getMaskElt(0), 2) &&
2744 isUndefOrEqual(N->getMaskElt(1), 3) &&
2745 isUndefOrEqual(N->getMaskElt(2), 2) &&
2746 isUndefOrEqual(N->getMaskElt(3), 3);
2749 /// isMOVLPMask - Return true if the specified VECTOR_SHUFFLE operand
2750 /// specifies a shuffle of elements that is suitable for input to MOVLP{S|D}.
2751 bool X86::isMOVLPMask(ShuffleVectorSDNode *N) {
2752 unsigned NumElems = N->getValueType(0).getVectorNumElements();
2754 if (NumElems != 2 && NumElems != 4)
2757 for (unsigned i = 0; i < NumElems/2; ++i)
2758 if (!isUndefOrEqual(N->getMaskElt(i), i + NumElems))
2761 for (unsigned i = NumElems/2; i < NumElems; ++i)
2762 if (!isUndefOrEqual(N->getMaskElt(i), i))
2768 /// isMOVLHPSMask - Return true if the specified VECTOR_SHUFFLE operand
2769 /// specifies a shuffle of elements that is suitable for input to MOVLHPS.
2770 bool X86::isMOVLHPSMask(ShuffleVectorSDNode *N) {
2771 unsigned NumElems = N->getValueType(0).getVectorNumElements();
2773 if (NumElems != 2 && NumElems != 4)
2776 for (unsigned i = 0; i < NumElems/2; ++i)
2777 if (!isUndefOrEqual(N->getMaskElt(i), i))
2780 for (unsigned i = 0; i < NumElems/2; ++i)
2781 if (!isUndefOrEqual(N->getMaskElt(i + NumElems/2), i + NumElems))
2787 /// isUNPCKLMask - Return true if the specified VECTOR_SHUFFLE operand
2788 /// specifies a shuffle of elements that is suitable for input to UNPCKL.
2789 static bool isUNPCKLMask(const SmallVectorImpl<int> &Mask, EVT VT,
2790 bool V2IsSplat = false) {
2791 int NumElts = VT.getVectorNumElements();
2792 if (NumElts != 2 && NumElts != 4 && NumElts != 8 && NumElts != 16)
2795 for (int i = 0, j = 0; i != NumElts; i += 2, ++j) {
2797 int BitI1 = Mask[i+1];
2798 if (!isUndefOrEqual(BitI, j))
2801 if (!isUndefOrEqual(BitI1, NumElts))
2804 if (!isUndefOrEqual(BitI1, j + NumElts))
2811 bool X86::isUNPCKLMask(ShuffleVectorSDNode *N, bool V2IsSplat) {
2812 SmallVector<int, 8> M;
2814 return ::isUNPCKLMask(M, N->getValueType(0), V2IsSplat);
2817 /// isUNPCKHMask - Return true if the specified VECTOR_SHUFFLE operand
2818 /// specifies a shuffle of elements that is suitable for input to UNPCKH.
2819 static bool isUNPCKHMask(const SmallVectorImpl<int> &Mask, EVT VT,
2820 bool V2IsSplat = false) {
2821 int NumElts = VT.getVectorNumElements();
2822 if (NumElts != 2 && NumElts != 4 && NumElts != 8 && NumElts != 16)
2825 for (int i = 0, j = 0; i != NumElts; i += 2, ++j) {
2827 int BitI1 = Mask[i+1];
2828 if (!isUndefOrEqual(BitI, j + NumElts/2))
2831 if (isUndefOrEqual(BitI1, NumElts))
2834 if (!isUndefOrEqual(BitI1, j + NumElts/2 + NumElts))
2841 bool X86::isUNPCKHMask(ShuffleVectorSDNode *N, bool V2IsSplat) {
2842 SmallVector<int, 8> M;
2844 return ::isUNPCKHMask(M, N->getValueType(0), V2IsSplat);
2847 /// isUNPCKL_v_undef_Mask - Special case of isUNPCKLMask for canonical form
2848 /// of vector_shuffle v, v, <0, 4, 1, 5>, i.e. vector_shuffle v, undef,
2850 static bool isUNPCKL_v_undef_Mask(const SmallVectorImpl<int> &Mask, EVT VT) {
2851 int NumElems = VT.getVectorNumElements();
2852 if (NumElems != 2 && NumElems != 4 && NumElems != 8 && NumElems != 16)
2855 for (int i = 0, j = 0; i != NumElems; i += 2, ++j) {
2857 int BitI1 = Mask[i+1];
2858 if (!isUndefOrEqual(BitI, j))
2860 if (!isUndefOrEqual(BitI1, j))
2866 bool X86::isUNPCKL_v_undef_Mask(ShuffleVectorSDNode *N) {
2867 SmallVector<int, 8> M;
2869 return ::isUNPCKL_v_undef_Mask(M, N->getValueType(0));
2872 /// isUNPCKH_v_undef_Mask - Special case of isUNPCKHMask for canonical form
2873 /// of vector_shuffle v, v, <2, 6, 3, 7>, i.e. vector_shuffle v, undef,
2875 static bool isUNPCKH_v_undef_Mask(const SmallVectorImpl<int> &Mask, EVT VT) {
2876 int NumElems = VT.getVectorNumElements();
2877 if (NumElems != 2 && NumElems != 4 && NumElems != 8 && NumElems != 16)
2880 for (int i = 0, j = NumElems / 2; i != NumElems; i += 2, ++j) {
2882 int BitI1 = Mask[i+1];
2883 if (!isUndefOrEqual(BitI, j))
2885 if (!isUndefOrEqual(BitI1, j))
2891 bool X86::isUNPCKH_v_undef_Mask(ShuffleVectorSDNode *N) {
2892 SmallVector<int, 8> M;
2894 return ::isUNPCKH_v_undef_Mask(M, N->getValueType(0));
2897 /// isMOVLMask - Return true if the specified VECTOR_SHUFFLE operand
2898 /// specifies a shuffle of elements that is suitable for input to MOVSS,
2899 /// MOVSD, and MOVD, i.e. setting the lowest element.
2900 static bool isMOVLMask(const SmallVectorImpl<int> &Mask, EVT VT) {
2901 if (VT.getVectorElementType().getSizeInBits() < 32)
2904 int NumElts = VT.getVectorNumElements();
2906 if (!isUndefOrEqual(Mask[0], NumElts))
2909 for (int i = 1; i < NumElts; ++i)
2910 if (!isUndefOrEqual(Mask[i], i))
2916 bool X86::isMOVLMask(ShuffleVectorSDNode *N) {
2917 SmallVector<int, 8> M;
2919 return ::isMOVLMask(M, N->getValueType(0));
2922 /// isCommutedMOVL - Returns true if the shuffle mask is except the reverse
2923 /// of what x86 movss want. X86 movs requires the lowest element to be lowest
2924 /// element of vector 2 and the other elements to come from vector 1 in order.
2925 static bool isCommutedMOVLMask(const SmallVectorImpl<int> &Mask, EVT VT,
2926 bool V2IsSplat = false, bool V2IsUndef = false) {
2927 int NumOps = VT.getVectorNumElements();
2928 if (NumOps != 2 && NumOps != 4 && NumOps != 8 && NumOps != 16)
2931 if (!isUndefOrEqual(Mask[0], 0))
2934 for (int i = 1; i < NumOps; ++i)
2935 if (!(isUndefOrEqual(Mask[i], i+NumOps) ||
2936 (V2IsUndef && isUndefOrInRange(Mask[i], NumOps, NumOps*2)) ||
2937 (V2IsSplat && isUndefOrEqual(Mask[i], NumOps))))
2943 static bool isCommutedMOVL(ShuffleVectorSDNode *N, bool V2IsSplat = false,
2944 bool V2IsUndef = false) {
2945 SmallVector<int, 8> M;
2947 return isCommutedMOVLMask(M, N->getValueType(0), V2IsSplat, V2IsUndef);
2950 /// isMOVSHDUPMask - Return true if the specified VECTOR_SHUFFLE operand
2951 /// specifies a shuffle of elements that is suitable for input to MOVSHDUP.
2952 bool X86::isMOVSHDUPMask(ShuffleVectorSDNode *N) {
2953 if (N->getValueType(0).getVectorNumElements() != 4)
2956 // Expect 1, 1, 3, 3
2957 for (unsigned i = 0; i < 2; ++i) {
2958 int Elt = N->getMaskElt(i);
2959 if (Elt >= 0 && Elt != 1)
2964 for (unsigned i = 2; i < 4; ++i) {
2965 int Elt = N->getMaskElt(i);
2966 if (Elt >= 0 && Elt != 3)
2971 // Don't use movshdup if it can be done with a shufps.
2972 // FIXME: verify that matching u, u, 3, 3 is what we want.
2976 /// isMOVSLDUPMask - Return true if the specified VECTOR_SHUFFLE operand
2977 /// specifies a shuffle of elements that is suitable for input to MOVSLDUP.
2978 bool X86::isMOVSLDUPMask(ShuffleVectorSDNode *N) {
2979 if (N->getValueType(0).getVectorNumElements() != 4)
2982 // Expect 0, 0, 2, 2
2983 for (unsigned i = 0; i < 2; ++i)
2984 if (N->getMaskElt(i) > 0)
2988 for (unsigned i = 2; i < 4; ++i) {
2989 int Elt = N->getMaskElt(i);
2990 if (Elt >= 0 && Elt != 2)
2995 // Don't use movsldup if it can be done with a shufps.
2999 /// isMOVDDUPMask - Return true if the specified VECTOR_SHUFFLE operand
3000 /// specifies a shuffle of elements that is suitable for input to MOVDDUP.
3001 bool X86::isMOVDDUPMask(ShuffleVectorSDNode *N) {
3002 int e = N->getValueType(0).getVectorNumElements() / 2;
3004 for (int i = 0; i < e; ++i)
3005 if (!isUndefOrEqual(N->getMaskElt(i), i))
3007 for (int i = 0; i < e; ++i)
3008 if (!isUndefOrEqual(N->getMaskElt(e+i), i))
3013 /// getShuffleSHUFImmediate - Return the appropriate immediate to shuffle
3014 /// the specified VECTOR_SHUFFLE mask with PSHUF* and SHUFP* instructions.
3015 unsigned X86::getShuffleSHUFImmediate(SDNode *N) {
3016 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
3017 int NumOperands = SVOp->getValueType(0).getVectorNumElements();
3019 unsigned Shift = (NumOperands == 4) ? 2 : 1;
3021 for (int i = 0; i < NumOperands; ++i) {
3022 int Val = SVOp->getMaskElt(NumOperands-i-1);
3023 if (Val < 0) Val = 0;
3024 if (Val >= NumOperands) Val -= NumOperands;
3026 if (i != NumOperands - 1)
3032 /// getShufflePSHUFHWImmediate - Return the appropriate immediate to shuffle
3033 /// the specified VECTOR_SHUFFLE mask with the PSHUFHW instruction.
3034 unsigned X86::getShufflePSHUFHWImmediate(SDNode *N) {
3035 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
3037 // 8 nodes, but we only care about the last 4.
3038 for (unsigned i = 7; i >= 4; --i) {
3039 int Val = SVOp->getMaskElt(i);
3048 /// getShufflePSHUFLWImmediate - Return the appropriate immediate to shuffle
3049 /// the specified VECTOR_SHUFFLE mask with the PSHUFLW instruction.
3050 unsigned X86::getShufflePSHUFLWImmediate(SDNode *N) {
3051 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
3053 // 8 nodes, but we only care about the first 4.
3054 for (int i = 3; i >= 0; --i) {
3055 int Val = SVOp->getMaskElt(i);
3064 /// getShufflePALIGNRImmediate - Return the appropriate immediate to shuffle
3065 /// the specified VECTOR_SHUFFLE mask with the PALIGNR instruction.
3066 unsigned X86::getShufflePALIGNRImmediate(SDNode *N) {
3067 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
3068 EVT VVT = N->getValueType(0);
3069 unsigned EltSize = VVT.getVectorElementType().getSizeInBits() >> 3;
3073 for (i = 0, e = VVT.getVectorNumElements(); i != e; ++i) {
3074 Val = SVOp->getMaskElt(i);
3078 return (Val - i) * EltSize;
3081 /// isZeroNode - Returns true if Elt is a constant zero or a floating point
3083 bool X86::isZeroNode(SDValue Elt) {
3084 return ((isa<ConstantSDNode>(Elt) &&
3085 cast<ConstantSDNode>(Elt)->getZExtValue() == 0) ||
3086 (isa<ConstantFPSDNode>(Elt) &&
3087 cast<ConstantFPSDNode>(Elt)->getValueAPF().isPosZero()));
3090 /// CommuteVectorShuffle - Swap vector_shuffle operands as well as values in
3091 /// their permute mask.
3092 static SDValue CommuteVectorShuffle(ShuffleVectorSDNode *SVOp,
3093 SelectionDAG &DAG) {
3094 EVT VT = SVOp->getValueType(0);
3095 unsigned NumElems = VT.getVectorNumElements();
3096 SmallVector<int, 8> MaskVec;
3098 for (unsigned i = 0; i != NumElems; ++i) {
3099 int idx = SVOp->getMaskElt(i);
3101 MaskVec.push_back(idx);
3102 else if (idx < (int)NumElems)
3103 MaskVec.push_back(idx + NumElems);
3105 MaskVec.push_back(idx - NumElems);
3107 return DAG.getVectorShuffle(VT, SVOp->getDebugLoc(), SVOp->getOperand(1),
3108 SVOp->getOperand(0), &MaskVec[0]);
3111 /// CommuteVectorShuffleMask - Change values in a shuffle permute mask assuming
3112 /// the two vector operands have swapped position.
3113 static void CommuteVectorShuffleMask(SmallVectorImpl<int> &Mask, EVT VT) {
3114 unsigned NumElems = VT.getVectorNumElements();
3115 for (unsigned i = 0; i != NumElems; ++i) {
3119 else if (idx < (int)NumElems)
3120 Mask[i] = idx + NumElems;
3122 Mask[i] = idx - NumElems;
3126 /// ShouldXformToMOVHLPS - Return true if the node should be transformed to
3127 /// match movhlps. The lower half elements should come from upper half of
3128 /// V1 (and in order), and the upper half elements should come from the upper
3129 /// half of V2 (and in order).
3130 static bool ShouldXformToMOVHLPS(ShuffleVectorSDNode *Op) {
3131 if (Op->getValueType(0).getVectorNumElements() != 4)
3133 for (unsigned i = 0, e = 2; i != e; ++i)
3134 if (!isUndefOrEqual(Op->getMaskElt(i), i+2))
3136 for (unsigned i = 2; i != 4; ++i)
3137 if (!isUndefOrEqual(Op->getMaskElt(i), i+4))
3142 /// isScalarLoadToVector - Returns true if the node is a scalar load that
3143 /// is promoted to a vector. It also returns the LoadSDNode by reference if
3145 static bool isScalarLoadToVector(SDNode *N, LoadSDNode **LD = NULL) {
3146 if (N->getOpcode() != ISD::SCALAR_TO_VECTOR)
3148 N = N->getOperand(0).getNode();
3149 if (!ISD::isNON_EXTLoad(N))
3152 *LD = cast<LoadSDNode>(N);
3156 /// ShouldXformToMOVLP{S|D} - Return true if the node should be transformed to
3157 /// match movlp{s|d}. The lower half elements should come from lower half of
3158 /// V1 (and in order), and the upper half elements should come from the upper
3159 /// half of V2 (and in order). And since V1 will become the source of the
3160 /// MOVLP, it must be either a vector load or a scalar load to vector.
3161 static bool ShouldXformToMOVLP(SDNode *V1, SDNode *V2,
3162 ShuffleVectorSDNode *Op) {
3163 if (!ISD::isNON_EXTLoad(V1) && !isScalarLoadToVector(V1))
3165 // Is V2 is a vector load, don't do this transformation. We will try to use
3166 // load folding shufps op.
3167 if (ISD::isNON_EXTLoad(V2))
3170 unsigned NumElems = Op->getValueType(0).getVectorNumElements();
3172 if (NumElems != 2 && NumElems != 4)
3174 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
3175 if (!isUndefOrEqual(Op->getMaskElt(i), i))
3177 for (unsigned i = NumElems/2; i != NumElems; ++i)
3178 if (!isUndefOrEqual(Op->getMaskElt(i), i+NumElems))
3183 /// isSplatVector - Returns true if N is a BUILD_VECTOR node whose elements are
3185 static bool isSplatVector(SDNode *N) {
3186 if (N->getOpcode() != ISD::BUILD_VECTOR)
3189 SDValue SplatValue = N->getOperand(0);
3190 for (unsigned i = 1, e = N->getNumOperands(); i != e; ++i)
3191 if (N->getOperand(i) != SplatValue)
3196 /// isZeroShuffle - Returns true if N is a VECTOR_SHUFFLE that can be resolved
3197 /// to an zero vector.
3198 /// FIXME: move to dag combiner / method on ShuffleVectorSDNode
3199 static bool isZeroShuffle(ShuffleVectorSDNode *N) {
3200 SDValue V1 = N->getOperand(0);
3201 SDValue V2 = N->getOperand(1);
3202 unsigned NumElems = N->getValueType(0).getVectorNumElements();
3203 for (unsigned i = 0; i != NumElems; ++i) {
3204 int Idx = N->getMaskElt(i);
3205 if (Idx >= (int)NumElems) {
3206 unsigned Opc = V2.getOpcode();
3207 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V2.getNode()))
3209 if (Opc != ISD::BUILD_VECTOR ||
3210 !X86::isZeroNode(V2.getOperand(Idx-NumElems)))
3212 } else if (Idx >= 0) {
3213 unsigned Opc = V1.getOpcode();
3214 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V1.getNode()))
3216 if (Opc != ISD::BUILD_VECTOR ||
3217 !X86::isZeroNode(V1.getOperand(Idx)))
3224 /// getZeroVector - Returns a vector of specified type with all zero elements.
3226 static SDValue getZeroVector(EVT VT, bool HasSSE2, SelectionDAG &DAG,
3228 assert(VT.isVector() && "Expected a vector type");
3230 // Always build zero vectors as <4 x i32> or <2 x i32> bitcasted to their dest
3231 // type. This ensures they get CSE'd.
3233 if (VT.getSizeInBits() == 64) { // MMX
3234 SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
3235 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2i32, Cst, Cst);
3236 } else if (HasSSE2) { // SSE2
3237 SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
3238 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
3240 SDValue Cst = DAG.getTargetConstantFP(+0.0, MVT::f32);
3241 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4f32, Cst, Cst, Cst, Cst);
3243 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Vec);
3246 /// getOnesVector - Returns a vector of specified type with all bits set.
3248 static SDValue getOnesVector(EVT VT, SelectionDAG &DAG, DebugLoc dl) {
3249 assert(VT.isVector() && "Expected a vector type");
3251 // Always build ones vectors as <4 x i32> or <2 x i32> bitcasted to their dest
3252 // type. This ensures they get CSE'd.
3253 SDValue Cst = DAG.getTargetConstant(~0U, MVT::i32);
3255 if (VT.getSizeInBits() == 64) // MMX
3256 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2i32, Cst, Cst);
3258 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
3259 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Vec);
3263 /// NormalizeMask - V2 is a splat, modify the mask (if needed) so all elements
3264 /// that point to V2 points to its first element.
3265 static SDValue NormalizeMask(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
3266 EVT VT = SVOp->getValueType(0);
3267 unsigned NumElems = VT.getVectorNumElements();
3269 bool Changed = false;
3270 SmallVector<int, 8> MaskVec;
3271 SVOp->getMask(MaskVec);
3273 for (unsigned i = 0; i != NumElems; ++i) {
3274 if (MaskVec[i] > (int)NumElems) {
3275 MaskVec[i] = NumElems;
3280 return DAG.getVectorShuffle(VT, SVOp->getDebugLoc(), SVOp->getOperand(0),
3281 SVOp->getOperand(1), &MaskVec[0]);
3282 return SDValue(SVOp, 0);
3285 /// getMOVLMask - Returns a vector_shuffle mask for an movs{s|d}, movd
3286 /// operation of specified width.
3287 static SDValue getMOVL(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1,
3289 unsigned NumElems = VT.getVectorNumElements();
3290 SmallVector<int, 8> Mask;
3291 Mask.push_back(NumElems);
3292 for (unsigned i = 1; i != NumElems; ++i)
3294 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
3297 /// getUnpackl - Returns a vector_shuffle node for an unpackl operation.
3298 static SDValue getUnpackl(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1,
3300 unsigned NumElems = VT.getVectorNumElements();
3301 SmallVector<int, 8> Mask;
3302 for (unsigned i = 0, e = NumElems/2; i != e; ++i) {
3304 Mask.push_back(i + NumElems);
3306 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
3309 /// getUnpackhMask - Returns a vector_shuffle node for an unpackh operation.
3310 static SDValue getUnpackh(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1,
3312 unsigned NumElems = VT.getVectorNumElements();
3313 unsigned Half = NumElems/2;
3314 SmallVector<int, 8> Mask;
3315 for (unsigned i = 0; i != Half; ++i) {
3316 Mask.push_back(i + Half);
3317 Mask.push_back(i + NumElems + Half);
3319 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
3322 /// PromoteSplat - Promote a splat of v4f32, v8i16 or v16i8 to v4i32.
3323 static SDValue PromoteSplat(ShuffleVectorSDNode *SV, SelectionDAG &DAG,
3325 if (SV->getValueType(0).getVectorNumElements() <= 4)
3326 return SDValue(SV, 0);
3328 EVT PVT = MVT::v4f32;
3329 EVT VT = SV->getValueType(0);
3330 DebugLoc dl = SV->getDebugLoc();
3331 SDValue V1 = SV->getOperand(0);
3332 int NumElems = VT.getVectorNumElements();
3333 int EltNo = SV->getSplatIndex();
3335 // unpack elements to the correct location
3336 while (NumElems > 4) {
3337 if (EltNo < NumElems/2) {
3338 V1 = getUnpackl(DAG, dl, VT, V1, V1);
3340 V1 = getUnpackh(DAG, dl, VT, V1, V1);
3341 EltNo -= NumElems/2;
3346 // Perform the splat.
3347 int SplatMask[4] = { EltNo, EltNo, EltNo, EltNo };
3348 V1 = DAG.getNode(ISD::BIT_CONVERT, dl, PVT, V1);
3349 V1 = DAG.getVectorShuffle(PVT, dl, V1, DAG.getUNDEF(PVT), &SplatMask[0]);
3350 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, V1);
3353 /// getShuffleVectorZeroOrUndef - Return a vector_shuffle of the specified
3354 /// vector of zero or undef vector. This produces a shuffle where the low
3355 /// element of V2 is swizzled into the zero/undef vector, landing at element
3356 /// Idx. This produces a shuffle mask like 4,1,2,3 (idx=0) or 0,1,2,4 (idx=3).
3357 static SDValue getShuffleVectorZeroOrUndef(SDValue V2, unsigned Idx,
3358 bool isZero, bool HasSSE2,
3359 SelectionDAG &DAG) {
3360 EVT VT = V2.getValueType();
3362 ? getZeroVector(VT, HasSSE2, DAG, V2.getDebugLoc()) : DAG.getUNDEF(VT);
3363 unsigned NumElems = VT.getVectorNumElements();
3364 SmallVector<int, 16> MaskVec;
3365 for (unsigned i = 0; i != NumElems; ++i)
3366 // If this is the insertion idx, put the low elt of V2 here.
3367 MaskVec.push_back(i == Idx ? NumElems : i);
3368 return DAG.getVectorShuffle(VT, V2.getDebugLoc(), V1, V2, &MaskVec[0]);
3371 /// getNumOfConsecutiveZeros - Return the number of elements in a result of
3372 /// a shuffle that is zero.
3374 unsigned getNumOfConsecutiveZeros(ShuffleVectorSDNode *SVOp, int NumElems,
3375 bool Low, SelectionDAG &DAG) {
3376 unsigned NumZeros = 0;
3377 for (int i = 0; i < NumElems; ++i) {
3378 unsigned Index = Low ? i : NumElems-i-1;
3379 int Idx = SVOp->getMaskElt(Index);
3384 SDValue Elt = DAG.getShuffleScalarElt(SVOp, Index);
3385 if (Elt.getNode() && X86::isZeroNode(Elt))
3393 /// isVectorShift - Returns true if the shuffle can be implemented as a
3394 /// logical left or right shift of a vector.
3395 /// FIXME: split into pslldqi, psrldqi, palignr variants.
3396 static bool isVectorShift(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
3397 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
3398 int NumElems = SVOp->getValueType(0).getVectorNumElements();
3401 unsigned NumZeros = getNumOfConsecutiveZeros(SVOp, NumElems, true, DAG);
3404 NumZeros = getNumOfConsecutiveZeros(SVOp, NumElems, false, DAG);
3408 bool SeenV1 = false;
3409 bool SeenV2 = false;
3410 for (int i = NumZeros; i < NumElems; ++i) {
3411 int Val = isLeft ? (i - NumZeros) : i;
3412 int Idx = SVOp->getMaskElt(isLeft ? i : (i - NumZeros));
3424 if (SeenV1 && SeenV2)
3427 ShVal = SeenV1 ? SVOp->getOperand(0) : SVOp->getOperand(1);
3433 /// LowerBuildVectorv16i8 - Custom lower build_vector of v16i8.
3435 static SDValue LowerBuildVectorv16i8(SDValue Op, unsigned NonZeros,
3436 unsigned NumNonZero, unsigned NumZero,
3437 SelectionDAG &DAG, TargetLowering &TLI) {
3441 DebugLoc dl = Op.getDebugLoc();
3444 for (unsigned i = 0; i < 16; ++i) {
3445 bool ThisIsNonZero = (NonZeros & (1 << i)) != 0;
3446 if (ThisIsNonZero && First) {
3448 V = getZeroVector(MVT::v8i16, true, DAG, dl);
3450 V = DAG.getUNDEF(MVT::v8i16);
3455 SDValue ThisElt(0, 0), LastElt(0, 0);
3456 bool LastIsNonZero = (NonZeros & (1 << (i-1))) != 0;
3457 if (LastIsNonZero) {
3458 LastElt = DAG.getNode(ISD::ZERO_EXTEND, dl,
3459 MVT::i16, Op.getOperand(i-1));
3461 if (ThisIsNonZero) {
3462 ThisElt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, Op.getOperand(i));
3463 ThisElt = DAG.getNode(ISD::SHL, dl, MVT::i16,
3464 ThisElt, DAG.getConstant(8, MVT::i8));
3466 ThisElt = DAG.getNode(ISD::OR, dl, MVT::i16, ThisElt, LastElt);
3470 if (ThisElt.getNode())
3471 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, V, ThisElt,
3472 DAG.getIntPtrConstant(i/2));
3476 return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v16i8, V);
3479 /// LowerBuildVectorv8i16 - Custom lower build_vector of v8i16.
3481 static SDValue LowerBuildVectorv8i16(SDValue Op, unsigned NonZeros,
3482 unsigned NumNonZero, unsigned NumZero,
3483 SelectionDAG &DAG, TargetLowering &TLI) {
3487 DebugLoc dl = Op.getDebugLoc();
3490 for (unsigned i = 0; i < 8; ++i) {
3491 bool isNonZero = (NonZeros & (1 << i)) != 0;
3495 V = getZeroVector(MVT::v8i16, true, DAG, dl);
3497 V = DAG.getUNDEF(MVT::v8i16);
3500 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl,
3501 MVT::v8i16, V, Op.getOperand(i),
3502 DAG.getIntPtrConstant(i));
3509 /// getVShift - Return a vector logical shift node.
3511 static SDValue getVShift(bool isLeft, EVT VT, SDValue SrcOp,
3512 unsigned NumBits, SelectionDAG &DAG,
3513 const TargetLowering &TLI, DebugLoc dl) {
3514 bool isMMX = VT.getSizeInBits() == 64;
3515 EVT ShVT = isMMX ? MVT::v1i64 : MVT::v2i64;
3516 unsigned Opc = isLeft ? X86ISD::VSHL : X86ISD::VSRL;
3517 SrcOp = DAG.getNode(ISD::BIT_CONVERT, dl, ShVT, SrcOp);
3518 return DAG.getNode(ISD::BIT_CONVERT, dl, VT,
3519 DAG.getNode(Opc, dl, ShVT, SrcOp,
3520 DAG.getConstant(NumBits, TLI.getShiftAmountTy())));
3524 X86TargetLowering::LowerAsSplatVectorLoad(SDValue SrcOp, EVT VT, DebugLoc dl,
3525 SelectionDAG &DAG) {
3527 // Check if the scalar load can be widened into a vector load. And if
3528 // the address is "base + cst" see if the cst can be "absorbed" into
3529 // the shuffle mask.
3530 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(SrcOp)) {
3531 SDValue Ptr = LD->getBasePtr();
3532 if (!ISD::isNormalLoad(LD) || LD->isVolatile())
3534 EVT PVT = LD->getValueType(0);
3535 if (PVT != MVT::i32 && PVT != MVT::f32)
3540 if (FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr)) {
3541 FI = FINode->getIndex();
3543 } else if (Ptr.getOpcode() == ISD::ADD &&
3544 isa<ConstantSDNode>(Ptr.getOperand(1)) &&
3545 isa<FrameIndexSDNode>(Ptr.getOperand(0))) {
3546 FI = cast<FrameIndexSDNode>(Ptr.getOperand(0))->getIndex();
3547 Offset = Ptr.getConstantOperandVal(1);
3548 Ptr = Ptr.getOperand(0);
3553 SDValue Chain = LD->getChain();
3554 // Make sure the stack object alignment is at least 16.
3555 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
3556 if (DAG.InferPtrAlignment(Ptr) < 16) {
3557 if (MFI->isFixedObjectIndex(FI)) {
3558 // Can't change the alignment. FIXME: It's possible to compute
3559 // the exact stack offset and reference FI + adjust offset instead.
3560 // If someone *really* cares about this. That's the way to implement it.
3563 MFI->setObjectAlignment(FI, 16);
3567 // (Offset % 16) must be multiple of 4. Then address is then
3568 // Ptr + (Offset & ~15).
3571 if ((Offset % 16) & 3)
3573 int64_t StartOffset = Offset & ~15;
3575 Ptr = DAG.getNode(ISD::ADD, Ptr.getDebugLoc(), Ptr.getValueType(),
3576 Ptr,DAG.getConstant(StartOffset, Ptr.getValueType()));
3578 int EltNo = (Offset - StartOffset) >> 2;
3579 int Mask[4] = { EltNo, EltNo, EltNo, EltNo };
3580 EVT VT = (PVT == MVT::i32) ? MVT::v4i32 : MVT::v4f32;
3581 SDValue V1 = DAG.getLoad(VT, dl, Chain, Ptr,LD->getSrcValue(),0,
3583 // Canonicalize it to a v4i32 shuffle.
3584 V1 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v4i32, V1);
3585 return DAG.getNode(ISD::BIT_CONVERT, dl, VT,
3586 DAG.getVectorShuffle(MVT::v4i32, dl, V1,
3587 DAG.getUNDEF(MVT::v4i32), &Mask[0]));
3594 X86TargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) {
3595 DebugLoc dl = Op.getDebugLoc();
3596 // All zero's are handled with pxor, all one's are handled with pcmpeqd.
3597 if (ISD::isBuildVectorAllZeros(Op.getNode())
3598 || ISD::isBuildVectorAllOnes(Op.getNode())) {
3599 // Canonicalize this to either <4 x i32> or <2 x i32> (SSE vs MMX) to
3600 // 1) ensure the zero vectors are CSE'd, and 2) ensure that i64 scalars are
3601 // eliminated on x86-32 hosts.
3602 if (Op.getValueType() == MVT::v4i32 || Op.getValueType() == MVT::v2i32)
3605 if (ISD::isBuildVectorAllOnes(Op.getNode()))
3606 return getOnesVector(Op.getValueType(), DAG, dl);
3607 return getZeroVector(Op.getValueType(), Subtarget->hasSSE2(), DAG, dl);
3610 EVT VT = Op.getValueType();
3611 EVT ExtVT = VT.getVectorElementType();
3612 unsigned EVTBits = ExtVT.getSizeInBits();
3614 unsigned NumElems = Op.getNumOperands();
3615 unsigned NumZero = 0;
3616 unsigned NumNonZero = 0;
3617 unsigned NonZeros = 0;
3618 bool IsAllConstants = true;
3619 SmallSet<SDValue, 8> Values;
3620 for (unsigned i = 0; i < NumElems; ++i) {
3621 SDValue Elt = Op.getOperand(i);
3622 if (Elt.getOpcode() == ISD::UNDEF)
3625 if (Elt.getOpcode() != ISD::Constant &&
3626 Elt.getOpcode() != ISD::ConstantFP)
3627 IsAllConstants = false;
3628 if (X86::isZeroNode(Elt))
3631 NonZeros |= (1 << i);
3636 if (NumNonZero == 0) {
3637 // All undef vector. Return an UNDEF. All zero vectors were handled above.
3638 return DAG.getUNDEF(VT);
3641 // Special case for single non-zero, non-undef, element.
3642 if (NumNonZero == 1) {
3643 unsigned Idx = CountTrailingZeros_32(NonZeros);
3644 SDValue Item = Op.getOperand(Idx);
3646 // If this is an insertion of an i64 value on x86-32, and if the top bits of
3647 // the value are obviously zero, truncate the value to i32 and do the
3648 // insertion that way. Only do this if the value is non-constant or if the
3649 // value is a constant being inserted into element 0. It is cheaper to do
3650 // a constant pool load than it is to do a movd + shuffle.
3651 if (ExtVT == MVT::i64 && !Subtarget->is64Bit() &&
3652 (!IsAllConstants || Idx == 0)) {
3653 if (DAG.MaskedValueIsZero(Item, APInt::getBitsSet(64, 32, 64))) {
3654 // Handle MMX and SSE both.
3655 EVT VecVT = VT == MVT::v2i64 ? MVT::v4i32 : MVT::v2i32;
3656 unsigned VecElts = VT == MVT::v2i64 ? 4 : 2;
3658 // Truncate the value (which may itself be a constant) to i32, and
3659 // convert it to a vector with movd (S2V+shuffle to zero extend).
3660 Item = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Item);
3661 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Item);
3662 Item = getShuffleVectorZeroOrUndef(Item, 0, true,
3663 Subtarget->hasSSE2(), DAG);
3665 // Now we have our 32-bit value zero extended in the low element of
3666 // a vector. If Idx != 0, swizzle it into place.
3668 SmallVector<int, 4> Mask;
3669 Mask.push_back(Idx);
3670 for (unsigned i = 1; i != VecElts; ++i)
3672 Item = DAG.getVectorShuffle(VecVT, dl, Item,
3673 DAG.getUNDEF(Item.getValueType()),
3676 return DAG.getNode(ISD::BIT_CONVERT, dl, Op.getValueType(), Item);
3680 // If we have a constant or non-constant insertion into the low element of
3681 // a vector, we can do this with SCALAR_TO_VECTOR + shuffle of zero into
3682 // the rest of the elements. This will be matched as movd/movq/movss/movsd
3683 // depending on what the source datatype is.
3686 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
3687 } else if (ExtVT == MVT::i32 || ExtVT == MVT::f32 || ExtVT == MVT::f64 ||
3688 (ExtVT == MVT::i64 && Subtarget->is64Bit())) {
3689 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
3690 // Turn it into a MOVL (i.e. movss, movsd, or movd) to a zero vector.
3691 return getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget->hasSSE2(),
3693 } else if (ExtVT == MVT::i16 || ExtVT == MVT::i8) {
3694 Item = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Item);
3695 EVT MiddleVT = VT.getSizeInBits() == 64 ? MVT::v2i32 : MVT::v4i32;
3696 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MiddleVT, Item);
3697 Item = getShuffleVectorZeroOrUndef(Item, 0, true,
3698 Subtarget->hasSSE2(), DAG);
3699 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Item);
3703 // Is it a vector logical left shift?
3704 if (NumElems == 2 && Idx == 1 &&
3705 X86::isZeroNode(Op.getOperand(0)) &&
3706 !X86::isZeroNode(Op.getOperand(1))) {
3707 unsigned NumBits = VT.getSizeInBits();
3708 return getVShift(true, VT,
3709 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
3710 VT, Op.getOperand(1)),
3711 NumBits/2, DAG, *this, dl);
3714 if (IsAllConstants) // Otherwise, it's better to do a constpool load.
3717 // Otherwise, if this is a vector with i32 or f32 elements, and the element
3718 // is a non-constant being inserted into an element other than the low one,
3719 // we can't use a constant pool load. Instead, use SCALAR_TO_VECTOR (aka
3720 // movd/movss) to move this into the low element, then shuffle it into
3722 if (EVTBits == 32) {
3723 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
3725 // Turn it into a shuffle of zero and zero-extended scalar to vector.
3726 Item = getShuffleVectorZeroOrUndef(Item, 0, NumZero > 0,
3727 Subtarget->hasSSE2(), DAG);
3728 SmallVector<int, 8> MaskVec;
3729 for (unsigned i = 0; i < NumElems; i++)
3730 MaskVec.push_back(i == Idx ? 0 : 1);
3731 return DAG.getVectorShuffle(VT, dl, Item, DAG.getUNDEF(VT), &MaskVec[0]);
3735 // Splat is obviously ok. Let legalizer expand it to a shuffle.
3736 if (Values.size() == 1) {
3737 if (EVTBits == 32) {
3738 // Instead of a shuffle like this:
3739 // shuffle (scalar_to_vector (load (ptr + 4))), undef, <0, 0, 0, 0>
3740 // Check if it's possible to issue this instead.
3741 // shuffle (vload ptr)), undef, <1, 1, 1, 1>
3742 unsigned Idx = CountTrailingZeros_32(NonZeros);
3743 SDValue Item = Op.getOperand(Idx);
3744 if (Op.getNode()->isOnlyUserOf(Item.getNode()))
3745 return LowerAsSplatVectorLoad(Item, VT, dl, DAG);
3750 // A vector full of immediates; various special cases are already
3751 // handled, so this is best done with a single constant-pool load.
3755 // Let legalizer expand 2-wide build_vectors.
3756 if (EVTBits == 64) {
3757 if (NumNonZero == 1) {
3758 // One half is zero or undef.
3759 unsigned Idx = CountTrailingZeros_32(NonZeros);
3760 SDValue V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT,
3761 Op.getOperand(Idx));
3762 return getShuffleVectorZeroOrUndef(V2, Idx, true,
3763 Subtarget->hasSSE2(), DAG);
3768 // If element VT is < 32 bits, convert it to inserts into a zero vector.
3769 if (EVTBits == 8 && NumElems == 16) {
3770 SDValue V = LowerBuildVectorv16i8(Op, NonZeros,NumNonZero,NumZero, DAG,
3772 if (V.getNode()) return V;
3775 if (EVTBits == 16 && NumElems == 8) {
3776 SDValue V = LowerBuildVectorv8i16(Op, NonZeros,NumNonZero,NumZero, DAG,
3778 if (V.getNode()) return V;
3781 // If element VT is == 32 bits, turn it into a number of shuffles.
3782 SmallVector<SDValue, 8> V;
3784 if (NumElems == 4 && NumZero > 0) {
3785 for (unsigned i = 0; i < 4; ++i) {
3786 bool isZero = !(NonZeros & (1 << i));
3788 V[i] = getZeroVector(VT, Subtarget->hasSSE2(), DAG, dl);
3790 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
3793 for (unsigned i = 0; i < 2; ++i) {
3794 switch ((NonZeros & (0x3 << i*2)) >> (i*2)) {
3797 V[i] = V[i*2]; // Must be a zero vector.
3800 V[i] = getMOVL(DAG, dl, VT, V[i*2+1], V[i*2]);
3803 V[i] = getMOVL(DAG, dl, VT, V[i*2], V[i*2+1]);
3806 V[i] = getUnpackl(DAG, dl, VT, V[i*2], V[i*2+1]);
3811 SmallVector<int, 8> MaskVec;
3812 bool Reverse = (NonZeros & 0x3) == 2;
3813 for (unsigned i = 0; i < 2; ++i)
3814 MaskVec.push_back(Reverse ? 1-i : i);
3815 Reverse = ((NonZeros & (0x3 << 2)) >> 2) == 2;
3816 for (unsigned i = 0; i < 2; ++i)
3817 MaskVec.push_back(Reverse ? 1-i+NumElems : i+NumElems);
3818 return DAG.getVectorShuffle(VT, dl, V[0], V[1], &MaskVec[0]);
3821 if (Values.size() > 2) {
3822 // If we have SSE 4.1, Expand into a number of inserts unless the number of
3823 // values to be inserted is equal to the number of elements, in which case
3824 // use the unpack code below in the hopes of matching the consecutive elts
3825 // load merge pattern for shuffles.
3826 // FIXME: We could probably just check that here directly.
3827 if (Values.size() < NumElems && VT.getSizeInBits() == 128 &&
3828 getSubtarget()->hasSSE41()) {
3829 V[0] = DAG.getUNDEF(VT);
3830 for (unsigned i = 0; i < NumElems; ++i)
3831 if (Op.getOperand(i).getOpcode() != ISD::UNDEF)
3832 V[0] = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, V[0],
3833 Op.getOperand(i), DAG.getIntPtrConstant(i));
3836 // Expand into a number of unpckl*.
3838 // Step 1: unpcklps 0, 2 ==> X: <?, ?, 2, 0>
3839 // : unpcklps 1, 3 ==> Y: <?, ?, 3, 1>
3840 // Step 2: unpcklps X, Y ==> <3, 2, 1, 0>
3841 for (unsigned i = 0; i < NumElems; ++i)
3842 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
3844 while (NumElems != 0) {
3845 for (unsigned i = 0; i < NumElems; ++i)
3846 V[i] = getUnpackl(DAG, dl, VT, V[i], V[i + NumElems]);
3856 X86TargetLowering::LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
3857 // We support concatenate two MMX registers and place them in a MMX
3858 // register. This is better than doing a stack convert.
3859 DebugLoc dl = Op.getDebugLoc();
3860 EVT ResVT = Op.getValueType();
3861 assert(Op.getNumOperands() == 2);
3862 assert(ResVT == MVT::v2i64 || ResVT == MVT::v4i32 ||
3863 ResVT == MVT::v8i16 || ResVT == MVT::v16i8);
3865 SDValue InVec = DAG.getNode(ISD::BIT_CONVERT,dl, MVT::v1i64, Op.getOperand(0));
3866 SDValue VecOp = DAG.getNode(X86ISD::MOVQ2DQ, dl, MVT::v2i64, InVec);
3867 InVec = Op.getOperand(1);
3868 if (InVec.getOpcode() == ISD::SCALAR_TO_VECTOR) {
3869 unsigned NumElts = ResVT.getVectorNumElements();
3870 VecOp = DAG.getNode(ISD::BIT_CONVERT, dl, ResVT, VecOp);
3871 VecOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, ResVT, VecOp,
3872 InVec.getOperand(0), DAG.getIntPtrConstant(NumElts/2+1));
3874 InVec = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v1i64, InVec);
3875 SDValue VecOp2 = DAG.getNode(X86ISD::MOVQ2DQ, dl, MVT::v2i64, InVec);
3876 Mask[0] = 0; Mask[1] = 2;
3877 VecOp = DAG.getVectorShuffle(MVT::v2i64, dl, VecOp, VecOp2, Mask);
3879 return DAG.getNode(ISD::BIT_CONVERT, dl, ResVT, VecOp);
3882 // v8i16 shuffles - Prefer shuffles in the following order:
3883 // 1. [all] pshuflw, pshufhw, optional move
3884 // 2. [ssse3] 1 x pshufb
3885 // 3. [ssse3] 2 x pshufb + 1 x por
3886 // 4. [all] mov + pshuflw + pshufhw + N x (pextrw + pinsrw)
3888 SDValue LowerVECTOR_SHUFFLEv8i16(ShuffleVectorSDNode *SVOp,
3889 SelectionDAG &DAG, X86TargetLowering &TLI) {
3890 SDValue V1 = SVOp->getOperand(0);
3891 SDValue V2 = SVOp->getOperand(1);
3892 DebugLoc dl = SVOp->getDebugLoc();
3893 SmallVector<int, 8> MaskVals;
3895 // Determine if more than 1 of the words in each of the low and high quadwords
3896 // of the result come from the same quadword of one of the two inputs. Undef
3897 // mask values count as coming from any quadword, for better codegen.
3898 SmallVector<unsigned, 4> LoQuad(4);
3899 SmallVector<unsigned, 4> HiQuad(4);
3900 BitVector InputQuads(4);
3901 for (unsigned i = 0; i < 8; ++i) {
3902 SmallVectorImpl<unsigned> &Quad = i < 4 ? LoQuad : HiQuad;
3903 int EltIdx = SVOp->getMaskElt(i);
3904 MaskVals.push_back(EltIdx);
3913 InputQuads.set(EltIdx / 4);
3916 int BestLoQuad = -1;
3917 unsigned MaxQuad = 1;
3918 for (unsigned i = 0; i < 4; ++i) {
3919 if (LoQuad[i] > MaxQuad) {
3921 MaxQuad = LoQuad[i];
3925 int BestHiQuad = -1;
3927 for (unsigned i = 0; i < 4; ++i) {
3928 if (HiQuad[i] > MaxQuad) {
3930 MaxQuad = HiQuad[i];
3934 // For SSSE3, If all 8 words of the result come from only 1 quadword of each
3935 // of the two input vectors, shuffle them into one input vector so only a
3936 // single pshufb instruction is necessary. If There are more than 2 input
3937 // quads, disable the next transformation since it does not help SSSE3.
3938 bool V1Used = InputQuads[0] || InputQuads[1];
3939 bool V2Used = InputQuads[2] || InputQuads[3];
3940 if (TLI.getSubtarget()->hasSSSE3()) {
3941 if (InputQuads.count() == 2 && V1Used && V2Used) {
3942 BestLoQuad = InputQuads.find_first();
3943 BestHiQuad = InputQuads.find_next(BestLoQuad);
3945 if (InputQuads.count() > 2) {
3951 // If BestLoQuad or BestHiQuad are set, shuffle the quads together and update
3952 // the shuffle mask. If a quad is scored as -1, that means that it contains
3953 // words from all 4 input quadwords.
3955 if (BestLoQuad >= 0 || BestHiQuad >= 0) {
3956 SmallVector<int, 8> MaskV;
3957 MaskV.push_back(BestLoQuad < 0 ? 0 : BestLoQuad);
3958 MaskV.push_back(BestHiQuad < 0 ? 1 : BestHiQuad);
3959 NewV = DAG.getVectorShuffle(MVT::v2i64, dl,
3960 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2i64, V1),
3961 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2i64, V2), &MaskV[0]);
3962 NewV = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v8i16, NewV);
3964 // Rewrite the MaskVals and assign NewV to V1 if NewV now contains all the
3965 // source words for the shuffle, to aid later transformations.
3966 bool AllWordsInNewV = true;
3967 bool InOrder[2] = { true, true };
3968 for (unsigned i = 0; i != 8; ++i) {
3969 int idx = MaskVals[i];
3971 InOrder[i/4] = false;
3972 if (idx < 0 || (idx/4) == BestLoQuad || (idx/4) == BestHiQuad)
3974 AllWordsInNewV = false;
3978 bool pshuflw = AllWordsInNewV, pshufhw = AllWordsInNewV;
3979 if (AllWordsInNewV) {
3980 for (int i = 0; i != 8; ++i) {
3981 int idx = MaskVals[i];
3984 idx = MaskVals[i] = (idx / 4) == BestLoQuad ? (idx & 3) : (idx & 3) + 4;
3985 if ((idx != i) && idx < 4)
3987 if ((idx != i) && idx > 3)
3996 // If we've eliminated the use of V2, and the new mask is a pshuflw or
3997 // pshufhw, that's as cheap as it gets. Return the new shuffle.
3998 if ((pshufhw && InOrder[0]) || (pshuflw && InOrder[1])) {
3999 return DAG.getVectorShuffle(MVT::v8i16, dl, NewV,
4000 DAG.getUNDEF(MVT::v8i16), &MaskVals[0]);
4004 // If we have SSSE3, and all words of the result are from 1 input vector,
4005 // case 2 is generated, otherwise case 3 is generated. If no SSSE3
4006 // is present, fall back to case 4.
4007 if (TLI.getSubtarget()->hasSSSE3()) {
4008 SmallVector<SDValue,16> pshufbMask;
4010 // If we have elements from both input vectors, set the high bit of the
4011 // shuffle mask element to zero out elements that come from V2 in the V1
4012 // mask, and elements that come from V1 in the V2 mask, so that the two
4013 // results can be OR'd together.
4014 bool TwoInputs = V1Used && V2Used;
4015 for (unsigned i = 0; i != 8; ++i) {
4016 int EltIdx = MaskVals[i] * 2;
4017 if (TwoInputs && (EltIdx >= 16)) {
4018 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
4019 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
4022 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
4023 pshufbMask.push_back(DAG.getConstant(EltIdx+1, MVT::i8));
4025 V1 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v16i8, V1);
4026 V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1,
4027 DAG.getNode(ISD::BUILD_VECTOR, dl,
4028 MVT::v16i8, &pshufbMask[0], 16));
4030 return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v8i16, V1);
4032 // Calculate the shuffle mask for the second input, shuffle it, and
4033 // OR it with the first shuffled input.
4035 for (unsigned i = 0; i != 8; ++i) {
4036 int EltIdx = MaskVals[i] * 2;
4038 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
4039 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
4042 pshufbMask.push_back(DAG.getConstant(EltIdx - 16, MVT::i8));
4043 pshufbMask.push_back(DAG.getConstant(EltIdx - 15, MVT::i8));
4045 V2 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v16i8, V2);
4046 V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2,
4047 DAG.getNode(ISD::BUILD_VECTOR, dl,
4048 MVT::v16i8, &pshufbMask[0], 16));
4049 V1 = DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
4050 return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v8i16, V1);
4053 // If BestLoQuad >= 0, generate a pshuflw to put the low elements in order,
4054 // and update MaskVals with new element order.
4055 BitVector InOrder(8);
4056 if (BestLoQuad >= 0) {
4057 SmallVector<int, 8> MaskV;
4058 for (int i = 0; i != 4; ++i) {
4059 int idx = MaskVals[i];
4061 MaskV.push_back(-1);
4063 } else if ((idx / 4) == BestLoQuad) {
4064 MaskV.push_back(idx & 3);
4067 MaskV.push_back(-1);
4070 for (unsigned i = 4; i != 8; ++i)
4072 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16),
4076 // If BestHi >= 0, generate a pshufhw to put the high elements in order,
4077 // and update MaskVals with the new element order.
4078 if (BestHiQuad >= 0) {
4079 SmallVector<int, 8> MaskV;
4080 for (unsigned i = 0; i != 4; ++i)
4082 for (unsigned i = 4; i != 8; ++i) {
4083 int idx = MaskVals[i];
4085 MaskV.push_back(-1);
4087 } else if ((idx / 4) == BestHiQuad) {
4088 MaskV.push_back((idx & 3) + 4);
4091 MaskV.push_back(-1);
4094 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16),
4098 // In case BestHi & BestLo were both -1, which means each quadword has a word
4099 // from each of the four input quadwords, calculate the InOrder bitvector now
4100 // before falling through to the insert/extract cleanup.
4101 if (BestLoQuad == -1 && BestHiQuad == -1) {
4103 for (int i = 0; i != 8; ++i)
4104 if (MaskVals[i] < 0 || MaskVals[i] == i)
4108 // The other elements are put in the right place using pextrw and pinsrw.
4109 for (unsigned i = 0; i != 8; ++i) {
4112 int EltIdx = MaskVals[i];
4115 SDValue ExtOp = (EltIdx < 8)
4116 ? DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V1,
4117 DAG.getIntPtrConstant(EltIdx))
4118 : DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V2,
4119 DAG.getIntPtrConstant(EltIdx - 8));
4120 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, ExtOp,
4121 DAG.getIntPtrConstant(i));
4126 // v16i8 shuffles - Prefer shuffles in the following order:
4127 // 1. [ssse3] 1 x pshufb
4128 // 2. [ssse3] 2 x pshufb + 1 x por
4129 // 3. [all] v8i16 shuffle + N x pextrw + rotate + pinsrw
4131 SDValue LowerVECTOR_SHUFFLEv16i8(ShuffleVectorSDNode *SVOp,
4132 SelectionDAG &DAG, X86TargetLowering &TLI) {
4133 SDValue V1 = SVOp->getOperand(0);
4134 SDValue V2 = SVOp->getOperand(1);
4135 DebugLoc dl = SVOp->getDebugLoc();
4136 SmallVector<int, 16> MaskVals;
4137 SVOp->getMask(MaskVals);
4139 // If we have SSSE3, case 1 is generated when all result bytes come from
4140 // one of the inputs. Otherwise, case 2 is generated. If no SSSE3 is
4141 // present, fall back to case 3.
4142 // FIXME: kill V2Only once shuffles are canonizalized by getNode.
4145 for (unsigned i = 0; i < 16; ++i) {
4146 int EltIdx = MaskVals[i];
4155 // If SSSE3, use 1 pshufb instruction per vector with elements in the result.
4156 if (TLI.getSubtarget()->hasSSSE3()) {
4157 SmallVector<SDValue,16> pshufbMask;
4159 // If all result elements are from one input vector, then only translate
4160 // undef mask values to 0x80 (zero out result) in the pshufb mask.
4162 // Otherwise, we have elements from both input vectors, and must zero out
4163 // elements that come from V2 in the first mask, and V1 in the second mask
4164 // so that we can OR them together.
4165 bool TwoInputs = !(V1Only || V2Only);
4166 for (unsigned i = 0; i != 16; ++i) {
4167 int EltIdx = MaskVals[i];
4168 if (EltIdx < 0 || (TwoInputs && EltIdx >= 16)) {
4169 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
4172 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
4174 // If all the elements are from V2, assign it to V1 and return after
4175 // building the first pshufb.
4178 V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1,
4179 DAG.getNode(ISD::BUILD_VECTOR, dl,
4180 MVT::v16i8, &pshufbMask[0], 16));
4184 // Calculate the shuffle mask for the second input, shuffle it, and
4185 // OR it with the first shuffled input.
4187 for (unsigned i = 0; i != 16; ++i) {
4188 int EltIdx = MaskVals[i];
4190 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
4193 pshufbMask.push_back(DAG.getConstant(EltIdx - 16, MVT::i8));
4195 V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2,
4196 DAG.getNode(ISD::BUILD_VECTOR, dl,
4197 MVT::v16i8, &pshufbMask[0], 16));
4198 return DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
4201 // No SSSE3 - Calculate in place words and then fix all out of place words
4202 // With 0-16 extracts & inserts. Worst case is 16 bytes out of order from
4203 // the 16 different words that comprise the two doublequadword input vectors.
4204 V1 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v8i16, V1);
4205 V2 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v8i16, V2);
4206 SDValue NewV = V2Only ? V2 : V1;
4207 for (int i = 0; i != 8; ++i) {
4208 int Elt0 = MaskVals[i*2];
4209 int Elt1 = MaskVals[i*2+1];
4211 // This word of the result is all undef, skip it.
4212 if (Elt0 < 0 && Elt1 < 0)
4215 // This word of the result is already in the correct place, skip it.
4216 if (V1Only && (Elt0 == i*2) && (Elt1 == i*2+1))
4218 if (V2Only && (Elt0 == i*2+16) && (Elt1 == i*2+17))
4221 SDValue Elt0Src = Elt0 < 16 ? V1 : V2;
4222 SDValue Elt1Src = Elt1 < 16 ? V1 : V2;
4225 // If Elt0 and Elt1 are defined, are consecutive, and can be load
4226 // using a single extract together, load it and store it.
4227 if ((Elt0 >= 0) && ((Elt0 + 1) == Elt1) && ((Elt0 & 1) == 0)) {
4228 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src,
4229 DAG.getIntPtrConstant(Elt1 / 2));
4230 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt,
4231 DAG.getIntPtrConstant(i));
4235 // If Elt1 is defined, extract it from the appropriate source. If the
4236 // source byte is not also odd, shift the extracted word left 8 bits
4237 // otherwise clear the bottom 8 bits if we need to do an or.
4239 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src,
4240 DAG.getIntPtrConstant(Elt1 / 2));
4241 if ((Elt1 & 1) == 0)
4242 InsElt = DAG.getNode(ISD::SHL, dl, MVT::i16, InsElt,
4243 DAG.getConstant(8, TLI.getShiftAmountTy()));
4245 InsElt = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt,
4246 DAG.getConstant(0xFF00, MVT::i16));
4248 // If Elt0 is defined, extract it from the appropriate source. If the
4249 // source byte is not also even, shift the extracted word right 8 bits. If
4250 // Elt1 was also defined, OR the extracted values together before
4251 // inserting them in the result.
4253 SDValue InsElt0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16,
4254 Elt0Src, DAG.getIntPtrConstant(Elt0 / 2));
4255 if ((Elt0 & 1) != 0)
4256 InsElt0 = DAG.getNode(ISD::SRL, dl, MVT::i16, InsElt0,
4257 DAG.getConstant(8, TLI.getShiftAmountTy()));
4259 InsElt0 = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt0,
4260 DAG.getConstant(0x00FF, MVT::i16));
4261 InsElt = Elt1 >= 0 ? DAG.getNode(ISD::OR, dl, MVT::i16, InsElt, InsElt0)
4264 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt,
4265 DAG.getIntPtrConstant(i));
4267 return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v16i8, NewV);
4270 /// RewriteAsNarrowerShuffle - Try rewriting v8i16 and v16i8 shuffles as 4 wide
4271 /// ones, or rewriting v4i32 / v2f32 as 2 wide ones if possible. This can be
4272 /// done when every pair / quad of shuffle mask elements point to elements in
4273 /// the right sequence. e.g.
4274 /// vector_shuffle <>, <>, < 3, 4, | 10, 11, | 0, 1, | 14, 15>
4276 SDValue RewriteAsNarrowerShuffle(ShuffleVectorSDNode *SVOp,
4278 TargetLowering &TLI, DebugLoc dl) {
4279 EVT VT = SVOp->getValueType(0);
4280 SDValue V1 = SVOp->getOperand(0);
4281 SDValue V2 = SVOp->getOperand(1);
4282 unsigned NumElems = VT.getVectorNumElements();
4283 unsigned NewWidth = (NumElems == 4) ? 2 : 4;
4284 EVT MaskVT = MVT::getIntVectorWithNumElements(NewWidth);
4285 EVT MaskEltVT = MaskVT.getVectorElementType();
4287 switch (VT.getSimpleVT().SimpleTy) {
4288 default: assert(false && "Unexpected!");
4289 case MVT::v4f32: NewVT = MVT::v2f64; break;
4290 case MVT::v4i32: NewVT = MVT::v2i64; break;
4291 case MVT::v8i16: NewVT = MVT::v4i32; break;
4292 case MVT::v16i8: NewVT = MVT::v4i32; break;
4295 if (NewWidth == 2) {
4301 int Scale = NumElems / NewWidth;
4302 SmallVector<int, 8> MaskVec;
4303 for (unsigned i = 0; i < NumElems; i += Scale) {
4305 for (int j = 0; j < Scale; ++j) {
4306 int EltIdx = SVOp->getMaskElt(i+j);
4310 StartIdx = EltIdx - (EltIdx % Scale);
4311 if (EltIdx != StartIdx + j)
4315 MaskVec.push_back(-1);
4317 MaskVec.push_back(StartIdx / Scale);
4320 V1 = DAG.getNode(ISD::BIT_CONVERT, dl, NewVT, V1);
4321 V2 = DAG.getNode(ISD::BIT_CONVERT, dl, NewVT, V2);
4322 return DAG.getVectorShuffle(NewVT, dl, V1, V2, &MaskVec[0]);
4325 /// getVZextMovL - Return a zero-extending vector move low node.
4327 static SDValue getVZextMovL(EVT VT, EVT OpVT,
4328 SDValue SrcOp, SelectionDAG &DAG,
4329 const X86Subtarget *Subtarget, DebugLoc dl) {
4330 if (VT == MVT::v2f64 || VT == MVT::v4f32) {
4331 LoadSDNode *LD = NULL;
4332 if (!isScalarLoadToVector(SrcOp.getNode(), &LD))
4333 LD = dyn_cast<LoadSDNode>(SrcOp);
4335 // movssrr and movsdrr do not clear top bits. Try to use movd, movq
4337 MVT ExtVT = (OpVT == MVT::v2f64) ? MVT::i64 : MVT::i32;
4338 if ((ExtVT.SimpleTy != MVT::i64 || Subtarget->is64Bit()) &&
4339 SrcOp.getOpcode() == ISD::SCALAR_TO_VECTOR &&
4340 SrcOp.getOperand(0).getOpcode() == ISD::BIT_CONVERT &&
4341 SrcOp.getOperand(0).getOperand(0).getValueType() == ExtVT) {
4343 OpVT = (OpVT == MVT::v2f64) ? MVT::v2i64 : MVT::v4i32;
4344 return DAG.getNode(ISD::BIT_CONVERT, dl, VT,
4345 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT,
4346 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
4354 return DAG.getNode(ISD::BIT_CONVERT, dl, VT,
4355 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT,
4356 DAG.getNode(ISD::BIT_CONVERT, dl,
4360 /// LowerVECTOR_SHUFFLE_4wide - Handle all 4 wide cases with a number of
4363 LowerVECTOR_SHUFFLE_4wide(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
4364 SDValue V1 = SVOp->getOperand(0);
4365 SDValue V2 = SVOp->getOperand(1);
4366 DebugLoc dl = SVOp->getDebugLoc();
4367 EVT VT = SVOp->getValueType(0);
4369 SmallVector<std::pair<int, int>, 8> Locs;
4371 SmallVector<int, 8> Mask1(4U, -1);
4372 SmallVector<int, 8> PermMask;
4373 SVOp->getMask(PermMask);
4377 for (unsigned i = 0; i != 4; ++i) {
4378 int Idx = PermMask[i];
4380 Locs[i] = std::make_pair(-1, -1);
4382 assert(Idx < 8 && "Invalid VECTOR_SHUFFLE index!");
4384 Locs[i] = std::make_pair(0, NumLo);
4388 Locs[i] = std::make_pair(1, NumHi);
4390 Mask1[2+NumHi] = Idx;
4396 if (NumLo <= 2 && NumHi <= 2) {
4397 // If no more than two elements come from either vector. This can be
4398 // implemented with two shuffles. First shuffle gather the elements.
4399 // The second shuffle, which takes the first shuffle as both of its
4400 // vector operands, put the elements into the right order.
4401 V1 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
4403 SmallVector<int, 8> Mask2(4U, -1);
4405 for (unsigned i = 0; i != 4; ++i) {
4406 if (Locs[i].first == -1)
4409 unsigned Idx = (i < 2) ? 0 : 4;
4410 Idx += Locs[i].first * 2 + Locs[i].second;
4415 return DAG.getVectorShuffle(VT, dl, V1, V1, &Mask2[0]);
4416 } else if (NumLo == 3 || NumHi == 3) {
4417 // Otherwise, we must have three elements from one vector, call it X, and
4418 // one element from the other, call it Y. First, use a shufps to build an
4419 // intermediate vector with the one element from Y and the element from X
4420 // that will be in the same half in the final destination (the indexes don't
4421 // matter). Then, use a shufps to build the final vector, taking the half
4422 // containing the element from Y from the intermediate, and the other half
4425 // Normalize it so the 3 elements come from V1.
4426 CommuteVectorShuffleMask(PermMask, VT);
4430 // Find the element from V2.
4432 for (HiIndex = 0; HiIndex < 3; ++HiIndex) {
4433 int Val = PermMask[HiIndex];
4440 Mask1[0] = PermMask[HiIndex];
4442 Mask1[2] = PermMask[HiIndex^1];
4444 V2 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
4447 Mask1[0] = PermMask[0];
4448 Mask1[1] = PermMask[1];
4449 Mask1[2] = HiIndex & 1 ? 6 : 4;
4450 Mask1[3] = HiIndex & 1 ? 4 : 6;
4451 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
4453 Mask1[0] = HiIndex & 1 ? 2 : 0;
4454 Mask1[1] = HiIndex & 1 ? 0 : 2;
4455 Mask1[2] = PermMask[2];
4456 Mask1[3] = PermMask[3];
4461 return DAG.getVectorShuffle(VT, dl, V2, V1, &Mask1[0]);
4465 // Break it into (shuffle shuffle_hi, shuffle_lo).
4467 SmallVector<int,8> LoMask(4U, -1);
4468 SmallVector<int,8> HiMask(4U, -1);
4470 SmallVector<int,8> *MaskPtr = &LoMask;
4471 unsigned MaskIdx = 0;
4474 for (unsigned i = 0; i != 4; ++i) {
4481 int Idx = PermMask[i];
4483 Locs[i] = std::make_pair(-1, -1);
4484 } else if (Idx < 4) {
4485 Locs[i] = std::make_pair(MaskIdx, LoIdx);
4486 (*MaskPtr)[LoIdx] = Idx;
4489 Locs[i] = std::make_pair(MaskIdx, HiIdx);
4490 (*MaskPtr)[HiIdx] = Idx;
4495 SDValue LoShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &LoMask[0]);
4496 SDValue HiShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &HiMask[0]);
4497 SmallVector<int, 8> MaskOps;
4498 for (unsigned i = 0; i != 4; ++i) {
4499 if (Locs[i].first == -1) {
4500 MaskOps.push_back(-1);
4502 unsigned Idx = Locs[i].first * 4 + Locs[i].second;
4503 MaskOps.push_back(Idx);
4506 return DAG.getVectorShuffle(VT, dl, LoShuffle, HiShuffle, &MaskOps[0]);
4510 X86TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) {
4511 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
4512 SDValue V1 = Op.getOperand(0);
4513 SDValue V2 = Op.getOperand(1);
4514 EVT VT = Op.getValueType();
4515 DebugLoc dl = Op.getDebugLoc();
4516 unsigned NumElems = VT.getVectorNumElements();
4517 bool isMMX = VT.getSizeInBits() == 64;
4518 bool V1IsUndef = V1.getOpcode() == ISD::UNDEF;
4519 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
4520 bool V1IsSplat = false;
4521 bool V2IsSplat = false;
4523 if (isZeroShuffle(SVOp))
4524 return getZeroVector(VT, Subtarget->hasSSE2(), DAG, dl);
4526 // Promote splats to v4f32.
4527 if (SVOp->isSplat()) {
4528 if (isMMX || NumElems < 4)
4530 return PromoteSplat(SVOp, DAG, Subtarget->hasSSE2());
4533 // If the shuffle can be profitably rewritten as a narrower shuffle, then
4535 if (VT == MVT::v8i16 || VT == MVT::v16i8) {
4536 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG, *this, dl);
4537 if (NewOp.getNode())
4538 return DAG.getNode(ISD::BIT_CONVERT, dl, VT,
4539 LowerVECTOR_SHUFFLE(NewOp, DAG));
4540 } else if ((VT == MVT::v4i32 || (VT == MVT::v4f32 && Subtarget->hasSSE2()))) {
4541 // FIXME: Figure out a cleaner way to do this.
4542 // Try to make use of movq to zero out the top part.
4543 if (ISD::isBuildVectorAllZeros(V2.getNode())) {
4544 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG, *this, dl);
4545 if (NewOp.getNode()) {
4546 if (isCommutedMOVL(cast<ShuffleVectorSDNode>(NewOp), true, false))
4547 return getVZextMovL(VT, NewOp.getValueType(), NewOp.getOperand(0),
4548 DAG, Subtarget, dl);
4550 } else if (ISD::isBuildVectorAllZeros(V1.getNode())) {
4551 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG, *this, dl);
4552 if (NewOp.getNode() && X86::isMOVLMask(cast<ShuffleVectorSDNode>(NewOp)))
4553 return getVZextMovL(VT, NewOp.getValueType(), NewOp.getOperand(1),
4554 DAG, Subtarget, dl);
4558 if (X86::isPSHUFDMask(SVOp))
4561 // Check if this can be converted into a logical shift.
4562 bool isLeft = false;
4565 bool isShift = getSubtarget()->hasSSE2() &&
4566 isVectorShift(SVOp, DAG, isLeft, ShVal, ShAmt);
4567 if (isShift && ShVal.hasOneUse()) {
4568 // If the shifted value has multiple uses, it may be cheaper to use
4569 // v_set0 + movlhps or movhlps, etc.
4570 EVT EltVT = VT.getVectorElementType();
4571 ShAmt *= EltVT.getSizeInBits();
4572 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl);
4575 if (X86::isMOVLMask(SVOp)) {
4578 if (ISD::isBuildVectorAllZeros(V1.getNode()))
4579 return getVZextMovL(VT, VT, V2, DAG, Subtarget, dl);
4584 // FIXME: fold these into legal mask.
4585 if (!isMMX && (X86::isMOVSHDUPMask(SVOp) ||
4586 X86::isMOVSLDUPMask(SVOp) ||
4587 X86::isMOVHLPSMask(SVOp) ||
4588 X86::isMOVLHPSMask(SVOp) ||
4589 X86::isMOVLPMask(SVOp)))
4592 if (ShouldXformToMOVHLPS(SVOp) ||
4593 ShouldXformToMOVLP(V1.getNode(), V2.getNode(), SVOp))
4594 return CommuteVectorShuffle(SVOp, DAG);
4597 // No better options. Use a vshl / vsrl.
4598 EVT EltVT = VT.getVectorElementType();
4599 ShAmt *= EltVT.getSizeInBits();
4600 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl);
4603 bool Commuted = false;
4604 // FIXME: This should also accept a bitcast of a splat? Be careful, not
4605 // 1,1,1,1 -> v8i16 though.
4606 V1IsSplat = isSplatVector(V1.getNode());
4607 V2IsSplat = isSplatVector(V2.getNode());
4609 // Canonicalize the splat or undef, if present, to be on the RHS.
4610 if ((V1IsSplat || V1IsUndef) && !(V2IsSplat || V2IsUndef)) {
4611 Op = CommuteVectorShuffle(SVOp, DAG);
4612 SVOp = cast<ShuffleVectorSDNode>(Op);
4613 V1 = SVOp->getOperand(0);
4614 V2 = SVOp->getOperand(1);
4615 std::swap(V1IsSplat, V2IsSplat);
4616 std::swap(V1IsUndef, V2IsUndef);
4620 if (isCommutedMOVL(SVOp, V2IsSplat, V2IsUndef)) {
4621 // Shuffling low element of v1 into undef, just return v1.
4624 // If V2 is a splat, the mask may be malformed such as <4,3,3,3>, which
4625 // the instruction selector will not match, so get a canonical MOVL with
4626 // swapped operands to undo the commute.
4627 return getMOVL(DAG, dl, VT, V2, V1);
4630 if (X86::isUNPCKL_v_undef_Mask(SVOp) ||
4631 X86::isUNPCKH_v_undef_Mask(SVOp) ||
4632 X86::isUNPCKLMask(SVOp) ||
4633 X86::isUNPCKHMask(SVOp))
4637 // Normalize mask so all entries that point to V2 points to its first
4638 // element then try to match unpck{h|l} again. If match, return a
4639 // new vector_shuffle with the corrected mask.
4640 SDValue NewMask = NormalizeMask(SVOp, DAG);
4641 ShuffleVectorSDNode *NSVOp = cast<ShuffleVectorSDNode>(NewMask);
4642 if (NSVOp != SVOp) {
4643 if (X86::isUNPCKLMask(NSVOp, true)) {
4645 } else if (X86::isUNPCKHMask(NSVOp, true)) {
4652 // Commute is back and try unpck* again.
4653 // FIXME: this seems wrong.
4654 SDValue NewOp = CommuteVectorShuffle(SVOp, DAG);
4655 ShuffleVectorSDNode *NewSVOp = cast<ShuffleVectorSDNode>(NewOp);
4656 if (X86::isUNPCKL_v_undef_Mask(NewSVOp) ||
4657 X86::isUNPCKH_v_undef_Mask(NewSVOp) ||
4658 X86::isUNPCKLMask(NewSVOp) ||
4659 X86::isUNPCKHMask(NewSVOp))
4663 // FIXME: for mmx, bitcast v2i32 to v4i16 for shuffle.
4665 // Normalize the node to match x86 shuffle ops if needed
4666 if (!isMMX && V2.getOpcode() != ISD::UNDEF && isCommutedSHUFP(SVOp))
4667 return CommuteVectorShuffle(SVOp, DAG);
4669 // Check for legal shuffle and return?
4670 SmallVector<int, 16> PermMask;
4671 SVOp->getMask(PermMask);
4672 if (isShuffleMaskLegal(PermMask, VT))
4675 // Handle v8i16 specifically since SSE can do byte extraction and insertion.
4676 if (VT == MVT::v8i16) {
4677 SDValue NewOp = LowerVECTOR_SHUFFLEv8i16(SVOp, DAG, *this);
4678 if (NewOp.getNode())
4682 if (VT == MVT::v16i8) {
4683 SDValue NewOp = LowerVECTOR_SHUFFLEv16i8(SVOp, DAG, *this);
4684 if (NewOp.getNode())
4688 // Handle all 4 wide cases with a number of shuffles except for MMX.
4689 if (NumElems == 4 && !isMMX)
4690 return LowerVECTOR_SHUFFLE_4wide(SVOp, DAG);
4696 X86TargetLowering::LowerEXTRACT_VECTOR_ELT_SSE4(SDValue Op,
4697 SelectionDAG &DAG) {
4698 EVT VT = Op.getValueType();
4699 DebugLoc dl = Op.getDebugLoc();
4700 if (VT.getSizeInBits() == 8) {
4701 SDValue Extract = DAG.getNode(X86ISD::PEXTRB, dl, MVT::i32,
4702 Op.getOperand(0), Op.getOperand(1));
4703 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
4704 DAG.getValueType(VT));
4705 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
4706 } else if (VT.getSizeInBits() == 16) {
4707 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
4708 // If Idx is 0, it's cheaper to do a move instead of a pextrw.
4710 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
4711 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
4712 DAG.getNode(ISD::BIT_CONVERT, dl,
4716 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, MVT::i32,
4717 Op.getOperand(0), Op.getOperand(1));
4718 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
4719 DAG.getValueType(VT));
4720 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
4721 } else if (VT == MVT::f32) {
4722 // EXTRACTPS outputs to a GPR32 register which will require a movd to copy
4723 // the result back to FR32 register. It's only worth matching if the
4724 // result has a single use which is a store or a bitcast to i32. And in
4725 // the case of a store, it's not worth it if the index is a constant 0,
4726 // because a MOVSSmr can be used instead, which is smaller and faster.
4727 if (!Op.hasOneUse())
4729 SDNode *User = *Op.getNode()->use_begin();
4730 if ((User->getOpcode() != ISD::STORE ||
4731 (isa<ConstantSDNode>(Op.getOperand(1)) &&
4732 cast<ConstantSDNode>(Op.getOperand(1))->isNullValue())) &&
4733 (User->getOpcode() != ISD::BIT_CONVERT ||
4734 User->getValueType(0) != MVT::i32))
4736 SDValue Extract = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
4737 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v4i32,
4740 return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, Extract);
4741 } else if (VT == MVT::i32) {
4742 // ExtractPS works with constant index.
4743 if (isa<ConstantSDNode>(Op.getOperand(1)))
4751 X86TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) {
4752 if (!isa<ConstantSDNode>(Op.getOperand(1)))
4755 if (Subtarget->hasSSE41()) {
4756 SDValue Res = LowerEXTRACT_VECTOR_ELT_SSE4(Op, DAG);
4761 EVT VT = Op.getValueType();
4762 DebugLoc dl = Op.getDebugLoc();
4763 // TODO: handle v16i8.
4764 if (VT.getSizeInBits() == 16) {
4765 SDValue Vec = Op.getOperand(0);
4766 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
4768 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
4769 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
4770 DAG.getNode(ISD::BIT_CONVERT, dl,
4773 // Transform it so it match pextrw which produces a 32-bit result.
4774 EVT EltVT = MVT::i32;
4775 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, EltVT,
4776 Op.getOperand(0), Op.getOperand(1));
4777 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, EltVT, Extract,
4778 DAG.getValueType(VT));
4779 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
4780 } else if (VT.getSizeInBits() == 32) {
4781 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
4785 // SHUFPS the element to the lowest double word, then movss.
4786 int Mask[4] = { Idx, -1, -1, -1 };
4787 EVT VVT = Op.getOperand(0).getValueType();
4788 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
4789 DAG.getUNDEF(VVT), Mask);
4790 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
4791 DAG.getIntPtrConstant(0));
4792 } else if (VT.getSizeInBits() == 64) {
4793 // FIXME: .td only matches this for <2 x f64>, not <2 x i64> on 32b
4794 // FIXME: seems like this should be unnecessary if mov{h,l}pd were taught
4795 // to match extract_elt for f64.
4796 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
4800 // UNPCKHPD the element to the lowest double word, then movsd.
4801 // Note if the lower 64 bits of the result of the UNPCKHPD is then stored
4802 // to a f64mem, the whole operation is folded into a single MOVHPDmr.
4803 int Mask[2] = { 1, -1 };
4804 EVT VVT = Op.getOperand(0).getValueType();
4805 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
4806 DAG.getUNDEF(VVT), Mask);
4807 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
4808 DAG.getIntPtrConstant(0));
4815 X86TargetLowering::LowerINSERT_VECTOR_ELT_SSE4(SDValue Op, SelectionDAG &DAG){
4816 EVT VT = Op.getValueType();
4817 EVT EltVT = VT.getVectorElementType();
4818 DebugLoc dl = Op.getDebugLoc();
4820 SDValue N0 = Op.getOperand(0);
4821 SDValue N1 = Op.getOperand(1);
4822 SDValue N2 = Op.getOperand(2);
4824 if ((EltVT.getSizeInBits() == 8 || EltVT.getSizeInBits() == 16) &&
4825 isa<ConstantSDNode>(N2)) {
4827 if (VT == MVT::v8i16)
4828 Opc = X86ISD::PINSRW;
4829 else if (VT == MVT::v4i16)
4830 Opc = X86ISD::MMX_PINSRW;
4831 else if (VT == MVT::v16i8)
4832 Opc = X86ISD::PINSRB;
4834 Opc = X86ISD::PINSRB;
4836 // Transform it so it match pinsr{b,w} which expects a GR32 as its second
4838 if (N1.getValueType() != MVT::i32)
4839 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
4840 if (N2.getValueType() != MVT::i32)
4841 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue());
4842 return DAG.getNode(Opc, dl, VT, N0, N1, N2);
4843 } else if (EltVT == MVT::f32 && isa<ConstantSDNode>(N2)) {
4844 // Bits [7:6] of the constant are the source select. This will always be
4845 // zero here. The DAG Combiner may combine an extract_elt index into these
4846 // bits. For example (insert (extract, 3), 2) could be matched by putting
4847 // the '3' into bits [7:6] of X86ISD::INSERTPS.
4848 // Bits [5:4] of the constant are the destination select. This is the
4849 // value of the incoming immediate.
4850 // Bits [3:0] of the constant are the zero mask. The DAG Combiner may
4851 // combine either bitwise AND or insert of float 0.0 to set these bits.
4852 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue() << 4);
4853 // Create this as a scalar to vector..
4854 N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4f32, N1);
4855 return DAG.getNode(X86ISD::INSERTPS, dl, VT, N0, N1, N2);
4856 } else if (EltVT == MVT::i32 && isa<ConstantSDNode>(N2)) {
4857 // PINSR* works with constant index.
4864 X86TargetLowering::LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) {
4865 EVT VT = Op.getValueType();
4866 EVT EltVT = VT.getVectorElementType();
4868 if (Subtarget->hasSSE41())
4869 return LowerINSERT_VECTOR_ELT_SSE4(Op, DAG);
4871 if (EltVT == MVT::i8)
4874 DebugLoc dl = Op.getDebugLoc();
4875 SDValue N0 = Op.getOperand(0);
4876 SDValue N1 = Op.getOperand(1);
4877 SDValue N2 = Op.getOperand(2);
4879 if (EltVT.getSizeInBits() == 16 && isa<ConstantSDNode>(N2)) {
4880 // Transform it so it match pinsrw which expects a 16-bit value in a GR32
4881 // as its second argument.
4882 if (N1.getValueType() != MVT::i32)
4883 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
4884 if (N2.getValueType() != MVT::i32)
4885 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue());
4886 return DAG.getNode(VT == MVT::v8i16 ? X86ISD::PINSRW : X86ISD::MMX_PINSRW,
4887 dl, VT, N0, N1, N2);
4893 X86TargetLowering::LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) {
4894 DebugLoc dl = Op.getDebugLoc();
4895 if (Op.getValueType() == MVT::v2f32)
4896 return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2f32,
4897 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i32,
4898 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32,
4899 Op.getOperand(0))));
4901 if (Op.getValueType() == MVT::v1i64 && Op.getOperand(0).getValueType() == MVT::i64)
4902 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v1i64, Op.getOperand(0));
4904 SDValue AnyExt = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, Op.getOperand(0));
4905 EVT VT = MVT::v2i32;
4906 switch (Op.getValueType().getSimpleVT().SimpleTy) {
4913 return DAG.getNode(ISD::BIT_CONVERT, dl, Op.getValueType(),
4914 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, AnyExt));
4917 // ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as
4918 // their target countpart wrapped in the X86ISD::Wrapper node. Suppose N is
4919 // one of the above mentioned nodes. It has to be wrapped because otherwise
4920 // Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only
4921 // be used to form addressing mode. These wrapped nodes will be selected
4924 X86TargetLowering::LowerConstantPool(SDValue Op, SelectionDAG &DAG) {
4925 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
4927 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
4929 unsigned char OpFlag = 0;
4930 unsigned WrapperKind = X86ISD::Wrapper;
4931 CodeModel::Model M = getTargetMachine().getCodeModel();
4933 if (Subtarget->isPICStyleRIPRel() &&
4934 (M == CodeModel::Small || M == CodeModel::Kernel))
4935 WrapperKind = X86ISD::WrapperRIP;
4936 else if (Subtarget->isPICStyleGOT())
4937 OpFlag = X86II::MO_GOTOFF;
4938 else if (Subtarget->isPICStyleStubPIC())
4939 OpFlag = X86II::MO_PIC_BASE_OFFSET;
4941 SDValue Result = DAG.getTargetConstantPool(CP->getConstVal(), getPointerTy(),
4943 CP->getOffset(), OpFlag);
4944 DebugLoc DL = CP->getDebugLoc();
4945 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
4946 // With PIC, the address is actually $g + Offset.
4948 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
4949 DAG.getNode(X86ISD::GlobalBaseReg,
4950 DebugLoc::getUnknownLoc(), getPointerTy()),
4957 SDValue X86TargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) {
4958 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
4960 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
4962 unsigned char OpFlag = 0;
4963 unsigned WrapperKind = X86ISD::Wrapper;
4964 CodeModel::Model M = getTargetMachine().getCodeModel();
4966 if (Subtarget->isPICStyleRIPRel() &&
4967 (M == CodeModel::Small || M == CodeModel::Kernel))
4968 WrapperKind = X86ISD::WrapperRIP;
4969 else if (Subtarget->isPICStyleGOT())
4970 OpFlag = X86II::MO_GOTOFF;
4971 else if (Subtarget->isPICStyleStubPIC())
4972 OpFlag = X86II::MO_PIC_BASE_OFFSET;
4974 SDValue Result = DAG.getTargetJumpTable(JT->getIndex(), getPointerTy(),
4976 DebugLoc DL = JT->getDebugLoc();
4977 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
4979 // With PIC, the address is actually $g + Offset.
4981 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
4982 DAG.getNode(X86ISD::GlobalBaseReg,
4983 DebugLoc::getUnknownLoc(), getPointerTy()),
4991 X86TargetLowering::LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) {
4992 const char *Sym = cast<ExternalSymbolSDNode>(Op)->getSymbol();
4994 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
4996 unsigned char OpFlag = 0;
4997 unsigned WrapperKind = X86ISD::Wrapper;
4998 CodeModel::Model M = getTargetMachine().getCodeModel();
5000 if (Subtarget->isPICStyleRIPRel() &&
5001 (M == CodeModel::Small || M == CodeModel::Kernel))
5002 WrapperKind = X86ISD::WrapperRIP;
5003 else if (Subtarget->isPICStyleGOT())
5004 OpFlag = X86II::MO_GOTOFF;
5005 else if (Subtarget->isPICStyleStubPIC())
5006 OpFlag = X86II::MO_PIC_BASE_OFFSET;
5008 SDValue Result = DAG.getTargetExternalSymbol(Sym, getPointerTy(), OpFlag);
5010 DebugLoc DL = Op.getDebugLoc();
5011 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
5014 // With PIC, the address is actually $g + Offset.
5015 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
5016 !Subtarget->is64Bit()) {
5017 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
5018 DAG.getNode(X86ISD::GlobalBaseReg,
5019 DebugLoc::getUnknownLoc(),
5028 X86TargetLowering::LowerBlockAddress(SDValue Op, SelectionDAG &DAG) {
5029 // Create the TargetBlockAddressAddress node.
5030 unsigned char OpFlags =
5031 Subtarget->ClassifyBlockAddressReference();
5032 CodeModel::Model M = getTargetMachine().getCodeModel();
5033 BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
5034 DebugLoc dl = Op.getDebugLoc();
5035 SDValue Result = DAG.getBlockAddress(BA, getPointerTy(),
5036 /*isTarget=*/true, OpFlags);
5038 if (Subtarget->isPICStyleRIPRel() &&
5039 (M == CodeModel::Small || M == CodeModel::Kernel))
5040 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
5042 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
5044 // With PIC, the address is actually $g + Offset.
5045 if (isGlobalRelativeToPICBase(OpFlags)) {
5046 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
5047 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
5055 X86TargetLowering::LowerGlobalAddress(const GlobalValue *GV, DebugLoc dl,
5057 SelectionDAG &DAG) const {
5058 // Create the TargetGlobalAddress node, folding in the constant
5059 // offset if it is legal.
5060 unsigned char OpFlags =
5061 Subtarget->ClassifyGlobalReference(GV, getTargetMachine());
5062 CodeModel::Model M = getTargetMachine().getCodeModel();
5064 if (OpFlags == X86II::MO_NO_FLAG &&
5065 X86::isOffsetSuitableForCodeModel(Offset, M)) {
5066 // A direct static reference to a global.
5067 Result = DAG.getTargetGlobalAddress(GV, getPointerTy(), Offset);
5070 Result = DAG.getTargetGlobalAddress(GV, getPointerTy(), 0, OpFlags);
5073 if (Subtarget->isPICStyleRIPRel() &&
5074 (M == CodeModel::Small || M == CodeModel::Kernel))
5075 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
5077 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
5079 // With PIC, the address is actually $g + Offset.
5080 if (isGlobalRelativeToPICBase(OpFlags)) {
5081 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
5082 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
5086 // For globals that require a load from a stub to get the address, emit the
5088 if (isGlobalStubReference(OpFlags))
5089 Result = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Result,
5090 PseudoSourceValue::getGOT(), 0, false, false, 0);
5092 // If there was a non-zero offset that we didn't fold, create an explicit
5095 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(), Result,
5096 DAG.getConstant(Offset, getPointerTy()));
5102 X86TargetLowering::LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) {
5103 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
5104 int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset();
5105 return LowerGlobalAddress(GV, Op.getDebugLoc(), Offset, DAG);
5109 GetTLSADDR(SelectionDAG &DAG, SDValue Chain, GlobalAddressSDNode *GA,
5110 SDValue *InFlag, const EVT PtrVT, unsigned ReturnReg,
5111 unsigned char OperandFlags) {
5112 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
5113 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
5114 DebugLoc dl = GA->getDebugLoc();
5115 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(),
5116 GA->getValueType(0),
5120 SDValue Ops[] = { Chain, TGA, *InFlag };
5121 Chain = DAG.getNode(X86ISD::TLSADDR, dl, NodeTys, Ops, 3);
5123 SDValue Ops[] = { Chain, TGA };
5124 Chain = DAG.getNode(X86ISD::TLSADDR, dl, NodeTys, Ops, 2);
5127 // TLSADDR will be codegen'ed as call. Inform MFI that function has calls.
5128 MFI->setHasCalls(true);
5130 SDValue Flag = Chain.getValue(1);
5131 return DAG.getCopyFromReg(Chain, dl, ReturnReg, PtrVT, Flag);
5134 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 32 bit
5136 LowerToTLSGeneralDynamicModel32(GlobalAddressSDNode *GA, SelectionDAG &DAG,
5139 DebugLoc dl = GA->getDebugLoc(); // ? function entry point might be better
5140 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
5141 DAG.getNode(X86ISD::GlobalBaseReg,
5142 DebugLoc::getUnknownLoc(),
5144 InFlag = Chain.getValue(1);
5146 return GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX, X86II::MO_TLSGD);
5149 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 64 bit
5151 LowerToTLSGeneralDynamicModel64(GlobalAddressSDNode *GA, SelectionDAG &DAG,
5153 return GetTLSADDR(DAG, DAG.getEntryNode(), GA, NULL, PtrVT,
5154 X86::RAX, X86II::MO_TLSGD);
5157 // Lower ISD::GlobalTLSAddress using the "initial exec" (for no-pic) or
5158 // "local exec" model.
5159 static SDValue LowerToTLSExecModel(GlobalAddressSDNode *GA, SelectionDAG &DAG,
5160 const EVT PtrVT, TLSModel::Model model,
5162 DebugLoc dl = GA->getDebugLoc();
5163 // Get the Thread Pointer
5164 SDValue Base = DAG.getNode(X86ISD::SegmentBaseAddress,
5165 DebugLoc::getUnknownLoc(), PtrVT,
5166 DAG.getRegister(is64Bit? X86::FS : X86::GS,
5169 SDValue ThreadPointer = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Base,
5170 NULL, 0, false, false, 0);
5172 unsigned char OperandFlags = 0;
5173 // Most TLS accesses are not RIP relative, even on x86-64. One exception is
5175 unsigned WrapperKind = X86ISD::Wrapper;
5176 if (model == TLSModel::LocalExec) {
5177 OperandFlags = is64Bit ? X86II::MO_TPOFF : X86II::MO_NTPOFF;
5178 } else if (is64Bit) {
5179 assert(model == TLSModel::InitialExec);
5180 OperandFlags = X86II::MO_GOTTPOFF;
5181 WrapperKind = X86ISD::WrapperRIP;
5183 assert(model == TLSModel::InitialExec);
5184 OperandFlags = X86II::MO_INDNTPOFF;
5187 // emit "addl x@ntpoff,%eax" (local exec) or "addl x@indntpoff,%eax" (initial
5189 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), GA->getValueType(0),
5190 GA->getOffset(), OperandFlags);
5191 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
5193 if (model == TLSModel::InitialExec)
5194 Offset = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Offset,
5195 PseudoSourceValue::getGOT(), 0, false, false, 0);
5197 // The address of the thread local variable is the add of the thread
5198 // pointer with the offset of the variable.
5199 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset);
5203 X86TargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) {
5204 // TODO: implement the "local dynamic" model
5205 // TODO: implement the "initial exec"model for pic executables
5206 assert(Subtarget->isTargetELF() &&
5207 "TLS not implemented for non-ELF targets");
5208 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
5209 const GlobalValue *GV = GA->getGlobal();
5211 // If GV is an alias then use the aliasee for determining
5212 // thread-localness.
5213 if (const GlobalAlias *GA = dyn_cast<GlobalAlias>(GV))
5214 GV = GA->resolveAliasedGlobal(false);
5216 TLSModel::Model model = getTLSModel(GV,
5217 getTargetMachine().getRelocationModel());
5220 case TLSModel::GeneralDynamic:
5221 case TLSModel::LocalDynamic: // not implemented
5222 if (Subtarget->is64Bit())
5223 return LowerToTLSGeneralDynamicModel64(GA, DAG, getPointerTy());
5224 return LowerToTLSGeneralDynamicModel32(GA, DAG, getPointerTy());
5226 case TLSModel::InitialExec:
5227 case TLSModel::LocalExec:
5228 return LowerToTLSExecModel(GA, DAG, getPointerTy(), model,
5229 Subtarget->is64Bit());
5232 llvm_unreachable("Unreachable");
5237 /// LowerShift - Lower SRA_PARTS and friends, which return two i32 values and
5238 /// take a 2 x i32 value to shift plus a shift amount.
5239 SDValue X86TargetLowering::LowerShift(SDValue Op, SelectionDAG &DAG) {
5240 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
5241 EVT VT = Op.getValueType();
5242 unsigned VTBits = VT.getSizeInBits();
5243 DebugLoc dl = Op.getDebugLoc();
5244 bool isSRA = Op.getOpcode() == ISD::SRA_PARTS;
5245 SDValue ShOpLo = Op.getOperand(0);
5246 SDValue ShOpHi = Op.getOperand(1);
5247 SDValue ShAmt = Op.getOperand(2);
5248 SDValue Tmp1 = isSRA ? DAG.getNode(ISD::SRA, dl, VT, ShOpHi,
5249 DAG.getConstant(VTBits - 1, MVT::i8))
5250 : DAG.getConstant(0, VT);
5253 if (Op.getOpcode() == ISD::SHL_PARTS) {
5254 Tmp2 = DAG.getNode(X86ISD::SHLD, dl, VT, ShOpHi, ShOpLo, ShAmt);
5255 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ShAmt);
5257 Tmp2 = DAG.getNode(X86ISD::SHRD, dl, VT, ShOpLo, ShOpHi, ShAmt);
5258 Tmp3 = DAG.getNode(isSRA ? ISD::SRA : ISD::SRL, dl, VT, ShOpHi, ShAmt);
5261 SDValue AndNode = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt,
5262 DAG.getConstant(VTBits, MVT::i8));
5263 SDValue Cond = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
5264 AndNode, DAG.getConstant(0, MVT::i8));
5267 SDValue CC = DAG.getConstant(X86::COND_NE, MVT::i8);
5268 SDValue Ops0[4] = { Tmp2, Tmp3, CC, Cond };
5269 SDValue Ops1[4] = { Tmp3, Tmp1, CC, Cond };
5271 if (Op.getOpcode() == ISD::SHL_PARTS) {
5272 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0, 4);
5273 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1, 4);
5275 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0, 4);
5276 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1, 4);
5279 SDValue Ops[2] = { Lo, Hi };
5280 return DAG.getMergeValues(Ops, 2, dl);
5283 SDValue X86TargetLowering::LowerSINT_TO_FP(SDValue Op, SelectionDAG &DAG) {
5284 EVT SrcVT = Op.getOperand(0).getValueType();
5286 if (SrcVT.isVector()) {
5287 if (SrcVT == MVT::v2i32 && Op.getValueType() == MVT::v2f64) {
5293 assert(SrcVT.getSimpleVT() <= MVT::i64 && SrcVT.getSimpleVT() >= MVT::i16 &&
5294 "Unknown SINT_TO_FP to lower!");
5296 // These are really Legal; return the operand so the caller accepts it as
5298 if (SrcVT == MVT::i32 && isScalarFPTypeInSSEReg(Op.getValueType()))
5300 if (SrcVT == MVT::i64 && isScalarFPTypeInSSEReg(Op.getValueType()) &&
5301 Subtarget->is64Bit()) {
5305 DebugLoc dl = Op.getDebugLoc();
5306 unsigned Size = SrcVT.getSizeInBits()/8;
5307 MachineFunction &MF = DAG.getMachineFunction();
5308 int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size, false);
5309 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
5310 SDValue Chain = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
5312 PseudoSourceValue::getFixedStack(SSFI), 0,
5314 return BuildFILD(Op, SrcVT, Chain, StackSlot, DAG);
5317 SDValue X86TargetLowering::BuildFILD(SDValue Op, EVT SrcVT, SDValue Chain,
5319 SelectionDAG &DAG) {
5321 DebugLoc dl = Op.getDebugLoc();
5323 bool useSSE = isScalarFPTypeInSSEReg(Op.getValueType());
5325 Tys = DAG.getVTList(MVT::f64, MVT::Other, MVT::Flag);
5327 Tys = DAG.getVTList(Op.getValueType(), MVT::Other);
5328 SDValue Ops[] = { Chain, StackSlot, DAG.getValueType(SrcVT) };
5329 SDValue Result = DAG.getNode(useSSE ? X86ISD::FILD_FLAG : X86ISD::FILD, dl,
5330 Tys, Ops, array_lengthof(Ops));
5333 Chain = Result.getValue(1);
5334 SDValue InFlag = Result.getValue(2);
5336 // FIXME: Currently the FST is flagged to the FILD_FLAG. This
5337 // shouldn't be necessary except that RFP cannot be live across
5338 // multiple blocks. When stackifier is fixed, they can be uncoupled.
5339 MachineFunction &MF = DAG.getMachineFunction();
5340 int SSFI = MF.getFrameInfo()->CreateStackObject(8, 8, false);
5341 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
5342 Tys = DAG.getVTList(MVT::Other);
5344 Chain, Result, StackSlot, DAG.getValueType(Op.getValueType()), InFlag
5346 Chain = DAG.getNode(X86ISD::FST, dl, Tys, Ops, array_lengthof(Ops));
5347 Result = DAG.getLoad(Op.getValueType(), dl, Chain, StackSlot,
5348 PseudoSourceValue::getFixedStack(SSFI), 0,
5355 // LowerUINT_TO_FP_i64 - 64-bit unsigned integer to double expansion.
5356 SDValue X86TargetLowering::LowerUINT_TO_FP_i64(SDValue Op, SelectionDAG &DAG) {
5357 // This algorithm is not obvious. Here it is in C code, more or less:
5359 double uint64_to_double( uint32_t hi, uint32_t lo ) {
5360 static const __m128i exp = { 0x4330000045300000ULL, 0 };
5361 static const __m128d bias = { 0x1.0p84, 0x1.0p52 };
5363 // Copy ints to xmm registers.
5364 __m128i xh = _mm_cvtsi32_si128( hi );
5365 __m128i xl = _mm_cvtsi32_si128( lo );
5367 // Combine into low half of a single xmm register.
5368 __m128i x = _mm_unpacklo_epi32( xh, xl );
5372 // Merge in appropriate exponents to give the integer bits the right
5374 x = _mm_unpacklo_epi32( x, exp );
5376 // Subtract away the biases to deal with the IEEE-754 double precision
5378 d = _mm_sub_pd( (__m128d) x, bias );
5380 // All conversions up to here are exact. The correctly rounded result is
5381 // calculated using the current rounding mode using the following
5383 d = _mm_add_sd( d, _mm_unpackhi_pd( d, d ) );
5384 _mm_store_sd( &sd, d ); // Because we are returning doubles in XMM, this
5385 // store doesn't really need to be here (except
5386 // maybe to zero the other double)
5391 DebugLoc dl = Op.getDebugLoc();
5392 LLVMContext *Context = DAG.getContext();
5394 // Build some magic constants.
5395 std::vector<Constant*> CV0;
5396 CV0.push_back(ConstantInt::get(*Context, APInt(32, 0x45300000)));
5397 CV0.push_back(ConstantInt::get(*Context, APInt(32, 0x43300000)));
5398 CV0.push_back(ConstantInt::get(*Context, APInt(32, 0)));
5399 CV0.push_back(ConstantInt::get(*Context, APInt(32, 0)));
5400 Constant *C0 = ConstantVector::get(CV0);
5401 SDValue CPIdx0 = DAG.getConstantPool(C0, getPointerTy(), 16);
5403 std::vector<Constant*> CV1;
5405 ConstantFP::get(*Context, APFloat(APInt(64, 0x4530000000000000ULL))));
5407 ConstantFP::get(*Context, APFloat(APInt(64, 0x4330000000000000ULL))));
5408 Constant *C1 = ConstantVector::get(CV1);
5409 SDValue CPIdx1 = DAG.getConstantPool(C1, getPointerTy(), 16);
5411 SDValue XR1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,
5412 DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
5414 DAG.getIntPtrConstant(1)));
5415 SDValue XR2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,
5416 DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
5418 DAG.getIntPtrConstant(0)));
5419 SDValue Unpck1 = getUnpackl(DAG, dl, MVT::v4i32, XR1, XR2);
5420 SDValue CLod0 = DAG.getLoad(MVT::v4i32, dl, DAG.getEntryNode(), CPIdx0,
5421 PseudoSourceValue::getConstantPool(), 0,
5423 SDValue Unpck2 = getUnpackl(DAG, dl, MVT::v4i32, Unpck1, CLod0);
5424 SDValue XR2F = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2f64, Unpck2);
5425 SDValue CLod1 = DAG.getLoad(MVT::v2f64, dl, CLod0.getValue(1), CPIdx1,
5426 PseudoSourceValue::getConstantPool(), 0,
5428 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, XR2F, CLod1);
5430 // Add the halves; easiest way is to swap them into another reg first.
5431 int ShufMask[2] = { 1, -1 };
5432 SDValue Shuf = DAG.getVectorShuffle(MVT::v2f64, dl, Sub,
5433 DAG.getUNDEF(MVT::v2f64), ShufMask);
5434 SDValue Add = DAG.getNode(ISD::FADD, dl, MVT::v2f64, Shuf, Sub);
5435 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Add,
5436 DAG.getIntPtrConstant(0));
5439 // LowerUINT_TO_FP_i32 - 32-bit unsigned integer to float expansion.
5440 SDValue X86TargetLowering::LowerUINT_TO_FP_i32(SDValue Op, SelectionDAG &DAG) {
5441 DebugLoc dl = Op.getDebugLoc();
5442 // FP constant to bias correct the final result.
5443 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL),
5446 // Load the 32-bit value into an XMM register.
5447 SDValue Load = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,
5448 DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
5450 DAG.getIntPtrConstant(0)));
5452 Load = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
5453 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2f64, Load),
5454 DAG.getIntPtrConstant(0));
5456 // Or the load with the bias.
5457 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64,
5458 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2i64,
5459 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
5461 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2i64,
5462 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
5463 MVT::v2f64, Bias)));
5464 Or = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
5465 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2f64, Or),
5466 DAG.getIntPtrConstant(0));
5468 // Subtract the bias.
5469 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Or, Bias);
5471 // Handle final rounding.
5472 EVT DestVT = Op.getValueType();
5474 if (DestVT.bitsLT(MVT::f64)) {
5475 return DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub,
5476 DAG.getIntPtrConstant(0));
5477 } else if (DestVT.bitsGT(MVT::f64)) {
5478 return DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub);
5481 // Handle final rounding.
5485 SDValue X86TargetLowering::LowerUINT_TO_FP(SDValue Op, SelectionDAG &DAG) {
5486 SDValue N0 = Op.getOperand(0);
5487 DebugLoc dl = Op.getDebugLoc();
5489 // Now not UINT_TO_FP is legal (it's marked custom), dag combiner won't
5490 // optimize it to a SINT_TO_FP when the sign bit is known zero. Perform
5491 // the optimization here.
5492 if (DAG.SignBitIsZero(N0))
5493 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(), N0);
5495 EVT SrcVT = N0.getValueType();
5496 if (SrcVT == MVT::i64) {
5497 // We only handle SSE2 f64 target here; caller can expand the rest.
5498 if (Op.getValueType() != MVT::f64 || !X86ScalarSSEf64)
5501 return LowerUINT_TO_FP_i64(Op, DAG);
5502 } else if (SrcVT == MVT::i32 && X86ScalarSSEf64) {
5503 return LowerUINT_TO_FP_i32(Op, DAG);
5506 assert(SrcVT == MVT::i32 && "Unknown UINT_TO_FP to lower!");
5508 // Make a 64-bit buffer, and use it to build an FILD.
5509 SDValue StackSlot = DAG.CreateStackTemporary(MVT::i64);
5510 SDValue WordOff = DAG.getConstant(4, getPointerTy());
5511 SDValue OffsetSlot = DAG.getNode(ISD::ADD, dl,
5512 getPointerTy(), StackSlot, WordOff);
5513 SDValue Store1 = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
5514 StackSlot, NULL, 0, false, false, 0);
5515 SDValue Store2 = DAG.getStore(Store1, dl, DAG.getConstant(0, MVT::i32),
5516 OffsetSlot, NULL, 0, false, false, 0);
5517 return BuildFILD(Op, MVT::i64, Store2, StackSlot, DAG);
5520 std::pair<SDValue,SDValue> X86TargetLowering::
5521 FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG, bool IsSigned) {
5522 DebugLoc dl = Op.getDebugLoc();
5524 EVT DstTy = Op.getValueType();
5527 assert(DstTy == MVT::i32 && "Unexpected FP_TO_UINT");
5531 assert(DstTy.getSimpleVT() <= MVT::i64 &&
5532 DstTy.getSimpleVT() >= MVT::i16 &&
5533 "Unknown FP_TO_SINT to lower!");
5535 // These are really Legal.
5536 if (DstTy == MVT::i32 &&
5537 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
5538 return std::make_pair(SDValue(), SDValue());
5539 if (Subtarget->is64Bit() &&
5540 DstTy == MVT::i64 &&
5541 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
5542 return std::make_pair(SDValue(), SDValue());
5544 // We lower FP->sint64 into FISTP64, followed by a load, all to a temporary
5546 MachineFunction &MF = DAG.getMachineFunction();
5547 unsigned MemSize = DstTy.getSizeInBits()/8;
5548 int SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
5549 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
5552 switch (DstTy.getSimpleVT().SimpleTy) {
5553 default: llvm_unreachable("Invalid FP_TO_SINT to lower!");
5554 case MVT::i16: Opc = X86ISD::FP_TO_INT16_IN_MEM; break;
5555 case MVT::i32: Opc = X86ISD::FP_TO_INT32_IN_MEM; break;
5556 case MVT::i64: Opc = X86ISD::FP_TO_INT64_IN_MEM; break;
5559 SDValue Chain = DAG.getEntryNode();
5560 SDValue Value = Op.getOperand(0);
5561 if (isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType())) {
5562 assert(DstTy == MVT::i64 && "Invalid FP_TO_SINT to lower!");
5563 Chain = DAG.getStore(Chain, dl, Value, StackSlot,
5564 PseudoSourceValue::getFixedStack(SSFI), 0,
5566 SDVTList Tys = DAG.getVTList(Op.getOperand(0).getValueType(), MVT::Other);
5568 Chain, StackSlot, DAG.getValueType(Op.getOperand(0).getValueType())
5570 Value = DAG.getNode(X86ISD::FLD, dl, Tys, Ops, 3);
5571 Chain = Value.getValue(1);
5572 SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
5573 StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
5576 // Build the FP_TO_INT*_IN_MEM
5577 SDValue Ops[] = { Chain, Value, StackSlot };
5578 SDValue FIST = DAG.getNode(Opc, dl, MVT::Other, Ops, 3);
5580 return std::make_pair(FIST, StackSlot);
5583 SDValue X86TargetLowering::LowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG) {
5584 if (Op.getValueType().isVector()) {
5585 if (Op.getValueType() == MVT::v2i32 &&
5586 Op.getOperand(0).getValueType() == MVT::v2f64) {
5592 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG, true);
5593 SDValue FIST = Vals.first, StackSlot = Vals.second;
5594 // If FP_TO_INTHelper failed, the node is actually supposed to be Legal.
5595 if (FIST.getNode() == 0) return Op;
5598 return DAG.getLoad(Op.getValueType(), Op.getDebugLoc(),
5599 FIST, StackSlot, NULL, 0, false, false, 0);
5602 SDValue X86TargetLowering::LowerFP_TO_UINT(SDValue Op, SelectionDAG &DAG) {
5603 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG, false);
5604 SDValue FIST = Vals.first, StackSlot = Vals.second;
5605 assert(FIST.getNode() && "Unexpected failure");
5608 return DAG.getLoad(Op.getValueType(), Op.getDebugLoc(),
5609 FIST, StackSlot, NULL, 0, false, false, 0);
5612 SDValue X86TargetLowering::LowerFABS(SDValue Op, SelectionDAG &DAG) {
5613 LLVMContext *Context = DAG.getContext();
5614 DebugLoc dl = Op.getDebugLoc();
5615 EVT VT = Op.getValueType();
5618 EltVT = VT.getVectorElementType();
5619 std::vector<Constant*> CV;
5620 if (EltVT == MVT::f64) {
5621 Constant *C = ConstantFP::get(*Context, APFloat(APInt(64, ~(1ULL << 63))));
5625 Constant *C = ConstantFP::get(*Context, APFloat(APInt(32, ~(1U << 31))));
5631 Constant *C = ConstantVector::get(CV);
5632 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
5633 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
5634 PseudoSourceValue::getConstantPool(), 0,
5636 return DAG.getNode(X86ISD::FAND, dl, VT, Op.getOperand(0), Mask);
5639 SDValue X86TargetLowering::LowerFNEG(SDValue Op, SelectionDAG &DAG) {
5640 LLVMContext *Context = DAG.getContext();
5641 DebugLoc dl = Op.getDebugLoc();
5642 EVT VT = Op.getValueType();
5645 EltVT = VT.getVectorElementType();
5646 std::vector<Constant*> CV;
5647 if (EltVT == MVT::f64) {
5648 Constant *C = ConstantFP::get(*Context, APFloat(APInt(64, 1ULL << 63)));
5652 Constant *C = ConstantFP::get(*Context, APFloat(APInt(32, 1U << 31)));
5658 Constant *C = ConstantVector::get(CV);
5659 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
5660 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
5661 PseudoSourceValue::getConstantPool(), 0,
5663 if (VT.isVector()) {
5664 return DAG.getNode(ISD::BIT_CONVERT, dl, VT,
5665 DAG.getNode(ISD::XOR, dl, MVT::v2i64,
5666 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2i64,
5668 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2i64, Mask)));
5670 return DAG.getNode(X86ISD::FXOR, dl, VT, Op.getOperand(0), Mask);
5674 SDValue X86TargetLowering::LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) {
5675 LLVMContext *Context = DAG.getContext();
5676 SDValue Op0 = Op.getOperand(0);
5677 SDValue Op1 = Op.getOperand(1);
5678 DebugLoc dl = Op.getDebugLoc();
5679 EVT VT = Op.getValueType();
5680 EVT SrcVT = Op1.getValueType();
5682 // If second operand is smaller, extend it first.
5683 if (SrcVT.bitsLT(VT)) {
5684 Op1 = DAG.getNode(ISD::FP_EXTEND, dl, VT, Op1);
5687 // And if it is bigger, shrink it first.
5688 if (SrcVT.bitsGT(VT)) {
5689 Op1 = DAG.getNode(ISD::FP_ROUND, dl, VT, Op1, DAG.getIntPtrConstant(1));
5693 // At this point the operands and the result should have the same
5694 // type, and that won't be f80 since that is not custom lowered.
5696 // First get the sign bit of second operand.
5697 std::vector<Constant*> CV;
5698 if (SrcVT == MVT::f64) {
5699 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, 1ULL << 63))));
5700 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, 0))));
5702 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 1U << 31))));
5703 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
5704 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
5705 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
5707 Constant *C = ConstantVector::get(CV);
5708 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
5709 SDValue Mask1 = DAG.getLoad(SrcVT, dl, DAG.getEntryNode(), CPIdx,
5710 PseudoSourceValue::getConstantPool(), 0,
5712 SDValue SignBit = DAG.getNode(X86ISD::FAND, dl, SrcVT, Op1, Mask1);
5714 // Shift sign bit right or left if the two operands have different types.
5715 if (SrcVT.bitsGT(VT)) {
5716 // Op0 is MVT::f32, Op1 is MVT::f64.
5717 SignBit = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f64, SignBit);
5718 SignBit = DAG.getNode(X86ISD::FSRL, dl, MVT::v2f64, SignBit,
5719 DAG.getConstant(32, MVT::i32));
5720 SignBit = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v4f32, SignBit);
5721 SignBit = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f32, SignBit,
5722 DAG.getIntPtrConstant(0));
5725 // Clear first operand sign bit.
5727 if (VT == MVT::f64) {
5728 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, ~(1ULL << 63)))));
5729 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, 0))));
5731 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, ~(1U << 31)))));
5732 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
5733 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
5734 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
5736 C = ConstantVector::get(CV);
5737 CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
5738 SDValue Mask2 = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
5739 PseudoSourceValue::getConstantPool(), 0,
5741 SDValue Val = DAG.getNode(X86ISD::FAND, dl, VT, Op0, Mask2);
5743 // Or the value with the sign bit.
5744 return DAG.getNode(X86ISD::FOR, dl, VT, Val, SignBit);
5747 /// Emit nodes that will be selected as "test Op0,Op0", or something
5749 SDValue X86TargetLowering::EmitTest(SDValue Op, unsigned X86CC,
5750 SelectionDAG &DAG) {
5751 DebugLoc dl = Op.getDebugLoc();
5753 // CF and OF aren't always set the way we want. Determine which
5754 // of these we need.
5755 bool NeedCF = false;
5756 bool NeedOF = false;
5758 case X86::COND_A: case X86::COND_AE:
5759 case X86::COND_B: case X86::COND_BE:
5762 case X86::COND_G: case X86::COND_GE:
5763 case X86::COND_L: case X86::COND_LE:
5764 case X86::COND_O: case X86::COND_NO:
5770 // See if we can use the EFLAGS value from the operand instead of
5771 // doing a separate TEST. TEST always sets OF and CF to 0, so unless
5772 // we prove that the arithmetic won't overflow, we can't use OF or CF.
5773 if (Op.getResNo() == 0 && !NeedOF && !NeedCF) {
5774 unsigned Opcode = 0;
5775 unsigned NumOperands = 0;
5776 switch (Op.getNode()->getOpcode()) {
5778 // Due to an isel shortcoming, be conservative if this add is likely to
5779 // be selected as part of a load-modify-store instruction. When the root
5780 // node in a match is a store, isel doesn't know how to remap non-chain
5781 // non-flag uses of other nodes in the match, such as the ADD in this
5782 // case. This leads to the ADD being left around and reselected, with
5783 // the result being two adds in the output.
5784 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
5785 UE = Op.getNode()->use_end(); UI != UE; ++UI)
5786 if (UI->getOpcode() == ISD::STORE)
5788 if (ConstantSDNode *C =
5789 dyn_cast<ConstantSDNode>(Op.getNode()->getOperand(1))) {
5790 // An add of one will be selected as an INC.
5791 if (C->getAPIntValue() == 1) {
5792 Opcode = X86ISD::INC;
5796 // An add of negative one (subtract of one) will be selected as a DEC.
5797 if (C->getAPIntValue().isAllOnesValue()) {
5798 Opcode = X86ISD::DEC;
5803 // Otherwise use a regular EFLAGS-setting add.
5804 Opcode = X86ISD::ADD;
5808 // If the primary and result isn't used, don't bother using X86ISD::AND,
5809 // because a TEST instruction will be better.
5810 bool NonFlagUse = false;
5811 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
5812 UE = Op.getNode()->use_end(); UI != UE; ++UI) {
5814 unsigned UOpNo = UI.getOperandNo();
5815 if (User->getOpcode() == ISD::TRUNCATE && User->hasOneUse()) {
5816 // Look pass truncate.
5817 UOpNo = User->use_begin().getOperandNo();
5818 User = *User->use_begin();
5820 if (User->getOpcode() != ISD::BRCOND &&
5821 User->getOpcode() != ISD::SETCC &&
5822 (User->getOpcode() != ISD::SELECT || UOpNo != 0)) {
5834 // Due to the ISEL shortcoming noted above, be conservative if this op is
5835 // likely to be selected as part of a load-modify-store instruction.
5836 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
5837 UE = Op.getNode()->use_end(); UI != UE; ++UI)
5838 if (UI->getOpcode() == ISD::STORE)
5840 // Otherwise use a regular EFLAGS-setting instruction.
5841 switch (Op.getNode()->getOpcode()) {
5842 case ISD::SUB: Opcode = X86ISD::SUB; break;
5843 case ISD::OR: Opcode = X86ISD::OR; break;
5844 case ISD::XOR: Opcode = X86ISD::XOR; break;
5845 case ISD::AND: Opcode = X86ISD::AND; break;
5846 default: llvm_unreachable("unexpected operator!");
5857 return SDValue(Op.getNode(), 1);
5863 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
5864 SmallVector<SDValue, 4> Ops;
5865 for (unsigned i = 0; i != NumOperands; ++i)
5866 Ops.push_back(Op.getOperand(i));
5867 SDValue New = DAG.getNode(Opcode, dl, VTs, &Ops[0], NumOperands);
5868 DAG.ReplaceAllUsesWith(Op, New);
5869 return SDValue(New.getNode(), 1);
5873 // Otherwise just emit a CMP with 0, which is the TEST pattern.
5874 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
5875 DAG.getConstant(0, Op.getValueType()));
5878 /// Emit nodes that will be selected as "cmp Op0,Op1", or something
5880 SDValue X86TargetLowering::EmitCmp(SDValue Op0, SDValue Op1, unsigned X86CC,
5881 SelectionDAG &DAG) {
5882 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op1))
5883 if (C->getAPIntValue() == 0)
5884 return EmitTest(Op0, X86CC, DAG);
5886 DebugLoc dl = Op0.getDebugLoc();
5887 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op0, Op1);
5890 /// LowerToBT - Result of 'and' is compared against zero. Turn it into a BT node
5891 /// if it's possible.
5892 static SDValue LowerToBT(SDValue And, ISD::CondCode CC,
5893 DebugLoc dl, SelectionDAG &DAG) {
5894 SDValue Op0 = And.getOperand(0);
5895 SDValue Op1 = And.getOperand(1);
5896 if (Op0.getOpcode() == ISD::TRUNCATE)
5897 Op0 = Op0.getOperand(0);
5898 if (Op1.getOpcode() == ISD::TRUNCATE)
5899 Op1 = Op1.getOperand(0);
5902 if (Op1.getOpcode() == ISD::SHL) {
5903 if (ConstantSDNode *And10C = dyn_cast<ConstantSDNode>(Op1.getOperand(0)))
5904 if (And10C->getZExtValue() == 1) {
5906 RHS = Op1.getOperand(1);
5908 } else if (Op0.getOpcode() == ISD::SHL) {
5909 if (ConstantSDNode *And00C = dyn_cast<ConstantSDNode>(Op0.getOperand(0)))
5910 if (And00C->getZExtValue() == 1) {
5912 RHS = Op0.getOperand(1);
5914 } else if (Op1.getOpcode() == ISD::Constant) {
5915 ConstantSDNode *AndRHS = cast<ConstantSDNode>(Op1);
5916 SDValue AndLHS = Op0;
5917 if (AndRHS->getZExtValue() == 1 && AndLHS.getOpcode() == ISD::SRL) {
5918 LHS = AndLHS.getOperand(0);
5919 RHS = AndLHS.getOperand(1);
5923 if (LHS.getNode()) {
5924 // If LHS is i8, promote it to i16 with any_extend. There is no i8 BT
5925 // instruction. Since the shift amount is in-range-or-undefined, we know
5926 // that doing a bittest on the i16 value is ok. We extend to i32 because
5927 // the encoding for the i16 version is larger than the i32 version.
5928 if (LHS.getValueType() == MVT::i8)
5929 LHS = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, LHS);
5931 // If the operand types disagree, extend the shift amount to match. Since
5932 // BT ignores high bits (like shifts) we can use anyextend.
5933 if (LHS.getValueType() != RHS.getValueType())
5934 RHS = DAG.getNode(ISD::ANY_EXTEND, dl, LHS.getValueType(), RHS);
5936 SDValue BT = DAG.getNode(X86ISD::BT, dl, MVT::i32, LHS, RHS);
5937 unsigned Cond = CC == ISD::SETEQ ? X86::COND_AE : X86::COND_B;
5938 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
5939 DAG.getConstant(Cond, MVT::i8), BT);
5945 SDValue X86TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) {
5946 assert(Op.getValueType() == MVT::i8 && "SetCC type must be 8-bit integer");
5947 SDValue Op0 = Op.getOperand(0);
5948 SDValue Op1 = Op.getOperand(1);
5949 DebugLoc dl = Op.getDebugLoc();
5950 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
5952 // Optimize to BT if possible.
5953 // Lower (X & (1 << N)) == 0 to BT(X, N).
5954 // Lower ((X >>u N) & 1) != 0 to BT(X, N).
5955 // Lower ((X >>s N) & 1) != 0 to BT(X, N).
5956 if (Op0.getOpcode() == ISD::AND &&
5958 Op1.getOpcode() == ISD::Constant &&
5959 cast<ConstantSDNode>(Op1)->getZExtValue() == 0 &&
5960 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
5961 SDValue NewSetCC = LowerToBT(Op0, CC, dl, DAG);
5962 if (NewSetCC.getNode())
5966 // Look for "(setcc) == / != 1" to avoid unncessary setcc.
5967 if (Op0.getOpcode() == X86ISD::SETCC &&
5968 Op1.getOpcode() == ISD::Constant &&
5969 (cast<ConstantSDNode>(Op1)->getZExtValue() == 1 ||
5970 cast<ConstantSDNode>(Op1)->isNullValue()) &&
5971 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
5972 X86::CondCode CCode = (X86::CondCode)Op0.getConstantOperandVal(0);
5973 bool Invert = (CC == ISD::SETNE) ^
5974 cast<ConstantSDNode>(Op1)->isNullValue();
5976 CCode = X86::GetOppositeBranchCondition(CCode);
5977 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
5978 DAG.getConstant(CCode, MVT::i8), Op0.getOperand(1));
5981 bool isFP = Op.getOperand(1).getValueType().isFloatingPoint();
5982 unsigned X86CC = TranslateX86CC(CC, isFP, Op0, Op1, DAG);
5983 if (X86CC == X86::COND_INVALID)
5986 SDValue Cond = EmitCmp(Op0, Op1, X86CC, DAG);
5988 // Use sbb x, x to materialize carry bit into a GPR.
5989 if (X86CC == X86::COND_B)
5990 return DAG.getNode(ISD::AND, dl, MVT::i8,
5991 DAG.getNode(X86ISD::SETCC_CARRY, dl, MVT::i8,
5992 DAG.getConstant(X86CC, MVT::i8), Cond),
5993 DAG.getConstant(1, MVT::i8));
5995 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
5996 DAG.getConstant(X86CC, MVT::i8), Cond);
5999 SDValue X86TargetLowering::LowerVSETCC(SDValue Op, SelectionDAG &DAG) {
6001 SDValue Op0 = Op.getOperand(0);
6002 SDValue Op1 = Op.getOperand(1);
6003 SDValue CC = Op.getOperand(2);
6004 EVT VT = Op.getValueType();
6005 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
6006 bool isFP = Op.getOperand(1).getValueType().isFloatingPoint();
6007 DebugLoc dl = Op.getDebugLoc();
6011 EVT VT0 = Op0.getValueType();
6012 assert(VT0 == MVT::v4f32 || VT0 == MVT::v2f64);
6013 unsigned Opc = VT0 == MVT::v4f32 ? X86ISD::CMPPS : X86ISD::CMPPD;
6016 switch (SetCCOpcode) {
6019 case ISD::SETEQ: SSECC = 0; break;
6021 case ISD::SETGT: Swap = true; // Fallthrough
6023 case ISD::SETOLT: SSECC = 1; break;
6025 case ISD::SETGE: Swap = true; // Fallthrough
6027 case ISD::SETOLE: SSECC = 2; break;
6028 case ISD::SETUO: SSECC = 3; break;
6030 case ISD::SETNE: SSECC = 4; break;
6031 case ISD::SETULE: Swap = true;
6032 case ISD::SETUGE: SSECC = 5; break;
6033 case ISD::SETULT: Swap = true;
6034 case ISD::SETUGT: SSECC = 6; break;
6035 case ISD::SETO: SSECC = 7; break;
6038 std::swap(Op0, Op1);
6040 // In the two special cases we can't handle, emit two comparisons.
6042 if (SetCCOpcode == ISD::SETUEQ) {
6044 UNORD = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(3, MVT::i8));
6045 EQ = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(0, MVT::i8));
6046 return DAG.getNode(ISD::OR, dl, VT, UNORD, EQ);
6048 else if (SetCCOpcode == ISD::SETONE) {
6050 ORD = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(7, MVT::i8));
6051 NEQ = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(4, MVT::i8));
6052 return DAG.getNode(ISD::AND, dl, VT, ORD, NEQ);
6054 llvm_unreachable("Illegal FP comparison");
6056 // Handle all other FP comparisons here.
6057 return DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(SSECC, MVT::i8));
6060 // We are handling one of the integer comparisons here. Since SSE only has
6061 // GT and EQ comparisons for integer, swapping operands and multiple
6062 // operations may be required for some comparisons.
6063 unsigned Opc = 0, EQOpc = 0, GTOpc = 0;
6064 bool Swap = false, Invert = false, FlipSigns = false;
6066 switch (VT.getSimpleVT().SimpleTy) {
6069 case MVT::v16i8: EQOpc = X86ISD::PCMPEQB; GTOpc = X86ISD::PCMPGTB; break;
6071 case MVT::v8i16: EQOpc = X86ISD::PCMPEQW; GTOpc = X86ISD::PCMPGTW; break;
6073 case MVT::v4i32: EQOpc = X86ISD::PCMPEQD; GTOpc = X86ISD::PCMPGTD; break;
6074 case MVT::v2i64: EQOpc = X86ISD::PCMPEQQ; GTOpc = X86ISD::PCMPGTQ; break;
6077 switch (SetCCOpcode) {
6079 case ISD::SETNE: Invert = true;
6080 case ISD::SETEQ: Opc = EQOpc; break;
6081 case ISD::SETLT: Swap = true;
6082 case ISD::SETGT: Opc = GTOpc; break;
6083 case ISD::SETGE: Swap = true;
6084 case ISD::SETLE: Opc = GTOpc; Invert = true; break;
6085 case ISD::SETULT: Swap = true;
6086 case ISD::SETUGT: Opc = GTOpc; FlipSigns = true; break;
6087 case ISD::SETUGE: Swap = true;
6088 case ISD::SETULE: Opc = GTOpc; FlipSigns = true; Invert = true; break;
6091 std::swap(Op0, Op1);
6093 // Since SSE has no unsigned integer comparisons, we need to flip the sign
6094 // bits of the inputs before performing those operations.
6096 EVT EltVT = VT.getVectorElementType();
6097 SDValue SignBit = DAG.getConstant(APInt::getSignBit(EltVT.getSizeInBits()),
6099 std::vector<SDValue> SignBits(VT.getVectorNumElements(), SignBit);
6100 SDValue SignVec = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &SignBits[0],
6102 Op0 = DAG.getNode(ISD::XOR, dl, VT, Op0, SignVec);
6103 Op1 = DAG.getNode(ISD::XOR, dl, VT, Op1, SignVec);
6106 SDValue Result = DAG.getNode(Opc, dl, VT, Op0, Op1);
6108 // If the logical-not of the result is required, perform that now.
6110 Result = DAG.getNOT(dl, Result, VT);
6115 // isX86LogicalCmp - Return true if opcode is a X86 logical comparison.
6116 static bool isX86LogicalCmp(SDValue Op) {
6117 unsigned Opc = Op.getNode()->getOpcode();
6118 if (Opc == X86ISD::CMP || Opc == X86ISD::COMI || Opc == X86ISD::UCOMI)
6120 if (Op.getResNo() == 1 &&
6121 (Opc == X86ISD::ADD ||
6122 Opc == X86ISD::SUB ||
6123 Opc == X86ISD::SMUL ||
6124 Opc == X86ISD::UMUL ||
6125 Opc == X86ISD::INC ||
6126 Opc == X86ISD::DEC ||
6127 Opc == X86ISD::OR ||
6128 Opc == X86ISD::XOR ||
6129 Opc == X86ISD::AND))
6135 SDValue X86TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) {
6136 bool addTest = true;
6137 SDValue Cond = Op.getOperand(0);
6138 DebugLoc dl = Op.getDebugLoc();
6141 if (Cond.getOpcode() == ISD::SETCC) {
6142 SDValue NewCond = LowerSETCC(Cond, DAG);
6143 if (NewCond.getNode())
6147 // (select (x == 0), -1, 0) -> (sign_bit (x - 1))
6148 SDValue Op1 = Op.getOperand(1);
6149 SDValue Op2 = Op.getOperand(2);
6150 if (Cond.getOpcode() == X86ISD::SETCC &&
6151 cast<ConstantSDNode>(Cond.getOperand(0))->getZExtValue() == X86::COND_E) {
6152 SDValue Cmp = Cond.getOperand(1);
6153 if (Cmp.getOpcode() == X86ISD::CMP) {
6154 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(Op1);
6155 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(Op2);
6156 ConstantSDNode *RHSC =
6157 dyn_cast<ConstantSDNode>(Cmp.getOperand(1).getNode());
6158 if (N1C && N1C->isAllOnesValue() &&
6159 N2C && N2C->isNullValue() &&
6160 RHSC && RHSC->isNullValue()) {
6161 SDValue CmpOp0 = Cmp.getOperand(0);
6162 Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
6163 CmpOp0, DAG.getConstant(1, CmpOp0.getValueType()));
6164 return DAG.getNode(X86ISD::SETCC_CARRY, dl, Op.getValueType(),
6165 DAG.getConstant(X86::COND_B, MVT::i8), Cmp);
6170 // Look pass (and (setcc_carry (cmp ...)), 1).
6171 if (Cond.getOpcode() == ISD::AND &&
6172 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
6173 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
6174 if (C && C->getAPIntValue() == 1)
6175 Cond = Cond.getOperand(0);
6178 // If condition flag is set by a X86ISD::CMP, then use it as the condition
6179 // setting operand in place of the X86ISD::SETCC.
6180 if (Cond.getOpcode() == X86ISD::SETCC ||
6181 Cond.getOpcode() == X86ISD::SETCC_CARRY) {
6182 CC = Cond.getOperand(0);
6184 SDValue Cmp = Cond.getOperand(1);
6185 unsigned Opc = Cmp.getOpcode();
6186 EVT VT = Op.getValueType();
6188 bool IllegalFPCMov = false;
6189 if (VT.isFloatingPoint() && !VT.isVector() &&
6190 !isScalarFPTypeInSSEReg(VT)) // FPStack?
6191 IllegalFPCMov = !hasFPCMov(cast<ConstantSDNode>(CC)->getSExtValue());
6193 if ((isX86LogicalCmp(Cmp) && !IllegalFPCMov) ||
6194 Opc == X86ISD::BT) { // FIXME
6201 // Look pass the truncate.
6202 if (Cond.getOpcode() == ISD::TRUNCATE)
6203 Cond = Cond.getOperand(0);
6205 // We know the result of AND is compared against zero. Try to match
6207 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
6208 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, dl, DAG);
6209 if (NewSetCC.getNode()) {
6210 CC = NewSetCC.getOperand(0);
6211 Cond = NewSetCC.getOperand(1);
6218 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
6219 Cond = EmitTest(Cond, X86::COND_NE, DAG);
6222 // X86ISD::CMOV means set the result (which is operand 1) to the RHS if
6223 // condition is true.
6224 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Flag);
6225 SDValue Ops[] = { Op2, Op1, CC, Cond };
6226 return DAG.getNode(X86ISD::CMOV, dl, VTs, Ops, array_lengthof(Ops));
6229 // isAndOrOfSingleUseSetCCs - Return true if node is an ISD::AND or
6230 // ISD::OR of two X86ISD::SETCC nodes each of which has no other use apart
6231 // from the AND / OR.
6232 static bool isAndOrOfSetCCs(SDValue Op, unsigned &Opc) {
6233 Opc = Op.getOpcode();
6234 if (Opc != ISD::OR && Opc != ISD::AND)
6236 return (Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
6237 Op.getOperand(0).hasOneUse() &&
6238 Op.getOperand(1).getOpcode() == X86ISD::SETCC &&
6239 Op.getOperand(1).hasOneUse());
6242 // isXor1OfSetCC - Return true if node is an ISD::XOR of a X86ISD::SETCC and
6243 // 1 and that the SETCC node has a single use.
6244 static bool isXor1OfSetCC(SDValue Op) {
6245 if (Op.getOpcode() != ISD::XOR)
6247 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
6248 if (N1C && N1C->getAPIntValue() == 1) {
6249 return Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
6250 Op.getOperand(0).hasOneUse();
6255 SDValue X86TargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) {
6256 bool addTest = true;
6257 SDValue Chain = Op.getOperand(0);
6258 SDValue Cond = Op.getOperand(1);
6259 SDValue Dest = Op.getOperand(2);
6260 DebugLoc dl = Op.getDebugLoc();
6263 if (Cond.getOpcode() == ISD::SETCC) {
6264 SDValue NewCond = LowerSETCC(Cond, DAG);
6265 if (NewCond.getNode())
6269 // FIXME: LowerXALUO doesn't handle these!!
6270 else if (Cond.getOpcode() == X86ISD::ADD ||
6271 Cond.getOpcode() == X86ISD::SUB ||
6272 Cond.getOpcode() == X86ISD::SMUL ||
6273 Cond.getOpcode() == X86ISD::UMUL)
6274 Cond = LowerXALUO(Cond, DAG);
6277 // Look pass (and (setcc_carry (cmp ...)), 1).
6278 if (Cond.getOpcode() == ISD::AND &&
6279 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
6280 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
6281 if (C && C->getAPIntValue() == 1)
6282 Cond = Cond.getOperand(0);
6285 // If condition flag is set by a X86ISD::CMP, then use it as the condition
6286 // setting operand in place of the X86ISD::SETCC.
6287 if (Cond.getOpcode() == X86ISD::SETCC ||
6288 Cond.getOpcode() == X86ISD::SETCC_CARRY) {
6289 CC = Cond.getOperand(0);
6291 SDValue Cmp = Cond.getOperand(1);
6292 unsigned Opc = Cmp.getOpcode();
6293 // FIXME: WHY THE SPECIAL CASING OF LogicalCmp??
6294 if (isX86LogicalCmp(Cmp) || Opc == X86ISD::BT) {
6298 switch (cast<ConstantSDNode>(CC)->getZExtValue()) {
6302 // These can only come from an arithmetic instruction with overflow,
6303 // e.g. SADDO, UADDO.
6304 Cond = Cond.getNode()->getOperand(1);
6311 if (Cond.hasOneUse() && isAndOrOfSetCCs(Cond, CondOpc)) {
6312 SDValue Cmp = Cond.getOperand(0).getOperand(1);
6313 if (CondOpc == ISD::OR) {
6314 // Also, recognize the pattern generated by an FCMP_UNE. We can emit
6315 // two branches instead of an explicit OR instruction with a
6317 if (Cmp == Cond.getOperand(1).getOperand(1) &&
6318 isX86LogicalCmp(Cmp)) {
6319 CC = Cond.getOperand(0).getOperand(0);
6320 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
6321 Chain, Dest, CC, Cmp);
6322 CC = Cond.getOperand(1).getOperand(0);
6326 } else { // ISD::AND
6327 // Also, recognize the pattern generated by an FCMP_OEQ. We can emit
6328 // two branches instead of an explicit AND instruction with a
6329 // separate test. However, we only do this if this block doesn't
6330 // have a fall-through edge, because this requires an explicit
6331 // jmp when the condition is false.
6332 if (Cmp == Cond.getOperand(1).getOperand(1) &&
6333 isX86LogicalCmp(Cmp) &&
6334 Op.getNode()->hasOneUse()) {
6335 X86::CondCode CCode =
6336 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
6337 CCode = X86::GetOppositeBranchCondition(CCode);
6338 CC = DAG.getConstant(CCode, MVT::i8);
6339 SDValue User = SDValue(*Op.getNode()->use_begin(), 0);
6340 // Look for an unconditional branch following this conditional branch.
6341 // We need this because we need to reverse the successors in order
6342 // to implement FCMP_OEQ.
6343 if (User.getOpcode() == ISD::BR) {
6344 SDValue FalseBB = User.getOperand(1);
6346 DAG.UpdateNodeOperands(User, User.getOperand(0), Dest);
6347 assert(NewBR == User);
6350 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
6351 Chain, Dest, CC, Cmp);
6352 X86::CondCode CCode =
6353 (X86::CondCode)Cond.getOperand(1).getConstantOperandVal(0);
6354 CCode = X86::GetOppositeBranchCondition(CCode);
6355 CC = DAG.getConstant(CCode, MVT::i8);
6361 } else if (Cond.hasOneUse() && isXor1OfSetCC(Cond)) {
6362 // Recognize for xorb (setcc), 1 patterns. The xor inverts the condition.
6363 // It should be transformed during dag combiner except when the condition
6364 // is set by a arithmetics with overflow node.
6365 X86::CondCode CCode =
6366 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
6367 CCode = X86::GetOppositeBranchCondition(CCode);
6368 CC = DAG.getConstant(CCode, MVT::i8);
6369 Cond = Cond.getOperand(0).getOperand(1);
6375 // Look pass the truncate.
6376 if (Cond.getOpcode() == ISD::TRUNCATE)
6377 Cond = Cond.getOperand(0);
6379 // We know the result of AND is compared against zero. Try to match
6381 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
6382 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, dl, DAG);
6383 if (NewSetCC.getNode()) {
6384 CC = NewSetCC.getOperand(0);
6385 Cond = NewSetCC.getOperand(1);
6392 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
6393 Cond = EmitTest(Cond, X86::COND_NE, DAG);
6395 return DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
6396 Chain, Dest, CC, Cond);
6400 // Lower dynamic stack allocation to _alloca call for Cygwin/Mingw targets.
6401 // Calls to _alloca is needed to probe the stack when allocating more than 4k
6402 // bytes in one go. Touching the stack at 4K increments is necessary to ensure
6403 // that the guard pages used by the OS virtual memory manager are allocated in
6404 // correct sequence.
6406 X86TargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
6407 SelectionDAG &DAG) {
6408 assert(Subtarget->isTargetCygMing() &&
6409 "This should be used only on Cygwin/Mingw targets");
6410 DebugLoc dl = Op.getDebugLoc();
6413 SDValue Chain = Op.getOperand(0);
6414 SDValue Size = Op.getOperand(1);
6415 // FIXME: Ensure alignment here
6419 EVT IntPtr = getPointerTy();
6420 EVT SPTy = Subtarget->is64Bit() ? MVT::i64 : MVT::i32;
6422 Chain = DAG.getCopyToReg(Chain, dl, X86::EAX, Size, Flag);
6423 Flag = Chain.getValue(1);
6425 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
6427 Chain = DAG.getNode(X86ISD::MINGW_ALLOCA, dl, NodeTys, Chain, Flag);
6428 Flag = Chain.getValue(1);
6430 Chain = DAG.getCopyFromReg(Chain, dl, X86StackPtr, SPTy).getValue(1);
6432 SDValue Ops1[2] = { Chain.getValue(0), Chain };
6433 return DAG.getMergeValues(Ops1, 2, dl);
6437 X86TargetLowering::EmitTargetCodeForMemset(SelectionDAG &DAG, DebugLoc dl,
6439 SDValue Dst, SDValue Src,
6440 SDValue Size, unsigned Align,
6442 uint64_t DstSVOff) {
6443 ConstantSDNode *ConstantSize = dyn_cast<ConstantSDNode>(Size);
6445 // If not DWORD aligned or size is more than the threshold, call the library.
6446 // The libc version is likely to be faster for these cases. It can use the
6447 // address value and run time information about the CPU.
6448 if ((Align & 3) != 0 ||
6450 ConstantSize->getZExtValue() >
6451 getSubtarget()->getMaxInlineSizeThreshold()) {
6452 SDValue InFlag(0, 0);
6454 // Check to see if there is a specialized entry-point for memory zeroing.
6455 ConstantSDNode *V = dyn_cast<ConstantSDNode>(Src);
6457 if (const char *bzeroEntry = V &&
6458 V->isNullValue() ? Subtarget->getBZeroEntry() : 0) {
6459 EVT IntPtr = getPointerTy();
6460 const Type *IntPtrTy = TD->getIntPtrType(*DAG.getContext());
6461 TargetLowering::ArgListTy Args;
6462 TargetLowering::ArgListEntry Entry;
6464 Entry.Ty = IntPtrTy;
6465 Args.push_back(Entry);
6467 Args.push_back(Entry);
6468 std::pair<SDValue,SDValue> CallResult =
6469 LowerCallTo(Chain, Type::getVoidTy(*DAG.getContext()),
6470 false, false, false, false,
6471 0, CallingConv::C, false, /*isReturnValueUsed=*/false,
6472 DAG.getExternalSymbol(bzeroEntry, IntPtr), Args, DAG, dl);
6473 return CallResult.second;
6476 // Otherwise have the target-independent code call memset.
6480 uint64_t SizeVal = ConstantSize->getZExtValue();
6481 SDValue InFlag(0, 0);
6484 ConstantSDNode *ValC = dyn_cast<ConstantSDNode>(Src);
6485 unsigned BytesLeft = 0;
6486 bool TwoRepStos = false;
6489 uint64_t Val = ValC->getZExtValue() & 255;
6491 // If the value is a constant, then we can potentially use larger sets.
6492 switch (Align & 3) {
6493 case 2: // WORD aligned
6496 Val = (Val << 8) | Val;
6498 case 0: // DWORD aligned
6501 Val = (Val << 8) | Val;
6502 Val = (Val << 16) | Val;
6503 if (Subtarget->is64Bit() && ((Align & 0x7) == 0)) { // QWORD aligned
6506 Val = (Val << 32) | Val;
6509 default: // Byte aligned
6512 Count = DAG.getIntPtrConstant(SizeVal);
6516 if (AVT.bitsGT(MVT::i8)) {
6517 unsigned UBytes = AVT.getSizeInBits() / 8;
6518 Count = DAG.getIntPtrConstant(SizeVal / UBytes);
6519 BytesLeft = SizeVal % UBytes;
6522 Chain = DAG.getCopyToReg(Chain, dl, ValReg, DAG.getConstant(Val, AVT),
6524 InFlag = Chain.getValue(1);
6527 Count = DAG.getIntPtrConstant(SizeVal);
6528 Chain = DAG.getCopyToReg(Chain, dl, X86::AL, Src, InFlag);
6529 InFlag = Chain.getValue(1);
6532 Chain = DAG.getCopyToReg(Chain, dl, Subtarget->is64Bit() ? X86::RCX :
6535 InFlag = Chain.getValue(1);
6536 Chain = DAG.getCopyToReg(Chain, dl, Subtarget->is64Bit() ? X86::RDI :
6539 InFlag = Chain.getValue(1);
6541 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
6542 SDValue Ops[] = { Chain, DAG.getValueType(AVT), InFlag };
6543 Chain = DAG.getNode(X86ISD::REP_STOS, dl, Tys, Ops, array_lengthof(Ops));
6546 InFlag = Chain.getValue(1);
6548 EVT CVT = Count.getValueType();
6549 SDValue Left = DAG.getNode(ISD::AND, dl, CVT, Count,
6550 DAG.getConstant((AVT == MVT::i64) ? 7 : 3, CVT));
6551 Chain = DAG.getCopyToReg(Chain, dl, (CVT == MVT::i64) ? X86::RCX :
6554 InFlag = Chain.getValue(1);
6555 Tys = DAG.getVTList(MVT::Other, MVT::Flag);
6556 SDValue Ops[] = { Chain, DAG.getValueType(MVT::i8), InFlag };
6557 Chain = DAG.getNode(X86ISD::REP_STOS, dl, Tys, Ops, array_lengthof(Ops));
6558 } else if (BytesLeft) {
6559 // Handle the last 1 - 7 bytes.
6560 unsigned Offset = SizeVal - BytesLeft;
6561 EVT AddrVT = Dst.getValueType();
6562 EVT SizeVT = Size.getValueType();
6564 Chain = DAG.getMemset(Chain, dl,
6565 DAG.getNode(ISD::ADD, dl, AddrVT, Dst,
6566 DAG.getConstant(Offset, AddrVT)),
6568 DAG.getConstant(BytesLeft, SizeVT),
6569 Align, DstSV, DstSVOff + Offset);
6572 // TODO: Use a Tokenfactor, as in memcpy, instead of a single chain.
6577 X86TargetLowering::EmitTargetCodeForMemcpy(SelectionDAG &DAG, DebugLoc dl,
6578 SDValue Chain, SDValue Dst, SDValue Src,
6579 SDValue Size, unsigned Align,
6581 const Value *DstSV, uint64_t DstSVOff,
6582 const Value *SrcSV, uint64_t SrcSVOff) {
6583 // This requires the copy size to be a constant, preferrably
6584 // within a subtarget-specific limit.
6585 ConstantSDNode *ConstantSize = dyn_cast<ConstantSDNode>(Size);
6588 uint64_t SizeVal = ConstantSize->getZExtValue();
6589 if (!AlwaysInline && SizeVal > getSubtarget()->getMaxInlineSizeThreshold())
6592 /// If not DWORD aligned, call the library.
6593 if ((Align & 3) != 0)
6598 if (Subtarget->is64Bit() && ((Align & 0x7) == 0)) // QWORD aligned
6601 unsigned UBytes = AVT.getSizeInBits() / 8;
6602 unsigned CountVal = SizeVal / UBytes;
6603 SDValue Count = DAG.getIntPtrConstant(CountVal);
6604 unsigned BytesLeft = SizeVal % UBytes;
6606 SDValue InFlag(0, 0);
6607 Chain = DAG.getCopyToReg(Chain, dl, Subtarget->is64Bit() ? X86::RCX :
6610 InFlag = Chain.getValue(1);
6611 Chain = DAG.getCopyToReg(Chain, dl, Subtarget->is64Bit() ? X86::RDI :
6614 InFlag = Chain.getValue(1);
6615 Chain = DAG.getCopyToReg(Chain, dl, Subtarget->is64Bit() ? X86::RSI :
6618 InFlag = Chain.getValue(1);
6620 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
6621 SDValue Ops[] = { Chain, DAG.getValueType(AVT), InFlag };
6622 SDValue RepMovs = DAG.getNode(X86ISD::REP_MOVS, dl, Tys, Ops,
6623 array_lengthof(Ops));
6625 SmallVector<SDValue, 4> Results;
6626 Results.push_back(RepMovs);
6628 // Handle the last 1 - 7 bytes.
6629 unsigned Offset = SizeVal - BytesLeft;
6630 EVT DstVT = Dst.getValueType();
6631 EVT SrcVT = Src.getValueType();
6632 EVT SizeVT = Size.getValueType();
6633 Results.push_back(DAG.getMemcpy(Chain, dl,
6634 DAG.getNode(ISD::ADD, dl, DstVT, Dst,
6635 DAG.getConstant(Offset, DstVT)),
6636 DAG.getNode(ISD::ADD, dl, SrcVT, Src,
6637 DAG.getConstant(Offset, SrcVT)),
6638 DAG.getConstant(BytesLeft, SizeVT),
6639 Align, AlwaysInline,
6640 DstSV, DstSVOff + Offset,
6641 SrcSV, SrcSVOff + Offset));
6644 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
6645 &Results[0], Results.size());
6648 SDValue X86TargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) {
6649 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
6650 DebugLoc dl = Op.getDebugLoc();
6652 if (!Subtarget->is64Bit()) {
6653 // vastart just stores the address of the VarArgsFrameIndex slot into the
6654 // memory location argument.
6655 SDValue FR = DAG.getFrameIndex(VarArgsFrameIndex, getPointerTy());
6656 return DAG.getStore(Op.getOperand(0), dl, FR, Op.getOperand(1), SV, 0,
6661 // gp_offset (0 - 6 * 8)
6662 // fp_offset (48 - 48 + 8 * 16)
6663 // overflow_arg_area (point to parameters coming in memory).
6665 SmallVector<SDValue, 8> MemOps;
6666 SDValue FIN = Op.getOperand(1);
6668 SDValue Store = DAG.getStore(Op.getOperand(0), dl,
6669 DAG.getConstant(VarArgsGPOffset, MVT::i32),
6670 FIN, SV, 0, false, false, 0);
6671 MemOps.push_back(Store);
6674 FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(),
6675 FIN, DAG.getIntPtrConstant(4));
6676 Store = DAG.getStore(Op.getOperand(0), dl,
6677 DAG.getConstant(VarArgsFPOffset, MVT::i32),
6678 FIN, SV, 0, false, false, 0);
6679 MemOps.push_back(Store);
6681 // Store ptr to overflow_arg_area
6682 FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(),
6683 FIN, DAG.getIntPtrConstant(4));
6684 SDValue OVFIN = DAG.getFrameIndex(VarArgsFrameIndex, getPointerTy());
6685 Store = DAG.getStore(Op.getOperand(0), dl, OVFIN, FIN, SV, 0,
6687 MemOps.push_back(Store);
6689 // Store ptr to reg_save_area.
6690 FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(),
6691 FIN, DAG.getIntPtrConstant(8));
6692 SDValue RSFIN = DAG.getFrameIndex(RegSaveFrameIndex, getPointerTy());
6693 Store = DAG.getStore(Op.getOperand(0), dl, RSFIN, FIN, SV, 0,
6695 MemOps.push_back(Store);
6696 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
6697 &MemOps[0], MemOps.size());
6700 SDValue X86TargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG) {
6701 // X86-64 va_list is a struct { i32, i32, i8*, i8* }.
6702 assert(Subtarget->is64Bit() && "This code only handles 64-bit va_arg!");
6703 SDValue Chain = Op.getOperand(0);
6704 SDValue SrcPtr = Op.getOperand(1);
6705 SDValue SrcSV = Op.getOperand(2);
6707 llvm_report_error("VAArgInst is not yet implemented for x86-64!");
6711 SDValue X86TargetLowering::LowerVACOPY(SDValue Op, SelectionDAG &DAG) {
6712 // X86-64 va_list is a struct { i32, i32, i8*, i8* }.
6713 assert(Subtarget->is64Bit() && "This code only handles 64-bit va_copy!");
6714 SDValue Chain = Op.getOperand(0);
6715 SDValue DstPtr = Op.getOperand(1);
6716 SDValue SrcPtr = Op.getOperand(2);
6717 const Value *DstSV = cast<SrcValueSDNode>(Op.getOperand(3))->getValue();
6718 const Value *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
6719 DebugLoc dl = Op.getDebugLoc();
6721 return DAG.getMemcpy(Chain, dl, DstPtr, SrcPtr,
6722 DAG.getIntPtrConstant(24), 8, false,
6723 DstSV, 0, SrcSV, 0);
6727 X86TargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) {
6728 DebugLoc dl = Op.getDebugLoc();
6729 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
6731 default: return SDValue(); // Don't custom lower most intrinsics.
6732 // Comparison intrinsics.
6733 case Intrinsic::x86_sse_comieq_ss:
6734 case Intrinsic::x86_sse_comilt_ss:
6735 case Intrinsic::x86_sse_comile_ss:
6736 case Intrinsic::x86_sse_comigt_ss:
6737 case Intrinsic::x86_sse_comige_ss:
6738 case Intrinsic::x86_sse_comineq_ss:
6739 case Intrinsic::x86_sse_ucomieq_ss:
6740 case Intrinsic::x86_sse_ucomilt_ss:
6741 case Intrinsic::x86_sse_ucomile_ss:
6742 case Intrinsic::x86_sse_ucomigt_ss:
6743 case Intrinsic::x86_sse_ucomige_ss:
6744 case Intrinsic::x86_sse_ucomineq_ss:
6745 case Intrinsic::x86_sse2_comieq_sd:
6746 case Intrinsic::x86_sse2_comilt_sd:
6747 case Intrinsic::x86_sse2_comile_sd:
6748 case Intrinsic::x86_sse2_comigt_sd:
6749 case Intrinsic::x86_sse2_comige_sd:
6750 case Intrinsic::x86_sse2_comineq_sd:
6751 case Intrinsic::x86_sse2_ucomieq_sd:
6752 case Intrinsic::x86_sse2_ucomilt_sd:
6753 case Intrinsic::x86_sse2_ucomile_sd:
6754 case Intrinsic::x86_sse2_ucomigt_sd:
6755 case Intrinsic::x86_sse2_ucomige_sd:
6756 case Intrinsic::x86_sse2_ucomineq_sd: {
6758 ISD::CondCode CC = ISD::SETCC_INVALID;
6761 case Intrinsic::x86_sse_comieq_ss:
6762 case Intrinsic::x86_sse2_comieq_sd:
6766 case Intrinsic::x86_sse_comilt_ss:
6767 case Intrinsic::x86_sse2_comilt_sd:
6771 case Intrinsic::x86_sse_comile_ss:
6772 case Intrinsic::x86_sse2_comile_sd:
6776 case Intrinsic::x86_sse_comigt_ss:
6777 case Intrinsic::x86_sse2_comigt_sd:
6781 case Intrinsic::x86_sse_comige_ss:
6782 case Intrinsic::x86_sse2_comige_sd:
6786 case Intrinsic::x86_sse_comineq_ss:
6787 case Intrinsic::x86_sse2_comineq_sd:
6791 case Intrinsic::x86_sse_ucomieq_ss:
6792 case Intrinsic::x86_sse2_ucomieq_sd:
6793 Opc = X86ISD::UCOMI;
6796 case Intrinsic::x86_sse_ucomilt_ss:
6797 case Intrinsic::x86_sse2_ucomilt_sd:
6798 Opc = X86ISD::UCOMI;
6801 case Intrinsic::x86_sse_ucomile_ss:
6802 case Intrinsic::x86_sse2_ucomile_sd:
6803 Opc = X86ISD::UCOMI;
6806 case Intrinsic::x86_sse_ucomigt_ss:
6807 case Intrinsic::x86_sse2_ucomigt_sd:
6808 Opc = X86ISD::UCOMI;
6811 case Intrinsic::x86_sse_ucomige_ss:
6812 case Intrinsic::x86_sse2_ucomige_sd:
6813 Opc = X86ISD::UCOMI;
6816 case Intrinsic::x86_sse_ucomineq_ss:
6817 case Intrinsic::x86_sse2_ucomineq_sd:
6818 Opc = X86ISD::UCOMI;
6823 SDValue LHS = Op.getOperand(1);
6824 SDValue RHS = Op.getOperand(2);
6825 unsigned X86CC = TranslateX86CC(CC, true, LHS, RHS, DAG);
6826 assert(X86CC != X86::COND_INVALID && "Unexpected illegal condition!");
6827 SDValue Cond = DAG.getNode(Opc, dl, MVT::i32, LHS, RHS);
6828 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
6829 DAG.getConstant(X86CC, MVT::i8), Cond);
6830 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
6832 // ptest intrinsics. The intrinsic these come from are designed to return
6833 // an integer value, not just an instruction so lower it to the ptest
6834 // pattern and a setcc for the result.
6835 case Intrinsic::x86_sse41_ptestz:
6836 case Intrinsic::x86_sse41_ptestc:
6837 case Intrinsic::x86_sse41_ptestnzc:{
6840 default: llvm_unreachable("Bad fallthrough in Intrinsic lowering.");
6841 case Intrinsic::x86_sse41_ptestz:
6843 X86CC = X86::COND_E;
6845 case Intrinsic::x86_sse41_ptestc:
6847 X86CC = X86::COND_B;
6849 case Intrinsic::x86_sse41_ptestnzc:
6851 X86CC = X86::COND_A;
6855 SDValue LHS = Op.getOperand(1);
6856 SDValue RHS = Op.getOperand(2);
6857 SDValue Test = DAG.getNode(X86ISD::PTEST, dl, MVT::i32, LHS, RHS);
6858 SDValue CC = DAG.getConstant(X86CC, MVT::i8);
6859 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8, CC, Test);
6860 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
6863 // Fix vector shift instructions where the last operand is a non-immediate
6865 case Intrinsic::x86_sse2_pslli_w:
6866 case Intrinsic::x86_sse2_pslli_d:
6867 case Intrinsic::x86_sse2_pslli_q:
6868 case Intrinsic::x86_sse2_psrli_w:
6869 case Intrinsic::x86_sse2_psrli_d:
6870 case Intrinsic::x86_sse2_psrli_q:
6871 case Intrinsic::x86_sse2_psrai_w:
6872 case Intrinsic::x86_sse2_psrai_d:
6873 case Intrinsic::x86_mmx_pslli_w:
6874 case Intrinsic::x86_mmx_pslli_d:
6875 case Intrinsic::x86_mmx_pslli_q:
6876 case Intrinsic::x86_mmx_psrli_w:
6877 case Intrinsic::x86_mmx_psrli_d:
6878 case Intrinsic::x86_mmx_psrli_q:
6879 case Intrinsic::x86_mmx_psrai_w:
6880 case Intrinsic::x86_mmx_psrai_d: {
6881 SDValue ShAmt = Op.getOperand(2);
6882 if (isa<ConstantSDNode>(ShAmt))
6885 unsigned NewIntNo = 0;
6886 EVT ShAmtVT = MVT::v4i32;
6888 case Intrinsic::x86_sse2_pslli_w:
6889 NewIntNo = Intrinsic::x86_sse2_psll_w;
6891 case Intrinsic::x86_sse2_pslli_d:
6892 NewIntNo = Intrinsic::x86_sse2_psll_d;
6894 case Intrinsic::x86_sse2_pslli_q:
6895 NewIntNo = Intrinsic::x86_sse2_psll_q;
6897 case Intrinsic::x86_sse2_psrli_w:
6898 NewIntNo = Intrinsic::x86_sse2_psrl_w;
6900 case Intrinsic::x86_sse2_psrli_d:
6901 NewIntNo = Intrinsic::x86_sse2_psrl_d;
6903 case Intrinsic::x86_sse2_psrli_q:
6904 NewIntNo = Intrinsic::x86_sse2_psrl_q;
6906 case Intrinsic::x86_sse2_psrai_w:
6907 NewIntNo = Intrinsic::x86_sse2_psra_w;
6909 case Intrinsic::x86_sse2_psrai_d:
6910 NewIntNo = Intrinsic::x86_sse2_psra_d;
6913 ShAmtVT = MVT::v2i32;
6915 case Intrinsic::x86_mmx_pslli_w:
6916 NewIntNo = Intrinsic::x86_mmx_psll_w;
6918 case Intrinsic::x86_mmx_pslli_d:
6919 NewIntNo = Intrinsic::x86_mmx_psll_d;
6921 case Intrinsic::x86_mmx_pslli_q:
6922 NewIntNo = Intrinsic::x86_mmx_psll_q;
6924 case Intrinsic::x86_mmx_psrli_w:
6925 NewIntNo = Intrinsic::x86_mmx_psrl_w;
6927 case Intrinsic::x86_mmx_psrli_d:
6928 NewIntNo = Intrinsic::x86_mmx_psrl_d;
6930 case Intrinsic::x86_mmx_psrli_q:
6931 NewIntNo = Intrinsic::x86_mmx_psrl_q;
6933 case Intrinsic::x86_mmx_psrai_w:
6934 NewIntNo = Intrinsic::x86_mmx_psra_w;
6936 case Intrinsic::x86_mmx_psrai_d:
6937 NewIntNo = Intrinsic::x86_mmx_psra_d;
6939 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
6945 // The vector shift intrinsics with scalars uses 32b shift amounts but
6946 // the sse2/mmx shift instructions reads 64 bits. Set the upper 32 bits
6950 ShOps[1] = DAG.getConstant(0, MVT::i32);
6951 if (ShAmtVT == MVT::v4i32) {
6952 ShOps[2] = DAG.getUNDEF(MVT::i32);
6953 ShOps[3] = DAG.getUNDEF(MVT::i32);
6954 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, ShAmtVT, &ShOps[0], 4);
6956 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, ShAmtVT, &ShOps[0], 2);
6959 EVT VT = Op.getValueType();
6960 ShAmt = DAG.getNode(ISD::BIT_CONVERT, dl, VT, ShAmt);
6961 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
6962 DAG.getConstant(NewIntNo, MVT::i32),
6963 Op.getOperand(1), ShAmt);
6968 SDValue X86TargetLowering::LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) {
6969 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
6970 DebugLoc dl = Op.getDebugLoc();
6973 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
6975 DAG.getConstant(TD->getPointerSize(),
6976 Subtarget->is64Bit() ? MVT::i64 : MVT::i32);
6977 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(),
6978 DAG.getNode(ISD::ADD, dl, getPointerTy(),
6980 NULL, 0, false, false, 0);
6983 // Just load the return address.
6984 SDValue RetAddrFI = getReturnAddressFrameIndex(DAG);
6985 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(),
6986 RetAddrFI, NULL, 0, false, false, 0);
6989 SDValue X86TargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) {
6990 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
6991 MFI->setFrameAddressIsTaken(true);
6992 EVT VT = Op.getValueType();
6993 DebugLoc dl = Op.getDebugLoc(); // FIXME probably not meaningful
6994 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
6995 unsigned FrameReg = Subtarget->is64Bit() ? X86::RBP : X86::EBP;
6996 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT);
6998 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr, NULL, 0,
7003 SDValue X86TargetLowering::LowerFRAME_TO_ARGS_OFFSET(SDValue Op,
7004 SelectionDAG &DAG) {
7005 return DAG.getIntPtrConstant(2*TD->getPointerSize());
7008 SDValue X86TargetLowering::LowerEH_RETURN(SDValue Op, SelectionDAG &DAG)
7010 MachineFunction &MF = DAG.getMachineFunction();
7011 SDValue Chain = Op.getOperand(0);
7012 SDValue Offset = Op.getOperand(1);
7013 SDValue Handler = Op.getOperand(2);
7014 DebugLoc dl = Op.getDebugLoc();
7016 SDValue Frame = DAG.getRegister(Subtarget->is64Bit() ? X86::RBP : X86::EBP,
7018 unsigned StoreAddrReg = (Subtarget->is64Bit() ? X86::RCX : X86::ECX);
7020 SDValue StoreAddr = DAG.getNode(ISD::SUB, dl, getPointerTy(), Frame,
7021 DAG.getIntPtrConstant(-TD->getPointerSize()));
7022 StoreAddr = DAG.getNode(ISD::ADD, dl, getPointerTy(), StoreAddr, Offset);
7023 Chain = DAG.getStore(Chain, dl, Handler, StoreAddr, NULL, 0, false, false, 0);
7024 Chain = DAG.getCopyToReg(Chain, dl, StoreAddrReg, StoreAddr);
7025 MF.getRegInfo().addLiveOut(StoreAddrReg);
7027 return DAG.getNode(X86ISD::EH_RETURN, dl,
7029 Chain, DAG.getRegister(StoreAddrReg, getPointerTy()));
7032 SDValue X86TargetLowering::LowerTRAMPOLINE(SDValue Op,
7033 SelectionDAG &DAG) {
7034 SDValue Root = Op.getOperand(0);
7035 SDValue Trmp = Op.getOperand(1); // trampoline
7036 SDValue FPtr = Op.getOperand(2); // nested function
7037 SDValue Nest = Op.getOperand(3); // 'nest' parameter value
7038 DebugLoc dl = Op.getDebugLoc();
7040 const Value *TrmpAddr = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
7042 if (Subtarget->is64Bit()) {
7043 SDValue OutChains[6];
7045 // Large code-model.
7046 const unsigned char JMP64r = 0xFF; // 64-bit jmp through register opcode.
7047 const unsigned char MOV64ri = 0xB8; // X86::MOV64ri opcode.
7049 const unsigned char N86R10 = RegInfo->getX86RegNum(X86::R10);
7050 const unsigned char N86R11 = RegInfo->getX86RegNum(X86::R11);
7052 const unsigned char REX_WB = 0x40 | 0x08 | 0x01; // REX prefix
7054 // Load the pointer to the nested function into R11.
7055 unsigned OpCode = ((MOV64ri | N86R11) << 8) | REX_WB; // movabsq r11
7056 SDValue Addr = Trmp;
7057 OutChains[0] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
7058 Addr, TrmpAddr, 0, false, false, 0);
7060 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
7061 DAG.getConstant(2, MVT::i64));
7062 OutChains[1] = DAG.getStore(Root, dl, FPtr, Addr, TrmpAddr, 2,
7065 // Load the 'nest' parameter value into R10.
7066 // R10 is specified in X86CallingConv.td
7067 OpCode = ((MOV64ri | N86R10) << 8) | REX_WB; // movabsq r10
7068 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
7069 DAG.getConstant(10, MVT::i64));
7070 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
7071 Addr, TrmpAddr, 10, false, false, 0);
7073 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
7074 DAG.getConstant(12, MVT::i64));
7075 OutChains[3] = DAG.getStore(Root, dl, Nest, Addr, TrmpAddr, 12,
7078 // Jump to the nested function.
7079 OpCode = (JMP64r << 8) | REX_WB; // jmpq *...
7080 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
7081 DAG.getConstant(20, MVT::i64));
7082 OutChains[4] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
7083 Addr, TrmpAddr, 20, false, false, 0);
7085 unsigned char ModRM = N86R11 | (4 << 3) | (3 << 6); // ...r11
7086 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
7087 DAG.getConstant(22, MVT::i64));
7088 OutChains[5] = DAG.getStore(Root, dl, DAG.getConstant(ModRM, MVT::i8), Addr,
7089 TrmpAddr, 22, false, false, 0);
7092 { Trmp, DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains, 6) };
7093 return DAG.getMergeValues(Ops, 2, dl);
7095 const Function *Func =
7096 cast<Function>(cast<SrcValueSDNode>(Op.getOperand(5))->getValue());
7097 CallingConv::ID CC = Func->getCallingConv();
7102 llvm_unreachable("Unsupported calling convention");
7103 case CallingConv::C:
7104 case CallingConv::X86_StdCall: {
7105 // Pass 'nest' parameter in ECX.
7106 // Must be kept in sync with X86CallingConv.td
7109 // Check that ECX wasn't needed by an 'inreg' parameter.
7110 const FunctionType *FTy = Func->getFunctionType();
7111 const AttrListPtr &Attrs = Func->getAttributes();
7113 if (!Attrs.isEmpty() && !Func->isVarArg()) {
7114 unsigned InRegCount = 0;
7117 for (FunctionType::param_iterator I = FTy->param_begin(),
7118 E = FTy->param_end(); I != E; ++I, ++Idx)
7119 if (Attrs.paramHasAttr(Idx, Attribute::InReg))
7120 // FIXME: should only count parameters that are lowered to integers.
7121 InRegCount += (TD->getTypeSizeInBits(*I) + 31) / 32;
7123 if (InRegCount > 2) {
7124 llvm_report_error("Nest register in use - reduce number of inreg parameters!");
7129 case CallingConv::X86_FastCall:
7130 case CallingConv::Fast:
7131 // Pass 'nest' parameter in EAX.
7132 // Must be kept in sync with X86CallingConv.td
7137 SDValue OutChains[4];
7140 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
7141 DAG.getConstant(10, MVT::i32));
7142 Disp = DAG.getNode(ISD::SUB, dl, MVT::i32, FPtr, Addr);
7144 // This is storing the opcode for MOV32ri.
7145 const unsigned char MOV32ri = 0xB8; // X86::MOV32ri's opcode byte.
7146 const unsigned char N86Reg = RegInfo->getX86RegNum(NestReg);
7147 OutChains[0] = DAG.getStore(Root, dl,
7148 DAG.getConstant(MOV32ri|N86Reg, MVT::i8),
7149 Trmp, TrmpAddr, 0, false, false, 0);
7151 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
7152 DAG.getConstant(1, MVT::i32));
7153 OutChains[1] = DAG.getStore(Root, dl, Nest, Addr, TrmpAddr, 1,
7156 const unsigned char JMP = 0xE9; // jmp <32bit dst> opcode.
7157 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
7158 DAG.getConstant(5, MVT::i32));
7159 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(JMP, MVT::i8), Addr,
7160 TrmpAddr, 5, false, false, 1);
7162 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
7163 DAG.getConstant(6, MVT::i32));
7164 OutChains[3] = DAG.getStore(Root, dl, Disp, Addr, TrmpAddr, 6,
7168 { Trmp, DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains, 4) };
7169 return DAG.getMergeValues(Ops, 2, dl);
7173 SDValue X86TargetLowering::LowerFLT_ROUNDS_(SDValue Op, SelectionDAG &DAG) {
7175 The rounding mode is in bits 11:10 of FPSR, and has the following
7182 FLT_ROUNDS, on the other hand, expects the following:
7189 To perform the conversion, we do:
7190 (((((FPSR & 0x800) >> 11) | ((FPSR & 0x400) >> 9)) + 1) & 3)
7193 MachineFunction &MF = DAG.getMachineFunction();
7194 const TargetMachine &TM = MF.getTarget();
7195 const TargetFrameInfo &TFI = *TM.getFrameInfo();
7196 unsigned StackAlignment = TFI.getStackAlignment();
7197 EVT VT = Op.getValueType();
7198 DebugLoc dl = Op.getDebugLoc();
7200 // Save FP Control Word to stack slot
7201 int SSFI = MF.getFrameInfo()->CreateStackObject(2, StackAlignment, false);
7202 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
7204 SDValue Chain = DAG.getNode(X86ISD::FNSTCW16m, dl, MVT::Other,
7205 DAG.getEntryNode(), StackSlot);
7207 // Load FP Control Word from stack slot
7208 SDValue CWD = DAG.getLoad(MVT::i16, dl, Chain, StackSlot, NULL, 0,
7211 // Transform as necessary
7213 DAG.getNode(ISD::SRL, dl, MVT::i16,
7214 DAG.getNode(ISD::AND, dl, MVT::i16,
7215 CWD, DAG.getConstant(0x800, MVT::i16)),
7216 DAG.getConstant(11, MVT::i8));
7218 DAG.getNode(ISD::SRL, dl, MVT::i16,
7219 DAG.getNode(ISD::AND, dl, MVT::i16,
7220 CWD, DAG.getConstant(0x400, MVT::i16)),
7221 DAG.getConstant(9, MVT::i8));
7224 DAG.getNode(ISD::AND, dl, MVT::i16,
7225 DAG.getNode(ISD::ADD, dl, MVT::i16,
7226 DAG.getNode(ISD::OR, dl, MVT::i16, CWD1, CWD2),
7227 DAG.getConstant(1, MVT::i16)),
7228 DAG.getConstant(3, MVT::i16));
7231 return DAG.getNode((VT.getSizeInBits() < 16 ?
7232 ISD::TRUNCATE : ISD::ZERO_EXTEND), dl, VT, RetVal);
7235 SDValue X86TargetLowering::LowerCTLZ(SDValue Op, SelectionDAG &DAG) {
7236 EVT VT = Op.getValueType();
7238 unsigned NumBits = VT.getSizeInBits();
7239 DebugLoc dl = Op.getDebugLoc();
7241 Op = Op.getOperand(0);
7242 if (VT == MVT::i8) {
7243 // Zero extend to i32 since there is not an i8 bsr.
7245 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
7248 // Issue a bsr (scan bits in reverse) which also sets EFLAGS.
7249 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
7250 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
7252 // If src is zero (i.e. bsr sets ZF), returns NumBits.
7255 DAG.getConstant(NumBits+NumBits-1, OpVT),
7256 DAG.getConstant(X86::COND_E, MVT::i8),
7259 Op = DAG.getNode(X86ISD::CMOV, dl, OpVT, Ops, array_lengthof(Ops));
7261 // Finally xor with NumBits-1.
7262 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT));
7265 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
7269 SDValue X86TargetLowering::LowerCTTZ(SDValue Op, SelectionDAG &DAG) {
7270 EVT VT = Op.getValueType();
7272 unsigned NumBits = VT.getSizeInBits();
7273 DebugLoc dl = Op.getDebugLoc();
7275 Op = Op.getOperand(0);
7276 if (VT == MVT::i8) {
7278 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
7281 // Issue a bsf (scan bits forward) which also sets EFLAGS.
7282 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
7283 Op = DAG.getNode(X86ISD::BSF, dl, VTs, Op);
7285 // If src is zero (i.e. bsf sets ZF), returns NumBits.
7288 DAG.getConstant(NumBits, OpVT),
7289 DAG.getConstant(X86::COND_E, MVT::i8),
7292 Op = DAG.getNode(X86ISD::CMOV, dl, OpVT, Ops, array_lengthof(Ops));
7295 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
7299 SDValue X86TargetLowering::LowerMUL_V2I64(SDValue Op, SelectionDAG &DAG) {
7300 EVT VT = Op.getValueType();
7301 assert(VT == MVT::v2i64 && "Only know how to lower V2I64 multiply");
7302 DebugLoc dl = Op.getDebugLoc();
7304 // ulong2 Ahi = __builtin_ia32_psrlqi128( a, 32);
7305 // ulong2 Bhi = __builtin_ia32_psrlqi128( b, 32);
7306 // ulong2 AloBlo = __builtin_ia32_pmuludq128( a, b );
7307 // ulong2 AloBhi = __builtin_ia32_pmuludq128( a, Bhi );
7308 // ulong2 AhiBlo = __builtin_ia32_pmuludq128( Ahi, b );
7310 // AloBhi = __builtin_ia32_psllqi128( AloBhi, 32 );
7311 // AhiBlo = __builtin_ia32_psllqi128( AhiBlo, 32 );
7312 // return AloBlo + AloBhi + AhiBlo;
7314 SDValue A = Op.getOperand(0);
7315 SDValue B = Op.getOperand(1);
7317 SDValue Ahi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
7318 DAG.getConstant(Intrinsic::x86_sse2_psrli_q, MVT::i32),
7319 A, DAG.getConstant(32, MVT::i32));
7320 SDValue Bhi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
7321 DAG.getConstant(Intrinsic::x86_sse2_psrli_q, MVT::i32),
7322 B, DAG.getConstant(32, MVT::i32));
7323 SDValue AloBlo = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
7324 DAG.getConstant(Intrinsic::x86_sse2_pmulu_dq, MVT::i32),
7326 SDValue AloBhi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
7327 DAG.getConstant(Intrinsic::x86_sse2_pmulu_dq, MVT::i32),
7329 SDValue AhiBlo = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
7330 DAG.getConstant(Intrinsic::x86_sse2_pmulu_dq, MVT::i32),
7332 AloBhi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
7333 DAG.getConstant(Intrinsic::x86_sse2_pslli_q, MVT::i32),
7334 AloBhi, DAG.getConstant(32, MVT::i32));
7335 AhiBlo = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
7336 DAG.getConstant(Intrinsic::x86_sse2_pslli_q, MVT::i32),
7337 AhiBlo, DAG.getConstant(32, MVT::i32));
7338 SDValue Res = DAG.getNode(ISD::ADD, dl, VT, AloBlo, AloBhi);
7339 Res = DAG.getNode(ISD::ADD, dl, VT, Res, AhiBlo);
7344 SDValue X86TargetLowering::LowerXALUO(SDValue Op, SelectionDAG &DAG) {
7345 // Lower the "add/sub/mul with overflow" instruction into a regular ins plus
7346 // a "setcc" instruction that checks the overflow flag. The "brcond" lowering
7347 // looks for this combo and may remove the "setcc" instruction if the "setcc"
7348 // has only one use.
7349 SDNode *N = Op.getNode();
7350 SDValue LHS = N->getOperand(0);
7351 SDValue RHS = N->getOperand(1);
7352 unsigned BaseOp = 0;
7354 DebugLoc dl = Op.getDebugLoc();
7356 switch (Op.getOpcode()) {
7357 default: llvm_unreachable("Unknown ovf instruction!");
7359 // A subtract of one will be selected as a INC. Note that INC doesn't
7360 // set CF, so we can't do this for UADDO.
7361 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op))
7362 if (C->getAPIntValue() == 1) {
7363 BaseOp = X86ISD::INC;
7367 BaseOp = X86ISD::ADD;
7371 BaseOp = X86ISD::ADD;
7375 // A subtract of one will be selected as a DEC. Note that DEC doesn't
7376 // set CF, so we can't do this for USUBO.
7377 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op))
7378 if (C->getAPIntValue() == 1) {
7379 BaseOp = X86ISD::DEC;
7383 BaseOp = X86ISD::SUB;
7387 BaseOp = X86ISD::SUB;
7391 BaseOp = X86ISD::SMUL;
7395 BaseOp = X86ISD::UMUL;
7400 // Also sets EFLAGS.
7401 SDVTList VTs = DAG.getVTList(N->getValueType(0), MVT::i32);
7402 SDValue Sum = DAG.getNode(BaseOp, dl, VTs, LHS, RHS);
7405 DAG.getNode(X86ISD::SETCC, dl, N->getValueType(1),
7406 DAG.getConstant(Cond, MVT::i32), SDValue(Sum.getNode(), 1));
7408 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), SetCC);
7412 SDValue X86TargetLowering::LowerCMP_SWAP(SDValue Op, SelectionDAG &DAG) {
7413 EVT T = Op.getValueType();
7414 DebugLoc dl = Op.getDebugLoc();
7417 switch(T.getSimpleVT().SimpleTy) {
7419 assert(false && "Invalid value type!");
7420 case MVT::i8: Reg = X86::AL; size = 1; break;
7421 case MVT::i16: Reg = X86::AX; size = 2; break;
7422 case MVT::i32: Reg = X86::EAX; size = 4; break;
7424 assert(Subtarget->is64Bit() && "Node not type legal!");
7425 Reg = X86::RAX; size = 8;
7428 SDValue cpIn = DAG.getCopyToReg(Op.getOperand(0), dl, Reg,
7429 Op.getOperand(2), SDValue());
7430 SDValue Ops[] = { cpIn.getValue(0),
7433 DAG.getTargetConstant(size, MVT::i8),
7435 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
7436 SDValue Result = DAG.getNode(X86ISD::LCMPXCHG_DAG, dl, Tys, Ops, 5);
7438 DAG.getCopyFromReg(Result.getValue(0), dl, Reg, T, Result.getValue(1));
7442 SDValue X86TargetLowering::LowerREADCYCLECOUNTER(SDValue Op,
7443 SelectionDAG &DAG) {
7444 assert(Subtarget->is64Bit() && "Result not type legalized?");
7445 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
7446 SDValue TheChain = Op.getOperand(0);
7447 DebugLoc dl = Op.getDebugLoc();
7448 SDValue rd = DAG.getNode(X86ISD::RDTSC_DAG, dl, Tys, &TheChain, 1);
7449 SDValue rax = DAG.getCopyFromReg(rd, dl, X86::RAX, MVT::i64, rd.getValue(1));
7450 SDValue rdx = DAG.getCopyFromReg(rax.getValue(1), dl, X86::RDX, MVT::i64,
7452 SDValue Tmp = DAG.getNode(ISD::SHL, dl, MVT::i64, rdx,
7453 DAG.getConstant(32, MVT::i8));
7455 DAG.getNode(ISD::OR, dl, MVT::i64, rax, Tmp),
7458 return DAG.getMergeValues(Ops, 2, dl);
7461 SDValue X86TargetLowering::LowerLOAD_SUB(SDValue Op, SelectionDAG &DAG) {
7462 SDNode *Node = Op.getNode();
7463 DebugLoc dl = Node->getDebugLoc();
7464 EVT T = Node->getValueType(0);
7465 SDValue negOp = DAG.getNode(ISD::SUB, dl, T,
7466 DAG.getConstant(0, T), Node->getOperand(2));
7467 return DAG.getAtomic(ISD::ATOMIC_LOAD_ADD, dl,
7468 cast<AtomicSDNode>(Node)->getMemoryVT(),
7469 Node->getOperand(0),
7470 Node->getOperand(1), negOp,
7471 cast<AtomicSDNode>(Node)->getSrcValue(),
7472 cast<AtomicSDNode>(Node)->getAlignment());
7475 /// LowerOperation - Provide custom lowering hooks for some operations.
7477 SDValue X86TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) {
7478 switch (Op.getOpcode()) {
7479 default: llvm_unreachable("Should not custom lower this!");
7480 case ISD::ATOMIC_CMP_SWAP: return LowerCMP_SWAP(Op,DAG);
7481 case ISD::ATOMIC_LOAD_SUB: return LowerLOAD_SUB(Op,DAG);
7482 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
7483 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG);
7484 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
7485 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
7486 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG);
7487 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
7488 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
7489 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
7490 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
7491 case ISD::ExternalSymbol: return LowerExternalSymbol(Op, DAG);
7492 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
7493 case ISD::SHL_PARTS:
7494 case ISD::SRA_PARTS:
7495 case ISD::SRL_PARTS: return LowerShift(Op, DAG);
7496 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG);
7497 case ISD::UINT_TO_FP: return LowerUINT_TO_FP(Op, DAG);
7498 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG);
7499 case ISD::FP_TO_UINT: return LowerFP_TO_UINT(Op, DAG);
7500 case ISD::FABS: return LowerFABS(Op, DAG);
7501 case ISD::FNEG: return LowerFNEG(Op, DAG);
7502 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG);
7503 case ISD::SETCC: return LowerSETCC(Op, DAG);
7504 case ISD::VSETCC: return LowerVSETCC(Op, DAG);
7505 case ISD::SELECT: return LowerSELECT(Op, DAG);
7506 case ISD::BRCOND: return LowerBRCOND(Op, DAG);
7507 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
7508 case ISD::VASTART: return LowerVASTART(Op, DAG);
7509 case ISD::VAARG: return LowerVAARG(Op, DAG);
7510 case ISD::VACOPY: return LowerVACOPY(Op, DAG);
7511 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
7512 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
7513 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
7514 case ISD::FRAME_TO_ARGS_OFFSET:
7515 return LowerFRAME_TO_ARGS_OFFSET(Op, DAG);
7516 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
7517 case ISD::EH_RETURN: return LowerEH_RETURN(Op, DAG);
7518 case ISD::TRAMPOLINE: return LowerTRAMPOLINE(Op, DAG);
7519 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
7520 case ISD::CTLZ: return LowerCTLZ(Op, DAG);
7521 case ISD::CTTZ: return LowerCTTZ(Op, DAG);
7522 case ISD::MUL: return LowerMUL_V2I64(Op, DAG);
7528 case ISD::UMULO: return LowerXALUO(Op, DAG);
7529 case ISD::READCYCLECOUNTER: return LowerREADCYCLECOUNTER(Op, DAG);
7533 void X86TargetLowering::
7534 ReplaceATOMIC_BINARY_64(SDNode *Node, SmallVectorImpl<SDValue>&Results,
7535 SelectionDAG &DAG, unsigned NewOp) {
7536 EVT T = Node->getValueType(0);
7537 DebugLoc dl = Node->getDebugLoc();
7538 assert (T == MVT::i64 && "Only know how to expand i64 atomics");
7540 SDValue Chain = Node->getOperand(0);
7541 SDValue In1 = Node->getOperand(1);
7542 SDValue In2L = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
7543 Node->getOperand(2), DAG.getIntPtrConstant(0));
7544 SDValue In2H = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
7545 Node->getOperand(2), DAG.getIntPtrConstant(1));
7546 SDValue Ops[] = { Chain, In1, In2L, In2H };
7547 SDVTList Tys = DAG.getVTList(MVT::i32, MVT::i32, MVT::Other);
7549 DAG.getMemIntrinsicNode(NewOp, dl, Tys, Ops, 4, MVT::i64,
7550 cast<MemSDNode>(Node)->getMemOperand());
7551 SDValue OpsF[] = { Result.getValue(0), Result.getValue(1)};
7552 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, OpsF, 2));
7553 Results.push_back(Result.getValue(2));
7556 /// ReplaceNodeResults - Replace a node with an illegal result type
7557 /// with a new node built out of custom code.
7558 void X86TargetLowering::ReplaceNodeResults(SDNode *N,
7559 SmallVectorImpl<SDValue>&Results,
7560 SelectionDAG &DAG) {
7561 DebugLoc dl = N->getDebugLoc();
7562 switch (N->getOpcode()) {
7564 assert(false && "Do not know how to custom type legalize this operation!");
7566 case ISD::FP_TO_SINT: {
7567 std::pair<SDValue,SDValue> Vals =
7568 FP_TO_INTHelper(SDValue(N, 0), DAG, true);
7569 SDValue FIST = Vals.first, StackSlot = Vals.second;
7570 if (FIST.getNode() != 0) {
7571 EVT VT = N->getValueType(0);
7572 // Return a load from the stack slot.
7573 Results.push_back(DAG.getLoad(VT, dl, FIST, StackSlot, NULL, 0,
7578 case ISD::READCYCLECOUNTER: {
7579 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
7580 SDValue TheChain = N->getOperand(0);
7581 SDValue rd = DAG.getNode(X86ISD::RDTSC_DAG, dl, Tys, &TheChain, 1);
7582 SDValue eax = DAG.getCopyFromReg(rd, dl, X86::EAX, MVT::i32,
7584 SDValue edx = DAG.getCopyFromReg(eax.getValue(1), dl, X86::EDX, MVT::i32,
7586 // Use a buildpair to merge the two 32-bit values into a 64-bit one.
7587 SDValue Ops[] = { eax, edx };
7588 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Ops, 2));
7589 Results.push_back(edx.getValue(1));
7592 case ISD::ATOMIC_CMP_SWAP: {
7593 EVT T = N->getValueType(0);
7594 assert (T == MVT::i64 && "Only know how to expand i64 Cmp and Swap");
7595 SDValue cpInL, cpInH;
7596 cpInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(2),
7597 DAG.getConstant(0, MVT::i32));
7598 cpInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(2),
7599 DAG.getConstant(1, MVT::i32));
7600 cpInL = DAG.getCopyToReg(N->getOperand(0), dl, X86::EAX, cpInL, SDValue());
7601 cpInH = DAG.getCopyToReg(cpInL.getValue(0), dl, X86::EDX, cpInH,
7603 SDValue swapInL, swapInH;
7604 swapInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(3),
7605 DAG.getConstant(0, MVT::i32));
7606 swapInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(3),
7607 DAG.getConstant(1, MVT::i32));
7608 swapInL = DAG.getCopyToReg(cpInH.getValue(0), dl, X86::EBX, swapInL,
7610 swapInH = DAG.getCopyToReg(swapInL.getValue(0), dl, X86::ECX, swapInH,
7611 swapInL.getValue(1));
7612 SDValue Ops[] = { swapInH.getValue(0),
7614 swapInH.getValue(1) };
7615 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
7616 SDValue Result = DAG.getNode(X86ISD::LCMPXCHG8_DAG, dl, Tys, Ops, 3);
7617 SDValue cpOutL = DAG.getCopyFromReg(Result.getValue(0), dl, X86::EAX,
7618 MVT::i32, Result.getValue(1));
7619 SDValue cpOutH = DAG.getCopyFromReg(cpOutL.getValue(1), dl, X86::EDX,
7620 MVT::i32, cpOutL.getValue(2));
7621 SDValue OpsF[] = { cpOutL.getValue(0), cpOutH.getValue(0)};
7622 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, OpsF, 2));
7623 Results.push_back(cpOutH.getValue(1));
7626 case ISD::ATOMIC_LOAD_ADD:
7627 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMADD64_DAG);
7629 case ISD::ATOMIC_LOAD_AND:
7630 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMAND64_DAG);
7632 case ISD::ATOMIC_LOAD_NAND:
7633 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMNAND64_DAG);
7635 case ISD::ATOMIC_LOAD_OR:
7636 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMOR64_DAG);
7638 case ISD::ATOMIC_LOAD_SUB:
7639 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMSUB64_DAG);
7641 case ISD::ATOMIC_LOAD_XOR:
7642 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMXOR64_DAG);
7644 case ISD::ATOMIC_SWAP:
7645 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMSWAP64_DAG);
7650 const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
7652 default: return NULL;
7653 case X86ISD::BSF: return "X86ISD::BSF";
7654 case X86ISD::BSR: return "X86ISD::BSR";
7655 case X86ISD::SHLD: return "X86ISD::SHLD";
7656 case X86ISD::SHRD: return "X86ISD::SHRD";
7657 case X86ISD::FAND: return "X86ISD::FAND";
7658 case X86ISD::FOR: return "X86ISD::FOR";
7659 case X86ISD::FXOR: return "X86ISD::FXOR";
7660 case X86ISD::FSRL: return "X86ISD::FSRL";
7661 case X86ISD::FILD: return "X86ISD::FILD";
7662 case X86ISD::FILD_FLAG: return "X86ISD::FILD_FLAG";
7663 case X86ISD::FP_TO_INT16_IN_MEM: return "X86ISD::FP_TO_INT16_IN_MEM";
7664 case X86ISD::FP_TO_INT32_IN_MEM: return "X86ISD::FP_TO_INT32_IN_MEM";
7665 case X86ISD::FP_TO_INT64_IN_MEM: return "X86ISD::FP_TO_INT64_IN_MEM";
7666 case X86ISD::FLD: return "X86ISD::FLD";
7667 case X86ISD::FST: return "X86ISD::FST";
7668 case X86ISD::CALL: return "X86ISD::CALL";
7669 case X86ISD::RDTSC_DAG: return "X86ISD::RDTSC_DAG";
7670 case X86ISD::BT: return "X86ISD::BT";
7671 case X86ISD::CMP: return "X86ISD::CMP";
7672 case X86ISD::COMI: return "X86ISD::COMI";
7673 case X86ISD::UCOMI: return "X86ISD::UCOMI";
7674 case X86ISD::SETCC: return "X86ISD::SETCC";
7675 case X86ISD::SETCC_CARRY: return "X86ISD::SETCC_CARRY";
7676 case X86ISD::CMOV: return "X86ISD::CMOV";
7677 case X86ISD::BRCOND: return "X86ISD::BRCOND";
7678 case X86ISD::RET_FLAG: return "X86ISD::RET_FLAG";
7679 case X86ISD::REP_STOS: return "X86ISD::REP_STOS";
7680 case X86ISD::REP_MOVS: return "X86ISD::REP_MOVS";
7681 case X86ISD::GlobalBaseReg: return "X86ISD::GlobalBaseReg";
7682 case X86ISD::Wrapper: return "X86ISD::Wrapper";
7683 case X86ISD::WrapperRIP: return "X86ISD::WrapperRIP";
7684 case X86ISD::PEXTRB: return "X86ISD::PEXTRB";
7685 case X86ISD::PEXTRW: return "X86ISD::PEXTRW";
7686 case X86ISD::INSERTPS: return "X86ISD::INSERTPS";
7687 case X86ISD::PINSRB: return "X86ISD::PINSRB";
7688 case X86ISD::PINSRW: return "X86ISD::PINSRW";
7689 case X86ISD::MMX_PINSRW: return "X86ISD::MMX_PINSRW";
7690 case X86ISD::PSHUFB: return "X86ISD::PSHUFB";
7691 case X86ISD::FMAX: return "X86ISD::FMAX";
7692 case X86ISD::FMIN: return "X86ISD::FMIN";
7693 case X86ISD::FRSQRT: return "X86ISD::FRSQRT";
7694 case X86ISD::FRCP: return "X86ISD::FRCP";
7695 case X86ISD::TLSADDR: return "X86ISD::TLSADDR";
7696 case X86ISD::SegmentBaseAddress: return "X86ISD::SegmentBaseAddress";
7697 case X86ISD::EH_RETURN: return "X86ISD::EH_RETURN";
7698 case X86ISD::TC_RETURN: return "X86ISD::TC_RETURN";
7699 case X86ISD::FNSTCW16m: return "X86ISD::FNSTCW16m";
7700 case X86ISD::LCMPXCHG_DAG: return "X86ISD::LCMPXCHG_DAG";
7701 case X86ISD::LCMPXCHG8_DAG: return "X86ISD::LCMPXCHG8_DAG";
7702 case X86ISD::ATOMADD64_DAG: return "X86ISD::ATOMADD64_DAG";
7703 case X86ISD::ATOMSUB64_DAG: return "X86ISD::ATOMSUB64_DAG";
7704 case X86ISD::ATOMOR64_DAG: return "X86ISD::ATOMOR64_DAG";
7705 case X86ISD::ATOMXOR64_DAG: return "X86ISD::ATOMXOR64_DAG";
7706 case X86ISD::ATOMAND64_DAG: return "X86ISD::ATOMAND64_DAG";
7707 case X86ISD::ATOMNAND64_DAG: return "X86ISD::ATOMNAND64_DAG";
7708 case X86ISD::VZEXT_MOVL: return "X86ISD::VZEXT_MOVL";
7709 case X86ISD::VZEXT_LOAD: return "X86ISD::VZEXT_LOAD";
7710 case X86ISD::VSHL: return "X86ISD::VSHL";
7711 case X86ISD::VSRL: return "X86ISD::VSRL";
7712 case X86ISD::CMPPD: return "X86ISD::CMPPD";
7713 case X86ISD::CMPPS: return "X86ISD::CMPPS";
7714 case X86ISD::PCMPEQB: return "X86ISD::PCMPEQB";
7715 case X86ISD::PCMPEQW: return "X86ISD::PCMPEQW";
7716 case X86ISD::PCMPEQD: return "X86ISD::PCMPEQD";
7717 case X86ISD::PCMPEQQ: return "X86ISD::PCMPEQQ";
7718 case X86ISD::PCMPGTB: return "X86ISD::PCMPGTB";
7719 case X86ISD::PCMPGTW: return "X86ISD::PCMPGTW";
7720 case X86ISD::PCMPGTD: return "X86ISD::PCMPGTD";
7721 case X86ISD::PCMPGTQ: return "X86ISD::PCMPGTQ";
7722 case X86ISD::ADD: return "X86ISD::ADD";
7723 case X86ISD::SUB: return "X86ISD::SUB";
7724 case X86ISD::SMUL: return "X86ISD::SMUL";
7725 case X86ISD::UMUL: return "X86ISD::UMUL";
7726 case X86ISD::INC: return "X86ISD::INC";
7727 case X86ISD::DEC: return "X86ISD::DEC";
7728 case X86ISD::OR: return "X86ISD::OR";
7729 case X86ISD::XOR: return "X86ISD::XOR";
7730 case X86ISD::AND: return "X86ISD::AND";
7731 case X86ISD::MUL_IMM: return "X86ISD::MUL_IMM";
7732 case X86ISD::PTEST: return "X86ISD::PTEST";
7733 case X86ISD::VASTART_SAVE_XMM_REGS: return "X86ISD::VASTART_SAVE_XMM_REGS";
7734 case X86ISD::MINGW_ALLOCA: return "X86ISD::MINGW_ALLOCA";
7738 // isLegalAddressingMode - Return true if the addressing mode represented
7739 // by AM is legal for this target, for a load/store of the specified type.
7740 bool X86TargetLowering::isLegalAddressingMode(const AddrMode &AM,
7741 const Type *Ty) const {
7742 // X86 supports extremely general addressing modes.
7743 CodeModel::Model M = getTargetMachine().getCodeModel();
7745 // X86 allows a sign-extended 32-bit immediate field as a displacement.
7746 if (!X86::isOffsetSuitableForCodeModel(AM.BaseOffs, M, AM.BaseGV != NULL))
7751 Subtarget->ClassifyGlobalReference(AM.BaseGV, getTargetMachine());
7753 // If a reference to this global requires an extra load, we can't fold it.
7754 if (isGlobalStubReference(GVFlags))
7757 // If BaseGV requires a register for the PIC base, we cannot also have a
7758 // BaseReg specified.
7759 if (AM.HasBaseReg && isGlobalRelativeToPICBase(GVFlags))
7762 // If lower 4G is not available, then we must use rip-relative addressing.
7763 if (Subtarget->is64Bit() && (AM.BaseOffs || AM.Scale > 1))
7773 // These scales always work.
7778 // These scales are formed with basereg+scalereg. Only accept if there is
7783 default: // Other stuff never works.
7791 bool X86TargetLowering::isTruncateFree(const Type *Ty1, const Type *Ty2) const {
7792 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
7794 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits();
7795 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits();
7796 if (NumBits1 <= NumBits2)
7801 bool X86TargetLowering::isTruncateFree(EVT VT1, EVT VT2) const {
7802 if (!VT1.isInteger() || !VT2.isInteger())
7804 unsigned NumBits1 = VT1.getSizeInBits();
7805 unsigned NumBits2 = VT2.getSizeInBits();
7806 if (NumBits1 <= NumBits2)
7811 bool X86TargetLowering::isZExtFree(const Type *Ty1, const Type *Ty2) const {
7812 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
7813 return Ty1->isIntegerTy(32) && Ty2->isIntegerTy(64) && Subtarget->is64Bit();
7816 bool X86TargetLowering::isZExtFree(EVT VT1, EVT VT2) const {
7817 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
7818 return VT1 == MVT::i32 && VT2 == MVT::i64 && Subtarget->is64Bit();
7821 bool X86TargetLowering::isNarrowingProfitable(EVT VT1, EVT VT2) const {
7822 // i16 instructions are longer (0x66 prefix) and potentially slower.
7823 return !(VT1 == MVT::i32 && VT2 == MVT::i16);
7826 /// isShuffleMaskLegal - Targets can use this to indicate that they only
7827 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
7828 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
7829 /// are assumed to be legal.
7831 X86TargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M,
7833 // Only do shuffles on 128-bit vector types for now.
7834 if (VT.getSizeInBits() == 64)
7837 // FIXME: pshufb, blends, shifts.
7838 return (VT.getVectorNumElements() == 2 ||
7839 ShuffleVectorSDNode::isSplatMask(&M[0], VT) ||
7840 isMOVLMask(M, VT) ||
7841 isSHUFPMask(M, VT) ||
7842 isPSHUFDMask(M, VT) ||
7843 isPSHUFHWMask(M, VT) ||
7844 isPSHUFLWMask(M, VT) ||
7845 isPALIGNRMask(M, VT, Subtarget->hasSSSE3()) ||
7846 isUNPCKLMask(M, VT) ||
7847 isUNPCKHMask(M, VT) ||
7848 isUNPCKL_v_undef_Mask(M, VT) ||
7849 isUNPCKH_v_undef_Mask(M, VT));
7853 X86TargetLowering::isVectorClearMaskLegal(const SmallVectorImpl<int> &Mask,
7855 unsigned NumElts = VT.getVectorNumElements();
7856 // FIXME: This collection of masks seems suspect.
7859 if (NumElts == 4 && VT.getSizeInBits() == 128) {
7860 return (isMOVLMask(Mask, VT) ||
7861 isCommutedMOVLMask(Mask, VT, true) ||
7862 isSHUFPMask(Mask, VT) ||
7863 isCommutedSHUFPMask(Mask, VT));
7868 //===----------------------------------------------------------------------===//
7869 // X86 Scheduler Hooks
7870 //===----------------------------------------------------------------------===//
7872 // private utility function
7874 X86TargetLowering::EmitAtomicBitwiseWithCustomInserter(MachineInstr *bInstr,
7875 MachineBasicBlock *MBB,
7883 TargetRegisterClass *RC,
7884 bool invSrc) const {
7885 // For the atomic bitwise operator, we generate
7888 // ld t1 = [bitinstr.addr]
7889 // op t2 = t1, [bitinstr.val]
7891 // lcs dest = [bitinstr.addr], t2 [EAX is implicit]
7893 // fallthrough -->nextMBB
7894 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
7895 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
7896 MachineFunction::iterator MBBIter = MBB;
7899 /// First build the CFG
7900 MachineFunction *F = MBB->getParent();
7901 MachineBasicBlock *thisMBB = MBB;
7902 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB);
7903 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB);
7904 F->insert(MBBIter, newMBB);
7905 F->insert(MBBIter, nextMBB);
7907 // Move all successors to thisMBB to nextMBB
7908 nextMBB->transferSuccessors(thisMBB);
7910 // Update thisMBB to fall through to newMBB
7911 thisMBB->addSuccessor(newMBB);
7913 // newMBB jumps to itself and fall through to nextMBB
7914 newMBB->addSuccessor(nextMBB);
7915 newMBB->addSuccessor(newMBB);
7917 // Insert instructions into newMBB based on incoming instruction
7918 assert(bInstr->getNumOperands() < X86AddrNumOperands + 4 &&
7919 "unexpected number of operands");
7920 DebugLoc dl = bInstr->getDebugLoc();
7921 MachineOperand& destOper = bInstr->getOperand(0);
7922 MachineOperand* argOpers[2 + X86AddrNumOperands];
7923 int numArgs = bInstr->getNumOperands() - 1;
7924 for (int i=0; i < numArgs; ++i)
7925 argOpers[i] = &bInstr->getOperand(i+1);
7927 // x86 address has 4 operands: base, index, scale, and displacement
7928 int lastAddrIndx = X86AddrNumOperands - 1; // [0,3]
7929 int valArgIndx = lastAddrIndx + 1;
7931 unsigned t1 = F->getRegInfo().createVirtualRegister(RC);
7932 MachineInstrBuilder MIB = BuildMI(newMBB, dl, TII->get(LoadOpc), t1);
7933 for (int i=0; i <= lastAddrIndx; ++i)
7934 (*MIB).addOperand(*argOpers[i]);
7936 unsigned tt = F->getRegInfo().createVirtualRegister(RC);
7938 MIB = BuildMI(newMBB, dl, TII->get(notOpc), tt).addReg(t1);
7943 unsigned t2 = F->getRegInfo().createVirtualRegister(RC);
7944 assert((argOpers[valArgIndx]->isReg() ||
7945 argOpers[valArgIndx]->isImm()) &&
7947 if (argOpers[valArgIndx]->isReg())
7948 MIB = BuildMI(newMBB, dl, TII->get(regOpc), t2);
7950 MIB = BuildMI(newMBB, dl, TII->get(immOpc), t2);
7952 (*MIB).addOperand(*argOpers[valArgIndx]);
7954 MIB = BuildMI(newMBB, dl, TII->get(copyOpc), EAXreg);
7957 MIB = BuildMI(newMBB, dl, TII->get(CXchgOpc));
7958 for (int i=0; i <= lastAddrIndx; ++i)
7959 (*MIB).addOperand(*argOpers[i]);
7961 assert(bInstr->hasOneMemOperand() && "Unexpected number of memoperand");
7962 (*MIB).setMemRefs(bInstr->memoperands_begin(),
7963 bInstr->memoperands_end());
7965 MIB = BuildMI(newMBB, dl, TII->get(copyOpc), destOper.getReg());
7969 BuildMI(newMBB, dl, TII->get(X86::JNE_4)).addMBB(newMBB);
7971 F->DeleteMachineInstr(bInstr); // The pseudo instruction is gone now.
7975 // private utility function: 64 bit atomics on 32 bit host.
7977 X86TargetLowering::EmitAtomicBit6432WithCustomInserter(MachineInstr *bInstr,
7978 MachineBasicBlock *MBB,
7983 bool invSrc) const {
7984 // For the atomic bitwise operator, we generate
7985 // thisMBB (instructions are in pairs, except cmpxchg8b)
7986 // ld t1,t2 = [bitinstr.addr]
7988 // out1, out2 = phi (thisMBB, t1/t2) (newMBB, t3/t4)
7989 // op t5, t6 <- out1, out2, [bitinstr.val]
7990 // (for SWAP, substitute: mov t5, t6 <- [bitinstr.val])
7991 // mov ECX, EBX <- t5, t6
7992 // mov EAX, EDX <- t1, t2
7993 // cmpxchg8b [bitinstr.addr] [EAX, EDX, EBX, ECX implicit]
7994 // mov t3, t4 <- EAX, EDX
7996 // result in out1, out2
7997 // fallthrough -->nextMBB
7999 const TargetRegisterClass *RC = X86::GR32RegisterClass;
8000 const unsigned LoadOpc = X86::MOV32rm;
8001 const unsigned copyOpc = X86::MOV32rr;
8002 const unsigned NotOpc = X86::NOT32r;
8003 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
8004 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
8005 MachineFunction::iterator MBBIter = MBB;
8008 /// First build the CFG
8009 MachineFunction *F = MBB->getParent();
8010 MachineBasicBlock *thisMBB = MBB;
8011 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB);
8012 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB);
8013 F->insert(MBBIter, newMBB);
8014 F->insert(MBBIter, nextMBB);
8016 // Move all successors to thisMBB to nextMBB
8017 nextMBB->transferSuccessors(thisMBB);
8019 // Update thisMBB to fall through to newMBB
8020 thisMBB->addSuccessor(newMBB);
8022 // newMBB jumps to itself and fall through to nextMBB
8023 newMBB->addSuccessor(nextMBB);
8024 newMBB->addSuccessor(newMBB);
8026 DebugLoc dl = bInstr->getDebugLoc();
8027 // Insert instructions into newMBB based on incoming instruction
8028 // There are 8 "real" operands plus 9 implicit def/uses, ignored here.
8029 assert(bInstr->getNumOperands() < X86AddrNumOperands + 14 &&
8030 "unexpected number of operands");
8031 MachineOperand& dest1Oper = bInstr->getOperand(0);
8032 MachineOperand& dest2Oper = bInstr->getOperand(1);
8033 MachineOperand* argOpers[2 + X86AddrNumOperands];
8034 for (int i=0; i < 2 + X86AddrNumOperands; ++i)
8035 argOpers[i] = &bInstr->getOperand(i+2);
8037 // x86 address has 5 operands: base, index, scale, displacement, and segment.
8038 int lastAddrIndx = X86AddrNumOperands - 1; // [0,3]
8040 unsigned t1 = F->getRegInfo().createVirtualRegister(RC);
8041 MachineInstrBuilder MIB = BuildMI(thisMBB, dl, TII->get(LoadOpc), t1);
8042 for (int i=0; i <= lastAddrIndx; ++i)
8043 (*MIB).addOperand(*argOpers[i]);
8044 unsigned t2 = F->getRegInfo().createVirtualRegister(RC);
8045 MIB = BuildMI(thisMBB, dl, TII->get(LoadOpc), t2);
8046 // add 4 to displacement.
8047 for (int i=0; i <= lastAddrIndx-2; ++i)
8048 (*MIB).addOperand(*argOpers[i]);
8049 MachineOperand newOp3 = *(argOpers[3]);
8051 newOp3.setImm(newOp3.getImm()+4);
8053 newOp3.setOffset(newOp3.getOffset()+4);
8054 (*MIB).addOperand(newOp3);
8055 (*MIB).addOperand(*argOpers[lastAddrIndx]);
8057 // t3/4 are defined later, at the bottom of the loop
8058 unsigned t3 = F->getRegInfo().createVirtualRegister(RC);
8059 unsigned t4 = F->getRegInfo().createVirtualRegister(RC);
8060 BuildMI(newMBB, dl, TII->get(X86::PHI), dest1Oper.getReg())
8061 .addReg(t1).addMBB(thisMBB).addReg(t3).addMBB(newMBB);
8062 BuildMI(newMBB, dl, TII->get(X86::PHI), dest2Oper.getReg())
8063 .addReg(t2).addMBB(thisMBB).addReg(t4).addMBB(newMBB);
8065 // The subsequent operations should be using the destination registers of
8066 //the PHI instructions.
8068 t1 = F->getRegInfo().createVirtualRegister(RC);
8069 t2 = F->getRegInfo().createVirtualRegister(RC);
8070 MIB = BuildMI(newMBB, dl, TII->get(NotOpc), t1).addReg(dest1Oper.getReg());
8071 MIB = BuildMI(newMBB, dl, TII->get(NotOpc), t2).addReg(dest2Oper.getReg());
8073 t1 = dest1Oper.getReg();
8074 t2 = dest2Oper.getReg();
8077 int valArgIndx = lastAddrIndx + 1;
8078 assert((argOpers[valArgIndx]->isReg() ||
8079 argOpers[valArgIndx]->isImm()) &&
8081 unsigned t5 = F->getRegInfo().createVirtualRegister(RC);
8082 unsigned t6 = F->getRegInfo().createVirtualRegister(RC);
8083 if (argOpers[valArgIndx]->isReg())
8084 MIB = BuildMI(newMBB, dl, TII->get(regOpcL), t5);
8086 MIB = BuildMI(newMBB, dl, TII->get(immOpcL), t5);
8087 if (regOpcL != X86::MOV32rr)
8089 (*MIB).addOperand(*argOpers[valArgIndx]);
8090 assert(argOpers[valArgIndx + 1]->isReg() ==
8091 argOpers[valArgIndx]->isReg());
8092 assert(argOpers[valArgIndx + 1]->isImm() ==
8093 argOpers[valArgIndx]->isImm());
8094 if (argOpers[valArgIndx + 1]->isReg())
8095 MIB = BuildMI(newMBB, dl, TII->get(regOpcH), t6);
8097 MIB = BuildMI(newMBB, dl, TII->get(immOpcH), t6);
8098 if (regOpcH != X86::MOV32rr)
8100 (*MIB).addOperand(*argOpers[valArgIndx + 1]);
8102 MIB = BuildMI(newMBB, dl, TII->get(copyOpc), X86::EAX);
8104 MIB = BuildMI(newMBB, dl, TII->get(copyOpc), X86::EDX);
8107 MIB = BuildMI(newMBB, dl, TII->get(copyOpc), X86::EBX);
8109 MIB = BuildMI(newMBB, dl, TII->get(copyOpc), X86::ECX);
8112 MIB = BuildMI(newMBB, dl, TII->get(X86::LCMPXCHG8B));
8113 for (int i=0; i <= lastAddrIndx; ++i)
8114 (*MIB).addOperand(*argOpers[i]);
8116 assert(bInstr->hasOneMemOperand() && "Unexpected number of memoperand");
8117 (*MIB).setMemRefs(bInstr->memoperands_begin(),
8118 bInstr->memoperands_end());
8120 MIB = BuildMI(newMBB, dl, TII->get(copyOpc), t3);
8121 MIB.addReg(X86::EAX);
8122 MIB = BuildMI(newMBB, dl, TII->get(copyOpc), t4);
8123 MIB.addReg(X86::EDX);
8126 BuildMI(newMBB, dl, TII->get(X86::JNE_4)).addMBB(newMBB);
8128 F->DeleteMachineInstr(bInstr); // The pseudo instruction is gone now.
8132 // private utility function
8134 X86TargetLowering::EmitAtomicMinMaxWithCustomInserter(MachineInstr *mInstr,
8135 MachineBasicBlock *MBB,
8136 unsigned cmovOpc) const {
8137 // For the atomic min/max operator, we generate
8140 // ld t1 = [min/max.addr]
8141 // mov t2 = [min/max.val]
8143 // cmov[cond] t2 = t1
8145 // lcs dest = [bitinstr.addr], t2 [EAX is implicit]
8147 // fallthrough -->nextMBB
8149 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
8150 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
8151 MachineFunction::iterator MBBIter = MBB;
8154 /// First build the CFG
8155 MachineFunction *F = MBB->getParent();
8156 MachineBasicBlock *thisMBB = MBB;
8157 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB);
8158 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB);
8159 F->insert(MBBIter, newMBB);
8160 F->insert(MBBIter, nextMBB);
8162 // Move all successors of thisMBB to nextMBB
8163 nextMBB->transferSuccessors(thisMBB);
8165 // Update thisMBB to fall through to newMBB
8166 thisMBB->addSuccessor(newMBB);
8168 // newMBB jumps to newMBB and fall through to nextMBB
8169 newMBB->addSuccessor(nextMBB);
8170 newMBB->addSuccessor(newMBB);
8172 DebugLoc dl = mInstr->getDebugLoc();
8173 // Insert instructions into newMBB based on incoming instruction
8174 assert(mInstr->getNumOperands() < X86AddrNumOperands + 4 &&
8175 "unexpected number of operands");
8176 MachineOperand& destOper = mInstr->getOperand(0);
8177 MachineOperand* argOpers[2 + X86AddrNumOperands];
8178 int numArgs = mInstr->getNumOperands() - 1;
8179 for (int i=0; i < numArgs; ++i)
8180 argOpers[i] = &mInstr->getOperand(i+1);
8182 // x86 address has 4 operands: base, index, scale, and displacement
8183 int lastAddrIndx = X86AddrNumOperands - 1; // [0,3]
8184 int valArgIndx = lastAddrIndx + 1;
8186 unsigned t1 = F->getRegInfo().createVirtualRegister(X86::GR32RegisterClass);
8187 MachineInstrBuilder MIB = BuildMI(newMBB, dl, TII->get(X86::MOV32rm), t1);
8188 for (int i=0; i <= lastAddrIndx; ++i)
8189 (*MIB).addOperand(*argOpers[i]);
8191 // We only support register and immediate values
8192 assert((argOpers[valArgIndx]->isReg() ||
8193 argOpers[valArgIndx]->isImm()) &&
8196 unsigned t2 = F->getRegInfo().createVirtualRegister(X86::GR32RegisterClass);
8197 if (argOpers[valArgIndx]->isReg())
8198 MIB = BuildMI(newMBB, dl, TII->get(X86::MOV32rr), t2);
8200 MIB = BuildMI(newMBB, dl, TII->get(X86::MOV32rr), t2);
8201 (*MIB).addOperand(*argOpers[valArgIndx]);
8203 MIB = BuildMI(newMBB, dl, TII->get(X86::MOV32rr), X86::EAX);
8206 MIB = BuildMI(newMBB, dl, TII->get(X86::CMP32rr));
8211 unsigned t3 = F->getRegInfo().createVirtualRegister(X86::GR32RegisterClass);
8212 MIB = BuildMI(newMBB, dl, TII->get(cmovOpc),t3);
8216 // Cmp and exchange if none has modified the memory location
8217 MIB = BuildMI(newMBB, dl, TII->get(X86::LCMPXCHG32));
8218 for (int i=0; i <= lastAddrIndx; ++i)
8219 (*MIB).addOperand(*argOpers[i]);
8221 assert(mInstr->hasOneMemOperand() && "Unexpected number of memoperand");
8222 (*MIB).setMemRefs(mInstr->memoperands_begin(),
8223 mInstr->memoperands_end());
8225 MIB = BuildMI(newMBB, dl, TII->get(X86::MOV32rr), destOper.getReg());
8226 MIB.addReg(X86::EAX);
8229 BuildMI(newMBB, dl, TII->get(X86::JNE_4)).addMBB(newMBB);
8231 F->DeleteMachineInstr(mInstr); // The pseudo instruction is gone now.
8235 // FIXME: When we get size specific XMM0 registers, i.e. XMM0_V16I8
8236 // all of this code can be replaced with that in the .td file.
8238 X86TargetLowering::EmitPCMP(MachineInstr *MI, MachineBasicBlock *BB,
8239 unsigned numArgs, bool memArg) const {
8241 MachineFunction *F = BB->getParent();
8242 DebugLoc dl = MI->getDebugLoc();
8243 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
8247 Opc = numArgs == 3 ? X86::PCMPISTRM128rm : X86::PCMPESTRM128rm;
8249 Opc = numArgs == 3 ? X86::PCMPISTRM128rr : X86::PCMPESTRM128rr;
8251 MachineInstrBuilder MIB = BuildMI(BB, dl, TII->get(Opc));
8253 for (unsigned i = 0; i < numArgs; ++i) {
8254 MachineOperand &Op = MI->getOperand(i+1);
8256 if (!(Op.isReg() && Op.isImplicit()))
8260 BuildMI(BB, dl, TII->get(X86::MOVAPSrr), MI->getOperand(0).getReg())
8263 F->DeleteMachineInstr(MI);
8269 X86TargetLowering::EmitVAStartSaveXMMRegsWithCustomInserter(
8271 MachineBasicBlock *MBB) const {
8272 // Emit code to save XMM registers to the stack. The ABI says that the
8273 // number of registers to save is given in %al, so it's theoretically
8274 // possible to do an indirect jump trick to avoid saving all of them,
8275 // however this code takes a simpler approach and just executes all
8276 // of the stores if %al is non-zero. It's less code, and it's probably
8277 // easier on the hardware branch predictor, and stores aren't all that
8278 // expensive anyway.
8280 // Create the new basic blocks. One block contains all the XMM stores,
8281 // and one block is the final destination regardless of whether any
8282 // stores were performed.
8283 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
8284 MachineFunction *F = MBB->getParent();
8285 MachineFunction::iterator MBBIter = MBB;
8287 MachineBasicBlock *XMMSaveMBB = F->CreateMachineBasicBlock(LLVM_BB);
8288 MachineBasicBlock *EndMBB = F->CreateMachineBasicBlock(LLVM_BB);
8289 F->insert(MBBIter, XMMSaveMBB);
8290 F->insert(MBBIter, EndMBB);
8293 // Move any original successors of MBB to the end block.
8294 EndMBB->transferSuccessors(MBB);
8295 // The original block will now fall through to the XMM save block.
8296 MBB->addSuccessor(XMMSaveMBB);
8297 // The XMMSaveMBB will fall through to the end block.
8298 XMMSaveMBB->addSuccessor(EndMBB);
8300 // Now add the instructions.
8301 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
8302 DebugLoc DL = MI->getDebugLoc();
8304 unsigned CountReg = MI->getOperand(0).getReg();
8305 int64_t RegSaveFrameIndex = MI->getOperand(1).getImm();
8306 int64_t VarArgsFPOffset = MI->getOperand(2).getImm();
8308 if (!Subtarget->isTargetWin64()) {
8309 // If %al is 0, branch around the XMM save block.
8310 BuildMI(MBB, DL, TII->get(X86::TEST8rr)).addReg(CountReg).addReg(CountReg);
8311 BuildMI(MBB, DL, TII->get(X86::JE_4)).addMBB(EndMBB);
8312 MBB->addSuccessor(EndMBB);
8315 // In the XMM save block, save all the XMM argument registers.
8316 for (int i = 3, e = MI->getNumOperands(); i != e; ++i) {
8317 int64_t Offset = (i - 3) * 16 + VarArgsFPOffset;
8318 MachineMemOperand *MMO =
8319 F->getMachineMemOperand(
8320 PseudoSourceValue::getFixedStack(RegSaveFrameIndex),
8321 MachineMemOperand::MOStore, Offset,
8322 /*Size=*/16, /*Align=*/16);
8323 BuildMI(XMMSaveMBB, DL, TII->get(X86::MOVAPSmr))
8324 .addFrameIndex(RegSaveFrameIndex)
8325 .addImm(/*Scale=*/1)
8326 .addReg(/*IndexReg=*/0)
8327 .addImm(/*Disp=*/Offset)
8328 .addReg(/*Segment=*/0)
8329 .addReg(MI->getOperand(i).getReg())
8330 .addMemOperand(MMO);
8333 F->DeleteMachineInstr(MI); // The pseudo instruction is gone now.
8339 X86TargetLowering::EmitLoweredSelect(MachineInstr *MI,
8340 MachineBasicBlock *BB,
8341 DenseMap<MachineBasicBlock*, MachineBasicBlock*> *EM) const {
8342 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
8343 DebugLoc DL = MI->getDebugLoc();
8345 // To "insert" a SELECT_CC instruction, we actually have to insert the
8346 // diamond control-flow pattern. The incoming instruction knows the
8347 // destination vreg to set, the condition code register to branch on, the
8348 // true/false values to select between, and a branch opcode to use.
8349 const BasicBlock *LLVM_BB = BB->getBasicBlock();
8350 MachineFunction::iterator It = BB;
8356 // cmpTY ccX, r1, r2
8358 // fallthrough --> copy0MBB
8359 MachineBasicBlock *thisMBB = BB;
8360 MachineFunction *F = BB->getParent();
8361 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
8362 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
8364 X86::GetCondBranchFromCond((X86::CondCode)MI->getOperand(3).getImm());
8365 BuildMI(BB, DL, TII->get(Opc)).addMBB(sinkMBB);
8366 F->insert(It, copy0MBB);
8367 F->insert(It, sinkMBB);
8368 // Update machine-CFG edges by first adding all successors of the current
8369 // block to the new block which will contain the Phi node for the select.
8370 // Also inform sdisel of the edge changes.
8371 for (MachineBasicBlock::succ_iterator I = BB->succ_begin(),
8372 E = BB->succ_end(); I != E; ++I) {
8373 EM->insert(std::make_pair(*I, sinkMBB));
8374 sinkMBB->addSuccessor(*I);
8376 // Next, remove all successors of the current block, and add the true
8377 // and fallthrough blocks as its successors.
8378 while (!BB->succ_empty())
8379 BB->removeSuccessor(BB->succ_begin());
8380 // Add the true and fallthrough blocks as its successors.
8381 BB->addSuccessor(copy0MBB);
8382 BB->addSuccessor(sinkMBB);
8385 // %FalseValue = ...
8386 // # fallthrough to sinkMBB
8389 // Update machine-CFG edges
8390 BB->addSuccessor(sinkMBB);
8393 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
8396 BuildMI(BB, DL, TII->get(X86::PHI), MI->getOperand(0).getReg())
8397 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB)
8398 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
8400 F->DeleteMachineInstr(MI); // The pseudo instruction is gone now.
8405 X86TargetLowering::EmitLoweredMingwAlloca(MachineInstr *MI,
8406 MachineBasicBlock *BB,
8407 DenseMap<MachineBasicBlock*, MachineBasicBlock*> *EM) const {
8408 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
8409 DebugLoc DL = MI->getDebugLoc();
8410 MachineFunction *F = BB->getParent();
8412 // The lowering is pretty easy: we're just emitting the call to _alloca. The
8413 // non-trivial part is impdef of ESP.
8414 // FIXME: The code should be tweaked as soon as we'll try to do codegen for
8417 BuildMI(BB, DL, TII->get(X86::CALLpcrel32))
8418 .addExternalSymbol("_alloca")
8419 .addReg(X86::EAX, RegState::Implicit)
8420 .addReg(X86::ESP, RegState::Implicit)
8421 .addReg(X86::EAX, RegState::Define | RegState::Implicit)
8422 .addReg(X86::ESP, RegState::Define | RegState::Implicit);
8424 F->DeleteMachineInstr(MI); // The pseudo instruction is gone now.
8429 X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
8430 MachineBasicBlock *BB,
8431 DenseMap<MachineBasicBlock*, MachineBasicBlock*> *EM) const {
8432 switch (MI->getOpcode()) {
8433 default: assert(false && "Unexpected instr type to insert");
8434 case X86::MINGW_ALLOCA:
8435 return EmitLoweredMingwAlloca(MI, BB, EM);
8437 case X86::CMOV_V1I64:
8438 case X86::CMOV_FR32:
8439 case X86::CMOV_FR64:
8440 case X86::CMOV_V4F32:
8441 case X86::CMOV_V2F64:
8442 case X86::CMOV_V2I64:
8443 case X86::CMOV_GR16:
8444 case X86::CMOV_GR32:
8445 case X86::CMOV_RFP32:
8446 case X86::CMOV_RFP64:
8447 case X86::CMOV_RFP80:
8448 return EmitLoweredSelect(MI, BB, EM);
8450 case X86::FP32_TO_INT16_IN_MEM:
8451 case X86::FP32_TO_INT32_IN_MEM:
8452 case X86::FP32_TO_INT64_IN_MEM:
8453 case X86::FP64_TO_INT16_IN_MEM:
8454 case X86::FP64_TO_INT32_IN_MEM:
8455 case X86::FP64_TO_INT64_IN_MEM:
8456 case X86::FP80_TO_INT16_IN_MEM:
8457 case X86::FP80_TO_INT32_IN_MEM:
8458 case X86::FP80_TO_INT64_IN_MEM: {
8459 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
8460 DebugLoc DL = MI->getDebugLoc();
8462 // Change the floating point control register to use "round towards zero"
8463 // mode when truncating to an integer value.
8464 MachineFunction *F = BB->getParent();
8465 int CWFrameIdx = F->getFrameInfo()->CreateStackObject(2, 2, false);
8466 addFrameReference(BuildMI(BB, DL, TII->get(X86::FNSTCW16m)), CWFrameIdx);
8468 // Load the old value of the high byte of the control word...
8470 F->getRegInfo().createVirtualRegister(X86::GR16RegisterClass);
8471 addFrameReference(BuildMI(BB, DL, TII->get(X86::MOV16rm), OldCW),
8474 // Set the high part to be round to zero...
8475 addFrameReference(BuildMI(BB, DL, TII->get(X86::MOV16mi)), CWFrameIdx)
8478 // Reload the modified control word now...
8479 addFrameReference(BuildMI(BB, DL, TII->get(X86::FLDCW16m)), CWFrameIdx);
8481 // Restore the memory image of control word to original value
8482 addFrameReference(BuildMI(BB, DL, TII->get(X86::MOV16mr)), CWFrameIdx)
8485 // Get the X86 opcode to use.
8487 switch (MI->getOpcode()) {
8488 default: llvm_unreachable("illegal opcode!");
8489 case X86::FP32_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m32; break;
8490 case X86::FP32_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m32; break;
8491 case X86::FP32_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m32; break;
8492 case X86::FP64_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m64; break;
8493 case X86::FP64_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m64; break;
8494 case X86::FP64_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m64; break;
8495 case X86::FP80_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m80; break;
8496 case X86::FP80_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m80; break;
8497 case X86::FP80_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m80; break;
8501 MachineOperand &Op = MI->getOperand(0);
8503 AM.BaseType = X86AddressMode::RegBase;
8504 AM.Base.Reg = Op.getReg();
8506 AM.BaseType = X86AddressMode::FrameIndexBase;
8507 AM.Base.FrameIndex = Op.getIndex();
8509 Op = MI->getOperand(1);
8511 AM.Scale = Op.getImm();
8512 Op = MI->getOperand(2);
8514 AM.IndexReg = Op.getImm();
8515 Op = MI->getOperand(3);
8516 if (Op.isGlobal()) {
8517 AM.GV = Op.getGlobal();
8519 AM.Disp = Op.getImm();
8521 addFullAddress(BuildMI(BB, DL, TII->get(Opc)), AM)
8522 .addReg(MI->getOperand(X86AddrNumOperands).getReg());
8524 // Reload the original control word now.
8525 addFrameReference(BuildMI(BB, DL, TII->get(X86::FLDCW16m)), CWFrameIdx);
8527 F->DeleteMachineInstr(MI); // The pseudo instruction is gone now.
8530 // DBG_VALUE. Only the frame index case is done here.
8531 case X86::DBG_VALUE: {
8532 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
8533 DebugLoc DL = MI->getDebugLoc();
8535 MachineFunction *F = BB->getParent();
8536 AM.BaseType = X86AddressMode::FrameIndexBase;
8537 AM.Base.FrameIndex = MI->getOperand(0).getImm();
8538 addFullAddress(BuildMI(BB, DL, TII->get(X86::DBG_VALUE)), AM).
8539 addImm(MI->getOperand(1).getImm()).
8540 addMetadata(MI->getOperand(2).getMetadata());
8541 F->DeleteMachineInstr(MI); // Remove pseudo.
8545 // String/text processing lowering.
8546 case X86::PCMPISTRM128REG:
8547 return EmitPCMP(MI, BB, 3, false /* in-mem */);
8548 case X86::PCMPISTRM128MEM:
8549 return EmitPCMP(MI, BB, 3, true /* in-mem */);
8550 case X86::PCMPESTRM128REG:
8551 return EmitPCMP(MI, BB, 5, false /* in mem */);
8552 case X86::PCMPESTRM128MEM:
8553 return EmitPCMP(MI, BB, 5, true /* in mem */);
8556 case X86::ATOMAND32:
8557 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND32rr,
8558 X86::AND32ri, X86::MOV32rm,
8559 X86::LCMPXCHG32, X86::MOV32rr,
8560 X86::NOT32r, X86::EAX,
8561 X86::GR32RegisterClass);
8563 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR32rr,
8564 X86::OR32ri, X86::MOV32rm,
8565 X86::LCMPXCHG32, X86::MOV32rr,
8566 X86::NOT32r, X86::EAX,
8567 X86::GR32RegisterClass);
8568 case X86::ATOMXOR32:
8569 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR32rr,
8570 X86::XOR32ri, X86::MOV32rm,
8571 X86::LCMPXCHG32, X86::MOV32rr,
8572 X86::NOT32r, X86::EAX,
8573 X86::GR32RegisterClass);
8574 case X86::ATOMNAND32:
8575 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND32rr,
8576 X86::AND32ri, X86::MOV32rm,
8577 X86::LCMPXCHG32, X86::MOV32rr,
8578 X86::NOT32r, X86::EAX,
8579 X86::GR32RegisterClass, true);
8580 case X86::ATOMMIN32:
8581 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL32rr);
8582 case X86::ATOMMAX32:
8583 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG32rr);
8584 case X86::ATOMUMIN32:
8585 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB32rr);
8586 case X86::ATOMUMAX32:
8587 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA32rr);
8589 case X86::ATOMAND16:
8590 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND16rr,
8591 X86::AND16ri, X86::MOV16rm,
8592 X86::LCMPXCHG16, X86::MOV16rr,
8593 X86::NOT16r, X86::AX,
8594 X86::GR16RegisterClass);
8596 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR16rr,
8597 X86::OR16ri, X86::MOV16rm,
8598 X86::LCMPXCHG16, X86::MOV16rr,
8599 X86::NOT16r, X86::AX,
8600 X86::GR16RegisterClass);
8601 case X86::ATOMXOR16:
8602 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR16rr,
8603 X86::XOR16ri, X86::MOV16rm,
8604 X86::LCMPXCHG16, X86::MOV16rr,
8605 X86::NOT16r, X86::AX,
8606 X86::GR16RegisterClass);
8607 case X86::ATOMNAND16:
8608 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND16rr,
8609 X86::AND16ri, X86::MOV16rm,
8610 X86::LCMPXCHG16, X86::MOV16rr,
8611 X86::NOT16r, X86::AX,
8612 X86::GR16RegisterClass, true);
8613 case X86::ATOMMIN16:
8614 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL16rr);
8615 case X86::ATOMMAX16:
8616 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG16rr);
8617 case X86::ATOMUMIN16:
8618 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB16rr);
8619 case X86::ATOMUMAX16:
8620 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA16rr);
8623 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND8rr,
8624 X86::AND8ri, X86::MOV8rm,
8625 X86::LCMPXCHG8, X86::MOV8rr,
8626 X86::NOT8r, X86::AL,
8627 X86::GR8RegisterClass);
8629 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR8rr,
8630 X86::OR8ri, X86::MOV8rm,
8631 X86::LCMPXCHG8, X86::MOV8rr,
8632 X86::NOT8r, X86::AL,
8633 X86::GR8RegisterClass);
8635 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR8rr,
8636 X86::XOR8ri, X86::MOV8rm,
8637 X86::LCMPXCHG8, X86::MOV8rr,
8638 X86::NOT8r, X86::AL,
8639 X86::GR8RegisterClass);
8640 case X86::ATOMNAND8:
8641 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND8rr,
8642 X86::AND8ri, X86::MOV8rm,
8643 X86::LCMPXCHG8, X86::MOV8rr,
8644 X86::NOT8r, X86::AL,
8645 X86::GR8RegisterClass, true);
8646 // FIXME: There are no CMOV8 instructions; MIN/MAX need some other way.
8647 // This group is for 64-bit host.
8648 case X86::ATOMAND64:
8649 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND64rr,
8650 X86::AND64ri32, X86::MOV64rm,
8651 X86::LCMPXCHG64, X86::MOV64rr,
8652 X86::NOT64r, X86::RAX,
8653 X86::GR64RegisterClass);
8655 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR64rr,
8656 X86::OR64ri32, X86::MOV64rm,
8657 X86::LCMPXCHG64, X86::MOV64rr,
8658 X86::NOT64r, X86::RAX,
8659 X86::GR64RegisterClass);
8660 case X86::ATOMXOR64:
8661 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR64rr,
8662 X86::XOR64ri32, X86::MOV64rm,
8663 X86::LCMPXCHG64, X86::MOV64rr,
8664 X86::NOT64r, X86::RAX,
8665 X86::GR64RegisterClass);
8666 case X86::ATOMNAND64:
8667 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND64rr,
8668 X86::AND64ri32, X86::MOV64rm,
8669 X86::LCMPXCHG64, X86::MOV64rr,
8670 X86::NOT64r, X86::RAX,
8671 X86::GR64RegisterClass, true);
8672 case X86::ATOMMIN64:
8673 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL64rr);
8674 case X86::ATOMMAX64:
8675 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG64rr);
8676 case X86::ATOMUMIN64:
8677 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB64rr);
8678 case X86::ATOMUMAX64:
8679 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA64rr);
8681 // This group does 64-bit operations on a 32-bit host.
8682 case X86::ATOMAND6432:
8683 return EmitAtomicBit6432WithCustomInserter(MI, BB,
8684 X86::AND32rr, X86::AND32rr,
8685 X86::AND32ri, X86::AND32ri,
8687 case X86::ATOMOR6432:
8688 return EmitAtomicBit6432WithCustomInserter(MI, BB,
8689 X86::OR32rr, X86::OR32rr,
8690 X86::OR32ri, X86::OR32ri,
8692 case X86::ATOMXOR6432:
8693 return EmitAtomicBit6432WithCustomInserter(MI, BB,
8694 X86::XOR32rr, X86::XOR32rr,
8695 X86::XOR32ri, X86::XOR32ri,
8697 case X86::ATOMNAND6432:
8698 return EmitAtomicBit6432WithCustomInserter(MI, BB,
8699 X86::AND32rr, X86::AND32rr,
8700 X86::AND32ri, X86::AND32ri,
8702 case X86::ATOMADD6432:
8703 return EmitAtomicBit6432WithCustomInserter(MI, BB,
8704 X86::ADD32rr, X86::ADC32rr,
8705 X86::ADD32ri, X86::ADC32ri,
8707 case X86::ATOMSUB6432:
8708 return EmitAtomicBit6432WithCustomInserter(MI, BB,
8709 X86::SUB32rr, X86::SBB32rr,
8710 X86::SUB32ri, X86::SBB32ri,
8712 case X86::ATOMSWAP6432:
8713 return EmitAtomicBit6432WithCustomInserter(MI, BB,
8714 X86::MOV32rr, X86::MOV32rr,
8715 X86::MOV32ri, X86::MOV32ri,
8717 case X86::VASTART_SAVE_XMM_REGS:
8718 return EmitVAStartSaveXMMRegsWithCustomInserter(MI, BB);
8722 //===----------------------------------------------------------------------===//
8723 // X86 Optimization Hooks
8724 //===----------------------------------------------------------------------===//
8726 void X86TargetLowering::computeMaskedBitsForTargetNode(const SDValue Op,
8730 const SelectionDAG &DAG,
8731 unsigned Depth) const {
8732 unsigned Opc = Op.getOpcode();
8733 assert((Opc >= ISD::BUILTIN_OP_END ||
8734 Opc == ISD::INTRINSIC_WO_CHAIN ||
8735 Opc == ISD::INTRINSIC_W_CHAIN ||
8736 Opc == ISD::INTRINSIC_VOID) &&
8737 "Should use MaskedValueIsZero if you don't know whether Op"
8738 " is a target node!");
8740 KnownZero = KnownOne = APInt(Mask.getBitWidth(), 0); // Don't know anything.
8752 // These nodes' second result is a boolean.
8753 if (Op.getResNo() == 0)
8757 KnownZero |= APInt::getHighBitsSet(Mask.getBitWidth(),
8758 Mask.getBitWidth() - 1);
8763 /// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the
8764 /// node is a GlobalAddress + offset.
8765 bool X86TargetLowering::isGAPlusOffset(SDNode *N,
8766 GlobalValue* &GA, int64_t &Offset) const{
8767 if (N->getOpcode() == X86ISD::Wrapper) {
8768 if (isa<GlobalAddressSDNode>(N->getOperand(0))) {
8769 GA = cast<GlobalAddressSDNode>(N->getOperand(0))->getGlobal();
8770 Offset = cast<GlobalAddressSDNode>(N->getOperand(0))->getOffset();
8774 return TargetLowering::isGAPlusOffset(N, GA, Offset);
8777 static bool EltsFromConsecutiveLoads(ShuffleVectorSDNode *N, unsigned NumElems,
8778 EVT EltVT, LoadSDNode *&LDBase,
8779 unsigned &LastLoadedElt,
8780 SelectionDAG &DAG, MachineFrameInfo *MFI,
8781 const TargetLowering &TLI) {
8783 LastLoadedElt = -1U;
8784 for (unsigned i = 0; i < NumElems; ++i) {
8785 if (N->getMaskElt(i) < 0) {
8791 SDValue Elt = DAG.getShuffleScalarElt(N, i);
8792 if (!Elt.getNode() ||
8793 (Elt.getOpcode() != ISD::UNDEF && !ISD::isNON_EXTLoad(Elt.getNode())))
8796 if (Elt.getNode()->getOpcode() == ISD::UNDEF)
8798 LDBase = cast<LoadSDNode>(Elt.getNode());
8802 if (Elt.getOpcode() == ISD::UNDEF)
8805 LoadSDNode *LD = cast<LoadSDNode>(Elt);
8806 if (!DAG.isConsecutiveLoad(LD, LDBase, EltVT.getSizeInBits()/8, i))
8813 /// PerformShuffleCombine - Combine a vector_shuffle that is equal to
8814 /// build_vector load1, load2, load3, load4, <0, 1, 2, 3> into a 128-bit load
8815 /// if the load addresses are consecutive, non-overlapping, and in the right
8816 /// order. In the case of v2i64, it will see if it can rewrite the
8817 /// shuffle to be an appropriate build vector so it can take advantage of
8818 // performBuildVectorCombine.
8819 static SDValue PerformShuffleCombine(SDNode *N, SelectionDAG &DAG,
8820 const TargetLowering &TLI) {
8821 DebugLoc dl = N->getDebugLoc();
8822 EVT VT = N->getValueType(0);
8823 EVT EltVT = VT.getVectorElementType();
8824 ShuffleVectorSDNode *SVN = cast<ShuffleVectorSDNode>(N);
8825 unsigned NumElems = VT.getVectorNumElements();
8827 if (VT.getSizeInBits() != 128)
8830 // Try to combine a vector_shuffle into a 128-bit load.
8831 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
8832 LoadSDNode *LD = NULL;
8833 unsigned LastLoadedElt;
8834 if (!EltsFromConsecutiveLoads(SVN, NumElems, EltVT, LD, LastLoadedElt, DAG,
8838 if (LastLoadedElt == NumElems - 1) {
8839 if (DAG.InferPtrAlignment(LD->getBasePtr()) >= 16)
8840 return DAG.getLoad(VT, dl, LD->getChain(), LD->getBasePtr(),
8841 LD->getSrcValue(), LD->getSrcValueOffset(),
8842 LD->isVolatile(), LD->isNonTemporal(), 0);
8843 return DAG.getLoad(VT, dl, LD->getChain(), LD->getBasePtr(),
8844 LD->getSrcValue(), LD->getSrcValueOffset(),
8845 LD->isVolatile(), LD->isNonTemporal(),
8846 LD->getAlignment());
8847 } else if (NumElems == 4 && LastLoadedElt == 1) {
8848 SDVTList Tys = DAG.getVTList(MVT::v2i64, MVT::Other);
8849 SDValue Ops[] = { LD->getChain(), LD->getBasePtr() };
8850 SDValue ResNode = DAG.getNode(X86ISD::VZEXT_LOAD, dl, Tys, Ops, 2);
8851 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, ResNode);
8856 /// PerformSELECTCombine - Do target-specific dag combines on SELECT nodes.
8857 static SDValue PerformSELECTCombine(SDNode *N, SelectionDAG &DAG,
8858 const X86Subtarget *Subtarget) {
8859 DebugLoc DL = N->getDebugLoc();
8860 SDValue Cond = N->getOperand(0);
8861 // Get the LHS/RHS of the select.
8862 SDValue LHS = N->getOperand(1);
8863 SDValue RHS = N->getOperand(2);
8865 // If we have SSE[12] support, try to form min/max nodes. SSE min/max
8866 // instructions match the semantics of the common C idiom x<y?x:y but not
8867 // x<=y?x:y, because of how they handle negative zero (which can be
8868 // ignored in unsafe-math mode).
8869 if (Subtarget->hasSSE2() &&
8870 (LHS.getValueType() == MVT::f32 || LHS.getValueType() == MVT::f64) &&
8871 Cond.getOpcode() == ISD::SETCC) {
8872 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
8874 unsigned Opcode = 0;
8875 // Check for x CC y ? x : y.
8876 if (DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
8877 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
8881 // Converting this to a min would handle NaNs incorrectly, and swapping
8882 // the operands would cause it to handle comparisons between positive
8883 // and negative zero incorrectly.
8884 if (!FiniteOnlyFPMath() &&
8885 (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))) {
8886 if (!UnsafeFPMath &&
8887 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
8889 std::swap(LHS, RHS);
8891 Opcode = X86ISD::FMIN;
8894 // Converting this to a min would handle comparisons between positive
8895 // and negative zero incorrectly.
8896 if (!UnsafeFPMath &&
8897 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
8899 Opcode = X86ISD::FMIN;
8902 // Converting this to a min would handle both negative zeros and NaNs
8903 // incorrectly, but we can swap the operands to fix both.
8904 std::swap(LHS, RHS);
8908 Opcode = X86ISD::FMIN;
8912 // Converting this to a max would handle comparisons between positive
8913 // and negative zero incorrectly.
8914 if (!UnsafeFPMath &&
8915 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(LHS))
8917 Opcode = X86ISD::FMAX;
8920 // Converting this to a max would handle NaNs incorrectly, and swapping
8921 // the operands would cause it to handle comparisons between positive
8922 // and negative zero incorrectly.
8923 if (!FiniteOnlyFPMath() &&
8924 (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))) {
8925 if (!UnsafeFPMath &&
8926 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
8928 std::swap(LHS, RHS);
8930 Opcode = X86ISD::FMAX;
8933 // Converting this to a max would handle both negative zeros and NaNs
8934 // incorrectly, but we can swap the operands to fix both.
8935 std::swap(LHS, RHS);
8939 Opcode = X86ISD::FMAX;
8942 // Check for x CC y ? y : x -- a min/max with reversed arms.
8943 } else if (DAG.isEqualTo(LHS, Cond.getOperand(1)) &&
8944 DAG.isEqualTo(RHS, Cond.getOperand(0))) {
8948 // Converting this to a min would handle comparisons between positive
8949 // and negative zero incorrectly, and swapping the operands would
8950 // cause it to handle NaNs incorrectly.
8951 if (!UnsafeFPMath &&
8952 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS))) {
8953 if (!FiniteOnlyFPMath() &&
8954 (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)))
8956 std::swap(LHS, RHS);
8958 Opcode = X86ISD::FMIN;
8961 // Converting this to a min would handle NaNs incorrectly.
8962 if (!UnsafeFPMath &&
8963 (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)))
8965 Opcode = X86ISD::FMIN;
8968 // Converting this to a min would handle both negative zeros and NaNs
8969 // incorrectly, but we can swap the operands to fix both.
8970 std::swap(LHS, RHS);
8974 Opcode = X86ISD::FMIN;
8978 // Converting this to a max would handle NaNs incorrectly.
8979 if (!FiniteOnlyFPMath() &&
8980 (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)))
8982 Opcode = X86ISD::FMAX;
8985 // Converting this to a max would handle comparisons between positive
8986 // and negative zero incorrectly, and swapping the operands would
8987 // cause it to handle NaNs incorrectly.
8988 if (!UnsafeFPMath &&
8989 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS)) {
8990 if (!FiniteOnlyFPMath() &&
8991 (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)))
8993 std::swap(LHS, RHS);
8995 Opcode = X86ISD::FMAX;
8998 // Converting this to a max would handle both negative zeros and NaNs
8999 // incorrectly, but we can swap the operands to fix both.
9000 std::swap(LHS, RHS);
9004 Opcode = X86ISD::FMAX;
9010 return DAG.getNode(Opcode, DL, N->getValueType(0), LHS, RHS);
9013 // If this is a select between two integer constants, try to do some
9015 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(LHS)) {
9016 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(RHS))
9017 // Don't do this for crazy integer types.
9018 if (DAG.getTargetLoweringInfo().isTypeLegal(LHS.getValueType())) {
9019 // If this is efficiently invertible, canonicalize the LHSC/RHSC values
9020 // so that TrueC (the true value) is larger than FalseC.
9021 bool NeedsCondInvert = false;
9023 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue()) &&
9024 // Efficiently invertible.
9025 (Cond.getOpcode() == ISD::SETCC || // setcc -> invertible.
9026 (Cond.getOpcode() == ISD::XOR && // xor(X, C) -> invertible.
9027 isa<ConstantSDNode>(Cond.getOperand(1))))) {
9028 NeedsCondInvert = true;
9029 std::swap(TrueC, FalseC);
9032 // Optimize C ? 8 : 0 -> zext(C) << 3. Likewise for any pow2/0.
9033 if (FalseC->getAPIntValue() == 0 &&
9034 TrueC->getAPIntValue().isPowerOf2()) {
9035 if (NeedsCondInvert) // Invert the condition if needed.
9036 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
9037 DAG.getConstant(1, Cond.getValueType()));
9039 // Zero extend the condition if needed.
9040 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, LHS.getValueType(), Cond);
9042 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
9043 return DAG.getNode(ISD::SHL, DL, LHS.getValueType(), Cond,
9044 DAG.getConstant(ShAmt, MVT::i8));
9047 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst.
9048 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
9049 if (NeedsCondInvert) // Invert the condition if needed.
9050 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
9051 DAG.getConstant(1, Cond.getValueType()));
9053 // Zero extend the condition if needed.
9054 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
9055 FalseC->getValueType(0), Cond);
9056 return DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
9057 SDValue(FalseC, 0));
9060 // Optimize cases that will turn into an LEA instruction. This requires
9061 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
9062 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
9063 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
9064 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
9066 bool isFastMultiplier = false;
9068 switch ((unsigned char)Diff) {
9070 case 1: // result = add base, cond
9071 case 2: // result = lea base( , cond*2)
9072 case 3: // result = lea base(cond, cond*2)
9073 case 4: // result = lea base( , cond*4)
9074 case 5: // result = lea base(cond, cond*4)
9075 case 8: // result = lea base( , cond*8)
9076 case 9: // result = lea base(cond, cond*8)
9077 isFastMultiplier = true;
9082 if (isFastMultiplier) {
9083 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
9084 if (NeedsCondInvert) // Invert the condition if needed.
9085 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
9086 DAG.getConstant(1, Cond.getValueType()));
9088 // Zero extend the condition if needed.
9089 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
9091 // Scale the condition by the difference.
9093 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
9094 DAG.getConstant(Diff, Cond.getValueType()));
9096 // Add the base if non-zero.
9097 if (FalseC->getAPIntValue() != 0)
9098 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
9099 SDValue(FalseC, 0));
9109 /// Optimize X86ISD::CMOV [LHS, RHS, CONDCODE (e.g. X86::COND_NE), CONDVAL]
9110 static SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG,
9111 TargetLowering::DAGCombinerInfo &DCI) {
9112 DebugLoc DL = N->getDebugLoc();
9114 // If the flag operand isn't dead, don't touch this CMOV.
9115 if (N->getNumValues() == 2 && !SDValue(N, 1).use_empty())
9118 // If this is a select between two integer constants, try to do some
9119 // optimizations. Note that the operands are ordered the opposite of SELECT
9121 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(N->getOperand(1))) {
9122 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(N->getOperand(0))) {
9123 // Canonicalize the TrueC/FalseC values so that TrueC (the true value) is
9124 // larger than FalseC (the false value).
9125 X86::CondCode CC = (X86::CondCode)N->getConstantOperandVal(2);
9127 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue())) {
9128 CC = X86::GetOppositeBranchCondition(CC);
9129 std::swap(TrueC, FalseC);
9132 // Optimize C ? 8 : 0 -> zext(setcc(C)) << 3. Likewise for any pow2/0.
9133 // This is efficient for any integer data type (including i8/i16) and
9135 if (FalseC->getAPIntValue() == 0 && TrueC->getAPIntValue().isPowerOf2()) {
9136 SDValue Cond = N->getOperand(3);
9137 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
9138 DAG.getConstant(CC, MVT::i8), Cond);
9140 // Zero extend the condition if needed.
9141 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, TrueC->getValueType(0), Cond);
9143 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
9144 Cond = DAG.getNode(ISD::SHL, DL, Cond.getValueType(), Cond,
9145 DAG.getConstant(ShAmt, MVT::i8));
9146 if (N->getNumValues() == 2) // Dead flag value?
9147 return DCI.CombineTo(N, Cond, SDValue());
9151 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst. This is efficient
9152 // for any integer data type, including i8/i16.
9153 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
9154 SDValue Cond = N->getOperand(3);
9155 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
9156 DAG.getConstant(CC, MVT::i8), Cond);
9158 // Zero extend the condition if needed.
9159 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
9160 FalseC->getValueType(0), Cond);
9161 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
9162 SDValue(FalseC, 0));
9164 if (N->getNumValues() == 2) // Dead flag value?
9165 return DCI.CombineTo(N, Cond, SDValue());
9169 // Optimize cases that will turn into an LEA instruction. This requires
9170 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
9171 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
9172 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
9173 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
9175 bool isFastMultiplier = false;
9177 switch ((unsigned char)Diff) {
9179 case 1: // result = add base, cond
9180 case 2: // result = lea base( , cond*2)
9181 case 3: // result = lea base(cond, cond*2)
9182 case 4: // result = lea base( , cond*4)
9183 case 5: // result = lea base(cond, cond*4)
9184 case 8: // result = lea base( , cond*8)
9185 case 9: // result = lea base(cond, cond*8)
9186 isFastMultiplier = true;
9191 if (isFastMultiplier) {
9192 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
9193 SDValue Cond = N->getOperand(3);
9194 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
9195 DAG.getConstant(CC, MVT::i8), Cond);
9196 // Zero extend the condition if needed.
9197 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
9199 // Scale the condition by the difference.
9201 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
9202 DAG.getConstant(Diff, Cond.getValueType()));
9204 // Add the base if non-zero.
9205 if (FalseC->getAPIntValue() != 0)
9206 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
9207 SDValue(FalseC, 0));
9208 if (N->getNumValues() == 2) // Dead flag value?
9209 return DCI.CombineTo(N, Cond, SDValue());
9219 /// PerformMulCombine - Optimize a single multiply with constant into two
9220 /// in order to implement it with two cheaper instructions, e.g.
9221 /// LEA + SHL, LEA + LEA.
9222 static SDValue PerformMulCombine(SDNode *N, SelectionDAG &DAG,
9223 TargetLowering::DAGCombinerInfo &DCI) {
9224 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer())
9227 EVT VT = N->getValueType(0);
9231 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
9234 uint64_t MulAmt = C->getZExtValue();
9235 if (isPowerOf2_64(MulAmt) || MulAmt == 3 || MulAmt == 5 || MulAmt == 9)
9238 uint64_t MulAmt1 = 0;
9239 uint64_t MulAmt2 = 0;
9240 if ((MulAmt % 9) == 0) {
9242 MulAmt2 = MulAmt / 9;
9243 } else if ((MulAmt % 5) == 0) {
9245 MulAmt2 = MulAmt / 5;
9246 } else if ((MulAmt % 3) == 0) {
9248 MulAmt2 = MulAmt / 3;
9251 (isPowerOf2_64(MulAmt2) || MulAmt2 == 3 || MulAmt2 == 5 || MulAmt2 == 9)){
9252 DebugLoc DL = N->getDebugLoc();
9254 if (isPowerOf2_64(MulAmt2) &&
9255 !(N->hasOneUse() && N->use_begin()->getOpcode() == ISD::ADD))
9256 // If second multiplifer is pow2, issue it first. We want the multiply by
9257 // 3, 5, or 9 to be folded into the addressing mode unless the lone use
9259 std::swap(MulAmt1, MulAmt2);
9262 if (isPowerOf2_64(MulAmt1))
9263 NewMul = DAG.getNode(ISD::SHL, DL, VT, N->getOperand(0),
9264 DAG.getConstant(Log2_64(MulAmt1), MVT::i8));
9266 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, N->getOperand(0),
9267 DAG.getConstant(MulAmt1, VT));
9269 if (isPowerOf2_64(MulAmt2))
9270 NewMul = DAG.getNode(ISD::SHL, DL, VT, NewMul,
9271 DAG.getConstant(Log2_64(MulAmt2), MVT::i8));
9273 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, NewMul,
9274 DAG.getConstant(MulAmt2, VT));
9276 // Do not add new nodes to DAG combiner worklist.
9277 DCI.CombineTo(N, NewMul, false);
9282 static SDValue PerformSHLCombine(SDNode *N, SelectionDAG &DAG) {
9283 SDValue N0 = N->getOperand(0);
9284 SDValue N1 = N->getOperand(1);
9285 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
9286 EVT VT = N0.getValueType();
9288 // fold (shl (and (setcc_c), c1), c2) -> (and setcc_c, (c1 << c2))
9289 // since the result of setcc_c is all zero's or all ones.
9290 if (N1C && N0.getOpcode() == ISD::AND &&
9291 N0.getOperand(1).getOpcode() == ISD::Constant) {
9292 SDValue N00 = N0.getOperand(0);
9293 if (N00.getOpcode() == X86ISD::SETCC_CARRY ||
9294 ((N00.getOpcode() == ISD::ANY_EXTEND ||
9295 N00.getOpcode() == ISD::ZERO_EXTEND) &&
9296 N00.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY)) {
9297 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
9298 APInt ShAmt = N1C->getAPIntValue();
9299 Mask = Mask.shl(ShAmt);
9301 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT,
9302 N00, DAG.getConstant(Mask, VT));
9309 /// PerformShiftCombine - Transforms vector shift nodes to use vector shifts
9311 static SDValue PerformShiftCombine(SDNode* N, SelectionDAG &DAG,
9312 const X86Subtarget *Subtarget) {
9313 EVT VT = N->getValueType(0);
9314 if (!VT.isVector() && VT.isInteger() &&
9315 N->getOpcode() == ISD::SHL)
9316 return PerformSHLCombine(N, DAG);
9318 // On X86 with SSE2 support, we can transform this to a vector shift if
9319 // all elements are shifted by the same amount. We can't do this in legalize
9320 // because the a constant vector is typically transformed to a constant pool
9321 // so we have no knowledge of the shift amount.
9322 if (!Subtarget->hasSSE2())
9325 if (VT != MVT::v2i64 && VT != MVT::v4i32 && VT != MVT::v8i16)
9328 SDValue ShAmtOp = N->getOperand(1);
9329 EVT EltVT = VT.getVectorElementType();
9330 DebugLoc DL = N->getDebugLoc();
9331 SDValue BaseShAmt = SDValue();
9332 if (ShAmtOp.getOpcode() == ISD::BUILD_VECTOR) {
9333 unsigned NumElts = VT.getVectorNumElements();
9335 for (; i != NumElts; ++i) {
9336 SDValue Arg = ShAmtOp.getOperand(i);
9337 if (Arg.getOpcode() == ISD::UNDEF) continue;
9341 for (; i != NumElts; ++i) {
9342 SDValue Arg = ShAmtOp.getOperand(i);
9343 if (Arg.getOpcode() == ISD::UNDEF) continue;
9344 if (Arg != BaseShAmt) {
9348 } else if (ShAmtOp.getOpcode() == ISD::VECTOR_SHUFFLE &&
9349 cast<ShuffleVectorSDNode>(ShAmtOp)->isSplat()) {
9350 SDValue InVec = ShAmtOp.getOperand(0);
9351 if (InVec.getOpcode() == ISD::BUILD_VECTOR) {
9352 unsigned NumElts = InVec.getValueType().getVectorNumElements();
9354 for (; i != NumElts; ++i) {
9355 SDValue Arg = InVec.getOperand(i);
9356 if (Arg.getOpcode() == ISD::UNDEF) continue;
9360 } else if (InVec.getOpcode() == ISD::INSERT_VECTOR_ELT) {
9361 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(InVec.getOperand(2))) {
9362 unsigned SplatIdx= cast<ShuffleVectorSDNode>(ShAmtOp)->getSplatIndex();
9363 if (C->getZExtValue() == SplatIdx)
9364 BaseShAmt = InVec.getOperand(1);
9367 if (BaseShAmt.getNode() == 0)
9368 BaseShAmt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, EltVT, ShAmtOp,
9369 DAG.getIntPtrConstant(0));
9373 // The shift amount is an i32.
9374 if (EltVT.bitsGT(MVT::i32))
9375 BaseShAmt = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, BaseShAmt);
9376 else if (EltVT.bitsLT(MVT::i32))
9377 BaseShAmt = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i32, BaseShAmt);
9379 // The shift amount is identical so we can do a vector shift.
9380 SDValue ValOp = N->getOperand(0);
9381 switch (N->getOpcode()) {
9383 llvm_unreachable("Unknown shift opcode!");
9386 if (VT == MVT::v2i64)
9387 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
9388 DAG.getConstant(Intrinsic::x86_sse2_pslli_q, MVT::i32),
9390 if (VT == MVT::v4i32)
9391 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
9392 DAG.getConstant(Intrinsic::x86_sse2_pslli_d, MVT::i32),
9394 if (VT == MVT::v8i16)
9395 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
9396 DAG.getConstant(Intrinsic::x86_sse2_pslli_w, MVT::i32),
9400 if (VT == MVT::v4i32)
9401 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
9402 DAG.getConstant(Intrinsic::x86_sse2_psrai_d, MVT::i32),
9404 if (VT == MVT::v8i16)
9405 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
9406 DAG.getConstant(Intrinsic::x86_sse2_psrai_w, MVT::i32),
9410 if (VT == MVT::v2i64)
9411 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
9412 DAG.getConstant(Intrinsic::x86_sse2_psrli_q, MVT::i32),
9414 if (VT == MVT::v4i32)
9415 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
9416 DAG.getConstant(Intrinsic::x86_sse2_psrli_d, MVT::i32),
9418 if (VT == MVT::v8i16)
9419 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
9420 DAG.getConstant(Intrinsic::x86_sse2_psrli_w, MVT::i32),
9427 static SDValue PerformOrCombine(SDNode *N, SelectionDAG &DAG,
9428 const X86Subtarget *Subtarget) {
9429 EVT VT = N->getValueType(0);
9430 if (VT != MVT::i64 || !Subtarget->is64Bit())
9433 // fold (or (x << c) | (y >> (64 - c))) ==> (shld64 x, y, c)
9434 SDValue N0 = N->getOperand(0);
9435 SDValue N1 = N->getOperand(1);
9436 if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL)
9438 if (N0.getOpcode() != ISD::SHL || N1.getOpcode() != ISD::SRL)
9441 SDValue ShAmt0 = N0.getOperand(1);
9442 if (ShAmt0.getValueType() != MVT::i8)
9444 SDValue ShAmt1 = N1.getOperand(1);
9445 if (ShAmt1.getValueType() != MVT::i8)
9447 if (ShAmt0.getOpcode() == ISD::TRUNCATE)
9448 ShAmt0 = ShAmt0.getOperand(0);
9449 if (ShAmt1.getOpcode() == ISD::TRUNCATE)
9450 ShAmt1 = ShAmt1.getOperand(0);
9452 DebugLoc DL = N->getDebugLoc();
9453 unsigned Opc = X86ISD::SHLD;
9454 SDValue Op0 = N0.getOperand(0);
9455 SDValue Op1 = N1.getOperand(0);
9456 if (ShAmt0.getOpcode() == ISD::SUB) {
9458 std::swap(Op0, Op1);
9459 std::swap(ShAmt0, ShAmt1);
9462 if (ShAmt1.getOpcode() == ISD::SUB) {
9463 SDValue Sum = ShAmt1.getOperand(0);
9464 if (ConstantSDNode *SumC = dyn_cast<ConstantSDNode>(Sum)) {
9465 if (SumC->getSExtValue() == 64 &&
9466 ShAmt1.getOperand(1) == ShAmt0)
9467 return DAG.getNode(Opc, DL, VT,
9469 DAG.getNode(ISD::TRUNCATE, DL,
9472 } else if (ConstantSDNode *ShAmt1C = dyn_cast<ConstantSDNode>(ShAmt1)) {
9473 ConstantSDNode *ShAmt0C = dyn_cast<ConstantSDNode>(ShAmt0);
9475 ShAmt0C->getSExtValue() + ShAmt1C->getSExtValue() == 64)
9476 return DAG.getNode(Opc, DL, VT,
9477 N0.getOperand(0), N1.getOperand(0),
9478 DAG.getNode(ISD::TRUNCATE, DL,
9485 /// PerformSTORECombine - Do target-specific dag combines on STORE nodes.
9486 static SDValue PerformSTORECombine(SDNode *N, SelectionDAG &DAG,
9487 const X86Subtarget *Subtarget) {
9488 // Turn load->store of MMX types into GPR load/stores. This avoids clobbering
9489 // the FP state in cases where an emms may be missing.
9490 // A preferable solution to the general problem is to figure out the right
9491 // places to insert EMMS. This qualifies as a quick hack.
9493 // Similarly, turn load->store of i64 into double load/stores in 32-bit mode.
9494 StoreSDNode *St = cast<StoreSDNode>(N);
9495 EVT VT = St->getValue().getValueType();
9496 if (VT.getSizeInBits() != 64)
9499 const Function *F = DAG.getMachineFunction().getFunction();
9500 bool NoImplicitFloatOps = F->hasFnAttr(Attribute::NoImplicitFloat);
9501 bool F64IsLegal = !UseSoftFloat && !NoImplicitFloatOps
9502 && Subtarget->hasSSE2();
9503 if ((VT.isVector() ||
9504 (VT == MVT::i64 && F64IsLegal && !Subtarget->is64Bit())) &&
9505 isa<LoadSDNode>(St->getValue()) &&
9506 !cast<LoadSDNode>(St->getValue())->isVolatile() &&
9507 St->getChain().hasOneUse() && !St->isVolatile()) {
9508 SDNode* LdVal = St->getValue().getNode();
9510 int TokenFactorIndex = -1;
9511 SmallVector<SDValue, 8> Ops;
9512 SDNode* ChainVal = St->getChain().getNode();
9513 // Must be a store of a load. We currently handle two cases: the load
9514 // is a direct child, and it's under an intervening TokenFactor. It is
9515 // possible to dig deeper under nested TokenFactors.
9516 if (ChainVal == LdVal)
9517 Ld = cast<LoadSDNode>(St->getChain());
9518 else if (St->getValue().hasOneUse() &&
9519 ChainVal->getOpcode() == ISD::TokenFactor) {
9520 for (unsigned i=0, e = ChainVal->getNumOperands(); i != e; ++i) {
9521 if (ChainVal->getOperand(i).getNode() == LdVal) {
9522 TokenFactorIndex = i;
9523 Ld = cast<LoadSDNode>(St->getValue());
9525 Ops.push_back(ChainVal->getOperand(i));
9529 if (!Ld || !ISD::isNormalLoad(Ld))
9532 // If this is not the MMX case, i.e. we are just turning i64 load/store
9533 // into f64 load/store, avoid the transformation if there are multiple
9534 // uses of the loaded value.
9535 if (!VT.isVector() && !Ld->hasNUsesOfValue(1, 0))
9538 DebugLoc LdDL = Ld->getDebugLoc();
9539 DebugLoc StDL = N->getDebugLoc();
9540 // If we are a 64-bit capable x86, lower to a single movq load/store pair.
9541 // Otherwise, if it's legal to use f64 SSE instructions, use f64 load/store
9543 if (Subtarget->is64Bit() || F64IsLegal) {
9544 EVT LdVT = Subtarget->is64Bit() ? MVT::i64 : MVT::f64;
9545 SDValue NewLd = DAG.getLoad(LdVT, LdDL, Ld->getChain(),
9546 Ld->getBasePtr(), Ld->getSrcValue(),
9547 Ld->getSrcValueOffset(), Ld->isVolatile(),
9548 Ld->isNonTemporal(), Ld->getAlignment());
9549 SDValue NewChain = NewLd.getValue(1);
9550 if (TokenFactorIndex != -1) {
9551 Ops.push_back(NewChain);
9552 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, &Ops[0],
9555 return DAG.getStore(NewChain, StDL, NewLd, St->getBasePtr(),
9556 St->getSrcValue(), St->getSrcValueOffset(),
9557 St->isVolatile(), St->isNonTemporal(),
9558 St->getAlignment());
9561 // Otherwise, lower to two pairs of 32-bit loads / stores.
9562 SDValue LoAddr = Ld->getBasePtr();
9563 SDValue HiAddr = DAG.getNode(ISD::ADD, LdDL, MVT::i32, LoAddr,
9564 DAG.getConstant(4, MVT::i32));
9566 SDValue LoLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), LoAddr,
9567 Ld->getSrcValue(), Ld->getSrcValueOffset(),
9568 Ld->isVolatile(), Ld->isNonTemporal(),
9569 Ld->getAlignment());
9570 SDValue HiLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), HiAddr,
9571 Ld->getSrcValue(), Ld->getSrcValueOffset()+4,
9572 Ld->isVolatile(), Ld->isNonTemporal(),
9573 MinAlign(Ld->getAlignment(), 4));
9575 SDValue NewChain = LoLd.getValue(1);
9576 if (TokenFactorIndex != -1) {
9577 Ops.push_back(LoLd);
9578 Ops.push_back(HiLd);
9579 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, &Ops[0],
9583 LoAddr = St->getBasePtr();
9584 HiAddr = DAG.getNode(ISD::ADD, StDL, MVT::i32, LoAddr,
9585 DAG.getConstant(4, MVT::i32));
9587 SDValue LoSt = DAG.getStore(NewChain, StDL, LoLd, LoAddr,
9588 St->getSrcValue(), St->getSrcValueOffset(),
9589 St->isVolatile(), St->isNonTemporal(),
9590 St->getAlignment());
9591 SDValue HiSt = DAG.getStore(NewChain, StDL, HiLd, HiAddr,
9593 St->getSrcValueOffset() + 4,
9595 St->isNonTemporal(),
9596 MinAlign(St->getAlignment(), 4));
9597 return DAG.getNode(ISD::TokenFactor, StDL, MVT::Other, LoSt, HiSt);
9602 /// PerformFORCombine - Do target-specific dag combines on X86ISD::FOR and
9603 /// X86ISD::FXOR nodes.
9604 static SDValue PerformFORCombine(SDNode *N, SelectionDAG &DAG) {
9605 assert(N->getOpcode() == X86ISD::FOR || N->getOpcode() == X86ISD::FXOR);
9606 // F[X]OR(0.0, x) -> x
9607 // F[X]OR(x, 0.0) -> x
9608 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
9609 if (C->getValueAPF().isPosZero())
9610 return N->getOperand(1);
9611 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
9612 if (C->getValueAPF().isPosZero())
9613 return N->getOperand(0);
9617 /// PerformFANDCombine - Do target-specific dag combines on X86ISD::FAND nodes.
9618 static SDValue PerformFANDCombine(SDNode *N, SelectionDAG &DAG) {
9619 // FAND(0.0, x) -> 0.0
9620 // FAND(x, 0.0) -> 0.0
9621 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
9622 if (C->getValueAPF().isPosZero())
9623 return N->getOperand(0);
9624 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
9625 if (C->getValueAPF().isPosZero())
9626 return N->getOperand(1);
9630 static SDValue PerformBTCombine(SDNode *N,
9632 TargetLowering::DAGCombinerInfo &DCI) {
9633 // BT ignores high bits in the bit index operand.
9634 SDValue Op1 = N->getOperand(1);
9635 if (Op1.hasOneUse()) {
9636 unsigned BitWidth = Op1.getValueSizeInBits();
9637 APInt DemandedMask = APInt::getLowBitsSet(BitWidth, Log2_32(BitWidth));
9638 APInt KnownZero, KnownOne;
9639 TargetLowering::TargetLoweringOpt TLO(DAG);
9640 TargetLowering &TLI = DAG.getTargetLoweringInfo();
9641 if (TLO.ShrinkDemandedConstant(Op1, DemandedMask) ||
9642 TLI.SimplifyDemandedBits(Op1, DemandedMask, KnownZero, KnownOne, TLO))
9643 DCI.CommitTargetLoweringOpt(TLO);
9648 static SDValue PerformVZEXT_MOVLCombine(SDNode *N, SelectionDAG &DAG) {
9649 SDValue Op = N->getOperand(0);
9650 if (Op.getOpcode() == ISD::BIT_CONVERT)
9651 Op = Op.getOperand(0);
9652 EVT VT = N->getValueType(0), OpVT = Op.getValueType();
9653 if (Op.getOpcode() == X86ISD::VZEXT_LOAD &&
9654 VT.getVectorElementType().getSizeInBits() ==
9655 OpVT.getVectorElementType().getSizeInBits()) {
9656 return DAG.getNode(ISD::BIT_CONVERT, N->getDebugLoc(), VT, Op);
9661 // On X86 and X86-64, atomic operations are lowered to locked instructions.
9662 // Locked instructions, in turn, have implicit fence semantics (all memory
9663 // operations are flushed before issuing the locked instruction, and the
9664 // are not buffered), so we can fold away the common pattern of
9665 // fence-atomic-fence.
9666 static SDValue PerformMEMBARRIERCombine(SDNode* N, SelectionDAG &DAG) {
9667 SDValue atomic = N->getOperand(0);
9668 switch (atomic.getOpcode()) {
9669 case ISD::ATOMIC_CMP_SWAP:
9670 case ISD::ATOMIC_SWAP:
9671 case ISD::ATOMIC_LOAD_ADD:
9672 case ISD::ATOMIC_LOAD_SUB:
9673 case ISD::ATOMIC_LOAD_AND:
9674 case ISD::ATOMIC_LOAD_OR:
9675 case ISD::ATOMIC_LOAD_XOR:
9676 case ISD::ATOMIC_LOAD_NAND:
9677 case ISD::ATOMIC_LOAD_MIN:
9678 case ISD::ATOMIC_LOAD_MAX:
9679 case ISD::ATOMIC_LOAD_UMIN:
9680 case ISD::ATOMIC_LOAD_UMAX:
9686 SDValue fence = atomic.getOperand(0);
9687 if (fence.getOpcode() != ISD::MEMBARRIER)
9690 switch (atomic.getOpcode()) {
9691 case ISD::ATOMIC_CMP_SWAP:
9692 return DAG.UpdateNodeOperands(atomic, fence.getOperand(0),
9693 atomic.getOperand(1), atomic.getOperand(2),
9694 atomic.getOperand(3));
9695 case ISD::ATOMIC_SWAP:
9696 case ISD::ATOMIC_LOAD_ADD:
9697 case ISD::ATOMIC_LOAD_SUB:
9698 case ISD::ATOMIC_LOAD_AND:
9699 case ISD::ATOMIC_LOAD_OR:
9700 case ISD::ATOMIC_LOAD_XOR:
9701 case ISD::ATOMIC_LOAD_NAND:
9702 case ISD::ATOMIC_LOAD_MIN:
9703 case ISD::ATOMIC_LOAD_MAX:
9704 case ISD::ATOMIC_LOAD_UMIN:
9705 case ISD::ATOMIC_LOAD_UMAX:
9706 return DAG.UpdateNodeOperands(atomic, fence.getOperand(0),
9707 atomic.getOperand(1), atomic.getOperand(2));
9713 static SDValue PerformZExtCombine(SDNode *N, SelectionDAG &DAG) {
9714 // (i32 zext (and (i8 x86isd::setcc_carry), 1)) ->
9715 // (and (i32 x86isd::setcc_carry), 1)
9716 // This eliminates the zext. This transformation is necessary because
9717 // ISD::SETCC is always legalized to i8.
9718 DebugLoc dl = N->getDebugLoc();
9719 SDValue N0 = N->getOperand(0);
9720 EVT VT = N->getValueType(0);
9721 if (N0.getOpcode() == ISD::AND &&
9723 N0.getOperand(0).hasOneUse()) {
9724 SDValue N00 = N0.getOperand(0);
9725 if (N00.getOpcode() != X86ISD::SETCC_CARRY)
9727 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
9728 if (!C || C->getZExtValue() != 1)
9730 return DAG.getNode(ISD::AND, dl, VT,
9731 DAG.getNode(X86ISD::SETCC_CARRY, dl, VT,
9732 N00.getOperand(0), N00.getOperand(1)),
9733 DAG.getConstant(1, VT));
9739 SDValue X86TargetLowering::PerformDAGCombine(SDNode *N,
9740 DAGCombinerInfo &DCI) const {
9741 SelectionDAG &DAG = DCI.DAG;
9742 switch (N->getOpcode()) {
9744 case ISD::VECTOR_SHUFFLE: return PerformShuffleCombine(N, DAG, *this);
9745 case ISD::SELECT: return PerformSELECTCombine(N, DAG, Subtarget);
9746 case X86ISD::CMOV: return PerformCMOVCombine(N, DAG, DCI);
9747 case ISD::MUL: return PerformMulCombine(N, DAG, DCI);
9750 case ISD::SRL: return PerformShiftCombine(N, DAG, Subtarget);
9751 case ISD::OR: return PerformOrCombine(N, DAG, Subtarget);
9752 case ISD::STORE: return PerformSTORECombine(N, DAG, Subtarget);
9754 case X86ISD::FOR: return PerformFORCombine(N, DAG);
9755 case X86ISD::FAND: return PerformFANDCombine(N, DAG);
9756 case X86ISD::BT: return PerformBTCombine(N, DAG, DCI);
9757 case X86ISD::VZEXT_MOVL: return PerformVZEXT_MOVLCombine(N, DAG);
9758 case ISD::MEMBARRIER: return PerformMEMBARRIERCombine(N, DAG);
9759 case ISD::ZERO_EXTEND: return PerformZExtCombine(N, DAG);
9765 //===----------------------------------------------------------------------===//
9766 // X86 Inline Assembly Support
9767 //===----------------------------------------------------------------------===//
9769 static bool LowerToBSwap(CallInst *CI) {
9770 // FIXME: this should verify that we are targetting a 486 or better. If not,
9771 // we will turn this bswap into something that will be lowered to logical ops
9772 // instead of emitting the bswap asm. For now, we don't support 486 or lower
9773 // so don't worry about this.
9775 // Verify this is a simple bswap.
9776 if (CI->getNumOperands() != 2 ||
9777 CI->getType() != CI->getOperand(1)->getType() ||
9778 !CI->getType()->isIntegerTy())
9781 const IntegerType *Ty = dyn_cast<IntegerType>(CI->getType());
9782 if (!Ty || Ty->getBitWidth() % 16 != 0)
9785 // Okay, we can do this xform, do so now.
9786 const Type *Tys[] = { Ty };
9787 Module *M = CI->getParent()->getParent()->getParent();
9788 Constant *Int = Intrinsic::getDeclaration(M, Intrinsic::bswap, Tys, 1);
9790 Value *Op = CI->getOperand(1);
9791 Op = CallInst::Create(Int, Op, CI->getName(), CI);
9793 CI->replaceAllUsesWith(Op);
9794 CI->eraseFromParent();
9798 bool X86TargetLowering::ExpandInlineAsm(CallInst *CI) const {
9799 InlineAsm *IA = cast<InlineAsm>(CI->getCalledValue());
9800 std::vector<InlineAsm::ConstraintInfo> Constraints = IA->ParseConstraints();
9802 std::string AsmStr = IA->getAsmString();
9804 // TODO: should remove alternatives from the asmstring: "foo {a|b}" -> "foo a"
9805 SmallVector<StringRef, 4> AsmPieces;
9806 SplitString(AsmStr, AsmPieces, "\n"); // ; as separator?
9808 switch (AsmPieces.size()) {
9809 default: return false;
9811 AsmStr = AsmPieces[0];
9813 SplitString(AsmStr, AsmPieces, " \t"); // Split with whitespace.
9816 if (AsmPieces.size() == 2 &&
9817 (AsmPieces[0] == "bswap" ||
9818 AsmPieces[0] == "bswapq" ||
9819 AsmPieces[0] == "bswapl") &&
9820 (AsmPieces[1] == "$0" ||
9821 AsmPieces[1] == "${0:q}")) {
9822 // No need to check constraints, nothing other than the equivalent of
9823 // "=r,0" would be valid here.
9824 return LowerToBSwap(CI);
9826 // rorw $$8, ${0:w} --> llvm.bswap.i16
9827 if (CI->getType()->isIntegerTy(16) &&
9828 AsmPieces.size() == 3 &&
9829 (AsmPieces[0] == "rorw" || AsmPieces[0] == "rolw") &&
9830 AsmPieces[1] == "$$8," &&
9831 AsmPieces[2] == "${0:w}" &&
9832 IA->getConstraintString().compare(0, 5, "=r,0,") == 0) {
9834 const std::string &Constraints = IA->getConstraintString();
9835 SplitString(StringRef(Constraints).substr(5), AsmPieces, ",");
9836 std::sort(AsmPieces.begin(), AsmPieces.end());
9837 if (AsmPieces.size() == 4 &&
9838 AsmPieces[0] == "~{cc}" &&
9839 AsmPieces[1] == "~{dirflag}" &&
9840 AsmPieces[2] == "~{flags}" &&
9841 AsmPieces[3] == "~{fpsr}") {
9842 return LowerToBSwap(CI);
9847 if (CI->getType()->isIntegerTy(64) &&
9848 Constraints.size() >= 2 &&
9849 Constraints[0].Codes.size() == 1 && Constraints[0].Codes[0] == "A" &&
9850 Constraints[1].Codes.size() == 1 && Constraints[1].Codes[0] == "0") {
9851 // bswap %eax / bswap %edx / xchgl %eax, %edx -> llvm.bswap.i64
9852 SmallVector<StringRef, 4> Words;
9853 SplitString(AsmPieces[0], Words, " \t");
9854 if (Words.size() == 2 && Words[0] == "bswap" && Words[1] == "%eax") {
9856 SplitString(AsmPieces[1], Words, " \t");
9857 if (Words.size() == 2 && Words[0] == "bswap" && Words[1] == "%edx") {
9859 SplitString(AsmPieces[2], Words, " \t,");
9860 if (Words.size() == 3 && Words[0] == "xchgl" && Words[1] == "%eax" &&
9861 Words[2] == "%edx") {
9862 return LowerToBSwap(CI);
9874 /// getConstraintType - Given a constraint letter, return the type of
9875 /// constraint it is for this target.
9876 X86TargetLowering::ConstraintType
9877 X86TargetLowering::getConstraintType(const std::string &Constraint) const {
9878 if (Constraint.size() == 1) {
9879 switch (Constraint[0]) {
9891 return C_RegisterClass;
9899 return TargetLowering::getConstraintType(Constraint);
9902 /// LowerXConstraint - try to replace an X constraint, which matches anything,
9903 /// with another that has more specific requirements based on the type of the
9904 /// corresponding operand.
9905 const char *X86TargetLowering::
9906 LowerXConstraint(EVT ConstraintVT) const {
9907 // FP X constraints get lowered to SSE1/2 registers if available, otherwise
9908 // 'f' like normal targets.
9909 if (ConstraintVT.isFloatingPoint()) {
9910 if (Subtarget->hasSSE2())
9912 if (Subtarget->hasSSE1())
9916 return TargetLowering::LowerXConstraint(ConstraintVT);
9919 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
9920 /// vector. If it is invalid, don't add anything to Ops.
9921 void X86TargetLowering::LowerAsmOperandForConstraint(SDValue Op,
9924 std::vector<SDValue>&Ops,
9925 SelectionDAG &DAG) const {
9926 SDValue Result(0, 0);
9928 switch (Constraint) {
9931 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
9932 if (C->getZExtValue() <= 31) {
9933 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
9939 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
9940 if (C->getZExtValue() <= 63) {
9941 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
9947 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
9948 if ((int8_t)C->getSExtValue() == C->getSExtValue()) {
9949 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
9955 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
9956 if (C->getZExtValue() <= 255) {
9957 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
9963 // 32-bit signed value
9964 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
9965 const ConstantInt *CI = C->getConstantIntValue();
9966 if (CI->isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
9967 C->getSExtValue())) {
9968 // Widen to 64 bits here to get it sign extended.
9969 Result = DAG.getTargetConstant(C->getSExtValue(), MVT::i64);
9972 // FIXME gcc accepts some relocatable values here too, but only in certain
9973 // memory models; it's complicated.
9978 // 32-bit unsigned value
9979 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
9980 const ConstantInt *CI = C->getConstantIntValue();
9981 if (CI->isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
9982 C->getZExtValue())) {
9983 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
9987 // FIXME gcc accepts some relocatable values here too, but only in certain
9988 // memory models; it's complicated.
9992 // Literal immediates are always ok.
9993 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op)) {
9994 // Widen to 64 bits here to get it sign extended.
9995 Result = DAG.getTargetConstant(CST->getSExtValue(), MVT::i64);
9999 // If we are in non-pic codegen mode, we allow the address of a global (with
10000 // an optional displacement) to be used with 'i'.
10001 GlobalAddressSDNode *GA = 0;
10002 int64_t Offset = 0;
10004 // Match either (GA), (GA+C), (GA+C1+C2), etc.
10006 if ((GA = dyn_cast<GlobalAddressSDNode>(Op))) {
10007 Offset += GA->getOffset();
10009 } else if (Op.getOpcode() == ISD::ADD) {
10010 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
10011 Offset += C->getZExtValue();
10012 Op = Op.getOperand(0);
10015 } else if (Op.getOpcode() == ISD::SUB) {
10016 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
10017 Offset += -C->getZExtValue();
10018 Op = Op.getOperand(0);
10023 // Otherwise, this isn't something we can handle, reject it.
10027 GlobalValue *GV = GA->getGlobal();
10028 // If we require an extra load to get this address, as in PIC mode, we
10029 // can't accept it.
10030 if (isGlobalStubReference(Subtarget->ClassifyGlobalReference(GV,
10031 getTargetMachine())))
10035 Op = LowerGlobalAddress(GV, Op.getDebugLoc(), Offset, DAG);
10037 Op = DAG.getTargetGlobalAddress(GV, GA->getValueType(0), Offset);
10043 if (Result.getNode()) {
10044 Ops.push_back(Result);
10047 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, hasMemory,
10051 std::vector<unsigned> X86TargetLowering::
10052 getRegClassForInlineAsmConstraint(const std::string &Constraint,
10054 if (Constraint.size() == 1) {
10055 // FIXME: not handling fp-stack yet!
10056 switch (Constraint[0]) { // GCC X86 Constraint Letters
10057 default: break; // Unknown constraint letter
10058 case 'q': // GENERAL_REGS in 64-bit mode, Q_REGS in 32-bit mode.
10059 if (Subtarget->is64Bit()) {
10060 if (VT == MVT::i32)
10061 return make_vector<unsigned>(X86::EAX, X86::EDX, X86::ECX, X86::EBX,
10062 X86::ESI, X86::EDI, X86::R8D, X86::R9D,
10063 X86::R10D,X86::R11D,X86::R12D,
10064 X86::R13D,X86::R14D,X86::R15D,
10065 X86::EBP, X86::ESP, 0);
10066 else if (VT == MVT::i16)
10067 return make_vector<unsigned>(X86::AX, X86::DX, X86::CX, X86::BX,
10068 X86::SI, X86::DI, X86::R8W,X86::R9W,
10069 X86::R10W,X86::R11W,X86::R12W,
10070 X86::R13W,X86::R14W,X86::R15W,
10071 X86::BP, X86::SP, 0);
10072 else if (VT == MVT::i8)
10073 return make_vector<unsigned>(X86::AL, X86::DL, X86::CL, X86::BL,
10074 X86::SIL, X86::DIL, X86::R8B,X86::R9B,
10075 X86::R10B,X86::R11B,X86::R12B,
10076 X86::R13B,X86::R14B,X86::R15B,
10077 X86::BPL, X86::SPL, 0);
10079 else if (VT == MVT::i64)
10080 return make_vector<unsigned>(X86::RAX, X86::RDX, X86::RCX, X86::RBX,
10081 X86::RSI, X86::RDI, X86::R8, X86::R9,
10082 X86::R10, X86::R11, X86::R12,
10083 X86::R13, X86::R14, X86::R15,
10084 X86::RBP, X86::RSP, 0);
10088 // 32-bit fallthrough
10089 case 'Q': // Q_REGS
10090 if (VT == MVT::i32)
10091 return make_vector<unsigned>(X86::EAX, X86::EDX, X86::ECX, X86::EBX, 0);
10092 else if (VT == MVT::i16)
10093 return make_vector<unsigned>(X86::AX, X86::DX, X86::CX, X86::BX, 0);
10094 else if (VT == MVT::i8)
10095 return make_vector<unsigned>(X86::AL, X86::DL, X86::CL, X86::BL, 0);
10096 else if (VT == MVT::i64)
10097 return make_vector<unsigned>(X86::RAX, X86::RDX, X86::RCX, X86::RBX, 0);
10102 return std::vector<unsigned>();
10105 std::pair<unsigned, const TargetRegisterClass*>
10106 X86TargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
10108 // First, see if this is a constraint that directly corresponds to an LLVM
10110 if (Constraint.size() == 1) {
10111 // GCC Constraint Letters
10112 switch (Constraint[0]) {
10114 case 'r': // GENERAL_REGS
10115 case 'l': // INDEX_REGS
10117 return std::make_pair(0U, X86::GR8RegisterClass);
10118 if (VT == MVT::i16)
10119 return std::make_pair(0U, X86::GR16RegisterClass);
10120 if (VT == MVT::i32 || !Subtarget->is64Bit())
10121 return std::make_pair(0U, X86::GR32RegisterClass);
10122 return std::make_pair(0U, X86::GR64RegisterClass);
10123 case 'R': // LEGACY_REGS
10125 return std::make_pair(0U, X86::GR8_NOREXRegisterClass);
10126 if (VT == MVT::i16)
10127 return std::make_pair(0U, X86::GR16_NOREXRegisterClass);
10128 if (VT == MVT::i32 || !Subtarget->is64Bit())
10129 return std::make_pair(0U, X86::GR32_NOREXRegisterClass);
10130 return std::make_pair(0U, X86::GR64_NOREXRegisterClass);
10131 case 'f': // FP Stack registers.
10132 // If SSE is enabled for this VT, use f80 to ensure the isel moves the
10133 // value to the correct fpstack register class.
10134 if (VT == MVT::f32 && !isScalarFPTypeInSSEReg(VT))
10135 return std::make_pair(0U, X86::RFP32RegisterClass);
10136 if (VT == MVT::f64 && !isScalarFPTypeInSSEReg(VT))
10137 return std::make_pair(0U, X86::RFP64RegisterClass);
10138 return std::make_pair(0U, X86::RFP80RegisterClass);
10139 case 'y': // MMX_REGS if MMX allowed.
10140 if (!Subtarget->hasMMX()) break;
10141 return std::make_pair(0U, X86::VR64RegisterClass);
10142 case 'Y': // SSE_REGS if SSE2 allowed
10143 if (!Subtarget->hasSSE2()) break;
10145 case 'x': // SSE_REGS if SSE1 allowed
10146 if (!Subtarget->hasSSE1()) break;
10148 switch (VT.getSimpleVT().SimpleTy) {
10150 // Scalar SSE types.
10153 return std::make_pair(0U, X86::FR32RegisterClass);
10156 return std::make_pair(0U, X86::FR64RegisterClass);
10164 return std::make_pair(0U, X86::VR128RegisterClass);
10170 // Use the default implementation in TargetLowering to convert the register
10171 // constraint into a member of a register class.
10172 std::pair<unsigned, const TargetRegisterClass*> Res;
10173 Res = TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
10175 // Not found as a standard register?
10176 if (Res.second == 0) {
10177 // Map st(0) -> st(7) -> ST0
10178 if (Constraint.size() == 7 && Constraint[0] == '{' &&
10179 tolower(Constraint[1]) == 's' &&
10180 tolower(Constraint[2]) == 't' &&
10181 Constraint[3] == '(' &&
10182 (Constraint[4] >= '0' && Constraint[4] <= '7') &&
10183 Constraint[5] == ')' &&
10184 Constraint[6] == '}') {
10186 Res.first = X86::ST0+Constraint[4]-'0';
10187 Res.second = X86::RFP80RegisterClass;
10191 // GCC allows "st(0)" to be called just plain "st".
10192 if (StringRef("{st}").equals_lower(Constraint)) {
10193 Res.first = X86::ST0;
10194 Res.second = X86::RFP80RegisterClass;
10199 if (StringRef("{flags}").equals_lower(Constraint)) {
10200 Res.first = X86::EFLAGS;
10201 Res.second = X86::CCRRegisterClass;
10205 // 'A' means EAX + EDX.
10206 if (Constraint == "A") {
10207 Res.first = X86::EAX;
10208 Res.second = X86::GR32_ADRegisterClass;
10214 // Otherwise, check to see if this is a register class of the wrong value
10215 // type. For example, we want to map "{ax},i32" -> {eax}, we don't want it to
10216 // turn into {ax},{dx}.
10217 if (Res.second->hasType(VT))
10218 return Res; // Correct type already, nothing to do.
10220 // All of the single-register GCC register classes map their values onto
10221 // 16-bit register pieces "ax","dx","cx","bx","si","di","bp","sp". If we
10222 // really want an 8-bit or 32-bit register, map to the appropriate register
10223 // class and return the appropriate register.
10224 if (Res.second == X86::GR16RegisterClass) {
10225 if (VT == MVT::i8) {
10226 unsigned DestReg = 0;
10227 switch (Res.first) {
10229 case X86::AX: DestReg = X86::AL; break;
10230 case X86::DX: DestReg = X86::DL; break;
10231 case X86::CX: DestReg = X86::CL; break;
10232 case X86::BX: DestReg = X86::BL; break;
10235 Res.first = DestReg;
10236 Res.second = X86::GR8RegisterClass;
10238 } else if (VT == MVT::i32) {
10239 unsigned DestReg = 0;
10240 switch (Res.first) {
10242 case X86::AX: DestReg = X86::EAX; break;
10243 case X86::DX: DestReg = X86::EDX; break;
10244 case X86::CX: DestReg = X86::ECX; break;
10245 case X86::BX: DestReg = X86::EBX; break;
10246 case X86::SI: DestReg = X86::ESI; break;
10247 case X86::DI: DestReg = X86::EDI; break;
10248 case X86::BP: DestReg = X86::EBP; break;
10249 case X86::SP: DestReg = X86::ESP; break;
10252 Res.first = DestReg;
10253 Res.second = X86::GR32RegisterClass;
10255 } else if (VT == MVT::i64) {
10256 unsigned DestReg = 0;
10257 switch (Res.first) {
10259 case X86::AX: DestReg = X86::RAX; break;
10260 case X86::DX: DestReg = X86::RDX; break;
10261 case X86::CX: DestReg = X86::RCX; break;
10262 case X86::BX: DestReg = X86::RBX; break;
10263 case X86::SI: DestReg = X86::RSI; break;
10264 case X86::DI: DestReg = X86::RDI; break;
10265 case X86::BP: DestReg = X86::RBP; break;
10266 case X86::SP: DestReg = X86::RSP; break;
10269 Res.first = DestReg;
10270 Res.second = X86::GR64RegisterClass;
10273 } else if (Res.second == X86::FR32RegisterClass ||
10274 Res.second == X86::FR64RegisterClass ||
10275 Res.second == X86::VR128RegisterClass) {
10276 // Handle references to XMM physical registers that got mapped into the
10277 // wrong class. This can happen with constraints like {xmm0} where the
10278 // target independent register mapper will just pick the first match it can
10279 // find, ignoring the required type.
10280 if (VT == MVT::f32)
10281 Res.second = X86::FR32RegisterClass;
10282 else if (VT == MVT::f64)
10283 Res.second = X86::FR64RegisterClass;
10284 else if (X86::VR128RegisterClass->hasType(VT))
10285 Res.second = X86::VR128RegisterClass;