1 //===-- X86ISelLowering.cpp - X86 DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that X86 uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "x86-isel"
16 #include "X86ISelLowering.h"
17 #include "Utils/X86ShuffleDecode.h"
19 #include "X86CallingConv.h"
20 #include "X86InstrBuilder.h"
21 #include "X86TargetMachine.h"
22 #include "X86TargetObjectFile.h"
23 #include "llvm/ADT/SmallSet.h"
24 #include "llvm/ADT/Statistic.h"
25 #include "llvm/ADT/StringExtras.h"
26 #include "llvm/ADT/VariadicFunction.h"
27 #include "llvm/CodeGen/IntrinsicLowering.h"
28 #include "llvm/CodeGen/MachineFrameInfo.h"
29 #include "llvm/CodeGen/MachineFunction.h"
30 #include "llvm/CodeGen/MachineInstrBuilder.h"
31 #include "llvm/CodeGen/MachineJumpTableInfo.h"
32 #include "llvm/CodeGen/MachineModuleInfo.h"
33 #include "llvm/CodeGen/MachineRegisterInfo.h"
34 #include "llvm/IR/CallingConv.h"
35 #include "llvm/IR/Constants.h"
36 #include "llvm/IR/DerivedTypes.h"
37 #include "llvm/IR/Function.h"
38 #include "llvm/IR/GlobalAlias.h"
39 #include "llvm/IR/GlobalVariable.h"
40 #include "llvm/IR/Instructions.h"
41 #include "llvm/IR/Intrinsics.h"
42 #include "llvm/IR/LLVMContext.h"
43 #include "llvm/MC/MCAsmInfo.h"
44 #include "llvm/MC/MCContext.h"
45 #include "llvm/MC/MCExpr.h"
46 #include "llvm/MC/MCSymbol.h"
47 #include "llvm/Support/CallSite.h"
48 #include "llvm/Support/Debug.h"
49 #include "llvm/Support/ErrorHandling.h"
50 #include "llvm/Support/MathExtras.h"
51 #include "llvm/Target/TargetOptions.h"
56 STATISTIC(NumTailCalls, "Number of tail calls");
58 // Forward declarations.
59 static SDValue getMOVL(SelectionDAG &DAG, SDLoc dl, EVT VT, SDValue V1,
62 static SDValue ExtractSubVector(SDValue Vec, unsigned IdxVal,
63 SelectionDAG &DAG, SDLoc dl,
64 unsigned vectorWidth) {
65 assert((vectorWidth == 128 || vectorWidth == 256) &&
66 "Unsupported vector width");
67 EVT VT = Vec.getValueType();
68 EVT ElVT = VT.getVectorElementType();
69 unsigned Factor = VT.getSizeInBits()/vectorWidth;
70 EVT ResultVT = EVT::getVectorVT(*DAG.getContext(), ElVT,
71 VT.getVectorNumElements()/Factor);
73 // Extract from UNDEF is UNDEF.
74 if (Vec.getOpcode() == ISD::UNDEF)
75 return DAG.getUNDEF(ResultVT);
77 // Extract the relevant vectorWidth bits. Generate an EXTRACT_SUBVECTOR
78 unsigned ElemsPerChunk = vectorWidth / ElVT.getSizeInBits();
80 // This is the index of the first element of the vectorWidth-bit chunk
82 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits()) / vectorWidth)
85 // If the input is a buildvector just emit a smaller one.
86 if (Vec.getOpcode() == ISD::BUILD_VECTOR)
87 return DAG.getNode(ISD::BUILD_VECTOR, dl, ResultVT,
88 Vec->op_begin()+NormalizedIdxVal, ElemsPerChunk);
90 SDValue VecIdx = DAG.getIntPtrConstant(NormalizedIdxVal);
91 SDValue Result = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, ResultVT, Vec,
97 /// Generate a DAG to grab 128-bits from a vector > 128 bits. This
98 /// sets things up to match to an AVX VEXTRACTF128 / VEXTRACTI128
99 /// or AVX-512 VEXTRACTF32x4 / VEXTRACTI32x4
100 /// instructions or a simple subregister reference. Idx is an index in the
101 /// 128 bits we want. It need not be aligned to a 128-bit bounday. That makes
102 /// lowering EXTRACT_VECTOR_ELT operations easier.
103 static SDValue Extract128BitVector(SDValue Vec, unsigned IdxVal,
104 SelectionDAG &DAG, SDLoc dl) {
105 assert((Vec.getValueType().is256BitVector() ||
106 Vec.getValueType().is512BitVector()) && "Unexpected vector size!");
107 return ExtractSubVector(Vec, IdxVal, DAG, dl, 128);
110 /// Generate a DAG to grab 256-bits from a 512-bit vector.
111 static SDValue Extract256BitVector(SDValue Vec, unsigned IdxVal,
112 SelectionDAG &DAG, SDLoc dl) {
113 assert(Vec.getValueType().is512BitVector() && "Unexpected vector size!");
114 return ExtractSubVector(Vec, IdxVal, DAG, dl, 256);
117 static SDValue InsertSubVector(SDValue Result, SDValue Vec,
118 unsigned IdxVal, SelectionDAG &DAG,
119 SDLoc dl, unsigned vectorWidth) {
120 assert((vectorWidth == 128 || vectorWidth == 256) &&
121 "Unsupported vector width");
122 // Inserting UNDEF is Result
123 if (Vec.getOpcode() == ISD::UNDEF)
125 EVT VT = Vec.getValueType();
126 EVT ElVT = VT.getVectorElementType();
127 EVT ResultVT = Result.getValueType();
129 // Insert the relevant vectorWidth bits.
130 unsigned ElemsPerChunk = vectorWidth/ElVT.getSizeInBits();
132 // This is the index of the first element of the vectorWidth-bit chunk
134 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits())/vectorWidth)
137 SDValue VecIdx = DAG.getIntPtrConstant(NormalizedIdxVal);
138 return DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResultVT, Result, Vec,
141 /// Generate a DAG to put 128-bits into a vector > 128 bits. This
142 /// sets things up to match to an AVX VINSERTF128/VINSERTI128 or
143 /// AVX-512 VINSERTF32x4/VINSERTI32x4 instructions or a
144 /// simple superregister reference. Idx is an index in the 128 bits
145 /// we want. It need not be aligned to a 128-bit bounday. That makes
146 /// lowering INSERT_VECTOR_ELT operations easier.
147 static SDValue Insert128BitVector(SDValue Result, SDValue Vec,
148 unsigned IdxVal, SelectionDAG &DAG,
150 assert(Vec.getValueType().is128BitVector() && "Unexpected vector size!");
151 return InsertSubVector(Result, Vec, IdxVal, DAG, dl, 128);
154 static SDValue Insert256BitVector(SDValue Result, SDValue Vec,
155 unsigned IdxVal, SelectionDAG &DAG,
157 assert(Vec.getValueType().is256BitVector() && "Unexpected vector size!");
158 return InsertSubVector(Result, Vec, IdxVal, DAG, dl, 256);
161 /// Concat two 128-bit vectors into a 256 bit vector using VINSERTF128
162 /// instructions. This is used because creating CONCAT_VECTOR nodes of
163 /// BUILD_VECTORS returns a larger BUILD_VECTOR while we're trying to lower
164 /// large BUILD_VECTORS.
165 static SDValue Concat128BitVectors(SDValue V1, SDValue V2, EVT VT,
166 unsigned NumElems, SelectionDAG &DAG,
168 SDValue V = Insert128BitVector(DAG.getUNDEF(VT), V1, 0, DAG, dl);
169 return Insert128BitVector(V, V2, NumElems/2, DAG, dl);
172 static SDValue Concat256BitVectors(SDValue V1, SDValue V2, EVT VT,
173 unsigned NumElems, SelectionDAG &DAG,
175 SDValue V = Insert256BitVector(DAG.getUNDEF(VT), V1, 0, DAG, dl);
176 return Insert256BitVector(V, V2, NumElems/2, DAG, dl);
179 static TargetLoweringObjectFile *createTLOF(X86TargetMachine &TM) {
180 const X86Subtarget *Subtarget = &TM.getSubtarget<X86Subtarget>();
181 bool is64Bit = Subtarget->is64Bit();
183 if (Subtarget->isTargetEnvMacho()) {
185 return new X86_64MachoTargetObjectFile();
186 return new TargetLoweringObjectFileMachO();
189 if (Subtarget->isTargetLinux())
190 return new X86LinuxTargetObjectFile();
191 if (Subtarget->isTargetELF())
192 return new TargetLoweringObjectFileELF();
193 if (Subtarget->isTargetCOFF() && !Subtarget->isTargetEnvMacho())
194 return new TargetLoweringObjectFileCOFF();
195 llvm_unreachable("unknown subtarget type");
198 X86TargetLowering::X86TargetLowering(X86TargetMachine &TM)
199 : TargetLowering(TM, createTLOF(TM)) {
200 Subtarget = &TM.getSubtarget<X86Subtarget>();
201 X86ScalarSSEf64 = Subtarget->hasSSE2();
202 X86ScalarSSEf32 = Subtarget->hasSSE1();
203 TD = getDataLayout();
205 resetOperationActions();
208 void X86TargetLowering::resetOperationActions() {
209 const TargetMachine &TM = getTargetMachine();
210 static bool FirstTimeThrough = true;
212 // If none of the target options have changed, then we don't need to reset the
213 // operation actions.
214 if (!FirstTimeThrough && TO == TM.Options) return;
216 if (!FirstTimeThrough) {
217 // Reinitialize the actions.
219 FirstTimeThrough = false;
224 // Set up the TargetLowering object.
225 static const MVT IntVTs[] = { MVT::i8, MVT::i16, MVT::i32, MVT::i64 };
227 // X86 is weird, it always uses i8 for shift amounts and setcc results.
228 setBooleanContents(ZeroOrOneBooleanContent);
229 // X86-SSE is even stranger. It uses -1 or 0 for vector masks.
230 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
232 // For 64-bit since we have so many registers use the ILP scheduler, for
233 // 32-bit code use the register pressure specific scheduling.
234 // For Atom, always use ILP scheduling.
235 if (Subtarget->isAtom())
236 setSchedulingPreference(Sched::ILP);
237 else if (Subtarget->is64Bit())
238 setSchedulingPreference(Sched::ILP);
240 setSchedulingPreference(Sched::RegPressure);
241 const X86RegisterInfo *RegInfo =
242 static_cast<const X86RegisterInfo*>(TM.getRegisterInfo());
243 setStackPointerRegisterToSaveRestore(RegInfo->getStackRegister());
245 // Bypass expensive divides on Atom when compiling with O2
246 if (Subtarget->hasSlowDivide() && TM.getOptLevel() >= CodeGenOpt::Default) {
247 addBypassSlowDiv(32, 8);
248 if (Subtarget->is64Bit())
249 addBypassSlowDiv(64, 16);
252 if (Subtarget->isTargetWindows() && !Subtarget->isTargetCygMing()) {
253 // Setup Windows compiler runtime calls.
254 setLibcallName(RTLIB::SDIV_I64, "_alldiv");
255 setLibcallName(RTLIB::UDIV_I64, "_aulldiv");
256 setLibcallName(RTLIB::SREM_I64, "_allrem");
257 setLibcallName(RTLIB::UREM_I64, "_aullrem");
258 setLibcallName(RTLIB::MUL_I64, "_allmul");
259 setLibcallCallingConv(RTLIB::SDIV_I64, CallingConv::X86_StdCall);
260 setLibcallCallingConv(RTLIB::UDIV_I64, CallingConv::X86_StdCall);
261 setLibcallCallingConv(RTLIB::SREM_I64, CallingConv::X86_StdCall);
262 setLibcallCallingConv(RTLIB::UREM_I64, CallingConv::X86_StdCall);
263 setLibcallCallingConv(RTLIB::MUL_I64, CallingConv::X86_StdCall);
265 // The _ftol2 runtime function has an unusual calling conv, which
266 // is modeled by a special pseudo-instruction.
267 setLibcallName(RTLIB::FPTOUINT_F64_I64, 0);
268 setLibcallName(RTLIB::FPTOUINT_F32_I64, 0);
269 setLibcallName(RTLIB::FPTOUINT_F64_I32, 0);
270 setLibcallName(RTLIB::FPTOUINT_F32_I32, 0);
273 if (Subtarget->isTargetDarwin()) {
274 // Darwin should use _setjmp/_longjmp instead of setjmp/longjmp.
275 setUseUnderscoreSetJmp(false);
276 setUseUnderscoreLongJmp(false);
277 } else if (Subtarget->isTargetMingw()) {
278 // MS runtime is weird: it exports _setjmp, but longjmp!
279 setUseUnderscoreSetJmp(true);
280 setUseUnderscoreLongJmp(false);
282 setUseUnderscoreSetJmp(true);
283 setUseUnderscoreLongJmp(true);
286 // Set up the register classes.
287 addRegisterClass(MVT::i8, &X86::GR8RegClass);
288 addRegisterClass(MVT::i16, &X86::GR16RegClass);
289 addRegisterClass(MVT::i32, &X86::GR32RegClass);
290 if (Subtarget->is64Bit())
291 addRegisterClass(MVT::i64, &X86::GR64RegClass);
293 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
295 // We don't accept any truncstore of integer registers.
296 setTruncStoreAction(MVT::i64, MVT::i32, Expand);
297 setTruncStoreAction(MVT::i64, MVT::i16, Expand);
298 setTruncStoreAction(MVT::i64, MVT::i8 , Expand);
299 setTruncStoreAction(MVT::i32, MVT::i16, Expand);
300 setTruncStoreAction(MVT::i32, MVT::i8 , Expand);
301 setTruncStoreAction(MVT::i16, MVT::i8, Expand);
303 // SETOEQ and SETUNE require checking two conditions.
304 setCondCodeAction(ISD::SETOEQ, MVT::f32, Expand);
305 setCondCodeAction(ISD::SETOEQ, MVT::f64, Expand);
306 setCondCodeAction(ISD::SETOEQ, MVT::f80, Expand);
307 setCondCodeAction(ISD::SETUNE, MVT::f32, Expand);
308 setCondCodeAction(ISD::SETUNE, MVT::f64, Expand);
309 setCondCodeAction(ISD::SETUNE, MVT::f80, Expand);
311 // Promote all UINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have this
313 setOperationAction(ISD::UINT_TO_FP , MVT::i1 , Promote);
314 setOperationAction(ISD::UINT_TO_FP , MVT::i8 , Promote);
315 setOperationAction(ISD::UINT_TO_FP , MVT::i16 , Promote);
317 if (Subtarget->is64Bit()) {
318 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote);
319 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
320 } else if (!TM.Options.UseSoftFloat) {
321 // We have an algorithm for SSE2->double, and we turn this into a
322 // 64-bit FILD followed by conditional FADD for other targets.
323 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
324 // We have an algorithm for SSE2, and we turn this into a 64-bit
325 // FILD for other targets.
326 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Custom);
329 // Promote i1/i8 SINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have
331 setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote);
332 setOperationAction(ISD::SINT_TO_FP , MVT::i8 , Promote);
334 if (!TM.Options.UseSoftFloat) {
335 // SSE has no i16 to fp conversion, only i32
336 if (X86ScalarSSEf32) {
337 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
338 // f32 and f64 cases are Legal, f80 case is not
339 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
341 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Custom);
342 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
345 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
346 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Promote);
349 // In 32-bit mode these are custom lowered. In 64-bit mode F32 and F64
350 // are Legal, f80 is custom lowered.
351 setOperationAction(ISD::FP_TO_SINT , MVT::i64 , Custom);
352 setOperationAction(ISD::SINT_TO_FP , MVT::i64 , Custom);
354 // Promote i1/i8 FP_TO_SINT to larger FP_TO_SINTS's, as X86 doesn't have
356 setOperationAction(ISD::FP_TO_SINT , MVT::i1 , Promote);
357 setOperationAction(ISD::FP_TO_SINT , MVT::i8 , Promote);
359 if (X86ScalarSSEf32) {
360 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Promote);
361 // f32 and f64 cases are Legal, f80 case is not
362 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
364 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Custom);
365 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
368 // Handle FP_TO_UINT by promoting the destination to a larger signed
370 setOperationAction(ISD::FP_TO_UINT , MVT::i1 , Promote);
371 setOperationAction(ISD::FP_TO_UINT , MVT::i8 , Promote);
372 setOperationAction(ISD::FP_TO_UINT , MVT::i16 , Promote);
374 if (Subtarget->is64Bit()) {
375 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Expand);
376 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote);
377 } else if (!TM.Options.UseSoftFloat) {
378 // Since AVX is a superset of SSE3, only check for SSE here.
379 if (Subtarget->hasSSE1() && !Subtarget->hasSSE3())
380 // Expand FP_TO_UINT into a select.
381 // FIXME: We would like to use a Custom expander here eventually to do
382 // the optimal thing for SSE vs. the default expansion in the legalizer.
383 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Expand);
385 // With SSE3 we can use fisttpll to convert to a signed i64; without
386 // SSE, we're stuck with a fistpll.
387 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Custom);
390 if (isTargetFTOL()) {
391 // Use the _ftol2 runtime function, which has a pseudo-instruction
392 // to handle its weird calling convention.
393 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Custom);
396 // TODO: when we have SSE, these could be more efficient, by using movd/movq.
397 if (!X86ScalarSSEf64) {
398 setOperationAction(ISD::BITCAST , MVT::f32 , Expand);
399 setOperationAction(ISD::BITCAST , MVT::i32 , Expand);
400 if (Subtarget->is64Bit()) {
401 setOperationAction(ISD::BITCAST , MVT::f64 , Expand);
402 // Without SSE, i64->f64 goes through memory.
403 setOperationAction(ISD::BITCAST , MVT::i64 , Expand);
407 // Scalar integer divide and remainder are lowered to use operations that
408 // produce two results, to match the available instructions. This exposes
409 // the two-result form to trivial CSE, which is able to combine x/y and x%y
410 // into a single instruction.
412 // Scalar integer multiply-high is also lowered to use two-result
413 // operations, to match the available instructions. However, plain multiply
414 // (low) operations are left as Legal, as there are single-result
415 // instructions for this in x86. Using the two-result multiply instructions
416 // when both high and low results are needed must be arranged by dagcombine.
417 for (unsigned i = 0; i != array_lengthof(IntVTs); ++i) {
419 setOperationAction(ISD::MULHS, VT, Expand);
420 setOperationAction(ISD::MULHU, VT, Expand);
421 setOperationAction(ISD::SDIV, VT, Expand);
422 setOperationAction(ISD::UDIV, VT, Expand);
423 setOperationAction(ISD::SREM, VT, Expand);
424 setOperationAction(ISD::UREM, VT, Expand);
426 // Add/Sub overflow ops with MVT::Glues are lowered to EFLAGS dependences.
427 setOperationAction(ISD::ADDC, VT, Custom);
428 setOperationAction(ISD::ADDE, VT, Custom);
429 setOperationAction(ISD::SUBC, VT, Custom);
430 setOperationAction(ISD::SUBE, VT, Custom);
433 setOperationAction(ISD::BR_JT , MVT::Other, Expand);
434 setOperationAction(ISD::BRCOND , MVT::Other, Custom);
435 setOperationAction(ISD::BR_CC , MVT::f32, Expand);
436 setOperationAction(ISD::BR_CC , MVT::f64, Expand);
437 setOperationAction(ISD::BR_CC , MVT::f80, Expand);
438 setOperationAction(ISD::BR_CC , MVT::i8, Expand);
439 setOperationAction(ISD::BR_CC , MVT::i16, Expand);
440 setOperationAction(ISD::BR_CC , MVT::i32, Expand);
441 setOperationAction(ISD::BR_CC , MVT::i64, Expand);
442 setOperationAction(ISD::SELECT_CC , MVT::Other, Expand);
443 if (Subtarget->is64Bit())
444 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal);
445 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Legal);
446 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Legal);
447 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
448 setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand);
449 setOperationAction(ISD::FREM , MVT::f32 , Expand);
450 setOperationAction(ISD::FREM , MVT::f64 , Expand);
451 setOperationAction(ISD::FREM , MVT::f80 , Expand);
452 setOperationAction(ISD::FLT_ROUNDS_ , MVT::i32 , Custom);
454 // Promote the i8 variants and force them on up to i32 which has a shorter
456 setOperationAction(ISD::CTTZ , MVT::i8 , Promote);
457 AddPromotedToType (ISD::CTTZ , MVT::i8 , MVT::i32);
458 setOperationAction(ISD::CTTZ_ZERO_UNDEF , MVT::i8 , Promote);
459 AddPromotedToType (ISD::CTTZ_ZERO_UNDEF , MVT::i8 , MVT::i32);
460 if (Subtarget->hasBMI()) {
461 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i16 , Expand);
462 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32 , Expand);
463 if (Subtarget->is64Bit())
464 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand);
466 setOperationAction(ISD::CTTZ , MVT::i16 , Custom);
467 setOperationAction(ISD::CTTZ , MVT::i32 , Custom);
468 if (Subtarget->is64Bit())
469 setOperationAction(ISD::CTTZ , MVT::i64 , Custom);
472 if (Subtarget->hasLZCNT()) {
473 // When promoting the i8 variants, force them to i32 for a shorter
475 setOperationAction(ISD::CTLZ , MVT::i8 , Promote);
476 AddPromotedToType (ISD::CTLZ , MVT::i8 , MVT::i32);
477 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Promote);
478 AddPromotedToType (ISD::CTLZ_ZERO_UNDEF, MVT::i8 , MVT::i32);
479 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Expand);
480 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Expand);
481 if (Subtarget->is64Bit())
482 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Expand);
484 setOperationAction(ISD::CTLZ , MVT::i8 , Custom);
485 setOperationAction(ISD::CTLZ , MVT::i16 , Custom);
486 setOperationAction(ISD::CTLZ , MVT::i32 , Custom);
487 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Custom);
488 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Custom);
489 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Custom);
490 if (Subtarget->is64Bit()) {
491 setOperationAction(ISD::CTLZ , MVT::i64 , Custom);
492 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Custom);
496 if (Subtarget->hasPOPCNT()) {
497 setOperationAction(ISD::CTPOP , MVT::i8 , Promote);
499 setOperationAction(ISD::CTPOP , MVT::i8 , Expand);
500 setOperationAction(ISD::CTPOP , MVT::i16 , Expand);
501 setOperationAction(ISD::CTPOP , MVT::i32 , Expand);
502 if (Subtarget->is64Bit())
503 setOperationAction(ISD::CTPOP , MVT::i64 , Expand);
506 setOperationAction(ISD::READCYCLECOUNTER , MVT::i64 , Custom);
507 setOperationAction(ISD::BSWAP , MVT::i16 , Expand);
509 // These should be promoted to a larger select which is supported.
510 setOperationAction(ISD::SELECT , MVT::i1 , Promote);
511 // X86 wants to expand cmov itself.
512 setOperationAction(ISD::SELECT , MVT::i8 , Custom);
513 setOperationAction(ISD::SELECT , MVT::i16 , Custom);
514 setOperationAction(ISD::SELECT , MVT::i32 , Custom);
515 setOperationAction(ISD::SELECT , MVT::f32 , Custom);
516 setOperationAction(ISD::SELECT , MVT::f64 , Custom);
517 setOperationAction(ISD::SELECT , MVT::f80 , Custom);
518 setOperationAction(ISD::SETCC , MVT::i8 , Custom);
519 setOperationAction(ISD::SETCC , MVT::i16 , Custom);
520 setOperationAction(ISD::SETCC , MVT::i32 , Custom);
521 setOperationAction(ISD::SETCC , MVT::f32 , Custom);
522 setOperationAction(ISD::SETCC , MVT::f64 , Custom);
523 setOperationAction(ISD::SETCC , MVT::f80 , Custom);
524 if (Subtarget->is64Bit()) {
525 setOperationAction(ISD::SELECT , MVT::i64 , Custom);
526 setOperationAction(ISD::SETCC , MVT::i64 , Custom);
528 setOperationAction(ISD::EH_RETURN , MVT::Other, Custom);
529 // NOTE: EH_SJLJ_SETJMP/_LONGJMP supported here is NOT intended to support
530 // SjLj exception handling but a light-weight setjmp/longjmp replacement to
531 // support continuation, user-level threading, and etc.. As a result, no
532 // other SjLj exception interfaces are implemented and please don't build
533 // your own exception handling based on them.
534 // LLVM/Clang supports zero-cost DWARF exception handling.
535 setOperationAction(ISD::EH_SJLJ_SETJMP, MVT::i32, Custom);
536 setOperationAction(ISD::EH_SJLJ_LONGJMP, MVT::Other, Custom);
539 setOperationAction(ISD::ConstantPool , MVT::i32 , Custom);
540 setOperationAction(ISD::JumpTable , MVT::i32 , Custom);
541 setOperationAction(ISD::GlobalAddress , MVT::i32 , Custom);
542 setOperationAction(ISD::GlobalTLSAddress, MVT::i32 , Custom);
543 if (Subtarget->is64Bit())
544 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
545 setOperationAction(ISD::ExternalSymbol , MVT::i32 , Custom);
546 setOperationAction(ISD::BlockAddress , MVT::i32 , Custom);
547 if (Subtarget->is64Bit()) {
548 setOperationAction(ISD::ConstantPool , MVT::i64 , Custom);
549 setOperationAction(ISD::JumpTable , MVT::i64 , Custom);
550 setOperationAction(ISD::GlobalAddress , MVT::i64 , Custom);
551 setOperationAction(ISD::ExternalSymbol, MVT::i64 , Custom);
552 setOperationAction(ISD::BlockAddress , MVT::i64 , Custom);
554 // 64-bit addm sub, shl, sra, srl (iff 32-bit x86)
555 setOperationAction(ISD::SHL_PARTS , MVT::i32 , Custom);
556 setOperationAction(ISD::SRA_PARTS , MVT::i32 , Custom);
557 setOperationAction(ISD::SRL_PARTS , MVT::i32 , Custom);
558 if (Subtarget->is64Bit()) {
559 setOperationAction(ISD::SHL_PARTS , MVT::i64 , Custom);
560 setOperationAction(ISD::SRA_PARTS , MVT::i64 , Custom);
561 setOperationAction(ISD::SRL_PARTS , MVT::i64 , Custom);
564 if (Subtarget->hasSSE1())
565 setOperationAction(ISD::PREFETCH , MVT::Other, Legal);
567 setOperationAction(ISD::ATOMIC_FENCE , MVT::Other, Custom);
569 // Expand certain atomics
570 for (unsigned i = 0; i != array_lengthof(IntVTs); ++i) {
572 setOperationAction(ISD::ATOMIC_CMP_SWAP, VT, Custom);
573 setOperationAction(ISD::ATOMIC_LOAD_SUB, VT, Custom);
574 setOperationAction(ISD::ATOMIC_STORE, VT, Custom);
577 if (!Subtarget->is64Bit()) {
578 setOperationAction(ISD::ATOMIC_LOAD, MVT::i64, Custom);
579 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i64, Custom);
580 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i64, Custom);
581 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i64, Custom);
582 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i64, Custom);
583 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i64, Custom);
584 setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i64, Custom);
585 setOperationAction(ISD::ATOMIC_SWAP, MVT::i64, Custom);
586 setOperationAction(ISD::ATOMIC_LOAD_MAX, MVT::i64, Custom);
587 setOperationAction(ISD::ATOMIC_LOAD_MIN, MVT::i64, Custom);
588 setOperationAction(ISD::ATOMIC_LOAD_UMAX, MVT::i64, Custom);
589 setOperationAction(ISD::ATOMIC_LOAD_UMIN, MVT::i64, Custom);
592 if (Subtarget->hasCmpxchg16b()) {
593 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i128, Custom);
596 // FIXME - use subtarget debug flags
597 if (!Subtarget->isTargetDarwin() &&
598 !Subtarget->isTargetELF() &&
599 !Subtarget->isTargetCygMing()) {
600 setOperationAction(ISD::EH_LABEL, MVT::Other, Expand);
603 if (Subtarget->is64Bit()) {
604 setExceptionPointerRegister(X86::RAX);
605 setExceptionSelectorRegister(X86::RDX);
607 setExceptionPointerRegister(X86::EAX);
608 setExceptionSelectorRegister(X86::EDX);
610 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i32, Custom);
611 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i64, Custom);
613 setOperationAction(ISD::INIT_TRAMPOLINE, MVT::Other, Custom);
614 setOperationAction(ISD::ADJUST_TRAMPOLINE, MVT::Other, Custom);
616 setOperationAction(ISD::TRAP, MVT::Other, Legal);
617 setOperationAction(ISD::DEBUGTRAP, MVT::Other, Legal);
619 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
620 setOperationAction(ISD::VASTART , MVT::Other, Custom);
621 setOperationAction(ISD::VAEND , MVT::Other, Expand);
622 if (Subtarget->is64Bit() && !Subtarget->isTargetWin64()) {
623 // TargetInfo::X86_64ABIBuiltinVaList
624 setOperationAction(ISD::VAARG , MVT::Other, Custom);
625 setOperationAction(ISD::VACOPY , MVT::Other, Custom);
627 // TargetInfo::CharPtrBuiltinVaList
628 setOperationAction(ISD::VAARG , MVT::Other, Expand);
629 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
632 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
633 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
635 if (Subtarget->isOSWindows() && !Subtarget->isTargetEnvMacho())
636 setOperationAction(ISD::DYNAMIC_STACKALLOC, Subtarget->is64Bit() ?
637 MVT::i64 : MVT::i32, Custom);
638 else if (TM.Options.EnableSegmentedStacks)
639 setOperationAction(ISD::DYNAMIC_STACKALLOC, Subtarget->is64Bit() ?
640 MVT::i64 : MVT::i32, Custom);
642 setOperationAction(ISD::DYNAMIC_STACKALLOC, Subtarget->is64Bit() ?
643 MVT::i64 : MVT::i32, Expand);
645 if (!TM.Options.UseSoftFloat && X86ScalarSSEf64) {
646 // f32 and f64 use SSE.
647 // Set up the FP register classes.
648 addRegisterClass(MVT::f32, &X86::FR32RegClass);
649 addRegisterClass(MVT::f64, &X86::FR64RegClass);
651 // Use ANDPD to simulate FABS.
652 setOperationAction(ISD::FABS , MVT::f64, Custom);
653 setOperationAction(ISD::FABS , MVT::f32, Custom);
655 // Use XORP to simulate FNEG.
656 setOperationAction(ISD::FNEG , MVT::f64, Custom);
657 setOperationAction(ISD::FNEG , MVT::f32, Custom);
659 // Use ANDPD and ORPD to simulate FCOPYSIGN.
660 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
661 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
663 // Lower this to FGETSIGNx86 plus an AND.
664 setOperationAction(ISD::FGETSIGN, MVT::i64, Custom);
665 setOperationAction(ISD::FGETSIGN, MVT::i32, Custom);
667 // We don't support sin/cos/fmod
668 setOperationAction(ISD::FSIN , MVT::f64, Expand);
669 setOperationAction(ISD::FCOS , MVT::f64, Expand);
670 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
671 setOperationAction(ISD::FSIN , MVT::f32, Expand);
672 setOperationAction(ISD::FCOS , MVT::f32, Expand);
673 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
675 // Expand FP immediates into loads from the stack, except for the special
677 addLegalFPImmediate(APFloat(+0.0)); // xorpd
678 addLegalFPImmediate(APFloat(+0.0f)); // xorps
679 } else if (!TM.Options.UseSoftFloat && X86ScalarSSEf32) {
680 // Use SSE for f32, x87 for f64.
681 // Set up the FP register classes.
682 addRegisterClass(MVT::f32, &X86::FR32RegClass);
683 addRegisterClass(MVT::f64, &X86::RFP64RegClass);
685 // Use ANDPS to simulate FABS.
686 setOperationAction(ISD::FABS , MVT::f32, Custom);
688 // Use XORP to simulate FNEG.
689 setOperationAction(ISD::FNEG , MVT::f32, Custom);
691 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
693 // Use ANDPS and ORPS to simulate FCOPYSIGN.
694 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
695 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
697 // We don't support sin/cos/fmod
698 setOperationAction(ISD::FSIN , MVT::f32, Expand);
699 setOperationAction(ISD::FCOS , MVT::f32, Expand);
700 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
702 // Special cases we handle for FP constants.
703 addLegalFPImmediate(APFloat(+0.0f)); // xorps
704 addLegalFPImmediate(APFloat(+0.0)); // FLD0
705 addLegalFPImmediate(APFloat(+1.0)); // FLD1
706 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
707 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
709 if (!TM.Options.UnsafeFPMath) {
710 setOperationAction(ISD::FSIN , MVT::f64, Expand);
711 setOperationAction(ISD::FCOS , MVT::f64, Expand);
712 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
714 } else if (!TM.Options.UseSoftFloat) {
715 // f32 and f64 in x87.
716 // Set up the FP register classes.
717 addRegisterClass(MVT::f64, &X86::RFP64RegClass);
718 addRegisterClass(MVT::f32, &X86::RFP32RegClass);
720 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
721 setOperationAction(ISD::UNDEF, MVT::f32, Expand);
722 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
723 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
725 if (!TM.Options.UnsafeFPMath) {
726 setOperationAction(ISD::FSIN , MVT::f64, Expand);
727 setOperationAction(ISD::FSIN , MVT::f32, Expand);
728 setOperationAction(ISD::FCOS , MVT::f64, Expand);
729 setOperationAction(ISD::FCOS , MVT::f32, Expand);
730 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
731 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
733 addLegalFPImmediate(APFloat(+0.0)); // FLD0
734 addLegalFPImmediate(APFloat(+1.0)); // FLD1
735 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
736 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
737 addLegalFPImmediate(APFloat(+0.0f)); // FLD0
738 addLegalFPImmediate(APFloat(+1.0f)); // FLD1
739 addLegalFPImmediate(APFloat(-0.0f)); // FLD0/FCHS
740 addLegalFPImmediate(APFloat(-1.0f)); // FLD1/FCHS
743 // We don't support FMA.
744 setOperationAction(ISD::FMA, MVT::f64, Expand);
745 setOperationAction(ISD::FMA, MVT::f32, Expand);
747 // Long double always uses X87.
748 if (!TM.Options.UseSoftFloat) {
749 addRegisterClass(MVT::f80, &X86::RFP80RegClass);
750 setOperationAction(ISD::UNDEF, MVT::f80, Expand);
751 setOperationAction(ISD::FCOPYSIGN, MVT::f80, Expand);
753 APFloat TmpFlt = APFloat::getZero(APFloat::x87DoubleExtended);
754 addLegalFPImmediate(TmpFlt); // FLD0
756 addLegalFPImmediate(TmpFlt); // FLD0/FCHS
759 APFloat TmpFlt2(+1.0);
760 TmpFlt2.convert(APFloat::x87DoubleExtended, APFloat::rmNearestTiesToEven,
762 addLegalFPImmediate(TmpFlt2); // FLD1
763 TmpFlt2.changeSign();
764 addLegalFPImmediate(TmpFlt2); // FLD1/FCHS
767 if (!TM.Options.UnsafeFPMath) {
768 setOperationAction(ISD::FSIN , MVT::f80, Expand);
769 setOperationAction(ISD::FCOS , MVT::f80, Expand);
770 setOperationAction(ISD::FSINCOS, MVT::f80, Expand);
773 setOperationAction(ISD::FFLOOR, MVT::f80, Expand);
774 setOperationAction(ISD::FCEIL, MVT::f80, Expand);
775 setOperationAction(ISD::FTRUNC, MVT::f80, Expand);
776 setOperationAction(ISD::FRINT, MVT::f80, Expand);
777 setOperationAction(ISD::FNEARBYINT, MVT::f80, Expand);
778 setOperationAction(ISD::FMA, MVT::f80, Expand);
781 // Always use a library call for pow.
782 setOperationAction(ISD::FPOW , MVT::f32 , Expand);
783 setOperationAction(ISD::FPOW , MVT::f64 , Expand);
784 setOperationAction(ISD::FPOW , MVT::f80 , Expand);
786 setOperationAction(ISD::FLOG, MVT::f80, Expand);
787 setOperationAction(ISD::FLOG2, MVT::f80, Expand);
788 setOperationAction(ISD::FLOG10, MVT::f80, Expand);
789 setOperationAction(ISD::FEXP, MVT::f80, Expand);
790 setOperationAction(ISD::FEXP2, MVT::f80, Expand);
792 // First set operation action for all vector types to either promote
793 // (for widening) or expand (for scalarization). Then we will selectively
794 // turn on ones that can be effectively codegen'd.
795 for (int i = MVT::FIRST_VECTOR_VALUETYPE;
796 i <= MVT::LAST_VECTOR_VALUETYPE; ++i) {
797 MVT VT = (MVT::SimpleValueType)i;
798 setOperationAction(ISD::ADD , VT, Expand);
799 setOperationAction(ISD::SUB , VT, Expand);
800 setOperationAction(ISD::FADD, VT, Expand);
801 setOperationAction(ISD::FNEG, VT, Expand);
802 setOperationAction(ISD::FSUB, VT, Expand);
803 setOperationAction(ISD::MUL , VT, Expand);
804 setOperationAction(ISD::FMUL, VT, Expand);
805 setOperationAction(ISD::SDIV, VT, Expand);
806 setOperationAction(ISD::UDIV, VT, Expand);
807 setOperationAction(ISD::FDIV, VT, Expand);
808 setOperationAction(ISD::SREM, VT, Expand);
809 setOperationAction(ISD::UREM, VT, Expand);
810 setOperationAction(ISD::LOAD, VT, Expand);
811 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Expand);
812 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT,Expand);
813 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Expand);
814 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT,Expand);
815 setOperationAction(ISD::INSERT_SUBVECTOR, VT,Expand);
816 setOperationAction(ISD::FABS, VT, Expand);
817 setOperationAction(ISD::FSIN, VT, Expand);
818 setOperationAction(ISD::FSINCOS, VT, Expand);
819 setOperationAction(ISD::FCOS, VT, Expand);
820 setOperationAction(ISD::FSINCOS, VT, Expand);
821 setOperationAction(ISD::FREM, VT, Expand);
822 setOperationAction(ISD::FMA, VT, Expand);
823 setOperationAction(ISD::FPOWI, VT, Expand);
824 setOperationAction(ISD::FSQRT, VT, Expand);
825 setOperationAction(ISD::FCOPYSIGN, VT, Expand);
826 setOperationAction(ISD::FFLOOR, VT, Expand);
827 setOperationAction(ISD::FCEIL, VT, Expand);
828 setOperationAction(ISD::FTRUNC, VT, Expand);
829 setOperationAction(ISD::FRINT, VT, Expand);
830 setOperationAction(ISD::FNEARBYINT, VT, Expand);
831 setOperationAction(ISD::SMUL_LOHI, VT, Expand);
832 setOperationAction(ISD::UMUL_LOHI, VT, Expand);
833 setOperationAction(ISD::SDIVREM, VT, Expand);
834 setOperationAction(ISD::UDIVREM, VT, Expand);
835 setOperationAction(ISD::FPOW, VT, Expand);
836 setOperationAction(ISD::CTPOP, VT, Expand);
837 setOperationAction(ISD::CTTZ, VT, Expand);
838 setOperationAction(ISD::CTTZ_ZERO_UNDEF, VT, Expand);
839 setOperationAction(ISD::CTLZ, VT, Expand);
840 setOperationAction(ISD::CTLZ_ZERO_UNDEF, VT, Expand);
841 setOperationAction(ISD::SHL, VT, Expand);
842 setOperationAction(ISD::SRA, VT, Expand);
843 setOperationAction(ISD::SRL, VT, Expand);
844 setOperationAction(ISD::ROTL, VT, Expand);
845 setOperationAction(ISD::ROTR, VT, Expand);
846 setOperationAction(ISD::BSWAP, VT, Expand);
847 setOperationAction(ISD::SETCC, VT, Expand);
848 setOperationAction(ISD::FLOG, VT, Expand);
849 setOperationAction(ISD::FLOG2, VT, Expand);
850 setOperationAction(ISD::FLOG10, VT, Expand);
851 setOperationAction(ISD::FEXP, VT, Expand);
852 setOperationAction(ISD::FEXP2, VT, Expand);
853 setOperationAction(ISD::FP_TO_UINT, VT, Expand);
854 setOperationAction(ISD::FP_TO_SINT, VT, Expand);
855 setOperationAction(ISD::UINT_TO_FP, VT, Expand);
856 setOperationAction(ISD::SINT_TO_FP, VT, Expand);
857 setOperationAction(ISD::SIGN_EXTEND_INREG, VT,Expand);
858 setOperationAction(ISD::TRUNCATE, VT, Expand);
859 setOperationAction(ISD::SIGN_EXTEND, VT, Expand);
860 setOperationAction(ISD::ZERO_EXTEND, VT, Expand);
861 setOperationAction(ISD::ANY_EXTEND, VT, Expand);
862 setOperationAction(ISD::VSELECT, VT, Expand);
863 for (int InnerVT = MVT::FIRST_VECTOR_VALUETYPE;
864 InnerVT <= MVT::LAST_VECTOR_VALUETYPE; ++InnerVT)
865 setTruncStoreAction(VT,
866 (MVT::SimpleValueType)InnerVT, Expand);
867 setLoadExtAction(ISD::SEXTLOAD, VT, Expand);
868 setLoadExtAction(ISD::ZEXTLOAD, VT, Expand);
869 setLoadExtAction(ISD::EXTLOAD, VT, Expand);
872 // FIXME: In order to prevent SSE instructions being expanded to MMX ones
873 // with -msoft-float, disable use of MMX as well.
874 if (!TM.Options.UseSoftFloat && Subtarget->hasMMX()) {
875 addRegisterClass(MVT::x86mmx, &X86::VR64RegClass);
876 // No operations on x86mmx supported, everything uses intrinsics.
879 // MMX-sized vectors (other than x86mmx) are expected to be expanded
880 // into smaller operations.
881 setOperationAction(ISD::MULHS, MVT::v8i8, Expand);
882 setOperationAction(ISD::MULHS, MVT::v4i16, Expand);
883 setOperationAction(ISD::MULHS, MVT::v2i32, Expand);
884 setOperationAction(ISD::MULHS, MVT::v1i64, Expand);
885 setOperationAction(ISD::AND, MVT::v8i8, Expand);
886 setOperationAction(ISD::AND, MVT::v4i16, Expand);
887 setOperationAction(ISD::AND, MVT::v2i32, Expand);
888 setOperationAction(ISD::AND, MVT::v1i64, Expand);
889 setOperationAction(ISD::OR, MVT::v8i8, Expand);
890 setOperationAction(ISD::OR, MVT::v4i16, Expand);
891 setOperationAction(ISD::OR, MVT::v2i32, Expand);
892 setOperationAction(ISD::OR, MVT::v1i64, Expand);
893 setOperationAction(ISD::XOR, MVT::v8i8, Expand);
894 setOperationAction(ISD::XOR, MVT::v4i16, Expand);
895 setOperationAction(ISD::XOR, MVT::v2i32, Expand);
896 setOperationAction(ISD::XOR, MVT::v1i64, Expand);
897 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i8, Expand);
898 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i16, Expand);
899 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2i32, Expand);
900 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v1i64, Expand);
901 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v1i64, Expand);
902 setOperationAction(ISD::SELECT, MVT::v8i8, Expand);
903 setOperationAction(ISD::SELECT, MVT::v4i16, Expand);
904 setOperationAction(ISD::SELECT, MVT::v2i32, Expand);
905 setOperationAction(ISD::SELECT, MVT::v1i64, Expand);
906 setOperationAction(ISD::BITCAST, MVT::v8i8, Expand);
907 setOperationAction(ISD::BITCAST, MVT::v4i16, Expand);
908 setOperationAction(ISD::BITCAST, MVT::v2i32, Expand);
909 setOperationAction(ISD::BITCAST, MVT::v1i64, Expand);
911 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE1()) {
912 addRegisterClass(MVT::v4f32, &X86::VR128RegClass);
914 setOperationAction(ISD::FADD, MVT::v4f32, Legal);
915 setOperationAction(ISD::FSUB, MVT::v4f32, Legal);
916 setOperationAction(ISD::FMUL, MVT::v4f32, Legal);
917 setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
918 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal);
919 setOperationAction(ISD::FNEG, MVT::v4f32, Custom);
920 setOperationAction(ISD::FABS, MVT::v4f32, Custom);
921 setOperationAction(ISD::LOAD, MVT::v4f32, Legal);
922 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
923 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f32, Custom);
924 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
925 setOperationAction(ISD::SELECT, MVT::v4f32, Custom);
928 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE2()) {
929 addRegisterClass(MVT::v2f64, &X86::VR128RegClass);
931 // FIXME: Unfortunately -soft-float and -no-implicit-float means XMM
932 // registers cannot be used even for integer operations.
933 addRegisterClass(MVT::v16i8, &X86::VR128RegClass);
934 addRegisterClass(MVT::v8i16, &X86::VR128RegClass);
935 addRegisterClass(MVT::v4i32, &X86::VR128RegClass);
936 addRegisterClass(MVT::v2i64, &X86::VR128RegClass);
938 setOperationAction(ISD::ADD, MVT::v16i8, Legal);
939 setOperationAction(ISD::ADD, MVT::v8i16, Legal);
940 setOperationAction(ISD::ADD, MVT::v4i32, Legal);
941 setOperationAction(ISD::ADD, MVT::v2i64, Legal);
942 setOperationAction(ISD::MUL, MVT::v4i32, Custom);
943 setOperationAction(ISD::MUL, MVT::v2i64, Custom);
944 setOperationAction(ISD::SUB, MVT::v16i8, Legal);
945 setOperationAction(ISD::SUB, MVT::v8i16, Legal);
946 setOperationAction(ISD::SUB, MVT::v4i32, Legal);
947 setOperationAction(ISD::SUB, MVT::v2i64, Legal);
948 setOperationAction(ISD::MUL, MVT::v8i16, Legal);
949 setOperationAction(ISD::FADD, MVT::v2f64, Legal);
950 setOperationAction(ISD::FSUB, MVT::v2f64, Legal);
951 setOperationAction(ISD::FMUL, MVT::v2f64, Legal);
952 setOperationAction(ISD::FDIV, MVT::v2f64, Legal);
953 setOperationAction(ISD::FSQRT, MVT::v2f64, Legal);
954 setOperationAction(ISD::FNEG, MVT::v2f64, Custom);
955 setOperationAction(ISD::FABS, MVT::v2f64, Custom);
957 setOperationAction(ISD::SETCC, MVT::v2i64, Custom);
958 setOperationAction(ISD::SETCC, MVT::v16i8, Custom);
959 setOperationAction(ISD::SETCC, MVT::v8i16, Custom);
960 setOperationAction(ISD::SETCC, MVT::v4i32, Custom);
962 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Custom);
963 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Custom);
964 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
965 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
966 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
968 // Custom lower build_vector, vector_shuffle, and extract_vector_elt.
969 for (int i = MVT::v16i8; i != MVT::v2i64; ++i) {
970 MVT VT = (MVT::SimpleValueType)i;
971 // Do not attempt to custom lower non-power-of-2 vectors
972 if (!isPowerOf2_32(VT.getVectorNumElements()))
974 // Do not attempt to custom lower non-128-bit vectors
975 if (!VT.is128BitVector())
977 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
978 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
979 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
982 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f64, Custom);
983 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i64, Custom);
984 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Custom);
985 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Custom);
986 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f64, Custom);
987 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Custom);
989 if (Subtarget->is64Bit()) {
990 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
991 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
994 // Promote v16i8, v8i16, v4i32 load, select, and, or, xor to v2i64.
995 for (int i = MVT::v16i8; i != MVT::v2i64; ++i) {
996 MVT VT = (MVT::SimpleValueType)i;
998 // Do not attempt to promote non-128-bit vectors
999 if (!VT.is128BitVector())
1002 setOperationAction(ISD::AND, VT, Promote);
1003 AddPromotedToType (ISD::AND, VT, MVT::v2i64);
1004 setOperationAction(ISD::OR, VT, Promote);
1005 AddPromotedToType (ISD::OR, VT, MVT::v2i64);
1006 setOperationAction(ISD::XOR, VT, Promote);
1007 AddPromotedToType (ISD::XOR, VT, MVT::v2i64);
1008 setOperationAction(ISD::LOAD, VT, Promote);
1009 AddPromotedToType (ISD::LOAD, VT, MVT::v2i64);
1010 setOperationAction(ISD::SELECT, VT, Promote);
1011 AddPromotedToType (ISD::SELECT, VT, MVT::v2i64);
1014 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
1016 // Custom lower v2i64 and v2f64 selects.
1017 setOperationAction(ISD::LOAD, MVT::v2f64, Legal);
1018 setOperationAction(ISD::LOAD, MVT::v2i64, Legal);
1019 setOperationAction(ISD::SELECT, MVT::v2f64, Custom);
1020 setOperationAction(ISD::SELECT, MVT::v2i64, Custom);
1022 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal);
1023 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal);
1025 setOperationAction(ISD::UINT_TO_FP, MVT::v4i8, Custom);
1026 setOperationAction(ISD::UINT_TO_FP, MVT::v4i16, Custom);
1027 // As there is no 64-bit GPR available, we need build a special custom
1028 // sequence to convert from v2i32 to v2f32.
1029 if (!Subtarget->is64Bit())
1030 setOperationAction(ISD::UINT_TO_FP, MVT::v2f32, Custom);
1032 setOperationAction(ISD::FP_EXTEND, MVT::v2f32, Custom);
1033 setOperationAction(ISD::FP_ROUND, MVT::v2f32, Custom);
1035 setLoadExtAction(ISD::EXTLOAD, MVT::v2f32, Legal);
1038 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE41()) {
1039 setOperationAction(ISD::FFLOOR, MVT::f32, Legal);
1040 setOperationAction(ISD::FCEIL, MVT::f32, Legal);
1041 setOperationAction(ISD::FTRUNC, MVT::f32, Legal);
1042 setOperationAction(ISD::FRINT, MVT::f32, Legal);
1043 setOperationAction(ISD::FNEARBYINT, MVT::f32, Legal);
1044 setOperationAction(ISD::FFLOOR, MVT::f64, Legal);
1045 setOperationAction(ISD::FCEIL, MVT::f64, Legal);
1046 setOperationAction(ISD::FTRUNC, MVT::f64, Legal);
1047 setOperationAction(ISD::FRINT, MVT::f64, Legal);
1048 setOperationAction(ISD::FNEARBYINT, MVT::f64, Legal);
1050 setOperationAction(ISD::FFLOOR, MVT::v4f32, Legal);
1051 setOperationAction(ISD::FCEIL, MVT::v4f32, Legal);
1052 setOperationAction(ISD::FTRUNC, MVT::v4f32, Legal);
1053 setOperationAction(ISD::FRINT, MVT::v4f32, Legal);
1054 setOperationAction(ISD::FNEARBYINT, MVT::v4f32, Legal);
1055 setOperationAction(ISD::FFLOOR, MVT::v2f64, Legal);
1056 setOperationAction(ISD::FCEIL, MVT::v2f64, Legal);
1057 setOperationAction(ISD::FTRUNC, MVT::v2f64, Legal);
1058 setOperationAction(ISD::FRINT, MVT::v2f64, Legal);
1059 setOperationAction(ISD::FNEARBYINT, MVT::v2f64, Legal);
1061 // FIXME: Do we need to handle scalar-to-vector here?
1062 setOperationAction(ISD::MUL, MVT::v4i32, Legal);
1064 setOperationAction(ISD::VSELECT, MVT::v2f64, Legal);
1065 setOperationAction(ISD::VSELECT, MVT::v2i64, Legal);
1066 setOperationAction(ISD::VSELECT, MVT::v16i8, Legal);
1067 setOperationAction(ISD::VSELECT, MVT::v4i32, Legal);
1068 setOperationAction(ISD::VSELECT, MVT::v4f32, Legal);
1070 // i8 and i16 vectors are custom , because the source register and source
1071 // source memory operand types are not the same width. f32 vectors are
1072 // custom since the immediate controlling the insert encodes additional
1074 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i8, Custom);
1075 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
1076 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
1077 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
1079 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i8, Custom);
1080 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i16, Custom);
1081 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i32, Custom);
1082 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
1084 // FIXME: these should be Legal but thats only for the case where
1085 // the index is constant. For now custom expand to deal with that.
1086 if (Subtarget->is64Bit()) {
1087 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
1088 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
1092 if (Subtarget->hasSSE2()) {
1093 setOperationAction(ISD::SRL, MVT::v8i16, Custom);
1094 setOperationAction(ISD::SRL, MVT::v16i8, Custom);
1096 setOperationAction(ISD::SHL, MVT::v8i16, Custom);
1097 setOperationAction(ISD::SHL, MVT::v16i8, Custom);
1099 setOperationAction(ISD::SRA, MVT::v8i16, Custom);
1100 setOperationAction(ISD::SRA, MVT::v16i8, Custom);
1102 // In the customized shift lowering, the legal cases in AVX2 will be
1104 setOperationAction(ISD::SRL, MVT::v2i64, Custom);
1105 setOperationAction(ISD::SRL, MVT::v4i32, Custom);
1107 setOperationAction(ISD::SHL, MVT::v2i64, Custom);
1108 setOperationAction(ISD::SHL, MVT::v4i32, Custom);
1110 setOperationAction(ISD::SRA, MVT::v4i32, Custom);
1112 setOperationAction(ISD::SDIV, MVT::v8i16, Custom);
1113 setOperationAction(ISD::SDIV, MVT::v4i32, Custom);
1116 if (!TM.Options.UseSoftFloat && Subtarget->hasFp256()) {
1117 addRegisterClass(MVT::v32i8, &X86::VR256RegClass);
1118 addRegisterClass(MVT::v16i16, &X86::VR256RegClass);
1119 addRegisterClass(MVT::v8i32, &X86::VR256RegClass);
1120 addRegisterClass(MVT::v8f32, &X86::VR256RegClass);
1121 addRegisterClass(MVT::v4i64, &X86::VR256RegClass);
1122 addRegisterClass(MVT::v4f64, &X86::VR256RegClass);
1124 setOperationAction(ISD::LOAD, MVT::v8f32, Legal);
1125 setOperationAction(ISD::LOAD, MVT::v4f64, Legal);
1126 setOperationAction(ISD::LOAD, MVT::v4i64, Legal);
1128 setOperationAction(ISD::FADD, MVT::v8f32, Legal);
1129 setOperationAction(ISD::FSUB, MVT::v8f32, Legal);
1130 setOperationAction(ISD::FMUL, MVT::v8f32, Legal);
1131 setOperationAction(ISD::FDIV, MVT::v8f32, Legal);
1132 setOperationAction(ISD::FSQRT, MVT::v8f32, Legal);
1133 setOperationAction(ISD::FFLOOR, MVT::v8f32, Legal);
1134 setOperationAction(ISD::FCEIL, MVT::v8f32, Legal);
1135 setOperationAction(ISD::FTRUNC, MVT::v8f32, Legal);
1136 setOperationAction(ISD::FRINT, MVT::v8f32, Legal);
1137 setOperationAction(ISD::FNEARBYINT, MVT::v8f32, Legal);
1138 setOperationAction(ISD::FNEG, MVT::v8f32, Custom);
1139 setOperationAction(ISD::FABS, MVT::v8f32, Custom);
1141 setOperationAction(ISD::FADD, MVT::v4f64, Legal);
1142 setOperationAction(ISD::FSUB, MVT::v4f64, Legal);
1143 setOperationAction(ISD::FMUL, MVT::v4f64, Legal);
1144 setOperationAction(ISD::FDIV, MVT::v4f64, Legal);
1145 setOperationAction(ISD::FSQRT, MVT::v4f64, Legal);
1146 setOperationAction(ISD::FFLOOR, MVT::v4f64, Legal);
1147 setOperationAction(ISD::FCEIL, MVT::v4f64, Legal);
1148 setOperationAction(ISD::FTRUNC, MVT::v4f64, Legal);
1149 setOperationAction(ISD::FRINT, MVT::v4f64, Legal);
1150 setOperationAction(ISD::FNEARBYINT, MVT::v4f64, Legal);
1151 setOperationAction(ISD::FNEG, MVT::v4f64, Custom);
1152 setOperationAction(ISD::FABS, MVT::v4f64, Custom);
1154 setOperationAction(ISD::FP_TO_SINT, MVT::v8i16, Custom);
1156 setOperationAction(ISD::FP_TO_SINT, MVT::v8i32, Legal);
1157 setOperationAction(ISD::SINT_TO_FP, MVT::v8i16, Promote);
1158 setOperationAction(ISD::SINT_TO_FP, MVT::v8i32, Legal);
1159 setOperationAction(ISD::FP_ROUND, MVT::v4f32, Legal);
1161 setOperationAction(ISD::UINT_TO_FP, MVT::v8i8, Custom);
1162 setOperationAction(ISD::UINT_TO_FP, MVT::v8i16, Custom);
1164 setLoadExtAction(ISD::EXTLOAD, MVT::v4f32, Legal);
1166 setOperationAction(ISD::SRL, MVT::v16i16, Custom);
1167 setOperationAction(ISD::SRL, MVT::v32i8, Custom);
1169 setOperationAction(ISD::SHL, MVT::v16i16, Custom);
1170 setOperationAction(ISD::SHL, MVT::v32i8, Custom);
1172 setOperationAction(ISD::SRA, MVT::v16i16, Custom);
1173 setOperationAction(ISD::SRA, MVT::v32i8, Custom);
1175 setOperationAction(ISD::SDIV, MVT::v16i16, Custom);
1177 setOperationAction(ISD::SETCC, MVT::v32i8, Custom);
1178 setOperationAction(ISD::SETCC, MVT::v16i16, Custom);
1179 setOperationAction(ISD::SETCC, MVT::v8i32, Custom);
1180 setOperationAction(ISD::SETCC, MVT::v4i64, Custom);
1182 setOperationAction(ISD::SELECT, MVT::v4f64, Custom);
1183 setOperationAction(ISD::SELECT, MVT::v4i64, Custom);
1184 setOperationAction(ISD::SELECT, MVT::v8f32, Custom);
1186 setOperationAction(ISD::VSELECT, MVT::v4f64, Legal);
1187 setOperationAction(ISD::VSELECT, MVT::v4i64, Legal);
1188 setOperationAction(ISD::VSELECT, MVT::v8i32, Legal);
1189 setOperationAction(ISD::VSELECT, MVT::v8f32, Legal);
1191 setOperationAction(ISD::SIGN_EXTEND, MVT::v4i64, Custom);
1192 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i32, Custom);
1193 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i16, Custom);
1194 setOperationAction(ISD::ZERO_EXTEND, MVT::v4i64, Custom);
1195 setOperationAction(ISD::ZERO_EXTEND, MVT::v8i32, Custom);
1196 setOperationAction(ISD::ZERO_EXTEND, MVT::v16i16, Custom);
1197 setOperationAction(ISD::ANY_EXTEND, MVT::v4i64, Custom);
1198 setOperationAction(ISD::ANY_EXTEND, MVT::v8i32, Custom);
1199 setOperationAction(ISD::ANY_EXTEND, MVT::v16i16, Custom);
1200 setOperationAction(ISD::TRUNCATE, MVT::v16i8, Custom);
1201 setOperationAction(ISD::TRUNCATE, MVT::v8i16, Custom);
1202 setOperationAction(ISD::TRUNCATE, MVT::v4i32, Custom);
1204 if (Subtarget->hasFMA() || Subtarget->hasFMA4()) {
1205 setOperationAction(ISD::FMA, MVT::v8f32, Legal);
1206 setOperationAction(ISD::FMA, MVT::v4f64, Legal);
1207 setOperationAction(ISD::FMA, MVT::v4f32, Legal);
1208 setOperationAction(ISD::FMA, MVT::v2f64, Legal);
1209 setOperationAction(ISD::FMA, MVT::f32, Legal);
1210 setOperationAction(ISD::FMA, MVT::f64, Legal);
1213 if (Subtarget->hasInt256()) {
1214 setOperationAction(ISD::ADD, MVT::v4i64, Legal);
1215 setOperationAction(ISD::ADD, MVT::v8i32, Legal);
1216 setOperationAction(ISD::ADD, MVT::v16i16, Legal);
1217 setOperationAction(ISD::ADD, MVT::v32i8, Legal);
1219 setOperationAction(ISD::SUB, MVT::v4i64, Legal);
1220 setOperationAction(ISD::SUB, MVT::v8i32, Legal);
1221 setOperationAction(ISD::SUB, MVT::v16i16, Legal);
1222 setOperationAction(ISD::SUB, MVT::v32i8, Legal);
1224 setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1225 setOperationAction(ISD::MUL, MVT::v8i32, Legal);
1226 setOperationAction(ISD::MUL, MVT::v16i16, Legal);
1227 // Don't lower v32i8 because there is no 128-bit byte mul
1229 setOperationAction(ISD::VSELECT, MVT::v32i8, Legal);
1231 setOperationAction(ISD::SDIV, MVT::v8i32, Custom);
1233 setOperationAction(ISD::ADD, MVT::v4i64, Custom);
1234 setOperationAction(ISD::ADD, MVT::v8i32, Custom);
1235 setOperationAction(ISD::ADD, MVT::v16i16, Custom);
1236 setOperationAction(ISD::ADD, MVT::v32i8, Custom);
1238 setOperationAction(ISD::SUB, MVT::v4i64, Custom);
1239 setOperationAction(ISD::SUB, MVT::v8i32, Custom);
1240 setOperationAction(ISD::SUB, MVT::v16i16, Custom);
1241 setOperationAction(ISD::SUB, MVT::v32i8, Custom);
1243 setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1244 setOperationAction(ISD::MUL, MVT::v8i32, Custom);
1245 setOperationAction(ISD::MUL, MVT::v16i16, Custom);
1246 // Don't lower v32i8 because there is no 128-bit byte mul
1249 // In the customized shift lowering, the legal cases in AVX2 will be
1251 setOperationAction(ISD::SRL, MVT::v4i64, Custom);
1252 setOperationAction(ISD::SRL, MVT::v8i32, Custom);
1254 setOperationAction(ISD::SHL, MVT::v4i64, Custom);
1255 setOperationAction(ISD::SHL, MVT::v8i32, Custom);
1257 setOperationAction(ISD::SRA, MVT::v8i32, Custom);
1259 // Custom lower several nodes for 256-bit types.
1260 for (int i = MVT::FIRST_VECTOR_VALUETYPE;
1261 i <= MVT::LAST_VECTOR_VALUETYPE; ++i) {
1262 MVT VT = (MVT::SimpleValueType)i;
1264 // Extract subvector is special because the value type
1265 // (result) is 128-bit but the source is 256-bit wide.
1266 if (VT.is128BitVector())
1267 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom);
1269 // Do not attempt to custom lower other non-256-bit vectors
1270 if (!VT.is256BitVector())
1273 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1274 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1275 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
1276 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1277 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom);
1278 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom);
1279 setOperationAction(ISD::CONCAT_VECTORS, VT, Custom);
1282 // Promote v32i8, v16i16, v8i32 select, and, or, xor to v4i64.
1283 for (int i = MVT::v32i8; i != MVT::v4i64; ++i) {
1284 MVT VT = (MVT::SimpleValueType)i;
1286 // Do not attempt to promote non-256-bit vectors
1287 if (!VT.is256BitVector())
1290 setOperationAction(ISD::AND, VT, Promote);
1291 AddPromotedToType (ISD::AND, VT, MVT::v4i64);
1292 setOperationAction(ISD::OR, VT, Promote);
1293 AddPromotedToType (ISD::OR, VT, MVT::v4i64);
1294 setOperationAction(ISD::XOR, VT, Promote);
1295 AddPromotedToType (ISD::XOR, VT, MVT::v4i64);
1296 setOperationAction(ISD::LOAD, VT, Promote);
1297 AddPromotedToType (ISD::LOAD, VT, MVT::v4i64);
1298 setOperationAction(ISD::SELECT, VT, Promote);
1299 AddPromotedToType (ISD::SELECT, VT, MVT::v4i64);
1303 if (!TM.Options.UseSoftFloat && Subtarget->hasAVX512()) {
1304 addRegisterClass(MVT::v16i32, &X86::VR512RegClass);
1305 addRegisterClass(MVT::v16f32, &X86::VR512RegClass);
1306 addRegisterClass(MVT::v8i64, &X86::VR512RegClass);
1307 addRegisterClass(MVT::v8f64, &X86::VR512RegClass);
1309 addRegisterClass(MVT::v8i1, &X86::VK8RegClass);
1310 addRegisterClass(MVT::v16i1, &X86::VK16RegClass);
1312 setLoadExtAction(ISD::EXTLOAD, MVT::v8f32, Legal);
1313 setOperationAction(ISD::LOAD, MVT::v16f32, Legal);
1314 setOperationAction(ISD::LOAD, MVT::v8f64, Legal);
1315 setOperationAction(ISD::LOAD, MVT::v8i64, Legal);
1316 setOperationAction(ISD::LOAD, MVT::v16i32, Legal);
1317 setOperationAction(ISD::LOAD, MVT::v16i1, Legal);
1319 setOperationAction(ISD::FADD, MVT::v16f32, Legal);
1320 setOperationAction(ISD::FSUB, MVT::v16f32, Legal);
1321 setOperationAction(ISD::FMUL, MVT::v16f32, Legal);
1322 setOperationAction(ISD::FDIV, MVT::v16f32, Legal);
1323 setOperationAction(ISD::FSQRT, MVT::v16f32, Legal);
1324 setOperationAction(ISD::FNEG, MVT::v16f32, Custom);
1326 setOperationAction(ISD::FADD, MVT::v8f64, Legal);
1327 setOperationAction(ISD::FSUB, MVT::v8f64, Legal);
1328 setOperationAction(ISD::FMUL, MVT::v8f64, Legal);
1329 setOperationAction(ISD::FDIV, MVT::v8f64, Legal);
1330 setOperationAction(ISD::FSQRT, MVT::v8f64, Legal);
1331 setOperationAction(ISD::FNEG, MVT::v8f64, Custom);
1332 setOperationAction(ISD::FMA, MVT::v8f64, Legal);
1333 setOperationAction(ISD::FMA, MVT::v16f32, Legal);
1334 setOperationAction(ISD::SDIV, MVT::v16i32, Custom);
1336 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Legal);
1337 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Legal);
1338 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Legal);
1339 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Legal);
1340 if (Subtarget->is64Bit()) {
1341 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Legal);
1342 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Legal);
1343 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Legal);
1344 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Legal);
1346 setOperationAction(ISD::FP_TO_SINT, MVT::v16i32, Legal);
1347 setOperationAction(ISD::FP_TO_UINT, MVT::v16i32, Legal);
1348 setOperationAction(ISD::FP_TO_UINT, MVT::v8i32, Legal);
1349 setOperationAction(ISD::SINT_TO_FP, MVT::v16i32, Legal);
1350 setOperationAction(ISD::UINT_TO_FP, MVT::v16i32, Legal);
1351 setOperationAction(ISD::UINT_TO_FP, MVT::v8i32, Legal);
1352 setOperationAction(ISD::FP_ROUND, MVT::v8f32, Legal);
1353 setOperationAction(ISD::FP_EXTEND, MVT::v8f32, Legal);
1355 setOperationAction(ISD::TRUNCATE, MVT::i1, Legal);
1356 setOperationAction(ISD::TRUNCATE, MVT::v16i8, Custom);
1357 setOperationAction(ISD::TRUNCATE, MVT::v8i32, Custom);
1358 setOperationAction(ISD::TRUNCATE, MVT::v8i1, Custom);
1359 setOperationAction(ISD::TRUNCATE, MVT::v16i1, Custom);
1360 setOperationAction(ISD::ZERO_EXTEND, MVT::v16i32, Custom);
1361 setOperationAction(ISD::ZERO_EXTEND, MVT::v8i64, Custom);
1362 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i32, Custom);
1363 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i64, Custom);
1364 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i8, Custom);
1365 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i16, Custom);
1366 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i16, Custom);
1368 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8f64, Custom);
1369 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i64, Custom);
1370 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16f32, Custom);
1371 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i32, Custom);
1372 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i1, Custom);
1374 setOperationAction(ISD::SETCC, MVT::v16i1, Custom);
1375 setOperationAction(ISD::SETCC, MVT::v8i1, Custom);
1377 setOperationAction(ISD::MUL, MVT::v8i64, Custom);
1379 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i1, Custom);
1380 setOperationAction(ISD::BUILD_VECTOR, MVT::v16i1, Custom);
1381 setOperationAction(ISD::SELECT, MVT::v8f64, Custom);
1382 setOperationAction(ISD::SELECT, MVT::v8i64, Custom);
1383 setOperationAction(ISD::SELECT, MVT::v16f32, Custom);
1385 setOperationAction(ISD::ADD, MVT::v8i64, Legal);
1386 setOperationAction(ISD::ADD, MVT::v16i32, Legal);
1388 setOperationAction(ISD::SUB, MVT::v8i64, Legal);
1389 setOperationAction(ISD::SUB, MVT::v16i32, Legal);
1391 setOperationAction(ISD::MUL, MVT::v16i32, Legal);
1393 setOperationAction(ISD::SRL, MVT::v8i64, Custom);
1394 setOperationAction(ISD::SRL, MVT::v16i32, Custom);
1396 setOperationAction(ISD::SHL, MVT::v8i64, Custom);
1397 setOperationAction(ISD::SHL, MVT::v16i32, Custom);
1399 setOperationAction(ISD::SRA, MVT::v8i64, Custom);
1400 setOperationAction(ISD::SRA, MVT::v16i32, Custom);
1402 setOperationAction(ISD::AND, MVT::v8i64, Legal);
1403 setOperationAction(ISD::OR, MVT::v8i64, Legal);
1404 setOperationAction(ISD::XOR, MVT::v8i64, Legal);
1405 setOperationAction(ISD::AND, MVT::v16i32, Legal);
1406 setOperationAction(ISD::OR, MVT::v16i32, Legal);
1407 setOperationAction(ISD::XOR, MVT::v16i32, Legal);
1409 // Custom lower several nodes.
1410 for (int i = MVT::FIRST_VECTOR_VALUETYPE;
1411 i <= MVT::LAST_VECTOR_VALUETYPE; ++i) {
1412 MVT VT = (MVT::SimpleValueType)i;
1414 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
1415 // Extract subvector is special because the value type
1416 // (result) is 256/128-bit but the source is 512-bit wide.
1417 if (VT.is128BitVector() || VT.is256BitVector())
1418 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom);
1420 if (VT.getVectorElementType() == MVT::i1)
1421 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Legal);
1423 // Do not attempt to custom lower other non-512-bit vectors
1424 if (!VT.is512BitVector())
1427 if ( EltSize >= 32) {
1428 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1429 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
1430 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1431 setOperationAction(ISD::VSELECT, VT, Legal);
1432 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1433 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom);
1434 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom);
1437 for (int i = MVT::v32i8; i != MVT::v8i64; ++i) {
1438 MVT VT = (MVT::SimpleValueType)i;
1440 // Do not attempt to promote non-256-bit vectors
1441 if (!VT.is512BitVector())
1444 setOperationAction(ISD::SELECT, VT, Promote);
1445 AddPromotedToType (ISD::SELECT, VT, MVT::v8i64);
1449 // SIGN_EXTEND_INREGs are evaluated by the extend type. Handle the expansion
1450 // of this type with custom code.
1451 for (int VT = MVT::FIRST_VECTOR_VALUETYPE;
1452 VT != MVT::LAST_VECTOR_VALUETYPE; VT++) {
1453 setOperationAction(ISD::SIGN_EXTEND_INREG, (MVT::SimpleValueType)VT,
1457 // We want to custom lower some of our intrinsics.
1458 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
1459 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::Other, Custom);
1460 setOperationAction(ISD::INTRINSIC_VOID, MVT::Other, Custom);
1462 // Only custom-lower 64-bit SADDO and friends on 64-bit because we don't
1463 // handle type legalization for these operations here.
1465 // FIXME: We really should do custom legalization for addition and
1466 // subtraction on x86-32 once PR3203 is fixed. We really can't do much better
1467 // than generic legalization for 64-bit multiplication-with-overflow, though.
1468 for (unsigned i = 0, e = 3+Subtarget->is64Bit(); i != e; ++i) {
1469 // Add/Sub/Mul with overflow operations are custom lowered.
1471 setOperationAction(ISD::SADDO, VT, Custom);
1472 setOperationAction(ISD::UADDO, VT, Custom);
1473 setOperationAction(ISD::SSUBO, VT, Custom);
1474 setOperationAction(ISD::USUBO, VT, Custom);
1475 setOperationAction(ISD::SMULO, VT, Custom);
1476 setOperationAction(ISD::UMULO, VT, Custom);
1479 // There are no 8-bit 3-address imul/mul instructions
1480 setOperationAction(ISD::SMULO, MVT::i8, Expand);
1481 setOperationAction(ISD::UMULO, MVT::i8, Expand);
1483 if (!Subtarget->is64Bit()) {
1484 // These libcalls are not available in 32-bit.
1485 setLibcallName(RTLIB::SHL_I128, 0);
1486 setLibcallName(RTLIB::SRL_I128, 0);
1487 setLibcallName(RTLIB::SRA_I128, 0);
1490 // Combine sin / cos into one node or libcall if possible.
1491 if (Subtarget->hasSinCos()) {
1492 setLibcallName(RTLIB::SINCOS_F32, "sincosf");
1493 setLibcallName(RTLIB::SINCOS_F64, "sincos");
1494 if (Subtarget->isTargetDarwin()) {
1495 // For MacOSX, we don't want to the normal expansion of a libcall to
1496 // sincos. We want to issue a libcall to __sincos_stret to avoid memory
1498 setOperationAction(ISD::FSINCOS, MVT::f64, Custom);
1499 setOperationAction(ISD::FSINCOS, MVT::f32, Custom);
1503 // We have target-specific dag combine patterns for the following nodes:
1504 setTargetDAGCombine(ISD::VECTOR_SHUFFLE);
1505 setTargetDAGCombine(ISD::EXTRACT_VECTOR_ELT);
1506 setTargetDAGCombine(ISD::VSELECT);
1507 setTargetDAGCombine(ISD::SELECT);
1508 setTargetDAGCombine(ISD::SHL);
1509 setTargetDAGCombine(ISD::SRA);
1510 setTargetDAGCombine(ISD::SRL);
1511 setTargetDAGCombine(ISD::OR);
1512 setTargetDAGCombine(ISD::AND);
1513 setTargetDAGCombine(ISD::ADD);
1514 setTargetDAGCombine(ISD::FADD);
1515 setTargetDAGCombine(ISD::FSUB);
1516 setTargetDAGCombine(ISD::FMA);
1517 setTargetDAGCombine(ISD::SUB);
1518 setTargetDAGCombine(ISD::LOAD);
1519 setTargetDAGCombine(ISD::STORE);
1520 setTargetDAGCombine(ISD::ZERO_EXTEND);
1521 setTargetDAGCombine(ISD::ANY_EXTEND);
1522 setTargetDAGCombine(ISD::SIGN_EXTEND);
1523 setTargetDAGCombine(ISD::SIGN_EXTEND_INREG);
1524 setTargetDAGCombine(ISD::TRUNCATE);
1525 setTargetDAGCombine(ISD::SINT_TO_FP);
1526 setTargetDAGCombine(ISD::SETCC);
1527 if (Subtarget->is64Bit())
1528 setTargetDAGCombine(ISD::MUL);
1529 setTargetDAGCombine(ISD::XOR);
1531 computeRegisterProperties();
1533 // On Darwin, -Os means optimize for size without hurting performance,
1534 // do not reduce the limit.
1535 MaxStoresPerMemset = 16; // For @llvm.memset -> sequence of stores
1536 MaxStoresPerMemsetOptSize = Subtarget->isTargetDarwin() ? 16 : 8;
1537 MaxStoresPerMemcpy = 8; // For @llvm.memcpy -> sequence of stores
1538 MaxStoresPerMemcpyOptSize = Subtarget->isTargetDarwin() ? 8 : 4;
1539 MaxStoresPerMemmove = 8; // For @llvm.memmove -> sequence of stores
1540 MaxStoresPerMemmoveOptSize = Subtarget->isTargetDarwin() ? 8 : 4;
1541 setPrefLoopAlignment(4); // 2^4 bytes.
1543 // Predictable cmov don't hurt on atom because it's in-order.
1544 PredictableSelectIsExpensive = !Subtarget->isAtom();
1546 setPrefFunctionAlignment(4); // 2^4 bytes.
1549 EVT X86TargetLowering::getSetCCResultType(LLVMContext &, EVT VT) const {
1553 const TargetMachine &TM = getTargetMachine();
1554 if (!TM.Options.UseSoftFloat && Subtarget->hasAVX512())
1555 switch(VT.getVectorNumElements()) {
1556 case 8: return MVT::v8i1;
1557 case 16: return MVT::v16i1;
1560 return VT.changeVectorElementTypeToInteger();
1563 /// getMaxByValAlign - Helper for getByValTypeAlignment to determine
1564 /// the desired ByVal argument alignment.
1565 static void getMaxByValAlign(Type *Ty, unsigned &MaxAlign) {
1568 if (VectorType *VTy = dyn_cast<VectorType>(Ty)) {
1569 if (VTy->getBitWidth() == 128)
1571 } else if (ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
1572 unsigned EltAlign = 0;
1573 getMaxByValAlign(ATy->getElementType(), EltAlign);
1574 if (EltAlign > MaxAlign)
1575 MaxAlign = EltAlign;
1576 } else if (StructType *STy = dyn_cast<StructType>(Ty)) {
1577 for (unsigned i = 0, e = STy->getNumElements(); i != e; ++i) {
1578 unsigned EltAlign = 0;
1579 getMaxByValAlign(STy->getElementType(i), EltAlign);
1580 if (EltAlign > MaxAlign)
1581 MaxAlign = EltAlign;
1588 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
1589 /// function arguments in the caller parameter area. For X86, aggregates
1590 /// that contain SSE vectors are placed at 16-byte boundaries while the rest
1591 /// are at 4-byte boundaries.
1592 unsigned X86TargetLowering::getByValTypeAlignment(Type *Ty) const {
1593 if (Subtarget->is64Bit()) {
1594 // Max of 8 and alignment of type.
1595 unsigned TyAlign = TD->getABITypeAlignment(Ty);
1602 if (Subtarget->hasSSE1())
1603 getMaxByValAlign(Ty, Align);
1607 /// getOptimalMemOpType - Returns the target specific optimal type for load
1608 /// and store operations as a result of memset, memcpy, and memmove
1609 /// lowering. If DstAlign is zero that means it's safe to destination
1610 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
1611 /// means there isn't a need to check it against alignment requirement,
1612 /// probably because the source does not need to be loaded. If 'IsMemset' is
1613 /// true, that means it's expanding a memset. If 'ZeroMemset' is true, that
1614 /// means it's a memset of zero. 'MemcpyStrSrc' indicates whether the memcpy
1615 /// source is constant so it does not need to be loaded.
1616 /// It returns EVT::Other if the type should be determined using generic
1617 /// target-independent logic.
1619 X86TargetLowering::getOptimalMemOpType(uint64_t Size,
1620 unsigned DstAlign, unsigned SrcAlign,
1621 bool IsMemset, bool ZeroMemset,
1623 MachineFunction &MF) const {
1624 const Function *F = MF.getFunction();
1625 if ((!IsMemset || ZeroMemset) &&
1626 !F->getAttributes().hasAttribute(AttributeSet::FunctionIndex,
1627 Attribute::NoImplicitFloat)) {
1629 (Subtarget->isUnalignedMemAccessFast() ||
1630 ((DstAlign == 0 || DstAlign >= 16) &&
1631 (SrcAlign == 0 || SrcAlign >= 16)))) {
1633 if (Subtarget->hasInt256())
1635 if (Subtarget->hasFp256())
1638 if (Subtarget->hasSSE2())
1640 if (Subtarget->hasSSE1())
1642 } else if (!MemcpyStrSrc && Size >= 8 &&
1643 !Subtarget->is64Bit() &&
1644 Subtarget->hasSSE2()) {
1645 // Do not use f64 to lower memcpy if source is string constant. It's
1646 // better to use i32 to avoid the loads.
1650 if (Subtarget->is64Bit() && Size >= 8)
1655 bool X86TargetLowering::isSafeMemOpType(MVT VT) const {
1657 return X86ScalarSSEf32;
1658 else if (VT == MVT::f64)
1659 return X86ScalarSSEf64;
1664 X86TargetLowering::allowsUnalignedMemoryAccesses(EVT VT, bool *Fast) const {
1666 *Fast = Subtarget->isUnalignedMemAccessFast();
1670 /// getJumpTableEncoding - Return the entry encoding for a jump table in the
1671 /// current function. The returned value is a member of the
1672 /// MachineJumpTableInfo::JTEntryKind enum.
1673 unsigned X86TargetLowering::getJumpTableEncoding() const {
1674 // In GOT pic mode, each entry in the jump table is emitted as a @GOTOFF
1676 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1677 Subtarget->isPICStyleGOT())
1678 return MachineJumpTableInfo::EK_Custom32;
1680 // Otherwise, use the normal jump table encoding heuristics.
1681 return TargetLowering::getJumpTableEncoding();
1685 X86TargetLowering::LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI,
1686 const MachineBasicBlock *MBB,
1687 unsigned uid,MCContext &Ctx) const{
1688 assert(getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1689 Subtarget->isPICStyleGOT());
1690 // In 32-bit ELF systems, our jump table entries are formed with @GOTOFF
1692 return MCSymbolRefExpr::Create(MBB->getSymbol(),
1693 MCSymbolRefExpr::VK_GOTOFF, Ctx);
1696 /// getPICJumpTableRelocaBase - Returns relocation base for the given PIC
1698 SDValue X86TargetLowering::getPICJumpTableRelocBase(SDValue Table,
1699 SelectionDAG &DAG) const {
1700 if (!Subtarget->is64Bit())
1701 // This doesn't have SDLoc associated with it, but is not really the
1702 // same as a Register.
1703 return DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), getPointerTy());
1707 /// getPICJumpTableRelocBaseExpr - This returns the relocation base for the
1708 /// given PIC jumptable, the same as getPICJumpTableRelocBase, but as an
1710 const MCExpr *X86TargetLowering::
1711 getPICJumpTableRelocBaseExpr(const MachineFunction *MF, unsigned JTI,
1712 MCContext &Ctx) const {
1713 // X86-64 uses RIP relative addressing based on the jump table label.
1714 if (Subtarget->isPICStyleRIPRel())
1715 return TargetLowering::getPICJumpTableRelocBaseExpr(MF, JTI, Ctx);
1717 // Otherwise, the reference is relative to the PIC base.
1718 return MCSymbolRefExpr::Create(MF->getPICBaseSymbol(), Ctx);
1721 // FIXME: Why this routine is here? Move to RegInfo!
1722 std::pair<const TargetRegisterClass*, uint8_t>
1723 X86TargetLowering::findRepresentativeClass(MVT VT) const{
1724 const TargetRegisterClass *RRC = 0;
1726 switch (VT.SimpleTy) {
1728 return TargetLowering::findRepresentativeClass(VT);
1729 case MVT::i8: case MVT::i16: case MVT::i32: case MVT::i64:
1730 RRC = Subtarget->is64Bit() ?
1731 (const TargetRegisterClass*)&X86::GR64RegClass :
1732 (const TargetRegisterClass*)&X86::GR32RegClass;
1735 RRC = &X86::VR64RegClass;
1737 case MVT::f32: case MVT::f64:
1738 case MVT::v16i8: case MVT::v8i16: case MVT::v4i32: case MVT::v2i64:
1739 case MVT::v4f32: case MVT::v2f64:
1740 case MVT::v32i8: case MVT::v8i32: case MVT::v4i64: case MVT::v8f32:
1742 RRC = &X86::VR128RegClass;
1745 return std::make_pair(RRC, Cost);
1748 bool X86TargetLowering::getStackCookieLocation(unsigned &AddressSpace,
1749 unsigned &Offset) const {
1750 if (!Subtarget->isTargetLinux())
1753 if (Subtarget->is64Bit()) {
1754 // %fs:0x28, unless we're using a Kernel code model, in which case it's %gs:
1756 if (getTargetMachine().getCodeModel() == CodeModel::Kernel)
1768 bool X86TargetLowering::isNoopAddrSpaceCast(unsigned SrcAS,
1769 unsigned DestAS) const {
1770 assert(SrcAS != DestAS && "Expected different address spaces!");
1772 return SrcAS < 256 && DestAS < 256;
1775 //===----------------------------------------------------------------------===//
1776 // Return Value Calling Convention Implementation
1777 //===----------------------------------------------------------------------===//
1779 #include "X86GenCallingConv.inc"
1782 X86TargetLowering::CanLowerReturn(CallingConv::ID CallConv,
1783 MachineFunction &MF, bool isVarArg,
1784 const SmallVectorImpl<ISD::OutputArg> &Outs,
1785 LLVMContext &Context) const {
1786 SmallVector<CCValAssign, 16> RVLocs;
1787 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(),
1789 return CCInfo.CheckReturn(Outs, RetCC_X86);
1792 const uint16_t *X86TargetLowering::getScratchRegisters(CallingConv::ID) const {
1793 static const uint16_t ScratchRegs[] = { X86::R11, 0 };
1798 X86TargetLowering::LowerReturn(SDValue Chain,
1799 CallingConv::ID CallConv, bool isVarArg,
1800 const SmallVectorImpl<ISD::OutputArg> &Outs,
1801 const SmallVectorImpl<SDValue> &OutVals,
1802 SDLoc dl, SelectionDAG &DAG) const {
1803 MachineFunction &MF = DAG.getMachineFunction();
1804 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1806 SmallVector<CCValAssign, 16> RVLocs;
1807 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(),
1808 RVLocs, *DAG.getContext());
1809 CCInfo.AnalyzeReturn(Outs, RetCC_X86);
1812 SmallVector<SDValue, 6> RetOps;
1813 RetOps.push_back(Chain); // Operand #0 = Chain (updated below)
1814 // Operand #1 = Bytes To Pop
1815 RetOps.push_back(DAG.getTargetConstant(FuncInfo->getBytesToPopOnReturn(),
1818 // Copy the result values into the output registers.
1819 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1820 CCValAssign &VA = RVLocs[i];
1821 assert(VA.isRegLoc() && "Can only return in registers!");
1822 SDValue ValToCopy = OutVals[i];
1823 EVT ValVT = ValToCopy.getValueType();
1825 // Promote values to the appropriate types
1826 if (VA.getLocInfo() == CCValAssign::SExt)
1827 ValToCopy = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), ValToCopy);
1828 else if (VA.getLocInfo() == CCValAssign::ZExt)
1829 ValToCopy = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), ValToCopy);
1830 else if (VA.getLocInfo() == CCValAssign::AExt)
1831 ValToCopy = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), ValToCopy);
1832 else if (VA.getLocInfo() == CCValAssign::BCvt)
1833 ValToCopy = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), ValToCopy);
1835 // If this is x86-64, and we disabled SSE, we can't return FP values,
1836 // or SSE or MMX vectors.
1837 if ((ValVT == MVT::f32 || ValVT == MVT::f64 ||
1838 VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) &&
1839 (Subtarget->is64Bit() && !Subtarget->hasSSE1())) {
1840 report_fatal_error("SSE register return with SSE disabled");
1842 // Likewise we can't return F64 values with SSE1 only. gcc does so, but
1843 // llvm-gcc has never done it right and no one has noticed, so this
1844 // should be OK for now.
1845 if (ValVT == MVT::f64 &&
1846 (Subtarget->is64Bit() && !Subtarget->hasSSE2()))
1847 report_fatal_error("SSE2 register return with SSE2 disabled");
1849 // Returns in ST0/ST1 are handled specially: these are pushed as operands to
1850 // the RET instruction and handled by the FP Stackifier.
1851 if (VA.getLocReg() == X86::ST0 ||
1852 VA.getLocReg() == X86::ST1) {
1853 // If this is a copy from an xmm register to ST(0), use an FPExtend to
1854 // change the value to the FP stack register class.
1855 if (isScalarFPTypeInSSEReg(VA.getValVT()))
1856 ValToCopy = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f80, ValToCopy);
1857 RetOps.push_back(ValToCopy);
1858 // Don't emit a copytoreg.
1862 // 64-bit vector (MMX) values are returned in XMM0 / XMM1 except for v1i64
1863 // which is returned in RAX / RDX.
1864 if (Subtarget->is64Bit()) {
1865 if (ValVT == MVT::x86mmx) {
1866 if (VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) {
1867 ValToCopy = DAG.getNode(ISD::BITCAST, dl, MVT::i64, ValToCopy);
1868 ValToCopy = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
1870 // If we don't have SSE2 available, convert to v4f32 so the generated
1871 // register is legal.
1872 if (!Subtarget->hasSSE2())
1873 ValToCopy = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32,ValToCopy);
1878 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), ValToCopy, Flag);
1879 Flag = Chain.getValue(1);
1880 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
1883 // The x86-64 ABIs require that for returning structs by value we copy
1884 // the sret argument into %rax/%eax (depending on ABI) for the return.
1885 // Win32 requires us to put the sret argument to %eax as well.
1886 // We saved the argument into a virtual register in the entry block,
1887 // so now we copy the value out and into %rax/%eax.
1888 if (DAG.getMachineFunction().getFunction()->hasStructRetAttr() &&
1889 (Subtarget->is64Bit() || Subtarget->isTargetWindows())) {
1890 MachineFunction &MF = DAG.getMachineFunction();
1891 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1892 unsigned Reg = FuncInfo->getSRetReturnReg();
1894 "SRetReturnReg should have been set in LowerFormalArguments().");
1895 SDValue Val = DAG.getCopyFromReg(Chain, dl, Reg, getPointerTy());
1898 = (Subtarget->is64Bit() && !Subtarget->isTarget64BitILP32()) ?
1899 X86::RAX : X86::EAX;
1900 Chain = DAG.getCopyToReg(Chain, dl, RetValReg, Val, Flag);
1901 Flag = Chain.getValue(1);
1903 // RAX/EAX now acts like a return value.
1904 RetOps.push_back(DAG.getRegister(RetValReg, getPointerTy()));
1907 RetOps[0] = Chain; // Update chain.
1909 // Add the flag if we have it.
1911 RetOps.push_back(Flag);
1913 return DAG.getNode(X86ISD::RET_FLAG, dl,
1914 MVT::Other, &RetOps[0], RetOps.size());
1917 bool X86TargetLowering::isUsedByReturnOnly(SDNode *N, SDValue &Chain) const {
1918 if (N->getNumValues() != 1)
1920 if (!N->hasNUsesOfValue(1, 0))
1923 SDValue TCChain = Chain;
1924 SDNode *Copy = *N->use_begin();
1925 if (Copy->getOpcode() == ISD::CopyToReg) {
1926 // If the copy has a glue operand, we conservatively assume it isn't safe to
1927 // perform a tail call.
1928 if (Copy->getOperand(Copy->getNumOperands()-1).getValueType() == MVT::Glue)
1930 TCChain = Copy->getOperand(0);
1931 } else if (Copy->getOpcode() != ISD::FP_EXTEND)
1934 bool HasRet = false;
1935 for (SDNode::use_iterator UI = Copy->use_begin(), UE = Copy->use_end();
1937 if (UI->getOpcode() != X86ISD::RET_FLAG)
1950 X86TargetLowering::getTypeForExtArgOrReturn(MVT VT,
1951 ISD::NodeType ExtendKind) const {
1953 // TODO: Is this also valid on 32-bit?
1954 if (Subtarget->is64Bit() && VT == MVT::i1 && ExtendKind == ISD::ZERO_EXTEND)
1955 ReturnMVT = MVT::i8;
1957 ReturnMVT = MVT::i32;
1959 MVT MinVT = getRegisterType(ReturnMVT);
1960 return VT.bitsLT(MinVT) ? MinVT : VT;
1963 /// LowerCallResult - Lower the result values of a call into the
1964 /// appropriate copies out of appropriate physical registers.
1967 X86TargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
1968 CallingConv::ID CallConv, bool isVarArg,
1969 const SmallVectorImpl<ISD::InputArg> &Ins,
1970 SDLoc dl, SelectionDAG &DAG,
1971 SmallVectorImpl<SDValue> &InVals) const {
1973 // Assign locations to each value returned by this call.
1974 SmallVector<CCValAssign, 16> RVLocs;
1975 bool Is64Bit = Subtarget->is64Bit();
1976 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
1977 getTargetMachine(), RVLocs, *DAG.getContext());
1978 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
1980 // Copy all of the result registers out of their specified physreg.
1981 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
1982 CCValAssign &VA = RVLocs[i];
1983 EVT CopyVT = VA.getValVT();
1985 // If this is x86-64, and we disabled SSE, we can't return FP values
1986 if ((CopyVT == MVT::f32 || CopyVT == MVT::f64) &&
1987 ((Is64Bit || Ins[i].Flags.isInReg()) && !Subtarget->hasSSE1())) {
1988 report_fatal_error("SSE register return with SSE disabled");
1993 // If this is a call to a function that returns an fp value on the floating
1994 // point stack, we must guarantee the value is popped from the stack, so
1995 // a CopyFromReg is not good enough - the copy instruction may be eliminated
1996 // if the return value is not used. We use the FpPOP_RETVAL instruction
1998 if (VA.getLocReg() == X86::ST0 || VA.getLocReg() == X86::ST1) {
1999 // If we prefer to use the value in xmm registers, copy it out as f80 and
2000 // use a truncate to move it from fp stack reg to xmm reg.
2001 if (isScalarFPTypeInSSEReg(VA.getValVT())) CopyVT = MVT::f80;
2002 SDValue Ops[] = { Chain, InFlag };
2003 Chain = SDValue(DAG.getMachineNode(X86::FpPOP_RETVAL, dl, CopyVT,
2004 MVT::Other, MVT::Glue, Ops), 1);
2005 Val = Chain.getValue(0);
2007 // Round the f80 to the right size, which also moves it to the appropriate
2009 if (CopyVT != VA.getValVT())
2010 Val = DAG.getNode(ISD::FP_ROUND, dl, VA.getValVT(), Val,
2011 // This truncation won't change the value.
2012 DAG.getIntPtrConstant(1));
2014 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(),
2015 CopyVT, InFlag).getValue(1);
2016 Val = Chain.getValue(0);
2018 InFlag = Chain.getValue(2);
2019 InVals.push_back(Val);
2025 //===----------------------------------------------------------------------===//
2026 // C & StdCall & Fast Calling Convention implementation
2027 //===----------------------------------------------------------------------===//
2028 // StdCall calling convention seems to be standard for many Windows' API
2029 // routines and around. It differs from C calling convention just a little:
2030 // callee should clean up the stack, not caller. Symbols should be also
2031 // decorated in some fancy way :) It doesn't support any vector arguments.
2032 // For info on fast calling convention see Fast Calling Convention (tail call)
2033 // implementation LowerX86_32FastCCCallTo.
2035 /// CallIsStructReturn - Determines whether a call uses struct return
2037 enum StructReturnType {
2042 static StructReturnType
2043 callIsStructReturn(const SmallVectorImpl<ISD::OutputArg> &Outs) {
2045 return NotStructReturn;
2047 const ISD::ArgFlagsTy &Flags = Outs[0].Flags;
2048 if (!Flags.isSRet())
2049 return NotStructReturn;
2050 if (Flags.isInReg())
2051 return RegStructReturn;
2052 return StackStructReturn;
2055 /// ArgsAreStructReturn - Determines whether a function uses struct
2056 /// return semantics.
2057 static StructReturnType
2058 argsAreStructReturn(const SmallVectorImpl<ISD::InputArg> &Ins) {
2060 return NotStructReturn;
2062 const ISD::ArgFlagsTy &Flags = Ins[0].Flags;
2063 if (!Flags.isSRet())
2064 return NotStructReturn;
2065 if (Flags.isInReg())
2066 return RegStructReturn;
2067 return StackStructReturn;
2070 /// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified
2071 /// by "Src" to address "Dst" with size and alignment information specified by
2072 /// the specific parameter attribute. The copy will be passed as a byval
2073 /// function parameter.
2075 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
2076 ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
2078 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32);
2080 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
2081 /*isVolatile*/false, /*AlwaysInline=*/true,
2082 MachinePointerInfo(), MachinePointerInfo());
2085 /// IsTailCallConvention - Return true if the calling convention is one that
2086 /// supports tail call optimization.
2087 static bool IsTailCallConvention(CallingConv::ID CC) {
2088 return (CC == CallingConv::Fast || CC == CallingConv::GHC ||
2089 CC == CallingConv::HiPE);
2092 /// \brief Return true if the calling convention is a C calling convention.
2093 static bool IsCCallConvention(CallingConv::ID CC) {
2094 return (CC == CallingConv::C || CC == CallingConv::X86_64_Win64 ||
2095 CC == CallingConv::X86_64_SysV);
2098 bool X86TargetLowering::mayBeEmittedAsTailCall(CallInst *CI) const {
2099 if (!CI->isTailCall() || getTargetMachine().Options.DisableTailCalls)
2103 CallingConv::ID CalleeCC = CS.getCallingConv();
2104 if (!IsTailCallConvention(CalleeCC) && !IsCCallConvention(CalleeCC))
2110 /// FuncIsMadeTailCallSafe - Return true if the function is being made into
2111 /// a tailcall target by changing its ABI.
2112 static bool FuncIsMadeTailCallSafe(CallingConv::ID CC,
2113 bool GuaranteedTailCallOpt) {
2114 return GuaranteedTailCallOpt && IsTailCallConvention(CC);
2118 X86TargetLowering::LowerMemArgument(SDValue Chain,
2119 CallingConv::ID CallConv,
2120 const SmallVectorImpl<ISD::InputArg> &Ins,
2121 SDLoc dl, SelectionDAG &DAG,
2122 const CCValAssign &VA,
2123 MachineFrameInfo *MFI,
2125 // Create the nodes corresponding to a load from this parameter slot.
2126 ISD::ArgFlagsTy Flags = Ins[i].Flags;
2127 bool AlwaysUseMutable = FuncIsMadeTailCallSafe(CallConv,
2128 getTargetMachine().Options.GuaranteedTailCallOpt);
2129 bool isImmutable = !AlwaysUseMutable && !Flags.isByVal();
2132 // If value is passed by pointer we have address passed instead of the value
2134 if (VA.getLocInfo() == CCValAssign::Indirect)
2135 ValVT = VA.getLocVT();
2137 ValVT = VA.getValVT();
2139 // FIXME: For now, all byval parameter objects are marked mutable. This can be
2140 // changed with more analysis.
2141 // In case of tail call optimization mark all arguments mutable. Since they
2142 // could be overwritten by lowering of arguments in case of a tail call.
2143 if (Flags.isByVal()) {
2144 unsigned Bytes = Flags.getByValSize();
2145 if (Bytes == 0) Bytes = 1; // Don't create zero-sized stack objects.
2146 int FI = MFI->CreateFixedObject(Bytes, VA.getLocMemOffset(), isImmutable);
2147 return DAG.getFrameIndex(FI, getPointerTy());
2149 int FI = MFI->CreateFixedObject(ValVT.getSizeInBits()/8,
2150 VA.getLocMemOffset(), isImmutable);
2151 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
2152 return DAG.getLoad(ValVT, dl, Chain, FIN,
2153 MachinePointerInfo::getFixedStack(FI),
2154 false, false, false, 0);
2159 X86TargetLowering::LowerFormalArguments(SDValue Chain,
2160 CallingConv::ID CallConv,
2162 const SmallVectorImpl<ISD::InputArg> &Ins,
2165 SmallVectorImpl<SDValue> &InVals)
2167 MachineFunction &MF = DAG.getMachineFunction();
2168 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
2170 const Function* Fn = MF.getFunction();
2171 if (Fn->hasExternalLinkage() &&
2172 Subtarget->isTargetCygMing() &&
2173 Fn->getName() == "main")
2174 FuncInfo->setForceFramePointer(true);
2176 MachineFrameInfo *MFI = MF.getFrameInfo();
2177 bool Is64Bit = Subtarget->is64Bit();
2178 bool IsWindows = Subtarget->isTargetWindows();
2179 bool IsWin64 = Subtarget->isCallingConvWin64(CallConv);
2181 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
2182 "Var args not supported with calling convention fastcc, ghc or hipe");
2184 // Assign locations to all of the incoming arguments.
2185 SmallVector<CCValAssign, 16> ArgLocs;
2186 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(),
2187 ArgLocs, *DAG.getContext());
2189 // Allocate shadow area for Win64
2191 CCInfo.AllocateStack(32, 8);
2193 CCInfo.AnalyzeFormalArguments(Ins, CC_X86);
2195 unsigned LastVal = ~0U;
2197 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2198 CCValAssign &VA = ArgLocs[i];
2199 // TODO: If an arg is passed in two places (e.g. reg and stack), skip later
2201 assert(VA.getValNo() != LastVal &&
2202 "Don't support value assigned to multiple locs yet");
2204 LastVal = VA.getValNo();
2206 if (VA.isRegLoc()) {
2207 EVT RegVT = VA.getLocVT();
2208 const TargetRegisterClass *RC;
2209 if (RegVT == MVT::i32)
2210 RC = &X86::GR32RegClass;
2211 else if (Is64Bit && RegVT == MVT::i64)
2212 RC = &X86::GR64RegClass;
2213 else if (RegVT == MVT::f32)
2214 RC = &X86::FR32RegClass;
2215 else if (RegVT == MVT::f64)
2216 RC = &X86::FR64RegClass;
2217 else if (RegVT.is512BitVector())
2218 RC = &X86::VR512RegClass;
2219 else if (RegVT.is256BitVector())
2220 RC = &X86::VR256RegClass;
2221 else if (RegVT.is128BitVector())
2222 RC = &X86::VR128RegClass;
2223 else if (RegVT == MVT::x86mmx)
2224 RC = &X86::VR64RegClass;
2225 else if (RegVT == MVT::v8i1)
2226 RC = &X86::VK8RegClass;
2227 else if (RegVT == MVT::v16i1)
2228 RC = &X86::VK16RegClass;
2230 llvm_unreachable("Unknown argument type!");
2232 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
2233 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
2235 // If this is an 8 or 16-bit value, it is really passed promoted to 32
2236 // bits. Insert an assert[sz]ext to capture this, then truncate to the
2238 if (VA.getLocInfo() == CCValAssign::SExt)
2239 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
2240 DAG.getValueType(VA.getValVT()));
2241 else if (VA.getLocInfo() == CCValAssign::ZExt)
2242 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
2243 DAG.getValueType(VA.getValVT()));
2244 else if (VA.getLocInfo() == CCValAssign::BCvt)
2245 ArgValue = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), ArgValue);
2247 if (VA.isExtInLoc()) {
2248 // Handle MMX values passed in XMM regs.
2249 if (RegVT.isVector())
2250 ArgValue = DAG.getNode(X86ISD::MOVDQ2Q, dl, VA.getValVT(), ArgValue);
2252 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
2255 assert(VA.isMemLoc());
2256 ArgValue = LowerMemArgument(Chain, CallConv, Ins, dl, DAG, VA, MFI, i);
2259 // If value is passed via pointer - do a load.
2260 if (VA.getLocInfo() == CCValAssign::Indirect)
2261 ArgValue = DAG.getLoad(VA.getValVT(), dl, Chain, ArgValue,
2262 MachinePointerInfo(), false, false, false, 0);
2264 InVals.push_back(ArgValue);
2267 // The x86-64 ABIs require that for returning structs by value we copy
2268 // the sret argument into %rax/%eax (depending on ABI) for the return.
2269 // Win32 requires us to put the sret argument to %eax as well.
2270 // Save the argument into a virtual register so that we can access it
2271 // from the return points.
2272 if (MF.getFunction()->hasStructRetAttr() &&
2273 (Subtarget->is64Bit() || Subtarget->isTargetWindows())) {
2274 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
2275 unsigned Reg = FuncInfo->getSRetReturnReg();
2277 MVT PtrTy = getPointerTy();
2278 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(PtrTy));
2279 FuncInfo->setSRetReturnReg(Reg);
2281 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, InVals[0]);
2282 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain);
2285 unsigned StackSize = CCInfo.getNextStackOffset();
2286 // Align stack specially for tail calls.
2287 if (FuncIsMadeTailCallSafe(CallConv,
2288 MF.getTarget().Options.GuaranteedTailCallOpt))
2289 StackSize = GetAlignedArgumentStackSize(StackSize, DAG);
2291 // If the function takes variable number of arguments, make a frame index for
2292 // the start of the first vararg value... for expansion of llvm.va_start.
2294 if (Is64Bit || (CallConv != CallingConv::X86_FastCall &&
2295 CallConv != CallingConv::X86_ThisCall)) {
2296 FuncInfo->setVarArgsFrameIndex(MFI->CreateFixedObject(1, StackSize,true));
2299 unsigned TotalNumIntRegs = 0, TotalNumXMMRegs = 0;
2301 // FIXME: We should really autogenerate these arrays
2302 static const uint16_t GPR64ArgRegsWin64[] = {
2303 X86::RCX, X86::RDX, X86::R8, X86::R9
2305 static const uint16_t GPR64ArgRegs64Bit[] = {
2306 X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9
2308 static const uint16_t XMMArgRegs64Bit[] = {
2309 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
2310 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
2312 const uint16_t *GPR64ArgRegs;
2313 unsigned NumXMMRegs = 0;
2316 // The XMM registers which might contain var arg parameters are shadowed
2317 // in their paired GPR. So we only need to save the GPR to their home
2319 TotalNumIntRegs = 4;
2320 GPR64ArgRegs = GPR64ArgRegsWin64;
2322 TotalNumIntRegs = 6; TotalNumXMMRegs = 8;
2323 GPR64ArgRegs = GPR64ArgRegs64Bit;
2325 NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs64Bit,
2328 unsigned NumIntRegs = CCInfo.getFirstUnallocated(GPR64ArgRegs,
2331 bool NoImplicitFloatOps = Fn->getAttributes().
2332 hasAttribute(AttributeSet::FunctionIndex, Attribute::NoImplicitFloat);
2333 assert(!(NumXMMRegs && !Subtarget->hasSSE1()) &&
2334 "SSE register cannot be used when SSE is disabled!");
2335 assert(!(NumXMMRegs && MF.getTarget().Options.UseSoftFloat &&
2336 NoImplicitFloatOps) &&
2337 "SSE register cannot be used when SSE is disabled!");
2338 if (MF.getTarget().Options.UseSoftFloat || NoImplicitFloatOps ||
2339 !Subtarget->hasSSE1())
2340 // Kernel mode asks for SSE to be disabled, so don't push them
2342 TotalNumXMMRegs = 0;
2345 const TargetFrameLowering &TFI = *getTargetMachine().getFrameLowering();
2346 // Get to the caller-allocated home save location. Add 8 to account
2347 // for the return address.
2348 int HomeOffset = TFI.getOffsetOfLocalArea() + 8;
2349 FuncInfo->setRegSaveFrameIndex(
2350 MFI->CreateFixedObject(1, NumIntRegs * 8 + HomeOffset, false));
2351 // Fixup to set vararg frame on shadow area (4 x i64).
2353 FuncInfo->setVarArgsFrameIndex(FuncInfo->getRegSaveFrameIndex());
2355 // For X86-64, if there are vararg parameters that are passed via
2356 // registers, then we must store them to their spots on the stack so
2357 // they may be loaded by deferencing the result of va_next.
2358 FuncInfo->setVarArgsGPOffset(NumIntRegs * 8);
2359 FuncInfo->setVarArgsFPOffset(TotalNumIntRegs * 8 + NumXMMRegs * 16);
2360 FuncInfo->setRegSaveFrameIndex(
2361 MFI->CreateStackObject(TotalNumIntRegs * 8 + TotalNumXMMRegs * 16, 16,
2365 // Store the integer parameter registers.
2366 SmallVector<SDValue, 8> MemOps;
2367 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
2369 unsigned Offset = FuncInfo->getVarArgsGPOffset();
2370 for (; NumIntRegs != TotalNumIntRegs; ++NumIntRegs) {
2371 SDValue FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), RSFIN,
2372 DAG.getIntPtrConstant(Offset));
2373 unsigned VReg = MF.addLiveIn(GPR64ArgRegs[NumIntRegs],
2374 &X86::GR64RegClass);
2375 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64);
2377 DAG.getStore(Val.getValue(1), dl, Val, FIN,
2378 MachinePointerInfo::getFixedStack(
2379 FuncInfo->getRegSaveFrameIndex(), Offset),
2381 MemOps.push_back(Store);
2385 if (TotalNumXMMRegs != 0 && NumXMMRegs != TotalNumXMMRegs) {
2386 // Now store the XMM (fp + vector) parameter registers.
2387 SmallVector<SDValue, 11> SaveXMMOps;
2388 SaveXMMOps.push_back(Chain);
2390 unsigned AL = MF.addLiveIn(X86::AL, &X86::GR8RegClass);
2391 SDValue ALVal = DAG.getCopyFromReg(DAG.getEntryNode(), dl, AL, MVT::i8);
2392 SaveXMMOps.push_back(ALVal);
2394 SaveXMMOps.push_back(DAG.getIntPtrConstant(
2395 FuncInfo->getRegSaveFrameIndex()));
2396 SaveXMMOps.push_back(DAG.getIntPtrConstant(
2397 FuncInfo->getVarArgsFPOffset()));
2399 for (; NumXMMRegs != TotalNumXMMRegs; ++NumXMMRegs) {
2400 unsigned VReg = MF.addLiveIn(XMMArgRegs64Bit[NumXMMRegs],
2401 &X86::VR128RegClass);
2402 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::v4f32);
2403 SaveXMMOps.push_back(Val);
2405 MemOps.push_back(DAG.getNode(X86ISD::VASTART_SAVE_XMM_REGS, dl,
2407 &SaveXMMOps[0], SaveXMMOps.size()));
2410 if (!MemOps.empty())
2411 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
2412 &MemOps[0], MemOps.size());
2416 // Some CCs need callee pop.
2417 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg,
2418 MF.getTarget().Options.GuaranteedTailCallOpt)) {
2419 FuncInfo->setBytesToPopOnReturn(StackSize); // Callee pops everything.
2421 FuncInfo->setBytesToPopOnReturn(0); // Callee pops nothing.
2422 // If this is an sret function, the return should pop the hidden pointer.
2423 if (!Is64Bit && !IsTailCallConvention(CallConv) && !IsWindows &&
2424 argsAreStructReturn(Ins) == StackStructReturn)
2425 FuncInfo->setBytesToPopOnReturn(4);
2429 // RegSaveFrameIndex is X86-64 only.
2430 FuncInfo->setRegSaveFrameIndex(0xAAAAAAA);
2431 if (CallConv == CallingConv::X86_FastCall ||
2432 CallConv == CallingConv::X86_ThisCall)
2433 // fastcc functions can't have varargs.
2434 FuncInfo->setVarArgsFrameIndex(0xAAAAAAA);
2437 FuncInfo->setArgumentStackSize(StackSize);
2443 X86TargetLowering::LowerMemOpCallTo(SDValue Chain,
2444 SDValue StackPtr, SDValue Arg,
2445 SDLoc dl, SelectionDAG &DAG,
2446 const CCValAssign &VA,
2447 ISD::ArgFlagsTy Flags) const {
2448 unsigned LocMemOffset = VA.getLocMemOffset();
2449 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
2450 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
2451 if (Flags.isByVal())
2452 return CreateCopyOfByValArgument(Arg, PtrOff, Chain, Flags, DAG, dl);
2454 return DAG.getStore(Chain, dl, Arg, PtrOff,
2455 MachinePointerInfo::getStack(LocMemOffset),
2459 /// EmitTailCallLoadRetAddr - Emit a load of return address if tail call
2460 /// optimization is performed and it is required.
2462 X86TargetLowering::EmitTailCallLoadRetAddr(SelectionDAG &DAG,
2463 SDValue &OutRetAddr, SDValue Chain,
2464 bool IsTailCall, bool Is64Bit,
2465 int FPDiff, SDLoc dl) const {
2466 // Adjust the Return address stack slot.
2467 EVT VT = getPointerTy();
2468 OutRetAddr = getReturnAddressFrameIndex(DAG);
2470 // Load the "old" Return address.
2471 OutRetAddr = DAG.getLoad(VT, dl, Chain, OutRetAddr, MachinePointerInfo(),
2472 false, false, false, 0);
2473 return SDValue(OutRetAddr.getNode(), 1);
2476 /// EmitTailCallStoreRetAddr - Emit a store of the return address if tail call
2477 /// optimization is performed and it is required (FPDiff!=0).
2479 EmitTailCallStoreRetAddr(SelectionDAG & DAG, MachineFunction &MF,
2480 SDValue Chain, SDValue RetAddrFrIdx, EVT PtrVT,
2481 unsigned SlotSize, int FPDiff, SDLoc dl) {
2482 // Store the return address to the appropriate stack slot.
2483 if (!FPDiff) return Chain;
2484 // Calculate the new stack slot for the return address.
2485 int NewReturnAddrFI =
2486 MF.getFrameInfo()->CreateFixedObject(SlotSize, (int64_t)FPDiff - SlotSize,
2488 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewReturnAddrFI, PtrVT);
2489 Chain = DAG.getStore(Chain, dl, RetAddrFrIdx, NewRetAddrFrIdx,
2490 MachinePointerInfo::getFixedStack(NewReturnAddrFI),
2496 X86TargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
2497 SmallVectorImpl<SDValue> &InVals) const {
2498 SelectionDAG &DAG = CLI.DAG;
2500 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
2501 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
2502 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
2503 SDValue Chain = CLI.Chain;
2504 SDValue Callee = CLI.Callee;
2505 CallingConv::ID CallConv = CLI.CallConv;
2506 bool &isTailCall = CLI.IsTailCall;
2507 bool isVarArg = CLI.IsVarArg;
2509 MachineFunction &MF = DAG.getMachineFunction();
2510 bool Is64Bit = Subtarget->is64Bit();
2511 bool IsWin64 = Subtarget->isCallingConvWin64(CallConv);
2512 bool IsWindows = Subtarget->isTargetWindows();
2513 StructReturnType SR = callIsStructReturn(Outs);
2514 bool IsSibcall = false;
2516 if (MF.getTarget().Options.DisableTailCalls)
2520 // Check if it's really possible to do a tail call.
2521 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv,
2522 isVarArg, SR != NotStructReturn,
2523 MF.getFunction()->hasStructRetAttr(), CLI.RetTy,
2524 Outs, OutVals, Ins, DAG);
2526 // Sibcalls are automatically detected tailcalls which do not require
2528 if (!MF.getTarget().Options.GuaranteedTailCallOpt && isTailCall)
2535 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
2536 "Var args not supported with calling convention fastcc, ghc or hipe");
2538 // Analyze operands of the call, assigning locations to each operand.
2539 SmallVector<CCValAssign, 16> ArgLocs;
2540 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(),
2541 ArgLocs, *DAG.getContext());
2543 // Allocate shadow area for Win64
2545 CCInfo.AllocateStack(32, 8);
2547 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
2549 // Get a count of how many bytes are to be pushed on the stack.
2550 unsigned NumBytes = CCInfo.getNextStackOffset();
2552 // This is a sibcall. The memory operands are available in caller's
2553 // own caller's stack.
2555 else if (getTargetMachine().Options.GuaranteedTailCallOpt &&
2556 IsTailCallConvention(CallConv))
2557 NumBytes = GetAlignedArgumentStackSize(NumBytes, DAG);
2560 if (isTailCall && !IsSibcall) {
2561 // Lower arguments at fp - stackoffset + fpdiff.
2562 X86MachineFunctionInfo *X86Info = MF.getInfo<X86MachineFunctionInfo>();
2563 unsigned NumBytesCallerPushed = X86Info->getBytesToPopOnReturn();
2565 FPDiff = NumBytesCallerPushed - NumBytes;
2567 // Set the delta of movement of the returnaddr stackslot.
2568 // But only set if delta is greater than previous delta.
2569 if (FPDiff < X86Info->getTCReturnAddrDelta())
2570 X86Info->setTCReturnAddrDelta(FPDiff);
2574 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true),
2577 SDValue RetAddrFrIdx;
2578 // Load return address for tail calls.
2579 if (isTailCall && FPDiff)
2580 Chain = EmitTailCallLoadRetAddr(DAG, RetAddrFrIdx, Chain, isTailCall,
2581 Is64Bit, FPDiff, dl);
2583 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
2584 SmallVector<SDValue, 8> MemOpChains;
2587 // Walk the register/memloc assignments, inserting copies/loads. In the case
2588 // of tail call optimization arguments are handle later.
2589 const X86RegisterInfo *RegInfo =
2590 static_cast<const X86RegisterInfo*>(getTargetMachine().getRegisterInfo());
2591 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2592 CCValAssign &VA = ArgLocs[i];
2593 EVT RegVT = VA.getLocVT();
2594 SDValue Arg = OutVals[i];
2595 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2596 bool isByVal = Flags.isByVal();
2598 // Promote the value if needed.
2599 switch (VA.getLocInfo()) {
2600 default: llvm_unreachable("Unknown loc info!");
2601 case CCValAssign::Full: break;
2602 case CCValAssign::SExt:
2603 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, RegVT, Arg);
2605 case CCValAssign::ZExt:
2606 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, RegVT, Arg);
2608 case CCValAssign::AExt:
2609 if (RegVT.is128BitVector()) {
2610 // Special case: passing MMX values in XMM registers.
2611 Arg = DAG.getNode(ISD::BITCAST, dl, MVT::i64, Arg);
2612 Arg = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, Arg);
2613 Arg = getMOVL(DAG, dl, MVT::v2i64, DAG.getUNDEF(MVT::v2i64), Arg);
2615 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, RegVT, Arg);
2617 case CCValAssign::BCvt:
2618 Arg = DAG.getNode(ISD::BITCAST, dl, RegVT, Arg);
2620 case CCValAssign::Indirect: {
2621 // Store the argument.
2622 SDValue SpillSlot = DAG.CreateStackTemporary(VA.getValVT());
2623 int FI = cast<FrameIndexSDNode>(SpillSlot)->getIndex();
2624 Chain = DAG.getStore(Chain, dl, Arg, SpillSlot,
2625 MachinePointerInfo::getFixedStack(FI),
2632 if (VA.isRegLoc()) {
2633 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
2634 if (isVarArg && IsWin64) {
2635 // Win64 ABI requires argument XMM reg to be copied to the corresponding
2636 // shadow reg if callee is a varargs function.
2637 unsigned ShadowReg = 0;
2638 switch (VA.getLocReg()) {
2639 case X86::XMM0: ShadowReg = X86::RCX; break;
2640 case X86::XMM1: ShadowReg = X86::RDX; break;
2641 case X86::XMM2: ShadowReg = X86::R8; break;
2642 case X86::XMM3: ShadowReg = X86::R9; break;
2645 RegsToPass.push_back(std::make_pair(ShadowReg, Arg));
2647 } else if (!IsSibcall && (!isTailCall || isByVal)) {
2648 assert(VA.isMemLoc());
2649 if (StackPtr.getNode() == 0)
2650 StackPtr = DAG.getCopyFromReg(Chain, dl, RegInfo->getStackRegister(),
2652 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Arg,
2653 dl, DAG, VA, Flags));
2657 if (!MemOpChains.empty())
2658 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
2659 &MemOpChains[0], MemOpChains.size());
2661 if (Subtarget->isPICStyleGOT()) {
2662 // ELF / PIC requires GOT in the EBX register before function calls via PLT
2665 RegsToPass.push_back(std::make_pair(unsigned(X86::EBX),
2666 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), getPointerTy())));
2668 // If we are tail calling and generating PIC/GOT style code load the
2669 // address of the callee into ECX. The value in ecx is used as target of
2670 // the tail jump. This is done to circumvent the ebx/callee-saved problem
2671 // for tail calls on PIC/GOT architectures. Normally we would just put the
2672 // address of GOT into ebx and then call target@PLT. But for tail calls
2673 // ebx would be restored (since ebx is callee saved) before jumping to the
2676 // Note: The actual moving to ECX is done further down.
2677 GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee);
2678 if (G && !G->getGlobal()->hasHiddenVisibility() &&
2679 !G->getGlobal()->hasProtectedVisibility())
2680 Callee = LowerGlobalAddress(Callee, DAG);
2681 else if (isa<ExternalSymbolSDNode>(Callee))
2682 Callee = LowerExternalSymbol(Callee, DAG);
2686 if (Is64Bit && isVarArg && !IsWin64) {
2687 // From AMD64 ABI document:
2688 // For calls that may call functions that use varargs or stdargs
2689 // (prototype-less calls or calls to functions containing ellipsis (...) in
2690 // the declaration) %al is used as hidden argument to specify the number
2691 // of SSE registers used. The contents of %al do not need to match exactly
2692 // the number of registers, but must be an ubound on the number of SSE
2693 // registers used and is in the range 0 - 8 inclusive.
2695 // Count the number of XMM registers allocated.
2696 static const uint16_t XMMArgRegs[] = {
2697 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
2698 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
2700 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs, 8);
2701 assert((Subtarget->hasSSE1() || !NumXMMRegs)
2702 && "SSE registers cannot be used when SSE is disabled");
2704 RegsToPass.push_back(std::make_pair(unsigned(X86::AL),
2705 DAG.getConstant(NumXMMRegs, MVT::i8)));
2708 // For tail calls lower the arguments to the 'real' stack slot.
2710 // Force all the incoming stack arguments to be loaded from the stack
2711 // before any new outgoing arguments are stored to the stack, because the
2712 // outgoing stack slots may alias the incoming argument stack slots, and
2713 // the alias isn't otherwise explicit. This is slightly more conservative
2714 // than necessary, because it means that each store effectively depends
2715 // on every argument instead of just those arguments it would clobber.
2716 SDValue ArgChain = DAG.getStackArgumentTokenFactor(Chain);
2718 SmallVector<SDValue, 8> MemOpChains2;
2721 if (getTargetMachine().Options.GuaranteedTailCallOpt) {
2722 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2723 CCValAssign &VA = ArgLocs[i];
2726 assert(VA.isMemLoc());
2727 SDValue Arg = OutVals[i];
2728 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2729 // Create frame index.
2730 int32_t Offset = VA.getLocMemOffset()+FPDiff;
2731 uint32_t OpSize = (VA.getLocVT().getSizeInBits()+7)/8;
2732 FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true);
2733 FIN = DAG.getFrameIndex(FI, getPointerTy());
2735 if (Flags.isByVal()) {
2736 // Copy relative to framepointer.
2737 SDValue Source = DAG.getIntPtrConstant(VA.getLocMemOffset());
2738 if (StackPtr.getNode() == 0)
2739 StackPtr = DAG.getCopyFromReg(Chain, dl,
2740 RegInfo->getStackRegister(),
2742 Source = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, Source);
2744 MemOpChains2.push_back(CreateCopyOfByValArgument(Source, FIN,
2748 // Store relative to framepointer.
2749 MemOpChains2.push_back(
2750 DAG.getStore(ArgChain, dl, Arg, FIN,
2751 MachinePointerInfo::getFixedStack(FI),
2757 if (!MemOpChains2.empty())
2758 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
2759 &MemOpChains2[0], MemOpChains2.size());
2761 // Store the return address to the appropriate stack slot.
2762 Chain = EmitTailCallStoreRetAddr(DAG, MF, Chain, RetAddrFrIdx,
2763 getPointerTy(), RegInfo->getSlotSize(),
2767 // Build a sequence of copy-to-reg nodes chained together with token chain
2768 // and flag operands which copy the outgoing args into registers.
2770 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
2771 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
2772 RegsToPass[i].second, InFlag);
2773 InFlag = Chain.getValue(1);
2776 if (getTargetMachine().getCodeModel() == CodeModel::Large) {
2777 assert(Is64Bit && "Large code model is only legal in 64-bit mode.");
2778 // In the 64-bit large code model, we have to make all calls
2779 // through a register, since the call instruction's 32-bit
2780 // pc-relative offset may not be large enough to hold the whole
2782 } else if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
2783 // If the callee is a GlobalAddress node (quite common, every direct call
2784 // is) turn it into a TargetGlobalAddress node so that legalize doesn't hack
2787 // We should use extra load for direct calls to dllimported functions in
2789 const GlobalValue *GV = G->getGlobal();
2790 if (!GV->hasDLLImportLinkage()) {
2791 unsigned char OpFlags = 0;
2792 bool ExtraLoad = false;
2793 unsigned WrapperKind = ISD::DELETED_NODE;
2795 // On ELF targets, in both X86-64 and X86-32 mode, direct calls to
2796 // external symbols most go through the PLT in PIC mode. If the symbol
2797 // has hidden or protected visibility, or if it is static or local, then
2798 // we don't need to use the PLT - we can directly call it.
2799 if (Subtarget->isTargetELF() &&
2800 getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
2801 GV->hasDefaultVisibility() && !GV->hasLocalLinkage()) {
2802 OpFlags = X86II::MO_PLT;
2803 } else if (Subtarget->isPICStyleStubAny() &&
2804 (GV->isDeclaration() || GV->isWeakForLinker()) &&
2805 (!Subtarget->getTargetTriple().isMacOSX() ||
2806 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
2807 // PC-relative references to external symbols should go through $stub,
2808 // unless we're building with the leopard linker or later, which
2809 // automatically synthesizes these stubs.
2810 OpFlags = X86II::MO_DARWIN_STUB;
2811 } else if (Subtarget->isPICStyleRIPRel() &&
2812 isa<Function>(GV) &&
2813 cast<Function>(GV)->getAttributes().
2814 hasAttribute(AttributeSet::FunctionIndex,
2815 Attribute::NonLazyBind)) {
2816 // If the function is marked as non-lazy, generate an indirect call
2817 // which loads from the GOT directly. This avoids runtime overhead
2818 // at the cost of eager binding (and one extra byte of encoding).
2819 OpFlags = X86II::MO_GOTPCREL;
2820 WrapperKind = X86ISD::WrapperRIP;
2824 Callee = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(),
2825 G->getOffset(), OpFlags);
2827 // Add a wrapper if needed.
2828 if (WrapperKind != ISD::DELETED_NODE)
2829 Callee = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Callee);
2830 // Add extra indirection if needed.
2832 Callee = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Callee,
2833 MachinePointerInfo::getGOT(),
2834 false, false, false, 0);
2836 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
2837 unsigned char OpFlags = 0;
2839 // On ELF targets, in either X86-64 or X86-32 mode, direct calls to
2840 // external symbols should go through the PLT.
2841 if (Subtarget->isTargetELF() &&
2842 getTargetMachine().getRelocationModel() == Reloc::PIC_) {
2843 OpFlags = X86II::MO_PLT;
2844 } else if (Subtarget->isPICStyleStubAny() &&
2845 (!Subtarget->getTargetTriple().isMacOSX() ||
2846 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
2847 // PC-relative references to external symbols should go through $stub,
2848 // unless we're building with the leopard linker or later, which
2849 // automatically synthesizes these stubs.
2850 OpFlags = X86II::MO_DARWIN_STUB;
2853 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy(),
2857 // Returns a chain & a flag for retval copy to use.
2858 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
2859 SmallVector<SDValue, 8> Ops;
2861 if (!IsSibcall && isTailCall) {
2862 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
2863 DAG.getIntPtrConstant(0, true), InFlag, dl);
2864 InFlag = Chain.getValue(1);
2867 Ops.push_back(Chain);
2868 Ops.push_back(Callee);
2871 Ops.push_back(DAG.getConstant(FPDiff, MVT::i32));
2873 // Add argument registers to the end of the list so that they are known live
2875 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
2876 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
2877 RegsToPass[i].second.getValueType()));
2879 // Add a register mask operand representing the call-preserved registers.
2880 const TargetRegisterInfo *TRI = getTargetMachine().getRegisterInfo();
2881 const uint32_t *Mask = TRI->getCallPreservedMask(CallConv);
2882 assert(Mask && "Missing call preserved mask for calling convention");
2883 Ops.push_back(DAG.getRegisterMask(Mask));
2885 if (InFlag.getNode())
2886 Ops.push_back(InFlag);
2890 //// If this is the first return lowered for this function, add the regs
2891 //// to the liveout set for the function.
2892 // This isn't right, although it's probably harmless on x86; liveouts
2893 // should be computed from returns not tail calls. Consider a void
2894 // function making a tail call to a function returning int.
2895 return DAG.getNode(X86ISD::TC_RETURN, dl, NodeTys, &Ops[0], Ops.size());
2898 Chain = DAG.getNode(X86ISD::CALL, dl, NodeTys, &Ops[0], Ops.size());
2899 InFlag = Chain.getValue(1);
2901 // Create the CALLSEQ_END node.
2902 unsigned NumBytesForCalleeToPush;
2903 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg,
2904 getTargetMachine().Options.GuaranteedTailCallOpt))
2905 NumBytesForCalleeToPush = NumBytes; // Callee pops everything
2906 else if (!Is64Bit && !IsTailCallConvention(CallConv) && !IsWindows &&
2907 SR == StackStructReturn)
2908 // If this is a call to a struct-return function, the callee
2909 // pops the hidden struct pointer, so we have to push it back.
2910 // This is common for Darwin/X86, Linux & Mingw32 targets.
2911 // For MSVC Win32 targets, the caller pops the hidden struct pointer.
2912 NumBytesForCalleeToPush = 4;
2914 NumBytesForCalleeToPush = 0; // Callee pops nothing.
2916 // Returns a flag for retval copy to use.
2918 Chain = DAG.getCALLSEQ_END(Chain,
2919 DAG.getIntPtrConstant(NumBytes, true),
2920 DAG.getIntPtrConstant(NumBytesForCalleeToPush,
2923 InFlag = Chain.getValue(1);
2926 // Handle result values, copying them out of physregs into vregs that we
2928 return LowerCallResult(Chain, InFlag, CallConv, isVarArg,
2929 Ins, dl, DAG, InVals);
2932 //===----------------------------------------------------------------------===//
2933 // Fast Calling Convention (tail call) implementation
2934 //===----------------------------------------------------------------------===//
2936 // Like std call, callee cleans arguments, convention except that ECX is
2937 // reserved for storing the tail called function address. Only 2 registers are
2938 // free for argument passing (inreg). Tail call optimization is performed
2940 // * tailcallopt is enabled
2941 // * caller/callee are fastcc
2942 // On X86_64 architecture with GOT-style position independent code only local
2943 // (within module) calls are supported at the moment.
2944 // To keep the stack aligned according to platform abi the function
2945 // GetAlignedArgumentStackSize ensures that argument delta is always multiples
2946 // of stack alignment. (Dynamic linkers need this - darwin's dyld for example)
2947 // If a tail called function callee has more arguments than the caller the
2948 // caller needs to make sure that there is room to move the RETADDR to. This is
2949 // achieved by reserving an area the size of the argument delta right after the
2950 // original REtADDR, but before the saved framepointer or the spilled registers
2951 // e.g. caller(arg1, arg2) calls callee(arg1, arg2,arg3,arg4)
2963 /// GetAlignedArgumentStackSize - Make the stack size align e.g 16n + 12 aligned
2964 /// for a 16 byte align requirement.
2966 X86TargetLowering::GetAlignedArgumentStackSize(unsigned StackSize,
2967 SelectionDAG& DAG) const {
2968 MachineFunction &MF = DAG.getMachineFunction();
2969 const TargetMachine &TM = MF.getTarget();
2970 const X86RegisterInfo *RegInfo =
2971 static_cast<const X86RegisterInfo*>(TM.getRegisterInfo());
2972 const TargetFrameLowering &TFI = *TM.getFrameLowering();
2973 unsigned StackAlignment = TFI.getStackAlignment();
2974 uint64_t AlignMask = StackAlignment - 1;
2975 int64_t Offset = StackSize;
2976 unsigned SlotSize = RegInfo->getSlotSize();
2977 if ( (Offset & AlignMask) <= (StackAlignment - SlotSize) ) {
2978 // Number smaller than 12 so just add the difference.
2979 Offset += ((StackAlignment - SlotSize) - (Offset & AlignMask));
2981 // Mask out lower bits, add stackalignment once plus the 12 bytes.
2982 Offset = ((~AlignMask) & Offset) + StackAlignment +
2983 (StackAlignment-SlotSize);
2988 /// MatchingStackOffset - Return true if the given stack call argument is
2989 /// already available in the same position (relatively) of the caller's
2990 /// incoming argument stack.
2992 bool MatchingStackOffset(SDValue Arg, unsigned Offset, ISD::ArgFlagsTy Flags,
2993 MachineFrameInfo *MFI, const MachineRegisterInfo *MRI,
2994 const X86InstrInfo *TII) {
2995 unsigned Bytes = Arg.getValueType().getSizeInBits() / 8;
2997 if (Arg.getOpcode() == ISD::CopyFromReg) {
2998 unsigned VR = cast<RegisterSDNode>(Arg.getOperand(1))->getReg();
2999 if (!TargetRegisterInfo::isVirtualRegister(VR))
3001 MachineInstr *Def = MRI->getVRegDef(VR);
3004 if (!Flags.isByVal()) {
3005 if (!TII->isLoadFromStackSlot(Def, FI))
3008 unsigned Opcode = Def->getOpcode();
3009 if ((Opcode == X86::LEA32r || Opcode == X86::LEA64r) &&
3010 Def->getOperand(1).isFI()) {
3011 FI = Def->getOperand(1).getIndex();
3012 Bytes = Flags.getByValSize();
3016 } else if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Arg)) {
3017 if (Flags.isByVal())
3018 // ByVal argument is passed in as a pointer but it's now being
3019 // dereferenced. e.g.
3020 // define @foo(%struct.X* %A) {
3021 // tail call @bar(%struct.X* byval %A)
3024 SDValue Ptr = Ld->getBasePtr();
3025 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr);
3028 FI = FINode->getIndex();
3029 } else if (Arg.getOpcode() == ISD::FrameIndex && Flags.isByVal()) {
3030 FrameIndexSDNode *FINode = cast<FrameIndexSDNode>(Arg);
3031 FI = FINode->getIndex();
3032 Bytes = Flags.getByValSize();
3036 assert(FI != INT_MAX);
3037 if (!MFI->isFixedObjectIndex(FI))
3039 return Offset == MFI->getObjectOffset(FI) && Bytes == MFI->getObjectSize(FI);
3042 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
3043 /// for tail call optimization. Targets which want to do tail call
3044 /// optimization should implement this function.
3046 X86TargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
3047 CallingConv::ID CalleeCC,
3049 bool isCalleeStructRet,
3050 bool isCallerStructRet,
3052 const SmallVectorImpl<ISD::OutputArg> &Outs,
3053 const SmallVectorImpl<SDValue> &OutVals,
3054 const SmallVectorImpl<ISD::InputArg> &Ins,
3055 SelectionDAG &DAG) const {
3056 if (!IsTailCallConvention(CalleeCC) && !IsCCallConvention(CalleeCC))
3059 // If -tailcallopt is specified, make fastcc functions tail-callable.
3060 const MachineFunction &MF = DAG.getMachineFunction();
3061 const Function *CallerF = MF.getFunction();
3063 // If the function return type is x86_fp80 and the callee return type is not,
3064 // then the FP_EXTEND of the call result is not a nop. It's not safe to
3065 // perform a tailcall optimization here.
3066 if (CallerF->getReturnType()->isX86_FP80Ty() && !RetTy->isX86_FP80Ty())
3069 CallingConv::ID CallerCC = CallerF->getCallingConv();
3070 bool CCMatch = CallerCC == CalleeCC;
3071 bool IsCalleeWin64 = Subtarget->isCallingConvWin64(CalleeCC);
3072 bool IsCallerWin64 = Subtarget->isCallingConvWin64(CallerCC);
3074 if (getTargetMachine().Options.GuaranteedTailCallOpt) {
3075 if (IsTailCallConvention(CalleeCC) && CCMatch)
3080 // Look for obvious safe cases to perform tail call optimization that do not
3081 // require ABI changes. This is what gcc calls sibcall.
3083 // Can't do sibcall if stack needs to be dynamically re-aligned. PEI needs to
3084 // emit a special epilogue.
3085 const X86RegisterInfo *RegInfo =
3086 static_cast<const X86RegisterInfo*>(getTargetMachine().getRegisterInfo());
3087 if (RegInfo->needsStackRealignment(MF))
3090 // Also avoid sibcall optimization if either caller or callee uses struct
3091 // return semantics.
3092 if (isCalleeStructRet || isCallerStructRet)
3095 // An stdcall caller is expected to clean up its arguments; the callee
3096 // isn't going to do that.
3097 if (!CCMatch && CallerCC == CallingConv::X86_StdCall)
3100 // Do not sibcall optimize vararg calls unless all arguments are passed via
3102 if (isVarArg && !Outs.empty()) {
3104 // Optimizing for varargs on Win64 is unlikely to be safe without
3105 // additional testing.
3106 if (IsCalleeWin64 || IsCallerWin64)
3109 SmallVector<CCValAssign, 16> ArgLocs;
3110 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(),
3111 getTargetMachine(), ArgLocs, *DAG.getContext());
3113 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
3114 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i)
3115 if (!ArgLocs[i].isRegLoc())
3119 // If the call result is in ST0 / ST1, it needs to be popped off the x87
3120 // stack. Therefore, if it's not used by the call it is not safe to optimize
3121 // this into a sibcall.
3122 bool Unused = false;
3123 for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
3130 SmallVector<CCValAssign, 16> RVLocs;
3131 CCState CCInfo(CalleeCC, false, DAG.getMachineFunction(),
3132 getTargetMachine(), RVLocs, *DAG.getContext());
3133 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
3134 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
3135 CCValAssign &VA = RVLocs[i];
3136 if (VA.getLocReg() == X86::ST0 || VA.getLocReg() == X86::ST1)
3141 // If the calling conventions do not match, then we'd better make sure the
3142 // results are returned in the same way as what the caller expects.
3144 SmallVector<CCValAssign, 16> RVLocs1;
3145 CCState CCInfo1(CalleeCC, false, DAG.getMachineFunction(),
3146 getTargetMachine(), RVLocs1, *DAG.getContext());
3147 CCInfo1.AnalyzeCallResult(Ins, RetCC_X86);
3149 SmallVector<CCValAssign, 16> RVLocs2;
3150 CCState CCInfo2(CallerCC, false, DAG.getMachineFunction(),
3151 getTargetMachine(), RVLocs2, *DAG.getContext());
3152 CCInfo2.AnalyzeCallResult(Ins, RetCC_X86);
3154 if (RVLocs1.size() != RVLocs2.size())
3156 for (unsigned i = 0, e = RVLocs1.size(); i != e; ++i) {
3157 if (RVLocs1[i].isRegLoc() != RVLocs2[i].isRegLoc())
3159 if (RVLocs1[i].getLocInfo() != RVLocs2[i].getLocInfo())
3161 if (RVLocs1[i].isRegLoc()) {
3162 if (RVLocs1[i].getLocReg() != RVLocs2[i].getLocReg())
3165 if (RVLocs1[i].getLocMemOffset() != RVLocs2[i].getLocMemOffset())
3171 // If the callee takes no arguments then go on to check the results of the
3173 if (!Outs.empty()) {
3174 // Check if stack adjustment is needed. For now, do not do this if any
3175 // argument is passed on the stack.
3176 SmallVector<CCValAssign, 16> ArgLocs;
3177 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(),
3178 getTargetMachine(), ArgLocs, *DAG.getContext());
3180 // Allocate shadow area for Win64
3182 CCInfo.AllocateStack(32, 8);
3184 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
3185 if (CCInfo.getNextStackOffset()) {
3186 MachineFunction &MF = DAG.getMachineFunction();
3187 if (MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn())
3190 // Check if the arguments are already laid out in the right way as
3191 // the caller's fixed stack objects.
3192 MachineFrameInfo *MFI = MF.getFrameInfo();
3193 const MachineRegisterInfo *MRI = &MF.getRegInfo();
3194 const X86InstrInfo *TII =
3195 ((const X86TargetMachine&)getTargetMachine()).getInstrInfo();
3196 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3197 CCValAssign &VA = ArgLocs[i];
3198 SDValue Arg = OutVals[i];
3199 ISD::ArgFlagsTy Flags = Outs[i].Flags;
3200 if (VA.getLocInfo() == CCValAssign::Indirect)
3202 if (!VA.isRegLoc()) {
3203 if (!MatchingStackOffset(Arg, VA.getLocMemOffset(), Flags,
3210 // If the tailcall address may be in a register, then make sure it's
3211 // possible to register allocate for it. In 32-bit, the call address can
3212 // only target EAX, EDX, or ECX since the tail call must be scheduled after
3213 // callee-saved registers are restored. These happen to be the same
3214 // registers used to pass 'inreg' arguments so watch out for those.
3215 if (!Subtarget->is64Bit() &&
3216 ((!isa<GlobalAddressSDNode>(Callee) &&
3217 !isa<ExternalSymbolSDNode>(Callee)) ||
3218 getTargetMachine().getRelocationModel() == Reloc::PIC_)) {
3219 unsigned NumInRegs = 0;
3220 // In PIC we need an extra register to formulate the address computation
3222 unsigned MaxInRegs =
3223 (getTargetMachine().getRelocationModel() == Reloc::PIC_) ? 2 : 3;
3225 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3226 CCValAssign &VA = ArgLocs[i];
3229 unsigned Reg = VA.getLocReg();
3232 case X86::EAX: case X86::EDX: case X86::ECX:
3233 if (++NumInRegs == MaxInRegs)
3245 X86TargetLowering::createFastISel(FunctionLoweringInfo &funcInfo,
3246 const TargetLibraryInfo *libInfo) const {
3247 return X86::createFastISel(funcInfo, libInfo);
3250 //===----------------------------------------------------------------------===//
3251 // Other Lowering Hooks
3252 //===----------------------------------------------------------------------===//
3254 static bool MayFoldLoad(SDValue Op) {
3255 return Op.hasOneUse() && ISD::isNormalLoad(Op.getNode());
3258 static bool MayFoldIntoStore(SDValue Op) {
3259 return Op.hasOneUse() && ISD::isNormalStore(*Op.getNode()->use_begin());
3262 static bool isTargetShuffle(unsigned Opcode) {
3264 default: return false;
3265 case X86ISD::PSHUFD:
3266 case X86ISD::PSHUFHW:
3267 case X86ISD::PSHUFLW:
3269 case X86ISD::PALIGNR:
3270 case X86ISD::MOVLHPS:
3271 case X86ISD::MOVLHPD:
3272 case X86ISD::MOVHLPS:
3273 case X86ISD::MOVLPS:
3274 case X86ISD::MOVLPD:
3275 case X86ISD::MOVSHDUP:
3276 case X86ISD::MOVSLDUP:
3277 case X86ISD::MOVDDUP:
3280 case X86ISD::UNPCKL:
3281 case X86ISD::UNPCKH:
3282 case X86ISD::VPERMILP:
3283 case X86ISD::VPERM2X128:
3284 case X86ISD::VPERMI:
3289 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3290 SDValue V1, SelectionDAG &DAG) {
3292 default: llvm_unreachable("Unknown x86 shuffle node");
3293 case X86ISD::MOVSHDUP:
3294 case X86ISD::MOVSLDUP:
3295 case X86ISD::MOVDDUP:
3296 return DAG.getNode(Opc, dl, VT, V1);
3300 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3301 SDValue V1, unsigned TargetMask,
3302 SelectionDAG &DAG) {
3304 default: llvm_unreachable("Unknown x86 shuffle node");
3305 case X86ISD::PSHUFD:
3306 case X86ISD::PSHUFHW:
3307 case X86ISD::PSHUFLW:
3308 case X86ISD::VPERMILP:
3309 case X86ISD::VPERMI:
3310 return DAG.getNode(Opc, dl, VT, V1, DAG.getConstant(TargetMask, MVT::i8));
3314 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3315 SDValue V1, SDValue V2, unsigned TargetMask,
3316 SelectionDAG &DAG) {
3318 default: llvm_unreachable("Unknown x86 shuffle node");
3319 case X86ISD::PALIGNR:
3321 case X86ISD::VPERM2X128:
3322 return DAG.getNode(Opc, dl, VT, V1, V2,
3323 DAG.getConstant(TargetMask, MVT::i8));
3327 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3328 SDValue V1, SDValue V2, SelectionDAG &DAG) {
3330 default: llvm_unreachable("Unknown x86 shuffle node");
3331 case X86ISD::MOVLHPS:
3332 case X86ISD::MOVLHPD:
3333 case X86ISD::MOVHLPS:
3334 case X86ISD::MOVLPS:
3335 case X86ISD::MOVLPD:
3338 case X86ISD::UNPCKL:
3339 case X86ISD::UNPCKH:
3340 return DAG.getNode(Opc, dl, VT, V1, V2);
3344 SDValue X86TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) const {
3345 MachineFunction &MF = DAG.getMachineFunction();
3346 const X86RegisterInfo *RegInfo =
3347 static_cast<const X86RegisterInfo*>(getTargetMachine().getRegisterInfo());
3348 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
3349 int ReturnAddrIndex = FuncInfo->getRAIndex();
3351 if (ReturnAddrIndex == 0) {
3352 // Set up a frame object for the return address.
3353 unsigned SlotSize = RegInfo->getSlotSize();
3354 ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(SlotSize,
3357 FuncInfo->setRAIndex(ReturnAddrIndex);
3360 return DAG.getFrameIndex(ReturnAddrIndex, getPointerTy());
3363 bool X86::isOffsetSuitableForCodeModel(int64_t Offset, CodeModel::Model M,
3364 bool hasSymbolicDisplacement) {
3365 // Offset should fit into 32 bit immediate field.
3366 if (!isInt<32>(Offset))
3369 // If we don't have a symbolic displacement - we don't have any extra
3371 if (!hasSymbolicDisplacement)
3374 // FIXME: Some tweaks might be needed for medium code model.
3375 if (M != CodeModel::Small && M != CodeModel::Kernel)
3378 // For small code model we assume that latest object is 16MB before end of 31
3379 // bits boundary. We may also accept pretty large negative constants knowing
3380 // that all objects are in the positive half of address space.
3381 if (M == CodeModel::Small && Offset < 16*1024*1024)
3384 // For kernel code model we know that all object resist in the negative half
3385 // of 32bits address space. We may not accept negative offsets, since they may
3386 // be just off and we may accept pretty large positive ones.
3387 if (M == CodeModel::Kernel && Offset > 0)
3393 /// isCalleePop - Determines whether the callee is required to pop its
3394 /// own arguments. Callee pop is necessary to support tail calls.
3395 bool X86::isCalleePop(CallingConv::ID CallingConv,
3396 bool is64Bit, bool IsVarArg, bool TailCallOpt) {
3400 switch (CallingConv) {
3403 case CallingConv::X86_StdCall:
3405 case CallingConv::X86_FastCall:
3407 case CallingConv::X86_ThisCall:
3409 case CallingConv::Fast:
3411 case CallingConv::GHC:
3413 case CallingConv::HiPE:
3418 /// TranslateX86CC - do a one to one translation of a ISD::CondCode to the X86
3419 /// specific condition code, returning the condition code and the LHS/RHS of the
3420 /// comparison to make.
3421 static unsigned TranslateX86CC(ISD::CondCode SetCCOpcode, bool isFP,
3422 SDValue &LHS, SDValue &RHS, SelectionDAG &DAG) {
3424 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
3425 if (SetCCOpcode == ISD::SETGT && RHSC->isAllOnesValue()) {
3426 // X > -1 -> X == 0, jump !sign.
3427 RHS = DAG.getConstant(0, RHS.getValueType());
3428 return X86::COND_NS;
3430 if (SetCCOpcode == ISD::SETLT && RHSC->isNullValue()) {
3431 // X < 0 -> X == 0, jump on sign.
3434 if (SetCCOpcode == ISD::SETLT && RHSC->getZExtValue() == 1) {
3436 RHS = DAG.getConstant(0, RHS.getValueType());
3437 return X86::COND_LE;
3441 switch (SetCCOpcode) {
3442 default: llvm_unreachable("Invalid integer condition!");
3443 case ISD::SETEQ: return X86::COND_E;
3444 case ISD::SETGT: return X86::COND_G;
3445 case ISD::SETGE: return X86::COND_GE;
3446 case ISD::SETLT: return X86::COND_L;
3447 case ISD::SETLE: return X86::COND_LE;
3448 case ISD::SETNE: return X86::COND_NE;
3449 case ISD::SETULT: return X86::COND_B;
3450 case ISD::SETUGT: return X86::COND_A;
3451 case ISD::SETULE: return X86::COND_BE;
3452 case ISD::SETUGE: return X86::COND_AE;
3456 // First determine if it is required or is profitable to flip the operands.
3458 // If LHS is a foldable load, but RHS is not, flip the condition.
3459 if (ISD::isNON_EXTLoad(LHS.getNode()) &&
3460 !ISD::isNON_EXTLoad(RHS.getNode())) {
3461 SetCCOpcode = getSetCCSwappedOperands(SetCCOpcode);
3462 std::swap(LHS, RHS);
3465 switch (SetCCOpcode) {
3471 std::swap(LHS, RHS);
3475 // On a floating point condition, the flags are set as follows:
3477 // 0 | 0 | 0 | X > Y
3478 // 0 | 0 | 1 | X < Y
3479 // 1 | 0 | 0 | X == Y
3480 // 1 | 1 | 1 | unordered
3481 switch (SetCCOpcode) {
3482 default: llvm_unreachable("Condcode should be pre-legalized away");
3484 case ISD::SETEQ: return X86::COND_E;
3485 case ISD::SETOLT: // flipped
3487 case ISD::SETGT: return X86::COND_A;
3488 case ISD::SETOLE: // flipped
3490 case ISD::SETGE: return X86::COND_AE;
3491 case ISD::SETUGT: // flipped
3493 case ISD::SETLT: return X86::COND_B;
3494 case ISD::SETUGE: // flipped
3496 case ISD::SETLE: return X86::COND_BE;
3498 case ISD::SETNE: return X86::COND_NE;
3499 case ISD::SETUO: return X86::COND_P;
3500 case ISD::SETO: return X86::COND_NP;
3502 case ISD::SETUNE: return X86::COND_INVALID;
3506 /// hasFPCMov - is there a floating point cmov for the specific X86 condition
3507 /// code. Current x86 isa includes the following FP cmov instructions:
3508 /// fcmovb, fcomvbe, fcomve, fcmovu, fcmovae, fcmova, fcmovne, fcmovnu.
3509 static bool hasFPCMov(unsigned X86CC) {
3525 /// isFPImmLegal - Returns true if the target can instruction select the
3526 /// specified FP immediate natively. If false, the legalizer will
3527 /// materialize the FP immediate as a load from a constant pool.
3528 bool X86TargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
3529 for (unsigned i = 0, e = LegalFPImmediates.size(); i != e; ++i) {
3530 if (Imm.bitwiseIsEqual(LegalFPImmediates[i]))
3536 /// isUndefOrInRange - Return true if Val is undef or if its value falls within
3537 /// the specified range (L, H].
3538 static bool isUndefOrInRange(int Val, int Low, int Hi) {
3539 return (Val < 0) || (Val >= Low && Val < Hi);
3542 /// isUndefOrEqual - Val is either less than zero (undef) or equal to the
3543 /// specified value.
3544 static bool isUndefOrEqual(int Val, int CmpVal) {
3545 return (Val < 0 || Val == CmpVal);
3548 /// isSequentialOrUndefInRange - Return true if every element in Mask, beginning
3549 /// from position Pos and ending in Pos+Size, falls within the specified
3550 /// sequential range (L, L+Pos]. or is undef.
3551 static bool isSequentialOrUndefInRange(ArrayRef<int> Mask,
3552 unsigned Pos, unsigned Size, int Low) {
3553 for (unsigned i = Pos, e = Pos+Size; i != e; ++i, ++Low)
3554 if (!isUndefOrEqual(Mask[i], Low))
3559 /// isPSHUFDMask - Return true if the node specifies a shuffle of elements that
3560 /// is suitable for input to PSHUFD or PSHUFW. That is, it doesn't reference
3561 /// the second operand.
3562 static bool isPSHUFDMask(ArrayRef<int> Mask, MVT VT) {
3563 if (VT == MVT::v4f32 || VT == MVT::v4i32 )
3564 return (Mask[0] < 4 && Mask[1] < 4 && Mask[2] < 4 && Mask[3] < 4);
3565 if (VT == MVT::v2f64 || VT == MVT::v2i64)
3566 return (Mask[0] < 2 && Mask[1] < 2);
3570 /// isPSHUFHWMask - Return true if the node specifies a shuffle of elements that
3571 /// is suitable for input to PSHUFHW.
3572 static bool isPSHUFHWMask(ArrayRef<int> Mask, MVT VT, bool HasInt256) {
3573 if (VT != MVT::v8i16 && (!HasInt256 || VT != MVT::v16i16))
3576 // Lower quadword copied in order or undef.
3577 if (!isSequentialOrUndefInRange(Mask, 0, 4, 0))
3580 // Upper quadword shuffled.
3581 for (unsigned i = 4; i != 8; ++i)
3582 if (!isUndefOrInRange(Mask[i], 4, 8))
3585 if (VT == MVT::v16i16) {
3586 // Lower quadword copied in order or undef.
3587 if (!isSequentialOrUndefInRange(Mask, 8, 4, 8))
3590 // Upper quadword shuffled.
3591 for (unsigned i = 12; i != 16; ++i)
3592 if (!isUndefOrInRange(Mask[i], 12, 16))
3599 /// isPSHUFLWMask - Return true if the node specifies a shuffle of elements that
3600 /// is suitable for input to PSHUFLW.
3601 static bool isPSHUFLWMask(ArrayRef<int> Mask, MVT VT, bool HasInt256) {
3602 if (VT != MVT::v8i16 && (!HasInt256 || VT != MVT::v16i16))
3605 // Upper quadword copied in order.
3606 if (!isSequentialOrUndefInRange(Mask, 4, 4, 4))
3609 // Lower quadword shuffled.
3610 for (unsigned i = 0; i != 4; ++i)
3611 if (!isUndefOrInRange(Mask[i], 0, 4))
3614 if (VT == MVT::v16i16) {
3615 // Upper quadword copied in order.
3616 if (!isSequentialOrUndefInRange(Mask, 12, 4, 12))
3619 // Lower quadword shuffled.
3620 for (unsigned i = 8; i != 12; ++i)
3621 if (!isUndefOrInRange(Mask[i], 8, 12))
3628 /// isPALIGNRMask - Return true if the node specifies a shuffle of elements that
3629 /// is suitable for input to PALIGNR.
3630 static bool isPALIGNRMask(ArrayRef<int> Mask, MVT VT,
3631 const X86Subtarget *Subtarget) {
3632 if ((VT.is128BitVector() && !Subtarget->hasSSSE3()) ||
3633 (VT.is256BitVector() && !Subtarget->hasInt256()))
3636 unsigned NumElts = VT.getVectorNumElements();
3637 unsigned NumLanes = VT.is512BitVector() ? 1: VT.getSizeInBits()/128;
3638 unsigned NumLaneElts = NumElts/NumLanes;
3640 // Do not handle 64-bit element shuffles with palignr.
3641 if (NumLaneElts == 2)
3644 for (unsigned l = 0; l != NumElts; l+=NumLaneElts) {
3646 for (i = 0; i != NumLaneElts; ++i) {
3651 // Lane is all undef, go to next lane
3652 if (i == NumLaneElts)
3655 int Start = Mask[i+l];
3657 // Make sure its in this lane in one of the sources
3658 if (!isUndefOrInRange(Start, l, l+NumLaneElts) &&
3659 !isUndefOrInRange(Start, l+NumElts, l+NumElts+NumLaneElts))
3662 // If not lane 0, then we must match lane 0
3663 if (l != 0 && Mask[i] >= 0 && !isUndefOrEqual(Start, Mask[i]+l))
3666 // Correct second source to be contiguous with first source
3667 if (Start >= (int)NumElts)
3668 Start -= NumElts - NumLaneElts;
3670 // Make sure we're shifting in the right direction.
3671 if (Start <= (int)(i+l))
3676 // Check the rest of the elements to see if they are consecutive.
3677 for (++i; i != NumLaneElts; ++i) {
3678 int Idx = Mask[i+l];
3680 // Make sure its in this lane
3681 if (!isUndefOrInRange(Idx, l, l+NumLaneElts) &&
3682 !isUndefOrInRange(Idx, l+NumElts, l+NumElts+NumLaneElts))
3685 // If not lane 0, then we must match lane 0
3686 if (l != 0 && Mask[i] >= 0 && !isUndefOrEqual(Idx, Mask[i]+l))
3689 if (Idx >= (int)NumElts)
3690 Idx -= NumElts - NumLaneElts;
3692 if (!isUndefOrEqual(Idx, Start+i))
3701 /// CommuteVectorShuffleMask - Change values in a shuffle permute mask assuming
3702 /// the two vector operands have swapped position.
3703 static void CommuteVectorShuffleMask(SmallVectorImpl<int> &Mask,
3704 unsigned NumElems) {
3705 for (unsigned i = 0; i != NumElems; ++i) {
3709 else if (idx < (int)NumElems)
3710 Mask[i] = idx + NumElems;
3712 Mask[i] = idx - NumElems;
3716 /// isSHUFPMask - Return true if the specified VECTOR_SHUFFLE operand
3717 /// specifies a shuffle of elements that is suitable for input to 128/256-bit
3718 /// SHUFPS and SHUFPD. If Commuted is true, then it checks for sources to be
3719 /// reverse of what x86 shuffles want.
3720 static bool isSHUFPMask(ArrayRef<int> Mask, MVT VT, bool Commuted = false) {
3722 unsigned NumElems = VT.getVectorNumElements();
3723 unsigned NumLanes = VT.getSizeInBits()/128;
3724 unsigned NumLaneElems = NumElems/NumLanes;
3726 if (NumLaneElems != 2 && NumLaneElems != 4)
3729 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
3730 bool symetricMaskRequired =
3731 (VT.getSizeInBits() >= 256) && (EltSize == 32);
3733 // VSHUFPSY divides the resulting vector into 4 chunks.
3734 // The sources are also splitted into 4 chunks, and each destination
3735 // chunk must come from a different source chunk.
3737 // SRC1 => X7 X6 X5 X4 X3 X2 X1 X0
3738 // SRC2 => Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y9
3740 // DST => Y7..Y4, Y7..Y4, X7..X4, X7..X4,
3741 // Y3..Y0, Y3..Y0, X3..X0, X3..X0
3743 // VSHUFPDY divides the resulting vector into 4 chunks.
3744 // The sources are also splitted into 4 chunks, and each destination
3745 // chunk must come from a different source chunk.
3747 // SRC1 => X3 X2 X1 X0
3748 // SRC2 => Y3 Y2 Y1 Y0
3750 // DST => Y3..Y2, X3..X2, Y1..Y0, X1..X0
3752 SmallVector<int, 4> MaskVal(NumLaneElems, -1);
3753 unsigned HalfLaneElems = NumLaneElems/2;
3754 for (unsigned l = 0; l != NumElems; l += NumLaneElems) {
3755 for (unsigned i = 0; i != NumLaneElems; ++i) {
3756 int Idx = Mask[i+l];
3757 unsigned RngStart = l + ((Commuted == (i<HalfLaneElems)) ? NumElems : 0);
3758 if (!isUndefOrInRange(Idx, RngStart, RngStart+NumLaneElems))
3760 // For VSHUFPSY, the mask of the second half must be the same as the
3761 // first but with the appropriate offsets. This works in the same way as
3762 // VPERMILPS works with masks.
3763 if (!symetricMaskRequired || Idx < 0)
3765 if (MaskVal[i] < 0) {
3766 MaskVal[i] = Idx - l;
3769 if ((signed)(Idx - l) != MaskVal[i])
3777 /// isMOVHLPSMask - Return true if the specified VECTOR_SHUFFLE operand
3778 /// specifies a shuffle of elements that is suitable for input to MOVHLPS.
3779 static bool isMOVHLPSMask(ArrayRef<int> Mask, MVT VT) {
3780 if (!VT.is128BitVector())
3783 unsigned NumElems = VT.getVectorNumElements();
3788 // Expect bit0 == 6, bit1 == 7, bit2 == 2, bit3 == 3
3789 return isUndefOrEqual(Mask[0], 6) &&
3790 isUndefOrEqual(Mask[1], 7) &&
3791 isUndefOrEqual(Mask[2], 2) &&
3792 isUndefOrEqual(Mask[3], 3);
3795 /// isMOVHLPS_v_undef_Mask - Special case of isMOVHLPSMask for canonical form
3796 /// of vector_shuffle v, v, <2, 3, 2, 3>, i.e. vector_shuffle v, undef,
3798 static bool isMOVHLPS_v_undef_Mask(ArrayRef<int> Mask, MVT VT) {
3799 if (!VT.is128BitVector())
3802 unsigned NumElems = VT.getVectorNumElements();
3807 return isUndefOrEqual(Mask[0], 2) &&
3808 isUndefOrEqual(Mask[1], 3) &&
3809 isUndefOrEqual(Mask[2], 2) &&
3810 isUndefOrEqual(Mask[3], 3);
3813 /// isMOVLPMask - Return true if the specified VECTOR_SHUFFLE operand
3814 /// specifies a shuffle of elements that is suitable for input to MOVLP{S|D}.
3815 static bool isMOVLPMask(ArrayRef<int> Mask, MVT VT) {
3816 if (!VT.is128BitVector())
3819 unsigned NumElems = VT.getVectorNumElements();
3821 if (NumElems != 2 && NumElems != 4)
3824 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
3825 if (!isUndefOrEqual(Mask[i], i + NumElems))
3828 for (unsigned i = NumElems/2, e = NumElems; i != e; ++i)
3829 if (!isUndefOrEqual(Mask[i], i))
3835 /// isMOVLHPSMask - Return true if the specified VECTOR_SHUFFLE operand
3836 /// specifies a shuffle of elements that is suitable for input to MOVLHPS.
3837 static bool isMOVLHPSMask(ArrayRef<int> Mask, MVT VT) {
3838 if (!VT.is128BitVector())
3841 unsigned NumElems = VT.getVectorNumElements();
3843 if (NumElems != 2 && NumElems != 4)
3846 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
3847 if (!isUndefOrEqual(Mask[i], i))
3850 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
3851 if (!isUndefOrEqual(Mask[i + e], i + NumElems))
3858 // Some special combinations that can be optimized.
3861 SDValue Compact8x32ShuffleNode(ShuffleVectorSDNode *SVOp,
3862 SelectionDAG &DAG) {
3863 MVT VT = SVOp->getSimpleValueType(0);
3866 if (VT != MVT::v8i32 && VT != MVT::v8f32)
3869 ArrayRef<int> Mask = SVOp->getMask();
3871 // These are the special masks that may be optimized.
3872 static const int MaskToOptimizeEven[] = {0, 8, 2, 10, 4, 12, 6, 14};
3873 static const int MaskToOptimizeOdd[] = {1, 9, 3, 11, 5, 13, 7, 15};
3874 bool MatchEvenMask = true;
3875 bool MatchOddMask = true;
3876 for (int i=0; i<8; ++i) {
3877 if (!isUndefOrEqual(Mask[i], MaskToOptimizeEven[i]))
3878 MatchEvenMask = false;
3879 if (!isUndefOrEqual(Mask[i], MaskToOptimizeOdd[i]))
3880 MatchOddMask = false;
3883 if (!MatchEvenMask && !MatchOddMask)
3886 SDValue UndefNode = DAG.getNode(ISD::UNDEF, dl, VT);
3888 SDValue Op0 = SVOp->getOperand(0);
3889 SDValue Op1 = SVOp->getOperand(1);
3891 if (MatchEvenMask) {
3892 // Shift the second operand right to 32 bits.
3893 static const int ShiftRightMask[] = {-1, 0, -1, 2, -1, 4, -1, 6 };
3894 Op1 = DAG.getVectorShuffle(VT, dl, Op1, UndefNode, ShiftRightMask);
3896 // Shift the first operand left to 32 bits.
3897 static const int ShiftLeftMask[] = {1, -1, 3, -1, 5, -1, 7, -1 };
3898 Op0 = DAG.getVectorShuffle(VT, dl, Op0, UndefNode, ShiftLeftMask);
3900 static const int BlendMask[] = {0, 9, 2, 11, 4, 13, 6, 15};
3901 return DAG.getVectorShuffle(VT, dl, Op0, Op1, BlendMask);
3904 /// isUNPCKLMask - Return true if the specified VECTOR_SHUFFLE operand
3905 /// specifies a shuffle of elements that is suitable for input to UNPCKL.
3906 static bool isUNPCKLMask(ArrayRef<int> Mask, MVT VT,
3907 bool HasInt256, bool V2IsSplat = false) {
3909 assert(VT.getSizeInBits() >= 128 &&
3910 "Unsupported vector type for unpckl");
3912 // AVX defines UNPCK* to operate independently on 128-bit lanes.
3914 unsigned NumOf256BitLanes;
3915 unsigned NumElts = VT.getVectorNumElements();
3916 if (VT.is256BitVector()) {
3917 if (NumElts != 4 && NumElts != 8 &&
3918 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
3921 NumOf256BitLanes = 1;
3922 } else if (VT.is512BitVector()) {
3923 assert(VT.getScalarType().getSizeInBits() >= 32 &&
3924 "Unsupported vector type for unpckh");
3926 NumOf256BitLanes = 2;
3929 NumOf256BitLanes = 1;
3932 unsigned NumEltsInStride = NumElts/NumOf256BitLanes;
3933 unsigned NumLaneElts = NumEltsInStride/NumLanes;
3935 for (unsigned l256 = 0; l256 < NumOf256BitLanes; l256 += 1) {
3936 for (unsigned l = 0; l != NumEltsInStride; l += NumLaneElts) {
3937 for (unsigned i = 0, j = l; i != NumLaneElts; i += 2, ++j) {
3938 int BitI = Mask[l256*NumEltsInStride+l+i];
3939 int BitI1 = Mask[l256*NumEltsInStride+l+i+1];
3940 if (!isUndefOrEqual(BitI, j+l256*NumElts))
3942 if (V2IsSplat && !isUndefOrEqual(BitI1, NumElts))
3944 if (!isUndefOrEqual(BitI1, j+l256*NumElts+NumEltsInStride))
3952 /// isUNPCKHMask - Return true if the specified VECTOR_SHUFFLE operand
3953 /// specifies a shuffle of elements that is suitable for input to UNPCKH.
3954 static bool isUNPCKHMask(ArrayRef<int> Mask, MVT VT,
3955 bool HasInt256, bool V2IsSplat = false) {
3956 assert(VT.getSizeInBits() >= 128 &&
3957 "Unsupported vector type for unpckh");
3959 // AVX defines UNPCK* to operate independently on 128-bit lanes.
3961 unsigned NumOf256BitLanes;
3962 unsigned NumElts = VT.getVectorNumElements();
3963 if (VT.is256BitVector()) {
3964 if (NumElts != 4 && NumElts != 8 &&
3965 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
3968 NumOf256BitLanes = 1;
3969 } else if (VT.is512BitVector()) {
3970 assert(VT.getScalarType().getSizeInBits() >= 32 &&
3971 "Unsupported vector type for unpckh");
3973 NumOf256BitLanes = 2;
3976 NumOf256BitLanes = 1;
3979 unsigned NumEltsInStride = NumElts/NumOf256BitLanes;
3980 unsigned NumLaneElts = NumEltsInStride/NumLanes;
3982 for (unsigned l256 = 0; l256 < NumOf256BitLanes; l256 += 1) {
3983 for (unsigned l = 0; l != NumEltsInStride; l += NumLaneElts) {
3984 for (unsigned i = 0, j = l+NumLaneElts/2; i != NumLaneElts; i += 2, ++j) {
3985 int BitI = Mask[l256*NumEltsInStride+l+i];
3986 int BitI1 = Mask[l256*NumEltsInStride+l+i+1];
3987 if (!isUndefOrEqual(BitI, j+l256*NumElts))
3989 if (V2IsSplat && !isUndefOrEqual(BitI1, NumElts))
3991 if (!isUndefOrEqual(BitI1, j+l256*NumElts+NumEltsInStride))
3999 /// isUNPCKL_v_undef_Mask - Special case of isUNPCKLMask for canonical form
4000 /// of vector_shuffle v, v, <0, 4, 1, 5>, i.e. vector_shuffle v, undef,
4002 static bool isUNPCKL_v_undef_Mask(ArrayRef<int> Mask, MVT VT, bool HasInt256) {
4003 unsigned NumElts = VT.getVectorNumElements();
4004 bool Is256BitVec = VT.is256BitVector();
4006 if (VT.is512BitVector())
4008 assert((VT.is128BitVector() || VT.is256BitVector()) &&
4009 "Unsupported vector type for unpckh");
4011 if (Is256BitVec && NumElts != 4 && NumElts != 8 &&
4012 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
4015 // For 256-bit i64/f64, use MOVDDUPY instead, so reject the matching pattern
4016 // FIXME: Need a better way to get rid of this, there's no latency difference
4017 // between UNPCKLPD and MOVDDUP, the later should always be checked first and
4018 // the former later. We should also remove the "_undef" special mask.
4019 if (NumElts == 4 && Is256BitVec)
4022 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
4023 // independently on 128-bit lanes.
4024 unsigned NumLanes = VT.getSizeInBits()/128;
4025 unsigned NumLaneElts = NumElts/NumLanes;
4027 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
4028 for (unsigned i = 0, j = l; i != NumLaneElts; i += 2, ++j) {
4029 int BitI = Mask[l+i];
4030 int BitI1 = Mask[l+i+1];
4032 if (!isUndefOrEqual(BitI, j))
4034 if (!isUndefOrEqual(BitI1, j))
4042 /// isUNPCKH_v_undef_Mask - Special case of isUNPCKHMask for canonical form
4043 /// of vector_shuffle v, v, <2, 6, 3, 7>, i.e. vector_shuffle v, undef,
4045 static bool isUNPCKH_v_undef_Mask(ArrayRef<int> Mask, MVT VT, bool HasInt256) {
4046 unsigned NumElts = VT.getVectorNumElements();
4048 if (VT.is512BitVector())
4051 assert((VT.is128BitVector() || VT.is256BitVector()) &&
4052 "Unsupported vector type for unpckh");
4054 if (VT.is256BitVector() && NumElts != 4 && NumElts != 8 &&
4055 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
4058 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
4059 // independently on 128-bit lanes.
4060 unsigned NumLanes = VT.getSizeInBits()/128;
4061 unsigned NumLaneElts = NumElts/NumLanes;
4063 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
4064 for (unsigned i = 0, j = l+NumLaneElts/2; i != NumLaneElts; i += 2, ++j) {
4065 int BitI = Mask[l+i];
4066 int BitI1 = Mask[l+i+1];
4067 if (!isUndefOrEqual(BitI, j))
4069 if (!isUndefOrEqual(BitI1, j))
4076 /// isMOVLMask - Return true if the specified VECTOR_SHUFFLE operand
4077 /// specifies a shuffle of elements that is suitable for input to MOVSS,
4078 /// MOVSD, and MOVD, i.e. setting the lowest element.
4079 static bool isMOVLMask(ArrayRef<int> Mask, EVT VT) {
4080 if (VT.getVectorElementType().getSizeInBits() < 32)
4082 if (!VT.is128BitVector())
4085 unsigned NumElts = VT.getVectorNumElements();
4087 if (!isUndefOrEqual(Mask[0], NumElts))
4090 for (unsigned i = 1; i != NumElts; ++i)
4091 if (!isUndefOrEqual(Mask[i], i))
4097 /// isVPERM2X128Mask - Match 256-bit shuffles where the elements are considered
4098 /// as permutations between 128-bit chunks or halves. As an example: this
4100 /// vector_shuffle <4, 5, 6, 7, 12, 13, 14, 15>
4101 /// The first half comes from the second half of V1 and the second half from the
4102 /// the second half of V2.
4103 static bool isVPERM2X128Mask(ArrayRef<int> Mask, MVT VT, bool HasFp256) {
4104 if (!HasFp256 || !VT.is256BitVector())
4107 // The shuffle result is divided into half A and half B. In total the two
4108 // sources have 4 halves, namely: C, D, E, F. The final values of A and
4109 // B must come from C, D, E or F.
4110 unsigned HalfSize = VT.getVectorNumElements()/2;
4111 bool MatchA = false, MatchB = false;
4113 // Check if A comes from one of C, D, E, F.
4114 for (unsigned Half = 0; Half != 4; ++Half) {
4115 if (isSequentialOrUndefInRange(Mask, 0, HalfSize, Half*HalfSize)) {
4121 // Check if B comes from one of C, D, E, F.
4122 for (unsigned Half = 0; Half != 4; ++Half) {
4123 if (isSequentialOrUndefInRange(Mask, HalfSize, HalfSize, Half*HalfSize)) {
4129 return MatchA && MatchB;
4132 /// getShuffleVPERM2X128Immediate - Return the appropriate immediate to shuffle
4133 /// the specified VECTOR_MASK mask with VPERM2F128/VPERM2I128 instructions.
4134 static unsigned getShuffleVPERM2X128Immediate(ShuffleVectorSDNode *SVOp) {
4135 MVT VT = SVOp->getSimpleValueType(0);
4137 unsigned HalfSize = VT.getVectorNumElements()/2;
4139 unsigned FstHalf = 0, SndHalf = 0;
4140 for (unsigned i = 0; i < HalfSize; ++i) {
4141 if (SVOp->getMaskElt(i) > 0) {
4142 FstHalf = SVOp->getMaskElt(i)/HalfSize;
4146 for (unsigned i = HalfSize; i < HalfSize*2; ++i) {
4147 if (SVOp->getMaskElt(i) > 0) {
4148 SndHalf = SVOp->getMaskElt(i)/HalfSize;
4153 return (FstHalf | (SndHalf << 4));
4156 // Symetric in-lane mask. Each lane has 4 elements (for imm8)
4157 static bool isPermImmMask(ArrayRef<int> Mask, MVT VT, unsigned& Imm8) {
4158 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
4162 unsigned NumElts = VT.getVectorNumElements();
4164 if (VT.is128BitVector() || (VT.is256BitVector() && EltSize == 64)) {
4165 for (unsigned i = 0; i != NumElts; ++i) {
4168 Imm8 |= Mask[i] << (i*2);
4173 unsigned LaneSize = 4;
4174 SmallVector<int, 4> MaskVal(LaneSize, -1);
4176 for (unsigned l = 0; l != NumElts; l += LaneSize) {
4177 for (unsigned i = 0; i != LaneSize; ++i) {
4178 if (!isUndefOrInRange(Mask[i+l], l, l+LaneSize))
4182 if (MaskVal[i] < 0) {
4183 MaskVal[i] = Mask[i+l] - l;
4184 Imm8 |= MaskVal[i] << (i*2);
4187 if (Mask[i+l] != (signed)(MaskVal[i]+l))
4194 /// isVPERMILPMask - Return true if the specified VECTOR_SHUFFLE operand
4195 /// specifies a shuffle of elements that is suitable for input to VPERMILPD*.
4196 /// Note that VPERMIL mask matching is different depending whether theunderlying
4197 /// type is 32 or 64. In the VPERMILPS the high half of the mask should point
4198 /// to the same elements of the low, but to the higher half of the source.
4199 /// In VPERMILPD the two lanes could be shuffled independently of each other
4200 /// with the same restriction that lanes can't be crossed. Also handles PSHUFDY.
4201 static bool isVPERMILPMask(ArrayRef<int> Mask, MVT VT) {
4202 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
4203 if (VT.getSizeInBits() < 256 || EltSize < 32)
4205 bool symetricMaskRequired = (EltSize == 32);
4206 unsigned NumElts = VT.getVectorNumElements();
4208 unsigned NumLanes = VT.getSizeInBits()/128;
4209 unsigned LaneSize = NumElts/NumLanes;
4210 // 2 or 4 elements in one lane
4212 SmallVector<int, 4> ExpectedMaskVal(LaneSize, -1);
4213 for (unsigned l = 0; l != NumElts; l += LaneSize) {
4214 for (unsigned i = 0; i != LaneSize; ++i) {
4215 if (!isUndefOrInRange(Mask[i+l], l, l+LaneSize))
4217 if (symetricMaskRequired) {
4218 if (ExpectedMaskVal[i] < 0 && Mask[i+l] >= 0) {
4219 ExpectedMaskVal[i] = Mask[i+l] - l;
4222 if (!isUndefOrEqual(Mask[i+l], ExpectedMaskVal[i]+l))
4230 /// isCommutedMOVLMask - Returns true if the shuffle mask is except the reverse
4231 /// of what x86 movss want. X86 movs requires the lowest element to be lowest
4232 /// element of vector 2 and the other elements to come from vector 1 in order.
4233 static bool isCommutedMOVLMask(ArrayRef<int> Mask, MVT VT,
4234 bool V2IsSplat = false, bool V2IsUndef = false) {
4235 if (!VT.is128BitVector())
4238 unsigned NumOps = VT.getVectorNumElements();
4239 if (NumOps != 2 && NumOps != 4 && NumOps != 8 && NumOps != 16)
4242 if (!isUndefOrEqual(Mask[0], 0))
4245 for (unsigned i = 1; i != NumOps; ++i)
4246 if (!(isUndefOrEqual(Mask[i], i+NumOps) ||
4247 (V2IsUndef && isUndefOrInRange(Mask[i], NumOps, NumOps*2)) ||
4248 (V2IsSplat && isUndefOrEqual(Mask[i], NumOps))))
4254 /// isMOVSHDUPMask - Return true if the specified VECTOR_SHUFFLE operand
4255 /// specifies a shuffle of elements that is suitable for input to MOVSHDUP.
4256 /// Masks to match: <1, 1, 3, 3> or <1, 1, 3, 3, 5, 5, 7, 7>
4257 static bool isMOVSHDUPMask(ArrayRef<int> Mask, MVT VT,
4258 const X86Subtarget *Subtarget) {
4259 if (!Subtarget->hasSSE3())
4262 unsigned NumElems = VT.getVectorNumElements();
4264 if ((VT.is128BitVector() && NumElems != 4) ||
4265 (VT.is256BitVector() && NumElems != 8) ||
4266 (VT.is512BitVector() && NumElems != 16))
4269 // "i+1" is the value the indexed mask element must have
4270 for (unsigned i = 0; i != NumElems; i += 2)
4271 if (!isUndefOrEqual(Mask[i], i+1) ||
4272 !isUndefOrEqual(Mask[i+1], i+1))
4278 /// isMOVSLDUPMask - Return true if the specified VECTOR_SHUFFLE operand
4279 /// specifies a shuffle of elements that is suitable for input to MOVSLDUP.
4280 /// Masks to match: <0, 0, 2, 2> or <0, 0, 2, 2, 4, 4, 6, 6>
4281 static bool isMOVSLDUPMask(ArrayRef<int> Mask, MVT VT,
4282 const X86Subtarget *Subtarget) {
4283 if (!Subtarget->hasSSE3())
4286 unsigned NumElems = VT.getVectorNumElements();
4288 if ((VT.is128BitVector() && NumElems != 4) ||
4289 (VT.is256BitVector() && NumElems != 8) ||
4290 (VT.is512BitVector() && NumElems != 16))
4293 // "i" is the value the indexed mask element must have
4294 for (unsigned i = 0; i != NumElems; i += 2)
4295 if (!isUndefOrEqual(Mask[i], i) ||
4296 !isUndefOrEqual(Mask[i+1], i))
4302 /// isMOVDDUPYMask - Return true if the specified VECTOR_SHUFFLE operand
4303 /// specifies a shuffle of elements that is suitable for input to 256-bit
4304 /// version of MOVDDUP.
4305 static bool isMOVDDUPYMask(ArrayRef<int> Mask, MVT VT, bool HasFp256) {
4306 if (!HasFp256 || !VT.is256BitVector())
4309 unsigned NumElts = VT.getVectorNumElements();
4313 for (unsigned i = 0; i != NumElts/2; ++i)
4314 if (!isUndefOrEqual(Mask[i], 0))
4316 for (unsigned i = NumElts/2; i != NumElts; ++i)
4317 if (!isUndefOrEqual(Mask[i], NumElts/2))
4322 /// isMOVDDUPMask - Return true if the specified VECTOR_SHUFFLE operand
4323 /// specifies a shuffle of elements that is suitable for input to 128-bit
4324 /// version of MOVDDUP.
4325 static bool isMOVDDUPMask(ArrayRef<int> Mask, MVT VT) {
4326 if (!VT.is128BitVector())
4329 unsigned e = VT.getVectorNumElements() / 2;
4330 for (unsigned i = 0; i != e; ++i)
4331 if (!isUndefOrEqual(Mask[i], i))
4333 for (unsigned i = 0; i != e; ++i)
4334 if (!isUndefOrEqual(Mask[e+i], i))
4339 /// isVEXTRACTIndex - Return true if the specified
4340 /// EXTRACT_SUBVECTOR operand specifies a vector extract that is
4341 /// suitable for instruction that extract 128 or 256 bit vectors
4342 static bool isVEXTRACTIndex(SDNode *N, unsigned vecWidth) {
4343 assert((vecWidth == 128 || vecWidth == 256) && "Unexpected vector width");
4344 if (!isa<ConstantSDNode>(N->getOperand(1).getNode()))
4347 // The index should be aligned on a vecWidth-bit boundary.
4349 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
4351 MVT VT = N->getSimpleValueType(0);
4352 unsigned ElSize = VT.getVectorElementType().getSizeInBits();
4353 bool Result = (Index * ElSize) % vecWidth == 0;
4358 /// isVINSERTIndex - Return true if the specified INSERT_SUBVECTOR
4359 /// operand specifies a subvector insert that is suitable for input to
4360 /// insertion of 128 or 256-bit subvectors
4361 static bool isVINSERTIndex(SDNode *N, unsigned vecWidth) {
4362 assert((vecWidth == 128 || vecWidth == 256) && "Unexpected vector width");
4363 if (!isa<ConstantSDNode>(N->getOperand(2).getNode()))
4365 // The index should be aligned on a vecWidth-bit boundary.
4367 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
4369 MVT VT = N->getSimpleValueType(0);
4370 unsigned ElSize = VT.getVectorElementType().getSizeInBits();
4371 bool Result = (Index * ElSize) % vecWidth == 0;
4376 bool X86::isVINSERT128Index(SDNode *N) {
4377 return isVINSERTIndex(N, 128);
4380 bool X86::isVINSERT256Index(SDNode *N) {
4381 return isVINSERTIndex(N, 256);
4384 bool X86::isVEXTRACT128Index(SDNode *N) {
4385 return isVEXTRACTIndex(N, 128);
4388 bool X86::isVEXTRACT256Index(SDNode *N) {
4389 return isVEXTRACTIndex(N, 256);
4392 /// getShuffleSHUFImmediate - Return the appropriate immediate to shuffle
4393 /// the specified VECTOR_SHUFFLE mask with PSHUF* and SHUFP* instructions.
4394 /// Handles 128-bit and 256-bit.
4395 static unsigned getShuffleSHUFImmediate(ShuffleVectorSDNode *N) {
4396 MVT VT = N->getSimpleValueType(0);
4398 assert((VT.getSizeInBits() >= 128) &&
4399 "Unsupported vector type for PSHUF/SHUFP");
4401 // Handle 128 and 256-bit vector lengths. AVX defines PSHUF/SHUFP to operate
4402 // independently on 128-bit lanes.
4403 unsigned NumElts = VT.getVectorNumElements();
4404 unsigned NumLanes = VT.getSizeInBits()/128;
4405 unsigned NumLaneElts = NumElts/NumLanes;
4407 assert((NumLaneElts == 2 || NumLaneElts == 4 || NumLaneElts == 8) &&
4408 "Only supports 2, 4 or 8 elements per lane");
4410 unsigned Shift = (NumLaneElts >= 4) ? 1 : 0;
4412 for (unsigned i = 0; i != NumElts; ++i) {
4413 int Elt = N->getMaskElt(i);
4414 if (Elt < 0) continue;
4415 Elt &= NumLaneElts - 1;
4416 unsigned ShAmt = (i << Shift) % 8;
4417 Mask |= Elt << ShAmt;
4423 /// getShufflePSHUFHWImmediate - Return the appropriate immediate to shuffle
4424 /// the specified VECTOR_SHUFFLE mask with the PSHUFHW instruction.
4425 static unsigned getShufflePSHUFHWImmediate(ShuffleVectorSDNode *N) {
4426 MVT VT = N->getSimpleValueType(0);
4428 assert((VT == MVT::v8i16 || VT == MVT::v16i16) &&
4429 "Unsupported vector type for PSHUFHW");
4431 unsigned NumElts = VT.getVectorNumElements();
4434 for (unsigned l = 0; l != NumElts; l += 8) {
4435 // 8 nodes per lane, but we only care about the last 4.
4436 for (unsigned i = 0; i < 4; ++i) {
4437 int Elt = N->getMaskElt(l+i+4);
4438 if (Elt < 0) continue;
4439 Elt &= 0x3; // only 2-bits.
4440 Mask |= Elt << (i * 2);
4447 /// getShufflePSHUFLWImmediate - Return the appropriate immediate to shuffle
4448 /// the specified VECTOR_SHUFFLE mask with the PSHUFLW instruction.
4449 static unsigned getShufflePSHUFLWImmediate(ShuffleVectorSDNode *N) {
4450 MVT VT = N->getSimpleValueType(0);
4452 assert((VT == MVT::v8i16 || VT == MVT::v16i16) &&
4453 "Unsupported vector type for PSHUFHW");
4455 unsigned NumElts = VT.getVectorNumElements();
4458 for (unsigned l = 0; l != NumElts; l += 8) {
4459 // 8 nodes per lane, but we only care about the first 4.
4460 for (unsigned i = 0; i < 4; ++i) {
4461 int Elt = N->getMaskElt(l+i);
4462 if (Elt < 0) continue;
4463 Elt &= 0x3; // only 2-bits
4464 Mask |= Elt << (i * 2);
4471 /// getShufflePALIGNRImmediate - Return the appropriate immediate to shuffle
4472 /// the specified VECTOR_SHUFFLE mask with the PALIGNR instruction.
4473 static unsigned getShufflePALIGNRImmediate(ShuffleVectorSDNode *SVOp) {
4474 MVT VT = SVOp->getSimpleValueType(0);
4475 unsigned EltSize = VT.is512BitVector() ? 1 :
4476 VT.getVectorElementType().getSizeInBits() >> 3;
4478 unsigned NumElts = VT.getVectorNumElements();
4479 unsigned NumLanes = VT.is512BitVector() ? 1 : VT.getSizeInBits()/128;
4480 unsigned NumLaneElts = NumElts/NumLanes;
4484 for (i = 0; i != NumElts; ++i) {
4485 Val = SVOp->getMaskElt(i);
4489 if (Val >= (int)NumElts)
4490 Val -= NumElts - NumLaneElts;
4492 assert(Val - i > 0 && "PALIGNR imm should be positive");
4493 return (Val - i) * EltSize;
4496 static unsigned getExtractVEXTRACTImmediate(SDNode *N, unsigned vecWidth) {
4497 assert((vecWidth == 128 || vecWidth == 256) && "Unsupported vector width");
4498 if (!isa<ConstantSDNode>(N->getOperand(1).getNode()))
4499 llvm_unreachable("Illegal extract subvector for VEXTRACT");
4502 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
4504 MVT VecVT = N->getOperand(0).getSimpleValueType();
4505 MVT ElVT = VecVT.getVectorElementType();
4507 unsigned NumElemsPerChunk = vecWidth / ElVT.getSizeInBits();
4508 return Index / NumElemsPerChunk;
4511 static unsigned getInsertVINSERTImmediate(SDNode *N, unsigned vecWidth) {
4512 assert((vecWidth == 128 || vecWidth == 256) && "Unsupported vector width");
4513 if (!isa<ConstantSDNode>(N->getOperand(2).getNode()))
4514 llvm_unreachable("Illegal insert subvector for VINSERT");
4517 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
4519 MVT VecVT = N->getSimpleValueType(0);
4520 MVT ElVT = VecVT.getVectorElementType();
4522 unsigned NumElemsPerChunk = vecWidth / ElVT.getSizeInBits();
4523 return Index / NumElemsPerChunk;
4526 /// getExtractVEXTRACT128Immediate - Return the appropriate immediate
4527 /// to extract the specified EXTRACT_SUBVECTOR index with VEXTRACTF128
4528 /// and VINSERTI128 instructions.
4529 unsigned X86::getExtractVEXTRACT128Immediate(SDNode *N) {
4530 return getExtractVEXTRACTImmediate(N, 128);
4533 /// getExtractVEXTRACT256Immediate - Return the appropriate immediate
4534 /// to extract the specified EXTRACT_SUBVECTOR index with VEXTRACTF64x4
4535 /// and VINSERTI64x4 instructions.
4536 unsigned X86::getExtractVEXTRACT256Immediate(SDNode *N) {
4537 return getExtractVEXTRACTImmediate(N, 256);
4540 /// getInsertVINSERT128Immediate - Return the appropriate immediate
4541 /// to insert at the specified INSERT_SUBVECTOR index with VINSERTF128
4542 /// and VINSERTI128 instructions.
4543 unsigned X86::getInsertVINSERT128Immediate(SDNode *N) {
4544 return getInsertVINSERTImmediate(N, 128);
4547 /// getInsertVINSERT256Immediate - Return the appropriate immediate
4548 /// to insert at the specified INSERT_SUBVECTOR index with VINSERTF46x4
4549 /// and VINSERTI64x4 instructions.
4550 unsigned X86::getInsertVINSERT256Immediate(SDNode *N) {
4551 return getInsertVINSERTImmediate(N, 256);
4554 /// isZeroNode - Returns true if Elt is a constant zero or a floating point
4556 bool X86::isZeroNode(SDValue Elt) {
4557 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Elt))
4558 return CN->isNullValue();
4559 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Elt))
4560 return CFP->getValueAPF().isPosZero();
4564 /// CommuteVectorShuffle - Swap vector_shuffle operands as well as values in
4565 /// their permute mask.
4566 static SDValue CommuteVectorShuffle(ShuffleVectorSDNode *SVOp,
4567 SelectionDAG &DAG) {
4568 MVT VT = SVOp->getSimpleValueType(0);
4569 unsigned NumElems = VT.getVectorNumElements();
4570 SmallVector<int, 8> MaskVec;
4572 for (unsigned i = 0; i != NumElems; ++i) {
4573 int Idx = SVOp->getMaskElt(i);
4575 if (Idx < (int)NumElems)
4580 MaskVec.push_back(Idx);
4582 return DAG.getVectorShuffle(VT, SDLoc(SVOp), SVOp->getOperand(1),
4583 SVOp->getOperand(0), &MaskVec[0]);
4586 /// ShouldXformToMOVHLPS - Return true if the node should be transformed to
4587 /// match movhlps. The lower half elements should come from upper half of
4588 /// V1 (and in order), and the upper half elements should come from the upper
4589 /// half of V2 (and in order).
4590 static bool ShouldXformToMOVHLPS(ArrayRef<int> Mask, MVT VT) {
4591 if (!VT.is128BitVector())
4593 if (VT.getVectorNumElements() != 4)
4595 for (unsigned i = 0, e = 2; i != e; ++i)
4596 if (!isUndefOrEqual(Mask[i], i+2))
4598 for (unsigned i = 2; i != 4; ++i)
4599 if (!isUndefOrEqual(Mask[i], i+4))
4604 /// isScalarLoadToVector - Returns true if the node is a scalar load that
4605 /// is promoted to a vector. It also returns the LoadSDNode by reference if
4607 static bool isScalarLoadToVector(SDNode *N, LoadSDNode **LD = NULL) {
4608 if (N->getOpcode() != ISD::SCALAR_TO_VECTOR)
4610 N = N->getOperand(0).getNode();
4611 if (!ISD::isNON_EXTLoad(N))
4614 *LD = cast<LoadSDNode>(N);
4618 // Test whether the given value is a vector value which will be legalized
4620 static bool WillBeConstantPoolLoad(SDNode *N) {
4621 if (N->getOpcode() != ISD::BUILD_VECTOR)
4624 // Check for any non-constant elements.
4625 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
4626 switch (N->getOperand(i).getNode()->getOpcode()) {
4628 case ISD::ConstantFP:
4635 // Vectors of all-zeros and all-ones are materialized with special
4636 // instructions rather than being loaded.
4637 return !ISD::isBuildVectorAllZeros(N) &&
4638 !ISD::isBuildVectorAllOnes(N);
4641 /// ShouldXformToMOVLP{S|D} - Return true if the node should be transformed to
4642 /// match movlp{s|d}. The lower half elements should come from lower half of
4643 /// V1 (and in order), and the upper half elements should come from the upper
4644 /// half of V2 (and in order). And since V1 will become the source of the
4645 /// MOVLP, it must be either a vector load or a scalar load to vector.
4646 static bool ShouldXformToMOVLP(SDNode *V1, SDNode *V2,
4647 ArrayRef<int> Mask, MVT VT) {
4648 if (!VT.is128BitVector())
4651 if (!ISD::isNON_EXTLoad(V1) && !isScalarLoadToVector(V1))
4653 // Is V2 is a vector load, don't do this transformation. We will try to use
4654 // load folding shufps op.
4655 if (ISD::isNON_EXTLoad(V2) || WillBeConstantPoolLoad(V2))
4658 unsigned NumElems = VT.getVectorNumElements();
4660 if (NumElems != 2 && NumElems != 4)
4662 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
4663 if (!isUndefOrEqual(Mask[i], i))
4665 for (unsigned i = NumElems/2, e = NumElems; i != e; ++i)
4666 if (!isUndefOrEqual(Mask[i], i+NumElems))
4671 /// isSplatVector - Returns true if N is a BUILD_VECTOR node whose elements are
4673 static bool isSplatVector(SDNode *N) {
4674 if (N->getOpcode() != ISD::BUILD_VECTOR)
4677 SDValue SplatValue = N->getOperand(0);
4678 for (unsigned i = 1, e = N->getNumOperands(); i != e; ++i)
4679 if (N->getOperand(i) != SplatValue)
4684 /// isZeroShuffle - Returns true if N is a VECTOR_SHUFFLE that can be resolved
4685 /// to an zero vector.
4686 /// FIXME: move to dag combiner / method on ShuffleVectorSDNode
4687 static bool isZeroShuffle(ShuffleVectorSDNode *N) {
4688 SDValue V1 = N->getOperand(0);
4689 SDValue V2 = N->getOperand(1);
4690 unsigned NumElems = N->getValueType(0).getVectorNumElements();
4691 for (unsigned i = 0; i != NumElems; ++i) {
4692 int Idx = N->getMaskElt(i);
4693 if (Idx >= (int)NumElems) {
4694 unsigned Opc = V2.getOpcode();
4695 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V2.getNode()))
4697 if (Opc != ISD::BUILD_VECTOR ||
4698 !X86::isZeroNode(V2.getOperand(Idx-NumElems)))
4700 } else if (Idx >= 0) {
4701 unsigned Opc = V1.getOpcode();
4702 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V1.getNode()))
4704 if (Opc != ISD::BUILD_VECTOR ||
4705 !X86::isZeroNode(V1.getOperand(Idx)))
4712 /// getZeroVector - Returns a vector of specified type with all zero elements.
4714 static SDValue getZeroVector(EVT VT, const X86Subtarget *Subtarget,
4715 SelectionDAG &DAG, SDLoc dl) {
4716 assert(VT.isVector() && "Expected a vector type");
4718 // Always build SSE zero vectors as <4 x i32> bitcasted
4719 // to their dest type. This ensures they get CSE'd.
4721 if (VT.is128BitVector()) { // SSE
4722 if (Subtarget->hasSSE2()) { // SSE2
4723 SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
4724 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4726 SDValue Cst = DAG.getTargetConstantFP(+0.0, MVT::f32);
4727 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4f32, Cst, Cst, Cst, Cst);
4729 } else if (VT.is256BitVector()) { // AVX
4730 if (Subtarget->hasInt256()) { // AVX2
4731 SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
4732 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4733 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops,
4734 array_lengthof(Ops));
4736 // 256-bit logic and arithmetic instructions in AVX are all
4737 // floating-point, no support for integer ops. Emit fp zeroed vectors.
4738 SDValue Cst = DAG.getTargetConstantFP(+0.0, MVT::f32);
4739 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4740 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8f32, Ops,
4741 array_lengthof(Ops));
4743 } else if (VT.is512BitVector()) { // AVX-512
4744 SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
4745 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst,
4746 Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4747 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v16i32, Ops, 16);
4749 llvm_unreachable("Unexpected vector type");
4751 return DAG.getNode(ISD::BITCAST, dl, VT, Vec);
4754 /// getOnesVector - Returns a vector of specified type with all bits set.
4755 /// Always build ones vectors as <4 x i32> or <8 x i32>. For 256-bit types with
4756 /// no AVX2 supprt, use two <4 x i32> inserted in a <8 x i32> appropriately.
4757 /// Then bitcast to their original type, ensuring they get CSE'd.
4758 static SDValue getOnesVector(MVT VT, bool HasInt256, SelectionDAG &DAG,
4760 assert(VT.isVector() && "Expected a vector type");
4762 SDValue Cst = DAG.getTargetConstant(~0U, MVT::i32);
4764 if (VT.is256BitVector()) {
4765 if (HasInt256) { // AVX2
4766 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4767 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops,
4768 array_lengthof(Ops));
4770 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4771 Vec = Concat128BitVectors(Vec, Vec, MVT::v8i32, 8, DAG, dl);
4773 } else if (VT.is128BitVector()) {
4774 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4776 llvm_unreachable("Unexpected vector type");
4778 return DAG.getNode(ISD::BITCAST, dl, VT, Vec);
4781 /// NormalizeMask - V2 is a splat, modify the mask (if needed) so all elements
4782 /// that point to V2 points to its first element.
4783 static void NormalizeMask(SmallVectorImpl<int> &Mask, unsigned NumElems) {
4784 for (unsigned i = 0; i != NumElems; ++i) {
4785 if (Mask[i] > (int)NumElems) {
4791 /// getMOVLMask - Returns a vector_shuffle mask for an movs{s|d}, movd
4792 /// operation of specified width.
4793 static SDValue getMOVL(SelectionDAG &DAG, SDLoc dl, EVT VT, SDValue V1,
4795 unsigned NumElems = VT.getVectorNumElements();
4796 SmallVector<int, 8> Mask;
4797 Mask.push_back(NumElems);
4798 for (unsigned i = 1; i != NumElems; ++i)
4800 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
4803 /// getUnpackl - Returns a vector_shuffle node for an unpackl operation.
4804 static SDValue getUnpackl(SelectionDAG &DAG, SDLoc dl, MVT VT, SDValue V1,
4806 unsigned NumElems = VT.getVectorNumElements();
4807 SmallVector<int, 8> Mask;
4808 for (unsigned i = 0, e = NumElems/2; i != e; ++i) {
4810 Mask.push_back(i + NumElems);
4812 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
4815 /// getUnpackh - Returns a vector_shuffle node for an unpackh operation.
4816 static SDValue getUnpackh(SelectionDAG &DAG, SDLoc dl, MVT VT, SDValue V1,
4818 unsigned NumElems = VT.getVectorNumElements();
4819 SmallVector<int, 8> Mask;
4820 for (unsigned i = 0, Half = NumElems/2; i != Half; ++i) {
4821 Mask.push_back(i + Half);
4822 Mask.push_back(i + NumElems + Half);
4824 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
4827 // PromoteSplati8i16 - All i16 and i8 vector types can't be used directly by
4828 // a generic shuffle instruction because the target has no such instructions.
4829 // Generate shuffles which repeat i16 and i8 several times until they can be
4830 // represented by v4f32 and then be manipulated by target suported shuffles.
4831 static SDValue PromoteSplati8i16(SDValue V, SelectionDAG &DAG, int &EltNo) {
4832 MVT VT = V.getSimpleValueType();
4833 int NumElems = VT.getVectorNumElements();
4836 while (NumElems > 4) {
4837 if (EltNo < NumElems/2) {
4838 V = getUnpackl(DAG, dl, VT, V, V);
4840 V = getUnpackh(DAG, dl, VT, V, V);
4841 EltNo -= NumElems/2;
4848 /// getLegalSplat - Generate a legal splat with supported x86 shuffles
4849 static SDValue getLegalSplat(SelectionDAG &DAG, SDValue V, int EltNo) {
4850 MVT VT = V.getSimpleValueType();
4853 if (VT.is128BitVector()) {
4854 V = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V);
4855 int SplatMask[4] = { EltNo, EltNo, EltNo, EltNo };
4856 V = DAG.getVectorShuffle(MVT::v4f32, dl, V, DAG.getUNDEF(MVT::v4f32),
4858 } else if (VT.is256BitVector()) {
4859 // To use VPERMILPS to splat scalars, the second half of indicies must
4860 // refer to the higher part, which is a duplication of the lower one,
4861 // because VPERMILPS can only handle in-lane permutations.
4862 int SplatMask[8] = { EltNo, EltNo, EltNo, EltNo,
4863 EltNo+4, EltNo+4, EltNo+4, EltNo+4 };
4865 V = DAG.getNode(ISD::BITCAST, dl, MVT::v8f32, V);
4866 V = DAG.getVectorShuffle(MVT::v8f32, dl, V, DAG.getUNDEF(MVT::v8f32),
4869 llvm_unreachable("Vector size not supported");
4871 return DAG.getNode(ISD::BITCAST, dl, VT, V);
4874 /// PromoteSplat - Splat is promoted to target supported vector shuffles.
4875 static SDValue PromoteSplat(ShuffleVectorSDNode *SV, SelectionDAG &DAG) {
4876 MVT SrcVT = SV->getSimpleValueType(0);
4877 SDValue V1 = SV->getOperand(0);
4880 int EltNo = SV->getSplatIndex();
4881 int NumElems = SrcVT.getVectorNumElements();
4882 bool Is256BitVec = SrcVT.is256BitVector();
4884 assert(((SrcVT.is128BitVector() && NumElems > 4) || Is256BitVec) &&
4885 "Unknown how to promote splat for type");
4887 // Extract the 128-bit part containing the splat element and update
4888 // the splat element index when it refers to the higher register.
4890 V1 = Extract128BitVector(V1, EltNo, DAG, dl);
4891 if (EltNo >= NumElems/2)
4892 EltNo -= NumElems/2;
4895 // All i16 and i8 vector types can't be used directly by a generic shuffle
4896 // instruction because the target has no such instruction. Generate shuffles
4897 // which repeat i16 and i8 several times until they fit in i32, and then can
4898 // be manipulated by target suported shuffles.
4899 MVT EltVT = SrcVT.getVectorElementType();
4900 if (EltVT == MVT::i8 || EltVT == MVT::i16)
4901 V1 = PromoteSplati8i16(V1, DAG, EltNo);
4903 // Recreate the 256-bit vector and place the same 128-bit vector
4904 // into the low and high part. This is necessary because we want
4905 // to use VPERM* to shuffle the vectors
4907 V1 = DAG.getNode(ISD::CONCAT_VECTORS, dl, SrcVT, V1, V1);
4910 return getLegalSplat(DAG, V1, EltNo);
4913 /// getShuffleVectorZeroOrUndef - Return a vector_shuffle of the specified
4914 /// vector of zero or undef vector. This produces a shuffle where the low
4915 /// element of V2 is swizzled into the zero/undef vector, landing at element
4916 /// Idx. This produces a shuffle mask like 4,1,2,3 (idx=0) or 0,1,2,4 (idx=3).
4917 static SDValue getShuffleVectorZeroOrUndef(SDValue V2, unsigned Idx,
4919 const X86Subtarget *Subtarget,
4920 SelectionDAG &DAG) {
4921 MVT VT = V2.getSimpleValueType();
4923 ? getZeroVector(VT, Subtarget, DAG, SDLoc(V2)) : DAG.getUNDEF(VT);
4924 unsigned NumElems = VT.getVectorNumElements();
4925 SmallVector<int, 16> MaskVec;
4926 for (unsigned i = 0; i != NumElems; ++i)
4927 // If this is the insertion idx, put the low elt of V2 here.
4928 MaskVec.push_back(i == Idx ? NumElems : i);
4929 return DAG.getVectorShuffle(VT, SDLoc(V2), V1, V2, &MaskVec[0]);
4932 /// getTargetShuffleMask - Calculates the shuffle mask corresponding to the
4933 /// target specific opcode. Returns true if the Mask could be calculated.
4934 /// Sets IsUnary to true if only uses one source.
4935 static bool getTargetShuffleMask(SDNode *N, MVT VT,
4936 SmallVectorImpl<int> &Mask, bool &IsUnary) {
4937 unsigned NumElems = VT.getVectorNumElements();
4941 switch(N->getOpcode()) {
4943 ImmN = N->getOperand(N->getNumOperands()-1);
4944 DecodeSHUFPMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4946 case X86ISD::UNPCKH:
4947 DecodeUNPCKHMask(VT, Mask);
4949 case X86ISD::UNPCKL:
4950 DecodeUNPCKLMask(VT, Mask);
4952 case X86ISD::MOVHLPS:
4953 DecodeMOVHLPSMask(NumElems, Mask);
4955 case X86ISD::MOVLHPS:
4956 DecodeMOVLHPSMask(NumElems, Mask);
4958 case X86ISD::PALIGNR:
4959 ImmN = N->getOperand(N->getNumOperands()-1);
4960 DecodePALIGNRMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4962 case X86ISD::PSHUFD:
4963 case X86ISD::VPERMILP:
4964 ImmN = N->getOperand(N->getNumOperands()-1);
4965 DecodePSHUFMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4968 case X86ISD::PSHUFHW:
4969 ImmN = N->getOperand(N->getNumOperands()-1);
4970 DecodePSHUFHWMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4973 case X86ISD::PSHUFLW:
4974 ImmN = N->getOperand(N->getNumOperands()-1);
4975 DecodePSHUFLWMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4978 case X86ISD::VPERMI:
4979 ImmN = N->getOperand(N->getNumOperands()-1);
4980 DecodeVPERMMask(cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4984 case X86ISD::MOVSD: {
4985 // The index 0 always comes from the first element of the second source,
4986 // this is why MOVSS and MOVSD are used in the first place. The other
4987 // elements come from the other positions of the first source vector
4988 Mask.push_back(NumElems);
4989 for (unsigned i = 1; i != NumElems; ++i) {
4994 case X86ISD::VPERM2X128:
4995 ImmN = N->getOperand(N->getNumOperands()-1);
4996 DecodeVPERM2X128Mask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4997 if (Mask.empty()) return false;
4999 case X86ISD::MOVDDUP:
5000 case X86ISD::MOVLHPD:
5001 case X86ISD::MOVLPD:
5002 case X86ISD::MOVLPS:
5003 case X86ISD::MOVSHDUP:
5004 case X86ISD::MOVSLDUP:
5005 // Not yet implemented
5007 default: llvm_unreachable("unknown target shuffle node");
5013 /// getShuffleScalarElt - Returns the scalar element that will make up the ith
5014 /// element of the result of the vector shuffle.
5015 static SDValue getShuffleScalarElt(SDNode *N, unsigned Index, SelectionDAG &DAG,
5018 return SDValue(); // Limit search depth.
5020 SDValue V = SDValue(N, 0);
5021 EVT VT = V.getValueType();
5022 unsigned Opcode = V.getOpcode();
5024 // Recurse into ISD::VECTOR_SHUFFLE node to find scalars.
5025 if (const ShuffleVectorSDNode *SV = dyn_cast<ShuffleVectorSDNode>(N)) {
5026 int Elt = SV->getMaskElt(Index);
5029 return DAG.getUNDEF(VT.getVectorElementType());
5031 unsigned NumElems = VT.getVectorNumElements();
5032 SDValue NewV = (Elt < (int)NumElems) ? SV->getOperand(0)
5033 : SV->getOperand(1);
5034 return getShuffleScalarElt(NewV.getNode(), Elt % NumElems, DAG, Depth+1);
5037 // Recurse into target specific vector shuffles to find scalars.
5038 if (isTargetShuffle(Opcode)) {
5039 MVT ShufVT = V.getSimpleValueType();
5040 unsigned NumElems = ShufVT.getVectorNumElements();
5041 SmallVector<int, 16> ShuffleMask;
5044 if (!getTargetShuffleMask(N, ShufVT, ShuffleMask, IsUnary))
5047 int Elt = ShuffleMask[Index];
5049 return DAG.getUNDEF(ShufVT.getVectorElementType());
5051 SDValue NewV = (Elt < (int)NumElems) ? N->getOperand(0)
5053 return getShuffleScalarElt(NewV.getNode(), Elt % NumElems, DAG,
5057 // Actual nodes that may contain scalar elements
5058 if (Opcode == ISD::BITCAST) {
5059 V = V.getOperand(0);
5060 EVT SrcVT = V.getValueType();
5061 unsigned NumElems = VT.getVectorNumElements();
5063 if (!SrcVT.isVector() || SrcVT.getVectorNumElements() != NumElems)
5067 if (V.getOpcode() == ISD::SCALAR_TO_VECTOR)
5068 return (Index == 0) ? V.getOperand(0)
5069 : DAG.getUNDEF(VT.getVectorElementType());
5071 if (V.getOpcode() == ISD::BUILD_VECTOR)
5072 return V.getOperand(Index);
5077 /// getNumOfConsecutiveZeros - Return the number of elements of a vector
5078 /// shuffle operation which come from a consecutively from a zero. The
5079 /// search can start in two different directions, from left or right.
5080 /// We count undefs as zeros until PreferredNum is reached.
5081 static unsigned getNumOfConsecutiveZeros(ShuffleVectorSDNode *SVOp,
5082 unsigned NumElems, bool ZerosFromLeft,
5084 unsigned PreferredNum = -1U) {
5085 unsigned NumZeros = 0;
5086 for (unsigned i = 0; i != NumElems; ++i) {
5087 unsigned Index = ZerosFromLeft ? i : NumElems - i - 1;
5088 SDValue Elt = getShuffleScalarElt(SVOp, Index, DAG, 0);
5092 if (X86::isZeroNode(Elt))
5094 else if (Elt.getOpcode() == ISD::UNDEF) // Undef as zero up to PreferredNum.
5095 NumZeros = std::min(NumZeros + 1, PreferredNum);
5103 /// isShuffleMaskConsecutive - Check if the shuffle mask indicies [MaskI, MaskE)
5104 /// correspond consecutively to elements from one of the vector operands,
5105 /// starting from its index OpIdx. Also tell OpNum which source vector operand.
5107 bool isShuffleMaskConsecutive(ShuffleVectorSDNode *SVOp,
5108 unsigned MaskI, unsigned MaskE, unsigned OpIdx,
5109 unsigned NumElems, unsigned &OpNum) {
5110 bool SeenV1 = false;
5111 bool SeenV2 = false;
5113 for (unsigned i = MaskI; i != MaskE; ++i, ++OpIdx) {
5114 int Idx = SVOp->getMaskElt(i);
5115 // Ignore undef indicies
5119 if (Idx < (int)NumElems)
5124 // Only accept consecutive elements from the same vector
5125 if ((Idx % NumElems != OpIdx) || (SeenV1 && SeenV2))
5129 OpNum = SeenV1 ? 0 : 1;
5133 /// isVectorShiftRight - Returns true if the shuffle can be implemented as a
5134 /// logical left shift of a vector.
5135 static bool isVectorShiftRight(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
5136 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
5138 SVOp->getSimpleValueType(0).getVectorNumElements();
5139 unsigned NumZeros = getNumOfConsecutiveZeros(
5140 SVOp, NumElems, false /* check zeros from right */, DAG,
5141 SVOp->getMaskElt(0));
5147 // Considering the elements in the mask that are not consecutive zeros,
5148 // check if they consecutively come from only one of the source vectors.
5150 // V1 = {X, A, B, C} 0
5152 // vector_shuffle V1, V2 <1, 2, 3, X>
5154 if (!isShuffleMaskConsecutive(SVOp,
5155 0, // Mask Start Index
5156 NumElems-NumZeros, // Mask End Index(exclusive)
5157 NumZeros, // Where to start looking in the src vector
5158 NumElems, // Number of elements in vector
5159 OpSrc)) // Which source operand ?
5164 ShVal = SVOp->getOperand(OpSrc);
5168 /// isVectorShiftLeft - Returns true if the shuffle can be implemented as a
5169 /// logical left shift of a vector.
5170 static bool isVectorShiftLeft(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
5171 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
5173 SVOp->getSimpleValueType(0).getVectorNumElements();
5174 unsigned NumZeros = getNumOfConsecutiveZeros(
5175 SVOp, NumElems, true /* check zeros from left */, DAG,
5176 NumElems - SVOp->getMaskElt(NumElems - 1) - 1);
5182 // Considering the elements in the mask that are not consecutive zeros,
5183 // check if they consecutively come from only one of the source vectors.
5185 // 0 { A, B, X, X } = V2
5187 // vector_shuffle V1, V2 <X, X, 4, 5>
5189 if (!isShuffleMaskConsecutive(SVOp,
5190 NumZeros, // Mask Start Index
5191 NumElems, // Mask End Index(exclusive)
5192 0, // Where to start looking in the src vector
5193 NumElems, // Number of elements in vector
5194 OpSrc)) // Which source operand ?
5199 ShVal = SVOp->getOperand(OpSrc);
5203 /// isVectorShift - Returns true if the shuffle can be implemented as a
5204 /// logical left or right shift of a vector.
5205 static bool isVectorShift(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
5206 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
5207 // Although the logic below support any bitwidth size, there are no
5208 // shift instructions which handle more than 128-bit vectors.
5209 if (!SVOp->getSimpleValueType(0).is128BitVector())
5212 if (isVectorShiftLeft(SVOp, DAG, isLeft, ShVal, ShAmt) ||
5213 isVectorShiftRight(SVOp, DAG, isLeft, ShVal, ShAmt))
5219 /// LowerBuildVectorv16i8 - Custom lower build_vector of v16i8.
5221 static SDValue LowerBuildVectorv16i8(SDValue Op, unsigned NonZeros,
5222 unsigned NumNonZero, unsigned NumZero,
5224 const X86Subtarget* Subtarget,
5225 const TargetLowering &TLI) {
5232 for (unsigned i = 0; i < 16; ++i) {
5233 bool ThisIsNonZero = (NonZeros & (1 << i)) != 0;
5234 if (ThisIsNonZero && First) {
5236 V = getZeroVector(MVT::v8i16, Subtarget, DAG, dl);
5238 V = DAG.getUNDEF(MVT::v8i16);
5243 SDValue ThisElt(0, 0), LastElt(0, 0);
5244 bool LastIsNonZero = (NonZeros & (1 << (i-1))) != 0;
5245 if (LastIsNonZero) {
5246 LastElt = DAG.getNode(ISD::ZERO_EXTEND, dl,
5247 MVT::i16, Op.getOperand(i-1));
5249 if (ThisIsNonZero) {
5250 ThisElt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, Op.getOperand(i));
5251 ThisElt = DAG.getNode(ISD::SHL, dl, MVT::i16,
5252 ThisElt, DAG.getConstant(8, MVT::i8));
5254 ThisElt = DAG.getNode(ISD::OR, dl, MVT::i16, ThisElt, LastElt);
5258 if (ThisElt.getNode())
5259 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, V, ThisElt,
5260 DAG.getIntPtrConstant(i/2));
5264 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V);
5267 /// LowerBuildVectorv8i16 - Custom lower build_vector of v8i16.
5269 static SDValue LowerBuildVectorv8i16(SDValue Op, unsigned NonZeros,
5270 unsigned NumNonZero, unsigned NumZero,
5272 const X86Subtarget* Subtarget,
5273 const TargetLowering &TLI) {
5280 for (unsigned i = 0; i < 8; ++i) {
5281 bool isNonZero = (NonZeros & (1 << i)) != 0;
5285 V = getZeroVector(MVT::v8i16, Subtarget, DAG, dl);
5287 V = DAG.getUNDEF(MVT::v8i16);
5290 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl,
5291 MVT::v8i16, V, Op.getOperand(i),
5292 DAG.getIntPtrConstant(i));
5299 /// getVShift - Return a vector logical shift node.
5301 static SDValue getVShift(bool isLeft, EVT VT, SDValue SrcOp,
5302 unsigned NumBits, SelectionDAG &DAG,
5303 const TargetLowering &TLI, SDLoc dl) {
5304 assert(VT.is128BitVector() && "Unknown type for VShift");
5305 EVT ShVT = MVT::v2i64;
5306 unsigned Opc = isLeft ? X86ISD::VSHLDQ : X86ISD::VSRLDQ;
5307 SrcOp = DAG.getNode(ISD::BITCAST, dl, ShVT, SrcOp);
5308 return DAG.getNode(ISD::BITCAST, dl, VT,
5309 DAG.getNode(Opc, dl, ShVT, SrcOp,
5310 DAG.getConstant(NumBits,
5311 TLI.getScalarShiftAmountTy(SrcOp.getValueType()))));
5315 LowerAsSplatVectorLoad(SDValue SrcOp, MVT VT, SDLoc dl, SelectionDAG &DAG) {
5317 // Check if the scalar load can be widened into a vector load. And if
5318 // the address is "base + cst" see if the cst can be "absorbed" into
5319 // the shuffle mask.
5320 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(SrcOp)) {
5321 SDValue Ptr = LD->getBasePtr();
5322 if (!ISD::isNormalLoad(LD) || LD->isVolatile())
5324 EVT PVT = LD->getValueType(0);
5325 if (PVT != MVT::i32 && PVT != MVT::f32)
5330 if (FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr)) {
5331 FI = FINode->getIndex();
5333 } else if (DAG.isBaseWithConstantOffset(Ptr) &&
5334 isa<FrameIndexSDNode>(Ptr.getOperand(0))) {
5335 FI = cast<FrameIndexSDNode>(Ptr.getOperand(0))->getIndex();
5336 Offset = Ptr.getConstantOperandVal(1);
5337 Ptr = Ptr.getOperand(0);
5342 // FIXME: 256-bit vector instructions don't require a strict alignment,
5343 // improve this code to support it better.
5344 unsigned RequiredAlign = VT.getSizeInBits()/8;
5345 SDValue Chain = LD->getChain();
5346 // Make sure the stack object alignment is at least 16 or 32.
5347 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
5348 if (DAG.InferPtrAlignment(Ptr) < RequiredAlign) {
5349 if (MFI->isFixedObjectIndex(FI)) {
5350 // Can't change the alignment. FIXME: It's possible to compute
5351 // the exact stack offset and reference FI + adjust offset instead.
5352 // If someone *really* cares about this. That's the way to implement it.
5355 MFI->setObjectAlignment(FI, RequiredAlign);
5359 // (Offset % 16 or 32) must be multiple of 4. Then address is then
5360 // Ptr + (Offset & ~15).
5363 if ((Offset % RequiredAlign) & 3)
5365 int64_t StartOffset = Offset & ~(RequiredAlign-1);
5367 Ptr = DAG.getNode(ISD::ADD, SDLoc(Ptr), Ptr.getValueType(),
5368 Ptr,DAG.getConstant(StartOffset, Ptr.getValueType()));
5370 int EltNo = (Offset - StartOffset) >> 2;
5371 unsigned NumElems = VT.getVectorNumElements();
5373 EVT NVT = EVT::getVectorVT(*DAG.getContext(), PVT, NumElems);
5374 SDValue V1 = DAG.getLoad(NVT, dl, Chain, Ptr,
5375 LD->getPointerInfo().getWithOffset(StartOffset),
5376 false, false, false, 0);
5378 SmallVector<int, 8> Mask;
5379 for (unsigned i = 0; i != NumElems; ++i)
5380 Mask.push_back(EltNo);
5382 return DAG.getVectorShuffle(NVT, dl, V1, DAG.getUNDEF(NVT), &Mask[0]);
5388 /// EltsFromConsecutiveLoads - Given the initializing elements 'Elts' of a
5389 /// vector of type 'VT', see if the elements can be replaced by a single large
5390 /// load which has the same value as a build_vector whose operands are 'elts'.
5392 /// Example: <load i32 *a, load i32 *a+4, undef, undef> -> zextload a
5394 /// FIXME: we'd also like to handle the case where the last elements are zero
5395 /// rather than undef via VZEXT_LOAD, but we do not detect that case today.
5396 /// There's even a handy isZeroNode for that purpose.
5397 static SDValue EltsFromConsecutiveLoads(EVT VT, SmallVectorImpl<SDValue> &Elts,
5398 SDLoc &DL, SelectionDAG &DAG) {
5399 EVT EltVT = VT.getVectorElementType();
5400 unsigned NumElems = Elts.size();
5402 LoadSDNode *LDBase = NULL;
5403 unsigned LastLoadedElt = -1U;
5405 // For each element in the initializer, see if we've found a load or an undef.
5406 // If we don't find an initial load element, or later load elements are
5407 // non-consecutive, bail out.
5408 for (unsigned i = 0; i < NumElems; ++i) {
5409 SDValue Elt = Elts[i];
5411 if (!Elt.getNode() ||
5412 (Elt.getOpcode() != ISD::UNDEF && !ISD::isNON_EXTLoad(Elt.getNode())))
5415 if (Elt.getNode()->getOpcode() == ISD::UNDEF)
5417 LDBase = cast<LoadSDNode>(Elt.getNode());
5421 if (Elt.getOpcode() == ISD::UNDEF)
5424 LoadSDNode *LD = cast<LoadSDNode>(Elt);
5425 if (!DAG.isConsecutiveLoad(LD, LDBase, EltVT.getSizeInBits()/8, i))
5430 // If we have found an entire vector of loads and undefs, then return a large
5431 // load of the entire vector width starting at the base pointer. If we found
5432 // consecutive loads for the low half, generate a vzext_load node.
5433 if (LastLoadedElt == NumElems - 1) {
5434 SDValue NewLd = SDValue();
5435 if (DAG.InferPtrAlignment(LDBase->getBasePtr()) >= 16)
5436 NewLd = DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(),
5437 LDBase->getPointerInfo(),
5438 LDBase->isVolatile(), LDBase->isNonTemporal(),
5439 LDBase->isInvariant(), 0);
5440 NewLd = DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(),
5441 LDBase->getPointerInfo(),
5442 LDBase->isVolatile(), LDBase->isNonTemporal(),
5443 LDBase->isInvariant(), LDBase->getAlignment());
5445 if (LDBase->hasAnyUseOfValue(1)) {
5446 SDValue NewChain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
5448 SDValue(NewLd.getNode(), 1));
5449 DAG.ReplaceAllUsesOfValueWith(SDValue(LDBase, 1), NewChain);
5450 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(LDBase, 1),
5451 SDValue(NewLd.getNode(), 1));
5456 if (NumElems == 4 && LastLoadedElt == 1 &&
5457 DAG.getTargetLoweringInfo().isTypeLegal(MVT::v2i64)) {
5458 SDVTList Tys = DAG.getVTList(MVT::v2i64, MVT::Other);
5459 SDValue Ops[] = { LDBase->getChain(), LDBase->getBasePtr() };
5461 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, DL, Tys, Ops,
5462 array_lengthof(Ops), MVT::i64,
5463 LDBase->getPointerInfo(),
5464 LDBase->getAlignment(),
5465 false/*isVolatile*/, true/*ReadMem*/,
5468 // Make sure the newly-created LOAD is in the same position as LDBase in
5469 // terms of dependency. We create a TokenFactor for LDBase and ResNode, and
5470 // update uses of LDBase's output chain to use the TokenFactor.
5471 if (LDBase->hasAnyUseOfValue(1)) {
5472 SDValue NewChain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
5473 SDValue(LDBase, 1), SDValue(ResNode.getNode(), 1));
5474 DAG.ReplaceAllUsesOfValueWith(SDValue(LDBase, 1), NewChain);
5475 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(LDBase, 1),
5476 SDValue(ResNode.getNode(), 1));
5479 return DAG.getNode(ISD::BITCAST, DL, VT, ResNode);
5484 /// LowerVectorBroadcast - Attempt to use the vbroadcast instruction
5485 /// to generate a splat value for the following cases:
5486 /// 1. A splat BUILD_VECTOR which uses a single scalar load, or a constant.
5487 /// 2. A splat shuffle which uses a scalar_to_vector node which comes from
5488 /// a scalar load, or a constant.
5489 /// The VBROADCAST node is returned when a pattern is found,
5490 /// or SDValue() otherwise.
5491 static SDValue LowerVectorBroadcast(SDValue Op, const X86Subtarget* Subtarget,
5492 SelectionDAG &DAG) {
5493 if (!Subtarget->hasFp256())
5496 MVT VT = Op.getSimpleValueType();
5499 assert((VT.is128BitVector() || VT.is256BitVector() || VT.is512BitVector()) &&
5500 "Unsupported vector type for broadcast.");
5505 switch (Op.getOpcode()) {
5507 // Unknown pattern found.
5510 case ISD::BUILD_VECTOR: {
5511 // The BUILD_VECTOR node must be a splat.
5512 if (!isSplatVector(Op.getNode()))
5515 Ld = Op.getOperand(0);
5516 ConstSplatVal = (Ld.getOpcode() == ISD::Constant ||
5517 Ld.getOpcode() == ISD::ConstantFP);
5519 // The suspected load node has several users. Make sure that all
5520 // of its users are from the BUILD_VECTOR node.
5521 // Constants may have multiple users.
5522 if (!ConstSplatVal && !Ld->hasNUsesOfValue(VT.getVectorNumElements(), 0))
5527 case ISD::VECTOR_SHUFFLE: {
5528 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
5530 // Shuffles must have a splat mask where the first element is
5532 if ((!SVOp->isSplat()) || SVOp->getMaskElt(0) != 0)
5535 SDValue Sc = Op.getOperand(0);
5536 if (Sc.getOpcode() != ISD::SCALAR_TO_VECTOR &&
5537 Sc.getOpcode() != ISD::BUILD_VECTOR) {
5539 if (!Subtarget->hasInt256())
5542 // Use the register form of the broadcast instruction available on AVX2.
5543 if (VT.getSizeInBits() >= 256)
5544 Sc = Extract128BitVector(Sc, 0, DAG, dl);
5545 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Sc);
5548 Ld = Sc.getOperand(0);
5549 ConstSplatVal = (Ld.getOpcode() == ISD::Constant ||
5550 Ld.getOpcode() == ISD::ConstantFP);
5552 // The scalar_to_vector node and the suspected
5553 // load node must have exactly one user.
5554 // Constants may have multiple users.
5556 // AVX-512 has register version of the broadcast
5557 bool hasRegVer = Subtarget->hasAVX512() && VT.is512BitVector() &&
5558 Ld.getValueType().getSizeInBits() >= 32;
5559 if (!ConstSplatVal && ((!Sc.hasOneUse() || !Ld.hasOneUse()) &&
5566 bool IsGE256 = (VT.getSizeInBits() >= 256);
5568 // Handle the broadcasting a single constant scalar from the constant pool
5569 // into a vector. On Sandybridge it is still better to load a constant vector
5570 // from the constant pool and not to broadcast it from a scalar.
5571 if (ConstSplatVal && Subtarget->hasInt256()) {
5572 EVT CVT = Ld.getValueType();
5573 assert(!CVT.isVector() && "Must not broadcast a vector type");
5574 unsigned ScalarSize = CVT.getSizeInBits();
5576 if (ScalarSize == 32 || (IsGE256 && ScalarSize == 64)) {
5577 const Constant *C = 0;
5578 if (ConstantSDNode *CI = dyn_cast<ConstantSDNode>(Ld))
5579 C = CI->getConstantIntValue();
5580 else if (ConstantFPSDNode *CF = dyn_cast<ConstantFPSDNode>(Ld))
5581 C = CF->getConstantFPValue();
5583 assert(C && "Invalid constant type");
5585 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
5586 SDValue CP = DAG.getConstantPool(C, TLI.getPointerTy());
5587 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
5588 Ld = DAG.getLoad(CVT, dl, DAG.getEntryNode(), CP,
5589 MachinePointerInfo::getConstantPool(),
5590 false, false, false, Alignment);
5592 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5596 bool IsLoad = ISD::isNormalLoad(Ld.getNode());
5597 unsigned ScalarSize = Ld.getValueType().getSizeInBits();
5599 // Handle AVX2 in-register broadcasts.
5600 if (!IsLoad && Subtarget->hasInt256() &&
5601 (ScalarSize == 32 || (IsGE256 && ScalarSize == 64)))
5602 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5604 // The scalar source must be a normal load.
5608 if (ScalarSize == 32 || (IsGE256 && ScalarSize == 64))
5609 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5611 // The integer check is needed for the 64-bit into 128-bit so it doesn't match
5612 // double since there is no vbroadcastsd xmm
5613 if (Subtarget->hasInt256() && Ld.getValueType().isInteger()) {
5614 if (ScalarSize == 8 || ScalarSize == 16 || ScalarSize == 64)
5615 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5618 // Unsupported broadcast.
5622 static SDValue buildFromShuffleMostly(SDValue Op, SelectionDAG &DAG) {
5623 MVT VT = Op.getSimpleValueType();
5625 // Skip if insert_vec_elt is not supported.
5626 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
5627 if (!TLI.isOperationLegalOrCustom(ISD::INSERT_VECTOR_ELT, VT))
5631 unsigned NumElems = Op.getNumOperands();
5635 SmallVector<unsigned, 4> InsertIndices;
5636 SmallVector<int, 8> Mask(NumElems, -1);
5638 for (unsigned i = 0; i != NumElems; ++i) {
5639 unsigned Opc = Op.getOperand(i).getOpcode();
5641 if (Opc == ISD::UNDEF)
5644 if (Opc != ISD::EXTRACT_VECTOR_ELT) {
5645 // Quit if more than 1 elements need inserting.
5646 if (InsertIndices.size() > 1)
5649 InsertIndices.push_back(i);
5653 SDValue ExtractedFromVec = Op.getOperand(i).getOperand(0);
5654 SDValue ExtIdx = Op.getOperand(i).getOperand(1);
5656 // Quit if extracted from vector of different type.
5657 if (ExtractedFromVec.getValueType() != VT)
5660 // Quit if non-constant index.
5661 if (!isa<ConstantSDNode>(ExtIdx))
5664 if (VecIn1.getNode() == 0)
5665 VecIn1 = ExtractedFromVec;
5666 else if (VecIn1 != ExtractedFromVec) {
5667 if (VecIn2.getNode() == 0)
5668 VecIn2 = ExtractedFromVec;
5669 else if (VecIn2 != ExtractedFromVec)
5670 // Quit if more than 2 vectors to shuffle
5674 unsigned Idx = cast<ConstantSDNode>(ExtIdx)->getZExtValue();
5676 if (ExtractedFromVec == VecIn1)
5678 else if (ExtractedFromVec == VecIn2)
5679 Mask[i] = Idx + NumElems;
5682 if (VecIn1.getNode() == 0)
5685 VecIn2 = VecIn2.getNode() ? VecIn2 : DAG.getUNDEF(VT);
5686 SDValue NV = DAG.getVectorShuffle(VT, DL, VecIn1, VecIn2, &Mask[0]);
5687 for (unsigned i = 0, e = InsertIndices.size(); i != e; ++i) {
5688 unsigned Idx = InsertIndices[i];
5689 NV = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, VT, NV, Op.getOperand(Idx),
5690 DAG.getIntPtrConstant(Idx));
5696 // Lower BUILD_VECTOR operation for v8i1 and v16i1 types.
5698 X86TargetLowering::LowerBUILD_VECTORvXi1(SDValue Op, SelectionDAG &DAG) const {
5700 MVT VT = Op.getSimpleValueType();
5701 assert((VT.getVectorElementType() == MVT::i1) && (VT.getSizeInBits() <= 16) &&
5702 "Unexpected type in LowerBUILD_VECTORvXi1!");
5705 if (ISD::isBuildVectorAllZeros(Op.getNode())) {
5706 SDValue Cst = DAG.getTargetConstant(0, MVT::i1);
5707 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst,
5708 Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
5709 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT,
5710 Ops, VT.getVectorNumElements());
5713 if (ISD::isBuildVectorAllOnes(Op.getNode())) {
5714 SDValue Cst = DAG.getTargetConstant(1, MVT::i1);
5715 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst,
5716 Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
5717 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT,
5718 Ops, VT.getVectorNumElements());
5721 bool AllContants = true;
5722 uint64_t Immediate = 0;
5723 for (unsigned idx = 0, e = Op.getNumOperands(); idx < e; ++idx) {
5724 SDValue In = Op.getOperand(idx);
5725 if (In.getOpcode() == ISD::UNDEF)
5727 if (!isa<ConstantSDNode>(In)) {
5728 AllContants = false;
5731 if (cast<ConstantSDNode>(In)->getZExtValue())
5732 Immediate |= (1ULL << idx);
5736 SDValue FullMask = DAG.getNode(ISD::BITCAST, dl, MVT::v16i1,
5737 DAG.getConstant(Immediate, MVT::i16));
5738 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, FullMask,
5739 DAG.getIntPtrConstant(0));
5742 // Splat vector (with undefs)
5743 SDValue In = Op.getOperand(0);
5744 for (unsigned i = 1, e = Op.getNumOperands(); i != e; ++i) {
5745 if (Op.getOperand(i) != In && Op.getOperand(i).getOpcode() != ISD::UNDEF)
5746 llvm_unreachable("Unsupported predicate operation");
5749 SDValue EFLAGS, X86CC;
5750 if (In.getOpcode() == ISD::SETCC) {
5751 SDValue Op0 = In.getOperand(0);
5752 SDValue Op1 = In.getOperand(1);
5753 ISD::CondCode CC = cast<CondCodeSDNode>(In.getOperand(2))->get();
5754 bool isFP = Op1.getValueType().isFloatingPoint();
5755 unsigned X86CCVal = TranslateX86CC(CC, isFP, Op0, Op1, DAG);
5757 assert(X86CCVal != X86::COND_INVALID && "Unsupported predicate operation");
5759 X86CC = DAG.getConstant(X86CCVal, MVT::i8);
5760 EFLAGS = EmitCmp(Op0, Op1, X86CCVal, DAG);
5761 EFLAGS = ConvertCmpIfNecessary(EFLAGS, DAG);
5762 } else if (In.getOpcode() == X86ISD::SETCC) {
5763 X86CC = In.getOperand(0);
5764 EFLAGS = In.getOperand(1);
5773 // res = allOnes ### CMOVNE -1, %res
5776 MVT InVT = In.getSimpleValueType();
5777 SDValue Bit1 = DAG.getNode(ISD::AND, dl, InVT, In, DAG.getConstant(1, InVT));
5778 EFLAGS = EmitTest(Bit1, X86::COND_NE, DAG);
5779 X86CC = DAG.getConstant(X86::COND_NE, MVT::i8);
5782 if (VT == MVT::v16i1) {
5783 SDValue Cst1 = DAG.getConstant(-1, MVT::i16);
5784 SDValue Cst0 = DAG.getConstant(0, MVT::i16);
5785 SDValue CmovOp = DAG.getNode(X86ISD::CMOV, dl, MVT::i16,
5786 Cst0, Cst1, X86CC, EFLAGS);
5787 return DAG.getNode(ISD::BITCAST, dl, VT, CmovOp);
5790 if (VT == MVT::v8i1) {
5791 SDValue Cst1 = DAG.getConstant(-1, MVT::i32);
5792 SDValue Cst0 = DAG.getConstant(0, MVT::i32);
5793 SDValue CmovOp = DAG.getNode(X86ISD::CMOV, dl, MVT::i32,
5794 Cst0, Cst1, X86CC, EFLAGS);
5795 CmovOp = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, CmovOp);
5796 return DAG.getNode(ISD::BITCAST, dl, VT, CmovOp);
5798 llvm_unreachable("Unsupported predicate operation");
5802 X86TargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const {
5805 MVT VT = Op.getSimpleValueType();
5806 MVT ExtVT = VT.getVectorElementType();
5807 unsigned NumElems = Op.getNumOperands();
5809 // Generate vectors for predicate vectors.
5810 if (VT.getScalarType() == MVT::i1 && Subtarget->hasAVX512())
5811 return LowerBUILD_VECTORvXi1(Op, DAG);
5813 // Vectors containing all zeros can be matched by pxor and xorps later
5814 if (ISD::isBuildVectorAllZeros(Op.getNode())) {
5815 // Canonicalize this to <4 x i32> to 1) ensure the zero vectors are CSE'd
5816 // and 2) ensure that i64 scalars are eliminated on x86-32 hosts.
5817 if (VT == MVT::v4i32 || VT == MVT::v8i32 || VT == MVT::v16i32)
5820 return getZeroVector(VT, Subtarget, DAG, dl);
5823 // Vectors containing all ones can be matched by pcmpeqd on 128-bit width
5824 // vectors or broken into v4i32 operations on 256-bit vectors. AVX2 can use
5825 // vpcmpeqd on 256-bit vectors.
5826 if (Subtarget->hasSSE2() && ISD::isBuildVectorAllOnes(Op.getNode())) {
5827 if (VT == MVT::v4i32 || (VT == MVT::v8i32 && Subtarget->hasInt256()))
5830 if (!VT.is512BitVector())
5831 return getOnesVector(VT, Subtarget->hasInt256(), DAG, dl);
5834 SDValue Broadcast = LowerVectorBroadcast(Op, Subtarget, DAG);
5835 if (Broadcast.getNode())
5838 unsigned EVTBits = ExtVT.getSizeInBits();
5840 unsigned NumZero = 0;
5841 unsigned NumNonZero = 0;
5842 unsigned NonZeros = 0;
5843 bool IsAllConstants = true;
5844 SmallSet<SDValue, 8> Values;
5845 for (unsigned i = 0; i < NumElems; ++i) {
5846 SDValue Elt = Op.getOperand(i);
5847 if (Elt.getOpcode() == ISD::UNDEF)
5850 if (Elt.getOpcode() != ISD::Constant &&
5851 Elt.getOpcode() != ISD::ConstantFP)
5852 IsAllConstants = false;
5853 if (X86::isZeroNode(Elt))
5856 NonZeros |= (1 << i);
5861 // All undef vector. Return an UNDEF. All zero vectors were handled above.
5862 if (NumNonZero == 0)
5863 return DAG.getUNDEF(VT);
5865 // Special case for single non-zero, non-undef, element.
5866 if (NumNonZero == 1) {
5867 unsigned Idx = countTrailingZeros(NonZeros);
5868 SDValue Item = Op.getOperand(Idx);
5870 // If this is an insertion of an i64 value on x86-32, and if the top bits of
5871 // the value are obviously zero, truncate the value to i32 and do the
5872 // insertion that way. Only do this if the value is non-constant or if the
5873 // value is a constant being inserted into element 0. It is cheaper to do
5874 // a constant pool load than it is to do a movd + shuffle.
5875 if (ExtVT == MVT::i64 && !Subtarget->is64Bit() &&
5876 (!IsAllConstants || Idx == 0)) {
5877 if (DAG.MaskedValueIsZero(Item, APInt::getBitsSet(64, 32, 64))) {
5879 assert(VT == MVT::v2i64 && "Expected an SSE value type!");
5880 EVT VecVT = MVT::v4i32;
5881 unsigned VecElts = 4;
5883 // Truncate the value (which may itself be a constant) to i32, and
5884 // convert it to a vector with movd (S2V+shuffle to zero extend).
5885 Item = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Item);
5886 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Item);
5887 Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
5889 // Now we have our 32-bit value zero extended in the low element of
5890 // a vector. If Idx != 0, swizzle it into place.
5892 SmallVector<int, 4> Mask;
5893 Mask.push_back(Idx);
5894 for (unsigned i = 1; i != VecElts; ++i)
5896 Item = DAG.getVectorShuffle(VecVT, dl, Item, DAG.getUNDEF(VecVT),
5899 return DAG.getNode(ISD::BITCAST, dl, VT, Item);
5903 // If we have a constant or non-constant insertion into the low element of
5904 // a vector, we can do this with SCALAR_TO_VECTOR + shuffle of zero into
5905 // the rest of the elements. This will be matched as movd/movq/movss/movsd
5906 // depending on what the source datatype is.
5909 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
5911 if (ExtVT == MVT::i32 || ExtVT == MVT::f32 || ExtVT == MVT::f64 ||
5912 (ExtVT == MVT::i64 && Subtarget->is64Bit())) {
5913 if (VT.is256BitVector() || VT.is512BitVector()) {
5914 SDValue ZeroVec = getZeroVector(VT, Subtarget, DAG, dl);
5915 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, ZeroVec,
5916 Item, DAG.getIntPtrConstant(0));
5918 assert(VT.is128BitVector() && "Expected an SSE value type!");
5919 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
5920 // Turn it into a MOVL (i.e. movss, movsd, or movd) to a zero vector.
5921 return getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
5924 if (ExtVT == MVT::i16 || ExtVT == MVT::i8) {
5925 Item = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Item);
5926 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, Item);
5927 if (VT.is256BitVector()) {
5928 SDValue ZeroVec = getZeroVector(MVT::v8i32, Subtarget, DAG, dl);
5929 Item = Insert128BitVector(ZeroVec, Item, 0, DAG, dl);
5931 assert(VT.is128BitVector() && "Expected an SSE value type!");
5932 Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
5934 return DAG.getNode(ISD::BITCAST, dl, VT, Item);
5938 // Is it a vector logical left shift?
5939 if (NumElems == 2 && Idx == 1 &&
5940 X86::isZeroNode(Op.getOperand(0)) &&
5941 !X86::isZeroNode(Op.getOperand(1))) {
5942 unsigned NumBits = VT.getSizeInBits();
5943 return getVShift(true, VT,
5944 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
5945 VT, Op.getOperand(1)),
5946 NumBits/2, DAG, *this, dl);
5949 if (IsAllConstants) // Otherwise, it's better to do a constpool load.
5952 // Otherwise, if this is a vector with i32 or f32 elements, and the element
5953 // is a non-constant being inserted into an element other than the low one,
5954 // we can't use a constant pool load. Instead, use SCALAR_TO_VECTOR (aka
5955 // movd/movss) to move this into the low element, then shuffle it into
5957 if (EVTBits == 32) {
5958 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
5960 // Turn it into a shuffle of zero and zero-extended scalar to vector.
5961 Item = getShuffleVectorZeroOrUndef(Item, 0, NumZero > 0, Subtarget, DAG);
5962 SmallVector<int, 8> MaskVec;
5963 for (unsigned i = 0; i != NumElems; ++i)
5964 MaskVec.push_back(i == Idx ? 0 : 1);
5965 return DAG.getVectorShuffle(VT, dl, Item, DAG.getUNDEF(VT), &MaskVec[0]);
5969 // Splat is obviously ok. Let legalizer expand it to a shuffle.
5970 if (Values.size() == 1) {
5971 if (EVTBits == 32) {
5972 // Instead of a shuffle like this:
5973 // shuffle (scalar_to_vector (load (ptr + 4))), undef, <0, 0, 0, 0>
5974 // Check if it's possible to issue this instead.
5975 // shuffle (vload ptr)), undef, <1, 1, 1, 1>
5976 unsigned Idx = countTrailingZeros(NonZeros);
5977 SDValue Item = Op.getOperand(Idx);
5978 if (Op.getNode()->isOnlyUserOf(Item.getNode()))
5979 return LowerAsSplatVectorLoad(Item, VT, dl, DAG);
5984 // A vector full of immediates; various special cases are already
5985 // handled, so this is best done with a single constant-pool load.
5989 // For AVX-length vectors, build the individual 128-bit pieces and use
5990 // shuffles to put them in place.
5991 if (VT.is256BitVector()) {
5992 SmallVector<SDValue, 32> V;
5993 for (unsigned i = 0; i != NumElems; ++i)
5994 V.push_back(Op.getOperand(i));
5996 EVT HVT = EVT::getVectorVT(*DAG.getContext(), ExtVT, NumElems/2);
5998 // Build both the lower and upper subvector.
5999 SDValue Lower = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT, &V[0], NumElems/2);
6000 SDValue Upper = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT, &V[NumElems / 2],
6003 // Recreate the wider vector with the lower and upper part.
6004 return Concat128BitVectors(Lower, Upper, VT, NumElems, DAG, dl);
6007 // Let legalizer expand 2-wide build_vectors.
6008 if (EVTBits == 64) {
6009 if (NumNonZero == 1) {
6010 // One half is zero or undef.
6011 unsigned Idx = countTrailingZeros(NonZeros);
6012 SDValue V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT,
6013 Op.getOperand(Idx));
6014 return getShuffleVectorZeroOrUndef(V2, Idx, true, Subtarget, DAG);
6019 // If element VT is < 32 bits, convert it to inserts into a zero vector.
6020 if (EVTBits == 8 && NumElems == 16) {
6021 SDValue V = LowerBuildVectorv16i8(Op, NonZeros,NumNonZero,NumZero, DAG,
6023 if (V.getNode()) return V;
6026 if (EVTBits == 16 && NumElems == 8) {
6027 SDValue V = LowerBuildVectorv8i16(Op, NonZeros,NumNonZero,NumZero, DAG,
6029 if (V.getNode()) return V;
6032 // If element VT is == 32 bits, turn it into a number of shuffles.
6033 SmallVector<SDValue, 8> V(NumElems);
6034 if (NumElems == 4 && NumZero > 0) {
6035 for (unsigned i = 0; i < 4; ++i) {
6036 bool isZero = !(NonZeros & (1 << i));
6038 V[i] = getZeroVector(VT, Subtarget, DAG, dl);
6040 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
6043 for (unsigned i = 0; i < 2; ++i) {
6044 switch ((NonZeros & (0x3 << i*2)) >> (i*2)) {
6047 V[i] = V[i*2]; // Must be a zero vector.
6050 V[i] = getMOVL(DAG, dl, VT, V[i*2+1], V[i*2]);
6053 V[i] = getMOVL(DAG, dl, VT, V[i*2], V[i*2+1]);
6056 V[i] = getUnpackl(DAG, dl, VT, V[i*2], V[i*2+1]);
6061 bool Reverse1 = (NonZeros & 0x3) == 2;
6062 bool Reverse2 = ((NonZeros & (0x3 << 2)) >> 2) == 2;
6066 static_cast<int>(Reverse2 ? NumElems+1 : NumElems),
6067 static_cast<int>(Reverse2 ? NumElems : NumElems+1)
6069 return DAG.getVectorShuffle(VT, dl, V[0], V[1], &MaskVec[0]);
6072 if (Values.size() > 1 && VT.is128BitVector()) {
6073 // Check for a build vector of consecutive loads.
6074 for (unsigned i = 0; i < NumElems; ++i)
6075 V[i] = Op.getOperand(i);
6077 // Check for elements which are consecutive loads.
6078 SDValue LD = EltsFromConsecutiveLoads(VT, V, dl, DAG);
6082 // Check for a build vector from mostly shuffle plus few inserting.
6083 SDValue Sh = buildFromShuffleMostly(Op, DAG);
6087 // For SSE 4.1, use insertps to put the high elements into the low element.
6088 if (getSubtarget()->hasSSE41()) {
6090 if (Op.getOperand(0).getOpcode() != ISD::UNDEF)
6091 Result = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(0));
6093 Result = DAG.getUNDEF(VT);
6095 for (unsigned i = 1; i < NumElems; ++i) {
6096 if (Op.getOperand(i).getOpcode() == ISD::UNDEF) continue;
6097 Result = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Result,
6098 Op.getOperand(i), DAG.getIntPtrConstant(i));
6103 // Otherwise, expand into a number of unpckl*, start by extending each of
6104 // our (non-undef) elements to the full vector width with the element in the
6105 // bottom slot of the vector (which generates no code for SSE).
6106 for (unsigned i = 0; i < NumElems; ++i) {
6107 if (Op.getOperand(i).getOpcode() != ISD::UNDEF)
6108 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
6110 V[i] = DAG.getUNDEF(VT);
6113 // Next, we iteratively mix elements, e.g. for v4f32:
6114 // Step 1: unpcklps 0, 2 ==> X: <?, ?, 2, 0>
6115 // : unpcklps 1, 3 ==> Y: <?, ?, 3, 1>
6116 // Step 2: unpcklps X, Y ==> <3, 2, 1, 0>
6117 unsigned EltStride = NumElems >> 1;
6118 while (EltStride != 0) {
6119 for (unsigned i = 0; i < EltStride; ++i) {
6120 // If V[i+EltStride] is undef and this is the first round of mixing,
6121 // then it is safe to just drop this shuffle: V[i] is already in the
6122 // right place, the one element (since it's the first round) being
6123 // inserted as undef can be dropped. This isn't safe for successive
6124 // rounds because they will permute elements within both vectors.
6125 if (V[i+EltStride].getOpcode() == ISD::UNDEF &&
6126 EltStride == NumElems/2)
6129 V[i] = getUnpackl(DAG, dl, VT, V[i], V[i + EltStride]);
6138 // LowerAVXCONCAT_VECTORS - 256-bit AVX can use the vinsertf128 instruction
6139 // to create 256-bit vectors from two other 128-bit ones.
6140 static SDValue LowerAVXCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
6142 MVT ResVT = Op.getSimpleValueType();
6144 assert((ResVT.is256BitVector() ||
6145 ResVT.is512BitVector()) && "Value type must be 256-/512-bit wide");
6147 SDValue V1 = Op.getOperand(0);
6148 SDValue V2 = Op.getOperand(1);
6149 unsigned NumElems = ResVT.getVectorNumElements();
6150 if(ResVT.is256BitVector())
6151 return Concat128BitVectors(V1, V2, ResVT, NumElems, DAG, dl);
6153 if (Op.getNumOperands() == 4) {
6154 MVT HalfVT = MVT::getVectorVT(ResVT.getScalarType(),
6155 ResVT.getVectorNumElements()/2);
6156 SDValue V3 = Op.getOperand(2);
6157 SDValue V4 = Op.getOperand(3);
6158 return Concat256BitVectors(Concat128BitVectors(V1, V2, HalfVT, NumElems/2, DAG, dl),
6159 Concat128BitVectors(V3, V4, HalfVT, NumElems/2, DAG, dl), ResVT, NumElems, DAG, dl);
6161 return Concat256BitVectors(V1, V2, ResVT, NumElems, DAG, dl);
6164 static SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
6165 MVT LLVM_ATTRIBUTE_UNUSED VT = Op.getSimpleValueType();
6166 assert((VT.is256BitVector() && Op.getNumOperands() == 2) ||
6167 (VT.is512BitVector() && (Op.getNumOperands() == 2 ||
6168 Op.getNumOperands() == 4)));
6170 // AVX can use the vinsertf128 instruction to create 256-bit vectors
6171 // from two other 128-bit ones.
6173 // 512-bit vector may contain 2 256-bit vectors or 4 128-bit vectors
6174 return LowerAVXCONCAT_VECTORS(Op, DAG);
6177 // Try to lower a shuffle node into a simple blend instruction.
6179 LowerVECTOR_SHUFFLEtoBlend(ShuffleVectorSDNode *SVOp,
6180 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
6181 SDValue V1 = SVOp->getOperand(0);
6182 SDValue V2 = SVOp->getOperand(1);
6184 MVT VT = SVOp->getSimpleValueType(0);
6185 MVT EltVT = VT.getVectorElementType();
6186 unsigned NumElems = VT.getVectorNumElements();
6188 // There is no blend with immediate in AVX-512.
6189 if (VT.is512BitVector())
6192 if (!Subtarget->hasSSE41() || EltVT == MVT::i8)
6194 if (!Subtarget->hasInt256() && VT == MVT::v16i16)
6197 // Check the mask for BLEND and build the value.
6198 unsigned MaskValue = 0;
6199 // There are 2 lanes if (NumElems > 8), and 1 lane otherwise.
6200 unsigned NumLanes = (NumElems-1)/8 + 1;
6201 unsigned NumElemsInLane = NumElems / NumLanes;
6203 // Blend for v16i16 should be symetric for the both lanes.
6204 for (unsigned i = 0; i < NumElemsInLane; ++i) {
6206 int SndLaneEltIdx = (NumLanes == 2) ?
6207 SVOp->getMaskElt(i + NumElemsInLane) : -1;
6208 int EltIdx = SVOp->getMaskElt(i);
6210 if ((EltIdx < 0 || EltIdx == (int)i) &&
6211 (SndLaneEltIdx < 0 || SndLaneEltIdx == (int)(i + NumElemsInLane)))
6214 if (((unsigned)EltIdx == (i + NumElems)) &&
6215 (SndLaneEltIdx < 0 ||
6216 (unsigned)SndLaneEltIdx == i + NumElems + NumElemsInLane))
6217 MaskValue |= (1<<i);
6222 // Convert i32 vectors to floating point if it is not AVX2.
6223 // AVX2 introduced VPBLENDD instruction for 128 and 256-bit vectors.
6225 if (EltVT == MVT::i64 || (EltVT == MVT::i32 && !Subtarget->hasInt256())) {
6226 BlendVT = MVT::getVectorVT(MVT::getFloatingPointVT(EltVT.getSizeInBits()),
6228 V1 = DAG.getNode(ISD::BITCAST, dl, VT, V1);
6229 V2 = DAG.getNode(ISD::BITCAST, dl, VT, V2);
6232 SDValue Ret = DAG.getNode(X86ISD::BLENDI, dl, BlendVT, V1, V2,
6233 DAG.getConstant(MaskValue, MVT::i32));
6234 return DAG.getNode(ISD::BITCAST, dl, VT, Ret);
6237 // v8i16 shuffles - Prefer shuffles in the following order:
6238 // 1. [all] pshuflw, pshufhw, optional move
6239 // 2. [ssse3] 1 x pshufb
6240 // 3. [ssse3] 2 x pshufb + 1 x por
6241 // 4. [all] mov + pshuflw + pshufhw + N x (pextrw + pinsrw)
6243 LowerVECTOR_SHUFFLEv8i16(SDValue Op, const X86Subtarget *Subtarget,
6244 SelectionDAG &DAG) {
6245 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
6246 SDValue V1 = SVOp->getOperand(0);
6247 SDValue V2 = SVOp->getOperand(1);
6249 SmallVector<int, 8> MaskVals;
6251 // Determine if more than 1 of the words in each of the low and high quadwords
6252 // of the result come from the same quadword of one of the two inputs. Undef
6253 // mask values count as coming from any quadword, for better codegen.
6254 unsigned LoQuad[] = { 0, 0, 0, 0 };
6255 unsigned HiQuad[] = { 0, 0, 0, 0 };
6256 std::bitset<4> InputQuads;
6257 for (unsigned i = 0; i < 8; ++i) {
6258 unsigned *Quad = i < 4 ? LoQuad : HiQuad;
6259 int EltIdx = SVOp->getMaskElt(i);
6260 MaskVals.push_back(EltIdx);
6269 InputQuads.set(EltIdx / 4);
6272 int BestLoQuad = -1;
6273 unsigned MaxQuad = 1;
6274 for (unsigned i = 0; i < 4; ++i) {
6275 if (LoQuad[i] > MaxQuad) {
6277 MaxQuad = LoQuad[i];
6281 int BestHiQuad = -1;
6283 for (unsigned i = 0; i < 4; ++i) {
6284 if (HiQuad[i] > MaxQuad) {
6286 MaxQuad = HiQuad[i];
6290 // For SSSE3, If all 8 words of the result come from only 1 quadword of each
6291 // of the two input vectors, shuffle them into one input vector so only a
6292 // single pshufb instruction is necessary. If There are more than 2 input
6293 // quads, disable the next transformation since it does not help SSSE3.
6294 bool V1Used = InputQuads[0] || InputQuads[1];
6295 bool V2Used = InputQuads[2] || InputQuads[3];
6296 if (Subtarget->hasSSSE3()) {
6297 if (InputQuads.count() == 2 && V1Used && V2Used) {
6298 BestLoQuad = InputQuads[0] ? 0 : 1;
6299 BestHiQuad = InputQuads[2] ? 2 : 3;
6301 if (InputQuads.count() > 2) {
6307 // If BestLoQuad or BestHiQuad are set, shuffle the quads together and update
6308 // the shuffle mask. If a quad is scored as -1, that means that it contains
6309 // words from all 4 input quadwords.
6311 if (BestLoQuad >= 0 || BestHiQuad >= 0) {
6313 BestLoQuad < 0 ? 0 : BestLoQuad,
6314 BestHiQuad < 0 ? 1 : BestHiQuad
6316 NewV = DAG.getVectorShuffle(MVT::v2i64, dl,
6317 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, V1),
6318 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, V2), &MaskV[0]);
6319 NewV = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, NewV);
6321 // Rewrite the MaskVals and assign NewV to V1 if NewV now contains all the
6322 // source words for the shuffle, to aid later transformations.
6323 bool AllWordsInNewV = true;
6324 bool InOrder[2] = { true, true };
6325 for (unsigned i = 0; i != 8; ++i) {
6326 int idx = MaskVals[i];
6328 InOrder[i/4] = false;
6329 if (idx < 0 || (idx/4) == BestLoQuad || (idx/4) == BestHiQuad)
6331 AllWordsInNewV = false;
6335 bool pshuflw = AllWordsInNewV, pshufhw = AllWordsInNewV;
6336 if (AllWordsInNewV) {
6337 for (int i = 0; i != 8; ++i) {
6338 int idx = MaskVals[i];
6341 idx = MaskVals[i] = (idx / 4) == BestLoQuad ? (idx & 3) : (idx & 3) + 4;
6342 if ((idx != i) && idx < 4)
6344 if ((idx != i) && idx > 3)
6353 // If we've eliminated the use of V2, and the new mask is a pshuflw or
6354 // pshufhw, that's as cheap as it gets. Return the new shuffle.
6355 if ((pshufhw && InOrder[0]) || (pshuflw && InOrder[1])) {
6356 unsigned Opc = pshufhw ? X86ISD::PSHUFHW : X86ISD::PSHUFLW;
6357 unsigned TargetMask = 0;
6358 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV,
6359 DAG.getUNDEF(MVT::v8i16), &MaskVals[0]);
6360 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode());
6361 TargetMask = pshufhw ? getShufflePSHUFHWImmediate(SVOp):
6362 getShufflePSHUFLWImmediate(SVOp);
6363 V1 = NewV.getOperand(0);
6364 return getTargetShuffleNode(Opc, dl, MVT::v8i16, V1, TargetMask, DAG);
6368 // Promote splats to a larger type which usually leads to more efficient code.
6369 // FIXME: Is this true if pshufb is available?
6370 if (SVOp->isSplat())
6371 return PromoteSplat(SVOp, DAG);
6373 // If we have SSSE3, and all words of the result are from 1 input vector,
6374 // case 2 is generated, otherwise case 3 is generated. If no SSSE3
6375 // is present, fall back to case 4.
6376 if (Subtarget->hasSSSE3()) {
6377 SmallVector<SDValue,16> pshufbMask;
6379 // If we have elements from both input vectors, set the high bit of the
6380 // shuffle mask element to zero out elements that come from V2 in the V1
6381 // mask, and elements that come from V1 in the V2 mask, so that the two
6382 // results can be OR'd together.
6383 bool TwoInputs = V1Used && V2Used;
6384 for (unsigned i = 0; i != 8; ++i) {
6385 int EltIdx = MaskVals[i] * 2;
6386 int Idx0 = (TwoInputs && (EltIdx >= 16)) ? 0x80 : EltIdx;
6387 int Idx1 = (TwoInputs && (EltIdx >= 16)) ? 0x80 : EltIdx+1;
6388 pshufbMask.push_back(DAG.getConstant(Idx0, MVT::i8));
6389 pshufbMask.push_back(DAG.getConstant(Idx1, MVT::i8));
6391 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V1);
6392 V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1,
6393 DAG.getNode(ISD::BUILD_VECTOR, dl,
6394 MVT::v16i8, &pshufbMask[0], 16));
6396 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
6398 // Calculate the shuffle mask for the second input, shuffle it, and
6399 // OR it with the first shuffled input.
6401 for (unsigned i = 0; i != 8; ++i) {
6402 int EltIdx = MaskVals[i] * 2;
6403 int Idx0 = (EltIdx < 16) ? 0x80 : EltIdx - 16;
6404 int Idx1 = (EltIdx < 16) ? 0x80 : EltIdx - 15;
6405 pshufbMask.push_back(DAG.getConstant(Idx0, MVT::i8));
6406 pshufbMask.push_back(DAG.getConstant(Idx1, MVT::i8));
6408 V2 = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V2);
6409 V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2,
6410 DAG.getNode(ISD::BUILD_VECTOR, dl,
6411 MVT::v16i8, &pshufbMask[0], 16));
6412 V1 = DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
6413 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
6416 // If BestLoQuad >= 0, generate a pshuflw to put the low elements in order,
6417 // and update MaskVals with new element order.
6418 std::bitset<8> InOrder;
6419 if (BestLoQuad >= 0) {
6420 int MaskV[] = { -1, -1, -1, -1, 4, 5, 6, 7 };
6421 for (int i = 0; i != 4; ++i) {
6422 int idx = MaskVals[i];
6425 } else if ((idx / 4) == BestLoQuad) {
6430 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16),
6433 if (NewV.getOpcode() == ISD::VECTOR_SHUFFLE && Subtarget->hasSSSE3()) {
6434 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode());
6435 NewV = getTargetShuffleNode(X86ISD::PSHUFLW, dl, MVT::v8i16,
6437 getShufflePSHUFLWImmediate(SVOp), DAG);
6441 // If BestHi >= 0, generate a pshufhw to put the high elements in order,
6442 // and update MaskVals with the new element order.
6443 if (BestHiQuad >= 0) {
6444 int MaskV[] = { 0, 1, 2, 3, -1, -1, -1, -1 };
6445 for (unsigned i = 4; i != 8; ++i) {
6446 int idx = MaskVals[i];
6449 } else if ((idx / 4) == BestHiQuad) {
6450 MaskV[i] = (idx & 3) + 4;
6454 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16),
6457 if (NewV.getOpcode() == ISD::VECTOR_SHUFFLE && Subtarget->hasSSSE3()) {
6458 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode());
6459 NewV = getTargetShuffleNode(X86ISD::PSHUFHW, dl, MVT::v8i16,
6461 getShufflePSHUFHWImmediate(SVOp), DAG);
6465 // In case BestHi & BestLo were both -1, which means each quadword has a word
6466 // from each of the four input quadwords, calculate the InOrder bitvector now
6467 // before falling through to the insert/extract cleanup.
6468 if (BestLoQuad == -1 && BestHiQuad == -1) {
6470 for (int i = 0; i != 8; ++i)
6471 if (MaskVals[i] < 0 || MaskVals[i] == i)
6475 // The other elements are put in the right place using pextrw and pinsrw.
6476 for (unsigned i = 0; i != 8; ++i) {
6479 int EltIdx = MaskVals[i];
6482 SDValue ExtOp = (EltIdx < 8) ?
6483 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V1,
6484 DAG.getIntPtrConstant(EltIdx)) :
6485 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V2,
6486 DAG.getIntPtrConstant(EltIdx - 8));
6487 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, ExtOp,
6488 DAG.getIntPtrConstant(i));
6493 // v16i8 shuffles - Prefer shuffles in the following order:
6494 // 1. [ssse3] 1 x pshufb
6495 // 2. [ssse3] 2 x pshufb + 1 x por
6496 // 3. [all] v8i16 shuffle + N x pextrw + rotate + pinsrw
6497 static SDValue LowerVECTOR_SHUFFLEv16i8(ShuffleVectorSDNode *SVOp,
6498 const X86Subtarget* Subtarget,
6499 SelectionDAG &DAG) {
6500 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
6501 SDValue V1 = SVOp->getOperand(0);
6502 SDValue V2 = SVOp->getOperand(1);
6504 ArrayRef<int> MaskVals = SVOp->getMask();
6506 // Promote splats to a larger type which usually leads to more efficient code.
6507 // FIXME: Is this true if pshufb is available?
6508 if (SVOp->isSplat())
6509 return PromoteSplat(SVOp, DAG);
6511 // If we have SSSE3, case 1 is generated when all result bytes come from
6512 // one of the inputs. Otherwise, case 2 is generated. If no SSSE3 is
6513 // present, fall back to case 3.
6515 // If SSSE3, use 1 pshufb instruction per vector with elements in the result.
6516 if (Subtarget->hasSSSE3()) {
6517 SmallVector<SDValue,16> pshufbMask;
6519 // If all result elements are from one input vector, then only translate
6520 // undef mask values to 0x80 (zero out result) in the pshufb mask.
6522 // Otherwise, we have elements from both input vectors, and must zero out
6523 // elements that come from V2 in the first mask, and V1 in the second mask
6524 // so that we can OR them together.
6525 for (unsigned i = 0; i != 16; ++i) {
6526 int EltIdx = MaskVals[i];
6527 if (EltIdx < 0 || EltIdx >= 16)
6529 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
6531 V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1,
6532 DAG.getNode(ISD::BUILD_VECTOR, dl,
6533 MVT::v16i8, &pshufbMask[0], 16));
6535 // As PSHUFB will zero elements with negative indices, it's safe to ignore
6536 // the 2nd operand if it's undefined or zero.
6537 if (V2.getOpcode() == ISD::UNDEF ||
6538 ISD::isBuildVectorAllZeros(V2.getNode()))
6541 // Calculate the shuffle mask for the second input, shuffle it, and
6542 // OR it with the first shuffled input.
6544 for (unsigned i = 0; i != 16; ++i) {
6545 int EltIdx = MaskVals[i];
6546 EltIdx = (EltIdx < 16) ? 0x80 : EltIdx - 16;
6547 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
6549 V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2,
6550 DAG.getNode(ISD::BUILD_VECTOR, dl,
6551 MVT::v16i8, &pshufbMask[0], 16));
6552 return DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
6555 // No SSSE3 - Calculate in place words and then fix all out of place words
6556 // With 0-16 extracts & inserts. Worst case is 16 bytes out of order from
6557 // the 16 different words that comprise the two doublequadword input vectors.
6558 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
6559 V2 = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V2);
6561 for (int i = 0; i != 8; ++i) {
6562 int Elt0 = MaskVals[i*2];
6563 int Elt1 = MaskVals[i*2+1];
6565 // This word of the result is all undef, skip it.
6566 if (Elt0 < 0 && Elt1 < 0)
6569 // This word of the result is already in the correct place, skip it.
6570 if ((Elt0 == i*2) && (Elt1 == i*2+1))
6573 SDValue Elt0Src = Elt0 < 16 ? V1 : V2;
6574 SDValue Elt1Src = Elt1 < 16 ? V1 : V2;
6577 // If Elt0 and Elt1 are defined, are consecutive, and can be load
6578 // using a single extract together, load it and store it.
6579 if ((Elt0 >= 0) && ((Elt0 + 1) == Elt1) && ((Elt0 & 1) == 0)) {
6580 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src,
6581 DAG.getIntPtrConstant(Elt1 / 2));
6582 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt,
6583 DAG.getIntPtrConstant(i));
6587 // If Elt1 is defined, extract it from the appropriate source. If the
6588 // source byte is not also odd, shift the extracted word left 8 bits
6589 // otherwise clear the bottom 8 bits if we need to do an or.
6591 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src,
6592 DAG.getIntPtrConstant(Elt1 / 2));
6593 if ((Elt1 & 1) == 0)
6594 InsElt = DAG.getNode(ISD::SHL, dl, MVT::i16, InsElt,
6596 TLI.getShiftAmountTy(InsElt.getValueType())));
6598 InsElt = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt,
6599 DAG.getConstant(0xFF00, MVT::i16));
6601 // If Elt0 is defined, extract it from the appropriate source. If the
6602 // source byte is not also even, shift the extracted word right 8 bits. If
6603 // Elt1 was also defined, OR the extracted values together before
6604 // inserting them in the result.
6606 SDValue InsElt0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16,
6607 Elt0Src, DAG.getIntPtrConstant(Elt0 / 2));
6608 if ((Elt0 & 1) != 0)
6609 InsElt0 = DAG.getNode(ISD::SRL, dl, MVT::i16, InsElt0,
6611 TLI.getShiftAmountTy(InsElt0.getValueType())));
6613 InsElt0 = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt0,
6614 DAG.getConstant(0x00FF, MVT::i16));
6615 InsElt = Elt1 >= 0 ? DAG.getNode(ISD::OR, dl, MVT::i16, InsElt, InsElt0)
6618 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt,
6619 DAG.getIntPtrConstant(i));
6621 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, NewV);
6624 // v32i8 shuffles - Translate to VPSHUFB if possible.
6626 SDValue LowerVECTOR_SHUFFLEv32i8(ShuffleVectorSDNode *SVOp,
6627 const X86Subtarget *Subtarget,
6628 SelectionDAG &DAG) {
6629 MVT VT = SVOp->getSimpleValueType(0);
6630 SDValue V1 = SVOp->getOperand(0);
6631 SDValue V2 = SVOp->getOperand(1);
6633 SmallVector<int, 32> MaskVals(SVOp->getMask().begin(), SVOp->getMask().end());
6635 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
6636 bool V1IsAllZero = ISD::isBuildVectorAllZeros(V1.getNode());
6637 bool V2IsAllZero = ISD::isBuildVectorAllZeros(V2.getNode());
6639 // VPSHUFB may be generated if
6640 // (1) one of input vector is undefined or zeroinitializer.
6641 // The mask value 0x80 puts 0 in the corresponding slot of the vector.
6642 // And (2) the mask indexes don't cross the 128-bit lane.
6643 if (VT != MVT::v32i8 || !Subtarget->hasInt256() ||
6644 (!V2IsUndef && !V2IsAllZero && !V1IsAllZero))
6647 if (V1IsAllZero && !V2IsAllZero) {
6648 CommuteVectorShuffleMask(MaskVals, 32);
6651 SmallVector<SDValue, 32> pshufbMask;
6652 for (unsigned i = 0; i != 32; i++) {
6653 int EltIdx = MaskVals[i];
6654 if (EltIdx < 0 || EltIdx >= 32)
6657 if ((EltIdx >= 16 && i < 16) || (EltIdx < 16 && i >= 16))
6658 // Cross lane is not allowed.
6662 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
6664 return DAG.getNode(X86ISD::PSHUFB, dl, MVT::v32i8, V1,
6665 DAG.getNode(ISD::BUILD_VECTOR, dl,
6666 MVT::v32i8, &pshufbMask[0], 32));
6669 /// RewriteAsNarrowerShuffle - Try rewriting v8i16 and v16i8 shuffles as 4 wide
6670 /// ones, or rewriting v4i32 / v4f32 as 2 wide ones if possible. This can be
6671 /// done when every pair / quad of shuffle mask elements point to elements in
6672 /// the right sequence. e.g.
6673 /// vector_shuffle X, Y, <2, 3, | 10, 11, | 0, 1, | 14, 15>
6675 SDValue RewriteAsNarrowerShuffle(ShuffleVectorSDNode *SVOp,
6676 SelectionDAG &DAG) {
6677 MVT VT = SVOp->getSimpleValueType(0);
6679 unsigned NumElems = VT.getVectorNumElements();
6682 switch (VT.SimpleTy) {
6683 default: llvm_unreachable("Unexpected!");
6684 case MVT::v4f32: NewVT = MVT::v2f64; Scale = 2; break;
6685 case MVT::v4i32: NewVT = MVT::v2i64; Scale = 2; break;
6686 case MVT::v8i16: NewVT = MVT::v4i32; Scale = 2; break;
6687 case MVT::v16i8: NewVT = MVT::v4i32; Scale = 4; break;
6688 case MVT::v16i16: NewVT = MVT::v8i32; Scale = 2; break;
6689 case MVT::v32i8: NewVT = MVT::v8i32; Scale = 4; break;
6692 SmallVector<int, 8> MaskVec;
6693 for (unsigned i = 0; i != NumElems; i += Scale) {
6695 for (unsigned j = 0; j != Scale; ++j) {
6696 int EltIdx = SVOp->getMaskElt(i+j);
6700 StartIdx = (EltIdx / Scale);
6701 if (EltIdx != (int)(StartIdx*Scale + j))
6704 MaskVec.push_back(StartIdx);
6707 SDValue V1 = DAG.getNode(ISD::BITCAST, dl, NewVT, SVOp->getOperand(0));
6708 SDValue V2 = DAG.getNode(ISD::BITCAST, dl, NewVT, SVOp->getOperand(1));
6709 return DAG.getVectorShuffle(NewVT, dl, V1, V2, &MaskVec[0]);
6712 /// getVZextMovL - Return a zero-extending vector move low node.
6714 static SDValue getVZextMovL(MVT VT, MVT OpVT,
6715 SDValue SrcOp, SelectionDAG &DAG,
6716 const X86Subtarget *Subtarget, SDLoc dl) {
6717 if (VT == MVT::v2f64 || VT == MVT::v4f32) {
6718 LoadSDNode *LD = NULL;
6719 if (!isScalarLoadToVector(SrcOp.getNode(), &LD))
6720 LD = dyn_cast<LoadSDNode>(SrcOp);
6722 // movssrr and movsdrr do not clear top bits. Try to use movd, movq
6724 MVT ExtVT = (OpVT == MVT::v2f64) ? MVT::i64 : MVT::i32;
6725 if ((ExtVT != MVT::i64 || Subtarget->is64Bit()) &&
6726 SrcOp.getOpcode() == ISD::SCALAR_TO_VECTOR &&
6727 SrcOp.getOperand(0).getOpcode() == ISD::BITCAST &&
6728 SrcOp.getOperand(0).getOperand(0).getValueType() == ExtVT) {
6730 OpVT = (OpVT == MVT::v2f64) ? MVT::v2i64 : MVT::v4i32;
6731 return DAG.getNode(ISD::BITCAST, dl, VT,
6732 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT,
6733 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
6741 return DAG.getNode(ISD::BITCAST, dl, VT,
6742 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT,
6743 DAG.getNode(ISD::BITCAST, dl,
6747 /// LowerVECTOR_SHUFFLE_256 - Handle all 256-bit wide vectors shuffles
6748 /// which could not be matched by any known target speficic shuffle
6750 LowerVECTOR_SHUFFLE_256(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
6752 SDValue NewOp = Compact8x32ShuffleNode(SVOp, DAG);
6753 if (NewOp.getNode())
6756 MVT VT = SVOp->getSimpleValueType(0);
6758 unsigned NumElems = VT.getVectorNumElements();
6759 unsigned NumLaneElems = NumElems / 2;
6762 MVT EltVT = VT.getVectorElementType();
6763 MVT NVT = MVT::getVectorVT(EltVT, NumLaneElems);
6766 SmallVector<int, 16> Mask;
6767 for (unsigned l = 0; l < 2; ++l) {
6768 // Build a shuffle mask for the output, discovering on the fly which
6769 // input vectors to use as shuffle operands (recorded in InputUsed).
6770 // If building a suitable shuffle vector proves too hard, then bail
6771 // out with UseBuildVector set.
6772 bool UseBuildVector = false;
6773 int InputUsed[2] = { -1, -1 }; // Not yet discovered.
6774 unsigned LaneStart = l * NumLaneElems;
6775 for (unsigned i = 0; i != NumLaneElems; ++i) {
6776 // The mask element. This indexes into the input.
6777 int Idx = SVOp->getMaskElt(i+LaneStart);
6779 // the mask element does not index into any input vector.
6784 // The input vector this mask element indexes into.
6785 int Input = Idx / NumLaneElems;
6787 // Turn the index into an offset from the start of the input vector.
6788 Idx -= Input * NumLaneElems;
6790 // Find or create a shuffle vector operand to hold this input.
6792 for (OpNo = 0; OpNo < array_lengthof(InputUsed); ++OpNo) {
6793 if (InputUsed[OpNo] == Input)
6794 // This input vector is already an operand.
6796 if (InputUsed[OpNo] < 0) {
6797 // Create a new operand for this input vector.
6798 InputUsed[OpNo] = Input;
6803 if (OpNo >= array_lengthof(InputUsed)) {
6804 // More than two input vectors used! Give up on trying to create a
6805 // shuffle vector. Insert all elements into a BUILD_VECTOR instead.
6806 UseBuildVector = true;
6810 // Add the mask index for the new shuffle vector.
6811 Mask.push_back(Idx + OpNo * NumLaneElems);
6814 if (UseBuildVector) {
6815 SmallVector<SDValue, 16> SVOps;
6816 for (unsigned i = 0; i != NumLaneElems; ++i) {
6817 // The mask element. This indexes into the input.
6818 int Idx = SVOp->getMaskElt(i+LaneStart);
6820 SVOps.push_back(DAG.getUNDEF(EltVT));
6824 // The input vector this mask element indexes into.
6825 int Input = Idx / NumElems;
6827 // Turn the index into an offset from the start of the input vector.
6828 Idx -= Input * NumElems;
6830 // Extract the vector element by hand.
6831 SVOps.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT,
6832 SVOp->getOperand(Input),
6833 DAG.getIntPtrConstant(Idx)));
6836 // Construct the output using a BUILD_VECTOR.
6837 Output[l] = DAG.getNode(ISD::BUILD_VECTOR, dl, NVT, &SVOps[0],
6839 } else if (InputUsed[0] < 0) {
6840 // No input vectors were used! The result is undefined.
6841 Output[l] = DAG.getUNDEF(NVT);
6843 SDValue Op0 = Extract128BitVector(SVOp->getOperand(InputUsed[0] / 2),
6844 (InputUsed[0] % 2) * NumLaneElems,
6846 // If only one input was used, use an undefined vector for the other.
6847 SDValue Op1 = (InputUsed[1] < 0) ? DAG.getUNDEF(NVT) :
6848 Extract128BitVector(SVOp->getOperand(InputUsed[1] / 2),
6849 (InputUsed[1] % 2) * NumLaneElems, DAG, dl);
6850 // At least one input vector was used. Create a new shuffle vector.
6851 Output[l] = DAG.getVectorShuffle(NVT, dl, Op0, Op1, &Mask[0]);
6857 // Concatenate the result back
6858 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, Output[0], Output[1]);
6861 /// LowerVECTOR_SHUFFLE_128v4 - Handle all 128-bit wide vectors with
6862 /// 4 elements, and match them with several different shuffle types.
6864 LowerVECTOR_SHUFFLE_128v4(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
6865 SDValue V1 = SVOp->getOperand(0);
6866 SDValue V2 = SVOp->getOperand(1);
6868 MVT VT = SVOp->getSimpleValueType(0);
6870 assert(VT.is128BitVector() && "Unsupported vector size");
6872 std::pair<int, int> Locs[4];
6873 int Mask1[] = { -1, -1, -1, -1 };
6874 SmallVector<int, 8> PermMask(SVOp->getMask().begin(), SVOp->getMask().end());
6878 for (unsigned i = 0; i != 4; ++i) {
6879 int Idx = PermMask[i];
6881 Locs[i] = std::make_pair(-1, -1);
6883 assert(Idx < 8 && "Invalid VECTOR_SHUFFLE index!");
6885 Locs[i] = std::make_pair(0, NumLo);
6889 Locs[i] = std::make_pair(1, NumHi);
6891 Mask1[2+NumHi] = Idx;
6897 if (NumLo <= 2 && NumHi <= 2) {
6898 // If no more than two elements come from either vector. This can be
6899 // implemented with two shuffles. First shuffle gather the elements.
6900 // The second shuffle, which takes the first shuffle as both of its
6901 // vector operands, put the elements into the right order.
6902 V1 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
6904 int Mask2[] = { -1, -1, -1, -1 };
6906 for (unsigned i = 0; i != 4; ++i)
6907 if (Locs[i].first != -1) {
6908 unsigned Idx = (i < 2) ? 0 : 4;
6909 Idx += Locs[i].first * 2 + Locs[i].second;
6913 return DAG.getVectorShuffle(VT, dl, V1, V1, &Mask2[0]);
6916 if (NumLo == 3 || NumHi == 3) {
6917 // Otherwise, we must have three elements from one vector, call it X, and
6918 // one element from the other, call it Y. First, use a shufps to build an
6919 // intermediate vector with the one element from Y and the element from X
6920 // that will be in the same half in the final destination (the indexes don't
6921 // matter). Then, use a shufps to build the final vector, taking the half
6922 // containing the element from Y from the intermediate, and the other half
6925 // Normalize it so the 3 elements come from V1.
6926 CommuteVectorShuffleMask(PermMask, 4);
6930 // Find the element from V2.
6932 for (HiIndex = 0; HiIndex < 3; ++HiIndex) {
6933 int Val = PermMask[HiIndex];
6940 Mask1[0] = PermMask[HiIndex];
6942 Mask1[2] = PermMask[HiIndex^1];
6944 V2 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
6947 Mask1[0] = PermMask[0];
6948 Mask1[1] = PermMask[1];
6949 Mask1[2] = HiIndex & 1 ? 6 : 4;
6950 Mask1[3] = HiIndex & 1 ? 4 : 6;
6951 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
6954 Mask1[0] = HiIndex & 1 ? 2 : 0;
6955 Mask1[1] = HiIndex & 1 ? 0 : 2;
6956 Mask1[2] = PermMask[2];
6957 Mask1[3] = PermMask[3];
6962 return DAG.getVectorShuffle(VT, dl, V2, V1, &Mask1[0]);
6965 // Break it into (shuffle shuffle_hi, shuffle_lo).
6966 int LoMask[] = { -1, -1, -1, -1 };
6967 int HiMask[] = { -1, -1, -1, -1 };
6969 int *MaskPtr = LoMask;
6970 unsigned MaskIdx = 0;
6973 for (unsigned i = 0; i != 4; ++i) {
6980 int Idx = PermMask[i];
6982 Locs[i] = std::make_pair(-1, -1);
6983 } else if (Idx < 4) {
6984 Locs[i] = std::make_pair(MaskIdx, LoIdx);
6985 MaskPtr[LoIdx] = Idx;
6988 Locs[i] = std::make_pair(MaskIdx, HiIdx);
6989 MaskPtr[HiIdx] = Idx;
6994 SDValue LoShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &LoMask[0]);
6995 SDValue HiShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &HiMask[0]);
6996 int MaskOps[] = { -1, -1, -1, -1 };
6997 for (unsigned i = 0; i != 4; ++i)
6998 if (Locs[i].first != -1)
6999 MaskOps[i] = Locs[i].first * 4 + Locs[i].second;
7000 return DAG.getVectorShuffle(VT, dl, LoShuffle, HiShuffle, &MaskOps[0]);
7003 static bool MayFoldVectorLoad(SDValue V) {
7004 while (V.hasOneUse() && V.getOpcode() == ISD::BITCAST)
7005 V = V.getOperand(0);
7007 if (V.hasOneUse() && V.getOpcode() == ISD::SCALAR_TO_VECTOR)
7008 V = V.getOperand(0);
7009 if (V.hasOneUse() && V.getOpcode() == ISD::BUILD_VECTOR &&
7010 V.getNumOperands() == 2 && V.getOperand(1).getOpcode() == ISD::UNDEF)
7011 // BUILD_VECTOR (load), undef
7012 V = V.getOperand(0);
7014 return MayFoldLoad(V);
7018 SDValue getMOVDDup(SDValue &Op, SDLoc &dl, SDValue V1, SelectionDAG &DAG) {
7019 MVT VT = Op.getSimpleValueType();
7021 // Canonizalize to v2f64.
7022 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, V1);
7023 return DAG.getNode(ISD::BITCAST, dl, VT,
7024 getTargetShuffleNode(X86ISD::MOVDDUP, dl, MVT::v2f64,
7029 SDValue getMOVLowToHigh(SDValue &Op, SDLoc &dl, SelectionDAG &DAG,
7031 SDValue V1 = Op.getOperand(0);
7032 SDValue V2 = Op.getOperand(1);
7033 MVT VT = Op.getSimpleValueType();
7035 assert(VT != MVT::v2i64 && "unsupported shuffle type");
7037 if (HasSSE2 && VT == MVT::v2f64)
7038 return getTargetShuffleNode(X86ISD::MOVLHPD, dl, VT, V1, V2, DAG);
7040 // v4f32 or v4i32: canonizalized to v4f32 (which is legal for SSE1)
7041 return DAG.getNode(ISD::BITCAST, dl, VT,
7042 getTargetShuffleNode(X86ISD::MOVLHPS, dl, MVT::v4f32,
7043 DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V1),
7044 DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V2), DAG));
7048 SDValue getMOVHighToLow(SDValue &Op, SDLoc &dl, SelectionDAG &DAG) {
7049 SDValue V1 = Op.getOperand(0);
7050 SDValue V2 = Op.getOperand(1);
7051 MVT VT = Op.getSimpleValueType();
7053 assert((VT == MVT::v4i32 || VT == MVT::v4f32) &&
7054 "unsupported shuffle type");
7056 if (V2.getOpcode() == ISD::UNDEF)
7060 return getTargetShuffleNode(X86ISD::MOVHLPS, dl, VT, V1, V2, DAG);
7064 SDValue getMOVLP(SDValue &Op, SDLoc &dl, SelectionDAG &DAG, bool HasSSE2) {
7065 SDValue V1 = Op.getOperand(0);
7066 SDValue V2 = Op.getOperand(1);
7067 MVT VT = Op.getSimpleValueType();
7068 unsigned NumElems = VT.getVectorNumElements();
7070 // Use MOVLPS and MOVLPD in case V1 or V2 are loads. During isel, the second
7071 // operand of these instructions is only memory, so check if there's a
7072 // potencial load folding here, otherwise use SHUFPS or MOVSD to match the
7074 bool CanFoldLoad = false;
7076 // Trivial case, when V2 comes from a load.
7077 if (MayFoldVectorLoad(V2))
7080 // When V1 is a load, it can be folded later into a store in isel, example:
7081 // (store (v4f32 (X86Movlps (load addr:$src1), VR128:$src2)), addr:$src1)
7083 // (MOVLPSmr addr:$src1, VR128:$src2)
7084 // So, recognize this potential and also use MOVLPS or MOVLPD
7085 else if (MayFoldVectorLoad(V1) && MayFoldIntoStore(Op))
7088 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
7090 if (HasSSE2 && NumElems == 2)
7091 return getTargetShuffleNode(X86ISD::MOVLPD, dl, VT, V1, V2, DAG);
7094 // If we don't care about the second element, proceed to use movss.
7095 if (SVOp->getMaskElt(1) != -1)
7096 return getTargetShuffleNode(X86ISD::MOVLPS, dl, VT, V1, V2, DAG);
7099 // movl and movlp will both match v2i64, but v2i64 is never matched by
7100 // movl earlier because we make it strict to avoid messing with the movlp load
7101 // folding logic (see the code above getMOVLP call). Match it here then,
7102 // this is horrible, but will stay like this until we move all shuffle
7103 // matching to x86 specific nodes. Note that for the 1st condition all
7104 // types are matched with movsd.
7106 // FIXME: isMOVLMask should be checked and matched before getMOVLP,
7107 // as to remove this logic from here, as much as possible
7108 if (NumElems == 2 || !isMOVLMask(SVOp->getMask(), VT))
7109 return getTargetShuffleNode(X86ISD::MOVSD, dl, VT, V1, V2, DAG);
7110 return getTargetShuffleNode(X86ISD::MOVSS, dl, VT, V1, V2, DAG);
7113 assert(VT != MVT::v4i32 && "unsupported shuffle type");
7115 // Invert the operand order and use SHUFPS to match it.
7116 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V2, V1,
7117 getShuffleSHUFImmediate(SVOp), DAG);
7120 // Reduce a vector shuffle to zext.
7121 static SDValue LowerVectorIntExtend(SDValue Op, const X86Subtarget *Subtarget,
7122 SelectionDAG &DAG) {
7123 // PMOVZX is only available from SSE41.
7124 if (!Subtarget->hasSSE41())
7127 MVT VT = Op.getSimpleValueType();
7129 // Only AVX2 support 256-bit vector integer extending.
7130 if (!Subtarget->hasInt256() && VT.is256BitVector())
7133 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
7135 SDValue V1 = Op.getOperand(0);
7136 SDValue V2 = Op.getOperand(1);
7137 unsigned NumElems = VT.getVectorNumElements();
7139 // Extending is an unary operation and the element type of the source vector
7140 // won't be equal to or larger than i64.
7141 if (V2.getOpcode() != ISD::UNDEF || !VT.isInteger() ||
7142 VT.getVectorElementType() == MVT::i64)
7145 // Find the expansion ratio, e.g. expanding from i8 to i32 has a ratio of 4.
7146 unsigned Shift = 1; // Start from 2, i.e. 1 << 1.
7147 while ((1U << Shift) < NumElems) {
7148 if (SVOp->getMaskElt(1U << Shift) == 1)
7151 // The maximal ratio is 8, i.e. from i8 to i64.
7156 // Check the shuffle mask.
7157 unsigned Mask = (1U << Shift) - 1;
7158 for (unsigned i = 0; i != NumElems; ++i) {
7159 int EltIdx = SVOp->getMaskElt(i);
7160 if ((i & Mask) != 0 && EltIdx != -1)
7162 if ((i & Mask) == 0 && (unsigned)EltIdx != (i >> Shift))
7166 unsigned NBits = VT.getVectorElementType().getSizeInBits() << Shift;
7167 MVT NeVT = MVT::getIntegerVT(NBits);
7168 MVT NVT = MVT::getVectorVT(NeVT, NumElems >> Shift);
7170 if (!DAG.getTargetLoweringInfo().isTypeLegal(NVT))
7173 // Simplify the operand as it's prepared to be fed into shuffle.
7174 unsigned SignificantBits = NVT.getSizeInBits() >> Shift;
7175 if (V1.getOpcode() == ISD::BITCAST &&
7176 V1.getOperand(0).getOpcode() == ISD::SCALAR_TO_VECTOR &&
7177 V1.getOperand(0).getOperand(0).getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
7178 V1.getOperand(0).getOperand(0)
7179 .getSimpleValueType().getSizeInBits() == SignificantBits) {
7180 // (bitcast (sclr2vec (ext_vec_elt x))) -> (bitcast x)
7181 SDValue V = V1.getOperand(0).getOperand(0).getOperand(0);
7182 ConstantSDNode *CIdx =
7183 dyn_cast<ConstantSDNode>(V1.getOperand(0).getOperand(0).getOperand(1));
7184 // If it's foldable, i.e. normal load with single use, we will let code
7185 // selection to fold it. Otherwise, we will short the conversion sequence.
7186 if (CIdx && CIdx->getZExtValue() == 0 &&
7187 (!ISD::isNormalLoad(V.getNode()) || !V.hasOneUse())) {
7188 MVT FullVT = V.getSimpleValueType();
7189 MVT V1VT = V1.getSimpleValueType();
7190 if (FullVT.getSizeInBits() > V1VT.getSizeInBits()) {
7191 // The "ext_vec_elt" node is wider than the result node.
7192 // In this case we should extract subvector from V.
7193 // (bitcast (sclr2vec (ext_vec_elt x))) -> (bitcast (extract_subvector x)).
7194 unsigned Ratio = FullVT.getSizeInBits() / V1VT.getSizeInBits();
7195 MVT SubVecVT = MVT::getVectorVT(FullVT.getVectorElementType(),
7196 FullVT.getVectorNumElements()/Ratio);
7197 V = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SubVecVT, V,
7198 DAG.getIntPtrConstant(0));
7200 V1 = DAG.getNode(ISD::BITCAST, DL, V1VT, V);
7204 return DAG.getNode(ISD::BITCAST, DL, VT,
7205 DAG.getNode(X86ISD::VZEXT, DL, NVT, V1));
7209 NormalizeVectorShuffle(SDValue Op, const X86Subtarget *Subtarget,
7210 SelectionDAG &DAG) {
7211 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
7212 MVT VT = Op.getSimpleValueType();
7214 SDValue V1 = Op.getOperand(0);
7215 SDValue V2 = Op.getOperand(1);
7217 if (isZeroShuffle(SVOp))
7218 return getZeroVector(VT, Subtarget, DAG, dl);
7220 // Handle splat operations
7221 if (SVOp->isSplat()) {
7222 // Use vbroadcast whenever the splat comes from a foldable load
7223 SDValue Broadcast = LowerVectorBroadcast(Op, Subtarget, DAG);
7224 if (Broadcast.getNode())
7228 // Check integer expanding shuffles.
7229 SDValue NewOp = LowerVectorIntExtend(Op, Subtarget, DAG);
7230 if (NewOp.getNode())
7233 // If the shuffle can be profitably rewritten as a narrower shuffle, then
7235 if (VT == MVT::v8i16 || VT == MVT::v16i8 ||
7236 VT == MVT::v16i16 || VT == MVT::v32i8) {
7237 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG);
7238 if (NewOp.getNode())
7239 return DAG.getNode(ISD::BITCAST, dl, VT, NewOp);
7240 } else if ((VT == MVT::v4i32 ||
7241 (VT == MVT::v4f32 && Subtarget->hasSSE2()))) {
7242 // FIXME: Figure out a cleaner way to do this.
7243 // Try to make use of movq to zero out the top part.
7244 if (ISD::isBuildVectorAllZeros(V2.getNode())) {
7245 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG);
7246 if (NewOp.getNode()) {
7247 MVT NewVT = NewOp.getSimpleValueType();
7248 if (isCommutedMOVLMask(cast<ShuffleVectorSDNode>(NewOp)->getMask(),
7249 NewVT, true, false))
7250 return getVZextMovL(VT, NewVT, NewOp.getOperand(0),
7251 DAG, Subtarget, dl);
7253 } else if (ISD::isBuildVectorAllZeros(V1.getNode())) {
7254 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG);
7255 if (NewOp.getNode()) {
7256 MVT NewVT = NewOp.getSimpleValueType();
7257 if (isMOVLMask(cast<ShuffleVectorSDNode>(NewOp)->getMask(), NewVT))
7258 return getVZextMovL(VT, NewVT, NewOp.getOperand(1),
7259 DAG, Subtarget, dl);
7267 X86TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const {
7268 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
7269 SDValue V1 = Op.getOperand(0);
7270 SDValue V2 = Op.getOperand(1);
7271 MVT VT = Op.getSimpleValueType();
7273 unsigned NumElems = VT.getVectorNumElements();
7274 bool V1IsUndef = V1.getOpcode() == ISD::UNDEF;
7275 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
7276 bool V1IsSplat = false;
7277 bool V2IsSplat = false;
7278 bool HasSSE2 = Subtarget->hasSSE2();
7279 bool HasFp256 = Subtarget->hasFp256();
7280 bool HasInt256 = Subtarget->hasInt256();
7281 MachineFunction &MF = DAG.getMachineFunction();
7282 bool OptForSize = MF.getFunction()->getAttributes().
7283 hasAttribute(AttributeSet::FunctionIndex, Attribute::OptimizeForSize);
7285 assert(VT.getSizeInBits() != 64 && "Can't lower MMX shuffles");
7287 if (V1IsUndef && V2IsUndef)
7288 return DAG.getUNDEF(VT);
7290 assert(!V1IsUndef && "Op 1 of shuffle should not be undef");
7292 // Vector shuffle lowering takes 3 steps:
7294 // 1) Normalize the input vectors. Here splats, zeroed vectors, profitable
7295 // narrowing and commutation of operands should be handled.
7296 // 2) Matching of shuffles with known shuffle masks to x86 target specific
7298 // 3) Rewriting of unmatched masks into new generic shuffle operations,
7299 // so the shuffle can be broken into other shuffles and the legalizer can
7300 // try the lowering again.
7302 // The general idea is that no vector_shuffle operation should be left to
7303 // be matched during isel, all of them must be converted to a target specific
7306 // Normalize the input vectors. Here splats, zeroed vectors, profitable
7307 // narrowing and commutation of operands should be handled. The actual code
7308 // doesn't include all of those, work in progress...
7309 SDValue NewOp = NormalizeVectorShuffle(Op, Subtarget, DAG);
7310 if (NewOp.getNode())
7313 SmallVector<int, 8> M(SVOp->getMask().begin(), SVOp->getMask().end());
7315 // NOTE: isPSHUFDMask can also match both masks below (unpckl_undef and
7316 // unpckh_undef). Only use pshufd if speed is more important than size.
7317 if (OptForSize && isUNPCKL_v_undef_Mask(M, VT, HasInt256))
7318 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
7319 if (OptForSize && isUNPCKH_v_undef_Mask(M, VT, HasInt256))
7320 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
7322 if (isMOVDDUPMask(M, VT) && Subtarget->hasSSE3() &&
7323 V2IsUndef && MayFoldVectorLoad(V1))
7324 return getMOVDDup(Op, dl, V1, DAG);
7326 if (isMOVHLPS_v_undef_Mask(M, VT))
7327 return getMOVHighToLow(Op, dl, DAG);
7329 // Use to match splats
7330 if (HasSSE2 && isUNPCKHMask(M, VT, HasInt256) && V2IsUndef &&
7331 (VT == MVT::v2f64 || VT == MVT::v2i64))
7332 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
7334 if (isPSHUFDMask(M, VT)) {
7335 // The actual implementation will match the mask in the if above and then
7336 // during isel it can match several different instructions, not only pshufd
7337 // as its name says, sad but true, emulate the behavior for now...
7338 if (isMOVDDUPMask(M, VT) && ((VT == MVT::v4f32 || VT == MVT::v2i64)))
7339 return getTargetShuffleNode(X86ISD::MOVLHPS, dl, VT, V1, V1, DAG);
7341 unsigned TargetMask = getShuffleSHUFImmediate(SVOp);
7343 if (HasSSE2 && (VT == MVT::v4f32 || VT == MVT::v4i32))
7344 return getTargetShuffleNode(X86ISD::PSHUFD, dl, VT, V1, TargetMask, DAG);
7346 if (HasFp256 && (VT == MVT::v4f32 || VT == MVT::v2f64))
7347 return getTargetShuffleNode(X86ISD::VPERMILP, dl, VT, V1, TargetMask,
7350 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V1, V1,
7354 if (isPALIGNRMask(M, VT, Subtarget))
7355 return getTargetShuffleNode(X86ISD::PALIGNR, dl, VT, V1, V2,
7356 getShufflePALIGNRImmediate(SVOp),
7359 // Check if this can be converted into a logical shift.
7360 bool isLeft = false;
7363 bool isShift = HasSSE2 && isVectorShift(SVOp, DAG, isLeft, ShVal, ShAmt);
7364 if (isShift && ShVal.hasOneUse()) {
7365 // If the shifted value has multiple uses, it may be cheaper to use
7366 // v_set0 + movlhps or movhlps, etc.
7367 MVT EltVT = VT.getVectorElementType();
7368 ShAmt *= EltVT.getSizeInBits();
7369 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl);
7372 if (isMOVLMask(M, VT)) {
7373 if (ISD::isBuildVectorAllZeros(V1.getNode()))
7374 return getVZextMovL(VT, VT, V2, DAG, Subtarget, dl);
7375 if (!isMOVLPMask(M, VT)) {
7376 if (HasSSE2 && (VT == MVT::v2i64 || VT == MVT::v2f64))
7377 return getTargetShuffleNode(X86ISD::MOVSD, dl, VT, V1, V2, DAG);
7379 if (VT == MVT::v4i32 || VT == MVT::v4f32)
7380 return getTargetShuffleNode(X86ISD::MOVSS, dl, VT, V1, V2, DAG);
7384 // FIXME: fold these into legal mask.
7385 if (isMOVLHPSMask(M, VT) && !isUNPCKLMask(M, VT, HasInt256))
7386 return getMOVLowToHigh(Op, dl, DAG, HasSSE2);
7388 if (isMOVHLPSMask(M, VT))
7389 return getMOVHighToLow(Op, dl, DAG);
7391 if (V2IsUndef && isMOVSHDUPMask(M, VT, Subtarget))
7392 return getTargetShuffleNode(X86ISD::MOVSHDUP, dl, VT, V1, DAG);
7394 if (V2IsUndef && isMOVSLDUPMask(M, VT, Subtarget))
7395 return getTargetShuffleNode(X86ISD::MOVSLDUP, dl, VT, V1, DAG);
7397 if (isMOVLPMask(M, VT))
7398 return getMOVLP(Op, dl, DAG, HasSSE2);
7400 if (ShouldXformToMOVHLPS(M, VT) ||
7401 ShouldXformToMOVLP(V1.getNode(), V2.getNode(), M, VT))
7402 return CommuteVectorShuffle(SVOp, DAG);
7405 // No better options. Use a vshldq / vsrldq.
7406 MVT EltVT = VT.getVectorElementType();
7407 ShAmt *= EltVT.getSizeInBits();
7408 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl);
7411 bool Commuted = false;
7412 // FIXME: This should also accept a bitcast of a splat? Be careful, not
7413 // 1,1,1,1 -> v8i16 though.
7414 V1IsSplat = isSplatVector(V1.getNode());
7415 V2IsSplat = isSplatVector(V2.getNode());
7417 // Canonicalize the splat or undef, if present, to be on the RHS.
7418 if (!V2IsUndef && V1IsSplat && !V2IsSplat) {
7419 CommuteVectorShuffleMask(M, NumElems);
7421 std::swap(V1IsSplat, V2IsSplat);
7425 if (isCommutedMOVLMask(M, VT, V2IsSplat, V2IsUndef)) {
7426 // Shuffling low element of v1 into undef, just return v1.
7429 // If V2 is a splat, the mask may be malformed such as <4,3,3,3>, which
7430 // the instruction selector will not match, so get a canonical MOVL with
7431 // swapped operands to undo the commute.
7432 return getMOVL(DAG, dl, VT, V2, V1);
7435 if (isUNPCKLMask(M, VT, HasInt256))
7436 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG);
7438 if (isUNPCKHMask(M, VT, HasInt256))
7439 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG);
7442 // Normalize mask so all entries that point to V2 points to its first
7443 // element then try to match unpck{h|l} again. If match, return a
7444 // new vector_shuffle with the corrected mask.p
7445 SmallVector<int, 8> NewMask(M.begin(), M.end());
7446 NormalizeMask(NewMask, NumElems);
7447 if (isUNPCKLMask(NewMask, VT, HasInt256, true))
7448 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG);
7449 if (isUNPCKHMask(NewMask, VT, HasInt256, true))
7450 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG);
7454 // Commute is back and try unpck* again.
7455 // FIXME: this seems wrong.
7456 CommuteVectorShuffleMask(M, NumElems);
7458 std::swap(V1IsSplat, V2IsSplat);
7461 if (isUNPCKLMask(M, VT, HasInt256))
7462 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG);
7464 if (isUNPCKHMask(M, VT, HasInt256))
7465 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG);
7468 // Normalize the node to match x86 shuffle ops if needed
7469 if (!V2IsUndef && (isSHUFPMask(M, VT, /* Commuted */ true)))
7470 return CommuteVectorShuffle(SVOp, DAG);
7472 // The checks below are all present in isShuffleMaskLegal, but they are
7473 // inlined here right now to enable us to directly emit target specific
7474 // nodes, and remove one by one until they don't return Op anymore.
7476 if (ShuffleVectorSDNode::isSplatMask(&M[0], VT) &&
7477 SVOp->getSplatIndex() == 0 && V2IsUndef) {
7478 if (VT == MVT::v2f64 || VT == MVT::v2i64)
7479 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
7482 if (isPSHUFHWMask(M, VT, HasInt256))
7483 return getTargetShuffleNode(X86ISD::PSHUFHW, dl, VT, V1,
7484 getShufflePSHUFHWImmediate(SVOp),
7487 if (isPSHUFLWMask(M, VT, HasInt256))
7488 return getTargetShuffleNode(X86ISD::PSHUFLW, dl, VT, V1,
7489 getShufflePSHUFLWImmediate(SVOp),
7492 if (isSHUFPMask(M, VT))
7493 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V1, V2,
7494 getShuffleSHUFImmediate(SVOp), DAG);
7496 if (isUNPCKL_v_undef_Mask(M, VT, HasInt256))
7497 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
7498 if (isUNPCKH_v_undef_Mask(M, VT, HasInt256))
7499 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
7501 //===--------------------------------------------------------------------===//
7502 // Generate target specific nodes for 128 or 256-bit shuffles only
7503 // supported in the AVX instruction set.
7506 // Handle VMOVDDUPY permutations
7507 if (V2IsUndef && isMOVDDUPYMask(M, VT, HasFp256))
7508 return getTargetShuffleNode(X86ISD::MOVDDUP, dl, VT, V1, DAG);
7510 // Handle VPERMILPS/D* permutations
7511 if (isVPERMILPMask(M, VT)) {
7512 if ((HasInt256 && VT == MVT::v8i32) || VT == MVT::v16i32)
7513 return getTargetShuffleNode(X86ISD::PSHUFD, dl, VT, V1,
7514 getShuffleSHUFImmediate(SVOp), DAG);
7515 return getTargetShuffleNode(X86ISD::VPERMILP, dl, VT, V1,
7516 getShuffleSHUFImmediate(SVOp), DAG);
7519 // Handle VPERM2F128/VPERM2I128 permutations
7520 if (isVPERM2X128Mask(M, VT, HasFp256))
7521 return getTargetShuffleNode(X86ISD::VPERM2X128, dl, VT, V1,
7522 V2, getShuffleVPERM2X128Immediate(SVOp), DAG);
7524 SDValue BlendOp = LowerVECTOR_SHUFFLEtoBlend(SVOp, Subtarget, DAG);
7525 if (BlendOp.getNode())
7529 if (V2IsUndef && HasInt256 && isPermImmMask(M, VT, Imm8))
7530 return getTargetShuffleNode(X86ISD::VPERMI, dl, VT, V1, Imm8, DAG);
7532 if ((V2IsUndef && HasInt256 && VT.is256BitVector() && NumElems == 8) ||
7533 VT.is512BitVector()) {
7534 MVT MaskEltVT = MVT::getIntegerVT(VT.getVectorElementType().getSizeInBits());
7535 MVT MaskVectorVT = MVT::getVectorVT(MaskEltVT, NumElems);
7536 SmallVector<SDValue, 16> permclMask;
7537 for (unsigned i = 0; i != NumElems; ++i) {
7538 permclMask.push_back(DAG.getConstant((M[i]>=0) ? M[i] : 0, MaskEltVT));
7541 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, MaskVectorVT,
7542 &permclMask[0], NumElems);
7544 // Bitcast is for VPERMPS since mask is v8i32 but node takes v8f32
7545 return DAG.getNode(X86ISD::VPERMV, dl, VT,
7546 DAG.getNode(ISD::BITCAST, dl, VT, Mask), V1);
7547 return DAG.getNode(X86ISD::VPERMV3, dl, VT,
7548 DAG.getNode(ISD::BITCAST, dl, VT, Mask), V1, V2);
7551 //===--------------------------------------------------------------------===//
7552 // Since no target specific shuffle was selected for this generic one,
7553 // lower it into other known shuffles. FIXME: this isn't true yet, but
7554 // this is the plan.
7557 // Handle v8i16 specifically since SSE can do byte extraction and insertion.
7558 if (VT == MVT::v8i16) {
7559 SDValue NewOp = LowerVECTOR_SHUFFLEv8i16(Op, Subtarget, DAG);
7560 if (NewOp.getNode())
7564 if (VT == MVT::v16i8) {
7565 SDValue NewOp = LowerVECTOR_SHUFFLEv16i8(SVOp, Subtarget, DAG);
7566 if (NewOp.getNode())
7570 if (VT == MVT::v32i8) {
7571 SDValue NewOp = LowerVECTOR_SHUFFLEv32i8(SVOp, Subtarget, DAG);
7572 if (NewOp.getNode())
7576 // Handle all 128-bit wide vectors with 4 elements, and match them with
7577 // several different shuffle types.
7578 if (NumElems == 4 && VT.is128BitVector())
7579 return LowerVECTOR_SHUFFLE_128v4(SVOp, DAG);
7581 // Handle general 256-bit shuffles
7582 if (VT.is256BitVector())
7583 return LowerVECTOR_SHUFFLE_256(SVOp, DAG);
7588 static SDValue LowerEXTRACT_VECTOR_ELT_SSE4(SDValue Op, SelectionDAG &DAG) {
7589 MVT VT = Op.getSimpleValueType();
7592 if (!Op.getOperand(0).getSimpleValueType().is128BitVector())
7595 if (VT.getSizeInBits() == 8) {
7596 SDValue Extract = DAG.getNode(X86ISD::PEXTRB, dl, MVT::i32,
7597 Op.getOperand(0), Op.getOperand(1));
7598 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
7599 DAG.getValueType(VT));
7600 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
7603 if (VT.getSizeInBits() == 16) {
7604 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
7605 // If Idx is 0, it's cheaper to do a move instead of a pextrw.
7607 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
7608 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
7609 DAG.getNode(ISD::BITCAST, dl,
7613 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, MVT::i32,
7614 Op.getOperand(0), Op.getOperand(1));
7615 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
7616 DAG.getValueType(VT));
7617 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
7620 if (VT == MVT::f32) {
7621 // EXTRACTPS outputs to a GPR32 register which will require a movd to copy
7622 // the result back to FR32 register. It's only worth matching if the
7623 // result has a single use which is a store or a bitcast to i32. And in
7624 // the case of a store, it's not worth it if the index is a constant 0,
7625 // because a MOVSSmr can be used instead, which is smaller and faster.
7626 if (!Op.hasOneUse())
7628 SDNode *User = *Op.getNode()->use_begin();
7629 if ((User->getOpcode() != ISD::STORE ||
7630 (isa<ConstantSDNode>(Op.getOperand(1)) &&
7631 cast<ConstantSDNode>(Op.getOperand(1))->isNullValue())) &&
7632 (User->getOpcode() != ISD::BITCAST ||
7633 User->getValueType(0) != MVT::i32))
7635 SDValue Extract = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
7636 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32,
7639 return DAG.getNode(ISD::BITCAST, dl, MVT::f32, Extract);
7642 if (VT == MVT::i32 || VT == MVT::i64) {
7643 // ExtractPS/pextrq works with constant index.
7644 if (isa<ConstantSDNode>(Op.getOperand(1)))
7651 X86TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op,
7652 SelectionDAG &DAG) const {
7654 SDValue Vec = Op.getOperand(0);
7655 MVT VecVT = Vec.getSimpleValueType();
7656 SDValue Idx = Op.getOperand(1);
7657 if (!isa<ConstantSDNode>(Idx)) {
7658 if (VecVT.is512BitVector() ||
7659 (VecVT.is256BitVector() && Subtarget->hasInt256() &&
7660 VecVT.getVectorElementType().getSizeInBits() == 32)) {
7663 MVT::getIntegerVT(VecVT.getVectorElementType().getSizeInBits());
7664 MVT MaskVT = MVT::getVectorVT(MaskEltVT, VecVT.getSizeInBits() /
7665 MaskEltVT.getSizeInBits());
7667 Idx = DAG.getZExtOrTrunc(Idx, dl, MaskEltVT);
7668 SDValue Mask = DAG.getNode(X86ISD::VINSERT, dl, MaskVT,
7669 getZeroVector(MaskVT, Subtarget, DAG, dl),
7670 Idx, DAG.getConstant(0, getPointerTy()));
7671 SDValue Perm = DAG.getNode(X86ISD::VPERMV, dl, VecVT, Mask, Vec);
7672 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, Op.getValueType(),
7673 Perm, DAG.getConstant(0, getPointerTy()));
7678 // If this is a 256-bit vector result, first extract the 128-bit vector and
7679 // then extract the element from the 128-bit vector.
7680 if (VecVT.is256BitVector() || VecVT.is512BitVector()) {
7682 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
7683 // Get the 128-bit vector.
7684 Vec = Extract128BitVector(Vec, IdxVal, DAG, dl);
7685 MVT EltVT = VecVT.getVectorElementType();
7687 unsigned ElemsPerChunk = 128 / EltVT.getSizeInBits();
7689 //if (IdxVal >= NumElems/2)
7690 // IdxVal -= NumElems/2;
7691 IdxVal -= (IdxVal/ElemsPerChunk)*ElemsPerChunk;
7692 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, Op.getValueType(), Vec,
7693 DAG.getConstant(IdxVal, MVT::i32));
7696 assert(VecVT.is128BitVector() && "Unexpected vector length");
7698 if (Subtarget->hasSSE41()) {
7699 SDValue Res = LowerEXTRACT_VECTOR_ELT_SSE4(Op, DAG);
7704 MVT VT = Op.getSimpleValueType();
7705 // TODO: handle v16i8.
7706 if (VT.getSizeInBits() == 16) {
7707 SDValue Vec = Op.getOperand(0);
7708 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
7710 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
7711 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
7712 DAG.getNode(ISD::BITCAST, dl,
7715 // Transform it so it match pextrw which produces a 32-bit result.
7716 MVT EltVT = MVT::i32;
7717 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, EltVT,
7718 Op.getOperand(0), Op.getOperand(1));
7719 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, EltVT, Extract,
7720 DAG.getValueType(VT));
7721 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
7724 if (VT.getSizeInBits() == 32) {
7725 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
7729 // SHUFPS the element to the lowest double word, then movss.
7730 int Mask[4] = { static_cast<int>(Idx), -1, -1, -1 };
7731 MVT VVT = Op.getOperand(0).getSimpleValueType();
7732 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
7733 DAG.getUNDEF(VVT), Mask);
7734 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
7735 DAG.getIntPtrConstant(0));
7738 if (VT.getSizeInBits() == 64) {
7739 // FIXME: .td only matches this for <2 x f64>, not <2 x i64> on 32b
7740 // FIXME: seems like this should be unnecessary if mov{h,l}pd were taught
7741 // to match extract_elt for f64.
7742 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
7746 // UNPCKHPD the element to the lowest double word, then movsd.
7747 // Note if the lower 64 bits of the result of the UNPCKHPD is then stored
7748 // to a f64mem, the whole operation is folded into a single MOVHPDmr.
7749 int Mask[2] = { 1, -1 };
7750 MVT VVT = Op.getOperand(0).getSimpleValueType();
7751 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
7752 DAG.getUNDEF(VVT), Mask);
7753 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
7754 DAG.getIntPtrConstant(0));
7760 static SDValue LowerINSERT_VECTOR_ELT_SSE4(SDValue Op, SelectionDAG &DAG) {
7761 MVT VT = Op.getSimpleValueType();
7762 MVT EltVT = VT.getVectorElementType();
7765 SDValue N0 = Op.getOperand(0);
7766 SDValue N1 = Op.getOperand(1);
7767 SDValue N2 = Op.getOperand(2);
7769 if (!VT.is128BitVector())
7772 if ((EltVT.getSizeInBits() == 8 || EltVT.getSizeInBits() == 16) &&
7773 isa<ConstantSDNode>(N2)) {
7775 if (VT == MVT::v8i16)
7776 Opc = X86ISD::PINSRW;
7777 else if (VT == MVT::v16i8)
7778 Opc = X86ISD::PINSRB;
7780 Opc = X86ISD::PINSRB;
7782 // Transform it so it match pinsr{b,w} which expects a GR32 as its second
7784 if (N1.getValueType() != MVT::i32)
7785 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
7786 if (N2.getValueType() != MVT::i32)
7787 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue());
7788 return DAG.getNode(Opc, dl, VT, N0, N1, N2);
7791 if (EltVT == MVT::f32 && isa<ConstantSDNode>(N2)) {
7792 // Bits [7:6] of the constant are the source select. This will always be
7793 // zero here. The DAG Combiner may combine an extract_elt index into these
7794 // bits. For example (insert (extract, 3), 2) could be matched by putting
7795 // the '3' into bits [7:6] of X86ISD::INSERTPS.
7796 // Bits [5:4] of the constant are the destination select. This is the
7797 // value of the incoming immediate.
7798 // Bits [3:0] of the constant are the zero mask. The DAG Combiner may
7799 // combine either bitwise AND or insert of float 0.0 to set these bits.
7800 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue() << 4);
7801 // Create this as a scalar to vector..
7802 N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4f32, N1);
7803 return DAG.getNode(X86ISD::INSERTPS, dl, VT, N0, N1, N2);
7806 if ((EltVT == MVT::i32 || EltVT == MVT::i64) && isa<ConstantSDNode>(N2)) {
7807 // PINSR* works with constant index.
7814 X86TargetLowering::LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const {
7815 MVT VT = Op.getSimpleValueType();
7816 MVT EltVT = VT.getVectorElementType();
7819 SDValue N0 = Op.getOperand(0);
7820 SDValue N1 = Op.getOperand(1);
7821 SDValue N2 = Op.getOperand(2);
7823 // If this is a 256-bit vector result, first extract the 128-bit vector,
7824 // insert the element into the extracted half and then place it back.
7825 if (VT.is256BitVector() || VT.is512BitVector()) {
7826 if (!isa<ConstantSDNode>(N2))
7829 // Get the desired 128-bit vector half.
7830 unsigned IdxVal = cast<ConstantSDNode>(N2)->getZExtValue();
7831 SDValue V = Extract128BitVector(N0, IdxVal, DAG, dl);
7833 // Insert the element into the desired half.
7834 unsigned NumEltsIn128 = 128/EltVT.getSizeInBits();
7835 unsigned IdxIn128 = IdxVal - (IdxVal/NumEltsIn128) * NumEltsIn128;
7837 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, V.getValueType(), V, N1,
7838 DAG.getConstant(IdxIn128, MVT::i32));
7840 // Insert the changed part back to the 256-bit vector
7841 return Insert128BitVector(N0, V, IdxVal, DAG, dl);
7844 if (Subtarget->hasSSE41())
7845 return LowerINSERT_VECTOR_ELT_SSE4(Op, DAG);
7847 if (EltVT == MVT::i8)
7850 if (EltVT.getSizeInBits() == 16 && isa<ConstantSDNode>(N2)) {
7851 // Transform it so it match pinsrw which expects a 16-bit value in a GR32
7852 // as its second argument.
7853 if (N1.getValueType() != MVT::i32)
7854 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
7855 if (N2.getValueType() != MVT::i32)
7856 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue());
7857 return DAG.getNode(X86ISD::PINSRW, dl, VT, N0, N1, N2);
7862 static SDValue LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) {
7864 MVT OpVT = Op.getSimpleValueType();
7866 // If this is a 256-bit vector result, first insert into a 128-bit
7867 // vector and then insert into the 256-bit vector.
7868 if (!OpVT.is128BitVector()) {
7869 // Insert into a 128-bit vector.
7870 unsigned SizeFactor = OpVT.getSizeInBits()/128;
7871 MVT VT128 = MVT::getVectorVT(OpVT.getVectorElementType(),
7872 OpVT.getVectorNumElements() / SizeFactor);
7874 Op = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT128, Op.getOperand(0));
7876 // Insert the 128-bit vector.
7877 return Insert128BitVector(DAG.getUNDEF(OpVT), Op, 0, DAG, dl);
7880 if (OpVT == MVT::v1i64 &&
7881 Op.getOperand(0).getValueType() == MVT::i64)
7882 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v1i64, Op.getOperand(0));
7884 SDValue AnyExt = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, Op.getOperand(0));
7885 assert(OpVT.is128BitVector() && "Expected an SSE type!");
7886 return DAG.getNode(ISD::BITCAST, dl, OpVT,
7887 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,AnyExt));
7890 // Lower a node with an EXTRACT_SUBVECTOR opcode. This may result in
7891 // a simple subregister reference or explicit instructions to grab
7892 // upper bits of a vector.
7893 static SDValue LowerEXTRACT_SUBVECTOR(SDValue Op, const X86Subtarget *Subtarget,
7894 SelectionDAG &DAG) {
7896 SDValue In = Op.getOperand(0);
7897 SDValue Idx = Op.getOperand(1);
7898 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
7899 MVT ResVT = Op.getSimpleValueType();
7900 MVT InVT = In.getSimpleValueType();
7902 if (Subtarget->hasFp256()) {
7903 if (ResVT.is128BitVector() &&
7904 (InVT.is256BitVector() || InVT.is512BitVector()) &&
7905 isa<ConstantSDNode>(Idx)) {
7906 return Extract128BitVector(In, IdxVal, DAG, dl);
7908 if (ResVT.is256BitVector() && InVT.is512BitVector() &&
7909 isa<ConstantSDNode>(Idx)) {
7910 return Extract256BitVector(In, IdxVal, DAG, dl);
7916 // Lower a node with an INSERT_SUBVECTOR opcode. This may result in a
7917 // simple superregister reference or explicit instructions to insert
7918 // the upper bits of a vector.
7919 static SDValue LowerINSERT_SUBVECTOR(SDValue Op, const X86Subtarget *Subtarget,
7920 SelectionDAG &DAG) {
7921 if (Subtarget->hasFp256()) {
7922 SDLoc dl(Op.getNode());
7923 SDValue Vec = Op.getNode()->getOperand(0);
7924 SDValue SubVec = Op.getNode()->getOperand(1);
7925 SDValue Idx = Op.getNode()->getOperand(2);
7927 if ((Op.getNode()->getSimpleValueType(0).is256BitVector() ||
7928 Op.getNode()->getSimpleValueType(0).is512BitVector()) &&
7929 SubVec.getNode()->getSimpleValueType(0).is128BitVector() &&
7930 isa<ConstantSDNode>(Idx)) {
7931 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
7932 return Insert128BitVector(Vec, SubVec, IdxVal, DAG, dl);
7935 if (Op.getNode()->getSimpleValueType(0).is512BitVector() &&
7936 SubVec.getNode()->getSimpleValueType(0).is256BitVector() &&
7937 isa<ConstantSDNode>(Idx)) {
7938 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
7939 return Insert256BitVector(Vec, SubVec, IdxVal, DAG, dl);
7945 // ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as
7946 // their target countpart wrapped in the X86ISD::Wrapper node. Suppose N is
7947 // one of the above mentioned nodes. It has to be wrapped because otherwise
7948 // Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only
7949 // be used to form addressing mode. These wrapped nodes will be selected
7952 X86TargetLowering::LowerConstantPool(SDValue Op, SelectionDAG &DAG) const {
7953 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
7955 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
7957 unsigned char OpFlag = 0;
7958 unsigned WrapperKind = X86ISD::Wrapper;
7959 CodeModel::Model M = getTargetMachine().getCodeModel();
7961 if (Subtarget->isPICStyleRIPRel() &&
7962 (M == CodeModel::Small || M == CodeModel::Kernel))
7963 WrapperKind = X86ISD::WrapperRIP;
7964 else if (Subtarget->isPICStyleGOT())
7965 OpFlag = X86II::MO_GOTOFF;
7966 else if (Subtarget->isPICStyleStubPIC())
7967 OpFlag = X86II::MO_PIC_BASE_OFFSET;
7969 SDValue Result = DAG.getTargetConstantPool(CP->getConstVal(), getPointerTy(),
7971 CP->getOffset(), OpFlag);
7973 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
7974 // With PIC, the address is actually $g + Offset.
7976 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
7977 DAG.getNode(X86ISD::GlobalBaseReg,
7978 SDLoc(), getPointerTy()),
7985 SDValue X86TargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) const {
7986 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
7988 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
7990 unsigned char OpFlag = 0;
7991 unsigned WrapperKind = X86ISD::Wrapper;
7992 CodeModel::Model M = getTargetMachine().getCodeModel();
7994 if (Subtarget->isPICStyleRIPRel() &&
7995 (M == CodeModel::Small || M == CodeModel::Kernel))
7996 WrapperKind = X86ISD::WrapperRIP;
7997 else if (Subtarget->isPICStyleGOT())
7998 OpFlag = X86II::MO_GOTOFF;
7999 else if (Subtarget->isPICStyleStubPIC())
8000 OpFlag = X86II::MO_PIC_BASE_OFFSET;
8002 SDValue Result = DAG.getTargetJumpTable(JT->getIndex(), getPointerTy(),
8005 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
8007 // With PIC, the address is actually $g + Offset.
8009 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
8010 DAG.getNode(X86ISD::GlobalBaseReg,
8011 SDLoc(), getPointerTy()),
8018 X86TargetLowering::LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) const {
8019 const char *Sym = cast<ExternalSymbolSDNode>(Op)->getSymbol();
8021 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
8023 unsigned char OpFlag = 0;
8024 unsigned WrapperKind = X86ISD::Wrapper;
8025 CodeModel::Model M = getTargetMachine().getCodeModel();
8027 if (Subtarget->isPICStyleRIPRel() &&
8028 (M == CodeModel::Small || M == CodeModel::Kernel)) {
8029 if (Subtarget->isTargetDarwin() || Subtarget->isTargetELF())
8030 OpFlag = X86II::MO_GOTPCREL;
8031 WrapperKind = X86ISD::WrapperRIP;
8032 } else if (Subtarget->isPICStyleGOT()) {
8033 OpFlag = X86II::MO_GOT;
8034 } else if (Subtarget->isPICStyleStubPIC()) {
8035 OpFlag = X86II::MO_DARWIN_NONLAZY_PIC_BASE;
8036 } else if (Subtarget->isPICStyleStubNoDynamic()) {
8037 OpFlag = X86II::MO_DARWIN_NONLAZY;
8040 SDValue Result = DAG.getTargetExternalSymbol(Sym, getPointerTy(), OpFlag);
8043 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
8045 // With PIC, the address is actually $g + Offset.
8046 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
8047 !Subtarget->is64Bit()) {
8048 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
8049 DAG.getNode(X86ISD::GlobalBaseReg,
8050 SDLoc(), getPointerTy()),
8054 // For symbols that require a load from a stub to get the address, emit the
8056 if (isGlobalStubReference(OpFlag))
8057 Result = DAG.getLoad(getPointerTy(), DL, DAG.getEntryNode(), Result,
8058 MachinePointerInfo::getGOT(), false, false, false, 0);
8064 X86TargetLowering::LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const {
8065 // Create the TargetBlockAddressAddress node.
8066 unsigned char OpFlags =
8067 Subtarget->ClassifyBlockAddressReference();
8068 CodeModel::Model M = getTargetMachine().getCodeModel();
8069 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
8070 int64_t Offset = cast<BlockAddressSDNode>(Op)->getOffset();
8072 SDValue Result = DAG.getTargetBlockAddress(BA, getPointerTy(), Offset,
8075 if (Subtarget->isPICStyleRIPRel() &&
8076 (M == CodeModel::Small || M == CodeModel::Kernel))
8077 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
8079 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
8081 // With PIC, the address is actually $g + Offset.
8082 if (isGlobalRelativeToPICBase(OpFlags)) {
8083 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
8084 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
8092 X86TargetLowering::LowerGlobalAddress(const GlobalValue *GV, SDLoc dl,
8093 int64_t Offset, SelectionDAG &DAG) const {
8094 // Create the TargetGlobalAddress node, folding in the constant
8095 // offset if it is legal.
8096 unsigned char OpFlags =
8097 Subtarget->ClassifyGlobalReference(GV, getTargetMachine());
8098 CodeModel::Model M = getTargetMachine().getCodeModel();
8100 if (OpFlags == X86II::MO_NO_FLAG &&
8101 X86::isOffsetSuitableForCodeModel(Offset, M)) {
8102 // A direct static reference to a global.
8103 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), Offset);
8106 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), 0, OpFlags);
8109 if (Subtarget->isPICStyleRIPRel() &&
8110 (M == CodeModel::Small || M == CodeModel::Kernel))
8111 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
8113 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
8115 // With PIC, the address is actually $g + Offset.
8116 if (isGlobalRelativeToPICBase(OpFlags)) {
8117 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
8118 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
8122 // For globals that require a load from a stub to get the address, emit the
8124 if (isGlobalStubReference(OpFlags))
8125 Result = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Result,
8126 MachinePointerInfo::getGOT(), false, false, false, 0);
8128 // If there was a non-zero offset that we didn't fold, create an explicit
8131 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(), Result,
8132 DAG.getConstant(Offset, getPointerTy()));
8138 X86TargetLowering::LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const {
8139 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
8140 int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset();
8141 return LowerGlobalAddress(GV, SDLoc(Op), Offset, DAG);
8145 GetTLSADDR(SelectionDAG &DAG, SDValue Chain, GlobalAddressSDNode *GA,
8146 SDValue *InFlag, const EVT PtrVT, unsigned ReturnReg,
8147 unsigned char OperandFlags, bool LocalDynamic = false) {
8148 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
8149 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
8151 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
8152 GA->getValueType(0),
8156 X86ISD::NodeType CallType = LocalDynamic ? X86ISD::TLSBASEADDR
8160 SDValue Ops[] = { Chain, TGA, *InFlag };
8161 Chain = DAG.getNode(CallType, dl, NodeTys, Ops, array_lengthof(Ops));
8163 SDValue Ops[] = { Chain, TGA };
8164 Chain = DAG.getNode(CallType, dl, NodeTys, Ops, array_lengthof(Ops));
8167 // TLSADDR will be codegen'ed as call. Inform MFI that function has calls.
8168 MFI->setAdjustsStack(true);
8170 SDValue Flag = Chain.getValue(1);
8171 return DAG.getCopyFromReg(Chain, dl, ReturnReg, PtrVT, Flag);
8174 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 32 bit
8176 LowerToTLSGeneralDynamicModel32(GlobalAddressSDNode *GA, SelectionDAG &DAG,
8179 SDLoc dl(GA); // ? function entry point might be better
8180 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
8181 DAG.getNode(X86ISD::GlobalBaseReg,
8182 SDLoc(), PtrVT), InFlag);
8183 InFlag = Chain.getValue(1);
8185 return GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX, X86II::MO_TLSGD);
8188 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 64 bit
8190 LowerToTLSGeneralDynamicModel64(GlobalAddressSDNode *GA, SelectionDAG &DAG,
8192 return GetTLSADDR(DAG, DAG.getEntryNode(), GA, NULL, PtrVT,
8193 X86::RAX, X86II::MO_TLSGD);
8196 static SDValue LowerToTLSLocalDynamicModel(GlobalAddressSDNode *GA,
8202 // Get the start address of the TLS block for this module.
8203 X86MachineFunctionInfo* MFI = DAG.getMachineFunction()
8204 .getInfo<X86MachineFunctionInfo>();
8205 MFI->incNumLocalDynamicTLSAccesses();
8209 Base = GetTLSADDR(DAG, DAG.getEntryNode(), GA, NULL, PtrVT, X86::RAX,
8210 X86II::MO_TLSLD, /*LocalDynamic=*/true);
8213 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
8214 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT), InFlag);
8215 InFlag = Chain.getValue(1);
8216 Base = GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX,
8217 X86II::MO_TLSLDM, /*LocalDynamic=*/true);
8220 // Note: the CleanupLocalDynamicTLSPass will remove redundant computations
8224 unsigned char OperandFlags = X86II::MO_DTPOFF;
8225 unsigned WrapperKind = X86ISD::Wrapper;
8226 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
8227 GA->getValueType(0),
8228 GA->getOffset(), OperandFlags);
8229 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
8231 // Add x@dtpoff with the base.
8232 return DAG.getNode(ISD::ADD, dl, PtrVT, Offset, Base);
8235 // Lower ISD::GlobalTLSAddress using the "initial exec" or "local exec" model.
8236 static SDValue LowerToTLSExecModel(GlobalAddressSDNode *GA, SelectionDAG &DAG,
8237 const EVT PtrVT, TLSModel::Model model,
8238 bool is64Bit, bool isPIC) {
8241 // Get the Thread Pointer, which is %gs:0 (32-bit) or %fs:0 (64-bit).
8242 Value *Ptr = Constant::getNullValue(Type::getInt8PtrTy(*DAG.getContext(),
8243 is64Bit ? 257 : 256));
8245 SDValue ThreadPointer =
8246 DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), DAG.getIntPtrConstant(0),
8247 MachinePointerInfo(Ptr), false, false, false, 0);
8249 unsigned char OperandFlags = 0;
8250 // Most TLS accesses are not RIP relative, even on x86-64. One exception is
8252 unsigned WrapperKind = X86ISD::Wrapper;
8253 if (model == TLSModel::LocalExec) {
8254 OperandFlags = is64Bit ? X86II::MO_TPOFF : X86II::MO_NTPOFF;
8255 } else if (model == TLSModel::InitialExec) {
8257 OperandFlags = X86II::MO_GOTTPOFF;
8258 WrapperKind = X86ISD::WrapperRIP;
8260 OperandFlags = isPIC ? X86II::MO_GOTNTPOFF : X86II::MO_INDNTPOFF;
8263 llvm_unreachable("Unexpected model");
8266 // emit "addl x@ntpoff,%eax" (local exec)
8267 // or "addl x@indntpoff,%eax" (initial exec)
8268 // or "addl x@gotntpoff(%ebx) ,%eax" (initial exec, 32-bit pic)
8270 DAG.getTargetGlobalAddress(GA->getGlobal(), dl, GA->getValueType(0),
8271 GA->getOffset(), OperandFlags);
8272 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
8274 if (model == TLSModel::InitialExec) {
8275 if (isPIC && !is64Bit) {
8276 Offset = DAG.getNode(ISD::ADD, dl, PtrVT,
8277 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT),
8281 Offset = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Offset,
8282 MachinePointerInfo::getGOT(), false, false, false, 0);
8285 // The address of the thread local variable is the add of the thread
8286 // pointer with the offset of the variable.
8287 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset);
8291 X86TargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const {
8293 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
8294 const GlobalValue *GV = GA->getGlobal();
8296 if (Subtarget->isTargetELF()) {
8297 TLSModel::Model model = getTargetMachine().getTLSModel(GV);
8300 case TLSModel::GeneralDynamic:
8301 if (Subtarget->is64Bit())
8302 return LowerToTLSGeneralDynamicModel64(GA, DAG, getPointerTy());
8303 return LowerToTLSGeneralDynamicModel32(GA, DAG, getPointerTy());
8304 case TLSModel::LocalDynamic:
8305 return LowerToTLSLocalDynamicModel(GA, DAG, getPointerTy(),
8306 Subtarget->is64Bit());
8307 case TLSModel::InitialExec:
8308 case TLSModel::LocalExec:
8309 return LowerToTLSExecModel(GA, DAG, getPointerTy(), model,
8310 Subtarget->is64Bit(),
8311 getTargetMachine().getRelocationModel() == Reloc::PIC_);
8313 llvm_unreachable("Unknown TLS model.");
8316 if (Subtarget->isTargetDarwin()) {
8317 // Darwin only has one model of TLS. Lower to that.
8318 unsigned char OpFlag = 0;
8319 unsigned WrapperKind = Subtarget->isPICStyleRIPRel() ?
8320 X86ISD::WrapperRIP : X86ISD::Wrapper;
8322 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
8324 bool PIC32 = (getTargetMachine().getRelocationModel() == Reloc::PIC_) &&
8325 !Subtarget->is64Bit();
8327 OpFlag = X86II::MO_TLVP_PIC_BASE;
8329 OpFlag = X86II::MO_TLVP;
8331 SDValue Result = DAG.getTargetGlobalAddress(GA->getGlobal(), DL,
8332 GA->getValueType(0),
8333 GA->getOffset(), OpFlag);
8334 SDValue Offset = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
8336 // With PIC32, the address is actually $g + Offset.
8338 Offset = DAG.getNode(ISD::ADD, DL, getPointerTy(),
8339 DAG.getNode(X86ISD::GlobalBaseReg,
8340 SDLoc(), getPointerTy()),
8343 // Lowering the machine isd will make sure everything is in the right
8345 SDValue Chain = DAG.getEntryNode();
8346 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
8347 SDValue Args[] = { Chain, Offset };
8348 Chain = DAG.getNode(X86ISD::TLSCALL, DL, NodeTys, Args, 2);
8350 // TLSCALL will be codegen'ed as call. Inform MFI that function has calls.
8351 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
8352 MFI->setAdjustsStack(true);
8354 // And our return value (tls address) is in the standard call return value
8356 unsigned Reg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
8357 return DAG.getCopyFromReg(Chain, DL, Reg, getPointerTy(),
8361 if (Subtarget->isTargetWindows() || Subtarget->isTargetMingw()) {
8362 // Just use the implicit TLS architecture
8363 // Need to generate someting similar to:
8364 // mov rdx, qword [gs:abs 58H]; Load pointer to ThreadLocalStorage
8366 // mov ecx, dword [rel _tls_index]: Load index (from C runtime)
8367 // mov rcx, qword [rdx+rcx*8]
8368 // mov eax, .tls$:tlsvar
8369 // [rax+rcx] contains the address
8370 // Windows 64bit: gs:0x58
8371 // Windows 32bit: fs:__tls_array
8373 // If GV is an alias then use the aliasee for determining
8374 // thread-localness.
8375 if (const GlobalAlias *GA = dyn_cast<GlobalAlias>(GV))
8376 GV = GA->resolveAliasedGlobal(false);
8378 SDValue Chain = DAG.getEntryNode();
8380 // Get the Thread Pointer, which is %fs:__tls_array (32-bit) or
8381 // %gs:0x58 (64-bit). On MinGW, __tls_array is not available, so directly
8382 // use its literal value of 0x2C.
8383 Value *Ptr = Constant::getNullValue(Subtarget->is64Bit()
8384 ? Type::getInt8PtrTy(*DAG.getContext(),
8386 : Type::getInt32PtrTy(*DAG.getContext(),
8389 SDValue TlsArray = Subtarget->is64Bit() ? DAG.getIntPtrConstant(0x58) :
8390 (Subtarget->isTargetMingw() ? DAG.getIntPtrConstant(0x2C) :
8391 DAG.getExternalSymbol("_tls_array", getPointerTy()));
8393 SDValue ThreadPointer = DAG.getLoad(getPointerTy(), dl, Chain, TlsArray,
8394 MachinePointerInfo(Ptr),
8395 false, false, false, 0);
8397 // Load the _tls_index variable
8398 SDValue IDX = DAG.getExternalSymbol("_tls_index", getPointerTy());
8399 if (Subtarget->is64Bit())
8400 IDX = DAG.getExtLoad(ISD::ZEXTLOAD, dl, getPointerTy(), Chain,
8401 IDX, MachinePointerInfo(), MVT::i32,
8404 IDX = DAG.getLoad(getPointerTy(), dl, Chain, IDX, MachinePointerInfo(),
8405 false, false, false, 0);
8407 SDValue Scale = DAG.getConstant(Log2_64_Ceil(TD->getPointerSize()),
8409 IDX = DAG.getNode(ISD::SHL, dl, getPointerTy(), IDX, Scale);
8411 SDValue res = DAG.getNode(ISD::ADD, dl, getPointerTy(), ThreadPointer, IDX);
8412 res = DAG.getLoad(getPointerTy(), dl, Chain, res, MachinePointerInfo(),
8413 false, false, false, 0);
8415 // Get the offset of start of .tls section
8416 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
8417 GA->getValueType(0),
8418 GA->getOffset(), X86II::MO_SECREL);
8419 SDValue Offset = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), TGA);
8421 // The address of the thread local variable is the add of the thread
8422 // pointer with the offset of the variable.
8423 return DAG.getNode(ISD::ADD, dl, getPointerTy(), res, Offset);
8426 llvm_unreachable("TLS not implemented for this target.");
8429 /// LowerShiftParts - Lower SRA_PARTS and friends, which return two i32 values
8430 /// and take a 2 x i32 value to shift plus a shift amount.
8431 SDValue X86TargetLowering::LowerShiftParts(SDValue Op, SelectionDAG &DAG) const{
8432 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
8433 EVT VT = Op.getValueType();
8434 unsigned VTBits = VT.getSizeInBits();
8436 bool isSRA = Op.getOpcode() == ISD::SRA_PARTS;
8437 SDValue ShOpLo = Op.getOperand(0);
8438 SDValue ShOpHi = Op.getOperand(1);
8439 SDValue ShAmt = Op.getOperand(2);
8440 SDValue Tmp1 = isSRA ? DAG.getNode(ISD::SRA, dl, VT, ShOpHi,
8441 DAG.getConstant(VTBits - 1, MVT::i8))
8442 : DAG.getConstant(0, VT);
8445 if (Op.getOpcode() == ISD::SHL_PARTS) {
8446 Tmp2 = DAG.getNode(X86ISD::SHLD, dl, VT, ShOpHi, ShOpLo, ShAmt);
8447 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ShAmt);
8449 Tmp2 = DAG.getNode(X86ISD::SHRD, dl, VT, ShOpLo, ShOpHi, ShAmt);
8450 Tmp3 = DAG.getNode(isSRA ? ISD::SRA : ISD::SRL, dl, VT, ShOpHi, ShAmt);
8453 SDValue AndNode = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt,
8454 DAG.getConstant(VTBits, MVT::i8));
8455 SDValue Cond = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
8456 AndNode, DAG.getConstant(0, MVT::i8));
8459 SDValue CC = DAG.getConstant(X86::COND_NE, MVT::i8);
8460 SDValue Ops0[4] = { Tmp2, Tmp3, CC, Cond };
8461 SDValue Ops1[4] = { Tmp3, Tmp1, CC, Cond };
8463 if (Op.getOpcode() == ISD::SHL_PARTS) {
8464 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0, 4);
8465 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1, 4);
8467 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0, 4);
8468 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1, 4);
8471 SDValue Ops[2] = { Lo, Hi };
8472 return DAG.getMergeValues(Ops, array_lengthof(Ops), dl);
8475 SDValue X86TargetLowering::LowerSINT_TO_FP(SDValue Op,
8476 SelectionDAG &DAG) const {
8477 EVT SrcVT = Op.getOperand(0).getValueType();
8479 if (SrcVT.isVector())
8482 assert(SrcVT.getSimpleVT() <= MVT::i64 && SrcVT.getSimpleVT() >= MVT::i16 &&
8483 "Unknown SINT_TO_FP to lower!");
8485 // These are really Legal; return the operand so the caller accepts it as
8487 if (SrcVT == MVT::i32 && isScalarFPTypeInSSEReg(Op.getValueType()))
8489 if (SrcVT == MVT::i64 && isScalarFPTypeInSSEReg(Op.getValueType()) &&
8490 Subtarget->is64Bit()) {
8495 unsigned Size = SrcVT.getSizeInBits()/8;
8496 MachineFunction &MF = DAG.getMachineFunction();
8497 int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size, false);
8498 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
8499 SDValue Chain = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
8501 MachinePointerInfo::getFixedStack(SSFI),
8503 return BuildFILD(Op, SrcVT, Chain, StackSlot, DAG);
8506 SDValue X86TargetLowering::BuildFILD(SDValue Op, EVT SrcVT, SDValue Chain,
8508 SelectionDAG &DAG) const {
8512 bool useSSE = isScalarFPTypeInSSEReg(Op.getValueType());
8514 Tys = DAG.getVTList(MVT::f64, MVT::Other, MVT::Glue);
8516 Tys = DAG.getVTList(Op.getValueType(), MVT::Other);
8518 unsigned ByteSize = SrcVT.getSizeInBits()/8;
8520 FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(StackSlot);
8521 MachineMemOperand *MMO;
8523 int SSFI = FI->getIndex();
8525 DAG.getMachineFunction()
8526 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
8527 MachineMemOperand::MOLoad, ByteSize, ByteSize);
8529 MMO = cast<LoadSDNode>(StackSlot)->getMemOperand();
8530 StackSlot = StackSlot.getOperand(1);
8532 SDValue Ops[] = { Chain, StackSlot, DAG.getValueType(SrcVT) };
8533 SDValue Result = DAG.getMemIntrinsicNode(useSSE ? X86ISD::FILD_FLAG :
8535 Tys, Ops, array_lengthof(Ops),
8539 Chain = Result.getValue(1);
8540 SDValue InFlag = Result.getValue(2);
8542 // FIXME: Currently the FST is flagged to the FILD_FLAG. This
8543 // shouldn't be necessary except that RFP cannot be live across
8544 // multiple blocks. When stackifier is fixed, they can be uncoupled.
8545 MachineFunction &MF = DAG.getMachineFunction();
8546 unsigned SSFISize = Op.getValueType().getSizeInBits()/8;
8547 int SSFI = MF.getFrameInfo()->CreateStackObject(SSFISize, SSFISize, false);
8548 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
8549 Tys = DAG.getVTList(MVT::Other);
8551 Chain, Result, StackSlot, DAG.getValueType(Op.getValueType()), InFlag
8553 MachineMemOperand *MMO =
8554 DAG.getMachineFunction()
8555 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
8556 MachineMemOperand::MOStore, SSFISize, SSFISize);
8558 Chain = DAG.getMemIntrinsicNode(X86ISD::FST, DL, Tys,
8559 Ops, array_lengthof(Ops),
8560 Op.getValueType(), MMO);
8561 Result = DAG.getLoad(Op.getValueType(), DL, Chain, StackSlot,
8562 MachinePointerInfo::getFixedStack(SSFI),
8563 false, false, false, 0);
8569 // LowerUINT_TO_FP_i64 - 64-bit unsigned integer to double expansion.
8570 SDValue X86TargetLowering::LowerUINT_TO_FP_i64(SDValue Op,
8571 SelectionDAG &DAG) const {
8572 // This algorithm is not obvious. Here it is what we're trying to output:
8575 punpckldq (c0), %xmm0 // c0: (uint4){ 0x43300000U, 0x45300000U, 0U, 0U }
8576 subpd (c1), %xmm0 // c1: (double2){ 0x1.0p52, 0x1.0p52 * 0x1.0p32 }
8580 pshufd $0x4e, %xmm0, %xmm1
8586 LLVMContext *Context = DAG.getContext();
8588 // Build some magic constants.
8589 static const uint32_t CV0[] = { 0x43300000, 0x45300000, 0, 0 };
8590 Constant *C0 = ConstantDataVector::get(*Context, CV0);
8591 SDValue CPIdx0 = DAG.getConstantPool(C0, getPointerTy(), 16);
8593 SmallVector<Constant*,2> CV1;
8595 ConstantFP::get(*Context, APFloat(APFloat::IEEEdouble,
8596 APInt(64, 0x4330000000000000ULL))));
8598 ConstantFP::get(*Context, APFloat(APFloat::IEEEdouble,
8599 APInt(64, 0x4530000000000000ULL))));
8600 Constant *C1 = ConstantVector::get(CV1);
8601 SDValue CPIdx1 = DAG.getConstantPool(C1, getPointerTy(), 16);
8603 // Load the 64-bit value into an XMM register.
8604 SDValue XR1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
8606 SDValue CLod0 = DAG.getLoad(MVT::v4i32, dl, DAG.getEntryNode(), CPIdx0,
8607 MachinePointerInfo::getConstantPool(),
8608 false, false, false, 16);
8609 SDValue Unpck1 = getUnpackl(DAG, dl, MVT::v4i32,
8610 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, XR1),
8613 SDValue CLod1 = DAG.getLoad(MVT::v2f64, dl, CLod0.getValue(1), CPIdx1,
8614 MachinePointerInfo::getConstantPool(),
8615 false, false, false, 16);
8616 SDValue XR2F = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Unpck1);
8617 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, XR2F, CLod1);
8620 if (Subtarget->hasSSE3()) {
8621 // FIXME: The 'haddpd' instruction may be slower than 'movhlps + addsd'.
8622 Result = DAG.getNode(X86ISD::FHADD, dl, MVT::v2f64, Sub, Sub);
8624 SDValue S2F = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Sub);
8625 SDValue Shuffle = getTargetShuffleNode(X86ISD::PSHUFD, dl, MVT::v4i32,
8627 Result = DAG.getNode(ISD::FADD, dl, MVT::v2f64,
8628 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Shuffle),
8632 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Result,
8633 DAG.getIntPtrConstant(0));
8636 // LowerUINT_TO_FP_i32 - 32-bit unsigned integer to float expansion.
8637 SDValue X86TargetLowering::LowerUINT_TO_FP_i32(SDValue Op,
8638 SelectionDAG &DAG) const {
8640 // FP constant to bias correct the final result.
8641 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL),
8644 // Load the 32-bit value into an XMM register.
8645 SDValue Load = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,
8648 // Zero out the upper parts of the register.
8649 Load = getShuffleVectorZeroOrUndef(Load, 0, true, Subtarget, DAG);
8651 Load = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
8652 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Load),
8653 DAG.getIntPtrConstant(0));
8655 // Or the load with the bias.
8656 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64,
8657 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
8658 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
8660 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
8661 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
8662 MVT::v2f64, Bias)));
8663 Or = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
8664 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Or),
8665 DAG.getIntPtrConstant(0));
8667 // Subtract the bias.
8668 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Or, Bias);
8670 // Handle final rounding.
8671 EVT DestVT = Op.getValueType();
8673 if (DestVT.bitsLT(MVT::f64))
8674 return DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub,
8675 DAG.getIntPtrConstant(0));
8676 if (DestVT.bitsGT(MVT::f64))
8677 return DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub);
8679 // Handle final rounding.
8683 SDValue X86TargetLowering::lowerUINT_TO_FP_vec(SDValue Op,
8684 SelectionDAG &DAG) const {
8685 SDValue N0 = Op.getOperand(0);
8686 EVT SVT = N0.getValueType();
8689 assert((SVT == MVT::v4i8 || SVT == MVT::v4i16 ||
8690 SVT == MVT::v8i8 || SVT == MVT::v8i16) &&
8691 "Custom UINT_TO_FP is not supported!");
8693 EVT NVT = EVT::getVectorVT(*DAG.getContext(), MVT::i32,
8694 SVT.getVectorNumElements());
8695 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(),
8696 DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, N0));
8699 SDValue X86TargetLowering::LowerUINT_TO_FP(SDValue Op,
8700 SelectionDAG &DAG) const {
8701 SDValue N0 = Op.getOperand(0);
8704 if (Op.getValueType().isVector())
8705 return lowerUINT_TO_FP_vec(Op, DAG);
8707 // Since UINT_TO_FP is legal (it's marked custom), dag combiner won't
8708 // optimize it to a SINT_TO_FP when the sign bit is known zero. Perform
8709 // the optimization here.
8710 if (DAG.SignBitIsZero(N0))
8711 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(), N0);
8713 EVT SrcVT = N0.getValueType();
8714 EVT DstVT = Op.getValueType();
8715 if (SrcVT == MVT::i64 && DstVT == MVT::f64 && X86ScalarSSEf64)
8716 return LowerUINT_TO_FP_i64(Op, DAG);
8717 if (SrcVT == MVT::i32 && X86ScalarSSEf64)
8718 return LowerUINT_TO_FP_i32(Op, DAG);
8719 if (Subtarget->is64Bit() && SrcVT == MVT::i64 && DstVT == MVT::f32)
8722 // Make a 64-bit buffer, and use it to build an FILD.
8723 SDValue StackSlot = DAG.CreateStackTemporary(MVT::i64);
8724 if (SrcVT == MVT::i32) {
8725 SDValue WordOff = DAG.getConstant(4, getPointerTy());
8726 SDValue OffsetSlot = DAG.getNode(ISD::ADD, dl,
8727 getPointerTy(), StackSlot, WordOff);
8728 SDValue Store1 = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
8729 StackSlot, MachinePointerInfo(),
8731 SDValue Store2 = DAG.getStore(Store1, dl, DAG.getConstant(0, MVT::i32),
8732 OffsetSlot, MachinePointerInfo(),
8734 SDValue Fild = BuildFILD(Op, MVT::i64, Store2, StackSlot, DAG);
8738 assert(SrcVT == MVT::i64 && "Unexpected type in UINT_TO_FP");
8739 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
8740 StackSlot, MachinePointerInfo(),
8742 // For i64 source, we need to add the appropriate power of 2 if the input
8743 // was negative. This is the same as the optimization in
8744 // DAGTypeLegalizer::ExpandIntOp_UNIT_TO_FP, and for it to be safe here,
8745 // we must be careful to do the computation in x87 extended precision, not
8746 // in SSE. (The generic code can't know it's OK to do this, or how to.)
8747 int SSFI = cast<FrameIndexSDNode>(StackSlot)->getIndex();
8748 MachineMemOperand *MMO =
8749 DAG.getMachineFunction()
8750 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
8751 MachineMemOperand::MOLoad, 8, 8);
8753 SDVTList Tys = DAG.getVTList(MVT::f80, MVT::Other);
8754 SDValue Ops[] = { Store, StackSlot, DAG.getValueType(MVT::i64) };
8755 SDValue Fild = DAG.getMemIntrinsicNode(X86ISD::FILD, dl, Tys, Ops,
8756 array_lengthof(Ops), MVT::i64, MMO);
8758 APInt FF(32, 0x5F800000ULL);
8760 // Check whether the sign bit is set.
8761 SDValue SignSet = DAG.getSetCC(dl,
8762 getSetCCResultType(*DAG.getContext(), MVT::i64),
8763 Op.getOperand(0), DAG.getConstant(0, MVT::i64),
8766 // Build a 64 bit pair (0, FF) in the constant pool, with FF in the lo bits.
8767 SDValue FudgePtr = DAG.getConstantPool(
8768 ConstantInt::get(*DAG.getContext(), FF.zext(64)),
8771 // Get a pointer to FF if the sign bit was set, or to 0 otherwise.
8772 SDValue Zero = DAG.getIntPtrConstant(0);
8773 SDValue Four = DAG.getIntPtrConstant(4);
8774 SDValue Offset = DAG.getNode(ISD::SELECT, dl, Zero.getValueType(), SignSet,
8776 FudgePtr = DAG.getNode(ISD::ADD, dl, getPointerTy(), FudgePtr, Offset);
8778 // Load the value out, extending it from f32 to f80.
8779 // FIXME: Avoid the extend by constructing the right constant pool?
8780 SDValue Fudge = DAG.getExtLoad(ISD::EXTLOAD, dl, MVT::f80, DAG.getEntryNode(),
8781 FudgePtr, MachinePointerInfo::getConstantPool(),
8782 MVT::f32, false, false, 4);
8783 // Extend everything to 80 bits to force it to be done on x87.
8784 SDValue Add = DAG.getNode(ISD::FADD, dl, MVT::f80, Fild, Fudge);
8785 return DAG.getNode(ISD::FP_ROUND, dl, DstVT, Add, DAG.getIntPtrConstant(0));
8788 std::pair<SDValue,SDValue>
8789 X86TargetLowering:: FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG,
8790 bool IsSigned, bool IsReplace) const {
8793 EVT DstTy = Op.getValueType();
8795 if (!IsSigned && !isIntegerTypeFTOL(DstTy)) {
8796 assert(DstTy == MVT::i32 && "Unexpected FP_TO_UINT");
8800 assert(DstTy.getSimpleVT() <= MVT::i64 &&
8801 DstTy.getSimpleVT() >= MVT::i16 &&
8802 "Unknown FP_TO_INT to lower!");
8804 // These are really Legal.
8805 if (DstTy == MVT::i32 &&
8806 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
8807 return std::make_pair(SDValue(), SDValue());
8808 if (Subtarget->is64Bit() &&
8809 DstTy == MVT::i64 &&
8810 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
8811 return std::make_pair(SDValue(), SDValue());
8813 // We lower FP->int64 either into FISTP64 followed by a load from a temporary
8814 // stack slot, or into the FTOL runtime function.
8815 MachineFunction &MF = DAG.getMachineFunction();
8816 unsigned MemSize = DstTy.getSizeInBits()/8;
8817 int SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
8818 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
8821 if (!IsSigned && isIntegerTypeFTOL(DstTy))
8822 Opc = X86ISD::WIN_FTOL;
8824 switch (DstTy.getSimpleVT().SimpleTy) {
8825 default: llvm_unreachable("Invalid FP_TO_SINT to lower!");
8826 case MVT::i16: Opc = X86ISD::FP_TO_INT16_IN_MEM; break;
8827 case MVT::i32: Opc = X86ISD::FP_TO_INT32_IN_MEM; break;
8828 case MVT::i64: Opc = X86ISD::FP_TO_INT64_IN_MEM; break;
8831 SDValue Chain = DAG.getEntryNode();
8832 SDValue Value = Op.getOperand(0);
8833 EVT TheVT = Op.getOperand(0).getValueType();
8834 // FIXME This causes a redundant load/store if the SSE-class value is already
8835 // in memory, such as if it is on the callstack.
8836 if (isScalarFPTypeInSSEReg(TheVT)) {
8837 assert(DstTy == MVT::i64 && "Invalid FP_TO_SINT to lower!");
8838 Chain = DAG.getStore(Chain, DL, Value, StackSlot,
8839 MachinePointerInfo::getFixedStack(SSFI),
8841 SDVTList Tys = DAG.getVTList(Op.getOperand(0).getValueType(), MVT::Other);
8843 Chain, StackSlot, DAG.getValueType(TheVT)
8846 MachineMemOperand *MMO =
8847 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
8848 MachineMemOperand::MOLoad, MemSize, MemSize);
8849 Value = DAG.getMemIntrinsicNode(X86ISD::FLD, DL, Tys, Ops,
8850 array_lengthof(Ops), DstTy, MMO);
8851 Chain = Value.getValue(1);
8852 SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
8853 StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
8856 MachineMemOperand *MMO =
8857 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
8858 MachineMemOperand::MOStore, MemSize, MemSize);
8860 if (Opc != X86ISD::WIN_FTOL) {
8861 // Build the FP_TO_INT*_IN_MEM
8862 SDValue Ops[] = { Chain, Value, StackSlot };
8863 SDValue FIST = DAG.getMemIntrinsicNode(Opc, DL, DAG.getVTList(MVT::Other),
8864 Ops, array_lengthof(Ops), DstTy,
8866 return std::make_pair(FIST, StackSlot);
8868 SDValue ftol = DAG.getNode(X86ISD::WIN_FTOL, DL,
8869 DAG.getVTList(MVT::Other, MVT::Glue),
8871 SDValue eax = DAG.getCopyFromReg(ftol, DL, X86::EAX,
8872 MVT::i32, ftol.getValue(1));
8873 SDValue edx = DAG.getCopyFromReg(eax.getValue(1), DL, X86::EDX,
8874 MVT::i32, eax.getValue(2));
8875 SDValue Ops[] = { eax, edx };
8876 SDValue pair = IsReplace
8877 ? DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops, array_lengthof(Ops))
8878 : DAG.getMergeValues(Ops, array_lengthof(Ops), DL);
8879 return std::make_pair(pair, SDValue());
8883 static SDValue LowerAVXExtend(SDValue Op, SelectionDAG &DAG,
8884 const X86Subtarget *Subtarget) {
8885 MVT VT = Op->getSimpleValueType(0);
8886 SDValue In = Op->getOperand(0);
8887 MVT InVT = In.getSimpleValueType();
8890 // Optimize vectors in AVX mode:
8893 // Use vpunpcklwd for 4 lower elements v8i16 -> v4i32.
8894 // Use vpunpckhwd for 4 upper elements v8i16 -> v4i32.
8895 // Concat upper and lower parts.
8898 // Use vpunpckldq for 4 lower elements v4i32 -> v2i64.
8899 // Use vpunpckhdq for 4 upper elements v4i32 -> v2i64.
8900 // Concat upper and lower parts.
8903 if (((VT != MVT::v16i16) || (InVT != MVT::v16i8)) &&
8904 ((VT != MVT::v8i32) || (InVT != MVT::v8i16)) &&
8905 ((VT != MVT::v4i64) || (InVT != MVT::v4i32)))
8908 if (Subtarget->hasInt256())
8909 return DAG.getNode(X86ISD::VZEXT_MOVL, dl, VT, In);
8911 SDValue ZeroVec = getZeroVector(InVT, Subtarget, DAG, dl);
8912 SDValue Undef = DAG.getUNDEF(InVT);
8913 bool NeedZero = Op.getOpcode() == ISD::ZERO_EXTEND;
8914 SDValue OpLo = getUnpackl(DAG, dl, InVT, In, NeedZero ? ZeroVec : Undef);
8915 SDValue OpHi = getUnpackh(DAG, dl, InVT, In, NeedZero ? ZeroVec : Undef);
8917 MVT HVT = MVT::getVectorVT(VT.getVectorElementType(),
8918 VT.getVectorNumElements()/2);
8920 OpLo = DAG.getNode(ISD::BITCAST, dl, HVT, OpLo);
8921 OpHi = DAG.getNode(ISD::BITCAST, dl, HVT, OpHi);
8923 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi);
8926 static SDValue LowerZERO_EXTEND_AVX512(SDValue Op,
8927 SelectionDAG &DAG) {
8928 MVT VT = Op->getValueType(0).getSimpleVT();
8929 SDValue In = Op->getOperand(0);
8930 MVT InVT = In.getValueType().getSimpleVT();
8932 unsigned int NumElts = VT.getVectorNumElements();
8933 if (NumElts != 8 && NumElts != 16)
8936 if (VT.is512BitVector() && InVT.getVectorElementType() != MVT::i1)
8937 return DAG.getNode(X86ISD::VZEXT, DL, VT, In);
8939 EVT ExtVT = (NumElts == 8)? MVT::v8i64 : MVT::v16i32;
8940 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
8941 // Now we have only mask extension
8942 assert(InVT.getVectorElementType() == MVT::i1);
8943 SDValue Cst = DAG.getTargetConstant(1, ExtVT.getScalarType());
8944 const Constant *C = (dyn_cast<ConstantSDNode>(Cst))->getConstantIntValue();
8945 SDValue CP = DAG.getConstantPool(C, TLI.getPointerTy());
8946 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
8947 SDValue Ld = DAG.getLoad(Cst.getValueType(), DL, DAG.getEntryNode(), CP,
8948 MachinePointerInfo::getConstantPool(),
8949 false, false, false, Alignment);
8951 SDValue Brcst = DAG.getNode(X86ISD::VBROADCASTM, DL, ExtVT, In, Ld);
8952 if (VT.is512BitVector())
8954 return DAG.getNode(X86ISD::VTRUNC, DL, VT, Brcst);
8957 static SDValue LowerANY_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
8958 SelectionDAG &DAG) {
8959 if (Subtarget->hasFp256()) {
8960 SDValue Res = LowerAVXExtend(Op, DAG, Subtarget);
8968 static SDValue LowerZERO_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
8969 SelectionDAG &DAG) {
8971 MVT VT = Op.getSimpleValueType();
8972 SDValue In = Op.getOperand(0);
8973 MVT SVT = In.getSimpleValueType();
8975 if (VT.is512BitVector() || SVT.getVectorElementType() == MVT::i1)
8976 return LowerZERO_EXTEND_AVX512(Op, DAG);
8978 if (Subtarget->hasFp256()) {
8979 SDValue Res = LowerAVXExtend(Op, DAG, Subtarget);
8984 assert(!VT.is256BitVector() || !SVT.is128BitVector() ||
8985 VT.getVectorNumElements() != SVT.getVectorNumElements());
8989 SDValue X86TargetLowering::LowerTRUNCATE(SDValue Op, SelectionDAG &DAG) const {
8991 MVT VT = Op.getSimpleValueType();
8992 SDValue In = Op.getOperand(0);
8993 MVT InVT = In.getSimpleValueType();
8994 assert(VT.getVectorNumElements() == InVT.getVectorNumElements() &&
8995 "Invalid TRUNCATE operation");
8997 if (InVT.is512BitVector() || VT.getVectorElementType() == MVT::i1) {
8998 if (VT.getVectorElementType().getSizeInBits() >=8)
8999 return DAG.getNode(X86ISD::VTRUNC, DL, VT, In);
9001 assert(VT.getVectorElementType() == MVT::i1 && "Unexpected vector type");
9002 unsigned NumElts = InVT.getVectorNumElements();
9003 assert ((NumElts == 8 || NumElts == 16) && "Unexpected vector type");
9004 if (InVT.getSizeInBits() < 512) {
9005 MVT ExtVT = (NumElts == 16)? MVT::v16i32 : MVT::v8i64;
9006 In = DAG.getNode(ISD::SIGN_EXTEND, DL, ExtVT, In);
9009 SDValue Cst = DAG.getTargetConstant(1, InVT.getVectorElementType());
9010 const Constant *C = (dyn_cast<ConstantSDNode>(Cst))->getConstantIntValue();
9011 SDValue CP = DAG.getConstantPool(C, getPointerTy());
9012 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
9013 SDValue Ld = DAG.getLoad(Cst.getValueType(), DL, DAG.getEntryNode(), CP,
9014 MachinePointerInfo::getConstantPool(),
9015 false, false, false, Alignment);
9016 SDValue OneV = DAG.getNode(X86ISD::VBROADCAST, DL, InVT, Ld);
9017 SDValue And = DAG.getNode(ISD::AND, DL, InVT, OneV, In);
9018 return DAG.getNode(X86ISD::TESTM, DL, VT, And, And);
9021 if ((VT == MVT::v4i32) && (InVT == MVT::v4i64)) {
9022 // On AVX2, v4i64 -> v4i32 becomes VPERMD.
9023 if (Subtarget->hasInt256()) {
9024 static const int ShufMask[] = {0, 2, 4, 6, -1, -1, -1, -1};
9025 In = DAG.getNode(ISD::BITCAST, DL, MVT::v8i32, In);
9026 In = DAG.getVectorShuffle(MVT::v8i32, DL, In, DAG.getUNDEF(MVT::v8i32),
9028 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, In,
9029 DAG.getIntPtrConstant(0));
9032 // On AVX, v4i64 -> v4i32 becomes a sequence that uses PSHUFD and MOVLHPS.
9033 SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
9034 DAG.getIntPtrConstant(0));
9035 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
9036 DAG.getIntPtrConstant(2));
9038 OpLo = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpLo);
9039 OpHi = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpHi);
9042 static const int ShufMask1[] = {0, 2, 0, 0};
9043 SDValue Undef = DAG.getUNDEF(VT);
9044 OpLo = DAG.getVectorShuffle(VT, DL, OpLo, Undef, ShufMask1);
9045 OpHi = DAG.getVectorShuffle(VT, DL, OpHi, Undef, ShufMask1);
9047 // The MOVLHPS mask:
9048 static const int ShufMask2[] = {0, 1, 4, 5};
9049 return DAG.getVectorShuffle(VT, DL, OpLo, OpHi, ShufMask2);
9052 if ((VT == MVT::v8i16) && (InVT == MVT::v8i32)) {
9053 // On AVX2, v8i32 -> v8i16 becomed PSHUFB.
9054 if (Subtarget->hasInt256()) {
9055 In = DAG.getNode(ISD::BITCAST, DL, MVT::v32i8, In);
9057 SmallVector<SDValue,32> pshufbMask;
9058 for (unsigned i = 0; i < 2; ++i) {
9059 pshufbMask.push_back(DAG.getConstant(0x0, MVT::i8));
9060 pshufbMask.push_back(DAG.getConstant(0x1, MVT::i8));
9061 pshufbMask.push_back(DAG.getConstant(0x4, MVT::i8));
9062 pshufbMask.push_back(DAG.getConstant(0x5, MVT::i8));
9063 pshufbMask.push_back(DAG.getConstant(0x8, MVT::i8));
9064 pshufbMask.push_back(DAG.getConstant(0x9, MVT::i8));
9065 pshufbMask.push_back(DAG.getConstant(0xc, MVT::i8));
9066 pshufbMask.push_back(DAG.getConstant(0xd, MVT::i8));
9067 for (unsigned j = 0; j < 8; ++j)
9068 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
9070 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v32i8,
9071 &pshufbMask[0], 32);
9072 In = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v32i8, In, BV);
9073 In = DAG.getNode(ISD::BITCAST, DL, MVT::v4i64, In);
9075 static const int ShufMask[] = {0, 2, -1, -1};
9076 In = DAG.getVectorShuffle(MVT::v4i64, DL, In, DAG.getUNDEF(MVT::v4i64),
9078 In = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
9079 DAG.getIntPtrConstant(0));
9080 return DAG.getNode(ISD::BITCAST, DL, VT, In);
9083 SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v4i32, In,
9084 DAG.getIntPtrConstant(0));
9086 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v4i32, In,
9087 DAG.getIntPtrConstant(4));
9089 OpLo = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, OpLo);
9090 OpHi = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, OpHi);
9093 static const int ShufMask1[] = {0, 1, 4, 5, 8, 9, 12, 13,
9094 -1, -1, -1, -1, -1, -1, -1, -1};
9096 SDValue Undef = DAG.getUNDEF(MVT::v16i8);
9097 OpLo = DAG.getVectorShuffle(MVT::v16i8, DL, OpLo, Undef, ShufMask1);
9098 OpHi = DAG.getVectorShuffle(MVT::v16i8, DL, OpHi, Undef, ShufMask1);
9100 OpLo = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpLo);
9101 OpHi = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpHi);
9103 // The MOVLHPS Mask:
9104 static const int ShufMask2[] = {0, 1, 4, 5};
9105 SDValue res = DAG.getVectorShuffle(MVT::v4i32, DL, OpLo, OpHi, ShufMask2);
9106 return DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, res);
9109 // Handle truncation of V256 to V128 using shuffles.
9110 if (!VT.is128BitVector() || !InVT.is256BitVector())
9113 assert(Subtarget->hasFp256() && "256-bit vector without AVX!");
9115 unsigned NumElems = VT.getVectorNumElements();
9116 EVT NVT = EVT::getVectorVT(*DAG.getContext(), VT.getVectorElementType(),
9119 SmallVector<int, 16> MaskVec(NumElems * 2, -1);
9120 // Prepare truncation shuffle mask
9121 for (unsigned i = 0; i != NumElems; ++i)
9123 SDValue V = DAG.getVectorShuffle(NVT, DL,
9124 DAG.getNode(ISD::BITCAST, DL, NVT, In),
9125 DAG.getUNDEF(NVT), &MaskVec[0]);
9126 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, V,
9127 DAG.getIntPtrConstant(0));
9130 SDValue X86TargetLowering::LowerFP_TO_SINT(SDValue Op,
9131 SelectionDAG &DAG) const {
9132 MVT VT = Op.getSimpleValueType();
9133 if (VT.isVector()) {
9134 if (VT == MVT::v8i16)
9135 return DAG.getNode(ISD::TRUNCATE, SDLoc(Op), VT,
9136 DAG.getNode(ISD::FP_TO_SINT, SDLoc(Op),
9137 MVT::v8i32, Op.getOperand(0)));
9141 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG,
9142 /*IsSigned=*/ true, /*IsReplace=*/ false);
9143 SDValue FIST = Vals.first, StackSlot = Vals.second;
9144 // If FP_TO_INTHelper failed, the node is actually supposed to be Legal.
9145 if (FIST.getNode() == 0) return Op;
9147 if (StackSlot.getNode())
9149 return DAG.getLoad(Op.getValueType(), SDLoc(Op),
9150 FIST, StackSlot, MachinePointerInfo(),
9151 false, false, false, 0);
9153 // The node is the result.
9157 SDValue X86TargetLowering::LowerFP_TO_UINT(SDValue Op,
9158 SelectionDAG &DAG) const {
9159 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG,
9160 /*IsSigned=*/ false, /*IsReplace=*/ false);
9161 SDValue FIST = Vals.first, StackSlot = Vals.second;
9162 assert(FIST.getNode() && "Unexpected failure");
9164 if (StackSlot.getNode())
9166 return DAG.getLoad(Op.getValueType(), SDLoc(Op),
9167 FIST, StackSlot, MachinePointerInfo(),
9168 false, false, false, 0);
9170 // The node is the result.
9174 static SDValue LowerFP_EXTEND(SDValue Op, SelectionDAG &DAG) {
9176 MVT VT = Op.getSimpleValueType();
9177 SDValue In = Op.getOperand(0);
9178 MVT SVT = In.getSimpleValueType();
9180 assert(SVT == MVT::v2f32 && "Only customize MVT::v2f32 type legalization!");
9182 return DAG.getNode(X86ISD::VFPEXT, DL, VT,
9183 DAG.getNode(ISD::CONCAT_VECTORS, DL, MVT::v4f32,
9184 In, DAG.getUNDEF(SVT)));
9187 SDValue X86TargetLowering::LowerFABS(SDValue Op, SelectionDAG &DAG) const {
9188 LLVMContext *Context = DAG.getContext();
9190 MVT VT = Op.getSimpleValueType();
9192 unsigned NumElts = VT == MVT::f64 ? 2 : 4;
9193 if (VT.isVector()) {
9194 EltVT = VT.getVectorElementType();
9195 NumElts = VT.getVectorNumElements();
9198 if (EltVT == MVT::f64)
9199 C = ConstantFP::get(*Context, APFloat(APFloat::IEEEdouble,
9200 APInt(64, ~(1ULL << 63))));
9202 C = ConstantFP::get(*Context, APFloat(APFloat::IEEEsingle,
9203 APInt(32, ~(1U << 31))));
9204 C = ConstantVector::getSplat(NumElts, C);
9205 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy());
9206 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
9207 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
9208 MachinePointerInfo::getConstantPool(),
9209 false, false, false, Alignment);
9210 if (VT.isVector()) {
9211 MVT ANDVT = VT.is128BitVector() ? MVT::v2i64 : MVT::v4i64;
9212 return DAG.getNode(ISD::BITCAST, dl, VT,
9213 DAG.getNode(ISD::AND, dl, ANDVT,
9214 DAG.getNode(ISD::BITCAST, dl, ANDVT,
9216 DAG.getNode(ISD::BITCAST, dl, ANDVT, Mask)));
9218 return DAG.getNode(X86ISD::FAND, dl, VT, Op.getOperand(0), Mask);
9221 SDValue X86TargetLowering::LowerFNEG(SDValue Op, SelectionDAG &DAG) const {
9222 LLVMContext *Context = DAG.getContext();
9224 MVT VT = Op.getSimpleValueType();
9226 unsigned NumElts = VT == MVT::f64 ? 2 : 4;
9227 if (VT.isVector()) {
9228 EltVT = VT.getVectorElementType();
9229 NumElts = VT.getVectorNumElements();
9232 if (EltVT == MVT::f64)
9233 C = ConstantFP::get(*Context, APFloat(APFloat::IEEEdouble,
9234 APInt(64, 1ULL << 63)));
9236 C = ConstantFP::get(*Context, APFloat(APFloat::IEEEsingle,
9237 APInt(32, 1U << 31)));
9238 C = ConstantVector::getSplat(NumElts, C);
9239 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy());
9240 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
9241 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
9242 MachinePointerInfo::getConstantPool(),
9243 false, false, false, Alignment);
9244 if (VT.isVector()) {
9245 MVT XORVT = MVT::getVectorVT(MVT::i64, VT.getSizeInBits()/64);
9246 return DAG.getNode(ISD::BITCAST, dl, VT,
9247 DAG.getNode(ISD::XOR, dl, XORVT,
9248 DAG.getNode(ISD::BITCAST, dl, XORVT,
9250 DAG.getNode(ISD::BITCAST, dl, XORVT, Mask)));
9253 return DAG.getNode(X86ISD::FXOR, dl, VT, Op.getOperand(0), Mask);
9256 SDValue X86TargetLowering::LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const {
9257 LLVMContext *Context = DAG.getContext();
9258 SDValue Op0 = Op.getOperand(0);
9259 SDValue Op1 = Op.getOperand(1);
9261 MVT VT = Op.getSimpleValueType();
9262 MVT SrcVT = Op1.getSimpleValueType();
9264 // If second operand is smaller, extend it first.
9265 if (SrcVT.bitsLT(VT)) {
9266 Op1 = DAG.getNode(ISD::FP_EXTEND, dl, VT, Op1);
9269 // And if it is bigger, shrink it first.
9270 if (SrcVT.bitsGT(VT)) {
9271 Op1 = DAG.getNode(ISD::FP_ROUND, dl, VT, Op1, DAG.getIntPtrConstant(1));
9275 // At this point the operands and the result should have the same
9276 // type, and that won't be f80 since that is not custom lowered.
9278 // First get the sign bit of second operand.
9279 SmallVector<Constant*,4> CV;
9280 if (SrcVT == MVT::f64) {
9281 const fltSemantics &Sem = APFloat::IEEEdouble;
9282 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(64, 1ULL << 63))));
9283 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(64, 0))));
9285 const fltSemantics &Sem = APFloat::IEEEsingle;
9286 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 1U << 31))));
9287 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
9288 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
9289 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
9291 Constant *C = ConstantVector::get(CV);
9292 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
9293 SDValue Mask1 = DAG.getLoad(SrcVT, dl, DAG.getEntryNode(), CPIdx,
9294 MachinePointerInfo::getConstantPool(),
9295 false, false, false, 16);
9296 SDValue SignBit = DAG.getNode(X86ISD::FAND, dl, SrcVT, Op1, Mask1);
9298 // Shift sign bit right or left if the two operands have different types.
9299 if (SrcVT.bitsGT(VT)) {
9300 // Op0 is MVT::f32, Op1 is MVT::f64.
9301 SignBit = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f64, SignBit);
9302 SignBit = DAG.getNode(X86ISD::FSRL, dl, MVT::v2f64, SignBit,
9303 DAG.getConstant(32, MVT::i32));
9304 SignBit = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, SignBit);
9305 SignBit = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f32, SignBit,
9306 DAG.getIntPtrConstant(0));
9309 // Clear first operand sign bit.
9311 if (VT == MVT::f64) {
9312 const fltSemantics &Sem = APFloat::IEEEdouble;
9313 CV.push_back(ConstantFP::get(*Context, APFloat(Sem,
9314 APInt(64, ~(1ULL << 63)))));
9315 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(64, 0))));
9317 const fltSemantics &Sem = APFloat::IEEEsingle;
9318 CV.push_back(ConstantFP::get(*Context, APFloat(Sem,
9319 APInt(32, ~(1U << 31)))));
9320 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
9321 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
9322 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
9324 C = ConstantVector::get(CV);
9325 CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
9326 SDValue Mask2 = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
9327 MachinePointerInfo::getConstantPool(),
9328 false, false, false, 16);
9329 SDValue Val = DAG.getNode(X86ISD::FAND, dl, VT, Op0, Mask2);
9331 // Or the value with the sign bit.
9332 return DAG.getNode(X86ISD::FOR, dl, VT, Val, SignBit);
9335 static SDValue LowerFGETSIGN(SDValue Op, SelectionDAG &DAG) {
9336 SDValue N0 = Op.getOperand(0);
9338 MVT VT = Op.getSimpleValueType();
9340 // Lower ISD::FGETSIGN to (AND (X86ISD::FGETSIGNx86 ...) 1).
9341 SDValue xFGETSIGN = DAG.getNode(X86ISD::FGETSIGNx86, dl, VT, N0,
9342 DAG.getConstant(1, VT));
9343 return DAG.getNode(ISD::AND, dl, VT, xFGETSIGN, DAG.getConstant(1, VT));
9346 // LowerVectorAllZeroTest - Check whether an OR'd tree is PTEST-able.
9348 static SDValue LowerVectorAllZeroTest(SDValue Op, const X86Subtarget *Subtarget,
9349 SelectionDAG &DAG) {
9350 assert(Op.getOpcode() == ISD::OR && "Only check OR'd tree.");
9352 if (!Subtarget->hasSSE41())
9355 if (!Op->hasOneUse())
9358 SDNode *N = Op.getNode();
9361 SmallVector<SDValue, 8> Opnds;
9362 DenseMap<SDValue, unsigned> VecInMap;
9363 EVT VT = MVT::Other;
9365 // Recognize a special case where a vector is casted into wide integer to
9367 Opnds.push_back(N->getOperand(0));
9368 Opnds.push_back(N->getOperand(1));
9370 for (unsigned Slot = 0, e = Opnds.size(); Slot < e; ++Slot) {
9371 SmallVectorImpl<SDValue>::const_iterator I = Opnds.begin() + Slot;
9372 // BFS traverse all OR'd operands.
9373 if (I->getOpcode() == ISD::OR) {
9374 Opnds.push_back(I->getOperand(0));
9375 Opnds.push_back(I->getOperand(1));
9376 // Re-evaluate the number of nodes to be traversed.
9377 e += 2; // 2 more nodes (LHS and RHS) are pushed.
9381 // Quit if a non-EXTRACT_VECTOR_ELT
9382 if (I->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
9385 // Quit if without a constant index.
9386 SDValue Idx = I->getOperand(1);
9387 if (!isa<ConstantSDNode>(Idx))
9390 SDValue ExtractedFromVec = I->getOperand(0);
9391 DenseMap<SDValue, unsigned>::iterator M = VecInMap.find(ExtractedFromVec);
9392 if (M == VecInMap.end()) {
9393 VT = ExtractedFromVec.getValueType();
9394 // Quit if not 128/256-bit vector.
9395 if (!VT.is128BitVector() && !VT.is256BitVector())
9397 // Quit if not the same type.
9398 if (VecInMap.begin() != VecInMap.end() &&
9399 VT != VecInMap.begin()->first.getValueType())
9401 M = VecInMap.insert(std::make_pair(ExtractedFromVec, 0)).first;
9403 M->second |= 1U << cast<ConstantSDNode>(Idx)->getZExtValue();
9406 assert((VT.is128BitVector() || VT.is256BitVector()) &&
9407 "Not extracted from 128-/256-bit vector.");
9409 unsigned FullMask = (1U << VT.getVectorNumElements()) - 1U;
9410 SmallVector<SDValue, 8> VecIns;
9412 for (DenseMap<SDValue, unsigned>::const_iterator
9413 I = VecInMap.begin(), E = VecInMap.end(); I != E; ++I) {
9414 // Quit if not all elements are used.
9415 if (I->second != FullMask)
9417 VecIns.push_back(I->first);
9420 EVT TestVT = VT.is128BitVector() ? MVT::v2i64 : MVT::v4i64;
9422 // Cast all vectors into TestVT for PTEST.
9423 for (unsigned i = 0, e = VecIns.size(); i < e; ++i)
9424 VecIns[i] = DAG.getNode(ISD::BITCAST, DL, TestVT, VecIns[i]);
9426 // If more than one full vectors are evaluated, OR them first before PTEST.
9427 for (unsigned Slot = 0, e = VecIns.size(); e - Slot > 1; Slot += 2, e += 1) {
9428 // Each iteration will OR 2 nodes and append the result until there is only
9429 // 1 node left, i.e. the final OR'd value of all vectors.
9430 SDValue LHS = VecIns[Slot];
9431 SDValue RHS = VecIns[Slot + 1];
9432 VecIns.push_back(DAG.getNode(ISD::OR, DL, TestVT, LHS, RHS));
9435 return DAG.getNode(X86ISD::PTEST, DL, MVT::i32,
9436 VecIns.back(), VecIns.back());
9439 /// Emit nodes that will be selected as "test Op0,Op0", or something
9441 SDValue X86TargetLowering::EmitTest(SDValue Op, unsigned X86CC,
9442 SelectionDAG &DAG) const {
9445 // CF and OF aren't always set the way we want. Determine which
9446 // of these we need.
9447 bool NeedCF = false;
9448 bool NeedOF = false;
9451 case X86::COND_A: case X86::COND_AE:
9452 case X86::COND_B: case X86::COND_BE:
9455 case X86::COND_G: case X86::COND_GE:
9456 case X86::COND_L: case X86::COND_LE:
9457 case X86::COND_O: case X86::COND_NO:
9462 // See if we can use the EFLAGS value from the operand instead of
9463 // doing a separate TEST. TEST always sets OF and CF to 0, so unless
9464 // we prove that the arithmetic won't overflow, we can't use OF or CF.
9465 if (Op.getResNo() != 0 || NeedOF || NeedCF)
9466 // Emit a CMP with 0, which is the TEST pattern.
9467 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
9468 DAG.getConstant(0, Op.getValueType()));
9470 unsigned Opcode = 0;
9471 unsigned NumOperands = 0;
9473 // Truncate operations may prevent the merge of the SETCC instruction
9474 // and the arithmetic instruction before it. Attempt to truncate the operands
9475 // of the arithmetic instruction and use a reduced bit-width instruction.
9476 bool NeedTruncation = false;
9477 SDValue ArithOp = Op;
9478 if (Op->getOpcode() == ISD::TRUNCATE && Op->hasOneUse()) {
9479 SDValue Arith = Op->getOperand(0);
9480 // Both the trunc and the arithmetic op need to have one user each.
9481 if (Arith->hasOneUse())
9482 switch (Arith.getOpcode()) {
9489 NeedTruncation = true;
9495 // NOTICE: In the code below we use ArithOp to hold the arithmetic operation
9496 // which may be the result of a CAST. We use the variable 'Op', which is the
9497 // non-casted variable when we check for possible users.
9498 switch (ArithOp.getOpcode()) {
9500 // Due to an isel shortcoming, be conservative if this add is likely to be
9501 // selected as part of a load-modify-store instruction. When the root node
9502 // in a match is a store, isel doesn't know how to remap non-chain non-flag
9503 // uses of other nodes in the match, such as the ADD in this case. This
9504 // leads to the ADD being left around and reselected, with the result being
9505 // two adds in the output. Alas, even if none our users are stores, that
9506 // doesn't prove we're O.K. Ergo, if we have any parents that aren't
9507 // CopyToReg or SETCC, eschew INC/DEC. A better fix seems to require
9508 // climbing the DAG back to the root, and it doesn't seem to be worth the
9510 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
9511 UE = Op.getNode()->use_end(); UI != UE; ++UI)
9512 if (UI->getOpcode() != ISD::CopyToReg &&
9513 UI->getOpcode() != ISD::SETCC &&
9514 UI->getOpcode() != ISD::STORE)
9517 if (ConstantSDNode *C =
9518 dyn_cast<ConstantSDNode>(ArithOp.getNode()->getOperand(1))) {
9519 // An add of one will be selected as an INC.
9520 if (C->getAPIntValue() == 1) {
9521 Opcode = X86ISD::INC;
9526 // An add of negative one (subtract of one) will be selected as a DEC.
9527 if (C->getAPIntValue().isAllOnesValue()) {
9528 Opcode = X86ISD::DEC;
9534 // Otherwise use a regular EFLAGS-setting add.
9535 Opcode = X86ISD::ADD;
9539 // If the primary and result isn't used, don't bother using X86ISD::AND,
9540 // because a TEST instruction will be better.
9541 bool NonFlagUse = false;
9542 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
9543 UE = Op.getNode()->use_end(); UI != UE; ++UI) {
9545 unsigned UOpNo = UI.getOperandNo();
9546 if (User->getOpcode() == ISD::TRUNCATE && User->hasOneUse()) {
9547 // Look pass truncate.
9548 UOpNo = User->use_begin().getOperandNo();
9549 User = *User->use_begin();
9552 if (User->getOpcode() != ISD::BRCOND &&
9553 User->getOpcode() != ISD::SETCC &&
9554 !(User->getOpcode() == ISD::SELECT && UOpNo == 0)) {
9567 // Due to the ISEL shortcoming noted above, be conservative if this op is
9568 // likely to be selected as part of a load-modify-store instruction.
9569 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
9570 UE = Op.getNode()->use_end(); UI != UE; ++UI)
9571 if (UI->getOpcode() == ISD::STORE)
9574 // Otherwise use a regular EFLAGS-setting instruction.
9575 switch (ArithOp.getOpcode()) {
9576 default: llvm_unreachable("unexpected operator!");
9577 case ISD::SUB: Opcode = X86ISD::SUB; break;
9578 case ISD::XOR: Opcode = X86ISD::XOR; break;
9579 case ISD::AND: Opcode = X86ISD::AND; break;
9581 if (!NeedTruncation && (X86CC == X86::COND_E || X86CC == X86::COND_NE)) {
9582 SDValue EFLAGS = LowerVectorAllZeroTest(Op, Subtarget, DAG);
9583 if (EFLAGS.getNode())
9586 Opcode = X86ISD::OR;
9600 return SDValue(Op.getNode(), 1);
9606 // If we found that truncation is beneficial, perform the truncation and
9608 if (NeedTruncation) {
9609 EVT VT = Op.getValueType();
9610 SDValue WideVal = Op->getOperand(0);
9611 EVT WideVT = WideVal.getValueType();
9612 unsigned ConvertedOp = 0;
9613 // Use a target machine opcode to prevent further DAGCombine
9614 // optimizations that may separate the arithmetic operations
9615 // from the setcc node.
9616 switch (WideVal.getOpcode()) {
9618 case ISD::ADD: ConvertedOp = X86ISD::ADD; break;
9619 case ISD::SUB: ConvertedOp = X86ISD::SUB; break;
9620 case ISD::AND: ConvertedOp = X86ISD::AND; break;
9621 case ISD::OR: ConvertedOp = X86ISD::OR; break;
9622 case ISD::XOR: ConvertedOp = X86ISD::XOR; break;
9626 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
9627 if (TLI.isOperationLegal(WideVal.getOpcode(), WideVT)) {
9628 SDValue V0 = DAG.getNode(ISD::TRUNCATE, dl, VT, WideVal.getOperand(0));
9629 SDValue V1 = DAG.getNode(ISD::TRUNCATE, dl, VT, WideVal.getOperand(1));
9630 Op = DAG.getNode(ConvertedOp, dl, VT, V0, V1);
9636 // Emit a CMP with 0, which is the TEST pattern.
9637 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
9638 DAG.getConstant(0, Op.getValueType()));
9640 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
9641 SmallVector<SDValue, 4> Ops;
9642 for (unsigned i = 0; i != NumOperands; ++i)
9643 Ops.push_back(Op.getOperand(i));
9645 SDValue New = DAG.getNode(Opcode, dl, VTs, &Ops[0], NumOperands);
9646 DAG.ReplaceAllUsesWith(Op, New);
9647 return SDValue(New.getNode(), 1);
9650 /// Emit nodes that will be selected as "cmp Op0,Op1", or something
9652 SDValue X86TargetLowering::EmitCmp(SDValue Op0, SDValue Op1, unsigned X86CC,
9653 SelectionDAG &DAG) const {
9654 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op1))
9655 if (C->getAPIntValue() == 0)
9656 return EmitTest(Op0, X86CC, DAG);
9659 if ((Op0.getValueType() == MVT::i8 || Op0.getValueType() == MVT::i16 ||
9660 Op0.getValueType() == MVT::i32 || Op0.getValueType() == MVT::i64)) {
9661 // Use SUB instead of CMP to enable CSE between SUB and CMP.
9662 SDVTList VTs = DAG.getVTList(Op0.getValueType(), MVT::i32);
9663 SDValue Sub = DAG.getNode(X86ISD::SUB, dl, VTs,
9665 return SDValue(Sub.getNode(), 1);
9667 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op0, Op1);
9670 /// Convert a comparison if required by the subtarget.
9671 SDValue X86TargetLowering::ConvertCmpIfNecessary(SDValue Cmp,
9672 SelectionDAG &DAG) const {
9673 // If the subtarget does not support the FUCOMI instruction, floating-point
9674 // comparisons have to be converted.
9675 if (Subtarget->hasCMov() ||
9676 Cmp.getOpcode() != X86ISD::CMP ||
9677 !Cmp.getOperand(0).getValueType().isFloatingPoint() ||
9678 !Cmp.getOperand(1).getValueType().isFloatingPoint())
9681 // The instruction selector will select an FUCOM instruction instead of
9682 // FUCOMI, which writes the comparison result to FPSW instead of EFLAGS. Hence
9683 // build an SDNode sequence that transfers the result from FPSW into EFLAGS:
9684 // (X86sahf (trunc (srl (X86fp_stsw (trunc (X86cmp ...)), 8))))
9686 SDValue TruncFPSW = DAG.getNode(ISD::TRUNCATE, dl, MVT::i16, Cmp);
9687 SDValue FNStSW = DAG.getNode(X86ISD::FNSTSW16r, dl, MVT::i16, TruncFPSW);
9688 SDValue Srl = DAG.getNode(ISD::SRL, dl, MVT::i16, FNStSW,
9689 DAG.getConstant(8, MVT::i8));
9690 SDValue TruncSrl = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Srl);
9691 return DAG.getNode(X86ISD::SAHF, dl, MVT::i32, TruncSrl);
9694 static bool isAllOnes(SDValue V) {
9695 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V);
9696 return C && C->isAllOnesValue();
9699 /// LowerToBT - Result of 'and' is compared against zero. Turn it into a BT node
9700 /// if it's possible.
9701 SDValue X86TargetLowering::LowerToBT(SDValue And, ISD::CondCode CC,
9702 SDLoc dl, SelectionDAG &DAG) const {
9703 SDValue Op0 = And.getOperand(0);
9704 SDValue Op1 = And.getOperand(1);
9705 if (Op0.getOpcode() == ISD::TRUNCATE)
9706 Op0 = Op0.getOperand(0);
9707 if (Op1.getOpcode() == ISD::TRUNCATE)
9708 Op1 = Op1.getOperand(0);
9711 if (Op1.getOpcode() == ISD::SHL)
9712 std::swap(Op0, Op1);
9713 if (Op0.getOpcode() == ISD::SHL) {
9714 if (ConstantSDNode *And00C = dyn_cast<ConstantSDNode>(Op0.getOperand(0)))
9715 if (And00C->getZExtValue() == 1) {
9716 // If we looked past a truncate, check that it's only truncating away
9718 unsigned BitWidth = Op0.getValueSizeInBits();
9719 unsigned AndBitWidth = And.getValueSizeInBits();
9720 if (BitWidth > AndBitWidth) {
9722 DAG.ComputeMaskedBits(Op0, Zeros, Ones);
9723 if (Zeros.countLeadingOnes() < BitWidth - AndBitWidth)
9727 RHS = Op0.getOperand(1);
9729 } else if (Op1.getOpcode() == ISD::Constant) {
9730 ConstantSDNode *AndRHS = cast<ConstantSDNode>(Op1);
9731 uint64_t AndRHSVal = AndRHS->getZExtValue();
9732 SDValue AndLHS = Op0;
9734 if (AndRHSVal == 1 && AndLHS.getOpcode() == ISD::SRL) {
9735 LHS = AndLHS.getOperand(0);
9736 RHS = AndLHS.getOperand(1);
9739 // Use BT if the immediate can't be encoded in a TEST instruction.
9740 if (!isUInt<32>(AndRHSVal) && isPowerOf2_64(AndRHSVal)) {
9742 RHS = DAG.getConstant(Log2_64_Ceil(AndRHSVal), LHS.getValueType());
9746 if (LHS.getNode()) {
9747 // If LHS is i8, promote it to i32 with any_extend. There is no i8 BT
9748 // instruction. Since the shift amount is in-range-or-undefined, we know
9749 // that doing a bittest on the i32 value is ok. We extend to i32 because
9750 // the encoding for the i16 version is larger than the i32 version.
9751 // Also promote i16 to i32 for performance / code size reason.
9752 if (LHS.getValueType() == MVT::i8 ||
9753 LHS.getValueType() == MVT::i16)
9754 LHS = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, LHS);
9756 // If the operand types disagree, extend the shift amount to match. Since
9757 // BT ignores high bits (like shifts) we can use anyextend.
9758 if (LHS.getValueType() != RHS.getValueType())
9759 RHS = DAG.getNode(ISD::ANY_EXTEND, dl, LHS.getValueType(), RHS);
9761 SDValue BT = DAG.getNode(X86ISD::BT, dl, MVT::i32, LHS, RHS);
9762 X86::CondCode Cond = CC == ISD::SETEQ ? X86::COND_AE : X86::COND_B;
9763 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
9764 DAG.getConstant(Cond, MVT::i8), BT);
9770 /// \brief - Turns an ISD::CondCode into a value suitable for SSE floating point
9772 static int translateX86FSETCC(ISD::CondCode SetCCOpcode, SDValue &Op0,
9777 // SSE Condition code mapping:
9786 switch (SetCCOpcode) {
9787 default: llvm_unreachable("Unexpected SETCC condition");
9789 case ISD::SETEQ: SSECC = 0; break;
9791 case ISD::SETGT: Swap = true; // Fallthrough
9793 case ISD::SETOLT: SSECC = 1; break;
9795 case ISD::SETGE: Swap = true; // Fallthrough
9797 case ISD::SETOLE: SSECC = 2; break;
9798 case ISD::SETUO: SSECC = 3; break;
9800 case ISD::SETNE: SSECC = 4; break;
9801 case ISD::SETULE: Swap = true; // Fallthrough
9802 case ISD::SETUGE: SSECC = 5; break;
9803 case ISD::SETULT: Swap = true; // Fallthrough
9804 case ISD::SETUGT: SSECC = 6; break;
9805 case ISD::SETO: SSECC = 7; break;
9807 case ISD::SETONE: SSECC = 8; break;
9810 std::swap(Op0, Op1);
9815 // Lower256IntVSETCC - Break a VSETCC 256-bit integer VSETCC into two new 128
9816 // ones, and then concatenate the result back.
9817 static SDValue Lower256IntVSETCC(SDValue Op, SelectionDAG &DAG) {
9818 MVT VT = Op.getSimpleValueType();
9820 assert(VT.is256BitVector() && Op.getOpcode() == ISD::SETCC &&
9821 "Unsupported value type for operation");
9823 unsigned NumElems = VT.getVectorNumElements();
9825 SDValue CC = Op.getOperand(2);
9827 // Extract the LHS vectors
9828 SDValue LHS = Op.getOperand(0);
9829 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
9830 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
9832 // Extract the RHS vectors
9833 SDValue RHS = Op.getOperand(1);
9834 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, dl);
9835 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, dl);
9837 // Issue the operation on the smaller types and concatenate the result back
9838 MVT EltVT = VT.getVectorElementType();
9839 MVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
9840 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
9841 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1, CC),
9842 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2, CC));
9845 static SDValue LowerIntVSETCC_AVX512(SDValue Op, SelectionDAG &DAG) {
9846 SDValue Op0 = Op.getOperand(0);
9847 SDValue Op1 = Op.getOperand(1);
9848 SDValue CC = Op.getOperand(2);
9849 MVT VT = Op.getSimpleValueType();
9851 assert(Op0.getValueType().getVectorElementType().getSizeInBits() >= 32 &&
9852 Op.getValueType().getScalarType() == MVT::i1 &&
9853 "Cannot set masked compare for this operation");
9855 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
9858 bool Unsigned = false;
9860 switch (SetCCOpcode) {
9861 default: llvm_unreachable("Unexpected SETCC condition");
9862 case ISD::SETNE: SSECC = 4; break;
9863 case ISD::SETEQ: SSECC = 0; break;
9864 case ISD::SETUGT: Unsigned = true;
9865 case ISD::SETGT: SSECC = 6; break; // NLE
9866 case ISD::SETULT: Unsigned = true;
9867 case ISD::SETLT: SSECC = 1; break;
9868 case ISD::SETUGE: Unsigned = true;
9869 case ISD::SETGE: SSECC = 5; break; // NLT
9870 case ISD::SETULE: Unsigned = true;
9871 case ISD::SETLE: SSECC = 2; break;
9873 unsigned Opc = Unsigned ? X86ISD::CMPMU: X86ISD::CMPM;
9874 return DAG.getNode(Opc, dl, VT, Op0, Op1,
9875 DAG.getConstant(SSECC, MVT::i8));
9879 static SDValue LowerVSETCC(SDValue Op, const X86Subtarget *Subtarget,
9880 SelectionDAG &DAG) {
9881 SDValue Op0 = Op.getOperand(0);
9882 SDValue Op1 = Op.getOperand(1);
9883 SDValue CC = Op.getOperand(2);
9884 MVT VT = Op.getSimpleValueType();
9885 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
9886 bool isFP = Op.getOperand(1).getSimpleValueType().isFloatingPoint();
9891 MVT EltVT = Op0.getSimpleValueType().getVectorElementType();
9892 assert(EltVT == MVT::f32 || EltVT == MVT::f64);
9895 unsigned SSECC = translateX86FSETCC(SetCCOpcode, Op0, Op1);
9896 unsigned Opc = X86ISD::CMPP;
9897 if (Subtarget->hasAVX512() && VT.getVectorElementType() == MVT::i1) {
9898 assert(VT.getVectorNumElements() <= 16);
9901 // In the two special cases we can't handle, emit two comparisons.
9904 unsigned CombineOpc;
9905 if (SetCCOpcode == ISD::SETUEQ) {
9906 CC0 = 3; CC1 = 0; CombineOpc = ISD::OR;
9908 assert(SetCCOpcode == ISD::SETONE);
9909 CC0 = 7; CC1 = 4; CombineOpc = ISD::AND;
9912 SDValue Cmp0 = DAG.getNode(Opc, dl, VT, Op0, Op1,
9913 DAG.getConstant(CC0, MVT::i8));
9914 SDValue Cmp1 = DAG.getNode(Opc, dl, VT, Op0, Op1,
9915 DAG.getConstant(CC1, MVT::i8));
9916 return DAG.getNode(CombineOpc, dl, VT, Cmp0, Cmp1);
9918 // Handle all other FP comparisons here.
9919 return DAG.getNode(Opc, dl, VT, Op0, Op1,
9920 DAG.getConstant(SSECC, MVT::i8));
9923 // Break 256-bit integer vector compare into smaller ones.
9924 if (VT.is256BitVector() && !Subtarget->hasInt256())
9925 return Lower256IntVSETCC(Op, DAG);
9927 bool MaskResult = (VT.getVectorElementType() == MVT::i1);
9928 EVT OpVT = Op1.getValueType();
9929 if (Subtarget->hasAVX512()) {
9930 if (Op1.getValueType().is512BitVector() ||
9931 (MaskResult && OpVT.getVectorElementType().getSizeInBits() >= 32))
9932 return LowerIntVSETCC_AVX512(Op, DAG);
9934 // In AVX-512 architecture setcc returns mask with i1 elements,
9935 // But there is no compare instruction for i8 and i16 elements.
9936 // We are not talking about 512-bit operands in this case, these
9937 // types are illegal.
9939 (OpVT.getVectorElementType().getSizeInBits() < 32 &&
9940 OpVT.getVectorElementType().getSizeInBits() >= 8))
9941 return DAG.getNode(ISD::TRUNCATE, dl, VT,
9942 DAG.getNode(ISD::SETCC, dl, OpVT, Op0, Op1, CC));
9945 // We are handling one of the integer comparisons here. Since SSE only has
9946 // GT and EQ comparisons for integer, swapping operands and multiple
9947 // operations may be required for some comparisons.
9949 bool Swap = false, Invert = false, FlipSigns = false, MinMax = false;
9951 switch (SetCCOpcode) {
9952 default: llvm_unreachable("Unexpected SETCC condition");
9953 case ISD::SETNE: Invert = true;
9954 case ISD::SETEQ: Opc = MaskResult? X86ISD::PCMPEQM: X86ISD::PCMPEQ; break;
9955 case ISD::SETLT: Swap = true;
9956 case ISD::SETGT: Opc = MaskResult? X86ISD::PCMPGTM: X86ISD::PCMPGT; break;
9957 case ISD::SETGE: Swap = true;
9958 case ISD::SETLE: Opc = MaskResult? X86ISD::PCMPGTM: X86ISD::PCMPGT;
9959 Invert = true; break;
9960 case ISD::SETULT: Swap = true;
9961 case ISD::SETUGT: Opc = MaskResult? X86ISD::PCMPGTM: X86ISD::PCMPGT;
9962 FlipSigns = true; break;
9963 case ISD::SETUGE: Swap = true;
9964 case ISD::SETULE: Opc = MaskResult? X86ISD::PCMPGTM: X86ISD::PCMPGT;
9965 FlipSigns = true; Invert = true; break;
9968 // Special case: Use min/max operations for SETULE/SETUGE
9969 MVT VET = VT.getVectorElementType();
9971 (Subtarget->hasSSE41() && (VET >= MVT::i8 && VET <= MVT::i32))
9972 || (Subtarget->hasSSE2() && (VET == MVT::i8));
9975 switch (SetCCOpcode) {
9977 case ISD::SETULE: Opc = X86ISD::UMIN; MinMax = true; break;
9978 case ISD::SETUGE: Opc = X86ISD::UMAX; MinMax = true; break;
9981 if (MinMax) { Swap = false; Invert = false; FlipSigns = false; }
9985 std::swap(Op0, Op1);
9987 // Check that the operation in question is available (most are plain SSE2,
9988 // but PCMPGTQ and PCMPEQQ have different requirements).
9989 if (VT == MVT::v2i64) {
9990 if (Opc == X86ISD::PCMPGT && !Subtarget->hasSSE42()) {
9991 assert(Subtarget->hasSSE2() && "Don't know how to lower!");
9993 // First cast everything to the right type.
9994 Op0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op0);
9995 Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op1);
9997 // Since SSE has no unsigned integer comparisons, we need to flip the sign
9998 // bits of the inputs before performing those operations. The lower
9999 // compare is always unsigned.
10002 SB = DAG.getConstant(0x80000000U, MVT::v4i32);
10004 SDValue Sign = DAG.getConstant(0x80000000U, MVT::i32);
10005 SDValue Zero = DAG.getConstant(0x00000000U, MVT::i32);
10006 SB = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32,
10007 Sign, Zero, Sign, Zero);
10009 Op0 = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Op0, SB);
10010 Op1 = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Op1, SB);
10012 // Emulate PCMPGTQ with (hi1 > hi2) | ((hi1 == hi2) & (lo1 > lo2))
10013 SDValue GT = DAG.getNode(X86ISD::PCMPGT, dl, MVT::v4i32, Op0, Op1);
10014 SDValue EQ = DAG.getNode(X86ISD::PCMPEQ, dl, MVT::v4i32, Op0, Op1);
10016 // Create masks for only the low parts/high parts of the 64 bit integers.
10017 static const int MaskHi[] = { 1, 1, 3, 3 };
10018 static const int MaskLo[] = { 0, 0, 2, 2 };
10019 SDValue EQHi = DAG.getVectorShuffle(MVT::v4i32, dl, EQ, EQ, MaskHi);
10020 SDValue GTLo = DAG.getVectorShuffle(MVT::v4i32, dl, GT, GT, MaskLo);
10021 SDValue GTHi = DAG.getVectorShuffle(MVT::v4i32, dl, GT, GT, MaskHi);
10023 SDValue Result = DAG.getNode(ISD::AND, dl, MVT::v4i32, EQHi, GTLo);
10024 Result = DAG.getNode(ISD::OR, dl, MVT::v4i32, Result, GTHi);
10027 Result = DAG.getNOT(dl, Result, MVT::v4i32);
10029 return DAG.getNode(ISD::BITCAST, dl, VT, Result);
10032 if (Opc == X86ISD::PCMPEQ && !Subtarget->hasSSE41()) {
10033 // If pcmpeqq is missing but pcmpeqd is available synthesize pcmpeqq with
10034 // pcmpeqd + pshufd + pand.
10035 assert(Subtarget->hasSSE2() && !FlipSigns && "Don't know how to lower!");
10037 // First cast everything to the right type.
10038 Op0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op0);
10039 Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op1);
10042 SDValue Result = DAG.getNode(Opc, dl, MVT::v4i32, Op0, Op1);
10044 // Make sure the lower and upper halves are both all-ones.
10045 static const int Mask[] = { 1, 0, 3, 2 };
10046 SDValue Shuf = DAG.getVectorShuffle(MVT::v4i32, dl, Result, Result, Mask);
10047 Result = DAG.getNode(ISD::AND, dl, MVT::v4i32, Result, Shuf);
10050 Result = DAG.getNOT(dl, Result, MVT::v4i32);
10052 return DAG.getNode(ISD::BITCAST, dl, VT, Result);
10056 // Since SSE has no unsigned integer comparisons, we need to flip the sign
10057 // bits of the inputs before performing those operations.
10059 EVT EltVT = VT.getVectorElementType();
10060 SDValue SB = DAG.getConstant(APInt::getSignBit(EltVT.getSizeInBits()), VT);
10061 Op0 = DAG.getNode(ISD::XOR, dl, VT, Op0, SB);
10062 Op1 = DAG.getNode(ISD::XOR, dl, VT, Op1, SB);
10065 SDValue Result = DAG.getNode(Opc, dl, VT, Op0, Op1);
10067 // If the logical-not of the result is required, perform that now.
10069 Result = DAG.getNOT(dl, Result, VT);
10072 Result = DAG.getNode(X86ISD::PCMPEQ, dl, VT, Op0, Result);
10077 SDValue X86TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
10079 MVT VT = Op.getSimpleValueType();
10081 if (VT.isVector()) return LowerVSETCC(Op, Subtarget, DAG);
10083 assert(VT == MVT::i8 && "SetCC type must be 8-bit integer");
10084 SDValue Op0 = Op.getOperand(0);
10085 SDValue Op1 = Op.getOperand(1);
10087 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
10089 // Optimize to BT if possible.
10090 // Lower (X & (1 << N)) == 0 to BT(X, N).
10091 // Lower ((X >>u N) & 1) != 0 to BT(X, N).
10092 // Lower ((X >>s N) & 1) != 0 to BT(X, N).
10093 if (Op0.getOpcode() == ISD::AND && Op0.hasOneUse() &&
10094 Op1.getOpcode() == ISD::Constant &&
10095 cast<ConstantSDNode>(Op1)->isNullValue() &&
10096 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
10097 SDValue NewSetCC = LowerToBT(Op0, CC, dl, DAG);
10098 if (NewSetCC.getNode())
10102 // Look for X == 0, X == 1, X != 0, or X != 1. We can simplify some forms of
10104 if (Op1.getOpcode() == ISD::Constant &&
10105 (cast<ConstantSDNode>(Op1)->getZExtValue() == 1 ||
10106 cast<ConstantSDNode>(Op1)->isNullValue()) &&
10107 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
10109 // If the input is a setcc, then reuse the input setcc or use a new one with
10110 // the inverted condition.
10111 if (Op0.getOpcode() == X86ISD::SETCC) {
10112 X86::CondCode CCode = (X86::CondCode)Op0.getConstantOperandVal(0);
10113 bool Invert = (CC == ISD::SETNE) ^
10114 cast<ConstantSDNode>(Op1)->isNullValue();
10115 if (!Invert) return Op0;
10117 CCode = X86::GetOppositeBranchCondition(CCode);
10118 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
10119 DAG.getConstant(CCode, MVT::i8), Op0.getOperand(1));
10123 bool isFP = Op1.getSimpleValueType().isFloatingPoint();
10124 unsigned X86CC = TranslateX86CC(CC, isFP, Op0, Op1, DAG);
10125 if (X86CC == X86::COND_INVALID)
10128 SDValue EFLAGS = EmitCmp(Op0, Op1, X86CC, DAG);
10129 EFLAGS = ConvertCmpIfNecessary(EFLAGS, DAG);
10130 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
10131 DAG.getConstant(X86CC, MVT::i8), EFLAGS);
10134 // isX86LogicalCmp - Return true if opcode is a X86 logical comparison.
10135 static bool isX86LogicalCmp(SDValue Op) {
10136 unsigned Opc = Op.getNode()->getOpcode();
10137 if (Opc == X86ISD::CMP || Opc == X86ISD::COMI || Opc == X86ISD::UCOMI ||
10138 Opc == X86ISD::SAHF)
10140 if (Op.getResNo() == 1 &&
10141 (Opc == X86ISD::ADD ||
10142 Opc == X86ISD::SUB ||
10143 Opc == X86ISD::ADC ||
10144 Opc == X86ISD::SBB ||
10145 Opc == X86ISD::SMUL ||
10146 Opc == X86ISD::UMUL ||
10147 Opc == X86ISD::INC ||
10148 Opc == X86ISD::DEC ||
10149 Opc == X86ISD::OR ||
10150 Opc == X86ISD::XOR ||
10151 Opc == X86ISD::AND))
10154 if (Op.getResNo() == 2 && Opc == X86ISD::UMUL)
10160 static bool isZero(SDValue V) {
10161 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V);
10162 return C && C->isNullValue();
10165 static bool isTruncWithZeroHighBitsInput(SDValue V, SelectionDAG &DAG) {
10166 if (V.getOpcode() != ISD::TRUNCATE)
10169 SDValue VOp0 = V.getOperand(0);
10170 unsigned InBits = VOp0.getValueSizeInBits();
10171 unsigned Bits = V.getValueSizeInBits();
10172 return DAG.MaskedValueIsZero(VOp0, APInt::getHighBitsSet(InBits,InBits-Bits));
10175 SDValue X86TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {
10176 bool addTest = true;
10177 SDValue Cond = Op.getOperand(0);
10178 SDValue Op1 = Op.getOperand(1);
10179 SDValue Op2 = Op.getOperand(2);
10181 EVT VT = Op1.getValueType();
10184 // Lower fp selects into a CMP/AND/ANDN/OR sequence when the necessary SSE ops
10185 // are available. Otherwise fp cmovs get lowered into a less efficient branch
10186 // sequence later on.
10187 if (Cond.getOpcode() == ISD::SETCC &&
10188 ((Subtarget->hasSSE2() && (VT == MVT::f32 || VT == MVT::f64)) ||
10189 (Subtarget->hasSSE1() && VT == MVT::f32)) &&
10190 VT == Cond.getOperand(0).getValueType() && Cond->hasOneUse()) {
10191 SDValue CondOp0 = Cond.getOperand(0), CondOp1 = Cond.getOperand(1);
10192 int SSECC = translateX86FSETCC(
10193 cast<CondCodeSDNode>(Cond.getOperand(2))->get(), CondOp0, CondOp1);
10196 unsigned Opcode = VT == MVT::f32 ? X86ISD::FSETCCss : X86ISD::FSETCCsd;
10197 SDValue Cmp = DAG.getNode(Opcode, DL, VT, CondOp0, CondOp1,
10198 DAG.getConstant(SSECC, MVT::i8));
10199 SDValue AndN = DAG.getNode(X86ISD::FANDN, DL, VT, Cmp, Op2);
10200 SDValue And = DAG.getNode(X86ISD::FAND, DL, VT, Cmp, Op1);
10201 return DAG.getNode(X86ISD::FOR, DL, VT, AndN, And);
10205 if (Cond.getOpcode() == ISD::SETCC) {
10206 SDValue NewCond = LowerSETCC(Cond, DAG);
10207 if (NewCond.getNode())
10211 // (select (x == 0), -1, y) -> (sign_bit (x - 1)) | y
10212 // (select (x == 0), y, -1) -> ~(sign_bit (x - 1)) | y
10213 // (select (x != 0), y, -1) -> (sign_bit (x - 1)) | y
10214 // (select (x != 0), -1, y) -> ~(sign_bit (x - 1)) | y
10215 if (Cond.getOpcode() == X86ISD::SETCC &&
10216 Cond.getOperand(1).getOpcode() == X86ISD::CMP &&
10217 isZero(Cond.getOperand(1).getOperand(1))) {
10218 SDValue Cmp = Cond.getOperand(1);
10220 unsigned CondCode =cast<ConstantSDNode>(Cond.getOperand(0))->getZExtValue();
10222 if ((isAllOnes(Op1) || isAllOnes(Op2)) &&
10223 (CondCode == X86::COND_E || CondCode == X86::COND_NE)) {
10224 SDValue Y = isAllOnes(Op2) ? Op1 : Op2;
10226 SDValue CmpOp0 = Cmp.getOperand(0);
10227 // Apply further optimizations for special cases
10228 // (select (x != 0), -1, 0) -> neg & sbb
10229 // (select (x == 0), 0, -1) -> neg & sbb
10230 if (ConstantSDNode *YC = dyn_cast<ConstantSDNode>(Y))
10231 if (YC->isNullValue() &&
10232 (isAllOnes(Op1) == (CondCode == X86::COND_NE))) {
10233 SDVTList VTs = DAG.getVTList(CmpOp0.getValueType(), MVT::i32);
10234 SDValue Neg = DAG.getNode(X86ISD::SUB, DL, VTs,
10235 DAG.getConstant(0, CmpOp0.getValueType()),
10237 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
10238 DAG.getConstant(X86::COND_B, MVT::i8),
10239 SDValue(Neg.getNode(), 1));
10243 Cmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32,
10244 CmpOp0, DAG.getConstant(1, CmpOp0.getValueType()));
10245 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
10247 SDValue Res = // Res = 0 or -1.
10248 DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
10249 DAG.getConstant(X86::COND_B, MVT::i8), Cmp);
10251 if (isAllOnes(Op1) != (CondCode == X86::COND_E))
10252 Res = DAG.getNOT(DL, Res, Res.getValueType());
10254 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(Op2);
10255 if (N2C == 0 || !N2C->isNullValue())
10256 Res = DAG.getNode(ISD::OR, DL, Res.getValueType(), Res, Y);
10261 // Look past (and (setcc_carry (cmp ...)), 1).
10262 if (Cond.getOpcode() == ISD::AND &&
10263 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
10264 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
10265 if (C && C->getAPIntValue() == 1)
10266 Cond = Cond.getOperand(0);
10269 // If condition flag is set by a X86ISD::CMP, then use it as the condition
10270 // setting operand in place of the X86ISD::SETCC.
10271 unsigned CondOpcode = Cond.getOpcode();
10272 if (CondOpcode == X86ISD::SETCC ||
10273 CondOpcode == X86ISD::SETCC_CARRY) {
10274 CC = Cond.getOperand(0);
10276 SDValue Cmp = Cond.getOperand(1);
10277 unsigned Opc = Cmp.getOpcode();
10278 MVT VT = Op.getSimpleValueType();
10280 bool IllegalFPCMov = false;
10281 if (VT.isFloatingPoint() && !VT.isVector() &&
10282 !isScalarFPTypeInSSEReg(VT)) // FPStack?
10283 IllegalFPCMov = !hasFPCMov(cast<ConstantSDNode>(CC)->getSExtValue());
10285 if ((isX86LogicalCmp(Cmp) && !IllegalFPCMov) ||
10286 Opc == X86ISD::BT) { // FIXME
10290 } else if (CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO ||
10291 CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO ||
10292 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) &&
10293 Cond.getOperand(0).getValueType() != MVT::i8)) {
10294 SDValue LHS = Cond.getOperand(0);
10295 SDValue RHS = Cond.getOperand(1);
10296 unsigned X86Opcode;
10299 switch (CondOpcode) {
10300 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break;
10301 case ISD::SADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break;
10302 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break;
10303 case ISD::SSUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break;
10304 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break;
10305 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break;
10306 default: llvm_unreachable("unexpected overflowing operator");
10308 if (CondOpcode == ISD::UMULO)
10309 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(),
10312 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
10314 SDValue X86Op = DAG.getNode(X86Opcode, DL, VTs, LHS, RHS);
10316 if (CondOpcode == ISD::UMULO)
10317 Cond = X86Op.getValue(2);
10319 Cond = X86Op.getValue(1);
10321 CC = DAG.getConstant(X86Cond, MVT::i8);
10326 // Look pass the truncate if the high bits are known zero.
10327 if (isTruncWithZeroHighBitsInput(Cond, DAG))
10328 Cond = Cond.getOperand(0);
10330 // We know the result of AND is compared against zero. Try to match
10332 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
10333 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, DL, DAG);
10334 if (NewSetCC.getNode()) {
10335 CC = NewSetCC.getOperand(0);
10336 Cond = NewSetCC.getOperand(1);
10343 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
10344 Cond = EmitTest(Cond, X86::COND_NE, DAG);
10347 // a < b ? -1 : 0 -> RES = ~setcc_carry
10348 // a < b ? 0 : -1 -> RES = setcc_carry
10349 // a >= b ? -1 : 0 -> RES = setcc_carry
10350 // a >= b ? 0 : -1 -> RES = ~setcc_carry
10351 if (Cond.getOpcode() == X86ISD::SUB) {
10352 Cond = ConvertCmpIfNecessary(Cond, DAG);
10353 unsigned CondCode = cast<ConstantSDNode>(CC)->getZExtValue();
10355 if ((CondCode == X86::COND_AE || CondCode == X86::COND_B) &&
10356 (isAllOnes(Op1) || isAllOnes(Op2)) && (isZero(Op1) || isZero(Op2))) {
10357 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
10358 DAG.getConstant(X86::COND_B, MVT::i8), Cond);
10359 if (isAllOnes(Op1) != (CondCode == X86::COND_B))
10360 return DAG.getNOT(DL, Res, Res.getValueType());
10365 // X86 doesn't have an i8 cmov. If both operands are the result of a truncate
10366 // widen the cmov and push the truncate through. This avoids introducing a new
10367 // branch during isel and doesn't add any extensions.
10368 if (Op.getValueType() == MVT::i8 &&
10369 Op1.getOpcode() == ISD::TRUNCATE && Op2.getOpcode() == ISD::TRUNCATE) {
10370 SDValue T1 = Op1.getOperand(0), T2 = Op2.getOperand(0);
10371 if (T1.getValueType() == T2.getValueType() &&
10372 // Blacklist CopyFromReg to avoid partial register stalls.
10373 T1.getOpcode() != ISD::CopyFromReg && T2.getOpcode()!=ISD::CopyFromReg){
10374 SDVTList VTs = DAG.getVTList(T1.getValueType(), MVT::Glue);
10375 SDValue Cmov = DAG.getNode(X86ISD::CMOV, DL, VTs, T2, T1, CC, Cond);
10376 return DAG.getNode(ISD::TRUNCATE, DL, Op.getValueType(), Cmov);
10380 // X86ISD::CMOV means set the result (which is operand 1) to the RHS if
10381 // condition is true.
10382 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue);
10383 SDValue Ops[] = { Op2, Op1, CC, Cond };
10384 return DAG.getNode(X86ISD::CMOV, DL, VTs, Ops, array_lengthof(Ops));
10387 static SDValue LowerSIGN_EXTEND_AVX512(SDValue Op, SelectionDAG &DAG) {
10388 MVT VT = Op->getSimpleValueType(0);
10389 SDValue In = Op->getOperand(0);
10390 MVT InVT = In.getSimpleValueType();
10393 unsigned int NumElts = VT.getVectorNumElements();
10394 if (NumElts != 8 && NumElts != 16)
10397 if (VT.is512BitVector() && InVT.getVectorElementType() != MVT::i1)
10398 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
10400 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
10401 assert (InVT.getVectorElementType() == MVT::i1 && "Unexpected vector type");
10403 MVT ExtVT = (NumElts == 8) ? MVT::v8i64 : MVT::v16i32;
10404 Constant *C = ConstantInt::get(*DAG.getContext(),
10405 APInt::getAllOnesValue(ExtVT.getScalarType().getSizeInBits()));
10407 SDValue CP = DAG.getConstantPool(C, TLI.getPointerTy());
10408 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
10409 SDValue Ld = DAG.getLoad(ExtVT.getScalarType(), dl, DAG.getEntryNode(), CP,
10410 MachinePointerInfo::getConstantPool(),
10411 false, false, false, Alignment);
10412 SDValue Brcst = DAG.getNode(X86ISD::VBROADCASTM, dl, ExtVT, In, Ld);
10413 if (VT.is512BitVector())
10415 return DAG.getNode(X86ISD::VTRUNC, dl, VT, Brcst);
10418 static SDValue LowerSIGN_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
10419 SelectionDAG &DAG) {
10420 MVT VT = Op->getSimpleValueType(0);
10421 SDValue In = Op->getOperand(0);
10422 MVT InVT = In.getSimpleValueType();
10425 if (VT.is512BitVector() || InVT.getVectorElementType() == MVT::i1)
10426 return LowerSIGN_EXTEND_AVX512(Op, DAG);
10428 if ((VT != MVT::v4i64 || InVT != MVT::v4i32) &&
10429 (VT != MVT::v8i32 || InVT != MVT::v8i16) &&
10430 (VT != MVT::v16i16 || InVT != MVT::v16i8))
10433 if (Subtarget->hasInt256())
10434 return DAG.getNode(X86ISD::VSEXT_MOVL, dl, VT, In);
10436 // Optimize vectors in AVX mode
10437 // Sign extend v8i16 to v8i32 and
10440 // Divide input vector into two parts
10441 // for v4i32 the shuffle mask will be { 0, 1, -1, -1} {2, 3, -1, -1}
10442 // use vpmovsx instruction to extend v4i32 -> v2i64; v8i16 -> v4i32
10443 // concat the vectors to original VT
10445 unsigned NumElems = InVT.getVectorNumElements();
10446 SDValue Undef = DAG.getUNDEF(InVT);
10448 SmallVector<int,8> ShufMask1(NumElems, -1);
10449 for (unsigned i = 0; i != NumElems/2; ++i)
10452 SDValue OpLo = DAG.getVectorShuffle(InVT, dl, In, Undef, &ShufMask1[0]);
10454 SmallVector<int,8> ShufMask2(NumElems, -1);
10455 for (unsigned i = 0; i != NumElems/2; ++i)
10456 ShufMask2[i] = i + NumElems/2;
10458 SDValue OpHi = DAG.getVectorShuffle(InVT, dl, In, Undef, &ShufMask2[0]);
10460 MVT HalfVT = MVT::getVectorVT(VT.getScalarType(),
10461 VT.getVectorNumElements()/2);
10463 OpLo = DAG.getNode(X86ISD::VSEXT_MOVL, dl, HalfVT, OpLo);
10464 OpHi = DAG.getNode(X86ISD::VSEXT_MOVL, dl, HalfVT, OpHi);
10466 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi);
10469 // isAndOrOfSingleUseSetCCs - Return true if node is an ISD::AND or
10470 // ISD::OR of two X86ISD::SETCC nodes each of which has no other use apart
10471 // from the AND / OR.
10472 static bool isAndOrOfSetCCs(SDValue Op, unsigned &Opc) {
10473 Opc = Op.getOpcode();
10474 if (Opc != ISD::OR && Opc != ISD::AND)
10476 return (Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
10477 Op.getOperand(0).hasOneUse() &&
10478 Op.getOperand(1).getOpcode() == X86ISD::SETCC &&
10479 Op.getOperand(1).hasOneUse());
10482 // isXor1OfSetCC - Return true if node is an ISD::XOR of a X86ISD::SETCC and
10483 // 1 and that the SETCC node has a single use.
10484 static bool isXor1OfSetCC(SDValue Op) {
10485 if (Op.getOpcode() != ISD::XOR)
10487 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
10488 if (N1C && N1C->getAPIntValue() == 1) {
10489 return Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
10490 Op.getOperand(0).hasOneUse();
10495 SDValue X86TargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) const {
10496 bool addTest = true;
10497 SDValue Chain = Op.getOperand(0);
10498 SDValue Cond = Op.getOperand(1);
10499 SDValue Dest = Op.getOperand(2);
10502 bool Inverted = false;
10504 if (Cond.getOpcode() == ISD::SETCC) {
10505 // Check for setcc([su]{add,sub,mul}o == 0).
10506 if (cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETEQ &&
10507 isa<ConstantSDNode>(Cond.getOperand(1)) &&
10508 cast<ConstantSDNode>(Cond.getOperand(1))->isNullValue() &&
10509 Cond.getOperand(0).getResNo() == 1 &&
10510 (Cond.getOperand(0).getOpcode() == ISD::SADDO ||
10511 Cond.getOperand(0).getOpcode() == ISD::UADDO ||
10512 Cond.getOperand(0).getOpcode() == ISD::SSUBO ||
10513 Cond.getOperand(0).getOpcode() == ISD::USUBO ||
10514 Cond.getOperand(0).getOpcode() == ISD::SMULO ||
10515 Cond.getOperand(0).getOpcode() == ISD::UMULO)) {
10517 Cond = Cond.getOperand(0);
10519 SDValue NewCond = LowerSETCC(Cond, DAG);
10520 if (NewCond.getNode())
10525 // FIXME: LowerXALUO doesn't handle these!!
10526 else if (Cond.getOpcode() == X86ISD::ADD ||
10527 Cond.getOpcode() == X86ISD::SUB ||
10528 Cond.getOpcode() == X86ISD::SMUL ||
10529 Cond.getOpcode() == X86ISD::UMUL)
10530 Cond = LowerXALUO(Cond, DAG);
10533 // Look pass (and (setcc_carry (cmp ...)), 1).
10534 if (Cond.getOpcode() == ISD::AND &&
10535 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
10536 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
10537 if (C && C->getAPIntValue() == 1)
10538 Cond = Cond.getOperand(0);
10541 // If condition flag is set by a X86ISD::CMP, then use it as the condition
10542 // setting operand in place of the X86ISD::SETCC.
10543 unsigned CondOpcode = Cond.getOpcode();
10544 if (CondOpcode == X86ISD::SETCC ||
10545 CondOpcode == X86ISD::SETCC_CARRY) {
10546 CC = Cond.getOperand(0);
10548 SDValue Cmp = Cond.getOperand(1);
10549 unsigned Opc = Cmp.getOpcode();
10550 // FIXME: WHY THE SPECIAL CASING OF LogicalCmp??
10551 if (isX86LogicalCmp(Cmp) || Opc == X86ISD::BT) {
10555 switch (cast<ConstantSDNode>(CC)->getZExtValue()) {
10559 // These can only come from an arithmetic instruction with overflow,
10560 // e.g. SADDO, UADDO.
10561 Cond = Cond.getNode()->getOperand(1);
10567 CondOpcode = Cond.getOpcode();
10568 if (CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO ||
10569 CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO ||
10570 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) &&
10571 Cond.getOperand(0).getValueType() != MVT::i8)) {
10572 SDValue LHS = Cond.getOperand(0);
10573 SDValue RHS = Cond.getOperand(1);
10574 unsigned X86Opcode;
10577 switch (CondOpcode) {
10578 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break;
10579 case ISD::SADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break;
10580 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break;
10581 case ISD::SSUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break;
10582 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break;
10583 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break;
10584 default: llvm_unreachable("unexpected overflowing operator");
10587 X86Cond = X86::GetOppositeBranchCondition((X86::CondCode)X86Cond);
10588 if (CondOpcode == ISD::UMULO)
10589 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(),
10592 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
10594 SDValue X86Op = DAG.getNode(X86Opcode, dl, VTs, LHS, RHS);
10596 if (CondOpcode == ISD::UMULO)
10597 Cond = X86Op.getValue(2);
10599 Cond = X86Op.getValue(1);
10601 CC = DAG.getConstant(X86Cond, MVT::i8);
10605 if (Cond.hasOneUse() && isAndOrOfSetCCs(Cond, CondOpc)) {
10606 SDValue Cmp = Cond.getOperand(0).getOperand(1);
10607 if (CondOpc == ISD::OR) {
10608 // Also, recognize the pattern generated by an FCMP_UNE. We can emit
10609 // two branches instead of an explicit OR instruction with a
10611 if (Cmp == Cond.getOperand(1).getOperand(1) &&
10612 isX86LogicalCmp(Cmp)) {
10613 CC = Cond.getOperand(0).getOperand(0);
10614 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
10615 Chain, Dest, CC, Cmp);
10616 CC = Cond.getOperand(1).getOperand(0);
10620 } else { // ISD::AND
10621 // Also, recognize the pattern generated by an FCMP_OEQ. We can emit
10622 // two branches instead of an explicit AND instruction with a
10623 // separate test. However, we only do this if this block doesn't
10624 // have a fall-through edge, because this requires an explicit
10625 // jmp when the condition is false.
10626 if (Cmp == Cond.getOperand(1).getOperand(1) &&
10627 isX86LogicalCmp(Cmp) &&
10628 Op.getNode()->hasOneUse()) {
10629 X86::CondCode CCode =
10630 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
10631 CCode = X86::GetOppositeBranchCondition(CCode);
10632 CC = DAG.getConstant(CCode, MVT::i8);
10633 SDNode *User = *Op.getNode()->use_begin();
10634 // Look for an unconditional branch following this conditional branch.
10635 // We need this because we need to reverse the successors in order
10636 // to implement FCMP_OEQ.
10637 if (User->getOpcode() == ISD::BR) {
10638 SDValue FalseBB = User->getOperand(1);
10640 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
10641 assert(NewBR == User);
10645 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
10646 Chain, Dest, CC, Cmp);
10647 X86::CondCode CCode =
10648 (X86::CondCode)Cond.getOperand(1).getConstantOperandVal(0);
10649 CCode = X86::GetOppositeBranchCondition(CCode);
10650 CC = DAG.getConstant(CCode, MVT::i8);
10656 } else if (Cond.hasOneUse() && isXor1OfSetCC(Cond)) {
10657 // Recognize for xorb (setcc), 1 patterns. The xor inverts the condition.
10658 // It should be transformed during dag combiner except when the condition
10659 // is set by a arithmetics with overflow node.
10660 X86::CondCode CCode =
10661 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
10662 CCode = X86::GetOppositeBranchCondition(CCode);
10663 CC = DAG.getConstant(CCode, MVT::i8);
10664 Cond = Cond.getOperand(0).getOperand(1);
10666 } else if (Cond.getOpcode() == ISD::SETCC &&
10667 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETOEQ) {
10668 // For FCMP_OEQ, we can emit
10669 // two branches instead of an explicit AND instruction with a
10670 // separate test. However, we only do this if this block doesn't
10671 // have a fall-through edge, because this requires an explicit
10672 // jmp when the condition is false.
10673 if (Op.getNode()->hasOneUse()) {
10674 SDNode *User = *Op.getNode()->use_begin();
10675 // Look for an unconditional branch following this conditional branch.
10676 // We need this because we need to reverse the successors in order
10677 // to implement FCMP_OEQ.
10678 if (User->getOpcode() == ISD::BR) {
10679 SDValue FalseBB = User->getOperand(1);
10681 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
10682 assert(NewBR == User);
10686 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
10687 Cond.getOperand(0), Cond.getOperand(1));
10688 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
10689 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
10690 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
10691 Chain, Dest, CC, Cmp);
10692 CC = DAG.getConstant(X86::COND_P, MVT::i8);
10697 } else if (Cond.getOpcode() == ISD::SETCC &&
10698 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETUNE) {
10699 // For FCMP_UNE, we can emit
10700 // two branches instead of an explicit AND instruction with a
10701 // separate test. However, we only do this if this block doesn't
10702 // have a fall-through edge, because this requires an explicit
10703 // jmp when the condition is false.
10704 if (Op.getNode()->hasOneUse()) {
10705 SDNode *User = *Op.getNode()->use_begin();
10706 // Look for an unconditional branch following this conditional branch.
10707 // We need this because we need to reverse the successors in order
10708 // to implement FCMP_UNE.
10709 if (User->getOpcode() == ISD::BR) {
10710 SDValue FalseBB = User->getOperand(1);
10712 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
10713 assert(NewBR == User);
10716 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
10717 Cond.getOperand(0), Cond.getOperand(1));
10718 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
10719 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
10720 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
10721 Chain, Dest, CC, Cmp);
10722 CC = DAG.getConstant(X86::COND_NP, MVT::i8);
10732 // Look pass the truncate if the high bits are known zero.
10733 if (isTruncWithZeroHighBitsInput(Cond, DAG))
10734 Cond = Cond.getOperand(0);
10736 // We know the result of AND is compared against zero. Try to match
10738 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
10739 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, dl, DAG);
10740 if (NewSetCC.getNode()) {
10741 CC = NewSetCC.getOperand(0);
10742 Cond = NewSetCC.getOperand(1);
10749 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
10750 Cond = EmitTest(Cond, X86::COND_NE, DAG);
10752 Cond = ConvertCmpIfNecessary(Cond, DAG);
10753 return DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
10754 Chain, Dest, CC, Cond);
10757 // Lower dynamic stack allocation to _alloca call for Cygwin/Mingw targets.
10758 // Calls to _alloca is needed to probe the stack when allocating more than 4k
10759 // bytes in one go. Touching the stack at 4K increments is necessary to ensure
10760 // that the guard pages used by the OS virtual memory manager are allocated in
10761 // correct sequence.
10763 X86TargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
10764 SelectionDAG &DAG) const {
10765 assert((Subtarget->isTargetCygMing() || Subtarget->isTargetWindows() ||
10766 getTargetMachine().Options.EnableSegmentedStacks) &&
10767 "This should be used only on Windows targets or when segmented stacks "
10769 assert(!Subtarget->isTargetEnvMacho() && "Not implemented");
10773 SDValue Chain = Op.getOperand(0);
10774 SDValue Size = Op.getOperand(1);
10775 unsigned Align = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue();
10776 EVT VT = Op.getNode()->getValueType(0);
10778 bool Is64Bit = Subtarget->is64Bit();
10779 EVT SPTy = Is64Bit ? MVT::i64 : MVT::i32;
10781 if (getTargetMachine().Options.EnableSegmentedStacks) {
10782 MachineFunction &MF = DAG.getMachineFunction();
10783 MachineRegisterInfo &MRI = MF.getRegInfo();
10786 // The 64 bit implementation of segmented stacks needs to clobber both r10
10787 // r11. This makes it impossible to use it along with nested parameters.
10788 const Function *F = MF.getFunction();
10790 for (Function::const_arg_iterator I = F->arg_begin(), E = F->arg_end();
10792 if (I->hasNestAttr())
10793 report_fatal_error("Cannot use segmented stacks with functions that "
10794 "have nested arguments.");
10797 const TargetRegisterClass *AddrRegClass =
10798 getRegClassFor(Subtarget->is64Bit() ? MVT::i64:MVT::i32);
10799 unsigned Vreg = MRI.createVirtualRegister(AddrRegClass);
10800 Chain = DAG.getCopyToReg(Chain, dl, Vreg, Size);
10801 SDValue Value = DAG.getNode(X86ISD::SEG_ALLOCA, dl, SPTy, Chain,
10802 DAG.getRegister(Vreg, SPTy));
10803 SDValue Ops1[2] = { Value, Chain };
10804 return DAG.getMergeValues(Ops1, 2, dl);
10807 unsigned Reg = (Subtarget->is64Bit() ? X86::RAX : X86::EAX);
10809 Chain = DAG.getCopyToReg(Chain, dl, Reg, Size, Flag);
10810 Flag = Chain.getValue(1);
10811 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
10813 Chain = DAG.getNode(X86ISD::WIN_ALLOCA, dl, NodeTys, Chain, Flag);
10815 const X86RegisterInfo *RegInfo =
10816 static_cast<const X86RegisterInfo*>(getTargetMachine().getRegisterInfo());
10817 unsigned SPReg = RegInfo->getStackRegister();
10818 SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, SPTy);
10819 Chain = SP.getValue(1);
10822 SP = DAG.getNode(ISD::AND, dl, VT, SP.getValue(0),
10823 DAG.getConstant(-(uint64_t)Align, VT));
10824 Chain = DAG.getCopyToReg(Chain, dl, SPReg, SP);
10827 SDValue Ops1[2] = { SP, Chain };
10828 return DAG.getMergeValues(Ops1, 2, dl);
10832 SDValue X86TargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const {
10833 MachineFunction &MF = DAG.getMachineFunction();
10834 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
10836 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
10839 if (!Subtarget->is64Bit() || Subtarget->isTargetWin64()) {
10840 // vastart just stores the address of the VarArgsFrameIndex slot into the
10841 // memory location argument.
10842 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
10844 return DAG.getStore(Op.getOperand(0), DL, FR, Op.getOperand(1),
10845 MachinePointerInfo(SV), false, false, 0);
10849 // gp_offset (0 - 6 * 8)
10850 // fp_offset (48 - 48 + 8 * 16)
10851 // overflow_arg_area (point to parameters coming in memory).
10853 SmallVector<SDValue, 8> MemOps;
10854 SDValue FIN = Op.getOperand(1);
10856 SDValue Store = DAG.getStore(Op.getOperand(0), DL,
10857 DAG.getConstant(FuncInfo->getVarArgsGPOffset(),
10859 FIN, MachinePointerInfo(SV), false, false, 0);
10860 MemOps.push_back(Store);
10863 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
10864 FIN, DAG.getIntPtrConstant(4));
10865 Store = DAG.getStore(Op.getOperand(0), DL,
10866 DAG.getConstant(FuncInfo->getVarArgsFPOffset(),
10868 FIN, MachinePointerInfo(SV, 4), false, false, 0);
10869 MemOps.push_back(Store);
10871 // Store ptr to overflow_arg_area
10872 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
10873 FIN, DAG.getIntPtrConstant(4));
10874 SDValue OVFIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
10876 Store = DAG.getStore(Op.getOperand(0), DL, OVFIN, FIN,
10877 MachinePointerInfo(SV, 8),
10879 MemOps.push_back(Store);
10881 // Store ptr to reg_save_area.
10882 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
10883 FIN, DAG.getIntPtrConstant(8));
10884 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
10886 Store = DAG.getStore(Op.getOperand(0), DL, RSFIN, FIN,
10887 MachinePointerInfo(SV, 16), false, false, 0);
10888 MemOps.push_back(Store);
10889 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
10890 &MemOps[0], MemOps.size());
10893 SDValue X86TargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG) const {
10894 assert(Subtarget->is64Bit() &&
10895 "LowerVAARG only handles 64-bit va_arg!");
10896 assert((Subtarget->isTargetLinux() ||
10897 Subtarget->isTargetDarwin()) &&
10898 "Unhandled target in LowerVAARG");
10899 assert(Op.getNode()->getNumOperands() == 4);
10900 SDValue Chain = Op.getOperand(0);
10901 SDValue SrcPtr = Op.getOperand(1);
10902 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
10903 unsigned Align = Op.getConstantOperandVal(3);
10906 EVT ArgVT = Op.getNode()->getValueType(0);
10907 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
10908 uint32_t ArgSize = getDataLayout()->getTypeAllocSize(ArgTy);
10911 // Decide which area this value should be read from.
10912 // TODO: Implement the AMD64 ABI in its entirety. This simple
10913 // selection mechanism works only for the basic types.
10914 if (ArgVT == MVT::f80) {
10915 llvm_unreachable("va_arg for f80 not yet implemented");
10916 } else if (ArgVT.isFloatingPoint() && ArgSize <= 16 /*bytes*/) {
10917 ArgMode = 2; // Argument passed in XMM register. Use fp_offset.
10918 } else if (ArgVT.isInteger() && ArgSize <= 32 /*bytes*/) {
10919 ArgMode = 1; // Argument passed in GPR64 register(s). Use gp_offset.
10921 llvm_unreachable("Unhandled argument type in LowerVAARG");
10924 if (ArgMode == 2) {
10925 // Sanity Check: Make sure using fp_offset makes sense.
10926 assert(!getTargetMachine().Options.UseSoftFloat &&
10927 !(DAG.getMachineFunction()
10928 .getFunction()->getAttributes()
10929 .hasAttribute(AttributeSet::FunctionIndex,
10930 Attribute::NoImplicitFloat)) &&
10931 Subtarget->hasSSE1());
10934 // Insert VAARG_64 node into the DAG
10935 // VAARG_64 returns two values: Variable Argument Address, Chain
10936 SmallVector<SDValue, 11> InstOps;
10937 InstOps.push_back(Chain);
10938 InstOps.push_back(SrcPtr);
10939 InstOps.push_back(DAG.getConstant(ArgSize, MVT::i32));
10940 InstOps.push_back(DAG.getConstant(ArgMode, MVT::i8));
10941 InstOps.push_back(DAG.getConstant(Align, MVT::i32));
10942 SDVTList VTs = DAG.getVTList(getPointerTy(), MVT::Other);
10943 SDValue VAARG = DAG.getMemIntrinsicNode(X86ISD::VAARG_64, dl,
10944 VTs, &InstOps[0], InstOps.size(),
10946 MachinePointerInfo(SV),
10948 /*Volatile=*/false,
10950 /*WriteMem=*/true);
10951 Chain = VAARG.getValue(1);
10953 // Load the next argument and return it
10954 return DAG.getLoad(ArgVT, dl,
10957 MachinePointerInfo(),
10958 false, false, false, 0);
10961 static SDValue LowerVACOPY(SDValue Op, const X86Subtarget *Subtarget,
10962 SelectionDAG &DAG) {
10963 // X86-64 va_list is a struct { i32, i32, i8*, i8* }.
10964 assert(Subtarget->is64Bit() && "This code only handles 64-bit va_copy!");
10965 SDValue Chain = Op.getOperand(0);
10966 SDValue DstPtr = Op.getOperand(1);
10967 SDValue SrcPtr = Op.getOperand(2);
10968 const Value *DstSV = cast<SrcValueSDNode>(Op.getOperand(3))->getValue();
10969 const Value *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
10972 return DAG.getMemcpy(Chain, DL, DstPtr, SrcPtr,
10973 DAG.getIntPtrConstant(24), 8, /*isVolatile*/false,
10975 MachinePointerInfo(DstSV), MachinePointerInfo(SrcSV));
10978 // getTargetVShiftByConstNode - Handle vector element shifts where the shift
10979 // amount is a constant. Takes immediate version of shift as input.
10980 static SDValue getTargetVShiftByConstNode(unsigned Opc, SDLoc dl, EVT VT,
10981 SDValue SrcOp, uint64_t ShiftAmt,
10982 SelectionDAG &DAG) {
10984 // Check for ShiftAmt >= element width
10985 if (ShiftAmt >= VT.getVectorElementType().getSizeInBits()) {
10986 if (Opc == X86ISD::VSRAI)
10987 ShiftAmt = VT.getVectorElementType().getSizeInBits() - 1;
10989 return DAG.getConstant(0, VT);
10992 assert((Opc == X86ISD::VSHLI || Opc == X86ISD::VSRLI || Opc == X86ISD::VSRAI)
10993 && "Unknown target vector shift-by-constant node");
10995 return DAG.getNode(Opc, dl, VT, SrcOp, DAG.getConstant(ShiftAmt, MVT::i8));
10998 // getTargetVShiftNode - Handle vector element shifts where the shift amount
10999 // may or may not be a constant. Takes immediate version of shift as input.
11000 static SDValue getTargetVShiftNode(unsigned Opc, SDLoc dl, EVT VT,
11001 SDValue SrcOp, SDValue ShAmt,
11002 SelectionDAG &DAG) {
11003 assert(ShAmt.getValueType() == MVT::i32 && "ShAmt is not i32");
11005 // Catch shift-by-constant.
11006 if (ConstantSDNode *CShAmt = dyn_cast<ConstantSDNode>(ShAmt))
11007 return getTargetVShiftByConstNode(Opc, dl, VT, SrcOp,
11008 CShAmt->getZExtValue(), DAG);
11010 // Change opcode to non-immediate version
11012 default: llvm_unreachable("Unknown target vector shift node");
11013 case X86ISD::VSHLI: Opc = X86ISD::VSHL; break;
11014 case X86ISD::VSRLI: Opc = X86ISD::VSRL; break;
11015 case X86ISD::VSRAI: Opc = X86ISD::VSRA; break;
11018 // Need to build a vector containing shift amount
11019 // Shift amount is 32-bits, but SSE instructions read 64-bit, so fill with 0
11022 ShOps[1] = DAG.getConstant(0, MVT::i32);
11023 ShOps[2] = ShOps[3] = DAG.getUNDEF(MVT::i32);
11024 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, &ShOps[0], 4);
11026 // The return type has to be a 128-bit type with the same element
11027 // type as the input type.
11028 MVT EltVT = VT.getVectorElementType().getSimpleVT();
11029 EVT ShVT = MVT::getVectorVT(EltVT, 128/EltVT.getSizeInBits());
11031 ShAmt = DAG.getNode(ISD::BITCAST, dl, ShVT, ShAmt);
11032 return DAG.getNode(Opc, dl, VT, SrcOp, ShAmt);
11035 static SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) {
11037 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
11039 default: return SDValue(); // Don't custom lower most intrinsics.
11040 // Comparison intrinsics.
11041 case Intrinsic::x86_sse_comieq_ss:
11042 case Intrinsic::x86_sse_comilt_ss:
11043 case Intrinsic::x86_sse_comile_ss:
11044 case Intrinsic::x86_sse_comigt_ss:
11045 case Intrinsic::x86_sse_comige_ss:
11046 case Intrinsic::x86_sse_comineq_ss:
11047 case Intrinsic::x86_sse_ucomieq_ss:
11048 case Intrinsic::x86_sse_ucomilt_ss:
11049 case Intrinsic::x86_sse_ucomile_ss:
11050 case Intrinsic::x86_sse_ucomigt_ss:
11051 case Intrinsic::x86_sse_ucomige_ss:
11052 case Intrinsic::x86_sse_ucomineq_ss:
11053 case Intrinsic::x86_sse2_comieq_sd:
11054 case Intrinsic::x86_sse2_comilt_sd:
11055 case Intrinsic::x86_sse2_comile_sd:
11056 case Intrinsic::x86_sse2_comigt_sd:
11057 case Intrinsic::x86_sse2_comige_sd:
11058 case Intrinsic::x86_sse2_comineq_sd:
11059 case Intrinsic::x86_sse2_ucomieq_sd:
11060 case Intrinsic::x86_sse2_ucomilt_sd:
11061 case Intrinsic::x86_sse2_ucomile_sd:
11062 case Intrinsic::x86_sse2_ucomigt_sd:
11063 case Intrinsic::x86_sse2_ucomige_sd:
11064 case Intrinsic::x86_sse2_ucomineq_sd: {
11068 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
11069 case Intrinsic::x86_sse_comieq_ss:
11070 case Intrinsic::x86_sse2_comieq_sd:
11071 Opc = X86ISD::COMI;
11074 case Intrinsic::x86_sse_comilt_ss:
11075 case Intrinsic::x86_sse2_comilt_sd:
11076 Opc = X86ISD::COMI;
11079 case Intrinsic::x86_sse_comile_ss:
11080 case Intrinsic::x86_sse2_comile_sd:
11081 Opc = X86ISD::COMI;
11084 case Intrinsic::x86_sse_comigt_ss:
11085 case Intrinsic::x86_sse2_comigt_sd:
11086 Opc = X86ISD::COMI;
11089 case Intrinsic::x86_sse_comige_ss:
11090 case Intrinsic::x86_sse2_comige_sd:
11091 Opc = X86ISD::COMI;
11094 case Intrinsic::x86_sse_comineq_ss:
11095 case Intrinsic::x86_sse2_comineq_sd:
11096 Opc = X86ISD::COMI;
11099 case Intrinsic::x86_sse_ucomieq_ss:
11100 case Intrinsic::x86_sse2_ucomieq_sd:
11101 Opc = X86ISD::UCOMI;
11104 case Intrinsic::x86_sse_ucomilt_ss:
11105 case Intrinsic::x86_sse2_ucomilt_sd:
11106 Opc = X86ISD::UCOMI;
11109 case Intrinsic::x86_sse_ucomile_ss:
11110 case Intrinsic::x86_sse2_ucomile_sd:
11111 Opc = X86ISD::UCOMI;
11114 case Intrinsic::x86_sse_ucomigt_ss:
11115 case Intrinsic::x86_sse2_ucomigt_sd:
11116 Opc = X86ISD::UCOMI;
11119 case Intrinsic::x86_sse_ucomige_ss:
11120 case Intrinsic::x86_sse2_ucomige_sd:
11121 Opc = X86ISD::UCOMI;
11124 case Intrinsic::x86_sse_ucomineq_ss:
11125 case Intrinsic::x86_sse2_ucomineq_sd:
11126 Opc = X86ISD::UCOMI;
11131 SDValue LHS = Op.getOperand(1);
11132 SDValue RHS = Op.getOperand(2);
11133 unsigned X86CC = TranslateX86CC(CC, true, LHS, RHS, DAG);
11134 assert(X86CC != X86::COND_INVALID && "Unexpected illegal condition!");
11135 SDValue Cond = DAG.getNode(Opc, dl, MVT::i32, LHS, RHS);
11136 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
11137 DAG.getConstant(X86CC, MVT::i8), Cond);
11138 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
11141 // Arithmetic intrinsics.
11142 case Intrinsic::x86_sse2_pmulu_dq:
11143 case Intrinsic::x86_avx2_pmulu_dq:
11144 return DAG.getNode(X86ISD::PMULUDQ, dl, Op.getValueType(),
11145 Op.getOperand(1), Op.getOperand(2));
11147 // SSE2/AVX2 sub with unsigned saturation intrinsics
11148 case Intrinsic::x86_sse2_psubus_b:
11149 case Intrinsic::x86_sse2_psubus_w:
11150 case Intrinsic::x86_avx2_psubus_b:
11151 case Intrinsic::x86_avx2_psubus_w:
11152 return DAG.getNode(X86ISD::SUBUS, dl, Op.getValueType(),
11153 Op.getOperand(1), Op.getOperand(2));
11155 // SSE3/AVX horizontal add/sub intrinsics
11156 case Intrinsic::x86_sse3_hadd_ps:
11157 case Intrinsic::x86_sse3_hadd_pd:
11158 case Intrinsic::x86_avx_hadd_ps_256:
11159 case Intrinsic::x86_avx_hadd_pd_256:
11160 case Intrinsic::x86_sse3_hsub_ps:
11161 case Intrinsic::x86_sse3_hsub_pd:
11162 case Intrinsic::x86_avx_hsub_ps_256:
11163 case Intrinsic::x86_avx_hsub_pd_256:
11164 case Intrinsic::x86_ssse3_phadd_w_128:
11165 case Intrinsic::x86_ssse3_phadd_d_128:
11166 case Intrinsic::x86_avx2_phadd_w:
11167 case Intrinsic::x86_avx2_phadd_d:
11168 case Intrinsic::x86_ssse3_phsub_w_128:
11169 case Intrinsic::x86_ssse3_phsub_d_128:
11170 case Intrinsic::x86_avx2_phsub_w:
11171 case Intrinsic::x86_avx2_phsub_d: {
11174 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
11175 case Intrinsic::x86_sse3_hadd_ps:
11176 case Intrinsic::x86_sse3_hadd_pd:
11177 case Intrinsic::x86_avx_hadd_ps_256:
11178 case Intrinsic::x86_avx_hadd_pd_256:
11179 Opcode = X86ISD::FHADD;
11181 case Intrinsic::x86_sse3_hsub_ps:
11182 case Intrinsic::x86_sse3_hsub_pd:
11183 case Intrinsic::x86_avx_hsub_ps_256:
11184 case Intrinsic::x86_avx_hsub_pd_256:
11185 Opcode = X86ISD::FHSUB;
11187 case Intrinsic::x86_ssse3_phadd_w_128:
11188 case Intrinsic::x86_ssse3_phadd_d_128:
11189 case Intrinsic::x86_avx2_phadd_w:
11190 case Intrinsic::x86_avx2_phadd_d:
11191 Opcode = X86ISD::HADD;
11193 case Intrinsic::x86_ssse3_phsub_w_128:
11194 case Intrinsic::x86_ssse3_phsub_d_128:
11195 case Intrinsic::x86_avx2_phsub_w:
11196 case Intrinsic::x86_avx2_phsub_d:
11197 Opcode = X86ISD::HSUB;
11200 return DAG.getNode(Opcode, dl, Op.getValueType(),
11201 Op.getOperand(1), Op.getOperand(2));
11204 // SSE2/SSE41/AVX2 integer max/min intrinsics.
11205 case Intrinsic::x86_sse2_pmaxu_b:
11206 case Intrinsic::x86_sse41_pmaxuw:
11207 case Intrinsic::x86_sse41_pmaxud:
11208 case Intrinsic::x86_avx2_pmaxu_b:
11209 case Intrinsic::x86_avx2_pmaxu_w:
11210 case Intrinsic::x86_avx2_pmaxu_d:
11211 case Intrinsic::x86_avx512_pmaxu_d:
11212 case Intrinsic::x86_avx512_pmaxu_q:
11213 case Intrinsic::x86_sse2_pminu_b:
11214 case Intrinsic::x86_sse41_pminuw:
11215 case Intrinsic::x86_sse41_pminud:
11216 case Intrinsic::x86_avx2_pminu_b:
11217 case Intrinsic::x86_avx2_pminu_w:
11218 case Intrinsic::x86_avx2_pminu_d:
11219 case Intrinsic::x86_avx512_pminu_d:
11220 case Intrinsic::x86_avx512_pminu_q:
11221 case Intrinsic::x86_sse41_pmaxsb:
11222 case Intrinsic::x86_sse2_pmaxs_w:
11223 case Intrinsic::x86_sse41_pmaxsd:
11224 case Intrinsic::x86_avx2_pmaxs_b:
11225 case Intrinsic::x86_avx2_pmaxs_w:
11226 case Intrinsic::x86_avx2_pmaxs_d:
11227 case Intrinsic::x86_avx512_pmaxs_d:
11228 case Intrinsic::x86_avx512_pmaxs_q:
11229 case Intrinsic::x86_sse41_pminsb:
11230 case Intrinsic::x86_sse2_pmins_w:
11231 case Intrinsic::x86_sse41_pminsd:
11232 case Intrinsic::x86_avx2_pmins_b:
11233 case Intrinsic::x86_avx2_pmins_w:
11234 case Intrinsic::x86_avx2_pmins_d:
11235 case Intrinsic::x86_avx512_pmins_d:
11236 case Intrinsic::x86_avx512_pmins_q: {
11239 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
11240 case Intrinsic::x86_sse2_pmaxu_b:
11241 case Intrinsic::x86_sse41_pmaxuw:
11242 case Intrinsic::x86_sse41_pmaxud:
11243 case Intrinsic::x86_avx2_pmaxu_b:
11244 case Intrinsic::x86_avx2_pmaxu_w:
11245 case Intrinsic::x86_avx2_pmaxu_d:
11246 case Intrinsic::x86_avx512_pmaxu_d:
11247 case Intrinsic::x86_avx512_pmaxu_q:
11248 Opcode = X86ISD::UMAX;
11250 case Intrinsic::x86_sse2_pminu_b:
11251 case Intrinsic::x86_sse41_pminuw:
11252 case Intrinsic::x86_sse41_pminud:
11253 case Intrinsic::x86_avx2_pminu_b:
11254 case Intrinsic::x86_avx2_pminu_w:
11255 case Intrinsic::x86_avx2_pminu_d:
11256 case Intrinsic::x86_avx512_pminu_d:
11257 case Intrinsic::x86_avx512_pminu_q:
11258 Opcode = X86ISD::UMIN;
11260 case Intrinsic::x86_sse41_pmaxsb:
11261 case Intrinsic::x86_sse2_pmaxs_w:
11262 case Intrinsic::x86_sse41_pmaxsd:
11263 case Intrinsic::x86_avx2_pmaxs_b:
11264 case Intrinsic::x86_avx2_pmaxs_w:
11265 case Intrinsic::x86_avx2_pmaxs_d:
11266 case Intrinsic::x86_avx512_pmaxs_d:
11267 case Intrinsic::x86_avx512_pmaxs_q:
11268 Opcode = X86ISD::SMAX;
11270 case Intrinsic::x86_sse41_pminsb:
11271 case Intrinsic::x86_sse2_pmins_w:
11272 case Intrinsic::x86_sse41_pminsd:
11273 case Intrinsic::x86_avx2_pmins_b:
11274 case Intrinsic::x86_avx2_pmins_w:
11275 case Intrinsic::x86_avx2_pmins_d:
11276 case Intrinsic::x86_avx512_pmins_d:
11277 case Intrinsic::x86_avx512_pmins_q:
11278 Opcode = X86ISD::SMIN;
11281 return DAG.getNode(Opcode, dl, Op.getValueType(),
11282 Op.getOperand(1), Op.getOperand(2));
11285 // SSE/SSE2/AVX floating point max/min intrinsics.
11286 case Intrinsic::x86_sse_max_ps:
11287 case Intrinsic::x86_sse2_max_pd:
11288 case Intrinsic::x86_avx_max_ps_256:
11289 case Intrinsic::x86_avx_max_pd_256:
11290 case Intrinsic::x86_avx512_max_ps_512:
11291 case Intrinsic::x86_avx512_max_pd_512:
11292 case Intrinsic::x86_sse_min_ps:
11293 case Intrinsic::x86_sse2_min_pd:
11294 case Intrinsic::x86_avx_min_ps_256:
11295 case Intrinsic::x86_avx_min_pd_256:
11296 case Intrinsic::x86_avx512_min_ps_512:
11297 case Intrinsic::x86_avx512_min_pd_512: {
11300 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
11301 case Intrinsic::x86_sse_max_ps:
11302 case Intrinsic::x86_sse2_max_pd:
11303 case Intrinsic::x86_avx_max_ps_256:
11304 case Intrinsic::x86_avx_max_pd_256:
11305 case Intrinsic::x86_avx512_max_ps_512:
11306 case Intrinsic::x86_avx512_max_pd_512:
11307 Opcode = X86ISD::FMAX;
11309 case Intrinsic::x86_sse_min_ps:
11310 case Intrinsic::x86_sse2_min_pd:
11311 case Intrinsic::x86_avx_min_ps_256:
11312 case Intrinsic::x86_avx_min_pd_256:
11313 case Intrinsic::x86_avx512_min_ps_512:
11314 case Intrinsic::x86_avx512_min_pd_512:
11315 Opcode = X86ISD::FMIN;
11318 return DAG.getNode(Opcode, dl, Op.getValueType(),
11319 Op.getOperand(1), Op.getOperand(2));
11322 // AVX2 variable shift intrinsics
11323 case Intrinsic::x86_avx2_psllv_d:
11324 case Intrinsic::x86_avx2_psllv_q:
11325 case Intrinsic::x86_avx2_psllv_d_256:
11326 case Intrinsic::x86_avx2_psllv_q_256:
11327 case Intrinsic::x86_avx2_psrlv_d:
11328 case Intrinsic::x86_avx2_psrlv_q:
11329 case Intrinsic::x86_avx2_psrlv_d_256:
11330 case Intrinsic::x86_avx2_psrlv_q_256:
11331 case Intrinsic::x86_avx2_psrav_d:
11332 case Intrinsic::x86_avx2_psrav_d_256: {
11335 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
11336 case Intrinsic::x86_avx2_psllv_d:
11337 case Intrinsic::x86_avx2_psllv_q:
11338 case Intrinsic::x86_avx2_psllv_d_256:
11339 case Intrinsic::x86_avx2_psllv_q_256:
11342 case Intrinsic::x86_avx2_psrlv_d:
11343 case Intrinsic::x86_avx2_psrlv_q:
11344 case Intrinsic::x86_avx2_psrlv_d_256:
11345 case Intrinsic::x86_avx2_psrlv_q_256:
11348 case Intrinsic::x86_avx2_psrav_d:
11349 case Intrinsic::x86_avx2_psrav_d_256:
11353 return DAG.getNode(Opcode, dl, Op.getValueType(),
11354 Op.getOperand(1), Op.getOperand(2));
11357 case Intrinsic::x86_ssse3_pshuf_b_128:
11358 case Intrinsic::x86_avx2_pshuf_b:
11359 return DAG.getNode(X86ISD::PSHUFB, dl, Op.getValueType(),
11360 Op.getOperand(1), Op.getOperand(2));
11362 case Intrinsic::x86_ssse3_psign_b_128:
11363 case Intrinsic::x86_ssse3_psign_w_128:
11364 case Intrinsic::x86_ssse3_psign_d_128:
11365 case Intrinsic::x86_avx2_psign_b:
11366 case Intrinsic::x86_avx2_psign_w:
11367 case Intrinsic::x86_avx2_psign_d:
11368 return DAG.getNode(X86ISD::PSIGN, dl, Op.getValueType(),
11369 Op.getOperand(1), Op.getOperand(2));
11371 case Intrinsic::x86_sse41_insertps:
11372 return DAG.getNode(X86ISD::INSERTPS, dl, Op.getValueType(),
11373 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
11375 case Intrinsic::x86_avx_vperm2f128_ps_256:
11376 case Intrinsic::x86_avx_vperm2f128_pd_256:
11377 case Intrinsic::x86_avx_vperm2f128_si_256:
11378 case Intrinsic::x86_avx2_vperm2i128:
11379 return DAG.getNode(X86ISD::VPERM2X128, dl, Op.getValueType(),
11380 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
11382 case Intrinsic::x86_avx2_permd:
11383 case Intrinsic::x86_avx2_permps:
11384 // Operands intentionally swapped. Mask is last operand to intrinsic,
11385 // but second operand for node/instruction.
11386 return DAG.getNode(X86ISD::VPERMV, dl, Op.getValueType(),
11387 Op.getOperand(2), Op.getOperand(1));
11389 case Intrinsic::x86_sse_sqrt_ps:
11390 case Intrinsic::x86_sse2_sqrt_pd:
11391 case Intrinsic::x86_avx_sqrt_ps_256:
11392 case Intrinsic::x86_avx_sqrt_pd_256:
11393 return DAG.getNode(ISD::FSQRT, dl, Op.getValueType(), Op.getOperand(1));
11395 // ptest and testp intrinsics. The intrinsic these come from are designed to
11396 // return an integer value, not just an instruction so lower it to the ptest
11397 // or testp pattern and a setcc for the result.
11398 case Intrinsic::x86_sse41_ptestz:
11399 case Intrinsic::x86_sse41_ptestc:
11400 case Intrinsic::x86_sse41_ptestnzc:
11401 case Intrinsic::x86_avx_ptestz_256:
11402 case Intrinsic::x86_avx_ptestc_256:
11403 case Intrinsic::x86_avx_ptestnzc_256:
11404 case Intrinsic::x86_avx_vtestz_ps:
11405 case Intrinsic::x86_avx_vtestc_ps:
11406 case Intrinsic::x86_avx_vtestnzc_ps:
11407 case Intrinsic::x86_avx_vtestz_pd:
11408 case Intrinsic::x86_avx_vtestc_pd:
11409 case Intrinsic::x86_avx_vtestnzc_pd:
11410 case Intrinsic::x86_avx_vtestz_ps_256:
11411 case Intrinsic::x86_avx_vtestc_ps_256:
11412 case Intrinsic::x86_avx_vtestnzc_ps_256:
11413 case Intrinsic::x86_avx_vtestz_pd_256:
11414 case Intrinsic::x86_avx_vtestc_pd_256:
11415 case Intrinsic::x86_avx_vtestnzc_pd_256: {
11416 bool IsTestPacked = false;
11419 default: llvm_unreachable("Bad fallthrough in Intrinsic lowering.");
11420 case Intrinsic::x86_avx_vtestz_ps:
11421 case Intrinsic::x86_avx_vtestz_pd:
11422 case Intrinsic::x86_avx_vtestz_ps_256:
11423 case Intrinsic::x86_avx_vtestz_pd_256:
11424 IsTestPacked = true; // Fallthrough
11425 case Intrinsic::x86_sse41_ptestz:
11426 case Intrinsic::x86_avx_ptestz_256:
11428 X86CC = X86::COND_E;
11430 case Intrinsic::x86_avx_vtestc_ps:
11431 case Intrinsic::x86_avx_vtestc_pd:
11432 case Intrinsic::x86_avx_vtestc_ps_256:
11433 case Intrinsic::x86_avx_vtestc_pd_256:
11434 IsTestPacked = true; // Fallthrough
11435 case Intrinsic::x86_sse41_ptestc:
11436 case Intrinsic::x86_avx_ptestc_256:
11438 X86CC = X86::COND_B;
11440 case Intrinsic::x86_avx_vtestnzc_ps:
11441 case Intrinsic::x86_avx_vtestnzc_pd:
11442 case Intrinsic::x86_avx_vtestnzc_ps_256:
11443 case Intrinsic::x86_avx_vtestnzc_pd_256:
11444 IsTestPacked = true; // Fallthrough
11445 case Intrinsic::x86_sse41_ptestnzc:
11446 case Intrinsic::x86_avx_ptestnzc_256:
11448 X86CC = X86::COND_A;
11452 SDValue LHS = Op.getOperand(1);
11453 SDValue RHS = Op.getOperand(2);
11454 unsigned TestOpc = IsTestPacked ? X86ISD::TESTP : X86ISD::PTEST;
11455 SDValue Test = DAG.getNode(TestOpc, dl, MVT::i32, LHS, RHS);
11456 SDValue CC = DAG.getConstant(X86CC, MVT::i8);
11457 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8, CC, Test);
11458 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
11460 case Intrinsic::x86_avx512_kortestz:
11461 case Intrinsic::x86_avx512_kortestc: {
11462 unsigned X86CC = (IntNo == Intrinsic::x86_avx512_kortestz)? X86::COND_E: X86::COND_B;
11463 SDValue LHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i1, Op.getOperand(1));
11464 SDValue RHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i1, Op.getOperand(2));
11465 SDValue CC = DAG.getConstant(X86CC, MVT::i8);
11466 SDValue Test = DAG.getNode(X86ISD::KORTEST, dl, MVT::i32, LHS, RHS);
11467 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8, CC, Test);
11468 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
11471 // SSE/AVX shift intrinsics
11472 case Intrinsic::x86_sse2_psll_w:
11473 case Intrinsic::x86_sse2_psll_d:
11474 case Intrinsic::x86_sse2_psll_q:
11475 case Intrinsic::x86_avx2_psll_w:
11476 case Intrinsic::x86_avx2_psll_d:
11477 case Intrinsic::x86_avx2_psll_q:
11478 case Intrinsic::x86_sse2_psrl_w:
11479 case Intrinsic::x86_sse2_psrl_d:
11480 case Intrinsic::x86_sse2_psrl_q:
11481 case Intrinsic::x86_avx2_psrl_w:
11482 case Intrinsic::x86_avx2_psrl_d:
11483 case Intrinsic::x86_avx2_psrl_q:
11484 case Intrinsic::x86_sse2_psra_w:
11485 case Intrinsic::x86_sse2_psra_d:
11486 case Intrinsic::x86_avx2_psra_w:
11487 case Intrinsic::x86_avx2_psra_d: {
11490 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
11491 case Intrinsic::x86_sse2_psll_w:
11492 case Intrinsic::x86_sse2_psll_d:
11493 case Intrinsic::x86_sse2_psll_q:
11494 case Intrinsic::x86_avx2_psll_w:
11495 case Intrinsic::x86_avx2_psll_d:
11496 case Intrinsic::x86_avx2_psll_q:
11497 Opcode = X86ISD::VSHL;
11499 case Intrinsic::x86_sse2_psrl_w:
11500 case Intrinsic::x86_sse2_psrl_d:
11501 case Intrinsic::x86_sse2_psrl_q:
11502 case Intrinsic::x86_avx2_psrl_w:
11503 case Intrinsic::x86_avx2_psrl_d:
11504 case Intrinsic::x86_avx2_psrl_q:
11505 Opcode = X86ISD::VSRL;
11507 case Intrinsic::x86_sse2_psra_w:
11508 case Intrinsic::x86_sse2_psra_d:
11509 case Intrinsic::x86_avx2_psra_w:
11510 case Intrinsic::x86_avx2_psra_d:
11511 Opcode = X86ISD::VSRA;
11514 return DAG.getNode(Opcode, dl, Op.getValueType(),
11515 Op.getOperand(1), Op.getOperand(2));
11518 // SSE/AVX immediate shift intrinsics
11519 case Intrinsic::x86_sse2_pslli_w:
11520 case Intrinsic::x86_sse2_pslli_d:
11521 case Intrinsic::x86_sse2_pslli_q:
11522 case Intrinsic::x86_avx2_pslli_w:
11523 case Intrinsic::x86_avx2_pslli_d:
11524 case Intrinsic::x86_avx2_pslli_q:
11525 case Intrinsic::x86_sse2_psrli_w:
11526 case Intrinsic::x86_sse2_psrli_d:
11527 case Intrinsic::x86_sse2_psrli_q:
11528 case Intrinsic::x86_avx2_psrli_w:
11529 case Intrinsic::x86_avx2_psrli_d:
11530 case Intrinsic::x86_avx2_psrli_q:
11531 case Intrinsic::x86_sse2_psrai_w:
11532 case Intrinsic::x86_sse2_psrai_d:
11533 case Intrinsic::x86_avx2_psrai_w:
11534 case Intrinsic::x86_avx2_psrai_d: {
11537 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
11538 case Intrinsic::x86_sse2_pslli_w:
11539 case Intrinsic::x86_sse2_pslli_d:
11540 case Intrinsic::x86_sse2_pslli_q:
11541 case Intrinsic::x86_avx2_pslli_w:
11542 case Intrinsic::x86_avx2_pslli_d:
11543 case Intrinsic::x86_avx2_pslli_q:
11544 Opcode = X86ISD::VSHLI;
11546 case Intrinsic::x86_sse2_psrli_w:
11547 case Intrinsic::x86_sse2_psrli_d:
11548 case Intrinsic::x86_sse2_psrli_q:
11549 case Intrinsic::x86_avx2_psrli_w:
11550 case Intrinsic::x86_avx2_psrli_d:
11551 case Intrinsic::x86_avx2_psrli_q:
11552 Opcode = X86ISD::VSRLI;
11554 case Intrinsic::x86_sse2_psrai_w:
11555 case Intrinsic::x86_sse2_psrai_d:
11556 case Intrinsic::x86_avx2_psrai_w:
11557 case Intrinsic::x86_avx2_psrai_d:
11558 Opcode = X86ISD::VSRAI;
11561 return getTargetVShiftNode(Opcode, dl, Op.getValueType(),
11562 Op.getOperand(1), Op.getOperand(2), DAG);
11565 case Intrinsic::x86_sse42_pcmpistria128:
11566 case Intrinsic::x86_sse42_pcmpestria128:
11567 case Intrinsic::x86_sse42_pcmpistric128:
11568 case Intrinsic::x86_sse42_pcmpestric128:
11569 case Intrinsic::x86_sse42_pcmpistrio128:
11570 case Intrinsic::x86_sse42_pcmpestrio128:
11571 case Intrinsic::x86_sse42_pcmpistris128:
11572 case Intrinsic::x86_sse42_pcmpestris128:
11573 case Intrinsic::x86_sse42_pcmpistriz128:
11574 case Intrinsic::x86_sse42_pcmpestriz128: {
11578 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
11579 case Intrinsic::x86_sse42_pcmpistria128:
11580 Opcode = X86ISD::PCMPISTRI;
11581 X86CC = X86::COND_A;
11583 case Intrinsic::x86_sse42_pcmpestria128:
11584 Opcode = X86ISD::PCMPESTRI;
11585 X86CC = X86::COND_A;
11587 case Intrinsic::x86_sse42_pcmpistric128:
11588 Opcode = X86ISD::PCMPISTRI;
11589 X86CC = X86::COND_B;
11591 case Intrinsic::x86_sse42_pcmpestric128:
11592 Opcode = X86ISD::PCMPESTRI;
11593 X86CC = X86::COND_B;
11595 case Intrinsic::x86_sse42_pcmpistrio128:
11596 Opcode = X86ISD::PCMPISTRI;
11597 X86CC = X86::COND_O;
11599 case Intrinsic::x86_sse42_pcmpestrio128:
11600 Opcode = X86ISD::PCMPESTRI;
11601 X86CC = X86::COND_O;
11603 case Intrinsic::x86_sse42_pcmpistris128:
11604 Opcode = X86ISD::PCMPISTRI;
11605 X86CC = X86::COND_S;
11607 case Intrinsic::x86_sse42_pcmpestris128:
11608 Opcode = X86ISD::PCMPESTRI;
11609 X86CC = X86::COND_S;
11611 case Intrinsic::x86_sse42_pcmpistriz128:
11612 Opcode = X86ISD::PCMPISTRI;
11613 X86CC = X86::COND_E;
11615 case Intrinsic::x86_sse42_pcmpestriz128:
11616 Opcode = X86ISD::PCMPESTRI;
11617 X86CC = X86::COND_E;
11620 SmallVector<SDValue, 5> NewOps(Op->op_begin()+1, Op->op_end());
11621 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
11622 SDValue PCMP = DAG.getNode(Opcode, dl, VTs, NewOps.data(), NewOps.size());
11623 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
11624 DAG.getConstant(X86CC, MVT::i8),
11625 SDValue(PCMP.getNode(), 1));
11626 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
11629 case Intrinsic::x86_sse42_pcmpistri128:
11630 case Intrinsic::x86_sse42_pcmpestri128: {
11632 if (IntNo == Intrinsic::x86_sse42_pcmpistri128)
11633 Opcode = X86ISD::PCMPISTRI;
11635 Opcode = X86ISD::PCMPESTRI;
11637 SmallVector<SDValue, 5> NewOps(Op->op_begin()+1, Op->op_end());
11638 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
11639 return DAG.getNode(Opcode, dl, VTs, NewOps.data(), NewOps.size());
11641 case Intrinsic::x86_fma_vfmadd_ps:
11642 case Intrinsic::x86_fma_vfmadd_pd:
11643 case Intrinsic::x86_fma_vfmsub_ps:
11644 case Intrinsic::x86_fma_vfmsub_pd:
11645 case Intrinsic::x86_fma_vfnmadd_ps:
11646 case Intrinsic::x86_fma_vfnmadd_pd:
11647 case Intrinsic::x86_fma_vfnmsub_ps:
11648 case Intrinsic::x86_fma_vfnmsub_pd:
11649 case Intrinsic::x86_fma_vfmaddsub_ps:
11650 case Intrinsic::x86_fma_vfmaddsub_pd:
11651 case Intrinsic::x86_fma_vfmsubadd_ps:
11652 case Intrinsic::x86_fma_vfmsubadd_pd:
11653 case Intrinsic::x86_fma_vfmadd_ps_256:
11654 case Intrinsic::x86_fma_vfmadd_pd_256:
11655 case Intrinsic::x86_fma_vfmsub_ps_256:
11656 case Intrinsic::x86_fma_vfmsub_pd_256:
11657 case Intrinsic::x86_fma_vfnmadd_ps_256:
11658 case Intrinsic::x86_fma_vfnmadd_pd_256:
11659 case Intrinsic::x86_fma_vfnmsub_ps_256:
11660 case Intrinsic::x86_fma_vfnmsub_pd_256:
11661 case Intrinsic::x86_fma_vfmaddsub_ps_256:
11662 case Intrinsic::x86_fma_vfmaddsub_pd_256:
11663 case Intrinsic::x86_fma_vfmsubadd_ps_256:
11664 case Intrinsic::x86_fma_vfmsubadd_pd_256:
11665 case Intrinsic::x86_fma_vfmadd_ps_512:
11666 case Intrinsic::x86_fma_vfmadd_pd_512:
11667 case Intrinsic::x86_fma_vfmsub_ps_512:
11668 case Intrinsic::x86_fma_vfmsub_pd_512:
11669 case Intrinsic::x86_fma_vfnmadd_ps_512:
11670 case Intrinsic::x86_fma_vfnmadd_pd_512:
11671 case Intrinsic::x86_fma_vfnmsub_ps_512:
11672 case Intrinsic::x86_fma_vfnmsub_pd_512:
11673 case Intrinsic::x86_fma_vfmaddsub_ps_512:
11674 case Intrinsic::x86_fma_vfmaddsub_pd_512:
11675 case Intrinsic::x86_fma_vfmsubadd_ps_512:
11676 case Intrinsic::x86_fma_vfmsubadd_pd_512: {
11679 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
11680 case Intrinsic::x86_fma_vfmadd_ps:
11681 case Intrinsic::x86_fma_vfmadd_pd:
11682 case Intrinsic::x86_fma_vfmadd_ps_256:
11683 case Intrinsic::x86_fma_vfmadd_pd_256:
11684 case Intrinsic::x86_fma_vfmadd_ps_512:
11685 case Intrinsic::x86_fma_vfmadd_pd_512:
11686 Opc = X86ISD::FMADD;
11688 case Intrinsic::x86_fma_vfmsub_ps:
11689 case Intrinsic::x86_fma_vfmsub_pd:
11690 case Intrinsic::x86_fma_vfmsub_ps_256:
11691 case Intrinsic::x86_fma_vfmsub_pd_256:
11692 case Intrinsic::x86_fma_vfmsub_ps_512:
11693 case Intrinsic::x86_fma_vfmsub_pd_512:
11694 Opc = X86ISD::FMSUB;
11696 case Intrinsic::x86_fma_vfnmadd_ps:
11697 case Intrinsic::x86_fma_vfnmadd_pd:
11698 case Intrinsic::x86_fma_vfnmadd_ps_256:
11699 case Intrinsic::x86_fma_vfnmadd_pd_256:
11700 case Intrinsic::x86_fma_vfnmadd_ps_512:
11701 case Intrinsic::x86_fma_vfnmadd_pd_512:
11702 Opc = X86ISD::FNMADD;
11704 case Intrinsic::x86_fma_vfnmsub_ps:
11705 case Intrinsic::x86_fma_vfnmsub_pd:
11706 case Intrinsic::x86_fma_vfnmsub_ps_256:
11707 case Intrinsic::x86_fma_vfnmsub_pd_256:
11708 case Intrinsic::x86_fma_vfnmsub_ps_512:
11709 case Intrinsic::x86_fma_vfnmsub_pd_512:
11710 Opc = X86ISD::FNMSUB;
11712 case Intrinsic::x86_fma_vfmaddsub_ps:
11713 case Intrinsic::x86_fma_vfmaddsub_pd:
11714 case Intrinsic::x86_fma_vfmaddsub_ps_256:
11715 case Intrinsic::x86_fma_vfmaddsub_pd_256:
11716 case Intrinsic::x86_fma_vfmaddsub_ps_512:
11717 case Intrinsic::x86_fma_vfmaddsub_pd_512:
11718 Opc = X86ISD::FMADDSUB;
11720 case Intrinsic::x86_fma_vfmsubadd_ps:
11721 case Intrinsic::x86_fma_vfmsubadd_pd:
11722 case Intrinsic::x86_fma_vfmsubadd_ps_256:
11723 case Intrinsic::x86_fma_vfmsubadd_pd_256:
11724 case Intrinsic::x86_fma_vfmsubadd_ps_512:
11725 case Intrinsic::x86_fma_vfmsubadd_pd_512:
11726 Opc = X86ISD::FMSUBADD;
11730 return DAG.getNode(Opc, dl, Op.getValueType(), Op.getOperand(1),
11731 Op.getOperand(2), Op.getOperand(3));
11736 static SDValue getGatherNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
11737 SDValue Base, SDValue Index,
11738 SDValue ScaleOp, SDValue Chain,
11739 const X86Subtarget * Subtarget) {
11741 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
11742 assert(C && "Invalid scale type");
11743 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), MVT::i8);
11744 SDValue Src = getZeroVector(Op.getValueType(), Subtarget, DAG, dl);
11745 EVT MaskVT = MVT::getVectorVT(MVT::i1,
11746 Index.getValueType().getVectorNumElements());
11747 SDValue MaskInReg = DAG.getConstant(~0, MaskVT);
11748 SDVTList VTs = DAG.getVTList(Op.getValueType(), MaskVT, MVT::Other);
11749 SDValue Disp = DAG.getTargetConstant(0, MVT::i32);
11750 SDValue Segment = DAG.getRegister(0, MVT::i32);
11751 SDValue Ops[] = {Src, MaskInReg, Base, Scale, Index, Disp, Segment, Chain};
11752 SDNode *Res = DAG.getMachineNode(Opc, dl, VTs, Ops);
11753 SDValue RetOps[] = { SDValue(Res, 0), SDValue(Res, 2) };
11754 return DAG.getMergeValues(RetOps, array_lengthof(RetOps), dl);
11757 static SDValue getMGatherNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
11758 SDValue Src, SDValue Mask, SDValue Base,
11759 SDValue Index, SDValue ScaleOp, SDValue Chain,
11760 const X86Subtarget * Subtarget) {
11762 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
11763 assert(C && "Invalid scale type");
11764 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), MVT::i8);
11765 EVT MaskVT = MVT::getVectorVT(MVT::i1,
11766 Index.getValueType().getVectorNumElements());
11767 SDValue MaskInReg = DAG.getNode(ISD::BITCAST, dl, MaskVT, Mask);
11768 SDVTList VTs = DAG.getVTList(Op.getValueType(), MaskVT, MVT::Other);
11769 SDValue Disp = DAG.getTargetConstant(0, MVT::i32);
11770 SDValue Segment = DAG.getRegister(0, MVT::i32);
11771 if (Src.getOpcode() == ISD::UNDEF)
11772 Src = getZeroVector(Op.getValueType(), Subtarget, DAG, dl);
11773 SDValue Ops[] = {Src, MaskInReg, Base, Scale, Index, Disp, Segment, Chain};
11774 SDNode *Res = DAG.getMachineNode(Opc, dl, VTs, Ops);
11775 SDValue RetOps[] = { SDValue(Res, 0), SDValue(Res, 2) };
11776 return DAG.getMergeValues(RetOps, array_lengthof(RetOps), dl);
11779 static SDValue getScatterNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
11780 SDValue Src, SDValue Base, SDValue Index,
11781 SDValue ScaleOp, SDValue Chain) {
11783 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
11784 assert(C && "Invalid scale type");
11785 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), MVT::i8);
11786 SDValue Disp = DAG.getTargetConstant(0, MVT::i32);
11787 SDValue Segment = DAG.getRegister(0, MVT::i32);
11788 EVT MaskVT = MVT::getVectorVT(MVT::i1,
11789 Index.getValueType().getVectorNumElements());
11790 SDValue MaskInReg = DAG.getConstant(~0, MaskVT);
11791 SDVTList VTs = DAG.getVTList(MaskVT, MVT::Other);
11792 SDValue Ops[] = {Base, Scale, Index, Disp, Segment, MaskInReg, Src, Chain};
11793 SDNode *Res = DAG.getMachineNode(Opc, dl, VTs, Ops);
11794 return SDValue(Res, 1);
11797 static SDValue getMScatterNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
11798 SDValue Src, SDValue Mask, SDValue Base,
11799 SDValue Index, SDValue ScaleOp, SDValue Chain) {
11801 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
11802 assert(C && "Invalid scale type");
11803 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), MVT::i8);
11804 SDValue Disp = DAG.getTargetConstant(0, MVT::i32);
11805 SDValue Segment = DAG.getRegister(0, MVT::i32);
11806 EVT MaskVT = MVT::getVectorVT(MVT::i1,
11807 Index.getValueType().getVectorNumElements());
11808 SDValue MaskInReg = DAG.getNode(ISD::BITCAST, dl, MaskVT, Mask);
11809 SDVTList VTs = DAG.getVTList(MaskVT, MVT::Other);
11810 SDValue Ops[] = {Base, Scale, Index, Disp, Segment, MaskInReg, Src, Chain};
11811 SDNode *Res = DAG.getMachineNode(Opc, dl, VTs, Ops);
11812 return SDValue(Res, 1);
11815 static SDValue LowerINTRINSIC_W_CHAIN(SDValue Op, const X86Subtarget *Subtarget,
11816 SelectionDAG &DAG) {
11818 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
11820 default: return SDValue(); // Don't custom lower most intrinsics.
11822 // RDRAND/RDSEED intrinsics.
11823 case Intrinsic::x86_rdrand_16:
11824 case Intrinsic::x86_rdrand_32:
11825 case Intrinsic::x86_rdrand_64:
11826 case Intrinsic::x86_rdseed_16:
11827 case Intrinsic::x86_rdseed_32:
11828 case Intrinsic::x86_rdseed_64: {
11829 unsigned Opcode = (IntNo == Intrinsic::x86_rdseed_16 ||
11830 IntNo == Intrinsic::x86_rdseed_32 ||
11831 IntNo == Intrinsic::x86_rdseed_64) ? X86ISD::RDSEED :
11833 // Emit the node with the right value type.
11834 SDVTList VTs = DAG.getVTList(Op->getValueType(0), MVT::Glue, MVT::Other);
11835 SDValue Result = DAG.getNode(Opcode, dl, VTs, Op.getOperand(0));
11837 // If the value returned by RDRAND/RDSEED was valid (CF=1), return 1.
11838 // Otherwise return the value from Rand, which is always 0, casted to i32.
11839 SDValue Ops[] = { DAG.getZExtOrTrunc(Result, dl, Op->getValueType(1)),
11840 DAG.getConstant(1, Op->getValueType(1)),
11841 DAG.getConstant(X86::COND_B, MVT::i32),
11842 SDValue(Result.getNode(), 1) };
11843 SDValue isValid = DAG.getNode(X86ISD::CMOV, dl,
11844 DAG.getVTList(Op->getValueType(1), MVT::Glue),
11845 Ops, array_lengthof(Ops));
11847 // Return { result, isValid, chain }.
11848 return DAG.getNode(ISD::MERGE_VALUES, dl, Op->getVTList(), Result, isValid,
11849 SDValue(Result.getNode(), 2));
11851 //int_gather(index, base, scale);
11852 case Intrinsic::x86_avx512_gather_qpd_512:
11853 case Intrinsic::x86_avx512_gather_qps_512:
11854 case Intrinsic::x86_avx512_gather_dpd_512:
11855 case Intrinsic::x86_avx512_gather_qpi_512:
11856 case Intrinsic::x86_avx512_gather_qpq_512:
11857 case Intrinsic::x86_avx512_gather_dpq_512:
11858 case Intrinsic::x86_avx512_gather_dps_512:
11859 case Intrinsic::x86_avx512_gather_dpi_512: {
11862 default: llvm_unreachable("Unexpected intrinsic!");
11863 case Intrinsic::x86_avx512_gather_qps_512: Opc = X86::VGATHERQPSZrm; break;
11864 case Intrinsic::x86_avx512_gather_qpd_512: Opc = X86::VGATHERQPDZrm; break;
11865 case Intrinsic::x86_avx512_gather_dpd_512: Opc = X86::VGATHERDPDZrm; break;
11866 case Intrinsic::x86_avx512_gather_dps_512: Opc = X86::VGATHERDPSZrm; break;
11867 case Intrinsic::x86_avx512_gather_qpi_512: Opc = X86::VPGATHERQDZrm; break;
11868 case Intrinsic::x86_avx512_gather_qpq_512: Opc = X86::VPGATHERQQZrm; break;
11869 case Intrinsic::x86_avx512_gather_dpi_512: Opc = X86::VPGATHERDDZrm; break;
11870 case Intrinsic::x86_avx512_gather_dpq_512: Opc = X86::VPGATHERDQZrm; break;
11872 SDValue Chain = Op.getOperand(0);
11873 SDValue Index = Op.getOperand(2);
11874 SDValue Base = Op.getOperand(3);
11875 SDValue Scale = Op.getOperand(4);
11876 return getGatherNode(Opc, Op, DAG, Base, Index, Scale, Chain, Subtarget);
11878 //int_gather_mask(v1, mask, index, base, scale);
11879 case Intrinsic::x86_avx512_gather_qps_mask_512:
11880 case Intrinsic::x86_avx512_gather_qpd_mask_512:
11881 case Intrinsic::x86_avx512_gather_dpd_mask_512:
11882 case Intrinsic::x86_avx512_gather_dps_mask_512:
11883 case Intrinsic::x86_avx512_gather_qpi_mask_512:
11884 case Intrinsic::x86_avx512_gather_qpq_mask_512:
11885 case Intrinsic::x86_avx512_gather_dpi_mask_512:
11886 case Intrinsic::x86_avx512_gather_dpq_mask_512: {
11889 default: llvm_unreachable("Unexpected intrinsic!");
11890 case Intrinsic::x86_avx512_gather_qps_mask_512:
11891 Opc = X86::VGATHERQPSZrm; break;
11892 case Intrinsic::x86_avx512_gather_qpd_mask_512:
11893 Opc = X86::VGATHERQPDZrm; break;
11894 case Intrinsic::x86_avx512_gather_dpd_mask_512:
11895 Opc = X86::VGATHERDPDZrm; break;
11896 case Intrinsic::x86_avx512_gather_dps_mask_512:
11897 Opc = X86::VGATHERDPSZrm; break;
11898 case Intrinsic::x86_avx512_gather_qpi_mask_512:
11899 Opc = X86::VPGATHERQDZrm; break;
11900 case Intrinsic::x86_avx512_gather_qpq_mask_512:
11901 Opc = X86::VPGATHERQQZrm; break;
11902 case Intrinsic::x86_avx512_gather_dpi_mask_512:
11903 Opc = X86::VPGATHERDDZrm; break;
11904 case Intrinsic::x86_avx512_gather_dpq_mask_512:
11905 Opc = X86::VPGATHERDQZrm; break;
11907 SDValue Chain = Op.getOperand(0);
11908 SDValue Src = Op.getOperand(2);
11909 SDValue Mask = Op.getOperand(3);
11910 SDValue Index = Op.getOperand(4);
11911 SDValue Base = Op.getOperand(5);
11912 SDValue Scale = Op.getOperand(6);
11913 return getMGatherNode(Opc, Op, DAG, Src, Mask, Base, Index, Scale, Chain,
11916 //int_scatter(base, index, v1, scale);
11917 case Intrinsic::x86_avx512_scatter_qpd_512:
11918 case Intrinsic::x86_avx512_scatter_qps_512:
11919 case Intrinsic::x86_avx512_scatter_dpd_512:
11920 case Intrinsic::x86_avx512_scatter_qpi_512:
11921 case Intrinsic::x86_avx512_scatter_qpq_512:
11922 case Intrinsic::x86_avx512_scatter_dpq_512:
11923 case Intrinsic::x86_avx512_scatter_dps_512:
11924 case Intrinsic::x86_avx512_scatter_dpi_512: {
11927 default: llvm_unreachable("Unexpected intrinsic!");
11928 case Intrinsic::x86_avx512_scatter_qpd_512:
11929 Opc = X86::VSCATTERQPDZmr; break;
11930 case Intrinsic::x86_avx512_scatter_qps_512:
11931 Opc = X86::VSCATTERQPSZmr; break;
11932 case Intrinsic::x86_avx512_scatter_dpd_512:
11933 Opc = X86::VSCATTERDPDZmr; break;
11934 case Intrinsic::x86_avx512_scatter_dps_512:
11935 Opc = X86::VSCATTERDPSZmr; break;
11936 case Intrinsic::x86_avx512_scatter_qpi_512:
11937 Opc = X86::VPSCATTERQDZmr; break;
11938 case Intrinsic::x86_avx512_scatter_qpq_512:
11939 Opc = X86::VPSCATTERQQZmr; break;
11940 case Intrinsic::x86_avx512_scatter_dpq_512:
11941 Opc = X86::VPSCATTERDQZmr; break;
11942 case Intrinsic::x86_avx512_scatter_dpi_512:
11943 Opc = X86::VPSCATTERDDZmr; break;
11945 SDValue Chain = Op.getOperand(0);
11946 SDValue Base = Op.getOperand(2);
11947 SDValue Index = Op.getOperand(3);
11948 SDValue Src = Op.getOperand(4);
11949 SDValue Scale = Op.getOperand(5);
11950 return getScatterNode(Opc, Op, DAG, Src, Base, Index, Scale, Chain);
11952 //int_scatter_mask(base, mask, index, v1, scale);
11953 case Intrinsic::x86_avx512_scatter_qps_mask_512:
11954 case Intrinsic::x86_avx512_scatter_qpd_mask_512:
11955 case Intrinsic::x86_avx512_scatter_dpd_mask_512:
11956 case Intrinsic::x86_avx512_scatter_dps_mask_512:
11957 case Intrinsic::x86_avx512_scatter_qpi_mask_512:
11958 case Intrinsic::x86_avx512_scatter_qpq_mask_512:
11959 case Intrinsic::x86_avx512_scatter_dpi_mask_512:
11960 case Intrinsic::x86_avx512_scatter_dpq_mask_512: {
11963 default: llvm_unreachable("Unexpected intrinsic!");
11964 case Intrinsic::x86_avx512_scatter_qpd_mask_512:
11965 Opc = X86::VSCATTERQPDZmr; break;
11966 case Intrinsic::x86_avx512_scatter_qps_mask_512:
11967 Opc = X86::VSCATTERQPSZmr; break;
11968 case Intrinsic::x86_avx512_scatter_dpd_mask_512:
11969 Opc = X86::VSCATTERDPDZmr; break;
11970 case Intrinsic::x86_avx512_scatter_dps_mask_512:
11971 Opc = X86::VSCATTERDPSZmr; break;
11972 case Intrinsic::x86_avx512_scatter_qpi_mask_512:
11973 Opc = X86::VPSCATTERQDZmr; break;
11974 case Intrinsic::x86_avx512_scatter_qpq_mask_512:
11975 Opc = X86::VPSCATTERQQZmr; break;
11976 case Intrinsic::x86_avx512_scatter_dpq_mask_512:
11977 Opc = X86::VPSCATTERDQZmr; break;
11978 case Intrinsic::x86_avx512_scatter_dpi_mask_512:
11979 Opc = X86::VPSCATTERDDZmr; break;
11981 SDValue Chain = Op.getOperand(0);
11982 SDValue Base = Op.getOperand(2);
11983 SDValue Mask = Op.getOperand(3);
11984 SDValue Index = Op.getOperand(4);
11985 SDValue Src = Op.getOperand(5);
11986 SDValue Scale = Op.getOperand(6);
11987 return getMScatterNode(Opc, Op, DAG, Src, Mask, Base, Index, Scale, Chain);
11989 // XTEST intrinsics.
11990 case Intrinsic::x86_xtest: {
11991 SDVTList VTs = DAG.getVTList(Op->getValueType(0), MVT::Other);
11992 SDValue InTrans = DAG.getNode(X86ISD::XTEST, dl, VTs, Op.getOperand(0));
11993 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
11994 DAG.getConstant(X86::COND_NE, MVT::i8),
11996 SDValue Ret = DAG.getNode(ISD::ZERO_EXTEND, dl, Op->getValueType(0), SetCC);
11997 return DAG.getNode(ISD::MERGE_VALUES, dl, Op->getVTList(),
11998 Ret, SDValue(InTrans.getNode(), 1));
12003 SDValue X86TargetLowering::LowerRETURNADDR(SDValue Op,
12004 SelectionDAG &DAG) const {
12005 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
12006 MFI->setReturnAddressIsTaken(true);
12008 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
12010 EVT PtrVT = getPointerTy();
12013 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
12014 const X86RegisterInfo *RegInfo =
12015 static_cast<const X86RegisterInfo*>(getTargetMachine().getRegisterInfo());
12016 SDValue Offset = DAG.getConstant(RegInfo->getSlotSize(), PtrVT);
12017 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
12018 DAG.getNode(ISD::ADD, dl, PtrVT,
12019 FrameAddr, Offset),
12020 MachinePointerInfo(), false, false, false, 0);
12023 // Just load the return address.
12024 SDValue RetAddrFI = getReturnAddressFrameIndex(DAG);
12025 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
12026 RetAddrFI, MachinePointerInfo(), false, false, false, 0);
12029 SDValue X86TargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {
12030 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
12031 MFI->setFrameAddressIsTaken(true);
12033 EVT VT = Op.getValueType();
12034 SDLoc dl(Op); // FIXME probably not meaningful
12035 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
12036 const X86RegisterInfo *RegInfo =
12037 static_cast<const X86RegisterInfo*>(getTargetMachine().getRegisterInfo());
12038 unsigned FrameReg = RegInfo->getFrameRegister(DAG.getMachineFunction());
12039 assert(((FrameReg == X86::RBP && VT == MVT::i64) ||
12040 (FrameReg == X86::EBP && VT == MVT::i32)) &&
12041 "Invalid Frame Register!");
12042 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT);
12044 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr,
12045 MachinePointerInfo(),
12046 false, false, false, 0);
12050 SDValue X86TargetLowering::LowerFRAME_TO_ARGS_OFFSET(SDValue Op,
12051 SelectionDAG &DAG) const {
12052 const X86RegisterInfo *RegInfo =
12053 static_cast<const X86RegisterInfo*>(getTargetMachine().getRegisterInfo());
12054 return DAG.getIntPtrConstant(2 * RegInfo->getSlotSize());
12057 SDValue X86TargetLowering::LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const {
12058 SDValue Chain = Op.getOperand(0);
12059 SDValue Offset = Op.getOperand(1);
12060 SDValue Handler = Op.getOperand(2);
12063 EVT PtrVT = getPointerTy();
12064 const X86RegisterInfo *RegInfo =
12065 static_cast<const X86RegisterInfo*>(getTargetMachine().getRegisterInfo());
12066 unsigned FrameReg = RegInfo->getFrameRegister(DAG.getMachineFunction());
12067 assert(((FrameReg == X86::RBP && PtrVT == MVT::i64) ||
12068 (FrameReg == X86::EBP && PtrVT == MVT::i32)) &&
12069 "Invalid Frame Register!");
12070 SDValue Frame = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, PtrVT);
12071 unsigned StoreAddrReg = (PtrVT == MVT::i64) ? X86::RCX : X86::ECX;
12073 SDValue StoreAddr = DAG.getNode(ISD::ADD, dl, PtrVT, Frame,
12074 DAG.getIntPtrConstant(RegInfo->getSlotSize()));
12075 StoreAddr = DAG.getNode(ISD::ADD, dl, PtrVT, StoreAddr, Offset);
12076 Chain = DAG.getStore(Chain, dl, Handler, StoreAddr, MachinePointerInfo(),
12078 Chain = DAG.getCopyToReg(Chain, dl, StoreAddrReg, StoreAddr);
12080 return DAG.getNode(X86ISD::EH_RETURN, dl, MVT::Other, Chain,
12081 DAG.getRegister(StoreAddrReg, PtrVT));
12084 SDValue X86TargetLowering::lowerEH_SJLJ_SETJMP(SDValue Op,
12085 SelectionDAG &DAG) const {
12087 return DAG.getNode(X86ISD::EH_SJLJ_SETJMP, DL,
12088 DAG.getVTList(MVT::i32, MVT::Other),
12089 Op.getOperand(0), Op.getOperand(1));
12092 SDValue X86TargetLowering::lowerEH_SJLJ_LONGJMP(SDValue Op,
12093 SelectionDAG &DAG) const {
12095 return DAG.getNode(X86ISD::EH_SJLJ_LONGJMP, DL, MVT::Other,
12096 Op.getOperand(0), Op.getOperand(1));
12099 static SDValue LowerADJUST_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) {
12100 return Op.getOperand(0);
12103 SDValue X86TargetLowering::LowerINIT_TRAMPOLINE(SDValue Op,
12104 SelectionDAG &DAG) const {
12105 SDValue Root = Op.getOperand(0);
12106 SDValue Trmp = Op.getOperand(1); // trampoline
12107 SDValue FPtr = Op.getOperand(2); // nested function
12108 SDValue Nest = Op.getOperand(3); // 'nest' parameter value
12111 const Value *TrmpAddr = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
12112 const TargetRegisterInfo* TRI = getTargetMachine().getRegisterInfo();
12114 if (Subtarget->is64Bit()) {
12115 SDValue OutChains[6];
12117 // Large code-model.
12118 const unsigned char JMP64r = 0xFF; // 64-bit jmp through register opcode.
12119 const unsigned char MOV64ri = 0xB8; // X86::MOV64ri opcode.
12121 const unsigned char N86R10 = TRI->getEncodingValue(X86::R10) & 0x7;
12122 const unsigned char N86R11 = TRI->getEncodingValue(X86::R11) & 0x7;
12124 const unsigned char REX_WB = 0x40 | 0x08 | 0x01; // REX prefix
12126 // Load the pointer to the nested function into R11.
12127 unsigned OpCode = ((MOV64ri | N86R11) << 8) | REX_WB; // movabsq r11
12128 SDValue Addr = Trmp;
12129 OutChains[0] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
12130 Addr, MachinePointerInfo(TrmpAddr),
12133 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
12134 DAG.getConstant(2, MVT::i64));
12135 OutChains[1] = DAG.getStore(Root, dl, FPtr, Addr,
12136 MachinePointerInfo(TrmpAddr, 2),
12139 // Load the 'nest' parameter value into R10.
12140 // R10 is specified in X86CallingConv.td
12141 OpCode = ((MOV64ri | N86R10) << 8) | REX_WB; // movabsq r10
12142 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
12143 DAG.getConstant(10, MVT::i64));
12144 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
12145 Addr, MachinePointerInfo(TrmpAddr, 10),
12148 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
12149 DAG.getConstant(12, MVT::i64));
12150 OutChains[3] = DAG.getStore(Root, dl, Nest, Addr,
12151 MachinePointerInfo(TrmpAddr, 12),
12154 // Jump to the nested function.
12155 OpCode = (JMP64r << 8) | REX_WB; // jmpq *...
12156 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
12157 DAG.getConstant(20, MVT::i64));
12158 OutChains[4] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
12159 Addr, MachinePointerInfo(TrmpAddr, 20),
12162 unsigned char ModRM = N86R11 | (4 << 3) | (3 << 6); // ...r11
12163 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
12164 DAG.getConstant(22, MVT::i64));
12165 OutChains[5] = DAG.getStore(Root, dl, DAG.getConstant(ModRM, MVT::i8), Addr,
12166 MachinePointerInfo(TrmpAddr, 22),
12169 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains, 6);
12171 const Function *Func =
12172 cast<Function>(cast<SrcValueSDNode>(Op.getOperand(5))->getValue());
12173 CallingConv::ID CC = Func->getCallingConv();
12178 llvm_unreachable("Unsupported calling convention");
12179 case CallingConv::C:
12180 case CallingConv::X86_StdCall: {
12181 // Pass 'nest' parameter in ECX.
12182 // Must be kept in sync with X86CallingConv.td
12183 NestReg = X86::ECX;
12185 // Check that ECX wasn't needed by an 'inreg' parameter.
12186 FunctionType *FTy = Func->getFunctionType();
12187 const AttributeSet &Attrs = Func->getAttributes();
12189 if (!Attrs.isEmpty() && !Func->isVarArg()) {
12190 unsigned InRegCount = 0;
12193 for (FunctionType::param_iterator I = FTy->param_begin(),
12194 E = FTy->param_end(); I != E; ++I, ++Idx)
12195 if (Attrs.hasAttribute(Idx, Attribute::InReg))
12196 // FIXME: should only count parameters that are lowered to integers.
12197 InRegCount += (TD->getTypeSizeInBits(*I) + 31) / 32;
12199 if (InRegCount > 2) {
12200 report_fatal_error("Nest register in use - reduce number of inreg"
12206 case CallingConv::X86_FastCall:
12207 case CallingConv::X86_ThisCall:
12208 case CallingConv::Fast:
12209 // Pass 'nest' parameter in EAX.
12210 // Must be kept in sync with X86CallingConv.td
12211 NestReg = X86::EAX;
12215 SDValue OutChains[4];
12216 SDValue Addr, Disp;
12218 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
12219 DAG.getConstant(10, MVT::i32));
12220 Disp = DAG.getNode(ISD::SUB, dl, MVT::i32, FPtr, Addr);
12222 // This is storing the opcode for MOV32ri.
12223 const unsigned char MOV32ri = 0xB8; // X86::MOV32ri's opcode byte.
12224 const unsigned char N86Reg = TRI->getEncodingValue(NestReg) & 0x7;
12225 OutChains[0] = DAG.getStore(Root, dl,
12226 DAG.getConstant(MOV32ri|N86Reg, MVT::i8),
12227 Trmp, MachinePointerInfo(TrmpAddr),
12230 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
12231 DAG.getConstant(1, MVT::i32));
12232 OutChains[1] = DAG.getStore(Root, dl, Nest, Addr,
12233 MachinePointerInfo(TrmpAddr, 1),
12236 const unsigned char JMP = 0xE9; // jmp <32bit dst> opcode.
12237 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
12238 DAG.getConstant(5, MVT::i32));
12239 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(JMP, MVT::i8), Addr,
12240 MachinePointerInfo(TrmpAddr, 5),
12243 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
12244 DAG.getConstant(6, MVT::i32));
12245 OutChains[3] = DAG.getStore(Root, dl, Disp, Addr,
12246 MachinePointerInfo(TrmpAddr, 6),
12249 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains, 4);
12253 SDValue X86TargetLowering::LowerFLT_ROUNDS_(SDValue Op,
12254 SelectionDAG &DAG) const {
12256 The rounding mode is in bits 11:10 of FPSR, and has the following
12258 00 Round to nearest
12263 FLT_ROUNDS, on the other hand, expects the following:
12270 To perform the conversion, we do:
12271 (((((FPSR & 0x800) >> 11) | ((FPSR & 0x400) >> 9)) + 1) & 3)
12274 MachineFunction &MF = DAG.getMachineFunction();
12275 const TargetMachine &TM = MF.getTarget();
12276 const TargetFrameLowering &TFI = *TM.getFrameLowering();
12277 unsigned StackAlignment = TFI.getStackAlignment();
12278 EVT VT = Op.getValueType();
12281 // Save FP Control Word to stack slot
12282 int SSFI = MF.getFrameInfo()->CreateStackObject(2, StackAlignment, false);
12283 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
12285 MachineMemOperand *MMO =
12286 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
12287 MachineMemOperand::MOStore, 2, 2);
12289 SDValue Ops[] = { DAG.getEntryNode(), StackSlot };
12290 SDValue Chain = DAG.getMemIntrinsicNode(X86ISD::FNSTCW16m, DL,
12291 DAG.getVTList(MVT::Other),
12292 Ops, array_lengthof(Ops), MVT::i16,
12295 // Load FP Control Word from stack slot
12296 SDValue CWD = DAG.getLoad(MVT::i16, DL, Chain, StackSlot,
12297 MachinePointerInfo(), false, false, false, 0);
12299 // Transform as necessary
12301 DAG.getNode(ISD::SRL, DL, MVT::i16,
12302 DAG.getNode(ISD::AND, DL, MVT::i16,
12303 CWD, DAG.getConstant(0x800, MVT::i16)),
12304 DAG.getConstant(11, MVT::i8));
12306 DAG.getNode(ISD::SRL, DL, MVT::i16,
12307 DAG.getNode(ISD::AND, DL, MVT::i16,
12308 CWD, DAG.getConstant(0x400, MVT::i16)),
12309 DAG.getConstant(9, MVT::i8));
12312 DAG.getNode(ISD::AND, DL, MVT::i16,
12313 DAG.getNode(ISD::ADD, DL, MVT::i16,
12314 DAG.getNode(ISD::OR, DL, MVT::i16, CWD1, CWD2),
12315 DAG.getConstant(1, MVT::i16)),
12316 DAG.getConstant(3, MVT::i16));
12318 return DAG.getNode((VT.getSizeInBits() < 16 ?
12319 ISD::TRUNCATE : ISD::ZERO_EXTEND), DL, VT, RetVal);
12322 static SDValue LowerCTLZ(SDValue Op, SelectionDAG &DAG) {
12323 EVT VT = Op.getValueType();
12325 unsigned NumBits = VT.getSizeInBits();
12328 Op = Op.getOperand(0);
12329 if (VT == MVT::i8) {
12330 // Zero extend to i32 since there is not an i8 bsr.
12332 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
12335 // Issue a bsr (scan bits in reverse) which also sets EFLAGS.
12336 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
12337 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
12339 // If src is zero (i.e. bsr sets ZF), returns NumBits.
12342 DAG.getConstant(NumBits+NumBits-1, OpVT),
12343 DAG.getConstant(X86::COND_E, MVT::i8),
12346 Op = DAG.getNode(X86ISD::CMOV, dl, OpVT, Ops, array_lengthof(Ops));
12348 // Finally xor with NumBits-1.
12349 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT));
12352 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
12356 static SDValue LowerCTLZ_ZERO_UNDEF(SDValue Op, SelectionDAG &DAG) {
12357 EVT VT = Op.getValueType();
12359 unsigned NumBits = VT.getSizeInBits();
12362 Op = Op.getOperand(0);
12363 if (VT == MVT::i8) {
12364 // Zero extend to i32 since there is not an i8 bsr.
12366 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
12369 // Issue a bsr (scan bits in reverse).
12370 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
12371 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
12373 // And xor with NumBits-1.
12374 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT));
12377 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
12381 static SDValue LowerCTTZ(SDValue Op, SelectionDAG &DAG) {
12382 EVT VT = Op.getValueType();
12383 unsigned NumBits = VT.getSizeInBits();
12385 Op = Op.getOperand(0);
12387 // Issue a bsf (scan bits forward) which also sets EFLAGS.
12388 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
12389 Op = DAG.getNode(X86ISD::BSF, dl, VTs, Op);
12391 // If src is zero (i.e. bsf sets ZF), returns NumBits.
12394 DAG.getConstant(NumBits, VT),
12395 DAG.getConstant(X86::COND_E, MVT::i8),
12398 return DAG.getNode(X86ISD::CMOV, dl, VT, Ops, array_lengthof(Ops));
12401 // Lower256IntArith - Break a 256-bit integer operation into two new 128-bit
12402 // ones, and then concatenate the result back.
12403 static SDValue Lower256IntArith(SDValue Op, SelectionDAG &DAG) {
12404 EVT VT = Op.getValueType();
12406 assert(VT.is256BitVector() && VT.isInteger() &&
12407 "Unsupported value type for operation");
12409 unsigned NumElems = VT.getVectorNumElements();
12412 // Extract the LHS vectors
12413 SDValue LHS = Op.getOperand(0);
12414 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
12415 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
12417 // Extract the RHS vectors
12418 SDValue RHS = Op.getOperand(1);
12419 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, dl);
12420 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, dl);
12422 MVT EltVT = VT.getVectorElementType().getSimpleVT();
12423 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
12425 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
12426 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1),
12427 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2));
12430 static SDValue LowerADD(SDValue Op, SelectionDAG &DAG) {
12431 assert(Op.getValueType().is256BitVector() &&
12432 Op.getValueType().isInteger() &&
12433 "Only handle AVX 256-bit vector integer operation");
12434 return Lower256IntArith(Op, DAG);
12437 static SDValue LowerSUB(SDValue Op, SelectionDAG &DAG) {
12438 assert(Op.getValueType().is256BitVector() &&
12439 Op.getValueType().isInteger() &&
12440 "Only handle AVX 256-bit vector integer operation");
12441 return Lower256IntArith(Op, DAG);
12444 static SDValue LowerMUL(SDValue Op, const X86Subtarget *Subtarget,
12445 SelectionDAG &DAG) {
12447 EVT VT = Op.getValueType();
12449 // Decompose 256-bit ops into smaller 128-bit ops.
12450 if (VT.is256BitVector() && !Subtarget->hasInt256())
12451 return Lower256IntArith(Op, DAG);
12453 SDValue A = Op.getOperand(0);
12454 SDValue B = Op.getOperand(1);
12456 // Lower v4i32 mul as 2x shuffle, 2x pmuludq, 2x shuffle.
12457 if (VT == MVT::v4i32) {
12458 assert(Subtarget->hasSSE2() && !Subtarget->hasSSE41() &&
12459 "Should not custom lower when pmuldq is available!");
12461 // Extract the odd parts.
12462 static const int UnpackMask[] = { 1, -1, 3, -1 };
12463 SDValue Aodds = DAG.getVectorShuffle(VT, dl, A, A, UnpackMask);
12464 SDValue Bodds = DAG.getVectorShuffle(VT, dl, B, B, UnpackMask);
12466 // Multiply the even parts.
12467 SDValue Evens = DAG.getNode(X86ISD::PMULUDQ, dl, MVT::v2i64, A, B);
12468 // Now multiply odd parts.
12469 SDValue Odds = DAG.getNode(X86ISD::PMULUDQ, dl, MVT::v2i64, Aodds, Bodds);
12471 Evens = DAG.getNode(ISD::BITCAST, dl, VT, Evens);
12472 Odds = DAG.getNode(ISD::BITCAST, dl, VT, Odds);
12474 // Merge the two vectors back together with a shuffle. This expands into 2
12476 static const int ShufMask[] = { 0, 4, 2, 6 };
12477 return DAG.getVectorShuffle(VT, dl, Evens, Odds, ShufMask);
12480 assert((VT == MVT::v2i64 || VT == MVT::v4i64 || VT == MVT::v8i64) &&
12481 "Only know how to lower V2I64/V4I64/V8I64 multiply");
12483 // Ahi = psrlqi(a, 32);
12484 // Bhi = psrlqi(b, 32);
12486 // AloBlo = pmuludq(a, b);
12487 // AloBhi = pmuludq(a, Bhi);
12488 // AhiBlo = pmuludq(Ahi, b);
12490 // AloBhi = psllqi(AloBhi, 32);
12491 // AhiBlo = psllqi(AhiBlo, 32);
12492 // return AloBlo + AloBhi + AhiBlo;
12494 SDValue Ahi = getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, A, 32, DAG);
12495 SDValue Bhi = getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, B, 32, DAG);
12497 // Bit cast to 32-bit vectors for MULUDQ
12498 EVT MulVT = (VT == MVT::v2i64) ? MVT::v4i32 :
12499 (VT == MVT::v4i64) ? MVT::v8i32 : MVT::v16i32;
12500 A = DAG.getNode(ISD::BITCAST, dl, MulVT, A);
12501 B = DAG.getNode(ISD::BITCAST, dl, MulVT, B);
12502 Ahi = DAG.getNode(ISD::BITCAST, dl, MulVT, Ahi);
12503 Bhi = DAG.getNode(ISD::BITCAST, dl, MulVT, Bhi);
12505 SDValue AloBlo = DAG.getNode(X86ISD::PMULUDQ, dl, VT, A, B);
12506 SDValue AloBhi = DAG.getNode(X86ISD::PMULUDQ, dl, VT, A, Bhi);
12507 SDValue AhiBlo = DAG.getNode(X86ISD::PMULUDQ, dl, VT, Ahi, B);
12509 AloBhi = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, AloBhi, 32, DAG);
12510 AhiBlo = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, AhiBlo, 32, DAG);
12512 SDValue Res = DAG.getNode(ISD::ADD, dl, VT, AloBlo, AloBhi);
12513 return DAG.getNode(ISD::ADD, dl, VT, Res, AhiBlo);
12516 static SDValue LowerSDIV(SDValue Op, SelectionDAG &DAG) {
12517 EVT VT = Op.getValueType();
12518 EVT EltTy = VT.getVectorElementType();
12519 unsigned NumElts = VT.getVectorNumElements();
12520 SDValue N0 = Op.getOperand(0);
12523 // Lower sdiv X, pow2-const.
12524 BuildVectorSDNode *C = dyn_cast<BuildVectorSDNode>(Op.getOperand(1));
12528 APInt SplatValue, SplatUndef;
12529 unsigned SplatBitSize;
12531 if (!C->isConstantSplat(SplatValue, SplatUndef, SplatBitSize,
12533 EltTy.getSizeInBits() < SplatBitSize)
12536 if ((SplatValue != 0) &&
12537 (SplatValue.isPowerOf2() || (-SplatValue).isPowerOf2())) {
12538 unsigned Lg2 = SplatValue.countTrailingZeros();
12539 // Splat the sign bit.
12540 SmallVector<SDValue, 16> Sz(NumElts,
12541 DAG.getConstant(EltTy.getSizeInBits() - 1,
12543 SDValue SGN = DAG.getNode(ISD::SRA, dl, VT, N0,
12544 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &Sz[0],
12546 // Add (N0 < 0) ? abs2 - 1 : 0;
12547 SmallVector<SDValue, 16> Amt(NumElts,
12548 DAG.getConstant(EltTy.getSizeInBits() - Lg2,
12550 SDValue SRL = DAG.getNode(ISD::SRL, dl, VT, SGN,
12551 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &Amt[0],
12553 SDValue ADD = DAG.getNode(ISD::ADD, dl, VT, N0, SRL);
12554 SmallVector<SDValue, 16> Lg2Amt(NumElts, DAG.getConstant(Lg2, EltTy));
12555 SDValue SRA = DAG.getNode(ISD::SRA, dl, VT, ADD,
12556 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &Lg2Amt[0],
12559 // If we're dividing by a positive value, we're done. Otherwise, we must
12560 // negate the result.
12561 if (SplatValue.isNonNegative())
12564 SmallVector<SDValue, 16> V(NumElts, DAG.getConstant(0, EltTy));
12565 SDValue Zero = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], NumElts);
12566 return DAG.getNode(ISD::SUB, dl, VT, Zero, SRA);
12571 static SDValue LowerScalarImmediateShift(SDValue Op, SelectionDAG &DAG,
12572 const X86Subtarget *Subtarget) {
12573 EVT VT = Op.getValueType();
12575 SDValue R = Op.getOperand(0);
12576 SDValue Amt = Op.getOperand(1);
12578 // Optimize shl/srl/sra with constant shift amount.
12579 if (isSplatVector(Amt.getNode())) {
12580 SDValue SclrAmt = Amt->getOperand(0);
12581 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(SclrAmt)) {
12582 uint64_t ShiftAmt = C->getZExtValue();
12584 if (VT == MVT::v2i64 || VT == MVT::v4i32 || VT == MVT::v8i16 ||
12585 (Subtarget->hasInt256() &&
12586 (VT == MVT::v4i64 || VT == MVT::v8i32 || VT == MVT::v16i16)) ||
12587 (Subtarget->hasAVX512() &&
12588 (VT == MVT::v8i64 || VT == MVT::v16i32))) {
12589 if (Op.getOpcode() == ISD::SHL)
12590 return getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, R, ShiftAmt,
12592 if (Op.getOpcode() == ISD::SRL)
12593 return getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, R, ShiftAmt,
12595 if (Op.getOpcode() == ISD::SRA && VT != MVT::v2i64 && VT != MVT::v4i64)
12596 return getTargetVShiftByConstNode(X86ISD::VSRAI, dl, VT, R, ShiftAmt,
12600 if (VT == MVT::v16i8) {
12601 if (Op.getOpcode() == ISD::SHL) {
12602 // Make a large shift.
12603 SDValue SHL = getTargetVShiftByConstNode(X86ISD::VSHLI, dl,
12604 MVT::v8i16, R, ShiftAmt,
12606 SHL = DAG.getNode(ISD::BITCAST, dl, VT, SHL);
12607 // Zero out the rightmost bits.
12608 SmallVector<SDValue, 16> V(16,
12609 DAG.getConstant(uint8_t(-1U << ShiftAmt),
12611 return DAG.getNode(ISD::AND, dl, VT, SHL,
12612 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 16));
12614 if (Op.getOpcode() == ISD::SRL) {
12615 // Make a large shift.
12616 SDValue SRL = getTargetVShiftByConstNode(X86ISD::VSRLI, dl,
12617 MVT::v8i16, R, ShiftAmt,
12619 SRL = DAG.getNode(ISD::BITCAST, dl, VT, SRL);
12620 // Zero out the leftmost bits.
12621 SmallVector<SDValue, 16> V(16,
12622 DAG.getConstant(uint8_t(-1U) >> ShiftAmt,
12624 return DAG.getNode(ISD::AND, dl, VT, SRL,
12625 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 16));
12627 if (Op.getOpcode() == ISD::SRA) {
12628 if (ShiftAmt == 7) {
12629 // R s>> 7 === R s< 0
12630 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
12631 return DAG.getNode(X86ISD::PCMPGT, dl, VT, Zeros, R);
12634 // R s>> a === ((R u>> a) ^ m) - m
12635 SDValue Res = DAG.getNode(ISD::SRL, dl, VT, R, Amt);
12636 SmallVector<SDValue, 16> V(16, DAG.getConstant(128 >> ShiftAmt,
12638 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 16);
12639 Res = DAG.getNode(ISD::XOR, dl, VT, Res, Mask);
12640 Res = DAG.getNode(ISD::SUB, dl, VT, Res, Mask);
12643 llvm_unreachable("Unknown shift opcode.");
12646 if (Subtarget->hasInt256() && VT == MVT::v32i8) {
12647 if (Op.getOpcode() == ISD::SHL) {
12648 // Make a large shift.
12649 SDValue SHL = getTargetVShiftByConstNode(X86ISD::VSHLI, dl,
12650 MVT::v16i16, R, ShiftAmt,
12652 SHL = DAG.getNode(ISD::BITCAST, dl, VT, SHL);
12653 // Zero out the rightmost bits.
12654 SmallVector<SDValue, 32> V(32,
12655 DAG.getConstant(uint8_t(-1U << ShiftAmt),
12657 return DAG.getNode(ISD::AND, dl, VT, SHL,
12658 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 32));
12660 if (Op.getOpcode() == ISD::SRL) {
12661 // Make a large shift.
12662 SDValue SRL = getTargetVShiftByConstNode(X86ISD::VSRLI, dl,
12663 MVT::v16i16, R, ShiftAmt,
12665 SRL = DAG.getNode(ISD::BITCAST, dl, VT, SRL);
12666 // Zero out the leftmost bits.
12667 SmallVector<SDValue, 32> V(32,
12668 DAG.getConstant(uint8_t(-1U) >> ShiftAmt,
12670 return DAG.getNode(ISD::AND, dl, VT, SRL,
12671 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 32));
12673 if (Op.getOpcode() == ISD::SRA) {
12674 if (ShiftAmt == 7) {
12675 // R s>> 7 === R s< 0
12676 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
12677 return DAG.getNode(X86ISD::PCMPGT, dl, VT, Zeros, R);
12680 // R s>> a === ((R u>> a) ^ m) - m
12681 SDValue Res = DAG.getNode(ISD::SRL, dl, VT, R, Amt);
12682 SmallVector<SDValue, 32> V(32, DAG.getConstant(128 >> ShiftAmt,
12684 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 32);
12685 Res = DAG.getNode(ISD::XOR, dl, VT, Res, Mask);
12686 Res = DAG.getNode(ISD::SUB, dl, VT, Res, Mask);
12689 llvm_unreachable("Unknown shift opcode.");
12694 // Special case in 32-bit mode, where i64 is expanded into high and low parts.
12695 if (!Subtarget->is64Bit() &&
12696 (VT == MVT::v2i64 || (Subtarget->hasInt256() && VT == MVT::v4i64)) &&
12697 Amt.getOpcode() == ISD::BITCAST &&
12698 Amt.getOperand(0).getOpcode() == ISD::BUILD_VECTOR) {
12699 Amt = Amt.getOperand(0);
12700 unsigned Ratio = Amt.getValueType().getVectorNumElements() /
12701 VT.getVectorNumElements();
12702 unsigned RatioInLog2 = Log2_32_Ceil(Ratio);
12703 uint64_t ShiftAmt = 0;
12704 for (unsigned i = 0; i != Ratio; ++i) {
12705 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Amt.getOperand(i));
12709 ShiftAmt |= C->getZExtValue() << (i * (1 << (6 - RatioInLog2)));
12711 // Check remaining shift amounts.
12712 for (unsigned i = Ratio; i != Amt.getNumOperands(); i += Ratio) {
12713 uint64_t ShAmt = 0;
12714 for (unsigned j = 0; j != Ratio; ++j) {
12715 ConstantSDNode *C =
12716 dyn_cast<ConstantSDNode>(Amt.getOperand(i + j));
12720 ShAmt |= C->getZExtValue() << (j * (1 << (6 - RatioInLog2)));
12722 if (ShAmt != ShiftAmt)
12725 switch (Op.getOpcode()) {
12727 llvm_unreachable("Unknown shift opcode!");
12729 return getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, R, ShiftAmt,
12732 return getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, R, ShiftAmt,
12735 return getTargetVShiftByConstNode(X86ISD::VSRAI, dl, VT, R, ShiftAmt,
12743 static SDValue LowerScalarVariableShift(SDValue Op, SelectionDAG &DAG,
12744 const X86Subtarget* Subtarget) {
12745 EVT VT = Op.getValueType();
12747 SDValue R = Op.getOperand(0);
12748 SDValue Amt = Op.getOperand(1);
12750 if ((VT == MVT::v2i64 && Op.getOpcode() != ISD::SRA) ||
12751 VT == MVT::v4i32 || VT == MVT::v8i16 ||
12752 (Subtarget->hasInt256() &&
12753 ((VT == MVT::v4i64 && Op.getOpcode() != ISD::SRA) ||
12754 VT == MVT::v8i32 || VT == MVT::v16i16)) ||
12755 (Subtarget->hasAVX512() && (VT == MVT::v8i64 || VT == MVT::v16i32))) {
12757 EVT EltVT = VT.getVectorElementType();
12759 if (Amt.getOpcode() == ISD::BUILD_VECTOR) {
12760 unsigned NumElts = VT.getVectorNumElements();
12762 for (i = 0; i != NumElts; ++i) {
12763 if (Amt.getOperand(i).getOpcode() == ISD::UNDEF)
12767 for (j = i; j != NumElts; ++j) {
12768 SDValue Arg = Amt.getOperand(j);
12769 if (Arg.getOpcode() == ISD::UNDEF) continue;
12770 if (Arg != Amt.getOperand(i))
12773 if (i != NumElts && j == NumElts)
12774 BaseShAmt = Amt.getOperand(i);
12776 if (Amt.getOpcode() == ISD::EXTRACT_SUBVECTOR)
12777 Amt = Amt.getOperand(0);
12778 if (Amt.getOpcode() == ISD::VECTOR_SHUFFLE &&
12779 cast<ShuffleVectorSDNode>(Amt)->isSplat()) {
12780 SDValue InVec = Amt.getOperand(0);
12781 if (InVec.getOpcode() == ISD::BUILD_VECTOR) {
12782 unsigned NumElts = InVec.getValueType().getVectorNumElements();
12784 for (; i != NumElts; ++i) {
12785 SDValue Arg = InVec.getOperand(i);
12786 if (Arg.getOpcode() == ISD::UNDEF) continue;
12790 } else if (InVec.getOpcode() == ISD::INSERT_VECTOR_ELT) {
12791 if (ConstantSDNode *C =
12792 dyn_cast<ConstantSDNode>(InVec.getOperand(2))) {
12793 unsigned SplatIdx =
12794 cast<ShuffleVectorSDNode>(Amt)->getSplatIndex();
12795 if (C->getZExtValue() == SplatIdx)
12796 BaseShAmt = InVec.getOperand(1);
12799 if (BaseShAmt.getNode() == 0)
12800 BaseShAmt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, Amt,
12801 DAG.getIntPtrConstant(0));
12805 if (BaseShAmt.getNode()) {
12806 if (EltVT.bitsGT(MVT::i32))
12807 BaseShAmt = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, BaseShAmt);
12808 else if (EltVT.bitsLT(MVT::i32))
12809 BaseShAmt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, BaseShAmt);
12811 switch (Op.getOpcode()) {
12813 llvm_unreachable("Unknown shift opcode!");
12815 switch (VT.getSimpleVT().SimpleTy) {
12816 default: return SDValue();
12825 return getTargetVShiftNode(X86ISD::VSHLI, dl, VT, R, BaseShAmt, DAG);
12828 switch (VT.getSimpleVT().SimpleTy) {
12829 default: return SDValue();
12836 return getTargetVShiftNode(X86ISD::VSRAI, dl, VT, R, BaseShAmt, DAG);
12839 switch (VT.getSimpleVT().SimpleTy) {
12840 default: return SDValue();
12849 return getTargetVShiftNode(X86ISD::VSRLI, dl, VT, R, BaseShAmt, DAG);
12855 // Special case in 32-bit mode, where i64 is expanded into high and low parts.
12856 if (!Subtarget->is64Bit() &&
12857 (VT == MVT::v2i64 || (Subtarget->hasInt256() && VT == MVT::v4i64) ||
12858 (Subtarget->hasAVX512() && VT == MVT::v8i64)) &&
12859 Amt.getOpcode() == ISD::BITCAST &&
12860 Amt.getOperand(0).getOpcode() == ISD::BUILD_VECTOR) {
12861 Amt = Amt.getOperand(0);
12862 unsigned Ratio = Amt.getValueType().getVectorNumElements() /
12863 VT.getVectorNumElements();
12864 std::vector<SDValue> Vals(Ratio);
12865 for (unsigned i = 0; i != Ratio; ++i)
12866 Vals[i] = Amt.getOperand(i);
12867 for (unsigned i = Ratio; i != Amt.getNumOperands(); i += Ratio) {
12868 for (unsigned j = 0; j != Ratio; ++j)
12869 if (Vals[j] != Amt.getOperand(i + j))
12872 switch (Op.getOpcode()) {
12874 llvm_unreachable("Unknown shift opcode!");
12876 return DAG.getNode(X86ISD::VSHL, dl, VT, R, Op.getOperand(1));
12878 return DAG.getNode(X86ISD::VSRL, dl, VT, R, Op.getOperand(1));
12880 return DAG.getNode(X86ISD::VSRA, dl, VT, R, Op.getOperand(1));
12887 static SDValue LowerShift(SDValue Op, const X86Subtarget* Subtarget,
12888 SelectionDAG &DAG) {
12890 EVT VT = Op.getValueType();
12892 SDValue R = Op.getOperand(0);
12893 SDValue Amt = Op.getOperand(1);
12896 if (!Subtarget->hasSSE2())
12899 V = LowerScalarImmediateShift(Op, DAG, Subtarget);
12903 V = LowerScalarVariableShift(Op, DAG, Subtarget);
12907 if (Subtarget->hasAVX512() && (VT == MVT::v16i32 || VT == MVT::v8i64))
12909 // AVX2 has VPSLLV/VPSRAV/VPSRLV.
12910 if (Subtarget->hasInt256()) {
12911 if (Op.getOpcode() == ISD::SRL &&
12912 (VT == MVT::v2i64 || VT == MVT::v4i32 ||
12913 VT == MVT::v4i64 || VT == MVT::v8i32))
12915 if (Op.getOpcode() == ISD::SHL &&
12916 (VT == MVT::v2i64 || VT == MVT::v4i32 ||
12917 VT == MVT::v4i64 || VT == MVT::v8i32))
12919 if (Op.getOpcode() == ISD::SRA && (VT == MVT::v4i32 || VT == MVT::v8i32))
12923 // Lower SHL with variable shift amount.
12924 if (VT == MVT::v4i32 && Op->getOpcode() == ISD::SHL) {
12925 Op = DAG.getNode(ISD::SHL, dl, VT, Amt, DAG.getConstant(23, VT));
12927 Op = DAG.getNode(ISD::ADD, dl, VT, Op, DAG.getConstant(0x3f800000U, VT));
12928 Op = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, Op);
12929 Op = DAG.getNode(ISD::FP_TO_SINT, dl, VT, Op);
12930 return DAG.getNode(ISD::MUL, dl, VT, Op, R);
12932 if (VT == MVT::v16i8 && Op->getOpcode() == ISD::SHL) {
12933 assert(Subtarget->hasSSE2() && "Need SSE2 for pslli/pcmpeq.");
12936 Op = DAG.getNode(ISD::SHL, dl, VT, Amt, DAG.getConstant(5, VT));
12937 Op = DAG.getNode(ISD::BITCAST, dl, VT, Op);
12939 // Turn 'a' into a mask suitable for VSELECT
12940 SDValue VSelM = DAG.getConstant(0x80, VT);
12941 SDValue OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
12942 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
12944 SDValue CM1 = DAG.getConstant(0x0f, VT);
12945 SDValue CM2 = DAG.getConstant(0x3f, VT);
12947 // r = VSELECT(r, psllw(r & (char16)15, 4), a);
12948 SDValue M = DAG.getNode(ISD::AND, dl, VT, R, CM1);
12949 M = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, MVT::v8i16, M, 4, DAG);
12950 M = DAG.getNode(ISD::BITCAST, dl, VT, M);
12951 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel, M, R);
12954 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op);
12955 OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
12956 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
12958 // r = VSELECT(r, psllw(r & (char16)63, 2), a);
12959 M = DAG.getNode(ISD::AND, dl, VT, R, CM2);
12960 M = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, MVT::v8i16, M, 2, DAG);
12961 M = DAG.getNode(ISD::BITCAST, dl, VT, M);
12962 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel, M, R);
12965 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op);
12966 OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
12967 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
12969 // return VSELECT(r, r+r, a);
12970 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel,
12971 DAG.getNode(ISD::ADD, dl, VT, R, R), R);
12975 // Decompose 256-bit shifts into smaller 128-bit shifts.
12976 if (VT.is256BitVector()) {
12977 unsigned NumElems = VT.getVectorNumElements();
12978 MVT EltVT = VT.getVectorElementType().getSimpleVT();
12979 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
12981 // Extract the two vectors
12982 SDValue V1 = Extract128BitVector(R, 0, DAG, dl);
12983 SDValue V2 = Extract128BitVector(R, NumElems/2, DAG, dl);
12985 // Recreate the shift amount vectors
12986 SDValue Amt1, Amt2;
12987 if (Amt.getOpcode() == ISD::BUILD_VECTOR) {
12988 // Constant shift amount
12989 SmallVector<SDValue, 4> Amt1Csts;
12990 SmallVector<SDValue, 4> Amt2Csts;
12991 for (unsigned i = 0; i != NumElems/2; ++i)
12992 Amt1Csts.push_back(Amt->getOperand(i));
12993 for (unsigned i = NumElems/2; i != NumElems; ++i)
12994 Amt2Csts.push_back(Amt->getOperand(i));
12996 Amt1 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT,
12997 &Amt1Csts[0], NumElems/2);
12998 Amt2 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT,
12999 &Amt2Csts[0], NumElems/2);
13001 // Variable shift amount
13002 Amt1 = Extract128BitVector(Amt, 0, DAG, dl);
13003 Amt2 = Extract128BitVector(Amt, NumElems/2, DAG, dl);
13006 // Issue new vector shifts for the smaller types
13007 V1 = DAG.getNode(Op.getOpcode(), dl, NewVT, V1, Amt1);
13008 V2 = DAG.getNode(Op.getOpcode(), dl, NewVT, V2, Amt2);
13010 // Concatenate the result back
13011 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, V1, V2);
13017 static SDValue LowerXALUO(SDValue Op, SelectionDAG &DAG) {
13018 // Lower the "add/sub/mul with overflow" instruction into a regular ins plus
13019 // a "setcc" instruction that checks the overflow flag. The "brcond" lowering
13020 // looks for this combo and may remove the "setcc" instruction if the "setcc"
13021 // has only one use.
13022 SDNode *N = Op.getNode();
13023 SDValue LHS = N->getOperand(0);
13024 SDValue RHS = N->getOperand(1);
13025 unsigned BaseOp = 0;
13028 switch (Op.getOpcode()) {
13029 default: llvm_unreachable("Unknown ovf instruction!");
13031 // A subtract of one will be selected as a INC. Note that INC doesn't
13032 // set CF, so we can't do this for UADDO.
13033 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
13035 BaseOp = X86ISD::INC;
13036 Cond = X86::COND_O;
13039 BaseOp = X86ISD::ADD;
13040 Cond = X86::COND_O;
13043 BaseOp = X86ISD::ADD;
13044 Cond = X86::COND_B;
13047 // A subtract of one will be selected as a DEC. Note that DEC doesn't
13048 // set CF, so we can't do this for USUBO.
13049 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
13051 BaseOp = X86ISD::DEC;
13052 Cond = X86::COND_O;
13055 BaseOp = X86ISD::SUB;
13056 Cond = X86::COND_O;
13059 BaseOp = X86ISD::SUB;
13060 Cond = X86::COND_B;
13063 BaseOp = X86ISD::SMUL;
13064 Cond = X86::COND_O;
13066 case ISD::UMULO: { // i64, i8 = umulo lhs, rhs --> i64, i64, i32 umul lhs,rhs
13067 SDVTList VTs = DAG.getVTList(N->getValueType(0), N->getValueType(0),
13069 SDValue Sum = DAG.getNode(X86ISD::UMUL, DL, VTs, LHS, RHS);
13072 DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
13073 DAG.getConstant(X86::COND_O, MVT::i32),
13074 SDValue(Sum.getNode(), 2));
13076 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
13080 // Also sets EFLAGS.
13081 SDVTList VTs = DAG.getVTList(N->getValueType(0), MVT::i32);
13082 SDValue Sum = DAG.getNode(BaseOp, DL, VTs, LHS, RHS);
13085 DAG.getNode(X86ISD::SETCC, DL, N->getValueType(1),
13086 DAG.getConstant(Cond, MVT::i32),
13087 SDValue(Sum.getNode(), 1));
13089 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
13092 SDValue X86TargetLowering::LowerSIGN_EXTEND_INREG(SDValue Op,
13093 SelectionDAG &DAG) const {
13095 EVT ExtraVT = cast<VTSDNode>(Op.getOperand(1))->getVT();
13096 EVT VT = Op.getValueType();
13098 if (!Subtarget->hasSSE2() || !VT.isVector())
13101 unsigned BitsDiff = VT.getScalarType().getSizeInBits() -
13102 ExtraVT.getScalarType().getSizeInBits();
13104 switch (VT.getSimpleVT().SimpleTy) {
13105 default: return SDValue();
13108 if (!Subtarget->hasFp256())
13110 if (!Subtarget->hasInt256()) {
13111 // needs to be split
13112 unsigned NumElems = VT.getVectorNumElements();
13114 // Extract the LHS vectors
13115 SDValue LHS = Op.getOperand(0);
13116 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
13117 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
13119 MVT EltVT = VT.getVectorElementType().getSimpleVT();
13120 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
13122 EVT ExtraEltVT = ExtraVT.getVectorElementType();
13123 unsigned ExtraNumElems = ExtraVT.getVectorNumElements();
13124 ExtraVT = EVT::getVectorVT(*DAG.getContext(), ExtraEltVT,
13126 SDValue Extra = DAG.getValueType(ExtraVT);
13128 LHS1 = DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, Extra);
13129 LHS2 = DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, Extra);
13131 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, LHS1, LHS2);
13136 // (sext (vzext x)) -> (vsext x)
13137 SDValue Op0 = Op.getOperand(0);
13138 SDValue Op00 = Op0.getOperand(0);
13140 // Hopefully, this VECTOR_SHUFFLE is just a VZEXT.
13141 if (Op0.getOpcode() == ISD::BITCAST &&
13142 Op00.getOpcode() == ISD::VECTOR_SHUFFLE)
13143 Tmp1 = LowerVectorIntExtend(Op00, Subtarget, DAG);
13144 if (Tmp1.getNode()) {
13145 SDValue Tmp1Op0 = Tmp1.getOperand(0);
13146 assert(Tmp1Op0.getOpcode() == X86ISD::VZEXT &&
13147 "This optimization is invalid without a VZEXT.");
13148 return DAG.getNode(X86ISD::VSEXT, dl, VT, Tmp1Op0.getOperand(0));
13151 // If the above didn't work, then just use Shift-Left + Shift-Right.
13152 Tmp1 = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, Op0, BitsDiff,
13154 return getTargetVShiftByConstNode(X86ISD::VSRAI, dl, VT, Tmp1, BitsDiff,
13160 static SDValue LowerATOMIC_FENCE(SDValue Op, const X86Subtarget *Subtarget,
13161 SelectionDAG &DAG) {
13163 AtomicOrdering FenceOrdering = static_cast<AtomicOrdering>(
13164 cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue());
13165 SynchronizationScope FenceScope = static_cast<SynchronizationScope>(
13166 cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue());
13168 // The only fence that needs an instruction is a sequentially-consistent
13169 // cross-thread fence.
13170 if (FenceOrdering == SequentiallyConsistent && FenceScope == CrossThread) {
13171 // Use mfence if we have SSE2 or we're on x86-64 (even if we asked for
13172 // no-sse2). There isn't any reason to disable it if the target processor
13174 if (Subtarget->hasSSE2() || Subtarget->is64Bit())
13175 return DAG.getNode(X86ISD::MFENCE, dl, MVT::Other, Op.getOperand(0));
13177 SDValue Chain = Op.getOperand(0);
13178 SDValue Zero = DAG.getConstant(0, MVT::i32);
13180 DAG.getRegister(X86::ESP, MVT::i32), // Base
13181 DAG.getTargetConstant(1, MVT::i8), // Scale
13182 DAG.getRegister(0, MVT::i32), // Index
13183 DAG.getTargetConstant(0, MVT::i32), // Disp
13184 DAG.getRegister(0, MVT::i32), // Segment.
13188 SDNode *Res = DAG.getMachineNode(X86::OR32mrLocked, dl, MVT::Other, Ops);
13189 return SDValue(Res, 0);
13192 // MEMBARRIER is a compiler barrier; it codegens to a no-op.
13193 return DAG.getNode(X86ISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0));
13196 static SDValue LowerCMP_SWAP(SDValue Op, const X86Subtarget *Subtarget,
13197 SelectionDAG &DAG) {
13198 EVT T = Op.getValueType();
13202 switch(T.getSimpleVT().SimpleTy) {
13203 default: llvm_unreachable("Invalid value type!");
13204 case MVT::i8: Reg = X86::AL; size = 1; break;
13205 case MVT::i16: Reg = X86::AX; size = 2; break;
13206 case MVT::i32: Reg = X86::EAX; size = 4; break;
13208 assert(Subtarget->is64Bit() && "Node not type legal!");
13209 Reg = X86::RAX; size = 8;
13212 SDValue cpIn = DAG.getCopyToReg(Op.getOperand(0), DL, Reg,
13213 Op.getOperand(2), SDValue());
13214 SDValue Ops[] = { cpIn.getValue(0),
13217 DAG.getTargetConstant(size, MVT::i8),
13218 cpIn.getValue(1) };
13219 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
13220 MachineMemOperand *MMO = cast<AtomicSDNode>(Op)->getMemOperand();
13221 SDValue Result = DAG.getMemIntrinsicNode(X86ISD::LCMPXCHG_DAG, DL, Tys,
13222 Ops, array_lengthof(Ops), T, MMO);
13224 DAG.getCopyFromReg(Result.getValue(0), DL, Reg, T, Result.getValue(1));
13228 static SDValue LowerREADCYCLECOUNTER(SDValue Op, const X86Subtarget *Subtarget,
13229 SelectionDAG &DAG) {
13230 assert(Subtarget->is64Bit() && "Result not type legalized?");
13231 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
13232 SDValue TheChain = Op.getOperand(0);
13234 SDValue rd = DAG.getNode(X86ISD::RDTSC_DAG, dl, Tys, &TheChain, 1);
13235 SDValue rax = DAG.getCopyFromReg(rd, dl, X86::RAX, MVT::i64, rd.getValue(1));
13236 SDValue rdx = DAG.getCopyFromReg(rax.getValue(1), dl, X86::RDX, MVT::i64,
13238 SDValue Tmp = DAG.getNode(ISD::SHL, dl, MVT::i64, rdx,
13239 DAG.getConstant(32, MVT::i8));
13241 DAG.getNode(ISD::OR, dl, MVT::i64, rax, Tmp),
13244 return DAG.getMergeValues(Ops, array_lengthof(Ops), dl);
13247 static SDValue LowerBITCAST(SDValue Op, const X86Subtarget *Subtarget,
13248 SelectionDAG &DAG) {
13249 MVT SrcVT = Op.getOperand(0).getSimpleValueType();
13250 MVT DstVT = Op.getSimpleValueType();
13251 assert(Subtarget->is64Bit() && !Subtarget->hasSSE2() &&
13252 Subtarget->hasMMX() && "Unexpected custom BITCAST");
13253 assert((DstVT == MVT::i64 ||
13254 (DstVT.isVector() && DstVT.getSizeInBits()==64)) &&
13255 "Unexpected custom BITCAST");
13256 // i64 <=> MMX conversions are Legal.
13257 if (SrcVT==MVT::i64 && DstVT.isVector())
13259 if (DstVT==MVT::i64 && SrcVT.isVector())
13261 // MMX <=> MMX conversions are Legal.
13262 if (SrcVT.isVector() && DstVT.isVector())
13264 // All other conversions need to be expanded.
13268 static SDValue LowerLOAD_SUB(SDValue Op, SelectionDAG &DAG) {
13269 SDNode *Node = Op.getNode();
13271 EVT T = Node->getValueType(0);
13272 SDValue negOp = DAG.getNode(ISD::SUB, dl, T,
13273 DAG.getConstant(0, T), Node->getOperand(2));
13274 return DAG.getAtomic(ISD::ATOMIC_LOAD_ADD, dl,
13275 cast<AtomicSDNode>(Node)->getMemoryVT(),
13276 Node->getOperand(0),
13277 Node->getOperand(1), negOp,
13278 cast<AtomicSDNode>(Node)->getSrcValue(),
13279 cast<AtomicSDNode>(Node)->getAlignment(),
13280 cast<AtomicSDNode>(Node)->getOrdering(),
13281 cast<AtomicSDNode>(Node)->getSynchScope());
13284 static SDValue LowerATOMIC_STORE(SDValue Op, SelectionDAG &DAG) {
13285 SDNode *Node = Op.getNode();
13287 EVT VT = cast<AtomicSDNode>(Node)->getMemoryVT();
13289 // Convert seq_cst store -> xchg
13290 // Convert wide store -> swap (-> cmpxchg8b/cmpxchg16b)
13291 // FIXME: On 32-bit, store -> fist or movq would be more efficient
13292 // (The only way to get a 16-byte store is cmpxchg16b)
13293 // FIXME: 16-byte ATOMIC_SWAP isn't actually hooked up at the moment.
13294 if (cast<AtomicSDNode>(Node)->getOrdering() == SequentiallyConsistent ||
13295 !DAG.getTargetLoweringInfo().isTypeLegal(VT)) {
13296 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_SWAP, dl,
13297 cast<AtomicSDNode>(Node)->getMemoryVT(),
13298 Node->getOperand(0),
13299 Node->getOperand(1), Node->getOperand(2),
13300 cast<AtomicSDNode>(Node)->getMemOperand(),
13301 cast<AtomicSDNode>(Node)->getOrdering(),
13302 cast<AtomicSDNode>(Node)->getSynchScope());
13303 return Swap.getValue(1);
13305 // Other atomic stores have a simple pattern.
13309 static SDValue LowerADDC_ADDE_SUBC_SUBE(SDValue Op, SelectionDAG &DAG) {
13310 EVT VT = Op.getNode()->getValueType(0);
13312 // Let legalize expand this if it isn't a legal type yet.
13313 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
13316 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
13319 bool ExtraOp = false;
13320 switch (Op.getOpcode()) {
13321 default: llvm_unreachable("Invalid code");
13322 case ISD::ADDC: Opc = X86ISD::ADD; break;
13323 case ISD::ADDE: Opc = X86ISD::ADC; ExtraOp = true; break;
13324 case ISD::SUBC: Opc = X86ISD::SUB; break;
13325 case ISD::SUBE: Opc = X86ISD::SBB; ExtraOp = true; break;
13329 return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0),
13331 return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0),
13332 Op.getOperand(1), Op.getOperand(2));
13335 static SDValue LowerFSINCOS(SDValue Op, const X86Subtarget *Subtarget,
13336 SelectionDAG &DAG) {
13337 assert(Subtarget->isTargetDarwin() && Subtarget->is64Bit());
13339 // For MacOSX, we want to call an alternative entry point: __sincos_stret,
13340 // which returns the values as { float, float } (in XMM0) or
13341 // { double, double } (which is returned in XMM0, XMM1).
13343 SDValue Arg = Op.getOperand(0);
13344 EVT ArgVT = Arg.getValueType();
13345 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
13347 TargetLowering::ArgListTy Args;
13348 TargetLowering::ArgListEntry Entry;
13352 Entry.isSExt = false;
13353 Entry.isZExt = false;
13354 Args.push_back(Entry);
13356 bool isF64 = ArgVT == MVT::f64;
13357 // Only optimize x86_64 for now. i386 is a bit messy. For f32,
13358 // the small struct {f32, f32} is returned in (eax, edx). For f64,
13359 // the results are returned via SRet in memory.
13360 const char *LibcallName = isF64 ? "__sincos_stret" : "__sincosf_stret";
13361 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
13362 SDValue Callee = DAG.getExternalSymbol(LibcallName, TLI.getPointerTy());
13364 Type *RetTy = isF64
13365 ? (Type*)StructType::get(ArgTy, ArgTy, NULL)
13366 : (Type*)VectorType::get(ArgTy, 4);
13368 CallLoweringInfo CLI(DAG.getEntryNode(), RetTy,
13369 false, false, false, false, 0,
13370 CallingConv::C, /*isTaillCall=*/false,
13371 /*doesNotRet=*/false, /*isReturnValueUsed*/true,
13372 Callee, Args, DAG, dl);
13373 std::pair<SDValue, SDValue> CallResult = TLI.LowerCallTo(CLI);
13376 // Returned in xmm0 and xmm1.
13377 return CallResult.first;
13379 // Returned in bits 0:31 and 32:64 xmm0.
13380 SDValue SinVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ArgVT,
13381 CallResult.first, DAG.getIntPtrConstant(0));
13382 SDValue CosVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ArgVT,
13383 CallResult.first, DAG.getIntPtrConstant(1));
13384 SDVTList Tys = DAG.getVTList(ArgVT, ArgVT);
13385 return DAG.getNode(ISD::MERGE_VALUES, dl, Tys, SinVal, CosVal);
13388 /// LowerOperation - Provide custom lowering hooks for some operations.
13390 SDValue X86TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
13391 switch (Op.getOpcode()) {
13392 default: llvm_unreachable("Should not custom lower this!");
13393 case ISD::SIGN_EXTEND_INREG: return LowerSIGN_EXTEND_INREG(Op,DAG);
13394 case ISD::ATOMIC_FENCE: return LowerATOMIC_FENCE(Op, Subtarget, DAG);
13395 case ISD::ATOMIC_CMP_SWAP: return LowerCMP_SWAP(Op, Subtarget, DAG);
13396 case ISD::ATOMIC_LOAD_SUB: return LowerLOAD_SUB(Op,DAG);
13397 case ISD::ATOMIC_STORE: return LowerATOMIC_STORE(Op,DAG);
13398 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
13399 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG);
13400 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
13401 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
13402 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG);
13403 case ISD::EXTRACT_SUBVECTOR: return LowerEXTRACT_SUBVECTOR(Op,Subtarget,DAG);
13404 case ISD::INSERT_SUBVECTOR: return LowerINSERT_SUBVECTOR(Op, Subtarget,DAG);
13405 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
13406 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
13407 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
13408 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
13409 case ISD::ExternalSymbol: return LowerExternalSymbol(Op, DAG);
13410 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
13411 case ISD::SHL_PARTS:
13412 case ISD::SRA_PARTS:
13413 case ISD::SRL_PARTS: return LowerShiftParts(Op, DAG);
13414 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG);
13415 case ISD::UINT_TO_FP: return LowerUINT_TO_FP(Op, DAG);
13416 case ISD::TRUNCATE: return LowerTRUNCATE(Op, DAG);
13417 case ISD::ZERO_EXTEND: return LowerZERO_EXTEND(Op, Subtarget, DAG);
13418 case ISD::SIGN_EXTEND: return LowerSIGN_EXTEND(Op, Subtarget, DAG);
13419 case ISD::ANY_EXTEND: return LowerANY_EXTEND(Op, Subtarget, DAG);
13420 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG);
13421 case ISD::FP_TO_UINT: return LowerFP_TO_UINT(Op, DAG);
13422 case ISD::FP_EXTEND: return LowerFP_EXTEND(Op, DAG);
13423 case ISD::FABS: return LowerFABS(Op, DAG);
13424 case ISD::FNEG: return LowerFNEG(Op, DAG);
13425 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG);
13426 case ISD::FGETSIGN: return LowerFGETSIGN(Op, DAG);
13427 case ISD::SETCC: return LowerSETCC(Op, DAG);
13428 case ISD::SELECT: return LowerSELECT(Op, DAG);
13429 case ISD::BRCOND: return LowerBRCOND(Op, DAG);
13430 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
13431 case ISD::VASTART: return LowerVASTART(Op, DAG);
13432 case ISD::VAARG: return LowerVAARG(Op, DAG);
13433 case ISD::VACOPY: return LowerVACOPY(Op, Subtarget, DAG);
13434 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
13435 case ISD::INTRINSIC_VOID:
13436 case ISD::INTRINSIC_W_CHAIN: return LowerINTRINSIC_W_CHAIN(Op, Subtarget, DAG);
13437 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
13438 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
13439 case ISD::FRAME_TO_ARGS_OFFSET:
13440 return LowerFRAME_TO_ARGS_OFFSET(Op, DAG);
13441 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
13442 case ISD::EH_RETURN: return LowerEH_RETURN(Op, DAG);
13443 case ISD::EH_SJLJ_SETJMP: return lowerEH_SJLJ_SETJMP(Op, DAG);
13444 case ISD::EH_SJLJ_LONGJMP: return lowerEH_SJLJ_LONGJMP(Op, DAG);
13445 case ISD::INIT_TRAMPOLINE: return LowerINIT_TRAMPOLINE(Op, DAG);
13446 case ISD::ADJUST_TRAMPOLINE: return LowerADJUST_TRAMPOLINE(Op, DAG);
13447 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
13448 case ISD::CTLZ: return LowerCTLZ(Op, DAG);
13449 case ISD::CTLZ_ZERO_UNDEF: return LowerCTLZ_ZERO_UNDEF(Op, DAG);
13450 case ISD::CTTZ: return LowerCTTZ(Op, DAG);
13451 case ISD::MUL: return LowerMUL(Op, Subtarget, DAG);
13454 case ISD::SHL: return LowerShift(Op, Subtarget, DAG);
13460 case ISD::UMULO: return LowerXALUO(Op, DAG);
13461 case ISD::READCYCLECOUNTER: return LowerREADCYCLECOUNTER(Op, Subtarget,DAG);
13462 case ISD::BITCAST: return LowerBITCAST(Op, Subtarget, DAG);
13466 case ISD::SUBE: return LowerADDC_ADDE_SUBC_SUBE(Op, DAG);
13467 case ISD::ADD: return LowerADD(Op, DAG);
13468 case ISD::SUB: return LowerSUB(Op, DAG);
13469 case ISD::SDIV: return LowerSDIV(Op, DAG);
13470 case ISD::FSINCOS: return LowerFSINCOS(Op, Subtarget, DAG);
13474 static void ReplaceATOMIC_LOAD(SDNode *Node,
13475 SmallVectorImpl<SDValue> &Results,
13476 SelectionDAG &DAG) {
13478 EVT VT = cast<AtomicSDNode>(Node)->getMemoryVT();
13480 // Convert wide load -> cmpxchg8b/cmpxchg16b
13481 // FIXME: On 32-bit, load -> fild or movq would be more efficient
13482 // (The only way to get a 16-byte load is cmpxchg16b)
13483 // FIXME: 16-byte ATOMIC_CMP_SWAP isn't actually hooked up at the moment.
13484 SDValue Zero = DAG.getConstant(0, VT);
13485 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_CMP_SWAP, dl, VT,
13486 Node->getOperand(0),
13487 Node->getOperand(1), Zero, Zero,
13488 cast<AtomicSDNode>(Node)->getMemOperand(),
13489 cast<AtomicSDNode>(Node)->getOrdering(),
13490 cast<AtomicSDNode>(Node)->getSynchScope());
13491 Results.push_back(Swap.getValue(0));
13492 Results.push_back(Swap.getValue(1));
13496 ReplaceATOMIC_BINARY_64(SDNode *Node, SmallVectorImpl<SDValue>&Results,
13497 SelectionDAG &DAG, unsigned NewOp) {
13499 assert (Node->getValueType(0) == MVT::i64 &&
13500 "Only know how to expand i64 atomics");
13502 SDValue Chain = Node->getOperand(0);
13503 SDValue In1 = Node->getOperand(1);
13504 SDValue In2L = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
13505 Node->getOperand(2), DAG.getIntPtrConstant(0));
13506 SDValue In2H = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
13507 Node->getOperand(2), DAG.getIntPtrConstant(1));
13508 SDValue Ops[] = { Chain, In1, In2L, In2H };
13509 SDVTList Tys = DAG.getVTList(MVT::i32, MVT::i32, MVT::Other);
13511 DAG.getMemIntrinsicNode(NewOp, dl, Tys, Ops, array_lengthof(Ops), MVT::i64,
13512 cast<MemSDNode>(Node)->getMemOperand());
13513 SDValue OpsF[] = { Result.getValue(0), Result.getValue(1)};
13514 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, OpsF, 2));
13515 Results.push_back(Result.getValue(2));
13518 /// ReplaceNodeResults - Replace a node with an illegal result type
13519 /// with a new node built out of custom code.
13520 void X86TargetLowering::ReplaceNodeResults(SDNode *N,
13521 SmallVectorImpl<SDValue>&Results,
13522 SelectionDAG &DAG) const {
13524 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
13525 switch (N->getOpcode()) {
13527 llvm_unreachable("Do not know how to custom type legalize this operation!");
13528 case ISD::SIGN_EXTEND_INREG:
13533 // We don't want to expand or promote these.
13535 case ISD::FP_TO_SINT:
13536 case ISD::FP_TO_UINT: {
13537 bool IsSigned = N->getOpcode() == ISD::FP_TO_SINT;
13539 if (!IsSigned && !isIntegerTypeFTOL(SDValue(N, 0).getValueType()))
13542 std::pair<SDValue,SDValue> Vals =
13543 FP_TO_INTHelper(SDValue(N, 0), DAG, IsSigned, /*IsReplace=*/ true);
13544 SDValue FIST = Vals.first, StackSlot = Vals.second;
13545 if (FIST.getNode() != 0) {
13546 EVT VT = N->getValueType(0);
13547 // Return a load from the stack slot.
13548 if (StackSlot.getNode() != 0)
13549 Results.push_back(DAG.getLoad(VT, dl, FIST, StackSlot,
13550 MachinePointerInfo(),
13551 false, false, false, 0));
13553 Results.push_back(FIST);
13557 case ISD::UINT_TO_FP: {
13558 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
13559 if (N->getOperand(0).getValueType() != MVT::v2i32 ||
13560 N->getValueType(0) != MVT::v2f32)
13562 SDValue ZExtIn = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v2i64,
13564 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL),
13566 SDValue VBias = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2f64, Bias, Bias);
13567 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64, ZExtIn,
13568 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, VBias));
13569 Or = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Or);
13570 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, Or, VBias);
13571 Results.push_back(DAG.getNode(X86ISD::VFPROUND, dl, MVT::v4f32, Sub));
13574 case ISD::FP_ROUND: {
13575 if (!TLI.isTypeLegal(N->getOperand(0).getValueType()))
13577 SDValue V = DAG.getNode(X86ISD::VFPROUND, dl, MVT::v4f32, N->getOperand(0));
13578 Results.push_back(V);
13581 case ISD::READCYCLECOUNTER: {
13582 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
13583 SDValue TheChain = N->getOperand(0);
13584 SDValue rd = DAG.getNode(X86ISD::RDTSC_DAG, dl, Tys, &TheChain, 1);
13585 SDValue eax = DAG.getCopyFromReg(rd, dl, X86::EAX, MVT::i32,
13587 SDValue edx = DAG.getCopyFromReg(eax.getValue(1), dl, X86::EDX, MVT::i32,
13589 // Use a buildpair to merge the two 32-bit values into a 64-bit one.
13590 SDValue Ops[] = { eax, edx };
13591 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Ops,
13592 array_lengthof(Ops)));
13593 Results.push_back(edx.getValue(1));
13596 case ISD::ATOMIC_CMP_SWAP: {
13597 EVT T = N->getValueType(0);
13598 assert((T == MVT::i64 || T == MVT::i128) && "can only expand cmpxchg pair");
13599 bool Regs64bit = T == MVT::i128;
13600 EVT HalfT = Regs64bit ? MVT::i64 : MVT::i32;
13601 SDValue cpInL, cpInH;
13602 cpInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2),
13603 DAG.getConstant(0, HalfT));
13604 cpInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2),
13605 DAG.getConstant(1, HalfT));
13606 cpInL = DAG.getCopyToReg(N->getOperand(0), dl,
13607 Regs64bit ? X86::RAX : X86::EAX,
13609 cpInH = DAG.getCopyToReg(cpInL.getValue(0), dl,
13610 Regs64bit ? X86::RDX : X86::EDX,
13611 cpInH, cpInL.getValue(1));
13612 SDValue swapInL, swapInH;
13613 swapInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3),
13614 DAG.getConstant(0, HalfT));
13615 swapInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3),
13616 DAG.getConstant(1, HalfT));
13617 swapInL = DAG.getCopyToReg(cpInH.getValue(0), dl,
13618 Regs64bit ? X86::RBX : X86::EBX,
13619 swapInL, cpInH.getValue(1));
13620 swapInH = DAG.getCopyToReg(swapInL.getValue(0), dl,
13621 Regs64bit ? X86::RCX : X86::ECX,
13622 swapInH, swapInL.getValue(1));
13623 SDValue Ops[] = { swapInH.getValue(0),
13625 swapInH.getValue(1) };
13626 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
13627 MachineMemOperand *MMO = cast<AtomicSDNode>(N)->getMemOperand();
13628 unsigned Opcode = Regs64bit ? X86ISD::LCMPXCHG16_DAG :
13629 X86ISD::LCMPXCHG8_DAG;
13630 SDValue Result = DAG.getMemIntrinsicNode(Opcode, dl, Tys,
13631 Ops, array_lengthof(Ops), T, MMO);
13632 SDValue cpOutL = DAG.getCopyFromReg(Result.getValue(0), dl,
13633 Regs64bit ? X86::RAX : X86::EAX,
13634 HalfT, Result.getValue(1));
13635 SDValue cpOutH = DAG.getCopyFromReg(cpOutL.getValue(1), dl,
13636 Regs64bit ? X86::RDX : X86::EDX,
13637 HalfT, cpOutL.getValue(2));
13638 SDValue OpsF[] = { cpOutL.getValue(0), cpOutH.getValue(0)};
13639 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, T, OpsF, 2));
13640 Results.push_back(cpOutH.getValue(1));
13643 case ISD::ATOMIC_LOAD_ADD:
13644 case ISD::ATOMIC_LOAD_AND:
13645 case ISD::ATOMIC_LOAD_NAND:
13646 case ISD::ATOMIC_LOAD_OR:
13647 case ISD::ATOMIC_LOAD_SUB:
13648 case ISD::ATOMIC_LOAD_XOR:
13649 case ISD::ATOMIC_LOAD_MAX:
13650 case ISD::ATOMIC_LOAD_MIN:
13651 case ISD::ATOMIC_LOAD_UMAX:
13652 case ISD::ATOMIC_LOAD_UMIN:
13653 case ISD::ATOMIC_SWAP: {
13655 switch (N->getOpcode()) {
13656 default: llvm_unreachable("Unexpected opcode");
13657 case ISD::ATOMIC_LOAD_ADD:
13658 Opc = X86ISD::ATOMADD64_DAG;
13660 case ISD::ATOMIC_LOAD_AND:
13661 Opc = X86ISD::ATOMAND64_DAG;
13663 case ISD::ATOMIC_LOAD_NAND:
13664 Opc = X86ISD::ATOMNAND64_DAG;
13666 case ISD::ATOMIC_LOAD_OR:
13667 Opc = X86ISD::ATOMOR64_DAG;
13669 case ISD::ATOMIC_LOAD_SUB:
13670 Opc = X86ISD::ATOMSUB64_DAG;
13672 case ISD::ATOMIC_LOAD_XOR:
13673 Opc = X86ISD::ATOMXOR64_DAG;
13675 case ISD::ATOMIC_LOAD_MAX:
13676 Opc = X86ISD::ATOMMAX64_DAG;
13678 case ISD::ATOMIC_LOAD_MIN:
13679 Opc = X86ISD::ATOMMIN64_DAG;
13681 case ISD::ATOMIC_LOAD_UMAX:
13682 Opc = X86ISD::ATOMUMAX64_DAG;
13684 case ISD::ATOMIC_LOAD_UMIN:
13685 Opc = X86ISD::ATOMUMIN64_DAG;
13687 case ISD::ATOMIC_SWAP:
13688 Opc = X86ISD::ATOMSWAP64_DAG;
13691 ReplaceATOMIC_BINARY_64(N, Results, DAG, Opc);
13694 case ISD::ATOMIC_LOAD:
13695 ReplaceATOMIC_LOAD(N, Results, DAG);
13699 const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
13701 default: return NULL;
13702 case X86ISD::BSF: return "X86ISD::BSF";
13703 case X86ISD::BSR: return "X86ISD::BSR";
13704 case X86ISD::SHLD: return "X86ISD::SHLD";
13705 case X86ISD::SHRD: return "X86ISD::SHRD";
13706 case X86ISD::FAND: return "X86ISD::FAND";
13707 case X86ISD::FANDN: return "X86ISD::FANDN";
13708 case X86ISD::FOR: return "X86ISD::FOR";
13709 case X86ISD::FXOR: return "X86ISD::FXOR";
13710 case X86ISD::FSRL: return "X86ISD::FSRL";
13711 case X86ISD::FILD: return "X86ISD::FILD";
13712 case X86ISD::FILD_FLAG: return "X86ISD::FILD_FLAG";
13713 case X86ISD::FP_TO_INT16_IN_MEM: return "X86ISD::FP_TO_INT16_IN_MEM";
13714 case X86ISD::FP_TO_INT32_IN_MEM: return "X86ISD::FP_TO_INT32_IN_MEM";
13715 case X86ISD::FP_TO_INT64_IN_MEM: return "X86ISD::FP_TO_INT64_IN_MEM";
13716 case X86ISD::FLD: return "X86ISD::FLD";
13717 case X86ISD::FST: return "X86ISD::FST";
13718 case X86ISD::CALL: return "X86ISD::CALL";
13719 case X86ISD::RDTSC_DAG: return "X86ISD::RDTSC_DAG";
13720 case X86ISD::BT: return "X86ISD::BT";
13721 case X86ISD::CMP: return "X86ISD::CMP";
13722 case X86ISD::COMI: return "X86ISD::COMI";
13723 case X86ISD::UCOMI: return "X86ISD::UCOMI";
13724 case X86ISD::CMPM: return "X86ISD::CMPM";
13725 case X86ISD::CMPMU: return "X86ISD::CMPMU";
13726 case X86ISD::SETCC: return "X86ISD::SETCC";
13727 case X86ISD::SETCC_CARRY: return "X86ISD::SETCC_CARRY";
13728 case X86ISD::FSETCCsd: return "X86ISD::FSETCCsd";
13729 case X86ISD::FSETCCss: return "X86ISD::FSETCCss";
13730 case X86ISD::CMOV: return "X86ISD::CMOV";
13731 case X86ISD::BRCOND: return "X86ISD::BRCOND";
13732 case X86ISD::RET_FLAG: return "X86ISD::RET_FLAG";
13733 case X86ISD::REP_STOS: return "X86ISD::REP_STOS";
13734 case X86ISD::REP_MOVS: return "X86ISD::REP_MOVS";
13735 case X86ISD::GlobalBaseReg: return "X86ISD::GlobalBaseReg";
13736 case X86ISD::Wrapper: return "X86ISD::Wrapper";
13737 case X86ISD::WrapperRIP: return "X86ISD::WrapperRIP";
13738 case X86ISD::PEXTRB: return "X86ISD::PEXTRB";
13739 case X86ISD::PEXTRW: return "X86ISD::PEXTRW";
13740 case X86ISD::INSERTPS: return "X86ISD::INSERTPS";
13741 case X86ISD::PINSRB: return "X86ISD::PINSRB";
13742 case X86ISD::PINSRW: return "X86ISD::PINSRW";
13743 case X86ISD::PSHUFB: return "X86ISD::PSHUFB";
13744 case X86ISD::ANDNP: return "X86ISD::ANDNP";
13745 case X86ISD::PSIGN: return "X86ISD::PSIGN";
13746 case X86ISD::BLENDV: return "X86ISD::BLENDV";
13747 case X86ISD::BLENDI: return "X86ISD::BLENDI";
13748 case X86ISD::SUBUS: return "X86ISD::SUBUS";
13749 case X86ISD::HADD: return "X86ISD::HADD";
13750 case X86ISD::HSUB: return "X86ISD::HSUB";
13751 case X86ISD::FHADD: return "X86ISD::FHADD";
13752 case X86ISD::FHSUB: return "X86ISD::FHSUB";
13753 case X86ISD::UMAX: return "X86ISD::UMAX";
13754 case X86ISD::UMIN: return "X86ISD::UMIN";
13755 case X86ISD::SMAX: return "X86ISD::SMAX";
13756 case X86ISD::SMIN: return "X86ISD::SMIN";
13757 case X86ISD::FMAX: return "X86ISD::FMAX";
13758 case X86ISD::FMIN: return "X86ISD::FMIN";
13759 case X86ISD::FMAXC: return "X86ISD::FMAXC";
13760 case X86ISD::FMINC: return "X86ISD::FMINC";
13761 case X86ISD::FRSQRT: return "X86ISD::FRSQRT";
13762 case X86ISD::FRCP: return "X86ISD::FRCP";
13763 case X86ISD::TLSADDR: return "X86ISD::TLSADDR";
13764 case X86ISD::TLSBASEADDR: return "X86ISD::TLSBASEADDR";
13765 case X86ISD::TLSCALL: return "X86ISD::TLSCALL";
13766 case X86ISD::EH_SJLJ_SETJMP: return "X86ISD::EH_SJLJ_SETJMP";
13767 case X86ISD::EH_SJLJ_LONGJMP: return "X86ISD::EH_SJLJ_LONGJMP";
13768 case X86ISD::EH_RETURN: return "X86ISD::EH_RETURN";
13769 case X86ISD::TC_RETURN: return "X86ISD::TC_RETURN";
13770 case X86ISD::FNSTCW16m: return "X86ISD::FNSTCW16m";
13771 case X86ISD::FNSTSW16r: return "X86ISD::FNSTSW16r";
13772 case X86ISD::LCMPXCHG_DAG: return "X86ISD::LCMPXCHG_DAG";
13773 case X86ISD::LCMPXCHG8_DAG: return "X86ISD::LCMPXCHG8_DAG";
13774 case X86ISD::ATOMADD64_DAG: return "X86ISD::ATOMADD64_DAG";
13775 case X86ISD::ATOMSUB64_DAG: return "X86ISD::ATOMSUB64_DAG";
13776 case X86ISD::ATOMOR64_DAG: return "X86ISD::ATOMOR64_DAG";
13777 case X86ISD::ATOMXOR64_DAG: return "X86ISD::ATOMXOR64_DAG";
13778 case X86ISD::ATOMAND64_DAG: return "X86ISD::ATOMAND64_DAG";
13779 case X86ISD::ATOMNAND64_DAG: return "X86ISD::ATOMNAND64_DAG";
13780 case X86ISD::VZEXT_MOVL: return "X86ISD::VZEXT_MOVL";
13781 case X86ISD::VSEXT_MOVL: return "X86ISD::VSEXT_MOVL";
13782 case X86ISD::VZEXT_LOAD: return "X86ISD::VZEXT_LOAD";
13783 case X86ISD::VZEXT: return "X86ISD::VZEXT";
13784 case X86ISD::VSEXT: return "X86ISD::VSEXT";
13785 case X86ISD::VTRUNC: return "X86ISD::VTRUNC";
13786 case X86ISD::VTRUNCM: return "X86ISD::VTRUNCM";
13787 case X86ISD::VINSERT: return "X86ISD::VINSERT";
13788 case X86ISD::VFPEXT: return "X86ISD::VFPEXT";
13789 case X86ISD::VFPROUND: return "X86ISD::VFPROUND";
13790 case X86ISD::VSHLDQ: return "X86ISD::VSHLDQ";
13791 case X86ISD::VSRLDQ: return "X86ISD::VSRLDQ";
13792 case X86ISD::VSHL: return "X86ISD::VSHL";
13793 case X86ISD::VSRL: return "X86ISD::VSRL";
13794 case X86ISD::VSRA: return "X86ISD::VSRA";
13795 case X86ISD::VSHLI: return "X86ISD::VSHLI";
13796 case X86ISD::VSRLI: return "X86ISD::VSRLI";
13797 case X86ISD::VSRAI: return "X86ISD::VSRAI";
13798 case X86ISD::CMPP: return "X86ISD::CMPP";
13799 case X86ISD::PCMPEQ: return "X86ISD::PCMPEQ";
13800 case X86ISD::PCMPGT: return "X86ISD::PCMPGT";
13801 case X86ISD::PCMPEQM: return "X86ISD::PCMPEQM";
13802 case X86ISD::PCMPGTM: return "X86ISD::PCMPGTM";
13803 case X86ISD::ADD: return "X86ISD::ADD";
13804 case X86ISD::SUB: return "X86ISD::SUB";
13805 case X86ISD::ADC: return "X86ISD::ADC";
13806 case X86ISD::SBB: return "X86ISD::SBB";
13807 case X86ISD::SMUL: return "X86ISD::SMUL";
13808 case X86ISD::UMUL: return "X86ISD::UMUL";
13809 case X86ISD::INC: return "X86ISD::INC";
13810 case X86ISD::DEC: return "X86ISD::DEC";
13811 case X86ISD::OR: return "X86ISD::OR";
13812 case X86ISD::XOR: return "X86ISD::XOR";
13813 case X86ISD::AND: return "X86ISD::AND";
13814 case X86ISD::BLSI: return "X86ISD::BLSI";
13815 case X86ISD::BLSMSK: return "X86ISD::BLSMSK";
13816 case X86ISD::BLSR: return "X86ISD::BLSR";
13817 case X86ISD::BZHI: return "X86ISD::BZHI";
13818 case X86ISD::BEXTR: return "X86ISD::BEXTR";
13819 case X86ISD::MUL_IMM: return "X86ISD::MUL_IMM";
13820 case X86ISD::PTEST: return "X86ISD::PTEST";
13821 case X86ISD::TESTP: return "X86ISD::TESTP";
13822 case X86ISD::TESTM: return "X86ISD::TESTM";
13823 case X86ISD::KORTEST: return "X86ISD::KORTEST";
13824 case X86ISD::KTEST: return "X86ISD::KTEST";
13825 case X86ISD::PALIGNR: return "X86ISD::PALIGNR";
13826 case X86ISD::PSHUFD: return "X86ISD::PSHUFD";
13827 case X86ISD::PSHUFHW: return "X86ISD::PSHUFHW";
13828 case X86ISD::PSHUFLW: return "X86ISD::PSHUFLW";
13829 case X86ISD::SHUFP: return "X86ISD::SHUFP";
13830 case X86ISD::MOVLHPS: return "X86ISD::MOVLHPS";
13831 case X86ISD::MOVLHPD: return "X86ISD::MOVLHPD";
13832 case X86ISD::MOVHLPS: return "X86ISD::MOVHLPS";
13833 case X86ISD::MOVLPS: return "X86ISD::MOVLPS";
13834 case X86ISD::MOVLPD: return "X86ISD::MOVLPD";
13835 case X86ISD::MOVDDUP: return "X86ISD::MOVDDUP";
13836 case X86ISD::MOVSHDUP: return "X86ISD::MOVSHDUP";
13837 case X86ISD::MOVSLDUP: return "X86ISD::MOVSLDUP";
13838 case X86ISD::MOVSD: return "X86ISD::MOVSD";
13839 case X86ISD::MOVSS: return "X86ISD::MOVSS";
13840 case X86ISD::UNPCKL: return "X86ISD::UNPCKL";
13841 case X86ISD::UNPCKH: return "X86ISD::UNPCKH";
13842 case X86ISD::VBROADCAST: return "X86ISD::VBROADCAST";
13843 case X86ISD::VBROADCASTM: return "X86ISD::VBROADCASTM";
13844 case X86ISD::VPERMILP: return "X86ISD::VPERMILP";
13845 case X86ISD::VPERM2X128: return "X86ISD::VPERM2X128";
13846 case X86ISD::VPERMV: return "X86ISD::VPERMV";
13847 case X86ISD::VPERMV3: return "X86ISD::VPERMV3";
13848 case X86ISD::VPERMI: return "X86ISD::VPERMI";
13849 case X86ISD::PMULUDQ: return "X86ISD::PMULUDQ";
13850 case X86ISD::VASTART_SAVE_XMM_REGS: return "X86ISD::VASTART_SAVE_XMM_REGS";
13851 case X86ISD::VAARG_64: return "X86ISD::VAARG_64";
13852 case X86ISD::WIN_ALLOCA: return "X86ISD::WIN_ALLOCA";
13853 case X86ISD::MEMBARRIER: return "X86ISD::MEMBARRIER";
13854 case X86ISD::SEG_ALLOCA: return "X86ISD::SEG_ALLOCA";
13855 case X86ISD::WIN_FTOL: return "X86ISD::WIN_FTOL";
13856 case X86ISD::SAHF: return "X86ISD::SAHF";
13857 case X86ISD::RDRAND: return "X86ISD::RDRAND";
13858 case X86ISD::RDSEED: return "X86ISD::RDSEED";
13859 case X86ISD::FMADD: return "X86ISD::FMADD";
13860 case X86ISD::FMSUB: return "X86ISD::FMSUB";
13861 case X86ISD::FNMADD: return "X86ISD::FNMADD";
13862 case X86ISD::FNMSUB: return "X86ISD::FNMSUB";
13863 case X86ISD::FMADDSUB: return "X86ISD::FMADDSUB";
13864 case X86ISD::FMSUBADD: return "X86ISD::FMSUBADD";
13865 case X86ISD::PCMPESTRI: return "X86ISD::PCMPESTRI";
13866 case X86ISD::PCMPISTRI: return "X86ISD::PCMPISTRI";
13867 case X86ISD::XTEST: return "X86ISD::XTEST";
13871 // isLegalAddressingMode - Return true if the addressing mode represented
13872 // by AM is legal for this target, for a load/store of the specified type.
13873 bool X86TargetLowering::isLegalAddressingMode(const AddrMode &AM,
13875 // X86 supports extremely general addressing modes.
13876 CodeModel::Model M = getTargetMachine().getCodeModel();
13877 Reloc::Model R = getTargetMachine().getRelocationModel();
13879 // X86 allows a sign-extended 32-bit immediate field as a displacement.
13880 if (!X86::isOffsetSuitableForCodeModel(AM.BaseOffs, M, AM.BaseGV != NULL))
13885 Subtarget->ClassifyGlobalReference(AM.BaseGV, getTargetMachine());
13887 // If a reference to this global requires an extra load, we can't fold it.
13888 if (isGlobalStubReference(GVFlags))
13891 // If BaseGV requires a register for the PIC base, we cannot also have a
13892 // BaseReg specified.
13893 if (AM.HasBaseReg && isGlobalRelativeToPICBase(GVFlags))
13896 // If lower 4G is not available, then we must use rip-relative addressing.
13897 if ((M != CodeModel::Small || R != Reloc::Static) &&
13898 Subtarget->is64Bit() && (AM.BaseOffs || AM.Scale > 1))
13902 switch (AM.Scale) {
13908 // These scales always work.
13913 // These scales are formed with basereg+scalereg. Only accept if there is
13918 default: // Other stuff never works.
13925 bool X86TargetLowering::isTruncateFree(Type *Ty1, Type *Ty2) const {
13926 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
13928 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits();
13929 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits();
13930 return NumBits1 > NumBits2;
13933 bool X86TargetLowering::allowTruncateForTailCall(Type *Ty1, Type *Ty2) const {
13934 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
13937 if (!isTypeLegal(EVT::getEVT(Ty1)))
13940 assert(Ty1->getPrimitiveSizeInBits() <= 64 && "i128 is probably not a noop");
13942 // Assuming the caller doesn't have a zeroext or signext return parameter,
13943 // truncation all the way down to i1 is valid.
13947 bool X86TargetLowering::isLegalICmpImmediate(int64_t Imm) const {
13948 return isInt<32>(Imm);
13951 bool X86TargetLowering::isLegalAddImmediate(int64_t Imm) const {
13952 // Can also use sub to handle negated immediates.
13953 return isInt<32>(Imm);
13956 bool X86TargetLowering::isTruncateFree(EVT VT1, EVT VT2) const {
13957 if (!VT1.isInteger() || !VT2.isInteger())
13959 unsigned NumBits1 = VT1.getSizeInBits();
13960 unsigned NumBits2 = VT2.getSizeInBits();
13961 return NumBits1 > NumBits2;
13964 bool X86TargetLowering::isZExtFree(Type *Ty1, Type *Ty2) const {
13965 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
13966 return Ty1->isIntegerTy(32) && Ty2->isIntegerTy(64) && Subtarget->is64Bit();
13969 bool X86TargetLowering::isZExtFree(EVT VT1, EVT VT2) const {
13970 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
13971 return VT1 == MVT::i32 && VT2 == MVT::i64 && Subtarget->is64Bit();
13974 bool X86TargetLowering::isZExtFree(SDValue Val, EVT VT2) const {
13975 EVT VT1 = Val.getValueType();
13976 if (isZExtFree(VT1, VT2))
13979 if (Val.getOpcode() != ISD::LOAD)
13982 if (!VT1.isSimple() || !VT1.isInteger() ||
13983 !VT2.isSimple() || !VT2.isInteger())
13986 switch (VT1.getSimpleVT().SimpleTy) {
13991 // X86 has 8, 16, and 32-bit zero-extending loads.
13999 X86TargetLowering::isFMAFasterThanFMulAndFAdd(EVT VT) const {
14000 if (!(Subtarget->hasFMA() || Subtarget->hasFMA4()))
14003 VT = VT.getScalarType();
14005 if (!VT.isSimple())
14008 switch (VT.getSimpleVT().SimpleTy) {
14019 bool X86TargetLowering::isNarrowingProfitable(EVT VT1, EVT VT2) const {
14020 // i16 instructions are longer (0x66 prefix) and potentially slower.
14021 return !(VT1 == MVT::i32 && VT2 == MVT::i16);
14024 /// isShuffleMaskLegal - Targets can use this to indicate that they only
14025 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
14026 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
14027 /// are assumed to be legal.
14029 X86TargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M,
14031 if (!VT.isSimple())
14034 MVT SVT = VT.getSimpleVT();
14036 // Very little shuffling can be done for 64-bit vectors right now.
14037 if (VT.getSizeInBits() == 64)
14040 // FIXME: pshufb, blends, shifts.
14041 return (SVT.getVectorNumElements() == 2 ||
14042 ShuffleVectorSDNode::isSplatMask(&M[0], VT) ||
14043 isMOVLMask(M, SVT) ||
14044 isSHUFPMask(M, SVT) ||
14045 isPSHUFDMask(M, SVT) ||
14046 isPSHUFHWMask(M, SVT, Subtarget->hasInt256()) ||
14047 isPSHUFLWMask(M, SVT, Subtarget->hasInt256()) ||
14048 isPALIGNRMask(M, SVT, Subtarget) ||
14049 isUNPCKLMask(M, SVT, Subtarget->hasInt256()) ||
14050 isUNPCKHMask(M, SVT, Subtarget->hasInt256()) ||
14051 isUNPCKL_v_undef_Mask(M, SVT, Subtarget->hasInt256()) ||
14052 isUNPCKH_v_undef_Mask(M, SVT, Subtarget->hasInt256()));
14056 X86TargetLowering::isVectorClearMaskLegal(const SmallVectorImpl<int> &Mask,
14058 if (!VT.isSimple())
14061 MVT SVT = VT.getSimpleVT();
14062 unsigned NumElts = SVT.getVectorNumElements();
14063 // FIXME: This collection of masks seems suspect.
14066 if (NumElts == 4 && SVT.is128BitVector()) {
14067 return (isMOVLMask(Mask, SVT) ||
14068 isCommutedMOVLMask(Mask, SVT, true) ||
14069 isSHUFPMask(Mask, SVT) ||
14070 isSHUFPMask(Mask, SVT, /* Commuted */ true));
14075 //===----------------------------------------------------------------------===//
14076 // X86 Scheduler Hooks
14077 //===----------------------------------------------------------------------===//
14079 /// Utility function to emit xbegin specifying the start of an RTM region.
14080 static MachineBasicBlock *EmitXBegin(MachineInstr *MI, MachineBasicBlock *MBB,
14081 const TargetInstrInfo *TII) {
14082 DebugLoc DL = MI->getDebugLoc();
14084 const BasicBlock *BB = MBB->getBasicBlock();
14085 MachineFunction::iterator I = MBB;
14088 // For the v = xbegin(), we generate
14099 MachineBasicBlock *thisMBB = MBB;
14100 MachineFunction *MF = MBB->getParent();
14101 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
14102 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
14103 MF->insert(I, mainMBB);
14104 MF->insert(I, sinkMBB);
14106 // Transfer the remainder of BB and its successor edges to sinkMBB.
14107 sinkMBB->splice(sinkMBB->begin(), MBB,
14108 llvm::next(MachineBasicBlock::iterator(MI)), MBB->end());
14109 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
14113 // # fallthrough to mainMBB
14114 // # abortion to sinkMBB
14115 BuildMI(thisMBB, DL, TII->get(X86::XBEGIN_4)).addMBB(sinkMBB);
14116 thisMBB->addSuccessor(mainMBB);
14117 thisMBB->addSuccessor(sinkMBB);
14121 BuildMI(mainMBB, DL, TII->get(X86::MOV32ri), X86::EAX).addImm(-1);
14122 mainMBB->addSuccessor(sinkMBB);
14125 // EAX is live into the sinkMBB
14126 sinkMBB->addLiveIn(X86::EAX);
14127 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
14128 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
14131 MI->eraseFromParent();
14135 // Get CMPXCHG opcode for the specified data type.
14136 static unsigned getCmpXChgOpcode(EVT VT) {
14137 switch (VT.getSimpleVT().SimpleTy) {
14138 case MVT::i8: return X86::LCMPXCHG8;
14139 case MVT::i16: return X86::LCMPXCHG16;
14140 case MVT::i32: return X86::LCMPXCHG32;
14141 case MVT::i64: return X86::LCMPXCHG64;
14145 llvm_unreachable("Invalid operand size!");
14148 // Get LOAD opcode for the specified data type.
14149 static unsigned getLoadOpcode(EVT VT) {
14150 switch (VT.getSimpleVT().SimpleTy) {
14151 case MVT::i8: return X86::MOV8rm;
14152 case MVT::i16: return X86::MOV16rm;
14153 case MVT::i32: return X86::MOV32rm;
14154 case MVT::i64: return X86::MOV64rm;
14158 llvm_unreachable("Invalid operand size!");
14161 // Get opcode of the non-atomic one from the specified atomic instruction.
14162 static unsigned getNonAtomicOpcode(unsigned Opc) {
14164 case X86::ATOMAND8: return X86::AND8rr;
14165 case X86::ATOMAND16: return X86::AND16rr;
14166 case X86::ATOMAND32: return X86::AND32rr;
14167 case X86::ATOMAND64: return X86::AND64rr;
14168 case X86::ATOMOR8: return X86::OR8rr;
14169 case X86::ATOMOR16: return X86::OR16rr;
14170 case X86::ATOMOR32: return X86::OR32rr;
14171 case X86::ATOMOR64: return X86::OR64rr;
14172 case X86::ATOMXOR8: return X86::XOR8rr;
14173 case X86::ATOMXOR16: return X86::XOR16rr;
14174 case X86::ATOMXOR32: return X86::XOR32rr;
14175 case X86::ATOMXOR64: return X86::XOR64rr;
14177 llvm_unreachable("Unhandled atomic-load-op opcode!");
14180 // Get opcode of the non-atomic one from the specified atomic instruction with
14182 static unsigned getNonAtomicOpcodeWithExtraOpc(unsigned Opc,
14183 unsigned &ExtraOpc) {
14185 case X86::ATOMNAND8: ExtraOpc = X86::NOT8r; return X86::AND8rr;
14186 case X86::ATOMNAND16: ExtraOpc = X86::NOT16r; return X86::AND16rr;
14187 case X86::ATOMNAND32: ExtraOpc = X86::NOT32r; return X86::AND32rr;
14188 case X86::ATOMNAND64: ExtraOpc = X86::NOT64r; return X86::AND64rr;
14189 case X86::ATOMMAX8: ExtraOpc = X86::CMP8rr; return X86::CMOVL32rr;
14190 case X86::ATOMMAX16: ExtraOpc = X86::CMP16rr; return X86::CMOVL16rr;
14191 case X86::ATOMMAX32: ExtraOpc = X86::CMP32rr; return X86::CMOVL32rr;
14192 case X86::ATOMMAX64: ExtraOpc = X86::CMP64rr; return X86::CMOVL64rr;
14193 case X86::ATOMMIN8: ExtraOpc = X86::CMP8rr; return X86::CMOVG32rr;
14194 case X86::ATOMMIN16: ExtraOpc = X86::CMP16rr; return X86::CMOVG16rr;
14195 case X86::ATOMMIN32: ExtraOpc = X86::CMP32rr; return X86::CMOVG32rr;
14196 case X86::ATOMMIN64: ExtraOpc = X86::CMP64rr; return X86::CMOVG64rr;
14197 case X86::ATOMUMAX8: ExtraOpc = X86::CMP8rr; return X86::CMOVB32rr;
14198 case X86::ATOMUMAX16: ExtraOpc = X86::CMP16rr; return X86::CMOVB16rr;
14199 case X86::ATOMUMAX32: ExtraOpc = X86::CMP32rr; return X86::CMOVB32rr;
14200 case X86::ATOMUMAX64: ExtraOpc = X86::CMP64rr; return X86::CMOVB64rr;
14201 case X86::ATOMUMIN8: ExtraOpc = X86::CMP8rr; return X86::CMOVA32rr;
14202 case X86::ATOMUMIN16: ExtraOpc = X86::CMP16rr; return X86::CMOVA16rr;
14203 case X86::ATOMUMIN32: ExtraOpc = X86::CMP32rr; return X86::CMOVA32rr;
14204 case X86::ATOMUMIN64: ExtraOpc = X86::CMP64rr; return X86::CMOVA64rr;
14206 llvm_unreachable("Unhandled atomic-load-op opcode!");
14209 // Get opcode of the non-atomic one from the specified atomic instruction for
14210 // 64-bit data type on 32-bit target.
14211 static unsigned getNonAtomic6432Opcode(unsigned Opc, unsigned &HiOpc) {
14213 case X86::ATOMAND6432: HiOpc = X86::AND32rr; return X86::AND32rr;
14214 case X86::ATOMOR6432: HiOpc = X86::OR32rr; return X86::OR32rr;
14215 case X86::ATOMXOR6432: HiOpc = X86::XOR32rr; return X86::XOR32rr;
14216 case X86::ATOMADD6432: HiOpc = X86::ADC32rr; return X86::ADD32rr;
14217 case X86::ATOMSUB6432: HiOpc = X86::SBB32rr; return X86::SUB32rr;
14218 case X86::ATOMSWAP6432: HiOpc = X86::MOV32rr; return X86::MOV32rr;
14219 case X86::ATOMMAX6432: HiOpc = X86::SETLr; return X86::SETLr;
14220 case X86::ATOMMIN6432: HiOpc = X86::SETGr; return X86::SETGr;
14221 case X86::ATOMUMAX6432: HiOpc = X86::SETBr; return X86::SETBr;
14222 case X86::ATOMUMIN6432: HiOpc = X86::SETAr; return X86::SETAr;
14224 llvm_unreachable("Unhandled atomic-load-op opcode!");
14227 // Get opcode of the non-atomic one from the specified atomic instruction for
14228 // 64-bit data type on 32-bit target with extra opcode.
14229 static unsigned getNonAtomic6432OpcodeWithExtraOpc(unsigned Opc,
14231 unsigned &ExtraOpc) {
14233 case X86::ATOMNAND6432:
14234 ExtraOpc = X86::NOT32r;
14235 HiOpc = X86::AND32rr;
14236 return X86::AND32rr;
14238 llvm_unreachable("Unhandled atomic-load-op opcode!");
14241 // Get pseudo CMOV opcode from the specified data type.
14242 static unsigned getPseudoCMOVOpc(EVT VT) {
14243 switch (VT.getSimpleVT().SimpleTy) {
14244 case MVT::i8: return X86::CMOV_GR8;
14245 case MVT::i16: return X86::CMOV_GR16;
14246 case MVT::i32: return X86::CMOV_GR32;
14250 llvm_unreachable("Unknown CMOV opcode!");
14253 // EmitAtomicLoadArith - emit the code sequence for pseudo atomic instructions.
14254 // They will be translated into a spin-loop or compare-exchange loop from
14257 // dst = atomic-fetch-op MI.addr, MI.val
14263 // t1 = LOAD MI.addr
14265 // t4 = phi(t1, t3 / loop)
14266 // t2 = OP MI.val, t4
14268 // LCMPXCHG [MI.addr], t2, [EAX is implicitly used & defined]
14274 MachineBasicBlock *
14275 X86TargetLowering::EmitAtomicLoadArith(MachineInstr *MI,
14276 MachineBasicBlock *MBB) const {
14277 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
14278 DebugLoc DL = MI->getDebugLoc();
14280 MachineFunction *MF = MBB->getParent();
14281 MachineRegisterInfo &MRI = MF->getRegInfo();
14283 const BasicBlock *BB = MBB->getBasicBlock();
14284 MachineFunction::iterator I = MBB;
14287 assert(MI->getNumOperands() <= X86::AddrNumOperands + 4 &&
14288 "Unexpected number of operands");
14290 assert(MI->hasOneMemOperand() &&
14291 "Expected atomic-load-op to have one memoperand");
14293 // Memory Reference
14294 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
14295 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
14297 unsigned DstReg, SrcReg;
14298 unsigned MemOpndSlot;
14300 unsigned CurOp = 0;
14302 DstReg = MI->getOperand(CurOp++).getReg();
14303 MemOpndSlot = CurOp;
14304 CurOp += X86::AddrNumOperands;
14305 SrcReg = MI->getOperand(CurOp++).getReg();
14307 const TargetRegisterClass *RC = MRI.getRegClass(DstReg);
14308 MVT::SimpleValueType VT = *RC->vt_begin();
14309 unsigned t1 = MRI.createVirtualRegister(RC);
14310 unsigned t2 = MRI.createVirtualRegister(RC);
14311 unsigned t3 = MRI.createVirtualRegister(RC);
14312 unsigned t4 = MRI.createVirtualRegister(RC);
14313 unsigned PhyReg = getX86SubSuperRegister(X86::EAX, VT);
14315 unsigned LCMPXCHGOpc = getCmpXChgOpcode(VT);
14316 unsigned LOADOpc = getLoadOpcode(VT);
14318 // For the atomic load-arith operator, we generate
14321 // t1 = LOAD [MI.addr]
14323 // t4 = phi(t1 / thisMBB, t3 / mainMBB)
14324 // t1 = OP MI.val, EAX
14326 // LCMPXCHG [MI.addr], t1, [EAX is implicitly used & defined]
14332 MachineBasicBlock *thisMBB = MBB;
14333 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
14334 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
14335 MF->insert(I, mainMBB);
14336 MF->insert(I, sinkMBB);
14338 MachineInstrBuilder MIB;
14340 // Transfer the remainder of BB and its successor edges to sinkMBB.
14341 sinkMBB->splice(sinkMBB->begin(), MBB,
14342 llvm::next(MachineBasicBlock::iterator(MI)), MBB->end());
14343 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
14346 MIB = BuildMI(thisMBB, DL, TII->get(LOADOpc), t1);
14347 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
14348 MachineOperand NewMO = MI->getOperand(MemOpndSlot + i);
14350 NewMO.setIsKill(false);
14351 MIB.addOperand(NewMO);
14353 for (MachineInstr::mmo_iterator MMOI = MMOBegin; MMOI != MMOEnd; ++MMOI) {
14354 unsigned flags = (*MMOI)->getFlags();
14355 flags = (flags & ~MachineMemOperand::MOStore) | MachineMemOperand::MOLoad;
14356 MachineMemOperand *MMO =
14357 MF->getMachineMemOperand((*MMOI)->getPointerInfo(), flags,
14358 (*MMOI)->getSize(),
14359 (*MMOI)->getBaseAlignment(),
14360 (*MMOI)->getTBAAInfo(),
14361 (*MMOI)->getRanges());
14362 MIB.addMemOperand(MMO);
14365 thisMBB->addSuccessor(mainMBB);
14368 MachineBasicBlock *origMainMBB = mainMBB;
14371 MachineInstr *Phi = BuildMI(mainMBB, DL, TII->get(X86::PHI), t4)
14372 .addReg(t1).addMBB(thisMBB).addReg(t3).addMBB(mainMBB);
14374 unsigned Opc = MI->getOpcode();
14377 llvm_unreachable("Unhandled atomic-load-op opcode!");
14378 case X86::ATOMAND8:
14379 case X86::ATOMAND16:
14380 case X86::ATOMAND32:
14381 case X86::ATOMAND64:
14383 case X86::ATOMOR16:
14384 case X86::ATOMOR32:
14385 case X86::ATOMOR64:
14386 case X86::ATOMXOR8:
14387 case X86::ATOMXOR16:
14388 case X86::ATOMXOR32:
14389 case X86::ATOMXOR64: {
14390 unsigned ARITHOpc = getNonAtomicOpcode(Opc);
14391 BuildMI(mainMBB, DL, TII->get(ARITHOpc), t2).addReg(SrcReg)
14395 case X86::ATOMNAND8:
14396 case X86::ATOMNAND16:
14397 case X86::ATOMNAND32:
14398 case X86::ATOMNAND64: {
14399 unsigned Tmp = MRI.createVirtualRegister(RC);
14401 unsigned ANDOpc = getNonAtomicOpcodeWithExtraOpc(Opc, NOTOpc);
14402 BuildMI(mainMBB, DL, TII->get(ANDOpc), Tmp).addReg(SrcReg)
14404 BuildMI(mainMBB, DL, TII->get(NOTOpc), t2).addReg(Tmp);
14407 case X86::ATOMMAX8:
14408 case X86::ATOMMAX16:
14409 case X86::ATOMMAX32:
14410 case X86::ATOMMAX64:
14411 case X86::ATOMMIN8:
14412 case X86::ATOMMIN16:
14413 case X86::ATOMMIN32:
14414 case X86::ATOMMIN64:
14415 case X86::ATOMUMAX8:
14416 case X86::ATOMUMAX16:
14417 case X86::ATOMUMAX32:
14418 case X86::ATOMUMAX64:
14419 case X86::ATOMUMIN8:
14420 case X86::ATOMUMIN16:
14421 case X86::ATOMUMIN32:
14422 case X86::ATOMUMIN64: {
14424 unsigned CMOVOpc = getNonAtomicOpcodeWithExtraOpc(Opc, CMPOpc);
14426 BuildMI(mainMBB, DL, TII->get(CMPOpc))
14430 if (Subtarget->hasCMov()) {
14431 if (VT != MVT::i8) {
14433 BuildMI(mainMBB, DL, TII->get(CMOVOpc), t2)
14437 // Promote i8 to i32 to use CMOV32
14438 const TargetRegisterInfo* TRI = getTargetMachine().getRegisterInfo();
14439 const TargetRegisterClass *RC32 =
14440 TRI->getSubClassWithSubReg(getRegClassFor(MVT::i32), X86::sub_8bit);
14441 unsigned SrcReg32 = MRI.createVirtualRegister(RC32);
14442 unsigned AccReg32 = MRI.createVirtualRegister(RC32);
14443 unsigned Tmp = MRI.createVirtualRegister(RC32);
14445 unsigned Undef = MRI.createVirtualRegister(RC32);
14446 BuildMI(mainMBB, DL, TII->get(TargetOpcode::IMPLICIT_DEF), Undef);
14448 BuildMI(mainMBB, DL, TII->get(TargetOpcode::INSERT_SUBREG), SrcReg32)
14451 .addImm(X86::sub_8bit);
14452 BuildMI(mainMBB, DL, TII->get(TargetOpcode::INSERT_SUBREG), AccReg32)
14455 .addImm(X86::sub_8bit);
14457 BuildMI(mainMBB, DL, TII->get(CMOVOpc), Tmp)
14461 BuildMI(mainMBB, DL, TII->get(TargetOpcode::COPY), t2)
14462 .addReg(Tmp, 0, X86::sub_8bit);
14465 // Use pseudo select and lower them.
14466 assert((VT == MVT::i8 || VT == MVT::i16 || VT == MVT::i32) &&
14467 "Invalid atomic-load-op transformation!");
14468 unsigned SelOpc = getPseudoCMOVOpc(VT);
14469 X86::CondCode CC = X86::getCondFromCMovOpc(CMOVOpc);
14470 assert(CC != X86::COND_INVALID && "Invalid atomic-load-op transformation!");
14471 MIB = BuildMI(mainMBB, DL, TII->get(SelOpc), t2)
14472 .addReg(SrcReg).addReg(t4)
14474 mainMBB = EmitLoweredSelect(MIB, mainMBB);
14475 // Replace the original PHI node as mainMBB is changed after CMOV
14477 BuildMI(*origMainMBB, Phi, DL, TII->get(X86::PHI), t4)
14478 .addReg(t1).addMBB(thisMBB).addReg(t3).addMBB(mainMBB);
14479 Phi->eraseFromParent();
14485 // Copy PhyReg back from virtual register.
14486 BuildMI(mainMBB, DL, TII->get(TargetOpcode::COPY), PhyReg)
14489 MIB = BuildMI(mainMBB, DL, TII->get(LCMPXCHGOpc));
14490 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
14491 MachineOperand NewMO = MI->getOperand(MemOpndSlot + i);
14493 NewMO.setIsKill(false);
14494 MIB.addOperand(NewMO);
14497 MIB.setMemRefs(MMOBegin, MMOEnd);
14499 // Copy PhyReg back to virtual register.
14500 BuildMI(mainMBB, DL, TII->get(TargetOpcode::COPY), t3)
14503 BuildMI(mainMBB, DL, TII->get(X86::JNE_4)).addMBB(origMainMBB);
14505 mainMBB->addSuccessor(origMainMBB);
14506 mainMBB->addSuccessor(sinkMBB);
14509 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
14510 TII->get(TargetOpcode::COPY), DstReg)
14513 MI->eraseFromParent();
14517 // EmitAtomicLoadArith6432 - emit the code sequence for pseudo atomic
14518 // instructions. They will be translated into a spin-loop or compare-exchange
14522 // dst = atomic-fetch-op MI.addr, MI.val
14528 // t1L = LOAD [MI.addr + 0]
14529 // t1H = LOAD [MI.addr + 4]
14531 // t4L = phi(t1L, t3L / loop)
14532 // t4H = phi(t1H, t3H / loop)
14533 // t2L = OP MI.val.lo, t4L
14534 // t2H = OP MI.val.hi, t4H
14539 // LCMPXCHG8B [MI.addr], [ECX:EBX & EDX:EAX are implicitly used and EDX:EAX is implicitly defined]
14547 MachineBasicBlock *
14548 X86TargetLowering::EmitAtomicLoadArith6432(MachineInstr *MI,
14549 MachineBasicBlock *MBB) const {
14550 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
14551 DebugLoc DL = MI->getDebugLoc();
14553 MachineFunction *MF = MBB->getParent();
14554 MachineRegisterInfo &MRI = MF->getRegInfo();
14556 const BasicBlock *BB = MBB->getBasicBlock();
14557 MachineFunction::iterator I = MBB;
14560 assert(MI->getNumOperands() <= X86::AddrNumOperands + 7 &&
14561 "Unexpected number of operands");
14563 assert(MI->hasOneMemOperand() &&
14564 "Expected atomic-load-op32 to have one memoperand");
14566 // Memory Reference
14567 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
14568 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
14570 unsigned DstLoReg, DstHiReg;
14571 unsigned SrcLoReg, SrcHiReg;
14572 unsigned MemOpndSlot;
14574 unsigned CurOp = 0;
14576 DstLoReg = MI->getOperand(CurOp++).getReg();
14577 DstHiReg = MI->getOperand(CurOp++).getReg();
14578 MemOpndSlot = CurOp;
14579 CurOp += X86::AddrNumOperands;
14580 SrcLoReg = MI->getOperand(CurOp++).getReg();
14581 SrcHiReg = MI->getOperand(CurOp++).getReg();
14583 const TargetRegisterClass *RC = &X86::GR32RegClass;
14584 const TargetRegisterClass *RC8 = &X86::GR8RegClass;
14586 unsigned t1L = MRI.createVirtualRegister(RC);
14587 unsigned t1H = MRI.createVirtualRegister(RC);
14588 unsigned t2L = MRI.createVirtualRegister(RC);
14589 unsigned t2H = MRI.createVirtualRegister(RC);
14590 unsigned t3L = MRI.createVirtualRegister(RC);
14591 unsigned t3H = MRI.createVirtualRegister(RC);
14592 unsigned t4L = MRI.createVirtualRegister(RC);
14593 unsigned t4H = MRI.createVirtualRegister(RC);
14595 unsigned LCMPXCHGOpc = X86::LCMPXCHG8B;
14596 unsigned LOADOpc = X86::MOV32rm;
14598 // For the atomic load-arith operator, we generate
14601 // t1L = LOAD [MI.addr + 0]
14602 // t1H = LOAD [MI.addr + 4]
14604 // t4L = phi(t1L / thisMBB, t3L / mainMBB)
14605 // t4H = phi(t1H / thisMBB, t3H / mainMBB)
14606 // t2L = OP MI.val.lo, t4L
14607 // t2H = OP MI.val.hi, t4H
14610 // LCMPXCHG8B [MI.addr], [ECX:EBX & EDX:EAX are implicitly used and EDX:EAX is implicitly defined]
14618 MachineBasicBlock *thisMBB = MBB;
14619 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
14620 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
14621 MF->insert(I, mainMBB);
14622 MF->insert(I, sinkMBB);
14624 MachineInstrBuilder MIB;
14626 // Transfer the remainder of BB and its successor edges to sinkMBB.
14627 sinkMBB->splice(sinkMBB->begin(), MBB,
14628 llvm::next(MachineBasicBlock::iterator(MI)), MBB->end());
14629 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
14633 MIB = BuildMI(thisMBB, DL, TII->get(LOADOpc), t1L);
14634 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
14635 MachineOperand NewMO = MI->getOperand(MemOpndSlot + i);
14637 NewMO.setIsKill(false);
14638 MIB.addOperand(NewMO);
14640 for (MachineInstr::mmo_iterator MMOI = MMOBegin; MMOI != MMOEnd; ++MMOI) {
14641 unsigned flags = (*MMOI)->getFlags();
14642 flags = (flags & ~MachineMemOperand::MOStore) | MachineMemOperand::MOLoad;
14643 MachineMemOperand *MMO =
14644 MF->getMachineMemOperand((*MMOI)->getPointerInfo(), flags,
14645 (*MMOI)->getSize(),
14646 (*MMOI)->getBaseAlignment(),
14647 (*MMOI)->getTBAAInfo(),
14648 (*MMOI)->getRanges());
14649 MIB.addMemOperand(MMO);
14651 MachineInstr *LowMI = MIB;
14654 MIB = BuildMI(thisMBB, DL, TII->get(LOADOpc), t1H);
14655 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
14656 if (i == X86::AddrDisp) {
14657 MIB.addDisp(MI->getOperand(MemOpndSlot + i), 4); // 4 == sizeof(i32)
14659 MachineOperand NewMO = MI->getOperand(MemOpndSlot + i);
14661 NewMO.setIsKill(false);
14662 MIB.addOperand(NewMO);
14665 MIB.setMemRefs(LowMI->memoperands_begin(), LowMI->memoperands_end());
14667 thisMBB->addSuccessor(mainMBB);
14670 MachineBasicBlock *origMainMBB = mainMBB;
14673 MachineInstr *PhiL = BuildMI(mainMBB, DL, TII->get(X86::PHI), t4L)
14674 .addReg(t1L).addMBB(thisMBB).addReg(t3L).addMBB(mainMBB);
14675 MachineInstr *PhiH = BuildMI(mainMBB, DL, TII->get(X86::PHI), t4H)
14676 .addReg(t1H).addMBB(thisMBB).addReg(t3H).addMBB(mainMBB);
14678 unsigned Opc = MI->getOpcode();
14681 llvm_unreachable("Unhandled atomic-load-op6432 opcode!");
14682 case X86::ATOMAND6432:
14683 case X86::ATOMOR6432:
14684 case X86::ATOMXOR6432:
14685 case X86::ATOMADD6432:
14686 case X86::ATOMSUB6432: {
14688 unsigned LoOpc = getNonAtomic6432Opcode(Opc, HiOpc);
14689 BuildMI(mainMBB, DL, TII->get(LoOpc), t2L).addReg(t4L)
14691 BuildMI(mainMBB, DL, TII->get(HiOpc), t2H).addReg(t4H)
14695 case X86::ATOMNAND6432: {
14696 unsigned HiOpc, NOTOpc;
14697 unsigned LoOpc = getNonAtomic6432OpcodeWithExtraOpc(Opc, HiOpc, NOTOpc);
14698 unsigned TmpL = MRI.createVirtualRegister(RC);
14699 unsigned TmpH = MRI.createVirtualRegister(RC);
14700 BuildMI(mainMBB, DL, TII->get(LoOpc), TmpL).addReg(SrcLoReg)
14702 BuildMI(mainMBB, DL, TII->get(HiOpc), TmpH).addReg(SrcHiReg)
14704 BuildMI(mainMBB, DL, TII->get(NOTOpc), t2L).addReg(TmpL);
14705 BuildMI(mainMBB, DL, TII->get(NOTOpc), t2H).addReg(TmpH);
14708 case X86::ATOMMAX6432:
14709 case X86::ATOMMIN6432:
14710 case X86::ATOMUMAX6432:
14711 case X86::ATOMUMIN6432: {
14713 unsigned LoOpc = getNonAtomic6432Opcode(Opc, HiOpc);
14714 unsigned cL = MRI.createVirtualRegister(RC8);
14715 unsigned cH = MRI.createVirtualRegister(RC8);
14716 unsigned cL32 = MRI.createVirtualRegister(RC);
14717 unsigned cH32 = MRI.createVirtualRegister(RC);
14718 unsigned cc = MRI.createVirtualRegister(RC);
14719 // cl := cmp src_lo, lo
14720 BuildMI(mainMBB, DL, TII->get(X86::CMP32rr))
14721 .addReg(SrcLoReg).addReg(t4L);
14722 BuildMI(mainMBB, DL, TII->get(LoOpc), cL);
14723 BuildMI(mainMBB, DL, TII->get(X86::MOVZX32rr8), cL32).addReg(cL);
14724 // ch := cmp src_hi, hi
14725 BuildMI(mainMBB, DL, TII->get(X86::CMP32rr))
14726 .addReg(SrcHiReg).addReg(t4H);
14727 BuildMI(mainMBB, DL, TII->get(HiOpc), cH);
14728 BuildMI(mainMBB, DL, TII->get(X86::MOVZX32rr8), cH32).addReg(cH);
14729 // cc := if (src_hi == hi) ? cl : ch;
14730 if (Subtarget->hasCMov()) {
14731 BuildMI(mainMBB, DL, TII->get(X86::CMOVE32rr), cc)
14732 .addReg(cH32).addReg(cL32);
14734 MIB = BuildMI(mainMBB, DL, TII->get(X86::CMOV_GR32), cc)
14735 .addReg(cH32).addReg(cL32)
14736 .addImm(X86::COND_E);
14737 mainMBB = EmitLoweredSelect(MIB, mainMBB);
14739 BuildMI(mainMBB, DL, TII->get(X86::TEST32rr)).addReg(cc).addReg(cc);
14740 if (Subtarget->hasCMov()) {
14741 BuildMI(mainMBB, DL, TII->get(X86::CMOVNE32rr), t2L)
14742 .addReg(SrcLoReg).addReg(t4L);
14743 BuildMI(mainMBB, DL, TII->get(X86::CMOVNE32rr), t2H)
14744 .addReg(SrcHiReg).addReg(t4H);
14746 MIB = BuildMI(mainMBB, DL, TII->get(X86::CMOV_GR32), t2L)
14747 .addReg(SrcLoReg).addReg(t4L)
14748 .addImm(X86::COND_NE);
14749 mainMBB = EmitLoweredSelect(MIB, mainMBB);
14750 // As the lowered CMOV won't clobber EFLAGS, we could reuse it for the
14751 // 2nd CMOV lowering.
14752 mainMBB->addLiveIn(X86::EFLAGS);
14753 MIB = BuildMI(mainMBB, DL, TII->get(X86::CMOV_GR32), t2H)
14754 .addReg(SrcHiReg).addReg(t4H)
14755 .addImm(X86::COND_NE);
14756 mainMBB = EmitLoweredSelect(MIB, mainMBB);
14757 // Replace the original PHI node as mainMBB is changed after CMOV
14759 BuildMI(*origMainMBB, PhiL, DL, TII->get(X86::PHI), t4L)
14760 .addReg(t1L).addMBB(thisMBB).addReg(t3L).addMBB(mainMBB);
14761 BuildMI(*origMainMBB, PhiH, DL, TII->get(X86::PHI), t4H)
14762 .addReg(t1H).addMBB(thisMBB).addReg(t3H).addMBB(mainMBB);
14763 PhiL->eraseFromParent();
14764 PhiH->eraseFromParent();
14768 case X86::ATOMSWAP6432: {
14770 unsigned LoOpc = getNonAtomic6432Opcode(Opc, HiOpc);
14771 BuildMI(mainMBB, DL, TII->get(LoOpc), t2L).addReg(SrcLoReg);
14772 BuildMI(mainMBB, DL, TII->get(HiOpc), t2H).addReg(SrcHiReg);
14777 // Copy EDX:EAX back from HiReg:LoReg
14778 BuildMI(mainMBB, DL, TII->get(TargetOpcode::COPY), X86::EAX).addReg(t4L);
14779 BuildMI(mainMBB, DL, TII->get(TargetOpcode::COPY), X86::EDX).addReg(t4H);
14780 // Copy ECX:EBX from t1H:t1L
14781 BuildMI(mainMBB, DL, TII->get(TargetOpcode::COPY), X86::EBX).addReg(t2L);
14782 BuildMI(mainMBB, DL, TII->get(TargetOpcode::COPY), X86::ECX).addReg(t2H);
14784 MIB = BuildMI(mainMBB, DL, TII->get(LCMPXCHGOpc));
14785 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
14786 MachineOperand NewMO = MI->getOperand(MemOpndSlot + i);
14788 NewMO.setIsKill(false);
14789 MIB.addOperand(NewMO);
14791 MIB.setMemRefs(MMOBegin, MMOEnd);
14793 // Copy EDX:EAX back to t3H:t3L
14794 BuildMI(mainMBB, DL, TII->get(TargetOpcode::COPY), t3L).addReg(X86::EAX);
14795 BuildMI(mainMBB, DL, TII->get(TargetOpcode::COPY), t3H).addReg(X86::EDX);
14797 BuildMI(mainMBB, DL, TII->get(X86::JNE_4)).addMBB(origMainMBB);
14799 mainMBB->addSuccessor(origMainMBB);
14800 mainMBB->addSuccessor(sinkMBB);
14803 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
14804 TII->get(TargetOpcode::COPY), DstLoReg)
14806 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
14807 TII->get(TargetOpcode::COPY), DstHiReg)
14810 MI->eraseFromParent();
14814 // FIXME: When we get size specific XMM0 registers, i.e. XMM0_V16I8
14815 // or XMM0_V32I8 in AVX all of this code can be replaced with that
14816 // in the .td file.
14817 static MachineBasicBlock *EmitPCMPSTRM(MachineInstr *MI, MachineBasicBlock *BB,
14818 const TargetInstrInfo *TII) {
14820 switch (MI->getOpcode()) {
14821 default: llvm_unreachable("illegal opcode!");
14822 case X86::PCMPISTRM128REG: Opc = X86::PCMPISTRM128rr; break;
14823 case X86::VPCMPISTRM128REG: Opc = X86::VPCMPISTRM128rr; break;
14824 case X86::PCMPISTRM128MEM: Opc = X86::PCMPISTRM128rm; break;
14825 case X86::VPCMPISTRM128MEM: Opc = X86::VPCMPISTRM128rm; break;
14826 case X86::PCMPESTRM128REG: Opc = X86::PCMPESTRM128rr; break;
14827 case X86::VPCMPESTRM128REG: Opc = X86::VPCMPESTRM128rr; break;
14828 case X86::PCMPESTRM128MEM: Opc = X86::PCMPESTRM128rm; break;
14829 case X86::VPCMPESTRM128MEM: Opc = X86::VPCMPESTRM128rm; break;
14832 DebugLoc dl = MI->getDebugLoc();
14833 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(Opc));
14835 unsigned NumArgs = MI->getNumOperands();
14836 for (unsigned i = 1; i < NumArgs; ++i) {
14837 MachineOperand &Op = MI->getOperand(i);
14838 if (!(Op.isReg() && Op.isImplicit()))
14839 MIB.addOperand(Op);
14841 if (MI->hasOneMemOperand())
14842 MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
14844 BuildMI(*BB, MI, dl,
14845 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
14846 .addReg(X86::XMM0);
14848 MI->eraseFromParent();
14852 // FIXME: Custom handling because TableGen doesn't support multiple implicit
14853 // defs in an instruction pattern
14854 static MachineBasicBlock *EmitPCMPSTRI(MachineInstr *MI, MachineBasicBlock *BB,
14855 const TargetInstrInfo *TII) {
14857 switch (MI->getOpcode()) {
14858 default: llvm_unreachable("illegal opcode!");
14859 case X86::PCMPISTRIREG: Opc = X86::PCMPISTRIrr; break;
14860 case X86::VPCMPISTRIREG: Opc = X86::VPCMPISTRIrr; break;
14861 case X86::PCMPISTRIMEM: Opc = X86::PCMPISTRIrm; break;
14862 case X86::VPCMPISTRIMEM: Opc = X86::VPCMPISTRIrm; break;
14863 case X86::PCMPESTRIREG: Opc = X86::PCMPESTRIrr; break;
14864 case X86::VPCMPESTRIREG: Opc = X86::VPCMPESTRIrr; break;
14865 case X86::PCMPESTRIMEM: Opc = X86::PCMPESTRIrm; break;
14866 case X86::VPCMPESTRIMEM: Opc = X86::VPCMPESTRIrm; break;
14869 DebugLoc dl = MI->getDebugLoc();
14870 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(Opc));
14872 unsigned NumArgs = MI->getNumOperands(); // remove the results
14873 for (unsigned i = 1; i < NumArgs; ++i) {
14874 MachineOperand &Op = MI->getOperand(i);
14875 if (!(Op.isReg() && Op.isImplicit()))
14876 MIB.addOperand(Op);
14878 if (MI->hasOneMemOperand())
14879 MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
14881 BuildMI(*BB, MI, dl,
14882 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
14885 MI->eraseFromParent();
14889 static MachineBasicBlock * EmitMonitor(MachineInstr *MI, MachineBasicBlock *BB,
14890 const TargetInstrInfo *TII,
14891 const X86Subtarget* Subtarget) {
14892 DebugLoc dl = MI->getDebugLoc();
14894 // Address into RAX/EAX, other two args into ECX, EDX.
14895 unsigned MemOpc = Subtarget->is64Bit() ? X86::LEA64r : X86::LEA32r;
14896 unsigned MemReg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
14897 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(MemOpc), MemReg);
14898 for (int i = 0; i < X86::AddrNumOperands; ++i)
14899 MIB.addOperand(MI->getOperand(i));
14901 unsigned ValOps = X86::AddrNumOperands;
14902 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::ECX)
14903 .addReg(MI->getOperand(ValOps).getReg());
14904 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::EDX)
14905 .addReg(MI->getOperand(ValOps+1).getReg());
14907 // The instruction doesn't actually take any operands though.
14908 BuildMI(*BB, MI, dl, TII->get(X86::MONITORrrr));
14910 MI->eraseFromParent(); // The pseudo is gone now.
14914 MachineBasicBlock *
14915 X86TargetLowering::EmitVAARG64WithCustomInserter(
14917 MachineBasicBlock *MBB) const {
14918 // Emit va_arg instruction on X86-64.
14920 // Operands to this pseudo-instruction:
14921 // 0 ) Output : destination address (reg)
14922 // 1-5) Input : va_list address (addr, i64mem)
14923 // 6 ) ArgSize : Size (in bytes) of vararg type
14924 // 7 ) ArgMode : 0=overflow only, 1=use gp_offset, 2=use fp_offset
14925 // 8 ) Align : Alignment of type
14926 // 9 ) EFLAGS (implicit-def)
14928 assert(MI->getNumOperands() == 10 && "VAARG_64 should have 10 operands!");
14929 assert(X86::AddrNumOperands == 5 && "VAARG_64 assumes 5 address operands");
14931 unsigned DestReg = MI->getOperand(0).getReg();
14932 MachineOperand &Base = MI->getOperand(1);
14933 MachineOperand &Scale = MI->getOperand(2);
14934 MachineOperand &Index = MI->getOperand(3);
14935 MachineOperand &Disp = MI->getOperand(4);
14936 MachineOperand &Segment = MI->getOperand(5);
14937 unsigned ArgSize = MI->getOperand(6).getImm();
14938 unsigned ArgMode = MI->getOperand(7).getImm();
14939 unsigned Align = MI->getOperand(8).getImm();
14941 // Memory Reference
14942 assert(MI->hasOneMemOperand() && "Expected VAARG_64 to have one memoperand");
14943 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
14944 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
14946 // Machine Information
14947 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
14948 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
14949 const TargetRegisterClass *AddrRegClass = getRegClassFor(MVT::i64);
14950 const TargetRegisterClass *OffsetRegClass = getRegClassFor(MVT::i32);
14951 DebugLoc DL = MI->getDebugLoc();
14953 // struct va_list {
14956 // i64 overflow_area (address)
14957 // i64 reg_save_area (address)
14959 // sizeof(va_list) = 24
14960 // alignment(va_list) = 8
14962 unsigned TotalNumIntRegs = 6;
14963 unsigned TotalNumXMMRegs = 8;
14964 bool UseGPOffset = (ArgMode == 1);
14965 bool UseFPOffset = (ArgMode == 2);
14966 unsigned MaxOffset = TotalNumIntRegs * 8 +
14967 (UseFPOffset ? TotalNumXMMRegs * 16 : 0);
14969 /* Align ArgSize to a multiple of 8 */
14970 unsigned ArgSizeA8 = (ArgSize + 7) & ~7;
14971 bool NeedsAlign = (Align > 8);
14973 MachineBasicBlock *thisMBB = MBB;
14974 MachineBasicBlock *overflowMBB;
14975 MachineBasicBlock *offsetMBB;
14976 MachineBasicBlock *endMBB;
14978 unsigned OffsetDestReg = 0; // Argument address computed by offsetMBB
14979 unsigned OverflowDestReg = 0; // Argument address computed by overflowMBB
14980 unsigned OffsetReg = 0;
14982 if (!UseGPOffset && !UseFPOffset) {
14983 // If we only pull from the overflow region, we don't create a branch.
14984 // We don't need to alter control flow.
14985 OffsetDestReg = 0; // unused
14986 OverflowDestReg = DestReg;
14989 overflowMBB = thisMBB;
14992 // First emit code to check if gp_offset (or fp_offset) is below the bound.
14993 // If so, pull the argument from reg_save_area. (branch to offsetMBB)
14994 // If not, pull from overflow_area. (branch to overflowMBB)
14999 // offsetMBB overflowMBB
15004 // Registers for the PHI in endMBB
15005 OffsetDestReg = MRI.createVirtualRegister(AddrRegClass);
15006 OverflowDestReg = MRI.createVirtualRegister(AddrRegClass);
15008 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
15009 MachineFunction *MF = MBB->getParent();
15010 overflowMBB = MF->CreateMachineBasicBlock(LLVM_BB);
15011 offsetMBB = MF->CreateMachineBasicBlock(LLVM_BB);
15012 endMBB = MF->CreateMachineBasicBlock(LLVM_BB);
15014 MachineFunction::iterator MBBIter = MBB;
15017 // Insert the new basic blocks
15018 MF->insert(MBBIter, offsetMBB);
15019 MF->insert(MBBIter, overflowMBB);
15020 MF->insert(MBBIter, endMBB);
15022 // Transfer the remainder of MBB and its successor edges to endMBB.
15023 endMBB->splice(endMBB->begin(), thisMBB,
15024 llvm::next(MachineBasicBlock::iterator(MI)),
15026 endMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
15028 // Make offsetMBB and overflowMBB successors of thisMBB
15029 thisMBB->addSuccessor(offsetMBB);
15030 thisMBB->addSuccessor(overflowMBB);
15032 // endMBB is a successor of both offsetMBB and overflowMBB
15033 offsetMBB->addSuccessor(endMBB);
15034 overflowMBB->addSuccessor(endMBB);
15036 // Load the offset value into a register
15037 OffsetReg = MRI.createVirtualRegister(OffsetRegClass);
15038 BuildMI(thisMBB, DL, TII->get(X86::MOV32rm), OffsetReg)
15042 .addDisp(Disp, UseFPOffset ? 4 : 0)
15043 .addOperand(Segment)
15044 .setMemRefs(MMOBegin, MMOEnd);
15046 // Check if there is enough room left to pull this argument.
15047 BuildMI(thisMBB, DL, TII->get(X86::CMP32ri))
15049 .addImm(MaxOffset + 8 - ArgSizeA8);
15051 // Branch to "overflowMBB" if offset >= max
15052 // Fall through to "offsetMBB" otherwise
15053 BuildMI(thisMBB, DL, TII->get(X86::GetCondBranchFromCond(X86::COND_AE)))
15054 .addMBB(overflowMBB);
15057 // In offsetMBB, emit code to use the reg_save_area.
15059 assert(OffsetReg != 0);
15061 // Read the reg_save_area address.
15062 unsigned RegSaveReg = MRI.createVirtualRegister(AddrRegClass);
15063 BuildMI(offsetMBB, DL, TII->get(X86::MOV64rm), RegSaveReg)
15068 .addOperand(Segment)
15069 .setMemRefs(MMOBegin, MMOEnd);
15071 // Zero-extend the offset
15072 unsigned OffsetReg64 = MRI.createVirtualRegister(AddrRegClass);
15073 BuildMI(offsetMBB, DL, TII->get(X86::SUBREG_TO_REG), OffsetReg64)
15076 .addImm(X86::sub_32bit);
15078 // Add the offset to the reg_save_area to get the final address.
15079 BuildMI(offsetMBB, DL, TII->get(X86::ADD64rr), OffsetDestReg)
15080 .addReg(OffsetReg64)
15081 .addReg(RegSaveReg);
15083 // Compute the offset for the next argument
15084 unsigned NextOffsetReg = MRI.createVirtualRegister(OffsetRegClass);
15085 BuildMI(offsetMBB, DL, TII->get(X86::ADD32ri), NextOffsetReg)
15087 .addImm(UseFPOffset ? 16 : 8);
15089 // Store it back into the va_list.
15090 BuildMI(offsetMBB, DL, TII->get(X86::MOV32mr))
15094 .addDisp(Disp, UseFPOffset ? 4 : 0)
15095 .addOperand(Segment)
15096 .addReg(NextOffsetReg)
15097 .setMemRefs(MMOBegin, MMOEnd);
15100 BuildMI(offsetMBB, DL, TII->get(X86::JMP_4))
15105 // Emit code to use overflow area
15108 // Load the overflow_area address into a register.
15109 unsigned OverflowAddrReg = MRI.createVirtualRegister(AddrRegClass);
15110 BuildMI(overflowMBB, DL, TII->get(X86::MOV64rm), OverflowAddrReg)
15115 .addOperand(Segment)
15116 .setMemRefs(MMOBegin, MMOEnd);
15118 // If we need to align it, do so. Otherwise, just copy the address
15119 // to OverflowDestReg.
15121 // Align the overflow address
15122 assert((Align & (Align-1)) == 0 && "Alignment must be a power of 2");
15123 unsigned TmpReg = MRI.createVirtualRegister(AddrRegClass);
15125 // aligned_addr = (addr + (align-1)) & ~(align-1)
15126 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), TmpReg)
15127 .addReg(OverflowAddrReg)
15130 BuildMI(overflowMBB, DL, TII->get(X86::AND64ri32), OverflowDestReg)
15132 .addImm(~(uint64_t)(Align-1));
15134 BuildMI(overflowMBB, DL, TII->get(TargetOpcode::COPY), OverflowDestReg)
15135 .addReg(OverflowAddrReg);
15138 // Compute the next overflow address after this argument.
15139 // (the overflow address should be kept 8-byte aligned)
15140 unsigned NextAddrReg = MRI.createVirtualRegister(AddrRegClass);
15141 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), NextAddrReg)
15142 .addReg(OverflowDestReg)
15143 .addImm(ArgSizeA8);
15145 // Store the new overflow address.
15146 BuildMI(overflowMBB, DL, TII->get(X86::MOV64mr))
15151 .addOperand(Segment)
15152 .addReg(NextAddrReg)
15153 .setMemRefs(MMOBegin, MMOEnd);
15155 // If we branched, emit the PHI to the front of endMBB.
15157 BuildMI(*endMBB, endMBB->begin(), DL,
15158 TII->get(X86::PHI), DestReg)
15159 .addReg(OffsetDestReg).addMBB(offsetMBB)
15160 .addReg(OverflowDestReg).addMBB(overflowMBB);
15163 // Erase the pseudo instruction
15164 MI->eraseFromParent();
15169 MachineBasicBlock *
15170 X86TargetLowering::EmitVAStartSaveXMMRegsWithCustomInserter(
15172 MachineBasicBlock *MBB) const {
15173 // Emit code to save XMM registers to the stack. The ABI says that the
15174 // number of registers to save is given in %al, so it's theoretically
15175 // possible to do an indirect jump trick to avoid saving all of them,
15176 // however this code takes a simpler approach and just executes all
15177 // of the stores if %al is non-zero. It's less code, and it's probably
15178 // easier on the hardware branch predictor, and stores aren't all that
15179 // expensive anyway.
15181 // Create the new basic blocks. One block contains all the XMM stores,
15182 // and one block is the final destination regardless of whether any
15183 // stores were performed.
15184 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
15185 MachineFunction *F = MBB->getParent();
15186 MachineFunction::iterator MBBIter = MBB;
15188 MachineBasicBlock *XMMSaveMBB = F->CreateMachineBasicBlock(LLVM_BB);
15189 MachineBasicBlock *EndMBB = F->CreateMachineBasicBlock(LLVM_BB);
15190 F->insert(MBBIter, XMMSaveMBB);
15191 F->insert(MBBIter, EndMBB);
15193 // Transfer the remainder of MBB and its successor edges to EndMBB.
15194 EndMBB->splice(EndMBB->begin(), MBB,
15195 llvm::next(MachineBasicBlock::iterator(MI)),
15197 EndMBB->transferSuccessorsAndUpdatePHIs(MBB);
15199 // The original block will now fall through to the XMM save block.
15200 MBB->addSuccessor(XMMSaveMBB);
15201 // The XMMSaveMBB will fall through to the end block.
15202 XMMSaveMBB->addSuccessor(EndMBB);
15204 // Now add the instructions.
15205 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
15206 DebugLoc DL = MI->getDebugLoc();
15208 unsigned CountReg = MI->getOperand(0).getReg();
15209 int64_t RegSaveFrameIndex = MI->getOperand(1).getImm();
15210 int64_t VarArgsFPOffset = MI->getOperand(2).getImm();
15212 if (!Subtarget->isTargetWin64()) {
15213 // If %al is 0, branch around the XMM save block.
15214 BuildMI(MBB, DL, TII->get(X86::TEST8rr)).addReg(CountReg).addReg(CountReg);
15215 BuildMI(MBB, DL, TII->get(X86::JE_4)).addMBB(EndMBB);
15216 MBB->addSuccessor(EndMBB);
15219 unsigned MOVOpc = Subtarget->hasFp256() ? X86::VMOVAPSmr : X86::MOVAPSmr;
15220 // In the XMM save block, save all the XMM argument registers.
15221 for (int i = 3, e = MI->getNumOperands(); i != e; ++i) {
15222 int64_t Offset = (i - 3) * 16 + VarArgsFPOffset;
15223 MachineMemOperand *MMO =
15224 F->getMachineMemOperand(
15225 MachinePointerInfo::getFixedStack(RegSaveFrameIndex, Offset),
15226 MachineMemOperand::MOStore,
15227 /*Size=*/16, /*Align=*/16);
15228 BuildMI(XMMSaveMBB, DL, TII->get(MOVOpc))
15229 .addFrameIndex(RegSaveFrameIndex)
15230 .addImm(/*Scale=*/1)
15231 .addReg(/*IndexReg=*/0)
15232 .addImm(/*Disp=*/Offset)
15233 .addReg(/*Segment=*/0)
15234 .addReg(MI->getOperand(i).getReg())
15235 .addMemOperand(MMO);
15238 MI->eraseFromParent(); // The pseudo instruction is gone now.
15243 // The EFLAGS operand of SelectItr might be missing a kill marker
15244 // because there were multiple uses of EFLAGS, and ISel didn't know
15245 // which to mark. Figure out whether SelectItr should have had a
15246 // kill marker, and set it if it should. Returns the correct kill
15248 static bool checkAndUpdateEFLAGSKill(MachineBasicBlock::iterator SelectItr,
15249 MachineBasicBlock* BB,
15250 const TargetRegisterInfo* TRI) {
15251 // Scan forward through BB for a use/def of EFLAGS.
15252 MachineBasicBlock::iterator miI(llvm::next(SelectItr));
15253 for (MachineBasicBlock::iterator miE = BB->end(); miI != miE; ++miI) {
15254 const MachineInstr& mi = *miI;
15255 if (mi.readsRegister(X86::EFLAGS))
15257 if (mi.definesRegister(X86::EFLAGS))
15258 break; // Should have kill-flag - update below.
15261 // If we hit the end of the block, check whether EFLAGS is live into a
15263 if (miI == BB->end()) {
15264 for (MachineBasicBlock::succ_iterator sItr = BB->succ_begin(),
15265 sEnd = BB->succ_end();
15266 sItr != sEnd; ++sItr) {
15267 MachineBasicBlock* succ = *sItr;
15268 if (succ->isLiveIn(X86::EFLAGS))
15273 // We found a def, or hit the end of the basic block and EFLAGS wasn't live
15274 // out. SelectMI should have a kill flag on EFLAGS.
15275 SelectItr->addRegisterKilled(X86::EFLAGS, TRI);
15279 MachineBasicBlock *
15280 X86TargetLowering::EmitLoweredSelect(MachineInstr *MI,
15281 MachineBasicBlock *BB) const {
15282 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
15283 DebugLoc DL = MI->getDebugLoc();
15285 // To "insert" a SELECT_CC instruction, we actually have to insert the
15286 // diamond control-flow pattern. The incoming instruction knows the
15287 // destination vreg to set, the condition code register to branch on, the
15288 // true/false values to select between, and a branch opcode to use.
15289 const BasicBlock *LLVM_BB = BB->getBasicBlock();
15290 MachineFunction::iterator It = BB;
15296 // cmpTY ccX, r1, r2
15298 // fallthrough --> copy0MBB
15299 MachineBasicBlock *thisMBB = BB;
15300 MachineFunction *F = BB->getParent();
15301 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
15302 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
15303 F->insert(It, copy0MBB);
15304 F->insert(It, sinkMBB);
15306 // If the EFLAGS register isn't dead in the terminator, then claim that it's
15307 // live into the sink and copy blocks.
15308 const TargetRegisterInfo* TRI = getTargetMachine().getRegisterInfo();
15309 if (!MI->killsRegister(X86::EFLAGS) &&
15310 !checkAndUpdateEFLAGSKill(MI, BB, TRI)) {
15311 copy0MBB->addLiveIn(X86::EFLAGS);
15312 sinkMBB->addLiveIn(X86::EFLAGS);
15315 // Transfer the remainder of BB and its successor edges to sinkMBB.
15316 sinkMBB->splice(sinkMBB->begin(), BB,
15317 llvm::next(MachineBasicBlock::iterator(MI)),
15319 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
15321 // Add the true and fallthrough blocks as its successors.
15322 BB->addSuccessor(copy0MBB);
15323 BB->addSuccessor(sinkMBB);
15325 // Create the conditional branch instruction.
15327 X86::GetCondBranchFromCond((X86::CondCode)MI->getOperand(3).getImm());
15328 BuildMI(BB, DL, TII->get(Opc)).addMBB(sinkMBB);
15331 // %FalseValue = ...
15332 // # fallthrough to sinkMBB
15333 copy0MBB->addSuccessor(sinkMBB);
15336 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
15338 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
15339 TII->get(X86::PHI), MI->getOperand(0).getReg())
15340 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB)
15341 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
15343 MI->eraseFromParent(); // The pseudo instruction is gone now.
15347 MachineBasicBlock *
15348 X86TargetLowering::EmitLoweredSegAlloca(MachineInstr *MI, MachineBasicBlock *BB,
15349 bool Is64Bit) const {
15350 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
15351 DebugLoc DL = MI->getDebugLoc();
15352 MachineFunction *MF = BB->getParent();
15353 const BasicBlock *LLVM_BB = BB->getBasicBlock();
15355 assert(getTargetMachine().Options.EnableSegmentedStacks);
15357 unsigned TlsReg = Is64Bit ? X86::FS : X86::GS;
15358 unsigned TlsOffset = Is64Bit ? 0x70 : 0x30;
15361 // ... [Till the alloca]
15362 // If stacklet is not large enough, jump to mallocMBB
15365 // Allocate by subtracting from RSP
15366 // Jump to continueMBB
15369 // Allocate by call to runtime
15373 // [rest of original BB]
15376 MachineBasicBlock *mallocMBB = MF->CreateMachineBasicBlock(LLVM_BB);
15377 MachineBasicBlock *bumpMBB = MF->CreateMachineBasicBlock(LLVM_BB);
15378 MachineBasicBlock *continueMBB = MF->CreateMachineBasicBlock(LLVM_BB);
15380 MachineRegisterInfo &MRI = MF->getRegInfo();
15381 const TargetRegisterClass *AddrRegClass =
15382 getRegClassFor(Is64Bit ? MVT::i64:MVT::i32);
15384 unsigned mallocPtrVReg = MRI.createVirtualRegister(AddrRegClass),
15385 bumpSPPtrVReg = MRI.createVirtualRegister(AddrRegClass),
15386 tmpSPVReg = MRI.createVirtualRegister(AddrRegClass),
15387 SPLimitVReg = MRI.createVirtualRegister(AddrRegClass),
15388 sizeVReg = MI->getOperand(1).getReg(),
15389 physSPReg = Is64Bit ? X86::RSP : X86::ESP;
15391 MachineFunction::iterator MBBIter = BB;
15394 MF->insert(MBBIter, bumpMBB);
15395 MF->insert(MBBIter, mallocMBB);
15396 MF->insert(MBBIter, continueMBB);
15398 continueMBB->splice(continueMBB->begin(), BB, llvm::next
15399 (MachineBasicBlock::iterator(MI)), BB->end());
15400 continueMBB->transferSuccessorsAndUpdatePHIs(BB);
15402 // Add code to the main basic block to check if the stack limit has been hit,
15403 // and if so, jump to mallocMBB otherwise to bumpMBB.
15404 BuildMI(BB, DL, TII->get(TargetOpcode::COPY), tmpSPVReg).addReg(physSPReg);
15405 BuildMI(BB, DL, TII->get(Is64Bit ? X86::SUB64rr:X86::SUB32rr), SPLimitVReg)
15406 .addReg(tmpSPVReg).addReg(sizeVReg);
15407 BuildMI(BB, DL, TII->get(Is64Bit ? X86::CMP64mr:X86::CMP32mr))
15408 .addReg(0).addImm(1).addReg(0).addImm(TlsOffset).addReg(TlsReg)
15409 .addReg(SPLimitVReg);
15410 BuildMI(BB, DL, TII->get(X86::JG_4)).addMBB(mallocMBB);
15412 // bumpMBB simply decreases the stack pointer, since we know the current
15413 // stacklet has enough space.
15414 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), physSPReg)
15415 .addReg(SPLimitVReg);
15416 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), bumpSPPtrVReg)
15417 .addReg(SPLimitVReg);
15418 BuildMI(bumpMBB, DL, TII->get(X86::JMP_4)).addMBB(continueMBB);
15420 // Calls into a routine in libgcc to allocate more space from the heap.
15421 const uint32_t *RegMask =
15422 getTargetMachine().getRegisterInfo()->getCallPreservedMask(CallingConv::C);
15424 BuildMI(mallocMBB, DL, TII->get(X86::MOV64rr), X86::RDI)
15426 BuildMI(mallocMBB, DL, TII->get(X86::CALL64pcrel32))
15427 .addExternalSymbol("__morestack_allocate_stack_space")
15428 .addRegMask(RegMask)
15429 .addReg(X86::RDI, RegState::Implicit)
15430 .addReg(X86::RAX, RegState::ImplicitDefine);
15432 BuildMI(mallocMBB, DL, TII->get(X86::SUB32ri), physSPReg).addReg(physSPReg)
15434 BuildMI(mallocMBB, DL, TII->get(X86::PUSH32r)).addReg(sizeVReg);
15435 BuildMI(mallocMBB, DL, TII->get(X86::CALLpcrel32))
15436 .addExternalSymbol("__morestack_allocate_stack_space")
15437 .addRegMask(RegMask)
15438 .addReg(X86::EAX, RegState::ImplicitDefine);
15442 BuildMI(mallocMBB, DL, TII->get(X86::ADD32ri), physSPReg).addReg(physSPReg)
15445 BuildMI(mallocMBB, DL, TII->get(TargetOpcode::COPY), mallocPtrVReg)
15446 .addReg(Is64Bit ? X86::RAX : X86::EAX);
15447 BuildMI(mallocMBB, DL, TII->get(X86::JMP_4)).addMBB(continueMBB);
15449 // Set up the CFG correctly.
15450 BB->addSuccessor(bumpMBB);
15451 BB->addSuccessor(mallocMBB);
15452 mallocMBB->addSuccessor(continueMBB);
15453 bumpMBB->addSuccessor(continueMBB);
15455 // Take care of the PHI nodes.
15456 BuildMI(*continueMBB, continueMBB->begin(), DL, TII->get(X86::PHI),
15457 MI->getOperand(0).getReg())
15458 .addReg(mallocPtrVReg).addMBB(mallocMBB)
15459 .addReg(bumpSPPtrVReg).addMBB(bumpMBB);
15461 // Delete the original pseudo instruction.
15462 MI->eraseFromParent();
15465 return continueMBB;
15468 MachineBasicBlock *
15469 X86TargetLowering::EmitLoweredWinAlloca(MachineInstr *MI,
15470 MachineBasicBlock *BB) const {
15471 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
15472 DebugLoc DL = MI->getDebugLoc();
15474 assert(!Subtarget->isTargetEnvMacho());
15476 // The lowering is pretty easy: we're just emitting the call to _alloca. The
15477 // non-trivial part is impdef of ESP.
15479 if (Subtarget->isTargetWin64()) {
15480 if (Subtarget->isTargetCygMing()) {
15481 // ___chkstk(Mingw64):
15482 // Clobbers R10, R11, RAX and EFLAGS.
15484 BuildMI(*BB, MI, DL, TII->get(X86::W64ALLOCA))
15485 .addExternalSymbol("___chkstk")
15486 .addReg(X86::RAX, RegState::Implicit)
15487 .addReg(X86::RSP, RegState::Implicit)
15488 .addReg(X86::RAX, RegState::Define | RegState::Implicit)
15489 .addReg(X86::RSP, RegState::Define | RegState::Implicit)
15490 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
15492 // __chkstk(MSVCRT): does not update stack pointer.
15493 // Clobbers R10, R11 and EFLAGS.
15494 BuildMI(*BB, MI, DL, TII->get(X86::W64ALLOCA))
15495 .addExternalSymbol("__chkstk")
15496 .addReg(X86::RAX, RegState::Implicit)
15497 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
15498 // RAX has the offset to be subtracted from RSP.
15499 BuildMI(*BB, MI, DL, TII->get(X86::SUB64rr), X86::RSP)
15504 const char *StackProbeSymbol =
15505 Subtarget->isTargetWindows() ? "_chkstk" : "_alloca";
15507 BuildMI(*BB, MI, DL, TII->get(X86::CALLpcrel32))
15508 .addExternalSymbol(StackProbeSymbol)
15509 .addReg(X86::EAX, RegState::Implicit)
15510 .addReg(X86::ESP, RegState::Implicit)
15511 .addReg(X86::EAX, RegState::Define | RegState::Implicit)
15512 .addReg(X86::ESP, RegState::Define | RegState::Implicit)
15513 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
15516 MI->eraseFromParent(); // The pseudo instruction is gone now.
15520 MachineBasicBlock *
15521 X86TargetLowering::EmitLoweredTLSCall(MachineInstr *MI,
15522 MachineBasicBlock *BB) const {
15523 // This is pretty easy. We're taking the value that we received from
15524 // our load from the relocation, sticking it in either RDI (x86-64)
15525 // or EAX and doing an indirect call. The return value will then
15526 // be in the normal return register.
15527 const X86InstrInfo *TII
15528 = static_cast<const X86InstrInfo*>(getTargetMachine().getInstrInfo());
15529 DebugLoc DL = MI->getDebugLoc();
15530 MachineFunction *F = BB->getParent();
15532 assert(Subtarget->isTargetDarwin() && "Darwin only instr emitted?");
15533 assert(MI->getOperand(3).isGlobal() && "This should be a global");
15535 // Get a register mask for the lowered call.
15536 // FIXME: The 32-bit calls have non-standard calling conventions. Use a
15537 // proper register mask.
15538 const uint32_t *RegMask =
15539 getTargetMachine().getRegisterInfo()->getCallPreservedMask(CallingConv::C);
15540 if (Subtarget->is64Bit()) {
15541 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
15542 TII->get(X86::MOV64rm), X86::RDI)
15544 .addImm(0).addReg(0)
15545 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
15546 MI->getOperand(3).getTargetFlags())
15548 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL64m));
15549 addDirectMem(MIB, X86::RDI);
15550 MIB.addReg(X86::RAX, RegState::ImplicitDefine).addRegMask(RegMask);
15551 } else if (getTargetMachine().getRelocationModel() != Reloc::PIC_) {
15552 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
15553 TII->get(X86::MOV32rm), X86::EAX)
15555 .addImm(0).addReg(0)
15556 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
15557 MI->getOperand(3).getTargetFlags())
15559 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
15560 addDirectMem(MIB, X86::EAX);
15561 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask);
15563 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
15564 TII->get(X86::MOV32rm), X86::EAX)
15565 .addReg(TII->getGlobalBaseReg(F))
15566 .addImm(0).addReg(0)
15567 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
15568 MI->getOperand(3).getTargetFlags())
15570 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
15571 addDirectMem(MIB, X86::EAX);
15572 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask);
15575 MI->eraseFromParent(); // The pseudo instruction is gone now.
15579 MachineBasicBlock *
15580 X86TargetLowering::emitEHSjLjSetJmp(MachineInstr *MI,
15581 MachineBasicBlock *MBB) const {
15582 DebugLoc DL = MI->getDebugLoc();
15583 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
15585 MachineFunction *MF = MBB->getParent();
15586 MachineRegisterInfo &MRI = MF->getRegInfo();
15588 const BasicBlock *BB = MBB->getBasicBlock();
15589 MachineFunction::iterator I = MBB;
15592 // Memory Reference
15593 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
15594 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
15597 unsigned MemOpndSlot = 0;
15599 unsigned CurOp = 0;
15601 DstReg = MI->getOperand(CurOp++).getReg();
15602 const TargetRegisterClass *RC = MRI.getRegClass(DstReg);
15603 assert(RC->hasType(MVT::i32) && "Invalid destination!");
15604 unsigned mainDstReg = MRI.createVirtualRegister(RC);
15605 unsigned restoreDstReg = MRI.createVirtualRegister(RC);
15607 MemOpndSlot = CurOp;
15609 MVT PVT = getPointerTy();
15610 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
15611 "Invalid Pointer Size!");
15613 // For v = setjmp(buf), we generate
15616 // buf[LabelOffset] = restoreMBB
15617 // SjLjSetup restoreMBB
15623 // v = phi(main, restore)
15628 MachineBasicBlock *thisMBB = MBB;
15629 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
15630 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
15631 MachineBasicBlock *restoreMBB = MF->CreateMachineBasicBlock(BB);
15632 MF->insert(I, mainMBB);
15633 MF->insert(I, sinkMBB);
15634 MF->push_back(restoreMBB);
15636 MachineInstrBuilder MIB;
15638 // Transfer the remainder of BB and its successor edges to sinkMBB.
15639 sinkMBB->splice(sinkMBB->begin(), MBB,
15640 llvm::next(MachineBasicBlock::iterator(MI)), MBB->end());
15641 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
15644 unsigned PtrStoreOpc = 0;
15645 unsigned LabelReg = 0;
15646 const int64_t LabelOffset = 1 * PVT.getStoreSize();
15647 Reloc::Model RM = getTargetMachine().getRelocationModel();
15648 bool UseImmLabel = (getTargetMachine().getCodeModel() == CodeModel::Small) &&
15649 (RM == Reloc::Static || RM == Reloc::DynamicNoPIC);
15651 // Prepare IP either in reg or imm.
15652 if (!UseImmLabel) {
15653 PtrStoreOpc = (PVT == MVT::i64) ? X86::MOV64mr : X86::MOV32mr;
15654 const TargetRegisterClass *PtrRC = getRegClassFor(PVT);
15655 LabelReg = MRI.createVirtualRegister(PtrRC);
15656 if (Subtarget->is64Bit()) {
15657 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::LEA64r), LabelReg)
15661 .addMBB(restoreMBB)
15664 const X86InstrInfo *XII = static_cast<const X86InstrInfo*>(TII);
15665 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::LEA32r), LabelReg)
15666 .addReg(XII->getGlobalBaseReg(MF))
15669 .addMBB(restoreMBB, Subtarget->ClassifyBlockAddressReference())
15673 PtrStoreOpc = (PVT == MVT::i64) ? X86::MOV64mi32 : X86::MOV32mi;
15675 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PtrStoreOpc));
15676 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
15677 if (i == X86::AddrDisp)
15678 MIB.addDisp(MI->getOperand(MemOpndSlot + i), LabelOffset);
15680 MIB.addOperand(MI->getOperand(MemOpndSlot + i));
15683 MIB.addReg(LabelReg);
15685 MIB.addMBB(restoreMBB);
15686 MIB.setMemRefs(MMOBegin, MMOEnd);
15688 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::EH_SjLj_Setup))
15689 .addMBB(restoreMBB);
15691 const X86RegisterInfo *RegInfo =
15692 static_cast<const X86RegisterInfo*>(getTargetMachine().getRegisterInfo());
15693 MIB.addRegMask(RegInfo->getNoPreservedMask());
15694 thisMBB->addSuccessor(mainMBB);
15695 thisMBB->addSuccessor(restoreMBB);
15699 BuildMI(mainMBB, DL, TII->get(X86::MOV32r0), mainDstReg);
15700 mainMBB->addSuccessor(sinkMBB);
15703 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
15704 TII->get(X86::PHI), DstReg)
15705 .addReg(mainDstReg).addMBB(mainMBB)
15706 .addReg(restoreDstReg).addMBB(restoreMBB);
15709 BuildMI(restoreMBB, DL, TII->get(X86::MOV32ri), restoreDstReg).addImm(1);
15710 BuildMI(restoreMBB, DL, TII->get(X86::JMP_4)).addMBB(sinkMBB);
15711 restoreMBB->addSuccessor(sinkMBB);
15713 MI->eraseFromParent();
15717 MachineBasicBlock *
15718 X86TargetLowering::emitEHSjLjLongJmp(MachineInstr *MI,
15719 MachineBasicBlock *MBB) const {
15720 DebugLoc DL = MI->getDebugLoc();
15721 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
15723 MachineFunction *MF = MBB->getParent();
15724 MachineRegisterInfo &MRI = MF->getRegInfo();
15726 // Memory Reference
15727 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
15728 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
15730 MVT PVT = getPointerTy();
15731 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
15732 "Invalid Pointer Size!");
15734 const TargetRegisterClass *RC =
15735 (PVT == MVT::i64) ? &X86::GR64RegClass : &X86::GR32RegClass;
15736 unsigned Tmp = MRI.createVirtualRegister(RC);
15737 // Since FP is only updated here but NOT referenced, it's treated as GPR.
15738 const X86RegisterInfo *RegInfo =
15739 static_cast<const X86RegisterInfo*>(getTargetMachine().getRegisterInfo());
15740 unsigned FP = (PVT == MVT::i64) ? X86::RBP : X86::EBP;
15741 unsigned SP = RegInfo->getStackRegister();
15743 MachineInstrBuilder MIB;
15745 const int64_t LabelOffset = 1 * PVT.getStoreSize();
15746 const int64_t SPOffset = 2 * PVT.getStoreSize();
15748 unsigned PtrLoadOpc = (PVT == MVT::i64) ? X86::MOV64rm : X86::MOV32rm;
15749 unsigned IJmpOpc = (PVT == MVT::i64) ? X86::JMP64r : X86::JMP32r;
15752 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), FP);
15753 for (unsigned i = 0; i < X86::AddrNumOperands; ++i)
15754 MIB.addOperand(MI->getOperand(i));
15755 MIB.setMemRefs(MMOBegin, MMOEnd);
15757 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), Tmp);
15758 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
15759 if (i == X86::AddrDisp)
15760 MIB.addDisp(MI->getOperand(i), LabelOffset);
15762 MIB.addOperand(MI->getOperand(i));
15764 MIB.setMemRefs(MMOBegin, MMOEnd);
15766 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), SP);
15767 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
15768 if (i == X86::AddrDisp)
15769 MIB.addDisp(MI->getOperand(i), SPOffset);
15771 MIB.addOperand(MI->getOperand(i));
15773 MIB.setMemRefs(MMOBegin, MMOEnd);
15775 BuildMI(*MBB, MI, DL, TII->get(IJmpOpc)).addReg(Tmp);
15777 MI->eraseFromParent();
15781 MachineBasicBlock *
15782 X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
15783 MachineBasicBlock *BB) const {
15784 switch (MI->getOpcode()) {
15785 default: llvm_unreachable("Unexpected instr type to insert");
15786 case X86::TAILJMPd64:
15787 case X86::TAILJMPr64:
15788 case X86::TAILJMPm64:
15789 llvm_unreachable("TAILJMP64 would not be touched here.");
15790 case X86::TCRETURNdi64:
15791 case X86::TCRETURNri64:
15792 case X86::TCRETURNmi64:
15794 case X86::WIN_ALLOCA:
15795 return EmitLoweredWinAlloca(MI, BB);
15796 case X86::SEG_ALLOCA_32:
15797 return EmitLoweredSegAlloca(MI, BB, false);
15798 case X86::SEG_ALLOCA_64:
15799 return EmitLoweredSegAlloca(MI, BB, true);
15800 case X86::TLSCall_32:
15801 case X86::TLSCall_64:
15802 return EmitLoweredTLSCall(MI, BB);
15803 case X86::CMOV_GR8:
15804 case X86::CMOV_FR32:
15805 case X86::CMOV_FR64:
15806 case X86::CMOV_V4F32:
15807 case X86::CMOV_V2F64:
15808 case X86::CMOV_V2I64:
15809 case X86::CMOV_V8F32:
15810 case X86::CMOV_V4F64:
15811 case X86::CMOV_V4I64:
15812 case X86::CMOV_V16F32:
15813 case X86::CMOV_V8F64:
15814 case X86::CMOV_V8I64:
15815 case X86::CMOV_GR16:
15816 case X86::CMOV_GR32:
15817 case X86::CMOV_RFP32:
15818 case X86::CMOV_RFP64:
15819 case X86::CMOV_RFP80:
15820 return EmitLoweredSelect(MI, BB);
15822 case X86::FP32_TO_INT16_IN_MEM:
15823 case X86::FP32_TO_INT32_IN_MEM:
15824 case X86::FP32_TO_INT64_IN_MEM:
15825 case X86::FP64_TO_INT16_IN_MEM:
15826 case X86::FP64_TO_INT32_IN_MEM:
15827 case X86::FP64_TO_INT64_IN_MEM:
15828 case X86::FP80_TO_INT16_IN_MEM:
15829 case X86::FP80_TO_INT32_IN_MEM:
15830 case X86::FP80_TO_INT64_IN_MEM: {
15831 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
15832 DebugLoc DL = MI->getDebugLoc();
15834 // Change the floating point control register to use "round towards zero"
15835 // mode when truncating to an integer value.
15836 MachineFunction *F = BB->getParent();
15837 int CWFrameIdx = F->getFrameInfo()->CreateStackObject(2, 2, false);
15838 addFrameReference(BuildMI(*BB, MI, DL,
15839 TII->get(X86::FNSTCW16m)), CWFrameIdx);
15841 // Load the old value of the high byte of the control word...
15843 F->getRegInfo().createVirtualRegister(&X86::GR16RegClass);
15844 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16rm), OldCW),
15847 // Set the high part to be round to zero...
15848 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mi)), CWFrameIdx)
15851 // Reload the modified control word now...
15852 addFrameReference(BuildMI(*BB, MI, DL,
15853 TII->get(X86::FLDCW16m)), CWFrameIdx);
15855 // Restore the memory image of control word to original value
15856 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mr)), CWFrameIdx)
15859 // Get the X86 opcode to use.
15861 switch (MI->getOpcode()) {
15862 default: llvm_unreachable("illegal opcode!");
15863 case X86::FP32_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m32; break;
15864 case X86::FP32_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m32; break;
15865 case X86::FP32_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m32; break;
15866 case X86::FP64_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m64; break;
15867 case X86::FP64_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m64; break;
15868 case X86::FP64_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m64; break;
15869 case X86::FP80_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m80; break;
15870 case X86::FP80_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m80; break;
15871 case X86::FP80_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m80; break;
15875 MachineOperand &Op = MI->getOperand(0);
15877 AM.BaseType = X86AddressMode::RegBase;
15878 AM.Base.Reg = Op.getReg();
15880 AM.BaseType = X86AddressMode::FrameIndexBase;
15881 AM.Base.FrameIndex = Op.getIndex();
15883 Op = MI->getOperand(1);
15885 AM.Scale = Op.getImm();
15886 Op = MI->getOperand(2);
15888 AM.IndexReg = Op.getImm();
15889 Op = MI->getOperand(3);
15890 if (Op.isGlobal()) {
15891 AM.GV = Op.getGlobal();
15893 AM.Disp = Op.getImm();
15895 addFullAddress(BuildMI(*BB, MI, DL, TII->get(Opc)), AM)
15896 .addReg(MI->getOperand(X86::AddrNumOperands).getReg());
15898 // Reload the original control word now.
15899 addFrameReference(BuildMI(*BB, MI, DL,
15900 TII->get(X86::FLDCW16m)), CWFrameIdx);
15902 MI->eraseFromParent(); // The pseudo instruction is gone now.
15905 // String/text processing lowering.
15906 case X86::PCMPISTRM128REG:
15907 case X86::VPCMPISTRM128REG:
15908 case X86::PCMPISTRM128MEM:
15909 case X86::VPCMPISTRM128MEM:
15910 case X86::PCMPESTRM128REG:
15911 case X86::VPCMPESTRM128REG:
15912 case X86::PCMPESTRM128MEM:
15913 case X86::VPCMPESTRM128MEM:
15914 assert(Subtarget->hasSSE42() &&
15915 "Target must have SSE4.2 or AVX features enabled");
15916 return EmitPCMPSTRM(MI, BB, getTargetMachine().getInstrInfo());
15918 // String/text processing lowering.
15919 case X86::PCMPISTRIREG:
15920 case X86::VPCMPISTRIREG:
15921 case X86::PCMPISTRIMEM:
15922 case X86::VPCMPISTRIMEM:
15923 case X86::PCMPESTRIREG:
15924 case X86::VPCMPESTRIREG:
15925 case X86::PCMPESTRIMEM:
15926 case X86::VPCMPESTRIMEM:
15927 assert(Subtarget->hasSSE42() &&
15928 "Target must have SSE4.2 or AVX features enabled");
15929 return EmitPCMPSTRI(MI, BB, getTargetMachine().getInstrInfo());
15931 // Thread synchronization.
15933 return EmitMonitor(MI, BB, getTargetMachine().getInstrInfo(), Subtarget);
15937 return EmitXBegin(MI, BB, getTargetMachine().getInstrInfo());
15939 // Atomic Lowering.
15940 case X86::ATOMAND8:
15941 case X86::ATOMAND16:
15942 case X86::ATOMAND32:
15943 case X86::ATOMAND64:
15946 case X86::ATOMOR16:
15947 case X86::ATOMOR32:
15948 case X86::ATOMOR64:
15950 case X86::ATOMXOR16:
15951 case X86::ATOMXOR8:
15952 case X86::ATOMXOR32:
15953 case X86::ATOMXOR64:
15955 case X86::ATOMNAND8:
15956 case X86::ATOMNAND16:
15957 case X86::ATOMNAND32:
15958 case X86::ATOMNAND64:
15960 case X86::ATOMMAX8:
15961 case X86::ATOMMAX16:
15962 case X86::ATOMMAX32:
15963 case X86::ATOMMAX64:
15965 case X86::ATOMMIN8:
15966 case X86::ATOMMIN16:
15967 case X86::ATOMMIN32:
15968 case X86::ATOMMIN64:
15970 case X86::ATOMUMAX8:
15971 case X86::ATOMUMAX16:
15972 case X86::ATOMUMAX32:
15973 case X86::ATOMUMAX64:
15975 case X86::ATOMUMIN8:
15976 case X86::ATOMUMIN16:
15977 case X86::ATOMUMIN32:
15978 case X86::ATOMUMIN64:
15979 return EmitAtomicLoadArith(MI, BB);
15981 // This group does 64-bit operations on a 32-bit host.
15982 case X86::ATOMAND6432:
15983 case X86::ATOMOR6432:
15984 case X86::ATOMXOR6432:
15985 case X86::ATOMNAND6432:
15986 case X86::ATOMADD6432:
15987 case X86::ATOMSUB6432:
15988 case X86::ATOMMAX6432:
15989 case X86::ATOMMIN6432:
15990 case X86::ATOMUMAX6432:
15991 case X86::ATOMUMIN6432:
15992 case X86::ATOMSWAP6432:
15993 return EmitAtomicLoadArith6432(MI, BB);
15995 case X86::VASTART_SAVE_XMM_REGS:
15996 return EmitVAStartSaveXMMRegsWithCustomInserter(MI, BB);
15998 case X86::VAARG_64:
15999 return EmitVAARG64WithCustomInserter(MI, BB);
16001 case X86::EH_SjLj_SetJmp32:
16002 case X86::EH_SjLj_SetJmp64:
16003 return emitEHSjLjSetJmp(MI, BB);
16005 case X86::EH_SjLj_LongJmp32:
16006 case X86::EH_SjLj_LongJmp64:
16007 return emitEHSjLjLongJmp(MI, BB);
16011 //===----------------------------------------------------------------------===//
16012 // X86 Optimization Hooks
16013 //===----------------------------------------------------------------------===//
16015 void X86TargetLowering::computeMaskedBitsForTargetNode(const SDValue Op,
16018 const SelectionDAG &DAG,
16019 unsigned Depth) const {
16020 unsigned BitWidth = KnownZero.getBitWidth();
16021 unsigned Opc = Op.getOpcode();
16022 assert((Opc >= ISD::BUILTIN_OP_END ||
16023 Opc == ISD::INTRINSIC_WO_CHAIN ||
16024 Opc == ISD::INTRINSIC_W_CHAIN ||
16025 Opc == ISD::INTRINSIC_VOID) &&
16026 "Should use MaskedValueIsZero if you don't know whether Op"
16027 " is a target node!");
16029 KnownZero = KnownOne = APInt(BitWidth, 0); // Don't know anything.
16043 // These nodes' second result is a boolean.
16044 if (Op.getResNo() == 0)
16047 case X86ISD::SETCC:
16048 KnownZero |= APInt::getHighBitsSet(BitWidth, BitWidth - 1);
16050 case ISD::INTRINSIC_WO_CHAIN: {
16051 unsigned IntId = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
16052 unsigned NumLoBits = 0;
16055 case Intrinsic::x86_sse_movmsk_ps:
16056 case Intrinsic::x86_avx_movmsk_ps_256:
16057 case Intrinsic::x86_sse2_movmsk_pd:
16058 case Intrinsic::x86_avx_movmsk_pd_256:
16059 case Intrinsic::x86_mmx_pmovmskb:
16060 case Intrinsic::x86_sse2_pmovmskb_128:
16061 case Intrinsic::x86_avx2_pmovmskb: {
16062 // High bits of movmskp{s|d}, pmovmskb are known zero.
16064 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
16065 case Intrinsic::x86_sse_movmsk_ps: NumLoBits = 4; break;
16066 case Intrinsic::x86_avx_movmsk_ps_256: NumLoBits = 8; break;
16067 case Intrinsic::x86_sse2_movmsk_pd: NumLoBits = 2; break;
16068 case Intrinsic::x86_avx_movmsk_pd_256: NumLoBits = 4; break;
16069 case Intrinsic::x86_mmx_pmovmskb: NumLoBits = 8; break;
16070 case Intrinsic::x86_sse2_pmovmskb_128: NumLoBits = 16; break;
16071 case Intrinsic::x86_avx2_pmovmskb: NumLoBits = 32; break;
16073 KnownZero = APInt::getHighBitsSet(BitWidth, BitWidth - NumLoBits);
16082 unsigned X86TargetLowering::ComputeNumSignBitsForTargetNode(SDValue Op,
16083 unsigned Depth) const {
16084 // SETCC_CARRY sets the dest to ~0 for true or 0 for false.
16085 if (Op.getOpcode() == X86ISD::SETCC_CARRY)
16086 return Op.getValueType().getScalarType().getSizeInBits();
16092 /// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the
16093 /// node is a GlobalAddress + offset.
16094 bool X86TargetLowering::isGAPlusOffset(SDNode *N,
16095 const GlobalValue* &GA,
16096 int64_t &Offset) const {
16097 if (N->getOpcode() == X86ISD::Wrapper) {
16098 if (isa<GlobalAddressSDNode>(N->getOperand(0))) {
16099 GA = cast<GlobalAddressSDNode>(N->getOperand(0))->getGlobal();
16100 Offset = cast<GlobalAddressSDNode>(N->getOperand(0))->getOffset();
16104 return TargetLowering::isGAPlusOffset(N, GA, Offset);
16107 /// isShuffleHigh128VectorInsertLow - Checks whether the shuffle node is the
16108 /// same as extracting the high 128-bit part of 256-bit vector and then
16109 /// inserting the result into the low part of a new 256-bit vector
16110 static bool isShuffleHigh128VectorInsertLow(ShuffleVectorSDNode *SVOp) {
16111 EVT VT = SVOp->getValueType(0);
16112 unsigned NumElems = VT.getVectorNumElements();
16114 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
16115 for (unsigned i = 0, j = NumElems/2; i != NumElems/2; ++i, ++j)
16116 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) ||
16117 SVOp->getMaskElt(j) >= 0)
16123 /// isShuffleLow128VectorInsertHigh - Checks whether the shuffle node is the
16124 /// same as extracting the low 128-bit part of 256-bit vector and then
16125 /// inserting the result into the high part of a new 256-bit vector
16126 static bool isShuffleLow128VectorInsertHigh(ShuffleVectorSDNode *SVOp) {
16127 EVT VT = SVOp->getValueType(0);
16128 unsigned NumElems = VT.getVectorNumElements();
16130 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
16131 for (unsigned i = NumElems/2, j = 0; i != NumElems; ++i, ++j)
16132 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) ||
16133 SVOp->getMaskElt(j) >= 0)
16139 /// PerformShuffleCombine256 - Performs shuffle combines for 256-bit vectors.
16140 static SDValue PerformShuffleCombine256(SDNode *N, SelectionDAG &DAG,
16141 TargetLowering::DAGCombinerInfo &DCI,
16142 const X86Subtarget* Subtarget) {
16144 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
16145 SDValue V1 = SVOp->getOperand(0);
16146 SDValue V2 = SVOp->getOperand(1);
16147 EVT VT = SVOp->getValueType(0);
16148 unsigned NumElems = VT.getVectorNumElements();
16150 if (V1.getOpcode() == ISD::CONCAT_VECTORS &&
16151 V2.getOpcode() == ISD::CONCAT_VECTORS) {
16155 // V UNDEF BUILD_VECTOR UNDEF
16157 // CONCAT_VECTOR CONCAT_VECTOR
16160 // RESULT: V + zero extended
16162 if (V2.getOperand(0).getOpcode() != ISD::BUILD_VECTOR ||
16163 V2.getOperand(1).getOpcode() != ISD::UNDEF ||
16164 V1.getOperand(1).getOpcode() != ISD::UNDEF)
16167 if (!ISD::isBuildVectorAllZeros(V2.getOperand(0).getNode()))
16170 // To match the shuffle mask, the first half of the mask should
16171 // be exactly the first vector, and all the rest a splat with the
16172 // first element of the second one.
16173 for (unsigned i = 0; i != NumElems/2; ++i)
16174 if (!isUndefOrEqual(SVOp->getMaskElt(i), i) ||
16175 !isUndefOrEqual(SVOp->getMaskElt(i+NumElems/2), NumElems))
16178 // If V1 is coming from a vector load then just fold to a VZEXT_LOAD.
16179 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(V1.getOperand(0))) {
16180 if (Ld->hasNUsesOfValue(1, 0)) {
16181 SDVTList Tys = DAG.getVTList(MVT::v4i64, MVT::Other);
16182 SDValue Ops[] = { Ld->getChain(), Ld->getBasePtr() };
16184 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, dl, Tys, Ops,
16185 array_lengthof(Ops),
16187 Ld->getPointerInfo(),
16188 Ld->getAlignment(),
16189 false/*isVolatile*/, true/*ReadMem*/,
16190 false/*WriteMem*/);
16192 // Make sure the newly-created LOAD is in the same position as Ld in
16193 // terms of dependency. We create a TokenFactor for Ld and ResNode,
16194 // and update uses of Ld's output chain to use the TokenFactor.
16195 if (Ld->hasAnyUseOfValue(1)) {
16196 SDValue NewChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
16197 SDValue(Ld, 1), SDValue(ResNode.getNode(), 1));
16198 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), NewChain);
16199 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(Ld, 1),
16200 SDValue(ResNode.getNode(), 1));
16203 return DAG.getNode(ISD::BITCAST, dl, VT, ResNode);
16207 // Emit a zeroed vector and insert the desired subvector on its
16209 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
16210 SDValue InsV = Insert128BitVector(Zeros, V1.getOperand(0), 0, DAG, dl);
16211 return DCI.CombineTo(N, InsV);
16214 //===--------------------------------------------------------------------===//
16215 // Combine some shuffles into subvector extracts and inserts:
16218 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
16219 if (isShuffleHigh128VectorInsertLow(SVOp)) {
16220 SDValue V = Extract128BitVector(V1, NumElems/2, DAG, dl);
16221 SDValue InsV = Insert128BitVector(DAG.getUNDEF(VT), V, 0, DAG, dl);
16222 return DCI.CombineTo(N, InsV);
16225 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
16226 if (isShuffleLow128VectorInsertHigh(SVOp)) {
16227 SDValue V = Extract128BitVector(V1, 0, DAG, dl);
16228 SDValue InsV = Insert128BitVector(DAG.getUNDEF(VT), V, NumElems/2, DAG, dl);
16229 return DCI.CombineTo(N, InsV);
16235 /// PerformShuffleCombine - Performs several different shuffle combines.
16236 static SDValue PerformShuffleCombine(SDNode *N, SelectionDAG &DAG,
16237 TargetLowering::DAGCombinerInfo &DCI,
16238 const X86Subtarget *Subtarget) {
16240 EVT VT = N->getValueType(0);
16242 // Don't create instructions with illegal types after legalize types has run.
16243 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
16244 if (!DCI.isBeforeLegalize() && !TLI.isTypeLegal(VT.getVectorElementType()))
16247 // Combine 256-bit vector shuffles. This is only profitable when in AVX mode
16248 if (Subtarget->hasFp256() && VT.is256BitVector() &&
16249 N->getOpcode() == ISD::VECTOR_SHUFFLE)
16250 return PerformShuffleCombine256(N, DAG, DCI, Subtarget);
16252 // Only handle 128 wide vector from here on.
16253 if (!VT.is128BitVector())
16256 // Combine a vector_shuffle that is equal to build_vector load1, load2, load3,
16257 // load4, <0, 1, 2, 3> into a 128-bit load if the load addresses are
16258 // consecutive, non-overlapping, and in the right order.
16259 SmallVector<SDValue, 16> Elts;
16260 for (unsigned i = 0, e = VT.getVectorNumElements(); i != e; ++i)
16261 Elts.push_back(getShuffleScalarElt(N, i, DAG, 0));
16263 return EltsFromConsecutiveLoads(VT, Elts, dl, DAG);
16266 /// PerformTruncateCombine - Converts truncate operation to
16267 /// a sequence of vector shuffle operations.
16268 /// It is possible when we truncate 256-bit vector to 128-bit vector
16269 static SDValue PerformTruncateCombine(SDNode *N, SelectionDAG &DAG,
16270 TargetLowering::DAGCombinerInfo &DCI,
16271 const X86Subtarget *Subtarget) {
16275 /// XFormVExtractWithShuffleIntoLoad - Check if a vector extract from a target
16276 /// specific shuffle of a load can be folded into a single element load.
16277 /// Similar handling for VECTOR_SHUFFLE is performed by DAGCombiner, but
16278 /// shuffles have been customed lowered so we need to handle those here.
16279 static SDValue XFormVExtractWithShuffleIntoLoad(SDNode *N, SelectionDAG &DAG,
16280 TargetLowering::DAGCombinerInfo &DCI) {
16281 if (DCI.isBeforeLegalizeOps())
16284 SDValue InVec = N->getOperand(0);
16285 SDValue EltNo = N->getOperand(1);
16287 if (!isa<ConstantSDNode>(EltNo))
16290 EVT VT = InVec.getValueType();
16292 bool HasShuffleIntoBitcast = false;
16293 if (InVec.getOpcode() == ISD::BITCAST) {
16294 // Don't duplicate a load with other uses.
16295 if (!InVec.hasOneUse())
16297 EVT BCVT = InVec.getOperand(0).getValueType();
16298 if (BCVT.getVectorNumElements() != VT.getVectorNumElements())
16300 InVec = InVec.getOperand(0);
16301 HasShuffleIntoBitcast = true;
16304 if (!isTargetShuffle(InVec.getOpcode()))
16307 // Don't duplicate a load with other uses.
16308 if (!InVec.hasOneUse())
16311 SmallVector<int, 16> ShuffleMask;
16313 if (!getTargetShuffleMask(InVec.getNode(), VT.getSimpleVT(), ShuffleMask,
16317 // Select the input vector, guarding against out of range extract vector.
16318 unsigned NumElems = VT.getVectorNumElements();
16319 int Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();
16320 int Idx = (Elt > (int)NumElems) ? -1 : ShuffleMask[Elt];
16321 SDValue LdNode = (Idx < (int)NumElems) ? InVec.getOperand(0)
16322 : InVec.getOperand(1);
16324 // If inputs to shuffle are the same for both ops, then allow 2 uses
16325 unsigned AllowedUses = InVec.getOperand(0) == InVec.getOperand(1) ? 2 : 1;
16327 if (LdNode.getOpcode() == ISD::BITCAST) {
16328 // Don't duplicate a load with other uses.
16329 if (!LdNode.getNode()->hasNUsesOfValue(AllowedUses, 0))
16332 AllowedUses = 1; // only allow 1 load use if we have a bitcast
16333 LdNode = LdNode.getOperand(0);
16336 if (!ISD::isNormalLoad(LdNode.getNode()))
16339 LoadSDNode *LN0 = cast<LoadSDNode>(LdNode);
16341 if (!LN0 ||!LN0->hasNUsesOfValue(AllowedUses, 0) || LN0->isVolatile())
16344 if (HasShuffleIntoBitcast) {
16345 // If there's a bitcast before the shuffle, check if the load type and
16346 // alignment is valid.
16347 unsigned Align = LN0->getAlignment();
16348 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
16349 unsigned NewAlign = TLI.getDataLayout()->
16350 getABITypeAlignment(VT.getTypeForEVT(*DAG.getContext()));
16352 if (NewAlign > Align || !TLI.isOperationLegalOrCustom(ISD::LOAD, VT))
16356 // All checks match so transform back to vector_shuffle so that DAG combiner
16357 // can finish the job
16360 // Create shuffle node taking into account the case that its a unary shuffle
16361 SDValue Shuffle = (UnaryShuffle) ? DAG.getUNDEF(VT) : InVec.getOperand(1);
16362 Shuffle = DAG.getVectorShuffle(InVec.getValueType(), dl,
16363 InVec.getOperand(0), Shuffle,
16365 Shuffle = DAG.getNode(ISD::BITCAST, dl, VT, Shuffle);
16366 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, N->getValueType(0), Shuffle,
16370 /// Extract one bit from mask vector, like v16i1 or v8i1.
16371 /// AVX-512 feature.
16372 static SDValue ExtractBitFromMaskVector(SDNode *N, SelectionDAG &DAG) {
16373 SDValue Vec = N->getOperand(0);
16375 MVT VecVT = Vec.getSimpleValueType();
16376 SDValue Idx = N->getOperand(1);
16377 MVT EltVT = N->getSimpleValueType(0);
16379 assert((VecVT.getVectorElementType() == MVT::i1 && EltVT == MVT::i8) ||
16380 "Unexpected operands in ExtractBitFromMaskVector");
16383 if (!isa<ConstantSDNode>(Idx)) {
16384 MVT ExtVT = (VecVT == MVT::v8i1 ? MVT::v8i64 : MVT::v16i32);
16385 SDValue Ext = DAG.getNode(ISD::ZERO_EXTEND, dl, ExtVT, Vec);
16386 SDValue Elt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
16387 ExtVT.getVectorElementType(), Ext);
16388 return DAG.getNode(ISD::TRUNCATE, dl, EltVT, Elt);
16391 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
16393 MVT ScalarVT = MVT::getIntegerVT(VecVT.getSizeInBits());
16394 unsigned MaxShift = VecVT.getSizeInBits() - 1;
16395 Vec = DAG.getNode(ISD::BITCAST, dl, ScalarVT, Vec);
16396 Vec = DAG.getNode(ISD::SHL, dl, ScalarVT, Vec,
16397 DAG.getConstant(MaxShift - IdxVal, ScalarVT));
16398 Vec = DAG.getNode(ISD::SRL, dl, ScalarVT, Vec,
16399 DAG.getConstant(MaxShift, ScalarVT));
16401 if (VecVT == MVT::v16i1) {
16402 Vec = DAG.getNode(ISD::BITCAST, dl, MVT::i16, Vec);
16403 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Vec);
16405 return DAG.getNode(ISD::BITCAST, dl, MVT::i8, Vec);
16408 /// PerformEXTRACT_VECTOR_ELTCombine - Detect vector gather/scatter index
16409 /// generation and convert it from being a bunch of shuffles and extracts
16410 /// to a simple store and scalar loads to extract the elements.
16411 static SDValue PerformEXTRACT_VECTOR_ELTCombine(SDNode *N, SelectionDAG &DAG,
16412 TargetLowering::DAGCombinerInfo &DCI) {
16413 SDValue NewOp = XFormVExtractWithShuffleIntoLoad(N, DAG, DCI);
16414 if (NewOp.getNode())
16417 SDValue InputVector = N->getOperand(0);
16419 if (InputVector.getValueType().getVectorElementType() == MVT::i1 &&
16420 !DCI.isBeforeLegalize())
16421 return ExtractBitFromMaskVector(N, DAG);
16423 // Detect whether we are trying to convert from mmx to i32 and the bitcast
16424 // from mmx to v2i32 has a single usage.
16425 if (InputVector.getNode()->getOpcode() == llvm::ISD::BITCAST &&
16426 InputVector.getNode()->getOperand(0).getValueType() == MVT::x86mmx &&
16427 InputVector.hasOneUse() && N->getValueType(0) == MVT::i32)
16428 return DAG.getNode(X86ISD::MMX_MOVD2W, SDLoc(InputVector),
16429 N->getValueType(0),
16430 InputVector.getNode()->getOperand(0));
16432 // Only operate on vectors of 4 elements, where the alternative shuffling
16433 // gets to be more expensive.
16434 if (InputVector.getValueType() != MVT::v4i32)
16437 // Check whether every use of InputVector is an EXTRACT_VECTOR_ELT with a
16438 // single use which is a sign-extend or zero-extend, and all elements are
16440 SmallVector<SDNode *, 4> Uses;
16441 unsigned ExtractedElements = 0;
16442 for (SDNode::use_iterator UI = InputVector.getNode()->use_begin(),
16443 UE = InputVector.getNode()->use_end(); UI != UE; ++UI) {
16444 if (UI.getUse().getResNo() != InputVector.getResNo())
16447 SDNode *Extract = *UI;
16448 if (Extract->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
16451 if (Extract->getValueType(0) != MVT::i32)
16453 if (!Extract->hasOneUse())
16455 if (Extract->use_begin()->getOpcode() != ISD::SIGN_EXTEND &&
16456 Extract->use_begin()->getOpcode() != ISD::ZERO_EXTEND)
16458 if (!isa<ConstantSDNode>(Extract->getOperand(1)))
16461 // Record which element was extracted.
16462 ExtractedElements |=
16463 1 << cast<ConstantSDNode>(Extract->getOperand(1))->getZExtValue();
16465 Uses.push_back(Extract);
16468 // If not all the elements were used, this may not be worthwhile.
16469 if (ExtractedElements != 15)
16472 // Ok, we've now decided to do the transformation.
16473 SDLoc dl(InputVector);
16475 // Store the value to a temporary stack slot.
16476 SDValue StackPtr = DAG.CreateStackTemporary(InputVector.getValueType());
16477 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, InputVector, StackPtr,
16478 MachinePointerInfo(), false, false, 0);
16480 // Replace each use (extract) with a load of the appropriate element.
16481 for (SmallVectorImpl<SDNode *>::iterator UI = Uses.begin(),
16482 UE = Uses.end(); UI != UE; ++UI) {
16483 SDNode *Extract = *UI;
16485 // cOMpute the element's address.
16486 SDValue Idx = Extract->getOperand(1);
16488 InputVector.getValueType().getVectorElementType().getSizeInBits()/8;
16489 uint64_t Offset = EltSize * cast<ConstantSDNode>(Idx)->getZExtValue();
16490 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
16491 SDValue OffsetVal = DAG.getConstant(Offset, TLI.getPointerTy());
16493 SDValue ScalarAddr = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(),
16494 StackPtr, OffsetVal);
16496 // Load the scalar.
16497 SDValue LoadScalar = DAG.getLoad(Extract->getValueType(0), dl, Ch,
16498 ScalarAddr, MachinePointerInfo(),
16499 false, false, false, 0);
16501 // Replace the exact with the load.
16502 DAG.ReplaceAllUsesOfValueWith(SDValue(Extract, 0), LoadScalar);
16505 // The replacement was made in place; don't return anything.
16509 /// \brief Matches a VSELECT onto min/max or return 0 if the node doesn't match.
16510 static std::pair<unsigned, bool>
16511 matchIntegerMINMAX(SDValue Cond, EVT VT, SDValue LHS, SDValue RHS,
16512 SelectionDAG &DAG, const X86Subtarget *Subtarget) {
16513 if (!VT.isVector())
16514 return std::make_pair(0, false);
16516 bool NeedSplit = false;
16517 switch (VT.getSimpleVT().SimpleTy) {
16518 default: return std::make_pair(0, false);
16522 if (!Subtarget->hasAVX2())
16524 if (!Subtarget->hasAVX())
16525 return std::make_pair(0, false);
16530 if (!Subtarget->hasSSE2())
16531 return std::make_pair(0, false);
16534 // SSE2 has only a small subset of the operations.
16535 bool hasUnsigned = Subtarget->hasSSE41() ||
16536 (Subtarget->hasSSE2() && VT == MVT::v16i8);
16537 bool hasSigned = Subtarget->hasSSE41() ||
16538 (Subtarget->hasSSE2() && VT == MVT::v8i16);
16540 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
16543 // Check for x CC y ? x : y.
16544 if (DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
16545 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
16550 Opc = hasUnsigned ? X86ISD::UMIN : 0; break;
16553 Opc = hasUnsigned ? X86ISD::UMAX : 0; break;
16556 Opc = hasSigned ? X86ISD::SMIN : 0; break;
16559 Opc = hasSigned ? X86ISD::SMAX : 0; break;
16561 // Check for x CC y ? y : x -- a min/max with reversed arms.
16562 } else if (DAG.isEqualTo(LHS, Cond.getOperand(1)) &&
16563 DAG.isEqualTo(RHS, Cond.getOperand(0))) {
16568 Opc = hasUnsigned ? X86ISD::UMAX : 0; break;
16571 Opc = hasUnsigned ? X86ISD::UMIN : 0; break;
16574 Opc = hasSigned ? X86ISD::SMAX : 0; break;
16577 Opc = hasSigned ? X86ISD::SMIN : 0; break;
16581 return std::make_pair(Opc, NeedSplit);
16584 /// PerformSELECTCombine - Do target-specific dag combines on SELECT and VSELECT
16586 static SDValue PerformSELECTCombine(SDNode *N, SelectionDAG &DAG,
16587 TargetLowering::DAGCombinerInfo &DCI,
16588 const X86Subtarget *Subtarget) {
16590 SDValue Cond = N->getOperand(0);
16591 // Get the LHS/RHS of the select.
16592 SDValue LHS = N->getOperand(1);
16593 SDValue RHS = N->getOperand(2);
16594 EVT VT = LHS.getValueType();
16595 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
16597 // If we have SSE[12] support, try to form min/max nodes. SSE min/max
16598 // instructions match the semantics of the common C idiom x<y?x:y but not
16599 // x<=y?x:y, because of how they handle negative zero (which can be
16600 // ignored in unsafe-math mode).
16601 if (Cond.getOpcode() == ISD::SETCC && VT.isFloatingPoint() &&
16602 VT != MVT::f80 && TLI.isTypeLegal(VT) &&
16603 (Subtarget->hasSSE2() ||
16604 (Subtarget->hasSSE1() && VT.getScalarType() == MVT::f32))) {
16605 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
16607 unsigned Opcode = 0;
16608 // Check for x CC y ? x : y.
16609 if (DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
16610 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
16614 // Converting this to a min would handle NaNs incorrectly, and swapping
16615 // the operands would cause it to handle comparisons between positive
16616 // and negative zero incorrectly.
16617 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
16618 if (!DAG.getTarget().Options.UnsafeFPMath &&
16619 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
16621 std::swap(LHS, RHS);
16623 Opcode = X86ISD::FMIN;
16626 // Converting this to a min would handle comparisons between positive
16627 // and negative zero incorrectly.
16628 if (!DAG.getTarget().Options.UnsafeFPMath &&
16629 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
16631 Opcode = X86ISD::FMIN;
16634 // Converting this to a min would handle both negative zeros and NaNs
16635 // incorrectly, but we can swap the operands to fix both.
16636 std::swap(LHS, RHS);
16640 Opcode = X86ISD::FMIN;
16644 // Converting this to a max would handle comparisons between positive
16645 // and negative zero incorrectly.
16646 if (!DAG.getTarget().Options.UnsafeFPMath &&
16647 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
16649 Opcode = X86ISD::FMAX;
16652 // Converting this to a max would handle NaNs incorrectly, and swapping
16653 // the operands would cause it to handle comparisons between positive
16654 // and negative zero incorrectly.
16655 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
16656 if (!DAG.getTarget().Options.UnsafeFPMath &&
16657 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
16659 std::swap(LHS, RHS);
16661 Opcode = X86ISD::FMAX;
16664 // Converting this to a max would handle both negative zeros and NaNs
16665 // incorrectly, but we can swap the operands to fix both.
16666 std::swap(LHS, RHS);
16670 Opcode = X86ISD::FMAX;
16673 // Check for x CC y ? y : x -- a min/max with reversed arms.
16674 } else if (DAG.isEqualTo(LHS, Cond.getOperand(1)) &&
16675 DAG.isEqualTo(RHS, Cond.getOperand(0))) {
16679 // Converting this to a min would handle comparisons between positive
16680 // and negative zero incorrectly, and swapping the operands would
16681 // cause it to handle NaNs incorrectly.
16682 if (!DAG.getTarget().Options.UnsafeFPMath &&
16683 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS))) {
16684 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
16686 std::swap(LHS, RHS);
16688 Opcode = X86ISD::FMIN;
16691 // Converting this to a min would handle NaNs incorrectly.
16692 if (!DAG.getTarget().Options.UnsafeFPMath &&
16693 (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)))
16695 Opcode = X86ISD::FMIN;
16698 // Converting this to a min would handle both negative zeros and NaNs
16699 // incorrectly, but we can swap the operands to fix both.
16700 std::swap(LHS, RHS);
16704 Opcode = X86ISD::FMIN;
16708 // Converting this to a max would handle NaNs incorrectly.
16709 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
16711 Opcode = X86ISD::FMAX;
16714 // Converting this to a max would handle comparisons between positive
16715 // and negative zero incorrectly, and swapping the operands would
16716 // cause it to handle NaNs incorrectly.
16717 if (!DAG.getTarget().Options.UnsafeFPMath &&
16718 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS)) {
16719 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
16721 std::swap(LHS, RHS);
16723 Opcode = X86ISD::FMAX;
16726 // Converting this to a max would handle both negative zeros and NaNs
16727 // incorrectly, but we can swap the operands to fix both.
16728 std::swap(LHS, RHS);
16732 Opcode = X86ISD::FMAX;
16738 return DAG.getNode(Opcode, DL, N->getValueType(0), LHS, RHS);
16741 EVT CondVT = Cond.getValueType();
16742 if (Subtarget->hasAVX512() && VT.isVector() && CondVT.isVector() &&
16743 CondVT.getVectorElementType() == MVT::i1) {
16744 // v16i8 (select v16i1, v16i8, v16i8) does not have a proper
16745 // lowering on AVX-512. In this case we convert it to
16746 // v16i8 (select v16i8, v16i8, v16i8) and use AVX instruction.
16747 // The same situation for all 128 and 256-bit vectors of i8 and i16
16748 EVT OpVT = LHS.getValueType();
16749 if ((OpVT.is128BitVector() || OpVT.is256BitVector()) &&
16750 (OpVT.getVectorElementType() == MVT::i8 ||
16751 OpVT.getVectorElementType() == MVT::i16)) {
16752 Cond = DAG.getNode(ISD::SIGN_EXTEND, DL, OpVT, Cond);
16753 DCI.AddToWorklist(Cond.getNode());
16754 return DAG.getNode(N->getOpcode(), DL, OpVT, Cond, LHS, RHS);
16757 // If this is a select between two integer constants, try to do some
16759 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(LHS)) {
16760 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(RHS))
16761 // Don't do this for crazy integer types.
16762 if (DAG.getTargetLoweringInfo().isTypeLegal(LHS.getValueType())) {
16763 // If this is efficiently invertible, canonicalize the LHSC/RHSC values
16764 // so that TrueC (the true value) is larger than FalseC.
16765 bool NeedsCondInvert = false;
16767 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue()) &&
16768 // Efficiently invertible.
16769 (Cond.getOpcode() == ISD::SETCC || // setcc -> invertible.
16770 (Cond.getOpcode() == ISD::XOR && // xor(X, C) -> invertible.
16771 isa<ConstantSDNode>(Cond.getOperand(1))))) {
16772 NeedsCondInvert = true;
16773 std::swap(TrueC, FalseC);
16776 // Optimize C ? 8 : 0 -> zext(C) << 3. Likewise for any pow2/0.
16777 if (FalseC->getAPIntValue() == 0 &&
16778 TrueC->getAPIntValue().isPowerOf2()) {
16779 if (NeedsCondInvert) // Invert the condition if needed.
16780 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
16781 DAG.getConstant(1, Cond.getValueType()));
16783 // Zero extend the condition if needed.
16784 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, LHS.getValueType(), Cond);
16786 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
16787 return DAG.getNode(ISD::SHL, DL, LHS.getValueType(), Cond,
16788 DAG.getConstant(ShAmt, MVT::i8));
16791 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst.
16792 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
16793 if (NeedsCondInvert) // Invert the condition if needed.
16794 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
16795 DAG.getConstant(1, Cond.getValueType()));
16797 // Zero extend the condition if needed.
16798 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
16799 FalseC->getValueType(0), Cond);
16800 return DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
16801 SDValue(FalseC, 0));
16804 // Optimize cases that will turn into an LEA instruction. This requires
16805 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
16806 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
16807 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
16808 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
16810 bool isFastMultiplier = false;
16812 switch ((unsigned char)Diff) {
16814 case 1: // result = add base, cond
16815 case 2: // result = lea base( , cond*2)
16816 case 3: // result = lea base(cond, cond*2)
16817 case 4: // result = lea base( , cond*4)
16818 case 5: // result = lea base(cond, cond*4)
16819 case 8: // result = lea base( , cond*8)
16820 case 9: // result = lea base(cond, cond*8)
16821 isFastMultiplier = true;
16826 if (isFastMultiplier) {
16827 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
16828 if (NeedsCondInvert) // Invert the condition if needed.
16829 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
16830 DAG.getConstant(1, Cond.getValueType()));
16832 // Zero extend the condition if needed.
16833 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
16835 // Scale the condition by the difference.
16837 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
16838 DAG.getConstant(Diff, Cond.getValueType()));
16840 // Add the base if non-zero.
16841 if (FalseC->getAPIntValue() != 0)
16842 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
16843 SDValue(FalseC, 0));
16850 // Canonicalize max and min:
16851 // (x > y) ? x : y -> (x >= y) ? x : y
16852 // (x < y) ? x : y -> (x <= y) ? x : y
16853 // This allows use of COND_S / COND_NS (see TranslateX86CC) which eliminates
16854 // the need for an extra compare
16855 // against zero. e.g.
16856 // (x - y) > 0 : (x - y) ? 0 -> (x - y) >= 0 : (x - y) ? 0
16858 // testl %edi, %edi
16860 // cmovgl %edi, %eax
16864 // cmovsl %eax, %edi
16865 if (N->getOpcode() == ISD::SELECT && Cond.getOpcode() == ISD::SETCC &&
16866 DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
16867 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
16868 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
16873 ISD::CondCode NewCC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGE;
16874 Cond = DAG.getSetCC(SDLoc(Cond), Cond.getValueType(),
16875 Cond.getOperand(0), Cond.getOperand(1), NewCC);
16876 return DAG.getNode(ISD::SELECT, DL, VT, Cond, LHS, RHS);
16881 // Early exit check
16882 if (!TLI.isTypeLegal(VT))
16885 // Match VSELECTs into subs with unsigned saturation.
16886 if (N->getOpcode() == ISD::VSELECT && Cond.getOpcode() == ISD::SETCC &&
16887 // psubus is available in SSE2 and AVX2 for i8 and i16 vectors.
16888 ((Subtarget->hasSSE2() && (VT == MVT::v16i8 || VT == MVT::v8i16)) ||
16889 (Subtarget->hasAVX2() && (VT == MVT::v32i8 || VT == MVT::v16i16)))) {
16890 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
16892 // Check if one of the arms of the VSELECT is a zero vector. If it's on the
16893 // left side invert the predicate to simplify logic below.
16895 if (ISD::isBuildVectorAllZeros(LHS.getNode())) {
16897 CC = ISD::getSetCCInverse(CC, true);
16898 } else if (ISD::isBuildVectorAllZeros(RHS.getNode())) {
16902 if (Other.getNode() && Other->getNumOperands() == 2 &&
16903 DAG.isEqualTo(Other->getOperand(0), Cond.getOperand(0))) {
16904 SDValue OpLHS = Other->getOperand(0), OpRHS = Other->getOperand(1);
16905 SDValue CondRHS = Cond->getOperand(1);
16907 // Look for a general sub with unsigned saturation first.
16908 // x >= y ? x-y : 0 --> subus x, y
16909 // x > y ? x-y : 0 --> subus x, y
16910 if ((CC == ISD::SETUGE || CC == ISD::SETUGT) &&
16911 Other->getOpcode() == ISD::SUB && DAG.isEqualTo(OpRHS, CondRHS))
16912 return DAG.getNode(X86ISD::SUBUS, DL, VT, OpLHS, OpRHS);
16914 // If the RHS is a constant we have to reverse the const canonicalization.
16915 // x > C-1 ? x+-C : 0 --> subus x, C
16916 if (CC == ISD::SETUGT && Other->getOpcode() == ISD::ADD &&
16917 isSplatVector(CondRHS.getNode()) && isSplatVector(OpRHS.getNode())) {
16918 APInt A = cast<ConstantSDNode>(OpRHS.getOperand(0))->getAPIntValue();
16919 if (CondRHS.getConstantOperandVal(0) == -A-1)
16920 return DAG.getNode(X86ISD::SUBUS, DL, VT, OpLHS,
16921 DAG.getConstant(-A, VT));
16924 // Another special case: If C was a sign bit, the sub has been
16925 // canonicalized into a xor.
16926 // FIXME: Would it be better to use ComputeMaskedBits to determine whether
16927 // it's safe to decanonicalize the xor?
16928 // x s< 0 ? x^C : 0 --> subus x, C
16929 if (CC == ISD::SETLT && Other->getOpcode() == ISD::XOR &&
16930 ISD::isBuildVectorAllZeros(CondRHS.getNode()) &&
16931 isSplatVector(OpRHS.getNode())) {
16932 APInt A = cast<ConstantSDNode>(OpRHS.getOperand(0))->getAPIntValue();
16934 return DAG.getNode(X86ISD::SUBUS, DL, VT, OpLHS, OpRHS);
16939 // Try to match a min/max vector operation.
16940 if (N->getOpcode() == ISD::VSELECT && Cond.getOpcode() == ISD::SETCC) {
16941 std::pair<unsigned, bool> ret = matchIntegerMINMAX(Cond, VT, LHS, RHS, DAG, Subtarget);
16942 unsigned Opc = ret.first;
16943 bool NeedSplit = ret.second;
16945 if (Opc && NeedSplit) {
16946 unsigned NumElems = VT.getVectorNumElements();
16947 // Extract the LHS vectors
16948 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, DL);
16949 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, DL);
16951 // Extract the RHS vectors
16952 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, DL);
16953 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, DL);
16955 // Create min/max for each subvector
16956 LHS = DAG.getNode(Opc, DL, LHS1.getValueType(), LHS1, RHS1);
16957 RHS = DAG.getNode(Opc, DL, LHS2.getValueType(), LHS2, RHS2);
16959 // Merge the result
16960 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, LHS, RHS);
16962 return DAG.getNode(Opc, DL, VT, LHS, RHS);
16965 // Simplify vector selection if the selector will be produced by CMPP*/PCMP*.
16966 if (N->getOpcode() == ISD::VSELECT && Cond.getOpcode() == ISD::SETCC &&
16967 // Check if SETCC has already been promoted
16968 TLI.getSetCCResultType(*DAG.getContext(), VT) == Cond.getValueType()) {
16970 assert(Cond.getValueType().isVector() &&
16971 "vector select expects a vector selector!");
16973 EVT IntVT = Cond.getValueType();
16974 bool TValIsAllOnes = ISD::isBuildVectorAllOnes(LHS.getNode());
16975 bool FValIsAllZeros = ISD::isBuildVectorAllZeros(RHS.getNode());
16977 if (!TValIsAllOnes && !FValIsAllZeros) {
16978 // Try invert the condition if true value is not all 1s and false value
16980 bool TValIsAllZeros = ISD::isBuildVectorAllZeros(LHS.getNode());
16981 bool FValIsAllOnes = ISD::isBuildVectorAllOnes(RHS.getNode());
16983 if (TValIsAllZeros || FValIsAllOnes) {
16984 SDValue CC = Cond.getOperand(2);
16985 ISD::CondCode NewCC =
16986 ISD::getSetCCInverse(cast<CondCodeSDNode>(CC)->get(),
16987 Cond.getOperand(0).getValueType().isInteger());
16988 Cond = DAG.getSetCC(DL, IntVT, Cond.getOperand(0), Cond.getOperand(1), NewCC);
16989 std::swap(LHS, RHS);
16990 TValIsAllOnes = FValIsAllOnes;
16991 FValIsAllZeros = TValIsAllZeros;
16995 if (TValIsAllOnes || FValIsAllZeros) {
16998 if (TValIsAllOnes && FValIsAllZeros)
17000 else if (TValIsAllOnes)
17001 Ret = DAG.getNode(ISD::OR, DL, IntVT, Cond,
17002 DAG.getNode(ISD::BITCAST, DL, IntVT, RHS));
17003 else if (FValIsAllZeros)
17004 Ret = DAG.getNode(ISD::AND, DL, IntVT, Cond,
17005 DAG.getNode(ISD::BITCAST, DL, IntVT, LHS));
17007 return DAG.getNode(ISD::BITCAST, DL, VT, Ret);
17011 // If we know that this node is legal then we know that it is going to be
17012 // matched by one of the SSE/AVX BLEND instructions. These instructions only
17013 // depend on the highest bit in each word. Try to use SimplifyDemandedBits
17014 // to simplify previous instructions.
17015 if (N->getOpcode() == ISD::VSELECT && DCI.isBeforeLegalizeOps() &&
17016 !DCI.isBeforeLegalize() && TLI.isOperationLegal(ISD::VSELECT, VT)) {
17017 unsigned BitWidth = Cond.getValueType().getScalarType().getSizeInBits();
17019 // Don't optimize vector selects that map to mask-registers.
17023 assert(BitWidth >= 8 && BitWidth <= 64 && "Invalid mask size");
17024 APInt DemandedMask = APInt::getHighBitsSet(BitWidth, 1);
17026 APInt KnownZero, KnownOne;
17027 TargetLowering::TargetLoweringOpt TLO(DAG, DCI.isBeforeLegalize(),
17028 DCI.isBeforeLegalizeOps());
17029 if (TLO.ShrinkDemandedConstant(Cond, DemandedMask) ||
17030 TLI.SimplifyDemandedBits(Cond, DemandedMask, KnownZero, KnownOne, TLO))
17031 DCI.CommitTargetLoweringOpt(TLO);
17037 // Check whether a boolean test is testing a boolean value generated by
17038 // X86ISD::SETCC. If so, return the operand of that SETCC and proper condition
17041 // Simplify the following patterns:
17042 // (Op (CMP (SETCC Cond EFLAGS) 1) EQ) or
17043 // (Op (CMP (SETCC Cond EFLAGS) 0) NEQ)
17044 // to (Op EFLAGS Cond)
17046 // (Op (CMP (SETCC Cond EFLAGS) 0) EQ) or
17047 // (Op (CMP (SETCC Cond EFLAGS) 1) NEQ)
17048 // to (Op EFLAGS !Cond)
17050 // where Op could be BRCOND or CMOV.
17052 static SDValue checkBoolTestSetCCCombine(SDValue Cmp, X86::CondCode &CC) {
17053 // Quit if not CMP and SUB with its value result used.
17054 if (Cmp.getOpcode() != X86ISD::CMP &&
17055 (Cmp.getOpcode() != X86ISD::SUB || Cmp.getNode()->hasAnyUseOfValue(0)))
17058 // Quit if not used as a boolean value.
17059 if (CC != X86::COND_E && CC != X86::COND_NE)
17062 // Check CMP operands. One of them should be 0 or 1 and the other should be
17063 // an SetCC or extended from it.
17064 SDValue Op1 = Cmp.getOperand(0);
17065 SDValue Op2 = Cmp.getOperand(1);
17068 const ConstantSDNode* C = 0;
17069 bool needOppositeCond = (CC == X86::COND_E);
17070 bool checkAgainstTrue = false; // Is it a comparison against 1?
17072 if ((C = dyn_cast<ConstantSDNode>(Op1)))
17074 else if ((C = dyn_cast<ConstantSDNode>(Op2)))
17076 else // Quit if all operands are not constants.
17079 if (C->getZExtValue() == 1) {
17080 needOppositeCond = !needOppositeCond;
17081 checkAgainstTrue = true;
17082 } else if (C->getZExtValue() != 0)
17083 // Quit if the constant is neither 0 or 1.
17086 bool truncatedToBoolWithAnd = false;
17087 // Skip (zext $x), (trunc $x), or (and $x, 1) node.
17088 while (SetCC.getOpcode() == ISD::ZERO_EXTEND ||
17089 SetCC.getOpcode() == ISD::TRUNCATE ||
17090 SetCC.getOpcode() == ISD::AND) {
17091 if (SetCC.getOpcode() == ISD::AND) {
17093 ConstantSDNode *CS;
17094 if ((CS = dyn_cast<ConstantSDNode>(SetCC.getOperand(0))) &&
17095 CS->getZExtValue() == 1)
17097 if ((CS = dyn_cast<ConstantSDNode>(SetCC.getOperand(1))) &&
17098 CS->getZExtValue() == 1)
17102 SetCC = SetCC.getOperand(OpIdx);
17103 truncatedToBoolWithAnd = true;
17105 SetCC = SetCC.getOperand(0);
17108 switch (SetCC.getOpcode()) {
17109 case X86ISD::SETCC_CARRY:
17110 // Since SETCC_CARRY gives output based on R = CF ? ~0 : 0, it's unsafe to
17111 // simplify it if the result of SETCC_CARRY is not canonicalized to 0 or 1,
17112 // i.e. it's a comparison against true but the result of SETCC_CARRY is not
17113 // truncated to i1 using 'and'.
17114 if (checkAgainstTrue && !truncatedToBoolWithAnd)
17116 assert(X86::CondCode(SetCC.getConstantOperandVal(0)) == X86::COND_B &&
17117 "Invalid use of SETCC_CARRY!");
17119 case X86ISD::SETCC:
17120 // Set the condition code or opposite one if necessary.
17121 CC = X86::CondCode(SetCC.getConstantOperandVal(0));
17122 if (needOppositeCond)
17123 CC = X86::GetOppositeBranchCondition(CC);
17124 return SetCC.getOperand(1);
17125 case X86ISD::CMOV: {
17126 // Check whether false/true value has canonical one, i.e. 0 or 1.
17127 ConstantSDNode *FVal = dyn_cast<ConstantSDNode>(SetCC.getOperand(0));
17128 ConstantSDNode *TVal = dyn_cast<ConstantSDNode>(SetCC.getOperand(1));
17129 // Quit if true value is not a constant.
17132 // Quit if false value is not a constant.
17134 SDValue Op = SetCC.getOperand(0);
17135 // Skip 'zext' or 'trunc' node.
17136 if (Op.getOpcode() == ISD::ZERO_EXTEND ||
17137 Op.getOpcode() == ISD::TRUNCATE)
17138 Op = Op.getOperand(0);
17139 // A special case for rdrand/rdseed, where 0 is set if false cond is
17141 if ((Op.getOpcode() != X86ISD::RDRAND &&
17142 Op.getOpcode() != X86ISD::RDSEED) || Op.getResNo() != 0)
17145 // Quit if false value is not the constant 0 or 1.
17146 bool FValIsFalse = true;
17147 if (FVal && FVal->getZExtValue() != 0) {
17148 if (FVal->getZExtValue() != 1)
17150 // If FVal is 1, opposite cond is needed.
17151 needOppositeCond = !needOppositeCond;
17152 FValIsFalse = false;
17154 // Quit if TVal is not the constant opposite of FVal.
17155 if (FValIsFalse && TVal->getZExtValue() != 1)
17157 if (!FValIsFalse && TVal->getZExtValue() != 0)
17159 CC = X86::CondCode(SetCC.getConstantOperandVal(2));
17160 if (needOppositeCond)
17161 CC = X86::GetOppositeBranchCondition(CC);
17162 return SetCC.getOperand(3);
17169 /// Optimize X86ISD::CMOV [LHS, RHS, CONDCODE (e.g. X86::COND_NE), CONDVAL]
17170 static SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG,
17171 TargetLowering::DAGCombinerInfo &DCI,
17172 const X86Subtarget *Subtarget) {
17175 // If the flag operand isn't dead, don't touch this CMOV.
17176 if (N->getNumValues() == 2 && !SDValue(N, 1).use_empty())
17179 SDValue FalseOp = N->getOperand(0);
17180 SDValue TrueOp = N->getOperand(1);
17181 X86::CondCode CC = (X86::CondCode)N->getConstantOperandVal(2);
17182 SDValue Cond = N->getOperand(3);
17184 if (CC == X86::COND_E || CC == X86::COND_NE) {
17185 switch (Cond.getOpcode()) {
17189 // If operand of BSR / BSF are proven never zero, then ZF cannot be set.
17190 if (DAG.isKnownNeverZero(Cond.getOperand(0)))
17191 return (CC == X86::COND_E) ? FalseOp : TrueOp;
17197 Flags = checkBoolTestSetCCCombine(Cond, CC);
17198 if (Flags.getNode() &&
17199 // Extra check as FCMOV only supports a subset of X86 cond.
17200 (FalseOp.getValueType() != MVT::f80 || hasFPCMov(CC))) {
17201 SDValue Ops[] = { FalseOp, TrueOp,
17202 DAG.getConstant(CC, MVT::i8), Flags };
17203 return DAG.getNode(X86ISD::CMOV, DL, N->getVTList(),
17204 Ops, array_lengthof(Ops));
17207 // If this is a select between two integer constants, try to do some
17208 // optimizations. Note that the operands are ordered the opposite of SELECT
17210 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(TrueOp)) {
17211 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(FalseOp)) {
17212 // Canonicalize the TrueC/FalseC values so that TrueC (the true value) is
17213 // larger than FalseC (the false value).
17214 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue())) {
17215 CC = X86::GetOppositeBranchCondition(CC);
17216 std::swap(TrueC, FalseC);
17217 std::swap(TrueOp, FalseOp);
17220 // Optimize C ? 8 : 0 -> zext(setcc(C)) << 3. Likewise for any pow2/0.
17221 // This is efficient for any integer data type (including i8/i16) and
17223 if (FalseC->getAPIntValue() == 0 && TrueC->getAPIntValue().isPowerOf2()) {
17224 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
17225 DAG.getConstant(CC, MVT::i8), Cond);
17227 // Zero extend the condition if needed.
17228 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, TrueC->getValueType(0), Cond);
17230 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
17231 Cond = DAG.getNode(ISD::SHL, DL, Cond.getValueType(), Cond,
17232 DAG.getConstant(ShAmt, MVT::i8));
17233 if (N->getNumValues() == 2) // Dead flag value?
17234 return DCI.CombineTo(N, Cond, SDValue());
17238 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst. This is efficient
17239 // for any integer data type, including i8/i16.
17240 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
17241 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
17242 DAG.getConstant(CC, MVT::i8), Cond);
17244 // Zero extend the condition if needed.
17245 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
17246 FalseC->getValueType(0), Cond);
17247 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
17248 SDValue(FalseC, 0));
17250 if (N->getNumValues() == 2) // Dead flag value?
17251 return DCI.CombineTo(N, Cond, SDValue());
17255 // Optimize cases that will turn into an LEA instruction. This requires
17256 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
17257 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
17258 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
17259 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
17261 bool isFastMultiplier = false;
17263 switch ((unsigned char)Diff) {
17265 case 1: // result = add base, cond
17266 case 2: // result = lea base( , cond*2)
17267 case 3: // result = lea base(cond, cond*2)
17268 case 4: // result = lea base( , cond*4)
17269 case 5: // result = lea base(cond, cond*4)
17270 case 8: // result = lea base( , cond*8)
17271 case 9: // result = lea base(cond, cond*8)
17272 isFastMultiplier = true;
17277 if (isFastMultiplier) {
17278 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
17279 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
17280 DAG.getConstant(CC, MVT::i8), Cond);
17281 // Zero extend the condition if needed.
17282 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
17284 // Scale the condition by the difference.
17286 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
17287 DAG.getConstant(Diff, Cond.getValueType()));
17289 // Add the base if non-zero.
17290 if (FalseC->getAPIntValue() != 0)
17291 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
17292 SDValue(FalseC, 0));
17293 if (N->getNumValues() == 2) // Dead flag value?
17294 return DCI.CombineTo(N, Cond, SDValue());
17301 // Handle these cases:
17302 // (select (x != c), e, c) -> select (x != c), e, x),
17303 // (select (x == c), c, e) -> select (x == c), x, e)
17304 // where the c is an integer constant, and the "select" is the combination
17305 // of CMOV and CMP.
17307 // The rationale for this change is that the conditional-move from a constant
17308 // needs two instructions, however, conditional-move from a register needs
17309 // only one instruction.
17311 // CAVEAT: By replacing a constant with a symbolic value, it may obscure
17312 // some instruction-combining opportunities. This opt needs to be
17313 // postponed as late as possible.
17315 if (!DCI.isBeforeLegalize() && !DCI.isBeforeLegalizeOps()) {
17316 // the DCI.xxxx conditions are provided to postpone the optimization as
17317 // late as possible.
17319 ConstantSDNode *CmpAgainst = 0;
17320 if ((Cond.getOpcode() == X86ISD::CMP || Cond.getOpcode() == X86ISD::SUB) &&
17321 (CmpAgainst = dyn_cast<ConstantSDNode>(Cond.getOperand(1))) &&
17322 !isa<ConstantSDNode>(Cond.getOperand(0))) {
17324 if (CC == X86::COND_NE &&
17325 CmpAgainst == dyn_cast<ConstantSDNode>(FalseOp)) {
17326 CC = X86::GetOppositeBranchCondition(CC);
17327 std::swap(TrueOp, FalseOp);
17330 if (CC == X86::COND_E &&
17331 CmpAgainst == dyn_cast<ConstantSDNode>(TrueOp)) {
17332 SDValue Ops[] = { FalseOp, Cond.getOperand(0),
17333 DAG.getConstant(CC, MVT::i8), Cond };
17334 return DAG.getNode(X86ISD::CMOV, DL, N->getVTList (), Ops,
17335 array_lengthof(Ops));
17343 /// PerformMulCombine - Optimize a single multiply with constant into two
17344 /// in order to implement it with two cheaper instructions, e.g.
17345 /// LEA + SHL, LEA + LEA.
17346 static SDValue PerformMulCombine(SDNode *N, SelectionDAG &DAG,
17347 TargetLowering::DAGCombinerInfo &DCI) {
17348 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer())
17351 EVT VT = N->getValueType(0);
17352 if (VT != MVT::i64)
17355 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
17358 uint64_t MulAmt = C->getZExtValue();
17359 if (isPowerOf2_64(MulAmt) || MulAmt == 3 || MulAmt == 5 || MulAmt == 9)
17362 uint64_t MulAmt1 = 0;
17363 uint64_t MulAmt2 = 0;
17364 if ((MulAmt % 9) == 0) {
17366 MulAmt2 = MulAmt / 9;
17367 } else if ((MulAmt % 5) == 0) {
17369 MulAmt2 = MulAmt / 5;
17370 } else if ((MulAmt % 3) == 0) {
17372 MulAmt2 = MulAmt / 3;
17375 (isPowerOf2_64(MulAmt2) || MulAmt2 == 3 || MulAmt2 == 5 || MulAmt2 == 9)){
17378 if (isPowerOf2_64(MulAmt2) &&
17379 !(N->hasOneUse() && N->use_begin()->getOpcode() == ISD::ADD))
17380 // If second multiplifer is pow2, issue it first. We want the multiply by
17381 // 3, 5, or 9 to be folded into the addressing mode unless the lone use
17383 std::swap(MulAmt1, MulAmt2);
17386 if (isPowerOf2_64(MulAmt1))
17387 NewMul = DAG.getNode(ISD::SHL, DL, VT, N->getOperand(0),
17388 DAG.getConstant(Log2_64(MulAmt1), MVT::i8));
17390 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, N->getOperand(0),
17391 DAG.getConstant(MulAmt1, VT));
17393 if (isPowerOf2_64(MulAmt2))
17394 NewMul = DAG.getNode(ISD::SHL, DL, VT, NewMul,
17395 DAG.getConstant(Log2_64(MulAmt2), MVT::i8));
17397 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, NewMul,
17398 DAG.getConstant(MulAmt2, VT));
17400 // Do not add new nodes to DAG combiner worklist.
17401 DCI.CombineTo(N, NewMul, false);
17406 static SDValue PerformSHLCombine(SDNode *N, SelectionDAG &DAG) {
17407 SDValue N0 = N->getOperand(0);
17408 SDValue N1 = N->getOperand(1);
17409 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
17410 EVT VT = N0.getValueType();
17412 // fold (shl (and (setcc_c), c1), c2) -> (and setcc_c, (c1 << c2))
17413 // since the result of setcc_c is all zero's or all ones.
17414 if (VT.isInteger() && !VT.isVector() &&
17415 N1C && N0.getOpcode() == ISD::AND &&
17416 N0.getOperand(1).getOpcode() == ISD::Constant) {
17417 SDValue N00 = N0.getOperand(0);
17418 if (N00.getOpcode() == X86ISD::SETCC_CARRY ||
17419 ((N00.getOpcode() == ISD::ANY_EXTEND ||
17420 N00.getOpcode() == ISD::ZERO_EXTEND) &&
17421 N00.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY)) {
17422 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
17423 APInt ShAmt = N1C->getAPIntValue();
17424 Mask = Mask.shl(ShAmt);
17426 return DAG.getNode(ISD::AND, SDLoc(N), VT,
17427 N00, DAG.getConstant(Mask, VT));
17431 // Hardware support for vector shifts is sparse which makes us scalarize the
17432 // vector operations in many cases. Also, on sandybridge ADD is faster than
17434 // (shl V, 1) -> add V,V
17435 if (isSplatVector(N1.getNode())) {
17436 assert(N0.getValueType().isVector() && "Invalid vector shift type");
17437 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1->getOperand(0));
17438 // We shift all of the values by one. In many cases we do not have
17439 // hardware support for this operation. This is better expressed as an ADD
17441 if (N1C && (1 == N1C->getZExtValue())) {
17442 return DAG.getNode(ISD::ADD, SDLoc(N), VT, N0, N0);
17449 /// \brief Returns a vector of 0s if the node in input is a vector logical
17450 /// shift by a constant amount which is known to be bigger than or equal
17451 /// to the vector element size in bits.
17452 static SDValue performShiftToAllZeros(SDNode *N, SelectionDAG &DAG,
17453 const X86Subtarget *Subtarget) {
17454 EVT VT = N->getValueType(0);
17456 if (VT != MVT::v2i64 && VT != MVT::v4i32 && VT != MVT::v8i16 &&
17457 (!Subtarget->hasInt256() ||
17458 (VT != MVT::v4i64 && VT != MVT::v8i32 && VT != MVT::v16i16)))
17461 SDValue Amt = N->getOperand(1);
17463 if (isSplatVector(Amt.getNode())) {
17464 SDValue SclrAmt = Amt->getOperand(0);
17465 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(SclrAmt)) {
17466 APInt ShiftAmt = C->getAPIntValue();
17467 unsigned MaxAmount = VT.getVectorElementType().getSizeInBits();
17469 // SSE2/AVX2 logical shifts always return a vector of 0s
17470 // if the shift amount is bigger than or equal to
17471 // the element size. The constant shift amount will be
17472 // encoded as a 8-bit immediate.
17473 if (ShiftAmt.trunc(8).uge(MaxAmount))
17474 return getZeroVector(VT, Subtarget, DAG, DL);
17481 /// PerformShiftCombine - Combine shifts.
17482 static SDValue PerformShiftCombine(SDNode* N, SelectionDAG &DAG,
17483 TargetLowering::DAGCombinerInfo &DCI,
17484 const X86Subtarget *Subtarget) {
17485 if (N->getOpcode() == ISD::SHL) {
17486 SDValue V = PerformSHLCombine(N, DAG);
17487 if (V.getNode()) return V;
17490 if (N->getOpcode() != ISD::SRA) {
17491 // Try to fold this logical shift into a zero vector.
17492 SDValue V = performShiftToAllZeros(N, DAG, Subtarget);
17493 if (V.getNode()) return V;
17499 // CMPEQCombine - Recognize the distinctive (AND (setcc ...) (setcc ..))
17500 // where both setccs reference the same FP CMP, and rewrite for CMPEQSS
17501 // and friends. Likewise for OR -> CMPNEQSS.
17502 static SDValue CMPEQCombine(SDNode *N, SelectionDAG &DAG,
17503 TargetLowering::DAGCombinerInfo &DCI,
17504 const X86Subtarget *Subtarget) {
17507 // SSE1 supports CMP{eq|ne}SS, and SSE2 added CMP{eq|ne}SD, but
17508 // we're requiring SSE2 for both.
17509 if (Subtarget->hasSSE2() && isAndOrOfSetCCs(SDValue(N, 0U), opcode)) {
17510 SDValue N0 = N->getOperand(0);
17511 SDValue N1 = N->getOperand(1);
17512 SDValue CMP0 = N0->getOperand(1);
17513 SDValue CMP1 = N1->getOperand(1);
17516 // The SETCCs should both refer to the same CMP.
17517 if (CMP0.getOpcode() != X86ISD::CMP || CMP0 != CMP1)
17520 SDValue CMP00 = CMP0->getOperand(0);
17521 SDValue CMP01 = CMP0->getOperand(1);
17522 EVT VT = CMP00.getValueType();
17524 if (VT == MVT::f32 || VT == MVT::f64) {
17525 bool ExpectingFlags = false;
17526 // Check for any users that want flags:
17527 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end();
17528 !ExpectingFlags && UI != UE; ++UI)
17529 switch (UI->getOpcode()) {
17534 ExpectingFlags = true;
17536 case ISD::CopyToReg:
17537 case ISD::SIGN_EXTEND:
17538 case ISD::ZERO_EXTEND:
17539 case ISD::ANY_EXTEND:
17543 if (!ExpectingFlags) {
17544 enum X86::CondCode cc0 = (enum X86::CondCode)N0.getConstantOperandVal(0);
17545 enum X86::CondCode cc1 = (enum X86::CondCode)N1.getConstantOperandVal(0);
17547 if (cc1 == X86::COND_E || cc1 == X86::COND_NE) {
17548 X86::CondCode tmp = cc0;
17553 if ((cc0 == X86::COND_E && cc1 == X86::COND_NP) ||
17554 (cc0 == X86::COND_NE && cc1 == X86::COND_P)) {
17555 bool is64BitFP = (CMP00.getValueType() == MVT::f64);
17556 X86ISD::NodeType NTOperator = is64BitFP ?
17557 X86ISD::FSETCCsd : X86ISD::FSETCCss;
17558 // FIXME: need symbolic constants for these magic numbers.
17559 // See X86ATTInstPrinter.cpp:printSSECC().
17560 unsigned x86cc = (cc0 == X86::COND_E) ? 0 : 4;
17561 SDValue OnesOrZeroesF = DAG.getNode(NTOperator, DL, MVT::f32, CMP00, CMP01,
17562 DAG.getConstant(x86cc, MVT::i8));
17563 SDValue OnesOrZeroesI = DAG.getNode(ISD::BITCAST, DL, MVT::i32,
17565 SDValue ANDed = DAG.getNode(ISD::AND, DL, MVT::i32, OnesOrZeroesI,
17566 DAG.getConstant(1, MVT::i32));
17567 SDValue OneBitOfTruth = DAG.getNode(ISD::TRUNCATE, DL, MVT::i8, ANDed);
17568 return OneBitOfTruth;
17576 /// CanFoldXORWithAllOnes - Test whether the XOR operand is a AllOnes vector
17577 /// so it can be folded inside ANDNP.
17578 static bool CanFoldXORWithAllOnes(const SDNode *N) {
17579 EVT VT = N->getValueType(0);
17581 // Match direct AllOnes for 128 and 256-bit vectors
17582 if (ISD::isBuildVectorAllOnes(N))
17585 // Look through a bit convert.
17586 if (N->getOpcode() == ISD::BITCAST)
17587 N = N->getOperand(0).getNode();
17589 // Sometimes the operand may come from a insert_subvector building a 256-bit
17591 if (VT.is256BitVector() &&
17592 N->getOpcode() == ISD::INSERT_SUBVECTOR) {
17593 SDValue V1 = N->getOperand(0);
17594 SDValue V2 = N->getOperand(1);
17596 if (V1.getOpcode() == ISD::INSERT_SUBVECTOR &&
17597 V1.getOperand(0).getOpcode() == ISD::UNDEF &&
17598 ISD::isBuildVectorAllOnes(V1.getOperand(1).getNode()) &&
17599 ISD::isBuildVectorAllOnes(V2.getNode()))
17606 // On AVX/AVX2 the type v8i1 is legalized to v8i16, which is an XMM sized
17607 // register. In most cases we actually compare or select YMM-sized registers
17608 // and mixing the two types creates horrible code. This method optimizes
17609 // some of the transition sequences.
17610 static SDValue WidenMaskArithmetic(SDNode *N, SelectionDAG &DAG,
17611 TargetLowering::DAGCombinerInfo &DCI,
17612 const X86Subtarget *Subtarget) {
17613 EVT VT = N->getValueType(0);
17614 if (!VT.is256BitVector())
17617 assert((N->getOpcode() == ISD::ANY_EXTEND ||
17618 N->getOpcode() == ISD::ZERO_EXTEND ||
17619 N->getOpcode() == ISD::SIGN_EXTEND) && "Invalid Node");
17621 SDValue Narrow = N->getOperand(0);
17622 EVT NarrowVT = Narrow->getValueType(0);
17623 if (!NarrowVT.is128BitVector())
17626 if (Narrow->getOpcode() != ISD::XOR &&
17627 Narrow->getOpcode() != ISD::AND &&
17628 Narrow->getOpcode() != ISD::OR)
17631 SDValue N0 = Narrow->getOperand(0);
17632 SDValue N1 = Narrow->getOperand(1);
17635 // The Left side has to be a trunc.
17636 if (N0.getOpcode() != ISD::TRUNCATE)
17639 // The type of the truncated inputs.
17640 EVT WideVT = N0->getOperand(0)->getValueType(0);
17644 // The right side has to be a 'trunc' or a constant vector.
17645 bool RHSTrunc = N1.getOpcode() == ISD::TRUNCATE;
17646 bool RHSConst = (isSplatVector(N1.getNode()) &&
17647 isa<ConstantSDNode>(N1->getOperand(0)));
17648 if (!RHSTrunc && !RHSConst)
17651 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
17653 if (!TLI.isOperationLegalOrPromote(Narrow->getOpcode(), WideVT))
17656 // Set N0 and N1 to hold the inputs to the new wide operation.
17657 N0 = N0->getOperand(0);
17659 N1 = DAG.getNode(ISD::ZERO_EXTEND, DL, WideVT.getScalarType(),
17660 N1->getOperand(0));
17661 SmallVector<SDValue, 8> C(WideVT.getVectorNumElements(), N1);
17662 N1 = DAG.getNode(ISD::BUILD_VECTOR, DL, WideVT, &C[0], C.size());
17663 } else if (RHSTrunc) {
17664 N1 = N1->getOperand(0);
17667 // Generate the wide operation.
17668 SDValue Op = DAG.getNode(Narrow->getOpcode(), DL, WideVT, N0, N1);
17669 unsigned Opcode = N->getOpcode();
17671 case ISD::ANY_EXTEND:
17673 case ISD::ZERO_EXTEND: {
17674 unsigned InBits = NarrowVT.getScalarType().getSizeInBits();
17675 APInt Mask = APInt::getAllOnesValue(InBits);
17676 Mask = Mask.zext(VT.getScalarType().getSizeInBits());
17677 return DAG.getNode(ISD::AND, DL, VT,
17678 Op, DAG.getConstant(Mask, VT));
17680 case ISD::SIGN_EXTEND:
17681 return DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, VT,
17682 Op, DAG.getValueType(NarrowVT));
17684 llvm_unreachable("Unexpected opcode");
17688 static SDValue PerformAndCombine(SDNode *N, SelectionDAG &DAG,
17689 TargetLowering::DAGCombinerInfo &DCI,
17690 const X86Subtarget *Subtarget) {
17691 EVT VT = N->getValueType(0);
17692 if (DCI.isBeforeLegalizeOps())
17695 SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget);
17699 // Create BLSI, BLSR, and BZHI instructions
17700 // BLSI is X & (-X)
17701 // BLSR is X & (X-1)
17702 // BZHI is X & ((1 << Y) - 1)
17703 // BEXTR is ((X >> imm) & (2**size-1))
17704 if (VT == MVT::i32 || VT == MVT::i64) {
17705 SDValue N0 = N->getOperand(0);
17706 SDValue N1 = N->getOperand(1);
17709 if (Subtarget->hasBMI()) {
17710 // Check LHS for neg
17711 if (N0.getOpcode() == ISD::SUB && N0.getOperand(1) == N1 &&
17712 isZero(N0.getOperand(0)))
17713 return DAG.getNode(X86ISD::BLSI, DL, VT, N1);
17715 // Check RHS for neg
17716 if (N1.getOpcode() == ISD::SUB && N1.getOperand(1) == N0 &&
17717 isZero(N1.getOperand(0)))
17718 return DAG.getNode(X86ISD::BLSI, DL, VT, N0);
17720 // Check LHS for X-1
17721 if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1 &&
17722 isAllOnes(N0.getOperand(1)))
17723 return DAG.getNode(X86ISD::BLSR, DL, VT, N1);
17725 // Check RHS for X-1
17726 if (N1.getOpcode() == ISD::ADD && N1.getOperand(0) == N0 &&
17727 isAllOnes(N1.getOperand(1)))
17728 return DAG.getNode(X86ISD::BLSR, DL, VT, N0);
17731 if (Subtarget->hasBMI2()) {
17732 // Check for (and (add (shl 1, Y), -1), X)
17733 if (N0.getOpcode() == ISD::ADD && isAllOnes(N0.getOperand(1))) {
17734 SDValue N00 = N0.getOperand(0);
17735 if (N00.getOpcode() == ISD::SHL) {
17736 SDValue N001 = N00.getOperand(1);
17737 assert(N001.getValueType() == MVT::i8 && "unexpected type");
17738 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N00.getOperand(0));
17739 if (C && C->getZExtValue() == 1)
17740 return DAG.getNode(X86ISD::BZHI, DL, VT, N1, N001);
17744 // Check for (and X, (add (shl 1, Y), -1))
17745 if (N1.getOpcode() == ISD::ADD && isAllOnes(N1.getOperand(1))) {
17746 SDValue N10 = N1.getOperand(0);
17747 if (N10.getOpcode() == ISD::SHL) {
17748 SDValue N101 = N10.getOperand(1);
17749 assert(N101.getValueType() == MVT::i8 && "unexpected type");
17750 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N10.getOperand(0));
17751 if (C && C->getZExtValue() == 1)
17752 return DAG.getNode(X86ISD::BZHI, DL, VT, N0, N101);
17757 // Check for BEXTR.
17758 if ((Subtarget->hasBMI() || Subtarget->hasTBM()) &&
17759 (N0.getOpcode() == ISD::SRA || N0.getOpcode() == ISD::SRL)) {
17760 ConstantSDNode *MaskNode = dyn_cast<ConstantSDNode>(N1);
17761 ConstantSDNode *ShiftNode = dyn_cast<ConstantSDNode>(N0.getOperand(1));
17762 if (MaskNode && ShiftNode) {
17763 uint64_t Mask = MaskNode->getZExtValue();
17764 uint64_t Shift = ShiftNode->getZExtValue();
17765 if (isMask_64(Mask)) {
17766 uint64_t MaskSize = CountPopulation_64(Mask);
17767 if (Shift + MaskSize <= VT.getSizeInBits())
17768 return DAG.getNode(X86ISD::BEXTR, DL, VT, N0.getOperand(0),
17769 DAG.getConstant(Shift | (MaskSize << 8), VT));
17777 // Want to form ANDNP nodes:
17778 // 1) In the hopes of then easily combining them with OR and AND nodes
17779 // to form PBLEND/PSIGN.
17780 // 2) To match ANDN packed intrinsics
17781 if (VT != MVT::v2i64 && VT != MVT::v4i64)
17784 SDValue N0 = N->getOperand(0);
17785 SDValue N1 = N->getOperand(1);
17788 // Check LHS for vnot
17789 if (N0.getOpcode() == ISD::XOR &&
17790 //ISD::isBuildVectorAllOnes(N0.getOperand(1).getNode()))
17791 CanFoldXORWithAllOnes(N0.getOperand(1).getNode()))
17792 return DAG.getNode(X86ISD::ANDNP, DL, VT, N0.getOperand(0), N1);
17794 // Check RHS for vnot
17795 if (N1.getOpcode() == ISD::XOR &&
17796 //ISD::isBuildVectorAllOnes(N1.getOperand(1).getNode()))
17797 CanFoldXORWithAllOnes(N1.getOperand(1).getNode()))
17798 return DAG.getNode(X86ISD::ANDNP, DL, VT, N1.getOperand(0), N0);
17803 static SDValue PerformOrCombine(SDNode *N, SelectionDAG &DAG,
17804 TargetLowering::DAGCombinerInfo &DCI,
17805 const X86Subtarget *Subtarget) {
17806 EVT VT = N->getValueType(0);
17807 if (DCI.isBeforeLegalizeOps())
17810 SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget);
17814 SDValue N0 = N->getOperand(0);
17815 SDValue N1 = N->getOperand(1);
17817 // look for psign/blend
17818 if (VT == MVT::v2i64 || VT == MVT::v4i64) {
17819 if (!Subtarget->hasSSSE3() ||
17820 (VT == MVT::v4i64 && !Subtarget->hasInt256()))
17823 // Canonicalize pandn to RHS
17824 if (N0.getOpcode() == X86ISD::ANDNP)
17826 // or (and (m, y), (pandn m, x))
17827 if (N0.getOpcode() == ISD::AND && N1.getOpcode() == X86ISD::ANDNP) {
17828 SDValue Mask = N1.getOperand(0);
17829 SDValue X = N1.getOperand(1);
17831 if (N0.getOperand(0) == Mask)
17832 Y = N0.getOperand(1);
17833 if (N0.getOperand(1) == Mask)
17834 Y = N0.getOperand(0);
17836 // Check to see if the mask appeared in both the AND and ANDNP and
17840 // Validate that X, Y, and Mask are BIT_CONVERTS, and see through them.
17841 // Look through mask bitcast.
17842 if (Mask.getOpcode() == ISD::BITCAST)
17843 Mask = Mask.getOperand(0);
17844 if (X.getOpcode() == ISD::BITCAST)
17845 X = X.getOperand(0);
17846 if (Y.getOpcode() == ISD::BITCAST)
17847 Y = Y.getOperand(0);
17849 EVT MaskVT = Mask.getValueType();
17851 // Validate that the Mask operand is a vector sra node.
17852 // FIXME: what to do for bytes, since there is a psignb/pblendvb, but
17853 // there is no psrai.b
17854 unsigned EltBits = MaskVT.getVectorElementType().getSizeInBits();
17855 unsigned SraAmt = ~0;
17856 if (Mask.getOpcode() == ISD::SRA) {
17857 SDValue Amt = Mask.getOperand(1);
17858 if (isSplatVector(Amt.getNode())) {
17859 SDValue SclrAmt = Amt->getOperand(0);
17860 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(SclrAmt))
17861 SraAmt = C->getZExtValue();
17863 } else if (Mask.getOpcode() == X86ISD::VSRAI) {
17864 SDValue SraC = Mask.getOperand(1);
17865 SraAmt = cast<ConstantSDNode>(SraC)->getZExtValue();
17867 if ((SraAmt + 1) != EltBits)
17872 // Now we know we at least have a plendvb with the mask val. See if
17873 // we can form a psignb/w/d.
17874 // psign = x.type == y.type == mask.type && y = sub(0, x);
17875 if (Y.getOpcode() == ISD::SUB && Y.getOperand(1) == X &&
17876 ISD::isBuildVectorAllZeros(Y.getOperand(0).getNode()) &&
17877 X.getValueType() == MaskVT && Y.getValueType() == MaskVT) {
17878 assert((EltBits == 8 || EltBits == 16 || EltBits == 32) &&
17879 "Unsupported VT for PSIGN");
17880 Mask = DAG.getNode(X86ISD::PSIGN, DL, MaskVT, X, Mask.getOperand(0));
17881 return DAG.getNode(ISD::BITCAST, DL, VT, Mask);
17883 // PBLENDVB only available on SSE 4.1
17884 if (!Subtarget->hasSSE41())
17887 EVT BlendVT = (VT == MVT::v4i64) ? MVT::v32i8 : MVT::v16i8;
17889 X = DAG.getNode(ISD::BITCAST, DL, BlendVT, X);
17890 Y = DAG.getNode(ISD::BITCAST, DL, BlendVT, Y);
17891 Mask = DAG.getNode(ISD::BITCAST, DL, BlendVT, Mask);
17892 Mask = DAG.getNode(ISD::VSELECT, DL, BlendVT, Mask, Y, X);
17893 return DAG.getNode(ISD::BITCAST, DL, VT, Mask);
17897 if (VT != MVT::i16 && VT != MVT::i32 && VT != MVT::i64)
17900 // fold (or (x << c) | (y >> (64 - c))) ==> (shld64 x, y, c)
17901 if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL)
17903 if (N0.getOpcode() != ISD::SHL || N1.getOpcode() != ISD::SRL)
17905 if (!N0.hasOneUse() || !N1.hasOneUse())
17908 SDValue ShAmt0 = N0.getOperand(1);
17909 if (ShAmt0.getValueType() != MVT::i8)
17911 SDValue ShAmt1 = N1.getOperand(1);
17912 if (ShAmt1.getValueType() != MVT::i8)
17914 if (ShAmt0.getOpcode() == ISD::TRUNCATE)
17915 ShAmt0 = ShAmt0.getOperand(0);
17916 if (ShAmt1.getOpcode() == ISD::TRUNCATE)
17917 ShAmt1 = ShAmt1.getOperand(0);
17920 unsigned Opc = X86ISD::SHLD;
17921 SDValue Op0 = N0.getOperand(0);
17922 SDValue Op1 = N1.getOperand(0);
17923 if (ShAmt0.getOpcode() == ISD::SUB) {
17924 Opc = X86ISD::SHRD;
17925 std::swap(Op0, Op1);
17926 std::swap(ShAmt0, ShAmt1);
17929 unsigned Bits = VT.getSizeInBits();
17930 if (ShAmt1.getOpcode() == ISD::SUB) {
17931 SDValue Sum = ShAmt1.getOperand(0);
17932 if (ConstantSDNode *SumC = dyn_cast<ConstantSDNode>(Sum)) {
17933 SDValue ShAmt1Op1 = ShAmt1.getOperand(1);
17934 if (ShAmt1Op1.getNode()->getOpcode() == ISD::TRUNCATE)
17935 ShAmt1Op1 = ShAmt1Op1.getOperand(0);
17936 if (SumC->getSExtValue() == Bits && ShAmt1Op1 == ShAmt0)
17937 return DAG.getNode(Opc, DL, VT,
17939 DAG.getNode(ISD::TRUNCATE, DL,
17942 } else if (ConstantSDNode *ShAmt1C = dyn_cast<ConstantSDNode>(ShAmt1)) {
17943 ConstantSDNode *ShAmt0C = dyn_cast<ConstantSDNode>(ShAmt0);
17945 ShAmt0C->getSExtValue() + ShAmt1C->getSExtValue() == Bits)
17946 return DAG.getNode(Opc, DL, VT,
17947 N0.getOperand(0), N1.getOperand(0),
17948 DAG.getNode(ISD::TRUNCATE, DL,
17955 // Generate NEG and CMOV for integer abs.
17956 static SDValue performIntegerAbsCombine(SDNode *N, SelectionDAG &DAG) {
17957 EVT VT = N->getValueType(0);
17959 // Since X86 does not have CMOV for 8-bit integer, we don't convert
17960 // 8-bit integer abs to NEG and CMOV.
17961 if (VT.isInteger() && VT.getSizeInBits() == 8)
17964 SDValue N0 = N->getOperand(0);
17965 SDValue N1 = N->getOperand(1);
17968 // Check pattern of XOR(ADD(X,Y), Y) where Y is SRA(X, size(X)-1)
17969 // and change it to SUB and CMOV.
17970 if (VT.isInteger() && N->getOpcode() == ISD::XOR &&
17971 N0.getOpcode() == ISD::ADD &&
17972 N0.getOperand(1) == N1 &&
17973 N1.getOpcode() == ISD::SRA &&
17974 N1.getOperand(0) == N0.getOperand(0))
17975 if (ConstantSDNode *Y1C = dyn_cast<ConstantSDNode>(N1.getOperand(1)))
17976 if (Y1C->getAPIntValue() == VT.getSizeInBits()-1) {
17977 // Generate SUB & CMOV.
17978 SDValue Neg = DAG.getNode(X86ISD::SUB, DL, DAG.getVTList(VT, MVT::i32),
17979 DAG.getConstant(0, VT), N0.getOperand(0));
17981 SDValue Ops[] = { N0.getOperand(0), Neg,
17982 DAG.getConstant(X86::COND_GE, MVT::i8),
17983 SDValue(Neg.getNode(), 1) };
17984 return DAG.getNode(X86ISD::CMOV, DL, DAG.getVTList(VT, MVT::Glue),
17985 Ops, array_lengthof(Ops));
17990 // PerformXorCombine - Attempts to turn XOR nodes into BLSMSK nodes
17991 static SDValue PerformXorCombine(SDNode *N, SelectionDAG &DAG,
17992 TargetLowering::DAGCombinerInfo &DCI,
17993 const X86Subtarget *Subtarget) {
17994 EVT VT = N->getValueType(0);
17995 if (DCI.isBeforeLegalizeOps())
17998 if (Subtarget->hasCMov()) {
17999 SDValue RV = performIntegerAbsCombine(N, DAG);
18004 // Try forming BMI if it is available.
18005 if (!Subtarget->hasBMI())
18008 if (VT != MVT::i32 && VT != MVT::i64)
18011 assert(Subtarget->hasBMI() && "Creating BLSMSK requires BMI instructions");
18013 // Create BLSMSK instructions by finding X ^ (X-1)
18014 SDValue N0 = N->getOperand(0);
18015 SDValue N1 = N->getOperand(1);
18018 if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1 &&
18019 isAllOnes(N0.getOperand(1)))
18020 return DAG.getNode(X86ISD::BLSMSK, DL, VT, N1);
18022 if (N1.getOpcode() == ISD::ADD && N1.getOperand(0) == N0 &&
18023 isAllOnes(N1.getOperand(1)))
18024 return DAG.getNode(X86ISD::BLSMSK, DL, VT, N0);
18029 /// PerformLOADCombine - Do target-specific dag combines on LOAD nodes.
18030 static SDValue PerformLOADCombine(SDNode *N, SelectionDAG &DAG,
18031 TargetLowering::DAGCombinerInfo &DCI,
18032 const X86Subtarget *Subtarget) {
18033 LoadSDNode *Ld = cast<LoadSDNode>(N);
18034 EVT RegVT = Ld->getValueType(0);
18035 EVT MemVT = Ld->getMemoryVT();
18037 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
18038 unsigned RegSz = RegVT.getSizeInBits();
18040 // On Sandybridge unaligned 256bit loads are inefficient.
18041 ISD::LoadExtType Ext = Ld->getExtensionType();
18042 unsigned Alignment = Ld->getAlignment();
18043 bool IsAligned = Alignment == 0 || Alignment >= MemVT.getSizeInBits()/8;
18044 if (RegVT.is256BitVector() && !Subtarget->hasInt256() &&
18045 !DCI.isBeforeLegalizeOps() && !IsAligned && Ext == ISD::NON_EXTLOAD) {
18046 unsigned NumElems = RegVT.getVectorNumElements();
18050 SDValue Ptr = Ld->getBasePtr();
18051 SDValue Increment = DAG.getConstant(16, TLI.getPointerTy());
18053 EVT HalfVT = EVT::getVectorVT(*DAG.getContext(), MemVT.getScalarType(),
18055 SDValue Load1 = DAG.getLoad(HalfVT, dl, Ld->getChain(), Ptr,
18056 Ld->getPointerInfo(), Ld->isVolatile(),
18057 Ld->isNonTemporal(), Ld->isInvariant(),
18059 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
18060 SDValue Load2 = DAG.getLoad(HalfVT, dl, Ld->getChain(), Ptr,
18061 Ld->getPointerInfo(), Ld->isVolatile(),
18062 Ld->isNonTemporal(), Ld->isInvariant(),
18063 std::min(16U, Alignment));
18064 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
18066 Load2.getValue(1));
18068 SDValue NewVec = DAG.getUNDEF(RegVT);
18069 NewVec = Insert128BitVector(NewVec, Load1, 0, DAG, dl);
18070 NewVec = Insert128BitVector(NewVec, Load2, NumElems/2, DAG, dl);
18071 return DCI.CombineTo(N, NewVec, TF, true);
18074 // If this is a vector EXT Load then attempt to optimize it using a
18075 // shuffle. If SSSE3 is not available we may emit an illegal shuffle but the
18076 // expansion is still better than scalar code.
18077 // We generate X86ISD::VSEXT for SEXTLOADs if it's available, otherwise we'll
18078 // emit a shuffle and a arithmetic shift.
18079 // TODO: It is possible to support ZExt by zeroing the undef values
18080 // during the shuffle phase or after the shuffle.
18081 if (RegVT.isVector() && RegVT.isInteger() && Subtarget->hasSSE2() &&
18082 (Ext == ISD::EXTLOAD || Ext == ISD::SEXTLOAD)) {
18083 assert(MemVT != RegVT && "Cannot extend to the same type");
18084 assert(MemVT.isVector() && "Must load a vector from memory");
18086 unsigned NumElems = RegVT.getVectorNumElements();
18087 unsigned MemSz = MemVT.getSizeInBits();
18088 assert(RegSz > MemSz && "Register size must be greater than the mem size");
18090 if (Ext == ISD::SEXTLOAD && RegSz == 256 && !Subtarget->hasInt256())
18093 // All sizes must be a power of two.
18094 if (!isPowerOf2_32(RegSz * MemSz * NumElems))
18097 // Attempt to load the original value using scalar loads.
18098 // Find the largest scalar type that divides the total loaded size.
18099 MVT SclrLoadTy = MVT::i8;
18100 for (unsigned tp = MVT::FIRST_INTEGER_VALUETYPE;
18101 tp < MVT::LAST_INTEGER_VALUETYPE; ++tp) {
18102 MVT Tp = (MVT::SimpleValueType)tp;
18103 if (TLI.isTypeLegal(Tp) && ((MemSz % Tp.getSizeInBits()) == 0)) {
18108 // On 32bit systems, we can't save 64bit integers. Try bitcasting to F64.
18109 if (TLI.isTypeLegal(MVT::f64) && SclrLoadTy.getSizeInBits() < 64 &&
18111 SclrLoadTy = MVT::f64;
18113 // Calculate the number of scalar loads that we need to perform
18114 // in order to load our vector from memory.
18115 unsigned NumLoads = MemSz / SclrLoadTy.getSizeInBits();
18116 if (Ext == ISD::SEXTLOAD && NumLoads > 1)
18119 unsigned loadRegZize = RegSz;
18120 if (Ext == ISD::SEXTLOAD && RegSz == 256)
18123 // Represent our vector as a sequence of elements which are the
18124 // largest scalar that we can load.
18125 EVT LoadUnitVecVT = EVT::getVectorVT(*DAG.getContext(), SclrLoadTy,
18126 loadRegZize/SclrLoadTy.getSizeInBits());
18128 // Represent the data using the same element type that is stored in
18129 // memory. In practice, we ''widen'' MemVT.
18131 EVT::getVectorVT(*DAG.getContext(), MemVT.getScalarType(),
18132 loadRegZize/MemVT.getScalarType().getSizeInBits());
18134 assert(WideVecVT.getSizeInBits() == LoadUnitVecVT.getSizeInBits() &&
18135 "Invalid vector type");
18137 // We can't shuffle using an illegal type.
18138 if (!TLI.isTypeLegal(WideVecVT))
18141 SmallVector<SDValue, 8> Chains;
18142 SDValue Ptr = Ld->getBasePtr();
18143 SDValue Increment = DAG.getConstant(SclrLoadTy.getSizeInBits()/8,
18144 TLI.getPointerTy());
18145 SDValue Res = DAG.getUNDEF(LoadUnitVecVT);
18147 for (unsigned i = 0; i < NumLoads; ++i) {
18148 // Perform a single load.
18149 SDValue ScalarLoad = DAG.getLoad(SclrLoadTy, dl, Ld->getChain(),
18150 Ptr, Ld->getPointerInfo(),
18151 Ld->isVolatile(), Ld->isNonTemporal(),
18152 Ld->isInvariant(), Ld->getAlignment());
18153 Chains.push_back(ScalarLoad.getValue(1));
18154 // Create the first element type using SCALAR_TO_VECTOR in order to avoid
18155 // another round of DAGCombining.
18157 Res = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, LoadUnitVecVT, ScalarLoad);
18159 Res = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, LoadUnitVecVT, Res,
18160 ScalarLoad, DAG.getIntPtrConstant(i));
18162 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
18165 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Chains[0],
18168 // Bitcast the loaded value to a vector of the original element type, in
18169 // the size of the target vector type.
18170 SDValue SlicedVec = DAG.getNode(ISD::BITCAST, dl, WideVecVT, Res);
18171 unsigned SizeRatio = RegSz/MemSz;
18173 if (Ext == ISD::SEXTLOAD) {
18174 // If we have SSE4.1 we can directly emit a VSEXT node.
18175 if (Subtarget->hasSSE41()) {
18176 SDValue Sext = DAG.getNode(X86ISD::VSEXT, dl, RegVT, SlicedVec);
18177 return DCI.CombineTo(N, Sext, TF, true);
18180 // Otherwise we'll shuffle the small elements in the high bits of the
18181 // larger type and perform an arithmetic shift. If the shift is not legal
18182 // it's better to scalarize.
18183 if (!TLI.isOperationLegalOrCustom(ISD::SRA, RegVT))
18186 // Redistribute the loaded elements into the different locations.
18187 SmallVector<int, 8> ShuffleVec(NumElems * SizeRatio, -1);
18188 for (unsigned i = 0; i != NumElems; ++i)
18189 ShuffleVec[i*SizeRatio + SizeRatio-1] = i;
18191 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, SlicedVec,
18192 DAG.getUNDEF(WideVecVT),
18195 Shuff = DAG.getNode(ISD::BITCAST, dl, RegVT, Shuff);
18197 // Build the arithmetic shift.
18198 unsigned Amt = RegVT.getVectorElementType().getSizeInBits() -
18199 MemVT.getVectorElementType().getSizeInBits();
18200 Shuff = DAG.getNode(ISD::SRA, dl, RegVT, Shuff,
18201 DAG.getConstant(Amt, RegVT));
18203 return DCI.CombineTo(N, Shuff, TF, true);
18206 // Redistribute the loaded elements into the different locations.
18207 SmallVector<int, 8> ShuffleVec(NumElems * SizeRatio, -1);
18208 for (unsigned i = 0; i != NumElems; ++i)
18209 ShuffleVec[i*SizeRatio] = i;
18211 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, SlicedVec,
18212 DAG.getUNDEF(WideVecVT),
18215 // Bitcast to the requested type.
18216 Shuff = DAG.getNode(ISD::BITCAST, dl, RegVT, Shuff);
18217 // Replace the original load with the new sequence
18218 // and return the new chain.
18219 return DCI.CombineTo(N, Shuff, TF, true);
18225 /// PerformSTORECombine - Do target-specific dag combines on STORE nodes.
18226 static SDValue PerformSTORECombine(SDNode *N, SelectionDAG &DAG,
18227 const X86Subtarget *Subtarget) {
18228 StoreSDNode *St = cast<StoreSDNode>(N);
18229 EVT VT = St->getValue().getValueType();
18230 EVT StVT = St->getMemoryVT();
18232 SDValue StoredVal = St->getOperand(1);
18233 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
18235 // If we are saving a concatenation of two XMM registers, perform two stores.
18236 // On Sandy Bridge, 256-bit memory operations are executed by two
18237 // 128-bit ports. However, on Haswell it is better to issue a single 256-bit
18238 // memory operation.
18239 unsigned Alignment = St->getAlignment();
18240 bool IsAligned = Alignment == 0 || Alignment >= VT.getSizeInBits()/8;
18241 if (VT.is256BitVector() && !Subtarget->hasInt256() &&
18242 StVT == VT && !IsAligned) {
18243 unsigned NumElems = VT.getVectorNumElements();
18247 SDValue Value0 = Extract128BitVector(StoredVal, 0, DAG, dl);
18248 SDValue Value1 = Extract128BitVector(StoredVal, NumElems/2, DAG, dl);
18250 SDValue Stride = DAG.getConstant(16, TLI.getPointerTy());
18251 SDValue Ptr0 = St->getBasePtr();
18252 SDValue Ptr1 = DAG.getNode(ISD::ADD, dl, Ptr0.getValueType(), Ptr0, Stride);
18254 SDValue Ch0 = DAG.getStore(St->getChain(), dl, Value0, Ptr0,
18255 St->getPointerInfo(), St->isVolatile(),
18256 St->isNonTemporal(), Alignment);
18257 SDValue Ch1 = DAG.getStore(St->getChain(), dl, Value1, Ptr1,
18258 St->getPointerInfo(), St->isVolatile(),
18259 St->isNonTemporal(),
18260 std::min(16U, Alignment));
18261 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Ch0, Ch1);
18264 // Optimize trunc store (of multiple scalars) to shuffle and store.
18265 // First, pack all of the elements in one place. Next, store to memory
18266 // in fewer chunks.
18267 if (St->isTruncatingStore() && VT.isVector()) {
18268 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
18269 unsigned NumElems = VT.getVectorNumElements();
18270 assert(StVT != VT && "Cannot truncate to the same type");
18271 unsigned FromSz = VT.getVectorElementType().getSizeInBits();
18272 unsigned ToSz = StVT.getVectorElementType().getSizeInBits();
18274 // From, To sizes and ElemCount must be pow of two
18275 if (!isPowerOf2_32(NumElems * FromSz * ToSz)) return SDValue();
18276 // We are going to use the original vector elt for storing.
18277 // Accumulated smaller vector elements must be a multiple of the store size.
18278 if (0 != (NumElems * FromSz) % ToSz) return SDValue();
18280 unsigned SizeRatio = FromSz / ToSz;
18282 assert(SizeRatio * NumElems * ToSz == VT.getSizeInBits());
18284 // Create a type on which we perform the shuffle
18285 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(),
18286 StVT.getScalarType(), NumElems*SizeRatio);
18288 assert(WideVecVT.getSizeInBits() == VT.getSizeInBits());
18290 SDValue WideVec = DAG.getNode(ISD::BITCAST, dl, WideVecVT, St->getValue());
18291 SmallVector<int, 8> ShuffleVec(NumElems * SizeRatio, -1);
18292 for (unsigned i = 0; i != NumElems; ++i)
18293 ShuffleVec[i] = i * SizeRatio;
18295 // Can't shuffle using an illegal type.
18296 if (!TLI.isTypeLegal(WideVecVT))
18299 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, WideVec,
18300 DAG.getUNDEF(WideVecVT),
18302 // At this point all of the data is stored at the bottom of the
18303 // register. We now need to save it to mem.
18305 // Find the largest store unit
18306 MVT StoreType = MVT::i8;
18307 for (unsigned tp = MVT::FIRST_INTEGER_VALUETYPE;
18308 tp < MVT::LAST_INTEGER_VALUETYPE; ++tp) {
18309 MVT Tp = (MVT::SimpleValueType)tp;
18310 if (TLI.isTypeLegal(Tp) && Tp.getSizeInBits() <= NumElems * ToSz)
18314 // On 32bit systems, we can't save 64bit integers. Try bitcasting to F64.
18315 if (TLI.isTypeLegal(MVT::f64) && StoreType.getSizeInBits() < 64 &&
18316 (64 <= NumElems * ToSz))
18317 StoreType = MVT::f64;
18319 // Bitcast the original vector into a vector of store-size units
18320 EVT StoreVecVT = EVT::getVectorVT(*DAG.getContext(),
18321 StoreType, VT.getSizeInBits()/StoreType.getSizeInBits());
18322 assert(StoreVecVT.getSizeInBits() == VT.getSizeInBits());
18323 SDValue ShuffWide = DAG.getNode(ISD::BITCAST, dl, StoreVecVT, Shuff);
18324 SmallVector<SDValue, 8> Chains;
18325 SDValue Increment = DAG.getConstant(StoreType.getSizeInBits()/8,
18326 TLI.getPointerTy());
18327 SDValue Ptr = St->getBasePtr();
18329 // Perform one or more big stores into memory.
18330 for (unsigned i=0, e=(ToSz*NumElems)/StoreType.getSizeInBits(); i!=e; ++i) {
18331 SDValue SubVec = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
18332 StoreType, ShuffWide,
18333 DAG.getIntPtrConstant(i));
18334 SDValue Ch = DAG.getStore(St->getChain(), dl, SubVec, Ptr,
18335 St->getPointerInfo(), St->isVolatile(),
18336 St->isNonTemporal(), St->getAlignment());
18337 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
18338 Chains.push_back(Ch);
18341 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Chains[0],
18345 // Turn load->store of MMX types into GPR load/stores. This avoids clobbering
18346 // the FP state in cases where an emms may be missing.
18347 // A preferable solution to the general problem is to figure out the right
18348 // places to insert EMMS. This qualifies as a quick hack.
18350 // Similarly, turn load->store of i64 into double load/stores in 32-bit mode.
18351 if (VT.getSizeInBits() != 64)
18354 const Function *F = DAG.getMachineFunction().getFunction();
18355 bool NoImplicitFloatOps = F->getAttributes().
18356 hasAttribute(AttributeSet::FunctionIndex, Attribute::NoImplicitFloat);
18357 bool F64IsLegal = !DAG.getTarget().Options.UseSoftFloat && !NoImplicitFloatOps
18358 && Subtarget->hasSSE2();
18359 if ((VT.isVector() ||
18360 (VT == MVT::i64 && F64IsLegal && !Subtarget->is64Bit())) &&
18361 isa<LoadSDNode>(St->getValue()) &&
18362 !cast<LoadSDNode>(St->getValue())->isVolatile() &&
18363 St->getChain().hasOneUse() && !St->isVolatile()) {
18364 SDNode* LdVal = St->getValue().getNode();
18365 LoadSDNode *Ld = 0;
18366 int TokenFactorIndex = -1;
18367 SmallVector<SDValue, 8> Ops;
18368 SDNode* ChainVal = St->getChain().getNode();
18369 // Must be a store of a load. We currently handle two cases: the load
18370 // is a direct child, and it's under an intervening TokenFactor. It is
18371 // possible to dig deeper under nested TokenFactors.
18372 if (ChainVal == LdVal)
18373 Ld = cast<LoadSDNode>(St->getChain());
18374 else if (St->getValue().hasOneUse() &&
18375 ChainVal->getOpcode() == ISD::TokenFactor) {
18376 for (unsigned i = 0, e = ChainVal->getNumOperands(); i != e; ++i) {
18377 if (ChainVal->getOperand(i).getNode() == LdVal) {
18378 TokenFactorIndex = i;
18379 Ld = cast<LoadSDNode>(St->getValue());
18381 Ops.push_back(ChainVal->getOperand(i));
18385 if (!Ld || !ISD::isNormalLoad(Ld))
18388 // If this is not the MMX case, i.e. we are just turning i64 load/store
18389 // into f64 load/store, avoid the transformation if there are multiple
18390 // uses of the loaded value.
18391 if (!VT.isVector() && !Ld->hasNUsesOfValue(1, 0))
18396 // If we are a 64-bit capable x86, lower to a single movq load/store pair.
18397 // Otherwise, if it's legal to use f64 SSE instructions, use f64 load/store
18399 if (Subtarget->is64Bit() || F64IsLegal) {
18400 EVT LdVT = Subtarget->is64Bit() ? MVT::i64 : MVT::f64;
18401 SDValue NewLd = DAG.getLoad(LdVT, LdDL, Ld->getChain(), Ld->getBasePtr(),
18402 Ld->getPointerInfo(), Ld->isVolatile(),
18403 Ld->isNonTemporal(), Ld->isInvariant(),
18404 Ld->getAlignment());
18405 SDValue NewChain = NewLd.getValue(1);
18406 if (TokenFactorIndex != -1) {
18407 Ops.push_back(NewChain);
18408 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, &Ops[0],
18411 return DAG.getStore(NewChain, StDL, NewLd, St->getBasePtr(),
18412 St->getPointerInfo(),
18413 St->isVolatile(), St->isNonTemporal(),
18414 St->getAlignment());
18417 // Otherwise, lower to two pairs of 32-bit loads / stores.
18418 SDValue LoAddr = Ld->getBasePtr();
18419 SDValue HiAddr = DAG.getNode(ISD::ADD, LdDL, MVT::i32, LoAddr,
18420 DAG.getConstant(4, MVT::i32));
18422 SDValue LoLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), LoAddr,
18423 Ld->getPointerInfo(),
18424 Ld->isVolatile(), Ld->isNonTemporal(),
18425 Ld->isInvariant(), Ld->getAlignment());
18426 SDValue HiLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), HiAddr,
18427 Ld->getPointerInfo().getWithOffset(4),
18428 Ld->isVolatile(), Ld->isNonTemporal(),
18430 MinAlign(Ld->getAlignment(), 4));
18432 SDValue NewChain = LoLd.getValue(1);
18433 if (TokenFactorIndex != -1) {
18434 Ops.push_back(LoLd);
18435 Ops.push_back(HiLd);
18436 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, &Ops[0],
18440 LoAddr = St->getBasePtr();
18441 HiAddr = DAG.getNode(ISD::ADD, StDL, MVT::i32, LoAddr,
18442 DAG.getConstant(4, MVT::i32));
18444 SDValue LoSt = DAG.getStore(NewChain, StDL, LoLd, LoAddr,
18445 St->getPointerInfo(),
18446 St->isVolatile(), St->isNonTemporal(),
18447 St->getAlignment());
18448 SDValue HiSt = DAG.getStore(NewChain, StDL, HiLd, HiAddr,
18449 St->getPointerInfo().getWithOffset(4),
18451 St->isNonTemporal(),
18452 MinAlign(St->getAlignment(), 4));
18453 return DAG.getNode(ISD::TokenFactor, StDL, MVT::Other, LoSt, HiSt);
18458 /// isHorizontalBinOp - Return 'true' if this vector operation is "horizontal"
18459 /// and return the operands for the horizontal operation in LHS and RHS. A
18460 /// horizontal operation performs the binary operation on successive elements
18461 /// of its first operand, then on successive elements of its second operand,
18462 /// returning the resulting values in a vector. For example, if
18463 /// A = < float a0, float a1, float a2, float a3 >
18465 /// B = < float b0, float b1, float b2, float b3 >
18466 /// then the result of doing a horizontal operation on A and B is
18467 /// A horizontal-op B = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >.
18468 /// In short, LHS and RHS are inspected to see if LHS op RHS is of the form
18469 /// A horizontal-op B, for some already available A and B, and if so then LHS is
18470 /// set to A, RHS to B, and the routine returns 'true'.
18471 /// Note that the binary operation should have the property that if one of the
18472 /// operands is UNDEF then the result is UNDEF.
18473 static bool isHorizontalBinOp(SDValue &LHS, SDValue &RHS, bool IsCommutative) {
18474 // Look for the following pattern: if
18475 // A = < float a0, float a1, float a2, float a3 >
18476 // B = < float b0, float b1, float b2, float b3 >
18478 // LHS = VECTOR_SHUFFLE A, B, <0, 2, 4, 6>
18479 // RHS = VECTOR_SHUFFLE A, B, <1, 3, 5, 7>
18480 // then LHS op RHS = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >
18481 // which is A horizontal-op B.
18483 // At least one of the operands should be a vector shuffle.
18484 if (LHS.getOpcode() != ISD::VECTOR_SHUFFLE &&
18485 RHS.getOpcode() != ISD::VECTOR_SHUFFLE)
18488 MVT VT = LHS.getSimpleValueType();
18490 assert((VT.is128BitVector() || VT.is256BitVector()) &&
18491 "Unsupported vector type for horizontal add/sub");
18493 // Handle 128 and 256-bit vector lengths. AVX defines horizontal add/sub to
18494 // operate independently on 128-bit lanes.
18495 unsigned NumElts = VT.getVectorNumElements();
18496 unsigned NumLanes = VT.getSizeInBits()/128;
18497 unsigned NumLaneElts = NumElts / NumLanes;
18498 assert((NumLaneElts % 2 == 0) &&
18499 "Vector type should have an even number of elements in each lane");
18500 unsigned HalfLaneElts = NumLaneElts/2;
18502 // View LHS in the form
18503 // LHS = VECTOR_SHUFFLE A, B, LMask
18504 // If LHS is not a shuffle then pretend it is the shuffle
18505 // LHS = VECTOR_SHUFFLE LHS, undef, <0, 1, ..., N-1>
18506 // NOTE: in what follows a default initialized SDValue represents an UNDEF of
18509 SmallVector<int, 16> LMask(NumElts);
18510 if (LHS.getOpcode() == ISD::VECTOR_SHUFFLE) {
18511 if (LHS.getOperand(0).getOpcode() != ISD::UNDEF)
18512 A = LHS.getOperand(0);
18513 if (LHS.getOperand(1).getOpcode() != ISD::UNDEF)
18514 B = LHS.getOperand(1);
18515 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(LHS.getNode())->getMask();
18516 std::copy(Mask.begin(), Mask.end(), LMask.begin());
18518 if (LHS.getOpcode() != ISD::UNDEF)
18520 for (unsigned i = 0; i != NumElts; ++i)
18524 // Likewise, view RHS in the form
18525 // RHS = VECTOR_SHUFFLE C, D, RMask
18527 SmallVector<int, 16> RMask(NumElts);
18528 if (RHS.getOpcode() == ISD::VECTOR_SHUFFLE) {
18529 if (RHS.getOperand(0).getOpcode() != ISD::UNDEF)
18530 C = RHS.getOperand(0);
18531 if (RHS.getOperand(1).getOpcode() != ISD::UNDEF)
18532 D = RHS.getOperand(1);
18533 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(RHS.getNode())->getMask();
18534 std::copy(Mask.begin(), Mask.end(), RMask.begin());
18536 if (RHS.getOpcode() != ISD::UNDEF)
18538 for (unsigned i = 0; i != NumElts; ++i)
18542 // Check that the shuffles are both shuffling the same vectors.
18543 if (!(A == C && B == D) && !(A == D && B == C))
18546 // If everything is UNDEF then bail out: it would be better to fold to UNDEF.
18547 if (!A.getNode() && !B.getNode())
18550 // If A and B occur in reverse order in RHS, then "swap" them (which means
18551 // rewriting the mask).
18553 CommuteVectorShuffleMask(RMask, NumElts);
18555 // At this point LHS and RHS are equivalent to
18556 // LHS = VECTOR_SHUFFLE A, B, LMask
18557 // RHS = VECTOR_SHUFFLE A, B, RMask
18558 // Check that the masks correspond to performing a horizontal operation.
18559 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
18560 for (unsigned i = 0; i != NumLaneElts; ++i) {
18561 int LIdx = LMask[i+l], RIdx = RMask[i+l];
18563 // Ignore any UNDEF components.
18564 if (LIdx < 0 || RIdx < 0 ||
18565 (!A.getNode() && (LIdx < (int)NumElts || RIdx < (int)NumElts)) ||
18566 (!B.getNode() && (LIdx >= (int)NumElts || RIdx >= (int)NumElts)))
18569 // Check that successive elements are being operated on. If not, this is
18570 // not a horizontal operation.
18571 unsigned Src = (i/HalfLaneElts); // each lane is split between srcs
18572 int Index = 2*(i%HalfLaneElts) + NumElts*Src + l;
18573 if (!(LIdx == Index && RIdx == Index + 1) &&
18574 !(IsCommutative && LIdx == Index + 1 && RIdx == Index))
18579 LHS = A.getNode() ? A : B; // If A is 'UNDEF', use B for it.
18580 RHS = B.getNode() ? B : A; // If B is 'UNDEF', use A for it.
18584 /// PerformFADDCombine - Do target-specific dag combines on floating point adds.
18585 static SDValue PerformFADDCombine(SDNode *N, SelectionDAG &DAG,
18586 const X86Subtarget *Subtarget) {
18587 EVT VT = N->getValueType(0);
18588 SDValue LHS = N->getOperand(0);
18589 SDValue RHS = N->getOperand(1);
18591 // Try to synthesize horizontal adds from adds of shuffles.
18592 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
18593 (Subtarget->hasFp256() && (VT == MVT::v8f32 || VT == MVT::v4f64))) &&
18594 isHorizontalBinOp(LHS, RHS, true))
18595 return DAG.getNode(X86ISD::FHADD, SDLoc(N), VT, LHS, RHS);
18599 /// PerformFSUBCombine - Do target-specific dag combines on floating point subs.
18600 static SDValue PerformFSUBCombine(SDNode *N, SelectionDAG &DAG,
18601 const X86Subtarget *Subtarget) {
18602 EVT VT = N->getValueType(0);
18603 SDValue LHS = N->getOperand(0);
18604 SDValue RHS = N->getOperand(1);
18606 // Try to synthesize horizontal subs from subs of shuffles.
18607 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
18608 (Subtarget->hasFp256() && (VT == MVT::v8f32 || VT == MVT::v4f64))) &&
18609 isHorizontalBinOp(LHS, RHS, false))
18610 return DAG.getNode(X86ISD::FHSUB, SDLoc(N), VT, LHS, RHS);
18614 /// PerformFORCombine - Do target-specific dag combines on X86ISD::FOR and
18615 /// X86ISD::FXOR nodes.
18616 static SDValue PerformFORCombine(SDNode *N, SelectionDAG &DAG) {
18617 assert(N->getOpcode() == X86ISD::FOR || N->getOpcode() == X86ISD::FXOR);
18618 // F[X]OR(0.0, x) -> x
18619 // F[X]OR(x, 0.0) -> x
18620 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
18621 if (C->getValueAPF().isPosZero())
18622 return N->getOperand(1);
18623 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
18624 if (C->getValueAPF().isPosZero())
18625 return N->getOperand(0);
18629 /// PerformFMinFMaxCombine - Do target-specific dag combines on X86ISD::FMIN and
18630 /// X86ISD::FMAX nodes.
18631 static SDValue PerformFMinFMaxCombine(SDNode *N, SelectionDAG &DAG) {
18632 assert(N->getOpcode() == X86ISD::FMIN || N->getOpcode() == X86ISD::FMAX);
18634 // Only perform optimizations if UnsafeMath is used.
18635 if (!DAG.getTarget().Options.UnsafeFPMath)
18638 // If we run in unsafe-math mode, then convert the FMAX and FMIN nodes
18639 // into FMINC and FMAXC, which are Commutative operations.
18640 unsigned NewOp = 0;
18641 switch (N->getOpcode()) {
18642 default: llvm_unreachable("unknown opcode");
18643 case X86ISD::FMIN: NewOp = X86ISD::FMINC; break;
18644 case X86ISD::FMAX: NewOp = X86ISD::FMAXC; break;
18647 return DAG.getNode(NewOp, SDLoc(N), N->getValueType(0),
18648 N->getOperand(0), N->getOperand(1));
18651 /// PerformFANDCombine - Do target-specific dag combines on X86ISD::FAND nodes.
18652 static SDValue PerformFANDCombine(SDNode *N, SelectionDAG &DAG) {
18653 // FAND(0.0, x) -> 0.0
18654 // FAND(x, 0.0) -> 0.0
18655 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
18656 if (C->getValueAPF().isPosZero())
18657 return N->getOperand(0);
18658 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
18659 if (C->getValueAPF().isPosZero())
18660 return N->getOperand(1);
18664 /// PerformFANDNCombine - Do target-specific dag combines on X86ISD::FANDN nodes
18665 static SDValue PerformFANDNCombine(SDNode *N, SelectionDAG &DAG) {
18666 // FANDN(x, 0.0) -> 0.0
18667 // FANDN(0.0, x) -> x
18668 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
18669 if (C->getValueAPF().isPosZero())
18670 return N->getOperand(1);
18671 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
18672 if (C->getValueAPF().isPosZero())
18673 return N->getOperand(1);
18677 static SDValue PerformBTCombine(SDNode *N,
18679 TargetLowering::DAGCombinerInfo &DCI) {
18680 // BT ignores high bits in the bit index operand.
18681 SDValue Op1 = N->getOperand(1);
18682 if (Op1.hasOneUse()) {
18683 unsigned BitWidth = Op1.getValueSizeInBits();
18684 APInt DemandedMask = APInt::getLowBitsSet(BitWidth, Log2_32(BitWidth));
18685 APInt KnownZero, KnownOne;
18686 TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(),
18687 !DCI.isBeforeLegalizeOps());
18688 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
18689 if (TLO.ShrinkDemandedConstant(Op1, DemandedMask) ||
18690 TLI.SimplifyDemandedBits(Op1, DemandedMask, KnownZero, KnownOne, TLO))
18691 DCI.CommitTargetLoweringOpt(TLO);
18696 static SDValue PerformVZEXT_MOVLCombine(SDNode *N, SelectionDAG &DAG) {
18697 SDValue Op = N->getOperand(0);
18698 if (Op.getOpcode() == ISD::BITCAST)
18699 Op = Op.getOperand(0);
18700 EVT VT = N->getValueType(0), OpVT = Op.getValueType();
18701 if (Op.getOpcode() == X86ISD::VZEXT_LOAD &&
18702 VT.getVectorElementType().getSizeInBits() ==
18703 OpVT.getVectorElementType().getSizeInBits()) {
18704 return DAG.getNode(ISD::BITCAST, SDLoc(N), VT, Op);
18709 static SDValue PerformSIGN_EXTEND_INREGCombine(SDNode *N, SelectionDAG &DAG,
18710 const X86Subtarget *Subtarget) {
18711 EVT VT = N->getValueType(0);
18712 if (!VT.isVector())
18715 SDValue N0 = N->getOperand(0);
18716 SDValue N1 = N->getOperand(1);
18717 EVT ExtraVT = cast<VTSDNode>(N1)->getVT();
18720 // The SIGN_EXTEND_INREG to v4i64 is expensive operation on the
18721 // both SSE and AVX2 since there is no sign-extended shift right
18722 // operation on a vector with 64-bit elements.
18723 //(sext_in_reg (v4i64 anyext (v4i32 x )), ExtraVT) ->
18724 // (v4i64 sext (v4i32 sext_in_reg (v4i32 x , ExtraVT)))
18725 if (VT == MVT::v4i64 && (N0.getOpcode() == ISD::ANY_EXTEND ||
18726 N0.getOpcode() == ISD::SIGN_EXTEND)) {
18727 SDValue N00 = N0.getOperand(0);
18729 // EXTLOAD has a better solution on AVX2,
18730 // it may be replaced with X86ISD::VSEXT node.
18731 if (N00.getOpcode() == ISD::LOAD && Subtarget->hasInt256())
18732 if (!ISD::isNormalLoad(N00.getNode()))
18735 if (N00.getValueType() == MVT::v4i32 && ExtraVT.getSizeInBits() < 128) {
18736 SDValue Tmp = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, MVT::v4i32,
18738 return DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v4i64, Tmp);
18744 static SDValue PerformSExtCombine(SDNode *N, SelectionDAG &DAG,
18745 TargetLowering::DAGCombinerInfo &DCI,
18746 const X86Subtarget *Subtarget) {
18747 if (!DCI.isBeforeLegalizeOps())
18750 if (!Subtarget->hasFp256())
18753 EVT VT = N->getValueType(0);
18754 if (VT.isVector() && VT.getSizeInBits() == 256) {
18755 SDValue R = WidenMaskArithmetic(N, DAG, DCI, Subtarget);
18763 static SDValue PerformFMACombine(SDNode *N, SelectionDAG &DAG,
18764 const X86Subtarget* Subtarget) {
18766 EVT VT = N->getValueType(0);
18768 // Let legalize expand this if it isn't a legal type yet.
18769 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
18772 EVT ScalarVT = VT.getScalarType();
18773 if ((ScalarVT != MVT::f32 && ScalarVT != MVT::f64) ||
18774 (!Subtarget->hasFMA() && !Subtarget->hasFMA4()))
18777 SDValue A = N->getOperand(0);
18778 SDValue B = N->getOperand(1);
18779 SDValue C = N->getOperand(2);
18781 bool NegA = (A.getOpcode() == ISD::FNEG);
18782 bool NegB = (B.getOpcode() == ISD::FNEG);
18783 bool NegC = (C.getOpcode() == ISD::FNEG);
18785 // Negative multiplication when NegA xor NegB
18786 bool NegMul = (NegA != NegB);
18788 A = A.getOperand(0);
18790 B = B.getOperand(0);
18792 C = C.getOperand(0);
18796 Opcode = (!NegC) ? X86ISD::FMADD : X86ISD::FMSUB;
18798 Opcode = (!NegC) ? X86ISD::FNMADD : X86ISD::FNMSUB;
18800 return DAG.getNode(Opcode, dl, VT, A, B, C);
18803 static SDValue PerformZExtCombine(SDNode *N, SelectionDAG &DAG,
18804 TargetLowering::DAGCombinerInfo &DCI,
18805 const X86Subtarget *Subtarget) {
18806 // (i32 zext (and (i8 x86isd::setcc_carry), 1)) ->
18807 // (and (i32 x86isd::setcc_carry), 1)
18808 // This eliminates the zext. This transformation is necessary because
18809 // ISD::SETCC is always legalized to i8.
18811 SDValue N0 = N->getOperand(0);
18812 EVT VT = N->getValueType(0);
18814 if (N0.getOpcode() == ISD::AND &&
18816 N0.getOperand(0).hasOneUse()) {
18817 SDValue N00 = N0.getOperand(0);
18818 if (N00.getOpcode() == X86ISD::SETCC_CARRY) {
18819 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
18820 if (!C || C->getZExtValue() != 1)
18822 return DAG.getNode(ISD::AND, dl, VT,
18823 DAG.getNode(X86ISD::SETCC_CARRY, dl, VT,
18824 N00.getOperand(0), N00.getOperand(1)),
18825 DAG.getConstant(1, VT));
18829 if (VT.is256BitVector()) {
18830 SDValue R = WidenMaskArithmetic(N, DAG, DCI, Subtarget);
18838 // Optimize x == -y --> x+y == 0
18839 // x != -y --> x+y != 0
18840 static SDValue PerformISDSETCCCombine(SDNode *N, SelectionDAG &DAG) {
18841 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(2))->get();
18842 SDValue LHS = N->getOperand(0);
18843 SDValue RHS = N->getOperand(1);
18845 if ((CC == ISD::SETNE || CC == ISD::SETEQ) && LHS.getOpcode() == ISD::SUB)
18846 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(LHS.getOperand(0)))
18847 if (C->getAPIntValue() == 0 && LHS.hasOneUse()) {
18848 SDValue addV = DAG.getNode(ISD::ADD, SDLoc(N),
18849 LHS.getValueType(), RHS, LHS.getOperand(1));
18850 return DAG.getSetCC(SDLoc(N), N->getValueType(0),
18851 addV, DAG.getConstant(0, addV.getValueType()), CC);
18853 if ((CC == ISD::SETNE || CC == ISD::SETEQ) && RHS.getOpcode() == ISD::SUB)
18854 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS.getOperand(0)))
18855 if (C->getAPIntValue() == 0 && RHS.hasOneUse()) {
18856 SDValue addV = DAG.getNode(ISD::ADD, SDLoc(N),
18857 RHS.getValueType(), LHS, RHS.getOperand(1));
18858 return DAG.getSetCC(SDLoc(N), N->getValueType(0),
18859 addV, DAG.getConstant(0, addV.getValueType()), CC);
18864 // Helper function of PerformSETCCCombine. It is to materialize "setb reg"
18865 // as "sbb reg,reg", since it can be extended without zext and produces
18866 // an all-ones bit which is more useful than 0/1 in some cases.
18867 static SDValue MaterializeSETB(SDLoc DL, SDValue EFLAGS, SelectionDAG &DAG) {
18868 return DAG.getNode(ISD::AND, DL, MVT::i8,
18869 DAG.getNode(X86ISD::SETCC_CARRY, DL, MVT::i8,
18870 DAG.getConstant(X86::COND_B, MVT::i8), EFLAGS),
18871 DAG.getConstant(1, MVT::i8));
18874 // Optimize RES = X86ISD::SETCC CONDCODE, EFLAG_INPUT
18875 static SDValue PerformSETCCCombine(SDNode *N, SelectionDAG &DAG,
18876 TargetLowering::DAGCombinerInfo &DCI,
18877 const X86Subtarget *Subtarget) {
18879 X86::CondCode CC = X86::CondCode(N->getConstantOperandVal(0));
18880 SDValue EFLAGS = N->getOperand(1);
18882 if (CC == X86::COND_A) {
18883 // Try to convert COND_A into COND_B in an attempt to facilitate
18884 // materializing "setb reg".
18886 // Do not flip "e > c", where "c" is a constant, because Cmp instruction
18887 // cannot take an immediate as its first operand.
18889 if (EFLAGS.getOpcode() == X86ISD::SUB && EFLAGS.hasOneUse() &&
18890 EFLAGS.getValueType().isInteger() &&
18891 !isa<ConstantSDNode>(EFLAGS.getOperand(1))) {
18892 SDValue NewSub = DAG.getNode(X86ISD::SUB, SDLoc(EFLAGS),
18893 EFLAGS.getNode()->getVTList(),
18894 EFLAGS.getOperand(1), EFLAGS.getOperand(0));
18895 SDValue NewEFLAGS = SDValue(NewSub.getNode(), EFLAGS.getResNo());
18896 return MaterializeSETB(DL, NewEFLAGS, DAG);
18900 // Materialize "setb reg" as "sbb reg,reg", since it can be extended without
18901 // a zext and produces an all-ones bit which is more useful than 0/1 in some
18903 if (CC == X86::COND_B)
18904 return MaterializeSETB(DL, EFLAGS, DAG);
18908 Flags = checkBoolTestSetCCCombine(EFLAGS, CC);
18909 if (Flags.getNode()) {
18910 SDValue Cond = DAG.getConstant(CC, MVT::i8);
18911 return DAG.getNode(X86ISD::SETCC, DL, N->getVTList(), Cond, Flags);
18917 // Optimize branch condition evaluation.
18919 static SDValue PerformBrCondCombine(SDNode *N, SelectionDAG &DAG,
18920 TargetLowering::DAGCombinerInfo &DCI,
18921 const X86Subtarget *Subtarget) {
18923 SDValue Chain = N->getOperand(0);
18924 SDValue Dest = N->getOperand(1);
18925 SDValue EFLAGS = N->getOperand(3);
18926 X86::CondCode CC = X86::CondCode(N->getConstantOperandVal(2));
18930 Flags = checkBoolTestSetCCCombine(EFLAGS, CC);
18931 if (Flags.getNode()) {
18932 SDValue Cond = DAG.getConstant(CC, MVT::i8);
18933 return DAG.getNode(X86ISD::BRCOND, DL, N->getVTList(), Chain, Dest, Cond,
18940 static SDValue PerformSINT_TO_FPCombine(SDNode *N, SelectionDAG &DAG,
18941 const X86TargetLowering *XTLI) {
18942 SDValue Op0 = N->getOperand(0);
18943 EVT InVT = Op0->getValueType(0);
18945 // SINT_TO_FP(v4i8) -> SINT_TO_FP(SEXT(v4i8 to v4i32))
18946 if (InVT == MVT::v8i8 || InVT == MVT::v4i8) {
18948 MVT DstVT = InVT == MVT::v4i8 ? MVT::v4i32 : MVT::v8i32;
18949 SDValue P = DAG.getNode(ISD::SIGN_EXTEND, dl, DstVT, Op0);
18950 return DAG.getNode(ISD::SINT_TO_FP, dl, N->getValueType(0), P);
18953 // Transform (SINT_TO_FP (i64 ...)) into an x87 operation if we have
18954 // a 32-bit target where SSE doesn't support i64->FP operations.
18955 if (Op0.getOpcode() == ISD::LOAD) {
18956 LoadSDNode *Ld = cast<LoadSDNode>(Op0.getNode());
18957 EVT VT = Ld->getValueType(0);
18958 if (!Ld->isVolatile() && !N->getValueType(0).isVector() &&
18959 ISD::isNON_EXTLoad(Op0.getNode()) && Op0.hasOneUse() &&
18960 !XTLI->getSubtarget()->is64Bit() &&
18962 SDValue FILDChain = XTLI->BuildFILD(SDValue(N, 0), Ld->getValueType(0),
18963 Ld->getChain(), Op0, DAG);
18964 DAG.ReplaceAllUsesOfValueWith(Op0.getValue(1), FILDChain.getValue(1));
18971 // Optimize RES, EFLAGS = X86ISD::ADC LHS, RHS, EFLAGS
18972 static SDValue PerformADCCombine(SDNode *N, SelectionDAG &DAG,
18973 X86TargetLowering::DAGCombinerInfo &DCI) {
18974 // If the LHS and RHS of the ADC node are zero, then it can't overflow and
18975 // the result is either zero or one (depending on the input carry bit).
18976 // Strength reduce this down to a "set on carry" aka SETCC_CARRY&1.
18977 if (X86::isZeroNode(N->getOperand(0)) &&
18978 X86::isZeroNode(N->getOperand(1)) &&
18979 // We don't have a good way to replace an EFLAGS use, so only do this when
18981 SDValue(N, 1).use_empty()) {
18983 EVT VT = N->getValueType(0);
18984 SDValue CarryOut = DAG.getConstant(0, N->getValueType(1));
18985 SDValue Res1 = DAG.getNode(ISD::AND, DL, VT,
18986 DAG.getNode(X86ISD::SETCC_CARRY, DL, VT,
18987 DAG.getConstant(X86::COND_B,MVT::i8),
18989 DAG.getConstant(1, VT));
18990 return DCI.CombineTo(N, Res1, CarryOut);
18996 // fold (add Y, (sete X, 0)) -> adc 0, Y
18997 // (add Y, (setne X, 0)) -> sbb -1, Y
18998 // (sub (sete X, 0), Y) -> sbb 0, Y
18999 // (sub (setne X, 0), Y) -> adc -1, Y
19000 static SDValue OptimizeConditionalInDecrement(SDNode *N, SelectionDAG &DAG) {
19003 // Look through ZExts.
19004 SDValue Ext = N->getOperand(N->getOpcode() == ISD::SUB ? 1 : 0);
19005 if (Ext.getOpcode() != ISD::ZERO_EXTEND || !Ext.hasOneUse())
19008 SDValue SetCC = Ext.getOperand(0);
19009 if (SetCC.getOpcode() != X86ISD::SETCC || !SetCC.hasOneUse())
19012 X86::CondCode CC = (X86::CondCode)SetCC.getConstantOperandVal(0);
19013 if (CC != X86::COND_E && CC != X86::COND_NE)
19016 SDValue Cmp = SetCC.getOperand(1);
19017 if (Cmp.getOpcode() != X86ISD::CMP || !Cmp.hasOneUse() ||
19018 !X86::isZeroNode(Cmp.getOperand(1)) ||
19019 !Cmp.getOperand(0).getValueType().isInteger())
19022 SDValue CmpOp0 = Cmp.getOperand(0);
19023 SDValue NewCmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32, CmpOp0,
19024 DAG.getConstant(1, CmpOp0.getValueType()));
19026 SDValue OtherVal = N->getOperand(N->getOpcode() == ISD::SUB ? 0 : 1);
19027 if (CC == X86::COND_NE)
19028 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::ADC : X86ISD::SBB,
19029 DL, OtherVal.getValueType(), OtherVal,
19030 DAG.getConstant(-1ULL, OtherVal.getValueType()), NewCmp);
19031 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::SBB : X86ISD::ADC,
19032 DL, OtherVal.getValueType(), OtherVal,
19033 DAG.getConstant(0, OtherVal.getValueType()), NewCmp);
19036 /// PerformADDCombine - Do target-specific dag combines on integer adds.
19037 static SDValue PerformAddCombine(SDNode *N, SelectionDAG &DAG,
19038 const X86Subtarget *Subtarget) {
19039 EVT VT = N->getValueType(0);
19040 SDValue Op0 = N->getOperand(0);
19041 SDValue Op1 = N->getOperand(1);
19043 // Try to synthesize horizontal adds from adds of shuffles.
19044 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) ||
19045 (Subtarget->hasInt256() && (VT == MVT::v16i16 || VT == MVT::v8i32))) &&
19046 isHorizontalBinOp(Op0, Op1, true))
19047 return DAG.getNode(X86ISD::HADD, SDLoc(N), VT, Op0, Op1);
19049 return OptimizeConditionalInDecrement(N, DAG);
19052 static SDValue PerformSubCombine(SDNode *N, SelectionDAG &DAG,
19053 const X86Subtarget *Subtarget) {
19054 SDValue Op0 = N->getOperand(0);
19055 SDValue Op1 = N->getOperand(1);
19057 // X86 can't encode an immediate LHS of a sub. See if we can push the
19058 // negation into a preceding instruction.
19059 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op0)) {
19060 // If the RHS of the sub is a XOR with one use and a constant, invert the
19061 // immediate. Then add one to the LHS of the sub so we can turn
19062 // X-Y -> X+~Y+1, saving one register.
19063 if (Op1->hasOneUse() && Op1.getOpcode() == ISD::XOR &&
19064 isa<ConstantSDNode>(Op1.getOperand(1))) {
19065 APInt XorC = cast<ConstantSDNode>(Op1.getOperand(1))->getAPIntValue();
19066 EVT VT = Op0.getValueType();
19067 SDValue NewXor = DAG.getNode(ISD::XOR, SDLoc(Op1), VT,
19069 DAG.getConstant(~XorC, VT));
19070 return DAG.getNode(ISD::ADD, SDLoc(N), VT, NewXor,
19071 DAG.getConstant(C->getAPIntValue()+1, VT));
19075 // Try to synthesize horizontal adds from adds of shuffles.
19076 EVT VT = N->getValueType(0);
19077 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) ||
19078 (Subtarget->hasInt256() && (VT == MVT::v16i16 || VT == MVT::v8i32))) &&
19079 isHorizontalBinOp(Op0, Op1, true))
19080 return DAG.getNode(X86ISD::HSUB, SDLoc(N), VT, Op0, Op1);
19082 return OptimizeConditionalInDecrement(N, DAG);
19085 /// performVZEXTCombine - Performs build vector combines
19086 static SDValue performVZEXTCombine(SDNode *N, SelectionDAG &DAG,
19087 TargetLowering::DAGCombinerInfo &DCI,
19088 const X86Subtarget *Subtarget) {
19089 // (vzext (bitcast (vzext (x)) -> (vzext x)
19090 SDValue In = N->getOperand(0);
19091 while (In.getOpcode() == ISD::BITCAST)
19092 In = In.getOperand(0);
19094 if (In.getOpcode() != X86ISD::VZEXT)
19097 return DAG.getNode(X86ISD::VZEXT, SDLoc(N), N->getValueType(0),
19101 SDValue X86TargetLowering::PerformDAGCombine(SDNode *N,
19102 DAGCombinerInfo &DCI) const {
19103 SelectionDAG &DAG = DCI.DAG;
19104 switch (N->getOpcode()) {
19106 case ISD::EXTRACT_VECTOR_ELT:
19107 return PerformEXTRACT_VECTOR_ELTCombine(N, DAG, DCI);
19109 case ISD::SELECT: return PerformSELECTCombine(N, DAG, DCI, Subtarget);
19110 case X86ISD::CMOV: return PerformCMOVCombine(N, DAG, DCI, Subtarget);
19111 case ISD::ADD: return PerformAddCombine(N, DAG, Subtarget);
19112 case ISD::SUB: return PerformSubCombine(N, DAG, Subtarget);
19113 case X86ISD::ADC: return PerformADCCombine(N, DAG, DCI);
19114 case ISD::MUL: return PerformMulCombine(N, DAG, DCI);
19117 case ISD::SRL: return PerformShiftCombine(N, DAG, DCI, Subtarget);
19118 case ISD::AND: return PerformAndCombine(N, DAG, DCI, Subtarget);
19119 case ISD::OR: return PerformOrCombine(N, DAG, DCI, Subtarget);
19120 case ISD::XOR: return PerformXorCombine(N, DAG, DCI, Subtarget);
19121 case ISD::LOAD: return PerformLOADCombine(N, DAG, DCI, Subtarget);
19122 case ISD::STORE: return PerformSTORECombine(N, DAG, Subtarget);
19123 case ISD::SINT_TO_FP: return PerformSINT_TO_FPCombine(N, DAG, this);
19124 case ISD::FADD: return PerformFADDCombine(N, DAG, Subtarget);
19125 case ISD::FSUB: return PerformFSUBCombine(N, DAG, Subtarget);
19127 case X86ISD::FOR: return PerformFORCombine(N, DAG);
19129 case X86ISD::FMAX: return PerformFMinFMaxCombine(N, DAG);
19130 case X86ISD::FAND: return PerformFANDCombine(N, DAG);
19131 case X86ISD::FANDN: return PerformFANDNCombine(N, DAG);
19132 case X86ISD::BT: return PerformBTCombine(N, DAG, DCI);
19133 case X86ISD::VZEXT_MOVL: return PerformVZEXT_MOVLCombine(N, DAG);
19134 case ISD::ANY_EXTEND:
19135 case ISD::ZERO_EXTEND: return PerformZExtCombine(N, DAG, DCI, Subtarget);
19136 case ISD::SIGN_EXTEND: return PerformSExtCombine(N, DAG, DCI, Subtarget);
19137 case ISD::SIGN_EXTEND_INREG: return PerformSIGN_EXTEND_INREGCombine(N, DAG, Subtarget);
19138 case ISD::TRUNCATE: return PerformTruncateCombine(N, DAG,DCI,Subtarget);
19139 case ISD::SETCC: return PerformISDSETCCCombine(N, DAG);
19140 case X86ISD::SETCC: return PerformSETCCCombine(N, DAG, DCI, Subtarget);
19141 case X86ISD::BRCOND: return PerformBrCondCombine(N, DAG, DCI, Subtarget);
19142 case X86ISD::VZEXT: return performVZEXTCombine(N, DAG, DCI, Subtarget);
19143 case X86ISD::SHUFP: // Handle all target specific shuffles
19144 case X86ISD::PALIGNR:
19145 case X86ISD::UNPCKH:
19146 case X86ISD::UNPCKL:
19147 case X86ISD::MOVHLPS:
19148 case X86ISD::MOVLHPS:
19149 case X86ISD::PSHUFD:
19150 case X86ISD::PSHUFHW:
19151 case X86ISD::PSHUFLW:
19152 case X86ISD::MOVSS:
19153 case X86ISD::MOVSD:
19154 case X86ISD::VPERMILP:
19155 case X86ISD::VPERM2X128:
19156 case ISD::VECTOR_SHUFFLE: return PerformShuffleCombine(N, DAG, DCI,Subtarget);
19157 case ISD::FMA: return PerformFMACombine(N, DAG, Subtarget);
19163 /// isTypeDesirableForOp - Return true if the target has native support for
19164 /// the specified value type and it is 'desirable' to use the type for the
19165 /// given node type. e.g. On x86 i16 is legal, but undesirable since i16
19166 /// instruction encodings are longer and some i16 instructions are slow.
19167 bool X86TargetLowering::isTypeDesirableForOp(unsigned Opc, EVT VT) const {
19168 if (!isTypeLegal(VT))
19170 if (VT != MVT::i16)
19177 case ISD::SIGN_EXTEND:
19178 case ISD::ZERO_EXTEND:
19179 case ISD::ANY_EXTEND:
19192 /// IsDesirableToPromoteOp - This method query the target whether it is
19193 /// beneficial for dag combiner to promote the specified node. If true, it
19194 /// should return the desired promotion type by reference.
19195 bool X86TargetLowering::IsDesirableToPromoteOp(SDValue Op, EVT &PVT) const {
19196 EVT VT = Op.getValueType();
19197 if (VT != MVT::i16)
19200 bool Promote = false;
19201 bool Commute = false;
19202 switch (Op.getOpcode()) {
19205 LoadSDNode *LD = cast<LoadSDNode>(Op);
19206 // If the non-extending load has a single use and it's not live out, then it
19207 // might be folded.
19208 if (LD->getExtensionType() == ISD::NON_EXTLOAD /*&&
19209 Op.hasOneUse()*/) {
19210 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
19211 UE = Op.getNode()->use_end(); UI != UE; ++UI) {
19212 // The only case where we'd want to promote LOAD (rather then it being
19213 // promoted as an operand is when it's only use is liveout.
19214 if (UI->getOpcode() != ISD::CopyToReg)
19221 case ISD::SIGN_EXTEND:
19222 case ISD::ZERO_EXTEND:
19223 case ISD::ANY_EXTEND:
19228 SDValue N0 = Op.getOperand(0);
19229 // Look out for (store (shl (load), x)).
19230 if (MayFoldLoad(N0) && MayFoldIntoStore(Op))
19243 SDValue N0 = Op.getOperand(0);
19244 SDValue N1 = Op.getOperand(1);
19245 if (!Commute && MayFoldLoad(N1))
19247 // Avoid disabling potential load folding opportunities.
19248 if (MayFoldLoad(N0) && (!isa<ConstantSDNode>(N1) || MayFoldIntoStore(Op)))
19250 if (MayFoldLoad(N1) && (!isa<ConstantSDNode>(N0) || MayFoldIntoStore(Op)))
19260 //===----------------------------------------------------------------------===//
19261 // X86 Inline Assembly Support
19262 //===----------------------------------------------------------------------===//
19265 // Helper to match a string separated by whitespace.
19266 bool matchAsmImpl(StringRef s, ArrayRef<const StringRef *> args) {
19267 s = s.substr(s.find_first_not_of(" \t")); // Skip leading whitespace.
19269 for (unsigned i = 0, e = args.size(); i != e; ++i) {
19270 StringRef piece(*args[i]);
19271 if (!s.startswith(piece)) // Check if the piece matches.
19274 s = s.substr(piece.size());
19275 StringRef::size_type pos = s.find_first_not_of(" \t");
19276 if (pos == 0) // We matched a prefix.
19284 const VariadicFunction1<bool, StringRef, StringRef, matchAsmImpl> matchAsm={};
19287 static bool clobbersFlagRegisters(const SmallVector<StringRef, 4> &AsmPieces) {
19289 if (AsmPieces.size() == 3 || AsmPieces.size() == 4) {
19290 if (std::count(AsmPieces.begin(), AsmPieces.end(), "~{cc}") &&
19291 std::count(AsmPieces.begin(), AsmPieces.end(), "~{flags}") &&
19292 std::count(AsmPieces.begin(), AsmPieces.end(), "~{fpsr}")) {
19294 if (AsmPieces.size() == 3)
19296 else if (std::count(AsmPieces.begin(), AsmPieces.end(), "~{dirflag}"))
19303 bool X86TargetLowering::ExpandInlineAsm(CallInst *CI) const {
19304 InlineAsm *IA = cast<InlineAsm>(CI->getCalledValue());
19306 std::string AsmStr = IA->getAsmString();
19308 IntegerType *Ty = dyn_cast<IntegerType>(CI->getType());
19309 if (!Ty || Ty->getBitWidth() % 16 != 0)
19312 // TODO: should remove alternatives from the asmstring: "foo {a|b}" -> "foo a"
19313 SmallVector<StringRef, 4> AsmPieces;
19314 SplitString(AsmStr, AsmPieces, ";\n");
19316 switch (AsmPieces.size()) {
19317 default: return false;
19319 // FIXME: this should verify that we are targeting a 486 or better. If not,
19320 // we will turn this bswap into something that will be lowered to logical
19321 // ops instead of emitting the bswap asm. For now, we don't support 486 or
19322 // lower so don't worry about this.
19324 if (matchAsm(AsmPieces[0], "bswap", "$0") ||
19325 matchAsm(AsmPieces[0], "bswapl", "$0") ||
19326 matchAsm(AsmPieces[0], "bswapq", "$0") ||
19327 matchAsm(AsmPieces[0], "bswap", "${0:q}") ||
19328 matchAsm(AsmPieces[0], "bswapl", "${0:q}") ||
19329 matchAsm(AsmPieces[0], "bswapq", "${0:q}")) {
19330 // No need to check constraints, nothing other than the equivalent of
19331 // "=r,0" would be valid here.
19332 return IntrinsicLowering::LowerToByteSwap(CI);
19335 // rorw $$8, ${0:w} --> llvm.bswap.i16
19336 if (CI->getType()->isIntegerTy(16) &&
19337 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 &&
19338 (matchAsm(AsmPieces[0], "rorw", "$$8,", "${0:w}") ||
19339 matchAsm(AsmPieces[0], "rolw", "$$8,", "${0:w}"))) {
19341 const std::string &ConstraintsStr = IA->getConstraintString();
19342 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
19343 array_pod_sort(AsmPieces.begin(), AsmPieces.end());
19344 if (clobbersFlagRegisters(AsmPieces))
19345 return IntrinsicLowering::LowerToByteSwap(CI);
19349 if (CI->getType()->isIntegerTy(32) &&
19350 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 &&
19351 matchAsm(AsmPieces[0], "rorw", "$$8,", "${0:w}") &&
19352 matchAsm(AsmPieces[1], "rorl", "$$16,", "$0") &&
19353 matchAsm(AsmPieces[2], "rorw", "$$8,", "${0:w}")) {
19355 const std::string &ConstraintsStr = IA->getConstraintString();
19356 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
19357 array_pod_sort(AsmPieces.begin(), AsmPieces.end());
19358 if (clobbersFlagRegisters(AsmPieces))
19359 return IntrinsicLowering::LowerToByteSwap(CI);
19362 if (CI->getType()->isIntegerTy(64)) {
19363 InlineAsm::ConstraintInfoVector Constraints = IA->ParseConstraints();
19364 if (Constraints.size() >= 2 &&
19365 Constraints[0].Codes.size() == 1 && Constraints[0].Codes[0] == "A" &&
19366 Constraints[1].Codes.size() == 1 && Constraints[1].Codes[0] == "0") {
19367 // bswap %eax / bswap %edx / xchgl %eax, %edx -> llvm.bswap.i64
19368 if (matchAsm(AsmPieces[0], "bswap", "%eax") &&
19369 matchAsm(AsmPieces[1], "bswap", "%edx") &&
19370 matchAsm(AsmPieces[2], "xchgl", "%eax,", "%edx"))
19371 return IntrinsicLowering::LowerToByteSwap(CI);
19379 /// getConstraintType - Given a constraint letter, return the type of
19380 /// constraint it is for this target.
19381 X86TargetLowering::ConstraintType
19382 X86TargetLowering::getConstraintType(const std::string &Constraint) const {
19383 if (Constraint.size() == 1) {
19384 switch (Constraint[0]) {
19395 return C_RegisterClass;
19419 return TargetLowering::getConstraintType(Constraint);
19422 /// Examine constraint type and operand type and determine a weight value.
19423 /// This object must already have been set up with the operand type
19424 /// and the current alternative constraint selected.
19425 TargetLowering::ConstraintWeight
19426 X86TargetLowering::getSingleConstraintMatchWeight(
19427 AsmOperandInfo &info, const char *constraint) const {
19428 ConstraintWeight weight = CW_Invalid;
19429 Value *CallOperandVal = info.CallOperandVal;
19430 // If we don't have a value, we can't do a match,
19431 // but allow it at the lowest weight.
19432 if (CallOperandVal == NULL)
19434 Type *type = CallOperandVal->getType();
19435 // Look at the constraint type.
19436 switch (*constraint) {
19438 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
19449 if (CallOperandVal->getType()->isIntegerTy())
19450 weight = CW_SpecificReg;
19455 if (type->isFloatingPointTy())
19456 weight = CW_SpecificReg;
19459 if (type->isX86_MMXTy() && Subtarget->hasMMX())
19460 weight = CW_SpecificReg;
19464 if (((type->getPrimitiveSizeInBits() == 128) && Subtarget->hasSSE1()) ||
19465 ((type->getPrimitiveSizeInBits() == 256) && Subtarget->hasFp256()))
19466 weight = CW_Register;
19469 if (ConstantInt *C = dyn_cast<ConstantInt>(info.CallOperandVal)) {
19470 if (C->getZExtValue() <= 31)
19471 weight = CW_Constant;
19475 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
19476 if (C->getZExtValue() <= 63)
19477 weight = CW_Constant;
19481 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
19482 if ((C->getSExtValue() >= -0x80) && (C->getSExtValue() <= 0x7f))
19483 weight = CW_Constant;
19487 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
19488 if ((C->getZExtValue() == 0xff) || (C->getZExtValue() == 0xffff))
19489 weight = CW_Constant;
19493 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
19494 if (C->getZExtValue() <= 3)
19495 weight = CW_Constant;
19499 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
19500 if (C->getZExtValue() <= 0xff)
19501 weight = CW_Constant;
19506 if (dyn_cast<ConstantFP>(CallOperandVal)) {
19507 weight = CW_Constant;
19511 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
19512 if ((C->getSExtValue() >= -0x80000000LL) &&
19513 (C->getSExtValue() <= 0x7fffffffLL))
19514 weight = CW_Constant;
19518 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
19519 if (C->getZExtValue() <= 0xffffffff)
19520 weight = CW_Constant;
19527 /// LowerXConstraint - try to replace an X constraint, which matches anything,
19528 /// with another that has more specific requirements based on the type of the
19529 /// corresponding operand.
19530 const char *X86TargetLowering::
19531 LowerXConstraint(EVT ConstraintVT) const {
19532 // FP X constraints get lowered to SSE1/2 registers if available, otherwise
19533 // 'f' like normal targets.
19534 if (ConstraintVT.isFloatingPoint()) {
19535 if (Subtarget->hasSSE2())
19537 if (Subtarget->hasSSE1())
19541 return TargetLowering::LowerXConstraint(ConstraintVT);
19544 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
19545 /// vector. If it is invalid, don't add anything to Ops.
19546 void X86TargetLowering::LowerAsmOperandForConstraint(SDValue Op,
19547 std::string &Constraint,
19548 std::vector<SDValue>&Ops,
19549 SelectionDAG &DAG) const {
19550 SDValue Result(0, 0);
19552 // Only support length 1 constraints for now.
19553 if (Constraint.length() > 1) return;
19555 char ConstraintLetter = Constraint[0];
19556 switch (ConstraintLetter) {
19559 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
19560 if (C->getZExtValue() <= 31) {
19561 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
19567 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
19568 if (C->getZExtValue() <= 63) {
19569 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
19575 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
19576 if (isInt<8>(C->getSExtValue())) {
19577 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
19583 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
19584 if (C->getZExtValue() <= 255) {
19585 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
19591 // 32-bit signed value
19592 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
19593 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
19594 C->getSExtValue())) {
19595 // Widen to 64 bits here to get it sign extended.
19596 Result = DAG.getTargetConstant(C->getSExtValue(), MVT::i64);
19599 // FIXME gcc accepts some relocatable values here too, but only in certain
19600 // memory models; it's complicated.
19605 // 32-bit unsigned value
19606 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
19607 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
19608 C->getZExtValue())) {
19609 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
19613 // FIXME gcc accepts some relocatable values here too, but only in certain
19614 // memory models; it's complicated.
19618 // Literal immediates are always ok.
19619 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op)) {
19620 // Widen to 64 bits here to get it sign extended.
19621 Result = DAG.getTargetConstant(CST->getSExtValue(), MVT::i64);
19625 // In any sort of PIC mode addresses need to be computed at runtime by
19626 // adding in a register or some sort of table lookup. These can't
19627 // be used as immediates.
19628 if (Subtarget->isPICStyleGOT() || Subtarget->isPICStyleStubPIC())
19631 // If we are in non-pic codegen mode, we allow the address of a global (with
19632 // an optional displacement) to be used with 'i'.
19633 GlobalAddressSDNode *GA = 0;
19634 int64_t Offset = 0;
19636 // Match either (GA), (GA+C), (GA+C1+C2), etc.
19638 if ((GA = dyn_cast<GlobalAddressSDNode>(Op))) {
19639 Offset += GA->getOffset();
19641 } else if (Op.getOpcode() == ISD::ADD) {
19642 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
19643 Offset += C->getZExtValue();
19644 Op = Op.getOperand(0);
19647 } else if (Op.getOpcode() == ISD::SUB) {
19648 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
19649 Offset += -C->getZExtValue();
19650 Op = Op.getOperand(0);
19655 // Otherwise, this isn't something we can handle, reject it.
19659 const GlobalValue *GV = GA->getGlobal();
19660 // If we require an extra load to get this address, as in PIC mode, we
19661 // can't accept it.
19662 if (isGlobalStubReference(Subtarget->ClassifyGlobalReference(GV,
19663 getTargetMachine())))
19666 Result = DAG.getTargetGlobalAddress(GV, SDLoc(Op),
19667 GA->getValueType(0), Offset);
19672 if (Result.getNode()) {
19673 Ops.push_back(Result);
19676 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
19679 std::pair<unsigned, const TargetRegisterClass*>
19680 X86TargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
19682 // First, see if this is a constraint that directly corresponds to an LLVM
19684 if (Constraint.size() == 1) {
19685 // GCC Constraint Letters
19686 switch (Constraint[0]) {
19688 // TODO: Slight differences here in allocation order and leaving
19689 // RIP in the class. Do they matter any more here than they do
19690 // in the normal allocation?
19691 case 'q': // GENERAL_REGS in 64-bit mode, Q_REGS in 32-bit mode.
19692 if (Subtarget->is64Bit()) {
19693 if (VT == MVT::i32 || VT == MVT::f32)
19694 return std::make_pair(0U, &X86::GR32RegClass);
19695 if (VT == MVT::i16)
19696 return std::make_pair(0U, &X86::GR16RegClass);
19697 if (VT == MVT::i8 || VT == MVT::i1)
19698 return std::make_pair(0U, &X86::GR8RegClass);
19699 if (VT == MVT::i64 || VT == MVT::f64)
19700 return std::make_pair(0U, &X86::GR64RegClass);
19703 // 32-bit fallthrough
19704 case 'Q': // Q_REGS
19705 if (VT == MVT::i32 || VT == MVT::f32)
19706 return std::make_pair(0U, &X86::GR32_ABCDRegClass);
19707 if (VT == MVT::i16)
19708 return std::make_pair(0U, &X86::GR16_ABCDRegClass);
19709 if (VT == MVT::i8 || VT == MVT::i1)
19710 return std::make_pair(0U, &X86::GR8_ABCD_LRegClass);
19711 if (VT == MVT::i64)
19712 return std::make_pair(0U, &X86::GR64_ABCDRegClass);
19714 case 'r': // GENERAL_REGS
19715 case 'l': // INDEX_REGS
19716 if (VT == MVT::i8 || VT == MVT::i1)
19717 return std::make_pair(0U, &X86::GR8RegClass);
19718 if (VT == MVT::i16)
19719 return std::make_pair(0U, &X86::GR16RegClass);
19720 if (VT == MVT::i32 || VT == MVT::f32 || !Subtarget->is64Bit())
19721 return std::make_pair(0U, &X86::GR32RegClass);
19722 return std::make_pair(0U, &X86::GR64RegClass);
19723 case 'R': // LEGACY_REGS
19724 if (VT == MVT::i8 || VT == MVT::i1)
19725 return std::make_pair(0U, &X86::GR8_NOREXRegClass);
19726 if (VT == MVT::i16)
19727 return std::make_pair(0U, &X86::GR16_NOREXRegClass);
19728 if (VT == MVT::i32 || !Subtarget->is64Bit())
19729 return std::make_pair(0U, &X86::GR32_NOREXRegClass);
19730 return std::make_pair(0U, &X86::GR64_NOREXRegClass);
19731 case 'f': // FP Stack registers.
19732 // If SSE is enabled for this VT, use f80 to ensure the isel moves the
19733 // value to the correct fpstack register class.
19734 if (VT == MVT::f32 && !isScalarFPTypeInSSEReg(VT))
19735 return std::make_pair(0U, &X86::RFP32RegClass);
19736 if (VT == MVT::f64 && !isScalarFPTypeInSSEReg(VT))
19737 return std::make_pair(0U, &X86::RFP64RegClass);
19738 return std::make_pair(0U, &X86::RFP80RegClass);
19739 case 'y': // MMX_REGS if MMX allowed.
19740 if (!Subtarget->hasMMX()) break;
19741 return std::make_pair(0U, &X86::VR64RegClass);
19742 case 'Y': // SSE_REGS if SSE2 allowed
19743 if (!Subtarget->hasSSE2()) break;
19745 case 'x': // SSE_REGS if SSE1 allowed or AVX_REGS if AVX allowed
19746 if (!Subtarget->hasSSE1()) break;
19748 switch (VT.SimpleTy) {
19750 // Scalar SSE types.
19753 return std::make_pair(0U, &X86::FR32RegClass);
19756 return std::make_pair(0U, &X86::FR64RegClass);
19764 return std::make_pair(0U, &X86::VR128RegClass);
19772 return std::make_pair(0U, &X86::VR256RegClass);
19777 return std::make_pair(0U, &X86::VR512RegClass);
19783 // Use the default implementation in TargetLowering to convert the register
19784 // constraint into a member of a register class.
19785 std::pair<unsigned, const TargetRegisterClass*> Res;
19786 Res = TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
19788 // Not found as a standard register?
19789 if (Res.second == 0) {
19790 // Map st(0) -> st(7) -> ST0
19791 if (Constraint.size() == 7 && Constraint[0] == '{' &&
19792 tolower(Constraint[1]) == 's' &&
19793 tolower(Constraint[2]) == 't' &&
19794 Constraint[3] == '(' &&
19795 (Constraint[4] >= '0' && Constraint[4] <= '7') &&
19796 Constraint[5] == ')' &&
19797 Constraint[6] == '}') {
19799 Res.first = X86::ST0+Constraint[4]-'0';
19800 Res.second = &X86::RFP80RegClass;
19804 // GCC allows "st(0)" to be called just plain "st".
19805 if (StringRef("{st}").equals_lower(Constraint)) {
19806 Res.first = X86::ST0;
19807 Res.second = &X86::RFP80RegClass;
19812 if (StringRef("{flags}").equals_lower(Constraint)) {
19813 Res.first = X86::EFLAGS;
19814 Res.second = &X86::CCRRegClass;
19818 // 'A' means EAX + EDX.
19819 if (Constraint == "A") {
19820 Res.first = X86::EAX;
19821 Res.second = &X86::GR32_ADRegClass;
19827 // Otherwise, check to see if this is a register class of the wrong value
19828 // type. For example, we want to map "{ax},i32" -> {eax}, we don't want it to
19829 // turn into {ax},{dx}.
19830 if (Res.second->hasType(VT))
19831 return Res; // Correct type already, nothing to do.
19833 // All of the single-register GCC register classes map their values onto
19834 // 16-bit register pieces "ax","dx","cx","bx","si","di","bp","sp". If we
19835 // really want an 8-bit or 32-bit register, map to the appropriate register
19836 // class and return the appropriate register.
19837 if (Res.second == &X86::GR16RegClass) {
19838 if (VT == MVT::i8 || VT == MVT::i1) {
19839 unsigned DestReg = 0;
19840 switch (Res.first) {
19842 case X86::AX: DestReg = X86::AL; break;
19843 case X86::DX: DestReg = X86::DL; break;
19844 case X86::CX: DestReg = X86::CL; break;
19845 case X86::BX: DestReg = X86::BL; break;
19848 Res.first = DestReg;
19849 Res.second = &X86::GR8RegClass;
19851 } else if (VT == MVT::i32 || VT == MVT::f32) {
19852 unsigned DestReg = 0;
19853 switch (Res.first) {
19855 case X86::AX: DestReg = X86::EAX; break;
19856 case X86::DX: DestReg = X86::EDX; break;
19857 case X86::CX: DestReg = X86::ECX; break;
19858 case X86::BX: DestReg = X86::EBX; break;
19859 case X86::SI: DestReg = X86::ESI; break;
19860 case X86::DI: DestReg = X86::EDI; break;
19861 case X86::BP: DestReg = X86::EBP; break;
19862 case X86::SP: DestReg = X86::ESP; break;
19865 Res.first = DestReg;
19866 Res.second = &X86::GR32RegClass;
19868 } else if (VT == MVT::i64 || VT == MVT::f64) {
19869 unsigned DestReg = 0;
19870 switch (Res.first) {
19872 case X86::AX: DestReg = X86::RAX; break;
19873 case X86::DX: DestReg = X86::RDX; break;
19874 case X86::CX: DestReg = X86::RCX; break;
19875 case X86::BX: DestReg = X86::RBX; break;
19876 case X86::SI: DestReg = X86::RSI; break;
19877 case X86::DI: DestReg = X86::RDI; break;
19878 case X86::BP: DestReg = X86::RBP; break;
19879 case X86::SP: DestReg = X86::RSP; break;
19882 Res.first = DestReg;
19883 Res.second = &X86::GR64RegClass;
19886 } else if (Res.second == &X86::FR32RegClass ||
19887 Res.second == &X86::FR64RegClass ||
19888 Res.second == &X86::VR128RegClass ||
19889 Res.second == &X86::VR256RegClass ||
19890 Res.second == &X86::FR32XRegClass ||
19891 Res.second == &X86::FR64XRegClass ||
19892 Res.second == &X86::VR128XRegClass ||
19893 Res.second == &X86::VR256XRegClass ||
19894 Res.second == &X86::VR512RegClass) {
19895 // Handle references to XMM physical registers that got mapped into the
19896 // wrong class. This can happen with constraints like {xmm0} where the
19897 // target independent register mapper will just pick the first match it can
19898 // find, ignoring the required type.
19900 if (VT == MVT::f32 || VT == MVT::i32)
19901 Res.second = &X86::FR32RegClass;
19902 else if (VT == MVT::f64 || VT == MVT::i64)
19903 Res.second = &X86::FR64RegClass;
19904 else if (X86::VR128RegClass.hasType(VT))
19905 Res.second = &X86::VR128RegClass;
19906 else if (X86::VR256RegClass.hasType(VT))
19907 Res.second = &X86::VR256RegClass;
19908 else if (X86::VR512RegClass.hasType(VT))
19909 Res.second = &X86::VR512RegClass;