1 //===-- X86ISelLowering.cpp - X86 DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that X86 uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #include "X86ISelLowering.h"
16 #include "Utils/X86ShuffleDecode.h"
17 #include "X86CallingConv.h"
18 #include "X86InstrBuilder.h"
19 #include "X86MachineFunctionInfo.h"
20 #include "X86TargetMachine.h"
21 #include "X86TargetObjectFile.h"
22 #include "llvm/ADT/SmallBitVector.h"
23 #include "llvm/ADT/SmallSet.h"
24 #include "llvm/ADT/Statistic.h"
25 #include "llvm/ADT/StringExtras.h"
26 #include "llvm/ADT/StringSwitch.h"
27 #include "llvm/ADT/VariadicFunction.h"
28 #include "llvm/CodeGen/IntrinsicLowering.h"
29 #include "llvm/CodeGen/MachineFrameInfo.h"
30 #include "llvm/CodeGen/MachineFunction.h"
31 #include "llvm/CodeGen/MachineInstrBuilder.h"
32 #include "llvm/CodeGen/MachineJumpTableInfo.h"
33 #include "llvm/CodeGen/MachineModuleInfo.h"
34 #include "llvm/CodeGen/MachineRegisterInfo.h"
35 #include "llvm/IR/CallSite.h"
36 #include "llvm/IR/CallingConv.h"
37 #include "llvm/IR/Constants.h"
38 #include "llvm/IR/DerivedTypes.h"
39 #include "llvm/IR/Function.h"
40 #include "llvm/IR/GlobalAlias.h"
41 #include "llvm/IR/GlobalVariable.h"
42 #include "llvm/IR/Instructions.h"
43 #include "llvm/IR/Intrinsics.h"
44 #include "llvm/MC/MCAsmInfo.h"
45 #include "llvm/MC/MCContext.h"
46 #include "llvm/MC/MCExpr.h"
47 #include "llvm/MC/MCSymbol.h"
48 #include "llvm/Support/CommandLine.h"
49 #include "llvm/Support/Debug.h"
50 #include "llvm/Support/ErrorHandling.h"
51 #include "llvm/Support/MathExtras.h"
52 #include "llvm/Target/TargetOptions.h"
53 #include "X86IntrinsicsInfo.h"
59 #define DEBUG_TYPE "x86-isel"
61 STATISTIC(NumTailCalls, "Number of tail calls");
63 static cl::opt<bool> ExperimentalVectorWideningLegalization(
64 "x86-experimental-vector-widening-legalization", cl::init(false),
65 cl::desc("Enable an experimental vector type legalization through widening "
66 "rather than promotion."),
69 static cl::opt<bool> ExperimentalVectorShuffleLowering(
70 "x86-experimental-vector-shuffle-lowering", cl::init(false),
71 cl::desc("Enable an experimental vector shuffle lowering code path."),
74 // Forward declarations.
75 static SDValue getMOVL(SelectionDAG &DAG, SDLoc dl, EVT VT, SDValue V1,
78 static SDValue ExtractSubVector(SDValue Vec, unsigned IdxVal,
79 SelectionDAG &DAG, SDLoc dl,
80 unsigned vectorWidth) {
81 assert((vectorWidth == 128 || vectorWidth == 256) &&
82 "Unsupported vector width");
83 EVT VT = Vec.getValueType();
84 EVT ElVT = VT.getVectorElementType();
85 unsigned Factor = VT.getSizeInBits()/vectorWidth;
86 EVT ResultVT = EVT::getVectorVT(*DAG.getContext(), ElVT,
87 VT.getVectorNumElements()/Factor);
89 // Extract from UNDEF is UNDEF.
90 if (Vec.getOpcode() == ISD::UNDEF)
91 return DAG.getUNDEF(ResultVT);
93 // Extract the relevant vectorWidth bits. Generate an EXTRACT_SUBVECTOR
94 unsigned ElemsPerChunk = vectorWidth / ElVT.getSizeInBits();
96 // This is the index of the first element of the vectorWidth-bit chunk
98 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits()) / vectorWidth)
101 // If the input is a buildvector just emit a smaller one.
102 if (Vec.getOpcode() == ISD::BUILD_VECTOR)
103 return DAG.getNode(ISD::BUILD_VECTOR, dl, ResultVT,
104 makeArrayRef(Vec->op_begin()+NormalizedIdxVal,
107 SDValue VecIdx = DAG.getIntPtrConstant(NormalizedIdxVal);
108 SDValue Result = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, ResultVT, Vec,
114 /// Generate a DAG to grab 128-bits from a vector > 128 bits. This
115 /// sets things up to match to an AVX VEXTRACTF128 / VEXTRACTI128
116 /// or AVX-512 VEXTRACTF32x4 / VEXTRACTI32x4
117 /// instructions or a simple subregister reference. Idx is an index in the
118 /// 128 bits we want. It need not be aligned to a 128-bit bounday. That makes
119 /// lowering EXTRACT_VECTOR_ELT operations easier.
120 static SDValue Extract128BitVector(SDValue Vec, unsigned IdxVal,
121 SelectionDAG &DAG, SDLoc dl) {
122 assert((Vec.getValueType().is256BitVector() ||
123 Vec.getValueType().is512BitVector()) && "Unexpected vector size!");
124 return ExtractSubVector(Vec, IdxVal, DAG, dl, 128);
127 /// Generate a DAG to grab 256-bits from a 512-bit vector.
128 static SDValue Extract256BitVector(SDValue Vec, unsigned IdxVal,
129 SelectionDAG &DAG, SDLoc dl) {
130 assert(Vec.getValueType().is512BitVector() && "Unexpected vector size!");
131 return ExtractSubVector(Vec, IdxVal, DAG, dl, 256);
134 static SDValue InsertSubVector(SDValue Result, SDValue Vec,
135 unsigned IdxVal, SelectionDAG &DAG,
136 SDLoc dl, unsigned vectorWidth) {
137 assert((vectorWidth == 128 || vectorWidth == 256) &&
138 "Unsupported vector width");
139 // Inserting UNDEF is Result
140 if (Vec.getOpcode() == ISD::UNDEF)
142 EVT VT = Vec.getValueType();
143 EVT ElVT = VT.getVectorElementType();
144 EVT ResultVT = Result.getValueType();
146 // Insert the relevant vectorWidth bits.
147 unsigned ElemsPerChunk = vectorWidth/ElVT.getSizeInBits();
149 // This is the index of the first element of the vectorWidth-bit chunk
151 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits())/vectorWidth)
154 SDValue VecIdx = DAG.getIntPtrConstant(NormalizedIdxVal);
155 return DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResultVT, Result, Vec,
158 /// Generate a DAG to put 128-bits into a vector > 128 bits. This
159 /// sets things up to match to an AVX VINSERTF128/VINSERTI128 or
160 /// AVX-512 VINSERTF32x4/VINSERTI32x4 instructions or a
161 /// simple superregister reference. Idx is an index in the 128 bits
162 /// we want. It need not be aligned to a 128-bit bounday. That makes
163 /// lowering INSERT_VECTOR_ELT operations easier.
164 static SDValue Insert128BitVector(SDValue Result, SDValue Vec,
165 unsigned IdxVal, SelectionDAG &DAG,
167 assert(Vec.getValueType().is128BitVector() && "Unexpected vector size!");
168 return InsertSubVector(Result, Vec, IdxVal, DAG, dl, 128);
171 static SDValue Insert256BitVector(SDValue Result, SDValue Vec,
172 unsigned IdxVal, SelectionDAG &DAG,
174 assert(Vec.getValueType().is256BitVector() && "Unexpected vector size!");
175 return InsertSubVector(Result, Vec, IdxVal, DAG, dl, 256);
178 /// Concat two 128-bit vectors into a 256 bit vector using VINSERTF128
179 /// instructions. This is used because creating CONCAT_VECTOR nodes of
180 /// BUILD_VECTORS returns a larger BUILD_VECTOR while we're trying to lower
181 /// large BUILD_VECTORS.
182 static SDValue Concat128BitVectors(SDValue V1, SDValue V2, EVT VT,
183 unsigned NumElems, SelectionDAG &DAG,
185 SDValue V = Insert128BitVector(DAG.getUNDEF(VT), V1, 0, DAG, dl);
186 return Insert128BitVector(V, V2, NumElems/2, DAG, dl);
189 static SDValue Concat256BitVectors(SDValue V1, SDValue V2, EVT VT,
190 unsigned NumElems, SelectionDAG &DAG,
192 SDValue V = Insert256BitVector(DAG.getUNDEF(VT), V1, 0, DAG, dl);
193 return Insert256BitVector(V, V2, NumElems/2, DAG, dl);
196 static TargetLoweringObjectFile *createTLOF(const Triple &TT) {
197 if (TT.isOSBinFormatMachO()) {
198 if (TT.getArch() == Triple::x86_64)
199 return new X86_64MachoTargetObjectFile();
200 return new TargetLoweringObjectFileMachO();
204 return new X86LinuxTargetObjectFile();
205 if (TT.isOSBinFormatELF())
206 return new TargetLoweringObjectFileELF();
207 if (TT.isKnownWindowsMSVCEnvironment())
208 return new X86WindowsTargetObjectFile();
209 if (TT.isOSBinFormatCOFF())
210 return new TargetLoweringObjectFileCOFF();
211 llvm_unreachable("unknown subtarget type");
214 // FIXME: This should stop caching the target machine as soon as
215 // we can remove resetOperationActions et al.
216 X86TargetLowering::X86TargetLowering(X86TargetMachine &TM)
217 : TargetLowering(TM, createTLOF(Triple(TM.getTargetTriple()))) {
218 Subtarget = &TM.getSubtarget<X86Subtarget>();
219 X86ScalarSSEf64 = Subtarget->hasSSE2();
220 X86ScalarSSEf32 = Subtarget->hasSSE1();
221 TD = getDataLayout();
223 resetOperationActions();
226 void X86TargetLowering::resetOperationActions() {
227 const TargetMachine &TM = getTargetMachine();
228 static bool FirstTimeThrough = true;
230 // If none of the target options have changed, then we don't need to reset the
231 // operation actions.
232 if (!FirstTimeThrough && TO == TM.Options) return;
234 if (!FirstTimeThrough) {
235 // Reinitialize the actions.
237 FirstTimeThrough = false;
242 // Set up the TargetLowering object.
243 static const MVT IntVTs[] = { MVT::i8, MVT::i16, MVT::i32, MVT::i64 };
245 // X86 is weird, it always uses i8 for shift amounts and setcc results.
246 setBooleanContents(ZeroOrOneBooleanContent);
247 // X86-SSE is even stranger. It uses -1 or 0 for vector masks.
248 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
250 // For 64-bit since we have so many registers use the ILP scheduler, for
251 // 32-bit code use the register pressure specific scheduling.
252 // For Atom, always use ILP scheduling.
253 if (Subtarget->isAtom())
254 setSchedulingPreference(Sched::ILP);
255 else if (Subtarget->is64Bit())
256 setSchedulingPreference(Sched::ILP);
258 setSchedulingPreference(Sched::RegPressure);
259 const X86RegisterInfo *RegInfo =
260 TM.getSubtarget<X86Subtarget>().getRegisterInfo();
261 setStackPointerRegisterToSaveRestore(RegInfo->getStackRegister());
263 // Bypass expensive divides on Atom when compiling with O2
264 if (Subtarget->hasSlowDivide() && TM.getOptLevel() >= CodeGenOpt::Default) {
265 addBypassSlowDiv(32, 8);
266 if (Subtarget->is64Bit())
267 addBypassSlowDiv(64, 16);
270 if (Subtarget->isTargetKnownWindowsMSVC()) {
271 // Setup Windows compiler runtime calls.
272 setLibcallName(RTLIB::SDIV_I64, "_alldiv");
273 setLibcallName(RTLIB::UDIV_I64, "_aulldiv");
274 setLibcallName(RTLIB::SREM_I64, "_allrem");
275 setLibcallName(RTLIB::UREM_I64, "_aullrem");
276 setLibcallName(RTLIB::MUL_I64, "_allmul");
277 setLibcallCallingConv(RTLIB::SDIV_I64, CallingConv::X86_StdCall);
278 setLibcallCallingConv(RTLIB::UDIV_I64, CallingConv::X86_StdCall);
279 setLibcallCallingConv(RTLIB::SREM_I64, CallingConv::X86_StdCall);
280 setLibcallCallingConv(RTLIB::UREM_I64, CallingConv::X86_StdCall);
281 setLibcallCallingConv(RTLIB::MUL_I64, CallingConv::X86_StdCall);
283 // The _ftol2 runtime function has an unusual calling conv, which
284 // is modeled by a special pseudo-instruction.
285 setLibcallName(RTLIB::FPTOUINT_F64_I64, nullptr);
286 setLibcallName(RTLIB::FPTOUINT_F32_I64, nullptr);
287 setLibcallName(RTLIB::FPTOUINT_F64_I32, nullptr);
288 setLibcallName(RTLIB::FPTOUINT_F32_I32, nullptr);
291 if (Subtarget->isTargetDarwin()) {
292 // Darwin should use _setjmp/_longjmp instead of setjmp/longjmp.
293 setUseUnderscoreSetJmp(false);
294 setUseUnderscoreLongJmp(false);
295 } else if (Subtarget->isTargetWindowsGNU()) {
296 // MS runtime is weird: it exports _setjmp, but longjmp!
297 setUseUnderscoreSetJmp(true);
298 setUseUnderscoreLongJmp(false);
300 setUseUnderscoreSetJmp(true);
301 setUseUnderscoreLongJmp(true);
304 // Set up the register classes.
305 addRegisterClass(MVT::i8, &X86::GR8RegClass);
306 addRegisterClass(MVT::i16, &X86::GR16RegClass);
307 addRegisterClass(MVT::i32, &X86::GR32RegClass);
308 if (Subtarget->is64Bit())
309 addRegisterClass(MVT::i64, &X86::GR64RegClass);
311 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
313 // We don't accept any truncstore of integer registers.
314 setTruncStoreAction(MVT::i64, MVT::i32, Expand);
315 setTruncStoreAction(MVT::i64, MVT::i16, Expand);
316 setTruncStoreAction(MVT::i64, MVT::i8 , Expand);
317 setTruncStoreAction(MVT::i32, MVT::i16, Expand);
318 setTruncStoreAction(MVT::i32, MVT::i8 , Expand);
319 setTruncStoreAction(MVT::i16, MVT::i8, Expand);
321 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
323 // SETOEQ and SETUNE require checking two conditions.
324 setCondCodeAction(ISD::SETOEQ, MVT::f32, Expand);
325 setCondCodeAction(ISD::SETOEQ, MVT::f64, Expand);
326 setCondCodeAction(ISD::SETOEQ, MVT::f80, Expand);
327 setCondCodeAction(ISD::SETUNE, MVT::f32, Expand);
328 setCondCodeAction(ISD::SETUNE, MVT::f64, Expand);
329 setCondCodeAction(ISD::SETUNE, MVT::f80, Expand);
331 // Promote all UINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have this
333 setOperationAction(ISD::UINT_TO_FP , MVT::i1 , Promote);
334 setOperationAction(ISD::UINT_TO_FP , MVT::i8 , Promote);
335 setOperationAction(ISD::UINT_TO_FP , MVT::i16 , Promote);
337 if (Subtarget->is64Bit()) {
338 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote);
339 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
340 } else if (!TM.Options.UseSoftFloat) {
341 // We have an algorithm for SSE2->double, and we turn this into a
342 // 64-bit FILD followed by conditional FADD for other targets.
343 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
344 // We have an algorithm for SSE2, and we turn this into a 64-bit
345 // FILD for other targets.
346 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Custom);
349 // Promote i1/i8 SINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have
351 setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote);
352 setOperationAction(ISD::SINT_TO_FP , MVT::i8 , Promote);
354 if (!TM.Options.UseSoftFloat) {
355 // SSE has no i16 to fp conversion, only i32
356 if (X86ScalarSSEf32) {
357 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
358 // f32 and f64 cases are Legal, f80 case is not
359 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
361 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Custom);
362 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
365 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
366 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Promote);
369 // In 32-bit mode these are custom lowered. In 64-bit mode F32 and F64
370 // are Legal, f80 is custom lowered.
371 setOperationAction(ISD::FP_TO_SINT , MVT::i64 , Custom);
372 setOperationAction(ISD::SINT_TO_FP , MVT::i64 , Custom);
374 // Promote i1/i8 FP_TO_SINT to larger FP_TO_SINTS's, as X86 doesn't have
376 setOperationAction(ISD::FP_TO_SINT , MVT::i1 , Promote);
377 setOperationAction(ISD::FP_TO_SINT , MVT::i8 , Promote);
379 if (X86ScalarSSEf32) {
380 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Promote);
381 // f32 and f64 cases are Legal, f80 case is not
382 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
384 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Custom);
385 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
388 // Handle FP_TO_UINT by promoting the destination to a larger signed
390 setOperationAction(ISD::FP_TO_UINT , MVT::i1 , Promote);
391 setOperationAction(ISD::FP_TO_UINT , MVT::i8 , Promote);
392 setOperationAction(ISD::FP_TO_UINT , MVT::i16 , Promote);
394 if (Subtarget->is64Bit()) {
395 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Expand);
396 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote);
397 } else if (!TM.Options.UseSoftFloat) {
398 // Since AVX is a superset of SSE3, only check for SSE here.
399 if (Subtarget->hasSSE1() && !Subtarget->hasSSE3())
400 // Expand FP_TO_UINT into a select.
401 // FIXME: We would like to use a Custom expander here eventually to do
402 // the optimal thing for SSE vs. the default expansion in the legalizer.
403 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Expand);
405 // With SSE3 we can use fisttpll to convert to a signed i64; without
406 // SSE, we're stuck with a fistpll.
407 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Custom);
410 if (isTargetFTOL()) {
411 // Use the _ftol2 runtime function, which has a pseudo-instruction
412 // to handle its weird calling convention.
413 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Custom);
416 // TODO: when we have SSE, these could be more efficient, by using movd/movq.
417 if (!X86ScalarSSEf64) {
418 setOperationAction(ISD::BITCAST , MVT::f32 , Expand);
419 setOperationAction(ISD::BITCAST , MVT::i32 , Expand);
420 if (Subtarget->is64Bit()) {
421 setOperationAction(ISD::BITCAST , MVT::f64 , Expand);
422 // Without SSE, i64->f64 goes through memory.
423 setOperationAction(ISD::BITCAST , MVT::i64 , Expand);
427 // Scalar integer divide and remainder are lowered to use operations that
428 // produce two results, to match the available instructions. This exposes
429 // the two-result form to trivial CSE, which is able to combine x/y and x%y
430 // into a single instruction.
432 // Scalar integer multiply-high is also lowered to use two-result
433 // operations, to match the available instructions. However, plain multiply
434 // (low) operations are left as Legal, as there are single-result
435 // instructions for this in x86. Using the two-result multiply instructions
436 // when both high and low results are needed must be arranged by dagcombine.
437 for (unsigned i = 0; i != array_lengthof(IntVTs); ++i) {
439 setOperationAction(ISD::MULHS, VT, Expand);
440 setOperationAction(ISD::MULHU, VT, Expand);
441 setOperationAction(ISD::SDIV, VT, Expand);
442 setOperationAction(ISD::UDIV, VT, Expand);
443 setOperationAction(ISD::SREM, VT, Expand);
444 setOperationAction(ISD::UREM, VT, Expand);
446 // Add/Sub overflow ops with MVT::Glues are lowered to EFLAGS dependences.
447 setOperationAction(ISD::ADDC, VT, Custom);
448 setOperationAction(ISD::ADDE, VT, Custom);
449 setOperationAction(ISD::SUBC, VT, Custom);
450 setOperationAction(ISD::SUBE, VT, Custom);
453 setOperationAction(ISD::BR_JT , MVT::Other, Expand);
454 setOperationAction(ISD::BRCOND , MVT::Other, Custom);
455 setOperationAction(ISD::BR_CC , MVT::f32, Expand);
456 setOperationAction(ISD::BR_CC , MVT::f64, Expand);
457 setOperationAction(ISD::BR_CC , MVT::f80, Expand);
458 setOperationAction(ISD::BR_CC , MVT::i8, Expand);
459 setOperationAction(ISD::BR_CC , MVT::i16, Expand);
460 setOperationAction(ISD::BR_CC , MVT::i32, Expand);
461 setOperationAction(ISD::BR_CC , MVT::i64, Expand);
462 setOperationAction(ISD::SELECT_CC , MVT::f32, Expand);
463 setOperationAction(ISD::SELECT_CC , MVT::f64, Expand);
464 setOperationAction(ISD::SELECT_CC , MVT::f80, Expand);
465 setOperationAction(ISD::SELECT_CC , MVT::i8, Expand);
466 setOperationAction(ISD::SELECT_CC , MVT::i16, Expand);
467 setOperationAction(ISD::SELECT_CC , MVT::i32, Expand);
468 setOperationAction(ISD::SELECT_CC , MVT::i64, Expand);
469 if (Subtarget->is64Bit())
470 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal);
471 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Legal);
472 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Legal);
473 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
474 setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand);
475 setOperationAction(ISD::FREM , MVT::f32 , Expand);
476 setOperationAction(ISD::FREM , MVT::f64 , Expand);
477 setOperationAction(ISD::FREM , MVT::f80 , Expand);
478 setOperationAction(ISD::FLT_ROUNDS_ , MVT::i32 , Custom);
480 // Promote the i8 variants and force them on up to i32 which has a shorter
482 setOperationAction(ISD::CTTZ , MVT::i8 , Promote);
483 AddPromotedToType (ISD::CTTZ , MVT::i8 , MVT::i32);
484 setOperationAction(ISD::CTTZ_ZERO_UNDEF , MVT::i8 , Promote);
485 AddPromotedToType (ISD::CTTZ_ZERO_UNDEF , MVT::i8 , MVT::i32);
486 if (Subtarget->hasBMI()) {
487 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i16 , Expand);
488 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32 , Expand);
489 if (Subtarget->is64Bit())
490 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand);
492 setOperationAction(ISD::CTTZ , MVT::i16 , Custom);
493 setOperationAction(ISD::CTTZ , MVT::i32 , Custom);
494 if (Subtarget->is64Bit())
495 setOperationAction(ISD::CTTZ , MVT::i64 , Custom);
498 if (Subtarget->hasLZCNT()) {
499 // When promoting the i8 variants, force them to i32 for a shorter
501 setOperationAction(ISD::CTLZ , MVT::i8 , Promote);
502 AddPromotedToType (ISD::CTLZ , MVT::i8 , MVT::i32);
503 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Promote);
504 AddPromotedToType (ISD::CTLZ_ZERO_UNDEF, MVT::i8 , MVT::i32);
505 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Expand);
506 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Expand);
507 if (Subtarget->is64Bit())
508 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Expand);
510 setOperationAction(ISD::CTLZ , MVT::i8 , Custom);
511 setOperationAction(ISD::CTLZ , MVT::i16 , Custom);
512 setOperationAction(ISD::CTLZ , MVT::i32 , Custom);
513 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Custom);
514 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Custom);
515 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Custom);
516 if (Subtarget->is64Bit()) {
517 setOperationAction(ISD::CTLZ , MVT::i64 , Custom);
518 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Custom);
522 // Special handling for half-precision floating point conversions.
523 // If we don't have F16C support, then lower half float conversions
524 // into library calls.
525 if (TM.Options.UseSoftFloat || !Subtarget->hasF16C()) {
526 setOperationAction(ISD::FP16_TO_FP, MVT::f32, Expand);
527 setOperationAction(ISD::FP_TO_FP16, MVT::f32, Expand);
530 // There's never any support for operations beyond MVT::f32.
531 setOperationAction(ISD::FP16_TO_FP, MVT::f64, Expand);
532 setOperationAction(ISD::FP16_TO_FP, MVT::f80, Expand);
533 setOperationAction(ISD::FP_TO_FP16, MVT::f64, Expand);
534 setOperationAction(ISD::FP_TO_FP16, MVT::f80, Expand);
536 setLoadExtAction(ISD::EXTLOAD, MVT::f16, Expand);
537 setTruncStoreAction(MVT::f32, MVT::f16, Expand);
538 setTruncStoreAction(MVT::f64, MVT::f16, Expand);
539 setTruncStoreAction(MVT::f80, MVT::f16, Expand);
541 if (Subtarget->hasPOPCNT()) {
542 setOperationAction(ISD::CTPOP , MVT::i8 , Promote);
544 setOperationAction(ISD::CTPOP , MVT::i8 , Expand);
545 setOperationAction(ISD::CTPOP , MVT::i16 , Expand);
546 setOperationAction(ISD::CTPOP , MVT::i32 , Expand);
547 if (Subtarget->is64Bit())
548 setOperationAction(ISD::CTPOP , MVT::i64 , Expand);
551 setOperationAction(ISD::READCYCLECOUNTER , MVT::i64 , Custom);
553 if (!Subtarget->hasMOVBE())
554 setOperationAction(ISD::BSWAP , MVT::i16 , Expand);
556 // These should be promoted to a larger select which is supported.
557 setOperationAction(ISD::SELECT , MVT::i1 , Promote);
558 // X86 wants to expand cmov itself.
559 setOperationAction(ISD::SELECT , MVT::i8 , Custom);
560 setOperationAction(ISD::SELECT , MVT::i16 , Custom);
561 setOperationAction(ISD::SELECT , MVT::i32 , Custom);
562 setOperationAction(ISD::SELECT , MVT::f32 , Custom);
563 setOperationAction(ISD::SELECT , MVT::f64 , Custom);
564 setOperationAction(ISD::SELECT , MVT::f80 , Custom);
565 setOperationAction(ISD::SETCC , MVT::i8 , Custom);
566 setOperationAction(ISD::SETCC , MVT::i16 , Custom);
567 setOperationAction(ISD::SETCC , MVT::i32 , Custom);
568 setOperationAction(ISD::SETCC , MVT::f32 , Custom);
569 setOperationAction(ISD::SETCC , MVT::f64 , Custom);
570 setOperationAction(ISD::SETCC , MVT::f80 , Custom);
571 if (Subtarget->is64Bit()) {
572 setOperationAction(ISD::SELECT , MVT::i64 , Custom);
573 setOperationAction(ISD::SETCC , MVT::i64 , Custom);
575 setOperationAction(ISD::EH_RETURN , MVT::Other, Custom);
576 // NOTE: EH_SJLJ_SETJMP/_LONGJMP supported here is NOT intended to support
577 // SjLj exception handling but a light-weight setjmp/longjmp replacement to
578 // support continuation, user-level threading, and etc.. As a result, no
579 // other SjLj exception interfaces are implemented and please don't build
580 // your own exception handling based on them.
581 // LLVM/Clang supports zero-cost DWARF exception handling.
582 setOperationAction(ISD::EH_SJLJ_SETJMP, MVT::i32, Custom);
583 setOperationAction(ISD::EH_SJLJ_LONGJMP, MVT::Other, Custom);
586 setOperationAction(ISD::ConstantPool , MVT::i32 , Custom);
587 setOperationAction(ISD::JumpTable , MVT::i32 , Custom);
588 setOperationAction(ISD::GlobalAddress , MVT::i32 , Custom);
589 setOperationAction(ISD::GlobalTLSAddress, MVT::i32 , Custom);
590 if (Subtarget->is64Bit())
591 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
592 setOperationAction(ISD::ExternalSymbol , MVT::i32 , Custom);
593 setOperationAction(ISD::BlockAddress , MVT::i32 , Custom);
594 if (Subtarget->is64Bit()) {
595 setOperationAction(ISD::ConstantPool , MVT::i64 , Custom);
596 setOperationAction(ISD::JumpTable , MVT::i64 , Custom);
597 setOperationAction(ISD::GlobalAddress , MVT::i64 , Custom);
598 setOperationAction(ISD::ExternalSymbol, MVT::i64 , Custom);
599 setOperationAction(ISD::BlockAddress , MVT::i64 , Custom);
601 // 64-bit addm sub, shl, sra, srl (iff 32-bit x86)
602 setOperationAction(ISD::SHL_PARTS , MVT::i32 , Custom);
603 setOperationAction(ISD::SRA_PARTS , MVT::i32 , Custom);
604 setOperationAction(ISD::SRL_PARTS , MVT::i32 , Custom);
605 if (Subtarget->is64Bit()) {
606 setOperationAction(ISD::SHL_PARTS , MVT::i64 , Custom);
607 setOperationAction(ISD::SRA_PARTS , MVT::i64 , Custom);
608 setOperationAction(ISD::SRL_PARTS , MVT::i64 , Custom);
611 if (Subtarget->hasSSE1())
612 setOperationAction(ISD::PREFETCH , MVT::Other, Legal);
614 setOperationAction(ISD::ATOMIC_FENCE , MVT::Other, Custom);
616 // Expand certain atomics
617 for (unsigned i = 0; i != array_lengthof(IntVTs); ++i) {
619 setOperationAction(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, VT, Custom);
620 setOperationAction(ISD::ATOMIC_LOAD_SUB, VT, Custom);
621 setOperationAction(ISD::ATOMIC_STORE, VT, Custom);
624 if (Subtarget->hasCmpxchg16b()) {
625 setOperationAction(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, MVT::i128, Custom);
628 // FIXME - use subtarget debug flags
629 if (!Subtarget->isTargetDarwin() && !Subtarget->isTargetELF() &&
630 !Subtarget->isTargetCygMing() && !Subtarget->isTargetWin64()) {
631 setOperationAction(ISD::EH_LABEL, MVT::Other, Expand);
634 if (Subtarget->is64Bit()) {
635 setExceptionPointerRegister(X86::RAX);
636 setExceptionSelectorRegister(X86::RDX);
638 setExceptionPointerRegister(X86::EAX);
639 setExceptionSelectorRegister(X86::EDX);
641 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i32, Custom);
642 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i64, Custom);
644 setOperationAction(ISD::INIT_TRAMPOLINE, MVT::Other, Custom);
645 setOperationAction(ISD::ADJUST_TRAMPOLINE, MVT::Other, Custom);
647 setOperationAction(ISD::TRAP, MVT::Other, Legal);
648 setOperationAction(ISD::DEBUGTRAP, MVT::Other, Legal);
650 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
651 setOperationAction(ISD::VASTART , MVT::Other, Custom);
652 setOperationAction(ISD::VAEND , MVT::Other, Expand);
653 if (Subtarget->is64Bit() && !Subtarget->isTargetWin64()) {
654 // TargetInfo::X86_64ABIBuiltinVaList
655 setOperationAction(ISD::VAARG , MVT::Other, Custom);
656 setOperationAction(ISD::VACOPY , MVT::Other, Custom);
658 // TargetInfo::CharPtrBuiltinVaList
659 setOperationAction(ISD::VAARG , MVT::Other, Expand);
660 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
663 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
664 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
666 setOperationAction(ISD::DYNAMIC_STACKALLOC, getPointerTy(), Custom);
668 if (!TM.Options.UseSoftFloat && X86ScalarSSEf64) {
669 // f32 and f64 use SSE.
670 // Set up the FP register classes.
671 addRegisterClass(MVT::f32, &X86::FR32RegClass);
672 addRegisterClass(MVT::f64, &X86::FR64RegClass);
674 // Use ANDPD to simulate FABS.
675 setOperationAction(ISD::FABS , MVT::f64, Custom);
676 setOperationAction(ISD::FABS , MVT::f32, Custom);
678 // Use XORP to simulate FNEG.
679 setOperationAction(ISD::FNEG , MVT::f64, Custom);
680 setOperationAction(ISD::FNEG , MVT::f32, Custom);
682 // Use ANDPD and ORPD to simulate FCOPYSIGN.
683 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
684 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
686 // Lower this to FGETSIGNx86 plus an AND.
687 setOperationAction(ISD::FGETSIGN, MVT::i64, Custom);
688 setOperationAction(ISD::FGETSIGN, MVT::i32, Custom);
690 // We don't support sin/cos/fmod
691 setOperationAction(ISD::FSIN , MVT::f64, Expand);
692 setOperationAction(ISD::FCOS , MVT::f64, Expand);
693 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
694 setOperationAction(ISD::FSIN , MVT::f32, Expand);
695 setOperationAction(ISD::FCOS , MVT::f32, Expand);
696 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
698 // Expand FP immediates into loads from the stack, except for the special
700 addLegalFPImmediate(APFloat(+0.0)); // xorpd
701 addLegalFPImmediate(APFloat(+0.0f)); // xorps
702 } else if (!TM.Options.UseSoftFloat && X86ScalarSSEf32) {
703 // Use SSE for f32, x87 for f64.
704 // Set up the FP register classes.
705 addRegisterClass(MVT::f32, &X86::FR32RegClass);
706 addRegisterClass(MVT::f64, &X86::RFP64RegClass);
708 // Use ANDPS to simulate FABS.
709 setOperationAction(ISD::FABS , MVT::f32, Custom);
711 // Use XORP to simulate FNEG.
712 setOperationAction(ISD::FNEG , MVT::f32, Custom);
714 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
716 // Use ANDPS and ORPS to simulate FCOPYSIGN.
717 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
718 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
720 // We don't support sin/cos/fmod
721 setOperationAction(ISD::FSIN , MVT::f32, Expand);
722 setOperationAction(ISD::FCOS , MVT::f32, Expand);
723 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
725 // Special cases we handle for FP constants.
726 addLegalFPImmediate(APFloat(+0.0f)); // xorps
727 addLegalFPImmediate(APFloat(+0.0)); // FLD0
728 addLegalFPImmediate(APFloat(+1.0)); // FLD1
729 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
730 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
732 if (!TM.Options.UnsafeFPMath) {
733 setOperationAction(ISD::FSIN , MVT::f64, Expand);
734 setOperationAction(ISD::FCOS , MVT::f64, Expand);
735 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
737 } else if (!TM.Options.UseSoftFloat) {
738 // f32 and f64 in x87.
739 // Set up the FP register classes.
740 addRegisterClass(MVT::f64, &X86::RFP64RegClass);
741 addRegisterClass(MVT::f32, &X86::RFP32RegClass);
743 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
744 setOperationAction(ISD::UNDEF, MVT::f32, Expand);
745 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
746 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
748 if (!TM.Options.UnsafeFPMath) {
749 setOperationAction(ISD::FSIN , MVT::f64, Expand);
750 setOperationAction(ISD::FSIN , MVT::f32, Expand);
751 setOperationAction(ISD::FCOS , MVT::f64, Expand);
752 setOperationAction(ISD::FCOS , MVT::f32, Expand);
753 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
754 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
756 addLegalFPImmediate(APFloat(+0.0)); // FLD0
757 addLegalFPImmediate(APFloat(+1.0)); // FLD1
758 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
759 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
760 addLegalFPImmediate(APFloat(+0.0f)); // FLD0
761 addLegalFPImmediate(APFloat(+1.0f)); // FLD1
762 addLegalFPImmediate(APFloat(-0.0f)); // FLD0/FCHS
763 addLegalFPImmediate(APFloat(-1.0f)); // FLD1/FCHS
766 // We don't support FMA.
767 setOperationAction(ISD::FMA, MVT::f64, Expand);
768 setOperationAction(ISD::FMA, MVT::f32, Expand);
770 // Long double always uses X87.
771 if (!TM.Options.UseSoftFloat) {
772 addRegisterClass(MVT::f80, &X86::RFP80RegClass);
773 setOperationAction(ISD::UNDEF, MVT::f80, Expand);
774 setOperationAction(ISD::FCOPYSIGN, MVT::f80, Expand);
776 APFloat TmpFlt = APFloat::getZero(APFloat::x87DoubleExtended);
777 addLegalFPImmediate(TmpFlt); // FLD0
779 addLegalFPImmediate(TmpFlt); // FLD0/FCHS
782 APFloat TmpFlt2(+1.0);
783 TmpFlt2.convert(APFloat::x87DoubleExtended, APFloat::rmNearestTiesToEven,
785 addLegalFPImmediate(TmpFlt2); // FLD1
786 TmpFlt2.changeSign();
787 addLegalFPImmediate(TmpFlt2); // FLD1/FCHS
790 if (!TM.Options.UnsafeFPMath) {
791 setOperationAction(ISD::FSIN , MVT::f80, Expand);
792 setOperationAction(ISD::FCOS , MVT::f80, Expand);
793 setOperationAction(ISD::FSINCOS, MVT::f80, Expand);
796 setOperationAction(ISD::FFLOOR, MVT::f80, Expand);
797 setOperationAction(ISD::FCEIL, MVT::f80, Expand);
798 setOperationAction(ISD::FTRUNC, MVT::f80, Expand);
799 setOperationAction(ISD::FRINT, MVT::f80, Expand);
800 setOperationAction(ISD::FNEARBYINT, MVT::f80, Expand);
801 setOperationAction(ISD::FMA, MVT::f80, Expand);
804 // Always use a library call for pow.
805 setOperationAction(ISD::FPOW , MVT::f32 , Expand);
806 setOperationAction(ISD::FPOW , MVT::f64 , Expand);
807 setOperationAction(ISD::FPOW , MVT::f80 , Expand);
809 setOperationAction(ISD::FLOG, MVT::f80, Expand);
810 setOperationAction(ISD::FLOG2, MVT::f80, Expand);
811 setOperationAction(ISD::FLOG10, MVT::f80, Expand);
812 setOperationAction(ISD::FEXP, MVT::f80, Expand);
813 setOperationAction(ISD::FEXP2, MVT::f80, Expand);
815 // First set operation action for all vector types to either promote
816 // (for widening) or expand (for scalarization). Then we will selectively
817 // turn on ones that can be effectively codegen'd.
818 for (int i = MVT::FIRST_VECTOR_VALUETYPE;
819 i <= MVT::LAST_VECTOR_VALUETYPE; ++i) {
820 MVT VT = (MVT::SimpleValueType)i;
821 setOperationAction(ISD::ADD , VT, Expand);
822 setOperationAction(ISD::SUB , VT, Expand);
823 setOperationAction(ISD::FADD, VT, Expand);
824 setOperationAction(ISD::FNEG, VT, Expand);
825 setOperationAction(ISD::FSUB, VT, Expand);
826 setOperationAction(ISD::MUL , VT, Expand);
827 setOperationAction(ISD::FMUL, VT, Expand);
828 setOperationAction(ISD::SDIV, VT, Expand);
829 setOperationAction(ISD::UDIV, VT, Expand);
830 setOperationAction(ISD::FDIV, VT, Expand);
831 setOperationAction(ISD::SREM, VT, Expand);
832 setOperationAction(ISD::UREM, VT, Expand);
833 setOperationAction(ISD::LOAD, VT, Expand);
834 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Expand);
835 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT,Expand);
836 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Expand);
837 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT,Expand);
838 setOperationAction(ISD::INSERT_SUBVECTOR, VT,Expand);
839 setOperationAction(ISD::FABS, VT, Expand);
840 setOperationAction(ISD::FSIN, VT, Expand);
841 setOperationAction(ISD::FSINCOS, VT, Expand);
842 setOperationAction(ISD::FCOS, VT, Expand);
843 setOperationAction(ISD::FSINCOS, VT, Expand);
844 setOperationAction(ISD::FREM, VT, Expand);
845 setOperationAction(ISD::FMA, VT, Expand);
846 setOperationAction(ISD::FPOWI, VT, Expand);
847 setOperationAction(ISD::FSQRT, VT, Expand);
848 setOperationAction(ISD::FCOPYSIGN, VT, Expand);
849 setOperationAction(ISD::FFLOOR, VT, Expand);
850 setOperationAction(ISD::FCEIL, VT, Expand);
851 setOperationAction(ISD::FTRUNC, VT, Expand);
852 setOperationAction(ISD::FRINT, VT, Expand);
853 setOperationAction(ISD::FNEARBYINT, VT, Expand);
854 setOperationAction(ISD::SMUL_LOHI, VT, Expand);
855 setOperationAction(ISD::MULHS, VT, Expand);
856 setOperationAction(ISD::UMUL_LOHI, VT, Expand);
857 setOperationAction(ISD::MULHU, VT, Expand);
858 setOperationAction(ISD::SDIVREM, VT, Expand);
859 setOperationAction(ISD::UDIVREM, VT, Expand);
860 setOperationAction(ISD::FPOW, VT, Expand);
861 setOperationAction(ISD::CTPOP, VT, Expand);
862 setOperationAction(ISD::CTTZ, VT, Expand);
863 setOperationAction(ISD::CTTZ_ZERO_UNDEF, VT, Expand);
864 setOperationAction(ISD::CTLZ, VT, Expand);
865 setOperationAction(ISD::CTLZ_ZERO_UNDEF, VT, Expand);
866 setOperationAction(ISD::SHL, VT, Expand);
867 setOperationAction(ISD::SRA, VT, Expand);
868 setOperationAction(ISD::SRL, VT, Expand);
869 setOperationAction(ISD::ROTL, VT, Expand);
870 setOperationAction(ISD::ROTR, VT, Expand);
871 setOperationAction(ISD::BSWAP, VT, Expand);
872 setOperationAction(ISD::SETCC, VT, Expand);
873 setOperationAction(ISD::FLOG, VT, Expand);
874 setOperationAction(ISD::FLOG2, VT, Expand);
875 setOperationAction(ISD::FLOG10, VT, Expand);
876 setOperationAction(ISD::FEXP, VT, Expand);
877 setOperationAction(ISD::FEXP2, VT, Expand);
878 setOperationAction(ISD::FP_TO_UINT, VT, Expand);
879 setOperationAction(ISD::FP_TO_SINT, VT, Expand);
880 setOperationAction(ISD::UINT_TO_FP, VT, Expand);
881 setOperationAction(ISD::SINT_TO_FP, VT, Expand);
882 setOperationAction(ISD::SIGN_EXTEND_INREG, VT,Expand);
883 setOperationAction(ISD::TRUNCATE, VT, Expand);
884 setOperationAction(ISD::SIGN_EXTEND, VT, Expand);
885 setOperationAction(ISD::ZERO_EXTEND, VT, Expand);
886 setOperationAction(ISD::ANY_EXTEND, VT, Expand);
887 setOperationAction(ISD::VSELECT, VT, Expand);
888 setOperationAction(ISD::SELECT_CC, VT, Expand);
889 for (int InnerVT = MVT::FIRST_VECTOR_VALUETYPE;
890 InnerVT <= MVT::LAST_VECTOR_VALUETYPE; ++InnerVT)
891 setTruncStoreAction(VT,
892 (MVT::SimpleValueType)InnerVT, Expand);
893 setLoadExtAction(ISD::SEXTLOAD, VT, Expand);
894 setLoadExtAction(ISD::ZEXTLOAD, VT, Expand);
896 // N.b. ISD::EXTLOAD legality is basically ignored except for i1-like types,
897 // we have to deal with them whether we ask for Expansion or not. Setting
898 // Expand causes its own optimisation problems though, so leave them legal.
899 if (VT.getVectorElementType() == MVT::i1)
900 setLoadExtAction(ISD::EXTLOAD, VT, Expand);
903 // FIXME: In order to prevent SSE instructions being expanded to MMX ones
904 // with -msoft-float, disable use of MMX as well.
905 if (!TM.Options.UseSoftFloat && Subtarget->hasMMX()) {
906 addRegisterClass(MVT::x86mmx, &X86::VR64RegClass);
907 // No operations on x86mmx supported, everything uses intrinsics.
910 // MMX-sized vectors (other than x86mmx) are expected to be expanded
911 // into smaller operations.
912 setOperationAction(ISD::MULHS, MVT::v8i8, Expand);
913 setOperationAction(ISD::MULHS, MVT::v4i16, Expand);
914 setOperationAction(ISD::MULHS, MVT::v2i32, Expand);
915 setOperationAction(ISD::MULHS, MVT::v1i64, Expand);
916 setOperationAction(ISD::AND, MVT::v8i8, Expand);
917 setOperationAction(ISD::AND, MVT::v4i16, Expand);
918 setOperationAction(ISD::AND, MVT::v2i32, Expand);
919 setOperationAction(ISD::AND, MVT::v1i64, Expand);
920 setOperationAction(ISD::OR, MVT::v8i8, Expand);
921 setOperationAction(ISD::OR, MVT::v4i16, Expand);
922 setOperationAction(ISD::OR, MVT::v2i32, Expand);
923 setOperationAction(ISD::OR, MVT::v1i64, Expand);
924 setOperationAction(ISD::XOR, MVT::v8i8, Expand);
925 setOperationAction(ISD::XOR, MVT::v4i16, Expand);
926 setOperationAction(ISD::XOR, MVT::v2i32, Expand);
927 setOperationAction(ISD::XOR, MVT::v1i64, Expand);
928 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i8, Expand);
929 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i16, Expand);
930 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2i32, Expand);
931 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v1i64, Expand);
932 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v1i64, Expand);
933 setOperationAction(ISD::SELECT, MVT::v8i8, Expand);
934 setOperationAction(ISD::SELECT, MVT::v4i16, Expand);
935 setOperationAction(ISD::SELECT, MVT::v2i32, Expand);
936 setOperationAction(ISD::SELECT, MVT::v1i64, Expand);
937 setOperationAction(ISD::BITCAST, MVT::v8i8, Expand);
938 setOperationAction(ISD::BITCAST, MVT::v4i16, Expand);
939 setOperationAction(ISD::BITCAST, MVT::v2i32, Expand);
940 setOperationAction(ISD::BITCAST, MVT::v1i64, Expand);
942 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE1()) {
943 addRegisterClass(MVT::v4f32, &X86::VR128RegClass);
945 setOperationAction(ISD::FADD, MVT::v4f32, Legal);
946 setOperationAction(ISD::FSUB, MVT::v4f32, Legal);
947 setOperationAction(ISD::FMUL, MVT::v4f32, Legal);
948 setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
949 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal);
950 setOperationAction(ISD::FNEG, MVT::v4f32, Custom);
951 setOperationAction(ISD::FABS, MVT::v4f32, Custom);
952 setOperationAction(ISD::LOAD, MVT::v4f32, Legal);
953 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
954 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f32, Custom);
955 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
956 setOperationAction(ISD::SELECT, MVT::v4f32, Custom);
959 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE2()) {
960 addRegisterClass(MVT::v2f64, &X86::VR128RegClass);
962 // FIXME: Unfortunately, -soft-float and -no-implicit-float mean XMM
963 // registers cannot be used even for integer operations.
964 addRegisterClass(MVT::v16i8, &X86::VR128RegClass);
965 addRegisterClass(MVT::v8i16, &X86::VR128RegClass);
966 addRegisterClass(MVT::v4i32, &X86::VR128RegClass);
967 addRegisterClass(MVT::v2i64, &X86::VR128RegClass);
969 setOperationAction(ISD::ADD, MVT::v16i8, Legal);
970 setOperationAction(ISD::ADD, MVT::v8i16, Legal);
971 setOperationAction(ISD::ADD, MVT::v4i32, Legal);
972 setOperationAction(ISD::ADD, MVT::v2i64, Legal);
973 setOperationAction(ISD::MUL, MVT::v4i32, Custom);
974 setOperationAction(ISD::MUL, MVT::v2i64, Custom);
975 setOperationAction(ISD::UMUL_LOHI, MVT::v4i32, Custom);
976 setOperationAction(ISD::SMUL_LOHI, MVT::v4i32, Custom);
977 setOperationAction(ISD::MULHU, MVT::v8i16, Legal);
978 setOperationAction(ISD::MULHS, MVT::v8i16, Legal);
979 setOperationAction(ISD::SUB, MVT::v16i8, Legal);
980 setOperationAction(ISD::SUB, MVT::v8i16, Legal);
981 setOperationAction(ISD::SUB, MVT::v4i32, Legal);
982 setOperationAction(ISD::SUB, MVT::v2i64, Legal);
983 setOperationAction(ISD::MUL, MVT::v8i16, Legal);
984 setOperationAction(ISD::FADD, MVT::v2f64, Legal);
985 setOperationAction(ISD::FSUB, MVT::v2f64, Legal);
986 setOperationAction(ISD::FMUL, MVT::v2f64, Legal);
987 setOperationAction(ISD::FDIV, MVT::v2f64, Legal);
988 setOperationAction(ISD::FSQRT, MVT::v2f64, Legal);
989 setOperationAction(ISD::FNEG, MVT::v2f64, Custom);
990 setOperationAction(ISD::FABS, MVT::v2f64, Custom);
992 setOperationAction(ISD::SETCC, MVT::v2i64, Custom);
993 setOperationAction(ISD::SETCC, MVT::v16i8, Custom);
994 setOperationAction(ISD::SETCC, MVT::v8i16, Custom);
995 setOperationAction(ISD::SETCC, MVT::v4i32, Custom);
997 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Custom);
998 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Custom);
999 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
1000 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
1001 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
1003 // Custom lower build_vector, vector_shuffle, and extract_vector_elt.
1004 for (int i = MVT::v16i8; i != MVT::v2i64; ++i) {
1005 MVT VT = (MVT::SimpleValueType)i;
1006 // Do not attempt to custom lower non-power-of-2 vectors
1007 if (!isPowerOf2_32(VT.getVectorNumElements()))
1009 // Do not attempt to custom lower non-128-bit vectors
1010 if (!VT.is128BitVector())
1012 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1013 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1014 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1017 // We support custom legalizing of sext and anyext loads for specific
1018 // memory vector types which we can load as a scalar (or sequence of
1019 // scalars) and extend in-register to a legal 128-bit vector type. For sext
1020 // loads these must work with a single scalar load.
1021 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i8, Custom);
1022 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i16, Custom);
1023 setLoadExtAction(ISD::SEXTLOAD, MVT::v8i8, Custom);
1024 setLoadExtAction(ISD::EXTLOAD, MVT::v2i8, Custom);
1025 setLoadExtAction(ISD::EXTLOAD, MVT::v2i16, Custom);
1026 setLoadExtAction(ISD::EXTLOAD, MVT::v2i32, Custom);
1027 setLoadExtAction(ISD::EXTLOAD, MVT::v4i8, Custom);
1028 setLoadExtAction(ISD::EXTLOAD, MVT::v4i16, Custom);
1029 setLoadExtAction(ISD::EXTLOAD, MVT::v8i8, Custom);
1031 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f64, Custom);
1032 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i64, Custom);
1033 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Custom);
1034 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Custom);
1035 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f64, Custom);
1036 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Custom);
1038 if (Subtarget->is64Bit()) {
1039 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
1040 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
1043 // Promote v16i8, v8i16, v4i32 load, select, and, or, xor to v2i64.
1044 for (int i = MVT::v16i8; i != MVT::v2i64; ++i) {
1045 MVT VT = (MVT::SimpleValueType)i;
1047 // Do not attempt to promote non-128-bit vectors
1048 if (!VT.is128BitVector())
1051 setOperationAction(ISD::AND, VT, Promote);
1052 AddPromotedToType (ISD::AND, VT, MVT::v2i64);
1053 setOperationAction(ISD::OR, VT, Promote);
1054 AddPromotedToType (ISD::OR, VT, MVT::v2i64);
1055 setOperationAction(ISD::XOR, VT, Promote);
1056 AddPromotedToType (ISD::XOR, VT, MVT::v2i64);
1057 setOperationAction(ISD::LOAD, VT, Promote);
1058 AddPromotedToType (ISD::LOAD, VT, MVT::v2i64);
1059 setOperationAction(ISD::SELECT, VT, Promote);
1060 AddPromotedToType (ISD::SELECT, VT, MVT::v2i64);
1063 // Custom lower v2i64 and v2f64 selects.
1064 setOperationAction(ISD::LOAD, MVT::v2f64, Legal);
1065 setOperationAction(ISD::LOAD, MVT::v2i64, Legal);
1066 setOperationAction(ISD::SELECT, MVT::v2f64, Custom);
1067 setOperationAction(ISD::SELECT, MVT::v2i64, Custom);
1069 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal);
1070 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal);
1072 setOperationAction(ISD::UINT_TO_FP, MVT::v4i8, Custom);
1073 setOperationAction(ISD::UINT_TO_FP, MVT::v4i16, Custom);
1074 // As there is no 64-bit GPR available, we need build a special custom
1075 // sequence to convert from v2i32 to v2f32.
1076 if (!Subtarget->is64Bit())
1077 setOperationAction(ISD::UINT_TO_FP, MVT::v2f32, Custom);
1079 setOperationAction(ISD::FP_EXTEND, MVT::v2f32, Custom);
1080 setOperationAction(ISD::FP_ROUND, MVT::v2f32, Custom);
1082 setLoadExtAction(ISD::EXTLOAD, MVT::v2f32, Legal);
1084 setOperationAction(ISD::BITCAST, MVT::v2i32, Custom);
1085 setOperationAction(ISD::BITCAST, MVT::v4i16, Custom);
1086 setOperationAction(ISD::BITCAST, MVT::v8i8, Custom);
1089 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE41()) {
1090 setOperationAction(ISD::FFLOOR, MVT::f32, Legal);
1091 setOperationAction(ISD::FCEIL, MVT::f32, Legal);
1092 setOperationAction(ISD::FTRUNC, MVT::f32, Legal);
1093 setOperationAction(ISD::FRINT, MVT::f32, Legal);
1094 setOperationAction(ISD::FNEARBYINT, MVT::f32, Legal);
1095 setOperationAction(ISD::FFLOOR, MVT::f64, Legal);
1096 setOperationAction(ISD::FCEIL, MVT::f64, Legal);
1097 setOperationAction(ISD::FTRUNC, MVT::f64, Legal);
1098 setOperationAction(ISD::FRINT, MVT::f64, Legal);
1099 setOperationAction(ISD::FNEARBYINT, MVT::f64, Legal);
1101 setOperationAction(ISD::FFLOOR, MVT::v4f32, Legal);
1102 setOperationAction(ISD::FCEIL, MVT::v4f32, Legal);
1103 setOperationAction(ISD::FTRUNC, MVT::v4f32, Legal);
1104 setOperationAction(ISD::FRINT, MVT::v4f32, Legal);
1105 setOperationAction(ISD::FNEARBYINT, MVT::v4f32, Legal);
1106 setOperationAction(ISD::FFLOOR, MVT::v2f64, Legal);
1107 setOperationAction(ISD::FCEIL, MVT::v2f64, Legal);
1108 setOperationAction(ISD::FTRUNC, MVT::v2f64, Legal);
1109 setOperationAction(ISD::FRINT, MVT::v2f64, Legal);
1110 setOperationAction(ISD::FNEARBYINT, MVT::v2f64, Legal);
1112 // FIXME: Do we need to handle scalar-to-vector here?
1113 setOperationAction(ISD::MUL, MVT::v4i32, Legal);
1115 setOperationAction(ISD::VSELECT, MVT::v2f64, Custom);
1116 setOperationAction(ISD::VSELECT, MVT::v2i64, Custom);
1117 setOperationAction(ISD::VSELECT, MVT::v4i32, Custom);
1118 setOperationAction(ISD::VSELECT, MVT::v4f32, Custom);
1119 setOperationAction(ISD::VSELECT, MVT::v8i16, Custom);
1120 // There is no BLENDI for byte vectors. We don't need to custom lower
1121 // some vselects for now.
1122 setOperationAction(ISD::VSELECT, MVT::v16i8, Legal);
1124 // SSE41 brings specific instructions for doing vector sign extend even in
1125 // cases where we don't have SRA.
1126 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i8, Custom);
1127 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i16, Custom);
1128 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i32, Custom);
1130 // i8 and i16 vectors are custom because the source register and source
1131 // source memory operand types are not the same width. f32 vectors are
1132 // custom since the immediate controlling the insert encodes additional
1134 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i8, Custom);
1135 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
1136 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
1137 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
1139 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i8, Custom);
1140 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i16, Custom);
1141 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i32, Custom);
1142 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
1144 // FIXME: these should be Legal, but that's only for the case where
1145 // the index is constant. For now custom expand to deal with that.
1146 if (Subtarget->is64Bit()) {
1147 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
1148 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
1152 if (Subtarget->hasSSE2()) {
1153 setOperationAction(ISD::SRL, MVT::v8i16, Custom);
1154 setOperationAction(ISD::SRL, MVT::v16i8, Custom);
1156 setOperationAction(ISD::SHL, MVT::v8i16, Custom);
1157 setOperationAction(ISD::SHL, MVT::v16i8, Custom);
1159 setOperationAction(ISD::SRA, MVT::v8i16, Custom);
1160 setOperationAction(ISD::SRA, MVT::v16i8, Custom);
1162 // In the customized shift lowering, the legal cases in AVX2 will be
1164 setOperationAction(ISD::SRL, MVT::v2i64, Custom);
1165 setOperationAction(ISD::SRL, MVT::v4i32, Custom);
1167 setOperationAction(ISD::SHL, MVT::v2i64, Custom);
1168 setOperationAction(ISD::SHL, MVT::v4i32, Custom);
1170 setOperationAction(ISD::SRA, MVT::v4i32, Custom);
1173 if (!TM.Options.UseSoftFloat && Subtarget->hasFp256()) {
1174 addRegisterClass(MVT::v32i8, &X86::VR256RegClass);
1175 addRegisterClass(MVT::v16i16, &X86::VR256RegClass);
1176 addRegisterClass(MVT::v8i32, &X86::VR256RegClass);
1177 addRegisterClass(MVT::v8f32, &X86::VR256RegClass);
1178 addRegisterClass(MVT::v4i64, &X86::VR256RegClass);
1179 addRegisterClass(MVT::v4f64, &X86::VR256RegClass);
1181 setOperationAction(ISD::LOAD, MVT::v8f32, Legal);
1182 setOperationAction(ISD::LOAD, MVT::v4f64, Legal);
1183 setOperationAction(ISD::LOAD, MVT::v4i64, Legal);
1185 setOperationAction(ISD::FADD, MVT::v8f32, Legal);
1186 setOperationAction(ISD::FSUB, MVT::v8f32, Legal);
1187 setOperationAction(ISD::FMUL, MVT::v8f32, Legal);
1188 setOperationAction(ISD::FDIV, MVT::v8f32, Legal);
1189 setOperationAction(ISD::FSQRT, MVT::v8f32, Legal);
1190 setOperationAction(ISD::FFLOOR, MVT::v8f32, Legal);
1191 setOperationAction(ISD::FCEIL, MVT::v8f32, Legal);
1192 setOperationAction(ISD::FTRUNC, MVT::v8f32, Legal);
1193 setOperationAction(ISD::FRINT, MVT::v8f32, Legal);
1194 setOperationAction(ISD::FNEARBYINT, MVT::v8f32, Legal);
1195 setOperationAction(ISD::FNEG, MVT::v8f32, Custom);
1196 setOperationAction(ISD::FABS, MVT::v8f32, Custom);
1198 setOperationAction(ISD::FADD, MVT::v4f64, Legal);
1199 setOperationAction(ISD::FSUB, MVT::v4f64, Legal);
1200 setOperationAction(ISD::FMUL, MVT::v4f64, Legal);
1201 setOperationAction(ISD::FDIV, MVT::v4f64, Legal);
1202 setOperationAction(ISD::FSQRT, MVT::v4f64, Legal);
1203 setOperationAction(ISD::FFLOOR, MVT::v4f64, Legal);
1204 setOperationAction(ISD::FCEIL, MVT::v4f64, Legal);
1205 setOperationAction(ISD::FTRUNC, MVT::v4f64, Legal);
1206 setOperationAction(ISD::FRINT, MVT::v4f64, Legal);
1207 setOperationAction(ISD::FNEARBYINT, MVT::v4f64, Legal);
1208 setOperationAction(ISD::FNEG, MVT::v4f64, Custom);
1209 setOperationAction(ISD::FABS, MVT::v4f64, Custom);
1211 // (fp_to_int:v8i16 (v8f32 ..)) requires the result type to be promoted
1212 // even though v8i16 is a legal type.
1213 setOperationAction(ISD::FP_TO_SINT, MVT::v8i16, Promote);
1214 setOperationAction(ISD::FP_TO_UINT, MVT::v8i16, Promote);
1215 setOperationAction(ISD::FP_TO_SINT, MVT::v8i32, Legal);
1217 setOperationAction(ISD::SINT_TO_FP, MVT::v8i16, Promote);
1218 setOperationAction(ISD::SINT_TO_FP, MVT::v8i32, Legal);
1219 setOperationAction(ISD::FP_ROUND, MVT::v4f32, Legal);
1221 setOperationAction(ISD::UINT_TO_FP, MVT::v8i8, Custom);
1222 setOperationAction(ISD::UINT_TO_FP, MVT::v8i16, Custom);
1224 setLoadExtAction(ISD::EXTLOAD, MVT::v4f32, Legal);
1226 setOperationAction(ISD::SRL, MVT::v16i16, Custom);
1227 setOperationAction(ISD::SRL, MVT::v32i8, Custom);
1229 setOperationAction(ISD::SHL, MVT::v16i16, Custom);
1230 setOperationAction(ISD::SHL, MVT::v32i8, Custom);
1232 setOperationAction(ISD::SRA, MVT::v16i16, Custom);
1233 setOperationAction(ISD::SRA, MVT::v32i8, Custom);
1235 setOperationAction(ISD::SETCC, MVT::v32i8, Custom);
1236 setOperationAction(ISD::SETCC, MVT::v16i16, Custom);
1237 setOperationAction(ISD::SETCC, MVT::v8i32, Custom);
1238 setOperationAction(ISD::SETCC, MVT::v4i64, Custom);
1240 setOperationAction(ISD::SELECT, MVT::v4f64, Custom);
1241 setOperationAction(ISD::SELECT, MVT::v4i64, Custom);
1242 setOperationAction(ISD::SELECT, MVT::v8f32, Custom);
1244 setOperationAction(ISD::VSELECT, MVT::v4f64, Custom);
1245 setOperationAction(ISD::VSELECT, MVT::v4i64, Custom);
1246 setOperationAction(ISD::VSELECT, MVT::v8i32, Custom);
1247 setOperationAction(ISD::VSELECT, MVT::v8f32, Custom);
1249 setOperationAction(ISD::SIGN_EXTEND, MVT::v4i64, Custom);
1250 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i32, Custom);
1251 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i16, Custom);
1252 setOperationAction(ISD::ZERO_EXTEND, MVT::v4i64, Custom);
1253 setOperationAction(ISD::ZERO_EXTEND, MVT::v8i32, Custom);
1254 setOperationAction(ISD::ZERO_EXTEND, MVT::v16i16, Custom);
1255 setOperationAction(ISD::ANY_EXTEND, MVT::v4i64, Custom);
1256 setOperationAction(ISD::ANY_EXTEND, MVT::v8i32, Custom);
1257 setOperationAction(ISD::ANY_EXTEND, MVT::v16i16, Custom);
1258 setOperationAction(ISD::TRUNCATE, MVT::v16i8, Custom);
1259 setOperationAction(ISD::TRUNCATE, MVT::v8i16, Custom);
1260 setOperationAction(ISD::TRUNCATE, MVT::v4i32, Custom);
1262 if (Subtarget->hasFMA() || Subtarget->hasFMA4()) {
1263 setOperationAction(ISD::FMA, MVT::v8f32, Legal);
1264 setOperationAction(ISD::FMA, MVT::v4f64, Legal);
1265 setOperationAction(ISD::FMA, MVT::v4f32, Legal);
1266 setOperationAction(ISD::FMA, MVT::v2f64, Legal);
1267 setOperationAction(ISD::FMA, MVT::f32, Legal);
1268 setOperationAction(ISD::FMA, MVT::f64, Legal);
1271 if (Subtarget->hasInt256()) {
1272 setOperationAction(ISD::ADD, MVT::v4i64, Legal);
1273 setOperationAction(ISD::ADD, MVT::v8i32, Legal);
1274 setOperationAction(ISD::ADD, MVT::v16i16, Legal);
1275 setOperationAction(ISD::ADD, MVT::v32i8, Legal);
1277 setOperationAction(ISD::SUB, MVT::v4i64, Legal);
1278 setOperationAction(ISD::SUB, MVT::v8i32, Legal);
1279 setOperationAction(ISD::SUB, MVT::v16i16, Legal);
1280 setOperationAction(ISD::SUB, MVT::v32i8, Legal);
1282 setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1283 setOperationAction(ISD::MUL, MVT::v8i32, Legal);
1284 setOperationAction(ISD::MUL, MVT::v16i16, Legal);
1285 // Don't lower v32i8 because there is no 128-bit byte mul
1287 setOperationAction(ISD::UMUL_LOHI, MVT::v8i32, Custom);
1288 setOperationAction(ISD::SMUL_LOHI, MVT::v8i32, Custom);
1289 setOperationAction(ISD::MULHU, MVT::v16i16, Legal);
1290 setOperationAction(ISD::MULHS, MVT::v16i16, Legal);
1292 setOperationAction(ISD::VSELECT, MVT::v16i16, Custom);
1293 setOperationAction(ISD::VSELECT, MVT::v32i8, Legal);
1295 setOperationAction(ISD::ADD, MVT::v4i64, Custom);
1296 setOperationAction(ISD::ADD, MVT::v8i32, Custom);
1297 setOperationAction(ISD::ADD, MVT::v16i16, Custom);
1298 setOperationAction(ISD::ADD, MVT::v32i8, Custom);
1300 setOperationAction(ISD::SUB, MVT::v4i64, Custom);
1301 setOperationAction(ISD::SUB, MVT::v8i32, Custom);
1302 setOperationAction(ISD::SUB, MVT::v16i16, Custom);
1303 setOperationAction(ISD::SUB, MVT::v32i8, Custom);
1305 setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1306 setOperationAction(ISD::MUL, MVT::v8i32, Custom);
1307 setOperationAction(ISD::MUL, MVT::v16i16, Custom);
1308 // Don't lower v32i8 because there is no 128-bit byte mul
1311 // In the customized shift lowering, the legal cases in AVX2 will be
1313 setOperationAction(ISD::SRL, MVT::v4i64, Custom);
1314 setOperationAction(ISD::SRL, MVT::v8i32, Custom);
1316 setOperationAction(ISD::SHL, MVT::v4i64, Custom);
1317 setOperationAction(ISD::SHL, MVT::v8i32, Custom);
1319 setOperationAction(ISD::SRA, MVT::v8i32, Custom);
1321 // Custom lower several nodes for 256-bit types.
1322 for (int i = MVT::FIRST_VECTOR_VALUETYPE;
1323 i <= MVT::LAST_VECTOR_VALUETYPE; ++i) {
1324 MVT VT = (MVT::SimpleValueType)i;
1326 // Extract subvector is special because the value type
1327 // (result) is 128-bit but the source is 256-bit wide.
1328 if (VT.is128BitVector())
1329 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom);
1331 // Do not attempt to custom lower other non-256-bit vectors
1332 if (!VT.is256BitVector())
1335 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1336 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1337 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
1338 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1339 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom);
1340 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom);
1341 setOperationAction(ISD::CONCAT_VECTORS, VT, Custom);
1344 // Promote v32i8, v16i16, v8i32 select, and, or, xor to v4i64.
1345 for (int i = MVT::v32i8; i != MVT::v4i64; ++i) {
1346 MVT VT = (MVT::SimpleValueType)i;
1348 // Do not attempt to promote non-256-bit vectors
1349 if (!VT.is256BitVector())
1352 setOperationAction(ISD::AND, VT, Promote);
1353 AddPromotedToType (ISD::AND, VT, MVT::v4i64);
1354 setOperationAction(ISD::OR, VT, Promote);
1355 AddPromotedToType (ISD::OR, VT, MVT::v4i64);
1356 setOperationAction(ISD::XOR, VT, Promote);
1357 AddPromotedToType (ISD::XOR, VT, MVT::v4i64);
1358 setOperationAction(ISD::LOAD, VT, Promote);
1359 AddPromotedToType (ISD::LOAD, VT, MVT::v4i64);
1360 setOperationAction(ISD::SELECT, VT, Promote);
1361 AddPromotedToType (ISD::SELECT, VT, MVT::v4i64);
1365 if (!TM.Options.UseSoftFloat && Subtarget->hasAVX512()) {
1366 addRegisterClass(MVT::v16i32, &X86::VR512RegClass);
1367 addRegisterClass(MVT::v16f32, &X86::VR512RegClass);
1368 addRegisterClass(MVT::v8i64, &X86::VR512RegClass);
1369 addRegisterClass(MVT::v8f64, &X86::VR512RegClass);
1371 addRegisterClass(MVT::i1, &X86::VK1RegClass);
1372 addRegisterClass(MVT::v8i1, &X86::VK8RegClass);
1373 addRegisterClass(MVT::v16i1, &X86::VK16RegClass);
1375 setOperationAction(ISD::BR_CC, MVT::i1, Expand);
1376 setOperationAction(ISD::SETCC, MVT::i1, Custom);
1377 setOperationAction(ISD::XOR, MVT::i1, Legal);
1378 setOperationAction(ISD::OR, MVT::i1, Legal);
1379 setOperationAction(ISD::AND, MVT::i1, Legal);
1380 setLoadExtAction(ISD::EXTLOAD, MVT::v8f32, Legal);
1381 setOperationAction(ISD::LOAD, MVT::v16f32, Legal);
1382 setOperationAction(ISD::LOAD, MVT::v8f64, Legal);
1383 setOperationAction(ISD::LOAD, MVT::v8i64, Legal);
1384 setOperationAction(ISD::LOAD, MVT::v16i32, Legal);
1385 setOperationAction(ISD::LOAD, MVT::v16i1, Legal);
1387 setOperationAction(ISD::FADD, MVT::v16f32, Legal);
1388 setOperationAction(ISD::FSUB, MVT::v16f32, Legal);
1389 setOperationAction(ISD::FMUL, MVT::v16f32, Legal);
1390 setOperationAction(ISD::FDIV, MVT::v16f32, Legal);
1391 setOperationAction(ISD::FSQRT, MVT::v16f32, Legal);
1392 setOperationAction(ISD::FNEG, MVT::v16f32, Custom);
1394 setOperationAction(ISD::FADD, MVT::v8f64, Legal);
1395 setOperationAction(ISD::FSUB, MVT::v8f64, Legal);
1396 setOperationAction(ISD::FMUL, MVT::v8f64, Legal);
1397 setOperationAction(ISD::FDIV, MVT::v8f64, Legal);
1398 setOperationAction(ISD::FSQRT, MVT::v8f64, Legal);
1399 setOperationAction(ISD::FNEG, MVT::v8f64, Custom);
1400 setOperationAction(ISD::FMA, MVT::v8f64, Legal);
1401 setOperationAction(ISD::FMA, MVT::v16f32, Legal);
1403 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Legal);
1404 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Legal);
1405 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Legal);
1406 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Legal);
1407 if (Subtarget->is64Bit()) {
1408 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Legal);
1409 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Legal);
1410 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Legal);
1411 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Legal);
1413 setOperationAction(ISD::FP_TO_SINT, MVT::v16i32, Legal);
1414 setOperationAction(ISD::FP_TO_UINT, MVT::v16i32, Legal);
1415 setOperationAction(ISD::FP_TO_UINT, MVT::v8i32, Legal);
1416 setOperationAction(ISD::FP_TO_UINT, MVT::v4i32, Legal);
1417 setOperationAction(ISD::SINT_TO_FP, MVT::v16i32, Legal);
1418 setOperationAction(ISD::UINT_TO_FP, MVT::v16i32, Legal);
1419 setOperationAction(ISD::UINT_TO_FP, MVT::v8i32, Legal);
1420 setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Legal);
1421 setOperationAction(ISD::FP_ROUND, MVT::v8f32, Legal);
1422 setOperationAction(ISD::FP_EXTEND, MVT::v8f32, Legal);
1424 setOperationAction(ISD::TRUNCATE, MVT::i1, Custom);
1425 setOperationAction(ISD::TRUNCATE, MVT::v16i8, Custom);
1426 setOperationAction(ISD::TRUNCATE, MVT::v8i32, Custom);
1427 setOperationAction(ISD::TRUNCATE, MVT::v8i1, Custom);
1428 setOperationAction(ISD::TRUNCATE, MVT::v16i1, Custom);
1429 setOperationAction(ISD::TRUNCATE, MVT::v16i16, Custom);
1430 setOperationAction(ISD::ZERO_EXTEND, MVT::v16i32, Custom);
1431 setOperationAction(ISD::ZERO_EXTEND, MVT::v8i64, Custom);
1432 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i32, Custom);
1433 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i64, Custom);
1434 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i8, Custom);
1435 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i16, Custom);
1436 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i16, Custom);
1438 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8f64, Custom);
1439 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i64, Custom);
1440 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16f32, Custom);
1441 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i32, Custom);
1442 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i1, Custom);
1443 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i1, Legal);
1445 setOperationAction(ISD::SETCC, MVT::v16i1, Custom);
1446 setOperationAction(ISD::SETCC, MVT::v8i1, Custom);
1448 setOperationAction(ISD::MUL, MVT::v8i64, Custom);
1450 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i1, Custom);
1451 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i1, Custom);
1452 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i1, Custom);
1453 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i1, Custom);
1454 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i1, Custom);
1455 setOperationAction(ISD::BUILD_VECTOR, MVT::v16i1, Custom);
1456 setOperationAction(ISD::SELECT, MVT::v8f64, Custom);
1457 setOperationAction(ISD::SELECT, MVT::v8i64, Custom);
1458 setOperationAction(ISD::SELECT, MVT::v16f32, Custom);
1460 setOperationAction(ISD::ADD, MVT::v8i64, Legal);
1461 setOperationAction(ISD::ADD, MVT::v16i32, Legal);
1463 setOperationAction(ISD::SUB, MVT::v8i64, Legal);
1464 setOperationAction(ISD::SUB, MVT::v16i32, Legal);
1466 setOperationAction(ISD::MUL, MVT::v16i32, Legal);
1468 setOperationAction(ISD::SRL, MVT::v8i64, Custom);
1469 setOperationAction(ISD::SRL, MVT::v16i32, Custom);
1471 setOperationAction(ISD::SHL, MVT::v8i64, Custom);
1472 setOperationAction(ISD::SHL, MVT::v16i32, Custom);
1474 setOperationAction(ISD::SRA, MVT::v8i64, Custom);
1475 setOperationAction(ISD::SRA, MVT::v16i32, Custom);
1477 setOperationAction(ISD::AND, MVT::v8i64, Legal);
1478 setOperationAction(ISD::OR, MVT::v8i64, Legal);
1479 setOperationAction(ISD::XOR, MVT::v8i64, Legal);
1480 setOperationAction(ISD::AND, MVT::v16i32, Legal);
1481 setOperationAction(ISD::OR, MVT::v16i32, Legal);
1482 setOperationAction(ISD::XOR, MVT::v16i32, Legal);
1484 if (Subtarget->hasCDI()) {
1485 setOperationAction(ISD::CTLZ, MVT::v8i64, Legal);
1486 setOperationAction(ISD::CTLZ, MVT::v16i32, Legal);
1489 // Custom lower several nodes.
1490 for (int i = MVT::FIRST_VECTOR_VALUETYPE;
1491 i <= MVT::LAST_VECTOR_VALUETYPE; ++i) {
1492 MVT VT = (MVT::SimpleValueType)i;
1494 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
1495 // Extract subvector is special because the value type
1496 // (result) is 256/128-bit but the source is 512-bit wide.
1497 if (VT.is128BitVector() || VT.is256BitVector())
1498 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom);
1500 if (VT.getVectorElementType() == MVT::i1)
1501 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Legal);
1503 // Do not attempt to custom lower other non-512-bit vectors
1504 if (!VT.is512BitVector())
1507 if ( EltSize >= 32) {
1508 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1509 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
1510 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1511 setOperationAction(ISD::VSELECT, VT, Legal);
1512 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1513 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom);
1514 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom);
1517 for (int i = MVT::v32i8; i != MVT::v8i64; ++i) {
1518 MVT VT = (MVT::SimpleValueType)i;
1520 // Do not attempt to promote non-256-bit vectors
1521 if (!VT.is512BitVector())
1524 setOperationAction(ISD::SELECT, VT, Promote);
1525 AddPromotedToType (ISD::SELECT, VT, MVT::v8i64);
1529 if (!TM.Options.UseSoftFloat && Subtarget->hasBWI()) {
1530 addRegisterClass(MVT::v32i16, &X86::VR512RegClass);
1531 addRegisterClass(MVT::v64i8, &X86::VR512RegClass);
1533 addRegisterClass(MVT::v32i1, &X86::VK32RegClass);
1534 addRegisterClass(MVT::v64i1, &X86::VK64RegClass);
1536 setOperationAction(ISD::LOAD, MVT::v32i16, Legal);
1537 setOperationAction(ISD::LOAD, MVT::v64i8, Legal);
1538 setOperationAction(ISD::SETCC, MVT::v32i1, Custom);
1539 setOperationAction(ISD::SETCC, MVT::v64i1, Custom);
1541 for (int i = MVT::v32i8; i != MVT::v8i64; ++i) {
1542 const MVT VT = (MVT::SimpleValueType)i;
1544 const unsigned EltSize = VT.getVectorElementType().getSizeInBits();
1546 // Do not attempt to promote non-256-bit vectors
1547 if (!VT.is512BitVector())
1550 if ( EltSize < 32) {
1551 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1552 setOperationAction(ISD::VSELECT, VT, Legal);
1557 if (!TM.Options.UseSoftFloat && Subtarget->hasVLX()) {
1558 addRegisterClass(MVT::v4i1, &X86::VK4RegClass);
1559 addRegisterClass(MVT::v2i1, &X86::VK2RegClass);
1561 setOperationAction(ISD::SETCC, MVT::v4i1, Custom);
1562 setOperationAction(ISD::SETCC, MVT::v2i1, Custom);
1565 // SIGN_EXTEND_INREGs are evaluated by the extend type. Handle the expansion
1566 // of this type with custom code.
1567 for (int VT = MVT::FIRST_VECTOR_VALUETYPE;
1568 VT != MVT::LAST_VECTOR_VALUETYPE; VT++) {
1569 setOperationAction(ISD::SIGN_EXTEND_INREG, (MVT::SimpleValueType)VT,
1573 // We want to custom lower some of our intrinsics.
1574 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
1575 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::Other, Custom);
1576 setOperationAction(ISD::INTRINSIC_VOID, MVT::Other, Custom);
1577 if (!Subtarget->is64Bit())
1578 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::i64, Custom);
1580 // Only custom-lower 64-bit SADDO and friends on 64-bit because we don't
1581 // handle type legalization for these operations here.
1583 // FIXME: We really should do custom legalization for addition and
1584 // subtraction on x86-32 once PR3203 is fixed. We really can't do much better
1585 // than generic legalization for 64-bit multiplication-with-overflow, though.
1586 for (unsigned i = 0, e = 3+Subtarget->is64Bit(); i != e; ++i) {
1587 // Add/Sub/Mul with overflow operations are custom lowered.
1589 setOperationAction(ISD::SADDO, VT, Custom);
1590 setOperationAction(ISD::UADDO, VT, Custom);
1591 setOperationAction(ISD::SSUBO, VT, Custom);
1592 setOperationAction(ISD::USUBO, VT, Custom);
1593 setOperationAction(ISD::SMULO, VT, Custom);
1594 setOperationAction(ISD::UMULO, VT, Custom);
1597 // There are no 8-bit 3-address imul/mul instructions
1598 setOperationAction(ISD::SMULO, MVT::i8, Expand);
1599 setOperationAction(ISD::UMULO, MVT::i8, Expand);
1601 if (!Subtarget->is64Bit()) {
1602 // These libcalls are not available in 32-bit.
1603 setLibcallName(RTLIB::SHL_I128, nullptr);
1604 setLibcallName(RTLIB::SRL_I128, nullptr);
1605 setLibcallName(RTLIB::SRA_I128, nullptr);
1608 // Combine sin / cos into one node or libcall if possible.
1609 if (Subtarget->hasSinCos()) {
1610 setLibcallName(RTLIB::SINCOS_F32, "sincosf");
1611 setLibcallName(RTLIB::SINCOS_F64, "sincos");
1612 if (Subtarget->isTargetDarwin()) {
1613 // For MacOSX, we don't want to the normal expansion of a libcall to
1614 // sincos. We want to issue a libcall to __sincos_stret to avoid memory
1616 setOperationAction(ISD::FSINCOS, MVT::f64, Custom);
1617 setOperationAction(ISD::FSINCOS, MVT::f32, Custom);
1621 if (Subtarget->isTargetWin64()) {
1622 setOperationAction(ISD::SDIV, MVT::i128, Custom);
1623 setOperationAction(ISD::UDIV, MVT::i128, Custom);
1624 setOperationAction(ISD::SREM, MVT::i128, Custom);
1625 setOperationAction(ISD::UREM, MVT::i128, Custom);
1626 setOperationAction(ISD::SDIVREM, MVT::i128, Custom);
1627 setOperationAction(ISD::UDIVREM, MVT::i128, Custom);
1630 // We have target-specific dag combine patterns for the following nodes:
1631 setTargetDAGCombine(ISD::VECTOR_SHUFFLE);
1632 setTargetDAGCombine(ISD::EXTRACT_VECTOR_ELT);
1633 setTargetDAGCombine(ISD::VSELECT);
1634 setTargetDAGCombine(ISD::SELECT);
1635 setTargetDAGCombine(ISD::SHL);
1636 setTargetDAGCombine(ISD::SRA);
1637 setTargetDAGCombine(ISD::SRL);
1638 setTargetDAGCombine(ISD::OR);
1639 setTargetDAGCombine(ISD::AND);
1640 setTargetDAGCombine(ISD::ADD);
1641 setTargetDAGCombine(ISD::FADD);
1642 setTargetDAGCombine(ISD::FSUB);
1643 setTargetDAGCombine(ISD::FMA);
1644 setTargetDAGCombine(ISD::SUB);
1645 setTargetDAGCombine(ISD::LOAD);
1646 setTargetDAGCombine(ISD::STORE);
1647 setTargetDAGCombine(ISD::ZERO_EXTEND);
1648 setTargetDAGCombine(ISD::ANY_EXTEND);
1649 setTargetDAGCombine(ISD::SIGN_EXTEND);
1650 setTargetDAGCombine(ISD::SIGN_EXTEND_INREG);
1651 setTargetDAGCombine(ISD::TRUNCATE);
1652 setTargetDAGCombine(ISD::SINT_TO_FP);
1653 setTargetDAGCombine(ISD::SETCC);
1654 setTargetDAGCombine(ISD::INTRINSIC_WO_CHAIN);
1655 setTargetDAGCombine(ISD::BUILD_VECTOR);
1656 if (Subtarget->is64Bit())
1657 setTargetDAGCombine(ISD::MUL);
1658 setTargetDAGCombine(ISD::XOR);
1660 computeRegisterProperties();
1662 // On Darwin, -Os means optimize for size without hurting performance,
1663 // do not reduce the limit.
1664 MaxStoresPerMemset = 16; // For @llvm.memset -> sequence of stores
1665 MaxStoresPerMemsetOptSize = Subtarget->isTargetDarwin() ? 16 : 8;
1666 MaxStoresPerMemcpy = 8; // For @llvm.memcpy -> sequence of stores
1667 MaxStoresPerMemcpyOptSize = Subtarget->isTargetDarwin() ? 8 : 4;
1668 MaxStoresPerMemmove = 8; // For @llvm.memmove -> sequence of stores
1669 MaxStoresPerMemmoveOptSize = Subtarget->isTargetDarwin() ? 8 : 4;
1670 setPrefLoopAlignment(4); // 2^4 bytes.
1672 // Predictable cmov don't hurt on atom because it's in-order.
1673 PredictableSelectIsExpensive = !Subtarget->isAtom();
1675 setPrefFunctionAlignment(4); // 2^4 bytes.
1677 verifyIntrinsicTables();
1680 // This has so far only been implemented for 64-bit MachO.
1681 bool X86TargetLowering::useLoadStackGuardNode() const {
1682 return Subtarget->getTargetTriple().getObjectFormat() == Triple::MachO &&
1683 Subtarget->is64Bit();
1686 TargetLoweringBase::LegalizeTypeAction
1687 X86TargetLowering::getPreferredVectorAction(EVT VT) const {
1688 if (ExperimentalVectorWideningLegalization &&
1689 VT.getVectorNumElements() != 1 &&
1690 VT.getVectorElementType().getSimpleVT() != MVT::i1)
1691 return TypeWidenVector;
1693 return TargetLoweringBase::getPreferredVectorAction(VT);
1696 EVT X86TargetLowering::getSetCCResultType(LLVMContext &, EVT VT) const {
1698 return Subtarget->hasAVX512() ? MVT::i1: MVT::i8;
1700 const unsigned NumElts = VT.getVectorNumElements();
1701 const EVT EltVT = VT.getVectorElementType();
1702 if (VT.is512BitVector()) {
1703 if (Subtarget->hasAVX512())
1704 if (EltVT == MVT::i32 || EltVT == MVT::i64 ||
1705 EltVT == MVT::f32 || EltVT == MVT::f64)
1707 case 8: return MVT::v8i1;
1708 case 16: return MVT::v16i1;
1710 if (Subtarget->hasBWI())
1711 if (EltVT == MVT::i8 || EltVT == MVT::i16)
1713 case 32: return MVT::v32i1;
1714 case 64: return MVT::v64i1;
1718 if (VT.is256BitVector() || VT.is128BitVector()) {
1719 if (Subtarget->hasVLX())
1720 if (EltVT == MVT::i32 || EltVT == MVT::i64 ||
1721 EltVT == MVT::f32 || EltVT == MVT::f64)
1723 case 2: return MVT::v2i1;
1724 case 4: return MVT::v4i1;
1725 case 8: return MVT::v8i1;
1727 if (Subtarget->hasBWI() && Subtarget->hasVLX())
1728 if (EltVT == MVT::i8 || EltVT == MVT::i16)
1730 case 8: return MVT::v8i1;
1731 case 16: return MVT::v16i1;
1732 case 32: return MVT::v32i1;
1736 return VT.changeVectorElementTypeToInteger();
1739 /// getMaxByValAlign - Helper for getByValTypeAlignment to determine
1740 /// the desired ByVal argument alignment.
1741 static void getMaxByValAlign(Type *Ty, unsigned &MaxAlign) {
1744 if (VectorType *VTy = dyn_cast<VectorType>(Ty)) {
1745 if (VTy->getBitWidth() == 128)
1747 } else if (ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
1748 unsigned EltAlign = 0;
1749 getMaxByValAlign(ATy->getElementType(), EltAlign);
1750 if (EltAlign > MaxAlign)
1751 MaxAlign = EltAlign;
1752 } else if (StructType *STy = dyn_cast<StructType>(Ty)) {
1753 for (unsigned i = 0, e = STy->getNumElements(); i != e; ++i) {
1754 unsigned EltAlign = 0;
1755 getMaxByValAlign(STy->getElementType(i), EltAlign);
1756 if (EltAlign > MaxAlign)
1757 MaxAlign = EltAlign;
1764 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
1765 /// function arguments in the caller parameter area. For X86, aggregates
1766 /// that contain SSE vectors are placed at 16-byte boundaries while the rest
1767 /// are at 4-byte boundaries.
1768 unsigned X86TargetLowering::getByValTypeAlignment(Type *Ty) const {
1769 if (Subtarget->is64Bit()) {
1770 // Max of 8 and alignment of type.
1771 unsigned TyAlign = TD->getABITypeAlignment(Ty);
1778 if (Subtarget->hasSSE1())
1779 getMaxByValAlign(Ty, Align);
1783 /// getOptimalMemOpType - Returns the target specific optimal type for load
1784 /// and store operations as a result of memset, memcpy, and memmove
1785 /// lowering. If DstAlign is zero that means it's safe to destination
1786 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
1787 /// means there isn't a need to check it against alignment requirement,
1788 /// probably because the source does not need to be loaded. If 'IsMemset' is
1789 /// true, that means it's expanding a memset. If 'ZeroMemset' is true, that
1790 /// means it's a memset of zero. 'MemcpyStrSrc' indicates whether the memcpy
1791 /// source is constant so it does not need to be loaded.
1792 /// It returns EVT::Other if the type should be determined using generic
1793 /// target-independent logic.
1795 X86TargetLowering::getOptimalMemOpType(uint64_t Size,
1796 unsigned DstAlign, unsigned SrcAlign,
1797 bool IsMemset, bool ZeroMemset,
1799 MachineFunction &MF) const {
1800 const Function *F = MF.getFunction();
1801 if ((!IsMemset || ZeroMemset) &&
1802 !F->getAttributes().hasAttribute(AttributeSet::FunctionIndex,
1803 Attribute::NoImplicitFloat)) {
1805 (Subtarget->isUnalignedMemAccessFast() ||
1806 ((DstAlign == 0 || DstAlign >= 16) &&
1807 (SrcAlign == 0 || SrcAlign >= 16)))) {
1809 if (Subtarget->hasInt256())
1811 if (Subtarget->hasFp256())
1814 if (Subtarget->hasSSE2())
1816 if (Subtarget->hasSSE1())
1818 } else if (!MemcpyStrSrc && Size >= 8 &&
1819 !Subtarget->is64Bit() &&
1820 Subtarget->hasSSE2()) {
1821 // Do not use f64 to lower memcpy if source is string constant. It's
1822 // better to use i32 to avoid the loads.
1826 if (Subtarget->is64Bit() && Size >= 8)
1831 bool X86TargetLowering::isSafeMemOpType(MVT VT) const {
1833 return X86ScalarSSEf32;
1834 else if (VT == MVT::f64)
1835 return X86ScalarSSEf64;
1840 X86TargetLowering::allowsMisalignedMemoryAccesses(EVT VT,
1845 *Fast = Subtarget->isUnalignedMemAccessFast();
1849 /// getJumpTableEncoding - Return the entry encoding for a jump table in the
1850 /// current function. The returned value is a member of the
1851 /// MachineJumpTableInfo::JTEntryKind enum.
1852 unsigned X86TargetLowering::getJumpTableEncoding() const {
1853 // In GOT pic mode, each entry in the jump table is emitted as a @GOTOFF
1855 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1856 Subtarget->isPICStyleGOT())
1857 return MachineJumpTableInfo::EK_Custom32;
1859 // Otherwise, use the normal jump table encoding heuristics.
1860 return TargetLowering::getJumpTableEncoding();
1864 X86TargetLowering::LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI,
1865 const MachineBasicBlock *MBB,
1866 unsigned uid,MCContext &Ctx) const{
1867 assert(MBB->getParent()->getTarget().getRelocationModel() == Reloc::PIC_ &&
1868 Subtarget->isPICStyleGOT());
1869 // In 32-bit ELF systems, our jump table entries are formed with @GOTOFF
1871 return MCSymbolRefExpr::Create(MBB->getSymbol(),
1872 MCSymbolRefExpr::VK_GOTOFF, Ctx);
1875 /// getPICJumpTableRelocaBase - Returns relocation base for the given PIC
1877 SDValue X86TargetLowering::getPICJumpTableRelocBase(SDValue Table,
1878 SelectionDAG &DAG) const {
1879 if (!Subtarget->is64Bit())
1880 // This doesn't have SDLoc associated with it, but is not really the
1881 // same as a Register.
1882 return DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), getPointerTy());
1886 /// getPICJumpTableRelocBaseExpr - This returns the relocation base for the
1887 /// given PIC jumptable, the same as getPICJumpTableRelocBase, but as an
1889 const MCExpr *X86TargetLowering::
1890 getPICJumpTableRelocBaseExpr(const MachineFunction *MF, unsigned JTI,
1891 MCContext &Ctx) const {
1892 // X86-64 uses RIP relative addressing based on the jump table label.
1893 if (Subtarget->isPICStyleRIPRel())
1894 return TargetLowering::getPICJumpTableRelocBaseExpr(MF, JTI, Ctx);
1896 // Otherwise, the reference is relative to the PIC base.
1897 return MCSymbolRefExpr::Create(MF->getPICBaseSymbol(), Ctx);
1900 // FIXME: Why this routine is here? Move to RegInfo!
1901 std::pair<const TargetRegisterClass*, uint8_t>
1902 X86TargetLowering::findRepresentativeClass(MVT VT) const{
1903 const TargetRegisterClass *RRC = nullptr;
1905 switch (VT.SimpleTy) {
1907 return TargetLowering::findRepresentativeClass(VT);
1908 case MVT::i8: case MVT::i16: case MVT::i32: case MVT::i64:
1909 RRC = Subtarget->is64Bit() ? &X86::GR64RegClass : &X86::GR32RegClass;
1912 RRC = &X86::VR64RegClass;
1914 case MVT::f32: case MVT::f64:
1915 case MVT::v16i8: case MVT::v8i16: case MVT::v4i32: case MVT::v2i64:
1916 case MVT::v4f32: case MVT::v2f64:
1917 case MVT::v32i8: case MVT::v8i32: case MVT::v4i64: case MVT::v8f32:
1919 RRC = &X86::VR128RegClass;
1922 return std::make_pair(RRC, Cost);
1925 bool X86TargetLowering::getStackCookieLocation(unsigned &AddressSpace,
1926 unsigned &Offset) const {
1927 if (!Subtarget->isTargetLinux())
1930 if (Subtarget->is64Bit()) {
1931 // %fs:0x28, unless we're using a Kernel code model, in which case it's %gs:
1933 if (getTargetMachine().getCodeModel() == CodeModel::Kernel)
1945 bool X86TargetLowering::isNoopAddrSpaceCast(unsigned SrcAS,
1946 unsigned DestAS) const {
1947 assert(SrcAS != DestAS && "Expected different address spaces!");
1949 return SrcAS < 256 && DestAS < 256;
1952 //===----------------------------------------------------------------------===//
1953 // Return Value Calling Convention Implementation
1954 //===----------------------------------------------------------------------===//
1956 #include "X86GenCallingConv.inc"
1959 X86TargetLowering::CanLowerReturn(CallingConv::ID CallConv,
1960 MachineFunction &MF, bool isVarArg,
1961 const SmallVectorImpl<ISD::OutputArg> &Outs,
1962 LLVMContext &Context) const {
1963 SmallVector<CCValAssign, 16> RVLocs;
1964 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, Context);
1965 return CCInfo.CheckReturn(Outs, RetCC_X86);
1968 const MCPhysReg *X86TargetLowering::getScratchRegisters(CallingConv::ID) const {
1969 static const MCPhysReg ScratchRegs[] = { X86::R11, 0 };
1974 X86TargetLowering::LowerReturn(SDValue Chain,
1975 CallingConv::ID CallConv, bool isVarArg,
1976 const SmallVectorImpl<ISD::OutputArg> &Outs,
1977 const SmallVectorImpl<SDValue> &OutVals,
1978 SDLoc dl, SelectionDAG &DAG) const {
1979 MachineFunction &MF = DAG.getMachineFunction();
1980 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1982 SmallVector<CCValAssign, 16> RVLocs;
1983 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, *DAG.getContext());
1984 CCInfo.AnalyzeReturn(Outs, RetCC_X86);
1987 SmallVector<SDValue, 6> RetOps;
1988 RetOps.push_back(Chain); // Operand #0 = Chain (updated below)
1989 // Operand #1 = Bytes To Pop
1990 RetOps.push_back(DAG.getTargetConstant(FuncInfo->getBytesToPopOnReturn(),
1993 // Copy the result values into the output registers.
1994 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1995 CCValAssign &VA = RVLocs[i];
1996 assert(VA.isRegLoc() && "Can only return in registers!");
1997 SDValue ValToCopy = OutVals[i];
1998 EVT ValVT = ValToCopy.getValueType();
2000 // Promote values to the appropriate types
2001 if (VA.getLocInfo() == CCValAssign::SExt)
2002 ValToCopy = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), ValToCopy);
2003 else if (VA.getLocInfo() == CCValAssign::ZExt)
2004 ValToCopy = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), ValToCopy);
2005 else if (VA.getLocInfo() == CCValAssign::AExt)
2006 ValToCopy = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), ValToCopy);
2007 else if (VA.getLocInfo() == CCValAssign::BCvt)
2008 ValToCopy = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), ValToCopy);
2010 assert(VA.getLocInfo() != CCValAssign::FPExt &&
2011 "Unexpected FP-extend for return value.");
2013 // If this is x86-64, and we disabled SSE, we can't return FP values,
2014 // or SSE or MMX vectors.
2015 if ((ValVT == MVT::f32 || ValVT == MVT::f64 ||
2016 VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) &&
2017 (Subtarget->is64Bit() && !Subtarget->hasSSE1())) {
2018 report_fatal_error("SSE register return with SSE disabled");
2020 // Likewise we can't return F64 values with SSE1 only. gcc does so, but
2021 // llvm-gcc has never done it right and no one has noticed, so this
2022 // should be OK for now.
2023 if (ValVT == MVT::f64 &&
2024 (Subtarget->is64Bit() && !Subtarget->hasSSE2()))
2025 report_fatal_error("SSE2 register return with SSE2 disabled");
2027 // Returns in ST0/ST1 are handled specially: these are pushed as operands to
2028 // the RET instruction and handled by the FP Stackifier.
2029 if (VA.getLocReg() == X86::FP0 ||
2030 VA.getLocReg() == X86::FP1) {
2031 // If this is a copy from an xmm register to ST(0), use an FPExtend to
2032 // change the value to the FP stack register class.
2033 if (isScalarFPTypeInSSEReg(VA.getValVT()))
2034 ValToCopy = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f80, ValToCopy);
2035 RetOps.push_back(ValToCopy);
2036 // Don't emit a copytoreg.
2040 // 64-bit vector (MMX) values are returned in XMM0 / XMM1 except for v1i64
2041 // which is returned in RAX / RDX.
2042 if (Subtarget->is64Bit()) {
2043 if (ValVT == MVT::x86mmx) {
2044 if (VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) {
2045 ValToCopy = DAG.getNode(ISD::BITCAST, dl, MVT::i64, ValToCopy);
2046 ValToCopy = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
2048 // If we don't have SSE2 available, convert to v4f32 so the generated
2049 // register is legal.
2050 if (!Subtarget->hasSSE2())
2051 ValToCopy = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32,ValToCopy);
2056 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), ValToCopy, Flag);
2057 Flag = Chain.getValue(1);
2058 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
2061 // The x86-64 ABIs require that for returning structs by value we copy
2062 // the sret argument into %rax/%eax (depending on ABI) for the return.
2063 // Win32 requires us to put the sret argument to %eax as well.
2064 // We saved the argument into a virtual register in the entry block,
2065 // so now we copy the value out and into %rax/%eax.
2066 if (DAG.getMachineFunction().getFunction()->hasStructRetAttr() &&
2067 (Subtarget->is64Bit() || Subtarget->isTargetKnownWindowsMSVC())) {
2068 MachineFunction &MF = DAG.getMachineFunction();
2069 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
2070 unsigned Reg = FuncInfo->getSRetReturnReg();
2072 "SRetReturnReg should have been set in LowerFormalArguments().");
2073 SDValue Val = DAG.getCopyFromReg(Chain, dl, Reg, getPointerTy());
2076 = (Subtarget->is64Bit() && !Subtarget->isTarget64BitILP32()) ?
2077 X86::RAX : X86::EAX;
2078 Chain = DAG.getCopyToReg(Chain, dl, RetValReg, Val, Flag);
2079 Flag = Chain.getValue(1);
2081 // RAX/EAX now acts like a return value.
2082 RetOps.push_back(DAG.getRegister(RetValReg, getPointerTy()));
2085 RetOps[0] = Chain; // Update chain.
2087 // Add the flag if we have it.
2089 RetOps.push_back(Flag);
2091 return DAG.getNode(X86ISD::RET_FLAG, dl, MVT::Other, RetOps);
2094 bool X86TargetLowering::isUsedByReturnOnly(SDNode *N, SDValue &Chain) const {
2095 if (N->getNumValues() != 1)
2097 if (!N->hasNUsesOfValue(1, 0))
2100 SDValue TCChain = Chain;
2101 SDNode *Copy = *N->use_begin();
2102 if (Copy->getOpcode() == ISD::CopyToReg) {
2103 // If the copy has a glue operand, we conservatively assume it isn't safe to
2104 // perform a tail call.
2105 if (Copy->getOperand(Copy->getNumOperands()-1).getValueType() == MVT::Glue)
2107 TCChain = Copy->getOperand(0);
2108 } else if (Copy->getOpcode() != ISD::FP_EXTEND)
2111 bool HasRet = false;
2112 for (SDNode::use_iterator UI = Copy->use_begin(), UE = Copy->use_end();
2114 if (UI->getOpcode() != X86ISD::RET_FLAG)
2116 // If we are returning more than one value, we can definitely
2117 // not make a tail call see PR19530
2118 if (UI->getNumOperands() > 4)
2120 if (UI->getNumOperands() == 4 &&
2121 UI->getOperand(UI->getNumOperands()-1).getValueType() != MVT::Glue)
2134 X86TargetLowering::getTypeForExtArgOrReturn(LLVMContext &Context, EVT VT,
2135 ISD::NodeType ExtendKind) const {
2137 // TODO: Is this also valid on 32-bit?
2138 if (Subtarget->is64Bit() && VT == MVT::i1 && ExtendKind == ISD::ZERO_EXTEND)
2139 ReturnMVT = MVT::i8;
2141 ReturnMVT = MVT::i32;
2143 EVT MinVT = getRegisterType(Context, ReturnMVT);
2144 return VT.bitsLT(MinVT) ? MinVT : VT;
2147 /// LowerCallResult - Lower the result values of a call into the
2148 /// appropriate copies out of appropriate physical registers.
2151 X86TargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
2152 CallingConv::ID CallConv, bool isVarArg,
2153 const SmallVectorImpl<ISD::InputArg> &Ins,
2154 SDLoc dl, SelectionDAG &DAG,
2155 SmallVectorImpl<SDValue> &InVals) const {
2157 // Assign locations to each value returned by this call.
2158 SmallVector<CCValAssign, 16> RVLocs;
2159 bool Is64Bit = Subtarget->is64Bit();
2160 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
2162 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
2164 // Copy all of the result registers out of their specified physreg.
2165 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
2166 CCValAssign &VA = RVLocs[i];
2167 EVT CopyVT = VA.getValVT();
2169 // If this is x86-64, and we disabled SSE, we can't return FP values
2170 if ((CopyVT == MVT::f32 || CopyVT == MVT::f64) &&
2171 ((Is64Bit || Ins[i].Flags.isInReg()) && !Subtarget->hasSSE1())) {
2172 report_fatal_error("SSE register return with SSE disabled");
2175 // If we prefer to use the value in xmm registers, copy it out as f80 and
2176 // use a truncate to move it from fp stack reg to xmm reg.
2177 if ((VA.getLocReg() == X86::FP0 || VA.getLocReg() == X86::FP1) &&
2178 isScalarFPTypeInSSEReg(VA.getValVT()))
2181 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(),
2182 CopyVT, InFlag).getValue(1);
2183 SDValue Val = Chain.getValue(0);
2185 if (CopyVT != VA.getValVT())
2186 Val = DAG.getNode(ISD::FP_ROUND, dl, VA.getValVT(), Val,
2187 // This truncation won't change the value.
2188 DAG.getIntPtrConstant(1));
2190 InFlag = Chain.getValue(2);
2191 InVals.push_back(Val);
2197 //===----------------------------------------------------------------------===//
2198 // C & StdCall & Fast Calling Convention implementation
2199 //===----------------------------------------------------------------------===//
2200 // StdCall calling convention seems to be standard for many Windows' API
2201 // routines and around. It differs from C calling convention just a little:
2202 // callee should clean up the stack, not caller. Symbols should be also
2203 // decorated in some fancy way :) It doesn't support any vector arguments.
2204 // For info on fast calling convention see Fast Calling Convention (tail call)
2205 // implementation LowerX86_32FastCCCallTo.
2207 /// CallIsStructReturn - Determines whether a call uses struct return
2209 enum StructReturnType {
2214 static StructReturnType
2215 callIsStructReturn(const SmallVectorImpl<ISD::OutputArg> &Outs) {
2217 return NotStructReturn;
2219 const ISD::ArgFlagsTy &Flags = Outs[0].Flags;
2220 if (!Flags.isSRet())
2221 return NotStructReturn;
2222 if (Flags.isInReg())
2223 return RegStructReturn;
2224 return StackStructReturn;
2227 /// ArgsAreStructReturn - Determines whether a function uses struct
2228 /// return semantics.
2229 static StructReturnType
2230 argsAreStructReturn(const SmallVectorImpl<ISD::InputArg> &Ins) {
2232 return NotStructReturn;
2234 const ISD::ArgFlagsTy &Flags = Ins[0].Flags;
2235 if (!Flags.isSRet())
2236 return NotStructReturn;
2237 if (Flags.isInReg())
2238 return RegStructReturn;
2239 return StackStructReturn;
2242 /// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified
2243 /// by "Src" to address "Dst" with size and alignment information specified by
2244 /// the specific parameter attribute. The copy will be passed as a byval
2245 /// function parameter.
2247 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
2248 ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
2250 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32);
2252 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
2253 /*isVolatile*/false, /*AlwaysInline=*/true,
2254 MachinePointerInfo(), MachinePointerInfo());
2257 /// IsTailCallConvention - Return true if the calling convention is one that
2258 /// supports tail call optimization.
2259 static bool IsTailCallConvention(CallingConv::ID CC) {
2260 return (CC == CallingConv::Fast || CC == CallingConv::GHC ||
2261 CC == CallingConv::HiPE);
2264 /// \brief Return true if the calling convention is a C calling convention.
2265 static bool IsCCallConvention(CallingConv::ID CC) {
2266 return (CC == CallingConv::C || CC == CallingConv::X86_64_Win64 ||
2267 CC == CallingConv::X86_64_SysV);
2270 bool X86TargetLowering::mayBeEmittedAsTailCall(CallInst *CI) const {
2271 if (!CI->isTailCall() || getTargetMachine().Options.DisableTailCalls)
2275 CallingConv::ID CalleeCC = CS.getCallingConv();
2276 if (!IsTailCallConvention(CalleeCC) && !IsCCallConvention(CalleeCC))
2282 /// FuncIsMadeTailCallSafe - Return true if the function is being made into
2283 /// a tailcall target by changing its ABI.
2284 static bool FuncIsMadeTailCallSafe(CallingConv::ID CC,
2285 bool GuaranteedTailCallOpt) {
2286 return GuaranteedTailCallOpt && IsTailCallConvention(CC);
2290 X86TargetLowering::LowerMemArgument(SDValue Chain,
2291 CallingConv::ID CallConv,
2292 const SmallVectorImpl<ISD::InputArg> &Ins,
2293 SDLoc dl, SelectionDAG &DAG,
2294 const CCValAssign &VA,
2295 MachineFrameInfo *MFI,
2297 // Create the nodes corresponding to a load from this parameter slot.
2298 ISD::ArgFlagsTy Flags = Ins[i].Flags;
2299 bool AlwaysUseMutable = FuncIsMadeTailCallSafe(
2300 CallConv, DAG.getTarget().Options.GuaranteedTailCallOpt);
2301 bool isImmutable = !AlwaysUseMutable && !Flags.isByVal();
2304 // If value is passed by pointer we have address passed instead of the value
2306 if (VA.getLocInfo() == CCValAssign::Indirect)
2307 ValVT = VA.getLocVT();
2309 ValVT = VA.getValVT();
2311 // FIXME: For now, all byval parameter objects are marked mutable. This can be
2312 // changed with more analysis.
2313 // In case of tail call optimization mark all arguments mutable. Since they
2314 // could be overwritten by lowering of arguments in case of a tail call.
2315 if (Flags.isByVal()) {
2316 unsigned Bytes = Flags.getByValSize();
2317 if (Bytes == 0) Bytes = 1; // Don't create zero-sized stack objects.
2318 int FI = MFI->CreateFixedObject(Bytes, VA.getLocMemOffset(), isImmutable);
2319 return DAG.getFrameIndex(FI, getPointerTy());
2321 int FI = MFI->CreateFixedObject(ValVT.getSizeInBits()/8,
2322 VA.getLocMemOffset(), isImmutable);
2323 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
2324 return DAG.getLoad(ValVT, dl, Chain, FIN,
2325 MachinePointerInfo::getFixedStack(FI),
2326 false, false, false, 0);
2330 // FIXME: Get this from tablegen.
2331 static ArrayRef<MCPhysReg> get64BitArgumentGPRs(CallingConv::ID CallConv,
2332 const X86Subtarget *Subtarget) {
2333 assert(Subtarget->is64Bit());
2335 if (Subtarget->isCallingConvWin64(CallConv)) {
2336 static const MCPhysReg GPR64ArgRegsWin64[] = {
2337 X86::RCX, X86::RDX, X86::R8, X86::R9
2339 return makeArrayRef(std::begin(GPR64ArgRegsWin64), std::end(GPR64ArgRegsWin64));
2342 static const MCPhysReg GPR64ArgRegs64Bit[] = {
2343 X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9
2345 return makeArrayRef(std::begin(GPR64ArgRegs64Bit), std::end(GPR64ArgRegs64Bit));
2348 // FIXME: Get this from tablegen.
2349 static ArrayRef<MCPhysReg> get64BitArgumentXMMs(MachineFunction &MF,
2350 CallingConv::ID CallConv,
2351 const X86Subtarget *Subtarget) {
2352 assert(Subtarget->is64Bit());
2353 if (Subtarget->isCallingConvWin64(CallConv)) {
2354 // The XMM registers which might contain var arg parameters are shadowed
2355 // in their paired GPR. So we only need to save the GPR to their home
2357 // TODO: __vectorcall will change this.
2361 const Function *Fn = MF.getFunction();
2362 bool NoImplicitFloatOps = Fn->getAttributes().
2363 hasAttribute(AttributeSet::FunctionIndex, Attribute::NoImplicitFloat);
2364 assert(!(MF.getTarget().Options.UseSoftFloat && NoImplicitFloatOps) &&
2365 "SSE register cannot be used when SSE is disabled!");
2366 if (MF.getTarget().Options.UseSoftFloat || NoImplicitFloatOps ||
2367 !Subtarget->hasSSE1())
2368 // Kernel mode asks for SSE to be disabled, so there are no XMM argument
2372 static const MCPhysReg XMMArgRegs64Bit[] = {
2373 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
2374 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
2376 return makeArrayRef(std::begin(XMMArgRegs64Bit), std::end(XMMArgRegs64Bit));
2380 X86TargetLowering::LowerFormalArguments(SDValue Chain,
2381 CallingConv::ID CallConv,
2383 const SmallVectorImpl<ISD::InputArg> &Ins,
2386 SmallVectorImpl<SDValue> &InVals)
2388 MachineFunction &MF = DAG.getMachineFunction();
2389 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
2391 const Function* Fn = MF.getFunction();
2392 if (Fn->hasExternalLinkage() &&
2393 Subtarget->isTargetCygMing() &&
2394 Fn->getName() == "main")
2395 FuncInfo->setForceFramePointer(true);
2397 MachineFrameInfo *MFI = MF.getFrameInfo();
2398 bool Is64Bit = Subtarget->is64Bit();
2399 bool IsWin64 = Subtarget->isCallingConvWin64(CallConv);
2401 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
2402 "Var args not supported with calling convention fastcc, ghc or hipe");
2404 // Assign locations to all of the incoming arguments.
2405 SmallVector<CCValAssign, 16> ArgLocs;
2406 CCState CCInfo(CallConv, isVarArg, MF, ArgLocs, *DAG.getContext());
2408 // Allocate shadow area for Win64
2410 CCInfo.AllocateStack(32, 8);
2412 CCInfo.AnalyzeFormalArguments(Ins, CC_X86);
2414 unsigned LastVal = ~0U;
2416 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2417 CCValAssign &VA = ArgLocs[i];
2418 // TODO: If an arg is passed in two places (e.g. reg and stack), skip later
2420 assert(VA.getValNo() != LastVal &&
2421 "Don't support value assigned to multiple locs yet");
2423 LastVal = VA.getValNo();
2425 if (VA.isRegLoc()) {
2426 EVT RegVT = VA.getLocVT();
2427 const TargetRegisterClass *RC;
2428 if (RegVT == MVT::i32)
2429 RC = &X86::GR32RegClass;
2430 else if (Is64Bit && RegVT == MVT::i64)
2431 RC = &X86::GR64RegClass;
2432 else if (RegVT == MVT::f32)
2433 RC = &X86::FR32RegClass;
2434 else if (RegVT == MVT::f64)
2435 RC = &X86::FR64RegClass;
2436 else if (RegVT.is512BitVector())
2437 RC = &X86::VR512RegClass;
2438 else if (RegVT.is256BitVector())
2439 RC = &X86::VR256RegClass;
2440 else if (RegVT.is128BitVector())
2441 RC = &X86::VR128RegClass;
2442 else if (RegVT == MVT::x86mmx)
2443 RC = &X86::VR64RegClass;
2444 else if (RegVT == MVT::i1)
2445 RC = &X86::VK1RegClass;
2446 else if (RegVT == MVT::v8i1)
2447 RC = &X86::VK8RegClass;
2448 else if (RegVT == MVT::v16i1)
2449 RC = &X86::VK16RegClass;
2450 else if (RegVT == MVT::v32i1)
2451 RC = &X86::VK32RegClass;
2452 else if (RegVT == MVT::v64i1)
2453 RC = &X86::VK64RegClass;
2455 llvm_unreachable("Unknown argument type!");
2457 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
2458 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
2460 // If this is an 8 or 16-bit value, it is really passed promoted to 32
2461 // bits. Insert an assert[sz]ext to capture this, then truncate to the
2463 if (VA.getLocInfo() == CCValAssign::SExt)
2464 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
2465 DAG.getValueType(VA.getValVT()));
2466 else if (VA.getLocInfo() == CCValAssign::ZExt)
2467 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
2468 DAG.getValueType(VA.getValVT()));
2469 else if (VA.getLocInfo() == CCValAssign::BCvt)
2470 ArgValue = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), ArgValue);
2472 if (VA.isExtInLoc()) {
2473 // Handle MMX values passed in XMM regs.
2474 if (RegVT.isVector())
2475 ArgValue = DAG.getNode(X86ISD::MOVDQ2Q, dl, VA.getValVT(), ArgValue);
2477 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
2480 assert(VA.isMemLoc());
2481 ArgValue = LowerMemArgument(Chain, CallConv, Ins, dl, DAG, VA, MFI, i);
2484 // If value is passed via pointer - do a load.
2485 if (VA.getLocInfo() == CCValAssign::Indirect)
2486 ArgValue = DAG.getLoad(VA.getValVT(), dl, Chain, ArgValue,
2487 MachinePointerInfo(), false, false, false, 0);
2489 InVals.push_back(ArgValue);
2492 if (Subtarget->is64Bit() || Subtarget->isTargetKnownWindowsMSVC()) {
2493 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2494 // The x86-64 ABIs require that for returning structs by value we copy
2495 // the sret argument into %rax/%eax (depending on ABI) for the return.
2496 // Win32 requires us to put the sret argument to %eax as well.
2497 // Save the argument into a virtual register so that we can access it
2498 // from the return points.
2499 if (Ins[i].Flags.isSRet()) {
2500 unsigned Reg = FuncInfo->getSRetReturnReg();
2502 MVT PtrTy = getPointerTy();
2503 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(PtrTy));
2504 FuncInfo->setSRetReturnReg(Reg);
2506 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, InVals[i]);
2507 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain);
2513 unsigned StackSize = CCInfo.getNextStackOffset();
2514 // Align stack specially for tail calls.
2515 if (FuncIsMadeTailCallSafe(CallConv,
2516 MF.getTarget().Options.GuaranteedTailCallOpt))
2517 StackSize = GetAlignedArgumentStackSize(StackSize, DAG);
2519 // If the function takes variable number of arguments, make a frame index for
2520 // the start of the first vararg value... for expansion of llvm.va_start. We
2521 // can skip this if there are no va_start calls.
2522 if (MFI->hasVAStart() &&
2523 (Is64Bit || (CallConv != CallingConv::X86_FastCall &&
2524 CallConv != CallingConv::X86_ThisCall))) {
2525 FuncInfo->setVarArgsFrameIndex(
2526 MFI->CreateFixedObject(1, StackSize, true));
2529 // 64-bit calling conventions support varargs and register parameters, so we
2530 // have to do extra work to spill them in the prologue or forward them to
2532 if (Is64Bit && isVarArg &&
2533 (MFI->hasVAStart() || MFI->hasMustTailInVarArgFunc())) {
2534 // Find the first unallocated argument registers.
2535 ArrayRef<MCPhysReg> ArgGPRs = get64BitArgumentGPRs(CallConv, Subtarget);
2536 ArrayRef<MCPhysReg> ArgXMMs = get64BitArgumentXMMs(MF, CallConv, Subtarget);
2537 unsigned NumIntRegs =
2538 CCInfo.getFirstUnallocated(ArgGPRs.data(), ArgGPRs.size());
2539 unsigned NumXMMRegs =
2540 CCInfo.getFirstUnallocated(ArgXMMs.data(), ArgXMMs.size());
2541 assert(!(NumXMMRegs && !Subtarget->hasSSE1()) &&
2542 "SSE register cannot be used when SSE is disabled!");
2544 // Gather all the live in physical registers.
2545 SmallVector<SDValue, 6> LiveGPRs;
2546 SmallVector<SDValue, 8> LiveXMMRegs;
2548 for (MCPhysReg Reg : ArgGPRs.slice(NumIntRegs)) {
2549 unsigned GPR = MF.addLiveIn(Reg, &X86::GR64RegClass);
2551 DAG.getCopyFromReg(Chain, dl, GPR, MVT::i64));
2553 if (!ArgXMMs.empty()) {
2554 unsigned AL = MF.addLiveIn(X86::AL, &X86::GR8RegClass);
2555 ALVal = DAG.getCopyFromReg(Chain, dl, AL, MVT::i8);
2556 for (MCPhysReg Reg : ArgXMMs.slice(NumXMMRegs)) {
2557 unsigned XMMReg = MF.addLiveIn(Reg, &X86::VR128RegClass);
2558 LiveXMMRegs.push_back(
2559 DAG.getCopyFromReg(Chain, dl, XMMReg, MVT::v4f32));
2563 // Store them to the va_list returned by va_start.
2564 if (MFI->hasVAStart()) {
2566 const TargetFrameLowering &TFI = *MF.getSubtarget().getFrameLowering();
2567 // Get to the caller-allocated home save location. Add 8 to account
2568 // for the return address.
2569 int HomeOffset = TFI.getOffsetOfLocalArea() + 8;
2570 FuncInfo->setRegSaveFrameIndex(
2571 MFI->CreateFixedObject(1, NumIntRegs * 8 + HomeOffset, false));
2572 // Fixup to set vararg frame on shadow area (4 x i64).
2574 FuncInfo->setVarArgsFrameIndex(FuncInfo->getRegSaveFrameIndex());
2576 // For X86-64, if there are vararg parameters that are passed via
2577 // registers, then we must store them to their spots on the stack so
2578 // they may be loaded by deferencing the result of va_next.
2579 FuncInfo->setVarArgsGPOffset(NumIntRegs * 8);
2580 FuncInfo->setVarArgsFPOffset(ArgGPRs.size() * 8 + NumXMMRegs * 16);
2581 FuncInfo->setRegSaveFrameIndex(MFI->CreateStackObject(
2582 ArgGPRs.size() * 8 + ArgXMMs.size() * 16, 16, false));
2585 // Store the integer parameter registers.
2586 SmallVector<SDValue, 8> MemOps;
2587 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
2589 unsigned Offset = FuncInfo->getVarArgsGPOffset();
2590 for (SDValue Val : LiveGPRs) {
2591 SDValue FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), RSFIN,
2592 DAG.getIntPtrConstant(Offset));
2594 DAG.getStore(Val.getValue(1), dl, Val, FIN,
2595 MachinePointerInfo::getFixedStack(
2596 FuncInfo->getRegSaveFrameIndex(), Offset),
2598 MemOps.push_back(Store);
2602 if (!ArgXMMs.empty() && NumXMMRegs != ArgXMMs.size()) {
2603 // Now store the XMM (fp + vector) parameter registers.
2604 SmallVector<SDValue, 12> SaveXMMOps;
2605 SaveXMMOps.push_back(Chain);
2606 SaveXMMOps.push_back(ALVal);
2607 SaveXMMOps.push_back(DAG.getIntPtrConstant(
2608 FuncInfo->getRegSaveFrameIndex()));
2609 SaveXMMOps.push_back(DAG.getIntPtrConstant(
2610 FuncInfo->getVarArgsFPOffset()));
2611 SaveXMMOps.insert(SaveXMMOps.end(), LiveXMMRegs.begin(),
2613 MemOps.push_back(DAG.getNode(X86ISD::VASTART_SAVE_XMM_REGS, dl,
2614 MVT::Other, SaveXMMOps));
2617 if (!MemOps.empty())
2618 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps);
2620 // Add all GPRs, al, and XMMs to the list of forwards. We will add then
2621 // to the liveout set on a musttail call.
2622 assert(MFI->hasMustTailInVarArgFunc());
2623 auto &Forwards = FuncInfo->getForwardedMustTailRegParms();
2624 typedef X86MachineFunctionInfo::Forward Forward;
2626 for (unsigned I = 0, E = LiveGPRs.size(); I != E; ++I) {
2628 MF.getRegInfo().createVirtualRegister(&X86::GR64RegClass);
2629 Chain = DAG.getCopyToReg(Chain, dl, VReg, LiveGPRs[I]);
2630 Forwards.push_back(Forward(VReg, ArgGPRs[NumIntRegs + I], MVT::i64));
2633 if (!ArgXMMs.empty()) {
2635 MF.getRegInfo().createVirtualRegister(&X86::GR8RegClass);
2636 Chain = DAG.getCopyToReg(Chain, dl, ALVReg, ALVal);
2637 Forwards.push_back(Forward(ALVReg, X86::AL, MVT::i8));
2639 for (unsigned I = 0, E = LiveXMMRegs.size(); I != E; ++I) {
2641 MF.getRegInfo().createVirtualRegister(&X86::VR128RegClass);
2642 Chain = DAG.getCopyToReg(Chain, dl, VReg, LiveXMMRegs[I]);
2644 Forward(VReg, ArgXMMs[NumXMMRegs + I], MVT::v4f32));
2650 // Some CCs need callee pop.
2651 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg,
2652 MF.getTarget().Options.GuaranteedTailCallOpt)) {
2653 FuncInfo->setBytesToPopOnReturn(StackSize); // Callee pops everything.
2655 FuncInfo->setBytesToPopOnReturn(0); // Callee pops nothing.
2656 // If this is an sret function, the return should pop the hidden pointer.
2657 if (!Is64Bit && !IsTailCallConvention(CallConv) &&
2658 !Subtarget->getTargetTriple().isOSMSVCRT() &&
2659 argsAreStructReturn(Ins) == StackStructReturn)
2660 FuncInfo->setBytesToPopOnReturn(4);
2664 // RegSaveFrameIndex is X86-64 only.
2665 FuncInfo->setRegSaveFrameIndex(0xAAAAAAA);
2666 if (CallConv == CallingConv::X86_FastCall ||
2667 CallConv == CallingConv::X86_ThisCall)
2668 // fastcc functions can't have varargs.
2669 FuncInfo->setVarArgsFrameIndex(0xAAAAAAA);
2672 FuncInfo->setArgumentStackSize(StackSize);
2678 X86TargetLowering::LowerMemOpCallTo(SDValue Chain,
2679 SDValue StackPtr, SDValue Arg,
2680 SDLoc dl, SelectionDAG &DAG,
2681 const CCValAssign &VA,
2682 ISD::ArgFlagsTy Flags) const {
2683 unsigned LocMemOffset = VA.getLocMemOffset();
2684 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
2685 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
2686 if (Flags.isByVal())
2687 return CreateCopyOfByValArgument(Arg, PtrOff, Chain, Flags, DAG, dl);
2689 return DAG.getStore(Chain, dl, Arg, PtrOff,
2690 MachinePointerInfo::getStack(LocMemOffset),
2694 /// EmitTailCallLoadRetAddr - Emit a load of return address if tail call
2695 /// optimization is performed and it is required.
2697 X86TargetLowering::EmitTailCallLoadRetAddr(SelectionDAG &DAG,
2698 SDValue &OutRetAddr, SDValue Chain,
2699 bool IsTailCall, bool Is64Bit,
2700 int FPDiff, SDLoc dl) const {
2701 // Adjust the Return address stack slot.
2702 EVT VT = getPointerTy();
2703 OutRetAddr = getReturnAddressFrameIndex(DAG);
2705 // Load the "old" Return address.
2706 OutRetAddr = DAG.getLoad(VT, dl, Chain, OutRetAddr, MachinePointerInfo(),
2707 false, false, false, 0);
2708 return SDValue(OutRetAddr.getNode(), 1);
2711 /// EmitTailCallStoreRetAddr - Emit a store of the return address if tail call
2712 /// optimization is performed and it is required (FPDiff!=0).
2713 static SDValue EmitTailCallStoreRetAddr(SelectionDAG &DAG, MachineFunction &MF,
2714 SDValue Chain, SDValue RetAddrFrIdx,
2715 EVT PtrVT, unsigned SlotSize,
2716 int FPDiff, SDLoc dl) {
2717 // Store the return address to the appropriate stack slot.
2718 if (!FPDiff) return Chain;
2719 // Calculate the new stack slot for the return address.
2720 int NewReturnAddrFI =
2721 MF.getFrameInfo()->CreateFixedObject(SlotSize, (int64_t)FPDiff - SlotSize,
2723 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewReturnAddrFI, PtrVT);
2724 Chain = DAG.getStore(Chain, dl, RetAddrFrIdx, NewRetAddrFrIdx,
2725 MachinePointerInfo::getFixedStack(NewReturnAddrFI),
2731 X86TargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
2732 SmallVectorImpl<SDValue> &InVals) const {
2733 SelectionDAG &DAG = CLI.DAG;
2735 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
2736 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
2737 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
2738 SDValue Chain = CLI.Chain;
2739 SDValue Callee = CLI.Callee;
2740 CallingConv::ID CallConv = CLI.CallConv;
2741 bool &isTailCall = CLI.IsTailCall;
2742 bool isVarArg = CLI.IsVarArg;
2744 MachineFunction &MF = DAG.getMachineFunction();
2745 bool Is64Bit = Subtarget->is64Bit();
2746 bool IsWin64 = Subtarget->isCallingConvWin64(CallConv);
2747 StructReturnType SR = callIsStructReturn(Outs);
2748 bool IsSibcall = false;
2749 X86MachineFunctionInfo *X86Info = MF.getInfo<X86MachineFunctionInfo>();
2751 if (MF.getTarget().Options.DisableTailCalls)
2754 bool IsMustTail = CLI.CS && CLI.CS->isMustTailCall();
2756 // Force this to be a tail call. The verifier rules are enough to ensure
2757 // that we can lower this successfully without moving the return address
2760 } else if (isTailCall) {
2761 // Check if it's really possible to do a tail call.
2762 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv,
2763 isVarArg, SR != NotStructReturn,
2764 MF.getFunction()->hasStructRetAttr(), CLI.RetTy,
2765 Outs, OutVals, Ins, DAG);
2767 // Sibcalls are automatically detected tailcalls which do not require
2769 if (!MF.getTarget().Options.GuaranteedTailCallOpt && isTailCall)
2776 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
2777 "Var args not supported with calling convention fastcc, ghc or hipe");
2779 // Analyze operands of the call, assigning locations to each operand.
2780 SmallVector<CCValAssign, 16> ArgLocs;
2781 CCState CCInfo(CallConv, isVarArg, MF, ArgLocs, *DAG.getContext());
2783 // Allocate shadow area for Win64
2785 CCInfo.AllocateStack(32, 8);
2787 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
2789 // Get a count of how many bytes are to be pushed on the stack.
2790 unsigned NumBytes = CCInfo.getNextStackOffset();
2792 // This is a sibcall. The memory operands are available in caller's
2793 // own caller's stack.
2795 else if (MF.getTarget().Options.GuaranteedTailCallOpt &&
2796 IsTailCallConvention(CallConv))
2797 NumBytes = GetAlignedArgumentStackSize(NumBytes, DAG);
2800 if (isTailCall && !IsSibcall && !IsMustTail) {
2801 // Lower arguments at fp - stackoffset + fpdiff.
2802 unsigned NumBytesCallerPushed = X86Info->getBytesToPopOnReturn();
2804 FPDiff = NumBytesCallerPushed - NumBytes;
2806 // Set the delta of movement of the returnaddr stackslot.
2807 // But only set if delta is greater than previous delta.
2808 if (FPDiff < X86Info->getTCReturnAddrDelta())
2809 X86Info->setTCReturnAddrDelta(FPDiff);
2812 unsigned NumBytesToPush = NumBytes;
2813 unsigned NumBytesToPop = NumBytes;
2815 // If we have an inalloca argument, all stack space has already been allocated
2816 // for us and be right at the top of the stack. We don't support multiple
2817 // arguments passed in memory when using inalloca.
2818 if (!Outs.empty() && Outs.back().Flags.isInAlloca()) {
2820 if (!ArgLocs.back().isMemLoc())
2821 report_fatal_error("cannot use inalloca attribute on a register "
2823 if (ArgLocs.back().getLocMemOffset() != 0)
2824 report_fatal_error("any parameter with the inalloca attribute must be "
2825 "the only memory argument");
2829 Chain = DAG.getCALLSEQ_START(
2830 Chain, DAG.getIntPtrConstant(NumBytesToPush, true), dl);
2832 SDValue RetAddrFrIdx;
2833 // Load return address for tail calls.
2834 if (isTailCall && FPDiff)
2835 Chain = EmitTailCallLoadRetAddr(DAG, RetAddrFrIdx, Chain, isTailCall,
2836 Is64Bit, FPDiff, dl);
2838 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
2839 SmallVector<SDValue, 8> MemOpChains;
2842 // Walk the register/memloc assignments, inserting copies/loads. In the case
2843 // of tail call optimization arguments are handle later.
2844 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
2845 DAG.getSubtarget().getRegisterInfo());
2846 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2847 // Skip inalloca arguments, they have already been written.
2848 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2849 if (Flags.isInAlloca())
2852 CCValAssign &VA = ArgLocs[i];
2853 EVT RegVT = VA.getLocVT();
2854 SDValue Arg = OutVals[i];
2855 bool isByVal = Flags.isByVal();
2857 // Promote the value if needed.
2858 switch (VA.getLocInfo()) {
2859 default: llvm_unreachable("Unknown loc info!");
2860 case CCValAssign::Full: break;
2861 case CCValAssign::SExt:
2862 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, RegVT, Arg);
2864 case CCValAssign::ZExt:
2865 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, RegVT, Arg);
2867 case CCValAssign::AExt:
2868 if (RegVT.is128BitVector()) {
2869 // Special case: passing MMX values in XMM registers.
2870 Arg = DAG.getNode(ISD::BITCAST, dl, MVT::i64, Arg);
2871 Arg = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, Arg);
2872 Arg = getMOVL(DAG, dl, MVT::v2i64, DAG.getUNDEF(MVT::v2i64), Arg);
2874 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, RegVT, Arg);
2876 case CCValAssign::BCvt:
2877 Arg = DAG.getNode(ISD::BITCAST, dl, RegVT, Arg);
2879 case CCValAssign::Indirect: {
2880 // Store the argument.
2881 SDValue SpillSlot = DAG.CreateStackTemporary(VA.getValVT());
2882 int FI = cast<FrameIndexSDNode>(SpillSlot)->getIndex();
2883 Chain = DAG.getStore(Chain, dl, Arg, SpillSlot,
2884 MachinePointerInfo::getFixedStack(FI),
2891 if (VA.isRegLoc()) {
2892 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
2893 if (isVarArg && IsWin64) {
2894 // Win64 ABI requires argument XMM reg to be copied to the corresponding
2895 // shadow reg if callee is a varargs function.
2896 unsigned ShadowReg = 0;
2897 switch (VA.getLocReg()) {
2898 case X86::XMM0: ShadowReg = X86::RCX; break;
2899 case X86::XMM1: ShadowReg = X86::RDX; break;
2900 case X86::XMM2: ShadowReg = X86::R8; break;
2901 case X86::XMM3: ShadowReg = X86::R9; break;
2904 RegsToPass.push_back(std::make_pair(ShadowReg, Arg));
2906 } else if (!IsSibcall && (!isTailCall || isByVal)) {
2907 assert(VA.isMemLoc());
2908 if (!StackPtr.getNode())
2909 StackPtr = DAG.getCopyFromReg(Chain, dl, RegInfo->getStackRegister(),
2911 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Arg,
2912 dl, DAG, VA, Flags));
2916 if (!MemOpChains.empty())
2917 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains);
2919 if (Subtarget->isPICStyleGOT()) {
2920 // ELF / PIC requires GOT in the EBX register before function calls via PLT
2923 RegsToPass.push_back(std::make_pair(unsigned(X86::EBX),
2924 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), getPointerTy())));
2926 // If we are tail calling and generating PIC/GOT style code load the
2927 // address of the callee into ECX. The value in ecx is used as target of
2928 // the tail jump. This is done to circumvent the ebx/callee-saved problem
2929 // for tail calls on PIC/GOT architectures. Normally we would just put the
2930 // address of GOT into ebx and then call target@PLT. But for tail calls
2931 // ebx would be restored (since ebx is callee saved) before jumping to the
2934 // Note: The actual moving to ECX is done further down.
2935 GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee);
2936 if (G && !G->getGlobal()->hasHiddenVisibility() &&
2937 !G->getGlobal()->hasProtectedVisibility())
2938 Callee = LowerGlobalAddress(Callee, DAG);
2939 else if (isa<ExternalSymbolSDNode>(Callee))
2940 Callee = LowerExternalSymbol(Callee, DAG);
2944 if (Is64Bit && isVarArg && !IsWin64 && !IsMustTail) {
2945 // From AMD64 ABI document:
2946 // For calls that may call functions that use varargs or stdargs
2947 // (prototype-less calls or calls to functions containing ellipsis (...) in
2948 // the declaration) %al is used as hidden argument to specify the number
2949 // of SSE registers used. The contents of %al do not need to match exactly
2950 // the number of registers, but must be an ubound on the number of SSE
2951 // registers used and is in the range 0 - 8 inclusive.
2953 // Count the number of XMM registers allocated.
2954 static const MCPhysReg XMMArgRegs[] = {
2955 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
2956 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
2958 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs, 8);
2959 assert((Subtarget->hasSSE1() || !NumXMMRegs)
2960 && "SSE registers cannot be used when SSE is disabled");
2962 RegsToPass.push_back(std::make_pair(unsigned(X86::AL),
2963 DAG.getConstant(NumXMMRegs, MVT::i8)));
2966 if (Is64Bit && isVarArg && IsMustTail) {
2967 const auto &Forwards = X86Info->getForwardedMustTailRegParms();
2968 for (const auto &F : Forwards) {
2969 SDValue Val = DAG.getCopyFromReg(Chain, dl, F.VReg, F.VT);
2970 RegsToPass.push_back(std::make_pair(unsigned(F.PReg), Val));
2974 // For tail calls lower the arguments to the 'real' stack slots. Sibcalls
2975 // don't need this because the eligibility check rejects calls that require
2976 // shuffling arguments passed in memory.
2977 if (!IsSibcall && isTailCall) {
2978 // Force all the incoming stack arguments to be loaded from the stack
2979 // before any new outgoing arguments are stored to the stack, because the
2980 // outgoing stack slots may alias the incoming argument stack slots, and
2981 // the alias isn't otherwise explicit. This is slightly more conservative
2982 // than necessary, because it means that each store effectively depends
2983 // on every argument instead of just those arguments it would clobber.
2984 SDValue ArgChain = DAG.getStackArgumentTokenFactor(Chain);
2986 SmallVector<SDValue, 8> MemOpChains2;
2989 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2990 CCValAssign &VA = ArgLocs[i];
2993 assert(VA.isMemLoc());
2994 SDValue Arg = OutVals[i];
2995 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2996 // Skip inalloca arguments. They don't require any work.
2997 if (Flags.isInAlloca())
2999 // Create frame index.
3000 int32_t Offset = VA.getLocMemOffset()+FPDiff;
3001 uint32_t OpSize = (VA.getLocVT().getSizeInBits()+7)/8;
3002 FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true);
3003 FIN = DAG.getFrameIndex(FI, getPointerTy());
3005 if (Flags.isByVal()) {
3006 // Copy relative to framepointer.
3007 SDValue Source = DAG.getIntPtrConstant(VA.getLocMemOffset());
3008 if (!StackPtr.getNode())
3009 StackPtr = DAG.getCopyFromReg(Chain, dl,
3010 RegInfo->getStackRegister(),
3012 Source = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, Source);
3014 MemOpChains2.push_back(CreateCopyOfByValArgument(Source, FIN,
3018 // Store relative to framepointer.
3019 MemOpChains2.push_back(
3020 DAG.getStore(ArgChain, dl, Arg, FIN,
3021 MachinePointerInfo::getFixedStack(FI),
3026 if (!MemOpChains2.empty())
3027 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains2);
3029 // Store the return address to the appropriate stack slot.
3030 Chain = EmitTailCallStoreRetAddr(DAG, MF, Chain, RetAddrFrIdx,
3031 getPointerTy(), RegInfo->getSlotSize(),
3035 // Build a sequence of copy-to-reg nodes chained together with token chain
3036 // and flag operands which copy the outgoing args into registers.
3038 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
3039 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
3040 RegsToPass[i].second, InFlag);
3041 InFlag = Chain.getValue(1);
3044 if (DAG.getTarget().getCodeModel() == CodeModel::Large) {
3045 assert(Is64Bit && "Large code model is only legal in 64-bit mode.");
3046 // In the 64-bit large code model, we have to make all calls
3047 // through a register, since the call instruction's 32-bit
3048 // pc-relative offset may not be large enough to hold the whole
3050 } else if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
3051 // If the callee is a GlobalAddress node (quite common, every direct call
3052 // is) turn it into a TargetGlobalAddress node so that legalize doesn't hack
3055 // We should use extra load for direct calls to dllimported functions in
3057 const GlobalValue *GV = G->getGlobal();
3058 if (!GV->hasDLLImportStorageClass()) {
3059 unsigned char OpFlags = 0;
3060 bool ExtraLoad = false;
3061 unsigned WrapperKind = ISD::DELETED_NODE;
3063 // On ELF targets, in both X86-64 and X86-32 mode, direct calls to
3064 // external symbols most go through the PLT in PIC mode. If the symbol
3065 // has hidden or protected visibility, or if it is static or local, then
3066 // we don't need to use the PLT - we can directly call it.
3067 if (Subtarget->isTargetELF() &&
3068 DAG.getTarget().getRelocationModel() == Reloc::PIC_ &&
3069 GV->hasDefaultVisibility() && !GV->hasLocalLinkage()) {
3070 OpFlags = X86II::MO_PLT;
3071 } else if (Subtarget->isPICStyleStubAny() &&
3072 (GV->isDeclaration() || GV->isWeakForLinker()) &&
3073 (!Subtarget->getTargetTriple().isMacOSX() ||
3074 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
3075 // PC-relative references to external symbols should go through $stub,
3076 // unless we're building with the leopard linker or later, which
3077 // automatically synthesizes these stubs.
3078 OpFlags = X86II::MO_DARWIN_STUB;
3079 } else if (Subtarget->isPICStyleRIPRel() &&
3080 isa<Function>(GV) &&
3081 cast<Function>(GV)->getAttributes().
3082 hasAttribute(AttributeSet::FunctionIndex,
3083 Attribute::NonLazyBind)) {
3084 // If the function is marked as non-lazy, generate an indirect call
3085 // which loads from the GOT directly. This avoids runtime overhead
3086 // at the cost of eager binding (and one extra byte of encoding).
3087 OpFlags = X86II::MO_GOTPCREL;
3088 WrapperKind = X86ISD::WrapperRIP;
3092 Callee = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(),
3093 G->getOffset(), OpFlags);
3095 // Add a wrapper if needed.
3096 if (WrapperKind != ISD::DELETED_NODE)
3097 Callee = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Callee);
3098 // Add extra indirection if needed.
3100 Callee = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Callee,
3101 MachinePointerInfo::getGOT(),
3102 false, false, false, 0);
3104 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
3105 unsigned char OpFlags = 0;
3107 // On ELF targets, in either X86-64 or X86-32 mode, direct calls to
3108 // external symbols should go through the PLT.
3109 if (Subtarget->isTargetELF() &&
3110 DAG.getTarget().getRelocationModel() == Reloc::PIC_) {
3111 OpFlags = X86II::MO_PLT;
3112 } else if (Subtarget->isPICStyleStubAny() &&
3113 (!Subtarget->getTargetTriple().isMacOSX() ||
3114 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
3115 // PC-relative references to external symbols should go through $stub,
3116 // unless we're building with the leopard linker or later, which
3117 // automatically synthesizes these stubs.
3118 OpFlags = X86II::MO_DARWIN_STUB;
3121 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy(),
3123 } else if (Subtarget->isTarget64BitILP32() && Callee->getValueType(0) == MVT::i32) {
3124 // Zero-extend the 32-bit Callee address into a 64-bit according to x32 ABI
3125 Callee = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i64, Callee);
3128 // Returns a chain & a flag for retval copy to use.
3129 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
3130 SmallVector<SDValue, 8> Ops;
3132 if (!IsSibcall && isTailCall) {
3133 Chain = DAG.getCALLSEQ_END(Chain,
3134 DAG.getIntPtrConstant(NumBytesToPop, true),
3135 DAG.getIntPtrConstant(0, true), InFlag, dl);
3136 InFlag = Chain.getValue(1);
3139 Ops.push_back(Chain);
3140 Ops.push_back(Callee);
3143 Ops.push_back(DAG.getConstant(FPDiff, MVT::i32));
3145 // Add argument registers to the end of the list so that they are known live
3147 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
3148 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
3149 RegsToPass[i].second.getValueType()));
3151 // Add a register mask operand representing the call-preserved registers.
3152 const TargetRegisterInfo *TRI = DAG.getSubtarget().getRegisterInfo();
3153 const uint32_t *Mask = TRI->getCallPreservedMask(CallConv);
3154 assert(Mask && "Missing call preserved mask for calling convention");
3155 Ops.push_back(DAG.getRegisterMask(Mask));
3157 if (InFlag.getNode())
3158 Ops.push_back(InFlag);
3162 //// If this is the first return lowered for this function, add the regs
3163 //// to the liveout set for the function.
3164 // This isn't right, although it's probably harmless on x86; liveouts
3165 // should be computed from returns not tail calls. Consider a void
3166 // function making a tail call to a function returning int.
3167 return DAG.getNode(X86ISD::TC_RETURN, dl, NodeTys, Ops);
3170 Chain = DAG.getNode(X86ISD::CALL, dl, NodeTys, Ops);
3171 InFlag = Chain.getValue(1);
3173 // Create the CALLSEQ_END node.
3174 unsigned NumBytesForCalleeToPop;
3175 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg,
3176 DAG.getTarget().Options.GuaranteedTailCallOpt))
3177 NumBytesForCalleeToPop = NumBytes; // Callee pops everything
3178 else if (!Is64Bit && !IsTailCallConvention(CallConv) &&
3179 !Subtarget->getTargetTriple().isOSMSVCRT() &&
3180 SR == StackStructReturn)
3181 // If this is a call to a struct-return function, the callee
3182 // pops the hidden struct pointer, so we have to push it back.
3183 // This is common for Darwin/X86, Linux & Mingw32 targets.
3184 // For MSVC Win32 targets, the caller pops the hidden struct pointer.
3185 NumBytesForCalleeToPop = 4;
3187 NumBytesForCalleeToPop = 0; // Callee pops nothing.
3189 // Returns a flag for retval copy to use.
3191 Chain = DAG.getCALLSEQ_END(Chain,
3192 DAG.getIntPtrConstant(NumBytesToPop, true),
3193 DAG.getIntPtrConstant(NumBytesForCalleeToPop,
3196 InFlag = Chain.getValue(1);
3199 // Handle result values, copying them out of physregs into vregs that we
3201 return LowerCallResult(Chain, InFlag, CallConv, isVarArg,
3202 Ins, dl, DAG, InVals);
3205 //===----------------------------------------------------------------------===//
3206 // Fast Calling Convention (tail call) implementation
3207 //===----------------------------------------------------------------------===//
3209 // Like std call, callee cleans arguments, convention except that ECX is
3210 // reserved for storing the tail called function address. Only 2 registers are
3211 // free for argument passing (inreg). Tail call optimization is performed
3213 // * tailcallopt is enabled
3214 // * caller/callee are fastcc
3215 // On X86_64 architecture with GOT-style position independent code only local
3216 // (within module) calls are supported at the moment.
3217 // To keep the stack aligned according to platform abi the function
3218 // GetAlignedArgumentStackSize ensures that argument delta is always multiples
3219 // of stack alignment. (Dynamic linkers need this - darwin's dyld for example)
3220 // If a tail called function callee has more arguments than the caller the
3221 // caller needs to make sure that there is room to move the RETADDR to. This is
3222 // achieved by reserving an area the size of the argument delta right after the
3223 // original RETADDR, but before the saved framepointer or the spilled registers
3224 // e.g. caller(arg1, arg2) calls callee(arg1, arg2,arg3,arg4)
3236 /// GetAlignedArgumentStackSize - Make the stack size align e.g 16n + 12 aligned
3237 /// for a 16 byte align requirement.
3239 X86TargetLowering::GetAlignedArgumentStackSize(unsigned StackSize,
3240 SelectionDAG& DAG) const {
3241 MachineFunction &MF = DAG.getMachineFunction();
3242 const TargetMachine &TM = MF.getTarget();
3243 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
3244 TM.getSubtargetImpl()->getRegisterInfo());
3245 const TargetFrameLowering &TFI = *TM.getSubtargetImpl()->getFrameLowering();
3246 unsigned StackAlignment = TFI.getStackAlignment();
3247 uint64_t AlignMask = StackAlignment - 1;
3248 int64_t Offset = StackSize;
3249 unsigned SlotSize = RegInfo->getSlotSize();
3250 if ( (Offset & AlignMask) <= (StackAlignment - SlotSize) ) {
3251 // Number smaller than 12 so just add the difference.
3252 Offset += ((StackAlignment - SlotSize) - (Offset & AlignMask));
3254 // Mask out lower bits, add stackalignment once plus the 12 bytes.
3255 Offset = ((~AlignMask) & Offset) + StackAlignment +
3256 (StackAlignment-SlotSize);
3261 /// MatchingStackOffset - Return true if the given stack call argument is
3262 /// already available in the same position (relatively) of the caller's
3263 /// incoming argument stack.
3265 bool MatchingStackOffset(SDValue Arg, unsigned Offset, ISD::ArgFlagsTy Flags,
3266 MachineFrameInfo *MFI, const MachineRegisterInfo *MRI,
3267 const X86InstrInfo *TII) {
3268 unsigned Bytes = Arg.getValueType().getSizeInBits() / 8;
3270 if (Arg.getOpcode() == ISD::CopyFromReg) {
3271 unsigned VR = cast<RegisterSDNode>(Arg.getOperand(1))->getReg();
3272 if (!TargetRegisterInfo::isVirtualRegister(VR))
3274 MachineInstr *Def = MRI->getVRegDef(VR);
3277 if (!Flags.isByVal()) {
3278 if (!TII->isLoadFromStackSlot(Def, FI))
3281 unsigned Opcode = Def->getOpcode();
3282 if ((Opcode == X86::LEA32r || Opcode == X86::LEA64r) &&
3283 Def->getOperand(1).isFI()) {
3284 FI = Def->getOperand(1).getIndex();
3285 Bytes = Flags.getByValSize();
3289 } else if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Arg)) {
3290 if (Flags.isByVal())
3291 // ByVal argument is passed in as a pointer but it's now being
3292 // dereferenced. e.g.
3293 // define @foo(%struct.X* %A) {
3294 // tail call @bar(%struct.X* byval %A)
3297 SDValue Ptr = Ld->getBasePtr();
3298 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr);
3301 FI = FINode->getIndex();
3302 } else if (Arg.getOpcode() == ISD::FrameIndex && Flags.isByVal()) {
3303 FrameIndexSDNode *FINode = cast<FrameIndexSDNode>(Arg);
3304 FI = FINode->getIndex();
3305 Bytes = Flags.getByValSize();
3309 assert(FI != INT_MAX);
3310 if (!MFI->isFixedObjectIndex(FI))
3312 return Offset == MFI->getObjectOffset(FI) && Bytes == MFI->getObjectSize(FI);
3315 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
3316 /// for tail call optimization. Targets which want to do tail call
3317 /// optimization should implement this function.
3319 X86TargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
3320 CallingConv::ID CalleeCC,
3322 bool isCalleeStructRet,
3323 bool isCallerStructRet,
3325 const SmallVectorImpl<ISD::OutputArg> &Outs,
3326 const SmallVectorImpl<SDValue> &OutVals,
3327 const SmallVectorImpl<ISD::InputArg> &Ins,
3328 SelectionDAG &DAG) const {
3329 if (!IsTailCallConvention(CalleeCC) && !IsCCallConvention(CalleeCC))
3332 // If -tailcallopt is specified, make fastcc functions tail-callable.
3333 const MachineFunction &MF = DAG.getMachineFunction();
3334 const Function *CallerF = MF.getFunction();
3336 // If the function return type is x86_fp80 and the callee return type is not,
3337 // then the FP_EXTEND of the call result is not a nop. It's not safe to
3338 // perform a tailcall optimization here.
3339 if (CallerF->getReturnType()->isX86_FP80Ty() && !RetTy->isX86_FP80Ty())
3342 CallingConv::ID CallerCC = CallerF->getCallingConv();
3343 bool CCMatch = CallerCC == CalleeCC;
3344 bool IsCalleeWin64 = Subtarget->isCallingConvWin64(CalleeCC);
3345 bool IsCallerWin64 = Subtarget->isCallingConvWin64(CallerCC);
3347 if (DAG.getTarget().Options.GuaranteedTailCallOpt) {
3348 if (IsTailCallConvention(CalleeCC) && CCMatch)
3353 // Look for obvious safe cases to perform tail call optimization that do not
3354 // require ABI changes. This is what gcc calls sibcall.
3356 // Can't do sibcall if stack needs to be dynamically re-aligned. PEI needs to
3357 // emit a special epilogue.
3358 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
3359 DAG.getSubtarget().getRegisterInfo());
3360 if (RegInfo->needsStackRealignment(MF))
3363 // Also avoid sibcall optimization if either caller or callee uses struct
3364 // return semantics.
3365 if (isCalleeStructRet || isCallerStructRet)
3368 // An stdcall/thiscall caller is expected to clean up its arguments; the
3369 // callee isn't going to do that.
3370 // FIXME: this is more restrictive than needed. We could produce a tailcall
3371 // when the stack adjustment matches. For example, with a thiscall that takes
3372 // only one argument.
3373 if (!CCMatch && (CallerCC == CallingConv::X86_StdCall ||
3374 CallerCC == CallingConv::X86_ThisCall))
3377 // Do not sibcall optimize vararg calls unless all arguments are passed via
3379 if (isVarArg && !Outs.empty()) {
3381 // Optimizing for varargs on Win64 is unlikely to be safe without
3382 // additional testing.
3383 if (IsCalleeWin64 || IsCallerWin64)
3386 SmallVector<CCValAssign, 16> ArgLocs;
3387 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(), ArgLocs,
3390 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
3391 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i)
3392 if (!ArgLocs[i].isRegLoc())
3396 // If the call result is in ST0 / ST1, it needs to be popped off the x87
3397 // stack. Therefore, if it's not used by the call it is not safe to optimize
3398 // this into a sibcall.
3399 bool Unused = false;
3400 for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
3407 SmallVector<CCValAssign, 16> RVLocs;
3408 CCState CCInfo(CalleeCC, false, DAG.getMachineFunction(), RVLocs,
3410 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
3411 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
3412 CCValAssign &VA = RVLocs[i];
3413 if (VA.getLocReg() == X86::FP0 || VA.getLocReg() == X86::FP1)
3418 // If the calling conventions do not match, then we'd better make sure the
3419 // results are returned in the same way as what the caller expects.
3421 SmallVector<CCValAssign, 16> RVLocs1;
3422 CCState CCInfo1(CalleeCC, false, DAG.getMachineFunction(), RVLocs1,
3424 CCInfo1.AnalyzeCallResult(Ins, RetCC_X86);
3426 SmallVector<CCValAssign, 16> RVLocs2;
3427 CCState CCInfo2(CallerCC, false, DAG.getMachineFunction(), RVLocs2,
3429 CCInfo2.AnalyzeCallResult(Ins, RetCC_X86);
3431 if (RVLocs1.size() != RVLocs2.size())
3433 for (unsigned i = 0, e = RVLocs1.size(); i != e; ++i) {
3434 if (RVLocs1[i].isRegLoc() != RVLocs2[i].isRegLoc())
3436 if (RVLocs1[i].getLocInfo() != RVLocs2[i].getLocInfo())
3438 if (RVLocs1[i].isRegLoc()) {
3439 if (RVLocs1[i].getLocReg() != RVLocs2[i].getLocReg())
3442 if (RVLocs1[i].getLocMemOffset() != RVLocs2[i].getLocMemOffset())
3448 // If the callee takes no arguments then go on to check the results of the
3450 if (!Outs.empty()) {
3451 // Check if stack adjustment is needed. For now, do not do this if any
3452 // argument is passed on the stack.
3453 SmallVector<CCValAssign, 16> ArgLocs;
3454 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(), ArgLocs,
3457 // Allocate shadow area for Win64
3459 CCInfo.AllocateStack(32, 8);
3461 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
3462 if (CCInfo.getNextStackOffset()) {
3463 MachineFunction &MF = DAG.getMachineFunction();
3464 if (MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn())
3467 // Check if the arguments are already laid out in the right way as
3468 // the caller's fixed stack objects.
3469 MachineFrameInfo *MFI = MF.getFrameInfo();
3470 const MachineRegisterInfo *MRI = &MF.getRegInfo();
3471 const X86InstrInfo *TII =
3472 static_cast<const X86InstrInfo *>(DAG.getSubtarget().getInstrInfo());
3473 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3474 CCValAssign &VA = ArgLocs[i];
3475 SDValue Arg = OutVals[i];
3476 ISD::ArgFlagsTy Flags = Outs[i].Flags;
3477 if (VA.getLocInfo() == CCValAssign::Indirect)
3479 if (!VA.isRegLoc()) {
3480 if (!MatchingStackOffset(Arg, VA.getLocMemOffset(), Flags,
3487 // If the tailcall address may be in a register, then make sure it's
3488 // possible to register allocate for it. In 32-bit, the call address can
3489 // only target EAX, EDX, or ECX since the tail call must be scheduled after
3490 // callee-saved registers are restored. These happen to be the same
3491 // registers used to pass 'inreg' arguments so watch out for those.
3492 if (!Subtarget->is64Bit() &&
3493 ((!isa<GlobalAddressSDNode>(Callee) &&
3494 !isa<ExternalSymbolSDNode>(Callee)) ||
3495 DAG.getTarget().getRelocationModel() == Reloc::PIC_)) {
3496 unsigned NumInRegs = 0;
3497 // In PIC we need an extra register to formulate the address computation
3499 unsigned MaxInRegs =
3500 (DAG.getTarget().getRelocationModel() == Reloc::PIC_) ? 2 : 3;
3502 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3503 CCValAssign &VA = ArgLocs[i];
3506 unsigned Reg = VA.getLocReg();
3509 case X86::EAX: case X86::EDX: case X86::ECX:
3510 if (++NumInRegs == MaxInRegs)
3522 X86TargetLowering::createFastISel(FunctionLoweringInfo &funcInfo,
3523 const TargetLibraryInfo *libInfo) const {
3524 return X86::createFastISel(funcInfo, libInfo);
3527 //===----------------------------------------------------------------------===//
3528 // Other Lowering Hooks
3529 //===----------------------------------------------------------------------===//
3531 static bool MayFoldLoad(SDValue Op) {
3532 return Op.hasOneUse() && ISD::isNormalLoad(Op.getNode());
3535 static bool MayFoldIntoStore(SDValue Op) {
3536 return Op.hasOneUse() && ISD::isNormalStore(*Op.getNode()->use_begin());
3539 static bool isTargetShuffle(unsigned Opcode) {
3541 default: return false;
3542 case X86ISD::PSHUFB:
3543 case X86ISD::PSHUFD:
3544 case X86ISD::PSHUFHW:
3545 case X86ISD::PSHUFLW:
3547 case X86ISD::PALIGNR:
3548 case X86ISD::MOVLHPS:
3549 case X86ISD::MOVLHPD:
3550 case X86ISD::MOVHLPS:
3551 case X86ISD::MOVLPS:
3552 case X86ISD::MOVLPD:
3553 case X86ISD::MOVSHDUP:
3554 case X86ISD::MOVSLDUP:
3555 case X86ISD::MOVDDUP:
3558 case X86ISD::UNPCKL:
3559 case X86ISD::UNPCKH:
3560 case X86ISD::VPERMILPI:
3561 case X86ISD::VPERM2X128:
3562 case X86ISD::VPERMI:
3567 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3568 SDValue V1, SelectionDAG &DAG) {
3570 default: llvm_unreachable("Unknown x86 shuffle node");
3571 case X86ISD::MOVSHDUP:
3572 case X86ISD::MOVSLDUP:
3573 case X86ISD::MOVDDUP:
3574 return DAG.getNode(Opc, dl, VT, V1);
3578 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3579 SDValue V1, unsigned TargetMask,
3580 SelectionDAG &DAG) {
3582 default: llvm_unreachable("Unknown x86 shuffle node");
3583 case X86ISD::PSHUFD:
3584 case X86ISD::PSHUFHW:
3585 case X86ISD::PSHUFLW:
3586 case X86ISD::VPERMILPI:
3587 case X86ISD::VPERMI:
3588 return DAG.getNode(Opc, dl, VT, V1, DAG.getConstant(TargetMask, MVT::i8));
3592 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3593 SDValue V1, SDValue V2, unsigned TargetMask,
3594 SelectionDAG &DAG) {
3596 default: llvm_unreachable("Unknown x86 shuffle node");
3597 case X86ISD::PALIGNR:
3598 case X86ISD::VALIGN:
3600 case X86ISD::VPERM2X128:
3601 return DAG.getNode(Opc, dl, VT, V1, V2,
3602 DAG.getConstant(TargetMask, MVT::i8));
3606 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3607 SDValue V1, SDValue V2, SelectionDAG &DAG) {
3609 default: llvm_unreachable("Unknown x86 shuffle node");
3610 case X86ISD::MOVLHPS:
3611 case X86ISD::MOVLHPD:
3612 case X86ISD::MOVHLPS:
3613 case X86ISD::MOVLPS:
3614 case X86ISD::MOVLPD:
3617 case X86ISD::UNPCKL:
3618 case X86ISD::UNPCKH:
3619 return DAG.getNode(Opc, dl, VT, V1, V2);
3623 SDValue X86TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) const {
3624 MachineFunction &MF = DAG.getMachineFunction();
3625 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
3626 DAG.getSubtarget().getRegisterInfo());
3627 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
3628 int ReturnAddrIndex = FuncInfo->getRAIndex();
3630 if (ReturnAddrIndex == 0) {
3631 // Set up a frame object for the return address.
3632 unsigned SlotSize = RegInfo->getSlotSize();
3633 ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(SlotSize,
3636 FuncInfo->setRAIndex(ReturnAddrIndex);
3639 return DAG.getFrameIndex(ReturnAddrIndex, getPointerTy());
3642 bool X86::isOffsetSuitableForCodeModel(int64_t Offset, CodeModel::Model M,
3643 bool hasSymbolicDisplacement) {
3644 // Offset should fit into 32 bit immediate field.
3645 if (!isInt<32>(Offset))
3648 // If we don't have a symbolic displacement - we don't have any extra
3650 if (!hasSymbolicDisplacement)
3653 // FIXME: Some tweaks might be needed for medium code model.
3654 if (M != CodeModel::Small && M != CodeModel::Kernel)
3657 // For small code model we assume that latest object is 16MB before end of 31
3658 // bits boundary. We may also accept pretty large negative constants knowing
3659 // that all objects are in the positive half of address space.
3660 if (M == CodeModel::Small && Offset < 16*1024*1024)
3663 // For kernel code model we know that all object resist in the negative half
3664 // of 32bits address space. We may not accept negative offsets, since they may
3665 // be just off and we may accept pretty large positive ones.
3666 if (M == CodeModel::Kernel && Offset > 0)
3672 /// isCalleePop - Determines whether the callee is required to pop its
3673 /// own arguments. Callee pop is necessary to support tail calls.
3674 bool X86::isCalleePop(CallingConv::ID CallingConv,
3675 bool is64Bit, bool IsVarArg, bool TailCallOpt) {
3676 switch (CallingConv) {
3679 case CallingConv::X86_StdCall:
3680 case CallingConv::X86_FastCall:
3681 case CallingConv::X86_ThisCall:
3683 case CallingConv::Fast:
3684 case CallingConv::GHC:
3685 case CallingConv::HiPE:
3692 /// \brief Return true if the condition is an unsigned comparison operation.
3693 static bool isX86CCUnsigned(unsigned X86CC) {
3695 default: llvm_unreachable("Invalid integer condition!");
3696 case X86::COND_E: return true;
3697 case X86::COND_G: return false;
3698 case X86::COND_GE: return false;
3699 case X86::COND_L: return false;
3700 case X86::COND_LE: return false;
3701 case X86::COND_NE: return true;
3702 case X86::COND_B: return true;
3703 case X86::COND_A: return true;
3704 case X86::COND_BE: return true;
3705 case X86::COND_AE: return true;
3707 llvm_unreachable("covered switch fell through?!");
3710 /// TranslateX86CC - do a one to one translation of a ISD::CondCode to the X86
3711 /// specific condition code, returning the condition code and the LHS/RHS of the
3712 /// comparison to make.
3713 static unsigned TranslateX86CC(ISD::CondCode SetCCOpcode, bool isFP,
3714 SDValue &LHS, SDValue &RHS, SelectionDAG &DAG) {
3716 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
3717 if (SetCCOpcode == ISD::SETGT && RHSC->isAllOnesValue()) {
3718 // X > -1 -> X == 0, jump !sign.
3719 RHS = DAG.getConstant(0, RHS.getValueType());
3720 return X86::COND_NS;
3722 if (SetCCOpcode == ISD::SETLT && RHSC->isNullValue()) {
3723 // X < 0 -> X == 0, jump on sign.
3726 if (SetCCOpcode == ISD::SETLT && RHSC->getZExtValue() == 1) {
3728 RHS = DAG.getConstant(0, RHS.getValueType());
3729 return X86::COND_LE;
3733 switch (SetCCOpcode) {
3734 default: llvm_unreachable("Invalid integer condition!");
3735 case ISD::SETEQ: return X86::COND_E;
3736 case ISD::SETGT: return X86::COND_G;
3737 case ISD::SETGE: return X86::COND_GE;
3738 case ISD::SETLT: return X86::COND_L;
3739 case ISD::SETLE: return X86::COND_LE;
3740 case ISD::SETNE: return X86::COND_NE;
3741 case ISD::SETULT: return X86::COND_B;
3742 case ISD::SETUGT: return X86::COND_A;
3743 case ISD::SETULE: return X86::COND_BE;
3744 case ISD::SETUGE: return X86::COND_AE;
3748 // First determine if it is required or is profitable to flip the operands.
3750 // If LHS is a foldable load, but RHS is not, flip the condition.
3751 if (ISD::isNON_EXTLoad(LHS.getNode()) &&
3752 !ISD::isNON_EXTLoad(RHS.getNode())) {
3753 SetCCOpcode = getSetCCSwappedOperands(SetCCOpcode);
3754 std::swap(LHS, RHS);
3757 switch (SetCCOpcode) {
3763 std::swap(LHS, RHS);
3767 // On a floating point condition, the flags are set as follows:
3769 // 0 | 0 | 0 | X > Y
3770 // 0 | 0 | 1 | X < Y
3771 // 1 | 0 | 0 | X == Y
3772 // 1 | 1 | 1 | unordered
3773 switch (SetCCOpcode) {
3774 default: llvm_unreachable("Condcode should be pre-legalized away");
3776 case ISD::SETEQ: return X86::COND_E;
3777 case ISD::SETOLT: // flipped
3779 case ISD::SETGT: return X86::COND_A;
3780 case ISD::SETOLE: // flipped
3782 case ISD::SETGE: return X86::COND_AE;
3783 case ISD::SETUGT: // flipped
3785 case ISD::SETLT: return X86::COND_B;
3786 case ISD::SETUGE: // flipped
3788 case ISD::SETLE: return X86::COND_BE;
3790 case ISD::SETNE: return X86::COND_NE;
3791 case ISD::SETUO: return X86::COND_P;
3792 case ISD::SETO: return X86::COND_NP;
3794 case ISD::SETUNE: return X86::COND_INVALID;
3798 /// hasFPCMov - is there a floating point cmov for the specific X86 condition
3799 /// code. Current x86 isa includes the following FP cmov instructions:
3800 /// fcmovb, fcomvbe, fcomve, fcmovu, fcmovae, fcmova, fcmovne, fcmovnu.
3801 static bool hasFPCMov(unsigned X86CC) {
3817 /// isFPImmLegal - Returns true if the target can instruction select the
3818 /// specified FP immediate natively. If false, the legalizer will
3819 /// materialize the FP immediate as a load from a constant pool.
3820 bool X86TargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
3821 for (unsigned i = 0, e = LegalFPImmediates.size(); i != e; ++i) {
3822 if (Imm.bitwiseIsEqual(LegalFPImmediates[i]))
3828 /// \brief Returns true if it is beneficial to convert a load of a constant
3829 /// to just the constant itself.
3830 bool X86TargetLowering::shouldConvertConstantLoadToIntImm(const APInt &Imm,
3832 assert(Ty->isIntegerTy());
3834 unsigned BitSize = Ty->getPrimitiveSizeInBits();
3835 if (BitSize == 0 || BitSize > 64)
3840 /// isUndefOrInRange - Return true if Val is undef or if its value falls within
3841 /// the specified range (L, H].
3842 static bool isUndefOrInRange(int Val, int Low, int Hi) {
3843 return (Val < 0) || (Val >= Low && Val < Hi);
3846 /// isUndefOrEqual - Val is either less than zero (undef) or equal to the
3847 /// specified value.
3848 static bool isUndefOrEqual(int Val, int CmpVal) {
3849 return (Val < 0 || Val == CmpVal);
3852 /// isSequentialOrUndefInRange - Return true if every element in Mask, beginning
3853 /// from position Pos and ending in Pos+Size, falls within the specified
3854 /// sequential range (L, L+Pos]. or is undef.
3855 static bool isSequentialOrUndefInRange(ArrayRef<int> Mask,
3856 unsigned Pos, unsigned Size, int Low) {
3857 for (unsigned i = Pos, e = Pos+Size; i != e; ++i, ++Low)
3858 if (!isUndefOrEqual(Mask[i], Low))
3863 /// isPSHUFDMask - Return true if the node specifies a shuffle of elements that
3864 /// is suitable for input to PSHUFD or PSHUFW. That is, it doesn't reference
3865 /// the second operand.
3866 static bool isPSHUFDMask(ArrayRef<int> Mask, MVT VT) {
3867 if (VT == MVT::v4f32 || VT == MVT::v4i32 )
3868 return (Mask[0] < 4 && Mask[1] < 4 && Mask[2] < 4 && Mask[3] < 4);
3869 if (VT == MVT::v2f64 || VT == MVT::v2i64)
3870 return (Mask[0] < 2 && Mask[1] < 2);
3874 /// isPSHUFHWMask - Return true if the node specifies a shuffle of elements that
3875 /// is suitable for input to PSHUFHW.
3876 static bool isPSHUFHWMask(ArrayRef<int> Mask, MVT VT, bool HasInt256) {
3877 if (VT != MVT::v8i16 && (!HasInt256 || VT != MVT::v16i16))
3880 // Lower quadword copied in order or undef.
3881 if (!isSequentialOrUndefInRange(Mask, 0, 4, 0))
3884 // Upper quadword shuffled.
3885 for (unsigned i = 4; i != 8; ++i)
3886 if (!isUndefOrInRange(Mask[i], 4, 8))
3889 if (VT == MVT::v16i16) {
3890 // Lower quadword copied in order or undef.
3891 if (!isSequentialOrUndefInRange(Mask, 8, 4, 8))
3894 // Upper quadword shuffled.
3895 for (unsigned i = 12; i != 16; ++i)
3896 if (!isUndefOrInRange(Mask[i], 12, 16))
3903 /// isPSHUFLWMask - Return true if the node specifies a shuffle of elements that
3904 /// is suitable for input to PSHUFLW.
3905 static bool isPSHUFLWMask(ArrayRef<int> Mask, MVT VT, bool HasInt256) {
3906 if (VT != MVT::v8i16 && (!HasInt256 || VT != MVT::v16i16))
3909 // Upper quadword copied in order.
3910 if (!isSequentialOrUndefInRange(Mask, 4, 4, 4))
3913 // Lower quadword shuffled.
3914 for (unsigned i = 0; i != 4; ++i)
3915 if (!isUndefOrInRange(Mask[i], 0, 4))
3918 if (VT == MVT::v16i16) {
3919 // Upper quadword copied in order.
3920 if (!isSequentialOrUndefInRange(Mask, 12, 4, 12))
3923 // Lower quadword shuffled.
3924 for (unsigned i = 8; i != 12; ++i)
3925 if (!isUndefOrInRange(Mask[i], 8, 12))
3932 /// \brief Return true if the mask specifies a shuffle of elements that is
3933 /// suitable for input to intralane (palignr) or interlane (valign) vector
3935 static bool isAlignrMask(ArrayRef<int> Mask, MVT VT, bool InterLane) {
3936 unsigned NumElts = VT.getVectorNumElements();
3937 unsigned NumLanes = InterLane ? 1: VT.getSizeInBits()/128;
3938 unsigned NumLaneElts = NumElts/NumLanes;
3940 // Do not handle 64-bit element shuffles with palignr.
3941 if (NumLaneElts == 2)
3944 for (unsigned l = 0; l != NumElts; l+=NumLaneElts) {
3946 for (i = 0; i != NumLaneElts; ++i) {
3951 // Lane is all undef, go to next lane
3952 if (i == NumLaneElts)
3955 int Start = Mask[i+l];
3957 // Make sure its in this lane in one of the sources
3958 if (!isUndefOrInRange(Start, l, l+NumLaneElts) &&
3959 !isUndefOrInRange(Start, l+NumElts, l+NumElts+NumLaneElts))
3962 // If not lane 0, then we must match lane 0
3963 if (l != 0 && Mask[i] >= 0 && !isUndefOrEqual(Start, Mask[i]+l))
3966 // Correct second source to be contiguous with first source
3967 if (Start >= (int)NumElts)
3968 Start -= NumElts - NumLaneElts;
3970 // Make sure we're shifting in the right direction.
3971 if (Start <= (int)(i+l))
3976 // Check the rest of the elements to see if they are consecutive.
3977 for (++i; i != NumLaneElts; ++i) {
3978 int Idx = Mask[i+l];
3980 // Make sure its in this lane
3981 if (!isUndefOrInRange(Idx, l, l+NumLaneElts) &&
3982 !isUndefOrInRange(Idx, l+NumElts, l+NumElts+NumLaneElts))
3985 // If not lane 0, then we must match lane 0
3986 if (l != 0 && Mask[i] >= 0 && !isUndefOrEqual(Idx, Mask[i]+l))
3989 if (Idx >= (int)NumElts)
3990 Idx -= NumElts - NumLaneElts;
3992 if (!isUndefOrEqual(Idx, Start+i))
4001 /// \brief Return true if the node specifies a shuffle of elements that is
4002 /// suitable for input to PALIGNR.
4003 static bool isPALIGNRMask(ArrayRef<int> Mask, MVT VT,
4004 const X86Subtarget *Subtarget) {
4005 if ((VT.is128BitVector() && !Subtarget->hasSSSE3()) ||
4006 (VT.is256BitVector() && !Subtarget->hasInt256()) ||
4007 VT.is512BitVector())
4008 // FIXME: Add AVX512BW.
4011 return isAlignrMask(Mask, VT, false);
4014 /// \brief Return true if the node specifies a shuffle of elements that is
4015 /// suitable for input to VALIGN.
4016 static bool isVALIGNMask(ArrayRef<int> Mask, MVT VT,
4017 const X86Subtarget *Subtarget) {
4018 // FIXME: Add AVX512VL.
4019 if (!VT.is512BitVector() || !Subtarget->hasAVX512())
4021 return isAlignrMask(Mask, VT, true);
4024 /// CommuteVectorShuffleMask - Change values in a shuffle permute mask assuming
4025 /// the two vector operands have swapped position.
4026 static void CommuteVectorShuffleMask(SmallVectorImpl<int> &Mask,
4027 unsigned NumElems) {
4028 for (unsigned i = 0; i != NumElems; ++i) {
4032 else if (idx < (int)NumElems)
4033 Mask[i] = idx + NumElems;
4035 Mask[i] = idx - NumElems;
4039 /// isSHUFPMask - Return true if the specified VECTOR_SHUFFLE operand
4040 /// specifies a shuffle of elements that is suitable for input to 128/256-bit
4041 /// SHUFPS and SHUFPD. If Commuted is true, then it checks for sources to be
4042 /// reverse of what x86 shuffles want.
4043 static bool isSHUFPMask(ArrayRef<int> Mask, MVT VT, bool Commuted = false) {
4045 unsigned NumElems = VT.getVectorNumElements();
4046 unsigned NumLanes = VT.getSizeInBits()/128;
4047 unsigned NumLaneElems = NumElems/NumLanes;
4049 if (NumLaneElems != 2 && NumLaneElems != 4)
4052 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
4053 bool symetricMaskRequired =
4054 (VT.getSizeInBits() >= 256) && (EltSize == 32);
4056 // VSHUFPSY divides the resulting vector into 4 chunks.
4057 // The sources are also splitted into 4 chunks, and each destination
4058 // chunk must come from a different source chunk.
4060 // SRC1 => X7 X6 X5 X4 X3 X2 X1 X0
4061 // SRC2 => Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y9
4063 // DST => Y7..Y4, Y7..Y4, X7..X4, X7..X4,
4064 // Y3..Y0, Y3..Y0, X3..X0, X3..X0
4066 // VSHUFPDY divides the resulting vector into 4 chunks.
4067 // The sources are also splitted into 4 chunks, and each destination
4068 // chunk must come from a different source chunk.
4070 // SRC1 => X3 X2 X1 X0
4071 // SRC2 => Y3 Y2 Y1 Y0
4073 // DST => Y3..Y2, X3..X2, Y1..Y0, X1..X0
4075 SmallVector<int, 4> MaskVal(NumLaneElems, -1);
4076 unsigned HalfLaneElems = NumLaneElems/2;
4077 for (unsigned l = 0; l != NumElems; l += NumLaneElems) {
4078 for (unsigned i = 0; i != NumLaneElems; ++i) {
4079 int Idx = Mask[i+l];
4080 unsigned RngStart = l + ((Commuted == (i<HalfLaneElems)) ? NumElems : 0);
4081 if (!isUndefOrInRange(Idx, RngStart, RngStart+NumLaneElems))
4083 // For VSHUFPSY, the mask of the second half must be the same as the
4084 // first but with the appropriate offsets. This works in the same way as
4085 // VPERMILPS works with masks.
4086 if (!symetricMaskRequired || Idx < 0)
4088 if (MaskVal[i] < 0) {
4089 MaskVal[i] = Idx - l;
4092 if ((signed)(Idx - l) != MaskVal[i])
4100 /// isMOVHLPSMask - Return true if the specified VECTOR_SHUFFLE operand
4101 /// specifies a shuffle of elements that is suitable for input to MOVHLPS.
4102 static bool isMOVHLPSMask(ArrayRef<int> Mask, MVT VT) {
4103 if (!VT.is128BitVector())
4106 unsigned NumElems = VT.getVectorNumElements();
4111 // Expect bit0 == 6, bit1 == 7, bit2 == 2, bit3 == 3
4112 return isUndefOrEqual(Mask[0], 6) &&
4113 isUndefOrEqual(Mask[1], 7) &&
4114 isUndefOrEqual(Mask[2], 2) &&
4115 isUndefOrEqual(Mask[3], 3);
4118 /// isMOVHLPS_v_undef_Mask - Special case of isMOVHLPSMask for canonical form
4119 /// of vector_shuffle v, v, <2, 3, 2, 3>, i.e. vector_shuffle v, undef,
4121 static bool isMOVHLPS_v_undef_Mask(ArrayRef<int> Mask, MVT VT) {
4122 if (!VT.is128BitVector())
4125 unsigned NumElems = VT.getVectorNumElements();
4130 return isUndefOrEqual(Mask[0], 2) &&
4131 isUndefOrEqual(Mask[1], 3) &&
4132 isUndefOrEqual(Mask[2], 2) &&
4133 isUndefOrEqual(Mask[3], 3);
4136 /// isMOVLPMask - Return true if the specified VECTOR_SHUFFLE operand
4137 /// specifies a shuffle of elements that is suitable for input to MOVLP{S|D}.
4138 static bool isMOVLPMask(ArrayRef<int> Mask, MVT VT) {
4139 if (!VT.is128BitVector())
4142 unsigned NumElems = VT.getVectorNumElements();
4144 if (NumElems != 2 && NumElems != 4)
4147 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
4148 if (!isUndefOrEqual(Mask[i], i + NumElems))
4151 for (unsigned i = NumElems/2, e = NumElems; i != e; ++i)
4152 if (!isUndefOrEqual(Mask[i], i))
4158 /// isMOVLHPSMask - Return true if the specified VECTOR_SHUFFLE operand
4159 /// specifies a shuffle of elements that is suitable for input to MOVLHPS.
4160 static bool isMOVLHPSMask(ArrayRef<int> Mask, MVT VT) {
4161 if (!VT.is128BitVector())
4164 unsigned NumElems = VT.getVectorNumElements();
4166 if (NumElems != 2 && NumElems != 4)
4169 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
4170 if (!isUndefOrEqual(Mask[i], i))
4173 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
4174 if (!isUndefOrEqual(Mask[i + e], i + NumElems))
4180 /// isINSERTPSMask - Return true if the specified VECTOR_SHUFFLE operand
4181 /// specifies a shuffle of elements that is suitable for input to INSERTPS.
4182 /// i. e: If all but one element come from the same vector.
4183 static bool isINSERTPSMask(ArrayRef<int> Mask, MVT VT) {
4184 // TODO: Deal with AVX's VINSERTPS
4185 if (!VT.is128BitVector() || (VT != MVT::v4f32 && VT != MVT::v4i32))
4188 unsigned CorrectPosV1 = 0;
4189 unsigned CorrectPosV2 = 0;
4190 for (int i = 0, e = (int)VT.getVectorNumElements(); i != e; ++i) {
4191 if (Mask[i] == -1) {
4199 else if (Mask[i] == i + 4)
4203 if (CorrectPosV1 == 3 || CorrectPosV2 == 3)
4204 // We have 3 elements (undefs count as elements from any vector) from one
4205 // vector, and one from another.
4212 // Some special combinations that can be optimized.
4215 SDValue Compact8x32ShuffleNode(ShuffleVectorSDNode *SVOp,
4216 SelectionDAG &DAG) {
4217 MVT VT = SVOp->getSimpleValueType(0);
4220 if (VT != MVT::v8i32 && VT != MVT::v8f32)
4223 ArrayRef<int> Mask = SVOp->getMask();
4225 // These are the special masks that may be optimized.
4226 static const int MaskToOptimizeEven[] = {0, 8, 2, 10, 4, 12, 6, 14};
4227 static const int MaskToOptimizeOdd[] = {1, 9, 3, 11, 5, 13, 7, 15};
4228 bool MatchEvenMask = true;
4229 bool MatchOddMask = true;
4230 for (int i=0; i<8; ++i) {
4231 if (!isUndefOrEqual(Mask[i], MaskToOptimizeEven[i]))
4232 MatchEvenMask = false;
4233 if (!isUndefOrEqual(Mask[i], MaskToOptimizeOdd[i]))
4234 MatchOddMask = false;
4237 if (!MatchEvenMask && !MatchOddMask)
4240 SDValue UndefNode = DAG.getNode(ISD::UNDEF, dl, VT);
4242 SDValue Op0 = SVOp->getOperand(0);
4243 SDValue Op1 = SVOp->getOperand(1);
4245 if (MatchEvenMask) {
4246 // Shift the second operand right to 32 bits.
4247 static const int ShiftRightMask[] = {-1, 0, -1, 2, -1, 4, -1, 6 };
4248 Op1 = DAG.getVectorShuffle(VT, dl, Op1, UndefNode, ShiftRightMask);
4250 // Shift the first operand left to 32 bits.
4251 static const int ShiftLeftMask[] = {1, -1, 3, -1, 5, -1, 7, -1 };
4252 Op0 = DAG.getVectorShuffle(VT, dl, Op0, UndefNode, ShiftLeftMask);
4254 static const int BlendMask[] = {0, 9, 2, 11, 4, 13, 6, 15};
4255 return DAG.getVectorShuffle(VT, dl, Op0, Op1, BlendMask);
4258 /// isUNPCKLMask - Return true if the specified VECTOR_SHUFFLE operand
4259 /// specifies a shuffle of elements that is suitable for input to UNPCKL.
4260 static bool isUNPCKLMask(ArrayRef<int> Mask, MVT VT,
4261 bool HasInt256, bool V2IsSplat = false) {
4263 assert(VT.getSizeInBits() >= 128 &&
4264 "Unsupported vector type for unpckl");
4266 unsigned NumElts = VT.getVectorNumElements();
4267 if (VT.is256BitVector() && NumElts != 4 && NumElts != 8 &&
4268 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
4271 assert((!VT.is512BitVector() || VT.getScalarType().getSizeInBits() >= 32) &&
4272 "Unsupported vector type for unpckh");
4274 // AVX defines UNPCK* to operate independently on 128-bit lanes.
4275 unsigned NumLanes = VT.getSizeInBits()/128;
4276 unsigned NumLaneElts = NumElts/NumLanes;
4278 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
4279 for (unsigned i = 0, j = l; i != NumLaneElts; i += 2, ++j) {
4280 int BitI = Mask[l+i];
4281 int BitI1 = Mask[l+i+1];
4282 if (!isUndefOrEqual(BitI, j))
4285 if (!isUndefOrEqual(BitI1, NumElts))
4288 if (!isUndefOrEqual(BitI1, j + NumElts))
4297 /// isUNPCKHMask - Return true if the specified VECTOR_SHUFFLE operand
4298 /// specifies a shuffle of elements that is suitable for input to UNPCKH.
4299 static bool isUNPCKHMask(ArrayRef<int> Mask, MVT VT,
4300 bool HasInt256, bool V2IsSplat = false) {
4301 assert(VT.getSizeInBits() >= 128 &&
4302 "Unsupported vector type for unpckh");
4304 unsigned NumElts = VT.getVectorNumElements();
4305 if (VT.is256BitVector() && NumElts != 4 && NumElts != 8 &&
4306 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
4309 assert((!VT.is512BitVector() || VT.getScalarType().getSizeInBits() >= 32) &&
4310 "Unsupported vector type for unpckh");
4312 // AVX defines UNPCK* to operate independently on 128-bit lanes.
4313 unsigned NumLanes = VT.getSizeInBits()/128;
4314 unsigned NumLaneElts = NumElts/NumLanes;
4316 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
4317 for (unsigned i = 0, j = l+NumLaneElts/2; i != NumLaneElts; i += 2, ++j) {
4318 int BitI = Mask[l+i];
4319 int BitI1 = Mask[l+i+1];
4320 if (!isUndefOrEqual(BitI, j))
4323 if (isUndefOrEqual(BitI1, NumElts))
4326 if (!isUndefOrEqual(BitI1, j+NumElts))
4334 /// isUNPCKL_v_undef_Mask - Special case of isUNPCKLMask for canonical form
4335 /// of vector_shuffle v, v, <0, 4, 1, 5>, i.e. vector_shuffle v, undef,
4337 static bool isUNPCKL_v_undef_Mask(ArrayRef<int> Mask, MVT VT, bool HasInt256) {
4338 unsigned NumElts = VT.getVectorNumElements();
4339 bool Is256BitVec = VT.is256BitVector();
4341 if (VT.is512BitVector())
4343 assert((VT.is128BitVector() || VT.is256BitVector()) &&
4344 "Unsupported vector type for unpckh");
4346 if (Is256BitVec && NumElts != 4 && NumElts != 8 &&
4347 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
4350 // For 256-bit i64/f64, use MOVDDUPY instead, so reject the matching pattern
4351 // FIXME: Need a better way to get rid of this, there's no latency difference
4352 // between UNPCKLPD and MOVDDUP, the later should always be checked first and
4353 // the former later. We should also remove the "_undef" special mask.
4354 if (NumElts == 4 && Is256BitVec)
4357 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
4358 // independently on 128-bit lanes.
4359 unsigned NumLanes = VT.getSizeInBits()/128;
4360 unsigned NumLaneElts = NumElts/NumLanes;
4362 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
4363 for (unsigned i = 0, j = l; i != NumLaneElts; i += 2, ++j) {
4364 int BitI = Mask[l+i];
4365 int BitI1 = Mask[l+i+1];
4367 if (!isUndefOrEqual(BitI, j))
4369 if (!isUndefOrEqual(BitI1, j))
4377 /// isUNPCKH_v_undef_Mask - Special case of isUNPCKHMask for canonical form
4378 /// of vector_shuffle v, v, <2, 6, 3, 7>, i.e. vector_shuffle v, undef,
4380 static bool isUNPCKH_v_undef_Mask(ArrayRef<int> Mask, MVT VT, bool HasInt256) {
4381 unsigned NumElts = VT.getVectorNumElements();
4383 if (VT.is512BitVector())
4386 assert((VT.is128BitVector() || VT.is256BitVector()) &&
4387 "Unsupported vector type for unpckh");
4389 if (VT.is256BitVector() && NumElts != 4 && NumElts != 8 &&
4390 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
4393 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
4394 // independently on 128-bit lanes.
4395 unsigned NumLanes = VT.getSizeInBits()/128;
4396 unsigned NumLaneElts = NumElts/NumLanes;
4398 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
4399 for (unsigned i = 0, j = l+NumLaneElts/2; i != NumLaneElts; i += 2, ++j) {
4400 int BitI = Mask[l+i];
4401 int BitI1 = Mask[l+i+1];
4402 if (!isUndefOrEqual(BitI, j))
4404 if (!isUndefOrEqual(BitI1, j))
4411 // Match for INSERTI64x4 INSERTF64x4 instructions (src0[0], src1[0]) or
4412 // (src1[0], src0[1]), manipulation with 256-bit sub-vectors
4413 static bool isINSERT64x4Mask(ArrayRef<int> Mask, MVT VT, unsigned int *Imm) {
4414 if (!VT.is512BitVector())
4417 unsigned NumElts = VT.getVectorNumElements();
4418 unsigned HalfSize = NumElts/2;
4419 if (isSequentialOrUndefInRange(Mask, 0, HalfSize, 0)) {
4420 if (isSequentialOrUndefInRange(Mask, HalfSize, HalfSize, NumElts)) {
4425 if (isSequentialOrUndefInRange(Mask, 0, HalfSize, NumElts)) {
4426 if (isSequentialOrUndefInRange(Mask, HalfSize, HalfSize, HalfSize)) {
4434 /// isMOVLMask - Return true if the specified VECTOR_SHUFFLE operand
4435 /// specifies a shuffle of elements that is suitable for input to MOVSS,
4436 /// MOVSD, and MOVD, i.e. setting the lowest element.
4437 static bool isMOVLMask(ArrayRef<int> Mask, EVT VT) {
4438 if (VT.getVectorElementType().getSizeInBits() < 32)
4440 if (!VT.is128BitVector())
4443 unsigned NumElts = VT.getVectorNumElements();
4445 if (!isUndefOrEqual(Mask[0], NumElts))
4448 for (unsigned i = 1; i != NumElts; ++i)
4449 if (!isUndefOrEqual(Mask[i], i))
4455 /// isVPERM2X128Mask - Match 256-bit shuffles where the elements are considered
4456 /// as permutations between 128-bit chunks or halves. As an example: this
4458 /// vector_shuffle <4, 5, 6, 7, 12, 13, 14, 15>
4459 /// The first half comes from the second half of V1 and the second half from the
4460 /// the second half of V2.
4461 static bool isVPERM2X128Mask(ArrayRef<int> Mask, MVT VT, bool HasFp256) {
4462 if (!HasFp256 || !VT.is256BitVector())
4465 // The shuffle result is divided into half A and half B. In total the two
4466 // sources have 4 halves, namely: C, D, E, F. The final values of A and
4467 // B must come from C, D, E or F.
4468 unsigned HalfSize = VT.getVectorNumElements()/2;
4469 bool MatchA = false, MatchB = false;
4471 // Check if A comes from one of C, D, E, F.
4472 for (unsigned Half = 0; Half != 4; ++Half) {
4473 if (isSequentialOrUndefInRange(Mask, 0, HalfSize, Half*HalfSize)) {
4479 // Check if B comes from one of C, D, E, F.
4480 for (unsigned Half = 0; Half != 4; ++Half) {
4481 if (isSequentialOrUndefInRange(Mask, HalfSize, HalfSize, Half*HalfSize)) {
4487 return MatchA && MatchB;
4490 /// getShuffleVPERM2X128Immediate - Return the appropriate immediate to shuffle
4491 /// the specified VECTOR_MASK mask with VPERM2F128/VPERM2I128 instructions.
4492 static unsigned getShuffleVPERM2X128Immediate(ShuffleVectorSDNode *SVOp) {
4493 MVT VT = SVOp->getSimpleValueType(0);
4495 unsigned HalfSize = VT.getVectorNumElements()/2;
4497 unsigned FstHalf = 0, SndHalf = 0;
4498 for (unsigned i = 0; i < HalfSize; ++i) {
4499 if (SVOp->getMaskElt(i) > 0) {
4500 FstHalf = SVOp->getMaskElt(i)/HalfSize;
4504 for (unsigned i = HalfSize; i < HalfSize*2; ++i) {
4505 if (SVOp->getMaskElt(i) > 0) {
4506 SndHalf = SVOp->getMaskElt(i)/HalfSize;
4511 return (FstHalf | (SndHalf << 4));
4514 // Symetric in-lane mask. Each lane has 4 elements (for imm8)
4515 static bool isPermImmMask(ArrayRef<int> Mask, MVT VT, unsigned& Imm8) {
4516 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
4520 unsigned NumElts = VT.getVectorNumElements();
4522 if (VT.is128BitVector() || (VT.is256BitVector() && EltSize == 64)) {
4523 for (unsigned i = 0; i != NumElts; ++i) {
4526 Imm8 |= Mask[i] << (i*2);
4531 unsigned LaneSize = 4;
4532 SmallVector<int, 4> MaskVal(LaneSize, -1);
4534 for (unsigned l = 0; l != NumElts; l += LaneSize) {
4535 for (unsigned i = 0; i != LaneSize; ++i) {
4536 if (!isUndefOrInRange(Mask[i+l], l, l+LaneSize))
4540 if (MaskVal[i] < 0) {
4541 MaskVal[i] = Mask[i+l] - l;
4542 Imm8 |= MaskVal[i] << (i*2);
4545 if (Mask[i+l] != (signed)(MaskVal[i]+l))
4552 /// isVPERMILPMask - Return true if the specified VECTOR_SHUFFLE operand
4553 /// specifies a shuffle of elements that is suitable for input to VPERMILPD*.
4554 /// Note that VPERMIL mask matching is different depending whether theunderlying
4555 /// type is 32 or 64. In the VPERMILPS the high half of the mask should point
4556 /// to the same elements of the low, but to the higher half of the source.
4557 /// In VPERMILPD the two lanes could be shuffled independently of each other
4558 /// with the same restriction that lanes can't be crossed. Also handles PSHUFDY.
4559 static bool isVPERMILPMask(ArrayRef<int> Mask, MVT VT) {
4560 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
4561 if (VT.getSizeInBits() < 256 || EltSize < 32)
4563 bool symetricMaskRequired = (EltSize == 32);
4564 unsigned NumElts = VT.getVectorNumElements();
4566 unsigned NumLanes = VT.getSizeInBits()/128;
4567 unsigned LaneSize = NumElts/NumLanes;
4568 // 2 or 4 elements in one lane
4570 SmallVector<int, 4> ExpectedMaskVal(LaneSize, -1);
4571 for (unsigned l = 0; l != NumElts; l += LaneSize) {
4572 for (unsigned i = 0; i != LaneSize; ++i) {
4573 if (!isUndefOrInRange(Mask[i+l], l, l+LaneSize))
4575 if (symetricMaskRequired) {
4576 if (ExpectedMaskVal[i] < 0 && Mask[i+l] >= 0) {
4577 ExpectedMaskVal[i] = Mask[i+l] - l;
4580 if (!isUndefOrEqual(Mask[i+l], ExpectedMaskVal[i]+l))
4588 /// isCommutedMOVLMask - Returns true if the shuffle mask is except the reverse
4589 /// of what x86 movss want. X86 movs requires the lowest element to be lowest
4590 /// element of vector 2 and the other elements to come from vector 1 in order.
4591 static bool isCommutedMOVLMask(ArrayRef<int> Mask, MVT VT,
4592 bool V2IsSplat = false, bool V2IsUndef = false) {
4593 if (!VT.is128BitVector())
4596 unsigned NumOps = VT.getVectorNumElements();
4597 if (NumOps != 2 && NumOps != 4 && NumOps != 8 && NumOps != 16)
4600 if (!isUndefOrEqual(Mask[0], 0))
4603 for (unsigned i = 1; i != NumOps; ++i)
4604 if (!(isUndefOrEqual(Mask[i], i+NumOps) ||
4605 (V2IsUndef && isUndefOrInRange(Mask[i], NumOps, NumOps*2)) ||
4606 (V2IsSplat && isUndefOrEqual(Mask[i], NumOps))))
4612 /// isMOVSHDUPMask - Return true if the specified VECTOR_SHUFFLE operand
4613 /// specifies a shuffle of elements that is suitable for input to MOVSHDUP.
4614 /// Masks to match: <1, 1, 3, 3> or <1, 1, 3, 3, 5, 5, 7, 7>
4615 static bool isMOVSHDUPMask(ArrayRef<int> Mask, MVT VT,
4616 const X86Subtarget *Subtarget) {
4617 if (!Subtarget->hasSSE3())
4620 unsigned NumElems = VT.getVectorNumElements();
4622 if ((VT.is128BitVector() && NumElems != 4) ||
4623 (VT.is256BitVector() && NumElems != 8) ||
4624 (VT.is512BitVector() && NumElems != 16))
4627 // "i+1" is the value the indexed mask element must have
4628 for (unsigned i = 0; i != NumElems; i += 2)
4629 if (!isUndefOrEqual(Mask[i], i+1) ||
4630 !isUndefOrEqual(Mask[i+1], i+1))
4636 /// isMOVSLDUPMask - Return true if the specified VECTOR_SHUFFLE operand
4637 /// specifies a shuffle of elements that is suitable for input to MOVSLDUP.
4638 /// Masks to match: <0, 0, 2, 2> or <0, 0, 2, 2, 4, 4, 6, 6>
4639 static bool isMOVSLDUPMask(ArrayRef<int> Mask, MVT VT,
4640 const X86Subtarget *Subtarget) {
4641 if (!Subtarget->hasSSE3())
4644 unsigned NumElems = VT.getVectorNumElements();
4646 if ((VT.is128BitVector() && NumElems != 4) ||
4647 (VT.is256BitVector() && NumElems != 8) ||
4648 (VT.is512BitVector() && NumElems != 16))
4651 // "i" is the value the indexed mask element must have
4652 for (unsigned i = 0; i != NumElems; i += 2)
4653 if (!isUndefOrEqual(Mask[i], i) ||
4654 !isUndefOrEqual(Mask[i+1], i))
4660 /// isMOVDDUPYMask - Return true if the specified VECTOR_SHUFFLE operand
4661 /// specifies a shuffle of elements that is suitable for input to 256-bit
4662 /// version of MOVDDUP.
4663 static bool isMOVDDUPYMask(ArrayRef<int> Mask, MVT VT, bool HasFp256) {
4664 if (!HasFp256 || !VT.is256BitVector())
4667 unsigned NumElts = VT.getVectorNumElements();
4671 for (unsigned i = 0; i != NumElts/2; ++i)
4672 if (!isUndefOrEqual(Mask[i], 0))
4674 for (unsigned i = NumElts/2; i != NumElts; ++i)
4675 if (!isUndefOrEqual(Mask[i], NumElts/2))
4680 /// isMOVDDUPMask - Return true if the specified VECTOR_SHUFFLE operand
4681 /// specifies a shuffle of elements that is suitable for input to 128-bit
4682 /// version of MOVDDUP.
4683 static bool isMOVDDUPMask(ArrayRef<int> Mask, MVT VT) {
4684 if (!VT.is128BitVector())
4687 unsigned e = VT.getVectorNumElements() / 2;
4688 for (unsigned i = 0; i != e; ++i)
4689 if (!isUndefOrEqual(Mask[i], i))
4691 for (unsigned i = 0; i != e; ++i)
4692 if (!isUndefOrEqual(Mask[e+i], i))
4697 /// isVEXTRACTIndex - Return true if the specified
4698 /// EXTRACT_SUBVECTOR operand specifies a vector extract that is
4699 /// suitable for instruction that extract 128 or 256 bit vectors
4700 static bool isVEXTRACTIndex(SDNode *N, unsigned vecWidth) {
4701 assert((vecWidth == 128 || vecWidth == 256) && "Unexpected vector width");
4702 if (!isa<ConstantSDNode>(N->getOperand(1).getNode()))
4705 // The index should be aligned on a vecWidth-bit boundary.
4707 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
4709 MVT VT = N->getSimpleValueType(0);
4710 unsigned ElSize = VT.getVectorElementType().getSizeInBits();
4711 bool Result = (Index * ElSize) % vecWidth == 0;
4716 /// isVINSERTIndex - Return true if the specified INSERT_SUBVECTOR
4717 /// operand specifies a subvector insert that is suitable for input to
4718 /// insertion of 128 or 256-bit subvectors
4719 static bool isVINSERTIndex(SDNode *N, unsigned vecWidth) {
4720 assert((vecWidth == 128 || vecWidth == 256) && "Unexpected vector width");
4721 if (!isa<ConstantSDNode>(N->getOperand(2).getNode()))
4723 // The index should be aligned on a vecWidth-bit boundary.
4725 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
4727 MVT VT = N->getSimpleValueType(0);
4728 unsigned ElSize = VT.getVectorElementType().getSizeInBits();
4729 bool Result = (Index * ElSize) % vecWidth == 0;
4734 bool X86::isVINSERT128Index(SDNode *N) {
4735 return isVINSERTIndex(N, 128);
4738 bool X86::isVINSERT256Index(SDNode *N) {
4739 return isVINSERTIndex(N, 256);
4742 bool X86::isVEXTRACT128Index(SDNode *N) {
4743 return isVEXTRACTIndex(N, 128);
4746 bool X86::isVEXTRACT256Index(SDNode *N) {
4747 return isVEXTRACTIndex(N, 256);
4750 /// getShuffleSHUFImmediate - Return the appropriate immediate to shuffle
4751 /// the specified VECTOR_SHUFFLE mask with PSHUF* and SHUFP* instructions.
4752 /// Handles 128-bit and 256-bit.
4753 static unsigned getShuffleSHUFImmediate(ShuffleVectorSDNode *N) {
4754 MVT VT = N->getSimpleValueType(0);
4756 assert((VT.getSizeInBits() >= 128) &&
4757 "Unsupported vector type for PSHUF/SHUFP");
4759 // Handle 128 and 256-bit vector lengths. AVX defines PSHUF/SHUFP to operate
4760 // independently on 128-bit lanes.
4761 unsigned NumElts = VT.getVectorNumElements();
4762 unsigned NumLanes = VT.getSizeInBits()/128;
4763 unsigned NumLaneElts = NumElts/NumLanes;
4765 assert((NumLaneElts == 2 || NumLaneElts == 4 || NumLaneElts == 8) &&
4766 "Only supports 2, 4 or 8 elements per lane");
4768 unsigned Shift = (NumLaneElts >= 4) ? 1 : 0;
4770 for (unsigned i = 0; i != NumElts; ++i) {
4771 int Elt = N->getMaskElt(i);
4772 if (Elt < 0) continue;
4773 Elt &= NumLaneElts - 1;
4774 unsigned ShAmt = (i << Shift) % 8;
4775 Mask |= Elt << ShAmt;
4781 /// getShufflePSHUFHWImmediate - Return the appropriate immediate to shuffle
4782 /// the specified VECTOR_SHUFFLE mask with the PSHUFHW instruction.
4783 static unsigned getShufflePSHUFHWImmediate(ShuffleVectorSDNode *N) {
4784 MVT VT = N->getSimpleValueType(0);
4786 assert((VT == MVT::v8i16 || VT == MVT::v16i16) &&
4787 "Unsupported vector type for PSHUFHW");
4789 unsigned NumElts = VT.getVectorNumElements();
4792 for (unsigned l = 0; l != NumElts; l += 8) {
4793 // 8 nodes per lane, but we only care about the last 4.
4794 for (unsigned i = 0; i < 4; ++i) {
4795 int Elt = N->getMaskElt(l+i+4);
4796 if (Elt < 0) continue;
4797 Elt &= 0x3; // only 2-bits.
4798 Mask |= Elt << (i * 2);
4805 /// getShufflePSHUFLWImmediate - Return the appropriate immediate to shuffle
4806 /// the specified VECTOR_SHUFFLE mask with the PSHUFLW instruction.
4807 static unsigned getShufflePSHUFLWImmediate(ShuffleVectorSDNode *N) {
4808 MVT VT = N->getSimpleValueType(0);
4810 assert((VT == MVT::v8i16 || VT == MVT::v16i16) &&
4811 "Unsupported vector type for PSHUFHW");
4813 unsigned NumElts = VT.getVectorNumElements();
4816 for (unsigned l = 0; l != NumElts; l += 8) {
4817 // 8 nodes per lane, but we only care about the first 4.
4818 for (unsigned i = 0; i < 4; ++i) {
4819 int Elt = N->getMaskElt(l+i);
4820 if (Elt < 0) continue;
4821 Elt &= 0x3; // only 2-bits
4822 Mask |= Elt << (i * 2);
4829 /// \brief Return the appropriate immediate to shuffle the specified
4830 /// VECTOR_SHUFFLE mask with the PALIGNR (if InterLane is false) or with
4831 /// VALIGN (if Interlane is true) instructions.
4832 static unsigned getShuffleAlignrImmediate(ShuffleVectorSDNode *SVOp,
4834 MVT VT = SVOp->getSimpleValueType(0);
4835 unsigned EltSize = InterLane ? 1 :
4836 VT.getVectorElementType().getSizeInBits() >> 3;
4838 unsigned NumElts = VT.getVectorNumElements();
4839 unsigned NumLanes = VT.is512BitVector() ? 1 : VT.getSizeInBits()/128;
4840 unsigned NumLaneElts = NumElts/NumLanes;
4844 for (i = 0; i != NumElts; ++i) {
4845 Val = SVOp->getMaskElt(i);
4849 if (Val >= (int)NumElts)
4850 Val -= NumElts - NumLaneElts;
4852 assert(Val - i > 0 && "PALIGNR imm should be positive");
4853 return (Val - i) * EltSize;
4856 /// \brief Return the appropriate immediate to shuffle the specified
4857 /// VECTOR_SHUFFLE mask with the PALIGNR instruction.
4858 static unsigned getShufflePALIGNRImmediate(ShuffleVectorSDNode *SVOp) {
4859 return getShuffleAlignrImmediate(SVOp, false);
4862 /// \brief Return the appropriate immediate to shuffle the specified
4863 /// VECTOR_SHUFFLE mask with the VALIGN instruction.
4864 static unsigned getShuffleVALIGNImmediate(ShuffleVectorSDNode *SVOp) {
4865 return getShuffleAlignrImmediate(SVOp, true);
4869 static unsigned getExtractVEXTRACTImmediate(SDNode *N, unsigned vecWidth) {
4870 assert((vecWidth == 128 || vecWidth == 256) && "Unsupported vector width");
4871 if (!isa<ConstantSDNode>(N->getOperand(1).getNode()))
4872 llvm_unreachable("Illegal extract subvector for VEXTRACT");
4875 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
4877 MVT VecVT = N->getOperand(0).getSimpleValueType();
4878 MVT ElVT = VecVT.getVectorElementType();
4880 unsigned NumElemsPerChunk = vecWidth / ElVT.getSizeInBits();
4881 return Index / NumElemsPerChunk;
4884 static unsigned getInsertVINSERTImmediate(SDNode *N, unsigned vecWidth) {
4885 assert((vecWidth == 128 || vecWidth == 256) && "Unsupported vector width");
4886 if (!isa<ConstantSDNode>(N->getOperand(2).getNode()))
4887 llvm_unreachable("Illegal insert subvector for VINSERT");
4890 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
4892 MVT VecVT = N->getSimpleValueType(0);
4893 MVT ElVT = VecVT.getVectorElementType();
4895 unsigned NumElemsPerChunk = vecWidth / ElVT.getSizeInBits();
4896 return Index / NumElemsPerChunk;
4899 /// getExtractVEXTRACT128Immediate - Return the appropriate immediate
4900 /// to extract the specified EXTRACT_SUBVECTOR index with VEXTRACTF128
4901 /// and VINSERTI128 instructions.
4902 unsigned X86::getExtractVEXTRACT128Immediate(SDNode *N) {
4903 return getExtractVEXTRACTImmediate(N, 128);
4906 /// getExtractVEXTRACT256Immediate - Return the appropriate immediate
4907 /// to extract the specified EXTRACT_SUBVECTOR index with VEXTRACTF64x4
4908 /// and VINSERTI64x4 instructions.
4909 unsigned X86::getExtractVEXTRACT256Immediate(SDNode *N) {
4910 return getExtractVEXTRACTImmediate(N, 256);
4913 /// getInsertVINSERT128Immediate - Return the appropriate immediate
4914 /// to insert at the specified INSERT_SUBVECTOR index with VINSERTF128
4915 /// and VINSERTI128 instructions.
4916 unsigned X86::getInsertVINSERT128Immediate(SDNode *N) {
4917 return getInsertVINSERTImmediate(N, 128);
4920 /// getInsertVINSERT256Immediate - Return the appropriate immediate
4921 /// to insert at the specified INSERT_SUBVECTOR index with VINSERTF46x4
4922 /// and VINSERTI64x4 instructions.
4923 unsigned X86::getInsertVINSERT256Immediate(SDNode *N) {
4924 return getInsertVINSERTImmediate(N, 256);
4927 /// isZero - Returns true if Elt is a constant integer zero
4928 static bool isZero(SDValue V) {
4929 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V);
4930 return C && C->isNullValue();
4933 /// isZeroNode - Returns true if Elt is a constant zero or a floating point
4935 bool X86::isZeroNode(SDValue Elt) {
4938 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Elt))
4939 return CFP->getValueAPF().isPosZero();
4943 /// ShouldXformToMOVHLPS - Return true if the node should be transformed to
4944 /// match movhlps. The lower half elements should come from upper half of
4945 /// V1 (and in order), and the upper half elements should come from the upper
4946 /// half of V2 (and in order).
4947 static bool ShouldXformToMOVHLPS(ArrayRef<int> Mask, MVT VT) {
4948 if (!VT.is128BitVector())
4950 if (VT.getVectorNumElements() != 4)
4952 for (unsigned i = 0, e = 2; i != e; ++i)
4953 if (!isUndefOrEqual(Mask[i], i+2))
4955 for (unsigned i = 2; i != 4; ++i)
4956 if (!isUndefOrEqual(Mask[i], i+4))
4961 /// isScalarLoadToVector - Returns true if the node is a scalar load that
4962 /// is promoted to a vector. It also returns the LoadSDNode by reference if
4964 static bool isScalarLoadToVector(SDNode *N, LoadSDNode **LD = nullptr) {
4965 if (N->getOpcode() != ISD::SCALAR_TO_VECTOR)
4967 N = N->getOperand(0).getNode();
4968 if (!ISD::isNON_EXTLoad(N))
4971 *LD = cast<LoadSDNode>(N);
4975 // Test whether the given value is a vector value which will be legalized
4977 static bool WillBeConstantPoolLoad(SDNode *N) {
4978 if (N->getOpcode() != ISD::BUILD_VECTOR)
4981 // Check for any non-constant elements.
4982 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
4983 switch (N->getOperand(i).getNode()->getOpcode()) {
4985 case ISD::ConstantFP:
4992 // Vectors of all-zeros and all-ones are materialized with special
4993 // instructions rather than being loaded.
4994 return !ISD::isBuildVectorAllZeros(N) &&
4995 !ISD::isBuildVectorAllOnes(N);
4998 /// ShouldXformToMOVLP{S|D} - Return true if the node should be transformed to
4999 /// match movlp{s|d}. The lower half elements should come from lower half of
5000 /// V1 (and in order), and the upper half elements should come from the upper
5001 /// half of V2 (and in order). And since V1 will become the source of the
5002 /// MOVLP, it must be either a vector load or a scalar load to vector.
5003 static bool ShouldXformToMOVLP(SDNode *V1, SDNode *V2,
5004 ArrayRef<int> Mask, MVT VT) {
5005 if (!VT.is128BitVector())
5008 if (!ISD::isNON_EXTLoad(V1) && !isScalarLoadToVector(V1))
5010 // Is V2 is a vector load, don't do this transformation. We will try to use
5011 // load folding shufps op.
5012 if (ISD::isNON_EXTLoad(V2) || WillBeConstantPoolLoad(V2))
5015 unsigned NumElems = VT.getVectorNumElements();
5017 if (NumElems != 2 && NumElems != 4)
5019 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
5020 if (!isUndefOrEqual(Mask[i], i))
5022 for (unsigned i = NumElems/2, e = NumElems; i != e; ++i)
5023 if (!isUndefOrEqual(Mask[i], i+NumElems))
5028 /// isZeroShuffle - Returns true if N is a VECTOR_SHUFFLE that can be resolved
5029 /// to an zero vector.
5030 /// FIXME: move to dag combiner / method on ShuffleVectorSDNode
5031 static bool isZeroShuffle(ShuffleVectorSDNode *N) {
5032 SDValue V1 = N->getOperand(0);
5033 SDValue V2 = N->getOperand(1);
5034 unsigned NumElems = N->getValueType(0).getVectorNumElements();
5035 for (unsigned i = 0; i != NumElems; ++i) {
5036 int Idx = N->getMaskElt(i);
5037 if (Idx >= (int)NumElems) {
5038 unsigned Opc = V2.getOpcode();
5039 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V2.getNode()))
5041 if (Opc != ISD::BUILD_VECTOR ||
5042 !X86::isZeroNode(V2.getOperand(Idx-NumElems)))
5044 } else if (Idx >= 0) {
5045 unsigned Opc = V1.getOpcode();
5046 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V1.getNode()))
5048 if (Opc != ISD::BUILD_VECTOR ||
5049 !X86::isZeroNode(V1.getOperand(Idx)))
5056 /// getZeroVector - Returns a vector of specified type with all zero elements.
5058 static SDValue getZeroVector(EVT VT, const X86Subtarget *Subtarget,
5059 SelectionDAG &DAG, SDLoc dl) {
5060 assert(VT.isVector() && "Expected a vector type");
5062 // Always build SSE zero vectors as <4 x i32> bitcasted
5063 // to their dest type. This ensures they get CSE'd.
5065 if (VT.is128BitVector()) { // SSE
5066 if (Subtarget->hasSSE2()) { // SSE2
5067 SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
5068 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
5070 SDValue Cst = DAG.getTargetConstantFP(+0.0, MVT::f32);
5071 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4f32, Cst, Cst, Cst, Cst);
5073 } else if (VT.is256BitVector()) { // AVX
5074 if (Subtarget->hasInt256()) { // AVX2
5075 SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
5076 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
5077 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops);
5079 // 256-bit logic and arithmetic instructions in AVX are all
5080 // floating-point, no support for integer ops. Emit fp zeroed vectors.
5081 SDValue Cst = DAG.getTargetConstantFP(+0.0, MVT::f32);
5082 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
5083 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8f32, Ops);
5085 } else if (VT.is512BitVector()) { // AVX-512
5086 SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
5087 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst,
5088 Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
5089 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v16i32, Ops);
5090 } else if (VT.getScalarType() == MVT::i1) {
5091 assert(VT.getVectorNumElements() <= 16 && "Unexpected vector type");
5092 SDValue Cst = DAG.getTargetConstant(0, MVT::i1);
5093 SmallVector<SDValue, 16> Ops(VT.getVectorNumElements(), Cst);
5094 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
5096 llvm_unreachable("Unexpected vector type");
5098 return DAG.getNode(ISD::BITCAST, dl, VT, Vec);
5101 /// getOnesVector - Returns a vector of specified type with all bits set.
5102 /// Always build ones vectors as <4 x i32> or <8 x i32>. For 256-bit types with
5103 /// no AVX2 supprt, use two <4 x i32> inserted in a <8 x i32> appropriately.
5104 /// Then bitcast to their original type, ensuring they get CSE'd.
5105 static SDValue getOnesVector(MVT VT, bool HasInt256, SelectionDAG &DAG,
5107 assert(VT.isVector() && "Expected a vector type");
5109 SDValue Cst = DAG.getTargetConstant(~0U, MVT::i32);
5111 if (VT.is256BitVector()) {
5112 if (HasInt256) { // AVX2
5113 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
5114 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops);
5116 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
5117 Vec = Concat128BitVectors(Vec, Vec, MVT::v8i32, 8, DAG, dl);
5119 } else if (VT.is128BitVector()) {
5120 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
5122 llvm_unreachable("Unexpected vector type");
5124 return DAG.getNode(ISD::BITCAST, dl, VT, Vec);
5127 /// NormalizeMask - V2 is a splat, modify the mask (if needed) so all elements
5128 /// that point to V2 points to its first element.
5129 static void NormalizeMask(SmallVectorImpl<int> &Mask, unsigned NumElems) {
5130 for (unsigned i = 0; i != NumElems; ++i) {
5131 if (Mask[i] > (int)NumElems) {
5137 /// getMOVLMask - Returns a vector_shuffle mask for an movs{s|d}, movd
5138 /// operation of specified width.
5139 static SDValue getMOVL(SelectionDAG &DAG, SDLoc dl, EVT VT, SDValue V1,
5141 unsigned NumElems = VT.getVectorNumElements();
5142 SmallVector<int, 8> Mask;
5143 Mask.push_back(NumElems);
5144 for (unsigned i = 1; i != NumElems; ++i)
5146 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
5149 /// getUnpackl - Returns a vector_shuffle node for an unpackl operation.
5150 static SDValue getUnpackl(SelectionDAG &DAG, SDLoc dl, MVT VT, SDValue V1,
5152 unsigned NumElems = VT.getVectorNumElements();
5153 SmallVector<int, 8> Mask;
5154 for (unsigned i = 0, e = NumElems/2; i != e; ++i) {
5156 Mask.push_back(i + NumElems);
5158 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
5161 /// getUnpackh - Returns a vector_shuffle node for an unpackh operation.
5162 static SDValue getUnpackh(SelectionDAG &DAG, SDLoc dl, MVT VT, SDValue V1,
5164 unsigned NumElems = VT.getVectorNumElements();
5165 SmallVector<int, 8> Mask;
5166 for (unsigned i = 0, Half = NumElems/2; i != Half; ++i) {
5167 Mask.push_back(i + Half);
5168 Mask.push_back(i + NumElems + Half);
5170 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
5173 // PromoteSplati8i16 - All i16 and i8 vector types can't be used directly by
5174 // a generic shuffle instruction because the target has no such instructions.
5175 // Generate shuffles which repeat i16 and i8 several times until they can be
5176 // represented by v4f32 and then be manipulated by target suported shuffles.
5177 static SDValue PromoteSplati8i16(SDValue V, SelectionDAG &DAG, int &EltNo) {
5178 MVT VT = V.getSimpleValueType();
5179 int NumElems = VT.getVectorNumElements();
5182 while (NumElems > 4) {
5183 if (EltNo < NumElems/2) {
5184 V = getUnpackl(DAG, dl, VT, V, V);
5186 V = getUnpackh(DAG, dl, VT, V, V);
5187 EltNo -= NumElems/2;
5194 /// getLegalSplat - Generate a legal splat with supported x86 shuffles
5195 static SDValue getLegalSplat(SelectionDAG &DAG, SDValue V, int EltNo) {
5196 MVT VT = V.getSimpleValueType();
5199 if (VT.is128BitVector()) {
5200 V = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V);
5201 int SplatMask[4] = { EltNo, EltNo, EltNo, EltNo };
5202 V = DAG.getVectorShuffle(MVT::v4f32, dl, V, DAG.getUNDEF(MVT::v4f32),
5204 } else if (VT.is256BitVector()) {
5205 // To use VPERMILPS to splat scalars, the second half of indicies must
5206 // refer to the higher part, which is a duplication of the lower one,
5207 // because VPERMILPS can only handle in-lane permutations.
5208 int SplatMask[8] = { EltNo, EltNo, EltNo, EltNo,
5209 EltNo+4, EltNo+4, EltNo+4, EltNo+4 };
5211 V = DAG.getNode(ISD::BITCAST, dl, MVT::v8f32, V);
5212 V = DAG.getVectorShuffle(MVT::v8f32, dl, V, DAG.getUNDEF(MVT::v8f32),
5215 llvm_unreachable("Vector size not supported");
5217 return DAG.getNode(ISD::BITCAST, dl, VT, V);
5220 /// PromoteSplat - Splat is promoted to target supported vector shuffles.
5221 static SDValue PromoteSplat(ShuffleVectorSDNode *SV, SelectionDAG &DAG) {
5222 MVT SrcVT = SV->getSimpleValueType(0);
5223 SDValue V1 = SV->getOperand(0);
5226 int EltNo = SV->getSplatIndex();
5227 int NumElems = SrcVT.getVectorNumElements();
5228 bool Is256BitVec = SrcVT.is256BitVector();
5230 assert(((SrcVT.is128BitVector() && NumElems > 4) || Is256BitVec) &&
5231 "Unknown how to promote splat for type");
5233 // Extract the 128-bit part containing the splat element and update
5234 // the splat element index when it refers to the higher register.
5236 V1 = Extract128BitVector(V1, EltNo, DAG, dl);
5237 if (EltNo >= NumElems/2)
5238 EltNo -= NumElems/2;
5241 // All i16 and i8 vector types can't be used directly by a generic shuffle
5242 // instruction because the target has no such instruction. Generate shuffles
5243 // which repeat i16 and i8 several times until they fit in i32, and then can
5244 // be manipulated by target suported shuffles.
5245 MVT EltVT = SrcVT.getVectorElementType();
5246 if (EltVT == MVT::i8 || EltVT == MVT::i16)
5247 V1 = PromoteSplati8i16(V1, DAG, EltNo);
5249 // Recreate the 256-bit vector and place the same 128-bit vector
5250 // into the low and high part. This is necessary because we want
5251 // to use VPERM* to shuffle the vectors
5253 V1 = DAG.getNode(ISD::CONCAT_VECTORS, dl, SrcVT, V1, V1);
5256 return getLegalSplat(DAG, V1, EltNo);
5259 /// getShuffleVectorZeroOrUndef - Return a vector_shuffle of the specified
5260 /// vector of zero or undef vector. This produces a shuffle where the low
5261 /// element of V2 is swizzled into the zero/undef vector, landing at element
5262 /// Idx. This produces a shuffle mask like 4,1,2,3 (idx=0) or 0,1,2,4 (idx=3).
5263 static SDValue getShuffleVectorZeroOrUndef(SDValue V2, unsigned Idx,
5265 const X86Subtarget *Subtarget,
5266 SelectionDAG &DAG) {
5267 MVT VT = V2.getSimpleValueType();
5269 ? getZeroVector(VT, Subtarget, DAG, SDLoc(V2)) : DAG.getUNDEF(VT);
5270 unsigned NumElems = VT.getVectorNumElements();
5271 SmallVector<int, 16> MaskVec;
5272 for (unsigned i = 0; i != NumElems; ++i)
5273 // If this is the insertion idx, put the low elt of V2 here.
5274 MaskVec.push_back(i == Idx ? NumElems : i);
5275 return DAG.getVectorShuffle(VT, SDLoc(V2), V1, V2, &MaskVec[0]);
5278 /// getTargetShuffleMask - Calculates the shuffle mask corresponding to the
5279 /// target specific opcode. Returns true if the Mask could be calculated. Sets
5280 /// IsUnary to true if only uses one source. Note that this will set IsUnary for
5281 /// shuffles which use a single input multiple times, and in those cases it will
5282 /// adjust the mask to only have indices within that single input.
5283 static bool getTargetShuffleMask(SDNode *N, MVT VT,
5284 SmallVectorImpl<int> &Mask, bool &IsUnary) {
5285 unsigned NumElems = VT.getVectorNumElements();
5289 bool IsFakeUnary = false;
5290 switch(N->getOpcode()) {
5292 ImmN = N->getOperand(N->getNumOperands()-1);
5293 DecodeSHUFPMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5294 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
5296 case X86ISD::UNPCKH:
5297 DecodeUNPCKHMask(VT, Mask);
5298 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
5300 case X86ISD::UNPCKL:
5301 DecodeUNPCKLMask(VT, Mask);
5302 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
5304 case X86ISD::MOVHLPS:
5305 DecodeMOVHLPSMask(NumElems, Mask);
5306 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
5308 case X86ISD::MOVLHPS:
5309 DecodeMOVLHPSMask(NumElems, Mask);
5310 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
5312 case X86ISD::PALIGNR:
5313 ImmN = N->getOperand(N->getNumOperands()-1);
5314 DecodePALIGNRMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5316 case X86ISD::PSHUFD:
5317 case X86ISD::VPERMILPI:
5318 ImmN = N->getOperand(N->getNumOperands()-1);
5319 DecodePSHUFMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5322 case X86ISD::PSHUFHW:
5323 ImmN = N->getOperand(N->getNumOperands()-1);
5324 DecodePSHUFHWMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5327 case X86ISD::PSHUFLW:
5328 ImmN = N->getOperand(N->getNumOperands()-1);
5329 DecodePSHUFLWMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5332 case X86ISD::PSHUFB: {
5334 SDValue MaskNode = N->getOperand(1);
5335 while (MaskNode->getOpcode() == ISD::BITCAST)
5336 MaskNode = MaskNode->getOperand(0);
5338 if (MaskNode->getOpcode() == ISD::BUILD_VECTOR) {
5339 // If we have a build-vector, then things are easy.
5340 EVT VT = MaskNode.getValueType();
5341 assert(VT.isVector() &&
5342 "Can't produce a non-vector with a build_vector!");
5343 if (!VT.isInteger())
5346 int NumBytesPerElement = VT.getVectorElementType().getSizeInBits() / 8;
5348 SmallVector<uint64_t, 32> RawMask;
5349 for (int i = 0, e = MaskNode->getNumOperands(); i < e; ++i) {
5350 auto *CN = dyn_cast<ConstantSDNode>(MaskNode->getOperand(i));
5353 APInt MaskElement = CN->getAPIntValue();
5355 // We now have to decode the element which could be any integer size and
5356 // extract each byte of it.
5357 for (int j = 0; j < NumBytesPerElement; ++j) {
5358 // Note that this is x86 and so always little endian: the low byte is
5359 // the first byte of the mask.
5360 RawMask.push_back(MaskElement.getLoBits(8).getZExtValue());
5361 MaskElement = MaskElement.lshr(8);
5364 DecodePSHUFBMask(RawMask, Mask);
5368 auto *MaskLoad = dyn_cast<LoadSDNode>(MaskNode);
5372 SDValue Ptr = MaskLoad->getBasePtr();
5373 if (Ptr->getOpcode() == X86ISD::Wrapper)
5374 Ptr = Ptr->getOperand(0);
5376 auto *MaskCP = dyn_cast<ConstantPoolSDNode>(Ptr);
5377 if (!MaskCP || MaskCP->isMachineConstantPoolEntry())
5380 if (auto *C = dyn_cast<ConstantDataSequential>(MaskCP->getConstVal())) {
5381 // FIXME: Support AVX-512 here.
5382 if (!C->getType()->isVectorTy() ||
5383 (C->getNumElements() != 16 && C->getNumElements() != 32))
5386 assert(C->getType()->isVectorTy() && "Expected a vector constant.");
5387 DecodePSHUFBMask(C, Mask);
5393 case X86ISD::VPERMI:
5394 ImmN = N->getOperand(N->getNumOperands()-1);
5395 DecodeVPERMMask(cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5399 case X86ISD::MOVSD: {
5400 // The index 0 always comes from the first element of the second source,
5401 // this is why MOVSS and MOVSD are used in the first place. The other
5402 // elements come from the other positions of the first source vector
5403 Mask.push_back(NumElems);
5404 for (unsigned i = 1; i != NumElems; ++i) {
5409 case X86ISD::VPERM2X128:
5410 ImmN = N->getOperand(N->getNumOperands()-1);
5411 DecodeVPERM2X128Mask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5412 if (Mask.empty()) return false;
5414 case X86ISD::MOVSLDUP:
5415 DecodeMOVSLDUPMask(VT, Mask);
5417 case X86ISD::MOVSHDUP:
5418 DecodeMOVSHDUPMask(VT, Mask);
5420 case X86ISD::MOVDDUP:
5421 case X86ISD::MOVLHPD:
5422 case X86ISD::MOVLPD:
5423 case X86ISD::MOVLPS:
5424 // Not yet implemented
5426 default: llvm_unreachable("unknown target shuffle node");
5429 // If we have a fake unary shuffle, the shuffle mask is spread across two
5430 // inputs that are actually the same node. Re-map the mask to always point
5431 // into the first input.
5434 if (M >= (int)Mask.size())
5440 /// getShuffleScalarElt - Returns the scalar element that will make up the ith
5441 /// element of the result of the vector shuffle.
5442 static SDValue getShuffleScalarElt(SDNode *N, unsigned Index, SelectionDAG &DAG,
5445 return SDValue(); // Limit search depth.
5447 SDValue V = SDValue(N, 0);
5448 EVT VT = V.getValueType();
5449 unsigned Opcode = V.getOpcode();
5451 // Recurse into ISD::VECTOR_SHUFFLE node to find scalars.
5452 if (const ShuffleVectorSDNode *SV = dyn_cast<ShuffleVectorSDNode>(N)) {
5453 int Elt = SV->getMaskElt(Index);
5456 return DAG.getUNDEF(VT.getVectorElementType());
5458 unsigned NumElems = VT.getVectorNumElements();
5459 SDValue NewV = (Elt < (int)NumElems) ? SV->getOperand(0)
5460 : SV->getOperand(1);
5461 return getShuffleScalarElt(NewV.getNode(), Elt % NumElems, DAG, Depth+1);
5464 // Recurse into target specific vector shuffles to find scalars.
5465 if (isTargetShuffle(Opcode)) {
5466 MVT ShufVT = V.getSimpleValueType();
5467 unsigned NumElems = ShufVT.getVectorNumElements();
5468 SmallVector<int, 16> ShuffleMask;
5471 if (!getTargetShuffleMask(N, ShufVT, ShuffleMask, IsUnary))
5474 int Elt = ShuffleMask[Index];
5476 return DAG.getUNDEF(ShufVT.getVectorElementType());
5478 SDValue NewV = (Elt < (int)NumElems) ? N->getOperand(0)
5480 return getShuffleScalarElt(NewV.getNode(), Elt % NumElems, DAG,
5484 // Actual nodes that may contain scalar elements
5485 if (Opcode == ISD::BITCAST) {
5486 V = V.getOperand(0);
5487 EVT SrcVT = V.getValueType();
5488 unsigned NumElems = VT.getVectorNumElements();
5490 if (!SrcVT.isVector() || SrcVT.getVectorNumElements() != NumElems)
5494 if (V.getOpcode() == ISD::SCALAR_TO_VECTOR)
5495 return (Index == 0) ? V.getOperand(0)
5496 : DAG.getUNDEF(VT.getVectorElementType());
5498 if (V.getOpcode() == ISD::BUILD_VECTOR)
5499 return V.getOperand(Index);
5504 /// getNumOfConsecutiveZeros - Return the number of elements of a vector
5505 /// shuffle operation which come from a consecutively from a zero. The
5506 /// search can start in two different directions, from left or right.
5507 /// We count undefs as zeros until PreferredNum is reached.
5508 static unsigned getNumOfConsecutiveZeros(ShuffleVectorSDNode *SVOp,
5509 unsigned NumElems, bool ZerosFromLeft,
5511 unsigned PreferredNum = -1U) {
5512 unsigned NumZeros = 0;
5513 for (unsigned i = 0; i != NumElems; ++i) {
5514 unsigned Index = ZerosFromLeft ? i : NumElems - i - 1;
5515 SDValue Elt = getShuffleScalarElt(SVOp, Index, DAG, 0);
5519 if (X86::isZeroNode(Elt))
5521 else if (Elt.getOpcode() == ISD::UNDEF) // Undef as zero up to PreferredNum.
5522 NumZeros = std::min(NumZeros + 1, PreferredNum);
5530 /// isShuffleMaskConsecutive - Check if the shuffle mask indicies [MaskI, MaskE)
5531 /// correspond consecutively to elements from one of the vector operands,
5532 /// starting from its index OpIdx. Also tell OpNum which source vector operand.
5534 bool isShuffleMaskConsecutive(ShuffleVectorSDNode *SVOp,
5535 unsigned MaskI, unsigned MaskE, unsigned OpIdx,
5536 unsigned NumElems, unsigned &OpNum) {
5537 bool SeenV1 = false;
5538 bool SeenV2 = false;
5540 for (unsigned i = MaskI; i != MaskE; ++i, ++OpIdx) {
5541 int Idx = SVOp->getMaskElt(i);
5542 // Ignore undef indicies
5546 if (Idx < (int)NumElems)
5551 // Only accept consecutive elements from the same vector
5552 if ((Idx % NumElems != OpIdx) || (SeenV1 && SeenV2))
5556 OpNum = SeenV1 ? 0 : 1;
5560 /// isVectorShiftRight - Returns true if the shuffle can be implemented as a
5561 /// logical left shift of a vector.
5562 static bool isVectorShiftRight(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
5563 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
5565 SVOp->getSimpleValueType(0).getVectorNumElements();
5566 unsigned NumZeros = getNumOfConsecutiveZeros(
5567 SVOp, NumElems, false /* check zeros from right */, DAG,
5568 SVOp->getMaskElt(0));
5574 // Considering the elements in the mask that are not consecutive zeros,
5575 // check if they consecutively come from only one of the source vectors.
5577 // V1 = {X, A, B, C} 0
5579 // vector_shuffle V1, V2 <1, 2, 3, X>
5581 if (!isShuffleMaskConsecutive(SVOp,
5582 0, // Mask Start Index
5583 NumElems-NumZeros, // Mask End Index(exclusive)
5584 NumZeros, // Where to start looking in the src vector
5585 NumElems, // Number of elements in vector
5586 OpSrc)) // Which source operand ?
5591 ShVal = SVOp->getOperand(OpSrc);
5595 /// isVectorShiftLeft - Returns true if the shuffle can be implemented as a
5596 /// logical left shift of a vector.
5597 static bool isVectorShiftLeft(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
5598 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
5600 SVOp->getSimpleValueType(0).getVectorNumElements();
5601 unsigned NumZeros = getNumOfConsecutiveZeros(
5602 SVOp, NumElems, true /* check zeros from left */, DAG,
5603 NumElems - SVOp->getMaskElt(NumElems - 1) - 1);
5609 // Considering the elements in the mask that are not consecutive zeros,
5610 // check if they consecutively come from only one of the source vectors.
5612 // 0 { A, B, X, X } = V2
5614 // vector_shuffle V1, V2 <X, X, 4, 5>
5616 if (!isShuffleMaskConsecutive(SVOp,
5617 NumZeros, // Mask Start Index
5618 NumElems, // Mask End Index(exclusive)
5619 0, // Where to start looking in the src vector
5620 NumElems, // Number of elements in vector
5621 OpSrc)) // Which source operand ?
5626 ShVal = SVOp->getOperand(OpSrc);
5630 /// isVectorShift - Returns true if the shuffle can be implemented as a
5631 /// logical left or right shift of a vector.
5632 static bool isVectorShift(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
5633 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
5634 // Although the logic below support any bitwidth size, there are no
5635 // shift instructions which handle more than 128-bit vectors.
5636 if (!SVOp->getSimpleValueType(0).is128BitVector())
5639 if (isVectorShiftLeft(SVOp, DAG, isLeft, ShVal, ShAmt) ||
5640 isVectorShiftRight(SVOp, DAG, isLeft, ShVal, ShAmt))
5646 /// LowerBuildVectorv16i8 - Custom lower build_vector of v16i8.
5648 static SDValue LowerBuildVectorv16i8(SDValue Op, unsigned NonZeros,
5649 unsigned NumNonZero, unsigned NumZero,
5651 const X86Subtarget* Subtarget,
5652 const TargetLowering &TLI) {
5659 for (unsigned i = 0; i < 16; ++i) {
5660 bool ThisIsNonZero = (NonZeros & (1 << i)) != 0;
5661 if (ThisIsNonZero && First) {
5663 V = getZeroVector(MVT::v8i16, Subtarget, DAG, dl);
5665 V = DAG.getUNDEF(MVT::v8i16);
5670 SDValue ThisElt, LastElt;
5671 bool LastIsNonZero = (NonZeros & (1 << (i-1))) != 0;
5672 if (LastIsNonZero) {
5673 LastElt = DAG.getNode(ISD::ZERO_EXTEND, dl,
5674 MVT::i16, Op.getOperand(i-1));
5676 if (ThisIsNonZero) {
5677 ThisElt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, Op.getOperand(i));
5678 ThisElt = DAG.getNode(ISD::SHL, dl, MVT::i16,
5679 ThisElt, DAG.getConstant(8, MVT::i8));
5681 ThisElt = DAG.getNode(ISD::OR, dl, MVT::i16, ThisElt, LastElt);
5685 if (ThisElt.getNode())
5686 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, V, ThisElt,
5687 DAG.getIntPtrConstant(i/2));
5691 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V);
5694 /// LowerBuildVectorv8i16 - Custom lower build_vector of v8i16.
5696 static SDValue LowerBuildVectorv8i16(SDValue Op, unsigned NonZeros,
5697 unsigned NumNonZero, unsigned NumZero,
5699 const X86Subtarget* Subtarget,
5700 const TargetLowering &TLI) {
5707 for (unsigned i = 0; i < 8; ++i) {
5708 bool isNonZero = (NonZeros & (1 << i)) != 0;
5712 V = getZeroVector(MVT::v8i16, Subtarget, DAG, dl);
5714 V = DAG.getUNDEF(MVT::v8i16);
5717 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl,
5718 MVT::v8i16, V, Op.getOperand(i),
5719 DAG.getIntPtrConstant(i));
5726 /// LowerBuildVectorv4x32 - Custom lower build_vector of v4i32 or v4f32.
5727 static SDValue LowerBuildVectorv4x32(SDValue Op, unsigned NumElems,
5728 unsigned NonZeros, unsigned NumNonZero,
5729 unsigned NumZero, SelectionDAG &DAG,
5730 const X86Subtarget *Subtarget,
5731 const TargetLowering &TLI) {
5732 // We know there's at least one non-zero element
5733 unsigned FirstNonZeroIdx = 0;
5734 SDValue FirstNonZero = Op->getOperand(FirstNonZeroIdx);
5735 while (FirstNonZero.getOpcode() == ISD::UNDEF ||
5736 X86::isZeroNode(FirstNonZero)) {
5738 FirstNonZero = Op->getOperand(FirstNonZeroIdx);
5741 if (FirstNonZero.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
5742 !isa<ConstantSDNode>(FirstNonZero.getOperand(1)))
5745 SDValue V = FirstNonZero.getOperand(0);
5746 MVT VVT = V.getSimpleValueType();
5747 if (!Subtarget->hasSSE41() || (VVT != MVT::v4f32 && VVT != MVT::v4i32))
5750 unsigned FirstNonZeroDst =
5751 cast<ConstantSDNode>(FirstNonZero.getOperand(1))->getZExtValue();
5752 unsigned CorrectIdx = FirstNonZeroDst == FirstNonZeroIdx;
5753 unsigned IncorrectIdx = CorrectIdx ? -1U : FirstNonZeroIdx;
5754 unsigned IncorrectDst = CorrectIdx ? -1U : FirstNonZeroDst;
5756 for (unsigned Idx = FirstNonZeroIdx + 1; Idx < NumElems; ++Idx) {
5757 SDValue Elem = Op.getOperand(Idx);
5758 if (Elem.getOpcode() == ISD::UNDEF || X86::isZeroNode(Elem))
5761 // TODO: What else can be here? Deal with it.
5762 if (Elem.getOpcode() != ISD::EXTRACT_VECTOR_ELT)
5765 // TODO: Some optimizations are still possible here
5766 // ex: Getting one element from a vector, and the rest from another.
5767 if (Elem.getOperand(0) != V)
5770 unsigned Dst = cast<ConstantSDNode>(Elem.getOperand(1))->getZExtValue();
5773 else if (IncorrectIdx == -1U) {
5777 // There was already one element with an incorrect index.
5778 // We can't optimize this case to an insertps.
5782 if (NumNonZero == CorrectIdx || NumNonZero == CorrectIdx + 1) {
5784 EVT VT = Op.getSimpleValueType();
5785 unsigned ElementMoveMask = 0;
5786 if (IncorrectIdx == -1U)
5787 ElementMoveMask = FirstNonZeroIdx << 6 | FirstNonZeroIdx << 4;
5789 ElementMoveMask = IncorrectDst << 6 | IncorrectIdx << 4;
5791 SDValue InsertpsMask =
5792 DAG.getIntPtrConstant(ElementMoveMask | (~NonZeros & 0xf));
5793 return DAG.getNode(X86ISD::INSERTPS, dl, VT, V, V, InsertpsMask);
5799 /// getVShift - Return a vector logical shift node.
5801 static SDValue getVShift(bool isLeft, EVT VT, SDValue SrcOp,
5802 unsigned NumBits, SelectionDAG &DAG,
5803 const TargetLowering &TLI, SDLoc dl) {
5804 assert(VT.is128BitVector() && "Unknown type for VShift");
5805 EVT ShVT = MVT::v2i64;
5806 unsigned Opc = isLeft ? X86ISD::VSHLDQ : X86ISD::VSRLDQ;
5807 SrcOp = DAG.getNode(ISD::BITCAST, dl, ShVT, SrcOp);
5808 return DAG.getNode(ISD::BITCAST, dl, VT,
5809 DAG.getNode(Opc, dl, ShVT, SrcOp,
5810 DAG.getConstant(NumBits,
5811 TLI.getScalarShiftAmountTy(SrcOp.getValueType()))));
5815 LowerAsSplatVectorLoad(SDValue SrcOp, MVT VT, SDLoc dl, SelectionDAG &DAG) {
5817 // Check if the scalar load can be widened into a vector load. And if
5818 // the address is "base + cst" see if the cst can be "absorbed" into
5819 // the shuffle mask.
5820 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(SrcOp)) {
5821 SDValue Ptr = LD->getBasePtr();
5822 if (!ISD::isNormalLoad(LD) || LD->isVolatile())
5824 EVT PVT = LD->getValueType(0);
5825 if (PVT != MVT::i32 && PVT != MVT::f32)
5830 if (FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr)) {
5831 FI = FINode->getIndex();
5833 } else if (DAG.isBaseWithConstantOffset(Ptr) &&
5834 isa<FrameIndexSDNode>(Ptr.getOperand(0))) {
5835 FI = cast<FrameIndexSDNode>(Ptr.getOperand(0))->getIndex();
5836 Offset = Ptr.getConstantOperandVal(1);
5837 Ptr = Ptr.getOperand(0);
5842 // FIXME: 256-bit vector instructions don't require a strict alignment,
5843 // improve this code to support it better.
5844 unsigned RequiredAlign = VT.getSizeInBits()/8;
5845 SDValue Chain = LD->getChain();
5846 // Make sure the stack object alignment is at least 16 or 32.
5847 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
5848 if (DAG.InferPtrAlignment(Ptr) < RequiredAlign) {
5849 if (MFI->isFixedObjectIndex(FI)) {
5850 // Can't change the alignment. FIXME: It's possible to compute
5851 // the exact stack offset and reference FI + adjust offset instead.
5852 // If someone *really* cares about this. That's the way to implement it.
5855 MFI->setObjectAlignment(FI, RequiredAlign);
5859 // (Offset % 16 or 32) must be multiple of 4. Then address is then
5860 // Ptr + (Offset & ~15).
5863 if ((Offset % RequiredAlign) & 3)
5865 int64_t StartOffset = Offset & ~(RequiredAlign-1);
5867 Ptr = DAG.getNode(ISD::ADD, SDLoc(Ptr), Ptr.getValueType(),
5868 Ptr,DAG.getConstant(StartOffset, Ptr.getValueType()));
5870 int EltNo = (Offset - StartOffset) >> 2;
5871 unsigned NumElems = VT.getVectorNumElements();
5873 EVT NVT = EVT::getVectorVT(*DAG.getContext(), PVT, NumElems);
5874 SDValue V1 = DAG.getLoad(NVT, dl, Chain, Ptr,
5875 LD->getPointerInfo().getWithOffset(StartOffset),
5876 false, false, false, 0);
5878 SmallVector<int, 8> Mask;
5879 for (unsigned i = 0; i != NumElems; ++i)
5880 Mask.push_back(EltNo);
5882 return DAG.getVectorShuffle(NVT, dl, V1, DAG.getUNDEF(NVT), &Mask[0]);
5888 /// EltsFromConsecutiveLoads - Given the initializing elements 'Elts' of a
5889 /// vector of type 'VT', see if the elements can be replaced by a single large
5890 /// load which has the same value as a build_vector whose operands are 'elts'.
5892 /// Example: <load i32 *a, load i32 *a+4, undef, undef> -> zextload a
5894 /// FIXME: we'd also like to handle the case where the last elements are zero
5895 /// rather than undef via VZEXT_LOAD, but we do not detect that case today.
5896 /// There's even a handy isZeroNode for that purpose.
5897 static SDValue EltsFromConsecutiveLoads(EVT VT, SmallVectorImpl<SDValue> &Elts,
5898 SDLoc &DL, SelectionDAG &DAG,
5899 bool isAfterLegalize) {
5900 EVT EltVT = VT.getVectorElementType();
5901 unsigned NumElems = Elts.size();
5903 LoadSDNode *LDBase = nullptr;
5904 unsigned LastLoadedElt = -1U;
5906 // For each element in the initializer, see if we've found a load or an undef.
5907 // If we don't find an initial load element, or later load elements are
5908 // non-consecutive, bail out.
5909 for (unsigned i = 0; i < NumElems; ++i) {
5910 SDValue Elt = Elts[i];
5912 if (!Elt.getNode() ||
5913 (Elt.getOpcode() != ISD::UNDEF && !ISD::isNON_EXTLoad(Elt.getNode())))
5916 if (Elt.getNode()->getOpcode() == ISD::UNDEF)
5918 LDBase = cast<LoadSDNode>(Elt.getNode());
5922 if (Elt.getOpcode() == ISD::UNDEF)
5925 LoadSDNode *LD = cast<LoadSDNode>(Elt);
5926 if (!DAG.isConsecutiveLoad(LD, LDBase, EltVT.getSizeInBits()/8, i))
5931 // If we have found an entire vector of loads and undefs, then return a large
5932 // load of the entire vector width starting at the base pointer. If we found
5933 // consecutive loads for the low half, generate a vzext_load node.
5934 if (LastLoadedElt == NumElems - 1) {
5936 if (isAfterLegalize &&
5937 !DAG.getTargetLoweringInfo().isOperationLegal(ISD::LOAD, VT))
5940 SDValue NewLd = SDValue();
5942 if (DAG.InferPtrAlignment(LDBase->getBasePtr()) >= 16)
5943 NewLd = DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(),
5944 LDBase->getPointerInfo(),
5945 LDBase->isVolatile(), LDBase->isNonTemporal(),
5946 LDBase->isInvariant(), 0);
5947 NewLd = DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(),
5948 LDBase->getPointerInfo(),
5949 LDBase->isVolatile(), LDBase->isNonTemporal(),
5950 LDBase->isInvariant(), LDBase->getAlignment());
5952 if (LDBase->hasAnyUseOfValue(1)) {
5953 SDValue NewChain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
5955 SDValue(NewLd.getNode(), 1));
5956 DAG.ReplaceAllUsesOfValueWith(SDValue(LDBase, 1), NewChain);
5957 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(LDBase, 1),
5958 SDValue(NewLd.getNode(), 1));
5963 if (NumElems == 4 && LastLoadedElt == 1 &&
5964 DAG.getTargetLoweringInfo().isTypeLegal(MVT::v2i64)) {
5965 SDVTList Tys = DAG.getVTList(MVT::v2i64, MVT::Other);
5966 SDValue Ops[] = { LDBase->getChain(), LDBase->getBasePtr() };
5968 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, DL, Tys, Ops, MVT::i64,
5969 LDBase->getPointerInfo(),
5970 LDBase->getAlignment(),
5971 false/*isVolatile*/, true/*ReadMem*/,
5974 // Make sure the newly-created LOAD is in the same position as LDBase in
5975 // terms of dependency. We create a TokenFactor for LDBase and ResNode, and
5976 // update uses of LDBase's output chain to use the TokenFactor.
5977 if (LDBase->hasAnyUseOfValue(1)) {
5978 SDValue NewChain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
5979 SDValue(LDBase, 1), SDValue(ResNode.getNode(), 1));
5980 DAG.ReplaceAllUsesOfValueWith(SDValue(LDBase, 1), NewChain);
5981 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(LDBase, 1),
5982 SDValue(ResNode.getNode(), 1));
5985 return DAG.getNode(ISD::BITCAST, DL, VT, ResNode);
5990 /// LowerVectorBroadcast - Attempt to use the vbroadcast instruction
5991 /// to generate a splat value for the following cases:
5992 /// 1. A splat BUILD_VECTOR which uses a single scalar load, or a constant.
5993 /// 2. A splat shuffle which uses a scalar_to_vector node which comes from
5994 /// a scalar load, or a constant.
5995 /// The VBROADCAST node is returned when a pattern is found,
5996 /// or SDValue() otherwise.
5997 static SDValue LowerVectorBroadcast(SDValue Op, const X86Subtarget* Subtarget,
5998 SelectionDAG &DAG) {
5999 // VBROADCAST requires AVX.
6000 // TODO: Splats could be generated for non-AVX CPUs using SSE
6001 // instructions, but there's less potential gain for only 128-bit vectors.
6002 if (!Subtarget->hasAVX())
6005 MVT VT = Op.getSimpleValueType();
6008 assert((VT.is128BitVector() || VT.is256BitVector() || VT.is512BitVector()) &&
6009 "Unsupported vector type for broadcast.");
6014 switch (Op.getOpcode()) {
6016 // Unknown pattern found.
6019 case ISD::BUILD_VECTOR: {
6020 auto *BVOp = cast<BuildVectorSDNode>(Op.getNode());
6021 BitVector UndefElements;
6022 SDValue Splat = BVOp->getSplatValue(&UndefElements);
6024 // We need a splat of a single value to use broadcast, and it doesn't
6025 // make any sense if the value is only in one element of the vector.
6026 if (!Splat || (VT.getVectorNumElements() - UndefElements.count()) <= 1)
6030 ConstSplatVal = (Ld.getOpcode() == ISD::Constant ||
6031 Ld.getOpcode() == ISD::ConstantFP);
6033 // Make sure that all of the users of a non-constant load are from the
6034 // BUILD_VECTOR node.
6035 if (!ConstSplatVal && !BVOp->isOnlyUserOf(Ld.getNode()))
6040 case ISD::VECTOR_SHUFFLE: {
6041 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
6043 // Shuffles must have a splat mask where the first element is
6045 if ((!SVOp->isSplat()) || SVOp->getMaskElt(0) != 0)
6048 SDValue Sc = Op.getOperand(0);
6049 if (Sc.getOpcode() != ISD::SCALAR_TO_VECTOR &&
6050 Sc.getOpcode() != ISD::BUILD_VECTOR) {
6052 if (!Subtarget->hasInt256())
6055 // Use the register form of the broadcast instruction available on AVX2.
6056 if (VT.getSizeInBits() >= 256)
6057 Sc = Extract128BitVector(Sc, 0, DAG, dl);
6058 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Sc);
6061 Ld = Sc.getOperand(0);
6062 ConstSplatVal = (Ld.getOpcode() == ISD::Constant ||
6063 Ld.getOpcode() == ISD::ConstantFP);
6065 // The scalar_to_vector node and the suspected
6066 // load node must have exactly one user.
6067 // Constants may have multiple users.
6069 // AVX-512 has register version of the broadcast
6070 bool hasRegVer = Subtarget->hasAVX512() && VT.is512BitVector() &&
6071 Ld.getValueType().getSizeInBits() >= 32;
6072 if (!ConstSplatVal && ((!Sc.hasOneUse() || !Ld.hasOneUse()) &&
6079 unsigned ScalarSize = Ld.getValueType().getSizeInBits();
6080 bool IsGE256 = (VT.getSizeInBits() >= 256);
6082 // When optimizing for size, generate up to 5 extra bytes for a broadcast
6083 // instruction to save 8 or more bytes of constant pool data.
6084 // TODO: If multiple splats are generated to load the same constant,
6085 // it may be detrimental to overall size. There needs to be a way to detect
6086 // that condition to know if this is truly a size win.
6087 const Function *F = DAG.getMachineFunction().getFunction();
6088 bool OptForSize = F->getAttributes().
6089 hasAttribute(AttributeSet::FunctionIndex, Attribute::OptimizeForSize);
6091 // Handle broadcasting a single constant scalar from the constant pool
6093 // On Sandybridge (no AVX2), it is still better to load a constant vector
6094 // from the constant pool and not to broadcast it from a scalar.
6095 // But override that restriction when optimizing for size.
6096 // TODO: Check if splatting is recommended for other AVX-capable CPUs.
6097 if (ConstSplatVal && (Subtarget->hasAVX2() || OptForSize)) {
6098 EVT CVT = Ld.getValueType();
6099 assert(!CVT.isVector() && "Must not broadcast a vector type");
6101 // Splat f32, i32, v4f64, v4i64 in all cases with AVX2.
6102 // For size optimization, also splat v2f64 and v2i64, and for size opt
6103 // with AVX2, also splat i8 and i16.
6104 // With pattern matching, the VBROADCAST node may become a VMOVDDUP.
6105 if (ScalarSize == 32 || (IsGE256 && ScalarSize == 64) ||
6106 (OptForSize && (ScalarSize == 64 || Subtarget->hasAVX2()))) {
6107 const Constant *C = nullptr;
6108 if (ConstantSDNode *CI = dyn_cast<ConstantSDNode>(Ld))
6109 C = CI->getConstantIntValue();
6110 else if (ConstantFPSDNode *CF = dyn_cast<ConstantFPSDNode>(Ld))
6111 C = CF->getConstantFPValue();
6113 assert(C && "Invalid constant type");
6115 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
6116 SDValue CP = DAG.getConstantPool(C, TLI.getPointerTy());
6117 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
6118 Ld = DAG.getLoad(CVT, dl, DAG.getEntryNode(), CP,
6119 MachinePointerInfo::getConstantPool(),
6120 false, false, false, Alignment);
6122 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
6126 bool IsLoad = ISD::isNormalLoad(Ld.getNode());
6128 // Handle AVX2 in-register broadcasts.
6129 if (!IsLoad && Subtarget->hasInt256() &&
6130 (ScalarSize == 32 || (IsGE256 && ScalarSize == 64)))
6131 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
6133 // The scalar source must be a normal load.
6137 if (ScalarSize == 32 || (IsGE256 && ScalarSize == 64))
6138 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
6140 // The integer check is needed for the 64-bit into 128-bit so it doesn't match
6141 // double since there is no vbroadcastsd xmm
6142 if (Subtarget->hasInt256() && Ld.getValueType().isInteger()) {
6143 if (ScalarSize == 8 || ScalarSize == 16 || ScalarSize == 64)
6144 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
6147 // Unsupported broadcast.
6151 /// \brief For an EXTRACT_VECTOR_ELT with a constant index return the real
6152 /// underlying vector and index.
6154 /// Modifies \p ExtractedFromVec to the real vector and returns the real
6156 static int getUnderlyingExtractedFromVec(SDValue &ExtractedFromVec,
6158 int Idx = cast<ConstantSDNode>(ExtIdx)->getZExtValue();
6159 if (!isa<ShuffleVectorSDNode>(ExtractedFromVec))
6162 // For 256-bit vectors, LowerEXTRACT_VECTOR_ELT_SSE4 may have already
6164 // (extract_vector_elt (v8f32 %vreg1), Constant<6>)
6166 // (extract_vector_elt (vector_shuffle<2,u,u,u>
6167 // (extract_subvector (v8f32 %vreg0), Constant<4>),
6170 // In this case the vector is the extract_subvector expression and the index
6171 // is 2, as specified by the shuffle.
6172 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(ExtractedFromVec);
6173 SDValue ShuffleVec = SVOp->getOperand(0);
6174 MVT ShuffleVecVT = ShuffleVec.getSimpleValueType();
6175 assert(ShuffleVecVT.getVectorElementType() ==
6176 ExtractedFromVec.getSimpleValueType().getVectorElementType());
6178 int ShuffleIdx = SVOp->getMaskElt(Idx);
6179 if (isUndefOrInRange(ShuffleIdx, 0, ShuffleVecVT.getVectorNumElements())) {
6180 ExtractedFromVec = ShuffleVec;
6186 static SDValue buildFromShuffleMostly(SDValue Op, SelectionDAG &DAG) {
6187 MVT VT = Op.getSimpleValueType();
6189 // Skip if insert_vec_elt is not supported.
6190 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
6191 if (!TLI.isOperationLegalOrCustom(ISD::INSERT_VECTOR_ELT, VT))
6195 unsigned NumElems = Op.getNumOperands();
6199 SmallVector<unsigned, 4> InsertIndices;
6200 SmallVector<int, 8> Mask(NumElems, -1);
6202 for (unsigned i = 0; i != NumElems; ++i) {
6203 unsigned Opc = Op.getOperand(i).getOpcode();
6205 if (Opc == ISD::UNDEF)
6208 if (Opc != ISD::EXTRACT_VECTOR_ELT) {
6209 // Quit if more than 1 elements need inserting.
6210 if (InsertIndices.size() > 1)
6213 InsertIndices.push_back(i);
6217 SDValue ExtractedFromVec = Op.getOperand(i).getOperand(0);
6218 SDValue ExtIdx = Op.getOperand(i).getOperand(1);
6219 // Quit if non-constant index.
6220 if (!isa<ConstantSDNode>(ExtIdx))
6222 int Idx = getUnderlyingExtractedFromVec(ExtractedFromVec, ExtIdx);
6224 // Quit if extracted from vector of different type.
6225 if (ExtractedFromVec.getValueType() != VT)
6228 if (!VecIn1.getNode())
6229 VecIn1 = ExtractedFromVec;
6230 else if (VecIn1 != ExtractedFromVec) {
6231 if (!VecIn2.getNode())
6232 VecIn2 = ExtractedFromVec;
6233 else if (VecIn2 != ExtractedFromVec)
6234 // Quit if more than 2 vectors to shuffle
6238 if (ExtractedFromVec == VecIn1)
6240 else if (ExtractedFromVec == VecIn2)
6241 Mask[i] = Idx + NumElems;
6244 if (!VecIn1.getNode())
6247 VecIn2 = VecIn2.getNode() ? VecIn2 : DAG.getUNDEF(VT);
6248 SDValue NV = DAG.getVectorShuffle(VT, DL, VecIn1, VecIn2, &Mask[0]);
6249 for (unsigned i = 0, e = InsertIndices.size(); i != e; ++i) {
6250 unsigned Idx = InsertIndices[i];
6251 NV = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, VT, NV, Op.getOperand(Idx),
6252 DAG.getIntPtrConstant(Idx));
6258 // Lower BUILD_VECTOR operation for v8i1 and v16i1 types.
6260 X86TargetLowering::LowerBUILD_VECTORvXi1(SDValue Op, SelectionDAG &DAG) const {
6262 MVT VT = Op.getSimpleValueType();
6263 assert((VT.getVectorElementType() == MVT::i1) && (VT.getSizeInBits() <= 16) &&
6264 "Unexpected type in LowerBUILD_VECTORvXi1!");
6267 if (ISD::isBuildVectorAllZeros(Op.getNode())) {
6268 SDValue Cst = DAG.getTargetConstant(0, MVT::i1);
6269 SmallVector<SDValue, 16> Ops(VT.getVectorNumElements(), Cst);
6270 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
6273 if (ISD::isBuildVectorAllOnes(Op.getNode())) {
6274 SDValue Cst = DAG.getTargetConstant(1, MVT::i1);
6275 SmallVector<SDValue, 16> Ops(VT.getVectorNumElements(), Cst);
6276 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
6279 bool AllContants = true;
6280 uint64_t Immediate = 0;
6281 int NonConstIdx = -1;
6282 bool IsSplat = true;
6283 unsigned NumNonConsts = 0;
6284 unsigned NumConsts = 0;
6285 for (unsigned idx = 0, e = Op.getNumOperands(); idx < e; ++idx) {
6286 SDValue In = Op.getOperand(idx);
6287 if (In.getOpcode() == ISD::UNDEF)
6289 if (!isa<ConstantSDNode>(In)) {
6290 AllContants = false;
6296 if (cast<ConstantSDNode>(In)->getZExtValue())
6297 Immediate |= (1ULL << idx);
6299 if (In != Op.getOperand(0))
6304 SDValue FullMask = DAG.getNode(ISD::BITCAST, dl, MVT::v16i1,
6305 DAG.getConstant(Immediate, MVT::i16));
6306 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, FullMask,
6307 DAG.getIntPtrConstant(0));
6310 if (NumNonConsts == 1 && NonConstIdx != 0) {
6313 SDValue VecAsImm = DAG.getConstant(Immediate,
6314 MVT::getIntegerVT(VT.getSizeInBits()));
6315 DstVec = DAG.getNode(ISD::BITCAST, dl, VT, VecAsImm);
6318 DstVec = DAG.getUNDEF(VT);
6319 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, DstVec,
6320 Op.getOperand(NonConstIdx),
6321 DAG.getIntPtrConstant(NonConstIdx));
6323 if (!IsSplat && (NonConstIdx != 0))
6324 llvm_unreachable("Unsupported BUILD_VECTOR operation");
6325 MVT SelectVT = (VT == MVT::v16i1)? MVT::i16 : MVT::i8;
6328 Select = DAG.getNode(ISD::SELECT, dl, SelectVT, Op.getOperand(0),
6329 DAG.getConstant(-1, SelectVT),
6330 DAG.getConstant(0, SelectVT));
6332 Select = DAG.getNode(ISD::SELECT, dl, SelectVT, Op.getOperand(0),
6333 DAG.getConstant((Immediate | 1), SelectVT),
6334 DAG.getConstant(Immediate, SelectVT));
6335 return DAG.getNode(ISD::BITCAST, dl, VT, Select);
6338 /// \brief Return true if \p N implements a horizontal binop and return the
6339 /// operands for the horizontal binop into V0 and V1.
6341 /// This is a helper function of PerformBUILD_VECTORCombine.
6342 /// This function checks that the build_vector \p N in input implements a
6343 /// horizontal operation. Parameter \p Opcode defines the kind of horizontal
6344 /// operation to match.
6345 /// For example, if \p Opcode is equal to ISD::ADD, then this function
6346 /// checks if \p N implements a horizontal arithmetic add; if instead \p Opcode
6347 /// is equal to ISD::SUB, then this function checks if this is a horizontal
6350 /// This function only analyzes elements of \p N whose indices are
6351 /// in range [BaseIdx, LastIdx).
6352 static bool isHorizontalBinOp(const BuildVectorSDNode *N, unsigned Opcode,
6354 unsigned BaseIdx, unsigned LastIdx,
6355 SDValue &V0, SDValue &V1) {
6356 EVT VT = N->getValueType(0);
6358 assert(BaseIdx * 2 <= LastIdx && "Invalid Indices in input!");
6359 assert(VT.isVector() && VT.getVectorNumElements() >= LastIdx &&
6360 "Invalid Vector in input!");
6362 bool IsCommutable = (Opcode == ISD::ADD || Opcode == ISD::FADD);
6363 bool CanFold = true;
6364 unsigned ExpectedVExtractIdx = BaseIdx;
6365 unsigned NumElts = LastIdx - BaseIdx;
6366 V0 = DAG.getUNDEF(VT);
6367 V1 = DAG.getUNDEF(VT);
6369 // Check if N implements a horizontal binop.
6370 for (unsigned i = 0, e = NumElts; i != e && CanFold; ++i) {
6371 SDValue Op = N->getOperand(i + BaseIdx);
6374 if (Op->getOpcode() == ISD::UNDEF) {
6375 // Update the expected vector extract index.
6376 if (i * 2 == NumElts)
6377 ExpectedVExtractIdx = BaseIdx;
6378 ExpectedVExtractIdx += 2;
6382 CanFold = Op->getOpcode() == Opcode && Op->hasOneUse();
6387 SDValue Op0 = Op.getOperand(0);
6388 SDValue Op1 = Op.getOperand(1);
6390 // Try to match the following pattern:
6391 // (BINOP (extract_vector_elt A, I), (extract_vector_elt A, I+1))
6392 CanFold = (Op0.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
6393 Op1.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
6394 Op0.getOperand(0) == Op1.getOperand(0) &&
6395 isa<ConstantSDNode>(Op0.getOperand(1)) &&
6396 isa<ConstantSDNode>(Op1.getOperand(1)));
6400 unsigned I0 = cast<ConstantSDNode>(Op0.getOperand(1))->getZExtValue();
6401 unsigned I1 = cast<ConstantSDNode>(Op1.getOperand(1))->getZExtValue();
6403 if (i * 2 < NumElts) {
6404 if (V0.getOpcode() == ISD::UNDEF)
6405 V0 = Op0.getOperand(0);
6407 if (V1.getOpcode() == ISD::UNDEF)
6408 V1 = Op0.getOperand(0);
6409 if (i * 2 == NumElts)
6410 ExpectedVExtractIdx = BaseIdx;
6413 SDValue Expected = (i * 2 < NumElts) ? V0 : V1;
6414 if (I0 == ExpectedVExtractIdx)
6415 CanFold = I1 == I0 + 1 && Op0.getOperand(0) == Expected;
6416 else if (IsCommutable && I1 == ExpectedVExtractIdx) {
6417 // Try to match the following dag sequence:
6418 // (BINOP (extract_vector_elt A, I+1), (extract_vector_elt A, I))
6419 CanFold = I0 == I1 + 1 && Op1.getOperand(0) == Expected;
6423 ExpectedVExtractIdx += 2;
6429 /// \brief Emit a sequence of two 128-bit horizontal add/sub followed by
6430 /// a concat_vector.
6432 /// This is a helper function of PerformBUILD_VECTORCombine.
6433 /// This function expects two 256-bit vectors called V0 and V1.
6434 /// At first, each vector is split into two separate 128-bit vectors.
6435 /// Then, the resulting 128-bit vectors are used to implement two
6436 /// horizontal binary operations.
6438 /// The kind of horizontal binary operation is defined by \p X86Opcode.
6440 /// \p Mode specifies how the 128-bit parts of V0 and V1 are passed in input to
6441 /// the two new horizontal binop.
6442 /// When Mode is set, the first horizontal binop dag node would take as input
6443 /// the lower 128-bit of V0 and the upper 128-bit of V0. The second
6444 /// horizontal binop dag node would take as input the lower 128-bit of V1
6445 /// and the upper 128-bit of V1.
6447 /// HADD V0_LO, V0_HI
6448 /// HADD V1_LO, V1_HI
6450 /// Otherwise, the first horizontal binop dag node takes as input the lower
6451 /// 128-bit of V0 and the lower 128-bit of V1, and the second horizontal binop
6452 /// dag node takes the the upper 128-bit of V0 and the upper 128-bit of V1.
6454 /// HADD V0_LO, V1_LO
6455 /// HADD V0_HI, V1_HI
6457 /// If \p isUndefLO is set, then the algorithm propagates UNDEF to the lower
6458 /// 128-bits of the result. If \p isUndefHI is set, then UNDEF is propagated to
6459 /// the upper 128-bits of the result.
6460 static SDValue ExpandHorizontalBinOp(const SDValue &V0, const SDValue &V1,
6461 SDLoc DL, SelectionDAG &DAG,
6462 unsigned X86Opcode, bool Mode,
6463 bool isUndefLO, bool isUndefHI) {
6464 EVT VT = V0.getValueType();
6465 assert(VT.is256BitVector() && VT == V1.getValueType() &&
6466 "Invalid nodes in input!");
6468 unsigned NumElts = VT.getVectorNumElements();
6469 SDValue V0_LO = Extract128BitVector(V0, 0, DAG, DL);
6470 SDValue V0_HI = Extract128BitVector(V0, NumElts/2, DAG, DL);
6471 SDValue V1_LO = Extract128BitVector(V1, 0, DAG, DL);
6472 SDValue V1_HI = Extract128BitVector(V1, NumElts/2, DAG, DL);
6473 EVT NewVT = V0_LO.getValueType();
6475 SDValue LO = DAG.getUNDEF(NewVT);
6476 SDValue HI = DAG.getUNDEF(NewVT);
6479 // Don't emit a horizontal binop if the result is expected to be UNDEF.
6480 if (!isUndefLO && V0->getOpcode() != ISD::UNDEF)
6481 LO = DAG.getNode(X86Opcode, DL, NewVT, V0_LO, V0_HI);
6482 if (!isUndefHI && V1->getOpcode() != ISD::UNDEF)
6483 HI = DAG.getNode(X86Opcode, DL, NewVT, V1_LO, V1_HI);
6485 // Don't emit a horizontal binop if the result is expected to be UNDEF.
6486 if (!isUndefLO && (V0_LO->getOpcode() != ISD::UNDEF ||
6487 V1_LO->getOpcode() != ISD::UNDEF))
6488 LO = DAG.getNode(X86Opcode, DL, NewVT, V0_LO, V1_LO);
6490 if (!isUndefHI && (V0_HI->getOpcode() != ISD::UNDEF ||
6491 V1_HI->getOpcode() != ISD::UNDEF))
6492 HI = DAG.getNode(X86Opcode, DL, NewVT, V0_HI, V1_HI);
6495 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, LO, HI);
6498 /// \brief Try to fold a build_vector that performs an 'addsub' into the
6499 /// sequence of 'vadd + vsub + blendi'.
6500 static SDValue matchAddSub(const BuildVectorSDNode *BV, SelectionDAG &DAG,
6501 const X86Subtarget *Subtarget) {
6503 EVT VT = BV->getValueType(0);
6504 unsigned NumElts = VT.getVectorNumElements();
6505 SDValue InVec0 = DAG.getUNDEF(VT);
6506 SDValue InVec1 = DAG.getUNDEF(VT);
6508 assert((VT == MVT::v8f32 || VT == MVT::v4f64 || VT == MVT::v4f32 ||
6509 VT == MVT::v2f64) && "build_vector with an invalid type found!");
6511 // Odd-numbered elements in the input build vector are obtained from
6512 // adding two integer/float elements.
6513 // Even-numbered elements in the input build vector are obtained from
6514 // subtracting two integer/float elements.
6515 unsigned ExpectedOpcode = ISD::FSUB;
6516 unsigned NextExpectedOpcode = ISD::FADD;
6517 bool AddFound = false;
6518 bool SubFound = false;
6520 for (unsigned i = 0, e = NumElts; i != e; i++) {
6521 SDValue Op = BV->getOperand(i);
6523 // Skip 'undef' values.
6524 unsigned Opcode = Op.getOpcode();
6525 if (Opcode == ISD::UNDEF) {
6526 std::swap(ExpectedOpcode, NextExpectedOpcode);
6530 // Early exit if we found an unexpected opcode.
6531 if (Opcode != ExpectedOpcode)
6534 SDValue Op0 = Op.getOperand(0);
6535 SDValue Op1 = Op.getOperand(1);
6537 // Try to match the following pattern:
6538 // (BINOP (extract_vector_elt A, i), (extract_vector_elt B, i))
6539 // Early exit if we cannot match that sequence.
6540 if (Op0.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
6541 Op1.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
6542 !isa<ConstantSDNode>(Op0.getOperand(1)) ||
6543 !isa<ConstantSDNode>(Op1.getOperand(1)) ||
6544 Op0.getOperand(1) != Op1.getOperand(1))
6547 unsigned I0 = cast<ConstantSDNode>(Op0.getOperand(1))->getZExtValue();
6551 // We found a valid add/sub node. Update the information accordingly.
6557 // Update InVec0 and InVec1.
6558 if (InVec0.getOpcode() == ISD::UNDEF)
6559 InVec0 = Op0.getOperand(0);
6560 if (InVec1.getOpcode() == ISD::UNDEF)
6561 InVec1 = Op1.getOperand(0);
6563 // Make sure that operands in input to each add/sub node always
6564 // come from a same pair of vectors.
6565 if (InVec0 != Op0.getOperand(0)) {
6566 if (ExpectedOpcode == ISD::FSUB)
6569 // FADD is commutable. Try to commute the operands
6570 // and then test again.
6571 std::swap(Op0, Op1);
6572 if (InVec0 != Op0.getOperand(0))
6576 if (InVec1 != Op1.getOperand(0))
6579 // Update the pair of expected opcodes.
6580 std::swap(ExpectedOpcode, NextExpectedOpcode);
6583 // Don't try to fold this build_vector into an ADDSUB if the inputs are undef.
6584 if (AddFound && SubFound && InVec0.getOpcode() != ISD::UNDEF &&
6585 InVec1.getOpcode() != ISD::UNDEF)
6586 return DAG.getNode(X86ISD::ADDSUB, DL, VT, InVec0, InVec1);
6591 static SDValue PerformBUILD_VECTORCombine(SDNode *N, SelectionDAG &DAG,
6592 const X86Subtarget *Subtarget) {
6594 EVT VT = N->getValueType(0);
6595 unsigned NumElts = VT.getVectorNumElements();
6596 BuildVectorSDNode *BV = cast<BuildVectorSDNode>(N);
6597 SDValue InVec0, InVec1;
6599 // Try to match an ADDSUB.
6600 if ((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
6601 (Subtarget->hasAVX() && (VT == MVT::v8f32 || VT == MVT::v4f64))) {
6602 SDValue Value = matchAddSub(BV, DAG, Subtarget);
6603 if (Value.getNode())
6607 // Try to match horizontal ADD/SUB.
6608 unsigned NumUndefsLO = 0;
6609 unsigned NumUndefsHI = 0;
6610 unsigned Half = NumElts/2;
6612 // Count the number of UNDEF operands in the build_vector in input.
6613 for (unsigned i = 0, e = Half; i != e; ++i)
6614 if (BV->getOperand(i)->getOpcode() == ISD::UNDEF)
6617 for (unsigned i = Half, e = NumElts; i != e; ++i)
6618 if (BV->getOperand(i)->getOpcode() == ISD::UNDEF)
6621 // Early exit if this is either a build_vector of all UNDEFs or all the
6622 // operands but one are UNDEF.
6623 if (NumUndefsLO + NumUndefsHI + 1 >= NumElts)
6626 if ((VT == MVT::v4f32 || VT == MVT::v2f64) && Subtarget->hasSSE3()) {
6627 // Try to match an SSE3 float HADD/HSUB.
6628 if (isHorizontalBinOp(BV, ISD::FADD, DAG, 0, NumElts, InVec0, InVec1))
6629 return DAG.getNode(X86ISD::FHADD, DL, VT, InVec0, InVec1);
6631 if (isHorizontalBinOp(BV, ISD::FSUB, DAG, 0, NumElts, InVec0, InVec1))
6632 return DAG.getNode(X86ISD::FHSUB, DL, VT, InVec0, InVec1);
6633 } else if ((VT == MVT::v4i32 || VT == MVT::v8i16) && Subtarget->hasSSSE3()) {
6634 // Try to match an SSSE3 integer HADD/HSUB.
6635 if (isHorizontalBinOp(BV, ISD::ADD, DAG, 0, NumElts, InVec0, InVec1))
6636 return DAG.getNode(X86ISD::HADD, DL, VT, InVec0, InVec1);
6638 if (isHorizontalBinOp(BV, ISD::SUB, DAG, 0, NumElts, InVec0, InVec1))
6639 return DAG.getNode(X86ISD::HSUB, DL, VT, InVec0, InVec1);
6642 if (!Subtarget->hasAVX())
6645 if ((VT == MVT::v8f32 || VT == MVT::v4f64)) {
6646 // Try to match an AVX horizontal add/sub of packed single/double
6647 // precision floating point values from 256-bit vectors.
6648 SDValue InVec2, InVec3;
6649 if (isHorizontalBinOp(BV, ISD::FADD, DAG, 0, Half, InVec0, InVec1) &&
6650 isHorizontalBinOp(BV, ISD::FADD, DAG, Half, NumElts, InVec2, InVec3) &&
6651 ((InVec0.getOpcode() == ISD::UNDEF ||
6652 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
6653 ((InVec1.getOpcode() == ISD::UNDEF ||
6654 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
6655 return DAG.getNode(X86ISD::FHADD, DL, VT, InVec0, InVec1);
6657 if (isHorizontalBinOp(BV, ISD::FSUB, DAG, 0, Half, InVec0, InVec1) &&
6658 isHorizontalBinOp(BV, ISD::FSUB, DAG, Half, NumElts, InVec2, InVec3) &&
6659 ((InVec0.getOpcode() == ISD::UNDEF ||
6660 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
6661 ((InVec1.getOpcode() == ISD::UNDEF ||
6662 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
6663 return DAG.getNode(X86ISD::FHSUB, DL, VT, InVec0, InVec1);
6664 } else if (VT == MVT::v8i32 || VT == MVT::v16i16) {
6665 // Try to match an AVX2 horizontal add/sub of signed integers.
6666 SDValue InVec2, InVec3;
6668 bool CanFold = true;
6670 if (isHorizontalBinOp(BV, ISD::ADD, DAG, 0, Half, InVec0, InVec1) &&
6671 isHorizontalBinOp(BV, ISD::ADD, DAG, Half, NumElts, InVec2, InVec3) &&
6672 ((InVec0.getOpcode() == ISD::UNDEF ||
6673 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
6674 ((InVec1.getOpcode() == ISD::UNDEF ||
6675 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
6676 X86Opcode = X86ISD::HADD;
6677 else if (isHorizontalBinOp(BV, ISD::SUB, DAG, 0, Half, InVec0, InVec1) &&
6678 isHorizontalBinOp(BV, ISD::SUB, DAG, Half, NumElts, InVec2, InVec3) &&
6679 ((InVec0.getOpcode() == ISD::UNDEF ||
6680 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
6681 ((InVec1.getOpcode() == ISD::UNDEF ||
6682 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
6683 X86Opcode = X86ISD::HSUB;
6688 // Fold this build_vector into a single horizontal add/sub.
6689 // Do this only if the target has AVX2.
6690 if (Subtarget->hasAVX2())
6691 return DAG.getNode(X86Opcode, DL, VT, InVec0, InVec1);
6693 // Do not try to expand this build_vector into a pair of horizontal
6694 // add/sub if we can emit a pair of scalar add/sub.
6695 if (NumUndefsLO + 1 == Half || NumUndefsHI + 1 == Half)
6698 // Convert this build_vector into a pair of horizontal binop followed by
6700 bool isUndefLO = NumUndefsLO == Half;
6701 bool isUndefHI = NumUndefsHI == Half;
6702 return ExpandHorizontalBinOp(InVec0, InVec1, DL, DAG, X86Opcode, false,
6703 isUndefLO, isUndefHI);
6707 if ((VT == MVT::v8f32 || VT == MVT::v4f64 || VT == MVT::v8i32 ||
6708 VT == MVT::v16i16) && Subtarget->hasAVX()) {
6710 if (isHorizontalBinOp(BV, ISD::ADD, DAG, 0, NumElts, InVec0, InVec1))
6711 X86Opcode = X86ISD::HADD;
6712 else if (isHorizontalBinOp(BV, ISD::SUB, DAG, 0, NumElts, InVec0, InVec1))
6713 X86Opcode = X86ISD::HSUB;
6714 else if (isHorizontalBinOp(BV, ISD::FADD, DAG, 0, NumElts, InVec0, InVec1))
6715 X86Opcode = X86ISD::FHADD;
6716 else if (isHorizontalBinOp(BV, ISD::FSUB, DAG, 0, NumElts, InVec0, InVec1))
6717 X86Opcode = X86ISD::FHSUB;
6721 // Don't try to expand this build_vector into a pair of horizontal add/sub
6722 // if we can simply emit a pair of scalar add/sub.
6723 if (NumUndefsLO + 1 == Half || NumUndefsHI + 1 == Half)
6726 // Convert this build_vector into two horizontal add/sub followed by
6728 bool isUndefLO = NumUndefsLO == Half;
6729 bool isUndefHI = NumUndefsHI == Half;
6730 return ExpandHorizontalBinOp(InVec0, InVec1, DL, DAG, X86Opcode, true,
6731 isUndefLO, isUndefHI);
6738 X86TargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const {
6741 MVT VT = Op.getSimpleValueType();
6742 MVT ExtVT = VT.getVectorElementType();
6743 unsigned NumElems = Op.getNumOperands();
6745 // Generate vectors for predicate vectors.
6746 if (VT.getScalarType() == MVT::i1 && Subtarget->hasAVX512())
6747 return LowerBUILD_VECTORvXi1(Op, DAG);
6749 // Vectors containing all zeros can be matched by pxor and xorps later
6750 if (ISD::isBuildVectorAllZeros(Op.getNode())) {
6751 // Canonicalize this to <4 x i32> to 1) ensure the zero vectors are CSE'd
6752 // and 2) ensure that i64 scalars are eliminated on x86-32 hosts.
6753 if (VT == MVT::v4i32 || VT == MVT::v8i32 || VT == MVT::v16i32)
6756 return getZeroVector(VT, Subtarget, DAG, dl);
6759 // Vectors containing all ones can be matched by pcmpeqd on 128-bit width
6760 // vectors or broken into v4i32 operations on 256-bit vectors. AVX2 can use
6761 // vpcmpeqd on 256-bit vectors.
6762 if (Subtarget->hasSSE2() && ISD::isBuildVectorAllOnes(Op.getNode())) {
6763 if (VT == MVT::v4i32 || (VT == MVT::v8i32 && Subtarget->hasInt256()))
6766 if (!VT.is512BitVector())
6767 return getOnesVector(VT, Subtarget->hasInt256(), DAG, dl);
6770 SDValue Broadcast = LowerVectorBroadcast(Op, Subtarget, DAG);
6771 if (Broadcast.getNode())
6774 unsigned EVTBits = ExtVT.getSizeInBits();
6776 unsigned NumZero = 0;
6777 unsigned NumNonZero = 0;
6778 unsigned NonZeros = 0;
6779 bool IsAllConstants = true;
6780 SmallSet<SDValue, 8> Values;
6781 for (unsigned i = 0; i < NumElems; ++i) {
6782 SDValue Elt = Op.getOperand(i);
6783 if (Elt.getOpcode() == ISD::UNDEF)
6786 if (Elt.getOpcode() != ISD::Constant &&
6787 Elt.getOpcode() != ISD::ConstantFP)
6788 IsAllConstants = false;
6789 if (X86::isZeroNode(Elt))
6792 NonZeros |= (1 << i);
6797 // All undef vector. Return an UNDEF. All zero vectors were handled above.
6798 if (NumNonZero == 0)
6799 return DAG.getUNDEF(VT);
6801 // Special case for single non-zero, non-undef, element.
6802 if (NumNonZero == 1) {
6803 unsigned Idx = countTrailingZeros(NonZeros);
6804 SDValue Item = Op.getOperand(Idx);
6806 // If this is an insertion of an i64 value on x86-32, and if the top bits of
6807 // the value are obviously zero, truncate the value to i32 and do the
6808 // insertion that way. Only do this if the value is non-constant or if the
6809 // value is a constant being inserted into element 0. It is cheaper to do
6810 // a constant pool load than it is to do a movd + shuffle.
6811 if (ExtVT == MVT::i64 && !Subtarget->is64Bit() &&
6812 (!IsAllConstants || Idx == 0)) {
6813 if (DAG.MaskedValueIsZero(Item, APInt::getBitsSet(64, 32, 64))) {
6815 assert(VT == MVT::v2i64 && "Expected an SSE value type!");
6816 EVT VecVT = MVT::v4i32;
6817 unsigned VecElts = 4;
6819 // Truncate the value (which may itself be a constant) to i32, and
6820 // convert it to a vector with movd (S2V+shuffle to zero extend).
6821 Item = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Item);
6822 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Item);
6824 // If using the new shuffle lowering, just directly insert this.
6825 if (ExperimentalVectorShuffleLowering)
6827 ISD::BITCAST, dl, VT,
6828 getShuffleVectorZeroOrUndef(Item, Idx * 2, true, Subtarget, DAG));
6830 Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
6832 // Now we have our 32-bit value zero extended in the low element of
6833 // a vector. If Idx != 0, swizzle it into place.
6835 SmallVector<int, 4> Mask;
6836 Mask.push_back(Idx);
6837 for (unsigned i = 1; i != VecElts; ++i)
6839 Item = DAG.getVectorShuffle(VecVT, dl, Item, DAG.getUNDEF(VecVT),
6842 return DAG.getNode(ISD::BITCAST, dl, VT, Item);
6846 // If we have a constant or non-constant insertion into the low element of
6847 // a vector, we can do this with SCALAR_TO_VECTOR + shuffle of zero into
6848 // the rest of the elements. This will be matched as movd/movq/movss/movsd
6849 // depending on what the source datatype is.
6852 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
6854 if (ExtVT == MVT::i32 || ExtVT == MVT::f32 || ExtVT == MVT::f64 ||
6855 (ExtVT == MVT::i64 && Subtarget->is64Bit())) {
6856 if (VT.is256BitVector() || VT.is512BitVector()) {
6857 SDValue ZeroVec = getZeroVector(VT, Subtarget, DAG, dl);
6858 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, ZeroVec,
6859 Item, DAG.getIntPtrConstant(0));
6861 assert(VT.is128BitVector() && "Expected an SSE value type!");
6862 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
6863 // Turn it into a MOVL (i.e. movss, movsd, or movd) to a zero vector.
6864 return getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
6867 if (ExtVT == MVT::i16 || ExtVT == MVT::i8) {
6868 Item = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Item);
6869 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, Item);
6870 if (VT.is256BitVector()) {
6871 SDValue ZeroVec = getZeroVector(MVT::v8i32, Subtarget, DAG, dl);
6872 Item = Insert128BitVector(ZeroVec, Item, 0, DAG, dl);
6874 assert(VT.is128BitVector() && "Expected an SSE value type!");
6875 Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
6877 return DAG.getNode(ISD::BITCAST, dl, VT, Item);
6881 // Is it a vector logical left shift?
6882 if (NumElems == 2 && Idx == 1 &&
6883 X86::isZeroNode(Op.getOperand(0)) &&
6884 !X86::isZeroNode(Op.getOperand(1))) {
6885 unsigned NumBits = VT.getSizeInBits();
6886 return getVShift(true, VT,
6887 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
6888 VT, Op.getOperand(1)),
6889 NumBits/2, DAG, *this, dl);
6892 if (IsAllConstants) // Otherwise, it's better to do a constpool load.
6895 // Otherwise, if this is a vector with i32 or f32 elements, and the element
6896 // is a non-constant being inserted into an element other than the low one,
6897 // we can't use a constant pool load. Instead, use SCALAR_TO_VECTOR (aka
6898 // movd/movss) to move this into the low element, then shuffle it into
6900 if (EVTBits == 32) {
6901 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
6903 // If using the new shuffle lowering, just directly insert this.
6904 if (ExperimentalVectorShuffleLowering)
6905 return getShuffleVectorZeroOrUndef(Item, Idx, NumZero > 0, Subtarget, DAG);
6907 // Turn it into a shuffle of zero and zero-extended scalar to vector.
6908 Item = getShuffleVectorZeroOrUndef(Item, 0, NumZero > 0, Subtarget, DAG);
6909 SmallVector<int, 8> MaskVec;
6910 for (unsigned i = 0; i != NumElems; ++i)
6911 MaskVec.push_back(i == Idx ? 0 : 1);
6912 return DAG.getVectorShuffle(VT, dl, Item, DAG.getUNDEF(VT), &MaskVec[0]);
6916 // Splat is obviously ok. Let legalizer expand it to a shuffle.
6917 if (Values.size() == 1) {
6918 if (EVTBits == 32) {
6919 // Instead of a shuffle like this:
6920 // shuffle (scalar_to_vector (load (ptr + 4))), undef, <0, 0, 0, 0>
6921 // Check if it's possible to issue this instead.
6922 // shuffle (vload ptr)), undef, <1, 1, 1, 1>
6923 unsigned Idx = countTrailingZeros(NonZeros);
6924 SDValue Item = Op.getOperand(Idx);
6925 if (Op.getNode()->isOnlyUserOf(Item.getNode()))
6926 return LowerAsSplatVectorLoad(Item, VT, dl, DAG);
6931 // A vector full of immediates; various special cases are already
6932 // handled, so this is best done with a single constant-pool load.
6936 // For AVX-length vectors, build the individual 128-bit pieces and use
6937 // shuffles to put them in place.
6938 if (VT.is256BitVector() || VT.is512BitVector()) {
6939 SmallVector<SDValue, 64> V;
6940 for (unsigned i = 0; i != NumElems; ++i)
6941 V.push_back(Op.getOperand(i));
6943 EVT HVT = EVT::getVectorVT(*DAG.getContext(), ExtVT, NumElems/2);
6945 // Build both the lower and upper subvector.
6946 SDValue Lower = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT,
6947 makeArrayRef(&V[0], NumElems/2));
6948 SDValue Upper = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT,
6949 makeArrayRef(&V[NumElems / 2], NumElems/2));
6951 // Recreate the wider vector with the lower and upper part.
6952 if (VT.is256BitVector())
6953 return Concat128BitVectors(Lower, Upper, VT, NumElems, DAG, dl);
6954 return Concat256BitVectors(Lower, Upper, VT, NumElems, DAG, dl);
6957 // Let legalizer expand 2-wide build_vectors.
6958 if (EVTBits == 64) {
6959 if (NumNonZero == 1) {
6960 // One half is zero or undef.
6961 unsigned Idx = countTrailingZeros(NonZeros);
6962 SDValue V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT,
6963 Op.getOperand(Idx));
6964 return getShuffleVectorZeroOrUndef(V2, Idx, true, Subtarget, DAG);
6969 // If element VT is < 32 bits, convert it to inserts into a zero vector.
6970 if (EVTBits == 8 && NumElems == 16) {
6971 SDValue V = LowerBuildVectorv16i8(Op, NonZeros,NumNonZero,NumZero, DAG,
6973 if (V.getNode()) return V;
6976 if (EVTBits == 16 && NumElems == 8) {
6977 SDValue V = LowerBuildVectorv8i16(Op, NonZeros,NumNonZero,NumZero, DAG,
6979 if (V.getNode()) return V;
6982 // If element VT is == 32 bits and has 4 elems, try to generate an INSERTPS
6983 if (EVTBits == 32 && NumElems == 4) {
6984 SDValue V = LowerBuildVectorv4x32(Op, NumElems, NonZeros, NumNonZero,
6985 NumZero, DAG, Subtarget, *this);
6990 // If element VT is == 32 bits, turn it into a number of shuffles.
6991 SmallVector<SDValue, 8> V(NumElems);
6992 if (NumElems == 4 && NumZero > 0) {
6993 for (unsigned i = 0; i < 4; ++i) {
6994 bool isZero = !(NonZeros & (1 << i));
6996 V[i] = getZeroVector(VT, Subtarget, DAG, dl);
6998 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
7001 for (unsigned i = 0; i < 2; ++i) {
7002 switch ((NonZeros & (0x3 << i*2)) >> (i*2)) {
7005 V[i] = V[i*2]; // Must be a zero vector.
7008 V[i] = getMOVL(DAG, dl, VT, V[i*2+1], V[i*2]);
7011 V[i] = getMOVL(DAG, dl, VT, V[i*2], V[i*2+1]);
7014 V[i] = getUnpackl(DAG, dl, VT, V[i*2], V[i*2+1]);
7019 bool Reverse1 = (NonZeros & 0x3) == 2;
7020 bool Reverse2 = ((NonZeros & (0x3 << 2)) >> 2) == 2;
7024 static_cast<int>(Reverse2 ? NumElems+1 : NumElems),
7025 static_cast<int>(Reverse2 ? NumElems : NumElems+1)
7027 return DAG.getVectorShuffle(VT, dl, V[0], V[1], &MaskVec[0]);
7030 if (Values.size() > 1 && VT.is128BitVector()) {
7031 // Check for a build vector of consecutive loads.
7032 for (unsigned i = 0; i < NumElems; ++i)
7033 V[i] = Op.getOperand(i);
7035 // Check for elements which are consecutive loads.
7036 SDValue LD = EltsFromConsecutiveLoads(VT, V, dl, DAG, false);
7040 // Check for a build vector from mostly shuffle plus few inserting.
7041 SDValue Sh = buildFromShuffleMostly(Op, DAG);
7045 // For SSE 4.1, use insertps to put the high elements into the low element.
7046 if (getSubtarget()->hasSSE41()) {
7048 if (Op.getOperand(0).getOpcode() != ISD::UNDEF)
7049 Result = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(0));
7051 Result = DAG.getUNDEF(VT);
7053 for (unsigned i = 1; i < NumElems; ++i) {
7054 if (Op.getOperand(i).getOpcode() == ISD::UNDEF) continue;
7055 Result = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Result,
7056 Op.getOperand(i), DAG.getIntPtrConstant(i));
7061 // Otherwise, expand into a number of unpckl*, start by extending each of
7062 // our (non-undef) elements to the full vector width with the element in the
7063 // bottom slot of the vector (which generates no code for SSE).
7064 for (unsigned i = 0; i < NumElems; ++i) {
7065 if (Op.getOperand(i).getOpcode() != ISD::UNDEF)
7066 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
7068 V[i] = DAG.getUNDEF(VT);
7071 // Next, we iteratively mix elements, e.g. for v4f32:
7072 // Step 1: unpcklps 0, 2 ==> X: <?, ?, 2, 0>
7073 // : unpcklps 1, 3 ==> Y: <?, ?, 3, 1>
7074 // Step 2: unpcklps X, Y ==> <3, 2, 1, 0>
7075 unsigned EltStride = NumElems >> 1;
7076 while (EltStride != 0) {
7077 for (unsigned i = 0; i < EltStride; ++i) {
7078 // If V[i+EltStride] is undef and this is the first round of mixing,
7079 // then it is safe to just drop this shuffle: V[i] is already in the
7080 // right place, the one element (since it's the first round) being
7081 // inserted as undef can be dropped. This isn't safe for successive
7082 // rounds because they will permute elements within both vectors.
7083 if (V[i+EltStride].getOpcode() == ISD::UNDEF &&
7084 EltStride == NumElems/2)
7087 V[i] = getUnpackl(DAG, dl, VT, V[i], V[i + EltStride]);
7096 // LowerAVXCONCAT_VECTORS - 256-bit AVX can use the vinsertf128 instruction
7097 // to create 256-bit vectors from two other 128-bit ones.
7098 static SDValue LowerAVXCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
7100 MVT ResVT = Op.getSimpleValueType();
7102 assert((ResVT.is256BitVector() ||
7103 ResVT.is512BitVector()) && "Value type must be 256-/512-bit wide");
7105 SDValue V1 = Op.getOperand(0);
7106 SDValue V2 = Op.getOperand(1);
7107 unsigned NumElems = ResVT.getVectorNumElements();
7108 if(ResVT.is256BitVector())
7109 return Concat128BitVectors(V1, V2, ResVT, NumElems, DAG, dl);
7111 if (Op.getNumOperands() == 4) {
7112 MVT HalfVT = MVT::getVectorVT(ResVT.getScalarType(),
7113 ResVT.getVectorNumElements()/2);
7114 SDValue V3 = Op.getOperand(2);
7115 SDValue V4 = Op.getOperand(3);
7116 return Concat256BitVectors(Concat128BitVectors(V1, V2, HalfVT, NumElems/2, DAG, dl),
7117 Concat128BitVectors(V3, V4, HalfVT, NumElems/2, DAG, dl), ResVT, NumElems, DAG, dl);
7119 return Concat256BitVectors(V1, V2, ResVT, NumElems, DAG, dl);
7122 static SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
7123 MVT LLVM_ATTRIBUTE_UNUSED VT = Op.getSimpleValueType();
7124 assert((VT.is256BitVector() && Op.getNumOperands() == 2) ||
7125 (VT.is512BitVector() && (Op.getNumOperands() == 2 ||
7126 Op.getNumOperands() == 4)));
7128 // AVX can use the vinsertf128 instruction to create 256-bit vectors
7129 // from two other 128-bit ones.
7131 // 512-bit vector may contain 2 256-bit vectors or 4 128-bit vectors
7132 return LowerAVXCONCAT_VECTORS(Op, DAG);
7136 //===----------------------------------------------------------------------===//
7137 // Vector shuffle lowering
7139 // This is an experimental code path for lowering vector shuffles on x86. It is
7140 // designed to handle arbitrary vector shuffles and blends, gracefully
7141 // degrading performance as necessary. It works hard to recognize idiomatic
7142 // shuffles and lower them to optimal instruction patterns without leaving
7143 // a framework that allows reasonably efficient handling of all vector shuffle
7145 //===----------------------------------------------------------------------===//
7147 /// \brief Tiny helper function to identify a no-op mask.
7149 /// This is a somewhat boring predicate function. It checks whether the mask
7150 /// array input, which is assumed to be a single-input shuffle mask of the kind
7151 /// used by the X86 shuffle instructions (not a fully general
7152 /// ShuffleVectorSDNode mask) requires any shuffles to occur. Both undef and an
7153 /// in-place shuffle are 'no-op's.
7154 static bool isNoopShuffleMask(ArrayRef<int> Mask) {
7155 for (int i = 0, Size = Mask.size(); i < Size; ++i)
7156 if (Mask[i] != -1 && Mask[i] != i)
7161 /// \brief Helper function to classify a mask as a single-input mask.
7163 /// This isn't a generic single-input test because in the vector shuffle
7164 /// lowering we canonicalize single inputs to be the first input operand. This
7165 /// means we can more quickly test for a single input by only checking whether
7166 /// an input from the second operand exists. We also assume that the size of
7167 /// mask corresponds to the size of the input vectors which isn't true in the
7168 /// fully general case.
7169 static bool isSingleInputShuffleMask(ArrayRef<int> Mask) {
7171 if (M >= (int)Mask.size())
7176 // Hide this symbol with an anonymous namespace instead of 'static' so that MSVC
7177 // 2013 will allow us to use it as a non-type template parameter.
7180 /// \brief Implementation of the \c isShuffleEquivalent variadic functor.
7182 /// See its documentation for details.
7183 bool isShuffleEquivalentImpl(ArrayRef<int> Mask, ArrayRef<const int *> Args) {
7184 if (Mask.size() != Args.size())
7186 for (int i = 0, e = Mask.size(); i < e; ++i) {
7187 assert(*Args[i] >= 0 && "Arguments must be positive integers!");
7188 if (Mask[i] != -1 && Mask[i] != *Args[i])
7196 /// \brief Checks whether a shuffle mask is equivalent to an explicit list of
7199 /// This is a fast way to test a shuffle mask against a fixed pattern:
7201 /// if (isShuffleEquivalent(Mask, 3, 2, 1, 0)) { ... }
7203 /// It returns true if the mask is exactly as wide as the argument list, and
7204 /// each element of the mask is either -1 (signifying undef) or the value given
7205 /// in the argument.
7206 static const VariadicFunction1<
7207 bool, ArrayRef<int>, int, isShuffleEquivalentImpl> isShuffleEquivalent = {};
7209 /// \brief Get a 4-lane 8-bit shuffle immediate for a mask.
7211 /// This helper function produces an 8-bit shuffle immediate corresponding to
7212 /// the ubiquitous shuffle encoding scheme used in x86 instructions for
7213 /// shuffling 4 lanes. It can be used with most of the PSHUF instructions for
7216 /// NB: We rely heavily on "undef" masks preserving the input lane.
7217 static SDValue getV4X86ShuffleImm8ForMask(ArrayRef<int> Mask,
7218 SelectionDAG &DAG) {
7219 assert(Mask.size() == 4 && "Only 4-lane shuffle masks");
7220 assert(Mask[0] >= -1 && Mask[0] < 4 && "Out of bound mask element!");
7221 assert(Mask[1] >= -1 && Mask[1] < 4 && "Out of bound mask element!");
7222 assert(Mask[2] >= -1 && Mask[2] < 4 && "Out of bound mask element!");
7223 assert(Mask[3] >= -1 && Mask[3] < 4 && "Out of bound mask element!");
7226 Imm |= (Mask[0] == -1 ? 0 : Mask[0]) << 0;
7227 Imm |= (Mask[1] == -1 ? 1 : Mask[1]) << 2;
7228 Imm |= (Mask[2] == -1 ? 2 : Mask[2]) << 4;
7229 Imm |= (Mask[3] == -1 ? 3 : Mask[3]) << 6;
7230 return DAG.getConstant(Imm, MVT::i8);
7233 /// \brief Try to emit a blend instruction for a shuffle.
7235 /// This doesn't do any checks for the availability of instructions for blending
7236 /// these values. It relies on the availability of the X86ISD::BLENDI pattern to
7237 /// be matched in the backend with the type given. What it does check for is
7238 /// that the shuffle mask is in fact a blend.
7239 static SDValue lowerVectorShuffleAsBlend(SDLoc DL, MVT VT, SDValue V1,
7240 SDValue V2, ArrayRef<int> Mask,
7241 SelectionDAG &DAG) {
7243 unsigned BlendMask = 0;
7244 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
7245 if (Mask[i] >= Size) {
7246 if (Mask[i] != i + Size)
7247 return SDValue(); // Shuffled V2 input!
7248 BlendMask |= 1u << i;
7251 if (Mask[i] >= 0 && Mask[i] != i)
7252 return SDValue(); // Shuffled V1 input!
7254 switch (VT.SimpleTy) {
7259 return DAG.getNode(X86ISD::BLENDI, DL, VT, V1, V2,
7260 DAG.getConstant(BlendMask, MVT::i8));
7265 // For integer shuffles we need to expand the mask and cast the inputs to
7266 // v8i16s prior to blending.
7267 int Scale = 8 / VT.getVectorNumElements();
7269 for (int i = 0, Size = Mask.size(); i < Size; ++i)
7270 if (Mask[i] >= Size)
7271 for (int j = 0; j < Scale; ++j)
7272 BlendMask |= 1u << (i * Scale + j);
7274 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V1);
7275 V2 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V2);
7276 return DAG.getNode(ISD::BITCAST, DL, VT,
7277 DAG.getNode(X86ISD::BLENDI, DL, MVT::v8i16, V1, V2,
7278 DAG.getConstant(BlendMask, MVT::i8)));
7282 llvm_unreachable("Not a supported integer vector type!");
7286 /// \brief Try to lower a vector shuffle as a byte rotation.
7288 /// We have a generic PALIGNR instruction in x86 that will do an arbitrary
7289 /// byte-rotation of a the concatentation of two vectors. This routine will
7290 /// try to generically lower a vector shuffle through such an instruction. It
7291 /// does not check for the availability of PALIGNR-based lowerings, only the
7292 /// applicability of this strategy to the given mask. This matches shuffle
7293 /// vectors that look like:
7295 /// v8i16 [11, 12, 13, 14, 15, 0, 1, 2]
7297 /// Essentially it concatenates V1 and V2, shifts right by some number of
7298 /// elements, and takes the low elements as the result. Note that while this is
7299 /// specified as a *right shift* because x86 is little-endian, it is a *left
7300 /// rotate* of the vector lanes.
7302 /// Note that this only handles 128-bit vector widths currently.
7303 static SDValue lowerVectorShuffleAsByteRotate(SDLoc DL, MVT VT, SDValue V1,
7306 SelectionDAG &DAG) {
7307 assert(!isNoopShuffleMask(Mask) && "We shouldn't lower no-op shuffles!");
7309 // We need to detect various ways of spelling a rotation:
7310 // [11, 12, 13, 14, 15, 0, 1, 2]
7311 // [-1, 12, 13, 14, -1, -1, 1, -1]
7312 // [-1, -1, -1, -1, -1, -1, 1, 2]
7313 // [ 3, 4, 5, 6, 7, 8, 9, 10]
7314 // [-1, 4, 5, 6, -1, -1, 9, -1]
7315 // [-1, 4, 5, 6, -1, -1, -1, -1]
7318 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
7321 assert(Mask[i] >= 0 && "Only -1 is a valid negative mask element!");
7323 // Based on the mod-Size value of this mask element determine where
7324 // a rotated vector would have started.
7325 int StartIdx = i - (Mask[i] % Size);
7327 // The identity rotation isn't interesting, stop.
7330 // If we found the tail of a vector the rotation must be the missing
7331 // front. If we found the head of a vector, it must be how much of the head.
7332 int CandidateRotation = StartIdx < 0 ? -StartIdx : Size - StartIdx;
7335 Rotation = CandidateRotation;
7336 else if (Rotation != CandidateRotation)
7337 // The rotations don't match, so we can't match this mask.
7340 // Compute which value this mask is pointing at.
7341 SDValue MaskV = Mask[i] < Size ? V1 : V2;
7343 // Compute which of the two target values this index should be assigned to.
7344 // This reflects whether the high elements are remaining or the low elements
7346 SDValue &TargetV = StartIdx < 0 ? Hi : Lo;
7348 // Either set up this value if we've not encountered it before, or check
7349 // that it remains consistent.
7352 else if (TargetV != MaskV)
7353 // This may be a rotation, but it pulls from the inputs in some
7354 // unsupported interleaving.
7358 // Check that we successfully analyzed the mask, and normalize the results.
7359 assert(Rotation != 0 && "Failed to locate a viable rotation!");
7360 assert((Lo || Hi) && "Failed to find a rotated input vector!");
7366 // Cast the inputs to v16i8 to match PALIGNR.
7367 Lo = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, Lo);
7368 Hi = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, Hi);
7370 assert(VT.getSizeInBits() == 128 &&
7371 "Rotate-based lowering only supports 128-bit lowering!");
7372 assert(Mask.size() <= 16 &&
7373 "Can shuffle at most 16 bytes in a 128-bit vector!");
7374 // The actual rotate instruction rotates bytes, so we need to scale the
7375 // rotation based on how many bytes are in the vector.
7376 int Scale = 16 / Mask.size();
7378 return DAG.getNode(ISD::BITCAST, DL, VT,
7379 DAG.getNode(X86ISD::PALIGNR, DL, MVT::v16i8, Hi, Lo,
7380 DAG.getConstant(Rotation * Scale, MVT::i8)));
7383 /// \brief Compute whether each element of a shuffle is zeroable.
7385 /// A "zeroable" vector shuffle element is one which can be lowered to zero.
7386 /// Either it is an undef element in the shuffle mask, the element of the input
7387 /// referenced is undef, or the element of the input referenced is known to be
7388 /// zero. Many x86 shuffles can zero lanes cheaply and we often want to handle
7389 /// as many lanes with this technique as possible to simplify the remaining
7391 static SmallBitVector computeZeroableShuffleElements(ArrayRef<int> Mask,
7392 SDValue V1, SDValue V2) {
7393 SmallBitVector Zeroable(Mask.size(), false);
7395 bool V1IsZero = ISD::isBuildVectorAllZeros(V1.getNode());
7396 bool V2IsZero = ISD::isBuildVectorAllZeros(V2.getNode());
7398 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
7400 // Handle the easy cases.
7401 if (M < 0 || (M >= 0 && M < Size && V1IsZero) || (M >= Size && V2IsZero)) {
7406 // If this is an index into a build_vector node, dig out the input value and
7408 SDValue V = M < Size ? V1 : V2;
7409 if (V.getOpcode() != ISD::BUILD_VECTOR)
7412 SDValue Input = V.getOperand(M % Size);
7413 // The UNDEF opcode check really should be dead code here, but not quite
7414 // worth asserting on (it isn't invalid, just unexpected).
7415 if (Input.getOpcode() == ISD::UNDEF || X86::isZeroNode(Input))
7422 /// \brief Lower a vector shuffle as a zero or any extension.
7424 /// Given a specific number of elements, element bit width, and extension
7425 /// stride, produce either a zero or any extension based on the available
7426 /// features of the subtarget.
7427 static SDValue lowerVectorShuffleAsSpecificZeroOrAnyExtend(
7428 SDLoc DL, MVT VT, int NumElements, int Scale, bool AnyExt, SDValue InputV,
7429 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
7430 assert(Scale > 1 && "Need a scale to extend.");
7431 int EltBits = VT.getSizeInBits() / NumElements;
7432 assert((EltBits == 8 || EltBits == 16 || EltBits == 32) &&
7433 "Only 8, 16, and 32 bit elements can be extended.");
7434 assert(Scale * EltBits <= 64 && "Cannot zero extend past 64 bits.");
7436 // Found a valid zext mask! Try various lowering strategies based on the
7437 // input type and available ISA extensions.
7438 if (Subtarget->hasSSE41()) {
7439 MVT InputVT = MVT::getVectorVT(MVT::getIntegerVT(EltBits), NumElements);
7440 MVT ExtVT = MVT::getVectorVT(MVT::getIntegerVT(EltBits * Scale),
7441 NumElements / Scale);
7442 InputV = DAG.getNode(ISD::BITCAST, DL, InputVT, InputV);
7443 return DAG.getNode(ISD::BITCAST, DL, VT,
7444 DAG.getNode(X86ISD::VZEXT, DL, ExtVT, InputV));
7447 // For any extends we can cheat for larger element sizes and use shuffle
7448 // instructions that can fold with a load and/or copy.
7449 if (AnyExt && EltBits == 32) {
7450 int PSHUFDMask[4] = {0, -1, 1, -1};
7452 ISD::BITCAST, DL, VT,
7453 DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32,
7454 DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, InputV),
7455 getV4X86ShuffleImm8ForMask(PSHUFDMask, DAG)));
7457 if (AnyExt && EltBits == 16 && Scale > 2) {
7458 int PSHUFDMask[4] = {0, -1, 0, -1};
7459 InputV = DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32,
7460 DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, InputV),
7461 getV4X86ShuffleImm8ForMask(PSHUFDMask, DAG));
7462 int PSHUFHWMask[4] = {1, -1, -1, -1};
7464 ISD::BITCAST, DL, VT,
7465 DAG.getNode(X86ISD::PSHUFHW, DL, MVT::v8i16,
7466 DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, InputV),
7467 getV4X86ShuffleImm8ForMask(PSHUFHWMask, DAG)));
7470 // If this would require more than 2 unpack instructions to expand, use
7471 // pshufb when available. We can only use more than 2 unpack instructions
7472 // when zero extending i8 elements which also makes it easier to use pshufb.
7473 if (Scale > 4 && EltBits == 8 && Subtarget->hasSSSE3()) {
7474 assert(NumElements == 16 && "Unexpected byte vector width!");
7475 SDValue PSHUFBMask[16];
7476 for (int i = 0; i < 16; ++i)
7478 DAG.getConstant((i % Scale == 0) ? i / Scale : 0x80, MVT::i8);
7479 InputV = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, InputV);
7480 return DAG.getNode(ISD::BITCAST, DL, VT,
7481 DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8, InputV,
7482 DAG.getNode(ISD::BUILD_VECTOR, DL,
7483 MVT::v16i8, PSHUFBMask)));
7486 // Otherwise emit a sequence of unpacks.
7488 MVT InputVT = MVT::getVectorVT(MVT::getIntegerVT(EltBits), NumElements);
7489 SDValue Ext = AnyExt ? DAG.getUNDEF(InputVT)
7490 : getZeroVector(InputVT, Subtarget, DAG, DL);
7491 InputV = DAG.getNode(ISD::BITCAST, DL, InputVT, InputV);
7492 InputV = DAG.getNode(X86ISD::UNPCKL, DL, InputVT, InputV, Ext);
7496 } while (Scale > 1);
7497 return DAG.getNode(ISD::BITCAST, DL, VT, InputV);
7500 /// \brief Try to lower a vector shuffle as a zero extension on any micrarch.
7502 /// This routine will try to do everything in its power to cleverly lower
7503 /// a shuffle which happens to match the pattern of a zero extend. It doesn't
7504 /// check for the profitability of this lowering, it tries to aggressively
7505 /// match this pattern. It will use all of the micro-architectural details it
7506 /// can to emit an efficient lowering. It handles both blends with all-zero
7507 /// inputs to explicitly zero-extend and undef-lanes (sometimes undef due to
7508 /// masking out later).
7510 /// The reason we have dedicated lowering for zext-style shuffles is that they
7511 /// are both incredibly common and often quite performance sensitive.
7512 static SDValue lowerVectorShuffleAsZeroOrAnyExtend(
7513 SDLoc DL, MVT VT, SDValue V1, SDValue V2, ArrayRef<int> Mask,
7514 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
7515 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
7517 int Bits = VT.getSizeInBits();
7518 int NumElements = Mask.size();
7520 // Define a helper function to check a particular ext-scale and lower to it if
7522 auto Lower = [&](int Scale) -> SDValue {
7525 for (int i = 0; i < NumElements; ++i) {
7527 continue; // Valid anywhere but doesn't tell us anything.
7528 if (i % Scale != 0) {
7529 // Each of the extend elements needs to be zeroable.
7533 // We no lorger are in the anyext case.
7538 // Each of the base elements needs to be consecutive indices into the
7539 // same input vector.
7540 SDValue V = Mask[i] < NumElements ? V1 : V2;
7543 else if (InputV != V)
7544 return SDValue(); // Flip-flopping inputs.
7546 if (Mask[i] % NumElements != i / Scale)
7547 return SDValue(); // Non-consecutive strided elemenst.
7550 // If we fail to find an input, we have a zero-shuffle which should always
7551 // have already been handled.
7552 // FIXME: Maybe handle this here in case during blending we end up with one?
7556 return lowerVectorShuffleAsSpecificZeroOrAnyExtend(
7557 DL, VT, NumElements, Scale, AnyExt, InputV, Subtarget, DAG);
7560 // The widest scale possible for extending is to a 64-bit integer.
7561 assert(Bits % 64 == 0 &&
7562 "The number of bits in a vector must be divisible by 64 on x86!");
7563 int NumExtElements = Bits / 64;
7565 // Each iteration, try extending the elements half as much, but into twice as
7567 for (; NumExtElements < NumElements; NumExtElements *= 2) {
7568 assert(NumElements % NumExtElements == 0 &&
7569 "The input vector size must be divisble by the extended size.");
7570 if (SDValue V = Lower(NumElements / NumExtElements))
7574 // No viable ext lowering found.
7578 /// \brief Try to lower insertion of a single element into a zero vector.
7580 /// This is a common pattern that we have especially efficient patterns to lower
7581 /// across all subtarget feature sets.
7582 static SDValue lowerVectorShuffleAsElementInsertion(
7583 MVT VT, SDLoc DL, SDValue V1, SDValue V2, ArrayRef<int> Mask,
7584 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
7585 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
7587 int V2Index = std::find_if(Mask.begin(), Mask.end(),
7588 [&Mask](int M) { return M >= (int)Mask.size(); }) -
7590 if (Mask.size() == 2) {
7591 if (!Zeroable[V2Index ^ 1]) {
7592 // For 2-wide masks we may be able to just invert the inputs. We use an xor
7593 // with 2 to flip from {2,3} to {0,1} and vice versa.
7594 int InverseMask[2] = {Mask[0] < 0 ? -1 : (Mask[0] ^ 2),
7595 Mask[1] < 0 ? -1 : (Mask[1] ^ 2)};
7596 if (Zeroable[V2Index])
7597 return lowerVectorShuffleAsElementInsertion(VT, DL, V2, V1, InverseMask,
7603 for (int i = 0, Size = Mask.size(); i < Size; ++i)
7604 if (i != V2Index && !Zeroable[i])
7605 return SDValue(); // Not inserting into a zero vector.
7608 // Step over any bitcasts on either input so we can scan the actual
7609 // BUILD_VECTOR nodes.
7610 while (V1.getOpcode() == ISD::BITCAST)
7611 V1 = V1.getOperand(0);
7612 while (V2.getOpcode() == ISD::BITCAST)
7613 V2 = V2.getOperand(0);
7615 // Check for a single input from a SCALAR_TO_VECTOR node.
7616 // FIXME: All of this should be canonicalized into INSERT_VECTOR_ELT and
7617 // all the smarts here sunk into that routine. However, the current
7618 // lowering of BUILD_VECTOR makes that nearly impossible until the old
7619 // vector shuffle lowering is dead.
7620 if (!((V2.getOpcode() == ISD::SCALAR_TO_VECTOR &&
7621 Mask[V2Index] == (int)Mask.size()) ||
7622 V2.getOpcode() == ISD::BUILD_VECTOR))
7625 SDValue V2S = V2.getOperand(Mask[V2Index] - Mask.size());
7627 // First, we need to zext the scalar if it is smaller than an i32.
7629 MVT EltVT = VT.getVectorElementType();
7630 V2S = DAG.getNode(ISD::BITCAST, DL, EltVT, V2S);
7631 if (EltVT == MVT::i8 || EltVT == MVT::i16) {
7632 // Zero-extend directly to i32.
7634 V2S = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i32, V2S);
7637 V2 = DAG.getNode(X86ISD::VZEXT_MOVL, DL, ExtVT,
7638 DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, ExtVT, V2S));
7640 V2 = DAG.getNode(ISD::BITCAST, DL, VT, V2);
7643 // If we have 4 or fewer lanes we can cheaply shuffle the element into
7644 // the desired position. Otherwise it is more efficient to do a vector
7645 // shift left. We know that we can do a vector shift left because all
7646 // the inputs are zero.
7647 if (VT.isFloatingPoint() || VT.getVectorNumElements() <= 4) {
7648 SmallVector<int, 4> V2Shuffle(Mask.size(), 1);
7649 V2Shuffle[V2Index] = 0;
7650 V2 = DAG.getVectorShuffle(VT, DL, V2, DAG.getUNDEF(VT), V2Shuffle);
7652 V2 = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, V2);
7654 X86ISD::VSHLDQ, DL, MVT::v2i64, V2,
7656 V2Index * EltVT.getSizeInBits(),
7657 DAG.getTargetLoweringInfo().getScalarShiftAmountTy(MVT::v2i64)));
7658 V2 = DAG.getNode(ISD::BITCAST, DL, VT, V2);
7664 /// \brief Handle lowering of 2-lane 64-bit floating point shuffles.
7666 /// This is the basis function for the 2-lane 64-bit shuffles as we have full
7667 /// support for floating point shuffles but not integer shuffles. These
7668 /// instructions will incur a domain crossing penalty on some chips though so
7669 /// it is better to avoid lowering through this for integer vectors where
7671 static SDValue lowerV2F64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
7672 const X86Subtarget *Subtarget,
7673 SelectionDAG &DAG) {
7675 assert(Op.getSimpleValueType() == MVT::v2f64 && "Bad shuffle type!");
7676 assert(V1.getSimpleValueType() == MVT::v2f64 && "Bad operand type!");
7677 assert(V2.getSimpleValueType() == MVT::v2f64 && "Bad operand type!");
7678 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
7679 ArrayRef<int> Mask = SVOp->getMask();
7680 assert(Mask.size() == 2 && "Unexpected mask size for v2 shuffle!");
7682 if (isSingleInputShuffleMask(Mask)) {
7683 // Straight shuffle of a single input vector. Simulate this by using the
7684 // single input as both of the "inputs" to this instruction..
7685 unsigned SHUFPDMask = (Mask[0] == 1) | ((Mask[1] == 1) << 1);
7687 if (Subtarget->hasAVX()) {
7688 // If we have AVX, we can use VPERMILPS which will allow folding a load
7689 // into the shuffle.
7690 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v2f64, V1,
7691 DAG.getConstant(SHUFPDMask, MVT::i8));
7694 return DAG.getNode(X86ISD::SHUFP, SDLoc(Op), MVT::v2f64, V1, V1,
7695 DAG.getConstant(SHUFPDMask, MVT::i8));
7697 assert(Mask[0] >= 0 && Mask[0] < 2 && "Non-canonicalized blend!");
7698 assert(Mask[1] >= 2 && "Non-canonicalized blend!");
7700 // Use dedicated unpack instructions for masks that match their pattern.
7701 if (isShuffleEquivalent(Mask, 0, 2))
7702 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v2f64, V1, V2);
7703 if (isShuffleEquivalent(Mask, 1, 3))
7704 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v2f64, V1, V2);
7706 // If we have a single input, insert that into V1 if we can do so cheaply.
7707 if ((Mask[0] >= 2) + (Mask[1] >= 2) == 1)
7708 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
7709 MVT::v2f64, DL, V1, V2, Mask, Subtarget, DAG))
7712 if (Subtarget->hasSSE41())
7714 lowerVectorShuffleAsBlend(DL, MVT::v2f64, V1, V2, Mask, DAG))
7717 unsigned SHUFPDMask = (Mask[0] == 1) | (((Mask[1] - 2) == 1) << 1);
7718 return DAG.getNode(X86ISD::SHUFP, SDLoc(Op), MVT::v2f64, V1, V2,
7719 DAG.getConstant(SHUFPDMask, MVT::i8));
7722 /// \brief Handle lowering of 2-lane 64-bit integer shuffles.
7724 /// Tries to lower a 2-lane 64-bit shuffle using shuffle operations provided by
7725 /// the integer unit to minimize domain crossing penalties. However, for blends
7726 /// it falls back to the floating point shuffle operation with appropriate bit
7728 static SDValue lowerV2I64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
7729 const X86Subtarget *Subtarget,
7730 SelectionDAG &DAG) {
7732 assert(Op.getSimpleValueType() == MVT::v2i64 && "Bad shuffle type!");
7733 assert(V1.getSimpleValueType() == MVT::v2i64 && "Bad operand type!");
7734 assert(V2.getSimpleValueType() == MVT::v2i64 && "Bad operand type!");
7735 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
7736 ArrayRef<int> Mask = SVOp->getMask();
7737 assert(Mask.size() == 2 && "Unexpected mask size for v2 shuffle!");
7739 if (isSingleInputShuffleMask(Mask)) {
7740 // Straight shuffle of a single input vector. For everything from SSE2
7741 // onward this has a single fast instruction with no scary immediates.
7742 // We have to map the mask as it is actually a v4i32 shuffle instruction.
7743 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, V1);
7744 int WidenedMask[4] = {
7745 std::max(Mask[0], 0) * 2, std::max(Mask[0], 0) * 2 + 1,
7746 std::max(Mask[1], 0) * 2, std::max(Mask[1], 0) * 2 + 1};
7748 ISD::BITCAST, DL, MVT::v2i64,
7749 DAG.getNode(X86ISD::PSHUFD, SDLoc(Op), MVT::v4i32, V1,
7750 getV4X86ShuffleImm8ForMask(WidenedMask, DAG)));
7753 // Use dedicated unpack instructions for masks that match their pattern.
7754 if (isShuffleEquivalent(Mask, 0, 2))
7755 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v2i64, V1, V2);
7756 if (isShuffleEquivalent(Mask, 1, 3))
7757 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v2i64, V1, V2);
7759 // If we have a single input from V2 insert that into V1 if we can do so
7761 if ((Mask[0] >= 2) + (Mask[1] >= 2) == 1)
7762 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
7763 MVT::v2i64, DL, V1, V2, Mask, Subtarget, DAG))
7766 if (Subtarget->hasSSE41())
7768 lowerVectorShuffleAsBlend(DL, MVT::v2i64, V1, V2, Mask, DAG))
7771 // Try to use rotation instructions if available.
7772 if (Subtarget->hasSSSE3())
7773 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
7774 DL, MVT::v2i64, V1, V2, Mask, DAG))
7777 // We implement this with SHUFPD which is pretty lame because it will likely
7778 // incur 2 cycles of stall for integer vectors on Nehalem and older chips.
7779 // However, all the alternatives are still more cycles and newer chips don't
7780 // have this problem. It would be really nice if x86 had better shuffles here.
7781 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v2f64, V1);
7782 V2 = DAG.getNode(ISD::BITCAST, DL, MVT::v2f64, V2);
7783 return DAG.getNode(ISD::BITCAST, DL, MVT::v2i64,
7784 DAG.getVectorShuffle(MVT::v2f64, DL, V1, V2, Mask));
7787 /// \brief Lower a vector shuffle using the SHUFPS instruction.
7789 /// This is a helper routine dedicated to lowering vector shuffles using SHUFPS.
7790 /// It makes no assumptions about whether this is the *best* lowering, it simply
7792 static SDValue lowerVectorShuffleWithSHUPFS(SDLoc DL, MVT VT,
7793 ArrayRef<int> Mask, SDValue V1,
7794 SDValue V2, SelectionDAG &DAG) {
7795 SDValue LowV = V1, HighV = V2;
7796 int NewMask[4] = {Mask[0], Mask[1], Mask[2], Mask[3]};
7799 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; });
7801 if (NumV2Elements == 1) {
7803 std::find_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; }) -
7806 // Compute the index adjacent to V2Index and in the same half by toggling
7808 int V2AdjIndex = V2Index ^ 1;
7810 if (Mask[V2AdjIndex] == -1) {
7811 // Handles all the cases where we have a single V2 element and an undef.
7812 // This will only ever happen in the high lanes because we commute the
7813 // vector otherwise.
7815 std::swap(LowV, HighV);
7816 NewMask[V2Index] -= 4;
7818 // Handle the case where the V2 element ends up adjacent to a V1 element.
7819 // To make this work, blend them together as the first step.
7820 int V1Index = V2AdjIndex;
7821 int BlendMask[4] = {Mask[V2Index] - 4, 0, Mask[V1Index], 0};
7822 V2 = DAG.getNode(X86ISD::SHUFP, DL, VT, V2, V1,
7823 getV4X86ShuffleImm8ForMask(BlendMask, DAG));
7825 // Now proceed to reconstruct the final blend as we have the necessary
7826 // high or low half formed.
7833 NewMask[V1Index] = 2; // We put the V1 element in V2[2].
7834 NewMask[V2Index] = 0; // We shifted the V2 element into V2[0].
7836 } else if (NumV2Elements == 2) {
7837 if (Mask[0] < 4 && Mask[1] < 4) {
7838 // Handle the easy case where we have V1 in the low lanes and V2 in the
7839 // high lanes. We never see this reversed because we sort the shuffle.
7843 // We have a mixture of V1 and V2 in both low and high lanes. Rather than
7844 // trying to place elements directly, just blend them and set up the final
7845 // shuffle to place them.
7847 // The first two blend mask elements are for V1, the second two are for
7849 int BlendMask[4] = {Mask[0] < 4 ? Mask[0] : Mask[1],
7850 Mask[2] < 4 ? Mask[2] : Mask[3],
7851 (Mask[0] >= 4 ? Mask[0] : Mask[1]) - 4,
7852 (Mask[2] >= 4 ? Mask[2] : Mask[3]) - 4};
7853 V1 = DAG.getNode(X86ISD::SHUFP, DL, VT, V1, V2,
7854 getV4X86ShuffleImm8ForMask(BlendMask, DAG));
7856 // Now we do a normal shuffle of V1 by giving V1 as both operands to
7859 NewMask[0] = Mask[0] < 4 ? 0 : 2;
7860 NewMask[1] = Mask[0] < 4 ? 2 : 0;
7861 NewMask[2] = Mask[2] < 4 ? 1 : 3;
7862 NewMask[3] = Mask[2] < 4 ? 3 : 1;
7865 return DAG.getNode(X86ISD::SHUFP, DL, VT, LowV, HighV,
7866 getV4X86ShuffleImm8ForMask(NewMask, DAG));
7869 /// \brief Lower 4-lane 32-bit floating point shuffles.
7871 /// Uses instructions exclusively from the floating point unit to minimize
7872 /// domain crossing penalties, as these are sufficient to implement all v4f32
7874 static SDValue lowerV4F32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
7875 const X86Subtarget *Subtarget,
7876 SelectionDAG &DAG) {
7878 assert(Op.getSimpleValueType() == MVT::v4f32 && "Bad shuffle type!");
7879 assert(V1.getSimpleValueType() == MVT::v4f32 && "Bad operand type!");
7880 assert(V2.getSimpleValueType() == MVT::v4f32 && "Bad operand type!");
7881 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
7882 ArrayRef<int> Mask = SVOp->getMask();
7883 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
7886 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; });
7888 if (NumV2Elements == 0) {
7889 if (Subtarget->hasAVX()) {
7890 // If we have AVX, we can use VPERMILPS which will allow folding a load
7891 // into the shuffle.
7892 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v4f32, V1,
7893 getV4X86ShuffleImm8ForMask(Mask, DAG));
7896 // Otherwise, use a straight shuffle of a single input vector. We pass the
7897 // input vector to both operands to simulate this with a SHUFPS.
7898 return DAG.getNode(X86ISD::SHUFP, DL, MVT::v4f32, V1, V1,
7899 getV4X86ShuffleImm8ForMask(Mask, DAG));
7902 // Use dedicated unpack instructions for masks that match their pattern.
7903 if (isShuffleEquivalent(Mask, 0, 4, 1, 5))
7904 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4f32, V1, V2);
7905 if (isShuffleEquivalent(Mask, 2, 6, 3, 7))
7906 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4f32, V1, V2);
7908 // There are special ways we can lower some single-element blends. However, we
7909 // have custom ways we can lower more complex single-element blends below that
7910 // we defer to if both this and BLENDPS fail to match, so restrict this to
7911 // when the V2 input is targeting element 0 of the mask -- that is the fast
7913 if (NumV2Elements == 1 && Mask[0] >= 4)
7914 if (SDValue V = lowerVectorShuffleAsElementInsertion(MVT::v4f32, DL, V1, V2,
7915 Mask, Subtarget, DAG))
7918 if (Subtarget->hasSSE41())
7920 lowerVectorShuffleAsBlend(DL, MVT::v4f32, V1, V2, Mask, DAG))
7923 // Check for whether we can use INSERTPS to perform the blend. We only use
7924 // INSERTPS when the V1 elements are already in the correct locations
7925 // because otherwise we can just always use two SHUFPS instructions which
7926 // are much smaller to encode than a SHUFPS and an INSERTPS.
7927 if (NumV2Elements == 1 && Subtarget->hasSSE41()) {
7929 std::find_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; }) -
7932 // When using INSERTPS we can zero any lane of the destination. Collect
7933 // the zero inputs into a mask and drop them from the lanes of V1 which
7934 // actually need to be present as inputs to the INSERTPS.
7935 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
7937 // Synthesize a shuffle mask for the non-zero and non-v2 inputs.
7938 bool InsertNeedsShuffle = false;
7940 for (int i = 0; i < 4; ++i)
7944 } else if (Mask[i] != i) {
7945 InsertNeedsShuffle = true;
7950 // We don't want to use INSERTPS or other insertion techniques if it will
7951 // require shuffling anyways.
7952 if (!InsertNeedsShuffle) {
7953 // If all of V1 is zeroable, replace it with undef.
7954 if ((ZMask | 1 << V2Index) == 0xF)
7955 V1 = DAG.getUNDEF(MVT::v4f32);
7957 unsigned InsertPSMask = (Mask[V2Index] - 4) << 6 | V2Index << 4 | ZMask;
7958 assert((InsertPSMask & ~0xFFu) == 0 && "Invalid mask!");
7960 // Insert the V2 element into the desired position.
7961 return DAG.getNode(X86ISD::INSERTPS, DL, MVT::v4f32, V1, V2,
7962 DAG.getConstant(InsertPSMask, MVT::i8));
7966 // Otherwise fall back to a SHUFPS lowering strategy.
7967 return lowerVectorShuffleWithSHUPFS(DL, MVT::v4f32, Mask, V1, V2, DAG);
7970 /// \brief Lower 4-lane i32 vector shuffles.
7972 /// We try to handle these with integer-domain shuffles where we can, but for
7973 /// blends we use the floating point domain blend instructions.
7974 static SDValue lowerV4I32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
7975 const X86Subtarget *Subtarget,
7976 SelectionDAG &DAG) {
7978 assert(Op.getSimpleValueType() == MVT::v4i32 && "Bad shuffle type!");
7979 assert(V1.getSimpleValueType() == MVT::v4i32 && "Bad operand type!");
7980 assert(V2.getSimpleValueType() == MVT::v4i32 && "Bad operand type!");
7981 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
7982 ArrayRef<int> Mask = SVOp->getMask();
7983 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
7986 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; });
7988 if (NumV2Elements == 0) {
7989 // Straight shuffle of a single input vector. For everything from SSE2
7990 // onward this has a single fast instruction with no scary immediates.
7991 // We coerce the shuffle pattern to be compatible with UNPCK instructions
7992 // but we aren't actually going to use the UNPCK instruction because doing
7993 // so prevents folding a load into this instruction or making a copy.
7994 const int UnpackLoMask[] = {0, 0, 1, 1};
7995 const int UnpackHiMask[] = {2, 2, 3, 3};
7996 if (isShuffleEquivalent(Mask, 0, 0, 1, 1))
7997 Mask = UnpackLoMask;
7998 else if (isShuffleEquivalent(Mask, 2, 2, 3, 3))
7999 Mask = UnpackHiMask;
8001 return DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32, V1,
8002 getV4X86ShuffleImm8ForMask(Mask, DAG));
8005 // Whenever we can lower this as a zext, that instruction is strictly faster
8006 // than any alternative.
8007 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(DL, MVT::v4i32, V1, V2,
8008 Mask, Subtarget, DAG))
8011 // Use dedicated unpack instructions for masks that match their pattern.
8012 if (isShuffleEquivalent(Mask, 0, 4, 1, 5))
8013 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4i32, V1, V2);
8014 if (isShuffleEquivalent(Mask, 2, 6, 3, 7))
8015 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4i32, V1, V2);
8017 // There are special ways we can lower some single-element blends.
8018 if (NumV2Elements == 1)
8019 if (SDValue V = lowerVectorShuffleAsElementInsertion(MVT::v4i32, DL, V1, V2,
8020 Mask, Subtarget, DAG))
8023 if (Subtarget->hasSSE41())
8025 lowerVectorShuffleAsBlend(DL, MVT::v4i32, V1, V2, Mask, DAG))
8028 // Try to use rotation instructions if available.
8029 if (Subtarget->hasSSSE3())
8030 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
8031 DL, MVT::v4i32, V1, V2, Mask, DAG))
8034 // We implement this with SHUFPS because it can blend from two vectors.
8035 // Because we're going to eventually use SHUFPS, we use SHUFPS even to build
8036 // up the inputs, bypassing domain shift penalties that we would encur if we
8037 // directly used PSHUFD on Nehalem and older. For newer chips, this isn't
8039 return DAG.getNode(ISD::BITCAST, DL, MVT::v4i32,
8040 DAG.getVectorShuffle(
8042 DAG.getNode(ISD::BITCAST, DL, MVT::v4f32, V1),
8043 DAG.getNode(ISD::BITCAST, DL, MVT::v4f32, V2), Mask));
8046 /// \brief Lowering of single-input v8i16 shuffles is the cornerstone of SSE2
8047 /// shuffle lowering, and the most complex part.
8049 /// The lowering strategy is to try to form pairs of input lanes which are
8050 /// targeted at the same half of the final vector, and then use a dword shuffle
8051 /// to place them onto the right half, and finally unpack the paired lanes into
8052 /// their final position.
8054 /// The exact breakdown of how to form these dword pairs and align them on the
8055 /// correct sides is really tricky. See the comments within the function for
8056 /// more of the details.
8057 static SDValue lowerV8I16SingleInputVectorShuffle(
8058 SDLoc DL, SDValue V, MutableArrayRef<int> Mask,
8059 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
8060 assert(V.getSimpleValueType() == MVT::v8i16 && "Bad input type!");
8061 MutableArrayRef<int> LoMask = Mask.slice(0, 4);
8062 MutableArrayRef<int> HiMask = Mask.slice(4, 4);
8064 SmallVector<int, 4> LoInputs;
8065 std::copy_if(LoMask.begin(), LoMask.end(), std::back_inserter(LoInputs),
8066 [](int M) { return M >= 0; });
8067 std::sort(LoInputs.begin(), LoInputs.end());
8068 LoInputs.erase(std::unique(LoInputs.begin(), LoInputs.end()), LoInputs.end());
8069 SmallVector<int, 4> HiInputs;
8070 std::copy_if(HiMask.begin(), HiMask.end(), std::back_inserter(HiInputs),
8071 [](int M) { return M >= 0; });
8072 std::sort(HiInputs.begin(), HiInputs.end());
8073 HiInputs.erase(std::unique(HiInputs.begin(), HiInputs.end()), HiInputs.end());
8075 std::lower_bound(LoInputs.begin(), LoInputs.end(), 4) - LoInputs.begin();
8076 int NumHToL = LoInputs.size() - NumLToL;
8078 std::lower_bound(HiInputs.begin(), HiInputs.end(), 4) - HiInputs.begin();
8079 int NumHToH = HiInputs.size() - NumLToH;
8080 MutableArrayRef<int> LToLInputs(LoInputs.data(), NumLToL);
8081 MutableArrayRef<int> LToHInputs(HiInputs.data(), NumLToH);
8082 MutableArrayRef<int> HToLInputs(LoInputs.data() + NumLToL, NumHToL);
8083 MutableArrayRef<int> HToHInputs(HiInputs.data() + NumLToH, NumHToH);
8085 // Use dedicated unpack instructions for masks that match their pattern.
8086 if (isShuffleEquivalent(Mask, 0, 0, 1, 1, 2, 2, 3, 3))
8087 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8i16, V, V);
8088 if (isShuffleEquivalent(Mask, 4, 4, 5, 5, 6, 6, 7, 7))
8089 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8i16, V, V);
8091 // Try to use rotation instructions if available.
8092 if (Subtarget->hasSSSE3())
8093 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
8094 DL, MVT::v8i16, V, V, Mask, DAG))
8097 // Simplify the 1-into-3 and 3-into-1 cases with a single pshufd. For all
8098 // such inputs we can swap two of the dwords across the half mark and end up
8099 // with <=2 inputs to each half in each half. Once there, we can fall through
8100 // to the generic code below. For example:
8102 // Input: [a, b, c, d, e, f, g, h] -PSHUFD[0,2,1,3]-> [a, b, e, f, c, d, g, h]
8103 // Mask: [0, 1, 2, 7, 4, 5, 6, 3] -----------------> [0, 1, 4, 7, 2, 3, 6, 5]
8105 // However in some very rare cases we have a 1-into-3 or 3-into-1 on one half
8106 // and an existing 2-into-2 on the other half. In this case we may have to
8107 // pre-shuffle the 2-into-2 half to avoid turning it into a 3-into-1 or
8108 // 1-into-3 which could cause us to cycle endlessly fixing each side in turn.
8109 // Fortunately, we don't have to handle anything but a 2-into-2 pattern
8110 // because any other situation (including a 3-into-1 or 1-into-3 in the other
8111 // half than the one we target for fixing) will be fixed when we re-enter this
8112 // path. We will also combine away any sequence of PSHUFD instructions that
8113 // result into a single instruction. Here is an example of the tricky case:
8115 // Input: [a, b, c, d, e, f, g, h] -PSHUFD[0,2,1,3]-> [a, b, e, f, c, d, g, h]
8116 // Mask: [3, 7, 1, 0, 2, 7, 3, 5] -THIS-IS-BAD!!!!-> [5, 7, 1, 0, 4, 7, 5, 3]
8118 // This now has a 1-into-3 in the high half! Instead, we do two shuffles:
8120 // Input: [a, b, c, d, e, f, g, h] PSHUFHW[0,2,1,3]-> [a, b, c, d, e, g, f, h]
8121 // Mask: [3, 7, 1, 0, 2, 7, 3, 5] -----------------> [3, 7, 1, 0, 2, 7, 3, 6]
8123 // Input: [a, b, c, d, e, g, f, h] -PSHUFD[0,2,1,3]-> [a, b, e, g, c, d, f, h]
8124 // Mask: [3, 7, 1, 0, 2, 7, 3, 6] -----------------> [5, 7, 1, 0, 4, 7, 5, 6]
8126 // The result is fine to be handled by the generic logic.
8127 auto balanceSides = [&](ArrayRef<int> AToAInputs, ArrayRef<int> BToAInputs,
8128 ArrayRef<int> BToBInputs, ArrayRef<int> AToBInputs,
8129 int AOffset, int BOffset) {
8130 assert((AToAInputs.size() == 3 || AToAInputs.size() == 1) &&
8131 "Must call this with A having 3 or 1 inputs from the A half.");
8132 assert((BToAInputs.size() == 1 || BToAInputs.size() == 3) &&
8133 "Must call this with B having 1 or 3 inputs from the B half.");
8134 assert(AToAInputs.size() + BToAInputs.size() == 4 &&
8135 "Must call this with either 3:1 or 1:3 inputs (summing to 4).");
8137 // Compute the index of dword with only one word among the three inputs in
8138 // a half by taking the sum of the half with three inputs and subtracting
8139 // the sum of the actual three inputs. The difference is the remaining
8142 int &TripleDWord = AToAInputs.size() == 3 ? ADWord : BDWord;
8143 int &OneInputDWord = AToAInputs.size() == 3 ? BDWord : ADWord;
8144 int TripleInputOffset = AToAInputs.size() == 3 ? AOffset : BOffset;
8145 ArrayRef<int> TripleInputs = AToAInputs.size() == 3 ? AToAInputs : BToAInputs;
8146 int OneInput = AToAInputs.size() == 3 ? BToAInputs[0] : AToAInputs[0];
8147 int TripleInputSum = 0 + 1 + 2 + 3 + (4 * TripleInputOffset);
8148 int TripleNonInputIdx =
8149 TripleInputSum - std::accumulate(TripleInputs.begin(), TripleInputs.end(), 0);
8150 TripleDWord = TripleNonInputIdx / 2;
8152 // We use xor with one to compute the adjacent DWord to whichever one the
8154 OneInputDWord = (OneInput / 2) ^ 1;
8156 // Check for one tricky case: We're fixing a 3<-1 or a 1<-3 shuffle for AToA
8157 // and BToA inputs. If there is also such a problem with the BToB and AToB
8158 // inputs, we don't try to fix it necessarily -- we'll recurse and see it in
8159 // the next pass. However, if we have a 2<-2 in the BToB and AToB inputs, it
8160 // is essential that we don't *create* a 3<-1 as then we might oscillate.
8161 if (BToBInputs.size() == 2 && AToBInputs.size() == 2) {
8162 // Compute how many inputs will be flipped by swapping these DWords. We
8164 // to balance this to ensure we don't form a 3-1 shuffle in the other
8166 int NumFlippedAToBInputs =
8167 std::count(AToBInputs.begin(), AToBInputs.end(), 2 * ADWord) +
8168 std::count(AToBInputs.begin(), AToBInputs.end(), 2 * ADWord + 1);
8169 int NumFlippedBToBInputs =
8170 std::count(BToBInputs.begin(), BToBInputs.end(), 2 * BDWord) +
8171 std::count(BToBInputs.begin(), BToBInputs.end(), 2 * BDWord + 1);
8172 if ((NumFlippedAToBInputs == 1 &&
8173 (NumFlippedBToBInputs == 0 || NumFlippedBToBInputs == 2)) ||
8174 (NumFlippedBToBInputs == 1 &&
8175 (NumFlippedAToBInputs == 0 || NumFlippedAToBInputs == 2))) {
8176 // We choose whether to fix the A half or B half based on whether that
8177 // half has zero flipped inputs. At zero, we may not be able to fix it
8178 // with that half. We also bias towards fixing the B half because that
8179 // will more commonly be the high half, and we have to bias one way.
8180 auto FixFlippedInputs = [&V, &DL, &Mask, &DAG](int PinnedIdx, int DWord,
8181 ArrayRef<int> Inputs) {
8182 int FixIdx = PinnedIdx ^ 1; // The adjacent slot to the pinned slot.
8183 bool IsFixIdxInput = std::find(Inputs.begin(), Inputs.end(),
8184 PinnedIdx ^ 1) != Inputs.end();
8185 // Determine whether the free index is in the flipped dword or the
8186 // unflipped dword based on where the pinned index is. We use this bit
8187 // in an xor to conditionally select the adjacent dword.
8188 int FixFreeIdx = 2 * (DWord ^ (PinnedIdx / 2 == DWord));
8189 bool IsFixFreeIdxInput = std::find(Inputs.begin(), Inputs.end(),
8190 FixFreeIdx) != Inputs.end();
8191 if (IsFixIdxInput == IsFixFreeIdxInput)
8193 IsFixFreeIdxInput = std::find(Inputs.begin(), Inputs.end(),
8194 FixFreeIdx) != Inputs.end();
8195 assert(IsFixIdxInput != IsFixFreeIdxInput &&
8196 "We need to be changing the number of flipped inputs!");
8197 int PSHUFHalfMask[] = {0, 1, 2, 3};
8198 std::swap(PSHUFHalfMask[FixFreeIdx % 4], PSHUFHalfMask[FixIdx % 4]);
8199 V = DAG.getNode(FixIdx < 4 ? X86ISD::PSHUFLW : X86ISD::PSHUFHW, DL,
8201 getV4X86ShuffleImm8ForMask(PSHUFHalfMask, DAG));
8204 if (M != -1 && M == FixIdx)
8206 else if (M != -1 && M == FixFreeIdx)
8209 if (NumFlippedBToBInputs != 0) {
8211 BToAInputs.size() == 3 ? TripleNonInputIdx : OneInput;
8212 FixFlippedInputs(BPinnedIdx, BDWord, BToBInputs);
8214 assert(NumFlippedAToBInputs != 0 && "Impossible given predicates!");
8216 AToAInputs.size() == 3 ? TripleNonInputIdx : OneInput;
8217 FixFlippedInputs(APinnedIdx, ADWord, AToBInputs);
8222 int PSHUFDMask[] = {0, 1, 2, 3};
8223 PSHUFDMask[ADWord] = BDWord;
8224 PSHUFDMask[BDWord] = ADWord;
8225 V = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16,
8226 DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32,
8227 DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, V),
8228 getV4X86ShuffleImm8ForMask(PSHUFDMask, DAG)));
8230 // Adjust the mask to match the new locations of A and B.
8232 if (M != -1 && M/2 == ADWord)
8233 M = 2 * BDWord + M % 2;
8234 else if (M != -1 && M/2 == BDWord)
8235 M = 2 * ADWord + M % 2;
8237 // Recurse back into this routine to re-compute state now that this isn't
8238 // a 3 and 1 problem.
8239 return DAG.getVectorShuffle(MVT::v8i16, DL, V, DAG.getUNDEF(MVT::v8i16),
8242 if ((NumLToL == 3 && NumHToL == 1) || (NumLToL == 1 && NumHToL == 3))
8243 return balanceSides(LToLInputs, HToLInputs, HToHInputs, LToHInputs, 0, 4);
8244 else if ((NumHToH == 3 && NumLToH == 1) || (NumHToH == 1 && NumLToH == 3))
8245 return balanceSides(HToHInputs, LToHInputs, LToLInputs, HToLInputs, 4, 0);
8247 // At this point there are at most two inputs to the low and high halves from
8248 // each half. That means the inputs can always be grouped into dwords and
8249 // those dwords can then be moved to the correct half with a dword shuffle.
8250 // We use at most one low and one high word shuffle to collect these paired
8251 // inputs into dwords, and finally a dword shuffle to place them.
8252 int PSHUFLMask[4] = {-1, -1, -1, -1};
8253 int PSHUFHMask[4] = {-1, -1, -1, -1};
8254 int PSHUFDMask[4] = {-1, -1, -1, -1};
8256 // First fix the masks for all the inputs that are staying in their
8257 // original halves. This will then dictate the targets of the cross-half
8259 auto fixInPlaceInputs =
8260 [&PSHUFDMask](ArrayRef<int> InPlaceInputs, ArrayRef<int> IncomingInputs,
8261 MutableArrayRef<int> SourceHalfMask,
8262 MutableArrayRef<int> HalfMask, int HalfOffset) {
8263 if (InPlaceInputs.empty())
8265 if (InPlaceInputs.size() == 1) {
8266 SourceHalfMask[InPlaceInputs[0] - HalfOffset] =
8267 InPlaceInputs[0] - HalfOffset;
8268 PSHUFDMask[InPlaceInputs[0] / 2] = InPlaceInputs[0] / 2;
8271 if (IncomingInputs.empty()) {
8272 // Just fix all of the in place inputs.
8273 for (int Input : InPlaceInputs) {
8274 SourceHalfMask[Input - HalfOffset] = Input - HalfOffset;
8275 PSHUFDMask[Input / 2] = Input / 2;
8280 assert(InPlaceInputs.size() == 2 && "Cannot handle 3 or 4 inputs!");
8281 SourceHalfMask[InPlaceInputs[0] - HalfOffset] =
8282 InPlaceInputs[0] - HalfOffset;
8283 // Put the second input next to the first so that they are packed into
8284 // a dword. We find the adjacent index by toggling the low bit.
8285 int AdjIndex = InPlaceInputs[0] ^ 1;
8286 SourceHalfMask[AdjIndex - HalfOffset] = InPlaceInputs[1] - HalfOffset;
8287 std::replace(HalfMask.begin(), HalfMask.end(), InPlaceInputs[1], AdjIndex);
8288 PSHUFDMask[AdjIndex / 2] = AdjIndex / 2;
8290 fixInPlaceInputs(LToLInputs, HToLInputs, PSHUFLMask, LoMask, 0);
8291 fixInPlaceInputs(HToHInputs, LToHInputs, PSHUFHMask, HiMask, 4);
8293 // Now gather the cross-half inputs and place them into a free dword of
8294 // their target half.
8295 // FIXME: This operation could almost certainly be simplified dramatically to
8296 // look more like the 3-1 fixing operation.
8297 auto moveInputsToRightHalf = [&PSHUFDMask](
8298 MutableArrayRef<int> IncomingInputs, ArrayRef<int> ExistingInputs,
8299 MutableArrayRef<int> SourceHalfMask, MutableArrayRef<int> HalfMask,
8300 MutableArrayRef<int> FinalSourceHalfMask, int SourceOffset,
8302 auto isWordClobbered = [](ArrayRef<int> SourceHalfMask, int Word) {
8303 return SourceHalfMask[Word] != -1 && SourceHalfMask[Word] != Word;
8305 auto isDWordClobbered = [&isWordClobbered](ArrayRef<int> SourceHalfMask,
8307 int LowWord = Word & ~1;
8308 int HighWord = Word | 1;
8309 return isWordClobbered(SourceHalfMask, LowWord) ||
8310 isWordClobbered(SourceHalfMask, HighWord);
8313 if (IncomingInputs.empty())
8316 if (ExistingInputs.empty()) {
8317 // Map any dwords with inputs from them into the right half.
8318 for (int Input : IncomingInputs) {
8319 // If the source half mask maps over the inputs, turn those into
8320 // swaps and use the swapped lane.
8321 if (isWordClobbered(SourceHalfMask, Input - SourceOffset)) {
8322 if (SourceHalfMask[SourceHalfMask[Input - SourceOffset]] == -1) {
8323 SourceHalfMask[SourceHalfMask[Input - SourceOffset]] =
8324 Input - SourceOffset;
8325 // We have to swap the uses in our half mask in one sweep.
8326 for (int &M : HalfMask)
8327 if (M == SourceHalfMask[Input - SourceOffset] + SourceOffset)
8329 else if (M == Input)
8330 M = SourceHalfMask[Input - SourceOffset] + SourceOffset;
8332 assert(SourceHalfMask[SourceHalfMask[Input - SourceOffset]] ==
8333 Input - SourceOffset &&
8334 "Previous placement doesn't match!");
8336 // Note that this correctly re-maps both when we do a swap and when
8337 // we observe the other side of the swap above. We rely on that to
8338 // avoid swapping the members of the input list directly.
8339 Input = SourceHalfMask[Input - SourceOffset] + SourceOffset;
8342 // Map the input's dword into the correct half.
8343 if (PSHUFDMask[(Input - SourceOffset + DestOffset) / 2] == -1)
8344 PSHUFDMask[(Input - SourceOffset + DestOffset) / 2] = Input / 2;
8346 assert(PSHUFDMask[(Input - SourceOffset + DestOffset) / 2] ==
8348 "Previous placement doesn't match!");
8351 // And just directly shift any other-half mask elements to be same-half
8352 // as we will have mirrored the dword containing the element into the
8353 // same position within that half.
8354 for (int &M : HalfMask)
8355 if (M >= SourceOffset && M < SourceOffset + 4) {
8356 M = M - SourceOffset + DestOffset;
8357 assert(M >= 0 && "This should never wrap below zero!");
8362 // Ensure we have the input in a viable dword of its current half. This
8363 // is particularly tricky because the original position may be clobbered
8364 // by inputs being moved and *staying* in that half.
8365 if (IncomingInputs.size() == 1) {
8366 if (isWordClobbered(SourceHalfMask, IncomingInputs[0] - SourceOffset)) {
8367 int InputFixed = std::find(std::begin(SourceHalfMask),
8368 std::end(SourceHalfMask), -1) -
8369 std::begin(SourceHalfMask) + SourceOffset;
8370 SourceHalfMask[InputFixed - SourceOffset] =
8371 IncomingInputs[0] - SourceOffset;
8372 std::replace(HalfMask.begin(), HalfMask.end(), IncomingInputs[0],
8374 IncomingInputs[0] = InputFixed;
8376 } else if (IncomingInputs.size() == 2) {
8377 if (IncomingInputs[0] / 2 != IncomingInputs[1] / 2 ||
8378 isDWordClobbered(SourceHalfMask, IncomingInputs[0] - SourceOffset)) {
8379 // We have two non-adjacent or clobbered inputs we need to extract from
8380 // the source half. To do this, we need to map them into some adjacent
8381 // dword slot in the source mask.
8382 int InputsFixed[2] = {IncomingInputs[0] - SourceOffset,
8383 IncomingInputs[1] - SourceOffset};
8385 // If there is a free slot in the source half mask adjacent to one of
8386 // the inputs, place the other input in it. We use (Index XOR 1) to
8387 // compute an adjacent index.
8388 if (!isWordClobbered(SourceHalfMask, InputsFixed[0]) &&
8389 SourceHalfMask[InputsFixed[0] ^ 1] == -1) {
8390 SourceHalfMask[InputsFixed[0]] = InputsFixed[0];
8391 SourceHalfMask[InputsFixed[0] ^ 1] = InputsFixed[1];
8392 InputsFixed[1] = InputsFixed[0] ^ 1;
8393 } else if (!isWordClobbered(SourceHalfMask, InputsFixed[1]) &&
8394 SourceHalfMask[InputsFixed[1] ^ 1] == -1) {
8395 SourceHalfMask[InputsFixed[1]] = InputsFixed[1];
8396 SourceHalfMask[InputsFixed[1] ^ 1] = InputsFixed[0];
8397 InputsFixed[0] = InputsFixed[1] ^ 1;
8398 } else if (SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1)] == -1 &&
8399 SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1) + 1] == -1) {
8400 // The two inputs are in the same DWord but it is clobbered and the
8401 // adjacent DWord isn't used at all. Move both inputs to the free
8403 SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1)] = InputsFixed[0];
8404 SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1) + 1] = InputsFixed[1];
8405 InputsFixed[0] = 2 * ((InputsFixed[0] / 2) ^ 1);
8406 InputsFixed[1] = 2 * ((InputsFixed[0] / 2) ^ 1) + 1;
8408 // The only way we hit this point is if there is no clobbering
8409 // (because there are no off-half inputs to this half) and there is no
8410 // free slot adjacent to one of the inputs. In this case, we have to
8411 // swap an input with a non-input.
8412 for (int i = 0; i < 4; ++i)
8413 assert((SourceHalfMask[i] == -1 || SourceHalfMask[i] == i) &&
8414 "We can't handle any clobbers here!");
8415 assert(InputsFixed[1] != (InputsFixed[0] ^ 1) &&
8416 "Cannot have adjacent inputs here!");
8418 SourceHalfMask[InputsFixed[0] ^ 1] = InputsFixed[1];
8419 SourceHalfMask[InputsFixed[1]] = InputsFixed[0] ^ 1;
8421 // We also have to update the final source mask in this case because
8422 // it may need to undo the above swap.
8423 for (int &M : FinalSourceHalfMask)
8424 if (M == (InputsFixed[0] ^ 1) + SourceOffset)
8425 M = InputsFixed[1] + SourceOffset;
8426 else if (M == InputsFixed[1] + SourceOffset)
8427 M = (InputsFixed[0] ^ 1) + SourceOffset;
8429 InputsFixed[1] = InputsFixed[0] ^ 1;
8432 // Point everything at the fixed inputs.
8433 for (int &M : HalfMask)
8434 if (M == IncomingInputs[0])
8435 M = InputsFixed[0] + SourceOffset;
8436 else if (M == IncomingInputs[1])
8437 M = InputsFixed[1] + SourceOffset;
8439 IncomingInputs[0] = InputsFixed[0] + SourceOffset;
8440 IncomingInputs[1] = InputsFixed[1] + SourceOffset;
8443 llvm_unreachable("Unhandled input size!");
8446 // Now hoist the DWord down to the right half.
8447 int FreeDWord = (PSHUFDMask[DestOffset / 2] == -1 ? 0 : 1) + DestOffset / 2;
8448 assert(PSHUFDMask[FreeDWord] == -1 && "DWord not free");
8449 PSHUFDMask[FreeDWord] = IncomingInputs[0] / 2;
8450 for (int &M : HalfMask)
8451 for (int Input : IncomingInputs)
8453 M = FreeDWord * 2 + Input % 2;
8455 moveInputsToRightHalf(HToLInputs, LToLInputs, PSHUFHMask, LoMask, HiMask,
8456 /*SourceOffset*/ 4, /*DestOffset*/ 0);
8457 moveInputsToRightHalf(LToHInputs, HToHInputs, PSHUFLMask, HiMask, LoMask,
8458 /*SourceOffset*/ 0, /*DestOffset*/ 4);
8460 // Now enact all the shuffles we've computed to move the inputs into their
8462 if (!isNoopShuffleMask(PSHUFLMask))
8463 V = DAG.getNode(X86ISD::PSHUFLW, DL, MVT::v8i16, V,
8464 getV4X86ShuffleImm8ForMask(PSHUFLMask, DAG));
8465 if (!isNoopShuffleMask(PSHUFHMask))
8466 V = DAG.getNode(X86ISD::PSHUFHW, DL, MVT::v8i16, V,
8467 getV4X86ShuffleImm8ForMask(PSHUFHMask, DAG));
8468 if (!isNoopShuffleMask(PSHUFDMask))
8469 V = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16,
8470 DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32,
8471 DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, V),
8472 getV4X86ShuffleImm8ForMask(PSHUFDMask, DAG)));
8474 // At this point, each half should contain all its inputs, and we can then
8475 // just shuffle them into their final position.
8476 assert(std::count_if(LoMask.begin(), LoMask.end(),
8477 [](int M) { return M >= 4; }) == 0 &&
8478 "Failed to lift all the high half inputs to the low mask!");
8479 assert(std::count_if(HiMask.begin(), HiMask.end(),
8480 [](int M) { return M >= 0 && M < 4; }) == 0 &&
8481 "Failed to lift all the low half inputs to the high mask!");
8483 // Do a half shuffle for the low mask.
8484 if (!isNoopShuffleMask(LoMask))
8485 V = DAG.getNode(X86ISD::PSHUFLW, DL, MVT::v8i16, V,
8486 getV4X86ShuffleImm8ForMask(LoMask, DAG));
8488 // Do a half shuffle with the high mask after shifting its values down.
8489 for (int &M : HiMask)
8492 if (!isNoopShuffleMask(HiMask))
8493 V = DAG.getNode(X86ISD::PSHUFHW, DL, MVT::v8i16, V,
8494 getV4X86ShuffleImm8ForMask(HiMask, DAG));
8499 /// \brief Detect whether the mask pattern should be lowered through
8502 /// This essentially tests whether viewing the mask as an interleaving of two
8503 /// sub-sequences reduces the cross-input traffic of a blend operation. If so,
8504 /// lowering it through interleaving is a significantly better strategy.
8505 static bool shouldLowerAsInterleaving(ArrayRef<int> Mask) {
8506 int NumEvenInputs[2] = {0, 0};
8507 int NumOddInputs[2] = {0, 0};
8508 int NumLoInputs[2] = {0, 0};
8509 int NumHiInputs[2] = {0, 0};
8510 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
8514 int InputIdx = Mask[i] >= Size;
8517 ++NumLoInputs[InputIdx];
8519 ++NumHiInputs[InputIdx];
8522 ++NumEvenInputs[InputIdx];
8524 ++NumOddInputs[InputIdx];
8527 // The minimum number of cross-input results for both the interleaved and
8528 // split cases. If interleaving results in fewer cross-input results, return
8530 int InterleavedCrosses = std::min(NumEvenInputs[1] + NumOddInputs[0],
8531 NumEvenInputs[0] + NumOddInputs[1]);
8532 int SplitCrosses = std::min(NumLoInputs[1] + NumHiInputs[0],
8533 NumLoInputs[0] + NumHiInputs[1]);
8534 return InterleavedCrosses < SplitCrosses;
8537 /// \brief Blend two v8i16 vectors using a naive unpack strategy.
8539 /// This strategy only works when the inputs from each vector fit into a single
8540 /// half of that vector, and generally there are not so many inputs as to leave
8541 /// the in-place shuffles required highly constrained (and thus expensive). It
8542 /// shifts all the inputs into a single side of both input vectors and then
8543 /// uses an unpack to interleave these inputs in a single vector. At that
8544 /// point, we will fall back on the generic single input shuffle lowering.
8545 static SDValue lowerV8I16BasicBlendVectorShuffle(SDLoc DL, SDValue V1,
8547 MutableArrayRef<int> Mask,
8548 const X86Subtarget *Subtarget,
8549 SelectionDAG &DAG) {
8550 assert(V1.getSimpleValueType() == MVT::v8i16 && "Bad input type!");
8551 assert(V2.getSimpleValueType() == MVT::v8i16 && "Bad input type!");
8552 SmallVector<int, 3> LoV1Inputs, HiV1Inputs, LoV2Inputs, HiV2Inputs;
8553 for (int i = 0; i < 8; ++i)
8554 if (Mask[i] >= 0 && Mask[i] < 4)
8555 LoV1Inputs.push_back(i);
8556 else if (Mask[i] >= 4 && Mask[i] < 8)
8557 HiV1Inputs.push_back(i);
8558 else if (Mask[i] >= 8 && Mask[i] < 12)
8559 LoV2Inputs.push_back(i);
8560 else if (Mask[i] >= 12)
8561 HiV2Inputs.push_back(i);
8563 int NumV1Inputs = LoV1Inputs.size() + HiV1Inputs.size();
8564 int NumV2Inputs = LoV2Inputs.size() + HiV2Inputs.size();
8567 assert(NumV1Inputs > 0 && NumV1Inputs <= 3 && "At most 3 inputs supported");
8568 assert(NumV2Inputs > 0 && NumV2Inputs <= 3 && "At most 3 inputs supported");
8569 assert(NumV1Inputs + NumV2Inputs <= 4 && "At most 4 combined inputs");
8571 bool MergeFromLo = LoV1Inputs.size() + LoV2Inputs.size() >=
8572 HiV1Inputs.size() + HiV2Inputs.size();
8574 auto moveInputsToHalf = [&](SDValue V, ArrayRef<int> LoInputs,
8575 ArrayRef<int> HiInputs, bool MoveToLo,
8577 ArrayRef<int> GoodInputs = MoveToLo ? LoInputs : HiInputs;
8578 ArrayRef<int> BadInputs = MoveToLo ? HiInputs : LoInputs;
8579 if (BadInputs.empty())
8582 int MoveMask[] = {-1, -1, -1, -1, -1, -1, -1, -1};
8583 int MoveOffset = MoveToLo ? 0 : 4;
8585 if (GoodInputs.empty()) {
8586 for (int BadInput : BadInputs) {
8587 MoveMask[Mask[BadInput] % 4 + MoveOffset] = Mask[BadInput] - MaskOffset;
8588 Mask[BadInput] = Mask[BadInput] % 4 + MoveOffset + MaskOffset;
8591 if (GoodInputs.size() == 2) {
8592 // If the low inputs are spread across two dwords, pack them into
8594 MoveMask[MoveOffset] = Mask[GoodInputs[0]] - MaskOffset;
8595 MoveMask[MoveOffset + 1] = Mask[GoodInputs[1]] - MaskOffset;
8596 Mask[GoodInputs[0]] = MoveOffset + MaskOffset;
8597 Mask[GoodInputs[1]] = MoveOffset + 1 + MaskOffset;
8599 // Otherwise pin the good inputs.
8600 for (int GoodInput : GoodInputs)
8601 MoveMask[Mask[GoodInput] - MaskOffset] = Mask[GoodInput] - MaskOffset;
8604 if (BadInputs.size() == 2) {
8605 // If we have two bad inputs then there may be either one or two good
8606 // inputs fixed in place. Find a fixed input, and then find the *other*
8607 // two adjacent indices by using modular arithmetic.
8609 std::find_if(std::begin(MoveMask) + MoveOffset, std::end(MoveMask),
8610 [](int M) { return M >= 0; }) -
8611 std::begin(MoveMask);
8613 ((((GoodMaskIdx - MoveOffset) & ~1) + 2) % 4) + MoveOffset;
8614 assert(MoveMask[MoveMaskIdx] == -1 && "Expected empty slot");
8615 assert(MoveMask[MoveMaskIdx + 1] == -1 && "Expected empty slot");
8616 MoveMask[MoveMaskIdx] = Mask[BadInputs[0]] - MaskOffset;
8617 MoveMask[MoveMaskIdx + 1] = Mask[BadInputs[1]] - MaskOffset;
8618 Mask[BadInputs[0]] = MoveMaskIdx + MaskOffset;
8619 Mask[BadInputs[1]] = MoveMaskIdx + 1 + MaskOffset;
8621 assert(BadInputs.size() == 1 && "All sizes handled");
8622 int MoveMaskIdx = std::find(std::begin(MoveMask) + MoveOffset,
8623 std::end(MoveMask), -1) -
8624 std::begin(MoveMask);
8625 MoveMask[MoveMaskIdx] = Mask[BadInputs[0]] - MaskOffset;
8626 Mask[BadInputs[0]] = MoveMaskIdx + MaskOffset;
8630 return DAG.getVectorShuffle(MVT::v8i16, DL, V, DAG.getUNDEF(MVT::v8i16),
8633 V1 = moveInputsToHalf(V1, LoV1Inputs, HiV1Inputs, MergeFromLo,
8635 V2 = moveInputsToHalf(V2, LoV2Inputs, HiV2Inputs, MergeFromLo,
8638 // FIXME: Select an interleaving of the merge of V1 and V2 that minimizes
8639 // cross-half traffic in the final shuffle.
8641 // Munge the mask to be a single-input mask after the unpack merges the
8645 M = 2 * (M % 4) + (M / 8);
8647 return DAG.getVectorShuffle(
8648 MVT::v8i16, DL, DAG.getNode(MergeFromLo ? X86ISD::UNPCKL : X86ISD::UNPCKH,
8649 DL, MVT::v8i16, V1, V2),
8650 DAG.getUNDEF(MVT::v8i16), Mask);
8653 /// \brief Generic lowering of 8-lane i16 shuffles.
8655 /// This handles both single-input shuffles and combined shuffle/blends with
8656 /// two inputs. The single input shuffles are immediately delegated to
8657 /// a dedicated lowering routine.
8659 /// The blends are lowered in one of three fundamental ways. If there are few
8660 /// enough inputs, it delegates to a basic UNPCK-based strategy. If the shuffle
8661 /// of the input is significantly cheaper when lowered as an interleaving of
8662 /// the two inputs, try to interleave them. Otherwise, blend the low and high
8663 /// halves of the inputs separately (making them have relatively few inputs)
8664 /// and then concatenate them.
8665 static SDValue lowerV8I16VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8666 const X86Subtarget *Subtarget,
8667 SelectionDAG &DAG) {
8669 assert(Op.getSimpleValueType() == MVT::v8i16 && "Bad shuffle type!");
8670 assert(V1.getSimpleValueType() == MVT::v8i16 && "Bad operand type!");
8671 assert(V2.getSimpleValueType() == MVT::v8i16 && "Bad operand type!");
8672 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8673 ArrayRef<int> OrigMask = SVOp->getMask();
8674 int MaskStorage[8] = {OrigMask[0], OrigMask[1], OrigMask[2], OrigMask[3],
8675 OrigMask[4], OrigMask[5], OrigMask[6], OrigMask[7]};
8676 MutableArrayRef<int> Mask(MaskStorage);
8678 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
8680 // Whenever we can lower this as a zext, that instruction is strictly faster
8681 // than any alternative.
8682 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(
8683 DL, MVT::v8i16, V1, V2, OrigMask, Subtarget, DAG))
8686 auto isV1 = [](int M) { return M >= 0 && M < 8; };
8687 auto isV2 = [](int M) { return M >= 8; };
8689 int NumV1Inputs = std::count_if(Mask.begin(), Mask.end(), isV1);
8690 int NumV2Inputs = std::count_if(Mask.begin(), Mask.end(), isV2);
8692 if (NumV2Inputs == 0)
8693 return lowerV8I16SingleInputVectorShuffle(DL, V1, Mask, Subtarget, DAG);
8695 assert(NumV1Inputs > 0 && "All single-input shuffles should be canonicalized "
8696 "to be V1-input shuffles.");
8698 // There are special ways we can lower some single-element blends.
8699 if (NumV2Inputs == 1)
8700 if (SDValue V = lowerVectorShuffleAsElementInsertion(MVT::v8i16, DL, V1, V2,
8701 Mask, Subtarget, DAG))
8704 if (Subtarget->hasSSE41())
8706 lowerVectorShuffleAsBlend(DL, MVT::v8i16, V1, V2, Mask, DAG))
8709 // Try to use rotation instructions if available.
8710 if (Subtarget->hasSSSE3())
8711 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(DL, MVT::v8i16, V1, V2, Mask, DAG))
8714 if (NumV1Inputs + NumV2Inputs <= 4)
8715 return lowerV8I16BasicBlendVectorShuffle(DL, V1, V2, Mask, Subtarget, DAG);
8717 // Check whether an interleaving lowering is likely to be more efficient.
8718 // This isn't perfect but it is a strong heuristic that tends to work well on
8719 // the kinds of shuffles that show up in practice.
8721 // FIXME: Handle 1x, 2x, and 4x interleaving.
8722 if (shouldLowerAsInterleaving(Mask)) {
8723 // FIXME: Figure out whether we should pack these into the low or high
8726 int EMask[8], OMask[8];
8727 for (int i = 0; i < 4; ++i) {
8728 EMask[i] = Mask[2*i];
8729 OMask[i] = Mask[2*i + 1];
8734 SDValue Evens = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, EMask);
8735 SDValue Odds = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, OMask);
8737 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8i16, Evens, Odds);
8740 int LoBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
8741 int HiBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
8743 for (int i = 0; i < 4; ++i) {
8744 LoBlendMask[i] = Mask[i];
8745 HiBlendMask[i] = Mask[i + 4];
8748 SDValue LoV = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, LoBlendMask);
8749 SDValue HiV = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, HiBlendMask);
8750 LoV = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, LoV);
8751 HiV = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, HiV);
8753 return DAG.getNode(ISD::BITCAST, DL, MVT::v8i16,
8754 DAG.getNode(X86ISD::UNPCKL, DL, MVT::v2i64, LoV, HiV));
8757 /// \brief Check whether a compaction lowering can be done by dropping even
8758 /// elements and compute how many times even elements must be dropped.
8760 /// This handles shuffles which take every Nth element where N is a power of
8761 /// two. Example shuffle masks:
8763 /// N = 1: 0, 2, 4, 6, 8, 10, 12, 14, 0, 2, 4, 6, 8, 10, 12, 14
8764 /// N = 1: 0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30
8765 /// N = 2: 0, 4, 8, 12, 0, 4, 8, 12, 0, 4, 8, 12, 0, 4, 8, 12
8766 /// N = 2: 0, 4, 8, 12, 16, 20, 24, 28, 0, 4, 8, 12, 16, 20, 24, 28
8767 /// N = 3: 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 0, 8
8768 /// N = 3: 0, 8, 16, 24, 0, 8, 16, 24, 0, 8, 16, 24, 0, 8, 16, 24
8770 /// Any of these lanes can of course be undef.
8772 /// This routine only supports N <= 3.
8773 /// FIXME: Evaluate whether either AVX or AVX-512 have any opportunities here
8776 /// \returns N above, or the number of times even elements must be dropped if
8777 /// there is such a number. Otherwise returns zero.
8778 static int canLowerByDroppingEvenElements(ArrayRef<int> Mask) {
8779 // Figure out whether we're looping over two inputs or just one.
8780 bool IsSingleInput = isSingleInputShuffleMask(Mask);
8782 // The modulus for the shuffle vector entries is based on whether this is
8783 // a single input or not.
8784 int ShuffleModulus = Mask.size() * (IsSingleInput ? 1 : 2);
8785 assert(isPowerOf2_32((uint32_t)ShuffleModulus) &&
8786 "We should only be called with masks with a power-of-2 size!");
8788 uint64_t ModMask = (uint64_t)ShuffleModulus - 1;
8790 // We track whether the input is viable for all power-of-2 strides 2^1, 2^2,
8791 // and 2^3 simultaneously. This is because we may have ambiguity with
8792 // partially undef inputs.
8793 bool ViableForN[3] = {true, true, true};
8795 for (int i = 0, e = Mask.size(); i < e; ++i) {
8796 // Ignore undef lanes, we'll optimistically collapse them to the pattern we
8801 bool IsAnyViable = false;
8802 for (unsigned j = 0; j != array_lengthof(ViableForN); ++j)
8803 if (ViableForN[j]) {
8806 // The shuffle mask must be equal to (i * 2^N) % M.
8807 if ((uint64_t)Mask[i] == (((uint64_t)i << N) & ModMask))
8810 ViableForN[j] = false;
8812 // Early exit if we exhaust the possible powers of two.
8817 for (unsigned j = 0; j != array_lengthof(ViableForN); ++j)
8821 // Return 0 as there is no viable power of two.
8825 /// \brief Generic lowering of v16i8 shuffles.
8827 /// This is a hybrid strategy to lower v16i8 vectors. It first attempts to
8828 /// detect any complexity reducing interleaving. If that doesn't help, it uses
8829 /// UNPCK to spread the i8 elements across two i16-element vectors, and uses
8830 /// the existing lowering for v8i16 blends on each half, finally PACK-ing them
8832 static SDValue lowerV16I8VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8833 const X86Subtarget *Subtarget,
8834 SelectionDAG &DAG) {
8836 assert(Op.getSimpleValueType() == MVT::v16i8 && "Bad shuffle type!");
8837 assert(V1.getSimpleValueType() == MVT::v16i8 && "Bad operand type!");
8838 assert(V2.getSimpleValueType() == MVT::v16i8 && "Bad operand type!");
8839 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8840 ArrayRef<int> OrigMask = SVOp->getMask();
8841 assert(OrigMask.size() == 16 && "Unexpected mask size for v16 shuffle!");
8843 // Try to use rotation instructions if available.
8844 if (Subtarget->hasSSSE3())
8845 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(DL, MVT::v16i8, V1, V2,
8849 // Try to use a zext lowering.
8850 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(
8851 DL, MVT::v16i8, V1, V2, OrigMask, Subtarget, DAG))
8854 int MaskStorage[16] = {
8855 OrigMask[0], OrigMask[1], OrigMask[2], OrigMask[3],
8856 OrigMask[4], OrigMask[5], OrigMask[6], OrigMask[7],
8857 OrigMask[8], OrigMask[9], OrigMask[10], OrigMask[11],
8858 OrigMask[12], OrigMask[13], OrigMask[14], OrigMask[15]};
8859 MutableArrayRef<int> Mask(MaskStorage);
8860 MutableArrayRef<int> LoMask = Mask.slice(0, 8);
8861 MutableArrayRef<int> HiMask = Mask.slice(8, 8);
8864 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 16; });
8866 // For single-input shuffles, there are some nicer lowering tricks we can use.
8867 if (NumV2Elements == 0) {
8868 // Check whether we can widen this to an i16 shuffle by duplicating bytes.
8869 // Notably, this handles splat and partial-splat shuffles more efficiently.
8870 // However, it only makes sense if the pre-duplication shuffle simplifies
8871 // things significantly. Currently, this means we need to be able to
8872 // express the pre-duplication shuffle as an i16 shuffle.
8874 // FIXME: We should check for other patterns which can be widened into an
8875 // i16 shuffle as well.
8876 auto canWidenViaDuplication = [](ArrayRef<int> Mask) {
8877 for (int i = 0; i < 16; i += 2)
8878 if (Mask[i] != -1 && Mask[i + 1] != -1 && Mask[i] != Mask[i + 1])
8883 auto tryToWidenViaDuplication = [&]() -> SDValue {
8884 if (!canWidenViaDuplication(Mask))
8886 SmallVector<int, 4> LoInputs;
8887 std::copy_if(Mask.begin(), Mask.end(), std::back_inserter(LoInputs),
8888 [](int M) { return M >= 0 && M < 8; });
8889 std::sort(LoInputs.begin(), LoInputs.end());
8890 LoInputs.erase(std::unique(LoInputs.begin(), LoInputs.end()),
8892 SmallVector<int, 4> HiInputs;
8893 std::copy_if(Mask.begin(), Mask.end(), std::back_inserter(HiInputs),
8894 [](int M) { return M >= 8; });
8895 std::sort(HiInputs.begin(), HiInputs.end());
8896 HiInputs.erase(std::unique(HiInputs.begin(), HiInputs.end()),
8899 bool TargetLo = LoInputs.size() >= HiInputs.size();
8900 ArrayRef<int> InPlaceInputs = TargetLo ? LoInputs : HiInputs;
8901 ArrayRef<int> MovingInputs = TargetLo ? HiInputs : LoInputs;
8903 int PreDupI16Shuffle[] = {-1, -1, -1, -1, -1, -1, -1, -1};
8904 SmallDenseMap<int, int, 8> LaneMap;
8905 for (int I : InPlaceInputs) {
8906 PreDupI16Shuffle[I/2] = I/2;
8909 int j = TargetLo ? 0 : 4, je = j + 4;
8910 for (int i = 0, ie = MovingInputs.size(); i < ie; ++i) {
8911 // Check if j is already a shuffle of this input. This happens when
8912 // there are two adjacent bytes after we move the low one.
8913 if (PreDupI16Shuffle[j] != MovingInputs[i] / 2) {
8914 // If we haven't yet mapped the input, search for a slot into which
8916 while (j < je && PreDupI16Shuffle[j] != -1)
8920 // We can't place the inputs into a single half with a simple i16 shuffle, so bail.
8923 // Map this input with the i16 shuffle.
8924 PreDupI16Shuffle[j] = MovingInputs[i] / 2;
8927 // Update the lane map based on the mapping we ended up with.
8928 LaneMap[MovingInputs[i]] = 2 * j + MovingInputs[i] % 2;
8931 ISD::BITCAST, DL, MVT::v16i8,
8932 DAG.getVectorShuffle(MVT::v8i16, DL,
8933 DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V1),
8934 DAG.getUNDEF(MVT::v8i16), PreDupI16Shuffle));
8936 // Unpack the bytes to form the i16s that will be shuffled into place.
8937 V1 = DAG.getNode(TargetLo ? X86ISD::UNPCKL : X86ISD::UNPCKH, DL,
8938 MVT::v16i8, V1, V1);
8940 int PostDupI16Shuffle[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
8941 for (int i = 0; i < 16; i += 2) {
8943 PostDupI16Shuffle[i / 2] = LaneMap[Mask[i]] - (TargetLo ? 0 : 8);
8944 assert(PostDupI16Shuffle[i / 2] < 8 && "Invalid v8 shuffle mask!");
8947 ISD::BITCAST, DL, MVT::v16i8,
8948 DAG.getVectorShuffle(MVT::v8i16, DL,
8949 DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V1),
8950 DAG.getUNDEF(MVT::v8i16), PostDupI16Shuffle));
8952 if (SDValue V = tryToWidenViaDuplication())
8956 // Check whether an interleaving lowering is likely to be more efficient.
8957 // This isn't perfect but it is a strong heuristic that tends to work well on
8958 // the kinds of shuffles that show up in practice.
8960 // FIXME: We need to handle other interleaving widths (i16, i32, ...).
8961 if (shouldLowerAsInterleaving(Mask)) {
8962 // FIXME: Figure out whether we should pack these into the low or high
8965 int EMask[16], OMask[16];
8966 for (int i = 0; i < 8; ++i) {
8967 EMask[i] = Mask[2*i];
8968 OMask[i] = Mask[2*i + 1];
8973 SDValue Evens = DAG.getVectorShuffle(MVT::v16i8, DL, V1, V2, EMask);
8974 SDValue Odds = DAG.getVectorShuffle(MVT::v16i8, DL, V1, V2, OMask);
8976 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v16i8, Evens, Odds);
8979 // Check for SSSE3 which lets us lower all v16i8 shuffles much more directly
8980 // with PSHUFB. It is important to do this before we attempt to generate any
8981 // blends but after all of the single-input lowerings. If the single input
8982 // lowerings can find an instruction sequence that is faster than a PSHUFB, we
8983 // want to preserve that and we can DAG combine any longer sequences into
8984 // a PSHUFB in the end. But once we start blending from multiple inputs,
8985 // the complexity of DAG combining bad patterns back into PSHUFB is too high,
8986 // and there are *very* few patterns that would actually be faster than the
8987 // PSHUFB approach because of its ability to zero lanes.
8989 // FIXME: The only exceptions to the above are blends which are exact
8990 // interleavings with direct instructions supporting them. We currently don't
8991 // handle those well here.
8992 if (Subtarget->hasSSSE3()) {
8995 for (int i = 0; i < 16; ++i)
8996 if (Mask[i] == -1) {
8997 V1Mask[i] = V2Mask[i] = DAG.getConstant(0x80, MVT::i8);
8999 V1Mask[i] = DAG.getConstant(Mask[i] < 16 ? Mask[i] : 0x80, MVT::i8);
9001 DAG.getConstant(Mask[i] < 16 ? 0x80 : Mask[i] - 16, MVT::i8);
9003 V1 = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8, V1,
9004 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v16i8, V1Mask));
9005 if (isSingleInputShuffleMask(Mask))
9006 return V1; // Single inputs are easy.
9008 // Otherwise, blend the two.
9009 V2 = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8, V2,
9010 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v16i8, V2Mask));
9011 return DAG.getNode(ISD::OR, DL, MVT::v16i8, V1, V2);
9014 // There are special ways we can lower some single-element blends.
9015 if (NumV2Elements == 1)
9016 if (SDValue V = lowerVectorShuffleAsElementInsertion(MVT::v16i8, DL, V1, V2,
9017 Mask, Subtarget, DAG))
9020 // Check whether a compaction lowering can be done. This handles shuffles
9021 // which take every Nth element for some even N. See the helper function for
9024 // We special case these as they can be particularly efficiently handled with
9025 // the PACKUSB instruction on x86 and they show up in common patterns of
9026 // rearranging bytes to truncate wide elements.
9027 if (int NumEvenDrops = canLowerByDroppingEvenElements(Mask)) {
9028 // NumEvenDrops is the power of two stride of the elements. Another way of
9029 // thinking about it is that we need to drop the even elements this many
9030 // times to get the original input.
9031 bool IsSingleInput = isSingleInputShuffleMask(Mask);
9033 // First we need to zero all the dropped bytes.
9034 assert(NumEvenDrops <= 3 &&
9035 "No support for dropping even elements more than 3 times.");
9036 // We use the mask type to pick which bytes are preserved based on how many
9037 // elements are dropped.
9038 MVT MaskVTs[] = { MVT::v8i16, MVT::v4i32, MVT::v2i64 };
9039 SDValue ByteClearMask =
9040 DAG.getNode(ISD::BITCAST, DL, MVT::v16i8,
9041 DAG.getConstant(0xFF, MaskVTs[NumEvenDrops - 1]));
9042 V1 = DAG.getNode(ISD::AND, DL, MVT::v16i8, V1, ByteClearMask);
9044 V2 = DAG.getNode(ISD::AND, DL, MVT::v16i8, V2, ByteClearMask);
9046 // Now pack things back together.
9047 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V1);
9048 V2 = IsSingleInput ? V1 : DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V2);
9049 SDValue Result = DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8, V1, V2);
9050 for (int i = 1; i < NumEvenDrops; ++i) {
9051 Result = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, Result);
9052 Result = DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8, Result, Result);
9058 int V1LoBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9059 int V1HiBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9060 int V2LoBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9061 int V2HiBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9063 auto buildBlendMasks = [](MutableArrayRef<int> HalfMask,
9064 MutableArrayRef<int> V1HalfBlendMask,
9065 MutableArrayRef<int> V2HalfBlendMask) {
9066 for (int i = 0; i < 8; ++i)
9067 if (HalfMask[i] >= 0 && HalfMask[i] < 16) {
9068 V1HalfBlendMask[i] = HalfMask[i];
9070 } else if (HalfMask[i] >= 16) {
9071 V2HalfBlendMask[i] = HalfMask[i] - 16;
9072 HalfMask[i] = i + 8;
9075 buildBlendMasks(LoMask, V1LoBlendMask, V2LoBlendMask);
9076 buildBlendMasks(HiMask, V1HiBlendMask, V2HiBlendMask);
9078 SDValue Zero = getZeroVector(MVT::v8i16, Subtarget, DAG, DL);
9080 auto buildLoAndHiV8s = [&](SDValue V, MutableArrayRef<int> LoBlendMask,
9081 MutableArrayRef<int> HiBlendMask) {
9083 // Check if any of the odd lanes in the v16i8 are used. If not, we can mask
9084 // them out and avoid using UNPCK{L,H} to extract the elements of V as
9086 if (std::none_of(LoBlendMask.begin(), LoBlendMask.end(),
9087 [](int M) { return M >= 0 && M % 2 == 1; }) &&
9088 std::none_of(HiBlendMask.begin(), HiBlendMask.end(),
9089 [](int M) { return M >= 0 && M % 2 == 1; })) {
9090 // Use a mask to drop the high bytes.
9091 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V);
9092 V1 = DAG.getNode(ISD::AND, DL, MVT::v8i16, V1,
9093 DAG.getConstant(0x00FF, MVT::v8i16));
9095 // This will be a single vector shuffle instead of a blend so nuke V2.
9096 V2 = DAG.getUNDEF(MVT::v8i16);
9098 // Squash the masks to point directly into V1.
9099 for (int &M : LoBlendMask)
9102 for (int &M : HiBlendMask)
9106 // Otherwise just unpack the low half of V into V1 and the high half into
9107 // V2 so that we can blend them as i16s.
9108 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16,
9109 DAG.getNode(X86ISD::UNPCKL, DL, MVT::v16i8, V, Zero));
9110 V2 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16,
9111 DAG.getNode(X86ISD::UNPCKH, DL, MVT::v16i8, V, Zero));
9114 SDValue BlendedLo = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, LoBlendMask);
9115 SDValue BlendedHi = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, HiBlendMask);
9116 return std::make_pair(BlendedLo, BlendedHi);
9118 SDValue V1Lo, V1Hi, V2Lo, V2Hi;
9119 std::tie(V1Lo, V1Hi) = buildLoAndHiV8s(V1, V1LoBlendMask, V1HiBlendMask);
9120 std::tie(V2Lo, V2Hi) = buildLoAndHiV8s(V2, V2LoBlendMask, V2HiBlendMask);
9122 SDValue LoV = DAG.getVectorShuffle(MVT::v8i16, DL, V1Lo, V2Lo, LoMask);
9123 SDValue HiV = DAG.getVectorShuffle(MVT::v8i16, DL, V1Hi, V2Hi, HiMask);
9125 return DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8, LoV, HiV);
9128 /// \brief Dispatching routine to lower various 128-bit x86 vector shuffles.
9130 /// This routine breaks down the specific type of 128-bit shuffle and
9131 /// dispatches to the lowering routines accordingly.
9132 static SDValue lower128BitVectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9133 MVT VT, const X86Subtarget *Subtarget,
9134 SelectionDAG &DAG) {
9135 switch (VT.SimpleTy) {
9137 return lowerV2I64VectorShuffle(Op, V1, V2, Subtarget, DAG);
9139 return lowerV2F64VectorShuffle(Op, V1, V2, Subtarget, DAG);
9141 return lowerV4I32VectorShuffle(Op, V1, V2, Subtarget, DAG);
9143 return lowerV4F32VectorShuffle(Op, V1, V2, Subtarget, DAG);
9145 return lowerV8I16VectorShuffle(Op, V1, V2, Subtarget, DAG);
9147 return lowerV16I8VectorShuffle(Op, V1, V2, Subtarget, DAG);
9150 llvm_unreachable("Unimplemented!");
9154 /// \brief Test whether there are elements crossing 128-bit lanes in this
9157 /// X86 divides up its shuffles into in-lane and cross-lane shuffle operations
9158 /// and we routinely test for these.
9159 static bool is128BitLaneCrossingShuffleMask(MVT VT, ArrayRef<int> Mask) {
9160 int LaneSize = 128 / VT.getScalarSizeInBits();
9161 int Size = Mask.size();
9162 for (int i = 0; i < Size; ++i)
9163 if (Mask[i] >= 0 && (Mask[i] % Size) / LaneSize != i / LaneSize)
9168 /// \brief Test whether a shuffle mask is equivalent within each 128-bit lane.
9170 /// This checks a shuffle mask to see if it is performing the same
9171 /// 128-bit lane-relative shuffle in each 128-bit lane. This trivially implies
9172 /// that it is also not lane-crossing.
9173 static bool is128BitLaneRepeatedShuffleMask(MVT VT, ArrayRef<int> Mask) {
9174 int LaneSize = 128 / VT.getScalarSizeInBits();
9175 int Size = Mask.size();
9176 for (int i = LaneSize; i < Size; ++i)
9177 if (Mask[i] >= 0 && Mask[i] != (Mask[i % LaneSize] + (i / LaneSize) * LaneSize))
9182 /// \brief Generic routine to split a 256-bit vector shuffle into 128-bit
9185 /// There is a severely limited set of shuffles available in AVX1 for 256-bit
9186 /// vectors resulting in routinely needing to split the shuffle into two 128-bit
9187 /// shuffles. This can be done generically for any 256-bit vector shuffle and so
9188 /// we encode the logic here for specific shuffle lowering routines to bail to
9189 /// when they exhaust the features avaible to more directly handle the shuffle.
9190 static SDValue splitAndLower256BitVectorShuffle(SDValue Op, SDValue V1,
9192 const X86Subtarget *Subtarget,
9193 SelectionDAG &DAG) {
9195 MVT VT = Op.getSimpleValueType();
9196 assert(VT.getSizeInBits() == 256 && "Only for 256-bit vector shuffles!");
9197 assert(V1.getSimpleValueType() == VT && "Bad operand type!");
9198 assert(V2.getSimpleValueType() == VT && "Bad operand type!");
9199 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9200 ArrayRef<int> Mask = SVOp->getMask();
9202 ArrayRef<int> LoMask = Mask.slice(0, Mask.size()/2);
9203 ArrayRef<int> HiMask = Mask.slice(Mask.size()/2);
9205 int NumElements = VT.getVectorNumElements();
9206 int SplitNumElements = NumElements / 2;
9207 MVT ScalarVT = VT.getScalarType();
9208 MVT SplitVT = MVT::getVectorVT(ScalarVT, NumElements / 2);
9210 SDValue LoV1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SplitVT, V1,
9211 DAG.getIntPtrConstant(0));
9212 SDValue HiV1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SplitVT, V1,
9213 DAG.getIntPtrConstant(SplitNumElements));
9214 SDValue LoV2 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SplitVT, V2,
9215 DAG.getIntPtrConstant(0));
9216 SDValue HiV2 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SplitVT, V2,
9217 DAG.getIntPtrConstant(SplitNumElements));
9219 // Now create two 4-way blends of these half-width vectors.
9220 auto HalfBlend = [&](ArrayRef<int> HalfMask) {
9221 SmallVector<int, 16> V1BlendMask, V2BlendMask, BlendMask;
9222 for (int i = 0; i < SplitNumElements; ++i) {
9223 int M = HalfMask[i];
9224 if (M >= NumElements) {
9225 V2BlendMask.push_back(M - NumElements);
9226 V1BlendMask.push_back(-1);
9227 BlendMask.push_back(SplitNumElements + i);
9228 } else if (M >= 0) {
9229 V2BlendMask.push_back(-1);
9230 V1BlendMask.push_back(M);
9231 BlendMask.push_back(i);
9233 V2BlendMask.push_back(-1);
9234 V1BlendMask.push_back(-1);
9235 BlendMask.push_back(-1);
9238 SDValue V1Blend = DAG.getVectorShuffle(SplitVT, DL, LoV1, HiV1, V1BlendMask);
9239 SDValue V2Blend = DAG.getVectorShuffle(SplitVT, DL, LoV2, HiV2, V2BlendMask);
9240 return DAG.getVectorShuffle(SplitVT, DL, V1Blend, V2Blend, BlendMask);
9242 SDValue Lo = HalfBlend(LoMask);
9243 SDValue Hi = HalfBlend(HiMask);
9244 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, Lo, Hi);
9247 /// \brief Handle lowering of 4-lane 64-bit floating point shuffles.
9249 /// Also ends up handling lowering of 4-lane 64-bit integer shuffles when AVX2
9250 /// isn't available.
9251 static SDValue lowerV4F64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9252 const X86Subtarget *Subtarget,
9253 SelectionDAG &DAG) {
9255 assert(V1.getSimpleValueType() == MVT::v4f64 && "Bad operand type!");
9256 assert(V2.getSimpleValueType() == MVT::v4f64 && "Bad operand type!");
9257 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9258 ArrayRef<int> Mask = SVOp->getMask();
9259 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
9261 if (is128BitLaneCrossingShuffleMask(MVT::v4f64, Mask))
9262 return splitAndLower256BitVectorShuffle(Op, V1, V2, Subtarget, DAG);
9264 if (isSingleInputShuffleMask(Mask)) {
9265 // Non-half-crossing single input shuffles can be lowerid with an
9266 // interleaved permutation.
9267 unsigned VPERMILPMask = (Mask[0] == 1) | ((Mask[1] == 1) << 1) |
9268 ((Mask[2] == 3) << 2) | ((Mask[3] == 3) << 3);
9269 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v4f64, V1,
9270 DAG.getConstant(VPERMILPMask, MVT::i8));
9273 // X86 has dedicated unpack instructions that can handle specific blend
9274 // operations: UNPCKH and UNPCKL.
9275 if (isShuffleEquivalent(Mask, 0, 4, 2, 6))
9276 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4f64, V1, V2);
9277 if (isShuffleEquivalent(Mask, 1, 5, 3, 7))
9278 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4f64, V1, V2);
9280 // If we have a single input to the zero element, insert that into V1 if we
9281 // can do so cheaply.
9283 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; });
9284 if (NumV2Elements == 1 && Mask[0] >= 4)
9285 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
9286 MVT::v4f64, DL, V1, V2, Mask, Subtarget, DAG))
9290 lowerVectorShuffleAsBlend(DL, MVT::v4f64, V1, V2, Mask, DAG))
9293 // Check if the blend happens to exactly fit that of SHUFPD.
9294 if (Mask[0] < 4 && (Mask[1] == -1 || Mask[1] >= 4) &&
9295 Mask[2] < 4 && (Mask[3] == -1 || Mask[3] >= 4)) {
9296 unsigned SHUFPDMask = (Mask[0] == 1) | ((Mask[1] == 5) << 1) |
9297 ((Mask[2] == 3) << 2) | ((Mask[3] == 7) << 3);
9298 return DAG.getNode(X86ISD::SHUFP, DL, MVT::v4f64, V1, V2,
9299 DAG.getConstant(SHUFPDMask, MVT::i8));
9301 if ((Mask[0] == -1 || Mask[0] >= 4) && Mask[1] < 4 &&
9302 (Mask[2] == -1 || Mask[2] >= 4) && Mask[3] < 4) {
9303 unsigned SHUFPDMask = (Mask[0] == 5) | ((Mask[1] == 1) << 1) |
9304 ((Mask[2] == 7) << 2) | ((Mask[3] == 3) << 3);
9305 return DAG.getNode(X86ISD::SHUFP, DL, MVT::v4f64, V2, V1,
9306 DAG.getConstant(SHUFPDMask, MVT::i8));
9309 // Shuffle the input elements into the desired positions in V1 and V2 and
9310 // blend them together.
9311 int V1Mask[] = {-1, -1, -1, -1};
9312 int V2Mask[] = {-1, -1, -1, -1};
9313 for (int i = 0; i < 4; ++i)
9314 if (Mask[i] >= 0 && Mask[i] < 4)
9315 V1Mask[i] = Mask[i];
9316 else if (Mask[i] >= 4)
9317 V2Mask[i] = Mask[i] - 4;
9319 V1 = DAG.getVectorShuffle(MVT::v4f64, DL, V1, DAG.getUNDEF(MVT::v4f64), V1Mask);
9320 V2 = DAG.getVectorShuffle(MVT::v4f64, DL, V2, DAG.getUNDEF(MVT::v4f64), V2Mask);
9322 unsigned BlendMask = 0;
9323 for (int i = 0; i < 4; ++i)
9325 BlendMask |= 1 << i;
9327 return DAG.getNode(X86ISD::BLENDI, DL, MVT::v4f64, V1, V2,
9328 DAG.getConstant(BlendMask, MVT::i8));
9331 /// \brief Handle lowering of 4-lane 64-bit integer shuffles.
9333 /// This routine is only called when we have AVX2 and thus a reasonable
9334 /// instruction set for v4i64 shuffling..
9335 static SDValue lowerV4I64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9336 const X86Subtarget *Subtarget,
9337 SelectionDAG &DAG) {
9339 assert(V1.getSimpleValueType() == MVT::v4i64 && "Bad operand type!");
9340 assert(V2.getSimpleValueType() == MVT::v4i64 && "Bad operand type!");
9341 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9342 ArrayRef<int> Mask = SVOp->getMask();
9343 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
9344 assert(Subtarget->hasAVX2() && "We can only lower v4i64 with AVX2!");
9346 // FIXME: Actually implement this using AVX2!!!
9347 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v4f64, V1);
9348 V2 = DAG.getNode(ISD::BITCAST, DL, MVT::v4f64, V2);
9349 return DAG.getNode(ISD::BITCAST, DL, MVT::v4i64,
9350 DAG.getVectorShuffle(MVT::v4f64, DL, V1, V2, Mask));
9353 /// \brief Handle lowering of 8-lane 32-bit floating point shuffles.
9355 /// Also ends up handling lowering of 8-lane 32-bit integer shuffles when AVX2
9356 /// isn't available.
9357 static SDValue lowerV8F32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9358 const X86Subtarget *Subtarget,
9359 SelectionDAG &DAG) {
9361 assert(V1.getSimpleValueType() == MVT::v8f32 && "Bad operand type!");
9362 assert(V2.getSimpleValueType() == MVT::v8f32 && "Bad operand type!");
9363 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9364 ArrayRef<int> Mask = SVOp->getMask();
9365 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
9367 if (is128BitLaneCrossingShuffleMask(MVT::v8f32, Mask))
9368 return splitAndLower256BitVectorShuffle(Op, V1, V2, Subtarget, DAG);
9371 lowerVectorShuffleAsBlend(DL, MVT::v8f32, V1, V2, Mask, DAG))
9374 // If the shuffle mask is repeated in each 128-bit lane, we have many more
9375 // options to efficiently lower the shuffle.
9376 if (is128BitLaneRepeatedShuffleMask(MVT::v8f32, Mask)) {
9377 ArrayRef<int> LoMask = Mask.slice(0, 4);
9378 if (isSingleInputShuffleMask(Mask))
9379 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v8f32, V1,
9380 getV4X86ShuffleImm8ForMask(LoMask, DAG));
9382 // Use dedicated unpack instructions for masks that match their pattern.
9383 if (isShuffleEquivalent(LoMask, 0, 8, 1, 9))
9384 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8f32, V1, V2);
9385 if (isShuffleEquivalent(LoMask, 2, 10, 3, 11))
9386 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8f32, V1, V2);
9388 // Otherwise, fall back to a SHUFPS sequence. Here it is important that we
9389 // have already handled any direct blends.
9390 int SHUFPSMask[] = {Mask[0], Mask[1], Mask[2], Mask[3]};
9391 for (int &M : SHUFPSMask)
9394 return lowerVectorShuffleWithSHUPFS(DL, MVT::v8f32, SHUFPSMask, V1, V2, DAG);
9397 // If we have a single input shuffle with different shuffle patterns in the
9398 // two 128-bit lanes use the variable mask to VPERMILPS.
9399 if (isSingleInputShuffleMask(Mask)) {
9400 SDValue VPermMask[8];
9401 for (int i = 0; i < 8; ++i)
9402 VPermMask[i] = Mask[i] < 0 ? DAG.getUNDEF(MVT::i32)
9403 : DAG.getConstant(Mask[i], MVT::i32);
9405 X86ISD::VPERMILPV, DL, MVT::v8f32, V1,
9406 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v8i32, VPermMask));
9409 // Shuffle the input elements into the desired positions in V1 and V2 and
9410 // blend them together.
9411 int V1Mask[] = {-1, -1, -1, -1, -1, -1, -1, -1};
9412 int V2Mask[] = {-1, -1, -1, -1, -1, -1, -1, -1};
9413 unsigned BlendMask = 0;
9414 for (int i = 0; i < 8; ++i)
9415 if (Mask[i] >= 0 && Mask[i] < 8) {
9416 V1Mask[i] = Mask[i];
9417 } else if (Mask[i] >= 8) {
9418 V2Mask[i] = Mask[i] - 8;
9419 BlendMask |= 1 << i;
9422 V1 = DAG.getVectorShuffle(MVT::v8f32, DL, V1, DAG.getUNDEF(MVT::v8f32), V1Mask);
9423 V2 = DAG.getVectorShuffle(MVT::v8f32, DL, V2, DAG.getUNDEF(MVT::v8f32), V2Mask);
9425 return DAG.getNode(X86ISD::BLENDI, DL, MVT::v8f32, V1, V2,
9426 DAG.getConstant(BlendMask, MVT::i8));
9429 /// \brief Handle lowering of 8-lane 32-bit integer shuffles.
9431 /// This routine is only called when we have AVX2 and thus a reasonable
9432 /// instruction set for v8i32 shuffling..
9433 static SDValue lowerV8I32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9434 const X86Subtarget *Subtarget,
9435 SelectionDAG &DAG) {
9437 assert(V1.getSimpleValueType() == MVT::v8i32 && "Bad operand type!");
9438 assert(V2.getSimpleValueType() == MVT::v8i32 && "Bad operand type!");
9439 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9440 ArrayRef<int> Mask = SVOp->getMask();
9441 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
9442 assert(Subtarget->hasAVX2() && "We can only lower v8i32 with AVX2!");
9444 // FIXME: Actually implement this using AVX2!!!
9445 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v8f32, V1);
9446 V2 = DAG.getNode(ISD::BITCAST, DL, MVT::v8f32, V2);
9447 return DAG.getNode(ISD::BITCAST, DL, MVT::v8i32,
9448 DAG.getVectorShuffle(MVT::v8f32, DL, V1, V2, Mask));
9451 /// \brief Handle lowering of 16-lane 16-bit integer shuffles.
9453 /// This routine is only called when we have AVX2 and thus a reasonable
9454 /// instruction set for v16i16 shuffling..
9455 static SDValue lowerV16I16VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9456 const X86Subtarget *Subtarget,
9457 SelectionDAG &DAG) {
9459 assert(V1.getSimpleValueType() == MVT::v16i16 && "Bad operand type!");
9460 assert(V2.getSimpleValueType() == MVT::v16i16 && "Bad operand type!");
9461 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9462 ArrayRef<int> Mask = SVOp->getMask();
9463 assert(Mask.size() == 16 && "Unexpected mask size for v16 shuffle!");
9464 assert(Subtarget->hasAVX2() && "We can only lower v16i16 with AVX2!");
9466 // FIXME: Actually implement this using AVX2!!!
9468 return splitAndLower256BitVectorShuffle(Op, V1, V2, Subtarget, DAG);
9471 /// \brief Handle lowering of 32-lane 8-bit integer shuffles.
9473 /// This routine is only called when we have AVX2 and thus a reasonable
9474 /// instruction set for v32i8 shuffling..
9475 static SDValue lowerV32I8VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9476 const X86Subtarget *Subtarget,
9477 SelectionDAG &DAG) {
9479 assert(V1.getSimpleValueType() == MVT::v32i8 && "Bad operand type!");
9480 assert(V2.getSimpleValueType() == MVT::v32i8 && "Bad operand type!");
9481 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9482 ArrayRef<int> Mask = SVOp->getMask();
9483 assert(Mask.size() == 32 && "Unexpected mask size for v32 shuffle!");
9484 assert(Subtarget->hasAVX2() && "We can only lower v32i8 with AVX2!");
9486 // FIXME: Actually implement this using AVX2!!!
9488 return splitAndLower256BitVectorShuffle(Op, V1, V2, Subtarget, DAG);
9491 /// \brief High-level routine to lower various 256-bit x86 vector shuffles.
9493 /// This routine either breaks down the specific type of a 256-bit x86 vector
9494 /// shuffle or splits it into two 128-bit shuffles and fuses the results back
9495 /// together based on the available instructions.
9496 static SDValue lower256BitVectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9497 MVT VT, const X86Subtarget *Subtarget,
9498 SelectionDAG &DAG) {
9500 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9501 ArrayRef<int> Mask = SVOp->getMask();
9503 // There is a really nice hard cut-over between AVX1 and AVX2 that means we can
9504 // check for those subtargets here and avoid much of the subtarget querying in
9505 // the per-vector-type lowering routines. With AVX1 we have essentially *zero*
9506 // ability to manipulate a 256-bit vector with integer types. Since we'll use
9507 // floating point types there eventually, just immediately cast everything to
9508 // a float and operate entirely in that domain.
9509 if (VT.isInteger() && !Subtarget->hasAVX2()) {
9510 int ElementBits = VT.getScalarSizeInBits();
9511 if (ElementBits < 32)
9512 // No floating point type available, decompose into 128-bit vectors.
9513 return splitAndLower256BitVectorShuffle(Op, V1, V2, Subtarget, DAG);
9515 MVT FpVT = MVT::getVectorVT(MVT::getFloatingPointVT(ElementBits),
9516 VT.getVectorNumElements());
9517 V1 = DAG.getNode(ISD::BITCAST, DL, FpVT, V1);
9518 V2 = DAG.getNode(ISD::BITCAST, DL, FpVT, V2);
9519 return DAG.getNode(ISD::BITCAST, DL, VT,
9520 DAG.getVectorShuffle(FpVT, DL, V1, V2, Mask));
9523 switch (VT.SimpleTy) {
9525 return lowerV4F64VectorShuffle(Op, V1, V2, Subtarget, DAG);
9527 return lowerV4I64VectorShuffle(Op, V1, V2, Subtarget, DAG);
9529 return lowerV8F32VectorShuffle(Op, V1, V2, Subtarget, DAG);
9531 return lowerV8I32VectorShuffle(Op, V1, V2, Subtarget, DAG);
9533 return lowerV16I16VectorShuffle(Op, V1, V2, Subtarget, DAG);
9535 return lowerV32I8VectorShuffle(Op, V1, V2, Subtarget, DAG);
9538 llvm_unreachable("Not a valid 256-bit x86 vector type!");
9542 /// \brief Tiny helper function to test whether a shuffle mask could be
9543 /// simplified by widening the elements being shuffled.
9544 static bool canWidenShuffleElements(ArrayRef<int> Mask) {
9545 for (int i = 0, Size = Mask.size(); i < Size; i += 2)
9546 if ((Mask[i] != -1 && Mask[i] % 2 != 0) ||
9547 (Mask[i + 1] != -1 && (Mask[i + 1] % 2 != 1 ||
9548 (Mask[i] != -1 && Mask[i] + 1 != Mask[i + 1]))))
9554 /// \brief Top-level lowering for x86 vector shuffles.
9556 /// This handles decomposition, canonicalization, and lowering of all x86
9557 /// vector shuffles. Most of the specific lowering strategies are encapsulated
9558 /// above in helper routines. The canonicalization attempts to widen shuffles
9559 /// to involve fewer lanes of wider elements, consolidate symmetric patterns
9560 /// s.t. only one of the two inputs needs to be tested, etc.
9561 static SDValue lowerVectorShuffle(SDValue Op, const X86Subtarget *Subtarget,
9562 SelectionDAG &DAG) {
9563 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9564 ArrayRef<int> Mask = SVOp->getMask();
9565 SDValue V1 = Op.getOperand(0);
9566 SDValue V2 = Op.getOperand(1);
9567 MVT VT = Op.getSimpleValueType();
9568 int NumElements = VT.getVectorNumElements();
9571 assert(VT.getSizeInBits() != 64 && "Can't lower MMX shuffles");
9573 bool V1IsUndef = V1.getOpcode() == ISD::UNDEF;
9574 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
9575 if (V1IsUndef && V2IsUndef)
9576 return DAG.getUNDEF(VT);
9578 // When we create a shuffle node we put the UNDEF node to second operand,
9579 // but in some cases the first operand may be transformed to UNDEF.
9580 // In this case we should just commute the node.
9582 return DAG.getCommutedVectorShuffle(*SVOp);
9584 // Check for non-undef masks pointing at an undef vector and make the masks
9585 // undef as well. This makes it easier to match the shuffle based solely on
9589 if (M >= NumElements) {
9590 SmallVector<int, 8> NewMask(Mask.begin(), Mask.end());
9591 for (int &M : NewMask)
9592 if (M >= NumElements)
9594 return DAG.getVectorShuffle(VT, dl, V1, V2, NewMask);
9597 // For integer vector shuffles, try to collapse them into a shuffle of fewer
9598 // lanes but wider integers. We cap this to not form integers larger than i64
9599 // but it might be interesting to form i128 integers to handle flipping the
9600 // low and high halves of AVX 256-bit vectors.
9601 if (VT.isInteger() && VT.getScalarSizeInBits() < 64 &&
9602 canWidenShuffleElements(Mask)) {
9603 SmallVector<int, 8> NewMask;
9604 for (int i = 0, Size = Mask.size(); i < Size; i += 2)
9605 NewMask.push_back(Mask[i] != -1
9607 : (Mask[i + 1] != -1 ? Mask[i + 1] / 2 : -1));
9609 MVT::getVectorVT(MVT::getIntegerVT(VT.getScalarSizeInBits() * 2),
9610 VT.getVectorNumElements() / 2);
9611 V1 = DAG.getNode(ISD::BITCAST, dl, NewVT, V1);
9612 V2 = DAG.getNode(ISD::BITCAST, dl, NewVT, V2);
9613 return DAG.getNode(ISD::BITCAST, dl, VT,
9614 DAG.getVectorShuffle(NewVT, dl, V1, V2, NewMask));
9617 int NumV1Elements = 0, NumUndefElements = 0, NumV2Elements = 0;
9618 for (int M : SVOp->getMask())
9621 else if (M < NumElements)
9626 // Commute the shuffle as needed such that more elements come from V1 than
9627 // V2. This allows us to match the shuffle pattern strictly on how many
9628 // elements come from V1 without handling the symmetric cases.
9629 if (NumV2Elements > NumV1Elements)
9630 return DAG.getCommutedVectorShuffle(*SVOp);
9632 // When the number of V1 and V2 elements are the same, try to minimize the
9633 // number of uses of V2 in the low half of the vector. When that is tied,
9634 // ensure that the sum of indices for V1 is equal to or lower than the sum
9636 if (NumV1Elements == NumV2Elements) {
9637 int LowV1Elements = 0, LowV2Elements = 0;
9638 for (int M : SVOp->getMask().slice(0, NumElements / 2))
9639 if (M >= NumElements)
9643 if (LowV2Elements > LowV1Elements)
9644 return DAG.getCommutedVectorShuffle(*SVOp);
9646 int SumV1Indices = 0, SumV2Indices = 0;
9647 for (int i = 0, Size = SVOp->getMask().size(); i < Size; ++i)
9648 if (SVOp->getMask()[i] >= NumElements)
9650 else if (SVOp->getMask()[i] >= 0)
9652 if (SumV2Indices < SumV1Indices)
9653 return DAG.getCommutedVectorShuffle(*SVOp);
9656 // For each vector width, delegate to a specialized lowering routine.
9657 if (VT.getSizeInBits() == 128)
9658 return lower128BitVectorShuffle(Op, V1, V2, VT, Subtarget, DAG);
9660 if (VT.getSizeInBits() == 256)
9661 return lower256BitVectorShuffle(Op, V1, V2, VT, Subtarget, DAG);
9663 llvm_unreachable("Unimplemented!");
9667 //===----------------------------------------------------------------------===//
9668 // Legacy vector shuffle lowering
9670 // This code is the legacy code handling vector shuffles until the above
9671 // replaces its functionality and performance.
9672 //===----------------------------------------------------------------------===//
9674 static bool isBlendMask(ArrayRef<int> MaskVals, MVT VT, bool hasSSE41,
9675 bool hasInt256, unsigned *MaskOut = nullptr) {
9676 MVT EltVT = VT.getVectorElementType();
9678 // There is no blend with immediate in AVX-512.
9679 if (VT.is512BitVector())
9682 if (!hasSSE41 || EltVT == MVT::i8)
9684 if (!hasInt256 && VT == MVT::v16i16)
9687 unsigned MaskValue = 0;
9688 unsigned NumElems = VT.getVectorNumElements();
9689 // There are 2 lanes if (NumElems > 8), and 1 lane otherwise.
9690 unsigned NumLanes = (NumElems - 1) / 8 + 1;
9691 unsigned NumElemsInLane = NumElems / NumLanes;
9693 // Blend for v16i16 should be symetric for the both lanes.
9694 for (unsigned i = 0; i < NumElemsInLane; ++i) {
9696 int SndLaneEltIdx = (NumLanes == 2) ? MaskVals[i + NumElemsInLane] : -1;
9697 int EltIdx = MaskVals[i];
9699 if ((EltIdx < 0 || EltIdx == (int)i) &&
9700 (SndLaneEltIdx < 0 || SndLaneEltIdx == (int)(i + NumElemsInLane)))
9703 if (((unsigned)EltIdx == (i + NumElems)) &&
9704 (SndLaneEltIdx < 0 ||
9705 (unsigned)SndLaneEltIdx == i + NumElems + NumElemsInLane))
9706 MaskValue |= (1 << i);
9712 *MaskOut = MaskValue;
9716 // Try to lower a shuffle node into a simple blend instruction.
9717 // This function assumes isBlendMask returns true for this
9718 // SuffleVectorSDNode
9719 static SDValue LowerVECTOR_SHUFFLEtoBlend(ShuffleVectorSDNode *SVOp,
9721 const X86Subtarget *Subtarget,
9722 SelectionDAG &DAG) {
9723 MVT VT = SVOp->getSimpleValueType(0);
9724 MVT EltVT = VT.getVectorElementType();
9725 assert(isBlendMask(SVOp->getMask(), VT, Subtarget->hasSSE41(),
9726 Subtarget->hasInt256() && "Trying to lower a "
9727 "VECTOR_SHUFFLE to a Blend but "
9728 "with the wrong mask"));
9729 SDValue V1 = SVOp->getOperand(0);
9730 SDValue V2 = SVOp->getOperand(1);
9732 unsigned NumElems = VT.getVectorNumElements();
9734 // Convert i32 vectors to floating point if it is not AVX2.
9735 // AVX2 introduced VPBLENDD instruction for 128 and 256-bit vectors.
9737 if (EltVT == MVT::i64 || (EltVT == MVT::i32 && !Subtarget->hasInt256())) {
9738 BlendVT = MVT::getVectorVT(MVT::getFloatingPointVT(EltVT.getSizeInBits()),
9740 V1 = DAG.getNode(ISD::BITCAST, dl, VT, V1);
9741 V2 = DAG.getNode(ISD::BITCAST, dl, VT, V2);
9744 SDValue Ret = DAG.getNode(X86ISD::BLENDI, dl, BlendVT, V1, V2,
9745 DAG.getConstant(MaskValue, MVT::i32));
9746 return DAG.getNode(ISD::BITCAST, dl, VT, Ret);
9749 /// In vector type \p VT, return true if the element at index \p InputIdx
9750 /// falls on a different 128-bit lane than \p OutputIdx.
9751 static bool ShuffleCrosses128bitLane(MVT VT, unsigned InputIdx,
9752 unsigned OutputIdx) {
9753 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
9754 return InputIdx * EltSize / 128 != OutputIdx * EltSize / 128;
9757 /// Generate a PSHUFB if possible. Selects elements from \p V1 according to
9758 /// \p MaskVals. MaskVals[OutputIdx] = InputIdx specifies that we want to
9759 /// shuffle the element at InputIdx in V1 to OutputIdx in the result. If \p
9760 /// MaskVals refers to elements outside of \p V1 or is undef (-1), insert a
9762 static SDValue getPSHUFB(ArrayRef<int> MaskVals, SDValue V1, SDLoc &dl,
9763 SelectionDAG &DAG) {
9764 MVT VT = V1.getSimpleValueType();
9765 assert(VT.is128BitVector() || VT.is256BitVector());
9767 MVT EltVT = VT.getVectorElementType();
9768 unsigned EltSizeInBytes = EltVT.getSizeInBits() / 8;
9769 unsigned NumElts = VT.getVectorNumElements();
9771 SmallVector<SDValue, 32> PshufbMask;
9772 for (unsigned OutputIdx = 0; OutputIdx < NumElts; ++OutputIdx) {
9773 int InputIdx = MaskVals[OutputIdx];
9774 unsigned InputByteIdx;
9776 if (InputIdx < 0 || NumElts <= (unsigned)InputIdx)
9777 InputByteIdx = 0x80;
9779 // Cross lane is not allowed.
9780 if (ShuffleCrosses128bitLane(VT, InputIdx, OutputIdx))
9782 InputByteIdx = InputIdx * EltSizeInBytes;
9783 // Index is an byte offset within the 128-bit lane.
9784 InputByteIdx &= 0xf;
9787 for (unsigned j = 0; j < EltSizeInBytes; ++j) {
9788 PshufbMask.push_back(DAG.getConstant(InputByteIdx, MVT::i8));
9789 if (InputByteIdx != 0x80)
9794 MVT ShufVT = MVT::getVectorVT(MVT::i8, PshufbMask.size());
9796 V1 = DAG.getNode(ISD::BITCAST, dl, ShufVT, V1);
9797 return DAG.getNode(X86ISD::PSHUFB, dl, ShufVT, V1,
9798 DAG.getNode(ISD::BUILD_VECTOR, dl, ShufVT, PshufbMask));
9801 // v8i16 shuffles - Prefer shuffles in the following order:
9802 // 1. [all] pshuflw, pshufhw, optional move
9803 // 2. [ssse3] 1 x pshufb
9804 // 3. [ssse3] 2 x pshufb + 1 x por
9805 // 4. [all] mov + pshuflw + pshufhw + N x (pextrw + pinsrw)
9807 LowerVECTOR_SHUFFLEv8i16(SDValue Op, const X86Subtarget *Subtarget,
9808 SelectionDAG &DAG) {
9809 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9810 SDValue V1 = SVOp->getOperand(0);
9811 SDValue V2 = SVOp->getOperand(1);
9813 SmallVector<int, 8> MaskVals;
9815 // Determine if more than 1 of the words in each of the low and high quadwords
9816 // of the result come from the same quadword of one of the two inputs. Undef
9817 // mask values count as coming from any quadword, for better codegen.
9819 // Lo/HiQuad[i] = j indicates how many words from the ith quad of the input
9820 // feeds this quad. For i, 0 and 1 refer to V1, 2 and 3 refer to V2.
9821 unsigned LoQuad[] = { 0, 0, 0, 0 };
9822 unsigned HiQuad[] = { 0, 0, 0, 0 };
9823 // Indices of quads used.
9824 std::bitset<4> InputQuads;
9825 for (unsigned i = 0; i < 8; ++i) {
9826 unsigned *Quad = i < 4 ? LoQuad : HiQuad;
9827 int EltIdx = SVOp->getMaskElt(i);
9828 MaskVals.push_back(EltIdx);
9837 InputQuads.set(EltIdx / 4);
9840 int BestLoQuad = -1;
9841 unsigned MaxQuad = 1;
9842 for (unsigned i = 0; i < 4; ++i) {
9843 if (LoQuad[i] > MaxQuad) {
9845 MaxQuad = LoQuad[i];
9849 int BestHiQuad = -1;
9851 for (unsigned i = 0; i < 4; ++i) {
9852 if (HiQuad[i] > MaxQuad) {
9854 MaxQuad = HiQuad[i];
9858 // For SSSE3, If all 8 words of the result come from only 1 quadword of each
9859 // of the two input vectors, shuffle them into one input vector so only a
9860 // single pshufb instruction is necessary. If there are more than 2 input
9861 // quads, disable the next transformation since it does not help SSSE3.
9862 bool V1Used = InputQuads[0] || InputQuads[1];
9863 bool V2Used = InputQuads[2] || InputQuads[3];
9864 if (Subtarget->hasSSSE3()) {
9865 if (InputQuads.count() == 2 && V1Used && V2Used) {
9866 BestLoQuad = InputQuads[0] ? 0 : 1;
9867 BestHiQuad = InputQuads[2] ? 2 : 3;
9869 if (InputQuads.count() > 2) {
9875 // If BestLoQuad or BestHiQuad are set, shuffle the quads together and update
9876 // the shuffle mask. If a quad is scored as -1, that means that it contains
9877 // words from all 4 input quadwords.
9879 if (BestLoQuad >= 0 || BestHiQuad >= 0) {
9881 BestLoQuad < 0 ? 0 : BestLoQuad,
9882 BestHiQuad < 0 ? 1 : BestHiQuad
9884 NewV = DAG.getVectorShuffle(MVT::v2i64, dl,
9885 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, V1),
9886 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, V2), &MaskV[0]);
9887 NewV = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, NewV);
9889 // Rewrite the MaskVals and assign NewV to V1 if NewV now contains all the
9890 // source words for the shuffle, to aid later transformations.
9891 bool AllWordsInNewV = true;
9892 bool InOrder[2] = { true, true };
9893 for (unsigned i = 0; i != 8; ++i) {
9894 int idx = MaskVals[i];
9896 InOrder[i/4] = false;
9897 if (idx < 0 || (idx/4) == BestLoQuad || (idx/4) == BestHiQuad)
9899 AllWordsInNewV = false;
9903 bool pshuflw = AllWordsInNewV, pshufhw = AllWordsInNewV;
9904 if (AllWordsInNewV) {
9905 for (int i = 0; i != 8; ++i) {
9906 int idx = MaskVals[i];
9909 idx = MaskVals[i] = (idx / 4) == BestLoQuad ? (idx & 3) : (idx & 3) + 4;
9910 if ((idx != i) && idx < 4)
9912 if ((idx != i) && idx > 3)
9921 // If we've eliminated the use of V2, and the new mask is a pshuflw or
9922 // pshufhw, that's as cheap as it gets. Return the new shuffle.
9923 if ((pshufhw && InOrder[0]) || (pshuflw && InOrder[1])) {
9924 unsigned Opc = pshufhw ? X86ISD::PSHUFHW : X86ISD::PSHUFLW;
9925 unsigned TargetMask = 0;
9926 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV,
9927 DAG.getUNDEF(MVT::v8i16), &MaskVals[0]);
9928 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode());
9929 TargetMask = pshufhw ? getShufflePSHUFHWImmediate(SVOp):
9930 getShufflePSHUFLWImmediate(SVOp);
9931 V1 = NewV.getOperand(0);
9932 return getTargetShuffleNode(Opc, dl, MVT::v8i16, V1, TargetMask, DAG);
9936 // Promote splats to a larger type which usually leads to more efficient code.
9937 // FIXME: Is this true if pshufb is available?
9938 if (SVOp->isSplat())
9939 return PromoteSplat(SVOp, DAG);
9941 // If we have SSSE3, and all words of the result are from 1 input vector,
9942 // case 2 is generated, otherwise case 3 is generated. If no SSSE3
9943 // is present, fall back to case 4.
9944 if (Subtarget->hasSSSE3()) {
9945 SmallVector<SDValue,16> pshufbMask;
9947 // If we have elements from both input vectors, set the high bit of the
9948 // shuffle mask element to zero out elements that come from V2 in the V1
9949 // mask, and elements that come from V1 in the V2 mask, so that the two
9950 // results can be OR'd together.
9951 bool TwoInputs = V1Used && V2Used;
9952 V1 = getPSHUFB(MaskVals, V1, dl, DAG);
9954 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
9956 // Calculate the shuffle mask for the second input, shuffle it, and
9957 // OR it with the first shuffled input.
9958 CommuteVectorShuffleMask(MaskVals, 8);
9959 V2 = getPSHUFB(MaskVals, V2, dl, DAG);
9960 V1 = DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
9961 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
9964 // If BestLoQuad >= 0, generate a pshuflw to put the low elements in order,
9965 // and update MaskVals with new element order.
9966 std::bitset<8> InOrder;
9967 if (BestLoQuad >= 0) {
9968 int MaskV[] = { -1, -1, -1, -1, 4, 5, 6, 7 };
9969 for (int i = 0; i != 4; ++i) {
9970 int idx = MaskVals[i];
9973 } else if ((idx / 4) == BestLoQuad) {
9978 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16),
9981 if (NewV.getOpcode() == ISD::VECTOR_SHUFFLE && Subtarget->hasSSE2()) {
9982 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode());
9983 NewV = getTargetShuffleNode(X86ISD::PSHUFLW, dl, MVT::v8i16,
9985 getShufflePSHUFLWImmediate(SVOp), DAG);
9989 // If BestHi >= 0, generate a pshufhw to put the high elements in order,
9990 // and update MaskVals with the new element order.
9991 if (BestHiQuad >= 0) {
9992 int MaskV[] = { 0, 1, 2, 3, -1, -1, -1, -1 };
9993 for (unsigned i = 4; i != 8; ++i) {
9994 int idx = MaskVals[i];
9997 } else if ((idx / 4) == BestHiQuad) {
9998 MaskV[i] = (idx & 3) + 4;
10002 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16),
10005 if (NewV.getOpcode() == ISD::VECTOR_SHUFFLE && Subtarget->hasSSE2()) {
10006 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode());
10007 NewV = getTargetShuffleNode(X86ISD::PSHUFHW, dl, MVT::v8i16,
10008 NewV.getOperand(0),
10009 getShufflePSHUFHWImmediate(SVOp), DAG);
10013 // In case BestHi & BestLo were both -1, which means each quadword has a word
10014 // from each of the four input quadwords, calculate the InOrder bitvector now
10015 // before falling through to the insert/extract cleanup.
10016 if (BestLoQuad == -1 && BestHiQuad == -1) {
10018 for (int i = 0; i != 8; ++i)
10019 if (MaskVals[i] < 0 || MaskVals[i] == i)
10023 // The other elements are put in the right place using pextrw and pinsrw.
10024 for (unsigned i = 0; i != 8; ++i) {
10027 int EltIdx = MaskVals[i];
10030 SDValue ExtOp = (EltIdx < 8) ?
10031 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V1,
10032 DAG.getIntPtrConstant(EltIdx)) :
10033 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V2,
10034 DAG.getIntPtrConstant(EltIdx - 8));
10035 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, ExtOp,
10036 DAG.getIntPtrConstant(i));
10041 /// \brief v16i16 shuffles
10043 /// FIXME: We only support generation of a single pshufb currently. We can
10044 /// generalize the other applicable cases from LowerVECTOR_SHUFFLEv8i16 as
10045 /// well (e.g 2 x pshufb + 1 x por).
10047 LowerVECTOR_SHUFFLEv16i16(SDValue Op, SelectionDAG &DAG) {
10048 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10049 SDValue V1 = SVOp->getOperand(0);
10050 SDValue V2 = SVOp->getOperand(1);
10053 if (V2.getOpcode() != ISD::UNDEF)
10056 SmallVector<int, 16> MaskVals(SVOp->getMask().begin(), SVOp->getMask().end());
10057 return getPSHUFB(MaskVals, V1, dl, DAG);
10060 // v16i8 shuffles - Prefer shuffles in the following order:
10061 // 1. [ssse3] 1 x pshufb
10062 // 2. [ssse3] 2 x pshufb + 1 x por
10063 // 3. [all] v8i16 shuffle + N x pextrw + rotate + pinsrw
10064 static SDValue LowerVECTOR_SHUFFLEv16i8(ShuffleVectorSDNode *SVOp,
10065 const X86Subtarget* Subtarget,
10066 SelectionDAG &DAG) {
10067 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
10068 SDValue V1 = SVOp->getOperand(0);
10069 SDValue V2 = SVOp->getOperand(1);
10071 ArrayRef<int> MaskVals = SVOp->getMask();
10073 // Promote splats to a larger type which usually leads to more efficient code.
10074 // FIXME: Is this true if pshufb is available?
10075 if (SVOp->isSplat())
10076 return PromoteSplat(SVOp, DAG);
10078 // If we have SSSE3, case 1 is generated when all result bytes come from
10079 // one of the inputs. Otherwise, case 2 is generated. If no SSSE3 is
10080 // present, fall back to case 3.
10082 // If SSSE3, use 1 pshufb instruction per vector with elements in the result.
10083 if (Subtarget->hasSSSE3()) {
10084 SmallVector<SDValue,16> pshufbMask;
10086 // If all result elements are from one input vector, then only translate
10087 // undef mask values to 0x80 (zero out result) in the pshufb mask.
10089 // Otherwise, we have elements from both input vectors, and must zero out
10090 // elements that come from V2 in the first mask, and V1 in the second mask
10091 // so that we can OR them together.
10092 for (unsigned i = 0; i != 16; ++i) {
10093 int EltIdx = MaskVals[i];
10094 if (EltIdx < 0 || EltIdx >= 16)
10096 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
10098 V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1,
10099 DAG.getNode(ISD::BUILD_VECTOR, dl,
10100 MVT::v16i8, pshufbMask));
10102 // As PSHUFB will zero elements with negative indices, it's safe to ignore
10103 // the 2nd operand if it's undefined or zero.
10104 if (V2.getOpcode() == ISD::UNDEF ||
10105 ISD::isBuildVectorAllZeros(V2.getNode()))
10108 // Calculate the shuffle mask for the second input, shuffle it, and
10109 // OR it with the first shuffled input.
10110 pshufbMask.clear();
10111 for (unsigned i = 0; i != 16; ++i) {
10112 int EltIdx = MaskVals[i];
10113 EltIdx = (EltIdx < 16) ? 0x80 : EltIdx - 16;
10114 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
10116 V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2,
10117 DAG.getNode(ISD::BUILD_VECTOR, dl,
10118 MVT::v16i8, pshufbMask));
10119 return DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
10122 // No SSSE3 - Calculate in place words and then fix all out of place words
10123 // With 0-16 extracts & inserts. Worst case is 16 bytes out of order from
10124 // the 16 different words that comprise the two doublequadword input vectors.
10125 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
10126 V2 = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V2);
10128 for (int i = 0; i != 8; ++i) {
10129 int Elt0 = MaskVals[i*2];
10130 int Elt1 = MaskVals[i*2+1];
10132 // This word of the result is all undef, skip it.
10133 if (Elt0 < 0 && Elt1 < 0)
10136 // This word of the result is already in the correct place, skip it.
10137 if ((Elt0 == i*2) && (Elt1 == i*2+1))
10140 SDValue Elt0Src = Elt0 < 16 ? V1 : V2;
10141 SDValue Elt1Src = Elt1 < 16 ? V1 : V2;
10144 // If Elt0 and Elt1 are defined, are consecutive, and can be load
10145 // using a single extract together, load it and store it.
10146 if ((Elt0 >= 0) && ((Elt0 + 1) == Elt1) && ((Elt0 & 1) == 0)) {
10147 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src,
10148 DAG.getIntPtrConstant(Elt1 / 2));
10149 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt,
10150 DAG.getIntPtrConstant(i));
10154 // If Elt1 is defined, extract it from the appropriate source. If the
10155 // source byte is not also odd, shift the extracted word left 8 bits
10156 // otherwise clear the bottom 8 bits if we need to do an or.
10158 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src,
10159 DAG.getIntPtrConstant(Elt1 / 2));
10160 if ((Elt1 & 1) == 0)
10161 InsElt = DAG.getNode(ISD::SHL, dl, MVT::i16, InsElt,
10163 TLI.getShiftAmountTy(InsElt.getValueType())));
10164 else if (Elt0 >= 0)
10165 InsElt = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt,
10166 DAG.getConstant(0xFF00, MVT::i16));
10168 // If Elt0 is defined, extract it from the appropriate source. If the
10169 // source byte is not also even, shift the extracted word right 8 bits. If
10170 // Elt1 was also defined, OR the extracted values together before
10171 // inserting them in the result.
10173 SDValue InsElt0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16,
10174 Elt0Src, DAG.getIntPtrConstant(Elt0 / 2));
10175 if ((Elt0 & 1) != 0)
10176 InsElt0 = DAG.getNode(ISD::SRL, dl, MVT::i16, InsElt0,
10178 TLI.getShiftAmountTy(InsElt0.getValueType())));
10179 else if (Elt1 >= 0)
10180 InsElt0 = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt0,
10181 DAG.getConstant(0x00FF, MVT::i16));
10182 InsElt = Elt1 >= 0 ? DAG.getNode(ISD::OR, dl, MVT::i16, InsElt, InsElt0)
10185 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt,
10186 DAG.getIntPtrConstant(i));
10188 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, NewV);
10191 // v32i8 shuffles - Translate to VPSHUFB if possible.
10193 SDValue LowerVECTOR_SHUFFLEv32i8(ShuffleVectorSDNode *SVOp,
10194 const X86Subtarget *Subtarget,
10195 SelectionDAG &DAG) {
10196 MVT VT = SVOp->getSimpleValueType(0);
10197 SDValue V1 = SVOp->getOperand(0);
10198 SDValue V2 = SVOp->getOperand(1);
10200 SmallVector<int, 32> MaskVals(SVOp->getMask().begin(), SVOp->getMask().end());
10202 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
10203 bool V1IsAllZero = ISD::isBuildVectorAllZeros(V1.getNode());
10204 bool V2IsAllZero = ISD::isBuildVectorAllZeros(V2.getNode());
10206 // VPSHUFB may be generated if
10207 // (1) one of input vector is undefined or zeroinitializer.
10208 // The mask value 0x80 puts 0 in the corresponding slot of the vector.
10209 // And (2) the mask indexes don't cross the 128-bit lane.
10210 if (VT != MVT::v32i8 || !Subtarget->hasInt256() ||
10211 (!V2IsUndef && !V2IsAllZero && !V1IsAllZero))
10214 if (V1IsAllZero && !V2IsAllZero) {
10215 CommuteVectorShuffleMask(MaskVals, 32);
10218 return getPSHUFB(MaskVals, V1, dl, DAG);
10221 /// RewriteAsNarrowerShuffle - Try rewriting v8i16 and v16i8 shuffles as 4 wide
10222 /// ones, or rewriting v4i32 / v4f32 as 2 wide ones if possible. This can be
10223 /// done when every pair / quad of shuffle mask elements point to elements in
10224 /// the right sequence. e.g.
10225 /// vector_shuffle X, Y, <2, 3, | 10, 11, | 0, 1, | 14, 15>
10227 SDValue RewriteAsNarrowerShuffle(ShuffleVectorSDNode *SVOp,
10228 SelectionDAG &DAG) {
10229 MVT VT = SVOp->getSimpleValueType(0);
10231 unsigned NumElems = VT.getVectorNumElements();
10234 switch (VT.SimpleTy) {
10235 default: llvm_unreachable("Unexpected!");
10238 return SDValue(SVOp, 0);
10239 case MVT::v4f32: NewVT = MVT::v2f64; Scale = 2; break;
10240 case MVT::v4i32: NewVT = MVT::v2i64; Scale = 2; break;
10241 case MVT::v8i16: NewVT = MVT::v4i32; Scale = 2; break;
10242 case MVT::v16i8: NewVT = MVT::v4i32; Scale = 4; break;
10243 case MVT::v16i16: NewVT = MVT::v8i32; Scale = 2; break;
10244 case MVT::v32i8: NewVT = MVT::v8i32; Scale = 4; break;
10247 SmallVector<int, 8> MaskVec;
10248 for (unsigned i = 0; i != NumElems; i += Scale) {
10250 for (unsigned j = 0; j != Scale; ++j) {
10251 int EltIdx = SVOp->getMaskElt(i+j);
10255 StartIdx = (EltIdx / Scale);
10256 if (EltIdx != (int)(StartIdx*Scale + j))
10259 MaskVec.push_back(StartIdx);
10262 SDValue V1 = DAG.getNode(ISD::BITCAST, dl, NewVT, SVOp->getOperand(0));
10263 SDValue V2 = DAG.getNode(ISD::BITCAST, dl, NewVT, SVOp->getOperand(1));
10264 return DAG.getVectorShuffle(NewVT, dl, V1, V2, &MaskVec[0]);
10267 /// getVZextMovL - Return a zero-extending vector move low node.
10269 static SDValue getVZextMovL(MVT VT, MVT OpVT,
10270 SDValue SrcOp, SelectionDAG &DAG,
10271 const X86Subtarget *Subtarget, SDLoc dl) {
10272 if (VT == MVT::v2f64 || VT == MVT::v4f32) {
10273 LoadSDNode *LD = nullptr;
10274 if (!isScalarLoadToVector(SrcOp.getNode(), &LD))
10275 LD = dyn_cast<LoadSDNode>(SrcOp);
10277 // movssrr and movsdrr do not clear top bits. Try to use movd, movq
10279 MVT ExtVT = (OpVT == MVT::v2f64) ? MVT::i64 : MVT::i32;
10280 if ((ExtVT != MVT::i64 || Subtarget->is64Bit()) &&
10281 SrcOp.getOpcode() == ISD::SCALAR_TO_VECTOR &&
10282 SrcOp.getOperand(0).getOpcode() == ISD::BITCAST &&
10283 SrcOp.getOperand(0).getOperand(0).getValueType() == ExtVT) {
10285 OpVT = (OpVT == MVT::v2f64) ? MVT::v2i64 : MVT::v4i32;
10286 return DAG.getNode(ISD::BITCAST, dl, VT,
10287 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT,
10288 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
10290 SrcOp.getOperand(0)
10296 return DAG.getNode(ISD::BITCAST, dl, VT,
10297 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT,
10298 DAG.getNode(ISD::BITCAST, dl,
10302 /// LowerVECTOR_SHUFFLE_256 - Handle all 256-bit wide vectors shuffles
10303 /// which could not be matched by any known target speficic shuffle
10305 LowerVECTOR_SHUFFLE_256(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
10307 SDValue NewOp = Compact8x32ShuffleNode(SVOp, DAG);
10308 if (NewOp.getNode())
10311 MVT VT = SVOp->getSimpleValueType(0);
10313 unsigned NumElems = VT.getVectorNumElements();
10314 unsigned NumLaneElems = NumElems / 2;
10317 MVT EltVT = VT.getVectorElementType();
10318 MVT NVT = MVT::getVectorVT(EltVT, NumLaneElems);
10321 SmallVector<int, 16> Mask;
10322 for (unsigned l = 0; l < 2; ++l) {
10323 // Build a shuffle mask for the output, discovering on the fly which
10324 // input vectors to use as shuffle operands (recorded in InputUsed).
10325 // If building a suitable shuffle vector proves too hard, then bail
10326 // out with UseBuildVector set.
10327 bool UseBuildVector = false;
10328 int InputUsed[2] = { -1, -1 }; // Not yet discovered.
10329 unsigned LaneStart = l * NumLaneElems;
10330 for (unsigned i = 0; i != NumLaneElems; ++i) {
10331 // The mask element. This indexes into the input.
10332 int Idx = SVOp->getMaskElt(i+LaneStart);
10334 // the mask element does not index into any input vector.
10335 Mask.push_back(-1);
10339 // The input vector this mask element indexes into.
10340 int Input = Idx / NumLaneElems;
10342 // Turn the index into an offset from the start of the input vector.
10343 Idx -= Input * NumLaneElems;
10345 // Find or create a shuffle vector operand to hold this input.
10347 for (OpNo = 0; OpNo < array_lengthof(InputUsed); ++OpNo) {
10348 if (InputUsed[OpNo] == Input)
10349 // This input vector is already an operand.
10351 if (InputUsed[OpNo] < 0) {
10352 // Create a new operand for this input vector.
10353 InputUsed[OpNo] = Input;
10358 if (OpNo >= array_lengthof(InputUsed)) {
10359 // More than two input vectors used! Give up on trying to create a
10360 // shuffle vector. Insert all elements into a BUILD_VECTOR instead.
10361 UseBuildVector = true;
10365 // Add the mask index for the new shuffle vector.
10366 Mask.push_back(Idx + OpNo * NumLaneElems);
10369 if (UseBuildVector) {
10370 SmallVector<SDValue, 16> SVOps;
10371 for (unsigned i = 0; i != NumLaneElems; ++i) {
10372 // The mask element. This indexes into the input.
10373 int Idx = SVOp->getMaskElt(i+LaneStart);
10375 SVOps.push_back(DAG.getUNDEF(EltVT));
10379 // The input vector this mask element indexes into.
10380 int Input = Idx / NumElems;
10382 // Turn the index into an offset from the start of the input vector.
10383 Idx -= Input * NumElems;
10385 // Extract the vector element by hand.
10386 SVOps.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT,
10387 SVOp->getOperand(Input),
10388 DAG.getIntPtrConstant(Idx)));
10391 // Construct the output using a BUILD_VECTOR.
10392 Output[l] = DAG.getNode(ISD::BUILD_VECTOR, dl, NVT, SVOps);
10393 } else if (InputUsed[0] < 0) {
10394 // No input vectors were used! The result is undefined.
10395 Output[l] = DAG.getUNDEF(NVT);
10397 SDValue Op0 = Extract128BitVector(SVOp->getOperand(InputUsed[0] / 2),
10398 (InputUsed[0] % 2) * NumLaneElems,
10400 // If only one input was used, use an undefined vector for the other.
10401 SDValue Op1 = (InputUsed[1] < 0) ? DAG.getUNDEF(NVT) :
10402 Extract128BitVector(SVOp->getOperand(InputUsed[1] / 2),
10403 (InputUsed[1] % 2) * NumLaneElems, DAG, dl);
10404 // At least one input vector was used. Create a new shuffle vector.
10405 Output[l] = DAG.getVectorShuffle(NVT, dl, Op0, Op1, &Mask[0]);
10411 // Concatenate the result back
10412 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, Output[0], Output[1]);
10415 /// LowerVECTOR_SHUFFLE_128v4 - Handle all 128-bit wide vectors with
10416 /// 4 elements, and match them with several different shuffle types.
10418 LowerVECTOR_SHUFFLE_128v4(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
10419 SDValue V1 = SVOp->getOperand(0);
10420 SDValue V2 = SVOp->getOperand(1);
10422 MVT VT = SVOp->getSimpleValueType(0);
10424 assert(VT.is128BitVector() && "Unsupported vector size");
10426 std::pair<int, int> Locs[4];
10427 int Mask1[] = { -1, -1, -1, -1 };
10428 SmallVector<int, 8> PermMask(SVOp->getMask().begin(), SVOp->getMask().end());
10430 unsigned NumHi = 0;
10431 unsigned NumLo = 0;
10432 for (unsigned i = 0; i != 4; ++i) {
10433 int Idx = PermMask[i];
10435 Locs[i] = std::make_pair(-1, -1);
10437 assert(Idx < 8 && "Invalid VECTOR_SHUFFLE index!");
10439 Locs[i] = std::make_pair(0, NumLo);
10440 Mask1[NumLo] = Idx;
10443 Locs[i] = std::make_pair(1, NumHi);
10445 Mask1[2+NumHi] = Idx;
10451 if (NumLo <= 2 && NumHi <= 2) {
10452 // If no more than two elements come from either vector. This can be
10453 // implemented with two shuffles. First shuffle gather the elements.
10454 // The second shuffle, which takes the first shuffle as both of its
10455 // vector operands, put the elements into the right order.
10456 V1 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
10458 int Mask2[] = { -1, -1, -1, -1 };
10460 for (unsigned i = 0; i != 4; ++i)
10461 if (Locs[i].first != -1) {
10462 unsigned Idx = (i < 2) ? 0 : 4;
10463 Idx += Locs[i].first * 2 + Locs[i].second;
10467 return DAG.getVectorShuffle(VT, dl, V1, V1, &Mask2[0]);
10470 if (NumLo == 3 || NumHi == 3) {
10471 // Otherwise, we must have three elements from one vector, call it X, and
10472 // one element from the other, call it Y. First, use a shufps to build an
10473 // intermediate vector with the one element from Y and the element from X
10474 // that will be in the same half in the final destination (the indexes don't
10475 // matter). Then, use a shufps to build the final vector, taking the half
10476 // containing the element from Y from the intermediate, and the other half
10479 // Normalize it so the 3 elements come from V1.
10480 CommuteVectorShuffleMask(PermMask, 4);
10484 // Find the element from V2.
10486 for (HiIndex = 0; HiIndex < 3; ++HiIndex) {
10487 int Val = PermMask[HiIndex];
10494 Mask1[0] = PermMask[HiIndex];
10496 Mask1[2] = PermMask[HiIndex^1];
10498 V2 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
10500 if (HiIndex >= 2) {
10501 Mask1[0] = PermMask[0];
10502 Mask1[1] = PermMask[1];
10503 Mask1[2] = HiIndex & 1 ? 6 : 4;
10504 Mask1[3] = HiIndex & 1 ? 4 : 6;
10505 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
10508 Mask1[0] = HiIndex & 1 ? 2 : 0;
10509 Mask1[1] = HiIndex & 1 ? 0 : 2;
10510 Mask1[2] = PermMask[2];
10511 Mask1[3] = PermMask[3];
10516 return DAG.getVectorShuffle(VT, dl, V2, V1, &Mask1[0]);
10519 // Break it into (shuffle shuffle_hi, shuffle_lo).
10520 int LoMask[] = { -1, -1, -1, -1 };
10521 int HiMask[] = { -1, -1, -1, -1 };
10523 int *MaskPtr = LoMask;
10524 unsigned MaskIdx = 0;
10525 unsigned LoIdx = 0;
10526 unsigned HiIdx = 2;
10527 for (unsigned i = 0; i != 4; ++i) {
10534 int Idx = PermMask[i];
10536 Locs[i] = std::make_pair(-1, -1);
10537 } else if (Idx < 4) {
10538 Locs[i] = std::make_pair(MaskIdx, LoIdx);
10539 MaskPtr[LoIdx] = Idx;
10542 Locs[i] = std::make_pair(MaskIdx, HiIdx);
10543 MaskPtr[HiIdx] = Idx;
10548 SDValue LoShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &LoMask[0]);
10549 SDValue HiShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &HiMask[0]);
10550 int MaskOps[] = { -1, -1, -1, -1 };
10551 for (unsigned i = 0; i != 4; ++i)
10552 if (Locs[i].first != -1)
10553 MaskOps[i] = Locs[i].first * 4 + Locs[i].second;
10554 return DAG.getVectorShuffle(VT, dl, LoShuffle, HiShuffle, &MaskOps[0]);
10557 static bool MayFoldVectorLoad(SDValue V) {
10558 while (V.hasOneUse() && V.getOpcode() == ISD::BITCAST)
10559 V = V.getOperand(0);
10561 if (V.hasOneUse() && V.getOpcode() == ISD::SCALAR_TO_VECTOR)
10562 V = V.getOperand(0);
10563 if (V.hasOneUse() && V.getOpcode() == ISD::BUILD_VECTOR &&
10564 V.getNumOperands() == 2 && V.getOperand(1).getOpcode() == ISD::UNDEF)
10565 // BUILD_VECTOR (load), undef
10566 V = V.getOperand(0);
10568 return MayFoldLoad(V);
10572 SDValue getMOVDDup(SDValue &Op, SDLoc &dl, SDValue V1, SelectionDAG &DAG) {
10573 MVT VT = Op.getSimpleValueType();
10575 // Canonizalize to v2f64.
10576 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, V1);
10577 return DAG.getNode(ISD::BITCAST, dl, VT,
10578 getTargetShuffleNode(X86ISD::MOVDDUP, dl, MVT::v2f64,
10583 SDValue getMOVLowToHigh(SDValue &Op, SDLoc &dl, SelectionDAG &DAG,
10585 SDValue V1 = Op.getOperand(0);
10586 SDValue V2 = Op.getOperand(1);
10587 MVT VT = Op.getSimpleValueType();
10589 assert(VT != MVT::v2i64 && "unsupported shuffle type");
10591 if (HasSSE2 && VT == MVT::v2f64)
10592 return getTargetShuffleNode(X86ISD::MOVLHPD, dl, VT, V1, V2, DAG);
10594 // v4f32 or v4i32: canonizalized to v4f32 (which is legal for SSE1)
10595 return DAG.getNode(ISD::BITCAST, dl, VT,
10596 getTargetShuffleNode(X86ISD::MOVLHPS, dl, MVT::v4f32,
10597 DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V1),
10598 DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V2), DAG));
10602 SDValue getMOVHighToLow(SDValue &Op, SDLoc &dl, SelectionDAG &DAG) {
10603 SDValue V1 = Op.getOperand(0);
10604 SDValue V2 = Op.getOperand(1);
10605 MVT VT = Op.getSimpleValueType();
10607 assert((VT == MVT::v4i32 || VT == MVT::v4f32) &&
10608 "unsupported shuffle type");
10610 if (V2.getOpcode() == ISD::UNDEF)
10614 return getTargetShuffleNode(X86ISD::MOVHLPS, dl, VT, V1, V2, DAG);
10618 SDValue getMOVLP(SDValue &Op, SDLoc &dl, SelectionDAG &DAG, bool HasSSE2) {
10619 SDValue V1 = Op.getOperand(0);
10620 SDValue V2 = Op.getOperand(1);
10621 MVT VT = Op.getSimpleValueType();
10622 unsigned NumElems = VT.getVectorNumElements();
10624 // Use MOVLPS and MOVLPD in case V1 or V2 are loads. During isel, the second
10625 // operand of these instructions is only memory, so check if there's a
10626 // potencial load folding here, otherwise use SHUFPS or MOVSD to match the
10628 bool CanFoldLoad = false;
10630 // Trivial case, when V2 comes from a load.
10631 if (MayFoldVectorLoad(V2))
10632 CanFoldLoad = true;
10634 // When V1 is a load, it can be folded later into a store in isel, example:
10635 // (store (v4f32 (X86Movlps (load addr:$src1), VR128:$src2)), addr:$src1)
10637 // (MOVLPSmr addr:$src1, VR128:$src2)
10638 // So, recognize this potential and also use MOVLPS or MOVLPD
10639 else if (MayFoldVectorLoad(V1) && MayFoldIntoStore(Op))
10640 CanFoldLoad = true;
10642 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10644 if (HasSSE2 && NumElems == 2)
10645 return getTargetShuffleNode(X86ISD::MOVLPD, dl, VT, V1, V2, DAG);
10648 // If we don't care about the second element, proceed to use movss.
10649 if (SVOp->getMaskElt(1) != -1)
10650 return getTargetShuffleNode(X86ISD::MOVLPS, dl, VT, V1, V2, DAG);
10653 // movl and movlp will both match v2i64, but v2i64 is never matched by
10654 // movl earlier because we make it strict to avoid messing with the movlp load
10655 // folding logic (see the code above getMOVLP call). Match it here then,
10656 // this is horrible, but will stay like this until we move all shuffle
10657 // matching to x86 specific nodes. Note that for the 1st condition all
10658 // types are matched with movsd.
10660 // FIXME: isMOVLMask should be checked and matched before getMOVLP,
10661 // as to remove this logic from here, as much as possible
10662 if (NumElems == 2 || !isMOVLMask(SVOp->getMask(), VT))
10663 return getTargetShuffleNode(X86ISD::MOVSD, dl, VT, V1, V2, DAG);
10664 return getTargetShuffleNode(X86ISD::MOVSS, dl, VT, V1, V2, DAG);
10667 assert(VT != MVT::v4i32 && "unsupported shuffle type");
10669 // Invert the operand order and use SHUFPS to match it.
10670 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V2, V1,
10671 getShuffleSHUFImmediate(SVOp), DAG);
10674 static SDValue NarrowVectorLoadToElement(LoadSDNode *Load, unsigned Index,
10675 SelectionDAG &DAG) {
10677 MVT VT = Load->getSimpleValueType(0);
10678 MVT EVT = VT.getVectorElementType();
10679 SDValue Addr = Load->getOperand(1);
10680 SDValue NewAddr = DAG.getNode(
10681 ISD::ADD, dl, Addr.getSimpleValueType(), Addr,
10682 DAG.getConstant(Index * EVT.getStoreSize(), Addr.getSimpleValueType()));
10685 DAG.getLoad(EVT, dl, Load->getChain(), NewAddr,
10686 DAG.getMachineFunction().getMachineMemOperand(
10687 Load->getMemOperand(), 0, EVT.getStoreSize()));
10691 // It is only safe to call this function if isINSERTPSMask is true for
10692 // this shufflevector mask.
10693 static SDValue getINSERTPS(ShuffleVectorSDNode *SVOp, SDLoc &dl,
10694 SelectionDAG &DAG) {
10695 // Generate an insertps instruction when inserting an f32 from memory onto a
10696 // v4f32 or when copying a member from one v4f32 to another.
10697 // We also use it for transferring i32 from one register to another,
10698 // since it simply copies the same bits.
10699 // If we're transferring an i32 from memory to a specific element in a
10700 // register, we output a generic DAG that will match the PINSRD
10702 MVT VT = SVOp->getSimpleValueType(0);
10703 MVT EVT = VT.getVectorElementType();
10704 SDValue V1 = SVOp->getOperand(0);
10705 SDValue V2 = SVOp->getOperand(1);
10706 auto Mask = SVOp->getMask();
10707 assert((VT == MVT::v4f32 || VT == MVT::v4i32) &&
10708 "unsupported vector type for insertps/pinsrd");
10710 auto FromV1Predicate = [](const int &i) { return i < 4 && i > -1; };
10711 auto FromV2Predicate = [](const int &i) { return i >= 4; };
10712 int FromV1 = std::count_if(Mask.begin(), Mask.end(), FromV1Predicate);
10716 unsigned DestIndex;
10720 DestIndex = std::find_if(Mask.begin(), Mask.end(), FromV1Predicate) -
10723 // If we have 1 element from each vector, we have to check if we're
10724 // changing V1's element's place. If so, we're done. Otherwise, we
10725 // should assume we're changing V2's element's place and behave
10727 int FromV2 = std::count_if(Mask.begin(), Mask.end(), FromV2Predicate);
10728 assert(DestIndex <= INT32_MAX && "truncated destination index");
10729 if (FromV1 == FromV2 &&
10730 static_cast<int>(DestIndex) == Mask[DestIndex] % 4) {
10734 std::find_if(Mask.begin(), Mask.end(), FromV2Predicate) - Mask.begin();
10737 assert(std::count_if(Mask.begin(), Mask.end(), FromV2Predicate) == 1 &&
10738 "More than one element from V1 and from V2, or no elements from one "
10739 "of the vectors. This case should not have returned true from "
10744 std::find_if(Mask.begin(), Mask.end(), FromV2Predicate) - Mask.begin();
10747 // Get an index into the source vector in the range [0,4) (the mask is
10748 // in the range [0,8) because it can address V1 and V2)
10749 unsigned SrcIndex = Mask[DestIndex] % 4;
10750 if (MayFoldLoad(From)) {
10751 // Trivial case, when From comes from a load and is only used by the
10752 // shuffle. Make it use insertps from the vector that we need from that
10755 NarrowVectorLoadToElement(cast<LoadSDNode>(From), SrcIndex, DAG);
10756 if (!NewLoad.getNode())
10759 if (EVT == MVT::f32) {
10760 // Create this as a scalar to vector to match the instruction pattern.
10761 SDValue LoadScalarToVector =
10762 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, NewLoad);
10763 SDValue InsertpsMask = DAG.getIntPtrConstant(DestIndex << 4);
10764 return DAG.getNode(X86ISD::INSERTPS, dl, VT, To, LoadScalarToVector,
10766 } else { // EVT == MVT::i32
10767 // If we're getting an i32 from memory, use an INSERT_VECTOR_ELT
10768 // instruction, to match the PINSRD instruction, which loads an i32 to a
10769 // certain vector element.
10770 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, To, NewLoad,
10771 DAG.getConstant(DestIndex, MVT::i32));
10775 // Vector-element-to-vector
10776 SDValue InsertpsMask = DAG.getIntPtrConstant(DestIndex << 4 | SrcIndex << 6);
10777 return DAG.getNode(X86ISD::INSERTPS, dl, VT, To, From, InsertpsMask);
10780 // Reduce a vector shuffle to zext.
10781 static SDValue LowerVectorIntExtend(SDValue Op, const X86Subtarget *Subtarget,
10782 SelectionDAG &DAG) {
10783 // PMOVZX is only available from SSE41.
10784 if (!Subtarget->hasSSE41())
10787 MVT VT = Op.getSimpleValueType();
10789 // Only AVX2 support 256-bit vector integer extending.
10790 if (!Subtarget->hasInt256() && VT.is256BitVector())
10793 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10795 SDValue V1 = Op.getOperand(0);
10796 SDValue V2 = Op.getOperand(1);
10797 unsigned NumElems = VT.getVectorNumElements();
10799 // Extending is an unary operation and the element type of the source vector
10800 // won't be equal to or larger than i64.
10801 if (V2.getOpcode() != ISD::UNDEF || !VT.isInteger() ||
10802 VT.getVectorElementType() == MVT::i64)
10805 // Find the expansion ratio, e.g. expanding from i8 to i32 has a ratio of 4.
10806 unsigned Shift = 1; // Start from 2, i.e. 1 << 1.
10807 while ((1U << Shift) < NumElems) {
10808 if (SVOp->getMaskElt(1U << Shift) == 1)
10811 // The maximal ratio is 8, i.e. from i8 to i64.
10816 // Check the shuffle mask.
10817 unsigned Mask = (1U << Shift) - 1;
10818 for (unsigned i = 0; i != NumElems; ++i) {
10819 int EltIdx = SVOp->getMaskElt(i);
10820 if ((i & Mask) != 0 && EltIdx != -1)
10822 if ((i & Mask) == 0 && (unsigned)EltIdx != (i >> Shift))
10826 unsigned NBits = VT.getVectorElementType().getSizeInBits() << Shift;
10827 MVT NeVT = MVT::getIntegerVT(NBits);
10828 MVT NVT = MVT::getVectorVT(NeVT, NumElems >> Shift);
10830 if (!DAG.getTargetLoweringInfo().isTypeLegal(NVT))
10833 // Simplify the operand as it's prepared to be fed into shuffle.
10834 unsigned SignificantBits = NVT.getSizeInBits() >> Shift;
10835 if (V1.getOpcode() == ISD::BITCAST &&
10836 V1.getOperand(0).getOpcode() == ISD::SCALAR_TO_VECTOR &&
10837 V1.getOperand(0).getOperand(0).getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
10838 V1.getOperand(0).getOperand(0)
10839 .getSimpleValueType().getSizeInBits() == SignificantBits) {
10840 // (bitcast (sclr2vec (ext_vec_elt x))) -> (bitcast x)
10841 SDValue V = V1.getOperand(0).getOperand(0).getOperand(0);
10842 ConstantSDNode *CIdx =
10843 dyn_cast<ConstantSDNode>(V1.getOperand(0).getOperand(0).getOperand(1));
10844 // If it's foldable, i.e. normal load with single use, we will let code
10845 // selection to fold it. Otherwise, we will short the conversion sequence.
10846 if (CIdx && CIdx->getZExtValue() == 0 &&
10847 (!ISD::isNormalLoad(V.getNode()) || !V.hasOneUse())) {
10848 MVT FullVT = V.getSimpleValueType();
10849 MVT V1VT = V1.getSimpleValueType();
10850 if (FullVT.getSizeInBits() > V1VT.getSizeInBits()) {
10851 // The "ext_vec_elt" node is wider than the result node.
10852 // In this case we should extract subvector from V.
10853 // (bitcast (sclr2vec (ext_vec_elt x))) -> (bitcast (extract_subvector x)).
10854 unsigned Ratio = FullVT.getSizeInBits() / V1VT.getSizeInBits();
10855 MVT SubVecVT = MVT::getVectorVT(FullVT.getVectorElementType(),
10856 FullVT.getVectorNumElements()/Ratio);
10857 V = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SubVecVT, V,
10858 DAG.getIntPtrConstant(0));
10860 V1 = DAG.getNode(ISD::BITCAST, DL, V1VT, V);
10864 return DAG.getNode(ISD::BITCAST, DL, VT,
10865 DAG.getNode(X86ISD::VZEXT, DL, NVT, V1));
10868 static SDValue NormalizeVectorShuffle(SDValue Op, const X86Subtarget *Subtarget,
10869 SelectionDAG &DAG) {
10870 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10871 MVT VT = Op.getSimpleValueType();
10873 SDValue V1 = Op.getOperand(0);
10874 SDValue V2 = Op.getOperand(1);
10876 if (isZeroShuffle(SVOp))
10877 return getZeroVector(VT, Subtarget, DAG, dl);
10879 // Handle splat operations
10880 if (SVOp->isSplat()) {
10881 // Use vbroadcast whenever the splat comes from a foldable load
10882 SDValue Broadcast = LowerVectorBroadcast(Op, Subtarget, DAG);
10883 if (Broadcast.getNode())
10887 // Check integer expanding shuffles.
10888 SDValue NewOp = LowerVectorIntExtend(Op, Subtarget, DAG);
10889 if (NewOp.getNode())
10892 // If the shuffle can be profitably rewritten as a narrower shuffle, then
10894 if (VT == MVT::v8i16 || VT == MVT::v16i8 || VT == MVT::v16i16 ||
10895 VT == MVT::v32i8) {
10896 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG);
10897 if (NewOp.getNode())
10898 return DAG.getNode(ISD::BITCAST, dl, VT, NewOp);
10899 } else if (VT.is128BitVector() && Subtarget->hasSSE2()) {
10900 // FIXME: Figure out a cleaner way to do this.
10901 if (ISD::isBuildVectorAllZeros(V2.getNode())) {
10902 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG);
10903 if (NewOp.getNode()) {
10904 MVT NewVT = NewOp.getSimpleValueType();
10905 if (isCommutedMOVLMask(cast<ShuffleVectorSDNode>(NewOp)->getMask(),
10906 NewVT, true, false))
10907 return getVZextMovL(VT, NewVT, NewOp.getOperand(0), DAG, Subtarget,
10910 } else if (ISD::isBuildVectorAllZeros(V1.getNode())) {
10911 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG);
10912 if (NewOp.getNode()) {
10913 MVT NewVT = NewOp.getSimpleValueType();
10914 if (isMOVLMask(cast<ShuffleVectorSDNode>(NewOp)->getMask(), NewVT))
10915 return getVZextMovL(VT, NewVT, NewOp.getOperand(1), DAG, Subtarget,
10924 X86TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const {
10925 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10926 SDValue V1 = Op.getOperand(0);
10927 SDValue V2 = Op.getOperand(1);
10928 MVT VT = Op.getSimpleValueType();
10930 unsigned NumElems = VT.getVectorNumElements();
10931 bool V1IsUndef = V1.getOpcode() == ISD::UNDEF;
10932 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
10933 bool V1IsSplat = false;
10934 bool V2IsSplat = false;
10935 bool HasSSE2 = Subtarget->hasSSE2();
10936 bool HasFp256 = Subtarget->hasFp256();
10937 bool HasInt256 = Subtarget->hasInt256();
10938 MachineFunction &MF = DAG.getMachineFunction();
10939 bool OptForSize = MF.getFunction()->getAttributes().
10940 hasAttribute(AttributeSet::FunctionIndex, Attribute::OptimizeForSize);
10942 // Check if we should use the experimental vector shuffle lowering. If so,
10943 // delegate completely to that code path.
10944 if (ExperimentalVectorShuffleLowering)
10945 return lowerVectorShuffle(Op, Subtarget, DAG);
10947 assert(VT.getSizeInBits() != 64 && "Can't lower MMX shuffles");
10949 if (V1IsUndef && V2IsUndef)
10950 return DAG.getUNDEF(VT);
10952 // When we create a shuffle node we put the UNDEF node to second operand,
10953 // but in some cases the first operand may be transformed to UNDEF.
10954 // In this case we should just commute the node.
10956 return DAG.getCommutedVectorShuffle(*SVOp);
10958 // Vector shuffle lowering takes 3 steps:
10960 // 1) Normalize the input vectors. Here splats, zeroed vectors, profitable
10961 // narrowing and commutation of operands should be handled.
10962 // 2) Matching of shuffles with known shuffle masks to x86 target specific
10964 // 3) Rewriting of unmatched masks into new generic shuffle operations,
10965 // so the shuffle can be broken into other shuffles and the legalizer can
10966 // try the lowering again.
10968 // The general idea is that no vector_shuffle operation should be left to
10969 // be matched during isel, all of them must be converted to a target specific
10972 // Normalize the input vectors. Here splats, zeroed vectors, profitable
10973 // narrowing and commutation of operands should be handled. The actual code
10974 // doesn't include all of those, work in progress...
10975 SDValue NewOp = NormalizeVectorShuffle(Op, Subtarget, DAG);
10976 if (NewOp.getNode())
10979 SmallVector<int, 8> M(SVOp->getMask().begin(), SVOp->getMask().end());
10981 // NOTE: isPSHUFDMask can also match both masks below (unpckl_undef and
10982 // unpckh_undef). Only use pshufd if speed is more important than size.
10983 if (OptForSize && isUNPCKL_v_undef_Mask(M, VT, HasInt256))
10984 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
10985 if (OptForSize && isUNPCKH_v_undef_Mask(M, VT, HasInt256))
10986 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
10988 if (isMOVDDUPMask(M, VT) && Subtarget->hasSSE3() &&
10989 V2IsUndef && MayFoldVectorLoad(V1))
10990 return getMOVDDup(Op, dl, V1, DAG);
10992 if (isMOVHLPS_v_undef_Mask(M, VT))
10993 return getMOVHighToLow(Op, dl, DAG);
10995 // Use to match splats
10996 if (HasSSE2 && isUNPCKHMask(M, VT, HasInt256) && V2IsUndef &&
10997 (VT == MVT::v2f64 || VT == MVT::v2i64))
10998 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
11000 if (isPSHUFDMask(M, VT)) {
11001 // The actual implementation will match the mask in the if above and then
11002 // during isel it can match several different instructions, not only pshufd
11003 // as its name says, sad but true, emulate the behavior for now...
11004 if (isMOVDDUPMask(M, VT) && ((VT == MVT::v4f32 || VT == MVT::v2i64)))
11005 return getTargetShuffleNode(X86ISD::MOVLHPS, dl, VT, V1, V1, DAG);
11007 unsigned TargetMask = getShuffleSHUFImmediate(SVOp);
11009 if (HasSSE2 && (VT == MVT::v4f32 || VT == MVT::v4i32))
11010 return getTargetShuffleNode(X86ISD::PSHUFD, dl, VT, V1, TargetMask, DAG);
11012 if (HasFp256 && (VT == MVT::v4f32 || VT == MVT::v2f64))
11013 return getTargetShuffleNode(X86ISD::VPERMILPI, dl, VT, V1, TargetMask,
11016 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V1, V1,
11020 if (isPALIGNRMask(M, VT, Subtarget))
11021 return getTargetShuffleNode(X86ISD::PALIGNR, dl, VT, V1, V2,
11022 getShufflePALIGNRImmediate(SVOp),
11025 if (isVALIGNMask(M, VT, Subtarget))
11026 return getTargetShuffleNode(X86ISD::VALIGN, dl, VT, V1, V2,
11027 getShuffleVALIGNImmediate(SVOp),
11030 // Check if this can be converted into a logical shift.
11031 bool isLeft = false;
11032 unsigned ShAmt = 0;
11034 bool isShift = HasSSE2 && isVectorShift(SVOp, DAG, isLeft, ShVal, ShAmt);
11035 if (isShift && ShVal.hasOneUse()) {
11036 // If the shifted value has multiple uses, it may be cheaper to use
11037 // v_set0 + movlhps or movhlps, etc.
11038 MVT EltVT = VT.getVectorElementType();
11039 ShAmt *= EltVT.getSizeInBits();
11040 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl);
11043 if (isMOVLMask(M, VT)) {
11044 if (ISD::isBuildVectorAllZeros(V1.getNode()))
11045 return getVZextMovL(VT, VT, V2, DAG, Subtarget, dl);
11046 if (!isMOVLPMask(M, VT)) {
11047 if (HasSSE2 && (VT == MVT::v2i64 || VT == MVT::v2f64))
11048 return getTargetShuffleNode(X86ISD::MOVSD, dl, VT, V1, V2, DAG);
11050 if (VT == MVT::v4i32 || VT == MVT::v4f32)
11051 return getTargetShuffleNode(X86ISD::MOVSS, dl, VT, V1, V2, DAG);
11055 // FIXME: fold these into legal mask.
11056 if (isMOVLHPSMask(M, VT) && !isUNPCKLMask(M, VT, HasInt256))
11057 return getMOVLowToHigh(Op, dl, DAG, HasSSE2);
11059 if (isMOVHLPSMask(M, VT))
11060 return getMOVHighToLow(Op, dl, DAG);
11062 if (V2IsUndef && isMOVSHDUPMask(M, VT, Subtarget))
11063 return getTargetShuffleNode(X86ISD::MOVSHDUP, dl, VT, V1, DAG);
11065 if (V2IsUndef && isMOVSLDUPMask(M, VT, Subtarget))
11066 return getTargetShuffleNode(X86ISD::MOVSLDUP, dl, VT, V1, DAG);
11068 if (isMOVLPMask(M, VT))
11069 return getMOVLP(Op, dl, DAG, HasSSE2);
11071 if (ShouldXformToMOVHLPS(M, VT) ||
11072 ShouldXformToMOVLP(V1.getNode(), V2.getNode(), M, VT))
11073 return DAG.getCommutedVectorShuffle(*SVOp);
11076 // No better options. Use a vshldq / vsrldq.
11077 MVT EltVT = VT.getVectorElementType();
11078 ShAmt *= EltVT.getSizeInBits();
11079 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl);
11082 bool Commuted = false;
11083 // FIXME: This should also accept a bitcast of a splat? Be careful, not
11084 // 1,1,1,1 -> v8i16 though.
11085 BitVector UndefElements;
11086 if (auto *BVOp = dyn_cast<BuildVectorSDNode>(V1.getNode()))
11087 if (BVOp->getConstantSplatNode(&UndefElements) && UndefElements.none())
11089 if (auto *BVOp = dyn_cast<BuildVectorSDNode>(V2.getNode()))
11090 if (BVOp->getConstantSplatNode(&UndefElements) && UndefElements.none())
11093 // Canonicalize the splat or undef, if present, to be on the RHS.
11094 if (!V2IsUndef && V1IsSplat && !V2IsSplat) {
11095 CommuteVectorShuffleMask(M, NumElems);
11097 std::swap(V1IsSplat, V2IsSplat);
11101 if (isCommutedMOVLMask(M, VT, V2IsSplat, V2IsUndef)) {
11102 // Shuffling low element of v1 into undef, just return v1.
11105 // If V2 is a splat, the mask may be malformed such as <4,3,3,3>, which
11106 // the instruction selector will not match, so get a canonical MOVL with
11107 // swapped operands to undo the commute.
11108 return getMOVL(DAG, dl, VT, V2, V1);
11111 if (isUNPCKLMask(M, VT, HasInt256))
11112 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG);
11114 if (isUNPCKHMask(M, VT, HasInt256))
11115 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG);
11118 // Normalize mask so all entries that point to V2 points to its first
11119 // element then try to match unpck{h|l} again. If match, return a
11120 // new vector_shuffle with the corrected mask.p
11121 SmallVector<int, 8> NewMask(M.begin(), M.end());
11122 NormalizeMask(NewMask, NumElems);
11123 if (isUNPCKLMask(NewMask, VT, HasInt256, true))
11124 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG);
11125 if (isUNPCKHMask(NewMask, VT, HasInt256, true))
11126 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG);
11130 // Commute is back and try unpck* again.
11131 // FIXME: this seems wrong.
11132 CommuteVectorShuffleMask(M, NumElems);
11134 std::swap(V1IsSplat, V2IsSplat);
11136 if (isUNPCKLMask(M, VT, HasInt256))
11137 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG);
11139 if (isUNPCKHMask(M, VT, HasInt256))
11140 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG);
11143 // Normalize the node to match x86 shuffle ops if needed
11144 if (!V2IsUndef && (isSHUFPMask(M, VT, /* Commuted */ true)))
11145 return DAG.getCommutedVectorShuffle(*SVOp);
11147 // The checks below are all present in isShuffleMaskLegal, but they are
11148 // inlined here right now to enable us to directly emit target specific
11149 // nodes, and remove one by one until they don't return Op anymore.
11151 if (ShuffleVectorSDNode::isSplatMask(&M[0], VT) &&
11152 SVOp->getSplatIndex() == 0 && V2IsUndef) {
11153 if (VT == MVT::v2f64 || VT == MVT::v2i64)
11154 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
11157 if (isPSHUFHWMask(M, VT, HasInt256))
11158 return getTargetShuffleNode(X86ISD::PSHUFHW, dl, VT, V1,
11159 getShufflePSHUFHWImmediate(SVOp),
11162 if (isPSHUFLWMask(M, VT, HasInt256))
11163 return getTargetShuffleNode(X86ISD::PSHUFLW, dl, VT, V1,
11164 getShufflePSHUFLWImmediate(SVOp),
11167 unsigned MaskValue;
11168 if (isBlendMask(M, VT, Subtarget->hasSSE41(), Subtarget->hasInt256(),
11170 return LowerVECTOR_SHUFFLEtoBlend(SVOp, MaskValue, Subtarget, DAG);
11172 if (isSHUFPMask(M, VT))
11173 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V1, V2,
11174 getShuffleSHUFImmediate(SVOp), DAG);
11176 if (isUNPCKL_v_undef_Mask(M, VT, HasInt256))
11177 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
11178 if (isUNPCKH_v_undef_Mask(M, VT, HasInt256))
11179 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
11181 //===--------------------------------------------------------------------===//
11182 // Generate target specific nodes for 128 or 256-bit shuffles only
11183 // supported in the AVX instruction set.
11186 // Handle VMOVDDUPY permutations
11187 if (V2IsUndef && isMOVDDUPYMask(M, VT, HasFp256))
11188 return getTargetShuffleNode(X86ISD::MOVDDUP, dl, VT, V1, DAG);
11190 // Handle VPERMILPS/D* permutations
11191 if (isVPERMILPMask(M, VT)) {
11192 if ((HasInt256 && VT == MVT::v8i32) || VT == MVT::v16i32)
11193 return getTargetShuffleNode(X86ISD::PSHUFD, dl, VT, V1,
11194 getShuffleSHUFImmediate(SVOp), DAG);
11195 return getTargetShuffleNode(X86ISD::VPERMILPI, dl, VT, V1,
11196 getShuffleSHUFImmediate(SVOp), DAG);
11200 if (VT.is512BitVector() && isINSERT64x4Mask(M, VT, &Idx))
11201 return Insert256BitVector(V1, Extract256BitVector(V2, 0, DAG, dl),
11202 Idx*(NumElems/2), DAG, dl);
11204 // Handle VPERM2F128/VPERM2I128 permutations
11205 if (isVPERM2X128Mask(M, VT, HasFp256))
11206 return getTargetShuffleNode(X86ISD::VPERM2X128, dl, VT, V1,
11207 V2, getShuffleVPERM2X128Immediate(SVOp), DAG);
11209 if (Subtarget->hasSSE41() && isINSERTPSMask(M, VT))
11210 return getINSERTPS(SVOp, dl, DAG);
11213 if (V2IsUndef && HasInt256 && isPermImmMask(M, VT, Imm8))
11214 return getTargetShuffleNode(X86ISD::VPERMI, dl, VT, V1, Imm8, DAG);
11216 if ((V2IsUndef && HasInt256 && VT.is256BitVector() && NumElems == 8) ||
11217 VT.is512BitVector()) {
11218 MVT MaskEltVT = MVT::getIntegerVT(VT.getVectorElementType().getSizeInBits());
11219 MVT MaskVectorVT = MVT::getVectorVT(MaskEltVT, NumElems);
11220 SmallVector<SDValue, 16> permclMask;
11221 for (unsigned i = 0; i != NumElems; ++i) {
11222 permclMask.push_back(DAG.getConstant((M[i]>=0) ? M[i] : 0, MaskEltVT));
11225 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, MaskVectorVT, permclMask);
11227 // Bitcast is for VPERMPS since mask is v8i32 but node takes v8f32
11228 return DAG.getNode(X86ISD::VPERMV, dl, VT,
11229 DAG.getNode(ISD::BITCAST, dl, VT, Mask), V1);
11230 return DAG.getNode(X86ISD::VPERMV3, dl, VT, V1,
11231 DAG.getNode(ISD::BITCAST, dl, VT, Mask), V2);
11234 //===--------------------------------------------------------------------===//
11235 // Since no target specific shuffle was selected for this generic one,
11236 // lower it into other known shuffles. FIXME: this isn't true yet, but
11237 // this is the plan.
11240 // Handle v8i16 specifically since SSE can do byte extraction and insertion.
11241 if (VT == MVT::v8i16) {
11242 SDValue NewOp = LowerVECTOR_SHUFFLEv8i16(Op, Subtarget, DAG);
11243 if (NewOp.getNode())
11247 if (VT == MVT::v16i16 && Subtarget->hasInt256()) {
11248 SDValue NewOp = LowerVECTOR_SHUFFLEv16i16(Op, DAG);
11249 if (NewOp.getNode())
11253 if (VT == MVT::v16i8) {
11254 SDValue NewOp = LowerVECTOR_SHUFFLEv16i8(SVOp, Subtarget, DAG);
11255 if (NewOp.getNode())
11259 if (VT == MVT::v32i8) {
11260 SDValue NewOp = LowerVECTOR_SHUFFLEv32i8(SVOp, Subtarget, DAG);
11261 if (NewOp.getNode())
11265 // Handle all 128-bit wide vectors with 4 elements, and match them with
11266 // several different shuffle types.
11267 if (NumElems == 4 && VT.is128BitVector())
11268 return LowerVECTOR_SHUFFLE_128v4(SVOp, DAG);
11270 // Handle general 256-bit shuffles
11271 if (VT.is256BitVector())
11272 return LowerVECTOR_SHUFFLE_256(SVOp, DAG);
11277 // This function assumes its argument is a BUILD_VECTOR of constants or
11278 // undef SDNodes. i.e: ISD::isBuildVectorOfConstantSDNodes(BuildVector) is
11280 static bool BUILD_VECTORtoBlendMask(BuildVectorSDNode *BuildVector,
11281 unsigned &MaskValue) {
11283 unsigned NumElems = BuildVector->getNumOperands();
11284 // There are 2 lanes if (NumElems > 8), and 1 lane otherwise.
11285 unsigned NumLanes = (NumElems - 1) / 8 + 1;
11286 unsigned NumElemsInLane = NumElems / NumLanes;
11288 // Blend for v16i16 should be symetric for the both lanes.
11289 for (unsigned i = 0; i < NumElemsInLane; ++i) {
11290 SDValue EltCond = BuildVector->getOperand(i);
11291 SDValue SndLaneEltCond =
11292 (NumLanes == 2) ? BuildVector->getOperand(i + NumElemsInLane) : EltCond;
11294 int Lane1Cond = -1, Lane2Cond = -1;
11295 if (isa<ConstantSDNode>(EltCond))
11296 Lane1Cond = !isZero(EltCond);
11297 if (isa<ConstantSDNode>(SndLaneEltCond))
11298 Lane2Cond = !isZero(SndLaneEltCond);
11300 if (Lane1Cond == Lane2Cond || Lane2Cond < 0)
11301 // Lane1Cond != 0, means we want the first argument.
11302 // Lane1Cond == 0, means we want the second argument.
11303 // The encoding of this argument is 0 for the first argument, 1
11304 // for the second. Therefore, invert the condition.
11305 MaskValue |= !Lane1Cond << i;
11306 else if (Lane1Cond < 0)
11307 MaskValue |= !Lane2Cond << i;
11314 // Try to lower a vselect node into a simple blend instruction.
11315 static SDValue LowerVSELECTtoBlend(SDValue Op, const X86Subtarget *Subtarget,
11316 SelectionDAG &DAG) {
11317 SDValue Cond = Op.getOperand(0);
11318 SDValue LHS = Op.getOperand(1);
11319 SDValue RHS = Op.getOperand(2);
11321 MVT VT = Op.getSimpleValueType();
11322 MVT EltVT = VT.getVectorElementType();
11323 unsigned NumElems = VT.getVectorNumElements();
11325 // There is no blend with immediate in AVX-512.
11326 if (VT.is512BitVector())
11329 if (!Subtarget->hasSSE41() || EltVT == MVT::i8)
11331 if (!Subtarget->hasInt256() && VT == MVT::v16i16)
11334 if (!ISD::isBuildVectorOfConstantSDNodes(Cond.getNode()))
11337 // Check the mask for BLEND and build the value.
11338 unsigned MaskValue = 0;
11339 if (!BUILD_VECTORtoBlendMask(cast<BuildVectorSDNode>(Cond), MaskValue))
11342 // Convert i32 vectors to floating point if it is not AVX2.
11343 // AVX2 introduced VPBLENDD instruction for 128 and 256-bit vectors.
11345 if (EltVT == MVT::i64 || (EltVT == MVT::i32 && !Subtarget->hasInt256())) {
11346 BlendVT = MVT::getVectorVT(MVT::getFloatingPointVT(EltVT.getSizeInBits()),
11348 LHS = DAG.getNode(ISD::BITCAST, dl, VT, LHS);
11349 RHS = DAG.getNode(ISD::BITCAST, dl, VT, RHS);
11352 SDValue Ret = DAG.getNode(X86ISD::BLENDI, dl, BlendVT, LHS, RHS,
11353 DAG.getConstant(MaskValue, MVT::i32));
11354 return DAG.getNode(ISD::BITCAST, dl, VT, Ret);
11357 SDValue X86TargetLowering::LowerVSELECT(SDValue Op, SelectionDAG &DAG) const {
11358 // A vselect where all conditions and data are constants can be optimized into
11359 // a single vector load by SelectionDAGLegalize::ExpandBUILD_VECTOR().
11360 if (ISD::isBuildVectorOfConstantSDNodes(Op.getOperand(0).getNode()) &&
11361 ISD::isBuildVectorOfConstantSDNodes(Op.getOperand(1).getNode()) &&
11362 ISD::isBuildVectorOfConstantSDNodes(Op.getOperand(2).getNode()))
11365 SDValue BlendOp = LowerVSELECTtoBlend(Op, Subtarget, DAG);
11366 if (BlendOp.getNode())
11369 // Some types for vselect were previously set to Expand, not Legal or
11370 // Custom. Return an empty SDValue so we fall-through to Expand, after
11371 // the Custom lowering phase.
11372 MVT VT = Op.getSimpleValueType();
11373 switch (VT.SimpleTy) {
11378 if (Subtarget->hasBWI() && Subtarget->hasVLX())
11383 // We couldn't create a "Blend with immediate" node.
11384 // This node should still be legal, but we'll have to emit a blendv*
11389 static SDValue LowerEXTRACT_VECTOR_ELT_SSE4(SDValue Op, SelectionDAG &DAG) {
11390 MVT VT = Op.getSimpleValueType();
11393 if (!Op.getOperand(0).getSimpleValueType().is128BitVector())
11396 if (VT.getSizeInBits() == 8) {
11397 SDValue Extract = DAG.getNode(X86ISD::PEXTRB, dl, MVT::i32,
11398 Op.getOperand(0), Op.getOperand(1));
11399 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
11400 DAG.getValueType(VT));
11401 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
11404 if (VT.getSizeInBits() == 16) {
11405 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
11406 // If Idx is 0, it's cheaper to do a move instead of a pextrw.
11408 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
11409 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
11410 DAG.getNode(ISD::BITCAST, dl,
11413 Op.getOperand(1)));
11414 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, MVT::i32,
11415 Op.getOperand(0), Op.getOperand(1));
11416 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
11417 DAG.getValueType(VT));
11418 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
11421 if (VT == MVT::f32) {
11422 // EXTRACTPS outputs to a GPR32 register which will require a movd to copy
11423 // the result back to FR32 register. It's only worth matching if the
11424 // result has a single use which is a store or a bitcast to i32. And in
11425 // the case of a store, it's not worth it if the index is a constant 0,
11426 // because a MOVSSmr can be used instead, which is smaller and faster.
11427 if (!Op.hasOneUse())
11429 SDNode *User = *Op.getNode()->use_begin();
11430 if ((User->getOpcode() != ISD::STORE ||
11431 (isa<ConstantSDNode>(Op.getOperand(1)) &&
11432 cast<ConstantSDNode>(Op.getOperand(1))->isNullValue())) &&
11433 (User->getOpcode() != ISD::BITCAST ||
11434 User->getValueType(0) != MVT::i32))
11436 SDValue Extract = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
11437 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32,
11440 return DAG.getNode(ISD::BITCAST, dl, MVT::f32, Extract);
11443 if (VT == MVT::i32 || VT == MVT::i64) {
11444 // ExtractPS/pextrq works with constant index.
11445 if (isa<ConstantSDNode>(Op.getOperand(1)))
11451 /// Extract one bit from mask vector, like v16i1 or v8i1.
11452 /// AVX-512 feature.
11454 X86TargetLowering::ExtractBitFromMaskVector(SDValue Op, SelectionDAG &DAG) const {
11455 SDValue Vec = Op.getOperand(0);
11457 MVT VecVT = Vec.getSimpleValueType();
11458 SDValue Idx = Op.getOperand(1);
11459 MVT EltVT = Op.getSimpleValueType();
11461 assert((EltVT == MVT::i1) && "Unexpected operands in ExtractBitFromMaskVector");
11463 // variable index can't be handled in mask registers,
11464 // extend vector to VR512
11465 if (!isa<ConstantSDNode>(Idx)) {
11466 MVT ExtVT = (VecVT == MVT::v8i1 ? MVT::v8i64 : MVT::v16i32);
11467 SDValue Ext = DAG.getNode(ISD::ZERO_EXTEND, dl, ExtVT, Vec);
11468 SDValue Elt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
11469 ExtVT.getVectorElementType(), Ext, Idx);
11470 return DAG.getNode(ISD::TRUNCATE, dl, EltVT, Elt);
11473 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
11474 const TargetRegisterClass* rc = getRegClassFor(VecVT);
11475 unsigned MaxSift = rc->getSize()*8 - 1;
11476 Vec = DAG.getNode(X86ISD::VSHLI, dl, VecVT, Vec,
11477 DAG.getConstant(MaxSift - IdxVal, MVT::i8));
11478 Vec = DAG.getNode(X86ISD::VSRLI, dl, VecVT, Vec,
11479 DAG.getConstant(MaxSift, MVT::i8));
11480 return DAG.getNode(X86ISD::VEXTRACT, dl, MVT::i1, Vec,
11481 DAG.getIntPtrConstant(0));
11485 X86TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op,
11486 SelectionDAG &DAG) const {
11488 SDValue Vec = Op.getOperand(0);
11489 MVT VecVT = Vec.getSimpleValueType();
11490 SDValue Idx = Op.getOperand(1);
11492 if (Op.getSimpleValueType() == MVT::i1)
11493 return ExtractBitFromMaskVector(Op, DAG);
11495 if (!isa<ConstantSDNode>(Idx)) {
11496 if (VecVT.is512BitVector() ||
11497 (VecVT.is256BitVector() && Subtarget->hasInt256() &&
11498 VecVT.getVectorElementType().getSizeInBits() == 32)) {
11501 MVT::getIntegerVT(VecVT.getVectorElementType().getSizeInBits());
11502 MVT MaskVT = MVT::getVectorVT(MaskEltVT, VecVT.getSizeInBits() /
11503 MaskEltVT.getSizeInBits());
11505 Idx = DAG.getZExtOrTrunc(Idx, dl, MaskEltVT);
11506 SDValue Mask = DAG.getNode(X86ISD::VINSERT, dl, MaskVT,
11507 getZeroVector(MaskVT, Subtarget, DAG, dl),
11508 Idx, DAG.getConstant(0, getPointerTy()));
11509 SDValue Perm = DAG.getNode(X86ISD::VPERMV, dl, VecVT, Mask, Vec);
11510 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, Op.getValueType(),
11511 Perm, DAG.getConstant(0, getPointerTy()));
11516 // If this is a 256-bit vector result, first extract the 128-bit vector and
11517 // then extract the element from the 128-bit vector.
11518 if (VecVT.is256BitVector() || VecVT.is512BitVector()) {
11520 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
11521 // Get the 128-bit vector.
11522 Vec = Extract128BitVector(Vec, IdxVal, DAG, dl);
11523 MVT EltVT = VecVT.getVectorElementType();
11525 unsigned ElemsPerChunk = 128 / EltVT.getSizeInBits();
11527 //if (IdxVal >= NumElems/2)
11528 // IdxVal -= NumElems/2;
11529 IdxVal -= (IdxVal/ElemsPerChunk)*ElemsPerChunk;
11530 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, Op.getValueType(), Vec,
11531 DAG.getConstant(IdxVal, MVT::i32));
11534 assert(VecVT.is128BitVector() && "Unexpected vector length");
11536 if (Subtarget->hasSSE41()) {
11537 SDValue Res = LowerEXTRACT_VECTOR_ELT_SSE4(Op, DAG);
11542 MVT VT = Op.getSimpleValueType();
11543 // TODO: handle v16i8.
11544 if (VT.getSizeInBits() == 16) {
11545 SDValue Vec = Op.getOperand(0);
11546 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
11548 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
11549 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
11550 DAG.getNode(ISD::BITCAST, dl,
11552 Op.getOperand(1)));
11553 // Transform it so it match pextrw which produces a 32-bit result.
11554 MVT EltVT = MVT::i32;
11555 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, EltVT,
11556 Op.getOperand(0), Op.getOperand(1));
11557 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, EltVT, Extract,
11558 DAG.getValueType(VT));
11559 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
11562 if (VT.getSizeInBits() == 32) {
11563 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
11567 // SHUFPS the element to the lowest double word, then movss.
11568 int Mask[4] = { static_cast<int>(Idx), -1, -1, -1 };
11569 MVT VVT = Op.getOperand(0).getSimpleValueType();
11570 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
11571 DAG.getUNDEF(VVT), Mask);
11572 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
11573 DAG.getIntPtrConstant(0));
11576 if (VT.getSizeInBits() == 64) {
11577 // FIXME: .td only matches this for <2 x f64>, not <2 x i64> on 32b
11578 // FIXME: seems like this should be unnecessary if mov{h,l}pd were taught
11579 // to match extract_elt for f64.
11580 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
11584 // UNPCKHPD the element to the lowest double word, then movsd.
11585 // Note if the lower 64 bits of the result of the UNPCKHPD is then stored
11586 // to a f64mem, the whole operation is folded into a single MOVHPDmr.
11587 int Mask[2] = { 1, -1 };
11588 MVT VVT = Op.getOperand(0).getSimpleValueType();
11589 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
11590 DAG.getUNDEF(VVT), Mask);
11591 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
11592 DAG.getIntPtrConstant(0));
11598 /// Insert one bit to mask vector, like v16i1 or v8i1.
11599 /// AVX-512 feature.
11601 X86TargetLowering::InsertBitToMaskVector(SDValue Op, SelectionDAG &DAG) const {
11603 SDValue Vec = Op.getOperand(0);
11604 SDValue Elt = Op.getOperand(1);
11605 SDValue Idx = Op.getOperand(2);
11606 MVT VecVT = Vec.getSimpleValueType();
11608 if (!isa<ConstantSDNode>(Idx)) {
11609 // Non constant index. Extend source and destination,
11610 // insert element and then truncate the result.
11611 MVT ExtVecVT = (VecVT == MVT::v8i1 ? MVT::v8i64 : MVT::v16i32);
11612 MVT ExtEltVT = (VecVT == MVT::v8i1 ? MVT::i64 : MVT::i32);
11613 SDValue ExtOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, ExtVecVT,
11614 DAG.getNode(ISD::ZERO_EXTEND, dl, ExtVecVT, Vec),
11615 DAG.getNode(ISD::ZERO_EXTEND, dl, ExtEltVT, Elt), Idx);
11616 return DAG.getNode(ISD::TRUNCATE, dl, VecVT, ExtOp);
11619 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
11620 SDValue EltInVec = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Elt);
11621 if (Vec.getOpcode() == ISD::UNDEF)
11622 return DAG.getNode(X86ISD::VSHLI, dl, VecVT, EltInVec,
11623 DAG.getConstant(IdxVal, MVT::i8));
11624 const TargetRegisterClass* rc = getRegClassFor(VecVT);
11625 unsigned MaxSift = rc->getSize()*8 - 1;
11626 EltInVec = DAG.getNode(X86ISD::VSHLI, dl, VecVT, EltInVec,
11627 DAG.getConstant(MaxSift, MVT::i8));
11628 EltInVec = DAG.getNode(X86ISD::VSRLI, dl, VecVT, EltInVec,
11629 DAG.getConstant(MaxSift - IdxVal, MVT::i8));
11630 return DAG.getNode(ISD::OR, dl, VecVT, Vec, EltInVec);
11633 SDValue X86TargetLowering::LowerINSERT_VECTOR_ELT(SDValue Op,
11634 SelectionDAG &DAG) const {
11635 MVT VT = Op.getSimpleValueType();
11636 MVT EltVT = VT.getVectorElementType();
11638 if (EltVT == MVT::i1)
11639 return InsertBitToMaskVector(Op, DAG);
11642 SDValue N0 = Op.getOperand(0);
11643 SDValue N1 = Op.getOperand(1);
11644 SDValue N2 = Op.getOperand(2);
11645 if (!isa<ConstantSDNode>(N2))
11647 auto *N2C = cast<ConstantSDNode>(N2);
11648 unsigned IdxVal = N2C->getZExtValue();
11650 // If the vector is wider than 128 bits, extract the 128-bit subvector, insert
11651 // into that, and then insert the subvector back into the result.
11652 if (VT.is256BitVector() || VT.is512BitVector()) {
11653 // Get the desired 128-bit vector half.
11654 SDValue V = Extract128BitVector(N0, IdxVal, DAG, dl);
11656 // Insert the element into the desired half.
11657 unsigned NumEltsIn128 = 128 / EltVT.getSizeInBits();
11658 unsigned IdxIn128 = IdxVal - (IdxVal / NumEltsIn128) * NumEltsIn128;
11660 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, V.getValueType(), V, N1,
11661 DAG.getConstant(IdxIn128, MVT::i32));
11663 // Insert the changed part back to the 256-bit vector
11664 return Insert128BitVector(N0, V, IdxVal, DAG, dl);
11666 assert(VT.is128BitVector() && "Only 128-bit vector types should be left!");
11668 if (Subtarget->hasSSE41()) {
11669 if (EltVT.getSizeInBits() == 8 || EltVT.getSizeInBits() == 16) {
11671 if (VT == MVT::v8i16) {
11672 Opc = X86ISD::PINSRW;
11674 assert(VT == MVT::v16i8);
11675 Opc = X86ISD::PINSRB;
11678 // Transform it so it match pinsr{b,w} which expects a GR32 as its second
11680 if (N1.getValueType() != MVT::i32)
11681 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
11682 if (N2.getValueType() != MVT::i32)
11683 N2 = DAG.getIntPtrConstant(IdxVal);
11684 return DAG.getNode(Opc, dl, VT, N0, N1, N2);
11687 if (EltVT == MVT::f32) {
11688 // Bits [7:6] of the constant are the source select. This will always be
11689 // zero here. The DAG Combiner may combine an extract_elt index into
11691 // bits. For example (insert (extract, 3), 2) could be matched by
11693 // the '3' into bits [7:6] of X86ISD::INSERTPS.
11694 // Bits [5:4] of the constant are the destination select. This is the
11695 // value of the incoming immediate.
11696 // Bits [3:0] of the constant are the zero mask. The DAG Combiner may
11697 // combine either bitwise AND or insert of float 0.0 to set these bits.
11698 N2 = DAG.getIntPtrConstant(IdxVal << 4);
11699 // Create this as a scalar to vector..
11700 N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4f32, N1);
11701 return DAG.getNode(X86ISD::INSERTPS, dl, VT, N0, N1, N2);
11704 if (EltVT == MVT::i32 || EltVT == MVT::i64) {
11705 // PINSR* works with constant index.
11710 if (EltVT == MVT::i8)
11713 if (EltVT.getSizeInBits() == 16) {
11714 // Transform it so it match pinsrw which expects a 16-bit value in a GR32
11715 // as its second argument.
11716 if (N1.getValueType() != MVT::i32)
11717 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
11718 if (N2.getValueType() != MVT::i32)
11719 N2 = DAG.getIntPtrConstant(IdxVal);
11720 return DAG.getNode(X86ISD::PINSRW, dl, VT, N0, N1, N2);
11725 static SDValue LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) {
11727 MVT OpVT = Op.getSimpleValueType();
11729 // If this is a 256-bit vector result, first insert into a 128-bit
11730 // vector and then insert into the 256-bit vector.
11731 if (!OpVT.is128BitVector()) {
11732 // Insert into a 128-bit vector.
11733 unsigned SizeFactor = OpVT.getSizeInBits()/128;
11734 MVT VT128 = MVT::getVectorVT(OpVT.getVectorElementType(),
11735 OpVT.getVectorNumElements() / SizeFactor);
11737 Op = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT128, Op.getOperand(0));
11739 // Insert the 128-bit vector.
11740 return Insert128BitVector(DAG.getUNDEF(OpVT), Op, 0, DAG, dl);
11743 if (OpVT == MVT::v1i64 &&
11744 Op.getOperand(0).getValueType() == MVT::i64)
11745 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v1i64, Op.getOperand(0));
11747 SDValue AnyExt = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, Op.getOperand(0));
11748 assert(OpVT.is128BitVector() && "Expected an SSE type!");
11749 return DAG.getNode(ISD::BITCAST, dl, OpVT,
11750 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,AnyExt));
11753 // Lower a node with an EXTRACT_SUBVECTOR opcode. This may result in
11754 // a simple subregister reference or explicit instructions to grab
11755 // upper bits of a vector.
11756 static SDValue LowerEXTRACT_SUBVECTOR(SDValue Op, const X86Subtarget *Subtarget,
11757 SelectionDAG &DAG) {
11759 SDValue In = Op.getOperand(0);
11760 SDValue Idx = Op.getOperand(1);
11761 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
11762 MVT ResVT = Op.getSimpleValueType();
11763 MVT InVT = In.getSimpleValueType();
11765 if (Subtarget->hasFp256()) {
11766 if (ResVT.is128BitVector() &&
11767 (InVT.is256BitVector() || InVT.is512BitVector()) &&
11768 isa<ConstantSDNode>(Idx)) {
11769 return Extract128BitVector(In, IdxVal, DAG, dl);
11771 if (ResVT.is256BitVector() && InVT.is512BitVector() &&
11772 isa<ConstantSDNode>(Idx)) {
11773 return Extract256BitVector(In, IdxVal, DAG, dl);
11779 // Lower a node with an INSERT_SUBVECTOR opcode. This may result in a
11780 // simple superregister reference or explicit instructions to insert
11781 // the upper bits of a vector.
11782 static SDValue LowerINSERT_SUBVECTOR(SDValue Op, const X86Subtarget *Subtarget,
11783 SelectionDAG &DAG) {
11784 if (Subtarget->hasFp256()) {
11785 SDLoc dl(Op.getNode());
11786 SDValue Vec = Op.getNode()->getOperand(0);
11787 SDValue SubVec = Op.getNode()->getOperand(1);
11788 SDValue Idx = Op.getNode()->getOperand(2);
11790 if ((Op.getNode()->getSimpleValueType(0).is256BitVector() ||
11791 Op.getNode()->getSimpleValueType(0).is512BitVector()) &&
11792 SubVec.getNode()->getSimpleValueType(0).is128BitVector() &&
11793 isa<ConstantSDNode>(Idx)) {
11794 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
11795 return Insert128BitVector(Vec, SubVec, IdxVal, DAG, dl);
11798 if (Op.getNode()->getSimpleValueType(0).is512BitVector() &&
11799 SubVec.getNode()->getSimpleValueType(0).is256BitVector() &&
11800 isa<ConstantSDNode>(Idx)) {
11801 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
11802 return Insert256BitVector(Vec, SubVec, IdxVal, DAG, dl);
11808 // ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as
11809 // their target countpart wrapped in the X86ISD::Wrapper node. Suppose N is
11810 // one of the above mentioned nodes. It has to be wrapped because otherwise
11811 // Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only
11812 // be used to form addressing mode. These wrapped nodes will be selected
11815 X86TargetLowering::LowerConstantPool(SDValue Op, SelectionDAG &DAG) const {
11816 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
11818 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
11819 // global base reg.
11820 unsigned char OpFlag = 0;
11821 unsigned WrapperKind = X86ISD::Wrapper;
11822 CodeModel::Model M = DAG.getTarget().getCodeModel();
11824 if (Subtarget->isPICStyleRIPRel() &&
11825 (M == CodeModel::Small || M == CodeModel::Kernel))
11826 WrapperKind = X86ISD::WrapperRIP;
11827 else if (Subtarget->isPICStyleGOT())
11828 OpFlag = X86II::MO_GOTOFF;
11829 else if (Subtarget->isPICStyleStubPIC())
11830 OpFlag = X86II::MO_PIC_BASE_OFFSET;
11832 SDValue Result = DAG.getTargetConstantPool(CP->getConstVal(), getPointerTy(),
11833 CP->getAlignment(),
11834 CP->getOffset(), OpFlag);
11836 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
11837 // With PIC, the address is actually $g + Offset.
11839 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
11840 DAG.getNode(X86ISD::GlobalBaseReg,
11841 SDLoc(), getPointerTy()),
11848 SDValue X86TargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) const {
11849 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
11851 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
11852 // global base reg.
11853 unsigned char OpFlag = 0;
11854 unsigned WrapperKind = X86ISD::Wrapper;
11855 CodeModel::Model M = DAG.getTarget().getCodeModel();
11857 if (Subtarget->isPICStyleRIPRel() &&
11858 (M == CodeModel::Small || M == CodeModel::Kernel))
11859 WrapperKind = X86ISD::WrapperRIP;
11860 else if (Subtarget->isPICStyleGOT())
11861 OpFlag = X86II::MO_GOTOFF;
11862 else if (Subtarget->isPICStyleStubPIC())
11863 OpFlag = X86II::MO_PIC_BASE_OFFSET;
11865 SDValue Result = DAG.getTargetJumpTable(JT->getIndex(), getPointerTy(),
11868 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
11870 // With PIC, the address is actually $g + Offset.
11872 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
11873 DAG.getNode(X86ISD::GlobalBaseReg,
11874 SDLoc(), getPointerTy()),
11881 X86TargetLowering::LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) const {
11882 const char *Sym = cast<ExternalSymbolSDNode>(Op)->getSymbol();
11884 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
11885 // global base reg.
11886 unsigned char OpFlag = 0;
11887 unsigned WrapperKind = X86ISD::Wrapper;
11888 CodeModel::Model M = DAG.getTarget().getCodeModel();
11890 if (Subtarget->isPICStyleRIPRel() &&
11891 (M == CodeModel::Small || M == CodeModel::Kernel)) {
11892 if (Subtarget->isTargetDarwin() || Subtarget->isTargetELF())
11893 OpFlag = X86II::MO_GOTPCREL;
11894 WrapperKind = X86ISD::WrapperRIP;
11895 } else if (Subtarget->isPICStyleGOT()) {
11896 OpFlag = X86II::MO_GOT;
11897 } else if (Subtarget->isPICStyleStubPIC()) {
11898 OpFlag = X86II::MO_DARWIN_NONLAZY_PIC_BASE;
11899 } else if (Subtarget->isPICStyleStubNoDynamic()) {
11900 OpFlag = X86II::MO_DARWIN_NONLAZY;
11903 SDValue Result = DAG.getTargetExternalSymbol(Sym, getPointerTy(), OpFlag);
11906 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
11908 // With PIC, the address is actually $g + Offset.
11909 if (DAG.getTarget().getRelocationModel() == Reloc::PIC_ &&
11910 !Subtarget->is64Bit()) {
11911 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
11912 DAG.getNode(X86ISD::GlobalBaseReg,
11913 SDLoc(), getPointerTy()),
11917 // For symbols that require a load from a stub to get the address, emit the
11919 if (isGlobalStubReference(OpFlag))
11920 Result = DAG.getLoad(getPointerTy(), DL, DAG.getEntryNode(), Result,
11921 MachinePointerInfo::getGOT(), false, false, false, 0);
11927 X86TargetLowering::LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const {
11928 // Create the TargetBlockAddressAddress node.
11929 unsigned char OpFlags =
11930 Subtarget->ClassifyBlockAddressReference();
11931 CodeModel::Model M = DAG.getTarget().getCodeModel();
11932 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
11933 int64_t Offset = cast<BlockAddressSDNode>(Op)->getOffset();
11935 SDValue Result = DAG.getTargetBlockAddress(BA, getPointerTy(), Offset,
11938 if (Subtarget->isPICStyleRIPRel() &&
11939 (M == CodeModel::Small || M == CodeModel::Kernel))
11940 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
11942 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
11944 // With PIC, the address is actually $g + Offset.
11945 if (isGlobalRelativeToPICBase(OpFlags)) {
11946 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
11947 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
11955 X86TargetLowering::LowerGlobalAddress(const GlobalValue *GV, SDLoc dl,
11956 int64_t Offset, SelectionDAG &DAG) const {
11957 // Create the TargetGlobalAddress node, folding in the constant
11958 // offset if it is legal.
11959 unsigned char OpFlags =
11960 Subtarget->ClassifyGlobalReference(GV, DAG.getTarget());
11961 CodeModel::Model M = DAG.getTarget().getCodeModel();
11963 if (OpFlags == X86II::MO_NO_FLAG &&
11964 X86::isOffsetSuitableForCodeModel(Offset, M)) {
11965 // A direct static reference to a global.
11966 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), Offset);
11969 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), 0, OpFlags);
11972 if (Subtarget->isPICStyleRIPRel() &&
11973 (M == CodeModel::Small || M == CodeModel::Kernel))
11974 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
11976 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
11978 // With PIC, the address is actually $g + Offset.
11979 if (isGlobalRelativeToPICBase(OpFlags)) {
11980 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
11981 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
11985 // For globals that require a load from a stub to get the address, emit the
11987 if (isGlobalStubReference(OpFlags))
11988 Result = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Result,
11989 MachinePointerInfo::getGOT(), false, false, false, 0);
11991 // If there was a non-zero offset that we didn't fold, create an explicit
11992 // addition for it.
11994 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(), Result,
11995 DAG.getConstant(Offset, getPointerTy()));
12001 X86TargetLowering::LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const {
12002 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
12003 int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset();
12004 return LowerGlobalAddress(GV, SDLoc(Op), Offset, DAG);
12008 GetTLSADDR(SelectionDAG &DAG, SDValue Chain, GlobalAddressSDNode *GA,
12009 SDValue *InFlag, const EVT PtrVT, unsigned ReturnReg,
12010 unsigned char OperandFlags, bool LocalDynamic = false) {
12011 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
12012 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
12014 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
12015 GA->getValueType(0),
12019 X86ISD::NodeType CallType = LocalDynamic ? X86ISD::TLSBASEADDR
12023 SDValue Ops[] = { Chain, TGA, *InFlag };
12024 Chain = DAG.getNode(CallType, dl, NodeTys, Ops);
12026 SDValue Ops[] = { Chain, TGA };
12027 Chain = DAG.getNode(CallType, dl, NodeTys, Ops);
12030 // TLSADDR will be codegen'ed as call. Inform MFI that function has calls.
12031 MFI->setAdjustsStack(true);
12033 SDValue Flag = Chain.getValue(1);
12034 return DAG.getCopyFromReg(Chain, dl, ReturnReg, PtrVT, Flag);
12037 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 32 bit
12039 LowerToTLSGeneralDynamicModel32(GlobalAddressSDNode *GA, SelectionDAG &DAG,
12042 SDLoc dl(GA); // ? function entry point might be better
12043 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
12044 DAG.getNode(X86ISD::GlobalBaseReg,
12045 SDLoc(), PtrVT), InFlag);
12046 InFlag = Chain.getValue(1);
12048 return GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX, X86II::MO_TLSGD);
12051 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 64 bit
12053 LowerToTLSGeneralDynamicModel64(GlobalAddressSDNode *GA, SelectionDAG &DAG,
12055 return GetTLSADDR(DAG, DAG.getEntryNode(), GA, nullptr, PtrVT,
12056 X86::RAX, X86II::MO_TLSGD);
12059 static SDValue LowerToTLSLocalDynamicModel(GlobalAddressSDNode *GA,
12065 // Get the start address of the TLS block for this module.
12066 X86MachineFunctionInfo* MFI = DAG.getMachineFunction()
12067 .getInfo<X86MachineFunctionInfo>();
12068 MFI->incNumLocalDynamicTLSAccesses();
12072 Base = GetTLSADDR(DAG, DAG.getEntryNode(), GA, nullptr, PtrVT, X86::RAX,
12073 X86II::MO_TLSLD, /*LocalDynamic=*/true);
12076 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
12077 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT), InFlag);
12078 InFlag = Chain.getValue(1);
12079 Base = GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX,
12080 X86II::MO_TLSLDM, /*LocalDynamic=*/true);
12083 // Note: the CleanupLocalDynamicTLSPass will remove redundant computations
12087 unsigned char OperandFlags = X86II::MO_DTPOFF;
12088 unsigned WrapperKind = X86ISD::Wrapper;
12089 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
12090 GA->getValueType(0),
12091 GA->getOffset(), OperandFlags);
12092 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
12094 // Add x@dtpoff with the base.
12095 return DAG.getNode(ISD::ADD, dl, PtrVT, Offset, Base);
12098 // Lower ISD::GlobalTLSAddress using the "initial exec" or "local exec" model.
12099 static SDValue LowerToTLSExecModel(GlobalAddressSDNode *GA, SelectionDAG &DAG,
12100 const EVT PtrVT, TLSModel::Model model,
12101 bool is64Bit, bool isPIC) {
12104 // Get the Thread Pointer, which is %gs:0 (32-bit) or %fs:0 (64-bit).
12105 Value *Ptr = Constant::getNullValue(Type::getInt8PtrTy(*DAG.getContext(),
12106 is64Bit ? 257 : 256));
12108 SDValue ThreadPointer =
12109 DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), DAG.getIntPtrConstant(0),
12110 MachinePointerInfo(Ptr), false, false, false, 0);
12112 unsigned char OperandFlags = 0;
12113 // Most TLS accesses are not RIP relative, even on x86-64. One exception is
12115 unsigned WrapperKind = X86ISD::Wrapper;
12116 if (model == TLSModel::LocalExec) {
12117 OperandFlags = is64Bit ? X86II::MO_TPOFF : X86II::MO_NTPOFF;
12118 } else if (model == TLSModel::InitialExec) {
12120 OperandFlags = X86II::MO_GOTTPOFF;
12121 WrapperKind = X86ISD::WrapperRIP;
12123 OperandFlags = isPIC ? X86II::MO_GOTNTPOFF : X86II::MO_INDNTPOFF;
12126 llvm_unreachable("Unexpected model");
12129 // emit "addl x@ntpoff,%eax" (local exec)
12130 // or "addl x@indntpoff,%eax" (initial exec)
12131 // or "addl x@gotntpoff(%ebx) ,%eax" (initial exec, 32-bit pic)
12133 DAG.getTargetGlobalAddress(GA->getGlobal(), dl, GA->getValueType(0),
12134 GA->getOffset(), OperandFlags);
12135 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
12137 if (model == TLSModel::InitialExec) {
12138 if (isPIC && !is64Bit) {
12139 Offset = DAG.getNode(ISD::ADD, dl, PtrVT,
12140 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT),
12144 Offset = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Offset,
12145 MachinePointerInfo::getGOT(), false, false, false, 0);
12148 // The address of the thread local variable is the add of the thread
12149 // pointer with the offset of the variable.
12150 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset);
12154 X86TargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const {
12156 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
12157 const GlobalValue *GV = GA->getGlobal();
12159 if (Subtarget->isTargetELF()) {
12160 TLSModel::Model model = DAG.getTarget().getTLSModel(GV);
12163 case TLSModel::GeneralDynamic:
12164 if (Subtarget->is64Bit())
12165 return LowerToTLSGeneralDynamicModel64(GA, DAG, getPointerTy());
12166 return LowerToTLSGeneralDynamicModel32(GA, DAG, getPointerTy());
12167 case TLSModel::LocalDynamic:
12168 return LowerToTLSLocalDynamicModel(GA, DAG, getPointerTy(),
12169 Subtarget->is64Bit());
12170 case TLSModel::InitialExec:
12171 case TLSModel::LocalExec:
12172 return LowerToTLSExecModel(
12173 GA, DAG, getPointerTy(), model, Subtarget->is64Bit(),
12174 DAG.getTarget().getRelocationModel() == Reloc::PIC_);
12176 llvm_unreachable("Unknown TLS model.");
12179 if (Subtarget->isTargetDarwin()) {
12180 // Darwin only has one model of TLS. Lower to that.
12181 unsigned char OpFlag = 0;
12182 unsigned WrapperKind = Subtarget->isPICStyleRIPRel() ?
12183 X86ISD::WrapperRIP : X86ISD::Wrapper;
12185 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
12186 // global base reg.
12187 bool PIC32 = (DAG.getTarget().getRelocationModel() == Reloc::PIC_) &&
12188 !Subtarget->is64Bit();
12190 OpFlag = X86II::MO_TLVP_PIC_BASE;
12192 OpFlag = X86II::MO_TLVP;
12194 SDValue Result = DAG.getTargetGlobalAddress(GA->getGlobal(), DL,
12195 GA->getValueType(0),
12196 GA->getOffset(), OpFlag);
12197 SDValue Offset = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
12199 // With PIC32, the address is actually $g + Offset.
12201 Offset = DAG.getNode(ISD::ADD, DL, getPointerTy(),
12202 DAG.getNode(X86ISD::GlobalBaseReg,
12203 SDLoc(), getPointerTy()),
12206 // Lowering the machine isd will make sure everything is in the right
12208 SDValue Chain = DAG.getEntryNode();
12209 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
12210 SDValue Args[] = { Chain, Offset };
12211 Chain = DAG.getNode(X86ISD::TLSCALL, DL, NodeTys, Args);
12213 // TLSCALL will be codegen'ed as call. Inform MFI that function has calls.
12214 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
12215 MFI->setAdjustsStack(true);
12217 // And our return value (tls address) is in the standard call return value
12219 unsigned Reg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
12220 return DAG.getCopyFromReg(Chain, DL, Reg, getPointerTy(),
12221 Chain.getValue(1));
12224 if (Subtarget->isTargetKnownWindowsMSVC() ||
12225 Subtarget->isTargetWindowsGNU()) {
12226 // Just use the implicit TLS architecture
12227 // Need to generate someting similar to:
12228 // mov rdx, qword [gs:abs 58H]; Load pointer to ThreadLocalStorage
12230 // mov ecx, dword [rel _tls_index]: Load index (from C runtime)
12231 // mov rcx, qword [rdx+rcx*8]
12232 // mov eax, .tls$:tlsvar
12233 // [rax+rcx] contains the address
12234 // Windows 64bit: gs:0x58
12235 // Windows 32bit: fs:__tls_array
12238 SDValue Chain = DAG.getEntryNode();
12240 // Get the Thread Pointer, which is %fs:__tls_array (32-bit) or
12241 // %gs:0x58 (64-bit). On MinGW, __tls_array is not available, so directly
12242 // use its literal value of 0x2C.
12243 Value *Ptr = Constant::getNullValue(Subtarget->is64Bit()
12244 ? Type::getInt8PtrTy(*DAG.getContext(),
12246 : Type::getInt32PtrTy(*DAG.getContext(),
12250 Subtarget->is64Bit()
12251 ? DAG.getIntPtrConstant(0x58)
12252 : (Subtarget->isTargetWindowsGNU()
12253 ? DAG.getIntPtrConstant(0x2C)
12254 : DAG.getExternalSymbol("_tls_array", getPointerTy()));
12256 SDValue ThreadPointer =
12257 DAG.getLoad(getPointerTy(), dl, Chain, TlsArray,
12258 MachinePointerInfo(Ptr), false, false, false, 0);
12260 // Load the _tls_index variable
12261 SDValue IDX = DAG.getExternalSymbol("_tls_index", getPointerTy());
12262 if (Subtarget->is64Bit())
12263 IDX = DAG.getExtLoad(ISD::ZEXTLOAD, dl, getPointerTy(), Chain,
12264 IDX, MachinePointerInfo(), MVT::i32,
12265 false, false, false, 0);
12267 IDX = DAG.getLoad(getPointerTy(), dl, Chain, IDX, MachinePointerInfo(),
12268 false, false, false, 0);
12270 SDValue Scale = DAG.getConstant(Log2_64_Ceil(TD->getPointerSize()),
12272 IDX = DAG.getNode(ISD::SHL, dl, getPointerTy(), IDX, Scale);
12274 SDValue res = DAG.getNode(ISD::ADD, dl, getPointerTy(), ThreadPointer, IDX);
12275 res = DAG.getLoad(getPointerTy(), dl, Chain, res, MachinePointerInfo(),
12276 false, false, false, 0);
12278 // Get the offset of start of .tls section
12279 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
12280 GA->getValueType(0),
12281 GA->getOffset(), X86II::MO_SECREL);
12282 SDValue Offset = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), TGA);
12284 // The address of the thread local variable is the add of the thread
12285 // pointer with the offset of the variable.
12286 return DAG.getNode(ISD::ADD, dl, getPointerTy(), res, Offset);
12289 llvm_unreachable("TLS not implemented for this target.");
12292 /// LowerShiftParts - Lower SRA_PARTS and friends, which return two i32 values
12293 /// and take a 2 x i32 value to shift plus a shift amount.
12294 static SDValue LowerShiftParts(SDValue Op, SelectionDAG &DAG) {
12295 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
12296 MVT VT = Op.getSimpleValueType();
12297 unsigned VTBits = VT.getSizeInBits();
12299 bool isSRA = Op.getOpcode() == ISD::SRA_PARTS;
12300 SDValue ShOpLo = Op.getOperand(0);
12301 SDValue ShOpHi = Op.getOperand(1);
12302 SDValue ShAmt = Op.getOperand(2);
12303 // X86ISD::SHLD and X86ISD::SHRD have defined overflow behavior but the
12304 // generic ISD nodes haven't. Insert an AND to be safe, it's optimized away
12306 SDValue SafeShAmt = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt,
12307 DAG.getConstant(VTBits - 1, MVT::i8));
12308 SDValue Tmp1 = isSRA ? DAG.getNode(ISD::SRA, dl, VT, ShOpHi,
12309 DAG.getConstant(VTBits - 1, MVT::i8))
12310 : DAG.getConstant(0, VT);
12312 SDValue Tmp2, Tmp3;
12313 if (Op.getOpcode() == ISD::SHL_PARTS) {
12314 Tmp2 = DAG.getNode(X86ISD::SHLD, dl, VT, ShOpHi, ShOpLo, ShAmt);
12315 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, SafeShAmt);
12317 Tmp2 = DAG.getNode(X86ISD::SHRD, dl, VT, ShOpLo, ShOpHi, ShAmt);
12318 Tmp3 = DAG.getNode(isSRA ? ISD::SRA : ISD::SRL, dl, VT, ShOpHi, SafeShAmt);
12321 // If the shift amount is larger or equal than the width of a part we can't
12322 // rely on the results of shld/shrd. Insert a test and select the appropriate
12323 // values for large shift amounts.
12324 SDValue AndNode = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt,
12325 DAG.getConstant(VTBits, MVT::i8));
12326 SDValue Cond = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
12327 AndNode, DAG.getConstant(0, MVT::i8));
12330 SDValue CC = DAG.getConstant(X86::COND_NE, MVT::i8);
12331 SDValue Ops0[4] = { Tmp2, Tmp3, CC, Cond };
12332 SDValue Ops1[4] = { Tmp3, Tmp1, CC, Cond };
12334 if (Op.getOpcode() == ISD::SHL_PARTS) {
12335 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0);
12336 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1);
12338 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0);
12339 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1);
12342 SDValue Ops[2] = { Lo, Hi };
12343 return DAG.getMergeValues(Ops, dl);
12346 SDValue X86TargetLowering::LowerSINT_TO_FP(SDValue Op,
12347 SelectionDAG &DAG) const {
12348 MVT SrcVT = Op.getOperand(0).getSimpleValueType();
12350 if (SrcVT.isVector())
12353 assert(SrcVT <= MVT::i64 && SrcVT >= MVT::i16 &&
12354 "Unknown SINT_TO_FP to lower!");
12356 // These are really Legal; return the operand so the caller accepts it as
12358 if (SrcVT == MVT::i32 && isScalarFPTypeInSSEReg(Op.getValueType()))
12360 if (SrcVT == MVT::i64 && isScalarFPTypeInSSEReg(Op.getValueType()) &&
12361 Subtarget->is64Bit()) {
12366 unsigned Size = SrcVT.getSizeInBits()/8;
12367 MachineFunction &MF = DAG.getMachineFunction();
12368 int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size, false);
12369 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
12370 SDValue Chain = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
12372 MachinePointerInfo::getFixedStack(SSFI),
12374 return BuildFILD(Op, SrcVT, Chain, StackSlot, DAG);
12377 SDValue X86TargetLowering::BuildFILD(SDValue Op, EVT SrcVT, SDValue Chain,
12379 SelectionDAG &DAG) const {
12383 bool useSSE = isScalarFPTypeInSSEReg(Op.getValueType());
12385 Tys = DAG.getVTList(MVT::f64, MVT::Other, MVT::Glue);
12387 Tys = DAG.getVTList(Op.getValueType(), MVT::Other);
12389 unsigned ByteSize = SrcVT.getSizeInBits()/8;
12391 FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(StackSlot);
12392 MachineMemOperand *MMO;
12394 int SSFI = FI->getIndex();
12396 DAG.getMachineFunction()
12397 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
12398 MachineMemOperand::MOLoad, ByteSize, ByteSize);
12400 MMO = cast<LoadSDNode>(StackSlot)->getMemOperand();
12401 StackSlot = StackSlot.getOperand(1);
12403 SDValue Ops[] = { Chain, StackSlot, DAG.getValueType(SrcVT) };
12404 SDValue Result = DAG.getMemIntrinsicNode(useSSE ? X86ISD::FILD_FLAG :
12406 Tys, Ops, SrcVT, MMO);
12409 Chain = Result.getValue(1);
12410 SDValue InFlag = Result.getValue(2);
12412 // FIXME: Currently the FST is flagged to the FILD_FLAG. This
12413 // shouldn't be necessary except that RFP cannot be live across
12414 // multiple blocks. When stackifier is fixed, they can be uncoupled.
12415 MachineFunction &MF = DAG.getMachineFunction();
12416 unsigned SSFISize = Op.getValueType().getSizeInBits()/8;
12417 int SSFI = MF.getFrameInfo()->CreateStackObject(SSFISize, SSFISize, false);
12418 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
12419 Tys = DAG.getVTList(MVT::Other);
12421 Chain, Result, StackSlot, DAG.getValueType(Op.getValueType()), InFlag
12423 MachineMemOperand *MMO =
12424 DAG.getMachineFunction()
12425 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
12426 MachineMemOperand::MOStore, SSFISize, SSFISize);
12428 Chain = DAG.getMemIntrinsicNode(X86ISD::FST, DL, Tys,
12429 Ops, Op.getValueType(), MMO);
12430 Result = DAG.getLoad(Op.getValueType(), DL, Chain, StackSlot,
12431 MachinePointerInfo::getFixedStack(SSFI),
12432 false, false, false, 0);
12438 // LowerUINT_TO_FP_i64 - 64-bit unsigned integer to double expansion.
12439 SDValue X86TargetLowering::LowerUINT_TO_FP_i64(SDValue Op,
12440 SelectionDAG &DAG) const {
12441 // This algorithm is not obvious. Here it is what we're trying to output:
12444 punpckldq (c0), %xmm0 // c0: (uint4){ 0x43300000U, 0x45300000U, 0U, 0U }
12445 subpd (c1), %xmm0 // c1: (double2){ 0x1.0p52, 0x1.0p52 * 0x1.0p32 }
12447 haddpd %xmm0, %xmm0
12449 pshufd $0x4e, %xmm0, %xmm1
12455 LLVMContext *Context = DAG.getContext();
12457 // Build some magic constants.
12458 static const uint32_t CV0[] = { 0x43300000, 0x45300000, 0, 0 };
12459 Constant *C0 = ConstantDataVector::get(*Context, CV0);
12460 SDValue CPIdx0 = DAG.getConstantPool(C0, getPointerTy(), 16);
12462 SmallVector<Constant*,2> CV1;
12464 ConstantFP::get(*Context, APFloat(APFloat::IEEEdouble,
12465 APInt(64, 0x4330000000000000ULL))));
12467 ConstantFP::get(*Context, APFloat(APFloat::IEEEdouble,
12468 APInt(64, 0x4530000000000000ULL))));
12469 Constant *C1 = ConstantVector::get(CV1);
12470 SDValue CPIdx1 = DAG.getConstantPool(C1, getPointerTy(), 16);
12472 // Load the 64-bit value into an XMM register.
12473 SDValue XR1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
12475 SDValue CLod0 = DAG.getLoad(MVT::v4i32, dl, DAG.getEntryNode(), CPIdx0,
12476 MachinePointerInfo::getConstantPool(),
12477 false, false, false, 16);
12478 SDValue Unpck1 = getUnpackl(DAG, dl, MVT::v4i32,
12479 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, XR1),
12482 SDValue CLod1 = DAG.getLoad(MVT::v2f64, dl, CLod0.getValue(1), CPIdx1,
12483 MachinePointerInfo::getConstantPool(),
12484 false, false, false, 16);
12485 SDValue XR2F = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Unpck1);
12486 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, XR2F, CLod1);
12489 if (Subtarget->hasSSE3()) {
12490 // FIXME: The 'haddpd' instruction may be slower than 'movhlps + addsd'.
12491 Result = DAG.getNode(X86ISD::FHADD, dl, MVT::v2f64, Sub, Sub);
12493 SDValue S2F = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Sub);
12494 SDValue Shuffle = getTargetShuffleNode(X86ISD::PSHUFD, dl, MVT::v4i32,
12496 Result = DAG.getNode(ISD::FADD, dl, MVT::v2f64,
12497 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Shuffle),
12501 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Result,
12502 DAG.getIntPtrConstant(0));
12505 // LowerUINT_TO_FP_i32 - 32-bit unsigned integer to float expansion.
12506 SDValue X86TargetLowering::LowerUINT_TO_FP_i32(SDValue Op,
12507 SelectionDAG &DAG) const {
12509 // FP constant to bias correct the final result.
12510 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL),
12513 // Load the 32-bit value into an XMM register.
12514 SDValue Load = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,
12517 // Zero out the upper parts of the register.
12518 Load = getShuffleVectorZeroOrUndef(Load, 0, true, Subtarget, DAG);
12520 Load = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
12521 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Load),
12522 DAG.getIntPtrConstant(0));
12524 // Or the load with the bias.
12525 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64,
12526 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
12527 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
12528 MVT::v2f64, Load)),
12529 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
12530 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
12531 MVT::v2f64, Bias)));
12532 Or = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
12533 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Or),
12534 DAG.getIntPtrConstant(0));
12536 // Subtract the bias.
12537 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Or, Bias);
12539 // Handle final rounding.
12540 EVT DestVT = Op.getValueType();
12542 if (DestVT.bitsLT(MVT::f64))
12543 return DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub,
12544 DAG.getIntPtrConstant(0));
12545 if (DestVT.bitsGT(MVT::f64))
12546 return DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub);
12548 // Handle final rounding.
12552 SDValue X86TargetLowering::lowerUINT_TO_FP_vec(SDValue Op,
12553 SelectionDAG &DAG) const {
12554 SDValue N0 = Op.getOperand(0);
12555 MVT SVT = N0.getSimpleValueType();
12558 assert((SVT == MVT::v4i8 || SVT == MVT::v4i16 ||
12559 SVT == MVT::v8i8 || SVT == MVT::v8i16) &&
12560 "Custom UINT_TO_FP is not supported!");
12562 MVT NVT = MVT::getVectorVT(MVT::i32, SVT.getVectorNumElements());
12563 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(),
12564 DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, N0));
12567 SDValue X86TargetLowering::LowerUINT_TO_FP(SDValue Op,
12568 SelectionDAG &DAG) const {
12569 SDValue N0 = Op.getOperand(0);
12572 if (Op.getValueType().isVector())
12573 return lowerUINT_TO_FP_vec(Op, DAG);
12575 // Since UINT_TO_FP is legal (it's marked custom), dag combiner won't
12576 // optimize it to a SINT_TO_FP when the sign bit is known zero. Perform
12577 // the optimization here.
12578 if (DAG.SignBitIsZero(N0))
12579 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(), N0);
12581 MVT SrcVT = N0.getSimpleValueType();
12582 MVT DstVT = Op.getSimpleValueType();
12583 if (SrcVT == MVT::i64 && DstVT == MVT::f64 && X86ScalarSSEf64)
12584 return LowerUINT_TO_FP_i64(Op, DAG);
12585 if (SrcVT == MVT::i32 && X86ScalarSSEf64)
12586 return LowerUINT_TO_FP_i32(Op, DAG);
12587 if (Subtarget->is64Bit() && SrcVT == MVT::i64 && DstVT == MVT::f32)
12590 // Make a 64-bit buffer, and use it to build an FILD.
12591 SDValue StackSlot = DAG.CreateStackTemporary(MVT::i64);
12592 if (SrcVT == MVT::i32) {
12593 SDValue WordOff = DAG.getConstant(4, getPointerTy());
12594 SDValue OffsetSlot = DAG.getNode(ISD::ADD, dl,
12595 getPointerTy(), StackSlot, WordOff);
12596 SDValue Store1 = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
12597 StackSlot, MachinePointerInfo(),
12599 SDValue Store2 = DAG.getStore(Store1, dl, DAG.getConstant(0, MVT::i32),
12600 OffsetSlot, MachinePointerInfo(),
12602 SDValue Fild = BuildFILD(Op, MVT::i64, Store2, StackSlot, DAG);
12606 assert(SrcVT == MVT::i64 && "Unexpected type in UINT_TO_FP");
12607 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
12608 StackSlot, MachinePointerInfo(),
12610 // For i64 source, we need to add the appropriate power of 2 if the input
12611 // was negative. This is the same as the optimization in
12612 // DAGTypeLegalizer::ExpandIntOp_UNIT_TO_FP, and for it to be safe here,
12613 // we must be careful to do the computation in x87 extended precision, not
12614 // in SSE. (The generic code can't know it's OK to do this, or how to.)
12615 int SSFI = cast<FrameIndexSDNode>(StackSlot)->getIndex();
12616 MachineMemOperand *MMO =
12617 DAG.getMachineFunction()
12618 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
12619 MachineMemOperand::MOLoad, 8, 8);
12621 SDVTList Tys = DAG.getVTList(MVT::f80, MVT::Other);
12622 SDValue Ops[] = { Store, StackSlot, DAG.getValueType(MVT::i64) };
12623 SDValue Fild = DAG.getMemIntrinsicNode(X86ISD::FILD, dl, Tys, Ops,
12626 APInt FF(32, 0x5F800000ULL);
12628 // Check whether the sign bit is set.
12629 SDValue SignSet = DAG.getSetCC(dl,
12630 getSetCCResultType(*DAG.getContext(), MVT::i64),
12631 Op.getOperand(0), DAG.getConstant(0, MVT::i64),
12634 // Build a 64 bit pair (0, FF) in the constant pool, with FF in the lo bits.
12635 SDValue FudgePtr = DAG.getConstantPool(
12636 ConstantInt::get(*DAG.getContext(), FF.zext(64)),
12639 // Get a pointer to FF if the sign bit was set, or to 0 otherwise.
12640 SDValue Zero = DAG.getIntPtrConstant(0);
12641 SDValue Four = DAG.getIntPtrConstant(4);
12642 SDValue Offset = DAG.getNode(ISD::SELECT, dl, Zero.getValueType(), SignSet,
12644 FudgePtr = DAG.getNode(ISD::ADD, dl, getPointerTy(), FudgePtr, Offset);
12646 // Load the value out, extending it from f32 to f80.
12647 // FIXME: Avoid the extend by constructing the right constant pool?
12648 SDValue Fudge = DAG.getExtLoad(ISD::EXTLOAD, dl, MVT::f80, DAG.getEntryNode(),
12649 FudgePtr, MachinePointerInfo::getConstantPool(),
12650 MVT::f32, false, false, false, 4);
12651 // Extend everything to 80 bits to force it to be done on x87.
12652 SDValue Add = DAG.getNode(ISD::FADD, dl, MVT::f80, Fild, Fudge);
12653 return DAG.getNode(ISD::FP_ROUND, dl, DstVT, Add, DAG.getIntPtrConstant(0));
12656 std::pair<SDValue,SDValue>
12657 X86TargetLowering:: FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG,
12658 bool IsSigned, bool IsReplace) const {
12661 EVT DstTy = Op.getValueType();
12663 if (!IsSigned && !isIntegerTypeFTOL(DstTy)) {
12664 assert(DstTy == MVT::i32 && "Unexpected FP_TO_UINT");
12668 assert(DstTy.getSimpleVT() <= MVT::i64 &&
12669 DstTy.getSimpleVT() >= MVT::i16 &&
12670 "Unknown FP_TO_INT to lower!");
12672 // These are really Legal.
12673 if (DstTy == MVT::i32 &&
12674 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
12675 return std::make_pair(SDValue(), SDValue());
12676 if (Subtarget->is64Bit() &&
12677 DstTy == MVT::i64 &&
12678 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
12679 return std::make_pair(SDValue(), SDValue());
12681 // We lower FP->int64 either into FISTP64 followed by a load from a temporary
12682 // stack slot, or into the FTOL runtime function.
12683 MachineFunction &MF = DAG.getMachineFunction();
12684 unsigned MemSize = DstTy.getSizeInBits()/8;
12685 int SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
12686 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
12689 if (!IsSigned && isIntegerTypeFTOL(DstTy))
12690 Opc = X86ISD::WIN_FTOL;
12692 switch (DstTy.getSimpleVT().SimpleTy) {
12693 default: llvm_unreachable("Invalid FP_TO_SINT to lower!");
12694 case MVT::i16: Opc = X86ISD::FP_TO_INT16_IN_MEM; break;
12695 case MVT::i32: Opc = X86ISD::FP_TO_INT32_IN_MEM; break;
12696 case MVT::i64: Opc = X86ISD::FP_TO_INT64_IN_MEM; break;
12699 SDValue Chain = DAG.getEntryNode();
12700 SDValue Value = Op.getOperand(0);
12701 EVT TheVT = Op.getOperand(0).getValueType();
12702 // FIXME This causes a redundant load/store if the SSE-class value is already
12703 // in memory, such as if it is on the callstack.
12704 if (isScalarFPTypeInSSEReg(TheVT)) {
12705 assert(DstTy == MVT::i64 && "Invalid FP_TO_SINT to lower!");
12706 Chain = DAG.getStore(Chain, DL, Value, StackSlot,
12707 MachinePointerInfo::getFixedStack(SSFI),
12709 SDVTList Tys = DAG.getVTList(Op.getOperand(0).getValueType(), MVT::Other);
12711 Chain, StackSlot, DAG.getValueType(TheVT)
12714 MachineMemOperand *MMO =
12715 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
12716 MachineMemOperand::MOLoad, MemSize, MemSize);
12717 Value = DAG.getMemIntrinsicNode(X86ISD::FLD, DL, Tys, Ops, DstTy, MMO);
12718 Chain = Value.getValue(1);
12719 SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
12720 StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
12723 MachineMemOperand *MMO =
12724 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
12725 MachineMemOperand::MOStore, MemSize, MemSize);
12727 if (Opc != X86ISD::WIN_FTOL) {
12728 // Build the FP_TO_INT*_IN_MEM
12729 SDValue Ops[] = { Chain, Value, StackSlot };
12730 SDValue FIST = DAG.getMemIntrinsicNode(Opc, DL, DAG.getVTList(MVT::Other),
12732 return std::make_pair(FIST, StackSlot);
12734 SDValue ftol = DAG.getNode(X86ISD::WIN_FTOL, DL,
12735 DAG.getVTList(MVT::Other, MVT::Glue),
12737 SDValue eax = DAG.getCopyFromReg(ftol, DL, X86::EAX,
12738 MVT::i32, ftol.getValue(1));
12739 SDValue edx = DAG.getCopyFromReg(eax.getValue(1), DL, X86::EDX,
12740 MVT::i32, eax.getValue(2));
12741 SDValue Ops[] = { eax, edx };
12742 SDValue pair = IsReplace
12743 ? DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops)
12744 : DAG.getMergeValues(Ops, DL);
12745 return std::make_pair(pair, SDValue());
12749 static SDValue LowerAVXExtend(SDValue Op, SelectionDAG &DAG,
12750 const X86Subtarget *Subtarget) {
12751 MVT VT = Op->getSimpleValueType(0);
12752 SDValue In = Op->getOperand(0);
12753 MVT InVT = In.getSimpleValueType();
12756 // Optimize vectors in AVX mode:
12759 // Use vpunpcklwd for 4 lower elements v8i16 -> v4i32.
12760 // Use vpunpckhwd for 4 upper elements v8i16 -> v4i32.
12761 // Concat upper and lower parts.
12764 // Use vpunpckldq for 4 lower elements v4i32 -> v2i64.
12765 // Use vpunpckhdq for 4 upper elements v4i32 -> v2i64.
12766 // Concat upper and lower parts.
12769 if (((VT != MVT::v16i16) || (InVT != MVT::v16i8)) &&
12770 ((VT != MVT::v8i32) || (InVT != MVT::v8i16)) &&
12771 ((VT != MVT::v4i64) || (InVT != MVT::v4i32)))
12774 if (Subtarget->hasInt256())
12775 return DAG.getNode(X86ISD::VZEXT, dl, VT, In);
12777 SDValue ZeroVec = getZeroVector(InVT, Subtarget, DAG, dl);
12778 SDValue Undef = DAG.getUNDEF(InVT);
12779 bool NeedZero = Op.getOpcode() == ISD::ZERO_EXTEND;
12780 SDValue OpLo = getUnpackl(DAG, dl, InVT, In, NeedZero ? ZeroVec : Undef);
12781 SDValue OpHi = getUnpackh(DAG, dl, InVT, In, NeedZero ? ZeroVec : Undef);
12783 MVT HVT = MVT::getVectorVT(VT.getVectorElementType(),
12784 VT.getVectorNumElements()/2);
12786 OpLo = DAG.getNode(ISD::BITCAST, dl, HVT, OpLo);
12787 OpHi = DAG.getNode(ISD::BITCAST, dl, HVT, OpHi);
12789 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi);
12792 static SDValue LowerZERO_EXTEND_AVX512(SDValue Op,
12793 SelectionDAG &DAG) {
12794 MVT VT = Op->getSimpleValueType(0);
12795 SDValue In = Op->getOperand(0);
12796 MVT InVT = In.getSimpleValueType();
12798 unsigned int NumElts = VT.getVectorNumElements();
12799 if (NumElts != 8 && NumElts != 16)
12802 if (VT.is512BitVector() && InVT.getVectorElementType() != MVT::i1)
12803 return DAG.getNode(X86ISD::VZEXT, DL, VT, In);
12805 EVT ExtVT = (NumElts == 8)? MVT::v8i64 : MVT::v16i32;
12806 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
12807 // Now we have only mask extension
12808 assert(InVT.getVectorElementType() == MVT::i1);
12809 SDValue Cst = DAG.getTargetConstant(1, ExtVT.getScalarType());
12810 const Constant *C = (dyn_cast<ConstantSDNode>(Cst))->getConstantIntValue();
12811 SDValue CP = DAG.getConstantPool(C, TLI.getPointerTy());
12812 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
12813 SDValue Ld = DAG.getLoad(Cst.getValueType(), DL, DAG.getEntryNode(), CP,
12814 MachinePointerInfo::getConstantPool(),
12815 false, false, false, Alignment);
12817 SDValue Brcst = DAG.getNode(X86ISD::VBROADCASTM, DL, ExtVT, In, Ld);
12818 if (VT.is512BitVector())
12820 return DAG.getNode(X86ISD::VTRUNC, DL, VT, Brcst);
12823 static SDValue LowerANY_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
12824 SelectionDAG &DAG) {
12825 if (Subtarget->hasFp256()) {
12826 SDValue Res = LowerAVXExtend(Op, DAG, Subtarget);
12834 static SDValue LowerZERO_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
12835 SelectionDAG &DAG) {
12837 MVT VT = Op.getSimpleValueType();
12838 SDValue In = Op.getOperand(0);
12839 MVT SVT = In.getSimpleValueType();
12841 if (VT.is512BitVector() || SVT.getVectorElementType() == MVT::i1)
12842 return LowerZERO_EXTEND_AVX512(Op, DAG);
12844 if (Subtarget->hasFp256()) {
12845 SDValue Res = LowerAVXExtend(Op, DAG, Subtarget);
12850 assert(!VT.is256BitVector() || !SVT.is128BitVector() ||
12851 VT.getVectorNumElements() != SVT.getVectorNumElements());
12855 SDValue X86TargetLowering::LowerTRUNCATE(SDValue Op, SelectionDAG &DAG) const {
12857 MVT VT = Op.getSimpleValueType();
12858 SDValue In = Op.getOperand(0);
12859 MVT InVT = In.getSimpleValueType();
12861 if (VT == MVT::i1) {
12862 assert((InVT.isInteger() && (InVT.getSizeInBits() <= 64)) &&
12863 "Invalid scalar TRUNCATE operation");
12864 if (InVT.getSizeInBits() >= 32)
12866 In = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i32, In);
12867 return DAG.getNode(ISD::TRUNCATE, DL, VT, In);
12869 assert(VT.getVectorNumElements() == InVT.getVectorNumElements() &&
12870 "Invalid TRUNCATE operation");
12872 if (InVT.is512BitVector() || VT.getVectorElementType() == MVT::i1) {
12873 if (VT.getVectorElementType().getSizeInBits() >=8)
12874 return DAG.getNode(X86ISD::VTRUNC, DL, VT, In);
12876 assert(VT.getVectorElementType() == MVT::i1 && "Unexpected vector type");
12877 unsigned NumElts = InVT.getVectorNumElements();
12878 assert ((NumElts == 8 || NumElts == 16) && "Unexpected vector type");
12879 if (InVT.getSizeInBits() < 512) {
12880 MVT ExtVT = (NumElts == 16)? MVT::v16i32 : MVT::v8i64;
12881 In = DAG.getNode(ISD::SIGN_EXTEND, DL, ExtVT, In);
12885 SDValue Cst = DAG.getTargetConstant(1, InVT.getVectorElementType());
12886 const Constant *C = (dyn_cast<ConstantSDNode>(Cst))->getConstantIntValue();
12887 SDValue CP = DAG.getConstantPool(C, getPointerTy());
12888 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
12889 SDValue Ld = DAG.getLoad(Cst.getValueType(), DL, DAG.getEntryNode(), CP,
12890 MachinePointerInfo::getConstantPool(),
12891 false, false, false, Alignment);
12892 SDValue OneV = DAG.getNode(X86ISD::VBROADCAST, DL, InVT, Ld);
12893 SDValue And = DAG.getNode(ISD::AND, DL, InVT, OneV, In);
12894 return DAG.getNode(X86ISD::TESTM, DL, VT, And, And);
12897 if ((VT == MVT::v4i32) && (InVT == MVT::v4i64)) {
12898 // On AVX2, v4i64 -> v4i32 becomes VPERMD.
12899 if (Subtarget->hasInt256()) {
12900 static const int ShufMask[] = {0, 2, 4, 6, -1, -1, -1, -1};
12901 In = DAG.getNode(ISD::BITCAST, DL, MVT::v8i32, In);
12902 In = DAG.getVectorShuffle(MVT::v8i32, DL, In, DAG.getUNDEF(MVT::v8i32),
12904 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, In,
12905 DAG.getIntPtrConstant(0));
12908 SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
12909 DAG.getIntPtrConstant(0));
12910 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
12911 DAG.getIntPtrConstant(2));
12912 OpLo = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpLo);
12913 OpHi = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpHi);
12914 static const int ShufMask[] = {0, 2, 4, 6};
12915 return DAG.getVectorShuffle(VT, DL, OpLo, OpHi, ShufMask);
12918 if ((VT == MVT::v8i16) && (InVT == MVT::v8i32)) {
12919 // On AVX2, v8i32 -> v8i16 becomed PSHUFB.
12920 if (Subtarget->hasInt256()) {
12921 In = DAG.getNode(ISD::BITCAST, DL, MVT::v32i8, In);
12923 SmallVector<SDValue,32> pshufbMask;
12924 for (unsigned i = 0; i < 2; ++i) {
12925 pshufbMask.push_back(DAG.getConstant(0x0, MVT::i8));
12926 pshufbMask.push_back(DAG.getConstant(0x1, MVT::i8));
12927 pshufbMask.push_back(DAG.getConstant(0x4, MVT::i8));
12928 pshufbMask.push_back(DAG.getConstant(0x5, MVT::i8));
12929 pshufbMask.push_back(DAG.getConstant(0x8, MVT::i8));
12930 pshufbMask.push_back(DAG.getConstant(0x9, MVT::i8));
12931 pshufbMask.push_back(DAG.getConstant(0xc, MVT::i8));
12932 pshufbMask.push_back(DAG.getConstant(0xd, MVT::i8));
12933 for (unsigned j = 0; j < 8; ++j)
12934 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
12936 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v32i8, pshufbMask);
12937 In = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v32i8, In, BV);
12938 In = DAG.getNode(ISD::BITCAST, DL, MVT::v4i64, In);
12940 static const int ShufMask[] = {0, 2, -1, -1};
12941 In = DAG.getVectorShuffle(MVT::v4i64, DL, In, DAG.getUNDEF(MVT::v4i64),
12943 In = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
12944 DAG.getIntPtrConstant(0));
12945 return DAG.getNode(ISD::BITCAST, DL, VT, In);
12948 SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v4i32, In,
12949 DAG.getIntPtrConstant(0));
12951 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v4i32, In,
12952 DAG.getIntPtrConstant(4));
12954 OpLo = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, OpLo);
12955 OpHi = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, OpHi);
12957 // The PSHUFB mask:
12958 static const int ShufMask1[] = {0, 1, 4, 5, 8, 9, 12, 13,
12959 -1, -1, -1, -1, -1, -1, -1, -1};
12961 SDValue Undef = DAG.getUNDEF(MVT::v16i8);
12962 OpLo = DAG.getVectorShuffle(MVT::v16i8, DL, OpLo, Undef, ShufMask1);
12963 OpHi = DAG.getVectorShuffle(MVT::v16i8, DL, OpHi, Undef, ShufMask1);
12965 OpLo = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpLo);
12966 OpHi = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpHi);
12968 // The MOVLHPS Mask:
12969 static const int ShufMask2[] = {0, 1, 4, 5};
12970 SDValue res = DAG.getVectorShuffle(MVT::v4i32, DL, OpLo, OpHi, ShufMask2);
12971 return DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, res);
12974 // Handle truncation of V256 to V128 using shuffles.
12975 if (!VT.is128BitVector() || !InVT.is256BitVector())
12978 assert(Subtarget->hasFp256() && "256-bit vector without AVX!");
12980 unsigned NumElems = VT.getVectorNumElements();
12981 MVT NVT = MVT::getVectorVT(VT.getVectorElementType(), NumElems * 2);
12983 SmallVector<int, 16> MaskVec(NumElems * 2, -1);
12984 // Prepare truncation shuffle mask
12985 for (unsigned i = 0; i != NumElems; ++i)
12986 MaskVec[i] = i * 2;
12987 SDValue V = DAG.getVectorShuffle(NVT, DL,
12988 DAG.getNode(ISD::BITCAST, DL, NVT, In),
12989 DAG.getUNDEF(NVT), &MaskVec[0]);
12990 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, V,
12991 DAG.getIntPtrConstant(0));
12994 SDValue X86TargetLowering::LowerFP_TO_SINT(SDValue Op,
12995 SelectionDAG &DAG) const {
12996 assert(!Op.getSimpleValueType().isVector());
12998 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG,
12999 /*IsSigned=*/ true, /*IsReplace=*/ false);
13000 SDValue FIST = Vals.first, StackSlot = Vals.second;
13001 // If FP_TO_INTHelper failed, the node is actually supposed to be Legal.
13002 if (!FIST.getNode()) return Op;
13004 if (StackSlot.getNode())
13005 // Load the result.
13006 return DAG.getLoad(Op.getValueType(), SDLoc(Op),
13007 FIST, StackSlot, MachinePointerInfo(),
13008 false, false, false, 0);
13010 // The node is the result.
13014 SDValue X86TargetLowering::LowerFP_TO_UINT(SDValue Op,
13015 SelectionDAG &DAG) const {
13016 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG,
13017 /*IsSigned=*/ false, /*IsReplace=*/ false);
13018 SDValue FIST = Vals.first, StackSlot = Vals.second;
13019 assert(FIST.getNode() && "Unexpected failure");
13021 if (StackSlot.getNode())
13022 // Load the result.
13023 return DAG.getLoad(Op.getValueType(), SDLoc(Op),
13024 FIST, StackSlot, MachinePointerInfo(),
13025 false, false, false, 0);
13027 // The node is the result.
13031 static SDValue LowerFP_EXTEND(SDValue Op, SelectionDAG &DAG) {
13033 MVT VT = Op.getSimpleValueType();
13034 SDValue In = Op.getOperand(0);
13035 MVT SVT = In.getSimpleValueType();
13037 assert(SVT == MVT::v2f32 && "Only customize MVT::v2f32 type legalization!");
13039 return DAG.getNode(X86ISD::VFPEXT, DL, VT,
13040 DAG.getNode(ISD::CONCAT_VECTORS, DL, MVT::v4f32,
13041 In, DAG.getUNDEF(SVT)));
13044 // The only differences between FABS and FNEG are the mask and the logic op.
13045 static SDValue LowerFABSorFNEG(SDValue Op, SelectionDAG &DAG) {
13046 assert((Op.getOpcode() == ISD::FABS || Op.getOpcode() == ISD::FNEG) &&
13047 "Wrong opcode for lowering FABS or FNEG.");
13049 bool IsFABS = (Op.getOpcode() == ISD::FABS);
13051 MVT VT = Op.getSimpleValueType();
13052 // Assume scalar op for initialization; update for vector if needed.
13053 // Note that there are no scalar bitwise logical SSE/AVX instructions, so we
13054 // generate a 16-byte vector constant and logic op even for the scalar case.
13055 // Using a 16-byte mask allows folding the load of the mask with
13056 // the logic op, so it can save (~4 bytes) on code size.
13058 unsigned NumElts = VT == MVT::f64 ? 2 : 4;
13059 // FIXME: Use function attribute "OptimizeForSize" and/or CodeGenOpt::Level to
13060 // decide if we should generate a 16-byte constant mask when we only need 4 or
13061 // 8 bytes for the scalar case.
13062 if (VT.isVector()) {
13063 EltVT = VT.getVectorElementType();
13064 NumElts = VT.getVectorNumElements();
13067 unsigned EltBits = EltVT.getSizeInBits();
13068 LLVMContext *Context = DAG.getContext();
13069 // For FABS, mask is 0x7f...; for FNEG, mask is 0x80...
13071 IsFABS ? APInt::getSignedMaxValue(EltBits) : APInt::getSignBit(EltBits);
13072 Constant *C = ConstantInt::get(*Context, MaskElt);
13073 C = ConstantVector::getSplat(NumElts, C);
13074 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
13075 SDValue CPIdx = DAG.getConstantPool(C, TLI.getPointerTy());
13076 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
13077 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
13078 MachinePointerInfo::getConstantPool(),
13079 false, false, false, Alignment);
13081 if (VT.isVector()) {
13082 // For a vector, cast operands to a vector type, perform the logic op,
13083 // and cast the result back to the original value type.
13084 MVT VecVT = MVT::getVectorVT(MVT::i64, VT.getSizeInBits() / 64);
13085 SDValue Op0Casted = DAG.getNode(ISD::BITCAST, dl, VecVT, Op.getOperand(0));
13086 SDValue MaskCasted = DAG.getNode(ISD::BITCAST, dl, VecVT, Mask);
13087 unsigned LogicOp = IsFABS ? ISD::AND : ISD::XOR;
13088 return DAG.getNode(ISD::BITCAST, dl, VT,
13089 DAG.getNode(LogicOp, dl, VecVT, Op0Casted, MaskCasted));
13091 // If not vector, then scalar.
13092 unsigned LogicOp = IsFABS ? X86ISD::FAND : X86ISD::FXOR;
13093 return DAG.getNode(LogicOp, dl, VT, Op.getOperand(0), Mask);
13096 static SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) {
13097 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
13098 LLVMContext *Context = DAG.getContext();
13099 SDValue Op0 = Op.getOperand(0);
13100 SDValue Op1 = Op.getOperand(1);
13102 MVT VT = Op.getSimpleValueType();
13103 MVT SrcVT = Op1.getSimpleValueType();
13105 // If second operand is smaller, extend it first.
13106 if (SrcVT.bitsLT(VT)) {
13107 Op1 = DAG.getNode(ISD::FP_EXTEND, dl, VT, Op1);
13110 // And if it is bigger, shrink it first.
13111 if (SrcVT.bitsGT(VT)) {
13112 Op1 = DAG.getNode(ISD::FP_ROUND, dl, VT, Op1, DAG.getIntPtrConstant(1));
13116 // At this point the operands and the result should have the same
13117 // type, and that won't be f80 since that is not custom lowered.
13119 // First get the sign bit of second operand.
13120 SmallVector<Constant*,4> CV;
13121 if (SrcVT == MVT::f64) {
13122 const fltSemantics &Sem = APFloat::IEEEdouble;
13123 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(64, 1ULL << 63))));
13124 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(64, 0))));
13126 const fltSemantics &Sem = APFloat::IEEEsingle;
13127 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 1U << 31))));
13128 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
13129 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
13130 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
13132 Constant *C = ConstantVector::get(CV);
13133 SDValue CPIdx = DAG.getConstantPool(C, TLI.getPointerTy(), 16);
13134 SDValue Mask1 = DAG.getLoad(SrcVT, dl, DAG.getEntryNode(), CPIdx,
13135 MachinePointerInfo::getConstantPool(),
13136 false, false, false, 16);
13137 SDValue SignBit = DAG.getNode(X86ISD::FAND, dl, SrcVT, Op1, Mask1);
13139 // Shift sign bit right or left if the two operands have different types.
13140 if (SrcVT.bitsGT(VT)) {
13141 // Op0 is MVT::f32, Op1 is MVT::f64.
13142 SignBit = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f64, SignBit);
13143 SignBit = DAG.getNode(X86ISD::FSRL, dl, MVT::v2f64, SignBit,
13144 DAG.getConstant(32, MVT::i32));
13145 SignBit = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, SignBit);
13146 SignBit = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f32, SignBit,
13147 DAG.getIntPtrConstant(0));
13150 // Clear first operand sign bit.
13152 if (VT == MVT::f64) {
13153 const fltSemantics &Sem = APFloat::IEEEdouble;
13154 CV.push_back(ConstantFP::get(*Context, APFloat(Sem,
13155 APInt(64, ~(1ULL << 63)))));
13156 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(64, 0))));
13158 const fltSemantics &Sem = APFloat::IEEEsingle;
13159 CV.push_back(ConstantFP::get(*Context, APFloat(Sem,
13160 APInt(32, ~(1U << 31)))));
13161 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
13162 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
13163 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
13165 C = ConstantVector::get(CV);
13166 CPIdx = DAG.getConstantPool(C, TLI.getPointerTy(), 16);
13167 SDValue Mask2 = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
13168 MachinePointerInfo::getConstantPool(),
13169 false, false, false, 16);
13170 SDValue Val = DAG.getNode(X86ISD::FAND, dl, VT, Op0, Mask2);
13172 // Or the value with the sign bit.
13173 return DAG.getNode(X86ISD::FOR, dl, VT, Val, SignBit);
13176 static SDValue LowerFGETSIGN(SDValue Op, SelectionDAG &DAG) {
13177 SDValue N0 = Op.getOperand(0);
13179 MVT VT = Op.getSimpleValueType();
13181 // Lower ISD::FGETSIGN to (AND (X86ISD::FGETSIGNx86 ...) 1).
13182 SDValue xFGETSIGN = DAG.getNode(X86ISD::FGETSIGNx86, dl, VT, N0,
13183 DAG.getConstant(1, VT));
13184 return DAG.getNode(ISD::AND, dl, VT, xFGETSIGN, DAG.getConstant(1, VT));
13187 // LowerVectorAllZeroTest - Check whether an OR'd tree is PTEST-able.
13189 static SDValue LowerVectorAllZeroTest(SDValue Op, const X86Subtarget *Subtarget,
13190 SelectionDAG &DAG) {
13191 assert(Op.getOpcode() == ISD::OR && "Only check OR'd tree.");
13193 if (!Subtarget->hasSSE41())
13196 if (!Op->hasOneUse())
13199 SDNode *N = Op.getNode();
13202 SmallVector<SDValue, 8> Opnds;
13203 DenseMap<SDValue, unsigned> VecInMap;
13204 SmallVector<SDValue, 8> VecIns;
13205 EVT VT = MVT::Other;
13207 // Recognize a special case where a vector is casted into wide integer to
13209 Opnds.push_back(N->getOperand(0));
13210 Opnds.push_back(N->getOperand(1));
13212 for (unsigned Slot = 0, e = Opnds.size(); Slot < e; ++Slot) {
13213 SmallVectorImpl<SDValue>::const_iterator I = Opnds.begin() + Slot;
13214 // BFS traverse all OR'd operands.
13215 if (I->getOpcode() == ISD::OR) {
13216 Opnds.push_back(I->getOperand(0));
13217 Opnds.push_back(I->getOperand(1));
13218 // Re-evaluate the number of nodes to be traversed.
13219 e += 2; // 2 more nodes (LHS and RHS) are pushed.
13223 // Quit if a non-EXTRACT_VECTOR_ELT
13224 if (I->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
13227 // Quit if without a constant index.
13228 SDValue Idx = I->getOperand(1);
13229 if (!isa<ConstantSDNode>(Idx))
13232 SDValue ExtractedFromVec = I->getOperand(0);
13233 DenseMap<SDValue, unsigned>::iterator M = VecInMap.find(ExtractedFromVec);
13234 if (M == VecInMap.end()) {
13235 VT = ExtractedFromVec.getValueType();
13236 // Quit if not 128/256-bit vector.
13237 if (!VT.is128BitVector() && !VT.is256BitVector())
13239 // Quit if not the same type.
13240 if (VecInMap.begin() != VecInMap.end() &&
13241 VT != VecInMap.begin()->first.getValueType())
13243 M = VecInMap.insert(std::make_pair(ExtractedFromVec, 0)).first;
13244 VecIns.push_back(ExtractedFromVec);
13246 M->second |= 1U << cast<ConstantSDNode>(Idx)->getZExtValue();
13249 assert((VT.is128BitVector() || VT.is256BitVector()) &&
13250 "Not extracted from 128-/256-bit vector.");
13252 unsigned FullMask = (1U << VT.getVectorNumElements()) - 1U;
13254 for (DenseMap<SDValue, unsigned>::const_iterator
13255 I = VecInMap.begin(), E = VecInMap.end(); I != E; ++I) {
13256 // Quit if not all elements are used.
13257 if (I->second != FullMask)
13261 EVT TestVT = VT.is128BitVector() ? MVT::v2i64 : MVT::v4i64;
13263 // Cast all vectors into TestVT for PTEST.
13264 for (unsigned i = 0, e = VecIns.size(); i < e; ++i)
13265 VecIns[i] = DAG.getNode(ISD::BITCAST, DL, TestVT, VecIns[i]);
13267 // If more than one full vectors are evaluated, OR them first before PTEST.
13268 for (unsigned Slot = 0, e = VecIns.size(); e - Slot > 1; Slot += 2, e += 1) {
13269 // Each iteration will OR 2 nodes and append the result until there is only
13270 // 1 node left, i.e. the final OR'd value of all vectors.
13271 SDValue LHS = VecIns[Slot];
13272 SDValue RHS = VecIns[Slot + 1];
13273 VecIns.push_back(DAG.getNode(ISD::OR, DL, TestVT, LHS, RHS));
13276 return DAG.getNode(X86ISD::PTEST, DL, MVT::i32,
13277 VecIns.back(), VecIns.back());
13280 /// \brief return true if \c Op has a use that doesn't just read flags.
13281 static bool hasNonFlagsUse(SDValue Op) {
13282 for (SDNode::use_iterator UI = Op->use_begin(), UE = Op->use_end(); UI != UE;
13284 SDNode *User = *UI;
13285 unsigned UOpNo = UI.getOperandNo();
13286 if (User->getOpcode() == ISD::TRUNCATE && User->hasOneUse()) {
13287 // Look pass truncate.
13288 UOpNo = User->use_begin().getOperandNo();
13289 User = *User->use_begin();
13292 if (User->getOpcode() != ISD::BRCOND && User->getOpcode() != ISD::SETCC &&
13293 !(User->getOpcode() == ISD::SELECT && UOpNo == 0))
13299 /// Emit nodes that will be selected as "test Op0,Op0", or something
13301 SDValue X86TargetLowering::EmitTest(SDValue Op, unsigned X86CC, SDLoc dl,
13302 SelectionDAG &DAG) const {
13303 if (Op.getValueType() == MVT::i1)
13304 // KORTEST instruction should be selected
13305 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
13306 DAG.getConstant(0, Op.getValueType()));
13308 // CF and OF aren't always set the way we want. Determine which
13309 // of these we need.
13310 bool NeedCF = false;
13311 bool NeedOF = false;
13314 case X86::COND_A: case X86::COND_AE:
13315 case X86::COND_B: case X86::COND_BE:
13318 case X86::COND_G: case X86::COND_GE:
13319 case X86::COND_L: case X86::COND_LE:
13320 case X86::COND_O: case X86::COND_NO: {
13321 // Check if we really need to set the
13322 // Overflow flag. If NoSignedWrap is present
13323 // that is not actually needed.
13324 switch (Op->getOpcode()) {
13329 const BinaryWithFlagsSDNode *BinNode =
13330 cast<BinaryWithFlagsSDNode>(Op.getNode());
13331 if (BinNode->hasNoSignedWrap())
13341 // See if we can use the EFLAGS value from the operand instead of
13342 // doing a separate TEST. TEST always sets OF and CF to 0, so unless
13343 // we prove that the arithmetic won't overflow, we can't use OF or CF.
13344 if (Op.getResNo() != 0 || NeedOF || NeedCF) {
13345 // Emit a CMP with 0, which is the TEST pattern.
13346 //if (Op.getValueType() == MVT::i1)
13347 // return DAG.getNode(X86ISD::CMP, dl, MVT::i1, Op,
13348 // DAG.getConstant(0, MVT::i1));
13349 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
13350 DAG.getConstant(0, Op.getValueType()));
13352 unsigned Opcode = 0;
13353 unsigned NumOperands = 0;
13355 // Truncate operations may prevent the merge of the SETCC instruction
13356 // and the arithmetic instruction before it. Attempt to truncate the operands
13357 // of the arithmetic instruction and use a reduced bit-width instruction.
13358 bool NeedTruncation = false;
13359 SDValue ArithOp = Op;
13360 if (Op->getOpcode() == ISD::TRUNCATE && Op->hasOneUse()) {
13361 SDValue Arith = Op->getOperand(0);
13362 // Both the trunc and the arithmetic op need to have one user each.
13363 if (Arith->hasOneUse())
13364 switch (Arith.getOpcode()) {
13371 NeedTruncation = true;
13377 // NOTICE: In the code below we use ArithOp to hold the arithmetic operation
13378 // which may be the result of a CAST. We use the variable 'Op', which is the
13379 // non-casted variable when we check for possible users.
13380 switch (ArithOp.getOpcode()) {
13382 // Due to an isel shortcoming, be conservative if this add is likely to be
13383 // selected as part of a load-modify-store instruction. When the root node
13384 // in a match is a store, isel doesn't know how to remap non-chain non-flag
13385 // uses of other nodes in the match, such as the ADD in this case. This
13386 // leads to the ADD being left around and reselected, with the result being
13387 // two adds in the output. Alas, even if none our users are stores, that
13388 // doesn't prove we're O.K. Ergo, if we have any parents that aren't
13389 // CopyToReg or SETCC, eschew INC/DEC. A better fix seems to require
13390 // climbing the DAG back to the root, and it doesn't seem to be worth the
13392 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
13393 UE = Op.getNode()->use_end(); UI != UE; ++UI)
13394 if (UI->getOpcode() != ISD::CopyToReg &&
13395 UI->getOpcode() != ISD::SETCC &&
13396 UI->getOpcode() != ISD::STORE)
13399 if (ConstantSDNode *C =
13400 dyn_cast<ConstantSDNode>(ArithOp.getNode()->getOperand(1))) {
13401 // An add of one will be selected as an INC.
13402 if (C->getAPIntValue() == 1 && !Subtarget->slowIncDec()) {
13403 Opcode = X86ISD::INC;
13408 // An add of negative one (subtract of one) will be selected as a DEC.
13409 if (C->getAPIntValue().isAllOnesValue() && !Subtarget->slowIncDec()) {
13410 Opcode = X86ISD::DEC;
13416 // Otherwise use a regular EFLAGS-setting add.
13417 Opcode = X86ISD::ADD;
13422 // If we have a constant logical shift that's only used in a comparison
13423 // against zero turn it into an equivalent AND. This allows turning it into
13424 // a TEST instruction later.
13425 if ((X86CC == X86::COND_E || X86CC == X86::COND_NE) && Op->hasOneUse() &&
13426 isa<ConstantSDNode>(Op->getOperand(1)) && !hasNonFlagsUse(Op)) {
13427 EVT VT = Op.getValueType();
13428 unsigned BitWidth = VT.getSizeInBits();
13429 unsigned ShAmt = Op->getConstantOperandVal(1);
13430 if (ShAmt >= BitWidth) // Avoid undefined shifts.
13432 APInt Mask = ArithOp.getOpcode() == ISD::SRL
13433 ? APInt::getHighBitsSet(BitWidth, BitWidth - ShAmt)
13434 : APInt::getLowBitsSet(BitWidth, BitWidth - ShAmt);
13435 if (!Mask.isSignedIntN(32)) // Avoid large immediates.
13437 SDValue New = DAG.getNode(ISD::AND, dl, VT, Op->getOperand(0),
13438 DAG.getConstant(Mask, VT));
13439 DAG.ReplaceAllUsesWith(Op, New);
13445 // If the primary and result isn't used, don't bother using X86ISD::AND,
13446 // because a TEST instruction will be better.
13447 if (!hasNonFlagsUse(Op))
13453 // Due to the ISEL shortcoming noted above, be conservative if this op is
13454 // likely to be selected as part of a load-modify-store instruction.
13455 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
13456 UE = Op.getNode()->use_end(); UI != UE; ++UI)
13457 if (UI->getOpcode() == ISD::STORE)
13460 // Otherwise use a regular EFLAGS-setting instruction.
13461 switch (ArithOp.getOpcode()) {
13462 default: llvm_unreachable("unexpected operator!");
13463 case ISD::SUB: Opcode = X86ISD::SUB; break;
13464 case ISD::XOR: Opcode = X86ISD::XOR; break;
13465 case ISD::AND: Opcode = X86ISD::AND; break;
13467 if (!NeedTruncation && (X86CC == X86::COND_E || X86CC == X86::COND_NE)) {
13468 SDValue EFLAGS = LowerVectorAllZeroTest(Op, Subtarget, DAG);
13469 if (EFLAGS.getNode())
13472 Opcode = X86ISD::OR;
13486 return SDValue(Op.getNode(), 1);
13492 // If we found that truncation is beneficial, perform the truncation and
13494 if (NeedTruncation) {
13495 EVT VT = Op.getValueType();
13496 SDValue WideVal = Op->getOperand(0);
13497 EVT WideVT = WideVal.getValueType();
13498 unsigned ConvertedOp = 0;
13499 // Use a target machine opcode to prevent further DAGCombine
13500 // optimizations that may separate the arithmetic operations
13501 // from the setcc node.
13502 switch (WideVal.getOpcode()) {
13504 case ISD::ADD: ConvertedOp = X86ISD::ADD; break;
13505 case ISD::SUB: ConvertedOp = X86ISD::SUB; break;
13506 case ISD::AND: ConvertedOp = X86ISD::AND; break;
13507 case ISD::OR: ConvertedOp = X86ISD::OR; break;
13508 case ISD::XOR: ConvertedOp = X86ISD::XOR; break;
13512 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
13513 if (TLI.isOperationLegal(WideVal.getOpcode(), WideVT)) {
13514 SDValue V0 = DAG.getNode(ISD::TRUNCATE, dl, VT, WideVal.getOperand(0));
13515 SDValue V1 = DAG.getNode(ISD::TRUNCATE, dl, VT, WideVal.getOperand(1));
13516 Op = DAG.getNode(ConvertedOp, dl, VT, V0, V1);
13522 // Emit a CMP with 0, which is the TEST pattern.
13523 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
13524 DAG.getConstant(0, Op.getValueType()));
13526 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
13527 SmallVector<SDValue, 4> Ops;
13528 for (unsigned i = 0; i != NumOperands; ++i)
13529 Ops.push_back(Op.getOperand(i));
13531 SDValue New = DAG.getNode(Opcode, dl, VTs, Ops);
13532 DAG.ReplaceAllUsesWith(Op, New);
13533 return SDValue(New.getNode(), 1);
13536 /// Emit nodes that will be selected as "cmp Op0,Op1", or something
13538 SDValue X86TargetLowering::EmitCmp(SDValue Op0, SDValue Op1, unsigned X86CC,
13539 SDLoc dl, SelectionDAG &DAG) const {
13540 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op1)) {
13541 if (C->getAPIntValue() == 0)
13542 return EmitTest(Op0, X86CC, dl, DAG);
13544 if (Op0.getValueType() == MVT::i1)
13545 llvm_unreachable("Unexpected comparison operation for MVT::i1 operands");
13548 if ((Op0.getValueType() == MVT::i8 || Op0.getValueType() == MVT::i16 ||
13549 Op0.getValueType() == MVT::i32 || Op0.getValueType() == MVT::i64)) {
13550 // Do the comparison at i32 if it's smaller, besides the Atom case.
13551 // This avoids subregister aliasing issues. Keep the smaller reference
13552 // if we're optimizing for size, however, as that'll allow better folding
13553 // of memory operations.
13554 if (Op0.getValueType() != MVT::i32 && Op0.getValueType() != MVT::i64 &&
13555 !DAG.getMachineFunction().getFunction()->getAttributes().hasAttribute(
13556 AttributeSet::FunctionIndex, Attribute::MinSize) &&
13557 !Subtarget->isAtom()) {
13558 unsigned ExtendOp =
13559 isX86CCUnsigned(X86CC) ? ISD::ZERO_EXTEND : ISD::SIGN_EXTEND;
13560 Op0 = DAG.getNode(ExtendOp, dl, MVT::i32, Op0);
13561 Op1 = DAG.getNode(ExtendOp, dl, MVT::i32, Op1);
13563 // Use SUB instead of CMP to enable CSE between SUB and CMP.
13564 SDVTList VTs = DAG.getVTList(Op0.getValueType(), MVT::i32);
13565 SDValue Sub = DAG.getNode(X86ISD::SUB, dl, VTs,
13567 return SDValue(Sub.getNode(), 1);
13569 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op0, Op1);
13572 /// Convert a comparison if required by the subtarget.
13573 SDValue X86TargetLowering::ConvertCmpIfNecessary(SDValue Cmp,
13574 SelectionDAG &DAG) const {
13575 // If the subtarget does not support the FUCOMI instruction, floating-point
13576 // comparisons have to be converted.
13577 if (Subtarget->hasCMov() ||
13578 Cmp.getOpcode() != X86ISD::CMP ||
13579 !Cmp.getOperand(0).getValueType().isFloatingPoint() ||
13580 !Cmp.getOperand(1).getValueType().isFloatingPoint())
13583 // The instruction selector will select an FUCOM instruction instead of
13584 // FUCOMI, which writes the comparison result to FPSW instead of EFLAGS. Hence
13585 // build an SDNode sequence that transfers the result from FPSW into EFLAGS:
13586 // (X86sahf (trunc (srl (X86fp_stsw (trunc (X86cmp ...)), 8))))
13588 SDValue TruncFPSW = DAG.getNode(ISD::TRUNCATE, dl, MVT::i16, Cmp);
13589 SDValue FNStSW = DAG.getNode(X86ISD::FNSTSW16r, dl, MVT::i16, TruncFPSW);
13590 SDValue Srl = DAG.getNode(ISD::SRL, dl, MVT::i16, FNStSW,
13591 DAG.getConstant(8, MVT::i8));
13592 SDValue TruncSrl = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Srl);
13593 return DAG.getNode(X86ISD::SAHF, dl, MVT::i32, TruncSrl);
13596 static bool isAllOnes(SDValue V) {
13597 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V);
13598 return C && C->isAllOnesValue();
13601 /// LowerToBT - Result of 'and' is compared against zero. Turn it into a BT node
13602 /// if it's possible.
13603 SDValue X86TargetLowering::LowerToBT(SDValue And, ISD::CondCode CC,
13604 SDLoc dl, SelectionDAG &DAG) const {
13605 SDValue Op0 = And.getOperand(0);
13606 SDValue Op1 = And.getOperand(1);
13607 if (Op0.getOpcode() == ISD::TRUNCATE)
13608 Op0 = Op0.getOperand(0);
13609 if (Op1.getOpcode() == ISD::TRUNCATE)
13610 Op1 = Op1.getOperand(0);
13613 if (Op1.getOpcode() == ISD::SHL)
13614 std::swap(Op0, Op1);
13615 if (Op0.getOpcode() == ISD::SHL) {
13616 if (ConstantSDNode *And00C = dyn_cast<ConstantSDNode>(Op0.getOperand(0)))
13617 if (And00C->getZExtValue() == 1) {
13618 // If we looked past a truncate, check that it's only truncating away
13620 unsigned BitWidth = Op0.getValueSizeInBits();
13621 unsigned AndBitWidth = And.getValueSizeInBits();
13622 if (BitWidth > AndBitWidth) {
13624 DAG.computeKnownBits(Op0, Zeros, Ones);
13625 if (Zeros.countLeadingOnes() < BitWidth - AndBitWidth)
13629 RHS = Op0.getOperand(1);
13631 } else if (Op1.getOpcode() == ISD::Constant) {
13632 ConstantSDNode *AndRHS = cast<ConstantSDNode>(Op1);
13633 uint64_t AndRHSVal = AndRHS->getZExtValue();
13634 SDValue AndLHS = Op0;
13636 if (AndRHSVal == 1 && AndLHS.getOpcode() == ISD::SRL) {
13637 LHS = AndLHS.getOperand(0);
13638 RHS = AndLHS.getOperand(1);
13641 // Use BT if the immediate can't be encoded in a TEST instruction.
13642 if (!isUInt<32>(AndRHSVal) && isPowerOf2_64(AndRHSVal)) {
13644 RHS = DAG.getConstant(Log2_64_Ceil(AndRHSVal), LHS.getValueType());
13648 if (LHS.getNode()) {
13649 // If LHS is i8, promote it to i32 with any_extend. There is no i8 BT
13650 // instruction. Since the shift amount is in-range-or-undefined, we know
13651 // that doing a bittest on the i32 value is ok. We extend to i32 because
13652 // the encoding for the i16 version is larger than the i32 version.
13653 // Also promote i16 to i32 for performance / code size reason.
13654 if (LHS.getValueType() == MVT::i8 ||
13655 LHS.getValueType() == MVT::i16)
13656 LHS = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, LHS);
13658 // If the operand types disagree, extend the shift amount to match. Since
13659 // BT ignores high bits (like shifts) we can use anyextend.
13660 if (LHS.getValueType() != RHS.getValueType())
13661 RHS = DAG.getNode(ISD::ANY_EXTEND, dl, LHS.getValueType(), RHS);
13663 SDValue BT = DAG.getNode(X86ISD::BT, dl, MVT::i32, LHS, RHS);
13664 X86::CondCode Cond = CC == ISD::SETEQ ? X86::COND_AE : X86::COND_B;
13665 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
13666 DAG.getConstant(Cond, MVT::i8), BT);
13672 /// \brief - Turns an ISD::CondCode into a value suitable for SSE floating point
13674 static int translateX86FSETCC(ISD::CondCode SetCCOpcode, SDValue &Op0,
13679 // SSE Condition code mapping:
13688 switch (SetCCOpcode) {
13689 default: llvm_unreachable("Unexpected SETCC condition");
13691 case ISD::SETEQ: SSECC = 0; break;
13693 case ISD::SETGT: Swap = true; // Fallthrough
13695 case ISD::SETOLT: SSECC = 1; break;
13697 case ISD::SETGE: Swap = true; // Fallthrough
13699 case ISD::SETOLE: SSECC = 2; break;
13700 case ISD::SETUO: SSECC = 3; break;
13702 case ISD::SETNE: SSECC = 4; break;
13703 case ISD::SETULE: Swap = true; // Fallthrough
13704 case ISD::SETUGE: SSECC = 5; break;
13705 case ISD::SETULT: Swap = true; // Fallthrough
13706 case ISD::SETUGT: SSECC = 6; break;
13707 case ISD::SETO: SSECC = 7; break;
13709 case ISD::SETONE: SSECC = 8; break;
13712 std::swap(Op0, Op1);
13717 // Lower256IntVSETCC - Break a VSETCC 256-bit integer VSETCC into two new 128
13718 // ones, and then concatenate the result back.
13719 static SDValue Lower256IntVSETCC(SDValue Op, SelectionDAG &DAG) {
13720 MVT VT = Op.getSimpleValueType();
13722 assert(VT.is256BitVector() && Op.getOpcode() == ISD::SETCC &&
13723 "Unsupported value type for operation");
13725 unsigned NumElems = VT.getVectorNumElements();
13727 SDValue CC = Op.getOperand(2);
13729 // Extract the LHS vectors
13730 SDValue LHS = Op.getOperand(0);
13731 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
13732 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
13734 // Extract the RHS vectors
13735 SDValue RHS = Op.getOperand(1);
13736 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, dl);
13737 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, dl);
13739 // Issue the operation on the smaller types and concatenate the result back
13740 MVT EltVT = VT.getVectorElementType();
13741 MVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
13742 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
13743 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1, CC),
13744 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2, CC));
13747 static SDValue LowerIntVSETCC_AVX512(SDValue Op, SelectionDAG &DAG,
13748 const X86Subtarget *Subtarget) {
13749 SDValue Op0 = Op.getOperand(0);
13750 SDValue Op1 = Op.getOperand(1);
13751 SDValue CC = Op.getOperand(2);
13752 MVT VT = Op.getSimpleValueType();
13755 assert(Op0.getValueType().getVectorElementType().getSizeInBits() >= 8 &&
13756 Op.getValueType().getScalarType() == MVT::i1 &&
13757 "Cannot set masked compare for this operation");
13759 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
13761 bool Unsigned = false;
13764 switch (SetCCOpcode) {
13765 default: llvm_unreachable("Unexpected SETCC condition");
13766 case ISD::SETNE: SSECC = 4; break;
13767 case ISD::SETEQ: Opc = X86ISD::PCMPEQM; break;
13768 case ISD::SETUGT: SSECC = 6; Unsigned = true; break;
13769 case ISD::SETLT: Swap = true; //fall-through
13770 case ISD::SETGT: Opc = X86ISD::PCMPGTM; break;
13771 case ISD::SETULT: SSECC = 1; Unsigned = true; break;
13772 case ISD::SETUGE: SSECC = 5; Unsigned = true; break; //NLT
13773 case ISD::SETGE: Swap = true; SSECC = 2; break; // LE + swap
13774 case ISD::SETULE: Unsigned = true; //fall-through
13775 case ISD::SETLE: SSECC = 2; break;
13779 std::swap(Op0, Op1);
13781 return DAG.getNode(Opc, dl, VT, Op0, Op1);
13782 Opc = Unsigned ? X86ISD::CMPMU: X86ISD::CMPM;
13783 return DAG.getNode(Opc, dl, VT, Op0, Op1,
13784 DAG.getConstant(SSECC, MVT::i8));
13787 /// \brief Try to turn a VSETULT into a VSETULE by modifying its second
13788 /// operand \p Op1. If non-trivial (for example because it's not constant)
13789 /// return an empty value.
13790 static SDValue ChangeVSETULTtoVSETULE(SDLoc dl, SDValue Op1, SelectionDAG &DAG)
13792 BuildVectorSDNode *BV = dyn_cast<BuildVectorSDNode>(Op1.getNode());
13796 MVT VT = Op1.getSimpleValueType();
13797 MVT EVT = VT.getVectorElementType();
13798 unsigned n = VT.getVectorNumElements();
13799 SmallVector<SDValue, 8> ULTOp1;
13801 for (unsigned i = 0; i < n; ++i) {
13802 ConstantSDNode *Elt = dyn_cast<ConstantSDNode>(BV->getOperand(i));
13803 if (!Elt || Elt->isOpaque() || Elt->getValueType(0) != EVT)
13806 // Avoid underflow.
13807 APInt Val = Elt->getAPIntValue();
13811 ULTOp1.push_back(DAG.getConstant(Val - 1, EVT));
13814 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, ULTOp1);
13817 static SDValue LowerVSETCC(SDValue Op, const X86Subtarget *Subtarget,
13818 SelectionDAG &DAG) {
13819 SDValue Op0 = Op.getOperand(0);
13820 SDValue Op1 = Op.getOperand(1);
13821 SDValue CC = Op.getOperand(2);
13822 MVT VT = Op.getSimpleValueType();
13823 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
13824 bool isFP = Op.getOperand(1).getSimpleValueType().isFloatingPoint();
13829 MVT EltVT = Op0.getSimpleValueType().getVectorElementType();
13830 assert(EltVT == MVT::f32 || EltVT == MVT::f64);
13833 unsigned SSECC = translateX86FSETCC(SetCCOpcode, Op0, Op1);
13834 unsigned Opc = X86ISD::CMPP;
13835 if (Subtarget->hasAVX512() && VT.getVectorElementType() == MVT::i1) {
13836 assert(VT.getVectorNumElements() <= 16);
13837 Opc = X86ISD::CMPM;
13839 // In the two special cases we can't handle, emit two comparisons.
13842 unsigned CombineOpc;
13843 if (SetCCOpcode == ISD::SETUEQ) {
13844 CC0 = 3; CC1 = 0; CombineOpc = ISD::OR;
13846 assert(SetCCOpcode == ISD::SETONE);
13847 CC0 = 7; CC1 = 4; CombineOpc = ISD::AND;
13850 SDValue Cmp0 = DAG.getNode(Opc, dl, VT, Op0, Op1,
13851 DAG.getConstant(CC0, MVT::i8));
13852 SDValue Cmp1 = DAG.getNode(Opc, dl, VT, Op0, Op1,
13853 DAG.getConstant(CC1, MVT::i8));
13854 return DAG.getNode(CombineOpc, dl, VT, Cmp0, Cmp1);
13856 // Handle all other FP comparisons here.
13857 return DAG.getNode(Opc, dl, VT, Op0, Op1,
13858 DAG.getConstant(SSECC, MVT::i8));
13861 // Break 256-bit integer vector compare into smaller ones.
13862 if (VT.is256BitVector() && !Subtarget->hasInt256())
13863 return Lower256IntVSETCC(Op, DAG);
13865 bool MaskResult = (VT.getVectorElementType() == MVT::i1);
13866 EVT OpVT = Op1.getValueType();
13867 if (Subtarget->hasAVX512()) {
13868 if (Op1.getValueType().is512BitVector() ||
13869 (Subtarget->hasBWI() && Subtarget->hasVLX()) ||
13870 (MaskResult && OpVT.getVectorElementType().getSizeInBits() >= 32))
13871 return LowerIntVSETCC_AVX512(Op, DAG, Subtarget);
13873 // In AVX-512 architecture setcc returns mask with i1 elements,
13874 // But there is no compare instruction for i8 and i16 elements in KNL.
13875 // We are not talking about 512-bit operands in this case, these
13876 // types are illegal.
13878 (OpVT.getVectorElementType().getSizeInBits() < 32 &&
13879 OpVT.getVectorElementType().getSizeInBits() >= 8))
13880 return DAG.getNode(ISD::TRUNCATE, dl, VT,
13881 DAG.getNode(ISD::SETCC, dl, OpVT, Op0, Op1, CC));
13884 // We are handling one of the integer comparisons here. Since SSE only has
13885 // GT and EQ comparisons for integer, swapping operands and multiple
13886 // operations may be required for some comparisons.
13888 bool Swap = false, Invert = false, FlipSigns = false, MinMax = false;
13889 bool Subus = false;
13891 switch (SetCCOpcode) {
13892 default: llvm_unreachable("Unexpected SETCC condition");
13893 case ISD::SETNE: Invert = true;
13894 case ISD::SETEQ: Opc = X86ISD::PCMPEQ; break;
13895 case ISD::SETLT: Swap = true;
13896 case ISD::SETGT: Opc = X86ISD::PCMPGT; break;
13897 case ISD::SETGE: Swap = true;
13898 case ISD::SETLE: Opc = X86ISD::PCMPGT;
13899 Invert = true; break;
13900 case ISD::SETULT: Swap = true;
13901 case ISD::SETUGT: Opc = X86ISD::PCMPGT;
13902 FlipSigns = true; break;
13903 case ISD::SETUGE: Swap = true;
13904 case ISD::SETULE: Opc = X86ISD::PCMPGT;
13905 FlipSigns = true; Invert = true; break;
13908 // Special case: Use min/max operations for SETULE/SETUGE
13909 MVT VET = VT.getVectorElementType();
13911 (Subtarget->hasSSE41() && (VET >= MVT::i8 && VET <= MVT::i32))
13912 || (Subtarget->hasSSE2() && (VET == MVT::i8));
13915 switch (SetCCOpcode) {
13917 case ISD::SETULE: Opc = X86ISD::UMIN; MinMax = true; break;
13918 case ISD::SETUGE: Opc = X86ISD::UMAX; MinMax = true; break;
13921 if (MinMax) { Swap = false; Invert = false; FlipSigns = false; }
13924 bool hasSubus = Subtarget->hasSSE2() && (VET == MVT::i8 || VET == MVT::i16);
13925 if (!MinMax && hasSubus) {
13926 // As another special case, use PSUBUS[BW] when it's profitable. E.g. for
13928 // t = psubus Op0, Op1
13929 // pcmpeq t, <0..0>
13930 switch (SetCCOpcode) {
13932 case ISD::SETULT: {
13933 // If the comparison is against a constant we can turn this into a
13934 // setule. With psubus, setule does not require a swap. This is
13935 // beneficial because the constant in the register is no longer
13936 // destructed as the destination so it can be hoisted out of a loop.
13937 // Only do this pre-AVX since vpcmp* is no longer destructive.
13938 if (Subtarget->hasAVX())
13940 SDValue ULEOp1 = ChangeVSETULTtoVSETULE(dl, Op1, DAG);
13941 if (ULEOp1.getNode()) {
13943 Subus = true; Invert = false; Swap = false;
13947 // Psubus is better than flip-sign because it requires no inversion.
13948 case ISD::SETUGE: Subus = true; Invert = false; Swap = true; break;
13949 case ISD::SETULE: Subus = true; Invert = false; Swap = false; break;
13953 Opc = X86ISD::SUBUS;
13959 std::swap(Op0, Op1);
13961 // Check that the operation in question is available (most are plain SSE2,
13962 // but PCMPGTQ and PCMPEQQ have different requirements).
13963 if (VT == MVT::v2i64) {
13964 if (Opc == X86ISD::PCMPGT && !Subtarget->hasSSE42()) {
13965 assert(Subtarget->hasSSE2() && "Don't know how to lower!");
13967 // First cast everything to the right type.
13968 Op0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op0);
13969 Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op1);
13971 // Since SSE has no unsigned integer comparisons, we need to flip the sign
13972 // bits of the inputs before performing those operations. The lower
13973 // compare is always unsigned.
13976 SB = DAG.getConstant(0x80000000U, MVT::v4i32);
13978 SDValue Sign = DAG.getConstant(0x80000000U, MVT::i32);
13979 SDValue Zero = DAG.getConstant(0x00000000U, MVT::i32);
13980 SB = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32,
13981 Sign, Zero, Sign, Zero);
13983 Op0 = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Op0, SB);
13984 Op1 = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Op1, SB);
13986 // Emulate PCMPGTQ with (hi1 > hi2) | ((hi1 == hi2) & (lo1 > lo2))
13987 SDValue GT = DAG.getNode(X86ISD::PCMPGT, dl, MVT::v4i32, Op0, Op1);
13988 SDValue EQ = DAG.getNode(X86ISD::PCMPEQ, dl, MVT::v4i32, Op0, Op1);
13990 // Create masks for only the low parts/high parts of the 64 bit integers.
13991 static const int MaskHi[] = { 1, 1, 3, 3 };
13992 static const int MaskLo[] = { 0, 0, 2, 2 };
13993 SDValue EQHi = DAG.getVectorShuffle(MVT::v4i32, dl, EQ, EQ, MaskHi);
13994 SDValue GTLo = DAG.getVectorShuffle(MVT::v4i32, dl, GT, GT, MaskLo);
13995 SDValue GTHi = DAG.getVectorShuffle(MVT::v4i32, dl, GT, GT, MaskHi);
13997 SDValue Result = DAG.getNode(ISD::AND, dl, MVT::v4i32, EQHi, GTLo);
13998 Result = DAG.getNode(ISD::OR, dl, MVT::v4i32, Result, GTHi);
14001 Result = DAG.getNOT(dl, Result, MVT::v4i32);
14003 return DAG.getNode(ISD::BITCAST, dl, VT, Result);
14006 if (Opc == X86ISD::PCMPEQ && !Subtarget->hasSSE41()) {
14007 // If pcmpeqq is missing but pcmpeqd is available synthesize pcmpeqq with
14008 // pcmpeqd + pshufd + pand.
14009 assert(Subtarget->hasSSE2() && !FlipSigns && "Don't know how to lower!");
14011 // First cast everything to the right type.
14012 Op0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op0);
14013 Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op1);
14016 SDValue Result = DAG.getNode(Opc, dl, MVT::v4i32, Op0, Op1);
14018 // Make sure the lower and upper halves are both all-ones.
14019 static const int Mask[] = { 1, 0, 3, 2 };
14020 SDValue Shuf = DAG.getVectorShuffle(MVT::v4i32, dl, Result, Result, Mask);
14021 Result = DAG.getNode(ISD::AND, dl, MVT::v4i32, Result, Shuf);
14024 Result = DAG.getNOT(dl, Result, MVT::v4i32);
14026 return DAG.getNode(ISD::BITCAST, dl, VT, Result);
14030 // Since SSE has no unsigned integer comparisons, we need to flip the sign
14031 // bits of the inputs before performing those operations.
14033 EVT EltVT = VT.getVectorElementType();
14034 SDValue SB = DAG.getConstant(APInt::getSignBit(EltVT.getSizeInBits()), VT);
14035 Op0 = DAG.getNode(ISD::XOR, dl, VT, Op0, SB);
14036 Op1 = DAG.getNode(ISD::XOR, dl, VT, Op1, SB);
14039 SDValue Result = DAG.getNode(Opc, dl, VT, Op0, Op1);
14041 // If the logical-not of the result is required, perform that now.
14043 Result = DAG.getNOT(dl, Result, VT);
14046 Result = DAG.getNode(X86ISD::PCMPEQ, dl, VT, Op0, Result);
14049 Result = DAG.getNode(X86ISD::PCMPEQ, dl, VT, Result,
14050 getZeroVector(VT, Subtarget, DAG, dl));
14055 SDValue X86TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
14057 MVT VT = Op.getSimpleValueType();
14059 if (VT.isVector()) return LowerVSETCC(Op, Subtarget, DAG);
14061 assert(((!Subtarget->hasAVX512() && VT == MVT::i8) || (VT == MVT::i1))
14062 && "SetCC type must be 8-bit or 1-bit integer");
14063 SDValue Op0 = Op.getOperand(0);
14064 SDValue Op1 = Op.getOperand(1);
14066 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
14068 // Optimize to BT if possible.
14069 // Lower (X & (1 << N)) == 0 to BT(X, N).
14070 // Lower ((X >>u N) & 1) != 0 to BT(X, N).
14071 // Lower ((X >>s N) & 1) != 0 to BT(X, N).
14072 if (Op0.getOpcode() == ISD::AND && Op0.hasOneUse() &&
14073 Op1.getOpcode() == ISD::Constant &&
14074 cast<ConstantSDNode>(Op1)->isNullValue() &&
14075 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
14076 SDValue NewSetCC = LowerToBT(Op0, CC, dl, DAG);
14077 if (NewSetCC.getNode())
14081 // Look for X == 0, X == 1, X != 0, or X != 1. We can simplify some forms of
14083 if (Op1.getOpcode() == ISD::Constant &&
14084 (cast<ConstantSDNode>(Op1)->getZExtValue() == 1 ||
14085 cast<ConstantSDNode>(Op1)->isNullValue()) &&
14086 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
14088 // If the input is a setcc, then reuse the input setcc or use a new one with
14089 // the inverted condition.
14090 if (Op0.getOpcode() == X86ISD::SETCC) {
14091 X86::CondCode CCode = (X86::CondCode)Op0.getConstantOperandVal(0);
14092 bool Invert = (CC == ISD::SETNE) ^
14093 cast<ConstantSDNode>(Op1)->isNullValue();
14097 CCode = X86::GetOppositeBranchCondition(CCode);
14098 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
14099 DAG.getConstant(CCode, MVT::i8),
14100 Op0.getOperand(1));
14102 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, SetCC);
14106 if ((Op0.getValueType() == MVT::i1) && (Op1.getOpcode() == ISD::Constant) &&
14107 (cast<ConstantSDNode>(Op1)->getZExtValue() == 1) &&
14108 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
14110 ISD::CondCode NewCC = ISD::getSetCCInverse(CC, true);
14111 return DAG.getSetCC(dl, VT, Op0, DAG.getConstant(0, MVT::i1), NewCC);
14114 bool isFP = Op1.getSimpleValueType().isFloatingPoint();
14115 unsigned X86CC = TranslateX86CC(CC, isFP, Op0, Op1, DAG);
14116 if (X86CC == X86::COND_INVALID)
14119 SDValue EFLAGS = EmitCmp(Op0, Op1, X86CC, dl, DAG);
14120 EFLAGS = ConvertCmpIfNecessary(EFLAGS, DAG);
14121 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
14122 DAG.getConstant(X86CC, MVT::i8), EFLAGS);
14124 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, SetCC);
14128 // isX86LogicalCmp - Return true if opcode is a X86 logical comparison.
14129 static bool isX86LogicalCmp(SDValue Op) {
14130 unsigned Opc = Op.getNode()->getOpcode();
14131 if (Opc == X86ISD::CMP || Opc == X86ISD::COMI || Opc == X86ISD::UCOMI ||
14132 Opc == X86ISD::SAHF)
14134 if (Op.getResNo() == 1 &&
14135 (Opc == X86ISD::ADD ||
14136 Opc == X86ISD::SUB ||
14137 Opc == X86ISD::ADC ||
14138 Opc == X86ISD::SBB ||
14139 Opc == X86ISD::SMUL ||
14140 Opc == X86ISD::UMUL ||
14141 Opc == X86ISD::INC ||
14142 Opc == X86ISD::DEC ||
14143 Opc == X86ISD::OR ||
14144 Opc == X86ISD::XOR ||
14145 Opc == X86ISD::AND))
14148 if (Op.getResNo() == 2 && Opc == X86ISD::UMUL)
14154 static bool isTruncWithZeroHighBitsInput(SDValue V, SelectionDAG &DAG) {
14155 if (V.getOpcode() != ISD::TRUNCATE)
14158 SDValue VOp0 = V.getOperand(0);
14159 unsigned InBits = VOp0.getValueSizeInBits();
14160 unsigned Bits = V.getValueSizeInBits();
14161 return DAG.MaskedValueIsZero(VOp0, APInt::getHighBitsSet(InBits,InBits-Bits));
14164 SDValue X86TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {
14165 bool addTest = true;
14166 SDValue Cond = Op.getOperand(0);
14167 SDValue Op1 = Op.getOperand(1);
14168 SDValue Op2 = Op.getOperand(2);
14170 EVT VT = Op1.getValueType();
14173 // Lower fp selects into a CMP/AND/ANDN/OR sequence when the necessary SSE ops
14174 // are available. Otherwise fp cmovs get lowered into a less efficient branch
14175 // sequence later on.
14176 if (Cond.getOpcode() == ISD::SETCC &&
14177 ((Subtarget->hasSSE2() && (VT == MVT::f32 || VT == MVT::f64)) ||
14178 (Subtarget->hasSSE1() && VT == MVT::f32)) &&
14179 VT == Cond.getOperand(0).getValueType() && Cond->hasOneUse()) {
14180 SDValue CondOp0 = Cond.getOperand(0), CondOp1 = Cond.getOperand(1);
14181 int SSECC = translateX86FSETCC(
14182 cast<CondCodeSDNode>(Cond.getOperand(2))->get(), CondOp0, CondOp1);
14185 if (Subtarget->hasAVX512()) {
14186 SDValue Cmp = DAG.getNode(X86ISD::FSETCC, DL, MVT::i1, CondOp0, CondOp1,
14187 DAG.getConstant(SSECC, MVT::i8));
14188 return DAG.getNode(X86ISD::SELECT, DL, VT, Cmp, Op1, Op2);
14190 SDValue Cmp = DAG.getNode(X86ISD::FSETCC, DL, VT, CondOp0, CondOp1,
14191 DAG.getConstant(SSECC, MVT::i8));
14192 SDValue AndN = DAG.getNode(X86ISD::FANDN, DL, VT, Cmp, Op2);
14193 SDValue And = DAG.getNode(X86ISD::FAND, DL, VT, Cmp, Op1);
14194 return DAG.getNode(X86ISD::FOR, DL, VT, AndN, And);
14198 if (Cond.getOpcode() == ISD::SETCC) {
14199 SDValue NewCond = LowerSETCC(Cond, DAG);
14200 if (NewCond.getNode())
14204 // (select (x == 0), -1, y) -> (sign_bit (x - 1)) | y
14205 // (select (x == 0), y, -1) -> ~(sign_bit (x - 1)) | y
14206 // (select (x != 0), y, -1) -> (sign_bit (x - 1)) | y
14207 // (select (x != 0), -1, y) -> ~(sign_bit (x - 1)) | y
14208 if (Cond.getOpcode() == X86ISD::SETCC &&
14209 Cond.getOperand(1).getOpcode() == X86ISD::CMP &&
14210 isZero(Cond.getOperand(1).getOperand(1))) {
14211 SDValue Cmp = Cond.getOperand(1);
14213 unsigned CondCode =cast<ConstantSDNode>(Cond.getOperand(0))->getZExtValue();
14215 if ((isAllOnes(Op1) || isAllOnes(Op2)) &&
14216 (CondCode == X86::COND_E || CondCode == X86::COND_NE)) {
14217 SDValue Y = isAllOnes(Op2) ? Op1 : Op2;
14219 SDValue CmpOp0 = Cmp.getOperand(0);
14220 // Apply further optimizations for special cases
14221 // (select (x != 0), -1, 0) -> neg & sbb
14222 // (select (x == 0), 0, -1) -> neg & sbb
14223 if (ConstantSDNode *YC = dyn_cast<ConstantSDNode>(Y))
14224 if (YC->isNullValue() &&
14225 (isAllOnes(Op1) == (CondCode == X86::COND_NE))) {
14226 SDVTList VTs = DAG.getVTList(CmpOp0.getValueType(), MVT::i32);
14227 SDValue Neg = DAG.getNode(X86ISD::SUB, DL, VTs,
14228 DAG.getConstant(0, CmpOp0.getValueType()),
14230 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
14231 DAG.getConstant(X86::COND_B, MVT::i8),
14232 SDValue(Neg.getNode(), 1));
14236 Cmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32,
14237 CmpOp0, DAG.getConstant(1, CmpOp0.getValueType()));
14238 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
14240 SDValue Res = // Res = 0 or -1.
14241 DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
14242 DAG.getConstant(X86::COND_B, MVT::i8), Cmp);
14244 if (isAllOnes(Op1) != (CondCode == X86::COND_E))
14245 Res = DAG.getNOT(DL, Res, Res.getValueType());
14247 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(Op2);
14248 if (!N2C || !N2C->isNullValue())
14249 Res = DAG.getNode(ISD::OR, DL, Res.getValueType(), Res, Y);
14254 // Look past (and (setcc_carry (cmp ...)), 1).
14255 if (Cond.getOpcode() == ISD::AND &&
14256 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
14257 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
14258 if (C && C->getAPIntValue() == 1)
14259 Cond = Cond.getOperand(0);
14262 // If condition flag is set by a X86ISD::CMP, then use it as the condition
14263 // setting operand in place of the X86ISD::SETCC.
14264 unsigned CondOpcode = Cond.getOpcode();
14265 if (CondOpcode == X86ISD::SETCC ||
14266 CondOpcode == X86ISD::SETCC_CARRY) {
14267 CC = Cond.getOperand(0);
14269 SDValue Cmp = Cond.getOperand(1);
14270 unsigned Opc = Cmp.getOpcode();
14271 MVT VT = Op.getSimpleValueType();
14273 bool IllegalFPCMov = false;
14274 if (VT.isFloatingPoint() && !VT.isVector() &&
14275 !isScalarFPTypeInSSEReg(VT)) // FPStack?
14276 IllegalFPCMov = !hasFPCMov(cast<ConstantSDNode>(CC)->getSExtValue());
14278 if ((isX86LogicalCmp(Cmp) && !IllegalFPCMov) ||
14279 Opc == X86ISD::BT) { // FIXME
14283 } else if (CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO ||
14284 CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO ||
14285 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) &&
14286 Cond.getOperand(0).getValueType() != MVT::i8)) {
14287 SDValue LHS = Cond.getOperand(0);
14288 SDValue RHS = Cond.getOperand(1);
14289 unsigned X86Opcode;
14292 switch (CondOpcode) {
14293 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break;
14294 case ISD::SADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break;
14295 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break;
14296 case ISD::SSUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break;
14297 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break;
14298 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break;
14299 default: llvm_unreachable("unexpected overflowing operator");
14301 if (CondOpcode == ISD::UMULO)
14302 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(),
14305 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
14307 SDValue X86Op = DAG.getNode(X86Opcode, DL, VTs, LHS, RHS);
14309 if (CondOpcode == ISD::UMULO)
14310 Cond = X86Op.getValue(2);
14312 Cond = X86Op.getValue(1);
14314 CC = DAG.getConstant(X86Cond, MVT::i8);
14319 // Look pass the truncate if the high bits are known zero.
14320 if (isTruncWithZeroHighBitsInput(Cond, DAG))
14321 Cond = Cond.getOperand(0);
14323 // We know the result of AND is compared against zero. Try to match
14325 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
14326 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, DL, DAG);
14327 if (NewSetCC.getNode()) {
14328 CC = NewSetCC.getOperand(0);
14329 Cond = NewSetCC.getOperand(1);
14336 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
14337 Cond = EmitTest(Cond, X86::COND_NE, DL, DAG);
14340 // a < b ? -1 : 0 -> RES = ~setcc_carry
14341 // a < b ? 0 : -1 -> RES = setcc_carry
14342 // a >= b ? -1 : 0 -> RES = setcc_carry
14343 // a >= b ? 0 : -1 -> RES = ~setcc_carry
14344 if (Cond.getOpcode() == X86ISD::SUB) {
14345 Cond = ConvertCmpIfNecessary(Cond, DAG);
14346 unsigned CondCode = cast<ConstantSDNode>(CC)->getZExtValue();
14348 if ((CondCode == X86::COND_AE || CondCode == X86::COND_B) &&
14349 (isAllOnes(Op1) || isAllOnes(Op2)) && (isZero(Op1) || isZero(Op2))) {
14350 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
14351 DAG.getConstant(X86::COND_B, MVT::i8), Cond);
14352 if (isAllOnes(Op1) != (CondCode == X86::COND_B))
14353 return DAG.getNOT(DL, Res, Res.getValueType());
14358 // X86 doesn't have an i8 cmov. If both operands are the result of a truncate
14359 // widen the cmov and push the truncate through. This avoids introducing a new
14360 // branch during isel and doesn't add any extensions.
14361 if (Op.getValueType() == MVT::i8 &&
14362 Op1.getOpcode() == ISD::TRUNCATE && Op2.getOpcode() == ISD::TRUNCATE) {
14363 SDValue T1 = Op1.getOperand(0), T2 = Op2.getOperand(0);
14364 if (T1.getValueType() == T2.getValueType() &&
14365 // Blacklist CopyFromReg to avoid partial register stalls.
14366 T1.getOpcode() != ISD::CopyFromReg && T2.getOpcode()!=ISD::CopyFromReg){
14367 SDVTList VTs = DAG.getVTList(T1.getValueType(), MVT::Glue);
14368 SDValue Cmov = DAG.getNode(X86ISD::CMOV, DL, VTs, T2, T1, CC, Cond);
14369 return DAG.getNode(ISD::TRUNCATE, DL, Op.getValueType(), Cmov);
14373 // X86ISD::CMOV means set the result (which is operand 1) to the RHS if
14374 // condition is true.
14375 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue);
14376 SDValue Ops[] = { Op2, Op1, CC, Cond };
14377 return DAG.getNode(X86ISD::CMOV, DL, VTs, Ops);
14380 static SDValue LowerSIGN_EXTEND_AVX512(SDValue Op, SelectionDAG &DAG) {
14381 MVT VT = Op->getSimpleValueType(0);
14382 SDValue In = Op->getOperand(0);
14383 MVT InVT = In.getSimpleValueType();
14386 unsigned int NumElts = VT.getVectorNumElements();
14387 if (NumElts != 8 && NumElts != 16)
14390 if (VT.is512BitVector() && InVT.getVectorElementType() != MVT::i1)
14391 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
14393 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
14394 assert (InVT.getVectorElementType() == MVT::i1 && "Unexpected vector type");
14396 MVT ExtVT = (NumElts == 8) ? MVT::v8i64 : MVT::v16i32;
14397 Constant *C = ConstantInt::get(*DAG.getContext(),
14398 APInt::getAllOnesValue(ExtVT.getScalarType().getSizeInBits()));
14400 SDValue CP = DAG.getConstantPool(C, TLI.getPointerTy());
14401 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
14402 SDValue Ld = DAG.getLoad(ExtVT.getScalarType(), dl, DAG.getEntryNode(), CP,
14403 MachinePointerInfo::getConstantPool(),
14404 false, false, false, Alignment);
14405 SDValue Brcst = DAG.getNode(X86ISD::VBROADCASTM, dl, ExtVT, In, Ld);
14406 if (VT.is512BitVector())
14408 return DAG.getNode(X86ISD::VTRUNC, dl, VT, Brcst);
14411 static SDValue LowerSIGN_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
14412 SelectionDAG &DAG) {
14413 MVT VT = Op->getSimpleValueType(0);
14414 SDValue In = Op->getOperand(0);
14415 MVT InVT = In.getSimpleValueType();
14418 if (VT.is512BitVector() || InVT.getVectorElementType() == MVT::i1)
14419 return LowerSIGN_EXTEND_AVX512(Op, DAG);
14421 if ((VT != MVT::v4i64 || InVT != MVT::v4i32) &&
14422 (VT != MVT::v8i32 || InVT != MVT::v8i16) &&
14423 (VT != MVT::v16i16 || InVT != MVT::v16i8))
14426 if (Subtarget->hasInt256())
14427 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
14429 // Optimize vectors in AVX mode
14430 // Sign extend v8i16 to v8i32 and
14433 // Divide input vector into two parts
14434 // for v4i32 the shuffle mask will be { 0, 1, -1, -1} {2, 3, -1, -1}
14435 // use vpmovsx instruction to extend v4i32 -> v2i64; v8i16 -> v4i32
14436 // concat the vectors to original VT
14438 unsigned NumElems = InVT.getVectorNumElements();
14439 SDValue Undef = DAG.getUNDEF(InVT);
14441 SmallVector<int,8> ShufMask1(NumElems, -1);
14442 for (unsigned i = 0; i != NumElems/2; ++i)
14445 SDValue OpLo = DAG.getVectorShuffle(InVT, dl, In, Undef, &ShufMask1[0]);
14447 SmallVector<int,8> ShufMask2(NumElems, -1);
14448 for (unsigned i = 0; i != NumElems/2; ++i)
14449 ShufMask2[i] = i + NumElems/2;
14451 SDValue OpHi = DAG.getVectorShuffle(InVT, dl, In, Undef, &ShufMask2[0]);
14453 MVT HalfVT = MVT::getVectorVT(VT.getScalarType(),
14454 VT.getVectorNumElements()/2);
14456 OpLo = DAG.getNode(X86ISD::VSEXT, dl, HalfVT, OpLo);
14457 OpHi = DAG.getNode(X86ISD::VSEXT, dl, HalfVT, OpHi);
14459 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi);
14462 // Lower vector extended loads using a shuffle. If SSSE3 is not available we
14463 // may emit an illegal shuffle but the expansion is still better than scalar
14464 // code. We generate X86ISD::VSEXT for SEXTLOADs if it's available, otherwise
14465 // we'll emit a shuffle and a arithmetic shift.
14466 // TODO: It is possible to support ZExt by zeroing the undef values during
14467 // the shuffle phase or after the shuffle.
14468 static SDValue LowerExtendedLoad(SDValue Op, const X86Subtarget *Subtarget,
14469 SelectionDAG &DAG) {
14470 MVT RegVT = Op.getSimpleValueType();
14471 assert(RegVT.isVector() && "We only custom lower vector sext loads.");
14472 assert(RegVT.isInteger() &&
14473 "We only custom lower integer vector sext loads.");
14475 // Nothing useful we can do without SSE2 shuffles.
14476 assert(Subtarget->hasSSE2() && "We only custom lower sext loads with SSE2.");
14478 LoadSDNode *Ld = cast<LoadSDNode>(Op.getNode());
14480 EVT MemVT = Ld->getMemoryVT();
14481 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
14482 unsigned RegSz = RegVT.getSizeInBits();
14484 ISD::LoadExtType Ext = Ld->getExtensionType();
14486 assert((Ext == ISD::EXTLOAD || Ext == ISD::SEXTLOAD)
14487 && "Only anyext and sext are currently implemented.");
14488 assert(MemVT != RegVT && "Cannot extend to the same type");
14489 assert(MemVT.isVector() && "Must load a vector from memory");
14491 unsigned NumElems = RegVT.getVectorNumElements();
14492 unsigned MemSz = MemVT.getSizeInBits();
14493 assert(RegSz > MemSz && "Register size must be greater than the mem size");
14495 if (Ext == ISD::SEXTLOAD && RegSz == 256 && !Subtarget->hasInt256()) {
14496 // The only way in which we have a legal 256-bit vector result but not the
14497 // integer 256-bit operations needed to directly lower a sextload is if we
14498 // have AVX1 but not AVX2. In that case, we can always emit a sextload to
14499 // a 128-bit vector and a normal sign_extend to 256-bits that should get
14500 // correctly legalized. We do this late to allow the canonical form of
14501 // sextload to persist throughout the rest of the DAG combiner -- it wants
14502 // to fold together any extensions it can, and so will fuse a sign_extend
14503 // of an sextload into a sextload targeting a wider value.
14505 if (MemSz == 128) {
14506 // Just switch this to a normal load.
14507 assert(TLI.isTypeLegal(MemVT) && "If the memory type is a 128-bit type, "
14508 "it must be a legal 128-bit vector "
14510 Load = DAG.getLoad(MemVT, dl, Ld->getChain(), Ld->getBasePtr(),
14511 Ld->getPointerInfo(), Ld->isVolatile(), Ld->isNonTemporal(),
14512 Ld->isInvariant(), Ld->getAlignment());
14514 assert(MemSz < 128 &&
14515 "Can't extend a type wider than 128 bits to a 256 bit vector!");
14516 // Do an sext load to a 128-bit vector type. We want to use the same
14517 // number of elements, but elements half as wide. This will end up being
14518 // recursively lowered by this routine, but will succeed as we definitely
14519 // have all the necessary features if we're using AVX1.
14521 EVT::getIntegerVT(*DAG.getContext(), RegVT.getScalarSizeInBits() / 2);
14522 EVT HalfVecVT = EVT::getVectorVT(*DAG.getContext(), HalfEltVT, NumElems);
14524 DAG.getExtLoad(Ext, dl, HalfVecVT, Ld->getChain(), Ld->getBasePtr(),
14525 Ld->getPointerInfo(), MemVT, Ld->isVolatile(),
14526 Ld->isNonTemporal(), Ld->isInvariant(),
14527 Ld->getAlignment());
14530 // Replace chain users with the new chain.
14531 assert(Load->getNumValues() == 2 && "Loads must carry a chain!");
14532 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), Load.getValue(1));
14534 // Finally, do a normal sign-extend to the desired register.
14535 return DAG.getSExtOrTrunc(Load, dl, RegVT);
14538 // All sizes must be a power of two.
14539 assert(isPowerOf2_32(RegSz * MemSz * NumElems) &&
14540 "Non-power-of-two elements are not custom lowered!");
14542 // Attempt to load the original value using scalar loads.
14543 // Find the largest scalar type that divides the total loaded size.
14544 MVT SclrLoadTy = MVT::i8;
14545 for (unsigned tp = MVT::FIRST_INTEGER_VALUETYPE;
14546 tp < MVT::LAST_INTEGER_VALUETYPE; ++tp) {
14547 MVT Tp = (MVT::SimpleValueType)tp;
14548 if (TLI.isTypeLegal(Tp) && ((MemSz % Tp.getSizeInBits()) == 0)) {
14553 // On 32bit systems, we can't save 64bit integers. Try bitcasting to F64.
14554 if (TLI.isTypeLegal(MVT::f64) && SclrLoadTy.getSizeInBits() < 64 &&
14556 SclrLoadTy = MVT::f64;
14558 // Calculate the number of scalar loads that we need to perform
14559 // in order to load our vector from memory.
14560 unsigned NumLoads = MemSz / SclrLoadTy.getSizeInBits();
14562 assert((Ext != ISD::SEXTLOAD || NumLoads == 1) &&
14563 "Can only lower sext loads with a single scalar load!");
14565 unsigned loadRegZize = RegSz;
14566 if (Ext == ISD::SEXTLOAD && RegSz == 256)
14569 // Represent our vector as a sequence of elements which are the
14570 // largest scalar that we can load.
14571 EVT LoadUnitVecVT = EVT::getVectorVT(
14572 *DAG.getContext(), SclrLoadTy, loadRegZize / SclrLoadTy.getSizeInBits());
14574 // Represent the data using the same element type that is stored in
14575 // memory. In practice, we ''widen'' MemVT.
14577 EVT::getVectorVT(*DAG.getContext(), MemVT.getScalarType(),
14578 loadRegZize / MemVT.getScalarType().getSizeInBits());
14580 assert(WideVecVT.getSizeInBits() == LoadUnitVecVT.getSizeInBits() &&
14581 "Invalid vector type");
14583 // We can't shuffle using an illegal type.
14584 assert(TLI.isTypeLegal(WideVecVT) &&
14585 "We only lower types that form legal widened vector types");
14587 SmallVector<SDValue, 8> Chains;
14588 SDValue Ptr = Ld->getBasePtr();
14589 SDValue Increment =
14590 DAG.getConstant(SclrLoadTy.getSizeInBits() / 8, TLI.getPointerTy());
14591 SDValue Res = DAG.getUNDEF(LoadUnitVecVT);
14593 for (unsigned i = 0; i < NumLoads; ++i) {
14594 // Perform a single load.
14595 SDValue ScalarLoad =
14596 DAG.getLoad(SclrLoadTy, dl, Ld->getChain(), Ptr, Ld->getPointerInfo(),
14597 Ld->isVolatile(), Ld->isNonTemporal(), Ld->isInvariant(),
14598 Ld->getAlignment());
14599 Chains.push_back(ScalarLoad.getValue(1));
14600 // Create the first element type using SCALAR_TO_VECTOR in order to avoid
14601 // another round of DAGCombining.
14603 Res = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, LoadUnitVecVT, ScalarLoad);
14605 Res = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, LoadUnitVecVT, Res,
14606 ScalarLoad, DAG.getIntPtrConstant(i));
14608 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
14611 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Chains);
14613 // Bitcast the loaded value to a vector of the original element type, in
14614 // the size of the target vector type.
14615 SDValue SlicedVec = DAG.getNode(ISD::BITCAST, dl, WideVecVT, Res);
14616 unsigned SizeRatio = RegSz / MemSz;
14618 if (Ext == ISD::SEXTLOAD) {
14619 // If we have SSE4.1, we can directly emit a VSEXT node.
14620 if (Subtarget->hasSSE41()) {
14621 SDValue Sext = DAG.getNode(X86ISD::VSEXT, dl, RegVT, SlicedVec);
14622 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), TF);
14626 // Otherwise we'll shuffle the small elements in the high bits of the
14627 // larger type and perform an arithmetic shift. If the shift is not legal
14628 // it's better to scalarize.
14629 assert(TLI.isOperationLegalOrCustom(ISD::SRA, RegVT) &&
14630 "We can't implement a sext load without an arithmetic right shift!");
14632 // Redistribute the loaded elements into the different locations.
14633 SmallVector<int, 16> ShuffleVec(NumElems * SizeRatio, -1);
14634 for (unsigned i = 0; i != NumElems; ++i)
14635 ShuffleVec[i * SizeRatio + SizeRatio - 1] = i;
14637 SDValue Shuff = DAG.getVectorShuffle(
14638 WideVecVT, dl, SlicedVec, DAG.getUNDEF(WideVecVT), &ShuffleVec[0]);
14640 Shuff = DAG.getNode(ISD::BITCAST, dl, RegVT, Shuff);
14642 // Build the arithmetic shift.
14643 unsigned Amt = RegVT.getVectorElementType().getSizeInBits() -
14644 MemVT.getVectorElementType().getSizeInBits();
14646 DAG.getNode(ISD::SRA, dl, RegVT, Shuff, DAG.getConstant(Amt, RegVT));
14648 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), TF);
14652 // Redistribute the loaded elements into the different locations.
14653 SmallVector<int, 16> ShuffleVec(NumElems * SizeRatio, -1);
14654 for (unsigned i = 0; i != NumElems; ++i)
14655 ShuffleVec[i * SizeRatio] = i;
14657 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, SlicedVec,
14658 DAG.getUNDEF(WideVecVT), &ShuffleVec[0]);
14660 // Bitcast to the requested type.
14661 Shuff = DAG.getNode(ISD::BITCAST, dl, RegVT, Shuff);
14662 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), TF);
14666 // isAndOrOfSingleUseSetCCs - Return true if node is an ISD::AND or
14667 // ISD::OR of two X86ISD::SETCC nodes each of which has no other use apart
14668 // from the AND / OR.
14669 static bool isAndOrOfSetCCs(SDValue Op, unsigned &Opc) {
14670 Opc = Op.getOpcode();
14671 if (Opc != ISD::OR && Opc != ISD::AND)
14673 return (Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
14674 Op.getOperand(0).hasOneUse() &&
14675 Op.getOperand(1).getOpcode() == X86ISD::SETCC &&
14676 Op.getOperand(1).hasOneUse());
14679 // isXor1OfSetCC - Return true if node is an ISD::XOR of a X86ISD::SETCC and
14680 // 1 and that the SETCC node has a single use.
14681 static bool isXor1OfSetCC(SDValue Op) {
14682 if (Op.getOpcode() != ISD::XOR)
14684 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
14685 if (N1C && N1C->getAPIntValue() == 1) {
14686 return Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
14687 Op.getOperand(0).hasOneUse();
14692 SDValue X86TargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) const {
14693 bool addTest = true;
14694 SDValue Chain = Op.getOperand(0);
14695 SDValue Cond = Op.getOperand(1);
14696 SDValue Dest = Op.getOperand(2);
14699 bool Inverted = false;
14701 if (Cond.getOpcode() == ISD::SETCC) {
14702 // Check for setcc([su]{add,sub,mul}o == 0).
14703 if (cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETEQ &&
14704 isa<ConstantSDNode>(Cond.getOperand(1)) &&
14705 cast<ConstantSDNode>(Cond.getOperand(1))->isNullValue() &&
14706 Cond.getOperand(0).getResNo() == 1 &&
14707 (Cond.getOperand(0).getOpcode() == ISD::SADDO ||
14708 Cond.getOperand(0).getOpcode() == ISD::UADDO ||
14709 Cond.getOperand(0).getOpcode() == ISD::SSUBO ||
14710 Cond.getOperand(0).getOpcode() == ISD::USUBO ||
14711 Cond.getOperand(0).getOpcode() == ISD::SMULO ||
14712 Cond.getOperand(0).getOpcode() == ISD::UMULO)) {
14714 Cond = Cond.getOperand(0);
14716 SDValue NewCond = LowerSETCC(Cond, DAG);
14717 if (NewCond.getNode())
14722 // FIXME: LowerXALUO doesn't handle these!!
14723 else if (Cond.getOpcode() == X86ISD::ADD ||
14724 Cond.getOpcode() == X86ISD::SUB ||
14725 Cond.getOpcode() == X86ISD::SMUL ||
14726 Cond.getOpcode() == X86ISD::UMUL)
14727 Cond = LowerXALUO(Cond, DAG);
14730 // Look pass (and (setcc_carry (cmp ...)), 1).
14731 if (Cond.getOpcode() == ISD::AND &&
14732 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
14733 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
14734 if (C && C->getAPIntValue() == 1)
14735 Cond = Cond.getOperand(0);
14738 // If condition flag is set by a X86ISD::CMP, then use it as the condition
14739 // setting operand in place of the X86ISD::SETCC.
14740 unsigned CondOpcode = Cond.getOpcode();
14741 if (CondOpcode == X86ISD::SETCC ||
14742 CondOpcode == X86ISD::SETCC_CARRY) {
14743 CC = Cond.getOperand(0);
14745 SDValue Cmp = Cond.getOperand(1);
14746 unsigned Opc = Cmp.getOpcode();
14747 // FIXME: WHY THE SPECIAL CASING OF LogicalCmp??
14748 if (isX86LogicalCmp(Cmp) || Opc == X86ISD::BT) {
14752 switch (cast<ConstantSDNode>(CC)->getZExtValue()) {
14756 // These can only come from an arithmetic instruction with overflow,
14757 // e.g. SADDO, UADDO.
14758 Cond = Cond.getNode()->getOperand(1);
14764 CondOpcode = Cond.getOpcode();
14765 if (CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO ||
14766 CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO ||
14767 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) &&
14768 Cond.getOperand(0).getValueType() != MVT::i8)) {
14769 SDValue LHS = Cond.getOperand(0);
14770 SDValue RHS = Cond.getOperand(1);
14771 unsigned X86Opcode;
14774 // Keep this in sync with LowerXALUO, otherwise we might create redundant
14775 // instructions that can't be removed afterwards (i.e. X86ISD::ADD and
14777 switch (CondOpcode) {
14778 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break;
14780 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
14782 X86Opcode = X86ISD::INC; X86Cond = X86::COND_O;
14785 X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break;
14786 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break;
14788 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
14790 X86Opcode = X86ISD::DEC; X86Cond = X86::COND_O;
14793 X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break;
14794 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break;
14795 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break;
14796 default: llvm_unreachable("unexpected overflowing operator");
14799 X86Cond = X86::GetOppositeBranchCondition((X86::CondCode)X86Cond);
14800 if (CondOpcode == ISD::UMULO)
14801 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(),
14804 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
14806 SDValue X86Op = DAG.getNode(X86Opcode, dl, VTs, LHS, RHS);
14808 if (CondOpcode == ISD::UMULO)
14809 Cond = X86Op.getValue(2);
14811 Cond = X86Op.getValue(1);
14813 CC = DAG.getConstant(X86Cond, MVT::i8);
14817 if (Cond.hasOneUse() && isAndOrOfSetCCs(Cond, CondOpc)) {
14818 SDValue Cmp = Cond.getOperand(0).getOperand(1);
14819 if (CondOpc == ISD::OR) {
14820 // Also, recognize the pattern generated by an FCMP_UNE. We can emit
14821 // two branches instead of an explicit OR instruction with a
14823 if (Cmp == Cond.getOperand(1).getOperand(1) &&
14824 isX86LogicalCmp(Cmp)) {
14825 CC = Cond.getOperand(0).getOperand(0);
14826 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
14827 Chain, Dest, CC, Cmp);
14828 CC = Cond.getOperand(1).getOperand(0);
14832 } else { // ISD::AND
14833 // Also, recognize the pattern generated by an FCMP_OEQ. We can emit
14834 // two branches instead of an explicit AND instruction with a
14835 // separate test. However, we only do this if this block doesn't
14836 // have a fall-through edge, because this requires an explicit
14837 // jmp when the condition is false.
14838 if (Cmp == Cond.getOperand(1).getOperand(1) &&
14839 isX86LogicalCmp(Cmp) &&
14840 Op.getNode()->hasOneUse()) {
14841 X86::CondCode CCode =
14842 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
14843 CCode = X86::GetOppositeBranchCondition(CCode);
14844 CC = DAG.getConstant(CCode, MVT::i8);
14845 SDNode *User = *Op.getNode()->use_begin();
14846 // Look for an unconditional branch following this conditional branch.
14847 // We need this because we need to reverse the successors in order
14848 // to implement FCMP_OEQ.
14849 if (User->getOpcode() == ISD::BR) {
14850 SDValue FalseBB = User->getOperand(1);
14852 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
14853 assert(NewBR == User);
14857 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
14858 Chain, Dest, CC, Cmp);
14859 X86::CondCode CCode =
14860 (X86::CondCode)Cond.getOperand(1).getConstantOperandVal(0);
14861 CCode = X86::GetOppositeBranchCondition(CCode);
14862 CC = DAG.getConstant(CCode, MVT::i8);
14868 } else if (Cond.hasOneUse() && isXor1OfSetCC(Cond)) {
14869 // Recognize for xorb (setcc), 1 patterns. The xor inverts the condition.
14870 // It should be transformed during dag combiner except when the condition
14871 // is set by a arithmetics with overflow node.
14872 X86::CondCode CCode =
14873 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
14874 CCode = X86::GetOppositeBranchCondition(CCode);
14875 CC = DAG.getConstant(CCode, MVT::i8);
14876 Cond = Cond.getOperand(0).getOperand(1);
14878 } else if (Cond.getOpcode() == ISD::SETCC &&
14879 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETOEQ) {
14880 // For FCMP_OEQ, we can emit
14881 // two branches instead of an explicit AND instruction with a
14882 // separate test. However, we only do this if this block doesn't
14883 // have a fall-through edge, because this requires an explicit
14884 // jmp when the condition is false.
14885 if (Op.getNode()->hasOneUse()) {
14886 SDNode *User = *Op.getNode()->use_begin();
14887 // Look for an unconditional branch following this conditional branch.
14888 // We need this because we need to reverse the successors in order
14889 // to implement FCMP_OEQ.
14890 if (User->getOpcode() == ISD::BR) {
14891 SDValue FalseBB = User->getOperand(1);
14893 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
14894 assert(NewBR == User);
14898 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
14899 Cond.getOperand(0), Cond.getOperand(1));
14900 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
14901 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
14902 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
14903 Chain, Dest, CC, Cmp);
14904 CC = DAG.getConstant(X86::COND_P, MVT::i8);
14909 } else if (Cond.getOpcode() == ISD::SETCC &&
14910 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETUNE) {
14911 // For FCMP_UNE, we can emit
14912 // two branches instead of an explicit AND instruction with a
14913 // separate test. However, we only do this if this block doesn't
14914 // have a fall-through edge, because this requires an explicit
14915 // jmp when the condition is false.
14916 if (Op.getNode()->hasOneUse()) {
14917 SDNode *User = *Op.getNode()->use_begin();
14918 // Look for an unconditional branch following this conditional branch.
14919 // We need this because we need to reverse the successors in order
14920 // to implement FCMP_UNE.
14921 if (User->getOpcode() == ISD::BR) {
14922 SDValue FalseBB = User->getOperand(1);
14924 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
14925 assert(NewBR == User);
14928 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
14929 Cond.getOperand(0), Cond.getOperand(1));
14930 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
14931 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
14932 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
14933 Chain, Dest, CC, Cmp);
14934 CC = DAG.getConstant(X86::COND_NP, MVT::i8);
14944 // Look pass the truncate if the high bits are known zero.
14945 if (isTruncWithZeroHighBitsInput(Cond, DAG))
14946 Cond = Cond.getOperand(0);
14948 // We know the result of AND is compared against zero. Try to match
14950 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
14951 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, dl, DAG);
14952 if (NewSetCC.getNode()) {
14953 CC = NewSetCC.getOperand(0);
14954 Cond = NewSetCC.getOperand(1);
14961 X86::CondCode X86Cond = Inverted ? X86::COND_E : X86::COND_NE;
14962 CC = DAG.getConstant(X86Cond, MVT::i8);
14963 Cond = EmitTest(Cond, X86Cond, dl, DAG);
14965 Cond = ConvertCmpIfNecessary(Cond, DAG);
14966 return DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
14967 Chain, Dest, CC, Cond);
14970 // Lower dynamic stack allocation to _alloca call for Cygwin/Mingw targets.
14971 // Calls to _alloca are needed to probe the stack when allocating more than 4k
14972 // bytes in one go. Touching the stack at 4K increments is necessary to ensure
14973 // that the guard pages used by the OS virtual memory manager are allocated in
14974 // correct sequence.
14976 X86TargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
14977 SelectionDAG &DAG) const {
14978 MachineFunction &MF = DAG.getMachineFunction();
14979 bool SplitStack = MF.shouldSplitStack();
14980 bool Lower = (Subtarget->isOSWindows() && !Subtarget->isTargetMacho()) ||
14985 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
14986 SDNode* Node = Op.getNode();
14988 unsigned SPReg = TLI.getStackPointerRegisterToSaveRestore();
14989 assert(SPReg && "Target cannot require DYNAMIC_STACKALLOC expansion and"
14990 " not tell us which reg is the stack pointer!");
14991 EVT VT = Node->getValueType(0);
14992 SDValue Tmp1 = SDValue(Node, 0);
14993 SDValue Tmp2 = SDValue(Node, 1);
14994 SDValue Tmp3 = Node->getOperand(2);
14995 SDValue Chain = Tmp1.getOperand(0);
14997 // Chain the dynamic stack allocation so that it doesn't modify the stack
14998 // pointer when other instructions are using the stack.
14999 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(0, true),
15002 SDValue Size = Tmp2.getOperand(1);
15003 SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, VT);
15004 Chain = SP.getValue(1);
15005 unsigned Align = cast<ConstantSDNode>(Tmp3)->getZExtValue();
15006 const TargetFrameLowering &TFI = *DAG.getSubtarget().getFrameLowering();
15007 unsigned StackAlign = TFI.getStackAlignment();
15008 Tmp1 = DAG.getNode(ISD::SUB, dl, VT, SP, Size); // Value
15009 if (Align > StackAlign)
15010 Tmp1 = DAG.getNode(ISD::AND, dl, VT, Tmp1,
15011 DAG.getConstant(-(uint64_t)Align, VT));
15012 Chain = DAG.getCopyToReg(Chain, dl, SPReg, Tmp1); // Output chain
15014 Tmp2 = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(0, true),
15015 DAG.getIntPtrConstant(0, true), SDValue(),
15018 SDValue Ops[2] = { Tmp1, Tmp2 };
15019 return DAG.getMergeValues(Ops, dl);
15023 SDValue Chain = Op.getOperand(0);
15024 SDValue Size = Op.getOperand(1);
15025 unsigned Align = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue();
15026 EVT VT = Op.getNode()->getValueType(0);
15028 bool Is64Bit = Subtarget->is64Bit();
15029 EVT SPTy = getPointerTy();
15032 MachineRegisterInfo &MRI = MF.getRegInfo();
15035 // The 64 bit implementation of segmented stacks needs to clobber both r10
15036 // r11. This makes it impossible to use it along with nested parameters.
15037 const Function *F = MF.getFunction();
15039 for (Function::const_arg_iterator I = F->arg_begin(), E = F->arg_end();
15041 if (I->hasNestAttr())
15042 report_fatal_error("Cannot use segmented stacks with functions that "
15043 "have nested arguments.");
15046 const TargetRegisterClass *AddrRegClass =
15047 getRegClassFor(getPointerTy());
15048 unsigned Vreg = MRI.createVirtualRegister(AddrRegClass);
15049 Chain = DAG.getCopyToReg(Chain, dl, Vreg, Size);
15050 SDValue Value = DAG.getNode(X86ISD::SEG_ALLOCA, dl, SPTy, Chain,
15051 DAG.getRegister(Vreg, SPTy));
15052 SDValue Ops1[2] = { Value, Chain };
15053 return DAG.getMergeValues(Ops1, dl);
15056 const unsigned Reg = (Subtarget->isTarget64BitLP64() ? X86::RAX : X86::EAX);
15058 Chain = DAG.getCopyToReg(Chain, dl, Reg, Size, Flag);
15059 Flag = Chain.getValue(1);
15060 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
15062 Chain = DAG.getNode(X86ISD::WIN_ALLOCA, dl, NodeTys, Chain, Flag);
15064 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
15065 DAG.getSubtarget().getRegisterInfo());
15066 unsigned SPReg = RegInfo->getStackRegister();
15067 SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, SPTy);
15068 Chain = SP.getValue(1);
15071 SP = DAG.getNode(ISD::AND, dl, VT, SP.getValue(0),
15072 DAG.getConstant(-(uint64_t)Align, VT));
15073 Chain = DAG.getCopyToReg(Chain, dl, SPReg, SP);
15076 SDValue Ops1[2] = { SP, Chain };
15077 return DAG.getMergeValues(Ops1, dl);
15081 SDValue X86TargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const {
15082 MachineFunction &MF = DAG.getMachineFunction();
15083 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
15085 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
15088 if (!Subtarget->is64Bit() || Subtarget->isTargetWin64()) {
15089 // vastart just stores the address of the VarArgsFrameIndex slot into the
15090 // memory location argument.
15091 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
15093 return DAG.getStore(Op.getOperand(0), DL, FR, Op.getOperand(1),
15094 MachinePointerInfo(SV), false, false, 0);
15098 // gp_offset (0 - 6 * 8)
15099 // fp_offset (48 - 48 + 8 * 16)
15100 // overflow_arg_area (point to parameters coming in memory).
15102 SmallVector<SDValue, 8> MemOps;
15103 SDValue FIN = Op.getOperand(1);
15105 SDValue Store = DAG.getStore(Op.getOperand(0), DL,
15106 DAG.getConstant(FuncInfo->getVarArgsGPOffset(),
15108 FIN, MachinePointerInfo(SV), false, false, 0);
15109 MemOps.push_back(Store);
15112 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
15113 FIN, DAG.getIntPtrConstant(4));
15114 Store = DAG.getStore(Op.getOperand(0), DL,
15115 DAG.getConstant(FuncInfo->getVarArgsFPOffset(),
15117 FIN, MachinePointerInfo(SV, 4), false, false, 0);
15118 MemOps.push_back(Store);
15120 // Store ptr to overflow_arg_area
15121 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
15122 FIN, DAG.getIntPtrConstant(4));
15123 SDValue OVFIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
15125 Store = DAG.getStore(Op.getOperand(0), DL, OVFIN, FIN,
15126 MachinePointerInfo(SV, 8),
15128 MemOps.push_back(Store);
15130 // Store ptr to reg_save_area.
15131 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
15132 FIN, DAG.getIntPtrConstant(8));
15133 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
15135 Store = DAG.getStore(Op.getOperand(0), DL, RSFIN, FIN,
15136 MachinePointerInfo(SV, 16), false, false, 0);
15137 MemOps.push_back(Store);
15138 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOps);
15141 SDValue X86TargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG) const {
15142 assert(Subtarget->is64Bit() &&
15143 "LowerVAARG only handles 64-bit va_arg!");
15144 assert((Subtarget->isTargetLinux() ||
15145 Subtarget->isTargetDarwin()) &&
15146 "Unhandled target in LowerVAARG");
15147 assert(Op.getNode()->getNumOperands() == 4);
15148 SDValue Chain = Op.getOperand(0);
15149 SDValue SrcPtr = Op.getOperand(1);
15150 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
15151 unsigned Align = Op.getConstantOperandVal(3);
15154 EVT ArgVT = Op.getNode()->getValueType(0);
15155 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
15156 uint32_t ArgSize = getDataLayout()->getTypeAllocSize(ArgTy);
15159 // Decide which area this value should be read from.
15160 // TODO: Implement the AMD64 ABI in its entirety. This simple
15161 // selection mechanism works only for the basic types.
15162 if (ArgVT == MVT::f80) {
15163 llvm_unreachable("va_arg for f80 not yet implemented");
15164 } else if (ArgVT.isFloatingPoint() && ArgSize <= 16 /*bytes*/) {
15165 ArgMode = 2; // Argument passed in XMM register. Use fp_offset.
15166 } else if (ArgVT.isInteger() && ArgSize <= 32 /*bytes*/) {
15167 ArgMode = 1; // Argument passed in GPR64 register(s). Use gp_offset.
15169 llvm_unreachable("Unhandled argument type in LowerVAARG");
15172 if (ArgMode == 2) {
15173 // Sanity Check: Make sure using fp_offset makes sense.
15174 assert(!DAG.getTarget().Options.UseSoftFloat &&
15175 !(DAG.getMachineFunction()
15176 .getFunction()->getAttributes()
15177 .hasAttribute(AttributeSet::FunctionIndex,
15178 Attribute::NoImplicitFloat)) &&
15179 Subtarget->hasSSE1());
15182 // Insert VAARG_64 node into the DAG
15183 // VAARG_64 returns two values: Variable Argument Address, Chain
15184 SmallVector<SDValue, 11> InstOps;
15185 InstOps.push_back(Chain);
15186 InstOps.push_back(SrcPtr);
15187 InstOps.push_back(DAG.getConstant(ArgSize, MVT::i32));
15188 InstOps.push_back(DAG.getConstant(ArgMode, MVT::i8));
15189 InstOps.push_back(DAG.getConstant(Align, MVT::i32));
15190 SDVTList VTs = DAG.getVTList(getPointerTy(), MVT::Other);
15191 SDValue VAARG = DAG.getMemIntrinsicNode(X86ISD::VAARG_64, dl,
15192 VTs, InstOps, MVT::i64,
15193 MachinePointerInfo(SV),
15195 /*Volatile=*/false,
15197 /*WriteMem=*/true);
15198 Chain = VAARG.getValue(1);
15200 // Load the next argument and return it
15201 return DAG.getLoad(ArgVT, dl,
15204 MachinePointerInfo(),
15205 false, false, false, 0);
15208 static SDValue LowerVACOPY(SDValue Op, const X86Subtarget *Subtarget,
15209 SelectionDAG &DAG) {
15210 // X86-64 va_list is a struct { i32, i32, i8*, i8* }.
15211 assert(Subtarget->is64Bit() && "This code only handles 64-bit va_copy!");
15212 SDValue Chain = Op.getOperand(0);
15213 SDValue DstPtr = Op.getOperand(1);
15214 SDValue SrcPtr = Op.getOperand(2);
15215 const Value *DstSV = cast<SrcValueSDNode>(Op.getOperand(3))->getValue();
15216 const Value *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
15219 return DAG.getMemcpy(Chain, DL, DstPtr, SrcPtr,
15220 DAG.getIntPtrConstant(24), 8, /*isVolatile*/false,
15222 MachinePointerInfo(DstSV), MachinePointerInfo(SrcSV));
15225 // getTargetVShiftByConstNode - Handle vector element shifts where the shift
15226 // amount is a constant. Takes immediate version of shift as input.
15227 static SDValue getTargetVShiftByConstNode(unsigned Opc, SDLoc dl, MVT VT,
15228 SDValue SrcOp, uint64_t ShiftAmt,
15229 SelectionDAG &DAG) {
15230 MVT ElementType = VT.getVectorElementType();
15232 // Fold this packed shift into its first operand if ShiftAmt is 0.
15236 // Check for ShiftAmt >= element width
15237 if (ShiftAmt >= ElementType.getSizeInBits()) {
15238 if (Opc == X86ISD::VSRAI)
15239 ShiftAmt = ElementType.getSizeInBits() - 1;
15241 return DAG.getConstant(0, VT);
15244 assert((Opc == X86ISD::VSHLI || Opc == X86ISD::VSRLI || Opc == X86ISD::VSRAI)
15245 && "Unknown target vector shift-by-constant node");
15247 // Fold this packed vector shift into a build vector if SrcOp is a
15248 // vector of Constants or UNDEFs, and SrcOp valuetype is the same as VT.
15249 if (VT == SrcOp.getSimpleValueType() &&
15250 ISD::isBuildVectorOfConstantSDNodes(SrcOp.getNode())) {
15251 SmallVector<SDValue, 8> Elts;
15252 unsigned NumElts = SrcOp->getNumOperands();
15253 ConstantSDNode *ND;
15256 default: llvm_unreachable(nullptr);
15257 case X86ISD::VSHLI:
15258 for (unsigned i=0; i!=NumElts; ++i) {
15259 SDValue CurrentOp = SrcOp->getOperand(i);
15260 if (CurrentOp->getOpcode() == ISD::UNDEF) {
15261 Elts.push_back(CurrentOp);
15264 ND = cast<ConstantSDNode>(CurrentOp);
15265 const APInt &C = ND->getAPIntValue();
15266 Elts.push_back(DAG.getConstant(C.shl(ShiftAmt), ElementType));
15269 case X86ISD::VSRLI:
15270 for (unsigned i=0; i!=NumElts; ++i) {
15271 SDValue CurrentOp = SrcOp->getOperand(i);
15272 if (CurrentOp->getOpcode() == ISD::UNDEF) {
15273 Elts.push_back(CurrentOp);
15276 ND = cast<ConstantSDNode>(CurrentOp);
15277 const APInt &C = ND->getAPIntValue();
15278 Elts.push_back(DAG.getConstant(C.lshr(ShiftAmt), ElementType));
15281 case X86ISD::VSRAI:
15282 for (unsigned i=0; i!=NumElts; ++i) {
15283 SDValue CurrentOp = SrcOp->getOperand(i);
15284 if (CurrentOp->getOpcode() == ISD::UNDEF) {
15285 Elts.push_back(CurrentOp);
15288 ND = cast<ConstantSDNode>(CurrentOp);
15289 const APInt &C = ND->getAPIntValue();
15290 Elts.push_back(DAG.getConstant(C.ashr(ShiftAmt), ElementType));
15295 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Elts);
15298 return DAG.getNode(Opc, dl, VT, SrcOp, DAG.getConstant(ShiftAmt, MVT::i8));
15301 // getTargetVShiftNode - Handle vector element shifts where the shift amount
15302 // may or may not be a constant. Takes immediate version of shift as input.
15303 static SDValue getTargetVShiftNode(unsigned Opc, SDLoc dl, MVT VT,
15304 SDValue SrcOp, SDValue ShAmt,
15305 SelectionDAG &DAG) {
15306 assert(ShAmt.getValueType() == MVT::i32 && "ShAmt is not i32");
15308 // Catch shift-by-constant.
15309 if (ConstantSDNode *CShAmt = dyn_cast<ConstantSDNode>(ShAmt))
15310 return getTargetVShiftByConstNode(Opc, dl, VT, SrcOp,
15311 CShAmt->getZExtValue(), DAG);
15313 // Change opcode to non-immediate version
15315 default: llvm_unreachable("Unknown target vector shift node");
15316 case X86ISD::VSHLI: Opc = X86ISD::VSHL; break;
15317 case X86ISD::VSRLI: Opc = X86ISD::VSRL; break;
15318 case X86ISD::VSRAI: Opc = X86ISD::VSRA; break;
15321 // Need to build a vector containing shift amount
15322 // Shift amount is 32-bits, but SSE instructions read 64-bit, so fill with 0
15325 ShOps[1] = DAG.getConstant(0, MVT::i32);
15326 ShOps[2] = ShOps[3] = DAG.getUNDEF(MVT::i32);
15327 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, ShOps);
15329 // The return type has to be a 128-bit type with the same element
15330 // type as the input type.
15331 MVT EltVT = VT.getVectorElementType();
15332 EVT ShVT = MVT::getVectorVT(EltVT, 128/EltVT.getSizeInBits());
15334 ShAmt = DAG.getNode(ISD::BITCAST, dl, ShVT, ShAmt);
15335 return DAG.getNode(Opc, dl, VT, SrcOp, ShAmt);
15338 /// \brief Return (vselect \p Mask, \p Op, \p PreservedSrc) along with the
15339 /// necessary casting for \p Mask when lowering masking intrinsics.
15340 static SDValue getVectorMaskingNode(SDValue Op, SDValue Mask,
15341 SDValue PreservedSrc, SelectionDAG &DAG) {
15342 EVT VT = Op.getValueType();
15343 EVT MaskVT = EVT::getVectorVT(*DAG.getContext(),
15344 MVT::i1, VT.getVectorNumElements());
15347 assert(MaskVT.isSimple() && "invalid mask type");
15348 return DAG.getNode(ISD::VSELECT, dl, VT,
15349 DAG.getNode(ISD::BITCAST, dl, MaskVT, Mask),
15353 static unsigned getOpcodeForFMAIntrinsic(unsigned IntNo) {
15355 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
15356 case Intrinsic::x86_fma_vfmadd_ps:
15357 case Intrinsic::x86_fma_vfmadd_pd:
15358 case Intrinsic::x86_fma_vfmadd_ps_256:
15359 case Intrinsic::x86_fma_vfmadd_pd_256:
15360 case Intrinsic::x86_fma_mask_vfmadd_ps_512:
15361 case Intrinsic::x86_fma_mask_vfmadd_pd_512:
15362 return X86ISD::FMADD;
15363 case Intrinsic::x86_fma_vfmsub_ps:
15364 case Intrinsic::x86_fma_vfmsub_pd:
15365 case Intrinsic::x86_fma_vfmsub_ps_256:
15366 case Intrinsic::x86_fma_vfmsub_pd_256:
15367 case Intrinsic::x86_fma_mask_vfmsub_ps_512:
15368 case Intrinsic::x86_fma_mask_vfmsub_pd_512:
15369 return X86ISD::FMSUB;
15370 case Intrinsic::x86_fma_vfnmadd_ps:
15371 case Intrinsic::x86_fma_vfnmadd_pd:
15372 case Intrinsic::x86_fma_vfnmadd_ps_256:
15373 case Intrinsic::x86_fma_vfnmadd_pd_256:
15374 case Intrinsic::x86_fma_mask_vfnmadd_ps_512:
15375 case Intrinsic::x86_fma_mask_vfnmadd_pd_512:
15376 return X86ISD::FNMADD;
15377 case Intrinsic::x86_fma_vfnmsub_ps:
15378 case Intrinsic::x86_fma_vfnmsub_pd:
15379 case Intrinsic::x86_fma_vfnmsub_ps_256:
15380 case Intrinsic::x86_fma_vfnmsub_pd_256:
15381 case Intrinsic::x86_fma_mask_vfnmsub_ps_512:
15382 case Intrinsic::x86_fma_mask_vfnmsub_pd_512:
15383 return X86ISD::FNMSUB;
15384 case Intrinsic::x86_fma_vfmaddsub_ps:
15385 case Intrinsic::x86_fma_vfmaddsub_pd:
15386 case Intrinsic::x86_fma_vfmaddsub_ps_256:
15387 case Intrinsic::x86_fma_vfmaddsub_pd_256:
15388 case Intrinsic::x86_fma_mask_vfmaddsub_ps_512:
15389 case Intrinsic::x86_fma_mask_vfmaddsub_pd_512:
15390 return X86ISD::FMADDSUB;
15391 case Intrinsic::x86_fma_vfmsubadd_ps:
15392 case Intrinsic::x86_fma_vfmsubadd_pd:
15393 case Intrinsic::x86_fma_vfmsubadd_ps_256:
15394 case Intrinsic::x86_fma_vfmsubadd_pd_256:
15395 case Intrinsic::x86_fma_mask_vfmsubadd_ps_512:
15396 case Intrinsic::x86_fma_mask_vfmsubadd_pd_512:
15397 return X86ISD::FMSUBADD;
15401 static SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) {
15403 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
15405 const IntrinsicData* IntrData = getIntrinsicWithoutChain(IntNo);
15407 switch(IntrData->Type) {
15408 case INTR_TYPE_1OP:
15409 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1));
15410 case INTR_TYPE_2OP:
15411 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1),
15413 case INTR_TYPE_3OP:
15414 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1),
15415 Op.getOperand(2), Op.getOperand(3));
15416 case COMI: { // Comparison intrinsics
15417 ISD::CondCode CC = (ISD::CondCode)IntrData->Opc1;
15418 SDValue LHS = Op.getOperand(1);
15419 SDValue RHS = Op.getOperand(2);
15420 unsigned X86CC = TranslateX86CC(CC, true, LHS, RHS, DAG);
15421 assert(X86CC != X86::COND_INVALID && "Unexpected illegal condition!");
15422 SDValue Cond = DAG.getNode(IntrData->Opc0, dl, MVT::i32, LHS, RHS);
15423 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
15424 DAG.getConstant(X86CC, MVT::i8), Cond);
15425 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
15428 return getTargetVShiftNode(IntrData->Opc0, dl, Op.getSimpleValueType(),
15429 Op.getOperand(1), Op.getOperand(2), DAG);
15436 default: return SDValue(); // Don't custom lower most intrinsics.
15438 // Arithmetic intrinsics.
15439 case Intrinsic::x86_sse2_pmulu_dq:
15440 case Intrinsic::x86_avx2_pmulu_dq:
15441 return DAG.getNode(X86ISD::PMULUDQ, dl, Op.getValueType(),
15442 Op.getOperand(1), Op.getOperand(2));
15444 case Intrinsic::x86_sse41_pmuldq:
15445 case Intrinsic::x86_avx2_pmul_dq:
15446 return DAG.getNode(X86ISD::PMULDQ, dl, Op.getValueType(),
15447 Op.getOperand(1), Op.getOperand(2));
15449 case Intrinsic::x86_sse2_pmulhu_w:
15450 case Intrinsic::x86_avx2_pmulhu_w:
15451 return DAG.getNode(ISD::MULHU, dl, Op.getValueType(),
15452 Op.getOperand(1), Op.getOperand(2));
15454 case Intrinsic::x86_sse2_pmulh_w:
15455 case Intrinsic::x86_avx2_pmulh_w:
15456 return DAG.getNode(ISD::MULHS, dl, Op.getValueType(),
15457 Op.getOperand(1), Op.getOperand(2));
15459 // SSE/SSE2/AVX floating point max/min intrinsics.
15460 case Intrinsic::x86_sse_max_ps:
15461 case Intrinsic::x86_sse2_max_pd:
15462 case Intrinsic::x86_avx_max_ps_256:
15463 case Intrinsic::x86_avx_max_pd_256:
15464 case Intrinsic::x86_sse_min_ps:
15465 case Intrinsic::x86_sse2_min_pd:
15466 case Intrinsic::x86_avx_min_ps_256:
15467 case Intrinsic::x86_avx_min_pd_256: {
15470 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
15471 case Intrinsic::x86_sse_max_ps:
15472 case Intrinsic::x86_sse2_max_pd:
15473 case Intrinsic::x86_avx_max_ps_256:
15474 case Intrinsic::x86_avx_max_pd_256:
15475 Opcode = X86ISD::FMAX;
15477 case Intrinsic::x86_sse_min_ps:
15478 case Intrinsic::x86_sse2_min_pd:
15479 case Intrinsic::x86_avx_min_ps_256:
15480 case Intrinsic::x86_avx_min_pd_256:
15481 Opcode = X86ISD::FMIN;
15484 return DAG.getNode(Opcode, dl, Op.getValueType(),
15485 Op.getOperand(1), Op.getOperand(2));
15488 // AVX2 variable shift intrinsics
15489 case Intrinsic::x86_avx2_psllv_d:
15490 case Intrinsic::x86_avx2_psllv_q:
15491 case Intrinsic::x86_avx2_psllv_d_256:
15492 case Intrinsic::x86_avx2_psllv_q_256:
15493 case Intrinsic::x86_avx2_psrlv_d:
15494 case Intrinsic::x86_avx2_psrlv_q:
15495 case Intrinsic::x86_avx2_psrlv_d_256:
15496 case Intrinsic::x86_avx2_psrlv_q_256:
15497 case Intrinsic::x86_avx2_psrav_d:
15498 case Intrinsic::x86_avx2_psrav_d_256: {
15501 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
15502 case Intrinsic::x86_avx2_psllv_d:
15503 case Intrinsic::x86_avx2_psllv_q:
15504 case Intrinsic::x86_avx2_psllv_d_256:
15505 case Intrinsic::x86_avx2_psllv_q_256:
15508 case Intrinsic::x86_avx2_psrlv_d:
15509 case Intrinsic::x86_avx2_psrlv_q:
15510 case Intrinsic::x86_avx2_psrlv_d_256:
15511 case Intrinsic::x86_avx2_psrlv_q_256:
15514 case Intrinsic::x86_avx2_psrav_d:
15515 case Intrinsic::x86_avx2_psrav_d_256:
15519 return DAG.getNode(Opcode, dl, Op.getValueType(),
15520 Op.getOperand(1), Op.getOperand(2));
15523 case Intrinsic::x86_sse2_packssdw_128:
15524 case Intrinsic::x86_sse2_packsswb_128:
15525 case Intrinsic::x86_avx2_packssdw:
15526 case Intrinsic::x86_avx2_packsswb:
15527 return DAG.getNode(X86ISD::PACKSS, dl, Op.getValueType(),
15528 Op.getOperand(1), Op.getOperand(2));
15530 case Intrinsic::x86_sse2_packuswb_128:
15531 case Intrinsic::x86_sse41_packusdw:
15532 case Intrinsic::x86_avx2_packuswb:
15533 case Intrinsic::x86_avx2_packusdw:
15534 return DAG.getNode(X86ISD::PACKUS, dl, Op.getValueType(),
15535 Op.getOperand(1), Op.getOperand(2));
15537 case Intrinsic::x86_ssse3_pshuf_b_128:
15538 case Intrinsic::x86_avx2_pshuf_b:
15539 return DAG.getNode(X86ISD::PSHUFB, dl, Op.getValueType(),
15540 Op.getOperand(1), Op.getOperand(2));
15542 case Intrinsic::x86_sse2_pshuf_d:
15543 return DAG.getNode(X86ISD::PSHUFD, dl, Op.getValueType(),
15544 Op.getOperand(1), Op.getOperand(2));
15546 case Intrinsic::x86_sse2_pshufl_w:
15547 return DAG.getNode(X86ISD::PSHUFLW, dl, Op.getValueType(),
15548 Op.getOperand(1), Op.getOperand(2));
15550 case Intrinsic::x86_sse2_pshufh_w:
15551 return DAG.getNode(X86ISD::PSHUFHW, dl, Op.getValueType(),
15552 Op.getOperand(1), Op.getOperand(2));
15554 case Intrinsic::x86_ssse3_psign_b_128:
15555 case Intrinsic::x86_ssse3_psign_w_128:
15556 case Intrinsic::x86_ssse3_psign_d_128:
15557 case Intrinsic::x86_avx2_psign_b:
15558 case Intrinsic::x86_avx2_psign_w:
15559 case Intrinsic::x86_avx2_psign_d:
15560 return DAG.getNode(X86ISD::PSIGN, dl, Op.getValueType(),
15561 Op.getOperand(1), Op.getOperand(2));
15563 case Intrinsic::x86_avx2_permd:
15564 case Intrinsic::x86_avx2_permps:
15565 // Operands intentionally swapped. Mask is last operand to intrinsic,
15566 // but second operand for node/instruction.
15567 return DAG.getNode(X86ISD::VPERMV, dl, Op.getValueType(),
15568 Op.getOperand(2), Op.getOperand(1));
15570 case Intrinsic::x86_avx512_mask_valign_q_512:
15571 case Intrinsic::x86_avx512_mask_valign_d_512:
15572 // Vector source operands are swapped.
15573 return getVectorMaskingNode(DAG.getNode(X86ISD::VALIGN, dl,
15574 Op.getValueType(), Op.getOperand(2),
15577 Op.getOperand(5), Op.getOperand(4), DAG);
15579 // ptest and testp intrinsics. The intrinsic these come from are designed to
15580 // return an integer value, not just an instruction so lower it to the ptest
15581 // or testp pattern and a setcc for the result.
15582 case Intrinsic::x86_sse41_ptestz:
15583 case Intrinsic::x86_sse41_ptestc:
15584 case Intrinsic::x86_sse41_ptestnzc:
15585 case Intrinsic::x86_avx_ptestz_256:
15586 case Intrinsic::x86_avx_ptestc_256:
15587 case Intrinsic::x86_avx_ptestnzc_256:
15588 case Intrinsic::x86_avx_vtestz_ps:
15589 case Intrinsic::x86_avx_vtestc_ps:
15590 case Intrinsic::x86_avx_vtestnzc_ps:
15591 case Intrinsic::x86_avx_vtestz_pd:
15592 case Intrinsic::x86_avx_vtestc_pd:
15593 case Intrinsic::x86_avx_vtestnzc_pd:
15594 case Intrinsic::x86_avx_vtestz_ps_256:
15595 case Intrinsic::x86_avx_vtestc_ps_256:
15596 case Intrinsic::x86_avx_vtestnzc_ps_256:
15597 case Intrinsic::x86_avx_vtestz_pd_256:
15598 case Intrinsic::x86_avx_vtestc_pd_256:
15599 case Intrinsic::x86_avx_vtestnzc_pd_256: {
15600 bool IsTestPacked = false;
15603 default: llvm_unreachable("Bad fallthrough in Intrinsic lowering.");
15604 case Intrinsic::x86_avx_vtestz_ps:
15605 case Intrinsic::x86_avx_vtestz_pd:
15606 case Intrinsic::x86_avx_vtestz_ps_256:
15607 case Intrinsic::x86_avx_vtestz_pd_256:
15608 IsTestPacked = true; // Fallthrough
15609 case Intrinsic::x86_sse41_ptestz:
15610 case Intrinsic::x86_avx_ptestz_256:
15612 X86CC = X86::COND_E;
15614 case Intrinsic::x86_avx_vtestc_ps:
15615 case Intrinsic::x86_avx_vtestc_pd:
15616 case Intrinsic::x86_avx_vtestc_ps_256:
15617 case Intrinsic::x86_avx_vtestc_pd_256:
15618 IsTestPacked = true; // Fallthrough
15619 case Intrinsic::x86_sse41_ptestc:
15620 case Intrinsic::x86_avx_ptestc_256:
15622 X86CC = X86::COND_B;
15624 case Intrinsic::x86_avx_vtestnzc_ps:
15625 case Intrinsic::x86_avx_vtestnzc_pd:
15626 case Intrinsic::x86_avx_vtestnzc_ps_256:
15627 case Intrinsic::x86_avx_vtestnzc_pd_256:
15628 IsTestPacked = true; // Fallthrough
15629 case Intrinsic::x86_sse41_ptestnzc:
15630 case Intrinsic::x86_avx_ptestnzc_256:
15632 X86CC = X86::COND_A;
15636 SDValue LHS = Op.getOperand(1);
15637 SDValue RHS = Op.getOperand(2);
15638 unsigned TestOpc = IsTestPacked ? X86ISD::TESTP : X86ISD::PTEST;
15639 SDValue Test = DAG.getNode(TestOpc, dl, MVT::i32, LHS, RHS);
15640 SDValue CC = DAG.getConstant(X86CC, MVT::i8);
15641 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8, CC, Test);
15642 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
15644 case Intrinsic::x86_avx512_kortestz_w:
15645 case Intrinsic::x86_avx512_kortestc_w: {
15646 unsigned X86CC = (IntNo == Intrinsic::x86_avx512_kortestz_w)? X86::COND_E: X86::COND_B;
15647 SDValue LHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i1, Op.getOperand(1));
15648 SDValue RHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i1, Op.getOperand(2));
15649 SDValue CC = DAG.getConstant(X86CC, MVT::i8);
15650 SDValue Test = DAG.getNode(X86ISD::KORTEST, dl, MVT::i32, LHS, RHS);
15651 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i1, CC, Test);
15652 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
15655 case Intrinsic::x86_sse42_pcmpistria128:
15656 case Intrinsic::x86_sse42_pcmpestria128:
15657 case Intrinsic::x86_sse42_pcmpistric128:
15658 case Intrinsic::x86_sse42_pcmpestric128:
15659 case Intrinsic::x86_sse42_pcmpistrio128:
15660 case Intrinsic::x86_sse42_pcmpestrio128:
15661 case Intrinsic::x86_sse42_pcmpistris128:
15662 case Intrinsic::x86_sse42_pcmpestris128:
15663 case Intrinsic::x86_sse42_pcmpistriz128:
15664 case Intrinsic::x86_sse42_pcmpestriz128: {
15668 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
15669 case Intrinsic::x86_sse42_pcmpistria128:
15670 Opcode = X86ISD::PCMPISTRI;
15671 X86CC = X86::COND_A;
15673 case Intrinsic::x86_sse42_pcmpestria128:
15674 Opcode = X86ISD::PCMPESTRI;
15675 X86CC = X86::COND_A;
15677 case Intrinsic::x86_sse42_pcmpistric128:
15678 Opcode = X86ISD::PCMPISTRI;
15679 X86CC = X86::COND_B;
15681 case Intrinsic::x86_sse42_pcmpestric128:
15682 Opcode = X86ISD::PCMPESTRI;
15683 X86CC = X86::COND_B;
15685 case Intrinsic::x86_sse42_pcmpistrio128:
15686 Opcode = X86ISD::PCMPISTRI;
15687 X86CC = X86::COND_O;
15689 case Intrinsic::x86_sse42_pcmpestrio128:
15690 Opcode = X86ISD::PCMPESTRI;
15691 X86CC = X86::COND_O;
15693 case Intrinsic::x86_sse42_pcmpistris128:
15694 Opcode = X86ISD::PCMPISTRI;
15695 X86CC = X86::COND_S;
15697 case Intrinsic::x86_sse42_pcmpestris128:
15698 Opcode = X86ISD::PCMPESTRI;
15699 X86CC = X86::COND_S;
15701 case Intrinsic::x86_sse42_pcmpistriz128:
15702 Opcode = X86ISD::PCMPISTRI;
15703 X86CC = X86::COND_E;
15705 case Intrinsic::x86_sse42_pcmpestriz128:
15706 Opcode = X86ISD::PCMPESTRI;
15707 X86CC = X86::COND_E;
15710 SmallVector<SDValue, 5> NewOps(Op->op_begin()+1, Op->op_end());
15711 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
15712 SDValue PCMP = DAG.getNode(Opcode, dl, VTs, NewOps);
15713 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
15714 DAG.getConstant(X86CC, MVT::i8),
15715 SDValue(PCMP.getNode(), 1));
15716 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
15719 case Intrinsic::x86_sse42_pcmpistri128:
15720 case Intrinsic::x86_sse42_pcmpestri128: {
15722 if (IntNo == Intrinsic::x86_sse42_pcmpistri128)
15723 Opcode = X86ISD::PCMPISTRI;
15725 Opcode = X86ISD::PCMPESTRI;
15727 SmallVector<SDValue, 5> NewOps(Op->op_begin()+1, Op->op_end());
15728 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
15729 return DAG.getNode(Opcode, dl, VTs, NewOps);
15732 case Intrinsic::x86_fma_mask_vfmadd_ps_512:
15733 case Intrinsic::x86_fma_mask_vfmadd_pd_512:
15734 case Intrinsic::x86_fma_mask_vfmsub_ps_512:
15735 case Intrinsic::x86_fma_mask_vfmsub_pd_512:
15736 case Intrinsic::x86_fma_mask_vfnmadd_ps_512:
15737 case Intrinsic::x86_fma_mask_vfnmadd_pd_512:
15738 case Intrinsic::x86_fma_mask_vfnmsub_ps_512:
15739 case Intrinsic::x86_fma_mask_vfnmsub_pd_512:
15740 case Intrinsic::x86_fma_mask_vfmaddsub_ps_512:
15741 case Intrinsic::x86_fma_mask_vfmaddsub_pd_512:
15742 case Intrinsic::x86_fma_mask_vfmsubadd_ps_512:
15743 case Intrinsic::x86_fma_mask_vfmsubadd_pd_512: {
15744 auto *SAE = cast<ConstantSDNode>(Op.getOperand(5));
15745 if (SAE->getZExtValue() == X86::STATIC_ROUNDING::CUR_DIRECTION)
15746 return getVectorMaskingNode(DAG.getNode(getOpcodeForFMAIntrinsic(IntNo),
15747 dl, Op.getValueType(),
15751 Op.getOperand(4), Op.getOperand(1), DAG);
15756 case Intrinsic::x86_fma_vfmadd_ps:
15757 case Intrinsic::x86_fma_vfmadd_pd:
15758 case Intrinsic::x86_fma_vfmsub_ps:
15759 case Intrinsic::x86_fma_vfmsub_pd:
15760 case Intrinsic::x86_fma_vfnmadd_ps:
15761 case Intrinsic::x86_fma_vfnmadd_pd:
15762 case Intrinsic::x86_fma_vfnmsub_ps:
15763 case Intrinsic::x86_fma_vfnmsub_pd:
15764 case Intrinsic::x86_fma_vfmaddsub_ps:
15765 case Intrinsic::x86_fma_vfmaddsub_pd:
15766 case Intrinsic::x86_fma_vfmsubadd_ps:
15767 case Intrinsic::x86_fma_vfmsubadd_pd:
15768 case Intrinsic::x86_fma_vfmadd_ps_256:
15769 case Intrinsic::x86_fma_vfmadd_pd_256:
15770 case Intrinsic::x86_fma_vfmsub_ps_256:
15771 case Intrinsic::x86_fma_vfmsub_pd_256:
15772 case Intrinsic::x86_fma_vfnmadd_ps_256:
15773 case Intrinsic::x86_fma_vfnmadd_pd_256:
15774 case Intrinsic::x86_fma_vfnmsub_ps_256:
15775 case Intrinsic::x86_fma_vfnmsub_pd_256:
15776 case Intrinsic::x86_fma_vfmaddsub_ps_256:
15777 case Intrinsic::x86_fma_vfmaddsub_pd_256:
15778 case Intrinsic::x86_fma_vfmsubadd_ps_256:
15779 case Intrinsic::x86_fma_vfmsubadd_pd_256:
15780 return DAG.getNode(getOpcodeForFMAIntrinsic(IntNo), dl, Op.getValueType(),
15781 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
15785 static SDValue getGatherNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
15786 SDValue Src, SDValue Mask, SDValue Base,
15787 SDValue Index, SDValue ScaleOp, SDValue Chain,
15788 const X86Subtarget * Subtarget) {
15790 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
15791 assert(C && "Invalid scale type");
15792 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), MVT::i8);
15793 EVT MaskVT = MVT::getVectorVT(MVT::i1,
15794 Index.getSimpleValueType().getVectorNumElements());
15796 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(Mask);
15798 MaskInReg = DAG.getTargetConstant(MaskC->getSExtValue(), MaskVT);
15800 MaskInReg = DAG.getNode(ISD::BITCAST, dl, MaskVT, Mask);
15801 SDVTList VTs = DAG.getVTList(Op.getValueType(), MaskVT, MVT::Other);
15802 SDValue Disp = DAG.getTargetConstant(0, MVT::i32);
15803 SDValue Segment = DAG.getRegister(0, MVT::i32);
15804 if (Src.getOpcode() == ISD::UNDEF)
15805 Src = getZeroVector(Op.getValueType(), Subtarget, DAG, dl);
15806 SDValue Ops[] = {Src, MaskInReg, Base, Scale, Index, Disp, Segment, Chain};
15807 SDNode *Res = DAG.getMachineNode(Opc, dl, VTs, Ops);
15808 SDValue RetOps[] = { SDValue(Res, 0), SDValue(Res, 2) };
15809 return DAG.getMergeValues(RetOps, dl);
15812 static SDValue getScatterNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
15813 SDValue Src, SDValue Mask, SDValue Base,
15814 SDValue Index, SDValue ScaleOp, SDValue Chain) {
15816 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
15817 assert(C && "Invalid scale type");
15818 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), MVT::i8);
15819 SDValue Disp = DAG.getTargetConstant(0, MVT::i32);
15820 SDValue Segment = DAG.getRegister(0, MVT::i32);
15821 EVT MaskVT = MVT::getVectorVT(MVT::i1,
15822 Index.getSimpleValueType().getVectorNumElements());
15824 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(Mask);
15826 MaskInReg = DAG.getTargetConstant(MaskC->getSExtValue(), MaskVT);
15828 MaskInReg = DAG.getNode(ISD::BITCAST, dl, MaskVT, Mask);
15829 SDVTList VTs = DAG.getVTList(MaskVT, MVT::Other);
15830 SDValue Ops[] = {Base, Scale, Index, Disp, Segment, MaskInReg, Src, Chain};
15831 SDNode *Res = DAG.getMachineNode(Opc, dl, VTs, Ops);
15832 return SDValue(Res, 1);
15835 static SDValue getPrefetchNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
15836 SDValue Mask, SDValue Base, SDValue Index,
15837 SDValue ScaleOp, SDValue Chain) {
15839 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
15840 assert(C && "Invalid scale type");
15841 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), MVT::i8);
15842 SDValue Disp = DAG.getTargetConstant(0, MVT::i32);
15843 SDValue Segment = DAG.getRegister(0, MVT::i32);
15845 MVT::getVectorVT(MVT::i1, Index.getSimpleValueType().getVectorNumElements());
15847 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(Mask);
15849 MaskInReg = DAG.getTargetConstant(MaskC->getSExtValue(), MaskVT);
15851 MaskInReg = DAG.getNode(ISD::BITCAST, dl, MaskVT, Mask);
15852 //SDVTList VTs = DAG.getVTList(MVT::Other);
15853 SDValue Ops[] = {MaskInReg, Base, Scale, Index, Disp, Segment, Chain};
15854 SDNode *Res = DAG.getMachineNode(Opc, dl, MVT::Other, Ops);
15855 return SDValue(Res, 0);
15858 // getReadPerformanceCounter - Handles the lowering of builtin intrinsics that
15859 // read performance monitor counters (x86_rdpmc).
15860 static void getReadPerformanceCounter(SDNode *N, SDLoc DL,
15861 SelectionDAG &DAG, const X86Subtarget *Subtarget,
15862 SmallVectorImpl<SDValue> &Results) {
15863 assert(N->getNumOperands() == 3 && "Unexpected number of operands!");
15864 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
15867 // The ECX register is used to select the index of the performance counter
15869 SDValue Chain = DAG.getCopyToReg(N->getOperand(0), DL, X86::ECX,
15871 SDValue rd = DAG.getNode(X86ISD::RDPMC_DAG, DL, Tys, Chain);
15873 // Reads the content of a 64-bit performance counter and returns it in the
15874 // registers EDX:EAX.
15875 if (Subtarget->is64Bit()) {
15876 LO = DAG.getCopyFromReg(rd, DL, X86::RAX, MVT::i64, rd.getValue(1));
15877 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::RDX, MVT::i64,
15880 LO = DAG.getCopyFromReg(rd, DL, X86::EAX, MVT::i32, rd.getValue(1));
15881 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::EDX, MVT::i32,
15884 Chain = HI.getValue(1);
15886 if (Subtarget->is64Bit()) {
15887 // The EAX register is loaded with the low-order 32 bits. The EDX register
15888 // is loaded with the supported high-order bits of the counter.
15889 SDValue Tmp = DAG.getNode(ISD::SHL, DL, MVT::i64, HI,
15890 DAG.getConstant(32, MVT::i8));
15891 Results.push_back(DAG.getNode(ISD::OR, DL, MVT::i64, LO, Tmp));
15892 Results.push_back(Chain);
15896 // Use a buildpair to merge the two 32-bit values into a 64-bit one.
15897 SDValue Ops[] = { LO, HI };
15898 SDValue Pair = DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops);
15899 Results.push_back(Pair);
15900 Results.push_back(Chain);
15903 // getReadTimeStampCounter - Handles the lowering of builtin intrinsics that
15904 // read the time stamp counter (x86_rdtsc and x86_rdtscp). This function is
15905 // also used to custom lower READCYCLECOUNTER nodes.
15906 static void getReadTimeStampCounter(SDNode *N, SDLoc DL, unsigned Opcode,
15907 SelectionDAG &DAG, const X86Subtarget *Subtarget,
15908 SmallVectorImpl<SDValue> &Results) {
15909 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
15910 SDValue rd = DAG.getNode(Opcode, DL, Tys, N->getOperand(0));
15913 // The processor's time-stamp counter (a 64-bit MSR) is stored into the
15914 // EDX:EAX registers. EDX is loaded with the high-order 32 bits of the MSR
15915 // and the EAX register is loaded with the low-order 32 bits.
15916 if (Subtarget->is64Bit()) {
15917 LO = DAG.getCopyFromReg(rd, DL, X86::RAX, MVT::i64, rd.getValue(1));
15918 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::RDX, MVT::i64,
15921 LO = DAG.getCopyFromReg(rd, DL, X86::EAX, MVT::i32, rd.getValue(1));
15922 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::EDX, MVT::i32,
15925 SDValue Chain = HI.getValue(1);
15927 if (Opcode == X86ISD::RDTSCP_DAG) {
15928 assert(N->getNumOperands() == 3 && "Unexpected number of operands!");
15930 // Instruction RDTSCP loads the IA32:TSC_AUX_MSR (address C000_0103H) into
15931 // the ECX register. Add 'ecx' explicitly to the chain.
15932 SDValue ecx = DAG.getCopyFromReg(Chain, DL, X86::ECX, MVT::i32,
15934 // Explicitly store the content of ECX at the location passed in input
15935 // to the 'rdtscp' intrinsic.
15936 Chain = DAG.getStore(ecx.getValue(1), DL, ecx, N->getOperand(2),
15937 MachinePointerInfo(), false, false, 0);
15940 if (Subtarget->is64Bit()) {
15941 // The EDX register is loaded with the high-order 32 bits of the MSR, and
15942 // the EAX register is loaded with the low-order 32 bits.
15943 SDValue Tmp = DAG.getNode(ISD::SHL, DL, MVT::i64, HI,
15944 DAG.getConstant(32, MVT::i8));
15945 Results.push_back(DAG.getNode(ISD::OR, DL, MVT::i64, LO, Tmp));
15946 Results.push_back(Chain);
15950 // Use a buildpair to merge the two 32-bit values into a 64-bit one.
15951 SDValue Ops[] = { LO, HI };
15952 SDValue Pair = DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops);
15953 Results.push_back(Pair);
15954 Results.push_back(Chain);
15957 static SDValue LowerREADCYCLECOUNTER(SDValue Op, const X86Subtarget *Subtarget,
15958 SelectionDAG &DAG) {
15959 SmallVector<SDValue, 2> Results;
15961 getReadTimeStampCounter(Op.getNode(), DL, X86ISD::RDTSC_DAG, DAG, Subtarget,
15963 return DAG.getMergeValues(Results, DL);
15967 static SDValue LowerINTRINSIC_W_CHAIN(SDValue Op, const X86Subtarget *Subtarget,
15968 SelectionDAG &DAG) {
15969 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
15971 const IntrinsicData* IntrData = getIntrinsicWithChain(IntNo);
15976 switch(IntrData->Type) {
15978 llvm_unreachable("Unknown Intrinsic Type");
15982 // Emit the node with the right value type.
15983 SDVTList VTs = DAG.getVTList(Op->getValueType(0), MVT::Glue, MVT::Other);
15984 SDValue Result = DAG.getNode(IntrData->Opc0, dl, VTs, Op.getOperand(0));
15986 // If the value returned by RDRAND/RDSEED was valid (CF=1), return 1.
15987 // Otherwise return the value from Rand, which is always 0, casted to i32.
15988 SDValue Ops[] = { DAG.getZExtOrTrunc(Result, dl, Op->getValueType(1)),
15989 DAG.getConstant(1, Op->getValueType(1)),
15990 DAG.getConstant(X86::COND_B, MVT::i32),
15991 SDValue(Result.getNode(), 1) };
15992 SDValue isValid = DAG.getNode(X86ISD::CMOV, dl,
15993 DAG.getVTList(Op->getValueType(1), MVT::Glue),
15996 // Return { result, isValid, chain }.
15997 return DAG.getNode(ISD::MERGE_VALUES, dl, Op->getVTList(), Result, isValid,
15998 SDValue(Result.getNode(), 2));
16001 //gather(v1, mask, index, base, scale);
16002 SDValue Chain = Op.getOperand(0);
16003 SDValue Src = Op.getOperand(2);
16004 SDValue Base = Op.getOperand(3);
16005 SDValue Index = Op.getOperand(4);
16006 SDValue Mask = Op.getOperand(5);
16007 SDValue Scale = Op.getOperand(6);
16008 return getGatherNode(IntrData->Opc0, Op, DAG, Src, Mask, Base, Index, Scale, Chain,
16012 //scatter(base, mask, index, v1, scale);
16013 SDValue Chain = Op.getOperand(0);
16014 SDValue Base = Op.getOperand(2);
16015 SDValue Mask = Op.getOperand(3);
16016 SDValue Index = Op.getOperand(4);
16017 SDValue Src = Op.getOperand(5);
16018 SDValue Scale = Op.getOperand(6);
16019 return getScatterNode(IntrData->Opc0, Op, DAG, Src, Mask, Base, Index, Scale, Chain);
16022 SDValue Hint = Op.getOperand(6);
16024 if (dyn_cast<ConstantSDNode> (Hint) == nullptr ||
16025 (HintVal = dyn_cast<ConstantSDNode> (Hint)->getZExtValue()) > 1)
16026 llvm_unreachable("Wrong prefetch hint in intrinsic: should be 0 or 1");
16027 unsigned Opcode = (HintVal ? IntrData->Opc1 : IntrData->Opc0);
16028 SDValue Chain = Op.getOperand(0);
16029 SDValue Mask = Op.getOperand(2);
16030 SDValue Index = Op.getOperand(3);
16031 SDValue Base = Op.getOperand(4);
16032 SDValue Scale = Op.getOperand(5);
16033 return getPrefetchNode(Opcode, Op, DAG, Mask, Base, Index, Scale, Chain);
16035 // Read Time Stamp Counter (RDTSC) and Processor ID (RDTSCP).
16037 SmallVector<SDValue, 2> Results;
16038 getReadTimeStampCounter(Op.getNode(), dl, IntrData->Opc0, DAG, Subtarget, Results);
16039 return DAG.getMergeValues(Results, dl);
16041 // Read Performance Monitoring Counters.
16043 SmallVector<SDValue, 2> Results;
16044 getReadPerformanceCounter(Op.getNode(), dl, DAG, Subtarget, Results);
16045 return DAG.getMergeValues(Results, dl);
16047 // XTEST intrinsics.
16049 SDVTList VTs = DAG.getVTList(Op->getValueType(0), MVT::Other);
16050 SDValue InTrans = DAG.getNode(IntrData->Opc0, dl, VTs, Op.getOperand(0));
16051 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
16052 DAG.getConstant(X86::COND_NE, MVT::i8),
16054 SDValue Ret = DAG.getNode(ISD::ZERO_EXTEND, dl, Op->getValueType(0), SetCC);
16055 return DAG.getNode(ISD::MERGE_VALUES, dl, Op->getVTList(),
16056 Ret, SDValue(InTrans.getNode(), 1));
16060 SmallVector<SDValue, 2> Results;
16061 SDVTList CFVTs = DAG.getVTList(Op->getValueType(0), MVT::Other);
16062 SDVTList VTs = DAG.getVTList(Op.getOperand(3)->getValueType(0), MVT::Other);
16063 SDValue GenCF = DAG.getNode(X86ISD::ADD, dl, CFVTs, Op.getOperand(2),
16064 DAG.getConstant(-1, MVT::i8));
16065 SDValue Res = DAG.getNode(IntrData->Opc0, dl, VTs, Op.getOperand(3),
16066 Op.getOperand(4), GenCF.getValue(1));
16067 SDValue Store = DAG.getStore(Op.getOperand(0), dl, Res.getValue(0),
16068 Op.getOperand(5), MachinePointerInfo(),
16070 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
16071 DAG.getConstant(X86::COND_B, MVT::i8),
16073 Results.push_back(SetCC);
16074 Results.push_back(Store);
16075 return DAG.getMergeValues(Results, dl);
16080 SDValue X86TargetLowering::LowerRETURNADDR(SDValue Op,
16081 SelectionDAG &DAG) const {
16082 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
16083 MFI->setReturnAddressIsTaken(true);
16085 if (verifyReturnAddressArgumentIsConstant(Op, DAG))
16088 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
16090 EVT PtrVT = getPointerTy();
16093 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
16094 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
16095 DAG.getSubtarget().getRegisterInfo());
16096 SDValue Offset = DAG.getConstant(RegInfo->getSlotSize(), PtrVT);
16097 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
16098 DAG.getNode(ISD::ADD, dl, PtrVT,
16099 FrameAddr, Offset),
16100 MachinePointerInfo(), false, false, false, 0);
16103 // Just load the return address.
16104 SDValue RetAddrFI = getReturnAddressFrameIndex(DAG);
16105 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
16106 RetAddrFI, MachinePointerInfo(), false, false, false, 0);
16109 SDValue X86TargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {
16110 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
16111 MFI->setFrameAddressIsTaken(true);
16113 EVT VT = Op.getValueType();
16114 SDLoc dl(Op); // FIXME probably not meaningful
16115 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
16116 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
16117 DAG.getSubtarget().getRegisterInfo());
16118 unsigned FrameReg = RegInfo->getFrameRegister(DAG.getMachineFunction());
16119 assert(((FrameReg == X86::RBP && VT == MVT::i64) ||
16120 (FrameReg == X86::EBP && VT == MVT::i32)) &&
16121 "Invalid Frame Register!");
16122 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT);
16124 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr,
16125 MachinePointerInfo(),
16126 false, false, false, 0);
16130 // FIXME? Maybe this could be a TableGen attribute on some registers and
16131 // this table could be generated automatically from RegInfo.
16132 unsigned X86TargetLowering::getRegisterByName(const char* RegName,
16134 unsigned Reg = StringSwitch<unsigned>(RegName)
16135 .Case("esp", X86::ESP)
16136 .Case("rsp", X86::RSP)
16140 report_fatal_error("Invalid register name global variable");
16143 SDValue X86TargetLowering::LowerFRAME_TO_ARGS_OFFSET(SDValue Op,
16144 SelectionDAG &DAG) const {
16145 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
16146 DAG.getSubtarget().getRegisterInfo());
16147 return DAG.getIntPtrConstant(2 * RegInfo->getSlotSize());
16150 SDValue X86TargetLowering::LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const {
16151 SDValue Chain = Op.getOperand(0);
16152 SDValue Offset = Op.getOperand(1);
16153 SDValue Handler = Op.getOperand(2);
16156 EVT PtrVT = getPointerTy();
16157 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
16158 DAG.getSubtarget().getRegisterInfo());
16159 unsigned FrameReg = RegInfo->getFrameRegister(DAG.getMachineFunction());
16160 assert(((FrameReg == X86::RBP && PtrVT == MVT::i64) ||
16161 (FrameReg == X86::EBP && PtrVT == MVT::i32)) &&
16162 "Invalid Frame Register!");
16163 SDValue Frame = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, PtrVT);
16164 unsigned StoreAddrReg = (PtrVT == MVT::i64) ? X86::RCX : X86::ECX;
16166 SDValue StoreAddr = DAG.getNode(ISD::ADD, dl, PtrVT, Frame,
16167 DAG.getIntPtrConstant(RegInfo->getSlotSize()));
16168 StoreAddr = DAG.getNode(ISD::ADD, dl, PtrVT, StoreAddr, Offset);
16169 Chain = DAG.getStore(Chain, dl, Handler, StoreAddr, MachinePointerInfo(),
16171 Chain = DAG.getCopyToReg(Chain, dl, StoreAddrReg, StoreAddr);
16173 return DAG.getNode(X86ISD::EH_RETURN, dl, MVT::Other, Chain,
16174 DAG.getRegister(StoreAddrReg, PtrVT));
16177 SDValue X86TargetLowering::lowerEH_SJLJ_SETJMP(SDValue Op,
16178 SelectionDAG &DAG) const {
16180 return DAG.getNode(X86ISD::EH_SJLJ_SETJMP, DL,
16181 DAG.getVTList(MVT::i32, MVT::Other),
16182 Op.getOperand(0), Op.getOperand(1));
16185 SDValue X86TargetLowering::lowerEH_SJLJ_LONGJMP(SDValue Op,
16186 SelectionDAG &DAG) const {
16188 return DAG.getNode(X86ISD::EH_SJLJ_LONGJMP, DL, MVT::Other,
16189 Op.getOperand(0), Op.getOperand(1));
16192 static SDValue LowerADJUST_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) {
16193 return Op.getOperand(0);
16196 SDValue X86TargetLowering::LowerINIT_TRAMPOLINE(SDValue Op,
16197 SelectionDAG &DAG) const {
16198 SDValue Root = Op.getOperand(0);
16199 SDValue Trmp = Op.getOperand(1); // trampoline
16200 SDValue FPtr = Op.getOperand(2); // nested function
16201 SDValue Nest = Op.getOperand(3); // 'nest' parameter value
16204 const Value *TrmpAddr = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
16205 const TargetRegisterInfo *TRI = DAG.getSubtarget().getRegisterInfo();
16207 if (Subtarget->is64Bit()) {
16208 SDValue OutChains[6];
16210 // Large code-model.
16211 const unsigned char JMP64r = 0xFF; // 64-bit jmp through register opcode.
16212 const unsigned char MOV64ri = 0xB8; // X86::MOV64ri opcode.
16214 const unsigned char N86R10 = TRI->getEncodingValue(X86::R10) & 0x7;
16215 const unsigned char N86R11 = TRI->getEncodingValue(X86::R11) & 0x7;
16217 const unsigned char REX_WB = 0x40 | 0x08 | 0x01; // REX prefix
16219 // Load the pointer to the nested function into R11.
16220 unsigned OpCode = ((MOV64ri | N86R11) << 8) | REX_WB; // movabsq r11
16221 SDValue Addr = Trmp;
16222 OutChains[0] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
16223 Addr, MachinePointerInfo(TrmpAddr),
16226 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
16227 DAG.getConstant(2, MVT::i64));
16228 OutChains[1] = DAG.getStore(Root, dl, FPtr, Addr,
16229 MachinePointerInfo(TrmpAddr, 2),
16232 // Load the 'nest' parameter value into R10.
16233 // R10 is specified in X86CallingConv.td
16234 OpCode = ((MOV64ri | N86R10) << 8) | REX_WB; // movabsq r10
16235 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
16236 DAG.getConstant(10, MVT::i64));
16237 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
16238 Addr, MachinePointerInfo(TrmpAddr, 10),
16241 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
16242 DAG.getConstant(12, MVT::i64));
16243 OutChains[3] = DAG.getStore(Root, dl, Nest, Addr,
16244 MachinePointerInfo(TrmpAddr, 12),
16247 // Jump to the nested function.
16248 OpCode = (JMP64r << 8) | REX_WB; // jmpq *...
16249 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
16250 DAG.getConstant(20, MVT::i64));
16251 OutChains[4] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
16252 Addr, MachinePointerInfo(TrmpAddr, 20),
16255 unsigned char ModRM = N86R11 | (4 << 3) | (3 << 6); // ...r11
16256 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
16257 DAG.getConstant(22, MVT::i64));
16258 OutChains[5] = DAG.getStore(Root, dl, DAG.getConstant(ModRM, MVT::i8), Addr,
16259 MachinePointerInfo(TrmpAddr, 22),
16262 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains);
16264 const Function *Func =
16265 cast<Function>(cast<SrcValueSDNode>(Op.getOperand(5))->getValue());
16266 CallingConv::ID CC = Func->getCallingConv();
16271 llvm_unreachable("Unsupported calling convention");
16272 case CallingConv::C:
16273 case CallingConv::X86_StdCall: {
16274 // Pass 'nest' parameter in ECX.
16275 // Must be kept in sync with X86CallingConv.td
16276 NestReg = X86::ECX;
16278 // Check that ECX wasn't needed by an 'inreg' parameter.
16279 FunctionType *FTy = Func->getFunctionType();
16280 const AttributeSet &Attrs = Func->getAttributes();
16282 if (!Attrs.isEmpty() && !Func->isVarArg()) {
16283 unsigned InRegCount = 0;
16286 for (FunctionType::param_iterator I = FTy->param_begin(),
16287 E = FTy->param_end(); I != E; ++I, ++Idx)
16288 if (Attrs.hasAttribute(Idx, Attribute::InReg))
16289 // FIXME: should only count parameters that are lowered to integers.
16290 InRegCount += (TD->getTypeSizeInBits(*I) + 31) / 32;
16292 if (InRegCount > 2) {
16293 report_fatal_error("Nest register in use - reduce number of inreg"
16299 case CallingConv::X86_FastCall:
16300 case CallingConv::X86_ThisCall:
16301 case CallingConv::Fast:
16302 // Pass 'nest' parameter in EAX.
16303 // Must be kept in sync with X86CallingConv.td
16304 NestReg = X86::EAX;
16308 SDValue OutChains[4];
16309 SDValue Addr, Disp;
16311 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
16312 DAG.getConstant(10, MVT::i32));
16313 Disp = DAG.getNode(ISD::SUB, dl, MVT::i32, FPtr, Addr);
16315 // This is storing the opcode for MOV32ri.
16316 const unsigned char MOV32ri = 0xB8; // X86::MOV32ri's opcode byte.
16317 const unsigned char N86Reg = TRI->getEncodingValue(NestReg) & 0x7;
16318 OutChains[0] = DAG.getStore(Root, dl,
16319 DAG.getConstant(MOV32ri|N86Reg, MVT::i8),
16320 Trmp, MachinePointerInfo(TrmpAddr),
16323 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
16324 DAG.getConstant(1, MVT::i32));
16325 OutChains[1] = DAG.getStore(Root, dl, Nest, Addr,
16326 MachinePointerInfo(TrmpAddr, 1),
16329 const unsigned char JMP = 0xE9; // jmp <32bit dst> opcode.
16330 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
16331 DAG.getConstant(5, MVT::i32));
16332 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(JMP, MVT::i8), Addr,
16333 MachinePointerInfo(TrmpAddr, 5),
16336 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
16337 DAG.getConstant(6, MVT::i32));
16338 OutChains[3] = DAG.getStore(Root, dl, Disp, Addr,
16339 MachinePointerInfo(TrmpAddr, 6),
16342 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains);
16346 SDValue X86TargetLowering::LowerFLT_ROUNDS_(SDValue Op,
16347 SelectionDAG &DAG) const {
16349 The rounding mode is in bits 11:10 of FPSR, and has the following
16351 00 Round to nearest
16356 FLT_ROUNDS, on the other hand, expects the following:
16363 To perform the conversion, we do:
16364 (((((FPSR & 0x800) >> 11) | ((FPSR & 0x400) >> 9)) + 1) & 3)
16367 MachineFunction &MF = DAG.getMachineFunction();
16368 const TargetMachine &TM = MF.getTarget();
16369 const TargetFrameLowering &TFI = *TM.getSubtargetImpl()->getFrameLowering();
16370 unsigned StackAlignment = TFI.getStackAlignment();
16371 MVT VT = Op.getSimpleValueType();
16374 // Save FP Control Word to stack slot
16375 int SSFI = MF.getFrameInfo()->CreateStackObject(2, StackAlignment, false);
16376 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
16378 MachineMemOperand *MMO =
16379 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
16380 MachineMemOperand::MOStore, 2, 2);
16382 SDValue Ops[] = { DAG.getEntryNode(), StackSlot };
16383 SDValue Chain = DAG.getMemIntrinsicNode(X86ISD::FNSTCW16m, DL,
16384 DAG.getVTList(MVT::Other),
16385 Ops, MVT::i16, MMO);
16387 // Load FP Control Word from stack slot
16388 SDValue CWD = DAG.getLoad(MVT::i16, DL, Chain, StackSlot,
16389 MachinePointerInfo(), false, false, false, 0);
16391 // Transform as necessary
16393 DAG.getNode(ISD::SRL, DL, MVT::i16,
16394 DAG.getNode(ISD::AND, DL, MVT::i16,
16395 CWD, DAG.getConstant(0x800, MVT::i16)),
16396 DAG.getConstant(11, MVT::i8));
16398 DAG.getNode(ISD::SRL, DL, MVT::i16,
16399 DAG.getNode(ISD::AND, DL, MVT::i16,
16400 CWD, DAG.getConstant(0x400, MVT::i16)),
16401 DAG.getConstant(9, MVT::i8));
16404 DAG.getNode(ISD::AND, DL, MVT::i16,
16405 DAG.getNode(ISD::ADD, DL, MVT::i16,
16406 DAG.getNode(ISD::OR, DL, MVT::i16, CWD1, CWD2),
16407 DAG.getConstant(1, MVT::i16)),
16408 DAG.getConstant(3, MVT::i16));
16410 return DAG.getNode((VT.getSizeInBits() < 16 ?
16411 ISD::TRUNCATE : ISD::ZERO_EXTEND), DL, VT, RetVal);
16414 static SDValue LowerCTLZ(SDValue Op, SelectionDAG &DAG) {
16415 MVT VT = Op.getSimpleValueType();
16417 unsigned NumBits = VT.getSizeInBits();
16420 Op = Op.getOperand(0);
16421 if (VT == MVT::i8) {
16422 // Zero extend to i32 since there is not an i8 bsr.
16424 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
16427 // Issue a bsr (scan bits in reverse) which also sets EFLAGS.
16428 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
16429 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
16431 // If src is zero (i.e. bsr sets ZF), returns NumBits.
16434 DAG.getConstant(NumBits+NumBits-1, OpVT),
16435 DAG.getConstant(X86::COND_E, MVT::i8),
16438 Op = DAG.getNode(X86ISD::CMOV, dl, OpVT, Ops);
16440 // Finally xor with NumBits-1.
16441 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT));
16444 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
16448 static SDValue LowerCTLZ_ZERO_UNDEF(SDValue Op, SelectionDAG &DAG) {
16449 MVT VT = Op.getSimpleValueType();
16451 unsigned NumBits = VT.getSizeInBits();
16454 Op = Op.getOperand(0);
16455 if (VT == MVT::i8) {
16456 // Zero extend to i32 since there is not an i8 bsr.
16458 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
16461 // Issue a bsr (scan bits in reverse).
16462 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
16463 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
16465 // And xor with NumBits-1.
16466 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT));
16469 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
16473 static SDValue LowerCTTZ(SDValue Op, SelectionDAG &DAG) {
16474 MVT VT = Op.getSimpleValueType();
16475 unsigned NumBits = VT.getSizeInBits();
16477 Op = Op.getOperand(0);
16479 // Issue a bsf (scan bits forward) which also sets EFLAGS.
16480 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
16481 Op = DAG.getNode(X86ISD::BSF, dl, VTs, Op);
16483 // If src is zero (i.e. bsf sets ZF), returns NumBits.
16486 DAG.getConstant(NumBits, VT),
16487 DAG.getConstant(X86::COND_E, MVT::i8),
16490 return DAG.getNode(X86ISD::CMOV, dl, VT, Ops);
16493 // Lower256IntArith - Break a 256-bit integer operation into two new 128-bit
16494 // ones, and then concatenate the result back.
16495 static SDValue Lower256IntArith(SDValue Op, SelectionDAG &DAG) {
16496 MVT VT = Op.getSimpleValueType();
16498 assert(VT.is256BitVector() && VT.isInteger() &&
16499 "Unsupported value type for operation");
16501 unsigned NumElems = VT.getVectorNumElements();
16504 // Extract the LHS vectors
16505 SDValue LHS = Op.getOperand(0);
16506 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
16507 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
16509 // Extract the RHS vectors
16510 SDValue RHS = Op.getOperand(1);
16511 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, dl);
16512 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, dl);
16514 MVT EltVT = VT.getVectorElementType();
16515 MVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
16517 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
16518 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1),
16519 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2));
16522 static SDValue LowerADD(SDValue Op, SelectionDAG &DAG) {
16523 assert(Op.getSimpleValueType().is256BitVector() &&
16524 Op.getSimpleValueType().isInteger() &&
16525 "Only handle AVX 256-bit vector integer operation");
16526 return Lower256IntArith(Op, DAG);
16529 static SDValue LowerSUB(SDValue Op, SelectionDAG &DAG) {
16530 assert(Op.getSimpleValueType().is256BitVector() &&
16531 Op.getSimpleValueType().isInteger() &&
16532 "Only handle AVX 256-bit vector integer operation");
16533 return Lower256IntArith(Op, DAG);
16536 static SDValue LowerMUL(SDValue Op, const X86Subtarget *Subtarget,
16537 SelectionDAG &DAG) {
16539 MVT VT = Op.getSimpleValueType();
16541 // Decompose 256-bit ops into smaller 128-bit ops.
16542 if (VT.is256BitVector() && !Subtarget->hasInt256())
16543 return Lower256IntArith(Op, DAG);
16545 SDValue A = Op.getOperand(0);
16546 SDValue B = Op.getOperand(1);
16548 // Lower v4i32 mul as 2x shuffle, 2x pmuludq, 2x shuffle.
16549 if (VT == MVT::v4i32) {
16550 assert(Subtarget->hasSSE2() && !Subtarget->hasSSE41() &&
16551 "Should not custom lower when pmuldq is available!");
16553 // Extract the odd parts.
16554 static const int UnpackMask[] = { 1, -1, 3, -1 };
16555 SDValue Aodds = DAG.getVectorShuffle(VT, dl, A, A, UnpackMask);
16556 SDValue Bodds = DAG.getVectorShuffle(VT, dl, B, B, UnpackMask);
16558 // Multiply the even parts.
16559 SDValue Evens = DAG.getNode(X86ISD::PMULUDQ, dl, MVT::v2i64, A, B);
16560 // Now multiply odd parts.
16561 SDValue Odds = DAG.getNode(X86ISD::PMULUDQ, dl, MVT::v2i64, Aodds, Bodds);
16563 Evens = DAG.getNode(ISD::BITCAST, dl, VT, Evens);
16564 Odds = DAG.getNode(ISD::BITCAST, dl, VT, Odds);
16566 // Merge the two vectors back together with a shuffle. This expands into 2
16568 static const int ShufMask[] = { 0, 4, 2, 6 };
16569 return DAG.getVectorShuffle(VT, dl, Evens, Odds, ShufMask);
16572 assert((VT == MVT::v2i64 || VT == MVT::v4i64 || VT == MVT::v8i64) &&
16573 "Only know how to lower V2I64/V4I64/V8I64 multiply");
16575 // Ahi = psrlqi(a, 32);
16576 // Bhi = psrlqi(b, 32);
16578 // AloBlo = pmuludq(a, b);
16579 // AloBhi = pmuludq(a, Bhi);
16580 // AhiBlo = pmuludq(Ahi, b);
16582 // AloBhi = psllqi(AloBhi, 32);
16583 // AhiBlo = psllqi(AhiBlo, 32);
16584 // return AloBlo + AloBhi + AhiBlo;
16586 SDValue Ahi = getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, A, 32, DAG);
16587 SDValue Bhi = getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, B, 32, DAG);
16589 // Bit cast to 32-bit vectors for MULUDQ
16590 EVT MulVT = (VT == MVT::v2i64) ? MVT::v4i32 :
16591 (VT == MVT::v4i64) ? MVT::v8i32 : MVT::v16i32;
16592 A = DAG.getNode(ISD::BITCAST, dl, MulVT, A);
16593 B = DAG.getNode(ISD::BITCAST, dl, MulVT, B);
16594 Ahi = DAG.getNode(ISD::BITCAST, dl, MulVT, Ahi);
16595 Bhi = DAG.getNode(ISD::BITCAST, dl, MulVT, Bhi);
16597 SDValue AloBlo = DAG.getNode(X86ISD::PMULUDQ, dl, VT, A, B);
16598 SDValue AloBhi = DAG.getNode(X86ISD::PMULUDQ, dl, VT, A, Bhi);
16599 SDValue AhiBlo = DAG.getNode(X86ISD::PMULUDQ, dl, VT, Ahi, B);
16601 AloBhi = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, AloBhi, 32, DAG);
16602 AhiBlo = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, AhiBlo, 32, DAG);
16604 SDValue Res = DAG.getNode(ISD::ADD, dl, VT, AloBlo, AloBhi);
16605 return DAG.getNode(ISD::ADD, dl, VT, Res, AhiBlo);
16608 SDValue X86TargetLowering::LowerWin64_i128OP(SDValue Op, SelectionDAG &DAG) const {
16609 assert(Subtarget->isTargetWin64() && "Unexpected target");
16610 EVT VT = Op.getValueType();
16611 assert(VT.isInteger() && VT.getSizeInBits() == 128 &&
16612 "Unexpected return type for lowering");
16616 switch (Op->getOpcode()) {
16617 default: llvm_unreachable("Unexpected request for libcall!");
16618 case ISD::SDIV: isSigned = true; LC = RTLIB::SDIV_I128; break;
16619 case ISD::UDIV: isSigned = false; LC = RTLIB::UDIV_I128; break;
16620 case ISD::SREM: isSigned = true; LC = RTLIB::SREM_I128; break;
16621 case ISD::UREM: isSigned = false; LC = RTLIB::UREM_I128; break;
16622 case ISD::SDIVREM: isSigned = true; LC = RTLIB::SDIVREM_I128; break;
16623 case ISD::UDIVREM: isSigned = false; LC = RTLIB::UDIVREM_I128; break;
16627 SDValue InChain = DAG.getEntryNode();
16629 TargetLowering::ArgListTy Args;
16630 TargetLowering::ArgListEntry Entry;
16631 for (unsigned i = 0, e = Op->getNumOperands(); i != e; ++i) {
16632 EVT ArgVT = Op->getOperand(i).getValueType();
16633 assert(ArgVT.isInteger() && ArgVT.getSizeInBits() == 128 &&
16634 "Unexpected argument type for lowering");
16635 SDValue StackPtr = DAG.CreateStackTemporary(ArgVT, 16);
16636 Entry.Node = StackPtr;
16637 InChain = DAG.getStore(InChain, dl, Op->getOperand(i), StackPtr, MachinePointerInfo(),
16639 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
16640 Entry.Ty = PointerType::get(ArgTy,0);
16641 Entry.isSExt = false;
16642 Entry.isZExt = false;
16643 Args.push_back(Entry);
16646 SDValue Callee = DAG.getExternalSymbol(getLibcallName(LC),
16649 TargetLowering::CallLoweringInfo CLI(DAG);
16650 CLI.setDebugLoc(dl).setChain(InChain)
16651 .setCallee(getLibcallCallingConv(LC),
16652 static_cast<EVT>(MVT::v2i64).getTypeForEVT(*DAG.getContext()),
16653 Callee, std::move(Args), 0)
16654 .setInRegister().setSExtResult(isSigned).setZExtResult(!isSigned);
16656 std::pair<SDValue, SDValue> CallInfo = LowerCallTo(CLI);
16657 return DAG.getNode(ISD::BITCAST, dl, VT, CallInfo.first);
16660 static SDValue LowerMUL_LOHI(SDValue Op, const X86Subtarget *Subtarget,
16661 SelectionDAG &DAG) {
16662 SDValue Op0 = Op.getOperand(0), Op1 = Op.getOperand(1);
16663 EVT VT = Op0.getValueType();
16666 assert((VT == MVT::v4i32 && Subtarget->hasSSE2()) ||
16667 (VT == MVT::v8i32 && Subtarget->hasInt256()));
16669 // PMULxD operations multiply each even value (starting at 0) of LHS with
16670 // the related value of RHS and produce a widen result.
16671 // E.g., PMULUDQ <4 x i32> <a|b|c|d>, <4 x i32> <e|f|g|h>
16672 // => <2 x i64> <ae|cg>
16674 // In other word, to have all the results, we need to perform two PMULxD:
16675 // 1. one with the even values.
16676 // 2. one with the odd values.
16677 // To achieve #2, with need to place the odd values at an even position.
16679 // Place the odd value at an even position (basically, shift all values 1
16680 // step to the left):
16681 const int Mask[] = {1, -1, 3, -1, 5, -1, 7, -1};
16682 // <a|b|c|d> => <b|undef|d|undef>
16683 SDValue Odd0 = DAG.getVectorShuffle(VT, dl, Op0, Op0, Mask);
16684 // <e|f|g|h> => <f|undef|h|undef>
16685 SDValue Odd1 = DAG.getVectorShuffle(VT, dl, Op1, Op1, Mask);
16687 // Emit two multiplies, one for the lower 2 ints and one for the higher 2
16689 MVT MulVT = VT == MVT::v4i32 ? MVT::v2i64 : MVT::v4i64;
16690 bool IsSigned = Op->getOpcode() == ISD::SMUL_LOHI;
16692 (!IsSigned || !Subtarget->hasSSE41()) ? X86ISD::PMULUDQ : X86ISD::PMULDQ;
16693 // PMULUDQ <4 x i32> <a|b|c|d>, <4 x i32> <e|f|g|h>
16694 // => <2 x i64> <ae|cg>
16695 SDValue Mul1 = DAG.getNode(ISD::BITCAST, dl, VT,
16696 DAG.getNode(Opcode, dl, MulVT, Op0, Op1));
16697 // PMULUDQ <4 x i32> <b|undef|d|undef>, <4 x i32> <f|undef|h|undef>
16698 // => <2 x i64> <bf|dh>
16699 SDValue Mul2 = DAG.getNode(ISD::BITCAST, dl, VT,
16700 DAG.getNode(Opcode, dl, MulVT, Odd0, Odd1));
16702 // Shuffle it back into the right order.
16703 SDValue Highs, Lows;
16704 if (VT == MVT::v8i32) {
16705 const int HighMask[] = {1, 9, 3, 11, 5, 13, 7, 15};
16706 Highs = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, HighMask);
16707 const int LowMask[] = {0, 8, 2, 10, 4, 12, 6, 14};
16708 Lows = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, LowMask);
16710 const int HighMask[] = {1, 5, 3, 7};
16711 Highs = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, HighMask);
16712 const int LowMask[] = {0, 4, 2, 6};
16713 Lows = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, LowMask);
16716 // If we have a signed multiply but no PMULDQ fix up the high parts of a
16717 // unsigned multiply.
16718 if (IsSigned && !Subtarget->hasSSE41()) {
16720 DAG.getConstant(31, DAG.getTargetLoweringInfo().getShiftAmountTy(VT));
16721 SDValue T1 = DAG.getNode(ISD::AND, dl, VT,
16722 DAG.getNode(ISD::SRA, dl, VT, Op0, ShAmt), Op1);
16723 SDValue T2 = DAG.getNode(ISD::AND, dl, VT,
16724 DAG.getNode(ISD::SRA, dl, VT, Op1, ShAmt), Op0);
16726 SDValue Fixup = DAG.getNode(ISD::ADD, dl, VT, T1, T2);
16727 Highs = DAG.getNode(ISD::SUB, dl, VT, Highs, Fixup);
16730 // The first result of MUL_LOHI is actually the low value, followed by the
16732 SDValue Ops[] = {Lows, Highs};
16733 return DAG.getMergeValues(Ops, dl);
16736 static SDValue LowerScalarImmediateShift(SDValue Op, SelectionDAG &DAG,
16737 const X86Subtarget *Subtarget) {
16738 MVT VT = Op.getSimpleValueType();
16740 SDValue R = Op.getOperand(0);
16741 SDValue Amt = Op.getOperand(1);
16743 // Optimize shl/srl/sra with constant shift amount.
16744 if (auto *BVAmt = dyn_cast<BuildVectorSDNode>(Amt)) {
16745 if (auto *ShiftConst = BVAmt->getConstantSplatNode()) {
16746 uint64_t ShiftAmt = ShiftConst->getZExtValue();
16748 if (VT == MVT::v2i64 || VT == MVT::v4i32 || VT == MVT::v8i16 ||
16749 (Subtarget->hasInt256() &&
16750 (VT == MVT::v4i64 || VT == MVT::v8i32 || VT == MVT::v16i16)) ||
16751 (Subtarget->hasAVX512() &&
16752 (VT == MVT::v8i64 || VT == MVT::v16i32))) {
16753 if (Op.getOpcode() == ISD::SHL)
16754 return getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, R, ShiftAmt,
16756 if (Op.getOpcode() == ISD::SRL)
16757 return getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, R, ShiftAmt,
16759 if (Op.getOpcode() == ISD::SRA && VT != MVT::v2i64 && VT != MVT::v4i64)
16760 return getTargetVShiftByConstNode(X86ISD::VSRAI, dl, VT, R, ShiftAmt,
16764 if (VT == MVT::v16i8) {
16765 if (Op.getOpcode() == ISD::SHL) {
16766 // Make a large shift.
16767 SDValue SHL = getTargetVShiftByConstNode(X86ISD::VSHLI, dl,
16768 MVT::v8i16, R, ShiftAmt,
16770 SHL = DAG.getNode(ISD::BITCAST, dl, VT, SHL);
16771 // Zero out the rightmost bits.
16772 SmallVector<SDValue, 16> V(16,
16773 DAG.getConstant(uint8_t(-1U << ShiftAmt),
16775 return DAG.getNode(ISD::AND, dl, VT, SHL,
16776 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V));
16778 if (Op.getOpcode() == ISD::SRL) {
16779 // Make a large shift.
16780 SDValue SRL = getTargetVShiftByConstNode(X86ISD::VSRLI, dl,
16781 MVT::v8i16, R, ShiftAmt,
16783 SRL = DAG.getNode(ISD::BITCAST, dl, VT, SRL);
16784 // Zero out the leftmost bits.
16785 SmallVector<SDValue, 16> V(16,
16786 DAG.getConstant(uint8_t(-1U) >> ShiftAmt,
16788 return DAG.getNode(ISD::AND, dl, VT, SRL,
16789 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V));
16791 if (Op.getOpcode() == ISD::SRA) {
16792 if (ShiftAmt == 7) {
16793 // R s>> 7 === R s< 0
16794 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
16795 return DAG.getNode(X86ISD::PCMPGT, dl, VT, Zeros, R);
16798 // R s>> a === ((R u>> a) ^ m) - m
16799 SDValue Res = DAG.getNode(ISD::SRL, dl, VT, R, Amt);
16800 SmallVector<SDValue, 16> V(16, DAG.getConstant(128 >> ShiftAmt,
16802 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V);
16803 Res = DAG.getNode(ISD::XOR, dl, VT, Res, Mask);
16804 Res = DAG.getNode(ISD::SUB, dl, VT, Res, Mask);
16807 llvm_unreachable("Unknown shift opcode.");
16810 if (Subtarget->hasInt256() && VT == MVT::v32i8) {
16811 if (Op.getOpcode() == ISD::SHL) {
16812 // Make a large shift.
16813 SDValue SHL = getTargetVShiftByConstNode(X86ISD::VSHLI, dl,
16814 MVT::v16i16, R, ShiftAmt,
16816 SHL = DAG.getNode(ISD::BITCAST, dl, VT, SHL);
16817 // Zero out the rightmost bits.
16818 SmallVector<SDValue, 32> V(32,
16819 DAG.getConstant(uint8_t(-1U << ShiftAmt),
16821 return DAG.getNode(ISD::AND, dl, VT, SHL,
16822 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V));
16824 if (Op.getOpcode() == ISD::SRL) {
16825 // Make a large shift.
16826 SDValue SRL = getTargetVShiftByConstNode(X86ISD::VSRLI, dl,
16827 MVT::v16i16, R, ShiftAmt,
16829 SRL = DAG.getNode(ISD::BITCAST, dl, VT, SRL);
16830 // Zero out the leftmost bits.
16831 SmallVector<SDValue, 32> V(32,
16832 DAG.getConstant(uint8_t(-1U) >> ShiftAmt,
16834 return DAG.getNode(ISD::AND, dl, VT, SRL,
16835 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V));
16837 if (Op.getOpcode() == ISD::SRA) {
16838 if (ShiftAmt == 7) {
16839 // R s>> 7 === R s< 0
16840 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
16841 return DAG.getNode(X86ISD::PCMPGT, dl, VT, Zeros, R);
16844 // R s>> a === ((R u>> a) ^ m) - m
16845 SDValue Res = DAG.getNode(ISD::SRL, dl, VT, R, Amt);
16846 SmallVector<SDValue, 32> V(32, DAG.getConstant(128 >> ShiftAmt,
16848 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V);
16849 Res = DAG.getNode(ISD::XOR, dl, VT, Res, Mask);
16850 Res = DAG.getNode(ISD::SUB, dl, VT, Res, Mask);
16853 llvm_unreachable("Unknown shift opcode.");
16858 // Special case in 32-bit mode, where i64 is expanded into high and low parts.
16859 if (!Subtarget->is64Bit() &&
16860 (VT == MVT::v2i64 || (Subtarget->hasInt256() && VT == MVT::v4i64)) &&
16861 Amt.getOpcode() == ISD::BITCAST &&
16862 Amt.getOperand(0).getOpcode() == ISD::BUILD_VECTOR) {
16863 Amt = Amt.getOperand(0);
16864 unsigned Ratio = Amt.getSimpleValueType().getVectorNumElements() /
16865 VT.getVectorNumElements();
16866 unsigned RatioInLog2 = Log2_32_Ceil(Ratio);
16867 uint64_t ShiftAmt = 0;
16868 for (unsigned i = 0; i != Ratio; ++i) {
16869 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Amt.getOperand(i));
16873 ShiftAmt |= C->getZExtValue() << (i * (1 << (6 - RatioInLog2)));
16875 // Check remaining shift amounts.
16876 for (unsigned i = Ratio; i != Amt.getNumOperands(); i += Ratio) {
16877 uint64_t ShAmt = 0;
16878 for (unsigned j = 0; j != Ratio; ++j) {
16879 ConstantSDNode *C =
16880 dyn_cast<ConstantSDNode>(Amt.getOperand(i + j));
16884 ShAmt |= C->getZExtValue() << (j * (1 << (6 - RatioInLog2)));
16886 if (ShAmt != ShiftAmt)
16889 switch (Op.getOpcode()) {
16891 llvm_unreachable("Unknown shift opcode!");
16893 return getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, R, ShiftAmt,
16896 return getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, R, ShiftAmt,
16899 return getTargetVShiftByConstNode(X86ISD::VSRAI, dl, VT, R, ShiftAmt,
16907 static SDValue LowerScalarVariableShift(SDValue Op, SelectionDAG &DAG,
16908 const X86Subtarget* Subtarget) {
16909 MVT VT = Op.getSimpleValueType();
16911 SDValue R = Op.getOperand(0);
16912 SDValue Amt = Op.getOperand(1);
16914 if ((VT == MVT::v2i64 && Op.getOpcode() != ISD::SRA) ||
16915 VT == MVT::v4i32 || VT == MVT::v8i16 ||
16916 (Subtarget->hasInt256() &&
16917 ((VT == MVT::v4i64 && Op.getOpcode() != ISD::SRA) ||
16918 VT == MVT::v8i32 || VT == MVT::v16i16)) ||
16919 (Subtarget->hasAVX512() && (VT == MVT::v8i64 || VT == MVT::v16i32))) {
16921 EVT EltVT = VT.getVectorElementType();
16923 if (Amt.getOpcode() == ISD::BUILD_VECTOR) {
16924 unsigned NumElts = VT.getVectorNumElements();
16926 for (i = 0; i != NumElts; ++i) {
16927 if (Amt.getOperand(i).getOpcode() == ISD::UNDEF)
16931 for (j = i; j != NumElts; ++j) {
16932 SDValue Arg = Amt.getOperand(j);
16933 if (Arg.getOpcode() == ISD::UNDEF) continue;
16934 if (Arg != Amt.getOperand(i))
16937 if (i != NumElts && j == NumElts)
16938 BaseShAmt = Amt.getOperand(i);
16940 if (Amt.getOpcode() == ISD::EXTRACT_SUBVECTOR)
16941 Amt = Amt.getOperand(0);
16942 if (Amt.getOpcode() == ISD::VECTOR_SHUFFLE &&
16943 cast<ShuffleVectorSDNode>(Amt)->isSplat()) {
16944 SDValue InVec = Amt.getOperand(0);
16945 if (InVec.getOpcode() == ISD::BUILD_VECTOR) {
16946 unsigned NumElts = InVec.getValueType().getVectorNumElements();
16948 for (; i != NumElts; ++i) {
16949 SDValue Arg = InVec.getOperand(i);
16950 if (Arg.getOpcode() == ISD::UNDEF) continue;
16954 } else if (InVec.getOpcode() == ISD::INSERT_VECTOR_ELT) {
16955 if (ConstantSDNode *C =
16956 dyn_cast<ConstantSDNode>(InVec.getOperand(2))) {
16957 unsigned SplatIdx =
16958 cast<ShuffleVectorSDNode>(Amt)->getSplatIndex();
16959 if (C->getZExtValue() == SplatIdx)
16960 BaseShAmt = InVec.getOperand(1);
16963 if (!BaseShAmt.getNode())
16964 BaseShAmt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, Amt,
16965 DAG.getIntPtrConstant(0));
16969 if (BaseShAmt.getNode()) {
16970 if (EltVT.bitsGT(MVT::i32))
16971 BaseShAmt = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, BaseShAmt);
16972 else if (EltVT.bitsLT(MVT::i32))
16973 BaseShAmt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, BaseShAmt);
16975 switch (Op.getOpcode()) {
16977 llvm_unreachable("Unknown shift opcode!");
16979 switch (VT.SimpleTy) {
16980 default: return SDValue();
16989 return getTargetVShiftNode(X86ISD::VSHLI, dl, VT, R, BaseShAmt, DAG);
16992 switch (VT.SimpleTy) {
16993 default: return SDValue();
17000 return getTargetVShiftNode(X86ISD::VSRAI, dl, VT, R, BaseShAmt, DAG);
17003 switch (VT.SimpleTy) {
17004 default: return SDValue();
17013 return getTargetVShiftNode(X86ISD::VSRLI, dl, VT, R, BaseShAmt, DAG);
17019 // Special case in 32-bit mode, where i64 is expanded into high and low parts.
17020 if (!Subtarget->is64Bit() &&
17021 (VT == MVT::v2i64 || (Subtarget->hasInt256() && VT == MVT::v4i64) ||
17022 (Subtarget->hasAVX512() && VT == MVT::v8i64)) &&
17023 Amt.getOpcode() == ISD::BITCAST &&
17024 Amt.getOperand(0).getOpcode() == ISD::BUILD_VECTOR) {
17025 Amt = Amt.getOperand(0);
17026 unsigned Ratio = Amt.getSimpleValueType().getVectorNumElements() /
17027 VT.getVectorNumElements();
17028 std::vector<SDValue> Vals(Ratio);
17029 for (unsigned i = 0; i != Ratio; ++i)
17030 Vals[i] = Amt.getOperand(i);
17031 for (unsigned i = Ratio; i != Amt.getNumOperands(); i += Ratio) {
17032 for (unsigned j = 0; j != Ratio; ++j)
17033 if (Vals[j] != Amt.getOperand(i + j))
17036 switch (Op.getOpcode()) {
17038 llvm_unreachable("Unknown shift opcode!");
17040 return DAG.getNode(X86ISD::VSHL, dl, VT, R, Op.getOperand(1));
17042 return DAG.getNode(X86ISD::VSRL, dl, VT, R, Op.getOperand(1));
17044 return DAG.getNode(X86ISD::VSRA, dl, VT, R, Op.getOperand(1));
17051 static SDValue LowerShift(SDValue Op, const X86Subtarget* Subtarget,
17052 SelectionDAG &DAG) {
17053 MVT VT = Op.getSimpleValueType();
17055 SDValue R = Op.getOperand(0);
17056 SDValue Amt = Op.getOperand(1);
17059 assert(VT.isVector() && "Custom lowering only for vector shifts!");
17060 assert(Subtarget->hasSSE2() && "Only custom lower when we have SSE2!");
17062 V = LowerScalarImmediateShift(Op, DAG, Subtarget);
17066 V = LowerScalarVariableShift(Op, DAG, Subtarget);
17070 if (Subtarget->hasAVX512() && (VT == MVT::v16i32 || VT == MVT::v8i64))
17072 // AVX2 has VPSLLV/VPSRAV/VPSRLV.
17073 if (Subtarget->hasInt256()) {
17074 if (Op.getOpcode() == ISD::SRL &&
17075 (VT == MVT::v2i64 || VT == MVT::v4i32 ||
17076 VT == MVT::v4i64 || VT == MVT::v8i32))
17078 if (Op.getOpcode() == ISD::SHL &&
17079 (VT == MVT::v2i64 || VT == MVT::v4i32 ||
17080 VT == MVT::v4i64 || VT == MVT::v8i32))
17082 if (Op.getOpcode() == ISD::SRA && (VT == MVT::v4i32 || VT == MVT::v8i32))
17086 // If possible, lower this packed shift into a vector multiply instead of
17087 // expanding it into a sequence of scalar shifts.
17088 // Do this only if the vector shift count is a constant build_vector.
17089 if (Op.getOpcode() == ISD::SHL &&
17090 (VT == MVT::v8i16 || VT == MVT::v4i32 ||
17091 (Subtarget->hasInt256() && VT == MVT::v16i16)) &&
17092 ISD::isBuildVectorOfConstantSDNodes(Amt.getNode())) {
17093 SmallVector<SDValue, 8> Elts;
17094 EVT SVT = VT.getScalarType();
17095 unsigned SVTBits = SVT.getSizeInBits();
17096 const APInt &One = APInt(SVTBits, 1);
17097 unsigned NumElems = VT.getVectorNumElements();
17099 for (unsigned i=0; i !=NumElems; ++i) {
17100 SDValue Op = Amt->getOperand(i);
17101 if (Op->getOpcode() == ISD::UNDEF) {
17102 Elts.push_back(Op);
17106 ConstantSDNode *ND = cast<ConstantSDNode>(Op);
17107 const APInt &C = APInt(SVTBits, ND->getAPIntValue().getZExtValue());
17108 uint64_t ShAmt = C.getZExtValue();
17109 if (ShAmt >= SVTBits) {
17110 Elts.push_back(DAG.getUNDEF(SVT));
17113 Elts.push_back(DAG.getConstant(One.shl(ShAmt), SVT));
17115 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Elts);
17116 return DAG.getNode(ISD::MUL, dl, VT, R, BV);
17119 // Lower SHL with variable shift amount.
17120 if (VT == MVT::v4i32 && Op->getOpcode() == ISD::SHL) {
17121 Op = DAG.getNode(ISD::SHL, dl, VT, Amt, DAG.getConstant(23, VT));
17123 Op = DAG.getNode(ISD::ADD, dl, VT, Op, DAG.getConstant(0x3f800000U, VT));
17124 Op = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, Op);
17125 Op = DAG.getNode(ISD::FP_TO_SINT, dl, VT, Op);
17126 return DAG.getNode(ISD::MUL, dl, VT, Op, R);
17129 // If possible, lower this shift as a sequence of two shifts by
17130 // constant plus a MOVSS/MOVSD instead of scalarizing it.
17132 // (v4i32 (srl A, (build_vector < X, Y, Y, Y>)))
17134 // Could be rewritten as:
17135 // (v4i32 (MOVSS (srl A, <Y,Y,Y,Y>), (srl A, <X,X,X,X>)))
17137 // The advantage is that the two shifts from the example would be
17138 // lowered as X86ISD::VSRLI nodes. This would be cheaper than scalarizing
17139 // the vector shift into four scalar shifts plus four pairs of vector
17141 if ((VT == MVT::v8i16 || VT == MVT::v4i32) &&
17142 ISD::isBuildVectorOfConstantSDNodes(Amt.getNode())) {
17143 unsigned TargetOpcode = X86ISD::MOVSS;
17144 bool CanBeSimplified;
17145 // The splat value for the first packed shift (the 'X' from the example).
17146 SDValue Amt1 = Amt->getOperand(0);
17147 // The splat value for the second packed shift (the 'Y' from the example).
17148 SDValue Amt2 = (VT == MVT::v4i32) ? Amt->getOperand(1) :
17149 Amt->getOperand(2);
17151 // See if it is possible to replace this node with a sequence of
17152 // two shifts followed by a MOVSS/MOVSD
17153 if (VT == MVT::v4i32) {
17154 // Check if it is legal to use a MOVSS.
17155 CanBeSimplified = Amt2 == Amt->getOperand(2) &&
17156 Amt2 == Amt->getOperand(3);
17157 if (!CanBeSimplified) {
17158 // Otherwise, check if we can still simplify this node using a MOVSD.
17159 CanBeSimplified = Amt1 == Amt->getOperand(1) &&
17160 Amt->getOperand(2) == Amt->getOperand(3);
17161 TargetOpcode = X86ISD::MOVSD;
17162 Amt2 = Amt->getOperand(2);
17165 // Do similar checks for the case where the machine value type
17167 CanBeSimplified = Amt1 == Amt->getOperand(1);
17168 for (unsigned i=3; i != 8 && CanBeSimplified; ++i)
17169 CanBeSimplified = Amt2 == Amt->getOperand(i);
17171 if (!CanBeSimplified) {
17172 TargetOpcode = X86ISD::MOVSD;
17173 CanBeSimplified = true;
17174 Amt2 = Amt->getOperand(4);
17175 for (unsigned i=0; i != 4 && CanBeSimplified; ++i)
17176 CanBeSimplified = Amt1 == Amt->getOperand(i);
17177 for (unsigned j=4; j != 8 && CanBeSimplified; ++j)
17178 CanBeSimplified = Amt2 == Amt->getOperand(j);
17182 if (CanBeSimplified && isa<ConstantSDNode>(Amt1) &&
17183 isa<ConstantSDNode>(Amt2)) {
17184 // Replace this node with two shifts followed by a MOVSS/MOVSD.
17185 EVT CastVT = MVT::v4i32;
17187 DAG.getConstant(cast<ConstantSDNode>(Amt1)->getAPIntValue(), VT);
17188 SDValue Shift1 = DAG.getNode(Op->getOpcode(), dl, VT, R, Splat1);
17190 DAG.getConstant(cast<ConstantSDNode>(Amt2)->getAPIntValue(), VT);
17191 SDValue Shift2 = DAG.getNode(Op->getOpcode(), dl, VT, R, Splat2);
17192 if (TargetOpcode == X86ISD::MOVSD)
17193 CastVT = MVT::v2i64;
17194 SDValue BitCast1 = DAG.getNode(ISD::BITCAST, dl, CastVT, Shift1);
17195 SDValue BitCast2 = DAG.getNode(ISD::BITCAST, dl, CastVT, Shift2);
17196 SDValue Result = getTargetShuffleNode(TargetOpcode, dl, CastVT, BitCast2,
17198 return DAG.getNode(ISD::BITCAST, dl, VT, Result);
17202 if (VT == MVT::v16i8 && Op->getOpcode() == ISD::SHL) {
17203 assert(Subtarget->hasSSE2() && "Need SSE2 for pslli/pcmpeq.");
17206 Op = DAG.getNode(ISD::SHL, dl, VT, Amt, DAG.getConstant(5, VT));
17207 Op = DAG.getNode(ISD::BITCAST, dl, VT, Op);
17209 // Turn 'a' into a mask suitable for VSELECT
17210 SDValue VSelM = DAG.getConstant(0x80, VT);
17211 SDValue OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
17212 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
17214 SDValue CM1 = DAG.getConstant(0x0f, VT);
17215 SDValue CM2 = DAG.getConstant(0x3f, VT);
17217 // r = VSELECT(r, psllw(r & (char16)15, 4), a);
17218 SDValue M = DAG.getNode(ISD::AND, dl, VT, R, CM1);
17219 M = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, MVT::v8i16, M, 4, DAG);
17220 M = DAG.getNode(ISD::BITCAST, dl, VT, M);
17221 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel, M, R);
17224 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op);
17225 OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
17226 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
17228 // r = VSELECT(r, psllw(r & (char16)63, 2), a);
17229 M = DAG.getNode(ISD::AND, dl, VT, R, CM2);
17230 M = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, MVT::v8i16, M, 2, DAG);
17231 M = DAG.getNode(ISD::BITCAST, dl, VT, M);
17232 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel, M, R);
17235 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op);
17236 OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
17237 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
17239 // return VSELECT(r, r+r, a);
17240 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel,
17241 DAG.getNode(ISD::ADD, dl, VT, R, R), R);
17245 // It's worth extending once and using the v8i32 shifts for 16-bit types, but
17246 // the extra overheads to get from v16i8 to v8i32 make the existing SSE
17247 // solution better.
17248 if (Subtarget->hasInt256() && VT == MVT::v8i16) {
17249 MVT NewVT = VT == MVT::v8i16 ? MVT::v8i32 : MVT::v16i16;
17251 Op.getOpcode() == ISD::SRA ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
17252 R = DAG.getNode(ExtOpc, dl, NewVT, R);
17253 Amt = DAG.getNode(ISD::ANY_EXTEND, dl, NewVT, Amt);
17254 return DAG.getNode(ISD::TRUNCATE, dl, VT,
17255 DAG.getNode(Op.getOpcode(), dl, NewVT, R, Amt));
17258 // Decompose 256-bit shifts into smaller 128-bit shifts.
17259 if (VT.is256BitVector()) {
17260 unsigned NumElems = VT.getVectorNumElements();
17261 MVT EltVT = VT.getVectorElementType();
17262 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
17264 // Extract the two vectors
17265 SDValue V1 = Extract128BitVector(R, 0, DAG, dl);
17266 SDValue V2 = Extract128BitVector(R, NumElems/2, DAG, dl);
17268 // Recreate the shift amount vectors
17269 SDValue Amt1, Amt2;
17270 if (Amt.getOpcode() == ISD::BUILD_VECTOR) {
17271 // Constant shift amount
17272 SmallVector<SDValue, 4> Amt1Csts;
17273 SmallVector<SDValue, 4> Amt2Csts;
17274 for (unsigned i = 0; i != NumElems/2; ++i)
17275 Amt1Csts.push_back(Amt->getOperand(i));
17276 for (unsigned i = NumElems/2; i != NumElems; ++i)
17277 Amt2Csts.push_back(Amt->getOperand(i));
17279 Amt1 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, Amt1Csts);
17280 Amt2 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, Amt2Csts);
17282 // Variable shift amount
17283 Amt1 = Extract128BitVector(Amt, 0, DAG, dl);
17284 Amt2 = Extract128BitVector(Amt, NumElems/2, DAG, dl);
17287 // Issue new vector shifts for the smaller types
17288 V1 = DAG.getNode(Op.getOpcode(), dl, NewVT, V1, Amt1);
17289 V2 = DAG.getNode(Op.getOpcode(), dl, NewVT, V2, Amt2);
17291 // Concatenate the result back
17292 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, V1, V2);
17298 static SDValue LowerXALUO(SDValue Op, SelectionDAG &DAG) {
17299 // Lower the "add/sub/mul with overflow" instruction into a regular ins plus
17300 // a "setcc" instruction that checks the overflow flag. The "brcond" lowering
17301 // looks for this combo and may remove the "setcc" instruction if the "setcc"
17302 // has only one use.
17303 SDNode *N = Op.getNode();
17304 SDValue LHS = N->getOperand(0);
17305 SDValue RHS = N->getOperand(1);
17306 unsigned BaseOp = 0;
17309 switch (Op.getOpcode()) {
17310 default: llvm_unreachable("Unknown ovf instruction!");
17312 // A subtract of one will be selected as a INC. Note that INC doesn't
17313 // set CF, so we can't do this for UADDO.
17314 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
17316 BaseOp = X86ISD::INC;
17317 Cond = X86::COND_O;
17320 BaseOp = X86ISD::ADD;
17321 Cond = X86::COND_O;
17324 BaseOp = X86ISD::ADD;
17325 Cond = X86::COND_B;
17328 // A subtract of one will be selected as a DEC. Note that DEC doesn't
17329 // set CF, so we can't do this for USUBO.
17330 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
17332 BaseOp = X86ISD::DEC;
17333 Cond = X86::COND_O;
17336 BaseOp = X86ISD::SUB;
17337 Cond = X86::COND_O;
17340 BaseOp = X86ISD::SUB;
17341 Cond = X86::COND_B;
17344 BaseOp = X86ISD::SMUL;
17345 Cond = X86::COND_O;
17347 case ISD::UMULO: { // i64, i8 = umulo lhs, rhs --> i64, i64, i32 umul lhs,rhs
17348 SDVTList VTs = DAG.getVTList(N->getValueType(0), N->getValueType(0),
17350 SDValue Sum = DAG.getNode(X86ISD::UMUL, DL, VTs, LHS, RHS);
17353 DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
17354 DAG.getConstant(X86::COND_O, MVT::i32),
17355 SDValue(Sum.getNode(), 2));
17357 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
17361 // Also sets EFLAGS.
17362 SDVTList VTs = DAG.getVTList(N->getValueType(0), MVT::i32);
17363 SDValue Sum = DAG.getNode(BaseOp, DL, VTs, LHS, RHS);
17366 DAG.getNode(X86ISD::SETCC, DL, N->getValueType(1),
17367 DAG.getConstant(Cond, MVT::i32),
17368 SDValue(Sum.getNode(), 1));
17370 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
17373 // Sign extension of the low part of vector elements. This may be used either
17374 // when sign extend instructions are not available or if the vector element
17375 // sizes already match the sign-extended size. If the vector elements are in
17376 // their pre-extended size and sign extend instructions are available, that will
17377 // be handled by LowerSIGN_EXTEND.
17378 SDValue X86TargetLowering::LowerSIGN_EXTEND_INREG(SDValue Op,
17379 SelectionDAG &DAG) const {
17381 EVT ExtraVT = cast<VTSDNode>(Op.getOperand(1))->getVT();
17382 MVT VT = Op.getSimpleValueType();
17384 if (!Subtarget->hasSSE2() || !VT.isVector())
17387 unsigned BitsDiff = VT.getScalarType().getSizeInBits() -
17388 ExtraVT.getScalarType().getSizeInBits();
17390 switch (VT.SimpleTy) {
17391 default: return SDValue();
17394 if (!Subtarget->hasFp256())
17396 if (!Subtarget->hasInt256()) {
17397 // needs to be split
17398 unsigned NumElems = VT.getVectorNumElements();
17400 // Extract the LHS vectors
17401 SDValue LHS = Op.getOperand(0);
17402 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
17403 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
17405 MVT EltVT = VT.getVectorElementType();
17406 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
17408 EVT ExtraEltVT = ExtraVT.getVectorElementType();
17409 unsigned ExtraNumElems = ExtraVT.getVectorNumElements();
17410 ExtraVT = EVT::getVectorVT(*DAG.getContext(), ExtraEltVT,
17412 SDValue Extra = DAG.getValueType(ExtraVT);
17414 LHS1 = DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, Extra);
17415 LHS2 = DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, Extra);
17417 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, LHS1, LHS2);
17422 SDValue Op0 = Op.getOperand(0);
17424 // This is a sign extension of some low part of vector elements without
17425 // changing the size of the vector elements themselves:
17426 // Shift-Left + Shift-Right-Algebraic.
17427 SDValue Shl = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, Op0,
17429 return getTargetVShiftByConstNode(X86ISD::VSRAI, dl, VT, Shl, BitsDiff,
17435 /// Returns true if the operand type is exactly twice the native width, and
17436 /// the corresponding cmpxchg8b or cmpxchg16b instruction is available.
17437 /// Used to know whether to use cmpxchg8/16b when expanding atomic operations
17438 /// (otherwise we leave them alone to become __sync_fetch_and_... calls).
17439 bool X86TargetLowering::needsCmpXchgNb(const Type *MemType) const {
17440 const X86Subtarget &Subtarget =
17441 getTargetMachine().getSubtarget<X86Subtarget>();
17442 unsigned OpWidth = MemType->getPrimitiveSizeInBits();
17445 return !Subtarget.is64Bit(); // FIXME this should be Subtarget.hasCmpxchg8b
17446 else if (OpWidth == 128)
17447 return Subtarget.hasCmpxchg16b();
17452 bool X86TargetLowering::shouldExpandAtomicStoreInIR(StoreInst *SI) const {
17453 return needsCmpXchgNb(SI->getValueOperand()->getType());
17456 bool X86TargetLowering::shouldExpandAtomicLoadInIR(LoadInst *SI) const {
17457 return false; // FIXME, currently these are expanded separately in this file.
17460 bool X86TargetLowering::shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const {
17461 const X86Subtarget &Subtarget =
17462 getTargetMachine().getSubtarget<X86Subtarget>();
17463 unsigned NativeWidth = Subtarget.is64Bit() ? 64 : 32;
17464 const Type *MemType = AI->getType();
17466 // If the operand is too big, we must see if cmpxchg8/16b is available
17467 // and default to library calls otherwise.
17468 if (MemType->getPrimitiveSizeInBits() > NativeWidth)
17469 return needsCmpXchgNb(MemType);
17471 AtomicRMWInst::BinOp Op = AI->getOperation();
17474 llvm_unreachable("Unknown atomic operation");
17475 case AtomicRMWInst::Xchg:
17476 case AtomicRMWInst::Add:
17477 case AtomicRMWInst::Sub:
17478 // It's better to use xadd, xsub or xchg for these in all cases.
17480 case AtomicRMWInst::Or:
17481 case AtomicRMWInst::And:
17482 case AtomicRMWInst::Xor:
17483 // If the atomicrmw's result isn't actually used, we can just add a "lock"
17484 // prefix to a normal instruction for these operations.
17485 return !AI->use_empty();
17486 case AtomicRMWInst::Nand:
17487 case AtomicRMWInst::Max:
17488 case AtomicRMWInst::Min:
17489 case AtomicRMWInst::UMax:
17490 case AtomicRMWInst::UMin:
17491 // These always require a non-trivial set of data operations on x86. We must
17492 // use a cmpxchg loop.
17497 static SDValue LowerATOMIC_FENCE(SDValue Op, const X86Subtarget *Subtarget,
17498 SelectionDAG &DAG) {
17500 AtomicOrdering FenceOrdering = static_cast<AtomicOrdering>(
17501 cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue());
17502 SynchronizationScope FenceScope = static_cast<SynchronizationScope>(
17503 cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue());
17505 // The only fence that needs an instruction is a sequentially-consistent
17506 // cross-thread fence.
17507 if (FenceOrdering == SequentiallyConsistent && FenceScope == CrossThread) {
17508 // Use mfence if we have SSE2 or we're on x86-64 (even if we asked for
17509 // no-sse2). There isn't any reason to disable it if the target processor
17511 if (Subtarget->hasSSE2() || Subtarget->is64Bit())
17512 return DAG.getNode(X86ISD::MFENCE, dl, MVT::Other, Op.getOperand(0));
17514 SDValue Chain = Op.getOperand(0);
17515 SDValue Zero = DAG.getConstant(0, MVT::i32);
17517 DAG.getRegister(X86::ESP, MVT::i32), // Base
17518 DAG.getTargetConstant(1, MVT::i8), // Scale
17519 DAG.getRegister(0, MVT::i32), // Index
17520 DAG.getTargetConstant(0, MVT::i32), // Disp
17521 DAG.getRegister(0, MVT::i32), // Segment.
17525 SDNode *Res = DAG.getMachineNode(X86::OR32mrLocked, dl, MVT::Other, Ops);
17526 return SDValue(Res, 0);
17529 // MEMBARRIER is a compiler barrier; it codegens to a no-op.
17530 return DAG.getNode(X86ISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0));
17533 static SDValue LowerCMP_SWAP(SDValue Op, const X86Subtarget *Subtarget,
17534 SelectionDAG &DAG) {
17535 MVT T = Op.getSimpleValueType();
17539 switch(T.SimpleTy) {
17540 default: llvm_unreachable("Invalid value type!");
17541 case MVT::i8: Reg = X86::AL; size = 1; break;
17542 case MVT::i16: Reg = X86::AX; size = 2; break;
17543 case MVT::i32: Reg = X86::EAX; size = 4; break;
17545 assert(Subtarget->is64Bit() && "Node not type legal!");
17546 Reg = X86::RAX; size = 8;
17549 SDValue cpIn = DAG.getCopyToReg(Op.getOperand(0), DL, Reg,
17550 Op.getOperand(2), SDValue());
17551 SDValue Ops[] = { cpIn.getValue(0),
17554 DAG.getTargetConstant(size, MVT::i8),
17555 cpIn.getValue(1) };
17556 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
17557 MachineMemOperand *MMO = cast<AtomicSDNode>(Op)->getMemOperand();
17558 SDValue Result = DAG.getMemIntrinsicNode(X86ISD::LCMPXCHG_DAG, DL, Tys,
17562 DAG.getCopyFromReg(Result.getValue(0), DL, Reg, T, Result.getValue(1));
17563 SDValue EFLAGS = DAG.getCopyFromReg(cpOut.getValue(1), DL, X86::EFLAGS,
17564 MVT::i32, cpOut.getValue(2));
17565 SDValue Success = DAG.getNode(X86ISD::SETCC, DL, Op->getValueType(1),
17566 DAG.getConstant(X86::COND_E, MVT::i8), EFLAGS);
17568 DAG.ReplaceAllUsesOfValueWith(Op.getValue(0), cpOut);
17569 DAG.ReplaceAllUsesOfValueWith(Op.getValue(1), Success);
17570 DAG.ReplaceAllUsesOfValueWith(Op.getValue(2), EFLAGS.getValue(1));
17574 static SDValue LowerBITCAST(SDValue Op, const X86Subtarget *Subtarget,
17575 SelectionDAG &DAG) {
17576 MVT SrcVT = Op.getOperand(0).getSimpleValueType();
17577 MVT DstVT = Op.getSimpleValueType();
17579 if (SrcVT == MVT::v2i32 || SrcVT == MVT::v4i16 || SrcVT == MVT::v8i8) {
17580 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
17581 if (DstVT != MVT::f64)
17582 // This conversion needs to be expanded.
17585 SDValue InVec = Op->getOperand(0);
17587 unsigned NumElts = SrcVT.getVectorNumElements();
17588 EVT SVT = SrcVT.getVectorElementType();
17590 // Widen the vector in input in the case of MVT::v2i32.
17591 // Example: from MVT::v2i32 to MVT::v4i32.
17592 SmallVector<SDValue, 16> Elts;
17593 for (unsigned i = 0, e = NumElts; i != e; ++i)
17594 Elts.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, SVT, InVec,
17595 DAG.getIntPtrConstant(i)));
17597 // Explicitly mark the extra elements as Undef.
17598 SDValue Undef = DAG.getUNDEF(SVT);
17599 for (unsigned i = NumElts, e = NumElts * 2; i != e; ++i)
17600 Elts.push_back(Undef);
17602 EVT NewVT = EVT::getVectorVT(*DAG.getContext(), SVT, NumElts * 2);
17603 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, Elts);
17604 SDValue ToV2F64 = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, BV);
17605 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, ToV2F64,
17606 DAG.getIntPtrConstant(0));
17609 assert(Subtarget->is64Bit() && !Subtarget->hasSSE2() &&
17610 Subtarget->hasMMX() && "Unexpected custom BITCAST");
17611 assert((DstVT == MVT::i64 ||
17612 (DstVT.isVector() && DstVT.getSizeInBits()==64)) &&
17613 "Unexpected custom BITCAST");
17614 // i64 <=> MMX conversions are Legal.
17615 if (SrcVT==MVT::i64 && DstVT.isVector())
17617 if (DstVT==MVT::i64 && SrcVT.isVector())
17619 // MMX <=> MMX conversions are Legal.
17620 if (SrcVT.isVector() && DstVT.isVector())
17622 // All other conversions need to be expanded.
17626 static SDValue LowerLOAD_SUB(SDValue Op, SelectionDAG &DAG) {
17627 SDNode *Node = Op.getNode();
17629 EVT T = Node->getValueType(0);
17630 SDValue negOp = DAG.getNode(ISD::SUB, dl, T,
17631 DAG.getConstant(0, T), Node->getOperand(2));
17632 return DAG.getAtomic(ISD::ATOMIC_LOAD_ADD, dl,
17633 cast<AtomicSDNode>(Node)->getMemoryVT(),
17634 Node->getOperand(0),
17635 Node->getOperand(1), negOp,
17636 cast<AtomicSDNode>(Node)->getMemOperand(),
17637 cast<AtomicSDNode>(Node)->getOrdering(),
17638 cast<AtomicSDNode>(Node)->getSynchScope());
17641 static SDValue LowerATOMIC_STORE(SDValue Op, SelectionDAG &DAG) {
17642 SDNode *Node = Op.getNode();
17644 EVT VT = cast<AtomicSDNode>(Node)->getMemoryVT();
17646 // Convert seq_cst store -> xchg
17647 // Convert wide store -> swap (-> cmpxchg8b/cmpxchg16b)
17648 // FIXME: On 32-bit, store -> fist or movq would be more efficient
17649 // (The only way to get a 16-byte store is cmpxchg16b)
17650 // FIXME: 16-byte ATOMIC_SWAP isn't actually hooked up at the moment.
17651 if (cast<AtomicSDNode>(Node)->getOrdering() == SequentiallyConsistent ||
17652 !DAG.getTargetLoweringInfo().isTypeLegal(VT)) {
17653 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_SWAP, dl,
17654 cast<AtomicSDNode>(Node)->getMemoryVT(),
17655 Node->getOperand(0),
17656 Node->getOperand(1), Node->getOperand(2),
17657 cast<AtomicSDNode>(Node)->getMemOperand(),
17658 cast<AtomicSDNode>(Node)->getOrdering(),
17659 cast<AtomicSDNode>(Node)->getSynchScope());
17660 return Swap.getValue(1);
17662 // Other atomic stores have a simple pattern.
17666 static SDValue LowerADDC_ADDE_SUBC_SUBE(SDValue Op, SelectionDAG &DAG) {
17667 EVT VT = Op.getNode()->getSimpleValueType(0);
17669 // Let legalize expand this if it isn't a legal type yet.
17670 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
17673 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
17676 bool ExtraOp = false;
17677 switch (Op.getOpcode()) {
17678 default: llvm_unreachable("Invalid code");
17679 case ISD::ADDC: Opc = X86ISD::ADD; break;
17680 case ISD::ADDE: Opc = X86ISD::ADC; ExtraOp = true; break;
17681 case ISD::SUBC: Opc = X86ISD::SUB; break;
17682 case ISD::SUBE: Opc = X86ISD::SBB; ExtraOp = true; break;
17686 return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0),
17688 return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0),
17689 Op.getOperand(1), Op.getOperand(2));
17692 static SDValue LowerFSINCOS(SDValue Op, const X86Subtarget *Subtarget,
17693 SelectionDAG &DAG) {
17694 assert(Subtarget->isTargetDarwin() && Subtarget->is64Bit());
17696 // For MacOSX, we want to call an alternative entry point: __sincos_stret,
17697 // which returns the values as { float, float } (in XMM0) or
17698 // { double, double } (which is returned in XMM0, XMM1).
17700 SDValue Arg = Op.getOperand(0);
17701 EVT ArgVT = Arg.getValueType();
17702 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
17704 TargetLowering::ArgListTy Args;
17705 TargetLowering::ArgListEntry Entry;
17709 Entry.isSExt = false;
17710 Entry.isZExt = false;
17711 Args.push_back(Entry);
17713 bool isF64 = ArgVT == MVT::f64;
17714 // Only optimize x86_64 for now. i386 is a bit messy. For f32,
17715 // the small struct {f32, f32} is returned in (eax, edx). For f64,
17716 // the results are returned via SRet in memory.
17717 const char *LibcallName = isF64 ? "__sincos_stret" : "__sincosf_stret";
17718 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
17719 SDValue Callee = DAG.getExternalSymbol(LibcallName, TLI.getPointerTy());
17721 Type *RetTy = isF64
17722 ? (Type*)StructType::get(ArgTy, ArgTy, NULL)
17723 : (Type*)VectorType::get(ArgTy, 4);
17725 TargetLowering::CallLoweringInfo CLI(DAG);
17726 CLI.setDebugLoc(dl).setChain(DAG.getEntryNode())
17727 .setCallee(CallingConv::C, RetTy, Callee, std::move(Args), 0);
17729 std::pair<SDValue, SDValue> CallResult = TLI.LowerCallTo(CLI);
17732 // Returned in xmm0 and xmm1.
17733 return CallResult.first;
17735 // Returned in bits 0:31 and 32:64 xmm0.
17736 SDValue SinVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ArgVT,
17737 CallResult.first, DAG.getIntPtrConstant(0));
17738 SDValue CosVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ArgVT,
17739 CallResult.first, DAG.getIntPtrConstant(1));
17740 SDVTList Tys = DAG.getVTList(ArgVT, ArgVT);
17741 return DAG.getNode(ISD::MERGE_VALUES, dl, Tys, SinVal, CosVal);
17744 /// LowerOperation - Provide custom lowering hooks for some operations.
17746 SDValue X86TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
17747 switch (Op.getOpcode()) {
17748 default: llvm_unreachable("Should not custom lower this!");
17749 case ISD::SIGN_EXTEND_INREG: return LowerSIGN_EXTEND_INREG(Op,DAG);
17750 case ISD::ATOMIC_FENCE: return LowerATOMIC_FENCE(Op, Subtarget, DAG);
17751 case ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS:
17752 return LowerCMP_SWAP(Op, Subtarget, DAG);
17753 case ISD::ATOMIC_LOAD_SUB: return LowerLOAD_SUB(Op,DAG);
17754 case ISD::ATOMIC_STORE: return LowerATOMIC_STORE(Op,DAG);
17755 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
17756 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG);
17757 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
17758 case ISD::VSELECT: return LowerVSELECT(Op, DAG);
17759 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
17760 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG);
17761 case ISD::EXTRACT_SUBVECTOR: return LowerEXTRACT_SUBVECTOR(Op,Subtarget,DAG);
17762 case ISD::INSERT_SUBVECTOR: return LowerINSERT_SUBVECTOR(Op, Subtarget,DAG);
17763 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
17764 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
17765 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
17766 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
17767 case ISD::ExternalSymbol: return LowerExternalSymbol(Op, DAG);
17768 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
17769 case ISD::SHL_PARTS:
17770 case ISD::SRA_PARTS:
17771 case ISD::SRL_PARTS: return LowerShiftParts(Op, DAG);
17772 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG);
17773 case ISD::UINT_TO_FP: return LowerUINT_TO_FP(Op, DAG);
17774 case ISD::TRUNCATE: return LowerTRUNCATE(Op, DAG);
17775 case ISD::ZERO_EXTEND: return LowerZERO_EXTEND(Op, Subtarget, DAG);
17776 case ISD::SIGN_EXTEND: return LowerSIGN_EXTEND(Op, Subtarget, DAG);
17777 case ISD::ANY_EXTEND: return LowerANY_EXTEND(Op, Subtarget, DAG);
17778 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG);
17779 case ISD::FP_TO_UINT: return LowerFP_TO_UINT(Op, DAG);
17780 case ISD::FP_EXTEND: return LowerFP_EXTEND(Op, DAG);
17781 case ISD::LOAD: return LowerExtendedLoad(Op, Subtarget, DAG);
17783 case ISD::FNEG: return LowerFABSorFNEG(Op, DAG);
17784 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG);
17785 case ISD::FGETSIGN: return LowerFGETSIGN(Op, DAG);
17786 case ISD::SETCC: return LowerSETCC(Op, DAG);
17787 case ISD::SELECT: return LowerSELECT(Op, DAG);
17788 case ISD::BRCOND: return LowerBRCOND(Op, DAG);
17789 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
17790 case ISD::VASTART: return LowerVASTART(Op, DAG);
17791 case ISD::VAARG: return LowerVAARG(Op, DAG);
17792 case ISD::VACOPY: return LowerVACOPY(Op, Subtarget, DAG);
17793 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
17794 case ISD::INTRINSIC_VOID:
17795 case ISD::INTRINSIC_W_CHAIN: return LowerINTRINSIC_W_CHAIN(Op, Subtarget, DAG);
17796 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
17797 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
17798 case ISD::FRAME_TO_ARGS_OFFSET:
17799 return LowerFRAME_TO_ARGS_OFFSET(Op, DAG);
17800 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
17801 case ISD::EH_RETURN: return LowerEH_RETURN(Op, DAG);
17802 case ISD::EH_SJLJ_SETJMP: return lowerEH_SJLJ_SETJMP(Op, DAG);
17803 case ISD::EH_SJLJ_LONGJMP: return lowerEH_SJLJ_LONGJMP(Op, DAG);
17804 case ISD::INIT_TRAMPOLINE: return LowerINIT_TRAMPOLINE(Op, DAG);
17805 case ISD::ADJUST_TRAMPOLINE: return LowerADJUST_TRAMPOLINE(Op, DAG);
17806 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
17807 case ISD::CTLZ: return LowerCTLZ(Op, DAG);
17808 case ISD::CTLZ_ZERO_UNDEF: return LowerCTLZ_ZERO_UNDEF(Op, DAG);
17809 case ISD::CTTZ: return LowerCTTZ(Op, DAG);
17810 case ISD::MUL: return LowerMUL(Op, Subtarget, DAG);
17811 case ISD::UMUL_LOHI:
17812 case ISD::SMUL_LOHI: return LowerMUL_LOHI(Op, Subtarget, DAG);
17815 case ISD::SHL: return LowerShift(Op, Subtarget, DAG);
17821 case ISD::UMULO: return LowerXALUO(Op, DAG);
17822 case ISD::READCYCLECOUNTER: return LowerREADCYCLECOUNTER(Op, Subtarget,DAG);
17823 case ISD::BITCAST: return LowerBITCAST(Op, Subtarget, DAG);
17827 case ISD::SUBE: return LowerADDC_ADDE_SUBC_SUBE(Op, DAG);
17828 case ISD::ADD: return LowerADD(Op, DAG);
17829 case ISD::SUB: return LowerSUB(Op, DAG);
17830 case ISD::FSINCOS: return LowerFSINCOS(Op, Subtarget, DAG);
17834 static void ReplaceATOMIC_LOAD(SDNode *Node,
17835 SmallVectorImpl<SDValue> &Results,
17836 SelectionDAG &DAG) {
17838 EVT VT = cast<AtomicSDNode>(Node)->getMemoryVT();
17840 // Convert wide load -> cmpxchg8b/cmpxchg16b
17841 // FIXME: On 32-bit, load -> fild or movq would be more efficient
17842 // (The only way to get a 16-byte load is cmpxchg16b)
17843 // FIXME: 16-byte ATOMIC_CMP_SWAP isn't actually hooked up at the moment.
17844 SDValue Zero = DAG.getConstant(0, VT);
17845 SDVTList VTs = DAG.getVTList(VT, MVT::i1, MVT::Other);
17847 DAG.getAtomicCmpSwap(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, dl, VT, VTs,
17848 Node->getOperand(0), Node->getOperand(1), Zero, Zero,
17849 cast<AtomicSDNode>(Node)->getMemOperand(),
17850 cast<AtomicSDNode>(Node)->getOrdering(),
17851 cast<AtomicSDNode>(Node)->getOrdering(),
17852 cast<AtomicSDNode>(Node)->getSynchScope());
17853 Results.push_back(Swap.getValue(0));
17854 Results.push_back(Swap.getValue(2));
17857 /// ReplaceNodeResults - Replace a node with an illegal result type
17858 /// with a new node built out of custom code.
17859 void X86TargetLowering::ReplaceNodeResults(SDNode *N,
17860 SmallVectorImpl<SDValue>&Results,
17861 SelectionDAG &DAG) const {
17863 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
17864 switch (N->getOpcode()) {
17866 llvm_unreachable("Do not know how to custom type legalize this operation!");
17867 case ISD::SIGN_EXTEND_INREG:
17872 // We don't want to expand or promote these.
17879 case ISD::UDIVREM: {
17880 SDValue V = LowerWin64_i128OP(SDValue(N,0), DAG);
17881 Results.push_back(V);
17884 case ISD::FP_TO_SINT:
17885 case ISD::FP_TO_UINT: {
17886 bool IsSigned = N->getOpcode() == ISD::FP_TO_SINT;
17888 if (!IsSigned && !isIntegerTypeFTOL(SDValue(N, 0).getValueType()))
17891 std::pair<SDValue,SDValue> Vals =
17892 FP_TO_INTHelper(SDValue(N, 0), DAG, IsSigned, /*IsReplace=*/ true);
17893 SDValue FIST = Vals.first, StackSlot = Vals.second;
17894 if (FIST.getNode()) {
17895 EVT VT = N->getValueType(0);
17896 // Return a load from the stack slot.
17897 if (StackSlot.getNode())
17898 Results.push_back(DAG.getLoad(VT, dl, FIST, StackSlot,
17899 MachinePointerInfo(),
17900 false, false, false, 0));
17902 Results.push_back(FIST);
17906 case ISD::UINT_TO_FP: {
17907 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
17908 if (N->getOperand(0).getValueType() != MVT::v2i32 ||
17909 N->getValueType(0) != MVT::v2f32)
17911 SDValue ZExtIn = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v2i64,
17913 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL),
17915 SDValue VBias = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2f64, Bias, Bias);
17916 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64, ZExtIn,
17917 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, VBias));
17918 Or = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Or);
17919 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, Or, VBias);
17920 Results.push_back(DAG.getNode(X86ISD::VFPROUND, dl, MVT::v4f32, Sub));
17923 case ISD::FP_ROUND: {
17924 if (!TLI.isTypeLegal(N->getOperand(0).getValueType()))
17926 SDValue V = DAG.getNode(X86ISD::VFPROUND, dl, MVT::v4f32, N->getOperand(0));
17927 Results.push_back(V);
17930 case ISD::INTRINSIC_W_CHAIN: {
17931 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
17933 default : llvm_unreachable("Do not know how to custom type "
17934 "legalize this intrinsic operation!");
17935 case Intrinsic::x86_rdtsc:
17936 return getReadTimeStampCounter(N, dl, X86ISD::RDTSC_DAG, DAG, Subtarget,
17938 case Intrinsic::x86_rdtscp:
17939 return getReadTimeStampCounter(N, dl, X86ISD::RDTSCP_DAG, DAG, Subtarget,
17941 case Intrinsic::x86_rdpmc:
17942 return getReadPerformanceCounter(N, dl, DAG, Subtarget, Results);
17945 case ISD::READCYCLECOUNTER: {
17946 return getReadTimeStampCounter(N, dl, X86ISD::RDTSC_DAG, DAG, Subtarget,
17949 case ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS: {
17950 EVT T = N->getValueType(0);
17951 assert((T == MVT::i64 || T == MVT::i128) && "can only expand cmpxchg pair");
17952 bool Regs64bit = T == MVT::i128;
17953 EVT HalfT = Regs64bit ? MVT::i64 : MVT::i32;
17954 SDValue cpInL, cpInH;
17955 cpInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2),
17956 DAG.getConstant(0, HalfT));
17957 cpInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2),
17958 DAG.getConstant(1, HalfT));
17959 cpInL = DAG.getCopyToReg(N->getOperand(0), dl,
17960 Regs64bit ? X86::RAX : X86::EAX,
17962 cpInH = DAG.getCopyToReg(cpInL.getValue(0), dl,
17963 Regs64bit ? X86::RDX : X86::EDX,
17964 cpInH, cpInL.getValue(1));
17965 SDValue swapInL, swapInH;
17966 swapInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3),
17967 DAG.getConstant(0, HalfT));
17968 swapInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3),
17969 DAG.getConstant(1, HalfT));
17970 swapInL = DAG.getCopyToReg(cpInH.getValue(0), dl,
17971 Regs64bit ? X86::RBX : X86::EBX,
17972 swapInL, cpInH.getValue(1));
17973 swapInH = DAG.getCopyToReg(swapInL.getValue(0), dl,
17974 Regs64bit ? X86::RCX : X86::ECX,
17975 swapInH, swapInL.getValue(1));
17976 SDValue Ops[] = { swapInH.getValue(0),
17978 swapInH.getValue(1) };
17979 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
17980 MachineMemOperand *MMO = cast<AtomicSDNode>(N)->getMemOperand();
17981 unsigned Opcode = Regs64bit ? X86ISD::LCMPXCHG16_DAG :
17982 X86ISD::LCMPXCHG8_DAG;
17983 SDValue Result = DAG.getMemIntrinsicNode(Opcode, dl, Tys, Ops, T, MMO);
17984 SDValue cpOutL = DAG.getCopyFromReg(Result.getValue(0), dl,
17985 Regs64bit ? X86::RAX : X86::EAX,
17986 HalfT, Result.getValue(1));
17987 SDValue cpOutH = DAG.getCopyFromReg(cpOutL.getValue(1), dl,
17988 Regs64bit ? X86::RDX : X86::EDX,
17989 HalfT, cpOutL.getValue(2));
17990 SDValue OpsF[] = { cpOutL.getValue(0), cpOutH.getValue(0)};
17992 SDValue EFLAGS = DAG.getCopyFromReg(cpOutH.getValue(1), dl, X86::EFLAGS,
17993 MVT::i32, cpOutH.getValue(2));
17995 DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
17996 DAG.getConstant(X86::COND_E, MVT::i8), EFLAGS);
17997 Success = DAG.getZExtOrTrunc(Success, dl, N->getValueType(1));
17999 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, T, OpsF));
18000 Results.push_back(Success);
18001 Results.push_back(EFLAGS.getValue(1));
18004 case ISD::ATOMIC_SWAP:
18005 case ISD::ATOMIC_LOAD_ADD:
18006 case ISD::ATOMIC_LOAD_SUB:
18007 case ISD::ATOMIC_LOAD_AND:
18008 case ISD::ATOMIC_LOAD_OR:
18009 case ISD::ATOMIC_LOAD_XOR:
18010 case ISD::ATOMIC_LOAD_NAND:
18011 case ISD::ATOMIC_LOAD_MIN:
18012 case ISD::ATOMIC_LOAD_MAX:
18013 case ISD::ATOMIC_LOAD_UMIN:
18014 case ISD::ATOMIC_LOAD_UMAX:
18015 // Delegate to generic TypeLegalization. Situations we can really handle
18016 // should have already been dealt with by AtomicExpandPass.cpp.
18018 case ISD::ATOMIC_LOAD: {
18019 ReplaceATOMIC_LOAD(N, Results, DAG);
18022 case ISD::BITCAST: {
18023 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
18024 EVT DstVT = N->getValueType(0);
18025 EVT SrcVT = N->getOperand(0)->getValueType(0);
18027 if (SrcVT != MVT::f64 ||
18028 (DstVT != MVT::v2i32 && DstVT != MVT::v4i16 && DstVT != MVT::v8i8))
18031 unsigned NumElts = DstVT.getVectorNumElements();
18032 EVT SVT = DstVT.getVectorElementType();
18033 EVT WiderVT = EVT::getVectorVT(*DAG.getContext(), SVT, NumElts * 2);
18034 SDValue Expanded = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
18035 MVT::v2f64, N->getOperand(0));
18036 SDValue ToVecInt = DAG.getNode(ISD::BITCAST, dl, WiderVT, Expanded);
18038 if (ExperimentalVectorWideningLegalization) {
18039 // If we are legalizing vectors by widening, we already have the desired
18040 // legal vector type, just return it.
18041 Results.push_back(ToVecInt);
18045 SmallVector<SDValue, 8> Elts;
18046 for (unsigned i = 0, e = NumElts; i != e; ++i)
18047 Elts.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, SVT,
18048 ToVecInt, DAG.getIntPtrConstant(i)));
18050 Results.push_back(DAG.getNode(ISD::BUILD_VECTOR, dl, DstVT, Elts));
18055 const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
18057 default: return nullptr;
18058 case X86ISD::BSF: return "X86ISD::BSF";
18059 case X86ISD::BSR: return "X86ISD::BSR";
18060 case X86ISD::SHLD: return "X86ISD::SHLD";
18061 case X86ISD::SHRD: return "X86ISD::SHRD";
18062 case X86ISD::FAND: return "X86ISD::FAND";
18063 case X86ISD::FANDN: return "X86ISD::FANDN";
18064 case X86ISD::FOR: return "X86ISD::FOR";
18065 case X86ISD::FXOR: return "X86ISD::FXOR";
18066 case X86ISD::FSRL: return "X86ISD::FSRL";
18067 case X86ISD::FILD: return "X86ISD::FILD";
18068 case X86ISD::FILD_FLAG: return "X86ISD::FILD_FLAG";
18069 case X86ISD::FP_TO_INT16_IN_MEM: return "X86ISD::FP_TO_INT16_IN_MEM";
18070 case X86ISD::FP_TO_INT32_IN_MEM: return "X86ISD::FP_TO_INT32_IN_MEM";
18071 case X86ISD::FP_TO_INT64_IN_MEM: return "X86ISD::FP_TO_INT64_IN_MEM";
18072 case X86ISD::FLD: return "X86ISD::FLD";
18073 case X86ISD::FST: return "X86ISD::FST";
18074 case X86ISD::CALL: return "X86ISD::CALL";
18075 case X86ISD::RDTSC_DAG: return "X86ISD::RDTSC_DAG";
18076 case X86ISD::RDTSCP_DAG: return "X86ISD::RDTSCP_DAG";
18077 case X86ISD::RDPMC_DAG: return "X86ISD::RDPMC_DAG";
18078 case X86ISD::BT: return "X86ISD::BT";
18079 case X86ISD::CMP: return "X86ISD::CMP";
18080 case X86ISD::COMI: return "X86ISD::COMI";
18081 case X86ISD::UCOMI: return "X86ISD::UCOMI";
18082 case X86ISD::CMPM: return "X86ISD::CMPM";
18083 case X86ISD::CMPMU: return "X86ISD::CMPMU";
18084 case X86ISD::SETCC: return "X86ISD::SETCC";
18085 case X86ISD::SETCC_CARRY: return "X86ISD::SETCC_CARRY";
18086 case X86ISD::FSETCC: return "X86ISD::FSETCC";
18087 case X86ISD::CMOV: return "X86ISD::CMOV";
18088 case X86ISD::BRCOND: return "X86ISD::BRCOND";
18089 case X86ISD::RET_FLAG: return "X86ISD::RET_FLAG";
18090 case X86ISD::REP_STOS: return "X86ISD::REP_STOS";
18091 case X86ISD::REP_MOVS: return "X86ISD::REP_MOVS";
18092 case X86ISD::GlobalBaseReg: return "X86ISD::GlobalBaseReg";
18093 case X86ISD::Wrapper: return "X86ISD::Wrapper";
18094 case X86ISD::WrapperRIP: return "X86ISD::WrapperRIP";
18095 case X86ISD::PEXTRB: return "X86ISD::PEXTRB";
18096 case X86ISD::PEXTRW: return "X86ISD::PEXTRW";
18097 case X86ISD::INSERTPS: return "X86ISD::INSERTPS";
18098 case X86ISD::PINSRB: return "X86ISD::PINSRB";
18099 case X86ISD::PINSRW: return "X86ISD::PINSRW";
18100 case X86ISD::PSHUFB: return "X86ISD::PSHUFB";
18101 case X86ISD::ANDNP: return "X86ISD::ANDNP";
18102 case X86ISD::PSIGN: return "X86ISD::PSIGN";
18103 case X86ISD::BLENDV: return "X86ISD::BLENDV";
18104 case X86ISD::BLENDI: return "X86ISD::BLENDI";
18105 case X86ISD::SUBUS: return "X86ISD::SUBUS";
18106 case X86ISD::HADD: return "X86ISD::HADD";
18107 case X86ISD::HSUB: return "X86ISD::HSUB";
18108 case X86ISD::FHADD: return "X86ISD::FHADD";
18109 case X86ISD::FHSUB: return "X86ISD::FHSUB";
18110 case X86ISD::UMAX: return "X86ISD::UMAX";
18111 case X86ISD::UMIN: return "X86ISD::UMIN";
18112 case X86ISD::SMAX: return "X86ISD::SMAX";
18113 case X86ISD::SMIN: return "X86ISD::SMIN";
18114 case X86ISD::FMAX: return "X86ISD::FMAX";
18115 case X86ISD::FMIN: return "X86ISD::FMIN";
18116 case X86ISD::FMAXC: return "X86ISD::FMAXC";
18117 case X86ISD::FMINC: return "X86ISD::FMINC";
18118 case X86ISD::FRSQRT: return "X86ISD::FRSQRT";
18119 case X86ISD::FRCP: return "X86ISD::FRCP";
18120 case X86ISD::TLSADDR: return "X86ISD::TLSADDR";
18121 case X86ISD::TLSBASEADDR: return "X86ISD::TLSBASEADDR";
18122 case X86ISD::TLSCALL: return "X86ISD::TLSCALL";
18123 case X86ISD::EH_SJLJ_SETJMP: return "X86ISD::EH_SJLJ_SETJMP";
18124 case X86ISD::EH_SJLJ_LONGJMP: return "X86ISD::EH_SJLJ_LONGJMP";
18125 case X86ISD::EH_RETURN: return "X86ISD::EH_RETURN";
18126 case X86ISD::TC_RETURN: return "X86ISD::TC_RETURN";
18127 case X86ISD::FNSTCW16m: return "X86ISD::FNSTCW16m";
18128 case X86ISD::FNSTSW16r: return "X86ISD::FNSTSW16r";
18129 case X86ISD::LCMPXCHG_DAG: return "X86ISD::LCMPXCHG_DAG";
18130 case X86ISD::LCMPXCHG8_DAG: return "X86ISD::LCMPXCHG8_DAG";
18131 case X86ISD::LCMPXCHG16_DAG: return "X86ISD::LCMPXCHG16_DAG";
18132 case X86ISD::VZEXT_MOVL: return "X86ISD::VZEXT_MOVL";
18133 case X86ISD::VZEXT_LOAD: return "X86ISD::VZEXT_LOAD";
18134 case X86ISD::VZEXT: return "X86ISD::VZEXT";
18135 case X86ISD::VSEXT: return "X86ISD::VSEXT";
18136 case X86ISD::VTRUNC: return "X86ISD::VTRUNC";
18137 case X86ISD::VTRUNCM: return "X86ISD::VTRUNCM";
18138 case X86ISD::VINSERT: return "X86ISD::VINSERT";
18139 case X86ISD::VFPEXT: return "X86ISD::VFPEXT";
18140 case X86ISD::VFPROUND: return "X86ISD::VFPROUND";
18141 case X86ISD::VSHLDQ: return "X86ISD::VSHLDQ";
18142 case X86ISD::VSRLDQ: return "X86ISD::VSRLDQ";
18143 case X86ISD::VSHL: return "X86ISD::VSHL";
18144 case X86ISD::VSRL: return "X86ISD::VSRL";
18145 case X86ISD::VSRA: return "X86ISD::VSRA";
18146 case X86ISD::VSHLI: return "X86ISD::VSHLI";
18147 case X86ISD::VSRLI: return "X86ISD::VSRLI";
18148 case X86ISD::VSRAI: return "X86ISD::VSRAI";
18149 case X86ISD::CMPP: return "X86ISD::CMPP";
18150 case X86ISD::PCMPEQ: return "X86ISD::PCMPEQ";
18151 case X86ISD::PCMPGT: return "X86ISD::PCMPGT";
18152 case X86ISD::PCMPEQM: return "X86ISD::PCMPEQM";
18153 case X86ISD::PCMPGTM: return "X86ISD::PCMPGTM";
18154 case X86ISD::ADD: return "X86ISD::ADD";
18155 case X86ISD::SUB: return "X86ISD::SUB";
18156 case X86ISD::ADC: return "X86ISD::ADC";
18157 case X86ISD::SBB: return "X86ISD::SBB";
18158 case X86ISD::SMUL: return "X86ISD::SMUL";
18159 case X86ISD::UMUL: return "X86ISD::UMUL";
18160 case X86ISD::INC: return "X86ISD::INC";
18161 case X86ISD::DEC: return "X86ISD::DEC";
18162 case X86ISD::OR: return "X86ISD::OR";
18163 case X86ISD::XOR: return "X86ISD::XOR";
18164 case X86ISD::AND: return "X86ISD::AND";
18165 case X86ISD::BEXTR: return "X86ISD::BEXTR";
18166 case X86ISD::MUL_IMM: return "X86ISD::MUL_IMM";
18167 case X86ISD::PTEST: return "X86ISD::PTEST";
18168 case X86ISD::TESTP: return "X86ISD::TESTP";
18169 case X86ISD::TESTM: return "X86ISD::TESTM";
18170 case X86ISD::TESTNM: return "X86ISD::TESTNM";
18171 case X86ISD::KORTEST: return "X86ISD::KORTEST";
18172 case X86ISD::PACKSS: return "X86ISD::PACKSS";
18173 case X86ISD::PACKUS: return "X86ISD::PACKUS";
18174 case X86ISD::PALIGNR: return "X86ISD::PALIGNR";
18175 case X86ISD::VALIGN: return "X86ISD::VALIGN";
18176 case X86ISD::PSHUFD: return "X86ISD::PSHUFD";
18177 case X86ISD::PSHUFHW: return "X86ISD::PSHUFHW";
18178 case X86ISD::PSHUFLW: return "X86ISD::PSHUFLW";
18179 case X86ISD::SHUFP: return "X86ISD::SHUFP";
18180 case X86ISD::MOVLHPS: return "X86ISD::MOVLHPS";
18181 case X86ISD::MOVLHPD: return "X86ISD::MOVLHPD";
18182 case X86ISD::MOVHLPS: return "X86ISD::MOVHLPS";
18183 case X86ISD::MOVLPS: return "X86ISD::MOVLPS";
18184 case X86ISD::MOVLPD: return "X86ISD::MOVLPD";
18185 case X86ISD::MOVDDUP: return "X86ISD::MOVDDUP";
18186 case X86ISD::MOVSHDUP: return "X86ISD::MOVSHDUP";
18187 case X86ISD::MOVSLDUP: return "X86ISD::MOVSLDUP";
18188 case X86ISD::MOVSD: return "X86ISD::MOVSD";
18189 case X86ISD::MOVSS: return "X86ISD::MOVSS";
18190 case X86ISD::UNPCKL: return "X86ISD::UNPCKL";
18191 case X86ISD::UNPCKH: return "X86ISD::UNPCKH";
18192 case X86ISD::VBROADCAST: return "X86ISD::VBROADCAST";
18193 case X86ISD::VBROADCASTM: return "X86ISD::VBROADCASTM";
18194 case X86ISD::VEXTRACT: return "X86ISD::VEXTRACT";
18195 case X86ISD::VPERMILPI: return "X86ISD::VPERMILPI";
18196 case X86ISD::VPERM2X128: return "X86ISD::VPERM2X128";
18197 case X86ISD::VPERMV: return "X86ISD::VPERMV";
18198 case X86ISD::VPERMV3: return "X86ISD::VPERMV3";
18199 case X86ISD::VPERMIV3: return "X86ISD::VPERMIV3";
18200 case X86ISD::VPERMI: return "X86ISD::VPERMI";
18201 case X86ISD::PMULUDQ: return "X86ISD::PMULUDQ";
18202 case X86ISD::PMULDQ: return "X86ISD::PMULDQ";
18203 case X86ISD::VASTART_SAVE_XMM_REGS: return "X86ISD::VASTART_SAVE_XMM_REGS";
18204 case X86ISD::VAARG_64: return "X86ISD::VAARG_64";
18205 case X86ISD::WIN_ALLOCA: return "X86ISD::WIN_ALLOCA";
18206 case X86ISD::MEMBARRIER: return "X86ISD::MEMBARRIER";
18207 case X86ISD::SEG_ALLOCA: return "X86ISD::SEG_ALLOCA";
18208 case X86ISD::WIN_FTOL: return "X86ISD::WIN_FTOL";
18209 case X86ISD::SAHF: return "X86ISD::SAHF";
18210 case X86ISD::RDRAND: return "X86ISD::RDRAND";
18211 case X86ISD::RDSEED: return "X86ISD::RDSEED";
18212 case X86ISD::FMADD: return "X86ISD::FMADD";
18213 case X86ISD::FMSUB: return "X86ISD::FMSUB";
18214 case X86ISD::FNMADD: return "X86ISD::FNMADD";
18215 case X86ISD::FNMSUB: return "X86ISD::FNMSUB";
18216 case X86ISD::FMADDSUB: return "X86ISD::FMADDSUB";
18217 case X86ISD::FMSUBADD: return "X86ISD::FMSUBADD";
18218 case X86ISD::PCMPESTRI: return "X86ISD::PCMPESTRI";
18219 case X86ISD::PCMPISTRI: return "X86ISD::PCMPISTRI";
18220 case X86ISD::XTEST: return "X86ISD::XTEST";
18224 // isLegalAddressingMode - Return true if the addressing mode represented
18225 // by AM is legal for this target, for a load/store of the specified type.
18226 bool X86TargetLowering::isLegalAddressingMode(const AddrMode &AM,
18228 // X86 supports extremely general addressing modes.
18229 CodeModel::Model M = getTargetMachine().getCodeModel();
18230 Reloc::Model R = getTargetMachine().getRelocationModel();
18232 // X86 allows a sign-extended 32-bit immediate field as a displacement.
18233 if (!X86::isOffsetSuitableForCodeModel(AM.BaseOffs, M, AM.BaseGV != nullptr))
18238 Subtarget->ClassifyGlobalReference(AM.BaseGV, getTargetMachine());
18240 // If a reference to this global requires an extra load, we can't fold it.
18241 if (isGlobalStubReference(GVFlags))
18244 // If BaseGV requires a register for the PIC base, we cannot also have a
18245 // BaseReg specified.
18246 if (AM.HasBaseReg && isGlobalRelativeToPICBase(GVFlags))
18249 // If lower 4G is not available, then we must use rip-relative addressing.
18250 if ((M != CodeModel::Small || R != Reloc::Static) &&
18251 Subtarget->is64Bit() && (AM.BaseOffs || AM.Scale > 1))
18255 switch (AM.Scale) {
18261 // These scales always work.
18266 // These scales are formed with basereg+scalereg. Only accept if there is
18271 default: // Other stuff never works.
18278 bool X86TargetLowering::isVectorShiftByScalarCheap(Type *Ty) const {
18279 unsigned Bits = Ty->getScalarSizeInBits();
18281 // 8-bit shifts are always expensive, but versions with a scalar amount aren't
18282 // particularly cheaper than those without.
18286 // On AVX2 there are new vpsllv[dq] instructions (and other shifts), that make
18287 // variable shifts just as cheap as scalar ones.
18288 if (Subtarget->hasInt256() && (Bits == 32 || Bits == 64))
18291 // Otherwise, it's significantly cheaper to shift by a scalar amount than by a
18292 // fully general vector.
18296 bool X86TargetLowering::isTruncateFree(Type *Ty1, Type *Ty2) const {
18297 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
18299 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits();
18300 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits();
18301 return NumBits1 > NumBits2;
18304 bool X86TargetLowering::allowTruncateForTailCall(Type *Ty1, Type *Ty2) const {
18305 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
18308 if (!isTypeLegal(EVT::getEVT(Ty1)))
18311 assert(Ty1->getPrimitiveSizeInBits() <= 64 && "i128 is probably not a noop");
18313 // Assuming the caller doesn't have a zeroext or signext return parameter,
18314 // truncation all the way down to i1 is valid.
18318 bool X86TargetLowering::isLegalICmpImmediate(int64_t Imm) const {
18319 return isInt<32>(Imm);
18322 bool X86TargetLowering::isLegalAddImmediate(int64_t Imm) const {
18323 // Can also use sub to handle negated immediates.
18324 return isInt<32>(Imm);
18327 bool X86TargetLowering::isTruncateFree(EVT VT1, EVT VT2) const {
18328 if (!VT1.isInteger() || !VT2.isInteger())
18330 unsigned NumBits1 = VT1.getSizeInBits();
18331 unsigned NumBits2 = VT2.getSizeInBits();
18332 return NumBits1 > NumBits2;
18335 bool X86TargetLowering::isZExtFree(Type *Ty1, Type *Ty2) const {
18336 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
18337 return Ty1->isIntegerTy(32) && Ty2->isIntegerTy(64) && Subtarget->is64Bit();
18340 bool X86TargetLowering::isZExtFree(EVT VT1, EVT VT2) const {
18341 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
18342 return VT1 == MVT::i32 && VT2 == MVT::i64 && Subtarget->is64Bit();
18345 bool X86TargetLowering::isZExtFree(SDValue Val, EVT VT2) const {
18346 EVT VT1 = Val.getValueType();
18347 if (isZExtFree(VT1, VT2))
18350 if (Val.getOpcode() != ISD::LOAD)
18353 if (!VT1.isSimple() || !VT1.isInteger() ||
18354 !VT2.isSimple() || !VT2.isInteger())
18357 switch (VT1.getSimpleVT().SimpleTy) {
18362 // X86 has 8, 16, and 32-bit zero-extending loads.
18370 X86TargetLowering::isFMAFasterThanFMulAndFAdd(EVT VT) const {
18371 if (!(Subtarget->hasFMA() || Subtarget->hasFMA4()))
18374 VT = VT.getScalarType();
18376 if (!VT.isSimple())
18379 switch (VT.getSimpleVT().SimpleTy) {
18390 bool X86TargetLowering::isNarrowingProfitable(EVT VT1, EVT VT2) const {
18391 // i16 instructions are longer (0x66 prefix) and potentially slower.
18392 return !(VT1 == MVT::i32 && VT2 == MVT::i16);
18395 /// isShuffleMaskLegal - Targets can use this to indicate that they only
18396 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
18397 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
18398 /// are assumed to be legal.
18400 X86TargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M,
18402 if (!VT.isSimple())
18405 MVT SVT = VT.getSimpleVT();
18407 // Very little shuffling can be done for 64-bit vectors right now.
18408 if (VT.getSizeInBits() == 64)
18411 // If this is a single-input shuffle with no 128 bit lane crossings we can
18412 // lower it into pshufb.
18413 if ((SVT.is128BitVector() && Subtarget->hasSSSE3()) ||
18414 (SVT.is256BitVector() && Subtarget->hasInt256())) {
18415 bool isLegal = true;
18416 for (unsigned I = 0, E = M.size(); I != E; ++I) {
18417 if (M[I] >= (int)SVT.getVectorNumElements() ||
18418 ShuffleCrosses128bitLane(SVT, I, M[I])) {
18427 // FIXME: blends, shifts.
18428 return (SVT.getVectorNumElements() == 2 ||
18429 ShuffleVectorSDNode::isSplatMask(&M[0], VT) ||
18430 isMOVLMask(M, SVT) ||
18431 isMOVHLPSMask(M, SVT) ||
18432 isSHUFPMask(M, SVT) ||
18433 isPSHUFDMask(M, SVT) ||
18434 isPSHUFHWMask(M, SVT, Subtarget->hasInt256()) ||
18435 isPSHUFLWMask(M, SVT, Subtarget->hasInt256()) ||
18436 isPALIGNRMask(M, SVT, Subtarget) ||
18437 isUNPCKLMask(M, SVT, Subtarget->hasInt256()) ||
18438 isUNPCKHMask(M, SVT, Subtarget->hasInt256()) ||
18439 isUNPCKL_v_undef_Mask(M, SVT, Subtarget->hasInt256()) ||
18440 isUNPCKH_v_undef_Mask(M, SVT, Subtarget->hasInt256()) ||
18441 isBlendMask(M, SVT, Subtarget->hasSSE41(), Subtarget->hasInt256()));
18445 X86TargetLowering::isVectorClearMaskLegal(const SmallVectorImpl<int> &Mask,
18447 if (!VT.isSimple())
18450 MVT SVT = VT.getSimpleVT();
18451 unsigned NumElts = SVT.getVectorNumElements();
18452 // FIXME: This collection of masks seems suspect.
18455 if (NumElts == 4 && SVT.is128BitVector()) {
18456 return (isMOVLMask(Mask, SVT) ||
18457 isCommutedMOVLMask(Mask, SVT, true) ||
18458 isSHUFPMask(Mask, SVT) ||
18459 isSHUFPMask(Mask, SVT, /* Commuted */ true));
18464 //===----------------------------------------------------------------------===//
18465 // X86 Scheduler Hooks
18466 //===----------------------------------------------------------------------===//
18468 /// Utility function to emit xbegin specifying the start of an RTM region.
18469 static MachineBasicBlock *EmitXBegin(MachineInstr *MI, MachineBasicBlock *MBB,
18470 const TargetInstrInfo *TII) {
18471 DebugLoc DL = MI->getDebugLoc();
18473 const BasicBlock *BB = MBB->getBasicBlock();
18474 MachineFunction::iterator I = MBB;
18477 // For the v = xbegin(), we generate
18488 MachineBasicBlock *thisMBB = MBB;
18489 MachineFunction *MF = MBB->getParent();
18490 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
18491 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
18492 MF->insert(I, mainMBB);
18493 MF->insert(I, sinkMBB);
18495 // Transfer the remainder of BB and its successor edges to sinkMBB.
18496 sinkMBB->splice(sinkMBB->begin(), MBB,
18497 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
18498 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
18502 // # fallthrough to mainMBB
18503 // # abortion to sinkMBB
18504 BuildMI(thisMBB, DL, TII->get(X86::XBEGIN_4)).addMBB(sinkMBB);
18505 thisMBB->addSuccessor(mainMBB);
18506 thisMBB->addSuccessor(sinkMBB);
18510 BuildMI(mainMBB, DL, TII->get(X86::MOV32ri), X86::EAX).addImm(-1);
18511 mainMBB->addSuccessor(sinkMBB);
18514 // EAX is live into the sinkMBB
18515 sinkMBB->addLiveIn(X86::EAX);
18516 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
18517 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
18520 MI->eraseFromParent();
18524 // FIXME: When we get size specific XMM0 registers, i.e. XMM0_V16I8
18525 // or XMM0_V32I8 in AVX all of this code can be replaced with that
18526 // in the .td file.
18527 static MachineBasicBlock *EmitPCMPSTRM(MachineInstr *MI, MachineBasicBlock *BB,
18528 const TargetInstrInfo *TII) {
18530 switch (MI->getOpcode()) {
18531 default: llvm_unreachable("illegal opcode!");
18532 case X86::PCMPISTRM128REG: Opc = X86::PCMPISTRM128rr; break;
18533 case X86::VPCMPISTRM128REG: Opc = X86::VPCMPISTRM128rr; break;
18534 case X86::PCMPISTRM128MEM: Opc = X86::PCMPISTRM128rm; break;
18535 case X86::VPCMPISTRM128MEM: Opc = X86::VPCMPISTRM128rm; break;
18536 case X86::PCMPESTRM128REG: Opc = X86::PCMPESTRM128rr; break;
18537 case X86::VPCMPESTRM128REG: Opc = X86::VPCMPESTRM128rr; break;
18538 case X86::PCMPESTRM128MEM: Opc = X86::PCMPESTRM128rm; break;
18539 case X86::VPCMPESTRM128MEM: Opc = X86::VPCMPESTRM128rm; break;
18542 DebugLoc dl = MI->getDebugLoc();
18543 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(Opc));
18545 unsigned NumArgs = MI->getNumOperands();
18546 for (unsigned i = 1; i < NumArgs; ++i) {
18547 MachineOperand &Op = MI->getOperand(i);
18548 if (!(Op.isReg() && Op.isImplicit()))
18549 MIB.addOperand(Op);
18551 if (MI->hasOneMemOperand())
18552 MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
18554 BuildMI(*BB, MI, dl,
18555 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
18556 .addReg(X86::XMM0);
18558 MI->eraseFromParent();
18562 // FIXME: Custom handling because TableGen doesn't support multiple implicit
18563 // defs in an instruction pattern
18564 static MachineBasicBlock *EmitPCMPSTRI(MachineInstr *MI, MachineBasicBlock *BB,
18565 const TargetInstrInfo *TII) {
18567 switch (MI->getOpcode()) {
18568 default: llvm_unreachable("illegal opcode!");
18569 case X86::PCMPISTRIREG: Opc = X86::PCMPISTRIrr; break;
18570 case X86::VPCMPISTRIREG: Opc = X86::VPCMPISTRIrr; break;
18571 case X86::PCMPISTRIMEM: Opc = X86::PCMPISTRIrm; break;
18572 case X86::VPCMPISTRIMEM: Opc = X86::VPCMPISTRIrm; break;
18573 case X86::PCMPESTRIREG: Opc = X86::PCMPESTRIrr; break;
18574 case X86::VPCMPESTRIREG: Opc = X86::VPCMPESTRIrr; break;
18575 case X86::PCMPESTRIMEM: Opc = X86::PCMPESTRIrm; break;
18576 case X86::VPCMPESTRIMEM: Opc = X86::VPCMPESTRIrm; break;
18579 DebugLoc dl = MI->getDebugLoc();
18580 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(Opc));
18582 unsigned NumArgs = MI->getNumOperands(); // remove the results
18583 for (unsigned i = 1; i < NumArgs; ++i) {
18584 MachineOperand &Op = MI->getOperand(i);
18585 if (!(Op.isReg() && Op.isImplicit()))
18586 MIB.addOperand(Op);
18588 if (MI->hasOneMemOperand())
18589 MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
18591 BuildMI(*BB, MI, dl,
18592 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
18595 MI->eraseFromParent();
18599 static MachineBasicBlock * EmitMonitor(MachineInstr *MI, MachineBasicBlock *BB,
18600 const TargetInstrInfo *TII,
18601 const X86Subtarget* Subtarget) {
18602 DebugLoc dl = MI->getDebugLoc();
18604 // Address into RAX/EAX, other two args into ECX, EDX.
18605 unsigned MemOpc = Subtarget->is64Bit() ? X86::LEA64r : X86::LEA32r;
18606 unsigned MemReg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
18607 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(MemOpc), MemReg);
18608 for (int i = 0; i < X86::AddrNumOperands; ++i)
18609 MIB.addOperand(MI->getOperand(i));
18611 unsigned ValOps = X86::AddrNumOperands;
18612 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::ECX)
18613 .addReg(MI->getOperand(ValOps).getReg());
18614 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::EDX)
18615 .addReg(MI->getOperand(ValOps+1).getReg());
18617 // The instruction doesn't actually take any operands though.
18618 BuildMI(*BB, MI, dl, TII->get(X86::MONITORrrr));
18620 MI->eraseFromParent(); // The pseudo is gone now.
18624 MachineBasicBlock *
18625 X86TargetLowering::EmitVAARG64WithCustomInserter(
18627 MachineBasicBlock *MBB) const {
18628 // Emit va_arg instruction on X86-64.
18630 // Operands to this pseudo-instruction:
18631 // 0 ) Output : destination address (reg)
18632 // 1-5) Input : va_list address (addr, i64mem)
18633 // 6 ) ArgSize : Size (in bytes) of vararg type
18634 // 7 ) ArgMode : 0=overflow only, 1=use gp_offset, 2=use fp_offset
18635 // 8 ) Align : Alignment of type
18636 // 9 ) EFLAGS (implicit-def)
18638 assert(MI->getNumOperands() == 10 && "VAARG_64 should have 10 operands!");
18639 assert(X86::AddrNumOperands == 5 && "VAARG_64 assumes 5 address operands");
18641 unsigned DestReg = MI->getOperand(0).getReg();
18642 MachineOperand &Base = MI->getOperand(1);
18643 MachineOperand &Scale = MI->getOperand(2);
18644 MachineOperand &Index = MI->getOperand(3);
18645 MachineOperand &Disp = MI->getOperand(4);
18646 MachineOperand &Segment = MI->getOperand(5);
18647 unsigned ArgSize = MI->getOperand(6).getImm();
18648 unsigned ArgMode = MI->getOperand(7).getImm();
18649 unsigned Align = MI->getOperand(8).getImm();
18651 // Memory Reference
18652 assert(MI->hasOneMemOperand() && "Expected VAARG_64 to have one memoperand");
18653 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
18654 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
18656 // Machine Information
18657 const TargetInstrInfo *TII = MBB->getParent()->getSubtarget().getInstrInfo();
18658 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
18659 const TargetRegisterClass *AddrRegClass = getRegClassFor(MVT::i64);
18660 const TargetRegisterClass *OffsetRegClass = getRegClassFor(MVT::i32);
18661 DebugLoc DL = MI->getDebugLoc();
18663 // struct va_list {
18666 // i64 overflow_area (address)
18667 // i64 reg_save_area (address)
18669 // sizeof(va_list) = 24
18670 // alignment(va_list) = 8
18672 unsigned TotalNumIntRegs = 6;
18673 unsigned TotalNumXMMRegs = 8;
18674 bool UseGPOffset = (ArgMode == 1);
18675 bool UseFPOffset = (ArgMode == 2);
18676 unsigned MaxOffset = TotalNumIntRegs * 8 +
18677 (UseFPOffset ? TotalNumXMMRegs * 16 : 0);
18679 /* Align ArgSize to a multiple of 8 */
18680 unsigned ArgSizeA8 = (ArgSize + 7) & ~7;
18681 bool NeedsAlign = (Align > 8);
18683 MachineBasicBlock *thisMBB = MBB;
18684 MachineBasicBlock *overflowMBB;
18685 MachineBasicBlock *offsetMBB;
18686 MachineBasicBlock *endMBB;
18688 unsigned OffsetDestReg = 0; // Argument address computed by offsetMBB
18689 unsigned OverflowDestReg = 0; // Argument address computed by overflowMBB
18690 unsigned OffsetReg = 0;
18692 if (!UseGPOffset && !UseFPOffset) {
18693 // If we only pull from the overflow region, we don't create a branch.
18694 // We don't need to alter control flow.
18695 OffsetDestReg = 0; // unused
18696 OverflowDestReg = DestReg;
18698 offsetMBB = nullptr;
18699 overflowMBB = thisMBB;
18702 // First emit code to check if gp_offset (or fp_offset) is below the bound.
18703 // If so, pull the argument from reg_save_area. (branch to offsetMBB)
18704 // If not, pull from overflow_area. (branch to overflowMBB)
18709 // offsetMBB overflowMBB
18714 // Registers for the PHI in endMBB
18715 OffsetDestReg = MRI.createVirtualRegister(AddrRegClass);
18716 OverflowDestReg = MRI.createVirtualRegister(AddrRegClass);
18718 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
18719 MachineFunction *MF = MBB->getParent();
18720 overflowMBB = MF->CreateMachineBasicBlock(LLVM_BB);
18721 offsetMBB = MF->CreateMachineBasicBlock(LLVM_BB);
18722 endMBB = MF->CreateMachineBasicBlock(LLVM_BB);
18724 MachineFunction::iterator MBBIter = MBB;
18727 // Insert the new basic blocks
18728 MF->insert(MBBIter, offsetMBB);
18729 MF->insert(MBBIter, overflowMBB);
18730 MF->insert(MBBIter, endMBB);
18732 // Transfer the remainder of MBB and its successor edges to endMBB.
18733 endMBB->splice(endMBB->begin(), thisMBB,
18734 std::next(MachineBasicBlock::iterator(MI)), thisMBB->end());
18735 endMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
18737 // Make offsetMBB and overflowMBB successors of thisMBB
18738 thisMBB->addSuccessor(offsetMBB);
18739 thisMBB->addSuccessor(overflowMBB);
18741 // endMBB is a successor of both offsetMBB and overflowMBB
18742 offsetMBB->addSuccessor(endMBB);
18743 overflowMBB->addSuccessor(endMBB);
18745 // Load the offset value into a register
18746 OffsetReg = MRI.createVirtualRegister(OffsetRegClass);
18747 BuildMI(thisMBB, DL, TII->get(X86::MOV32rm), OffsetReg)
18751 .addDisp(Disp, UseFPOffset ? 4 : 0)
18752 .addOperand(Segment)
18753 .setMemRefs(MMOBegin, MMOEnd);
18755 // Check if there is enough room left to pull this argument.
18756 BuildMI(thisMBB, DL, TII->get(X86::CMP32ri))
18758 .addImm(MaxOffset + 8 - ArgSizeA8);
18760 // Branch to "overflowMBB" if offset >= max
18761 // Fall through to "offsetMBB" otherwise
18762 BuildMI(thisMBB, DL, TII->get(X86::GetCondBranchFromCond(X86::COND_AE)))
18763 .addMBB(overflowMBB);
18766 // In offsetMBB, emit code to use the reg_save_area.
18768 assert(OffsetReg != 0);
18770 // Read the reg_save_area address.
18771 unsigned RegSaveReg = MRI.createVirtualRegister(AddrRegClass);
18772 BuildMI(offsetMBB, DL, TII->get(X86::MOV64rm), RegSaveReg)
18777 .addOperand(Segment)
18778 .setMemRefs(MMOBegin, MMOEnd);
18780 // Zero-extend the offset
18781 unsigned OffsetReg64 = MRI.createVirtualRegister(AddrRegClass);
18782 BuildMI(offsetMBB, DL, TII->get(X86::SUBREG_TO_REG), OffsetReg64)
18785 .addImm(X86::sub_32bit);
18787 // Add the offset to the reg_save_area to get the final address.
18788 BuildMI(offsetMBB, DL, TII->get(X86::ADD64rr), OffsetDestReg)
18789 .addReg(OffsetReg64)
18790 .addReg(RegSaveReg);
18792 // Compute the offset for the next argument
18793 unsigned NextOffsetReg = MRI.createVirtualRegister(OffsetRegClass);
18794 BuildMI(offsetMBB, DL, TII->get(X86::ADD32ri), NextOffsetReg)
18796 .addImm(UseFPOffset ? 16 : 8);
18798 // Store it back into the va_list.
18799 BuildMI(offsetMBB, DL, TII->get(X86::MOV32mr))
18803 .addDisp(Disp, UseFPOffset ? 4 : 0)
18804 .addOperand(Segment)
18805 .addReg(NextOffsetReg)
18806 .setMemRefs(MMOBegin, MMOEnd);
18809 BuildMI(offsetMBB, DL, TII->get(X86::JMP_4))
18814 // Emit code to use overflow area
18817 // Load the overflow_area address into a register.
18818 unsigned OverflowAddrReg = MRI.createVirtualRegister(AddrRegClass);
18819 BuildMI(overflowMBB, DL, TII->get(X86::MOV64rm), OverflowAddrReg)
18824 .addOperand(Segment)
18825 .setMemRefs(MMOBegin, MMOEnd);
18827 // If we need to align it, do so. Otherwise, just copy the address
18828 // to OverflowDestReg.
18830 // Align the overflow address
18831 assert((Align & (Align-1)) == 0 && "Alignment must be a power of 2");
18832 unsigned TmpReg = MRI.createVirtualRegister(AddrRegClass);
18834 // aligned_addr = (addr + (align-1)) & ~(align-1)
18835 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), TmpReg)
18836 .addReg(OverflowAddrReg)
18839 BuildMI(overflowMBB, DL, TII->get(X86::AND64ri32), OverflowDestReg)
18841 .addImm(~(uint64_t)(Align-1));
18843 BuildMI(overflowMBB, DL, TII->get(TargetOpcode::COPY), OverflowDestReg)
18844 .addReg(OverflowAddrReg);
18847 // Compute the next overflow address after this argument.
18848 // (the overflow address should be kept 8-byte aligned)
18849 unsigned NextAddrReg = MRI.createVirtualRegister(AddrRegClass);
18850 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), NextAddrReg)
18851 .addReg(OverflowDestReg)
18852 .addImm(ArgSizeA8);
18854 // Store the new overflow address.
18855 BuildMI(overflowMBB, DL, TII->get(X86::MOV64mr))
18860 .addOperand(Segment)
18861 .addReg(NextAddrReg)
18862 .setMemRefs(MMOBegin, MMOEnd);
18864 // If we branched, emit the PHI to the front of endMBB.
18866 BuildMI(*endMBB, endMBB->begin(), DL,
18867 TII->get(X86::PHI), DestReg)
18868 .addReg(OffsetDestReg).addMBB(offsetMBB)
18869 .addReg(OverflowDestReg).addMBB(overflowMBB);
18872 // Erase the pseudo instruction
18873 MI->eraseFromParent();
18878 MachineBasicBlock *
18879 X86TargetLowering::EmitVAStartSaveXMMRegsWithCustomInserter(
18881 MachineBasicBlock *MBB) const {
18882 // Emit code to save XMM registers to the stack. The ABI says that the
18883 // number of registers to save is given in %al, so it's theoretically
18884 // possible to do an indirect jump trick to avoid saving all of them,
18885 // however this code takes a simpler approach and just executes all
18886 // of the stores if %al is non-zero. It's less code, and it's probably
18887 // easier on the hardware branch predictor, and stores aren't all that
18888 // expensive anyway.
18890 // Create the new basic blocks. One block contains all the XMM stores,
18891 // and one block is the final destination regardless of whether any
18892 // stores were performed.
18893 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
18894 MachineFunction *F = MBB->getParent();
18895 MachineFunction::iterator MBBIter = MBB;
18897 MachineBasicBlock *XMMSaveMBB = F->CreateMachineBasicBlock(LLVM_BB);
18898 MachineBasicBlock *EndMBB = F->CreateMachineBasicBlock(LLVM_BB);
18899 F->insert(MBBIter, XMMSaveMBB);
18900 F->insert(MBBIter, EndMBB);
18902 // Transfer the remainder of MBB and its successor edges to EndMBB.
18903 EndMBB->splice(EndMBB->begin(), MBB,
18904 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
18905 EndMBB->transferSuccessorsAndUpdatePHIs(MBB);
18907 // The original block will now fall through to the XMM save block.
18908 MBB->addSuccessor(XMMSaveMBB);
18909 // The XMMSaveMBB will fall through to the end block.
18910 XMMSaveMBB->addSuccessor(EndMBB);
18912 // Now add the instructions.
18913 const TargetInstrInfo *TII = MBB->getParent()->getSubtarget().getInstrInfo();
18914 DebugLoc DL = MI->getDebugLoc();
18916 unsigned CountReg = MI->getOperand(0).getReg();
18917 int64_t RegSaveFrameIndex = MI->getOperand(1).getImm();
18918 int64_t VarArgsFPOffset = MI->getOperand(2).getImm();
18920 if (!Subtarget->isTargetWin64()) {
18921 // If %al is 0, branch around the XMM save block.
18922 BuildMI(MBB, DL, TII->get(X86::TEST8rr)).addReg(CountReg).addReg(CountReg);
18923 BuildMI(MBB, DL, TII->get(X86::JE_4)).addMBB(EndMBB);
18924 MBB->addSuccessor(EndMBB);
18927 // Make sure the last operand is EFLAGS, which gets clobbered by the branch
18928 // that was just emitted, but clearly shouldn't be "saved".
18929 assert((MI->getNumOperands() <= 3 ||
18930 !MI->getOperand(MI->getNumOperands() - 1).isReg() ||
18931 MI->getOperand(MI->getNumOperands() - 1).getReg() == X86::EFLAGS)
18932 && "Expected last argument to be EFLAGS");
18933 unsigned MOVOpc = Subtarget->hasFp256() ? X86::VMOVAPSmr : X86::MOVAPSmr;
18934 // In the XMM save block, save all the XMM argument registers.
18935 for (int i = 3, e = MI->getNumOperands() - 1; i != e; ++i) {
18936 int64_t Offset = (i - 3) * 16 + VarArgsFPOffset;
18937 MachineMemOperand *MMO =
18938 F->getMachineMemOperand(
18939 MachinePointerInfo::getFixedStack(RegSaveFrameIndex, Offset),
18940 MachineMemOperand::MOStore,
18941 /*Size=*/16, /*Align=*/16);
18942 BuildMI(XMMSaveMBB, DL, TII->get(MOVOpc))
18943 .addFrameIndex(RegSaveFrameIndex)
18944 .addImm(/*Scale=*/1)
18945 .addReg(/*IndexReg=*/0)
18946 .addImm(/*Disp=*/Offset)
18947 .addReg(/*Segment=*/0)
18948 .addReg(MI->getOperand(i).getReg())
18949 .addMemOperand(MMO);
18952 MI->eraseFromParent(); // The pseudo instruction is gone now.
18957 // The EFLAGS operand of SelectItr might be missing a kill marker
18958 // because there were multiple uses of EFLAGS, and ISel didn't know
18959 // which to mark. Figure out whether SelectItr should have had a
18960 // kill marker, and set it if it should. Returns the correct kill
18962 static bool checkAndUpdateEFLAGSKill(MachineBasicBlock::iterator SelectItr,
18963 MachineBasicBlock* BB,
18964 const TargetRegisterInfo* TRI) {
18965 // Scan forward through BB for a use/def of EFLAGS.
18966 MachineBasicBlock::iterator miI(std::next(SelectItr));
18967 for (MachineBasicBlock::iterator miE = BB->end(); miI != miE; ++miI) {
18968 const MachineInstr& mi = *miI;
18969 if (mi.readsRegister(X86::EFLAGS))
18971 if (mi.definesRegister(X86::EFLAGS))
18972 break; // Should have kill-flag - update below.
18975 // If we hit the end of the block, check whether EFLAGS is live into a
18977 if (miI == BB->end()) {
18978 for (MachineBasicBlock::succ_iterator sItr = BB->succ_begin(),
18979 sEnd = BB->succ_end();
18980 sItr != sEnd; ++sItr) {
18981 MachineBasicBlock* succ = *sItr;
18982 if (succ->isLiveIn(X86::EFLAGS))
18987 // We found a def, or hit the end of the basic block and EFLAGS wasn't live
18988 // out. SelectMI should have a kill flag on EFLAGS.
18989 SelectItr->addRegisterKilled(X86::EFLAGS, TRI);
18993 MachineBasicBlock *
18994 X86TargetLowering::EmitLoweredSelect(MachineInstr *MI,
18995 MachineBasicBlock *BB) const {
18996 const TargetInstrInfo *TII = BB->getParent()->getSubtarget().getInstrInfo();
18997 DebugLoc DL = MI->getDebugLoc();
18999 // To "insert" a SELECT_CC instruction, we actually have to insert the
19000 // diamond control-flow pattern. The incoming instruction knows the
19001 // destination vreg to set, the condition code register to branch on, the
19002 // true/false values to select between, and a branch opcode to use.
19003 const BasicBlock *LLVM_BB = BB->getBasicBlock();
19004 MachineFunction::iterator It = BB;
19010 // cmpTY ccX, r1, r2
19012 // fallthrough --> copy0MBB
19013 MachineBasicBlock *thisMBB = BB;
19014 MachineFunction *F = BB->getParent();
19015 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
19016 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
19017 F->insert(It, copy0MBB);
19018 F->insert(It, sinkMBB);
19020 // If the EFLAGS register isn't dead in the terminator, then claim that it's
19021 // live into the sink and copy blocks.
19022 const TargetRegisterInfo *TRI =
19023 BB->getParent()->getSubtarget().getRegisterInfo();
19024 if (!MI->killsRegister(X86::EFLAGS) &&
19025 !checkAndUpdateEFLAGSKill(MI, BB, TRI)) {
19026 copy0MBB->addLiveIn(X86::EFLAGS);
19027 sinkMBB->addLiveIn(X86::EFLAGS);
19030 // Transfer the remainder of BB and its successor edges to sinkMBB.
19031 sinkMBB->splice(sinkMBB->begin(), BB,
19032 std::next(MachineBasicBlock::iterator(MI)), BB->end());
19033 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
19035 // Add the true and fallthrough blocks as its successors.
19036 BB->addSuccessor(copy0MBB);
19037 BB->addSuccessor(sinkMBB);
19039 // Create the conditional branch instruction.
19041 X86::GetCondBranchFromCond((X86::CondCode)MI->getOperand(3).getImm());
19042 BuildMI(BB, DL, TII->get(Opc)).addMBB(sinkMBB);
19045 // %FalseValue = ...
19046 // # fallthrough to sinkMBB
19047 copy0MBB->addSuccessor(sinkMBB);
19050 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
19052 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
19053 TII->get(X86::PHI), MI->getOperand(0).getReg())
19054 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB)
19055 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
19057 MI->eraseFromParent(); // The pseudo instruction is gone now.
19061 MachineBasicBlock *
19062 X86TargetLowering::EmitLoweredSegAlloca(MachineInstr *MI,
19063 MachineBasicBlock *BB) const {
19064 MachineFunction *MF = BB->getParent();
19065 const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo();
19066 DebugLoc DL = MI->getDebugLoc();
19067 const BasicBlock *LLVM_BB = BB->getBasicBlock();
19069 assert(MF->shouldSplitStack());
19071 const bool Is64Bit = Subtarget->is64Bit();
19072 const bool IsLP64 = Subtarget->isTarget64BitLP64();
19074 const unsigned TlsReg = Is64Bit ? X86::FS : X86::GS;
19075 const unsigned TlsOffset = IsLP64 ? 0x70 : Is64Bit ? 0x40 : 0x30;
19078 // ... [Till the alloca]
19079 // If stacklet is not large enough, jump to mallocMBB
19082 // Allocate by subtracting from RSP
19083 // Jump to continueMBB
19086 // Allocate by call to runtime
19090 // [rest of original BB]
19093 MachineBasicBlock *mallocMBB = MF->CreateMachineBasicBlock(LLVM_BB);
19094 MachineBasicBlock *bumpMBB = MF->CreateMachineBasicBlock(LLVM_BB);
19095 MachineBasicBlock *continueMBB = MF->CreateMachineBasicBlock(LLVM_BB);
19097 MachineRegisterInfo &MRI = MF->getRegInfo();
19098 const TargetRegisterClass *AddrRegClass =
19099 getRegClassFor(getPointerTy());
19101 unsigned mallocPtrVReg = MRI.createVirtualRegister(AddrRegClass),
19102 bumpSPPtrVReg = MRI.createVirtualRegister(AddrRegClass),
19103 tmpSPVReg = MRI.createVirtualRegister(AddrRegClass),
19104 SPLimitVReg = MRI.createVirtualRegister(AddrRegClass),
19105 sizeVReg = MI->getOperand(1).getReg(),
19106 physSPReg = IsLP64 || Subtarget->isTargetNaCl64() ? X86::RSP : X86::ESP;
19108 MachineFunction::iterator MBBIter = BB;
19111 MF->insert(MBBIter, bumpMBB);
19112 MF->insert(MBBIter, mallocMBB);
19113 MF->insert(MBBIter, continueMBB);
19115 continueMBB->splice(continueMBB->begin(), BB,
19116 std::next(MachineBasicBlock::iterator(MI)), BB->end());
19117 continueMBB->transferSuccessorsAndUpdatePHIs(BB);
19119 // Add code to the main basic block to check if the stack limit has been hit,
19120 // and if so, jump to mallocMBB otherwise to bumpMBB.
19121 BuildMI(BB, DL, TII->get(TargetOpcode::COPY), tmpSPVReg).addReg(physSPReg);
19122 BuildMI(BB, DL, TII->get(IsLP64 ? X86::SUB64rr:X86::SUB32rr), SPLimitVReg)
19123 .addReg(tmpSPVReg).addReg(sizeVReg);
19124 BuildMI(BB, DL, TII->get(IsLP64 ? X86::CMP64mr:X86::CMP32mr))
19125 .addReg(0).addImm(1).addReg(0).addImm(TlsOffset).addReg(TlsReg)
19126 .addReg(SPLimitVReg);
19127 BuildMI(BB, DL, TII->get(X86::JG_4)).addMBB(mallocMBB);
19129 // bumpMBB simply decreases the stack pointer, since we know the current
19130 // stacklet has enough space.
19131 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), physSPReg)
19132 .addReg(SPLimitVReg);
19133 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), bumpSPPtrVReg)
19134 .addReg(SPLimitVReg);
19135 BuildMI(bumpMBB, DL, TII->get(X86::JMP_4)).addMBB(continueMBB);
19137 // Calls into a routine in libgcc to allocate more space from the heap.
19138 const uint32_t *RegMask = MF->getTarget()
19139 .getSubtargetImpl()
19140 ->getRegisterInfo()
19141 ->getCallPreservedMask(CallingConv::C);
19143 BuildMI(mallocMBB, DL, TII->get(X86::MOV64rr), X86::RDI)
19145 BuildMI(mallocMBB, DL, TII->get(X86::CALL64pcrel32))
19146 .addExternalSymbol("__morestack_allocate_stack_space")
19147 .addRegMask(RegMask)
19148 .addReg(X86::RDI, RegState::Implicit)
19149 .addReg(X86::RAX, RegState::ImplicitDefine);
19150 } else if (Is64Bit) {
19151 BuildMI(mallocMBB, DL, TII->get(X86::MOV32rr), X86::EDI)
19153 BuildMI(mallocMBB, DL, TII->get(X86::CALL64pcrel32))
19154 .addExternalSymbol("__morestack_allocate_stack_space")
19155 .addRegMask(RegMask)
19156 .addReg(X86::EDI, RegState::Implicit)
19157 .addReg(X86::EAX, RegState::ImplicitDefine);
19159 BuildMI(mallocMBB, DL, TII->get(X86::SUB32ri), physSPReg).addReg(physSPReg)
19161 BuildMI(mallocMBB, DL, TII->get(X86::PUSH32r)).addReg(sizeVReg);
19162 BuildMI(mallocMBB, DL, TII->get(X86::CALLpcrel32))
19163 .addExternalSymbol("__morestack_allocate_stack_space")
19164 .addRegMask(RegMask)
19165 .addReg(X86::EAX, RegState::ImplicitDefine);
19169 BuildMI(mallocMBB, DL, TII->get(X86::ADD32ri), physSPReg).addReg(physSPReg)
19172 BuildMI(mallocMBB, DL, TII->get(TargetOpcode::COPY), mallocPtrVReg)
19173 .addReg(IsLP64 ? X86::RAX : X86::EAX);
19174 BuildMI(mallocMBB, DL, TII->get(X86::JMP_4)).addMBB(continueMBB);
19176 // Set up the CFG correctly.
19177 BB->addSuccessor(bumpMBB);
19178 BB->addSuccessor(mallocMBB);
19179 mallocMBB->addSuccessor(continueMBB);
19180 bumpMBB->addSuccessor(continueMBB);
19182 // Take care of the PHI nodes.
19183 BuildMI(*continueMBB, continueMBB->begin(), DL, TII->get(X86::PHI),
19184 MI->getOperand(0).getReg())
19185 .addReg(mallocPtrVReg).addMBB(mallocMBB)
19186 .addReg(bumpSPPtrVReg).addMBB(bumpMBB);
19188 // Delete the original pseudo instruction.
19189 MI->eraseFromParent();
19192 return continueMBB;
19195 MachineBasicBlock *
19196 X86TargetLowering::EmitLoweredWinAlloca(MachineInstr *MI,
19197 MachineBasicBlock *BB) const {
19198 const TargetInstrInfo *TII = BB->getParent()->getSubtarget().getInstrInfo();
19199 DebugLoc DL = MI->getDebugLoc();
19201 assert(!Subtarget->isTargetMacho());
19203 // The lowering is pretty easy: we're just emitting the call to _alloca. The
19204 // non-trivial part is impdef of ESP.
19206 if (Subtarget->isTargetWin64()) {
19207 if (Subtarget->isTargetCygMing()) {
19208 // ___chkstk(Mingw64):
19209 // Clobbers R10, R11, RAX and EFLAGS.
19211 BuildMI(*BB, MI, DL, TII->get(X86::W64ALLOCA))
19212 .addExternalSymbol("___chkstk")
19213 .addReg(X86::RAX, RegState::Implicit)
19214 .addReg(X86::RSP, RegState::Implicit)
19215 .addReg(X86::RAX, RegState::Define | RegState::Implicit)
19216 .addReg(X86::RSP, RegState::Define | RegState::Implicit)
19217 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
19219 // __chkstk(MSVCRT): does not update stack pointer.
19220 // Clobbers R10, R11 and EFLAGS.
19221 BuildMI(*BB, MI, DL, TII->get(X86::W64ALLOCA))
19222 .addExternalSymbol("__chkstk")
19223 .addReg(X86::RAX, RegState::Implicit)
19224 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
19225 // RAX has the offset to be subtracted from RSP.
19226 BuildMI(*BB, MI, DL, TII->get(X86::SUB64rr), X86::RSP)
19231 const char *StackProbeSymbol =
19232 Subtarget->isTargetKnownWindowsMSVC() ? "_chkstk" : "_alloca";
19234 BuildMI(*BB, MI, DL, TII->get(X86::CALLpcrel32))
19235 .addExternalSymbol(StackProbeSymbol)
19236 .addReg(X86::EAX, RegState::Implicit)
19237 .addReg(X86::ESP, RegState::Implicit)
19238 .addReg(X86::EAX, RegState::Define | RegState::Implicit)
19239 .addReg(X86::ESP, RegState::Define | RegState::Implicit)
19240 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
19243 MI->eraseFromParent(); // The pseudo instruction is gone now.
19247 MachineBasicBlock *
19248 X86TargetLowering::EmitLoweredTLSCall(MachineInstr *MI,
19249 MachineBasicBlock *BB) const {
19250 // This is pretty easy. We're taking the value that we received from
19251 // our load from the relocation, sticking it in either RDI (x86-64)
19252 // or EAX and doing an indirect call. The return value will then
19253 // be in the normal return register.
19254 MachineFunction *F = BB->getParent();
19255 const X86InstrInfo *TII =
19256 static_cast<const X86InstrInfo *>(F->getSubtarget().getInstrInfo());
19257 DebugLoc DL = MI->getDebugLoc();
19259 assert(Subtarget->isTargetDarwin() && "Darwin only instr emitted?");
19260 assert(MI->getOperand(3).isGlobal() && "This should be a global");
19262 // Get a register mask for the lowered call.
19263 // FIXME: The 32-bit calls have non-standard calling conventions. Use a
19264 // proper register mask.
19265 const uint32_t *RegMask = F->getTarget()
19266 .getSubtargetImpl()
19267 ->getRegisterInfo()
19268 ->getCallPreservedMask(CallingConv::C);
19269 if (Subtarget->is64Bit()) {
19270 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
19271 TII->get(X86::MOV64rm), X86::RDI)
19273 .addImm(0).addReg(0)
19274 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
19275 MI->getOperand(3).getTargetFlags())
19277 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL64m));
19278 addDirectMem(MIB, X86::RDI);
19279 MIB.addReg(X86::RAX, RegState::ImplicitDefine).addRegMask(RegMask);
19280 } else if (F->getTarget().getRelocationModel() != Reloc::PIC_) {
19281 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
19282 TII->get(X86::MOV32rm), X86::EAX)
19284 .addImm(0).addReg(0)
19285 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
19286 MI->getOperand(3).getTargetFlags())
19288 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
19289 addDirectMem(MIB, X86::EAX);
19290 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask);
19292 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
19293 TII->get(X86::MOV32rm), X86::EAX)
19294 .addReg(TII->getGlobalBaseReg(F))
19295 .addImm(0).addReg(0)
19296 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
19297 MI->getOperand(3).getTargetFlags())
19299 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
19300 addDirectMem(MIB, X86::EAX);
19301 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask);
19304 MI->eraseFromParent(); // The pseudo instruction is gone now.
19308 MachineBasicBlock *
19309 X86TargetLowering::emitEHSjLjSetJmp(MachineInstr *MI,
19310 MachineBasicBlock *MBB) const {
19311 DebugLoc DL = MI->getDebugLoc();
19312 MachineFunction *MF = MBB->getParent();
19313 const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo();
19314 MachineRegisterInfo &MRI = MF->getRegInfo();
19316 const BasicBlock *BB = MBB->getBasicBlock();
19317 MachineFunction::iterator I = MBB;
19320 // Memory Reference
19321 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
19322 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
19325 unsigned MemOpndSlot = 0;
19327 unsigned CurOp = 0;
19329 DstReg = MI->getOperand(CurOp++).getReg();
19330 const TargetRegisterClass *RC = MRI.getRegClass(DstReg);
19331 assert(RC->hasType(MVT::i32) && "Invalid destination!");
19332 unsigned mainDstReg = MRI.createVirtualRegister(RC);
19333 unsigned restoreDstReg = MRI.createVirtualRegister(RC);
19335 MemOpndSlot = CurOp;
19337 MVT PVT = getPointerTy();
19338 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
19339 "Invalid Pointer Size!");
19341 // For v = setjmp(buf), we generate
19344 // buf[LabelOffset] = restoreMBB
19345 // SjLjSetup restoreMBB
19351 // v = phi(main, restore)
19356 MachineBasicBlock *thisMBB = MBB;
19357 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
19358 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
19359 MachineBasicBlock *restoreMBB = MF->CreateMachineBasicBlock(BB);
19360 MF->insert(I, mainMBB);
19361 MF->insert(I, sinkMBB);
19362 MF->push_back(restoreMBB);
19364 MachineInstrBuilder MIB;
19366 // Transfer the remainder of BB and its successor edges to sinkMBB.
19367 sinkMBB->splice(sinkMBB->begin(), MBB,
19368 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
19369 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
19372 unsigned PtrStoreOpc = 0;
19373 unsigned LabelReg = 0;
19374 const int64_t LabelOffset = 1 * PVT.getStoreSize();
19375 Reloc::Model RM = MF->getTarget().getRelocationModel();
19376 bool UseImmLabel = (MF->getTarget().getCodeModel() == CodeModel::Small) &&
19377 (RM == Reloc::Static || RM == Reloc::DynamicNoPIC);
19379 // Prepare IP either in reg or imm.
19380 if (!UseImmLabel) {
19381 PtrStoreOpc = (PVT == MVT::i64) ? X86::MOV64mr : X86::MOV32mr;
19382 const TargetRegisterClass *PtrRC = getRegClassFor(PVT);
19383 LabelReg = MRI.createVirtualRegister(PtrRC);
19384 if (Subtarget->is64Bit()) {
19385 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::LEA64r), LabelReg)
19389 .addMBB(restoreMBB)
19392 const X86InstrInfo *XII = static_cast<const X86InstrInfo*>(TII);
19393 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::LEA32r), LabelReg)
19394 .addReg(XII->getGlobalBaseReg(MF))
19397 .addMBB(restoreMBB, Subtarget->ClassifyBlockAddressReference())
19401 PtrStoreOpc = (PVT == MVT::i64) ? X86::MOV64mi32 : X86::MOV32mi;
19403 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PtrStoreOpc));
19404 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
19405 if (i == X86::AddrDisp)
19406 MIB.addDisp(MI->getOperand(MemOpndSlot + i), LabelOffset);
19408 MIB.addOperand(MI->getOperand(MemOpndSlot + i));
19411 MIB.addReg(LabelReg);
19413 MIB.addMBB(restoreMBB);
19414 MIB.setMemRefs(MMOBegin, MMOEnd);
19416 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::EH_SjLj_Setup))
19417 .addMBB(restoreMBB);
19419 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
19420 MF->getSubtarget().getRegisterInfo());
19421 MIB.addRegMask(RegInfo->getNoPreservedMask());
19422 thisMBB->addSuccessor(mainMBB);
19423 thisMBB->addSuccessor(restoreMBB);
19427 BuildMI(mainMBB, DL, TII->get(X86::MOV32r0), mainDstReg);
19428 mainMBB->addSuccessor(sinkMBB);
19431 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
19432 TII->get(X86::PHI), DstReg)
19433 .addReg(mainDstReg).addMBB(mainMBB)
19434 .addReg(restoreDstReg).addMBB(restoreMBB);
19437 BuildMI(restoreMBB, DL, TII->get(X86::MOV32ri), restoreDstReg).addImm(1);
19438 BuildMI(restoreMBB, DL, TII->get(X86::JMP_4)).addMBB(sinkMBB);
19439 restoreMBB->addSuccessor(sinkMBB);
19441 MI->eraseFromParent();
19445 MachineBasicBlock *
19446 X86TargetLowering::emitEHSjLjLongJmp(MachineInstr *MI,
19447 MachineBasicBlock *MBB) const {
19448 DebugLoc DL = MI->getDebugLoc();
19449 MachineFunction *MF = MBB->getParent();
19450 const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo();
19451 MachineRegisterInfo &MRI = MF->getRegInfo();
19453 // Memory Reference
19454 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
19455 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
19457 MVT PVT = getPointerTy();
19458 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
19459 "Invalid Pointer Size!");
19461 const TargetRegisterClass *RC =
19462 (PVT == MVT::i64) ? &X86::GR64RegClass : &X86::GR32RegClass;
19463 unsigned Tmp = MRI.createVirtualRegister(RC);
19464 // Since FP is only updated here but NOT referenced, it's treated as GPR.
19465 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
19466 MF->getSubtarget().getRegisterInfo());
19467 unsigned FP = (PVT == MVT::i64) ? X86::RBP : X86::EBP;
19468 unsigned SP = RegInfo->getStackRegister();
19470 MachineInstrBuilder MIB;
19472 const int64_t LabelOffset = 1 * PVT.getStoreSize();
19473 const int64_t SPOffset = 2 * PVT.getStoreSize();
19475 unsigned PtrLoadOpc = (PVT == MVT::i64) ? X86::MOV64rm : X86::MOV32rm;
19476 unsigned IJmpOpc = (PVT == MVT::i64) ? X86::JMP64r : X86::JMP32r;
19479 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), FP);
19480 for (unsigned i = 0; i < X86::AddrNumOperands; ++i)
19481 MIB.addOperand(MI->getOperand(i));
19482 MIB.setMemRefs(MMOBegin, MMOEnd);
19484 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), Tmp);
19485 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
19486 if (i == X86::AddrDisp)
19487 MIB.addDisp(MI->getOperand(i), LabelOffset);
19489 MIB.addOperand(MI->getOperand(i));
19491 MIB.setMemRefs(MMOBegin, MMOEnd);
19493 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), SP);
19494 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
19495 if (i == X86::AddrDisp)
19496 MIB.addDisp(MI->getOperand(i), SPOffset);
19498 MIB.addOperand(MI->getOperand(i));
19500 MIB.setMemRefs(MMOBegin, MMOEnd);
19502 BuildMI(*MBB, MI, DL, TII->get(IJmpOpc)).addReg(Tmp);
19504 MI->eraseFromParent();
19508 // Replace 213-type (isel default) FMA3 instructions with 231-type for
19509 // accumulator loops. Writing back to the accumulator allows the coalescer
19510 // to remove extra copies in the loop.
19511 MachineBasicBlock *
19512 X86TargetLowering::emitFMA3Instr(MachineInstr *MI,
19513 MachineBasicBlock *MBB) const {
19514 MachineOperand &AddendOp = MI->getOperand(3);
19516 // Bail out early if the addend isn't a register - we can't switch these.
19517 if (!AddendOp.isReg())
19520 MachineFunction &MF = *MBB->getParent();
19521 MachineRegisterInfo &MRI = MF.getRegInfo();
19523 // Check whether the addend is defined by a PHI:
19524 assert(MRI.hasOneDef(AddendOp.getReg()) && "Multiple defs in SSA?");
19525 MachineInstr &AddendDef = *MRI.def_instr_begin(AddendOp.getReg());
19526 if (!AddendDef.isPHI())
19529 // Look for the following pattern:
19531 // %addend = phi [%entry, 0], [%loop, %result]
19533 // %result<tied1> = FMA213 %m2<tied0>, %m1, %addend
19537 // %addend = phi [%entry, 0], [%loop, %result]
19539 // %result<tied1> = FMA231 %addend<tied0>, %m1, %m2
19541 for (unsigned i = 1, e = AddendDef.getNumOperands(); i < e; i += 2) {
19542 assert(AddendDef.getOperand(i).isReg());
19543 MachineOperand PHISrcOp = AddendDef.getOperand(i);
19544 MachineInstr &PHISrcInst = *MRI.def_instr_begin(PHISrcOp.getReg());
19545 if (&PHISrcInst == MI) {
19546 // Found a matching instruction.
19547 unsigned NewFMAOpc = 0;
19548 switch (MI->getOpcode()) {
19549 case X86::VFMADDPDr213r: NewFMAOpc = X86::VFMADDPDr231r; break;
19550 case X86::VFMADDPSr213r: NewFMAOpc = X86::VFMADDPSr231r; break;
19551 case X86::VFMADDSDr213r: NewFMAOpc = X86::VFMADDSDr231r; break;
19552 case X86::VFMADDSSr213r: NewFMAOpc = X86::VFMADDSSr231r; break;
19553 case X86::VFMSUBPDr213r: NewFMAOpc = X86::VFMSUBPDr231r; break;
19554 case X86::VFMSUBPSr213r: NewFMAOpc = X86::VFMSUBPSr231r; break;
19555 case X86::VFMSUBSDr213r: NewFMAOpc = X86::VFMSUBSDr231r; break;
19556 case X86::VFMSUBSSr213r: NewFMAOpc = X86::VFMSUBSSr231r; break;
19557 case X86::VFNMADDPDr213r: NewFMAOpc = X86::VFNMADDPDr231r; break;
19558 case X86::VFNMADDPSr213r: NewFMAOpc = X86::VFNMADDPSr231r; break;
19559 case X86::VFNMADDSDr213r: NewFMAOpc = X86::VFNMADDSDr231r; break;
19560 case X86::VFNMADDSSr213r: NewFMAOpc = X86::VFNMADDSSr231r; break;
19561 case X86::VFNMSUBPDr213r: NewFMAOpc = X86::VFNMSUBPDr231r; break;
19562 case X86::VFNMSUBPSr213r: NewFMAOpc = X86::VFNMSUBPSr231r; break;
19563 case X86::VFNMSUBSDr213r: NewFMAOpc = X86::VFNMSUBSDr231r; break;
19564 case X86::VFNMSUBSSr213r: NewFMAOpc = X86::VFNMSUBSSr231r; break;
19565 case X86::VFMADDPDr213rY: NewFMAOpc = X86::VFMADDPDr231rY; break;
19566 case X86::VFMADDPSr213rY: NewFMAOpc = X86::VFMADDPSr231rY; break;
19567 case X86::VFMSUBPDr213rY: NewFMAOpc = X86::VFMSUBPDr231rY; break;
19568 case X86::VFMSUBPSr213rY: NewFMAOpc = X86::VFMSUBPSr231rY; break;
19569 case X86::VFNMADDPDr213rY: NewFMAOpc = X86::VFNMADDPDr231rY; break;
19570 case X86::VFNMADDPSr213rY: NewFMAOpc = X86::VFNMADDPSr231rY; break;
19571 case X86::VFNMSUBPDr213rY: NewFMAOpc = X86::VFNMSUBPDr231rY; break;
19572 case X86::VFNMSUBPSr213rY: NewFMAOpc = X86::VFNMSUBPSr231rY; break;
19573 default: llvm_unreachable("Unrecognized FMA variant.");
19576 const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo();
19577 MachineInstrBuilder MIB =
19578 BuildMI(MF, MI->getDebugLoc(), TII.get(NewFMAOpc))
19579 .addOperand(MI->getOperand(0))
19580 .addOperand(MI->getOperand(3))
19581 .addOperand(MI->getOperand(2))
19582 .addOperand(MI->getOperand(1));
19583 MBB->insert(MachineBasicBlock::iterator(MI), MIB);
19584 MI->eraseFromParent();
19591 MachineBasicBlock *
19592 X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
19593 MachineBasicBlock *BB) const {
19594 switch (MI->getOpcode()) {
19595 default: llvm_unreachable("Unexpected instr type to insert");
19596 case X86::TAILJMPd64:
19597 case X86::TAILJMPr64:
19598 case X86::TAILJMPm64:
19599 llvm_unreachable("TAILJMP64 would not be touched here.");
19600 case X86::TCRETURNdi64:
19601 case X86::TCRETURNri64:
19602 case X86::TCRETURNmi64:
19604 case X86::WIN_ALLOCA:
19605 return EmitLoweredWinAlloca(MI, BB);
19606 case X86::SEG_ALLOCA_32:
19607 case X86::SEG_ALLOCA_64:
19608 return EmitLoweredSegAlloca(MI, BB);
19609 case X86::TLSCall_32:
19610 case X86::TLSCall_64:
19611 return EmitLoweredTLSCall(MI, BB);
19612 case X86::CMOV_GR8:
19613 case X86::CMOV_FR32:
19614 case X86::CMOV_FR64:
19615 case X86::CMOV_V4F32:
19616 case X86::CMOV_V2F64:
19617 case X86::CMOV_V2I64:
19618 case X86::CMOV_V8F32:
19619 case X86::CMOV_V4F64:
19620 case X86::CMOV_V4I64:
19621 case X86::CMOV_V16F32:
19622 case X86::CMOV_V8F64:
19623 case X86::CMOV_V8I64:
19624 case X86::CMOV_GR16:
19625 case X86::CMOV_GR32:
19626 case X86::CMOV_RFP32:
19627 case X86::CMOV_RFP64:
19628 case X86::CMOV_RFP80:
19629 return EmitLoweredSelect(MI, BB);
19631 case X86::FP32_TO_INT16_IN_MEM:
19632 case X86::FP32_TO_INT32_IN_MEM:
19633 case X86::FP32_TO_INT64_IN_MEM:
19634 case X86::FP64_TO_INT16_IN_MEM:
19635 case X86::FP64_TO_INT32_IN_MEM:
19636 case X86::FP64_TO_INT64_IN_MEM:
19637 case X86::FP80_TO_INT16_IN_MEM:
19638 case X86::FP80_TO_INT32_IN_MEM:
19639 case X86::FP80_TO_INT64_IN_MEM: {
19640 MachineFunction *F = BB->getParent();
19641 const TargetInstrInfo *TII = F->getSubtarget().getInstrInfo();
19642 DebugLoc DL = MI->getDebugLoc();
19644 // Change the floating point control register to use "round towards zero"
19645 // mode when truncating to an integer value.
19646 int CWFrameIdx = F->getFrameInfo()->CreateStackObject(2, 2, false);
19647 addFrameReference(BuildMI(*BB, MI, DL,
19648 TII->get(X86::FNSTCW16m)), CWFrameIdx);
19650 // Load the old value of the high byte of the control word...
19652 F->getRegInfo().createVirtualRegister(&X86::GR16RegClass);
19653 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16rm), OldCW),
19656 // Set the high part to be round to zero...
19657 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mi)), CWFrameIdx)
19660 // Reload the modified control word now...
19661 addFrameReference(BuildMI(*BB, MI, DL,
19662 TII->get(X86::FLDCW16m)), CWFrameIdx);
19664 // Restore the memory image of control word to original value
19665 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mr)), CWFrameIdx)
19668 // Get the X86 opcode to use.
19670 switch (MI->getOpcode()) {
19671 default: llvm_unreachable("illegal opcode!");
19672 case X86::FP32_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m32; break;
19673 case X86::FP32_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m32; break;
19674 case X86::FP32_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m32; break;
19675 case X86::FP64_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m64; break;
19676 case X86::FP64_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m64; break;
19677 case X86::FP64_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m64; break;
19678 case X86::FP80_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m80; break;
19679 case X86::FP80_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m80; break;
19680 case X86::FP80_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m80; break;
19684 MachineOperand &Op = MI->getOperand(0);
19686 AM.BaseType = X86AddressMode::RegBase;
19687 AM.Base.Reg = Op.getReg();
19689 AM.BaseType = X86AddressMode::FrameIndexBase;
19690 AM.Base.FrameIndex = Op.getIndex();
19692 Op = MI->getOperand(1);
19694 AM.Scale = Op.getImm();
19695 Op = MI->getOperand(2);
19697 AM.IndexReg = Op.getImm();
19698 Op = MI->getOperand(3);
19699 if (Op.isGlobal()) {
19700 AM.GV = Op.getGlobal();
19702 AM.Disp = Op.getImm();
19704 addFullAddress(BuildMI(*BB, MI, DL, TII->get(Opc)), AM)
19705 .addReg(MI->getOperand(X86::AddrNumOperands).getReg());
19707 // Reload the original control word now.
19708 addFrameReference(BuildMI(*BB, MI, DL,
19709 TII->get(X86::FLDCW16m)), CWFrameIdx);
19711 MI->eraseFromParent(); // The pseudo instruction is gone now.
19714 // String/text processing lowering.
19715 case X86::PCMPISTRM128REG:
19716 case X86::VPCMPISTRM128REG:
19717 case X86::PCMPISTRM128MEM:
19718 case X86::VPCMPISTRM128MEM:
19719 case X86::PCMPESTRM128REG:
19720 case X86::VPCMPESTRM128REG:
19721 case X86::PCMPESTRM128MEM:
19722 case X86::VPCMPESTRM128MEM:
19723 assert(Subtarget->hasSSE42() &&
19724 "Target must have SSE4.2 or AVX features enabled");
19725 return EmitPCMPSTRM(MI, BB, BB->getParent()->getSubtarget().getInstrInfo());
19727 // String/text processing lowering.
19728 case X86::PCMPISTRIREG:
19729 case X86::VPCMPISTRIREG:
19730 case X86::PCMPISTRIMEM:
19731 case X86::VPCMPISTRIMEM:
19732 case X86::PCMPESTRIREG:
19733 case X86::VPCMPESTRIREG:
19734 case X86::PCMPESTRIMEM:
19735 case X86::VPCMPESTRIMEM:
19736 assert(Subtarget->hasSSE42() &&
19737 "Target must have SSE4.2 or AVX features enabled");
19738 return EmitPCMPSTRI(MI, BB, BB->getParent()->getSubtarget().getInstrInfo());
19740 // Thread synchronization.
19742 return EmitMonitor(MI, BB, BB->getParent()->getSubtarget().getInstrInfo(),
19747 return EmitXBegin(MI, BB, BB->getParent()->getSubtarget().getInstrInfo());
19749 case X86::VASTART_SAVE_XMM_REGS:
19750 return EmitVAStartSaveXMMRegsWithCustomInserter(MI, BB);
19752 case X86::VAARG_64:
19753 return EmitVAARG64WithCustomInserter(MI, BB);
19755 case X86::EH_SjLj_SetJmp32:
19756 case X86::EH_SjLj_SetJmp64:
19757 return emitEHSjLjSetJmp(MI, BB);
19759 case X86::EH_SjLj_LongJmp32:
19760 case X86::EH_SjLj_LongJmp64:
19761 return emitEHSjLjLongJmp(MI, BB);
19763 case TargetOpcode::STACKMAP:
19764 case TargetOpcode::PATCHPOINT:
19765 return emitPatchPoint(MI, BB);
19767 case X86::VFMADDPDr213r:
19768 case X86::VFMADDPSr213r:
19769 case X86::VFMADDSDr213r:
19770 case X86::VFMADDSSr213r:
19771 case X86::VFMSUBPDr213r:
19772 case X86::VFMSUBPSr213r:
19773 case X86::VFMSUBSDr213r:
19774 case X86::VFMSUBSSr213r:
19775 case X86::VFNMADDPDr213r:
19776 case X86::VFNMADDPSr213r:
19777 case X86::VFNMADDSDr213r:
19778 case X86::VFNMADDSSr213r:
19779 case X86::VFNMSUBPDr213r:
19780 case X86::VFNMSUBPSr213r:
19781 case X86::VFNMSUBSDr213r:
19782 case X86::VFNMSUBSSr213r:
19783 case X86::VFMADDPDr213rY:
19784 case X86::VFMADDPSr213rY:
19785 case X86::VFMSUBPDr213rY:
19786 case X86::VFMSUBPSr213rY:
19787 case X86::VFNMADDPDr213rY:
19788 case X86::VFNMADDPSr213rY:
19789 case X86::VFNMSUBPDr213rY:
19790 case X86::VFNMSUBPSr213rY:
19791 return emitFMA3Instr(MI, BB);
19795 //===----------------------------------------------------------------------===//
19796 // X86 Optimization Hooks
19797 //===----------------------------------------------------------------------===//
19799 void X86TargetLowering::computeKnownBitsForTargetNode(const SDValue Op,
19802 const SelectionDAG &DAG,
19803 unsigned Depth) const {
19804 unsigned BitWidth = KnownZero.getBitWidth();
19805 unsigned Opc = Op.getOpcode();
19806 assert((Opc >= ISD::BUILTIN_OP_END ||
19807 Opc == ISD::INTRINSIC_WO_CHAIN ||
19808 Opc == ISD::INTRINSIC_W_CHAIN ||
19809 Opc == ISD::INTRINSIC_VOID) &&
19810 "Should use MaskedValueIsZero if you don't know whether Op"
19811 " is a target node!");
19813 KnownZero = KnownOne = APInt(BitWidth, 0); // Don't know anything.
19827 // These nodes' second result is a boolean.
19828 if (Op.getResNo() == 0)
19831 case X86ISD::SETCC:
19832 KnownZero |= APInt::getHighBitsSet(BitWidth, BitWidth - 1);
19834 case ISD::INTRINSIC_WO_CHAIN: {
19835 unsigned IntId = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
19836 unsigned NumLoBits = 0;
19839 case Intrinsic::x86_sse_movmsk_ps:
19840 case Intrinsic::x86_avx_movmsk_ps_256:
19841 case Intrinsic::x86_sse2_movmsk_pd:
19842 case Intrinsic::x86_avx_movmsk_pd_256:
19843 case Intrinsic::x86_mmx_pmovmskb:
19844 case Intrinsic::x86_sse2_pmovmskb_128:
19845 case Intrinsic::x86_avx2_pmovmskb: {
19846 // High bits of movmskp{s|d}, pmovmskb are known zero.
19848 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
19849 case Intrinsic::x86_sse_movmsk_ps: NumLoBits = 4; break;
19850 case Intrinsic::x86_avx_movmsk_ps_256: NumLoBits = 8; break;
19851 case Intrinsic::x86_sse2_movmsk_pd: NumLoBits = 2; break;
19852 case Intrinsic::x86_avx_movmsk_pd_256: NumLoBits = 4; break;
19853 case Intrinsic::x86_mmx_pmovmskb: NumLoBits = 8; break;
19854 case Intrinsic::x86_sse2_pmovmskb_128: NumLoBits = 16; break;
19855 case Intrinsic::x86_avx2_pmovmskb: NumLoBits = 32; break;
19857 KnownZero = APInt::getHighBitsSet(BitWidth, BitWidth - NumLoBits);
19866 unsigned X86TargetLowering::ComputeNumSignBitsForTargetNode(
19868 const SelectionDAG &,
19869 unsigned Depth) const {
19870 // SETCC_CARRY sets the dest to ~0 for true or 0 for false.
19871 if (Op.getOpcode() == X86ISD::SETCC_CARRY)
19872 return Op.getValueType().getScalarType().getSizeInBits();
19878 /// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the
19879 /// node is a GlobalAddress + offset.
19880 bool X86TargetLowering::isGAPlusOffset(SDNode *N,
19881 const GlobalValue* &GA,
19882 int64_t &Offset) const {
19883 if (N->getOpcode() == X86ISD::Wrapper) {
19884 if (isa<GlobalAddressSDNode>(N->getOperand(0))) {
19885 GA = cast<GlobalAddressSDNode>(N->getOperand(0))->getGlobal();
19886 Offset = cast<GlobalAddressSDNode>(N->getOperand(0))->getOffset();
19890 return TargetLowering::isGAPlusOffset(N, GA, Offset);
19893 /// isShuffleHigh128VectorInsertLow - Checks whether the shuffle node is the
19894 /// same as extracting the high 128-bit part of 256-bit vector and then
19895 /// inserting the result into the low part of a new 256-bit vector
19896 static bool isShuffleHigh128VectorInsertLow(ShuffleVectorSDNode *SVOp) {
19897 EVT VT = SVOp->getValueType(0);
19898 unsigned NumElems = VT.getVectorNumElements();
19900 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
19901 for (unsigned i = 0, j = NumElems/2; i != NumElems/2; ++i, ++j)
19902 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) ||
19903 SVOp->getMaskElt(j) >= 0)
19909 /// isShuffleLow128VectorInsertHigh - Checks whether the shuffle node is the
19910 /// same as extracting the low 128-bit part of 256-bit vector and then
19911 /// inserting the result into the high part of a new 256-bit vector
19912 static bool isShuffleLow128VectorInsertHigh(ShuffleVectorSDNode *SVOp) {
19913 EVT VT = SVOp->getValueType(0);
19914 unsigned NumElems = VT.getVectorNumElements();
19916 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
19917 for (unsigned i = NumElems/2, j = 0; i != NumElems; ++i, ++j)
19918 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) ||
19919 SVOp->getMaskElt(j) >= 0)
19925 /// PerformShuffleCombine256 - Performs shuffle combines for 256-bit vectors.
19926 static SDValue PerformShuffleCombine256(SDNode *N, SelectionDAG &DAG,
19927 TargetLowering::DAGCombinerInfo &DCI,
19928 const X86Subtarget* Subtarget) {
19930 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
19931 SDValue V1 = SVOp->getOperand(0);
19932 SDValue V2 = SVOp->getOperand(1);
19933 EVT VT = SVOp->getValueType(0);
19934 unsigned NumElems = VT.getVectorNumElements();
19936 if (V1.getOpcode() == ISD::CONCAT_VECTORS &&
19937 V2.getOpcode() == ISD::CONCAT_VECTORS) {
19941 // V UNDEF BUILD_VECTOR UNDEF
19943 // CONCAT_VECTOR CONCAT_VECTOR
19946 // RESULT: V + zero extended
19948 if (V2.getOperand(0).getOpcode() != ISD::BUILD_VECTOR ||
19949 V2.getOperand(1).getOpcode() != ISD::UNDEF ||
19950 V1.getOperand(1).getOpcode() != ISD::UNDEF)
19953 if (!ISD::isBuildVectorAllZeros(V2.getOperand(0).getNode()))
19956 // To match the shuffle mask, the first half of the mask should
19957 // be exactly the first vector, and all the rest a splat with the
19958 // first element of the second one.
19959 for (unsigned i = 0; i != NumElems/2; ++i)
19960 if (!isUndefOrEqual(SVOp->getMaskElt(i), i) ||
19961 !isUndefOrEqual(SVOp->getMaskElt(i+NumElems/2), NumElems))
19964 // If V1 is coming from a vector load then just fold to a VZEXT_LOAD.
19965 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(V1.getOperand(0))) {
19966 if (Ld->hasNUsesOfValue(1, 0)) {
19967 SDVTList Tys = DAG.getVTList(MVT::v4i64, MVT::Other);
19968 SDValue Ops[] = { Ld->getChain(), Ld->getBasePtr() };
19970 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, dl, Tys, Ops,
19972 Ld->getPointerInfo(),
19973 Ld->getAlignment(),
19974 false/*isVolatile*/, true/*ReadMem*/,
19975 false/*WriteMem*/);
19977 // Make sure the newly-created LOAD is in the same position as Ld in
19978 // terms of dependency. We create a TokenFactor for Ld and ResNode,
19979 // and update uses of Ld's output chain to use the TokenFactor.
19980 if (Ld->hasAnyUseOfValue(1)) {
19981 SDValue NewChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
19982 SDValue(Ld, 1), SDValue(ResNode.getNode(), 1));
19983 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), NewChain);
19984 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(Ld, 1),
19985 SDValue(ResNode.getNode(), 1));
19988 return DAG.getNode(ISD::BITCAST, dl, VT, ResNode);
19992 // Emit a zeroed vector and insert the desired subvector on its
19994 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
19995 SDValue InsV = Insert128BitVector(Zeros, V1.getOperand(0), 0, DAG, dl);
19996 return DCI.CombineTo(N, InsV);
19999 //===--------------------------------------------------------------------===//
20000 // Combine some shuffles into subvector extracts and inserts:
20003 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
20004 if (isShuffleHigh128VectorInsertLow(SVOp)) {
20005 SDValue V = Extract128BitVector(V1, NumElems/2, DAG, dl);
20006 SDValue InsV = Insert128BitVector(DAG.getUNDEF(VT), V, 0, DAG, dl);
20007 return DCI.CombineTo(N, InsV);
20010 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
20011 if (isShuffleLow128VectorInsertHigh(SVOp)) {
20012 SDValue V = Extract128BitVector(V1, 0, DAG, dl);
20013 SDValue InsV = Insert128BitVector(DAG.getUNDEF(VT), V, NumElems/2, DAG, dl);
20014 return DCI.CombineTo(N, InsV);
20020 /// \brief Combine an arbitrary chain of shuffles into a single instruction if
20023 /// This is the leaf of the recursive combinine below. When we have found some
20024 /// chain of single-use x86 shuffle instructions and accumulated the combined
20025 /// shuffle mask represented by them, this will try to pattern match that mask
20026 /// into either a single instruction if there is a special purpose instruction
20027 /// for this operation, or into a PSHUFB instruction which is a fully general
20028 /// instruction but should only be used to replace chains over a certain depth.
20029 static bool combineX86ShuffleChain(SDValue Op, SDValue Root, ArrayRef<int> Mask,
20030 int Depth, bool HasPSHUFB, SelectionDAG &DAG,
20031 TargetLowering::DAGCombinerInfo &DCI,
20032 const X86Subtarget *Subtarget) {
20033 assert(!Mask.empty() && "Cannot combine an empty shuffle mask!");
20035 // Find the operand that enters the chain. Note that multiple uses are OK
20036 // here, we're not going to remove the operand we find.
20037 SDValue Input = Op.getOperand(0);
20038 while (Input.getOpcode() == ISD::BITCAST)
20039 Input = Input.getOperand(0);
20041 MVT VT = Input.getSimpleValueType();
20042 MVT RootVT = Root.getSimpleValueType();
20045 // Just remove no-op shuffle masks.
20046 if (Mask.size() == 1) {
20047 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Input),
20052 // Use the float domain if the operand type is a floating point type.
20053 bool FloatDomain = VT.isFloatingPoint();
20055 // For floating point shuffles, we don't have free copies in the shuffle
20056 // instructions or the ability to load as part of the instruction, so
20057 // canonicalize their shuffles to UNPCK or MOV variants.
20059 // Note that even with AVX we prefer the PSHUFD form of shuffle for integer
20060 // vectors because it can have a load folded into it that UNPCK cannot. This
20061 // doesn't preclude something switching to the shorter encoding post-RA.
20063 if (Mask.equals(0, 0) || Mask.equals(1, 1)) {
20064 bool Lo = Mask.equals(0, 0);
20067 // Check if we have SSE3 which will let us use MOVDDUP. That instruction
20068 // is no slower than UNPCKLPD but has the option to fold the input operand
20069 // into even an unaligned memory load.
20070 if (Lo && Subtarget->hasSSE3()) {
20071 Shuffle = X86ISD::MOVDDUP;
20072 ShuffleVT = MVT::v2f64;
20074 // We have MOVLHPS and MOVHLPS throughout SSE and they encode smaller
20075 // than the UNPCK variants.
20076 Shuffle = Lo ? X86ISD::MOVLHPS : X86ISD::MOVHLPS;
20077 ShuffleVT = MVT::v4f32;
20079 if (Depth == 1 && Root->getOpcode() == Shuffle)
20080 return false; // Nothing to do!
20081 Op = DAG.getNode(ISD::BITCAST, DL, ShuffleVT, Input);
20082 DCI.AddToWorklist(Op.getNode());
20083 if (Shuffle == X86ISD::MOVDDUP)
20084 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op);
20086 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op, Op);
20087 DCI.AddToWorklist(Op.getNode());
20088 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Op),
20092 if (Subtarget->hasSSE3() &&
20093 (Mask.equals(0, 0, 2, 2) || Mask.equals(1, 1, 3, 3))) {
20094 bool Lo = Mask.equals(0, 0, 2, 2);
20095 unsigned Shuffle = Lo ? X86ISD::MOVSLDUP : X86ISD::MOVSHDUP;
20096 MVT ShuffleVT = MVT::v4f32;
20097 if (Depth == 1 && Root->getOpcode() == Shuffle)
20098 return false; // Nothing to do!
20099 Op = DAG.getNode(ISD::BITCAST, DL, ShuffleVT, Input);
20100 DCI.AddToWorklist(Op.getNode());
20101 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op);
20102 DCI.AddToWorklist(Op.getNode());
20103 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Op),
20107 if (Mask.equals(0, 0, 1, 1) || Mask.equals(2, 2, 3, 3)) {
20108 bool Lo = Mask.equals(0, 0, 1, 1);
20109 unsigned Shuffle = Lo ? X86ISD::UNPCKL : X86ISD::UNPCKH;
20110 MVT ShuffleVT = MVT::v4f32;
20111 if (Depth == 1 && Root->getOpcode() == Shuffle)
20112 return false; // Nothing to do!
20113 Op = DAG.getNode(ISD::BITCAST, DL, ShuffleVT, Input);
20114 DCI.AddToWorklist(Op.getNode());
20115 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op, Op);
20116 DCI.AddToWorklist(Op.getNode());
20117 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Op),
20123 // We always canonicalize the 8 x i16 and 16 x i8 shuffles into their UNPCK
20124 // variants as none of these have single-instruction variants that are
20125 // superior to the UNPCK formulation.
20126 if (!FloatDomain &&
20127 (Mask.equals(0, 0, 1, 1, 2, 2, 3, 3) ||
20128 Mask.equals(4, 4, 5, 5, 6, 6, 7, 7) ||
20129 Mask.equals(0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7) ||
20130 Mask.equals(8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15,
20132 bool Lo = Mask[0] == 0;
20133 unsigned Shuffle = Lo ? X86ISD::UNPCKL : X86ISD::UNPCKH;
20134 if (Depth == 1 && Root->getOpcode() == Shuffle)
20135 return false; // Nothing to do!
20137 switch (Mask.size()) {
20139 ShuffleVT = MVT::v8i16;
20142 ShuffleVT = MVT::v16i8;
20145 llvm_unreachable("Impossible mask size!");
20147 Op = DAG.getNode(ISD::BITCAST, DL, ShuffleVT, Input);
20148 DCI.AddToWorklist(Op.getNode());
20149 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op, Op);
20150 DCI.AddToWorklist(Op.getNode());
20151 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Op),
20156 // Don't try to re-form single instruction chains under any circumstances now
20157 // that we've done encoding canonicalization for them.
20161 // If we have 3 or more shuffle instructions or a chain involving PSHUFB, we
20162 // can replace them with a single PSHUFB instruction profitably. Intel's
20163 // manuals suggest only using PSHUFB if doing so replacing 5 instructions, but
20164 // in practice PSHUFB tends to be *very* fast so we're more aggressive.
20165 if ((Depth >= 3 || HasPSHUFB) && Subtarget->hasSSSE3()) {
20166 SmallVector<SDValue, 16> PSHUFBMask;
20167 assert(Mask.size() <= 16 && "Can't shuffle elements smaller than bytes!");
20168 int Ratio = 16 / Mask.size();
20169 for (unsigned i = 0; i < 16; ++i) {
20170 int M = Mask[i / Ratio] != SM_SentinelZero
20171 ? Ratio * Mask[i / Ratio] + i % Ratio
20173 PSHUFBMask.push_back(DAG.getConstant(M, MVT::i8));
20175 Op = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, Input);
20176 DCI.AddToWorklist(Op.getNode());
20177 SDValue PSHUFBMaskOp =
20178 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v16i8, PSHUFBMask);
20179 DCI.AddToWorklist(PSHUFBMaskOp.getNode());
20180 Op = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8, Op, PSHUFBMaskOp);
20181 DCI.AddToWorklist(Op.getNode());
20182 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Op),
20187 // Failed to find any combines.
20191 /// \brief Fully generic combining of x86 shuffle instructions.
20193 /// This should be the last combine run over the x86 shuffle instructions. Once
20194 /// they have been fully optimized, this will recursively consider all chains
20195 /// of single-use shuffle instructions, build a generic model of the cumulative
20196 /// shuffle operation, and check for simpler instructions which implement this
20197 /// operation. We use this primarily for two purposes:
20199 /// 1) Collapse generic shuffles to specialized single instructions when
20200 /// equivalent. In most cases, this is just an encoding size win, but
20201 /// sometimes we will collapse multiple generic shuffles into a single
20202 /// special-purpose shuffle.
20203 /// 2) Look for sequences of shuffle instructions with 3 or more total
20204 /// instructions, and replace them with the slightly more expensive SSSE3
20205 /// PSHUFB instruction if available. We do this as the last combining step
20206 /// to ensure we avoid using PSHUFB if we can implement the shuffle with
20207 /// a suitable short sequence of other instructions. The PHUFB will either
20208 /// use a register or have to read from memory and so is slightly (but only
20209 /// slightly) more expensive than the other shuffle instructions.
20211 /// Because this is inherently a quadratic operation (for each shuffle in
20212 /// a chain, we recurse up the chain), the depth is limited to 8 instructions.
20213 /// This should never be an issue in practice as the shuffle lowering doesn't
20214 /// produce sequences of more than 8 instructions.
20216 /// FIXME: We will currently miss some cases where the redundant shuffling
20217 /// would simplify under the threshold for PSHUFB formation because of
20218 /// combine-ordering. To fix this, we should do the redundant instruction
20219 /// combining in this recursive walk.
20220 static bool combineX86ShufflesRecursively(SDValue Op, SDValue Root,
20221 ArrayRef<int> RootMask,
20222 int Depth, bool HasPSHUFB,
20224 TargetLowering::DAGCombinerInfo &DCI,
20225 const X86Subtarget *Subtarget) {
20226 // Bound the depth of our recursive combine because this is ultimately
20227 // quadratic in nature.
20231 // Directly rip through bitcasts to find the underlying operand.
20232 while (Op.getOpcode() == ISD::BITCAST && Op.getOperand(0).hasOneUse())
20233 Op = Op.getOperand(0);
20235 MVT VT = Op.getSimpleValueType();
20236 if (!VT.isVector())
20237 return false; // Bail if we hit a non-vector.
20238 // FIXME: This routine should be taught about 256-bit shuffles, or a 256-bit
20239 // version should be added.
20240 if (VT.getSizeInBits() != 128)
20243 assert(Root.getSimpleValueType().isVector() &&
20244 "Shuffles operate on vector types!");
20245 assert(VT.getSizeInBits() == Root.getSimpleValueType().getSizeInBits() &&
20246 "Can only combine shuffles of the same vector register size.");
20248 if (!isTargetShuffle(Op.getOpcode()))
20250 SmallVector<int, 16> OpMask;
20252 bool HaveMask = getTargetShuffleMask(Op.getNode(), VT, OpMask, IsUnary);
20253 // We only can combine unary shuffles which we can decode the mask for.
20254 if (!HaveMask || !IsUnary)
20257 assert(VT.getVectorNumElements() == OpMask.size() &&
20258 "Different mask size from vector size!");
20259 assert(((RootMask.size() > OpMask.size() &&
20260 RootMask.size() % OpMask.size() == 0) ||
20261 (OpMask.size() > RootMask.size() &&
20262 OpMask.size() % RootMask.size() == 0) ||
20263 OpMask.size() == RootMask.size()) &&
20264 "The smaller number of elements must divide the larger.");
20265 int RootRatio = std::max<int>(1, OpMask.size() / RootMask.size());
20266 int OpRatio = std::max<int>(1, RootMask.size() / OpMask.size());
20267 assert(((RootRatio == 1 && OpRatio == 1) ||
20268 (RootRatio == 1) != (OpRatio == 1)) &&
20269 "Must not have a ratio for both incoming and op masks!");
20271 SmallVector<int, 16> Mask;
20272 Mask.reserve(std::max(OpMask.size(), RootMask.size()));
20274 // Merge this shuffle operation's mask into our accumulated mask. Note that
20275 // this shuffle's mask will be the first applied to the input, followed by the
20276 // root mask to get us all the way to the root value arrangement. The reason
20277 // for this order is that we are recursing up the operation chain.
20278 for (int i = 0, e = std::max(OpMask.size(), RootMask.size()); i < e; ++i) {
20279 int RootIdx = i / RootRatio;
20280 if (RootMask[RootIdx] == SM_SentinelZero) {
20281 // This is a zero-ed lane, we're done.
20282 Mask.push_back(SM_SentinelZero);
20286 int RootMaskedIdx = RootMask[RootIdx] * RootRatio + i % RootRatio;
20287 int OpIdx = RootMaskedIdx / OpRatio;
20288 if (OpMask[OpIdx] == SM_SentinelZero) {
20289 // The incoming lanes are zero, it doesn't matter which ones we are using.
20290 Mask.push_back(SM_SentinelZero);
20294 // Ok, we have non-zero lanes, map them through.
20295 Mask.push_back(OpMask[OpIdx] * OpRatio +
20296 RootMaskedIdx % OpRatio);
20299 // See if we can recurse into the operand to combine more things.
20300 switch (Op.getOpcode()) {
20301 case X86ISD::PSHUFB:
20303 case X86ISD::PSHUFD:
20304 case X86ISD::PSHUFHW:
20305 case X86ISD::PSHUFLW:
20306 if (Op.getOperand(0).hasOneUse() &&
20307 combineX86ShufflesRecursively(Op.getOperand(0), Root, Mask, Depth + 1,
20308 HasPSHUFB, DAG, DCI, Subtarget))
20312 case X86ISD::UNPCKL:
20313 case X86ISD::UNPCKH:
20314 assert(Op.getOperand(0) == Op.getOperand(1) && "We only combine unary shuffles!");
20315 // We can't check for single use, we have to check that this shuffle is the only user.
20316 if (Op->isOnlyUserOf(Op.getOperand(0).getNode()) &&
20317 combineX86ShufflesRecursively(Op.getOperand(0), Root, Mask, Depth + 1,
20318 HasPSHUFB, DAG, DCI, Subtarget))
20323 // Minor canonicalization of the accumulated shuffle mask to make it easier
20324 // to match below. All this does is detect masks with squential pairs of
20325 // elements, and shrink them to the half-width mask. It does this in a loop
20326 // so it will reduce the size of the mask to the minimal width mask which
20327 // performs an equivalent shuffle.
20328 while (Mask.size() > 1 && canWidenShuffleElements(Mask)) {
20329 for (int i = 0, e = Mask.size() / 2; i < e; ++i)
20330 Mask[i] = Mask[2 * i] / 2;
20331 Mask.resize(Mask.size() / 2);
20334 return combineX86ShuffleChain(Op, Root, Mask, Depth, HasPSHUFB, DAG, DCI,
20338 /// \brief Get the PSHUF-style mask from PSHUF node.
20340 /// This is a very minor wrapper around getTargetShuffleMask to easy forming v4
20341 /// PSHUF-style masks that can be reused with such instructions.
20342 static SmallVector<int, 4> getPSHUFShuffleMask(SDValue N) {
20343 SmallVector<int, 4> Mask;
20345 bool HaveMask = getTargetShuffleMask(N.getNode(), N.getSimpleValueType(), Mask, IsUnary);
20349 switch (N.getOpcode()) {
20350 case X86ISD::PSHUFD:
20352 case X86ISD::PSHUFLW:
20355 case X86ISD::PSHUFHW:
20356 Mask.erase(Mask.begin(), Mask.begin() + 4);
20357 for (int &M : Mask)
20361 llvm_unreachable("No valid shuffle instruction found!");
20365 /// \brief Search for a combinable shuffle across a chain ending in pshufd.
20367 /// We walk up the chain and look for a combinable shuffle, skipping over
20368 /// shuffles that we could hoist this shuffle's transformation past without
20369 /// altering anything.
20371 combineRedundantDWordShuffle(SDValue N, MutableArrayRef<int> Mask,
20373 TargetLowering::DAGCombinerInfo &DCI) {
20374 assert(N.getOpcode() == X86ISD::PSHUFD &&
20375 "Called with something other than an x86 128-bit half shuffle!");
20378 // Walk up a single-use chain looking for a combinable shuffle. Keep a stack
20379 // of the shuffles in the chain so that we can form a fresh chain to replace
20381 SmallVector<SDValue, 8> Chain;
20382 SDValue V = N.getOperand(0);
20383 for (; V.hasOneUse(); V = V.getOperand(0)) {
20384 switch (V.getOpcode()) {
20386 return SDValue(); // Nothing combined!
20389 // Skip bitcasts as we always know the type for the target specific
20393 case X86ISD::PSHUFD:
20394 // Found another dword shuffle.
20397 case X86ISD::PSHUFLW:
20398 // Check that the low words (being shuffled) are the identity in the
20399 // dword shuffle, and the high words are self-contained.
20400 if (Mask[0] != 0 || Mask[1] != 1 ||
20401 !(Mask[2] >= 2 && Mask[2] < 4 && Mask[3] >= 2 && Mask[3] < 4))
20404 Chain.push_back(V);
20407 case X86ISD::PSHUFHW:
20408 // Check that the high words (being shuffled) are the identity in the
20409 // dword shuffle, and the low words are self-contained.
20410 if (Mask[2] != 2 || Mask[3] != 3 ||
20411 !(Mask[0] >= 0 && Mask[0] < 2 && Mask[1] >= 0 && Mask[1] < 2))
20414 Chain.push_back(V);
20417 case X86ISD::UNPCKL:
20418 case X86ISD::UNPCKH:
20419 // For either i8 -> i16 or i16 -> i32 unpacks, we can combine a dword
20420 // shuffle into a preceding word shuffle.
20421 if (V.getValueType() != MVT::v16i8 && V.getValueType() != MVT::v8i16)
20424 // Search for a half-shuffle which we can combine with.
20425 unsigned CombineOp =
20426 V.getOpcode() == X86ISD::UNPCKL ? X86ISD::PSHUFLW : X86ISD::PSHUFHW;
20427 if (V.getOperand(0) != V.getOperand(1) ||
20428 !V->isOnlyUserOf(V.getOperand(0).getNode()))
20430 Chain.push_back(V);
20431 V = V.getOperand(0);
20433 switch (V.getOpcode()) {
20435 return SDValue(); // Nothing to combine.
20437 case X86ISD::PSHUFLW:
20438 case X86ISD::PSHUFHW:
20439 if (V.getOpcode() == CombineOp)
20442 Chain.push_back(V);
20446 V = V.getOperand(0);
20450 } while (V.hasOneUse());
20453 // Break out of the loop if we break out of the switch.
20457 if (!V.hasOneUse())
20458 // We fell out of the loop without finding a viable combining instruction.
20461 // Merge this node's mask and our incoming mask.
20462 SmallVector<int, 4> VMask = getPSHUFShuffleMask(V);
20463 for (int &M : Mask)
20465 V = DAG.getNode(V.getOpcode(), DL, V.getValueType(), V.getOperand(0),
20466 getV4X86ShuffleImm8ForMask(Mask, DAG));
20468 // Rebuild the chain around this new shuffle.
20469 while (!Chain.empty()) {
20470 SDValue W = Chain.pop_back_val();
20472 if (V.getValueType() != W.getOperand(0).getValueType())
20473 V = DAG.getNode(ISD::BITCAST, DL, W.getOperand(0).getValueType(), V);
20475 switch (W.getOpcode()) {
20477 llvm_unreachable("Only PSHUF and UNPCK instructions get here!");
20479 case X86ISD::UNPCKL:
20480 case X86ISD::UNPCKH:
20481 V = DAG.getNode(W.getOpcode(), DL, W.getValueType(), V, V);
20484 case X86ISD::PSHUFD:
20485 case X86ISD::PSHUFLW:
20486 case X86ISD::PSHUFHW:
20487 V = DAG.getNode(W.getOpcode(), DL, W.getValueType(), V, W.getOperand(1));
20491 if (V.getValueType() != N.getValueType())
20492 V = DAG.getNode(ISD::BITCAST, DL, N.getValueType(), V);
20494 // Return the new chain to replace N.
20498 /// \brief Search for a combinable shuffle across a chain ending in pshuflw or pshufhw.
20500 /// We walk up the chain, skipping shuffles of the other half and looking
20501 /// through shuffles which switch halves trying to find a shuffle of the same
20502 /// pair of dwords.
20503 static bool combineRedundantHalfShuffle(SDValue N, MutableArrayRef<int> Mask,
20505 TargetLowering::DAGCombinerInfo &DCI) {
20507 (N.getOpcode() == X86ISD::PSHUFLW || N.getOpcode() == X86ISD::PSHUFHW) &&
20508 "Called with something other than an x86 128-bit half shuffle!");
20510 unsigned CombineOpcode = N.getOpcode();
20512 // Walk up a single-use chain looking for a combinable shuffle.
20513 SDValue V = N.getOperand(0);
20514 for (; V.hasOneUse(); V = V.getOperand(0)) {
20515 switch (V.getOpcode()) {
20517 return false; // Nothing combined!
20520 // Skip bitcasts as we always know the type for the target specific
20524 case X86ISD::PSHUFLW:
20525 case X86ISD::PSHUFHW:
20526 if (V.getOpcode() == CombineOpcode)
20529 // Other-half shuffles are no-ops.
20532 // Break out of the loop if we break out of the switch.
20536 if (!V.hasOneUse())
20537 // We fell out of the loop without finding a viable combining instruction.
20540 // Combine away the bottom node as its shuffle will be accumulated into
20541 // a preceding shuffle.
20542 DCI.CombineTo(N.getNode(), N.getOperand(0), /*AddTo*/ true);
20544 // Record the old value.
20547 // Merge this node's mask and our incoming mask (adjusted to account for all
20548 // the pshufd instructions encountered).
20549 SmallVector<int, 4> VMask = getPSHUFShuffleMask(V);
20550 for (int &M : Mask)
20552 V = DAG.getNode(V.getOpcode(), DL, MVT::v8i16, V.getOperand(0),
20553 getV4X86ShuffleImm8ForMask(Mask, DAG));
20555 // Check that the shuffles didn't cancel each other out. If not, we need to
20556 // combine to the new one.
20558 // Replace the combinable shuffle with the combined one, updating all users
20559 // so that we re-evaluate the chain here.
20560 DCI.CombineTo(Old.getNode(), V, /*AddTo*/ true);
20565 /// \brief Try to combine x86 target specific shuffles.
20566 static SDValue PerformTargetShuffleCombine(SDValue N, SelectionDAG &DAG,
20567 TargetLowering::DAGCombinerInfo &DCI,
20568 const X86Subtarget *Subtarget) {
20570 MVT VT = N.getSimpleValueType();
20571 SmallVector<int, 4> Mask;
20573 switch (N.getOpcode()) {
20574 case X86ISD::PSHUFD:
20575 case X86ISD::PSHUFLW:
20576 case X86ISD::PSHUFHW:
20577 Mask = getPSHUFShuffleMask(N);
20578 assert(Mask.size() == 4);
20584 // Nuke no-op shuffles that show up after combining.
20585 if (isNoopShuffleMask(Mask))
20586 return DCI.CombineTo(N.getNode(), N.getOperand(0), /*AddTo*/ true);
20588 // Look for simplifications involving one or two shuffle instructions.
20589 SDValue V = N.getOperand(0);
20590 switch (N.getOpcode()) {
20593 case X86ISD::PSHUFLW:
20594 case X86ISD::PSHUFHW:
20595 assert(VT == MVT::v8i16);
20598 if (combineRedundantHalfShuffle(N, Mask, DAG, DCI))
20599 return SDValue(); // We combined away this shuffle, so we're done.
20601 // See if this reduces to a PSHUFD which is no more expensive and can
20602 // combine with more operations.
20603 if (canWidenShuffleElements(Mask)) {
20604 int DMask[] = {-1, -1, -1, -1};
20605 int DOffset = N.getOpcode() == X86ISD::PSHUFLW ? 0 : 2;
20606 DMask[DOffset + 0] = DOffset + Mask[0] / 2;
20607 DMask[DOffset + 1] = DOffset + Mask[2] / 2;
20608 V = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, V);
20609 DCI.AddToWorklist(V.getNode());
20610 V = DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32, V,
20611 getV4X86ShuffleImm8ForMask(DMask, DAG));
20612 DCI.AddToWorklist(V.getNode());
20613 return DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V);
20616 // Look for shuffle patterns which can be implemented as a single unpack.
20617 // FIXME: This doesn't handle the location of the PSHUFD generically, and
20618 // only works when we have a PSHUFD followed by two half-shuffles.
20619 if (Mask[0] == Mask[1] && Mask[2] == Mask[3] &&
20620 (V.getOpcode() == X86ISD::PSHUFLW ||
20621 V.getOpcode() == X86ISD::PSHUFHW) &&
20622 V.getOpcode() != N.getOpcode() &&
20624 SDValue D = V.getOperand(0);
20625 while (D.getOpcode() == ISD::BITCAST && D.hasOneUse())
20626 D = D.getOperand(0);
20627 if (D.getOpcode() == X86ISD::PSHUFD && D.hasOneUse()) {
20628 SmallVector<int, 4> VMask = getPSHUFShuffleMask(V);
20629 SmallVector<int, 4> DMask = getPSHUFShuffleMask(D);
20630 int NOffset = N.getOpcode() == X86ISD::PSHUFLW ? 0 : 4;
20631 int VOffset = V.getOpcode() == X86ISD::PSHUFLW ? 0 : 4;
20633 for (int i = 0; i < 4; ++i) {
20634 WordMask[i + NOffset] = Mask[i] + NOffset;
20635 WordMask[i + VOffset] = VMask[i] + VOffset;
20637 // Map the word mask through the DWord mask.
20639 for (int i = 0; i < 8; ++i)
20640 MappedMask[i] = 2 * DMask[WordMask[i] / 2] + WordMask[i] % 2;
20641 const int UnpackLoMask[] = {0, 0, 1, 1, 2, 2, 3, 3};
20642 const int UnpackHiMask[] = {4, 4, 5, 5, 6, 6, 7, 7};
20643 if (std::equal(std::begin(MappedMask), std::end(MappedMask),
20644 std::begin(UnpackLoMask)) ||
20645 std::equal(std::begin(MappedMask), std::end(MappedMask),
20646 std::begin(UnpackHiMask))) {
20647 // We can replace all three shuffles with an unpack.
20648 V = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, D.getOperand(0));
20649 DCI.AddToWorklist(V.getNode());
20650 return DAG.getNode(MappedMask[0] == 0 ? X86ISD::UNPCKL
20652 DL, MVT::v8i16, V, V);
20659 case X86ISD::PSHUFD:
20660 if (SDValue NewN = combineRedundantDWordShuffle(N, Mask, DAG, DCI))
20669 /// \brief Try to combine a shuffle into a target-specific add-sub node.
20671 /// We combine this directly on the abstract vector shuffle nodes so it is
20672 /// easier to generically match. We also insert dummy vector shuffle nodes for
20673 /// the operands which explicitly discard the lanes which are unused by this
20674 /// operation to try to flow through the rest of the combiner the fact that
20675 /// they're unused.
20676 static SDValue combineShuffleToAddSub(SDNode *N, SelectionDAG &DAG) {
20678 EVT VT = N->getValueType(0);
20680 // We only handle target-independent shuffles.
20681 // FIXME: It would be easy and harmless to use the target shuffle mask
20682 // extraction tool to support more.
20683 if (N->getOpcode() != ISD::VECTOR_SHUFFLE)
20686 auto *SVN = cast<ShuffleVectorSDNode>(N);
20687 ArrayRef<int> Mask = SVN->getMask();
20688 SDValue V1 = N->getOperand(0);
20689 SDValue V2 = N->getOperand(1);
20691 // We require the first shuffle operand to be the SUB node, and the second to
20692 // be the ADD node.
20693 // FIXME: We should support the commuted patterns.
20694 if (V1->getOpcode() != ISD::FSUB || V2->getOpcode() != ISD::FADD)
20697 // If there are other uses of these operations we can't fold them.
20698 if (!V1->hasOneUse() || !V2->hasOneUse())
20701 // Ensure that both operations have the same operands. Note that we can
20702 // commute the FADD operands.
20703 SDValue LHS = V1->getOperand(0), RHS = V1->getOperand(1);
20704 if ((V2->getOperand(0) != LHS || V2->getOperand(1) != RHS) &&
20705 (V2->getOperand(0) != RHS || V2->getOperand(1) != LHS))
20708 // We're looking for blends between FADD and FSUB nodes. We insist on these
20709 // nodes being lined up in a specific expected pattern.
20710 if (!(isShuffleEquivalent(Mask, 0, 3) ||
20711 isShuffleEquivalent(Mask, 0, 5, 2, 7) ||
20712 isShuffleEquivalent(Mask, 0, 9, 2, 11, 4, 13, 6, 15)))
20715 // Only specific types are legal at this point, assert so we notice if and
20716 // when these change.
20717 assert((VT == MVT::v4f32 || VT == MVT::v2f64 || VT == MVT::v8f32 ||
20718 VT == MVT::v4f64) &&
20719 "Unknown vector type encountered!");
20721 return DAG.getNode(X86ISD::ADDSUB, DL, VT, LHS, RHS);
20724 /// PerformShuffleCombine - Performs several different shuffle combines.
20725 static SDValue PerformShuffleCombine(SDNode *N, SelectionDAG &DAG,
20726 TargetLowering::DAGCombinerInfo &DCI,
20727 const X86Subtarget *Subtarget) {
20729 SDValue N0 = N->getOperand(0);
20730 SDValue N1 = N->getOperand(1);
20731 EVT VT = N->getValueType(0);
20733 // Don't create instructions with illegal types after legalize types has run.
20734 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
20735 if (!DCI.isBeforeLegalize() && !TLI.isTypeLegal(VT.getVectorElementType()))
20738 // If we have legalized the vector types, look for blends of FADD and FSUB
20739 // nodes that we can fuse into an ADDSUB node.
20740 if (TLI.isTypeLegal(VT) && Subtarget->hasSSE3())
20741 if (SDValue AddSub = combineShuffleToAddSub(N, DAG))
20744 // Combine 256-bit vector shuffles. This is only profitable when in AVX mode
20745 if (Subtarget->hasFp256() && VT.is256BitVector() &&
20746 N->getOpcode() == ISD::VECTOR_SHUFFLE)
20747 return PerformShuffleCombine256(N, DAG, DCI, Subtarget);
20749 // During Type Legalization, when promoting illegal vector types,
20750 // the backend might introduce new shuffle dag nodes and bitcasts.
20752 // This code performs the following transformation:
20753 // fold: (shuffle (bitcast (BINOP A, B)), Undef, <Mask>) ->
20754 // (shuffle (BINOP (bitcast A), (bitcast B)), Undef, <Mask>)
20756 // We do this only if both the bitcast and the BINOP dag nodes have
20757 // one use. Also, perform this transformation only if the new binary
20758 // operation is legal. This is to avoid introducing dag nodes that
20759 // potentially need to be further expanded (or custom lowered) into a
20760 // less optimal sequence of dag nodes.
20761 if (!DCI.isBeforeLegalize() && DCI.isBeforeLegalizeOps() &&
20762 N1.getOpcode() == ISD::UNDEF && N0.hasOneUse() &&
20763 N0.getOpcode() == ISD::BITCAST) {
20764 SDValue BC0 = N0.getOperand(0);
20765 EVT SVT = BC0.getValueType();
20766 unsigned Opcode = BC0.getOpcode();
20767 unsigned NumElts = VT.getVectorNumElements();
20769 if (BC0.hasOneUse() && SVT.isVector() &&
20770 SVT.getVectorNumElements() * 2 == NumElts &&
20771 TLI.isOperationLegal(Opcode, VT)) {
20772 bool CanFold = false;
20784 unsigned SVTNumElts = SVT.getVectorNumElements();
20785 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
20786 for (unsigned i = 0, e = SVTNumElts; i != e && CanFold; ++i)
20787 CanFold = SVOp->getMaskElt(i) == (int)(i * 2);
20788 for (unsigned i = SVTNumElts, e = NumElts; i != e && CanFold; ++i)
20789 CanFold = SVOp->getMaskElt(i) < 0;
20792 SDValue BC00 = DAG.getNode(ISD::BITCAST, dl, VT, BC0.getOperand(0));
20793 SDValue BC01 = DAG.getNode(ISD::BITCAST, dl, VT, BC0.getOperand(1));
20794 SDValue NewBinOp = DAG.getNode(BC0.getOpcode(), dl, VT, BC00, BC01);
20795 return DAG.getVectorShuffle(VT, dl, NewBinOp, N1, &SVOp->getMask()[0]);
20800 // Only handle 128 wide vector from here on.
20801 if (!VT.is128BitVector())
20804 // Combine a vector_shuffle that is equal to build_vector load1, load2, load3,
20805 // load4, <0, 1, 2, 3> into a 128-bit load if the load addresses are
20806 // consecutive, non-overlapping, and in the right order.
20807 SmallVector<SDValue, 16> Elts;
20808 for (unsigned i = 0, e = VT.getVectorNumElements(); i != e; ++i)
20809 Elts.push_back(getShuffleScalarElt(N, i, DAG, 0));
20811 SDValue LD = EltsFromConsecutiveLoads(VT, Elts, dl, DAG, true);
20815 if (isTargetShuffle(N->getOpcode())) {
20817 PerformTargetShuffleCombine(SDValue(N, 0), DAG, DCI, Subtarget);
20818 if (Shuffle.getNode())
20821 // Try recursively combining arbitrary sequences of x86 shuffle
20822 // instructions into higher-order shuffles. We do this after combining
20823 // specific PSHUF instruction sequences into their minimal form so that we
20824 // can evaluate how many specialized shuffle instructions are involved in
20825 // a particular chain.
20826 SmallVector<int, 1> NonceMask; // Just a placeholder.
20827 NonceMask.push_back(0);
20828 if (combineX86ShufflesRecursively(SDValue(N, 0), SDValue(N, 0), NonceMask,
20829 /*Depth*/ 1, /*HasPSHUFB*/ false, DAG,
20831 return SDValue(); // This routine will use CombineTo to replace N.
20837 /// PerformTruncateCombine - Converts truncate operation to
20838 /// a sequence of vector shuffle operations.
20839 /// It is possible when we truncate 256-bit vector to 128-bit vector
20840 static SDValue PerformTruncateCombine(SDNode *N, SelectionDAG &DAG,
20841 TargetLowering::DAGCombinerInfo &DCI,
20842 const X86Subtarget *Subtarget) {
20846 /// XFormVExtractWithShuffleIntoLoad - Check if a vector extract from a target
20847 /// specific shuffle of a load can be folded into a single element load.
20848 /// Similar handling for VECTOR_SHUFFLE is performed by DAGCombiner, but
20849 /// shuffles have been customed lowered so we need to handle those here.
20850 static SDValue XFormVExtractWithShuffleIntoLoad(SDNode *N, SelectionDAG &DAG,
20851 TargetLowering::DAGCombinerInfo &DCI) {
20852 if (DCI.isBeforeLegalizeOps())
20855 SDValue InVec = N->getOperand(0);
20856 SDValue EltNo = N->getOperand(1);
20858 if (!isa<ConstantSDNode>(EltNo))
20861 EVT VT = InVec.getValueType();
20863 if (InVec.getOpcode() == ISD::BITCAST) {
20864 // Don't duplicate a load with other uses.
20865 if (!InVec.hasOneUse())
20867 EVT BCVT = InVec.getOperand(0).getValueType();
20868 if (BCVT.getVectorNumElements() != VT.getVectorNumElements())
20870 InVec = InVec.getOperand(0);
20873 if (!isTargetShuffle(InVec.getOpcode()))
20876 // Don't duplicate a load with other uses.
20877 if (!InVec.hasOneUse())
20880 SmallVector<int, 16> ShuffleMask;
20882 if (!getTargetShuffleMask(InVec.getNode(), VT.getSimpleVT(), ShuffleMask,
20886 // Select the input vector, guarding against out of range extract vector.
20887 unsigned NumElems = VT.getVectorNumElements();
20888 int Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();
20889 int Idx = (Elt > (int)NumElems) ? -1 : ShuffleMask[Elt];
20890 SDValue LdNode = (Idx < (int)NumElems) ? InVec.getOperand(0)
20891 : InVec.getOperand(1);
20893 // If inputs to shuffle are the same for both ops, then allow 2 uses
20894 unsigned AllowedUses = InVec.getOperand(0) == InVec.getOperand(1) ? 2 : 1;
20896 if (LdNode.getOpcode() == ISD::BITCAST) {
20897 // Don't duplicate a load with other uses.
20898 if (!LdNode.getNode()->hasNUsesOfValue(AllowedUses, 0))
20901 AllowedUses = 1; // only allow 1 load use if we have a bitcast
20902 LdNode = LdNode.getOperand(0);
20905 if (!ISD::isNormalLoad(LdNode.getNode()))
20908 LoadSDNode *LN0 = cast<LoadSDNode>(LdNode);
20910 if (!LN0 ||!LN0->hasNUsesOfValue(AllowedUses, 0) || LN0->isVolatile())
20913 EVT EltVT = N->getValueType(0);
20914 // If there's a bitcast before the shuffle, check if the load type and
20915 // alignment is valid.
20916 unsigned Align = LN0->getAlignment();
20917 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
20918 unsigned NewAlign = TLI.getDataLayout()->getABITypeAlignment(
20919 EltVT.getTypeForEVT(*DAG.getContext()));
20921 if (NewAlign > Align || !TLI.isOperationLegalOrCustom(ISD::LOAD, EltVT))
20924 // All checks match so transform back to vector_shuffle so that DAG combiner
20925 // can finish the job
20928 // Create shuffle node taking into account the case that its a unary shuffle
20929 SDValue Shuffle = (UnaryShuffle) ? DAG.getUNDEF(VT) : InVec.getOperand(1);
20930 Shuffle = DAG.getVectorShuffle(InVec.getValueType(), dl,
20931 InVec.getOperand(0), Shuffle,
20933 Shuffle = DAG.getNode(ISD::BITCAST, dl, VT, Shuffle);
20934 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, N->getValueType(0), Shuffle,
20938 /// PerformEXTRACT_VECTOR_ELTCombine - Detect vector gather/scatter index
20939 /// generation and convert it from being a bunch of shuffles and extracts
20940 /// to a simple store and scalar loads to extract the elements.
20941 static SDValue PerformEXTRACT_VECTOR_ELTCombine(SDNode *N, SelectionDAG &DAG,
20942 TargetLowering::DAGCombinerInfo &DCI) {
20943 SDValue NewOp = XFormVExtractWithShuffleIntoLoad(N, DAG, DCI);
20944 if (NewOp.getNode())
20947 SDValue InputVector = N->getOperand(0);
20949 // Detect whether we are trying to convert from mmx to i32 and the bitcast
20950 // from mmx to v2i32 has a single usage.
20951 if (InputVector.getNode()->getOpcode() == llvm::ISD::BITCAST &&
20952 InputVector.getNode()->getOperand(0).getValueType() == MVT::x86mmx &&
20953 InputVector.hasOneUse() && N->getValueType(0) == MVT::i32)
20954 return DAG.getNode(X86ISD::MMX_MOVD2W, SDLoc(InputVector),
20955 N->getValueType(0),
20956 InputVector.getNode()->getOperand(0));
20958 // Only operate on vectors of 4 elements, where the alternative shuffling
20959 // gets to be more expensive.
20960 if (InputVector.getValueType() != MVT::v4i32)
20963 // Check whether every use of InputVector is an EXTRACT_VECTOR_ELT with a
20964 // single use which is a sign-extend or zero-extend, and all elements are
20966 SmallVector<SDNode *, 4> Uses;
20967 unsigned ExtractedElements = 0;
20968 for (SDNode::use_iterator UI = InputVector.getNode()->use_begin(),
20969 UE = InputVector.getNode()->use_end(); UI != UE; ++UI) {
20970 if (UI.getUse().getResNo() != InputVector.getResNo())
20973 SDNode *Extract = *UI;
20974 if (Extract->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
20977 if (Extract->getValueType(0) != MVT::i32)
20979 if (!Extract->hasOneUse())
20981 if (Extract->use_begin()->getOpcode() != ISD::SIGN_EXTEND &&
20982 Extract->use_begin()->getOpcode() != ISD::ZERO_EXTEND)
20984 if (!isa<ConstantSDNode>(Extract->getOperand(1)))
20987 // Record which element was extracted.
20988 ExtractedElements |=
20989 1 << cast<ConstantSDNode>(Extract->getOperand(1))->getZExtValue();
20991 Uses.push_back(Extract);
20994 // If not all the elements were used, this may not be worthwhile.
20995 if (ExtractedElements != 15)
20998 // Ok, we've now decided to do the transformation.
20999 SDLoc dl(InputVector);
21001 // Store the value to a temporary stack slot.
21002 SDValue StackPtr = DAG.CreateStackTemporary(InputVector.getValueType());
21003 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, InputVector, StackPtr,
21004 MachinePointerInfo(), false, false, 0);
21006 // Replace each use (extract) with a load of the appropriate element.
21007 for (SmallVectorImpl<SDNode *>::iterator UI = Uses.begin(),
21008 UE = Uses.end(); UI != UE; ++UI) {
21009 SDNode *Extract = *UI;
21011 // cOMpute the element's address.
21012 SDValue Idx = Extract->getOperand(1);
21014 InputVector.getValueType().getVectorElementType().getSizeInBits()/8;
21015 uint64_t Offset = EltSize * cast<ConstantSDNode>(Idx)->getZExtValue();
21016 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
21017 SDValue OffsetVal = DAG.getConstant(Offset, TLI.getPointerTy());
21019 SDValue ScalarAddr = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(),
21020 StackPtr, OffsetVal);
21022 // Load the scalar.
21023 SDValue LoadScalar = DAG.getLoad(Extract->getValueType(0), dl, Ch,
21024 ScalarAddr, MachinePointerInfo(),
21025 false, false, false, 0);
21027 // Replace the exact with the load.
21028 DAG.ReplaceAllUsesOfValueWith(SDValue(Extract, 0), LoadScalar);
21031 // The replacement was made in place; don't return anything.
21035 /// \brief Matches a VSELECT onto min/max or return 0 if the node doesn't match.
21036 static std::pair<unsigned, bool>
21037 matchIntegerMINMAX(SDValue Cond, EVT VT, SDValue LHS, SDValue RHS,
21038 SelectionDAG &DAG, const X86Subtarget *Subtarget) {
21039 if (!VT.isVector())
21040 return std::make_pair(0, false);
21042 bool NeedSplit = false;
21043 switch (VT.getSimpleVT().SimpleTy) {
21044 default: return std::make_pair(0, false);
21048 if (!Subtarget->hasAVX2())
21050 if (!Subtarget->hasAVX())
21051 return std::make_pair(0, false);
21056 if (!Subtarget->hasSSE2())
21057 return std::make_pair(0, false);
21060 // SSE2 has only a small subset of the operations.
21061 bool hasUnsigned = Subtarget->hasSSE41() ||
21062 (Subtarget->hasSSE2() && VT == MVT::v16i8);
21063 bool hasSigned = Subtarget->hasSSE41() ||
21064 (Subtarget->hasSSE2() && VT == MVT::v8i16);
21066 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
21069 // Check for x CC y ? x : y.
21070 if (DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
21071 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
21076 Opc = hasUnsigned ? X86ISD::UMIN : 0; break;
21079 Opc = hasUnsigned ? X86ISD::UMAX : 0; break;
21082 Opc = hasSigned ? X86ISD::SMIN : 0; break;
21085 Opc = hasSigned ? X86ISD::SMAX : 0; break;
21087 // Check for x CC y ? y : x -- a min/max with reversed arms.
21088 } else if (DAG.isEqualTo(LHS, Cond.getOperand(1)) &&
21089 DAG.isEqualTo(RHS, Cond.getOperand(0))) {
21094 Opc = hasUnsigned ? X86ISD::UMAX : 0; break;
21097 Opc = hasUnsigned ? X86ISD::UMIN : 0; break;
21100 Opc = hasSigned ? X86ISD::SMAX : 0; break;
21103 Opc = hasSigned ? X86ISD::SMIN : 0; break;
21107 return std::make_pair(Opc, NeedSplit);
21111 TransformVSELECTtoBlendVECTOR_SHUFFLE(SDNode *N, SelectionDAG &DAG,
21112 const X86Subtarget *Subtarget) {
21114 SDValue Cond = N->getOperand(0);
21115 SDValue LHS = N->getOperand(1);
21116 SDValue RHS = N->getOperand(2);
21118 if (Cond.getOpcode() == ISD::SIGN_EXTEND) {
21119 SDValue CondSrc = Cond->getOperand(0);
21120 if (CondSrc->getOpcode() == ISD::SIGN_EXTEND_INREG)
21121 Cond = CondSrc->getOperand(0);
21124 MVT VT = N->getSimpleValueType(0);
21125 MVT EltVT = VT.getVectorElementType();
21126 unsigned NumElems = VT.getVectorNumElements();
21127 // There is no blend with immediate in AVX-512.
21128 if (VT.is512BitVector())
21131 if (!Subtarget->hasSSE41() || EltVT == MVT::i8)
21133 if (!Subtarget->hasInt256() && VT == MVT::v16i16)
21136 if (!ISD::isBuildVectorOfConstantSDNodes(Cond.getNode()))
21139 // A vselect where all conditions and data are constants can be optimized into
21140 // a single vector load by SelectionDAGLegalize::ExpandBUILD_VECTOR().
21141 if (ISD::isBuildVectorOfConstantSDNodes(LHS.getNode()) &&
21142 ISD::isBuildVectorOfConstantSDNodes(RHS.getNode()))
21145 unsigned MaskValue = 0;
21146 if (!BUILD_VECTORtoBlendMask(cast<BuildVectorSDNode>(Cond), MaskValue))
21149 SmallVector<int, 8> ShuffleMask(NumElems, -1);
21150 for (unsigned i = 0; i < NumElems; ++i) {
21151 // Be sure we emit undef where we can.
21152 if (Cond.getOperand(i)->getOpcode() == ISD::UNDEF)
21153 ShuffleMask[i] = -1;
21155 ShuffleMask[i] = i + NumElems * ((MaskValue >> i) & 1);
21158 return DAG.getVectorShuffle(VT, dl, LHS, RHS, &ShuffleMask[0]);
21161 /// PerformSELECTCombine - Do target-specific dag combines on SELECT and VSELECT
21163 static SDValue PerformSELECTCombine(SDNode *N, SelectionDAG &DAG,
21164 TargetLowering::DAGCombinerInfo &DCI,
21165 const X86Subtarget *Subtarget) {
21167 SDValue Cond = N->getOperand(0);
21168 // Get the LHS/RHS of the select.
21169 SDValue LHS = N->getOperand(1);
21170 SDValue RHS = N->getOperand(2);
21171 EVT VT = LHS.getValueType();
21172 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
21174 // If we have SSE[12] support, try to form min/max nodes. SSE min/max
21175 // instructions match the semantics of the common C idiom x<y?x:y but not
21176 // x<=y?x:y, because of how they handle negative zero (which can be
21177 // ignored in unsafe-math mode).
21178 if (Cond.getOpcode() == ISD::SETCC && VT.isFloatingPoint() &&
21179 VT != MVT::f80 && TLI.isTypeLegal(VT) &&
21180 (Subtarget->hasSSE2() ||
21181 (Subtarget->hasSSE1() && VT.getScalarType() == MVT::f32))) {
21182 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
21184 unsigned Opcode = 0;
21185 // Check for x CC y ? x : y.
21186 if (DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
21187 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
21191 // Converting this to a min would handle NaNs incorrectly, and swapping
21192 // the operands would cause it to handle comparisons between positive
21193 // and negative zero incorrectly.
21194 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
21195 if (!DAG.getTarget().Options.UnsafeFPMath &&
21196 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
21198 std::swap(LHS, RHS);
21200 Opcode = X86ISD::FMIN;
21203 // Converting this to a min would handle comparisons between positive
21204 // and negative zero incorrectly.
21205 if (!DAG.getTarget().Options.UnsafeFPMath &&
21206 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
21208 Opcode = X86ISD::FMIN;
21211 // Converting this to a min would handle both negative zeros and NaNs
21212 // incorrectly, but we can swap the operands to fix both.
21213 std::swap(LHS, RHS);
21217 Opcode = X86ISD::FMIN;
21221 // Converting this to a max would handle comparisons between positive
21222 // and negative zero incorrectly.
21223 if (!DAG.getTarget().Options.UnsafeFPMath &&
21224 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
21226 Opcode = X86ISD::FMAX;
21229 // Converting this to a max would handle NaNs incorrectly, and swapping
21230 // the operands would cause it to handle comparisons between positive
21231 // and negative zero incorrectly.
21232 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
21233 if (!DAG.getTarget().Options.UnsafeFPMath &&
21234 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
21236 std::swap(LHS, RHS);
21238 Opcode = X86ISD::FMAX;
21241 // Converting this to a max would handle both negative zeros and NaNs
21242 // incorrectly, but we can swap the operands to fix both.
21243 std::swap(LHS, RHS);
21247 Opcode = X86ISD::FMAX;
21250 // Check for x CC y ? y : x -- a min/max with reversed arms.
21251 } else if (DAG.isEqualTo(LHS, Cond.getOperand(1)) &&
21252 DAG.isEqualTo(RHS, Cond.getOperand(0))) {
21256 // Converting this to a min would handle comparisons between positive
21257 // and negative zero incorrectly, and swapping the operands would
21258 // cause it to handle NaNs incorrectly.
21259 if (!DAG.getTarget().Options.UnsafeFPMath &&
21260 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS))) {
21261 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
21263 std::swap(LHS, RHS);
21265 Opcode = X86ISD::FMIN;
21268 // Converting this to a min would handle NaNs incorrectly.
21269 if (!DAG.getTarget().Options.UnsafeFPMath &&
21270 (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)))
21272 Opcode = X86ISD::FMIN;
21275 // Converting this to a min would handle both negative zeros and NaNs
21276 // incorrectly, but we can swap the operands to fix both.
21277 std::swap(LHS, RHS);
21281 Opcode = X86ISD::FMIN;
21285 // Converting this to a max would handle NaNs incorrectly.
21286 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
21288 Opcode = X86ISD::FMAX;
21291 // Converting this to a max would handle comparisons between positive
21292 // and negative zero incorrectly, and swapping the operands would
21293 // cause it to handle NaNs incorrectly.
21294 if (!DAG.getTarget().Options.UnsafeFPMath &&
21295 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS)) {
21296 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
21298 std::swap(LHS, RHS);
21300 Opcode = X86ISD::FMAX;
21303 // Converting this to a max would handle both negative zeros and NaNs
21304 // incorrectly, but we can swap the operands to fix both.
21305 std::swap(LHS, RHS);
21309 Opcode = X86ISD::FMAX;
21315 return DAG.getNode(Opcode, DL, N->getValueType(0), LHS, RHS);
21318 EVT CondVT = Cond.getValueType();
21319 if (Subtarget->hasAVX512() && VT.isVector() && CondVT.isVector() &&
21320 CondVT.getVectorElementType() == MVT::i1) {
21321 // v16i8 (select v16i1, v16i8, v16i8) does not have a proper
21322 // lowering on KNL. In this case we convert it to
21323 // v16i8 (select v16i8, v16i8, v16i8) and use AVX instruction.
21324 // The same situation for all 128 and 256-bit vectors of i8 and i16.
21325 // Since SKX these selects have a proper lowering.
21326 EVT OpVT = LHS.getValueType();
21327 if ((OpVT.is128BitVector() || OpVT.is256BitVector()) &&
21328 (OpVT.getVectorElementType() == MVT::i8 ||
21329 OpVT.getVectorElementType() == MVT::i16) &&
21330 !(Subtarget->hasBWI() && Subtarget->hasVLX())) {
21331 Cond = DAG.getNode(ISD::SIGN_EXTEND, DL, OpVT, Cond);
21332 DCI.AddToWorklist(Cond.getNode());
21333 return DAG.getNode(N->getOpcode(), DL, OpVT, Cond, LHS, RHS);
21336 // If this is a select between two integer constants, try to do some
21338 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(LHS)) {
21339 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(RHS))
21340 // Don't do this for crazy integer types.
21341 if (DAG.getTargetLoweringInfo().isTypeLegal(LHS.getValueType())) {
21342 // If this is efficiently invertible, canonicalize the LHSC/RHSC values
21343 // so that TrueC (the true value) is larger than FalseC.
21344 bool NeedsCondInvert = false;
21346 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue()) &&
21347 // Efficiently invertible.
21348 (Cond.getOpcode() == ISD::SETCC || // setcc -> invertible.
21349 (Cond.getOpcode() == ISD::XOR && // xor(X, C) -> invertible.
21350 isa<ConstantSDNode>(Cond.getOperand(1))))) {
21351 NeedsCondInvert = true;
21352 std::swap(TrueC, FalseC);
21355 // Optimize C ? 8 : 0 -> zext(C) << 3. Likewise for any pow2/0.
21356 if (FalseC->getAPIntValue() == 0 &&
21357 TrueC->getAPIntValue().isPowerOf2()) {
21358 if (NeedsCondInvert) // Invert the condition if needed.
21359 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
21360 DAG.getConstant(1, Cond.getValueType()));
21362 // Zero extend the condition if needed.
21363 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, LHS.getValueType(), Cond);
21365 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
21366 return DAG.getNode(ISD::SHL, DL, LHS.getValueType(), Cond,
21367 DAG.getConstant(ShAmt, MVT::i8));
21370 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst.
21371 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
21372 if (NeedsCondInvert) // Invert the condition if needed.
21373 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
21374 DAG.getConstant(1, Cond.getValueType()));
21376 // Zero extend the condition if needed.
21377 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
21378 FalseC->getValueType(0), Cond);
21379 return DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
21380 SDValue(FalseC, 0));
21383 // Optimize cases that will turn into an LEA instruction. This requires
21384 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
21385 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
21386 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
21387 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
21389 bool isFastMultiplier = false;
21391 switch ((unsigned char)Diff) {
21393 case 1: // result = add base, cond
21394 case 2: // result = lea base( , cond*2)
21395 case 3: // result = lea base(cond, cond*2)
21396 case 4: // result = lea base( , cond*4)
21397 case 5: // result = lea base(cond, cond*4)
21398 case 8: // result = lea base( , cond*8)
21399 case 9: // result = lea base(cond, cond*8)
21400 isFastMultiplier = true;
21405 if (isFastMultiplier) {
21406 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
21407 if (NeedsCondInvert) // Invert the condition if needed.
21408 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
21409 DAG.getConstant(1, Cond.getValueType()));
21411 // Zero extend the condition if needed.
21412 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
21414 // Scale the condition by the difference.
21416 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
21417 DAG.getConstant(Diff, Cond.getValueType()));
21419 // Add the base if non-zero.
21420 if (FalseC->getAPIntValue() != 0)
21421 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
21422 SDValue(FalseC, 0));
21429 // Canonicalize max and min:
21430 // (x > y) ? x : y -> (x >= y) ? x : y
21431 // (x < y) ? x : y -> (x <= y) ? x : y
21432 // This allows use of COND_S / COND_NS (see TranslateX86CC) which eliminates
21433 // the need for an extra compare
21434 // against zero. e.g.
21435 // (x - y) > 0 : (x - y) ? 0 -> (x - y) >= 0 : (x - y) ? 0
21437 // testl %edi, %edi
21439 // cmovgl %edi, %eax
21443 // cmovsl %eax, %edi
21444 if (N->getOpcode() == ISD::SELECT && Cond.getOpcode() == ISD::SETCC &&
21445 DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
21446 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
21447 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
21452 ISD::CondCode NewCC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGE;
21453 Cond = DAG.getSetCC(SDLoc(Cond), Cond.getValueType(),
21454 Cond.getOperand(0), Cond.getOperand(1), NewCC);
21455 return DAG.getNode(ISD::SELECT, DL, VT, Cond, LHS, RHS);
21460 // Early exit check
21461 if (!TLI.isTypeLegal(VT))
21464 // Match VSELECTs into subs with unsigned saturation.
21465 if (N->getOpcode() == ISD::VSELECT && Cond.getOpcode() == ISD::SETCC &&
21466 // psubus is available in SSE2 and AVX2 for i8 and i16 vectors.
21467 ((Subtarget->hasSSE2() && (VT == MVT::v16i8 || VT == MVT::v8i16)) ||
21468 (Subtarget->hasAVX2() && (VT == MVT::v32i8 || VT == MVT::v16i16)))) {
21469 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
21471 // Check if one of the arms of the VSELECT is a zero vector. If it's on the
21472 // left side invert the predicate to simplify logic below.
21474 if (ISD::isBuildVectorAllZeros(LHS.getNode())) {
21476 CC = ISD::getSetCCInverse(CC, true);
21477 } else if (ISD::isBuildVectorAllZeros(RHS.getNode())) {
21481 if (Other.getNode() && Other->getNumOperands() == 2 &&
21482 DAG.isEqualTo(Other->getOperand(0), Cond.getOperand(0))) {
21483 SDValue OpLHS = Other->getOperand(0), OpRHS = Other->getOperand(1);
21484 SDValue CondRHS = Cond->getOperand(1);
21486 // Look for a general sub with unsigned saturation first.
21487 // x >= y ? x-y : 0 --> subus x, y
21488 // x > y ? x-y : 0 --> subus x, y
21489 if ((CC == ISD::SETUGE || CC == ISD::SETUGT) &&
21490 Other->getOpcode() == ISD::SUB && DAG.isEqualTo(OpRHS, CondRHS))
21491 return DAG.getNode(X86ISD::SUBUS, DL, VT, OpLHS, OpRHS);
21493 if (auto *OpRHSBV = dyn_cast<BuildVectorSDNode>(OpRHS))
21494 if (auto *OpRHSConst = OpRHSBV->getConstantSplatNode()) {
21495 if (auto *CondRHSBV = dyn_cast<BuildVectorSDNode>(CondRHS))
21496 if (auto *CondRHSConst = CondRHSBV->getConstantSplatNode())
21497 // If the RHS is a constant we have to reverse the const
21498 // canonicalization.
21499 // x > C-1 ? x+-C : 0 --> subus x, C
21500 if (CC == ISD::SETUGT && Other->getOpcode() == ISD::ADD &&
21501 CondRHSConst->getAPIntValue() ==
21502 (-OpRHSConst->getAPIntValue() - 1))
21503 return DAG.getNode(
21504 X86ISD::SUBUS, DL, VT, OpLHS,
21505 DAG.getConstant(-OpRHSConst->getAPIntValue(), VT));
21507 // Another special case: If C was a sign bit, the sub has been
21508 // canonicalized into a xor.
21509 // FIXME: Would it be better to use computeKnownBits to determine
21510 // whether it's safe to decanonicalize the xor?
21511 // x s< 0 ? x^C : 0 --> subus x, C
21512 if (CC == ISD::SETLT && Other->getOpcode() == ISD::XOR &&
21513 ISD::isBuildVectorAllZeros(CondRHS.getNode()) &&
21514 OpRHSConst->getAPIntValue().isSignBit())
21515 // Note that we have to rebuild the RHS constant here to ensure we
21516 // don't rely on particular values of undef lanes.
21517 return DAG.getNode(
21518 X86ISD::SUBUS, DL, VT, OpLHS,
21519 DAG.getConstant(OpRHSConst->getAPIntValue(), VT));
21524 // Try to match a min/max vector operation.
21525 if (N->getOpcode() == ISD::VSELECT && Cond.getOpcode() == ISD::SETCC) {
21526 std::pair<unsigned, bool> ret = matchIntegerMINMAX(Cond, VT, LHS, RHS, DAG, Subtarget);
21527 unsigned Opc = ret.first;
21528 bool NeedSplit = ret.second;
21530 if (Opc && NeedSplit) {
21531 unsigned NumElems = VT.getVectorNumElements();
21532 // Extract the LHS vectors
21533 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, DL);
21534 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, DL);
21536 // Extract the RHS vectors
21537 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, DL);
21538 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, DL);
21540 // Create min/max for each subvector
21541 LHS = DAG.getNode(Opc, DL, LHS1.getValueType(), LHS1, RHS1);
21542 RHS = DAG.getNode(Opc, DL, LHS2.getValueType(), LHS2, RHS2);
21544 // Merge the result
21545 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, LHS, RHS);
21547 return DAG.getNode(Opc, DL, VT, LHS, RHS);
21550 // Simplify vector selection if the selector will be produced by CMPP*/PCMP*.
21551 if (N->getOpcode() == ISD::VSELECT && Cond.getOpcode() == ISD::SETCC &&
21552 // Check if SETCC has already been promoted
21553 TLI.getSetCCResultType(*DAG.getContext(), VT) == CondVT &&
21554 // Check that condition value type matches vselect operand type
21557 assert(Cond.getValueType().isVector() &&
21558 "vector select expects a vector selector!");
21560 bool TValIsAllOnes = ISD::isBuildVectorAllOnes(LHS.getNode());
21561 bool FValIsAllZeros = ISD::isBuildVectorAllZeros(RHS.getNode());
21563 if (!TValIsAllOnes && !FValIsAllZeros) {
21564 // Try invert the condition if true value is not all 1s and false value
21566 bool TValIsAllZeros = ISD::isBuildVectorAllZeros(LHS.getNode());
21567 bool FValIsAllOnes = ISD::isBuildVectorAllOnes(RHS.getNode());
21569 if (TValIsAllZeros || FValIsAllOnes) {
21570 SDValue CC = Cond.getOperand(2);
21571 ISD::CondCode NewCC =
21572 ISD::getSetCCInverse(cast<CondCodeSDNode>(CC)->get(),
21573 Cond.getOperand(0).getValueType().isInteger());
21574 Cond = DAG.getSetCC(DL, CondVT, Cond.getOperand(0), Cond.getOperand(1), NewCC);
21575 std::swap(LHS, RHS);
21576 TValIsAllOnes = FValIsAllOnes;
21577 FValIsAllZeros = TValIsAllZeros;
21581 if (TValIsAllOnes || FValIsAllZeros) {
21584 if (TValIsAllOnes && FValIsAllZeros)
21586 else if (TValIsAllOnes)
21587 Ret = DAG.getNode(ISD::OR, DL, CondVT, Cond,
21588 DAG.getNode(ISD::BITCAST, DL, CondVT, RHS));
21589 else if (FValIsAllZeros)
21590 Ret = DAG.getNode(ISD::AND, DL, CondVT, Cond,
21591 DAG.getNode(ISD::BITCAST, DL, CondVT, LHS));
21593 return DAG.getNode(ISD::BITCAST, DL, VT, Ret);
21597 // Try to fold this VSELECT into a MOVSS/MOVSD
21598 if (N->getOpcode() == ISD::VSELECT &&
21599 Cond.getOpcode() == ISD::BUILD_VECTOR && !DCI.isBeforeLegalize()) {
21600 if (VT == MVT::v4i32 || VT == MVT::v4f32 ||
21601 (Subtarget->hasSSE2() && (VT == MVT::v2i64 || VT == MVT::v2f64))) {
21602 bool CanFold = false;
21603 unsigned NumElems = Cond.getNumOperands();
21607 if (isZero(Cond.getOperand(0))) {
21610 // fold (vselect <0,-1,-1,-1>, A, B) -> (movss A, B)
21611 // fold (vselect <0,-1> -> (movsd A, B)
21612 for (unsigned i = 1, e = NumElems; i != e && CanFold; ++i)
21613 CanFold = isAllOnes(Cond.getOperand(i));
21614 } else if (isAllOnes(Cond.getOperand(0))) {
21618 // fold (vselect <-1,0,0,0>, A, B) -> (movss B, A)
21619 // fold (vselect <-1,0> -> (movsd B, A)
21620 for (unsigned i = 1, e = NumElems; i != e && CanFold; ++i)
21621 CanFold = isZero(Cond.getOperand(i));
21625 if (VT == MVT::v4i32 || VT == MVT::v4f32)
21626 return getTargetShuffleNode(X86ISD::MOVSS, DL, VT, A, B, DAG);
21627 return getTargetShuffleNode(X86ISD::MOVSD, DL, VT, A, B, DAG);
21630 if (Subtarget->hasSSE2() && (VT == MVT::v4i32 || VT == MVT::v4f32)) {
21631 // fold (v4i32: vselect <0,0,-1,-1>, A, B) ->
21632 // (v4i32 (bitcast (movsd (v2i64 (bitcast A)),
21633 // (v2i64 (bitcast B)))))
21635 // fold (v4f32: vselect <0,0,-1,-1>, A, B) ->
21636 // (v4f32 (bitcast (movsd (v2f64 (bitcast A)),
21637 // (v2f64 (bitcast B)))))
21639 // fold (v4i32: vselect <-1,-1,0,0>, A, B) ->
21640 // (v4i32 (bitcast (movsd (v2i64 (bitcast B)),
21641 // (v2i64 (bitcast A)))))
21643 // fold (v4f32: vselect <-1,-1,0,0>, A, B) ->
21644 // (v4f32 (bitcast (movsd (v2f64 (bitcast B)),
21645 // (v2f64 (bitcast A)))))
21647 CanFold = (isZero(Cond.getOperand(0)) &&
21648 isZero(Cond.getOperand(1)) &&
21649 isAllOnes(Cond.getOperand(2)) &&
21650 isAllOnes(Cond.getOperand(3)));
21652 if (!CanFold && isAllOnes(Cond.getOperand(0)) &&
21653 isAllOnes(Cond.getOperand(1)) &&
21654 isZero(Cond.getOperand(2)) &&
21655 isZero(Cond.getOperand(3))) {
21657 std::swap(LHS, RHS);
21661 EVT NVT = (VT == MVT::v4i32) ? MVT::v2i64 : MVT::v2f64;
21662 SDValue NewA = DAG.getNode(ISD::BITCAST, DL, NVT, LHS);
21663 SDValue NewB = DAG.getNode(ISD::BITCAST, DL, NVT, RHS);
21664 SDValue Select = getTargetShuffleNode(X86ISD::MOVSD, DL, NVT, NewA,
21666 return DAG.getNode(ISD::BITCAST, DL, VT, Select);
21672 // If we know that this node is legal then we know that it is going to be
21673 // matched by one of the SSE/AVX BLEND instructions. These instructions only
21674 // depend on the highest bit in each word. Try to use SimplifyDemandedBits
21675 // to simplify previous instructions.
21676 if (N->getOpcode() == ISD::VSELECT && DCI.isBeforeLegalizeOps() &&
21677 !DCI.isBeforeLegalize() &&
21678 // We explicitly check against v8i16 and v16i16 because, although
21679 // they're marked as Custom, they might only be legal when Cond is a
21680 // build_vector of constants. This will be taken care in a later
21682 (TLI.isOperationLegalOrCustom(ISD::VSELECT, VT) && VT != MVT::v16i16 &&
21683 VT != MVT::v8i16)) {
21684 unsigned BitWidth = Cond.getValueType().getScalarType().getSizeInBits();
21686 // Don't optimize vector selects that map to mask-registers.
21690 // Check all uses of that condition operand to check whether it will be
21691 // consumed by non-BLEND instructions, which may depend on all bits are set
21693 for (SDNode::use_iterator I = Cond->use_begin(),
21694 E = Cond->use_end(); I != E; ++I)
21695 if (I->getOpcode() != ISD::VSELECT)
21696 // TODO: Add other opcodes eventually lowered into BLEND.
21699 assert(BitWidth >= 8 && BitWidth <= 64 && "Invalid mask size");
21700 APInt DemandedMask = APInt::getHighBitsSet(BitWidth, 1);
21702 APInt KnownZero, KnownOne;
21703 TargetLowering::TargetLoweringOpt TLO(DAG, DCI.isBeforeLegalize(),
21704 DCI.isBeforeLegalizeOps());
21705 if (TLO.ShrinkDemandedConstant(Cond, DemandedMask) ||
21706 TLI.SimplifyDemandedBits(Cond, DemandedMask, KnownZero, KnownOne, TLO))
21707 DCI.CommitTargetLoweringOpt(TLO);
21710 // We should generate an X86ISD::BLENDI from a vselect if its argument
21711 // is a sign_extend_inreg of an any_extend of a BUILD_VECTOR of
21712 // constants. This specific pattern gets generated when we split a
21713 // selector for a 512 bit vector in a machine without AVX512 (but with
21714 // 256-bit vectors), during legalization:
21716 // (vselect (sign_extend (any_extend (BUILD_VECTOR)) i1) LHS RHS)
21718 // Iff we find this pattern and the build_vectors are built from
21719 // constants, we translate the vselect into a shuffle_vector that we
21720 // know will be matched by LowerVECTOR_SHUFFLEtoBlend.
21721 if (N->getOpcode() == ISD::VSELECT && !DCI.isBeforeLegalize()) {
21722 SDValue Shuffle = TransformVSELECTtoBlendVECTOR_SHUFFLE(N, DAG, Subtarget);
21723 if (Shuffle.getNode())
21730 // Check whether a boolean test is testing a boolean value generated by
21731 // X86ISD::SETCC. If so, return the operand of that SETCC and proper condition
21734 // Simplify the following patterns:
21735 // (Op (CMP (SETCC Cond EFLAGS) 1) EQ) or
21736 // (Op (CMP (SETCC Cond EFLAGS) 0) NEQ)
21737 // to (Op EFLAGS Cond)
21739 // (Op (CMP (SETCC Cond EFLAGS) 0) EQ) or
21740 // (Op (CMP (SETCC Cond EFLAGS) 1) NEQ)
21741 // to (Op EFLAGS !Cond)
21743 // where Op could be BRCOND or CMOV.
21745 static SDValue checkBoolTestSetCCCombine(SDValue Cmp, X86::CondCode &CC) {
21746 // Quit if not CMP and SUB with its value result used.
21747 if (Cmp.getOpcode() != X86ISD::CMP &&
21748 (Cmp.getOpcode() != X86ISD::SUB || Cmp.getNode()->hasAnyUseOfValue(0)))
21751 // Quit if not used as a boolean value.
21752 if (CC != X86::COND_E && CC != X86::COND_NE)
21755 // Check CMP operands. One of them should be 0 or 1 and the other should be
21756 // an SetCC or extended from it.
21757 SDValue Op1 = Cmp.getOperand(0);
21758 SDValue Op2 = Cmp.getOperand(1);
21761 const ConstantSDNode* C = nullptr;
21762 bool needOppositeCond = (CC == X86::COND_E);
21763 bool checkAgainstTrue = false; // Is it a comparison against 1?
21765 if ((C = dyn_cast<ConstantSDNode>(Op1)))
21767 else if ((C = dyn_cast<ConstantSDNode>(Op2)))
21769 else // Quit if all operands are not constants.
21772 if (C->getZExtValue() == 1) {
21773 needOppositeCond = !needOppositeCond;
21774 checkAgainstTrue = true;
21775 } else if (C->getZExtValue() != 0)
21776 // Quit if the constant is neither 0 or 1.
21779 bool truncatedToBoolWithAnd = false;
21780 // Skip (zext $x), (trunc $x), or (and $x, 1) node.
21781 while (SetCC.getOpcode() == ISD::ZERO_EXTEND ||
21782 SetCC.getOpcode() == ISD::TRUNCATE ||
21783 SetCC.getOpcode() == ISD::AND) {
21784 if (SetCC.getOpcode() == ISD::AND) {
21786 ConstantSDNode *CS;
21787 if ((CS = dyn_cast<ConstantSDNode>(SetCC.getOperand(0))) &&
21788 CS->getZExtValue() == 1)
21790 if ((CS = dyn_cast<ConstantSDNode>(SetCC.getOperand(1))) &&
21791 CS->getZExtValue() == 1)
21795 SetCC = SetCC.getOperand(OpIdx);
21796 truncatedToBoolWithAnd = true;
21798 SetCC = SetCC.getOperand(0);
21801 switch (SetCC.getOpcode()) {
21802 case X86ISD::SETCC_CARRY:
21803 // Since SETCC_CARRY gives output based on R = CF ? ~0 : 0, it's unsafe to
21804 // simplify it if the result of SETCC_CARRY is not canonicalized to 0 or 1,
21805 // i.e. it's a comparison against true but the result of SETCC_CARRY is not
21806 // truncated to i1 using 'and'.
21807 if (checkAgainstTrue && !truncatedToBoolWithAnd)
21809 assert(X86::CondCode(SetCC.getConstantOperandVal(0)) == X86::COND_B &&
21810 "Invalid use of SETCC_CARRY!");
21812 case X86ISD::SETCC:
21813 // Set the condition code or opposite one if necessary.
21814 CC = X86::CondCode(SetCC.getConstantOperandVal(0));
21815 if (needOppositeCond)
21816 CC = X86::GetOppositeBranchCondition(CC);
21817 return SetCC.getOperand(1);
21818 case X86ISD::CMOV: {
21819 // Check whether false/true value has canonical one, i.e. 0 or 1.
21820 ConstantSDNode *FVal = dyn_cast<ConstantSDNode>(SetCC.getOperand(0));
21821 ConstantSDNode *TVal = dyn_cast<ConstantSDNode>(SetCC.getOperand(1));
21822 // Quit if true value is not a constant.
21825 // Quit if false value is not a constant.
21827 SDValue Op = SetCC.getOperand(0);
21828 // Skip 'zext' or 'trunc' node.
21829 if (Op.getOpcode() == ISD::ZERO_EXTEND ||
21830 Op.getOpcode() == ISD::TRUNCATE)
21831 Op = Op.getOperand(0);
21832 // A special case for rdrand/rdseed, where 0 is set if false cond is
21834 if ((Op.getOpcode() != X86ISD::RDRAND &&
21835 Op.getOpcode() != X86ISD::RDSEED) || Op.getResNo() != 0)
21838 // Quit if false value is not the constant 0 or 1.
21839 bool FValIsFalse = true;
21840 if (FVal && FVal->getZExtValue() != 0) {
21841 if (FVal->getZExtValue() != 1)
21843 // If FVal is 1, opposite cond is needed.
21844 needOppositeCond = !needOppositeCond;
21845 FValIsFalse = false;
21847 // Quit if TVal is not the constant opposite of FVal.
21848 if (FValIsFalse && TVal->getZExtValue() != 1)
21850 if (!FValIsFalse && TVal->getZExtValue() != 0)
21852 CC = X86::CondCode(SetCC.getConstantOperandVal(2));
21853 if (needOppositeCond)
21854 CC = X86::GetOppositeBranchCondition(CC);
21855 return SetCC.getOperand(3);
21862 /// Optimize X86ISD::CMOV [LHS, RHS, CONDCODE (e.g. X86::COND_NE), CONDVAL]
21863 static SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG,
21864 TargetLowering::DAGCombinerInfo &DCI,
21865 const X86Subtarget *Subtarget) {
21868 // If the flag operand isn't dead, don't touch this CMOV.
21869 if (N->getNumValues() == 2 && !SDValue(N, 1).use_empty())
21872 SDValue FalseOp = N->getOperand(0);
21873 SDValue TrueOp = N->getOperand(1);
21874 X86::CondCode CC = (X86::CondCode)N->getConstantOperandVal(2);
21875 SDValue Cond = N->getOperand(3);
21877 if (CC == X86::COND_E || CC == X86::COND_NE) {
21878 switch (Cond.getOpcode()) {
21882 // If operand of BSR / BSF are proven never zero, then ZF cannot be set.
21883 if (DAG.isKnownNeverZero(Cond.getOperand(0)))
21884 return (CC == X86::COND_E) ? FalseOp : TrueOp;
21890 Flags = checkBoolTestSetCCCombine(Cond, CC);
21891 if (Flags.getNode() &&
21892 // Extra check as FCMOV only supports a subset of X86 cond.
21893 (FalseOp.getValueType() != MVT::f80 || hasFPCMov(CC))) {
21894 SDValue Ops[] = { FalseOp, TrueOp,
21895 DAG.getConstant(CC, MVT::i8), Flags };
21896 return DAG.getNode(X86ISD::CMOV, DL, N->getVTList(), Ops);
21899 // If this is a select between two integer constants, try to do some
21900 // optimizations. Note that the operands are ordered the opposite of SELECT
21902 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(TrueOp)) {
21903 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(FalseOp)) {
21904 // Canonicalize the TrueC/FalseC values so that TrueC (the true value) is
21905 // larger than FalseC (the false value).
21906 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue())) {
21907 CC = X86::GetOppositeBranchCondition(CC);
21908 std::swap(TrueC, FalseC);
21909 std::swap(TrueOp, FalseOp);
21912 // Optimize C ? 8 : 0 -> zext(setcc(C)) << 3. Likewise for any pow2/0.
21913 // This is efficient for any integer data type (including i8/i16) and
21915 if (FalseC->getAPIntValue() == 0 && TrueC->getAPIntValue().isPowerOf2()) {
21916 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
21917 DAG.getConstant(CC, MVT::i8), Cond);
21919 // Zero extend the condition if needed.
21920 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, TrueC->getValueType(0), Cond);
21922 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
21923 Cond = DAG.getNode(ISD::SHL, DL, Cond.getValueType(), Cond,
21924 DAG.getConstant(ShAmt, MVT::i8));
21925 if (N->getNumValues() == 2) // Dead flag value?
21926 return DCI.CombineTo(N, Cond, SDValue());
21930 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst. This is efficient
21931 // for any integer data type, including i8/i16.
21932 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
21933 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
21934 DAG.getConstant(CC, MVT::i8), Cond);
21936 // Zero extend the condition if needed.
21937 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
21938 FalseC->getValueType(0), Cond);
21939 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
21940 SDValue(FalseC, 0));
21942 if (N->getNumValues() == 2) // Dead flag value?
21943 return DCI.CombineTo(N, Cond, SDValue());
21947 // Optimize cases that will turn into an LEA instruction. This requires
21948 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
21949 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
21950 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
21951 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
21953 bool isFastMultiplier = false;
21955 switch ((unsigned char)Diff) {
21957 case 1: // result = add base, cond
21958 case 2: // result = lea base( , cond*2)
21959 case 3: // result = lea base(cond, cond*2)
21960 case 4: // result = lea base( , cond*4)
21961 case 5: // result = lea base(cond, cond*4)
21962 case 8: // result = lea base( , cond*8)
21963 case 9: // result = lea base(cond, cond*8)
21964 isFastMultiplier = true;
21969 if (isFastMultiplier) {
21970 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
21971 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
21972 DAG.getConstant(CC, MVT::i8), Cond);
21973 // Zero extend the condition if needed.
21974 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
21976 // Scale the condition by the difference.
21978 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
21979 DAG.getConstant(Diff, Cond.getValueType()));
21981 // Add the base if non-zero.
21982 if (FalseC->getAPIntValue() != 0)
21983 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
21984 SDValue(FalseC, 0));
21985 if (N->getNumValues() == 2) // Dead flag value?
21986 return DCI.CombineTo(N, Cond, SDValue());
21993 // Handle these cases:
21994 // (select (x != c), e, c) -> select (x != c), e, x),
21995 // (select (x == c), c, e) -> select (x == c), x, e)
21996 // where the c is an integer constant, and the "select" is the combination
21997 // of CMOV and CMP.
21999 // The rationale for this change is that the conditional-move from a constant
22000 // needs two instructions, however, conditional-move from a register needs
22001 // only one instruction.
22003 // CAVEAT: By replacing a constant with a symbolic value, it may obscure
22004 // some instruction-combining opportunities. This opt needs to be
22005 // postponed as late as possible.
22007 if (!DCI.isBeforeLegalize() && !DCI.isBeforeLegalizeOps()) {
22008 // the DCI.xxxx conditions are provided to postpone the optimization as
22009 // late as possible.
22011 ConstantSDNode *CmpAgainst = nullptr;
22012 if ((Cond.getOpcode() == X86ISD::CMP || Cond.getOpcode() == X86ISD::SUB) &&
22013 (CmpAgainst = dyn_cast<ConstantSDNode>(Cond.getOperand(1))) &&
22014 !isa<ConstantSDNode>(Cond.getOperand(0))) {
22016 if (CC == X86::COND_NE &&
22017 CmpAgainst == dyn_cast<ConstantSDNode>(FalseOp)) {
22018 CC = X86::GetOppositeBranchCondition(CC);
22019 std::swap(TrueOp, FalseOp);
22022 if (CC == X86::COND_E &&
22023 CmpAgainst == dyn_cast<ConstantSDNode>(TrueOp)) {
22024 SDValue Ops[] = { FalseOp, Cond.getOperand(0),
22025 DAG.getConstant(CC, MVT::i8), Cond };
22026 return DAG.getNode(X86ISD::CMOV, DL, N->getVTList (), Ops);
22034 static SDValue PerformINTRINSIC_WO_CHAINCombine(SDNode *N, SelectionDAG &DAG,
22035 const X86Subtarget *Subtarget) {
22036 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(0))->getZExtValue();
22038 default: return SDValue();
22039 // SSE/AVX/AVX2 blend intrinsics.
22040 case Intrinsic::x86_avx2_pblendvb:
22041 case Intrinsic::x86_avx2_pblendw:
22042 case Intrinsic::x86_avx2_pblendd_128:
22043 case Intrinsic::x86_avx2_pblendd_256:
22044 // Don't try to simplify this intrinsic if we don't have AVX2.
22045 if (!Subtarget->hasAVX2())
22048 case Intrinsic::x86_avx_blend_pd_256:
22049 case Intrinsic::x86_avx_blend_ps_256:
22050 case Intrinsic::x86_avx_blendv_pd_256:
22051 case Intrinsic::x86_avx_blendv_ps_256:
22052 // Don't try to simplify this intrinsic if we don't have AVX.
22053 if (!Subtarget->hasAVX())
22056 case Intrinsic::x86_sse41_pblendw:
22057 case Intrinsic::x86_sse41_blendpd:
22058 case Intrinsic::x86_sse41_blendps:
22059 case Intrinsic::x86_sse41_blendvps:
22060 case Intrinsic::x86_sse41_blendvpd:
22061 case Intrinsic::x86_sse41_pblendvb: {
22062 SDValue Op0 = N->getOperand(1);
22063 SDValue Op1 = N->getOperand(2);
22064 SDValue Mask = N->getOperand(3);
22066 // Don't try to simplify this intrinsic if we don't have SSE4.1.
22067 if (!Subtarget->hasSSE41())
22070 // fold (blend A, A, Mask) -> A
22073 // fold (blend A, B, allZeros) -> A
22074 if (ISD::isBuildVectorAllZeros(Mask.getNode()))
22076 // fold (blend A, B, allOnes) -> B
22077 if (ISD::isBuildVectorAllOnes(Mask.getNode()))
22080 // Simplify the case where the mask is a constant i32 value.
22081 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Mask)) {
22082 if (C->isNullValue())
22084 if (C->isAllOnesValue())
22091 // Packed SSE2/AVX2 arithmetic shift immediate intrinsics.
22092 case Intrinsic::x86_sse2_psrai_w:
22093 case Intrinsic::x86_sse2_psrai_d:
22094 case Intrinsic::x86_avx2_psrai_w:
22095 case Intrinsic::x86_avx2_psrai_d:
22096 case Intrinsic::x86_sse2_psra_w:
22097 case Intrinsic::x86_sse2_psra_d:
22098 case Intrinsic::x86_avx2_psra_w:
22099 case Intrinsic::x86_avx2_psra_d: {
22100 SDValue Op0 = N->getOperand(1);
22101 SDValue Op1 = N->getOperand(2);
22102 EVT VT = Op0.getValueType();
22103 assert(VT.isVector() && "Expected a vector type!");
22105 if (isa<BuildVectorSDNode>(Op1))
22106 Op1 = Op1.getOperand(0);
22108 if (!isa<ConstantSDNode>(Op1))
22111 EVT SVT = VT.getVectorElementType();
22112 unsigned SVTBits = SVT.getSizeInBits();
22114 ConstantSDNode *CND = cast<ConstantSDNode>(Op1);
22115 const APInt &C = APInt(SVTBits, CND->getAPIntValue().getZExtValue());
22116 uint64_t ShAmt = C.getZExtValue();
22118 // Don't try to convert this shift into a ISD::SRA if the shift
22119 // count is bigger than or equal to the element size.
22120 if (ShAmt >= SVTBits)
22123 // Trivial case: if the shift count is zero, then fold this
22124 // into the first operand.
22128 // Replace this packed shift intrinsic with a target independent
22130 SDValue Splat = DAG.getConstant(C, VT);
22131 return DAG.getNode(ISD::SRA, SDLoc(N), VT, Op0, Splat);
22136 /// PerformMulCombine - Optimize a single multiply with constant into two
22137 /// in order to implement it with two cheaper instructions, e.g.
22138 /// LEA + SHL, LEA + LEA.
22139 static SDValue PerformMulCombine(SDNode *N, SelectionDAG &DAG,
22140 TargetLowering::DAGCombinerInfo &DCI) {
22141 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer())
22144 EVT VT = N->getValueType(0);
22145 if (VT != MVT::i64)
22148 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
22151 uint64_t MulAmt = C->getZExtValue();
22152 if (isPowerOf2_64(MulAmt) || MulAmt == 3 || MulAmt == 5 || MulAmt == 9)
22155 uint64_t MulAmt1 = 0;
22156 uint64_t MulAmt2 = 0;
22157 if ((MulAmt % 9) == 0) {
22159 MulAmt2 = MulAmt / 9;
22160 } else if ((MulAmt % 5) == 0) {
22162 MulAmt2 = MulAmt / 5;
22163 } else if ((MulAmt % 3) == 0) {
22165 MulAmt2 = MulAmt / 3;
22168 (isPowerOf2_64(MulAmt2) || MulAmt2 == 3 || MulAmt2 == 5 || MulAmt2 == 9)){
22171 if (isPowerOf2_64(MulAmt2) &&
22172 !(N->hasOneUse() && N->use_begin()->getOpcode() == ISD::ADD))
22173 // If second multiplifer is pow2, issue it first. We want the multiply by
22174 // 3, 5, or 9 to be folded into the addressing mode unless the lone use
22176 std::swap(MulAmt1, MulAmt2);
22179 if (isPowerOf2_64(MulAmt1))
22180 NewMul = DAG.getNode(ISD::SHL, DL, VT, N->getOperand(0),
22181 DAG.getConstant(Log2_64(MulAmt1), MVT::i8));
22183 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, N->getOperand(0),
22184 DAG.getConstant(MulAmt1, VT));
22186 if (isPowerOf2_64(MulAmt2))
22187 NewMul = DAG.getNode(ISD::SHL, DL, VT, NewMul,
22188 DAG.getConstant(Log2_64(MulAmt2), MVT::i8));
22190 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, NewMul,
22191 DAG.getConstant(MulAmt2, VT));
22193 // Do not add new nodes to DAG combiner worklist.
22194 DCI.CombineTo(N, NewMul, false);
22199 static SDValue PerformSHLCombine(SDNode *N, SelectionDAG &DAG) {
22200 SDValue N0 = N->getOperand(0);
22201 SDValue N1 = N->getOperand(1);
22202 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
22203 EVT VT = N0.getValueType();
22205 // fold (shl (and (setcc_c), c1), c2) -> (and setcc_c, (c1 << c2))
22206 // since the result of setcc_c is all zero's or all ones.
22207 if (VT.isInteger() && !VT.isVector() &&
22208 N1C && N0.getOpcode() == ISD::AND &&
22209 N0.getOperand(1).getOpcode() == ISD::Constant) {
22210 SDValue N00 = N0.getOperand(0);
22211 if (N00.getOpcode() == X86ISD::SETCC_CARRY ||
22212 ((N00.getOpcode() == ISD::ANY_EXTEND ||
22213 N00.getOpcode() == ISD::ZERO_EXTEND) &&
22214 N00.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY)) {
22215 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
22216 APInt ShAmt = N1C->getAPIntValue();
22217 Mask = Mask.shl(ShAmt);
22219 return DAG.getNode(ISD::AND, SDLoc(N), VT,
22220 N00, DAG.getConstant(Mask, VT));
22224 // Hardware support for vector shifts is sparse which makes us scalarize the
22225 // vector operations in many cases. Also, on sandybridge ADD is faster than
22227 // (shl V, 1) -> add V,V
22228 if (auto *N1BV = dyn_cast<BuildVectorSDNode>(N1))
22229 if (auto *N1SplatC = N1BV->getConstantSplatNode()) {
22230 assert(N0.getValueType().isVector() && "Invalid vector shift type");
22231 // We shift all of the values by one. In many cases we do not have
22232 // hardware support for this operation. This is better expressed as an ADD
22234 if (N1SplatC->getZExtValue() == 1)
22235 return DAG.getNode(ISD::ADD, SDLoc(N), VT, N0, N0);
22241 /// \brief Returns a vector of 0s if the node in input is a vector logical
22242 /// shift by a constant amount which is known to be bigger than or equal
22243 /// to the vector element size in bits.
22244 static SDValue performShiftToAllZeros(SDNode *N, SelectionDAG &DAG,
22245 const X86Subtarget *Subtarget) {
22246 EVT VT = N->getValueType(0);
22248 if (VT != MVT::v2i64 && VT != MVT::v4i32 && VT != MVT::v8i16 &&
22249 (!Subtarget->hasInt256() ||
22250 (VT != MVT::v4i64 && VT != MVT::v8i32 && VT != MVT::v16i16)))
22253 SDValue Amt = N->getOperand(1);
22255 if (auto *AmtBV = dyn_cast<BuildVectorSDNode>(Amt))
22256 if (auto *AmtSplat = AmtBV->getConstantSplatNode()) {
22257 APInt ShiftAmt = AmtSplat->getAPIntValue();
22258 unsigned MaxAmount = VT.getVectorElementType().getSizeInBits();
22260 // SSE2/AVX2 logical shifts always return a vector of 0s
22261 // if the shift amount is bigger than or equal to
22262 // the element size. The constant shift amount will be
22263 // encoded as a 8-bit immediate.
22264 if (ShiftAmt.trunc(8).uge(MaxAmount))
22265 return getZeroVector(VT, Subtarget, DAG, DL);
22271 /// PerformShiftCombine - Combine shifts.
22272 static SDValue PerformShiftCombine(SDNode* N, SelectionDAG &DAG,
22273 TargetLowering::DAGCombinerInfo &DCI,
22274 const X86Subtarget *Subtarget) {
22275 if (N->getOpcode() == ISD::SHL) {
22276 SDValue V = PerformSHLCombine(N, DAG);
22277 if (V.getNode()) return V;
22280 if (N->getOpcode() != ISD::SRA) {
22281 // Try to fold this logical shift into a zero vector.
22282 SDValue V = performShiftToAllZeros(N, DAG, Subtarget);
22283 if (V.getNode()) return V;
22289 // CMPEQCombine - Recognize the distinctive (AND (setcc ...) (setcc ..))
22290 // where both setccs reference the same FP CMP, and rewrite for CMPEQSS
22291 // and friends. Likewise for OR -> CMPNEQSS.
22292 static SDValue CMPEQCombine(SDNode *N, SelectionDAG &DAG,
22293 TargetLowering::DAGCombinerInfo &DCI,
22294 const X86Subtarget *Subtarget) {
22297 // SSE1 supports CMP{eq|ne}SS, and SSE2 added CMP{eq|ne}SD, but
22298 // we're requiring SSE2 for both.
22299 if (Subtarget->hasSSE2() && isAndOrOfSetCCs(SDValue(N, 0U), opcode)) {
22300 SDValue N0 = N->getOperand(0);
22301 SDValue N1 = N->getOperand(1);
22302 SDValue CMP0 = N0->getOperand(1);
22303 SDValue CMP1 = N1->getOperand(1);
22306 // The SETCCs should both refer to the same CMP.
22307 if (CMP0.getOpcode() != X86ISD::CMP || CMP0 != CMP1)
22310 SDValue CMP00 = CMP0->getOperand(0);
22311 SDValue CMP01 = CMP0->getOperand(1);
22312 EVT VT = CMP00.getValueType();
22314 if (VT == MVT::f32 || VT == MVT::f64) {
22315 bool ExpectingFlags = false;
22316 // Check for any users that want flags:
22317 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end();
22318 !ExpectingFlags && UI != UE; ++UI)
22319 switch (UI->getOpcode()) {
22324 ExpectingFlags = true;
22326 case ISD::CopyToReg:
22327 case ISD::SIGN_EXTEND:
22328 case ISD::ZERO_EXTEND:
22329 case ISD::ANY_EXTEND:
22333 if (!ExpectingFlags) {
22334 enum X86::CondCode cc0 = (enum X86::CondCode)N0.getConstantOperandVal(0);
22335 enum X86::CondCode cc1 = (enum X86::CondCode)N1.getConstantOperandVal(0);
22337 if (cc1 == X86::COND_E || cc1 == X86::COND_NE) {
22338 X86::CondCode tmp = cc0;
22343 if ((cc0 == X86::COND_E && cc1 == X86::COND_NP) ||
22344 (cc0 == X86::COND_NE && cc1 == X86::COND_P)) {
22345 // FIXME: need symbolic constants for these magic numbers.
22346 // See X86ATTInstPrinter.cpp:printSSECC().
22347 unsigned x86cc = (cc0 == X86::COND_E) ? 0 : 4;
22348 if (Subtarget->hasAVX512()) {
22349 SDValue FSetCC = DAG.getNode(X86ISD::FSETCC, DL, MVT::i1, CMP00,
22350 CMP01, DAG.getConstant(x86cc, MVT::i8));
22351 if (N->getValueType(0) != MVT::i1)
22352 return DAG.getNode(ISD::ZERO_EXTEND, DL, N->getValueType(0),
22356 SDValue OnesOrZeroesF = DAG.getNode(X86ISD::FSETCC, DL,
22357 CMP00.getValueType(), CMP00, CMP01,
22358 DAG.getConstant(x86cc, MVT::i8));
22360 bool is64BitFP = (CMP00.getValueType() == MVT::f64);
22361 MVT IntVT = is64BitFP ? MVT::i64 : MVT::i32;
22363 if (is64BitFP && !Subtarget->is64Bit()) {
22364 // On a 32-bit target, we cannot bitcast the 64-bit float to a
22365 // 64-bit integer, since that's not a legal type. Since
22366 // OnesOrZeroesF is all ones of all zeroes, we don't need all the
22367 // bits, but can do this little dance to extract the lowest 32 bits
22368 // and work with those going forward.
22369 SDValue Vector64 = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, MVT::v2f64,
22371 SDValue Vector32 = DAG.getNode(ISD::BITCAST, DL, MVT::v4f32,
22373 OnesOrZeroesF = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32,
22374 Vector32, DAG.getIntPtrConstant(0));
22378 SDValue OnesOrZeroesI = DAG.getNode(ISD::BITCAST, DL, IntVT, OnesOrZeroesF);
22379 SDValue ANDed = DAG.getNode(ISD::AND, DL, IntVT, OnesOrZeroesI,
22380 DAG.getConstant(1, IntVT));
22381 SDValue OneBitOfTruth = DAG.getNode(ISD::TRUNCATE, DL, MVT::i8, ANDed);
22382 return OneBitOfTruth;
22390 /// CanFoldXORWithAllOnes - Test whether the XOR operand is a AllOnes vector
22391 /// so it can be folded inside ANDNP.
22392 static bool CanFoldXORWithAllOnes(const SDNode *N) {
22393 EVT VT = N->getValueType(0);
22395 // Match direct AllOnes for 128 and 256-bit vectors
22396 if (ISD::isBuildVectorAllOnes(N))
22399 // Look through a bit convert.
22400 if (N->getOpcode() == ISD::BITCAST)
22401 N = N->getOperand(0).getNode();
22403 // Sometimes the operand may come from a insert_subvector building a 256-bit
22405 if (VT.is256BitVector() &&
22406 N->getOpcode() == ISD::INSERT_SUBVECTOR) {
22407 SDValue V1 = N->getOperand(0);
22408 SDValue V2 = N->getOperand(1);
22410 if (V1.getOpcode() == ISD::INSERT_SUBVECTOR &&
22411 V1.getOperand(0).getOpcode() == ISD::UNDEF &&
22412 ISD::isBuildVectorAllOnes(V1.getOperand(1).getNode()) &&
22413 ISD::isBuildVectorAllOnes(V2.getNode()))
22420 // On AVX/AVX2 the type v8i1 is legalized to v8i16, which is an XMM sized
22421 // register. In most cases we actually compare or select YMM-sized registers
22422 // and mixing the two types creates horrible code. This method optimizes
22423 // some of the transition sequences.
22424 static SDValue WidenMaskArithmetic(SDNode *N, SelectionDAG &DAG,
22425 TargetLowering::DAGCombinerInfo &DCI,
22426 const X86Subtarget *Subtarget) {
22427 EVT VT = N->getValueType(0);
22428 if (!VT.is256BitVector())
22431 assert((N->getOpcode() == ISD::ANY_EXTEND ||
22432 N->getOpcode() == ISD::ZERO_EXTEND ||
22433 N->getOpcode() == ISD::SIGN_EXTEND) && "Invalid Node");
22435 SDValue Narrow = N->getOperand(0);
22436 EVT NarrowVT = Narrow->getValueType(0);
22437 if (!NarrowVT.is128BitVector())
22440 if (Narrow->getOpcode() != ISD::XOR &&
22441 Narrow->getOpcode() != ISD::AND &&
22442 Narrow->getOpcode() != ISD::OR)
22445 SDValue N0 = Narrow->getOperand(0);
22446 SDValue N1 = Narrow->getOperand(1);
22449 // The Left side has to be a trunc.
22450 if (N0.getOpcode() != ISD::TRUNCATE)
22453 // The type of the truncated inputs.
22454 EVT WideVT = N0->getOperand(0)->getValueType(0);
22458 // The right side has to be a 'trunc' or a constant vector.
22459 bool RHSTrunc = N1.getOpcode() == ISD::TRUNCATE;
22460 ConstantSDNode *RHSConstSplat = nullptr;
22461 if (auto *RHSBV = dyn_cast<BuildVectorSDNode>(N1))
22462 RHSConstSplat = RHSBV->getConstantSplatNode();
22463 if (!RHSTrunc && !RHSConstSplat)
22466 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
22468 if (!TLI.isOperationLegalOrPromote(Narrow->getOpcode(), WideVT))
22471 // Set N0 and N1 to hold the inputs to the new wide operation.
22472 N0 = N0->getOperand(0);
22473 if (RHSConstSplat) {
22474 N1 = DAG.getNode(ISD::ZERO_EXTEND, DL, WideVT.getScalarType(),
22475 SDValue(RHSConstSplat, 0));
22476 SmallVector<SDValue, 8> C(WideVT.getVectorNumElements(), N1);
22477 N1 = DAG.getNode(ISD::BUILD_VECTOR, DL, WideVT, C);
22478 } else if (RHSTrunc) {
22479 N1 = N1->getOperand(0);
22482 // Generate the wide operation.
22483 SDValue Op = DAG.getNode(Narrow->getOpcode(), DL, WideVT, N0, N1);
22484 unsigned Opcode = N->getOpcode();
22486 case ISD::ANY_EXTEND:
22488 case ISD::ZERO_EXTEND: {
22489 unsigned InBits = NarrowVT.getScalarType().getSizeInBits();
22490 APInt Mask = APInt::getAllOnesValue(InBits);
22491 Mask = Mask.zext(VT.getScalarType().getSizeInBits());
22492 return DAG.getNode(ISD::AND, DL, VT,
22493 Op, DAG.getConstant(Mask, VT));
22495 case ISD::SIGN_EXTEND:
22496 return DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, VT,
22497 Op, DAG.getValueType(NarrowVT));
22499 llvm_unreachable("Unexpected opcode");
22503 static SDValue PerformAndCombine(SDNode *N, SelectionDAG &DAG,
22504 TargetLowering::DAGCombinerInfo &DCI,
22505 const X86Subtarget *Subtarget) {
22506 EVT VT = N->getValueType(0);
22507 if (DCI.isBeforeLegalizeOps())
22510 SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget);
22514 // Create BEXTR instructions
22515 // BEXTR is ((X >> imm) & (2**size-1))
22516 if (VT == MVT::i32 || VT == MVT::i64) {
22517 SDValue N0 = N->getOperand(0);
22518 SDValue N1 = N->getOperand(1);
22521 // Check for BEXTR.
22522 if ((Subtarget->hasBMI() || Subtarget->hasTBM()) &&
22523 (N0.getOpcode() == ISD::SRA || N0.getOpcode() == ISD::SRL)) {
22524 ConstantSDNode *MaskNode = dyn_cast<ConstantSDNode>(N1);
22525 ConstantSDNode *ShiftNode = dyn_cast<ConstantSDNode>(N0.getOperand(1));
22526 if (MaskNode && ShiftNode) {
22527 uint64_t Mask = MaskNode->getZExtValue();
22528 uint64_t Shift = ShiftNode->getZExtValue();
22529 if (isMask_64(Mask)) {
22530 uint64_t MaskSize = CountPopulation_64(Mask);
22531 if (Shift + MaskSize <= VT.getSizeInBits())
22532 return DAG.getNode(X86ISD::BEXTR, DL, VT, N0.getOperand(0),
22533 DAG.getConstant(Shift | (MaskSize << 8), VT));
22541 // Want to form ANDNP nodes:
22542 // 1) In the hopes of then easily combining them with OR and AND nodes
22543 // to form PBLEND/PSIGN.
22544 // 2) To match ANDN packed intrinsics
22545 if (VT != MVT::v2i64 && VT != MVT::v4i64)
22548 SDValue N0 = N->getOperand(0);
22549 SDValue N1 = N->getOperand(1);
22552 // Check LHS for vnot
22553 if (N0.getOpcode() == ISD::XOR &&
22554 //ISD::isBuildVectorAllOnes(N0.getOperand(1).getNode()))
22555 CanFoldXORWithAllOnes(N0.getOperand(1).getNode()))
22556 return DAG.getNode(X86ISD::ANDNP, DL, VT, N0.getOperand(0), N1);
22558 // Check RHS for vnot
22559 if (N1.getOpcode() == ISD::XOR &&
22560 //ISD::isBuildVectorAllOnes(N1.getOperand(1).getNode()))
22561 CanFoldXORWithAllOnes(N1.getOperand(1).getNode()))
22562 return DAG.getNode(X86ISD::ANDNP, DL, VT, N1.getOperand(0), N0);
22567 static SDValue PerformOrCombine(SDNode *N, SelectionDAG &DAG,
22568 TargetLowering::DAGCombinerInfo &DCI,
22569 const X86Subtarget *Subtarget) {
22570 if (DCI.isBeforeLegalizeOps())
22573 SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget);
22577 SDValue N0 = N->getOperand(0);
22578 SDValue N1 = N->getOperand(1);
22579 EVT VT = N->getValueType(0);
22581 // look for psign/blend
22582 if (VT == MVT::v2i64 || VT == MVT::v4i64) {
22583 if (!Subtarget->hasSSSE3() ||
22584 (VT == MVT::v4i64 && !Subtarget->hasInt256()))
22587 // Canonicalize pandn to RHS
22588 if (N0.getOpcode() == X86ISD::ANDNP)
22590 // or (and (m, y), (pandn m, x))
22591 if (N0.getOpcode() == ISD::AND && N1.getOpcode() == X86ISD::ANDNP) {
22592 SDValue Mask = N1.getOperand(0);
22593 SDValue X = N1.getOperand(1);
22595 if (N0.getOperand(0) == Mask)
22596 Y = N0.getOperand(1);
22597 if (N0.getOperand(1) == Mask)
22598 Y = N0.getOperand(0);
22600 // Check to see if the mask appeared in both the AND and ANDNP and
22604 // Validate that X, Y, and Mask are BIT_CONVERTS, and see through them.
22605 // Look through mask bitcast.
22606 if (Mask.getOpcode() == ISD::BITCAST)
22607 Mask = Mask.getOperand(0);
22608 if (X.getOpcode() == ISD::BITCAST)
22609 X = X.getOperand(0);
22610 if (Y.getOpcode() == ISD::BITCAST)
22611 Y = Y.getOperand(0);
22613 EVT MaskVT = Mask.getValueType();
22615 // Validate that the Mask operand is a vector sra node.
22616 // FIXME: what to do for bytes, since there is a psignb/pblendvb, but
22617 // there is no psrai.b
22618 unsigned EltBits = MaskVT.getVectorElementType().getSizeInBits();
22619 unsigned SraAmt = ~0;
22620 if (Mask.getOpcode() == ISD::SRA) {
22621 if (auto *AmtBV = dyn_cast<BuildVectorSDNode>(Mask.getOperand(1)))
22622 if (auto *AmtConst = AmtBV->getConstantSplatNode())
22623 SraAmt = AmtConst->getZExtValue();
22624 } else if (Mask.getOpcode() == X86ISD::VSRAI) {
22625 SDValue SraC = Mask.getOperand(1);
22626 SraAmt = cast<ConstantSDNode>(SraC)->getZExtValue();
22628 if ((SraAmt + 1) != EltBits)
22633 // Now we know we at least have a plendvb with the mask val. See if
22634 // we can form a psignb/w/d.
22635 // psign = x.type == y.type == mask.type && y = sub(0, x);
22636 if (Y.getOpcode() == ISD::SUB && Y.getOperand(1) == X &&
22637 ISD::isBuildVectorAllZeros(Y.getOperand(0).getNode()) &&
22638 X.getValueType() == MaskVT && Y.getValueType() == MaskVT) {
22639 assert((EltBits == 8 || EltBits == 16 || EltBits == 32) &&
22640 "Unsupported VT for PSIGN");
22641 Mask = DAG.getNode(X86ISD::PSIGN, DL, MaskVT, X, Mask.getOperand(0));
22642 return DAG.getNode(ISD::BITCAST, DL, VT, Mask);
22644 // PBLENDVB only available on SSE 4.1
22645 if (!Subtarget->hasSSE41())
22648 EVT BlendVT = (VT == MVT::v4i64) ? MVT::v32i8 : MVT::v16i8;
22650 X = DAG.getNode(ISD::BITCAST, DL, BlendVT, X);
22651 Y = DAG.getNode(ISD::BITCAST, DL, BlendVT, Y);
22652 Mask = DAG.getNode(ISD::BITCAST, DL, BlendVT, Mask);
22653 Mask = DAG.getNode(ISD::VSELECT, DL, BlendVT, Mask, Y, X);
22654 return DAG.getNode(ISD::BITCAST, DL, VT, Mask);
22658 if (VT != MVT::i16 && VT != MVT::i32 && VT != MVT::i64)
22661 // fold (or (x << c) | (y >> (64 - c))) ==> (shld64 x, y, c)
22662 MachineFunction &MF = DAG.getMachineFunction();
22663 bool OptForSize = MF.getFunction()->getAttributes().
22664 hasAttribute(AttributeSet::FunctionIndex, Attribute::OptimizeForSize);
22666 // SHLD/SHRD instructions have lower register pressure, but on some
22667 // platforms they have higher latency than the equivalent
22668 // series of shifts/or that would otherwise be generated.
22669 // Don't fold (or (x << c) | (y >> (64 - c))) if SHLD/SHRD instructions
22670 // have higher latencies and we are not optimizing for size.
22671 if (!OptForSize && Subtarget->isSHLDSlow())
22674 if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL)
22676 if (N0.getOpcode() != ISD::SHL || N1.getOpcode() != ISD::SRL)
22678 if (!N0.hasOneUse() || !N1.hasOneUse())
22681 SDValue ShAmt0 = N0.getOperand(1);
22682 if (ShAmt0.getValueType() != MVT::i8)
22684 SDValue ShAmt1 = N1.getOperand(1);
22685 if (ShAmt1.getValueType() != MVT::i8)
22687 if (ShAmt0.getOpcode() == ISD::TRUNCATE)
22688 ShAmt0 = ShAmt0.getOperand(0);
22689 if (ShAmt1.getOpcode() == ISD::TRUNCATE)
22690 ShAmt1 = ShAmt1.getOperand(0);
22693 unsigned Opc = X86ISD::SHLD;
22694 SDValue Op0 = N0.getOperand(0);
22695 SDValue Op1 = N1.getOperand(0);
22696 if (ShAmt0.getOpcode() == ISD::SUB) {
22697 Opc = X86ISD::SHRD;
22698 std::swap(Op0, Op1);
22699 std::swap(ShAmt0, ShAmt1);
22702 unsigned Bits = VT.getSizeInBits();
22703 if (ShAmt1.getOpcode() == ISD::SUB) {
22704 SDValue Sum = ShAmt1.getOperand(0);
22705 if (ConstantSDNode *SumC = dyn_cast<ConstantSDNode>(Sum)) {
22706 SDValue ShAmt1Op1 = ShAmt1.getOperand(1);
22707 if (ShAmt1Op1.getNode()->getOpcode() == ISD::TRUNCATE)
22708 ShAmt1Op1 = ShAmt1Op1.getOperand(0);
22709 if (SumC->getSExtValue() == Bits && ShAmt1Op1 == ShAmt0)
22710 return DAG.getNode(Opc, DL, VT,
22712 DAG.getNode(ISD::TRUNCATE, DL,
22715 } else if (ConstantSDNode *ShAmt1C = dyn_cast<ConstantSDNode>(ShAmt1)) {
22716 ConstantSDNode *ShAmt0C = dyn_cast<ConstantSDNode>(ShAmt0);
22718 ShAmt0C->getSExtValue() + ShAmt1C->getSExtValue() == Bits)
22719 return DAG.getNode(Opc, DL, VT,
22720 N0.getOperand(0), N1.getOperand(0),
22721 DAG.getNode(ISD::TRUNCATE, DL,
22728 // Generate NEG and CMOV for integer abs.
22729 static SDValue performIntegerAbsCombine(SDNode *N, SelectionDAG &DAG) {
22730 EVT VT = N->getValueType(0);
22732 // Since X86 does not have CMOV for 8-bit integer, we don't convert
22733 // 8-bit integer abs to NEG and CMOV.
22734 if (VT.isInteger() && VT.getSizeInBits() == 8)
22737 SDValue N0 = N->getOperand(0);
22738 SDValue N1 = N->getOperand(1);
22741 // Check pattern of XOR(ADD(X,Y), Y) where Y is SRA(X, size(X)-1)
22742 // and change it to SUB and CMOV.
22743 if (VT.isInteger() && N->getOpcode() == ISD::XOR &&
22744 N0.getOpcode() == ISD::ADD &&
22745 N0.getOperand(1) == N1 &&
22746 N1.getOpcode() == ISD::SRA &&
22747 N1.getOperand(0) == N0.getOperand(0))
22748 if (ConstantSDNode *Y1C = dyn_cast<ConstantSDNode>(N1.getOperand(1)))
22749 if (Y1C->getAPIntValue() == VT.getSizeInBits()-1) {
22750 // Generate SUB & CMOV.
22751 SDValue Neg = DAG.getNode(X86ISD::SUB, DL, DAG.getVTList(VT, MVT::i32),
22752 DAG.getConstant(0, VT), N0.getOperand(0));
22754 SDValue Ops[] = { N0.getOperand(0), Neg,
22755 DAG.getConstant(X86::COND_GE, MVT::i8),
22756 SDValue(Neg.getNode(), 1) };
22757 return DAG.getNode(X86ISD::CMOV, DL, DAG.getVTList(VT, MVT::Glue), Ops);
22762 // PerformXorCombine - Attempts to turn XOR nodes into BLSMSK nodes
22763 static SDValue PerformXorCombine(SDNode *N, SelectionDAG &DAG,
22764 TargetLowering::DAGCombinerInfo &DCI,
22765 const X86Subtarget *Subtarget) {
22766 if (DCI.isBeforeLegalizeOps())
22769 if (Subtarget->hasCMov()) {
22770 SDValue RV = performIntegerAbsCombine(N, DAG);
22778 /// PerformLOADCombine - Do target-specific dag combines on LOAD nodes.
22779 static SDValue PerformLOADCombine(SDNode *N, SelectionDAG &DAG,
22780 TargetLowering::DAGCombinerInfo &DCI,
22781 const X86Subtarget *Subtarget) {
22782 LoadSDNode *Ld = cast<LoadSDNode>(N);
22783 EVT RegVT = Ld->getValueType(0);
22784 EVT MemVT = Ld->getMemoryVT();
22786 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
22788 // On Sandybridge unaligned 256bit loads are inefficient.
22789 ISD::LoadExtType Ext = Ld->getExtensionType();
22790 unsigned Alignment = Ld->getAlignment();
22791 bool IsAligned = Alignment == 0 || Alignment >= MemVT.getSizeInBits()/8;
22792 if (RegVT.is256BitVector() && !Subtarget->hasInt256() &&
22793 !DCI.isBeforeLegalizeOps() && !IsAligned && Ext == ISD::NON_EXTLOAD) {
22794 unsigned NumElems = RegVT.getVectorNumElements();
22798 SDValue Ptr = Ld->getBasePtr();
22799 SDValue Increment = DAG.getConstant(16, TLI.getPointerTy());
22801 EVT HalfVT = EVT::getVectorVT(*DAG.getContext(), MemVT.getScalarType(),
22803 SDValue Load1 = DAG.getLoad(HalfVT, dl, Ld->getChain(), Ptr,
22804 Ld->getPointerInfo(), Ld->isVolatile(),
22805 Ld->isNonTemporal(), Ld->isInvariant(),
22807 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
22808 SDValue Load2 = DAG.getLoad(HalfVT, dl, Ld->getChain(), Ptr,
22809 Ld->getPointerInfo(), Ld->isVolatile(),
22810 Ld->isNonTemporal(), Ld->isInvariant(),
22811 std::min(16U, Alignment));
22812 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
22814 Load2.getValue(1));
22816 SDValue NewVec = DAG.getUNDEF(RegVT);
22817 NewVec = Insert128BitVector(NewVec, Load1, 0, DAG, dl);
22818 NewVec = Insert128BitVector(NewVec, Load2, NumElems/2, DAG, dl);
22819 return DCI.CombineTo(N, NewVec, TF, true);
22825 /// PerformSTORECombine - Do target-specific dag combines on STORE nodes.
22826 static SDValue PerformSTORECombine(SDNode *N, SelectionDAG &DAG,
22827 const X86Subtarget *Subtarget) {
22828 StoreSDNode *St = cast<StoreSDNode>(N);
22829 EVT VT = St->getValue().getValueType();
22830 EVT StVT = St->getMemoryVT();
22832 SDValue StoredVal = St->getOperand(1);
22833 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
22835 // If we are saving a concatenation of two XMM registers, perform two stores.
22836 // On Sandy Bridge, 256-bit memory operations are executed by two
22837 // 128-bit ports. However, on Haswell it is better to issue a single 256-bit
22838 // memory operation.
22839 unsigned Alignment = St->getAlignment();
22840 bool IsAligned = Alignment == 0 || Alignment >= VT.getSizeInBits()/8;
22841 if (VT.is256BitVector() && !Subtarget->hasInt256() &&
22842 StVT == VT && !IsAligned) {
22843 unsigned NumElems = VT.getVectorNumElements();
22847 SDValue Value0 = Extract128BitVector(StoredVal, 0, DAG, dl);
22848 SDValue Value1 = Extract128BitVector(StoredVal, NumElems/2, DAG, dl);
22850 SDValue Stride = DAG.getConstant(16, TLI.getPointerTy());
22851 SDValue Ptr0 = St->getBasePtr();
22852 SDValue Ptr1 = DAG.getNode(ISD::ADD, dl, Ptr0.getValueType(), Ptr0, Stride);
22854 SDValue Ch0 = DAG.getStore(St->getChain(), dl, Value0, Ptr0,
22855 St->getPointerInfo(), St->isVolatile(),
22856 St->isNonTemporal(), Alignment);
22857 SDValue Ch1 = DAG.getStore(St->getChain(), dl, Value1, Ptr1,
22858 St->getPointerInfo(), St->isVolatile(),
22859 St->isNonTemporal(),
22860 std::min(16U, Alignment));
22861 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Ch0, Ch1);
22864 // Optimize trunc store (of multiple scalars) to shuffle and store.
22865 // First, pack all of the elements in one place. Next, store to memory
22866 // in fewer chunks.
22867 if (St->isTruncatingStore() && VT.isVector()) {
22868 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
22869 unsigned NumElems = VT.getVectorNumElements();
22870 assert(StVT != VT && "Cannot truncate to the same type");
22871 unsigned FromSz = VT.getVectorElementType().getSizeInBits();
22872 unsigned ToSz = StVT.getVectorElementType().getSizeInBits();
22874 // From, To sizes and ElemCount must be pow of two
22875 if (!isPowerOf2_32(NumElems * FromSz * ToSz)) return SDValue();
22876 // We are going to use the original vector elt for storing.
22877 // Accumulated smaller vector elements must be a multiple of the store size.
22878 if (0 != (NumElems * FromSz) % ToSz) return SDValue();
22880 unsigned SizeRatio = FromSz / ToSz;
22882 assert(SizeRatio * NumElems * ToSz == VT.getSizeInBits());
22884 // Create a type on which we perform the shuffle
22885 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(),
22886 StVT.getScalarType(), NumElems*SizeRatio);
22888 assert(WideVecVT.getSizeInBits() == VT.getSizeInBits());
22890 SDValue WideVec = DAG.getNode(ISD::BITCAST, dl, WideVecVT, St->getValue());
22891 SmallVector<int, 8> ShuffleVec(NumElems * SizeRatio, -1);
22892 for (unsigned i = 0; i != NumElems; ++i)
22893 ShuffleVec[i] = i * SizeRatio;
22895 // Can't shuffle using an illegal type.
22896 if (!TLI.isTypeLegal(WideVecVT))
22899 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, WideVec,
22900 DAG.getUNDEF(WideVecVT),
22902 // At this point all of the data is stored at the bottom of the
22903 // register. We now need to save it to mem.
22905 // Find the largest store unit
22906 MVT StoreType = MVT::i8;
22907 for (unsigned tp = MVT::FIRST_INTEGER_VALUETYPE;
22908 tp < MVT::LAST_INTEGER_VALUETYPE; ++tp) {
22909 MVT Tp = (MVT::SimpleValueType)tp;
22910 if (TLI.isTypeLegal(Tp) && Tp.getSizeInBits() <= NumElems * ToSz)
22914 // On 32bit systems, we can't save 64bit integers. Try bitcasting to F64.
22915 if (TLI.isTypeLegal(MVT::f64) && StoreType.getSizeInBits() < 64 &&
22916 (64 <= NumElems * ToSz))
22917 StoreType = MVT::f64;
22919 // Bitcast the original vector into a vector of store-size units
22920 EVT StoreVecVT = EVT::getVectorVT(*DAG.getContext(),
22921 StoreType, VT.getSizeInBits()/StoreType.getSizeInBits());
22922 assert(StoreVecVT.getSizeInBits() == VT.getSizeInBits());
22923 SDValue ShuffWide = DAG.getNode(ISD::BITCAST, dl, StoreVecVT, Shuff);
22924 SmallVector<SDValue, 8> Chains;
22925 SDValue Increment = DAG.getConstant(StoreType.getSizeInBits()/8,
22926 TLI.getPointerTy());
22927 SDValue Ptr = St->getBasePtr();
22929 // Perform one or more big stores into memory.
22930 for (unsigned i=0, e=(ToSz*NumElems)/StoreType.getSizeInBits(); i!=e; ++i) {
22931 SDValue SubVec = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
22932 StoreType, ShuffWide,
22933 DAG.getIntPtrConstant(i));
22934 SDValue Ch = DAG.getStore(St->getChain(), dl, SubVec, Ptr,
22935 St->getPointerInfo(), St->isVolatile(),
22936 St->isNonTemporal(), St->getAlignment());
22937 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
22938 Chains.push_back(Ch);
22941 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Chains);
22944 // Turn load->store of MMX types into GPR load/stores. This avoids clobbering
22945 // the FP state in cases where an emms may be missing.
22946 // A preferable solution to the general problem is to figure out the right
22947 // places to insert EMMS. This qualifies as a quick hack.
22949 // Similarly, turn load->store of i64 into double load/stores in 32-bit mode.
22950 if (VT.getSizeInBits() != 64)
22953 const Function *F = DAG.getMachineFunction().getFunction();
22954 bool NoImplicitFloatOps = F->getAttributes().
22955 hasAttribute(AttributeSet::FunctionIndex, Attribute::NoImplicitFloat);
22956 bool F64IsLegal = !DAG.getTarget().Options.UseSoftFloat && !NoImplicitFloatOps
22957 && Subtarget->hasSSE2();
22958 if ((VT.isVector() ||
22959 (VT == MVT::i64 && F64IsLegal && !Subtarget->is64Bit())) &&
22960 isa<LoadSDNode>(St->getValue()) &&
22961 !cast<LoadSDNode>(St->getValue())->isVolatile() &&
22962 St->getChain().hasOneUse() && !St->isVolatile()) {
22963 SDNode* LdVal = St->getValue().getNode();
22964 LoadSDNode *Ld = nullptr;
22965 int TokenFactorIndex = -1;
22966 SmallVector<SDValue, 8> Ops;
22967 SDNode* ChainVal = St->getChain().getNode();
22968 // Must be a store of a load. We currently handle two cases: the load
22969 // is a direct child, and it's under an intervening TokenFactor. It is
22970 // possible to dig deeper under nested TokenFactors.
22971 if (ChainVal == LdVal)
22972 Ld = cast<LoadSDNode>(St->getChain());
22973 else if (St->getValue().hasOneUse() &&
22974 ChainVal->getOpcode() == ISD::TokenFactor) {
22975 for (unsigned i = 0, e = ChainVal->getNumOperands(); i != e; ++i) {
22976 if (ChainVal->getOperand(i).getNode() == LdVal) {
22977 TokenFactorIndex = i;
22978 Ld = cast<LoadSDNode>(St->getValue());
22980 Ops.push_back(ChainVal->getOperand(i));
22984 if (!Ld || !ISD::isNormalLoad(Ld))
22987 // If this is not the MMX case, i.e. we are just turning i64 load/store
22988 // into f64 load/store, avoid the transformation if there are multiple
22989 // uses of the loaded value.
22990 if (!VT.isVector() && !Ld->hasNUsesOfValue(1, 0))
22995 // If we are a 64-bit capable x86, lower to a single movq load/store pair.
22996 // Otherwise, if it's legal to use f64 SSE instructions, use f64 load/store
22998 if (Subtarget->is64Bit() || F64IsLegal) {
22999 EVT LdVT = Subtarget->is64Bit() ? MVT::i64 : MVT::f64;
23000 SDValue NewLd = DAG.getLoad(LdVT, LdDL, Ld->getChain(), Ld->getBasePtr(),
23001 Ld->getPointerInfo(), Ld->isVolatile(),
23002 Ld->isNonTemporal(), Ld->isInvariant(),
23003 Ld->getAlignment());
23004 SDValue NewChain = NewLd.getValue(1);
23005 if (TokenFactorIndex != -1) {
23006 Ops.push_back(NewChain);
23007 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, Ops);
23009 return DAG.getStore(NewChain, StDL, NewLd, St->getBasePtr(),
23010 St->getPointerInfo(),
23011 St->isVolatile(), St->isNonTemporal(),
23012 St->getAlignment());
23015 // Otherwise, lower to two pairs of 32-bit loads / stores.
23016 SDValue LoAddr = Ld->getBasePtr();
23017 SDValue HiAddr = DAG.getNode(ISD::ADD, LdDL, MVT::i32, LoAddr,
23018 DAG.getConstant(4, MVT::i32));
23020 SDValue LoLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), LoAddr,
23021 Ld->getPointerInfo(),
23022 Ld->isVolatile(), Ld->isNonTemporal(),
23023 Ld->isInvariant(), Ld->getAlignment());
23024 SDValue HiLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), HiAddr,
23025 Ld->getPointerInfo().getWithOffset(4),
23026 Ld->isVolatile(), Ld->isNonTemporal(),
23028 MinAlign(Ld->getAlignment(), 4));
23030 SDValue NewChain = LoLd.getValue(1);
23031 if (TokenFactorIndex != -1) {
23032 Ops.push_back(LoLd);
23033 Ops.push_back(HiLd);
23034 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, Ops);
23037 LoAddr = St->getBasePtr();
23038 HiAddr = DAG.getNode(ISD::ADD, StDL, MVT::i32, LoAddr,
23039 DAG.getConstant(4, MVT::i32));
23041 SDValue LoSt = DAG.getStore(NewChain, StDL, LoLd, LoAddr,
23042 St->getPointerInfo(),
23043 St->isVolatile(), St->isNonTemporal(),
23044 St->getAlignment());
23045 SDValue HiSt = DAG.getStore(NewChain, StDL, HiLd, HiAddr,
23046 St->getPointerInfo().getWithOffset(4),
23048 St->isNonTemporal(),
23049 MinAlign(St->getAlignment(), 4));
23050 return DAG.getNode(ISD::TokenFactor, StDL, MVT::Other, LoSt, HiSt);
23055 /// isHorizontalBinOp - Return 'true' if this vector operation is "horizontal"
23056 /// and return the operands for the horizontal operation in LHS and RHS. A
23057 /// horizontal operation performs the binary operation on successive elements
23058 /// of its first operand, then on successive elements of its second operand,
23059 /// returning the resulting values in a vector. For example, if
23060 /// A = < float a0, float a1, float a2, float a3 >
23062 /// B = < float b0, float b1, float b2, float b3 >
23063 /// then the result of doing a horizontal operation on A and B is
23064 /// A horizontal-op B = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >.
23065 /// In short, LHS and RHS are inspected to see if LHS op RHS is of the form
23066 /// A horizontal-op B, for some already available A and B, and if so then LHS is
23067 /// set to A, RHS to B, and the routine returns 'true'.
23068 /// Note that the binary operation should have the property that if one of the
23069 /// operands is UNDEF then the result is UNDEF.
23070 static bool isHorizontalBinOp(SDValue &LHS, SDValue &RHS, bool IsCommutative) {
23071 // Look for the following pattern: if
23072 // A = < float a0, float a1, float a2, float a3 >
23073 // B = < float b0, float b1, float b2, float b3 >
23075 // LHS = VECTOR_SHUFFLE A, B, <0, 2, 4, 6>
23076 // RHS = VECTOR_SHUFFLE A, B, <1, 3, 5, 7>
23077 // then LHS op RHS = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >
23078 // which is A horizontal-op B.
23080 // At least one of the operands should be a vector shuffle.
23081 if (LHS.getOpcode() != ISD::VECTOR_SHUFFLE &&
23082 RHS.getOpcode() != ISD::VECTOR_SHUFFLE)
23085 MVT VT = LHS.getSimpleValueType();
23087 assert((VT.is128BitVector() || VT.is256BitVector()) &&
23088 "Unsupported vector type for horizontal add/sub");
23090 // Handle 128 and 256-bit vector lengths. AVX defines horizontal add/sub to
23091 // operate independently on 128-bit lanes.
23092 unsigned NumElts = VT.getVectorNumElements();
23093 unsigned NumLanes = VT.getSizeInBits()/128;
23094 unsigned NumLaneElts = NumElts / NumLanes;
23095 assert((NumLaneElts % 2 == 0) &&
23096 "Vector type should have an even number of elements in each lane");
23097 unsigned HalfLaneElts = NumLaneElts/2;
23099 // View LHS in the form
23100 // LHS = VECTOR_SHUFFLE A, B, LMask
23101 // If LHS is not a shuffle then pretend it is the shuffle
23102 // LHS = VECTOR_SHUFFLE LHS, undef, <0, 1, ..., N-1>
23103 // NOTE: in what follows a default initialized SDValue represents an UNDEF of
23106 SmallVector<int, 16> LMask(NumElts);
23107 if (LHS.getOpcode() == ISD::VECTOR_SHUFFLE) {
23108 if (LHS.getOperand(0).getOpcode() != ISD::UNDEF)
23109 A = LHS.getOperand(0);
23110 if (LHS.getOperand(1).getOpcode() != ISD::UNDEF)
23111 B = LHS.getOperand(1);
23112 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(LHS.getNode())->getMask();
23113 std::copy(Mask.begin(), Mask.end(), LMask.begin());
23115 if (LHS.getOpcode() != ISD::UNDEF)
23117 for (unsigned i = 0; i != NumElts; ++i)
23121 // Likewise, view RHS in the form
23122 // RHS = VECTOR_SHUFFLE C, D, RMask
23124 SmallVector<int, 16> RMask(NumElts);
23125 if (RHS.getOpcode() == ISD::VECTOR_SHUFFLE) {
23126 if (RHS.getOperand(0).getOpcode() != ISD::UNDEF)
23127 C = RHS.getOperand(0);
23128 if (RHS.getOperand(1).getOpcode() != ISD::UNDEF)
23129 D = RHS.getOperand(1);
23130 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(RHS.getNode())->getMask();
23131 std::copy(Mask.begin(), Mask.end(), RMask.begin());
23133 if (RHS.getOpcode() != ISD::UNDEF)
23135 for (unsigned i = 0; i != NumElts; ++i)
23139 // Check that the shuffles are both shuffling the same vectors.
23140 if (!(A == C && B == D) && !(A == D && B == C))
23143 // If everything is UNDEF then bail out: it would be better to fold to UNDEF.
23144 if (!A.getNode() && !B.getNode())
23147 // If A and B occur in reverse order in RHS, then "swap" them (which means
23148 // rewriting the mask).
23150 CommuteVectorShuffleMask(RMask, NumElts);
23152 // At this point LHS and RHS are equivalent to
23153 // LHS = VECTOR_SHUFFLE A, B, LMask
23154 // RHS = VECTOR_SHUFFLE A, B, RMask
23155 // Check that the masks correspond to performing a horizontal operation.
23156 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
23157 for (unsigned i = 0; i != NumLaneElts; ++i) {
23158 int LIdx = LMask[i+l], RIdx = RMask[i+l];
23160 // Ignore any UNDEF components.
23161 if (LIdx < 0 || RIdx < 0 ||
23162 (!A.getNode() && (LIdx < (int)NumElts || RIdx < (int)NumElts)) ||
23163 (!B.getNode() && (LIdx >= (int)NumElts || RIdx >= (int)NumElts)))
23166 // Check that successive elements are being operated on. If not, this is
23167 // not a horizontal operation.
23168 unsigned Src = (i/HalfLaneElts); // each lane is split between srcs
23169 int Index = 2*(i%HalfLaneElts) + NumElts*Src + l;
23170 if (!(LIdx == Index && RIdx == Index + 1) &&
23171 !(IsCommutative && LIdx == Index + 1 && RIdx == Index))
23176 LHS = A.getNode() ? A : B; // If A is 'UNDEF', use B for it.
23177 RHS = B.getNode() ? B : A; // If B is 'UNDEF', use A for it.
23181 /// PerformFADDCombine - Do target-specific dag combines on floating point adds.
23182 static SDValue PerformFADDCombine(SDNode *N, SelectionDAG &DAG,
23183 const X86Subtarget *Subtarget) {
23184 EVT VT = N->getValueType(0);
23185 SDValue LHS = N->getOperand(0);
23186 SDValue RHS = N->getOperand(1);
23188 // Try to synthesize horizontal adds from adds of shuffles.
23189 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
23190 (Subtarget->hasFp256() && (VT == MVT::v8f32 || VT == MVT::v4f64))) &&
23191 isHorizontalBinOp(LHS, RHS, true))
23192 return DAG.getNode(X86ISD::FHADD, SDLoc(N), VT, LHS, RHS);
23196 /// PerformFSUBCombine - Do target-specific dag combines on floating point subs.
23197 static SDValue PerformFSUBCombine(SDNode *N, SelectionDAG &DAG,
23198 const X86Subtarget *Subtarget) {
23199 EVT VT = N->getValueType(0);
23200 SDValue LHS = N->getOperand(0);
23201 SDValue RHS = N->getOperand(1);
23203 // Try to synthesize horizontal subs from subs of shuffles.
23204 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
23205 (Subtarget->hasFp256() && (VT == MVT::v8f32 || VT == MVT::v4f64))) &&
23206 isHorizontalBinOp(LHS, RHS, false))
23207 return DAG.getNode(X86ISD::FHSUB, SDLoc(N), VT, LHS, RHS);
23211 /// PerformFORCombine - Do target-specific dag combines on X86ISD::FOR and
23212 /// X86ISD::FXOR nodes.
23213 static SDValue PerformFORCombine(SDNode *N, SelectionDAG &DAG) {
23214 assert(N->getOpcode() == X86ISD::FOR || N->getOpcode() == X86ISD::FXOR);
23215 // F[X]OR(0.0, x) -> x
23216 // F[X]OR(x, 0.0) -> x
23217 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
23218 if (C->getValueAPF().isPosZero())
23219 return N->getOperand(1);
23220 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
23221 if (C->getValueAPF().isPosZero())
23222 return N->getOperand(0);
23226 /// PerformFMinFMaxCombine - Do target-specific dag combines on X86ISD::FMIN and
23227 /// X86ISD::FMAX nodes.
23228 static SDValue PerformFMinFMaxCombine(SDNode *N, SelectionDAG &DAG) {
23229 assert(N->getOpcode() == X86ISD::FMIN || N->getOpcode() == X86ISD::FMAX);
23231 // Only perform optimizations if UnsafeMath is used.
23232 if (!DAG.getTarget().Options.UnsafeFPMath)
23235 // If we run in unsafe-math mode, then convert the FMAX and FMIN nodes
23236 // into FMINC and FMAXC, which are Commutative operations.
23237 unsigned NewOp = 0;
23238 switch (N->getOpcode()) {
23239 default: llvm_unreachable("unknown opcode");
23240 case X86ISD::FMIN: NewOp = X86ISD::FMINC; break;
23241 case X86ISD::FMAX: NewOp = X86ISD::FMAXC; break;
23244 return DAG.getNode(NewOp, SDLoc(N), N->getValueType(0),
23245 N->getOperand(0), N->getOperand(1));
23248 /// PerformFANDCombine - Do target-specific dag combines on X86ISD::FAND nodes.
23249 static SDValue PerformFANDCombine(SDNode *N, SelectionDAG &DAG) {
23250 // FAND(0.0, x) -> 0.0
23251 // FAND(x, 0.0) -> 0.0
23252 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
23253 if (C->getValueAPF().isPosZero())
23254 return N->getOperand(0);
23255 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
23256 if (C->getValueAPF().isPosZero())
23257 return N->getOperand(1);
23261 /// PerformFANDNCombine - Do target-specific dag combines on X86ISD::FANDN nodes
23262 static SDValue PerformFANDNCombine(SDNode *N, SelectionDAG &DAG) {
23263 // FANDN(x, 0.0) -> 0.0
23264 // FANDN(0.0, x) -> x
23265 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
23266 if (C->getValueAPF().isPosZero())
23267 return N->getOperand(1);
23268 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
23269 if (C->getValueAPF().isPosZero())
23270 return N->getOperand(1);
23274 static SDValue PerformBTCombine(SDNode *N,
23276 TargetLowering::DAGCombinerInfo &DCI) {
23277 // BT ignores high bits in the bit index operand.
23278 SDValue Op1 = N->getOperand(1);
23279 if (Op1.hasOneUse()) {
23280 unsigned BitWidth = Op1.getValueSizeInBits();
23281 APInt DemandedMask = APInt::getLowBitsSet(BitWidth, Log2_32(BitWidth));
23282 APInt KnownZero, KnownOne;
23283 TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(),
23284 !DCI.isBeforeLegalizeOps());
23285 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
23286 if (TLO.ShrinkDemandedConstant(Op1, DemandedMask) ||
23287 TLI.SimplifyDemandedBits(Op1, DemandedMask, KnownZero, KnownOne, TLO))
23288 DCI.CommitTargetLoweringOpt(TLO);
23293 static SDValue PerformVZEXT_MOVLCombine(SDNode *N, SelectionDAG &DAG) {
23294 SDValue Op = N->getOperand(0);
23295 if (Op.getOpcode() == ISD::BITCAST)
23296 Op = Op.getOperand(0);
23297 EVT VT = N->getValueType(0), OpVT = Op.getValueType();
23298 if (Op.getOpcode() == X86ISD::VZEXT_LOAD &&
23299 VT.getVectorElementType().getSizeInBits() ==
23300 OpVT.getVectorElementType().getSizeInBits()) {
23301 return DAG.getNode(ISD::BITCAST, SDLoc(N), VT, Op);
23306 static SDValue PerformSIGN_EXTEND_INREGCombine(SDNode *N, SelectionDAG &DAG,
23307 const X86Subtarget *Subtarget) {
23308 EVT VT = N->getValueType(0);
23309 if (!VT.isVector())
23312 SDValue N0 = N->getOperand(0);
23313 SDValue N1 = N->getOperand(1);
23314 EVT ExtraVT = cast<VTSDNode>(N1)->getVT();
23317 // The SIGN_EXTEND_INREG to v4i64 is expensive operation on the
23318 // both SSE and AVX2 since there is no sign-extended shift right
23319 // operation on a vector with 64-bit elements.
23320 //(sext_in_reg (v4i64 anyext (v4i32 x )), ExtraVT) ->
23321 // (v4i64 sext (v4i32 sext_in_reg (v4i32 x , ExtraVT)))
23322 if (VT == MVT::v4i64 && (N0.getOpcode() == ISD::ANY_EXTEND ||
23323 N0.getOpcode() == ISD::SIGN_EXTEND)) {
23324 SDValue N00 = N0.getOperand(0);
23326 // EXTLOAD has a better solution on AVX2,
23327 // it may be replaced with X86ISD::VSEXT node.
23328 if (N00.getOpcode() == ISD::LOAD && Subtarget->hasInt256())
23329 if (!ISD::isNormalLoad(N00.getNode()))
23332 if (N00.getValueType() == MVT::v4i32 && ExtraVT.getSizeInBits() < 128) {
23333 SDValue Tmp = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, MVT::v4i32,
23335 return DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v4i64, Tmp);
23341 static SDValue PerformSExtCombine(SDNode *N, SelectionDAG &DAG,
23342 TargetLowering::DAGCombinerInfo &DCI,
23343 const X86Subtarget *Subtarget) {
23344 if (!DCI.isBeforeLegalizeOps())
23347 if (!Subtarget->hasFp256())
23350 EVT VT = N->getValueType(0);
23351 if (VT.isVector() && VT.getSizeInBits() == 256) {
23352 SDValue R = WidenMaskArithmetic(N, DAG, DCI, Subtarget);
23360 static SDValue PerformFMACombine(SDNode *N, SelectionDAG &DAG,
23361 const X86Subtarget* Subtarget) {
23363 EVT VT = N->getValueType(0);
23365 // Let legalize expand this if it isn't a legal type yet.
23366 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
23369 EVT ScalarVT = VT.getScalarType();
23370 if ((ScalarVT != MVT::f32 && ScalarVT != MVT::f64) ||
23371 (!Subtarget->hasFMA() && !Subtarget->hasFMA4()))
23374 SDValue A = N->getOperand(0);
23375 SDValue B = N->getOperand(1);
23376 SDValue C = N->getOperand(2);
23378 bool NegA = (A.getOpcode() == ISD::FNEG);
23379 bool NegB = (B.getOpcode() == ISD::FNEG);
23380 bool NegC = (C.getOpcode() == ISD::FNEG);
23382 // Negative multiplication when NegA xor NegB
23383 bool NegMul = (NegA != NegB);
23385 A = A.getOperand(0);
23387 B = B.getOperand(0);
23389 C = C.getOperand(0);
23393 Opcode = (!NegC) ? X86ISD::FMADD : X86ISD::FMSUB;
23395 Opcode = (!NegC) ? X86ISD::FNMADD : X86ISD::FNMSUB;
23397 return DAG.getNode(Opcode, dl, VT, A, B, C);
23400 static SDValue PerformZExtCombine(SDNode *N, SelectionDAG &DAG,
23401 TargetLowering::DAGCombinerInfo &DCI,
23402 const X86Subtarget *Subtarget) {
23403 // (i32 zext (and (i8 x86isd::setcc_carry), 1)) ->
23404 // (and (i32 x86isd::setcc_carry), 1)
23405 // This eliminates the zext. This transformation is necessary because
23406 // ISD::SETCC is always legalized to i8.
23408 SDValue N0 = N->getOperand(0);
23409 EVT VT = N->getValueType(0);
23411 if (N0.getOpcode() == ISD::AND &&
23413 N0.getOperand(0).hasOneUse()) {
23414 SDValue N00 = N0.getOperand(0);
23415 if (N00.getOpcode() == X86ISD::SETCC_CARRY) {
23416 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
23417 if (!C || C->getZExtValue() != 1)
23419 return DAG.getNode(ISD::AND, dl, VT,
23420 DAG.getNode(X86ISD::SETCC_CARRY, dl, VT,
23421 N00.getOperand(0), N00.getOperand(1)),
23422 DAG.getConstant(1, VT));
23426 if (N0.getOpcode() == ISD::TRUNCATE &&
23428 N0.getOperand(0).hasOneUse()) {
23429 SDValue N00 = N0.getOperand(0);
23430 if (N00.getOpcode() == X86ISD::SETCC_CARRY) {
23431 return DAG.getNode(ISD::AND, dl, VT,
23432 DAG.getNode(X86ISD::SETCC_CARRY, dl, VT,
23433 N00.getOperand(0), N00.getOperand(1)),
23434 DAG.getConstant(1, VT));
23437 if (VT.is256BitVector()) {
23438 SDValue R = WidenMaskArithmetic(N, DAG, DCI, Subtarget);
23446 // Optimize x == -y --> x+y == 0
23447 // x != -y --> x+y != 0
23448 static SDValue PerformISDSETCCCombine(SDNode *N, SelectionDAG &DAG,
23449 const X86Subtarget* Subtarget) {
23450 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(2))->get();
23451 SDValue LHS = N->getOperand(0);
23452 SDValue RHS = N->getOperand(1);
23453 EVT VT = N->getValueType(0);
23456 if ((CC == ISD::SETNE || CC == ISD::SETEQ) && LHS.getOpcode() == ISD::SUB)
23457 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(LHS.getOperand(0)))
23458 if (C->getAPIntValue() == 0 && LHS.hasOneUse()) {
23459 SDValue addV = DAG.getNode(ISD::ADD, SDLoc(N),
23460 LHS.getValueType(), RHS, LHS.getOperand(1));
23461 return DAG.getSetCC(SDLoc(N), N->getValueType(0),
23462 addV, DAG.getConstant(0, addV.getValueType()), CC);
23464 if ((CC == ISD::SETNE || CC == ISD::SETEQ) && RHS.getOpcode() == ISD::SUB)
23465 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS.getOperand(0)))
23466 if (C->getAPIntValue() == 0 && RHS.hasOneUse()) {
23467 SDValue addV = DAG.getNode(ISD::ADD, SDLoc(N),
23468 RHS.getValueType(), LHS, RHS.getOperand(1));
23469 return DAG.getSetCC(SDLoc(N), N->getValueType(0),
23470 addV, DAG.getConstant(0, addV.getValueType()), CC);
23473 if (VT.getScalarType() == MVT::i1) {
23474 bool IsSEXT0 = (LHS.getOpcode() == ISD::SIGN_EXTEND) &&
23475 (LHS.getOperand(0).getValueType().getScalarType() == MVT::i1);
23476 bool IsVZero0 = ISD::isBuildVectorAllZeros(LHS.getNode());
23477 if (!IsSEXT0 && !IsVZero0)
23479 bool IsSEXT1 = (RHS.getOpcode() == ISD::SIGN_EXTEND) &&
23480 (RHS.getOperand(0).getValueType().getScalarType() == MVT::i1);
23481 bool IsVZero1 = ISD::isBuildVectorAllZeros(RHS.getNode());
23483 if (!IsSEXT1 && !IsVZero1)
23486 if (IsSEXT0 && IsVZero1) {
23487 assert(VT == LHS.getOperand(0).getValueType() && "Uexpected operand type");
23488 if (CC == ISD::SETEQ)
23489 return DAG.getNOT(DL, LHS.getOperand(0), VT);
23490 return LHS.getOperand(0);
23492 if (IsSEXT1 && IsVZero0) {
23493 assert(VT == RHS.getOperand(0).getValueType() && "Uexpected operand type");
23494 if (CC == ISD::SETEQ)
23495 return DAG.getNOT(DL, RHS.getOperand(0), VT);
23496 return RHS.getOperand(0);
23503 static SDValue PerformINSERTPSCombine(SDNode *N, SelectionDAG &DAG,
23504 const X86Subtarget *Subtarget) {
23506 MVT VT = N->getOperand(1)->getSimpleValueType(0);
23507 assert((VT == MVT::v4f32 || VT == MVT::v4i32) &&
23508 "X86insertps is only defined for v4x32");
23510 SDValue Ld = N->getOperand(1);
23511 if (MayFoldLoad(Ld)) {
23512 // Extract the countS bits from the immediate so we can get the proper
23513 // address when narrowing the vector load to a specific element.
23514 // When the second source op is a memory address, interps doesn't use
23515 // countS and just gets an f32 from that address.
23516 unsigned DestIndex =
23517 cast<ConstantSDNode>(N->getOperand(2))->getZExtValue() >> 6;
23518 Ld = NarrowVectorLoadToElement(cast<LoadSDNode>(Ld), DestIndex, DAG);
23522 // Create this as a scalar to vector to match the instruction pattern.
23523 SDValue LoadScalarToVector = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Ld);
23524 // countS bits are ignored when loading from memory on insertps, which
23525 // means we don't need to explicitly set them to 0.
23526 return DAG.getNode(X86ISD::INSERTPS, dl, VT, N->getOperand(0),
23527 LoadScalarToVector, N->getOperand(2));
23530 // Helper function of PerformSETCCCombine. It is to materialize "setb reg"
23531 // as "sbb reg,reg", since it can be extended without zext and produces
23532 // an all-ones bit which is more useful than 0/1 in some cases.
23533 static SDValue MaterializeSETB(SDLoc DL, SDValue EFLAGS, SelectionDAG &DAG,
23536 return DAG.getNode(ISD::AND, DL, VT,
23537 DAG.getNode(X86ISD::SETCC_CARRY, DL, MVT::i8,
23538 DAG.getConstant(X86::COND_B, MVT::i8), EFLAGS),
23539 DAG.getConstant(1, VT));
23540 assert (VT == MVT::i1 && "Unexpected type for SECCC node");
23541 return DAG.getNode(ISD::TRUNCATE, DL, MVT::i1,
23542 DAG.getNode(X86ISD::SETCC_CARRY, DL, MVT::i8,
23543 DAG.getConstant(X86::COND_B, MVT::i8), EFLAGS));
23546 // Optimize RES = X86ISD::SETCC CONDCODE, EFLAG_INPUT
23547 static SDValue PerformSETCCCombine(SDNode *N, SelectionDAG &DAG,
23548 TargetLowering::DAGCombinerInfo &DCI,
23549 const X86Subtarget *Subtarget) {
23551 X86::CondCode CC = X86::CondCode(N->getConstantOperandVal(0));
23552 SDValue EFLAGS = N->getOperand(1);
23554 if (CC == X86::COND_A) {
23555 // Try to convert COND_A into COND_B in an attempt to facilitate
23556 // materializing "setb reg".
23558 // Do not flip "e > c", where "c" is a constant, because Cmp instruction
23559 // cannot take an immediate as its first operand.
23561 if (EFLAGS.getOpcode() == X86ISD::SUB && EFLAGS.hasOneUse() &&
23562 EFLAGS.getValueType().isInteger() &&
23563 !isa<ConstantSDNode>(EFLAGS.getOperand(1))) {
23564 SDValue NewSub = DAG.getNode(X86ISD::SUB, SDLoc(EFLAGS),
23565 EFLAGS.getNode()->getVTList(),
23566 EFLAGS.getOperand(1), EFLAGS.getOperand(0));
23567 SDValue NewEFLAGS = SDValue(NewSub.getNode(), EFLAGS.getResNo());
23568 return MaterializeSETB(DL, NewEFLAGS, DAG, N->getSimpleValueType(0));
23572 // Materialize "setb reg" as "sbb reg,reg", since it can be extended without
23573 // a zext and produces an all-ones bit which is more useful than 0/1 in some
23575 if (CC == X86::COND_B)
23576 return MaterializeSETB(DL, EFLAGS, DAG, N->getSimpleValueType(0));
23580 Flags = checkBoolTestSetCCCombine(EFLAGS, CC);
23581 if (Flags.getNode()) {
23582 SDValue Cond = DAG.getConstant(CC, MVT::i8);
23583 return DAG.getNode(X86ISD::SETCC, DL, N->getVTList(), Cond, Flags);
23589 // Optimize branch condition evaluation.
23591 static SDValue PerformBrCondCombine(SDNode *N, SelectionDAG &DAG,
23592 TargetLowering::DAGCombinerInfo &DCI,
23593 const X86Subtarget *Subtarget) {
23595 SDValue Chain = N->getOperand(0);
23596 SDValue Dest = N->getOperand(1);
23597 SDValue EFLAGS = N->getOperand(3);
23598 X86::CondCode CC = X86::CondCode(N->getConstantOperandVal(2));
23602 Flags = checkBoolTestSetCCCombine(EFLAGS, CC);
23603 if (Flags.getNode()) {
23604 SDValue Cond = DAG.getConstant(CC, MVT::i8);
23605 return DAG.getNode(X86ISD::BRCOND, DL, N->getVTList(), Chain, Dest, Cond,
23612 static SDValue performVectorCompareAndMaskUnaryOpCombine(SDNode *N,
23613 SelectionDAG &DAG) {
23614 // Take advantage of vector comparisons producing 0 or -1 in each lane to
23615 // optimize away operation when it's from a constant.
23617 // The general transformation is:
23618 // UNARYOP(AND(VECTOR_CMP(x,y), constant)) -->
23619 // AND(VECTOR_CMP(x,y), constant2)
23620 // constant2 = UNARYOP(constant)
23622 // Early exit if this isn't a vector operation, the operand of the
23623 // unary operation isn't a bitwise AND, or if the sizes of the operations
23624 // aren't the same.
23625 EVT VT = N->getValueType(0);
23626 if (!VT.isVector() || N->getOperand(0)->getOpcode() != ISD::AND ||
23627 N->getOperand(0)->getOperand(0)->getOpcode() != ISD::SETCC ||
23628 VT.getSizeInBits() != N->getOperand(0)->getValueType(0).getSizeInBits())
23631 // Now check that the other operand of the AND is a constant. We could
23632 // make the transformation for non-constant splats as well, but it's unclear
23633 // that would be a benefit as it would not eliminate any operations, just
23634 // perform one more step in scalar code before moving to the vector unit.
23635 if (BuildVectorSDNode *BV =
23636 dyn_cast<BuildVectorSDNode>(N->getOperand(0)->getOperand(1))) {
23637 // Bail out if the vector isn't a constant.
23638 if (!BV->isConstant())
23641 // Everything checks out. Build up the new and improved node.
23643 EVT IntVT = BV->getValueType(0);
23644 // Create a new constant of the appropriate type for the transformed
23646 SDValue SourceConst = DAG.getNode(N->getOpcode(), DL, VT, SDValue(BV, 0));
23647 // The AND node needs bitcasts to/from an integer vector type around it.
23648 SDValue MaskConst = DAG.getNode(ISD::BITCAST, DL, IntVT, SourceConst);
23649 SDValue NewAnd = DAG.getNode(ISD::AND, DL, IntVT,
23650 N->getOperand(0)->getOperand(0), MaskConst);
23651 SDValue Res = DAG.getNode(ISD::BITCAST, DL, VT, NewAnd);
23658 static SDValue PerformSINT_TO_FPCombine(SDNode *N, SelectionDAG &DAG,
23659 const X86TargetLowering *XTLI) {
23660 // First try to optimize away the conversion entirely when it's
23661 // conditionally from a constant. Vectors only.
23662 SDValue Res = performVectorCompareAndMaskUnaryOpCombine(N, DAG);
23663 if (Res != SDValue())
23666 // Now move on to more general possibilities.
23667 SDValue Op0 = N->getOperand(0);
23668 EVT InVT = Op0->getValueType(0);
23670 // SINT_TO_FP(v4i8) -> SINT_TO_FP(SEXT(v4i8 to v4i32))
23671 if (InVT == MVT::v8i8 || InVT == MVT::v4i8) {
23673 MVT DstVT = InVT == MVT::v4i8 ? MVT::v4i32 : MVT::v8i32;
23674 SDValue P = DAG.getNode(ISD::SIGN_EXTEND, dl, DstVT, Op0);
23675 return DAG.getNode(ISD::SINT_TO_FP, dl, N->getValueType(0), P);
23678 // Transform (SINT_TO_FP (i64 ...)) into an x87 operation if we have
23679 // a 32-bit target where SSE doesn't support i64->FP operations.
23680 if (Op0.getOpcode() == ISD::LOAD) {
23681 LoadSDNode *Ld = cast<LoadSDNode>(Op0.getNode());
23682 EVT VT = Ld->getValueType(0);
23683 if (!Ld->isVolatile() && !N->getValueType(0).isVector() &&
23684 ISD::isNON_EXTLoad(Op0.getNode()) && Op0.hasOneUse() &&
23685 !XTLI->getSubtarget()->is64Bit() &&
23687 SDValue FILDChain = XTLI->BuildFILD(SDValue(N, 0), Ld->getValueType(0),
23688 Ld->getChain(), Op0, DAG);
23689 DAG.ReplaceAllUsesOfValueWith(Op0.getValue(1), FILDChain.getValue(1));
23696 // Optimize RES, EFLAGS = X86ISD::ADC LHS, RHS, EFLAGS
23697 static SDValue PerformADCCombine(SDNode *N, SelectionDAG &DAG,
23698 X86TargetLowering::DAGCombinerInfo &DCI) {
23699 // If the LHS and RHS of the ADC node are zero, then it can't overflow and
23700 // the result is either zero or one (depending on the input carry bit).
23701 // Strength reduce this down to a "set on carry" aka SETCC_CARRY&1.
23702 if (X86::isZeroNode(N->getOperand(0)) &&
23703 X86::isZeroNode(N->getOperand(1)) &&
23704 // We don't have a good way to replace an EFLAGS use, so only do this when
23706 SDValue(N, 1).use_empty()) {
23708 EVT VT = N->getValueType(0);
23709 SDValue CarryOut = DAG.getConstant(0, N->getValueType(1));
23710 SDValue Res1 = DAG.getNode(ISD::AND, DL, VT,
23711 DAG.getNode(X86ISD::SETCC_CARRY, DL, VT,
23712 DAG.getConstant(X86::COND_B,MVT::i8),
23714 DAG.getConstant(1, VT));
23715 return DCI.CombineTo(N, Res1, CarryOut);
23721 // fold (add Y, (sete X, 0)) -> adc 0, Y
23722 // (add Y, (setne X, 0)) -> sbb -1, Y
23723 // (sub (sete X, 0), Y) -> sbb 0, Y
23724 // (sub (setne X, 0), Y) -> adc -1, Y
23725 static SDValue OptimizeConditionalInDecrement(SDNode *N, SelectionDAG &DAG) {
23728 // Look through ZExts.
23729 SDValue Ext = N->getOperand(N->getOpcode() == ISD::SUB ? 1 : 0);
23730 if (Ext.getOpcode() != ISD::ZERO_EXTEND || !Ext.hasOneUse())
23733 SDValue SetCC = Ext.getOperand(0);
23734 if (SetCC.getOpcode() != X86ISD::SETCC || !SetCC.hasOneUse())
23737 X86::CondCode CC = (X86::CondCode)SetCC.getConstantOperandVal(0);
23738 if (CC != X86::COND_E && CC != X86::COND_NE)
23741 SDValue Cmp = SetCC.getOperand(1);
23742 if (Cmp.getOpcode() != X86ISD::CMP || !Cmp.hasOneUse() ||
23743 !X86::isZeroNode(Cmp.getOperand(1)) ||
23744 !Cmp.getOperand(0).getValueType().isInteger())
23747 SDValue CmpOp0 = Cmp.getOperand(0);
23748 SDValue NewCmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32, CmpOp0,
23749 DAG.getConstant(1, CmpOp0.getValueType()));
23751 SDValue OtherVal = N->getOperand(N->getOpcode() == ISD::SUB ? 0 : 1);
23752 if (CC == X86::COND_NE)
23753 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::ADC : X86ISD::SBB,
23754 DL, OtherVal.getValueType(), OtherVal,
23755 DAG.getConstant(-1ULL, OtherVal.getValueType()), NewCmp);
23756 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::SBB : X86ISD::ADC,
23757 DL, OtherVal.getValueType(), OtherVal,
23758 DAG.getConstant(0, OtherVal.getValueType()), NewCmp);
23761 /// PerformADDCombine - Do target-specific dag combines on integer adds.
23762 static SDValue PerformAddCombine(SDNode *N, SelectionDAG &DAG,
23763 const X86Subtarget *Subtarget) {
23764 EVT VT = N->getValueType(0);
23765 SDValue Op0 = N->getOperand(0);
23766 SDValue Op1 = N->getOperand(1);
23768 // Try to synthesize horizontal adds from adds of shuffles.
23769 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) ||
23770 (Subtarget->hasInt256() && (VT == MVT::v16i16 || VT == MVT::v8i32))) &&
23771 isHorizontalBinOp(Op0, Op1, true))
23772 return DAG.getNode(X86ISD::HADD, SDLoc(N), VT, Op0, Op1);
23774 return OptimizeConditionalInDecrement(N, DAG);
23777 static SDValue PerformSubCombine(SDNode *N, SelectionDAG &DAG,
23778 const X86Subtarget *Subtarget) {
23779 SDValue Op0 = N->getOperand(0);
23780 SDValue Op1 = N->getOperand(1);
23782 // X86 can't encode an immediate LHS of a sub. See if we can push the
23783 // negation into a preceding instruction.
23784 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op0)) {
23785 // If the RHS of the sub is a XOR with one use and a constant, invert the
23786 // immediate. Then add one to the LHS of the sub so we can turn
23787 // X-Y -> X+~Y+1, saving one register.
23788 if (Op1->hasOneUse() && Op1.getOpcode() == ISD::XOR &&
23789 isa<ConstantSDNode>(Op1.getOperand(1))) {
23790 APInt XorC = cast<ConstantSDNode>(Op1.getOperand(1))->getAPIntValue();
23791 EVT VT = Op0.getValueType();
23792 SDValue NewXor = DAG.getNode(ISD::XOR, SDLoc(Op1), VT,
23794 DAG.getConstant(~XorC, VT));
23795 return DAG.getNode(ISD::ADD, SDLoc(N), VT, NewXor,
23796 DAG.getConstant(C->getAPIntValue()+1, VT));
23800 // Try to synthesize horizontal adds from adds of shuffles.
23801 EVT VT = N->getValueType(0);
23802 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) ||
23803 (Subtarget->hasInt256() && (VT == MVT::v16i16 || VT == MVT::v8i32))) &&
23804 isHorizontalBinOp(Op0, Op1, true))
23805 return DAG.getNode(X86ISD::HSUB, SDLoc(N), VT, Op0, Op1);
23807 return OptimizeConditionalInDecrement(N, DAG);
23810 /// performVZEXTCombine - Performs build vector combines
23811 static SDValue performVZEXTCombine(SDNode *N, SelectionDAG &DAG,
23812 TargetLowering::DAGCombinerInfo &DCI,
23813 const X86Subtarget *Subtarget) {
23814 // (vzext (bitcast (vzext (x)) -> (vzext x)
23815 SDValue In = N->getOperand(0);
23816 while (In.getOpcode() == ISD::BITCAST)
23817 In = In.getOperand(0);
23819 if (In.getOpcode() != X86ISD::VZEXT)
23822 return DAG.getNode(X86ISD::VZEXT, SDLoc(N), N->getValueType(0),
23826 SDValue X86TargetLowering::PerformDAGCombine(SDNode *N,
23827 DAGCombinerInfo &DCI) const {
23828 SelectionDAG &DAG = DCI.DAG;
23829 switch (N->getOpcode()) {
23831 case ISD::EXTRACT_VECTOR_ELT:
23832 return PerformEXTRACT_VECTOR_ELTCombine(N, DAG, DCI);
23834 case ISD::SELECT: return PerformSELECTCombine(N, DAG, DCI, Subtarget);
23835 case X86ISD::CMOV: return PerformCMOVCombine(N, DAG, DCI, Subtarget);
23836 case ISD::ADD: return PerformAddCombine(N, DAG, Subtarget);
23837 case ISD::SUB: return PerformSubCombine(N, DAG, Subtarget);
23838 case X86ISD::ADC: return PerformADCCombine(N, DAG, DCI);
23839 case ISD::MUL: return PerformMulCombine(N, DAG, DCI);
23842 case ISD::SRL: return PerformShiftCombine(N, DAG, DCI, Subtarget);
23843 case ISD::AND: return PerformAndCombine(N, DAG, DCI, Subtarget);
23844 case ISD::OR: return PerformOrCombine(N, DAG, DCI, Subtarget);
23845 case ISD::XOR: return PerformXorCombine(N, DAG, DCI, Subtarget);
23846 case ISD::LOAD: return PerformLOADCombine(N, DAG, DCI, Subtarget);
23847 case ISD::STORE: return PerformSTORECombine(N, DAG, Subtarget);
23848 case ISD::SINT_TO_FP: return PerformSINT_TO_FPCombine(N, DAG, this);
23849 case ISD::FADD: return PerformFADDCombine(N, DAG, Subtarget);
23850 case ISD::FSUB: return PerformFSUBCombine(N, DAG, Subtarget);
23852 case X86ISD::FOR: return PerformFORCombine(N, DAG);
23854 case X86ISD::FMAX: return PerformFMinFMaxCombine(N, DAG);
23855 case X86ISD::FAND: return PerformFANDCombine(N, DAG);
23856 case X86ISD::FANDN: return PerformFANDNCombine(N, DAG);
23857 case X86ISD::BT: return PerformBTCombine(N, DAG, DCI);
23858 case X86ISD::VZEXT_MOVL: return PerformVZEXT_MOVLCombine(N, DAG);
23859 case ISD::ANY_EXTEND:
23860 case ISD::ZERO_EXTEND: return PerformZExtCombine(N, DAG, DCI, Subtarget);
23861 case ISD::SIGN_EXTEND: return PerformSExtCombine(N, DAG, DCI, Subtarget);
23862 case ISD::SIGN_EXTEND_INREG:
23863 return PerformSIGN_EXTEND_INREGCombine(N, DAG, Subtarget);
23864 case ISD::TRUNCATE: return PerformTruncateCombine(N, DAG,DCI,Subtarget);
23865 case ISD::SETCC: return PerformISDSETCCCombine(N, DAG, Subtarget);
23866 case X86ISD::SETCC: return PerformSETCCCombine(N, DAG, DCI, Subtarget);
23867 case X86ISD::BRCOND: return PerformBrCondCombine(N, DAG, DCI, Subtarget);
23868 case X86ISD::VZEXT: return performVZEXTCombine(N, DAG, DCI, Subtarget);
23869 case X86ISD::SHUFP: // Handle all target specific shuffles
23870 case X86ISD::PALIGNR:
23871 case X86ISD::UNPCKH:
23872 case X86ISD::UNPCKL:
23873 case X86ISD::MOVHLPS:
23874 case X86ISD::MOVLHPS:
23875 case X86ISD::PSHUFB:
23876 case X86ISD::PSHUFD:
23877 case X86ISD::PSHUFHW:
23878 case X86ISD::PSHUFLW:
23879 case X86ISD::MOVSS:
23880 case X86ISD::MOVSD:
23881 case X86ISD::VPERMILPI:
23882 case X86ISD::VPERM2X128:
23883 case ISD::VECTOR_SHUFFLE: return PerformShuffleCombine(N, DAG, DCI,Subtarget);
23884 case ISD::FMA: return PerformFMACombine(N, DAG, Subtarget);
23885 case ISD::INTRINSIC_WO_CHAIN:
23886 return PerformINTRINSIC_WO_CHAINCombine(N, DAG, Subtarget);
23887 case X86ISD::INSERTPS:
23888 return PerformINSERTPSCombine(N, DAG, Subtarget);
23889 case ISD::BUILD_VECTOR: return PerformBUILD_VECTORCombine(N, DAG, Subtarget);
23895 /// isTypeDesirableForOp - Return true if the target has native support for
23896 /// the specified value type and it is 'desirable' to use the type for the
23897 /// given node type. e.g. On x86 i16 is legal, but undesirable since i16
23898 /// instruction encodings are longer and some i16 instructions are slow.
23899 bool X86TargetLowering::isTypeDesirableForOp(unsigned Opc, EVT VT) const {
23900 if (!isTypeLegal(VT))
23902 if (VT != MVT::i16)
23909 case ISD::SIGN_EXTEND:
23910 case ISD::ZERO_EXTEND:
23911 case ISD::ANY_EXTEND:
23924 /// IsDesirableToPromoteOp - This method query the target whether it is
23925 /// beneficial for dag combiner to promote the specified node. If true, it
23926 /// should return the desired promotion type by reference.
23927 bool X86TargetLowering::IsDesirableToPromoteOp(SDValue Op, EVT &PVT) const {
23928 EVT VT = Op.getValueType();
23929 if (VT != MVT::i16)
23932 bool Promote = false;
23933 bool Commute = false;
23934 switch (Op.getOpcode()) {
23937 LoadSDNode *LD = cast<LoadSDNode>(Op);
23938 // If the non-extending load has a single use and it's not live out, then it
23939 // might be folded.
23940 if (LD->getExtensionType() == ISD::NON_EXTLOAD /*&&
23941 Op.hasOneUse()*/) {
23942 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
23943 UE = Op.getNode()->use_end(); UI != UE; ++UI) {
23944 // The only case where we'd want to promote LOAD (rather then it being
23945 // promoted as an operand is when it's only use is liveout.
23946 if (UI->getOpcode() != ISD::CopyToReg)
23953 case ISD::SIGN_EXTEND:
23954 case ISD::ZERO_EXTEND:
23955 case ISD::ANY_EXTEND:
23960 SDValue N0 = Op.getOperand(0);
23961 // Look out for (store (shl (load), x)).
23962 if (MayFoldLoad(N0) && MayFoldIntoStore(Op))
23975 SDValue N0 = Op.getOperand(0);
23976 SDValue N1 = Op.getOperand(1);
23977 if (!Commute && MayFoldLoad(N1))
23979 // Avoid disabling potential load folding opportunities.
23980 if (MayFoldLoad(N0) && (!isa<ConstantSDNode>(N1) || MayFoldIntoStore(Op)))
23982 if (MayFoldLoad(N1) && (!isa<ConstantSDNode>(N0) || MayFoldIntoStore(Op)))
23992 //===----------------------------------------------------------------------===//
23993 // X86 Inline Assembly Support
23994 //===----------------------------------------------------------------------===//
23997 // Helper to match a string separated by whitespace.
23998 bool matchAsmImpl(StringRef s, ArrayRef<const StringRef *> args) {
23999 s = s.substr(s.find_first_not_of(" \t")); // Skip leading whitespace.
24001 for (unsigned i = 0, e = args.size(); i != e; ++i) {
24002 StringRef piece(*args[i]);
24003 if (!s.startswith(piece)) // Check if the piece matches.
24006 s = s.substr(piece.size());
24007 StringRef::size_type pos = s.find_first_not_of(" \t");
24008 if (pos == 0) // We matched a prefix.
24016 const VariadicFunction1<bool, StringRef, StringRef, matchAsmImpl> matchAsm={};
24019 static bool clobbersFlagRegisters(const SmallVector<StringRef, 4> &AsmPieces) {
24021 if (AsmPieces.size() == 3 || AsmPieces.size() == 4) {
24022 if (std::count(AsmPieces.begin(), AsmPieces.end(), "~{cc}") &&
24023 std::count(AsmPieces.begin(), AsmPieces.end(), "~{flags}") &&
24024 std::count(AsmPieces.begin(), AsmPieces.end(), "~{fpsr}")) {
24026 if (AsmPieces.size() == 3)
24028 else if (std::count(AsmPieces.begin(), AsmPieces.end(), "~{dirflag}"))
24035 bool X86TargetLowering::ExpandInlineAsm(CallInst *CI) const {
24036 InlineAsm *IA = cast<InlineAsm>(CI->getCalledValue());
24038 std::string AsmStr = IA->getAsmString();
24040 IntegerType *Ty = dyn_cast<IntegerType>(CI->getType());
24041 if (!Ty || Ty->getBitWidth() % 16 != 0)
24044 // TODO: should remove alternatives from the asmstring: "foo {a|b}" -> "foo a"
24045 SmallVector<StringRef, 4> AsmPieces;
24046 SplitString(AsmStr, AsmPieces, ";\n");
24048 switch (AsmPieces.size()) {
24049 default: return false;
24051 // FIXME: this should verify that we are targeting a 486 or better. If not,
24052 // we will turn this bswap into something that will be lowered to logical
24053 // ops instead of emitting the bswap asm. For now, we don't support 486 or
24054 // lower so don't worry about this.
24056 if (matchAsm(AsmPieces[0], "bswap", "$0") ||
24057 matchAsm(AsmPieces[0], "bswapl", "$0") ||
24058 matchAsm(AsmPieces[0], "bswapq", "$0") ||
24059 matchAsm(AsmPieces[0], "bswap", "${0:q}") ||
24060 matchAsm(AsmPieces[0], "bswapl", "${0:q}") ||
24061 matchAsm(AsmPieces[0], "bswapq", "${0:q}")) {
24062 // No need to check constraints, nothing other than the equivalent of
24063 // "=r,0" would be valid here.
24064 return IntrinsicLowering::LowerToByteSwap(CI);
24067 // rorw $$8, ${0:w} --> llvm.bswap.i16
24068 if (CI->getType()->isIntegerTy(16) &&
24069 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 &&
24070 (matchAsm(AsmPieces[0], "rorw", "$$8,", "${0:w}") ||
24071 matchAsm(AsmPieces[0], "rolw", "$$8,", "${0:w}"))) {
24073 const std::string &ConstraintsStr = IA->getConstraintString();
24074 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
24075 array_pod_sort(AsmPieces.begin(), AsmPieces.end());
24076 if (clobbersFlagRegisters(AsmPieces))
24077 return IntrinsicLowering::LowerToByteSwap(CI);
24081 if (CI->getType()->isIntegerTy(32) &&
24082 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 &&
24083 matchAsm(AsmPieces[0], "rorw", "$$8,", "${0:w}") &&
24084 matchAsm(AsmPieces[1], "rorl", "$$16,", "$0") &&
24085 matchAsm(AsmPieces[2], "rorw", "$$8,", "${0:w}")) {
24087 const std::string &ConstraintsStr = IA->getConstraintString();
24088 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
24089 array_pod_sort(AsmPieces.begin(), AsmPieces.end());
24090 if (clobbersFlagRegisters(AsmPieces))
24091 return IntrinsicLowering::LowerToByteSwap(CI);
24094 if (CI->getType()->isIntegerTy(64)) {
24095 InlineAsm::ConstraintInfoVector Constraints = IA->ParseConstraints();
24096 if (Constraints.size() >= 2 &&
24097 Constraints[0].Codes.size() == 1 && Constraints[0].Codes[0] == "A" &&
24098 Constraints[1].Codes.size() == 1 && Constraints[1].Codes[0] == "0") {
24099 // bswap %eax / bswap %edx / xchgl %eax, %edx -> llvm.bswap.i64
24100 if (matchAsm(AsmPieces[0], "bswap", "%eax") &&
24101 matchAsm(AsmPieces[1], "bswap", "%edx") &&
24102 matchAsm(AsmPieces[2], "xchgl", "%eax,", "%edx"))
24103 return IntrinsicLowering::LowerToByteSwap(CI);
24111 /// getConstraintType - Given a constraint letter, return the type of
24112 /// constraint it is for this target.
24113 X86TargetLowering::ConstraintType
24114 X86TargetLowering::getConstraintType(const std::string &Constraint) const {
24115 if (Constraint.size() == 1) {
24116 switch (Constraint[0]) {
24127 return C_RegisterClass;
24151 return TargetLowering::getConstraintType(Constraint);
24154 /// Examine constraint type and operand type and determine a weight value.
24155 /// This object must already have been set up with the operand type
24156 /// and the current alternative constraint selected.
24157 TargetLowering::ConstraintWeight
24158 X86TargetLowering::getSingleConstraintMatchWeight(
24159 AsmOperandInfo &info, const char *constraint) const {
24160 ConstraintWeight weight = CW_Invalid;
24161 Value *CallOperandVal = info.CallOperandVal;
24162 // If we don't have a value, we can't do a match,
24163 // but allow it at the lowest weight.
24164 if (!CallOperandVal)
24166 Type *type = CallOperandVal->getType();
24167 // Look at the constraint type.
24168 switch (*constraint) {
24170 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
24181 if (CallOperandVal->getType()->isIntegerTy())
24182 weight = CW_SpecificReg;
24187 if (type->isFloatingPointTy())
24188 weight = CW_SpecificReg;
24191 if (type->isX86_MMXTy() && Subtarget->hasMMX())
24192 weight = CW_SpecificReg;
24196 if (((type->getPrimitiveSizeInBits() == 128) && Subtarget->hasSSE1()) ||
24197 ((type->getPrimitiveSizeInBits() == 256) && Subtarget->hasFp256()))
24198 weight = CW_Register;
24201 if (ConstantInt *C = dyn_cast<ConstantInt>(info.CallOperandVal)) {
24202 if (C->getZExtValue() <= 31)
24203 weight = CW_Constant;
24207 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
24208 if (C->getZExtValue() <= 63)
24209 weight = CW_Constant;
24213 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
24214 if ((C->getSExtValue() >= -0x80) && (C->getSExtValue() <= 0x7f))
24215 weight = CW_Constant;
24219 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
24220 if ((C->getZExtValue() == 0xff) || (C->getZExtValue() == 0xffff))
24221 weight = CW_Constant;
24225 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
24226 if (C->getZExtValue() <= 3)
24227 weight = CW_Constant;
24231 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
24232 if (C->getZExtValue() <= 0xff)
24233 weight = CW_Constant;
24238 if (dyn_cast<ConstantFP>(CallOperandVal)) {
24239 weight = CW_Constant;
24243 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
24244 if ((C->getSExtValue() >= -0x80000000LL) &&
24245 (C->getSExtValue() <= 0x7fffffffLL))
24246 weight = CW_Constant;
24250 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
24251 if (C->getZExtValue() <= 0xffffffff)
24252 weight = CW_Constant;
24259 /// LowerXConstraint - try to replace an X constraint, which matches anything,
24260 /// with another that has more specific requirements based on the type of the
24261 /// corresponding operand.
24262 const char *X86TargetLowering::
24263 LowerXConstraint(EVT ConstraintVT) const {
24264 // FP X constraints get lowered to SSE1/2 registers if available, otherwise
24265 // 'f' like normal targets.
24266 if (ConstraintVT.isFloatingPoint()) {
24267 if (Subtarget->hasSSE2())
24269 if (Subtarget->hasSSE1())
24273 return TargetLowering::LowerXConstraint(ConstraintVT);
24276 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
24277 /// vector. If it is invalid, don't add anything to Ops.
24278 void X86TargetLowering::LowerAsmOperandForConstraint(SDValue Op,
24279 std::string &Constraint,
24280 std::vector<SDValue>&Ops,
24281 SelectionDAG &DAG) const {
24284 // Only support length 1 constraints for now.
24285 if (Constraint.length() > 1) return;
24287 char ConstraintLetter = Constraint[0];
24288 switch (ConstraintLetter) {
24291 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
24292 if (C->getZExtValue() <= 31) {
24293 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
24299 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
24300 if (C->getZExtValue() <= 63) {
24301 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
24307 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
24308 if (isInt<8>(C->getSExtValue())) {
24309 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
24315 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
24316 if (C->getZExtValue() <= 255) {
24317 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
24323 // 32-bit signed value
24324 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
24325 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
24326 C->getSExtValue())) {
24327 // Widen to 64 bits here to get it sign extended.
24328 Result = DAG.getTargetConstant(C->getSExtValue(), MVT::i64);
24331 // FIXME gcc accepts some relocatable values here too, but only in certain
24332 // memory models; it's complicated.
24337 // 32-bit unsigned value
24338 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
24339 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
24340 C->getZExtValue())) {
24341 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
24345 // FIXME gcc accepts some relocatable values here too, but only in certain
24346 // memory models; it's complicated.
24350 // Literal immediates are always ok.
24351 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op)) {
24352 // Widen to 64 bits here to get it sign extended.
24353 Result = DAG.getTargetConstant(CST->getSExtValue(), MVT::i64);
24357 // In any sort of PIC mode addresses need to be computed at runtime by
24358 // adding in a register or some sort of table lookup. These can't
24359 // be used as immediates.
24360 if (Subtarget->isPICStyleGOT() || Subtarget->isPICStyleStubPIC())
24363 // If we are in non-pic codegen mode, we allow the address of a global (with
24364 // an optional displacement) to be used with 'i'.
24365 GlobalAddressSDNode *GA = nullptr;
24366 int64_t Offset = 0;
24368 // Match either (GA), (GA+C), (GA+C1+C2), etc.
24370 if ((GA = dyn_cast<GlobalAddressSDNode>(Op))) {
24371 Offset += GA->getOffset();
24373 } else if (Op.getOpcode() == ISD::ADD) {
24374 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
24375 Offset += C->getZExtValue();
24376 Op = Op.getOperand(0);
24379 } else if (Op.getOpcode() == ISD::SUB) {
24380 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
24381 Offset += -C->getZExtValue();
24382 Op = Op.getOperand(0);
24387 // Otherwise, this isn't something we can handle, reject it.
24391 const GlobalValue *GV = GA->getGlobal();
24392 // If we require an extra load to get this address, as in PIC mode, we
24393 // can't accept it.
24394 if (isGlobalStubReference(
24395 Subtarget->ClassifyGlobalReference(GV, DAG.getTarget())))
24398 Result = DAG.getTargetGlobalAddress(GV, SDLoc(Op),
24399 GA->getValueType(0), Offset);
24404 if (Result.getNode()) {
24405 Ops.push_back(Result);
24408 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
24411 std::pair<unsigned, const TargetRegisterClass*>
24412 X86TargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
24414 // First, see if this is a constraint that directly corresponds to an LLVM
24416 if (Constraint.size() == 1) {
24417 // GCC Constraint Letters
24418 switch (Constraint[0]) {
24420 // TODO: Slight differences here in allocation order and leaving
24421 // RIP in the class. Do they matter any more here than they do
24422 // in the normal allocation?
24423 case 'q': // GENERAL_REGS in 64-bit mode, Q_REGS in 32-bit mode.
24424 if (Subtarget->is64Bit()) {
24425 if (VT == MVT::i32 || VT == MVT::f32)
24426 return std::make_pair(0U, &X86::GR32RegClass);
24427 if (VT == MVT::i16)
24428 return std::make_pair(0U, &X86::GR16RegClass);
24429 if (VT == MVT::i8 || VT == MVT::i1)
24430 return std::make_pair(0U, &X86::GR8RegClass);
24431 if (VT == MVT::i64 || VT == MVT::f64)
24432 return std::make_pair(0U, &X86::GR64RegClass);
24435 // 32-bit fallthrough
24436 case 'Q': // Q_REGS
24437 if (VT == MVT::i32 || VT == MVT::f32)
24438 return std::make_pair(0U, &X86::GR32_ABCDRegClass);
24439 if (VT == MVT::i16)
24440 return std::make_pair(0U, &X86::GR16_ABCDRegClass);
24441 if (VT == MVT::i8 || VT == MVT::i1)
24442 return std::make_pair(0U, &X86::GR8_ABCD_LRegClass);
24443 if (VT == MVT::i64)
24444 return std::make_pair(0U, &X86::GR64_ABCDRegClass);
24446 case 'r': // GENERAL_REGS
24447 case 'l': // INDEX_REGS
24448 if (VT == MVT::i8 || VT == MVT::i1)
24449 return std::make_pair(0U, &X86::GR8RegClass);
24450 if (VT == MVT::i16)
24451 return std::make_pair(0U, &X86::GR16RegClass);
24452 if (VT == MVT::i32 || VT == MVT::f32 || !Subtarget->is64Bit())
24453 return std::make_pair(0U, &X86::GR32RegClass);
24454 return std::make_pair(0U, &X86::GR64RegClass);
24455 case 'R': // LEGACY_REGS
24456 if (VT == MVT::i8 || VT == MVT::i1)
24457 return std::make_pair(0U, &X86::GR8_NOREXRegClass);
24458 if (VT == MVT::i16)
24459 return std::make_pair(0U, &X86::GR16_NOREXRegClass);
24460 if (VT == MVT::i32 || !Subtarget->is64Bit())
24461 return std::make_pair(0U, &X86::GR32_NOREXRegClass);
24462 return std::make_pair(0U, &X86::GR64_NOREXRegClass);
24463 case 'f': // FP Stack registers.
24464 // If SSE is enabled for this VT, use f80 to ensure the isel moves the
24465 // value to the correct fpstack register class.
24466 if (VT == MVT::f32 && !isScalarFPTypeInSSEReg(VT))
24467 return std::make_pair(0U, &X86::RFP32RegClass);
24468 if (VT == MVT::f64 && !isScalarFPTypeInSSEReg(VT))
24469 return std::make_pair(0U, &X86::RFP64RegClass);
24470 return std::make_pair(0U, &X86::RFP80RegClass);
24471 case 'y': // MMX_REGS if MMX allowed.
24472 if (!Subtarget->hasMMX()) break;
24473 return std::make_pair(0U, &X86::VR64RegClass);
24474 case 'Y': // SSE_REGS if SSE2 allowed
24475 if (!Subtarget->hasSSE2()) break;
24477 case 'x': // SSE_REGS if SSE1 allowed or AVX_REGS if AVX allowed
24478 if (!Subtarget->hasSSE1()) break;
24480 switch (VT.SimpleTy) {
24482 // Scalar SSE types.
24485 return std::make_pair(0U, &X86::FR32RegClass);
24488 return std::make_pair(0U, &X86::FR64RegClass);
24496 return std::make_pair(0U, &X86::VR128RegClass);
24504 return std::make_pair(0U, &X86::VR256RegClass);
24509 return std::make_pair(0U, &X86::VR512RegClass);
24515 // Use the default implementation in TargetLowering to convert the register
24516 // constraint into a member of a register class.
24517 std::pair<unsigned, const TargetRegisterClass*> Res;
24518 Res = TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
24520 // Not found as a standard register?
24522 // Map st(0) -> st(7) -> ST0
24523 if (Constraint.size() == 7 && Constraint[0] == '{' &&
24524 tolower(Constraint[1]) == 's' &&
24525 tolower(Constraint[2]) == 't' &&
24526 Constraint[3] == '(' &&
24527 (Constraint[4] >= '0' && Constraint[4] <= '7') &&
24528 Constraint[5] == ')' &&
24529 Constraint[6] == '}') {
24531 Res.first = X86::FP0+Constraint[4]-'0';
24532 Res.second = &X86::RFP80RegClass;
24536 // GCC allows "st(0)" to be called just plain "st".
24537 if (StringRef("{st}").equals_lower(Constraint)) {
24538 Res.first = X86::FP0;
24539 Res.second = &X86::RFP80RegClass;
24544 if (StringRef("{flags}").equals_lower(Constraint)) {
24545 Res.first = X86::EFLAGS;
24546 Res.second = &X86::CCRRegClass;
24550 // 'A' means EAX + EDX.
24551 if (Constraint == "A") {
24552 Res.first = X86::EAX;
24553 Res.second = &X86::GR32_ADRegClass;
24559 // Otherwise, check to see if this is a register class of the wrong value
24560 // type. For example, we want to map "{ax},i32" -> {eax}, we don't want it to
24561 // turn into {ax},{dx}.
24562 if (Res.second->hasType(VT))
24563 return Res; // Correct type already, nothing to do.
24565 // All of the single-register GCC register classes map their values onto
24566 // 16-bit register pieces "ax","dx","cx","bx","si","di","bp","sp". If we
24567 // really want an 8-bit or 32-bit register, map to the appropriate register
24568 // class and return the appropriate register.
24569 if (Res.second == &X86::GR16RegClass) {
24570 if (VT == MVT::i8 || VT == MVT::i1) {
24571 unsigned DestReg = 0;
24572 switch (Res.first) {
24574 case X86::AX: DestReg = X86::AL; break;
24575 case X86::DX: DestReg = X86::DL; break;
24576 case X86::CX: DestReg = X86::CL; break;
24577 case X86::BX: DestReg = X86::BL; break;
24580 Res.first = DestReg;
24581 Res.second = &X86::GR8RegClass;
24583 } else if (VT == MVT::i32 || VT == MVT::f32) {
24584 unsigned DestReg = 0;
24585 switch (Res.first) {
24587 case X86::AX: DestReg = X86::EAX; break;
24588 case X86::DX: DestReg = X86::EDX; break;
24589 case X86::CX: DestReg = X86::ECX; break;
24590 case X86::BX: DestReg = X86::EBX; break;
24591 case X86::SI: DestReg = X86::ESI; break;
24592 case X86::DI: DestReg = X86::EDI; break;
24593 case X86::BP: DestReg = X86::EBP; break;
24594 case X86::SP: DestReg = X86::ESP; break;
24597 Res.first = DestReg;
24598 Res.second = &X86::GR32RegClass;
24600 } else if (VT == MVT::i64 || VT == MVT::f64) {
24601 unsigned DestReg = 0;
24602 switch (Res.first) {
24604 case X86::AX: DestReg = X86::RAX; break;
24605 case X86::DX: DestReg = X86::RDX; break;
24606 case X86::CX: DestReg = X86::RCX; break;
24607 case X86::BX: DestReg = X86::RBX; break;
24608 case X86::SI: DestReg = X86::RSI; break;
24609 case X86::DI: DestReg = X86::RDI; break;
24610 case X86::BP: DestReg = X86::RBP; break;
24611 case X86::SP: DestReg = X86::RSP; break;
24614 Res.first = DestReg;
24615 Res.second = &X86::GR64RegClass;
24618 } else if (Res.second == &X86::FR32RegClass ||
24619 Res.second == &X86::FR64RegClass ||
24620 Res.second == &X86::VR128RegClass ||
24621 Res.second == &X86::VR256RegClass ||
24622 Res.second == &X86::FR32XRegClass ||
24623 Res.second == &X86::FR64XRegClass ||
24624 Res.second == &X86::VR128XRegClass ||
24625 Res.second == &X86::VR256XRegClass ||
24626 Res.second == &X86::VR512RegClass) {
24627 // Handle references to XMM physical registers that got mapped into the
24628 // wrong class. This can happen with constraints like {xmm0} where the
24629 // target independent register mapper will just pick the first match it can
24630 // find, ignoring the required type.
24632 if (VT == MVT::f32 || VT == MVT::i32)
24633 Res.second = &X86::FR32RegClass;
24634 else if (VT == MVT::f64 || VT == MVT::i64)
24635 Res.second = &X86::FR64RegClass;
24636 else if (X86::VR128RegClass.hasType(VT))
24637 Res.second = &X86::VR128RegClass;
24638 else if (X86::VR256RegClass.hasType(VT))
24639 Res.second = &X86::VR256RegClass;
24640 else if (X86::VR512RegClass.hasType(VT))
24641 Res.second = &X86::VR512RegClass;
24647 int X86TargetLowering::getScalingFactorCost(const AddrMode &AM,
24649 // Scaling factors are not free at all.
24650 // An indexed folded instruction, i.e., inst (reg1, reg2, scale),
24651 // will take 2 allocations in the out of order engine instead of 1
24652 // for plain addressing mode, i.e. inst (reg1).
24654 // vaddps (%rsi,%drx), %ymm0, %ymm1
24655 // Requires two allocations (one for the load, one for the computation)
24657 // vaddps (%rsi), %ymm0, %ymm1
24658 // Requires just 1 allocation, i.e., freeing allocations for other operations
24659 // and having less micro operations to execute.
24661 // For some X86 architectures, this is even worse because for instance for
24662 // stores, the complex addressing mode forces the instruction to use the
24663 // "load" ports instead of the dedicated "store" port.
24664 // E.g., on Haswell:
24665 // vmovaps %ymm1, (%r8, %rdi) can use port 2 or 3.
24666 // vmovaps %ymm1, (%r8) can use port 2, 3, or 7.
24667 if (isLegalAddressingMode(AM, Ty))
24668 // Scale represents reg2 * scale, thus account for 1
24669 // as soon as we use a second register.
24670 return AM.Scale != 0;
24674 bool X86TargetLowering::isTargetFTOL() const {
24675 return Subtarget->isTargetKnownWindowsMSVC() && !Subtarget->is64Bit();