1 //===-- X86ISelLowering.cpp - X86 DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that X86 uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #include "X86ISelLowering.h"
16 #include "Utils/X86ShuffleDecode.h"
17 #include "X86CallingConv.h"
18 #include "X86FrameLowering.h"
19 #include "X86InstrBuilder.h"
20 #include "X86MachineFunctionInfo.h"
21 #include "X86TargetMachine.h"
22 #include "X86TargetObjectFile.h"
23 #include "llvm/ADT/SmallBitVector.h"
24 #include "llvm/ADT/SmallSet.h"
25 #include "llvm/ADT/Statistic.h"
26 #include "llvm/ADT/StringExtras.h"
27 #include "llvm/ADT/StringSwitch.h"
28 #include "llvm/Analysis/LibCallSemantics.h"
29 #include "llvm/CodeGen/IntrinsicLowering.h"
30 #include "llvm/CodeGen/MachineFrameInfo.h"
31 #include "llvm/CodeGen/MachineFunction.h"
32 #include "llvm/CodeGen/MachineInstrBuilder.h"
33 #include "llvm/CodeGen/MachineJumpTableInfo.h"
34 #include "llvm/CodeGen/MachineModuleInfo.h"
35 #include "llvm/CodeGen/MachineRegisterInfo.h"
36 #include "llvm/CodeGen/WinEHFuncInfo.h"
37 #include "llvm/IR/CallSite.h"
38 #include "llvm/IR/CallingConv.h"
39 #include "llvm/IR/Constants.h"
40 #include "llvm/IR/DerivedTypes.h"
41 #include "llvm/IR/Function.h"
42 #include "llvm/IR/GlobalAlias.h"
43 #include "llvm/IR/GlobalVariable.h"
44 #include "llvm/IR/Instructions.h"
45 #include "llvm/IR/Intrinsics.h"
46 #include "llvm/MC/MCAsmInfo.h"
47 #include "llvm/MC/MCContext.h"
48 #include "llvm/MC/MCExpr.h"
49 #include "llvm/MC/MCSymbol.h"
50 #include "llvm/Support/CommandLine.h"
51 #include "llvm/Support/Debug.h"
52 #include "llvm/Support/ErrorHandling.h"
53 #include "llvm/Support/MathExtras.h"
54 #include "llvm/Target/TargetOptions.h"
55 #include "X86IntrinsicsInfo.h"
61 #define DEBUG_TYPE "x86-isel"
63 STATISTIC(NumTailCalls, "Number of tail calls");
65 static cl::opt<bool> ExperimentalVectorWideningLegalization(
66 "x86-experimental-vector-widening-legalization", cl::init(false),
67 cl::desc("Enable an experimental vector type legalization through widening "
68 "rather than promotion."),
71 X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM,
72 const X86Subtarget &STI)
73 : TargetLowering(TM), Subtarget(&STI) {
74 X86ScalarSSEf64 = Subtarget->hasSSE2();
75 X86ScalarSSEf32 = Subtarget->hasSSE1();
76 MVT PtrVT = MVT::getIntegerVT(8 * TM.getPointerSize());
78 // Set up the TargetLowering object.
80 // X86 is weird. It always uses i8 for shift amounts and setcc results.
81 setBooleanContents(ZeroOrOneBooleanContent);
82 // X86-SSE is even stranger. It uses -1 or 0 for vector masks.
83 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
85 // For 64-bit, since we have so many registers, use the ILP scheduler.
86 // For 32-bit, use the register pressure specific scheduling.
87 // For Atom, always use ILP scheduling.
88 if (Subtarget->isAtom())
89 setSchedulingPreference(Sched::ILP);
90 else if (Subtarget->is64Bit())
91 setSchedulingPreference(Sched::ILP);
93 setSchedulingPreference(Sched::RegPressure);
94 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
95 setStackPointerRegisterToSaveRestore(RegInfo->getStackRegister());
97 // Bypass expensive divides on Atom when compiling with O2.
98 if (TM.getOptLevel() >= CodeGenOpt::Default) {
99 if (Subtarget->hasSlowDivide32())
100 addBypassSlowDiv(32, 8);
101 if (Subtarget->hasSlowDivide64() && Subtarget->is64Bit())
102 addBypassSlowDiv(64, 16);
105 if (Subtarget->isTargetKnownWindowsMSVC()) {
106 // Setup Windows compiler runtime calls.
107 setLibcallName(RTLIB::SDIV_I64, "_alldiv");
108 setLibcallName(RTLIB::UDIV_I64, "_aulldiv");
109 setLibcallName(RTLIB::SREM_I64, "_allrem");
110 setLibcallName(RTLIB::UREM_I64, "_aullrem");
111 setLibcallName(RTLIB::MUL_I64, "_allmul");
112 setLibcallCallingConv(RTLIB::SDIV_I64, CallingConv::X86_StdCall);
113 setLibcallCallingConv(RTLIB::UDIV_I64, CallingConv::X86_StdCall);
114 setLibcallCallingConv(RTLIB::SREM_I64, CallingConv::X86_StdCall);
115 setLibcallCallingConv(RTLIB::UREM_I64, CallingConv::X86_StdCall);
116 setLibcallCallingConv(RTLIB::MUL_I64, CallingConv::X86_StdCall);
119 if (Subtarget->isTargetDarwin()) {
120 // Darwin should use _setjmp/_longjmp instead of setjmp/longjmp.
121 setUseUnderscoreSetJmp(false);
122 setUseUnderscoreLongJmp(false);
123 } else if (Subtarget->isTargetWindowsGNU()) {
124 // MS runtime is weird: it exports _setjmp, but longjmp!
125 setUseUnderscoreSetJmp(true);
126 setUseUnderscoreLongJmp(false);
128 setUseUnderscoreSetJmp(true);
129 setUseUnderscoreLongJmp(true);
132 // Set up the register classes.
133 addRegisterClass(MVT::i8, &X86::GR8RegClass);
134 addRegisterClass(MVT::i16, &X86::GR16RegClass);
135 addRegisterClass(MVT::i32, &X86::GR32RegClass);
136 if (Subtarget->is64Bit())
137 addRegisterClass(MVT::i64, &X86::GR64RegClass);
139 for (MVT VT : MVT::integer_valuetypes())
140 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote);
142 // We don't accept any truncstore of integer registers.
143 setTruncStoreAction(MVT::i64, MVT::i32, Expand);
144 setTruncStoreAction(MVT::i64, MVT::i16, Expand);
145 setTruncStoreAction(MVT::i64, MVT::i8 , Expand);
146 setTruncStoreAction(MVT::i32, MVT::i16, Expand);
147 setTruncStoreAction(MVT::i32, MVT::i8 , Expand);
148 setTruncStoreAction(MVT::i16, MVT::i8, Expand);
150 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
152 // SETOEQ and SETUNE require checking two conditions.
153 setCondCodeAction(ISD::SETOEQ, MVT::f32, Expand);
154 setCondCodeAction(ISD::SETOEQ, MVT::f64, Expand);
155 setCondCodeAction(ISD::SETOEQ, MVT::f80, Expand);
156 setCondCodeAction(ISD::SETUNE, MVT::f32, Expand);
157 setCondCodeAction(ISD::SETUNE, MVT::f64, Expand);
158 setCondCodeAction(ISD::SETUNE, MVT::f80, Expand);
160 // Promote all UINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have this
162 setOperationAction(ISD::UINT_TO_FP , MVT::i1 , Promote);
163 setOperationAction(ISD::UINT_TO_FP , MVT::i8 , Promote);
164 setOperationAction(ISD::UINT_TO_FP , MVT::i16 , Promote);
166 if (Subtarget->is64Bit()) {
167 if (!Subtarget->useSoftFloat() && Subtarget->hasAVX512())
168 // f32/f64 are legal, f80 is custom.
169 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Custom);
171 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote);
172 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
173 } else if (!Subtarget->useSoftFloat()) {
174 // We have an algorithm for SSE2->double, and we turn this into a
175 // 64-bit FILD followed by conditional FADD for other targets.
176 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
177 // We have an algorithm for SSE2, and we turn this into a 64-bit
178 // FILD or VCVTUSI2SS/SD for other targets.
179 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Custom);
182 // Promote i1/i8 SINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have
184 setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote);
185 setOperationAction(ISD::SINT_TO_FP , MVT::i8 , Promote);
187 if (!Subtarget->useSoftFloat()) {
188 // SSE has no i16 to fp conversion, only i32
189 if (X86ScalarSSEf32) {
190 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
191 // f32 and f64 cases are Legal, f80 case is not
192 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
194 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Custom);
195 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
198 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
199 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Promote);
202 // Promote i1/i8 FP_TO_SINT to larger FP_TO_SINTS's, as X86 doesn't have
204 setOperationAction(ISD::FP_TO_SINT , MVT::i1 , Promote);
205 setOperationAction(ISD::FP_TO_SINT , MVT::i8 , Promote);
207 if (!Subtarget->useSoftFloat()) {
208 // In 32-bit mode these are custom lowered. In 64-bit mode F32 and F64
209 // are Legal, f80 is custom lowered.
210 setOperationAction(ISD::FP_TO_SINT , MVT::i64 , Custom);
211 setOperationAction(ISD::SINT_TO_FP , MVT::i64 , Custom);
213 if (X86ScalarSSEf32) {
214 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Promote);
215 // f32 and f64 cases are Legal, f80 case is not
216 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
218 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Custom);
219 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
222 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Promote);
223 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Expand);
224 setOperationAction(ISD::FP_TO_SINT , MVT::i64 , Expand);
227 // Handle FP_TO_UINT by promoting the destination to a larger signed
229 setOperationAction(ISD::FP_TO_UINT , MVT::i1 , Promote);
230 setOperationAction(ISD::FP_TO_UINT , MVT::i8 , Promote);
231 setOperationAction(ISD::FP_TO_UINT , MVT::i16 , Promote);
233 if (Subtarget->is64Bit()) {
234 if (!Subtarget->useSoftFloat() && Subtarget->hasAVX512()) {
235 // FP_TO_UINT-i32/i64 is legal for f32/f64, but custom for f80.
236 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Custom);
237 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Custom);
239 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote);
240 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Expand);
242 } else if (!Subtarget->useSoftFloat()) {
243 // Since AVX is a superset of SSE3, only check for SSE here.
244 if (Subtarget->hasSSE1() && !Subtarget->hasSSE3())
245 // Expand FP_TO_UINT into a select.
246 // FIXME: We would like to use a Custom expander here eventually to do
247 // the optimal thing for SSE vs. the default expansion in the legalizer.
248 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Expand);
250 // With AVX512 we can use vcvts[ds]2usi for f32/f64->i32, f80 is custom.
251 // With SSE3 we can use fisttpll to convert to a signed i64; without
252 // SSE, we're stuck with a fistpll.
253 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Custom);
255 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Custom);
258 // TODO: when we have SSE, these could be more efficient, by using movd/movq.
259 if (!X86ScalarSSEf64) {
260 setOperationAction(ISD::BITCAST , MVT::f32 , Expand);
261 setOperationAction(ISD::BITCAST , MVT::i32 , Expand);
262 if (Subtarget->is64Bit()) {
263 setOperationAction(ISD::BITCAST , MVT::f64 , Expand);
264 // Without SSE, i64->f64 goes through memory.
265 setOperationAction(ISD::BITCAST , MVT::i64 , Expand);
269 // Scalar integer divide and remainder are lowered to use operations that
270 // produce two results, to match the available instructions. This exposes
271 // the two-result form to trivial CSE, which is able to combine x/y and x%y
272 // into a single instruction.
274 // Scalar integer multiply-high is also lowered to use two-result
275 // operations, to match the available instructions. However, plain multiply
276 // (low) operations are left as Legal, as there are single-result
277 // instructions for this in x86. Using the two-result multiply instructions
278 // when both high and low results are needed must be arranged by dagcombine.
279 for (auto VT : { MVT::i8, MVT::i16, MVT::i32, MVT::i64 }) {
280 setOperationAction(ISD::MULHS, VT, Expand);
281 setOperationAction(ISD::MULHU, VT, Expand);
282 setOperationAction(ISD::SDIV, VT, Expand);
283 setOperationAction(ISD::UDIV, VT, Expand);
284 setOperationAction(ISD::SREM, VT, Expand);
285 setOperationAction(ISD::UREM, VT, Expand);
287 // Add/Sub overflow ops with MVT::Glues are lowered to EFLAGS dependences.
288 setOperationAction(ISD::ADDC, VT, Custom);
289 setOperationAction(ISD::ADDE, VT, Custom);
290 setOperationAction(ISD::SUBC, VT, Custom);
291 setOperationAction(ISD::SUBE, VT, Custom);
294 setOperationAction(ISD::BR_JT , MVT::Other, Expand);
295 setOperationAction(ISD::BRCOND , MVT::Other, Custom);
296 setOperationAction(ISD::BR_CC , MVT::f32, Expand);
297 setOperationAction(ISD::BR_CC , MVT::f64, Expand);
298 setOperationAction(ISD::BR_CC , MVT::f80, Expand);
299 setOperationAction(ISD::BR_CC , MVT::i8, Expand);
300 setOperationAction(ISD::BR_CC , MVT::i16, Expand);
301 setOperationAction(ISD::BR_CC , MVT::i32, Expand);
302 setOperationAction(ISD::BR_CC , MVT::i64, Expand);
303 setOperationAction(ISD::SELECT_CC , MVT::f32, Expand);
304 setOperationAction(ISD::SELECT_CC , MVT::f64, Expand);
305 setOperationAction(ISD::SELECT_CC , MVT::f80, Expand);
306 setOperationAction(ISD::SELECT_CC , MVT::i8, Expand);
307 setOperationAction(ISD::SELECT_CC , MVT::i16, Expand);
308 setOperationAction(ISD::SELECT_CC , MVT::i32, Expand);
309 setOperationAction(ISD::SELECT_CC , MVT::i64, Expand);
310 if (Subtarget->is64Bit())
311 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal);
312 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Legal);
313 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Legal);
314 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
315 setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand);
317 if (Subtarget->is32Bit() && Subtarget->isTargetKnownWindowsMSVC()) {
318 // On 32 bit MSVC, `fmodf(f32)` is not defined - only `fmod(f64)`
319 // is. We should promote the value to 64-bits to solve this.
320 // This is what the CRT headers do - `fmodf` is an inline header
321 // function casting to f64 and calling `fmod`.
322 setOperationAction(ISD::FREM , MVT::f32 , Promote);
324 setOperationAction(ISD::FREM , MVT::f32 , Expand);
327 setOperationAction(ISD::FREM , MVT::f64 , Expand);
328 setOperationAction(ISD::FREM , MVT::f80 , Expand);
329 setOperationAction(ISD::FLT_ROUNDS_ , MVT::i32 , Custom);
331 // Promote the i8 variants and force them on up to i32 which has a shorter
333 setOperationAction(ISD::CTTZ , MVT::i8 , Promote);
334 AddPromotedToType (ISD::CTTZ , MVT::i8 , MVT::i32);
335 setOperationAction(ISD::CTTZ_ZERO_UNDEF , MVT::i8 , Promote);
336 AddPromotedToType (ISD::CTTZ_ZERO_UNDEF , MVT::i8 , MVT::i32);
337 if (Subtarget->hasBMI()) {
338 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i16 , Expand);
339 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32 , Expand);
340 if (Subtarget->is64Bit())
341 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand);
343 setOperationAction(ISD::CTTZ , MVT::i16 , Custom);
344 setOperationAction(ISD::CTTZ , MVT::i32 , Custom);
345 if (Subtarget->is64Bit())
346 setOperationAction(ISD::CTTZ , MVT::i64 , Custom);
349 if (Subtarget->hasLZCNT()) {
350 // When promoting the i8 variants, force them to i32 for a shorter
352 setOperationAction(ISD::CTLZ , MVT::i8 , Promote);
353 AddPromotedToType (ISD::CTLZ , MVT::i8 , MVT::i32);
354 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Promote);
355 AddPromotedToType (ISD::CTLZ_ZERO_UNDEF, MVT::i8 , MVT::i32);
356 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Expand);
357 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Expand);
358 if (Subtarget->is64Bit())
359 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Expand);
361 setOperationAction(ISD::CTLZ , MVT::i8 , Custom);
362 setOperationAction(ISD::CTLZ , MVT::i16 , Custom);
363 setOperationAction(ISD::CTLZ , MVT::i32 , Custom);
364 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Custom);
365 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Custom);
366 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Custom);
367 if (Subtarget->is64Bit()) {
368 setOperationAction(ISD::CTLZ , MVT::i64 , Custom);
369 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Custom);
373 // Special handling for half-precision floating point conversions.
374 // If we don't have F16C support, then lower half float conversions
375 // into library calls.
376 if (Subtarget->useSoftFloat() || !Subtarget->hasF16C()) {
377 setOperationAction(ISD::FP16_TO_FP, MVT::f32, Expand);
378 setOperationAction(ISD::FP_TO_FP16, MVT::f32, Expand);
381 // There's never any support for operations beyond MVT::f32.
382 setOperationAction(ISD::FP16_TO_FP, MVT::f64, Expand);
383 setOperationAction(ISD::FP16_TO_FP, MVT::f80, Expand);
384 setOperationAction(ISD::FP_TO_FP16, MVT::f64, Expand);
385 setOperationAction(ISD::FP_TO_FP16, MVT::f80, Expand);
387 setLoadExtAction(ISD::EXTLOAD, MVT::f32, MVT::f16, Expand);
388 setLoadExtAction(ISD::EXTLOAD, MVT::f64, MVT::f16, Expand);
389 setLoadExtAction(ISD::EXTLOAD, MVT::f80, MVT::f16, Expand);
390 setTruncStoreAction(MVT::f32, MVT::f16, Expand);
391 setTruncStoreAction(MVT::f64, MVT::f16, Expand);
392 setTruncStoreAction(MVT::f80, MVT::f16, Expand);
394 if (Subtarget->hasPOPCNT()) {
395 setOperationAction(ISD::CTPOP , MVT::i8 , Promote);
397 setOperationAction(ISD::CTPOP , MVT::i8 , Expand);
398 setOperationAction(ISD::CTPOP , MVT::i16 , Expand);
399 setOperationAction(ISD::CTPOP , MVT::i32 , Expand);
400 if (Subtarget->is64Bit())
401 setOperationAction(ISD::CTPOP , MVT::i64 , Expand);
404 setOperationAction(ISD::READCYCLECOUNTER , MVT::i64 , Custom);
406 if (!Subtarget->hasMOVBE())
407 setOperationAction(ISD::BSWAP , MVT::i16 , Expand);
409 // These should be promoted to a larger select which is supported.
410 setOperationAction(ISD::SELECT , MVT::i1 , Promote);
411 // X86 wants to expand cmov itself.
412 setOperationAction(ISD::SELECT , MVT::i8 , Custom);
413 setOperationAction(ISD::SELECT , MVT::i16 , Custom);
414 setOperationAction(ISD::SELECT , MVT::i32 , Custom);
415 setOperationAction(ISD::SELECT , MVT::f32 , Custom);
416 setOperationAction(ISD::SELECT , MVT::f64 , Custom);
417 setOperationAction(ISD::SELECT , MVT::f80 , Custom);
418 setOperationAction(ISD::SETCC , MVT::i8 , Custom);
419 setOperationAction(ISD::SETCC , MVT::i16 , Custom);
420 setOperationAction(ISD::SETCC , MVT::i32 , Custom);
421 setOperationAction(ISD::SETCC , MVT::f32 , Custom);
422 setOperationAction(ISD::SETCC , MVT::f64 , Custom);
423 setOperationAction(ISD::SETCC , MVT::f80 , Custom);
424 setOperationAction(ISD::SETCCE , MVT::i8 , Custom);
425 setOperationAction(ISD::SETCCE , MVT::i16 , Custom);
426 setOperationAction(ISD::SETCCE , MVT::i32 , Custom);
427 if (Subtarget->is64Bit()) {
428 setOperationAction(ISD::SELECT , MVT::i64 , Custom);
429 setOperationAction(ISD::SETCC , MVT::i64 , Custom);
430 setOperationAction(ISD::SETCCE , MVT::i64 , Custom);
432 setOperationAction(ISD::EH_RETURN , MVT::Other, Custom);
433 // NOTE: EH_SJLJ_SETJMP/_LONGJMP supported here is NOT intended to support
434 // SjLj exception handling but a light-weight setjmp/longjmp replacement to
435 // support continuation, user-level threading, and etc.. As a result, no
436 // other SjLj exception interfaces are implemented and please don't build
437 // your own exception handling based on them.
438 // LLVM/Clang supports zero-cost DWARF exception handling.
439 setOperationAction(ISD::EH_SJLJ_SETJMP, MVT::i32, Custom);
440 setOperationAction(ISD::EH_SJLJ_LONGJMP, MVT::Other, Custom);
443 setOperationAction(ISD::ConstantPool , MVT::i32 , Custom);
444 setOperationAction(ISD::JumpTable , MVT::i32 , Custom);
445 setOperationAction(ISD::GlobalAddress , MVT::i32 , Custom);
446 setOperationAction(ISD::GlobalTLSAddress, MVT::i32 , Custom);
447 if (Subtarget->is64Bit())
448 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
449 setOperationAction(ISD::ExternalSymbol , MVT::i32 , Custom);
450 setOperationAction(ISD::BlockAddress , MVT::i32 , Custom);
451 if (Subtarget->is64Bit()) {
452 setOperationAction(ISD::ConstantPool , MVT::i64 , Custom);
453 setOperationAction(ISD::JumpTable , MVT::i64 , Custom);
454 setOperationAction(ISD::GlobalAddress , MVT::i64 , Custom);
455 setOperationAction(ISD::ExternalSymbol, MVT::i64 , Custom);
456 setOperationAction(ISD::BlockAddress , MVT::i64 , Custom);
458 // 64-bit addm sub, shl, sra, srl (iff 32-bit x86)
459 setOperationAction(ISD::SHL_PARTS , MVT::i32 , Custom);
460 setOperationAction(ISD::SRA_PARTS , MVT::i32 , Custom);
461 setOperationAction(ISD::SRL_PARTS , MVT::i32 , Custom);
462 if (Subtarget->is64Bit()) {
463 setOperationAction(ISD::SHL_PARTS , MVT::i64 , Custom);
464 setOperationAction(ISD::SRA_PARTS , MVT::i64 , Custom);
465 setOperationAction(ISD::SRL_PARTS , MVT::i64 , Custom);
468 if (Subtarget->hasSSE1())
469 setOperationAction(ISD::PREFETCH , MVT::Other, Legal);
471 setOperationAction(ISD::ATOMIC_FENCE , MVT::Other, Custom);
473 // Expand certain atomics
474 for (auto VT : { MVT::i8, MVT::i16, MVT::i32, MVT::i64 }) {
475 setOperationAction(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, VT, Custom);
476 setOperationAction(ISD::ATOMIC_LOAD_SUB, VT, Custom);
477 setOperationAction(ISD::ATOMIC_STORE, VT, Custom);
480 if (Subtarget->hasCmpxchg16b()) {
481 setOperationAction(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, MVT::i128, Custom);
484 // FIXME - use subtarget debug flags
485 if (!Subtarget->isTargetDarwin() && !Subtarget->isTargetELF() &&
486 !Subtarget->isTargetCygMing() && !Subtarget->isTargetWin64()) {
487 setOperationAction(ISD::EH_LABEL, MVT::Other, Expand);
490 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i32, Custom);
491 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i64, Custom);
493 setOperationAction(ISD::INIT_TRAMPOLINE, MVT::Other, Custom);
494 setOperationAction(ISD::ADJUST_TRAMPOLINE, MVT::Other, Custom);
496 setOperationAction(ISD::TRAP, MVT::Other, Legal);
497 setOperationAction(ISD::DEBUGTRAP, MVT::Other, Legal);
499 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
500 setOperationAction(ISD::VASTART , MVT::Other, Custom);
501 setOperationAction(ISD::VAEND , MVT::Other, Expand);
502 if (Subtarget->is64Bit()) {
503 setOperationAction(ISD::VAARG , MVT::Other, Custom);
504 setOperationAction(ISD::VACOPY , MVT::Other, Custom);
506 // TargetInfo::CharPtrBuiltinVaList
507 setOperationAction(ISD::VAARG , MVT::Other, Expand);
508 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
511 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
512 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
514 setOperationAction(ISD::DYNAMIC_STACKALLOC, PtrVT, Custom);
516 // GC_TRANSITION_START and GC_TRANSITION_END need custom lowering.
517 setOperationAction(ISD::GC_TRANSITION_START, MVT::Other, Custom);
518 setOperationAction(ISD::GC_TRANSITION_END, MVT::Other, Custom);
520 if (!Subtarget->useSoftFloat() && X86ScalarSSEf64) {
521 // f32 and f64 use SSE.
522 // Set up the FP register classes.
523 addRegisterClass(MVT::f32, &X86::FR32RegClass);
524 addRegisterClass(MVT::f64, &X86::FR64RegClass);
526 // Use ANDPD to simulate FABS.
527 setOperationAction(ISD::FABS , MVT::f64, Custom);
528 setOperationAction(ISD::FABS , MVT::f32, Custom);
530 // Use XORP to simulate FNEG.
531 setOperationAction(ISD::FNEG , MVT::f64, Custom);
532 setOperationAction(ISD::FNEG , MVT::f32, Custom);
534 // Use ANDPD and ORPD to simulate FCOPYSIGN.
535 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
536 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
538 // Lower this to FGETSIGNx86 plus an AND.
539 setOperationAction(ISD::FGETSIGN, MVT::i64, Custom);
540 setOperationAction(ISD::FGETSIGN, MVT::i32, Custom);
542 // We don't support sin/cos/fmod
543 setOperationAction(ISD::FSIN , MVT::f64, Expand);
544 setOperationAction(ISD::FCOS , MVT::f64, Expand);
545 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
546 setOperationAction(ISD::FSIN , MVT::f32, Expand);
547 setOperationAction(ISD::FCOS , MVT::f32, Expand);
548 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
550 // Expand FP immediates into loads from the stack, except for the special
552 addLegalFPImmediate(APFloat(+0.0)); // xorpd
553 addLegalFPImmediate(APFloat(+0.0f)); // xorps
554 } else if (!Subtarget->useSoftFloat() && X86ScalarSSEf32) {
555 // Use SSE for f32, x87 for f64.
556 // Set up the FP register classes.
557 addRegisterClass(MVT::f32, &X86::FR32RegClass);
558 addRegisterClass(MVT::f64, &X86::RFP64RegClass);
560 // Use ANDPS to simulate FABS.
561 setOperationAction(ISD::FABS , MVT::f32, Custom);
563 // Use XORP to simulate FNEG.
564 setOperationAction(ISD::FNEG , MVT::f32, Custom);
566 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
568 // Use ANDPS and ORPS to simulate FCOPYSIGN.
569 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
570 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
572 // We don't support sin/cos/fmod
573 setOperationAction(ISD::FSIN , MVT::f32, Expand);
574 setOperationAction(ISD::FCOS , MVT::f32, Expand);
575 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
577 // Special cases we handle for FP constants.
578 addLegalFPImmediate(APFloat(+0.0f)); // xorps
579 addLegalFPImmediate(APFloat(+0.0)); // FLD0
580 addLegalFPImmediate(APFloat(+1.0)); // FLD1
581 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
582 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
584 if (!TM.Options.UnsafeFPMath) {
585 setOperationAction(ISD::FSIN , MVT::f64, Expand);
586 setOperationAction(ISD::FCOS , MVT::f64, Expand);
587 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
589 } else if (!Subtarget->useSoftFloat()) {
590 // f32 and f64 in x87.
591 // Set up the FP register classes.
592 addRegisterClass(MVT::f64, &X86::RFP64RegClass);
593 addRegisterClass(MVT::f32, &X86::RFP32RegClass);
595 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
596 setOperationAction(ISD::UNDEF, MVT::f32, Expand);
597 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
598 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
600 if (!TM.Options.UnsafeFPMath) {
601 setOperationAction(ISD::FSIN , MVT::f64, Expand);
602 setOperationAction(ISD::FSIN , MVT::f32, Expand);
603 setOperationAction(ISD::FCOS , MVT::f64, Expand);
604 setOperationAction(ISD::FCOS , MVT::f32, Expand);
605 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
606 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
608 addLegalFPImmediate(APFloat(+0.0)); // FLD0
609 addLegalFPImmediate(APFloat(+1.0)); // FLD1
610 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
611 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
612 addLegalFPImmediate(APFloat(+0.0f)); // FLD0
613 addLegalFPImmediate(APFloat(+1.0f)); // FLD1
614 addLegalFPImmediate(APFloat(-0.0f)); // FLD0/FCHS
615 addLegalFPImmediate(APFloat(-1.0f)); // FLD1/FCHS
618 // We don't support FMA.
619 setOperationAction(ISD::FMA, MVT::f64, Expand);
620 setOperationAction(ISD::FMA, MVT::f32, Expand);
622 // Long double always uses X87.
623 if (!Subtarget->useSoftFloat()) {
624 addRegisterClass(MVT::f80, &X86::RFP80RegClass);
625 setOperationAction(ISD::UNDEF, MVT::f80, Expand);
626 setOperationAction(ISD::FCOPYSIGN, MVT::f80, Expand);
628 APFloat TmpFlt = APFloat::getZero(APFloat::x87DoubleExtended);
629 addLegalFPImmediate(TmpFlt); // FLD0
631 addLegalFPImmediate(TmpFlt); // FLD0/FCHS
634 APFloat TmpFlt2(+1.0);
635 TmpFlt2.convert(APFloat::x87DoubleExtended, APFloat::rmNearestTiesToEven,
637 addLegalFPImmediate(TmpFlt2); // FLD1
638 TmpFlt2.changeSign();
639 addLegalFPImmediate(TmpFlt2); // FLD1/FCHS
642 if (!TM.Options.UnsafeFPMath) {
643 setOperationAction(ISD::FSIN , MVT::f80, Expand);
644 setOperationAction(ISD::FCOS , MVT::f80, Expand);
645 setOperationAction(ISD::FSINCOS, MVT::f80, Expand);
648 setOperationAction(ISD::FFLOOR, MVT::f80, Expand);
649 setOperationAction(ISD::FCEIL, MVT::f80, Expand);
650 setOperationAction(ISD::FTRUNC, MVT::f80, Expand);
651 setOperationAction(ISD::FRINT, MVT::f80, Expand);
652 setOperationAction(ISD::FNEARBYINT, MVT::f80, Expand);
653 setOperationAction(ISD::FMA, MVT::f80, Expand);
656 // Always use a library call for pow.
657 setOperationAction(ISD::FPOW , MVT::f32 , Expand);
658 setOperationAction(ISD::FPOW , MVT::f64 , Expand);
659 setOperationAction(ISD::FPOW , MVT::f80 , Expand);
661 setOperationAction(ISD::FLOG, MVT::f80, Expand);
662 setOperationAction(ISD::FLOG2, MVT::f80, Expand);
663 setOperationAction(ISD::FLOG10, MVT::f80, Expand);
664 setOperationAction(ISD::FEXP, MVT::f80, Expand);
665 setOperationAction(ISD::FEXP2, MVT::f80, Expand);
666 setOperationAction(ISD::FMINNUM, MVT::f80, Expand);
667 setOperationAction(ISD::FMAXNUM, MVT::f80, Expand);
669 // First set operation action for all vector types to either promote
670 // (for widening) or expand (for scalarization). Then we will selectively
671 // turn on ones that can be effectively codegen'd.
672 for (MVT VT : MVT::vector_valuetypes()) {
673 setOperationAction(ISD::ADD , VT, Expand);
674 setOperationAction(ISD::SUB , VT, Expand);
675 setOperationAction(ISD::FADD, VT, Expand);
676 setOperationAction(ISD::FNEG, VT, Expand);
677 setOperationAction(ISD::FSUB, VT, Expand);
678 setOperationAction(ISD::MUL , VT, Expand);
679 setOperationAction(ISD::FMUL, VT, Expand);
680 setOperationAction(ISD::SDIV, VT, Expand);
681 setOperationAction(ISD::UDIV, VT, Expand);
682 setOperationAction(ISD::FDIV, VT, Expand);
683 setOperationAction(ISD::SREM, VT, Expand);
684 setOperationAction(ISD::UREM, VT, Expand);
685 setOperationAction(ISD::LOAD, VT, Expand);
686 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Expand);
687 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT,Expand);
688 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Expand);
689 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT,Expand);
690 setOperationAction(ISD::INSERT_SUBVECTOR, VT,Expand);
691 setOperationAction(ISD::FABS, VT, Expand);
692 setOperationAction(ISD::FSIN, VT, Expand);
693 setOperationAction(ISD::FSINCOS, VT, Expand);
694 setOperationAction(ISD::FCOS, VT, Expand);
695 setOperationAction(ISD::FSINCOS, VT, Expand);
696 setOperationAction(ISD::FREM, VT, Expand);
697 setOperationAction(ISD::FMA, VT, Expand);
698 setOperationAction(ISD::FPOWI, VT, Expand);
699 setOperationAction(ISD::FSQRT, VT, Expand);
700 setOperationAction(ISD::FCOPYSIGN, VT, Expand);
701 setOperationAction(ISD::FFLOOR, VT, Expand);
702 setOperationAction(ISD::FCEIL, VT, Expand);
703 setOperationAction(ISD::FTRUNC, VT, Expand);
704 setOperationAction(ISD::FRINT, VT, Expand);
705 setOperationAction(ISD::FNEARBYINT, VT, Expand);
706 setOperationAction(ISD::SMUL_LOHI, VT, Expand);
707 setOperationAction(ISD::MULHS, VT, Expand);
708 setOperationAction(ISD::UMUL_LOHI, VT, Expand);
709 setOperationAction(ISD::MULHU, VT, Expand);
710 setOperationAction(ISD::SDIVREM, VT, Expand);
711 setOperationAction(ISD::UDIVREM, VT, Expand);
712 setOperationAction(ISD::FPOW, VT, Expand);
713 setOperationAction(ISD::CTPOP, VT, Expand);
714 setOperationAction(ISD::CTTZ, VT, Expand);
715 setOperationAction(ISD::CTTZ_ZERO_UNDEF, VT, Expand);
716 setOperationAction(ISD::CTLZ, VT, Expand);
717 setOperationAction(ISD::CTLZ_ZERO_UNDEF, VT, Expand);
718 setOperationAction(ISD::SHL, VT, Expand);
719 setOperationAction(ISD::SRA, VT, Expand);
720 setOperationAction(ISD::SRL, VT, Expand);
721 setOperationAction(ISD::ROTL, VT, Expand);
722 setOperationAction(ISD::ROTR, VT, Expand);
723 setOperationAction(ISD::BSWAP, VT, Expand);
724 setOperationAction(ISD::SETCC, VT, Expand);
725 setOperationAction(ISD::FLOG, VT, Expand);
726 setOperationAction(ISD::FLOG2, VT, Expand);
727 setOperationAction(ISD::FLOG10, VT, Expand);
728 setOperationAction(ISD::FEXP, VT, Expand);
729 setOperationAction(ISD::FEXP2, VT, Expand);
730 setOperationAction(ISD::FP_TO_UINT, VT, Expand);
731 setOperationAction(ISD::FP_TO_SINT, VT, Expand);
732 setOperationAction(ISD::UINT_TO_FP, VT, Expand);
733 setOperationAction(ISD::SINT_TO_FP, VT, Expand);
734 setOperationAction(ISD::SIGN_EXTEND_INREG, VT,Expand);
735 setOperationAction(ISD::TRUNCATE, VT, Expand);
736 setOperationAction(ISD::SIGN_EXTEND, VT, Expand);
737 setOperationAction(ISD::ZERO_EXTEND, VT, Expand);
738 setOperationAction(ISD::ANY_EXTEND, VT, Expand);
739 setOperationAction(ISD::VSELECT, VT, Expand);
740 setOperationAction(ISD::SELECT_CC, VT, Expand);
741 for (MVT InnerVT : MVT::vector_valuetypes()) {
742 setTruncStoreAction(InnerVT, VT, Expand);
744 setLoadExtAction(ISD::SEXTLOAD, InnerVT, VT, Expand);
745 setLoadExtAction(ISD::ZEXTLOAD, InnerVT, VT, Expand);
747 // N.b. ISD::EXTLOAD legality is basically ignored except for i1-like
748 // types, we have to deal with them whether we ask for Expansion or not.
749 // Setting Expand causes its own optimisation problems though, so leave
751 if (VT.getVectorElementType() == MVT::i1)
752 setLoadExtAction(ISD::EXTLOAD, InnerVT, VT, Expand);
754 // EXTLOAD for MVT::f16 vectors is not legal because f16 vectors are
755 // split/scalarized right now.
756 if (VT.getVectorElementType() == MVT::f16)
757 setLoadExtAction(ISD::EXTLOAD, InnerVT, VT, Expand);
761 // FIXME: In order to prevent SSE instructions being expanded to MMX ones
762 // with -msoft-float, disable use of MMX as well.
763 if (!Subtarget->useSoftFloat() && Subtarget->hasMMX()) {
764 addRegisterClass(MVT::x86mmx, &X86::VR64RegClass);
765 // No operations on x86mmx supported, everything uses intrinsics.
768 // MMX-sized vectors (other than x86mmx) are expected to be expanded
769 // into smaller operations.
770 for (MVT MMXTy : {MVT::v8i8, MVT::v4i16, MVT::v2i32, MVT::v1i64}) {
771 setOperationAction(ISD::MULHS, MMXTy, Expand);
772 setOperationAction(ISD::AND, MMXTy, Expand);
773 setOperationAction(ISD::OR, MMXTy, Expand);
774 setOperationAction(ISD::XOR, MMXTy, Expand);
775 setOperationAction(ISD::SCALAR_TO_VECTOR, MMXTy, Expand);
776 setOperationAction(ISD::SELECT, MMXTy, Expand);
777 setOperationAction(ISD::BITCAST, MMXTy, Expand);
779 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v1i64, Expand);
781 if (!Subtarget->useSoftFloat() && Subtarget->hasSSE1()) {
782 addRegisterClass(MVT::v4f32, &X86::VR128RegClass);
784 setOperationAction(ISD::FADD, MVT::v4f32, Legal);
785 setOperationAction(ISD::FSUB, MVT::v4f32, Legal);
786 setOperationAction(ISD::FMUL, MVT::v4f32, Legal);
787 setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
788 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal);
789 setOperationAction(ISD::FNEG, MVT::v4f32, Custom);
790 setOperationAction(ISD::FABS, MVT::v4f32, Custom);
791 setOperationAction(ISD::LOAD, MVT::v4f32, Legal);
792 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
793 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f32, Custom);
794 setOperationAction(ISD::VSELECT, MVT::v4f32, Custom);
795 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
796 setOperationAction(ISD::SELECT, MVT::v4f32, Custom);
797 setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Custom);
800 if (!Subtarget->useSoftFloat() && Subtarget->hasSSE2()) {
801 addRegisterClass(MVT::v2f64, &X86::VR128RegClass);
803 // FIXME: Unfortunately, -soft-float and -no-implicit-float mean XMM
804 // registers cannot be used even for integer operations.
805 addRegisterClass(MVT::v16i8, &X86::VR128RegClass);
806 addRegisterClass(MVT::v8i16, &X86::VR128RegClass);
807 addRegisterClass(MVT::v4i32, &X86::VR128RegClass);
808 addRegisterClass(MVT::v2i64, &X86::VR128RegClass);
810 setOperationAction(ISD::ADD, MVT::v16i8, Legal);
811 setOperationAction(ISD::ADD, MVT::v8i16, Legal);
812 setOperationAction(ISD::ADD, MVT::v4i32, Legal);
813 setOperationAction(ISD::ADD, MVT::v2i64, Legal);
814 setOperationAction(ISD::MUL, MVT::v16i8, Custom);
815 setOperationAction(ISD::MUL, MVT::v4i32, Custom);
816 setOperationAction(ISD::MUL, MVT::v2i64, Custom);
817 setOperationAction(ISD::UMUL_LOHI, MVT::v4i32, Custom);
818 setOperationAction(ISD::SMUL_LOHI, MVT::v4i32, Custom);
819 setOperationAction(ISD::MULHU, MVT::v8i16, Legal);
820 setOperationAction(ISD::MULHS, MVT::v8i16, Legal);
821 setOperationAction(ISD::SUB, MVT::v16i8, Legal);
822 setOperationAction(ISD::SUB, MVT::v8i16, Legal);
823 setOperationAction(ISD::SUB, MVT::v4i32, Legal);
824 setOperationAction(ISD::SUB, MVT::v2i64, Legal);
825 setOperationAction(ISD::MUL, MVT::v8i16, Legal);
826 setOperationAction(ISD::FADD, MVT::v2f64, Legal);
827 setOperationAction(ISD::FSUB, MVT::v2f64, Legal);
828 setOperationAction(ISD::FMUL, MVT::v2f64, Legal);
829 setOperationAction(ISD::FDIV, MVT::v2f64, Legal);
830 setOperationAction(ISD::FSQRT, MVT::v2f64, Legal);
831 setOperationAction(ISD::FNEG, MVT::v2f64, Custom);
832 setOperationAction(ISD::FABS, MVT::v2f64, Custom);
834 setOperationAction(ISD::SMAX, MVT::v8i16, Legal);
835 setOperationAction(ISD::UMAX, MVT::v16i8, Legal);
836 setOperationAction(ISD::SMIN, MVT::v8i16, Legal);
837 setOperationAction(ISD::UMIN, MVT::v16i8, Legal);
839 setOperationAction(ISD::SETCC, MVT::v2i64, Custom);
840 setOperationAction(ISD::SETCC, MVT::v16i8, Custom);
841 setOperationAction(ISD::SETCC, MVT::v8i16, Custom);
842 setOperationAction(ISD::SETCC, MVT::v4i32, Custom);
844 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Custom);
845 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Custom);
846 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
847 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
848 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
850 setOperationAction(ISD::CTPOP, MVT::v16i8, Custom);
851 setOperationAction(ISD::CTPOP, MVT::v8i16, Custom);
852 setOperationAction(ISD::CTPOP, MVT::v4i32, Custom);
853 setOperationAction(ISD::CTPOP, MVT::v2i64, Custom);
855 setOperationAction(ISD::CTTZ, MVT::v16i8, Custom);
856 setOperationAction(ISD::CTTZ, MVT::v8i16, Custom);
857 setOperationAction(ISD::CTTZ, MVT::v4i32, Custom);
858 // ISD::CTTZ v2i64 - scalarization is faster.
859 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v16i8, Custom);
860 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v8i16, Custom);
861 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v4i32, Custom);
862 // ISD::CTTZ_ZERO_UNDEF v2i64 - scalarization is faster.
864 // Custom lower build_vector, vector_shuffle, and extract_vector_elt.
865 for (auto VT : { MVT::v16i8, MVT::v8i16, MVT::v4i32 }) {
866 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
867 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
868 setOperationAction(ISD::VSELECT, VT, Custom);
869 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
872 // We support custom legalizing of sext and anyext loads for specific
873 // memory vector types which we can load as a scalar (or sequence of
874 // scalars) and extend in-register to a legal 128-bit vector type. For sext
875 // loads these must work with a single scalar load.
876 for (MVT VT : MVT::integer_vector_valuetypes()) {
877 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v4i8, Custom);
878 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v4i16, Custom);
879 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v8i8, Custom);
880 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v2i8, Custom);
881 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v2i16, Custom);
882 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v2i32, Custom);
883 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v4i8, Custom);
884 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v4i16, Custom);
885 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v8i8, Custom);
888 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f64, Custom);
889 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i64, Custom);
890 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Custom);
891 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Custom);
892 setOperationAction(ISD::VSELECT, MVT::v2f64, Custom);
893 setOperationAction(ISD::VSELECT, MVT::v2i64, Custom);
894 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f64, Custom);
895 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Custom);
897 if (Subtarget->is64Bit()) {
898 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
899 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
902 // Promote v16i8, v8i16, v4i32 load, select, and, or, xor to v2i64.
903 for (auto VT : { MVT::v16i8, MVT::v8i16, MVT::v4i32 }) {
904 setOperationAction(ISD::AND, VT, Promote);
905 AddPromotedToType (ISD::AND, VT, MVT::v2i64);
906 setOperationAction(ISD::OR, VT, Promote);
907 AddPromotedToType (ISD::OR, VT, MVT::v2i64);
908 setOperationAction(ISD::XOR, VT, Promote);
909 AddPromotedToType (ISD::XOR, VT, MVT::v2i64);
910 setOperationAction(ISD::LOAD, VT, Promote);
911 AddPromotedToType (ISD::LOAD, VT, MVT::v2i64);
912 setOperationAction(ISD::SELECT, VT, Promote);
913 AddPromotedToType (ISD::SELECT, VT, MVT::v2i64);
916 // Custom lower v2i64 and v2f64 selects.
917 setOperationAction(ISD::LOAD, MVT::v2f64, Legal);
918 setOperationAction(ISD::LOAD, MVT::v2i64, Legal);
919 setOperationAction(ISD::SELECT, MVT::v2f64, Custom);
920 setOperationAction(ISD::SELECT, MVT::v2i64, Custom);
922 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal);
923 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal);
925 setOperationAction(ISD::SINT_TO_FP, MVT::v2i32, Custom);
927 setOperationAction(ISD::UINT_TO_FP, MVT::v4i8, Custom);
928 setOperationAction(ISD::UINT_TO_FP, MVT::v4i16, Custom);
929 // As there is no 64-bit GPR available, we need build a special custom
930 // sequence to convert from v2i32 to v2f32.
931 if (!Subtarget->is64Bit())
932 setOperationAction(ISD::UINT_TO_FP, MVT::v2f32, Custom);
934 setOperationAction(ISD::FP_EXTEND, MVT::v2f32, Custom);
935 setOperationAction(ISD::FP_ROUND, MVT::v2f32, Custom);
937 for (MVT VT : MVT::fp_vector_valuetypes())
938 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v2f32, Legal);
940 setOperationAction(ISD::BITCAST, MVT::v2i32, Custom);
941 setOperationAction(ISD::BITCAST, MVT::v4i16, Custom);
942 setOperationAction(ISD::BITCAST, MVT::v8i8, Custom);
945 if (!Subtarget->useSoftFloat() && Subtarget->hasSSE41()) {
946 for (MVT RoundedTy : {MVT::f32, MVT::f64, MVT::v4f32, MVT::v2f64}) {
947 setOperationAction(ISD::FFLOOR, RoundedTy, Legal);
948 setOperationAction(ISD::FCEIL, RoundedTy, Legal);
949 setOperationAction(ISD::FTRUNC, RoundedTy, Legal);
950 setOperationAction(ISD::FRINT, RoundedTy, Legal);
951 setOperationAction(ISD::FNEARBYINT, RoundedTy, Legal);
954 setOperationAction(ISD::SMAX, MVT::v16i8, Legal);
955 setOperationAction(ISD::SMAX, MVT::v4i32, Legal);
956 setOperationAction(ISD::UMAX, MVT::v8i16, Legal);
957 setOperationAction(ISD::UMAX, MVT::v4i32, Legal);
958 setOperationAction(ISD::SMIN, MVT::v16i8, Legal);
959 setOperationAction(ISD::SMIN, MVT::v4i32, Legal);
960 setOperationAction(ISD::UMIN, MVT::v8i16, Legal);
961 setOperationAction(ISD::UMIN, MVT::v4i32, Legal);
963 // FIXME: Do we need to handle scalar-to-vector here?
964 setOperationAction(ISD::MUL, MVT::v4i32, Legal);
966 // We directly match byte blends in the backend as they match the VSELECT
968 setOperationAction(ISD::VSELECT, MVT::v16i8, Legal);
970 // SSE41 brings specific instructions for doing vector sign extend even in
971 // cases where we don't have SRA.
972 for (MVT VT : MVT::integer_vector_valuetypes()) {
973 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v2i8, Custom);
974 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v2i16, Custom);
975 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v2i32, Custom);
978 // SSE41 also has vector sign/zero extending loads, PMOV[SZ]X
979 setLoadExtAction(ISD::SEXTLOAD, MVT::v8i16, MVT::v8i8, Legal);
980 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i32, MVT::v4i8, Legal);
981 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i64, MVT::v2i8, Legal);
982 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i32, MVT::v4i16, Legal);
983 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i64, MVT::v2i16, Legal);
984 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i64, MVT::v2i32, Legal);
986 setLoadExtAction(ISD::ZEXTLOAD, MVT::v8i16, MVT::v8i8, Legal);
987 setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i32, MVT::v4i8, Legal);
988 setLoadExtAction(ISD::ZEXTLOAD, MVT::v2i64, MVT::v2i8, Legal);
989 setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i32, MVT::v4i16, Legal);
990 setLoadExtAction(ISD::ZEXTLOAD, MVT::v2i64, MVT::v2i16, Legal);
991 setLoadExtAction(ISD::ZEXTLOAD, MVT::v2i64, MVT::v2i32, Legal);
993 // i8 and i16 vectors are custom because the source register and source
994 // source memory operand types are not the same width. f32 vectors are
995 // custom since the immediate controlling the insert encodes additional
997 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i8, Custom);
998 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
999 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
1000 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
1002 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i8, Custom);
1003 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i16, Custom);
1004 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i32, Custom);
1005 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
1007 // FIXME: these should be Legal, but that's only for the case where
1008 // the index is constant. For now custom expand to deal with that.
1009 if (Subtarget->is64Bit()) {
1010 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
1011 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
1015 if (Subtarget->hasSSE2()) {
1016 setOperationAction(ISD::SIGN_EXTEND_VECTOR_INREG, MVT::v2i64, Custom);
1017 setOperationAction(ISD::SIGN_EXTEND_VECTOR_INREG, MVT::v4i32, Custom);
1018 setOperationAction(ISD::SIGN_EXTEND_VECTOR_INREG, MVT::v8i16, Custom);
1020 setOperationAction(ISD::SRL, MVT::v8i16, Custom);
1021 setOperationAction(ISD::SRL, MVT::v16i8, Custom);
1023 setOperationAction(ISD::SHL, MVT::v8i16, Custom);
1024 setOperationAction(ISD::SHL, MVT::v16i8, Custom);
1026 setOperationAction(ISD::SRA, MVT::v8i16, Custom);
1027 setOperationAction(ISD::SRA, MVT::v16i8, Custom);
1029 // In the customized shift lowering, the legal cases in AVX2 will be
1031 setOperationAction(ISD::SRL, MVT::v2i64, Custom);
1032 setOperationAction(ISD::SRL, MVT::v4i32, Custom);
1034 setOperationAction(ISD::SHL, MVT::v2i64, Custom);
1035 setOperationAction(ISD::SHL, MVT::v4i32, Custom);
1037 setOperationAction(ISD::SRA, MVT::v2i64, Custom);
1038 setOperationAction(ISD::SRA, MVT::v4i32, Custom);
1041 if (Subtarget->hasXOP()) {
1042 setOperationAction(ISD::ROTL, MVT::v16i8, Custom);
1043 setOperationAction(ISD::ROTL, MVT::v8i16, Custom);
1044 setOperationAction(ISD::ROTL, MVT::v4i32, Custom);
1045 setOperationAction(ISD::ROTL, MVT::v2i64, Custom);
1046 setOperationAction(ISD::ROTL, MVT::v32i8, Custom);
1047 setOperationAction(ISD::ROTL, MVT::v16i16, Custom);
1048 setOperationAction(ISD::ROTL, MVT::v8i32, Custom);
1049 setOperationAction(ISD::ROTL, MVT::v4i64, Custom);
1052 if (!Subtarget->useSoftFloat() && Subtarget->hasFp256()) {
1053 addRegisterClass(MVT::v32i8, &X86::VR256RegClass);
1054 addRegisterClass(MVT::v16i16, &X86::VR256RegClass);
1055 addRegisterClass(MVT::v8i32, &X86::VR256RegClass);
1056 addRegisterClass(MVT::v8f32, &X86::VR256RegClass);
1057 addRegisterClass(MVT::v4i64, &X86::VR256RegClass);
1058 addRegisterClass(MVT::v4f64, &X86::VR256RegClass);
1060 setOperationAction(ISD::LOAD, MVT::v8f32, Legal);
1061 setOperationAction(ISD::LOAD, MVT::v4f64, Legal);
1062 setOperationAction(ISD::LOAD, MVT::v4i64, Legal);
1064 setOperationAction(ISD::FADD, MVT::v8f32, Legal);
1065 setOperationAction(ISD::FSUB, MVT::v8f32, Legal);
1066 setOperationAction(ISD::FMUL, MVT::v8f32, Legal);
1067 setOperationAction(ISD::FDIV, MVT::v8f32, Legal);
1068 setOperationAction(ISD::FSQRT, MVT::v8f32, Legal);
1069 setOperationAction(ISD::FFLOOR, MVT::v8f32, Legal);
1070 setOperationAction(ISD::FCEIL, MVT::v8f32, Legal);
1071 setOperationAction(ISD::FTRUNC, MVT::v8f32, Legal);
1072 setOperationAction(ISD::FRINT, MVT::v8f32, Legal);
1073 setOperationAction(ISD::FNEARBYINT, MVT::v8f32, Legal);
1074 setOperationAction(ISD::FNEG, MVT::v8f32, Custom);
1075 setOperationAction(ISD::FABS, MVT::v8f32, Custom);
1077 setOperationAction(ISD::FADD, MVT::v4f64, Legal);
1078 setOperationAction(ISD::FSUB, MVT::v4f64, Legal);
1079 setOperationAction(ISD::FMUL, MVT::v4f64, Legal);
1080 setOperationAction(ISD::FDIV, MVT::v4f64, Legal);
1081 setOperationAction(ISD::FSQRT, MVT::v4f64, Legal);
1082 setOperationAction(ISD::FFLOOR, MVT::v4f64, Legal);
1083 setOperationAction(ISD::FCEIL, MVT::v4f64, Legal);
1084 setOperationAction(ISD::FTRUNC, MVT::v4f64, Legal);
1085 setOperationAction(ISD::FRINT, MVT::v4f64, Legal);
1086 setOperationAction(ISD::FNEARBYINT, MVT::v4f64, Legal);
1087 setOperationAction(ISD::FNEG, MVT::v4f64, Custom);
1088 setOperationAction(ISD::FABS, MVT::v4f64, Custom);
1090 // (fp_to_int:v8i16 (v8f32 ..)) requires the result type to be promoted
1091 // even though v8i16 is a legal type.
1092 setOperationAction(ISD::FP_TO_SINT, MVT::v8i16, Promote);
1093 setOperationAction(ISD::FP_TO_UINT, MVT::v8i16, Promote);
1094 setOperationAction(ISD::FP_TO_SINT, MVT::v8i32, Legal);
1096 setOperationAction(ISD::SINT_TO_FP, MVT::v8i16, Promote);
1097 setOperationAction(ISD::SINT_TO_FP, MVT::v8i32, Legal);
1098 setOperationAction(ISD::FP_ROUND, MVT::v4f32, Legal);
1100 setOperationAction(ISD::UINT_TO_FP, MVT::v8i8, Custom);
1101 setOperationAction(ISD::UINT_TO_FP, MVT::v8i16, Custom);
1103 for (MVT VT : MVT::fp_vector_valuetypes())
1104 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v4f32, Legal);
1106 setOperationAction(ISD::SRL, MVT::v16i16, Custom);
1107 setOperationAction(ISD::SRL, MVT::v32i8, Custom);
1109 setOperationAction(ISD::SHL, MVT::v16i16, Custom);
1110 setOperationAction(ISD::SHL, MVT::v32i8, Custom);
1112 setOperationAction(ISD::SRA, MVT::v16i16, Custom);
1113 setOperationAction(ISD::SRA, MVT::v32i8, Custom);
1115 setOperationAction(ISD::SETCC, MVT::v32i8, Custom);
1116 setOperationAction(ISD::SETCC, MVT::v16i16, Custom);
1117 setOperationAction(ISD::SETCC, MVT::v8i32, Custom);
1118 setOperationAction(ISD::SETCC, MVT::v4i64, Custom);
1120 setOperationAction(ISD::SELECT, MVT::v4f64, Custom);
1121 setOperationAction(ISD::SELECT, MVT::v4i64, Custom);
1122 setOperationAction(ISD::SELECT, MVT::v8f32, Custom);
1124 setOperationAction(ISD::SIGN_EXTEND, MVT::v4i64, Custom);
1125 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i32, Custom);
1126 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i16, Custom);
1127 setOperationAction(ISD::ZERO_EXTEND, MVT::v4i64, Custom);
1128 setOperationAction(ISD::ZERO_EXTEND, MVT::v8i32, Custom);
1129 setOperationAction(ISD::ZERO_EXTEND, MVT::v16i16, Custom);
1130 setOperationAction(ISD::ANY_EXTEND, MVT::v4i64, Custom);
1131 setOperationAction(ISD::ANY_EXTEND, MVT::v8i32, Custom);
1132 setOperationAction(ISD::ANY_EXTEND, MVT::v16i16, Custom);
1133 setOperationAction(ISD::TRUNCATE, MVT::v16i8, Custom);
1134 setOperationAction(ISD::TRUNCATE, MVT::v8i16, Custom);
1135 setOperationAction(ISD::TRUNCATE, MVT::v4i32, Custom);
1137 setOperationAction(ISD::CTPOP, MVT::v32i8, Custom);
1138 setOperationAction(ISD::CTPOP, MVT::v16i16, Custom);
1139 setOperationAction(ISD::CTPOP, MVT::v8i32, Custom);
1140 setOperationAction(ISD::CTPOP, MVT::v4i64, Custom);
1142 setOperationAction(ISD::CTTZ, MVT::v32i8, Custom);
1143 setOperationAction(ISD::CTTZ, MVT::v16i16, Custom);
1144 setOperationAction(ISD::CTTZ, MVT::v8i32, Custom);
1145 setOperationAction(ISD::CTTZ, MVT::v4i64, Custom);
1146 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v32i8, Custom);
1147 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v16i16, Custom);
1148 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v8i32, Custom);
1149 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v4i64, Custom);
1151 if (Subtarget->hasFMA() || Subtarget->hasFMA4() || Subtarget->hasAVX512()) {
1152 setOperationAction(ISD::FMA, MVT::v8f32, Legal);
1153 setOperationAction(ISD::FMA, MVT::v4f64, Legal);
1154 setOperationAction(ISD::FMA, MVT::v4f32, Legal);
1155 setOperationAction(ISD::FMA, MVT::v2f64, Legal);
1156 setOperationAction(ISD::FMA, MVT::f32, Legal);
1157 setOperationAction(ISD::FMA, MVT::f64, Legal);
1160 if (Subtarget->hasInt256()) {
1161 setOperationAction(ISD::ADD, MVT::v4i64, Legal);
1162 setOperationAction(ISD::ADD, MVT::v8i32, Legal);
1163 setOperationAction(ISD::ADD, MVT::v16i16, Legal);
1164 setOperationAction(ISD::ADD, MVT::v32i8, Legal);
1166 setOperationAction(ISD::SUB, MVT::v4i64, Legal);
1167 setOperationAction(ISD::SUB, MVT::v8i32, Legal);
1168 setOperationAction(ISD::SUB, MVT::v16i16, Legal);
1169 setOperationAction(ISD::SUB, MVT::v32i8, Legal);
1171 setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1172 setOperationAction(ISD::MUL, MVT::v8i32, Legal);
1173 setOperationAction(ISD::MUL, MVT::v16i16, Legal);
1174 setOperationAction(ISD::MUL, MVT::v32i8, Custom);
1176 setOperationAction(ISD::UMUL_LOHI, MVT::v8i32, Custom);
1177 setOperationAction(ISD::SMUL_LOHI, MVT::v8i32, Custom);
1178 setOperationAction(ISD::MULHU, MVT::v16i16, Legal);
1179 setOperationAction(ISD::MULHS, MVT::v16i16, Legal);
1181 setOperationAction(ISD::SMAX, MVT::v32i8, Legal);
1182 setOperationAction(ISD::SMAX, MVT::v16i16, Legal);
1183 setOperationAction(ISD::SMAX, MVT::v8i32, Legal);
1184 setOperationAction(ISD::UMAX, MVT::v32i8, Legal);
1185 setOperationAction(ISD::UMAX, MVT::v16i16, Legal);
1186 setOperationAction(ISD::UMAX, MVT::v8i32, Legal);
1187 setOperationAction(ISD::SMIN, MVT::v32i8, Legal);
1188 setOperationAction(ISD::SMIN, MVT::v16i16, Legal);
1189 setOperationAction(ISD::SMIN, MVT::v8i32, Legal);
1190 setOperationAction(ISD::UMIN, MVT::v32i8, Legal);
1191 setOperationAction(ISD::UMIN, MVT::v16i16, Legal);
1192 setOperationAction(ISD::UMIN, MVT::v8i32, Legal);
1194 // The custom lowering for UINT_TO_FP for v8i32 becomes interesting
1195 // when we have a 256bit-wide blend with immediate.
1196 setOperationAction(ISD::UINT_TO_FP, MVT::v8i32, Custom);
1198 // AVX2 also has wider vector sign/zero extending loads, VPMOV[SZ]X
1199 setLoadExtAction(ISD::SEXTLOAD, MVT::v16i16, MVT::v16i8, Legal);
1200 setLoadExtAction(ISD::SEXTLOAD, MVT::v8i32, MVT::v8i8, Legal);
1201 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i64, MVT::v4i8, Legal);
1202 setLoadExtAction(ISD::SEXTLOAD, MVT::v8i32, MVT::v8i16, Legal);
1203 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i64, MVT::v4i16, Legal);
1204 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i64, MVT::v4i32, Legal);
1206 setLoadExtAction(ISD::ZEXTLOAD, MVT::v16i16, MVT::v16i8, Legal);
1207 setLoadExtAction(ISD::ZEXTLOAD, MVT::v8i32, MVT::v8i8, Legal);
1208 setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i64, MVT::v4i8, Legal);
1209 setLoadExtAction(ISD::ZEXTLOAD, MVT::v8i32, MVT::v8i16, Legal);
1210 setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i64, MVT::v4i16, Legal);
1211 setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i64, MVT::v4i32, Legal);
1213 setOperationAction(ISD::ADD, MVT::v4i64, Custom);
1214 setOperationAction(ISD::ADD, MVT::v8i32, Custom);
1215 setOperationAction(ISD::ADD, MVT::v16i16, Custom);
1216 setOperationAction(ISD::ADD, MVT::v32i8, Custom);
1218 setOperationAction(ISD::SUB, MVT::v4i64, Custom);
1219 setOperationAction(ISD::SUB, MVT::v8i32, Custom);
1220 setOperationAction(ISD::SUB, MVT::v16i16, Custom);
1221 setOperationAction(ISD::SUB, MVT::v32i8, Custom);
1223 setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1224 setOperationAction(ISD::MUL, MVT::v8i32, Custom);
1225 setOperationAction(ISD::MUL, MVT::v16i16, Custom);
1226 setOperationAction(ISD::MUL, MVT::v32i8, Custom);
1228 setOperationAction(ISD::SMAX, MVT::v32i8, Custom);
1229 setOperationAction(ISD::SMAX, MVT::v16i16, Custom);
1230 setOperationAction(ISD::SMAX, MVT::v8i32, Custom);
1231 setOperationAction(ISD::UMAX, MVT::v32i8, Custom);
1232 setOperationAction(ISD::UMAX, MVT::v16i16, Custom);
1233 setOperationAction(ISD::UMAX, MVT::v8i32, Custom);
1234 setOperationAction(ISD::SMIN, MVT::v32i8, Custom);
1235 setOperationAction(ISD::SMIN, MVT::v16i16, Custom);
1236 setOperationAction(ISD::SMIN, MVT::v8i32, Custom);
1237 setOperationAction(ISD::UMIN, MVT::v32i8, Custom);
1238 setOperationAction(ISD::UMIN, MVT::v16i16, Custom);
1239 setOperationAction(ISD::UMIN, MVT::v8i32, Custom);
1242 // In the customized shift lowering, the legal cases in AVX2 will be
1244 setOperationAction(ISD::SRL, MVT::v4i64, Custom);
1245 setOperationAction(ISD::SRL, MVT::v8i32, Custom);
1247 setOperationAction(ISD::SHL, MVT::v4i64, Custom);
1248 setOperationAction(ISD::SHL, MVT::v8i32, Custom);
1250 setOperationAction(ISD::SRA, MVT::v4i64, Custom);
1251 setOperationAction(ISD::SRA, MVT::v8i32, Custom);
1253 // Custom lower several nodes for 256-bit types.
1254 for (MVT VT : MVT::vector_valuetypes()) {
1255 if (VT.getScalarSizeInBits() >= 32) {
1256 setOperationAction(ISD::MLOAD, VT, Legal);
1257 setOperationAction(ISD::MSTORE, VT, Legal);
1259 // Extract subvector is special because the value type
1260 // (result) is 128-bit but the source is 256-bit wide.
1261 if (VT.is128BitVector()) {
1262 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom);
1264 // Do not attempt to custom lower other non-256-bit vectors
1265 if (!VT.is256BitVector())
1268 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1269 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1270 setOperationAction(ISD::VSELECT, VT, Custom);
1271 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
1272 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1273 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom);
1274 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom);
1275 setOperationAction(ISD::CONCAT_VECTORS, VT, Custom);
1278 if (Subtarget->hasInt256())
1279 setOperationAction(ISD::VSELECT, MVT::v32i8, Legal);
1281 // Promote v32i8, v16i16, v8i32 select, and, or, xor to v4i64.
1282 for (auto VT : { MVT::v32i8, MVT::v16i16, MVT::v8i32 }) {
1283 setOperationAction(ISD::AND, VT, Promote);
1284 AddPromotedToType (ISD::AND, VT, MVT::v4i64);
1285 setOperationAction(ISD::OR, VT, Promote);
1286 AddPromotedToType (ISD::OR, VT, MVT::v4i64);
1287 setOperationAction(ISD::XOR, VT, Promote);
1288 AddPromotedToType (ISD::XOR, VT, MVT::v4i64);
1289 setOperationAction(ISD::LOAD, VT, Promote);
1290 AddPromotedToType (ISD::LOAD, VT, MVT::v4i64);
1291 setOperationAction(ISD::SELECT, VT, Promote);
1292 AddPromotedToType (ISD::SELECT, VT, MVT::v4i64);
1296 if (!Subtarget->useSoftFloat() && Subtarget->hasAVX512()) {
1297 addRegisterClass(MVT::v16i32, &X86::VR512RegClass);
1298 addRegisterClass(MVT::v16f32, &X86::VR512RegClass);
1299 addRegisterClass(MVT::v8i64, &X86::VR512RegClass);
1300 addRegisterClass(MVT::v8f64, &X86::VR512RegClass);
1302 addRegisterClass(MVT::i1, &X86::VK1RegClass);
1303 addRegisterClass(MVT::v8i1, &X86::VK8RegClass);
1304 addRegisterClass(MVT::v16i1, &X86::VK16RegClass);
1306 for (MVT VT : MVT::fp_vector_valuetypes())
1307 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v8f32, Legal);
1309 setLoadExtAction(ISD::ZEXTLOAD, MVT::v16i32, MVT::v16i8, Legal);
1310 setLoadExtAction(ISD::SEXTLOAD, MVT::v16i32, MVT::v16i8, Legal);
1311 setLoadExtAction(ISD::ZEXTLOAD, MVT::v16i32, MVT::v16i16, Legal);
1312 setLoadExtAction(ISD::SEXTLOAD, MVT::v16i32, MVT::v16i16, Legal);
1313 setLoadExtAction(ISD::ZEXTLOAD, MVT::v32i16, MVT::v32i8, Legal);
1314 setLoadExtAction(ISD::SEXTLOAD, MVT::v32i16, MVT::v32i8, Legal);
1315 setLoadExtAction(ISD::ZEXTLOAD, MVT::v8i64, MVT::v8i8, Legal);
1316 setLoadExtAction(ISD::SEXTLOAD, MVT::v8i64, MVT::v8i8, Legal);
1317 setLoadExtAction(ISD::ZEXTLOAD, MVT::v8i64, MVT::v8i16, Legal);
1318 setLoadExtAction(ISD::SEXTLOAD, MVT::v8i64, MVT::v8i16, Legal);
1319 setLoadExtAction(ISD::ZEXTLOAD, MVT::v8i64, MVT::v8i32, Legal);
1320 setLoadExtAction(ISD::SEXTLOAD, MVT::v8i64, MVT::v8i32, Legal);
1322 setOperationAction(ISD::BR_CC, MVT::i1, Expand);
1323 setOperationAction(ISD::SETCC, MVT::i1, Custom);
1324 setOperationAction(ISD::SELECT_CC, MVT::i1, Expand);
1325 setOperationAction(ISD::XOR, MVT::i1, Legal);
1326 setOperationAction(ISD::OR, MVT::i1, Legal);
1327 setOperationAction(ISD::AND, MVT::i1, Legal);
1328 setOperationAction(ISD::SUB, MVT::i1, Custom);
1329 setOperationAction(ISD::ADD, MVT::i1, Custom);
1330 setOperationAction(ISD::MUL, MVT::i1, Custom);
1331 setOperationAction(ISD::LOAD, MVT::v16f32, Legal);
1332 setOperationAction(ISD::LOAD, MVT::v8f64, Legal);
1333 setOperationAction(ISD::LOAD, MVT::v8i64, Legal);
1334 setOperationAction(ISD::LOAD, MVT::v16i32, Legal);
1335 setOperationAction(ISD::LOAD, MVT::v16i1, Legal);
1337 setOperationAction(ISD::FADD, MVT::v16f32, Legal);
1338 setOperationAction(ISD::FSUB, MVT::v16f32, Legal);
1339 setOperationAction(ISD::FMUL, MVT::v16f32, Legal);
1340 setOperationAction(ISD::FDIV, MVT::v16f32, Legal);
1341 setOperationAction(ISD::FSQRT, MVT::v16f32, Legal);
1342 setOperationAction(ISD::FNEG, MVT::v16f32, Custom);
1344 setOperationAction(ISD::FADD, MVT::v8f64, Legal);
1345 setOperationAction(ISD::FSUB, MVT::v8f64, Legal);
1346 setOperationAction(ISD::FMUL, MVT::v8f64, Legal);
1347 setOperationAction(ISD::FDIV, MVT::v8f64, Legal);
1348 setOperationAction(ISD::FSQRT, MVT::v8f64, Legal);
1349 setOperationAction(ISD::FNEG, MVT::v8f64, Custom);
1350 setOperationAction(ISD::FMA, MVT::v8f64, Legal);
1351 setOperationAction(ISD::FMA, MVT::v16f32, Legal);
1353 setOperationAction(ISD::FP_TO_SINT, MVT::v16i32, Legal);
1354 setOperationAction(ISD::FP_TO_UINT, MVT::v16i32, Legal);
1355 setOperationAction(ISD::FP_TO_UINT, MVT::v8i32, Legal);
1356 setOperationAction(ISD::FP_TO_UINT, MVT::v4i32, Legal);
1357 setOperationAction(ISD::SINT_TO_FP, MVT::v16i32, Legal);
1358 setOperationAction(ISD::SINT_TO_FP, MVT::v8i1, Custom);
1359 setOperationAction(ISD::SINT_TO_FP, MVT::v16i1, Custom);
1360 setOperationAction(ISD::SINT_TO_FP, MVT::v16i8, Promote);
1361 setOperationAction(ISD::SINT_TO_FP, MVT::v16i16, Promote);
1362 setOperationAction(ISD::UINT_TO_FP, MVT::v16i32, Legal);
1363 setOperationAction(ISD::UINT_TO_FP, MVT::v8i32, Legal);
1364 setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Legal);
1365 setOperationAction(ISD::UINT_TO_FP, MVT::v16i8, Custom);
1366 setOperationAction(ISD::UINT_TO_FP, MVT::v16i16, Custom);
1367 setOperationAction(ISD::FP_ROUND, MVT::v8f32, Legal);
1368 setOperationAction(ISD::FP_EXTEND, MVT::v8f32, Legal);
1370 setTruncStoreAction(MVT::v8i64, MVT::v8i8, Legal);
1371 setTruncStoreAction(MVT::v8i64, MVT::v8i16, Legal);
1372 setTruncStoreAction(MVT::v8i64, MVT::v8i32, Legal);
1373 setTruncStoreAction(MVT::v16i32, MVT::v16i8, Legal);
1374 setTruncStoreAction(MVT::v16i32, MVT::v16i16, Legal);
1375 if (Subtarget->hasVLX()){
1376 setTruncStoreAction(MVT::v4i64, MVT::v4i8, Legal);
1377 setTruncStoreAction(MVT::v4i64, MVT::v4i16, Legal);
1378 setTruncStoreAction(MVT::v4i64, MVT::v4i32, Legal);
1379 setTruncStoreAction(MVT::v8i32, MVT::v8i8, Legal);
1380 setTruncStoreAction(MVT::v8i32, MVT::v8i16, Legal);
1382 setTruncStoreAction(MVT::v2i64, MVT::v2i8, Legal);
1383 setTruncStoreAction(MVT::v2i64, MVT::v2i16, Legal);
1384 setTruncStoreAction(MVT::v2i64, MVT::v2i32, Legal);
1385 setTruncStoreAction(MVT::v4i32, MVT::v4i8, Legal);
1386 setTruncStoreAction(MVT::v4i32, MVT::v4i16, Legal);
1388 setOperationAction(ISD::TRUNCATE, MVT::i1, Custom);
1389 setOperationAction(ISD::TRUNCATE, MVT::v16i8, Custom);
1390 setOperationAction(ISD::TRUNCATE, MVT::v8i32, Custom);
1391 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v8i1, Custom);
1392 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v16i1, Custom);
1393 if (Subtarget->hasDQI()) {
1394 setOperationAction(ISD::TRUNCATE, MVT::v2i1, Custom);
1395 setOperationAction(ISD::TRUNCATE, MVT::v4i1, Custom);
1397 setOperationAction(ISD::SINT_TO_FP, MVT::v8i64, Legal);
1398 setOperationAction(ISD::UINT_TO_FP, MVT::v8i64, Legal);
1399 setOperationAction(ISD::FP_TO_SINT, MVT::v8i64, Legal);
1400 setOperationAction(ISD::FP_TO_UINT, MVT::v8i64, Legal);
1401 if (Subtarget->hasVLX()) {
1402 setOperationAction(ISD::SINT_TO_FP, MVT::v4i64, Legal);
1403 setOperationAction(ISD::SINT_TO_FP, MVT::v2i64, Legal);
1404 setOperationAction(ISD::UINT_TO_FP, MVT::v4i64, Legal);
1405 setOperationAction(ISD::UINT_TO_FP, MVT::v2i64, Legal);
1406 setOperationAction(ISD::FP_TO_SINT, MVT::v4i64, Legal);
1407 setOperationAction(ISD::FP_TO_SINT, MVT::v2i64, Legal);
1408 setOperationAction(ISD::FP_TO_UINT, MVT::v4i64, Legal);
1409 setOperationAction(ISD::FP_TO_UINT, MVT::v2i64, Legal);
1412 if (Subtarget->hasVLX()) {
1413 setOperationAction(ISD::SINT_TO_FP, MVT::v8i32, Legal);
1414 setOperationAction(ISD::UINT_TO_FP, MVT::v8i32, Legal);
1415 setOperationAction(ISD::FP_TO_SINT, MVT::v8i32, Legal);
1416 setOperationAction(ISD::FP_TO_UINT, MVT::v8i32, Legal);
1417 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal);
1418 setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Legal);
1419 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal);
1420 setOperationAction(ISD::FP_TO_UINT, MVT::v4i32, Legal);
1422 setOperationAction(ISD::TRUNCATE, MVT::v8i1, Custom);
1423 setOperationAction(ISD::TRUNCATE, MVT::v16i1, Custom);
1424 setOperationAction(ISD::TRUNCATE, MVT::v16i16, Custom);
1425 setOperationAction(ISD::ZERO_EXTEND, MVT::v16i32, Custom);
1426 setOperationAction(ISD::ZERO_EXTEND, MVT::v8i64, Custom);
1427 setOperationAction(ISD::ANY_EXTEND, MVT::v16i32, Custom);
1428 setOperationAction(ISD::ANY_EXTEND, MVT::v8i64, Custom);
1429 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i32, Custom);
1430 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i64, Custom);
1431 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i8, Custom);
1432 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i16, Custom);
1433 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i16, Custom);
1434 if (Subtarget->hasDQI()) {
1435 setOperationAction(ISD::SIGN_EXTEND, MVT::v4i32, Custom);
1436 setOperationAction(ISD::SIGN_EXTEND, MVT::v2i64, Custom);
1438 setOperationAction(ISD::FFLOOR, MVT::v16f32, Legal);
1439 setOperationAction(ISD::FFLOOR, MVT::v8f64, Legal);
1440 setOperationAction(ISD::FCEIL, MVT::v16f32, Legal);
1441 setOperationAction(ISD::FCEIL, MVT::v8f64, Legal);
1442 setOperationAction(ISD::FTRUNC, MVT::v16f32, Legal);
1443 setOperationAction(ISD::FTRUNC, MVT::v8f64, Legal);
1444 setOperationAction(ISD::FRINT, MVT::v16f32, Legal);
1445 setOperationAction(ISD::FRINT, MVT::v8f64, Legal);
1446 setOperationAction(ISD::FNEARBYINT, MVT::v16f32, Legal);
1447 setOperationAction(ISD::FNEARBYINT, MVT::v8f64, Legal);
1449 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8f64, Custom);
1450 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i64, Custom);
1451 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16f32, Custom);
1452 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i32, Custom);
1453 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i1, Custom);
1455 setOperationAction(ISD::SETCC, MVT::v16i1, Custom);
1456 setOperationAction(ISD::SETCC, MVT::v8i1, Custom);
1458 setOperationAction(ISD::MUL, MVT::v8i64, Custom);
1460 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i1, Custom);
1461 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i1, Custom);
1462 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i1, Custom);
1463 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i1, Custom);
1464 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i1, Custom);
1465 setOperationAction(ISD::BUILD_VECTOR, MVT::v16i1, Custom);
1466 setOperationAction(ISD::SELECT, MVT::v8f64, Custom);
1467 setOperationAction(ISD::SELECT, MVT::v8i64, Custom);
1468 setOperationAction(ISD::SELECT, MVT::v16f32, Custom);
1469 setOperationAction(ISD::SELECT, MVT::v16i1, Custom);
1470 setOperationAction(ISD::SELECT, MVT::v8i1, Custom);
1472 setOperationAction(ISD::SMAX, MVT::v16i32, Legal);
1473 setOperationAction(ISD::SMAX, MVT::v8i64, Legal);
1474 setOperationAction(ISD::UMAX, MVT::v16i32, Legal);
1475 setOperationAction(ISD::UMAX, MVT::v8i64, Legal);
1476 setOperationAction(ISD::SMIN, MVT::v16i32, Legal);
1477 setOperationAction(ISD::SMIN, MVT::v8i64, Legal);
1478 setOperationAction(ISD::UMIN, MVT::v16i32, Legal);
1479 setOperationAction(ISD::UMIN, MVT::v8i64, Legal);
1481 setOperationAction(ISD::ADD, MVT::v8i64, Legal);
1482 setOperationAction(ISD::ADD, MVT::v16i32, Legal);
1484 setOperationAction(ISD::SUB, MVT::v8i64, Legal);
1485 setOperationAction(ISD::SUB, MVT::v16i32, Legal);
1487 setOperationAction(ISD::MUL, MVT::v16i32, Legal);
1489 setOperationAction(ISD::SRL, MVT::v8i64, Custom);
1490 setOperationAction(ISD::SRL, MVT::v16i32, Custom);
1492 setOperationAction(ISD::SHL, MVT::v8i64, Custom);
1493 setOperationAction(ISD::SHL, MVT::v16i32, Custom);
1495 setOperationAction(ISD::SRA, MVT::v8i64, Custom);
1496 setOperationAction(ISD::SRA, MVT::v16i32, Custom);
1498 setOperationAction(ISD::AND, MVT::v8i64, Legal);
1499 setOperationAction(ISD::OR, MVT::v8i64, Legal);
1500 setOperationAction(ISD::XOR, MVT::v8i64, Legal);
1501 setOperationAction(ISD::AND, MVT::v16i32, Legal);
1502 setOperationAction(ISD::OR, MVT::v16i32, Legal);
1503 setOperationAction(ISD::XOR, MVT::v16i32, Legal);
1505 if (Subtarget->hasCDI()) {
1506 setOperationAction(ISD::CTLZ, MVT::v8i64, Legal);
1507 setOperationAction(ISD::CTLZ, MVT::v16i32, Legal);
1508 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v8i64, Legal);
1509 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v16i32, Legal);
1511 setOperationAction(ISD::CTLZ, MVT::v8i16, Custom);
1512 setOperationAction(ISD::CTLZ, MVT::v16i8, Custom);
1513 setOperationAction(ISD::CTLZ, MVT::v16i16, Custom);
1514 setOperationAction(ISD::CTLZ, MVT::v32i8, Custom);
1515 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v8i16, Custom);
1516 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v16i8, Custom);
1517 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v16i16, Custom);
1518 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v32i8, Custom);
1520 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v8i64, Custom);
1521 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v16i32, Custom);
1523 if (Subtarget->hasVLX()) {
1524 setOperationAction(ISD::CTLZ, MVT::v4i64, Legal);
1525 setOperationAction(ISD::CTLZ, MVT::v8i32, Legal);
1526 setOperationAction(ISD::CTLZ, MVT::v2i64, Legal);
1527 setOperationAction(ISD::CTLZ, MVT::v4i32, Legal);
1528 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v4i64, Legal);
1529 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v8i32, Legal);
1530 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v2i64, Legal);
1531 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v4i32, Legal);
1533 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v4i64, Custom);
1534 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v8i32, Custom);
1535 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v2i64, Custom);
1536 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v4i32, Custom);
1538 setOperationAction(ISD::CTLZ, MVT::v4i64, Custom);
1539 setOperationAction(ISD::CTLZ, MVT::v8i32, Custom);
1540 setOperationAction(ISD::CTLZ, MVT::v2i64, Custom);
1541 setOperationAction(ISD::CTLZ, MVT::v4i32, Custom);
1542 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v4i64, Custom);
1543 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v8i32, Custom);
1544 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v2i64, Custom);
1545 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v4i32, Custom);
1547 } // Subtarget->hasCDI()
1549 if (Subtarget->hasDQI()) {
1550 setOperationAction(ISD::MUL, MVT::v2i64, Legal);
1551 setOperationAction(ISD::MUL, MVT::v4i64, Legal);
1552 setOperationAction(ISD::MUL, MVT::v8i64, Legal);
1554 // Custom lower several nodes.
1555 for (MVT VT : MVT::vector_valuetypes()) {
1556 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
1558 setOperationAction(ISD::AND, VT, Legal);
1559 setOperationAction(ISD::OR, VT, Legal);
1560 setOperationAction(ISD::XOR, VT, Legal);
1562 if (EltSize >= 32 && VT.getSizeInBits() <= 512) {
1563 setOperationAction(ISD::MGATHER, VT, Custom);
1564 setOperationAction(ISD::MSCATTER, VT, Custom);
1566 // Extract subvector is special because the value type
1567 // (result) is 256/128-bit but the source is 512-bit wide.
1568 if (VT.is128BitVector() || VT.is256BitVector()) {
1569 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom);
1571 if (VT.getVectorElementType() == MVT::i1)
1572 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Legal);
1574 // Do not attempt to custom lower other non-512-bit vectors
1575 if (!VT.is512BitVector())
1578 if (EltSize >= 32) {
1579 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1580 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
1581 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1582 setOperationAction(ISD::VSELECT, VT, Legal);
1583 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1584 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom);
1585 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom);
1586 setOperationAction(ISD::MLOAD, VT, Legal);
1587 setOperationAction(ISD::MSTORE, VT, Legal);
1590 for (auto VT : { MVT::v64i8, MVT::v32i16, MVT::v16i32 }) {
1591 setOperationAction(ISD::SELECT, VT, Promote);
1592 AddPromotedToType (ISD::SELECT, VT, MVT::v8i64);
1596 if (!Subtarget->useSoftFloat() && Subtarget->hasBWI()) {
1597 addRegisterClass(MVT::v32i16, &X86::VR512RegClass);
1598 addRegisterClass(MVT::v64i8, &X86::VR512RegClass);
1600 addRegisterClass(MVT::v32i1, &X86::VK32RegClass);
1601 addRegisterClass(MVT::v64i1, &X86::VK64RegClass);
1603 setOperationAction(ISD::LOAD, MVT::v32i16, Legal);
1604 setOperationAction(ISD::LOAD, MVT::v64i8, Legal);
1605 setOperationAction(ISD::SETCC, MVT::v32i1, Custom);
1606 setOperationAction(ISD::SETCC, MVT::v64i1, Custom);
1607 setOperationAction(ISD::ADD, MVT::v32i16, Legal);
1608 setOperationAction(ISD::ADD, MVT::v64i8, Legal);
1609 setOperationAction(ISD::SUB, MVT::v32i16, Legal);
1610 setOperationAction(ISD::SUB, MVT::v64i8, Legal);
1611 setOperationAction(ISD::MUL, MVT::v32i16, Legal);
1612 setOperationAction(ISD::MULHS, MVT::v32i16, Legal);
1613 setOperationAction(ISD::MULHU, MVT::v32i16, Legal);
1614 setOperationAction(ISD::CONCAT_VECTORS, MVT::v32i1, Custom);
1615 setOperationAction(ISD::CONCAT_VECTORS, MVT::v64i1, Custom);
1616 setOperationAction(ISD::CONCAT_VECTORS, MVT::v32i16, Custom);
1617 setOperationAction(ISD::CONCAT_VECTORS, MVT::v64i8, Custom);
1618 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v32i1, Custom);
1619 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v64i1, Custom);
1620 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v32i16, Custom);
1621 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v64i8, Custom);
1622 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v32i16, Custom);
1623 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v64i8, Custom);
1624 setOperationAction(ISD::SELECT, MVT::v32i1, Custom);
1625 setOperationAction(ISD::SELECT, MVT::v64i1, Custom);
1626 setOperationAction(ISD::SIGN_EXTEND, MVT::v32i8, Custom);
1627 setOperationAction(ISD::ZERO_EXTEND, MVT::v32i8, Custom);
1628 setOperationAction(ISD::SIGN_EXTEND, MVT::v32i16, Custom);
1629 setOperationAction(ISD::ZERO_EXTEND, MVT::v32i16, Custom);
1630 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v32i16, Custom);
1631 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v64i8, Custom);
1632 setOperationAction(ISD::SIGN_EXTEND, MVT::v64i8, Custom);
1633 setOperationAction(ISD::ZERO_EXTEND, MVT::v64i8, Custom);
1634 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v32i1, Custom);
1635 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v64i1, Custom);
1636 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v32i16, Custom);
1637 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v64i8, Custom);
1638 setOperationAction(ISD::VSELECT, MVT::v32i16, Legal);
1639 setOperationAction(ISD::VSELECT, MVT::v64i8, Legal);
1640 setOperationAction(ISD::TRUNCATE, MVT::v32i1, Custom);
1641 setOperationAction(ISD::TRUNCATE, MVT::v64i1, Custom);
1642 setOperationAction(ISD::TRUNCATE, MVT::v32i8, Custom);
1643 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v32i1, Custom);
1644 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v64i1, Custom);
1646 setOperationAction(ISD::SMAX, MVT::v64i8, Legal);
1647 setOperationAction(ISD::SMAX, MVT::v32i16, Legal);
1648 setOperationAction(ISD::UMAX, MVT::v64i8, Legal);
1649 setOperationAction(ISD::UMAX, MVT::v32i16, Legal);
1650 setOperationAction(ISD::SMIN, MVT::v64i8, Legal);
1651 setOperationAction(ISD::SMIN, MVT::v32i16, Legal);
1652 setOperationAction(ISD::UMIN, MVT::v64i8, Legal);
1653 setOperationAction(ISD::UMIN, MVT::v32i16, Legal);
1655 setTruncStoreAction(MVT::v32i16, MVT::v32i8, Legal);
1656 setTruncStoreAction(MVT::v16i16, MVT::v16i8, Legal);
1657 if (Subtarget->hasVLX())
1658 setTruncStoreAction(MVT::v8i16, MVT::v8i8, Legal);
1660 if (Subtarget->hasCDI()) {
1661 setOperationAction(ISD::CTLZ, MVT::v32i16, Custom);
1662 setOperationAction(ISD::CTLZ, MVT::v64i8, Custom);
1663 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v32i16, Custom);
1664 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v64i8, Custom);
1667 for (auto VT : { MVT::v64i8, MVT::v32i16 }) {
1668 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1669 setOperationAction(ISD::VSELECT, VT, Legal);
1673 if (!Subtarget->useSoftFloat() && Subtarget->hasVLX()) {
1674 addRegisterClass(MVT::v4i1, &X86::VK4RegClass);
1675 addRegisterClass(MVT::v2i1, &X86::VK2RegClass);
1677 setOperationAction(ISD::SETCC, MVT::v4i1, Custom);
1678 setOperationAction(ISD::SETCC, MVT::v2i1, Custom);
1679 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4i1, Custom);
1680 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i1, Custom);
1681 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v8i1, Custom);
1682 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v4i1, Custom);
1683 setOperationAction(ISD::SELECT, MVT::v4i1, Custom);
1684 setOperationAction(ISD::SELECT, MVT::v2i1, Custom);
1685 setOperationAction(ISD::BUILD_VECTOR, MVT::v4i1, Custom);
1686 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i1, Custom);
1687 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i1, Custom);
1688 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4i1, Custom);
1690 setOperationAction(ISD::AND, MVT::v8i32, Legal);
1691 setOperationAction(ISD::OR, MVT::v8i32, Legal);
1692 setOperationAction(ISD::XOR, MVT::v8i32, Legal);
1693 setOperationAction(ISD::AND, MVT::v4i32, Legal);
1694 setOperationAction(ISD::OR, MVT::v4i32, Legal);
1695 setOperationAction(ISD::XOR, MVT::v4i32, Legal);
1696 setOperationAction(ISD::SRA, MVT::v2i64, Custom);
1697 setOperationAction(ISD::SRA, MVT::v4i64, Custom);
1699 setOperationAction(ISD::SMAX, MVT::v2i64, Legal);
1700 setOperationAction(ISD::SMAX, MVT::v4i64, Legal);
1701 setOperationAction(ISD::UMAX, MVT::v2i64, Legal);
1702 setOperationAction(ISD::UMAX, MVT::v4i64, Legal);
1703 setOperationAction(ISD::SMIN, MVT::v2i64, Legal);
1704 setOperationAction(ISD::SMIN, MVT::v4i64, Legal);
1705 setOperationAction(ISD::UMIN, MVT::v2i64, Legal);
1706 setOperationAction(ISD::UMIN, MVT::v4i64, Legal);
1709 // We want to custom lower some of our intrinsics.
1710 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
1711 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::Other, Custom);
1712 setOperationAction(ISD::INTRINSIC_VOID, MVT::Other, Custom);
1713 if (!Subtarget->is64Bit())
1714 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::i64, Custom);
1716 // Only custom-lower 64-bit SADDO and friends on 64-bit because we don't
1717 // handle type legalization for these operations here.
1719 // FIXME: We really should do custom legalization for addition and
1720 // subtraction on x86-32 once PR3203 is fixed. We really can't do much better
1721 // than generic legalization for 64-bit multiplication-with-overflow, though.
1722 for (auto VT : { MVT::i8, MVT::i16, MVT::i32, MVT::i64 }) {
1723 if (VT == MVT::i64 && !Subtarget->is64Bit())
1725 // Add/Sub/Mul with overflow operations are custom lowered.
1726 setOperationAction(ISD::SADDO, VT, Custom);
1727 setOperationAction(ISD::UADDO, VT, Custom);
1728 setOperationAction(ISD::SSUBO, VT, Custom);
1729 setOperationAction(ISD::USUBO, VT, Custom);
1730 setOperationAction(ISD::SMULO, VT, Custom);
1731 setOperationAction(ISD::UMULO, VT, Custom);
1734 if (!Subtarget->is64Bit()) {
1735 // These libcalls are not available in 32-bit.
1736 setLibcallName(RTLIB::SHL_I128, nullptr);
1737 setLibcallName(RTLIB::SRL_I128, nullptr);
1738 setLibcallName(RTLIB::SRA_I128, nullptr);
1741 // Combine sin / cos into one node or libcall if possible.
1742 if (Subtarget->hasSinCos()) {
1743 setLibcallName(RTLIB::SINCOS_F32, "sincosf");
1744 setLibcallName(RTLIB::SINCOS_F64, "sincos");
1745 if (Subtarget->isTargetDarwin()) {
1746 // For MacOSX, we don't want the normal expansion of a libcall to sincos.
1747 // We want to issue a libcall to __sincos_stret to avoid memory traffic.
1748 setOperationAction(ISD::FSINCOS, MVT::f64, Custom);
1749 setOperationAction(ISD::FSINCOS, MVT::f32, Custom);
1753 if (Subtarget->isTargetWin64()) {
1754 setOperationAction(ISD::SDIV, MVT::i128, Custom);
1755 setOperationAction(ISD::UDIV, MVT::i128, Custom);
1756 setOperationAction(ISD::SREM, MVT::i128, Custom);
1757 setOperationAction(ISD::UREM, MVT::i128, Custom);
1758 setOperationAction(ISD::SDIVREM, MVT::i128, Custom);
1759 setOperationAction(ISD::UDIVREM, MVT::i128, Custom);
1762 // We have target-specific dag combine patterns for the following nodes:
1763 setTargetDAGCombine(ISD::VECTOR_SHUFFLE);
1764 setTargetDAGCombine(ISD::EXTRACT_VECTOR_ELT);
1765 setTargetDAGCombine(ISD::BITCAST);
1766 setTargetDAGCombine(ISD::VSELECT);
1767 setTargetDAGCombine(ISD::SELECT);
1768 setTargetDAGCombine(ISD::SHL);
1769 setTargetDAGCombine(ISD::SRA);
1770 setTargetDAGCombine(ISD::SRL);
1771 setTargetDAGCombine(ISD::OR);
1772 setTargetDAGCombine(ISD::AND);
1773 setTargetDAGCombine(ISD::ADD);
1774 setTargetDAGCombine(ISD::FADD);
1775 setTargetDAGCombine(ISD::FSUB);
1776 setTargetDAGCombine(ISD::FNEG);
1777 setTargetDAGCombine(ISD::FMA);
1778 setTargetDAGCombine(ISD::SUB);
1779 setTargetDAGCombine(ISD::LOAD);
1780 setTargetDAGCombine(ISD::MLOAD);
1781 setTargetDAGCombine(ISD::STORE);
1782 setTargetDAGCombine(ISD::MSTORE);
1783 setTargetDAGCombine(ISD::TRUNCATE);
1784 setTargetDAGCombine(ISD::ZERO_EXTEND);
1785 setTargetDAGCombine(ISD::ANY_EXTEND);
1786 setTargetDAGCombine(ISD::SIGN_EXTEND);
1787 setTargetDAGCombine(ISD::SIGN_EXTEND_INREG);
1788 setTargetDAGCombine(ISD::SINT_TO_FP);
1789 setTargetDAGCombine(ISD::UINT_TO_FP);
1790 setTargetDAGCombine(ISD::SETCC);
1791 setTargetDAGCombine(ISD::BUILD_VECTOR);
1792 setTargetDAGCombine(ISD::MUL);
1793 setTargetDAGCombine(ISD::XOR);
1795 computeRegisterProperties(Subtarget->getRegisterInfo());
1797 MaxStoresPerMemset = 16; // For @llvm.memset -> sequence of stores
1798 MaxStoresPerMemsetOptSize = 8;
1799 MaxStoresPerMemcpy = 8; // For @llvm.memcpy -> sequence of stores
1800 MaxStoresPerMemcpyOptSize = 4;
1801 MaxStoresPerMemmove = 8; // For @llvm.memmove -> sequence of stores
1802 MaxStoresPerMemmoveOptSize = 4;
1803 setPrefLoopAlignment(4); // 2^4 bytes.
1805 // A predictable cmov does not hurt on an in-order CPU.
1806 // FIXME: Use a CPU attribute to trigger this, not a CPU model.
1807 PredictableSelectIsExpensive = !Subtarget->isAtom();
1808 EnableExtLdPromotion = true;
1809 setPrefFunctionAlignment(4); // 2^4 bytes.
1811 verifyIntrinsicTables();
1814 // This has so far only been implemented for 64-bit MachO.
1815 bool X86TargetLowering::useLoadStackGuardNode() const {
1816 return Subtarget->isTargetMachO() && Subtarget->is64Bit();
1819 TargetLoweringBase::LegalizeTypeAction
1820 X86TargetLowering::getPreferredVectorAction(EVT VT) const {
1821 if (ExperimentalVectorWideningLegalization &&
1822 VT.getVectorNumElements() != 1 &&
1823 VT.getVectorElementType().getSimpleVT() != MVT::i1)
1824 return TypeWidenVector;
1826 return TargetLoweringBase::getPreferredVectorAction(VT);
1829 EVT X86TargetLowering::getSetCCResultType(const DataLayout &DL, LLVMContext &,
1832 return Subtarget->hasAVX512() ? MVT::i1: MVT::i8;
1834 if (VT.isSimple()) {
1835 MVT VVT = VT.getSimpleVT();
1836 const unsigned NumElts = VVT.getVectorNumElements();
1837 const MVT EltVT = VVT.getVectorElementType();
1838 if (VVT.is512BitVector()) {
1839 if (Subtarget->hasAVX512())
1840 if (EltVT == MVT::i32 || EltVT == MVT::i64 ||
1841 EltVT == MVT::f32 || EltVT == MVT::f64)
1843 case 8: return MVT::v8i1;
1844 case 16: return MVT::v16i1;
1846 if (Subtarget->hasBWI())
1847 if (EltVT == MVT::i8 || EltVT == MVT::i16)
1849 case 32: return MVT::v32i1;
1850 case 64: return MVT::v64i1;
1854 if (VVT.is256BitVector() || VVT.is128BitVector()) {
1855 if (Subtarget->hasVLX())
1856 if (EltVT == MVT::i32 || EltVT == MVT::i64 ||
1857 EltVT == MVT::f32 || EltVT == MVT::f64)
1859 case 2: return MVT::v2i1;
1860 case 4: return MVT::v4i1;
1861 case 8: return MVT::v8i1;
1863 if (Subtarget->hasBWI() && Subtarget->hasVLX())
1864 if (EltVT == MVT::i8 || EltVT == MVT::i16)
1866 case 8: return MVT::v8i1;
1867 case 16: return MVT::v16i1;
1868 case 32: return MVT::v32i1;
1873 return VT.changeVectorElementTypeToInteger();
1876 /// Helper for getByValTypeAlignment to determine
1877 /// the desired ByVal argument alignment.
1878 static void getMaxByValAlign(Type *Ty, unsigned &MaxAlign) {
1881 if (VectorType *VTy = dyn_cast<VectorType>(Ty)) {
1882 if (VTy->getBitWidth() == 128)
1884 } else if (ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
1885 unsigned EltAlign = 0;
1886 getMaxByValAlign(ATy->getElementType(), EltAlign);
1887 if (EltAlign > MaxAlign)
1888 MaxAlign = EltAlign;
1889 } else if (StructType *STy = dyn_cast<StructType>(Ty)) {
1890 for (auto *EltTy : STy->elements()) {
1891 unsigned EltAlign = 0;
1892 getMaxByValAlign(EltTy, EltAlign);
1893 if (EltAlign > MaxAlign)
1894 MaxAlign = EltAlign;
1901 /// Return the desired alignment for ByVal aggregate
1902 /// function arguments in the caller parameter area. For X86, aggregates
1903 /// that contain SSE vectors are placed at 16-byte boundaries while the rest
1904 /// are at 4-byte boundaries.
1905 unsigned X86TargetLowering::getByValTypeAlignment(Type *Ty,
1906 const DataLayout &DL) const {
1907 if (Subtarget->is64Bit()) {
1908 // Max of 8 and alignment of type.
1909 unsigned TyAlign = DL.getABITypeAlignment(Ty);
1916 if (Subtarget->hasSSE1())
1917 getMaxByValAlign(Ty, Align);
1921 /// Returns the target specific optimal type for load
1922 /// and store operations as a result of memset, memcpy, and memmove
1923 /// lowering. If DstAlign is zero that means it's safe to destination
1924 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
1925 /// means there isn't a need to check it against alignment requirement,
1926 /// probably because the source does not need to be loaded. If 'IsMemset' is
1927 /// true, that means it's expanding a memset. If 'ZeroMemset' is true, that
1928 /// means it's a memset of zero. 'MemcpyStrSrc' indicates whether the memcpy
1929 /// source is constant so it does not need to be loaded.
1930 /// It returns EVT::Other if the type should be determined using generic
1931 /// target-independent logic.
1933 X86TargetLowering::getOptimalMemOpType(uint64_t Size,
1934 unsigned DstAlign, unsigned SrcAlign,
1935 bool IsMemset, bool ZeroMemset,
1937 MachineFunction &MF) const {
1938 const Function *F = MF.getFunction();
1939 if ((!IsMemset || ZeroMemset) &&
1940 !F->hasFnAttribute(Attribute::NoImplicitFloat)) {
1942 (!Subtarget->isUnalignedMem16Slow() ||
1943 ((DstAlign == 0 || DstAlign >= 16) &&
1944 (SrcAlign == 0 || SrcAlign >= 16)))) {
1946 // FIXME: Check if unaligned 32-byte accesses are slow.
1947 if (Subtarget->hasInt256())
1949 if (Subtarget->hasFp256())
1952 if (Subtarget->hasSSE2())
1954 if (Subtarget->hasSSE1())
1956 } else if (!MemcpyStrSrc && Size >= 8 &&
1957 !Subtarget->is64Bit() &&
1958 Subtarget->hasSSE2()) {
1959 // Do not use f64 to lower memcpy if source is string constant. It's
1960 // better to use i32 to avoid the loads.
1964 // This is a compromise. If we reach here, unaligned accesses may be slow on
1965 // this target. However, creating smaller, aligned accesses could be even
1966 // slower and would certainly be a lot more code.
1967 if (Subtarget->is64Bit() && Size >= 8)
1972 bool X86TargetLowering::isSafeMemOpType(MVT VT) const {
1974 return X86ScalarSSEf32;
1975 else if (VT == MVT::f64)
1976 return X86ScalarSSEf64;
1981 X86TargetLowering::allowsMisalignedMemoryAccesses(EVT VT,
1986 switch (VT.getSizeInBits()) {
1988 // 8-byte and under are always assumed to be fast.
1992 *Fast = !Subtarget->isUnalignedMem16Slow();
1995 *Fast = !Subtarget->isUnalignedMem32Slow();
1997 // TODO: What about AVX-512 (512-bit) accesses?
2000 // Misaligned accesses of any size are always allowed.
2004 /// Return the entry encoding for a jump table in the
2005 /// current function. The returned value is a member of the
2006 /// MachineJumpTableInfo::JTEntryKind enum.
2007 unsigned X86TargetLowering::getJumpTableEncoding() const {
2008 // In GOT pic mode, each entry in the jump table is emitted as a @GOTOFF
2010 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
2011 Subtarget->isPICStyleGOT())
2012 return MachineJumpTableInfo::EK_Custom32;
2014 // Otherwise, use the normal jump table encoding heuristics.
2015 return TargetLowering::getJumpTableEncoding();
2018 bool X86TargetLowering::useSoftFloat() const {
2019 return Subtarget->useSoftFloat();
2023 X86TargetLowering::LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI,
2024 const MachineBasicBlock *MBB,
2025 unsigned uid,MCContext &Ctx) const{
2026 assert(MBB->getParent()->getTarget().getRelocationModel() == Reloc::PIC_ &&
2027 Subtarget->isPICStyleGOT());
2028 // In 32-bit ELF systems, our jump table entries are formed with @GOTOFF
2030 return MCSymbolRefExpr::create(MBB->getSymbol(),
2031 MCSymbolRefExpr::VK_GOTOFF, Ctx);
2034 /// Returns relocation base for the given PIC jumptable.
2035 SDValue X86TargetLowering::getPICJumpTableRelocBase(SDValue Table,
2036 SelectionDAG &DAG) const {
2037 if (!Subtarget->is64Bit())
2038 // This doesn't have SDLoc associated with it, but is not really the
2039 // same as a Register.
2040 return DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(),
2041 getPointerTy(DAG.getDataLayout()));
2045 /// This returns the relocation base for the given PIC jumptable,
2046 /// the same as getPICJumpTableRelocBase, but as an MCExpr.
2047 const MCExpr *X86TargetLowering::
2048 getPICJumpTableRelocBaseExpr(const MachineFunction *MF, unsigned JTI,
2049 MCContext &Ctx) const {
2050 // X86-64 uses RIP relative addressing based on the jump table label.
2051 if (Subtarget->isPICStyleRIPRel())
2052 return TargetLowering::getPICJumpTableRelocBaseExpr(MF, JTI, Ctx);
2054 // Otherwise, the reference is relative to the PIC base.
2055 return MCSymbolRefExpr::create(MF->getPICBaseSymbol(), Ctx);
2058 std::pair<const TargetRegisterClass *, uint8_t>
2059 X86TargetLowering::findRepresentativeClass(const TargetRegisterInfo *TRI,
2061 const TargetRegisterClass *RRC = nullptr;
2063 switch (VT.SimpleTy) {
2065 return TargetLowering::findRepresentativeClass(TRI, VT);
2066 case MVT::i8: case MVT::i16: case MVT::i32: case MVT::i64:
2067 RRC = Subtarget->is64Bit() ? &X86::GR64RegClass : &X86::GR32RegClass;
2070 RRC = &X86::VR64RegClass;
2072 case MVT::f32: case MVT::f64:
2073 case MVT::v16i8: case MVT::v8i16: case MVT::v4i32: case MVT::v2i64:
2074 case MVT::v4f32: case MVT::v2f64:
2075 case MVT::v32i8: case MVT::v8i32: case MVT::v4i64: case MVT::v8f32:
2077 RRC = &X86::VR128RegClass;
2080 return std::make_pair(RRC, Cost);
2083 bool X86TargetLowering::getStackCookieLocation(unsigned &AddressSpace,
2084 unsigned &Offset) const {
2085 if (!Subtarget->isTargetLinux())
2088 if (Subtarget->is64Bit()) {
2089 // %fs:0x28, unless we're using a Kernel code model, in which case it's %gs:
2091 if (getTargetMachine().getCodeModel() == CodeModel::Kernel)
2103 Value *X86TargetLowering::getSafeStackPointerLocation(IRBuilder<> &IRB) const {
2104 if (!Subtarget->isTargetAndroid())
2105 return TargetLowering::getSafeStackPointerLocation(IRB);
2107 // Android provides a fixed TLS slot for the SafeStack pointer. See the
2108 // definition of TLS_SLOT_SAFESTACK in
2109 // https://android.googlesource.com/platform/bionic/+/master/libc/private/bionic_tls.h
2110 unsigned AddressSpace, Offset;
2111 if (Subtarget->is64Bit()) {
2112 // %fs:0x48, unless we're using a Kernel code model, in which case it's %gs:
2114 if (getTargetMachine().getCodeModel() == CodeModel::Kernel)
2124 return ConstantExpr::getIntToPtr(
2125 ConstantInt::get(Type::getInt32Ty(IRB.getContext()), Offset),
2126 Type::getInt8PtrTy(IRB.getContext())->getPointerTo(AddressSpace));
2129 bool X86TargetLowering::isNoopAddrSpaceCast(unsigned SrcAS,
2130 unsigned DestAS) const {
2131 assert(SrcAS != DestAS && "Expected different address spaces!");
2133 return SrcAS < 256 && DestAS < 256;
2136 //===----------------------------------------------------------------------===//
2137 // Return Value Calling Convention Implementation
2138 //===----------------------------------------------------------------------===//
2140 #include "X86GenCallingConv.inc"
2142 bool X86TargetLowering::CanLowerReturn(
2143 CallingConv::ID CallConv, MachineFunction &MF, bool isVarArg,
2144 const SmallVectorImpl<ISD::OutputArg> &Outs, LLVMContext &Context) const {
2145 SmallVector<CCValAssign, 16> RVLocs;
2146 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, Context);
2147 return CCInfo.CheckReturn(Outs, RetCC_X86);
2150 const MCPhysReg *X86TargetLowering::getScratchRegisters(CallingConv::ID) const {
2151 static const MCPhysReg ScratchRegs[] = { X86::R11, 0 };
2156 X86TargetLowering::LowerReturn(SDValue Chain,
2157 CallingConv::ID CallConv, bool isVarArg,
2158 const SmallVectorImpl<ISD::OutputArg> &Outs,
2159 const SmallVectorImpl<SDValue> &OutVals,
2160 SDLoc dl, SelectionDAG &DAG) const {
2161 MachineFunction &MF = DAG.getMachineFunction();
2162 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
2164 SmallVector<CCValAssign, 16> RVLocs;
2165 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, *DAG.getContext());
2166 CCInfo.AnalyzeReturn(Outs, RetCC_X86);
2169 SmallVector<SDValue, 6> RetOps;
2170 RetOps.push_back(Chain); // Operand #0 = Chain (updated below)
2171 // Operand #1 = Bytes To Pop
2172 RetOps.push_back(DAG.getTargetConstant(FuncInfo->getBytesToPopOnReturn(), dl,
2175 // Copy the result values into the output registers.
2176 for (unsigned i = 0; i != RVLocs.size(); ++i) {
2177 CCValAssign &VA = RVLocs[i];
2178 assert(VA.isRegLoc() && "Can only return in registers!");
2179 SDValue ValToCopy = OutVals[i];
2180 EVT ValVT = ValToCopy.getValueType();
2182 // Promote values to the appropriate types.
2183 if (VA.getLocInfo() == CCValAssign::SExt)
2184 ValToCopy = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), ValToCopy);
2185 else if (VA.getLocInfo() == CCValAssign::ZExt)
2186 ValToCopy = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), ValToCopy);
2187 else if (VA.getLocInfo() == CCValAssign::AExt) {
2188 if (ValVT.isVector() && ValVT.getVectorElementType() == MVT::i1)
2189 ValToCopy = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), ValToCopy);
2191 ValToCopy = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), ValToCopy);
2193 else if (VA.getLocInfo() == CCValAssign::BCvt)
2194 ValToCopy = DAG.getBitcast(VA.getLocVT(), ValToCopy);
2196 assert(VA.getLocInfo() != CCValAssign::FPExt &&
2197 "Unexpected FP-extend for return value.");
2199 // If this is x86-64, and we disabled SSE, we can't return FP values,
2200 // or SSE or MMX vectors.
2201 if ((ValVT == MVT::f32 || ValVT == MVT::f64 ||
2202 VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) &&
2203 (Subtarget->is64Bit() && !Subtarget->hasSSE1())) {
2204 report_fatal_error("SSE register return with SSE disabled");
2206 // Likewise we can't return F64 values with SSE1 only. gcc does so, but
2207 // llvm-gcc has never done it right and no one has noticed, so this
2208 // should be OK for now.
2209 if (ValVT == MVT::f64 &&
2210 (Subtarget->is64Bit() && !Subtarget->hasSSE2()))
2211 report_fatal_error("SSE2 register return with SSE2 disabled");
2213 // Returns in ST0/ST1 are handled specially: these are pushed as operands to
2214 // the RET instruction and handled by the FP Stackifier.
2215 if (VA.getLocReg() == X86::FP0 ||
2216 VA.getLocReg() == X86::FP1) {
2217 // If this is a copy from an xmm register to ST(0), use an FPExtend to
2218 // change the value to the FP stack register class.
2219 if (isScalarFPTypeInSSEReg(VA.getValVT()))
2220 ValToCopy = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f80, ValToCopy);
2221 RetOps.push_back(ValToCopy);
2222 // Don't emit a copytoreg.
2226 // 64-bit vector (MMX) values are returned in XMM0 / XMM1 except for v1i64
2227 // which is returned in RAX / RDX.
2228 if (Subtarget->is64Bit()) {
2229 if (ValVT == MVT::x86mmx) {
2230 if (VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) {
2231 ValToCopy = DAG.getBitcast(MVT::i64, ValToCopy);
2232 ValToCopy = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
2234 // If we don't have SSE2 available, convert to v4f32 so the generated
2235 // register is legal.
2236 if (!Subtarget->hasSSE2())
2237 ValToCopy = DAG.getBitcast(MVT::v4f32, ValToCopy);
2242 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), ValToCopy, Flag);
2243 Flag = Chain.getValue(1);
2244 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
2247 // All x86 ABIs require that for returning structs by value we copy
2248 // the sret argument into %rax/%eax (depending on ABI) for the return.
2249 // We saved the argument into a virtual register in the entry block,
2250 // so now we copy the value out and into %rax/%eax.
2252 // Checking Function.hasStructRetAttr() here is insufficient because the IR
2253 // may not have an explicit sret argument. If FuncInfo.CanLowerReturn is
2254 // false, then an sret argument may be implicitly inserted in the SelDAG. In
2255 // either case FuncInfo->setSRetReturnReg() will have been called.
2256 if (unsigned SRetReg = FuncInfo->getSRetReturnReg()) {
2257 SDValue Val = DAG.getCopyFromReg(Chain, dl, SRetReg,
2258 getPointerTy(MF.getDataLayout()));
2261 = (Subtarget->is64Bit() && !Subtarget->isTarget64BitILP32()) ?
2262 X86::RAX : X86::EAX;
2263 Chain = DAG.getCopyToReg(Chain, dl, RetValReg, Val, Flag);
2264 Flag = Chain.getValue(1);
2266 // RAX/EAX now acts like a return value.
2268 DAG.getRegister(RetValReg, getPointerTy(DAG.getDataLayout())));
2271 RetOps[0] = Chain; // Update chain.
2273 // Add the flag if we have it.
2275 RetOps.push_back(Flag);
2277 return DAG.getNode(X86ISD::RET_FLAG, dl, MVT::Other, RetOps);
2280 bool X86TargetLowering::isUsedByReturnOnly(SDNode *N, SDValue &Chain) const {
2281 if (N->getNumValues() != 1)
2283 if (!N->hasNUsesOfValue(1, 0))
2286 SDValue TCChain = Chain;
2287 SDNode *Copy = *N->use_begin();
2288 if (Copy->getOpcode() == ISD::CopyToReg) {
2289 // If the copy has a glue operand, we conservatively assume it isn't safe to
2290 // perform a tail call.
2291 if (Copy->getOperand(Copy->getNumOperands()-1).getValueType() == MVT::Glue)
2293 TCChain = Copy->getOperand(0);
2294 } else if (Copy->getOpcode() != ISD::FP_EXTEND)
2297 bool HasRet = false;
2298 for (SDNode::use_iterator UI = Copy->use_begin(), UE = Copy->use_end();
2300 if (UI->getOpcode() != X86ISD::RET_FLAG)
2302 // If we are returning more than one value, we can definitely
2303 // not make a tail call see PR19530
2304 if (UI->getNumOperands() > 4)
2306 if (UI->getNumOperands() == 4 &&
2307 UI->getOperand(UI->getNumOperands()-1).getValueType() != MVT::Glue)
2320 X86TargetLowering::getTypeForExtArgOrReturn(LLVMContext &Context, EVT VT,
2321 ISD::NodeType ExtendKind) const {
2323 // TODO: Is this also valid on 32-bit?
2324 if (Subtarget->is64Bit() && VT == MVT::i1 && ExtendKind == ISD::ZERO_EXTEND)
2325 ReturnMVT = MVT::i8;
2327 ReturnMVT = MVT::i32;
2329 EVT MinVT = getRegisterType(Context, ReturnMVT);
2330 return VT.bitsLT(MinVT) ? MinVT : VT;
2333 /// Lower the result values of a call into the
2334 /// appropriate copies out of appropriate physical registers.
2337 X86TargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
2338 CallingConv::ID CallConv, bool isVarArg,
2339 const SmallVectorImpl<ISD::InputArg> &Ins,
2340 SDLoc dl, SelectionDAG &DAG,
2341 SmallVectorImpl<SDValue> &InVals) const {
2343 // Assign locations to each value returned by this call.
2344 SmallVector<CCValAssign, 16> RVLocs;
2345 bool Is64Bit = Subtarget->is64Bit();
2346 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
2348 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
2350 // Copy all of the result registers out of their specified physreg.
2351 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
2352 CCValAssign &VA = RVLocs[i];
2353 EVT CopyVT = VA.getLocVT();
2355 // If this is x86-64, and we disabled SSE, we can't return FP values
2356 if ((CopyVT == MVT::f32 || CopyVT == MVT::f64) &&
2357 ((Is64Bit || Ins[i].Flags.isInReg()) && !Subtarget->hasSSE1())) {
2358 report_fatal_error("SSE register return with SSE disabled");
2361 // If we prefer to use the value in xmm registers, copy it out as f80 and
2362 // use a truncate to move it from fp stack reg to xmm reg.
2363 bool RoundAfterCopy = false;
2364 if ((VA.getLocReg() == X86::FP0 || VA.getLocReg() == X86::FP1) &&
2365 isScalarFPTypeInSSEReg(VA.getValVT())) {
2367 RoundAfterCopy = (CopyVT != VA.getLocVT());
2370 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(),
2371 CopyVT, InFlag).getValue(1);
2372 SDValue Val = Chain.getValue(0);
2375 Val = DAG.getNode(ISD::FP_ROUND, dl, VA.getValVT(), Val,
2376 // This truncation won't change the value.
2377 DAG.getIntPtrConstant(1, dl));
2379 if (VA.isExtInLoc() && VA.getValVT().getScalarType() == MVT::i1)
2380 Val = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Val);
2382 InFlag = Chain.getValue(2);
2383 InVals.push_back(Val);
2389 //===----------------------------------------------------------------------===//
2390 // C & StdCall & Fast Calling Convention implementation
2391 //===----------------------------------------------------------------------===//
2392 // StdCall calling convention seems to be standard for many Windows' API
2393 // routines and around. It differs from C calling convention just a little:
2394 // callee should clean up the stack, not caller. Symbols should be also
2395 // decorated in some fancy way :) It doesn't support any vector arguments.
2396 // For info on fast calling convention see Fast Calling Convention (tail call)
2397 // implementation LowerX86_32FastCCCallTo.
2399 /// CallIsStructReturn - Determines whether a call uses struct return
2401 enum StructReturnType {
2406 static StructReturnType
2407 callIsStructReturn(const SmallVectorImpl<ISD::OutputArg> &Outs) {
2409 return NotStructReturn;
2411 const ISD::ArgFlagsTy &Flags = Outs[0].Flags;
2412 if (!Flags.isSRet())
2413 return NotStructReturn;
2414 if (Flags.isInReg())
2415 return RegStructReturn;
2416 return StackStructReturn;
2419 /// Determines whether a function uses struct return semantics.
2420 static StructReturnType
2421 argsAreStructReturn(const SmallVectorImpl<ISD::InputArg> &Ins) {
2423 return NotStructReturn;
2425 const ISD::ArgFlagsTy &Flags = Ins[0].Flags;
2426 if (!Flags.isSRet())
2427 return NotStructReturn;
2428 if (Flags.isInReg())
2429 return RegStructReturn;
2430 return StackStructReturn;
2433 /// Make a copy of an aggregate at address specified by "Src" to address
2434 /// "Dst" with size and alignment information specified by the specific
2435 /// parameter attribute. The copy will be passed as a byval function parameter.
2437 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
2438 ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
2440 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), dl, MVT::i32);
2442 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
2443 /*isVolatile*/false, /*AlwaysInline=*/true,
2444 /*isTailCall*/false,
2445 MachinePointerInfo(), MachinePointerInfo());
2448 /// Return true if the calling convention is one that we can guarantee TCO for.
2449 static bool canGuaranteeTCO(CallingConv::ID CC) {
2450 return (CC == CallingConv::Fast || CC == CallingConv::GHC ||
2451 CC == CallingConv::HiPE || CC == CallingConv::HHVM);
2454 /// Return true if we might ever do TCO for calls with this calling convention.
2455 static bool mayTailCallThisCC(CallingConv::ID CC) {
2457 // C calling conventions:
2458 case CallingConv::C:
2459 case CallingConv::X86_64_Win64:
2460 case CallingConv::X86_64_SysV:
2461 // Callee pop conventions:
2462 case CallingConv::X86_ThisCall:
2463 case CallingConv::X86_StdCall:
2464 case CallingConv::X86_VectorCall:
2465 case CallingConv::X86_FastCall:
2468 return canGuaranteeTCO(CC);
2472 /// Return true if the function is being made into a tailcall target by
2473 /// changing its ABI.
2474 static bool shouldGuaranteeTCO(CallingConv::ID CC, bool GuaranteedTailCallOpt) {
2475 return GuaranteedTailCallOpt && canGuaranteeTCO(CC);
2478 bool X86TargetLowering::mayBeEmittedAsTailCall(CallInst *CI) const {
2480 CI->getParent()->getParent()->getFnAttribute("disable-tail-calls");
2481 if (!CI->isTailCall() || Attr.getValueAsString() == "true")
2485 CallingConv::ID CalleeCC = CS.getCallingConv();
2486 if (!mayTailCallThisCC(CalleeCC))
2493 X86TargetLowering::LowerMemArgument(SDValue Chain,
2494 CallingConv::ID CallConv,
2495 const SmallVectorImpl<ISD::InputArg> &Ins,
2496 SDLoc dl, SelectionDAG &DAG,
2497 const CCValAssign &VA,
2498 MachineFrameInfo *MFI,
2500 // Create the nodes corresponding to a load from this parameter slot.
2501 ISD::ArgFlagsTy Flags = Ins[i].Flags;
2502 bool AlwaysUseMutable = shouldGuaranteeTCO(
2503 CallConv, DAG.getTarget().Options.GuaranteedTailCallOpt);
2504 bool isImmutable = !AlwaysUseMutable && !Flags.isByVal();
2507 // If value is passed by pointer we have address passed instead of the value
2509 bool ExtendedInMem = VA.isExtInLoc() &&
2510 VA.getValVT().getScalarType() == MVT::i1;
2512 if (VA.getLocInfo() == CCValAssign::Indirect || ExtendedInMem)
2513 ValVT = VA.getLocVT();
2515 ValVT = VA.getValVT();
2517 // FIXME: For now, all byval parameter objects are marked mutable. This can be
2518 // changed with more analysis.
2519 // In case of tail call optimization mark all arguments mutable. Since they
2520 // could be overwritten by lowering of arguments in case of a tail call.
2521 if (Flags.isByVal()) {
2522 unsigned Bytes = Flags.getByValSize();
2523 if (Bytes == 0) Bytes = 1; // Don't create zero-sized stack objects.
2524 int FI = MFI->CreateFixedObject(Bytes, VA.getLocMemOffset(), isImmutable);
2525 return DAG.getFrameIndex(FI, getPointerTy(DAG.getDataLayout()));
2527 int FI = MFI->CreateFixedObject(ValVT.getSizeInBits()/8,
2528 VA.getLocMemOffset(), isImmutable);
2529 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy(DAG.getDataLayout()));
2530 SDValue Val = DAG.getLoad(
2531 ValVT, dl, Chain, FIN,
2532 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FI), false,
2534 return ExtendedInMem ?
2535 DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Val) : Val;
2539 // FIXME: Get this from tablegen.
2540 static ArrayRef<MCPhysReg> get64BitArgumentGPRs(CallingConv::ID CallConv,
2541 const X86Subtarget *Subtarget) {
2542 assert(Subtarget->is64Bit());
2544 if (Subtarget->isCallingConvWin64(CallConv)) {
2545 static const MCPhysReg GPR64ArgRegsWin64[] = {
2546 X86::RCX, X86::RDX, X86::R8, X86::R9
2548 return makeArrayRef(std::begin(GPR64ArgRegsWin64), std::end(GPR64ArgRegsWin64));
2551 static const MCPhysReg GPR64ArgRegs64Bit[] = {
2552 X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9
2554 return makeArrayRef(std::begin(GPR64ArgRegs64Bit), std::end(GPR64ArgRegs64Bit));
2557 // FIXME: Get this from tablegen.
2558 static ArrayRef<MCPhysReg> get64BitArgumentXMMs(MachineFunction &MF,
2559 CallingConv::ID CallConv,
2560 const X86Subtarget *Subtarget) {
2561 assert(Subtarget->is64Bit());
2562 if (Subtarget->isCallingConvWin64(CallConv)) {
2563 // The XMM registers which might contain var arg parameters are shadowed
2564 // in their paired GPR. So we only need to save the GPR to their home
2566 // TODO: __vectorcall will change this.
2570 const Function *Fn = MF.getFunction();
2571 bool NoImplicitFloatOps = Fn->hasFnAttribute(Attribute::NoImplicitFloat);
2572 bool isSoftFloat = Subtarget->useSoftFloat();
2573 assert(!(isSoftFloat && NoImplicitFloatOps) &&
2574 "SSE register cannot be used when SSE is disabled!");
2575 if (isSoftFloat || NoImplicitFloatOps || !Subtarget->hasSSE1())
2576 // Kernel mode asks for SSE to be disabled, so there are no XMM argument
2580 static const MCPhysReg XMMArgRegs64Bit[] = {
2581 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
2582 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
2584 return makeArrayRef(std::begin(XMMArgRegs64Bit), std::end(XMMArgRegs64Bit));
2587 SDValue X86TargetLowering::LowerFormalArguments(
2588 SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
2589 const SmallVectorImpl<ISD::InputArg> &Ins, SDLoc dl, SelectionDAG &DAG,
2590 SmallVectorImpl<SDValue> &InVals) const {
2591 MachineFunction &MF = DAG.getMachineFunction();
2592 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
2593 const TargetFrameLowering &TFI = *Subtarget->getFrameLowering();
2595 const Function* Fn = MF.getFunction();
2596 if (Fn->hasExternalLinkage() &&
2597 Subtarget->isTargetCygMing() &&
2598 Fn->getName() == "main")
2599 FuncInfo->setForceFramePointer(true);
2601 MachineFrameInfo *MFI = MF.getFrameInfo();
2602 bool Is64Bit = Subtarget->is64Bit();
2603 bool IsWin64 = Subtarget->isCallingConvWin64(CallConv);
2605 assert(!(isVarArg && canGuaranteeTCO(CallConv)) &&
2606 "Var args not supported with calling convention fastcc, ghc or hipe");
2608 // Assign locations to all of the incoming arguments.
2609 SmallVector<CCValAssign, 16> ArgLocs;
2610 CCState CCInfo(CallConv, isVarArg, MF, ArgLocs, *DAG.getContext());
2612 // Allocate shadow area for Win64
2614 CCInfo.AllocateStack(32, 8);
2616 CCInfo.AnalyzeFormalArguments(Ins, CC_X86);
2618 unsigned LastVal = ~0U;
2620 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2621 CCValAssign &VA = ArgLocs[i];
2622 // TODO: If an arg is passed in two places (e.g. reg and stack), skip later
2624 assert(VA.getValNo() != LastVal &&
2625 "Don't support value assigned to multiple locs yet");
2627 LastVal = VA.getValNo();
2629 if (VA.isRegLoc()) {
2630 EVT RegVT = VA.getLocVT();
2631 const TargetRegisterClass *RC;
2632 if (RegVT == MVT::i32)
2633 RC = &X86::GR32RegClass;
2634 else if (Is64Bit && RegVT == MVT::i64)
2635 RC = &X86::GR64RegClass;
2636 else if (RegVT == MVT::f32)
2637 RC = &X86::FR32RegClass;
2638 else if (RegVT == MVT::f64)
2639 RC = &X86::FR64RegClass;
2640 else if (RegVT.is512BitVector())
2641 RC = &X86::VR512RegClass;
2642 else if (RegVT.is256BitVector())
2643 RC = &X86::VR256RegClass;
2644 else if (RegVT.is128BitVector())
2645 RC = &X86::VR128RegClass;
2646 else if (RegVT == MVT::x86mmx)
2647 RC = &X86::VR64RegClass;
2648 else if (RegVT == MVT::i1)
2649 RC = &X86::VK1RegClass;
2650 else if (RegVT == MVT::v8i1)
2651 RC = &X86::VK8RegClass;
2652 else if (RegVT == MVT::v16i1)
2653 RC = &X86::VK16RegClass;
2654 else if (RegVT == MVT::v32i1)
2655 RC = &X86::VK32RegClass;
2656 else if (RegVT == MVT::v64i1)
2657 RC = &X86::VK64RegClass;
2659 llvm_unreachable("Unknown argument type!");
2661 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
2662 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
2664 // If this is an 8 or 16-bit value, it is really passed promoted to 32
2665 // bits. Insert an assert[sz]ext to capture this, then truncate to the
2667 if (VA.getLocInfo() == CCValAssign::SExt)
2668 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
2669 DAG.getValueType(VA.getValVT()));
2670 else if (VA.getLocInfo() == CCValAssign::ZExt)
2671 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
2672 DAG.getValueType(VA.getValVT()));
2673 else if (VA.getLocInfo() == CCValAssign::BCvt)
2674 ArgValue = DAG.getBitcast(VA.getValVT(), ArgValue);
2676 if (VA.isExtInLoc()) {
2677 // Handle MMX values passed in XMM regs.
2678 if (RegVT.isVector() && VA.getValVT().getScalarType() != MVT::i1)
2679 ArgValue = DAG.getNode(X86ISD::MOVDQ2Q, dl, VA.getValVT(), ArgValue);
2681 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
2684 assert(VA.isMemLoc());
2685 ArgValue = LowerMemArgument(Chain, CallConv, Ins, dl, DAG, VA, MFI, i);
2688 // If value is passed via pointer - do a load.
2689 if (VA.getLocInfo() == CCValAssign::Indirect)
2690 ArgValue = DAG.getLoad(VA.getValVT(), dl, Chain, ArgValue,
2691 MachinePointerInfo(), false, false, false, 0);
2693 InVals.push_back(ArgValue);
2696 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2697 // All x86 ABIs require that for returning structs by value we copy the
2698 // sret argument into %rax/%eax (depending on ABI) for the return. Save
2699 // the argument into a virtual register so that we can access it from the
2701 if (Ins[i].Flags.isSRet()) {
2702 unsigned Reg = FuncInfo->getSRetReturnReg();
2704 MVT PtrTy = getPointerTy(DAG.getDataLayout());
2705 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(PtrTy));
2706 FuncInfo->setSRetReturnReg(Reg);
2708 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, InVals[i]);
2709 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain);
2714 unsigned StackSize = CCInfo.getNextStackOffset();
2715 // Align stack specially for tail calls.
2716 if (shouldGuaranteeTCO(CallConv,
2717 MF.getTarget().Options.GuaranteedTailCallOpt))
2718 StackSize = GetAlignedArgumentStackSize(StackSize, DAG);
2720 // If the function takes variable number of arguments, make a frame index for
2721 // the start of the first vararg value... for expansion of llvm.va_start. We
2722 // can skip this if there are no va_start calls.
2723 if (MFI->hasVAStart() &&
2724 (Is64Bit || (CallConv != CallingConv::X86_FastCall &&
2725 CallConv != CallingConv::X86_ThisCall))) {
2726 FuncInfo->setVarArgsFrameIndex(
2727 MFI->CreateFixedObject(1, StackSize, true));
2730 // Figure out if XMM registers are in use.
2731 assert(!(Subtarget->useSoftFloat() &&
2732 Fn->hasFnAttribute(Attribute::NoImplicitFloat)) &&
2733 "SSE register cannot be used when SSE is disabled!");
2735 // 64-bit calling conventions support varargs and register parameters, so we
2736 // have to do extra work to spill them in the prologue.
2737 if (Is64Bit && isVarArg && MFI->hasVAStart()) {
2738 // Find the first unallocated argument registers.
2739 ArrayRef<MCPhysReg> ArgGPRs = get64BitArgumentGPRs(CallConv, Subtarget);
2740 ArrayRef<MCPhysReg> ArgXMMs = get64BitArgumentXMMs(MF, CallConv, Subtarget);
2741 unsigned NumIntRegs = CCInfo.getFirstUnallocated(ArgGPRs);
2742 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(ArgXMMs);
2743 assert(!(NumXMMRegs && !Subtarget->hasSSE1()) &&
2744 "SSE register cannot be used when SSE is disabled!");
2746 // Gather all the live in physical registers.
2747 SmallVector<SDValue, 6> LiveGPRs;
2748 SmallVector<SDValue, 8> LiveXMMRegs;
2750 for (MCPhysReg Reg : ArgGPRs.slice(NumIntRegs)) {
2751 unsigned GPR = MF.addLiveIn(Reg, &X86::GR64RegClass);
2753 DAG.getCopyFromReg(Chain, dl, GPR, MVT::i64));
2755 if (!ArgXMMs.empty()) {
2756 unsigned AL = MF.addLiveIn(X86::AL, &X86::GR8RegClass);
2757 ALVal = DAG.getCopyFromReg(Chain, dl, AL, MVT::i8);
2758 for (MCPhysReg Reg : ArgXMMs.slice(NumXMMRegs)) {
2759 unsigned XMMReg = MF.addLiveIn(Reg, &X86::VR128RegClass);
2760 LiveXMMRegs.push_back(
2761 DAG.getCopyFromReg(Chain, dl, XMMReg, MVT::v4f32));
2766 // Get to the caller-allocated home save location. Add 8 to account
2767 // for the return address.
2768 int HomeOffset = TFI.getOffsetOfLocalArea() + 8;
2769 FuncInfo->setRegSaveFrameIndex(
2770 MFI->CreateFixedObject(1, NumIntRegs * 8 + HomeOffset, false));
2771 // Fixup to set vararg frame on shadow area (4 x i64).
2773 FuncInfo->setVarArgsFrameIndex(FuncInfo->getRegSaveFrameIndex());
2775 // For X86-64, if there are vararg parameters that are passed via
2776 // registers, then we must store them to their spots on the stack so
2777 // they may be loaded by deferencing the result of va_next.
2778 FuncInfo->setVarArgsGPOffset(NumIntRegs * 8);
2779 FuncInfo->setVarArgsFPOffset(ArgGPRs.size() * 8 + NumXMMRegs * 16);
2780 FuncInfo->setRegSaveFrameIndex(MFI->CreateStackObject(
2781 ArgGPRs.size() * 8 + ArgXMMs.size() * 16, 16, false));
2784 // Store the integer parameter registers.
2785 SmallVector<SDValue, 8> MemOps;
2786 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
2787 getPointerTy(DAG.getDataLayout()));
2788 unsigned Offset = FuncInfo->getVarArgsGPOffset();
2789 for (SDValue Val : LiveGPRs) {
2790 SDValue FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(DAG.getDataLayout()),
2791 RSFIN, DAG.getIntPtrConstant(Offset, dl));
2793 DAG.getStore(Val.getValue(1), dl, Val, FIN,
2794 MachinePointerInfo::getFixedStack(
2795 DAG.getMachineFunction(),
2796 FuncInfo->getRegSaveFrameIndex(), Offset),
2798 MemOps.push_back(Store);
2802 if (!ArgXMMs.empty() && NumXMMRegs != ArgXMMs.size()) {
2803 // Now store the XMM (fp + vector) parameter registers.
2804 SmallVector<SDValue, 12> SaveXMMOps;
2805 SaveXMMOps.push_back(Chain);
2806 SaveXMMOps.push_back(ALVal);
2807 SaveXMMOps.push_back(DAG.getIntPtrConstant(
2808 FuncInfo->getRegSaveFrameIndex(), dl));
2809 SaveXMMOps.push_back(DAG.getIntPtrConstant(
2810 FuncInfo->getVarArgsFPOffset(), dl));
2811 SaveXMMOps.insert(SaveXMMOps.end(), LiveXMMRegs.begin(),
2813 MemOps.push_back(DAG.getNode(X86ISD::VASTART_SAVE_XMM_REGS, dl,
2814 MVT::Other, SaveXMMOps));
2817 if (!MemOps.empty())
2818 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps);
2821 if (isVarArg && MFI->hasMustTailInVarArgFunc()) {
2822 // Find the largest legal vector type.
2823 MVT VecVT = MVT::Other;
2824 // FIXME: Only some x86_32 calling conventions support AVX512.
2825 if (Subtarget->hasAVX512() &&
2826 (Is64Bit || (CallConv == CallingConv::X86_VectorCall ||
2827 CallConv == CallingConv::Intel_OCL_BI)))
2828 VecVT = MVT::v16f32;
2829 else if (Subtarget->hasAVX())
2831 else if (Subtarget->hasSSE2())
2834 // We forward some GPRs and some vector types.
2835 SmallVector<MVT, 2> RegParmTypes;
2836 MVT IntVT = Is64Bit ? MVT::i64 : MVT::i32;
2837 RegParmTypes.push_back(IntVT);
2838 if (VecVT != MVT::Other)
2839 RegParmTypes.push_back(VecVT);
2841 // Compute the set of forwarded registers. The rest are scratch.
2842 SmallVectorImpl<ForwardedRegister> &Forwards =
2843 FuncInfo->getForwardedMustTailRegParms();
2844 CCInfo.analyzeMustTailForwardedRegisters(Forwards, RegParmTypes, CC_X86);
2846 // Conservatively forward AL on x86_64, since it might be used for varargs.
2847 if (Is64Bit && !CCInfo.isAllocated(X86::AL)) {
2848 unsigned ALVReg = MF.addLiveIn(X86::AL, &X86::GR8RegClass);
2849 Forwards.push_back(ForwardedRegister(ALVReg, X86::AL, MVT::i8));
2852 // Copy all forwards from physical to virtual registers.
2853 for (ForwardedRegister &F : Forwards) {
2854 // FIXME: Can we use a less constrained schedule?
2855 SDValue RegVal = DAG.getCopyFromReg(Chain, dl, F.VReg, F.VT);
2856 F.VReg = MF.getRegInfo().createVirtualRegister(getRegClassFor(F.VT));
2857 Chain = DAG.getCopyToReg(Chain, dl, F.VReg, RegVal);
2861 // Some CCs need callee pop.
2862 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg,
2863 MF.getTarget().Options.GuaranteedTailCallOpt)) {
2864 FuncInfo->setBytesToPopOnReturn(StackSize); // Callee pops everything.
2866 FuncInfo->setBytesToPopOnReturn(0); // Callee pops nothing.
2867 // If this is an sret function, the return should pop the hidden pointer.
2868 if (!Is64Bit && !canGuaranteeTCO(CallConv) &&
2869 !Subtarget->getTargetTriple().isOSMSVCRT() &&
2870 argsAreStructReturn(Ins) == StackStructReturn)
2871 FuncInfo->setBytesToPopOnReturn(4);
2875 // RegSaveFrameIndex is X86-64 only.
2876 FuncInfo->setRegSaveFrameIndex(0xAAAAAAA);
2877 if (CallConv == CallingConv::X86_FastCall ||
2878 CallConv == CallingConv::X86_ThisCall)
2879 // fastcc functions can't have varargs.
2880 FuncInfo->setVarArgsFrameIndex(0xAAAAAAA);
2883 FuncInfo->setArgumentStackSize(StackSize);
2885 if (WinEHFuncInfo *EHInfo = MF.getWinEHFuncInfo()) {
2886 EHPersonality Personality = classifyEHPersonality(Fn->getPersonalityFn());
2887 if (Personality == EHPersonality::CoreCLR) {
2889 // TODO: Add a mechanism to frame lowering that will allow us to indicate
2890 // that we'd prefer this slot be allocated towards the bottom of the frame
2891 // (i.e. near the stack pointer after allocating the frame). Every
2892 // funclet needs a copy of this slot in its (mostly empty) frame, and the
2893 // offset from the bottom of this and each funclet's frame must be the
2894 // same, so the size of funclets' (mostly empty) frames is dictated by
2895 // how far this slot is from the bottom (since they allocate just enough
2896 // space to accomodate holding this slot at the correct offset).
2897 int PSPSymFI = MFI->CreateStackObject(8, 8, /*isSS=*/false);
2898 EHInfo->PSPSymFrameIdx = PSPSymFI;
2906 X86TargetLowering::LowerMemOpCallTo(SDValue Chain,
2907 SDValue StackPtr, SDValue Arg,
2908 SDLoc dl, SelectionDAG &DAG,
2909 const CCValAssign &VA,
2910 ISD::ArgFlagsTy Flags) const {
2911 unsigned LocMemOffset = VA.getLocMemOffset();
2912 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset, dl);
2913 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(DAG.getDataLayout()),
2915 if (Flags.isByVal())
2916 return CreateCopyOfByValArgument(Arg, PtrOff, Chain, Flags, DAG, dl);
2918 return DAG.getStore(
2919 Chain, dl, Arg, PtrOff,
2920 MachinePointerInfo::getStack(DAG.getMachineFunction(), LocMemOffset),
2924 /// Emit a load of return address if tail call
2925 /// optimization is performed and it is required.
2927 X86TargetLowering::EmitTailCallLoadRetAddr(SelectionDAG &DAG,
2928 SDValue &OutRetAddr, SDValue Chain,
2929 bool IsTailCall, bool Is64Bit,
2930 int FPDiff, SDLoc dl) const {
2931 // Adjust the Return address stack slot.
2932 EVT VT = getPointerTy(DAG.getDataLayout());
2933 OutRetAddr = getReturnAddressFrameIndex(DAG);
2935 // Load the "old" Return address.
2936 OutRetAddr = DAG.getLoad(VT, dl, Chain, OutRetAddr, MachinePointerInfo(),
2937 false, false, false, 0);
2938 return SDValue(OutRetAddr.getNode(), 1);
2941 /// Emit a store of the return address if tail call
2942 /// optimization is performed and it is required (FPDiff!=0).
2943 static SDValue EmitTailCallStoreRetAddr(SelectionDAG &DAG, MachineFunction &MF,
2944 SDValue Chain, SDValue RetAddrFrIdx,
2945 EVT PtrVT, unsigned SlotSize,
2946 int FPDiff, SDLoc dl) {
2947 // Store the return address to the appropriate stack slot.
2948 if (!FPDiff) return Chain;
2949 // Calculate the new stack slot for the return address.
2950 int NewReturnAddrFI =
2951 MF.getFrameInfo()->CreateFixedObject(SlotSize, (int64_t)FPDiff - SlotSize,
2953 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewReturnAddrFI, PtrVT);
2954 Chain = DAG.getStore(Chain, dl, RetAddrFrIdx, NewRetAddrFrIdx,
2955 MachinePointerInfo::getFixedStack(
2956 DAG.getMachineFunction(), NewReturnAddrFI),
2961 /// Returns a vector_shuffle mask for an movs{s|d}, movd
2962 /// operation of specified width.
2963 static SDValue getMOVL(SelectionDAG &DAG, SDLoc dl, MVT VT, SDValue V1,
2965 unsigned NumElems = VT.getVectorNumElements();
2966 SmallVector<int, 8> Mask;
2967 Mask.push_back(NumElems);
2968 for (unsigned i = 1; i != NumElems; ++i)
2970 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
2974 X86TargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
2975 SmallVectorImpl<SDValue> &InVals) const {
2976 SelectionDAG &DAG = CLI.DAG;
2978 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
2979 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
2980 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
2981 SDValue Chain = CLI.Chain;
2982 SDValue Callee = CLI.Callee;
2983 CallingConv::ID CallConv = CLI.CallConv;
2984 bool &isTailCall = CLI.IsTailCall;
2985 bool isVarArg = CLI.IsVarArg;
2987 MachineFunction &MF = DAG.getMachineFunction();
2988 bool Is64Bit = Subtarget->is64Bit();
2989 bool IsWin64 = Subtarget->isCallingConvWin64(CallConv);
2990 StructReturnType SR = callIsStructReturn(Outs);
2991 bool IsSibcall = false;
2992 X86MachineFunctionInfo *X86Info = MF.getInfo<X86MachineFunctionInfo>();
2993 auto Attr = MF.getFunction()->getFnAttribute("disable-tail-calls");
2995 if (Attr.getValueAsString() == "true")
2998 if (Subtarget->isPICStyleGOT() &&
2999 !MF.getTarget().Options.GuaranteedTailCallOpt) {
3000 // If we are using a GOT, disable tail calls to external symbols with
3001 // default visibility. Tail calling such a symbol requires using a GOT
3002 // relocation, which forces early binding of the symbol. This breaks code
3003 // that require lazy function symbol resolution. Using musttail or
3004 // GuaranteedTailCallOpt will override this.
3005 GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee);
3006 if (!G || (!G->getGlobal()->hasLocalLinkage() &&
3007 G->getGlobal()->hasDefaultVisibility()))
3011 bool IsMustTail = CLI.CS && CLI.CS->isMustTailCall();
3013 // Force this to be a tail call. The verifier rules are enough to ensure
3014 // that we can lower this successfully without moving the return address
3017 } else if (isTailCall) {
3018 // Check if it's really possible to do a tail call.
3019 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv,
3020 isVarArg, SR != NotStructReturn,
3021 MF.getFunction()->hasStructRetAttr(), CLI.RetTy,
3022 Outs, OutVals, Ins, DAG);
3024 // Sibcalls are automatically detected tailcalls which do not require
3026 if (!MF.getTarget().Options.GuaranteedTailCallOpt && isTailCall)
3033 assert(!(isVarArg && canGuaranteeTCO(CallConv)) &&
3034 "Var args not supported with calling convention fastcc, ghc or hipe");
3036 // Analyze operands of the call, assigning locations to each operand.
3037 SmallVector<CCValAssign, 16> ArgLocs;
3038 CCState CCInfo(CallConv, isVarArg, MF, ArgLocs, *DAG.getContext());
3040 // Allocate shadow area for Win64
3042 CCInfo.AllocateStack(32, 8);
3044 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
3046 // Get a count of how many bytes are to be pushed on the stack.
3047 unsigned NumBytes = CCInfo.getAlignedCallFrameSize();
3049 // This is a sibcall. The memory operands are available in caller's
3050 // own caller's stack.
3052 else if (MF.getTarget().Options.GuaranteedTailCallOpt &&
3053 canGuaranteeTCO(CallConv))
3054 NumBytes = GetAlignedArgumentStackSize(NumBytes, DAG);
3057 if (isTailCall && !IsSibcall && !IsMustTail) {
3058 // Lower arguments at fp - stackoffset + fpdiff.
3059 unsigned NumBytesCallerPushed = X86Info->getBytesToPopOnReturn();
3061 FPDiff = NumBytesCallerPushed - NumBytes;
3063 // Set the delta of movement of the returnaddr stackslot.
3064 // But only set if delta is greater than previous delta.
3065 if (FPDiff < X86Info->getTCReturnAddrDelta())
3066 X86Info->setTCReturnAddrDelta(FPDiff);
3069 unsigned NumBytesToPush = NumBytes;
3070 unsigned NumBytesToPop = NumBytes;
3072 // If we have an inalloca argument, all stack space has already been allocated
3073 // for us and be right at the top of the stack. We don't support multiple
3074 // arguments passed in memory when using inalloca.
3075 if (!Outs.empty() && Outs.back().Flags.isInAlloca()) {
3077 if (!ArgLocs.back().isMemLoc())
3078 report_fatal_error("cannot use inalloca attribute on a register "
3080 if (ArgLocs.back().getLocMemOffset() != 0)
3081 report_fatal_error("any parameter with the inalloca attribute must be "
3082 "the only memory argument");
3086 Chain = DAG.getCALLSEQ_START(
3087 Chain, DAG.getIntPtrConstant(NumBytesToPush, dl, true), dl);
3089 SDValue RetAddrFrIdx;
3090 // Load return address for tail calls.
3091 if (isTailCall && FPDiff)
3092 Chain = EmitTailCallLoadRetAddr(DAG, RetAddrFrIdx, Chain, isTailCall,
3093 Is64Bit, FPDiff, dl);
3095 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
3096 SmallVector<SDValue, 8> MemOpChains;
3099 // Walk the register/memloc assignments, inserting copies/loads. In the case
3100 // of tail call optimization arguments are handle later.
3101 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
3102 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3103 // Skip inalloca arguments, they have already been written.
3104 ISD::ArgFlagsTy Flags = Outs[i].Flags;
3105 if (Flags.isInAlloca())
3108 CCValAssign &VA = ArgLocs[i];
3109 EVT RegVT = VA.getLocVT();
3110 SDValue Arg = OutVals[i];
3111 bool isByVal = Flags.isByVal();
3113 // Promote the value if needed.
3114 switch (VA.getLocInfo()) {
3115 default: llvm_unreachable("Unknown loc info!");
3116 case CCValAssign::Full: break;
3117 case CCValAssign::SExt:
3118 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, RegVT, Arg);
3120 case CCValAssign::ZExt:
3121 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, RegVT, Arg);
3123 case CCValAssign::AExt:
3124 if (Arg.getValueType().isVector() &&
3125 Arg.getValueType().getVectorElementType() == MVT::i1)
3126 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, RegVT, Arg);
3127 else if (RegVT.is128BitVector()) {
3128 // Special case: passing MMX values in XMM registers.
3129 Arg = DAG.getBitcast(MVT::i64, Arg);
3130 Arg = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, Arg);
3131 Arg = getMOVL(DAG, dl, MVT::v2i64, DAG.getUNDEF(MVT::v2i64), Arg);
3133 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, RegVT, Arg);
3135 case CCValAssign::BCvt:
3136 Arg = DAG.getBitcast(RegVT, Arg);
3138 case CCValAssign::Indirect: {
3139 // Store the argument.
3140 SDValue SpillSlot = DAG.CreateStackTemporary(VA.getValVT());
3141 int FI = cast<FrameIndexSDNode>(SpillSlot)->getIndex();
3142 Chain = DAG.getStore(
3143 Chain, dl, Arg, SpillSlot,
3144 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FI),
3151 if (VA.isRegLoc()) {
3152 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
3153 if (isVarArg && IsWin64) {
3154 // Win64 ABI requires argument XMM reg to be copied to the corresponding
3155 // shadow reg if callee is a varargs function.
3156 unsigned ShadowReg = 0;
3157 switch (VA.getLocReg()) {
3158 case X86::XMM0: ShadowReg = X86::RCX; break;
3159 case X86::XMM1: ShadowReg = X86::RDX; break;
3160 case X86::XMM2: ShadowReg = X86::R8; break;
3161 case X86::XMM3: ShadowReg = X86::R9; break;
3164 RegsToPass.push_back(std::make_pair(ShadowReg, Arg));
3166 } else if (!IsSibcall && (!isTailCall || isByVal)) {
3167 assert(VA.isMemLoc());
3168 if (!StackPtr.getNode())
3169 StackPtr = DAG.getCopyFromReg(Chain, dl, RegInfo->getStackRegister(),
3170 getPointerTy(DAG.getDataLayout()));
3171 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Arg,
3172 dl, DAG, VA, Flags));
3176 if (!MemOpChains.empty())
3177 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains);
3179 if (Subtarget->isPICStyleGOT()) {
3180 // ELF / PIC requires GOT in the EBX register before function calls via PLT
3183 RegsToPass.push_back(std::make_pair(
3184 unsigned(X86::EBX), DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(),
3185 getPointerTy(DAG.getDataLayout()))));
3187 // If we are tail calling and generating PIC/GOT style code load the
3188 // address of the callee into ECX. The value in ecx is used as target of
3189 // the tail jump. This is done to circumvent the ebx/callee-saved problem
3190 // for tail calls on PIC/GOT architectures. Normally we would just put the
3191 // address of GOT into ebx and then call target@PLT. But for tail calls
3192 // ebx would be restored (since ebx is callee saved) before jumping to the
3195 // Note: The actual moving to ECX is done further down.
3196 GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee);
3197 if (G && !G->getGlobal()->hasLocalLinkage() &&
3198 G->getGlobal()->hasDefaultVisibility())
3199 Callee = LowerGlobalAddress(Callee, DAG);
3200 else if (isa<ExternalSymbolSDNode>(Callee))
3201 Callee = LowerExternalSymbol(Callee, DAG);
3205 if (Is64Bit && isVarArg && !IsWin64 && !IsMustTail) {
3206 // From AMD64 ABI document:
3207 // For calls that may call functions that use varargs or stdargs
3208 // (prototype-less calls or calls to functions containing ellipsis (...) in
3209 // the declaration) %al is used as hidden argument to specify the number
3210 // of SSE registers used. The contents of %al do not need to match exactly
3211 // the number of registers, but must be an ubound on the number of SSE
3212 // registers used and is in the range 0 - 8 inclusive.
3214 // Count the number of XMM registers allocated.
3215 static const MCPhysReg XMMArgRegs[] = {
3216 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
3217 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
3219 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs);
3220 assert((Subtarget->hasSSE1() || !NumXMMRegs)
3221 && "SSE registers cannot be used when SSE is disabled");
3223 RegsToPass.push_back(std::make_pair(unsigned(X86::AL),
3224 DAG.getConstant(NumXMMRegs, dl,
3228 if (isVarArg && IsMustTail) {
3229 const auto &Forwards = X86Info->getForwardedMustTailRegParms();
3230 for (const auto &F : Forwards) {
3231 SDValue Val = DAG.getCopyFromReg(Chain, dl, F.VReg, F.VT);
3232 RegsToPass.push_back(std::make_pair(unsigned(F.PReg), Val));
3236 // For tail calls lower the arguments to the 'real' stack slots. Sibcalls
3237 // don't need this because the eligibility check rejects calls that require
3238 // shuffling arguments passed in memory.
3239 if (!IsSibcall && isTailCall) {
3240 // Force all the incoming stack arguments to be loaded from the stack
3241 // before any new outgoing arguments are stored to the stack, because the
3242 // outgoing stack slots may alias the incoming argument stack slots, and
3243 // the alias isn't otherwise explicit. This is slightly more conservative
3244 // than necessary, because it means that each store effectively depends
3245 // on every argument instead of just those arguments it would clobber.
3246 SDValue ArgChain = DAG.getStackArgumentTokenFactor(Chain);
3248 SmallVector<SDValue, 8> MemOpChains2;
3251 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3252 CCValAssign &VA = ArgLocs[i];
3255 assert(VA.isMemLoc());
3256 SDValue Arg = OutVals[i];
3257 ISD::ArgFlagsTy Flags = Outs[i].Flags;
3258 // Skip inalloca arguments. They don't require any work.
3259 if (Flags.isInAlloca())
3261 // Create frame index.
3262 int32_t Offset = VA.getLocMemOffset()+FPDiff;
3263 uint32_t OpSize = (VA.getLocVT().getSizeInBits()+7)/8;
3264 FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true);
3265 FIN = DAG.getFrameIndex(FI, getPointerTy(DAG.getDataLayout()));
3267 if (Flags.isByVal()) {
3268 // Copy relative to framepointer.
3269 SDValue Source = DAG.getIntPtrConstant(VA.getLocMemOffset(), dl);
3270 if (!StackPtr.getNode())
3271 StackPtr = DAG.getCopyFromReg(Chain, dl, RegInfo->getStackRegister(),
3272 getPointerTy(DAG.getDataLayout()));
3273 Source = DAG.getNode(ISD::ADD, dl, getPointerTy(DAG.getDataLayout()),
3276 MemOpChains2.push_back(CreateCopyOfByValArgument(Source, FIN,
3280 // Store relative to framepointer.
3281 MemOpChains2.push_back(DAG.getStore(
3282 ArgChain, dl, Arg, FIN,
3283 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FI),
3288 if (!MemOpChains2.empty())
3289 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains2);
3291 // Store the return address to the appropriate stack slot.
3292 Chain = EmitTailCallStoreRetAddr(DAG, MF, Chain, RetAddrFrIdx,
3293 getPointerTy(DAG.getDataLayout()),
3294 RegInfo->getSlotSize(), FPDiff, dl);
3297 // Build a sequence of copy-to-reg nodes chained together with token chain
3298 // and flag operands which copy the outgoing args into registers.
3300 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
3301 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
3302 RegsToPass[i].second, InFlag);
3303 InFlag = Chain.getValue(1);
3306 if (DAG.getTarget().getCodeModel() == CodeModel::Large) {
3307 assert(Is64Bit && "Large code model is only legal in 64-bit mode.");
3308 // In the 64-bit large code model, we have to make all calls
3309 // through a register, since the call instruction's 32-bit
3310 // pc-relative offset may not be large enough to hold the whole
3312 } else if (Callee->getOpcode() == ISD::GlobalAddress) {
3313 // If the callee is a GlobalAddress node (quite common, every direct call
3314 // is) turn it into a TargetGlobalAddress node so that legalize doesn't hack
3316 GlobalAddressSDNode* G = cast<GlobalAddressSDNode>(Callee);
3318 // We should use extra load for direct calls to dllimported functions in
3320 const GlobalValue *GV = G->getGlobal();
3321 if (!GV->hasDLLImportStorageClass()) {
3322 unsigned char OpFlags = 0;
3323 bool ExtraLoad = false;
3324 unsigned WrapperKind = ISD::DELETED_NODE;
3326 // On ELF targets, in both X86-64 and X86-32 mode, direct calls to
3327 // external symbols most go through the PLT in PIC mode. If the symbol
3328 // has hidden or protected visibility, or if it is static or local, then
3329 // we don't need to use the PLT - we can directly call it.
3330 if (Subtarget->isTargetELF() &&
3331 DAG.getTarget().getRelocationModel() == Reloc::PIC_ &&
3332 GV->hasDefaultVisibility() && !GV->hasLocalLinkage()) {
3333 OpFlags = X86II::MO_PLT;
3334 } else if (Subtarget->isPICStyleStubAny() &&
3335 !GV->isStrongDefinitionForLinker() &&
3336 (!Subtarget->getTargetTriple().isMacOSX() ||
3337 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
3338 // PC-relative references to external symbols should go through $stub,
3339 // unless we're building with the leopard linker or later, which
3340 // automatically synthesizes these stubs.
3341 OpFlags = X86II::MO_DARWIN_STUB;
3342 } else if (Subtarget->isPICStyleRIPRel() && isa<Function>(GV) &&
3343 cast<Function>(GV)->hasFnAttribute(Attribute::NonLazyBind)) {
3344 // If the function is marked as non-lazy, generate an indirect call
3345 // which loads from the GOT directly. This avoids runtime overhead
3346 // at the cost of eager binding (and one extra byte of encoding).
3347 OpFlags = X86II::MO_GOTPCREL;
3348 WrapperKind = X86ISD::WrapperRIP;
3352 Callee = DAG.getTargetGlobalAddress(
3353 GV, dl, getPointerTy(DAG.getDataLayout()), G->getOffset(), OpFlags);
3355 // Add a wrapper if needed.
3356 if (WrapperKind != ISD::DELETED_NODE)
3357 Callee = DAG.getNode(X86ISD::WrapperRIP, dl,
3358 getPointerTy(DAG.getDataLayout()), Callee);
3359 // Add extra indirection if needed.
3361 Callee = DAG.getLoad(
3362 getPointerTy(DAG.getDataLayout()), dl, DAG.getEntryNode(), Callee,
3363 MachinePointerInfo::getGOT(DAG.getMachineFunction()), false, false,
3366 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
3367 unsigned char OpFlags = 0;
3369 // On ELF targets, in either X86-64 or X86-32 mode, direct calls to
3370 // external symbols should go through the PLT.
3371 if (Subtarget->isTargetELF() &&
3372 DAG.getTarget().getRelocationModel() == Reloc::PIC_) {
3373 OpFlags = X86II::MO_PLT;
3374 } else if (Subtarget->isPICStyleStubAny() &&
3375 (!Subtarget->getTargetTriple().isMacOSX() ||
3376 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
3377 // PC-relative references to external symbols should go through $stub,
3378 // unless we're building with the leopard linker or later, which
3379 // automatically synthesizes these stubs.
3380 OpFlags = X86II::MO_DARWIN_STUB;
3383 Callee = DAG.getTargetExternalSymbol(
3384 S->getSymbol(), getPointerTy(DAG.getDataLayout()), OpFlags);
3385 } else if (Subtarget->isTarget64BitILP32() &&
3386 Callee->getValueType(0) == MVT::i32) {
3387 // Zero-extend the 32-bit Callee address into a 64-bit according to x32 ABI
3388 Callee = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i64, Callee);
3391 // Returns a chain & a flag for retval copy to use.
3392 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
3393 SmallVector<SDValue, 8> Ops;
3395 if (!IsSibcall && isTailCall) {
3396 Chain = DAG.getCALLSEQ_END(Chain,
3397 DAG.getIntPtrConstant(NumBytesToPop, dl, true),
3398 DAG.getIntPtrConstant(0, dl, true), InFlag, dl);
3399 InFlag = Chain.getValue(1);
3402 Ops.push_back(Chain);
3403 Ops.push_back(Callee);
3406 Ops.push_back(DAG.getConstant(FPDiff, dl, MVT::i32));
3408 // Add argument registers to the end of the list so that they are known live
3410 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
3411 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
3412 RegsToPass[i].second.getValueType()));
3414 // Add a register mask operand representing the call-preserved registers.
3415 const uint32_t *Mask = RegInfo->getCallPreservedMask(MF, CallConv);
3416 assert(Mask && "Missing call preserved mask for calling convention");
3418 // If this is an invoke in a 32-bit function using a funclet-based
3419 // personality, assume the function clobbers all registers. If an exception
3420 // is thrown, the runtime will not restore CSRs.
3421 // FIXME: Model this more precisely so that we can register allocate across
3422 // the normal edge and spill and fill across the exceptional edge.
3423 if (!Is64Bit && CLI.CS && CLI.CS->isInvoke()) {
3424 const Function *CallerFn = MF.getFunction();
3425 EHPersonality Pers =
3426 CallerFn->hasPersonalityFn()
3427 ? classifyEHPersonality(CallerFn->getPersonalityFn())
3428 : EHPersonality::Unknown;
3429 if (isFuncletEHPersonality(Pers))
3430 Mask = RegInfo->getNoPreservedMask();
3433 Ops.push_back(DAG.getRegisterMask(Mask));
3435 if (InFlag.getNode())
3436 Ops.push_back(InFlag);
3440 //// If this is the first return lowered for this function, add the regs
3441 //// to the liveout set for the function.
3442 // This isn't right, although it's probably harmless on x86; liveouts
3443 // should be computed from returns not tail calls. Consider a void
3444 // function making a tail call to a function returning int.
3445 MF.getFrameInfo()->setHasTailCall();
3446 return DAG.getNode(X86ISD::TC_RETURN, dl, NodeTys, Ops);
3449 Chain = DAG.getNode(X86ISD::CALL, dl, NodeTys, Ops);
3450 InFlag = Chain.getValue(1);
3452 // Create the CALLSEQ_END node.
3453 unsigned NumBytesForCalleeToPop;
3454 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg,
3455 DAG.getTarget().Options.GuaranteedTailCallOpt))
3456 NumBytesForCalleeToPop = NumBytes; // Callee pops everything
3457 else if (!Is64Bit && !canGuaranteeTCO(CallConv) &&
3458 !Subtarget->getTargetTriple().isOSMSVCRT() &&
3459 SR == StackStructReturn)
3460 // If this is a call to a struct-return function, the callee
3461 // pops the hidden struct pointer, so we have to push it back.
3462 // This is common for Darwin/X86, Linux & Mingw32 targets.
3463 // For MSVC Win32 targets, the caller pops the hidden struct pointer.
3464 NumBytesForCalleeToPop = 4;
3466 NumBytesForCalleeToPop = 0; // Callee pops nothing.
3468 // Returns a flag for retval copy to use.
3470 Chain = DAG.getCALLSEQ_END(Chain,
3471 DAG.getIntPtrConstant(NumBytesToPop, dl, true),
3472 DAG.getIntPtrConstant(NumBytesForCalleeToPop, dl,
3475 InFlag = Chain.getValue(1);
3478 // Handle result values, copying them out of physregs into vregs that we
3480 return LowerCallResult(Chain, InFlag, CallConv, isVarArg,
3481 Ins, dl, DAG, InVals);
3484 //===----------------------------------------------------------------------===//
3485 // Fast Calling Convention (tail call) implementation
3486 //===----------------------------------------------------------------------===//
3488 // Like std call, callee cleans arguments, convention except that ECX is
3489 // reserved for storing the tail called function address. Only 2 registers are
3490 // free for argument passing (inreg). Tail call optimization is performed
3492 // * tailcallopt is enabled
3493 // * caller/callee are fastcc
3494 // On X86_64 architecture with GOT-style position independent code only local
3495 // (within module) calls are supported at the moment.
3496 // To keep the stack aligned according to platform abi the function
3497 // GetAlignedArgumentStackSize ensures that argument delta is always multiples
3498 // of stack alignment. (Dynamic linkers need this - darwin's dyld for example)
3499 // If a tail called function callee has more arguments than the caller the
3500 // caller needs to make sure that there is room to move the RETADDR to. This is
3501 // achieved by reserving an area the size of the argument delta right after the
3502 // original RETADDR, but before the saved framepointer or the spilled registers
3503 // e.g. caller(arg1, arg2) calls callee(arg1, arg2,arg3,arg4)
3515 /// Make the stack size align e.g 16n + 12 aligned for a 16-byte align
3518 X86TargetLowering::GetAlignedArgumentStackSize(unsigned StackSize,
3519 SelectionDAG& DAG) const {
3520 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
3521 const TargetFrameLowering &TFI = *Subtarget->getFrameLowering();
3522 unsigned StackAlignment = TFI.getStackAlignment();
3523 uint64_t AlignMask = StackAlignment - 1;
3524 int64_t Offset = StackSize;
3525 unsigned SlotSize = RegInfo->getSlotSize();
3526 if ( (Offset & AlignMask) <= (StackAlignment - SlotSize) ) {
3527 // Number smaller than 12 so just add the difference.
3528 Offset += ((StackAlignment - SlotSize) - (Offset & AlignMask));
3530 // Mask out lower bits, add stackalignment once plus the 12 bytes.
3531 Offset = ((~AlignMask) & Offset) + StackAlignment +
3532 (StackAlignment-SlotSize);
3537 /// Return true if the given stack call argument is already available in the
3538 /// same position (relatively) of the caller's incoming argument stack.
3540 bool MatchingStackOffset(SDValue Arg, unsigned Offset, ISD::ArgFlagsTy Flags,
3541 MachineFrameInfo *MFI, const MachineRegisterInfo *MRI,
3542 const X86InstrInfo *TII) {
3543 unsigned Bytes = Arg.getValueType().getSizeInBits() / 8;
3545 if (Arg.getOpcode() == ISD::CopyFromReg) {
3546 unsigned VR = cast<RegisterSDNode>(Arg.getOperand(1))->getReg();
3547 if (!TargetRegisterInfo::isVirtualRegister(VR))
3549 MachineInstr *Def = MRI->getVRegDef(VR);
3552 if (!Flags.isByVal()) {
3553 if (!TII->isLoadFromStackSlot(Def, FI))
3556 unsigned Opcode = Def->getOpcode();
3557 if ((Opcode == X86::LEA32r || Opcode == X86::LEA64r ||
3558 Opcode == X86::LEA64_32r) &&
3559 Def->getOperand(1).isFI()) {
3560 FI = Def->getOperand(1).getIndex();
3561 Bytes = Flags.getByValSize();
3565 } else if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Arg)) {
3566 if (Flags.isByVal())
3567 // ByVal argument is passed in as a pointer but it's now being
3568 // dereferenced. e.g.
3569 // define @foo(%struct.X* %A) {
3570 // tail call @bar(%struct.X* byval %A)
3573 SDValue Ptr = Ld->getBasePtr();
3574 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr);
3577 FI = FINode->getIndex();
3578 } else if (Arg.getOpcode() == ISD::FrameIndex && Flags.isByVal()) {
3579 FrameIndexSDNode *FINode = cast<FrameIndexSDNode>(Arg);
3580 FI = FINode->getIndex();
3581 Bytes = Flags.getByValSize();
3585 assert(FI != INT_MAX);
3586 if (!MFI->isFixedObjectIndex(FI))
3588 return Offset == MFI->getObjectOffset(FI) && Bytes == MFI->getObjectSize(FI);
3591 /// Check whether the call is eligible for tail call optimization. Targets
3592 /// that want to do tail call optimization should implement this function.
3593 bool X86TargetLowering::IsEligibleForTailCallOptimization(
3594 SDValue Callee, CallingConv::ID CalleeCC, bool isVarArg,
3595 bool isCalleeStructRet, bool isCallerStructRet, Type *RetTy,
3596 const SmallVectorImpl<ISD::OutputArg> &Outs,
3597 const SmallVectorImpl<SDValue> &OutVals,
3598 const SmallVectorImpl<ISD::InputArg> &Ins, SelectionDAG &DAG) const {
3599 if (!mayTailCallThisCC(CalleeCC))
3602 // If -tailcallopt is specified, make fastcc functions tail-callable.
3603 MachineFunction &MF = DAG.getMachineFunction();
3604 const Function *CallerF = MF.getFunction();
3606 // If the function return type is x86_fp80 and the callee return type is not,
3607 // then the FP_EXTEND of the call result is not a nop. It's not safe to
3608 // perform a tailcall optimization here.
3609 if (CallerF->getReturnType()->isX86_FP80Ty() && !RetTy->isX86_FP80Ty())
3612 CallingConv::ID CallerCC = CallerF->getCallingConv();
3613 bool CCMatch = CallerCC == CalleeCC;
3614 bool IsCalleeWin64 = Subtarget->isCallingConvWin64(CalleeCC);
3615 bool IsCallerWin64 = Subtarget->isCallingConvWin64(CallerCC);
3617 // Win64 functions have extra shadow space for argument homing. Don't do the
3618 // sibcall if the caller and callee have mismatched expectations for this
3620 if (IsCalleeWin64 != IsCallerWin64)
3623 if (DAG.getTarget().Options.GuaranteedTailCallOpt) {
3624 if (canGuaranteeTCO(CalleeCC) && CCMatch)
3629 // Look for obvious safe cases to perform tail call optimization that do not
3630 // require ABI changes. This is what gcc calls sibcall.
3632 // Can't do sibcall if stack needs to be dynamically re-aligned. PEI needs to
3633 // emit a special epilogue.
3634 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
3635 if (RegInfo->needsStackRealignment(MF))
3638 // Also avoid sibcall optimization if either caller or callee uses struct
3639 // return semantics.
3640 if (isCalleeStructRet || isCallerStructRet)
3643 // Do not sibcall optimize vararg calls unless all arguments are passed via
3645 if (isVarArg && !Outs.empty()) {
3646 // Optimizing for varargs on Win64 is unlikely to be safe without
3647 // additional testing.
3648 if (IsCalleeWin64 || IsCallerWin64)
3651 SmallVector<CCValAssign, 16> ArgLocs;
3652 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(), ArgLocs,
3655 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
3656 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i)
3657 if (!ArgLocs[i].isRegLoc())
3661 // If the call result is in ST0 / ST1, it needs to be popped off the x87
3662 // stack. Therefore, if it's not used by the call it is not safe to optimize
3663 // this into a sibcall.
3664 bool Unused = false;
3665 for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
3672 SmallVector<CCValAssign, 16> RVLocs;
3673 CCState CCInfo(CalleeCC, false, DAG.getMachineFunction(), RVLocs,
3675 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
3676 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
3677 CCValAssign &VA = RVLocs[i];
3678 if (VA.getLocReg() == X86::FP0 || VA.getLocReg() == X86::FP1)
3683 // If the calling conventions do not match, then we'd better make sure the
3684 // results are returned in the same way as what the caller expects.
3686 SmallVector<CCValAssign, 16> RVLocs1;
3687 CCState CCInfo1(CalleeCC, false, DAG.getMachineFunction(), RVLocs1,
3689 CCInfo1.AnalyzeCallResult(Ins, RetCC_X86);
3691 SmallVector<CCValAssign, 16> RVLocs2;
3692 CCState CCInfo2(CallerCC, false, DAG.getMachineFunction(), RVLocs2,
3694 CCInfo2.AnalyzeCallResult(Ins, RetCC_X86);
3696 if (RVLocs1.size() != RVLocs2.size())
3698 for (unsigned i = 0, e = RVLocs1.size(); i != e; ++i) {
3699 if (RVLocs1[i].isRegLoc() != RVLocs2[i].isRegLoc())
3701 if (RVLocs1[i].getLocInfo() != RVLocs2[i].getLocInfo())
3703 if (RVLocs1[i].isRegLoc()) {
3704 if (RVLocs1[i].getLocReg() != RVLocs2[i].getLocReg())
3707 if (RVLocs1[i].getLocMemOffset() != RVLocs2[i].getLocMemOffset())
3713 unsigned StackArgsSize = 0;
3715 // If the callee takes no arguments then go on to check the results of the
3717 if (!Outs.empty()) {
3718 // Check if stack adjustment is needed. For now, do not do this if any
3719 // argument is passed on the stack.
3720 SmallVector<CCValAssign, 16> ArgLocs;
3721 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(), ArgLocs,
3724 // Allocate shadow area for Win64
3726 CCInfo.AllocateStack(32, 8);
3728 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
3729 StackArgsSize = CCInfo.getNextStackOffset();
3731 if (CCInfo.getNextStackOffset()) {
3732 // Check if the arguments are already laid out in the right way as
3733 // the caller's fixed stack objects.
3734 MachineFrameInfo *MFI = MF.getFrameInfo();
3735 const MachineRegisterInfo *MRI = &MF.getRegInfo();
3736 const X86InstrInfo *TII = Subtarget->getInstrInfo();
3737 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3738 CCValAssign &VA = ArgLocs[i];
3739 SDValue Arg = OutVals[i];
3740 ISD::ArgFlagsTy Flags = Outs[i].Flags;
3741 if (VA.getLocInfo() == CCValAssign::Indirect)
3743 if (!VA.isRegLoc()) {
3744 if (!MatchingStackOffset(Arg, VA.getLocMemOffset(), Flags,
3751 // If the tailcall address may be in a register, then make sure it's
3752 // possible to register allocate for it. In 32-bit, the call address can
3753 // only target EAX, EDX, or ECX since the tail call must be scheduled after
3754 // callee-saved registers are restored. These happen to be the same
3755 // registers used to pass 'inreg' arguments so watch out for those.
3756 if (!Subtarget->is64Bit() &&
3757 ((!isa<GlobalAddressSDNode>(Callee) &&
3758 !isa<ExternalSymbolSDNode>(Callee)) ||
3759 DAG.getTarget().getRelocationModel() == Reloc::PIC_)) {
3760 unsigned NumInRegs = 0;
3761 // In PIC we need an extra register to formulate the address computation
3763 unsigned MaxInRegs =
3764 (DAG.getTarget().getRelocationModel() == Reloc::PIC_) ? 2 : 3;
3766 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3767 CCValAssign &VA = ArgLocs[i];
3770 unsigned Reg = VA.getLocReg();
3773 case X86::EAX: case X86::EDX: case X86::ECX:
3774 if (++NumInRegs == MaxInRegs)
3782 bool CalleeWillPop =
3783 X86::isCalleePop(CalleeCC, Subtarget->is64Bit(), isVarArg,
3784 MF.getTarget().Options.GuaranteedTailCallOpt);
3786 if (unsigned BytesToPop =
3787 MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn()) {
3788 // If we have bytes to pop, the callee must pop them.
3789 bool CalleePopMatches = CalleeWillPop && BytesToPop == StackArgsSize;
3790 if (!CalleePopMatches)
3792 } else if (CalleeWillPop && StackArgsSize > 0) {
3793 // If we don't have bytes to pop, make sure the callee doesn't pop any.
3801 X86TargetLowering::createFastISel(FunctionLoweringInfo &funcInfo,
3802 const TargetLibraryInfo *libInfo) const {
3803 return X86::createFastISel(funcInfo, libInfo);
3806 //===----------------------------------------------------------------------===//
3807 // Other Lowering Hooks
3808 //===----------------------------------------------------------------------===//
3810 static bool MayFoldLoad(SDValue Op) {
3811 return Op.hasOneUse() && ISD::isNormalLoad(Op.getNode());
3814 static bool MayFoldIntoStore(SDValue Op) {
3815 return Op.hasOneUse() && ISD::isNormalStore(*Op.getNode()->use_begin());
3818 static bool isTargetShuffle(unsigned Opcode) {
3820 default: return false;
3821 case X86ISD::BLENDI:
3822 case X86ISD::PSHUFB:
3823 case X86ISD::PSHUFD:
3824 case X86ISD::PSHUFHW:
3825 case X86ISD::PSHUFLW:
3827 case X86ISD::PALIGNR:
3828 case X86ISD::MOVLHPS:
3829 case X86ISD::MOVLHPD:
3830 case X86ISD::MOVHLPS:
3831 case X86ISD::MOVLPS:
3832 case X86ISD::MOVLPD:
3833 case X86ISD::MOVSHDUP:
3834 case X86ISD::MOVSLDUP:
3835 case X86ISD::MOVDDUP:
3838 case X86ISD::UNPCKL:
3839 case X86ISD::UNPCKH:
3840 case X86ISD::VPERMILPI:
3841 case X86ISD::VPERM2X128:
3842 case X86ISD::VPERMI:
3843 case X86ISD::VPERMV:
3844 case X86ISD::VPERMV3:
3849 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, MVT VT,
3850 SDValue V1, unsigned TargetMask,
3851 SelectionDAG &DAG) {
3853 default: llvm_unreachable("Unknown x86 shuffle node");
3854 case X86ISD::PSHUFD:
3855 case X86ISD::PSHUFHW:
3856 case X86ISD::PSHUFLW:
3857 case X86ISD::VPERMILPI:
3858 case X86ISD::VPERMI:
3859 return DAG.getNode(Opc, dl, VT, V1,
3860 DAG.getConstant(TargetMask, dl, MVT::i8));
3864 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, MVT VT,
3865 SDValue V1, SDValue V2, SelectionDAG &DAG) {
3867 default: llvm_unreachable("Unknown x86 shuffle node");
3868 case X86ISD::MOVLHPS:
3869 case X86ISD::MOVLHPD:
3870 case X86ISD::MOVHLPS:
3871 case X86ISD::MOVLPS:
3872 case X86ISD::MOVLPD:
3875 case X86ISD::UNPCKL:
3876 case X86ISD::UNPCKH:
3877 return DAG.getNode(Opc, dl, VT, V1, V2);
3881 SDValue X86TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) const {
3882 MachineFunction &MF = DAG.getMachineFunction();
3883 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
3884 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
3885 int ReturnAddrIndex = FuncInfo->getRAIndex();
3887 if (ReturnAddrIndex == 0) {
3888 // Set up a frame object for the return address.
3889 unsigned SlotSize = RegInfo->getSlotSize();
3890 ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(SlotSize,
3893 FuncInfo->setRAIndex(ReturnAddrIndex);
3896 return DAG.getFrameIndex(ReturnAddrIndex, getPointerTy(DAG.getDataLayout()));
3899 bool X86::isOffsetSuitableForCodeModel(int64_t Offset, CodeModel::Model M,
3900 bool hasSymbolicDisplacement) {
3901 // Offset should fit into 32 bit immediate field.
3902 if (!isInt<32>(Offset))
3905 // If we don't have a symbolic displacement - we don't have any extra
3907 if (!hasSymbolicDisplacement)
3910 // FIXME: Some tweaks might be needed for medium code model.
3911 if (M != CodeModel::Small && M != CodeModel::Kernel)
3914 // For small code model we assume that latest object is 16MB before end of 31
3915 // bits boundary. We may also accept pretty large negative constants knowing
3916 // that all objects are in the positive half of address space.
3917 if (M == CodeModel::Small && Offset < 16*1024*1024)
3920 // For kernel code model we know that all object resist in the negative half
3921 // of 32bits address space. We may not accept negative offsets, since they may
3922 // be just off and we may accept pretty large positive ones.
3923 if (M == CodeModel::Kernel && Offset >= 0)
3929 /// Determines whether the callee is required to pop its own arguments.
3930 /// Callee pop is necessary to support tail calls.
3931 bool X86::isCalleePop(CallingConv::ID CallingConv,
3932 bool is64Bit, bool IsVarArg, bool GuaranteeTCO) {
3933 // If GuaranteeTCO is true, we force some calls to be callee pop so that we
3934 // can guarantee TCO.
3935 if (!IsVarArg && shouldGuaranteeTCO(CallingConv, GuaranteeTCO))
3938 switch (CallingConv) {
3941 case CallingConv::X86_StdCall:
3942 case CallingConv::X86_FastCall:
3943 case CallingConv::X86_ThisCall:
3944 case CallingConv::X86_VectorCall:
3949 /// \brief Return true if the condition is an unsigned comparison operation.
3950 static bool isX86CCUnsigned(unsigned X86CC) {
3952 default: llvm_unreachable("Invalid integer condition!");
3953 case X86::COND_E: return true;
3954 case X86::COND_G: return false;
3955 case X86::COND_GE: return false;
3956 case X86::COND_L: return false;
3957 case X86::COND_LE: return false;
3958 case X86::COND_NE: return true;
3959 case X86::COND_B: return true;
3960 case X86::COND_A: return true;
3961 case X86::COND_BE: return true;
3962 case X86::COND_AE: return true;
3966 static X86::CondCode TranslateIntegerX86CC(ISD::CondCode SetCCOpcode) {
3967 switch (SetCCOpcode) {
3968 default: llvm_unreachable("Invalid integer condition!");
3969 case ISD::SETEQ: return X86::COND_E;
3970 case ISD::SETGT: return X86::COND_G;
3971 case ISD::SETGE: return X86::COND_GE;
3972 case ISD::SETLT: return X86::COND_L;
3973 case ISD::SETLE: return X86::COND_LE;
3974 case ISD::SETNE: return X86::COND_NE;
3975 case ISD::SETULT: return X86::COND_B;
3976 case ISD::SETUGT: return X86::COND_A;
3977 case ISD::SETULE: return X86::COND_BE;
3978 case ISD::SETUGE: return X86::COND_AE;
3982 /// Do a one-to-one translation of a ISD::CondCode to the X86-specific
3983 /// condition code, returning the condition code and the LHS/RHS of the
3984 /// comparison to make.
3985 static unsigned TranslateX86CC(ISD::CondCode SetCCOpcode, SDLoc DL, bool isFP,
3986 SDValue &LHS, SDValue &RHS, SelectionDAG &DAG) {
3988 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
3989 if (SetCCOpcode == ISD::SETGT && RHSC->isAllOnesValue()) {
3990 // X > -1 -> X == 0, jump !sign.
3991 RHS = DAG.getConstant(0, DL, RHS.getValueType());
3992 return X86::COND_NS;
3994 if (SetCCOpcode == ISD::SETLT && RHSC->isNullValue()) {
3995 // X < 0 -> X == 0, jump on sign.
3998 if (SetCCOpcode == ISD::SETLT && RHSC->getZExtValue() == 1) {
4000 RHS = DAG.getConstant(0, DL, RHS.getValueType());
4001 return X86::COND_LE;
4005 return TranslateIntegerX86CC(SetCCOpcode);
4008 // First determine if it is required or is profitable to flip the operands.
4010 // If LHS is a foldable load, but RHS is not, flip the condition.
4011 if (ISD::isNON_EXTLoad(LHS.getNode()) &&
4012 !ISD::isNON_EXTLoad(RHS.getNode())) {
4013 SetCCOpcode = getSetCCSwappedOperands(SetCCOpcode);
4014 std::swap(LHS, RHS);
4017 switch (SetCCOpcode) {
4023 std::swap(LHS, RHS);
4027 // On a floating point condition, the flags are set as follows:
4029 // 0 | 0 | 0 | X > Y
4030 // 0 | 0 | 1 | X < Y
4031 // 1 | 0 | 0 | X == Y
4032 // 1 | 1 | 1 | unordered
4033 switch (SetCCOpcode) {
4034 default: llvm_unreachable("Condcode should be pre-legalized away");
4036 case ISD::SETEQ: return X86::COND_E;
4037 case ISD::SETOLT: // flipped
4039 case ISD::SETGT: return X86::COND_A;
4040 case ISD::SETOLE: // flipped
4042 case ISD::SETGE: return X86::COND_AE;
4043 case ISD::SETUGT: // flipped
4045 case ISD::SETLT: return X86::COND_B;
4046 case ISD::SETUGE: // flipped
4048 case ISD::SETLE: return X86::COND_BE;
4050 case ISD::SETNE: return X86::COND_NE;
4051 case ISD::SETUO: return X86::COND_P;
4052 case ISD::SETO: return X86::COND_NP;
4054 case ISD::SETUNE: return X86::COND_INVALID;
4058 /// Is there a floating point cmov for the specific X86 condition code?
4059 /// Current x86 isa includes the following FP cmov instructions:
4060 /// fcmovb, fcomvbe, fcomve, fcmovu, fcmovae, fcmova, fcmovne, fcmovnu.
4061 static bool hasFPCMov(unsigned X86CC) {
4077 /// Returns true if the target can instruction select the
4078 /// specified FP immediate natively. If false, the legalizer will
4079 /// materialize the FP immediate as a load from a constant pool.
4080 bool X86TargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
4081 for (unsigned i = 0, e = LegalFPImmediates.size(); i != e; ++i) {
4082 if (Imm.bitwiseIsEqual(LegalFPImmediates[i]))
4088 bool X86TargetLowering::shouldReduceLoadWidth(SDNode *Load,
4089 ISD::LoadExtType ExtTy,
4091 // "ELF Handling for Thread-Local Storage" specifies that R_X86_64_GOTTPOFF
4092 // relocation target a movq or addq instruction: don't let the load shrink.
4093 SDValue BasePtr = cast<LoadSDNode>(Load)->getBasePtr();
4094 if (BasePtr.getOpcode() == X86ISD::WrapperRIP)
4095 if (const auto *GA = dyn_cast<GlobalAddressSDNode>(BasePtr.getOperand(0)))
4096 return GA->getTargetFlags() != X86II::MO_GOTTPOFF;
4100 /// \brief Returns true if it is beneficial to convert a load of a constant
4101 /// to just the constant itself.
4102 bool X86TargetLowering::shouldConvertConstantLoadToIntImm(const APInt &Imm,
4104 assert(Ty->isIntegerTy());
4106 unsigned BitSize = Ty->getPrimitiveSizeInBits();
4107 if (BitSize == 0 || BitSize > 64)
4112 bool X86TargetLowering::isExtractSubvectorCheap(EVT ResVT,
4113 unsigned Index) const {
4114 if (!isOperationLegalOrCustom(ISD::EXTRACT_SUBVECTOR, ResVT))
4117 return (Index == 0 || Index == ResVT.getVectorNumElements());
4120 bool X86TargetLowering::isCheapToSpeculateCttz() const {
4121 // Speculate cttz only if we can directly use TZCNT.
4122 return Subtarget->hasBMI();
4125 bool X86TargetLowering::isCheapToSpeculateCtlz() const {
4126 // Speculate ctlz only if we can directly use LZCNT.
4127 return Subtarget->hasLZCNT();
4130 /// Return true if every element in Mask, beginning
4131 /// from position Pos and ending in Pos+Size is undef.
4132 static bool isUndefInRange(ArrayRef<int> Mask, unsigned Pos, unsigned Size) {
4133 for (unsigned i = Pos, e = Pos + Size; i != e; ++i)
4139 /// Return true if Val is undef or if its value falls within the
4140 /// specified range (L, H].
4141 static bool isUndefOrInRange(int Val, int Low, int Hi) {
4142 return (Val < 0) || (Val >= Low && Val < Hi);
4145 /// Val is either less than zero (undef) or equal to the specified value.
4146 static bool isUndefOrEqual(int Val, int CmpVal) {
4147 return (Val < 0 || Val == CmpVal);
4150 /// Return true if every element in Mask, beginning
4151 /// from position Pos and ending in Pos+Size, falls within the specified
4152 /// sequential range (Low, Low+Size]. or is undef.
4153 static bool isSequentialOrUndefInRange(ArrayRef<int> Mask,
4154 unsigned Pos, unsigned Size, int Low) {
4155 for (unsigned i = Pos, e = Pos+Size; i != e; ++i, ++Low)
4156 if (!isUndefOrEqual(Mask[i], Low))
4161 /// Return true if the specified EXTRACT_SUBVECTOR operand specifies a vector
4162 /// extract that is suitable for instruction that extract 128 or 256 bit vectors
4163 static bool isVEXTRACTIndex(SDNode *N, unsigned vecWidth) {
4164 assert((vecWidth == 128 || vecWidth == 256) && "Unexpected vector width");
4165 if (!isa<ConstantSDNode>(N->getOperand(1).getNode()))
4168 // The index should be aligned on a vecWidth-bit boundary.
4170 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
4172 MVT VT = N->getSimpleValueType(0);
4173 unsigned ElSize = VT.getVectorElementType().getSizeInBits();
4174 bool Result = (Index * ElSize) % vecWidth == 0;
4179 /// Return true if the specified INSERT_SUBVECTOR
4180 /// operand specifies a subvector insert that is suitable for input to
4181 /// insertion of 128 or 256-bit subvectors
4182 static bool isVINSERTIndex(SDNode *N, unsigned vecWidth) {
4183 assert((vecWidth == 128 || vecWidth == 256) && "Unexpected vector width");
4184 if (!isa<ConstantSDNode>(N->getOperand(2).getNode()))
4186 // The index should be aligned on a vecWidth-bit boundary.
4188 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
4190 MVT VT = N->getSimpleValueType(0);
4191 unsigned ElSize = VT.getVectorElementType().getSizeInBits();
4192 bool Result = (Index * ElSize) % vecWidth == 0;
4197 bool X86::isVINSERT128Index(SDNode *N) {
4198 return isVINSERTIndex(N, 128);
4201 bool X86::isVINSERT256Index(SDNode *N) {
4202 return isVINSERTIndex(N, 256);
4205 bool X86::isVEXTRACT128Index(SDNode *N) {
4206 return isVEXTRACTIndex(N, 128);
4209 bool X86::isVEXTRACT256Index(SDNode *N) {
4210 return isVEXTRACTIndex(N, 256);
4213 static unsigned getExtractVEXTRACTImmediate(SDNode *N, unsigned vecWidth) {
4214 assert((vecWidth == 128 || vecWidth == 256) && "Unsupported vector width");
4215 assert(isa<ConstantSDNode>(N->getOperand(1).getNode()) &&
4216 "Illegal extract subvector for VEXTRACT");
4219 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
4221 MVT VecVT = N->getOperand(0).getSimpleValueType();
4222 MVT ElVT = VecVT.getVectorElementType();
4224 unsigned NumElemsPerChunk = vecWidth / ElVT.getSizeInBits();
4225 return Index / NumElemsPerChunk;
4228 static unsigned getInsertVINSERTImmediate(SDNode *N, unsigned vecWidth) {
4229 assert((vecWidth == 128 || vecWidth == 256) && "Unsupported vector width");
4230 assert(isa<ConstantSDNode>(N->getOperand(2).getNode()) &&
4231 "Illegal insert subvector for VINSERT");
4234 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
4236 MVT VecVT = N->getSimpleValueType(0);
4237 MVT ElVT = VecVT.getVectorElementType();
4239 unsigned NumElemsPerChunk = vecWidth / ElVT.getSizeInBits();
4240 return Index / NumElemsPerChunk;
4243 /// Return the appropriate immediate to extract the specified
4244 /// EXTRACT_SUBVECTOR index with VEXTRACTF128 and VINSERTI128 instructions.
4245 unsigned X86::getExtractVEXTRACT128Immediate(SDNode *N) {
4246 return getExtractVEXTRACTImmediate(N, 128);
4249 /// Return the appropriate immediate to extract the specified
4250 /// EXTRACT_SUBVECTOR index with VEXTRACTF64x4 and VINSERTI64x4 instructions.
4251 unsigned X86::getExtractVEXTRACT256Immediate(SDNode *N) {
4252 return getExtractVEXTRACTImmediate(N, 256);
4255 /// Return the appropriate immediate to insert at the specified
4256 /// INSERT_SUBVECTOR index with VINSERTF128 and VINSERTI128 instructions.
4257 unsigned X86::getInsertVINSERT128Immediate(SDNode *N) {
4258 return getInsertVINSERTImmediate(N, 128);
4261 /// Return the appropriate immediate to insert at the specified
4262 /// INSERT_SUBVECTOR index with VINSERTF46x4 and VINSERTI64x4 instructions.
4263 unsigned X86::getInsertVINSERT256Immediate(SDNode *N) {
4264 return getInsertVINSERTImmediate(N, 256);
4267 /// Returns true if Elt is a constant zero or a floating point constant +0.0.
4268 bool X86::isZeroNode(SDValue Elt) {
4269 return isNullConstant(Elt) || isNullFPConstant(Elt);
4272 // Build a vector of constants
4273 // Use an UNDEF node if MaskElt == -1.
4274 // Spilt 64-bit constants in the 32-bit mode.
4275 static SDValue getConstVector(ArrayRef<int> Values, MVT VT,
4277 SDLoc dl, bool IsMask = false) {
4279 SmallVector<SDValue, 32> Ops;
4282 MVT ConstVecVT = VT;
4283 unsigned NumElts = VT.getVectorNumElements();
4284 bool In64BitMode = DAG.getTargetLoweringInfo().isTypeLegal(MVT::i64);
4285 if (!In64BitMode && VT.getVectorElementType() == MVT::i64) {
4286 ConstVecVT = MVT::getVectorVT(MVT::i32, NumElts * 2);
4290 MVT EltVT = ConstVecVT.getVectorElementType();
4291 for (unsigned i = 0; i < NumElts; ++i) {
4292 bool IsUndef = Values[i] < 0 && IsMask;
4293 SDValue OpNode = IsUndef ? DAG.getUNDEF(EltVT) :
4294 DAG.getConstant(Values[i], dl, EltVT);
4295 Ops.push_back(OpNode);
4297 Ops.push_back(IsUndef ? DAG.getUNDEF(EltVT) :
4298 DAG.getConstant(0, dl, EltVT));
4300 SDValue ConstsNode = DAG.getNode(ISD::BUILD_VECTOR, dl, ConstVecVT, Ops);
4302 ConstsNode = DAG.getBitcast(VT, ConstsNode);
4306 /// Returns a vector of specified type with all zero elements.
4307 static SDValue getZeroVector(EVT VT, const X86Subtarget *Subtarget,
4308 SelectionDAG &DAG, SDLoc dl) {
4309 assert(VT.isVector() && "Expected a vector type");
4311 // Always build SSE zero vectors as <4 x i32> bitcasted
4312 // to their dest type. This ensures they get CSE'd.
4314 if (VT.is128BitVector()) { // SSE
4315 if (Subtarget->hasSSE2()) { // SSE2
4316 SDValue Cst = DAG.getConstant(0, dl, MVT::i32);
4317 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4319 SDValue Cst = DAG.getConstantFP(+0.0, dl, MVT::f32);
4320 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4f32, Cst, Cst, Cst, Cst);
4322 } else if (VT.is256BitVector()) { // AVX
4323 if (Subtarget->hasInt256()) { // AVX2
4324 SDValue Cst = DAG.getConstant(0, dl, MVT::i32);
4325 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4326 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops);
4328 // 256-bit logic and arithmetic instructions in AVX are all
4329 // floating-point, no support for integer ops. Emit fp zeroed vectors.
4330 SDValue Cst = DAG.getConstantFP(+0.0, dl, MVT::f32);
4331 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4332 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8f32, Ops);
4334 } else if (VT.is512BitVector()) { // AVX-512
4335 SDValue Cst = DAG.getConstant(0, dl, MVT::i32);
4336 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst,
4337 Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4338 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v16i32, Ops);
4339 } else if (VT.getVectorElementType() == MVT::i1) {
4341 assert((Subtarget->hasBWI() || VT.getVectorNumElements() <= 16)
4342 && "Unexpected vector type");
4343 assert((Subtarget->hasVLX() || VT.getVectorNumElements() >= 8)
4344 && "Unexpected vector type");
4345 SDValue Cst = DAG.getConstant(0, dl, MVT::i1);
4346 SmallVector<SDValue, 64> Ops(VT.getVectorNumElements(), Cst);
4347 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
4349 llvm_unreachable("Unexpected vector type");
4351 return DAG.getBitcast(VT, Vec);
4354 static SDValue ExtractSubVector(SDValue Vec, unsigned IdxVal,
4355 SelectionDAG &DAG, SDLoc dl,
4356 unsigned vectorWidth) {
4357 assert((vectorWidth == 128 || vectorWidth == 256) &&
4358 "Unsupported vector width");
4359 EVT VT = Vec.getValueType();
4360 EVT ElVT = VT.getVectorElementType();
4361 unsigned Factor = VT.getSizeInBits()/vectorWidth;
4362 EVT ResultVT = EVT::getVectorVT(*DAG.getContext(), ElVT,
4363 VT.getVectorNumElements()/Factor);
4365 // Extract from UNDEF is UNDEF.
4366 if (Vec.getOpcode() == ISD::UNDEF)
4367 return DAG.getUNDEF(ResultVT);
4369 // Extract the relevant vectorWidth bits. Generate an EXTRACT_SUBVECTOR
4370 unsigned ElemsPerChunk = vectorWidth / ElVT.getSizeInBits();
4371 assert(isPowerOf2_32(ElemsPerChunk) && "Elements per chunk not power of 2");
4373 // This is the index of the first element of the vectorWidth-bit chunk
4374 // we want. Since ElemsPerChunk is a power of 2 just need to clear bits.
4375 IdxVal &= ~(ElemsPerChunk - 1);
4377 // If the input is a buildvector just emit a smaller one.
4378 if (Vec.getOpcode() == ISD::BUILD_VECTOR)
4379 return DAG.getNode(ISD::BUILD_VECTOR, dl, ResultVT,
4380 makeArrayRef(Vec->op_begin() + IdxVal, ElemsPerChunk));
4382 SDValue VecIdx = DAG.getIntPtrConstant(IdxVal, dl);
4383 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, ResultVT, Vec, VecIdx);
4386 /// Generate a DAG to grab 128-bits from a vector > 128 bits. This
4387 /// sets things up to match to an AVX VEXTRACTF128 / VEXTRACTI128
4388 /// or AVX-512 VEXTRACTF32x4 / VEXTRACTI32x4
4389 /// instructions or a simple subregister reference. Idx is an index in the
4390 /// 128 bits we want. It need not be aligned to a 128-bit boundary. That makes
4391 /// lowering EXTRACT_VECTOR_ELT operations easier.
4392 static SDValue Extract128BitVector(SDValue Vec, unsigned IdxVal,
4393 SelectionDAG &DAG, SDLoc dl) {
4394 assert((Vec.getValueType().is256BitVector() ||
4395 Vec.getValueType().is512BitVector()) && "Unexpected vector size!");
4396 return ExtractSubVector(Vec, IdxVal, DAG, dl, 128);
4399 /// Generate a DAG to grab 256-bits from a 512-bit vector.
4400 static SDValue Extract256BitVector(SDValue Vec, unsigned IdxVal,
4401 SelectionDAG &DAG, SDLoc dl) {
4402 assert(Vec.getValueType().is512BitVector() && "Unexpected vector size!");
4403 return ExtractSubVector(Vec, IdxVal, DAG, dl, 256);
4406 static SDValue InsertSubVector(SDValue Result, SDValue Vec,
4407 unsigned IdxVal, SelectionDAG &DAG,
4408 SDLoc dl, unsigned vectorWidth) {
4409 assert((vectorWidth == 128 || vectorWidth == 256) &&
4410 "Unsupported vector width");
4411 // Inserting UNDEF is Result
4412 if (Vec.getOpcode() == ISD::UNDEF)
4414 EVT VT = Vec.getValueType();
4415 EVT ElVT = VT.getVectorElementType();
4416 EVT ResultVT = Result.getValueType();
4418 // Insert the relevant vectorWidth bits.
4419 unsigned ElemsPerChunk = vectorWidth/ElVT.getSizeInBits();
4420 assert(isPowerOf2_32(ElemsPerChunk) && "Elements per chunk not power of 2");
4422 // This is the index of the first element of the vectorWidth-bit chunk
4423 // we want. Since ElemsPerChunk is a power of 2 just need to clear bits.
4424 IdxVal &= ~(ElemsPerChunk - 1);
4426 SDValue VecIdx = DAG.getIntPtrConstant(IdxVal, dl);
4427 return DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResultVT, Result, Vec, VecIdx);
4430 /// Generate a DAG to put 128-bits into a vector > 128 bits. This
4431 /// sets things up to match to an AVX VINSERTF128/VINSERTI128 or
4432 /// AVX-512 VINSERTF32x4/VINSERTI32x4 instructions or a
4433 /// simple superregister reference. Idx is an index in the 128 bits
4434 /// we want. It need not be aligned to a 128-bit boundary. That makes
4435 /// lowering INSERT_VECTOR_ELT operations easier.
4436 static SDValue Insert128BitVector(SDValue Result, SDValue Vec, unsigned IdxVal,
4437 SelectionDAG &DAG, SDLoc dl) {
4438 assert(Vec.getValueType().is128BitVector() && "Unexpected vector size!");
4440 // For insertion into the zero index (low half) of a 256-bit vector, it is
4441 // more efficient to generate a blend with immediate instead of an insert*128.
4442 // We are still creating an INSERT_SUBVECTOR below with an undef node to
4443 // extend the subvector to the size of the result vector. Make sure that
4444 // we are not recursing on that node by checking for undef here.
4445 if (IdxVal == 0 && Result.getValueType().is256BitVector() &&
4446 Result.getOpcode() != ISD::UNDEF) {
4447 EVT ResultVT = Result.getValueType();
4448 SDValue ZeroIndex = DAG.getIntPtrConstant(0, dl);
4449 SDValue Undef = DAG.getUNDEF(ResultVT);
4450 SDValue Vec256 = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResultVT, Undef,
4453 // The blend instruction, and therefore its mask, depend on the data type.
4454 MVT ScalarType = ResultVT.getVectorElementType().getSimpleVT();
4455 if (ScalarType.isFloatingPoint()) {
4456 // Choose either vblendps (float) or vblendpd (double).
4457 unsigned ScalarSize = ScalarType.getSizeInBits();
4458 assert((ScalarSize == 64 || ScalarSize == 32) && "Unknown float type");
4459 unsigned MaskVal = (ScalarSize == 64) ? 0x03 : 0x0f;
4460 SDValue Mask = DAG.getConstant(MaskVal, dl, MVT::i8);
4461 return DAG.getNode(X86ISD::BLENDI, dl, ResultVT, Result, Vec256, Mask);
4464 const X86Subtarget &Subtarget =
4465 static_cast<const X86Subtarget &>(DAG.getSubtarget());
4467 // AVX2 is needed for 256-bit integer blend support.
4468 // Integers must be cast to 32-bit because there is only vpblendd;
4469 // vpblendw can't be used for this because it has a handicapped mask.
4471 // If we don't have AVX2, then cast to float. Using a wrong domain blend
4472 // is still more efficient than using the wrong domain vinsertf128 that
4473 // will be created by InsertSubVector().
4474 MVT CastVT = Subtarget.hasAVX2() ? MVT::v8i32 : MVT::v8f32;
4476 SDValue Mask = DAG.getConstant(0x0f, dl, MVT::i8);
4477 Vec256 = DAG.getBitcast(CastVT, Vec256);
4478 Vec256 = DAG.getNode(X86ISD::BLENDI, dl, CastVT, Result, Vec256, Mask);
4479 return DAG.getBitcast(ResultVT, Vec256);
4482 return InsertSubVector(Result, Vec, IdxVal, DAG, dl, 128);
4485 static SDValue Insert256BitVector(SDValue Result, SDValue Vec, unsigned IdxVal,
4486 SelectionDAG &DAG, SDLoc dl) {
4487 assert(Vec.getValueType().is256BitVector() && "Unexpected vector size!");
4488 return InsertSubVector(Result, Vec, IdxVal, DAG, dl, 256);
4491 /// Insert i1-subvector to i1-vector.
4492 static SDValue Insert1BitVector(SDValue Op, SelectionDAG &DAG) {
4495 SDValue Vec = Op.getOperand(0);
4496 SDValue SubVec = Op.getOperand(1);
4497 SDValue Idx = Op.getOperand(2);
4499 if (!isa<ConstantSDNode>(Idx))
4502 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
4503 if (IdxVal == 0 && Vec.isUndef()) // the operation is legal
4506 MVT OpVT = Op.getSimpleValueType();
4507 MVT SubVecVT = SubVec.getSimpleValueType();
4508 unsigned NumElems = OpVT.getVectorNumElements();
4509 unsigned SubVecNumElems = SubVecVT.getVectorNumElements();
4511 assert(IdxVal + SubVecNumElems <= NumElems &&
4512 IdxVal % SubVecVT.getSizeInBits() == 0 &&
4513 "Unexpected index value in INSERT_SUBVECTOR");
4515 // There are 3 possible cases:
4516 // 1. Subvector should be inserted in the lower part (IdxVal == 0)
4517 // 2. Subvector should be inserted in the upper part
4518 // (IdxVal + SubVecNumElems == NumElems)
4519 // 3. Subvector should be inserted in the middle (for example v2i1
4520 // to v16i1, index 2)
4522 SDValue ZeroIdx = DAG.getIntPtrConstant(0, dl);
4523 SDValue Undef = DAG.getUNDEF(OpVT);
4524 SDValue WideSubVec =
4525 DAG.getNode(ISD::INSERT_SUBVECTOR, dl, OpVT, Undef, SubVec, ZeroIdx);
4527 return DAG.getNode(X86ISD::VSHLI, dl, OpVT, WideSubVec,
4528 DAG.getConstant(IdxVal, dl, MVT::i8));
4530 if (ISD::isBuildVectorAllZeros(Vec.getNode())) {
4531 unsigned ShiftLeft = NumElems - SubVecNumElems;
4532 unsigned ShiftRight = NumElems - SubVecNumElems - IdxVal;
4533 WideSubVec = DAG.getNode(X86ISD::VSHLI, dl, OpVT, WideSubVec,
4534 DAG.getConstant(ShiftLeft, dl, MVT::i8));
4535 return ShiftRight ? DAG.getNode(X86ISD::VSRLI, dl, OpVT, WideSubVec,
4536 DAG.getConstant(ShiftRight, dl, MVT::i8)) : WideSubVec;
4540 // Zero lower bits of the Vec
4541 SDValue ShiftBits = DAG.getConstant(SubVecNumElems, dl, MVT::i8);
4542 Vec = DAG.getNode(X86ISD::VSRLI, dl, OpVT, Vec, ShiftBits);
4543 Vec = DAG.getNode(X86ISD::VSHLI, dl, OpVT, Vec, ShiftBits);
4544 // Merge them together
4545 return DAG.getNode(ISD::OR, dl, OpVT, Vec, WideSubVec);
4548 // Simple case when we put subvector in the upper part
4549 if (IdxVal + SubVecNumElems == NumElems) {
4550 // Zero upper bits of the Vec
4551 WideSubVec = DAG.getNode(X86ISD::VSHLI, dl, OpVT, Vec,
4552 DAG.getConstant(IdxVal, dl, MVT::i8));
4553 SDValue ShiftBits = DAG.getConstant(SubVecNumElems, dl, MVT::i8);
4554 Vec = DAG.getNode(X86ISD::VSHLI, dl, OpVT, Vec, ShiftBits);
4555 Vec = DAG.getNode(X86ISD::VSRLI, dl, OpVT, Vec, ShiftBits);
4556 return DAG.getNode(ISD::OR, dl, OpVT, Vec, WideSubVec);
4558 // Subvector should be inserted in the middle - use shuffle
4559 SmallVector<int, 64> Mask;
4560 for (unsigned i = 0; i < NumElems; ++i)
4561 Mask.push_back(i >= IdxVal && i < IdxVal + SubVecNumElems ?
4563 return DAG.getVectorShuffle(OpVT, dl, WideSubVec, Vec, Mask);
4566 /// Concat two 128-bit vectors into a 256 bit vector using VINSERTF128
4567 /// instructions. This is used because creating CONCAT_VECTOR nodes of
4568 /// BUILD_VECTORS returns a larger BUILD_VECTOR while we're trying to lower
4569 /// large BUILD_VECTORS.
4570 static SDValue Concat128BitVectors(SDValue V1, SDValue V2, EVT VT,
4571 unsigned NumElems, SelectionDAG &DAG,
4573 SDValue V = Insert128BitVector(DAG.getUNDEF(VT), V1, 0, DAG, dl);
4574 return Insert128BitVector(V, V2, NumElems/2, DAG, dl);
4577 static SDValue Concat256BitVectors(SDValue V1, SDValue V2, EVT VT,
4578 unsigned NumElems, SelectionDAG &DAG,
4580 SDValue V = Insert256BitVector(DAG.getUNDEF(VT), V1, 0, DAG, dl);
4581 return Insert256BitVector(V, V2, NumElems/2, DAG, dl);
4584 /// Returns a vector of specified type with all bits set.
4585 /// Always build ones vectors as <4 x i32> or <8 x i32>. For 256-bit types with
4586 /// no AVX2 supprt, use two <4 x i32> inserted in a <8 x i32> appropriately.
4587 /// Then bitcast to their original type, ensuring they get CSE'd.
4588 static SDValue getOnesVector(EVT VT, const X86Subtarget *Subtarget,
4589 SelectionDAG &DAG, SDLoc dl) {
4590 assert(VT.isVector() && "Expected a vector type");
4592 SDValue Cst = DAG.getConstant(~0U, dl, MVT::i32);
4594 if (VT.is512BitVector()) {
4595 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst,
4596 Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4597 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v16i32, Ops);
4598 } else if (VT.is256BitVector()) {
4599 if (Subtarget->hasInt256()) { // AVX2
4600 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4601 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops);
4603 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4604 Vec = Concat128BitVectors(Vec, Vec, MVT::v8i32, 8, DAG, dl);
4606 } else if (VT.is128BitVector()) {
4607 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4609 llvm_unreachable("Unexpected vector type");
4611 return DAG.getBitcast(VT, Vec);
4614 /// Returns a vector_shuffle node for an unpackl operation.
4615 static SDValue getUnpackl(SelectionDAG &DAG, SDLoc dl, MVT VT, SDValue V1,
4617 unsigned NumElems = VT.getVectorNumElements();
4618 SmallVector<int, 8> Mask;
4619 for (unsigned i = 0, e = NumElems/2; i != e; ++i) {
4621 Mask.push_back(i + NumElems);
4623 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
4626 /// Returns a vector_shuffle node for an unpackh operation.
4627 static SDValue getUnpackh(SelectionDAG &DAG, SDLoc dl, MVT VT, SDValue V1,
4629 unsigned NumElems = VT.getVectorNumElements();
4630 SmallVector<int, 8> Mask;
4631 for (unsigned i = 0, Half = NumElems/2; i != Half; ++i) {
4632 Mask.push_back(i + Half);
4633 Mask.push_back(i + NumElems + Half);
4635 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
4638 /// Return a vector_shuffle of the specified vector of zero or undef vector.
4639 /// This produces a shuffle where the low element of V2 is swizzled into the
4640 /// zero/undef vector, landing at element Idx.
4641 /// This produces a shuffle mask like 4,1,2,3 (idx=0) or 0,1,2,4 (idx=3).
4642 static SDValue getShuffleVectorZeroOrUndef(SDValue V2, unsigned Idx,
4644 const X86Subtarget *Subtarget,
4645 SelectionDAG &DAG) {
4646 MVT VT = V2.getSimpleValueType();
4648 ? getZeroVector(VT, Subtarget, DAG, SDLoc(V2)) : DAG.getUNDEF(VT);
4649 unsigned NumElems = VT.getVectorNumElements();
4650 SmallVector<int, 16> MaskVec;
4651 for (unsigned i = 0; i != NumElems; ++i)
4652 // If this is the insertion idx, put the low elt of V2 here.
4653 MaskVec.push_back(i == Idx ? NumElems : i);
4654 return DAG.getVectorShuffle(VT, SDLoc(V2), V1, V2, &MaskVec[0]);
4657 /// Calculates the shuffle mask corresponding to the target-specific opcode.
4658 /// Returns true if the Mask could be calculated. Sets IsUnary to true if only
4659 /// uses one source. Note that this will set IsUnary for shuffles which use a
4660 /// single input multiple times, and in those cases it will
4661 /// adjust the mask to only have indices within that single input.
4662 /// FIXME: Add support for Decode*Mask functions that return SM_SentinelZero.
4663 static bool getTargetShuffleMask(SDNode *N, MVT VT,
4664 SmallVectorImpl<int> &Mask, bool &IsUnary) {
4665 unsigned NumElems = VT.getVectorNumElements();
4669 bool IsFakeUnary = false;
4670 switch(N->getOpcode()) {
4671 case X86ISD::BLENDI:
4672 ImmN = N->getOperand(N->getNumOperands()-1);
4673 DecodeBLENDMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4676 ImmN = N->getOperand(N->getNumOperands()-1);
4677 DecodeSHUFPMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4678 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
4680 case X86ISD::UNPCKH:
4681 DecodeUNPCKHMask(VT, Mask);
4682 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
4684 case X86ISD::UNPCKL:
4685 DecodeUNPCKLMask(VT, Mask);
4686 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
4688 case X86ISD::MOVHLPS:
4689 DecodeMOVHLPSMask(NumElems, Mask);
4690 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
4692 case X86ISD::MOVLHPS:
4693 DecodeMOVLHPSMask(NumElems, Mask);
4694 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
4696 case X86ISD::PALIGNR:
4697 ImmN = N->getOperand(N->getNumOperands()-1);
4698 DecodePALIGNRMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4700 case X86ISD::PSHUFD:
4701 case X86ISD::VPERMILPI:
4702 ImmN = N->getOperand(N->getNumOperands()-1);
4703 DecodePSHUFMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4706 case X86ISD::PSHUFHW:
4707 ImmN = N->getOperand(N->getNumOperands()-1);
4708 DecodePSHUFHWMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4711 case X86ISD::PSHUFLW:
4712 ImmN = N->getOperand(N->getNumOperands()-1);
4713 DecodePSHUFLWMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4716 case X86ISD::PSHUFB: {
4718 SDValue MaskNode = N->getOperand(1);
4719 while (MaskNode->getOpcode() == ISD::BITCAST)
4720 MaskNode = MaskNode->getOperand(0);
4722 if (MaskNode->getOpcode() == ISD::BUILD_VECTOR) {
4723 // If we have a build-vector, then things are easy.
4724 MVT VT = MaskNode.getSimpleValueType();
4725 assert(VT.isVector() &&
4726 "Can't produce a non-vector with a build_vector!");
4727 if (!VT.isInteger())
4730 int NumBytesPerElement = VT.getVectorElementType().getSizeInBits() / 8;
4732 SmallVector<uint64_t, 32> RawMask;
4733 for (int i = 0, e = MaskNode->getNumOperands(); i < e; ++i) {
4734 SDValue Op = MaskNode->getOperand(i);
4735 if (Op->getOpcode() == ISD::UNDEF) {
4736 RawMask.push_back((uint64_t)SM_SentinelUndef);
4739 auto *CN = dyn_cast<ConstantSDNode>(Op.getNode());
4742 APInt MaskElement = CN->getAPIntValue();
4744 // We now have to decode the element which could be any integer size and
4745 // extract each byte of it.
4746 for (int j = 0; j < NumBytesPerElement; ++j) {
4747 // Note that this is x86 and so always little endian: the low byte is
4748 // the first byte of the mask.
4749 RawMask.push_back(MaskElement.getLoBits(8).getZExtValue());
4750 MaskElement = MaskElement.lshr(8);
4753 DecodePSHUFBMask(RawMask, Mask);
4757 auto *MaskLoad = dyn_cast<LoadSDNode>(MaskNode);
4761 SDValue Ptr = MaskLoad->getBasePtr();
4762 if (Ptr->getOpcode() == X86ISD::Wrapper ||
4763 Ptr->getOpcode() == X86ISD::WrapperRIP)
4764 Ptr = Ptr->getOperand(0);
4766 auto *MaskCP = dyn_cast<ConstantPoolSDNode>(Ptr);
4767 if (!MaskCP || MaskCP->isMachineConstantPoolEntry())
4770 if (auto *C = dyn_cast<Constant>(MaskCP->getConstVal())) {
4771 DecodePSHUFBMask(C, Mask);
4779 case X86ISD::VPERMI:
4780 ImmN = N->getOperand(N->getNumOperands()-1);
4781 DecodeVPERMMask(cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4786 DecodeScalarMoveMask(VT, /* IsLoad */ false, Mask);
4788 case X86ISD::VPERM2X128:
4789 ImmN = N->getOperand(N->getNumOperands()-1);
4790 DecodeVPERM2X128Mask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4791 if (Mask.empty()) return false;
4792 // Mask only contains negative index if an element is zero.
4793 if (std::any_of(Mask.begin(), Mask.end(),
4794 [](int M){ return M == SM_SentinelZero; }))
4797 case X86ISD::MOVSLDUP:
4798 DecodeMOVSLDUPMask(VT, Mask);
4801 case X86ISD::MOVSHDUP:
4802 DecodeMOVSHDUPMask(VT, Mask);
4805 case X86ISD::MOVDDUP:
4806 DecodeMOVDDUPMask(VT, Mask);
4809 case X86ISD::MOVLHPD:
4810 case X86ISD::MOVLPD:
4811 case X86ISD::MOVLPS:
4812 // Not yet implemented
4814 case X86ISD::VPERMV: {
4816 SDValue MaskNode = N->getOperand(0);
4817 while (MaskNode->getOpcode() == ISD::BITCAST)
4818 MaskNode = MaskNode->getOperand(0);
4820 unsigned MaskLoBits = Log2_64(VT.getVectorNumElements());
4821 SmallVector<uint64_t, 32> RawMask;
4822 if (MaskNode->getOpcode() == ISD::BUILD_VECTOR) {
4823 // If we have a build-vector, then things are easy.
4824 assert(MaskNode.getSimpleValueType().isInteger() &&
4825 MaskNode.getSimpleValueType().getVectorNumElements() ==
4826 VT.getVectorNumElements());
4828 for (unsigned i = 0; i < MaskNode->getNumOperands(); ++i) {
4829 SDValue Op = MaskNode->getOperand(i);
4830 if (Op->getOpcode() == ISD::UNDEF)
4831 RawMask.push_back((uint64_t)SM_SentinelUndef);
4832 else if (isa<ConstantSDNode>(Op)) {
4833 APInt MaskElement = cast<ConstantSDNode>(Op)->getAPIntValue();
4834 RawMask.push_back(MaskElement.getLoBits(MaskLoBits).getZExtValue());
4838 DecodeVPERMVMask(RawMask, Mask);
4841 if (MaskNode->getOpcode() == X86ISD::VBROADCAST) {
4842 unsigned NumEltsInMask = MaskNode->getNumOperands();
4843 MaskNode = MaskNode->getOperand(0);
4844 auto *CN = dyn_cast<ConstantSDNode>(MaskNode);
4846 APInt MaskEltValue = CN->getAPIntValue();
4847 for (unsigned i = 0; i < NumEltsInMask; ++i)
4848 RawMask.push_back(MaskEltValue.getLoBits(MaskLoBits).getZExtValue());
4849 DecodeVPERMVMask(RawMask, Mask);
4852 // It may be a scalar load
4855 auto *MaskLoad = dyn_cast<LoadSDNode>(MaskNode);
4859 SDValue Ptr = MaskLoad->getBasePtr();
4860 if (Ptr->getOpcode() == X86ISD::Wrapper ||
4861 Ptr->getOpcode() == X86ISD::WrapperRIP)
4862 Ptr = Ptr->getOperand(0);
4864 auto *MaskCP = dyn_cast<ConstantPoolSDNode>(Ptr);
4865 if (!MaskCP || MaskCP->isMachineConstantPoolEntry())
4868 auto *C = dyn_cast<Constant>(MaskCP->getConstVal());
4870 DecodeVPERMVMask(C, VT, Mask);
4877 case X86ISD::VPERMV3: {
4879 SDValue MaskNode = N->getOperand(1);
4880 while (MaskNode->getOpcode() == ISD::BITCAST)
4881 MaskNode = MaskNode->getOperand(1);
4883 if (MaskNode->getOpcode() == ISD::BUILD_VECTOR) {
4884 // If we have a build-vector, then things are easy.
4885 assert(MaskNode.getSimpleValueType().isInteger() &&
4886 MaskNode.getSimpleValueType().getVectorNumElements() ==
4887 VT.getVectorNumElements());
4889 SmallVector<uint64_t, 32> RawMask;
4890 unsigned MaskLoBits = Log2_64(VT.getVectorNumElements()*2);
4892 for (unsigned i = 0; i < MaskNode->getNumOperands(); ++i) {
4893 SDValue Op = MaskNode->getOperand(i);
4894 if (Op->getOpcode() == ISD::UNDEF)
4895 RawMask.push_back((uint64_t)SM_SentinelUndef);
4897 auto *CN = dyn_cast<ConstantSDNode>(Op.getNode());
4900 APInt MaskElement = CN->getAPIntValue();
4901 RawMask.push_back(MaskElement.getLoBits(MaskLoBits).getZExtValue());
4904 DecodeVPERMV3Mask(RawMask, Mask);
4908 auto *MaskLoad = dyn_cast<LoadSDNode>(MaskNode);
4912 SDValue Ptr = MaskLoad->getBasePtr();
4913 if (Ptr->getOpcode() == X86ISD::Wrapper ||
4914 Ptr->getOpcode() == X86ISD::WrapperRIP)
4915 Ptr = Ptr->getOperand(0);
4917 auto *MaskCP = dyn_cast<ConstantPoolSDNode>(Ptr);
4918 if (!MaskCP || MaskCP->isMachineConstantPoolEntry())
4921 auto *C = dyn_cast<Constant>(MaskCP->getConstVal());
4923 DecodeVPERMV3Mask(C, VT, Mask);
4930 default: llvm_unreachable("unknown target shuffle node");
4933 // If we have a fake unary shuffle, the shuffle mask is spread across two
4934 // inputs that are actually the same node. Re-map the mask to always point
4935 // into the first input.
4938 if (M >= (int)Mask.size())
4944 /// Returns the scalar element that will make up the ith
4945 /// element of the result of the vector shuffle.
4946 static SDValue getShuffleScalarElt(SDNode *N, unsigned Index, SelectionDAG &DAG,
4949 return SDValue(); // Limit search depth.
4951 SDValue V = SDValue(N, 0);
4952 EVT VT = V.getValueType();
4953 unsigned Opcode = V.getOpcode();
4955 // Recurse into ISD::VECTOR_SHUFFLE node to find scalars.
4956 if (const ShuffleVectorSDNode *SV = dyn_cast<ShuffleVectorSDNode>(N)) {
4957 int Elt = SV->getMaskElt(Index);
4960 return DAG.getUNDEF(VT.getVectorElementType());
4962 unsigned NumElems = VT.getVectorNumElements();
4963 SDValue NewV = (Elt < (int)NumElems) ? SV->getOperand(0)
4964 : SV->getOperand(1);
4965 return getShuffleScalarElt(NewV.getNode(), Elt % NumElems, DAG, Depth+1);
4968 // Recurse into target specific vector shuffles to find scalars.
4969 if (isTargetShuffle(Opcode)) {
4970 MVT ShufVT = V.getSimpleValueType();
4971 unsigned NumElems = ShufVT.getVectorNumElements();
4972 SmallVector<int, 16> ShuffleMask;
4975 if (!getTargetShuffleMask(N, ShufVT, ShuffleMask, IsUnary))
4978 int Elt = ShuffleMask[Index];
4980 return DAG.getUNDEF(ShufVT.getVectorElementType());
4982 SDValue NewV = (Elt < (int)NumElems) ? N->getOperand(0)
4984 return getShuffleScalarElt(NewV.getNode(), Elt % NumElems, DAG,
4988 // Actual nodes that may contain scalar elements
4989 if (Opcode == ISD::BITCAST) {
4990 V = V.getOperand(0);
4991 EVT SrcVT = V.getValueType();
4992 unsigned NumElems = VT.getVectorNumElements();
4994 if (!SrcVT.isVector() || SrcVT.getVectorNumElements() != NumElems)
4998 if (V.getOpcode() == ISD::SCALAR_TO_VECTOR)
4999 return (Index == 0) ? V.getOperand(0)
5000 : DAG.getUNDEF(VT.getVectorElementType());
5002 if (V.getOpcode() == ISD::BUILD_VECTOR)
5003 return V.getOperand(Index);
5008 /// Custom lower build_vector of v16i8.
5009 static SDValue LowerBuildVectorv16i8(SDValue Op, unsigned NonZeros,
5010 unsigned NumNonZero, unsigned NumZero,
5012 const X86Subtarget* Subtarget,
5013 const TargetLowering &TLI) {
5021 // SSE4.1 - use PINSRB to insert each byte directly.
5022 if (Subtarget->hasSSE41()) {
5023 for (unsigned i = 0; i < 16; ++i) {
5024 bool isNonZero = (NonZeros & (1 << i)) != 0;
5028 V = getZeroVector(MVT::v16i8, Subtarget, DAG, dl);
5030 V = DAG.getUNDEF(MVT::v16i8);
5033 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl,
5034 MVT::v16i8, V, Op.getOperand(i),
5035 DAG.getIntPtrConstant(i, dl));
5042 // Pre-SSE4.1 - merge byte pairs and insert with PINSRW.
5043 for (unsigned i = 0; i < 16; ++i) {
5044 bool ThisIsNonZero = (NonZeros & (1 << i)) != 0;
5045 if (ThisIsNonZero && First) {
5047 V = getZeroVector(MVT::v8i16, Subtarget, DAG, dl);
5049 V = DAG.getUNDEF(MVT::v8i16);
5054 SDValue ThisElt, LastElt;
5055 bool LastIsNonZero = (NonZeros & (1 << (i-1))) != 0;
5056 if (LastIsNonZero) {
5057 LastElt = DAG.getNode(ISD::ZERO_EXTEND, dl,
5058 MVT::i16, Op.getOperand(i-1));
5060 if (ThisIsNonZero) {
5061 ThisElt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, Op.getOperand(i));
5062 ThisElt = DAG.getNode(ISD::SHL, dl, MVT::i16,
5063 ThisElt, DAG.getConstant(8, dl, MVT::i8));
5065 ThisElt = DAG.getNode(ISD::OR, dl, MVT::i16, ThisElt, LastElt);
5069 if (ThisElt.getNode())
5070 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, V, ThisElt,
5071 DAG.getIntPtrConstant(i/2, dl));
5075 return DAG.getBitcast(MVT::v16i8, V);
5078 /// Custom lower build_vector of v8i16.
5079 static SDValue LowerBuildVectorv8i16(SDValue Op, unsigned NonZeros,
5080 unsigned NumNonZero, unsigned NumZero,
5082 const X86Subtarget* Subtarget,
5083 const TargetLowering &TLI) {
5090 for (unsigned i = 0; i < 8; ++i) {
5091 bool isNonZero = (NonZeros & (1 << i)) != 0;
5095 V = getZeroVector(MVT::v8i16, Subtarget, DAG, dl);
5097 V = DAG.getUNDEF(MVT::v8i16);
5100 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl,
5101 MVT::v8i16, V, Op.getOperand(i),
5102 DAG.getIntPtrConstant(i, dl));
5109 /// Custom lower build_vector of v4i32 or v4f32.
5110 static SDValue LowerBuildVectorv4x32(SDValue Op, SelectionDAG &DAG,
5111 const X86Subtarget *Subtarget,
5112 const TargetLowering &TLI) {
5113 // Find all zeroable elements.
5114 std::bitset<4> Zeroable;
5115 for (int i=0; i < 4; ++i) {
5116 SDValue Elt = Op->getOperand(i);
5117 Zeroable[i] = (Elt.getOpcode() == ISD::UNDEF || X86::isZeroNode(Elt));
5119 assert(Zeroable.size() - Zeroable.count() > 1 &&
5120 "We expect at least two non-zero elements!");
5122 // We only know how to deal with build_vector nodes where elements are either
5123 // zeroable or extract_vector_elt with constant index.
5124 SDValue FirstNonZero;
5125 unsigned FirstNonZeroIdx;
5126 for (unsigned i=0; i < 4; ++i) {
5129 SDValue Elt = Op->getOperand(i);
5130 if (Elt.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
5131 !isa<ConstantSDNode>(Elt.getOperand(1)))
5133 // Make sure that this node is extracting from a 128-bit vector.
5134 MVT VT = Elt.getOperand(0).getSimpleValueType();
5135 if (!VT.is128BitVector())
5137 if (!FirstNonZero.getNode()) {
5139 FirstNonZeroIdx = i;
5143 assert(FirstNonZero.getNode() && "Unexpected build vector of all zeros!");
5144 SDValue V1 = FirstNonZero.getOperand(0);
5145 MVT VT = V1.getSimpleValueType();
5147 // See if this build_vector can be lowered as a blend with zero.
5149 unsigned EltMaskIdx, EltIdx;
5151 for (EltIdx = 0; EltIdx < 4; ++EltIdx) {
5152 if (Zeroable[EltIdx]) {
5153 // The zero vector will be on the right hand side.
5154 Mask[EltIdx] = EltIdx+4;
5158 Elt = Op->getOperand(EltIdx);
5159 // By construction, Elt is a EXTRACT_VECTOR_ELT with constant index.
5160 EltMaskIdx = cast<ConstantSDNode>(Elt.getOperand(1))->getZExtValue();
5161 if (Elt.getOperand(0) != V1 || EltMaskIdx != EltIdx)
5163 Mask[EltIdx] = EltIdx;
5167 // Let the shuffle legalizer deal with blend operations.
5168 SDValue VZero = getZeroVector(VT, Subtarget, DAG, SDLoc(Op));
5169 if (V1.getSimpleValueType() != VT)
5170 V1 = DAG.getNode(ISD::BITCAST, SDLoc(V1), VT, V1);
5171 return DAG.getVectorShuffle(VT, SDLoc(V1), V1, VZero, &Mask[0]);
5174 // See if we can lower this build_vector to a INSERTPS.
5175 if (!Subtarget->hasSSE41())
5178 SDValue V2 = Elt.getOperand(0);
5179 if (Elt == FirstNonZero && EltIdx == FirstNonZeroIdx)
5182 bool CanFold = true;
5183 for (unsigned i = EltIdx + 1; i < 4 && CanFold; ++i) {
5187 SDValue Current = Op->getOperand(i);
5188 SDValue SrcVector = Current->getOperand(0);
5191 CanFold = SrcVector == V1 &&
5192 cast<ConstantSDNode>(Current.getOperand(1))->getZExtValue() == i;
5198 assert(V1.getNode() && "Expected at least two non-zero elements!");
5199 if (V1.getSimpleValueType() != MVT::v4f32)
5200 V1 = DAG.getNode(ISD::BITCAST, SDLoc(V1), MVT::v4f32, V1);
5201 if (V2.getSimpleValueType() != MVT::v4f32)
5202 V2 = DAG.getNode(ISD::BITCAST, SDLoc(V2), MVT::v4f32, V2);
5204 // Ok, we can emit an INSERTPS instruction.
5205 unsigned ZMask = Zeroable.to_ulong();
5207 unsigned InsertPSMask = EltMaskIdx << 6 | EltIdx << 4 | ZMask;
5208 assert((InsertPSMask & ~0xFFu) == 0 && "Invalid mask!");
5210 SDValue Result = DAG.getNode(X86ISD::INSERTPS, DL, MVT::v4f32, V1, V2,
5211 DAG.getIntPtrConstant(InsertPSMask, DL));
5212 return DAG.getBitcast(VT, Result);
5215 /// Return a vector logical shift node.
5216 static SDValue getVShift(bool isLeft, EVT VT, SDValue SrcOp,
5217 unsigned NumBits, SelectionDAG &DAG,
5218 const TargetLowering &TLI, SDLoc dl) {
5219 assert(VT.is128BitVector() && "Unknown type for VShift");
5220 MVT ShVT = MVT::v2i64;
5221 unsigned Opc = isLeft ? X86ISD::VSHLDQ : X86ISD::VSRLDQ;
5222 SrcOp = DAG.getBitcast(ShVT, SrcOp);
5223 MVT ScalarShiftTy = TLI.getScalarShiftAmountTy(DAG.getDataLayout(), VT);
5224 assert(NumBits % 8 == 0 && "Only support byte sized shifts");
5225 SDValue ShiftVal = DAG.getConstant(NumBits/8, dl, ScalarShiftTy);
5226 return DAG.getBitcast(VT, DAG.getNode(Opc, dl, ShVT, SrcOp, ShiftVal));
5230 LowerAsSplatVectorLoad(SDValue SrcOp, MVT VT, SDLoc dl, SelectionDAG &DAG) {
5232 // Check if the scalar load can be widened into a vector load. And if
5233 // the address is "base + cst" see if the cst can be "absorbed" into
5234 // the shuffle mask.
5235 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(SrcOp)) {
5236 SDValue Ptr = LD->getBasePtr();
5237 if (!ISD::isNormalLoad(LD) || LD->isVolatile())
5239 EVT PVT = LD->getValueType(0);
5240 if (PVT != MVT::i32 && PVT != MVT::f32)
5245 if (FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr)) {
5246 FI = FINode->getIndex();
5248 } else if (DAG.isBaseWithConstantOffset(Ptr) &&
5249 isa<FrameIndexSDNode>(Ptr.getOperand(0))) {
5250 FI = cast<FrameIndexSDNode>(Ptr.getOperand(0))->getIndex();
5251 Offset = Ptr.getConstantOperandVal(1);
5252 Ptr = Ptr.getOperand(0);
5257 // FIXME: 256-bit vector instructions don't require a strict alignment,
5258 // improve this code to support it better.
5259 unsigned RequiredAlign = VT.getSizeInBits()/8;
5260 SDValue Chain = LD->getChain();
5261 // Make sure the stack object alignment is at least 16 or 32.
5262 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
5263 if (DAG.InferPtrAlignment(Ptr) < RequiredAlign) {
5264 if (MFI->isFixedObjectIndex(FI)) {
5265 // Can't change the alignment. FIXME: It's possible to compute
5266 // the exact stack offset and reference FI + adjust offset instead.
5267 // If someone *really* cares about this. That's the way to implement it.
5270 MFI->setObjectAlignment(FI, RequiredAlign);
5274 // (Offset % 16 or 32) must be multiple of 4. Then address is then
5275 // Ptr + (Offset & ~15).
5278 if ((Offset % RequiredAlign) & 3)
5280 int64_t StartOffset = Offset & ~int64_t(RequiredAlign - 1);
5283 Ptr = DAG.getNode(ISD::ADD, DL, Ptr.getValueType(), Ptr,
5284 DAG.getConstant(StartOffset, DL, Ptr.getValueType()));
5287 int EltNo = (Offset - StartOffset) >> 2;
5288 unsigned NumElems = VT.getVectorNumElements();
5290 EVT NVT = EVT::getVectorVT(*DAG.getContext(), PVT, NumElems);
5291 SDValue V1 = DAG.getLoad(NVT, dl, Chain, Ptr,
5292 LD->getPointerInfo().getWithOffset(StartOffset),
5293 false, false, false, 0);
5295 SmallVector<int, 8> Mask(NumElems, EltNo);
5297 return DAG.getVectorShuffle(NVT, dl, V1, DAG.getUNDEF(NVT), &Mask[0]);
5303 /// Given the initializing elements 'Elts' of a vector of type 'VT', see if the
5304 /// elements can be replaced by a single large load which has the same value as
5305 /// a build_vector or insert_subvector whose loaded operands are 'Elts'.
5307 /// Example: <load i32 *a, load i32 *a+4, undef, undef> -> zextload a
5309 /// FIXME: we'd also like to handle the case where the last elements are zero
5310 /// rather than undef via VZEXT_LOAD, but we do not detect that case today.
5311 /// There's even a handy isZeroNode for that purpose.
5312 static SDValue EltsFromConsecutiveLoads(EVT VT, ArrayRef<SDValue> Elts,
5313 SDLoc &DL, SelectionDAG &DAG,
5314 bool isAfterLegalize) {
5315 unsigned NumElems = Elts.size();
5317 LoadSDNode *LDBase = nullptr;
5318 unsigned LastLoadedElt = -1U;
5320 // For each element in the initializer, see if we've found a load or an undef.
5321 // If we don't find an initial load element, or later load elements are
5322 // non-consecutive, bail out.
5323 for (unsigned i = 0; i < NumElems; ++i) {
5324 SDValue Elt = Elts[i];
5325 // Look through a bitcast.
5326 if (Elt.getNode() && Elt.getOpcode() == ISD::BITCAST)
5327 Elt = Elt.getOperand(0);
5328 if (!Elt.getNode() ||
5329 (Elt.getOpcode() != ISD::UNDEF && !ISD::isNON_EXTLoad(Elt.getNode())))
5332 if (Elt.getNode()->getOpcode() == ISD::UNDEF)
5334 LDBase = cast<LoadSDNode>(Elt.getNode());
5338 if (Elt.getOpcode() == ISD::UNDEF)
5341 LoadSDNode *LD = cast<LoadSDNode>(Elt);
5342 EVT LdVT = Elt.getValueType();
5343 // Each loaded element must be the correct fractional portion of the
5344 // requested vector load.
5345 if (LdVT.getSizeInBits() != VT.getSizeInBits() / NumElems)
5347 if (!DAG.isConsecutiveLoad(LD, LDBase, LdVT.getSizeInBits() / 8, i))
5352 // If we have found an entire vector of loads and undefs, then return a large
5353 // load of the entire vector width starting at the base pointer. If we found
5354 // consecutive loads for the low half, generate a vzext_load node.
5355 if (LastLoadedElt == NumElems - 1) {
5356 assert(LDBase && "Did not find base load for merging consecutive loads");
5357 EVT EltVT = LDBase->getValueType(0);
5358 // Ensure that the input vector size for the merged loads matches the
5359 // cumulative size of the input elements.
5360 if (VT.getSizeInBits() != EltVT.getSizeInBits() * NumElems)
5363 if (isAfterLegalize &&
5364 !DAG.getTargetLoweringInfo().isOperationLegal(ISD::LOAD, VT))
5367 SDValue NewLd = SDValue();
5369 NewLd = DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(),
5370 LDBase->getPointerInfo(), LDBase->isVolatile(),
5371 LDBase->isNonTemporal(), LDBase->isInvariant(),
5372 LDBase->getAlignment());
5374 if (LDBase->hasAnyUseOfValue(1)) {
5375 SDValue NewChain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
5377 SDValue(NewLd.getNode(), 1));
5378 DAG.ReplaceAllUsesOfValueWith(SDValue(LDBase, 1), NewChain);
5379 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(LDBase, 1),
5380 SDValue(NewLd.getNode(), 1));
5386 //TODO: The code below fires only for for loading the low v2i32 / v2f32
5387 //of a v4i32 / v4f32. It's probably worth generalizing.
5388 EVT EltVT = VT.getVectorElementType();
5389 if (NumElems == 4 && LastLoadedElt == 1 && (EltVT.getSizeInBits() == 32) &&
5390 DAG.getTargetLoweringInfo().isTypeLegal(MVT::v2i64)) {
5391 SDVTList Tys = DAG.getVTList(MVT::v2i64, MVT::Other);
5392 SDValue Ops[] = { LDBase->getChain(), LDBase->getBasePtr() };
5394 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, DL, Tys, Ops, MVT::i64,
5395 LDBase->getPointerInfo(),
5396 LDBase->getAlignment(),
5397 false/*isVolatile*/, true/*ReadMem*/,
5400 // Make sure the newly-created LOAD is in the same position as LDBase in
5401 // terms of dependency. We create a TokenFactor for LDBase and ResNode, and
5402 // update uses of LDBase's output chain to use the TokenFactor.
5403 if (LDBase->hasAnyUseOfValue(1)) {
5404 SDValue NewChain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
5405 SDValue(LDBase, 1), SDValue(ResNode.getNode(), 1));
5406 DAG.ReplaceAllUsesOfValueWith(SDValue(LDBase, 1), NewChain);
5407 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(LDBase, 1),
5408 SDValue(ResNode.getNode(), 1));
5411 return DAG.getBitcast(VT, ResNode);
5416 /// LowerVectorBroadcast - Attempt to use the vbroadcast instruction
5417 /// to generate a splat value for the following cases:
5418 /// 1. A splat BUILD_VECTOR which uses a single scalar load, or a constant.
5419 /// 2. A splat shuffle which uses a scalar_to_vector node which comes from
5420 /// a scalar load, or a constant.
5421 /// The VBROADCAST node is returned when a pattern is found,
5422 /// or SDValue() otherwise.
5423 static SDValue LowerVectorBroadcast(SDValue Op, const X86Subtarget* Subtarget,
5424 SelectionDAG &DAG) {
5425 // VBROADCAST requires AVX.
5426 // TODO: Splats could be generated for non-AVX CPUs using SSE
5427 // instructions, but there's less potential gain for only 128-bit vectors.
5428 if (!Subtarget->hasAVX())
5431 MVT VT = Op.getSimpleValueType();
5434 assert((VT.is128BitVector() || VT.is256BitVector() || VT.is512BitVector()) &&
5435 "Unsupported vector type for broadcast.");
5440 switch (Op.getOpcode()) {
5442 // Unknown pattern found.
5445 case ISD::BUILD_VECTOR: {
5446 auto *BVOp = cast<BuildVectorSDNode>(Op.getNode());
5447 BitVector UndefElements;
5448 SDValue Splat = BVOp->getSplatValue(&UndefElements);
5450 // We need a splat of a single value to use broadcast, and it doesn't
5451 // make any sense if the value is only in one element of the vector.
5452 if (!Splat || (VT.getVectorNumElements() - UndefElements.count()) <= 1)
5456 ConstSplatVal = (Ld.getOpcode() == ISD::Constant ||
5457 Ld.getOpcode() == ISD::ConstantFP);
5459 // Make sure that all of the users of a non-constant load are from the
5460 // BUILD_VECTOR node.
5461 if (!ConstSplatVal && !BVOp->isOnlyUserOf(Ld.getNode()))
5466 case ISD::VECTOR_SHUFFLE: {
5467 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
5469 // Shuffles must have a splat mask where the first element is
5471 if ((!SVOp->isSplat()) || SVOp->getMaskElt(0) != 0)
5474 SDValue Sc = Op.getOperand(0);
5475 if (Sc.getOpcode() != ISD::SCALAR_TO_VECTOR &&
5476 Sc.getOpcode() != ISD::BUILD_VECTOR) {
5478 if (!Subtarget->hasInt256())
5481 // Use the register form of the broadcast instruction available on AVX2.
5482 if (VT.getSizeInBits() >= 256)
5483 Sc = Extract128BitVector(Sc, 0, DAG, dl);
5484 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Sc);
5487 Ld = Sc.getOperand(0);
5488 ConstSplatVal = (Ld.getOpcode() == ISD::Constant ||
5489 Ld.getOpcode() == ISD::ConstantFP);
5491 // The scalar_to_vector node and the suspected
5492 // load node must have exactly one user.
5493 // Constants may have multiple users.
5495 // AVX-512 has register version of the broadcast
5496 bool hasRegVer = Subtarget->hasAVX512() && VT.is512BitVector() &&
5497 Ld.getValueType().getSizeInBits() >= 32;
5498 if (!ConstSplatVal && ((!Sc.hasOneUse() || !Ld.hasOneUse()) &&
5505 unsigned ScalarSize = Ld.getValueType().getSizeInBits();
5506 bool IsGE256 = (VT.getSizeInBits() >= 256);
5508 // When optimizing for size, generate up to 5 extra bytes for a broadcast
5509 // instruction to save 8 or more bytes of constant pool data.
5510 // TODO: If multiple splats are generated to load the same constant,
5511 // it may be detrimental to overall size. There needs to be a way to detect
5512 // that condition to know if this is truly a size win.
5513 bool OptForSize = DAG.getMachineFunction().getFunction()->optForSize();
5515 // Handle broadcasting a single constant scalar from the constant pool
5517 // On Sandybridge (no AVX2), it is still better to load a constant vector
5518 // from the constant pool and not to broadcast it from a scalar.
5519 // But override that restriction when optimizing for size.
5520 // TODO: Check if splatting is recommended for other AVX-capable CPUs.
5521 if (ConstSplatVal && (Subtarget->hasAVX2() || OptForSize)) {
5522 EVT CVT = Ld.getValueType();
5523 assert(!CVT.isVector() && "Must not broadcast a vector type");
5525 // Splat f32, i32, v4f64, v4i64 in all cases with AVX2.
5526 // For size optimization, also splat v2f64 and v2i64, and for size opt
5527 // with AVX2, also splat i8 and i16.
5528 // With pattern matching, the VBROADCAST node may become a VMOVDDUP.
5529 if (ScalarSize == 32 || (IsGE256 && ScalarSize == 64) ||
5530 (OptForSize && (ScalarSize == 64 || Subtarget->hasAVX2()))) {
5531 const Constant *C = nullptr;
5532 if (ConstantSDNode *CI = dyn_cast<ConstantSDNode>(Ld))
5533 C = CI->getConstantIntValue();
5534 else if (ConstantFPSDNode *CF = dyn_cast<ConstantFPSDNode>(Ld))
5535 C = CF->getConstantFPValue();
5537 assert(C && "Invalid constant type");
5539 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
5541 DAG.getConstantPool(C, TLI.getPointerTy(DAG.getDataLayout()));
5542 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
5544 CVT, dl, DAG.getEntryNode(), CP,
5545 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()), false,
5546 false, false, Alignment);
5548 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5552 bool IsLoad = ISD::isNormalLoad(Ld.getNode());
5554 // Handle AVX2 in-register broadcasts.
5555 if (!IsLoad && Subtarget->hasInt256() &&
5556 (ScalarSize == 32 || (IsGE256 && ScalarSize == 64)))
5557 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5559 // The scalar source must be a normal load.
5563 if (ScalarSize == 32 || (IsGE256 && ScalarSize == 64) ||
5564 (Subtarget->hasVLX() && ScalarSize == 64))
5565 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5567 // The integer check is needed for the 64-bit into 128-bit so it doesn't match
5568 // double since there is no vbroadcastsd xmm
5569 if (Subtarget->hasInt256() && Ld.getValueType().isInteger()) {
5570 if (ScalarSize == 8 || ScalarSize == 16 || ScalarSize == 64)
5571 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5574 // Unsupported broadcast.
5578 /// \brief For an EXTRACT_VECTOR_ELT with a constant index return the real
5579 /// underlying vector and index.
5581 /// Modifies \p ExtractedFromVec to the real vector and returns the real
5583 static int getUnderlyingExtractedFromVec(SDValue &ExtractedFromVec,
5585 int Idx = cast<ConstantSDNode>(ExtIdx)->getZExtValue();
5586 if (!isa<ShuffleVectorSDNode>(ExtractedFromVec))
5589 // For 256-bit vectors, LowerEXTRACT_VECTOR_ELT_SSE4 may have already
5591 // (extract_vector_elt (v8f32 %vreg1), Constant<6>)
5593 // (extract_vector_elt (vector_shuffle<2,u,u,u>
5594 // (extract_subvector (v8f32 %vreg0), Constant<4>),
5597 // In this case the vector is the extract_subvector expression and the index
5598 // is 2, as specified by the shuffle.
5599 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(ExtractedFromVec);
5600 SDValue ShuffleVec = SVOp->getOperand(0);
5601 MVT ShuffleVecVT = ShuffleVec.getSimpleValueType();
5602 assert(ShuffleVecVT.getVectorElementType() ==
5603 ExtractedFromVec.getSimpleValueType().getVectorElementType());
5605 int ShuffleIdx = SVOp->getMaskElt(Idx);
5606 if (isUndefOrInRange(ShuffleIdx, 0, ShuffleVecVT.getVectorNumElements())) {
5607 ExtractedFromVec = ShuffleVec;
5613 static SDValue buildFromShuffleMostly(SDValue Op, SelectionDAG &DAG) {
5614 MVT VT = Op.getSimpleValueType();
5616 // Skip if insert_vec_elt is not supported.
5617 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
5618 if (!TLI.isOperationLegalOrCustom(ISD::INSERT_VECTOR_ELT, VT))
5622 unsigned NumElems = Op.getNumOperands();
5626 SmallVector<unsigned, 4> InsertIndices;
5627 SmallVector<int, 8> Mask(NumElems, -1);
5629 for (unsigned i = 0; i != NumElems; ++i) {
5630 unsigned Opc = Op.getOperand(i).getOpcode();
5632 if (Opc == ISD::UNDEF)
5635 if (Opc != ISD::EXTRACT_VECTOR_ELT) {
5636 // Quit if more than 1 elements need inserting.
5637 if (InsertIndices.size() > 1)
5640 InsertIndices.push_back(i);
5644 SDValue ExtractedFromVec = Op.getOperand(i).getOperand(0);
5645 SDValue ExtIdx = Op.getOperand(i).getOperand(1);
5646 // Quit if non-constant index.
5647 if (!isa<ConstantSDNode>(ExtIdx))
5649 int Idx = getUnderlyingExtractedFromVec(ExtractedFromVec, ExtIdx);
5651 // Quit if extracted from vector of different type.
5652 if (ExtractedFromVec.getValueType() != VT)
5655 if (!VecIn1.getNode())
5656 VecIn1 = ExtractedFromVec;
5657 else if (VecIn1 != ExtractedFromVec) {
5658 if (!VecIn2.getNode())
5659 VecIn2 = ExtractedFromVec;
5660 else if (VecIn2 != ExtractedFromVec)
5661 // Quit if more than 2 vectors to shuffle
5665 if (ExtractedFromVec == VecIn1)
5667 else if (ExtractedFromVec == VecIn2)
5668 Mask[i] = Idx + NumElems;
5671 if (!VecIn1.getNode())
5674 VecIn2 = VecIn2.getNode() ? VecIn2 : DAG.getUNDEF(VT);
5675 SDValue NV = DAG.getVectorShuffle(VT, DL, VecIn1, VecIn2, &Mask[0]);
5676 for (unsigned i = 0, e = InsertIndices.size(); i != e; ++i) {
5677 unsigned Idx = InsertIndices[i];
5678 NV = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, VT, NV, Op.getOperand(Idx),
5679 DAG.getIntPtrConstant(Idx, DL));
5685 static SDValue ConvertI1VectorToInteger(SDValue Op, SelectionDAG &DAG) {
5686 assert(ISD::isBuildVectorOfConstantSDNodes(Op.getNode()) &&
5687 Op.getScalarValueSizeInBits() == 1 &&
5688 "Can not convert non-constant vector");
5689 uint64_t Immediate = 0;
5690 for (unsigned idx = 0, e = Op.getNumOperands(); idx < e; ++idx) {
5691 SDValue In = Op.getOperand(idx);
5692 if (In.getOpcode() != ISD::UNDEF)
5693 Immediate |= cast<ConstantSDNode>(In)->getZExtValue() << idx;
5697 MVT::getIntegerVT(std::max((int)Op.getValueType().getSizeInBits(), 8));
5698 return DAG.getConstant(Immediate, dl, VT);
5700 // Lower BUILD_VECTOR operation for v8i1 and v16i1 types.
5702 X86TargetLowering::LowerBUILD_VECTORvXi1(SDValue Op, SelectionDAG &DAG) const {
5704 MVT VT = Op.getSimpleValueType();
5705 assert((VT.getVectorElementType() == MVT::i1) &&
5706 "Unexpected type in LowerBUILD_VECTORvXi1!");
5709 if (ISD::isBuildVectorAllZeros(Op.getNode())) {
5710 SDValue Cst = DAG.getTargetConstant(0, dl, MVT::i1);
5711 SmallVector<SDValue, 16> Ops(VT.getVectorNumElements(), Cst);
5712 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
5715 if (ISD::isBuildVectorAllOnes(Op.getNode())) {
5716 SDValue Cst = DAG.getTargetConstant(1, dl, MVT::i1);
5717 SmallVector<SDValue, 16> Ops(VT.getVectorNumElements(), Cst);
5718 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
5721 if (ISD::isBuildVectorOfConstantSDNodes(Op.getNode())) {
5722 SDValue Imm = ConvertI1VectorToInteger(Op, DAG);
5723 if (Imm.getValueSizeInBits() == VT.getSizeInBits())
5724 return DAG.getBitcast(VT, Imm);
5725 SDValue ExtVec = DAG.getBitcast(MVT::v8i1, Imm);
5726 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, ExtVec,
5727 DAG.getIntPtrConstant(0, dl));
5730 // Vector has one or more non-const elements
5731 uint64_t Immediate = 0;
5732 SmallVector<unsigned, 16> NonConstIdx;
5733 bool IsSplat = true;
5734 bool HasConstElts = false;
5736 for (unsigned idx = 0, e = Op.getNumOperands(); idx < e; ++idx) {
5737 SDValue In = Op.getOperand(idx);
5738 if (In.getOpcode() == ISD::UNDEF)
5740 if (!isa<ConstantSDNode>(In))
5741 NonConstIdx.push_back(idx);
5743 Immediate |= cast<ConstantSDNode>(In)->getZExtValue() << idx;
5744 HasConstElts = true;
5748 else if (In != Op.getOperand(SplatIdx))
5752 // for splat use " (select i1 splat_elt, all-ones, all-zeroes)"
5754 return DAG.getNode(ISD::SELECT, dl, VT, Op.getOperand(SplatIdx),
5755 DAG.getConstant(1, dl, VT),
5756 DAG.getConstant(0, dl, VT));
5758 // insert elements one by one
5762 MVT ImmVT = MVT::getIntegerVT(std::max((int)VT.getSizeInBits(), 8));
5763 Imm = DAG.getConstant(Immediate, dl, ImmVT);
5765 else if (HasConstElts)
5766 Imm = DAG.getConstant(0, dl, VT);
5768 Imm = DAG.getUNDEF(VT);
5769 if (Imm.getValueSizeInBits() == VT.getSizeInBits())
5770 DstVec = DAG.getBitcast(VT, Imm);
5772 SDValue ExtVec = DAG.getBitcast(MVT::v8i1, Imm);
5773 DstVec = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, ExtVec,
5774 DAG.getIntPtrConstant(0, dl));
5777 for (unsigned i = 0; i < NonConstIdx.size(); ++i) {
5778 unsigned InsertIdx = NonConstIdx[i];
5779 DstVec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, DstVec,
5780 Op.getOperand(InsertIdx),
5781 DAG.getIntPtrConstant(InsertIdx, dl));
5786 /// \brief Return true if \p N implements a horizontal binop and return the
5787 /// operands for the horizontal binop into V0 and V1.
5789 /// This is a helper function of LowerToHorizontalOp().
5790 /// This function checks that the build_vector \p N in input implements a
5791 /// horizontal operation. Parameter \p Opcode defines the kind of horizontal
5792 /// operation to match.
5793 /// For example, if \p Opcode is equal to ISD::ADD, then this function
5794 /// checks if \p N implements a horizontal arithmetic add; if instead \p Opcode
5795 /// is equal to ISD::SUB, then this function checks if this is a horizontal
5798 /// This function only analyzes elements of \p N whose indices are
5799 /// in range [BaseIdx, LastIdx).
5800 static bool isHorizontalBinOp(const BuildVectorSDNode *N, unsigned Opcode,
5802 unsigned BaseIdx, unsigned LastIdx,
5803 SDValue &V0, SDValue &V1) {
5804 EVT VT = N->getValueType(0);
5806 assert(BaseIdx * 2 <= LastIdx && "Invalid Indices in input!");
5807 assert(VT.isVector() && VT.getVectorNumElements() >= LastIdx &&
5808 "Invalid Vector in input!");
5810 bool IsCommutable = (Opcode == ISD::ADD || Opcode == ISD::FADD);
5811 bool CanFold = true;
5812 unsigned ExpectedVExtractIdx = BaseIdx;
5813 unsigned NumElts = LastIdx - BaseIdx;
5814 V0 = DAG.getUNDEF(VT);
5815 V1 = DAG.getUNDEF(VT);
5817 // Check if N implements a horizontal binop.
5818 for (unsigned i = 0, e = NumElts; i != e && CanFold; ++i) {
5819 SDValue Op = N->getOperand(i + BaseIdx);
5822 if (Op->getOpcode() == ISD::UNDEF) {
5823 // Update the expected vector extract index.
5824 if (i * 2 == NumElts)
5825 ExpectedVExtractIdx = BaseIdx;
5826 ExpectedVExtractIdx += 2;
5830 CanFold = Op->getOpcode() == Opcode && Op->hasOneUse();
5835 SDValue Op0 = Op.getOperand(0);
5836 SDValue Op1 = Op.getOperand(1);
5838 // Try to match the following pattern:
5839 // (BINOP (extract_vector_elt A, I), (extract_vector_elt A, I+1))
5840 CanFold = (Op0.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
5841 Op1.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
5842 Op0.getOperand(0) == Op1.getOperand(0) &&
5843 isa<ConstantSDNode>(Op0.getOperand(1)) &&
5844 isa<ConstantSDNode>(Op1.getOperand(1)));
5848 unsigned I0 = cast<ConstantSDNode>(Op0.getOperand(1))->getZExtValue();
5849 unsigned I1 = cast<ConstantSDNode>(Op1.getOperand(1))->getZExtValue();
5851 if (i * 2 < NumElts) {
5852 if (V0.getOpcode() == ISD::UNDEF) {
5853 V0 = Op0.getOperand(0);
5854 if (V0.getValueType() != VT)
5858 if (V1.getOpcode() == ISD::UNDEF) {
5859 V1 = Op0.getOperand(0);
5860 if (V1.getValueType() != VT)
5863 if (i * 2 == NumElts)
5864 ExpectedVExtractIdx = BaseIdx;
5867 SDValue Expected = (i * 2 < NumElts) ? V0 : V1;
5868 if (I0 == ExpectedVExtractIdx)
5869 CanFold = I1 == I0 + 1 && Op0.getOperand(0) == Expected;
5870 else if (IsCommutable && I1 == ExpectedVExtractIdx) {
5871 // Try to match the following dag sequence:
5872 // (BINOP (extract_vector_elt A, I+1), (extract_vector_elt A, I))
5873 CanFold = I0 == I1 + 1 && Op1.getOperand(0) == Expected;
5877 ExpectedVExtractIdx += 2;
5883 /// \brief Emit a sequence of two 128-bit horizontal add/sub followed by
5884 /// a concat_vector.
5886 /// This is a helper function of LowerToHorizontalOp().
5887 /// This function expects two 256-bit vectors called V0 and V1.
5888 /// At first, each vector is split into two separate 128-bit vectors.
5889 /// Then, the resulting 128-bit vectors are used to implement two
5890 /// horizontal binary operations.
5892 /// The kind of horizontal binary operation is defined by \p X86Opcode.
5894 /// \p Mode specifies how the 128-bit parts of V0 and V1 are passed in input to
5895 /// the two new horizontal binop.
5896 /// When Mode is set, the first horizontal binop dag node would take as input
5897 /// the lower 128-bit of V0 and the upper 128-bit of V0. The second
5898 /// horizontal binop dag node would take as input the lower 128-bit of V1
5899 /// and the upper 128-bit of V1.
5901 /// HADD V0_LO, V0_HI
5902 /// HADD V1_LO, V1_HI
5904 /// Otherwise, the first horizontal binop dag node takes as input the lower
5905 /// 128-bit of V0 and the lower 128-bit of V1, and the second horizontal binop
5906 /// dag node takes the upper 128-bit of V0 and the upper 128-bit of V1.
5908 /// HADD V0_LO, V1_LO
5909 /// HADD V0_HI, V1_HI
5911 /// If \p isUndefLO is set, then the algorithm propagates UNDEF to the lower
5912 /// 128-bits of the result. If \p isUndefHI is set, then UNDEF is propagated to
5913 /// the upper 128-bits of the result.
5914 static SDValue ExpandHorizontalBinOp(const SDValue &V0, const SDValue &V1,
5915 SDLoc DL, SelectionDAG &DAG,
5916 unsigned X86Opcode, bool Mode,
5917 bool isUndefLO, bool isUndefHI) {
5918 EVT VT = V0.getValueType();
5919 assert(VT.is256BitVector() && VT == V1.getValueType() &&
5920 "Invalid nodes in input!");
5922 unsigned NumElts = VT.getVectorNumElements();
5923 SDValue V0_LO = Extract128BitVector(V0, 0, DAG, DL);
5924 SDValue V0_HI = Extract128BitVector(V0, NumElts/2, DAG, DL);
5925 SDValue V1_LO = Extract128BitVector(V1, 0, DAG, DL);
5926 SDValue V1_HI = Extract128BitVector(V1, NumElts/2, DAG, DL);
5927 EVT NewVT = V0_LO.getValueType();
5929 SDValue LO = DAG.getUNDEF(NewVT);
5930 SDValue HI = DAG.getUNDEF(NewVT);
5933 // Don't emit a horizontal binop if the result is expected to be UNDEF.
5934 if (!isUndefLO && V0->getOpcode() != ISD::UNDEF)
5935 LO = DAG.getNode(X86Opcode, DL, NewVT, V0_LO, V0_HI);
5936 if (!isUndefHI && V1->getOpcode() != ISD::UNDEF)
5937 HI = DAG.getNode(X86Opcode, DL, NewVT, V1_LO, V1_HI);
5939 // Don't emit a horizontal binop if the result is expected to be UNDEF.
5940 if (!isUndefLO && (V0_LO->getOpcode() != ISD::UNDEF ||
5941 V1_LO->getOpcode() != ISD::UNDEF))
5942 LO = DAG.getNode(X86Opcode, DL, NewVT, V0_LO, V1_LO);
5944 if (!isUndefHI && (V0_HI->getOpcode() != ISD::UNDEF ||
5945 V1_HI->getOpcode() != ISD::UNDEF))
5946 HI = DAG.getNode(X86Opcode, DL, NewVT, V0_HI, V1_HI);
5949 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, LO, HI);
5952 /// Try to fold a build_vector that performs an 'addsub' to an X86ISD::ADDSUB
5954 static SDValue LowerToAddSub(const BuildVectorSDNode *BV,
5955 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
5956 MVT VT = BV->getSimpleValueType(0);
5957 if ((!Subtarget->hasSSE3() || (VT != MVT::v4f32 && VT != MVT::v2f64)) &&
5958 (!Subtarget->hasAVX() || (VT != MVT::v8f32 && VT != MVT::v4f64)))
5962 unsigned NumElts = VT.getVectorNumElements();
5963 SDValue InVec0 = DAG.getUNDEF(VT);
5964 SDValue InVec1 = DAG.getUNDEF(VT);
5966 assert((VT == MVT::v8f32 || VT == MVT::v4f64 || VT == MVT::v4f32 ||
5967 VT == MVT::v2f64) && "build_vector with an invalid type found!");
5969 // Odd-numbered elements in the input build vector are obtained from
5970 // adding two integer/float elements.
5971 // Even-numbered elements in the input build vector are obtained from
5972 // subtracting two integer/float elements.
5973 unsigned ExpectedOpcode = ISD::FSUB;
5974 unsigned NextExpectedOpcode = ISD::FADD;
5975 bool AddFound = false;
5976 bool SubFound = false;
5978 for (unsigned i = 0, e = NumElts; i != e; ++i) {
5979 SDValue Op = BV->getOperand(i);
5981 // Skip 'undef' values.
5982 unsigned Opcode = Op.getOpcode();
5983 if (Opcode == ISD::UNDEF) {
5984 std::swap(ExpectedOpcode, NextExpectedOpcode);
5988 // Early exit if we found an unexpected opcode.
5989 if (Opcode != ExpectedOpcode)
5992 SDValue Op0 = Op.getOperand(0);
5993 SDValue Op1 = Op.getOperand(1);
5995 // Try to match the following pattern:
5996 // (BINOP (extract_vector_elt A, i), (extract_vector_elt B, i))
5997 // Early exit if we cannot match that sequence.
5998 if (Op0.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
5999 Op1.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
6000 !isa<ConstantSDNode>(Op0.getOperand(1)) ||
6001 !isa<ConstantSDNode>(Op1.getOperand(1)) ||
6002 Op0.getOperand(1) != Op1.getOperand(1))
6005 unsigned I0 = cast<ConstantSDNode>(Op0.getOperand(1))->getZExtValue();
6009 // We found a valid add/sub node. Update the information accordingly.
6015 // Update InVec0 and InVec1.
6016 if (InVec0.getOpcode() == ISD::UNDEF) {
6017 InVec0 = Op0.getOperand(0);
6018 if (InVec0.getSimpleValueType() != VT)
6021 if (InVec1.getOpcode() == ISD::UNDEF) {
6022 InVec1 = Op1.getOperand(0);
6023 if (InVec1.getSimpleValueType() != VT)
6027 // Make sure that operands in input to each add/sub node always
6028 // come from a same pair of vectors.
6029 if (InVec0 != Op0.getOperand(0)) {
6030 if (ExpectedOpcode == ISD::FSUB)
6033 // FADD is commutable. Try to commute the operands
6034 // and then test again.
6035 std::swap(Op0, Op1);
6036 if (InVec0 != Op0.getOperand(0))
6040 if (InVec1 != Op1.getOperand(0))
6043 // Update the pair of expected opcodes.
6044 std::swap(ExpectedOpcode, NextExpectedOpcode);
6047 // Don't try to fold this build_vector into an ADDSUB if the inputs are undef.
6048 if (AddFound && SubFound && InVec0.getOpcode() != ISD::UNDEF &&
6049 InVec1.getOpcode() != ISD::UNDEF)
6050 return DAG.getNode(X86ISD::ADDSUB, DL, VT, InVec0, InVec1);
6055 /// Lower BUILD_VECTOR to a horizontal add/sub operation if possible.
6056 static SDValue LowerToHorizontalOp(const BuildVectorSDNode *BV,
6057 const X86Subtarget *Subtarget,
6058 SelectionDAG &DAG) {
6059 MVT VT = BV->getSimpleValueType(0);
6060 unsigned NumElts = VT.getVectorNumElements();
6061 unsigned NumUndefsLO = 0;
6062 unsigned NumUndefsHI = 0;
6063 unsigned Half = NumElts/2;
6065 // Count the number of UNDEF operands in the build_vector in input.
6066 for (unsigned i = 0, e = Half; i != e; ++i)
6067 if (BV->getOperand(i)->getOpcode() == ISD::UNDEF)
6070 for (unsigned i = Half, e = NumElts; i != e; ++i)
6071 if (BV->getOperand(i)->getOpcode() == ISD::UNDEF)
6074 // Early exit if this is either a build_vector of all UNDEFs or all the
6075 // operands but one are UNDEF.
6076 if (NumUndefsLO + NumUndefsHI + 1 >= NumElts)
6080 SDValue InVec0, InVec1;
6081 if ((VT == MVT::v4f32 || VT == MVT::v2f64) && Subtarget->hasSSE3()) {
6082 // Try to match an SSE3 float HADD/HSUB.
6083 if (isHorizontalBinOp(BV, ISD::FADD, DAG, 0, NumElts, InVec0, InVec1))
6084 return DAG.getNode(X86ISD::FHADD, DL, VT, InVec0, InVec1);
6086 if (isHorizontalBinOp(BV, ISD::FSUB, DAG, 0, NumElts, InVec0, InVec1))
6087 return DAG.getNode(X86ISD::FHSUB, DL, VT, InVec0, InVec1);
6088 } else if ((VT == MVT::v4i32 || VT == MVT::v8i16) && Subtarget->hasSSSE3()) {
6089 // Try to match an SSSE3 integer HADD/HSUB.
6090 if (isHorizontalBinOp(BV, ISD::ADD, DAG, 0, NumElts, InVec0, InVec1))
6091 return DAG.getNode(X86ISD::HADD, DL, VT, InVec0, InVec1);
6093 if (isHorizontalBinOp(BV, ISD::SUB, DAG, 0, NumElts, InVec0, InVec1))
6094 return DAG.getNode(X86ISD::HSUB, DL, VT, InVec0, InVec1);
6097 if (!Subtarget->hasAVX())
6100 if ((VT == MVT::v8f32 || VT == MVT::v4f64)) {
6101 // Try to match an AVX horizontal add/sub of packed single/double
6102 // precision floating point values from 256-bit vectors.
6103 SDValue InVec2, InVec3;
6104 if (isHorizontalBinOp(BV, ISD::FADD, DAG, 0, Half, InVec0, InVec1) &&
6105 isHorizontalBinOp(BV, ISD::FADD, DAG, Half, NumElts, InVec2, InVec3) &&
6106 ((InVec0.getOpcode() == ISD::UNDEF ||
6107 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
6108 ((InVec1.getOpcode() == ISD::UNDEF ||
6109 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
6110 return DAG.getNode(X86ISD::FHADD, DL, VT, InVec0, InVec1);
6112 if (isHorizontalBinOp(BV, ISD::FSUB, DAG, 0, Half, InVec0, InVec1) &&
6113 isHorizontalBinOp(BV, ISD::FSUB, DAG, Half, NumElts, InVec2, InVec3) &&
6114 ((InVec0.getOpcode() == ISD::UNDEF ||
6115 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
6116 ((InVec1.getOpcode() == ISD::UNDEF ||
6117 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
6118 return DAG.getNode(X86ISD::FHSUB, DL, VT, InVec0, InVec1);
6119 } else if (VT == MVT::v8i32 || VT == MVT::v16i16) {
6120 // Try to match an AVX2 horizontal add/sub of signed integers.
6121 SDValue InVec2, InVec3;
6123 bool CanFold = true;
6125 if (isHorizontalBinOp(BV, ISD::ADD, DAG, 0, Half, InVec0, InVec1) &&
6126 isHorizontalBinOp(BV, ISD::ADD, DAG, Half, NumElts, InVec2, InVec3) &&
6127 ((InVec0.getOpcode() == ISD::UNDEF ||
6128 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
6129 ((InVec1.getOpcode() == ISD::UNDEF ||
6130 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
6131 X86Opcode = X86ISD::HADD;
6132 else if (isHorizontalBinOp(BV, ISD::SUB, DAG, 0, Half, InVec0, InVec1) &&
6133 isHorizontalBinOp(BV, ISD::SUB, DAG, Half, NumElts, InVec2, InVec3) &&
6134 ((InVec0.getOpcode() == ISD::UNDEF ||
6135 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
6136 ((InVec1.getOpcode() == ISD::UNDEF ||
6137 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
6138 X86Opcode = X86ISD::HSUB;
6143 // Fold this build_vector into a single horizontal add/sub.
6144 // Do this only if the target has AVX2.
6145 if (Subtarget->hasAVX2())
6146 return DAG.getNode(X86Opcode, DL, VT, InVec0, InVec1);
6148 // Do not try to expand this build_vector into a pair of horizontal
6149 // add/sub if we can emit a pair of scalar add/sub.
6150 if (NumUndefsLO + 1 == Half || NumUndefsHI + 1 == Half)
6153 // Convert this build_vector into a pair of horizontal binop followed by
6155 bool isUndefLO = NumUndefsLO == Half;
6156 bool isUndefHI = NumUndefsHI == Half;
6157 return ExpandHorizontalBinOp(InVec0, InVec1, DL, DAG, X86Opcode, false,
6158 isUndefLO, isUndefHI);
6162 if ((VT == MVT::v8f32 || VT == MVT::v4f64 || VT == MVT::v8i32 ||
6163 VT == MVT::v16i16) && Subtarget->hasAVX()) {
6165 if (isHorizontalBinOp(BV, ISD::ADD, DAG, 0, NumElts, InVec0, InVec1))
6166 X86Opcode = X86ISD::HADD;
6167 else if (isHorizontalBinOp(BV, ISD::SUB, DAG, 0, NumElts, InVec0, InVec1))
6168 X86Opcode = X86ISD::HSUB;
6169 else if (isHorizontalBinOp(BV, ISD::FADD, DAG, 0, NumElts, InVec0, InVec1))
6170 X86Opcode = X86ISD::FHADD;
6171 else if (isHorizontalBinOp(BV, ISD::FSUB, DAG, 0, NumElts, InVec0, InVec1))
6172 X86Opcode = X86ISD::FHSUB;
6176 // Don't try to expand this build_vector into a pair of horizontal add/sub
6177 // if we can simply emit a pair of scalar add/sub.
6178 if (NumUndefsLO + 1 == Half || NumUndefsHI + 1 == Half)
6181 // Convert this build_vector into two horizontal add/sub followed by
6183 bool isUndefLO = NumUndefsLO == Half;
6184 bool isUndefHI = NumUndefsHI == Half;
6185 return ExpandHorizontalBinOp(InVec0, InVec1, DL, DAG, X86Opcode, true,
6186 isUndefLO, isUndefHI);
6193 X86TargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const {
6196 MVT VT = Op.getSimpleValueType();
6197 MVT ExtVT = VT.getVectorElementType();
6198 unsigned NumElems = Op.getNumOperands();
6200 // Generate vectors for predicate vectors.
6201 if (VT.getVectorElementType() == MVT::i1 && Subtarget->hasAVX512())
6202 return LowerBUILD_VECTORvXi1(Op, DAG);
6204 // Vectors containing all zeros can be matched by pxor and xorps later
6205 if (ISD::isBuildVectorAllZeros(Op.getNode())) {
6206 // Canonicalize this to <4 x i32> to 1) ensure the zero vectors are CSE'd
6207 // and 2) ensure that i64 scalars are eliminated on x86-32 hosts.
6208 if (VT == MVT::v4i32 || VT == MVT::v8i32 || VT == MVT::v16i32)
6211 return getZeroVector(VT, Subtarget, DAG, dl);
6214 // Vectors containing all ones can be matched by pcmpeqd on 128-bit width
6215 // vectors or broken into v4i32 operations on 256-bit vectors. AVX2 can use
6216 // vpcmpeqd on 256-bit vectors.
6217 if (Subtarget->hasSSE2() && ISD::isBuildVectorAllOnes(Op.getNode())) {
6218 if (VT == MVT::v4i32 || (VT == MVT::v8i32 && Subtarget->hasInt256()))
6221 if (!VT.is512BitVector())
6222 return getOnesVector(VT, Subtarget, DAG, dl);
6225 BuildVectorSDNode *BV = cast<BuildVectorSDNode>(Op.getNode());
6226 if (SDValue AddSub = LowerToAddSub(BV, Subtarget, DAG))
6228 if (SDValue HorizontalOp = LowerToHorizontalOp(BV, Subtarget, DAG))
6229 return HorizontalOp;
6230 if (SDValue Broadcast = LowerVectorBroadcast(Op, Subtarget, DAG))
6233 unsigned EVTBits = ExtVT.getSizeInBits();
6235 unsigned NumZero = 0;
6236 unsigned NumNonZero = 0;
6237 uint64_t NonZeros = 0;
6238 bool IsAllConstants = true;
6239 SmallSet<SDValue, 8> Values;
6240 for (unsigned i = 0; i < NumElems; ++i) {
6241 SDValue Elt = Op.getOperand(i);
6242 if (Elt.getOpcode() == ISD::UNDEF)
6245 if (Elt.getOpcode() != ISD::Constant &&
6246 Elt.getOpcode() != ISD::ConstantFP)
6247 IsAllConstants = false;
6248 if (X86::isZeroNode(Elt))
6251 assert(i < sizeof(NonZeros) * 8); // Make sure the shift is within range.
6252 NonZeros |= ((uint64_t)1 << i);
6257 // All undef vector. Return an UNDEF. All zero vectors were handled above.
6258 if (NumNonZero == 0)
6259 return DAG.getUNDEF(VT);
6261 // Special case for single non-zero, non-undef, element.
6262 if (NumNonZero == 1) {
6263 unsigned Idx = countTrailingZeros(NonZeros);
6264 SDValue Item = Op.getOperand(Idx);
6266 // If this is an insertion of an i64 value on x86-32, and if the top bits of
6267 // the value are obviously zero, truncate the value to i32 and do the
6268 // insertion that way. Only do this if the value is non-constant or if the
6269 // value is a constant being inserted into element 0. It is cheaper to do
6270 // a constant pool load than it is to do a movd + shuffle.
6271 if (ExtVT == MVT::i64 && !Subtarget->is64Bit() &&
6272 (!IsAllConstants || Idx == 0)) {
6273 if (DAG.MaskedValueIsZero(Item, APInt::getBitsSet(64, 32, 64))) {
6275 assert(VT == MVT::v2i64 && "Expected an SSE value type!");
6276 MVT VecVT = MVT::v4i32;
6278 // Truncate the value (which may itself be a constant) to i32, and
6279 // convert it to a vector with movd (S2V+shuffle to zero extend).
6280 Item = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Item);
6281 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Item);
6282 return DAG.getBitcast(VT, getShuffleVectorZeroOrUndef(
6283 Item, Idx * 2, true, Subtarget, DAG));
6287 // If we have a constant or non-constant insertion into the low element of
6288 // a vector, we can do this with SCALAR_TO_VECTOR + shuffle of zero into
6289 // the rest of the elements. This will be matched as movd/movq/movss/movsd
6290 // depending on what the source datatype is.
6293 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
6295 if (ExtVT == MVT::i32 || ExtVT == MVT::f32 || ExtVT == MVT::f64 ||
6296 (ExtVT == MVT::i64 && Subtarget->is64Bit())) {
6297 if (VT.is512BitVector()) {
6298 SDValue ZeroVec = getZeroVector(VT, Subtarget, DAG, dl);
6299 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, ZeroVec,
6300 Item, DAG.getIntPtrConstant(0, dl));
6302 assert((VT.is128BitVector() || VT.is256BitVector()) &&
6303 "Expected an SSE value type!");
6304 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
6305 // Turn it into a MOVL (i.e. movss, movsd, or movd) to a zero vector.
6306 return getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
6309 // We can't directly insert an i8 or i16 into a vector, so zero extend
6311 if (ExtVT == MVT::i16 || ExtVT == MVT::i8) {
6312 Item = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Item);
6313 if (VT.is256BitVector()) {
6314 if (Subtarget->hasAVX()) {
6315 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v8i32, Item);
6316 Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
6318 // Without AVX, we need to extend to a 128-bit vector and then
6319 // insert into the 256-bit vector.
6320 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, Item);
6321 SDValue ZeroVec = getZeroVector(MVT::v8i32, Subtarget, DAG, dl);
6322 Item = Insert128BitVector(ZeroVec, Item, 0, DAG, dl);
6325 assert(VT.is128BitVector() && "Expected an SSE value type!");
6326 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, Item);
6327 Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
6329 return DAG.getBitcast(VT, Item);
6333 // Is it a vector logical left shift?
6334 if (NumElems == 2 && Idx == 1 &&
6335 X86::isZeroNode(Op.getOperand(0)) &&
6336 !X86::isZeroNode(Op.getOperand(1))) {
6337 unsigned NumBits = VT.getSizeInBits();
6338 return getVShift(true, VT,
6339 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
6340 VT, Op.getOperand(1)),
6341 NumBits/2, DAG, *this, dl);
6344 if (IsAllConstants) // Otherwise, it's better to do a constpool load.
6347 // Otherwise, if this is a vector with i32 or f32 elements, and the element
6348 // is a non-constant being inserted into an element other than the low one,
6349 // we can't use a constant pool load. Instead, use SCALAR_TO_VECTOR (aka
6350 // movd/movss) to move this into the low element, then shuffle it into
6352 if (EVTBits == 32) {
6353 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
6354 return getShuffleVectorZeroOrUndef(Item, Idx, NumZero > 0, Subtarget, DAG);
6358 // Splat is obviously ok. Let legalizer expand it to a shuffle.
6359 if (Values.size() == 1) {
6360 if (EVTBits == 32) {
6361 // Instead of a shuffle like this:
6362 // shuffle (scalar_to_vector (load (ptr + 4))), undef, <0, 0, 0, 0>
6363 // Check if it's possible to issue this instead.
6364 // shuffle (vload ptr)), undef, <1, 1, 1, 1>
6365 unsigned Idx = countTrailingZeros(NonZeros);
6366 SDValue Item = Op.getOperand(Idx);
6367 if (Op.getNode()->isOnlyUserOf(Item.getNode()))
6368 return LowerAsSplatVectorLoad(Item, VT, dl, DAG);
6373 // A vector full of immediates; various special cases are already
6374 // handled, so this is best done with a single constant-pool load.
6378 // For AVX-length vectors, see if we can use a vector load to get all of the
6379 // elements, otherwise build the individual 128-bit pieces and use
6380 // shuffles to put them in place.
6381 if (VT.is256BitVector() || VT.is512BitVector()) {
6382 SmallVector<SDValue, 64> V(Op->op_begin(), Op->op_begin() + NumElems);
6384 // Check for a build vector of consecutive loads.
6385 if (SDValue LD = EltsFromConsecutiveLoads(VT, V, dl, DAG, false))
6388 EVT HVT = EVT::getVectorVT(*DAG.getContext(), ExtVT, NumElems/2);
6390 // Build both the lower and upper subvector.
6391 SDValue Lower = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT,
6392 makeArrayRef(&V[0], NumElems/2));
6393 SDValue Upper = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT,
6394 makeArrayRef(&V[NumElems / 2], NumElems/2));
6396 // Recreate the wider vector with the lower and upper part.
6397 if (VT.is256BitVector())
6398 return Concat128BitVectors(Lower, Upper, VT, NumElems, DAG, dl);
6399 return Concat256BitVectors(Lower, Upper, VT, NumElems, DAG, dl);
6402 // Let legalizer expand 2-wide build_vectors.
6403 if (EVTBits == 64) {
6404 if (NumNonZero == 1) {
6405 // One half is zero or undef.
6406 unsigned Idx = countTrailingZeros(NonZeros);
6407 SDValue V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT,
6408 Op.getOperand(Idx));
6409 return getShuffleVectorZeroOrUndef(V2, Idx, true, Subtarget, DAG);
6414 // If element VT is < 32 bits, convert it to inserts into a zero vector.
6415 if (EVTBits == 8 && NumElems == 16)
6416 if (SDValue V = LowerBuildVectorv16i8(Op, NonZeros, NumNonZero, NumZero,
6417 DAG, Subtarget, *this))
6420 if (EVTBits == 16 && NumElems == 8)
6421 if (SDValue V = LowerBuildVectorv8i16(Op, NonZeros, NumNonZero, NumZero,
6422 DAG, Subtarget, *this))
6425 // If element VT is == 32 bits and has 4 elems, try to generate an INSERTPS
6426 if (EVTBits == 32 && NumElems == 4)
6427 if (SDValue V = LowerBuildVectorv4x32(Op, DAG, Subtarget, *this))
6430 // If element VT is == 32 bits, turn it into a number of shuffles.
6431 SmallVector<SDValue, 8> V(NumElems);
6432 if (NumElems == 4 && NumZero > 0) {
6433 for (unsigned i = 0; i < 4; ++i) {
6434 bool isZero = !(NonZeros & (1 << i));
6436 V[i] = getZeroVector(VT, Subtarget, DAG, dl);
6438 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
6441 for (unsigned i = 0; i < 2; ++i) {
6442 switch ((NonZeros & (0x3 << i*2)) >> (i*2)) {
6445 V[i] = V[i*2]; // Must be a zero vector.
6448 V[i] = getMOVL(DAG, dl, VT, V[i*2+1], V[i*2]);
6451 V[i] = getMOVL(DAG, dl, VT, V[i*2], V[i*2+1]);
6454 V[i] = getUnpackl(DAG, dl, VT, V[i*2], V[i*2+1]);
6459 bool Reverse1 = (NonZeros & 0x3) == 2;
6460 bool Reverse2 = ((NonZeros & (0x3 << 2)) >> 2) == 2;
6464 static_cast<int>(Reverse2 ? NumElems+1 : NumElems),
6465 static_cast<int>(Reverse2 ? NumElems : NumElems+1)
6467 return DAG.getVectorShuffle(VT, dl, V[0], V[1], &MaskVec[0]);
6470 if (Values.size() > 1 && VT.is128BitVector()) {
6471 // Check for a build vector of consecutive loads.
6472 for (unsigned i = 0; i < NumElems; ++i)
6473 V[i] = Op.getOperand(i);
6475 // Check for elements which are consecutive loads.
6476 if (SDValue LD = EltsFromConsecutiveLoads(VT, V, dl, DAG, false))
6479 // Check for a build vector from mostly shuffle plus few inserting.
6480 if (SDValue Sh = buildFromShuffleMostly(Op, DAG))
6483 // For SSE 4.1, use insertps to put the high elements into the low element.
6484 if (Subtarget->hasSSE41()) {
6486 if (Op.getOperand(0).getOpcode() != ISD::UNDEF)
6487 Result = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(0));
6489 Result = DAG.getUNDEF(VT);
6491 for (unsigned i = 1; i < NumElems; ++i) {
6492 if (Op.getOperand(i).getOpcode() == ISD::UNDEF) continue;
6493 Result = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Result,
6494 Op.getOperand(i), DAG.getIntPtrConstant(i, dl));
6499 // Otherwise, expand into a number of unpckl*, start by extending each of
6500 // our (non-undef) elements to the full vector width with the element in the
6501 // bottom slot of the vector (which generates no code for SSE).
6502 for (unsigned i = 0; i < NumElems; ++i) {
6503 if (Op.getOperand(i).getOpcode() != ISD::UNDEF)
6504 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
6506 V[i] = DAG.getUNDEF(VT);
6509 // Next, we iteratively mix elements, e.g. for v4f32:
6510 // Step 1: unpcklps 0, 2 ==> X: <?, ?, 2, 0>
6511 // : unpcklps 1, 3 ==> Y: <?, ?, 3, 1>
6512 // Step 2: unpcklps X, Y ==> <3, 2, 1, 0>
6513 unsigned EltStride = NumElems >> 1;
6514 while (EltStride != 0) {
6515 for (unsigned i = 0; i < EltStride; ++i) {
6516 // If V[i+EltStride] is undef and this is the first round of mixing,
6517 // then it is safe to just drop this shuffle: V[i] is already in the
6518 // right place, the one element (since it's the first round) being
6519 // inserted as undef can be dropped. This isn't safe for successive
6520 // rounds because they will permute elements within both vectors.
6521 if (V[i+EltStride].getOpcode() == ISD::UNDEF &&
6522 EltStride == NumElems/2)
6525 V[i] = getUnpackl(DAG, dl, VT, V[i], V[i + EltStride]);
6534 // 256-bit AVX can use the vinsertf128 instruction
6535 // to create 256-bit vectors from two other 128-bit ones.
6536 static SDValue LowerAVXCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
6538 MVT ResVT = Op.getSimpleValueType();
6540 assert((ResVT.is256BitVector() ||
6541 ResVT.is512BitVector()) && "Value type must be 256-/512-bit wide");
6543 SDValue V1 = Op.getOperand(0);
6544 SDValue V2 = Op.getOperand(1);
6545 unsigned NumElems = ResVT.getVectorNumElements();
6546 if (ResVT.is256BitVector())
6547 return Concat128BitVectors(V1, V2, ResVT, NumElems, DAG, dl);
6549 if (Op.getNumOperands() == 4) {
6550 MVT HalfVT = MVT::getVectorVT(ResVT.getVectorElementType(),
6551 ResVT.getVectorNumElements()/2);
6552 SDValue V3 = Op.getOperand(2);
6553 SDValue V4 = Op.getOperand(3);
6554 return Concat256BitVectors(Concat128BitVectors(V1, V2, HalfVT, NumElems/2, DAG, dl),
6555 Concat128BitVectors(V3, V4, HalfVT, NumElems/2, DAG, dl), ResVT, NumElems, DAG, dl);
6557 return Concat256BitVectors(V1, V2, ResVT, NumElems, DAG, dl);
6560 static SDValue LowerCONCAT_VECTORSvXi1(SDValue Op,
6561 const X86Subtarget *Subtarget,
6562 SelectionDAG & DAG) {
6564 MVT ResVT = Op.getSimpleValueType();
6565 unsigned NumOfOperands = Op.getNumOperands();
6567 assert(isPowerOf2_32(NumOfOperands) &&
6568 "Unexpected number of operands in CONCAT_VECTORS");
6570 SDValue Undef = DAG.getUNDEF(ResVT);
6571 if (NumOfOperands > 2) {
6572 // Specialize the cases when all, or all but one, of the operands are undef.
6573 unsigned NumOfDefinedOps = 0;
6575 for (unsigned i = 0; i < NumOfOperands; i++)
6576 if (!Op.getOperand(i).isUndef()) {
6580 if (NumOfDefinedOps == 0)
6582 if (NumOfDefinedOps == 1) {
6583 unsigned SubVecNumElts =
6584 Op.getOperand(OpIdx).getValueType().getVectorNumElements();
6585 SDValue IdxVal = DAG.getIntPtrConstant(SubVecNumElts * OpIdx, dl);
6586 return DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResVT, Undef,
6587 Op.getOperand(OpIdx), IdxVal);
6590 MVT HalfVT = MVT::getVectorVT(ResVT.getVectorElementType(),
6591 ResVT.getVectorNumElements()/2);
6592 SmallVector<SDValue, 2> Ops;
6593 for (unsigned i = 0; i < NumOfOperands/2; i++)
6594 Ops.push_back(Op.getOperand(i));
6595 SDValue Lo = DAG.getNode(ISD::CONCAT_VECTORS, dl, HalfVT, Ops);
6597 for (unsigned i = NumOfOperands/2; i < NumOfOperands; i++)
6598 Ops.push_back(Op.getOperand(i));
6599 SDValue Hi = DAG.getNode(ISD::CONCAT_VECTORS, dl, HalfVT, Ops);
6600 return DAG.getNode(ISD::CONCAT_VECTORS, dl, ResVT, Lo, Hi);
6604 SDValue V1 = Op.getOperand(0);
6605 SDValue V2 = Op.getOperand(1);
6606 unsigned NumElems = ResVT.getVectorNumElements();
6607 assert(V1.getValueType() == V2.getValueType() &&
6608 V1.getValueType().getVectorNumElements() == NumElems/2 &&
6609 "Unexpected operands in CONCAT_VECTORS");
6611 if (ResVT.getSizeInBits() >= 16)
6612 return Op; // The operation is legal with KUNPCK
6614 bool IsZeroV1 = ISD::isBuildVectorAllZeros(V1.getNode());
6615 bool IsZeroV2 = ISD::isBuildVectorAllZeros(V2.getNode());
6616 SDValue ZeroVec = getZeroVector(ResVT, Subtarget, DAG, dl);
6617 if (IsZeroV1 && IsZeroV2)
6620 SDValue ZeroIdx = DAG.getIntPtrConstant(0, dl);
6622 return DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResVT, Undef, V1, ZeroIdx);
6624 return DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResVT, ZeroVec, V1, ZeroIdx);
6626 SDValue IdxVal = DAG.getIntPtrConstant(NumElems/2, dl);
6628 V2 = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResVT, Undef, V2, IdxVal);
6631 return DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResVT, ZeroVec, V2, IdxVal);
6633 V1 = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResVT, Undef, V1, ZeroIdx);
6634 return DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResVT, V1, V2, IdxVal);
6637 static SDValue LowerCONCAT_VECTORS(SDValue Op,
6638 const X86Subtarget *Subtarget,
6639 SelectionDAG &DAG) {
6640 MVT VT = Op.getSimpleValueType();
6641 if (VT.getVectorElementType() == MVT::i1)
6642 return LowerCONCAT_VECTORSvXi1(Op, Subtarget, DAG);
6644 assert((VT.is256BitVector() && Op.getNumOperands() == 2) ||
6645 (VT.is512BitVector() && (Op.getNumOperands() == 2 ||
6646 Op.getNumOperands() == 4)));
6648 // AVX can use the vinsertf128 instruction to create 256-bit vectors
6649 // from two other 128-bit ones.
6651 // 512-bit vector may contain 2 256-bit vectors or 4 128-bit vectors
6652 return LowerAVXCONCAT_VECTORS(Op, DAG);
6655 //===----------------------------------------------------------------------===//
6656 // Vector shuffle lowering
6658 // This is an experimental code path for lowering vector shuffles on x86. It is
6659 // designed to handle arbitrary vector shuffles and blends, gracefully
6660 // degrading performance as necessary. It works hard to recognize idiomatic
6661 // shuffles and lower them to optimal instruction patterns without leaving
6662 // a framework that allows reasonably efficient handling of all vector shuffle
6664 //===----------------------------------------------------------------------===//
6666 /// \brief Tiny helper function to identify a no-op mask.
6668 /// This is a somewhat boring predicate function. It checks whether the mask
6669 /// array input, which is assumed to be a single-input shuffle mask of the kind
6670 /// used by the X86 shuffle instructions (not a fully general
6671 /// ShuffleVectorSDNode mask) requires any shuffles to occur. Both undef and an
6672 /// in-place shuffle are 'no-op's.
6673 static bool isNoopShuffleMask(ArrayRef<int> Mask) {
6674 for (int i = 0, Size = Mask.size(); i < Size; ++i)
6675 if (Mask[i] != -1 && Mask[i] != i)
6680 /// \brief Helper function to classify a mask as a single-input mask.
6682 /// This isn't a generic single-input test because in the vector shuffle
6683 /// lowering we canonicalize single inputs to be the first input operand. This
6684 /// means we can more quickly test for a single input by only checking whether
6685 /// an input from the second operand exists. We also assume that the size of
6686 /// mask corresponds to the size of the input vectors which isn't true in the
6687 /// fully general case.
6688 static bool isSingleInputShuffleMask(ArrayRef<int> Mask) {
6690 if (M >= (int)Mask.size())
6695 /// \brief Test whether there are elements crossing 128-bit lanes in this
6698 /// X86 divides up its shuffles into in-lane and cross-lane shuffle operations
6699 /// and we routinely test for these.
6700 static bool is128BitLaneCrossingShuffleMask(MVT VT, ArrayRef<int> Mask) {
6701 int LaneSize = 128 / VT.getScalarSizeInBits();
6702 int Size = Mask.size();
6703 for (int i = 0; i < Size; ++i)
6704 if (Mask[i] >= 0 && (Mask[i] % Size) / LaneSize != i / LaneSize)
6709 /// \brief Test whether a shuffle mask is equivalent within each 128-bit lane.
6711 /// This checks a shuffle mask to see if it is performing the same
6712 /// 128-bit lane-relative shuffle in each 128-bit lane. This trivially implies
6713 /// that it is also not lane-crossing. It may however involve a blend from the
6714 /// same lane of a second vector.
6716 /// The specific repeated shuffle mask is populated in \p RepeatedMask, as it is
6717 /// non-trivial to compute in the face of undef lanes. The representation is
6718 /// *not* suitable for use with existing 128-bit shuffles as it will contain
6719 /// entries from both V1 and V2 inputs to the wider mask.
6721 is128BitLaneRepeatedShuffleMask(MVT VT, ArrayRef<int> Mask,
6722 SmallVectorImpl<int> &RepeatedMask) {
6723 int LaneSize = 128 / VT.getScalarSizeInBits();
6724 RepeatedMask.resize(LaneSize, -1);
6725 int Size = Mask.size();
6726 for (int i = 0; i < Size; ++i) {
6729 if ((Mask[i] % Size) / LaneSize != i / LaneSize)
6730 // This entry crosses lanes, so there is no way to model this shuffle.
6733 // Ok, handle the in-lane shuffles by detecting if and when they repeat.
6734 if (RepeatedMask[i % LaneSize] == -1)
6735 // This is the first non-undef entry in this slot of a 128-bit lane.
6736 RepeatedMask[i % LaneSize] =
6737 Mask[i] < Size ? Mask[i] % LaneSize : Mask[i] % LaneSize + Size;
6738 else if (RepeatedMask[i % LaneSize] + (i / LaneSize) * LaneSize != Mask[i])
6739 // Found a mismatch with the repeated mask.
6745 /// \brief Checks whether a shuffle mask is equivalent to an explicit list of
6748 /// This is a fast way to test a shuffle mask against a fixed pattern:
6750 /// if (isShuffleEquivalent(Mask, 3, 2, {1, 0})) { ... }
6752 /// It returns true if the mask is exactly as wide as the argument list, and
6753 /// each element of the mask is either -1 (signifying undef) or the value given
6754 /// in the argument.
6755 static bool isShuffleEquivalent(SDValue V1, SDValue V2, ArrayRef<int> Mask,
6756 ArrayRef<int> ExpectedMask) {
6757 if (Mask.size() != ExpectedMask.size())
6760 int Size = Mask.size();
6762 // If the values are build vectors, we can look through them to find
6763 // equivalent inputs that make the shuffles equivalent.
6764 auto *BV1 = dyn_cast<BuildVectorSDNode>(V1);
6765 auto *BV2 = dyn_cast<BuildVectorSDNode>(V2);
6767 for (int i = 0; i < Size; ++i)
6768 if (Mask[i] != -1 && Mask[i] != ExpectedMask[i]) {
6769 auto *MaskBV = Mask[i] < Size ? BV1 : BV2;
6770 auto *ExpectedBV = ExpectedMask[i] < Size ? BV1 : BV2;
6771 if (!MaskBV || !ExpectedBV ||
6772 MaskBV->getOperand(Mask[i] % Size) !=
6773 ExpectedBV->getOperand(ExpectedMask[i] % Size))
6780 /// \brief Get a 4-lane 8-bit shuffle immediate for a mask.
6782 /// This helper function produces an 8-bit shuffle immediate corresponding to
6783 /// the ubiquitous shuffle encoding scheme used in x86 instructions for
6784 /// shuffling 4 lanes. It can be used with most of the PSHUF instructions for
6787 /// NB: We rely heavily on "undef" masks preserving the input lane.
6788 static SDValue getV4X86ShuffleImm8ForMask(ArrayRef<int> Mask, SDLoc DL,
6789 SelectionDAG &DAG) {
6790 assert(Mask.size() == 4 && "Only 4-lane shuffle masks");
6791 assert(Mask[0] >= -1 && Mask[0] < 4 && "Out of bound mask element!");
6792 assert(Mask[1] >= -1 && Mask[1] < 4 && "Out of bound mask element!");
6793 assert(Mask[2] >= -1 && Mask[2] < 4 && "Out of bound mask element!");
6794 assert(Mask[3] >= -1 && Mask[3] < 4 && "Out of bound mask element!");
6797 Imm |= (Mask[0] == -1 ? 0 : Mask[0]) << 0;
6798 Imm |= (Mask[1] == -1 ? 1 : Mask[1]) << 2;
6799 Imm |= (Mask[2] == -1 ? 2 : Mask[2]) << 4;
6800 Imm |= (Mask[3] == -1 ? 3 : Mask[3]) << 6;
6801 return DAG.getConstant(Imm, DL, MVT::i8);
6804 /// \brief Compute whether each element of a shuffle is zeroable.
6806 /// A "zeroable" vector shuffle element is one which can be lowered to zero.
6807 /// Either it is an undef element in the shuffle mask, the element of the input
6808 /// referenced is undef, or the element of the input referenced is known to be
6809 /// zero. Many x86 shuffles can zero lanes cheaply and we often want to handle
6810 /// as many lanes with this technique as possible to simplify the remaining
6812 static SmallBitVector computeZeroableShuffleElements(ArrayRef<int> Mask,
6813 SDValue V1, SDValue V2) {
6814 SmallBitVector Zeroable(Mask.size(), false);
6816 while (V1.getOpcode() == ISD::BITCAST)
6817 V1 = V1->getOperand(0);
6818 while (V2.getOpcode() == ISD::BITCAST)
6819 V2 = V2->getOperand(0);
6821 bool V1IsZero = ISD::isBuildVectorAllZeros(V1.getNode());
6822 bool V2IsZero = ISD::isBuildVectorAllZeros(V2.getNode());
6824 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
6826 // Handle the easy cases.
6827 if (M < 0 || (M >= 0 && M < Size && V1IsZero) || (M >= Size && V2IsZero)) {
6832 // If this is an index into a build_vector node (which has the same number
6833 // of elements), dig out the input value and use it.
6834 SDValue V = M < Size ? V1 : V2;
6835 if (V.getOpcode() != ISD::BUILD_VECTOR || Size != (int)V.getNumOperands())
6838 SDValue Input = V.getOperand(M % Size);
6839 // The UNDEF opcode check really should be dead code here, but not quite
6840 // worth asserting on (it isn't invalid, just unexpected).
6841 if (Input.getOpcode() == ISD::UNDEF || X86::isZeroNode(Input))
6848 // X86 has dedicated unpack instructions that can handle specific blend
6849 // operations: UNPCKH and UNPCKL.
6850 static SDValue lowerVectorShuffleWithUNPCK(SDLoc DL, MVT VT, ArrayRef<int> Mask,
6851 SDValue V1, SDValue V2,
6852 SelectionDAG &DAG) {
6853 int NumElts = VT.getVectorNumElements();
6854 int NumEltsInLane = 128 / VT.getScalarSizeInBits();
6855 SmallVector<int, 8> Unpckl;
6856 SmallVector<int, 8> Unpckh;
6858 for (int i = 0; i < NumElts; ++i) {
6859 unsigned LaneStart = (i / NumEltsInLane) * NumEltsInLane;
6860 int LoPos = (i % NumEltsInLane) / 2 + LaneStart + NumElts * (i % 2);
6861 int HiPos = LoPos + NumEltsInLane / 2;
6862 Unpckl.push_back(LoPos);
6863 Unpckh.push_back(HiPos);
6866 if (isShuffleEquivalent(V1, V2, Mask, Unpckl))
6867 return DAG.getNode(X86ISD::UNPCKL, DL, VT, V1, V2);
6868 if (isShuffleEquivalent(V1, V2, Mask, Unpckh))
6869 return DAG.getNode(X86ISD::UNPCKH, DL, VT, V1, V2);
6871 // Commute and try again.
6872 ShuffleVectorSDNode::commuteMask(Unpckl);
6873 if (isShuffleEquivalent(V1, V2, Mask, Unpckl))
6874 return DAG.getNode(X86ISD::UNPCKL, DL, VT, V2, V1);
6876 ShuffleVectorSDNode::commuteMask(Unpckh);
6877 if (isShuffleEquivalent(V1, V2, Mask, Unpckh))
6878 return DAG.getNode(X86ISD::UNPCKH, DL, VT, V2, V1);
6883 /// \brief Try to emit a bitmask instruction for a shuffle.
6885 /// This handles cases where we can model a blend exactly as a bitmask due to
6886 /// one of the inputs being zeroable.
6887 static SDValue lowerVectorShuffleAsBitMask(SDLoc DL, MVT VT, SDValue V1,
6888 SDValue V2, ArrayRef<int> Mask,
6889 SelectionDAG &DAG) {
6890 MVT EltVT = VT.getVectorElementType();
6891 int NumEltBits = EltVT.getSizeInBits();
6892 MVT IntEltVT = MVT::getIntegerVT(NumEltBits);
6893 SDValue Zero = DAG.getConstant(0, DL, IntEltVT);
6894 SDValue AllOnes = DAG.getConstant(APInt::getAllOnesValue(NumEltBits), DL,
6896 if (EltVT.isFloatingPoint()) {
6897 Zero = DAG.getBitcast(EltVT, Zero);
6898 AllOnes = DAG.getBitcast(EltVT, AllOnes);
6900 SmallVector<SDValue, 16> VMaskOps(Mask.size(), Zero);
6901 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
6903 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
6906 if (Mask[i] % Size != i)
6907 return SDValue(); // Not a blend.
6909 V = Mask[i] < Size ? V1 : V2;
6910 else if (V != (Mask[i] < Size ? V1 : V2))
6911 return SDValue(); // Can only let one input through the mask.
6913 VMaskOps[i] = AllOnes;
6916 return SDValue(); // No non-zeroable elements!
6918 SDValue VMask = DAG.getNode(ISD::BUILD_VECTOR, DL, VT, VMaskOps);
6919 V = DAG.getNode(VT.isFloatingPoint()
6920 ? (unsigned) X86ISD::FAND : (unsigned) ISD::AND,
6925 /// \brief Try to emit a blend instruction for a shuffle using bit math.
6927 /// This is used as a fallback approach when first class blend instructions are
6928 /// unavailable. Currently it is only suitable for integer vectors, but could
6929 /// be generalized for floating point vectors if desirable.
6930 static SDValue lowerVectorShuffleAsBitBlend(SDLoc DL, MVT VT, SDValue V1,
6931 SDValue V2, ArrayRef<int> Mask,
6932 SelectionDAG &DAG) {
6933 assert(VT.isInteger() && "Only supports integer vector types!");
6934 MVT EltVT = VT.getVectorElementType();
6935 int NumEltBits = EltVT.getSizeInBits();
6936 SDValue Zero = DAG.getConstant(0, DL, EltVT);
6937 SDValue AllOnes = DAG.getConstant(APInt::getAllOnesValue(NumEltBits), DL,
6939 SmallVector<SDValue, 16> MaskOps;
6940 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
6941 if (Mask[i] != -1 && Mask[i] != i && Mask[i] != i + Size)
6942 return SDValue(); // Shuffled input!
6943 MaskOps.push_back(Mask[i] < Size ? AllOnes : Zero);
6946 SDValue V1Mask = DAG.getNode(ISD::BUILD_VECTOR, DL, VT, MaskOps);
6947 V1 = DAG.getNode(ISD::AND, DL, VT, V1, V1Mask);
6948 // We have to cast V2 around.
6949 MVT MaskVT = MVT::getVectorVT(MVT::i64, VT.getSizeInBits() / 64);
6950 V2 = DAG.getBitcast(VT, DAG.getNode(X86ISD::ANDNP, DL, MaskVT,
6951 DAG.getBitcast(MaskVT, V1Mask),
6952 DAG.getBitcast(MaskVT, V2)));
6953 return DAG.getNode(ISD::OR, DL, VT, V1, V2);
6956 /// \brief Try to emit a blend instruction for a shuffle.
6958 /// This doesn't do any checks for the availability of instructions for blending
6959 /// these values. It relies on the availability of the X86ISD::BLENDI pattern to
6960 /// be matched in the backend with the type given. What it does check for is
6961 /// that the shuffle mask is a blend, or convertible into a blend with zero.
6962 static SDValue lowerVectorShuffleAsBlend(SDLoc DL, MVT VT, SDValue V1,
6963 SDValue V2, ArrayRef<int> Original,
6964 const X86Subtarget *Subtarget,
6965 SelectionDAG &DAG) {
6966 bool V1IsZero = ISD::isBuildVectorAllZeros(V1.getNode());
6967 bool V2IsZero = ISD::isBuildVectorAllZeros(V2.getNode());
6968 SmallVector<int, 8> Mask(Original.begin(), Original.end());
6969 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
6970 bool ForceV1Zero = false, ForceV2Zero = false;
6972 // Attempt to generate the binary blend mask. If an input is zero then
6973 // we can use any lane.
6974 // TODO: generalize the zero matching to any scalar like isShuffleEquivalent.
6975 unsigned BlendMask = 0;
6976 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
6982 if (M == i + Size) {
6983 BlendMask |= 1u << i;
6994 BlendMask |= 1u << i;
6999 return SDValue(); // Shuffled input!
7002 // Create a REAL zero vector - ISD::isBuildVectorAllZeros allows UNDEFs.
7004 V1 = getZeroVector(VT, Subtarget, DAG, DL);
7006 V2 = getZeroVector(VT, Subtarget, DAG, DL);
7008 auto ScaleBlendMask = [](unsigned BlendMask, int Size, int Scale) {
7009 unsigned ScaledMask = 0;
7010 for (int i = 0; i != Size; ++i)
7011 if (BlendMask & (1u << i))
7012 for (int j = 0; j != Scale; ++j)
7013 ScaledMask |= 1u << (i * Scale + j);
7017 switch (VT.SimpleTy) {
7022 return DAG.getNode(X86ISD::BLENDI, DL, VT, V1, V2,
7023 DAG.getConstant(BlendMask, DL, MVT::i8));
7027 assert(Subtarget->hasAVX2() && "256-bit integer blends require AVX2!");
7031 // If we have AVX2 it is faster to use VPBLENDD when the shuffle fits into
7032 // that instruction.
7033 if (Subtarget->hasAVX2()) {
7034 // Scale the blend by the number of 32-bit dwords per element.
7035 int Scale = VT.getScalarSizeInBits() / 32;
7036 BlendMask = ScaleBlendMask(BlendMask, Mask.size(), Scale);
7037 MVT BlendVT = VT.getSizeInBits() > 128 ? MVT::v8i32 : MVT::v4i32;
7038 V1 = DAG.getBitcast(BlendVT, V1);
7039 V2 = DAG.getBitcast(BlendVT, V2);
7040 return DAG.getBitcast(
7041 VT, DAG.getNode(X86ISD::BLENDI, DL, BlendVT, V1, V2,
7042 DAG.getConstant(BlendMask, DL, MVT::i8)));
7046 // For integer shuffles we need to expand the mask and cast the inputs to
7047 // v8i16s prior to blending.
7048 int Scale = 8 / VT.getVectorNumElements();
7049 BlendMask = ScaleBlendMask(BlendMask, Mask.size(), Scale);
7050 V1 = DAG.getBitcast(MVT::v8i16, V1);
7051 V2 = DAG.getBitcast(MVT::v8i16, V2);
7052 return DAG.getBitcast(VT,
7053 DAG.getNode(X86ISD::BLENDI, DL, MVT::v8i16, V1, V2,
7054 DAG.getConstant(BlendMask, DL, MVT::i8)));
7058 assert(Subtarget->hasAVX2() && "256-bit integer blends require AVX2!");
7059 SmallVector<int, 8> RepeatedMask;
7060 if (is128BitLaneRepeatedShuffleMask(MVT::v16i16, Mask, RepeatedMask)) {
7061 // We can lower these with PBLENDW which is mirrored across 128-bit lanes.
7062 assert(RepeatedMask.size() == 8 && "Repeated mask size doesn't match!");
7064 for (int i = 0; i < 8; ++i)
7065 if (RepeatedMask[i] >= 16)
7066 BlendMask |= 1u << i;
7067 return DAG.getNode(X86ISD::BLENDI, DL, MVT::v16i16, V1, V2,
7068 DAG.getConstant(BlendMask, DL, MVT::i8));
7074 assert((VT.is128BitVector() || Subtarget->hasAVX2()) &&
7075 "256-bit byte-blends require AVX2 support!");
7077 // Attempt to lower to a bitmask if we can. VPAND is faster than VPBLENDVB.
7078 if (SDValue Masked = lowerVectorShuffleAsBitMask(DL, VT, V1, V2, Mask, DAG))
7081 // Scale the blend by the number of bytes per element.
7082 int Scale = VT.getScalarSizeInBits() / 8;
7084 // This form of blend is always done on bytes. Compute the byte vector
7086 MVT BlendVT = MVT::getVectorVT(MVT::i8, VT.getSizeInBits() / 8);
7088 // Compute the VSELECT mask. Note that VSELECT is really confusing in the
7089 // mix of LLVM's code generator and the x86 backend. We tell the code
7090 // generator that boolean values in the elements of an x86 vector register
7091 // are -1 for true and 0 for false. We then use the LLVM semantics of 'true'
7092 // mapping a select to operand #1, and 'false' mapping to operand #2. The
7093 // reality in x86 is that vector masks (pre-AVX-512) use only the high bit
7094 // of the element (the remaining are ignored) and 0 in that high bit would
7095 // mean operand #1 while 1 in the high bit would mean operand #2. So while
7096 // the LLVM model for boolean values in vector elements gets the relevant
7097 // bit set, it is set backwards and over constrained relative to x86's
7099 SmallVector<SDValue, 32> VSELECTMask;
7100 for (int i = 0, Size = Mask.size(); i < Size; ++i)
7101 for (int j = 0; j < Scale; ++j)
7102 VSELECTMask.push_back(
7103 Mask[i] < 0 ? DAG.getUNDEF(MVT::i8)
7104 : DAG.getConstant(Mask[i] < Size ? -1 : 0, DL,
7107 V1 = DAG.getBitcast(BlendVT, V1);
7108 V2 = DAG.getBitcast(BlendVT, V2);
7109 return DAG.getBitcast(VT, DAG.getNode(ISD::VSELECT, DL, BlendVT,
7110 DAG.getNode(ISD::BUILD_VECTOR, DL,
7111 BlendVT, VSELECTMask),
7116 llvm_unreachable("Not a supported integer vector type!");
7120 /// \brief Try to lower as a blend of elements from two inputs followed by
7121 /// a single-input permutation.
7123 /// This matches the pattern where we can blend elements from two inputs and
7124 /// then reduce the shuffle to a single-input permutation.
7125 static SDValue lowerVectorShuffleAsBlendAndPermute(SDLoc DL, MVT VT, SDValue V1,
7128 SelectionDAG &DAG) {
7129 // We build up the blend mask while checking whether a blend is a viable way
7130 // to reduce the shuffle.
7131 SmallVector<int, 32> BlendMask(Mask.size(), -1);
7132 SmallVector<int, 32> PermuteMask(Mask.size(), -1);
7134 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
7138 assert(Mask[i] < Size * 2 && "Shuffle input is out of bounds.");
7140 if (BlendMask[Mask[i] % Size] == -1)
7141 BlendMask[Mask[i] % Size] = Mask[i];
7142 else if (BlendMask[Mask[i] % Size] != Mask[i])
7143 return SDValue(); // Can't blend in the needed input!
7145 PermuteMask[i] = Mask[i] % Size;
7148 SDValue V = DAG.getVectorShuffle(VT, DL, V1, V2, BlendMask);
7149 return DAG.getVectorShuffle(VT, DL, V, DAG.getUNDEF(VT), PermuteMask);
7152 /// \brief Generic routine to decompose a shuffle and blend into indepndent
7153 /// blends and permutes.
7155 /// This matches the extremely common pattern for handling combined
7156 /// shuffle+blend operations on newer X86 ISAs where we have very fast blend
7157 /// operations. It will try to pick the best arrangement of shuffles and
7159 static SDValue lowerVectorShuffleAsDecomposedShuffleBlend(SDLoc DL, MVT VT,
7163 SelectionDAG &DAG) {
7164 // Shuffle the input elements into the desired positions in V1 and V2 and
7165 // blend them together.
7166 SmallVector<int, 32> V1Mask(Mask.size(), -1);
7167 SmallVector<int, 32> V2Mask(Mask.size(), -1);
7168 SmallVector<int, 32> BlendMask(Mask.size(), -1);
7169 for (int i = 0, Size = Mask.size(); i < Size; ++i)
7170 if (Mask[i] >= 0 && Mask[i] < Size) {
7171 V1Mask[i] = Mask[i];
7173 } else if (Mask[i] >= Size) {
7174 V2Mask[i] = Mask[i] - Size;
7175 BlendMask[i] = i + Size;
7178 // Try to lower with the simpler initial blend strategy unless one of the
7179 // input shuffles would be a no-op. We prefer to shuffle inputs as the
7180 // shuffle may be able to fold with a load or other benefit. However, when
7181 // we'll have to do 2x as many shuffles in order to achieve this, blending
7182 // first is a better strategy.
7183 if (!isNoopShuffleMask(V1Mask) && !isNoopShuffleMask(V2Mask))
7184 if (SDValue BlendPerm =
7185 lowerVectorShuffleAsBlendAndPermute(DL, VT, V1, V2, Mask, DAG))
7188 V1 = DAG.getVectorShuffle(VT, DL, V1, DAG.getUNDEF(VT), V1Mask);
7189 V2 = DAG.getVectorShuffle(VT, DL, V2, DAG.getUNDEF(VT), V2Mask);
7190 return DAG.getVectorShuffle(VT, DL, V1, V2, BlendMask);
7193 /// \brief Try to lower a vector shuffle as a byte rotation.
7195 /// SSSE3 has a generic PALIGNR instruction in x86 that will do an arbitrary
7196 /// byte-rotation of the concatenation of two vectors; pre-SSSE3 can use
7197 /// a PSRLDQ/PSLLDQ/POR pattern to get a similar effect. This routine will
7198 /// try to generically lower a vector shuffle through such an pattern. It
7199 /// does not check for the profitability of lowering either as PALIGNR or
7200 /// PSRLDQ/PSLLDQ/POR, only whether the mask is valid to lower in that form.
7201 /// This matches shuffle vectors that look like:
7203 /// v8i16 [11, 12, 13, 14, 15, 0, 1, 2]
7205 /// Essentially it concatenates V1 and V2, shifts right by some number of
7206 /// elements, and takes the low elements as the result. Note that while this is
7207 /// specified as a *right shift* because x86 is little-endian, it is a *left
7208 /// rotate* of the vector lanes.
7209 static SDValue lowerVectorShuffleAsByteRotate(SDLoc DL, MVT VT, SDValue V1,
7212 const X86Subtarget *Subtarget,
7213 SelectionDAG &DAG) {
7214 assert(!isNoopShuffleMask(Mask) && "We shouldn't lower no-op shuffles!");
7216 int NumElts = Mask.size();
7217 int NumLanes = VT.getSizeInBits() / 128;
7218 int NumLaneElts = NumElts / NumLanes;
7220 // We need to detect various ways of spelling a rotation:
7221 // [11, 12, 13, 14, 15, 0, 1, 2]
7222 // [-1, 12, 13, 14, -1, -1, 1, -1]
7223 // [-1, -1, -1, -1, -1, -1, 1, 2]
7224 // [ 3, 4, 5, 6, 7, 8, 9, 10]
7225 // [-1, 4, 5, 6, -1, -1, 9, -1]
7226 // [-1, 4, 5, 6, -1, -1, -1, -1]
7229 for (int l = 0; l < NumElts; l += NumLaneElts) {
7230 for (int i = 0; i < NumLaneElts; ++i) {
7231 if (Mask[l + i] == -1)
7233 assert(Mask[l + i] >= 0 && "Only -1 is a valid negative mask element!");
7235 // Get the mod-Size index and lane correct it.
7236 int LaneIdx = (Mask[l + i] % NumElts) - l;
7237 // Make sure it was in this lane.
7238 if (LaneIdx < 0 || LaneIdx >= NumLaneElts)
7241 // Determine where a rotated vector would have started.
7242 int StartIdx = i - LaneIdx;
7244 // The identity rotation isn't interesting, stop.
7247 // If we found the tail of a vector the rotation must be the missing
7248 // front. If we found the head of a vector, it must be how much of the
7250 int CandidateRotation = StartIdx < 0 ? -StartIdx : NumLaneElts - StartIdx;
7253 Rotation = CandidateRotation;
7254 else if (Rotation != CandidateRotation)
7255 // The rotations don't match, so we can't match this mask.
7258 // Compute which value this mask is pointing at.
7259 SDValue MaskV = Mask[l + i] < NumElts ? V1 : V2;
7261 // Compute which of the two target values this index should be assigned
7262 // to. This reflects whether the high elements are remaining or the low
7263 // elements are remaining.
7264 SDValue &TargetV = StartIdx < 0 ? Hi : Lo;
7266 // Either set up this value if we've not encountered it before, or check
7267 // that it remains consistent.
7270 else if (TargetV != MaskV)
7271 // This may be a rotation, but it pulls from the inputs in some
7272 // unsupported interleaving.
7277 // Check that we successfully analyzed the mask, and normalize the results.
7278 assert(Rotation != 0 && "Failed to locate a viable rotation!");
7279 assert((Lo || Hi) && "Failed to find a rotated input vector!");
7285 // The actual rotate instruction rotates bytes, so we need to scale the
7286 // rotation based on how many bytes are in the vector lane.
7287 int Scale = 16 / NumLaneElts;
7289 // SSSE3 targets can use the palignr instruction.
7290 if (Subtarget->hasSSSE3()) {
7291 // Cast the inputs to i8 vector of correct length to match PALIGNR.
7292 MVT AlignVT = MVT::getVectorVT(MVT::i8, 16 * NumLanes);
7293 Lo = DAG.getBitcast(AlignVT, Lo);
7294 Hi = DAG.getBitcast(AlignVT, Hi);
7296 return DAG.getBitcast(
7297 VT, DAG.getNode(X86ISD::PALIGNR, DL, AlignVT, Lo, Hi,
7298 DAG.getConstant(Rotation * Scale, DL, MVT::i8)));
7301 assert(VT.is128BitVector() &&
7302 "Rotate-based lowering only supports 128-bit lowering!");
7303 assert(Mask.size() <= 16 &&
7304 "Can shuffle at most 16 bytes in a 128-bit vector!");
7306 // Default SSE2 implementation
7307 int LoByteShift = 16 - Rotation * Scale;
7308 int HiByteShift = Rotation * Scale;
7310 // Cast the inputs to v2i64 to match PSLLDQ/PSRLDQ.
7311 Lo = DAG.getBitcast(MVT::v2i64, Lo);
7312 Hi = DAG.getBitcast(MVT::v2i64, Hi);
7314 SDValue LoShift = DAG.getNode(X86ISD::VSHLDQ, DL, MVT::v2i64, Lo,
7315 DAG.getConstant(LoByteShift, DL, MVT::i8));
7316 SDValue HiShift = DAG.getNode(X86ISD::VSRLDQ, DL, MVT::v2i64, Hi,
7317 DAG.getConstant(HiByteShift, DL, MVT::i8));
7318 return DAG.getBitcast(VT,
7319 DAG.getNode(ISD::OR, DL, MVT::v2i64, LoShift, HiShift));
7322 /// \brief Try to lower a vector shuffle as a bit shift (shifts in zeros).
7324 /// Attempts to match a shuffle mask against the PSLL(W/D/Q/DQ) and
7325 /// PSRL(W/D/Q/DQ) SSE2 and AVX2 logical bit-shift instructions. The function
7326 /// matches elements from one of the input vectors shuffled to the left or
7327 /// right with zeroable elements 'shifted in'. It handles both the strictly
7328 /// bit-wise element shifts and the byte shift across an entire 128-bit double
7331 /// PSHL : (little-endian) left bit shift.
7332 /// [ zz, 0, zz, 2 ]
7333 /// [ -1, 4, zz, -1 ]
7334 /// PSRL : (little-endian) right bit shift.
7336 /// [ -1, -1, 7, zz]
7337 /// PSLLDQ : (little-endian) left byte shift
7338 /// [ zz, 0, 1, 2, 3, 4, 5, 6]
7339 /// [ zz, zz, -1, -1, 2, 3, 4, -1]
7340 /// [ zz, zz, zz, zz, zz, zz, -1, 1]
7341 /// PSRLDQ : (little-endian) right byte shift
7342 /// [ 5, 6, 7, zz, zz, zz, zz, zz]
7343 /// [ -1, 5, 6, 7, zz, zz, zz, zz]
7344 /// [ 1, 2, -1, -1, -1, -1, zz, zz]
7345 static SDValue lowerVectorShuffleAsShift(SDLoc DL, MVT VT, SDValue V1,
7346 SDValue V2, ArrayRef<int> Mask,
7347 SelectionDAG &DAG) {
7348 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
7350 int Size = Mask.size();
7351 assert(Size == (int)VT.getVectorNumElements() && "Unexpected mask size");
7353 auto CheckZeros = [&](int Shift, int Scale, bool Left) {
7354 for (int i = 0; i < Size; i += Scale)
7355 for (int j = 0; j < Shift; ++j)
7356 if (!Zeroable[i + j + (Left ? 0 : (Scale - Shift))])
7362 auto MatchShift = [&](int Shift, int Scale, bool Left, SDValue V) {
7363 for (int i = 0; i != Size; i += Scale) {
7364 unsigned Pos = Left ? i + Shift : i;
7365 unsigned Low = Left ? i : i + Shift;
7366 unsigned Len = Scale - Shift;
7367 if (!isSequentialOrUndefInRange(Mask, Pos, Len,
7368 Low + (V == V1 ? 0 : Size)))
7372 int ShiftEltBits = VT.getScalarSizeInBits() * Scale;
7373 bool ByteShift = ShiftEltBits > 64;
7374 unsigned OpCode = Left ? (ByteShift ? X86ISD::VSHLDQ : X86ISD::VSHLI)
7375 : (ByteShift ? X86ISD::VSRLDQ : X86ISD::VSRLI);
7376 int ShiftAmt = Shift * VT.getScalarSizeInBits() / (ByteShift ? 8 : 1);
7378 // Normalize the scale for byte shifts to still produce an i64 element
7380 Scale = ByteShift ? Scale / 2 : Scale;
7382 // We need to round trip through the appropriate type for the shift.
7383 MVT ShiftSVT = MVT::getIntegerVT(VT.getScalarSizeInBits() * Scale);
7384 MVT ShiftVT = MVT::getVectorVT(ShiftSVT, Size / Scale);
7385 assert(DAG.getTargetLoweringInfo().isTypeLegal(ShiftVT) &&
7386 "Illegal integer vector type");
7387 V = DAG.getBitcast(ShiftVT, V);
7389 V = DAG.getNode(OpCode, DL, ShiftVT, V,
7390 DAG.getConstant(ShiftAmt, DL, MVT::i8));
7391 return DAG.getBitcast(VT, V);
7394 // SSE/AVX supports logical shifts up to 64-bit integers - so we can just
7395 // keep doubling the size of the integer elements up to that. We can
7396 // then shift the elements of the integer vector by whole multiples of
7397 // their width within the elements of the larger integer vector. Test each
7398 // multiple to see if we can find a match with the moved element indices
7399 // and that the shifted in elements are all zeroable.
7400 for (int Scale = 2; Scale * VT.getScalarSizeInBits() <= 128; Scale *= 2)
7401 for (int Shift = 1; Shift != Scale; ++Shift)
7402 for (bool Left : {true, false})
7403 if (CheckZeros(Shift, Scale, Left))
7404 for (SDValue V : {V1, V2})
7405 if (SDValue Match = MatchShift(Shift, Scale, Left, V))
7412 /// \brief Try to lower a vector shuffle using SSE4a EXTRQ/INSERTQ.
7413 static SDValue lowerVectorShuffleWithSSE4A(SDLoc DL, MVT VT, SDValue V1,
7414 SDValue V2, ArrayRef<int> Mask,
7415 SelectionDAG &DAG) {
7416 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
7417 assert(!Zeroable.all() && "Fully zeroable shuffle mask");
7419 int Size = Mask.size();
7420 int HalfSize = Size / 2;
7421 assert(Size == (int)VT.getVectorNumElements() && "Unexpected mask size");
7423 // Upper half must be undefined.
7424 if (!isUndefInRange(Mask, HalfSize, HalfSize))
7427 // EXTRQ: Extract Len elements from lower half of source, starting at Idx.
7428 // Remainder of lower half result is zero and upper half is all undef.
7429 auto LowerAsEXTRQ = [&]() {
7430 // Determine the extraction length from the part of the
7431 // lower half that isn't zeroable.
7433 for (; Len > 0; --Len)
7434 if (!Zeroable[Len - 1])
7436 assert(Len > 0 && "Zeroable shuffle mask");
7438 // Attempt to match first Len sequential elements from the lower half.
7441 for (int i = 0; i != Len; ++i) {
7445 SDValue &V = (M < Size ? V1 : V2);
7448 // The extracted elements must start at a valid index and all mask
7449 // elements must be in the lower half.
7450 if (i > M || M >= HalfSize)
7453 if (Idx < 0 || (Src == V && Idx == (M - i))) {
7464 assert((Idx + Len) <= HalfSize && "Illegal extraction mask");
7465 int BitLen = (Len * VT.getScalarSizeInBits()) & 0x3f;
7466 int BitIdx = (Idx * VT.getScalarSizeInBits()) & 0x3f;
7467 return DAG.getNode(X86ISD::EXTRQI, DL, VT, Src,
7468 DAG.getConstant(BitLen, DL, MVT::i8),
7469 DAG.getConstant(BitIdx, DL, MVT::i8));
7472 if (SDValue ExtrQ = LowerAsEXTRQ())
7475 // INSERTQ: Extract lowest Len elements from lower half of second source and
7476 // insert over first source, starting at Idx.
7477 // { A[0], .., A[Idx-1], B[0], .., B[Len-1], A[Idx+Len], .., UNDEF, ... }
7478 auto LowerAsInsertQ = [&]() {
7479 for (int Idx = 0; Idx != HalfSize; ++Idx) {
7482 // Attempt to match first source from mask before insertion point.
7483 if (isUndefInRange(Mask, 0, Idx)) {
7485 } else if (isSequentialOrUndefInRange(Mask, 0, Idx, 0)) {
7487 } else if (isSequentialOrUndefInRange(Mask, 0, Idx, Size)) {
7493 // Extend the extraction length looking to match both the insertion of
7494 // the second source and the remaining elements of the first.
7495 for (int Hi = Idx + 1; Hi <= HalfSize; ++Hi) {
7500 if (isSequentialOrUndefInRange(Mask, Idx, Len, 0)) {
7502 } else if (isSequentialOrUndefInRange(Mask, Idx, Len, Size)) {
7508 // Match the remaining elements of the lower half.
7509 if (isUndefInRange(Mask, Hi, HalfSize - Hi)) {
7511 } else if ((!Base || (Base == V1)) &&
7512 isSequentialOrUndefInRange(Mask, Hi, HalfSize - Hi, Hi)) {
7514 } else if ((!Base || (Base == V2)) &&
7515 isSequentialOrUndefInRange(Mask, Hi, HalfSize - Hi,
7522 // We may not have a base (first source) - this can safely be undefined.
7524 Base = DAG.getUNDEF(VT);
7526 int BitLen = (Len * VT.getScalarSizeInBits()) & 0x3f;
7527 int BitIdx = (Idx * VT.getScalarSizeInBits()) & 0x3f;
7528 return DAG.getNode(X86ISD::INSERTQI, DL, VT, Base, Insert,
7529 DAG.getConstant(BitLen, DL, MVT::i8),
7530 DAG.getConstant(BitIdx, DL, MVT::i8));
7537 if (SDValue InsertQ = LowerAsInsertQ())
7543 /// \brief Lower a vector shuffle as a zero or any extension.
7545 /// Given a specific number of elements, element bit width, and extension
7546 /// stride, produce either a zero or any extension based on the available
7547 /// features of the subtarget. The extended elements are consecutive and
7548 /// begin and can start from an offseted element index in the input; to
7549 /// avoid excess shuffling the offset must either being in the bottom lane
7550 /// or at the start of a higher lane. All extended elements must be from
7552 static SDValue lowerVectorShuffleAsSpecificZeroOrAnyExtend(
7553 SDLoc DL, MVT VT, int Scale, int Offset, bool AnyExt, SDValue InputV,
7554 ArrayRef<int> Mask, const X86Subtarget *Subtarget, SelectionDAG &DAG) {
7555 assert(Scale > 1 && "Need a scale to extend.");
7556 int EltBits = VT.getScalarSizeInBits();
7557 int NumElements = VT.getVectorNumElements();
7558 int NumEltsPerLane = 128 / EltBits;
7559 int OffsetLane = Offset / NumEltsPerLane;
7560 assert((EltBits == 8 || EltBits == 16 || EltBits == 32) &&
7561 "Only 8, 16, and 32 bit elements can be extended.");
7562 assert(Scale * EltBits <= 64 && "Cannot zero extend past 64 bits.");
7563 assert(0 <= Offset && "Extension offset must be positive.");
7564 assert((Offset < NumEltsPerLane || Offset % NumEltsPerLane == 0) &&
7565 "Extension offset must be in the first lane or start an upper lane.");
7567 // Check that an index is in same lane as the base offset.
7568 auto SafeOffset = [&](int Idx) {
7569 return OffsetLane == (Idx / NumEltsPerLane);
7572 // Shift along an input so that the offset base moves to the first element.
7573 auto ShuffleOffset = [&](SDValue V) {
7577 SmallVector<int, 8> ShMask((unsigned)NumElements, -1);
7578 for (int i = 0; i * Scale < NumElements; ++i) {
7579 int SrcIdx = i + Offset;
7580 ShMask[i] = SafeOffset(SrcIdx) ? SrcIdx : -1;
7582 return DAG.getVectorShuffle(VT, DL, V, DAG.getUNDEF(VT), ShMask);
7585 // Found a valid zext mask! Try various lowering strategies based on the
7586 // input type and available ISA extensions.
7587 if (Subtarget->hasSSE41()) {
7588 // Not worth offseting 128-bit vectors if scale == 2, a pattern using
7589 // PUNPCK will catch this in a later shuffle match.
7590 if (Offset && Scale == 2 && VT.is128BitVector())
7592 MVT ExtVT = MVT::getVectorVT(MVT::getIntegerVT(EltBits * Scale),
7593 NumElements / Scale);
7594 InputV = DAG.getNode(X86ISD::VZEXT, DL, ExtVT, ShuffleOffset(InputV));
7595 return DAG.getBitcast(VT, InputV);
7598 assert(VT.is128BitVector() && "Only 128-bit vectors can be extended.");
7600 // For any extends we can cheat for larger element sizes and use shuffle
7601 // instructions that can fold with a load and/or copy.
7602 if (AnyExt && EltBits == 32) {
7603 int PSHUFDMask[4] = {Offset, -1, SafeOffset(Offset + 1) ? Offset + 1 : -1,
7605 return DAG.getBitcast(
7606 VT, DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32,
7607 DAG.getBitcast(MVT::v4i32, InputV),
7608 getV4X86ShuffleImm8ForMask(PSHUFDMask, DL, DAG)));
7610 if (AnyExt && EltBits == 16 && Scale > 2) {
7611 int PSHUFDMask[4] = {Offset / 2, -1,
7612 SafeOffset(Offset + 1) ? (Offset + 1) / 2 : -1, -1};
7613 InputV = DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32,
7614 DAG.getBitcast(MVT::v4i32, InputV),
7615 getV4X86ShuffleImm8ForMask(PSHUFDMask, DL, DAG));
7616 int PSHUFWMask[4] = {1, -1, -1, -1};
7617 unsigned OddEvenOp = (Offset & 1 ? X86ISD::PSHUFLW : X86ISD::PSHUFHW);
7618 return DAG.getBitcast(
7619 VT, DAG.getNode(OddEvenOp, DL, MVT::v8i16,
7620 DAG.getBitcast(MVT::v8i16, InputV),
7621 getV4X86ShuffleImm8ForMask(PSHUFWMask, DL, DAG)));
7624 // The SSE4A EXTRQ instruction can efficiently extend the first 2 lanes
7626 if ((Scale * EltBits) == 64 && EltBits < 32 && Subtarget->hasSSE4A()) {
7627 assert(NumElements == (int)Mask.size() && "Unexpected shuffle mask size!");
7628 assert(VT.is128BitVector() && "Unexpected vector width!");
7630 int LoIdx = Offset * EltBits;
7631 SDValue Lo = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64,
7632 DAG.getNode(X86ISD::EXTRQI, DL, VT, InputV,
7633 DAG.getConstant(EltBits, DL, MVT::i8),
7634 DAG.getConstant(LoIdx, DL, MVT::i8)));
7636 if (isUndefInRange(Mask, NumElements / 2, NumElements / 2) ||
7637 !SafeOffset(Offset + 1))
7638 return DAG.getNode(ISD::BITCAST, DL, VT, Lo);
7640 int HiIdx = (Offset + 1) * EltBits;
7641 SDValue Hi = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64,
7642 DAG.getNode(X86ISD::EXTRQI, DL, VT, InputV,
7643 DAG.getConstant(EltBits, DL, MVT::i8),
7644 DAG.getConstant(HiIdx, DL, MVT::i8)));
7645 return DAG.getNode(ISD::BITCAST, DL, VT,
7646 DAG.getNode(X86ISD::UNPCKL, DL, MVT::v2i64, Lo, Hi));
7649 // If this would require more than 2 unpack instructions to expand, use
7650 // pshufb when available. We can only use more than 2 unpack instructions
7651 // when zero extending i8 elements which also makes it easier to use pshufb.
7652 if (Scale > 4 && EltBits == 8 && Subtarget->hasSSSE3()) {
7653 assert(NumElements == 16 && "Unexpected byte vector width!");
7654 SDValue PSHUFBMask[16];
7655 for (int i = 0; i < 16; ++i) {
7656 int Idx = Offset + (i / Scale);
7657 PSHUFBMask[i] = DAG.getConstant(
7658 (i % Scale == 0 && SafeOffset(Idx)) ? Idx : 0x80, DL, MVT::i8);
7660 InputV = DAG.getBitcast(MVT::v16i8, InputV);
7661 return DAG.getBitcast(VT,
7662 DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8, InputV,
7663 DAG.getNode(ISD::BUILD_VECTOR, DL,
7664 MVT::v16i8, PSHUFBMask)));
7667 // If we are extending from an offset, ensure we start on a boundary that
7668 // we can unpack from.
7669 int AlignToUnpack = Offset % (NumElements / Scale);
7670 if (AlignToUnpack) {
7671 SmallVector<int, 8> ShMask((unsigned)NumElements, -1);
7672 for (int i = AlignToUnpack; i < NumElements; ++i)
7673 ShMask[i - AlignToUnpack] = i;
7674 InputV = DAG.getVectorShuffle(VT, DL, InputV, DAG.getUNDEF(VT), ShMask);
7675 Offset -= AlignToUnpack;
7678 // Otherwise emit a sequence of unpacks.
7680 unsigned UnpackLoHi = X86ISD::UNPCKL;
7681 if (Offset >= (NumElements / 2)) {
7682 UnpackLoHi = X86ISD::UNPCKH;
7683 Offset -= (NumElements / 2);
7686 MVT InputVT = MVT::getVectorVT(MVT::getIntegerVT(EltBits), NumElements);
7687 SDValue Ext = AnyExt ? DAG.getUNDEF(InputVT)
7688 : getZeroVector(InputVT, Subtarget, DAG, DL);
7689 InputV = DAG.getBitcast(InputVT, InputV);
7690 InputV = DAG.getNode(UnpackLoHi, DL, InputVT, InputV, Ext);
7694 } while (Scale > 1);
7695 return DAG.getBitcast(VT, InputV);
7698 /// \brief Try to lower a vector shuffle as a zero extension on any microarch.
7700 /// This routine will try to do everything in its power to cleverly lower
7701 /// a shuffle which happens to match the pattern of a zero extend. It doesn't
7702 /// check for the profitability of this lowering, it tries to aggressively
7703 /// match this pattern. It will use all of the micro-architectural details it
7704 /// can to emit an efficient lowering. It handles both blends with all-zero
7705 /// inputs to explicitly zero-extend and undef-lanes (sometimes undef due to
7706 /// masking out later).
7708 /// The reason we have dedicated lowering for zext-style shuffles is that they
7709 /// are both incredibly common and often quite performance sensitive.
7710 static SDValue lowerVectorShuffleAsZeroOrAnyExtend(
7711 SDLoc DL, MVT VT, SDValue V1, SDValue V2, ArrayRef<int> Mask,
7712 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
7713 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
7715 int Bits = VT.getSizeInBits();
7716 int NumLanes = Bits / 128;
7717 int NumElements = VT.getVectorNumElements();
7718 int NumEltsPerLane = NumElements / NumLanes;
7719 assert(VT.getScalarSizeInBits() <= 32 &&
7720 "Exceeds 32-bit integer zero extension limit");
7721 assert((int)Mask.size() == NumElements && "Unexpected shuffle mask size");
7723 // Define a helper function to check a particular ext-scale and lower to it if
7725 auto Lower = [&](int Scale) -> SDValue {
7730 for (int i = 0; i < NumElements; ++i) {
7733 continue; // Valid anywhere but doesn't tell us anything.
7734 if (i % Scale != 0) {
7735 // Each of the extended elements need to be zeroable.
7739 // We no longer are in the anyext case.
7744 // Each of the base elements needs to be consecutive indices into the
7745 // same input vector.
7746 SDValue V = M < NumElements ? V1 : V2;
7747 M = M % NumElements;
7750 Offset = M - (i / Scale);
7751 } else if (InputV != V)
7752 return SDValue(); // Flip-flopping inputs.
7754 // Offset must start in the lowest 128-bit lane or at the start of an
7756 // FIXME: Is it ever worth allowing a negative base offset?
7757 if (!((0 <= Offset && Offset < NumEltsPerLane) ||
7758 (Offset % NumEltsPerLane) == 0))
7761 // If we are offsetting, all referenced entries must come from the same
7763 if (Offset && (Offset / NumEltsPerLane) != (M / NumEltsPerLane))
7766 if ((M % NumElements) != (Offset + (i / Scale)))
7767 return SDValue(); // Non-consecutive strided elements.
7771 // If we fail to find an input, we have a zero-shuffle which should always
7772 // have already been handled.
7773 // FIXME: Maybe handle this here in case during blending we end up with one?
7777 // If we are offsetting, don't extend if we only match a single input, we
7778 // can always do better by using a basic PSHUF or PUNPCK.
7779 if (Offset != 0 && Matches < 2)
7782 return lowerVectorShuffleAsSpecificZeroOrAnyExtend(
7783 DL, VT, Scale, Offset, AnyExt, InputV, Mask, Subtarget, DAG);
7786 // The widest scale possible for extending is to a 64-bit integer.
7787 assert(Bits % 64 == 0 &&
7788 "The number of bits in a vector must be divisible by 64 on x86!");
7789 int NumExtElements = Bits / 64;
7791 // Each iteration, try extending the elements half as much, but into twice as
7793 for (; NumExtElements < NumElements; NumExtElements *= 2) {
7794 assert(NumElements % NumExtElements == 0 &&
7795 "The input vector size must be divisible by the extended size.");
7796 if (SDValue V = Lower(NumElements / NumExtElements))
7800 // General extends failed, but 128-bit vectors may be able to use MOVQ.
7804 // Returns one of the source operands if the shuffle can be reduced to a
7805 // MOVQ, copying the lower 64-bits and zero-extending to the upper 64-bits.
7806 auto CanZExtLowHalf = [&]() {
7807 for (int i = NumElements / 2; i != NumElements; ++i)
7810 if (isSequentialOrUndefInRange(Mask, 0, NumElements / 2, 0))
7812 if (isSequentialOrUndefInRange(Mask, 0, NumElements / 2, NumElements))
7817 if (SDValue V = CanZExtLowHalf()) {
7818 V = DAG.getBitcast(MVT::v2i64, V);
7819 V = DAG.getNode(X86ISD::VZEXT_MOVL, DL, MVT::v2i64, V);
7820 return DAG.getBitcast(VT, V);
7823 // No viable ext lowering found.
7827 /// \brief Try to get a scalar value for a specific element of a vector.
7829 /// Looks through BUILD_VECTOR and SCALAR_TO_VECTOR nodes to find a scalar.
7830 static SDValue getScalarValueForVectorElement(SDValue V, int Idx,
7831 SelectionDAG &DAG) {
7832 MVT VT = V.getSimpleValueType();
7833 MVT EltVT = VT.getVectorElementType();
7834 while (V.getOpcode() == ISD::BITCAST)
7835 V = V.getOperand(0);
7836 // If the bitcasts shift the element size, we can't extract an equivalent
7838 MVT NewVT = V.getSimpleValueType();
7839 if (!NewVT.isVector() || NewVT.getScalarSizeInBits() != VT.getScalarSizeInBits())
7842 if (V.getOpcode() == ISD::BUILD_VECTOR ||
7843 (Idx == 0 && V.getOpcode() == ISD::SCALAR_TO_VECTOR)) {
7844 // Ensure the scalar operand is the same size as the destination.
7845 // FIXME: Add support for scalar truncation where possible.
7846 SDValue S = V.getOperand(Idx);
7847 if (EltVT.getSizeInBits() == S.getSimpleValueType().getSizeInBits())
7848 return DAG.getNode(ISD::BITCAST, SDLoc(V), EltVT, S);
7854 /// \brief Helper to test for a load that can be folded with x86 shuffles.
7856 /// This is particularly important because the set of instructions varies
7857 /// significantly based on whether the operand is a load or not.
7858 static bool isShuffleFoldableLoad(SDValue V) {
7859 while (V.getOpcode() == ISD::BITCAST)
7860 V = V.getOperand(0);
7862 return ISD::isNON_EXTLoad(V.getNode());
7865 /// \brief Try to lower insertion of a single element into a zero vector.
7867 /// This is a common pattern that we have especially efficient patterns to lower
7868 /// across all subtarget feature sets.
7869 static SDValue lowerVectorShuffleAsElementInsertion(
7870 SDLoc DL, MVT VT, SDValue V1, SDValue V2, ArrayRef<int> Mask,
7871 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
7872 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
7874 MVT EltVT = VT.getVectorElementType();
7876 int V2Index = std::find_if(Mask.begin(), Mask.end(),
7877 [&Mask](int M) { return M >= (int)Mask.size(); }) -
7879 bool IsV1Zeroable = true;
7880 for (int i = 0, Size = Mask.size(); i < Size; ++i)
7881 if (i != V2Index && !Zeroable[i]) {
7882 IsV1Zeroable = false;
7886 // Check for a single input from a SCALAR_TO_VECTOR node.
7887 // FIXME: All of this should be canonicalized into INSERT_VECTOR_ELT and
7888 // all the smarts here sunk into that routine. However, the current
7889 // lowering of BUILD_VECTOR makes that nearly impossible until the old
7890 // vector shuffle lowering is dead.
7891 SDValue V2S = getScalarValueForVectorElement(V2, Mask[V2Index] - Mask.size(),
7893 if (V2S && DAG.getTargetLoweringInfo().isTypeLegal(V2S.getValueType())) {
7894 // We need to zext the scalar if it is smaller than an i32.
7895 V2S = DAG.getBitcast(EltVT, V2S);
7896 if (EltVT == MVT::i8 || EltVT == MVT::i16) {
7897 // Using zext to expand a narrow element won't work for non-zero
7902 // Zero-extend directly to i32.
7904 V2S = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i32, V2S);
7906 V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, ExtVT, V2S);
7907 } else if (Mask[V2Index] != (int)Mask.size() || EltVT == MVT::i8 ||
7908 EltVT == MVT::i16) {
7909 // Either not inserting from the low element of the input or the input
7910 // element size is too small to use VZEXT_MOVL to clear the high bits.
7914 if (!IsV1Zeroable) {
7915 // If V1 can't be treated as a zero vector we have fewer options to lower
7916 // this. We can't support integer vectors or non-zero targets cheaply, and
7917 // the V1 elements can't be permuted in any way.
7918 assert(VT == ExtVT && "Cannot change extended type when non-zeroable!");
7919 if (!VT.isFloatingPoint() || V2Index != 0)
7921 SmallVector<int, 8> V1Mask(Mask.begin(), Mask.end());
7922 V1Mask[V2Index] = -1;
7923 if (!isNoopShuffleMask(V1Mask))
7925 // This is essentially a special case blend operation, but if we have
7926 // general purpose blend operations, they are always faster. Bail and let
7927 // the rest of the lowering handle these as blends.
7928 if (Subtarget->hasSSE41())
7931 // Otherwise, use MOVSD or MOVSS.
7932 assert((EltVT == MVT::f32 || EltVT == MVT::f64) &&
7933 "Only two types of floating point element types to handle!");
7934 return DAG.getNode(EltVT == MVT::f32 ? X86ISD::MOVSS : X86ISD::MOVSD, DL,
7938 // This lowering only works for the low element with floating point vectors.
7939 if (VT.isFloatingPoint() && V2Index != 0)
7942 V2 = DAG.getNode(X86ISD::VZEXT_MOVL, DL, ExtVT, V2);
7944 V2 = DAG.getBitcast(VT, V2);
7947 // If we have 4 or fewer lanes we can cheaply shuffle the element into
7948 // the desired position. Otherwise it is more efficient to do a vector
7949 // shift left. We know that we can do a vector shift left because all
7950 // the inputs are zero.
7951 if (VT.isFloatingPoint() || VT.getVectorNumElements() <= 4) {
7952 SmallVector<int, 4> V2Shuffle(Mask.size(), 1);
7953 V2Shuffle[V2Index] = 0;
7954 V2 = DAG.getVectorShuffle(VT, DL, V2, DAG.getUNDEF(VT), V2Shuffle);
7956 V2 = DAG.getBitcast(MVT::v2i64, V2);
7958 X86ISD::VSHLDQ, DL, MVT::v2i64, V2,
7959 DAG.getConstant(V2Index * EltVT.getSizeInBits() / 8, DL,
7960 DAG.getTargetLoweringInfo().getScalarShiftAmountTy(
7961 DAG.getDataLayout(), VT)));
7962 V2 = DAG.getBitcast(VT, V2);
7968 /// \brief Try to lower broadcast of a single - truncated - integer element,
7969 /// coming from a scalar_to_vector/build_vector node \p V0 with larger elements.
7971 /// This assumes we have AVX2.
7972 static SDValue lowerVectorShuffleAsTruncBroadcast(SDLoc DL, MVT VT, SDValue V0,
7974 const X86Subtarget *Subtarget,
7975 SelectionDAG &DAG) {
7976 assert(Subtarget->hasAVX2() &&
7977 "We can only lower integer broadcasts with AVX2!");
7979 EVT EltVT = VT.getVectorElementType();
7980 EVT V0VT = V0.getValueType();
7982 assert(VT.isInteger() && "Unexpected non-integer trunc broadcast!");
7983 assert(V0VT.isVector() && "Unexpected non-vector vector-sized value!");
7985 EVT V0EltVT = V0VT.getVectorElementType();
7986 if (!V0EltVT.isInteger())
7989 const unsigned EltSize = EltVT.getSizeInBits();
7990 const unsigned V0EltSize = V0EltVT.getSizeInBits();
7992 // This is only a truncation if the original element type is larger.
7993 if (V0EltSize <= EltSize)
7996 assert(((V0EltSize % EltSize) == 0) &&
7997 "Scalar type sizes must all be powers of 2 on x86!");
7999 const unsigned V0Opc = V0.getOpcode();
8000 const unsigned Scale = V0EltSize / EltSize;
8001 const unsigned V0BroadcastIdx = BroadcastIdx / Scale;
8003 if ((V0Opc != ISD::SCALAR_TO_VECTOR || V0BroadcastIdx != 0) &&
8004 V0Opc != ISD::BUILD_VECTOR)
8007 SDValue Scalar = V0.getOperand(V0BroadcastIdx);
8009 // If we're extracting non-least-significant bits, shift so we can truncate.
8010 // Hopefully, we can fold away the trunc/srl/load into the broadcast.
8011 // Even if we can't (and !isShuffleFoldableLoad(Scalar)), prefer
8012 // vpbroadcast+vmovd+shr to vpshufb(m)+vmovd.
8013 if (const int OffsetIdx = BroadcastIdx % Scale)
8014 Scalar = DAG.getNode(ISD::SRL, DL, Scalar.getValueType(), Scalar,
8015 DAG.getConstant(OffsetIdx * EltSize, DL, Scalar.getValueType()));
8017 return DAG.getNode(X86ISD::VBROADCAST, DL, VT,
8018 DAG.getNode(ISD::TRUNCATE, DL, EltVT, Scalar));
8021 /// \brief Try to lower broadcast of a single element.
8023 /// For convenience, this code also bundles all of the subtarget feature set
8024 /// filtering. While a little annoying to re-dispatch on type here, there isn't
8025 /// a convenient way to factor it out.
8026 static SDValue lowerVectorShuffleAsBroadcast(SDLoc DL, MVT VT, SDValue V,
8028 const X86Subtarget *Subtarget,
8029 SelectionDAG &DAG) {
8030 if (!Subtarget->hasAVX())
8032 if (VT.isInteger() && !Subtarget->hasAVX2())
8035 // Check that the mask is a broadcast.
8036 int BroadcastIdx = -1;
8038 if (M >= 0 && BroadcastIdx == -1)
8040 else if (M >= 0 && M != BroadcastIdx)
8043 assert(BroadcastIdx < (int)Mask.size() && "We only expect to be called with "
8044 "a sorted mask where the broadcast "
8047 // Go up the chain of (vector) values to find a scalar load that we can
8048 // combine with the broadcast.
8050 switch (V.getOpcode()) {
8051 case ISD::CONCAT_VECTORS: {
8052 int OperandSize = Mask.size() / V.getNumOperands();
8053 V = V.getOperand(BroadcastIdx / OperandSize);
8054 BroadcastIdx %= OperandSize;
8058 case ISD::INSERT_SUBVECTOR: {
8059 SDValue VOuter = V.getOperand(0), VInner = V.getOperand(1);
8060 auto ConstantIdx = dyn_cast<ConstantSDNode>(V.getOperand(2));
8064 int BeginIdx = (int)ConstantIdx->getZExtValue();
8066 BeginIdx + (int)VInner.getSimpleValueType().getVectorNumElements();
8067 if (BroadcastIdx >= BeginIdx && BroadcastIdx < EndIdx) {
8068 BroadcastIdx -= BeginIdx;
8079 // Check if this is a broadcast of a scalar. We special case lowering
8080 // for scalars so that we can more effectively fold with loads.
8081 // First, look through bitcast: if the original value has a larger element
8082 // type than the shuffle, the broadcast element is in essence truncated.
8083 // Make that explicit to ease folding.
8084 if (V.getOpcode() == ISD::BITCAST && VT.isInteger())
8085 if (SDValue TruncBroadcast = lowerVectorShuffleAsTruncBroadcast(
8086 DL, VT, V.getOperand(0), BroadcastIdx, Subtarget, DAG))
8087 return TruncBroadcast;
8089 // Also check the simpler case, where we can directly reuse the scalar.
8090 if (V.getOpcode() == ISD::BUILD_VECTOR ||
8091 (V.getOpcode() == ISD::SCALAR_TO_VECTOR && BroadcastIdx == 0)) {
8092 V = V.getOperand(BroadcastIdx);
8094 // If the scalar isn't a load, we can't broadcast from it in AVX1.
8095 // Only AVX2 has register broadcasts.
8096 if (!Subtarget->hasAVX2() && !isShuffleFoldableLoad(V))
8098 } else if (BroadcastIdx != 0 || !Subtarget->hasAVX2()) {
8099 // We can't broadcast from a vector register without AVX2, and we can only
8100 // broadcast from the zero-element of a vector register.
8104 return DAG.getNode(X86ISD::VBROADCAST, DL, VT, V);
8107 // Check for whether we can use INSERTPS to perform the shuffle. We only use
8108 // INSERTPS when the V1 elements are already in the correct locations
8109 // because otherwise we can just always use two SHUFPS instructions which
8110 // are much smaller to encode than a SHUFPS and an INSERTPS. We can also
8111 // perform INSERTPS if a single V1 element is out of place and all V2
8112 // elements are zeroable.
8113 static SDValue lowerVectorShuffleAsInsertPS(SDValue Op, SDValue V1, SDValue V2,
8115 SelectionDAG &DAG) {
8116 assert(Op.getSimpleValueType() == MVT::v4f32 && "Bad shuffle type!");
8117 assert(V1.getSimpleValueType() == MVT::v4f32 && "Bad operand type!");
8118 assert(V2.getSimpleValueType() == MVT::v4f32 && "Bad operand type!");
8119 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
8121 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
8124 int V1DstIndex = -1;
8125 int V2DstIndex = -1;
8126 bool V1UsedInPlace = false;
8128 for (int i = 0; i < 4; ++i) {
8129 // Synthesize a zero mask from the zeroable elements (includes undefs).
8135 // Flag if we use any V1 inputs in place.
8137 V1UsedInPlace = true;
8141 // We can only insert a single non-zeroable element.
8142 if (V1DstIndex != -1 || V2DstIndex != -1)
8146 // V1 input out of place for insertion.
8149 // V2 input for insertion.
8154 // Don't bother if we have no (non-zeroable) element for insertion.
8155 if (V1DstIndex == -1 && V2DstIndex == -1)
8158 // Determine element insertion src/dst indices. The src index is from the
8159 // start of the inserted vector, not the start of the concatenated vector.
8160 unsigned V2SrcIndex = 0;
8161 if (V1DstIndex != -1) {
8162 // If we have a V1 input out of place, we use V1 as the V2 element insertion
8163 // and don't use the original V2 at all.
8164 V2SrcIndex = Mask[V1DstIndex];
8165 V2DstIndex = V1DstIndex;
8168 V2SrcIndex = Mask[V2DstIndex] - 4;
8171 // If no V1 inputs are used in place, then the result is created only from
8172 // the zero mask and the V2 insertion - so remove V1 dependency.
8174 V1 = DAG.getUNDEF(MVT::v4f32);
8176 unsigned InsertPSMask = V2SrcIndex << 6 | V2DstIndex << 4 | ZMask;
8177 assert((InsertPSMask & ~0xFFu) == 0 && "Invalid mask!");
8179 // Insert the V2 element into the desired position.
8181 return DAG.getNode(X86ISD::INSERTPS, DL, MVT::v4f32, V1, V2,
8182 DAG.getConstant(InsertPSMask, DL, MVT::i8));
8185 /// \brief Try to lower a shuffle as a permute of the inputs followed by an
8186 /// UNPCK instruction.
8188 /// This specifically targets cases where we end up with alternating between
8189 /// the two inputs, and so can permute them into something that feeds a single
8190 /// UNPCK instruction. Note that this routine only targets integer vectors
8191 /// because for floating point vectors we have a generalized SHUFPS lowering
8192 /// strategy that handles everything that doesn't *exactly* match an unpack,
8193 /// making this clever lowering unnecessary.
8194 static SDValue lowerVectorShuffleAsPermuteAndUnpack(SDLoc DL, MVT VT,
8195 SDValue V1, SDValue V2,
8197 SelectionDAG &DAG) {
8198 assert(!VT.isFloatingPoint() &&
8199 "This routine only supports integer vectors.");
8200 assert(!isSingleInputShuffleMask(Mask) &&
8201 "This routine should only be used when blending two inputs.");
8202 assert(Mask.size() >= 2 && "Single element masks are invalid.");
8204 int Size = Mask.size();
8206 int NumLoInputs = std::count_if(Mask.begin(), Mask.end(), [Size](int M) {
8207 return M >= 0 && M % Size < Size / 2;
8209 int NumHiInputs = std::count_if(
8210 Mask.begin(), Mask.end(), [Size](int M) { return M % Size >= Size / 2; });
8212 bool UnpackLo = NumLoInputs >= NumHiInputs;
8214 auto TryUnpack = [&](MVT UnpackVT, int Scale) {
8215 SmallVector<int, 32> V1Mask(Mask.size(), -1);
8216 SmallVector<int, 32> V2Mask(Mask.size(), -1);
8218 for (int i = 0; i < Size; ++i) {
8222 // Each element of the unpack contains Scale elements from this mask.
8223 int UnpackIdx = i / Scale;
8225 // We only handle the case where V1 feeds the first slots of the unpack.
8226 // We rely on canonicalization to ensure this is the case.
8227 if ((UnpackIdx % 2 == 0) != (Mask[i] < Size))
8230 // Setup the mask for this input. The indexing is tricky as we have to
8231 // handle the unpack stride.
8232 SmallVectorImpl<int> &VMask = (UnpackIdx % 2 == 0) ? V1Mask : V2Mask;
8233 VMask[(UnpackIdx / 2) * Scale + i % Scale + (UnpackLo ? 0 : Size / 2)] =
8237 // If we will have to shuffle both inputs to use the unpack, check whether
8238 // we can just unpack first and shuffle the result. If so, skip this unpack.
8239 if ((NumLoInputs == 0 || NumHiInputs == 0) && !isNoopShuffleMask(V1Mask) &&
8240 !isNoopShuffleMask(V2Mask))
8243 // Shuffle the inputs into place.
8244 V1 = DAG.getVectorShuffle(VT, DL, V1, DAG.getUNDEF(VT), V1Mask);
8245 V2 = DAG.getVectorShuffle(VT, DL, V2, DAG.getUNDEF(VT), V2Mask);
8247 // Cast the inputs to the type we will use to unpack them.
8248 V1 = DAG.getBitcast(UnpackVT, V1);
8249 V2 = DAG.getBitcast(UnpackVT, V2);
8251 // Unpack the inputs and cast the result back to the desired type.
8252 return DAG.getBitcast(
8253 VT, DAG.getNode(UnpackLo ? X86ISD::UNPCKL : X86ISD::UNPCKH, DL,
8257 // We try each unpack from the largest to the smallest to try and find one
8258 // that fits this mask.
8259 int OrigNumElements = VT.getVectorNumElements();
8260 int OrigScalarSize = VT.getScalarSizeInBits();
8261 for (int ScalarSize = 64; ScalarSize >= OrigScalarSize; ScalarSize /= 2) {
8262 int Scale = ScalarSize / OrigScalarSize;
8263 int NumElements = OrigNumElements / Scale;
8264 MVT UnpackVT = MVT::getVectorVT(MVT::getIntegerVT(ScalarSize), NumElements);
8265 if (SDValue Unpack = TryUnpack(UnpackVT, Scale))
8269 // If none of the unpack-rooted lowerings worked (or were profitable) try an
8271 if (NumLoInputs == 0 || NumHiInputs == 0) {
8272 assert((NumLoInputs > 0 || NumHiInputs > 0) &&
8273 "We have to have *some* inputs!");
8274 int HalfOffset = NumLoInputs == 0 ? Size / 2 : 0;
8276 // FIXME: We could consider the total complexity of the permute of each
8277 // possible unpacking. Or at the least we should consider how many
8278 // half-crossings are created.
8279 // FIXME: We could consider commuting the unpacks.
8281 SmallVector<int, 32> PermMask;
8282 PermMask.assign(Size, -1);
8283 for (int i = 0; i < Size; ++i) {
8287 assert(Mask[i] % Size >= HalfOffset && "Found input from wrong half!");
8290 2 * ((Mask[i] % Size) - HalfOffset) + (Mask[i] < Size ? 0 : 1);
8292 return DAG.getVectorShuffle(
8293 VT, DL, DAG.getNode(NumLoInputs == 0 ? X86ISD::UNPCKH : X86ISD::UNPCKL,
8295 DAG.getUNDEF(VT), PermMask);
8301 /// \brief Handle lowering of 2-lane 64-bit floating point shuffles.
8303 /// This is the basis function for the 2-lane 64-bit shuffles as we have full
8304 /// support for floating point shuffles but not integer shuffles. These
8305 /// instructions will incur a domain crossing penalty on some chips though so
8306 /// it is better to avoid lowering through this for integer vectors where
8308 static SDValue lowerV2F64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8309 const X86Subtarget *Subtarget,
8310 SelectionDAG &DAG) {
8312 assert(Op.getSimpleValueType() == MVT::v2f64 && "Bad shuffle type!");
8313 assert(V1.getSimpleValueType() == MVT::v2f64 && "Bad operand type!");
8314 assert(V2.getSimpleValueType() == MVT::v2f64 && "Bad operand type!");
8315 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8316 ArrayRef<int> Mask = SVOp->getMask();
8317 assert(Mask.size() == 2 && "Unexpected mask size for v2 shuffle!");
8319 if (isSingleInputShuffleMask(Mask)) {
8320 // Use low duplicate instructions for masks that match their pattern.
8321 if (Subtarget->hasSSE3())
8322 if (isShuffleEquivalent(V1, V2, Mask, {0, 0}))
8323 return DAG.getNode(X86ISD::MOVDDUP, DL, MVT::v2f64, V1);
8325 // Straight shuffle of a single input vector. Simulate this by using the
8326 // single input as both of the "inputs" to this instruction..
8327 unsigned SHUFPDMask = (Mask[0] == 1) | ((Mask[1] == 1) << 1);
8329 if (Subtarget->hasAVX()) {
8330 // If we have AVX, we can use VPERMILPS which will allow folding a load
8331 // into the shuffle.
8332 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v2f64, V1,
8333 DAG.getConstant(SHUFPDMask, DL, MVT::i8));
8336 return DAG.getNode(X86ISD::SHUFP, DL, MVT::v2f64, V1, V1,
8337 DAG.getConstant(SHUFPDMask, DL, MVT::i8));
8339 assert(Mask[0] >= 0 && Mask[0] < 2 && "Non-canonicalized blend!");
8340 assert(Mask[1] >= 2 && "Non-canonicalized blend!");
8342 // If we have a single input, insert that into V1 if we can do so cheaply.
8343 if ((Mask[0] >= 2) + (Mask[1] >= 2) == 1) {
8344 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
8345 DL, MVT::v2f64, V1, V2, Mask, Subtarget, DAG))
8347 // Try inverting the insertion since for v2 masks it is easy to do and we
8348 // can't reliably sort the mask one way or the other.
8349 int InverseMask[2] = {Mask[0] < 0 ? -1 : (Mask[0] ^ 2),
8350 Mask[1] < 0 ? -1 : (Mask[1] ^ 2)};
8351 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
8352 DL, MVT::v2f64, V2, V1, InverseMask, Subtarget, DAG))
8356 // Try to use one of the special instruction patterns to handle two common
8357 // blend patterns if a zero-blend above didn't work.
8358 if (isShuffleEquivalent(V1, V2, Mask, {0, 3}) ||
8359 isShuffleEquivalent(V1, V2, Mask, {1, 3}))
8360 if (SDValue V1S = getScalarValueForVectorElement(V1, Mask[0], DAG))
8361 // We can either use a special instruction to load over the low double or
8362 // to move just the low double.
8364 isShuffleFoldableLoad(V1S) ? X86ISD::MOVLPD : X86ISD::MOVSD,
8366 DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, MVT::v2f64, V1S));
8368 if (Subtarget->hasSSE41())
8369 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v2f64, V1, V2, Mask,
8373 // Use dedicated unpack instructions for masks that match their pattern.
8375 lowerVectorShuffleWithUNPCK(DL, MVT::v2f64, Mask, V1, V2, DAG))
8378 unsigned SHUFPDMask = (Mask[0] == 1) | (((Mask[1] - 2) == 1) << 1);
8379 return DAG.getNode(X86ISD::SHUFP, DL, MVT::v2f64, V1, V2,
8380 DAG.getConstant(SHUFPDMask, DL, MVT::i8));
8383 /// \brief Handle lowering of 2-lane 64-bit integer shuffles.
8385 /// Tries to lower a 2-lane 64-bit shuffle using shuffle operations provided by
8386 /// the integer unit to minimize domain crossing penalties. However, for blends
8387 /// it falls back to the floating point shuffle operation with appropriate bit
8389 static SDValue lowerV2I64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8390 const X86Subtarget *Subtarget,
8391 SelectionDAG &DAG) {
8393 assert(Op.getSimpleValueType() == MVT::v2i64 && "Bad shuffle type!");
8394 assert(V1.getSimpleValueType() == MVT::v2i64 && "Bad operand type!");
8395 assert(V2.getSimpleValueType() == MVT::v2i64 && "Bad operand type!");
8396 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8397 ArrayRef<int> Mask = SVOp->getMask();
8398 assert(Mask.size() == 2 && "Unexpected mask size for v2 shuffle!");
8400 if (isSingleInputShuffleMask(Mask)) {
8401 // Check for being able to broadcast a single element.
8402 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v2i64, V1,
8403 Mask, Subtarget, DAG))
8406 // Straight shuffle of a single input vector. For everything from SSE2
8407 // onward this has a single fast instruction with no scary immediates.
8408 // We have to map the mask as it is actually a v4i32 shuffle instruction.
8409 V1 = DAG.getBitcast(MVT::v4i32, V1);
8410 int WidenedMask[4] = {
8411 std::max(Mask[0], 0) * 2, std::max(Mask[0], 0) * 2 + 1,
8412 std::max(Mask[1], 0) * 2, std::max(Mask[1], 0) * 2 + 1};
8413 return DAG.getBitcast(
8415 DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32, V1,
8416 getV4X86ShuffleImm8ForMask(WidenedMask, DL, DAG)));
8418 assert(Mask[0] != -1 && "No undef lanes in multi-input v2 shuffles!");
8419 assert(Mask[1] != -1 && "No undef lanes in multi-input v2 shuffles!");
8420 assert(Mask[0] < 2 && "We sort V1 to be the first input.");
8421 assert(Mask[1] >= 2 && "We sort V2 to be the second input.");
8423 // If we have a blend of two PACKUS operations an the blend aligns with the
8424 // low and half halves, we can just merge the PACKUS operations. This is
8425 // particularly important as it lets us merge shuffles that this routine itself
8427 auto GetPackNode = [](SDValue V) {
8428 while (V.getOpcode() == ISD::BITCAST)
8429 V = V.getOperand(0);
8431 return V.getOpcode() == X86ISD::PACKUS ? V : SDValue();
8433 if (SDValue V1Pack = GetPackNode(V1))
8434 if (SDValue V2Pack = GetPackNode(V2))
8435 return DAG.getBitcast(MVT::v2i64,
8436 DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8,
8437 Mask[0] == 0 ? V1Pack.getOperand(0)
8438 : V1Pack.getOperand(1),
8439 Mask[1] == 2 ? V2Pack.getOperand(0)
8440 : V2Pack.getOperand(1)));
8442 // Try to use shift instructions.
8444 lowerVectorShuffleAsShift(DL, MVT::v2i64, V1, V2, Mask, DAG))
8447 // When loading a scalar and then shuffling it into a vector we can often do
8448 // the insertion cheaply.
8449 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
8450 DL, MVT::v2i64, V1, V2, Mask, Subtarget, DAG))
8452 // Try inverting the insertion since for v2 masks it is easy to do and we
8453 // can't reliably sort the mask one way or the other.
8454 int InverseMask[2] = {Mask[0] ^ 2, Mask[1] ^ 2};
8455 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
8456 DL, MVT::v2i64, V2, V1, InverseMask, Subtarget, DAG))
8459 // We have different paths for blend lowering, but they all must use the
8460 // *exact* same predicate.
8461 bool IsBlendSupported = Subtarget->hasSSE41();
8462 if (IsBlendSupported)
8463 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v2i64, V1, V2, Mask,
8467 // Use dedicated unpack instructions for masks that match their pattern.
8469 lowerVectorShuffleWithUNPCK(DL, MVT::v2i64, Mask, V1, V2, DAG))
8472 // Try to use byte rotation instructions.
8473 // Its more profitable for pre-SSSE3 to use shuffles/unpacks.
8474 if (Subtarget->hasSSSE3())
8475 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
8476 DL, MVT::v2i64, V1, V2, Mask, Subtarget, DAG))
8479 // If we have direct support for blends, we should lower by decomposing into
8480 // a permute. That will be faster than the domain cross.
8481 if (IsBlendSupported)
8482 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v2i64, V1, V2,
8485 // We implement this with SHUFPD which is pretty lame because it will likely
8486 // incur 2 cycles of stall for integer vectors on Nehalem and older chips.
8487 // However, all the alternatives are still more cycles and newer chips don't
8488 // have this problem. It would be really nice if x86 had better shuffles here.
8489 V1 = DAG.getBitcast(MVT::v2f64, V1);
8490 V2 = DAG.getBitcast(MVT::v2f64, V2);
8491 return DAG.getBitcast(MVT::v2i64,
8492 DAG.getVectorShuffle(MVT::v2f64, DL, V1, V2, Mask));
8495 /// \brief Test whether this can be lowered with a single SHUFPS instruction.
8497 /// This is used to disable more specialized lowerings when the shufps lowering
8498 /// will happen to be efficient.
8499 static bool isSingleSHUFPSMask(ArrayRef<int> Mask) {
8500 // This routine only handles 128-bit shufps.
8501 assert(Mask.size() == 4 && "Unsupported mask size!");
8503 // To lower with a single SHUFPS we need to have the low half and high half
8504 // each requiring a single input.
8505 if (Mask[0] != -1 && Mask[1] != -1 && (Mask[0] < 4) != (Mask[1] < 4))
8507 if (Mask[2] != -1 && Mask[3] != -1 && (Mask[2] < 4) != (Mask[3] < 4))
8513 /// \brief Lower a vector shuffle using the SHUFPS instruction.
8515 /// This is a helper routine dedicated to lowering vector shuffles using SHUFPS.
8516 /// It makes no assumptions about whether this is the *best* lowering, it simply
8518 static SDValue lowerVectorShuffleWithSHUFPS(SDLoc DL, MVT VT,
8519 ArrayRef<int> Mask, SDValue V1,
8520 SDValue V2, SelectionDAG &DAG) {
8521 SDValue LowV = V1, HighV = V2;
8522 int NewMask[4] = {Mask[0], Mask[1], Mask[2], Mask[3]};
8525 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; });
8527 if (NumV2Elements == 1) {
8529 std::find_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; }) -
8532 // Compute the index adjacent to V2Index and in the same half by toggling
8534 int V2AdjIndex = V2Index ^ 1;
8536 if (Mask[V2AdjIndex] == -1) {
8537 // Handles all the cases where we have a single V2 element and an undef.
8538 // This will only ever happen in the high lanes because we commute the
8539 // vector otherwise.
8541 std::swap(LowV, HighV);
8542 NewMask[V2Index] -= 4;
8544 // Handle the case where the V2 element ends up adjacent to a V1 element.
8545 // To make this work, blend them together as the first step.
8546 int V1Index = V2AdjIndex;
8547 int BlendMask[4] = {Mask[V2Index] - 4, 0, Mask[V1Index], 0};
8548 V2 = DAG.getNode(X86ISD::SHUFP, DL, VT, V2, V1,
8549 getV4X86ShuffleImm8ForMask(BlendMask, DL, DAG));
8551 // Now proceed to reconstruct the final blend as we have the necessary
8552 // high or low half formed.
8559 NewMask[V1Index] = 2; // We put the V1 element in V2[2].
8560 NewMask[V2Index] = 0; // We shifted the V2 element into V2[0].
8562 } else if (NumV2Elements == 2) {
8563 if (Mask[0] < 4 && Mask[1] < 4) {
8564 // Handle the easy case where we have V1 in the low lanes and V2 in the
8568 } else if (Mask[2] < 4 && Mask[3] < 4) {
8569 // We also handle the reversed case because this utility may get called
8570 // when we detect a SHUFPS pattern but can't easily commute the shuffle to
8571 // arrange things in the right direction.
8577 // We have a mixture of V1 and V2 in both low and high lanes. Rather than
8578 // trying to place elements directly, just blend them and set up the final
8579 // shuffle to place them.
8581 // The first two blend mask elements are for V1, the second two are for
8583 int BlendMask[4] = {Mask[0] < 4 ? Mask[0] : Mask[1],
8584 Mask[2] < 4 ? Mask[2] : Mask[3],
8585 (Mask[0] >= 4 ? Mask[0] : Mask[1]) - 4,
8586 (Mask[2] >= 4 ? Mask[2] : Mask[3]) - 4};
8587 V1 = DAG.getNode(X86ISD::SHUFP, DL, VT, V1, V2,
8588 getV4X86ShuffleImm8ForMask(BlendMask, DL, DAG));
8590 // Now we do a normal shuffle of V1 by giving V1 as both operands to
8593 NewMask[0] = Mask[0] < 4 ? 0 : 2;
8594 NewMask[1] = Mask[0] < 4 ? 2 : 0;
8595 NewMask[2] = Mask[2] < 4 ? 1 : 3;
8596 NewMask[3] = Mask[2] < 4 ? 3 : 1;
8599 return DAG.getNode(X86ISD::SHUFP, DL, VT, LowV, HighV,
8600 getV4X86ShuffleImm8ForMask(NewMask, DL, DAG));
8603 /// \brief Lower 4-lane 32-bit floating point shuffles.
8605 /// Uses instructions exclusively from the floating point unit to minimize
8606 /// domain crossing penalties, as these are sufficient to implement all v4f32
8608 static SDValue lowerV4F32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8609 const X86Subtarget *Subtarget,
8610 SelectionDAG &DAG) {
8612 assert(Op.getSimpleValueType() == MVT::v4f32 && "Bad shuffle type!");
8613 assert(V1.getSimpleValueType() == MVT::v4f32 && "Bad operand type!");
8614 assert(V2.getSimpleValueType() == MVT::v4f32 && "Bad operand type!");
8615 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8616 ArrayRef<int> Mask = SVOp->getMask();
8617 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
8620 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; });
8622 if (NumV2Elements == 0) {
8623 // Check for being able to broadcast a single element.
8624 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v4f32, V1,
8625 Mask, Subtarget, DAG))
8628 // Use even/odd duplicate instructions for masks that match their pattern.
8629 if (Subtarget->hasSSE3()) {
8630 if (isShuffleEquivalent(V1, V2, Mask, {0, 0, 2, 2}))
8631 return DAG.getNode(X86ISD::MOVSLDUP, DL, MVT::v4f32, V1);
8632 if (isShuffleEquivalent(V1, V2, Mask, {1, 1, 3, 3}))
8633 return DAG.getNode(X86ISD::MOVSHDUP, DL, MVT::v4f32, V1);
8636 if (Subtarget->hasAVX()) {
8637 // If we have AVX, we can use VPERMILPS which will allow folding a load
8638 // into the shuffle.
8639 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v4f32, V1,
8640 getV4X86ShuffleImm8ForMask(Mask, DL, DAG));
8643 // Otherwise, use a straight shuffle of a single input vector. We pass the
8644 // input vector to both operands to simulate this with a SHUFPS.
8645 return DAG.getNode(X86ISD::SHUFP, DL, MVT::v4f32, V1, V1,
8646 getV4X86ShuffleImm8ForMask(Mask, DL, DAG));
8649 // There are special ways we can lower some single-element blends. However, we
8650 // have custom ways we can lower more complex single-element blends below that
8651 // we defer to if both this and BLENDPS fail to match, so restrict this to
8652 // when the V2 input is targeting element 0 of the mask -- that is the fast
8654 if (NumV2Elements == 1 && Mask[0] >= 4)
8655 if (SDValue V = lowerVectorShuffleAsElementInsertion(DL, MVT::v4f32, V1, V2,
8656 Mask, Subtarget, DAG))
8659 if (Subtarget->hasSSE41()) {
8660 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4f32, V1, V2, Mask,
8664 // Use INSERTPS if we can complete the shuffle efficiently.
8665 if (SDValue V = lowerVectorShuffleAsInsertPS(Op, V1, V2, Mask, DAG))
8668 if (!isSingleSHUFPSMask(Mask))
8669 if (SDValue BlendPerm = lowerVectorShuffleAsBlendAndPermute(
8670 DL, MVT::v4f32, V1, V2, Mask, DAG))
8674 // Use dedicated unpack instructions for masks that match their pattern.
8676 lowerVectorShuffleWithUNPCK(DL, MVT::v4f32, Mask, V1, V2, DAG))
8679 // Otherwise fall back to a SHUFPS lowering strategy.
8680 return lowerVectorShuffleWithSHUFPS(DL, MVT::v4f32, Mask, V1, V2, DAG);
8683 /// \brief Lower 4-lane i32 vector shuffles.
8685 /// We try to handle these with integer-domain shuffles where we can, but for
8686 /// blends we use the floating point domain blend instructions.
8687 static SDValue lowerV4I32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8688 const X86Subtarget *Subtarget,
8689 SelectionDAG &DAG) {
8691 assert(Op.getSimpleValueType() == MVT::v4i32 && "Bad shuffle type!");
8692 assert(V1.getSimpleValueType() == MVT::v4i32 && "Bad operand type!");
8693 assert(V2.getSimpleValueType() == MVT::v4i32 && "Bad operand type!");
8694 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8695 ArrayRef<int> Mask = SVOp->getMask();
8696 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
8698 // Whenever we can lower this as a zext, that instruction is strictly faster
8699 // than any alternative. It also allows us to fold memory operands into the
8700 // shuffle in many cases.
8701 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(DL, MVT::v4i32, V1, V2,
8702 Mask, Subtarget, DAG))
8706 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; });
8708 if (NumV2Elements == 0) {
8709 // Check for being able to broadcast a single element.
8710 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v4i32, V1,
8711 Mask, Subtarget, DAG))
8714 // Straight shuffle of a single input vector. For everything from SSE2
8715 // onward this has a single fast instruction with no scary immediates.
8716 // We coerce the shuffle pattern to be compatible with UNPCK instructions
8717 // but we aren't actually going to use the UNPCK instruction because doing
8718 // so prevents folding a load into this instruction or making a copy.
8719 const int UnpackLoMask[] = {0, 0, 1, 1};
8720 const int UnpackHiMask[] = {2, 2, 3, 3};
8721 if (isShuffleEquivalent(V1, V2, Mask, {0, 0, 1, 1}))
8722 Mask = UnpackLoMask;
8723 else if (isShuffleEquivalent(V1, V2, Mask, {2, 2, 3, 3}))
8724 Mask = UnpackHiMask;
8726 return DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32, V1,
8727 getV4X86ShuffleImm8ForMask(Mask, DL, DAG));
8730 // Try to use shift instructions.
8732 lowerVectorShuffleAsShift(DL, MVT::v4i32, V1, V2, Mask, DAG))
8735 // There are special ways we can lower some single-element blends.
8736 if (NumV2Elements == 1)
8737 if (SDValue V = lowerVectorShuffleAsElementInsertion(DL, MVT::v4i32, V1, V2,
8738 Mask, Subtarget, DAG))
8741 // We have different paths for blend lowering, but they all must use the
8742 // *exact* same predicate.
8743 bool IsBlendSupported = Subtarget->hasSSE41();
8744 if (IsBlendSupported)
8745 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4i32, V1, V2, Mask,
8749 if (SDValue Masked =
8750 lowerVectorShuffleAsBitMask(DL, MVT::v4i32, V1, V2, Mask, DAG))
8753 // Use dedicated unpack instructions for masks that match their pattern.
8755 lowerVectorShuffleWithUNPCK(DL, MVT::v4i32, Mask, V1, V2, DAG))
8758 // Try to use byte rotation instructions.
8759 // Its more profitable for pre-SSSE3 to use shuffles/unpacks.
8760 if (Subtarget->hasSSSE3())
8761 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
8762 DL, MVT::v4i32, V1, V2, Mask, Subtarget, DAG))
8765 // If we have direct support for blends, we should lower by decomposing into
8766 // a permute. That will be faster than the domain cross.
8767 if (IsBlendSupported)
8768 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v4i32, V1, V2,
8771 // Try to lower by permuting the inputs into an unpack instruction.
8772 if (SDValue Unpack = lowerVectorShuffleAsPermuteAndUnpack(DL, MVT::v4i32, V1,
8776 // We implement this with SHUFPS because it can blend from two vectors.
8777 // Because we're going to eventually use SHUFPS, we use SHUFPS even to build
8778 // up the inputs, bypassing domain shift penalties that we would encur if we
8779 // directly used PSHUFD on Nehalem and older. For newer chips, this isn't
8781 return DAG.getBitcast(
8783 DAG.getVectorShuffle(MVT::v4f32, DL, DAG.getBitcast(MVT::v4f32, V1),
8784 DAG.getBitcast(MVT::v4f32, V2), Mask));
8787 /// \brief Lowering of single-input v8i16 shuffles is the cornerstone of SSE2
8788 /// shuffle lowering, and the most complex part.
8790 /// The lowering strategy is to try to form pairs of input lanes which are
8791 /// targeted at the same half of the final vector, and then use a dword shuffle
8792 /// to place them onto the right half, and finally unpack the paired lanes into
8793 /// their final position.
8795 /// The exact breakdown of how to form these dword pairs and align them on the
8796 /// correct sides is really tricky. See the comments within the function for
8797 /// more of the details.
8799 /// This code also handles repeated 128-bit lanes of v8i16 shuffles, but each
8800 /// lane must shuffle the *exact* same way. In fact, you must pass a v8 Mask to
8801 /// this routine for it to work correctly. To shuffle a 256-bit or 512-bit i16
8802 /// vector, form the analogous 128-bit 8-element Mask.
8803 static SDValue lowerV8I16GeneralSingleInputVectorShuffle(
8804 SDLoc DL, MVT VT, SDValue V, MutableArrayRef<int> Mask,
8805 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
8806 assert(VT.getVectorElementType() == MVT::i16 && "Bad input type!");
8807 MVT PSHUFDVT = MVT::getVectorVT(MVT::i32, VT.getVectorNumElements() / 2);
8809 assert(Mask.size() == 8 && "Shuffle mask length doen't match!");
8810 MutableArrayRef<int> LoMask = Mask.slice(0, 4);
8811 MutableArrayRef<int> HiMask = Mask.slice(4, 4);
8813 SmallVector<int, 4> LoInputs;
8814 std::copy_if(LoMask.begin(), LoMask.end(), std::back_inserter(LoInputs),
8815 [](int M) { return M >= 0; });
8816 std::sort(LoInputs.begin(), LoInputs.end());
8817 LoInputs.erase(std::unique(LoInputs.begin(), LoInputs.end()), LoInputs.end());
8818 SmallVector<int, 4> HiInputs;
8819 std::copy_if(HiMask.begin(), HiMask.end(), std::back_inserter(HiInputs),
8820 [](int M) { return M >= 0; });
8821 std::sort(HiInputs.begin(), HiInputs.end());
8822 HiInputs.erase(std::unique(HiInputs.begin(), HiInputs.end()), HiInputs.end());
8824 std::lower_bound(LoInputs.begin(), LoInputs.end(), 4) - LoInputs.begin();
8825 int NumHToL = LoInputs.size() - NumLToL;
8827 std::lower_bound(HiInputs.begin(), HiInputs.end(), 4) - HiInputs.begin();
8828 int NumHToH = HiInputs.size() - NumLToH;
8829 MutableArrayRef<int> LToLInputs(LoInputs.data(), NumLToL);
8830 MutableArrayRef<int> LToHInputs(HiInputs.data(), NumLToH);
8831 MutableArrayRef<int> HToLInputs(LoInputs.data() + NumLToL, NumHToL);
8832 MutableArrayRef<int> HToHInputs(HiInputs.data() + NumLToH, NumHToH);
8834 // Simplify the 1-into-3 and 3-into-1 cases with a single pshufd. For all
8835 // such inputs we can swap two of the dwords across the half mark and end up
8836 // with <=2 inputs to each half in each half. Once there, we can fall through
8837 // to the generic code below. For example:
8839 // Input: [a, b, c, d, e, f, g, h] -PSHUFD[0,2,1,3]-> [a, b, e, f, c, d, g, h]
8840 // Mask: [0, 1, 2, 7, 4, 5, 6, 3] -----------------> [0, 1, 4, 7, 2, 3, 6, 5]
8842 // However in some very rare cases we have a 1-into-3 or 3-into-1 on one half
8843 // and an existing 2-into-2 on the other half. In this case we may have to
8844 // pre-shuffle the 2-into-2 half to avoid turning it into a 3-into-1 or
8845 // 1-into-3 which could cause us to cycle endlessly fixing each side in turn.
8846 // Fortunately, we don't have to handle anything but a 2-into-2 pattern
8847 // because any other situation (including a 3-into-1 or 1-into-3 in the other
8848 // half than the one we target for fixing) will be fixed when we re-enter this
8849 // path. We will also combine away any sequence of PSHUFD instructions that
8850 // result into a single instruction. Here is an example of the tricky case:
8852 // Input: [a, b, c, d, e, f, g, h] -PSHUFD[0,2,1,3]-> [a, b, e, f, c, d, g, h]
8853 // Mask: [3, 7, 1, 0, 2, 7, 3, 5] -THIS-IS-BAD!!!!-> [5, 7, 1, 0, 4, 7, 5, 3]
8855 // This now has a 1-into-3 in the high half! Instead, we do two shuffles:
8857 // Input: [a, b, c, d, e, f, g, h] PSHUFHW[0,2,1,3]-> [a, b, c, d, e, g, f, h]
8858 // Mask: [3, 7, 1, 0, 2, 7, 3, 5] -----------------> [3, 7, 1, 0, 2, 7, 3, 6]
8860 // Input: [a, b, c, d, e, g, f, h] -PSHUFD[0,2,1,3]-> [a, b, e, g, c, d, f, h]
8861 // Mask: [3, 7, 1, 0, 2, 7, 3, 6] -----------------> [5, 7, 1, 0, 4, 7, 5, 6]
8863 // The result is fine to be handled by the generic logic.
8864 auto balanceSides = [&](ArrayRef<int> AToAInputs, ArrayRef<int> BToAInputs,
8865 ArrayRef<int> BToBInputs, ArrayRef<int> AToBInputs,
8866 int AOffset, int BOffset) {
8867 assert((AToAInputs.size() == 3 || AToAInputs.size() == 1) &&
8868 "Must call this with A having 3 or 1 inputs from the A half.");
8869 assert((BToAInputs.size() == 1 || BToAInputs.size() == 3) &&
8870 "Must call this with B having 1 or 3 inputs from the B half.");
8871 assert(AToAInputs.size() + BToAInputs.size() == 4 &&
8872 "Must call this with either 3:1 or 1:3 inputs (summing to 4).");
8874 bool ThreeAInputs = AToAInputs.size() == 3;
8876 // Compute the index of dword with only one word among the three inputs in
8877 // a half by taking the sum of the half with three inputs and subtracting
8878 // the sum of the actual three inputs. The difference is the remaining
8881 int &TripleDWord = ThreeAInputs ? ADWord : BDWord;
8882 int &OneInputDWord = ThreeAInputs ? BDWord : ADWord;
8883 int TripleInputOffset = ThreeAInputs ? AOffset : BOffset;
8884 ArrayRef<int> TripleInputs = ThreeAInputs ? AToAInputs : BToAInputs;
8885 int OneInput = ThreeAInputs ? BToAInputs[0] : AToAInputs[0];
8886 int TripleInputSum = 0 + 1 + 2 + 3 + (4 * TripleInputOffset);
8887 int TripleNonInputIdx =
8888 TripleInputSum - std::accumulate(TripleInputs.begin(), TripleInputs.end(), 0);
8889 TripleDWord = TripleNonInputIdx / 2;
8891 // We use xor with one to compute the adjacent DWord to whichever one the
8893 OneInputDWord = (OneInput / 2) ^ 1;
8895 // Check for one tricky case: We're fixing a 3<-1 or a 1<-3 shuffle for AToA
8896 // and BToA inputs. If there is also such a problem with the BToB and AToB
8897 // inputs, we don't try to fix it necessarily -- we'll recurse and see it in
8898 // the next pass. However, if we have a 2<-2 in the BToB and AToB inputs, it
8899 // is essential that we don't *create* a 3<-1 as then we might oscillate.
8900 if (BToBInputs.size() == 2 && AToBInputs.size() == 2) {
8901 // Compute how many inputs will be flipped by swapping these DWords. We
8903 // to balance this to ensure we don't form a 3-1 shuffle in the other
8905 int NumFlippedAToBInputs =
8906 std::count(AToBInputs.begin(), AToBInputs.end(), 2 * ADWord) +
8907 std::count(AToBInputs.begin(), AToBInputs.end(), 2 * ADWord + 1);
8908 int NumFlippedBToBInputs =
8909 std::count(BToBInputs.begin(), BToBInputs.end(), 2 * BDWord) +
8910 std::count(BToBInputs.begin(), BToBInputs.end(), 2 * BDWord + 1);
8911 if ((NumFlippedAToBInputs == 1 &&
8912 (NumFlippedBToBInputs == 0 || NumFlippedBToBInputs == 2)) ||
8913 (NumFlippedBToBInputs == 1 &&
8914 (NumFlippedAToBInputs == 0 || NumFlippedAToBInputs == 2))) {
8915 // We choose whether to fix the A half or B half based on whether that
8916 // half has zero flipped inputs. At zero, we may not be able to fix it
8917 // with that half. We also bias towards fixing the B half because that
8918 // will more commonly be the high half, and we have to bias one way.
8919 auto FixFlippedInputs = [&V, &DL, &Mask, &DAG](int PinnedIdx, int DWord,
8920 ArrayRef<int> Inputs) {
8921 int FixIdx = PinnedIdx ^ 1; // The adjacent slot to the pinned slot.
8922 bool IsFixIdxInput = std::find(Inputs.begin(), Inputs.end(),
8923 PinnedIdx ^ 1) != Inputs.end();
8924 // Determine whether the free index is in the flipped dword or the
8925 // unflipped dword based on where the pinned index is. We use this bit
8926 // in an xor to conditionally select the adjacent dword.
8927 int FixFreeIdx = 2 * (DWord ^ (PinnedIdx / 2 == DWord));
8928 bool IsFixFreeIdxInput = std::find(Inputs.begin(), Inputs.end(),
8929 FixFreeIdx) != Inputs.end();
8930 if (IsFixIdxInput == IsFixFreeIdxInput)
8932 IsFixFreeIdxInput = std::find(Inputs.begin(), Inputs.end(),
8933 FixFreeIdx) != Inputs.end();
8934 assert(IsFixIdxInput != IsFixFreeIdxInput &&
8935 "We need to be changing the number of flipped inputs!");
8936 int PSHUFHalfMask[] = {0, 1, 2, 3};
8937 std::swap(PSHUFHalfMask[FixFreeIdx % 4], PSHUFHalfMask[FixIdx % 4]);
8938 V = DAG.getNode(FixIdx < 4 ? X86ISD::PSHUFLW : X86ISD::PSHUFHW, DL,
8940 getV4X86ShuffleImm8ForMask(PSHUFHalfMask, DL, DAG));
8943 if (M != -1 && M == FixIdx)
8945 else if (M != -1 && M == FixFreeIdx)
8948 if (NumFlippedBToBInputs != 0) {
8950 BToAInputs.size() == 3 ? TripleNonInputIdx : OneInput;
8951 FixFlippedInputs(BPinnedIdx, BDWord, BToBInputs);
8953 assert(NumFlippedAToBInputs != 0 && "Impossible given predicates!");
8954 int APinnedIdx = ThreeAInputs ? TripleNonInputIdx : OneInput;
8955 FixFlippedInputs(APinnedIdx, ADWord, AToBInputs);
8960 int PSHUFDMask[] = {0, 1, 2, 3};
8961 PSHUFDMask[ADWord] = BDWord;
8962 PSHUFDMask[BDWord] = ADWord;
8965 DAG.getNode(X86ISD::PSHUFD, DL, PSHUFDVT, DAG.getBitcast(PSHUFDVT, V),
8966 getV4X86ShuffleImm8ForMask(PSHUFDMask, DL, DAG)));
8968 // Adjust the mask to match the new locations of A and B.
8970 if (M != -1 && M/2 == ADWord)
8971 M = 2 * BDWord + M % 2;
8972 else if (M != -1 && M/2 == BDWord)
8973 M = 2 * ADWord + M % 2;
8975 // Recurse back into this routine to re-compute state now that this isn't
8976 // a 3 and 1 problem.
8977 return lowerV8I16GeneralSingleInputVectorShuffle(DL, VT, V, Mask, Subtarget,
8980 if ((NumLToL == 3 && NumHToL == 1) || (NumLToL == 1 && NumHToL == 3))
8981 return balanceSides(LToLInputs, HToLInputs, HToHInputs, LToHInputs, 0, 4);
8982 else if ((NumHToH == 3 && NumLToH == 1) || (NumHToH == 1 && NumLToH == 3))
8983 return balanceSides(HToHInputs, LToHInputs, LToLInputs, HToLInputs, 4, 0);
8985 // At this point there are at most two inputs to the low and high halves from
8986 // each half. That means the inputs can always be grouped into dwords and
8987 // those dwords can then be moved to the correct half with a dword shuffle.
8988 // We use at most one low and one high word shuffle to collect these paired
8989 // inputs into dwords, and finally a dword shuffle to place them.
8990 int PSHUFLMask[4] = {-1, -1, -1, -1};
8991 int PSHUFHMask[4] = {-1, -1, -1, -1};
8992 int PSHUFDMask[4] = {-1, -1, -1, -1};
8994 // First fix the masks for all the inputs that are staying in their
8995 // original halves. This will then dictate the targets of the cross-half
8997 auto fixInPlaceInputs =
8998 [&PSHUFDMask](ArrayRef<int> InPlaceInputs, ArrayRef<int> IncomingInputs,
8999 MutableArrayRef<int> SourceHalfMask,
9000 MutableArrayRef<int> HalfMask, int HalfOffset) {
9001 if (InPlaceInputs.empty())
9003 if (InPlaceInputs.size() == 1) {
9004 SourceHalfMask[InPlaceInputs[0] - HalfOffset] =
9005 InPlaceInputs[0] - HalfOffset;
9006 PSHUFDMask[InPlaceInputs[0] / 2] = InPlaceInputs[0] / 2;
9009 if (IncomingInputs.empty()) {
9010 // Just fix all of the in place inputs.
9011 for (int Input : InPlaceInputs) {
9012 SourceHalfMask[Input - HalfOffset] = Input - HalfOffset;
9013 PSHUFDMask[Input / 2] = Input / 2;
9018 assert(InPlaceInputs.size() == 2 && "Cannot handle 3 or 4 inputs!");
9019 SourceHalfMask[InPlaceInputs[0] - HalfOffset] =
9020 InPlaceInputs[0] - HalfOffset;
9021 // Put the second input next to the first so that they are packed into
9022 // a dword. We find the adjacent index by toggling the low bit.
9023 int AdjIndex = InPlaceInputs[0] ^ 1;
9024 SourceHalfMask[AdjIndex - HalfOffset] = InPlaceInputs[1] - HalfOffset;
9025 std::replace(HalfMask.begin(), HalfMask.end(), InPlaceInputs[1], AdjIndex);
9026 PSHUFDMask[AdjIndex / 2] = AdjIndex / 2;
9028 fixInPlaceInputs(LToLInputs, HToLInputs, PSHUFLMask, LoMask, 0);
9029 fixInPlaceInputs(HToHInputs, LToHInputs, PSHUFHMask, HiMask, 4);
9031 // Now gather the cross-half inputs and place them into a free dword of
9032 // their target half.
9033 // FIXME: This operation could almost certainly be simplified dramatically to
9034 // look more like the 3-1 fixing operation.
9035 auto moveInputsToRightHalf = [&PSHUFDMask](
9036 MutableArrayRef<int> IncomingInputs, ArrayRef<int> ExistingInputs,
9037 MutableArrayRef<int> SourceHalfMask, MutableArrayRef<int> HalfMask,
9038 MutableArrayRef<int> FinalSourceHalfMask, int SourceOffset,
9040 auto isWordClobbered = [](ArrayRef<int> SourceHalfMask, int Word) {
9041 return SourceHalfMask[Word] != -1 && SourceHalfMask[Word] != Word;
9043 auto isDWordClobbered = [&isWordClobbered](ArrayRef<int> SourceHalfMask,
9045 int LowWord = Word & ~1;
9046 int HighWord = Word | 1;
9047 return isWordClobbered(SourceHalfMask, LowWord) ||
9048 isWordClobbered(SourceHalfMask, HighWord);
9051 if (IncomingInputs.empty())
9054 if (ExistingInputs.empty()) {
9055 // Map any dwords with inputs from them into the right half.
9056 for (int Input : IncomingInputs) {
9057 // If the source half mask maps over the inputs, turn those into
9058 // swaps and use the swapped lane.
9059 if (isWordClobbered(SourceHalfMask, Input - SourceOffset)) {
9060 if (SourceHalfMask[SourceHalfMask[Input - SourceOffset]] == -1) {
9061 SourceHalfMask[SourceHalfMask[Input - SourceOffset]] =
9062 Input - SourceOffset;
9063 // We have to swap the uses in our half mask in one sweep.
9064 for (int &M : HalfMask)
9065 if (M == SourceHalfMask[Input - SourceOffset] + SourceOffset)
9067 else if (M == Input)
9068 M = SourceHalfMask[Input - SourceOffset] + SourceOffset;
9070 assert(SourceHalfMask[SourceHalfMask[Input - SourceOffset]] ==
9071 Input - SourceOffset &&
9072 "Previous placement doesn't match!");
9074 // Note that this correctly re-maps both when we do a swap and when
9075 // we observe the other side of the swap above. We rely on that to
9076 // avoid swapping the members of the input list directly.
9077 Input = SourceHalfMask[Input - SourceOffset] + SourceOffset;
9080 // Map the input's dword into the correct half.
9081 if (PSHUFDMask[(Input - SourceOffset + DestOffset) / 2] == -1)
9082 PSHUFDMask[(Input - SourceOffset + DestOffset) / 2] = Input / 2;
9084 assert(PSHUFDMask[(Input - SourceOffset + DestOffset) / 2] ==
9086 "Previous placement doesn't match!");
9089 // And just directly shift any other-half mask elements to be same-half
9090 // as we will have mirrored the dword containing the element into the
9091 // same position within that half.
9092 for (int &M : HalfMask)
9093 if (M >= SourceOffset && M < SourceOffset + 4) {
9094 M = M - SourceOffset + DestOffset;
9095 assert(M >= 0 && "This should never wrap below zero!");
9100 // Ensure we have the input in a viable dword of its current half. This
9101 // is particularly tricky because the original position may be clobbered
9102 // by inputs being moved and *staying* in that half.
9103 if (IncomingInputs.size() == 1) {
9104 if (isWordClobbered(SourceHalfMask, IncomingInputs[0] - SourceOffset)) {
9105 int InputFixed = std::find(std::begin(SourceHalfMask),
9106 std::end(SourceHalfMask), -1) -
9107 std::begin(SourceHalfMask) + SourceOffset;
9108 SourceHalfMask[InputFixed - SourceOffset] =
9109 IncomingInputs[0] - SourceOffset;
9110 std::replace(HalfMask.begin(), HalfMask.end(), IncomingInputs[0],
9112 IncomingInputs[0] = InputFixed;
9114 } else if (IncomingInputs.size() == 2) {
9115 if (IncomingInputs[0] / 2 != IncomingInputs[1] / 2 ||
9116 isDWordClobbered(SourceHalfMask, IncomingInputs[0] - SourceOffset)) {
9117 // We have two non-adjacent or clobbered inputs we need to extract from
9118 // the source half. To do this, we need to map them into some adjacent
9119 // dword slot in the source mask.
9120 int InputsFixed[2] = {IncomingInputs[0] - SourceOffset,
9121 IncomingInputs[1] - SourceOffset};
9123 // If there is a free slot in the source half mask adjacent to one of
9124 // the inputs, place the other input in it. We use (Index XOR 1) to
9125 // compute an adjacent index.
9126 if (!isWordClobbered(SourceHalfMask, InputsFixed[0]) &&
9127 SourceHalfMask[InputsFixed[0] ^ 1] == -1) {
9128 SourceHalfMask[InputsFixed[0]] = InputsFixed[0];
9129 SourceHalfMask[InputsFixed[0] ^ 1] = InputsFixed[1];
9130 InputsFixed[1] = InputsFixed[0] ^ 1;
9131 } else if (!isWordClobbered(SourceHalfMask, InputsFixed[1]) &&
9132 SourceHalfMask[InputsFixed[1] ^ 1] == -1) {
9133 SourceHalfMask[InputsFixed[1]] = InputsFixed[1];
9134 SourceHalfMask[InputsFixed[1] ^ 1] = InputsFixed[0];
9135 InputsFixed[0] = InputsFixed[1] ^ 1;
9136 } else if (SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1)] == -1 &&
9137 SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1) + 1] == -1) {
9138 // The two inputs are in the same DWord but it is clobbered and the
9139 // adjacent DWord isn't used at all. Move both inputs to the free
9141 SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1)] = InputsFixed[0];
9142 SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1) + 1] = InputsFixed[1];
9143 InputsFixed[0] = 2 * ((InputsFixed[0] / 2) ^ 1);
9144 InputsFixed[1] = 2 * ((InputsFixed[0] / 2) ^ 1) + 1;
9146 // The only way we hit this point is if there is no clobbering
9147 // (because there are no off-half inputs to this half) and there is no
9148 // free slot adjacent to one of the inputs. In this case, we have to
9149 // swap an input with a non-input.
9150 for (int i = 0; i < 4; ++i)
9151 assert((SourceHalfMask[i] == -1 || SourceHalfMask[i] == i) &&
9152 "We can't handle any clobbers here!");
9153 assert(InputsFixed[1] != (InputsFixed[0] ^ 1) &&
9154 "Cannot have adjacent inputs here!");
9156 SourceHalfMask[InputsFixed[0] ^ 1] = InputsFixed[1];
9157 SourceHalfMask[InputsFixed[1]] = InputsFixed[0] ^ 1;
9159 // We also have to update the final source mask in this case because
9160 // it may need to undo the above swap.
9161 for (int &M : FinalSourceHalfMask)
9162 if (M == (InputsFixed[0] ^ 1) + SourceOffset)
9163 M = InputsFixed[1] + SourceOffset;
9164 else if (M == InputsFixed[1] + SourceOffset)
9165 M = (InputsFixed[0] ^ 1) + SourceOffset;
9167 InputsFixed[1] = InputsFixed[0] ^ 1;
9170 // Point everything at the fixed inputs.
9171 for (int &M : HalfMask)
9172 if (M == IncomingInputs[0])
9173 M = InputsFixed[0] + SourceOffset;
9174 else if (M == IncomingInputs[1])
9175 M = InputsFixed[1] + SourceOffset;
9177 IncomingInputs[0] = InputsFixed[0] + SourceOffset;
9178 IncomingInputs[1] = InputsFixed[1] + SourceOffset;
9181 llvm_unreachable("Unhandled input size!");
9184 // Now hoist the DWord down to the right half.
9185 int FreeDWord = (PSHUFDMask[DestOffset / 2] == -1 ? 0 : 1) + DestOffset / 2;
9186 assert(PSHUFDMask[FreeDWord] == -1 && "DWord not free");
9187 PSHUFDMask[FreeDWord] = IncomingInputs[0] / 2;
9188 for (int &M : HalfMask)
9189 for (int Input : IncomingInputs)
9191 M = FreeDWord * 2 + Input % 2;
9193 moveInputsToRightHalf(HToLInputs, LToLInputs, PSHUFHMask, LoMask, HiMask,
9194 /*SourceOffset*/ 4, /*DestOffset*/ 0);
9195 moveInputsToRightHalf(LToHInputs, HToHInputs, PSHUFLMask, HiMask, LoMask,
9196 /*SourceOffset*/ 0, /*DestOffset*/ 4);
9198 // Now enact all the shuffles we've computed to move the inputs into their
9200 if (!isNoopShuffleMask(PSHUFLMask))
9201 V = DAG.getNode(X86ISD::PSHUFLW, DL, VT, V,
9202 getV4X86ShuffleImm8ForMask(PSHUFLMask, DL, DAG));
9203 if (!isNoopShuffleMask(PSHUFHMask))
9204 V = DAG.getNode(X86ISD::PSHUFHW, DL, VT, V,
9205 getV4X86ShuffleImm8ForMask(PSHUFHMask, DL, DAG));
9206 if (!isNoopShuffleMask(PSHUFDMask))
9209 DAG.getNode(X86ISD::PSHUFD, DL, PSHUFDVT, DAG.getBitcast(PSHUFDVT, V),
9210 getV4X86ShuffleImm8ForMask(PSHUFDMask, DL, DAG)));
9212 // At this point, each half should contain all its inputs, and we can then
9213 // just shuffle them into their final position.
9214 assert(std::count_if(LoMask.begin(), LoMask.end(),
9215 [](int M) { return M >= 4; }) == 0 &&
9216 "Failed to lift all the high half inputs to the low mask!");
9217 assert(std::count_if(HiMask.begin(), HiMask.end(),
9218 [](int M) { return M >= 0 && M < 4; }) == 0 &&
9219 "Failed to lift all the low half inputs to the high mask!");
9221 // Do a half shuffle for the low mask.
9222 if (!isNoopShuffleMask(LoMask))
9223 V = DAG.getNode(X86ISD::PSHUFLW, DL, VT, V,
9224 getV4X86ShuffleImm8ForMask(LoMask, DL, DAG));
9226 // Do a half shuffle with the high mask after shifting its values down.
9227 for (int &M : HiMask)
9230 if (!isNoopShuffleMask(HiMask))
9231 V = DAG.getNode(X86ISD::PSHUFHW, DL, VT, V,
9232 getV4X86ShuffleImm8ForMask(HiMask, DL, DAG));
9237 /// \brief Helper to form a PSHUFB-based shuffle+blend.
9238 static SDValue lowerVectorShuffleAsPSHUFB(SDLoc DL, MVT VT, SDValue V1,
9239 SDValue V2, ArrayRef<int> Mask,
9240 SelectionDAG &DAG, bool &V1InUse,
9242 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
9248 int Size = Mask.size();
9249 int Scale = 16 / Size;
9250 for (int i = 0; i < 16; ++i) {
9251 if (Mask[i / Scale] == -1) {
9252 V1Mask[i] = V2Mask[i] = DAG.getUNDEF(MVT::i8);
9254 const int ZeroMask = 0x80;
9255 int V1Idx = Mask[i / Scale] < Size ? Mask[i / Scale] * Scale + i % Scale
9257 int V2Idx = Mask[i / Scale] < Size
9259 : (Mask[i / Scale] - Size) * Scale + i % Scale;
9260 if (Zeroable[i / Scale])
9261 V1Idx = V2Idx = ZeroMask;
9262 V1Mask[i] = DAG.getConstant(V1Idx, DL, MVT::i8);
9263 V2Mask[i] = DAG.getConstant(V2Idx, DL, MVT::i8);
9264 V1InUse |= (ZeroMask != V1Idx);
9265 V2InUse |= (ZeroMask != V2Idx);
9270 V1 = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8,
9271 DAG.getBitcast(MVT::v16i8, V1),
9272 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v16i8, V1Mask));
9274 V2 = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8,
9275 DAG.getBitcast(MVT::v16i8, V2),
9276 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v16i8, V2Mask));
9278 // If we need shuffled inputs from both, blend the two.
9280 if (V1InUse && V2InUse)
9281 V = DAG.getNode(ISD::OR, DL, MVT::v16i8, V1, V2);
9283 V = V1InUse ? V1 : V2;
9285 // Cast the result back to the correct type.
9286 return DAG.getBitcast(VT, V);
9289 /// \brief Generic lowering of 8-lane i16 shuffles.
9291 /// This handles both single-input shuffles and combined shuffle/blends with
9292 /// two inputs. The single input shuffles are immediately delegated to
9293 /// a dedicated lowering routine.
9295 /// The blends are lowered in one of three fundamental ways. If there are few
9296 /// enough inputs, it delegates to a basic UNPCK-based strategy. If the shuffle
9297 /// of the input is significantly cheaper when lowered as an interleaving of
9298 /// the two inputs, try to interleave them. Otherwise, blend the low and high
9299 /// halves of the inputs separately (making them have relatively few inputs)
9300 /// and then concatenate them.
9301 static SDValue lowerV8I16VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9302 const X86Subtarget *Subtarget,
9303 SelectionDAG &DAG) {
9305 assert(Op.getSimpleValueType() == MVT::v8i16 && "Bad shuffle type!");
9306 assert(V1.getSimpleValueType() == MVT::v8i16 && "Bad operand type!");
9307 assert(V2.getSimpleValueType() == MVT::v8i16 && "Bad operand type!");
9308 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9309 ArrayRef<int> OrigMask = SVOp->getMask();
9310 int MaskStorage[8] = {OrigMask[0], OrigMask[1], OrigMask[2], OrigMask[3],
9311 OrigMask[4], OrigMask[5], OrigMask[6], OrigMask[7]};
9312 MutableArrayRef<int> Mask(MaskStorage);
9314 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
9316 // Whenever we can lower this as a zext, that instruction is strictly faster
9317 // than any alternative.
9318 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(
9319 DL, MVT::v8i16, V1, V2, OrigMask, Subtarget, DAG))
9322 auto isV1 = [](int M) { return M >= 0 && M < 8; };
9324 auto isV2 = [](int M) { return M >= 8; };
9326 int NumV2Inputs = std::count_if(Mask.begin(), Mask.end(), isV2);
9328 if (NumV2Inputs == 0) {
9329 // Check for being able to broadcast a single element.
9330 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v8i16, V1,
9331 Mask, Subtarget, DAG))
9334 // Try to use shift instructions.
9336 lowerVectorShuffleAsShift(DL, MVT::v8i16, V1, V1, Mask, DAG))
9339 // Use dedicated unpack instructions for masks that match their pattern.
9341 lowerVectorShuffleWithUNPCK(DL, MVT::v8i16, Mask, V1, V2, DAG))
9344 // Try to use byte rotation instructions.
9345 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(DL, MVT::v8i16, V1, V1,
9346 Mask, Subtarget, DAG))
9349 return lowerV8I16GeneralSingleInputVectorShuffle(DL, MVT::v8i16, V1, Mask,
9353 assert(std::any_of(Mask.begin(), Mask.end(), isV1) &&
9354 "All single-input shuffles should be canonicalized to be V1-input "
9357 // Try to use shift instructions.
9359 lowerVectorShuffleAsShift(DL, MVT::v8i16, V1, V2, Mask, DAG))
9362 // See if we can use SSE4A Extraction / Insertion.
9363 if (Subtarget->hasSSE4A())
9364 if (SDValue V = lowerVectorShuffleWithSSE4A(DL, MVT::v8i16, V1, V2, Mask, DAG))
9367 // There are special ways we can lower some single-element blends.
9368 if (NumV2Inputs == 1)
9369 if (SDValue V = lowerVectorShuffleAsElementInsertion(DL, MVT::v8i16, V1, V2,
9370 Mask, Subtarget, DAG))
9373 // We have different paths for blend lowering, but they all must use the
9374 // *exact* same predicate.
9375 bool IsBlendSupported = Subtarget->hasSSE41();
9376 if (IsBlendSupported)
9377 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v8i16, V1, V2, Mask,
9381 if (SDValue Masked =
9382 lowerVectorShuffleAsBitMask(DL, MVT::v8i16, V1, V2, Mask, DAG))
9385 // Use dedicated unpack instructions for masks that match their pattern.
9387 lowerVectorShuffleWithUNPCK(DL, MVT::v8i16, Mask, V1, V2, DAG))
9390 // Try to use byte rotation instructions.
9391 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
9392 DL, MVT::v8i16, V1, V2, Mask, Subtarget, DAG))
9395 if (SDValue BitBlend =
9396 lowerVectorShuffleAsBitBlend(DL, MVT::v8i16, V1, V2, Mask, DAG))
9399 if (SDValue Unpack = lowerVectorShuffleAsPermuteAndUnpack(DL, MVT::v8i16, V1,
9403 // If we can't directly blend but can use PSHUFB, that will be better as it
9404 // can both shuffle and set up the inefficient blend.
9405 if (!IsBlendSupported && Subtarget->hasSSSE3()) {
9406 bool V1InUse, V2InUse;
9407 return lowerVectorShuffleAsPSHUFB(DL, MVT::v8i16, V1, V2, Mask, DAG,
9411 // We can always bit-blend if we have to so the fallback strategy is to
9412 // decompose into single-input permutes and blends.
9413 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v8i16, V1, V2,
9417 /// \brief Check whether a compaction lowering can be done by dropping even
9418 /// elements and compute how many times even elements must be dropped.
9420 /// This handles shuffles which take every Nth element where N is a power of
9421 /// two. Example shuffle masks:
9423 /// N = 1: 0, 2, 4, 6, 8, 10, 12, 14, 0, 2, 4, 6, 8, 10, 12, 14
9424 /// N = 1: 0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30
9425 /// N = 2: 0, 4, 8, 12, 0, 4, 8, 12, 0, 4, 8, 12, 0, 4, 8, 12
9426 /// N = 2: 0, 4, 8, 12, 16, 20, 24, 28, 0, 4, 8, 12, 16, 20, 24, 28
9427 /// N = 3: 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 0, 8
9428 /// N = 3: 0, 8, 16, 24, 0, 8, 16, 24, 0, 8, 16, 24, 0, 8, 16, 24
9430 /// Any of these lanes can of course be undef.
9432 /// This routine only supports N <= 3.
9433 /// FIXME: Evaluate whether either AVX or AVX-512 have any opportunities here
9436 /// \returns N above, or the number of times even elements must be dropped if
9437 /// there is such a number. Otherwise returns zero.
9438 static int canLowerByDroppingEvenElements(ArrayRef<int> Mask) {
9439 // Figure out whether we're looping over two inputs or just one.
9440 bool IsSingleInput = isSingleInputShuffleMask(Mask);
9442 // The modulus for the shuffle vector entries is based on whether this is
9443 // a single input or not.
9444 int ShuffleModulus = Mask.size() * (IsSingleInput ? 1 : 2);
9445 assert(isPowerOf2_32((uint32_t)ShuffleModulus) &&
9446 "We should only be called with masks with a power-of-2 size!");
9448 uint64_t ModMask = (uint64_t)ShuffleModulus - 1;
9450 // We track whether the input is viable for all power-of-2 strides 2^1, 2^2,
9451 // and 2^3 simultaneously. This is because we may have ambiguity with
9452 // partially undef inputs.
9453 bool ViableForN[3] = {true, true, true};
9455 for (int i = 0, e = Mask.size(); i < e; ++i) {
9456 // Ignore undef lanes, we'll optimistically collapse them to the pattern we
9461 bool IsAnyViable = false;
9462 for (unsigned j = 0; j != array_lengthof(ViableForN); ++j)
9463 if (ViableForN[j]) {
9466 // The shuffle mask must be equal to (i * 2^N) % M.
9467 if ((uint64_t)Mask[i] == (((uint64_t)i << N) & ModMask))
9470 ViableForN[j] = false;
9472 // Early exit if we exhaust the possible powers of two.
9477 for (unsigned j = 0; j != array_lengthof(ViableForN); ++j)
9481 // Return 0 as there is no viable power of two.
9485 /// \brief Generic lowering of v16i8 shuffles.
9487 /// This is a hybrid strategy to lower v16i8 vectors. It first attempts to
9488 /// detect any complexity reducing interleaving. If that doesn't help, it uses
9489 /// UNPCK to spread the i8 elements across two i16-element vectors, and uses
9490 /// the existing lowering for v8i16 blends on each half, finally PACK-ing them
9492 static SDValue lowerV16I8VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9493 const X86Subtarget *Subtarget,
9494 SelectionDAG &DAG) {
9496 assert(Op.getSimpleValueType() == MVT::v16i8 && "Bad shuffle type!");
9497 assert(V1.getSimpleValueType() == MVT::v16i8 && "Bad operand type!");
9498 assert(V2.getSimpleValueType() == MVT::v16i8 && "Bad operand type!");
9499 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9500 ArrayRef<int> Mask = SVOp->getMask();
9501 assert(Mask.size() == 16 && "Unexpected mask size for v16 shuffle!");
9503 // Try to use shift instructions.
9505 lowerVectorShuffleAsShift(DL, MVT::v16i8, V1, V2, Mask, DAG))
9508 // Try to use byte rotation instructions.
9509 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
9510 DL, MVT::v16i8, V1, V2, Mask, Subtarget, DAG))
9513 // Try to use a zext lowering.
9514 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(
9515 DL, MVT::v16i8, V1, V2, Mask, Subtarget, DAG))
9518 // See if we can use SSE4A Extraction / Insertion.
9519 if (Subtarget->hasSSE4A())
9520 if (SDValue V = lowerVectorShuffleWithSSE4A(DL, MVT::v16i8, V1, V2, Mask, DAG))
9524 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 16; });
9526 // For single-input shuffles, there are some nicer lowering tricks we can use.
9527 if (NumV2Elements == 0) {
9528 // Check for being able to broadcast a single element.
9529 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v16i8, V1,
9530 Mask, Subtarget, DAG))
9533 // Check whether we can widen this to an i16 shuffle by duplicating bytes.
9534 // Notably, this handles splat and partial-splat shuffles more efficiently.
9535 // However, it only makes sense if the pre-duplication shuffle simplifies
9536 // things significantly. Currently, this means we need to be able to
9537 // express the pre-duplication shuffle as an i16 shuffle.
9539 // FIXME: We should check for other patterns which can be widened into an
9540 // i16 shuffle as well.
9541 auto canWidenViaDuplication = [](ArrayRef<int> Mask) {
9542 for (int i = 0; i < 16; i += 2)
9543 if (Mask[i] != -1 && Mask[i + 1] != -1 && Mask[i] != Mask[i + 1])
9548 auto tryToWidenViaDuplication = [&]() -> SDValue {
9549 if (!canWidenViaDuplication(Mask))
9551 SmallVector<int, 4> LoInputs;
9552 std::copy_if(Mask.begin(), Mask.end(), std::back_inserter(LoInputs),
9553 [](int M) { return M >= 0 && M < 8; });
9554 std::sort(LoInputs.begin(), LoInputs.end());
9555 LoInputs.erase(std::unique(LoInputs.begin(), LoInputs.end()),
9557 SmallVector<int, 4> HiInputs;
9558 std::copy_if(Mask.begin(), Mask.end(), std::back_inserter(HiInputs),
9559 [](int M) { return M >= 8; });
9560 std::sort(HiInputs.begin(), HiInputs.end());
9561 HiInputs.erase(std::unique(HiInputs.begin(), HiInputs.end()),
9564 bool TargetLo = LoInputs.size() >= HiInputs.size();
9565 ArrayRef<int> InPlaceInputs = TargetLo ? LoInputs : HiInputs;
9566 ArrayRef<int> MovingInputs = TargetLo ? HiInputs : LoInputs;
9568 int PreDupI16Shuffle[] = {-1, -1, -1, -1, -1, -1, -1, -1};
9569 SmallDenseMap<int, int, 8> LaneMap;
9570 for (int I : InPlaceInputs) {
9571 PreDupI16Shuffle[I/2] = I/2;
9574 int j = TargetLo ? 0 : 4, je = j + 4;
9575 for (int i = 0, ie = MovingInputs.size(); i < ie; ++i) {
9576 // Check if j is already a shuffle of this input. This happens when
9577 // there are two adjacent bytes after we move the low one.
9578 if (PreDupI16Shuffle[j] != MovingInputs[i] / 2) {
9579 // If we haven't yet mapped the input, search for a slot into which
9581 while (j < je && PreDupI16Shuffle[j] != -1)
9585 // We can't place the inputs into a single half with a simple i16 shuffle, so bail.
9588 // Map this input with the i16 shuffle.
9589 PreDupI16Shuffle[j] = MovingInputs[i] / 2;
9592 // Update the lane map based on the mapping we ended up with.
9593 LaneMap[MovingInputs[i]] = 2 * j + MovingInputs[i] % 2;
9595 V1 = DAG.getBitcast(
9597 DAG.getVectorShuffle(MVT::v8i16, DL, DAG.getBitcast(MVT::v8i16, V1),
9598 DAG.getUNDEF(MVT::v8i16), PreDupI16Shuffle));
9600 // Unpack the bytes to form the i16s that will be shuffled into place.
9601 V1 = DAG.getNode(TargetLo ? X86ISD::UNPCKL : X86ISD::UNPCKH, DL,
9602 MVT::v16i8, V1, V1);
9604 int PostDupI16Shuffle[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9605 for (int i = 0; i < 16; ++i)
9606 if (Mask[i] != -1) {
9607 int MappedMask = LaneMap[Mask[i]] - (TargetLo ? 0 : 8);
9608 assert(MappedMask < 8 && "Invalid v8 shuffle mask!");
9609 if (PostDupI16Shuffle[i / 2] == -1)
9610 PostDupI16Shuffle[i / 2] = MappedMask;
9612 assert(PostDupI16Shuffle[i / 2] == MappedMask &&
9613 "Conflicting entrties in the original shuffle!");
9615 return DAG.getBitcast(
9617 DAG.getVectorShuffle(MVT::v8i16, DL, DAG.getBitcast(MVT::v8i16, V1),
9618 DAG.getUNDEF(MVT::v8i16), PostDupI16Shuffle));
9620 if (SDValue V = tryToWidenViaDuplication())
9624 if (SDValue Masked =
9625 lowerVectorShuffleAsBitMask(DL, MVT::v16i8, V1, V2, Mask, DAG))
9628 // Use dedicated unpack instructions for masks that match their pattern.
9630 lowerVectorShuffleWithUNPCK(DL, MVT::v16i8, Mask, V1, V2, DAG))
9633 // Check for SSSE3 which lets us lower all v16i8 shuffles much more directly
9634 // with PSHUFB. It is important to do this before we attempt to generate any
9635 // blends but after all of the single-input lowerings. If the single input
9636 // lowerings can find an instruction sequence that is faster than a PSHUFB, we
9637 // want to preserve that and we can DAG combine any longer sequences into
9638 // a PSHUFB in the end. But once we start blending from multiple inputs,
9639 // the complexity of DAG combining bad patterns back into PSHUFB is too high,
9640 // and there are *very* few patterns that would actually be faster than the
9641 // PSHUFB approach because of its ability to zero lanes.
9643 // FIXME: The only exceptions to the above are blends which are exact
9644 // interleavings with direct instructions supporting them. We currently don't
9645 // handle those well here.
9646 if (Subtarget->hasSSSE3()) {
9647 bool V1InUse = false;
9648 bool V2InUse = false;
9650 SDValue PSHUFB = lowerVectorShuffleAsPSHUFB(DL, MVT::v16i8, V1, V2, Mask,
9651 DAG, V1InUse, V2InUse);
9653 // If both V1 and V2 are in use and we can use a direct blend or an unpack,
9654 // do so. This avoids using them to handle blends-with-zero which is
9655 // important as a single pshufb is significantly faster for that.
9656 if (V1InUse && V2InUse) {
9657 if (Subtarget->hasSSE41())
9658 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v16i8, V1, V2,
9659 Mask, Subtarget, DAG))
9662 // We can use an unpack to do the blending rather than an or in some
9663 // cases. Even though the or may be (very minorly) more efficient, we
9664 // preference this lowering because there are common cases where part of
9665 // the complexity of the shuffles goes away when we do the final blend as
9667 // FIXME: It might be worth trying to detect if the unpack-feeding
9668 // shuffles will both be pshufb, in which case we shouldn't bother with
9670 if (SDValue Unpack = lowerVectorShuffleAsPermuteAndUnpack(
9671 DL, MVT::v16i8, V1, V2, Mask, DAG))
9678 // There are special ways we can lower some single-element blends.
9679 if (NumV2Elements == 1)
9680 if (SDValue V = lowerVectorShuffleAsElementInsertion(DL, MVT::v16i8, V1, V2,
9681 Mask, Subtarget, DAG))
9684 if (SDValue BitBlend =
9685 lowerVectorShuffleAsBitBlend(DL, MVT::v16i8, V1, V2, Mask, DAG))
9688 // Check whether a compaction lowering can be done. This handles shuffles
9689 // which take every Nth element for some even N. See the helper function for
9692 // We special case these as they can be particularly efficiently handled with
9693 // the PACKUSB instruction on x86 and they show up in common patterns of
9694 // rearranging bytes to truncate wide elements.
9695 if (int NumEvenDrops = canLowerByDroppingEvenElements(Mask)) {
9696 // NumEvenDrops is the power of two stride of the elements. Another way of
9697 // thinking about it is that we need to drop the even elements this many
9698 // times to get the original input.
9699 bool IsSingleInput = isSingleInputShuffleMask(Mask);
9701 // First we need to zero all the dropped bytes.
9702 assert(NumEvenDrops <= 3 &&
9703 "No support for dropping even elements more than 3 times.");
9704 // We use the mask type to pick which bytes are preserved based on how many
9705 // elements are dropped.
9706 MVT MaskVTs[] = { MVT::v8i16, MVT::v4i32, MVT::v2i64 };
9707 SDValue ByteClearMask = DAG.getBitcast(
9708 MVT::v16i8, DAG.getConstant(0xFF, DL, MaskVTs[NumEvenDrops - 1]));
9709 V1 = DAG.getNode(ISD::AND, DL, MVT::v16i8, V1, ByteClearMask);
9711 V2 = DAG.getNode(ISD::AND, DL, MVT::v16i8, V2, ByteClearMask);
9713 // Now pack things back together.
9714 V1 = DAG.getBitcast(MVT::v8i16, V1);
9715 V2 = IsSingleInput ? V1 : DAG.getBitcast(MVT::v8i16, V2);
9716 SDValue Result = DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8, V1, V2);
9717 for (int i = 1; i < NumEvenDrops; ++i) {
9718 Result = DAG.getBitcast(MVT::v8i16, Result);
9719 Result = DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8, Result, Result);
9725 // Handle multi-input cases by blending single-input shuffles.
9726 if (NumV2Elements > 0)
9727 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v16i8, V1, V2,
9730 // The fallback path for single-input shuffles widens this into two v8i16
9731 // vectors with unpacks, shuffles those, and then pulls them back together
9735 int LoBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9736 int HiBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9737 for (int i = 0; i < 16; ++i)
9739 (i < 8 ? LoBlendMask[i] : HiBlendMask[i % 8]) = Mask[i];
9741 SDValue Zero = getZeroVector(MVT::v8i16, Subtarget, DAG, DL);
9743 SDValue VLoHalf, VHiHalf;
9744 // Check if any of the odd lanes in the v16i8 are used. If not, we can mask
9745 // them out and avoid using UNPCK{L,H} to extract the elements of V as
9747 if (std::none_of(std::begin(LoBlendMask), std::end(LoBlendMask),
9748 [](int M) { return M >= 0 && M % 2 == 1; }) &&
9749 std::none_of(std::begin(HiBlendMask), std::end(HiBlendMask),
9750 [](int M) { return M >= 0 && M % 2 == 1; })) {
9751 // Use a mask to drop the high bytes.
9752 VLoHalf = DAG.getBitcast(MVT::v8i16, V);
9753 VLoHalf = DAG.getNode(ISD::AND, DL, MVT::v8i16, VLoHalf,
9754 DAG.getConstant(0x00FF, DL, MVT::v8i16));
9756 // This will be a single vector shuffle instead of a blend so nuke VHiHalf.
9757 VHiHalf = DAG.getUNDEF(MVT::v8i16);
9759 // Squash the masks to point directly into VLoHalf.
9760 for (int &M : LoBlendMask)
9763 for (int &M : HiBlendMask)
9767 // Otherwise just unpack the low half of V into VLoHalf and the high half into
9768 // VHiHalf so that we can blend them as i16s.
9769 VLoHalf = DAG.getBitcast(
9770 MVT::v8i16, DAG.getNode(X86ISD::UNPCKL, DL, MVT::v16i8, V, Zero));
9771 VHiHalf = DAG.getBitcast(
9772 MVT::v8i16, DAG.getNode(X86ISD::UNPCKH, DL, MVT::v16i8, V, Zero));
9775 SDValue LoV = DAG.getVectorShuffle(MVT::v8i16, DL, VLoHalf, VHiHalf, LoBlendMask);
9776 SDValue HiV = DAG.getVectorShuffle(MVT::v8i16, DL, VLoHalf, VHiHalf, HiBlendMask);
9778 return DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8, LoV, HiV);
9781 /// \brief Dispatching routine to lower various 128-bit x86 vector shuffles.
9783 /// This routine breaks down the specific type of 128-bit shuffle and
9784 /// dispatches to the lowering routines accordingly.
9785 static SDValue lower128BitVectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9786 MVT VT, const X86Subtarget *Subtarget,
9787 SelectionDAG &DAG) {
9788 switch (VT.SimpleTy) {
9790 return lowerV2I64VectorShuffle(Op, V1, V2, Subtarget, DAG);
9792 return lowerV2F64VectorShuffle(Op, V1, V2, Subtarget, DAG);
9794 return lowerV4I32VectorShuffle(Op, V1, V2, Subtarget, DAG);
9796 return lowerV4F32VectorShuffle(Op, V1, V2, Subtarget, DAG);
9798 return lowerV8I16VectorShuffle(Op, V1, V2, Subtarget, DAG);
9800 return lowerV16I8VectorShuffle(Op, V1, V2, Subtarget, DAG);
9803 llvm_unreachable("Unimplemented!");
9807 /// \brief Helper function to test whether a shuffle mask could be
9808 /// simplified by widening the elements being shuffled.
9810 /// Appends the mask for wider elements in WidenedMask if valid. Otherwise
9811 /// leaves it in an unspecified state.
9813 /// NOTE: This must handle normal vector shuffle masks and *target* vector
9814 /// shuffle masks. The latter have the special property of a '-2' representing
9815 /// a zero-ed lane of a vector.
9816 static bool canWidenShuffleElements(ArrayRef<int> Mask,
9817 SmallVectorImpl<int> &WidenedMask) {
9818 for (int i = 0, Size = Mask.size(); i < Size; i += 2) {
9819 // If both elements are undef, its trivial.
9820 if (Mask[i] == SM_SentinelUndef && Mask[i + 1] == SM_SentinelUndef) {
9821 WidenedMask.push_back(SM_SentinelUndef);
9825 // Check for an undef mask and a mask value properly aligned to fit with
9826 // a pair of values. If we find such a case, use the non-undef mask's value.
9827 if (Mask[i] == SM_SentinelUndef && Mask[i + 1] >= 0 && Mask[i + 1] % 2 == 1) {
9828 WidenedMask.push_back(Mask[i + 1] / 2);
9831 if (Mask[i + 1] == SM_SentinelUndef && Mask[i] >= 0 && Mask[i] % 2 == 0) {
9832 WidenedMask.push_back(Mask[i] / 2);
9836 // When zeroing, we need to spread the zeroing across both lanes to widen.
9837 if (Mask[i] == SM_SentinelZero || Mask[i + 1] == SM_SentinelZero) {
9838 if ((Mask[i] == SM_SentinelZero || Mask[i] == SM_SentinelUndef) &&
9839 (Mask[i + 1] == SM_SentinelZero || Mask[i + 1] == SM_SentinelUndef)) {
9840 WidenedMask.push_back(SM_SentinelZero);
9846 // Finally check if the two mask values are adjacent and aligned with
9848 if (Mask[i] != SM_SentinelUndef && Mask[i] % 2 == 0 && Mask[i] + 1 == Mask[i + 1]) {
9849 WidenedMask.push_back(Mask[i] / 2);
9853 // Otherwise we can't safely widen the elements used in this shuffle.
9856 assert(WidenedMask.size() == Mask.size() / 2 &&
9857 "Incorrect size of mask after widening the elements!");
9862 /// \brief Generic routine to split vector shuffle into half-sized shuffles.
9864 /// This routine just extracts two subvectors, shuffles them independently, and
9865 /// then concatenates them back together. This should work effectively with all
9866 /// AVX vector shuffle types.
9867 static SDValue splitAndLowerVectorShuffle(SDLoc DL, MVT VT, SDValue V1,
9868 SDValue V2, ArrayRef<int> Mask,
9869 SelectionDAG &DAG) {
9870 assert(VT.getSizeInBits() >= 256 &&
9871 "Only for 256-bit or wider vector shuffles!");
9872 assert(V1.getSimpleValueType() == VT && "Bad operand type!");
9873 assert(V2.getSimpleValueType() == VT && "Bad operand type!");
9875 ArrayRef<int> LoMask = Mask.slice(0, Mask.size() / 2);
9876 ArrayRef<int> HiMask = Mask.slice(Mask.size() / 2);
9878 int NumElements = VT.getVectorNumElements();
9879 int SplitNumElements = NumElements / 2;
9880 MVT ScalarVT = VT.getVectorElementType();
9881 MVT SplitVT = MVT::getVectorVT(ScalarVT, NumElements / 2);
9883 // Rather than splitting build-vectors, just build two narrower build
9884 // vectors. This helps shuffling with splats and zeros.
9885 auto SplitVector = [&](SDValue V) {
9886 while (V.getOpcode() == ISD::BITCAST)
9887 V = V->getOperand(0);
9889 MVT OrigVT = V.getSimpleValueType();
9890 int OrigNumElements = OrigVT.getVectorNumElements();
9891 int OrigSplitNumElements = OrigNumElements / 2;
9892 MVT OrigScalarVT = OrigVT.getVectorElementType();
9893 MVT OrigSplitVT = MVT::getVectorVT(OrigScalarVT, OrigNumElements / 2);
9897 auto *BV = dyn_cast<BuildVectorSDNode>(V);
9899 LoV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, OrigSplitVT, V,
9900 DAG.getIntPtrConstant(0, DL));
9901 HiV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, OrigSplitVT, V,
9902 DAG.getIntPtrConstant(OrigSplitNumElements, DL));
9905 SmallVector<SDValue, 16> LoOps, HiOps;
9906 for (int i = 0; i < OrigSplitNumElements; ++i) {
9907 LoOps.push_back(BV->getOperand(i));
9908 HiOps.push_back(BV->getOperand(i + OrigSplitNumElements));
9910 LoV = DAG.getNode(ISD::BUILD_VECTOR, DL, OrigSplitVT, LoOps);
9911 HiV = DAG.getNode(ISD::BUILD_VECTOR, DL, OrigSplitVT, HiOps);
9913 return std::make_pair(DAG.getBitcast(SplitVT, LoV),
9914 DAG.getBitcast(SplitVT, HiV));
9917 SDValue LoV1, HiV1, LoV2, HiV2;
9918 std::tie(LoV1, HiV1) = SplitVector(V1);
9919 std::tie(LoV2, HiV2) = SplitVector(V2);
9921 // Now create two 4-way blends of these half-width vectors.
9922 auto HalfBlend = [&](ArrayRef<int> HalfMask) {
9923 bool UseLoV1 = false, UseHiV1 = false, UseLoV2 = false, UseHiV2 = false;
9924 SmallVector<int, 32> V1BlendMask, V2BlendMask, BlendMask;
9925 for (int i = 0; i < SplitNumElements; ++i) {
9926 int M = HalfMask[i];
9927 if (M >= NumElements) {
9928 if (M >= NumElements + SplitNumElements)
9932 V2BlendMask.push_back(M - NumElements);
9933 V1BlendMask.push_back(-1);
9934 BlendMask.push_back(SplitNumElements + i);
9935 } else if (M >= 0) {
9936 if (M >= SplitNumElements)
9940 V2BlendMask.push_back(-1);
9941 V1BlendMask.push_back(M);
9942 BlendMask.push_back(i);
9944 V2BlendMask.push_back(-1);
9945 V1BlendMask.push_back(-1);
9946 BlendMask.push_back(-1);
9950 // Because the lowering happens after all combining takes place, we need to
9951 // manually combine these blend masks as much as possible so that we create
9952 // a minimal number of high-level vector shuffle nodes.
9954 // First try just blending the halves of V1 or V2.
9955 if (!UseLoV1 && !UseHiV1 && !UseLoV2 && !UseHiV2)
9956 return DAG.getUNDEF(SplitVT);
9957 if (!UseLoV2 && !UseHiV2)
9958 return DAG.getVectorShuffle(SplitVT, DL, LoV1, HiV1, V1BlendMask);
9959 if (!UseLoV1 && !UseHiV1)
9960 return DAG.getVectorShuffle(SplitVT, DL, LoV2, HiV2, V2BlendMask);
9962 SDValue V1Blend, V2Blend;
9963 if (UseLoV1 && UseHiV1) {
9965 DAG.getVectorShuffle(SplitVT, DL, LoV1, HiV1, V1BlendMask);
9967 // We only use half of V1 so map the usage down into the final blend mask.
9968 V1Blend = UseLoV1 ? LoV1 : HiV1;
9969 for (int i = 0; i < SplitNumElements; ++i)
9970 if (BlendMask[i] >= 0 && BlendMask[i] < SplitNumElements)
9971 BlendMask[i] = V1BlendMask[i] - (UseLoV1 ? 0 : SplitNumElements);
9973 if (UseLoV2 && UseHiV2) {
9975 DAG.getVectorShuffle(SplitVT, DL, LoV2, HiV2, V2BlendMask);
9977 // We only use half of V2 so map the usage down into the final blend mask.
9978 V2Blend = UseLoV2 ? LoV2 : HiV2;
9979 for (int i = 0; i < SplitNumElements; ++i)
9980 if (BlendMask[i] >= SplitNumElements)
9981 BlendMask[i] = V2BlendMask[i] + (UseLoV2 ? SplitNumElements : 0);
9983 return DAG.getVectorShuffle(SplitVT, DL, V1Blend, V2Blend, BlendMask);
9985 SDValue Lo = HalfBlend(LoMask);
9986 SDValue Hi = HalfBlend(HiMask);
9987 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, Lo, Hi);
9990 /// \brief Either split a vector in halves or decompose the shuffles and the
9993 /// This is provided as a good fallback for many lowerings of non-single-input
9994 /// shuffles with more than one 128-bit lane. In those cases, we want to select
9995 /// between splitting the shuffle into 128-bit components and stitching those
9996 /// back together vs. extracting the single-input shuffles and blending those
9998 static SDValue lowerVectorShuffleAsSplitOrBlend(SDLoc DL, MVT VT, SDValue V1,
9999 SDValue V2, ArrayRef<int> Mask,
10000 SelectionDAG &DAG) {
10001 assert(!isSingleInputShuffleMask(Mask) && "This routine must not be used to "
10002 "lower single-input shuffles as it "
10003 "could then recurse on itself.");
10004 int Size = Mask.size();
10006 // If this can be modeled as a broadcast of two elements followed by a blend,
10007 // prefer that lowering. This is especially important because broadcasts can
10008 // often fold with memory operands.
10009 auto DoBothBroadcast = [&] {
10010 int V1BroadcastIdx = -1, V2BroadcastIdx = -1;
10013 if (V2BroadcastIdx == -1)
10014 V2BroadcastIdx = M - Size;
10015 else if (M - Size != V2BroadcastIdx)
10017 } else if (M >= 0) {
10018 if (V1BroadcastIdx == -1)
10019 V1BroadcastIdx = M;
10020 else if (M != V1BroadcastIdx)
10025 if (DoBothBroadcast())
10026 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, VT, V1, V2, Mask,
10029 // If the inputs all stem from a single 128-bit lane of each input, then we
10030 // split them rather than blending because the split will decompose to
10031 // unusually few instructions.
10032 int LaneCount = VT.getSizeInBits() / 128;
10033 int LaneSize = Size / LaneCount;
10034 SmallBitVector LaneInputs[2];
10035 LaneInputs[0].resize(LaneCount, false);
10036 LaneInputs[1].resize(LaneCount, false);
10037 for (int i = 0; i < Size; ++i)
10039 LaneInputs[Mask[i] / Size][(Mask[i] % Size) / LaneSize] = true;
10040 if (LaneInputs[0].count() <= 1 && LaneInputs[1].count() <= 1)
10041 return splitAndLowerVectorShuffle(DL, VT, V1, V2, Mask, DAG);
10043 // Otherwise, just fall back to decomposed shuffles and a blend. This requires
10044 // that the decomposed single-input shuffles don't end up here.
10045 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, VT, V1, V2, Mask, DAG);
10048 /// \brief Lower a vector shuffle crossing multiple 128-bit lanes as
10049 /// a permutation and blend of those lanes.
10051 /// This essentially blends the out-of-lane inputs to each lane into the lane
10052 /// from a permuted copy of the vector. This lowering strategy results in four
10053 /// instructions in the worst case for a single-input cross lane shuffle which
10054 /// is lower than any other fully general cross-lane shuffle strategy I'm aware
10055 /// of. Special cases for each particular shuffle pattern should be handled
10056 /// prior to trying this lowering.
10057 static SDValue lowerVectorShuffleAsLanePermuteAndBlend(SDLoc DL, MVT VT,
10058 SDValue V1, SDValue V2,
10059 ArrayRef<int> Mask,
10060 SelectionDAG &DAG) {
10061 // FIXME: This should probably be generalized for 512-bit vectors as well.
10062 assert(VT.is256BitVector() && "Only for 256-bit vector shuffles!");
10063 int LaneSize = Mask.size() / 2;
10065 // If there are only inputs from one 128-bit lane, splitting will in fact be
10066 // less expensive. The flags track whether the given lane contains an element
10067 // that crosses to another lane.
10068 bool LaneCrossing[2] = {false, false};
10069 for (int i = 0, Size = Mask.size(); i < Size; ++i)
10070 if (Mask[i] >= 0 && (Mask[i] % Size) / LaneSize != i / LaneSize)
10071 LaneCrossing[(Mask[i] % Size) / LaneSize] = true;
10072 if (!LaneCrossing[0] || !LaneCrossing[1])
10073 return splitAndLowerVectorShuffle(DL, VT, V1, V2, Mask, DAG);
10075 if (isSingleInputShuffleMask(Mask)) {
10076 SmallVector<int, 32> FlippedBlendMask;
10077 for (int i = 0, Size = Mask.size(); i < Size; ++i)
10078 FlippedBlendMask.push_back(
10079 Mask[i] < 0 ? -1 : (((Mask[i] % Size) / LaneSize == i / LaneSize)
10081 : Mask[i] % LaneSize +
10082 (i / LaneSize) * LaneSize + Size));
10084 // Flip the vector, and blend the results which should now be in-lane. The
10085 // VPERM2X128 mask uses the low 2 bits for the low source and bits 4 and
10086 // 5 for the high source. The value 3 selects the high half of source 2 and
10087 // the value 2 selects the low half of source 2. We only use source 2 to
10088 // allow folding it into a memory operand.
10089 unsigned PERMMask = 3 | 2 << 4;
10090 SDValue Flipped = DAG.getNode(X86ISD::VPERM2X128, DL, VT, DAG.getUNDEF(VT),
10091 V1, DAG.getConstant(PERMMask, DL, MVT::i8));
10092 return DAG.getVectorShuffle(VT, DL, V1, Flipped, FlippedBlendMask);
10095 // This now reduces to two single-input shuffles of V1 and V2 which at worst
10096 // will be handled by the above logic and a blend of the results, much like
10097 // other patterns in AVX.
10098 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, VT, V1, V2, Mask, DAG);
10101 /// \brief Handle lowering 2-lane 128-bit shuffles.
10102 static SDValue lowerV2X128VectorShuffle(SDLoc DL, MVT VT, SDValue V1,
10103 SDValue V2, ArrayRef<int> Mask,
10104 const X86Subtarget *Subtarget,
10105 SelectionDAG &DAG) {
10106 // TODO: If minimizing size and one of the inputs is a zero vector and the
10107 // the zero vector has only one use, we could use a VPERM2X128 to save the
10108 // instruction bytes needed to explicitly generate the zero vector.
10110 // Blends are faster and handle all the non-lane-crossing cases.
10111 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, VT, V1, V2, Mask,
10115 bool IsV1Zero = ISD::isBuildVectorAllZeros(V1.getNode());
10116 bool IsV2Zero = ISD::isBuildVectorAllZeros(V2.getNode());
10118 // If either input operand is a zero vector, use VPERM2X128 because its mask
10119 // allows us to replace the zero input with an implicit zero.
10120 if (!IsV1Zero && !IsV2Zero) {
10121 // Check for patterns which can be matched with a single insert of a 128-bit
10123 bool OnlyUsesV1 = isShuffleEquivalent(V1, V2, Mask, {0, 1, 0, 1});
10124 if (OnlyUsesV1 || isShuffleEquivalent(V1, V2, Mask, {0, 1, 4, 5})) {
10125 MVT SubVT = MVT::getVectorVT(VT.getVectorElementType(),
10126 VT.getVectorNumElements() / 2);
10127 SDValue LoV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SubVT, V1,
10128 DAG.getIntPtrConstant(0, DL));
10129 SDValue HiV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SubVT,
10130 OnlyUsesV1 ? V1 : V2,
10131 DAG.getIntPtrConstant(0, DL));
10132 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, LoV, HiV);
10136 // Otherwise form a 128-bit permutation. After accounting for undefs,
10137 // convert the 64-bit shuffle mask selection values into 128-bit
10138 // selection bits by dividing the indexes by 2 and shifting into positions
10139 // defined by a vperm2*128 instruction's immediate control byte.
10141 // The immediate permute control byte looks like this:
10142 // [1:0] - select 128 bits from sources for low half of destination
10144 // [3] - zero low half of destination
10145 // [5:4] - select 128 bits from sources for high half of destination
10147 // [7] - zero high half of destination
10149 int MaskLO = Mask[0];
10150 if (MaskLO == SM_SentinelUndef)
10151 MaskLO = Mask[1] == SM_SentinelUndef ? 0 : Mask[1];
10153 int MaskHI = Mask[2];
10154 if (MaskHI == SM_SentinelUndef)
10155 MaskHI = Mask[3] == SM_SentinelUndef ? 0 : Mask[3];
10157 unsigned PermMask = MaskLO / 2 | (MaskHI / 2) << 4;
10159 // If either input is a zero vector, replace it with an undef input.
10160 // Shuffle mask values < 4 are selecting elements of V1.
10161 // Shuffle mask values >= 4 are selecting elements of V2.
10162 // Adjust each half of the permute mask by clearing the half that was
10163 // selecting the zero vector and setting the zero mask bit.
10165 V1 = DAG.getUNDEF(VT);
10167 PermMask = (PermMask & 0xf0) | 0x08;
10169 PermMask = (PermMask & 0x0f) | 0x80;
10172 V2 = DAG.getUNDEF(VT);
10174 PermMask = (PermMask & 0xf0) | 0x08;
10176 PermMask = (PermMask & 0x0f) | 0x80;
10179 return DAG.getNode(X86ISD::VPERM2X128, DL, VT, V1, V2,
10180 DAG.getConstant(PermMask, DL, MVT::i8));
10183 /// \brief Lower a vector shuffle by first fixing the 128-bit lanes and then
10184 /// shuffling each lane.
10186 /// This will only succeed when the result of fixing the 128-bit lanes results
10187 /// in a single-input non-lane-crossing shuffle with a repeating shuffle mask in
10188 /// each 128-bit lanes. This handles many cases where we can quickly blend away
10189 /// the lane crosses early and then use simpler shuffles within each lane.
10191 /// FIXME: It might be worthwhile at some point to support this without
10192 /// requiring the 128-bit lane-relative shuffles to be repeating, but currently
10193 /// in x86 only floating point has interesting non-repeating shuffles, and even
10194 /// those are still *marginally* more expensive.
10195 static SDValue lowerVectorShuffleByMerging128BitLanes(
10196 SDLoc DL, MVT VT, SDValue V1, SDValue V2, ArrayRef<int> Mask,
10197 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
10198 assert(!isSingleInputShuffleMask(Mask) &&
10199 "This is only useful with multiple inputs.");
10201 int Size = Mask.size();
10202 int LaneSize = 128 / VT.getScalarSizeInBits();
10203 int NumLanes = Size / LaneSize;
10204 assert(NumLanes > 1 && "Only handles 256-bit and wider shuffles.");
10206 // See if we can build a hypothetical 128-bit lane-fixing shuffle mask. Also
10207 // check whether the in-128-bit lane shuffles share a repeating pattern.
10208 SmallVector<int, 4> Lanes;
10209 Lanes.resize(NumLanes, -1);
10210 SmallVector<int, 4> InLaneMask;
10211 InLaneMask.resize(LaneSize, -1);
10212 for (int i = 0; i < Size; ++i) {
10216 int j = i / LaneSize;
10218 if (Lanes[j] < 0) {
10219 // First entry we've seen for this lane.
10220 Lanes[j] = Mask[i] / LaneSize;
10221 } else if (Lanes[j] != Mask[i] / LaneSize) {
10222 // This doesn't match the lane selected previously!
10226 // Check that within each lane we have a consistent shuffle mask.
10227 int k = i % LaneSize;
10228 if (InLaneMask[k] < 0) {
10229 InLaneMask[k] = Mask[i] % LaneSize;
10230 } else if (InLaneMask[k] != Mask[i] % LaneSize) {
10231 // This doesn't fit a repeating in-lane mask.
10236 // First shuffle the lanes into place.
10237 MVT LaneVT = MVT::getVectorVT(VT.isFloatingPoint() ? MVT::f64 : MVT::i64,
10238 VT.getSizeInBits() / 64);
10239 SmallVector<int, 8> LaneMask;
10240 LaneMask.resize(NumLanes * 2, -1);
10241 for (int i = 0; i < NumLanes; ++i)
10242 if (Lanes[i] >= 0) {
10243 LaneMask[2 * i + 0] = 2*Lanes[i] + 0;
10244 LaneMask[2 * i + 1] = 2*Lanes[i] + 1;
10247 V1 = DAG.getBitcast(LaneVT, V1);
10248 V2 = DAG.getBitcast(LaneVT, V2);
10249 SDValue LaneShuffle = DAG.getVectorShuffle(LaneVT, DL, V1, V2, LaneMask);
10251 // Cast it back to the type we actually want.
10252 LaneShuffle = DAG.getBitcast(VT, LaneShuffle);
10254 // Now do a simple shuffle that isn't lane crossing.
10255 SmallVector<int, 8> NewMask;
10256 NewMask.resize(Size, -1);
10257 for (int i = 0; i < Size; ++i)
10259 NewMask[i] = (i / LaneSize) * LaneSize + Mask[i] % LaneSize;
10260 assert(!is128BitLaneCrossingShuffleMask(VT, NewMask) &&
10261 "Must not introduce lane crosses at this point!");
10263 return DAG.getVectorShuffle(VT, DL, LaneShuffle, DAG.getUNDEF(VT), NewMask);
10266 /// \brief Test whether the specified input (0 or 1) is in-place blended by the
10269 /// This returns true if the elements from a particular input are already in the
10270 /// slot required by the given mask and require no permutation.
10271 static bool isShuffleMaskInputInPlace(int Input, ArrayRef<int> Mask) {
10272 assert((Input == 0 || Input == 1) && "Only two inputs to shuffles.");
10273 int Size = Mask.size();
10274 for (int i = 0; i < Size; ++i)
10275 if (Mask[i] >= 0 && Mask[i] / Size == Input && Mask[i] % Size != i)
10281 static SDValue lowerVectorShuffleWithSHUFPD(SDLoc DL, MVT VT,
10282 ArrayRef<int> Mask, SDValue V1,
10283 SDValue V2, SelectionDAG &DAG) {
10285 // Mask for V8F64: 0/1, 8/9, 2/3, 10/11, 4/5, ..
10286 // Mask for V4F64; 0/1, 4/5, 2/3, 6/7..
10287 assert(VT.getScalarSizeInBits() == 64 && "Unexpected data type for VSHUFPD");
10288 int NumElts = VT.getVectorNumElements();
10289 bool ShufpdMask = true;
10290 bool CommutableMask = true;
10291 unsigned Immediate = 0;
10292 for (int i = 0; i < NumElts; ++i) {
10295 int Val = (i & 6) + NumElts * (i & 1);
10296 int CommutVal = (i & 0xe) + NumElts * ((i & 1)^1);
10297 if (Mask[i] < Val || Mask[i] > Val + 1)
10298 ShufpdMask = false;
10299 if (Mask[i] < CommutVal || Mask[i] > CommutVal + 1)
10300 CommutableMask = false;
10301 Immediate |= (Mask[i] % 2) << i;
10304 return DAG.getNode(X86ISD::SHUFP, DL, VT, V1, V2,
10305 DAG.getConstant(Immediate, DL, MVT::i8));
10306 if (CommutableMask)
10307 return DAG.getNode(X86ISD::SHUFP, DL, VT, V2, V1,
10308 DAG.getConstant(Immediate, DL, MVT::i8));
10312 /// \brief Handle lowering of 4-lane 64-bit floating point shuffles.
10314 /// Also ends up handling lowering of 4-lane 64-bit integer shuffles when AVX2
10315 /// isn't available.
10316 static SDValue lowerV4F64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10317 const X86Subtarget *Subtarget,
10318 SelectionDAG &DAG) {
10320 assert(V1.getSimpleValueType() == MVT::v4f64 && "Bad operand type!");
10321 assert(V2.getSimpleValueType() == MVT::v4f64 && "Bad operand type!");
10322 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10323 ArrayRef<int> Mask = SVOp->getMask();
10324 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
10326 SmallVector<int, 4> WidenedMask;
10327 if (canWidenShuffleElements(Mask, WidenedMask))
10328 return lowerV2X128VectorShuffle(DL, MVT::v4f64, V1, V2, Mask, Subtarget,
10331 if (isSingleInputShuffleMask(Mask)) {
10332 // Check for being able to broadcast a single element.
10333 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v4f64, V1,
10334 Mask, Subtarget, DAG))
10337 // Use low duplicate instructions for masks that match their pattern.
10338 if (isShuffleEquivalent(V1, V2, Mask, {0, 0, 2, 2}))
10339 return DAG.getNode(X86ISD::MOVDDUP, DL, MVT::v4f64, V1);
10341 if (!is128BitLaneCrossingShuffleMask(MVT::v4f64, Mask)) {
10342 // Non-half-crossing single input shuffles can be lowerid with an
10343 // interleaved permutation.
10344 unsigned VPERMILPMask = (Mask[0] == 1) | ((Mask[1] == 1) << 1) |
10345 ((Mask[2] == 3) << 2) | ((Mask[3] == 3) << 3);
10346 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v4f64, V1,
10347 DAG.getConstant(VPERMILPMask, DL, MVT::i8));
10350 // With AVX2 we have direct support for this permutation.
10351 if (Subtarget->hasAVX2())
10352 return DAG.getNode(X86ISD::VPERMI, DL, MVT::v4f64, V1,
10353 getV4X86ShuffleImm8ForMask(Mask, DL, DAG));
10355 // Otherwise, fall back.
10356 return lowerVectorShuffleAsLanePermuteAndBlend(DL, MVT::v4f64, V1, V2, Mask,
10360 // Use dedicated unpack instructions for masks that match their pattern.
10362 lowerVectorShuffleWithUNPCK(DL, MVT::v4f64, Mask, V1, V2, DAG))
10365 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4f64, V1, V2, Mask,
10369 // Check if the blend happens to exactly fit that of SHUFPD.
10371 lowerVectorShuffleWithSHUFPD(DL, MVT::v4f64, Mask, V1, V2, DAG))
10374 // Try to simplify this by merging 128-bit lanes to enable a lane-based
10375 // shuffle. However, if we have AVX2 and either inputs are already in place,
10376 // we will be able to shuffle even across lanes the other input in a single
10377 // instruction so skip this pattern.
10378 if (!(Subtarget->hasAVX2() && (isShuffleMaskInputInPlace(0, Mask) ||
10379 isShuffleMaskInputInPlace(1, Mask))))
10380 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
10381 DL, MVT::v4f64, V1, V2, Mask, Subtarget, DAG))
10384 // If we have AVX2 then we always want to lower with a blend because an v4 we
10385 // can fully permute the elements.
10386 if (Subtarget->hasAVX2())
10387 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v4f64, V1, V2,
10390 // Otherwise fall back on generic lowering.
10391 return lowerVectorShuffleAsSplitOrBlend(DL, MVT::v4f64, V1, V2, Mask, DAG);
10394 /// \brief Handle lowering of 4-lane 64-bit integer shuffles.
10396 /// This routine is only called when we have AVX2 and thus a reasonable
10397 /// instruction set for v4i64 shuffling..
10398 static SDValue lowerV4I64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10399 const X86Subtarget *Subtarget,
10400 SelectionDAG &DAG) {
10402 assert(V1.getSimpleValueType() == MVT::v4i64 && "Bad operand type!");
10403 assert(V2.getSimpleValueType() == MVT::v4i64 && "Bad operand type!");
10404 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10405 ArrayRef<int> Mask = SVOp->getMask();
10406 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
10407 assert(Subtarget->hasAVX2() && "We can only lower v4i64 with AVX2!");
10409 SmallVector<int, 4> WidenedMask;
10410 if (canWidenShuffleElements(Mask, WidenedMask))
10411 return lowerV2X128VectorShuffle(DL, MVT::v4i64, V1, V2, Mask, Subtarget,
10414 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4i64, V1, V2, Mask,
10418 // Check for being able to broadcast a single element.
10419 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v4i64, V1,
10420 Mask, Subtarget, DAG))
10423 // When the shuffle is mirrored between the 128-bit lanes of the unit, we can
10424 // use lower latency instructions that will operate on both 128-bit lanes.
10425 SmallVector<int, 2> RepeatedMask;
10426 if (is128BitLaneRepeatedShuffleMask(MVT::v4i64, Mask, RepeatedMask)) {
10427 if (isSingleInputShuffleMask(Mask)) {
10428 int PSHUFDMask[] = {-1, -1, -1, -1};
10429 for (int i = 0; i < 2; ++i)
10430 if (RepeatedMask[i] >= 0) {
10431 PSHUFDMask[2 * i] = 2 * RepeatedMask[i];
10432 PSHUFDMask[2 * i + 1] = 2 * RepeatedMask[i] + 1;
10434 return DAG.getBitcast(
10436 DAG.getNode(X86ISD::PSHUFD, DL, MVT::v8i32,
10437 DAG.getBitcast(MVT::v8i32, V1),
10438 getV4X86ShuffleImm8ForMask(PSHUFDMask, DL, DAG)));
10442 // AVX2 provides a direct instruction for permuting a single input across
10444 if (isSingleInputShuffleMask(Mask))
10445 return DAG.getNode(X86ISD::VPERMI, DL, MVT::v4i64, V1,
10446 getV4X86ShuffleImm8ForMask(Mask, DL, DAG));
10448 // Try to use shift instructions.
10449 if (SDValue Shift =
10450 lowerVectorShuffleAsShift(DL, MVT::v4i64, V1, V2, Mask, DAG))
10453 // Use dedicated unpack instructions for masks that match their pattern.
10455 lowerVectorShuffleWithUNPCK(DL, MVT::v4i64, Mask, V1, V2, DAG))
10458 // Try to simplify this by merging 128-bit lanes to enable a lane-based
10459 // shuffle. However, if we have AVX2 and either inputs are already in place,
10460 // we will be able to shuffle even across lanes the other input in a single
10461 // instruction so skip this pattern.
10462 if (!(Subtarget->hasAVX2() && (isShuffleMaskInputInPlace(0, Mask) ||
10463 isShuffleMaskInputInPlace(1, Mask))))
10464 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
10465 DL, MVT::v4i64, V1, V2, Mask, Subtarget, DAG))
10468 // Otherwise fall back on generic blend lowering.
10469 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v4i64, V1, V2,
10473 /// \brief Handle lowering of 8-lane 32-bit floating point shuffles.
10475 /// Also ends up handling lowering of 8-lane 32-bit integer shuffles when AVX2
10476 /// isn't available.
10477 static SDValue lowerV8F32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10478 const X86Subtarget *Subtarget,
10479 SelectionDAG &DAG) {
10481 assert(V1.getSimpleValueType() == MVT::v8f32 && "Bad operand type!");
10482 assert(V2.getSimpleValueType() == MVT::v8f32 && "Bad operand type!");
10483 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10484 ArrayRef<int> Mask = SVOp->getMask();
10485 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
10487 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v8f32, V1, V2, Mask,
10491 // Check for being able to broadcast a single element.
10492 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v8f32, V1,
10493 Mask, Subtarget, DAG))
10496 // If the shuffle mask is repeated in each 128-bit lane, we have many more
10497 // options to efficiently lower the shuffle.
10498 SmallVector<int, 4> RepeatedMask;
10499 if (is128BitLaneRepeatedShuffleMask(MVT::v8f32, Mask, RepeatedMask)) {
10500 assert(RepeatedMask.size() == 4 &&
10501 "Repeated masks must be half the mask width!");
10503 // Use even/odd duplicate instructions for masks that match their pattern.
10504 if (isShuffleEquivalent(V1, V2, Mask, {0, 0, 2, 2, 4, 4, 6, 6}))
10505 return DAG.getNode(X86ISD::MOVSLDUP, DL, MVT::v8f32, V1);
10506 if (isShuffleEquivalent(V1, V2, Mask, {1, 1, 3, 3, 5, 5, 7, 7}))
10507 return DAG.getNode(X86ISD::MOVSHDUP, DL, MVT::v8f32, V1);
10509 if (isSingleInputShuffleMask(Mask))
10510 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v8f32, V1,
10511 getV4X86ShuffleImm8ForMask(RepeatedMask, DL, DAG));
10513 // Use dedicated unpack instructions for masks that match their pattern.
10515 lowerVectorShuffleWithUNPCK(DL, MVT::v8f32, Mask, V1, V2, DAG))
10518 // Otherwise, fall back to a SHUFPS sequence. Here it is important that we
10519 // have already handled any direct blends. We also need to squash the
10520 // repeated mask into a simulated v4f32 mask.
10521 for (int i = 0; i < 4; ++i)
10522 if (RepeatedMask[i] >= 8)
10523 RepeatedMask[i] -= 4;
10524 return lowerVectorShuffleWithSHUFPS(DL, MVT::v8f32, RepeatedMask, V1, V2, DAG);
10527 // If we have a single input shuffle with different shuffle patterns in the
10528 // two 128-bit lanes use the variable mask to VPERMILPS.
10529 if (isSingleInputShuffleMask(Mask)) {
10530 SDValue VPermMask[8];
10531 for (int i = 0; i < 8; ++i)
10532 VPermMask[i] = Mask[i] < 0 ? DAG.getUNDEF(MVT::i32)
10533 : DAG.getConstant(Mask[i], DL, MVT::i32);
10534 if (!is128BitLaneCrossingShuffleMask(MVT::v8f32, Mask))
10535 return DAG.getNode(
10536 X86ISD::VPERMILPV, DL, MVT::v8f32, V1,
10537 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v8i32, VPermMask));
10539 if (Subtarget->hasAVX2())
10540 return DAG.getNode(
10541 X86ISD::VPERMV, DL, MVT::v8f32,
10542 DAG.getBitcast(MVT::v8f32, DAG.getNode(ISD::BUILD_VECTOR, DL,
10543 MVT::v8i32, VPermMask)),
10546 // Otherwise, fall back.
10547 return lowerVectorShuffleAsLanePermuteAndBlend(DL, MVT::v8f32, V1, V2, Mask,
10551 // Try to simplify this by merging 128-bit lanes to enable a lane-based
10553 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
10554 DL, MVT::v8f32, V1, V2, Mask, Subtarget, DAG))
10557 // If we have AVX2 then we always want to lower with a blend because at v8 we
10558 // can fully permute the elements.
10559 if (Subtarget->hasAVX2())
10560 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v8f32, V1, V2,
10563 // Otherwise fall back on generic lowering.
10564 return lowerVectorShuffleAsSplitOrBlend(DL, MVT::v8f32, V1, V2, Mask, DAG);
10567 /// \brief Handle lowering of 8-lane 32-bit integer shuffles.
10569 /// This routine is only called when we have AVX2 and thus a reasonable
10570 /// instruction set for v8i32 shuffling..
10571 static SDValue lowerV8I32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10572 const X86Subtarget *Subtarget,
10573 SelectionDAG &DAG) {
10575 assert(V1.getSimpleValueType() == MVT::v8i32 && "Bad operand type!");
10576 assert(V2.getSimpleValueType() == MVT::v8i32 && "Bad operand type!");
10577 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10578 ArrayRef<int> Mask = SVOp->getMask();
10579 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
10580 assert(Subtarget->hasAVX2() && "We can only lower v8i32 with AVX2!");
10582 // Whenever we can lower this as a zext, that instruction is strictly faster
10583 // than any alternative. It also allows us to fold memory operands into the
10584 // shuffle in many cases.
10585 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(DL, MVT::v8i32, V1, V2,
10586 Mask, Subtarget, DAG))
10589 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v8i32, V1, V2, Mask,
10593 // Check for being able to broadcast a single element.
10594 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v8i32, V1,
10595 Mask, Subtarget, DAG))
10598 // If the shuffle mask is repeated in each 128-bit lane we can use more
10599 // efficient instructions that mirror the shuffles across the two 128-bit
10601 SmallVector<int, 4> RepeatedMask;
10602 if (is128BitLaneRepeatedShuffleMask(MVT::v8i32, Mask, RepeatedMask)) {
10603 assert(RepeatedMask.size() == 4 && "Unexpected repeated mask size!");
10604 if (isSingleInputShuffleMask(Mask))
10605 return DAG.getNode(X86ISD::PSHUFD, DL, MVT::v8i32, V1,
10606 getV4X86ShuffleImm8ForMask(RepeatedMask, DL, DAG));
10608 // Use dedicated unpack instructions for masks that match their pattern.
10610 lowerVectorShuffleWithUNPCK(DL, MVT::v8i32, Mask, V1, V2, DAG))
10614 // Try to use shift instructions.
10615 if (SDValue Shift =
10616 lowerVectorShuffleAsShift(DL, MVT::v8i32, V1, V2, Mask, DAG))
10619 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
10620 DL, MVT::v8i32, V1, V2, Mask, Subtarget, DAG))
10623 // If the shuffle patterns aren't repeated but it is a single input, directly
10624 // generate a cross-lane VPERMD instruction.
10625 if (isSingleInputShuffleMask(Mask)) {
10626 SDValue VPermMask[8];
10627 for (int i = 0; i < 8; ++i)
10628 VPermMask[i] = Mask[i] < 0 ? DAG.getUNDEF(MVT::i32)
10629 : DAG.getConstant(Mask[i], DL, MVT::i32);
10630 return DAG.getNode(
10631 X86ISD::VPERMV, DL, MVT::v8i32,
10632 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v8i32, VPermMask), V1);
10635 // Try to simplify this by merging 128-bit lanes to enable a lane-based
10637 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
10638 DL, MVT::v8i32, V1, V2, Mask, Subtarget, DAG))
10641 // Otherwise fall back on generic blend lowering.
10642 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v8i32, V1, V2,
10646 /// \brief Handle lowering of 16-lane 16-bit integer shuffles.
10648 /// This routine is only called when we have AVX2 and thus a reasonable
10649 /// instruction set for v16i16 shuffling..
10650 static SDValue lowerV16I16VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10651 const X86Subtarget *Subtarget,
10652 SelectionDAG &DAG) {
10654 assert(V1.getSimpleValueType() == MVT::v16i16 && "Bad operand type!");
10655 assert(V2.getSimpleValueType() == MVT::v16i16 && "Bad operand type!");
10656 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10657 ArrayRef<int> Mask = SVOp->getMask();
10658 assert(Mask.size() == 16 && "Unexpected mask size for v16 shuffle!");
10659 assert(Subtarget->hasAVX2() && "We can only lower v16i16 with AVX2!");
10661 // Whenever we can lower this as a zext, that instruction is strictly faster
10662 // than any alternative. It also allows us to fold memory operands into the
10663 // shuffle in many cases.
10664 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(DL, MVT::v16i16, V1, V2,
10665 Mask, Subtarget, DAG))
10668 // Check for being able to broadcast a single element.
10669 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v16i16, V1,
10670 Mask, Subtarget, DAG))
10673 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v16i16, V1, V2, Mask,
10677 // Use dedicated unpack instructions for masks that match their pattern.
10679 lowerVectorShuffleWithUNPCK(DL, MVT::v16i16, Mask, V1, V2, DAG))
10682 // Try to use shift instructions.
10683 if (SDValue Shift =
10684 lowerVectorShuffleAsShift(DL, MVT::v16i16, V1, V2, Mask, DAG))
10687 // Try to use byte rotation instructions.
10688 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
10689 DL, MVT::v16i16, V1, V2, Mask, Subtarget, DAG))
10692 if (isSingleInputShuffleMask(Mask)) {
10693 // There are no generalized cross-lane shuffle operations available on i16
10695 if (is128BitLaneCrossingShuffleMask(MVT::v16i16, Mask))
10696 return lowerVectorShuffleAsLanePermuteAndBlend(DL, MVT::v16i16, V1, V2,
10699 SmallVector<int, 8> RepeatedMask;
10700 if (is128BitLaneRepeatedShuffleMask(MVT::v16i16, Mask, RepeatedMask)) {
10701 // As this is a single-input shuffle, the repeated mask should be
10702 // a strictly valid v8i16 mask that we can pass through to the v8i16
10703 // lowering to handle even the v16 case.
10704 return lowerV8I16GeneralSingleInputVectorShuffle(
10705 DL, MVT::v16i16, V1, RepeatedMask, Subtarget, DAG);
10708 SDValue PSHUFBMask[32];
10709 for (int i = 0; i < 16; ++i) {
10710 if (Mask[i] == -1) {
10711 PSHUFBMask[2 * i] = PSHUFBMask[2 * i + 1] = DAG.getUNDEF(MVT::i8);
10715 int M = i < 8 ? Mask[i] : Mask[i] - 8;
10716 assert(M >= 0 && M < 8 && "Invalid single-input mask!");
10717 PSHUFBMask[2 * i] = DAG.getConstant(2 * M, DL, MVT::i8);
10718 PSHUFBMask[2 * i + 1] = DAG.getConstant(2 * M + 1, DL, MVT::i8);
10720 return DAG.getBitcast(MVT::v16i16,
10721 DAG.getNode(X86ISD::PSHUFB, DL, MVT::v32i8,
10722 DAG.getBitcast(MVT::v32i8, V1),
10723 DAG.getNode(ISD::BUILD_VECTOR, DL,
10724 MVT::v32i8, PSHUFBMask)));
10727 // Try to simplify this by merging 128-bit lanes to enable a lane-based
10729 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
10730 DL, MVT::v16i16, V1, V2, Mask, Subtarget, DAG))
10733 // Otherwise fall back on generic lowering.
10734 return lowerVectorShuffleAsSplitOrBlend(DL, MVT::v16i16, V1, V2, Mask, DAG);
10737 /// \brief Handle lowering of 32-lane 8-bit integer shuffles.
10739 /// This routine is only called when we have AVX2 and thus a reasonable
10740 /// instruction set for v32i8 shuffling..
10741 static SDValue lowerV32I8VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10742 const X86Subtarget *Subtarget,
10743 SelectionDAG &DAG) {
10745 assert(V1.getSimpleValueType() == MVT::v32i8 && "Bad operand type!");
10746 assert(V2.getSimpleValueType() == MVT::v32i8 && "Bad operand type!");
10747 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10748 ArrayRef<int> Mask = SVOp->getMask();
10749 assert(Mask.size() == 32 && "Unexpected mask size for v32 shuffle!");
10750 assert(Subtarget->hasAVX2() && "We can only lower v32i8 with AVX2!");
10752 // Whenever we can lower this as a zext, that instruction is strictly faster
10753 // than any alternative. It also allows us to fold memory operands into the
10754 // shuffle in many cases.
10755 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(DL, MVT::v32i8, V1, V2,
10756 Mask, Subtarget, DAG))
10759 // Check for being able to broadcast a single element.
10760 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v32i8, V1,
10761 Mask, Subtarget, DAG))
10764 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v32i8, V1, V2, Mask,
10768 // Use dedicated unpack instructions for masks that match their pattern.
10770 lowerVectorShuffleWithUNPCK(DL, MVT::v32i8, Mask, V1, V2, DAG))
10773 // Try to use shift instructions.
10774 if (SDValue Shift =
10775 lowerVectorShuffleAsShift(DL, MVT::v32i8, V1, V2, Mask, DAG))
10778 // Try to use byte rotation instructions.
10779 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
10780 DL, MVT::v32i8, V1, V2, Mask, Subtarget, DAG))
10783 if (isSingleInputShuffleMask(Mask)) {
10784 // There are no generalized cross-lane shuffle operations available on i8
10786 if (is128BitLaneCrossingShuffleMask(MVT::v32i8, Mask))
10787 return lowerVectorShuffleAsLanePermuteAndBlend(DL, MVT::v32i8, V1, V2,
10790 SDValue PSHUFBMask[32];
10791 for (int i = 0; i < 32; ++i)
10794 ? DAG.getUNDEF(MVT::i8)
10795 : DAG.getConstant(Mask[i] < 16 ? Mask[i] : Mask[i] - 16, DL,
10798 return DAG.getNode(
10799 X86ISD::PSHUFB, DL, MVT::v32i8, V1,
10800 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v32i8, PSHUFBMask));
10803 // Try to simplify this by merging 128-bit lanes to enable a lane-based
10805 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
10806 DL, MVT::v32i8, V1, V2, Mask, Subtarget, DAG))
10809 // Otherwise fall back on generic lowering.
10810 return lowerVectorShuffleAsSplitOrBlend(DL, MVT::v32i8, V1, V2, Mask, DAG);
10813 /// \brief High-level routine to lower various 256-bit x86 vector shuffles.
10815 /// This routine either breaks down the specific type of a 256-bit x86 vector
10816 /// shuffle or splits it into two 128-bit shuffles and fuses the results back
10817 /// together based on the available instructions.
10818 static SDValue lower256BitVectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10819 MVT VT, const X86Subtarget *Subtarget,
10820 SelectionDAG &DAG) {
10822 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10823 ArrayRef<int> Mask = SVOp->getMask();
10825 // If we have a single input to the zero element, insert that into V1 if we
10826 // can do so cheaply.
10827 int NumElts = VT.getVectorNumElements();
10828 int NumV2Elements = std::count_if(Mask.begin(), Mask.end(), [NumElts](int M) {
10829 return M >= NumElts;
10832 if (NumV2Elements == 1 && Mask[0] >= NumElts)
10833 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
10834 DL, VT, V1, V2, Mask, Subtarget, DAG))
10837 // There is a really nice hard cut-over between AVX1 and AVX2 that means we
10838 // can check for those subtargets here and avoid much of the subtarget
10839 // querying in the per-vector-type lowering routines. With AVX1 we have
10840 // essentially *zero* ability to manipulate a 256-bit vector with integer
10841 // types. Since we'll use floating point types there eventually, just
10842 // immediately cast everything to a float and operate entirely in that domain.
10843 if (VT.isInteger() && !Subtarget->hasAVX2()) {
10844 int ElementBits = VT.getScalarSizeInBits();
10845 if (ElementBits < 32)
10846 // No floating point type available, decompose into 128-bit vectors.
10847 return splitAndLowerVectorShuffle(DL, VT, V1, V2, Mask, DAG);
10849 MVT FpVT = MVT::getVectorVT(MVT::getFloatingPointVT(ElementBits),
10850 VT.getVectorNumElements());
10851 V1 = DAG.getBitcast(FpVT, V1);
10852 V2 = DAG.getBitcast(FpVT, V2);
10853 return DAG.getBitcast(VT, DAG.getVectorShuffle(FpVT, DL, V1, V2, Mask));
10856 switch (VT.SimpleTy) {
10858 return lowerV4F64VectorShuffle(Op, V1, V2, Subtarget, DAG);
10860 return lowerV4I64VectorShuffle(Op, V1, V2, Subtarget, DAG);
10862 return lowerV8F32VectorShuffle(Op, V1, V2, Subtarget, DAG);
10864 return lowerV8I32VectorShuffle(Op, V1, V2, Subtarget, DAG);
10866 return lowerV16I16VectorShuffle(Op, V1, V2, Subtarget, DAG);
10868 return lowerV32I8VectorShuffle(Op, V1, V2, Subtarget, DAG);
10871 llvm_unreachable("Not a valid 256-bit x86 vector type!");
10875 /// \brief Try to lower a vector shuffle as a 128-bit shuffles.
10876 static SDValue lowerV4X128VectorShuffle(SDLoc DL, MVT VT,
10877 ArrayRef<int> Mask,
10878 SDValue V1, SDValue V2,
10879 SelectionDAG &DAG) {
10880 assert(VT.getScalarSizeInBits() == 64 &&
10881 "Unexpected element type size for 128bit shuffle.");
10883 // To handle 256 bit vector requires VLX and most probably
10884 // function lowerV2X128VectorShuffle() is better solution.
10885 assert(VT.is512BitVector() && "Unexpected vector size for 128bit shuffle.");
10887 SmallVector<int, 4> WidenedMask;
10888 if (!canWidenShuffleElements(Mask, WidenedMask))
10891 // Form a 128-bit permutation.
10892 // Convert the 64-bit shuffle mask selection values into 128-bit selection
10893 // bits defined by a vshuf64x2 instruction's immediate control byte.
10894 unsigned PermMask = 0, Imm = 0;
10895 unsigned ControlBitsNum = WidenedMask.size() / 2;
10897 for (int i = 0, Size = WidenedMask.size(); i < Size; ++i) {
10898 if (WidenedMask[i] == SM_SentinelZero)
10901 // Use first element in place of undef mask.
10902 Imm = (WidenedMask[i] == SM_SentinelUndef) ? 0 : WidenedMask[i];
10903 PermMask |= (Imm % WidenedMask.size()) << (i * ControlBitsNum);
10906 return DAG.getNode(X86ISD::SHUF128, DL, VT, V1, V2,
10907 DAG.getConstant(PermMask, DL, MVT::i8));
10910 static SDValue lowerVectorShuffleWithPERMV(SDLoc DL, MVT VT,
10911 ArrayRef<int> Mask, SDValue V1,
10912 SDValue V2, SelectionDAG &DAG) {
10914 assert(VT.getScalarSizeInBits() >= 16 && "Unexpected data type for PERMV");
10916 MVT MaskEltVT = MVT::getIntegerVT(VT.getScalarSizeInBits());
10917 MVT MaskVecVT = MVT::getVectorVT(MaskEltVT, VT.getVectorNumElements());
10919 SDValue MaskNode = getConstVector(Mask, MaskVecVT, DAG, DL, true);
10920 if (isSingleInputShuffleMask(Mask))
10921 return DAG.getNode(X86ISD::VPERMV, DL, VT, MaskNode, V1);
10923 return DAG.getNode(X86ISD::VPERMV3, DL, VT, V1, MaskNode, V2);
10926 /// \brief Handle lowering of 8-lane 64-bit floating point shuffles.
10927 static SDValue lowerV8F64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10928 const X86Subtarget *Subtarget,
10929 SelectionDAG &DAG) {
10931 assert(V1.getSimpleValueType() == MVT::v8f64 && "Bad operand type!");
10932 assert(V2.getSimpleValueType() == MVT::v8f64 && "Bad operand type!");
10933 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10934 ArrayRef<int> Mask = SVOp->getMask();
10935 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
10937 if (SDValue Shuf128 =
10938 lowerV4X128VectorShuffle(DL, MVT::v8f64, Mask, V1, V2, DAG))
10941 if (SDValue Unpck =
10942 lowerVectorShuffleWithUNPCK(DL, MVT::v8f64, Mask, V1, V2, DAG))
10945 return lowerVectorShuffleWithPERMV(DL, MVT::v8f64, Mask, V1, V2, DAG);
10948 /// \brief Handle lowering of 16-lane 32-bit floating point shuffles.
10949 static SDValue lowerV16F32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10950 const X86Subtarget *Subtarget,
10951 SelectionDAG &DAG) {
10953 assert(V1.getSimpleValueType() == MVT::v16f32 && "Bad operand type!");
10954 assert(V2.getSimpleValueType() == MVT::v16f32 && "Bad operand type!");
10955 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10956 ArrayRef<int> Mask = SVOp->getMask();
10957 assert(Mask.size() == 16 && "Unexpected mask size for v16 shuffle!");
10959 if (SDValue Unpck =
10960 lowerVectorShuffleWithUNPCK(DL, MVT::v16f32, Mask, V1, V2, DAG))
10963 return lowerVectorShuffleWithPERMV(DL, MVT::v16f32, Mask, V1, V2, DAG);
10966 /// \brief Handle lowering of 8-lane 64-bit integer shuffles.
10967 static SDValue lowerV8I64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10968 const X86Subtarget *Subtarget,
10969 SelectionDAG &DAG) {
10971 assert(V1.getSimpleValueType() == MVT::v8i64 && "Bad operand type!");
10972 assert(V2.getSimpleValueType() == MVT::v8i64 && "Bad operand type!");
10973 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10974 ArrayRef<int> Mask = SVOp->getMask();
10975 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
10977 if (SDValue Shuf128 =
10978 lowerV4X128VectorShuffle(DL, MVT::v8i64, Mask, V1, V2, DAG))
10981 if (SDValue Unpck =
10982 lowerVectorShuffleWithUNPCK(DL, MVT::v8i64, Mask, V1, V2, DAG))
10985 return lowerVectorShuffleWithPERMV(DL, MVT::v8i64, Mask, V1, V2, DAG);
10988 /// \brief Handle lowering of 16-lane 32-bit integer shuffles.
10989 static SDValue lowerV16I32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10990 const X86Subtarget *Subtarget,
10991 SelectionDAG &DAG) {
10993 assert(V1.getSimpleValueType() == MVT::v16i32 && "Bad operand type!");
10994 assert(V2.getSimpleValueType() == MVT::v16i32 && "Bad operand type!");
10995 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10996 ArrayRef<int> Mask = SVOp->getMask();
10997 assert(Mask.size() == 16 && "Unexpected mask size for v16 shuffle!");
10999 if (SDValue Unpck =
11000 lowerVectorShuffleWithUNPCK(DL, MVT::v16i32, Mask, V1, V2, DAG))
11003 return lowerVectorShuffleWithPERMV(DL, MVT::v16i32, Mask, V1, V2, DAG);
11006 /// \brief Handle lowering of 32-lane 16-bit integer shuffles.
11007 static SDValue lowerV32I16VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
11008 const X86Subtarget *Subtarget,
11009 SelectionDAG &DAG) {
11011 assert(V1.getSimpleValueType() == MVT::v32i16 && "Bad operand type!");
11012 assert(V2.getSimpleValueType() == MVT::v32i16 && "Bad operand type!");
11013 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
11014 ArrayRef<int> Mask = SVOp->getMask();
11015 assert(Mask.size() == 32 && "Unexpected mask size for v32 shuffle!");
11016 assert(Subtarget->hasBWI() && "We can only lower v32i16 with AVX-512-BWI!");
11018 return lowerVectorShuffleWithPERMV(DL, MVT::v32i16, Mask, V1, V2, DAG);
11021 /// \brief Handle lowering of 64-lane 8-bit integer shuffles.
11022 static SDValue lowerV64I8VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
11023 const X86Subtarget *Subtarget,
11024 SelectionDAG &DAG) {
11026 assert(V1.getSimpleValueType() == MVT::v64i8 && "Bad operand type!");
11027 assert(V2.getSimpleValueType() == MVT::v64i8 && "Bad operand type!");
11028 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
11029 ArrayRef<int> Mask = SVOp->getMask();
11030 assert(Mask.size() == 64 && "Unexpected mask size for v64 shuffle!");
11031 assert(Subtarget->hasBWI() && "We can only lower v64i8 with AVX-512-BWI!");
11033 // FIXME: Implement direct support for this type!
11034 return splitAndLowerVectorShuffle(DL, MVT::v64i8, V1, V2, Mask, DAG);
11037 /// \brief High-level routine to lower various 512-bit x86 vector shuffles.
11039 /// This routine either breaks down the specific type of a 512-bit x86 vector
11040 /// shuffle or splits it into two 256-bit shuffles and fuses the results back
11041 /// together based on the available instructions.
11042 static SDValue lower512BitVectorShuffle(SDValue Op, SDValue V1, SDValue V2,
11043 MVT VT, const X86Subtarget *Subtarget,
11044 SelectionDAG &DAG) {
11046 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
11047 ArrayRef<int> Mask = SVOp->getMask();
11048 assert(Subtarget->hasAVX512() &&
11049 "Cannot lower 512-bit vectors w/ basic ISA!");
11051 // Check for being able to broadcast a single element.
11052 if (SDValue Broadcast =
11053 lowerVectorShuffleAsBroadcast(DL, VT, V1, Mask, Subtarget, DAG))
11056 // Dispatch to each element type for lowering. If we don't have supprot for
11057 // specific element type shuffles at 512 bits, immediately split them and
11058 // lower them. Each lowering routine of a given type is allowed to assume that
11059 // the requisite ISA extensions for that element type are available.
11060 switch (VT.SimpleTy) {
11062 return lowerV8F64VectorShuffle(Op, V1, V2, Subtarget, DAG);
11064 return lowerV16F32VectorShuffle(Op, V1, V2, Subtarget, DAG);
11066 return lowerV8I64VectorShuffle(Op, V1, V2, Subtarget, DAG);
11068 return lowerV16I32VectorShuffle(Op, V1, V2, Subtarget, DAG);
11070 if (Subtarget->hasBWI())
11071 return lowerV32I16VectorShuffle(Op, V1, V2, Subtarget, DAG);
11074 if (Subtarget->hasBWI())
11075 return lowerV64I8VectorShuffle(Op, V1, V2, Subtarget, DAG);
11079 llvm_unreachable("Not a valid 512-bit x86 vector type!");
11082 // Otherwise fall back on splitting.
11083 return splitAndLowerVectorShuffle(DL, VT, V1, V2, Mask, DAG);
11086 // Lower vXi1 vector shuffles.
11087 // There is no a dedicated instruction on AVX-512 that shuffles the masks.
11088 // The only way to shuffle bits is to sign-extend the mask vector to SIMD
11089 // vector, shuffle and then truncate it back.
11090 static SDValue lower1BitVectorShuffle(SDValue Op, SDValue V1, SDValue V2,
11091 MVT VT, const X86Subtarget *Subtarget,
11092 SelectionDAG &DAG) {
11094 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
11095 ArrayRef<int> Mask = SVOp->getMask();
11096 assert(Subtarget->hasAVX512() &&
11097 "Cannot lower 512-bit vectors w/o basic ISA!");
11099 switch (VT.SimpleTy) {
11101 llvm_unreachable("Expected a vector of i1 elements");
11103 ExtVT = MVT::v2i64;
11106 ExtVT = MVT::v4i32;
11109 ExtVT = MVT::v8i64; // Take 512-bit type, more shuffles on KNL
11112 ExtVT = MVT::v16i32;
11115 ExtVT = MVT::v32i16;
11118 ExtVT = MVT::v64i8;
11122 if (ISD::isBuildVectorAllZeros(V1.getNode()))
11123 V1 = getZeroVector(ExtVT, Subtarget, DAG, DL);
11124 else if (ISD::isBuildVectorAllOnes(V1.getNode()))
11125 V1 = getOnesVector(ExtVT, Subtarget, DAG, DL);
11127 V1 = DAG.getNode(ISD::SIGN_EXTEND, DL, ExtVT, V1);
11130 V2 = DAG.getUNDEF(ExtVT);
11131 else if (ISD::isBuildVectorAllZeros(V2.getNode()))
11132 V2 = getZeroVector(ExtVT, Subtarget, DAG, DL);
11133 else if (ISD::isBuildVectorAllOnes(V2.getNode()))
11134 V2 = getOnesVector(ExtVT, Subtarget, DAG, DL);
11136 V2 = DAG.getNode(ISD::SIGN_EXTEND, DL, ExtVT, V2);
11137 return DAG.getNode(ISD::TRUNCATE, DL, VT,
11138 DAG.getVectorShuffle(ExtVT, DL, V1, V2, Mask));
11140 /// \brief Top-level lowering for x86 vector shuffles.
11142 /// This handles decomposition, canonicalization, and lowering of all x86
11143 /// vector shuffles. Most of the specific lowering strategies are encapsulated
11144 /// above in helper routines. The canonicalization attempts to widen shuffles
11145 /// to involve fewer lanes of wider elements, consolidate symmetric patterns
11146 /// s.t. only one of the two inputs needs to be tested, etc.
11147 static SDValue lowerVectorShuffle(SDValue Op, const X86Subtarget *Subtarget,
11148 SelectionDAG &DAG) {
11149 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
11150 ArrayRef<int> Mask = SVOp->getMask();
11151 SDValue V1 = Op.getOperand(0);
11152 SDValue V2 = Op.getOperand(1);
11153 MVT VT = Op.getSimpleValueType();
11154 int NumElements = VT.getVectorNumElements();
11156 bool Is1BitVector = (VT.getVectorElementType() == MVT::i1);
11158 assert((VT.getSizeInBits() != 64 || Is1BitVector) &&
11159 "Can't lower MMX shuffles");
11161 bool V1IsUndef = V1.getOpcode() == ISD::UNDEF;
11162 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
11163 if (V1IsUndef && V2IsUndef)
11164 return DAG.getUNDEF(VT);
11166 // When we create a shuffle node we put the UNDEF node to second operand,
11167 // but in some cases the first operand may be transformed to UNDEF.
11168 // In this case we should just commute the node.
11170 return DAG.getCommutedVectorShuffle(*SVOp);
11172 // Check for non-undef masks pointing at an undef vector and make the masks
11173 // undef as well. This makes it easier to match the shuffle based solely on
11177 if (M >= NumElements) {
11178 SmallVector<int, 8> NewMask(Mask.begin(), Mask.end());
11179 for (int &M : NewMask)
11180 if (M >= NumElements)
11182 return DAG.getVectorShuffle(VT, dl, V1, V2, NewMask);
11185 // We actually see shuffles that are entirely re-arrangements of a set of
11186 // zero inputs. This mostly happens while decomposing complex shuffles into
11187 // simple ones. Directly lower these as a buildvector of zeros.
11188 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
11189 if (Zeroable.all())
11190 return getZeroVector(VT, Subtarget, DAG, dl);
11192 // Try to collapse shuffles into using a vector type with fewer elements but
11193 // wider element types. We cap this to not form integers or floating point
11194 // elements wider than 64 bits, but it might be interesting to form i128
11195 // integers to handle flipping the low and high halves of AVX 256-bit vectors.
11196 SmallVector<int, 16> WidenedMask;
11197 if (VT.getScalarSizeInBits() < 64 && !Is1BitVector &&
11198 canWidenShuffleElements(Mask, WidenedMask)) {
11199 MVT NewEltVT = VT.isFloatingPoint()
11200 ? MVT::getFloatingPointVT(VT.getScalarSizeInBits() * 2)
11201 : MVT::getIntegerVT(VT.getScalarSizeInBits() * 2);
11202 MVT NewVT = MVT::getVectorVT(NewEltVT, VT.getVectorNumElements() / 2);
11203 // Make sure that the new vector type is legal. For example, v2f64 isn't
11205 if (DAG.getTargetLoweringInfo().isTypeLegal(NewVT)) {
11206 V1 = DAG.getBitcast(NewVT, V1);
11207 V2 = DAG.getBitcast(NewVT, V2);
11208 return DAG.getBitcast(
11209 VT, DAG.getVectorShuffle(NewVT, dl, V1, V2, WidenedMask));
11213 int NumV1Elements = 0, NumUndefElements = 0, NumV2Elements = 0;
11214 for (int M : SVOp->getMask())
11216 ++NumUndefElements;
11217 else if (M < NumElements)
11222 // Commute the shuffle as needed such that more elements come from V1 than
11223 // V2. This allows us to match the shuffle pattern strictly on how many
11224 // elements come from V1 without handling the symmetric cases.
11225 if (NumV2Elements > NumV1Elements)
11226 return DAG.getCommutedVectorShuffle(*SVOp);
11228 // When the number of V1 and V2 elements are the same, try to minimize the
11229 // number of uses of V2 in the low half of the vector. When that is tied,
11230 // ensure that the sum of indices for V1 is equal to or lower than the sum
11231 // indices for V2. When those are equal, try to ensure that the number of odd
11232 // indices for V1 is lower than the number of odd indices for V2.
11233 if (NumV1Elements == NumV2Elements) {
11234 int LowV1Elements = 0, LowV2Elements = 0;
11235 for (int M : SVOp->getMask().slice(0, NumElements / 2))
11236 if (M >= NumElements)
11240 if (LowV2Elements > LowV1Elements) {
11241 return DAG.getCommutedVectorShuffle(*SVOp);
11242 } else if (LowV2Elements == LowV1Elements) {
11243 int SumV1Indices = 0, SumV2Indices = 0;
11244 for (int i = 0, Size = SVOp->getMask().size(); i < Size; ++i)
11245 if (SVOp->getMask()[i] >= NumElements)
11247 else if (SVOp->getMask()[i] >= 0)
11249 if (SumV2Indices < SumV1Indices) {
11250 return DAG.getCommutedVectorShuffle(*SVOp);
11251 } else if (SumV2Indices == SumV1Indices) {
11252 int NumV1OddIndices = 0, NumV2OddIndices = 0;
11253 for (int i = 0, Size = SVOp->getMask().size(); i < Size; ++i)
11254 if (SVOp->getMask()[i] >= NumElements)
11255 NumV2OddIndices += i % 2;
11256 else if (SVOp->getMask()[i] >= 0)
11257 NumV1OddIndices += i % 2;
11258 if (NumV2OddIndices < NumV1OddIndices)
11259 return DAG.getCommutedVectorShuffle(*SVOp);
11264 // For each vector width, delegate to a specialized lowering routine.
11265 if (VT.is128BitVector())
11266 return lower128BitVectorShuffle(Op, V1, V2, VT, Subtarget, DAG);
11268 if (VT.is256BitVector())
11269 return lower256BitVectorShuffle(Op, V1, V2, VT, Subtarget, DAG);
11271 if (VT.is512BitVector())
11272 return lower512BitVectorShuffle(Op, V1, V2, VT, Subtarget, DAG);
11275 return lower1BitVectorShuffle(Op, V1, V2, VT, Subtarget, DAG);
11276 llvm_unreachable("Unimplemented!");
11279 // This function assumes its argument is a BUILD_VECTOR of constants or
11280 // undef SDNodes. i.e: ISD::isBuildVectorOfConstantSDNodes(BuildVector) is
11282 static bool BUILD_VECTORtoBlendMask(BuildVectorSDNode *BuildVector,
11283 unsigned &MaskValue) {
11285 unsigned NumElems = BuildVector->getNumOperands();
11287 // There are 2 lanes if (NumElems > 8), and 1 lane otherwise.
11288 // We don't handle the >2 lanes case right now.
11289 unsigned NumLanes = (NumElems - 1) / 8 + 1;
11293 unsigned NumElemsInLane = NumElems / NumLanes;
11295 // Blend for v16i16 should be symmetric for the both lanes.
11296 for (unsigned i = 0; i < NumElemsInLane; ++i) {
11297 SDValue EltCond = BuildVector->getOperand(i);
11298 SDValue SndLaneEltCond =
11299 (NumLanes == 2) ? BuildVector->getOperand(i + NumElemsInLane) : EltCond;
11301 int Lane1Cond = -1, Lane2Cond = -1;
11302 if (isa<ConstantSDNode>(EltCond))
11303 Lane1Cond = !isNullConstant(EltCond);
11304 if (isa<ConstantSDNode>(SndLaneEltCond))
11305 Lane2Cond = !isNullConstant(SndLaneEltCond);
11307 unsigned LaneMask = 0;
11308 if (Lane1Cond == Lane2Cond || Lane2Cond < 0)
11309 // Lane1Cond != 0, means we want the first argument.
11310 // Lane1Cond == 0, means we want the second argument.
11311 // The encoding of this argument is 0 for the first argument, 1
11312 // for the second. Therefore, invert the condition.
11313 LaneMask = !Lane1Cond << i;
11314 else if (Lane1Cond < 0)
11315 LaneMask = !Lane2Cond << i;
11319 MaskValue |= LaneMask;
11321 MaskValue |= LaneMask << NumElemsInLane;
11326 /// \brief Try to lower a VSELECT instruction to a vector shuffle.
11327 static SDValue lowerVSELECTtoVectorShuffle(SDValue Op,
11328 const X86Subtarget *Subtarget,
11329 SelectionDAG &DAG) {
11330 SDValue Cond = Op.getOperand(0);
11331 SDValue LHS = Op.getOperand(1);
11332 SDValue RHS = Op.getOperand(2);
11334 MVT VT = Op.getSimpleValueType();
11336 if (!ISD::isBuildVectorOfConstantSDNodes(Cond.getNode()))
11338 auto *CondBV = cast<BuildVectorSDNode>(Cond);
11340 // Only non-legal VSELECTs reach this lowering, convert those into generic
11341 // shuffles and re-use the shuffle lowering path for blends.
11342 SmallVector<int, 32> Mask;
11343 for (int i = 0, Size = VT.getVectorNumElements(); i < Size; ++i) {
11344 SDValue CondElt = CondBV->getOperand(i);
11346 isa<ConstantSDNode>(CondElt) ? i + (isNullConstant(CondElt) ? Size : 0)
11349 return DAG.getVectorShuffle(VT, dl, LHS, RHS, Mask);
11352 SDValue X86TargetLowering::LowerVSELECT(SDValue Op, SelectionDAG &DAG) const {
11353 // A vselect where all conditions and data are constants can be optimized into
11354 // a single vector load by SelectionDAGLegalize::ExpandBUILD_VECTOR().
11355 if (ISD::isBuildVectorOfConstantSDNodes(Op.getOperand(0).getNode()) &&
11356 ISD::isBuildVectorOfConstantSDNodes(Op.getOperand(1).getNode()) &&
11357 ISD::isBuildVectorOfConstantSDNodes(Op.getOperand(2).getNode()))
11360 // Try to lower this to a blend-style vector shuffle. This can handle all
11361 // constant condition cases.
11362 if (SDValue BlendOp = lowerVSELECTtoVectorShuffle(Op, Subtarget, DAG))
11365 // Variable blends are only legal from SSE4.1 onward.
11366 if (!Subtarget->hasSSE41())
11369 // Only some types will be legal on some subtargets. If we can emit a legal
11370 // VSELECT-matching blend, return Op, and but if we need to expand, return
11372 switch (Op.getSimpleValueType().SimpleTy) {
11374 // Most of the vector types have blends past SSE4.1.
11378 // The byte blends for AVX vectors were introduced only in AVX2.
11379 if (Subtarget->hasAVX2())
11386 // AVX-512 BWI and VLX features support VSELECT with i16 elements.
11387 if (Subtarget->hasBWI() && Subtarget->hasVLX())
11390 // FIXME: We should custom lower this by fixing the condition and using i8
11396 static SDValue LowerEXTRACT_VECTOR_ELT_SSE4(SDValue Op, SelectionDAG &DAG) {
11397 MVT VT = Op.getSimpleValueType();
11400 if (!Op.getOperand(0).getSimpleValueType().is128BitVector())
11403 if (VT.getSizeInBits() == 8) {
11404 SDValue Extract = DAG.getNode(X86ISD::PEXTRB, dl, MVT::i32,
11405 Op.getOperand(0), Op.getOperand(1));
11406 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
11407 DAG.getValueType(VT));
11408 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
11411 if (VT.getSizeInBits() == 16) {
11412 // If Idx is 0, it's cheaper to do a move instead of a pextrw.
11413 if (isNullConstant(Op.getOperand(1)))
11414 return DAG.getNode(
11415 ISD::TRUNCATE, dl, MVT::i16,
11416 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
11417 DAG.getBitcast(MVT::v4i32, Op.getOperand(0)),
11418 Op.getOperand(1)));
11419 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, MVT::i32,
11420 Op.getOperand(0), Op.getOperand(1));
11421 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
11422 DAG.getValueType(VT));
11423 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
11426 if (VT == MVT::f32) {
11427 // EXTRACTPS outputs to a GPR32 register which will require a movd to copy
11428 // the result back to FR32 register. It's only worth matching if the
11429 // result has a single use which is a store or a bitcast to i32. And in
11430 // the case of a store, it's not worth it if the index is a constant 0,
11431 // because a MOVSSmr can be used instead, which is smaller and faster.
11432 if (!Op.hasOneUse())
11434 SDNode *User = *Op.getNode()->use_begin();
11435 if ((User->getOpcode() != ISD::STORE ||
11436 isNullConstant(Op.getOperand(1))) &&
11437 (User->getOpcode() != ISD::BITCAST ||
11438 User->getValueType(0) != MVT::i32))
11440 SDValue Extract = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
11441 DAG.getBitcast(MVT::v4i32, Op.getOperand(0)),
11443 return DAG.getBitcast(MVT::f32, Extract);
11446 if (VT == MVT::i32 || VT == MVT::i64) {
11447 // ExtractPS/pextrq works with constant index.
11448 if (isa<ConstantSDNode>(Op.getOperand(1)))
11454 /// Extract one bit from mask vector, like v16i1 or v8i1.
11455 /// AVX-512 feature.
11457 X86TargetLowering::ExtractBitFromMaskVector(SDValue Op, SelectionDAG &DAG) const {
11458 SDValue Vec = Op.getOperand(0);
11460 MVT VecVT = Vec.getSimpleValueType();
11461 SDValue Idx = Op.getOperand(1);
11462 MVT EltVT = Op.getSimpleValueType();
11464 assert((EltVT == MVT::i1) && "Unexpected operands in ExtractBitFromMaskVector");
11465 assert((VecVT.getVectorNumElements() <= 16 || Subtarget->hasBWI()) &&
11466 "Unexpected vector type in ExtractBitFromMaskVector");
11468 // variable index can't be handled in mask registers,
11469 // extend vector to VR512
11470 if (!isa<ConstantSDNode>(Idx)) {
11471 MVT ExtVT = (VecVT == MVT::v8i1 ? MVT::v8i64 : MVT::v16i32);
11472 SDValue Ext = DAG.getNode(ISD::ZERO_EXTEND, dl, ExtVT, Vec);
11473 SDValue Elt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
11474 ExtVT.getVectorElementType(), Ext, Idx);
11475 return DAG.getNode(ISD::TRUNCATE, dl, EltVT, Elt);
11478 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
11479 const TargetRegisterClass* rc = getRegClassFor(VecVT);
11480 if (!Subtarget->hasDQI() && (VecVT.getVectorNumElements() <= 8))
11481 rc = getRegClassFor(MVT::v16i1);
11482 unsigned MaxSift = rc->getSize()*8 - 1;
11483 Vec = DAG.getNode(X86ISD::VSHLI, dl, VecVT, Vec,
11484 DAG.getConstant(MaxSift - IdxVal, dl, MVT::i8));
11485 Vec = DAG.getNode(X86ISD::VSRLI, dl, VecVT, Vec,
11486 DAG.getConstant(MaxSift, dl, MVT::i8));
11487 return DAG.getNode(X86ISD::VEXTRACT, dl, MVT::i1, Vec,
11488 DAG.getIntPtrConstant(0, dl));
11492 X86TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op,
11493 SelectionDAG &DAG) const {
11495 SDValue Vec = Op.getOperand(0);
11496 MVT VecVT = Vec.getSimpleValueType();
11497 SDValue Idx = Op.getOperand(1);
11499 if (Op.getSimpleValueType() == MVT::i1)
11500 return ExtractBitFromMaskVector(Op, DAG);
11502 if (!isa<ConstantSDNode>(Idx)) {
11503 if (VecVT.is512BitVector() ||
11504 (VecVT.is256BitVector() && Subtarget->hasInt256() &&
11505 VecVT.getVectorElementType().getSizeInBits() == 32)) {
11508 MVT::getIntegerVT(VecVT.getVectorElementType().getSizeInBits());
11509 MVT MaskVT = MVT::getVectorVT(MaskEltVT, VecVT.getSizeInBits() /
11510 MaskEltVT.getSizeInBits());
11512 Idx = DAG.getZExtOrTrunc(Idx, dl, MaskEltVT);
11513 auto PtrVT = getPointerTy(DAG.getDataLayout());
11514 SDValue Mask = DAG.getNode(X86ISD::VINSERT, dl, MaskVT,
11515 getZeroVector(MaskVT, Subtarget, DAG, dl), Idx,
11516 DAG.getConstant(0, dl, PtrVT));
11517 SDValue Perm = DAG.getNode(X86ISD::VPERMV, dl, VecVT, Mask, Vec);
11518 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, Op.getValueType(), Perm,
11519 DAG.getConstant(0, dl, PtrVT));
11524 // If this is a 256-bit vector result, first extract the 128-bit vector and
11525 // then extract the element from the 128-bit vector.
11526 if (VecVT.is256BitVector() || VecVT.is512BitVector()) {
11528 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
11529 // Get the 128-bit vector.
11530 Vec = Extract128BitVector(Vec, IdxVal, DAG, dl);
11531 MVT EltVT = VecVT.getVectorElementType();
11533 unsigned ElemsPerChunk = 128 / EltVT.getSizeInBits();
11534 assert(isPowerOf2_32(ElemsPerChunk) && "Elements per chunk not power of 2");
11536 // Find IdxVal modulo ElemsPerChunk. Since ElemsPerChunk is a power of 2
11537 // this can be done with a mask.
11538 IdxVal &= ElemsPerChunk - 1;
11539 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, Op.getValueType(), Vec,
11540 DAG.getConstant(IdxVal, dl, MVT::i32));
11543 assert(VecVT.is128BitVector() && "Unexpected vector length");
11545 if (Subtarget->hasSSE41())
11546 if (SDValue Res = LowerEXTRACT_VECTOR_ELT_SSE4(Op, DAG))
11549 MVT VT = Op.getSimpleValueType();
11550 // TODO: handle v16i8.
11551 if (VT.getSizeInBits() == 16) {
11552 SDValue Vec = Op.getOperand(0);
11553 if (isNullConstant(Op.getOperand(1)))
11554 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
11555 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
11556 DAG.getBitcast(MVT::v4i32, Vec),
11557 Op.getOperand(1)));
11558 // Transform it so it match pextrw which produces a 32-bit result.
11559 MVT EltVT = MVT::i32;
11560 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, EltVT,
11561 Op.getOperand(0), Op.getOperand(1));
11562 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, EltVT, Extract,
11563 DAG.getValueType(VT));
11564 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
11567 if (VT.getSizeInBits() == 32) {
11568 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
11572 // SHUFPS the element to the lowest double word, then movss.
11573 int Mask[4] = { static_cast<int>(Idx), -1, -1, -1 };
11574 MVT VVT = Op.getOperand(0).getSimpleValueType();
11575 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
11576 DAG.getUNDEF(VVT), Mask);
11577 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
11578 DAG.getIntPtrConstant(0, dl));
11581 if (VT.getSizeInBits() == 64) {
11582 // FIXME: .td only matches this for <2 x f64>, not <2 x i64> on 32b
11583 // FIXME: seems like this should be unnecessary if mov{h,l}pd were taught
11584 // to match extract_elt for f64.
11585 if (isNullConstant(Op.getOperand(1)))
11588 // UNPCKHPD the element to the lowest double word, then movsd.
11589 // Note if the lower 64 bits of the result of the UNPCKHPD is then stored
11590 // to a f64mem, the whole operation is folded into a single MOVHPDmr.
11591 int Mask[2] = { 1, -1 };
11592 MVT VVT = Op.getOperand(0).getSimpleValueType();
11593 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
11594 DAG.getUNDEF(VVT), Mask);
11595 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
11596 DAG.getIntPtrConstant(0, dl));
11602 /// Insert one bit to mask vector, like v16i1 or v8i1.
11603 /// AVX-512 feature.
11605 X86TargetLowering::InsertBitToMaskVector(SDValue Op, SelectionDAG &DAG) const {
11607 SDValue Vec = Op.getOperand(0);
11608 SDValue Elt = Op.getOperand(1);
11609 SDValue Idx = Op.getOperand(2);
11610 MVT VecVT = Vec.getSimpleValueType();
11612 if (!isa<ConstantSDNode>(Idx)) {
11613 // Non constant index. Extend source and destination,
11614 // insert element and then truncate the result.
11615 MVT ExtVecVT = (VecVT == MVT::v8i1 ? MVT::v8i64 : MVT::v16i32);
11616 MVT ExtEltVT = (VecVT == MVT::v8i1 ? MVT::i64 : MVT::i32);
11617 SDValue ExtOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, ExtVecVT,
11618 DAG.getNode(ISD::ZERO_EXTEND, dl, ExtVecVT, Vec),
11619 DAG.getNode(ISD::ZERO_EXTEND, dl, ExtEltVT, Elt), Idx);
11620 return DAG.getNode(ISD::TRUNCATE, dl, VecVT, ExtOp);
11623 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
11624 SDValue EltInVec = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Elt);
11626 EltInVec = DAG.getNode(X86ISD::VSHLI, dl, VecVT, EltInVec,
11627 DAG.getConstant(IdxVal, dl, MVT::i8));
11628 if (Vec.getOpcode() == ISD::UNDEF)
11630 return DAG.getNode(ISD::OR, dl, VecVT, Vec, EltInVec);
11633 SDValue X86TargetLowering::LowerINSERT_VECTOR_ELT(SDValue Op,
11634 SelectionDAG &DAG) const {
11635 MVT VT = Op.getSimpleValueType();
11636 MVT EltVT = VT.getVectorElementType();
11638 if (EltVT == MVT::i1)
11639 return InsertBitToMaskVector(Op, DAG);
11642 SDValue N0 = Op.getOperand(0);
11643 SDValue N1 = Op.getOperand(1);
11644 SDValue N2 = Op.getOperand(2);
11645 if (!isa<ConstantSDNode>(N2))
11647 auto *N2C = cast<ConstantSDNode>(N2);
11648 unsigned IdxVal = N2C->getZExtValue();
11650 // If the vector is wider than 128 bits, extract the 128-bit subvector, insert
11651 // into that, and then insert the subvector back into the result.
11652 if (VT.is256BitVector() || VT.is512BitVector()) {
11653 // With a 256-bit vector, we can insert into the zero element efficiently
11654 // using a blend if we have AVX or AVX2 and the right data type.
11655 if (VT.is256BitVector() && IdxVal == 0) {
11656 // TODO: It is worthwhile to cast integer to floating point and back
11657 // and incur a domain crossing penalty if that's what we'll end up
11658 // doing anyway after extracting to a 128-bit vector.
11659 if ((Subtarget->hasAVX() && (EltVT == MVT::f64 || EltVT == MVT::f32)) ||
11660 (Subtarget->hasAVX2() && EltVT == MVT::i32)) {
11661 SDValue N1Vec = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, N1);
11662 N2 = DAG.getIntPtrConstant(1, dl);
11663 return DAG.getNode(X86ISD::BLENDI, dl, VT, N0, N1Vec, N2);
11667 // Get the desired 128-bit vector chunk.
11668 SDValue V = Extract128BitVector(N0, IdxVal, DAG, dl);
11670 // Insert the element into the desired chunk.
11671 unsigned NumEltsIn128 = 128 / EltVT.getSizeInBits();
11672 assert(isPowerOf2_32(NumEltsIn128));
11673 // Since NumEltsIn128 is a power of 2 we can use mask instead of modulo.
11674 unsigned IdxIn128 = IdxVal & (NumEltsIn128 - 1);
11676 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, V.getValueType(), V, N1,
11677 DAG.getConstant(IdxIn128, dl, MVT::i32));
11679 // Insert the changed part back into the bigger vector
11680 return Insert128BitVector(N0, V, IdxVal, DAG, dl);
11682 assert(VT.is128BitVector() && "Only 128-bit vector types should be left!");
11684 if (Subtarget->hasSSE41()) {
11685 if (EltVT.getSizeInBits() == 8 || EltVT.getSizeInBits() == 16) {
11687 if (VT == MVT::v8i16) {
11688 Opc = X86ISD::PINSRW;
11690 assert(VT == MVT::v16i8);
11691 Opc = X86ISD::PINSRB;
11694 // Transform it so it match pinsr{b,w} which expects a GR32 as its second
11696 if (N1.getValueType() != MVT::i32)
11697 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
11698 if (N2.getValueType() != MVT::i32)
11699 N2 = DAG.getIntPtrConstant(IdxVal, dl);
11700 return DAG.getNode(Opc, dl, VT, N0, N1, N2);
11703 if (EltVT == MVT::f32) {
11704 // Bits [7:6] of the constant are the source select. This will always be
11705 // zero here. The DAG Combiner may combine an extract_elt index into
11706 // these bits. For example (insert (extract, 3), 2) could be matched by
11707 // putting the '3' into bits [7:6] of X86ISD::INSERTPS.
11708 // Bits [5:4] of the constant are the destination select. This is the
11709 // value of the incoming immediate.
11710 // Bits [3:0] of the constant are the zero mask. The DAG Combiner may
11711 // combine either bitwise AND or insert of float 0.0 to set these bits.
11713 bool MinSize = DAG.getMachineFunction().getFunction()->optForMinSize();
11714 if (IdxVal == 0 && (!MinSize || !MayFoldLoad(N1))) {
11715 // If this is an insertion of 32-bits into the low 32-bits of
11716 // a vector, we prefer to generate a blend with immediate rather
11717 // than an insertps. Blends are simpler operations in hardware and so
11718 // will always have equal or better performance than insertps.
11719 // But if optimizing for size and there's a load folding opportunity,
11720 // generate insertps because blendps does not have a 32-bit memory
11722 N2 = DAG.getIntPtrConstant(1, dl);
11723 N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4f32, N1);
11724 return DAG.getNode(X86ISD::BLENDI, dl, VT, N0, N1, N2);
11726 N2 = DAG.getIntPtrConstant(IdxVal << 4, dl);
11727 // Create this as a scalar to vector..
11728 N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4f32, N1);
11729 return DAG.getNode(X86ISD::INSERTPS, dl, VT, N0, N1, N2);
11732 if (EltVT == MVT::i32 || EltVT == MVT::i64) {
11733 // PINSR* works with constant index.
11738 if (EltVT == MVT::i8)
11741 if (EltVT.getSizeInBits() == 16) {
11742 // Transform it so it match pinsrw which expects a 16-bit value in a GR32
11743 // as its second argument.
11744 if (N1.getValueType() != MVT::i32)
11745 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
11746 if (N2.getValueType() != MVT::i32)
11747 N2 = DAG.getIntPtrConstant(IdxVal, dl);
11748 return DAG.getNode(X86ISD::PINSRW, dl, VT, N0, N1, N2);
11753 static SDValue LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) {
11755 MVT OpVT = Op.getSimpleValueType();
11757 // If this is a 256-bit vector result, first insert into a 128-bit
11758 // vector and then insert into the 256-bit vector.
11759 if (!OpVT.is128BitVector()) {
11760 // Insert into a 128-bit vector.
11761 unsigned SizeFactor = OpVT.getSizeInBits()/128;
11762 MVT VT128 = MVT::getVectorVT(OpVT.getVectorElementType(),
11763 OpVT.getVectorNumElements() / SizeFactor);
11765 Op = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT128, Op.getOperand(0));
11767 // Insert the 128-bit vector.
11768 return Insert128BitVector(DAG.getUNDEF(OpVT), Op, 0, DAG, dl);
11771 if (OpVT == MVT::v1i64 &&
11772 Op.getOperand(0).getValueType() == MVT::i64)
11773 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v1i64, Op.getOperand(0));
11775 SDValue AnyExt = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, Op.getOperand(0));
11776 assert(OpVT.is128BitVector() && "Expected an SSE type!");
11777 return DAG.getBitcast(
11778 OpVT, DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, AnyExt));
11781 // Lower a node with an EXTRACT_SUBVECTOR opcode. This may result in
11782 // a simple subregister reference or explicit instructions to grab
11783 // upper bits of a vector.
11784 static SDValue LowerEXTRACT_SUBVECTOR(SDValue Op, const X86Subtarget *Subtarget,
11785 SelectionDAG &DAG) {
11787 SDValue In = Op.getOperand(0);
11788 SDValue Idx = Op.getOperand(1);
11789 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
11790 MVT ResVT = Op.getSimpleValueType();
11791 MVT InVT = In.getSimpleValueType();
11793 if (Subtarget->hasFp256()) {
11794 if (ResVT.is128BitVector() &&
11795 (InVT.is256BitVector() || InVT.is512BitVector()) &&
11796 isa<ConstantSDNode>(Idx)) {
11797 return Extract128BitVector(In, IdxVal, DAG, dl);
11799 if (ResVT.is256BitVector() && InVT.is512BitVector() &&
11800 isa<ConstantSDNode>(Idx)) {
11801 return Extract256BitVector(In, IdxVal, DAG, dl);
11807 // Lower a node with an INSERT_SUBVECTOR opcode. This may result in a
11808 // simple superregister reference or explicit instructions to insert
11809 // the upper bits of a vector.
11810 static SDValue LowerINSERT_SUBVECTOR(SDValue Op, const X86Subtarget *Subtarget,
11811 SelectionDAG &DAG) {
11812 if (!Subtarget->hasAVX())
11816 SDValue Vec = Op.getOperand(0);
11817 SDValue SubVec = Op.getOperand(1);
11818 SDValue Idx = Op.getOperand(2);
11820 if (!isa<ConstantSDNode>(Idx))
11823 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
11824 MVT OpVT = Op.getSimpleValueType();
11825 MVT SubVecVT = SubVec.getSimpleValueType();
11827 // Fold two 16-byte subvector loads into one 32-byte load:
11828 // (insert_subvector (insert_subvector undef, (load addr), 0),
11829 // (load addr + 16), Elts/2)
11831 if ((IdxVal == OpVT.getVectorNumElements() / 2) &&
11832 Vec.getOpcode() == ISD::INSERT_SUBVECTOR &&
11833 OpVT.is256BitVector() && SubVecVT.is128BitVector()) {
11834 auto *Idx2 = dyn_cast<ConstantSDNode>(Vec.getOperand(2));
11835 if (Idx2 && Idx2->getZExtValue() == 0) {
11836 SDValue SubVec2 = Vec.getOperand(1);
11837 // If needed, look through a bitcast to get to the load.
11838 if (SubVec2.getNode() && SubVec2.getOpcode() == ISD::BITCAST)
11839 SubVec2 = SubVec2.getOperand(0);
11841 if (auto *FirstLd = dyn_cast<LoadSDNode>(SubVec2)) {
11843 unsigned Alignment = FirstLd->getAlignment();
11844 unsigned AS = FirstLd->getAddressSpace();
11845 const X86TargetLowering *TLI = Subtarget->getTargetLowering();
11846 if (TLI->allowsMemoryAccess(*DAG.getContext(), DAG.getDataLayout(),
11847 OpVT, AS, Alignment, &Fast) && Fast) {
11848 SDValue Ops[] = { SubVec2, SubVec };
11849 if (SDValue Ld = EltsFromConsecutiveLoads(OpVT, Ops, dl, DAG, false))
11856 if ((OpVT.is256BitVector() || OpVT.is512BitVector()) &&
11857 SubVecVT.is128BitVector())
11858 return Insert128BitVector(Vec, SubVec, IdxVal, DAG, dl);
11860 if (OpVT.is512BitVector() && SubVecVT.is256BitVector())
11861 return Insert256BitVector(Vec, SubVec, IdxVal, DAG, dl);
11863 if (OpVT.getVectorElementType() == MVT::i1)
11864 return Insert1BitVector(Op, DAG);
11869 // ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as
11870 // their target countpart wrapped in the X86ISD::Wrapper node. Suppose N is
11871 // one of the above mentioned nodes. It has to be wrapped because otherwise
11872 // Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only
11873 // be used to form addressing mode. These wrapped nodes will be selected
11876 X86TargetLowering::LowerConstantPool(SDValue Op, SelectionDAG &DAG) const {
11877 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
11879 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
11880 // global base reg.
11881 unsigned char OpFlag = 0;
11882 unsigned WrapperKind = X86ISD::Wrapper;
11883 CodeModel::Model M = DAG.getTarget().getCodeModel();
11885 if (Subtarget->isPICStyleRIPRel() &&
11886 (M == CodeModel::Small || M == CodeModel::Kernel))
11887 WrapperKind = X86ISD::WrapperRIP;
11888 else if (Subtarget->isPICStyleGOT())
11889 OpFlag = X86II::MO_GOTOFF;
11890 else if (Subtarget->isPICStyleStubPIC())
11891 OpFlag = X86II::MO_PIC_BASE_OFFSET;
11893 auto PtrVT = getPointerTy(DAG.getDataLayout());
11894 SDValue Result = DAG.getTargetConstantPool(
11895 CP->getConstVal(), PtrVT, CP->getAlignment(), CP->getOffset(), OpFlag);
11897 Result = DAG.getNode(WrapperKind, DL, PtrVT, Result);
11898 // With PIC, the address is actually $g + Offset.
11901 DAG.getNode(ISD::ADD, DL, PtrVT,
11902 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT), Result);
11908 SDValue X86TargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) const {
11909 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
11911 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
11912 // global base reg.
11913 unsigned char OpFlag = 0;
11914 unsigned WrapperKind = X86ISD::Wrapper;
11915 CodeModel::Model M = DAG.getTarget().getCodeModel();
11917 if (Subtarget->isPICStyleRIPRel() &&
11918 (M == CodeModel::Small || M == CodeModel::Kernel))
11919 WrapperKind = X86ISD::WrapperRIP;
11920 else if (Subtarget->isPICStyleGOT())
11921 OpFlag = X86II::MO_GOTOFF;
11922 else if (Subtarget->isPICStyleStubPIC())
11923 OpFlag = X86II::MO_PIC_BASE_OFFSET;
11925 auto PtrVT = getPointerTy(DAG.getDataLayout());
11926 SDValue Result = DAG.getTargetJumpTable(JT->getIndex(), PtrVT, OpFlag);
11928 Result = DAG.getNode(WrapperKind, DL, PtrVT, Result);
11930 // With PIC, the address is actually $g + Offset.
11933 DAG.getNode(ISD::ADD, DL, PtrVT,
11934 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT), Result);
11940 X86TargetLowering::LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) const {
11941 const char *Sym = cast<ExternalSymbolSDNode>(Op)->getSymbol();
11943 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
11944 // global base reg.
11945 unsigned char OpFlag = 0;
11946 unsigned WrapperKind = X86ISD::Wrapper;
11947 CodeModel::Model M = DAG.getTarget().getCodeModel();
11949 if (Subtarget->isPICStyleRIPRel() &&
11950 (M == CodeModel::Small || M == CodeModel::Kernel)) {
11951 if (Subtarget->isTargetDarwin() || Subtarget->isTargetELF())
11952 OpFlag = X86II::MO_GOTPCREL;
11953 WrapperKind = X86ISD::WrapperRIP;
11954 } else if (Subtarget->isPICStyleGOT()) {
11955 OpFlag = X86II::MO_GOT;
11956 } else if (Subtarget->isPICStyleStubPIC()) {
11957 OpFlag = X86II::MO_DARWIN_NONLAZY_PIC_BASE;
11958 } else if (Subtarget->isPICStyleStubNoDynamic()) {
11959 OpFlag = X86II::MO_DARWIN_NONLAZY;
11962 auto PtrVT = getPointerTy(DAG.getDataLayout());
11963 SDValue Result = DAG.getTargetExternalSymbol(Sym, PtrVT, OpFlag);
11966 Result = DAG.getNode(WrapperKind, DL, PtrVT, Result);
11968 // With PIC, the address is actually $g + Offset.
11969 if (DAG.getTarget().getRelocationModel() == Reloc::PIC_ &&
11970 !Subtarget->is64Bit()) {
11972 DAG.getNode(ISD::ADD, DL, PtrVT,
11973 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT), Result);
11976 // For symbols that require a load from a stub to get the address, emit the
11978 if (isGlobalStubReference(OpFlag))
11979 Result = DAG.getLoad(PtrVT, DL, DAG.getEntryNode(), Result,
11980 MachinePointerInfo::getGOT(DAG.getMachineFunction()),
11981 false, false, false, 0);
11987 X86TargetLowering::LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const {
11988 // Create the TargetBlockAddressAddress node.
11989 unsigned char OpFlags =
11990 Subtarget->ClassifyBlockAddressReference();
11991 CodeModel::Model M = DAG.getTarget().getCodeModel();
11992 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
11993 int64_t Offset = cast<BlockAddressSDNode>(Op)->getOffset();
11995 auto PtrVT = getPointerTy(DAG.getDataLayout());
11996 SDValue Result = DAG.getTargetBlockAddress(BA, PtrVT, Offset, OpFlags);
11998 if (Subtarget->isPICStyleRIPRel() &&
11999 (M == CodeModel::Small || M == CodeModel::Kernel))
12000 Result = DAG.getNode(X86ISD::WrapperRIP, dl, PtrVT, Result);
12002 Result = DAG.getNode(X86ISD::Wrapper, dl, PtrVT, Result);
12004 // With PIC, the address is actually $g + Offset.
12005 if (isGlobalRelativeToPICBase(OpFlags)) {
12006 Result = DAG.getNode(ISD::ADD, dl, PtrVT,
12007 DAG.getNode(X86ISD::GlobalBaseReg, dl, PtrVT), Result);
12014 X86TargetLowering::LowerGlobalAddress(const GlobalValue *GV, SDLoc dl,
12015 int64_t Offset, SelectionDAG &DAG) const {
12016 // Create the TargetGlobalAddress node, folding in the constant
12017 // offset if it is legal.
12018 unsigned char OpFlags =
12019 Subtarget->ClassifyGlobalReference(GV, DAG.getTarget());
12020 CodeModel::Model M = DAG.getTarget().getCodeModel();
12021 auto PtrVT = getPointerTy(DAG.getDataLayout());
12023 if (OpFlags == X86II::MO_NO_FLAG &&
12024 X86::isOffsetSuitableForCodeModel(Offset, M)) {
12025 // A direct static reference to a global.
12026 Result = DAG.getTargetGlobalAddress(GV, dl, PtrVT, Offset);
12029 Result = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, OpFlags);
12032 if (Subtarget->isPICStyleRIPRel() &&
12033 (M == CodeModel::Small || M == CodeModel::Kernel))
12034 Result = DAG.getNode(X86ISD::WrapperRIP, dl, PtrVT, Result);
12036 Result = DAG.getNode(X86ISD::Wrapper, dl, PtrVT, Result);
12038 // With PIC, the address is actually $g + Offset.
12039 if (isGlobalRelativeToPICBase(OpFlags)) {
12040 Result = DAG.getNode(ISD::ADD, dl, PtrVT,
12041 DAG.getNode(X86ISD::GlobalBaseReg, dl, PtrVT), Result);
12044 // For globals that require a load from a stub to get the address, emit the
12046 if (isGlobalStubReference(OpFlags))
12047 Result = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Result,
12048 MachinePointerInfo::getGOT(DAG.getMachineFunction()),
12049 false, false, false, 0);
12051 // If there was a non-zero offset that we didn't fold, create an explicit
12052 // addition for it.
12054 Result = DAG.getNode(ISD::ADD, dl, PtrVT, Result,
12055 DAG.getConstant(Offset, dl, PtrVT));
12061 X86TargetLowering::LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const {
12062 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
12063 int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset();
12064 return LowerGlobalAddress(GV, SDLoc(Op), Offset, DAG);
12068 GetTLSADDR(SelectionDAG &DAG, SDValue Chain, GlobalAddressSDNode *GA,
12069 SDValue *InFlag, const EVT PtrVT, unsigned ReturnReg,
12070 unsigned char OperandFlags, bool LocalDynamic = false) {
12071 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
12072 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
12074 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
12075 GA->getValueType(0),
12079 X86ISD::NodeType CallType = LocalDynamic ? X86ISD::TLSBASEADDR
12083 SDValue Ops[] = { Chain, TGA, *InFlag };
12084 Chain = DAG.getNode(CallType, dl, NodeTys, Ops);
12086 SDValue Ops[] = { Chain, TGA };
12087 Chain = DAG.getNode(CallType, dl, NodeTys, Ops);
12090 // TLSADDR will be codegen'ed as call. Inform MFI that function has calls.
12091 MFI->setAdjustsStack(true);
12092 MFI->setHasCalls(true);
12094 SDValue Flag = Chain.getValue(1);
12095 return DAG.getCopyFromReg(Chain, dl, ReturnReg, PtrVT, Flag);
12098 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 32 bit
12100 LowerToTLSGeneralDynamicModel32(GlobalAddressSDNode *GA, SelectionDAG &DAG,
12103 SDLoc dl(GA); // ? function entry point might be better
12104 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
12105 DAG.getNode(X86ISD::GlobalBaseReg,
12106 SDLoc(), PtrVT), InFlag);
12107 InFlag = Chain.getValue(1);
12109 return GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX, X86II::MO_TLSGD);
12112 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 64 bit
12114 LowerToTLSGeneralDynamicModel64(GlobalAddressSDNode *GA, SelectionDAG &DAG,
12116 return GetTLSADDR(DAG, DAG.getEntryNode(), GA, nullptr, PtrVT,
12117 X86::RAX, X86II::MO_TLSGD);
12120 static SDValue LowerToTLSLocalDynamicModel(GlobalAddressSDNode *GA,
12126 // Get the start address of the TLS block for this module.
12127 X86MachineFunctionInfo* MFI = DAG.getMachineFunction()
12128 .getInfo<X86MachineFunctionInfo>();
12129 MFI->incNumLocalDynamicTLSAccesses();
12133 Base = GetTLSADDR(DAG, DAG.getEntryNode(), GA, nullptr, PtrVT, X86::RAX,
12134 X86II::MO_TLSLD, /*LocalDynamic=*/true);
12137 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
12138 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT), InFlag);
12139 InFlag = Chain.getValue(1);
12140 Base = GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX,
12141 X86II::MO_TLSLDM, /*LocalDynamic=*/true);
12144 // Note: the CleanupLocalDynamicTLSPass will remove redundant computations
12148 unsigned char OperandFlags = X86II::MO_DTPOFF;
12149 unsigned WrapperKind = X86ISD::Wrapper;
12150 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
12151 GA->getValueType(0),
12152 GA->getOffset(), OperandFlags);
12153 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
12155 // Add x@dtpoff with the base.
12156 return DAG.getNode(ISD::ADD, dl, PtrVT, Offset, Base);
12159 // Lower ISD::GlobalTLSAddress using the "initial exec" or "local exec" model.
12160 static SDValue LowerToTLSExecModel(GlobalAddressSDNode *GA, SelectionDAG &DAG,
12161 const EVT PtrVT, TLSModel::Model model,
12162 bool is64Bit, bool isPIC) {
12165 // Get the Thread Pointer, which is %gs:0 (32-bit) or %fs:0 (64-bit).
12166 Value *Ptr = Constant::getNullValue(Type::getInt8PtrTy(*DAG.getContext(),
12167 is64Bit ? 257 : 256));
12169 SDValue ThreadPointer =
12170 DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), DAG.getIntPtrConstant(0, dl),
12171 MachinePointerInfo(Ptr), false, false, false, 0);
12173 unsigned char OperandFlags = 0;
12174 // Most TLS accesses are not RIP relative, even on x86-64. One exception is
12176 unsigned WrapperKind = X86ISD::Wrapper;
12177 if (model == TLSModel::LocalExec) {
12178 OperandFlags = is64Bit ? X86II::MO_TPOFF : X86II::MO_NTPOFF;
12179 } else if (model == TLSModel::InitialExec) {
12181 OperandFlags = X86II::MO_GOTTPOFF;
12182 WrapperKind = X86ISD::WrapperRIP;
12184 OperandFlags = isPIC ? X86II::MO_GOTNTPOFF : X86II::MO_INDNTPOFF;
12187 llvm_unreachable("Unexpected model");
12190 // emit "addl x@ntpoff,%eax" (local exec)
12191 // or "addl x@indntpoff,%eax" (initial exec)
12192 // or "addl x@gotntpoff(%ebx) ,%eax" (initial exec, 32-bit pic)
12194 DAG.getTargetGlobalAddress(GA->getGlobal(), dl, GA->getValueType(0),
12195 GA->getOffset(), OperandFlags);
12196 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
12198 if (model == TLSModel::InitialExec) {
12199 if (isPIC && !is64Bit) {
12200 Offset = DAG.getNode(ISD::ADD, dl, PtrVT,
12201 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT),
12205 Offset = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Offset,
12206 MachinePointerInfo::getGOT(DAG.getMachineFunction()),
12207 false, false, false, 0);
12210 // The address of the thread local variable is the add of the thread
12211 // pointer with the offset of the variable.
12212 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset);
12216 X86TargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const {
12218 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
12219 const GlobalValue *GV = GA->getGlobal();
12220 auto PtrVT = getPointerTy(DAG.getDataLayout());
12222 if (Subtarget->isTargetELF()) {
12223 if (DAG.getTarget().Options.EmulatedTLS)
12224 return LowerToTLSEmulatedModel(GA, DAG);
12225 TLSModel::Model model = DAG.getTarget().getTLSModel(GV);
12227 case TLSModel::GeneralDynamic:
12228 if (Subtarget->is64Bit())
12229 return LowerToTLSGeneralDynamicModel64(GA, DAG, PtrVT);
12230 return LowerToTLSGeneralDynamicModel32(GA, DAG, PtrVT);
12231 case TLSModel::LocalDynamic:
12232 return LowerToTLSLocalDynamicModel(GA, DAG, PtrVT,
12233 Subtarget->is64Bit());
12234 case TLSModel::InitialExec:
12235 case TLSModel::LocalExec:
12236 return LowerToTLSExecModel(GA, DAG, PtrVT, model, Subtarget->is64Bit(),
12237 DAG.getTarget().getRelocationModel() ==
12240 llvm_unreachable("Unknown TLS model.");
12243 if (Subtarget->isTargetDarwin()) {
12244 // Darwin only has one model of TLS. Lower to that.
12245 unsigned char OpFlag = 0;
12246 unsigned WrapperKind = Subtarget->isPICStyleRIPRel() ?
12247 X86ISD::WrapperRIP : X86ISD::Wrapper;
12249 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
12250 // global base reg.
12251 bool PIC32 = (DAG.getTarget().getRelocationModel() == Reloc::PIC_) &&
12252 !Subtarget->is64Bit();
12254 OpFlag = X86II::MO_TLVP_PIC_BASE;
12256 OpFlag = X86II::MO_TLVP;
12258 SDValue Result = DAG.getTargetGlobalAddress(GA->getGlobal(), DL,
12259 GA->getValueType(0),
12260 GA->getOffset(), OpFlag);
12261 SDValue Offset = DAG.getNode(WrapperKind, DL, PtrVT, Result);
12263 // With PIC32, the address is actually $g + Offset.
12265 Offset = DAG.getNode(ISD::ADD, DL, PtrVT,
12266 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT),
12269 // Lowering the machine isd will make sure everything is in the right
12271 SDValue Chain = DAG.getEntryNode();
12272 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
12273 SDValue Args[] = { Chain, Offset };
12274 Chain = DAG.getNode(X86ISD::TLSCALL, DL, NodeTys, Args);
12276 // TLSCALL will be codegen'ed as call. Inform MFI that function has calls.
12277 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
12278 MFI->setAdjustsStack(true);
12280 // And our return value (tls address) is in the standard call return value
12282 unsigned Reg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
12283 return DAG.getCopyFromReg(Chain, DL, Reg, PtrVT, Chain.getValue(1));
12286 if (Subtarget->isTargetKnownWindowsMSVC() ||
12287 Subtarget->isTargetWindowsGNU()) {
12288 // Just use the implicit TLS architecture
12289 // Need to generate someting similar to:
12290 // mov rdx, qword [gs:abs 58H]; Load pointer to ThreadLocalStorage
12292 // mov ecx, dword [rel _tls_index]: Load index (from C runtime)
12293 // mov rcx, qword [rdx+rcx*8]
12294 // mov eax, .tls$:tlsvar
12295 // [rax+rcx] contains the address
12296 // Windows 64bit: gs:0x58
12297 // Windows 32bit: fs:__tls_array
12300 SDValue Chain = DAG.getEntryNode();
12302 // Get the Thread Pointer, which is %fs:__tls_array (32-bit) or
12303 // %gs:0x58 (64-bit). On MinGW, __tls_array is not available, so directly
12304 // use its literal value of 0x2C.
12305 Value *Ptr = Constant::getNullValue(Subtarget->is64Bit()
12306 ? Type::getInt8PtrTy(*DAG.getContext(),
12308 : Type::getInt32PtrTy(*DAG.getContext(),
12311 SDValue TlsArray = Subtarget->is64Bit()
12312 ? DAG.getIntPtrConstant(0x58, dl)
12313 : (Subtarget->isTargetWindowsGNU()
12314 ? DAG.getIntPtrConstant(0x2C, dl)
12315 : DAG.getExternalSymbol("_tls_array", PtrVT));
12317 SDValue ThreadPointer =
12318 DAG.getLoad(PtrVT, dl, Chain, TlsArray, MachinePointerInfo(Ptr), false,
12322 if (GV->getThreadLocalMode() == GlobalVariable::LocalExecTLSModel) {
12323 res = ThreadPointer;
12325 // Load the _tls_index variable
12326 SDValue IDX = DAG.getExternalSymbol("_tls_index", PtrVT);
12327 if (Subtarget->is64Bit())
12328 IDX = DAG.getExtLoad(ISD::ZEXTLOAD, dl, PtrVT, Chain, IDX,
12329 MachinePointerInfo(), MVT::i32, false, false,
12332 IDX = DAG.getLoad(PtrVT, dl, Chain, IDX, MachinePointerInfo(), false,
12335 auto &DL = DAG.getDataLayout();
12337 DAG.getConstant(Log2_64_Ceil(DL.getPointerSize()), dl, PtrVT);
12338 IDX = DAG.getNode(ISD::SHL, dl, PtrVT, IDX, Scale);
12340 res = DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, IDX);
12343 res = DAG.getLoad(PtrVT, dl, Chain, res, MachinePointerInfo(), false, false,
12346 // Get the offset of start of .tls section
12347 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
12348 GA->getValueType(0),
12349 GA->getOffset(), X86II::MO_SECREL);
12350 SDValue Offset = DAG.getNode(X86ISD::Wrapper, dl, PtrVT, TGA);
12352 // The address of the thread local variable is the add of the thread
12353 // pointer with the offset of the variable.
12354 return DAG.getNode(ISD::ADD, dl, PtrVT, res, Offset);
12357 llvm_unreachable("TLS not implemented for this target.");
12360 /// LowerShiftParts - Lower SRA_PARTS and friends, which return two i32 values
12361 /// and take a 2 x i32 value to shift plus a shift amount.
12362 static SDValue LowerShiftParts(SDValue Op, SelectionDAG &DAG) {
12363 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
12364 MVT VT = Op.getSimpleValueType();
12365 unsigned VTBits = VT.getSizeInBits();
12367 bool isSRA = Op.getOpcode() == ISD::SRA_PARTS;
12368 SDValue ShOpLo = Op.getOperand(0);
12369 SDValue ShOpHi = Op.getOperand(1);
12370 SDValue ShAmt = Op.getOperand(2);
12371 // X86ISD::SHLD and X86ISD::SHRD have defined overflow behavior but the
12372 // generic ISD nodes haven't. Insert an AND to be safe, it's optimized away
12374 SDValue SafeShAmt = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt,
12375 DAG.getConstant(VTBits - 1, dl, MVT::i8));
12376 SDValue Tmp1 = isSRA ? DAG.getNode(ISD::SRA, dl, VT, ShOpHi,
12377 DAG.getConstant(VTBits - 1, dl, MVT::i8))
12378 : DAG.getConstant(0, dl, VT);
12380 SDValue Tmp2, Tmp3;
12381 if (Op.getOpcode() == ISD::SHL_PARTS) {
12382 Tmp2 = DAG.getNode(X86ISD::SHLD, dl, VT, ShOpHi, ShOpLo, ShAmt);
12383 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, SafeShAmt);
12385 Tmp2 = DAG.getNode(X86ISD::SHRD, dl, VT, ShOpLo, ShOpHi, ShAmt);
12386 Tmp3 = DAG.getNode(isSRA ? ISD::SRA : ISD::SRL, dl, VT, ShOpHi, SafeShAmt);
12389 // If the shift amount is larger or equal than the width of a part we can't
12390 // rely on the results of shld/shrd. Insert a test and select the appropriate
12391 // values for large shift amounts.
12392 SDValue AndNode = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt,
12393 DAG.getConstant(VTBits, dl, MVT::i8));
12394 SDValue Cond = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
12395 AndNode, DAG.getConstant(0, dl, MVT::i8));
12398 SDValue CC = DAG.getConstant(X86::COND_NE, dl, MVT::i8);
12399 SDValue Ops0[4] = { Tmp2, Tmp3, CC, Cond };
12400 SDValue Ops1[4] = { Tmp3, Tmp1, CC, Cond };
12402 if (Op.getOpcode() == ISD::SHL_PARTS) {
12403 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0);
12404 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1);
12406 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0);
12407 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1);
12410 SDValue Ops[2] = { Lo, Hi };
12411 return DAG.getMergeValues(Ops, dl);
12414 SDValue X86TargetLowering::LowerSINT_TO_FP(SDValue Op,
12415 SelectionDAG &DAG) const {
12416 SDValue Src = Op.getOperand(0);
12417 MVT SrcVT = Src.getSimpleValueType();
12418 MVT VT = Op.getSimpleValueType();
12421 if (SrcVT.isVector()) {
12422 if (SrcVT == MVT::v2i32 && VT == MVT::v2f64) {
12423 return DAG.getNode(X86ISD::CVTDQ2PD, dl, VT,
12424 DAG.getNode(ISD::CONCAT_VECTORS, dl, MVT::v4i32, Src,
12425 DAG.getUNDEF(SrcVT)));
12427 if (SrcVT.getVectorElementType() == MVT::i1) {
12428 MVT IntegerVT = MVT::getVectorVT(MVT::i32, SrcVT.getVectorNumElements());
12429 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(),
12430 DAG.getNode(ISD::SIGN_EXTEND, dl, IntegerVT, Src));
12435 assert(SrcVT <= MVT::i64 && SrcVT >= MVT::i16 &&
12436 "Unknown SINT_TO_FP to lower!");
12438 // These are really Legal; return the operand so the caller accepts it as
12440 if (SrcVT == MVT::i32 && isScalarFPTypeInSSEReg(Op.getValueType()))
12442 if (SrcVT == MVT::i64 && isScalarFPTypeInSSEReg(Op.getValueType()) &&
12443 Subtarget->is64Bit()) {
12447 unsigned Size = SrcVT.getSizeInBits()/8;
12448 MachineFunction &MF = DAG.getMachineFunction();
12449 auto PtrVT = getPointerTy(MF.getDataLayout());
12450 int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size, false);
12451 SDValue StackSlot = DAG.getFrameIndex(SSFI, PtrVT);
12452 SDValue Chain = DAG.getStore(
12453 DAG.getEntryNode(), dl, Op.getOperand(0), StackSlot,
12454 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), SSFI), false,
12456 return BuildFILD(Op, SrcVT, Chain, StackSlot, DAG);
12459 SDValue X86TargetLowering::BuildFILD(SDValue Op, EVT SrcVT, SDValue Chain,
12461 SelectionDAG &DAG) const {
12465 bool useSSE = isScalarFPTypeInSSEReg(Op.getValueType());
12467 Tys = DAG.getVTList(MVT::f64, MVT::Other, MVT::Glue);
12469 Tys = DAG.getVTList(Op.getValueType(), MVT::Other);
12471 unsigned ByteSize = SrcVT.getSizeInBits()/8;
12473 FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(StackSlot);
12474 MachineMemOperand *MMO;
12476 int SSFI = FI->getIndex();
12477 MMO = DAG.getMachineFunction().getMachineMemOperand(
12478 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), SSFI),
12479 MachineMemOperand::MOLoad, ByteSize, ByteSize);
12481 MMO = cast<LoadSDNode>(StackSlot)->getMemOperand();
12482 StackSlot = StackSlot.getOperand(1);
12484 SDValue Ops[] = { Chain, StackSlot, DAG.getValueType(SrcVT) };
12485 SDValue Result = DAG.getMemIntrinsicNode(useSSE ? X86ISD::FILD_FLAG :
12487 Tys, Ops, SrcVT, MMO);
12490 Chain = Result.getValue(1);
12491 SDValue InFlag = Result.getValue(2);
12493 // FIXME: Currently the FST is flagged to the FILD_FLAG. This
12494 // shouldn't be necessary except that RFP cannot be live across
12495 // multiple blocks. When stackifier is fixed, they can be uncoupled.
12496 MachineFunction &MF = DAG.getMachineFunction();
12497 unsigned SSFISize = Op.getValueType().getSizeInBits()/8;
12498 int SSFI = MF.getFrameInfo()->CreateStackObject(SSFISize, SSFISize, false);
12499 auto PtrVT = getPointerTy(MF.getDataLayout());
12500 SDValue StackSlot = DAG.getFrameIndex(SSFI, PtrVT);
12501 Tys = DAG.getVTList(MVT::Other);
12503 Chain, Result, StackSlot, DAG.getValueType(Op.getValueType()), InFlag
12505 MachineMemOperand *MMO = DAG.getMachineFunction().getMachineMemOperand(
12506 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), SSFI),
12507 MachineMemOperand::MOStore, SSFISize, SSFISize);
12509 Chain = DAG.getMemIntrinsicNode(X86ISD::FST, DL, Tys,
12510 Ops, Op.getValueType(), MMO);
12511 Result = DAG.getLoad(
12512 Op.getValueType(), DL, Chain, StackSlot,
12513 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), SSFI),
12514 false, false, false, 0);
12520 // LowerUINT_TO_FP_i64 - 64-bit unsigned integer to double expansion.
12521 SDValue X86TargetLowering::LowerUINT_TO_FP_i64(SDValue Op,
12522 SelectionDAG &DAG) const {
12523 // This algorithm is not obvious. Here it is what we're trying to output:
12526 punpckldq (c0), %xmm0 // c0: (uint4){ 0x43300000U, 0x45300000U, 0U, 0U }
12527 subpd (c1), %xmm0 // c1: (double2){ 0x1.0p52, 0x1.0p52 * 0x1.0p32 }
12529 haddpd %xmm0, %xmm0
12531 pshufd $0x4e, %xmm0, %xmm1
12537 LLVMContext *Context = DAG.getContext();
12539 // Build some magic constants.
12540 static const uint32_t CV0[] = { 0x43300000, 0x45300000, 0, 0 };
12541 Constant *C0 = ConstantDataVector::get(*Context, CV0);
12542 auto PtrVT = getPointerTy(DAG.getDataLayout());
12543 SDValue CPIdx0 = DAG.getConstantPool(C0, PtrVT, 16);
12545 SmallVector<Constant*,2> CV1;
12547 ConstantFP::get(*Context, APFloat(APFloat::IEEEdouble,
12548 APInt(64, 0x4330000000000000ULL))));
12550 ConstantFP::get(*Context, APFloat(APFloat::IEEEdouble,
12551 APInt(64, 0x4530000000000000ULL))));
12552 Constant *C1 = ConstantVector::get(CV1);
12553 SDValue CPIdx1 = DAG.getConstantPool(C1, PtrVT, 16);
12555 // Load the 64-bit value into an XMM register.
12556 SDValue XR1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
12559 DAG.getLoad(MVT::v4i32, dl, DAG.getEntryNode(), CPIdx0,
12560 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()),
12561 false, false, false, 16);
12563 getUnpackl(DAG, dl, MVT::v4i32, DAG.getBitcast(MVT::v4i32, XR1), CLod0);
12566 DAG.getLoad(MVT::v2f64, dl, CLod0.getValue(1), CPIdx1,
12567 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()),
12568 false, false, false, 16);
12569 SDValue XR2F = DAG.getBitcast(MVT::v2f64, Unpck1);
12570 // TODO: Are there any fast-math-flags to propagate here?
12571 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, XR2F, CLod1);
12574 if (Subtarget->hasSSE3()) {
12575 // FIXME: The 'haddpd' instruction may be slower than 'movhlps + addsd'.
12576 Result = DAG.getNode(X86ISD::FHADD, dl, MVT::v2f64, Sub, Sub);
12578 SDValue S2F = DAG.getBitcast(MVT::v4i32, Sub);
12579 SDValue Shuffle = getTargetShuffleNode(X86ISD::PSHUFD, dl, MVT::v4i32,
12581 Result = DAG.getNode(ISD::FADD, dl, MVT::v2f64,
12582 DAG.getBitcast(MVT::v2f64, Shuffle), Sub);
12585 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Result,
12586 DAG.getIntPtrConstant(0, dl));
12589 // LowerUINT_TO_FP_i32 - 32-bit unsigned integer to float expansion.
12590 SDValue X86TargetLowering::LowerUINT_TO_FP_i32(SDValue Op,
12591 SelectionDAG &DAG) const {
12593 // FP constant to bias correct the final result.
12594 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL), dl,
12597 // Load the 32-bit value into an XMM register.
12598 SDValue Load = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,
12601 // Zero out the upper parts of the register.
12602 Load = getShuffleVectorZeroOrUndef(Load, 0, true, Subtarget, DAG);
12604 Load = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
12605 DAG.getBitcast(MVT::v2f64, Load),
12606 DAG.getIntPtrConstant(0, dl));
12608 // Or the load with the bias.
12609 SDValue Or = DAG.getNode(
12610 ISD::OR, dl, MVT::v2i64,
12611 DAG.getBitcast(MVT::v2i64,
12612 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f64, Load)),
12613 DAG.getBitcast(MVT::v2i64,
12614 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f64, Bias)));
12616 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
12617 DAG.getBitcast(MVT::v2f64, Or), DAG.getIntPtrConstant(0, dl));
12619 // Subtract the bias.
12620 // TODO: Are there any fast-math-flags to propagate here?
12621 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Or, Bias);
12623 // Handle final rounding.
12624 MVT DestVT = Op.getSimpleValueType();
12626 if (DestVT.bitsLT(MVT::f64))
12627 return DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub,
12628 DAG.getIntPtrConstant(0, dl));
12629 if (DestVT.bitsGT(MVT::f64))
12630 return DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub);
12632 // Handle final rounding.
12636 static SDValue lowerUINT_TO_FP_vXi32(SDValue Op, SelectionDAG &DAG,
12637 const X86Subtarget &Subtarget) {
12638 // The algorithm is the following:
12639 // #ifdef __SSE4_1__
12640 // uint4 lo = _mm_blend_epi16( v, (uint4) 0x4b000000, 0xaa);
12641 // uint4 hi = _mm_blend_epi16( _mm_srli_epi32(v,16),
12642 // (uint4) 0x53000000, 0xaa);
12644 // uint4 lo = (v & (uint4) 0xffff) | (uint4) 0x4b000000;
12645 // uint4 hi = (v >> 16) | (uint4) 0x53000000;
12647 // float4 fhi = (float4) hi - (0x1.0p39f + 0x1.0p23f);
12648 // return (float4) lo + fhi;
12650 // We shouldn't use it when unsafe-fp-math is enabled though: we might later
12651 // reassociate the two FADDs, and if we do that, the algorithm fails
12652 // spectacularly (PR24512).
12653 // FIXME: If we ever have some kind of Machine FMF, this should be marked
12654 // as non-fast and always be enabled. Why isn't SDAG FMF enough? Because
12655 // there's also the MachineCombiner reassociations happening on Machine IR.
12656 if (DAG.getTarget().Options.UnsafeFPMath)
12660 SDValue V = Op->getOperand(0);
12661 MVT VecIntVT = V.getSimpleValueType();
12662 bool Is128 = VecIntVT == MVT::v4i32;
12663 MVT VecFloatVT = Is128 ? MVT::v4f32 : MVT::v8f32;
12664 // If we convert to something else than the supported type, e.g., to v4f64,
12666 if (VecFloatVT != Op->getSimpleValueType(0))
12669 unsigned NumElts = VecIntVT.getVectorNumElements();
12670 assert((VecIntVT == MVT::v4i32 || VecIntVT == MVT::v8i32) &&
12671 "Unsupported custom type");
12672 assert(NumElts <= 8 && "The size of the constant array must be fixed");
12674 // In the #idef/#else code, we have in common:
12675 // - The vector of constants:
12681 // Create the splat vector for 0x4b000000.
12682 SDValue CstLow = DAG.getConstant(0x4b000000, DL, MVT::i32);
12683 SDValue CstLowArray[] = {CstLow, CstLow, CstLow, CstLow,
12684 CstLow, CstLow, CstLow, CstLow};
12685 SDValue VecCstLow = DAG.getNode(ISD::BUILD_VECTOR, DL, VecIntVT,
12686 makeArrayRef(&CstLowArray[0], NumElts));
12687 // Create the splat vector for 0x53000000.
12688 SDValue CstHigh = DAG.getConstant(0x53000000, DL, MVT::i32);
12689 SDValue CstHighArray[] = {CstHigh, CstHigh, CstHigh, CstHigh,
12690 CstHigh, CstHigh, CstHigh, CstHigh};
12691 SDValue VecCstHigh = DAG.getNode(ISD::BUILD_VECTOR, DL, VecIntVT,
12692 makeArrayRef(&CstHighArray[0], NumElts));
12694 // Create the right shift.
12695 SDValue CstShift = DAG.getConstant(16, DL, MVT::i32);
12696 SDValue CstShiftArray[] = {CstShift, CstShift, CstShift, CstShift,
12697 CstShift, CstShift, CstShift, CstShift};
12698 SDValue VecCstShift = DAG.getNode(ISD::BUILD_VECTOR, DL, VecIntVT,
12699 makeArrayRef(&CstShiftArray[0], NumElts));
12700 SDValue HighShift = DAG.getNode(ISD::SRL, DL, VecIntVT, V, VecCstShift);
12703 if (Subtarget.hasSSE41()) {
12704 MVT VecI16VT = Is128 ? MVT::v8i16 : MVT::v16i16;
12705 // uint4 lo = _mm_blend_epi16( v, (uint4) 0x4b000000, 0xaa);
12706 SDValue VecCstLowBitcast = DAG.getBitcast(VecI16VT, VecCstLow);
12707 SDValue VecBitcast = DAG.getBitcast(VecI16VT, V);
12708 // Low will be bitcasted right away, so do not bother bitcasting back to its
12710 Low = DAG.getNode(X86ISD::BLENDI, DL, VecI16VT, VecBitcast,
12711 VecCstLowBitcast, DAG.getConstant(0xaa, DL, MVT::i32));
12712 // uint4 hi = _mm_blend_epi16( _mm_srli_epi32(v,16),
12713 // (uint4) 0x53000000, 0xaa);
12714 SDValue VecCstHighBitcast = DAG.getBitcast(VecI16VT, VecCstHigh);
12715 SDValue VecShiftBitcast = DAG.getBitcast(VecI16VT, HighShift);
12716 // High will be bitcasted right away, so do not bother bitcasting back to
12717 // its original type.
12718 High = DAG.getNode(X86ISD::BLENDI, DL, VecI16VT, VecShiftBitcast,
12719 VecCstHighBitcast, DAG.getConstant(0xaa, DL, MVT::i32));
12721 SDValue CstMask = DAG.getConstant(0xffff, DL, MVT::i32);
12722 SDValue VecCstMask = DAG.getNode(ISD::BUILD_VECTOR, DL, VecIntVT, CstMask,
12723 CstMask, CstMask, CstMask);
12724 // uint4 lo = (v & (uint4) 0xffff) | (uint4) 0x4b000000;
12725 SDValue LowAnd = DAG.getNode(ISD::AND, DL, VecIntVT, V, VecCstMask);
12726 Low = DAG.getNode(ISD::OR, DL, VecIntVT, LowAnd, VecCstLow);
12728 // uint4 hi = (v >> 16) | (uint4) 0x53000000;
12729 High = DAG.getNode(ISD::OR, DL, VecIntVT, HighShift, VecCstHigh);
12732 // Create the vector constant for -(0x1.0p39f + 0x1.0p23f).
12733 SDValue CstFAdd = DAG.getConstantFP(
12734 APFloat(APFloat::IEEEsingle, APInt(32, 0xD3000080)), DL, MVT::f32);
12735 SDValue CstFAddArray[] = {CstFAdd, CstFAdd, CstFAdd, CstFAdd,
12736 CstFAdd, CstFAdd, CstFAdd, CstFAdd};
12737 SDValue VecCstFAdd = DAG.getNode(ISD::BUILD_VECTOR, DL, VecFloatVT,
12738 makeArrayRef(&CstFAddArray[0], NumElts));
12740 // float4 fhi = (float4) hi - (0x1.0p39f + 0x1.0p23f);
12741 SDValue HighBitcast = DAG.getBitcast(VecFloatVT, High);
12742 // TODO: Are there any fast-math-flags to propagate here?
12744 DAG.getNode(ISD::FADD, DL, VecFloatVT, HighBitcast, VecCstFAdd);
12745 // return (float4) lo + fhi;
12746 SDValue LowBitcast = DAG.getBitcast(VecFloatVT, Low);
12747 return DAG.getNode(ISD::FADD, DL, VecFloatVT, LowBitcast, FHigh);
12750 SDValue X86TargetLowering::lowerUINT_TO_FP_vec(SDValue Op,
12751 SelectionDAG &DAG) const {
12752 SDValue N0 = Op.getOperand(0);
12753 MVT SVT = N0.getSimpleValueType();
12756 switch (SVT.SimpleTy) {
12758 llvm_unreachable("Custom UINT_TO_FP is not supported!");
12763 MVT NVT = MVT::getVectorVT(MVT::i32, SVT.getVectorNumElements());
12764 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(),
12765 DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, N0));
12769 return lowerUINT_TO_FP_vXi32(Op, DAG, *Subtarget);
12772 assert(Subtarget->hasAVX512());
12773 return DAG.getNode(ISD::UINT_TO_FP, dl, Op.getValueType(),
12774 DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v16i32, N0));
12778 SDValue X86TargetLowering::LowerUINT_TO_FP(SDValue Op,
12779 SelectionDAG &DAG) const {
12780 SDValue N0 = Op.getOperand(0);
12782 auto PtrVT = getPointerTy(DAG.getDataLayout());
12784 if (Op.getSimpleValueType().isVector())
12785 return lowerUINT_TO_FP_vec(Op, DAG);
12787 // Since UINT_TO_FP is legal (it's marked custom), dag combiner won't
12788 // optimize it to a SINT_TO_FP when the sign bit is known zero. Perform
12789 // the optimization here.
12790 if (DAG.SignBitIsZero(N0))
12791 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(), N0);
12793 MVT SrcVT = N0.getSimpleValueType();
12794 MVT DstVT = Op.getSimpleValueType();
12796 if (Subtarget->hasAVX512() && isScalarFPTypeInSSEReg(DstVT) &&
12797 (SrcVT == MVT::i32 || (SrcVT == MVT::i64 && Subtarget->is64Bit()))) {
12798 // Conversions from unsigned i32 to f32/f64 are legal,
12799 // using VCVTUSI2SS/SD. Same for i64 in 64-bit mode.
12803 if (SrcVT == MVT::i64 && DstVT == MVT::f64 && X86ScalarSSEf64)
12804 return LowerUINT_TO_FP_i64(Op, DAG);
12805 if (SrcVT == MVT::i32 && X86ScalarSSEf64)
12806 return LowerUINT_TO_FP_i32(Op, DAG);
12807 if (Subtarget->is64Bit() && SrcVT == MVT::i64 && DstVT == MVT::f32)
12810 // Make a 64-bit buffer, and use it to build an FILD.
12811 SDValue StackSlot = DAG.CreateStackTemporary(MVT::i64);
12812 if (SrcVT == MVT::i32) {
12813 SDValue WordOff = DAG.getConstant(4, dl, PtrVT);
12814 SDValue OffsetSlot = DAG.getNode(ISD::ADD, dl, PtrVT, StackSlot, WordOff);
12815 SDValue Store1 = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
12816 StackSlot, MachinePointerInfo(),
12818 SDValue Store2 = DAG.getStore(Store1, dl, DAG.getConstant(0, dl, MVT::i32),
12819 OffsetSlot, MachinePointerInfo(),
12821 SDValue Fild = BuildFILD(Op, MVT::i64, Store2, StackSlot, DAG);
12825 assert(SrcVT == MVT::i64 && "Unexpected type in UINT_TO_FP");
12826 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
12827 StackSlot, MachinePointerInfo(),
12829 // For i64 source, we need to add the appropriate power of 2 if the input
12830 // was negative. This is the same as the optimization in
12831 // DAGTypeLegalizer::ExpandIntOp_UNIT_TO_FP, and for it to be safe here,
12832 // we must be careful to do the computation in x87 extended precision, not
12833 // in SSE. (The generic code can't know it's OK to do this, or how to.)
12834 int SSFI = cast<FrameIndexSDNode>(StackSlot)->getIndex();
12835 MachineMemOperand *MMO = DAG.getMachineFunction().getMachineMemOperand(
12836 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), SSFI),
12837 MachineMemOperand::MOLoad, 8, 8);
12839 SDVTList Tys = DAG.getVTList(MVT::f80, MVT::Other);
12840 SDValue Ops[] = { Store, StackSlot, DAG.getValueType(MVT::i64) };
12841 SDValue Fild = DAG.getMemIntrinsicNode(X86ISD::FILD, dl, Tys, Ops,
12844 APInt FF(32, 0x5F800000ULL);
12846 // Check whether the sign bit is set.
12847 SDValue SignSet = DAG.getSetCC(
12848 dl, getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), MVT::i64),
12849 Op.getOperand(0), DAG.getConstant(0, dl, MVT::i64), ISD::SETLT);
12851 // Build a 64 bit pair (0, FF) in the constant pool, with FF in the lo bits.
12852 SDValue FudgePtr = DAG.getConstantPool(
12853 ConstantInt::get(*DAG.getContext(), FF.zext(64)), PtrVT);
12855 // Get a pointer to FF if the sign bit was set, or to 0 otherwise.
12856 SDValue Zero = DAG.getIntPtrConstant(0, dl);
12857 SDValue Four = DAG.getIntPtrConstant(4, dl);
12858 SDValue Offset = DAG.getNode(ISD::SELECT, dl, Zero.getValueType(), SignSet,
12860 FudgePtr = DAG.getNode(ISD::ADD, dl, PtrVT, FudgePtr, Offset);
12862 // Load the value out, extending it from f32 to f80.
12863 // FIXME: Avoid the extend by constructing the right constant pool?
12864 SDValue Fudge = DAG.getExtLoad(
12865 ISD::EXTLOAD, dl, MVT::f80, DAG.getEntryNode(), FudgePtr,
12866 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()), MVT::f32,
12867 false, false, false, 4);
12868 // Extend everything to 80 bits to force it to be done on x87.
12869 // TODO: Are there any fast-math-flags to propagate here?
12870 SDValue Add = DAG.getNode(ISD::FADD, dl, MVT::f80, Fild, Fudge);
12871 return DAG.getNode(ISD::FP_ROUND, dl, DstVT, Add,
12872 DAG.getIntPtrConstant(0, dl));
12875 // If the given FP_TO_SINT (IsSigned) or FP_TO_UINT (!IsSigned) operation
12876 // is legal, or has an fp128 or f16 source (which needs to be promoted to f32),
12877 // just return an <SDValue(), SDValue()> pair.
12878 // Otherwise it is assumed to be a conversion from one of f32, f64 or f80
12879 // to i16, i32 or i64, and we lower it to a legal sequence.
12880 // If lowered to the final integer result we return a <result, SDValue()> pair.
12881 // Otherwise we lower it to a sequence ending with a FIST, return a
12882 // <FIST, StackSlot> pair, and the caller is responsible for loading
12883 // the final integer result from StackSlot.
12884 std::pair<SDValue,SDValue>
12885 X86TargetLowering::FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG,
12886 bool IsSigned, bool IsReplace) const {
12889 EVT DstTy = Op.getValueType();
12890 EVT TheVT = Op.getOperand(0).getValueType();
12891 auto PtrVT = getPointerTy(DAG.getDataLayout());
12893 if (TheVT != MVT::f32 && TheVT != MVT::f64 && TheVT != MVT::f80) {
12894 // f16 must be promoted before using the lowering in this routine.
12895 // fp128 does not use this lowering.
12896 return std::make_pair(SDValue(), SDValue());
12899 // If using FIST to compute an unsigned i64, we'll need some fixup
12900 // to handle values above the maximum signed i64. A FIST is always
12901 // used for the 32-bit subtarget, but also for f80 on a 64-bit target.
12902 bool UnsignedFixup = !IsSigned &&
12903 DstTy == MVT::i64 &&
12904 (!Subtarget->is64Bit() ||
12905 !isScalarFPTypeInSSEReg(TheVT));
12907 if (!IsSigned && DstTy != MVT::i64 && !Subtarget->hasAVX512()) {
12908 // Replace the fp-to-uint32 operation with an fp-to-sint64 FIST.
12909 // The low 32 bits of the fist result will have the correct uint32 result.
12910 assert(DstTy == MVT::i32 && "Unexpected FP_TO_UINT");
12914 assert(DstTy.getSimpleVT() <= MVT::i64 &&
12915 DstTy.getSimpleVT() >= MVT::i16 &&
12916 "Unknown FP_TO_INT to lower!");
12918 // These are really Legal.
12919 if (DstTy == MVT::i32 &&
12920 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
12921 return std::make_pair(SDValue(), SDValue());
12922 if (Subtarget->is64Bit() &&
12923 DstTy == MVT::i64 &&
12924 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
12925 return std::make_pair(SDValue(), SDValue());
12927 // We lower FP->int64 into FISTP64 followed by a load from a temporary
12929 MachineFunction &MF = DAG.getMachineFunction();
12930 unsigned MemSize = DstTy.getSizeInBits()/8;
12931 int SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
12932 SDValue StackSlot = DAG.getFrameIndex(SSFI, PtrVT);
12935 switch (DstTy.getSimpleVT().SimpleTy) {
12936 default: llvm_unreachable("Invalid FP_TO_SINT to lower!");
12937 case MVT::i16: Opc = X86ISD::FP_TO_INT16_IN_MEM; break;
12938 case MVT::i32: Opc = X86ISD::FP_TO_INT32_IN_MEM; break;
12939 case MVT::i64: Opc = X86ISD::FP_TO_INT64_IN_MEM; break;
12942 SDValue Chain = DAG.getEntryNode();
12943 SDValue Value = Op.getOperand(0);
12944 SDValue Adjust; // 0x0 or 0x80000000, for result sign bit adjustment.
12946 if (UnsignedFixup) {
12948 // Conversion to unsigned i64 is implemented with a select,
12949 // depending on whether the source value fits in the range
12950 // of a signed i64. Let Thresh be the FP equivalent of
12951 // 0x8000000000000000ULL.
12953 // Adjust i32 = (Value < Thresh) ? 0 : 0x80000000;
12954 // FistSrc = (Value < Thresh) ? Value : (Value - Thresh);
12955 // Fist-to-mem64 FistSrc
12956 // Add 0 or 0x800...0ULL to the 64-bit result, which is equivalent
12957 // to XOR'ing the high 32 bits with Adjust.
12959 // Being a power of 2, Thresh is exactly representable in all FP formats.
12960 // For X87 we'd like to use the smallest FP type for this constant, but
12961 // for DAG type consistency we have to match the FP operand type.
12963 APFloat Thresh(APFloat::IEEEsingle, APInt(32, 0x5f000000));
12964 LLVM_ATTRIBUTE_UNUSED APFloat::opStatus Status = APFloat::opOK;
12965 bool LosesInfo = false;
12966 if (TheVT == MVT::f64)
12967 // The rounding mode is irrelevant as the conversion should be exact.
12968 Status = Thresh.convert(APFloat::IEEEdouble, APFloat::rmNearestTiesToEven,
12970 else if (TheVT == MVT::f80)
12971 Status = Thresh.convert(APFloat::x87DoubleExtended,
12972 APFloat::rmNearestTiesToEven, &LosesInfo);
12974 assert(Status == APFloat::opOK && !LosesInfo &&
12975 "FP conversion should have been exact");
12977 SDValue ThreshVal = DAG.getConstantFP(Thresh, DL, TheVT);
12979 SDValue Cmp = DAG.getSetCC(DL,
12980 getSetCCResultType(DAG.getDataLayout(),
12981 *DAG.getContext(), TheVT),
12982 Value, ThreshVal, ISD::SETLT);
12983 Adjust = DAG.getSelect(DL, MVT::i32, Cmp,
12984 DAG.getConstant(0, DL, MVT::i32),
12985 DAG.getConstant(0x80000000, DL, MVT::i32));
12986 SDValue Sub = DAG.getNode(ISD::FSUB, DL, TheVT, Value, ThreshVal);
12987 Cmp = DAG.getSetCC(DL, getSetCCResultType(DAG.getDataLayout(),
12988 *DAG.getContext(), TheVT),
12989 Value, ThreshVal, ISD::SETLT);
12990 Value = DAG.getSelect(DL, TheVT, Cmp, Value, Sub);
12993 // FIXME This causes a redundant load/store if the SSE-class value is already
12994 // in memory, such as if it is on the callstack.
12995 if (isScalarFPTypeInSSEReg(TheVT)) {
12996 assert(DstTy == MVT::i64 && "Invalid FP_TO_SINT to lower!");
12997 Chain = DAG.getStore(Chain, DL, Value, StackSlot,
12998 MachinePointerInfo::getFixedStack(MF, SSFI), false,
13000 SDVTList Tys = DAG.getVTList(Op.getOperand(0).getValueType(), MVT::Other);
13002 Chain, StackSlot, DAG.getValueType(TheVT)
13005 MachineMemOperand *MMO =
13006 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(MF, SSFI),
13007 MachineMemOperand::MOLoad, MemSize, MemSize);
13008 Value = DAG.getMemIntrinsicNode(X86ISD::FLD, DL, Tys, Ops, DstTy, MMO);
13009 Chain = Value.getValue(1);
13010 SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
13011 StackSlot = DAG.getFrameIndex(SSFI, PtrVT);
13014 MachineMemOperand *MMO =
13015 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(MF, SSFI),
13016 MachineMemOperand::MOStore, MemSize, MemSize);
13018 if (UnsignedFixup) {
13020 // Insert the FIST, load its result as two i32's,
13021 // and XOR the high i32 with Adjust.
13023 SDValue FistOps[] = { Chain, Value, StackSlot };
13024 SDValue FIST = DAG.getMemIntrinsicNode(Opc, DL, DAG.getVTList(MVT::Other),
13025 FistOps, DstTy, MMO);
13027 SDValue Low32 = DAG.getLoad(MVT::i32, DL, FIST, StackSlot,
13028 MachinePointerInfo(),
13029 false, false, false, 0);
13030 SDValue HighAddr = DAG.getNode(ISD::ADD, DL, PtrVT, StackSlot,
13031 DAG.getConstant(4, DL, PtrVT));
13033 SDValue High32 = DAG.getLoad(MVT::i32, DL, FIST, HighAddr,
13034 MachinePointerInfo(),
13035 false, false, false, 0);
13036 High32 = DAG.getNode(ISD::XOR, DL, MVT::i32, High32, Adjust);
13038 if (Subtarget->is64Bit()) {
13039 // Join High32 and Low32 into a 64-bit result.
13040 // (High32 << 32) | Low32
13041 Low32 = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i64, Low32);
13042 High32 = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, High32);
13043 High32 = DAG.getNode(ISD::SHL, DL, MVT::i64, High32,
13044 DAG.getConstant(32, DL, MVT::i8));
13045 SDValue Result = DAG.getNode(ISD::OR, DL, MVT::i64, High32, Low32);
13046 return std::make_pair(Result, SDValue());
13049 SDValue ResultOps[] = { Low32, High32 };
13051 SDValue pair = IsReplace
13052 ? DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, ResultOps)
13053 : DAG.getMergeValues(ResultOps, DL);
13054 return std::make_pair(pair, SDValue());
13056 // Build the FP_TO_INT*_IN_MEM
13057 SDValue Ops[] = { Chain, Value, StackSlot };
13058 SDValue FIST = DAG.getMemIntrinsicNode(Opc, DL, DAG.getVTList(MVT::Other),
13060 return std::make_pair(FIST, StackSlot);
13064 static SDValue LowerAVXExtend(SDValue Op, SelectionDAG &DAG,
13065 const X86Subtarget *Subtarget) {
13066 MVT VT = Op->getSimpleValueType(0);
13067 SDValue In = Op->getOperand(0);
13068 MVT InVT = In.getSimpleValueType();
13071 if (VT.is512BitVector() || InVT.getVectorElementType() == MVT::i1)
13072 return DAG.getNode(ISD::ZERO_EXTEND, dl, VT, In);
13074 // Optimize vectors in AVX mode:
13077 // Use vpunpcklwd for 4 lower elements v8i16 -> v4i32.
13078 // Use vpunpckhwd for 4 upper elements v8i16 -> v4i32.
13079 // Concat upper and lower parts.
13082 // Use vpunpckldq for 4 lower elements v4i32 -> v2i64.
13083 // Use vpunpckhdq for 4 upper elements v4i32 -> v2i64.
13084 // Concat upper and lower parts.
13087 if (((VT != MVT::v16i16) || (InVT != MVT::v16i8)) &&
13088 ((VT != MVT::v8i32) || (InVT != MVT::v8i16)) &&
13089 ((VT != MVT::v4i64) || (InVT != MVT::v4i32)))
13092 if (Subtarget->hasInt256())
13093 return DAG.getNode(X86ISD::VZEXT, dl, VT, In);
13095 SDValue ZeroVec = getZeroVector(InVT, Subtarget, DAG, dl);
13096 SDValue Undef = DAG.getUNDEF(InVT);
13097 bool NeedZero = Op.getOpcode() == ISD::ZERO_EXTEND;
13098 SDValue OpLo = getUnpackl(DAG, dl, InVT, In, NeedZero ? ZeroVec : Undef);
13099 SDValue OpHi = getUnpackh(DAG, dl, InVT, In, NeedZero ? ZeroVec : Undef);
13101 MVT HVT = MVT::getVectorVT(VT.getVectorElementType(),
13102 VT.getVectorNumElements()/2);
13104 OpLo = DAG.getBitcast(HVT, OpLo);
13105 OpHi = DAG.getBitcast(HVT, OpHi);
13107 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi);
13110 static SDValue LowerZERO_EXTEND_AVX512(SDValue Op,
13111 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
13112 MVT VT = Op->getSimpleValueType(0);
13113 SDValue In = Op->getOperand(0);
13114 MVT InVT = In.getSimpleValueType();
13116 unsigned int NumElts = VT.getVectorNumElements();
13117 if (NumElts != 8 && NumElts != 16 && !Subtarget->hasBWI())
13120 if (VT.is512BitVector() && InVT.getVectorElementType() != MVT::i1)
13121 return DAG.getNode(X86ISD::VZEXT, DL, VT, In);
13123 assert(InVT.getVectorElementType() == MVT::i1);
13124 MVT ExtVT = NumElts == 8 ? MVT::v8i64 : MVT::v16i32;
13126 DAG.getConstant(APInt(ExtVT.getScalarSizeInBits(), 1), DL, ExtVT);
13128 DAG.getConstant(APInt::getNullValue(ExtVT.getScalarSizeInBits()), DL, ExtVT);
13130 SDValue V = DAG.getNode(ISD::VSELECT, DL, ExtVT, In, One, Zero);
13131 if (VT.is512BitVector())
13133 return DAG.getNode(X86ISD::VTRUNC, DL, VT, V);
13136 static SDValue LowerANY_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
13137 SelectionDAG &DAG) {
13138 if (Subtarget->hasFp256())
13139 if (SDValue Res = LowerAVXExtend(Op, DAG, Subtarget))
13145 static SDValue LowerZERO_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
13146 SelectionDAG &DAG) {
13148 MVT VT = Op.getSimpleValueType();
13149 SDValue In = Op.getOperand(0);
13150 MVT SVT = In.getSimpleValueType();
13152 if (VT.is512BitVector() || SVT.getVectorElementType() == MVT::i1)
13153 return LowerZERO_EXTEND_AVX512(Op, Subtarget, DAG);
13155 if (Subtarget->hasFp256())
13156 if (SDValue Res = LowerAVXExtend(Op, DAG, Subtarget))
13159 assert(!VT.is256BitVector() || !SVT.is128BitVector() ||
13160 VT.getVectorNumElements() != SVT.getVectorNumElements());
13164 SDValue X86TargetLowering::LowerTRUNCATE(SDValue Op, SelectionDAG &DAG) const {
13166 MVT VT = Op.getSimpleValueType();
13167 SDValue In = Op.getOperand(0);
13168 MVT InVT = In.getSimpleValueType();
13170 if (VT == MVT::i1) {
13171 assert((InVT.isInteger() && (InVT.getSizeInBits() <= 64)) &&
13172 "Invalid scalar TRUNCATE operation");
13173 if (InVT.getSizeInBits() >= 32)
13175 In = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i32, In);
13176 return DAG.getNode(ISD::TRUNCATE, DL, VT, In);
13178 assert(VT.getVectorNumElements() == InVT.getVectorNumElements() &&
13179 "Invalid TRUNCATE operation");
13181 // move vector to mask - truncate solution for SKX
13182 if (VT.getVectorElementType() == MVT::i1) {
13183 if (InVT.is512BitVector() && InVT.getScalarSizeInBits() <= 16 &&
13184 Subtarget->hasBWI())
13185 return Op; // legal, will go to VPMOVB2M, VPMOVW2M
13186 if ((InVT.is256BitVector() || InVT.is128BitVector())
13187 && InVT.getScalarSizeInBits() <= 16 &&
13188 Subtarget->hasBWI() && Subtarget->hasVLX())
13189 return Op; // legal, will go to VPMOVB2M, VPMOVW2M
13190 if (InVT.is512BitVector() && InVT.getScalarSizeInBits() >= 32 &&
13191 Subtarget->hasDQI())
13192 return Op; // legal, will go to VPMOVD2M, VPMOVQ2M
13193 if ((InVT.is256BitVector() || InVT.is128BitVector())
13194 && InVT.getScalarSizeInBits() >= 32 &&
13195 Subtarget->hasDQI() && Subtarget->hasVLX())
13196 return Op; // legal, will go to VPMOVB2M, VPMOVQ2M
13199 if (VT.getVectorElementType() == MVT::i1) {
13200 assert(VT.getVectorElementType() == MVT::i1 && "Unexpected vector type");
13201 unsigned NumElts = InVT.getVectorNumElements();
13202 assert ((NumElts == 8 || NumElts == 16) && "Unexpected vector type");
13203 if (InVT.getSizeInBits() < 512) {
13204 MVT ExtVT = (NumElts == 16)? MVT::v16i32 : MVT::v8i64;
13205 In = DAG.getNode(ISD::SIGN_EXTEND, DL, ExtVT, In);
13210 DAG.getConstant(APInt::getSignBit(InVT.getScalarSizeInBits()), DL, InVT);
13211 SDValue And = DAG.getNode(ISD::AND, DL, InVT, OneV, In);
13212 return DAG.getNode(X86ISD::TESTM, DL, VT, And, And);
13215 // vpmovqb/w/d, vpmovdb/w, vpmovwb
13216 if (Subtarget->hasAVX512()) {
13217 // word to byte only under BWI
13218 if (InVT == MVT::v16i16 && !Subtarget->hasBWI()) // v16i16 -> v16i8
13219 return DAG.getNode(X86ISD::VTRUNC, DL, VT,
13220 DAG.getNode(X86ISD::VSEXT, DL, MVT::v16i32, In));
13221 return DAG.getNode(X86ISD::VTRUNC, DL, VT, In);
13223 if ((VT == MVT::v4i32) && (InVT == MVT::v4i64)) {
13224 // On AVX2, v4i64 -> v4i32 becomes VPERMD.
13225 if (Subtarget->hasInt256()) {
13226 static const int ShufMask[] = {0, 2, 4, 6, -1, -1, -1, -1};
13227 In = DAG.getBitcast(MVT::v8i32, In);
13228 In = DAG.getVectorShuffle(MVT::v8i32, DL, In, DAG.getUNDEF(MVT::v8i32),
13230 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, In,
13231 DAG.getIntPtrConstant(0, DL));
13234 SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
13235 DAG.getIntPtrConstant(0, DL));
13236 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
13237 DAG.getIntPtrConstant(2, DL));
13238 OpLo = DAG.getBitcast(MVT::v4i32, OpLo);
13239 OpHi = DAG.getBitcast(MVT::v4i32, OpHi);
13240 static const int ShufMask[] = {0, 2, 4, 6};
13241 return DAG.getVectorShuffle(VT, DL, OpLo, OpHi, ShufMask);
13244 if ((VT == MVT::v8i16) && (InVT == MVT::v8i32)) {
13245 // On AVX2, v8i32 -> v8i16 becomed PSHUFB.
13246 if (Subtarget->hasInt256()) {
13247 In = DAG.getBitcast(MVT::v32i8, In);
13249 SmallVector<SDValue,32> pshufbMask;
13250 for (unsigned i = 0; i < 2; ++i) {
13251 pshufbMask.push_back(DAG.getConstant(0x0, DL, MVT::i8));
13252 pshufbMask.push_back(DAG.getConstant(0x1, DL, MVT::i8));
13253 pshufbMask.push_back(DAG.getConstant(0x4, DL, MVT::i8));
13254 pshufbMask.push_back(DAG.getConstant(0x5, DL, MVT::i8));
13255 pshufbMask.push_back(DAG.getConstant(0x8, DL, MVT::i8));
13256 pshufbMask.push_back(DAG.getConstant(0x9, DL, MVT::i8));
13257 pshufbMask.push_back(DAG.getConstant(0xc, DL, MVT::i8));
13258 pshufbMask.push_back(DAG.getConstant(0xd, DL, MVT::i8));
13259 for (unsigned j = 0; j < 8; ++j)
13260 pshufbMask.push_back(DAG.getConstant(0x80, DL, MVT::i8));
13262 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v32i8, pshufbMask);
13263 In = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v32i8, In, BV);
13264 In = DAG.getBitcast(MVT::v4i64, In);
13266 static const int ShufMask[] = {0, 2, -1, -1};
13267 In = DAG.getVectorShuffle(MVT::v4i64, DL, In, DAG.getUNDEF(MVT::v4i64),
13269 In = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
13270 DAG.getIntPtrConstant(0, DL));
13271 return DAG.getBitcast(VT, In);
13274 SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v4i32, In,
13275 DAG.getIntPtrConstant(0, DL));
13277 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v4i32, In,
13278 DAG.getIntPtrConstant(4, DL));
13280 OpLo = DAG.getBitcast(MVT::v16i8, OpLo);
13281 OpHi = DAG.getBitcast(MVT::v16i8, OpHi);
13283 // The PSHUFB mask:
13284 static const int ShufMask1[] = {0, 1, 4, 5, 8, 9, 12, 13,
13285 -1, -1, -1, -1, -1, -1, -1, -1};
13287 SDValue Undef = DAG.getUNDEF(MVT::v16i8);
13288 OpLo = DAG.getVectorShuffle(MVT::v16i8, DL, OpLo, Undef, ShufMask1);
13289 OpHi = DAG.getVectorShuffle(MVT::v16i8, DL, OpHi, Undef, ShufMask1);
13291 OpLo = DAG.getBitcast(MVT::v4i32, OpLo);
13292 OpHi = DAG.getBitcast(MVT::v4i32, OpHi);
13294 // The MOVLHPS Mask:
13295 static const int ShufMask2[] = {0, 1, 4, 5};
13296 SDValue res = DAG.getVectorShuffle(MVT::v4i32, DL, OpLo, OpHi, ShufMask2);
13297 return DAG.getBitcast(MVT::v8i16, res);
13300 // Handle truncation of V256 to V128 using shuffles.
13301 if (!VT.is128BitVector() || !InVT.is256BitVector())
13304 assert(Subtarget->hasFp256() && "256-bit vector without AVX!");
13306 unsigned NumElems = VT.getVectorNumElements();
13307 MVT NVT = MVT::getVectorVT(VT.getVectorElementType(), NumElems * 2);
13309 SmallVector<int, 16> MaskVec(NumElems * 2, -1);
13310 // Prepare truncation shuffle mask
13311 for (unsigned i = 0; i != NumElems; ++i)
13312 MaskVec[i] = i * 2;
13313 SDValue V = DAG.getVectorShuffle(NVT, DL, DAG.getBitcast(NVT, In),
13314 DAG.getUNDEF(NVT), &MaskVec[0]);
13315 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, V,
13316 DAG.getIntPtrConstant(0, DL));
13319 SDValue X86TargetLowering::LowerFP_TO_SINT(SDValue Op,
13320 SelectionDAG &DAG) const {
13321 assert(!Op.getSimpleValueType().isVector());
13323 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG,
13324 /*IsSigned=*/ true, /*IsReplace=*/ false);
13325 SDValue FIST = Vals.first, StackSlot = Vals.second;
13326 // If FP_TO_INTHelper failed, the node is actually supposed to be Legal.
13327 if (!FIST.getNode())
13330 if (StackSlot.getNode())
13331 // Load the result.
13332 return DAG.getLoad(Op.getValueType(), SDLoc(Op),
13333 FIST, StackSlot, MachinePointerInfo(),
13334 false, false, false, 0);
13336 // The node is the result.
13340 SDValue X86TargetLowering::LowerFP_TO_UINT(SDValue Op,
13341 SelectionDAG &DAG) const {
13342 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG,
13343 /*IsSigned=*/ false, /*IsReplace=*/ false);
13344 SDValue FIST = Vals.first, StackSlot = Vals.second;
13345 // If FP_TO_INTHelper failed, the node is actually supposed to be Legal.
13346 if (!FIST.getNode())
13349 if (StackSlot.getNode())
13350 // Load the result.
13351 return DAG.getLoad(Op.getValueType(), SDLoc(Op),
13352 FIST, StackSlot, MachinePointerInfo(),
13353 false, false, false, 0);
13355 // The node is the result.
13359 static SDValue LowerFP_EXTEND(SDValue Op, SelectionDAG &DAG) {
13361 MVT VT = Op.getSimpleValueType();
13362 SDValue In = Op.getOperand(0);
13363 MVT SVT = In.getSimpleValueType();
13365 assert(SVT == MVT::v2f32 && "Only customize MVT::v2f32 type legalization!");
13367 return DAG.getNode(X86ISD::VFPEXT, DL, VT,
13368 DAG.getNode(ISD::CONCAT_VECTORS, DL, MVT::v4f32,
13369 In, DAG.getUNDEF(SVT)));
13372 /// The only differences between FABS and FNEG are the mask and the logic op.
13373 /// FNEG also has a folding opportunity for FNEG(FABS(x)).
13374 static SDValue LowerFABSorFNEG(SDValue Op, SelectionDAG &DAG) {
13375 assert((Op.getOpcode() == ISD::FABS || Op.getOpcode() == ISD::FNEG) &&
13376 "Wrong opcode for lowering FABS or FNEG.");
13378 bool IsFABS = (Op.getOpcode() == ISD::FABS);
13380 // If this is a FABS and it has an FNEG user, bail out to fold the combination
13381 // into an FNABS. We'll lower the FABS after that if it is still in use.
13383 for (SDNode *User : Op->uses())
13384 if (User->getOpcode() == ISD::FNEG)
13388 MVT VT = Op.getSimpleValueType();
13390 // FIXME: Use function attribute "OptimizeForSize" and/or CodeGenOpt::Level to
13391 // decide if we should generate a 16-byte constant mask when we only need 4 or
13392 // 8 bytes for the scalar case.
13398 if (VT.isVector()) {
13400 EltVT = VT.getVectorElementType();
13401 NumElts = VT.getVectorNumElements();
13403 // There are no scalar bitwise logical SSE/AVX instructions, so we
13404 // generate a 16-byte vector constant and logic op even for the scalar case.
13405 // Using a 16-byte mask allows folding the load of the mask with
13406 // the logic op, so it can save (~4 bytes) on code size.
13407 LogicVT = (VT == MVT::f64) ? MVT::v2f64 : MVT::v4f32;
13409 NumElts = (VT == MVT::f64) ? 2 : 4;
13412 unsigned EltBits = EltVT.getSizeInBits();
13413 LLVMContext *Context = DAG.getContext();
13414 // For FABS, mask is 0x7f...; for FNEG, mask is 0x80...
13416 IsFABS ? APInt::getSignedMaxValue(EltBits) : APInt::getSignBit(EltBits);
13417 Constant *C = ConstantInt::get(*Context, MaskElt);
13418 C = ConstantVector::getSplat(NumElts, C);
13419 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
13420 SDValue CPIdx = DAG.getConstantPool(C, TLI.getPointerTy(DAG.getDataLayout()));
13421 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
13423 DAG.getLoad(LogicVT, dl, DAG.getEntryNode(), CPIdx,
13424 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()),
13425 false, false, false, Alignment);
13427 SDValue Op0 = Op.getOperand(0);
13428 bool IsFNABS = !IsFABS && (Op0.getOpcode() == ISD::FABS);
13430 IsFABS ? X86ISD::FAND : IsFNABS ? X86ISD::FOR : X86ISD::FXOR;
13431 SDValue Operand = IsFNABS ? Op0.getOperand(0) : Op0;
13434 return DAG.getNode(LogicOp, dl, LogicVT, Operand, Mask);
13436 // For the scalar case extend to a 128-bit vector, perform the logic op,
13437 // and extract the scalar result back out.
13438 Operand = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, LogicVT, Operand);
13439 SDValue LogicNode = DAG.getNode(LogicOp, dl, LogicVT, Operand, Mask);
13440 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, LogicNode,
13441 DAG.getIntPtrConstant(0, dl));
13444 static SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) {
13445 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
13446 LLVMContext *Context = DAG.getContext();
13447 SDValue Op0 = Op.getOperand(0);
13448 SDValue Op1 = Op.getOperand(1);
13450 MVT VT = Op.getSimpleValueType();
13451 MVT SrcVT = Op1.getSimpleValueType();
13453 // If second operand is smaller, extend it first.
13454 if (SrcVT.bitsLT(VT)) {
13455 Op1 = DAG.getNode(ISD::FP_EXTEND, dl, VT, Op1);
13458 // And if it is bigger, shrink it first.
13459 if (SrcVT.bitsGT(VT)) {
13460 Op1 = DAG.getNode(ISD::FP_ROUND, dl, VT, Op1, DAG.getIntPtrConstant(1, dl));
13464 // At this point the operands and the result should have the same
13465 // type, and that won't be f80 since that is not custom lowered.
13467 const fltSemantics &Sem =
13468 VT == MVT::f64 ? APFloat::IEEEdouble : APFloat::IEEEsingle;
13469 const unsigned SizeInBits = VT.getSizeInBits();
13471 SmallVector<Constant *, 4> CV(
13472 VT == MVT::f64 ? 2 : 4,
13473 ConstantFP::get(*Context, APFloat(Sem, APInt(SizeInBits, 0))));
13475 // First, clear all bits but the sign bit from the second operand (sign).
13476 CV[0] = ConstantFP::get(*Context,
13477 APFloat(Sem, APInt::getHighBitsSet(SizeInBits, 1)));
13478 Constant *C = ConstantVector::get(CV);
13479 auto PtrVT = TLI.getPointerTy(DAG.getDataLayout());
13480 SDValue CPIdx = DAG.getConstantPool(C, PtrVT, 16);
13482 // Perform all logic operations as 16-byte vectors because there are no
13483 // scalar FP logic instructions in SSE. This allows load folding of the
13484 // constants into the logic instructions.
13485 MVT LogicVT = (VT == MVT::f64) ? MVT::v2f64 : MVT::v4f32;
13487 DAG.getLoad(LogicVT, dl, DAG.getEntryNode(), CPIdx,
13488 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()),
13489 false, false, false, 16);
13490 Op1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, LogicVT, Op1);
13491 SDValue SignBit = DAG.getNode(X86ISD::FAND, dl, LogicVT, Op1, Mask1);
13493 // Next, clear the sign bit from the first operand (magnitude).
13494 // If it's a constant, we can clear it here.
13495 if (ConstantFPSDNode *Op0CN = dyn_cast<ConstantFPSDNode>(Op0)) {
13496 APFloat APF = Op0CN->getValueAPF();
13497 // If the magnitude is a positive zero, the sign bit alone is enough.
13498 if (APF.isPosZero())
13499 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, SrcVT, SignBit,
13500 DAG.getIntPtrConstant(0, dl));
13502 CV[0] = ConstantFP::get(*Context, APF);
13504 CV[0] = ConstantFP::get(
13506 APFloat(Sem, APInt::getLowBitsSet(SizeInBits, SizeInBits - 1)));
13508 C = ConstantVector::get(CV);
13509 CPIdx = DAG.getConstantPool(C, PtrVT, 16);
13511 DAG.getLoad(LogicVT, dl, DAG.getEntryNode(), CPIdx,
13512 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()),
13513 false, false, false, 16);
13514 // If the magnitude operand wasn't a constant, we need to AND out the sign.
13515 if (!isa<ConstantFPSDNode>(Op0)) {
13516 Op0 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, LogicVT, Op0);
13517 Val = DAG.getNode(X86ISD::FAND, dl, LogicVT, Op0, Val);
13519 // OR the magnitude value with the sign bit.
13520 Val = DAG.getNode(X86ISD::FOR, dl, LogicVT, Val, SignBit);
13521 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, SrcVT, Val,
13522 DAG.getIntPtrConstant(0, dl));
13525 static SDValue LowerFGETSIGN(SDValue Op, SelectionDAG &DAG) {
13526 SDValue N0 = Op.getOperand(0);
13528 MVT VT = Op.getSimpleValueType();
13530 // Lower ISD::FGETSIGN to (AND (X86ISD::FGETSIGNx86 ...) 1).
13531 SDValue xFGETSIGN = DAG.getNode(X86ISD::FGETSIGNx86, dl, VT, N0,
13532 DAG.getConstant(1, dl, VT));
13533 return DAG.getNode(ISD::AND, dl, VT, xFGETSIGN, DAG.getConstant(1, dl, VT));
13536 // Check whether an OR'd tree is PTEST-able.
13537 static SDValue LowerVectorAllZeroTest(SDValue Op, const X86Subtarget *Subtarget,
13538 SelectionDAG &DAG) {
13539 assert(Op.getOpcode() == ISD::OR && "Only check OR'd tree.");
13541 if (!Subtarget->hasSSE41())
13544 if (!Op->hasOneUse())
13547 SDNode *N = Op.getNode();
13550 SmallVector<SDValue, 8> Opnds;
13551 DenseMap<SDValue, unsigned> VecInMap;
13552 SmallVector<SDValue, 8> VecIns;
13553 EVT VT = MVT::Other;
13555 // Recognize a special case where a vector is casted into wide integer to
13557 Opnds.push_back(N->getOperand(0));
13558 Opnds.push_back(N->getOperand(1));
13560 for (unsigned Slot = 0, e = Opnds.size(); Slot < e; ++Slot) {
13561 SmallVectorImpl<SDValue>::const_iterator I = Opnds.begin() + Slot;
13562 // BFS traverse all OR'd operands.
13563 if (I->getOpcode() == ISD::OR) {
13564 Opnds.push_back(I->getOperand(0));
13565 Opnds.push_back(I->getOperand(1));
13566 // Re-evaluate the number of nodes to be traversed.
13567 e += 2; // 2 more nodes (LHS and RHS) are pushed.
13571 // Quit if a non-EXTRACT_VECTOR_ELT
13572 if (I->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
13575 // Quit if without a constant index.
13576 SDValue Idx = I->getOperand(1);
13577 if (!isa<ConstantSDNode>(Idx))
13580 SDValue ExtractedFromVec = I->getOperand(0);
13581 DenseMap<SDValue, unsigned>::iterator M = VecInMap.find(ExtractedFromVec);
13582 if (M == VecInMap.end()) {
13583 VT = ExtractedFromVec.getValueType();
13584 // Quit if not 128/256-bit vector.
13585 if (!VT.is128BitVector() && !VT.is256BitVector())
13587 // Quit if not the same type.
13588 if (VecInMap.begin() != VecInMap.end() &&
13589 VT != VecInMap.begin()->first.getValueType())
13591 M = VecInMap.insert(std::make_pair(ExtractedFromVec, 0)).first;
13592 VecIns.push_back(ExtractedFromVec);
13594 M->second |= 1U << cast<ConstantSDNode>(Idx)->getZExtValue();
13597 assert((VT.is128BitVector() || VT.is256BitVector()) &&
13598 "Not extracted from 128-/256-bit vector.");
13600 unsigned FullMask = (1U << VT.getVectorNumElements()) - 1U;
13602 for (DenseMap<SDValue, unsigned>::const_iterator
13603 I = VecInMap.begin(), E = VecInMap.end(); I != E; ++I) {
13604 // Quit if not all elements are used.
13605 if (I->second != FullMask)
13609 MVT TestVT = VT.is128BitVector() ? MVT::v2i64 : MVT::v4i64;
13611 // Cast all vectors into TestVT for PTEST.
13612 for (unsigned i = 0, e = VecIns.size(); i < e; ++i)
13613 VecIns[i] = DAG.getBitcast(TestVT, VecIns[i]);
13615 // If more than one full vectors are evaluated, OR them first before PTEST.
13616 for (unsigned Slot = 0, e = VecIns.size(); e - Slot > 1; Slot += 2, e += 1) {
13617 // Each iteration will OR 2 nodes and append the result until there is only
13618 // 1 node left, i.e. the final OR'd value of all vectors.
13619 SDValue LHS = VecIns[Slot];
13620 SDValue RHS = VecIns[Slot + 1];
13621 VecIns.push_back(DAG.getNode(ISD::OR, DL, TestVT, LHS, RHS));
13624 return DAG.getNode(X86ISD::PTEST, DL, MVT::i32,
13625 VecIns.back(), VecIns.back());
13628 /// \brief return true if \c Op has a use that doesn't just read flags.
13629 static bool hasNonFlagsUse(SDValue Op) {
13630 for (SDNode::use_iterator UI = Op->use_begin(), UE = Op->use_end(); UI != UE;
13632 SDNode *User = *UI;
13633 unsigned UOpNo = UI.getOperandNo();
13634 if (User->getOpcode() == ISD::TRUNCATE && User->hasOneUse()) {
13635 // Look pass truncate.
13636 UOpNo = User->use_begin().getOperandNo();
13637 User = *User->use_begin();
13640 if (User->getOpcode() != ISD::BRCOND && User->getOpcode() != ISD::SETCC &&
13641 !(User->getOpcode() == ISD::SELECT && UOpNo == 0))
13647 /// Emit nodes that will be selected as "test Op0,Op0", or something
13649 SDValue X86TargetLowering::EmitTest(SDValue Op, unsigned X86CC, SDLoc dl,
13650 SelectionDAG &DAG) const {
13651 if (Op.getValueType() == MVT::i1) {
13652 SDValue ExtOp = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i8, Op);
13653 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, ExtOp,
13654 DAG.getConstant(0, dl, MVT::i8));
13656 // CF and OF aren't always set the way we want. Determine which
13657 // of these we need.
13658 bool NeedCF = false;
13659 bool NeedOF = false;
13662 case X86::COND_A: case X86::COND_AE:
13663 case X86::COND_B: case X86::COND_BE:
13666 case X86::COND_G: case X86::COND_GE:
13667 case X86::COND_L: case X86::COND_LE:
13668 case X86::COND_O: case X86::COND_NO: {
13669 // Check if we really need to set the
13670 // Overflow flag. If NoSignedWrap is present
13671 // that is not actually needed.
13672 switch (Op->getOpcode()) {
13677 const auto *BinNode = cast<BinaryWithFlagsSDNode>(Op.getNode());
13678 if (BinNode->Flags.hasNoSignedWrap())
13688 // See if we can use the EFLAGS value from the operand instead of
13689 // doing a separate TEST. TEST always sets OF and CF to 0, so unless
13690 // we prove that the arithmetic won't overflow, we can't use OF or CF.
13691 if (Op.getResNo() != 0 || NeedOF || NeedCF) {
13692 // Emit a CMP with 0, which is the TEST pattern.
13693 //if (Op.getValueType() == MVT::i1)
13694 // return DAG.getNode(X86ISD::CMP, dl, MVT::i1, Op,
13695 // DAG.getConstant(0, MVT::i1));
13696 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
13697 DAG.getConstant(0, dl, Op.getValueType()));
13699 unsigned Opcode = 0;
13700 unsigned NumOperands = 0;
13702 // Truncate operations may prevent the merge of the SETCC instruction
13703 // and the arithmetic instruction before it. Attempt to truncate the operands
13704 // of the arithmetic instruction and use a reduced bit-width instruction.
13705 bool NeedTruncation = false;
13706 SDValue ArithOp = Op;
13707 if (Op->getOpcode() == ISD::TRUNCATE && Op->hasOneUse()) {
13708 SDValue Arith = Op->getOperand(0);
13709 // Both the trunc and the arithmetic op need to have one user each.
13710 if (Arith->hasOneUse())
13711 switch (Arith.getOpcode()) {
13718 NeedTruncation = true;
13724 // NOTICE: In the code below we use ArithOp to hold the arithmetic operation
13725 // which may be the result of a CAST. We use the variable 'Op', which is the
13726 // non-casted variable when we check for possible users.
13727 switch (ArithOp.getOpcode()) {
13729 // Due to an isel shortcoming, be conservative if this add is likely to be
13730 // selected as part of a load-modify-store instruction. When the root node
13731 // in a match is a store, isel doesn't know how to remap non-chain non-flag
13732 // uses of other nodes in the match, such as the ADD in this case. This
13733 // leads to the ADD being left around and reselected, with the result being
13734 // two adds in the output. Alas, even if none our users are stores, that
13735 // doesn't prove we're O.K. Ergo, if we have any parents that aren't
13736 // CopyToReg or SETCC, eschew INC/DEC. A better fix seems to require
13737 // climbing the DAG back to the root, and it doesn't seem to be worth the
13739 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
13740 UE = Op.getNode()->use_end(); UI != UE; ++UI)
13741 if (UI->getOpcode() != ISD::CopyToReg &&
13742 UI->getOpcode() != ISD::SETCC &&
13743 UI->getOpcode() != ISD::STORE)
13746 if (ConstantSDNode *C =
13747 dyn_cast<ConstantSDNode>(ArithOp.getNode()->getOperand(1))) {
13748 // An add of one will be selected as an INC.
13749 if (C->isOne() && !Subtarget->slowIncDec()) {
13750 Opcode = X86ISD::INC;
13755 // An add of negative one (subtract of one) will be selected as a DEC.
13756 if (C->isAllOnesValue() && !Subtarget->slowIncDec()) {
13757 Opcode = X86ISD::DEC;
13763 // Otherwise use a regular EFLAGS-setting add.
13764 Opcode = X86ISD::ADD;
13769 // If we have a constant logical shift that's only used in a comparison
13770 // against zero turn it into an equivalent AND. This allows turning it into
13771 // a TEST instruction later.
13772 if ((X86CC == X86::COND_E || X86CC == X86::COND_NE) && Op->hasOneUse() &&
13773 isa<ConstantSDNode>(Op->getOperand(1)) && !hasNonFlagsUse(Op)) {
13774 EVT VT = Op.getValueType();
13775 unsigned BitWidth = VT.getSizeInBits();
13776 unsigned ShAmt = Op->getConstantOperandVal(1);
13777 if (ShAmt >= BitWidth) // Avoid undefined shifts.
13779 APInt Mask = ArithOp.getOpcode() == ISD::SRL
13780 ? APInt::getHighBitsSet(BitWidth, BitWidth - ShAmt)
13781 : APInt::getLowBitsSet(BitWidth, BitWidth - ShAmt);
13782 if (!Mask.isSignedIntN(32)) // Avoid large immediates.
13784 SDValue New = DAG.getNode(ISD::AND, dl, VT, Op->getOperand(0),
13785 DAG.getConstant(Mask, dl, VT));
13786 DAG.ReplaceAllUsesWith(Op, New);
13792 // If the primary and result isn't used, don't bother using X86ISD::AND,
13793 // because a TEST instruction will be better.
13794 if (!hasNonFlagsUse(Op))
13800 // Due to the ISEL shortcoming noted above, be conservative if this op is
13801 // likely to be selected as part of a load-modify-store instruction.
13802 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
13803 UE = Op.getNode()->use_end(); UI != UE; ++UI)
13804 if (UI->getOpcode() == ISD::STORE)
13807 // Otherwise use a regular EFLAGS-setting instruction.
13808 switch (ArithOp.getOpcode()) {
13809 default: llvm_unreachable("unexpected operator!");
13810 case ISD::SUB: Opcode = X86ISD::SUB; break;
13811 case ISD::XOR: Opcode = X86ISD::XOR; break;
13812 case ISD::AND: Opcode = X86ISD::AND; break;
13814 if (!NeedTruncation && (X86CC == X86::COND_E || X86CC == X86::COND_NE)) {
13815 SDValue EFLAGS = LowerVectorAllZeroTest(Op, Subtarget, DAG);
13816 if (EFLAGS.getNode())
13819 Opcode = X86ISD::OR;
13833 return SDValue(Op.getNode(), 1);
13839 // If we found that truncation is beneficial, perform the truncation and
13841 if (NeedTruncation) {
13842 EVT VT = Op.getValueType();
13843 SDValue WideVal = Op->getOperand(0);
13844 EVT WideVT = WideVal.getValueType();
13845 unsigned ConvertedOp = 0;
13846 // Use a target machine opcode to prevent further DAGCombine
13847 // optimizations that may separate the arithmetic operations
13848 // from the setcc node.
13849 switch (WideVal.getOpcode()) {
13851 case ISD::ADD: ConvertedOp = X86ISD::ADD; break;
13852 case ISD::SUB: ConvertedOp = X86ISD::SUB; break;
13853 case ISD::AND: ConvertedOp = X86ISD::AND; break;
13854 case ISD::OR: ConvertedOp = X86ISD::OR; break;
13855 case ISD::XOR: ConvertedOp = X86ISD::XOR; break;
13859 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
13860 if (TLI.isOperationLegal(WideVal.getOpcode(), WideVT)) {
13861 SDValue V0 = DAG.getNode(ISD::TRUNCATE, dl, VT, WideVal.getOperand(0));
13862 SDValue V1 = DAG.getNode(ISD::TRUNCATE, dl, VT, WideVal.getOperand(1));
13863 Op = DAG.getNode(ConvertedOp, dl, VT, V0, V1);
13869 // Emit a CMP with 0, which is the TEST pattern.
13870 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
13871 DAG.getConstant(0, dl, Op.getValueType()));
13873 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
13874 SmallVector<SDValue, 4> Ops(Op->op_begin(), Op->op_begin() + NumOperands);
13876 SDValue New = DAG.getNode(Opcode, dl, VTs, Ops);
13877 DAG.ReplaceAllUsesWith(Op, New);
13878 return SDValue(New.getNode(), 1);
13881 /// Emit nodes that will be selected as "cmp Op0,Op1", or something
13883 SDValue X86TargetLowering::EmitCmp(SDValue Op0, SDValue Op1, unsigned X86CC,
13884 SDLoc dl, SelectionDAG &DAG) const {
13885 if (isNullConstant(Op1))
13886 return EmitTest(Op0, X86CC, dl, DAG);
13888 assert(!(isa<ConstantSDNode>(Op1) && Op0.getValueType() == MVT::i1) &&
13889 "Unexpected comparison operation for MVT::i1 operands");
13891 if ((Op0.getValueType() == MVT::i8 || Op0.getValueType() == MVT::i16 ||
13892 Op0.getValueType() == MVT::i32 || Op0.getValueType() == MVT::i64)) {
13893 // Do the comparison at i32 if it's smaller, besides the Atom case.
13894 // This avoids subregister aliasing issues. Keep the smaller reference
13895 // if we're optimizing for size, however, as that'll allow better folding
13896 // of memory operations.
13897 if (Op0.getValueType() != MVT::i32 && Op0.getValueType() != MVT::i64 &&
13898 !DAG.getMachineFunction().getFunction()->optForMinSize() &&
13899 !Subtarget->isAtom()) {
13900 unsigned ExtendOp =
13901 isX86CCUnsigned(X86CC) ? ISD::ZERO_EXTEND : ISD::SIGN_EXTEND;
13902 Op0 = DAG.getNode(ExtendOp, dl, MVT::i32, Op0);
13903 Op1 = DAG.getNode(ExtendOp, dl, MVT::i32, Op1);
13905 // Use SUB instead of CMP to enable CSE between SUB and CMP.
13906 SDVTList VTs = DAG.getVTList(Op0.getValueType(), MVT::i32);
13907 SDValue Sub = DAG.getNode(X86ISD::SUB, dl, VTs,
13909 return SDValue(Sub.getNode(), 1);
13911 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op0, Op1);
13914 /// Convert a comparison if required by the subtarget.
13915 SDValue X86TargetLowering::ConvertCmpIfNecessary(SDValue Cmp,
13916 SelectionDAG &DAG) const {
13917 // If the subtarget does not support the FUCOMI instruction, floating-point
13918 // comparisons have to be converted.
13919 if (Subtarget->hasCMov() ||
13920 Cmp.getOpcode() != X86ISD::CMP ||
13921 !Cmp.getOperand(0).getValueType().isFloatingPoint() ||
13922 !Cmp.getOperand(1).getValueType().isFloatingPoint())
13925 // The instruction selector will select an FUCOM instruction instead of
13926 // FUCOMI, which writes the comparison result to FPSW instead of EFLAGS. Hence
13927 // build an SDNode sequence that transfers the result from FPSW into EFLAGS:
13928 // (X86sahf (trunc (srl (X86fp_stsw (trunc (X86cmp ...)), 8))))
13930 SDValue TruncFPSW = DAG.getNode(ISD::TRUNCATE, dl, MVT::i16, Cmp);
13931 SDValue FNStSW = DAG.getNode(X86ISD::FNSTSW16r, dl, MVT::i16, TruncFPSW);
13932 SDValue Srl = DAG.getNode(ISD::SRL, dl, MVT::i16, FNStSW,
13933 DAG.getConstant(8, dl, MVT::i8));
13934 SDValue TruncSrl = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Srl);
13935 return DAG.getNode(X86ISD::SAHF, dl, MVT::i32, TruncSrl);
13938 /// The minimum architected relative accuracy is 2^-12. We need one
13939 /// Newton-Raphson step to have a good float result (24 bits of precision).
13940 SDValue X86TargetLowering::getRsqrtEstimate(SDValue Op,
13941 DAGCombinerInfo &DCI,
13942 unsigned &RefinementSteps,
13943 bool &UseOneConstNR) const {
13944 EVT VT = Op.getValueType();
13945 const char *RecipOp;
13947 // SSE1 has rsqrtss and rsqrtps. AVX adds a 256-bit variant for rsqrtps.
13948 // TODO: Add support for AVX512 (v16f32).
13949 // It is likely not profitable to do this for f64 because a double-precision
13950 // rsqrt estimate with refinement on x86 prior to FMA requires at least 16
13951 // instructions: convert to single, rsqrtss, convert back to double, refine
13952 // (3 steps = at least 13 insts). If an 'rsqrtsd' variant was added to the ISA
13953 // along with FMA, this could be a throughput win.
13954 if (VT == MVT::f32 && Subtarget->hasSSE1())
13956 else if ((VT == MVT::v4f32 && Subtarget->hasSSE1()) ||
13957 (VT == MVT::v8f32 && Subtarget->hasAVX()))
13958 RecipOp = "vec-sqrtf";
13962 TargetRecip Recips = DCI.DAG.getTarget().Options.Reciprocals;
13963 if (!Recips.isEnabled(RecipOp))
13966 RefinementSteps = Recips.getRefinementSteps(RecipOp);
13967 UseOneConstNR = false;
13968 return DCI.DAG.getNode(X86ISD::FRSQRT, SDLoc(Op), VT, Op);
13971 /// The minimum architected relative accuracy is 2^-12. We need one
13972 /// Newton-Raphson step to have a good float result (24 bits of precision).
13973 SDValue X86TargetLowering::getRecipEstimate(SDValue Op,
13974 DAGCombinerInfo &DCI,
13975 unsigned &RefinementSteps) const {
13976 EVT VT = Op.getValueType();
13977 const char *RecipOp;
13979 // SSE1 has rcpss and rcpps. AVX adds a 256-bit variant for rcpps.
13980 // TODO: Add support for AVX512 (v16f32).
13981 // It is likely not profitable to do this for f64 because a double-precision
13982 // reciprocal estimate with refinement on x86 prior to FMA requires
13983 // 15 instructions: convert to single, rcpss, convert back to double, refine
13984 // (3 steps = 12 insts). If an 'rcpsd' variant was added to the ISA
13985 // along with FMA, this could be a throughput win.
13986 if (VT == MVT::f32 && Subtarget->hasSSE1())
13988 else if ((VT == MVT::v4f32 && Subtarget->hasSSE1()) ||
13989 (VT == MVT::v8f32 && Subtarget->hasAVX()))
13990 RecipOp = "vec-divf";
13994 TargetRecip Recips = DCI.DAG.getTarget().Options.Reciprocals;
13995 if (!Recips.isEnabled(RecipOp))
13998 RefinementSteps = Recips.getRefinementSteps(RecipOp);
13999 return DCI.DAG.getNode(X86ISD::FRCP, SDLoc(Op), VT, Op);
14002 /// If we have at least two divisions that use the same divisor, convert to
14003 /// multplication by a reciprocal. This may need to be adjusted for a given
14004 /// CPU if a division's cost is not at least twice the cost of a multiplication.
14005 /// This is because we still need one division to calculate the reciprocal and
14006 /// then we need two multiplies by that reciprocal as replacements for the
14007 /// original divisions.
14008 unsigned X86TargetLowering::combineRepeatedFPDivisors() const {
14012 /// LowerToBT - Result of 'and' is compared against zero. Turn it into a BT node
14013 /// if it's possible.
14014 SDValue X86TargetLowering::LowerToBT(SDValue And, ISD::CondCode CC,
14015 SDLoc dl, SelectionDAG &DAG) const {
14016 SDValue Op0 = And.getOperand(0);
14017 SDValue Op1 = And.getOperand(1);
14018 if (Op0.getOpcode() == ISD::TRUNCATE)
14019 Op0 = Op0.getOperand(0);
14020 if (Op1.getOpcode() == ISD::TRUNCATE)
14021 Op1 = Op1.getOperand(0);
14024 if (Op1.getOpcode() == ISD::SHL)
14025 std::swap(Op0, Op1);
14026 if (Op0.getOpcode() == ISD::SHL) {
14027 if (isOneConstant(Op0.getOperand(0))) {
14028 // If we looked past a truncate, check that it's only truncating away
14030 unsigned BitWidth = Op0.getValueSizeInBits();
14031 unsigned AndBitWidth = And.getValueSizeInBits();
14032 if (BitWidth > AndBitWidth) {
14034 DAG.computeKnownBits(Op0, Zeros, Ones);
14035 if (Zeros.countLeadingOnes() < BitWidth - AndBitWidth)
14039 RHS = Op0.getOperand(1);
14041 } else if (Op1.getOpcode() == ISD::Constant) {
14042 ConstantSDNode *AndRHS = cast<ConstantSDNode>(Op1);
14043 uint64_t AndRHSVal = AndRHS->getZExtValue();
14044 SDValue AndLHS = Op0;
14046 if (AndRHSVal == 1 && AndLHS.getOpcode() == ISD::SRL) {
14047 LHS = AndLHS.getOperand(0);
14048 RHS = AndLHS.getOperand(1);
14051 // Use BT if the immediate can't be encoded in a TEST instruction.
14052 if (!isUInt<32>(AndRHSVal) && isPowerOf2_64(AndRHSVal)) {
14054 RHS = DAG.getConstant(Log2_64_Ceil(AndRHSVal), dl, LHS.getValueType());
14058 if (LHS.getNode()) {
14059 // If LHS is i8, promote it to i32 with any_extend. There is no i8 BT
14060 // instruction. Since the shift amount is in-range-or-undefined, we know
14061 // that doing a bittest on the i32 value is ok. We extend to i32 because
14062 // the encoding for the i16 version is larger than the i32 version.
14063 // Also promote i16 to i32 for performance / code size reason.
14064 if (LHS.getValueType() == MVT::i8 ||
14065 LHS.getValueType() == MVT::i16)
14066 LHS = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, LHS);
14068 // If the operand types disagree, extend the shift amount to match. Since
14069 // BT ignores high bits (like shifts) we can use anyextend.
14070 if (LHS.getValueType() != RHS.getValueType())
14071 RHS = DAG.getNode(ISD::ANY_EXTEND, dl, LHS.getValueType(), RHS);
14073 SDValue BT = DAG.getNode(X86ISD::BT, dl, MVT::i32, LHS, RHS);
14074 X86::CondCode Cond = CC == ISD::SETEQ ? X86::COND_AE : X86::COND_B;
14075 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
14076 DAG.getConstant(Cond, dl, MVT::i8), BT);
14082 /// \brief - Turns an ISD::CondCode into a value suitable for SSE floating point
14084 static int translateX86FSETCC(ISD::CondCode SetCCOpcode, SDValue &Op0,
14089 // SSE Condition code mapping:
14098 switch (SetCCOpcode) {
14099 default: llvm_unreachable("Unexpected SETCC condition");
14101 case ISD::SETEQ: SSECC = 0; break;
14103 case ISD::SETGT: Swap = true; // Fallthrough
14105 case ISD::SETOLT: SSECC = 1; break;
14107 case ISD::SETGE: Swap = true; // Fallthrough
14109 case ISD::SETOLE: SSECC = 2; break;
14110 case ISD::SETUO: SSECC = 3; break;
14112 case ISD::SETNE: SSECC = 4; break;
14113 case ISD::SETULE: Swap = true; // Fallthrough
14114 case ISD::SETUGE: SSECC = 5; break;
14115 case ISD::SETULT: Swap = true; // Fallthrough
14116 case ISD::SETUGT: SSECC = 6; break;
14117 case ISD::SETO: SSECC = 7; break;
14119 case ISD::SETONE: SSECC = 8; break;
14122 std::swap(Op0, Op1);
14127 // Lower256IntVSETCC - Break a VSETCC 256-bit integer VSETCC into two new 128
14128 // ones, and then concatenate the result back.
14129 static SDValue Lower256IntVSETCC(SDValue Op, SelectionDAG &DAG) {
14130 MVT VT = Op.getSimpleValueType();
14132 assert(VT.is256BitVector() && Op.getOpcode() == ISD::SETCC &&
14133 "Unsupported value type for operation");
14135 unsigned NumElems = VT.getVectorNumElements();
14137 SDValue CC = Op.getOperand(2);
14139 // Extract the LHS vectors
14140 SDValue LHS = Op.getOperand(0);
14141 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
14142 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
14144 // Extract the RHS vectors
14145 SDValue RHS = Op.getOperand(1);
14146 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, dl);
14147 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, dl);
14149 // Issue the operation on the smaller types and concatenate the result back
14150 MVT EltVT = VT.getVectorElementType();
14151 MVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
14152 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
14153 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1, CC),
14154 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2, CC));
14157 static SDValue LowerBoolVSETCC_AVX512(SDValue Op, SelectionDAG &DAG) {
14158 SDValue Op0 = Op.getOperand(0);
14159 SDValue Op1 = Op.getOperand(1);
14160 SDValue CC = Op.getOperand(2);
14161 MVT VT = Op.getSimpleValueType();
14164 assert(Op0.getSimpleValueType().getVectorElementType() == MVT::i1 &&
14165 "Unexpected type for boolean compare operation");
14166 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
14167 SDValue NotOp0 = DAG.getNode(ISD::XOR, dl, VT, Op0,
14168 DAG.getConstant(-1, dl, VT));
14169 SDValue NotOp1 = DAG.getNode(ISD::XOR, dl, VT, Op1,
14170 DAG.getConstant(-1, dl, VT));
14171 switch (SetCCOpcode) {
14172 default: llvm_unreachable("Unexpected SETCC condition");
14174 // (x == y) -> ~(x ^ y)
14175 return DAG.getNode(ISD::XOR, dl, VT,
14176 DAG.getNode(ISD::XOR, dl, VT, Op0, Op1),
14177 DAG.getConstant(-1, dl, VT));
14179 // (x != y) -> (x ^ y)
14180 return DAG.getNode(ISD::XOR, dl, VT, Op0, Op1);
14183 // (x > y) -> (x & ~y)
14184 return DAG.getNode(ISD::AND, dl, VT, Op0, NotOp1);
14187 // (x < y) -> (~x & y)
14188 return DAG.getNode(ISD::AND, dl, VT, NotOp0, Op1);
14191 // (x <= y) -> (~x | y)
14192 return DAG.getNode(ISD::OR, dl, VT, NotOp0, Op1);
14195 // (x >=y) -> (x | ~y)
14196 return DAG.getNode(ISD::OR, dl, VT, Op0, NotOp1);
14200 static SDValue LowerIntVSETCC_AVX512(SDValue Op, SelectionDAG &DAG,
14201 const X86Subtarget *Subtarget) {
14202 SDValue Op0 = Op.getOperand(0);
14203 SDValue Op1 = Op.getOperand(1);
14204 SDValue CC = Op.getOperand(2);
14205 MVT VT = Op.getSimpleValueType();
14208 assert(Op0.getSimpleValueType().getVectorElementType().getSizeInBits() >= 8 &&
14209 Op.getSimpleValueType().getVectorElementType() == MVT::i1 &&
14210 "Cannot set masked compare for this operation");
14212 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
14214 bool Unsigned = false;
14217 switch (SetCCOpcode) {
14218 default: llvm_unreachable("Unexpected SETCC condition");
14219 case ISD::SETNE: SSECC = 4; break;
14220 case ISD::SETEQ: Opc = X86ISD::PCMPEQM; break;
14221 case ISD::SETUGT: SSECC = 6; Unsigned = true; break;
14222 case ISD::SETLT: Swap = true; //fall-through
14223 case ISD::SETGT: Opc = X86ISD::PCMPGTM; break;
14224 case ISD::SETULT: SSECC = 1; Unsigned = true; break;
14225 case ISD::SETUGE: SSECC = 5; Unsigned = true; break; //NLT
14226 case ISD::SETGE: Swap = true; SSECC = 2; break; // LE + swap
14227 case ISD::SETULE: Unsigned = true; //fall-through
14228 case ISD::SETLE: SSECC = 2; break;
14232 std::swap(Op0, Op1);
14234 return DAG.getNode(Opc, dl, VT, Op0, Op1);
14235 Opc = Unsigned ? X86ISD::CMPMU: X86ISD::CMPM;
14236 return DAG.getNode(Opc, dl, VT, Op0, Op1,
14237 DAG.getConstant(SSECC, dl, MVT::i8));
14240 /// \brief Try to turn a VSETULT into a VSETULE by modifying its second
14241 /// operand \p Op1. If non-trivial (for example because it's not constant)
14242 /// return an empty value.
14243 static SDValue ChangeVSETULTtoVSETULE(SDLoc dl, SDValue Op1, SelectionDAG &DAG)
14245 BuildVectorSDNode *BV = dyn_cast<BuildVectorSDNode>(Op1.getNode());
14249 MVT VT = Op1.getSimpleValueType();
14250 MVT EVT = VT.getVectorElementType();
14251 unsigned n = VT.getVectorNumElements();
14252 SmallVector<SDValue, 8> ULTOp1;
14254 for (unsigned i = 0; i < n; ++i) {
14255 ConstantSDNode *Elt = dyn_cast<ConstantSDNode>(BV->getOperand(i));
14256 if (!Elt || Elt->isOpaque() || Elt->getSimpleValueType(0) != EVT)
14259 // Avoid underflow.
14260 APInt Val = Elt->getAPIntValue();
14264 ULTOp1.push_back(DAG.getConstant(Val - 1, dl, EVT));
14267 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, ULTOp1);
14270 static SDValue LowerVSETCC(SDValue Op, const X86Subtarget *Subtarget,
14271 SelectionDAG &DAG) {
14272 SDValue Op0 = Op.getOperand(0);
14273 SDValue Op1 = Op.getOperand(1);
14274 SDValue CC = Op.getOperand(2);
14275 MVT VT = Op.getSimpleValueType();
14276 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
14277 bool isFP = Op.getOperand(1).getSimpleValueType().isFloatingPoint();
14282 MVT EltVT = Op0.getSimpleValueType().getVectorElementType();
14283 assert(EltVT == MVT::f32 || EltVT == MVT::f64);
14286 unsigned SSECC = translateX86FSETCC(SetCCOpcode, Op0, Op1);
14287 unsigned Opc = X86ISD::CMPP;
14288 if (Subtarget->hasAVX512() && VT.getVectorElementType() == MVT::i1) {
14289 assert(VT.getVectorNumElements() <= 16);
14290 Opc = X86ISD::CMPM;
14292 // In the two special cases we can't handle, emit two comparisons.
14295 unsigned CombineOpc;
14296 if (SetCCOpcode == ISD::SETUEQ) {
14297 CC0 = 3; CC1 = 0; CombineOpc = ISD::OR;
14299 assert(SetCCOpcode == ISD::SETONE);
14300 CC0 = 7; CC1 = 4; CombineOpc = ISD::AND;
14303 SDValue Cmp0 = DAG.getNode(Opc, dl, VT, Op0, Op1,
14304 DAG.getConstant(CC0, dl, MVT::i8));
14305 SDValue Cmp1 = DAG.getNode(Opc, dl, VT, Op0, Op1,
14306 DAG.getConstant(CC1, dl, MVT::i8));
14307 return DAG.getNode(CombineOpc, dl, VT, Cmp0, Cmp1);
14309 // Handle all other FP comparisons here.
14310 return DAG.getNode(Opc, dl, VT, Op0, Op1,
14311 DAG.getConstant(SSECC, dl, MVT::i8));
14314 MVT VTOp0 = Op0.getSimpleValueType();
14315 assert(VTOp0 == Op1.getSimpleValueType() &&
14316 "Expected operands with same type!");
14317 assert(VT.getVectorNumElements() == VTOp0.getVectorNumElements() &&
14318 "Invalid number of packed elements for source and destination!");
14320 if (VT.is128BitVector() && VTOp0.is256BitVector()) {
14321 // On non-AVX512 targets, a vector of MVT::i1 is promoted by the type
14322 // legalizer to a wider vector type. In the case of 'vsetcc' nodes, the
14323 // legalizer firstly checks if the first operand in input to the setcc has
14324 // a legal type. If so, then it promotes the return type to that same type.
14325 // Otherwise, the return type is promoted to the 'next legal type' which,
14326 // for a vector of MVT::i1 is always a 128-bit integer vector type.
14328 // We reach this code only if the following two conditions are met:
14329 // 1. Both return type and operand type have been promoted to wider types
14330 // by the type legalizer.
14331 // 2. The original operand type has been promoted to a 256-bit vector.
14333 // Note that condition 2. only applies for AVX targets.
14334 SDValue NewOp = DAG.getSetCC(dl, VTOp0, Op0, Op1, SetCCOpcode);
14335 return DAG.getZExtOrTrunc(NewOp, dl, VT);
14338 // The non-AVX512 code below works under the assumption that source and
14339 // destination types are the same.
14340 assert((Subtarget->hasAVX512() || (VT == VTOp0)) &&
14341 "Value types for source and destination must be the same!");
14343 // Break 256-bit integer vector compare into smaller ones.
14344 if (VT.is256BitVector() && !Subtarget->hasInt256())
14345 return Lower256IntVSETCC(Op, DAG);
14347 MVT OpVT = Op1.getSimpleValueType();
14348 if (OpVT.getVectorElementType() == MVT::i1)
14349 return LowerBoolVSETCC_AVX512(Op, DAG);
14351 bool MaskResult = (VT.getVectorElementType() == MVT::i1);
14352 if (Subtarget->hasAVX512()) {
14353 if (Op1.getSimpleValueType().is512BitVector() ||
14354 (Subtarget->hasBWI() && Subtarget->hasVLX()) ||
14355 (MaskResult && OpVT.getVectorElementType().getSizeInBits() >= 32))
14356 return LowerIntVSETCC_AVX512(Op, DAG, Subtarget);
14358 // In AVX-512 architecture setcc returns mask with i1 elements,
14359 // But there is no compare instruction for i8 and i16 elements in KNL.
14360 // We are not talking about 512-bit operands in this case, these
14361 // types are illegal.
14363 (OpVT.getVectorElementType().getSizeInBits() < 32 &&
14364 OpVT.getVectorElementType().getSizeInBits() >= 8))
14365 return DAG.getNode(ISD::TRUNCATE, dl, VT,
14366 DAG.getNode(ISD::SETCC, dl, OpVT, Op0, Op1, CC));
14369 // Lower using XOP integer comparisons.
14370 if ((VT == MVT::v16i8 || VT == MVT::v8i16 ||
14371 VT == MVT::v4i32 || VT == MVT::v2i64) && Subtarget->hasXOP()) {
14372 // Translate compare code to XOP PCOM compare mode.
14373 unsigned CmpMode = 0;
14374 switch (SetCCOpcode) {
14375 default: llvm_unreachable("Unexpected SETCC condition");
14377 case ISD::SETLT: CmpMode = 0x00; break;
14379 case ISD::SETLE: CmpMode = 0x01; break;
14381 case ISD::SETGT: CmpMode = 0x02; break;
14383 case ISD::SETGE: CmpMode = 0x03; break;
14384 case ISD::SETEQ: CmpMode = 0x04; break;
14385 case ISD::SETNE: CmpMode = 0x05; break;
14388 // Are we comparing unsigned or signed integers?
14389 unsigned Opc = ISD::isUnsignedIntSetCC(SetCCOpcode)
14390 ? X86ISD::VPCOMU : X86ISD::VPCOM;
14392 return DAG.getNode(Opc, dl, VT, Op0, Op1,
14393 DAG.getConstant(CmpMode, dl, MVT::i8));
14396 // We are handling one of the integer comparisons here. Since SSE only has
14397 // GT and EQ comparisons for integer, swapping operands and multiple
14398 // operations may be required for some comparisons.
14400 bool Swap = false, Invert = false, FlipSigns = false, MinMax = false;
14401 bool Subus = false;
14403 switch (SetCCOpcode) {
14404 default: llvm_unreachable("Unexpected SETCC condition");
14405 case ISD::SETNE: Invert = true;
14406 case ISD::SETEQ: Opc = X86ISD::PCMPEQ; break;
14407 case ISD::SETLT: Swap = true;
14408 case ISD::SETGT: Opc = X86ISD::PCMPGT; break;
14409 case ISD::SETGE: Swap = true;
14410 case ISD::SETLE: Opc = X86ISD::PCMPGT;
14411 Invert = true; break;
14412 case ISD::SETULT: Swap = true;
14413 case ISD::SETUGT: Opc = X86ISD::PCMPGT;
14414 FlipSigns = true; break;
14415 case ISD::SETUGE: Swap = true;
14416 case ISD::SETULE: Opc = X86ISD::PCMPGT;
14417 FlipSigns = true; Invert = true; break;
14420 // Special case: Use min/max operations for SETULE/SETUGE
14421 MVT VET = VT.getVectorElementType();
14423 (Subtarget->hasSSE41() && (VET >= MVT::i8 && VET <= MVT::i32))
14424 || (Subtarget->hasSSE2() && (VET == MVT::i8));
14427 switch (SetCCOpcode) {
14429 case ISD::SETULE: Opc = ISD::UMIN; MinMax = true; break;
14430 case ISD::SETUGE: Opc = ISD::UMAX; MinMax = true; break;
14433 if (MinMax) { Swap = false; Invert = false; FlipSigns = false; }
14436 bool hasSubus = Subtarget->hasSSE2() && (VET == MVT::i8 || VET == MVT::i16);
14437 if (!MinMax && hasSubus) {
14438 // As another special case, use PSUBUS[BW] when it's profitable. E.g. for
14440 // t = psubus Op0, Op1
14441 // pcmpeq t, <0..0>
14442 switch (SetCCOpcode) {
14444 case ISD::SETULT: {
14445 // If the comparison is against a constant we can turn this into a
14446 // setule. With psubus, setule does not require a swap. This is
14447 // beneficial because the constant in the register is no longer
14448 // destructed as the destination so it can be hoisted out of a loop.
14449 // Only do this pre-AVX since vpcmp* is no longer destructive.
14450 if (Subtarget->hasAVX())
14452 SDValue ULEOp1 = ChangeVSETULTtoVSETULE(dl, Op1, DAG);
14453 if (ULEOp1.getNode()) {
14455 Subus = true; Invert = false; Swap = false;
14459 // Psubus is better than flip-sign because it requires no inversion.
14460 case ISD::SETUGE: Subus = true; Invert = false; Swap = true; break;
14461 case ISD::SETULE: Subus = true; Invert = false; Swap = false; break;
14465 Opc = X86ISD::SUBUS;
14471 std::swap(Op0, Op1);
14473 // Check that the operation in question is available (most are plain SSE2,
14474 // but PCMPGTQ and PCMPEQQ have different requirements).
14475 if (VT == MVT::v2i64) {
14476 if (Opc == X86ISD::PCMPGT && !Subtarget->hasSSE42()) {
14477 assert(Subtarget->hasSSE2() && "Don't know how to lower!");
14479 // First cast everything to the right type.
14480 Op0 = DAG.getBitcast(MVT::v4i32, Op0);
14481 Op1 = DAG.getBitcast(MVT::v4i32, Op1);
14483 // Since SSE has no unsigned integer comparisons, we need to flip the sign
14484 // bits of the inputs before performing those operations. The lower
14485 // compare is always unsigned.
14488 SB = DAG.getConstant(0x80000000U, dl, MVT::v4i32);
14490 SDValue Sign = DAG.getConstant(0x80000000U, dl, MVT::i32);
14491 SDValue Zero = DAG.getConstant(0x00000000U, dl, MVT::i32);
14492 SB = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32,
14493 Sign, Zero, Sign, Zero);
14495 Op0 = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Op0, SB);
14496 Op1 = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Op1, SB);
14498 // Emulate PCMPGTQ with (hi1 > hi2) | ((hi1 == hi2) & (lo1 > lo2))
14499 SDValue GT = DAG.getNode(X86ISD::PCMPGT, dl, MVT::v4i32, Op0, Op1);
14500 SDValue EQ = DAG.getNode(X86ISD::PCMPEQ, dl, MVT::v4i32, Op0, Op1);
14502 // Create masks for only the low parts/high parts of the 64 bit integers.
14503 static const int MaskHi[] = { 1, 1, 3, 3 };
14504 static const int MaskLo[] = { 0, 0, 2, 2 };
14505 SDValue EQHi = DAG.getVectorShuffle(MVT::v4i32, dl, EQ, EQ, MaskHi);
14506 SDValue GTLo = DAG.getVectorShuffle(MVT::v4i32, dl, GT, GT, MaskLo);
14507 SDValue GTHi = DAG.getVectorShuffle(MVT::v4i32, dl, GT, GT, MaskHi);
14509 SDValue Result = DAG.getNode(ISD::AND, dl, MVT::v4i32, EQHi, GTLo);
14510 Result = DAG.getNode(ISD::OR, dl, MVT::v4i32, Result, GTHi);
14513 Result = DAG.getNOT(dl, Result, MVT::v4i32);
14515 return DAG.getBitcast(VT, Result);
14518 if (Opc == X86ISD::PCMPEQ && !Subtarget->hasSSE41()) {
14519 // If pcmpeqq is missing but pcmpeqd is available synthesize pcmpeqq with
14520 // pcmpeqd + pshufd + pand.
14521 assert(Subtarget->hasSSE2() && !FlipSigns && "Don't know how to lower!");
14523 // First cast everything to the right type.
14524 Op0 = DAG.getBitcast(MVT::v4i32, Op0);
14525 Op1 = DAG.getBitcast(MVT::v4i32, Op1);
14528 SDValue Result = DAG.getNode(Opc, dl, MVT::v4i32, Op0, Op1);
14530 // Make sure the lower and upper halves are both all-ones.
14531 static const int Mask[] = { 1, 0, 3, 2 };
14532 SDValue Shuf = DAG.getVectorShuffle(MVT::v4i32, dl, Result, Result, Mask);
14533 Result = DAG.getNode(ISD::AND, dl, MVT::v4i32, Result, Shuf);
14536 Result = DAG.getNOT(dl, Result, MVT::v4i32);
14538 return DAG.getBitcast(VT, Result);
14542 // Since SSE has no unsigned integer comparisons, we need to flip the sign
14543 // bits of the inputs before performing those operations.
14545 MVT EltVT = VT.getVectorElementType();
14546 SDValue SB = DAG.getConstant(APInt::getSignBit(EltVT.getSizeInBits()), dl,
14548 Op0 = DAG.getNode(ISD::XOR, dl, VT, Op0, SB);
14549 Op1 = DAG.getNode(ISD::XOR, dl, VT, Op1, SB);
14552 SDValue Result = DAG.getNode(Opc, dl, VT, Op0, Op1);
14554 // If the logical-not of the result is required, perform that now.
14556 Result = DAG.getNOT(dl, Result, VT);
14559 Result = DAG.getNode(X86ISD::PCMPEQ, dl, VT, Op0, Result);
14562 Result = DAG.getNode(X86ISD::PCMPEQ, dl, VT, Result,
14563 getZeroVector(VT, Subtarget, DAG, dl));
14568 SDValue X86TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
14570 MVT VT = Op.getSimpleValueType();
14572 if (VT.isVector()) return LowerVSETCC(Op, Subtarget, DAG);
14574 assert(((!Subtarget->hasAVX512() && VT == MVT::i8) || (VT == MVT::i1))
14575 && "SetCC type must be 8-bit or 1-bit integer");
14576 SDValue Op0 = Op.getOperand(0);
14577 SDValue Op1 = Op.getOperand(1);
14579 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
14581 // Optimize to BT if possible.
14582 // Lower (X & (1 << N)) == 0 to BT(X, N).
14583 // Lower ((X >>u N) & 1) != 0 to BT(X, N).
14584 // Lower ((X >>s N) & 1) != 0 to BT(X, N).
14585 if (Op0.getOpcode() == ISD::AND && Op0.hasOneUse() &&
14586 isNullConstant(Op1) &&
14587 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
14588 if (SDValue NewSetCC = LowerToBT(Op0, CC, dl, DAG)) {
14590 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, NewSetCC);
14595 // Look for X == 0, X == 1, X != 0, or X != 1. We can simplify some forms of
14597 if ((isOneConstant(Op1) || isNullConstant(Op1)) &&
14598 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
14600 // If the input is a setcc, then reuse the input setcc or use a new one with
14601 // the inverted condition.
14602 if (Op0.getOpcode() == X86ISD::SETCC) {
14603 X86::CondCode CCode = (X86::CondCode)Op0.getConstantOperandVal(0);
14604 bool Invert = (CC == ISD::SETNE) ^ isNullConstant(Op1);
14608 CCode = X86::GetOppositeBranchCondition(CCode);
14609 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
14610 DAG.getConstant(CCode, dl, MVT::i8),
14611 Op0.getOperand(1));
14613 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, SetCC);
14617 if ((Op0.getValueType() == MVT::i1) && isOneConstant(Op1) &&
14618 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
14620 ISD::CondCode NewCC = ISD::getSetCCInverse(CC, true);
14621 return DAG.getSetCC(dl, VT, Op0, DAG.getConstant(0, dl, MVT::i1), NewCC);
14624 bool isFP = Op1.getSimpleValueType().isFloatingPoint();
14625 unsigned X86CC = TranslateX86CC(CC, dl, isFP, Op0, Op1, DAG);
14626 if (X86CC == X86::COND_INVALID)
14629 SDValue EFLAGS = EmitCmp(Op0, Op1, X86CC, dl, DAG);
14630 EFLAGS = ConvertCmpIfNecessary(EFLAGS, DAG);
14631 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
14632 DAG.getConstant(X86CC, dl, MVT::i8), EFLAGS);
14634 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, SetCC);
14638 SDValue X86TargetLowering::LowerSETCCE(SDValue Op, SelectionDAG &DAG) const {
14639 SDValue LHS = Op.getOperand(0);
14640 SDValue RHS = Op.getOperand(1);
14641 SDValue Carry = Op.getOperand(2);
14642 SDValue Cond = Op.getOperand(3);
14645 assert(LHS.getSimpleValueType().isInteger() && "SETCCE is integer only.");
14646 X86::CondCode CC = TranslateIntegerX86CC(cast<CondCodeSDNode>(Cond)->get());
14648 assert(Carry.getOpcode() != ISD::CARRY_FALSE);
14649 SDVTList VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
14650 SDValue Cmp = DAG.getNode(X86ISD::SBB, DL, VTs, LHS, RHS, Carry);
14651 return DAG.getNode(X86ISD::SETCC, DL, Op.getValueType(),
14652 DAG.getConstant(CC, DL, MVT::i8), Cmp.getValue(1));
14655 // isX86LogicalCmp - Return true if opcode is a X86 logical comparison.
14656 static bool isX86LogicalCmp(SDValue Op) {
14657 unsigned Opc = Op.getNode()->getOpcode();
14658 if (Opc == X86ISD::CMP || Opc == X86ISD::COMI || Opc == X86ISD::UCOMI ||
14659 Opc == X86ISD::SAHF)
14661 if (Op.getResNo() == 1 &&
14662 (Opc == X86ISD::ADD ||
14663 Opc == X86ISD::SUB ||
14664 Opc == X86ISD::ADC ||
14665 Opc == X86ISD::SBB ||
14666 Opc == X86ISD::SMUL ||
14667 Opc == X86ISD::UMUL ||
14668 Opc == X86ISD::INC ||
14669 Opc == X86ISD::DEC ||
14670 Opc == X86ISD::OR ||
14671 Opc == X86ISD::XOR ||
14672 Opc == X86ISD::AND))
14675 if (Op.getResNo() == 2 && Opc == X86ISD::UMUL)
14681 static bool isTruncWithZeroHighBitsInput(SDValue V, SelectionDAG &DAG) {
14682 if (V.getOpcode() != ISD::TRUNCATE)
14685 SDValue VOp0 = V.getOperand(0);
14686 unsigned InBits = VOp0.getValueSizeInBits();
14687 unsigned Bits = V.getValueSizeInBits();
14688 return DAG.MaskedValueIsZero(VOp0, APInt::getHighBitsSet(InBits,InBits-Bits));
14691 SDValue X86TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {
14692 bool addTest = true;
14693 SDValue Cond = Op.getOperand(0);
14694 SDValue Op1 = Op.getOperand(1);
14695 SDValue Op2 = Op.getOperand(2);
14697 MVT VT = Op1.getSimpleValueType();
14700 // Lower FP selects into a CMP/AND/ANDN/OR sequence when the necessary SSE ops
14701 // are available or VBLENDV if AVX is available.
14702 // Otherwise FP cmovs get lowered into a less efficient branch sequence later.
14703 if (Cond.getOpcode() == ISD::SETCC &&
14704 ((Subtarget->hasSSE2() && (VT == MVT::f32 || VT == MVT::f64)) ||
14705 (Subtarget->hasSSE1() && VT == MVT::f32)) &&
14706 VT == Cond.getOperand(0).getSimpleValueType() && Cond->hasOneUse()) {
14707 SDValue CondOp0 = Cond.getOperand(0), CondOp1 = Cond.getOperand(1);
14708 int SSECC = translateX86FSETCC(
14709 cast<CondCodeSDNode>(Cond.getOperand(2))->get(), CondOp0, CondOp1);
14712 if (Subtarget->hasAVX512()) {
14713 SDValue Cmp = DAG.getNode(X86ISD::FSETCC, DL, MVT::i1, CondOp0, CondOp1,
14714 DAG.getConstant(SSECC, DL, MVT::i8));
14715 return DAG.getNode(X86ISD::SELECT, DL, VT, Cmp, Op1, Op2);
14718 SDValue Cmp = DAG.getNode(X86ISD::FSETCC, DL, VT, CondOp0, CondOp1,
14719 DAG.getConstant(SSECC, DL, MVT::i8));
14721 // If we have AVX, we can use a variable vector select (VBLENDV) instead
14722 // of 3 logic instructions for size savings and potentially speed.
14723 // Unfortunately, there is no scalar form of VBLENDV.
14725 // If either operand is a constant, don't try this. We can expect to
14726 // optimize away at least one of the logic instructions later in that
14727 // case, so that sequence would be faster than a variable blend.
14729 // BLENDV was introduced with SSE 4.1, but the 2 register form implicitly
14730 // uses XMM0 as the selection register. That may need just as many
14731 // instructions as the AND/ANDN/OR sequence due to register moves, so
14734 if (Subtarget->hasAVX() &&
14735 !isa<ConstantFPSDNode>(Op1) && !isa<ConstantFPSDNode>(Op2)) {
14737 // Convert to vectors, do a VSELECT, and convert back to scalar.
14738 // All of the conversions should be optimized away.
14740 MVT VecVT = VT == MVT::f32 ? MVT::v4f32 : MVT::v2f64;
14741 SDValue VOp1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, VecVT, Op1);
14742 SDValue VOp2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, VecVT, Op2);
14743 SDValue VCmp = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, VecVT, Cmp);
14745 MVT VCmpVT = VT == MVT::f32 ? MVT::v4i32 : MVT::v2i64;
14746 VCmp = DAG.getBitcast(VCmpVT, VCmp);
14748 SDValue VSel = DAG.getNode(ISD::VSELECT, DL, VecVT, VCmp, VOp1, VOp2);
14750 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, VT,
14751 VSel, DAG.getIntPtrConstant(0, DL));
14753 SDValue AndN = DAG.getNode(X86ISD::FANDN, DL, VT, Cmp, Op2);
14754 SDValue And = DAG.getNode(X86ISD::FAND, DL, VT, Cmp, Op1);
14755 return DAG.getNode(X86ISD::FOR, DL, VT, AndN, And);
14759 if (VT.isVector() && VT.getVectorElementType() == MVT::i1) {
14761 if (ISD::isBuildVectorOfConstantSDNodes(Op1.getNode()))
14762 Op1Scalar = ConvertI1VectorToInteger(Op1, DAG);
14763 else if (Op1.getOpcode() == ISD::BITCAST && Op1.getOperand(0))
14764 Op1Scalar = Op1.getOperand(0);
14766 if (ISD::isBuildVectorOfConstantSDNodes(Op2.getNode()))
14767 Op2Scalar = ConvertI1VectorToInteger(Op2, DAG);
14768 else if (Op2.getOpcode() == ISD::BITCAST && Op2.getOperand(0))
14769 Op2Scalar = Op2.getOperand(0);
14770 if (Op1Scalar.getNode() && Op2Scalar.getNode()) {
14771 SDValue newSelect = DAG.getNode(ISD::SELECT, DL,
14772 Op1Scalar.getValueType(),
14773 Cond, Op1Scalar, Op2Scalar);
14774 if (newSelect.getValueSizeInBits() == VT.getSizeInBits())
14775 return DAG.getBitcast(VT, newSelect);
14776 SDValue ExtVec = DAG.getBitcast(MVT::v8i1, newSelect);
14777 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, ExtVec,
14778 DAG.getIntPtrConstant(0, DL));
14782 if (VT == MVT::v4i1 || VT == MVT::v2i1) {
14783 SDValue zeroConst = DAG.getIntPtrConstant(0, DL);
14784 Op1 = DAG.getNode(ISD::INSERT_SUBVECTOR, DL, MVT::v8i1,
14785 DAG.getUNDEF(MVT::v8i1), Op1, zeroConst);
14786 Op2 = DAG.getNode(ISD::INSERT_SUBVECTOR, DL, MVT::v8i1,
14787 DAG.getUNDEF(MVT::v8i1), Op2, zeroConst);
14788 SDValue newSelect = DAG.getNode(ISD::SELECT, DL, MVT::v8i1,
14790 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, newSelect, zeroConst);
14793 if (Cond.getOpcode() == ISD::SETCC) {
14794 SDValue NewCond = LowerSETCC(Cond, DAG);
14795 if (NewCond.getNode())
14799 // (select (x == 0), -1, y) -> (sign_bit (x - 1)) | y
14800 // (select (x == 0), y, -1) -> ~(sign_bit (x - 1)) | y
14801 // (select (x != 0), y, -1) -> (sign_bit (x - 1)) | y
14802 // (select (x != 0), -1, y) -> ~(sign_bit (x - 1)) | y
14803 if (Cond.getOpcode() == X86ISD::SETCC &&
14804 Cond.getOperand(1).getOpcode() == X86ISD::CMP &&
14805 isNullConstant(Cond.getOperand(1).getOperand(1))) {
14806 SDValue Cmp = Cond.getOperand(1);
14808 unsigned CondCode =cast<ConstantSDNode>(Cond.getOperand(0))->getZExtValue();
14810 if ((isAllOnesConstant(Op1) || isAllOnesConstant(Op2)) &&
14811 (CondCode == X86::COND_E || CondCode == X86::COND_NE)) {
14812 SDValue Y = isAllOnesConstant(Op2) ? Op1 : Op2;
14814 SDValue CmpOp0 = Cmp.getOperand(0);
14815 // Apply further optimizations for special cases
14816 // (select (x != 0), -1, 0) -> neg & sbb
14817 // (select (x == 0), 0, -1) -> neg & sbb
14818 if (isNullConstant(Y) &&
14819 (isAllOnesConstant(Op1) == (CondCode == X86::COND_NE))) {
14820 SDVTList VTs = DAG.getVTList(CmpOp0.getValueType(), MVT::i32);
14821 SDValue Neg = DAG.getNode(X86ISD::SUB, DL, VTs,
14822 DAG.getConstant(0, DL,
14823 CmpOp0.getValueType()),
14825 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
14826 DAG.getConstant(X86::COND_B, DL, MVT::i8),
14827 SDValue(Neg.getNode(), 1));
14831 Cmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32,
14832 CmpOp0, DAG.getConstant(1, DL, CmpOp0.getValueType()));
14833 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
14835 SDValue Res = // Res = 0 or -1.
14836 DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
14837 DAG.getConstant(X86::COND_B, DL, MVT::i8), Cmp);
14839 if (isAllOnesConstant(Op1) != (CondCode == X86::COND_E))
14840 Res = DAG.getNOT(DL, Res, Res.getValueType());
14842 if (!isNullConstant(Op2))
14843 Res = DAG.getNode(ISD::OR, DL, Res.getValueType(), Res, Y);
14848 // Look past (and (setcc_carry (cmp ...)), 1).
14849 if (Cond.getOpcode() == ISD::AND &&
14850 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY &&
14851 isOneConstant(Cond.getOperand(1)))
14852 Cond = Cond.getOperand(0);
14854 // If condition flag is set by a X86ISD::CMP, then use it as the condition
14855 // setting operand in place of the X86ISD::SETCC.
14856 unsigned CondOpcode = Cond.getOpcode();
14857 if (CondOpcode == X86ISD::SETCC ||
14858 CondOpcode == X86ISD::SETCC_CARRY) {
14859 CC = Cond.getOperand(0);
14861 SDValue Cmp = Cond.getOperand(1);
14862 unsigned Opc = Cmp.getOpcode();
14863 MVT VT = Op.getSimpleValueType();
14865 bool IllegalFPCMov = false;
14866 if (VT.isFloatingPoint() && !VT.isVector() &&
14867 !isScalarFPTypeInSSEReg(VT)) // FPStack?
14868 IllegalFPCMov = !hasFPCMov(cast<ConstantSDNode>(CC)->getSExtValue());
14870 if ((isX86LogicalCmp(Cmp) && !IllegalFPCMov) ||
14871 Opc == X86ISD::BT) { // FIXME
14875 } else if (CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO ||
14876 CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO ||
14877 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) &&
14878 Cond.getOperand(0).getValueType() != MVT::i8)) {
14879 SDValue LHS = Cond.getOperand(0);
14880 SDValue RHS = Cond.getOperand(1);
14881 unsigned X86Opcode;
14884 switch (CondOpcode) {
14885 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break;
14886 case ISD::SADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break;
14887 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break;
14888 case ISD::SSUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break;
14889 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break;
14890 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break;
14891 default: llvm_unreachable("unexpected overflowing operator");
14893 if (CondOpcode == ISD::UMULO)
14894 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(),
14897 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
14899 SDValue X86Op = DAG.getNode(X86Opcode, DL, VTs, LHS, RHS);
14901 if (CondOpcode == ISD::UMULO)
14902 Cond = X86Op.getValue(2);
14904 Cond = X86Op.getValue(1);
14906 CC = DAG.getConstant(X86Cond, DL, MVT::i8);
14911 // Look past the truncate if the high bits are known zero.
14912 if (isTruncWithZeroHighBitsInput(Cond, DAG))
14913 Cond = Cond.getOperand(0);
14915 // We know the result of AND is compared against zero. Try to match
14917 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
14918 if (SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, DL, DAG)) {
14919 CC = NewSetCC.getOperand(0);
14920 Cond = NewSetCC.getOperand(1);
14927 CC = DAG.getConstant(X86::COND_NE, DL, MVT::i8);
14928 Cond = EmitTest(Cond, X86::COND_NE, DL, DAG);
14931 // a < b ? -1 : 0 -> RES = ~setcc_carry
14932 // a < b ? 0 : -1 -> RES = setcc_carry
14933 // a >= b ? -1 : 0 -> RES = setcc_carry
14934 // a >= b ? 0 : -1 -> RES = ~setcc_carry
14935 if (Cond.getOpcode() == X86ISD::SUB) {
14936 Cond = ConvertCmpIfNecessary(Cond, DAG);
14937 unsigned CondCode = cast<ConstantSDNode>(CC)->getZExtValue();
14939 if ((CondCode == X86::COND_AE || CondCode == X86::COND_B) &&
14940 (isAllOnesConstant(Op1) || isAllOnesConstant(Op2)) &&
14941 (isNullConstant(Op1) || isNullConstant(Op2))) {
14942 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
14943 DAG.getConstant(X86::COND_B, DL, MVT::i8),
14945 if (isAllOnesConstant(Op1) != (CondCode == X86::COND_B))
14946 return DAG.getNOT(DL, Res, Res.getValueType());
14951 // X86 doesn't have an i8 cmov. If both operands are the result of a truncate
14952 // widen the cmov and push the truncate through. This avoids introducing a new
14953 // branch during isel and doesn't add any extensions.
14954 if (Op.getValueType() == MVT::i8 &&
14955 Op1.getOpcode() == ISD::TRUNCATE && Op2.getOpcode() == ISD::TRUNCATE) {
14956 SDValue T1 = Op1.getOperand(0), T2 = Op2.getOperand(0);
14957 if (T1.getValueType() == T2.getValueType() &&
14958 // Blacklist CopyFromReg to avoid partial register stalls.
14959 T1.getOpcode() != ISD::CopyFromReg && T2.getOpcode()!=ISD::CopyFromReg){
14960 SDVTList VTs = DAG.getVTList(T1.getValueType(), MVT::Glue);
14961 SDValue Cmov = DAG.getNode(X86ISD::CMOV, DL, VTs, T2, T1, CC, Cond);
14962 return DAG.getNode(ISD::TRUNCATE, DL, Op.getValueType(), Cmov);
14966 // X86ISD::CMOV means set the result (which is operand 1) to the RHS if
14967 // condition is true.
14968 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue);
14969 SDValue Ops[] = { Op2, Op1, CC, Cond };
14970 return DAG.getNode(X86ISD::CMOV, DL, VTs, Ops);
14973 static SDValue LowerSIGN_EXTEND_AVX512(SDValue Op,
14974 const X86Subtarget *Subtarget,
14975 SelectionDAG &DAG) {
14976 MVT VT = Op->getSimpleValueType(0);
14977 SDValue In = Op->getOperand(0);
14978 MVT InVT = In.getSimpleValueType();
14979 MVT VTElt = VT.getVectorElementType();
14980 MVT InVTElt = InVT.getVectorElementType();
14984 if ((InVTElt == MVT::i1) &&
14985 (((Subtarget->hasBWI() && Subtarget->hasVLX() &&
14986 VT.getSizeInBits() <= 256 && VTElt.getSizeInBits() <= 16)) ||
14988 ((Subtarget->hasBWI() && VT.is512BitVector() &&
14989 VTElt.getSizeInBits() <= 16)) ||
14991 ((Subtarget->hasDQI() && Subtarget->hasVLX() &&
14992 VT.getSizeInBits() <= 256 && VTElt.getSizeInBits() >= 32)) ||
14994 ((Subtarget->hasDQI() && VT.is512BitVector() &&
14995 VTElt.getSizeInBits() >= 32))))
14996 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
14998 unsigned int NumElts = VT.getVectorNumElements();
15000 if (NumElts != 8 && NumElts != 16 && !Subtarget->hasBWI())
15003 if (VT.is512BitVector() && InVT.getVectorElementType() != MVT::i1) {
15004 if (In.getOpcode() == X86ISD::VSEXT || In.getOpcode() == X86ISD::VZEXT)
15005 return DAG.getNode(In.getOpcode(), dl, VT, In.getOperand(0));
15006 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
15009 assert (InVT.getVectorElementType() == MVT::i1 && "Unexpected vector type");
15010 MVT ExtVT = NumElts == 8 ? MVT::v8i64 : MVT::v16i32;
15012 DAG.getConstant(APInt::getAllOnesValue(ExtVT.getScalarSizeInBits()), dl,
15015 DAG.getConstant(APInt::getNullValue(ExtVT.getScalarSizeInBits()), dl, ExtVT);
15017 SDValue V = DAG.getNode(ISD::VSELECT, dl, ExtVT, In, NegOne, Zero);
15018 if (VT.is512BitVector())
15020 return DAG.getNode(X86ISD::VTRUNC, dl, VT, V);
15023 static SDValue LowerSIGN_EXTEND_VECTOR_INREG(SDValue Op,
15024 const X86Subtarget *Subtarget,
15025 SelectionDAG &DAG) {
15026 SDValue In = Op->getOperand(0);
15027 MVT VT = Op->getSimpleValueType(0);
15028 MVT InVT = In.getSimpleValueType();
15029 assert(VT.getSizeInBits() == InVT.getSizeInBits());
15031 MVT InSVT = InVT.getVectorElementType();
15032 assert(VT.getVectorElementType().getSizeInBits() > InSVT.getSizeInBits());
15034 if (VT != MVT::v2i64 && VT != MVT::v4i32 && VT != MVT::v8i16)
15036 if (InSVT != MVT::i32 && InSVT != MVT::i16 && InSVT != MVT::i8)
15041 // SSE41 targets can use the pmovsx* instructions directly.
15042 if (Subtarget->hasSSE41())
15043 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
15045 // pre-SSE41 targets unpack lower lanes and then sign-extend using SRAI.
15049 // As SRAI is only available on i16/i32 types, we expand only up to i32
15050 // and handle i64 separately.
15051 while (CurrVT != VT && CurrVT.getVectorElementType() != MVT::i32) {
15052 Curr = DAG.getNode(X86ISD::UNPCKL, dl, CurrVT, DAG.getUNDEF(CurrVT), Curr);
15053 MVT CurrSVT = MVT::getIntegerVT(CurrVT.getScalarSizeInBits() * 2);
15054 CurrVT = MVT::getVectorVT(CurrSVT, CurrVT.getVectorNumElements() / 2);
15055 Curr = DAG.getBitcast(CurrVT, Curr);
15058 SDValue SignExt = Curr;
15059 if (CurrVT != InVT) {
15060 unsigned SignExtShift =
15061 CurrVT.getVectorElementType().getSizeInBits() - InSVT.getSizeInBits();
15062 SignExt = DAG.getNode(X86ISD::VSRAI, dl, CurrVT, Curr,
15063 DAG.getConstant(SignExtShift, dl, MVT::i8));
15069 if (VT == MVT::v2i64 && CurrVT == MVT::v4i32) {
15070 SDValue Sign = DAG.getNode(X86ISD::VSRAI, dl, CurrVT, Curr,
15071 DAG.getConstant(31, dl, MVT::i8));
15072 SDValue Ext = DAG.getVectorShuffle(CurrVT, dl, SignExt, Sign, {0, 4, 1, 5});
15073 return DAG.getBitcast(VT, Ext);
15079 static SDValue LowerSIGN_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
15080 SelectionDAG &DAG) {
15081 MVT VT = Op->getSimpleValueType(0);
15082 SDValue In = Op->getOperand(0);
15083 MVT InVT = In.getSimpleValueType();
15086 if (VT.is512BitVector() || InVT.getVectorElementType() == MVT::i1)
15087 return LowerSIGN_EXTEND_AVX512(Op, Subtarget, DAG);
15089 if ((VT != MVT::v4i64 || InVT != MVT::v4i32) &&
15090 (VT != MVT::v8i32 || InVT != MVT::v8i16) &&
15091 (VT != MVT::v16i16 || InVT != MVT::v16i8))
15094 if (Subtarget->hasInt256())
15095 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
15097 // Optimize vectors in AVX mode
15098 // Sign extend v8i16 to v8i32 and
15101 // Divide input vector into two parts
15102 // for v4i32 the shuffle mask will be { 0, 1, -1, -1} {2, 3, -1, -1}
15103 // use vpmovsx instruction to extend v4i32 -> v2i64; v8i16 -> v4i32
15104 // concat the vectors to original VT
15106 unsigned NumElems = InVT.getVectorNumElements();
15107 SDValue Undef = DAG.getUNDEF(InVT);
15109 SmallVector<int,8> ShufMask1(NumElems, -1);
15110 for (unsigned i = 0; i != NumElems/2; ++i)
15113 SDValue OpLo = DAG.getVectorShuffle(InVT, dl, In, Undef, &ShufMask1[0]);
15115 SmallVector<int,8> ShufMask2(NumElems, -1);
15116 for (unsigned i = 0; i != NumElems/2; ++i)
15117 ShufMask2[i] = i + NumElems/2;
15119 SDValue OpHi = DAG.getVectorShuffle(InVT, dl, In, Undef, &ShufMask2[0]);
15121 MVT HalfVT = MVT::getVectorVT(VT.getVectorElementType(),
15122 VT.getVectorNumElements()/2);
15124 OpLo = DAG.getNode(X86ISD::VSEXT, dl, HalfVT, OpLo);
15125 OpHi = DAG.getNode(X86ISD::VSEXT, dl, HalfVT, OpHi);
15127 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi);
15130 // Lower vector extended loads using a shuffle. If SSSE3 is not available we
15131 // may emit an illegal shuffle but the expansion is still better than scalar
15132 // code. We generate X86ISD::VSEXT for SEXTLOADs if it's available, otherwise
15133 // we'll emit a shuffle and a arithmetic shift.
15134 // FIXME: Is the expansion actually better than scalar code? It doesn't seem so.
15135 // TODO: It is possible to support ZExt by zeroing the undef values during
15136 // the shuffle phase or after the shuffle.
15137 static SDValue LowerExtendedLoad(SDValue Op, const X86Subtarget *Subtarget,
15138 SelectionDAG &DAG) {
15139 MVT RegVT = Op.getSimpleValueType();
15140 assert(RegVT.isVector() && "We only custom lower vector sext loads.");
15141 assert(RegVT.isInteger() &&
15142 "We only custom lower integer vector sext loads.");
15144 // Nothing useful we can do without SSE2 shuffles.
15145 assert(Subtarget->hasSSE2() && "We only custom lower sext loads with SSE2.");
15147 LoadSDNode *Ld = cast<LoadSDNode>(Op.getNode());
15149 EVT MemVT = Ld->getMemoryVT();
15150 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
15151 unsigned RegSz = RegVT.getSizeInBits();
15153 ISD::LoadExtType Ext = Ld->getExtensionType();
15155 assert((Ext == ISD::EXTLOAD || Ext == ISD::SEXTLOAD)
15156 && "Only anyext and sext are currently implemented.");
15157 assert(MemVT != RegVT && "Cannot extend to the same type");
15158 assert(MemVT.isVector() && "Must load a vector from memory");
15160 unsigned NumElems = RegVT.getVectorNumElements();
15161 unsigned MemSz = MemVT.getSizeInBits();
15162 assert(RegSz > MemSz && "Register size must be greater than the mem size");
15164 if (Ext == ISD::SEXTLOAD && RegSz == 256 && !Subtarget->hasInt256()) {
15165 // The only way in which we have a legal 256-bit vector result but not the
15166 // integer 256-bit operations needed to directly lower a sextload is if we
15167 // have AVX1 but not AVX2. In that case, we can always emit a sextload to
15168 // a 128-bit vector and a normal sign_extend to 256-bits that should get
15169 // correctly legalized. We do this late to allow the canonical form of
15170 // sextload to persist throughout the rest of the DAG combiner -- it wants
15171 // to fold together any extensions it can, and so will fuse a sign_extend
15172 // of an sextload into a sextload targeting a wider value.
15174 if (MemSz == 128) {
15175 // Just switch this to a normal load.
15176 assert(TLI.isTypeLegal(MemVT) && "If the memory type is a 128-bit type, "
15177 "it must be a legal 128-bit vector "
15179 Load = DAG.getLoad(MemVT, dl, Ld->getChain(), Ld->getBasePtr(),
15180 Ld->getPointerInfo(), Ld->isVolatile(), Ld->isNonTemporal(),
15181 Ld->isInvariant(), Ld->getAlignment());
15183 assert(MemSz < 128 &&
15184 "Can't extend a type wider than 128 bits to a 256 bit vector!");
15185 // Do an sext load to a 128-bit vector type. We want to use the same
15186 // number of elements, but elements half as wide. This will end up being
15187 // recursively lowered by this routine, but will succeed as we definitely
15188 // have all the necessary features if we're using AVX1.
15190 EVT::getIntegerVT(*DAG.getContext(), RegVT.getScalarSizeInBits() / 2);
15191 EVT HalfVecVT = EVT::getVectorVT(*DAG.getContext(), HalfEltVT, NumElems);
15193 DAG.getExtLoad(Ext, dl, HalfVecVT, Ld->getChain(), Ld->getBasePtr(),
15194 Ld->getPointerInfo(), MemVT, Ld->isVolatile(),
15195 Ld->isNonTemporal(), Ld->isInvariant(),
15196 Ld->getAlignment());
15199 // Replace chain users with the new chain.
15200 assert(Load->getNumValues() == 2 && "Loads must carry a chain!");
15201 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), Load.getValue(1));
15203 // Finally, do a normal sign-extend to the desired register.
15204 return DAG.getSExtOrTrunc(Load, dl, RegVT);
15207 // All sizes must be a power of two.
15208 assert(isPowerOf2_32(RegSz * MemSz * NumElems) &&
15209 "Non-power-of-two elements are not custom lowered!");
15211 // Attempt to load the original value using scalar loads.
15212 // Find the largest scalar type that divides the total loaded size.
15213 MVT SclrLoadTy = MVT::i8;
15214 for (MVT Tp : MVT::integer_valuetypes()) {
15215 if (TLI.isTypeLegal(Tp) && ((MemSz % Tp.getSizeInBits()) == 0)) {
15220 // On 32bit systems, we can't save 64bit integers. Try bitcasting to F64.
15221 if (TLI.isTypeLegal(MVT::f64) && SclrLoadTy.getSizeInBits() < 64 &&
15223 SclrLoadTy = MVT::f64;
15225 // Calculate the number of scalar loads that we need to perform
15226 // in order to load our vector from memory.
15227 unsigned NumLoads = MemSz / SclrLoadTy.getSizeInBits();
15229 assert((Ext != ISD::SEXTLOAD || NumLoads == 1) &&
15230 "Can only lower sext loads with a single scalar load!");
15232 unsigned loadRegZize = RegSz;
15233 if (Ext == ISD::SEXTLOAD && RegSz >= 256)
15236 // Represent our vector as a sequence of elements which are the
15237 // largest scalar that we can load.
15238 EVT LoadUnitVecVT = EVT::getVectorVT(
15239 *DAG.getContext(), SclrLoadTy, loadRegZize / SclrLoadTy.getSizeInBits());
15241 // Represent the data using the same element type that is stored in
15242 // memory. In practice, we ''widen'' MemVT.
15244 EVT::getVectorVT(*DAG.getContext(), MemVT.getScalarType(),
15245 loadRegZize / MemVT.getScalarSizeInBits());
15247 assert(WideVecVT.getSizeInBits() == LoadUnitVecVT.getSizeInBits() &&
15248 "Invalid vector type");
15250 // We can't shuffle using an illegal type.
15251 assert(TLI.isTypeLegal(WideVecVT) &&
15252 "We only lower types that form legal widened vector types");
15254 SmallVector<SDValue, 8> Chains;
15255 SDValue Ptr = Ld->getBasePtr();
15256 SDValue Increment = DAG.getConstant(SclrLoadTy.getSizeInBits() / 8, dl,
15257 TLI.getPointerTy(DAG.getDataLayout()));
15258 SDValue Res = DAG.getUNDEF(LoadUnitVecVT);
15260 for (unsigned i = 0; i < NumLoads; ++i) {
15261 // Perform a single load.
15262 SDValue ScalarLoad =
15263 DAG.getLoad(SclrLoadTy, dl, Ld->getChain(), Ptr, Ld->getPointerInfo(),
15264 Ld->isVolatile(), Ld->isNonTemporal(), Ld->isInvariant(),
15265 Ld->getAlignment());
15266 Chains.push_back(ScalarLoad.getValue(1));
15267 // Create the first element type using SCALAR_TO_VECTOR in order to avoid
15268 // another round of DAGCombining.
15270 Res = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, LoadUnitVecVT, ScalarLoad);
15272 Res = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, LoadUnitVecVT, Res,
15273 ScalarLoad, DAG.getIntPtrConstant(i, dl));
15275 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
15278 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Chains);
15280 // Bitcast the loaded value to a vector of the original element type, in
15281 // the size of the target vector type.
15282 SDValue SlicedVec = DAG.getBitcast(WideVecVT, Res);
15283 unsigned SizeRatio = RegSz / MemSz;
15285 if (Ext == ISD::SEXTLOAD) {
15286 // If we have SSE4.1, we can directly emit a VSEXT node.
15287 if (Subtarget->hasSSE41()) {
15288 SDValue Sext = DAG.getNode(X86ISD::VSEXT, dl, RegVT, SlicedVec);
15289 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), TF);
15293 // Otherwise we'll use SIGN_EXTEND_VECTOR_INREG to sign extend the lowest
15295 assert(TLI.isOperationLegalOrCustom(ISD::SIGN_EXTEND_VECTOR_INREG, RegVT) &&
15296 "We can't implement a sext load without SIGN_EXTEND_VECTOR_INREG!");
15298 SDValue Shuff = DAG.getSignExtendVectorInReg(SlicedVec, dl, RegVT);
15299 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), TF);
15303 // Redistribute the loaded elements into the different locations.
15304 SmallVector<int, 16> ShuffleVec(NumElems * SizeRatio, -1);
15305 for (unsigned i = 0; i != NumElems; ++i)
15306 ShuffleVec[i * SizeRatio] = i;
15308 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, SlicedVec,
15309 DAG.getUNDEF(WideVecVT), &ShuffleVec[0]);
15311 // Bitcast to the requested type.
15312 Shuff = DAG.getBitcast(RegVT, Shuff);
15313 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), TF);
15317 // isAndOrOfSingleUseSetCCs - Return true if node is an ISD::AND or
15318 // ISD::OR of two X86ISD::SETCC nodes each of which has no other use apart
15319 // from the AND / OR.
15320 static bool isAndOrOfSetCCs(SDValue Op, unsigned &Opc) {
15321 Opc = Op.getOpcode();
15322 if (Opc != ISD::OR && Opc != ISD::AND)
15324 return (Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
15325 Op.getOperand(0).hasOneUse() &&
15326 Op.getOperand(1).getOpcode() == X86ISD::SETCC &&
15327 Op.getOperand(1).hasOneUse());
15330 // isXor1OfSetCC - Return true if node is an ISD::XOR of a X86ISD::SETCC and
15331 // 1 and that the SETCC node has a single use.
15332 static bool isXor1OfSetCC(SDValue Op) {
15333 if (Op.getOpcode() != ISD::XOR)
15335 if (isOneConstant(Op.getOperand(1)))
15336 return Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
15337 Op.getOperand(0).hasOneUse();
15341 SDValue X86TargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) const {
15342 bool addTest = true;
15343 SDValue Chain = Op.getOperand(0);
15344 SDValue Cond = Op.getOperand(1);
15345 SDValue Dest = Op.getOperand(2);
15348 bool Inverted = false;
15350 if (Cond.getOpcode() == ISD::SETCC) {
15351 // Check for setcc([su]{add,sub,mul}o == 0).
15352 if (cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETEQ &&
15353 isNullConstant(Cond.getOperand(1)) &&
15354 Cond.getOperand(0).getResNo() == 1 &&
15355 (Cond.getOperand(0).getOpcode() == ISD::SADDO ||
15356 Cond.getOperand(0).getOpcode() == ISD::UADDO ||
15357 Cond.getOperand(0).getOpcode() == ISD::SSUBO ||
15358 Cond.getOperand(0).getOpcode() == ISD::USUBO ||
15359 Cond.getOperand(0).getOpcode() == ISD::SMULO ||
15360 Cond.getOperand(0).getOpcode() == ISD::UMULO)) {
15362 Cond = Cond.getOperand(0);
15364 SDValue NewCond = LowerSETCC(Cond, DAG);
15365 if (NewCond.getNode())
15370 // FIXME: LowerXALUO doesn't handle these!!
15371 else if (Cond.getOpcode() == X86ISD::ADD ||
15372 Cond.getOpcode() == X86ISD::SUB ||
15373 Cond.getOpcode() == X86ISD::SMUL ||
15374 Cond.getOpcode() == X86ISD::UMUL)
15375 Cond = LowerXALUO(Cond, DAG);
15378 // Look pass (and (setcc_carry (cmp ...)), 1).
15379 if (Cond.getOpcode() == ISD::AND &&
15380 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY &&
15381 isOneConstant(Cond.getOperand(1)))
15382 Cond = Cond.getOperand(0);
15384 // If condition flag is set by a X86ISD::CMP, then use it as the condition
15385 // setting operand in place of the X86ISD::SETCC.
15386 unsigned CondOpcode = Cond.getOpcode();
15387 if (CondOpcode == X86ISD::SETCC ||
15388 CondOpcode == X86ISD::SETCC_CARRY) {
15389 CC = Cond.getOperand(0);
15391 SDValue Cmp = Cond.getOperand(1);
15392 unsigned Opc = Cmp.getOpcode();
15393 // FIXME: WHY THE SPECIAL CASING OF LogicalCmp??
15394 if (isX86LogicalCmp(Cmp) || Opc == X86ISD::BT) {
15398 switch (cast<ConstantSDNode>(CC)->getZExtValue()) {
15402 // These can only come from an arithmetic instruction with overflow,
15403 // e.g. SADDO, UADDO.
15404 Cond = Cond.getNode()->getOperand(1);
15410 CondOpcode = Cond.getOpcode();
15411 if (CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO ||
15412 CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO ||
15413 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) &&
15414 Cond.getOperand(0).getValueType() != MVT::i8)) {
15415 SDValue LHS = Cond.getOperand(0);
15416 SDValue RHS = Cond.getOperand(1);
15417 unsigned X86Opcode;
15420 // Keep this in sync with LowerXALUO, otherwise we might create redundant
15421 // instructions that can't be removed afterwards (i.e. X86ISD::ADD and
15423 switch (CondOpcode) {
15424 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break;
15426 if (isOneConstant(RHS)) {
15427 X86Opcode = X86ISD::INC; X86Cond = X86::COND_O;
15430 X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break;
15431 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break;
15433 if (isOneConstant(RHS)) {
15434 X86Opcode = X86ISD::DEC; X86Cond = X86::COND_O;
15437 X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break;
15438 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break;
15439 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break;
15440 default: llvm_unreachable("unexpected overflowing operator");
15443 X86Cond = X86::GetOppositeBranchCondition((X86::CondCode)X86Cond);
15444 if (CondOpcode == ISD::UMULO)
15445 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(),
15448 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
15450 SDValue X86Op = DAG.getNode(X86Opcode, dl, VTs, LHS, RHS);
15452 if (CondOpcode == ISD::UMULO)
15453 Cond = X86Op.getValue(2);
15455 Cond = X86Op.getValue(1);
15457 CC = DAG.getConstant(X86Cond, dl, MVT::i8);
15461 if (Cond.hasOneUse() && isAndOrOfSetCCs(Cond, CondOpc)) {
15462 SDValue Cmp = Cond.getOperand(0).getOperand(1);
15463 if (CondOpc == ISD::OR) {
15464 // Also, recognize the pattern generated by an FCMP_UNE. We can emit
15465 // two branches instead of an explicit OR instruction with a
15467 if (Cmp == Cond.getOperand(1).getOperand(1) &&
15468 isX86LogicalCmp(Cmp)) {
15469 CC = Cond.getOperand(0).getOperand(0);
15470 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
15471 Chain, Dest, CC, Cmp);
15472 CC = Cond.getOperand(1).getOperand(0);
15476 } else { // ISD::AND
15477 // Also, recognize the pattern generated by an FCMP_OEQ. We can emit
15478 // two branches instead of an explicit AND instruction with a
15479 // separate test. However, we only do this if this block doesn't
15480 // have a fall-through edge, because this requires an explicit
15481 // jmp when the condition is false.
15482 if (Cmp == Cond.getOperand(1).getOperand(1) &&
15483 isX86LogicalCmp(Cmp) &&
15484 Op.getNode()->hasOneUse()) {
15485 X86::CondCode CCode =
15486 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
15487 CCode = X86::GetOppositeBranchCondition(CCode);
15488 CC = DAG.getConstant(CCode, dl, MVT::i8);
15489 SDNode *User = *Op.getNode()->use_begin();
15490 // Look for an unconditional branch following this conditional branch.
15491 // We need this because we need to reverse the successors in order
15492 // to implement FCMP_OEQ.
15493 if (User->getOpcode() == ISD::BR) {
15494 SDValue FalseBB = User->getOperand(1);
15496 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
15497 assert(NewBR == User);
15501 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
15502 Chain, Dest, CC, Cmp);
15503 X86::CondCode CCode =
15504 (X86::CondCode)Cond.getOperand(1).getConstantOperandVal(0);
15505 CCode = X86::GetOppositeBranchCondition(CCode);
15506 CC = DAG.getConstant(CCode, dl, MVT::i8);
15512 } else if (Cond.hasOneUse() && isXor1OfSetCC(Cond)) {
15513 // Recognize for xorb (setcc), 1 patterns. The xor inverts the condition.
15514 // It should be transformed during dag combiner except when the condition
15515 // is set by a arithmetics with overflow node.
15516 X86::CondCode CCode =
15517 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
15518 CCode = X86::GetOppositeBranchCondition(CCode);
15519 CC = DAG.getConstant(CCode, dl, MVT::i8);
15520 Cond = Cond.getOperand(0).getOperand(1);
15522 } else if (Cond.getOpcode() == ISD::SETCC &&
15523 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETOEQ) {
15524 // For FCMP_OEQ, we can emit
15525 // two branches instead of an explicit AND instruction with a
15526 // separate test. However, we only do this if this block doesn't
15527 // have a fall-through edge, because this requires an explicit
15528 // jmp when the condition is false.
15529 if (Op.getNode()->hasOneUse()) {
15530 SDNode *User = *Op.getNode()->use_begin();
15531 // Look for an unconditional branch following this conditional branch.
15532 // We need this because we need to reverse the successors in order
15533 // to implement FCMP_OEQ.
15534 if (User->getOpcode() == ISD::BR) {
15535 SDValue FalseBB = User->getOperand(1);
15537 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
15538 assert(NewBR == User);
15542 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
15543 Cond.getOperand(0), Cond.getOperand(1));
15544 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
15545 CC = DAG.getConstant(X86::COND_NE, dl, MVT::i8);
15546 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
15547 Chain, Dest, CC, Cmp);
15548 CC = DAG.getConstant(X86::COND_P, dl, MVT::i8);
15553 } else if (Cond.getOpcode() == ISD::SETCC &&
15554 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETUNE) {
15555 // For FCMP_UNE, we can emit
15556 // two branches instead of an explicit AND instruction with a
15557 // separate test. However, we only do this if this block doesn't
15558 // have a fall-through edge, because this requires an explicit
15559 // jmp when the condition is false.
15560 if (Op.getNode()->hasOneUse()) {
15561 SDNode *User = *Op.getNode()->use_begin();
15562 // Look for an unconditional branch following this conditional branch.
15563 // We need this because we need to reverse the successors in order
15564 // to implement FCMP_UNE.
15565 if (User->getOpcode() == ISD::BR) {
15566 SDValue FalseBB = User->getOperand(1);
15568 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
15569 assert(NewBR == User);
15572 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
15573 Cond.getOperand(0), Cond.getOperand(1));
15574 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
15575 CC = DAG.getConstant(X86::COND_NE, dl, MVT::i8);
15576 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
15577 Chain, Dest, CC, Cmp);
15578 CC = DAG.getConstant(X86::COND_NP, dl, MVT::i8);
15588 // Look pass the truncate if the high bits are known zero.
15589 if (isTruncWithZeroHighBitsInput(Cond, DAG))
15590 Cond = Cond.getOperand(0);
15592 // We know the result of AND is compared against zero. Try to match
15594 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
15595 if (SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, dl, DAG)) {
15596 CC = NewSetCC.getOperand(0);
15597 Cond = NewSetCC.getOperand(1);
15604 X86::CondCode X86Cond = Inverted ? X86::COND_E : X86::COND_NE;
15605 CC = DAG.getConstant(X86Cond, dl, MVT::i8);
15606 Cond = EmitTest(Cond, X86Cond, dl, DAG);
15608 Cond = ConvertCmpIfNecessary(Cond, DAG);
15609 return DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
15610 Chain, Dest, CC, Cond);
15613 // Lower dynamic stack allocation to _alloca call for Cygwin/Mingw targets.
15614 // Calls to _alloca are needed to probe the stack when allocating more than 4k
15615 // bytes in one go. Touching the stack at 4K increments is necessary to ensure
15616 // that the guard pages used by the OS virtual memory manager are allocated in
15617 // correct sequence.
15619 X86TargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
15620 SelectionDAG &DAG) const {
15621 MachineFunction &MF = DAG.getMachineFunction();
15622 bool SplitStack = MF.shouldSplitStack();
15623 bool Lower = (Subtarget->isOSWindows() && !Subtarget->isTargetMachO()) ||
15628 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
15629 SDNode* Node = Op.getNode();
15631 unsigned SPReg = TLI.getStackPointerRegisterToSaveRestore();
15632 assert(SPReg && "Target cannot require DYNAMIC_STACKALLOC expansion and"
15633 " not tell us which reg is the stack pointer!");
15634 EVT VT = Node->getValueType(0);
15635 SDValue Tmp1 = SDValue(Node, 0);
15636 SDValue Tmp2 = SDValue(Node, 1);
15637 SDValue Tmp3 = Node->getOperand(2);
15638 SDValue Chain = Tmp1.getOperand(0);
15640 // Chain the dynamic stack allocation so that it doesn't modify the stack
15641 // pointer when other instructions are using the stack.
15642 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(0, dl, true),
15645 SDValue Size = Tmp2.getOperand(1);
15646 SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, VT);
15647 Chain = SP.getValue(1);
15648 unsigned Align = cast<ConstantSDNode>(Tmp3)->getZExtValue();
15649 const TargetFrameLowering &TFI = *Subtarget->getFrameLowering();
15650 unsigned StackAlign = TFI.getStackAlignment();
15651 Tmp1 = DAG.getNode(ISD::SUB, dl, VT, SP, Size); // Value
15652 if (Align > StackAlign)
15653 Tmp1 = DAG.getNode(ISD::AND, dl, VT, Tmp1,
15654 DAG.getConstant(-(uint64_t)Align, dl, VT));
15655 Chain = DAG.getCopyToReg(Chain, dl, SPReg, Tmp1); // Output chain
15657 Tmp2 = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(0, dl, true),
15658 DAG.getIntPtrConstant(0, dl, true), SDValue(),
15661 SDValue Ops[2] = { Tmp1, Tmp2 };
15662 return DAG.getMergeValues(Ops, dl);
15666 SDValue Chain = Op.getOperand(0);
15667 SDValue Size = Op.getOperand(1);
15668 unsigned Align = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue();
15669 EVT VT = Op.getNode()->getValueType(0);
15671 bool Is64Bit = Subtarget->is64Bit();
15672 MVT SPTy = getPointerTy(DAG.getDataLayout());
15675 MachineRegisterInfo &MRI = MF.getRegInfo();
15678 // The 64 bit implementation of segmented stacks needs to clobber both r10
15679 // r11. This makes it impossible to use it along with nested parameters.
15680 const Function *F = MF.getFunction();
15682 for (Function::const_arg_iterator I = F->arg_begin(), E = F->arg_end();
15684 if (I->hasNestAttr())
15685 report_fatal_error("Cannot use segmented stacks with functions that "
15686 "have nested arguments.");
15689 const TargetRegisterClass *AddrRegClass = getRegClassFor(SPTy);
15690 unsigned Vreg = MRI.createVirtualRegister(AddrRegClass);
15691 Chain = DAG.getCopyToReg(Chain, dl, Vreg, Size);
15692 SDValue Value = DAG.getNode(X86ISD::SEG_ALLOCA, dl, SPTy, Chain,
15693 DAG.getRegister(Vreg, SPTy));
15694 SDValue Ops1[2] = { Value, Chain };
15695 return DAG.getMergeValues(Ops1, dl);
15698 const unsigned Reg = (Subtarget->isTarget64BitLP64() ? X86::RAX : X86::EAX);
15700 Chain = DAG.getCopyToReg(Chain, dl, Reg, Size, Flag);
15701 Flag = Chain.getValue(1);
15702 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
15704 Chain = DAG.getNode(X86ISD::WIN_ALLOCA, dl, NodeTys, Chain, Flag);
15706 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
15707 unsigned SPReg = RegInfo->getStackRegister();
15708 SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, SPTy);
15709 Chain = SP.getValue(1);
15712 SP = DAG.getNode(ISD::AND, dl, VT, SP.getValue(0),
15713 DAG.getConstant(-(uint64_t)Align, dl, VT));
15714 Chain = DAG.getCopyToReg(Chain, dl, SPReg, SP);
15717 SDValue Ops1[2] = { SP, Chain };
15718 return DAG.getMergeValues(Ops1, dl);
15722 SDValue X86TargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const {
15723 MachineFunction &MF = DAG.getMachineFunction();
15724 auto PtrVT = getPointerTy(MF.getDataLayout());
15725 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
15727 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
15730 if (!Subtarget->is64Bit() ||
15731 Subtarget->isCallingConvWin64(MF.getFunction()->getCallingConv())) {
15732 // vastart just stores the address of the VarArgsFrameIndex slot into the
15733 // memory location argument.
15734 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
15735 return DAG.getStore(Op.getOperand(0), DL, FR, Op.getOperand(1),
15736 MachinePointerInfo(SV), false, false, 0);
15740 // gp_offset (0 - 6 * 8)
15741 // fp_offset (48 - 48 + 8 * 16)
15742 // overflow_arg_area (point to parameters coming in memory).
15744 SmallVector<SDValue, 8> MemOps;
15745 SDValue FIN = Op.getOperand(1);
15747 SDValue Store = DAG.getStore(Op.getOperand(0), DL,
15748 DAG.getConstant(FuncInfo->getVarArgsGPOffset(),
15750 FIN, MachinePointerInfo(SV), false, false, 0);
15751 MemOps.push_back(Store);
15754 FIN = DAG.getNode(ISD::ADD, DL, PtrVT, FIN, DAG.getIntPtrConstant(4, DL));
15755 Store = DAG.getStore(Op.getOperand(0), DL,
15756 DAG.getConstant(FuncInfo->getVarArgsFPOffset(), DL,
15758 FIN, MachinePointerInfo(SV, 4), false, false, 0);
15759 MemOps.push_back(Store);
15761 // Store ptr to overflow_arg_area
15762 FIN = DAG.getNode(ISD::ADD, DL, PtrVT, FIN, DAG.getIntPtrConstant(4, DL));
15763 SDValue OVFIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
15764 Store = DAG.getStore(Op.getOperand(0), DL, OVFIN, FIN,
15765 MachinePointerInfo(SV, 8),
15767 MemOps.push_back(Store);
15769 // Store ptr to reg_save_area.
15770 FIN = DAG.getNode(ISD::ADD, DL, PtrVT, FIN, DAG.getIntPtrConstant(
15771 Subtarget->isTarget64BitLP64() ? 8 : 4, DL));
15772 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(), PtrVT);
15773 Store = DAG.getStore(Op.getOperand(0), DL, RSFIN, FIN, MachinePointerInfo(
15774 SV, Subtarget->isTarget64BitLP64() ? 16 : 12), false, false, 0);
15775 MemOps.push_back(Store);
15776 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOps);
15779 SDValue X86TargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG) const {
15780 assert(Subtarget->is64Bit() &&
15781 "LowerVAARG only handles 64-bit va_arg!");
15782 assert(Op.getNode()->getNumOperands() == 4);
15784 MachineFunction &MF = DAG.getMachineFunction();
15785 if (Subtarget->isCallingConvWin64(MF.getFunction()->getCallingConv()))
15786 // The Win64 ABI uses char* instead of a structure.
15787 return DAG.expandVAArg(Op.getNode());
15789 SDValue Chain = Op.getOperand(0);
15790 SDValue SrcPtr = Op.getOperand(1);
15791 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
15792 unsigned Align = Op.getConstantOperandVal(3);
15795 EVT ArgVT = Op.getNode()->getValueType(0);
15796 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
15797 uint32_t ArgSize = DAG.getDataLayout().getTypeAllocSize(ArgTy);
15800 // Decide which area this value should be read from.
15801 // TODO: Implement the AMD64 ABI in its entirety. This simple
15802 // selection mechanism works only for the basic types.
15803 if (ArgVT == MVT::f80) {
15804 llvm_unreachable("va_arg for f80 not yet implemented");
15805 } else if (ArgVT.isFloatingPoint() && ArgSize <= 16 /*bytes*/) {
15806 ArgMode = 2; // Argument passed in XMM register. Use fp_offset.
15807 } else if (ArgVT.isInteger() && ArgSize <= 32 /*bytes*/) {
15808 ArgMode = 1; // Argument passed in GPR64 register(s). Use gp_offset.
15810 llvm_unreachable("Unhandled argument type in LowerVAARG");
15813 if (ArgMode == 2) {
15814 // Sanity Check: Make sure using fp_offset makes sense.
15815 assert(!Subtarget->useSoftFloat() &&
15816 !(MF.getFunction()->hasFnAttribute(Attribute::NoImplicitFloat)) &&
15817 Subtarget->hasSSE1());
15820 // Insert VAARG_64 node into the DAG
15821 // VAARG_64 returns two values: Variable Argument Address, Chain
15822 SDValue InstOps[] = {Chain, SrcPtr, DAG.getConstant(ArgSize, dl, MVT::i32),
15823 DAG.getConstant(ArgMode, dl, MVT::i8),
15824 DAG.getConstant(Align, dl, MVT::i32)};
15825 SDVTList VTs = DAG.getVTList(getPointerTy(DAG.getDataLayout()), MVT::Other);
15826 SDValue VAARG = DAG.getMemIntrinsicNode(X86ISD::VAARG_64, dl,
15827 VTs, InstOps, MVT::i64,
15828 MachinePointerInfo(SV),
15830 /*Volatile=*/false,
15832 /*WriteMem=*/true);
15833 Chain = VAARG.getValue(1);
15835 // Load the next argument and return it
15836 return DAG.getLoad(ArgVT, dl,
15839 MachinePointerInfo(),
15840 false, false, false, 0);
15843 static SDValue LowerVACOPY(SDValue Op, const X86Subtarget *Subtarget,
15844 SelectionDAG &DAG) {
15845 // X86-64 va_list is a struct { i32, i32, i8*, i8* }, except on Windows,
15846 // where a va_list is still an i8*.
15847 assert(Subtarget->is64Bit() && "This code only handles 64-bit va_copy!");
15848 if (Subtarget->isCallingConvWin64(
15849 DAG.getMachineFunction().getFunction()->getCallingConv()))
15850 // Probably a Win64 va_copy.
15851 return DAG.expandVACopy(Op.getNode());
15853 SDValue Chain = Op.getOperand(0);
15854 SDValue DstPtr = Op.getOperand(1);
15855 SDValue SrcPtr = Op.getOperand(2);
15856 const Value *DstSV = cast<SrcValueSDNode>(Op.getOperand(3))->getValue();
15857 const Value *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
15860 return DAG.getMemcpy(Chain, DL, DstPtr, SrcPtr,
15861 DAG.getIntPtrConstant(24, DL), 8, /*isVolatile*/false,
15863 MachinePointerInfo(DstSV), MachinePointerInfo(SrcSV));
15866 // getTargetVShiftByConstNode - Handle vector element shifts where the shift
15867 // amount is a constant. Takes immediate version of shift as input.
15868 static SDValue getTargetVShiftByConstNode(unsigned Opc, SDLoc dl, MVT VT,
15869 SDValue SrcOp, uint64_t ShiftAmt,
15870 SelectionDAG &DAG) {
15871 MVT ElementType = VT.getVectorElementType();
15873 // Fold this packed shift into its first operand if ShiftAmt is 0.
15877 // Check for ShiftAmt >= element width
15878 if (ShiftAmt >= ElementType.getSizeInBits()) {
15879 if (Opc == X86ISD::VSRAI)
15880 ShiftAmt = ElementType.getSizeInBits() - 1;
15882 return DAG.getConstant(0, dl, VT);
15885 assert((Opc == X86ISD::VSHLI || Opc == X86ISD::VSRLI || Opc == X86ISD::VSRAI)
15886 && "Unknown target vector shift-by-constant node");
15888 // Fold this packed vector shift into a build vector if SrcOp is a
15889 // vector of Constants or UNDEFs, and SrcOp valuetype is the same as VT.
15890 if (VT == SrcOp.getSimpleValueType() &&
15891 ISD::isBuildVectorOfConstantSDNodes(SrcOp.getNode())) {
15892 SmallVector<SDValue, 8> Elts;
15893 unsigned NumElts = SrcOp->getNumOperands();
15894 ConstantSDNode *ND;
15897 default: llvm_unreachable(nullptr);
15898 case X86ISD::VSHLI:
15899 for (unsigned i=0; i!=NumElts; ++i) {
15900 SDValue CurrentOp = SrcOp->getOperand(i);
15901 if (CurrentOp->getOpcode() == ISD::UNDEF) {
15902 Elts.push_back(CurrentOp);
15905 ND = cast<ConstantSDNode>(CurrentOp);
15906 const APInt &C = ND->getAPIntValue();
15907 Elts.push_back(DAG.getConstant(C.shl(ShiftAmt), dl, ElementType));
15910 case X86ISD::VSRLI:
15911 for (unsigned i=0; i!=NumElts; ++i) {
15912 SDValue CurrentOp = SrcOp->getOperand(i);
15913 if (CurrentOp->getOpcode() == ISD::UNDEF) {
15914 Elts.push_back(CurrentOp);
15917 ND = cast<ConstantSDNode>(CurrentOp);
15918 const APInt &C = ND->getAPIntValue();
15919 Elts.push_back(DAG.getConstant(C.lshr(ShiftAmt), dl, ElementType));
15922 case X86ISD::VSRAI:
15923 for (unsigned i=0; i!=NumElts; ++i) {
15924 SDValue CurrentOp = SrcOp->getOperand(i);
15925 if (CurrentOp->getOpcode() == ISD::UNDEF) {
15926 Elts.push_back(CurrentOp);
15929 ND = cast<ConstantSDNode>(CurrentOp);
15930 const APInt &C = ND->getAPIntValue();
15931 Elts.push_back(DAG.getConstant(C.ashr(ShiftAmt), dl, ElementType));
15936 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Elts);
15939 return DAG.getNode(Opc, dl, VT, SrcOp,
15940 DAG.getConstant(ShiftAmt, dl, MVT::i8));
15943 // getTargetVShiftNode - Handle vector element shifts where the shift amount
15944 // may or may not be a constant. Takes immediate version of shift as input.
15945 static SDValue getTargetVShiftNode(unsigned Opc, SDLoc dl, MVT VT,
15946 SDValue SrcOp, SDValue ShAmt,
15947 SelectionDAG &DAG) {
15948 MVT SVT = ShAmt.getSimpleValueType();
15949 assert((SVT == MVT::i32 || SVT == MVT::i64) && "Unexpected value type!");
15951 // Catch shift-by-constant.
15952 if (ConstantSDNode *CShAmt = dyn_cast<ConstantSDNode>(ShAmt))
15953 return getTargetVShiftByConstNode(Opc, dl, VT, SrcOp,
15954 CShAmt->getZExtValue(), DAG);
15956 // Change opcode to non-immediate version
15958 default: llvm_unreachable("Unknown target vector shift node");
15959 case X86ISD::VSHLI: Opc = X86ISD::VSHL; break;
15960 case X86ISD::VSRLI: Opc = X86ISD::VSRL; break;
15961 case X86ISD::VSRAI: Opc = X86ISD::VSRA; break;
15964 const X86Subtarget &Subtarget =
15965 static_cast<const X86Subtarget &>(DAG.getSubtarget());
15966 if (Subtarget.hasSSE41() && ShAmt.getOpcode() == ISD::ZERO_EXTEND &&
15967 ShAmt.getOperand(0).getSimpleValueType() == MVT::i16) {
15968 // Let the shuffle legalizer expand this shift amount node.
15969 SDValue Op0 = ShAmt.getOperand(0);
15970 Op0 = DAG.getNode(ISD::SCALAR_TO_VECTOR, SDLoc(Op0), MVT::v8i16, Op0);
15971 ShAmt = getShuffleVectorZeroOrUndef(Op0, 0, true, &Subtarget, DAG);
15973 // Need to build a vector containing shift amount.
15974 // SSE/AVX packed shifts only use the lower 64-bit of the shift count.
15975 SmallVector<SDValue, 4> ShOps;
15976 ShOps.push_back(ShAmt);
15977 if (SVT == MVT::i32) {
15978 ShOps.push_back(DAG.getConstant(0, dl, SVT));
15979 ShOps.push_back(DAG.getUNDEF(SVT));
15981 ShOps.push_back(DAG.getUNDEF(SVT));
15983 MVT BVT = SVT == MVT::i32 ? MVT::v4i32 : MVT::v2i64;
15984 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, BVT, ShOps);
15987 // The return type has to be a 128-bit type with the same element
15988 // type as the input type.
15989 MVT EltVT = VT.getVectorElementType();
15990 MVT ShVT = MVT::getVectorVT(EltVT, 128/EltVT.getSizeInBits());
15992 ShAmt = DAG.getBitcast(ShVT, ShAmt);
15993 return DAG.getNode(Opc, dl, VT, SrcOp, ShAmt);
15996 /// \brief Return (and \p Op, \p Mask) for compare instructions or
15997 /// (vselect \p Mask, \p Op, \p PreservedSrc) for others along with the
15998 /// necessary casting or extending for \p Mask when lowering masking intrinsics
15999 static SDValue getVectorMaskingNode(SDValue Op, SDValue Mask,
16000 SDValue PreservedSrc,
16001 const X86Subtarget *Subtarget,
16002 SelectionDAG &DAG) {
16003 MVT VT = Op.getSimpleValueType();
16004 MVT MaskVT = MVT::getVectorVT(MVT::i1, VT.getVectorNumElements());
16006 unsigned OpcodeSelect = ISD::VSELECT;
16009 if (isAllOnesConstant(Mask))
16012 if (MaskVT.bitsGT(Mask.getSimpleValueType())) {
16013 MVT newMaskVT = MVT::getIntegerVT(MaskVT.getSizeInBits());
16014 VMask = DAG.getBitcast(MaskVT,
16015 DAG.getNode(ISD::ANY_EXTEND, dl, newMaskVT, Mask));
16017 MVT BitcastVT = MVT::getVectorVT(MVT::i1,
16018 Mask.getSimpleValueType().getSizeInBits());
16019 // In case when MaskVT equals v2i1 or v4i1, low 2 or 4 elements
16020 // are extracted by EXTRACT_SUBVECTOR.
16021 VMask = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MaskVT,
16022 DAG.getBitcast(BitcastVT, Mask),
16023 DAG.getIntPtrConstant(0, dl));
16026 switch (Op.getOpcode()) {
16028 case X86ISD::PCMPEQM:
16029 case X86ISD::PCMPGTM:
16031 case X86ISD::CMPMU:
16032 return DAG.getNode(ISD::AND, dl, VT, Op, VMask);
16033 case X86ISD::VFPCLASS:
16034 case X86ISD::VFPCLASSS:
16035 return DAG.getNode(ISD::OR, dl, VT, Op, VMask);
16036 case X86ISD::VTRUNC:
16037 case X86ISD::VTRUNCS:
16038 case X86ISD::VTRUNCUS:
16039 // We can't use ISD::VSELECT here because it is not always "Legal"
16040 // for the destination type. For example vpmovqb require only AVX512
16041 // and vselect that can operate on byte element type require BWI
16042 OpcodeSelect = X86ISD::SELECT;
16045 if (PreservedSrc.getOpcode() == ISD::UNDEF)
16046 PreservedSrc = getZeroVector(VT, Subtarget, DAG, dl);
16047 return DAG.getNode(OpcodeSelect, dl, VT, VMask, Op, PreservedSrc);
16050 /// \brief Creates an SDNode for a predicated scalar operation.
16051 /// \returns (X86vselect \p Mask, \p Op, \p PreservedSrc).
16052 /// The mask is coming as MVT::i8 and it should be truncated
16053 /// to MVT::i1 while lowering masking intrinsics.
16054 /// The main difference between ScalarMaskingNode and VectorMaskingNode is using
16055 /// "X86select" instead of "vselect". We just can't create the "vselect" node
16056 /// for a scalar instruction.
16057 static SDValue getScalarMaskingNode(SDValue Op, SDValue Mask,
16058 SDValue PreservedSrc,
16059 const X86Subtarget *Subtarget,
16060 SelectionDAG &DAG) {
16061 if (isAllOnesConstant(Mask))
16064 MVT VT = Op.getSimpleValueType();
16066 // The mask should be of type MVT::i1
16067 SDValue IMask = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, Mask);
16069 if (Op.getOpcode() == X86ISD::FSETCC)
16070 return DAG.getNode(ISD::AND, dl, VT, Op, IMask);
16071 if (Op.getOpcode() == X86ISD::VFPCLASS ||
16072 Op.getOpcode() == X86ISD::VFPCLASSS)
16073 return DAG.getNode(ISD::OR, dl, VT, Op, IMask);
16075 if (PreservedSrc.getOpcode() == ISD::UNDEF)
16076 PreservedSrc = getZeroVector(VT, Subtarget, DAG, dl);
16077 return DAG.getNode(X86ISD::SELECT, dl, VT, IMask, Op, PreservedSrc);
16080 static int getSEHRegistrationNodeSize(const Function *Fn) {
16081 if (!Fn->hasPersonalityFn())
16082 report_fatal_error(
16083 "querying registration node size for function without personality");
16084 // The RegNodeSize is 6 32-bit words for SEH and 4 for C++ EH. See
16085 // WinEHStatePass for the full struct definition.
16086 switch (classifyEHPersonality(Fn->getPersonalityFn())) {
16087 case EHPersonality::MSVC_X86SEH: return 24;
16088 case EHPersonality::MSVC_CXX: return 16;
16091 report_fatal_error("can only recover FP for MSVC EH personality functions");
16094 /// When the 32-bit MSVC runtime transfers control to us, either to an outlined
16095 /// function or when returning to a parent frame after catching an exception, we
16096 /// recover the parent frame pointer by doing arithmetic on the incoming EBP.
16097 /// Here's the math:
16098 /// RegNodeBase = EntryEBP - RegNodeSize
16099 /// ParentFP = RegNodeBase - RegNodeFrameOffset
16100 /// Subtracting RegNodeSize takes us to the offset of the registration node, and
16101 /// subtracting the offset (negative on x86) takes us back to the parent FP.
16102 static SDValue recoverFramePointer(SelectionDAG &DAG, const Function *Fn,
16103 SDValue EntryEBP) {
16104 MachineFunction &MF = DAG.getMachineFunction();
16107 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
16108 MVT PtrVT = TLI.getPointerTy(DAG.getDataLayout());
16110 // It's possible that the parent function no longer has a personality function
16111 // if the exceptional code was optimized away, in which case we just return
16112 // the incoming EBP.
16113 if (!Fn->hasPersonalityFn())
16116 int RegNodeSize = getSEHRegistrationNodeSize(Fn);
16118 // Get an MCSymbol that will ultimately resolve to the frame offset of the EH
16120 MCSymbol *OffsetSym =
16121 MF.getMMI().getContext().getOrCreateParentFrameOffsetSymbol(
16122 GlobalValue::getRealLinkageName(Fn->getName()));
16123 SDValue OffsetSymVal = DAG.getMCSymbol(OffsetSym, PtrVT);
16124 SDValue RegNodeFrameOffset =
16125 DAG.getNode(ISD::LOCAL_RECOVER, dl, PtrVT, OffsetSymVal);
16127 // RegNodeBase = EntryEBP - RegNodeSize
16128 // ParentFP = RegNodeBase - RegNodeFrameOffset
16129 SDValue RegNodeBase = DAG.getNode(ISD::SUB, dl, PtrVT, EntryEBP,
16130 DAG.getConstant(RegNodeSize, dl, PtrVT));
16131 return DAG.getNode(ISD::SUB, dl, PtrVT, RegNodeBase, RegNodeFrameOffset);
16134 static SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, const X86Subtarget *Subtarget,
16135 SelectionDAG &DAG) {
16137 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
16138 MVT VT = Op.getSimpleValueType();
16139 const IntrinsicData* IntrData = getIntrinsicWithoutChain(IntNo);
16141 switch(IntrData->Type) {
16142 case INTR_TYPE_1OP:
16143 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1));
16144 case INTR_TYPE_2OP:
16145 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1),
16147 case INTR_TYPE_2OP_IMM8:
16148 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1),
16149 DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op.getOperand(2)));
16150 case INTR_TYPE_3OP:
16151 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1),
16152 Op.getOperand(2), Op.getOperand(3));
16153 case INTR_TYPE_4OP:
16154 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1),
16155 Op.getOperand(2), Op.getOperand(3), Op.getOperand(4));
16156 case INTR_TYPE_1OP_MASK_RM: {
16157 SDValue Src = Op.getOperand(1);
16158 SDValue PassThru = Op.getOperand(2);
16159 SDValue Mask = Op.getOperand(3);
16160 SDValue RoundingMode;
16161 // We allways add rounding mode to the Node.
16162 // If the rounding mode is not specified, we add the
16163 // "current direction" mode.
16164 if (Op.getNumOperands() == 4)
16166 DAG.getConstant(X86::STATIC_ROUNDING::CUR_DIRECTION, dl, MVT::i32);
16168 RoundingMode = Op.getOperand(4);
16169 unsigned IntrWithRoundingModeOpcode = IntrData->Opc1;
16170 if (IntrWithRoundingModeOpcode != 0)
16171 if (cast<ConstantSDNode>(RoundingMode)->getZExtValue() !=
16172 X86::STATIC_ROUNDING::CUR_DIRECTION)
16173 return getVectorMaskingNode(DAG.getNode(IntrWithRoundingModeOpcode,
16174 dl, Op.getValueType(), Src, RoundingMode),
16175 Mask, PassThru, Subtarget, DAG);
16176 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT, Src,
16178 Mask, PassThru, Subtarget, DAG);
16180 case INTR_TYPE_1OP_MASK: {
16181 SDValue Src = Op.getOperand(1);
16182 SDValue PassThru = Op.getOperand(2);
16183 SDValue Mask = Op.getOperand(3);
16184 // We add rounding mode to the Node when
16185 // - RM Opcode is specified and
16186 // - RM is not "current direction".
16187 unsigned IntrWithRoundingModeOpcode = IntrData->Opc1;
16188 if (IntrWithRoundingModeOpcode != 0) {
16189 SDValue Rnd = Op.getOperand(4);
16190 unsigned Round = cast<ConstantSDNode>(Rnd)->getZExtValue();
16191 if (Round != X86::STATIC_ROUNDING::CUR_DIRECTION) {
16192 return getVectorMaskingNode(DAG.getNode(IntrWithRoundingModeOpcode,
16193 dl, Op.getValueType(),
16195 Mask, PassThru, Subtarget, DAG);
16198 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT, Src),
16199 Mask, PassThru, Subtarget, DAG);
16201 case INTR_TYPE_SCALAR_MASK: {
16202 SDValue Src1 = Op.getOperand(1);
16203 SDValue Src2 = Op.getOperand(2);
16204 SDValue passThru = Op.getOperand(3);
16205 SDValue Mask = Op.getOperand(4);
16206 return getScalarMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT, Src1, Src2),
16207 Mask, passThru, Subtarget, DAG);
16209 case INTR_TYPE_SCALAR_MASK_RM: {
16210 SDValue Src1 = Op.getOperand(1);
16211 SDValue Src2 = Op.getOperand(2);
16212 SDValue Src0 = Op.getOperand(3);
16213 SDValue Mask = Op.getOperand(4);
16214 // There are 2 kinds of intrinsics in this group:
16215 // (1) With suppress-all-exceptions (sae) or rounding mode- 6 operands
16216 // (2) With rounding mode and sae - 7 operands.
16217 if (Op.getNumOperands() == 6) {
16218 SDValue Sae = Op.getOperand(5);
16219 unsigned Opc = IntrData->Opc1 ? IntrData->Opc1 : IntrData->Opc0;
16220 return getScalarMaskingNode(DAG.getNode(Opc, dl, VT, Src1, Src2,
16222 Mask, Src0, Subtarget, DAG);
16224 assert(Op.getNumOperands() == 7 && "Unexpected intrinsic form");
16225 SDValue RoundingMode = Op.getOperand(5);
16226 SDValue Sae = Op.getOperand(6);
16227 return getScalarMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT, Src1, Src2,
16228 RoundingMode, Sae),
16229 Mask, Src0, Subtarget, DAG);
16231 case INTR_TYPE_2OP_MASK:
16232 case INTR_TYPE_2OP_IMM8_MASK: {
16233 SDValue Src1 = Op.getOperand(1);
16234 SDValue Src2 = Op.getOperand(2);
16235 SDValue PassThru = Op.getOperand(3);
16236 SDValue Mask = Op.getOperand(4);
16238 if (IntrData->Type == INTR_TYPE_2OP_IMM8_MASK)
16239 Src2 = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Src2);
16241 // We specify 2 possible opcodes for intrinsics with rounding modes.
16242 // First, we check if the intrinsic may have non-default rounding mode,
16243 // (IntrData->Opc1 != 0), then we check the rounding mode operand.
16244 unsigned IntrWithRoundingModeOpcode = IntrData->Opc1;
16245 if (IntrWithRoundingModeOpcode != 0) {
16246 SDValue Rnd = Op.getOperand(5);
16247 unsigned Round = cast<ConstantSDNode>(Rnd)->getZExtValue();
16248 if (Round != X86::STATIC_ROUNDING::CUR_DIRECTION) {
16249 return getVectorMaskingNode(DAG.getNode(IntrWithRoundingModeOpcode,
16250 dl, Op.getValueType(),
16252 Mask, PassThru, Subtarget, DAG);
16255 // TODO: Intrinsics should have fast-math-flags to propagate.
16256 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT,Src1,Src2),
16257 Mask, PassThru, Subtarget, DAG);
16259 case INTR_TYPE_2OP_MASK_RM: {
16260 SDValue Src1 = Op.getOperand(1);
16261 SDValue Src2 = Op.getOperand(2);
16262 SDValue PassThru = Op.getOperand(3);
16263 SDValue Mask = Op.getOperand(4);
16264 // We specify 2 possible modes for intrinsics, with/without rounding
16266 // First, we check if the intrinsic have rounding mode (6 operands),
16267 // if not, we set rounding mode to "current".
16269 if (Op.getNumOperands() == 6)
16270 Rnd = Op.getOperand(5);
16272 Rnd = DAG.getConstant(X86::STATIC_ROUNDING::CUR_DIRECTION, dl, MVT::i32);
16273 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT,
16275 Mask, PassThru, Subtarget, DAG);
16277 case INTR_TYPE_3OP_SCALAR_MASK_RM: {
16278 SDValue Src1 = Op.getOperand(1);
16279 SDValue Src2 = Op.getOperand(2);
16280 SDValue Src3 = Op.getOperand(3);
16281 SDValue PassThru = Op.getOperand(4);
16282 SDValue Mask = Op.getOperand(5);
16283 SDValue Sae = Op.getOperand(6);
16285 return getScalarMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT, Src1,
16287 Mask, PassThru, Subtarget, DAG);
16289 case INTR_TYPE_3OP_MASK_RM: {
16290 SDValue Src1 = Op.getOperand(1);
16291 SDValue Src2 = Op.getOperand(2);
16292 SDValue Imm = Op.getOperand(3);
16293 SDValue PassThru = Op.getOperand(4);
16294 SDValue Mask = Op.getOperand(5);
16295 // We specify 2 possible modes for intrinsics, with/without rounding
16297 // First, we check if the intrinsic have rounding mode (7 operands),
16298 // if not, we set rounding mode to "current".
16300 if (Op.getNumOperands() == 7)
16301 Rnd = Op.getOperand(6);
16303 Rnd = DAG.getConstant(X86::STATIC_ROUNDING::CUR_DIRECTION, dl, MVT::i32);
16304 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT,
16305 Src1, Src2, Imm, Rnd),
16306 Mask, PassThru, Subtarget, DAG);
16308 case INTR_TYPE_3OP_IMM8_MASK:
16309 case INTR_TYPE_3OP_MASK:
16310 case INSERT_SUBVEC: {
16311 SDValue Src1 = Op.getOperand(1);
16312 SDValue Src2 = Op.getOperand(2);
16313 SDValue Src3 = Op.getOperand(3);
16314 SDValue PassThru = Op.getOperand(4);
16315 SDValue Mask = Op.getOperand(5);
16317 if (IntrData->Type == INTR_TYPE_3OP_IMM8_MASK)
16318 Src3 = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Src3);
16319 else if (IntrData->Type == INSERT_SUBVEC) {
16320 // imm should be adapted to ISD::INSERT_SUBVECTOR behavior
16321 assert(isa<ConstantSDNode>(Src3) && "Expected a ConstantSDNode here!");
16322 unsigned Imm = cast<ConstantSDNode>(Src3)->getZExtValue();
16323 Imm *= Src2.getSimpleValueType().getVectorNumElements();
16324 Src3 = DAG.getTargetConstant(Imm, dl, MVT::i32);
16327 // We specify 2 possible opcodes for intrinsics with rounding modes.
16328 // First, we check if the intrinsic may have non-default rounding mode,
16329 // (IntrData->Opc1 != 0), then we check the rounding mode operand.
16330 unsigned IntrWithRoundingModeOpcode = IntrData->Opc1;
16331 if (IntrWithRoundingModeOpcode != 0) {
16332 SDValue Rnd = Op.getOperand(6);
16333 unsigned Round = cast<ConstantSDNode>(Rnd)->getZExtValue();
16334 if (Round != X86::STATIC_ROUNDING::CUR_DIRECTION) {
16335 return getVectorMaskingNode(DAG.getNode(IntrWithRoundingModeOpcode,
16336 dl, Op.getValueType(),
16337 Src1, Src2, Src3, Rnd),
16338 Mask, PassThru, Subtarget, DAG);
16341 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT,
16343 Mask, PassThru, Subtarget, DAG);
16345 case VPERM_3OP_MASKZ:
16346 case VPERM_3OP_MASK:{
16347 // Src2 is the PassThru
16348 SDValue Src1 = Op.getOperand(1);
16349 SDValue Src2 = Op.getOperand(2);
16350 SDValue Src3 = Op.getOperand(3);
16351 SDValue Mask = Op.getOperand(4);
16352 MVT VT = Op.getSimpleValueType();
16353 SDValue PassThru = SDValue();
16355 // set PassThru element
16356 if (IntrData->Type == VPERM_3OP_MASKZ)
16357 PassThru = getZeroVector(VT, Subtarget, DAG, dl);
16361 // Swap Src1 and Src2 in the node creation
16362 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0,
16363 dl, Op.getValueType(),
16365 Mask, PassThru, Subtarget, DAG);
16369 case FMA_OP_MASK: {
16370 SDValue Src1 = Op.getOperand(1);
16371 SDValue Src2 = Op.getOperand(2);
16372 SDValue Src3 = Op.getOperand(3);
16373 SDValue Mask = Op.getOperand(4);
16374 MVT VT = Op.getSimpleValueType();
16375 SDValue PassThru = SDValue();
16377 // set PassThru element
16378 if (IntrData->Type == FMA_OP_MASKZ)
16379 PassThru = getZeroVector(VT, Subtarget, DAG, dl);
16380 else if (IntrData->Type == FMA_OP_MASK3)
16385 // We specify 2 possible opcodes for intrinsics with rounding modes.
16386 // First, we check if the intrinsic may have non-default rounding mode,
16387 // (IntrData->Opc1 != 0), then we check the rounding mode operand.
16388 unsigned IntrWithRoundingModeOpcode = IntrData->Opc1;
16389 if (IntrWithRoundingModeOpcode != 0) {
16390 SDValue Rnd = Op.getOperand(5);
16391 if (cast<ConstantSDNode>(Rnd)->getZExtValue() !=
16392 X86::STATIC_ROUNDING::CUR_DIRECTION)
16393 return getVectorMaskingNode(DAG.getNode(IntrWithRoundingModeOpcode,
16394 dl, Op.getValueType(),
16395 Src1, Src2, Src3, Rnd),
16396 Mask, PassThru, Subtarget, DAG);
16398 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0,
16399 dl, Op.getValueType(),
16401 Mask, PassThru, Subtarget, DAG);
16403 case TERLOG_OP_MASK:
16404 case TERLOG_OP_MASKZ: {
16405 SDValue Src1 = Op.getOperand(1);
16406 SDValue Src2 = Op.getOperand(2);
16407 SDValue Src3 = Op.getOperand(3);
16408 SDValue Src4 = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op.getOperand(4));
16409 SDValue Mask = Op.getOperand(5);
16410 MVT VT = Op.getSimpleValueType();
16411 SDValue PassThru = Src1;
16412 // Set PassThru element.
16413 if (IntrData->Type == TERLOG_OP_MASKZ)
16414 PassThru = getZeroVector(VT, Subtarget, DAG, dl);
16416 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT,
16417 Src1, Src2, Src3, Src4),
16418 Mask, PassThru, Subtarget, DAG);
16421 // FPclass intrinsics with mask
16422 SDValue Src1 = Op.getOperand(1);
16423 MVT VT = Src1.getSimpleValueType();
16424 MVT MaskVT = MVT::getVectorVT(MVT::i1, VT.getVectorNumElements());
16425 SDValue Imm = Op.getOperand(2);
16426 SDValue Mask = Op.getOperand(3);
16427 MVT BitcastVT = MVT::getVectorVT(MVT::i1,
16428 Mask.getSimpleValueType().getSizeInBits());
16429 SDValue FPclass = DAG.getNode(IntrData->Opc0, dl, MaskVT, Src1, Imm);
16430 SDValue FPclassMask = getVectorMaskingNode(FPclass, Mask,
16431 DAG.getTargetConstant(0, dl, MaskVT),
16433 SDValue Res = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, BitcastVT,
16434 DAG.getUNDEF(BitcastVT), FPclassMask,
16435 DAG.getIntPtrConstant(0, dl));
16436 return DAG.getBitcast(Op.getValueType(), Res);
16439 SDValue Src1 = Op.getOperand(1);
16440 SDValue Imm = Op.getOperand(2);
16441 SDValue Mask = Op.getOperand(3);
16442 SDValue FPclass = DAG.getNode(IntrData->Opc0, dl, MVT::i1, Src1, Imm);
16443 SDValue FPclassMask = getScalarMaskingNode(FPclass, Mask,
16444 DAG.getTargetConstant(0, dl, MVT::i1), Subtarget, DAG);
16445 return DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::i8, FPclassMask);
16448 case CMP_MASK_CC: {
16449 // Comparison intrinsics with masks.
16450 // Example of transformation:
16451 // (i8 (int_x86_avx512_mask_pcmpeq_q_128
16452 // (v2i64 %a), (v2i64 %b), (i8 %mask))) ->
16454 // (v8i1 (insert_subvector undef,
16455 // (v2i1 (and (PCMPEQM %a, %b),
16456 // (extract_subvector
16457 // (v8i1 (bitcast %mask)), 0))), 0))))
16458 MVT VT = Op.getOperand(1).getSimpleValueType();
16459 MVT MaskVT = MVT::getVectorVT(MVT::i1, VT.getVectorNumElements());
16460 SDValue Mask = Op.getOperand((IntrData->Type == CMP_MASK_CC) ? 4 : 3);
16461 MVT BitcastVT = MVT::getVectorVT(MVT::i1,
16462 Mask.getSimpleValueType().getSizeInBits());
16464 if (IntrData->Type == CMP_MASK_CC) {
16465 SDValue CC = Op.getOperand(3);
16466 CC = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, CC);
16467 // We specify 2 possible opcodes for intrinsics with rounding modes.
16468 // First, we check if the intrinsic may have non-default rounding mode,
16469 // (IntrData->Opc1 != 0), then we check the rounding mode operand.
16470 if (IntrData->Opc1 != 0) {
16471 SDValue Rnd = Op.getOperand(5);
16472 if (cast<ConstantSDNode>(Rnd)->getZExtValue() !=
16473 X86::STATIC_ROUNDING::CUR_DIRECTION)
16474 Cmp = DAG.getNode(IntrData->Opc1, dl, MaskVT, Op.getOperand(1),
16475 Op.getOperand(2), CC, Rnd);
16477 //default rounding mode
16479 Cmp = DAG.getNode(IntrData->Opc0, dl, MaskVT, Op.getOperand(1),
16480 Op.getOperand(2), CC);
16483 assert(IntrData->Type == CMP_MASK && "Unexpected intrinsic type!");
16484 Cmp = DAG.getNode(IntrData->Opc0, dl, MaskVT, Op.getOperand(1),
16487 SDValue CmpMask = getVectorMaskingNode(Cmp, Mask,
16488 DAG.getTargetConstant(0, dl,
16491 SDValue Res = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, BitcastVT,
16492 DAG.getUNDEF(BitcastVT), CmpMask,
16493 DAG.getIntPtrConstant(0, dl));
16494 return DAG.getBitcast(Op.getValueType(), Res);
16496 case CMP_MASK_SCALAR_CC: {
16497 SDValue Src1 = Op.getOperand(1);
16498 SDValue Src2 = Op.getOperand(2);
16499 SDValue CC = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op.getOperand(3));
16500 SDValue Mask = Op.getOperand(4);
16503 if (IntrData->Opc1 != 0) {
16504 SDValue Rnd = Op.getOperand(5);
16505 if (cast<ConstantSDNode>(Rnd)->getZExtValue() !=
16506 X86::STATIC_ROUNDING::CUR_DIRECTION)
16507 Cmp = DAG.getNode(IntrData->Opc1, dl, MVT::i1, Src1, Src2, CC, Rnd);
16509 //default rounding mode
16511 Cmp = DAG.getNode(IntrData->Opc0, dl, MVT::i1, Src1, Src2, CC);
16513 SDValue CmpMask = getScalarMaskingNode(Cmp, Mask,
16514 DAG.getTargetConstant(0, dl,
16518 return DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, MVT::i8,
16519 DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i8, CmpMask),
16520 DAG.getValueType(MVT::i1));
16522 case COMI: { // Comparison intrinsics
16523 ISD::CondCode CC = (ISD::CondCode)IntrData->Opc1;
16524 SDValue LHS = Op.getOperand(1);
16525 SDValue RHS = Op.getOperand(2);
16526 unsigned X86CC = TranslateX86CC(CC, dl, true, LHS, RHS, DAG);
16527 assert(X86CC != X86::COND_INVALID && "Unexpected illegal condition!");
16528 SDValue Cond = DAG.getNode(IntrData->Opc0, dl, MVT::i32, LHS, RHS);
16529 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
16530 DAG.getConstant(X86CC, dl, MVT::i8), Cond);
16531 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
16534 return getTargetVShiftNode(IntrData->Opc0, dl, Op.getSimpleValueType(),
16535 Op.getOperand(1), Op.getOperand(2), DAG);
16537 return getVectorMaskingNode(getTargetVShiftNode(IntrData->Opc0, dl,
16538 Op.getSimpleValueType(),
16540 Op.getOperand(2), DAG),
16541 Op.getOperand(4), Op.getOperand(3), Subtarget,
16543 case COMPRESS_EXPAND_IN_REG: {
16544 SDValue Mask = Op.getOperand(3);
16545 SDValue DataToCompress = Op.getOperand(1);
16546 SDValue PassThru = Op.getOperand(2);
16547 if (isAllOnesConstant(Mask)) // return data as is
16548 return Op.getOperand(1);
16550 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT,
16552 Mask, PassThru, Subtarget, DAG);
16555 SDValue Mask = Op.getOperand(1);
16556 MVT MaskVT = MVT::getVectorVT(MVT::i1, Mask.getSimpleValueType().getSizeInBits());
16557 Mask = DAG.getBitcast(MaskVT, Mask);
16558 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Mask);
16561 SDValue Mask = Op.getOperand(3);
16562 MVT VT = Op.getSimpleValueType();
16563 MVT MaskVT = MVT::getVectorVT(MVT::i1, VT.getVectorNumElements());
16564 MVT BitcastVT = MVT::getVectorVT(MVT::i1,
16565 Mask.getSimpleValueType().getSizeInBits());
16567 SDValue VMask = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MaskVT,
16568 DAG.getBitcast(BitcastVT, Mask),
16569 DAG.getIntPtrConstant(0, dl));
16570 return DAG.getNode(IntrData->Opc0, dl, VT, VMask, Op.getOperand(1),
16579 default: return SDValue(); // Don't custom lower most intrinsics.
16581 case Intrinsic::x86_avx2_permd:
16582 case Intrinsic::x86_avx2_permps:
16583 // Operands intentionally swapped. Mask is last operand to intrinsic,
16584 // but second operand for node/instruction.
16585 return DAG.getNode(X86ISD::VPERMV, dl, Op.getValueType(),
16586 Op.getOperand(2), Op.getOperand(1));
16588 // ptest and testp intrinsics. The intrinsic these come from are designed to
16589 // return an integer value, not just an instruction so lower it to the ptest
16590 // or testp pattern and a setcc for the result.
16591 case Intrinsic::x86_sse41_ptestz:
16592 case Intrinsic::x86_sse41_ptestc:
16593 case Intrinsic::x86_sse41_ptestnzc:
16594 case Intrinsic::x86_avx_ptestz_256:
16595 case Intrinsic::x86_avx_ptestc_256:
16596 case Intrinsic::x86_avx_ptestnzc_256:
16597 case Intrinsic::x86_avx_vtestz_ps:
16598 case Intrinsic::x86_avx_vtestc_ps:
16599 case Intrinsic::x86_avx_vtestnzc_ps:
16600 case Intrinsic::x86_avx_vtestz_pd:
16601 case Intrinsic::x86_avx_vtestc_pd:
16602 case Intrinsic::x86_avx_vtestnzc_pd:
16603 case Intrinsic::x86_avx_vtestz_ps_256:
16604 case Intrinsic::x86_avx_vtestc_ps_256:
16605 case Intrinsic::x86_avx_vtestnzc_ps_256:
16606 case Intrinsic::x86_avx_vtestz_pd_256:
16607 case Intrinsic::x86_avx_vtestc_pd_256:
16608 case Intrinsic::x86_avx_vtestnzc_pd_256: {
16609 bool IsTestPacked = false;
16612 default: llvm_unreachable("Bad fallthrough in Intrinsic lowering.");
16613 case Intrinsic::x86_avx_vtestz_ps:
16614 case Intrinsic::x86_avx_vtestz_pd:
16615 case Intrinsic::x86_avx_vtestz_ps_256:
16616 case Intrinsic::x86_avx_vtestz_pd_256:
16617 IsTestPacked = true; // Fallthrough
16618 case Intrinsic::x86_sse41_ptestz:
16619 case Intrinsic::x86_avx_ptestz_256:
16621 X86CC = X86::COND_E;
16623 case Intrinsic::x86_avx_vtestc_ps:
16624 case Intrinsic::x86_avx_vtestc_pd:
16625 case Intrinsic::x86_avx_vtestc_ps_256:
16626 case Intrinsic::x86_avx_vtestc_pd_256:
16627 IsTestPacked = true; // Fallthrough
16628 case Intrinsic::x86_sse41_ptestc:
16629 case Intrinsic::x86_avx_ptestc_256:
16631 X86CC = X86::COND_B;
16633 case Intrinsic::x86_avx_vtestnzc_ps:
16634 case Intrinsic::x86_avx_vtestnzc_pd:
16635 case Intrinsic::x86_avx_vtestnzc_ps_256:
16636 case Intrinsic::x86_avx_vtestnzc_pd_256:
16637 IsTestPacked = true; // Fallthrough
16638 case Intrinsic::x86_sse41_ptestnzc:
16639 case Intrinsic::x86_avx_ptestnzc_256:
16641 X86CC = X86::COND_A;
16645 SDValue LHS = Op.getOperand(1);
16646 SDValue RHS = Op.getOperand(2);
16647 unsigned TestOpc = IsTestPacked ? X86ISD::TESTP : X86ISD::PTEST;
16648 SDValue Test = DAG.getNode(TestOpc, dl, MVT::i32, LHS, RHS);
16649 SDValue CC = DAG.getConstant(X86CC, dl, MVT::i8);
16650 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8, CC, Test);
16651 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
16653 case Intrinsic::x86_avx512_kortestz_w:
16654 case Intrinsic::x86_avx512_kortestc_w: {
16655 unsigned X86CC = (IntNo == Intrinsic::x86_avx512_kortestz_w)? X86::COND_E: X86::COND_B;
16656 SDValue LHS = DAG.getBitcast(MVT::v16i1, Op.getOperand(1));
16657 SDValue RHS = DAG.getBitcast(MVT::v16i1, Op.getOperand(2));
16658 SDValue CC = DAG.getConstant(X86CC, dl, MVT::i8);
16659 SDValue Test = DAG.getNode(X86ISD::KORTEST, dl, MVT::i32, LHS, RHS);
16660 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i1, CC, Test);
16661 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
16664 case Intrinsic::x86_sse42_pcmpistria128:
16665 case Intrinsic::x86_sse42_pcmpestria128:
16666 case Intrinsic::x86_sse42_pcmpistric128:
16667 case Intrinsic::x86_sse42_pcmpestric128:
16668 case Intrinsic::x86_sse42_pcmpistrio128:
16669 case Intrinsic::x86_sse42_pcmpestrio128:
16670 case Intrinsic::x86_sse42_pcmpistris128:
16671 case Intrinsic::x86_sse42_pcmpestris128:
16672 case Intrinsic::x86_sse42_pcmpistriz128:
16673 case Intrinsic::x86_sse42_pcmpestriz128: {
16677 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
16678 case Intrinsic::x86_sse42_pcmpistria128:
16679 Opcode = X86ISD::PCMPISTRI;
16680 X86CC = X86::COND_A;
16682 case Intrinsic::x86_sse42_pcmpestria128:
16683 Opcode = X86ISD::PCMPESTRI;
16684 X86CC = X86::COND_A;
16686 case Intrinsic::x86_sse42_pcmpistric128:
16687 Opcode = X86ISD::PCMPISTRI;
16688 X86CC = X86::COND_B;
16690 case Intrinsic::x86_sse42_pcmpestric128:
16691 Opcode = X86ISD::PCMPESTRI;
16692 X86CC = X86::COND_B;
16694 case Intrinsic::x86_sse42_pcmpistrio128:
16695 Opcode = X86ISD::PCMPISTRI;
16696 X86CC = X86::COND_O;
16698 case Intrinsic::x86_sse42_pcmpestrio128:
16699 Opcode = X86ISD::PCMPESTRI;
16700 X86CC = X86::COND_O;
16702 case Intrinsic::x86_sse42_pcmpistris128:
16703 Opcode = X86ISD::PCMPISTRI;
16704 X86CC = X86::COND_S;
16706 case Intrinsic::x86_sse42_pcmpestris128:
16707 Opcode = X86ISD::PCMPESTRI;
16708 X86CC = X86::COND_S;
16710 case Intrinsic::x86_sse42_pcmpistriz128:
16711 Opcode = X86ISD::PCMPISTRI;
16712 X86CC = X86::COND_E;
16714 case Intrinsic::x86_sse42_pcmpestriz128:
16715 Opcode = X86ISD::PCMPESTRI;
16716 X86CC = X86::COND_E;
16719 SmallVector<SDValue, 5> NewOps(Op->op_begin()+1, Op->op_end());
16720 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
16721 SDValue PCMP = DAG.getNode(Opcode, dl, VTs, NewOps);
16722 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
16723 DAG.getConstant(X86CC, dl, MVT::i8),
16724 SDValue(PCMP.getNode(), 1));
16725 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
16728 case Intrinsic::x86_sse42_pcmpistri128:
16729 case Intrinsic::x86_sse42_pcmpestri128: {
16731 if (IntNo == Intrinsic::x86_sse42_pcmpistri128)
16732 Opcode = X86ISD::PCMPISTRI;
16734 Opcode = X86ISD::PCMPESTRI;
16736 SmallVector<SDValue, 5> NewOps(Op->op_begin()+1, Op->op_end());
16737 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
16738 return DAG.getNode(Opcode, dl, VTs, NewOps);
16741 case Intrinsic::x86_seh_lsda: {
16742 // Compute the symbol for the LSDA. We know it'll get emitted later.
16743 MachineFunction &MF = DAG.getMachineFunction();
16744 SDValue Op1 = Op.getOperand(1);
16745 auto *Fn = cast<Function>(cast<GlobalAddressSDNode>(Op1)->getGlobal());
16746 MCSymbol *LSDASym = MF.getMMI().getContext().getOrCreateLSDASymbol(
16747 GlobalValue::getRealLinkageName(Fn->getName()));
16749 // Generate a simple absolute symbol reference. This intrinsic is only
16750 // supported on 32-bit Windows, which isn't PIC.
16751 SDValue Result = DAG.getMCSymbol(LSDASym, VT);
16752 return DAG.getNode(X86ISD::Wrapper, dl, VT, Result);
16755 case Intrinsic::x86_seh_recoverfp: {
16756 SDValue FnOp = Op.getOperand(1);
16757 SDValue IncomingFPOp = Op.getOperand(2);
16758 GlobalAddressSDNode *GSD = dyn_cast<GlobalAddressSDNode>(FnOp);
16759 auto *Fn = dyn_cast_or_null<Function>(GSD ? GSD->getGlobal() : nullptr);
16761 report_fatal_error(
16762 "llvm.x86.seh.recoverfp must take a function as the first argument");
16763 return recoverFramePointer(DAG, Fn, IncomingFPOp);
16766 case Intrinsic::localaddress: {
16767 // Returns one of the stack, base, or frame pointer registers, depending on
16768 // which is used to reference local variables.
16769 MachineFunction &MF = DAG.getMachineFunction();
16770 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
16772 if (RegInfo->hasBasePointer(MF))
16773 Reg = RegInfo->getBaseRegister();
16774 else // This function handles the SP or FP case.
16775 Reg = RegInfo->getPtrSizedFrameRegister(MF);
16776 return DAG.getCopyFromReg(DAG.getEntryNode(), dl, Reg, VT);
16781 static SDValue getGatherNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
16782 SDValue Src, SDValue Mask, SDValue Base,
16783 SDValue Index, SDValue ScaleOp, SDValue Chain,
16784 const X86Subtarget * Subtarget) {
16786 auto *C = cast<ConstantSDNode>(ScaleOp);
16787 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), dl, MVT::i8);
16788 MVT MaskVT = MVT::getVectorVT(MVT::i1,
16789 Index.getSimpleValueType().getVectorNumElements());
16791 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(Mask);
16793 MaskInReg = DAG.getTargetConstant(MaskC->getSExtValue(), dl, MaskVT);
16795 MVT BitcastVT = MVT::getVectorVT(MVT::i1,
16796 Mask.getSimpleValueType().getSizeInBits());
16798 // In case when MaskVT equals v2i1 or v4i1, low 2 or 4 elements
16799 // are extracted by EXTRACT_SUBVECTOR.
16800 MaskInReg = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MaskVT,
16801 DAG.getBitcast(BitcastVT, Mask),
16802 DAG.getIntPtrConstant(0, dl));
16804 SDVTList VTs = DAG.getVTList(Op.getValueType(), MaskVT, MVT::Other);
16805 SDValue Disp = DAG.getTargetConstant(0, dl, MVT::i32);
16806 SDValue Segment = DAG.getRegister(0, MVT::i32);
16807 if (Src.getOpcode() == ISD::UNDEF)
16808 Src = getZeroVector(Op.getValueType(), Subtarget, DAG, dl);
16809 SDValue Ops[] = {Src, MaskInReg, Base, Scale, Index, Disp, Segment, Chain};
16810 SDNode *Res = DAG.getMachineNode(Opc, dl, VTs, Ops);
16811 SDValue RetOps[] = { SDValue(Res, 0), SDValue(Res, 2) };
16812 return DAG.getMergeValues(RetOps, dl);
16815 static SDValue getScatterNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
16816 SDValue Src, SDValue Mask, SDValue Base,
16817 SDValue Index, SDValue ScaleOp, SDValue Chain) {
16819 auto *C = cast<ConstantSDNode>(ScaleOp);
16820 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), dl, MVT::i8);
16821 SDValue Disp = DAG.getTargetConstant(0, dl, MVT::i32);
16822 SDValue Segment = DAG.getRegister(0, MVT::i32);
16823 MVT MaskVT = MVT::getVectorVT(MVT::i1,
16824 Index.getSimpleValueType().getVectorNumElements());
16826 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(Mask);
16828 MaskInReg = DAG.getTargetConstant(MaskC->getSExtValue(), dl, MaskVT);
16830 MVT BitcastVT = MVT::getVectorVT(MVT::i1,
16831 Mask.getSimpleValueType().getSizeInBits());
16833 // In case when MaskVT equals v2i1 or v4i1, low 2 or 4 elements
16834 // are extracted by EXTRACT_SUBVECTOR.
16835 MaskInReg = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MaskVT,
16836 DAG.getBitcast(BitcastVT, Mask),
16837 DAG.getIntPtrConstant(0, dl));
16839 SDVTList VTs = DAG.getVTList(MaskVT, MVT::Other);
16840 SDValue Ops[] = {Base, Scale, Index, Disp, Segment, MaskInReg, Src, Chain};
16841 SDNode *Res = DAG.getMachineNode(Opc, dl, VTs, Ops);
16842 return SDValue(Res, 1);
16845 static SDValue getPrefetchNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
16846 SDValue Mask, SDValue Base, SDValue Index,
16847 SDValue ScaleOp, SDValue Chain) {
16849 auto *C = cast<ConstantSDNode>(ScaleOp);
16850 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), dl, MVT::i8);
16851 SDValue Disp = DAG.getTargetConstant(0, dl, MVT::i32);
16852 SDValue Segment = DAG.getRegister(0, MVT::i32);
16854 MVT::getVectorVT(MVT::i1, Index.getSimpleValueType().getVectorNumElements());
16856 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(Mask);
16858 MaskInReg = DAG.getTargetConstant(MaskC->getSExtValue(), dl, MaskVT);
16860 MaskInReg = DAG.getBitcast(MaskVT, Mask);
16861 //SDVTList VTs = DAG.getVTList(MVT::Other);
16862 SDValue Ops[] = {MaskInReg, Base, Scale, Index, Disp, Segment, Chain};
16863 SDNode *Res = DAG.getMachineNode(Opc, dl, MVT::Other, Ops);
16864 return SDValue(Res, 0);
16867 // getReadPerformanceCounter - Handles the lowering of builtin intrinsics that
16868 // read performance monitor counters (x86_rdpmc).
16869 static void getReadPerformanceCounter(SDNode *N, SDLoc DL,
16870 SelectionDAG &DAG, const X86Subtarget *Subtarget,
16871 SmallVectorImpl<SDValue> &Results) {
16872 assert(N->getNumOperands() == 3 && "Unexpected number of operands!");
16873 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
16876 // The ECX register is used to select the index of the performance counter
16878 SDValue Chain = DAG.getCopyToReg(N->getOperand(0), DL, X86::ECX,
16880 SDValue rd = DAG.getNode(X86ISD::RDPMC_DAG, DL, Tys, Chain);
16882 // Reads the content of a 64-bit performance counter and returns it in the
16883 // registers EDX:EAX.
16884 if (Subtarget->is64Bit()) {
16885 LO = DAG.getCopyFromReg(rd, DL, X86::RAX, MVT::i64, rd.getValue(1));
16886 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::RDX, MVT::i64,
16889 LO = DAG.getCopyFromReg(rd, DL, X86::EAX, MVT::i32, rd.getValue(1));
16890 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::EDX, MVT::i32,
16893 Chain = HI.getValue(1);
16895 if (Subtarget->is64Bit()) {
16896 // The EAX register is loaded with the low-order 32 bits. The EDX register
16897 // is loaded with the supported high-order bits of the counter.
16898 SDValue Tmp = DAG.getNode(ISD::SHL, DL, MVT::i64, HI,
16899 DAG.getConstant(32, DL, MVT::i8));
16900 Results.push_back(DAG.getNode(ISD::OR, DL, MVT::i64, LO, Tmp));
16901 Results.push_back(Chain);
16905 // Use a buildpair to merge the two 32-bit values into a 64-bit one.
16906 SDValue Ops[] = { LO, HI };
16907 SDValue Pair = DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops);
16908 Results.push_back(Pair);
16909 Results.push_back(Chain);
16912 // getReadTimeStampCounter - Handles the lowering of builtin intrinsics that
16913 // read the time stamp counter (x86_rdtsc and x86_rdtscp). This function is
16914 // also used to custom lower READCYCLECOUNTER nodes.
16915 static void getReadTimeStampCounter(SDNode *N, SDLoc DL, unsigned Opcode,
16916 SelectionDAG &DAG, const X86Subtarget *Subtarget,
16917 SmallVectorImpl<SDValue> &Results) {
16918 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
16919 SDValue rd = DAG.getNode(Opcode, DL, Tys, N->getOperand(0));
16922 // The processor's time-stamp counter (a 64-bit MSR) is stored into the
16923 // EDX:EAX registers. EDX is loaded with the high-order 32 bits of the MSR
16924 // and the EAX register is loaded with the low-order 32 bits.
16925 if (Subtarget->is64Bit()) {
16926 LO = DAG.getCopyFromReg(rd, DL, X86::RAX, MVT::i64, rd.getValue(1));
16927 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::RDX, MVT::i64,
16930 LO = DAG.getCopyFromReg(rd, DL, X86::EAX, MVT::i32, rd.getValue(1));
16931 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::EDX, MVT::i32,
16934 SDValue Chain = HI.getValue(1);
16936 if (Opcode == X86ISD::RDTSCP_DAG) {
16937 assert(N->getNumOperands() == 3 && "Unexpected number of operands!");
16939 // Instruction RDTSCP loads the IA32:TSC_AUX_MSR (address C000_0103H) into
16940 // the ECX register. Add 'ecx' explicitly to the chain.
16941 SDValue ecx = DAG.getCopyFromReg(Chain, DL, X86::ECX, MVT::i32,
16943 // Explicitly store the content of ECX at the location passed in input
16944 // to the 'rdtscp' intrinsic.
16945 Chain = DAG.getStore(ecx.getValue(1), DL, ecx, N->getOperand(2),
16946 MachinePointerInfo(), false, false, 0);
16949 if (Subtarget->is64Bit()) {
16950 // The EDX register is loaded with the high-order 32 bits of the MSR, and
16951 // the EAX register is loaded with the low-order 32 bits.
16952 SDValue Tmp = DAG.getNode(ISD::SHL, DL, MVT::i64, HI,
16953 DAG.getConstant(32, DL, MVT::i8));
16954 Results.push_back(DAG.getNode(ISD::OR, DL, MVT::i64, LO, Tmp));
16955 Results.push_back(Chain);
16959 // Use a buildpair to merge the two 32-bit values into a 64-bit one.
16960 SDValue Ops[] = { LO, HI };
16961 SDValue Pair = DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops);
16962 Results.push_back(Pair);
16963 Results.push_back(Chain);
16966 static SDValue LowerREADCYCLECOUNTER(SDValue Op, const X86Subtarget *Subtarget,
16967 SelectionDAG &DAG) {
16968 SmallVector<SDValue, 2> Results;
16970 getReadTimeStampCounter(Op.getNode(), DL, X86ISD::RDTSC_DAG, DAG, Subtarget,
16972 return DAG.getMergeValues(Results, DL);
16975 static SDValue LowerSEHRESTOREFRAME(SDValue Op, const X86Subtarget *Subtarget,
16976 SelectionDAG &DAG) {
16977 MachineFunction &MF = DAG.getMachineFunction();
16978 const Function *Fn = MF.getFunction();
16980 SDValue Chain = Op.getOperand(0);
16982 assert(Subtarget->getFrameLowering()->hasFP(MF) &&
16983 "using llvm.x86.seh.restoreframe requires a frame pointer");
16985 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
16986 MVT VT = TLI.getPointerTy(DAG.getDataLayout());
16988 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
16989 unsigned FrameReg =
16990 RegInfo->getPtrSizedFrameRegister(DAG.getMachineFunction());
16991 unsigned SPReg = RegInfo->getStackRegister();
16992 unsigned SlotSize = RegInfo->getSlotSize();
16994 // Get incoming EBP.
16995 SDValue IncomingEBP =
16996 DAG.getCopyFromReg(Chain, dl, FrameReg, VT);
16998 // SP is saved in the first field of every registration node, so load
16999 // [EBP-RegNodeSize] into SP.
17000 int RegNodeSize = getSEHRegistrationNodeSize(Fn);
17001 SDValue SPAddr = DAG.getNode(ISD::ADD, dl, VT, IncomingEBP,
17002 DAG.getConstant(-RegNodeSize, dl, VT));
17004 DAG.getLoad(VT, dl, Chain, SPAddr, MachinePointerInfo(), false, false,
17005 false, VT.getScalarSizeInBits() / 8);
17006 Chain = DAG.getCopyToReg(Chain, dl, SPReg, NewSP);
17008 if (!RegInfo->needsStackRealignment(MF)) {
17009 // Adjust EBP to point back to the original frame position.
17010 SDValue NewFP = recoverFramePointer(DAG, Fn, IncomingEBP);
17011 Chain = DAG.getCopyToReg(Chain, dl, FrameReg, NewFP);
17013 assert(RegInfo->hasBasePointer(MF) &&
17014 "functions with Win32 EH must use frame or base pointer register");
17016 // Reload the base pointer (ESI) with the adjusted incoming EBP.
17017 SDValue NewBP = recoverFramePointer(DAG, Fn, IncomingEBP);
17018 Chain = DAG.getCopyToReg(Chain, dl, RegInfo->getBaseRegister(), NewBP);
17020 // Reload the spilled EBP value, now that the stack and base pointers are
17022 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
17023 X86FI->setHasSEHFramePtrSave(true);
17024 int FI = MF.getFrameInfo()->CreateSpillStackObject(SlotSize, SlotSize);
17025 X86FI->setSEHFramePtrSaveIndex(FI);
17026 SDValue NewFP = DAG.getLoad(VT, dl, Chain, DAG.getFrameIndex(FI, VT),
17027 MachinePointerInfo(), false, false, false,
17028 VT.getScalarSizeInBits() / 8);
17029 Chain = DAG.getCopyToReg(NewFP, dl, FrameReg, NewFP);
17035 static SDValue MarkEHRegistrationNode(SDValue Op, SelectionDAG &DAG) {
17036 MachineFunction &MF = DAG.getMachineFunction();
17037 SDValue Chain = Op.getOperand(0);
17038 SDValue RegNode = Op.getOperand(2);
17039 WinEHFuncInfo *EHInfo = MF.getWinEHFuncInfo();
17041 report_fatal_error("EH registrations only live in functions using WinEH");
17043 // Cast the operand to an alloca, and remember the frame index.
17044 auto *FINode = dyn_cast<FrameIndexSDNode>(RegNode);
17046 report_fatal_error("llvm.x86.seh.ehregnode expects a static alloca");
17047 EHInfo->EHRegNodeFrameIndex = FINode->getIndex();
17049 // Return the chain operand without making any DAG nodes.
17053 /// \brief Lower intrinsics for TRUNCATE_TO_MEM case
17054 /// return truncate Store/MaskedStore Node
17055 static SDValue LowerINTRINSIC_TRUNCATE_TO_MEM(const SDValue & Op,
17059 SDValue Mask = Op.getOperand(4);
17060 SDValue DataToTruncate = Op.getOperand(3);
17061 SDValue Addr = Op.getOperand(2);
17062 SDValue Chain = Op.getOperand(0);
17064 MVT VT = DataToTruncate.getSimpleValueType();
17065 MVT SVT = MVT::getVectorVT(ElementType, VT.getVectorNumElements());
17067 if (isAllOnesConstant(Mask)) // return just a truncate store
17068 return DAG.getTruncStore(Chain, dl, DataToTruncate, Addr,
17069 MachinePointerInfo(), SVT, false, false,
17070 SVT.getScalarSizeInBits()/8);
17072 MVT MaskVT = MVT::getVectorVT(MVT::i1, VT.getVectorNumElements());
17073 MVT BitcastVT = MVT::getVectorVT(MVT::i1,
17074 Mask.getSimpleValueType().getSizeInBits());
17075 // In case when MaskVT equals v2i1 or v4i1, low 2 or 4 elements
17076 // are extracted by EXTRACT_SUBVECTOR.
17077 SDValue VMask = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MaskVT,
17078 DAG.getBitcast(BitcastVT, Mask),
17079 DAG.getIntPtrConstant(0, dl));
17081 MachineMemOperand *MMO = DAG.getMachineFunction().
17082 getMachineMemOperand(MachinePointerInfo(),
17083 MachineMemOperand::MOStore, SVT.getStoreSize(),
17084 SVT.getScalarSizeInBits()/8);
17086 return DAG.getMaskedStore(Chain, dl, DataToTruncate, Addr,
17087 VMask, SVT, MMO, true);
17090 static SDValue LowerINTRINSIC_W_CHAIN(SDValue Op, const X86Subtarget *Subtarget,
17091 SelectionDAG &DAG) {
17092 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
17094 const IntrinsicData* IntrData = getIntrinsicWithChain(IntNo);
17096 if (IntNo == llvm::Intrinsic::x86_seh_restoreframe)
17097 return LowerSEHRESTOREFRAME(Op, Subtarget, DAG);
17098 else if (IntNo == llvm::Intrinsic::x86_seh_ehregnode)
17099 return MarkEHRegistrationNode(Op, DAG);
17104 switch(IntrData->Type) {
17105 default: llvm_unreachable("Unknown Intrinsic Type");
17108 // Emit the node with the right value type.
17109 SDVTList VTs = DAG.getVTList(Op->getValueType(0), MVT::Glue, MVT::Other);
17110 SDValue Result = DAG.getNode(IntrData->Opc0, dl, VTs, Op.getOperand(0));
17112 // If the value returned by RDRAND/RDSEED was valid (CF=1), return 1.
17113 // Otherwise return the value from Rand, which is always 0, casted to i32.
17114 SDValue Ops[] = { DAG.getZExtOrTrunc(Result, dl, Op->getValueType(1)),
17115 DAG.getConstant(1, dl, Op->getValueType(1)),
17116 DAG.getConstant(X86::COND_B, dl, MVT::i32),
17117 SDValue(Result.getNode(), 1) };
17118 SDValue isValid = DAG.getNode(X86ISD::CMOV, dl,
17119 DAG.getVTList(Op->getValueType(1), MVT::Glue),
17122 // Return { result, isValid, chain }.
17123 return DAG.getNode(ISD::MERGE_VALUES, dl, Op->getVTList(), Result, isValid,
17124 SDValue(Result.getNode(), 2));
17127 //gather(v1, mask, index, base, scale);
17128 SDValue Chain = Op.getOperand(0);
17129 SDValue Src = Op.getOperand(2);
17130 SDValue Base = Op.getOperand(3);
17131 SDValue Index = Op.getOperand(4);
17132 SDValue Mask = Op.getOperand(5);
17133 SDValue Scale = Op.getOperand(6);
17134 return getGatherNode(IntrData->Opc0, Op, DAG, Src, Mask, Base, Index, Scale,
17138 //scatter(base, mask, index, v1, scale);
17139 SDValue Chain = Op.getOperand(0);
17140 SDValue Base = Op.getOperand(2);
17141 SDValue Mask = Op.getOperand(3);
17142 SDValue Index = Op.getOperand(4);
17143 SDValue Src = Op.getOperand(5);
17144 SDValue Scale = Op.getOperand(6);
17145 return getScatterNode(IntrData->Opc0, Op, DAG, Src, Mask, Base, Index,
17149 SDValue Hint = Op.getOperand(6);
17150 unsigned HintVal = cast<ConstantSDNode>(Hint)->getZExtValue();
17151 assert(HintVal < 2 && "Wrong prefetch hint in intrinsic: should be 0 or 1");
17152 unsigned Opcode = (HintVal ? IntrData->Opc1 : IntrData->Opc0);
17153 SDValue Chain = Op.getOperand(0);
17154 SDValue Mask = Op.getOperand(2);
17155 SDValue Index = Op.getOperand(3);
17156 SDValue Base = Op.getOperand(4);
17157 SDValue Scale = Op.getOperand(5);
17158 return getPrefetchNode(Opcode, Op, DAG, Mask, Base, Index, Scale, Chain);
17160 // Read Time Stamp Counter (RDTSC) and Processor ID (RDTSCP).
17162 SmallVector<SDValue, 2> Results;
17163 getReadTimeStampCounter(Op.getNode(), dl, IntrData->Opc0, DAG, Subtarget,
17165 return DAG.getMergeValues(Results, dl);
17167 // Read Performance Monitoring Counters.
17169 SmallVector<SDValue, 2> Results;
17170 getReadPerformanceCounter(Op.getNode(), dl, DAG, Subtarget, Results);
17171 return DAG.getMergeValues(Results, dl);
17173 // XTEST intrinsics.
17175 SDVTList VTs = DAG.getVTList(Op->getValueType(0), MVT::Other);
17176 SDValue InTrans = DAG.getNode(IntrData->Opc0, dl, VTs, Op.getOperand(0));
17177 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
17178 DAG.getConstant(X86::COND_NE, dl, MVT::i8),
17180 SDValue Ret = DAG.getNode(ISD::ZERO_EXTEND, dl, Op->getValueType(0), SetCC);
17181 return DAG.getNode(ISD::MERGE_VALUES, dl, Op->getVTList(),
17182 Ret, SDValue(InTrans.getNode(), 1));
17186 SmallVector<SDValue, 2> Results;
17187 SDVTList CFVTs = DAG.getVTList(Op->getValueType(0), MVT::Other);
17188 SDVTList VTs = DAG.getVTList(Op.getOperand(3)->getValueType(0), MVT::Other);
17189 SDValue GenCF = DAG.getNode(X86ISD::ADD, dl, CFVTs, Op.getOperand(2),
17190 DAG.getConstant(-1, dl, MVT::i8));
17191 SDValue Res = DAG.getNode(IntrData->Opc0, dl, VTs, Op.getOperand(3),
17192 Op.getOperand(4), GenCF.getValue(1));
17193 SDValue Store = DAG.getStore(Op.getOperand(0), dl, Res.getValue(0),
17194 Op.getOperand(5), MachinePointerInfo(),
17196 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
17197 DAG.getConstant(X86::COND_B, dl, MVT::i8),
17199 Results.push_back(SetCC);
17200 Results.push_back(Store);
17201 return DAG.getMergeValues(Results, dl);
17203 case COMPRESS_TO_MEM: {
17205 SDValue Mask = Op.getOperand(4);
17206 SDValue DataToCompress = Op.getOperand(3);
17207 SDValue Addr = Op.getOperand(2);
17208 SDValue Chain = Op.getOperand(0);
17210 MVT VT = DataToCompress.getSimpleValueType();
17211 if (isAllOnesConstant(Mask)) // return just a store
17212 return DAG.getStore(Chain, dl, DataToCompress, Addr,
17213 MachinePointerInfo(), false, false,
17214 VT.getScalarSizeInBits()/8);
17216 SDValue Compressed =
17217 getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT, DataToCompress),
17218 Mask, DAG.getUNDEF(VT), Subtarget, DAG);
17219 return DAG.getStore(Chain, dl, Compressed, Addr,
17220 MachinePointerInfo(), false, false,
17221 VT.getScalarSizeInBits()/8);
17223 case TRUNCATE_TO_MEM_VI8:
17224 return LowerINTRINSIC_TRUNCATE_TO_MEM(Op, DAG, MVT::i8);
17225 case TRUNCATE_TO_MEM_VI16:
17226 return LowerINTRINSIC_TRUNCATE_TO_MEM(Op, DAG, MVT::i16);
17227 case TRUNCATE_TO_MEM_VI32:
17228 return LowerINTRINSIC_TRUNCATE_TO_MEM(Op, DAG, MVT::i32);
17229 case EXPAND_FROM_MEM: {
17231 SDValue Mask = Op.getOperand(4);
17232 SDValue PassThru = Op.getOperand(3);
17233 SDValue Addr = Op.getOperand(2);
17234 SDValue Chain = Op.getOperand(0);
17235 MVT VT = Op.getSimpleValueType();
17237 if (isAllOnesConstant(Mask)) // return just a load
17238 return DAG.getLoad(VT, dl, Chain, Addr, MachinePointerInfo(), false, false,
17239 false, VT.getScalarSizeInBits()/8);
17241 SDValue DataToExpand = DAG.getLoad(VT, dl, Chain, Addr, MachinePointerInfo(),
17242 false, false, false,
17243 VT.getScalarSizeInBits()/8);
17245 SDValue Results[] = {
17246 getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT, DataToExpand),
17247 Mask, PassThru, Subtarget, DAG), Chain};
17248 return DAG.getMergeValues(Results, dl);
17253 SDValue X86TargetLowering::LowerRETURNADDR(SDValue Op,
17254 SelectionDAG &DAG) const {
17255 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
17256 MFI->setReturnAddressIsTaken(true);
17258 if (verifyReturnAddressArgumentIsConstant(Op, DAG))
17261 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
17263 EVT PtrVT = getPointerTy(DAG.getDataLayout());
17266 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
17267 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
17268 SDValue Offset = DAG.getConstant(RegInfo->getSlotSize(), dl, PtrVT);
17269 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
17270 DAG.getNode(ISD::ADD, dl, PtrVT,
17271 FrameAddr, Offset),
17272 MachinePointerInfo(), false, false, false, 0);
17275 // Just load the return address.
17276 SDValue RetAddrFI = getReturnAddressFrameIndex(DAG);
17277 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
17278 RetAddrFI, MachinePointerInfo(), false, false, false, 0);
17281 SDValue X86TargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {
17282 MachineFunction &MF = DAG.getMachineFunction();
17283 MachineFrameInfo *MFI = MF.getFrameInfo();
17284 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
17285 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
17286 EVT VT = Op.getValueType();
17288 MFI->setFrameAddressIsTaken(true);
17290 if (MF.getTarget().getMCAsmInfo()->usesWindowsCFI()) {
17291 // Depth > 0 makes no sense on targets which use Windows unwind codes. It
17292 // is not possible to crawl up the stack without looking at the unwind codes
17294 int FrameAddrIndex = FuncInfo->getFAIndex();
17295 if (!FrameAddrIndex) {
17296 // Set up a frame object for the return address.
17297 unsigned SlotSize = RegInfo->getSlotSize();
17298 FrameAddrIndex = MF.getFrameInfo()->CreateFixedObject(
17299 SlotSize, /*Offset=*/0, /*IsImmutable=*/false);
17300 FuncInfo->setFAIndex(FrameAddrIndex);
17302 return DAG.getFrameIndex(FrameAddrIndex, VT);
17305 unsigned FrameReg =
17306 RegInfo->getPtrSizedFrameRegister(DAG.getMachineFunction());
17307 SDLoc dl(Op); // FIXME probably not meaningful
17308 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
17309 assert(((FrameReg == X86::RBP && VT == MVT::i64) ||
17310 (FrameReg == X86::EBP && VT == MVT::i32)) &&
17311 "Invalid Frame Register!");
17312 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT);
17314 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr,
17315 MachinePointerInfo(),
17316 false, false, false, 0);
17320 // FIXME? Maybe this could be a TableGen attribute on some registers and
17321 // this table could be generated automatically from RegInfo.
17322 unsigned X86TargetLowering::getRegisterByName(const char* RegName, EVT VT,
17323 SelectionDAG &DAG) const {
17324 const TargetFrameLowering &TFI = *Subtarget->getFrameLowering();
17325 const MachineFunction &MF = DAG.getMachineFunction();
17327 unsigned Reg = StringSwitch<unsigned>(RegName)
17328 .Case("esp", X86::ESP)
17329 .Case("rsp", X86::RSP)
17330 .Case("ebp", X86::EBP)
17331 .Case("rbp", X86::RBP)
17334 if (Reg == X86::EBP || Reg == X86::RBP) {
17335 if (!TFI.hasFP(MF))
17336 report_fatal_error("register " + StringRef(RegName) +
17337 " is allocatable: function has no frame pointer");
17340 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
17341 unsigned FrameReg =
17342 RegInfo->getPtrSizedFrameRegister(DAG.getMachineFunction());
17343 assert((FrameReg == X86::EBP || FrameReg == X86::RBP) &&
17344 "Invalid Frame Register!");
17352 report_fatal_error("Invalid register name global variable");
17355 SDValue X86TargetLowering::LowerFRAME_TO_ARGS_OFFSET(SDValue Op,
17356 SelectionDAG &DAG) const {
17357 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
17358 return DAG.getIntPtrConstant(2 * RegInfo->getSlotSize(), SDLoc(Op));
17361 unsigned X86TargetLowering::getExceptionPointerRegister(
17362 const Constant *PersonalityFn) const {
17363 if (classifyEHPersonality(PersonalityFn) == EHPersonality::CoreCLR)
17364 return Subtarget->isTarget64BitLP64() ? X86::RDX : X86::EDX;
17366 return Subtarget->isTarget64BitLP64() ? X86::RAX : X86::EAX;
17369 unsigned X86TargetLowering::getExceptionSelectorRegister(
17370 const Constant *PersonalityFn) const {
17371 // Funclet personalities don't use selectors (the runtime does the selection).
17372 assert(!isFuncletEHPersonality(classifyEHPersonality(PersonalityFn)));
17373 return Subtarget->isTarget64BitLP64() ? X86::RDX : X86::EDX;
17376 SDValue X86TargetLowering::LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const {
17377 SDValue Chain = Op.getOperand(0);
17378 SDValue Offset = Op.getOperand(1);
17379 SDValue Handler = Op.getOperand(2);
17382 EVT PtrVT = getPointerTy(DAG.getDataLayout());
17383 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
17384 unsigned FrameReg = RegInfo->getFrameRegister(DAG.getMachineFunction());
17385 assert(((FrameReg == X86::RBP && PtrVT == MVT::i64) ||
17386 (FrameReg == X86::EBP && PtrVT == MVT::i32)) &&
17387 "Invalid Frame Register!");
17388 SDValue Frame = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, PtrVT);
17389 unsigned StoreAddrReg = (PtrVT == MVT::i64) ? X86::RCX : X86::ECX;
17391 SDValue StoreAddr = DAG.getNode(ISD::ADD, dl, PtrVT, Frame,
17392 DAG.getIntPtrConstant(RegInfo->getSlotSize(),
17394 StoreAddr = DAG.getNode(ISD::ADD, dl, PtrVT, StoreAddr, Offset);
17395 Chain = DAG.getStore(Chain, dl, Handler, StoreAddr, MachinePointerInfo(),
17397 Chain = DAG.getCopyToReg(Chain, dl, StoreAddrReg, StoreAddr);
17399 return DAG.getNode(X86ISD::EH_RETURN, dl, MVT::Other, Chain,
17400 DAG.getRegister(StoreAddrReg, PtrVT));
17403 SDValue X86TargetLowering::lowerEH_SJLJ_SETJMP(SDValue Op,
17404 SelectionDAG &DAG) const {
17406 return DAG.getNode(X86ISD::EH_SJLJ_SETJMP, DL,
17407 DAG.getVTList(MVT::i32, MVT::Other),
17408 Op.getOperand(0), Op.getOperand(1));
17411 SDValue X86TargetLowering::lowerEH_SJLJ_LONGJMP(SDValue Op,
17412 SelectionDAG &DAG) const {
17414 return DAG.getNode(X86ISD::EH_SJLJ_LONGJMP, DL, MVT::Other,
17415 Op.getOperand(0), Op.getOperand(1));
17418 static SDValue LowerADJUST_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) {
17419 return Op.getOperand(0);
17422 SDValue X86TargetLowering::LowerINIT_TRAMPOLINE(SDValue Op,
17423 SelectionDAG &DAG) const {
17424 SDValue Root = Op.getOperand(0);
17425 SDValue Trmp = Op.getOperand(1); // trampoline
17426 SDValue FPtr = Op.getOperand(2); // nested function
17427 SDValue Nest = Op.getOperand(3); // 'nest' parameter value
17430 const Value *TrmpAddr = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
17431 const TargetRegisterInfo *TRI = Subtarget->getRegisterInfo();
17433 if (Subtarget->is64Bit()) {
17434 SDValue OutChains[6];
17436 // Large code-model.
17437 const unsigned char JMP64r = 0xFF; // 64-bit jmp through register opcode.
17438 const unsigned char MOV64ri = 0xB8; // X86::MOV64ri opcode.
17440 const unsigned char N86R10 = TRI->getEncodingValue(X86::R10) & 0x7;
17441 const unsigned char N86R11 = TRI->getEncodingValue(X86::R11) & 0x7;
17443 const unsigned char REX_WB = 0x40 | 0x08 | 0x01; // REX prefix
17445 // Load the pointer to the nested function into R11.
17446 unsigned OpCode = ((MOV64ri | N86R11) << 8) | REX_WB; // movabsq r11
17447 SDValue Addr = Trmp;
17448 OutChains[0] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, dl, MVT::i16),
17449 Addr, MachinePointerInfo(TrmpAddr),
17452 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
17453 DAG.getConstant(2, dl, MVT::i64));
17454 OutChains[1] = DAG.getStore(Root, dl, FPtr, Addr,
17455 MachinePointerInfo(TrmpAddr, 2),
17458 // Load the 'nest' parameter value into R10.
17459 // R10 is specified in X86CallingConv.td
17460 OpCode = ((MOV64ri | N86R10) << 8) | REX_WB; // movabsq r10
17461 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
17462 DAG.getConstant(10, dl, MVT::i64));
17463 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, dl, MVT::i16),
17464 Addr, MachinePointerInfo(TrmpAddr, 10),
17467 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
17468 DAG.getConstant(12, dl, MVT::i64));
17469 OutChains[3] = DAG.getStore(Root, dl, Nest, Addr,
17470 MachinePointerInfo(TrmpAddr, 12),
17473 // Jump to the nested function.
17474 OpCode = (JMP64r << 8) | REX_WB; // jmpq *...
17475 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
17476 DAG.getConstant(20, dl, MVT::i64));
17477 OutChains[4] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, dl, MVT::i16),
17478 Addr, MachinePointerInfo(TrmpAddr, 20),
17481 unsigned char ModRM = N86R11 | (4 << 3) | (3 << 6); // ...r11
17482 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
17483 DAG.getConstant(22, dl, MVT::i64));
17484 OutChains[5] = DAG.getStore(Root, dl, DAG.getConstant(ModRM, dl, MVT::i8),
17485 Addr, MachinePointerInfo(TrmpAddr, 22),
17488 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains);
17490 const Function *Func =
17491 cast<Function>(cast<SrcValueSDNode>(Op.getOperand(5))->getValue());
17492 CallingConv::ID CC = Func->getCallingConv();
17497 llvm_unreachable("Unsupported calling convention");
17498 case CallingConv::C:
17499 case CallingConv::X86_StdCall: {
17500 // Pass 'nest' parameter in ECX.
17501 // Must be kept in sync with X86CallingConv.td
17502 NestReg = X86::ECX;
17504 // Check that ECX wasn't needed by an 'inreg' parameter.
17505 FunctionType *FTy = Func->getFunctionType();
17506 const AttributeSet &Attrs = Func->getAttributes();
17508 if (!Attrs.isEmpty() && !Func->isVarArg()) {
17509 unsigned InRegCount = 0;
17512 for (FunctionType::param_iterator I = FTy->param_begin(),
17513 E = FTy->param_end(); I != E; ++I, ++Idx)
17514 if (Attrs.hasAttribute(Idx, Attribute::InReg)) {
17515 auto &DL = DAG.getDataLayout();
17516 // FIXME: should only count parameters that are lowered to integers.
17517 InRegCount += (DL.getTypeSizeInBits(*I) + 31) / 32;
17520 if (InRegCount > 2) {
17521 report_fatal_error("Nest register in use - reduce number of inreg"
17527 case CallingConv::X86_FastCall:
17528 case CallingConv::X86_ThisCall:
17529 case CallingConv::Fast:
17530 // Pass 'nest' parameter in EAX.
17531 // Must be kept in sync with X86CallingConv.td
17532 NestReg = X86::EAX;
17536 SDValue OutChains[4];
17537 SDValue Addr, Disp;
17539 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
17540 DAG.getConstant(10, dl, MVT::i32));
17541 Disp = DAG.getNode(ISD::SUB, dl, MVT::i32, FPtr, Addr);
17543 // This is storing the opcode for MOV32ri.
17544 const unsigned char MOV32ri = 0xB8; // X86::MOV32ri's opcode byte.
17545 const unsigned char N86Reg = TRI->getEncodingValue(NestReg) & 0x7;
17546 OutChains[0] = DAG.getStore(Root, dl,
17547 DAG.getConstant(MOV32ri|N86Reg, dl, MVT::i8),
17548 Trmp, MachinePointerInfo(TrmpAddr),
17551 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
17552 DAG.getConstant(1, dl, MVT::i32));
17553 OutChains[1] = DAG.getStore(Root, dl, Nest, Addr,
17554 MachinePointerInfo(TrmpAddr, 1),
17557 const unsigned char JMP = 0xE9; // jmp <32bit dst> opcode.
17558 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
17559 DAG.getConstant(5, dl, MVT::i32));
17560 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(JMP, dl, MVT::i8),
17561 Addr, MachinePointerInfo(TrmpAddr, 5),
17564 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
17565 DAG.getConstant(6, dl, MVT::i32));
17566 OutChains[3] = DAG.getStore(Root, dl, Disp, Addr,
17567 MachinePointerInfo(TrmpAddr, 6),
17570 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains);
17574 SDValue X86TargetLowering::LowerFLT_ROUNDS_(SDValue Op,
17575 SelectionDAG &DAG) const {
17577 The rounding mode is in bits 11:10 of FPSR, and has the following
17579 00 Round to nearest
17584 FLT_ROUNDS, on the other hand, expects the following:
17591 To perform the conversion, we do:
17592 (((((FPSR & 0x800) >> 11) | ((FPSR & 0x400) >> 9)) + 1) & 3)
17595 MachineFunction &MF = DAG.getMachineFunction();
17596 const TargetFrameLowering &TFI = *Subtarget->getFrameLowering();
17597 unsigned StackAlignment = TFI.getStackAlignment();
17598 MVT VT = Op.getSimpleValueType();
17601 // Save FP Control Word to stack slot
17602 int SSFI = MF.getFrameInfo()->CreateStackObject(2, StackAlignment, false);
17603 SDValue StackSlot =
17604 DAG.getFrameIndex(SSFI, getPointerTy(DAG.getDataLayout()));
17606 MachineMemOperand *MMO =
17607 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(MF, SSFI),
17608 MachineMemOperand::MOStore, 2, 2);
17610 SDValue Ops[] = { DAG.getEntryNode(), StackSlot };
17611 SDValue Chain = DAG.getMemIntrinsicNode(X86ISD::FNSTCW16m, DL,
17612 DAG.getVTList(MVT::Other),
17613 Ops, MVT::i16, MMO);
17615 // Load FP Control Word from stack slot
17616 SDValue CWD = DAG.getLoad(MVT::i16, DL, Chain, StackSlot,
17617 MachinePointerInfo(), false, false, false, 0);
17619 // Transform as necessary
17621 DAG.getNode(ISD::SRL, DL, MVT::i16,
17622 DAG.getNode(ISD::AND, DL, MVT::i16,
17623 CWD, DAG.getConstant(0x800, DL, MVT::i16)),
17624 DAG.getConstant(11, DL, MVT::i8));
17626 DAG.getNode(ISD::SRL, DL, MVT::i16,
17627 DAG.getNode(ISD::AND, DL, MVT::i16,
17628 CWD, DAG.getConstant(0x400, DL, MVT::i16)),
17629 DAG.getConstant(9, DL, MVT::i8));
17632 DAG.getNode(ISD::AND, DL, MVT::i16,
17633 DAG.getNode(ISD::ADD, DL, MVT::i16,
17634 DAG.getNode(ISD::OR, DL, MVT::i16, CWD1, CWD2),
17635 DAG.getConstant(1, DL, MVT::i16)),
17636 DAG.getConstant(3, DL, MVT::i16));
17638 return DAG.getNode((VT.getSizeInBits() < 16 ?
17639 ISD::TRUNCATE : ISD::ZERO_EXTEND), DL, VT, RetVal);
17642 /// \brief Lower a vector CTLZ using native supported vector CTLZ instruction.
17644 // 1. i32/i64 128/256-bit vector (native support require VLX) are expended
17645 // to 512-bit vector.
17646 // 2. i8/i16 vector implemented using dword LZCNT vector instruction
17647 // ( sub(trunc(lzcnt(zext32(x)))) ). In case zext32(x) is illegal,
17648 // split the vector, perform operation on it's Lo a Hi part and
17649 // concatenate the results.
17650 static SDValue LowerVectorCTLZ_AVX512(SDValue Op, SelectionDAG &DAG) {
17652 MVT VT = Op.getSimpleValueType();
17653 MVT EltVT = VT.getVectorElementType();
17654 unsigned NumElems = VT.getVectorNumElements();
17656 if (EltVT == MVT::i64 || EltVT == MVT::i32) {
17657 // Extend to 512 bit vector.
17658 assert((VT.is256BitVector() || VT.is128BitVector()) &&
17659 "Unsupported value type for operation");
17661 MVT NewVT = MVT::getVectorVT(EltVT, 512 / VT.getScalarSizeInBits());
17662 SDValue Vec512 = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, NewVT,
17663 DAG.getUNDEF(NewVT),
17665 DAG.getIntPtrConstant(0, dl));
17666 SDValue CtlzNode = DAG.getNode(ISD::CTLZ, dl, NewVT, Vec512);
17668 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, CtlzNode,
17669 DAG.getIntPtrConstant(0, dl));
17672 assert((EltVT == MVT::i8 || EltVT == MVT::i16) &&
17673 "Unsupported element type");
17675 if (16 < NumElems) {
17676 // Split vector, it's Lo and Hi parts will be handled in next iteration.
17678 std::tie(Lo, Hi) = DAG.SplitVector(Op.getOperand(0), dl);
17679 MVT OutVT = MVT::getVectorVT(EltVT, NumElems/2);
17681 Lo = DAG.getNode(Op.getOpcode(), dl, OutVT, Lo);
17682 Hi = DAG.getNode(Op.getOpcode(), dl, OutVT, Hi);
17684 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, Lo, Hi);
17687 MVT NewVT = MVT::getVectorVT(MVT::i32, NumElems);
17689 assert((NewVT.is256BitVector() || NewVT.is512BitVector()) &&
17690 "Unsupported value type for operation");
17692 // Use native supported vector instruction vplzcntd.
17693 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, NewVT, Op.getOperand(0));
17694 SDValue CtlzNode = DAG.getNode(ISD::CTLZ, dl, NewVT, Op);
17695 SDValue TruncNode = DAG.getNode(ISD::TRUNCATE, dl, VT, CtlzNode);
17696 SDValue Delta = DAG.getConstant(32 - EltVT.getSizeInBits(), dl, VT);
17698 return DAG.getNode(ISD::SUB, dl, VT, TruncNode, Delta);
17701 static SDValue LowerCTLZ(SDValue Op, const X86Subtarget *Subtarget,
17702 SelectionDAG &DAG) {
17703 MVT VT = Op.getSimpleValueType();
17705 unsigned NumBits = VT.getSizeInBits();
17708 if (VT.isVector() && Subtarget->hasAVX512())
17709 return LowerVectorCTLZ_AVX512(Op, DAG);
17711 Op = Op.getOperand(0);
17712 if (VT == MVT::i8) {
17713 // Zero extend to i32 since there is not an i8 bsr.
17715 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
17718 // Issue a bsr (scan bits in reverse) which also sets EFLAGS.
17719 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
17720 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
17722 // If src is zero (i.e. bsr sets ZF), returns NumBits.
17725 DAG.getConstant(NumBits + NumBits - 1, dl, OpVT),
17726 DAG.getConstant(X86::COND_E, dl, MVT::i8),
17729 Op = DAG.getNode(X86ISD::CMOV, dl, OpVT, Ops);
17731 // Finally xor with NumBits-1.
17732 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op,
17733 DAG.getConstant(NumBits - 1, dl, OpVT));
17736 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
17740 static SDValue LowerCTLZ_ZERO_UNDEF(SDValue Op, const X86Subtarget *Subtarget,
17741 SelectionDAG &DAG) {
17742 MVT VT = Op.getSimpleValueType();
17744 unsigned NumBits = VT.getSizeInBits();
17747 if (VT.isVector() && Subtarget->hasAVX512())
17748 return LowerVectorCTLZ_AVX512(Op, DAG);
17750 Op = Op.getOperand(0);
17751 if (VT == MVT::i8) {
17752 // Zero extend to i32 since there is not an i8 bsr.
17754 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
17757 // Issue a bsr (scan bits in reverse).
17758 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
17759 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
17761 // And xor with NumBits-1.
17762 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op,
17763 DAG.getConstant(NumBits - 1, dl, OpVT));
17766 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
17770 static SDValue LowerCTTZ(SDValue Op, SelectionDAG &DAG) {
17771 MVT VT = Op.getSimpleValueType();
17772 unsigned NumBits = VT.getScalarSizeInBits();
17775 if (VT.isVector()) {
17776 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
17778 SDValue N0 = Op.getOperand(0);
17779 SDValue Zero = DAG.getConstant(0, dl, VT);
17781 // lsb(x) = (x & -x)
17782 SDValue LSB = DAG.getNode(ISD::AND, dl, VT, N0,
17783 DAG.getNode(ISD::SUB, dl, VT, Zero, N0));
17785 // cttz_undef(x) = (width - 1) - ctlz(lsb)
17786 if (Op.getOpcode() == ISD::CTTZ_ZERO_UNDEF &&
17787 TLI.isOperationLegal(ISD::CTLZ, VT)) {
17788 SDValue WidthMinusOne = DAG.getConstant(NumBits - 1, dl, VT);
17789 return DAG.getNode(ISD::SUB, dl, VT, WidthMinusOne,
17790 DAG.getNode(ISD::CTLZ, dl, VT, LSB));
17793 // cttz(x) = ctpop(lsb - 1)
17794 SDValue One = DAG.getConstant(1, dl, VT);
17795 return DAG.getNode(ISD::CTPOP, dl, VT,
17796 DAG.getNode(ISD::SUB, dl, VT, LSB, One));
17799 assert(Op.getOpcode() == ISD::CTTZ &&
17800 "Only scalar CTTZ requires custom lowering");
17802 // Issue a bsf (scan bits forward) which also sets EFLAGS.
17803 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
17804 Op = DAG.getNode(X86ISD::BSF, dl, VTs, Op.getOperand(0));
17806 // If src is zero (i.e. bsf sets ZF), returns NumBits.
17809 DAG.getConstant(NumBits, dl, VT),
17810 DAG.getConstant(X86::COND_E, dl, MVT::i8),
17813 return DAG.getNode(X86ISD::CMOV, dl, VT, Ops);
17816 // Lower256IntArith - Break a 256-bit integer operation into two new 128-bit
17817 // ones, and then concatenate the result back.
17818 static SDValue Lower256IntArith(SDValue Op, SelectionDAG &DAG) {
17819 MVT VT = Op.getSimpleValueType();
17821 assert(VT.is256BitVector() && VT.isInteger() &&
17822 "Unsupported value type for operation");
17824 unsigned NumElems = VT.getVectorNumElements();
17827 // Extract the LHS vectors
17828 SDValue LHS = Op.getOperand(0);
17829 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
17830 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
17832 // Extract the RHS vectors
17833 SDValue RHS = Op.getOperand(1);
17834 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, dl);
17835 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, dl);
17837 MVT EltVT = VT.getVectorElementType();
17838 MVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
17840 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
17841 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1),
17842 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2));
17845 static SDValue LowerADD(SDValue Op, SelectionDAG &DAG) {
17846 if (Op.getValueType() == MVT::i1)
17847 return DAG.getNode(ISD::XOR, SDLoc(Op), Op.getValueType(),
17848 Op.getOperand(0), Op.getOperand(1));
17849 assert(Op.getSimpleValueType().is256BitVector() &&
17850 Op.getSimpleValueType().isInteger() &&
17851 "Only handle AVX 256-bit vector integer operation");
17852 return Lower256IntArith(Op, DAG);
17855 static SDValue LowerSUB(SDValue Op, SelectionDAG &DAG) {
17856 if (Op.getValueType() == MVT::i1)
17857 return DAG.getNode(ISD::XOR, SDLoc(Op), Op.getValueType(),
17858 Op.getOperand(0), Op.getOperand(1));
17859 assert(Op.getSimpleValueType().is256BitVector() &&
17860 Op.getSimpleValueType().isInteger() &&
17861 "Only handle AVX 256-bit vector integer operation");
17862 return Lower256IntArith(Op, DAG);
17865 static SDValue LowerMINMAX(SDValue Op, SelectionDAG &DAG) {
17866 assert(Op.getSimpleValueType().is256BitVector() &&
17867 Op.getSimpleValueType().isInteger() &&
17868 "Only handle AVX 256-bit vector integer operation");
17869 return Lower256IntArith(Op, DAG);
17872 static SDValue LowerMUL(SDValue Op, const X86Subtarget *Subtarget,
17873 SelectionDAG &DAG) {
17875 MVT VT = Op.getSimpleValueType();
17878 return DAG.getNode(ISD::AND, dl, VT, Op.getOperand(0), Op.getOperand(1));
17880 // Decompose 256-bit ops into smaller 128-bit ops.
17881 if (VT.is256BitVector() && !Subtarget->hasInt256())
17882 return Lower256IntArith(Op, DAG);
17884 SDValue A = Op.getOperand(0);
17885 SDValue B = Op.getOperand(1);
17887 // Lower v16i8/v32i8 mul as promotion to v8i16/v16i16 vector
17888 // pairs, multiply and truncate.
17889 if (VT == MVT::v16i8 || VT == MVT::v32i8) {
17890 if (Subtarget->hasInt256()) {
17891 if (VT == MVT::v32i8) {
17892 MVT SubVT = MVT::getVectorVT(MVT::i8, VT.getVectorNumElements() / 2);
17893 SDValue Lo = DAG.getIntPtrConstant(0, dl);
17894 SDValue Hi = DAG.getIntPtrConstant(VT.getVectorNumElements() / 2, dl);
17895 SDValue ALo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, SubVT, A, Lo);
17896 SDValue BLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, SubVT, B, Lo);
17897 SDValue AHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, SubVT, A, Hi);
17898 SDValue BHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, SubVT, B, Hi);
17899 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
17900 DAG.getNode(ISD::MUL, dl, SubVT, ALo, BLo),
17901 DAG.getNode(ISD::MUL, dl, SubVT, AHi, BHi));
17904 MVT ExVT = MVT::getVectorVT(MVT::i16, VT.getVectorNumElements());
17905 return DAG.getNode(
17906 ISD::TRUNCATE, dl, VT,
17907 DAG.getNode(ISD::MUL, dl, ExVT,
17908 DAG.getNode(ISD::SIGN_EXTEND, dl, ExVT, A),
17909 DAG.getNode(ISD::SIGN_EXTEND, dl, ExVT, B)));
17912 assert(VT == MVT::v16i8 &&
17913 "Pre-AVX2 support only supports v16i8 multiplication");
17914 MVT ExVT = MVT::v8i16;
17916 // Extract the lo parts and sign extend to i16
17918 if (Subtarget->hasSSE41()) {
17919 ALo = DAG.getNode(X86ISD::VSEXT, dl, ExVT, A);
17920 BLo = DAG.getNode(X86ISD::VSEXT, dl, ExVT, B);
17922 const int ShufMask[] = {-1, 0, -1, 1, -1, 2, -1, 3,
17923 -1, 4, -1, 5, -1, 6, -1, 7};
17924 ALo = DAG.getVectorShuffle(VT, dl, A, A, ShufMask);
17925 BLo = DAG.getVectorShuffle(VT, dl, B, B, ShufMask);
17926 ALo = DAG.getBitcast(ExVT, ALo);
17927 BLo = DAG.getBitcast(ExVT, BLo);
17928 ALo = DAG.getNode(ISD::SRA, dl, ExVT, ALo, DAG.getConstant(8, dl, ExVT));
17929 BLo = DAG.getNode(ISD::SRA, dl, ExVT, BLo, DAG.getConstant(8, dl, ExVT));
17932 // Extract the hi parts and sign extend to i16
17934 if (Subtarget->hasSSE41()) {
17935 const int ShufMask[] = {8, 9, 10, 11, 12, 13, 14, 15,
17936 -1, -1, -1, -1, -1, -1, -1, -1};
17937 AHi = DAG.getVectorShuffle(VT, dl, A, A, ShufMask);
17938 BHi = DAG.getVectorShuffle(VT, dl, B, B, ShufMask);
17939 AHi = DAG.getNode(X86ISD::VSEXT, dl, ExVT, AHi);
17940 BHi = DAG.getNode(X86ISD::VSEXT, dl, ExVT, BHi);
17942 const int ShufMask[] = {-1, 8, -1, 9, -1, 10, -1, 11,
17943 -1, 12, -1, 13, -1, 14, -1, 15};
17944 AHi = DAG.getVectorShuffle(VT, dl, A, A, ShufMask);
17945 BHi = DAG.getVectorShuffle(VT, dl, B, B, ShufMask);
17946 AHi = DAG.getBitcast(ExVT, AHi);
17947 BHi = DAG.getBitcast(ExVT, BHi);
17948 AHi = DAG.getNode(ISD::SRA, dl, ExVT, AHi, DAG.getConstant(8, dl, ExVT));
17949 BHi = DAG.getNode(ISD::SRA, dl, ExVT, BHi, DAG.getConstant(8, dl, ExVT));
17952 // Multiply, mask the lower 8bits of the lo/hi results and pack
17953 SDValue RLo = DAG.getNode(ISD::MUL, dl, ExVT, ALo, BLo);
17954 SDValue RHi = DAG.getNode(ISD::MUL, dl, ExVT, AHi, BHi);
17955 RLo = DAG.getNode(ISD::AND, dl, ExVT, RLo, DAG.getConstant(255, dl, ExVT));
17956 RHi = DAG.getNode(ISD::AND, dl, ExVT, RHi, DAG.getConstant(255, dl, ExVT));
17957 return DAG.getNode(X86ISD::PACKUS, dl, VT, RLo, RHi);
17960 // Lower v4i32 mul as 2x shuffle, 2x pmuludq, 2x shuffle.
17961 if (VT == MVT::v4i32) {
17962 assert(Subtarget->hasSSE2() && !Subtarget->hasSSE41() &&
17963 "Should not custom lower when pmuldq is available!");
17965 // Extract the odd parts.
17966 static const int UnpackMask[] = { 1, -1, 3, -1 };
17967 SDValue Aodds = DAG.getVectorShuffle(VT, dl, A, A, UnpackMask);
17968 SDValue Bodds = DAG.getVectorShuffle(VT, dl, B, B, UnpackMask);
17970 // Multiply the even parts.
17971 SDValue Evens = DAG.getNode(X86ISD::PMULUDQ, dl, MVT::v2i64, A, B);
17972 // Now multiply odd parts.
17973 SDValue Odds = DAG.getNode(X86ISD::PMULUDQ, dl, MVT::v2i64, Aodds, Bodds);
17975 Evens = DAG.getBitcast(VT, Evens);
17976 Odds = DAG.getBitcast(VT, Odds);
17978 // Merge the two vectors back together with a shuffle. This expands into 2
17980 static const int ShufMask[] = { 0, 4, 2, 6 };
17981 return DAG.getVectorShuffle(VT, dl, Evens, Odds, ShufMask);
17984 assert((VT == MVT::v2i64 || VT == MVT::v4i64 || VT == MVT::v8i64) &&
17985 "Only know how to lower V2I64/V4I64/V8I64 multiply");
17987 // Ahi = psrlqi(a, 32);
17988 // Bhi = psrlqi(b, 32);
17990 // AloBlo = pmuludq(a, b);
17991 // AloBhi = pmuludq(a, Bhi);
17992 // AhiBlo = pmuludq(Ahi, b);
17994 // AloBhi = psllqi(AloBhi, 32);
17995 // AhiBlo = psllqi(AhiBlo, 32);
17996 // return AloBlo + AloBhi + AhiBlo;
17998 SDValue Ahi = getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, A, 32, DAG);
17999 SDValue Bhi = getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, B, 32, DAG);
18001 SDValue AhiBlo = Ahi;
18002 SDValue AloBhi = Bhi;
18003 // Bit cast to 32-bit vectors for MULUDQ
18004 MVT MulVT = (VT == MVT::v2i64) ? MVT::v4i32 :
18005 (VT == MVT::v4i64) ? MVT::v8i32 : MVT::v16i32;
18006 A = DAG.getBitcast(MulVT, A);
18007 B = DAG.getBitcast(MulVT, B);
18008 Ahi = DAG.getBitcast(MulVT, Ahi);
18009 Bhi = DAG.getBitcast(MulVT, Bhi);
18011 SDValue AloBlo = DAG.getNode(X86ISD::PMULUDQ, dl, VT, A, B);
18012 // After shifting right const values the result may be all-zero.
18013 if (!ISD::isBuildVectorAllZeros(Ahi.getNode())) {
18014 AhiBlo = DAG.getNode(X86ISD::PMULUDQ, dl, VT, Ahi, B);
18015 AhiBlo = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, AhiBlo, 32, DAG);
18017 if (!ISD::isBuildVectorAllZeros(Bhi.getNode())) {
18018 AloBhi = DAG.getNode(X86ISD::PMULUDQ, dl, VT, A, Bhi);
18019 AloBhi = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, AloBhi, 32, DAG);
18022 SDValue Res = DAG.getNode(ISD::ADD, dl, VT, AloBlo, AloBhi);
18023 return DAG.getNode(ISD::ADD, dl, VT, Res, AhiBlo);
18026 SDValue X86TargetLowering::LowerWin64_i128OP(SDValue Op, SelectionDAG &DAG) const {
18027 assert(Subtarget->isTargetWin64() && "Unexpected target");
18028 EVT VT = Op.getValueType();
18029 assert(VT.isInteger() && VT.getSizeInBits() == 128 &&
18030 "Unexpected return type for lowering");
18034 switch (Op->getOpcode()) {
18035 default: llvm_unreachable("Unexpected request for libcall!");
18036 case ISD::SDIV: isSigned = true; LC = RTLIB::SDIV_I128; break;
18037 case ISD::UDIV: isSigned = false; LC = RTLIB::UDIV_I128; break;
18038 case ISD::SREM: isSigned = true; LC = RTLIB::SREM_I128; break;
18039 case ISD::UREM: isSigned = false; LC = RTLIB::UREM_I128; break;
18040 case ISD::SDIVREM: isSigned = true; LC = RTLIB::SDIVREM_I128; break;
18041 case ISD::UDIVREM: isSigned = false; LC = RTLIB::UDIVREM_I128; break;
18045 SDValue InChain = DAG.getEntryNode();
18047 TargetLowering::ArgListTy Args;
18048 TargetLowering::ArgListEntry Entry;
18049 for (unsigned i = 0, e = Op->getNumOperands(); i != e; ++i) {
18050 EVT ArgVT = Op->getOperand(i).getValueType();
18051 assert(ArgVT.isInteger() && ArgVT.getSizeInBits() == 128 &&
18052 "Unexpected argument type for lowering");
18053 SDValue StackPtr = DAG.CreateStackTemporary(ArgVT, 16);
18054 Entry.Node = StackPtr;
18055 InChain = DAG.getStore(InChain, dl, Op->getOperand(i), StackPtr, MachinePointerInfo(),
18057 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
18058 Entry.Ty = PointerType::get(ArgTy,0);
18059 Entry.isSExt = false;
18060 Entry.isZExt = false;
18061 Args.push_back(Entry);
18064 SDValue Callee = DAG.getExternalSymbol(getLibcallName(LC),
18065 getPointerTy(DAG.getDataLayout()));
18067 TargetLowering::CallLoweringInfo CLI(DAG);
18068 CLI.setDebugLoc(dl).setChain(InChain)
18069 .setCallee(getLibcallCallingConv(LC),
18070 static_cast<EVT>(MVT::v2i64).getTypeForEVT(*DAG.getContext()),
18071 Callee, std::move(Args), 0)
18072 .setInRegister().setSExtResult(isSigned).setZExtResult(!isSigned);
18074 std::pair<SDValue, SDValue> CallInfo = LowerCallTo(CLI);
18075 return DAG.getBitcast(VT, CallInfo.first);
18078 static SDValue LowerMUL_LOHI(SDValue Op, const X86Subtarget *Subtarget,
18079 SelectionDAG &DAG) {
18080 SDValue Op0 = Op.getOperand(0), Op1 = Op.getOperand(1);
18081 MVT VT = Op0.getSimpleValueType();
18084 assert((VT == MVT::v4i32 && Subtarget->hasSSE2()) ||
18085 (VT == MVT::v8i32 && Subtarget->hasInt256()));
18087 // PMULxD operations multiply each even value (starting at 0) of LHS with
18088 // the related value of RHS and produce a widen result.
18089 // E.g., PMULUDQ <4 x i32> <a|b|c|d>, <4 x i32> <e|f|g|h>
18090 // => <2 x i64> <ae|cg>
18092 // In other word, to have all the results, we need to perform two PMULxD:
18093 // 1. one with the even values.
18094 // 2. one with the odd values.
18095 // To achieve #2, with need to place the odd values at an even position.
18097 // Place the odd value at an even position (basically, shift all values 1
18098 // step to the left):
18099 const int Mask[] = {1, -1, 3, -1, 5, -1, 7, -1};
18100 // <a|b|c|d> => <b|undef|d|undef>
18101 SDValue Odd0 = DAG.getVectorShuffle(VT, dl, Op0, Op0, Mask);
18102 // <e|f|g|h> => <f|undef|h|undef>
18103 SDValue Odd1 = DAG.getVectorShuffle(VT, dl, Op1, Op1, Mask);
18105 // Emit two multiplies, one for the lower 2 ints and one for the higher 2
18107 MVT MulVT = VT == MVT::v4i32 ? MVT::v2i64 : MVT::v4i64;
18108 bool IsSigned = Op->getOpcode() == ISD::SMUL_LOHI;
18110 (!IsSigned || !Subtarget->hasSSE41()) ? X86ISD::PMULUDQ : X86ISD::PMULDQ;
18111 // PMULUDQ <4 x i32> <a|b|c|d>, <4 x i32> <e|f|g|h>
18112 // => <2 x i64> <ae|cg>
18113 SDValue Mul1 = DAG.getBitcast(VT, DAG.getNode(Opcode, dl, MulVT, Op0, Op1));
18114 // PMULUDQ <4 x i32> <b|undef|d|undef>, <4 x i32> <f|undef|h|undef>
18115 // => <2 x i64> <bf|dh>
18116 SDValue Mul2 = DAG.getBitcast(VT, DAG.getNode(Opcode, dl, MulVT, Odd0, Odd1));
18118 // Shuffle it back into the right order.
18119 SDValue Highs, Lows;
18120 if (VT == MVT::v8i32) {
18121 const int HighMask[] = {1, 9, 3, 11, 5, 13, 7, 15};
18122 Highs = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, HighMask);
18123 const int LowMask[] = {0, 8, 2, 10, 4, 12, 6, 14};
18124 Lows = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, LowMask);
18126 const int HighMask[] = {1, 5, 3, 7};
18127 Highs = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, HighMask);
18128 const int LowMask[] = {0, 4, 2, 6};
18129 Lows = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, LowMask);
18132 // If we have a signed multiply but no PMULDQ fix up the high parts of a
18133 // unsigned multiply.
18134 if (IsSigned && !Subtarget->hasSSE41()) {
18135 SDValue ShAmt = DAG.getConstant(
18137 DAG.getTargetLoweringInfo().getShiftAmountTy(VT, DAG.getDataLayout()));
18138 SDValue T1 = DAG.getNode(ISD::AND, dl, VT,
18139 DAG.getNode(ISD::SRA, dl, VT, Op0, ShAmt), Op1);
18140 SDValue T2 = DAG.getNode(ISD::AND, dl, VT,
18141 DAG.getNode(ISD::SRA, dl, VT, Op1, ShAmt), Op0);
18143 SDValue Fixup = DAG.getNode(ISD::ADD, dl, VT, T1, T2);
18144 Highs = DAG.getNode(ISD::SUB, dl, VT, Highs, Fixup);
18147 // The first result of MUL_LOHI is actually the low value, followed by the
18149 SDValue Ops[] = {Lows, Highs};
18150 return DAG.getMergeValues(Ops, dl);
18153 // Return true if the required (according to Opcode) shift-imm form is natively
18154 // supported by the Subtarget
18155 static bool SupportedVectorShiftWithImm(MVT VT, const X86Subtarget *Subtarget,
18157 if (VT.getScalarSizeInBits() < 16)
18160 if (VT.is512BitVector() &&
18161 (VT.getScalarSizeInBits() > 16 || Subtarget->hasBWI()))
18164 bool LShift = VT.is128BitVector() ||
18165 (VT.is256BitVector() && Subtarget->hasInt256());
18167 bool AShift = LShift && (Subtarget->hasVLX() ||
18168 (VT != MVT::v2i64 && VT != MVT::v4i64));
18169 return (Opcode == ISD::SRA) ? AShift : LShift;
18172 // The shift amount is a variable, but it is the same for all vector lanes.
18173 // These instructions are defined together with shift-immediate.
18175 bool SupportedVectorShiftWithBaseAmnt(MVT VT, const X86Subtarget *Subtarget,
18177 return SupportedVectorShiftWithImm(VT, Subtarget, Opcode);
18180 // Return true if the required (according to Opcode) variable-shift form is
18181 // natively supported by the Subtarget
18182 static bool SupportedVectorVarShift(MVT VT, const X86Subtarget *Subtarget,
18185 if (!Subtarget->hasInt256() || VT.getScalarSizeInBits() < 16)
18188 // vXi16 supported only on AVX-512, BWI
18189 if (VT.getScalarSizeInBits() == 16 && !Subtarget->hasBWI())
18192 if (VT.is512BitVector() || Subtarget->hasVLX())
18195 bool LShift = VT.is128BitVector() || VT.is256BitVector();
18196 bool AShift = LShift && VT != MVT::v2i64 && VT != MVT::v4i64;
18197 return (Opcode == ISD::SRA) ? AShift : LShift;
18200 static SDValue LowerScalarImmediateShift(SDValue Op, SelectionDAG &DAG,
18201 const X86Subtarget *Subtarget) {
18202 MVT VT = Op.getSimpleValueType();
18204 SDValue R = Op.getOperand(0);
18205 SDValue Amt = Op.getOperand(1);
18207 unsigned X86Opc = (Op.getOpcode() == ISD::SHL) ? X86ISD::VSHLI :
18208 (Op.getOpcode() == ISD::SRL) ? X86ISD::VSRLI : X86ISD::VSRAI;
18210 auto ArithmeticShiftRight64 = [&](uint64_t ShiftAmt) {
18211 assert((VT == MVT::v2i64 || VT == MVT::v4i64) && "Unexpected SRA type");
18212 MVT ExVT = MVT::getVectorVT(MVT::i32, VT.getVectorNumElements() * 2);
18213 SDValue Ex = DAG.getBitcast(ExVT, R);
18215 if (ShiftAmt >= 32) {
18216 // Splat sign to upper i32 dst, and SRA upper i32 src to lower i32.
18218 getTargetVShiftByConstNode(X86ISD::VSRAI, dl, ExVT, Ex, 31, DAG);
18219 SDValue Lower = getTargetVShiftByConstNode(X86ISD::VSRAI, dl, ExVT, Ex,
18220 ShiftAmt - 32, DAG);
18221 if (VT == MVT::v2i64)
18222 Ex = DAG.getVectorShuffle(ExVT, dl, Upper, Lower, {5, 1, 7, 3});
18223 if (VT == MVT::v4i64)
18224 Ex = DAG.getVectorShuffle(ExVT, dl, Upper, Lower,
18225 {9, 1, 11, 3, 13, 5, 15, 7});
18227 // SRA upper i32, SHL whole i64 and select lower i32.
18228 SDValue Upper = getTargetVShiftByConstNode(X86ISD::VSRAI, dl, ExVT, Ex,
18231 getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, R, ShiftAmt, DAG);
18232 Lower = DAG.getBitcast(ExVT, Lower);
18233 if (VT == MVT::v2i64)
18234 Ex = DAG.getVectorShuffle(ExVT, dl, Upper, Lower, {4, 1, 6, 3});
18235 if (VT == MVT::v4i64)
18236 Ex = DAG.getVectorShuffle(ExVT, dl, Upper, Lower,
18237 {8, 1, 10, 3, 12, 5, 14, 7});
18239 return DAG.getBitcast(VT, Ex);
18242 // Optimize shl/srl/sra with constant shift amount.
18243 if (auto *BVAmt = dyn_cast<BuildVectorSDNode>(Amt)) {
18244 if (auto *ShiftConst = BVAmt->getConstantSplatNode()) {
18245 uint64_t ShiftAmt = ShiftConst->getZExtValue();
18247 if (SupportedVectorShiftWithImm(VT, Subtarget, Op.getOpcode()))
18248 return getTargetVShiftByConstNode(X86Opc, dl, VT, R, ShiftAmt, DAG);
18250 // i64 SRA needs to be performed as partial shifts.
18251 if ((VT == MVT::v2i64 || (Subtarget->hasInt256() && VT == MVT::v4i64)) &&
18252 Op.getOpcode() == ISD::SRA && !Subtarget->hasXOP())
18253 return ArithmeticShiftRight64(ShiftAmt);
18255 if (VT == MVT::v16i8 || (Subtarget->hasInt256() && VT == MVT::v32i8)) {
18256 unsigned NumElts = VT.getVectorNumElements();
18257 MVT ShiftVT = MVT::getVectorVT(MVT::i16, NumElts / 2);
18259 // Simple i8 add case
18260 if (Op.getOpcode() == ISD::SHL && ShiftAmt == 1)
18261 return DAG.getNode(ISD::ADD, dl, VT, R, R);
18263 // ashr(R, 7) === cmp_slt(R, 0)
18264 if (Op.getOpcode() == ISD::SRA && ShiftAmt == 7) {
18265 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
18266 return DAG.getNode(X86ISD::PCMPGT, dl, VT, Zeros, R);
18269 // XOP can shift v16i8 directly instead of as shift v8i16 + mask.
18270 if (VT == MVT::v16i8 && Subtarget->hasXOP())
18273 if (Op.getOpcode() == ISD::SHL) {
18274 // Make a large shift.
18275 SDValue SHL = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, ShiftVT,
18277 SHL = DAG.getBitcast(VT, SHL);
18278 // Zero out the rightmost bits.
18279 SmallVector<SDValue, 32> V(
18280 NumElts, DAG.getConstant(uint8_t(-1U << ShiftAmt), dl, MVT::i8));
18281 return DAG.getNode(ISD::AND, dl, VT, SHL,
18282 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V));
18284 if (Op.getOpcode() == ISD::SRL) {
18285 // Make a large shift.
18286 SDValue SRL = getTargetVShiftByConstNode(X86ISD::VSRLI, dl, ShiftVT,
18288 SRL = DAG.getBitcast(VT, SRL);
18289 // Zero out the leftmost bits.
18290 SmallVector<SDValue, 32> V(
18291 NumElts, DAG.getConstant(uint8_t(-1U) >> ShiftAmt, dl, MVT::i8));
18292 return DAG.getNode(ISD::AND, dl, VT, SRL,
18293 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V));
18295 if (Op.getOpcode() == ISD::SRA) {
18296 // ashr(R, Amt) === sub(xor(lshr(R, Amt), Mask), Mask)
18297 SDValue Res = DAG.getNode(ISD::SRL, dl, VT, R, Amt);
18298 SmallVector<SDValue, 32> V(NumElts,
18299 DAG.getConstant(128 >> ShiftAmt, dl,
18301 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V);
18302 Res = DAG.getNode(ISD::XOR, dl, VT, Res, Mask);
18303 Res = DAG.getNode(ISD::SUB, dl, VT, Res, Mask);
18306 llvm_unreachable("Unknown shift opcode.");
18311 // Special case in 32-bit mode, where i64 is expanded into high and low parts.
18312 if (!Subtarget->is64Bit() && !Subtarget->hasXOP() &&
18313 (VT == MVT::v2i64 || (Subtarget->hasInt256() && VT == MVT::v4i64))) {
18315 // Peek through any splat that was introduced for i64 shift vectorization.
18316 int SplatIndex = -1;
18317 if (ShuffleVectorSDNode *SVN = dyn_cast<ShuffleVectorSDNode>(Amt.getNode()))
18318 if (SVN->isSplat()) {
18319 SplatIndex = SVN->getSplatIndex();
18320 Amt = Amt.getOperand(0);
18321 assert(SplatIndex < (int)VT.getVectorNumElements() &&
18322 "Splat shuffle referencing second operand");
18325 if (Amt.getOpcode() != ISD::BITCAST ||
18326 Amt.getOperand(0).getOpcode() != ISD::BUILD_VECTOR)
18329 Amt = Amt.getOperand(0);
18330 unsigned Ratio = Amt.getSimpleValueType().getVectorNumElements() /
18331 VT.getVectorNumElements();
18332 unsigned RatioInLog2 = Log2_32_Ceil(Ratio);
18333 uint64_t ShiftAmt = 0;
18334 unsigned BaseOp = (SplatIndex < 0 ? 0 : SplatIndex * Ratio);
18335 for (unsigned i = 0; i != Ratio; ++i) {
18336 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Amt.getOperand(i + BaseOp));
18340 ShiftAmt |= C->getZExtValue() << (i * (1 << (6 - RatioInLog2)));
18343 // Check remaining shift amounts (if not a splat).
18344 if (SplatIndex < 0) {
18345 for (unsigned i = Ratio; i != Amt.getNumOperands(); i += Ratio) {
18346 uint64_t ShAmt = 0;
18347 for (unsigned j = 0; j != Ratio; ++j) {
18348 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Amt.getOperand(i + j));
18352 ShAmt |= C->getZExtValue() << (j * (1 << (6 - RatioInLog2)));
18354 if (ShAmt != ShiftAmt)
18359 if (SupportedVectorShiftWithImm(VT, Subtarget, Op.getOpcode()))
18360 return getTargetVShiftByConstNode(X86Opc, dl, VT, R, ShiftAmt, DAG);
18362 if (Op.getOpcode() == ISD::SRA)
18363 return ArithmeticShiftRight64(ShiftAmt);
18369 static SDValue LowerScalarVariableShift(SDValue Op, SelectionDAG &DAG,
18370 const X86Subtarget* Subtarget) {
18371 MVT VT = Op.getSimpleValueType();
18373 SDValue R = Op.getOperand(0);
18374 SDValue Amt = Op.getOperand(1);
18376 unsigned X86OpcI = (Op.getOpcode() == ISD::SHL) ? X86ISD::VSHLI :
18377 (Op.getOpcode() == ISD::SRL) ? X86ISD::VSRLI : X86ISD::VSRAI;
18379 unsigned X86OpcV = (Op.getOpcode() == ISD::SHL) ? X86ISD::VSHL :
18380 (Op.getOpcode() == ISD::SRL) ? X86ISD::VSRL : X86ISD::VSRA;
18382 if (SupportedVectorShiftWithBaseAmnt(VT, Subtarget, Op.getOpcode())) {
18384 MVT EltVT = VT.getVectorElementType();
18386 if (BuildVectorSDNode *BV = dyn_cast<BuildVectorSDNode>(Amt)) {
18387 // Check if this build_vector node is doing a splat.
18388 // If so, then set BaseShAmt equal to the splat value.
18389 BaseShAmt = BV->getSplatValue();
18390 if (BaseShAmt && BaseShAmt.getOpcode() == ISD::UNDEF)
18391 BaseShAmt = SDValue();
18393 if (Amt.getOpcode() == ISD::EXTRACT_SUBVECTOR)
18394 Amt = Amt.getOperand(0);
18396 ShuffleVectorSDNode *SVN = dyn_cast<ShuffleVectorSDNode>(Amt);
18397 if (SVN && SVN->isSplat()) {
18398 unsigned SplatIdx = (unsigned)SVN->getSplatIndex();
18399 SDValue InVec = Amt.getOperand(0);
18400 if (InVec.getOpcode() == ISD::BUILD_VECTOR) {
18401 assert((SplatIdx < InVec.getSimpleValueType().getVectorNumElements()) &&
18402 "Unexpected shuffle index found!");
18403 BaseShAmt = InVec.getOperand(SplatIdx);
18404 } else if (InVec.getOpcode() == ISD::INSERT_VECTOR_ELT) {
18405 if (ConstantSDNode *C =
18406 dyn_cast<ConstantSDNode>(InVec.getOperand(2))) {
18407 if (C->getZExtValue() == SplatIdx)
18408 BaseShAmt = InVec.getOperand(1);
18413 // Avoid introducing an extract element from a shuffle.
18414 BaseShAmt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, InVec,
18415 DAG.getIntPtrConstant(SplatIdx, dl));
18419 if (BaseShAmt.getNode()) {
18420 assert(EltVT.bitsLE(MVT::i64) && "Unexpected element type!");
18421 if (EltVT != MVT::i64 && EltVT.bitsGT(MVT::i32))
18422 BaseShAmt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i64, BaseShAmt);
18423 else if (EltVT.bitsLT(MVT::i32))
18424 BaseShAmt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, BaseShAmt);
18426 return getTargetVShiftNode(X86OpcI, dl, VT, R, BaseShAmt, DAG);
18430 // Special case in 32-bit mode, where i64 is expanded into high and low parts.
18431 if (!Subtarget->is64Bit() && VT == MVT::v2i64 &&
18432 Amt.getOpcode() == ISD::BITCAST &&
18433 Amt.getOperand(0).getOpcode() == ISD::BUILD_VECTOR) {
18434 Amt = Amt.getOperand(0);
18435 unsigned Ratio = Amt.getSimpleValueType().getVectorNumElements() /
18436 VT.getVectorNumElements();
18437 std::vector<SDValue> Vals(Ratio);
18438 for (unsigned i = 0; i != Ratio; ++i)
18439 Vals[i] = Amt.getOperand(i);
18440 for (unsigned i = Ratio; i != Amt.getNumOperands(); i += Ratio) {
18441 for (unsigned j = 0; j != Ratio; ++j)
18442 if (Vals[j] != Amt.getOperand(i + j))
18446 if (SupportedVectorShiftWithBaseAmnt(VT, Subtarget, Op.getOpcode()))
18447 return DAG.getNode(X86OpcV, dl, VT, R, Op.getOperand(1));
18452 static SDValue LowerShift(SDValue Op, const X86Subtarget* Subtarget,
18453 SelectionDAG &DAG) {
18454 MVT VT = Op.getSimpleValueType();
18456 SDValue R = Op.getOperand(0);
18457 SDValue Amt = Op.getOperand(1);
18459 assert(VT.isVector() && "Custom lowering only for vector shifts!");
18460 assert(Subtarget->hasSSE2() && "Only custom lower when we have SSE2!");
18462 if (SDValue V = LowerScalarImmediateShift(Op, DAG, Subtarget))
18465 if (SDValue V = LowerScalarVariableShift(Op, DAG, Subtarget))
18468 if (SupportedVectorVarShift(VT, Subtarget, Op.getOpcode()))
18471 // XOP has 128-bit variable logical/arithmetic shifts.
18472 // +ve/-ve Amt = shift left/right.
18473 if (Subtarget->hasXOP() &&
18474 (VT == MVT::v2i64 || VT == MVT::v4i32 ||
18475 VT == MVT::v8i16 || VT == MVT::v16i8)) {
18476 if (Op.getOpcode() == ISD::SRL || Op.getOpcode() == ISD::SRA) {
18477 SDValue Zero = getZeroVector(VT, Subtarget, DAG, dl);
18478 Amt = DAG.getNode(ISD::SUB, dl, VT, Zero, Amt);
18480 if (Op.getOpcode() == ISD::SHL || Op.getOpcode() == ISD::SRL)
18481 return DAG.getNode(X86ISD::VPSHL, dl, VT, R, Amt);
18482 if (Op.getOpcode() == ISD::SRA)
18483 return DAG.getNode(X86ISD::VPSHA, dl, VT, R, Amt);
18486 // 2i64 vector logical shifts can efficiently avoid scalarization - do the
18487 // shifts per-lane and then shuffle the partial results back together.
18488 if (VT == MVT::v2i64 && Op.getOpcode() != ISD::SRA) {
18489 // Splat the shift amounts so the scalar shifts above will catch it.
18490 SDValue Amt0 = DAG.getVectorShuffle(VT, dl, Amt, Amt, {0, 0});
18491 SDValue Amt1 = DAG.getVectorShuffle(VT, dl, Amt, Amt, {1, 1});
18492 SDValue R0 = DAG.getNode(Op->getOpcode(), dl, VT, R, Amt0);
18493 SDValue R1 = DAG.getNode(Op->getOpcode(), dl, VT, R, Amt1);
18494 return DAG.getVectorShuffle(VT, dl, R0, R1, {0, 3});
18497 // i64 vector arithmetic shift can be emulated with the transform:
18498 // M = lshr(SIGN_BIT, Amt)
18499 // ashr(R, Amt) === sub(xor(lshr(R, Amt), M), M)
18500 if ((VT == MVT::v2i64 || (VT == MVT::v4i64 && Subtarget->hasInt256())) &&
18501 Op.getOpcode() == ISD::SRA) {
18502 SDValue S = DAG.getConstant(APInt::getSignBit(64), dl, VT);
18503 SDValue M = DAG.getNode(ISD::SRL, dl, VT, S, Amt);
18504 R = DAG.getNode(ISD::SRL, dl, VT, R, Amt);
18505 R = DAG.getNode(ISD::XOR, dl, VT, R, M);
18506 R = DAG.getNode(ISD::SUB, dl, VT, R, M);
18510 // If possible, lower this packed shift into a vector multiply instead of
18511 // expanding it into a sequence of scalar shifts.
18512 // Do this only if the vector shift count is a constant build_vector.
18513 if (Op.getOpcode() == ISD::SHL &&
18514 (VT == MVT::v8i16 || VT == MVT::v4i32 ||
18515 (Subtarget->hasInt256() && VT == MVT::v16i16)) &&
18516 ISD::isBuildVectorOfConstantSDNodes(Amt.getNode())) {
18517 SmallVector<SDValue, 8> Elts;
18518 MVT SVT = VT.getVectorElementType();
18519 unsigned SVTBits = SVT.getSizeInBits();
18520 APInt One(SVTBits, 1);
18521 unsigned NumElems = VT.getVectorNumElements();
18523 for (unsigned i=0; i !=NumElems; ++i) {
18524 SDValue Op = Amt->getOperand(i);
18525 if (Op->getOpcode() == ISD::UNDEF) {
18526 Elts.push_back(Op);
18530 ConstantSDNode *ND = cast<ConstantSDNode>(Op);
18531 APInt C(SVTBits, ND->getAPIntValue().getZExtValue());
18532 uint64_t ShAmt = C.getZExtValue();
18533 if (ShAmt >= SVTBits) {
18534 Elts.push_back(DAG.getUNDEF(SVT));
18537 Elts.push_back(DAG.getConstant(One.shl(ShAmt), dl, SVT));
18539 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Elts);
18540 return DAG.getNode(ISD::MUL, dl, VT, R, BV);
18543 // Lower SHL with variable shift amount.
18544 if (VT == MVT::v4i32 && Op->getOpcode() == ISD::SHL) {
18545 Op = DAG.getNode(ISD::SHL, dl, VT, Amt, DAG.getConstant(23, dl, VT));
18547 Op = DAG.getNode(ISD::ADD, dl, VT, Op,
18548 DAG.getConstant(0x3f800000U, dl, VT));
18549 Op = DAG.getBitcast(MVT::v4f32, Op);
18550 Op = DAG.getNode(ISD::FP_TO_SINT, dl, VT, Op);
18551 return DAG.getNode(ISD::MUL, dl, VT, Op, R);
18554 // If possible, lower this shift as a sequence of two shifts by
18555 // constant plus a MOVSS/MOVSD instead of scalarizing it.
18557 // (v4i32 (srl A, (build_vector < X, Y, Y, Y>)))
18559 // Could be rewritten as:
18560 // (v4i32 (MOVSS (srl A, <Y,Y,Y,Y>), (srl A, <X,X,X,X>)))
18562 // The advantage is that the two shifts from the example would be
18563 // lowered as X86ISD::VSRLI nodes. This would be cheaper than scalarizing
18564 // the vector shift into four scalar shifts plus four pairs of vector
18566 if ((VT == MVT::v8i16 || VT == MVT::v4i32) &&
18567 ISD::isBuildVectorOfConstantSDNodes(Amt.getNode())) {
18568 unsigned TargetOpcode = X86ISD::MOVSS;
18569 bool CanBeSimplified;
18570 // The splat value for the first packed shift (the 'X' from the example).
18571 SDValue Amt1 = Amt->getOperand(0);
18572 // The splat value for the second packed shift (the 'Y' from the example).
18573 SDValue Amt2 = (VT == MVT::v4i32) ? Amt->getOperand(1) :
18574 Amt->getOperand(2);
18576 // See if it is possible to replace this node with a sequence of
18577 // two shifts followed by a MOVSS/MOVSD
18578 if (VT == MVT::v4i32) {
18579 // Check if it is legal to use a MOVSS.
18580 CanBeSimplified = Amt2 == Amt->getOperand(2) &&
18581 Amt2 == Amt->getOperand(3);
18582 if (!CanBeSimplified) {
18583 // Otherwise, check if we can still simplify this node using a MOVSD.
18584 CanBeSimplified = Amt1 == Amt->getOperand(1) &&
18585 Amt->getOperand(2) == Amt->getOperand(3);
18586 TargetOpcode = X86ISD::MOVSD;
18587 Amt2 = Amt->getOperand(2);
18590 // Do similar checks for the case where the machine value type
18592 CanBeSimplified = Amt1 == Amt->getOperand(1);
18593 for (unsigned i=3; i != 8 && CanBeSimplified; ++i)
18594 CanBeSimplified = Amt2 == Amt->getOperand(i);
18596 if (!CanBeSimplified) {
18597 TargetOpcode = X86ISD::MOVSD;
18598 CanBeSimplified = true;
18599 Amt2 = Amt->getOperand(4);
18600 for (unsigned i=0; i != 4 && CanBeSimplified; ++i)
18601 CanBeSimplified = Amt1 == Amt->getOperand(i);
18602 for (unsigned j=4; j != 8 && CanBeSimplified; ++j)
18603 CanBeSimplified = Amt2 == Amt->getOperand(j);
18607 if (CanBeSimplified && isa<ConstantSDNode>(Amt1) &&
18608 isa<ConstantSDNode>(Amt2)) {
18609 // Replace this node with two shifts followed by a MOVSS/MOVSD.
18610 MVT CastVT = MVT::v4i32;
18612 DAG.getConstant(cast<ConstantSDNode>(Amt1)->getAPIntValue(), dl, VT);
18613 SDValue Shift1 = DAG.getNode(Op->getOpcode(), dl, VT, R, Splat1);
18615 DAG.getConstant(cast<ConstantSDNode>(Amt2)->getAPIntValue(), dl, VT);
18616 SDValue Shift2 = DAG.getNode(Op->getOpcode(), dl, VT, R, Splat2);
18617 if (TargetOpcode == X86ISD::MOVSD)
18618 CastVT = MVT::v2i64;
18619 SDValue BitCast1 = DAG.getBitcast(CastVT, Shift1);
18620 SDValue BitCast2 = DAG.getBitcast(CastVT, Shift2);
18621 SDValue Result = getTargetShuffleNode(TargetOpcode, dl, CastVT, BitCast2,
18623 return DAG.getBitcast(VT, Result);
18627 // v4i32 Non Uniform Shifts.
18628 // If the shift amount is constant we can shift each lane using the SSE2
18629 // immediate shifts, else we need to zero-extend each lane to the lower i64
18630 // and shift using the SSE2 variable shifts.
18631 // The separate results can then be blended together.
18632 if (VT == MVT::v4i32) {
18633 unsigned Opc = Op.getOpcode();
18634 SDValue Amt0, Amt1, Amt2, Amt3;
18635 if (ISD::isBuildVectorOfConstantSDNodes(Amt.getNode())) {
18636 Amt0 = DAG.getVectorShuffle(VT, dl, Amt, DAG.getUNDEF(VT), {0, 0, 0, 0});
18637 Amt1 = DAG.getVectorShuffle(VT, dl, Amt, DAG.getUNDEF(VT), {1, 1, 1, 1});
18638 Amt2 = DAG.getVectorShuffle(VT, dl, Amt, DAG.getUNDEF(VT), {2, 2, 2, 2});
18639 Amt3 = DAG.getVectorShuffle(VT, dl, Amt, DAG.getUNDEF(VT), {3, 3, 3, 3});
18641 // ISD::SHL is handled above but we include it here for completeness.
18644 llvm_unreachable("Unknown target vector shift node");
18646 Opc = X86ISD::VSHL;
18649 Opc = X86ISD::VSRL;
18652 Opc = X86ISD::VSRA;
18655 // The SSE2 shifts use the lower i64 as the same shift amount for
18656 // all lanes and the upper i64 is ignored. These shuffle masks
18657 // optimally zero-extend each lanes on SSE2/SSE41/AVX targets.
18658 SDValue Z = getZeroVector(VT, Subtarget, DAG, dl);
18659 Amt0 = DAG.getVectorShuffle(VT, dl, Amt, Z, {0, 4, -1, -1});
18660 Amt1 = DAG.getVectorShuffle(VT, dl, Amt, Z, {1, 5, -1, -1});
18661 Amt2 = DAG.getVectorShuffle(VT, dl, Amt, Z, {2, 6, -1, -1});
18662 Amt3 = DAG.getVectorShuffle(VT, dl, Amt, Z, {3, 7, -1, -1});
18665 SDValue R0 = DAG.getNode(Opc, dl, VT, R, Amt0);
18666 SDValue R1 = DAG.getNode(Opc, dl, VT, R, Amt1);
18667 SDValue R2 = DAG.getNode(Opc, dl, VT, R, Amt2);
18668 SDValue R3 = DAG.getNode(Opc, dl, VT, R, Amt3);
18669 SDValue R02 = DAG.getVectorShuffle(VT, dl, R0, R2, {0, -1, 6, -1});
18670 SDValue R13 = DAG.getVectorShuffle(VT, dl, R1, R3, {-1, 1, -1, 7});
18671 return DAG.getVectorShuffle(VT, dl, R02, R13, {0, 5, 2, 7});
18674 if (VT == MVT::v16i8 ||
18675 (VT == MVT::v32i8 && Subtarget->hasInt256() && !Subtarget->hasXOP())) {
18676 MVT ExtVT = MVT::getVectorVT(MVT::i16, VT.getVectorNumElements() / 2);
18677 unsigned ShiftOpcode = Op->getOpcode();
18679 auto SignBitSelect = [&](MVT SelVT, SDValue Sel, SDValue V0, SDValue V1) {
18680 // On SSE41 targets we make use of the fact that VSELECT lowers
18681 // to PBLENDVB which selects bytes based just on the sign bit.
18682 if (Subtarget->hasSSE41()) {
18683 V0 = DAG.getBitcast(VT, V0);
18684 V1 = DAG.getBitcast(VT, V1);
18685 Sel = DAG.getBitcast(VT, Sel);
18686 return DAG.getBitcast(SelVT,
18687 DAG.getNode(ISD::VSELECT, dl, VT, Sel, V0, V1));
18689 // On pre-SSE41 targets we test for the sign bit by comparing to
18690 // zero - a negative value will set all bits of the lanes to true
18691 // and VSELECT uses that in its OR(AND(V0,C),AND(V1,~C)) lowering.
18692 SDValue Z = getZeroVector(SelVT, Subtarget, DAG, dl);
18693 SDValue C = DAG.getNode(X86ISD::PCMPGT, dl, SelVT, Z, Sel);
18694 return DAG.getNode(ISD::VSELECT, dl, SelVT, C, V0, V1);
18697 // Turn 'a' into a mask suitable for VSELECT: a = a << 5;
18698 // We can safely do this using i16 shifts as we're only interested in
18699 // the 3 lower bits of each byte.
18700 Amt = DAG.getBitcast(ExtVT, Amt);
18701 Amt = DAG.getNode(ISD::SHL, dl, ExtVT, Amt, DAG.getConstant(5, dl, ExtVT));
18702 Amt = DAG.getBitcast(VT, Amt);
18704 if (Op->getOpcode() == ISD::SHL || Op->getOpcode() == ISD::SRL) {
18705 // r = VSELECT(r, shift(r, 4), a);
18707 DAG.getNode(ShiftOpcode, dl, VT, R, DAG.getConstant(4, dl, VT));
18708 R = SignBitSelect(VT, Amt, M, R);
18711 Amt = DAG.getNode(ISD::ADD, dl, VT, Amt, Amt);
18713 // r = VSELECT(r, shift(r, 2), a);
18714 M = DAG.getNode(ShiftOpcode, dl, VT, R, DAG.getConstant(2, dl, VT));
18715 R = SignBitSelect(VT, Amt, M, R);
18718 Amt = DAG.getNode(ISD::ADD, dl, VT, Amt, Amt);
18720 // return VSELECT(r, shift(r, 1), a);
18721 M = DAG.getNode(ShiftOpcode, dl, VT, R, DAG.getConstant(1, dl, VT));
18722 R = SignBitSelect(VT, Amt, M, R);
18726 if (Op->getOpcode() == ISD::SRA) {
18727 // For SRA we need to unpack each byte to the higher byte of a i16 vector
18728 // so we can correctly sign extend. We don't care what happens to the
18730 SDValue ALo = DAG.getNode(X86ISD::UNPCKL, dl, VT, DAG.getUNDEF(VT), Amt);
18731 SDValue AHi = DAG.getNode(X86ISD::UNPCKH, dl, VT, DAG.getUNDEF(VT), Amt);
18732 SDValue RLo = DAG.getNode(X86ISD::UNPCKL, dl, VT, DAG.getUNDEF(VT), R);
18733 SDValue RHi = DAG.getNode(X86ISD::UNPCKH, dl, VT, DAG.getUNDEF(VT), R);
18734 ALo = DAG.getBitcast(ExtVT, ALo);
18735 AHi = DAG.getBitcast(ExtVT, AHi);
18736 RLo = DAG.getBitcast(ExtVT, RLo);
18737 RHi = DAG.getBitcast(ExtVT, RHi);
18739 // r = VSELECT(r, shift(r, 4), a);
18740 SDValue MLo = DAG.getNode(ShiftOpcode, dl, ExtVT, RLo,
18741 DAG.getConstant(4, dl, ExtVT));
18742 SDValue MHi = DAG.getNode(ShiftOpcode, dl, ExtVT, RHi,
18743 DAG.getConstant(4, dl, ExtVT));
18744 RLo = SignBitSelect(ExtVT, ALo, MLo, RLo);
18745 RHi = SignBitSelect(ExtVT, AHi, MHi, RHi);
18748 ALo = DAG.getNode(ISD::ADD, dl, ExtVT, ALo, ALo);
18749 AHi = DAG.getNode(ISD::ADD, dl, ExtVT, AHi, AHi);
18751 // r = VSELECT(r, shift(r, 2), a);
18752 MLo = DAG.getNode(ShiftOpcode, dl, ExtVT, RLo,
18753 DAG.getConstant(2, dl, ExtVT));
18754 MHi = DAG.getNode(ShiftOpcode, dl, ExtVT, RHi,
18755 DAG.getConstant(2, dl, ExtVT));
18756 RLo = SignBitSelect(ExtVT, ALo, MLo, RLo);
18757 RHi = SignBitSelect(ExtVT, AHi, MHi, RHi);
18760 ALo = DAG.getNode(ISD::ADD, dl, ExtVT, ALo, ALo);
18761 AHi = DAG.getNode(ISD::ADD, dl, ExtVT, AHi, AHi);
18763 // r = VSELECT(r, shift(r, 1), a);
18764 MLo = DAG.getNode(ShiftOpcode, dl, ExtVT, RLo,
18765 DAG.getConstant(1, dl, ExtVT));
18766 MHi = DAG.getNode(ShiftOpcode, dl, ExtVT, RHi,
18767 DAG.getConstant(1, dl, ExtVT));
18768 RLo = SignBitSelect(ExtVT, ALo, MLo, RLo);
18769 RHi = SignBitSelect(ExtVT, AHi, MHi, RHi);
18771 // Logical shift the result back to the lower byte, leaving a zero upper
18773 // meaning that we can safely pack with PACKUSWB.
18775 DAG.getNode(ISD::SRL, dl, ExtVT, RLo, DAG.getConstant(8, dl, ExtVT));
18777 DAG.getNode(ISD::SRL, dl, ExtVT, RHi, DAG.getConstant(8, dl, ExtVT));
18778 return DAG.getNode(X86ISD::PACKUS, dl, VT, RLo, RHi);
18782 // It's worth extending once and using the v8i32 shifts for 16-bit types, but
18783 // the extra overheads to get from v16i8 to v8i32 make the existing SSE
18784 // solution better.
18785 if (Subtarget->hasInt256() && VT == MVT::v8i16) {
18786 MVT ExtVT = MVT::v8i32;
18788 Op.getOpcode() == ISD::SRA ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
18789 R = DAG.getNode(ExtOpc, dl, ExtVT, R);
18790 Amt = DAG.getNode(ISD::ANY_EXTEND, dl, ExtVT, Amt);
18791 return DAG.getNode(ISD::TRUNCATE, dl, VT,
18792 DAG.getNode(Op.getOpcode(), dl, ExtVT, R, Amt));
18795 if (Subtarget->hasInt256() && !Subtarget->hasXOP() && VT == MVT::v16i16) {
18796 MVT ExtVT = MVT::v8i32;
18797 SDValue Z = getZeroVector(VT, Subtarget, DAG, dl);
18798 SDValue ALo = DAG.getNode(X86ISD::UNPCKL, dl, VT, Amt, Z);
18799 SDValue AHi = DAG.getNode(X86ISD::UNPCKH, dl, VT, Amt, Z);
18800 SDValue RLo = DAG.getNode(X86ISD::UNPCKL, dl, VT, R, R);
18801 SDValue RHi = DAG.getNode(X86ISD::UNPCKH, dl, VT, R, R);
18802 ALo = DAG.getBitcast(ExtVT, ALo);
18803 AHi = DAG.getBitcast(ExtVT, AHi);
18804 RLo = DAG.getBitcast(ExtVT, RLo);
18805 RHi = DAG.getBitcast(ExtVT, RHi);
18806 SDValue Lo = DAG.getNode(Op.getOpcode(), dl, ExtVT, RLo, ALo);
18807 SDValue Hi = DAG.getNode(Op.getOpcode(), dl, ExtVT, RHi, AHi);
18808 Lo = DAG.getNode(ISD::SRL, dl, ExtVT, Lo, DAG.getConstant(16, dl, ExtVT));
18809 Hi = DAG.getNode(ISD::SRL, dl, ExtVT, Hi, DAG.getConstant(16, dl, ExtVT));
18810 return DAG.getNode(X86ISD::PACKUS, dl, VT, Lo, Hi);
18813 if (VT == MVT::v8i16) {
18814 unsigned ShiftOpcode = Op->getOpcode();
18816 auto SignBitSelect = [&](SDValue Sel, SDValue V0, SDValue V1) {
18817 // On SSE41 targets we make use of the fact that VSELECT lowers
18818 // to PBLENDVB which selects bytes based just on the sign bit.
18819 if (Subtarget->hasSSE41()) {
18820 MVT ExtVT = MVT::getVectorVT(MVT::i8, VT.getVectorNumElements() * 2);
18821 V0 = DAG.getBitcast(ExtVT, V0);
18822 V1 = DAG.getBitcast(ExtVT, V1);
18823 Sel = DAG.getBitcast(ExtVT, Sel);
18824 return DAG.getBitcast(
18825 VT, DAG.getNode(ISD::VSELECT, dl, ExtVT, Sel, V0, V1));
18827 // On pre-SSE41 targets we splat the sign bit - a negative value will
18828 // set all bits of the lanes to true and VSELECT uses that in
18829 // its OR(AND(V0,C),AND(V1,~C)) lowering.
18831 DAG.getNode(ISD::SRA, dl, VT, Sel, DAG.getConstant(15, dl, VT));
18832 return DAG.getNode(ISD::VSELECT, dl, VT, C, V0, V1);
18835 // Turn 'a' into a mask suitable for VSELECT: a = a << 12;
18836 if (Subtarget->hasSSE41()) {
18837 // On SSE41 targets we need to replicate the shift mask in both
18838 // bytes for PBLENDVB.
18841 DAG.getNode(ISD::SHL, dl, VT, Amt, DAG.getConstant(4, dl, VT)),
18842 DAG.getNode(ISD::SHL, dl, VT, Amt, DAG.getConstant(12, dl, VT)));
18844 Amt = DAG.getNode(ISD::SHL, dl, VT, Amt, DAG.getConstant(12, dl, VT));
18847 // r = VSELECT(r, shift(r, 8), a);
18848 SDValue M = DAG.getNode(ShiftOpcode, dl, VT, R, DAG.getConstant(8, dl, VT));
18849 R = SignBitSelect(Amt, M, R);
18852 Amt = DAG.getNode(ISD::ADD, dl, VT, Amt, Amt);
18854 // r = VSELECT(r, shift(r, 4), a);
18855 M = DAG.getNode(ShiftOpcode, dl, VT, R, DAG.getConstant(4, dl, VT));
18856 R = SignBitSelect(Amt, M, R);
18859 Amt = DAG.getNode(ISD::ADD, dl, VT, Amt, Amt);
18861 // r = VSELECT(r, shift(r, 2), a);
18862 M = DAG.getNode(ShiftOpcode, dl, VT, R, DAG.getConstant(2, dl, VT));
18863 R = SignBitSelect(Amt, M, R);
18866 Amt = DAG.getNode(ISD::ADD, dl, VT, Amt, Amt);
18868 // return VSELECT(r, shift(r, 1), a);
18869 M = DAG.getNode(ShiftOpcode, dl, VT, R, DAG.getConstant(1, dl, VT));
18870 R = SignBitSelect(Amt, M, R);
18874 // Decompose 256-bit shifts into smaller 128-bit shifts.
18875 if (VT.is256BitVector()) {
18876 unsigned NumElems = VT.getVectorNumElements();
18877 MVT EltVT = VT.getVectorElementType();
18878 MVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
18880 // Extract the two vectors
18881 SDValue V1 = Extract128BitVector(R, 0, DAG, dl);
18882 SDValue V2 = Extract128BitVector(R, NumElems/2, DAG, dl);
18884 // Recreate the shift amount vectors
18885 SDValue Amt1, Amt2;
18886 if (Amt.getOpcode() == ISD::BUILD_VECTOR) {
18887 // Constant shift amount
18888 SmallVector<SDValue, 8> Ops(Amt->op_begin(), Amt->op_begin() + NumElems);
18889 ArrayRef<SDValue> Amt1Csts = makeArrayRef(Ops).slice(0, NumElems / 2);
18890 ArrayRef<SDValue> Amt2Csts = makeArrayRef(Ops).slice(NumElems / 2);
18892 Amt1 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, Amt1Csts);
18893 Amt2 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, Amt2Csts);
18895 // Variable shift amount
18896 Amt1 = Extract128BitVector(Amt, 0, DAG, dl);
18897 Amt2 = Extract128BitVector(Amt, NumElems/2, DAG, dl);
18900 // Issue new vector shifts for the smaller types
18901 V1 = DAG.getNode(Op.getOpcode(), dl, NewVT, V1, Amt1);
18902 V2 = DAG.getNode(Op.getOpcode(), dl, NewVT, V2, Amt2);
18904 // Concatenate the result back
18905 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, V1, V2);
18911 static SDValue LowerRotate(SDValue Op, const X86Subtarget *Subtarget,
18912 SelectionDAG &DAG) {
18913 MVT VT = Op.getSimpleValueType();
18915 SDValue R = Op.getOperand(0);
18916 SDValue Amt = Op.getOperand(1);
18918 assert(VT.isVector() && "Custom lowering only for vector rotates!");
18919 assert(Subtarget->hasXOP() && "XOP support required for vector rotates!");
18920 assert((Op.getOpcode() == ISD::ROTL) && "Only ROTL supported");
18922 // XOP has 128-bit vector variable + immediate rotates.
18923 // +ve/-ve Amt = rotate left/right.
18925 // Split 256-bit integers.
18926 if (VT.is256BitVector())
18927 return Lower256IntArith(Op, DAG);
18929 assert(VT.is128BitVector() && "Only rotate 128-bit vectors!");
18931 // Attempt to rotate by immediate.
18932 if (auto *BVAmt = dyn_cast<BuildVectorSDNode>(Amt)) {
18933 if (auto *RotateConst = BVAmt->getConstantSplatNode()) {
18934 uint64_t RotateAmt = RotateConst->getAPIntValue().getZExtValue();
18935 assert(RotateAmt < VT.getScalarSizeInBits() && "Rotation out of range");
18936 return DAG.getNode(X86ISD::VPROTI, DL, VT, R,
18937 DAG.getConstant(RotateAmt, DL, MVT::i8));
18941 // Use general rotate by variable (per-element).
18942 return DAG.getNode(X86ISD::VPROT, DL, VT, R, Amt);
18945 static SDValue LowerXALUO(SDValue Op, SelectionDAG &DAG) {
18946 // Lower the "add/sub/mul with overflow" instruction into a regular ins plus
18947 // a "setcc" instruction that checks the overflow flag. The "brcond" lowering
18948 // looks for this combo and may remove the "setcc" instruction if the "setcc"
18949 // has only one use.
18950 SDNode *N = Op.getNode();
18951 SDValue LHS = N->getOperand(0);
18952 SDValue RHS = N->getOperand(1);
18953 unsigned BaseOp = 0;
18956 switch (Op.getOpcode()) {
18957 default: llvm_unreachable("Unknown ovf instruction!");
18959 // A subtract of one will be selected as a INC. Note that INC doesn't
18960 // set CF, so we can't do this for UADDO.
18961 if (isOneConstant(RHS)) {
18962 BaseOp = X86ISD::INC;
18963 Cond = X86::COND_O;
18966 BaseOp = X86ISD::ADD;
18967 Cond = X86::COND_O;
18970 BaseOp = X86ISD::ADD;
18971 Cond = X86::COND_B;
18974 // A subtract of one will be selected as a DEC. Note that DEC doesn't
18975 // set CF, so we can't do this for USUBO.
18976 if (isOneConstant(RHS)) {
18977 BaseOp = X86ISD::DEC;
18978 Cond = X86::COND_O;
18981 BaseOp = X86ISD::SUB;
18982 Cond = X86::COND_O;
18985 BaseOp = X86ISD::SUB;
18986 Cond = X86::COND_B;
18989 BaseOp = N->getValueType(0) == MVT::i8 ? X86ISD::SMUL8 : X86ISD::SMUL;
18990 Cond = X86::COND_O;
18992 case ISD::UMULO: { // i64, i8 = umulo lhs, rhs --> i64, i64, i32 umul lhs,rhs
18993 if (N->getValueType(0) == MVT::i8) {
18994 BaseOp = X86ISD::UMUL8;
18995 Cond = X86::COND_O;
18998 SDVTList VTs = DAG.getVTList(N->getValueType(0), N->getValueType(0),
19000 SDValue Sum = DAG.getNode(X86ISD::UMUL, DL, VTs, LHS, RHS);
19003 DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
19004 DAG.getConstant(X86::COND_O, DL, MVT::i32),
19005 SDValue(Sum.getNode(), 2));
19007 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
19011 // Also sets EFLAGS.
19012 SDVTList VTs = DAG.getVTList(N->getValueType(0), MVT::i32);
19013 SDValue Sum = DAG.getNode(BaseOp, DL, VTs, LHS, RHS);
19016 DAG.getNode(X86ISD::SETCC, DL, N->getValueType(1),
19017 DAG.getConstant(Cond, DL, MVT::i32),
19018 SDValue(Sum.getNode(), 1));
19020 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
19023 /// Returns true if the operand type is exactly twice the native width, and
19024 /// the corresponding cmpxchg8b or cmpxchg16b instruction is available.
19025 /// Used to know whether to use cmpxchg8/16b when expanding atomic operations
19026 /// (otherwise we leave them alone to become __sync_fetch_and_... calls).
19027 bool X86TargetLowering::needsCmpXchgNb(Type *MemType) const {
19028 unsigned OpWidth = MemType->getPrimitiveSizeInBits();
19031 return !Subtarget->is64Bit(); // FIXME this should be Subtarget.hasCmpxchg8b
19032 else if (OpWidth == 128)
19033 return Subtarget->hasCmpxchg16b();
19038 bool X86TargetLowering::shouldExpandAtomicStoreInIR(StoreInst *SI) const {
19039 return needsCmpXchgNb(SI->getValueOperand()->getType());
19042 // Note: this turns large loads into lock cmpxchg8b/16b.
19043 // FIXME: On 32 bits x86, fild/movq might be faster than lock cmpxchg8b.
19044 TargetLowering::AtomicExpansionKind
19045 X86TargetLowering::shouldExpandAtomicLoadInIR(LoadInst *LI) const {
19046 auto PTy = cast<PointerType>(LI->getPointerOperand()->getType());
19047 return needsCmpXchgNb(PTy->getElementType()) ? AtomicExpansionKind::CmpXChg
19048 : AtomicExpansionKind::None;
19051 TargetLowering::AtomicExpansionKind
19052 X86TargetLowering::shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const {
19053 unsigned NativeWidth = Subtarget->is64Bit() ? 64 : 32;
19054 Type *MemType = AI->getType();
19056 // If the operand is too big, we must see if cmpxchg8/16b is available
19057 // and default to library calls otherwise.
19058 if (MemType->getPrimitiveSizeInBits() > NativeWidth) {
19059 return needsCmpXchgNb(MemType) ? AtomicExpansionKind::CmpXChg
19060 : AtomicExpansionKind::None;
19063 AtomicRMWInst::BinOp Op = AI->getOperation();
19066 llvm_unreachable("Unknown atomic operation");
19067 case AtomicRMWInst::Xchg:
19068 case AtomicRMWInst::Add:
19069 case AtomicRMWInst::Sub:
19070 // It's better to use xadd, xsub or xchg for these in all cases.
19071 return AtomicExpansionKind::None;
19072 case AtomicRMWInst::Or:
19073 case AtomicRMWInst::And:
19074 case AtomicRMWInst::Xor:
19075 // If the atomicrmw's result isn't actually used, we can just add a "lock"
19076 // prefix to a normal instruction for these operations.
19077 return !AI->use_empty() ? AtomicExpansionKind::CmpXChg
19078 : AtomicExpansionKind::None;
19079 case AtomicRMWInst::Nand:
19080 case AtomicRMWInst::Max:
19081 case AtomicRMWInst::Min:
19082 case AtomicRMWInst::UMax:
19083 case AtomicRMWInst::UMin:
19084 // These always require a non-trivial set of data operations on x86. We must
19085 // use a cmpxchg loop.
19086 return AtomicExpansionKind::CmpXChg;
19090 static bool hasMFENCE(const X86Subtarget& Subtarget) {
19091 // Use mfence if we have SSE2 or we're on x86-64 (even if we asked for
19092 // no-sse2). There isn't any reason to disable it if the target processor
19094 return Subtarget.hasSSE2() || Subtarget.is64Bit();
19098 X86TargetLowering::lowerIdempotentRMWIntoFencedLoad(AtomicRMWInst *AI) const {
19099 unsigned NativeWidth = Subtarget->is64Bit() ? 64 : 32;
19100 Type *MemType = AI->getType();
19101 // Accesses larger than the native width are turned into cmpxchg/libcalls, so
19102 // there is no benefit in turning such RMWs into loads, and it is actually
19103 // harmful as it introduces a mfence.
19104 if (MemType->getPrimitiveSizeInBits() > NativeWidth)
19107 auto Builder = IRBuilder<>(AI);
19108 Module *M = Builder.GetInsertBlock()->getParent()->getParent();
19109 auto SynchScope = AI->getSynchScope();
19110 // We must restrict the ordering to avoid generating loads with Release or
19111 // ReleaseAcquire orderings.
19112 auto Order = AtomicCmpXchgInst::getStrongestFailureOrdering(AI->getOrdering());
19113 auto Ptr = AI->getPointerOperand();
19115 // Before the load we need a fence. Here is an example lifted from
19116 // http://www.hpl.hp.com/techreports/2012/HPL-2012-68.pdf showing why a fence
19119 // x.store(1, relaxed);
19120 // r1 = y.fetch_add(0, release);
19122 // y.fetch_add(42, acquire);
19123 // r2 = x.load(relaxed);
19124 // r1 = r2 = 0 is impossible, but becomes possible if the idempotent rmw is
19125 // lowered to just a load without a fence. A mfence flushes the store buffer,
19126 // making the optimization clearly correct.
19127 // FIXME: it is required if isAtLeastRelease(Order) but it is not clear
19128 // otherwise, we might be able to be more aggressive on relaxed idempotent
19129 // rmw. In practice, they do not look useful, so we don't try to be
19130 // especially clever.
19131 if (SynchScope == SingleThread)
19132 // FIXME: we could just insert an X86ISD::MEMBARRIER here, except we are at
19133 // the IR level, so we must wrap it in an intrinsic.
19136 if (!hasMFENCE(*Subtarget))
19137 // FIXME: it might make sense to use a locked operation here but on a
19138 // different cache-line to prevent cache-line bouncing. In practice it
19139 // is probably a small win, and x86 processors without mfence are rare
19140 // enough that we do not bother.
19144 llvm::Intrinsic::getDeclaration(M, Intrinsic::x86_sse2_mfence);
19145 Builder.CreateCall(MFence, {});
19147 // Finally we can emit the atomic load.
19148 LoadInst *Loaded = Builder.CreateAlignedLoad(Ptr,
19149 AI->getType()->getPrimitiveSizeInBits());
19150 Loaded->setAtomic(Order, SynchScope);
19151 AI->replaceAllUsesWith(Loaded);
19152 AI->eraseFromParent();
19156 static SDValue LowerATOMIC_FENCE(SDValue Op, const X86Subtarget *Subtarget,
19157 SelectionDAG &DAG) {
19159 AtomicOrdering FenceOrdering = static_cast<AtomicOrdering>(
19160 cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue());
19161 SynchronizationScope FenceScope = static_cast<SynchronizationScope>(
19162 cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue());
19164 // The only fence that needs an instruction is a sequentially-consistent
19165 // cross-thread fence.
19166 if (FenceOrdering == SequentiallyConsistent && FenceScope == CrossThread) {
19167 if (hasMFENCE(*Subtarget))
19168 return DAG.getNode(X86ISD::MFENCE, dl, MVT::Other, Op.getOperand(0));
19170 SDValue Chain = Op.getOperand(0);
19171 SDValue Zero = DAG.getConstant(0, dl, MVT::i32);
19173 DAG.getRegister(X86::ESP, MVT::i32), // Base
19174 DAG.getTargetConstant(1, dl, MVT::i8), // Scale
19175 DAG.getRegister(0, MVT::i32), // Index
19176 DAG.getTargetConstant(0, dl, MVT::i32), // Disp
19177 DAG.getRegister(0, MVT::i32), // Segment.
19181 SDNode *Res = DAG.getMachineNode(X86::OR32mrLocked, dl, MVT::Other, Ops);
19182 return SDValue(Res, 0);
19185 // MEMBARRIER is a compiler barrier; it codegens to a no-op.
19186 return DAG.getNode(X86ISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0));
19189 static SDValue LowerCMP_SWAP(SDValue Op, const X86Subtarget *Subtarget,
19190 SelectionDAG &DAG) {
19191 MVT T = Op.getSimpleValueType();
19195 switch(T.SimpleTy) {
19196 default: llvm_unreachable("Invalid value type!");
19197 case MVT::i8: Reg = X86::AL; size = 1; break;
19198 case MVT::i16: Reg = X86::AX; size = 2; break;
19199 case MVT::i32: Reg = X86::EAX; size = 4; break;
19201 assert(Subtarget->is64Bit() && "Node not type legal!");
19202 Reg = X86::RAX; size = 8;
19205 SDValue cpIn = DAG.getCopyToReg(Op.getOperand(0), DL, Reg,
19206 Op.getOperand(2), SDValue());
19207 SDValue Ops[] = { cpIn.getValue(0),
19210 DAG.getTargetConstant(size, DL, MVT::i8),
19211 cpIn.getValue(1) };
19212 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
19213 MachineMemOperand *MMO = cast<AtomicSDNode>(Op)->getMemOperand();
19214 SDValue Result = DAG.getMemIntrinsicNode(X86ISD::LCMPXCHG_DAG, DL, Tys,
19218 DAG.getCopyFromReg(Result.getValue(0), DL, Reg, T, Result.getValue(1));
19219 SDValue EFLAGS = DAG.getCopyFromReg(cpOut.getValue(1), DL, X86::EFLAGS,
19220 MVT::i32, cpOut.getValue(2));
19221 SDValue Success = DAG.getNode(X86ISD::SETCC, DL, Op->getValueType(1),
19222 DAG.getConstant(X86::COND_E, DL, MVT::i8),
19225 DAG.ReplaceAllUsesOfValueWith(Op.getValue(0), cpOut);
19226 DAG.ReplaceAllUsesOfValueWith(Op.getValue(1), Success);
19227 DAG.ReplaceAllUsesOfValueWith(Op.getValue(2), EFLAGS.getValue(1));
19231 static SDValue LowerBITCAST(SDValue Op, const X86Subtarget *Subtarget,
19232 SelectionDAG &DAG) {
19233 MVT SrcVT = Op.getOperand(0).getSimpleValueType();
19234 MVT DstVT = Op.getSimpleValueType();
19236 if (SrcVT == MVT::v2i32 || SrcVT == MVT::v4i16 || SrcVT == MVT::v8i8) {
19237 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
19238 if (DstVT != MVT::f64)
19239 // This conversion needs to be expanded.
19242 SDValue InVec = Op->getOperand(0);
19244 unsigned NumElts = SrcVT.getVectorNumElements();
19245 MVT SVT = SrcVT.getVectorElementType();
19247 // Widen the vector in input in the case of MVT::v2i32.
19248 // Example: from MVT::v2i32 to MVT::v4i32.
19249 SmallVector<SDValue, 16> Elts;
19250 for (unsigned i = 0, e = NumElts; i != e; ++i)
19251 Elts.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, SVT, InVec,
19252 DAG.getIntPtrConstant(i, dl)));
19254 // Explicitly mark the extra elements as Undef.
19255 Elts.append(NumElts, DAG.getUNDEF(SVT));
19257 EVT NewVT = EVT::getVectorVT(*DAG.getContext(), SVT, NumElts * 2);
19258 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, Elts);
19259 SDValue ToV2F64 = DAG.getBitcast(MVT::v2f64, BV);
19260 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, ToV2F64,
19261 DAG.getIntPtrConstant(0, dl));
19264 assert(Subtarget->is64Bit() && !Subtarget->hasSSE2() &&
19265 Subtarget->hasMMX() && "Unexpected custom BITCAST");
19266 assert((DstVT == MVT::i64 ||
19267 (DstVT.isVector() && DstVT.getSizeInBits()==64)) &&
19268 "Unexpected custom BITCAST");
19269 // i64 <=> MMX conversions are Legal.
19270 if (SrcVT==MVT::i64 && DstVT.isVector())
19272 if (DstVT==MVT::i64 && SrcVT.isVector())
19274 // MMX <=> MMX conversions are Legal.
19275 if (SrcVT.isVector() && DstVT.isVector())
19277 // All other conversions need to be expanded.
19281 /// Compute the horizontal sum of bytes in V for the elements of VT.
19283 /// Requires V to be a byte vector and VT to be an integer vector type with
19284 /// wider elements than V's type. The width of the elements of VT determines
19285 /// how many bytes of V are summed horizontally to produce each element of the
19287 static SDValue LowerHorizontalByteSum(SDValue V, MVT VT,
19288 const X86Subtarget *Subtarget,
19289 SelectionDAG &DAG) {
19291 MVT ByteVecVT = V.getSimpleValueType();
19292 MVT EltVT = VT.getVectorElementType();
19293 int NumElts = VT.getVectorNumElements();
19294 assert(ByteVecVT.getVectorElementType() == MVT::i8 &&
19295 "Expected value to have byte element type.");
19296 assert(EltVT != MVT::i8 &&
19297 "Horizontal byte sum only makes sense for wider elements!");
19298 unsigned VecSize = VT.getSizeInBits();
19299 assert(ByteVecVT.getSizeInBits() == VecSize && "Cannot change vector size!");
19301 // PSADBW instruction horizontally add all bytes and leave the result in i64
19302 // chunks, thus directly computes the pop count for v2i64 and v4i64.
19303 if (EltVT == MVT::i64) {
19304 SDValue Zeros = getZeroVector(ByteVecVT, Subtarget, DAG, DL);
19305 MVT SadVecVT = MVT::getVectorVT(MVT::i64, VecSize / 64);
19306 V = DAG.getNode(X86ISD::PSADBW, DL, SadVecVT, V, Zeros);
19307 return DAG.getBitcast(VT, V);
19310 if (EltVT == MVT::i32) {
19311 // We unpack the low half and high half into i32s interleaved with zeros so
19312 // that we can use PSADBW to horizontally sum them. The most useful part of
19313 // this is that it lines up the results of two PSADBW instructions to be
19314 // two v2i64 vectors which concatenated are the 4 population counts. We can
19315 // then use PACKUSWB to shrink and concatenate them into a v4i32 again.
19316 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, DL);
19317 SDValue Low = DAG.getNode(X86ISD::UNPCKL, DL, VT, V, Zeros);
19318 SDValue High = DAG.getNode(X86ISD::UNPCKH, DL, VT, V, Zeros);
19320 // Do the horizontal sums into two v2i64s.
19321 Zeros = getZeroVector(ByteVecVT, Subtarget, DAG, DL);
19322 MVT SadVecVT = MVT::getVectorVT(MVT::i64, VecSize / 64);
19323 Low = DAG.getNode(X86ISD::PSADBW, DL, SadVecVT,
19324 DAG.getBitcast(ByteVecVT, Low), Zeros);
19325 High = DAG.getNode(X86ISD::PSADBW, DL, SadVecVT,
19326 DAG.getBitcast(ByteVecVT, High), Zeros);
19328 // Merge them together.
19329 MVT ShortVecVT = MVT::getVectorVT(MVT::i16, VecSize / 16);
19330 V = DAG.getNode(X86ISD::PACKUS, DL, ByteVecVT,
19331 DAG.getBitcast(ShortVecVT, Low),
19332 DAG.getBitcast(ShortVecVT, High));
19334 return DAG.getBitcast(VT, V);
19337 // The only element type left is i16.
19338 assert(EltVT == MVT::i16 && "Unknown how to handle type");
19340 // To obtain pop count for each i16 element starting from the pop count for
19341 // i8 elements, shift the i16s left by 8, sum as i8s, and then shift as i16s
19342 // right by 8. It is important to shift as i16s as i8 vector shift isn't
19343 // directly supported.
19344 SmallVector<SDValue, 16> Shifters(NumElts, DAG.getConstant(8, DL, EltVT));
19345 SDValue Shifter = DAG.getNode(ISD::BUILD_VECTOR, DL, VT, Shifters);
19346 SDValue Shl = DAG.getNode(ISD::SHL, DL, VT, DAG.getBitcast(VT, V), Shifter);
19347 V = DAG.getNode(ISD::ADD, DL, ByteVecVT, DAG.getBitcast(ByteVecVT, Shl),
19348 DAG.getBitcast(ByteVecVT, V));
19349 return DAG.getNode(ISD::SRL, DL, VT, DAG.getBitcast(VT, V), Shifter);
19352 static SDValue LowerVectorCTPOPInRegLUT(SDValue Op, SDLoc DL,
19353 const X86Subtarget *Subtarget,
19354 SelectionDAG &DAG) {
19355 MVT VT = Op.getSimpleValueType();
19356 MVT EltVT = VT.getVectorElementType();
19357 unsigned VecSize = VT.getSizeInBits();
19359 // Implement a lookup table in register by using an algorithm based on:
19360 // http://wm.ite.pl/articles/sse-popcount.html
19362 // The general idea is that every lower byte nibble in the input vector is an
19363 // index into a in-register pre-computed pop count table. We then split up the
19364 // input vector in two new ones: (1) a vector with only the shifted-right
19365 // higher nibbles for each byte and (2) a vector with the lower nibbles (and
19366 // masked out higher ones) for each byte. PSHUB is used separately with both
19367 // to index the in-register table. Next, both are added and the result is a
19368 // i8 vector where each element contains the pop count for input byte.
19370 // To obtain the pop count for elements != i8, we follow up with the same
19371 // approach and use additional tricks as described below.
19373 const int LUT[16] = {/* 0 */ 0, /* 1 */ 1, /* 2 */ 1, /* 3 */ 2,
19374 /* 4 */ 1, /* 5 */ 2, /* 6 */ 2, /* 7 */ 3,
19375 /* 8 */ 1, /* 9 */ 2, /* a */ 2, /* b */ 3,
19376 /* c */ 2, /* d */ 3, /* e */ 3, /* f */ 4};
19378 int NumByteElts = VecSize / 8;
19379 MVT ByteVecVT = MVT::getVectorVT(MVT::i8, NumByteElts);
19380 SDValue In = DAG.getBitcast(ByteVecVT, Op);
19381 SmallVector<SDValue, 16> LUTVec;
19382 for (int i = 0; i < NumByteElts; ++i)
19383 LUTVec.push_back(DAG.getConstant(LUT[i % 16], DL, MVT::i8));
19384 SDValue InRegLUT = DAG.getNode(ISD::BUILD_VECTOR, DL, ByteVecVT, LUTVec);
19385 SmallVector<SDValue, 16> Mask0F(NumByteElts,
19386 DAG.getConstant(0x0F, DL, MVT::i8));
19387 SDValue M0F = DAG.getNode(ISD::BUILD_VECTOR, DL, ByteVecVT, Mask0F);
19390 SmallVector<SDValue, 16> Four(NumByteElts, DAG.getConstant(4, DL, MVT::i8));
19391 SDValue FourV = DAG.getNode(ISD::BUILD_VECTOR, DL, ByteVecVT, Four);
19392 SDValue HighNibbles = DAG.getNode(ISD::SRL, DL, ByteVecVT, In, FourV);
19395 SDValue LowNibbles = DAG.getNode(ISD::AND, DL, ByteVecVT, In, M0F);
19397 // The input vector is used as the shuffle mask that index elements into the
19398 // LUT. After counting low and high nibbles, add the vector to obtain the
19399 // final pop count per i8 element.
19400 SDValue HighPopCnt =
19401 DAG.getNode(X86ISD::PSHUFB, DL, ByteVecVT, InRegLUT, HighNibbles);
19402 SDValue LowPopCnt =
19403 DAG.getNode(X86ISD::PSHUFB, DL, ByteVecVT, InRegLUT, LowNibbles);
19404 SDValue PopCnt = DAG.getNode(ISD::ADD, DL, ByteVecVT, HighPopCnt, LowPopCnt);
19406 if (EltVT == MVT::i8)
19409 return LowerHorizontalByteSum(PopCnt, VT, Subtarget, DAG);
19412 static SDValue LowerVectorCTPOPBitmath(SDValue Op, SDLoc DL,
19413 const X86Subtarget *Subtarget,
19414 SelectionDAG &DAG) {
19415 MVT VT = Op.getSimpleValueType();
19416 assert(VT.is128BitVector() &&
19417 "Only 128-bit vector bitmath lowering supported.");
19419 int VecSize = VT.getSizeInBits();
19420 MVT EltVT = VT.getVectorElementType();
19421 int Len = EltVT.getSizeInBits();
19423 // This is the vectorized version of the "best" algorithm from
19424 // http://graphics.stanford.edu/~seander/bithacks.html#CountBitsSetParallel
19425 // with a minor tweak to use a series of adds + shifts instead of vector
19426 // multiplications. Implemented for all integer vector types. We only use
19427 // this when we don't have SSSE3 which allows a LUT-based lowering that is
19428 // much faster, even faster than using native popcnt instructions.
19430 auto GetShift = [&](unsigned OpCode, SDValue V, int Shifter) {
19431 MVT VT = V.getSimpleValueType();
19432 SmallVector<SDValue, 32> Shifters(
19433 VT.getVectorNumElements(),
19434 DAG.getConstant(Shifter, DL, VT.getVectorElementType()));
19435 return DAG.getNode(OpCode, DL, VT, V,
19436 DAG.getNode(ISD::BUILD_VECTOR, DL, VT, Shifters));
19438 auto GetMask = [&](SDValue V, APInt Mask) {
19439 MVT VT = V.getSimpleValueType();
19440 SmallVector<SDValue, 32> Masks(
19441 VT.getVectorNumElements(),
19442 DAG.getConstant(Mask, DL, VT.getVectorElementType()));
19443 return DAG.getNode(ISD::AND, DL, VT, V,
19444 DAG.getNode(ISD::BUILD_VECTOR, DL, VT, Masks));
19447 // We don't want to incur the implicit masks required to SRL vNi8 vectors on
19448 // x86, so set the SRL type to have elements at least i16 wide. This is
19449 // correct because all of our SRLs are followed immediately by a mask anyways
19450 // that handles any bits that sneak into the high bits of the byte elements.
19451 MVT SrlVT = Len > 8 ? VT : MVT::getVectorVT(MVT::i16, VecSize / 16);
19455 // v = v - ((v >> 1) & 0x55555555...)
19457 DAG.getBitcast(VT, GetShift(ISD::SRL, DAG.getBitcast(SrlVT, V), 1));
19458 SDValue And = GetMask(Srl, APInt::getSplat(Len, APInt(8, 0x55)));
19459 V = DAG.getNode(ISD::SUB, DL, VT, V, And);
19461 // v = (v & 0x33333333...) + ((v >> 2) & 0x33333333...)
19462 SDValue AndLHS = GetMask(V, APInt::getSplat(Len, APInt(8, 0x33)));
19463 Srl = DAG.getBitcast(VT, GetShift(ISD::SRL, DAG.getBitcast(SrlVT, V), 2));
19464 SDValue AndRHS = GetMask(Srl, APInt::getSplat(Len, APInt(8, 0x33)));
19465 V = DAG.getNode(ISD::ADD, DL, VT, AndLHS, AndRHS);
19467 // v = (v + (v >> 4)) & 0x0F0F0F0F...
19468 Srl = DAG.getBitcast(VT, GetShift(ISD::SRL, DAG.getBitcast(SrlVT, V), 4));
19469 SDValue Add = DAG.getNode(ISD::ADD, DL, VT, V, Srl);
19470 V = GetMask(Add, APInt::getSplat(Len, APInt(8, 0x0F)));
19472 // At this point, V contains the byte-wise population count, and we are
19473 // merely doing a horizontal sum if necessary to get the wider element
19475 if (EltVT == MVT::i8)
19478 return LowerHorizontalByteSum(
19479 DAG.getBitcast(MVT::getVectorVT(MVT::i8, VecSize / 8), V), VT, Subtarget,
19483 static SDValue LowerVectorCTPOP(SDValue Op, const X86Subtarget *Subtarget,
19484 SelectionDAG &DAG) {
19485 MVT VT = Op.getSimpleValueType();
19486 // FIXME: Need to add AVX-512 support here!
19487 assert((VT.is256BitVector() || VT.is128BitVector()) &&
19488 "Unknown CTPOP type to handle");
19489 SDLoc DL(Op.getNode());
19490 SDValue Op0 = Op.getOperand(0);
19492 if (!Subtarget->hasSSSE3()) {
19493 // We can't use the fast LUT approach, so fall back on vectorized bitmath.
19494 assert(VT.is128BitVector() && "Only 128-bit vectors supported in SSE!");
19495 return LowerVectorCTPOPBitmath(Op0, DL, Subtarget, DAG);
19498 if (VT.is256BitVector() && !Subtarget->hasInt256()) {
19499 unsigned NumElems = VT.getVectorNumElements();
19501 // Extract each 128-bit vector, compute pop count and concat the result.
19502 SDValue LHS = Extract128BitVector(Op0, 0, DAG, DL);
19503 SDValue RHS = Extract128BitVector(Op0, NumElems/2, DAG, DL);
19505 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT,
19506 LowerVectorCTPOPInRegLUT(LHS, DL, Subtarget, DAG),
19507 LowerVectorCTPOPInRegLUT(RHS, DL, Subtarget, DAG));
19510 return LowerVectorCTPOPInRegLUT(Op0, DL, Subtarget, DAG);
19513 static SDValue LowerCTPOP(SDValue Op, const X86Subtarget *Subtarget,
19514 SelectionDAG &DAG) {
19515 assert(Op.getSimpleValueType().isVector() &&
19516 "We only do custom lowering for vector population count.");
19517 return LowerVectorCTPOP(Op, Subtarget, DAG);
19520 static SDValue LowerLOAD_SUB(SDValue Op, SelectionDAG &DAG) {
19521 SDNode *Node = Op.getNode();
19523 EVT T = Node->getValueType(0);
19524 SDValue negOp = DAG.getNode(ISD::SUB, dl, T,
19525 DAG.getConstant(0, dl, T), Node->getOperand(2));
19526 return DAG.getAtomic(ISD::ATOMIC_LOAD_ADD, dl,
19527 cast<AtomicSDNode>(Node)->getMemoryVT(),
19528 Node->getOperand(0),
19529 Node->getOperand(1), negOp,
19530 cast<AtomicSDNode>(Node)->getMemOperand(),
19531 cast<AtomicSDNode>(Node)->getOrdering(),
19532 cast<AtomicSDNode>(Node)->getSynchScope());
19535 static SDValue LowerATOMIC_STORE(SDValue Op, SelectionDAG &DAG) {
19536 SDNode *Node = Op.getNode();
19538 EVT VT = cast<AtomicSDNode>(Node)->getMemoryVT();
19540 // Convert seq_cst store -> xchg
19541 // Convert wide store -> swap (-> cmpxchg8b/cmpxchg16b)
19542 // FIXME: On 32-bit, store -> fist or movq would be more efficient
19543 // (The only way to get a 16-byte store is cmpxchg16b)
19544 // FIXME: 16-byte ATOMIC_SWAP isn't actually hooked up at the moment.
19545 if (cast<AtomicSDNode>(Node)->getOrdering() == SequentiallyConsistent ||
19546 !DAG.getTargetLoweringInfo().isTypeLegal(VT)) {
19547 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_SWAP, dl,
19548 cast<AtomicSDNode>(Node)->getMemoryVT(),
19549 Node->getOperand(0),
19550 Node->getOperand(1), Node->getOperand(2),
19551 cast<AtomicSDNode>(Node)->getMemOperand(),
19552 cast<AtomicSDNode>(Node)->getOrdering(),
19553 cast<AtomicSDNode>(Node)->getSynchScope());
19554 return Swap.getValue(1);
19556 // Other atomic stores have a simple pattern.
19560 static SDValue LowerADDC_ADDE_SUBC_SUBE(SDValue Op, SelectionDAG &DAG) {
19561 MVT VT = Op.getNode()->getSimpleValueType(0);
19563 // Let legalize expand this if it isn't a legal type yet.
19564 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
19567 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
19570 bool ExtraOp = false;
19571 switch (Op.getOpcode()) {
19572 default: llvm_unreachable("Invalid code");
19573 case ISD::ADDC: Opc = X86ISD::ADD; break;
19574 case ISD::ADDE: Opc = X86ISD::ADC; ExtraOp = true; break;
19575 case ISD::SUBC: Opc = X86ISD::SUB; break;
19576 case ISD::SUBE: Opc = X86ISD::SBB; ExtraOp = true; break;
19580 return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0),
19582 return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0),
19583 Op.getOperand(1), Op.getOperand(2));
19586 static SDValue LowerFSINCOS(SDValue Op, const X86Subtarget *Subtarget,
19587 SelectionDAG &DAG) {
19588 assert(Subtarget->isTargetDarwin() && Subtarget->is64Bit());
19590 // For MacOSX, we want to call an alternative entry point: __sincos_stret,
19591 // which returns the values as { float, float } (in XMM0) or
19592 // { double, double } (which is returned in XMM0, XMM1).
19594 SDValue Arg = Op.getOperand(0);
19595 EVT ArgVT = Arg.getValueType();
19596 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
19598 TargetLowering::ArgListTy Args;
19599 TargetLowering::ArgListEntry Entry;
19603 Entry.isSExt = false;
19604 Entry.isZExt = false;
19605 Args.push_back(Entry);
19607 bool isF64 = ArgVT == MVT::f64;
19608 // Only optimize x86_64 for now. i386 is a bit messy. For f32,
19609 // the small struct {f32, f32} is returned in (eax, edx). For f64,
19610 // the results are returned via SRet in memory.
19611 const char *LibcallName = isF64 ? "__sincos_stret" : "__sincosf_stret";
19612 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
19614 DAG.getExternalSymbol(LibcallName, TLI.getPointerTy(DAG.getDataLayout()));
19616 Type *RetTy = isF64
19617 ? (Type*)StructType::get(ArgTy, ArgTy, nullptr)
19618 : (Type*)VectorType::get(ArgTy, 4);
19620 TargetLowering::CallLoweringInfo CLI(DAG);
19621 CLI.setDebugLoc(dl).setChain(DAG.getEntryNode())
19622 .setCallee(CallingConv::C, RetTy, Callee, std::move(Args), 0);
19624 std::pair<SDValue, SDValue> CallResult = TLI.LowerCallTo(CLI);
19627 // Returned in xmm0 and xmm1.
19628 return CallResult.first;
19630 // Returned in bits 0:31 and 32:64 xmm0.
19631 SDValue SinVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ArgVT,
19632 CallResult.first, DAG.getIntPtrConstant(0, dl));
19633 SDValue CosVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ArgVT,
19634 CallResult.first, DAG.getIntPtrConstant(1, dl));
19635 SDVTList Tys = DAG.getVTList(ArgVT, ArgVT);
19636 return DAG.getNode(ISD::MERGE_VALUES, dl, Tys, SinVal, CosVal);
19639 static SDValue LowerMSCATTER(SDValue Op, const X86Subtarget *Subtarget,
19640 SelectionDAG &DAG) {
19641 assert(Subtarget->hasAVX512() &&
19642 "MGATHER/MSCATTER are supported on AVX-512 arch only");
19644 MaskedScatterSDNode *N = cast<MaskedScatterSDNode>(Op.getNode());
19645 MVT VT = N->getValue().getSimpleValueType();
19646 assert(VT.getScalarSizeInBits() >= 32 && "Unsupported scatter op");
19649 // X86 scatter kills mask register, so its type should be added to
19650 // the list of return values
19651 if (N->getNumValues() == 1) {
19652 SDValue Index = N->getIndex();
19653 if (!Subtarget->hasVLX() && !VT.is512BitVector() &&
19654 !Index.getSimpleValueType().is512BitVector())
19655 Index = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v8i64, Index);
19657 SDVTList VTs = DAG.getVTList(N->getMask().getValueType(), MVT::Other);
19658 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), N->getOperand(2),
19659 N->getOperand(3), Index };
19661 SDValue NewScatter = DAG.getMaskedScatter(VTs, VT, dl, Ops, N->getMemOperand());
19662 DAG.ReplaceAllUsesWith(Op, SDValue(NewScatter.getNode(), 1));
19663 return SDValue(NewScatter.getNode(), 0);
19668 static SDValue LowerMGATHER(SDValue Op, const X86Subtarget *Subtarget,
19669 SelectionDAG &DAG) {
19670 assert(Subtarget->hasAVX512() &&
19671 "MGATHER/MSCATTER are supported on AVX-512 arch only");
19673 MaskedGatherSDNode *N = cast<MaskedGatherSDNode>(Op.getNode());
19674 MVT VT = Op.getSimpleValueType();
19675 assert(VT.getScalarSizeInBits() >= 32 && "Unsupported gather op");
19678 SDValue Index = N->getIndex();
19679 if (!Subtarget->hasVLX() && !VT.is512BitVector() &&
19680 !Index.getSimpleValueType().is512BitVector()) {
19681 Index = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v8i64, Index);
19682 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), N->getOperand(2),
19683 N->getOperand(3), Index };
19684 DAG.UpdateNodeOperands(N, Ops);
19689 SDValue X86TargetLowering::LowerGC_TRANSITION_START(SDValue Op,
19690 SelectionDAG &DAG) const {
19691 // TODO: Eventually, the lowering of these nodes should be informed by or
19692 // deferred to the GC strategy for the function in which they appear. For
19693 // now, however, they must be lowered to something. Since they are logically
19694 // no-ops in the case of a null GC strategy (or a GC strategy which does not
19695 // require special handling for these nodes), lower them as literal NOOPs for
19697 SmallVector<SDValue, 2> Ops;
19699 Ops.push_back(Op.getOperand(0));
19700 if (Op->getGluedNode())
19701 Ops.push_back(Op->getOperand(Op->getNumOperands() - 1));
19704 SDVTList VTs = DAG.getVTList(MVT::Other, MVT::Glue);
19705 SDValue NOOP(DAG.getMachineNode(X86::NOOP, SDLoc(Op), VTs, Ops), 0);
19710 SDValue X86TargetLowering::LowerGC_TRANSITION_END(SDValue Op,
19711 SelectionDAG &DAG) const {
19712 // TODO: Eventually, the lowering of these nodes should be informed by or
19713 // deferred to the GC strategy for the function in which they appear. For
19714 // now, however, they must be lowered to something. Since they are logically
19715 // no-ops in the case of a null GC strategy (or a GC strategy which does not
19716 // require special handling for these nodes), lower them as literal NOOPs for
19718 SmallVector<SDValue, 2> Ops;
19720 Ops.push_back(Op.getOperand(0));
19721 if (Op->getGluedNode())
19722 Ops.push_back(Op->getOperand(Op->getNumOperands() - 1));
19725 SDVTList VTs = DAG.getVTList(MVT::Other, MVT::Glue);
19726 SDValue NOOP(DAG.getMachineNode(X86::NOOP, SDLoc(Op), VTs, Ops), 0);
19731 /// LowerOperation - Provide custom lowering hooks for some operations.
19733 SDValue X86TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
19734 switch (Op.getOpcode()) {
19735 default: llvm_unreachable("Should not custom lower this!");
19736 case ISD::ATOMIC_FENCE: return LowerATOMIC_FENCE(Op, Subtarget, DAG);
19737 case ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS:
19738 return LowerCMP_SWAP(Op, Subtarget, DAG);
19739 case ISD::CTPOP: return LowerCTPOP(Op, Subtarget, DAG);
19740 case ISD::ATOMIC_LOAD_SUB: return LowerLOAD_SUB(Op,DAG);
19741 case ISD::ATOMIC_STORE: return LowerATOMIC_STORE(Op,DAG);
19742 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
19743 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, Subtarget, DAG);
19744 case ISD::VECTOR_SHUFFLE: return lowerVectorShuffle(Op, Subtarget, DAG);
19745 case ISD::VSELECT: return LowerVSELECT(Op, DAG);
19746 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
19747 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG);
19748 case ISD::EXTRACT_SUBVECTOR: return LowerEXTRACT_SUBVECTOR(Op,Subtarget,DAG);
19749 case ISD::INSERT_SUBVECTOR: return LowerINSERT_SUBVECTOR(Op, Subtarget,DAG);
19750 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
19751 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
19752 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
19753 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
19754 case ISD::ExternalSymbol: return LowerExternalSymbol(Op, DAG);
19755 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
19756 case ISD::SHL_PARTS:
19757 case ISD::SRA_PARTS:
19758 case ISD::SRL_PARTS: return LowerShiftParts(Op, DAG);
19759 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG);
19760 case ISD::UINT_TO_FP: return LowerUINT_TO_FP(Op, DAG);
19761 case ISD::TRUNCATE: return LowerTRUNCATE(Op, DAG);
19762 case ISD::ZERO_EXTEND: return LowerZERO_EXTEND(Op, Subtarget, DAG);
19763 case ISD::SIGN_EXTEND: return LowerSIGN_EXTEND(Op, Subtarget, DAG);
19764 case ISD::ANY_EXTEND: return LowerANY_EXTEND(Op, Subtarget, DAG);
19765 case ISD::SIGN_EXTEND_VECTOR_INREG:
19766 return LowerSIGN_EXTEND_VECTOR_INREG(Op, Subtarget, DAG);
19767 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG);
19768 case ISD::FP_TO_UINT: return LowerFP_TO_UINT(Op, DAG);
19769 case ISD::FP_EXTEND: return LowerFP_EXTEND(Op, DAG);
19770 case ISD::LOAD: return LowerExtendedLoad(Op, Subtarget, DAG);
19772 case ISD::FNEG: return LowerFABSorFNEG(Op, DAG);
19773 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG);
19774 case ISD::FGETSIGN: return LowerFGETSIGN(Op, DAG);
19775 case ISD::SETCC: return LowerSETCC(Op, DAG);
19776 case ISD::SETCCE: return LowerSETCCE(Op, DAG);
19777 case ISD::SELECT: return LowerSELECT(Op, DAG);
19778 case ISD::BRCOND: return LowerBRCOND(Op, DAG);
19779 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
19780 case ISD::VASTART: return LowerVASTART(Op, DAG);
19781 case ISD::VAARG: return LowerVAARG(Op, DAG);
19782 case ISD::VACOPY: return LowerVACOPY(Op, Subtarget, DAG);
19783 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, Subtarget, DAG);
19784 case ISD::INTRINSIC_VOID:
19785 case ISD::INTRINSIC_W_CHAIN: return LowerINTRINSIC_W_CHAIN(Op, Subtarget, DAG);
19786 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
19787 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
19788 case ISD::FRAME_TO_ARGS_OFFSET:
19789 return LowerFRAME_TO_ARGS_OFFSET(Op, DAG);
19790 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
19791 case ISD::EH_RETURN: return LowerEH_RETURN(Op, DAG);
19792 case ISD::EH_SJLJ_SETJMP: return lowerEH_SJLJ_SETJMP(Op, DAG);
19793 case ISD::EH_SJLJ_LONGJMP: return lowerEH_SJLJ_LONGJMP(Op, DAG);
19794 case ISD::INIT_TRAMPOLINE: return LowerINIT_TRAMPOLINE(Op, DAG);
19795 case ISD::ADJUST_TRAMPOLINE: return LowerADJUST_TRAMPOLINE(Op, DAG);
19796 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
19797 case ISD::CTLZ: return LowerCTLZ(Op, Subtarget, DAG);
19798 case ISD::CTLZ_ZERO_UNDEF: return LowerCTLZ_ZERO_UNDEF(Op, Subtarget, DAG);
19800 case ISD::CTTZ_ZERO_UNDEF: return LowerCTTZ(Op, DAG);
19801 case ISD::MUL: return LowerMUL(Op, Subtarget, DAG);
19802 case ISD::UMUL_LOHI:
19803 case ISD::SMUL_LOHI: return LowerMUL_LOHI(Op, Subtarget, DAG);
19804 case ISD::ROTL: return LowerRotate(Op, Subtarget, DAG);
19807 case ISD::SHL: return LowerShift(Op, Subtarget, DAG);
19813 case ISD::UMULO: return LowerXALUO(Op, DAG);
19814 case ISD::READCYCLECOUNTER: return LowerREADCYCLECOUNTER(Op, Subtarget,DAG);
19815 case ISD::BITCAST: return LowerBITCAST(Op, Subtarget, DAG);
19819 case ISD::SUBE: return LowerADDC_ADDE_SUBC_SUBE(Op, DAG);
19820 case ISD::ADD: return LowerADD(Op, DAG);
19821 case ISD::SUB: return LowerSUB(Op, DAG);
19825 case ISD::UMIN: return LowerMINMAX(Op, DAG);
19826 case ISD::FSINCOS: return LowerFSINCOS(Op, Subtarget, DAG);
19827 case ISD::MGATHER: return LowerMGATHER(Op, Subtarget, DAG);
19828 case ISD::MSCATTER: return LowerMSCATTER(Op, Subtarget, DAG);
19829 case ISD::GC_TRANSITION_START:
19830 return LowerGC_TRANSITION_START(Op, DAG);
19831 case ISD::GC_TRANSITION_END: return LowerGC_TRANSITION_END(Op, DAG);
19835 /// ReplaceNodeResults - Replace a node with an illegal result type
19836 /// with a new node built out of custom code.
19837 void X86TargetLowering::ReplaceNodeResults(SDNode *N,
19838 SmallVectorImpl<SDValue>&Results,
19839 SelectionDAG &DAG) const {
19841 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
19842 switch (N->getOpcode()) {
19844 llvm_unreachable("Do not know how to custom type legalize this operation!");
19845 case X86ISD::AVG: {
19846 // Legalize types for X86ISD::AVG by expanding vectors.
19847 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
19849 auto InVT = N->getValueType(0);
19850 auto InVTSize = InVT.getSizeInBits();
19851 const unsigned RegSize =
19852 (InVTSize > 128) ? ((InVTSize > 256) ? 512 : 256) : 128;
19853 assert((!Subtarget->hasAVX512() || RegSize < 512) &&
19854 "512-bit vector requires AVX512");
19855 assert((!Subtarget->hasAVX2() || RegSize < 256) &&
19856 "256-bit vector requires AVX2");
19858 auto ElemVT = InVT.getVectorElementType();
19859 auto RegVT = EVT::getVectorVT(*DAG.getContext(), ElemVT,
19860 RegSize / ElemVT.getSizeInBits());
19861 assert(RegSize % InVT.getSizeInBits() == 0);
19862 unsigned NumConcat = RegSize / InVT.getSizeInBits();
19864 SmallVector<SDValue, 16> Ops(NumConcat, DAG.getUNDEF(InVT));
19865 Ops[0] = N->getOperand(0);
19866 SDValue InVec0 = DAG.getNode(ISD::CONCAT_VECTORS, dl, RegVT, Ops);
19867 Ops[0] = N->getOperand(1);
19868 SDValue InVec1 = DAG.getNode(ISD::CONCAT_VECTORS, dl, RegVT, Ops);
19870 SDValue Res = DAG.getNode(X86ISD::AVG, dl, RegVT, InVec0, InVec1);
19871 Results.push_back(DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, InVT, Res,
19872 DAG.getIntPtrConstant(0, dl)));
19875 // We might have generated v2f32 FMIN/FMAX operations. Widen them to v4f32.
19876 case X86ISD::FMINC:
19878 case X86ISD::FMAXC:
19879 case X86ISD::FMAX: {
19880 EVT VT = N->getValueType(0);
19881 assert(VT == MVT::v2f32 && "Unexpected type (!= v2f32) on FMIN/FMAX.");
19882 SDValue UNDEF = DAG.getUNDEF(VT);
19883 SDValue LHS = DAG.getNode(ISD::CONCAT_VECTORS, dl, MVT::v4f32,
19884 N->getOperand(0), UNDEF);
19885 SDValue RHS = DAG.getNode(ISD::CONCAT_VECTORS, dl, MVT::v4f32,
19886 N->getOperand(1), UNDEF);
19887 Results.push_back(DAG.getNode(N->getOpcode(), dl, MVT::v4f32, LHS, RHS));
19890 case ISD::SIGN_EXTEND_INREG:
19895 // We don't want to expand or promote these.
19902 case ISD::UDIVREM: {
19903 SDValue V = LowerWin64_i128OP(SDValue(N,0), DAG);
19904 Results.push_back(V);
19907 case ISD::FP_TO_SINT:
19908 case ISD::FP_TO_UINT: {
19909 bool IsSigned = N->getOpcode() == ISD::FP_TO_SINT;
19911 std::pair<SDValue,SDValue> Vals =
19912 FP_TO_INTHelper(SDValue(N, 0), DAG, IsSigned, /*IsReplace=*/ true);
19913 SDValue FIST = Vals.first, StackSlot = Vals.second;
19914 if (FIST.getNode()) {
19915 EVT VT = N->getValueType(0);
19916 // Return a load from the stack slot.
19917 if (StackSlot.getNode())
19918 Results.push_back(DAG.getLoad(VT, dl, FIST, StackSlot,
19919 MachinePointerInfo(),
19920 false, false, false, 0));
19922 Results.push_back(FIST);
19926 case ISD::UINT_TO_FP: {
19927 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
19928 if (N->getOperand(0).getValueType() != MVT::v2i32 ||
19929 N->getValueType(0) != MVT::v2f32)
19931 SDValue ZExtIn = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v2i64,
19933 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL), dl,
19935 SDValue VBias = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2f64, Bias, Bias);
19936 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64, ZExtIn,
19937 DAG.getBitcast(MVT::v2i64, VBias));
19938 Or = DAG.getBitcast(MVT::v2f64, Or);
19939 // TODO: Are there any fast-math-flags to propagate here?
19940 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, Or, VBias);
19941 Results.push_back(DAG.getNode(X86ISD::VFPROUND, dl, MVT::v4f32, Sub));
19944 case ISD::FP_ROUND: {
19945 if (!TLI.isTypeLegal(N->getOperand(0).getValueType()))
19947 SDValue V = DAG.getNode(X86ISD::VFPROUND, dl, MVT::v4f32, N->getOperand(0));
19948 Results.push_back(V);
19951 case ISD::FP_EXTEND: {
19952 // Right now, only MVT::v2f32 has OperationAction for FP_EXTEND.
19953 // No other ValueType for FP_EXTEND should reach this point.
19954 assert(N->getValueType(0) == MVT::v2f32 &&
19955 "Do not know how to legalize this Node");
19958 case ISD::INTRINSIC_W_CHAIN: {
19959 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
19961 default : llvm_unreachable("Do not know how to custom type "
19962 "legalize this intrinsic operation!");
19963 case Intrinsic::x86_rdtsc:
19964 return getReadTimeStampCounter(N, dl, X86ISD::RDTSC_DAG, DAG, Subtarget,
19966 case Intrinsic::x86_rdtscp:
19967 return getReadTimeStampCounter(N, dl, X86ISD::RDTSCP_DAG, DAG, Subtarget,
19969 case Intrinsic::x86_rdpmc:
19970 return getReadPerformanceCounter(N, dl, DAG, Subtarget, Results);
19973 case ISD::READCYCLECOUNTER: {
19974 return getReadTimeStampCounter(N, dl, X86ISD::RDTSC_DAG, DAG, Subtarget,
19977 case ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS: {
19978 EVT T = N->getValueType(0);
19979 assert((T == MVT::i64 || T == MVT::i128) && "can only expand cmpxchg pair");
19980 bool Regs64bit = T == MVT::i128;
19981 MVT HalfT = Regs64bit ? MVT::i64 : MVT::i32;
19982 SDValue cpInL, cpInH;
19983 cpInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2),
19984 DAG.getConstant(0, dl, HalfT));
19985 cpInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2),
19986 DAG.getConstant(1, dl, HalfT));
19987 cpInL = DAG.getCopyToReg(N->getOperand(0), dl,
19988 Regs64bit ? X86::RAX : X86::EAX,
19990 cpInH = DAG.getCopyToReg(cpInL.getValue(0), dl,
19991 Regs64bit ? X86::RDX : X86::EDX,
19992 cpInH, cpInL.getValue(1));
19993 SDValue swapInL, swapInH;
19994 swapInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3),
19995 DAG.getConstant(0, dl, HalfT));
19996 swapInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3),
19997 DAG.getConstant(1, dl, HalfT));
19998 swapInL = DAG.getCopyToReg(cpInH.getValue(0), dl,
19999 Regs64bit ? X86::RBX : X86::EBX,
20000 swapInL, cpInH.getValue(1));
20001 swapInH = DAG.getCopyToReg(swapInL.getValue(0), dl,
20002 Regs64bit ? X86::RCX : X86::ECX,
20003 swapInH, swapInL.getValue(1));
20004 SDValue Ops[] = { swapInH.getValue(0),
20006 swapInH.getValue(1) };
20007 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
20008 MachineMemOperand *MMO = cast<AtomicSDNode>(N)->getMemOperand();
20009 unsigned Opcode = Regs64bit ? X86ISD::LCMPXCHG16_DAG :
20010 X86ISD::LCMPXCHG8_DAG;
20011 SDValue Result = DAG.getMemIntrinsicNode(Opcode, dl, Tys, Ops, T, MMO);
20012 SDValue cpOutL = DAG.getCopyFromReg(Result.getValue(0), dl,
20013 Regs64bit ? X86::RAX : X86::EAX,
20014 HalfT, Result.getValue(1));
20015 SDValue cpOutH = DAG.getCopyFromReg(cpOutL.getValue(1), dl,
20016 Regs64bit ? X86::RDX : X86::EDX,
20017 HalfT, cpOutL.getValue(2));
20018 SDValue OpsF[] = { cpOutL.getValue(0), cpOutH.getValue(0)};
20020 SDValue EFLAGS = DAG.getCopyFromReg(cpOutH.getValue(1), dl, X86::EFLAGS,
20021 MVT::i32, cpOutH.getValue(2));
20023 DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
20024 DAG.getConstant(X86::COND_E, dl, MVT::i8), EFLAGS);
20025 Success = DAG.getZExtOrTrunc(Success, dl, N->getValueType(1));
20027 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, T, OpsF));
20028 Results.push_back(Success);
20029 Results.push_back(EFLAGS.getValue(1));
20032 case ISD::ATOMIC_SWAP:
20033 case ISD::ATOMIC_LOAD_ADD:
20034 case ISD::ATOMIC_LOAD_SUB:
20035 case ISD::ATOMIC_LOAD_AND:
20036 case ISD::ATOMIC_LOAD_OR:
20037 case ISD::ATOMIC_LOAD_XOR:
20038 case ISD::ATOMIC_LOAD_NAND:
20039 case ISD::ATOMIC_LOAD_MIN:
20040 case ISD::ATOMIC_LOAD_MAX:
20041 case ISD::ATOMIC_LOAD_UMIN:
20042 case ISD::ATOMIC_LOAD_UMAX:
20043 case ISD::ATOMIC_LOAD: {
20044 // Delegate to generic TypeLegalization. Situations we can really handle
20045 // should have already been dealt with by AtomicExpandPass.cpp.
20048 case ISD::BITCAST: {
20049 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
20050 EVT DstVT = N->getValueType(0);
20051 EVT SrcVT = N->getOperand(0)->getValueType(0);
20053 if (SrcVT != MVT::f64 ||
20054 (DstVT != MVT::v2i32 && DstVT != MVT::v4i16 && DstVT != MVT::v8i8))
20057 unsigned NumElts = DstVT.getVectorNumElements();
20058 EVT SVT = DstVT.getVectorElementType();
20059 EVT WiderVT = EVT::getVectorVT(*DAG.getContext(), SVT, NumElts * 2);
20060 SDValue Expanded = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
20061 MVT::v2f64, N->getOperand(0));
20062 SDValue ToVecInt = DAG.getBitcast(WiderVT, Expanded);
20064 if (ExperimentalVectorWideningLegalization) {
20065 // If we are legalizing vectors by widening, we already have the desired
20066 // legal vector type, just return it.
20067 Results.push_back(ToVecInt);
20071 SmallVector<SDValue, 8> Elts;
20072 for (unsigned i = 0, e = NumElts; i != e; ++i)
20073 Elts.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, SVT,
20074 ToVecInt, DAG.getIntPtrConstant(i, dl)));
20076 Results.push_back(DAG.getNode(ISD::BUILD_VECTOR, dl, DstVT, Elts));
20081 const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
20082 switch ((X86ISD::NodeType)Opcode) {
20083 case X86ISD::FIRST_NUMBER: break;
20084 case X86ISD::BSF: return "X86ISD::BSF";
20085 case X86ISD::BSR: return "X86ISD::BSR";
20086 case X86ISD::SHLD: return "X86ISD::SHLD";
20087 case X86ISD::SHRD: return "X86ISD::SHRD";
20088 case X86ISD::FAND: return "X86ISD::FAND";
20089 case X86ISD::FANDN: return "X86ISD::FANDN";
20090 case X86ISD::FOR: return "X86ISD::FOR";
20091 case X86ISD::FXOR: return "X86ISD::FXOR";
20092 case X86ISD::FILD: return "X86ISD::FILD";
20093 case X86ISD::FILD_FLAG: return "X86ISD::FILD_FLAG";
20094 case X86ISD::FP_TO_INT16_IN_MEM: return "X86ISD::FP_TO_INT16_IN_MEM";
20095 case X86ISD::FP_TO_INT32_IN_MEM: return "X86ISD::FP_TO_INT32_IN_MEM";
20096 case X86ISD::FP_TO_INT64_IN_MEM: return "X86ISD::FP_TO_INT64_IN_MEM";
20097 case X86ISD::FLD: return "X86ISD::FLD";
20098 case X86ISD::FST: return "X86ISD::FST";
20099 case X86ISD::CALL: return "X86ISD::CALL";
20100 case X86ISD::RDTSC_DAG: return "X86ISD::RDTSC_DAG";
20101 case X86ISD::RDTSCP_DAG: return "X86ISD::RDTSCP_DAG";
20102 case X86ISD::RDPMC_DAG: return "X86ISD::RDPMC_DAG";
20103 case X86ISD::BT: return "X86ISD::BT";
20104 case X86ISD::CMP: return "X86ISD::CMP";
20105 case X86ISD::COMI: return "X86ISD::COMI";
20106 case X86ISD::UCOMI: return "X86ISD::UCOMI";
20107 case X86ISD::CMPM: return "X86ISD::CMPM";
20108 case X86ISD::CMPMU: return "X86ISD::CMPMU";
20109 case X86ISD::CMPM_RND: return "X86ISD::CMPM_RND";
20110 case X86ISD::SETCC: return "X86ISD::SETCC";
20111 case X86ISD::SETCC_CARRY: return "X86ISD::SETCC_CARRY";
20112 case X86ISD::FSETCC: return "X86ISD::FSETCC";
20113 case X86ISD::FGETSIGNx86: return "X86ISD::FGETSIGNx86";
20114 case X86ISD::CMOV: return "X86ISD::CMOV";
20115 case X86ISD::BRCOND: return "X86ISD::BRCOND";
20116 case X86ISD::RET_FLAG: return "X86ISD::RET_FLAG";
20117 case X86ISD::REP_STOS: return "X86ISD::REP_STOS";
20118 case X86ISD::REP_MOVS: return "X86ISD::REP_MOVS";
20119 case X86ISD::GlobalBaseReg: return "X86ISD::GlobalBaseReg";
20120 case X86ISD::Wrapper: return "X86ISD::Wrapper";
20121 case X86ISD::WrapperRIP: return "X86ISD::WrapperRIP";
20122 case X86ISD::MOVDQ2Q: return "X86ISD::MOVDQ2Q";
20123 case X86ISD::MMX_MOVD2W: return "X86ISD::MMX_MOVD2W";
20124 case X86ISD::MMX_MOVW2D: return "X86ISD::MMX_MOVW2D";
20125 case X86ISD::PEXTRB: return "X86ISD::PEXTRB";
20126 case X86ISD::PEXTRW: return "X86ISD::PEXTRW";
20127 case X86ISD::INSERTPS: return "X86ISD::INSERTPS";
20128 case X86ISD::PINSRB: return "X86ISD::PINSRB";
20129 case X86ISD::PINSRW: return "X86ISD::PINSRW";
20130 case X86ISD::MMX_PINSRW: return "X86ISD::MMX_PINSRW";
20131 case X86ISD::PSHUFB: return "X86ISD::PSHUFB";
20132 case X86ISD::ANDNP: return "X86ISD::ANDNP";
20133 case X86ISD::PSIGN: return "X86ISD::PSIGN";
20134 case X86ISD::BLENDI: return "X86ISD::BLENDI";
20135 case X86ISD::SHRUNKBLEND: return "X86ISD::SHRUNKBLEND";
20136 case X86ISD::ADDUS: return "X86ISD::ADDUS";
20137 case X86ISD::SUBUS: return "X86ISD::SUBUS";
20138 case X86ISD::HADD: return "X86ISD::HADD";
20139 case X86ISD::HSUB: return "X86ISD::HSUB";
20140 case X86ISD::FHADD: return "X86ISD::FHADD";
20141 case X86ISD::FHSUB: return "X86ISD::FHSUB";
20142 case X86ISD::ABS: return "X86ISD::ABS";
20143 case X86ISD::CONFLICT: return "X86ISD::CONFLICT";
20144 case X86ISD::FMAX: return "X86ISD::FMAX";
20145 case X86ISD::FMAX_RND: return "X86ISD::FMAX_RND";
20146 case X86ISD::FMIN: return "X86ISD::FMIN";
20147 case X86ISD::FMIN_RND: return "X86ISD::FMIN_RND";
20148 case X86ISD::FMAXC: return "X86ISD::FMAXC";
20149 case X86ISD::FMINC: return "X86ISD::FMINC";
20150 case X86ISD::FRSQRT: return "X86ISD::FRSQRT";
20151 case X86ISD::FRCP: return "X86ISD::FRCP";
20152 case X86ISD::EXTRQI: return "X86ISD::EXTRQI";
20153 case X86ISD::INSERTQI: return "X86ISD::INSERTQI";
20154 case X86ISD::TLSADDR: return "X86ISD::TLSADDR";
20155 case X86ISD::TLSBASEADDR: return "X86ISD::TLSBASEADDR";
20156 case X86ISD::TLSCALL: return "X86ISD::TLSCALL";
20157 case X86ISD::EH_SJLJ_SETJMP: return "X86ISD::EH_SJLJ_SETJMP";
20158 case X86ISD::EH_SJLJ_LONGJMP: return "X86ISD::EH_SJLJ_LONGJMP";
20159 case X86ISD::EH_RETURN: return "X86ISD::EH_RETURN";
20160 case X86ISD::TC_RETURN: return "X86ISD::TC_RETURN";
20161 case X86ISD::FNSTCW16m: return "X86ISD::FNSTCW16m";
20162 case X86ISD::FNSTSW16r: return "X86ISD::FNSTSW16r";
20163 case X86ISD::LCMPXCHG_DAG: return "X86ISD::LCMPXCHG_DAG";
20164 case X86ISD::LCMPXCHG8_DAG: return "X86ISD::LCMPXCHG8_DAG";
20165 case X86ISD::LCMPXCHG16_DAG: return "X86ISD::LCMPXCHG16_DAG";
20166 case X86ISD::VZEXT_MOVL: return "X86ISD::VZEXT_MOVL";
20167 case X86ISD::VZEXT_LOAD: return "X86ISD::VZEXT_LOAD";
20168 case X86ISD::VZEXT: return "X86ISD::VZEXT";
20169 case X86ISD::VSEXT: return "X86ISD::VSEXT";
20170 case X86ISD::VTRUNC: return "X86ISD::VTRUNC";
20171 case X86ISD::VTRUNCS: return "X86ISD::VTRUNCS";
20172 case X86ISD::VTRUNCUS: return "X86ISD::VTRUNCUS";
20173 case X86ISD::VINSERT: return "X86ISD::VINSERT";
20174 case X86ISD::VFPEXT: return "X86ISD::VFPEXT";
20175 case X86ISD::VFPROUND: return "X86ISD::VFPROUND";
20176 case X86ISD::CVTDQ2PD: return "X86ISD::CVTDQ2PD";
20177 case X86ISD::CVTUDQ2PD: return "X86ISD::CVTUDQ2PD";
20178 case X86ISD::VSHLDQ: return "X86ISD::VSHLDQ";
20179 case X86ISD::VSRLDQ: return "X86ISD::VSRLDQ";
20180 case X86ISD::VSHL: return "X86ISD::VSHL";
20181 case X86ISD::VSRL: return "X86ISD::VSRL";
20182 case X86ISD::VSRA: return "X86ISD::VSRA";
20183 case X86ISD::VSHLI: return "X86ISD::VSHLI";
20184 case X86ISD::VSRLI: return "X86ISD::VSRLI";
20185 case X86ISD::VSRAI: return "X86ISD::VSRAI";
20186 case X86ISD::CMPP: return "X86ISD::CMPP";
20187 case X86ISD::PCMPEQ: return "X86ISD::PCMPEQ";
20188 case X86ISD::PCMPGT: return "X86ISD::PCMPGT";
20189 case X86ISD::PCMPEQM: return "X86ISD::PCMPEQM";
20190 case X86ISD::PCMPGTM: return "X86ISD::PCMPGTM";
20191 case X86ISD::ADD: return "X86ISD::ADD";
20192 case X86ISD::SUB: return "X86ISD::SUB";
20193 case X86ISD::ADC: return "X86ISD::ADC";
20194 case X86ISD::SBB: return "X86ISD::SBB";
20195 case X86ISD::SMUL: return "X86ISD::SMUL";
20196 case X86ISD::UMUL: return "X86ISD::UMUL";
20197 case X86ISD::SMUL8: return "X86ISD::SMUL8";
20198 case X86ISD::UMUL8: return "X86ISD::UMUL8";
20199 case X86ISD::SDIVREM8_SEXT_HREG: return "X86ISD::SDIVREM8_SEXT_HREG";
20200 case X86ISD::UDIVREM8_ZEXT_HREG: return "X86ISD::UDIVREM8_ZEXT_HREG";
20201 case X86ISD::INC: return "X86ISD::INC";
20202 case X86ISD::DEC: return "X86ISD::DEC";
20203 case X86ISD::OR: return "X86ISD::OR";
20204 case X86ISD::XOR: return "X86ISD::XOR";
20205 case X86ISD::AND: return "X86ISD::AND";
20206 case X86ISD::BEXTR: return "X86ISD::BEXTR";
20207 case X86ISD::MUL_IMM: return "X86ISD::MUL_IMM";
20208 case X86ISD::PTEST: return "X86ISD::PTEST";
20209 case X86ISD::TESTP: return "X86ISD::TESTP";
20210 case X86ISD::TESTM: return "X86ISD::TESTM";
20211 case X86ISD::TESTNM: return "X86ISD::TESTNM";
20212 case X86ISD::KORTEST: return "X86ISD::KORTEST";
20213 case X86ISD::KTEST: return "X86ISD::KTEST";
20214 case X86ISD::PACKSS: return "X86ISD::PACKSS";
20215 case X86ISD::PACKUS: return "X86ISD::PACKUS";
20216 case X86ISD::PALIGNR: return "X86ISD::PALIGNR";
20217 case X86ISD::VALIGN: return "X86ISD::VALIGN";
20218 case X86ISD::PSHUFD: return "X86ISD::PSHUFD";
20219 case X86ISD::PSHUFHW: return "X86ISD::PSHUFHW";
20220 case X86ISD::PSHUFLW: return "X86ISD::PSHUFLW";
20221 case X86ISD::SHUFP: return "X86ISD::SHUFP";
20222 case X86ISD::SHUF128: return "X86ISD::SHUF128";
20223 case X86ISD::MOVLHPS: return "X86ISD::MOVLHPS";
20224 case X86ISD::MOVLHPD: return "X86ISD::MOVLHPD";
20225 case X86ISD::MOVHLPS: return "X86ISD::MOVHLPS";
20226 case X86ISD::MOVLPS: return "X86ISD::MOVLPS";
20227 case X86ISD::MOVLPD: return "X86ISD::MOVLPD";
20228 case X86ISD::MOVDDUP: return "X86ISD::MOVDDUP";
20229 case X86ISD::MOVSHDUP: return "X86ISD::MOVSHDUP";
20230 case X86ISD::MOVSLDUP: return "X86ISD::MOVSLDUP";
20231 case X86ISD::MOVSD: return "X86ISD::MOVSD";
20232 case X86ISD::MOVSS: return "X86ISD::MOVSS";
20233 case X86ISD::UNPCKL: return "X86ISD::UNPCKL";
20234 case X86ISD::UNPCKH: return "X86ISD::UNPCKH";
20235 case X86ISD::VBROADCAST: return "X86ISD::VBROADCAST";
20236 case X86ISD::VBROADCASTM: return "X86ISD::VBROADCASTM";
20237 case X86ISD::SUBV_BROADCAST: return "X86ISD::SUBV_BROADCAST";
20238 case X86ISD::VEXTRACT: return "X86ISD::VEXTRACT";
20239 case X86ISD::VPERMILPV: return "X86ISD::VPERMILPV";
20240 case X86ISD::VPERMILPI: return "X86ISD::VPERMILPI";
20241 case X86ISD::VPERM2X128: return "X86ISD::VPERM2X128";
20242 case X86ISD::VPERMV: return "X86ISD::VPERMV";
20243 case X86ISD::VPERMV3: return "X86ISD::VPERMV3";
20244 case X86ISD::VPERMIV3: return "X86ISD::VPERMIV3";
20245 case X86ISD::VPERMI: return "X86ISD::VPERMI";
20246 case X86ISD::VPTERNLOG: return "X86ISD::VPTERNLOG";
20247 case X86ISD::VFIXUPIMM: return "X86ISD::VFIXUPIMM";
20248 case X86ISD::VRANGE: return "X86ISD::VRANGE";
20249 case X86ISD::PMULUDQ: return "X86ISD::PMULUDQ";
20250 case X86ISD::PMULDQ: return "X86ISD::PMULDQ";
20251 case X86ISD::PSADBW: return "X86ISD::PSADBW";
20252 case X86ISD::DBPSADBW: return "X86ISD::DBPSADBW";
20253 case X86ISD::VASTART_SAVE_XMM_REGS: return "X86ISD::VASTART_SAVE_XMM_REGS";
20254 case X86ISD::VAARG_64: return "X86ISD::VAARG_64";
20255 case X86ISD::WIN_ALLOCA: return "X86ISD::WIN_ALLOCA";
20256 case X86ISD::MEMBARRIER: return "X86ISD::MEMBARRIER";
20257 case X86ISD::MFENCE: return "X86ISD::MFENCE";
20258 case X86ISD::SFENCE: return "X86ISD::SFENCE";
20259 case X86ISD::LFENCE: return "X86ISD::LFENCE";
20260 case X86ISD::SEG_ALLOCA: return "X86ISD::SEG_ALLOCA";
20261 case X86ISD::SAHF: return "X86ISD::SAHF";
20262 case X86ISD::RDRAND: return "X86ISD::RDRAND";
20263 case X86ISD::RDSEED: return "X86ISD::RDSEED";
20264 case X86ISD::VPMADDUBSW: return "X86ISD::VPMADDUBSW";
20265 case X86ISD::VPMADDWD: return "X86ISD::VPMADDWD";
20266 case X86ISD::VPROT: return "X86ISD::VPROT";
20267 case X86ISD::VPROTI: return "X86ISD::VPROTI";
20268 case X86ISD::VPSHA: return "X86ISD::VPSHA";
20269 case X86ISD::VPSHL: return "X86ISD::VPSHL";
20270 case X86ISD::VPCOM: return "X86ISD::VPCOM";
20271 case X86ISD::VPCOMU: return "X86ISD::VPCOMU";
20272 case X86ISD::FMADD: return "X86ISD::FMADD";
20273 case X86ISD::FMSUB: return "X86ISD::FMSUB";
20274 case X86ISD::FNMADD: return "X86ISD::FNMADD";
20275 case X86ISD::FNMSUB: return "X86ISD::FNMSUB";
20276 case X86ISD::FMADDSUB: return "X86ISD::FMADDSUB";
20277 case X86ISD::FMSUBADD: return "X86ISD::FMSUBADD";
20278 case X86ISD::FMADD_RND: return "X86ISD::FMADD_RND";
20279 case X86ISD::FNMADD_RND: return "X86ISD::FNMADD_RND";
20280 case X86ISD::FMSUB_RND: return "X86ISD::FMSUB_RND";
20281 case X86ISD::FNMSUB_RND: return "X86ISD::FNMSUB_RND";
20282 case X86ISD::FMADDSUB_RND: return "X86ISD::FMADDSUB_RND";
20283 case X86ISD::FMSUBADD_RND: return "X86ISD::FMSUBADD_RND";
20284 case X86ISD::VRNDSCALE: return "X86ISD::VRNDSCALE";
20285 case X86ISD::VREDUCE: return "X86ISD::VREDUCE";
20286 case X86ISD::VGETMANT: return "X86ISD::VGETMANT";
20287 case X86ISD::PCMPESTRI: return "X86ISD::PCMPESTRI";
20288 case X86ISD::PCMPISTRI: return "X86ISD::PCMPISTRI";
20289 case X86ISD::XTEST: return "X86ISD::XTEST";
20290 case X86ISD::COMPRESS: return "X86ISD::COMPRESS";
20291 case X86ISD::EXPAND: return "X86ISD::EXPAND";
20292 case X86ISD::SELECT: return "X86ISD::SELECT";
20293 case X86ISD::ADDSUB: return "X86ISD::ADDSUB";
20294 case X86ISD::RCP28: return "X86ISD::RCP28";
20295 case X86ISD::EXP2: return "X86ISD::EXP2";
20296 case X86ISD::RSQRT28: return "X86ISD::RSQRT28";
20297 case X86ISD::FADD_RND: return "X86ISD::FADD_RND";
20298 case X86ISD::FSUB_RND: return "X86ISD::FSUB_RND";
20299 case X86ISD::FMUL_RND: return "X86ISD::FMUL_RND";
20300 case X86ISD::FDIV_RND: return "X86ISD::FDIV_RND";
20301 case X86ISD::FSQRT_RND: return "X86ISD::FSQRT_RND";
20302 case X86ISD::FGETEXP_RND: return "X86ISD::FGETEXP_RND";
20303 case X86ISD::SCALEF: return "X86ISD::SCALEF";
20304 case X86ISD::ADDS: return "X86ISD::ADDS";
20305 case X86ISD::SUBS: return "X86ISD::SUBS";
20306 case X86ISD::AVG: return "X86ISD::AVG";
20307 case X86ISD::MULHRS: return "X86ISD::MULHRS";
20308 case X86ISD::SINT_TO_FP_RND: return "X86ISD::SINT_TO_FP_RND";
20309 case X86ISD::UINT_TO_FP_RND: return "X86ISD::UINT_TO_FP_RND";
20310 case X86ISD::FP_TO_SINT_RND: return "X86ISD::FP_TO_SINT_RND";
20311 case X86ISD::FP_TO_UINT_RND: return "X86ISD::FP_TO_UINT_RND";
20312 case X86ISD::VFPCLASS: return "X86ISD::VFPCLASS";
20313 case X86ISD::VFPCLASSS: return "X86ISD::VFPCLASSS";
20318 // isLegalAddressingMode - Return true if the addressing mode represented
20319 // by AM is legal for this target, for a load/store of the specified type.
20320 bool X86TargetLowering::isLegalAddressingMode(const DataLayout &DL,
20321 const AddrMode &AM, Type *Ty,
20322 unsigned AS) const {
20323 // X86 supports extremely general addressing modes.
20324 CodeModel::Model M = getTargetMachine().getCodeModel();
20325 Reloc::Model R = getTargetMachine().getRelocationModel();
20327 // X86 allows a sign-extended 32-bit immediate field as a displacement.
20328 if (!X86::isOffsetSuitableForCodeModel(AM.BaseOffs, M, AM.BaseGV != nullptr))
20333 Subtarget->ClassifyGlobalReference(AM.BaseGV, getTargetMachine());
20335 // If a reference to this global requires an extra load, we can't fold it.
20336 if (isGlobalStubReference(GVFlags))
20339 // If BaseGV requires a register for the PIC base, we cannot also have a
20340 // BaseReg specified.
20341 if (AM.HasBaseReg && isGlobalRelativeToPICBase(GVFlags))
20344 // If lower 4G is not available, then we must use rip-relative addressing.
20345 if ((M != CodeModel::Small || R != Reloc::Static) &&
20346 Subtarget->is64Bit() && (AM.BaseOffs || AM.Scale > 1))
20350 switch (AM.Scale) {
20356 // These scales always work.
20361 // These scales are formed with basereg+scalereg. Only accept if there is
20366 default: // Other stuff never works.
20373 bool X86TargetLowering::isVectorShiftByScalarCheap(Type *Ty) const {
20374 unsigned Bits = Ty->getScalarSizeInBits();
20376 // 8-bit shifts are always expensive, but versions with a scalar amount aren't
20377 // particularly cheaper than those without.
20381 // On AVX2 there are new vpsllv[dq] instructions (and other shifts), that make
20382 // variable shifts just as cheap as scalar ones.
20383 if (Subtarget->hasInt256() && (Bits == 32 || Bits == 64))
20386 // Otherwise, it's significantly cheaper to shift by a scalar amount than by a
20387 // fully general vector.
20391 bool X86TargetLowering::isTruncateFree(Type *Ty1, Type *Ty2) const {
20392 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
20394 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits();
20395 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits();
20396 return NumBits1 > NumBits2;
20399 bool X86TargetLowering::allowTruncateForTailCall(Type *Ty1, Type *Ty2) const {
20400 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
20403 if (!isTypeLegal(EVT::getEVT(Ty1)))
20406 assert(Ty1->getPrimitiveSizeInBits() <= 64 && "i128 is probably not a noop");
20408 // Assuming the caller doesn't have a zeroext or signext return parameter,
20409 // truncation all the way down to i1 is valid.
20413 bool X86TargetLowering::isLegalICmpImmediate(int64_t Imm) const {
20414 return isInt<32>(Imm);
20417 bool X86TargetLowering::isLegalAddImmediate(int64_t Imm) const {
20418 // Can also use sub to handle negated immediates.
20419 return isInt<32>(Imm);
20422 bool X86TargetLowering::isTruncateFree(EVT VT1, EVT VT2) const {
20423 if (!VT1.isInteger() || !VT2.isInteger())
20425 unsigned NumBits1 = VT1.getSizeInBits();
20426 unsigned NumBits2 = VT2.getSizeInBits();
20427 return NumBits1 > NumBits2;
20430 bool X86TargetLowering::isZExtFree(Type *Ty1, Type *Ty2) const {
20431 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
20432 return Ty1->isIntegerTy(32) && Ty2->isIntegerTy(64) && Subtarget->is64Bit();
20435 bool X86TargetLowering::isZExtFree(EVT VT1, EVT VT2) const {
20436 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
20437 return VT1 == MVT::i32 && VT2 == MVT::i64 && Subtarget->is64Bit();
20440 bool X86TargetLowering::isZExtFree(SDValue Val, EVT VT2) const {
20441 EVT VT1 = Val.getValueType();
20442 if (isZExtFree(VT1, VT2))
20445 if (Val.getOpcode() != ISD::LOAD)
20448 if (!VT1.isSimple() || !VT1.isInteger() ||
20449 !VT2.isSimple() || !VT2.isInteger())
20452 switch (VT1.getSimpleVT().SimpleTy) {
20457 // X86 has 8, 16, and 32-bit zero-extending loads.
20464 bool X86TargetLowering::isVectorLoadExtDesirable(SDValue) const { return true; }
20467 X86TargetLowering::isFMAFasterThanFMulAndFAdd(EVT VT) const {
20468 if (!(Subtarget->hasFMA() || Subtarget->hasFMA4() || Subtarget->hasAVX512()))
20471 VT = VT.getScalarType();
20473 if (!VT.isSimple())
20476 switch (VT.getSimpleVT().SimpleTy) {
20487 bool X86TargetLowering::isNarrowingProfitable(EVT VT1, EVT VT2) const {
20488 // i16 instructions are longer (0x66 prefix) and potentially slower.
20489 return !(VT1 == MVT::i32 && VT2 == MVT::i16);
20492 /// isShuffleMaskLegal - Targets can use this to indicate that they only
20493 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
20494 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
20495 /// are assumed to be legal.
20497 X86TargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M,
20499 if (!VT.isSimple())
20502 // Not for i1 vectors
20503 if (VT.getSimpleVT().getScalarType() == MVT::i1)
20506 // Very little shuffling can be done for 64-bit vectors right now.
20507 if (VT.getSimpleVT().getSizeInBits() == 64)
20510 // We only care that the types being shuffled are legal. The lowering can
20511 // handle any possible shuffle mask that results.
20512 return isTypeLegal(VT.getSimpleVT());
20516 X86TargetLowering::isVectorClearMaskLegal(const SmallVectorImpl<int> &Mask,
20518 // Just delegate to the generic legality, clear masks aren't special.
20519 return isShuffleMaskLegal(Mask, VT);
20522 //===----------------------------------------------------------------------===//
20523 // X86 Scheduler Hooks
20524 //===----------------------------------------------------------------------===//
20526 /// Utility function to emit xbegin specifying the start of an RTM region.
20527 static MachineBasicBlock *EmitXBegin(MachineInstr *MI, MachineBasicBlock *MBB,
20528 const TargetInstrInfo *TII) {
20529 DebugLoc DL = MI->getDebugLoc();
20531 const BasicBlock *BB = MBB->getBasicBlock();
20532 MachineFunction::iterator I = ++MBB->getIterator();
20534 // For the v = xbegin(), we generate
20545 MachineBasicBlock *thisMBB = MBB;
20546 MachineFunction *MF = MBB->getParent();
20547 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
20548 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
20549 MF->insert(I, mainMBB);
20550 MF->insert(I, sinkMBB);
20552 // Transfer the remainder of BB and its successor edges to sinkMBB.
20553 sinkMBB->splice(sinkMBB->begin(), MBB,
20554 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
20555 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
20559 // # fallthrough to mainMBB
20560 // # abortion to sinkMBB
20561 BuildMI(thisMBB, DL, TII->get(X86::XBEGIN_4)).addMBB(sinkMBB);
20562 thisMBB->addSuccessor(mainMBB);
20563 thisMBB->addSuccessor(sinkMBB);
20567 BuildMI(mainMBB, DL, TII->get(X86::MOV32ri), X86::EAX).addImm(-1);
20568 mainMBB->addSuccessor(sinkMBB);
20571 // EAX is live into the sinkMBB
20572 sinkMBB->addLiveIn(X86::EAX);
20573 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
20574 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
20577 MI->eraseFromParent();
20581 // FIXME: When we get size specific XMM0 registers, i.e. XMM0_V16I8
20582 // or XMM0_V32I8 in AVX all of this code can be replaced with that
20583 // in the .td file.
20584 static MachineBasicBlock *EmitPCMPSTRM(MachineInstr *MI, MachineBasicBlock *BB,
20585 const TargetInstrInfo *TII) {
20587 switch (MI->getOpcode()) {
20588 default: llvm_unreachable("illegal opcode!");
20589 case X86::PCMPISTRM128REG: Opc = X86::PCMPISTRM128rr; break;
20590 case X86::VPCMPISTRM128REG: Opc = X86::VPCMPISTRM128rr; break;
20591 case X86::PCMPISTRM128MEM: Opc = X86::PCMPISTRM128rm; break;
20592 case X86::VPCMPISTRM128MEM: Opc = X86::VPCMPISTRM128rm; break;
20593 case X86::PCMPESTRM128REG: Opc = X86::PCMPESTRM128rr; break;
20594 case X86::VPCMPESTRM128REG: Opc = X86::VPCMPESTRM128rr; break;
20595 case X86::PCMPESTRM128MEM: Opc = X86::PCMPESTRM128rm; break;
20596 case X86::VPCMPESTRM128MEM: Opc = X86::VPCMPESTRM128rm; break;
20599 DebugLoc dl = MI->getDebugLoc();
20600 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(Opc));
20602 unsigned NumArgs = MI->getNumOperands();
20603 for (unsigned i = 1; i < NumArgs; ++i) {
20604 MachineOperand &Op = MI->getOperand(i);
20605 if (!(Op.isReg() && Op.isImplicit()))
20606 MIB.addOperand(Op);
20608 if (MI->hasOneMemOperand())
20609 MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
20611 BuildMI(*BB, MI, dl,
20612 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
20613 .addReg(X86::XMM0);
20615 MI->eraseFromParent();
20619 // FIXME: Custom handling because TableGen doesn't support multiple implicit
20620 // defs in an instruction pattern
20621 static MachineBasicBlock *EmitPCMPSTRI(MachineInstr *MI, MachineBasicBlock *BB,
20622 const TargetInstrInfo *TII) {
20624 switch (MI->getOpcode()) {
20625 default: llvm_unreachable("illegal opcode!");
20626 case X86::PCMPISTRIREG: Opc = X86::PCMPISTRIrr; break;
20627 case X86::VPCMPISTRIREG: Opc = X86::VPCMPISTRIrr; break;
20628 case X86::PCMPISTRIMEM: Opc = X86::PCMPISTRIrm; break;
20629 case X86::VPCMPISTRIMEM: Opc = X86::VPCMPISTRIrm; break;
20630 case X86::PCMPESTRIREG: Opc = X86::PCMPESTRIrr; break;
20631 case X86::VPCMPESTRIREG: Opc = X86::VPCMPESTRIrr; break;
20632 case X86::PCMPESTRIMEM: Opc = X86::PCMPESTRIrm; break;
20633 case X86::VPCMPESTRIMEM: Opc = X86::VPCMPESTRIrm; break;
20636 DebugLoc dl = MI->getDebugLoc();
20637 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(Opc));
20639 unsigned NumArgs = MI->getNumOperands(); // remove the results
20640 for (unsigned i = 1; i < NumArgs; ++i) {
20641 MachineOperand &Op = MI->getOperand(i);
20642 if (!(Op.isReg() && Op.isImplicit()))
20643 MIB.addOperand(Op);
20645 if (MI->hasOneMemOperand())
20646 MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
20648 BuildMI(*BB, MI, dl,
20649 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
20652 MI->eraseFromParent();
20656 static MachineBasicBlock *EmitMonitor(MachineInstr *MI, MachineBasicBlock *BB,
20657 const X86Subtarget *Subtarget) {
20658 DebugLoc dl = MI->getDebugLoc();
20659 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
20660 // Address into RAX/EAX, other two args into ECX, EDX.
20661 unsigned MemOpc = Subtarget->is64Bit() ? X86::LEA64r : X86::LEA32r;
20662 unsigned MemReg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
20663 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(MemOpc), MemReg);
20664 for (int i = 0; i < X86::AddrNumOperands; ++i)
20665 MIB.addOperand(MI->getOperand(i));
20667 unsigned ValOps = X86::AddrNumOperands;
20668 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::ECX)
20669 .addReg(MI->getOperand(ValOps).getReg());
20670 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::EDX)
20671 .addReg(MI->getOperand(ValOps+1).getReg());
20673 // The instruction doesn't actually take any operands though.
20674 BuildMI(*BB, MI, dl, TII->get(X86::MONITORrrr));
20676 MI->eraseFromParent(); // The pseudo is gone now.
20680 MachineBasicBlock *
20681 X86TargetLowering::EmitVAARG64WithCustomInserter(MachineInstr *MI,
20682 MachineBasicBlock *MBB) const {
20683 // Emit va_arg instruction on X86-64.
20685 // Operands to this pseudo-instruction:
20686 // 0 ) Output : destination address (reg)
20687 // 1-5) Input : va_list address (addr, i64mem)
20688 // 6 ) ArgSize : Size (in bytes) of vararg type
20689 // 7 ) ArgMode : 0=overflow only, 1=use gp_offset, 2=use fp_offset
20690 // 8 ) Align : Alignment of type
20691 // 9 ) EFLAGS (implicit-def)
20693 assert(MI->getNumOperands() == 10 && "VAARG_64 should have 10 operands!");
20694 static_assert(X86::AddrNumOperands == 5,
20695 "VAARG_64 assumes 5 address operands");
20697 unsigned DestReg = MI->getOperand(0).getReg();
20698 MachineOperand &Base = MI->getOperand(1);
20699 MachineOperand &Scale = MI->getOperand(2);
20700 MachineOperand &Index = MI->getOperand(3);
20701 MachineOperand &Disp = MI->getOperand(4);
20702 MachineOperand &Segment = MI->getOperand(5);
20703 unsigned ArgSize = MI->getOperand(6).getImm();
20704 unsigned ArgMode = MI->getOperand(7).getImm();
20705 unsigned Align = MI->getOperand(8).getImm();
20707 // Memory Reference
20708 assert(MI->hasOneMemOperand() && "Expected VAARG_64 to have one memoperand");
20709 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
20710 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
20712 // Machine Information
20713 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
20714 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
20715 const TargetRegisterClass *AddrRegClass = getRegClassFor(MVT::i64);
20716 const TargetRegisterClass *OffsetRegClass = getRegClassFor(MVT::i32);
20717 DebugLoc DL = MI->getDebugLoc();
20719 // struct va_list {
20722 // i64 overflow_area (address)
20723 // i64 reg_save_area (address)
20725 // sizeof(va_list) = 24
20726 // alignment(va_list) = 8
20728 unsigned TotalNumIntRegs = 6;
20729 unsigned TotalNumXMMRegs = 8;
20730 bool UseGPOffset = (ArgMode == 1);
20731 bool UseFPOffset = (ArgMode == 2);
20732 unsigned MaxOffset = TotalNumIntRegs * 8 +
20733 (UseFPOffset ? TotalNumXMMRegs * 16 : 0);
20735 /* Align ArgSize to a multiple of 8 */
20736 unsigned ArgSizeA8 = (ArgSize + 7) & ~7;
20737 bool NeedsAlign = (Align > 8);
20739 MachineBasicBlock *thisMBB = MBB;
20740 MachineBasicBlock *overflowMBB;
20741 MachineBasicBlock *offsetMBB;
20742 MachineBasicBlock *endMBB;
20744 unsigned OffsetDestReg = 0; // Argument address computed by offsetMBB
20745 unsigned OverflowDestReg = 0; // Argument address computed by overflowMBB
20746 unsigned OffsetReg = 0;
20748 if (!UseGPOffset && !UseFPOffset) {
20749 // If we only pull from the overflow region, we don't create a branch.
20750 // We don't need to alter control flow.
20751 OffsetDestReg = 0; // unused
20752 OverflowDestReg = DestReg;
20754 offsetMBB = nullptr;
20755 overflowMBB = thisMBB;
20758 // First emit code to check if gp_offset (or fp_offset) is below the bound.
20759 // If so, pull the argument from reg_save_area. (branch to offsetMBB)
20760 // If not, pull from overflow_area. (branch to overflowMBB)
20765 // offsetMBB overflowMBB
20770 // Registers for the PHI in endMBB
20771 OffsetDestReg = MRI.createVirtualRegister(AddrRegClass);
20772 OverflowDestReg = MRI.createVirtualRegister(AddrRegClass);
20774 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
20775 MachineFunction *MF = MBB->getParent();
20776 overflowMBB = MF->CreateMachineBasicBlock(LLVM_BB);
20777 offsetMBB = MF->CreateMachineBasicBlock(LLVM_BB);
20778 endMBB = MF->CreateMachineBasicBlock(LLVM_BB);
20780 MachineFunction::iterator MBBIter = ++MBB->getIterator();
20782 // Insert the new basic blocks
20783 MF->insert(MBBIter, offsetMBB);
20784 MF->insert(MBBIter, overflowMBB);
20785 MF->insert(MBBIter, endMBB);
20787 // Transfer the remainder of MBB and its successor edges to endMBB.
20788 endMBB->splice(endMBB->begin(), thisMBB,
20789 std::next(MachineBasicBlock::iterator(MI)), thisMBB->end());
20790 endMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
20792 // Make offsetMBB and overflowMBB successors of thisMBB
20793 thisMBB->addSuccessor(offsetMBB);
20794 thisMBB->addSuccessor(overflowMBB);
20796 // endMBB is a successor of both offsetMBB and overflowMBB
20797 offsetMBB->addSuccessor(endMBB);
20798 overflowMBB->addSuccessor(endMBB);
20800 // Load the offset value into a register
20801 OffsetReg = MRI.createVirtualRegister(OffsetRegClass);
20802 BuildMI(thisMBB, DL, TII->get(X86::MOV32rm), OffsetReg)
20806 .addDisp(Disp, UseFPOffset ? 4 : 0)
20807 .addOperand(Segment)
20808 .setMemRefs(MMOBegin, MMOEnd);
20810 // Check if there is enough room left to pull this argument.
20811 BuildMI(thisMBB, DL, TII->get(X86::CMP32ri))
20813 .addImm(MaxOffset + 8 - ArgSizeA8);
20815 // Branch to "overflowMBB" if offset >= max
20816 // Fall through to "offsetMBB" otherwise
20817 BuildMI(thisMBB, DL, TII->get(X86::GetCondBranchFromCond(X86::COND_AE)))
20818 .addMBB(overflowMBB);
20821 // In offsetMBB, emit code to use the reg_save_area.
20823 assert(OffsetReg != 0);
20825 // Read the reg_save_area address.
20826 unsigned RegSaveReg = MRI.createVirtualRegister(AddrRegClass);
20827 BuildMI(offsetMBB, DL, TII->get(X86::MOV64rm), RegSaveReg)
20832 .addOperand(Segment)
20833 .setMemRefs(MMOBegin, MMOEnd);
20835 // Zero-extend the offset
20836 unsigned OffsetReg64 = MRI.createVirtualRegister(AddrRegClass);
20837 BuildMI(offsetMBB, DL, TII->get(X86::SUBREG_TO_REG), OffsetReg64)
20840 .addImm(X86::sub_32bit);
20842 // Add the offset to the reg_save_area to get the final address.
20843 BuildMI(offsetMBB, DL, TII->get(X86::ADD64rr), OffsetDestReg)
20844 .addReg(OffsetReg64)
20845 .addReg(RegSaveReg);
20847 // Compute the offset for the next argument
20848 unsigned NextOffsetReg = MRI.createVirtualRegister(OffsetRegClass);
20849 BuildMI(offsetMBB, DL, TII->get(X86::ADD32ri), NextOffsetReg)
20851 .addImm(UseFPOffset ? 16 : 8);
20853 // Store it back into the va_list.
20854 BuildMI(offsetMBB, DL, TII->get(X86::MOV32mr))
20858 .addDisp(Disp, UseFPOffset ? 4 : 0)
20859 .addOperand(Segment)
20860 .addReg(NextOffsetReg)
20861 .setMemRefs(MMOBegin, MMOEnd);
20864 BuildMI(offsetMBB, DL, TII->get(X86::JMP_1))
20869 // Emit code to use overflow area
20872 // Load the overflow_area address into a register.
20873 unsigned OverflowAddrReg = MRI.createVirtualRegister(AddrRegClass);
20874 BuildMI(overflowMBB, DL, TII->get(X86::MOV64rm), OverflowAddrReg)
20879 .addOperand(Segment)
20880 .setMemRefs(MMOBegin, MMOEnd);
20882 // If we need to align it, do so. Otherwise, just copy the address
20883 // to OverflowDestReg.
20885 // Align the overflow address
20886 assert((Align & (Align-1)) == 0 && "Alignment must be a power of 2");
20887 unsigned TmpReg = MRI.createVirtualRegister(AddrRegClass);
20889 // aligned_addr = (addr + (align-1)) & ~(align-1)
20890 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), TmpReg)
20891 .addReg(OverflowAddrReg)
20894 BuildMI(overflowMBB, DL, TII->get(X86::AND64ri32), OverflowDestReg)
20896 .addImm(~(uint64_t)(Align-1));
20898 BuildMI(overflowMBB, DL, TII->get(TargetOpcode::COPY), OverflowDestReg)
20899 .addReg(OverflowAddrReg);
20902 // Compute the next overflow address after this argument.
20903 // (the overflow address should be kept 8-byte aligned)
20904 unsigned NextAddrReg = MRI.createVirtualRegister(AddrRegClass);
20905 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), NextAddrReg)
20906 .addReg(OverflowDestReg)
20907 .addImm(ArgSizeA8);
20909 // Store the new overflow address.
20910 BuildMI(overflowMBB, DL, TII->get(X86::MOV64mr))
20915 .addOperand(Segment)
20916 .addReg(NextAddrReg)
20917 .setMemRefs(MMOBegin, MMOEnd);
20919 // If we branched, emit the PHI to the front of endMBB.
20921 BuildMI(*endMBB, endMBB->begin(), DL,
20922 TII->get(X86::PHI), DestReg)
20923 .addReg(OffsetDestReg).addMBB(offsetMBB)
20924 .addReg(OverflowDestReg).addMBB(overflowMBB);
20927 // Erase the pseudo instruction
20928 MI->eraseFromParent();
20933 MachineBasicBlock *
20934 X86TargetLowering::EmitVAStartSaveXMMRegsWithCustomInserter(
20936 MachineBasicBlock *MBB) const {
20937 // Emit code to save XMM registers to the stack. The ABI says that the
20938 // number of registers to save is given in %al, so it's theoretically
20939 // possible to do an indirect jump trick to avoid saving all of them,
20940 // however this code takes a simpler approach and just executes all
20941 // of the stores if %al is non-zero. It's less code, and it's probably
20942 // easier on the hardware branch predictor, and stores aren't all that
20943 // expensive anyway.
20945 // Create the new basic blocks. One block contains all the XMM stores,
20946 // and one block is the final destination regardless of whether any
20947 // stores were performed.
20948 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
20949 MachineFunction *F = MBB->getParent();
20950 MachineFunction::iterator MBBIter = ++MBB->getIterator();
20951 MachineBasicBlock *XMMSaveMBB = F->CreateMachineBasicBlock(LLVM_BB);
20952 MachineBasicBlock *EndMBB = F->CreateMachineBasicBlock(LLVM_BB);
20953 F->insert(MBBIter, XMMSaveMBB);
20954 F->insert(MBBIter, EndMBB);
20956 // Transfer the remainder of MBB and its successor edges to EndMBB.
20957 EndMBB->splice(EndMBB->begin(), MBB,
20958 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
20959 EndMBB->transferSuccessorsAndUpdatePHIs(MBB);
20961 // The original block will now fall through to the XMM save block.
20962 MBB->addSuccessor(XMMSaveMBB);
20963 // The XMMSaveMBB will fall through to the end block.
20964 XMMSaveMBB->addSuccessor(EndMBB);
20966 // Now add the instructions.
20967 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
20968 DebugLoc DL = MI->getDebugLoc();
20970 unsigned CountReg = MI->getOperand(0).getReg();
20971 int64_t RegSaveFrameIndex = MI->getOperand(1).getImm();
20972 int64_t VarArgsFPOffset = MI->getOperand(2).getImm();
20974 if (!Subtarget->isCallingConvWin64(F->getFunction()->getCallingConv())) {
20975 // If %al is 0, branch around the XMM save block.
20976 BuildMI(MBB, DL, TII->get(X86::TEST8rr)).addReg(CountReg).addReg(CountReg);
20977 BuildMI(MBB, DL, TII->get(X86::JE_1)).addMBB(EndMBB);
20978 MBB->addSuccessor(EndMBB);
20981 // Make sure the last operand is EFLAGS, which gets clobbered by the branch
20982 // that was just emitted, but clearly shouldn't be "saved".
20983 assert((MI->getNumOperands() <= 3 ||
20984 !MI->getOperand(MI->getNumOperands() - 1).isReg() ||
20985 MI->getOperand(MI->getNumOperands() - 1).getReg() == X86::EFLAGS)
20986 && "Expected last argument to be EFLAGS");
20987 unsigned MOVOpc = Subtarget->hasFp256() ? X86::VMOVAPSmr : X86::MOVAPSmr;
20988 // In the XMM save block, save all the XMM argument registers.
20989 for (int i = 3, e = MI->getNumOperands() - 1; i != e; ++i) {
20990 int64_t Offset = (i - 3) * 16 + VarArgsFPOffset;
20991 MachineMemOperand *MMO = F->getMachineMemOperand(
20992 MachinePointerInfo::getFixedStack(*F, RegSaveFrameIndex, Offset),
20993 MachineMemOperand::MOStore,
20994 /*Size=*/16, /*Align=*/16);
20995 BuildMI(XMMSaveMBB, DL, TII->get(MOVOpc))
20996 .addFrameIndex(RegSaveFrameIndex)
20997 .addImm(/*Scale=*/1)
20998 .addReg(/*IndexReg=*/0)
20999 .addImm(/*Disp=*/Offset)
21000 .addReg(/*Segment=*/0)
21001 .addReg(MI->getOperand(i).getReg())
21002 .addMemOperand(MMO);
21005 MI->eraseFromParent(); // The pseudo instruction is gone now.
21010 // The EFLAGS operand of SelectItr might be missing a kill marker
21011 // because there were multiple uses of EFLAGS, and ISel didn't know
21012 // which to mark. Figure out whether SelectItr should have had a
21013 // kill marker, and set it if it should. Returns the correct kill
21015 static bool checkAndUpdateEFLAGSKill(MachineBasicBlock::iterator SelectItr,
21016 MachineBasicBlock* BB,
21017 const TargetRegisterInfo* TRI) {
21018 // Scan forward through BB for a use/def of EFLAGS.
21019 MachineBasicBlock::iterator miI(std::next(SelectItr));
21020 for (MachineBasicBlock::iterator miE = BB->end(); miI != miE; ++miI) {
21021 const MachineInstr& mi = *miI;
21022 if (mi.readsRegister(X86::EFLAGS))
21024 if (mi.definesRegister(X86::EFLAGS))
21025 break; // Should have kill-flag - update below.
21028 // If we hit the end of the block, check whether EFLAGS is live into a
21030 if (miI == BB->end()) {
21031 for (MachineBasicBlock::succ_iterator sItr = BB->succ_begin(),
21032 sEnd = BB->succ_end();
21033 sItr != sEnd; ++sItr) {
21034 MachineBasicBlock* succ = *sItr;
21035 if (succ->isLiveIn(X86::EFLAGS))
21040 // We found a def, or hit the end of the basic block and EFLAGS wasn't live
21041 // out. SelectMI should have a kill flag on EFLAGS.
21042 SelectItr->addRegisterKilled(X86::EFLAGS, TRI);
21046 // Return true if it is OK for this CMOV pseudo-opcode to be cascaded
21047 // together with other CMOV pseudo-opcodes into a single basic-block with
21048 // conditional jump around it.
21049 static bool isCMOVPseudo(MachineInstr *MI) {
21050 switch (MI->getOpcode()) {
21051 case X86::CMOV_FR32:
21052 case X86::CMOV_FR64:
21053 case X86::CMOV_GR8:
21054 case X86::CMOV_GR16:
21055 case X86::CMOV_GR32:
21056 case X86::CMOV_RFP32:
21057 case X86::CMOV_RFP64:
21058 case X86::CMOV_RFP80:
21059 case X86::CMOV_V2F64:
21060 case X86::CMOV_V2I64:
21061 case X86::CMOV_V4F32:
21062 case X86::CMOV_V4F64:
21063 case X86::CMOV_V4I64:
21064 case X86::CMOV_V16F32:
21065 case X86::CMOV_V8F32:
21066 case X86::CMOV_V8F64:
21067 case X86::CMOV_V8I64:
21068 case X86::CMOV_V8I1:
21069 case X86::CMOV_V16I1:
21070 case X86::CMOV_V32I1:
21071 case X86::CMOV_V64I1:
21079 MachineBasicBlock *
21080 X86TargetLowering::EmitLoweredSelect(MachineInstr *MI,
21081 MachineBasicBlock *BB) const {
21082 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
21083 DebugLoc DL = MI->getDebugLoc();
21085 // To "insert" a SELECT_CC instruction, we actually have to insert the
21086 // diamond control-flow pattern. The incoming instruction knows the
21087 // destination vreg to set, the condition code register to branch on, the
21088 // true/false values to select between, and a branch opcode to use.
21089 const BasicBlock *LLVM_BB = BB->getBasicBlock();
21090 MachineFunction::iterator It = ++BB->getIterator();
21095 // cmpTY ccX, r1, r2
21097 // fallthrough --> copy0MBB
21098 MachineBasicBlock *thisMBB = BB;
21099 MachineFunction *F = BB->getParent();
21101 // This code lowers all pseudo-CMOV instructions. Generally it lowers these
21102 // as described above, by inserting a BB, and then making a PHI at the join
21103 // point to select the true and false operands of the CMOV in the PHI.
21105 // The code also handles two different cases of multiple CMOV opcodes
21109 // In this case, there are multiple CMOVs in a row, all which are based on
21110 // the same condition setting (or the exact opposite condition setting).
21111 // In this case we can lower all the CMOVs using a single inserted BB, and
21112 // then make a number of PHIs at the join point to model the CMOVs. The only
21113 // trickiness here, is that in a case like:
21115 // t2 = CMOV cond1 t1, f1
21116 // t3 = CMOV cond1 t2, f2
21118 // when rewriting this into PHIs, we have to perform some renaming on the
21119 // temps since you cannot have a PHI operand refer to a PHI result earlier
21120 // in the same block. The "simple" but wrong lowering would be:
21122 // t2 = PHI t1(BB1), f1(BB2)
21123 // t3 = PHI t2(BB1), f2(BB2)
21125 // but clearly t2 is not defined in BB1, so that is incorrect. The proper
21126 // renaming is to note that on the path through BB1, t2 is really just a
21127 // copy of t1, and do that renaming, properly generating:
21129 // t2 = PHI t1(BB1), f1(BB2)
21130 // t3 = PHI t1(BB1), f2(BB2)
21132 // Case 2, we lower cascaded CMOVs such as
21134 // (CMOV (CMOV F, T, cc1), T, cc2)
21136 // to two successives branches. For that, we look for another CMOV as the
21137 // following instruction.
21139 // Without this, we would add a PHI between the two jumps, which ends up
21140 // creating a few copies all around. For instance, for
21142 // (sitofp (zext (fcmp une)))
21144 // we would generate:
21146 // ucomiss %xmm1, %xmm0
21147 // movss <1.0f>, %xmm0
21148 // movaps %xmm0, %xmm1
21150 // xorps %xmm1, %xmm1
21153 // movaps %xmm1, %xmm0
21157 // because this custom-inserter would have generated:
21169 // A: X = ...; Y = ...
21171 // C: Z = PHI [X, A], [Y, B]
21173 // E: PHI [X, C], [Z, D]
21175 // If we lower both CMOVs in a single step, we can instead generate:
21187 // A: X = ...; Y = ...
21189 // E: PHI [X, A], [X, C], [Y, D]
21191 // Which, in our sitofp/fcmp example, gives us something like:
21193 // ucomiss %xmm1, %xmm0
21194 // movss <1.0f>, %xmm0
21197 // xorps %xmm0, %xmm0
21201 MachineInstr *CascadedCMOV = nullptr;
21202 MachineInstr *LastCMOV = MI;
21203 X86::CondCode CC = X86::CondCode(MI->getOperand(3).getImm());
21204 X86::CondCode OppCC = X86::GetOppositeBranchCondition(CC);
21205 MachineBasicBlock::iterator NextMIIt =
21206 std::next(MachineBasicBlock::iterator(MI));
21208 // Check for case 1, where there are multiple CMOVs with the same condition
21209 // first. Of the two cases of multiple CMOV lowerings, case 1 reduces the
21210 // number of jumps the most.
21212 if (isCMOVPseudo(MI)) {
21213 // See if we have a string of CMOVS with the same condition.
21214 while (NextMIIt != BB->end() &&
21215 isCMOVPseudo(NextMIIt) &&
21216 (NextMIIt->getOperand(3).getImm() == CC ||
21217 NextMIIt->getOperand(3).getImm() == OppCC)) {
21218 LastCMOV = &*NextMIIt;
21223 // This checks for case 2, but only do this if we didn't already find
21224 // case 1, as indicated by LastCMOV == MI.
21225 if (LastCMOV == MI &&
21226 NextMIIt != BB->end() && NextMIIt->getOpcode() == MI->getOpcode() &&
21227 NextMIIt->getOperand(2).getReg() == MI->getOperand(2).getReg() &&
21228 NextMIIt->getOperand(1).getReg() == MI->getOperand(0).getReg()) {
21229 CascadedCMOV = &*NextMIIt;
21232 MachineBasicBlock *jcc1MBB = nullptr;
21234 // If we have a cascaded CMOV, we lower it to two successive branches to
21235 // the same block. EFLAGS is used by both, so mark it as live in the second.
21236 if (CascadedCMOV) {
21237 jcc1MBB = F->CreateMachineBasicBlock(LLVM_BB);
21238 F->insert(It, jcc1MBB);
21239 jcc1MBB->addLiveIn(X86::EFLAGS);
21242 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
21243 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
21244 F->insert(It, copy0MBB);
21245 F->insert(It, sinkMBB);
21247 // If the EFLAGS register isn't dead in the terminator, then claim that it's
21248 // live into the sink and copy blocks.
21249 const TargetRegisterInfo *TRI = Subtarget->getRegisterInfo();
21251 MachineInstr *LastEFLAGSUser = CascadedCMOV ? CascadedCMOV : LastCMOV;
21252 if (!LastEFLAGSUser->killsRegister(X86::EFLAGS) &&
21253 !checkAndUpdateEFLAGSKill(LastEFLAGSUser, BB, TRI)) {
21254 copy0MBB->addLiveIn(X86::EFLAGS);
21255 sinkMBB->addLiveIn(X86::EFLAGS);
21258 // Transfer the remainder of BB and its successor edges to sinkMBB.
21259 sinkMBB->splice(sinkMBB->begin(), BB,
21260 std::next(MachineBasicBlock::iterator(LastCMOV)), BB->end());
21261 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
21263 // Add the true and fallthrough blocks as its successors.
21264 if (CascadedCMOV) {
21265 // The fallthrough block may be jcc1MBB, if we have a cascaded CMOV.
21266 BB->addSuccessor(jcc1MBB);
21268 // In that case, jcc1MBB will itself fallthrough the copy0MBB, and
21269 // jump to the sinkMBB.
21270 jcc1MBB->addSuccessor(copy0MBB);
21271 jcc1MBB->addSuccessor(sinkMBB);
21273 BB->addSuccessor(copy0MBB);
21276 // The true block target of the first (or only) branch is always sinkMBB.
21277 BB->addSuccessor(sinkMBB);
21279 // Create the conditional branch instruction.
21280 unsigned Opc = X86::GetCondBranchFromCond(CC);
21281 BuildMI(BB, DL, TII->get(Opc)).addMBB(sinkMBB);
21283 if (CascadedCMOV) {
21284 unsigned Opc2 = X86::GetCondBranchFromCond(
21285 (X86::CondCode)CascadedCMOV->getOperand(3).getImm());
21286 BuildMI(jcc1MBB, DL, TII->get(Opc2)).addMBB(sinkMBB);
21290 // %FalseValue = ...
21291 // # fallthrough to sinkMBB
21292 copy0MBB->addSuccessor(sinkMBB);
21295 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
21297 MachineBasicBlock::iterator MIItBegin = MachineBasicBlock::iterator(MI);
21298 MachineBasicBlock::iterator MIItEnd =
21299 std::next(MachineBasicBlock::iterator(LastCMOV));
21300 MachineBasicBlock::iterator SinkInsertionPoint = sinkMBB->begin();
21301 DenseMap<unsigned, std::pair<unsigned, unsigned>> RegRewriteTable;
21302 MachineInstrBuilder MIB;
21304 // As we are creating the PHIs, we have to be careful if there is more than
21305 // one. Later CMOVs may reference the results of earlier CMOVs, but later
21306 // PHIs have to reference the individual true/false inputs from earlier PHIs.
21307 // That also means that PHI construction must work forward from earlier to
21308 // later, and that the code must maintain a mapping from earlier PHI's
21309 // destination registers, and the registers that went into the PHI.
21311 for (MachineBasicBlock::iterator MIIt = MIItBegin; MIIt != MIItEnd; ++MIIt) {
21312 unsigned DestReg = MIIt->getOperand(0).getReg();
21313 unsigned Op1Reg = MIIt->getOperand(1).getReg();
21314 unsigned Op2Reg = MIIt->getOperand(2).getReg();
21316 // If this CMOV we are generating is the opposite condition from
21317 // the jump we generated, then we have to swap the operands for the
21318 // PHI that is going to be generated.
21319 if (MIIt->getOperand(3).getImm() == OppCC)
21320 std::swap(Op1Reg, Op2Reg);
21322 if (RegRewriteTable.find(Op1Reg) != RegRewriteTable.end())
21323 Op1Reg = RegRewriteTable[Op1Reg].first;
21325 if (RegRewriteTable.find(Op2Reg) != RegRewriteTable.end())
21326 Op2Reg = RegRewriteTable[Op2Reg].second;
21328 MIB = BuildMI(*sinkMBB, SinkInsertionPoint, DL,
21329 TII->get(X86::PHI), DestReg)
21330 .addReg(Op1Reg).addMBB(copy0MBB)
21331 .addReg(Op2Reg).addMBB(thisMBB);
21333 // Add this PHI to the rewrite table.
21334 RegRewriteTable[DestReg] = std::make_pair(Op1Reg, Op2Reg);
21337 // If we have a cascaded CMOV, the second Jcc provides the same incoming
21338 // value as the first Jcc (the True operand of the SELECT_CC/CMOV nodes).
21339 if (CascadedCMOV) {
21340 MIB.addReg(MI->getOperand(2).getReg()).addMBB(jcc1MBB);
21341 // Copy the PHI result to the register defined by the second CMOV.
21342 BuildMI(*sinkMBB, std::next(MachineBasicBlock::iterator(MIB.getInstr())),
21343 DL, TII->get(TargetOpcode::COPY),
21344 CascadedCMOV->getOperand(0).getReg())
21345 .addReg(MI->getOperand(0).getReg());
21346 CascadedCMOV->eraseFromParent();
21349 // Now remove the CMOV(s).
21350 for (MachineBasicBlock::iterator MIIt = MIItBegin; MIIt != MIItEnd; )
21351 (MIIt++)->eraseFromParent();
21356 MachineBasicBlock *
21357 X86TargetLowering::EmitLoweredAtomicFP(MachineInstr *MI,
21358 MachineBasicBlock *BB) const {
21359 // Combine the following atomic floating-point modification pattern:
21360 // a.store(reg OP a.load(acquire), release)
21361 // Transform them into:
21362 // OPss (%gpr), %xmm
21363 // movss %xmm, (%gpr)
21364 // Or sd equivalent for 64-bit operations.
21366 switch (MI->getOpcode()) {
21367 default: llvm_unreachable("unexpected instr type for EmitLoweredAtomicFP");
21368 case X86::RELEASE_FADD32mr: MOp = X86::MOVSSmr; FOp = X86::ADDSSrm; break;
21369 case X86::RELEASE_FADD64mr: MOp = X86::MOVSDmr; FOp = X86::ADDSDrm; break;
21371 const X86InstrInfo *TII = Subtarget->getInstrInfo();
21372 DebugLoc DL = MI->getDebugLoc();
21373 MachineRegisterInfo &MRI = BB->getParent()->getRegInfo();
21374 MachineOperand MSrc = MI->getOperand(0);
21375 unsigned VSrc = MI->getOperand(5).getReg();
21376 const MachineOperand &Disp = MI->getOperand(3);
21377 MachineOperand ZeroDisp = MachineOperand::CreateImm(0);
21378 bool hasDisp = Disp.isGlobal() || Disp.isImm();
21379 if (hasDisp && MSrc.isReg())
21380 MSrc.setIsKill(false);
21381 MachineInstrBuilder MIM = BuildMI(*BB, MI, DL, TII->get(MOp))
21382 .addOperand(/*Base=*/MSrc)
21383 .addImm(/*Scale=*/1)
21384 .addReg(/*Index=*/0)
21385 .addDisp(hasDisp ? Disp : ZeroDisp, /*off=*/0)
21387 MachineInstr *MIO = BuildMI(*BB, (MachineInstr *)MIM, DL, TII->get(FOp),
21388 MRI.createVirtualRegister(MRI.getRegClass(VSrc)))
21390 .addOperand(/*Base=*/MSrc)
21391 .addImm(/*Scale=*/1)
21392 .addReg(/*Index=*/0)
21393 .addDisp(hasDisp ? Disp : ZeroDisp, /*off=*/0)
21394 .addReg(/*Segment=*/0);
21395 MIM.addReg(MIO->getOperand(0).getReg(), RegState::Kill);
21396 MI->eraseFromParent(); // The pseudo instruction is gone now.
21400 MachineBasicBlock *
21401 X86TargetLowering::EmitLoweredSegAlloca(MachineInstr *MI,
21402 MachineBasicBlock *BB) const {
21403 MachineFunction *MF = BB->getParent();
21404 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
21405 DebugLoc DL = MI->getDebugLoc();
21406 const BasicBlock *LLVM_BB = BB->getBasicBlock();
21408 assert(MF->shouldSplitStack());
21410 const bool Is64Bit = Subtarget->is64Bit();
21411 const bool IsLP64 = Subtarget->isTarget64BitLP64();
21413 const unsigned TlsReg = Is64Bit ? X86::FS : X86::GS;
21414 const unsigned TlsOffset = IsLP64 ? 0x70 : Is64Bit ? 0x40 : 0x30;
21417 // ... [Till the alloca]
21418 // If stacklet is not large enough, jump to mallocMBB
21421 // Allocate by subtracting from RSP
21422 // Jump to continueMBB
21425 // Allocate by call to runtime
21429 // [rest of original BB]
21432 MachineBasicBlock *mallocMBB = MF->CreateMachineBasicBlock(LLVM_BB);
21433 MachineBasicBlock *bumpMBB = MF->CreateMachineBasicBlock(LLVM_BB);
21434 MachineBasicBlock *continueMBB = MF->CreateMachineBasicBlock(LLVM_BB);
21436 MachineRegisterInfo &MRI = MF->getRegInfo();
21437 const TargetRegisterClass *AddrRegClass =
21438 getRegClassFor(getPointerTy(MF->getDataLayout()));
21440 unsigned mallocPtrVReg = MRI.createVirtualRegister(AddrRegClass),
21441 bumpSPPtrVReg = MRI.createVirtualRegister(AddrRegClass),
21442 tmpSPVReg = MRI.createVirtualRegister(AddrRegClass),
21443 SPLimitVReg = MRI.createVirtualRegister(AddrRegClass),
21444 sizeVReg = MI->getOperand(1).getReg(),
21445 physSPReg = IsLP64 || Subtarget->isTargetNaCl64() ? X86::RSP : X86::ESP;
21447 MachineFunction::iterator MBBIter = ++BB->getIterator();
21449 MF->insert(MBBIter, bumpMBB);
21450 MF->insert(MBBIter, mallocMBB);
21451 MF->insert(MBBIter, continueMBB);
21453 continueMBB->splice(continueMBB->begin(), BB,
21454 std::next(MachineBasicBlock::iterator(MI)), BB->end());
21455 continueMBB->transferSuccessorsAndUpdatePHIs(BB);
21457 // Add code to the main basic block to check if the stack limit has been hit,
21458 // and if so, jump to mallocMBB otherwise to bumpMBB.
21459 BuildMI(BB, DL, TII->get(TargetOpcode::COPY), tmpSPVReg).addReg(physSPReg);
21460 BuildMI(BB, DL, TII->get(IsLP64 ? X86::SUB64rr:X86::SUB32rr), SPLimitVReg)
21461 .addReg(tmpSPVReg).addReg(sizeVReg);
21462 BuildMI(BB, DL, TII->get(IsLP64 ? X86::CMP64mr:X86::CMP32mr))
21463 .addReg(0).addImm(1).addReg(0).addImm(TlsOffset).addReg(TlsReg)
21464 .addReg(SPLimitVReg);
21465 BuildMI(BB, DL, TII->get(X86::JG_1)).addMBB(mallocMBB);
21467 // bumpMBB simply decreases the stack pointer, since we know the current
21468 // stacklet has enough space.
21469 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), physSPReg)
21470 .addReg(SPLimitVReg);
21471 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), bumpSPPtrVReg)
21472 .addReg(SPLimitVReg);
21473 BuildMI(bumpMBB, DL, TII->get(X86::JMP_1)).addMBB(continueMBB);
21475 // Calls into a routine in libgcc to allocate more space from the heap.
21476 const uint32_t *RegMask =
21477 Subtarget->getRegisterInfo()->getCallPreservedMask(*MF, CallingConv::C);
21479 BuildMI(mallocMBB, DL, TII->get(X86::MOV64rr), X86::RDI)
21481 BuildMI(mallocMBB, DL, TII->get(X86::CALL64pcrel32))
21482 .addExternalSymbol("__morestack_allocate_stack_space")
21483 .addRegMask(RegMask)
21484 .addReg(X86::RDI, RegState::Implicit)
21485 .addReg(X86::RAX, RegState::ImplicitDefine);
21486 } else if (Is64Bit) {
21487 BuildMI(mallocMBB, DL, TII->get(X86::MOV32rr), X86::EDI)
21489 BuildMI(mallocMBB, DL, TII->get(X86::CALL64pcrel32))
21490 .addExternalSymbol("__morestack_allocate_stack_space")
21491 .addRegMask(RegMask)
21492 .addReg(X86::EDI, RegState::Implicit)
21493 .addReg(X86::EAX, RegState::ImplicitDefine);
21495 BuildMI(mallocMBB, DL, TII->get(X86::SUB32ri), physSPReg).addReg(physSPReg)
21497 BuildMI(mallocMBB, DL, TII->get(X86::PUSH32r)).addReg(sizeVReg);
21498 BuildMI(mallocMBB, DL, TII->get(X86::CALLpcrel32))
21499 .addExternalSymbol("__morestack_allocate_stack_space")
21500 .addRegMask(RegMask)
21501 .addReg(X86::EAX, RegState::ImplicitDefine);
21505 BuildMI(mallocMBB, DL, TII->get(X86::ADD32ri), physSPReg).addReg(physSPReg)
21508 BuildMI(mallocMBB, DL, TII->get(TargetOpcode::COPY), mallocPtrVReg)
21509 .addReg(IsLP64 ? X86::RAX : X86::EAX);
21510 BuildMI(mallocMBB, DL, TII->get(X86::JMP_1)).addMBB(continueMBB);
21512 // Set up the CFG correctly.
21513 BB->addSuccessor(bumpMBB);
21514 BB->addSuccessor(mallocMBB);
21515 mallocMBB->addSuccessor(continueMBB);
21516 bumpMBB->addSuccessor(continueMBB);
21518 // Take care of the PHI nodes.
21519 BuildMI(*continueMBB, continueMBB->begin(), DL, TII->get(X86::PHI),
21520 MI->getOperand(0).getReg())
21521 .addReg(mallocPtrVReg).addMBB(mallocMBB)
21522 .addReg(bumpSPPtrVReg).addMBB(bumpMBB);
21524 // Delete the original pseudo instruction.
21525 MI->eraseFromParent();
21528 return continueMBB;
21531 MachineBasicBlock *
21532 X86TargetLowering::EmitLoweredWinAlloca(MachineInstr *MI,
21533 MachineBasicBlock *BB) const {
21534 assert(!Subtarget->isTargetMachO());
21535 DebugLoc DL = MI->getDebugLoc();
21536 MachineInstr *ResumeMI = Subtarget->getFrameLowering()->emitStackProbe(
21537 *BB->getParent(), *BB, MI, DL, false);
21538 MachineBasicBlock *ResumeBB = ResumeMI->getParent();
21539 MI->eraseFromParent(); // The pseudo instruction is gone now.
21543 MachineBasicBlock *
21544 X86TargetLowering::EmitLoweredCatchRet(MachineInstr *MI,
21545 MachineBasicBlock *BB) const {
21546 MachineFunction *MF = BB->getParent();
21547 const TargetInstrInfo &TII = *Subtarget->getInstrInfo();
21548 MachineBasicBlock *TargetMBB = MI->getOperand(0).getMBB();
21549 DebugLoc DL = MI->getDebugLoc();
21551 assert(!isAsynchronousEHPersonality(
21552 classifyEHPersonality(MF->getFunction()->getPersonalityFn())) &&
21553 "SEH does not use catchret!");
21555 // Only 32-bit EH needs to worry about manually restoring stack pointers.
21556 if (!Subtarget->is32Bit())
21559 // C++ EH creates a new target block to hold the restore code, and wires up
21560 // the new block to the return destination with a normal JMP_4.
21561 MachineBasicBlock *RestoreMBB =
21562 MF->CreateMachineBasicBlock(BB->getBasicBlock());
21563 assert(BB->succ_size() == 1);
21564 MF->insert(std::next(BB->getIterator()), RestoreMBB);
21565 RestoreMBB->transferSuccessorsAndUpdatePHIs(BB);
21566 BB->addSuccessor(RestoreMBB);
21567 MI->getOperand(0).setMBB(RestoreMBB);
21569 auto RestoreMBBI = RestoreMBB->begin();
21570 BuildMI(*RestoreMBB, RestoreMBBI, DL, TII.get(X86::EH_RESTORE));
21571 BuildMI(*RestoreMBB, RestoreMBBI, DL, TII.get(X86::JMP_4)).addMBB(TargetMBB);
21575 MachineBasicBlock *
21576 X86TargetLowering::EmitLoweredCatchPad(MachineInstr *MI,
21577 MachineBasicBlock *BB) const {
21578 MachineFunction *MF = BB->getParent();
21579 const Constant *PerFn = MF->getFunction()->getPersonalityFn();
21580 bool IsSEH = isAsynchronousEHPersonality(classifyEHPersonality(PerFn));
21581 // Only 32-bit SEH requires special handling for catchpad.
21582 if (IsSEH && Subtarget->is32Bit()) {
21583 const TargetInstrInfo &TII = *Subtarget->getInstrInfo();
21584 DebugLoc DL = MI->getDebugLoc();
21585 BuildMI(*BB, MI, DL, TII.get(X86::EH_RESTORE));
21587 MI->eraseFromParent();
21591 MachineBasicBlock *
21592 X86TargetLowering::EmitLoweredTLSCall(MachineInstr *MI,
21593 MachineBasicBlock *BB) const {
21594 // This is pretty easy. We're taking the value that we received from
21595 // our load from the relocation, sticking it in either RDI (x86-64)
21596 // or EAX and doing an indirect call. The return value will then
21597 // be in the normal return register.
21598 MachineFunction *F = BB->getParent();
21599 const X86InstrInfo *TII = Subtarget->getInstrInfo();
21600 DebugLoc DL = MI->getDebugLoc();
21602 assert(Subtarget->isTargetDarwin() && "Darwin only instr emitted?");
21603 assert(MI->getOperand(3).isGlobal() && "This should be a global");
21605 // Get a register mask for the lowered call.
21606 // FIXME: The 32-bit calls have non-standard calling conventions. Use a
21607 // proper register mask.
21608 const uint32_t *RegMask =
21609 Subtarget->is64Bit() ?
21610 Subtarget->getRegisterInfo()->getDarwinTLSCallPreservedMask() :
21611 Subtarget->getRegisterInfo()->getCallPreservedMask(*F, CallingConv::C);
21612 if (Subtarget->is64Bit()) {
21613 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
21614 TII->get(X86::MOV64rm), X86::RDI)
21616 .addImm(0).addReg(0)
21617 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
21618 MI->getOperand(3).getTargetFlags())
21620 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL64m));
21621 addDirectMem(MIB, X86::RDI);
21622 MIB.addReg(X86::RAX, RegState::ImplicitDefine).addRegMask(RegMask);
21623 } else if (F->getTarget().getRelocationModel() != Reloc::PIC_) {
21624 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
21625 TII->get(X86::MOV32rm), X86::EAX)
21627 .addImm(0).addReg(0)
21628 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
21629 MI->getOperand(3).getTargetFlags())
21631 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
21632 addDirectMem(MIB, X86::EAX);
21633 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask);
21635 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
21636 TII->get(X86::MOV32rm), X86::EAX)
21637 .addReg(TII->getGlobalBaseReg(F))
21638 .addImm(0).addReg(0)
21639 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
21640 MI->getOperand(3).getTargetFlags())
21642 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
21643 addDirectMem(MIB, X86::EAX);
21644 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask);
21647 MI->eraseFromParent(); // The pseudo instruction is gone now.
21651 MachineBasicBlock *
21652 X86TargetLowering::emitEHSjLjSetJmp(MachineInstr *MI,
21653 MachineBasicBlock *MBB) const {
21654 DebugLoc DL = MI->getDebugLoc();
21655 MachineFunction *MF = MBB->getParent();
21656 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
21657 MachineRegisterInfo &MRI = MF->getRegInfo();
21659 const BasicBlock *BB = MBB->getBasicBlock();
21660 MachineFunction::iterator I = ++MBB->getIterator();
21662 // Memory Reference
21663 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
21664 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
21667 unsigned MemOpndSlot = 0;
21669 unsigned CurOp = 0;
21671 DstReg = MI->getOperand(CurOp++).getReg();
21672 const TargetRegisterClass *RC = MRI.getRegClass(DstReg);
21673 assert(RC->hasType(MVT::i32) && "Invalid destination!");
21674 unsigned mainDstReg = MRI.createVirtualRegister(RC);
21675 unsigned restoreDstReg = MRI.createVirtualRegister(RC);
21677 MemOpndSlot = CurOp;
21679 MVT PVT = getPointerTy(MF->getDataLayout());
21680 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
21681 "Invalid Pointer Size!");
21683 // For v = setjmp(buf), we generate
21686 // buf[LabelOffset] = restoreMBB <-- takes address of restoreMBB
21687 // SjLjSetup restoreMBB
21693 // v = phi(main, restore)
21696 // if base pointer being used, load it from frame
21699 MachineBasicBlock *thisMBB = MBB;
21700 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
21701 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
21702 MachineBasicBlock *restoreMBB = MF->CreateMachineBasicBlock(BB);
21703 MF->insert(I, mainMBB);
21704 MF->insert(I, sinkMBB);
21705 MF->push_back(restoreMBB);
21706 restoreMBB->setHasAddressTaken();
21708 MachineInstrBuilder MIB;
21710 // Transfer the remainder of BB and its successor edges to sinkMBB.
21711 sinkMBB->splice(sinkMBB->begin(), MBB,
21712 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
21713 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
21716 unsigned PtrStoreOpc = 0;
21717 unsigned LabelReg = 0;
21718 const int64_t LabelOffset = 1 * PVT.getStoreSize();
21719 Reloc::Model RM = MF->getTarget().getRelocationModel();
21720 bool UseImmLabel = (MF->getTarget().getCodeModel() == CodeModel::Small) &&
21721 (RM == Reloc::Static || RM == Reloc::DynamicNoPIC);
21723 // Prepare IP either in reg or imm.
21724 if (!UseImmLabel) {
21725 PtrStoreOpc = (PVT == MVT::i64) ? X86::MOV64mr : X86::MOV32mr;
21726 const TargetRegisterClass *PtrRC = getRegClassFor(PVT);
21727 LabelReg = MRI.createVirtualRegister(PtrRC);
21728 if (Subtarget->is64Bit()) {
21729 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::LEA64r), LabelReg)
21733 .addMBB(restoreMBB)
21736 const X86InstrInfo *XII = static_cast<const X86InstrInfo*>(TII);
21737 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::LEA32r), LabelReg)
21738 .addReg(XII->getGlobalBaseReg(MF))
21741 .addMBB(restoreMBB, Subtarget->ClassifyBlockAddressReference())
21745 PtrStoreOpc = (PVT == MVT::i64) ? X86::MOV64mi32 : X86::MOV32mi;
21747 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PtrStoreOpc));
21748 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
21749 if (i == X86::AddrDisp)
21750 MIB.addDisp(MI->getOperand(MemOpndSlot + i), LabelOffset);
21752 MIB.addOperand(MI->getOperand(MemOpndSlot + i));
21755 MIB.addReg(LabelReg);
21757 MIB.addMBB(restoreMBB);
21758 MIB.setMemRefs(MMOBegin, MMOEnd);
21760 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::EH_SjLj_Setup))
21761 .addMBB(restoreMBB);
21763 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
21764 MIB.addRegMask(RegInfo->getNoPreservedMask());
21765 thisMBB->addSuccessor(mainMBB);
21766 thisMBB->addSuccessor(restoreMBB);
21770 BuildMI(mainMBB, DL, TII->get(X86::MOV32r0), mainDstReg);
21771 mainMBB->addSuccessor(sinkMBB);
21774 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
21775 TII->get(X86::PHI), DstReg)
21776 .addReg(mainDstReg).addMBB(mainMBB)
21777 .addReg(restoreDstReg).addMBB(restoreMBB);
21780 if (RegInfo->hasBasePointer(*MF)) {
21781 const bool Uses64BitFramePtr =
21782 Subtarget->isTarget64BitLP64() || Subtarget->isTargetNaCl64();
21783 X86MachineFunctionInfo *X86FI = MF->getInfo<X86MachineFunctionInfo>();
21784 X86FI->setRestoreBasePointer(MF);
21785 unsigned FramePtr = RegInfo->getFrameRegister(*MF);
21786 unsigned BasePtr = RegInfo->getBaseRegister();
21787 unsigned Opm = Uses64BitFramePtr ? X86::MOV64rm : X86::MOV32rm;
21788 addRegOffset(BuildMI(restoreMBB, DL, TII->get(Opm), BasePtr),
21789 FramePtr, true, X86FI->getRestoreBasePointerOffset())
21790 .setMIFlag(MachineInstr::FrameSetup);
21792 BuildMI(restoreMBB, DL, TII->get(X86::MOV32ri), restoreDstReg).addImm(1);
21793 BuildMI(restoreMBB, DL, TII->get(X86::JMP_1)).addMBB(sinkMBB);
21794 restoreMBB->addSuccessor(sinkMBB);
21796 MI->eraseFromParent();
21800 MachineBasicBlock *
21801 X86TargetLowering::emitEHSjLjLongJmp(MachineInstr *MI,
21802 MachineBasicBlock *MBB) const {
21803 DebugLoc DL = MI->getDebugLoc();
21804 MachineFunction *MF = MBB->getParent();
21805 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
21806 MachineRegisterInfo &MRI = MF->getRegInfo();
21808 // Memory Reference
21809 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
21810 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
21812 MVT PVT = getPointerTy(MF->getDataLayout());
21813 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
21814 "Invalid Pointer Size!");
21816 const TargetRegisterClass *RC =
21817 (PVT == MVT::i64) ? &X86::GR64RegClass : &X86::GR32RegClass;
21818 unsigned Tmp = MRI.createVirtualRegister(RC);
21819 // Since FP is only updated here but NOT referenced, it's treated as GPR.
21820 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
21821 unsigned FP = (PVT == MVT::i64) ? X86::RBP : X86::EBP;
21822 unsigned SP = RegInfo->getStackRegister();
21824 MachineInstrBuilder MIB;
21826 const int64_t LabelOffset = 1 * PVT.getStoreSize();
21827 const int64_t SPOffset = 2 * PVT.getStoreSize();
21829 unsigned PtrLoadOpc = (PVT == MVT::i64) ? X86::MOV64rm : X86::MOV32rm;
21830 unsigned IJmpOpc = (PVT == MVT::i64) ? X86::JMP64r : X86::JMP32r;
21833 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), FP);
21834 for (unsigned i = 0; i < X86::AddrNumOperands; ++i)
21835 MIB.addOperand(MI->getOperand(i));
21836 MIB.setMemRefs(MMOBegin, MMOEnd);
21838 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), Tmp);
21839 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
21840 if (i == X86::AddrDisp)
21841 MIB.addDisp(MI->getOperand(i), LabelOffset);
21843 MIB.addOperand(MI->getOperand(i));
21845 MIB.setMemRefs(MMOBegin, MMOEnd);
21847 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), SP);
21848 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
21849 if (i == X86::AddrDisp)
21850 MIB.addDisp(MI->getOperand(i), SPOffset);
21852 MIB.addOperand(MI->getOperand(i));
21854 MIB.setMemRefs(MMOBegin, MMOEnd);
21856 BuildMI(*MBB, MI, DL, TII->get(IJmpOpc)).addReg(Tmp);
21858 MI->eraseFromParent();
21862 // Replace 213-type (isel default) FMA3 instructions with 231-type for
21863 // accumulator loops. Writing back to the accumulator allows the coalescer
21864 // to remove extra copies in the loop.
21865 // FIXME: Do this on AVX512. We don't support 231 variants yet (PR23937).
21866 MachineBasicBlock *
21867 X86TargetLowering::emitFMA3Instr(MachineInstr *MI,
21868 MachineBasicBlock *MBB) const {
21869 MachineOperand &AddendOp = MI->getOperand(3);
21871 // Bail out early if the addend isn't a register - we can't switch these.
21872 if (!AddendOp.isReg())
21875 MachineFunction &MF = *MBB->getParent();
21876 MachineRegisterInfo &MRI = MF.getRegInfo();
21878 // Check whether the addend is defined by a PHI:
21879 assert(MRI.hasOneDef(AddendOp.getReg()) && "Multiple defs in SSA?");
21880 MachineInstr &AddendDef = *MRI.def_instr_begin(AddendOp.getReg());
21881 if (!AddendDef.isPHI())
21884 // Look for the following pattern:
21886 // %addend = phi [%entry, 0], [%loop, %result]
21888 // %result<tied1> = FMA213 %m2<tied0>, %m1, %addend
21892 // %addend = phi [%entry, 0], [%loop, %result]
21894 // %result<tied1> = FMA231 %addend<tied0>, %m1, %m2
21896 for (unsigned i = 1, e = AddendDef.getNumOperands(); i < e; i += 2) {
21897 assert(AddendDef.getOperand(i).isReg());
21898 MachineOperand PHISrcOp = AddendDef.getOperand(i);
21899 MachineInstr &PHISrcInst = *MRI.def_instr_begin(PHISrcOp.getReg());
21900 if (&PHISrcInst == MI) {
21901 // Found a matching instruction.
21902 unsigned NewFMAOpc = 0;
21903 switch (MI->getOpcode()) {
21904 case X86::VFMADDPDr213r: NewFMAOpc = X86::VFMADDPDr231r; break;
21905 case X86::VFMADDPSr213r: NewFMAOpc = X86::VFMADDPSr231r; break;
21906 case X86::VFMADDSDr213r: NewFMAOpc = X86::VFMADDSDr231r; break;
21907 case X86::VFMADDSSr213r: NewFMAOpc = X86::VFMADDSSr231r; break;
21908 case X86::VFMSUBPDr213r: NewFMAOpc = X86::VFMSUBPDr231r; break;
21909 case X86::VFMSUBPSr213r: NewFMAOpc = X86::VFMSUBPSr231r; break;
21910 case X86::VFMSUBSDr213r: NewFMAOpc = X86::VFMSUBSDr231r; break;
21911 case X86::VFMSUBSSr213r: NewFMAOpc = X86::VFMSUBSSr231r; break;
21912 case X86::VFNMADDPDr213r: NewFMAOpc = X86::VFNMADDPDr231r; break;
21913 case X86::VFNMADDPSr213r: NewFMAOpc = X86::VFNMADDPSr231r; break;
21914 case X86::VFNMADDSDr213r: NewFMAOpc = X86::VFNMADDSDr231r; break;
21915 case X86::VFNMADDSSr213r: NewFMAOpc = X86::VFNMADDSSr231r; break;
21916 case X86::VFNMSUBPDr213r: NewFMAOpc = X86::VFNMSUBPDr231r; break;
21917 case X86::VFNMSUBPSr213r: NewFMAOpc = X86::VFNMSUBPSr231r; break;
21918 case X86::VFNMSUBSDr213r: NewFMAOpc = X86::VFNMSUBSDr231r; break;
21919 case X86::VFNMSUBSSr213r: NewFMAOpc = X86::VFNMSUBSSr231r; break;
21920 case X86::VFMADDSUBPDr213r: NewFMAOpc = X86::VFMADDSUBPDr231r; break;
21921 case X86::VFMADDSUBPSr213r: NewFMAOpc = X86::VFMADDSUBPSr231r; break;
21922 case X86::VFMSUBADDPDr213r: NewFMAOpc = X86::VFMSUBADDPDr231r; break;
21923 case X86::VFMSUBADDPSr213r: NewFMAOpc = X86::VFMSUBADDPSr231r; break;
21925 case X86::VFMADDPDr213rY: NewFMAOpc = X86::VFMADDPDr231rY; break;
21926 case X86::VFMADDPSr213rY: NewFMAOpc = X86::VFMADDPSr231rY; break;
21927 case X86::VFMSUBPDr213rY: NewFMAOpc = X86::VFMSUBPDr231rY; break;
21928 case X86::VFMSUBPSr213rY: NewFMAOpc = X86::VFMSUBPSr231rY; break;
21929 case X86::VFNMADDPDr213rY: NewFMAOpc = X86::VFNMADDPDr231rY; break;
21930 case X86::VFNMADDPSr213rY: NewFMAOpc = X86::VFNMADDPSr231rY; break;
21931 case X86::VFNMSUBPDr213rY: NewFMAOpc = X86::VFNMSUBPDr231rY; break;
21932 case X86::VFNMSUBPSr213rY: NewFMAOpc = X86::VFNMSUBPSr231rY; break;
21933 case X86::VFMADDSUBPDr213rY: NewFMAOpc = X86::VFMADDSUBPDr231rY; break;
21934 case X86::VFMADDSUBPSr213rY: NewFMAOpc = X86::VFMADDSUBPSr231rY; break;
21935 case X86::VFMSUBADDPDr213rY: NewFMAOpc = X86::VFMSUBADDPDr231rY; break;
21936 case X86::VFMSUBADDPSr213rY: NewFMAOpc = X86::VFMSUBADDPSr231rY; break;
21937 default: llvm_unreachable("Unrecognized FMA variant.");
21940 const TargetInstrInfo &TII = *Subtarget->getInstrInfo();
21941 MachineInstrBuilder MIB =
21942 BuildMI(MF, MI->getDebugLoc(), TII.get(NewFMAOpc))
21943 .addOperand(MI->getOperand(0))
21944 .addOperand(MI->getOperand(3))
21945 .addOperand(MI->getOperand(2))
21946 .addOperand(MI->getOperand(1));
21947 MBB->insert(MachineBasicBlock::iterator(MI), MIB);
21948 MI->eraseFromParent();
21955 MachineBasicBlock *
21956 X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
21957 MachineBasicBlock *BB) const {
21958 switch (MI->getOpcode()) {
21959 default: llvm_unreachable("Unexpected instr type to insert");
21960 case X86::TAILJMPd64:
21961 case X86::TAILJMPr64:
21962 case X86::TAILJMPm64:
21963 case X86::TAILJMPd64_REX:
21964 case X86::TAILJMPr64_REX:
21965 case X86::TAILJMPm64_REX:
21966 llvm_unreachable("TAILJMP64 would not be touched here.");
21967 case X86::TCRETURNdi64:
21968 case X86::TCRETURNri64:
21969 case X86::TCRETURNmi64:
21971 case X86::WIN_ALLOCA:
21972 return EmitLoweredWinAlloca(MI, BB);
21973 case X86::CATCHRET:
21974 return EmitLoweredCatchRet(MI, BB);
21975 case X86::CATCHPAD:
21976 return EmitLoweredCatchPad(MI, BB);
21977 case X86::SEG_ALLOCA_32:
21978 case X86::SEG_ALLOCA_64:
21979 return EmitLoweredSegAlloca(MI, BB);
21980 case X86::TLSCall_32:
21981 case X86::TLSCall_64:
21982 return EmitLoweredTLSCall(MI, BB);
21983 case X86::CMOV_FR32:
21984 case X86::CMOV_FR64:
21985 case X86::CMOV_GR8:
21986 case X86::CMOV_GR16:
21987 case X86::CMOV_GR32:
21988 case X86::CMOV_RFP32:
21989 case X86::CMOV_RFP64:
21990 case X86::CMOV_RFP80:
21991 case X86::CMOV_V2F64:
21992 case X86::CMOV_V2I64:
21993 case X86::CMOV_V4F32:
21994 case X86::CMOV_V4F64:
21995 case X86::CMOV_V4I64:
21996 case X86::CMOV_V16F32:
21997 case X86::CMOV_V8F32:
21998 case X86::CMOV_V8F64:
21999 case X86::CMOV_V8I64:
22000 case X86::CMOV_V8I1:
22001 case X86::CMOV_V16I1:
22002 case X86::CMOV_V32I1:
22003 case X86::CMOV_V64I1:
22004 return EmitLoweredSelect(MI, BB);
22006 case X86::RELEASE_FADD32mr:
22007 case X86::RELEASE_FADD64mr:
22008 return EmitLoweredAtomicFP(MI, BB);
22010 case X86::FP32_TO_INT16_IN_MEM:
22011 case X86::FP32_TO_INT32_IN_MEM:
22012 case X86::FP32_TO_INT64_IN_MEM:
22013 case X86::FP64_TO_INT16_IN_MEM:
22014 case X86::FP64_TO_INT32_IN_MEM:
22015 case X86::FP64_TO_INT64_IN_MEM:
22016 case X86::FP80_TO_INT16_IN_MEM:
22017 case X86::FP80_TO_INT32_IN_MEM:
22018 case X86::FP80_TO_INT64_IN_MEM: {
22019 MachineFunction *F = BB->getParent();
22020 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
22021 DebugLoc DL = MI->getDebugLoc();
22023 // Change the floating point control register to use "round towards zero"
22024 // mode when truncating to an integer value.
22025 int CWFrameIdx = F->getFrameInfo()->CreateStackObject(2, 2, false);
22026 addFrameReference(BuildMI(*BB, MI, DL,
22027 TII->get(X86::FNSTCW16m)), CWFrameIdx);
22029 // Load the old value of the high byte of the control word...
22031 F->getRegInfo().createVirtualRegister(&X86::GR16RegClass);
22032 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16rm), OldCW),
22035 // Set the high part to be round to zero...
22036 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mi)), CWFrameIdx)
22039 // Reload the modified control word now...
22040 addFrameReference(BuildMI(*BB, MI, DL,
22041 TII->get(X86::FLDCW16m)), CWFrameIdx);
22043 // Restore the memory image of control word to original value
22044 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mr)), CWFrameIdx)
22047 // Get the X86 opcode to use.
22049 switch (MI->getOpcode()) {
22050 default: llvm_unreachable("illegal opcode!");
22051 case X86::FP32_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m32; break;
22052 case X86::FP32_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m32; break;
22053 case X86::FP32_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m32; break;
22054 case X86::FP64_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m64; break;
22055 case X86::FP64_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m64; break;
22056 case X86::FP64_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m64; break;
22057 case X86::FP80_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m80; break;
22058 case X86::FP80_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m80; break;
22059 case X86::FP80_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m80; break;
22063 MachineOperand &Op = MI->getOperand(0);
22065 AM.BaseType = X86AddressMode::RegBase;
22066 AM.Base.Reg = Op.getReg();
22068 AM.BaseType = X86AddressMode::FrameIndexBase;
22069 AM.Base.FrameIndex = Op.getIndex();
22071 Op = MI->getOperand(1);
22073 AM.Scale = Op.getImm();
22074 Op = MI->getOperand(2);
22076 AM.IndexReg = Op.getImm();
22077 Op = MI->getOperand(3);
22078 if (Op.isGlobal()) {
22079 AM.GV = Op.getGlobal();
22081 AM.Disp = Op.getImm();
22083 addFullAddress(BuildMI(*BB, MI, DL, TII->get(Opc)), AM)
22084 .addReg(MI->getOperand(X86::AddrNumOperands).getReg());
22086 // Reload the original control word now.
22087 addFrameReference(BuildMI(*BB, MI, DL,
22088 TII->get(X86::FLDCW16m)), CWFrameIdx);
22090 MI->eraseFromParent(); // The pseudo instruction is gone now.
22093 // String/text processing lowering.
22094 case X86::PCMPISTRM128REG:
22095 case X86::VPCMPISTRM128REG:
22096 case X86::PCMPISTRM128MEM:
22097 case X86::VPCMPISTRM128MEM:
22098 case X86::PCMPESTRM128REG:
22099 case X86::VPCMPESTRM128REG:
22100 case X86::PCMPESTRM128MEM:
22101 case X86::VPCMPESTRM128MEM:
22102 assert(Subtarget->hasSSE42() &&
22103 "Target must have SSE4.2 or AVX features enabled");
22104 return EmitPCMPSTRM(MI, BB, Subtarget->getInstrInfo());
22106 // String/text processing lowering.
22107 case X86::PCMPISTRIREG:
22108 case X86::VPCMPISTRIREG:
22109 case X86::PCMPISTRIMEM:
22110 case X86::VPCMPISTRIMEM:
22111 case X86::PCMPESTRIREG:
22112 case X86::VPCMPESTRIREG:
22113 case X86::PCMPESTRIMEM:
22114 case X86::VPCMPESTRIMEM:
22115 assert(Subtarget->hasSSE42() &&
22116 "Target must have SSE4.2 or AVX features enabled");
22117 return EmitPCMPSTRI(MI, BB, Subtarget->getInstrInfo());
22119 // Thread synchronization.
22121 return EmitMonitor(MI, BB, Subtarget);
22125 return EmitXBegin(MI, BB, Subtarget->getInstrInfo());
22127 case X86::VASTART_SAVE_XMM_REGS:
22128 return EmitVAStartSaveXMMRegsWithCustomInserter(MI, BB);
22130 case X86::VAARG_64:
22131 return EmitVAARG64WithCustomInserter(MI, BB);
22133 case X86::EH_SjLj_SetJmp32:
22134 case X86::EH_SjLj_SetJmp64:
22135 return emitEHSjLjSetJmp(MI, BB);
22137 case X86::EH_SjLj_LongJmp32:
22138 case X86::EH_SjLj_LongJmp64:
22139 return emitEHSjLjLongJmp(MI, BB);
22141 case TargetOpcode::STATEPOINT:
22142 // As an implementation detail, STATEPOINT shares the STACKMAP format at
22143 // this point in the process. We diverge later.
22144 return emitPatchPoint(MI, BB);
22146 case TargetOpcode::STACKMAP:
22147 case TargetOpcode::PATCHPOINT:
22148 return emitPatchPoint(MI, BB);
22150 case X86::VFMADDPDr213r:
22151 case X86::VFMADDPSr213r:
22152 case X86::VFMADDSDr213r:
22153 case X86::VFMADDSSr213r:
22154 case X86::VFMSUBPDr213r:
22155 case X86::VFMSUBPSr213r:
22156 case X86::VFMSUBSDr213r:
22157 case X86::VFMSUBSSr213r:
22158 case X86::VFNMADDPDr213r:
22159 case X86::VFNMADDPSr213r:
22160 case X86::VFNMADDSDr213r:
22161 case X86::VFNMADDSSr213r:
22162 case X86::VFNMSUBPDr213r:
22163 case X86::VFNMSUBPSr213r:
22164 case X86::VFNMSUBSDr213r:
22165 case X86::VFNMSUBSSr213r:
22166 case X86::VFMADDSUBPDr213r:
22167 case X86::VFMADDSUBPSr213r:
22168 case X86::VFMSUBADDPDr213r:
22169 case X86::VFMSUBADDPSr213r:
22170 case X86::VFMADDPDr213rY:
22171 case X86::VFMADDPSr213rY:
22172 case X86::VFMSUBPDr213rY:
22173 case X86::VFMSUBPSr213rY:
22174 case X86::VFNMADDPDr213rY:
22175 case X86::VFNMADDPSr213rY:
22176 case X86::VFNMSUBPDr213rY:
22177 case X86::VFNMSUBPSr213rY:
22178 case X86::VFMADDSUBPDr213rY:
22179 case X86::VFMADDSUBPSr213rY:
22180 case X86::VFMSUBADDPDr213rY:
22181 case X86::VFMSUBADDPSr213rY:
22182 return emitFMA3Instr(MI, BB);
22186 //===----------------------------------------------------------------------===//
22187 // X86 Optimization Hooks
22188 //===----------------------------------------------------------------------===//
22190 void X86TargetLowering::computeKnownBitsForTargetNode(const SDValue Op,
22193 const SelectionDAG &DAG,
22194 unsigned Depth) const {
22195 unsigned BitWidth = KnownZero.getBitWidth();
22196 unsigned Opc = Op.getOpcode();
22197 assert((Opc >= ISD::BUILTIN_OP_END ||
22198 Opc == ISD::INTRINSIC_WO_CHAIN ||
22199 Opc == ISD::INTRINSIC_W_CHAIN ||
22200 Opc == ISD::INTRINSIC_VOID) &&
22201 "Should use MaskedValueIsZero if you don't know whether Op"
22202 " is a target node!");
22204 KnownZero = KnownOne = APInt(BitWidth, 0); // Don't know anything.
22218 // These nodes' second result is a boolean.
22219 if (Op.getResNo() == 0)
22222 case X86ISD::SETCC:
22223 KnownZero |= APInt::getHighBitsSet(BitWidth, BitWidth - 1);
22225 case ISD::INTRINSIC_WO_CHAIN: {
22226 unsigned IntId = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
22227 unsigned NumLoBits = 0;
22230 case Intrinsic::x86_sse_movmsk_ps:
22231 case Intrinsic::x86_avx_movmsk_ps_256:
22232 case Intrinsic::x86_sse2_movmsk_pd:
22233 case Intrinsic::x86_avx_movmsk_pd_256:
22234 case Intrinsic::x86_mmx_pmovmskb:
22235 case Intrinsic::x86_sse2_pmovmskb_128:
22236 case Intrinsic::x86_avx2_pmovmskb: {
22237 // High bits of movmskp{s|d}, pmovmskb are known zero.
22239 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
22240 case Intrinsic::x86_sse_movmsk_ps: NumLoBits = 4; break;
22241 case Intrinsic::x86_avx_movmsk_ps_256: NumLoBits = 8; break;
22242 case Intrinsic::x86_sse2_movmsk_pd: NumLoBits = 2; break;
22243 case Intrinsic::x86_avx_movmsk_pd_256: NumLoBits = 4; break;
22244 case Intrinsic::x86_mmx_pmovmskb: NumLoBits = 8; break;
22245 case Intrinsic::x86_sse2_pmovmskb_128: NumLoBits = 16; break;
22246 case Intrinsic::x86_avx2_pmovmskb: NumLoBits = 32; break;
22248 KnownZero = APInt::getHighBitsSet(BitWidth, BitWidth - NumLoBits);
22257 unsigned X86TargetLowering::ComputeNumSignBitsForTargetNode(
22259 const SelectionDAG &,
22260 unsigned Depth) const {
22261 // SETCC_CARRY sets the dest to ~0 for true or 0 for false.
22262 if (Op.getOpcode() == X86ISD::SETCC_CARRY)
22263 return Op.getValueType().getScalarSizeInBits();
22269 /// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the
22270 /// node is a GlobalAddress + offset.
22271 bool X86TargetLowering::isGAPlusOffset(SDNode *N,
22272 const GlobalValue* &GA,
22273 int64_t &Offset) const {
22274 if (N->getOpcode() == X86ISD::Wrapper) {
22275 if (isa<GlobalAddressSDNode>(N->getOperand(0))) {
22276 GA = cast<GlobalAddressSDNode>(N->getOperand(0))->getGlobal();
22277 Offset = cast<GlobalAddressSDNode>(N->getOperand(0))->getOffset();
22281 return TargetLowering::isGAPlusOffset(N, GA, Offset);
22284 /// isShuffleHigh128VectorInsertLow - Checks whether the shuffle node is the
22285 /// same as extracting the high 128-bit part of 256-bit vector and then
22286 /// inserting the result into the low part of a new 256-bit vector
22287 static bool isShuffleHigh128VectorInsertLow(ShuffleVectorSDNode *SVOp) {
22288 EVT VT = SVOp->getValueType(0);
22289 unsigned NumElems = VT.getVectorNumElements();
22291 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
22292 for (unsigned i = 0, j = NumElems/2; i != NumElems/2; ++i, ++j)
22293 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) ||
22294 SVOp->getMaskElt(j) >= 0)
22300 /// isShuffleLow128VectorInsertHigh - Checks whether the shuffle node is the
22301 /// same as extracting the low 128-bit part of 256-bit vector and then
22302 /// inserting the result into the high part of a new 256-bit vector
22303 static bool isShuffleLow128VectorInsertHigh(ShuffleVectorSDNode *SVOp) {
22304 EVT VT = SVOp->getValueType(0);
22305 unsigned NumElems = VT.getVectorNumElements();
22307 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
22308 for (unsigned i = NumElems/2, j = 0; i != NumElems; ++i, ++j)
22309 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) ||
22310 SVOp->getMaskElt(j) >= 0)
22316 /// PerformShuffleCombine256 - Performs shuffle combines for 256-bit vectors.
22317 static SDValue PerformShuffleCombine256(SDNode *N, SelectionDAG &DAG,
22318 TargetLowering::DAGCombinerInfo &DCI,
22319 const X86Subtarget* Subtarget) {
22321 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
22322 SDValue V1 = SVOp->getOperand(0);
22323 SDValue V2 = SVOp->getOperand(1);
22324 EVT VT = SVOp->getValueType(0);
22325 unsigned NumElems = VT.getVectorNumElements();
22327 if (V1.getOpcode() == ISD::CONCAT_VECTORS &&
22328 V2.getOpcode() == ISD::CONCAT_VECTORS) {
22332 // V UNDEF BUILD_VECTOR UNDEF
22334 // CONCAT_VECTOR CONCAT_VECTOR
22337 // RESULT: V + zero extended
22339 if (V2.getOperand(0).getOpcode() != ISD::BUILD_VECTOR ||
22340 V2.getOperand(1).getOpcode() != ISD::UNDEF ||
22341 V1.getOperand(1).getOpcode() != ISD::UNDEF)
22344 if (!ISD::isBuildVectorAllZeros(V2.getOperand(0).getNode()))
22347 // To match the shuffle mask, the first half of the mask should
22348 // be exactly the first vector, and all the rest a splat with the
22349 // first element of the second one.
22350 for (unsigned i = 0; i != NumElems/2; ++i)
22351 if (!isUndefOrEqual(SVOp->getMaskElt(i), i) ||
22352 !isUndefOrEqual(SVOp->getMaskElt(i+NumElems/2), NumElems))
22355 // If V1 is coming from a vector load then just fold to a VZEXT_LOAD.
22356 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(V1.getOperand(0))) {
22357 if (Ld->hasNUsesOfValue(1, 0)) {
22358 SDVTList Tys = DAG.getVTList(MVT::v4i64, MVT::Other);
22359 SDValue Ops[] = { Ld->getChain(), Ld->getBasePtr() };
22361 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, dl, Tys, Ops,
22363 Ld->getPointerInfo(),
22364 Ld->getAlignment(),
22365 false/*isVolatile*/, true/*ReadMem*/,
22366 false/*WriteMem*/);
22368 // Make sure the newly-created LOAD is in the same position as Ld in
22369 // terms of dependency. We create a TokenFactor for Ld and ResNode,
22370 // and update uses of Ld's output chain to use the TokenFactor.
22371 if (Ld->hasAnyUseOfValue(1)) {
22372 SDValue NewChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
22373 SDValue(Ld, 1), SDValue(ResNode.getNode(), 1));
22374 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), NewChain);
22375 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(Ld, 1),
22376 SDValue(ResNode.getNode(), 1));
22379 return DAG.getBitcast(VT, ResNode);
22383 // Emit a zeroed vector and insert the desired subvector on its
22385 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
22386 SDValue InsV = Insert128BitVector(Zeros, V1.getOperand(0), 0, DAG, dl);
22387 return DCI.CombineTo(N, InsV);
22390 //===--------------------------------------------------------------------===//
22391 // Combine some shuffles into subvector extracts and inserts:
22394 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
22395 if (isShuffleHigh128VectorInsertLow(SVOp)) {
22396 SDValue V = Extract128BitVector(V1, NumElems/2, DAG, dl);
22397 SDValue InsV = Insert128BitVector(DAG.getUNDEF(VT), V, 0, DAG, dl);
22398 return DCI.CombineTo(N, InsV);
22401 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
22402 if (isShuffleLow128VectorInsertHigh(SVOp)) {
22403 SDValue V = Extract128BitVector(V1, 0, DAG, dl);
22404 SDValue InsV = Insert128BitVector(DAG.getUNDEF(VT), V, NumElems/2, DAG, dl);
22405 return DCI.CombineTo(N, InsV);
22411 /// \brief Combine an arbitrary chain of shuffles into a single instruction if
22414 /// This is the leaf of the recursive combinine below. When we have found some
22415 /// chain of single-use x86 shuffle instructions and accumulated the combined
22416 /// shuffle mask represented by them, this will try to pattern match that mask
22417 /// into either a single instruction if there is a special purpose instruction
22418 /// for this operation, or into a PSHUFB instruction which is a fully general
22419 /// instruction but should only be used to replace chains over a certain depth.
22420 static bool combineX86ShuffleChain(SDValue Op, SDValue Root, ArrayRef<int> Mask,
22421 int Depth, bool HasPSHUFB, SelectionDAG &DAG,
22422 TargetLowering::DAGCombinerInfo &DCI,
22423 const X86Subtarget *Subtarget) {
22424 assert(!Mask.empty() && "Cannot combine an empty shuffle mask!");
22426 // Find the operand that enters the chain. Note that multiple uses are OK
22427 // here, we're not going to remove the operand we find.
22428 SDValue Input = Op.getOperand(0);
22429 while (Input.getOpcode() == ISD::BITCAST)
22430 Input = Input.getOperand(0);
22432 MVT VT = Input.getSimpleValueType();
22433 MVT RootVT = Root.getSimpleValueType();
22436 if (Mask.size() == 1) {
22437 int Index = Mask[0];
22438 assert((Index >= 0 || Index == SM_SentinelUndef ||
22439 Index == SM_SentinelZero) &&
22440 "Invalid shuffle index found!");
22442 // We may end up with an accumulated mask of size 1 as a result of
22443 // widening of shuffle operands (see function canWidenShuffleElements).
22444 // If the only shuffle index is equal to SM_SentinelZero then propagate
22445 // a zero vector. Otherwise, the combine shuffle mask is a no-op shuffle
22446 // mask, and therefore the entire chain of shuffles can be folded away.
22447 if (Index == SM_SentinelZero)
22448 DCI.CombineTo(Root.getNode(), getZeroVector(RootVT, Subtarget, DAG, DL));
22450 DCI.CombineTo(Root.getNode(), DAG.getBitcast(RootVT, Input),
22455 // Use the float domain if the operand type is a floating point type.
22456 bool FloatDomain = VT.isFloatingPoint();
22458 // For floating point shuffles, we don't have free copies in the shuffle
22459 // instructions or the ability to load as part of the instruction, so
22460 // canonicalize their shuffles to UNPCK or MOV variants.
22462 // Note that even with AVX we prefer the PSHUFD form of shuffle for integer
22463 // vectors because it can have a load folded into it that UNPCK cannot. This
22464 // doesn't preclude something switching to the shorter encoding post-RA.
22466 // FIXME: Should teach these routines about AVX vector widths.
22467 if (FloatDomain && VT.is128BitVector()) {
22468 if (Mask.equals({0, 0}) || Mask.equals({1, 1})) {
22469 bool Lo = Mask.equals({0, 0});
22472 // Check if we have SSE3 which will let us use MOVDDUP. That instruction
22473 // is no slower than UNPCKLPD but has the option to fold the input operand
22474 // into even an unaligned memory load.
22475 if (Lo && Subtarget->hasSSE3()) {
22476 Shuffle = X86ISD::MOVDDUP;
22477 ShuffleVT = MVT::v2f64;
22479 // We have MOVLHPS and MOVHLPS throughout SSE and they encode smaller
22480 // than the UNPCK variants.
22481 Shuffle = Lo ? X86ISD::MOVLHPS : X86ISD::MOVHLPS;
22482 ShuffleVT = MVT::v4f32;
22484 if (Depth == 1 && Root->getOpcode() == Shuffle)
22485 return false; // Nothing to do!
22486 Op = DAG.getBitcast(ShuffleVT, Input);
22487 DCI.AddToWorklist(Op.getNode());
22488 if (Shuffle == X86ISD::MOVDDUP)
22489 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op);
22491 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op, Op);
22492 DCI.AddToWorklist(Op.getNode());
22493 DCI.CombineTo(Root.getNode(), DAG.getBitcast(RootVT, Op),
22497 if (Subtarget->hasSSE3() &&
22498 (Mask.equals({0, 0, 2, 2}) || Mask.equals({1, 1, 3, 3}))) {
22499 bool Lo = Mask.equals({0, 0, 2, 2});
22500 unsigned Shuffle = Lo ? X86ISD::MOVSLDUP : X86ISD::MOVSHDUP;
22501 MVT ShuffleVT = MVT::v4f32;
22502 if (Depth == 1 && Root->getOpcode() == Shuffle)
22503 return false; // Nothing to do!
22504 Op = DAG.getBitcast(ShuffleVT, Input);
22505 DCI.AddToWorklist(Op.getNode());
22506 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op);
22507 DCI.AddToWorklist(Op.getNode());
22508 DCI.CombineTo(Root.getNode(), DAG.getBitcast(RootVT, Op),
22512 if (Mask.equals({0, 0, 1, 1}) || Mask.equals({2, 2, 3, 3})) {
22513 bool Lo = Mask.equals({0, 0, 1, 1});
22514 unsigned Shuffle = Lo ? X86ISD::UNPCKL : X86ISD::UNPCKH;
22515 MVT ShuffleVT = MVT::v4f32;
22516 if (Depth == 1 && Root->getOpcode() == Shuffle)
22517 return false; // Nothing to do!
22518 Op = DAG.getBitcast(ShuffleVT, Input);
22519 DCI.AddToWorklist(Op.getNode());
22520 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op, Op);
22521 DCI.AddToWorklist(Op.getNode());
22522 DCI.CombineTo(Root.getNode(), DAG.getBitcast(RootVT, Op),
22528 // We always canonicalize the 8 x i16 and 16 x i8 shuffles into their UNPCK
22529 // variants as none of these have single-instruction variants that are
22530 // superior to the UNPCK formulation.
22531 if (!FloatDomain && VT.is128BitVector() &&
22532 (Mask.equals({0, 0, 1, 1, 2, 2, 3, 3}) ||
22533 Mask.equals({4, 4, 5, 5, 6, 6, 7, 7}) ||
22534 Mask.equals({0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7}) ||
22536 {8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 15}))) {
22537 bool Lo = Mask[0] == 0;
22538 unsigned Shuffle = Lo ? X86ISD::UNPCKL : X86ISD::UNPCKH;
22539 if (Depth == 1 && Root->getOpcode() == Shuffle)
22540 return false; // Nothing to do!
22542 switch (Mask.size()) {
22544 ShuffleVT = MVT::v8i16;
22547 ShuffleVT = MVT::v16i8;
22550 llvm_unreachable("Impossible mask size!");
22552 Op = DAG.getBitcast(ShuffleVT, Input);
22553 DCI.AddToWorklist(Op.getNode());
22554 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op, Op);
22555 DCI.AddToWorklist(Op.getNode());
22556 DCI.CombineTo(Root.getNode(), DAG.getBitcast(RootVT, Op),
22561 // Don't try to re-form single instruction chains under any circumstances now
22562 // that we've done encoding canonicalization for them.
22566 // If we have 3 or more shuffle instructions or a chain involving PSHUFB, we
22567 // can replace them with a single PSHUFB instruction profitably. Intel's
22568 // manuals suggest only using PSHUFB if doing so replacing 5 instructions, but
22569 // in practice PSHUFB tends to be *very* fast so we're more aggressive.
22570 if ((Depth >= 3 || HasPSHUFB) && Subtarget->hasSSSE3()) {
22571 SmallVector<SDValue, 16> PSHUFBMask;
22572 int NumBytes = VT.getSizeInBits() / 8;
22573 int Ratio = NumBytes / Mask.size();
22574 for (int i = 0; i < NumBytes; ++i) {
22575 if (Mask[i / Ratio] == SM_SentinelUndef) {
22576 PSHUFBMask.push_back(DAG.getUNDEF(MVT::i8));
22579 int M = Mask[i / Ratio] != SM_SentinelZero
22580 ? Ratio * Mask[i / Ratio] + i % Ratio
22582 PSHUFBMask.push_back(DAG.getConstant(M, DL, MVT::i8));
22584 MVT ByteVT = MVT::getVectorVT(MVT::i8, NumBytes);
22585 Op = DAG.getBitcast(ByteVT, Input);
22586 DCI.AddToWorklist(Op.getNode());
22587 SDValue PSHUFBMaskOp =
22588 DAG.getNode(ISD::BUILD_VECTOR, DL, ByteVT, PSHUFBMask);
22589 DCI.AddToWorklist(PSHUFBMaskOp.getNode());
22590 Op = DAG.getNode(X86ISD::PSHUFB, DL, ByteVT, Op, PSHUFBMaskOp);
22591 DCI.AddToWorklist(Op.getNode());
22592 DCI.CombineTo(Root.getNode(), DAG.getBitcast(RootVT, Op),
22597 // Failed to find any combines.
22601 /// \brief Fully generic combining of x86 shuffle instructions.
22603 /// This should be the last combine run over the x86 shuffle instructions. Once
22604 /// they have been fully optimized, this will recursively consider all chains
22605 /// of single-use shuffle instructions, build a generic model of the cumulative
22606 /// shuffle operation, and check for simpler instructions which implement this
22607 /// operation. We use this primarily for two purposes:
22609 /// 1) Collapse generic shuffles to specialized single instructions when
22610 /// equivalent. In most cases, this is just an encoding size win, but
22611 /// sometimes we will collapse multiple generic shuffles into a single
22612 /// special-purpose shuffle.
22613 /// 2) Look for sequences of shuffle instructions with 3 or more total
22614 /// instructions, and replace them with the slightly more expensive SSSE3
22615 /// PSHUFB instruction if available. We do this as the last combining step
22616 /// to ensure we avoid using PSHUFB if we can implement the shuffle with
22617 /// a suitable short sequence of other instructions. The PHUFB will either
22618 /// use a register or have to read from memory and so is slightly (but only
22619 /// slightly) more expensive than the other shuffle instructions.
22621 /// Because this is inherently a quadratic operation (for each shuffle in
22622 /// a chain, we recurse up the chain), the depth is limited to 8 instructions.
22623 /// This should never be an issue in practice as the shuffle lowering doesn't
22624 /// produce sequences of more than 8 instructions.
22626 /// FIXME: We will currently miss some cases where the redundant shuffling
22627 /// would simplify under the threshold for PSHUFB formation because of
22628 /// combine-ordering. To fix this, we should do the redundant instruction
22629 /// combining in this recursive walk.
22630 static bool combineX86ShufflesRecursively(SDValue Op, SDValue Root,
22631 ArrayRef<int> RootMask,
22632 int Depth, bool HasPSHUFB,
22634 TargetLowering::DAGCombinerInfo &DCI,
22635 const X86Subtarget *Subtarget) {
22636 // Bound the depth of our recursive combine because this is ultimately
22637 // quadratic in nature.
22641 // Directly rip through bitcasts to find the underlying operand.
22642 while (Op.getOpcode() == ISD::BITCAST && Op.getOperand(0).hasOneUse())
22643 Op = Op.getOperand(0);
22645 MVT VT = Op.getSimpleValueType();
22646 if (!VT.isVector())
22647 return false; // Bail if we hit a non-vector.
22649 assert(Root.getSimpleValueType().isVector() &&
22650 "Shuffles operate on vector types!");
22651 assert(VT.getSizeInBits() == Root.getSimpleValueType().getSizeInBits() &&
22652 "Can only combine shuffles of the same vector register size.");
22654 if (!isTargetShuffle(Op.getOpcode()))
22656 SmallVector<int, 16> OpMask;
22658 bool HaveMask = getTargetShuffleMask(Op.getNode(), VT, OpMask, IsUnary);
22659 // We only can combine unary shuffles which we can decode the mask for.
22660 if (!HaveMask || !IsUnary)
22663 assert(VT.getVectorNumElements() == OpMask.size() &&
22664 "Different mask size from vector size!");
22665 assert(((RootMask.size() > OpMask.size() &&
22666 RootMask.size() % OpMask.size() == 0) ||
22667 (OpMask.size() > RootMask.size() &&
22668 OpMask.size() % RootMask.size() == 0) ||
22669 OpMask.size() == RootMask.size()) &&
22670 "The smaller number of elements must divide the larger.");
22671 int RootRatio = std::max<int>(1, OpMask.size() / RootMask.size());
22672 int OpRatio = std::max<int>(1, RootMask.size() / OpMask.size());
22673 assert(((RootRatio == 1 && OpRatio == 1) ||
22674 (RootRatio == 1) != (OpRatio == 1)) &&
22675 "Must not have a ratio for both incoming and op masks!");
22677 SmallVector<int, 16> Mask;
22678 Mask.reserve(std::max(OpMask.size(), RootMask.size()));
22680 // Merge this shuffle operation's mask into our accumulated mask. Note that
22681 // this shuffle's mask will be the first applied to the input, followed by the
22682 // root mask to get us all the way to the root value arrangement. The reason
22683 // for this order is that we are recursing up the operation chain.
22684 for (int i = 0, e = std::max(OpMask.size(), RootMask.size()); i < e; ++i) {
22685 int RootIdx = i / RootRatio;
22686 if (RootMask[RootIdx] < 0) {
22687 // This is a zero or undef lane, we're done.
22688 Mask.push_back(RootMask[RootIdx]);
22692 int RootMaskedIdx = RootMask[RootIdx] * RootRatio + i % RootRatio;
22693 int OpIdx = RootMaskedIdx / OpRatio;
22694 if (OpMask[OpIdx] < 0) {
22695 // The incoming lanes are zero or undef, it doesn't matter which ones we
22697 Mask.push_back(OpMask[OpIdx]);
22701 // Ok, we have non-zero lanes, map them through.
22702 Mask.push_back(OpMask[OpIdx] * OpRatio +
22703 RootMaskedIdx % OpRatio);
22706 // See if we can recurse into the operand to combine more things.
22707 switch (Op.getOpcode()) {
22708 case X86ISD::PSHUFB:
22710 case X86ISD::PSHUFD:
22711 case X86ISD::PSHUFHW:
22712 case X86ISD::PSHUFLW:
22713 if (Op.getOperand(0).hasOneUse() &&
22714 combineX86ShufflesRecursively(Op.getOperand(0), Root, Mask, Depth + 1,
22715 HasPSHUFB, DAG, DCI, Subtarget))
22719 case X86ISD::UNPCKL:
22720 case X86ISD::UNPCKH:
22721 assert(Op.getOperand(0) == Op.getOperand(1) &&
22722 "We only combine unary shuffles!");
22723 // We can't check for single use, we have to check that this shuffle is the
22725 if (Op->isOnlyUserOf(Op.getOperand(0).getNode()) &&
22726 combineX86ShufflesRecursively(Op.getOperand(0), Root, Mask, Depth + 1,
22727 HasPSHUFB, DAG, DCI, Subtarget))
22732 // Minor canonicalization of the accumulated shuffle mask to make it easier
22733 // to match below. All this does is detect masks with squential pairs of
22734 // elements, and shrink them to the half-width mask. It does this in a loop
22735 // so it will reduce the size of the mask to the minimal width mask which
22736 // performs an equivalent shuffle.
22737 SmallVector<int, 16> WidenedMask;
22738 while (Mask.size() > 1 && canWidenShuffleElements(Mask, WidenedMask)) {
22739 Mask = std::move(WidenedMask);
22740 WidenedMask.clear();
22743 return combineX86ShuffleChain(Op, Root, Mask, Depth, HasPSHUFB, DAG, DCI,
22747 /// \brief Get the PSHUF-style mask from PSHUF node.
22749 /// This is a very minor wrapper around getTargetShuffleMask to easy forming v4
22750 /// PSHUF-style masks that can be reused with such instructions.
22751 static SmallVector<int, 4> getPSHUFShuffleMask(SDValue N) {
22752 MVT VT = N.getSimpleValueType();
22753 SmallVector<int, 4> Mask;
22755 bool HaveMask = getTargetShuffleMask(N.getNode(), VT, Mask, IsUnary);
22759 // If we have more than 128-bits, only the low 128-bits of shuffle mask
22760 // matter. Check that the upper masks are repeats and remove them.
22761 if (VT.getSizeInBits() > 128) {
22762 int LaneElts = 128 / VT.getScalarSizeInBits();
22764 for (int i = 1, NumLanes = VT.getSizeInBits() / 128; i < NumLanes; ++i)
22765 for (int j = 0; j < LaneElts; ++j)
22766 assert(Mask[j] == Mask[i * LaneElts + j] - (LaneElts * i) &&
22767 "Mask doesn't repeat in high 128-bit lanes!");
22769 Mask.resize(LaneElts);
22772 switch (N.getOpcode()) {
22773 case X86ISD::PSHUFD:
22775 case X86ISD::PSHUFLW:
22778 case X86ISD::PSHUFHW:
22779 Mask.erase(Mask.begin(), Mask.begin() + 4);
22780 for (int &M : Mask)
22784 llvm_unreachable("No valid shuffle instruction found!");
22788 /// \brief Search for a combinable shuffle across a chain ending in pshufd.
22790 /// We walk up the chain and look for a combinable shuffle, skipping over
22791 /// shuffles that we could hoist this shuffle's transformation past without
22792 /// altering anything.
22794 combineRedundantDWordShuffle(SDValue N, MutableArrayRef<int> Mask,
22796 TargetLowering::DAGCombinerInfo &DCI) {
22797 assert(N.getOpcode() == X86ISD::PSHUFD &&
22798 "Called with something other than an x86 128-bit half shuffle!");
22801 // Walk up a single-use chain looking for a combinable shuffle. Keep a stack
22802 // of the shuffles in the chain so that we can form a fresh chain to replace
22804 SmallVector<SDValue, 8> Chain;
22805 SDValue V = N.getOperand(0);
22806 for (; V.hasOneUse(); V = V.getOperand(0)) {
22807 switch (V.getOpcode()) {
22809 return SDValue(); // Nothing combined!
22812 // Skip bitcasts as we always know the type for the target specific
22816 case X86ISD::PSHUFD:
22817 // Found another dword shuffle.
22820 case X86ISD::PSHUFLW:
22821 // Check that the low words (being shuffled) are the identity in the
22822 // dword shuffle, and the high words are self-contained.
22823 if (Mask[0] != 0 || Mask[1] != 1 ||
22824 !(Mask[2] >= 2 && Mask[2] < 4 && Mask[3] >= 2 && Mask[3] < 4))
22827 Chain.push_back(V);
22830 case X86ISD::PSHUFHW:
22831 // Check that the high words (being shuffled) are the identity in the
22832 // dword shuffle, and the low words are self-contained.
22833 if (Mask[2] != 2 || Mask[3] != 3 ||
22834 !(Mask[0] >= 0 && Mask[0] < 2 && Mask[1] >= 0 && Mask[1] < 2))
22837 Chain.push_back(V);
22840 case X86ISD::UNPCKL:
22841 case X86ISD::UNPCKH:
22842 // For either i8 -> i16 or i16 -> i32 unpacks, we can combine a dword
22843 // shuffle into a preceding word shuffle.
22844 if (V.getSimpleValueType().getVectorElementType() != MVT::i8 &&
22845 V.getSimpleValueType().getVectorElementType() != MVT::i16)
22848 // Search for a half-shuffle which we can combine with.
22849 unsigned CombineOp =
22850 V.getOpcode() == X86ISD::UNPCKL ? X86ISD::PSHUFLW : X86ISD::PSHUFHW;
22851 if (V.getOperand(0) != V.getOperand(1) ||
22852 !V->isOnlyUserOf(V.getOperand(0).getNode()))
22854 Chain.push_back(V);
22855 V = V.getOperand(0);
22857 switch (V.getOpcode()) {
22859 return SDValue(); // Nothing to combine.
22861 case X86ISD::PSHUFLW:
22862 case X86ISD::PSHUFHW:
22863 if (V.getOpcode() == CombineOp)
22866 Chain.push_back(V);
22870 V = V.getOperand(0);
22874 } while (V.hasOneUse());
22877 // Break out of the loop if we break out of the switch.
22881 if (!V.hasOneUse())
22882 // We fell out of the loop without finding a viable combining instruction.
22885 // Merge this node's mask and our incoming mask.
22886 SmallVector<int, 4> VMask = getPSHUFShuffleMask(V);
22887 for (int &M : Mask)
22889 V = DAG.getNode(V.getOpcode(), DL, V.getValueType(), V.getOperand(0),
22890 getV4X86ShuffleImm8ForMask(Mask, DL, DAG));
22892 // Rebuild the chain around this new shuffle.
22893 while (!Chain.empty()) {
22894 SDValue W = Chain.pop_back_val();
22896 if (V.getValueType() != W.getOperand(0).getValueType())
22897 V = DAG.getBitcast(W.getOperand(0).getValueType(), V);
22899 switch (W.getOpcode()) {
22901 llvm_unreachable("Only PSHUF and UNPCK instructions get here!");
22903 case X86ISD::UNPCKL:
22904 case X86ISD::UNPCKH:
22905 V = DAG.getNode(W.getOpcode(), DL, W.getValueType(), V, V);
22908 case X86ISD::PSHUFD:
22909 case X86ISD::PSHUFLW:
22910 case X86ISD::PSHUFHW:
22911 V = DAG.getNode(W.getOpcode(), DL, W.getValueType(), V, W.getOperand(1));
22915 if (V.getValueType() != N.getValueType())
22916 V = DAG.getBitcast(N.getValueType(), V);
22918 // Return the new chain to replace N.
22922 /// \brief Search for a combinable shuffle across a chain ending in pshuflw or
22925 /// We walk up the chain, skipping shuffles of the other half and looking
22926 /// through shuffles which switch halves trying to find a shuffle of the same
22927 /// pair of dwords.
22928 static bool combineRedundantHalfShuffle(SDValue N, MutableArrayRef<int> Mask,
22930 TargetLowering::DAGCombinerInfo &DCI) {
22932 (N.getOpcode() == X86ISD::PSHUFLW || N.getOpcode() == X86ISD::PSHUFHW) &&
22933 "Called with something other than an x86 128-bit half shuffle!");
22935 unsigned CombineOpcode = N.getOpcode();
22937 // Walk up a single-use chain looking for a combinable shuffle.
22938 SDValue V = N.getOperand(0);
22939 for (; V.hasOneUse(); V = V.getOperand(0)) {
22940 switch (V.getOpcode()) {
22942 return false; // Nothing combined!
22945 // Skip bitcasts as we always know the type for the target specific
22949 case X86ISD::PSHUFLW:
22950 case X86ISD::PSHUFHW:
22951 if (V.getOpcode() == CombineOpcode)
22954 // Other-half shuffles are no-ops.
22957 // Break out of the loop if we break out of the switch.
22961 if (!V.hasOneUse())
22962 // We fell out of the loop without finding a viable combining instruction.
22965 // Combine away the bottom node as its shuffle will be accumulated into
22966 // a preceding shuffle.
22967 DCI.CombineTo(N.getNode(), N.getOperand(0), /*AddTo*/ true);
22969 // Record the old value.
22972 // Merge this node's mask and our incoming mask (adjusted to account for all
22973 // the pshufd instructions encountered).
22974 SmallVector<int, 4> VMask = getPSHUFShuffleMask(V);
22975 for (int &M : Mask)
22977 V = DAG.getNode(V.getOpcode(), DL, MVT::v8i16, V.getOperand(0),
22978 getV4X86ShuffleImm8ForMask(Mask, DL, DAG));
22980 // Check that the shuffles didn't cancel each other out. If not, we need to
22981 // combine to the new one.
22983 // Replace the combinable shuffle with the combined one, updating all users
22984 // so that we re-evaluate the chain here.
22985 DCI.CombineTo(Old.getNode(), V, /*AddTo*/ true);
22990 /// \brief Try to combine x86 target specific shuffles.
22991 static SDValue PerformTargetShuffleCombine(SDValue N, SelectionDAG &DAG,
22992 TargetLowering::DAGCombinerInfo &DCI,
22993 const X86Subtarget *Subtarget) {
22995 MVT VT = N.getSimpleValueType();
22996 SmallVector<int, 4> Mask;
22998 switch (N.getOpcode()) {
22999 case X86ISD::PSHUFD:
23000 case X86ISD::PSHUFLW:
23001 case X86ISD::PSHUFHW:
23002 Mask = getPSHUFShuffleMask(N);
23003 assert(Mask.size() == 4);
23005 case X86ISD::UNPCKL: {
23006 // Combine X86ISD::UNPCKL and ISD::VECTOR_SHUFFLE into X86ISD::UNPCKH, in
23007 // which X86ISD::UNPCKL has a ISD::UNDEF operand, and ISD::VECTOR_SHUFFLE
23008 // moves upper half elements into the lower half part. For example:
23010 // t2: v16i8 = vector_shuffle<8,9,10,11,12,13,14,15,u,u,u,u,u,u,u,u> t1,
23012 // t3: v16i8 = X86ISD::UNPCKL undef:v16i8, t2
23014 // will be combined to:
23016 // t3: v16i8 = X86ISD::UNPCKH undef:v16i8, t1
23018 // This is only for 128-bit vectors. From SSE4.1 onward this combine may not
23019 // happen due to advanced instructions.
23020 if (!VT.is128BitVector())
23023 auto Op0 = N.getOperand(0);
23024 auto Op1 = N.getOperand(1);
23025 if (Op0.getOpcode() == ISD::UNDEF &&
23026 Op1.getNode()->getOpcode() == ISD::VECTOR_SHUFFLE) {
23027 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(Op1.getNode())->getMask();
23029 unsigned NumElts = VT.getVectorNumElements();
23030 SmallVector<int, 8> ExpectedMask(NumElts, -1);
23031 std::iota(ExpectedMask.begin(), ExpectedMask.begin() + NumElts / 2,
23034 auto ShufOp = Op1.getOperand(0);
23035 if (isShuffleEquivalent(Op1, ShufOp, Mask, ExpectedMask))
23036 return DAG.getNode(X86ISD::UNPCKH, DL, VT, N.getOperand(0), ShufOp);
23044 // Nuke no-op shuffles that show up after combining.
23045 if (isNoopShuffleMask(Mask))
23046 return DCI.CombineTo(N.getNode(), N.getOperand(0), /*AddTo*/ true);
23048 // Look for simplifications involving one or two shuffle instructions.
23049 SDValue V = N.getOperand(0);
23050 switch (N.getOpcode()) {
23053 case X86ISD::PSHUFLW:
23054 case X86ISD::PSHUFHW:
23055 assert(VT.getVectorElementType() == MVT::i16 && "Bad word shuffle type!");
23057 if (combineRedundantHalfShuffle(N, Mask, DAG, DCI))
23058 return SDValue(); // We combined away this shuffle, so we're done.
23060 // See if this reduces to a PSHUFD which is no more expensive and can
23061 // combine with more operations. Note that it has to at least flip the
23062 // dwords as otherwise it would have been removed as a no-op.
23063 if (makeArrayRef(Mask).equals({2, 3, 0, 1})) {
23064 int DMask[] = {0, 1, 2, 3};
23065 int DOffset = N.getOpcode() == X86ISD::PSHUFLW ? 0 : 2;
23066 DMask[DOffset + 0] = DOffset + 1;
23067 DMask[DOffset + 1] = DOffset + 0;
23068 MVT DVT = MVT::getVectorVT(MVT::i32, VT.getVectorNumElements() / 2);
23069 V = DAG.getBitcast(DVT, V);
23070 DCI.AddToWorklist(V.getNode());
23071 V = DAG.getNode(X86ISD::PSHUFD, DL, DVT, V,
23072 getV4X86ShuffleImm8ForMask(DMask, DL, DAG));
23073 DCI.AddToWorklist(V.getNode());
23074 return DAG.getBitcast(VT, V);
23077 // Look for shuffle patterns which can be implemented as a single unpack.
23078 // FIXME: This doesn't handle the location of the PSHUFD generically, and
23079 // only works when we have a PSHUFD followed by two half-shuffles.
23080 if (Mask[0] == Mask[1] && Mask[2] == Mask[3] &&
23081 (V.getOpcode() == X86ISD::PSHUFLW ||
23082 V.getOpcode() == X86ISD::PSHUFHW) &&
23083 V.getOpcode() != N.getOpcode() &&
23085 SDValue D = V.getOperand(0);
23086 while (D.getOpcode() == ISD::BITCAST && D.hasOneUse())
23087 D = D.getOperand(0);
23088 if (D.getOpcode() == X86ISD::PSHUFD && D.hasOneUse()) {
23089 SmallVector<int, 4> VMask = getPSHUFShuffleMask(V);
23090 SmallVector<int, 4> DMask = getPSHUFShuffleMask(D);
23091 int NOffset = N.getOpcode() == X86ISD::PSHUFLW ? 0 : 4;
23092 int VOffset = V.getOpcode() == X86ISD::PSHUFLW ? 0 : 4;
23094 for (int i = 0; i < 4; ++i) {
23095 WordMask[i + NOffset] = Mask[i] + NOffset;
23096 WordMask[i + VOffset] = VMask[i] + VOffset;
23098 // Map the word mask through the DWord mask.
23100 for (int i = 0; i < 8; ++i)
23101 MappedMask[i] = 2 * DMask[WordMask[i] / 2] + WordMask[i] % 2;
23102 if (makeArrayRef(MappedMask).equals({0, 0, 1, 1, 2, 2, 3, 3}) ||
23103 makeArrayRef(MappedMask).equals({4, 4, 5, 5, 6, 6, 7, 7})) {
23104 // We can replace all three shuffles with an unpack.
23105 V = DAG.getBitcast(VT, D.getOperand(0));
23106 DCI.AddToWorklist(V.getNode());
23107 return DAG.getNode(MappedMask[0] == 0 ? X86ISD::UNPCKL
23116 case X86ISD::PSHUFD:
23117 if (SDValue NewN = combineRedundantDWordShuffle(N, Mask, DAG, DCI))
23126 /// \brief Try to combine a shuffle into a target-specific add-sub node.
23128 /// We combine this directly on the abstract vector shuffle nodes so it is
23129 /// easier to generically match. We also insert dummy vector shuffle nodes for
23130 /// the operands which explicitly discard the lanes which are unused by this
23131 /// operation to try to flow through the rest of the combiner the fact that
23132 /// they're unused.
23133 static SDValue combineShuffleToAddSub(SDNode *N, SelectionDAG &DAG) {
23135 EVT VT = N->getValueType(0);
23137 // We only handle target-independent shuffles.
23138 // FIXME: It would be easy and harmless to use the target shuffle mask
23139 // extraction tool to support more.
23140 if (N->getOpcode() != ISD::VECTOR_SHUFFLE)
23143 auto *SVN = cast<ShuffleVectorSDNode>(N);
23144 SmallVector<int, 8> Mask;
23145 for (int M : SVN->getMask())
23148 SDValue V1 = N->getOperand(0);
23149 SDValue V2 = N->getOperand(1);
23151 // We require the first shuffle operand to be the FSUB node, and the second to
23152 // be the FADD node.
23153 if (V1.getOpcode() == ISD::FADD && V2.getOpcode() == ISD::FSUB) {
23154 ShuffleVectorSDNode::commuteMask(Mask);
23156 } else if (V1.getOpcode() != ISD::FSUB || V2.getOpcode() != ISD::FADD)
23159 // If there are other uses of these operations we can't fold them.
23160 if (!V1->hasOneUse() || !V2->hasOneUse())
23163 // Ensure that both operations have the same operands. Note that we can
23164 // commute the FADD operands.
23165 SDValue LHS = V1->getOperand(0), RHS = V1->getOperand(1);
23166 if ((V2->getOperand(0) != LHS || V2->getOperand(1) != RHS) &&
23167 (V2->getOperand(0) != RHS || V2->getOperand(1) != LHS))
23170 // We're looking for blends between FADD and FSUB nodes. We insist on these
23171 // nodes being lined up in a specific expected pattern.
23172 if (!(isShuffleEquivalent(V1, V2, Mask, {0, 3}) ||
23173 isShuffleEquivalent(V1, V2, Mask, {0, 5, 2, 7}) ||
23174 isShuffleEquivalent(V1, V2, Mask, {0, 9, 2, 11, 4, 13, 6, 15})))
23177 // Only specific types are legal at this point, assert so we notice if and
23178 // when these change.
23179 assert((VT == MVT::v4f32 || VT == MVT::v2f64 || VT == MVT::v8f32 ||
23180 VT == MVT::v4f64) &&
23181 "Unknown vector type encountered!");
23183 return DAG.getNode(X86ISD::ADDSUB, DL, VT, LHS, RHS);
23186 /// PerformShuffleCombine - Performs several different shuffle combines.
23187 static SDValue PerformShuffleCombine(SDNode *N, SelectionDAG &DAG,
23188 TargetLowering::DAGCombinerInfo &DCI,
23189 const X86Subtarget *Subtarget) {
23191 SDValue N0 = N->getOperand(0);
23192 SDValue N1 = N->getOperand(1);
23193 EVT VT = N->getValueType(0);
23195 // Don't create instructions with illegal types after legalize types has run.
23196 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
23197 if (!DCI.isBeforeLegalize() && !TLI.isTypeLegal(VT.getVectorElementType()))
23200 // If we have legalized the vector types, look for blends of FADD and FSUB
23201 // nodes that we can fuse into an ADDSUB node.
23202 if (TLI.isTypeLegal(VT) && Subtarget->hasSSE3())
23203 if (SDValue AddSub = combineShuffleToAddSub(N, DAG))
23206 // Combine 256-bit vector shuffles. This is only profitable when in AVX mode
23207 if (Subtarget->hasFp256() && VT.is256BitVector() &&
23208 N->getOpcode() == ISD::VECTOR_SHUFFLE)
23209 return PerformShuffleCombine256(N, DAG, DCI, Subtarget);
23211 // During Type Legalization, when promoting illegal vector types,
23212 // the backend might introduce new shuffle dag nodes and bitcasts.
23214 // This code performs the following transformation:
23215 // fold: (shuffle (bitcast (BINOP A, B)), Undef, <Mask>) ->
23216 // (shuffle (BINOP (bitcast A), (bitcast B)), Undef, <Mask>)
23218 // We do this only if both the bitcast and the BINOP dag nodes have
23219 // one use. Also, perform this transformation only if the new binary
23220 // operation is legal. This is to avoid introducing dag nodes that
23221 // potentially need to be further expanded (or custom lowered) into a
23222 // less optimal sequence of dag nodes.
23223 if (!DCI.isBeforeLegalize() && DCI.isBeforeLegalizeOps() &&
23224 N1.getOpcode() == ISD::UNDEF && N0.hasOneUse() &&
23225 N0.getOpcode() == ISD::BITCAST) {
23226 SDValue BC0 = N0.getOperand(0);
23227 EVT SVT = BC0.getValueType();
23228 unsigned Opcode = BC0.getOpcode();
23229 unsigned NumElts = VT.getVectorNumElements();
23231 if (BC0.hasOneUse() && SVT.isVector() &&
23232 SVT.getVectorNumElements() * 2 == NumElts &&
23233 TLI.isOperationLegal(Opcode, VT)) {
23234 bool CanFold = false;
23246 unsigned SVTNumElts = SVT.getVectorNumElements();
23247 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
23248 for (unsigned i = 0, e = SVTNumElts; i != e && CanFold; ++i)
23249 CanFold = SVOp->getMaskElt(i) == (int)(i * 2);
23250 for (unsigned i = SVTNumElts, e = NumElts; i != e && CanFold; ++i)
23251 CanFold = SVOp->getMaskElt(i) < 0;
23254 SDValue BC00 = DAG.getBitcast(VT, BC0.getOperand(0));
23255 SDValue BC01 = DAG.getBitcast(VT, BC0.getOperand(1));
23256 SDValue NewBinOp = DAG.getNode(BC0.getOpcode(), dl, VT, BC00, BC01);
23257 return DAG.getVectorShuffle(VT, dl, NewBinOp, N1, &SVOp->getMask()[0]);
23262 // Combine a vector_shuffle that is equal to build_vector load1, load2, load3,
23263 // load4, <0, 1, 2, 3> into a 128-bit load if the load addresses are
23264 // consecutive, non-overlapping, and in the right order.
23265 SmallVector<SDValue, 16> Elts;
23266 for (unsigned i = 0, e = VT.getVectorNumElements(); i != e; ++i)
23267 Elts.push_back(getShuffleScalarElt(N, i, DAG, 0));
23269 if (SDValue LD = EltsFromConsecutiveLoads(VT, Elts, dl, DAG, true))
23272 if (isTargetShuffle(N->getOpcode())) {
23274 PerformTargetShuffleCombine(SDValue(N, 0), DAG, DCI, Subtarget);
23275 if (Shuffle.getNode())
23278 // Try recursively combining arbitrary sequences of x86 shuffle
23279 // instructions into higher-order shuffles. We do this after combining
23280 // specific PSHUF instruction sequences into their minimal form so that we
23281 // can evaluate how many specialized shuffle instructions are involved in
23282 // a particular chain.
23283 SmallVector<int, 1> NonceMask; // Just a placeholder.
23284 NonceMask.push_back(0);
23285 if (combineX86ShufflesRecursively(SDValue(N, 0), SDValue(N, 0), NonceMask,
23286 /*Depth*/ 1, /*HasPSHUFB*/ false, DAG,
23288 return SDValue(); // This routine will use CombineTo to replace N.
23294 /// XFormVExtractWithShuffleIntoLoad - Check if a vector extract from a target
23295 /// specific shuffle of a load can be folded into a single element load.
23296 /// Similar handling for VECTOR_SHUFFLE is performed by DAGCombiner, but
23297 /// shuffles have been custom lowered so we need to handle those here.
23298 static SDValue XFormVExtractWithShuffleIntoLoad(SDNode *N, SelectionDAG &DAG,
23299 TargetLowering::DAGCombinerInfo &DCI) {
23300 if (DCI.isBeforeLegalizeOps())
23303 SDValue InVec = N->getOperand(0);
23304 SDValue EltNo = N->getOperand(1);
23306 if (!isa<ConstantSDNode>(EltNo))
23309 EVT OriginalVT = InVec.getValueType();
23311 if (InVec.getOpcode() == ISD::BITCAST) {
23312 // Don't duplicate a load with other uses.
23313 if (!InVec.hasOneUse())
23315 EVT BCVT = InVec.getOperand(0).getValueType();
23316 if (!BCVT.isVector() ||
23317 BCVT.getVectorNumElements() != OriginalVT.getVectorNumElements())
23319 InVec = InVec.getOperand(0);
23322 EVT CurrentVT = InVec.getValueType();
23324 if (!isTargetShuffle(InVec.getOpcode()))
23327 // Don't duplicate a load with other uses.
23328 if (!InVec.hasOneUse())
23331 SmallVector<int, 16> ShuffleMask;
23333 if (!getTargetShuffleMask(InVec.getNode(), CurrentVT.getSimpleVT(),
23334 ShuffleMask, UnaryShuffle))
23337 // Select the input vector, guarding against out of range extract vector.
23338 unsigned NumElems = CurrentVT.getVectorNumElements();
23339 int Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();
23340 int Idx = (Elt > (int)NumElems) ? -1 : ShuffleMask[Elt];
23341 SDValue LdNode = (Idx < (int)NumElems) ? InVec.getOperand(0)
23342 : InVec.getOperand(1);
23344 // If inputs to shuffle are the same for both ops, then allow 2 uses
23345 unsigned AllowedUses = InVec.getNumOperands() > 1 &&
23346 InVec.getOperand(0) == InVec.getOperand(1) ? 2 : 1;
23348 if (LdNode.getOpcode() == ISD::BITCAST) {
23349 // Don't duplicate a load with other uses.
23350 if (!LdNode.getNode()->hasNUsesOfValue(AllowedUses, 0))
23353 AllowedUses = 1; // only allow 1 load use if we have a bitcast
23354 LdNode = LdNode.getOperand(0);
23357 if (!ISD::isNormalLoad(LdNode.getNode()))
23360 LoadSDNode *LN0 = cast<LoadSDNode>(LdNode);
23362 if (!LN0 ||!LN0->hasNUsesOfValue(AllowedUses, 0) || LN0->isVolatile())
23365 EVT EltVT = N->getValueType(0);
23366 // If there's a bitcast before the shuffle, check if the load type and
23367 // alignment is valid.
23368 unsigned Align = LN0->getAlignment();
23369 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
23370 unsigned NewAlign = DAG.getDataLayout().getABITypeAlignment(
23371 EltVT.getTypeForEVT(*DAG.getContext()));
23373 if (NewAlign > Align || !TLI.isOperationLegalOrCustom(ISD::LOAD, EltVT))
23376 // All checks match so transform back to vector_shuffle so that DAG combiner
23377 // can finish the job
23380 // Create shuffle node taking into account the case that its a unary shuffle
23381 SDValue Shuffle = (UnaryShuffle) ? DAG.getUNDEF(CurrentVT)
23382 : InVec.getOperand(1);
23383 Shuffle = DAG.getVectorShuffle(CurrentVT, dl,
23384 InVec.getOperand(0), Shuffle,
23386 Shuffle = DAG.getBitcast(OriginalVT, Shuffle);
23387 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, N->getValueType(0), Shuffle,
23391 static SDValue PerformBITCASTCombine(SDNode *N, SelectionDAG &DAG,
23392 const X86Subtarget *Subtarget) {
23393 SDValue N0 = N->getOperand(0);
23394 EVT VT = N->getValueType(0);
23396 // Detect bitcasts between i32 to x86mmx low word. Since MMX types are
23397 // special and don't usually play with other vector types, it's better to
23398 // handle them early to be sure we emit efficient code by avoiding
23399 // store-load conversions.
23400 if (VT == MVT::x86mmx && N0.getOpcode() == ISD::BUILD_VECTOR &&
23401 N0.getValueType() == MVT::v2i32 &&
23402 isNullConstant(N0.getOperand(1))) {
23403 SDValue N00 = N0->getOperand(0);
23404 if (N00.getValueType() == MVT::i32)
23405 return DAG.getNode(X86ISD::MMX_MOVW2D, SDLoc(N00), VT, N00);
23408 // Convert a bitcasted integer logic operation that has one bitcasted
23409 // floating-point operand and one constant operand into a floating-point
23410 // logic operation. This may create a load of the constant, but that is
23411 // cheaper than materializing the constant in an integer register and
23412 // transferring it to an SSE register or transferring the SSE operand to
23413 // integer register and back.
23415 switch (N0.getOpcode()) {
23416 case ISD::AND: FPOpcode = X86ISD::FAND; break;
23417 case ISD::OR: FPOpcode = X86ISD::FOR; break;
23418 case ISD::XOR: FPOpcode = X86ISD::FXOR; break;
23419 default: return SDValue();
23421 if (((Subtarget->hasSSE1() && VT == MVT::f32) ||
23422 (Subtarget->hasSSE2() && VT == MVT::f64)) &&
23423 isa<ConstantSDNode>(N0.getOperand(1)) &&
23424 N0.getOperand(0).getOpcode() == ISD::BITCAST &&
23425 N0.getOperand(0).getOperand(0).getValueType() == VT) {
23426 SDValue N000 = N0.getOperand(0).getOperand(0);
23427 SDValue FPConst = DAG.getBitcast(VT, N0.getOperand(1));
23428 return DAG.getNode(FPOpcode, SDLoc(N0), VT, N000, FPConst);
23434 /// PerformEXTRACT_VECTOR_ELTCombine - Detect vector gather/scatter index
23435 /// generation and convert it from being a bunch of shuffles and extracts
23436 /// into a somewhat faster sequence. For i686, the best sequence is apparently
23437 /// storing the value and loading scalars back, while for x64 we should
23438 /// use 64-bit extracts and shifts.
23439 static SDValue PerformEXTRACT_VECTOR_ELTCombine(SDNode *N, SelectionDAG &DAG,
23440 TargetLowering::DAGCombinerInfo &DCI) {
23441 if (SDValue NewOp = XFormVExtractWithShuffleIntoLoad(N, DAG, DCI))
23444 SDValue InputVector = N->getOperand(0);
23445 SDLoc dl(InputVector);
23446 // Detect mmx to i32 conversion through a v2i32 elt extract.
23447 if (InputVector.getOpcode() == ISD::BITCAST && InputVector.hasOneUse() &&
23448 N->getValueType(0) == MVT::i32 &&
23449 InputVector.getValueType() == MVT::v2i32) {
23451 // The bitcast source is a direct mmx result.
23452 SDValue MMXSrc = InputVector.getNode()->getOperand(0);
23453 if (MMXSrc.getValueType() == MVT::x86mmx)
23454 return DAG.getNode(X86ISD::MMX_MOVD2W, SDLoc(InputVector),
23455 N->getValueType(0),
23456 InputVector.getNode()->getOperand(0));
23458 // The mmx is indirect: (i64 extract_elt (v1i64 bitcast (x86mmx ...))).
23459 if (MMXSrc.getOpcode() == ISD::EXTRACT_VECTOR_ELT && MMXSrc.hasOneUse() &&
23460 MMXSrc.getValueType() == MVT::i64) {
23461 SDValue MMXSrcOp = MMXSrc.getOperand(0);
23462 if (MMXSrcOp.hasOneUse() && MMXSrcOp.getOpcode() == ISD::BITCAST &&
23463 MMXSrcOp.getValueType() == MVT::v1i64 &&
23464 MMXSrcOp.getOperand(0).getValueType() == MVT::x86mmx)
23465 return DAG.getNode(X86ISD::MMX_MOVD2W, SDLoc(InputVector),
23466 N->getValueType(0), MMXSrcOp.getOperand(0));
23470 EVT VT = N->getValueType(0);
23472 if (VT == MVT::i1 && isa<ConstantSDNode>(N->getOperand(1)) &&
23473 InputVector.getOpcode() == ISD::BITCAST &&
23474 isa<ConstantSDNode>(InputVector.getOperand(0))) {
23475 uint64_t ExtractedElt =
23476 cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
23477 uint64_t InputValue =
23478 cast<ConstantSDNode>(InputVector.getOperand(0))->getZExtValue();
23479 uint64_t Res = (InputValue >> ExtractedElt) & 1;
23480 return DAG.getConstant(Res, dl, MVT::i1);
23482 // Only operate on vectors of 4 elements, where the alternative shuffling
23483 // gets to be more expensive.
23484 if (InputVector.getValueType() != MVT::v4i32)
23487 // Check whether every use of InputVector is an EXTRACT_VECTOR_ELT with a
23488 // single use which is a sign-extend or zero-extend, and all elements are
23490 SmallVector<SDNode *, 4> Uses;
23491 unsigned ExtractedElements = 0;
23492 for (SDNode::use_iterator UI = InputVector.getNode()->use_begin(),
23493 UE = InputVector.getNode()->use_end(); UI != UE; ++UI) {
23494 if (UI.getUse().getResNo() != InputVector.getResNo())
23497 SDNode *Extract = *UI;
23498 if (Extract->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
23501 if (Extract->getValueType(0) != MVT::i32)
23503 if (!Extract->hasOneUse())
23505 if (Extract->use_begin()->getOpcode() != ISD::SIGN_EXTEND &&
23506 Extract->use_begin()->getOpcode() != ISD::ZERO_EXTEND)
23508 if (!isa<ConstantSDNode>(Extract->getOperand(1)))
23511 // Record which element was extracted.
23512 ExtractedElements |=
23513 1 << cast<ConstantSDNode>(Extract->getOperand(1))->getZExtValue();
23515 Uses.push_back(Extract);
23518 // If not all the elements were used, this may not be worthwhile.
23519 if (ExtractedElements != 15)
23522 // Ok, we've now decided to do the transformation.
23523 // If 64-bit shifts are legal, use the extract-shift sequence,
23524 // otherwise bounce the vector off the cache.
23525 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
23528 if (TLI.isOperationLegal(ISD::SRA, MVT::i64)) {
23529 SDValue Cst = DAG.getBitcast(MVT::v2i64, InputVector);
23530 auto &DL = DAG.getDataLayout();
23531 EVT VecIdxTy = DAG.getTargetLoweringInfo().getVectorIdxTy(DL);
23532 SDValue BottomHalf = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i64, Cst,
23533 DAG.getConstant(0, dl, VecIdxTy));
23534 SDValue TopHalf = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i64, Cst,
23535 DAG.getConstant(1, dl, VecIdxTy));
23537 SDValue ShAmt = DAG.getConstant(
23538 32, dl, DAG.getTargetLoweringInfo().getShiftAmountTy(MVT::i64, DL));
23539 Vals[0] = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, BottomHalf);
23540 Vals[1] = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32,
23541 DAG.getNode(ISD::SRA, dl, MVT::i64, BottomHalf, ShAmt));
23542 Vals[2] = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, TopHalf);
23543 Vals[3] = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32,
23544 DAG.getNode(ISD::SRA, dl, MVT::i64, TopHalf, ShAmt));
23546 // Store the value to a temporary stack slot.
23547 SDValue StackPtr = DAG.CreateStackTemporary(InputVector.getValueType());
23548 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, InputVector, StackPtr,
23549 MachinePointerInfo(), false, false, 0);
23551 EVT ElementType = InputVector.getValueType().getVectorElementType();
23552 unsigned EltSize = ElementType.getSizeInBits() / 8;
23554 // Replace each use (extract) with a load of the appropriate element.
23555 for (unsigned i = 0; i < 4; ++i) {
23556 uint64_t Offset = EltSize * i;
23557 auto PtrVT = TLI.getPointerTy(DAG.getDataLayout());
23558 SDValue OffsetVal = DAG.getConstant(Offset, dl, PtrVT);
23560 SDValue ScalarAddr =
23561 DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, OffsetVal);
23563 // Load the scalar.
23564 Vals[i] = DAG.getLoad(ElementType, dl, Ch,
23565 ScalarAddr, MachinePointerInfo(),
23566 false, false, false, 0);
23571 // Replace the extracts
23572 for (SmallVectorImpl<SDNode *>::iterator UI = Uses.begin(),
23573 UE = Uses.end(); UI != UE; ++UI) {
23574 SDNode *Extract = *UI;
23576 SDValue Idx = Extract->getOperand(1);
23577 uint64_t IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
23578 DAG.ReplaceAllUsesOfValueWith(SDValue(Extract, 0), Vals[IdxVal]);
23581 // The replacement was made in place; don't return anything.
23586 transformVSELECTtoBlendVECTOR_SHUFFLE(SDNode *N, SelectionDAG &DAG,
23587 const X86Subtarget *Subtarget) {
23589 SDValue Cond = N->getOperand(0);
23590 SDValue LHS = N->getOperand(1);
23591 SDValue RHS = N->getOperand(2);
23593 if (Cond.getOpcode() == ISD::SIGN_EXTEND) {
23594 SDValue CondSrc = Cond->getOperand(0);
23595 if (CondSrc->getOpcode() == ISD::SIGN_EXTEND_INREG)
23596 Cond = CondSrc->getOperand(0);
23599 if (!ISD::isBuildVectorOfConstantSDNodes(Cond.getNode()))
23602 // A vselect where all conditions and data are constants can be optimized into
23603 // a single vector load by SelectionDAGLegalize::ExpandBUILD_VECTOR().
23604 if (ISD::isBuildVectorOfConstantSDNodes(LHS.getNode()) &&
23605 ISD::isBuildVectorOfConstantSDNodes(RHS.getNode()))
23608 unsigned MaskValue = 0;
23609 if (!BUILD_VECTORtoBlendMask(cast<BuildVectorSDNode>(Cond), MaskValue))
23612 MVT VT = N->getSimpleValueType(0);
23613 unsigned NumElems = VT.getVectorNumElements();
23614 SmallVector<int, 8> ShuffleMask(NumElems, -1);
23615 for (unsigned i = 0; i < NumElems; ++i) {
23616 // Be sure we emit undef where we can.
23617 if (Cond.getOperand(i)->getOpcode() == ISD::UNDEF)
23618 ShuffleMask[i] = -1;
23620 ShuffleMask[i] = i + NumElems * ((MaskValue >> i) & 1);
23623 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
23624 if (!TLI.isShuffleMaskLegal(ShuffleMask, VT))
23626 return DAG.getVectorShuffle(VT, dl, LHS, RHS, &ShuffleMask[0]);
23629 /// PerformSELECTCombine - Do target-specific dag combines on SELECT and VSELECT
23631 static SDValue PerformSELECTCombine(SDNode *N, SelectionDAG &DAG,
23632 TargetLowering::DAGCombinerInfo &DCI,
23633 const X86Subtarget *Subtarget) {
23635 SDValue Cond = N->getOperand(0);
23636 // Get the LHS/RHS of the select.
23637 SDValue LHS = N->getOperand(1);
23638 SDValue RHS = N->getOperand(2);
23639 EVT VT = LHS.getValueType();
23640 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
23642 // If we have SSE[12] support, try to form min/max nodes. SSE min/max
23643 // instructions match the semantics of the common C idiom x<y?x:y but not
23644 // x<=y?x:y, because of how they handle negative zero (which can be
23645 // ignored in unsafe-math mode).
23646 // We also try to create v2f32 min/max nodes, which we later widen to v4f32.
23647 if (Cond.getOpcode() == ISD::SETCC && VT.isFloatingPoint() &&
23648 VT != MVT::f80 && (TLI.isTypeLegal(VT) || VT == MVT::v2f32) &&
23649 (Subtarget->hasSSE2() ||
23650 (Subtarget->hasSSE1() && VT.getScalarType() == MVT::f32))) {
23651 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
23653 unsigned Opcode = 0;
23654 // Check for x CC y ? x : y.
23655 if (DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
23656 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
23660 // Converting this to a min would handle NaNs incorrectly, and swapping
23661 // the operands would cause it to handle comparisons between positive
23662 // and negative zero incorrectly.
23663 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
23664 if (!DAG.getTarget().Options.UnsafeFPMath &&
23665 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
23667 std::swap(LHS, RHS);
23669 Opcode = X86ISD::FMIN;
23672 // Converting this to a min would handle comparisons between positive
23673 // and negative zero incorrectly.
23674 if (!DAG.getTarget().Options.UnsafeFPMath &&
23675 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
23677 Opcode = X86ISD::FMIN;
23680 // Converting this to a min would handle both negative zeros and NaNs
23681 // incorrectly, but we can swap the operands to fix both.
23682 std::swap(LHS, RHS);
23686 Opcode = X86ISD::FMIN;
23690 // Converting this to a max would handle comparisons between positive
23691 // and negative zero incorrectly.
23692 if (!DAG.getTarget().Options.UnsafeFPMath &&
23693 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
23695 Opcode = X86ISD::FMAX;
23698 // Converting this to a max would handle NaNs incorrectly, and swapping
23699 // the operands would cause it to handle comparisons between positive
23700 // and negative zero incorrectly.
23701 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
23702 if (!DAG.getTarget().Options.UnsafeFPMath &&
23703 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
23705 std::swap(LHS, RHS);
23707 Opcode = X86ISD::FMAX;
23710 // Converting this to a max would handle both negative zeros and NaNs
23711 // incorrectly, but we can swap the operands to fix both.
23712 std::swap(LHS, RHS);
23716 Opcode = X86ISD::FMAX;
23719 // Check for x CC y ? y : x -- a min/max with reversed arms.
23720 } else if (DAG.isEqualTo(LHS, Cond.getOperand(1)) &&
23721 DAG.isEqualTo(RHS, Cond.getOperand(0))) {
23725 // Converting this to a min would handle comparisons between positive
23726 // and negative zero incorrectly, and swapping the operands would
23727 // cause it to handle NaNs incorrectly.
23728 if (!DAG.getTarget().Options.UnsafeFPMath &&
23729 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS))) {
23730 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
23732 std::swap(LHS, RHS);
23734 Opcode = X86ISD::FMIN;
23737 // Converting this to a min would handle NaNs incorrectly.
23738 if (!DAG.getTarget().Options.UnsafeFPMath &&
23739 (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)))
23741 Opcode = X86ISD::FMIN;
23744 // Converting this to a min would handle both negative zeros and NaNs
23745 // incorrectly, but we can swap the operands to fix both.
23746 std::swap(LHS, RHS);
23750 Opcode = X86ISD::FMIN;
23754 // Converting this to a max would handle NaNs incorrectly.
23755 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
23757 Opcode = X86ISD::FMAX;
23760 // Converting this to a max would handle comparisons between positive
23761 // and negative zero incorrectly, and swapping the operands would
23762 // cause it to handle NaNs incorrectly.
23763 if (!DAG.getTarget().Options.UnsafeFPMath &&
23764 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS)) {
23765 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
23767 std::swap(LHS, RHS);
23769 Opcode = X86ISD::FMAX;
23772 // Converting this to a max would handle both negative zeros and NaNs
23773 // incorrectly, but we can swap the operands to fix both.
23774 std::swap(LHS, RHS);
23778 Opcode = X86ISD::FMAX;
23784 return DAG.getNode(Opcode, DL, N->getValueType(0), LHS, RHS);
23787 EVT CondVT = Cond.getValueType();
23788 if (Subtarget->hasAVX512() && VT.isVector() && CondVT.isVector() &&
23789 CondVT.getVectorElementType() == MVT::i1) {
23790 // v16i8 (select v16i1, v16i8, v16i8) does not have a proper
23791 // lowering on KNL. In this case we convert it to
23792 // v16i8 (select v16i8, v16i8, v16i8) and use AVX instruction.
23793 // The same situation for all 128 and 256-bit vectors of i8 and i16.
23794 // Since SKX these selects have a proper lowering.
23795 EVT OpVT = LHS.getValueType();
23796 if ((OpVT.is128BitVector() || OpVT.is256BitVector()) &&
23797 (OpVT.getVectorElementType() == MVT::i8 ||
23798 OpVT.getVectorElementType() == MVT::i16) &&
23799 !(Subtarget->hasBWI() && Subtarget->hasVLX())) {
23800 Cond = DAG.getNode(ISD::SIGN_EXTEND, DL, OpVT, Cond);
23801 DCI.AddToWorklist(Cond.getNode());
23802 return DAG.getNode(N->getOpcode(), DL, OpVT, Cond, LHS, RHS);
23805 // If this is a select between two integer constants, try to do some
23807 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(LHS)) {
23808 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(RHS))
23809 // Don't do this for crazy integer types.
23810 if (DAG.getTargetLoweringInfo().isTypeLegal(LHS.getValueType())) {
23811 // If this is efficiently invertible, canonicalize the LHSC/RHSC values
23812 // so that TrueC (the true value) is larger than FalseC.
23813 bool NeedsCondInvert = false;
23815 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue()) &&
23816 // Efficiently invertible.
23817 (Cond.getOpcode() == ISD::SETCC || // setcc -> invertible.
23818 (Cond.getOpcode() == ISD::XOR && // xor(X, C) -> invertible.
23819 isa<ConstantSDNode>(Cond.getOperand(1))))) {
23820 NeedsCondInvert = true;
23821 std::swap(TrueC, FalseC);
23824 // Optimize C ? 8 : 0 -> zext(C) << 3. Likewise for any pow2/0.
23825 if (FalseC->getAPIntValue() == 0 &&
23826 TrueC->getAPIntValue().isPowerOf2()) {
23827 if (NeedsCondInvert) // Invert the condition if needed.
23828 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
23829 DAG.getConstant(1, DL, Cond.getValueType()));
23831 // Zero extend the condition if needed.
23832 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, LHS.getValueType(), Cond);
23834 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
23835 return DAG.getNode(ISD::SHL, DL, LHS.getValueType(), Cond,
23836 DAG.getConstant(ShAmt, DL, MVT::i8));
23839 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst.
23840 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
23841 if (NeedsCondInvert) // Invert the condition if needed.
23842 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
23843 DAG.getConstant(1, DL, Cond.getValueType()));
23845 // Zero extend the condition if needed.
23846 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
23847 FalseC->getValueType(0), Cond);
23848 return DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
23849 SDValue(FalseC, 0));
23852 // Optimize cases that will turn into an LEA instruction. This requires
23853 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
23854 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
23855 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
23856 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
23858 bool isFastMultiplier = false;
23860 switch ((unsigned char)Diff) {
23862 case 1: // result = add base, cond
23863 case 2: // result = lea base( , cond*2)
23864 case 3: // result = lea base(cond, cond*2)
23865 case 4: // result = lea base( , cond*4)
23866 case 5: // result = lea base(cond, cond*4)
23867 case 8: // result = lea base( , cond*8)
23868 case 9: // result = lea base(cond, cond*8)
23869 isFastMultiplier = true;
23874 if (isFastMultiplier) {
23875 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
23876 if (NeedsCondInvert) // Invert the condition if needed.
23877 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
23878 DAG.getConstant(1, DL, Cond.getValueType()));
23880 // Zero extend the condition if needed.
23881 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
23883 // Scale the condition by the difference.
23885 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
23886 DAG.getConstant(Diff, DL,
23887 Cond.getValueType()));
23889 // Add the base if non-zero.
23890 if (FalseC->getAPIntValue() != 0)
23891 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
23892 SDValue(FalseC, 0));
23899 // Canonicalize max and min:
23900 // (x > y) ? x : y -> (x >= y) ? x : y
23901 // (x < y) ? x : y -> (x <= y) ? x : y
23902 // This allows use of COND_S / COND_NS (see TranslateX86CC) which eliminates
23903 // the need for an extra compare
23904 // against zero. e.g.
23905 // (x - y) > 0 : (x - y) ? 0 -> (x - y) >= 0 : (x - y) ? 0
23907 // testl %edi, %edi
23909 // cmovgl %edi, %eax
23913 // cmovsl %eax, %edi
23914 if (N->getOpcode() == ISD::SELECT && Cond.getOpcode() == ISD::SETCC &&
23915 DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
23916 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
23917 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
23922 ISD::CondCode NewCC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGE;
23923 Cond = DAG.getSetCC(SDLoc(Cond), Cond.getValueType(),
23924 Cond.getOperand(0), Cond.getOperand(1), NewCC);
23925 return DAG.getNode(ISD::SELECT, DL, VT, Cond, LHS, RHS);
23930 // Early exit check
23931 if (!TLI.isTypeLegal(VT))
23934 // Match VSELECTs into subs with unsigned saturation.
23935 if (N->getOpcode() == ISD::VSELECT && Cond.getOpcode() == ISD::SETCC &&
23936 // psubus is available in SSE2 and AVX2 for i8 and i16 vectors.
23937 ((Subtarget->hasSSE2() && (VT == MVT::v16i8 || VT == MVT::v8i16)) ||
23938 (Subtarget->hasAVX2() && (VT == MVT::v32i8 || VT == MVT::v16i16)))) {
23939 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
23941 // Check if one of the arms of the VSELECT is a zero vector. If it's on the
23942 // left side invert the predicate to simplify logic below.
23944 if (ISD::isBuildVectorAllZeros(LHS.getNode())) {
23946 CC = ISD::getSetCCInverse(CC, true);
23947 } else if (ISD::isBuildVectorAllZeros(RHS.getNode())) {
23951 if (Other.getNode() && Other->getNumOperands() == 2 &&
23952 DAG.isEqualTo(Other->getOperand(0), Cond.getOperand(0))) {
23953 SDValue OpLHS = Other->getOperand(0), OpRHS = Other->getOperand(1);
23954 SDValue CondRHS = Cond->getOperand(1);
23956 // Look for a general sub with unsigned saturation first.
23957 // x >= y ? x-y : 0 --> subus x, y
23958 // x > y ? x-y : 0 --> subus x, y
23959 if ((CC == ISD::SETUGE || CC == ISD::SETUGT) &&
23960 Other->getOpcode() == ISD::SUB && DAG.isEqualTo(OpRHS, CondRHS))
23961 return DAG.getNode(X86ISD::SUBUS, DL, VT, OpLHS, OpRHS);
23963 if (auto *OpRHSBV = dyn_cast<BuildVectorSDNode>(OpRHS))
23964 if (auto *OpRHSConst = OpRHSBV->getConstantSplatNode()) {
23965 if (auto *CondRHSBV = dyn_cast<BuildVectorSDNode>(CondRHS))
23966 if (auto *CondRHSConst = CondRHSBV->getConstantSplatNode())
23967 // If the RHS is a constant we have to reverse the const
23968 // canonicalization.
23969 // x > C-1 ? x+-C : 0 --> subus x, C
23970 if (CC == ISD::SETUGT && Other->getOpcode() == ISD::ADD &&
23971 CondRHSConst->getAPIntValue() ==
23972 (-OpRHSConst->getAPIntValue() - 1))
23973 return DAG.getNode(
23974 X86ISD::SUBUS, DL, VT, OpLHS,
23975 DAG.getConstant(-OpRHSConst->getAPIntValue(), DL, VT));
23977 // Another special case: If C was a sign bit, the sub has been
23978 // canonicalized into a xor.
23979 // FIXME: Would it be better to use computeKnownBits to determine
23980 // whether it's safe to decanonicalize the xor?
23981 // x s< 0 ? x^C : 0 --> subus x, C
23982 if (CC == ISD::SETLT && Other->getOpcode() == ISD::XOR &&
23983 ISD::isBuildVectorAllZeros(CondRHS.getNode()) &&
23984 OpRHSConst->getAPIntValue().isSignBit())
23985 // Note that we have to rebuild the RHS constant here to ensure we
23986 // don't rely on particular values of undef lanes.
23987 return DAG.getNode(
23988 X86ISD::SUBUS, DL, VT, OpLHS,
23989 DAG.getConstant(OpRHSConst->getAPIntValue(), DL, VT));
23994 // Simplify vector selection if condition value type matches vselect
23996 if (N->getOpcode() == ISD::VSELECT && CondVT == VT) {
23997 assert(Cond.getValueType().isVector() &&
23998 "vector select expects a vector selector!");
24000 bool TValIsAllOnes = ISD::isBuildVectorAllOnes(LHS.getNode());
24001 bool FValIsAllZeros = ISD::isBuildVectorAllZeros(RHS.getNode());
24003 // Try invert the condition if true value is not all 1s and false value
24005 if (!TValIsAllOnes && !FValIsAllZeros &&
24006 // Check if the selector will be produced by CMPP*/PCMP*
24007 Cond.getOpcode() == ISD::SETCC &&
24008 // Check if SETCC has already been promoted
24009 TLI.getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), VT) ==
24011 bool TValIsAllZeros = ISD::isBuildVectorAllZeros(LHS.getNode());
24012 bool FValIsAllOnes = ISD::isBuildVectorAllOnes(RHS.getNode());
24014 if (TValIsAllZeros || FValIsAllOnes) {
24015 SDValue CC = Cond.getOperand(2);
24016 ISD::CondCode NewCC =
24017 ISD::getSetCCInverse(cast<CondCodeSDNode>(CC)->get(),
24018 Cond.getOperand(0).getValueType().isInteger());
24019 Cond = DAG.getSetCC(DL, CondVT, Cond.getOperand(0), Cond.getOperand(1), NewCC);
24020 std::swap(LHS, RHS);
24021 TValIsAllOnes = FValIsAllOnes;
24022 FValIsAllZeros = TValIsAllZeros;
24026 if (TValIsAllOnes || FValIsAllZeros) {
24029 if (TValIsAllOnes && FValIsAllZeros)
24031 else if (TValIsAllOnes)
24033 DAG.getNode(ISD::OR, DL, CondVT, Cond, DAG.getBitcast(CondVT, RHS));
24034 else if (FValIsAllZeros)
24035 Ret = DAG.getNode(ISD::AND, DL, CondVT, Cond,
24036 DAG.getBitcast(CondVT, LHS));
24038 return DAG.getBitcast(VT, Ret);
24042 // We should generate an X86ISD::BLENDI from a vselect if its argument
24043 // is a sign_extend_inreg of an any_extend of a BUILD_VECTOR of
24044 // constants. This specific pattern gets generated when we split a
24045 // selector for a 512 bit vector in a machine without AVX512 (but with
24046 // 256-bit vectors), during legalization:
24048 // (vselect (sign_extend (any_extend (BUILD_VECTOR)) i1) LHS RHS)
24050 // Iff we find this pattern and the build_vectors are built from
24051 // constants, we translate the vselect into a shuffle_vector that we
24052 // know will be matched by LowerVECTOR_SHUFFLEtoBlend.
24053 if ((N->getOpcode() == ISD::VSELECT ||
24054 N->getOpcode() == X86ISD::SHRUNKBLEND) &&
24055 !DCI.isBeforeLegalize() && !VT.is512BitVector()) {
24056 SDValue Shuffle = transformVSELECTtoBlendVECTOR_SHUFFLE(N, DAG, Subtarget);
24057 if (Shuffle.getNode())
24061 // If this is a *dynamic* select (non-constant condition) and we can match
24062 // this node with one of the variable blend instructions, restructure the
24063 // condition so that the blends can use the high bit of each element and use
24064 // SimplifyDemandedBits to simplify the condition operand.
24065 if (N->getOpcode() == ISD::VSELECT && DCI.isBeforeLegalizeOps() &&
24066 !DCI.isBeforeLegalize() &&
24067 !ISD::isBuildVectorOfConstantSDNodes(Cond.getNode())) {
24068 unsigned BitWidth = Cond.getValueType().getScalarSizeInBits();
24070 // Don't optimize vector selects that map to mask-registers.
24074 // We can only handle the cases where VSELECT is directly legal on the
24075 // subtarget. We custom lower VSELECT nodes with constant conditions and
24076 // this makes it hard to see whether a dynamic VSELECT will correctly
24077 // lower, so we both check the operation's status and explicitly handle the
24078 // cases where a *dynamic* blend will fail even though a constant-condition
24079 // blend could be custom lowered.
24080 // FIXME: We should find a better way to handle this class of problems.
24081 // Potentially, we should combine constant-condition vselect nodes
24082 // pre-legalization into shuffles and not mark as many types as custom
24084 if (!TLI.isOperationLegalOrCustom(ISD::VSELECT, VT))
24086 // FIXME: We don't support i16-element blends currently. We could and
24087 // should support them by making *all* the bits in the condition be set
24088 // rather than just the high bit and using an i8-element blend.
24089 if (VT.getVectorElementType() == MVT::i16)
24091 // Dynamic blending was only available from SSE4.1 onward.
24092 if (VT.is128BitVector() && !Subtarget->hasSSE41())
24094 // Byte blends are only available in AVX2
24095 if (VT == MVT::v32i8 && !Subtarget->hasAVX2())
24098 assert(BitWidth >= 8 && BitWidth <= 64 && "Invalid mask size");
24099 APInt DemandedMask = APInt::getHighBitsSet(BitWidth, 1);
24101 APInt KnownZero, KnownOne;
24102 TargetLowering::TargetLoweringOpt TLO(DAG, DCI.isBeforeLegalize(),
24103 DCI.isBeforeLegalizeOps());
24104 if (TLO.ShrinkDemandedConstant(Cond, DemandedMask) ||
24105 TLI.SimplifyDemandedBits(Cond, DemandedMask, KnownZero, KnownOne,
24107 // If we changed the computation somewhere in the DAG, this change
24108 // will affect all users of Cond.
24109 // Make sure it is fine and update all the nodes so that we do not
24110 // use the generic VSELECT anymore. Otherwise, we may perform
24111 // wrong optimizations as we messed up with the actual expectation
24112 // for the vector boolean values.
24113 if (Cond != TLO.Old) {
24114 // Check all uses of that condition operand to check whether it will be
24115 // consumed by non-BLEND instructions, which may depend on all bits are
24117 for (SDNode::use_iterator I = Cond->use_begin(), E = Cond->use_end();
24119 if (I->getOpcode() != ISD::VSELECT)
24120 // TODO: Add other opcodes eventually lowered into BLEND.
24123 // Update all the users of the condition, before committing the change,
24124 // so that the VSELECT optimizations that expect the correct vector
24125 // boolean value will not be triggered.
24126 for (SDNode::use_iterator I = Cond->use_begin(), E = Cond->use_end();
24128 DAG.ReplaceAllUsesOfValueWith(
24130 DAG.getNode(X86ISD::SHRUNKBLEND, SDLoc(*I), I->getValueType(0),
24131 Cond, I->getOperand(1), I->getOperand(2)));
24132 DCI.CommitTargetLoweringOpt(TLO);
24135 // At this point, only Cond is changed. Change the condition
24136 // just for N to keep the opportunity to optimize all other
24137 // users their own way.
24138 DAG.ReplaceAllUsesOfValueWith(
24140 DAG.getNode(X86ISD::SHRUNKBLEND, SDLoc(N), N->getValueType(0),
24141 TLO.New, N->getOperand(1), N->getOperand(2)));
24149 // Check whether a boolean test is testing a boolean value generated by
24150 // X86ISD::SETCC. If so, return the operand of that SETCC and proper condition
24153 // Simplify the following patterns:
24154 // (Op (CMP (SETCC Cond EFLAGS) 1) EQ) or
24155 // (Op (CMP (SETCC Cond EFLAGS) 0) NEQ)
24156 // to (Op EFLAGS Cond)
24158 // (Op (CMP (SETCC Cond EFLAGS) 0) EQ) or
24159 // (Op (CMP (SETCC Cond EFLAGS) 1) NEQ)
24160 // to (Op EFLAGS !Cond)
24162 // where Op could be BRCOND or CMOV.
24164 static SDValue checkBoolTestSetCCCombine(SDValue Cmp, X86::CondCode &CC) {
24165 // Quit if not CMP and SUB with its value result used.
24166 if (Cmp.getOpcode() != X86ISD::CMP &&
24167 (Cmp.getOpcode() != X86ISD::SUB || Cmp.getNode()->hasAnyUseOfValue(0)))
24170 // Quit if not used as a boolean value.
24171 if (CC != X86::COND_E && CC != X86::COND_NE)
24174 // Check CMP operands. One of them should be 0 or 1 and the other should be
24175 // an SetCC or extended from it.
24176 SDValue Op1 = Cmp.getOperand(0);
24177 SDValue Op2 = Cmp.getOperand(1);
24180 const ConstantSDNode* C = nullptr;
24181 bool needOppositeCond = (CC == X86::COND_E);
24182 bool checkAgainstTrue = false; // Is it a comparison against 1?
24184 if ((C = dyn_cast<ConstantSDNode>(Op1)))
24186 else if ((C = dyn_cast<ConstantSDNode>(Op2)))
24188 else // Quit if all operands are not constants.
24191 if (C->getZExtValue() == 1) {
24192 needOppositeCond = !needOppositeCond;
24193 checkAgainstTrue = true;
24194 } else if (C->getZExtValue() != 0)
24195 // Quit if the constant is neither 0 or 1.
24198 bool truncatedToBoolWithAnd = false;
24199 // Skip (zext $x), (trunc $x), or (and $x, 1) node.
24200 while (SetCC.getOpcode() == ISD::ZERO_EXTEND ||
24201 SetCC.getOpcode() == ISD::TRUNCATE ||
24202 SetCC.getOpcode() == ISD::AND) {
24203 if (SetCC.getOpcode() == ISD::AND) {
24205 if (isOneConstant(SetCC.getOperand(0)))
24207 if (isOneConstant(SetCC.getOperand(1)))
24211 SetCC = SetCC.getOperand(OpIdx);
24212 truncatedToBoolWithAnd = true;
24214 SetCC = SetCC.getOperand(0);
24217 switch (SetCC.getOpcode()) {
24218 case X86ISD::SETCC_CARRY:
24219 // Since SETCC_CARRY gives output based on R = CF ? ~0 : 0, it's unsafe to
24220 // simplify it if the result of SETCC_CARRY is not canonicalized to 0 or 1,
24221 // i.e. it's a comparison against true but the result of SETCC_CARRY is not
24222 // truncated to i1 using 'and'.
24223 if (checkAgainstTrue && !truncatedToBoolWithAnd)
24225 assert(X86::CondCode(SetCC.getConstantOperandVal(0)) == X86::COND_B &&
24226 "Invalid use of SETCC_CARRY!");
24228 case X86ISD::SETCC:
24229 // Set the condition code or opposite one if necessary.
24230 CC = X86::CondCode(SetCC.getConstantOperandVal(0));
24231 if (needOppositeCond)
24232 CC = X86::GetOppositeBranchCondition(CC);
24233 return SetCC.getOperand(1);
24234 case X86ISD::CMOV: {
24235 // Check whether false/true value has canonical one, i.e. 0 or 1.
24236 ConstantSDNode *FVal = dyn_cast<ConstantSDNode>(SetCC.getOperand(0));
24237 ConstantSDNode *TVal = dyn_cast<ConstantSDNode>(SetCC.getOperand(1));
24238 // Quit if true value is not a constant.
24241 // Quit if false value is not a constant.
24243 SDValue Op = SetCC.getOperand(0);
24244 // Skip 'zext' or 'trunc' node.
24245 if (Op.getOpcode() == ISD::ZERO_EXTEND ||
24246 Op.getOpcode() == ISD::TRUNCATE)
24247 Op = Op.getOperand(0);
24248 // A special case for rdrand/rdseed, where 0 is set if false cond is
24250 if ((Op.getOpcode() != X86ISD::RDRAND &&
24251 Op.getOpcode() != X86ISD::RDSEED) || Op.getResNo() != 0)
24254 // Quit if false value is not the constant 0 or 1.
24255 bool FValIsFalse = true;
24256 if (FVal && FVal->getZExtValue() != 0) {
24257 if (FVal->getZExtValue() != 1)
24259 // If FVal is 1, opposite cond is needed.
24260 needOppositeCond = !needOppositeCond;
24261 FValIsFalse = false;
24263 // Quit if TVal is not the constant opposite of FVal.
24264 if (FValIsFalse && TVal->getZExtValue() != 1)
24266 if (!FValIsFalse && TVal->getZExtValue() != 0)
24268 CC = X86::CondCode(SetCC.getConstantOperandVal(2));
24269 if (needOppositeCond)
24270 CC = X86::GetOppositeBranchCondition(CC);
24271 return SetCC.getOperand(3);
24278 /// Check whether Cond is an AND/OR of SETCCs off of the same EFLAGS.
24280 /// (X86or (X86setcc) (X86setcc))
24281 /// (X86cmp (and (X86setcc) (X86setcc)), 0)
24282 static bool checkBoolTestAndOrSetCCCombine(SDValue Cond, X86::CondCode &CC0,
24283 X86::CondCode &CC1, SDValue &Flags,
24285 if (Cond->getOpcode() == X86ISD::CMP) {
24286 if (!isNullConstant(Cond->getOperand(1)))
24289 Cond = Cond->getOperand(0);
24294 SDValue SetCC0, SetCC1;
24295 switch (Cond->getOpcode()) {
24296 default: return false;
24303 SetCC0 = Cond->getOperand(0);
24304 SetCC1 = Cond->getOperand(1);
24308 // Make sure we have SETCC nodes, using the same flags value.
24309 if (SetCC0.getOpcode() != X86ISD::SETCC ||
24310 SetCC1.getOpcode() != X86ISD::SETCC ||
24311 SetCC0->getOperand(1) != SetCC1->getOperand(1))
24314 CC0 = (X86::CondCode)SetCC0->getConstantOperandVal(0);
24315 CC1 = (X86::CondCode)SetCC1->getConstantOperandVal(0);
24316 Flags = SetCC0->getOperand(1);
24320 /// Optimize X86ISD::CMOV [LHS, RHS, CONDCODE (e.g. X86::COND_NE), CONDVAL]
24321 static SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG,
24322 TargetLowering::DAGCombinerInfo &DCI,
24323 const X86Subtarget *Subtarget) {
24326 // If the flag operand isn't dead, don't touch this CMOV.
24327 if (N->getNumValues() == 2 && !SDValue(N, 1).use_empty())
24330 SDValue FalseOp = N->getOperand(0);
24331 SDValue TrueOp = N->getOperand(1);
24332 X86::CondCode CC = (X86::CondCode)N->getConstantOperandVal(2);
24333 SDValue Cond = N->getOperand(3);
24335 if (CC == X86::COND_E || CC == X86::COND_NE) {
24336 switch (Cond.getOpcode()) {
24340 // If operand of BSR / BSF are proven never zero, then ZF cannot be set.
24341 if (DAG.isKnownNeverZero(Cond.getOperand(0)))
24342 return (CC == X86::COND_E) ? FalseOp : TrueOp;
24348 Flags = checkBoolTestSetCCCombine(Cond, CC);
24349 if (Flags.getNode() &&
24350 // Extra check as FCMOV only supports a subset of X86 cond.
24351 (FalseOp.getValueType() != MVT::f80 || hasFPCMov(CC))) {
24352 SDValue Ops[] = { FalseOp, TrueOp,
24353 DAG.getConstant(CC, DL, MVT::i8), Flags };
24354 return DAG.getNode(X86ISD::CMOV, DL, N->getVTList(), Ops);
24357 // If this is a select between two integer constants, try to do some
24358 // optimizations. Note that the operands are ordered the opposite of SELECT
24360 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(TrueOp)) {
24361 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(FalseOp)) {
24362 // Canonicalize the TrueC/FalseC values so that TrueC (the true value) is
24363 // larger than FalseC (the false value).
24364 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue())) {
24365 CC = X86::GetOppositeBranchCondition(CC);
24366 std::swap(TrueC, FalseC);
24367 std::swap(TrueOp, FalseOp);
24370 // Optimize C ? 8 : 0 -> zext(setcc(C)) << 3. Likewise for any pow2/0.
24371 // This is efficient for any integer data type (including i8/i16) and
24373 if (FalseC->getAPIntValue() == 0 && TrueC->getAPIntValue().isPowerOf2()) {
24374 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
24375 DAG.getConstant(CC, DL, MVT::i8), Cond);
24377 // Zero extend the condition if needed.
24378 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, TrueC->getValueType(0), Cond);
24380 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
24381 Cond = DAG.getNode(ISD::SHL, DL, Cond.getValueType(), Cond,
24382 DAG.getConstant(ShAmt, DL, MVT::i8));
24383 if (N->getNumValues() == 2) // Dead flag value?
24384 return DCI.CombineTo(N, Cond, SDValue());
24388 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst. This is efficient
24389 // for any integer data type, including i8/i16.
24390 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
24391 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
24392 DAG.getConstant(CC, DL, MVT::i8), Cond);
24394 // Zero extend the condition if needed.
24395 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
24396 FalseC->getValueType(0), Cond);
24397 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
24398 SDValue(FalseC, 0));
24400 if (N->getNumValues() == 2) // Dead flag value?
24401 return DCI.CombineTo(N, Cond, SDValue());
24405 // Optimize cases that will turn into an LEA instruction. This requires
24406 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
24407 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
24408 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
24409 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
24411 bool isFastMultiplier = false;
24413 switch ((unsigned char)Diff) {
24415 case 1: // result = add base, cond
24416 case 2: // result = lea base( , cond*2)
24417 case 3: // result = lea base(cond, cond*2)
24418 case 4: // result = lea base( , cond*4)
24419 case 5: // result = lea base(cond, cond*4)
24420 case 8: // result = lea base( , cond*8)
24421 case 9: // result = lea base(cond, cond*8)
24422 isFastMultiplier = true;
24427 if (isFastMultiplier) {
24428 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
24429 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
24430 DAG.getConstant(CC, DL, MVT::i8), Cond);
24431 // Zero extend the condition if needed.
24432 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
24434 // Scale the condition by the difference.
24436 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
24437 DAG.getConstant(Diff, DL, Cond.getValueType()));
24439 // Add the base if non-zero.
24440 if (FalseC->getAPIntValue() != 0)
24441 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
24442 SDValue(FalseC, 0));
24443 if (N->getNumValues() == 2) // Dead flag value?
24444 return DCI.CombineTo(N, Cond, SDValue());
24451 // Handle these cases:
24452 // (select (x != c), e, c) -> select (x != c), e, x),
24453 // (select (x == c), c, e) -> select (x == c), x, e)
24454 // where the c is an integer constant, and the "select" is the combination
24455 // of CMOV and CMP.
24457 // The rationale for this change is that the conditional-move from a constant
24458 // needs two instructions, however, conditional-move from a register needs
24459 // only one instruction.
24461 // CAVEAT: By replacing a constant with a symbolic value, it may obscure
24462 // some instruction-combining opportunities. This opt needs to be
24463 // postponed as late as possible.
24465 if (!DCI.isBeforeLegalize() && !DCI.isBeforeLegalizeOps()) {
24466 // the DCI.xxxx conditions are provided to postpone the optimization as
24467 // late as possible.
24469 ConstantSDNode *CmpAgainst = nullptr;
24470 if ((Cond.getOpcode() == X86ISD::CMP || Cond.getOpcode() == X86ISD::SUB) &&
24471 (CmpAgainst = dyn_cast<ConstantSDNode>(Cond.getOperand(1))) &&
24472 !isa<ConstantSDNode>(Cond.getOperand(0))) {
24474 if (CC == X86::COND_NE &&
24475 CmpAgainst == dyn_cast<ConstantSDNode>(FalseOp)) {
24476 CC = X86::GetOppositeBranchCondition(CC);
24477 std::swap(TrueOp, FalseOp);
24480 if (CC == X86::COND_E &&
24481 CmpAgainst == dyn_cast<ConstantSDNode>(TrueOp)) {
24482 SDValue Ops[] = { FalseOp, Cond.getOperand(0),
24483 DAG.getConstant(CC, DL, MVT::i8), Cond };
24484 return DAG.getNode(X86ISD::CMOV, DL, N->getVTList (), Ops);
24489 // Fold and/or of setcc's to double CMOV:
24490 // (CMOV F, T, ((cc1 | cc2) != 0)) -> (CMOV (CMOV F, T, cc1), T, cc2)
24491 // (CMOV F, T, ((cc1 & cc2) != 0)) -> (CMOV (CMOV T, F, !cc1), F, !cc2)
24493 // This combine lets us generate:
24494 // cmovcc1 (jcc1 if we don't have CMOV)
24500 // cmovne (jne if we don't have CMOV)
24501 // When we can't use the CMOV instruction, it might increase branch
24503 // When we can use CMOV, or when there is no mispredict, this improves
24504 // throughput and reduces register pressure.
24506 if (CC == X86::COND_NE) {
24508 X86::CondCode CC0, CC1;
24510 if (checkBoolTestAndOrSetCCCombine(Cond, CC0, CC1, Flags, isAndSetCC)) {
24512 std::swap(FalseOp, TrueOp);
24513 CC0 = X86::GetOppositeBranchCondition(CC0);
24514 CC1 = X86::GetOppositeBranchCondition(CC1);
24517 SDValue LOps[] = {FalseOp, TrueOp, DAG.getConstant(CC0, DL, MVT::i8),
24519 SDValue LCMOV = DAG.getNode(X86ISD::CMOV, DL, N->getVTList(), LOps);
24520 SDValue Ops[] = {LCMOV, TrueOp, DAG.getConstant(CC1, DL, MVT::i8), Flags};
24521 SDValue CMOV = DAG.getNode(X86ISD::CMOV, DL, N->getVTList(), Ops);
24522 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), SDValue(CMOV.getNode(), 1));
24530 /// PerformMulCombine - Optimize a single multiply with constant into two
24531 /// in order to implement it with two cheaper instructions, e.g.
24532 /// LEA + SHL, LEA + LEA.
24533 static SDValue PerformMulCombine(SDNode *N, SelectionDAG &DAG,
24534 TargetLowering::DAGCombinerInfo &DCI) {
24535 // An imul is usually smaller than the alternative sequence.
24536 if (DAG.getMachineFunction().getFunction()->optForMinSize())
24539 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer())
24542 EVT VT = N->getValueType(0);
24543 if (VT != MVT::i64 && VT != MVT::i32)
24546 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
24549 uint64_t MulAmt = C->getZExtValue();
24550 if (isPowerOf2_64(MulAmt) || MulAmt == 3 || MulAmt == 5 || MulAmt == 9)
24553 uint64_t MulAmt1 = 0;
24554 uint64_t MulAmt2 = 0;
24555 if ((MulAmt % 9) == 0) {
24557 MulAmt2 = MulAmt / 9;
24558 } else if ((MulAmt % 5) == 0) {
24560 MulAmt2 = MulAmt / 5;
24561 } else if ((MulAmt % 3) == 0) {
24563 MulAmt2 = MulAmt / 3;
24566 (isPowerOf2_64(MulAmt2) || MulAmt2 == 3 || MulAmt2 == 5 || MulAmt2 == 9)){
24569 if (isPowerOf2_64(MulAmt2) &&
24570 !(N->hasOneUse() && N->use_begin()->getOpcode() == ISD::ADD))
24571 // If second multiplifer is pow2, issue it first. We want the multiply by
24572 // 3, 5, or 9 to be folded into the addressing mode unless the lone use
24574 std::swap(MulAmt1, MulAmt2);
24577 if (isPowerOf2_64(MulAmt1))
24578 NewMul = DAG.getNode(ISD::SHL, DL, VT, N->getOperand(0),
24579 DAG.getConstant(Log2_64(MulAmt1), DL, MVT::i8));
24581 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, N->getOperand(0),
24582 DAG.getConstant(MulAmt1, DL, VT));
24584 if (isPowerOf2_64(MulAmt2))
24585 NewMul = DAG.getNode(ISD::SHL, DL, VT, NewMul,
24586 DAG.getConstant(Log2_64(MulAmt2), DL, MVT::i8));
24588 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, NewMul,
24589 DAG.getConstant(MulAmt2, DL, VT));
24591 // Do not add new nodes to DAG combiner worklist.
24592 DCI.CombineTo(N, NewMul, false);
24597 static SDValue PerformSHLCombine(SDNode *N, SelectionDAG &DAG) {
24598 SDValue N0 = N->getOperand(0);
24599 SDValue N1 = N->getOperand(1);
24600 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
24601 EVT VT = N0.getValueType();
24603 // fold (shl (and (setcc_c), c1), c2) -> (and setcc_c, (c1 << c2))
24604 // since the result of setcc_c is all zero's or all ones.
24605 if (VT.isInteger() && !VT.isVector() &&
24606 N1C && N0.getOpcode() == ISD::AND &&
24607 N0.getOperand(1).getOpcode() == ISD::Constant) {
24608 SDValue N00 = N0.getOperand(0);
24609 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
24610 APInt ShAmt = N1C->getAPIntValue();
24611 Mask = Mask.shl(ShAmt);
24612 bool MaskOK = false;
24613 // We can handle cases concerning bit-widening nodes containing setcc_c if
24614 // we carefully interrogate the mask to make sure we are semantics
24616 // The transform is not safe if the result of C1 << C2 exceeds the bitwidth
24617 // of the underlying setcc_c operation if the setcc_c was zero extended.
24618 // Consider the following example:
24619 // zext(setcc_c) -> i32 0x0000FFFF
24620 // c1 -> i32 0x0000FFFF
24621 // c2 -> i32 0x00000001
24622 // (shl (and (setcc_c), c1), c2) -> i32 0x0001FFFE
24623 // (and setcc_c, (c1 << c2)) -> i32 0x0000FFFE
24624 if (N00.getOpcode() == X86ISD::SETCC_CARRY) {
24626 } else if (N00.getOpcode() == ISD::SIGN_EXTEND &&
24627 N00.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
24629 } else if ((N00.getOpcode() == ISD::ZERO_EXTEND ||
24630 N00.getOpcode() == ISD::ANY_EXTEND) &&
24631 N00.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
24632 MaskOK = Mask.isIntN(N00.getOperand(0).getValueSizeInBits());
24634 if (MaskOK && Mask != 0) {
24636 return DAG.getNode(ISD::AND, DL, VT, N00, DAG.getConstant(Mask, DL, VT));
24640 // Hardware support for vector shifts is sparse which makes us scalarize the
24641 // vector operations in many cases. Also, on sandybridge ADD is faster than
24643 // (shl V, 1) -> add V,V
24644 if (auto *N1BV = dyn_cast<BuildVectorSDNode>(N1))
24645 if (auto *N1SplatC = N1BV->getConstantSplatNode()) {
24646 assert(N0.getValueType().isVector() && "Invalid vector shift type");
24647 // We shift all of the values by one. In many cases we do not have
24648 // hardware support for this operation. This is better expressed as an ADD
24650 if (N1SplatC->getAPIntValue() == 1)
24651 return DAG.getNode(ISD::ADD, SDLoc(N), VT, N0, N0);
24657 /// \brief Returns a vector of 0s if the node in input is a vector logical
24658 /// shift by a constant amount which is known to be bigger than or equal
24659 /// to the vector element size in bits.
24660 static SDValue performShiftToAllZeros(SDNode *N, SelectionDAG &DAG,
24661 const X86Subtarget *Subtarget) {
24662 EVT VT = N->getValueType(0);
24664 if (VT != MVT::v2i64 && VT != MVT::v4i32 && VT != MVT::v8i16 &&
24665 (!Subtarget->hasInt256() ||
24666 (VT != MVT::v4i64 && VT != MVT::v8i32 && VT != MVT::v16i16)))
24669 SDValue Amt = N->getOperand(1);
24671 if (auto *AmtBV = dyn_cast<BuildVectorSDNode>(Amt))
24672 if (auto *AmtSplat = AmtBV->getConstantSplatNode()) {
24673 APInt ShiftAmt = AmtSplat->getAPIntValue();
24674 unsigned MaxAmount =
24675 VT.getSimpleVT().getVectorElementType().getSizeInBits();
24677 // SSE2/AVX2 logical shifts always return a vector of 0s
24678 // if the shift amount is bigger than or equal to
24679 // the element size. The constant shift amount will be
24680 // encoded as a 8-bit immediate.
24681 if (ShiftAmt.trunc(8).uge(MaxAmount))
24682 return getZeroVector(VT, Subtarget, DAG, DL);
24688 /// PerformShiftCombine - Combine shifts.
24689 static SDValue PerformShiftCombine(SDNode* N, SelectionDAG &DAG,
24690 TargetLowering::DAGCombinerInfo &DCI,
24691 const X86Subtarget *Subtarget) {
24692 if (N->getOpcode() == ISD::SHL)
24693 if (SDValue V = PerformSHLCombine(N, DAG))
24696 // Try to fold this logical shift into a zero vector.
24697 if (N->getOpcode() != ISD::SRA)
24698 if (SDValue V = performShiftToAllZeros(N, DAG, Subtarget))
24704 // CMPEQCombine - Recognize the distinctive (AND (setcc ...) (setcc ..))
24705 // where both setccs reference the same FP CMP, and rewrite for CMPEQSS
24706 // and friends. Likewise for OR -> CMPNEQSS.
24707 static SDValue CMPEQCombine(SDNode *N, SelectionDAG &DAG,
24708 TargetLowering::DAGCombinerInfo &DCI,
24709 const X86Subtarget *Subtarget) {
24712 // SSE1 supports CMP{eq|ne}SS, and SSE2 added CMP{eq|ne}SD, but
24713 // we're requiring SSE2 for both.
24714 if (Subtarget->hasSSE2() && isAndOrOfSetCCs(SDValue(N, 0U), opcode)) {
24715 SDValue N0 = N->getOperand(0);
24716 SDValue N1 = N->getOperand(1);
24717 SDValue CMP0 = N0->getOperand(1);
24718 SDValue CMP1 = N1->getOperand(1);
24721 // The SETCCs should both refer to the same CMP.
24722 if (CMP0.getOpcode() != X86ISD::CMP || CMP0 != CMP1)
24725 SDValue CMP00 = CMP0->getOperand(0);
24726 SDValue CMP01 = CMP0->getOperand(1);
24727 EVT VT = CMP00.getValueType();
24729 if (VT == MVT::f32 || VT == MVT::f64) {
24730 bool ExpectingFlags = false;
24731 // Check for any users that want flags:
24732 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end();
24733 !ExpectingFlags && UI != UE; ++UI)
24734 switch (UI->getOpcode()) {
24739 ExpectingFlags = true;
24741 case ISD::CopyToReg:
24742 case ISD::SIGN_EXTEND:
24743 case ISD::ZERO_EXTEND:
24744 case ISD::ANY_EXTEND:
24748 if (!ExpectingFlags) {
24749 enum X86::CondCode cc0 = (enum X86::CondCode)N0.getConstantOperandVal(0);
24750 enum X86::CondCode cc1 = (enum X86::CondCode)N1.getConstantOperandVal(0);
24752 if (cc1 == X86::COND_E || cc1 == X86::COND_NE) {
24753 X86::CondCode tmp = cc0;
24758 if ((cc0 == X86::COND_E && cc1 == X86::COND_NP) ||
24759 (cc0 == X86::COND_NE && cc1 == X86::COND_P)) {
24760 // FIXME: need symbolic constants for these magic numbers.
24761 // See X86ATTInstPrinter.cpp:printSSECC().
24762 unsigned x86cc = (cc0 == X86::COND_E) ? 0 : 4;
24763 if (Subtarget->hasAVX512()) {
24764 SDValue FSetCC = DAG.getNode(X86ISD::FSETCC, DL, MVT::i1, CMP00,
24766 DAG.getConstant(x86cc, DL, MVT::i8));
24767 if (N->getValueType(0) != MVT::i1)
24768 return DAG.getNode(ISD::ZERO_EXTEND, DL, N->getValueType(0),
24772 SDValue OnesOrZeroesF = DAG.getNode(X86ISD::FSETCC, DL,
24773 CMP00.getValueType(), CMP00, CMP01,
24774 DAG.getConstant(x86cc, DL,
24777 bool is64BitFP = (CMP00.getValueType() == MVT::f64);
24778 MVT IntVT = is64BitFP ? MVT::i64 : MVT::i32;
24780 if (is64BitFP && !Subtarget->is64Bit()) {
24781 // On a 32-bit target, we cannot bitcast the 64-bit float to a
24782 // 64-bit integer, since that's not a legal type. Since
24783 // OnesOrZeroesF is all ones of all zeroes, we don't need all the
24784 // bits, but can do this little dance to extract the lowest 32 bits
24785 // and work with those going forward.
24786 SDValue Vector64 = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, MVT::v2f64,
24788 SDValue Vector32 = DAG.getBitcast(MVT::v4f32, Vector64);
24789 OnesOrZeroesF = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32,
24790 Vector32, DAG.getIntPtrConstant(0, DL));
24794 SDValue OnesOrZeroesI = DAG.getBitcast(IntVT, OnesOrZeroesF);
24795 SDValue ANDed = DAG.getNode(ISD::AND, DL, IntVT, OnesOrZeroesI,
24796 DAG.getConstant(1, DL, IntVT));
24797 SDValue OneBitOfTruth = DAG.getNode(ISD::TRUNCATE, DL, MVT::i8,
24799 return OneBitOfTruth;
24807 /// CanFoldXORWithAllOnes - Test whether the XOR operand is a AllOnes vector
24808 /// so it can be folded inside ANDNP.
24809 static bool CanFoldXORWithAllOnes(const SDNode *N) {
24810 EVT VT = N->getValueType(0);
24812 // Match direct AllOnes for 128 and 256-bit vectors
24813 if (ISD::isBuildVectorAllOnes(N))
24816 // Look through a bit convert.
24817 if (N->getOpcode() == ISD::BITCAST)
24818 N = N->getOperand(0).getNode();
24820 // Sometimes the operand may come from a insert_subvector building a 256-bit
24822 if (VT.is256BitVector() &&
24823 N->getOpcode() == ISD::INSERT_SUBVECTOR) {
24824 SDValue V1 = N->getOperand(0);
24825 SDValue V2 = N->getOperand(1);
24827 if (V1.getOpcode() == ISD::INSERT_SUBVECTOR &&
24828 V1.getOperand(0).getOpcode() == ISD::UNDEF &&
24829 ISD::isBuildVectorAllOnes(V1.getOperand(1).getNode()) &&
24830 ISD::isBuildVectorAllOnes(V2.getNode()))
24837 // On AVX/AVX2 the type v8i1 is legalized to v8i16, which is an XMM sized
24838 // register. In most cases we actually compare or select YMM-sized registers
24839 // and mixing the two types creates horrible code. This method optimizes
24840 // some of the transition sequences.
24841 static SDValue WidenMaskArithmetic(SDNode *N, SelectionDAG &DAG,
24842 TargetLowering::DAGCombinerInfo &DCI,
24843 const X86Subtarget *Subtarget) {
24844 EVT VT = N->getValueType(0);
24845 if (!VT.is256BitVector())
24848 assert((N->getOpcode() == ISD::ANY_EXTEND ||
24849 N->getOpcode() == ISD::ZERO_EXTEND ||
24850 N->getOpcode() == ISD::SIGN_EXTEND) && "Invalid Node");
24852 SDValue Narrow = N->getOperand(0);
24853 EVT NarrowVT = Narrow->getValueType(0);
24854 if (!NarrowVT.is128BitVector())
24857 if (Narrow->getOpcode() != ISD::XOR &&
24858 Narrow->getOpcode() != ISD::AND &&
24859 Narrow->getOpcode() != ISD::OR)
24862 SDValue N0 = Narrow->getOperand(0);
24863 SDValue N1 = Narrow->getOperand(1);
24866 // The Left side has to be a trunc.
24867 if (N0.getOpcode() != ISD::TRUNCATE)
24870 // The type of the truncated inputs.
24871 EVT WideVT = N0->getOperand(0)->getValueType(0);
24875 // The right side has to be a 'trunc' or a constant vector.
24876 bool RHSTrunc = N1.getOpcode() == ISD::TRUNCATE;
24877 ConstantSDNode *RHSConstSplat = nullptr;
24878 if (auto *RHSBV = dyn_cast<BuildVectorSDNode>(N1))
24879 RHSConstSplat = RHSBV->getConstantSplatNode();
24880 if (!RHSTrunc && !RHSConstSplat)
24883 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
24885 if (!TLI.isOperationLegalOrPromote(Narrow->getOpcode(), WideVT))
24888 // Set N0 and N1 to hold the inputs to the new wide operation.
24889 N0 = N0->getOperand(0);
24890 if (RHSConstSplat) {
24891 N1 = DAG.getNode(ISD::ZERO_EXTEND, DL, WideVT.getVectorElementType(),
24892 SDValue(RHSConstSplat, 0));
24893 SmallVector<SDValue, 8> C(WideVT.getVectorNumElements(), N1);
24894 N1 = DAG.getNode(ISD::BUILD_VECTOR, DL, WideVT, C);
24895 } else if (RHSTrunc) {
24896 N1 = N1->getOperand(0);
24899 // Generate the wide operation.
24900 SDValue Op = DAG.getNode(Narrow->getOpcode(), DL, WideVT, N0, N1);
24901 unsigned Opcode = N->getOpcode();
24903 case ISD::ANY_EXTEND:
24905 case ISD::ZERO_EXTEND: {
24906 unsigned InBits = NarrowVT.getScalarSizeInBits();
24907 APInt Mask = APInt::getAllOnesValue(InBits);
24908 Mask = Mask.zext(VT.getScalarSizeInBits());
24909 return DAG.getNode(ISD::AND, DL, VT,
24910 Op, DAG.getConstant(Mask, DL, VT));
24912 case ISD::SIGN_EXTEND:
24913 return DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, VT,
24914 Op, DAG.getValueType(NarrowVT));
24916 llvm_unreachable("Unexpected opcode");
24920 static SDValue VectorZextCombine(SDNode *N, SelectionDAG &DAG,
24921 TargetLowering::DAGCombinerInfo &DCI,
24922 const X86Subtarget *Subtarget) {
24923 SDValue N0 = N->getOperand(0);
24924 SDValue N1 = N->getOperand(1);
24927 // A vector zext_in_reg may be represented as a shuffle,
24928 // feeding into a bitcast (this represents anyext) feeding into
24929 // an and with a mask.
24930 // We'd like to try to combine that into a shuffle with zero
24931 // plus a bitcast, removing the and.
24932 if (N0.getOpcode() != ISD::BITCAST ||
24933 N0.getOperand(0).getOpcode() != ISD::VECTOR_SHUFFLE)
24936 // The other side of the AND should be a splat of 2^C, where C
24937 // is the number of bits in the source type.
24938 if (N1.getOpcode() == ISD::BITCAST)
24939 N1 = N1.getOperand(0);
24940 if (N1.getOpcode() != ISD::BUILD_VECTOR)
24942 BuildVectorSDNode *Vector = cast<BuildVectorSDNode>(N1);
24944 ShuffleVectorSDNode *Shuffle = cast<ShuffleVectorSDNode>(N0.getOperand(0));
24945 EVT SrcType = Shuffle->getValueType(0);
24947 // We expect a single-source shuffle
24948 if (Shuffle->getOperand(1)->getOpcode() != ISD::UNDEF)
24951 unsigned SrcSize = SrcType.getScalarSizeInBits();
24953 APInt SplatValue, SplatUndef;
24954 unsigned SplatBitSize;
24956 if (!Vector->isConstantSplat(SplatValue, SplatUndef,
24957 SplatBitSize, HasAnyUndefs))
24960 unsigned ResSize = N1.getValueType().getScalarSizeInBits();
24961 // Make sure the splat matches the mask we expect
24962 if (SplatBitSize > ResSize ||
24963 (SplatValue + 1).exactLogBase2() != (int)SrcSize)
24966 // Make sure the input and output size make sense
24967 if (SrcSize >= ResSize || ResSize % SrcSize)
24970 // We expect a shuffle of the form <0, u, u, u, 1, u, u, u...>
24971 // The number of u's between each two values depends on the ratio between
24972 // the source and dest type.
24973 unsigned ZextRatio = ResSize / SrcSize;
24974 bool IsZext = true;
24975 for (unsigned i = 0; i < SrcType.getVectorNumElements(); ++i) {
24976 if (i % ZextRatio) {
24977 if (Shuffle->getMaskElt(i) > 0) {
24983 if (Shuffle->getMaskElt(i) != (int)(i / ZextRatio)) {
24984 // Expected element number
24994 // Ok, perform the transformation - replace the shuffle with
24995 // a shuffle of the form <0, k, k, k, 1, k, k, k> with zero
24996 // (instead of undef) where the k elements come from the zero vector.
24997 SmallVector<int, 8> Mask;
24998 unsigned NumElems = SrcType.getVectorNumElements();
24999 for (unsigned i = 0; i < NumElems; ++i)
25001 Mask.push_back(NumElems);
25003 Mask.push_back(i / ZextRatio);
25005 SDValue NewShuffle = DAG.getVectorShuffle(Shuffle->getValueType(0), DL,
25006 Shuffle->getOperand(0), DAG.getConstant(0, DL, SrcType), Mask);
25007 return DAG.getBitcast(N0.getValueType(), NewShuffle);
25010 /// If both input operands of a logic op are being cast from floating point
25011 /// types, try to convert this into a floating point logic node to avoid
25012 /// unnecessary moves from SSE to integer registers.
25013 static SDValue convertIntLogicToFPLogic(SDNode *N, SelectionDAG &DAG,
25014 const X86Subtarget *Subtarget) {
25015 unsigned FPOpcode = ISD::DELETED_NODE;
25016 if (N->getOpcode() == ISD::AND)
25017 FPOpcode = X86ISD::FAND;
25018 else if (N->getOpcode() == ISD::OR)
25019 FPOpcode = X86ISD::FOR;
25020 else if (N->getOpcode() == ISD::XOR)
25021 FPOpcode = X86ISD::FXOR;
25023 assert(FPOpcode != ISD::DELETED_NODE &&
25024 "Unexpected input node for FP logic conversion");
25026 EVT VT = N->getValueType(0);
25027 SDValue N0 = N->getOperand(0);
25028 SDValue N1 = N->getOperand(1);
25030 if (N0.getOpcode() == ISD::BITCAST && N1.getOpcode() == ISD::BITCAST &&
25031 ((Subtarget->hasSSE1() && VT == MVT::i32) ||
25032 (Subtarget->hasSSE2() && VT == MVT::i64))) {
25033 SDValue N00 = N0.getOperand(0);
25034 SDValue N10 = N1.getOperand(0);
25035 EVT N00Type = N00.getValueType();
25036 EVT N10Type = N10.getValueType();
25037 if (N00Type.isFloatingPoint() && N10Type.isFloatingPoint()) {
25038 SDValue FPLogic = DAG.getNode(FPOpcode, DL, N00Type, N00, N10);
25039 return DAG.getBitcast(VT, FPLogic);
25045 static SDValue PerformAndCombine(SDNode *N, SelectionDAG &DAG,
25046 TargetLowering::DAGCombinerInfo &DCI,
25047 const X86Subtarget *Subtarget) {
25048 if (DCI.isBeforeLegalizeOps())
25051 if (SDValue Zext = VectorZextCombine(N, DAG, DCI, Subtarget))
25054 if (SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget))
25057 if (SDValue FPLogic = convertIntLogicToFPLogic(N, DAG, Subtarget))
25060 EVT VT = N->getValueType(0);
25061 SDValue N0 = N->getOperand(0);
25062 SDValue N1 = N->getOperand(1);
25065 // Create BEXTR instructions
25066 // BEXTR is ((X >> imm) & (2**size-1))
25067 if (VT == MVT::i32 || VT == MVT::i64) {
25068 // Check for BEXTR.
25069 if ((Subtarget->hasBMI() || Subtarget->hasTBM()) &&
25070 (N0.getOpcode() == ISD::SRA || N0.getOpcode() == ISD::SRL)) {
25071 ConstantSDNode *MaskNode = dyn_cast<ConstantSDNode>(N1);
25072 ConstantSDNode *ShiftNode = dyn_cast<ConstantSDNode>(N0.getOperand(1));
25073 if (MaskNode && ShiftNode) {
25074 uint64_t Mask = MaskNode->getZExtValue();
25075 uint64_t Shift = ShiftNode->getZExtValue();
25076 if (isMask_64(Mask)) {
25077 uint64_t MaskSize = countPopulation(Mask);
25078 if (Shift + MaskSize <= VT.getSizeInBits())
25079 return DAG.getNode(X86ISD::BEXTR, DL, VT, N0.getOperand(0),
25080 DAG.getConstant(Shift | (MaskSize << 8), DL,
25089 // Want to form ANDNP nodes:
25090 // 1) In the hopes of then easily combining them with OR and AND nodes
25091 // to form PBLEND/PSIGN.
25092 // 2) To match ANDN packed intrinsics
25093 if (VT != MVT::v2i64 && VT != MVT::v4i64)
25096 // Check LHS for vnot
25097 if (N0.getOpcode() == ISD::XOR &&
25098 //ISD::isBuildVectorAllOnes(N0.getOperand(1).getNode()))
25099 CanFoldXORWithAllOnes(N0.getOperand(1).getNode()))
25100 return DAG.getNode(X86ISD::ANDNP, DL, VT, N0.getOperand(0), N1);
25102 // Check RHS for vnot
25103 if (N1.getOpcode() == ISD::XOR &&
25104 //ISD::isBuildVectorAllOnes(N1.getOperand(1).getNode()))
25105 CanFoldXORWithAllOnes(N1.getOperand(1).getNode()))
25106 return DAG.getNode(X86ISD::ANDNP, DL, VT, N1.getOperand(0), N0);
25111 static SDValue PerformOrCombine(SDNode *N, SelectionDAG &DAG,
25112 TargetLowering::DAGCombinerInfo &DCI,
25113 const X86Subtarget *Subtarget) {
25114 if (DCI.isBeforeLegalizeOps())
25117 if (SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget))
25120 if (SDValue FPLogic = convertIntLogicToFPLogic(N, DAG, Subtarget))
25123 SDValue N0 = N->getOperand(0);
25124 SDValue N1 = N->getOperand(1);
25125 EVT VT = N->getValueType(0);
25127 // look for psign/blend
25128 if (VT == MVT::v2i64 || VT == MVT::v4i64) {
25129 if (!Subtarget->hasSSSE3() ||
25130 (VT == MVT::v4i64 && !Subtarget->hasInt256()))
25133 // Canonicalize pandn to RHS
25134 if (N0.getOpcode() == X86ISD::ANDNP)
25136 // or (and (m, y), (pandn m, x))
25137 if (N0.getOpcode() == ISD::AND && N1.getOpcode() == X86ISD::ANDNP) {
25138 SDValue Mask = N1.getOperand(0);
25139 SDValue X = N1.getOperand(1);
25141 if (N0.getOperand(0) == Mask)
25142 Y = N0.getOperand(1);
25143 if (N0.getOperand(1) == Mask)
25144 Y = N0.getOperand(0);
25146 // Check to see if the mask appeared in both the AND and ANDNP and
25150 // Validate that X, Y, and Mask are BIT_CONVERTS, and see through them.
25151 // Look through mask bitcast.
25152 if (Mask.getOpcode() == ISD::BITCAST)
25153 Mask = Mask.getOperand(0);
25154 if (X.getOpcode() == ISD::BITCAST)
25155 X = X.getOperand(0);
25156 if (Y.getOpcode() == ISD::BITCAST)
25157 Y = Y.getOperand(0);
25159 EVT MaskVT = Mask.getValueType();
25161 // Validate that the Mask operand is a vector sra node.
25162 // FIXME: what to do for bytes, since there is a psignb/pblendvb, but
25163 // there is no psrai.b
25164 unsigned EltBits = MaskVT.getVectorElementType().getSizeInBits();
25165 unsigned SraAmt = ~0;
25166 if (Mask.getOpcode() == ISD::SRA) {
25167 if (auto *AmtBV = dyn_cast<BuildVectorSDNode>(Mask.getOperand(1)))
25168 if (auto *AmtConst = AmtBV->getConstantSplatNode())
25169 SraAmt = AmtConst->getZExtValue();
25170 } else if (Mask.getOpcode() == X86ISD::VSRAI) {
25171 SDValue SraC = Mask.getOperand(1);
25172 SraAmt = cast<ConstantSDNode>(SraC)->getZExtValue();
25174 if ((SraAmt + 1) != EltBits)
25179 // Now we know we at least have a plendvb with the mask val. See if
25180 // we can form a psignb/w/d.
25181 // psign = x.type == y.type == mask.type && y = sub(0, x);
25182 if (Y.getOpcode() == ISD::SUB && Y.getOperand(1) == X &&
25183 ISD::isBuildVectorAllZeros(Y.getOperand(0).getNode()) &&
25184 X.getValueType() == MaskVT && Y.getValueType() == MaskVT) {
25185 assert((EltBits == 8 || EltBits == 16 || EltBits == 32) &&
25186 "Unsupported VT for PSIGN");
25187 Mask = DAG.getNode(X86ISD::PSIGN, DL, MaskVT, X, Mask.getOperand(0));
25188 return DAG.getBitcast(VT, Mask);
25190 // PBLENDVB only available on SSE 4.1
25191 if (!Subtarget->hasSSE41())
25194 MVT BlendVT = (VT == MVT::v4i64) ? MVT::v32i8 : MVT::v16i8;
25196 X = DAG.getBitcast(BlendVT, X);
25197 Y = DAG.getBitcast(BlendVT, Y);
25198 Mask = DAG.getBitcast(BlendVT, Mask);
25199 Mask = DAG.getNode(ISD::VSELECT, DL, BlendVT, Mask, Y, X);
25200 return DAG.getBitcast(VT, Mask);
25204 if (VT != MVT::i16 && VT != MVT::i32 && VT != MVT::i64)
25207 // fold (or (x << c) | (y >> (64 - c))) ==> (shld64 x, y, c)
25208 bool OptForSize = DAG.getMachineFunction().getFunction()->optForSize();
25210 // SHLD/SHRD instructions have lower register pressure, but on some
25211 // platforms they have higher latency than the equivalent
25212 // series of shifts/or that would otherwise be generated.
25213 // Don't fold (or (x << c) | (y >> (64 - c))) if SHLD/SHRD instructions
25214 // have higher latencies and we are not optimizing for size.
25215 if (!OptForSize && Subtarget->isSHLDSlow())
25218 if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL)
25220 if (N0.getOpcode() != ISD::SHL || N1.getOpcode() != ISD::SRL)
25222 if (!N0.hasOneUse() || !N1.hasOneUse())
25225 SDValue ShAmt0 = N0.getOperand(1);
25226 if (ShAmt0.getValueType() != MVT::i8)
25228 SDValue ShAmt1 = N1.getOperand(1);
25229 if (ShAmt1.getValueType() != MVT::i8)
25231 if (ShAmt0.getOpcode() == ISD::TRUNCATE)
25232 ShAmt0 = ShAmt0.getOperand(0);
25233 if (ShAmt1.getOpcode() == ISD::TRUNCATE)
25234 ShAmt1 = ShAmt1.getOperand(0);
25237 unsigned Opc = X86ISD::SHLD;
25238 SDValue Op0 = N0.getOperand(0);
25239 SDValue Op1 = N1.getOperand(0);
25240 if (ShAmt0.getOpcode() == ISD::SUB) {
25241 Opc = X86ISD::SHRD;
25242 std::swap(Op0, Op1);
25243 std::swap(ShAmt0, ShAmt1);
25246 unsigned Bits = VT.getSizeInBits();
25247 if (ShAmt1.getOpcode() == ISD::SUB) {
25248 SDValue Sum = ShAmt1.getOperand(0);
25249 if (ConstantSDNode *SumC = dyn_cast<ConstantSDNode>(Sum)) {
25250 SDValue ShAmt1Op1 = ShAmt1.getOperand(1);
25251 if (ShAmt1Op1.getNode()->getOpcode() == ISD::TRUNCATE)
25252 ShAmt1Op1 = ShAmt1Op1.getOperand(0);
25253 if (SumC->getSExtValue() == Bits && ShAmt1Op1 == ShAmt0)
25254 return DAG.getNode(Opc, DL, VT,
25256 DAG.getNode(ISD::TRUNCATE, DL,
25259 } else if (ConstantSDNode *ShAmt1C = dyn_cast<ConstantSDNode>(ShAmt1)) {
25260 ConstantSDNode *ShAmt0C = dyn_cast<ConstantSDNode>(ShAmt0);
25262 ShAmt0C->getSExtValue() + ShAmt1C->getSExtValue() == Bits)
25263 return DAG.getNode(Opc, DL, VT,
25264 N0.getOperand(0), N1.getOperand(0),
25265 DAG.getNode(ISD::TRUNCATE, DL,
25272 // Generate NEG and CMOV for integer abs.
25273 static SDValue performIntegerAbsCombine(SDNode *N, SelectionDAG &DAG) {
25274 EVT VT = N->getValueType(0);
25276 // Since X86 does not have CMOV for 8-bit integer, we don't convert
25277 // 8-bit integer abs to NEG and CMOV.
25278 if (VT.isInteger() && VT.getSizeInBits() == 8)
25281 SDValue N0 = N->getOperand(0);
25282 SDValue N1 = N->getOperand(1);
25285 // Check pattern of XOR(ADD(X,Y), Y) where Y is SRA(X, size(X)-1)
25286 // and change it to SUB and CMOV.
25287 if (VT.isInteger() && N->getOpcode() == ISD::XOR &&
25288 N0.getOpcode() == ISD::ADD &&
25289 N0.getOperand(1) == N1 &&
25290 N1.getOpcode() == ISD::SRA &&
25291 N1.getOperand(0) == N0.getOperand(0))
25292 if (ConstantSDNode *Y1C = dyn_cast<ConstantSDNode>(N1.getOperand(1)))
25293 if (Y1C->getAPIntValue() == VT.getSizeInBits()-1) {
25294 // Generate SUB & CMOV.
25295 SDValue Neg = DAG.getNode(X86ISD::SUB, DL, DAG.getVTList(VT, MVT::i32),
25296 DAG.getConstant(0, DL, VT), N0.getOperand(0));
25298 SDValue Ops[] = { N0.getOperand(0), Neg,
25299 DAG.getConstant(X86::COND_GE, DL, MVT::i8),
25300 SDValue(Neg.getNode(), 1) };
25301 return DAG.getNode(X86ISD::CMOV, DL, DAG.getVTList(VT, MVT::Glue), Ops);
25306 // Try to turn tests against the signbit in the form of:
25307 // XOR(TRUNCATE(SRL(X, size(X)-1)), 1)
25310 static SDValue foldXorTruncShiftIntoCmp(SDNode *N, SelectionDAG &DAG) {
25311 // This is only worth doing if the output type is i8.
25312 if (N->getValueType(0) != MVT::i8)
25315 SDValue N0 = N->getOperand(0);
25316 SDValue N1 = N->getOperand(1);
25318 // We should be performing an xor against a truncated shift.
25319 if (N0.getOpcode() != ISD::TRUNCATE || !N0.hasOneUse())
25322 // Make sure we are performing an xor against one.
25323 if (!isOneConstant(N1))
25326 // SetCC on x86 zero extends so only act on this if it's a logical shift.
25327 SDValue Shift = N0.getOperand(0);
25328 if (Shift.getOpcode() != ISD::SRL || !Shift.hasOneUse())
25331 // Make sure we are truncating from one of i16, i32 or i64.
25332 EVT ShiftTy = Shift.getValueType();
25333 if (ShiftTy != MVT::i16 && ShiftTy != MVT::i32 && ShiftTy != MVT::i64)
25336 // Make sure the shift amount extracts the sign bit.
25337 if (!isa<ConstantSDNode>(Shift.getOperand(1)) ||
25338 Shift.getConstantOperandVal(1) != ShiftTy.getSizeInBits() - 1)
25341 // Create a greater-than comparison against -1.
25342 // N.B. Using SETGE against 0 works but we want a canonical looking
25343 // comparison, using SETGT matches up with what TranslateX86CC.
25345 SDValue ShiftOp = Shift.getOperand(0);
25346 EVT ShiftOpTy = ShiftOp.getValueType();
25347 SDValue Cond = DAG.getSetCC(DL, MVT::i8, ShiftOp,
25348 DAG.getConstant(-1, DL, ShiftOpTy), ISD::SETGT);
25352 static SDValue PerformXorCombine(SDNode *N, SelectionDAG &DAG,
25353 TargetLowering::DAGCombinerInfo &DCI,
25354 const X86Subtarget *Subtarget) {
25355 if (DCI.isBeforeLegalizeOps())
25358 if (SDValue RV = foldXorTruncShiftIntoCmp(N, DAG))
25361 if (Subtarget->hasCMov())
25362 if (SDValue RV = performIntegerAbsCombine(N, DAG))
25365 if (SDValue FPLogic = convertIntLogicToFPLogic(N, DAG, Subtarget))
25371 /// This function detects the AVG pattern between vectors of unsigned i8/i16,
25372 /// which is c = (a + b + 1) / 2, and replace this operation with the efficient
25373 /// X86ISD::AVG instruction.
25374 static SDValue detectAVGPattern(SDValue In, EVT VT, SelectionDAG &DAG,
25375 const X86Subtarget *Subtarget, SDLoc DL) {
25376 if (!VT.isVector() || !VT.isSimple())
25378 EVT InVT = In.getValueType();
25379 unsigned NumElems = VT.getVectorNumElements();
25381 EVT ScalarVT = VT.getVectorElementType();
25382 if (!((ScalarVT == MVT::i8 || ScalarVT == MVT::i16) &&
25383 isPowerOf2_32(NumElems)))
25386 // InScalarVT is the intermediate type in AVG pattern and it should be greater
25387 // than the original input type (i8/i16).
25388 EVT InScalarVT = InVT.getVectorElementType();
25389 if (InScalarVT.getSizeInBits() <= ScalarVT.getSizeInBits())
25392 if (Subtarget->hasAVX512()) {
25393 if (VT.getSizeInBits() > 512)
25395 } else if (Subtarget->hasAVX2()) {
25396 if (VT.getSizeInBits() > 256)
25399 if (VT.getSizeInBits() > 128)
25403 // Detect the following pattern:
25405 // %1 = zext <N x i8> %a to <N x i32>
25406 // %2 = zext <N x i8> %b to <N x i32>
25407 // %3 = add nuw nsw <N x i32> %1, <i32 1 x N>
25408 // %4 = add nuw nsw <N x i32> %3, %2
25409 // %5 = lshr <N x i32> %N, <i32 1 x N>
25410 // %6 = trunc <N x i32> %5 to <N x i8>
25412 // In AVX512, the last instruction can also be a trunc store.
25414 if (In.getOpcode() != ISD::SRL)
25417 // A lambda checking the given SDValue is a constant vector and each element
25418 // is in the range [Min, Max].
25419 auto IsConstVectorInRange = [](SDValue V, unsigned Min, unsigned Max) {
25420 BuildVectorSDNode *BV = dyn_cast<BuildVectorSDNode>(V);
25421 if (!BV || !BV->isConstant())
25423 for (unsigned i = 0, e = V.getNumOperands(); i < e; i++) {
25424 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V.getOperand(i));
25427 uint64_t Val = C->getZExtValue();
25428 if (Val < Min || Val > Max)
25434 // Check if each element of the vector is left-shifted by one.
25435 auto LHS = In.getOperand(0);
25436 auto RHS = In.getOperand(1);
25437 if (!IsConstVectorInRange(RHS, 1, 1))
25439 if (LHS.getOpcode() != ISD::ADD)
25442 // Detect a pattern of a + b + 1 where the order doesn't matter.
25443 SDValue Operands[3];
25444 Operands[0] = LHS.getOperand(0);
25445 Operands[1] = LHS.getOperand(1);
25447 // Take care of the case when one of the operands is a constant vector whose
25448 // element is in the range [1, 256].
25449 if (IsConstVectorInRange(Operands[1], 1, ScalarVT == MVT::i8 ? 256 : 65536) &&
25450 Operands[0].getOpcode() == ISD::ZERO_EXTEND &&
25451 Operands[0].getOperand(0).getValueType() == VT) {
25452 // The pattern is detected. Subtract one from the constant vector, then
25453 // demote it and emit X86ISD::AVG instruction.
25454 SDValue One = DAG.getConstant(1, DL, InScalarVT);
25455 SDValue Ones = DAG.getNode(ISD::BUILD_VECTOR, DL, InVT,
25456 SmallVector<SDValue, 8>(NumElems, One));
25457 Operands[1] = DAG.getNode(ISD::SUB, DL, InVT, Operands[1], Ones);
25458 Operands[1] = DAG.getNode(ISD::TRUNCATE, DL, VT, Operands[1]);
25459 return DAG.getNode(X86ISD::AVG, DL, VT, Operands[0].getOperand(0),
25463 if (Operands[0].getOpcode() == ISD::ADD)
25464 std::swap(Operands[0], Operands[1]);
25465 else if (Operands[1].getOpcode() != ISD::ADD)
25467 Operands[2] = Operands[1].getOperand(0);
25468 Operands[1] = Operands[1].getOperand(1);
25470 // Now we have three operands of two additions. Check that one of them is a
25471 // constant vector with ones, and the other two are promoted from i8/i16.
25472 for (int i = 0; i < 3; ++i) {
25473 if (!IsConstVectorInRange(Operands[i], 1, 1))
25475 std::swap(Operands[i], Operands[2]);
25477 // Check if Operands[0] and Operands[1] are results of type promotion.
25478 for (int j = 0; j < 2; ++j)
25479 if (Operands[j].getOpcode() != ISD::ZERO_EXTEND ||
25480 Operands[j].getOperand(0).getValueType() != VT)
25483 // The pattern is detected, emit X86ISD::AVG instruction.
25484 return DAG.getNode(X86ISD::AVG, DL, VT, Operands[0].getOperand(0),
25485 Operands[1].getOperand(0));
25491 static SDValue PerformTRUNCATECombine(SDNode *N, SelectionDAG &DAG,
25492 const X86Subtarget *Subtarget) {
25493 return detectAVGPattern(N->getOperand(0), N->getValueType(0), DAG, Subtarget,
25497 /// PerformLOADCombine - Do target-specific dag combines on LOAD nodes.
25498 static SDValue PerformLOADCombine(SDNode *N, SelectionDAG &DAG,
25499 TargetLowering::DAGCombinerInfo &DCI,
25500 const X86Subtarget *Subtarget) {
25501 LoadSDNode *Ld = cast<LoadSDNode>(N);
25502 EVT RegVT = Ld->getValueType(0);
25503 EVT MemVT = Ld->getMemoryVT();
25505 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
25507 // For chips with slow 32-byte unaligned loads, break the 32-byte operation
25508 // into two 16-byte operations.
25509 ISD::LoadExtType Ext = Ld->getExtensionType();
25511 unsigned AddressSpace = Ld->getAddressSpace();
25512 unsigned Alignment = Ld->getAlignment();
25513 if (RegVT.is256BitVector() && !DCI.isBeforeLegalizeOps() &&
25514 Ext == ISD::NON_EXTLOAD &&
25515 TLI.allowsMemoryAccess(*DAG.getContext(), DAG.getDataLayout(), RegVT,
25516 AddressSpace, Alignment, &Fast) && !Fast) {
25517 unsigned NumElems = RegVT.getVectorNumElements();
25521 SDValue Ptr = Ld->getBasePtr();
25522 SDValue Increment =
25523 DAG.getConstant(16, dl, TLI.getPointerTy(DAG.getDataLayout()));
25525 EVT HalfVT = EVT::getVectorVT(*DAG.getContext(), MemVT.getScalarType(),
25527 SDValue Load1 = DAG.getLoad(HalfVT, dl, Ld->getChain(), Ptr,
25528 Ld->getPointerInfo(), Ld->isVolatile(),
25529 Ld->isNonTemporal(), Ld->isInvariant(),
25531 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
25532 SDValue Load2 = DAG.getLoad(HalfVT, dl, Ld->getChain(), Ptr,
25533 Ld->getPointerInfo(), Ld->isVolatile(),
25534 Ld->isNonTemporal(), Ld->isInvariant(),
25535 std::min(16U, Alignment));
25536 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
25538 Load2.getValue(1));
25540 SDValue NewVec = DAG.getUNDEF(RegVT);
25541 NewVec = Insert128BitVector(NewVec, Load1, 0, DAG, dl);
25542 NewVec = Insert128BitVector(NewVec, Load2, NumElems/2, DAG, dl);
25543 return DCI.CombineTo(N, NewVec, TF, true);
25549 /// PerformMLOADCombine - Resolve extending loads
25550 static SDValue PerformMLOADCombine(SDNode *N, SelectionDAG &DAG,
25551 TargetLowering::DAGCombinerInfo &DCI,
25552 const X86Subtarget *Subtarget) {
25553 MaskedLoadSDNode *Mld = cast<MaskedLoadSDNode>(N);
25554 if (Mld->getExtensionType() != ISD::SEXTLOAD)
25557 EVT VT = Mld->getValueType(0);
25558 unsigned NumElems = VT.getVectorNumElements();
25559 EVT LdVT = Mld->getMemoryVT();
25562 assert(LdVT != VT && "Cannot extend to the same type");
25563 unsigned ToSz = VT.getVectorElementType().getSizeInBits();
25564 unsigned FromSz = LdVT.getVectorElementType().getSizeInBits();
25565 // From, To sizes and ElemCount must be pow of two
25566 assert (isPowerOf2_32(NumElems * FromSz * ToSz) &&
25567 "Unexpected size for extending masked load");
25569 unsigned SizeRatio = ToSz / FromSz;
25570 assert(SizeRatio * NumElems * FromSz == VT.getSizeInBits());
25572 // Create a type on which we perform the shuffle
25573 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(),
25574 LdVT.getScalarType(), NumElems*SizeRatio);
25575 assert(WideVecVT.getSizeInBits() == VT.getSizeInBits());
25577 // Convert Src0 value
25578 SDValue WideSrc0 = DAG.getBitcast(WideVecVT, Mld->getSrc0());
25579 if (Mld->getSrc0().getOpcode() != ISD::UNDEF) {
25580 SmallVector<int, 16> ShuffleVec(NumElems * SizeRatio, -1);
25581 for (unsigned i = 0; i != NumElems; ++i)
25582 ShuffleVec[i] = i * SizeRatio;
25584 // Can't shuffle using an illegal type.
25585 assert(DAG.getTargetLoweringInfo().isTypeLegal(WideVecVT) &&
25586 "WideVecVT should be legal");
25587 WideSrc0 = DAG.getVectorShuffle(WideVecVT, dl, WideSrc0,
25588 DAG.getUNDEF(WideVecVT), &ShuffleVec[0]);
25590 // Prepare the new mask
25592 SDValue Mask = Mld->getMask();
25593 if (Mask.getValueType() == VT) {
25594 // Mask and original value have the same type
25595 NewMask = DAG.getBitcast(WideVecVT, Mask);
25596 SmallVector<int, 16> ShuffleVec(NumElems * SizeRatio, -1);
25597 for (unsigned i = 0; i != NumElems; ++i)
25598 ShuffleVec[i] = i * SizeRatio;
25599 for (unsigned i = NumElems; i != NumElems*SizeRatio; ++i)
25600 ShuffleVec[i] = NumElems*SizeRatio;
25601 NewMask = DAG.getVectorShuffle(WideVecVT, dl, NewMask,
25602 DAG.getConstant(0, dl, WideVecVT),
25606 assert(Mask.getValueType().getVectorElementType() == MVT::i1);
25607 unsigned WidenNumElts = NumElems*SizeRatio;
25608 unsigned MaskNumElts = VT.getVectorNumElements();
25609 EVT NewMaskVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
25612 unsigned NumConcat = WidenNumElts / MaskNumElts;
25613 SmallVector<SDValue, 16> Ops(NumConcat);
25614 SDValue ZeroVal = DAG.getConstant(0, dl, Mask.getValueType());
25616 for (unsigned i = 1; i != NumConcat; ++i)
25619 NewMask = DAG.getNode(ISD::CONCAT_VECTORS, dl, NewMaskVT, Ops);
25622 SDValue WideLd = DAG.getMaskedLoad(WideVecVT, dl, Mld->getChain(),
25623 Mld->getBasePtr(), NewMask, WideSrc0,
25624 Mld->getMemoryVT(), Mld->getMemOperand(),
25626 SDValue NewVec = DAG.getNode(X86ISD::VSEXT, dl, VT, WideLd);
25627 return DCI.CombineTo(N, NewVec, WideLd.getValue(1), true);
25629 /// PerformMSTORECombine - Resolve truncating stores
25630 static SDValue PerformMSTORECombine(SDNode *N, SelectionDAG &DAG,
25631 const X86Subtarget *Subtarget) {
25632 MaskedStoreSDNode *Mst = cast<MaskedStoreSDNode>(N);
25633 if (!Mst->isTruncatingStore())
25636 EVT VT = Mst->getValue().getValueType();
25637 unsigned NumElems = VT.getVectorNumElements();
25638 EVT StVT = Mst->getMemoryVT();
25641 assert(StVT != VT && "Cannot truncate to the same type");
25642 unsigned FromSz = VT.getVectorElementType().getSizeInBits();
25643 unsigned ToSz = StVT.getVectorElementType().getSizeInBits();
25645 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
25647 // The truncating store is legal in some cases. For example
25648 // vpmovqb, vpmovqw, vpmovqd, vpmovdb, vpmovdw
25649 // are designated for truncate store.
25650 // In this case we don't need any further transformations.
25651 if (TLI.isTruncStoreLegal(VT, StVT))
25654 // From, To sizes and ElemCount must be pow of two
25655 assert (isPowerOf2_32(NumElems * FromSz * ToSz) &&
25656 "Unexpected size for truncating masked store");
25657 // We are going to use the original vector elt for storing.
25658 // Accumulated smaller vector elements must be a multiple of the store size.
25659 assert (((NumElems * FromSz) % ToSz) == 0 &&
25660 "Unexpected ratio for truncating masked store");
25662 unsigned SizeRatio = FromSz / ToSz;
25663 assert(SizeRatio * NumElems * ToSz == VT.getSizeInBits());
25665 // Create a type on which we perform the shuffle
25666 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(),
25667 StVT.getScalarType(), NumElems*SizeRatio);
25669 assert(WideVecVT.getSizeInBits() == VT.getSizeInBits());
25671 SDValue WideVec = DAG.getBitcast(WideVecVT, Mst->getValue());
25672 SmallVector<int, 16> ShuffleVec(NumElems * SizeRatio, -1);
25673 for (unsigned i = 0; i != NumElems; ++i)
25674 ShuffleVec[i] = i * SizeRatio;
25676 // Can't shuffle using an illegal type.
25677 assert(DAG.getTargetLoweringInfo().isTypeLegal(WideVecVT) &&
25678 "WideVecVT should be legal");
25680 SDValue TruncatedVal = DAG.getVectorShuffle(WideVecVT, dl, WideVec,
25681 DAG.getUNDEF(WideVecVT),
25685 SDValue Mask = Mst->getMask();
25686 if (Mask.getValueType() == VT) {
25687 // Mask and original value have the same type
25688 NewMask = DAG.getBitcast(WideVecVT, Mask);
25689 for (unsigned i = 0; i != NumElems; ++i)
25690 ShuffleVec[i] = i * SizeRatio;
25691 for (unsigned i = NumElems; i != NumElems*SizeRatio; ++i)
25692 ShuffleVec[i] = NumElems*SizeRatio;
25693 NewMask = DAG.getVectorShuffle(WideVecVT, dl, NewMask,
25694 DAG.getConstant(0, dl, WideVecVT),
25698 assert(Mask.getValueType().getVectorElementType() == MVT::i1);
25699 unsigned WidenNumElts = NumElems*SizeRatio;
25700 unsigned MaskNumElts = VT.getVectorNumElements();
25701 EVT NewMaskVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
25704 unsigned NumConcat = WidenNumElts / MaskNumElts;
25705 SmallVector<SDValue, 16> Ops(NumConcat);
25706 SDValue ZeroVal = DAG.getConstant(0, dl, Mask.getValueType());
25708 for (unsigned i = 1; i != NumConcat; ++i)
25711 NewMask = DAG.getNode(ISD::CONCAT_VECTORS, dl, NewMaskVT, Ops);
25714 return DAG.getMaskedStore(Mst->getChain(), dl, TruncatedVal, Mst->getBasePtr(),
25715 NewMask, StVT, Mst->getMemOperand(), false);
25717 /// PerformSTORECombine - Do target-specific dag combines on STORE nodes.
25718 static SDValue PerformSTORECombine(SDNode *N, SelectionDAG &DAG,
25719 const X86Subtarget *Subtarget) {
25720 StoreSDNode *St = cast<StoreSDNode>(N);
25721 EVT VT = St->getValue().getValueType();
25722 EVT StVT = St->getMemoryVT();
25724 SDValue StoredVal = St->getOperand(1);
25725 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
25727 // If we are saving a concatenation of two XMM registers and 32-byte stores
25728 // are slow, such as on Sandy Bridge, perform two 16-byte stores.
25730 unsigned AddressSpace = St->getAddressSpace();
25731 unsigned Alignment = St->getAlignment();
25732 if (VT.is256BitVector() && StVT == VT &&
25733 TLI.allowsMemoryAccess(*DAG.getContext(), DAG.getDataLayout(), VT,
25734 AddressSpace, Alignment, &Fast) && !Fast) {
25735 unsigned NumElems = VT.getVectorNumElements();
25739 SDValue Value0 = Extract128BitVector(StoredVal, 0, DAG, dl);
25740 SDValue Value1 = Extract128BitVector(StoredVal, NumElems/2, DAG, dl);
25743 DAG.getConstant(16, dl, TLI.getPointerTy(DAG.getDataLayout()));
25744 SDValue Ptr0 = St->getBasePtr();
25745 SDValue Ptr1 = DAG.getNode(ISD::ADD, dl, Ptr0.getValueType(), Ptr0, Stride);
25747 SDValue Ch0 = DAG.getStore(St->getChain(), dl, Value0, Ptr0,
25748 St->getPointerInfo(), St->isVolatile(),
25749 St->isNonTemporal(), Alignment);
25750 SDValue Ch1 = DAG.getStore(St->getChain(), dl, Value1, Ptr1,
25751 St->getPointerInfo(), St->isVolatile(),
25752 St->isNonTemporal(),
25753 std::min(16U, Alignment));
25754 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Ch0, Ch1);
25757 // Optimize trunc store (of multiple scalars) to shuffle and store.
25758 // First, pack all of the elements in one place. Next, store to memory
25759 // in fewer chunks.
25760 if (St->isTruncatingStore() && VT.isVector()) {
25761 // Check if we can detect an AVG pattern from the truncation. If yes,
25762 // replace the trunc store by a normal store with the result of X86ISD::AVG
25765 detectAVGPattern(St->getValue(), St->getMemoryVT(), DAG, Subtarget, dl);
25767 return DAG.getStore(St->getChain(), dl, Avg, St->getBasePtr(),
25768 St->getPointerInfo(), St->isVolatile(),
25769 St->isNonTemporal(), St->getAlignment());
25771 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
25772 unsigned NumElems = VT.getVectorNumElements();
25773 assert(StVT != VT && "Cannot truncate to the same type");
25774 unsigned FromSz = VT.getVectorElementType().getSizeInBits();
25775 unsigned ToSz = StVT.getVectorElementType().getSizeInBits();
25777 // The truncating store is legal in some cases. For example
25778 // vpmovqb, vpmovqw, vpmovqd, vpmovdb, vpmovdw
25779 // are designated for truncate store.
25780 // In this case we don't need any further transformations.
25781 if (TLI.isTruncStoreLegal(VT, StVT))
25784 // From, To sizes and ElemCount must be pow of two
25785 if (!isPowerOf2_32(NumElems * FromSz * ToSz)) return SDValue();
25786 // We are going to use the original vector elt for storing.
25787 // Accumulated smaller vector elements must be a multiple of the store size.
25788 if (0 != (NumElems * FromSz) % ToSz) return SDValue();
25790 unsigned SizeRatio = FromSz / ToSz;
25792 assert(SizeRatio * NumElems * ToSz == VT.getSizeInBits());
25794 // Create a type on which we perform the shuffle
25795 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(),
25796 StVT.getScalarType(), NumElems*SizeRatio);
25798 assert(WideVecVT.getSizeInBits() == VT.getSizeInBits());
25800 SDValue WideVec = DAG.getBitcast(WideVecVT, St->getValue());
25801 SmallVector<int, 8> ShuffleVec(NumElems * SizeRatio, -1);
25802 for (unsigned i = 0; i != NumElems; ++i)
25803 ShuffleVec[i] = i * SizeRatio;
25805 // Can't shuffle using an illegal type.
25806 if (!TLI.isTypeLegal(WideVecVT))
25809 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, WideVec,
25810 DAG.getUNDEF(WideVecVT),
25812 // At this point all of the data is stored at the bottom of the
25813 // register. We now need to save it to mem.
25815 // Find the largest store unit
25816 MVT StoreType = MVT::i8;
25817 for (MVT Tp : MVT::integer_valuetypes()) {
25818 if (TLI.isTypeLegal(Tp) && Tp.getSizeInBits() <= NumElems * ToSz)
25822 // On 32bit systems, we can't save 64bit integers. Try bitcasting to F64.
25823 if (TLI.isTypeLegal(MVT::f64) && StoreType.getSizeInBits() < 64 &&
25824 (64 <= NumElems * ToSz))
25825 StoreType = MVT::f64;
25827 // Bitcast the original vector into a vector of store-size units
25828 EVT StoreVecVT = EVT::getVectorVT(*DAG.getContext(),
25829 StoreType, VT.getSizeInBits()/StoreType.getSizeInBits());
25830 assert(StoreVecVT.getSizeInBits() == VT.getSizeInBits());
25831 SDValue ShuffWide = DAG.getBitcast(StoreVecVT, Shuff);
25832 SmallVector<SDValue, 8> Chains;
25833 SDValue Increment = DAG.getConstant(StoreType.getSizeInBits() / 8, dl,
25834 TLI.getPointerTy(DAG.getDataLayout()));
25835 SDValue Ptr = St->getBasePtr();
25837 // Perform one or more big stores into memory.
25838 for (unsigned i=0, e=(ToSz*NumElems)/StoreType.getSizeInBits(); i!=e; ++i) {
25839 SDValue SubVec = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
25840 StoreType, ShuffWide,
25841 DAG.getIntPtrConstant(i, dl));
25842 SDValue Ch = DAG.getStore(St->getChain(), dl, SubVec, Ptr,
25843 St->getPointerInfo(), St->isVolatile(),
25844 St->isNonTemporal(), St->getAlignment());
25845 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
25846 Chains.push_back(Ch);
25849 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Chains);
25852 // Turn load->store of MMX types into GPR load/stores. This avoids clobbering
25853 // the FP state in cases where an emms may be missing.
25854 // A preferable solution to the general problem is to figure out the right
25855 // places to insert EMMS. This qualifies as a quick hack.
25857 // Similarly, turn load->store of i64 into double load/stores in 32-bit mode.
25858 if (VT.getSizeInBits() != 64)
25861 const Function *F = DAG.getMachineFunction().getFunction();
25862 bool NoImplicitFloatOps = F->hasFnAttribute(Attribute::NoImplicitFloat);
25864 !Subtarget->useSoftFloat() && !NoImplicitFloatOps && Subtarget->hasSSE2();
25865 if ((VT.isVector() ||
25866 (VT == MVT::i64 && F64IsLegal && !Subtarget->is64Bit())) &&
25867 isa<LoadSDNode>(St->getValue()) &&
25868 !cast<LoadSDNode>(St->getValue())->isVolatile() &&
25869 St->getChain().hasOneUse() && !St->isVolatile()) {
25870 SDNode* LdVal = St->getValue().getNode();
25871 LoadSDNode *Ld = nullptr;
25872 int TokenFactorIndex = -1;
25873 SmallVector<SDValue, 8> Ops;
25874 SDNode* ChainVal = St->getChain().getNode();
25875 // Must be a store of a load. We currently handle two cases: the load
25876 // is a direct child, and it's under an intervening TokenFactor. It is
25877 // possible to dig deeper under nested TokenFactors.
25878 if (ChainVal == LdVal)
25879 Ld = cast<LoadSDNode>(St->getChain());
25880 else if (St->getValue().hasOneUse() &&
25881 ChainVal->getOpcode() == ISD::TokenFactor) {
25882 for (unsigned i = 0, e = ChainVal->getNumOperands(); i != e; ++i) {
25883 if (ChainVal->getOperand(i).getNode() == LdVal) {
25884 TokenFactorIndex = i;
25885 Ld = cast<LoadSDNode>(St->getValue());
25887 Ops.push_back(ChainVal->getOperand(i));
25891 if (!Ld || !ISD::isNormalLoad(Ld))
25894 // If this is not the MMX case, i.e. we are just turning i64 load/store
25895 // into f64 load/store, avoid the transformation if there are multiple
25896 // uses of the loaded value.
25897 if (!VT.isVector() && !Ld->hasNUsesOfValue(1, 0))
25902 // If we are a 64-bit capable x86, lower to a single movq load/store pair.
25903 // Otherwise, if it's legal to use f64 SSE instructions, use f64 load/store
25905 if (Subtarget->is64Bit() || F64IsLegal) {
25906 MVT LdVT = Subtarget->is64Bit() ? MVT::i64 : MVT::f64;
25907 SDValue NewLd = DAG.getLoad(LdVT, LdDL, Ld->getChain(), Ld->getBasePtr(),
25908 Ld->getPointerInfo(), Ld->isVolatile(),
25909 Ld->isNonTemporal(), Ld->isInvariant(),
25910 Ld->getAlignment());
25911 SDValue NewChain = NewLd.getValue(1);
25912 if (TokenFactorIndex != -1) {
25913 Ops.push_back(NewChain);
25914 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, Ops);
25916 return DAG.getStore(NewChain, StDL, NewLd, St->getBasePtr(),
25917 St->getPointerInfo(),
25918 St->isVolatile(), St->isNonTemporal(),
25919 St->getAlignment());
25922 // Otherwise, lower to two pairs of 32-bit loads / stores.
25923 SDValue LoAddr = Ld->getBasePtr();
25924 SDValue HiAddr = DAG.getNode(ISD::ADD, LdDL, MVT::i32, LoAddr,
25925 DAG.getConstant(4, LdDL, MVT::i32));
25927 SDValue LoLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), LoAddr,
25928 Ld->getPointerInfo(),
25929 Ld->isVolatile(), Ld->isNonTemporal(),
25930 Ld->isInvariant(), Ld->getAlignment());
25931 SDValue HiLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), HiAddr,
25932 Ld->getPointerInfo().getWithOffset(4),
25933 Ld->isVolatile(), Ld->isNonTemporal(),
25935 MinAlign(Ld->getAlignment(), 4));
25937 SDValue NewChain = LoLd.getValue(1);
25938 if (TokenFactorIndex != -1) {
25939 Ops.push_back(LoLd);
25940 Ops.push_back(HiLd);
25941 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, Ops);
25944 LoAddr = St->getBasePtr();
25945 HiAddr = DAG.getNode(ISD::ADD, StDL, MVT::i32, LoAddr,
25946 DAG.getConstant(4, StDL, MVT::i32));
25948 SDValue LoSt = DAG.getStore(NewChain, StDL, LoLd, LoAddr,
25949 St->getPointerInfo(),
25950 St->isVolatile(), St->isNonTemporal(),
25951 St->getAlignment());
25952 SDValue HiSt = DAG.getStore(NewChain, StDL, HiLd, HiAddr,
25953 St->getPointerInfo().getWithOffset(4),
25955 St->isNonTemporal(),
25956 MinAlign(St->getAlignment(), 4));
25957 return DAG.getNode(ISD::TokenFactor, StDL, MVT::Other, LoSt, HiSt);
25960 // This is similar to the above case, but here we handle a scalar 64-bit
25961 // integer store that is extracted from a vector on a 32-bit target.
25962 // If we have SSE2, then we can treat it like a floating-point double
25963 // to get past legalization. The execution dependencies fixup pass will
25964 // choose the optimal machine instruction for the store if this really is
25965 // an integer or v2f32 rather than an f64.
25966 if (VT == MVT::i64 && F64IsLegal && !Subtarget->is64Bit() &&
25967 St->getOperand(1).getOpcode() == ISD::EXTRACT_VECTOR_ELT) {
25968 SDValue OldExtract = St->getOperand(1);
25969 SDValue ExtOp0 = OldExtract.getOperand(0);
25970 unsigned VecSize = ExtOp0.getValueSizeInBits();
25971 EVT VecVT = EVT::getVectorVT(*DAG.getContext(), MVT::f64, VecSize / 64);
25972 SDValue BitCast = DAG.getBitcast(VecVT, ExtOp0);
25973 SDValue NewExtract = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
25974 BitCast, OldExtract.getOperand(1));
25975 return DAG.getStore(St->getChain(), dl, NewExtract, St->getBasePtr(),
25976 St->getPointerInfo(), St->isVolatile(),
25977 St->isNonTemporal(), St->getAlignment());
25983 /// Return 'true' if this vector operation is "horizontal"
25984 /// and return the operands for the horizontal operation in LHS and RHS. A
25985 /// horizontal operation performs the binary operation on successive elements
25986 /// of its first operand, then on successive elements of its second operand,
25987 /// returning the resulting values in a vector. For example, if
25988 /// A = < float a0, float a1, float a2, float a3 >
25990 /// B = < float b0, float b1, float b2, float b3 >
25991 /// then the result of doing a horizontal operation on A and B is
25992 /// A horizontal-op B = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >.
25993 /// In short, LHS and RHS are inspected to see if LHS op RHS is of the form
25994 /// A horizontal-op B, for some already available A and B, and if so then LHS is
25995 /// set to A, RHS to B, and the routine returns 'true'.
25996 /// Note that the binary operation should have the property that if one of the
25997 /// operands is UNDEF then the result is UNDEF.
25998 static bool isHorizontalBinOp(SDValue &LHS, SDValue &RHS, bool IsCommutative) {
25999 // Look for the following pattern: if
26000 // A = < float a0, float a1, float a2, float a3 >
26001 // B = < float b0, float b1, float b2, float b3 >
26003 // LHS = VECTOR_SHUFFLE A, B, <0, 2, 4, 6>
26004 // RHS = VECTOR_SHUFFLE A, B, <1, 3, 5, 7>
26005 // then LHS op RHS = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >
26006 // which is A horizontal-op B.
26008 // At least one of the operands should be a vector shuffle.
26009 if (LHS.getOpcode() != ISD::VECTOR_SHUFFLE &&
26010 RHS.getOpcode() != ISD::VECTOR_SHUFFLE)
26013 MVT VT = LHS.getSimpleValueType();
26015 assert((VT.is128BitVector() || VT.is256BitVector()) &&
26016 "Unsupported vector type for horizontal add/sub");
26018 // Handle 128 and 256-bit vector lengths. AVX defines horizontal add/sub to
26019 // operate independently on 128-bit lanes.
26020 unsigned NumElts = VT.getVectorNumElements();
26021 unsigned NumLanes = VT.getSizeInBits()/128;
26022 unsigned NumLaneElts = NumElts / NumLanes;
26023 assert((NumLaneElts % 2 == 0) &&
26024 "Vector type should have an even number of elements in each lane");
26025 unsigned HalfLaneElts = NumLaneElts/2;
26027 // View LHS in the form
26028 // LHS = VECTOR_SHUFFLE A, B, LMask
26029 // If LHS is not a shuffle then pretend it is the shuffle
26030 // LHS = VECTOR_SHUFFLE LHS, undef, <0, 1, ..., N-1>
26031 // NOTE: in what follows a default initialized SDValue represents an UNDEF of
26034 SmallVector<int, 16> LMask(NumElts);
26035 if (LHS.getOpcode() == ISD::VECTOR_SHUFFLE) {
26036 if (LHS.getOperand(0).getOpcode() != ISD::UNDEF)
26037 A = LHS.getOperand(0);
26038 if (LHS.getOperand(1).getOpcode() != ISD::UNDEF)
26039 B = LHS.getOperand(1);
26040 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(LHS.getNode())->getMask();
26041 std::copy(Mask.begin(), Mask.end(), LMask.begin());
26043 if (LHS.getOpcode() != ISD::UNDEF)
26045 for (unsigned i = 0; i != NumElts; ++i)
26049 // Likewise, view RHS in the form
26050 // RHS = VECTOR_SHUFFLE C, D, RMask
26052 SmallVector<int, 16> RMask(NumElts);
26053 if (RHS.getOpcode() == ISD::VECTOR_SHUFFLE) {
26054 if (RHS.getOperand(0).getOpcode() != ISD::UNDEF)
26055 C = RHS.getOperand(0);
26056 if (RHS.getOperand(1).getOpcode() != ISD::UNDEF)
26057 D = RHS.getOperand(1);
26058 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(RHS.getNode())->getMask();
26059 std::copy(Mask.begin(), Mask.end(), RMask.begin());
26061 if (RHS.getOpcode() != ISD::UNDEF)
26063 for (unsigned i = 0; i != NumElts; ++i)
26067 // Check that the shuffles are both shuffling the same vectors.
26068 if (!(A == C && B == D) && !(A == D && B == C))
26071 // If everything is UNDEF then bail out: it would be better to fold to UNDEF.
26072 if (!A.getNode() && !B.getNode())
26075 // If A and B occur in reverse order in RHS, then "swap" them (which means
26076 // rewriting the mask).
26078 ShuffleVectorSDNode::commuteMask(RMask);
26080 // At this point LHS and RHS are equivalent to
26081 // LHS = VECTOR_SHUFFLE A, B, LMask
26082 // RHS = VECTOR_SHUFFLE A, B, RMask
26083 // Check that the masks correspond to performing a horizontal operation.
26084 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
26085 for (unsigned i = 0; i != NumLaneElts; ++i) {
26086 int LIdx = LMask[i+l], RIdx = RMask[i+l];
26088 // Ignore any UNDEF components.
26089 if (LIdx < 0 || RIdx < 0 ||
26090 (!A.getNode() && (LIdx < (int)NumElts || RIdx < (int)NumElts)) ||
26091 (!B.getNode() && (LIdx >= (int)NumElts || RIdx >= (int)NumElts)))
26094 // Check that successive elements are being operated on. If not, this is
26095 // not a horizontal operation.
26096 unsigned Src = (i/HalfLaneElts); // each lane is split between srcs
26097 int Index = 2*(i%HalfLaneElts) + NumElts*Src + l;
26098 if (!(LIdx == Index && RIdx == Index + 1) &&
26099 !(IsCommutative && LIdx == Index + 1 && RIdx == Index))
26104 LHS = A.getNode() ? A : B; // If A is 'UNDEF', use B for it.
26105 RHS = B.getNode() ? B : A; // If B is 'UNDEF', use A for it.
26109 /// Do target-specific dag combines on floating point adds.
26110 static SDValue PerformFADDCombine(SDNode *N, SelectionDAG &DAG,
26111 const X86Subtarget *Subtarget) {
26112 EVT VT = N->getValueType(0);
26113 SDValue LHS = N->getOperand(0);
26114 SDValue RHS = N->getOperand(1);
26116 // Try to synthesize horizontal adds from adds of shuffles.
26117 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
26118 (Subtarget->hasFp256() && (VT == MVT::v8f32 || VT == MVT::v4f64))) &&
26119 isHorizontalBinOp(LHS, RHS, true))
26120 return DAG.getNode(X86ISD::FHADD, SDLoc(N), VT, LHS, RHS);
26124 /// Do target-specific dag combines on floating point subs.
26125 static SDValue PerformFSUBCombine(SDNode *N, SelectionDAG &DAG,
26126 const X86Subtarget *Subtarget) {
26127 EVT VT = N->getValueType(0);
26128 SDValue LHS = N->getOperand(0);
26129 SDValue RHS = N->getOperand(1);
26131 // Try to synthesize horizontal subs from subs of shuffles.
26132 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
26133 (Subtarget->hasFp256() && (VT == MVT::v8f32 || VT == MVT::v4f64))) &&
26134 isHorizontalBinOp(LHS, RHS, false))
26135 return DAG.getNode(X86ISD::FHSUB, SDLoc(N), VT, LHS, RHS);
26139 /// Do target-specific dag combines on floating point negations.
26140 static SDValue PerformFNEGCombine(SDNode *N, SelectionDAG &DAG,
26141 const X86Subtarget *Subtarget) {
26142 EVT VT = N->getValueType(0);
26143 SDValue Arg = N->getOperand(0);
26145 // If we're negating a FMA node, then we can adjust the
26146 // instruction to include the extra negation.
26147 if (Arg.hasOneUse()) {
26148 switch (Arg.getOpcode()) {
26149 case X86ISD::FMADD:
26150 return DAG.getNode(X86ISD::FNMSUB, SDLoc(N), VT, Arg.getOperand(0),
26151 Arg.getOperand(1), Arg.getOperand(2));
26152 case X86ISD::FMSUB:
26153 return DAG.getNode(X86ISD::FNMADD, SDLoc(N), VT, Arg.getOperand(0),
26154 Arg.getOperand(1), Arg.getOperand(2));
26155 case X86ISD::FNMADD:
26156 return DAG.getNode(X86ISD::FMSUB, SDLoc(N), VT, Arg.getOperand(0),
26157 Arg.getOperand(1), Arg.getOperand(2));
26158 case X86ISD::FNMSUB:
26159 return DAG.getNode(X86ISD::FMADD, SDLoc(N), VT, Arg.getOperand(0),
26160 Arg.getOperand(1), Arg.getOperand(2));
26166 /// Do target-specific dag combines on X86ISD::FOR and X86ISD::FXOR nodes.
26167 static SDValue PerformFORCombine(SDNode *N, SelectionDAG &DAG,
26168 const X86Subtarget *Subtarget) {
26169 assert(N->getOpcode() == X86ISD::FOR || N->getOpcode() == X86ISD::FXOR);
26171 // F[X]OR(0.0, x) -> x
26172 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
26173 if (C->getValueAPF().isPosZero())
26174 return N->getOperand(1);
26176 // F[X]OR(x, 0.0) -> x
26177 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
26178 if (C->getValueAPF().isPosZero())
26179 return N->getOperand(0);
26181 EVT VT = N->getValueType(0);
26182 if (VT.is512BitVector() && !Subtarget->hasDQI()) {
26184 MVT IntScalar = MVT::getIntegerVT(VT.getScalarSizeInBits());
26185 MVT IntVT = MVT::getVectorVT(IntScalar, VT.getVectorNumElements());
26187 SDValue Op0 = DAG.getNode(ISD::BITCAST, dl, IntVT, N->getOperand(0));
26188 SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, IntVT, N->getOperand(1));
26189 unsigned IntOpcode = (N->getOpcode() == X86ISD::FOR) ? ISD::OR : ISD::XOR;
26190 SDValue IntOp = DAG.getNode(IntOpcode, dl, IntVT, Op0, Op1);
26191 return DAG.getNode(ISD::BITCAST, dl, VT, IntOp);
26196 /// Do target-specific dag combines on X86ISD::FMIN and X86ISD::FMAX nodes.
26197 static SDValue PerformFMinFMaxCombine(SDNode *N, SelectionDAG &DAG) {
26198 assert(N->getOpcode() == X86ISD::FMIN || N->getOpcode() == X86ISD::FMAX);
26200 // Only perform optimizations if UnsafeMath is used.
26201 if (!DAG.getTarget().Options.UnsafeFPMath)
26204 // If we run in unsafe-math mode, then convert the FMAX and FMIN nodes
26205 // into FMINC and FMAXC, which are Commutative operations.
26206 unsigned NewOp = 0;
26207 switch (N->getOpcode()) {
26208 default: llvm_unreachable("unknown opcode");
26209 case X86ISD::FMIN: NewOp = X86ISD::FMINC; break;
26210 case X86ISD::FMAX: NewOp = X86ISD::FMAXC; break;
26213 return DAG.getNode(NewOp, SDLoc(N), N->getValueType(0),
26214 N->getOperand(0), N->getOperand(1));
26217 /// Do target-specific dag combines on X86ISD::FAND nodes.
26218 static SDValue PerformFANDCombine(SDNode *N, SelectionDAG &DAG) {
26219 // FAND(0.0, x) -> 0.0
26220 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
26221 if (C->getValueAPF().isPosZero())
26222 return N->getOperand(0);
26224 // FAND(x, 0.0) -> 0.0
26225 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
26226 if (C->getValueAPF().isPosZero())
26227 return N->getOperand(1);
26232 /// Do target-specific dag combines on X86ISD::FANDN nodes
26233 static SDValue PerformFANDNCombine(SDNode *N, SelectionDAG &DAG) {
26234 // FANDN(0.0, x) -> x
26235 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
26236 if (C->getValueAPF().isPosZero())
26237 return N->getOperand(1);
26239 // FANDN(x, 0.0) -> 0.0
26240 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
26241 if (C->getValueAPF().isPosZero())
26242 return N->getOperand(1);
26247 static SDValue PerformBTCombine(SDNode *N,
26249 TargetLowering::DAGCombinerInfo &DCI) {
26250 // BT ignores high bits in the bit index operand.
26251 SDValue Op1 = N->getOperand(1);
26252 if (Op1.hasOneUse()) {
26253 unsigned BitWidth = Op1.getValueSizeInBits();
26254 APInt DemandedMask = APInt::getLowBitsSet(BitWidth, Log2_32(BitWidth));
26255 APInt KnownZero, KnownOne;
26256 TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(),
26257 !DCI.isBeforeLegalizeOps());
26258 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
26259 if (TLO.ShrinkDemandedConstant(Op1, DemandedMask) ||
26260 TLI.SimplifyDemandedBits(Op1, DemandedMask, KnownZero, KnownOne, TLO))
26261 DCI.CommitTargetLoweringOpt(TLO);
26266 static SDValue PerformVZEXT_MOVLCombine(SDNode *N, SelectionDAG &DAG) {
26267 SDValue Op = N->getOperand(0);
26268 if (Op.getOpcode() == ISD::BITCAST)
26269 Op = Op.getOperand(0);
26270 EVT VT = N->getValueType(0), OpVT = Op.getValueType();
26271 if (Op.getOpcode() == X86ISD::VZEXT_LOAD &&
26272 VT.getVectorElementType().getSizeInBits() ==
26273 OpVT.getVectorElementType().getSizeInBits()) {
26274 return DAG.getNode(ISD::BITCAST, SDLoc(N), VT, Op);
26279 static SDValue PerformSIGN_EXTEND_INREGCombine(SDNode *N, SelectionDAG &DAG,
26280 const X86Subtarget *Subtarget) {
26281 EVT VT = N->getValueType(0);
26282 if (!VT.isVector())
26285 SDValue N0 = N->getOperand(0);
26286 SDValue N1 = N->getOperand(1);
26287 EVT ExtraVT = cast<VTSDNode>(N1)->getVT();
26290 // The SIGN_EXTEND_INREG to v4i64 is expensive operation on the
26291 // both SSE and AVX2 since there is no sign-extended shift right
26292 // operation on a vector with 64-bit elements.
26293 //(sext_in_reg (v4i64 anyext (v4i32 x )), ExtraVT) ->
26294 // (v4i64 sext (v4i32 sext_in_reg (v4i32 x , ExtraVT)))
26295 if (VT == MVT::v4i64 && (N0.getOpcode() == ISD::ANY_EXTEND ||
26296 N0.getOpcode() == ISD::SIGN_EXTEND)) {
26297 SDValue N00 = N0.getOperand(0);
26299 // EXTLOAD has a better solution on AVX2,
26300 // it may be replaced with X86ISD::VSEXT node.
26301 if (N00.getOpcode() == ISD::LOAD && Subtarget->hasInt256())
26302 if (!ISD::isNormalLoad(N00.getNode()))
26305 if (N00.getValueType() == MVT::v4i32 && ExtraVT.getSizeInBits() < 128) {
26306 SDValue Tmp = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, MVT::v4i32,
26308 return DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v4i64, Tmp);
26314 /// sext(add_nsw(x, C)) --> add(sext(x), C_sext)
26315 /// Promoting a sign extension ahead of an 'add nsw' exposes opportunities
26316 /// to combine math ops, use an LEA, or use a complex addressing mode. This can
26317 /// eliminate extend, add, and shift instructions.
26318 static SDValue promoteSextBeforeAddNSW(SDNode *Sext, SelectionDAG &DAG,
26319 const X86Subtarget *Subtarget) {
26320 // TODO: This should be valid for other integer types.
26321 EVT VT = Sext->getValueType(0);
26322 if (VT != MVT::i64)
26325 // We need an 'add nsw' feeding into the 'sext'.
26326 SDValue Add = Sext->getOperand(0);
26327 if (Add.getOpcode() != ISD::ADD || !Add->getFlags()->hasNoSignedWrap())
26330 // Having a constant operand to the 'add' ensures that we are not increasing
26331 // the instruction count because the constant is extended for free below.
26332 // A constant operand can also become the displacement field of an LEA.
26333 auto *AddOp1 = dyn_cast<ConstantSDNode>(Add.getOperand(1));
26337 // Don't make the 'add' bigger if there's no hope of combining it with some
26338 // other 'add' or 'shl' instruction.
26339 // TODO: It may be profitable to generate simpler LEA instructions in place
26340 // of single 'add' instructions, but the cost model for selecting an LEA
26341 // currently has a high threshold.
26342 bool HasLEAPotential = false;
26343 for (auto *User : Sext->uses()) {
26344 if (User->getOpcode() == ISD::ADD || User->getOpcode() == ISD::SHL) {
26345 HasLEAPotential = true;
26349 if (!HasLEAPotential)
26352 // Everything looks good, so pull the 'sext' ahead of the 'add'.
26353 int64_t AddConstant = AddOp1->getSExtValue();
26354 SDValue AddOp0 = Add.getOperand(0);
26355 SDValue NewSext = DAG.getNode(ISD::SIGN_EXTEND, SDLoc(Sext), VT, AddOp0);
26356 SDValue NewConstant = DAG.getConstant(AddConstant, SDLoc(Add), VT);
26358 // The wider add is guaranteed to not wrap because both operands are
26361 Flags.setNoSignedWrap(true);
26362 return DAG.getNode(ISD::ADD, SDLoc(Add), VT, NewSext, NewConstant, &Flags);
26365 static SDValue PerformSExtCombine(SDNode *N, SelectionDAG &DAG,
26366 TargetLowering::DAGCombinerInfo &DCI,
26367 const X86Subtarget *Subtarget) {
26368 SDValue N0 = N->getOperand(0);
26369 EVT VT = N->getValueType(0);
26370 EVT SVT = VT.getScalarType();
26371 EVT InVT = N0.getValueType();
26372 EVT InSVT = InVT.getScalarType();
26375 // (i8,i32 sext (sdivrem (i8 x, i8 y)) ->
26376 // (i8,i32 (sdivrem_sext_hreg (i8 x, i8 y)
26377 // This exposes the sext to the sdivrem lowering, so that it directly extends
26378 // from AH (which we otherwise need to do contortions to access).
26379 if (N0.getOpcode() == ISD::SDIVREM && N0.getResNo() == 1 &&
26380 InVT == MVT::i8 && VT == MVT::i32) {
26381 SDVTList NodeTys = DAG.getVTList(MVT::i8, VT);
26382 SDValue R = DAG.getNode(X86ISD::SDIVREM8_SEXT_HREG, DL, NodeTys,
26383 N0.getOperand(0), N0.getOperand(1));
26384 DAG.ReplaceAllUsesOfValueWith(N0.getValue(0), R.getValue(0));
26385 return R.getValue(1);
26388 if (!DCI.isBeforeLegalizeOps()) {
26389 if (InVT == MVT::i1) {
26390 SDValue Zero = DAG.getConstant(0, DL, VT);
26392 DAG.getConstant(APInt::getAllOnesValue(VT.getSizeInBits()), DL, VT);
26393 return DAG.getNode(ISD::SELECT, DL, VT, N0, AllOnes, Zero);
26398 if (VT.isVector() && Subtarget->hasSSE2()) {
26399 auto ExtendVecSize = [&DAG](SDLoc DL, SDValue N, unsigned Size) {
26400 EVT InVT = N.getValueType();
26401 EVT OutVT = EVT::getVectorVT(*DAG.getContext(), InVT.getScalarType(),
26402 Size / InVT.getScalarSizeInBits());
26403 SmallVector<SDValue, 8> Opnds(Size / InVT.getSizeInBits(),
26404 DAG.getUNDEF(InVT));
26406 return DAG.getNode(ISD::CONCAT_VECTORS, DL, OutVT, Opnds);
26409 // If target-size is less than 128-bits, extend to a type that would extend
26410 // to 128 bits, extend that and extract the original target vector.
26411 if (VT.getSizeInBits() < 128 && !(128 % VT.getSizeInBits()) &&
26412 (SVT == MVT::i64 || SVT == MVT::i32 || SVT == MVT::i16) &&
26413 (InSVT == MVT::i32 || InSVT == MVT::i16 || InSVT == MVT::i8)) {
26414 unsigned Scale = 128 / VT.getSizeInBits();
26416 EVT::getVectorVT(*DAG.getContext(), SVT, 128 / SVT.getSizeInBits());
26417 SDValue Ex = ExtendVecSize(DL, N0, Scale * InVT.getSizeInBits());
26418 SDValue SExt = DAG.getNode(ISD::SIGN_EXTEND, DL, ExVT, Ex);
26419 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, SExt,
26420 DAG.getIntPtrConstant(0, DL));
26423 // If target-size is 128-bits, then convert to ISD::SIGN_EXTEND_VECTOR_INREG
26424 // which ensures lowering to X86ISD::VSEXT (pmovsx*).
26425 if (VT.getSizeInBits() == 128 &&
26426 (SVT == MVT::i64 || SVT == MVT::i32 || SVT == MVT::i16) &&
26427 (InSVT == MVT::i32 || InSVT == MVT::i16 || InSVT == MVT::i8)) {
26428 SDValue ExOp = ExtendVecSize(DL, N0, 128);
26429 return DAG.getSignExtendVectorInReg(ExOp, DL, VT);
26432 // On pre-AVX2 targets, split into 128-bit nodes of
26433 // ISD::SIGN_EXTEND_VECTOR_INREG.
26434 if (!Subtarget->hasInt256() && !(VT.getSizeInBits() % 128) &&
26435 (SVT == MVT::i64 || SVT == MVT::i32 || SVT == MVT::i16) &&
26436 (InSVT == MVT::i32 || InSVT == MVT::i16 || InSVT == MVT::i8)) {
26437 unsigned NumVecs = VT.getSizeInBits() / 128;
26438 unsigned NumSubElts = 128 / SVT.getSizeInBits();
26439 EVT SubVT = EVT::getVectorVT(*DAG.getContext(), SVT, NumSubElts);
26440 EVT InSubVT = EVT::getVectorVT(*DAG.getContext(), InSVT, NumSubElts);
26442 SmallVector<SDValue, 8> Opnds;
26443 for (unsigned i = 0, Offset = 0; i != NumVecs;
26444 ++i, Offset += NumSubElts) {
26445 SDValue SrcVec = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, InSubVT, N0,
26446 DAG.getIntPtrConstant(Offset, DL));
26447 SrcVec = ExtendVecSize(DL, SrcVec, 128);
26448 SrcVec = DAG.getSignExtendVectorInReg(SrcVec, DL, SubVT);
26449 Opnds.push_back(SrcVec);
26451 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, Opnds);
26455 if (Subtarget->hasAVX() && VT.is256BitVector())
26456 if (SDValue R = WidenMaskArithmetic(N, DAG, DCI, Subtarget))
26459 if (SDValue NewAdd = promoteSextBeforeAddNSW(N, DAG, Subtarget))
26465 static SDValue PerformFMACombine(SDNode *N, SelectionDAG &DAG,
26466 const X86Subtarget* Subtarget) {
26468 EVT VT = N->getValueType(0);
26470 // Let legalize expand this if it isn't a legal type yet.
26471 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
26474 EVT ScalarVT = VT.getScalarType();
26475 if ((ScalarVT != MVT::f32 && ScalarVT != MVT::f64) ||
26476 (!Subtarget->hasFMA() && !Subtarget->hasFMA4() &&
26477 !Subtarget->hasAVX512()))
26480 SDValue A = N->getOperand(0);
26481 SDValue B = N->getOperand(1);
26482 SDValue C = N->getOperand(2);
26484 bool NegA = (A.getOpcode() == ISD::FNEG);
26485 bool NegB = (B.getOpcode() == ISD::FNEG);
26486 bool NegC = (C.getOpcode() == ISD::FNEG);
26488 // Negative multiplication when NegA xor NegB
26489 bool NegMul = (NegA != NegB);
26491 A = A.getOperand(0);
26493 B = B.getOperand(0);
26495 C = C.getOperand(0);
26499 Opcode = (!NegC) ? X86ISD::FMADD : X86ISD::FMSUB;
26501 Opcode = (!NegC) ? X86ISD::FNMADD : X86ISD::FNMSUB;
26503 return DAG.getNode(Opcode, dl, VT, A, B, C);
26506 static SDValue PerformZExtCombine(SDNode *N, SelectionDAG &DAG,
26507 TargetLowering::DAGCombinerInfo &DCI,
26508 const X86Subtarget *Subtarget) {
26509 // (i32 zext (and (i8 x86isd::setcc_carry), 1)) ->
26510 // (and (i32 x86isd::setcc_carry), 1)
26511 // This eliminates the zext. This transformation is necessary because
26512 // ISD::SETCC is always legalized to i8.
26514 SDValue N0 = N->getOperand(0);
26515 EVT VT = N->getValueType(0);
26517 if (N0.getOpcode() == ISD::AND &&
26519 N0.getOperand(0).hasOneUse()) {
26520 SDValue N00 = N0.getOperand(0);
26521 if (N00.getOpcode() == X86ISD::SETCC_CARRY) {
26522 if (!isOneConstant(N0.getOperand(1)))
26524 return DAG.getNode(ISD::AND, dl, VT,
26525 DAG.getNode(X86ISD::SETCC_CARRY, dl, VT,
26526 N00.getOperand(0), N00.getOperand(1)),
26527 DAG.getConstant(1, dl, VT));
26531 if (N0.getOpcode() == ISD::TRUNCATE &&
26533 N0.getOperand(0).hasOneUse()) {
26534 SDValue N00 = N0.getOperand(0);
26535 if (N00.getOpcode() == X86ISD::SETCC_CARRY) {
26536 return DAG.getNode(ISD::AND, dl, VT,
26537 DAG.getNode(X86ISD::SETCC_CARRY, dl, VT,
26538 N00.getOperand(0), N00.getOperand(1)),
26539 DAG.getConstant(1, dl, VT));
26543 if (VT.is256BitVector())
26544 if (SDValue R = WidenMaskArithmetic(N, DAG, DCI, Subtarget))
26547 // (i8,i32 zext (udivrem (i8 x, i8 y)) ->
26548 // (i8,i32 (udivrem_zext_hreg (i8 x, i8 y)
26549 // This exposes the zext to the udivrem lowering, so that it directly extends
26550 // from AH (which we otherwise need to do contortions to access).
26551 if (N0.getOpcode() == ISD::UDIVREM &&
26552 N0.getResNo() == 1 && N0.getValueType() == MVT::i8 &&
26553 (VT == MVT::i32 || VT == MVT::i64)) {
26554 SDVTList NodeTys = DAG.getVTList(MVT::i8, VT);
26555 SDValue R = DAG.getNode(X86ISD::UDIVREM8_ZEXT_HREG, dl, NodeTys,
26556 N0.getOperand(0), N0.getOperand(1));
26557 DAG.ReplaceAllUsesOfValueWith(N0.getValue(0), R.getValue(0));
26558 return R.getValue(1);
26564 // Optimize x == -y --> x+y == 0
26565 // x != -y --> x+y != 0
26566 static SDValue PerformISDSETCCCombine(SDNode *N, SelectionDAG &DAG,
26567 const X86Subtarget* Subtarget) {
26568 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(2))->get();
26569 SDValue LHS = N->getOperand(0);
26570 SDValue RHS = N->getOperand(1);
26571 EVT VT = N->getValueType(0);
26574 if ((CC == ISD::SETNE || CC == ISD::SETEQ) && LHS.getOpcode() == ISD::SUB)
26575 if (isNullConstant(LHS.getOperand(0)) && LHS.hasOneUse()) {
26576 SDValue addV = DAG.getNode(ISD::ADD, DL, LHS.getValueType(), RHS,
26577 LHS.getOperand(1));
26578 return DAG.getSetCC(DL, N->getValueType(0), addV,
26579 DAG.getConstant(0, DL, addV.getValueType()), CC);
26581 if ((CC == ISD::SETNE || CC == ISD::SETEQ) && RHS.getOpcode() == ISD::SUB)
26582 if (isNullConstant(RHS.getOperand(0)) && RHS.hasOneUse()) {
26583 SDValue addV = DAG.getNode(ISD::ADD, DL, RHS.getValueType(), LHS,
26584 RHS.getOperand(1));
26585 return DAG.getSetCC(DL, N->getValueType(0), addV,
26586 DAG.getConstant(0, DL, addV.getValueType()), CC);
26589 if (VT.getScalarType() == MVT::i1 &&
26590 (CC == ISD::SETNE || CC == ISD::SETEQ || ISD::isSignedIntSetCC(CC))) {
26592 (LHS.getOpcode() == ISD::SIGN_EXTEND) &&
26593 (LHS.getOperand(0).getValueType().getScalarType() == MVT::i1);
26594 bool IsVZero1 = ISD::isBuildVectorAllZeros(RHS.getNode());
26596 if (!IsSEXT0 || !IsVZero1) {
26597 // Swap the operands and update the condition code.
26598 std::swap(LHS, RHS);
26599 CC = ISD::getSetCCSwappedOperands(CC);
26601 IsSEXT0 = (LHS.getOpcode() == ISD::SIGN_EXTEND) &&
26602 (LHS.getOperand(0).getValueType().getScalarType() == MVT::i1);
26603 IsVZero1 = ISD::isBuildVectorAllZeros(RHS.getNode());
26606 if (IsSEXT0 && IsVZero1) {
26607 assert(VT == LHS.getOperand(0).getValueType() &&
26608 "Uexpected operand type");
26609 if (CC == ISD::SETGT)
26610 return DAG.getConstant(0, DL, VT);
26611 if (CC == ISD::SETLE)
26612 return DAG.getConstant(1, DL, VT);
26613 if (CC == ISD::SETEQ || CC == ISD::SETGE)
26614 return DAG.getNOT(DL, LHS.getOperand(0), VT);
26616 assert((CC == ISD::SETNE || CC == ISD::SETLT) &&
26617 "Unexpected condition code!");
26618 return LHS.getOperand(0);
26625 static SDValue PerformBLENDICombine(SDNode *N, SelectionDAG &DAG) {
26626 SDValue V0 = N->getOperand(0);
26627 SDValue V1 = N->getOperand(1);
26629 EVT VT = N->getValueType(0);
26631 // Canonicalize a v2f64 blend with a mask of 2 by swapping the vector
26632 // operands and changing the mask to 1. This saves us a bunch of
26633 // pattern-matching possibilities related to scalar math ops in SSE/AVX.
26634 // x86InstrInfo knows how to commute this back after instruction selection
26635 // if it would help register allocation.
26637 // TODO: If optimizing for size or a processor that doesn't suffer from
26638 // partial register update stalls, this should be transformed into a MOVSD
26639 // instruction because a MOVSD is 1-2 bytes smaller than a BLENDPD.
26641 if (VT == MVT::v2f64)
26642 if (auto *Mask = dyn_cast<ConstantSDNode>(N->getOperand(2)))
26643 if (Mask->getZExtValue() == 2 && !isShuffleFoldableLoad(V0)) {
26644 SDValue NewMask = DAG.getConstant(1, DL, MVT::i8);
26645 return DAG.getNode(X86ISD::BLENDI, DL, VT, V1, V0, NewMask);
26651 // Helper function of PerformSETCCCombine. It is to materialize "setb reg"
26652 // as "sbb reg,reg", since it can be extended without zext and produces
26653 // an all-ones bit which is more useful than 0/1 in some cases.
26654 static SDValue MaterializeSETB(SDLoc DL, SDValue EFLAGS, SelectionDAG &DAG,
26657 return DAG.getNode(ISD::AND, DL, VT,
26658 DAG.getNode(X86ISD::SETCC_CARRY, DL, MVT::i8,
26659 DAG.getConstant(X86::COND_B, DL, MVT::i8),
26661 DAG.getConstant(1, DL, VT));
26662 assert (VT == MVT::i1 && "Unexpected type for SECCC node");
26663 return DAG.getNode(ISD::TRUNCATE, DL, MVT::i1,
26664 DAG.getNode(X86ISD::SETCC_CARRY, DL, MVT::i8,
26665 DAG.getConstant(X86::COND_B, DL, MVT::i8),
26669 // Optimize RES = X86ISD::SETCC CONDCODE, EFLAG_INPUT
26670 static SDValue PerformSETCCCombine(SDNode *N, SelectionDAG &DAG,
26671 TargetLowering::DAGCombinerInfo &DCI,
26672 const X86Subtarget *Subtarget) {
26674 X86::CondCode CC = X86::CondCode(N->getConstantOperandVal(0));
26675 SDValue EFLAGS = N->getOperand(1);
26677 if (CC == X86::COND_A) {
26678 // Try to convert COND_A into COND_B in an attempt to facilitate
26679 // materializing "setb reg".
26681 // Do not flip "e > c", where "c" is a constant, because Cmp instruction
26682 // cannot take an immediate as its first operand.
26684 if (EFLAGS.getOpcode() == X86ISD::SUB && EFLAGS.hasOneUse() &&
26685 EFLAGS.getValueType().isInteger() &&
26686 !isa<ConstantSDNode>(EFLAGS.getOperand(1))) {
26687 SDValue NewSub = DAG.getNode(X86ISD::SUB, SDLoc(EFLAGS),
26688 EFLAGS.getNode()->getVTList(),
26689 EFLAGS.getOperand(1), EFLAGS.getOperand(0));
26690 SDValue NewEFLAGS = SDValue(NewSub.getNode(), EFLAGS.getResNo());
26691 return MaterializeSETB(DL, NewEFLAGS, DAG, N->getSimpleValueType(0));
26695 // Materialize "setb reg" as "sbb reg,reg", since it can be extended without
26696 // a zext and produces an all-ones bit which is more useful than 0/1 in some
26698 if (CC == X86::COND_B)
26699 return MaterializeSETB(DL, EFLAGS, DAG, N->getSimpleValueType(0));
26701 if (SDValue Flags = checkBoolTestSetCCCombine(EFLAGS, CC)) {
26702 SDValue Cond = DAG.getConstant(CC, DL, MVT::i8);
26703 return DAG.getNode(X86ISD::SETCC, DL, N->getVTList(), Cond, Flags);
26709 // Optimize branch condition evaluation.
26711 static SDValue PerformBrCondCombine(SDNode *N, SelectionDAG &DAG,
26712 TargetLowering::DAGCombinerInfo &DCI,
26713 const X86Subtarget *Subtarget) {
26715 SDValue Chain = N->getOperand(0);
26716 SDValue Dest = N->getOperand(1);
26717 SDValue EFLAGS = N->getOperand(3);
26718 X86::CondCode CC = X86::CondCode(N->getConstantOperandVal(2));
26720 if (SDValue Flags = checkBoolTestSetCCCombine(EFLAGS, CC)) {
26721 SDValue Cond = DAG.getConstant(CC, DL, MVT::i8);
26722 return DAG.getNode(X86ISD::BRCOND, DL, N->getVTList(), Chain, Dest, Cond,
26729 static SDValue performVectorCompareAndMaskUnaryOpCombine(SDNode *N,
26730 SelectionDAG &DAG) {
26731 // Take advantage of vector comparisons producing 0 or -1 in each lane to
26732 // optimize away operation when it's from a constant.
26734 // The general transformation is:
26735 // UNARYOP(AND(VECTOR_CMP(x,y), constant)) -->
26736 // AND(VECTOR_CMP(x,y), constant2)
26737 // constant2 = UNARYOP(constant)
26739 // Early exit if this isn't a vector operation, the operand of the
26740 // unary operation isn't a bitwise AND, or if the sizes of the operations
26741 // aren't the same.
26742 EVT VT = N->getValueType(0);
26743 if (!VT.isVector() || N->getOperand(0)->getOpcode() != ISD::AND ||
26744 N->getOperand(0)->getOperand(0)->getOpcode() != ISD::SETCC ||
26745 VT.getSizeInBits() != N->getOperand(0)->getValueType(0).getSizeInBits())
26748 // Now check that the other operand of the AND is a constant. We could
26749 // make the transformation for non-constant splats as well, but it's unclear
26750 // that would be a benefit as it would not eliminate any operations, just
26751 // perform one more step in scalar code before moving to the vector unit.
26752 if (BuildVectorSDNode *BV =
26753 dyn_cast<BuildVectorSDNode>(N->getOperand(0)->getOperand(1))) {
26754 // Bail out if the vector isn't a constant.
26755 if (!BV->isConstant())
26758 // Everything checks out. Build up the new and improved node.
26760 EVT IntVT = BV->getValueType(0);
26761 // Create a new constant of the appropriate type for the transformed
26763 SDValue SourceConst = DAG.getNode(N->getOpcode(), DL, VT, SDValue(BV, 0));
26764 // The AND node needs bitcasts to/from an integer vector type around it.
26765 SDValue MaskConst = DAG.getBitcast(IntVT, SourceConst);
26766 SDValue NewAnd = DAG.getNode(ISD::AND, DL, IntVT,
26767 N->getOperand(0)->getOperand(0), MaskConst);
26768 SDValue Res = DAG.getBitcast(VT, NewAnd);
26775 static SDValue PerformUINT_TO_FPCombine(SDNode *N, SelectionDAG &DAG,
26776 const X86Subtarget *Subtarget) {
26777 SDValue Op0 = N->getOperand(0);
26778 EVT VT = N->getValueType(0);
26779 EVT InVT = Op0.getValueType();
26780 EVT InSVT = InVT.getScalarType();
26781 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
26783 // UINT_TO_FP(vXi8) -> SINT_TO_FP(ZEXT(vXi8 to vXi32))
26784 // UINT_TO_FP(vXi16) -> SINT_TO_FP(ZEXT(vXi16 to vXi32))
26785 if (InVT.isVector() && (InSVT == MVT::i8 || InSVT == MVT::i16)) {
26787 EVT DstVT = EVT::getVectorVT(*DAG.getContext(), MVT::i32,
26788 InVT.getVectorNumElements());
26789 SDValue P = DAG.getNode(ISD::ZERO_EXTEND, dl, DstVT, Op0);
26791 if (TLI.isOperationLegal(ISD::UINT_TO_FP, DstVT))
26792 return DAG.getNode(ISD::UINT_TO_FP, dl, VT, P);
26794 return DAG.getNode(ISD::SINT_TO_FP, dl, VT, P);
26800 static SDValue PerformSINT_TO_FPCombine(SDNode *N, SelectionDAG &DAG,
26801 const X86Subtarget *Subtarget) {
26802 // First try to optimize away the conversion entirely when it's
26803 // conditionally from a constant. Vectors only.
26804 if (SDValue Res = performVectorCompareAndMaskUnaryOpCombine(N, DAG))
26807 // Now move on to more general possibilities.
26808 SDValue Op0 = N->getOperand(0);
26809 EVT VT = N->getValueType(0);
26810 EVT InVT = Op0.getValueType();
26811 EVT InSVT = InVT.getScalarType();
26813 // SINT_TO_FP(vXi8) -> SINT_TO_FP(SEXT(vXi8 to vXi32))
26814 // SINT_TO_FP(vXi16) -> SINT_TO_FP(SEXT(vXi16 to vXi32))
26815 if (InVT.isVector() && (InSVT == MVT::i8 || InSVT == MVT::i16)) {
26817 EVT DstVT = EVT::getVectorVT(*DAG.getContext(), MVT::i32,
26818 InVT.getVectorNumElements());
26819 SDValue P = DAG.getNode(ISD::SIGN_EXTEND, dl, DstVT, Op0);
26820 return DAG.getNode(ISD::SINT_TO_FP, dl, VT, P);
26823 // Transform (SINT_TO_FP (i64 ...)) into an x87 operation if we have
26824 // a 32-bit target where SSE doesn't support i64->FP operations.
26825 if (!Subtarget->useSoftFloat() && Op0.getOpcode() == ISD::LOAD) {
26826 LoadSDNode *Ld = cast<LoadSDNode>(Op0.getNode());
26827 EVT LdVT = Ld->getValueType(0);
26829 // This transformation is not supported if the result type is f16
26830 if (VT == MVT::f16)
26833 if (!Ld->isVolatile() && !VT.isVector() &&
26834 ISD::isNON_EXTLoad(Op0.getNode()) && Op0.hasOneUse() &&
26835 !Subtarget->is64Bit() && LdVT == MVT::i64) {
26836 SDValue FILDChain = Subtarget->getTargetLowering()->BuildFILD(
26837 SDValue(N, 0), LdVT, Ld->getChain(), Op0, DAG);
26838 DAG.ReplaceAllUsesOfValueWith(Op0.getValue(1), FILDChain.getValue(1));
26845 // Optimize RES, EFLAGS = X86ISD::ADC LHS, RHS, EFLAGS
26846 static SDValue PerformADCCombine(SDNode *N, SelectionDAG &DAG,
26847 X86TargetLowering::DAGCombinerInfo &DCI) {
26848 // If the LHS and RHS of the ADC node are zero, then it can't overflow and
26849 // the result is either zero or one (depending on the input carry bit).
26850 // Strength reduce this down to a "set on carry" aka SETCC_CARRY&1.
26851 if (X86::isZeroNode(N->getOperand(0)) &&
26852 X86::isZeroNode(N->getOperand(1)) &&
26853 // We don't have a good way to replace an EFLAGS use, so only do this when
26855 SDValue(N, 1).use_empty()) {
26857 EVT VT = N->getValueType(0);
26858 SDValue CarryOut = DAG.getConstant(0, DL, N->getValueType(1));
26859 SDValue Res1 = DAG.getNode(ISD::AND, DL, VT,
26860 DAG.getNode(X86ISD::SETCC_CARRY, DL, VT,
26861 DAG.getConstant(X86::COND_B, DL,
26864 DAG.getConstant(1, DL, VT));
26865 return DCI.CombineTo(N, Res1, CarryOut);
26871 // fold (add Y, (sete X, 0)) -> adc 0, Y
26872 // (add Y, (setne X, 0)) -> sbb -1, Y
26873 // (sub (sete X, 0), Y) -> sbb 0, Y
26874 // (sub (setne X, 0), Y) -> adc -1, Y
26875 static SDValue OptimizeConditionalInDecrement(SDNode *N, SelectionDAG &DAG) {
26878 // Look through ZExts.
26879 SDValue Ext = N->getOperand(N->getOpcode() == ISD::SUB ? 1 : 0);
26880 if (Ext.getOpcode() != ISD::ZERO_EXTEND || !Ext.hasOneUse())
26883 SDValue SetCC = Ext.getOperand(0);
26884 if (SetCC.getOpcode() != X86ISD::SETCC || !SetCC.hasOneUse())
26887 X86::CondCode CC = (X86::CondCode)SetCC.getConstantOperandVal(0);
26888 if (CC != X86::COND_E && CC != X86::COND_NE)
26891 SDValue Cmp = SetCC.getOperand(1);
26892 if (Cmp.getOpcode() != X86ISD::CMP || !Cmp.hasOneUse() ||
26893 !X86::isZeroNode(Cmp.getOperand(1)) ||
26894 !Cmp.getOperand(0).getValueType().isInteger())
26897 SDValue CmpOp0 = Cmp.getOperand(0);
26898 SDValue NewCmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32, CmpOp0,
26899 DAG.getConstant(1, DL, CmpOp0.getValueType()));
26901 SDValue OtherVal = N->getOperand(N->getOpcode() == ISD::SUB ? 0 : 1);
26902 if (CC == X86::COND_NE)
26903 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::ADC : X86ISD::SBB,
26904 DL, OtherVal.getValueType(), OtherVal,
26905 DAG.getConstant(-1ULL, DL, OtherVal.getValueType()),
26907 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::SBB : X86ISD::ADC,
26908 DL, OtherVal.getValueType(), OtherVal,
26909 DAG.getConstant(0, DL, OtherVal.getValueType()), NewCmp);
26912 /// PerformADDCombine - Do target-specific dag combines on integer adds.
26913 static SDValue PerformAddCombine(SDNode *N, SelectionDAG &DAG,
26914 const X86Subtarget *Subtarget) {
26915 EVT VT = N->getValueType(0);
26916 SDValue Op0 = N->getOperand(0);
26917 SDValue Op1 = N->getOperand(1);
26919 // Try to synthesize horizontal adds from adds of shuffles.
26920 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) ||
26921 (Subtarget->hasInt256() && (VT == MVT::v16i16 || VT == MVT::v8i32))) &&
26922 isHorizontalBinOp(Op0, Op1, true))
26923 return DAG.getNode(X86ISD::HADD, SDLoc(N), VT, Op0, Op1);
26925 return OptimizeConditionalInDecrement(N, DAG);
26928 static SDValue PerformSubCombine(SDNode *N, SelectionDAG &DAG,
26929 const X86Subtarget *Subtarget) {
26930 SDValue Op0 = N->getOperand(0);
26931 SDValue Op1 = N->getOperand(1);
26933 // X86 can't encode an immediate LHS of a sub. See if we can push the
26934 // negation into a preceding instruction.
26935 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op0)) {
26936 // If the RHS of the sub is a XOR with one use and a constant, invert the
26937 // immediate. Then add one to the LHS of the sub so we can turn
26938 // X-Y -> X+~Y+1, saving one register.
26939 if (Op1->hasOneUse() && Op1.getOpcode() == ISD::XOR &&
26940 isa<ConstantSDNode>(Op1.getOperand(1))) {
26941 APInt XorC = cast<ConstantSDNode>(Op1.getOperand(1))->getAPIntValue();
26942 EVT VT = Op0.getValueType();
26943 SDValue NewXor = DAG.getNode(ISD::XOR, SDLoc(Op1), VT,
26945 DAG.getConstant(~XorC, SDLoc(Op1), VT));
26946 return DAG.getNode(ISD::ADD, SDLoc(N), VT, NewXor,
26947 DAG.getConstant(C->getAPIntValue() + 1, SDLoc(N), VT));
26951 // Try to synthesize horizontal adds from adds of shuffles.
26952 EVT VT = N->getValueType(0);
26953 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) ||
26954 (Subtarget->hasInt256() && (VT == MVT::v16i16 || VT == MVT::v8i32))) &&
26955 isHorizontalBinOp(Op0, Op1, true))
26956 return DAG.getNode(X86ISD::HSUB, SDLoc(N), VT, Op0, Op1);
26958 return OptimizeConditionalInDecrement(N, DAG);
26961 /// performVZEXTCombine - Performs build vector combines
26962 static SDValue performVZEXTCombine(SDNode *N, SelectionDAG &DAG,
26963 TargetLowering::DAGCombinerInfo &DCI,
26964 const X86Subtarget *Subtarget) {
26966 MVT VT = N->getSimpleValueType(0);
26967 SDValue Op = N->getOperand(0);
26968 MVT OpVT = Op.getSimpleValueType();
26969 MVT OpEltVT = OpVT.getVectorElementType();
26970 unsigned InputBits = OpEltVT.getSizeInBits() * VT.getVectorNumElements();
26972 // (vzext (bitcast (vzext (x)) -> (vzext x)
26974 while (V.getOpcode() == ISD::BITCAST)
26975 V = V.getOperand(0);
26977 if (V != Op && V.getOpcode() == X86ISD::VZEXT) {
26978 MVT InnerVT = V.getSimpleValueType();
26979 MVT InnerEltVT = InnerVT.getVectorElementType();
26981 // If the element sizes match exactly, we can just do one larger vzext. This
26982 // is always an exact type match as vzext operates on integer types.
26983 if (OpEltVT == InnerEltVT) {
26984 assert(OpVT == InnerVT && "Types must match for vzext!");
26985 return DAG.getNode(X86ISD::VZEXT, DL, VT, V.getOperand(0));
26988 // The only other way we can combine them is if only a single element of the
26989 // inner vzext is used in the input to the outer vzext.
26990 if (InnerEltVT.getSizeInBits() < InputBits)
26993 // In this case, the inner vzext is completely dead because we're going to
26994 // only look at bits inside of the low element. Just do the outer vzext on
26995 // a bitcast of the input to the inner.
26996 return DAG.getNode(X86ISD::VZEXT, DL, VT, DAG.getBitcast(OpVT, V));
26999 // Check if we can bypass extracting and re-inserting an element of an input
27000 // vector. Essentially:
27001 // (bitcast (sclr2vec (ext_vec_elt x))) -> (bitcast x)
27002 if (V.getOpcode() == ISD::SCALAR_TO_VECTOR &&
27003 V.getOperand(0).getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
27004 V.getOperand(0).getSimpleValueType().getSizeInBits() == InputBits) {
27005 SDValue ExtractedV = V.getOperand(0);
27006 SDValue OrigV = ExtractedV.getOperand(0);
27007 if (isNullConstant(ExtractedV.getOperand(1))) {
27008 MVT OrigVT = OrigV.getSimpleValueType();
27009 // Extract a subvector if necessary...
27010 if (OrigVT.getSizeInBits() > OpVT.getSizeInBits()) {
27011 int Ratio = OrigVT.getSizeInBits() / OpVT.getSizeInBits();
27012 OrigVT = MVT::getVectorVT(OrigVT.getVectorElementType(),
27013 OrigVT.getVectorNumElements() / Ratio);
27014 OrigV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, OrigVT, OrigV,
27015 DAG.getIntPtrConstant(0, DL));
27017 Op = DAG.getBitcast(OpVT, OrigV);
27018 return DAG.getNode(X86ISD::VZEXT, DL, VT, Op);
27025 SDValue X86TargetLowering::PerformDAGCombine(SDNode *N,
27026 DAGCombinerInfo &DCI) const {
27027 SelectionDAG &DAG = DCI.DAG;
27028 switch (N->getOpcode()) {
27030 case ISD::EXTRACT_VECTOR_ELT:
27031 return PerformEXTRACT_VECTOR_ELTCombine(N, DAG, DCI);
27034 case X86ISD::SHRUNKBLEND:
27035 return PerformSELECTCombine(N, DAG, DCI, Subtarget);
27036 case ISD::BITCAST: return PerformBITCASTCombine(N, DAG, Subtarget);
27037 case X86ISD::CMOV: return PerformCMOVCombine(N, DAG, DCI, Subtarget);
27038 case ISD::ADD: return PerformAddCombine(N, DAG, Subtarget);
27039 case ISD::SUB: return PerformSubCombine(N, DAG, Subtarget);
27040 case X86ISD::ADC: return PerformADCCombine(N, DAG, DCI);
27041 case ISD::MUL: return PerformMulCombine(N, DAG, DCI);
27044 case ISD::SRL: return PerformShiftCombine(N, DAG, DCI, Subtarget);
27045 case ISD::AND: return PerformAndCombine(N, DAG, DCI, Subtarget);
27046 case ISD::OR: return PerformOrCombine(N, DAG, DCI, Subtarget);
27047 case ISD::XOR: return PerformXorCombine(N, DAG, DCI, Subtarget);
27048 case ISD::LOAD: return PerformLOADCombine(N, DAG, DCI, Subtarget);
27049 case ISD::MLOAD: return PerformMLOADCombine(N, DAG, DCI, Subtarget);
27050 case ISD::STORE: return PerformSTORECombine(N, DAG, Subtarget);
27051 case ISD::MSTORE: return PerformMSTORECombine(N, DAG, Subtarget);
27052 case ISD::SINT_TO_FP: return PerformSINT_TO_FPCombine(N, DAG, Subtarget);
27053 case ISD::UINT_TO_FP: return PerformUINT_TO_FPCombine(N, DAG, Subtarget);
27054 case ISD::FADD: return PerformFADDCombine(N, DAG, Subtarget);
27055 case ISD::FSUB: return PerformFSUBCombine(N, DAG, Subtarget);
27056 case ISD::FNEG: return PerformFNEGCombine(N, DAG, Subtarget);
27057 case ISD::TRUNCATE: return PerformTRUNCATECombine(N, DAG, Subtarget);
27059 case X86ISD::FOR: return PerformFORCombine(N, DAG, Subtarget);
27061 case X86ISD::FMAX: return PerformFMinFMaxCombine(N, DAG);
27062 case X86ISD::FAND: return PerformFANDCombine(N, DAG);
27063 case X86ISD::FANDN: return PerformFANDNCombine(N, DAG);
27064 case X86ISD::BT: return PerformBTCombine(N, DAG, DCI);
27065 case X86ISD::VZEXT_MOVL: return PerformVZEXT_MOVLCombine(N, DAG);
27066 case ISD::ANY_EXTEND:
27067 case ISD::ZERO_EXTEND: return PerformZExtCombine(N, DAG, DCI, Subtarget);
27068 case ISD::SIGN_EXTEND: return PerformSExtCombine(N, DAG, DCI, Subtarget);
27069 case ISD::SIGN_EXTEND_INREG:
27070 return PerformSIGN_EXTEND_INREGCombine(N, DAG, Subtarget);
27071 case ISD::SETCC: return PerformISDSETCCCombine(N, DAG, Subtarget);
27072 case X86ISD::SETCC: return PerformSETCCCombine(N, DAG, DCI, Subtarget);
27073 case X86ISD::BRCOND: return PerformBrCondCombine(N, DAG, DCI, Subtarget);
27074 case X86ISD::VZEXT: return performVZEXTCombine(N, DAG, DCI, Subtarget);
27075 case X86ISD::SHUFP: // Handle all target specific shuffles
27076 case X86ISD::PALIGNR:
27077 case X86ISD::UNPCKH:
27078 case X86ISD::UNPCKL:
27079 case X86ISD::MOVHLPS:
27080 case X86ISD::MOVLHPS:
27081 case X86ISD::PSHUFB:
27082 case X86ISD::PSHUFD:
27083 case X86ISD::PSHUFHW:
27084 case X86ISD::PSHUFLW:
27085 case X86ISD::MOVSS:
27086 case X86ISD::MOVSD:
27087 case X86ISD::VPERMILPI:
27088 case X86ISD::VPERM2X128:
27089 case ISD::VECTOR_SHUFFLE: return PerformShuffleCombine(N, DAG, DCI,Subtarget);
27090 case ISD::FMA: return PerformFMACombine(N, DAG, Subtarget);
27091 case X86ISD::BLENDI: return PerformBLENDICombine(N, DAG);
27097 /// isTypeDesirableForOp - Return true if the target has native support for
27098 /// the specified value type and it is 'desirable' to use the type for the
27099 /// given node type. e.g. On x86 i16 is legal, but undesirable since i16
27100 /// instruction encodings are longer and some i16 instructions are slow.
27101 bool X86TargetLowering::isTypeDesirableForOp(unsigned Opc, EVT VT) const {
27102 if (!isTypeLegal(VT))
27104 if (VT != MVT::i16)
27111 case ISD::SIGN_EXTEND:
27112 case ISD::ZERO_EXTEND:
27113 case ISD::ANY_EXTEND:
27126 /// IsDesirableToPromoteOp - This method query the target whether it is
27127 /// beneficial for dag combiner to promote the specified node. If true, it
27128 /// should return the desired promotion type by reference.
27129 bool X86TargetLowering::IsDesirableToPromoteOp(SDValue Op, EVT &PVT) const {
27130 EVT VT = Op.getValueType();
27131 if (VT != MVT::i16)
27134 bool Promote = false;
27135 bool Commute = false;
27136 switch (Op.getOpcode()) {
27139 LoadSDNode *LD = cast<LoadSDNode>(Op);
27140 // If the non-extending load has a single use and it's not live out, then it
27141 // might be folded.
27142 if (LD->getExtensionType() == ISD::NON_EXTLOAD /*&&
27143 Op.hasOneUse()*/) {
27144 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
27145 UE = Op.getNode()->use_end(); UI != UE; ++UI) {
27146 // The only case where we'd want to promote LOAD (rather then it being
27147 // promoted as an operand is when it's only use is liveout.
27148 if (UI->getOpcode() != ISD::CopyToReg)
27155 case ISD::SIGN_EXTEND:
27156 case ISD::ZERO_EXTEND:
27157 case ISD::ANY_EXTEND:
27162 SDValue N0 = Op.getOperand(0);
27163 // Look out for (store (shl (load), x)).
27164 if (MayFoldLoad(N0) && MayFoldIntoStore(Op))
27177 SDValue N0 = Op.getOperand(0);
27178 SDValue N1 = Op.getOperand(1);
27179 if (!Commute && MayFoldLoad(N1))
27181 // Avoid disabling potential load folding opportunities.
27182 if (MayFoldLoad(N0) && (!isa<ConstantSDNode>(N1) || MayFoldIntoStore(Op)))
27184 if (MayFoldLoad(N1) && (!isa<ConstantSDNode>(N0) || MayFoldIntoStore(Op)))
27194 //===----------------------------------------------------------------------===//
27195 // X86 Inline Assembly Support
27196 //===----------------------------------------------------------------------===//
27198 // Helper to match a string separated by whitespace.
27199 static bool matchAsm(StringRef S, ArrayRef<const char *> Pieces) {
27200 S = S.substr(S.find_first_not_of(" \t")); // Skip leading whitespace.
27202 for (StringRef Piece : Pieces) {
27203 if (!S.startswith(Piece)) // Check if the piece matches.
27206 S = S.substr(Piece.size());
27207 StringRef::size_type Pos = S.find_first_not_of(" \t");
27208 if (Pos == 0) // We matched a prefix.
27217 static bool clobbersFlagRegisters(const SmallVector<StringRef, 4> &AsmPieces) {
27219 if (AsmPieces.size() == 3 || AsmPieces.size() == 4) {
27220 if (std::count(AsmPieces.begin(), AsmPieces.end(), "~{cc}") &&
27221 std::count(AsmPieces.begin(), AsmPieces.end(), "~{flags}") &&
27222 std::count(AsmPieces.begin(), AsmPieces.end(), "~{fpsr}")) {
27224 if (AsmPieces.size() == 3)
27226 else if (std::count(AsmPieces.begin(), AsmPieces.end(), "~{dirflag}"))
27233 bool X86TargetLowering::ExpandInlineAsm(CallInst *CI) const {
27234 InlineAsm *IA = cast<InlineAsm>(CI->getCalledValue());
27236 std::string AsmStr = IA->getAsmString();
27238 IntegerType *Ty = dyn_cast<IntegerType>(CI->getType());
27239 if (!Ty || Ty->getBitWidth() % 16 != 0)
27242 // TODO: should remove alternatives from the asmstring: "foo {a|b}" -> "foo a"
27243 SmallVector<StringRef, 4> AsmPieces;
27244 SplitString(AsmStr, AsmPieces, ";\n");
27246 switch (AsmPieces.size()) {
27247 default: return false;
27249 // FIXME: this should verify that we are targeting a 486 or better. If not,
27250 // we will turn this bswap into something that will be lowered to logical
27251 // ops instead of emitting the bswap asm. For now, we don't support 486 or
27252 // lower so don't worry about this.
27254 if (matchAsm(AsmPieces[0], {"bswap", "$0"}) ||
27255 matchAsm(AsmPieces[0], {"bswapl", "$0"}) ||
27256 matchAsm(AsmPieces[0], {"bswapq", "$0"}) ||
27257 matchAsm(AsmPieces[0], {"bswap", "${0:q}"}) ||
27258 matchAsm(AsmPieces[0], {"bswapl", "${0:q}"}) ||
27259 matchAsm(AsmPieces[0], {"bswapq", "${0:q}"})) {
27260 // No need to check constraints, nothing other than the equivalent of
27261 // "=r,0" would be valid here.
27262 return IntrinsicLowering::LowerToByteSwap(CI);
27265 // rorw $$8, ${0:w} --> llvm.bswap.i16
27266 if (CI->getType()->isIntegerTy(16) &&
27267 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 &&
27268 (matchAsm(AsmPieces[0], {"rorw", "$$8,", "${0:w}"}) ||
27269 matchAsm(AsmPieces[0], {"rolw", "$$8,", "${0:w}"}))) {
27271 StringRef ConstraintsStr = IA->getConstraintString();
27272 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
27273 array_pod_sort(AsmPieces.begin(), AsmPieces.end());
27274 if (clobbersFlagRegisters(AsmPieces))
27275 return IntrinsicLowering::LowerToByteSwap(CI);
27279 if (CI->getType()->isIntegerTy(32) &&
27280 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 &&
27281 matchAsm(AsmPieces[0], {"rorw", "$$8,", "${0:w}"}) &&
27282 matchAsm(AsmPieces[1], {"rorl", "$$16,", "$0"}) &&
27283 matchAsm(AsmPieces[2], {"rorw", "$$8,", "${0:w}"})) {
27285 StringRef ConstraintsStr = IA->getConstraintString();
27286 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
27287 array_pod_sort(AsmPieces.begin(), AsmPieces.end());
27288 if (clobbersFlagRegisters(AsmPieces))
27289 return IntrinsicLowering::LowerToByteSwap(CI);
27292 if (CI->getType()->isIntegerTy(64)) {
27293 InlineAsm::ConstraintInfoVector Constraints = IA->ParseConstraints();
27294 if (Constraints.size() >= 2 &&
27295 Constraints[0].Codes.size() == 1 && Constraints[0].Codes[0] == "A" &&
27296 Constraints[1].Codes.size() == 1 && Constraints[1].Codes[0] == "0") {
27297 // bswap %eax / bswap %edx / xchgl %eax, %edx -> llvm.bswap.i64
27298 if (matchAsm(AsmPieces[0], {"bswap", "%eax"}) &&
27299 matchAsm(AsmPieces[1], {"bswap", "%edx"}) &&
27300 matchAsm(AsmPieces[2], {"xchgl", "%eax,", "%edx"}))
27301 return IntrinsicLowering::LowerToByteSwap(CI);
27309 /// getConstraintType - Given a constraint letter, return the type of
27310 /// constraint it is for this target.
27311 X86TargetLowering::ConstraintType
27312 X86TargetLowering::getConstraintType(StringRef Constraint) const {
27313 if (Constraint.size() == 1) {
27314 switch (Constraint[0]) {
27325 return C_RegisterClass;
27349 return TargetLowering::getConstraintType(Constraint);
27352 /// Examine constraint type and operand type and determine a weight value.
27353 /// This object must already have been set up with the operand type
27354 /// and the current alternative constraint selected.
27355 TargetLowering::ConstraintWeight
27356 X86TargetLowering::getSingleConstraintMatchWeight(
27357 AsmOperandInfo &info, const char *constraint) const {
27358 ConstraintWeight weight = CW_Invalid;
27359 Value *CallOperandVal = info.CallOperandVal;
27360 // If we don't have a value, we can't do a match,
27361 // but allow it at the lowest weight.
27362 if (!CallOperandVal)
27364 Type *type = CallOperandVal->getType();
27365 // Look at the constraint type.
27366 switch (*constraint) {
27368 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
27379 if (CallOperandVal->getType()->isIntegerTy())
27380 weight = CW_SpecificReg;
27385 if (type->isFloatingPointTy())
27386 weight = CW_SpecificReg;
27389 if (type->isX86_MMXTy() && Subtarget->hasMMX())
27390 weight = CW_SpecificReg;
27394 if (((type->getPrimitiveSizeInBits() == 128) && Subtarget->hasSSE1()) ||
27395 ((type->getPrimitiveSizeInBits() == 256) && Subtarget->hasFp256()))
27396 weight = CW_Register;
27399 if (ConstantInt *C = dyn_cast<ConstantInt>(info.CallOperandVal)) {
27400 if (C->getZExtValue() <= 31)
27401 weight = CW_Constant;
27405 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
27406 if (C->getZExtValue() <= 63)
27407 weight = CW_Constant;
27411 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
27412 if ((C->getSExtValue() >= -0x80) && (C->getSExtValue() <= 0x7f))
27413 weight = CW_Constant;
27417 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
27418 if ((C->getZExtValue() == 0xff) || (C->getZExtValue() == 0xffff))
27419 weight = CW_Constant;
27423 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
27424 if (C->getZExtValue() <= 3)
27425 weight = CW_Constant;
27429 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
27430 if (C->getZExtValue() <= 0xff)
27431 weight = CW_Constant;
27436 if (isa<ConstantFP>(CallOperandVal)) {
27437 weight = CW_Constant;
27441 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
27442 if ((C->getSExtValue() >= -0x80000000LL) &&
27443 (C->getSExtValue() <= 0x7fffffffLL))
27444 weight = CW_Constant;
27448 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
27449 if (C->getZExtValue() <= 0xffffffff)
27450 weight = CW_Constant;
27457 /// LowerXConstraint - try to replace an X constraint, which matches anything,
27458 /// with another that has more specific requirements based on the type of the
27459 /// corresponding operand.
27460 const char *X86TargetLowering::
27461 LowerXConstraint(EVT ConstraintVT) const {
27462 // FP X constraints get lowered to SSE1/2 registers if available, otherwise
27463 // 'f' like normal targets.
27464 if (ConstraintVT.isFloatingPoint()) {
27465 if (Subtarget->hasSSE2())
27467 if (Subtarget->hasSSE1())
27471 return TargetLowering::LowerXConstraint(ConstraintVT);
27474 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
27475 /// vector. If it is invalid, don't add anything to Ops.
27476 void X86TargetLowering::LowerAsmOperandForConstraint(SDValue Op,
27477 std::string &Constraint,
27478 std::vector<SDValue>&Ops,
27479 SelectionDAG &DAG) const {
27482 // Only support length 1 constraints for now.
27483 if (Constraint.length() > 1) return;
27485 char ConstraintLetter = Constraint[0];
27486 switch (ConstraintLetter) {
27489 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
27490 if (C->getZExtValue() <= 31) {
27491 Result = DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op),
27492 Op.getValueType());
27498 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
27499 if (C->getZExtValue() <= 63) {
27500 Result = DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op),
27501 Op.getValueType());
27507 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
27508 if (isInt<8>(C->getSExtValue())) {
27509 Result = DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op),
27510 Op.getValueType());
27516 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
27517 if (C->getZExtValue() == 0xff || C->getZExtValue() == 0xffff ||
27518 (Subtarget->is64Bit() && C->getZExtValue() == 0xffffffff)) {
27519 Result = DAG.getTargetConstant(C->getSExtValue(), SDLoc(Op),
27520 Op.getValueType());
27526 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
27527 if (C->getZExtValue() <= 3) {
27528 Result = DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op),
27529 Op.getValueType());
27535 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
27536 if (C->getZExtValue() <= 255) {
27537 Result = DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op),
27538 Op.getValueType());
27544 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
27545 if (C->getZExtValue() <= 127) {
27546 Result = DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op),
27547 Op.getValueType());
27553 // 32-bit signed value
27554 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
27555 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
27556 C->getSExtValue())) {
27557 // Widen to 64 bits here to get it sign extended.
27558 Result = DAG.getTargetConstant(C->getSExtValue(), SDLoc(Op), MVT::i64);
27561 // FIXME gcc accepts some relocatable values here too, but only in certain
27562 // memory models; it's complicated.
27567 // 32-bit unsigned value
27568 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
27569 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
27570 C->getZExtValue())) {
27571 Result = DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op),
27572 Op.getValueType());
27576 // FIXME gcc accepts some relocatable values here too, but only in certain
27577 // memory models; it's complicated.
27581 // Literal immediates are always ok.
27582 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op)) {
27583 // Widen to 64 bits here to get it sign extended.
27584 Result = DAG.getTargetConstant(CST->getSExtValue(), SDLoc(Op), MVT::i64);
27588 // In any sort of PIC mode addresses need to be computed at runtime by
27589 // adding in a register or some sort of table lookup. These can't
27590 // be used as immediates.
27591 if (Subtarget->isPICStyleGOT() || Subtarget->isPICStyleStubPIC())
27594 // If we are in non-pic codegen mode, we allow the address of a global (with
27595 // an optional displacement) to be used with 'i'.
27596 GlobalAddressSDNode *GA = nullptr;
27597 int64_t Offset = 0;
27599 // Match either (GA), (GA+C), (GA+C1+C2), etc.
27601 if ((GA = dyn_cast<GlobalAddressSDNode>(Op))) {
27602 Offset += GA->getOffset();
27604 } else if (Op.getOpcode() == ISD::ADD) {
27605 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
27606 Offset += C->getZExtValue();
27607 Op = Op.getOperand(0);
27610 } else if (Op.getOpcode() == ISD::SUB) {
27611 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
27612 Offset += -C->getZExtValue();
27613 Op = Op.getOperand(0);
27618 // Otherwise, this isn't something we can handle, reject it.
27622 const GlobalValue *GV = GA->getGlobal();
27623 // If we require an extra load to get this address, as in PIC mode, we
27624 // can't accept it.
27625 if (isGlobalStubReference(
27626 Subtarget->ClassifyGlobalReference(GV, DAG.getTarget())))
27629 Result = DAG.getTargetGlobalAddress(GV, SDLoc(Op),
27630 GA->getValueType(0), Offset);
27635 if (Result.getNode()) {
27636 Ops.push_back(Result);
27639 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
27642 std::pair<unsigned, const TargetRegisterClass *>
27643 X86TargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
27644 StringRef Constraint,
27646 // First, see if this is a constraint that directly corresponds to an LLVM
27648 if (Constraint.size() == 1) {
27649 // GCC Constraint Letters
27650 switch (Constraint[0]) {
27652 // TODO: Slight differences here in allocation order and leaving
27653 // RIP in the class. Do they matter any more here than they do
27654 // in the normal allocation?
27655 case 'q': // GENERAL_REGS in 64-bit mode, Q_REGS in 32-bit mode.
27656 if (Subtarget->is64Bit()) {
27657 if (VT == MVT::i32 || VT == MVT::f32)
27658 return std::make_pair(0U, &X86::GR32RegClass);
27659 if (VT == MVT::i16)
27660 return std::make_pair(0U, &X86::GR16RegClass);
27661 if (VT == MVT::i8 || VT == MVT::i1)
27662 return std::make_pair(0U, &X86::GR8RegClass);
27663 if (VT == MVT::i64 || VT == MVT::f64)
27664 return std::make_pair(0U, &X86::GR64RegClass);
27667 // 32-bit fallthrough
27668 case 'Q': // Q_REGS
27669 if (VT == MVT::i32 || VT == MVT::f32)
27670 return std::make_pair(0U, &X86::GR32_ABCDRegClass);
27671 if (VT == MVT::i16)
27672 return std::make_pair(0U, &X86::GR16_ABCDRegClass);
27673 if (VT == MVT::i8 || VT == MVT::i1)
27674 return std::make_pair(0U, &X86::GR8_ABCD_LRegClass);
27675 if (VT == MVT::i64)
27676 return std::make_pair(0U, &X86::GR64_ABCDRegClass);
27678 case 'r': // GENERAL_REGS
27679 case 'l': // INDEX_REGS
27680 if (VT == MVT::i8 || VT == MVT::i1)
27681 return std::make_pair(0U, &X86::GR8RegClass);
27682 if (VT == MVT::i16)
27683 return std::make_pair(0U, &X86::GR16RegClass);
27684 if (VT == MVT::i32 || VT == MVT::f32 || !Subtarget->is64Bit())
27685 return std::make_pair(0U, &X86::GR32RegClass);
27686 return std::make_pair(0U, &X86::GR64RegClass);
27687 case 'R': // LEGACY_REGS
27688 if (VT == MVT::i8 || VT == MVT::i1)
27689 return std::make_pair(0U, &X86::GR8_NOREXRegClass);
27690 if (VT == MVT::i16)
27691 return std::make_pair(0U, &X86::GR16_NOREXRegClass);
27692 if (VT == MVT::i32 || !Subtarget->is64Bit())
27693 return std::make_pair(0U, &X86::GR32_NOREXRegClass);
27694 return std::make_pair(0U, &X86::GR64_NOREXRegClass);
27695 case 'f': // FP Stack registers.
27696 // If SSE is enabled for this VT, use f80 to ensure the isel moves the
27697 // value to the correct fpstack register class.
27698 if (VT == MVT::f32 && !isScalarFPTypeInSSEReg(VT))
27699 return std::make_pair(0U, &X86::RFP32RegClass);
27700 if (VT == MVT::f64 && !isScalarFPTypeInSSEReg(VT))
27701 return std::make_pair(0U, &X86::RFP64RegClass);
27702 return std::make_pair(0U, &X86::RFP80RegClass);
27703 case 'y': // MMX_REGS if MMX allowed.
27704 if (!Subtarget->hasMMX()) break;
27705 return std::make_pair(0U, &X86::VR64RegClass);
27706 case 'Y': // SSE_REGS if SSE2 allowed
27707 if (!Subtarget->hasSSE2()) break;
27709 case 'x': // SSE_REGS if SSE1 allowed or AVX_REGS if AVX allowed
27710 if (!Subtarget->hasSSE1()) break;
27712 switch (VT.SimpleTy) {
27714 // Scalar SSE types.
27717 return std::make_pair(0U, &X86::FR32RegClass);
27720 return std::make_pair(0U, &X86::FR64RegClass);
27728 return std::make_pair(0U, &X86::VR128RegClass);
27736 return std::make_pair(0U, &X86::VR256RegClass);
27741 return std::make_pair(0U, &X86::VR512RegClass);
27747 // Use the default implementation in TargetLowering to convert the register
27748 // constraint into a member of a register class.
27749 std::pair<unsigned, const TargetRegisterClass*> Res;
27750 Res = TargetLowering::getRegForInlineAsmConstraint(TRI, Constraint, VT);
27752 // Not found as a standard register?
27754 // Map st(0) -> st(7) -> ST0
27755 if (Constraint.size() == 7 && Constraint[0] == '{' &&
27756 tolower(Constraint[1]) == 's' &&
27757 tolower(Constraint[2]) == 't' &&
27758 Constraint[3] == '(' &&
27759 (Constraint[4] >= '0' && Constraint[4] <= '7') &&
27760 Constraint[5] == ')' &&
27761 Constraint[6] == '}') {
27763 Res.first = X86::FP0+Constraint[4]-'0';
27764 Res.second = &X86::RFP80RegClass;
27768 // GCC allows "st(0)" to be called just plain "st".
27769 if (StringRef("{st}").equals_lower(Constraint)) {
27770 Res.first = X86::FP0;
27771 Res.second = &X86::RFP80RegClass;
27776 if (StringRef("{flags}").equals_lower(Constraint)) {
27777 Res.first = X86::EFLAGS;
27778 Res.second = &X86::CCRRegClass;
27782 // 'A' means EAX + EDX.
27783 if (Constraint == "A") {
27784 Res.first = X86::EAX;
27785 Res.second = &X86::GR32_ADRegClass;
27791 // Otherwise, check to see if this is a register class of the wrong value
27792 // type. For example, we want to map "{ax},i32" -> {eax}, we don't want it to
27793 // turn into {ax},{dx}.
27794 // MVT::Other is used to specify clobber names.
27795 if (Res.second->hasType(VT) || VT == MVT::Other)
27796 return Res; // Correct type already, nothing to do.
27798 // Get a matching integer of the correct size. i.e. "ax" with MVT::32 should
27799 // return "eax". This should even work for things like getting 64bit integer
27800 // registers when given an f64 type.
27801 const TargetRegisterClass *Class = Res.second;
27802 if (Class == &X86::GR8RegClass || Class == &X86::GR16RegClass ||
27803 Class == &X86::GR32RegClass || Class == &X86::GR64RegClass) {
27804 unsigned Size = VT.getSizeInBits();
27805 MVT::SimpleValueType SimpleTy = Size == 1 || Size == 8 ? MVT::i8
27806 : Size == 16 ? MVT::i16
27807 : Size == 32 ? MVT::i32
27808 : Size == 64 ? MVT::i64
27810 unsigned DestReg = getX86SubSuperRegisterOrZero(Res.first, SimpleTy);
27812 Res.first = DestReg;
27813 Res.second = SimpleTy == MVT::i8 ? &X86::GR8RegClass
27814 : SimpleTy == MVT::i16 ? &X86::GR16RegClass
27815 : SimpleTy == MVT::i32 ? &X86::GR32RegClass
27816 : &X86::GR64RegClass;
27817 assert(Res.second->contains(Res.first) && "Register in register class");
27819 // No register found/type mismatch.
27821 Res.second = nullptr;
27823 } else if (Class == &X86::FR32RegClass || Class == &X86::FR64RegClass ||
27824 Class == &X86::VR128RegClass || Class == &X86::VR256RegClass ||
27825 Class == &X86::FR32XRegClass || Class == &X86::FR64XRegClass ||
27826 Class == &X86::VR128XRegClass || Class == &X86::VR256XRegClass ||
27827 Class == &X86::VR512RegClass) {
27828 // Handle references to XMM physical registers that got mapped into the
27829 // wrong class. This can happen with constraints like {xmm0} where the
27830 // target independent register mapper will just pick the first match it can
27831 // find, ignoring the required type.
27833 if (VT == MVT::f32 || VT == MVT::i32)
27834 Res.second = &X86::FR32RegClass;
27835 else if (VT == MVT::f64 || VT == MVT::i64)
27836 Res.second = &X86::FR64RegClass;
27837 else if (X86::VR128RegClass.hasType(VT))
27838 Res.second = &X86::VR128RegClass;
27839 else if (X86::VR256RegClass.hasType(VT))
27840 Res.second = &X86::VR256RegClass;
27841 else if (X86::VR512RegClass.hasType(VT))
27842 Res.second = &X86::VR512RegClass;
27844 // Type mismatch and not a clobber: Return an error;
27846 Res.second = nullptr;
27853 int X86TargetLowering::getScalingFactorCost(const DataLayout &DL,
27854 const AddrMode &AM, Type *Ty,
27855 unsigned AS) const {
27856 // Scaling factors are not free at all.
27857 // An indexed folded instruction, i.e., inst (reg1, reg2, scale),
27858 // will take 2 allocations in the out of order engine instead of 1
27859 // for plain addressing mode, i.e. inst (reg1).
27861 // vaddps (%rsi,%drx), %ymm0, %ymm1
27862 // Requires two allocations (one for the load, one for the computation)
27864 // vaddps (%rsi), %ymm0, %ymm1
27865 // Requires just 1 allocation, i.e., freeing allocations for other operations
27866 // and having less micro operations to execute.
27868 // For some X86 architectures, this is even worse because for instance for
27869 // stores, the complex addressing mode forces the instruction to use the
27870 // "load" ports instead of the dedicated "store" port.
27871 // E.g., on Haswell:
27872 // vmovaps %ymm1, (%r8, %rdi) can use port 2 or 3.
27873 // vmovaps %ymm1, (%r8) can use port 2, 3, or 7.
27874 if (isLegalAddressingMode(DL, AM, Ty, AS))
27875 // Scale represents reg2 * scale, thus account for 1
27876 // as soon as we use a second register.
27877 return AM.Scale != 0;
27881 bool X86TargetLowering::isIntDivCheap(EVT VT, AttributeSet Attr) const {
27882 // Integer division on x86 is expensive. However, when aggressively optimizing
27883 // for code size, we prefer to use a div instruction, as it is usually smaller
27884 // than the alternative sequence.
27885 // The exception to this is vector division. Since x86 doesn't have vector
27886 // integer division, leaving the division as-is is a loss even in terms of
27887 // size, because it will have to be scalarized, while the alternative code
27888 // sequence can be performed in vector form.
27889 bool OptSize = Attr.hasAttribute(AttributeSet::FunctionIndex,
27890 Attribute::MinSize);
27891 return OptSize && !VT.isVector();
27894 void X86TargetLowering::markInRegArguments(SelectionDAG &DAG,
27895 TargetLowering::ArgListTy& Args) const {
27896 // The MCU psABI requires some arguments to be passed in-register.
27897 // For regular calls, the inreg arguments are marked by the front-end.
27898 // However, for compiler generated library calls, we have to patch this
27900 if (!Subtarget->isTargetMCU() || !Args.size())
27903 unsigned FreeRegs = 3;
27904 for (auto &Arg : Args) {
27905 // For library functions, we do not expect any fancy types.
27906 unsigned Size = DAG.getDataLayout().getTypeSizeInBits(Arg.Ty);
27907 unsigned SizeInRegs = (Size + 31) / 32;
27908 if (SizeInRegs > 2 || SizeInRegs > FreeRegs)
27911 Arg.isInReg = true;
27912 FreeRegs -= SizeInRegs;