1 //===-- X86ISelLowering.cpp - X86 DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that X86 uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
16 #include "X86InstrBuilder.h"
17 #include "X86ISelLowering.h"
18 #include "X86MachineFunctionInfo.h"
19 #include "X86TargetMachine.h"
20 #include "llvm/CallingConv.h"
21 #include "llvm/Constants.h"
22 #include "llvm/DerivedTypes.h"
23 #include "llvm/GlobalVariable.h"
24 #include "llvm/Function.h"
25 #include "llvm/Intrinsics.h"
26 #include "llvm/ADT/BitVector.h"
27 #include "llvm/ADT/VectorExtras.h"
28 #include "llvm/CodeGen/CallingConvLower.h"
29 #include "llvm/CodeGen/MachineFrameInfo.h"
30 #include "llvm/CodeGen/MachineFunction.h"
31 #include "llvm/CodeGen/MachineInstrBuilder.h"
32 #include "llvm/CodeGen/MachineModuleInfo.h"
33 #include "llvm/CodeGen/MachineRegisterInfo.h"
34 #include "llvm/CodeGen/PseudoSourceValue.h"
35 #include "llvm/CodeGen/SelectionDAG.h"
36 #include "llvm/Support/MathExtras.h"
37 #include "llvm/Support/Debug.h"
38 #include "llvm/Target/TargetOptions.h"
39 #include "llvm/ADT/SmallSet.h"
40 #include "llvm/ADT/StringExtras.h"
43 // Forward declarations.
44 static SDValue getMOVLMask(unsigned NumElems, SelectionDAG &DAG);
46 X86TargetLowering::X86TargetLowering(X86TargetMachine &TM)
47 : TargetLowering(TM) {
48 Subtarget = &TM.getSubtarget<X86Subtarget>();
49 X86ScalarSSEf64 = Subtarget->hasSSE2();
50 X86ScalarSSEf32 = Subtarget->hasSSE1();
51 X86StackPtr = Subtarget->is64Bit() ? X86::RSP : X86::ESP;
55 RegInfo = TM.getRegisterInfo();
58 // Set up the TargetLowering object.
60 // X86 is weird, it always uses i8 for shift amounts and setcc results.
61 setShiftAmountType(MVT::i8);
62 setSetCCResultContents(ZeroOrOneSetCCResult);
63 setSchedulingPreference(SchedulingForRegPressure);
64 setShiftAmountFlavor(Mask); // shl X, 32 == shl X, 0
65 setStackPointerRegisterToSaveRestore(X86StackPtr);
67 if (Subtarget->isTargetDarwin()) {
68 // Darwin should use _setjmp/_longjmp instead of setjmp/longjmp.
69 setUseUnderscoreSetJmp(false);
70 setUseUnderscoreLongJmp(false);
71 } else if (Subtarget->isTargetMingw()) {
72 // MS runtime is weird: it exports _setjmp, but longjmp!
73 setUseUnderscoreSetJmp(true);
74 setUseUnderscoreLongJmp(false);
76 setUseUnderscoreSetJmp(true);
77 setUseUnderscoreLongJmp(true);
80 // Set up the register classes.
81 addRegisterClass(MVT::i8, X86::GR8RegisterClass);
82 addRegisterClass(MVT::i16, X86::GR16RegisterClass);
83 addRegisterClass(MVT::i32, X86::GR32RegisterClass);
84 if (Subtarget->is64Bit())
85 addRegisterClass(MVT::i64, X86::GR64RegisterClass);
87 setLoadXAction(ISD::SEXTLOAD, MVT::i1, Promote);
89 // We don't accept any truncstore of integer registers.
90 setTruncStoreAction(MVT::i64, MVT::i32, Expand);
91 setTruncStoreAction(MVT::i64, MVT::i16, Expand);
92 setTruncStoreAction(MVT::i64, MVT::i8 , Expand);
93 setTruncStoreAction(MVT::i32, MVT::i16, Expand);
94 setTruncStoreAction(MVT::i32, MVT::i8 , Expand);
95 setTruncStoreAction(MVT::i16, MVT::i8, Expand);
97 // Promote all UINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have this
99 setOperationAction(ISD::UINT_TO_FP , MVT::i1 , Promote);
100 setOperationAction(ISD::UINT_TO_FP , MVT::i8 , Promote);
101 setOperationAction(ISD::UINT_TO_FP , MVT::i16 , Promote);
103 if (Subtarget->is64Bit()) {
104 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Expand);
105 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote);
108 // If SSE i64 SINT_TO_FP is not available, expand i32 UINT_TO_FP.
109 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Expand);
111 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote);
114 // Promote i1/i8 SINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have
116 setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote);
117 setOperationAction(ISD::SINT_TO_FP , MVT::i8 , Promote);
118 // SSE has no i16 to fp conversion, only i32
119 if (X86ScalarSSEf32) {
120 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
121 // f32 and f64 cases are Legal, f80 case is not
122 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
124 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Custom);
125 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
128 // In 32-bit mode these are custom lowered. In 64-bit mode F32 and F64
129 // are Legal, f80 is custom lowered.
130 setOperationAction(ISD::FP_TO_SINT , MVT::i64 , Custom);
131 setOperationAction(ISD::SINT_TO_FP , MVT::i64 , Custom);
133 // Promote i1/i8 FP_TO_SINT to larger FP_TO_SINTS's, as X86 doesn't have
135 setOperationAction(ISD::FP_TO_SINT , MVT::i1 , Promote);
136 setOperationAction(ISD::FP_TO_SINT , MVT::i8 , Promote);
138 if (X86ScalarSSEf32) {
139 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Promote);
140 // f32 and f64 cases are Legal, f80 case is not
141 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
143 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Custom);
144 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
147 // Handle FP_TO_UINT by promoting the destination to a larger signed
149 setOperationAction(ISD::FP_TO_UINT , MVT::i1 , Promote);
150 setOperationAction(ISD::FP_TO_UINT , MVT::i8 , Promote);
151 setOperationAction(ISD::FP_TO_UINT , MVT::i16 , Promote);
153 if (Subtarget->is64Bit()) {
154 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Expand);
155 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote);
157 if (X86ScalarSSEf32 && !Subtarget->hasSSE3())
158 // Expand FP_TO_UINT into a select.
159 // FIXME: We would like to use a Custom expander here eventually to do
160 // the optimal thing for SSE vs. the default expansion in the legalizer.
161 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Expand);
163 // With SSE3 we can use fisttpll to convert to a signed i64.
164 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote);
167 // TODO: when we have SSE, these could be more efficient, by using movd/movq.
168 if (!X86ScalarSSEf64) {
169 setOperationAction(ISD::BIT_CONVERT , MVT::f32 , Expand);
170 setOperationAction(ISD::BIT_CONVERT , MVT::i32 , Expand);
173 // Scalar integer divide and remainder are lowered to use operations that
174 // produce two results, to match the available instructions. This exposes
175 // the two-result form to trivial CSE, which is able to combine x/y and x%y
176 // into a single instruction.
178 // Scalar integer multiply-high is also lowered to use two-result
179 // operations, to match the available instructions. However, plain multiply
180 // (low) operations are left as Legal, as there are single-result
181 // instructions for this in x86. Using the two-result multiply instructions
182 // when both high and low results are needed must be arranged by dagcombine.
183 setOperationAction(ISD::MULHS , MVT::i8 , Expand);
184 setOperationAction(ISD::MULHU , MVT::i8 , Expand);
185 setOperationAction(ISD::SDIV , MVT::i8 , Expand);
186 setOperationAction(ISD::UDIV , MVT::i8 , Expand);
187 setOperationAction(ISD::SREM , MVT::i8 , Expand);
188 setOperationAction(ISD::UREM , MVT::i8 , Expand);
189 setOperationAction(ISD::MULHS , MVT::i16 , Expand);
190 setOperationAction(ISD::MULHU , MVT::i16 , Expand);
191 setOperationAction(ISD::SDIV , MVT::i16 , Expand);
192 setOperationAction(ISD::UDIV , MVT::i16 , Expand);
193 setOperationAction(ISD::SREM , MVT::i16 , Expand);
194 setOperationAction(ISD::UREM , MVT::i16 , Expand);
195 setOperationAction(ISD::MULHS , MVT::i32 , Expand);
196 setOperationAction(ISD::MULHU , MVT::i32 , Expand);
197 setOperationAction(ISD::SDIV , MVT::i32 , Expand);
198 setOperationAction(ISD::UDIV , MVT::i32 , Expand);
199 setOperationAction(ISD::SREM , MVT::i32 , Expand);
200 setOperationAction(ISD::UREM , MVT::i32 , Expand);
201 setOperationAction(ISD::MULHS , MVT::i64 , Expand);
202 setOperationAction(ISD::MULHU , MVT::i64 , Expand);
203 setOperationAction(ISD::SDIV , MVT::i64 , Expand);
204 setOperationAction(ISD::UDIV , MVT::i64 , Expand);
205 setOperationAction(ISD::SREM , MVT::i64 , Expand);
206 setOperationAction(ISD::UREM , MVT::i64 , Expand);
208 setOperationAction(ISD::BR_JT , MVT::Other, Expand);
209 setOperationAction(ISD::BRCOND , MVT::Other, Custom);
210 setOperationAction(ISD::BR_CC , MVT::Other, Expand);
211 setOperationAction(ISD::SELECT_CC , MVT::Other, Expand);
212 if (Subtarget->is64Bit())
213 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal);
214 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Legal);
215 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Legal);
216 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
217 setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand);
218 setOperationAction(ISD::FREM , MVT::f32 , Expand);
219 setOperationAction(ISD::FREM , MVT::f64 , Expand);
220 setOperationAction(ISD::FREM , MVT::f80 , Expand);
221 setOperationAction(ISD::FLT_ROUNDS_ , MVT::i32 , Custom);
223 setOperationAction(ISD::CTPOP , MVT::i8 , Expand);
224 setOperationAction(ISD::CTTZ , MVT::i8 , Custom);
225 setOperationAction(ISD::CTLZ , MVT::i8 , Custom);
226 setOperationAction(ISD::CTPOP , MVT::i16 , Expand);
227 setOperationAction(ISD::CTTZ , MVT::i16 , Custom);
228 setOperationAction(ISD::CTLZ , MVT::i16 , Custom);
229 setOperationAction(ISD::CTPOP , MVT::i32 , Expand);
230 setOperationAction(ISD::CTTZ , MVT::i32 , Custom);
231 setOperationAction(ISD::CTLZ , MVT::i32 , Custom);
232 if (Subtarget->is64Bit()) {
233 setOperationAction(ISD::CTPOP , MVT::i64 , Expand);
234 setOperationAction(ISD::CTTZ , MVT::i64 , Custom);
235 setOperationAction(ISD::CTLZ , MVT::i64 , Custom);
238 setOperationAction(ISD::READCYCLECOUNTER , MVT::i64 , Custom);
239 setOperationAction(ISD::BSWAP , MVT::i16 , Expand);
241 // These should be promoted to a larger select which is supported.
242 setOperationAction(ISD::SELECT , MVT::i1 , Promote);
243 setOperationAction(ISD::SELECT , MVT::i8 , Promote);
244 // X86 wants to expand cmov itself.
245 setOperationAction(ISD::SELECT , MVT::i16 , Custom);
246 setOperationAction(ISD::SELECT , MVT::i32 , Custom);
247 setOperationAction(ISD::SELECT , MVT::f32 , Custom);
248 setOperationAction(ISD::SELECT , MVT::f64 , Custom);
249 setOperationAction(ISD::SELECT , MVT::f80 , Custom);
250 setOperationAction(ISD::SETCC , MVT::i8 , Custom);
251 setOperationAction(ISD::SETCC , MVT::i16 , Custom);
252 setOperationAction(ISD::SETCC , MVT::i32 , Custom);
253 setOperationAction(ISD::SETCC , MVT::f32 , Custom);
254 setOperationAction(ISD::SETCC , MVT::f64 , Custom);
255 setOperationAction(ISD::SETCC , MVT::f80 , Custom);
256 if (Subtarget->is64Bit()) {
257 setOperationAction(ISD::SELECT , MVT::i64 , Custom);
258 setOperationAction(ISD::SETCC , MVT::i64 , Custom);
260 // X86 ret instruction may pop stack.
261 setOperationAction(ISD::RET , MVT::Other, Custom);
262 setOperationAction(ISD::EH_RETURN , MVT::Other, Custom);
265 setOperationAction(ISD::ConstantPool , MVT::i32 , Custom);
266 setOperationAction(ISD::JumpTable , MVT::i32 , Custom);
267 setOperationAction(ISD::GlobalAddress , MVT::i32 , Custom);
268 setOperationAction(ISD::GlobalTLSAddress, MVT::i32 , Custom);
269 if (Subtarget->is64Bit())
270 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
271 setOperationAction(ISD::ExternalSymbol , MVT::i32 , Custom);
272 if (Subtarget->is64Bit()) {
273 setOperationAction(ISD::ConstantPool , MVT::i64 , Custom);
274 setOperationAction(ISD::JumpTable , MVT::i64 , Custom);
275 setOperationAction(ISD::GlobalAddress , MVT::i64 , Custom);
276 setOperationAction(ISD::ExternalSymbol, MVT::i64 , Custom);
278 // 64-bit addm sub, shl, sra, srl (iff 32-bit x86)
279 setOperationAction(ISD::SHL_PARTS , MVT::i32 , Custom);
280 setOperationAction(ISD::SRA_PARTS , MVT::i32 , Custom);
281 setOperationAction(ISD::SRL_PARTS , MVT::i32 , Custom);
282 if (Subtarget->is64Bit()) {
283 setOperationAction(ISD::SHL_PARTS , MVT::i64 , Custom);
284 setOperationAction(ISD::SRA_PARTS , MVT::i64 , Custom);
285 setOperationAction(ISD::SRL_PARTS , MVT::i64 , Custom);
288 if (Subtarget->hasSSE1())
289 setOperationAction(ISD::PREFETCH , MVT::Other, Legal);
291 if (!Subtarget->hasSSE2())
292 setOperationAction(ISD::MEMBARRIER , MVT::Other, Expand);
294 // Expand certain atomics
295 setOperationAction(ISD::ATOMIC_CMP_SWAP_8 , MVT::i8, Custom);
296 setOperationAction(ISD::ATOMIC_CMP_SWAP_16, MVT::i16, Custom);
297 setOperationAction(ISD::ATOMIC_CMP_SWAP_32, MVT::i32, Custom);
298 setOperationAction(ISD::ATOMIC_CMP_SWAP_64, MVT::i64, Custom);
300 setOperationAction(ISD::ATOMIC_LOAD_SUB_8, MVT::i8, Expand);
301 setOperationAction(ISD::ATOMIC_LOAD_SUB_16, MVT::i16, Expand);
302 setOperationAction(ISD::ATOMIC_LOAD_SUB_32, MVT::i32, Expand);
303 setOperationAction(ISD::ATOMIC_LOAD_SUB_64, MVT::i64, Expand);
305 // Use the default ISD::DBG_STOPPOINT, ISD::DECLARE expansion.
306 setOperationAction(ISD::DBG_STOPPOINT, MVT::Other, Expand);
307 // FIXME - use subtarget debug flags
308 if (!Subtarget->isTargetDarwin() &&
309 !Subtarget->isTargetELF() &&
310 !Subtarget->isTargetCygMing()) {
311 setOperationAction(ISD::DBG_LABEL, MVT::Other, Expand);
312 setOperationAction(ISD::EH_LABEL, MVT::Other, Expand);
315 setOperationAction(ISD::EXCEPTIONADDR, MVT::i64, Expand);
316 setOperationAction(ISD::EHSELECTION, MVT::i64, Expand);
317 setOperationAction(ISD::EXCEPTIONADDR, MVT::i32, Expand);
318 setOperationAction(ISD::EHSELECTION, MVT::i32, Expand);
319 if (Subtarget->is64Bit()) {
320 setExceptionPointerRegister(X86::RAX);
321 setExceptionSelectorRegister(X86::RDX);
323 setExceptionPointerRegister(X86::EAX);
324 setExceptionSelectorRegister(X86::EDX);
326 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i32, Custom);
327 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i64, Custom);
329 setOperationAction(ISD::TRAMPOLINE, MVT::Other, Custom);
331 setOperationAction(ISD::TRAP, MVT::Other, Legal);
333 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
334 setOperationAction(ISD::VASTART , MVT::Other, Custom);
335 setOperationAction(ISD::VAEND , MVT::Other, Expand);
336 if (Subtarget->is64Bit()) {
337 setOperationAction(ISD::VAARG , MVT::Other, Custom);
338 setOperationAction(ISD::VACOPY , MVT::Other, Custom);
340 setOperationAction(ISD::VAARG , MVT::Other, Expand);
341 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
344 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
345 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
346 if (Subtarget->is64Bit())
347 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64, Expand);
348 if (Subtarget->isTargetCygMing())
349 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Custom);
351 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Expand);
353 if (X86ScalarSSEf64) {
354 // f32 and f64 use SSE.
355 // Set up the FP register classes.
356 addRegisterClass(MVT::f32, X86::FR32RegisterClass);
357 addRegisterClass(MVT::f64, X86::FR64RegisterClass);
359 // Use ANDPD to simulate FABS.
360 setOperationAction(ISD::FABS , MVT::f64, Custom);
361 setOperationAction(ISD::FABS , MVT::f32, Custom);
363 // Use XORP to simulate FNEG.
364 setOperationAction(ISD::FNEG , MVT::f64, Custom);
365 setOperationAction(ISD::FNEG , MVT::f32, Custom);
367 // Use ANDPD and ORPD to simulate FCOPYSIGN.
368 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
369 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
371 // We don't support sin/cos/fmod
372 setOperationAction(ISD::FSIN , MVT::f64, Expand);
373 setOperationAction(ISD::FCOS , MVT::f64, Expand);
374 setOperationAction(ISD::FSIN , MVT::f32, Expand);
375 setOperationAction(ISD::FCOS , MVT::f32, Expand);
377 // Expand FP immediates into loads from the stack, except for the special
379 addLegalFPImmediate(APFloat(+0.0)); // xorpd
380 addLegalFPImmediate(APFloat(+0.0f)); // xorps
382 // Floating truncations from f80 and extensions to f80 go through memory.
383 // If optimizing, we lie about this though and handle it in
384 // InstructionSelectPreprocess so that dagcombine2 can hack on these.
386 setConvertAction(MVT::f32, MVT::f80, Expand);
387 setConvertAction(MVT::f64, MVT::f80, Expand);
388 setConvertAction(MVT::f80, MVT::f32, Expand);
389 setConvertAction(MVT::f80, MVT::f64, Expand);
391 } else if (X86ScalarSSEf32) {
392 // Use SSE for f32, x87 for f64.
393 // Set up the FP register classes.
394 addRegisterClass(MVT::f32, X86::FR32RegisterClass);
395 addRegisterClass(MVT::f64, X86::RFP64RegisterClass);
397 // Use ANDPS to simulate FABS.
398 setOperationAction(ISD::FABS , MVT::f32, Custom);
400 // Use XORP to simulate FNEG.
401 setOperationAction(ISD::FNEG , MVT::f32, Custom);
403 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
405 // Use ANDPS and ORPS to simulate FCOPYSIGN.
406 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
407 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
409 // We don't support sin/cos/fmod
410 setOperationAction(ISD::FSIN , MVT::f32, Expand);
411 setOperationAction(ISD::FCOS , MVT::f32, Expand);
413 // Special cases we handle for FP constants.
414 addLegalFPImmediate(APFloat(+0.0f)); // xorps
415 addLegalFPImmediate(APFloat(+0.0)); // FLD0
416 addLegalFPImmediate(APFloat(+1.0)); // FLD1
417 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
418 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
420 // SSE <-> X87 conversions go through memory. If optimizing, we lie about
421 // this though and handle it in InstructionSelectPreprocess so that
422 // dagcombine2 can hack on these.
424 setConvertAction(MVT::f32, MVT::f64, Expand);
425 setConvertAction(MVT::f32, MVT::f80, Expand);
426 setConvertAction(MVT::f80, MVT::f32, Expand);
427 setConvertAction(MVT::f64, MVT::f32, Expand);
428 // And x87->x87 truncations also.
429 setConvertAction(MVT::f80, MVT::f64, Expand);
433 setOperationAction(ISD::FSIN , MVT::f64 , Expand);
434 setOperationAction(ISD::FCOS , MVT::f64 , Expand);
437 // f32 and f64 in x87.
438 // Set up the FP register classes.
439 addRegisterClass(MVT::f64, X86::RFP64RegisterClass);
440 addRegisterClass(MVT::f32, X86::RFP32RegisterClass);
442 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
443 setOperationAction(ISD::UNDEF, MVT::f32, Expand);
444 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
445 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
447 // Floating truncations go through memory. If optimizing, we lie about
448 // this though and handle it in InstructionSelectPreprocess so that
449 // dagcombine2 can hack on these.
451 setConvertAction(MVT::f80, MVT::f32, Expand);
452 setConvertAction(MVT::f64, MVT::f32, Expand);
453 setConvertAction(MVT::f80, MVT::f64, Expand);
457 setOperationAction(ISD::FSIN , MVT::f64 , Expand);
458 setOperationAction(ISD::FCOS , MVT::f64 , Expand);
460 addLegalFPImmediate(APFloat(+0.0)); // FLD0
461 addLegalFPImmediate(APFloat(+1.0)); // FLD1
462 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
463 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
464 addLegalFPImmediate(APFloat(+0.0f)); // FLD0
465 addLegalFPImmediate(APFloat(+1.0f)); // FLD1
466 addLegalFPImmediate(APFloat(-0.0f)); // FLD0/FCHS
467 addLegalFPImmediate(APFloat(-1.0f)); // FLD1/FCHS
470 // Long double always uses X87.
471 addRegisterClass(MVT::f80, X86::RFP80RegisterClass);
472 setOperationAction(ISD::UNDEF, MVT::f80, Expand);
473 setOperationAction(ISD::FCOPYSIGN, MVT::f80, Expand);
475 APFloat TmpFlt(+0.0);
476 TmpFlt.convert(APFloat::x87DoubleExtended, APFloat::rmNearestTiesToEven);
477 addLegalFPImmediate(TmpFlt); // FLD0
479 addLegalFPImmediate(TmpFlt); // FLD0/FCHS
480 APFloat TmpFlt2(+1.0);
481 TmpFlt2.convert(APFloat::x87DoubleExtended, APFloat::rmNearestTiesToEven);
482 addLegalFPImmediate(TmpFlt2); // FLD1
483 TmpFlt2.changeSign();
484 addLegalFPImmediate(TmpFlt2); // FLD1/FCHS
488 setOperationAction(ISD::FSIN , MVT::f80 , Expand);
489 setOperationAction(ISD::FCOS , MVT::f80 , Expand);
492 // Always use a library call for pow.
493 setOperationAction(ISD::FPOW , MVT::f32 , Expand);
494 setOperationAction(ISD::FPOW , MVT::f64 , Expand);
495 setOperationAction(ISD::FPOW , MVT::f80 , Expand);
497 setOperationAction(ISD::FLOG, MVT::f32, Expand);
498 setOperationAction(ISD::FLOG, MVT::f64, Expand);
499 setOperationAction(ISD::FLOG, MVT::f80, Expand);
500 setOperationAction(ISD::FLOG2, MVT::f32, Expand);
501 setOperationAction(ISD::FLOG2, MVT::f64, Expand);
502 setOperationAction(ISD::FLOG2, MVT::f80, Expand);
503 setOperationAction(ISD::FLOG10, MVT::f32, Expand);
504 setOperationAction(ISD::FLOG10, MVT::f64, Expand);
505 setOperationAction(ISD::FLOG10, MVT::f80, Expand);
506 setOperationAction(ISD::FEXP, MVT::f32, Expand);
507 setOperationAction(ISD::FEXP, MVT::f64, Expand);
508 setOperationAction(ISD::FEXP, MVT::f80, Expand);
509 setOperationAction(ISD::FEXP2, MVT::f32, Expand);
510 setOperationAction(ISD::FEXP2, MVT::f64, Expand);
511 setOperationAction(ISD::FEXP2, MVT::f80, Expand);
513 // First set operation action for all vector types to expand. Then we
514 // will selectively turn on ones that can be effectively codegen'd.
515 for (unsigned VT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
516 VT <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++VT) {
517 setOperationAction(ISD::ADD , (MVT::SimpleValueType)VT, Expand);
518 setOperationAction(ISD::SUB , (MVT::SimpleValueType)VT, Expand);
519 setOperationAction(ISD::FADD, (MVT::SimpleValueType)VT, Expand);
520 setOperationAction(ISD::FNEG, (MVT::SimpleValueType)VT, Expand);
521 setOperationAction(ISD::FSUB, (MVT::SimpleValueType)VT, Expand);
522 setOperationAction(ISD::MUL , (MVT::SimpleValueType)VT, Expand);
523 setOperationAction(ISD::FMUL, (MVT::SimpleValueType)VT, Expand);
524 setOperationAction(ISD::SDIV, (MVT::SimpleValueType)VT, Expand);
525 setOperationAction(ISD::UDIV, (MVT::SimpleValueType)VT, Expand);
526 setOperationAction(ISD::FDIV, (MVT::SimpleValueType)VT, Expand);
527 setOperationAction(ISD::SREM, (MVT::SimpleValueType)VT, Expand);
528 setOperationAction(ISD::UREM, (MVT::SimpleValueType)VT, Expand);
529 setOperationAction(ISD::LOAD, (MVT::SimpleValueType)VT, Expand);
530 setOperationAction(ISD::VECTOR_SHUFFLE, (MVT::SimpleValueType)VT, Expand);
531 setOperationAction(ISD::EXTRACT_VECTOR_ELT,(MVT::SimpleValueType)VT,Expand);
532 setOperationAction(ISD::INSERT_VECTOR_ELT,(MVT::SimpleValueType)VT, Expand);
533 setOperationAction(ISD::FABS, (MVT::SimpleValueType)VT, Expand);
534 setOperationAction(ISD::FSIN, (MVT::SimpleValueType)VT, Expand);
535 setOperationAction(ISD::FCOS, (MVT::SimpleValueType)VT, Expand);
536 setOperationAction(ISD::FREM, (MVT::SimpleValueType)VT, Expand);
537 setOperationAction(ISD::FPOWI, (MVT::SimpleValueType)VT, Expand);
538 setOperationAction(ISD::FSQRT, (MVT::SimpleValueType)VT, Expand);
539 setOperationAction(ISD::FCOPYSIGN, (MVT::SimpleValueType)VT, Expand);
540 setOperationAction(ISD::SMUL_LOHI, (MVT::SimpleValueType)VT, Expand);
541 setOperationAction(ISD::UMUL_LOHI, (MVT::SimpleValueType)VT, Expand);
542 setOperationAction(ISD::SDIVREM, (MVT::SimpleValueType)VT, Expand);
543 setOperationAction(ISD::UDIVREM, (MVT::SimpleValueType)VT, Expand);
544 setOperationAction(ISD::FPOW, (MVT::SimpleValueType)VT, Expand);
545 setOperationAction(ISD::CTPOP, (MVT::SimpleValueType)VT, Expand);
546 setOperationAction(ISD::CTTZ, (MVT::SimpleValueType)VT, Expand);
547 setOperationAction(ISD::CTLZ, (MVT::SimpleValueType)VT, Expand);
548 setOperationAction(ISD::SHL, (MVT::SimpleValueType)VT, Expand);
549 setOperationAction(ISD::SRA, (MVT::SimpleValueType)VT, Expand);
550 setOperationAction(ISD::SRL, (MVT::SimpleValueType)VT, Expand);
551 setOperationAction(ISD::ROTL, (MVT::SimpleValueType)VT, Expand);
552 setOperationAction(ISD::ROTR, (MVT::SimpleValueType)VT, Expand);
553 setOperationAction(ISD::BSWAP, (MVT::SimpleValueType)VT, Expand);
554 setOperationAction(ISD::VSETCC, (MVT::SimpleValueType)VT, Expand);
555 setOperationAction(ISD::FLOG, (MVT::SimpleValueType)VT, Expand);
556 setOperationAction(ISD::FLOG2, (MVT::SimpleValueType)VT, Expand);
557 setOperationAction(ISD::FLOG10, (MVT::SimpleValueType)VT, Expand);
558 setOperationAction(ISD::FEXP, (MVT::SimpleValueType)VT, Expand);
559 setOperationAction(ISD::FEXP2, (MVT::SimpleValueType)VT, Expand);
562 if (Subtarget->hasMMX()) {
563 addRegisterClass(MVT::v8i8, X86::VR64RegisterClass);
564 addRegisterClass(MVT::v4i16, X86::VR64RegisterClass);
565 addRegisterClass(MVT::v2i32, X86::VR64RegisterClass);
566 addRegisterClass(MVT::v2f32, X86::VR64RegisterClass);
567 addRegisterClass(MVT::v1i64, X86::VR64RegisterClass);
569 // FIXME: add MMX packed arithmetics
571 setOperationAction(ISD::ADD, MVT::v8i8, Legal);
572 setOperationAction(ISD::ADD, MVT::v4i16, Legal);
573 setOperationAction(ISD::ADD, MVT::v2i32, Legal);
574 setOperationAction(ISD::ADD, MVT::v1i64, Legal);
576 setOperationAction(ISD::SUB, MVT::v8i8, Legal);
577 setOperationAction(ISD::SUB, MVT::v4i16, Legal);
578 setOperationAction(ISD::SUB, MVT::v2i32, Legal);
579 setOperationAction(ISD::SUB, MVT::v1i64, Legal);
581 setOperationAction(ISD::MULHS, MVT::v4i16, Legal);
582 setOperationAction(ISD::MUL, MVT::v4i16, Legal);
584 setOperationAction(ISD::AND, MVT::v8i8, Promote);
585 AddPromotedToType (ISD::AND, MVT::v8i8, MVT::v1i64);
586 setOperationAction(ISD::AND, MVT::v4i16, Promote);
587 AddPromotedToType (ISD::AND, MVT::v4i16, MVT::v1i64);
588 setOperationAction(ISD::AND, MVT::v2i32, Promote);
589 AddPromotedToType (ISD::AND, MVT::v2i32, MVT::v1i64);
590 setOperationAction(ISD::AND, MVT::v1i64, Legal);
592 setOperationAction(ISD::OR, MVT::v8i8, Promote);
593 AddPromotedToType (ISD::OR, MVT::v8i8, MVT::v1i64);
594 setOperationAction(ISD::OR, MVT::v4i16, Promote);
595 AddPromotedToType (ISD::OR, MVT::v4i16, MVT::v1i64);
596 setOperationAction(ISD::OR, MVT::v2i32, Promote);
597 AddPromotedToType (ISD::OR, MVT::v2i32, MVT::v1i64);
598 setOperationAction(ISD::OR, MVT::v1i64, Legal);
600 setOperationAction(ISD::XOR, MVT::v8i8, Promote);
601 AddPromotedToType (ISD::XOR, MVT::v8i8, MVT::v1i64);
602 setOperationAction(ISD::XOR, MVT::v4i16, Promote);
603 AddPromotedToType (ISD::XOR, MVT::v4i16, MVT::v1i64);
604 setOperationAction(ISD::XOR, MVT::v2i32, Promote);
605 AddPromotedToType (ISD::XOR, MVT::v2i32, MVT::v1i64);
606 setOperationAction(ISD::XOR, MVT::v1i64, Legal);
608 setOperationAction(ISD::LOAD, MVT::v8i8, Promote);
609 AddPromotedToType (ISD::LOAD, MVT::v8i8, MVT::v1i64);
610 setOperationAction(ISD::LOAD, MVT::v4i16, Promote);
611 AddPromotedToType (ISD::LOAD, MVT::v4i16, MVT::v1i64);
612 setOperationAction(ISD::LOAD, MVT::v2i32, Promote);
613 AddPromotedToType (ISD::LOAD, MVT::v2i32, MVT::v1i64);
614 setOperationAction(ISD::LOAD, MVT::v2f32, Promote);
615 AddPromotedToType (ISD::LOAD, MVT::v2f32, MVT::v1i64);
616 setOperationAction(ISD::LOAD, MVT::v1i64, Legal);
618 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i8, Custom);
619 setOperationAction(ISD::BUILD_VECTOR, MVT::v4i16, Custom);
620 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i32, Custom);
621 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f32, Custom);
622 setOperationAction(ISD::BUILD_VECTOR, MVT::v1i64, Custom);
624 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v8i8, Custom);
625 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4i16, Custom);
626 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i32, Custom);
627 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v1i64, Custom);
629 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2f32, Custom);
630 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i8, Custom);
631 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i16, Custom);
632 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v1i64, Custom);
634 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i16, Custom);
637 if (Subtarget->hasSSE1()) {
638 addRegisterClass(MVT::v4f32, X86::VR128RegisterClass);
640 setOperationAction(ISD::FADD, MVT::v4f32, Legal);
641 setOperationAction(ISD::FSUB, MVT::v4f32, Legal);
642 setOperationAction(ISD::FMUL, MVT::v4f32, Legal);
643 setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
644 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal);
645 setOperationAction(ISD::FNEG, MVT::v4f32, Custom);
646 setOperationAction(ISD::LOAD, MVT::v4f32, Legal);
647 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
648 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f32, Custom);
649 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
650 setOperationAction(ISD::SELECT, MVT::v4f32, Custom);
651 setOperationAction(ISD::VSETCC, MVT::v4f32, Custom);
654 if (Subtarget->hasSSE2()) {
655 addRegisterClass(MVT::v2f64, X86::VR128RegisterClass);
656 addRegisterClass(MVT::v16i8, X86::VR128RegisterClass);
657 addRegisterClass(MVT::v8i16, X86::VR128RegisterClass);
658 addRegisterClass(MVT::v4i32, X86::VR128RegisterClass);
659 addRegisterClass(MVT::v2i64, X86::VR128RegisterClass);
661 setOperationAction(ISD::ADD, MVT::v16i8, Legal);
662 setOperationAction(ISD::ADD, MVT::v8i16, Legal);
663 setOperationAction(ISD::ADD, MVT::v4i32, Legal);
664 setOperationAction(ISD::ADD, MVT::v2i64, Legal);
665 setOperationAction(ISD::SUB, MVT::v16i8, Legal);
666 setOperationAction(ISD::SUB, MVT::v8i16, Legal);
667 setOperationAction(ISD::SUB, MVT::v4i32, Legal);
668 setOperationAction(ISD::SUB, MVT::v2i64, Legal);
669 setOperationAction(ISD::MUL, MVT::v8i16, Legal);
670 setOperationAction(ISD::FADD, MVT::v2f64, Legal);
671 setOperationAction(ISD::FSUB, MVT::v2f64, Legal);
672 setOperationAction(ISD::FMUL, MVT::v2f64, Legal);
673 setOperationAction(ISD::FDIV, MVT::v2f64, Legal);
674 setOperationAction(ISD::FSQRT, MVT::v2f64, Legal);
675 setOperationAction(ISD::FNEG, MVT::v2f64, Custom);
677 setOperationAction(ISD::VSETCC, MVT::v2f64, Custom);
678 setOperationAction(ISD::VSETCC, MVT::v16i8, Custom);
679 setOperationAction(ISD::VSETCC, MVT::v8i16, Custom);
680 setOperationAction(ISD::VSETCC, MVT::v4i32, Custom);
682 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Custom);
683 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Custom);
684 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
685 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
686 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
688 // Custom lower build_vector, vector_shuffle, and extract_vector_elt.
689 for (unsigned i = (unsigned)MVT::v16i8; i != (unsigned)MVT::v2i64; ++i) {
690 MVT VT = (MVT::SimpleValueType)i;
691 // Do not attempt to custom lower non-power-of-2 vectors
692 if (!isPowerOf2_32(VT.getVectorNumElements()))
694 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
695 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
696 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
698 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f64, Custom);
699 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i64, Custom);
700 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Custom);
701 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Custom);
702 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f64, Custom);
703 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Custom);
704 if (Subtarget->is64Bit()) {
705 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
706 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
709 // Promote v16i8, v8i16, v4i32 load, select, and, or, xor to v2i64.
710 for (unsigned VT = (unsigned)MVT::v16i8; VT != (unsigned)MVT::v2i64; VT++) {
711 setOperationAction(ISD::AND, (MVT::SimpleValueType)VT, Promote);
712 AddPromotedToType (ISD::AND, (MVT::SimpleValueType)VT, MVT::v2i64);
713 setOperationAction(ISD::OR, (MVT::SimpleValueType)VT, Promote);
714 AddPromotedToType (ISD::OR, (MVT::SimpleValueType)VT, MVT::v2i64);
715 setOperationAction(ISD::XOR, (MVT::SimpleValueType)VT, Promote);
716 AddPromotedToType (ISD::XOR, (MVT::SimpleValueType)VT, MVT::v2i64);
717 setOperationAction(ISD::LOAD, (MVT::SimpleValueType)VT, Promote);
718 AddPromotedToType (ISD::LOAD, (MVT::SimpleValueType)VT, MVT::v2i64);
719 setOperationAction(ISD::SELECT, (MVT::SimpleValueType)VT, Promote);
720 AddPromotedToType (ISD::SELECT, (MVT::SimpleValueType)VT, MVT::v2i64);
723 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
725 // Custom lower v2i64 and v2f64 selects.
726 setOperationAction(ISD::LOAD, MVT::v2f64, Legal);
727 setOperationAction(ISD::LOAD, MVT::v2i64, Legal);
728 setOperationAction(ISD::SELECT, MVT::v2f64, Custom);
729 setOperationAction(ISD::SELECT, MVT::v2i64, Custom);
733 if (Subtarget->hasSSE41()) {
734 // FIXME: Do we need to handle scalar-to-vector here?
735 setOperationAction(ISD::MUL, MVT::v4i32, Legal);
736 setOperationAction(ISD::MUL, MVT::v2i64, Legal);
738 // i8 and i16 vectors are custom , because the source register and source
739 // source memory operand types are not the same width. f32 vectors are
740 // custom since the immediate controlling the insert encodes additional
742 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i8, Custom);
743 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
744 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Legal);
745 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
747 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i8, Custom);
748 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i16, Custom);
749 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i32, Legal);
750 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
752 if (Subtarget->is64Bit()) {
753 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Legal);
754 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Legal);
758 if (Subtarget->hasSSE42()) {
759 setOperationAction(ISD::VSETCC, MVT::v2i64, Custom);
762 // We want to custom lower some of our intrinsics.
763 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
765 // We have target-specific dag combine patterns for the following nodes:
766 setTargetDAGCombine(ISD::VECTOR_SHUFFLE);
767 setTargetDAGCombine(ISD::BUILD_VECTOR);
768 setTargetDAGCombine(ISD::SELECT);
769 setTargetDAGCombine(ISD::STORE);
771 computeRegisterProperties();
773 // FIXME: These should be based on subtarget info. Plus, the values should
774 // be smaller when we are in optimizing for size mode.
775 maxStoresPerMemset = 16; // For @llvm.memset -> sequence of stores
776 maxStoresPerMemcpy = 16; // For @llvm.memcpy -> sequence of stores
777 maxStoresPerMemmove = 3; // For @llvm.memmove -> sequence of stores
778 allowUnalignedMemoryAccesses = true; // x86 supports it!
779 setPrefLoopAlignment(16);
783 MVT X86TargetLowering::getSetCCResultType(const SDValue &) const {
788 /// getMaxByValAlign - Helper for getByValTypeAlignment to determine
789 /// the desired ByVal argument alignment.
790 static void getMaxByValAlign(const Type *Ty, unsigned &MaxAlign) {
793 if (const VectorType *VTy = dyn_cast<VectorType>(Ty)) {
794 if (VTy->getBitWidth() == 128)
796 } else if (const ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
797 unsigned EltAlign = 0;
798 getMaxByValAlign(ATy->getElementType(), EltAlign);
799 if (EltAlign > MaxAlign)
801 } else if (const StructType *STy = dyn_cast<StructType>(Ty)) {
802 for (unsigned i = 0, e = STy->getNumElements(); i != e; ++i) {
803 unsigned EltAlign = 0;
804 getMaxByValAlign(STy->getElementType(i), EltAlign);
805 if (EltAlign > MaxAlign)
814 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
815 /// function arguments in the caller parameter area. For X86, aggregates
816 /// that contain SSE vectors are placed at 16-byte boundaries while the rest
817 /// are at 4-byte boundaries.
818 unsigned X86TargetLowering::getByValTypeAlignment(const Type *Ty) const {
819 if (Subtarget->is64Bit()) {
820 // Max of 8 and alignment of type.
821 unsigned TyAlign = TD->getABITypeAlignment(Ty);
828 if (Subtarget->hasSSE1())
829 getMaxByValAlign(Ty, Align);
833 /// getOptimalMemOpType - Returns the target specific optimal type for load
834 /// and store operations as a result of memset, memcpy, and memmove
835 /// lowering. It returns MVT::iAny if SelectionDAG should be responsible for
838 X86TargetLowering::getOptimalMemOpType(uint64_t Size, unsigned Align,
839 bool isSrcConst, bool isSrcStr) const {
840 if ((isSrcConst || isSrcStr) && Subtarget->hasSSE2() && Size >= 16)
842 if ((isSrcConst || isSrcStr) && Subtarget->hasSSE1() && Size >= 16)
844 if (Subtarget->is64Bit() && Size >= 8)
850 /// getPICJumpTableRelocaBase - Returns relocation base for the given PIC
852 SDValue X86TargetLowering::getPICJumpTableRelocBase(SDValue Table,
853 SelectionDAG &DAG) const {
854 if (usesGlobalOffsetTable())
855 return DAG.getNode(ISD::GLOBAL_OFFSET_TABLE, getPointerTy());
856 if (!Subtarget->isPICStyleRIPRel())
857 return DAG.getNode(X86ISD::GlobalBaseReg, getPointerTy());
861 //===----------------------------------------------------------------------===//
862 // Return Value Calling Convention Implementation
863 //===----------------------------------------------------------------------===//
865 #include "X86GenCallingConv.inc"
867 /// LowerRET - Lower an ISD::RET node.
868 SDValue X86TargetLowering::LowerRET(SDValue Op, SelectionDAG &DAG) {
869 assert((Op.getNumOperands() & 1) == 1 && "ISD::RET should have odd # args");
871 SmallVector<CCValAssign, 16> RVLocs;
872 unsigned CC = DAG.getMachineFunction().getFunction()->getCallingConv();
873 bool isVarArg = DAG.getMachineFunction().getFunction()->isVarArg();
874 CCState CCInfo(CC, isVarArg, getTargetMachine(), RVLocs);
875 CCInfo.AnalyzeReturn(Op.getNode(), RetCC_X86);
877 // If this is the first return lowered for this function, add the regs to the
878 // liveout set for the function.
879 if (DAG.getMachineFunction().getRegInfo().liveout_empty()) {
880 for (unsigned i = 0; i != RVLocs.size(); ++i)
881 if (RVLocs[i].isRegLoc())
882 DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg());
884 SDValue Chain = Op.getOperand(0);
886 // Handle tail call return.
887 Chain = GetPossiblePreceedingTailCall(Chain, X86ISD::TAILCALL);
888 if (Chain.getOpcode() == X86ISD::TAILCALL) {
889 SDValue TailCall = Chain;
890 SDValue TargetAddress = TailCall.getOperand(1);
891 SDValue StackAdjustment = TailCall.getOperand(2);
892 assert(((TargetAddress.getOpcode() == ISD::Register &&
893 (cast<RegisterSDNode>(TargetAddress)->getReg() == X86::ECX ||
894 cast<RegisterSDNode>(TargetAddress)->getReg() == X86::R9)) ||
895 TargetAddress.getOpcode() == ISD::TargetExternalSymbol ||
896 TargetAddress.getOpcode() == ISD::TargetGlobalAddress) &&
897 "Expecting an global address, external symbol, or register");
898 assert(StackAdjustment.getOpcode() == ISD::Constant &&
899 "Expecting a const value");
901 SmallVector<SDValue,8> Operands;
902 Operands.push_back(Chain.getOperand(0));
903 Operands.push_back(TargetAddress);
904 Operands.push_back(StackAdjustment);
905 // Copy registers used by the call. Last operand is a flag so it is not
907 for (unsigned i=3; i < TailCall.getNumOperands()-1; i++) {
908 Operands.push_back(Chain.getOperand(i));
910 return DAG.getNode(X86ISD::TC_RETURN, MVT::Other, &Operands[0],
917 SmallVector<SDValue, 6> RetOps;
918 RetOps.push_back(Chain); // Operand #0 = Chain (updated below)
919 // Operand #1 = Bytes To Pop
920 RetOps.push_back(DAG.getConstant(getBytesToPopOnReturn(), MVT::i16));
922 // Copy the result values into the output registers.
923 for (unsigned i = 0; i != RVLocs.size(); ++i) {
924 CCValAssign &VA = RVLocs[i];
925 assert(VA.isRegLoc() && "Can only return in registers!");
926 SDValue ValToCopy = Op.getOperand(i*2+1);
928 // Returns in ST0/ST1 are handled specially: these are pushed as operands to
929 // the RET instruction and handled by the FP Stackifier.
930 if (RVLocs[i].getLocReg() == X86::ST0 ||
931 RVLocs[i].getLocReg() == X86::ST1) {
932 // If this is a copy from an xmm register to ST(0), use an FPExtend to
933 // change the value to the FP stack register class.
934 if (isScalarFPTypeInSSEReg(RVLocs[i].getValVT()))
935 ValToCopy = DAG.getNode(ISD::FP_EXTEND, MVT::f80, ValToCopy);
936 RetOps.push_back(ValToCopy);
937 // Don't emit a copytoreg.
941 Chain = DAG.getCopyToReg(Chain, VA.getLocReg(), ValToCopy, Flag);
942 Flag = Chain.getValue(1);
945 // The x86-64 ABI for returning structs by value requires that we copy
946 // the sret argument into %rax for the return. We saved the argument into
947 // a virtual register in the entry block, so now we copy the value out
949 if (Subtarget->is64Bit() &&
950 DAG.getMachineFunction().getFunction()->hasStructRetAttr()) {
951 MachineFunction &MF = DAG.getMachineFunction();
952 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
953 unsigned Reg = FuncInfo->getSRetReturnReg();
955 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(MVT::i64));
956 FuncInfo->setSRetReturnReg(Reg);
958 SDValue Val = DAG.getCopyFromReg(Chain, Reg, getPointerTy());
960 Chain = DAG.getCopyToReg(Chain, X86::RAX, Val, Flag);
961 Flag = Chain.getValue(1);
964 RetOps[0] = Chain; // Update chain.
966 // Add the flag if we have it.
968 RetOps.push_back(Flag);
970 return DAG.getNode(X86ISD::RET_FLAG, MVT::Other, &RetOps[0], RetOps.size());
974 /// LowerCallResult - Lower the result values of an ISD::CALL into the
975 /// appropriate copies out of appropriate physical registers. This assumes that
976 /// Chain/InFlag are the input chain/flag to use, and that TheCall is the call
977 /// being lowered. The returns a SDNode with the same number of values as the
979 SDNode *X86TargetLowering::
980 LowerCallResult(SDValue Chain, SDValue InFlag, CallSDNode *TheCall,
981 unsigned CallingConv, SelectionDAG &DAG) {
983 // Assign locations to each value returned by this call.
984 SmallVector<CCValAssign, 16> RVLocs;
985 bool isVarArg = TheCall->isVarArg();
986 CCState CCInfo(CallingConv, isVarArg, getTargetMachine(), RVLocs);
987 CCInfo.AnalyzeCallResult(TheCall, RetCC_X86);
989 SmallVector<SDValue, 8> ResultVals;
991 // Copy all of the result registers out of their specified physreg.
992 for (unsigned i = 0; i != RVLocs.size(); ++i) {
993 MVT CopyVT = RVLocs[i].getValVT();
995 // If this is a call to a function that returns an fp value on the floating
996 // point stack, but where we prefer to use the value in xmm registers, copy
997 // it out as F80 and use a truncate to move it from fp stack reg to xmm reg.
998 if ((RVLocs[i].getLocReg() == X86::ST0 ||
999 RVLocs[i].getLocReg() == X86::ST1) &&
1000 isScalarFPTypeInSSEReg(RVLocs[i].getValVT())) {
1004 Chain = DAG.getCopyFromReg(Chain, RVLocs[i].getLocReg(),
1005 CopyVT, InFlag).getValue(1);
1006 SDValue Val = Chain.getValue(0);
1007 InFlag = Chain.getValue(2);
1009 if (CopyVT != RVLocs[i].getValVT()) {
1010 // Round the F80 the right size, which also moves to the appropriate xmm
1012 Val = DAG.getNode(ISD::FP_ROUND, RVLocs[i].getValVT(), Val,
1013 // This truncation won't change the value.
1014 DAG.getIntPtrConstant(1));
1017 ResultVals.push_back(Val);
1020 // Merge everything together with a MERGE_VALUES node.
1021 ResultVals.push_back(Chain);
1022 return DAG.getMergeValues(TheCall->getVTList(), &ResultVals[0],
1023 ResultVals.size()).getNode();
1027 //===----------------------------------------------------------------------===//
1028 // C & StdCall & Fast Calling Convention implementation
1029 //===----------------------------------------------------------------------===//
1030 // StdCall calling convention seems to be standard for many Windows' API
1031 // routines and around. It differs from C calling convention just a little:
1032 // callee should clean up the stack, not caller. Symbols should be also
1033 // decorated in some fancy way :) It doesn't support any vector arguments.
1034 // For info on fast calling convention see Fast Calling Convention (tail call)
1035 // implementation LowerX86_32FastCCCallTo.
1037 /// AddLiveIn - This helper function adds the specified physical register to the
1038 /// MachineFunction as a live in value. It also creates a corresponding virtual
1039 /// register for it.
1040 static unsigned AddLiveIn(MachineFunction &MF, unsigned PReg,
1041 const TargetRegisterClass *RC) {
1042 assert(RC->contains(PReg) && "Not the correct regclass!");
1043 unsigned VReg = MF.getRegInfo().createVirtualRegister(RC);
1044 MF.getRegInfo().addLiveIn(PReg, VReg);
1048 /// CallIsStructReturn - Determines whether a CALL node uses struct return
1050 static bool CallIsStructReturn(CallSDNode *TheCall) {
1051 unsigned NumOps = TheCall->getNumArgs();
1055 return TheCall->getArgFlags(0).isSRet();
1058 /// ArgsAreStructReturn - Determines whether a FORMAL_ARGUMENTS node uses struct
1059 /// return semantics.
1060 static bool ArgsAreStructReturn(SDValue Op) {
1061 unsigned NumArgs = Op.getNode()->getNumValues() - 1;
1065 return cast<ARG_FLAGSSDNode>(Op.getOperand(3))->getArgFlags().isSRet();
1068 /// IsCalleePop - Determines whether a CALL or FORMAL_ARGUMENTS node requires
1069 /// the callee to pop its own arguments. Callee pop is necessary to support tail
1071 bool X86TargetLowering::IsCalleePop(bool IsVarArg, unsigned CallingConv) {
1075 switch (CallingConv) {
1078 case CallingConv::X86_StdCall:
1079 return !Subtarget->is64Bit();
1080 case CallingConv::X86_FastCall:
1081 return !Subtarget->is64Bit();
1082 case CallingConv::Fast:
1083 return PerformTailCallOpt;
1087 /// CCAssignFnForNode - Selects the correct CCAssignFn for a the
1088 /// given CallingConvention value.
1089 CCAssignFn *X86TargetLowering::CCAssignFnForNode(unsigned CC) const {
1090 if (Subtarget->is64Bit()) {
1091 if (Subtarget->isTargetWin64())
1092 return CC_X86_Win64_C;
1093 else if (CC == CallingConv::Fast && PerformTailCallOpt)
1094 return CC_X86_64_TailCall;
1099 if (CC == CallingConv::X86_FastCall)
1100 return CC_X86_32_FastCall;
1101 else if (CC == CallingConv::Fast && PerformTailCallOpt)
1102 return CC_X86_32_TailCall;
1103 else if (CC == CallingConv::Fast)
1104 return CC_X86_32_FastCC;
1109 /// NameDecorationForFORMAL_ARGUMENTS - Selects the appropriate decoration to
1110 /// apply to a MachineFunction containing a given FORMAL_ARGUMENTS node.
1112 X86TargetLowering::NameDecorationForFORMAL_ARGUMENTS(SDValue Op) {
1113 unsigned CC = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
1114 if (CC == CallingConv::X86_FastCall)
1116 else if (CC == CallingConv::X86_StdCall)
1122 /// CallRequiresGOTInRegister - Check whether the call requires the GOT pointer
1123 /// in a register before calling.
1124 bool X86TargetLowering::CallRequiresGOTPtrInReg(bool Is64Bit, bool IsTailCall) {
1125 return !IsTailCall && !Is64Bit &&
1126 getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1127 Subtarget->isPICStyleGOT();
1130 /// CallRequiresFnAddressInReg - Check whether the call requires the function
1131 /// address to be loaded in a register.
1133 X86TargetLowering::CallRequiresFnAddressInReg(bool Is64Bit, bool IsTailCall) {
1134 return !Is64Bit && IsTailCall &&
1135 getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1136 Subtarget->isPICStyleGOT();
1139 /// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified
1140 /// by "Src" to address "Dst" with size and alignment information specified by
1141 /// the specific parameter attribute. The copy will be passed as a byval
1142 /// function parameter.
1144 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
1145 ISD::ArgFlagsTy Flags, SelectionDAG &DAG) {
1146 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32);
1147 return DAG.getMemcpy(Chain, Dst, Src, SizeNode, Flags.getByValAlign(),
1148 /*AlwaysInline=*/true, NULL, 0, NULL, 0);
1151 SDValue X86TargetLowering::LowerMemArgument(SDValue Op, SelectionDAG &DAG,
1152 const CCValAssign &VA,
1153 MachineFrameInfo *MFI,
1155 SDValue Root, unsigned i) {
1156 // Create the nodes corresponding to a load from this parameter slot.
1157 ISD::ArgFlagsTy Flags =
1158 cast<ARG_FLAGSSDNode>(Op.getOperand(3 + i))->getArgFlags();
1159 bool AlwaysUseMutable = (CC==CallingConv::Fast) && PerformTailCallOpt;
1160 bool isImmutable = !AlwaysUseMutable && !Flags.isByVal();
1162 // FIXME: For now, all byval parameter objects are marked mutable. This can be
1163 // changed with more analysis.
1164 // In case of tail call optimization mark all arguments mutable. Since they
1165 // could be overwritten by lowering of arguments in case of a tail call.
1166 int FI = MFI->CreateFixedObject(VA.getValVT().getSizeInBits()/8,
1167 VA.getLocMemOffset(), isImmutable);
1168 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
1169 if (Flags.isByVal())
1171 return DAG.getLoad(VA.getValVT(), Root, FIN,
1172 PseudoSourceValue::getFixedStack(FI), 0);
1176 X86TargetLowering::LowerFORMAL_ARGUMENTS(SDValue Op, SelectionDAG &DAG) {
1177 MachineFunction &MF = DAG.getMachineFunction();
1178 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1180 const Function* Fn = MF.getFunction();
1181 if (Fn->hasExternalLinkage() &&
1182 Subtarget->isTargetCygMing() &&
1183 Fn->getName() == "main")
1184 FuncInfo->setForceFramePointer(true);
1186 // Decorate the function name.
1187 FuncInfo->setDecorationStyle(NameDecorationForFORMAL_ARGUMENTS(Op));
1189 MachineFrameInfo *MFI = MF.getFrameInfo();
1190 SDValue Root = Op.getOperand(0);
1191 bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue() != 0;
1192 unsigned CC = MF.getFunction()->getCallingConv();
1193 bool Is64Bit = Subtarget->is64Bit();
1194 bool IsWin64 = Subtarget->isTargetWin64();
1196 assert(!(isVarArg && CC == CallingConv::Fast) &&
1197 "Var args not supported with calling convention fastcc");
1199 // Assign locations to all of the incoming arguments.
1200 SmallVector<CCValAssign, 16> ArgLocs;
1201 CCState CCInfo(CC, isVarArg, getTargetMachine(), ArgLocs);
1202 CCInfo.AnalyzeFormalArguments(Op.getNode(), CCAssignFnForNode(CC));
1204 SmallVector<SDValue, 8> ArgValues;
1205 unsigned LastVal = ~0U;
1206 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1207 CCValAssign &VA = ArgLocs[i];
1208 // TODO: If an arg is passed in two places (e.g. reg and stack), skip later
1210 assert(VA.getValNo() != LastVal &&
1211 "Don't support value assigned to multiple locs yet");
1212 LastVal = VA.getValNo();
1214 if (VA.isRegLoc()) {
1215 MVT RegVT = VA.getLocVT();
1216 TargetRegisterClass *RC;
1217 if (RegVT == MVT::i32)
1218 RC = X86::GR32RegisterClass;
1219 else if (Is64Bit && RegVT == MVT::i64)
1220 RC = X86::GR64RegisterClass;
1221 else if (RegVT == MVT::f32)
1222 RC = X86::FR32RegisterClass;
1223 else if (RegVT == MVT::f64)
1224 RC = X86::FR64RegisterClass;
1225 else if (RegVT.isVector() && RegVT.getSizeInBits() == 128)
1226 RC = X86::VR128RegisterClass;
1227 else if (RegVT.isVector()) {
1228 assert(RegVT.getSizeInBits() == 64);
1230 RC = X86::VR64RegisterClass; // MMX values are passed in MMXs.
1232 // Darwin calling convention passes MMX values in either GPRs or
1233 // XMMs in x86-64. Other targets pass them in memory.
1234 if (RegVT != MVT::v1i64 && Subtarget->hasSSE2()) {
1235 RC = X86::VR128RegisterClass; // MMX values are passed in XMMs.
1238 RC = X86::GR64RegisterClass; // v1i64 values are passed in GPRs.
1243 assert(0 && "Unknown argument type!");
1246 unsigned Reg = AddLiveIn(DAG.getMachineFunction(), VA.getLocReg(), RC);
1247 SDValue ArgValue = DAG.getCopyFromReg(Root, Reg, RegVT);
1249 // If this is an 8 or 16-bit value, it is really passed promoted to 32
1250 // bits. Insert an assert[sz]ext to capture this, then truncate to the
1252 if (VA.getLocInfo() == CCValAssign::SExt)
1253 ArgValue = DAG.getNode(ISD::AssertSext, RegVT, ArgValue,
1254 DAG.getValueType(VA.getValVT()));
1255 else if (VA.getLocInfo() == CCValAssign::ZExt)
1256 ArgValue = DAG.getNode(ISD::AssertZext, RegVT, ArgValue,
1257 DAG.getValueType(VA.getValVT()));
1259 if (VA.getLocInfo() != CCValAssign::Full)
1260 ArgValue = DAG.getNode(ISD::TRUNCATE, VA.getValVT(), ArgValue);
1262 // Handle MMX values passed in GPRs.
1263 if (Is64Bit && RegVT != VA.getLocVT()) {
1264 if (RegVT.getSizeInBits() == 64 && RC == X86::GR64RegisterClass)
1265 ArgValue = DAG.getNode(ISD::BIT_CONVERT, VA.getLocVT(), ArgValue);
1266 else if (RC == X86::VR128RegisterClass) {
1267 ArgValue = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, MVT::i64, ArgValue,
1268 DAG.getConstant(0, MVT::i64));
1269 ArgValue = DAG.getNode(ISD::BIT_CONVERT, VA.getLocVT(), ArgValue);
1273 ArgValues.push_back(ArgValue);
1275 assert(VA.isMemLoc());
1276 ArgValues.push_back(LowerMemArgument(Op, DAG, VA, MFI, CC, Root, i));
1280 // The x86-64 ABI for returning structs by value requires that we copy
1281 // the sret argument into %rax for the return. Save the argument into
1282 // a virtual register so that we can access it from the return points.
1283 if (Is64Bit && DAG.getMachineFunction().getFunction()->hasStructRetAttr()) {
1284 MachineFunction &MF = DAG.getMachineFunction();
1285 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1286 unsigned Reg = FuncInfo->getSRetReturnReg();
1288 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(MVT::i64));
1289 FuncInfo->setSRetReturnReg(Reg);
1291 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), Reg, ArgValues[0]);
1292 Root = DAG.getNode(ISD::TokenFactor, MVT::Other, Copy, Root);
1295 unsigned StackSize = CCInfo.getNextStackOffset();
1296 // align stack specially for tail calls
1297 if (PerformTailCallOpt && CC == CallingConv::Fast)
1298 StackSize = GetAlignedArgumentStackSize(StackSize, DAG);
1300 // If the function takes variable number of arguments, make a frame index for
1301 // the start of the first vararg value... for expansion of llvm.va_start.
1303 if (Is64Bit || CC != CallingConv::X86_FastCall) {
1304 VarArgsFrameIndex = MFI->CreateFixedObject(1, StackSize);
1307 unsigned TotalNumIntRegs = 0, TotalNumXMMRegs = 0;
1309 // FIXME: We should really autogenerate these arrays
1310 static const unsigned GPR64ArgRegsWin64[] = {
1311 X86::RCX, X86::RDX, X86::R8, X86::R9
1313 static const unsigned XMMArgRegsWin64[] = {
1314 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3
1316 static const unsigned GPR64ArgRegs64Bit[] = {
1317 X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9
1319 static const unsigned XMMArgRegs64Bit[] = {
1320 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
1321 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
1323 const unsigned *GPR64ArgRegs, *XMMArgRegs;
1326 TotalNumIntRegs = 4; TotalNumXMMRegs = 4;
1327 GPR64ArgRegs = GPR64ArgRegsWin64;
1328 XMMArgRegs = XMMArgRegsWin64;
1330 TotalNumIntRegs = 6; TotalNumXMMRegs = 8;
1331 GPR64ArgRegs = GPR64ArgRegs64Bit;
1332 XMMArgRegs = XMMArgRegs64Bit;
1334 unsigned NumIntRegs = CCInfo.getFirstUnallocated(GPR64ArgRegs,
1336 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs,
1339 // For X86-64, if there are vararg parameters that are passed via
1340 // registers, then we must store them to their spots on the stack so they
1341 // may be loaded by deferencing the result of va_next.
1342 VarArgsGPOffset = NumIntRegs * 8;
1343 VarArgsFPOffset = TotalNumIntRegs * 8 + NumXMMRegs * 16;
1344 RegSaveFrameIndex = MFI->CreateStackObject(TotalNumIntRegs * 8 +
1345 TotalNumXMMRegs * 16, 16);
1347 // Store the integer parameter registers.
1348 SmallVector<SDValue, 8> MemOps;
1349 SDValue RSFIN = DAG.getFrameIndex(RegSaveFrameIndex, getPointerTy());
1350 SDValue FIN = DAG.getNode(ISD::ADD, getPointerTy(), RSFIN,
1351 DAG.getIntPtrConstant(VarArgsGPOffset));
1352 for (; NumIntRegs != TotalNumIntRegs; ++NumIntRegs) {
1353 unsigned VReg = AddLiveIn(MF, GPR64ArgRegs[NumIntRegs],
1354 X86::GR64RegisterClass);
1355 SDValue Val = DAG.getCopyFromReg(Root, VReg, MVT::i64);
1357 DAG.getStore(Val.getValue(1), Val, FIN,
1358 PseudoSourceValue::getFixedStack(RegSaveFrameIndex), 0);
1359 MemOps.push_back(Store);
1360 FIN = DAG.getNode(ISD::ADD, getPointerTy(), FIN,
1361 DAG.getIntPtrConstant(8));
1364 // Now store the XMM (fp + vector) parameter registers.
1365 FIN = DAG.getNode(ISD::ADD, getPointerTy(), RSFIN,
1366 DAG.getIntPtrConstant(VarArgsFPOffset));
1367 for (; NumXMMRegs != TotalNumXMMRegs; ++NumXMMRegs) {
1368 unsigned VReg = AddLiveIn(MF, XMMArgRegs[NumXMMRegs],
1369 X86::VR128RegisterClass);
1370 SDValue Val = DAG.getCopyFromReg(Root, VReg, MVT::v4f32);
1372 DAG.getStore(Val.getValue(1), Val, FIN,
1373 PseudoSourceValue::getFixedStack(RegSaveFrameIndex), 0);
1374 MemOps.push_back(Store);
1375 FIN = DAG.getNode(ISD::ADD, getPointerTy(), FIN,
1376 DAG.getIntPtrConstant(16));
1378 if (!MemOps.empty())
1379 Root = DAG.getNode(ISD::TokenFactor, MVT::Other,
1380 &MemOps[0], MemOps.size());
1384 ArgValues.push_back(Root);
1386 // Some CCs need callee pop.
1387 if (IsCalleePop(isVarArg, CC)) {
1388 BytesToPopOnReturn = StackSize; // Callee pops everything.
1389 BytesCallerReserves = 0;
1391 BytesToPopOnReturn = 0; // Callee pops nothing.
1392 // If this is an sret function, the return should pop the hidden pointer.
1393 if (!Is64Bit && CC != CallingConv::Fast && ArgsAreStructReturn(Op))
1394 BytesToPopOnReturn = 4;
1395 BytesCallerReserves = StackSize;
1399 RegSaveFrameIndex = 0xAAAAAAA; // RegSaveFrameIndex is X86-64 only.
1400 if (CC == CallingConv::X86_FastCall)
1401 VarArgsFrameIndex = 0xAAAAAAA; // fastcc functions can't have varargs.
1404 FuncInfo->setBytesToPopOnReturn(BytesToPopOnReturn);
1406 // Return the new list of results.
1407 return DAG.getMergeValues(Op.getNode()->getVTList(), &ArgValues[0],
1408 ArgValues.size()).getValue(Op.getResNo());
1412 X86TargetLowering::LowerMemOpCallTo(CallSDNode *TheCall, SelectionDAG &DAG,
1413 const SDValue &StackPtr,
1414 const CCValAssign &VA,
1416 SDValue Arg, ISD::ArgFlagsTy Flags) {
1417 unsigned LocMemOffset = VA.getLocMemOffset();
1418 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
1419 PtrOff = DAG.getNode(ISD::ADD, getPointerTy(), StackPtr, PtrOff);
1420 if (Flags.isByVal()) {
1421 return CreateCopyOfByValArgument(Arg, PtrOff, Chain, Flags, DAG);
1423 return DAG.getStore(Chain, Arg, PtrOff,
1424 PseudoSourceValue::getStack(), LocMemOffset);
1427 /// EmitTailCallLoadRetAddr - Emit a load of return adress if tail call
1428 /// optimization is performed and it is required.
1430 X86TargetLowering::EmitTailCallLoadRetAddr(SelectionDAG &DAG,
1431 SDValue &OutRetAddr,
1436 if (!IsTailCall || FPDiff==0) return Chain;
1438 // Adjust the Return address stack slot.
1439 MVT VT = getPointerTy();
1440 OutRetAddr = getReturnAddressFrameIndex(DAG);
1441 // Load the "old" Return address.
1442 OutRetAddr = DAG.getLoad(VT, Chain,OutRetAddr, NULL, 0);
1443 return SDValue(OutRetAddr.getNode(), 1);
1446 /// EmitTailCallStoreRetAddr - Emit a store of the return adress if tail call
1447 /// optimization is performed and it is required (FPDiff!=0).
1449 EmitTailCallStoreRetAddr(SelectionDAG & DAG, MachineFunction &MF,
1450 SDValue Chain, SDValue RetAddrFrIdx,
1451 bool Is64Bit, int FPDiff) {
1452 // Store the return address to the appropriate stack slot.
1453 if (!FPDiff) return Chain;
1454 // Calculate the new stack slot for the return address.
1455 int SlotSize = Is64Bit ? 8 : 4;
1456 int NewReturnAddrFI =
1457 MF.getFrameInfo()->CreateFixedObject(SlotSize, FPDiff-SlotSize);
1458 MVT VT = Is64Bit ? MVT::i64 : MVT::i32;
1459 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewReturnAddrFI, VT);
1460 Chain = DAG.getStore(Chain, RetAddrFrIdx, NewRetAddrFrIdx,
1461 PseudoSourceValue::getFixedStack(NewReturnAddrFI), 0);
1465 SDValue X86TargetLowering::LowerCALL(SDValue Op, SelectionDAG &DAG) {
1466 MachineFunction &MF = DAG.getMachineFunction();
1467 CallSDNode *TheCall = cast<CallSDNode>(Op.getNode());
1468 SDValue Chain = TheCall->getChain();
1469 unsigned CC = TheCall->getCallingConv();
1470 bool isVarArg = TheCall->isVarArg();
1471 bool IsTailCall = TheCall->isTailCall() &&
1472 CC == CallingConv::Fast && PerformTailCallOpt;
1473 SDValue Callee = TheCall->getCallee();
1474 bool Is64Bit = Subtarget->is64Bit();
1475 bool IsStructRet = CallIsStructReturn(TheCall);
1477 assert(!(isVarArg && CC == CallingConv::Fast) &&
1478 "Var args not supported with calling convention fastcc");
1480 // Analyze operands of the call, assigning locations to each operand.
1481 SmallVector<CCValAssign, 16> ArgLocs;
1482 CCState CCInfo(CC, isVarArg, getTargetMachine(), ArgLocs);
1483 CCInfo.AnalyzeCallOperands(TheCall, CCAssignFnForNode(CC));
1485 // Get a count of how many bytes are to be pushed on the stack.
1486 unsigned NumBytes = CCInfo.getNextStackOffset();
1487 if (PerformTailCallOpt && CC == CallingConv::Fast)
1488 NumBytes = GetAlignedArgumentStackSize(NumBytes, DAG);
1492 // Lower arguments at fp - stackoffset + fpdiff.
1493 unsigned NumBytesCallerPushed =
1494 MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn();
1495 FPDiff = NumBytesCallerPushed - NumBytes;
1497 // Set the delta of movement of the returnaddr stackslot.
1498 // But only set if delta is greater than previous delta.
1499 if (FPDiff < (MF.getInfo<X86MachineFunctionInfo>()->getTCReturnAddrDelta()))
1500 MF.getInfo<X86MachineFunctionInfo>()->setTCReturnAddrDelta(FPDiff);
1503 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes));
1505 SDValue RetAddrFrIdx;
1506 // Load return adress for tail calls.
1507 Chain = EmitTailCallLoadRetAddr(DAG, RetAddrFrIdx, Chain, IsTailCall, Is64Bit,
1510 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
1511 SmallVector<SDValue, 8> MemOpChains;
1514 // Walk the register/memloc assignments, inserting copies/loads. In the case
1515 // of tail call optimization arguments are handle later.
1516 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1517 CCValAssign &VA = ArgLocs[i];
1518 SDValue Arg = TheCall->getArg(i);
1519 ISD::ArgFlagsTy Flags = TheCall->getArgFlags(i);
1520 bool isByVal = Flags.isByVal();
1522 // Promote the value if needed.
1523 switch (VA.getLocInfo()) {
1524 default: assert(0 && "Unknown loc info!");
1525 case CCValAssign::Full: break;
1526 case CCValAssign::SExt:
1527 Arg = DAG.getNode(ISD::SIGN_EXTEND, VA.getLocVT(), Arg);
1529 case CCValAssign::ZExt:
1530 Arg = DAG.getNode(ISD::ZERO_EXTEND, VA.getLocVT(), Arg);
1532 case CCValAssign::AExt:
1533 Arg = DAG.getNode(ISD::ANY_EXTEND, VA.getLocVT(), Arg);
1537 if (VA.isRegLoc()) {
1539 MVT RegVT = VA.getLocVT();
1540 if (RegVT.isVector() && RegVT.getSizeInBits() == 64)
1541 switch (VA.getLocReg()) {
1544 case X86::RDI: case X86::RSI: case X86::RDX: case X86::RCX:
1546 // Special case: passing MMX values in GPR registers.
1547 Arg = DAG.getNode(ISD::BIT_CONVERT, MVT::i64, Arg);
1550 case X86::XMM0: case X86::XMM1: case X86::XMM2: case X86::XMM3:
1551 case X86::XMM4: case X86::XMM5: case X86::XMM6: case X86::XMM7: {
1552 // Special case: passing MMX values in XMM registers.
1553 Arg = DAG.getNode(ISD::BIT_CONVERT, MVT::i64, Arg);
1554 Arg = DAG.getNode(ISD::SCALAR_TO_VECTOR, MVT::v2i64, Arg);
1555 Arg = DAG.getNode(ISD::VECTOR_SHUFFLE, MVT::v2i64,
1556 DAG.getNode(ISD::UNDEF, MVT::v2i64), Arg,
1557 getMOVLMask(2, DAG));
1562 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
1564 if (!IsTailCall || (IsTailCall && isByVal)) {
1565 assert(VA.isMemLoc());
1566 if (StackPtr.getNode() == 0)
1567 StackPtr = DAG.getCopyFromReg(Chain, X86StackPtr, getPointerTy());
1569 MemOpChains.push_back(LowerMemOpCallTo(TheCall, DAG, StackPtr, VA,
1570 Chain, Arg, Flags));
1575 if (!MemOpChains.empty())
1576 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other,
1577 &MemOpChains[0], MemOpChains.size());
1579 // Build a sequence of copy-to-reg nodes chained together with token chain
1580 // and flag operands which copy the outgoing args into registers.
1582 // Tail call byval lowering might overwrite argument registers so in case of
1583 // tail call optimization the copies to registers are lowered later.
1585 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
1586 Chain = DAG.getCopyToReg(Chain, RegsToPass[i].first, RegsToPass[i].second,
1588 InFlag = Chain.getValue(1);
1591 // ELF / PIC requires GOT in the EBX register before function calls via PLT
1593 if (CallRequiresGOTPtrInReg(Is64Bit, IsTailCall)) {
1594 Chain = DAG.getCopyToReg(Chain, X86::EBX,
1595 DAG.getNode(X86ISD::GlobalBaseReg, getPointerTy()),
1597 InFlag = Chain.getValue(1);
1599 // If we are tail calling and generating PIC/GOT style code load the address
1600 // of the callee into ecx. The value in ecx is used as target of the tail
1601 // jump. This is done to circumvent the ebx/callee-saved problem for tail
1602 // calls on PIC/GOT architectures. Normally we would just put the address of
1603 // GOT into ebx and then call target@PLT. But for tail callss ebx would be
1604 // restored (since ebx is callee saved) before jumping to the target@PLT.
1605 if (CallRequiresFnAddressInReg(Is64Bit, IsTailCall)) {
1606 // Note: The actual moving to ecx is done further down.
1607 GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee);
1608 if (G && !G->getGlobal()->hasHiddenVisibility() &&
1609 !G->getGlobal()->hasProtectedVisibility())
1610 Callee = LowerGlobalAddress(Callee, DAG);
1611 else if (isa<ExternalSymbolSDNode>(Callee))
1612 Callee = LowerExternalSymbol(Callee,DAG);
1615 if (Is64Bit && isVarArg) {
1616 // From AMD64 ABI document:
1617 // For calls that may call functions that use varargs or stdargs
1618 // (prototype-less calls or calls to functions containing ellipsis (...) in
1619 // the declaration) %al is used as hidden argument to specify the number
1620 // of SSE registers used. The contents of %al do not need to match exactly
1621 // the number of registers, but must be an ubound on the number of SSE
1622 // registers used and is in the range 0 - 8 inclusive.
1624 // FIXME: Verify this on Win64
1625 // Count the number of XMM registers allocated.
1626 static const unsigned XMMArgRegs[] = {
1627 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
1628 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
1630 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs, 8);
1632 Chain = DAG.getCopyToReg(Chain, X86::AL,
1633 DAG.getConstant(NumXMMRegs, MVT::i8), InFlag);
1634 InFlag = Chain.getValue(1);
1638 // For tail calls lower the arguments to the 'real' stack slot.
1640 SmallVector<SDValue, 8> MemOpChains2;
1643 // Do not flag preceeding copytoreg stuff together with the following stuff.
1645 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1646 CCValAssign &VA = ArgLocs[i];
1647 if (!VA.isRegLoc()) {
1648 assert(VA.isMemLoc());
1649 SDValue Arg = TheCall->getArg(i);
1650 ISD::ArgFlagsTy Flags = TheCall->getArgFlags(i);
1651 // Create frame index.
1652 int32_t Offset = VA.getLocMemOffset()+FPDiff;
1653 uint32_t OpSize = (VA.getLocVT().getSizeInBits()+7)/8;
1654 FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset);
1655 FIN = DAG.getFrameIndex(FI, getPointerTy());
1657 if (Flags.isByVal()) {
1658 // Copy relative to framepointer.
1659 SDValue Source = DAG.getIntPtrConstant(VA.getLocMemOffset());
1660 if (StackPtr.getNode() == 0)
1661 StackPtr = DAG.getCopyFromReg(Chain, X86StackPtr, getPointerTy());
1662 Source = DAG.getNode(ISD::ADD, getPointerTy(), StackPtr, Source);
1664 MemOpChains2.push_back(CreateCopyOfByValArgument(Source, FIN, Chain,
1667 // Store relative to framepointer.
1668 MemOpChains2.push_back(
1669 DAG.getStore(Chain, Arg, FIN,
1670 PseudoSourceValue::getFixedStack(FI), 0));
1675 if (!MemOpChains2.empty())
1676 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other,
1677 &MemOpChains2[0], MemOpChains2.size());
1679 // Copy arguments to their registers.
1680 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
1681 Chain = DAG.getCopyToReg(Chain, RegsToPass[i].first, RegsToPass[i].second,
1683 InFlag = Chain.getValue(1);
1687 // Store the return address to the appropriate stack slot.
1688 Chain = EmitTailCallStoreRetAddr(DAG, MF, Chain, RetAddrFrIdx, Is64Bit,
1692 // If the callee is a GlobalAddress node (quite common, every direct call is)
1693 // turn it into a TargetGlobalAddress node so that legalize doesn't hack it.
1694 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
1695 // We should use extra load for direct calls to dllimported functions in
1697 if (!Subtarget->GVRequiresExtraLoad(G->getGlobal(),
1698 getTargetMachine(), true))
1699 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), getPointerTy());
1700 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
1701 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy());
1702 } else if (IsTailCall) {
1703 unsigned Opc = Is64Bit ? X86::R9 : X86::ECX;
1705 Chain = DAG.getCopyToReg(Chain,
1706 DAG.getRegister(Opc, getPointerTy()),
1708 Callee = DAG.getRegister(Opc, getPointerTy());
1709 // Add register as live out.
1710 DAG.getMachineFunction().getRegInfo().addLiveOut(Opc);
1713 // Returns a chain & a flag for retval copy to use.
1714 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
1715 SmallVector<SDValue, 8> Ops;
1718 Ops.push_back(Chain);
1719 Ops.push_back(DAG.getIntPtrConstant(NumBytes));
1720 Ops.push_back(DAG.getIntPtrConstant(0));
1721 if (InFlag.getNode())
1722 Ops.push_back(InFlag);
1723 Chain = DAG.getNode(ISD::CALLSEQ_END, NodeTys, &Ops[0], Ops.size());
1724 InFlag = Chain.getValue(1);
1726 // Returns a chain & a flag for retval copy to use.
1727 NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
1731 Ops.push_back(Chain);
1732 Ops.push_back(Callee);
1735 Ops.push_back(DAG.getConstant(FPDiff, MVT::i32));
1737 // Add argument registers to the end of the list so that they are known live
1739 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
1740 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
1741 RegsToPass[i].second.getValueType()));
1743 // Add an implicit use GOT pointer in EBX.
1744 if (!IsTailCall && !Is64Bit &&
1745 getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1746 Subtarget->isPICStyleGOT())
1747 Ops.push_back(DAG.getRegister(X86::EBX, getPointerTy()));
1749 // Add an implicit use of AL for x86 vararg functions.
1750 if (Is64Bit && isVarArg)
1751 Ops.push_back(DAG.getRegister(X86::AL, MVT::i8));
1753 if (InFlag.getNode())
1754 Ops.push_back(InFlag);
1757 assert(InFlag.getNode() &&
1758 "Flag must be set. Depend on flag being set in LowerRET");
1759 Chain = DAG.getNode(X86ISD::TAILCALL,
1760 TheCall->getVTList(), &Ops[0], Ops.size());
1762 return SDValue(Chain.getNode(), Op.getResNo());
1765 Chain = DAG.getNode(X86ISD::CALL, NodeTys, &Ops[0], Ops.size());
1766 InFlag = Chain.getValue(1);
1768 // Create the CALLSEQ_END node.
1769 unsigned NumBytesForCalleeToPush;
1770 if (IsCalleePop(isVarArg, CC))
1771 NumBytesForCalleeToPush = NumBytes; // Callee pops everything
1772 else if (!Is64Bit && CC != CallingConv::Fast && IsStructRet)
1773 // If this is is a call to a struct-return function, the callee
1774 // pops the hidden struct pointer, so we have to push it back.
1775 // This is common for Darwin/X86, Linux & Mingw32 targets.
1776 NumBytesForCalleeToPush = 4;
1778 NumBytesForCalleeToPush = 0; // Callee pops nothing.
1780 // Returns a flag for retval copy to use.
1781 Chain = DAG.getCALLSEQ_END(Chain,
1782 DAG.getIntPtrConstant(NumBytes),
1783 DAG.getIntPtrConstant(NumBytesForCalleeToPush),
1785 InFlag = Chain.getValue(1);
1787 // Handle result values, copying them out of physregs into vregs that we
1789 return SDValue(LowerCallResult(Chain, InFlag, TheCall, CC, DAG),
1794 //===----------------------------------------------------------------------===//
1795 // Fast Calling Convention (tail call) implementation
1796 //===----------------------------------------------------------------------===//
1798 // Like std call, callee cleans arguments, convention except that ECX is
1799 // reserved for storing the tail called function address. Only 2 registers are
1800 // free for argument passing (inreg). Tail call optimization is performed
1802 // * tailcallopt is enabled
1803 // * caller/callee are fastcc
1804 // On X86_64 architecture with GOT-style position independent code only local
1805 // (within module) calls are supported at the moment.
1806 // To keep the stack aligned according to platform abi the function
1807 // GetAlignedArgumentStackSize ensures that argument delta is always multiples
1808 // of stack alignment. (Dynamic linkers need this - darwin's dyld for example)
1809 // If a tail called function callee has more arguments than the caller the
1810 // caller needs to make sure that there is room to move the RETADDR to. This is
1811 // achieved by reserving an area the size of the argument delta right after the
1812 // original REtADDR, but before the saved framepointer or the spilled registers
1813 // e.g. caller(arg1, arg2) calls callee(arg1, arg2,arg3,arg4)
1825 /// GetAlignedArgumentStackSize - Make the stack size align e.g 16n + 12 aligned
1826 /// for a 16 byte align requirement.
1827 unsigned X86TargetLowering::GetAlignedArgumentStackSize(unsigned StackSize,
1828 SelectionDAG& DAG) {
1829 MachineFunction &MF = DAG.getMachineFunction();
1830 const TargetMachine &TM = MF.getTarget();
1831 const TargetFrameInfo &TFI = *TM.getFrameInfo();
1832 unsigned StackAlignment = TFI.getStackAlignment();
1833 uint64_t AlignMask = StackAlignment - 1;
1834 int64_t Offset = StackSize;
1835 uint64_t SlotSize = TD->getPointerSize();
1836 if ( (Offset & AlignMask) <= (StackAlignment - SlotSize) ) {
1837 // Number smaller than 12 so just add the difference.
1838 Offset += ((StackAlignment - SlotSize) - (Offset & AlignMask));
1840 // Mask out lower bits, add stackalignment once plus the 12 bytes.
1841 Offset = ((~AlignMask) & Offset) + StackAlignment +
1842 (StackAlignment-SlotSize);
1847 /// IsEligibleForTailCallElimination - Check to see whether the next instruction
1848 /// following the call is a return. A function is eligible if caller/callee
1849 /// calling conventions match, currently only fastcc supports tail calls, and
1850 /// the function CALL is immediatly followed by a RET.
1851 bool X86TargetLowering::IsEligibleForTailCallOptimization(CallSDNode *TheCall,
1853 SelectionDAG& DAG) const {
1854 if (!PerformTailCallOpt)
1857 if (CheckTailCallReturnConstraints(TheCall, Ret)) {
1858 MachineFunction &MF = DAG.getMachineFunction();
1859 unsigned CallerCC = MF.getFunction()->getCallingConv();
1860 unsigned CalleeCC= TheCall->getCallingConv();
1861 if (CalleeCC == CallingConv::Fast && CallerCC == CalleeCC) {
1862 SDValue Callee = TheCall->getCallee();
1863 // On x86/32Bit PIC/GOT tail calls are supported.
1864 if (getTargetMachine().getRelocationModel() != Reloc::PIC_ ||
1865 !Subtarget->isPICStyleGOT()|| !Subtarget->is64Bit())
1868 // Can only do local tail calls (in same module, hidden or protected) on
1869 // x86_64 PIC/GOT at the moment.
1870 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
1871 return G->getGlobal()->hasHiddenVisibility()
1872 || G->getGlobal()->hasProtectedVisibility();
1880 X86TargetLowering::createFastISel(MachineFunction &mf,
1881 DenseMap<const Value *, unsigned> &vm,
1882 DenseMap<const BasicBlock *,
1883 MachineBasicBlock *> &bm,
1884 DenseMap<const AllocaInst *, int> &am) {
1886 return X86::createFastISel(mf, vm, bm, am);
1890 //===----------------------------------------------------------------------===//
1891 // Other Lowering Hooks
1892 //===----------------------------------------------------------------------===//
1895 SDValue X86TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) {
1896 MachineFunction &MF = DAG.getMachineFunction();
1897 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1898 int ReturnAddrIndex = FuncInfo->getRAIndex();
1899 uint64_t SlotSize = TD->getPointerSize();
1901 if (ReturnAddrIndex == 0) {
1902 // Set up a frame object for the return address.
1903 ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(SlotSize, -SlotSize);
1904 FuncInfo->setRAIndex(ReturnAddrIndex);
1907 return DAG.getFrameIndex(ReturnAddrIndex, getPointerTy());
1911 /// translateX86CC - do a one to one translation of a ISD::CondCode to the X86
1912 /// specific condition code. It returns a false if it cannot do a direct
1913 /// translation. X86CC is the translated CondCode. LHS/RHS are modified as
1915 static bool translateX86CC(ISD::CondCode SetCCOpcode, bool isFP,
1916 unsigned &X86CC, SDValue &LHS, SDValue &RHS,
1917 SelectionDAG &DAG) {
1918 X86CC = X86::COND_INVALID;
1920 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
1921 if (SetCCOpcode == ISD::SETGT && RHSC->isAllOnesValue()) {
1922 // X > -1 -> X == 0, jump !sign.
1923 RHS = DAG.getConstant(0, RHS.getValueType());
1924 X86CC = X86::COND_NS;
1926 } else if (SetCCOpcode == ISD::SETLT && RHSC->isNullValue()) {
1927 // X < 0 -> X == 0, jump on sign.
1928 X86CC = X86::COND_S;
1930 } else if (SetCCOpcode == ISD::SETLT && RHSC->getZExtValue() == 1) {
1932 RHS = DAG.getConstant(0, RHS.getValueType());
1933 X86CC = X86::COND_LE;
1938 switch (SetCCOpcode) {
1940 case ISD::SETEQ: X86CC = X86::COND_E; break;
1941 case ISD::SETGT: X86CC = X86::COND_G; break;
1942 case ISD::SETGE: X86CC = X86::COND_GE; break;
1943 case ISD::SETLT: X86CC = X86::COND_L; break;
1944 case ISD::SETLE: X86CC = X86::COND_LE; break;
1945 case ISD::SETNE: X86CC = X86::COND_NE; break;
1946 case ISD::SETULT: X86CC = X86::COND_B; break;
1947 case ISD::SETUGT: X86CC = X86::COND_A; break;
1948 case ISD::SETULE: X86CC = X86::COND_BE; break;
1949 case ISD::SETUGE: X86CC = X86::COND_AE; break;
1952 // First determine if it requires or is profitable to flip the operands.
1954 switch (SetCCOpcode) {
1964 // If LHS is a foldable load, but RHS is not, flip the condition.
1966 (ISD::isNON_EXTLoad(LHS.getNode()) && LHS.hasOneUse()) &&
1967 !(ISD::isNON_EXTLoad(RHS.getNode()) && RHS.hasOneUse())) {
1968 SetCCOpcode = getSetCCSwappedOperands(SetCCOpcode);
1972 std::swap(LHS, RHS);
1974 // On a floating point condition, the flags are set as follows:
1976 // 0 | 0 | 0 | X > Y
1977 // 0 | 0 | 1 | X < Y
1978 // 1 | 0 | 0 | X == Y
1979 // 1 | 1 | 1 | unordered
1980 switch (SetCCOpcode) {
1984 X86CC = X86::COND_E;
1986 case ISD::SETOLT: // flipped
1989 X86CC = X86::COND_A;
1991 case ISD::SETOLE: // flipped
1994 X86CC = X86::COND_AE;
1996 case ISD::SETUGT: // flipped
1999 X86CC = X86::COND_B;
2001 case ISD::SETUGE: // flipped
2004 X86CC = X86::COND_BE;
2008 X86CC = X86::COND_NE;
2011 X86CC = X86::COND_P;
2014 X86CC = X86::COND_NP;
2019 return X86CC != X86::COND_INVALID;
2022 /// hasFPCMov - is there a floating point cmov for the specific X86 condition
2023 /// code. Current x86 isa includes the following FP cmov instructions:
2024 /// fcmovb, fcomvbe, fcomve, fcmovu, fcmovae, fcmova, fcmovne, fcmovnu.
2025 static bool hasFPCMov(unsigned X86CC) {
2041 /// isUndefOrInRange - Op is either an undef node or a ConstantSDNode. Return
2042 /// true if Op is undef or if its value falls within the specified range (L, H].
2043 static bool isUndefOrInRange(SDValue Op, unsigned Low, unsigned Hi) {
2044 if (Op.getOpcode() == ISD::UNDEF)
2047 unsigned Val = cast<ConstantSDNode>(Op)->getZExtValue();
2048 return (Val >= Low && Val < Hi);
2051 /// isUndefOrEqual - Op is either an undef node or a ConstantSDNode. Return
2052 /// true if Op is undef or if its value equal to the specified value.
2053 static bool isUndefOrEqual(SDValue Op, unsigned Val) {
2054 if (Op.getOpcode() == ISD::UNDEF)
2056 return cast<ConstantSDNode>(Op)->getZExtValue() == Val;
2059 /// isPSHUFDMask - Return true if the specified VECTOR_SHUFFLE operand
2060 /// specifies a shuffle of elements that is suitable for input to PSHUFD.
2061 bool X86::isPSHUFDMask(SDNode *N) {
2062 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2064 if (N->getNumOperands() != 2 && N->getNumOperands() != 4)
2067 // Check if the value doesn't reference the second vector.
2068 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
2069 SDValue Arg = N->getOperand(i);
2070 if (Arg.getOpcode() == ISD::UNDEF) continue;
2071 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
2072 if (cast<ConstantSDNode>(Arg)->getZExtValue() >= e)
2079 /// isPSHUFHWMask - Return true if the specified VECTOR_SHUFFLE operand
2080 /// specifies a shuffle of elements that is suitable for input to PSHUFHW.
2081 bool X86::isPSHUFHWMask(SDNode *N) {
2082 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2084 if (N->getNumOperands() != 8)
2087 // Lower quadword copied in order.
2088 for (unsigned i = 0; i != 4; ++i) {
2089 SDValue Arg = N->getOperand(i);
2090 if (Arg.getOpcode() == ISD::UNDEF) continue;
2091 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
2092 if (cast<ConstantSDNode>(Arg)->getZExtValue() != i)
2096 // Upper quadword shuffled.
2097 for (unsigned i = 4; i != 8; ++i) {
2098 SDValue Arg = N->getOperand(i);
2099 if (Arg.getOpcode() == ISD::UNDEF) continue;
2100 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
2101 unsigned Val = cast<ConstantSDNode>(Arg)->getZExtValue();
2102 if (Val < 4 || Val > 7)
2109 /// isPSHUFLWMask - Return true if the specified VECTOR_SHUFFLE operand
2110 /// specifies a shuffle of elements that is suitable for input to PSHUFLW.
2111 bool X86::isPSHUFLWMask(SDNode *N) {
2112 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2114 if (N->getNumOperands() != 8)
2117 // Upper quadword copied in order.
2118 for (unsigned i = 4; i != 8; ++i)
2119 if (!isUndefOrEqual(N->getOperand(i), i))
2122 // Lower quadword shuffled.
2123 for (unsigned i = 0; i != 4; ++i)
2124 if (!isUndefOrInRange(N->getOperand(i), 0, 4))
2130 /// isSHUFPMask - Return true if the specified VECTOR_SHUFFLE operand
2131 /// specifies a shuffle of elements that is suitable for input to SHUFP*.
2132 static bool isSHUFPMask(SDOperandPtr Elems, unsigned NumElems) {
2133 if (NumElems != 2 && NumElems != 4) return false;
2135 unsigned Half = NumElems / 2;
2136 for (unsigned i = 0; i < Half; ++i)
2137 if (!isUndefOrInRange(Elems[i], 0, NumElems))
2139 for (unsigned i = Half; i < NumElems; ++i)
2140 if (!isUndefOrInRange(Elems[i], NumElems, NumElems*2))
2146 bool X86::isSHUFPMask(SDNode *N) {
2147 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2148 return ::isSHUFPMask(N->op_begin(), N->getNumOperands());
2151 /// isCommutedSHUFP - Returns true if the shuffle mask is exactly
2152 /// the reverse of what x86 shuffles want. x86 shuffles requires the lower
2153 /// half elements to come from vector 1 (which would equal the dest.) and
2154 /// the upper half to come from vector 2.
2155 static bool isCommutedSHUFP(SDOperandPtr Ops, unsigned NumOps) {
2156 if (NumOps != 2 && NumOps != 4) return false;
2158 unsigned Half = NumOps / 2;
2159 for (unsigned i = 0; i < Half; ++i)
2160 if (!isUndefOrInRange(Ops[i], NumOps, NumOps*2))
2162 for (unsigned i = Half; i < NumOps; ++i)
2163 if (!isUndefOrInRange(Ops[i], 0, NumOps))
2168 static bool isCommutedSHUFP(SDNode *N) {
2169 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2170 return isCommutedSHUFP(N->op_begin(), N->getNumOperands());
2173 /// isMOVHLPSMask - Return true if the specified VECTOR_SHUFFLE operand
2174 /// specifies a shuffle of elements that is suitable for input to MOVHLPS.
2175 bool X86::isMOVHLPSMask(SDNode *N) {
2176 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2178 if (N->getNumOperands() != 4)
2181 // Expect bit0 == 6, bit1 == 7, bit2 == 2, bit3 == 3
2182 return isUndefOrEqual(N->getOperand(0), 6) &&
2183 isUndefOrEqual(N->getOperand(1), 7) &&
2184 isUndefOrEqual(N->getOperand(2), 2) &&
2185 isUndefOrEqual(N->getOperand(3), 3);
2188 /// isMOVHLPS_v_undef_Mask - Special case of isMOVHLPSMask for canonical form
2189 /// of vector_shuffle v, v, <2, 3, 2, 3>, i.e. vector_shuffle v, undef,
2191 bool X86::isMOVHLPS_v_undef_Mask(SDNode *N) {
2192 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2194 if (N->getNumOperands() != 4)
2197 // Expect bit0 == 2, bit1 == 3, bit2 == 2, bit3 == 3
2198 return isUndefOrEqual(N->getOperand(0), 2) &&
2199 isUndefOrEqual(N->getOperand(1), 3) &&
2200 isUndefOrEqual(N->getOperand(2), 2) &&
2201 isUndefOrEqual(N->getOperand(3), 3);
2204 /// isMOVLPMask - Return true if the specified VECTOR_SHUFFLE operand
2205 /// specifies a shuffle of elements that is suitable for input to MOVLP{S|D}.
2206 bool X86::isMOVLPMask(SDNode *N) {
2207 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2209 unsigned NumElems = N->getNumOperands();
2210 if (NumElems != 2 && NumElems != 4)
2213 for (unsigned i = 0; i < NumElems/2; ++i)
2214 if (!isUndefOrEqual(N->getOperand(i), i + NumElems))
2217 for (unsigned i = NumElems/2; i < NumElems; ++i)
2218 if (!isUndefOrEqual(N->getOperand(i), i))
2224 /// isMOVHPMask - Return true if the specified VECTOR_SHUFFLE operand
2225 /// specifies a shuffle of elements that is suitable for input to MOVHP{S|D}
2227 bool X86::isMOVHPMask(SDNode *N) {
2228 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2230 unsigned NumElems = N->getNumOperands();
2231 if (NumElems != 2 && NumElems != 4)
2234 for (unsigned i = 0; i < NumElems/2; ++i)
2235 if (!isUndefOrEqual(N->getOperand(i), i))
2238 for (unsigned i = 0; i < NumElems/2; ++i) {
2239 SDValue Arg = N->getOperand(i + NumElems/2);
2240 if (!isUndefOrEqual(Arg, i + NumElems))
2247 /// isUNPCKLMask - Return true if the specified VECTOR_SHUFFLE operand
2248 /// specifies a shuffle of elements that is suitable for input to UNPCKL.
2249 bool static isUNPCKLMask(SDOperandPtr Elts, unsigned NumElts,
2250 bool V2IsSplat = false) {
2251 if (NumElts != 2 && NumElts != 4 && NumElts != 8 && NumElts != 16)
2254 for (unsigned i = 0, j = 0; i != NumElts; i += 2, ++j) {
2255 SDValue BitI = Elts[i];
2256 SDValue BitI1 = Elts[i+1];
2257 if (!isUndefOrEqual(BitI, j))
2260 if (isUndefOrEqual(BitI1, NumElts))
2263 if (!isUndefOrEqual(BitI1, j + NumElts))
2271 bool X86::isUNPCKLMask(SDNode *N, bool V2IsSplat) {
2272 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2273 return ::isUNPCKLMask(N->op_begin(), N->getNumOperands(), V2IsSplat);
2276 /// isUNPCKHMask - Return true if the specified VECTOR_SHUFFLE operand
2277 /// specifies a shuffle of elements that is suitable for input to UNPCKH.
2278 bool static isUNPCKHMask(SDOperandPtr Elts, unsigned NumElts,
2279 bool V2IsSplat = false) {
2280 if (NumElts != 2 && NumElts != 4 && NumElts != 8 && NumElts != 16)
2283 for (unsigned i = 0, j = 0; i != NumElts; i += 2, ++j) {
2284 SDValue BitI = Elts[i];
2285 SDValue BitI1 = Elts[i+1];
2286 if (!isUndefOrEqual(BitI, j + NumElts/2))
2289 if (isUndefOrEqual(BitI1, NumElts))
2292 if (!isUndefOrEqual(BitI1, j + NumElts/2 + NumElts))
2300 bool X86::isUNPCKHMask(SDNode *N, bool V2IsSplat) {
2301 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2302 return ::isUNPCKHMask(N->op_begin(), N->getNumOperands(), V2IsSplat);
2305 /// isUNPCKL_v_undef_Mask - Special case of isUNPCKLMask for canonical form
2306 /// of vector_shuffle v, v, <0, 4, 1, 5>, i.e. vector_shuffle v, undef,
2308 bool X86::isUNPCKL_v_undef_Mask(SDNode *N) {
2309 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2311 unsigned NumElems = N->getNumOperands();
2312 if (NumElems != 2 && NumElems != 4 && NumElems != 8 && NumElems != 16)
2315 for (unsigned i = 0, j = 0; i != NumElems; i += 2, ++j) {
2316 SDValue BitI = N->getOperand(i);
2317 SDValue BitI1 = N->getOperand(i+1);
2319 if (!isUndefOrEqual(BitI, j))
2321 if (!isUndefOrEqual(BitI1, j))
2328 /// isUNPCKH_v_undef_Mask - Special case of isUNPCKHMask for canonical form
2329 /// of vector_shuffle v, v, <2, 6, 3, 7>, i.e. vector_shuffle v, undef,
2331 bool X86::isUNPCKH_v_undef_Mask(SDNode *N) {
2332 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2334 unsigned NumElems = N->getNumOperands();
2335 if (NumElems != 2 && NumElems != 4 && NumElems != 8 && NumElems != 16)
2338 for (unsigned i = 0, j = NumElems / 2; i != NumElems; i += 2, ++j) {
2339 SDValue BitI = N->getOperand(i);
2340 SDValue BitI1 = N->getOperand(i + 1);
2342 if (!isUndefOrEqual(BitI, j))
2344 if (!isUndefOrEqual(BitI1, j))
2351 /// isMOVLMask - Return true if the specified VECTOR_SHUFFLE operand
2352 /// specifies a shuffle of elements that is suitable for input to MOVSS,
2353 /// MOVSD, and MOVD, i.e. setting the lowest element.
2354 static bool isMOVLMask(SDOperandPtr Elts, unsigned NumElts) {
2355 if (NumElts != 2 && NumElts != 4)
2358 if (!isUndefOrEqual(Elts[0], NumElts))
2361 for (unsigned i = 1; i < NumElts; ++i) {
2362 if (!isUndefOrEqual(Elts[i], i))
2369 bool X86::isMOVLMask(SDNode *N) {
2370 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2371 return ::isMOVLMask(N->op_begin(), N->getNumOperands());
2374 /// isCommutedMOVL - Returns true if the shuffle mask is except the reverse
2375 /// of what x86 movss want. X86 movs requires the lowest element to be lowest
2376 /// element of vector 2 and the other elements to come from vector 1 in order.
2377 static bool isCommutedMOVL(SDOperandPtr Ops, unsigned NumOps,
2378 bool V2IsSplat = false,
2379 bool V2IsUndef = false) {
2380 if (NumOps != 2 && NumOps != 4 && NumOps != 8 && NumOps != 16)
2383 if (!isUndefOrEqual(Ops[0], 0))
2386 for (unsigned i = 1; i < NumOps; ++i) {
2387 SDValue Arg = Ops[i];
2388 if (!(isUndefOrEqual(Arg, i+NumOps) ||
2389 (V2IsUndef && isUndefOrInRange(Arg, NumOps, NumOps*2)) ||
2390 (V2IsSplat && isUndefOrEqual(Arg, NumOps))))
2397 static bool isCommutedMOVL(SDNode *N, bool V2IsSplat = false,
2398 bool V2IsUndef = false) {
2399 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2400 return isCommutedMOVL(N->op_begin(), N->getNumOperands(),
2401 V2IsSplat, V2IsUndef);
2404 /// isMOVSHDUPMask - Return true if the specified VECTOR_SHUFFLE operand
2405 /// specifies a shuffle of elements that is suitable for input to MOVSHDUP.
2406 bool X86::isMOVSHDUPMask(SDNode *N) {
2407 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2409 if (N->getNumOperands() != 4)
2412 // Expect 1, 1, 3, 3
2413 for (unsigned i = 0; i < 2; ++i) {
2414 SDValue Arg = N->getOperand(i);
2415 if (Arg.getOpcode() == ISD::UNDEF) continue;
2416 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
2417 unsigned Val = cast<ConstantSDNode>(Arg)->getZExtValue();
2418 if (Val != 1) return false;
2422 for (unsigned i = 2; i < 4; ++i) {
2423 SDValue Arg = N->getOperand(i);
2424 if (Arg.getOpcode() == ISD::UNDEF) continue;
2425 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
2426 unsigned Val = cast<ConstantSDNode>(Arg)->getZExtValue();
2427 if (Val != 3) return false;
2431 // Don't use movshdup if it can be done with a shufps.
2435 /// isMOVSLDUPMask - Return true if the specified VECTOR_SHUFFLE operand
2436 /// specifies a shuffle of elements that is suitable for input to MOVSLDUP.
2437 bool X86::isMOVSLDUPMask(SDNode *N) {
2438 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2440 if (N->getNumOperands() != 4)
2443 // Expect 0, 0, 2, 2
2444 for (unsigned i = 0; i < 2; ++i) {
2445 SDValue Arg = N->getOperand(i);
2446 if (Arg.getOpcode() == ISD::UNDEF) continue;
2447 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
2448 unsigned Val = cast<ConstantSDNode>(Arg)->getZExtValue();
2449 if (Val != 0) return false;
2453 for (unsigned i = 2; i < 4; ++i) {
2454 SDValue Arg = N->getOperand(i);
2455 if (Arg.getOpcode() == ISD::UNDEF) continue;
2456 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
2457 unsigned Val = cast<ConstantSDNode>(Arg)->getZExtValue();
2458 if (Val != 2) return false;
2462 // Don't use movshdup if it can be done with a shufps.
2466 /// isIdentityMask - Return true if the specified VECTOR_SHUFFLE operand
2467 /// specifies a identity operation on the LHS or RHS.
2468 static bool isIdentityMask(SDNode *N, bool RHS = false) {
2469 unsigned NumElems = N->getNumOperands();
2470 for (unsigned i = 0; i < NumElems; ++i)
2471 if (!isUndefOrEqual(N->getOperand(i), i + (RHS ? NumElems : 0)))
2476 /// isSplatMask - Return true if the specified VECTOR_SHUFFLE operand specifies
2477 /// a splat of a single element.
2478 static bool isSplatMask(SDNode *N) {
2479 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2481 // This is a splat operation if each element of the permute is the same, and
2482 // if the value doesn't reference the second vector.
2483 unsigned NumElems = N->getNumOperands();
2484 SDValue ElementBase;
2486 for (; i != NumElems; ++i) {
2487 SDValue Elt = N->getOperand(i);
2488 if (isa<ConstantSDNode>(Elt)) {
2494 if (!ElementBase.getNode())
2497 for (; i != NumElems; ++i) {
2498 SDValue Arg = N->getOperand(i);
2499 if (Arg.getOpcode() == ISD::UNDEF) continue;
2500 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
2501 if (Arg != ElementBase) return false;
2504 // Make sure it is a splat of the first vector operand.
2505 return cast<ConstantSDNode>(ElementBase)->getZExtValue() < NumElems;
2508 /// isSplatMask - Return true if the specified VECTOR_SHUFFLE operand specifies
2509 /// a splat of a single element and it's a 2 or 4 element mask.
2510 bool X86::isSplatMask(SDNode *N) {
2511 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2513 // We can only splat 64-bit, and 32-bit quantities with a single instruction.
2514 if (N->getNumOperands() != 4 && N->getNumOperands() != 2)
2516 return ::isSplatMask(N);
2519 /// isSplatLoMask - Return true if the specified VECTOR_SHUFFLE operand
2520 /// specifies a splat of zero element.
2521 bool X86::isSplatLoMask(SDNode *N) {
2522 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2524 for (unsigned i = 0, e = N->getNumOperands(); i < e; ++i)
2525 if (!isUndefOrEqual(N->getOperand(i), 0))
2530 /// getShuffleSHUFImmediate - Return the appropriate immediate to shuffle
2531 /// the specified isShuffleMask VECTOR_SHUFFLE mask with PSHUF* and SHUFP*
2533 unsigned X86::getShuffleSHUFImmediate(SDNode *N) {
2534 unsigned NumOperands = N->getNumOperands();
2535 unsigned Shift = (NumOperands == 4) ? 2 : 1;
2537 for (unsigned i = 0; i < NumOperands; ++i) {
2539 SDValue Arg = N->getOperand(NumOperands-i-1);
2540 if (Arg.getOpcode() != ISD::UNDEF)
2541 Val = cast<ConstantSDNode>(Arg)->getZExtValue();
2542 if (Val >= NumOperands) Val -= NumOperands;
2544 if (i != NumOperands - 1)
2551 /// getShufflePSHUFHWImmediate - Return the appropriate immediate to shuffle
2552 /// the specified isShuffleMask VECTOR_SHUFFLE mask with PSHUFHW
2554 unsigned X86::getShufflePSHUFHWImmediate(SDNode *N) {
2556 // 8 nodes, but we only care about the last 4.
2557 for (unsigned i = 7; i >= 4; --i) {
2559 SDValue Arg = N->getOperand(i);
2560 if (Arg.getOpcode() != ISD::UNDEF)
2561 Val = cast<ConstantSDNode>(Arg)->getZExtValue();
2570 /// getShufflePSHUFLWImmediate - Return the appropriate immediate to shuffle
2571 /// the specified isShuffleMask VECTOR_SHUFFLE mask with PSHUFLW
2573 unsigned X86::getShufflePSHUFLWImmediate(SDNode *N) {
2575 // 8 nodes, but we only care about the first 4.
2576 for (int i = 3; i >= 0; --i) {
2578 SDValue Arg = N->getOperand(i);
2579 if (Arg.getOpcode() != ISD::UNDEF)
2580 Val = cast<ConstantSDNode>(Arg)->getZExtValue();
2589 /// isPSHUFHW_PSHUFLWMask - true if the specified VECTOR_SHUFFLE operand
2590 /// specifies a 8 element shuffle that can be broken into a pair of
2591 /// PSHUFHW and PSHUFLW.
2592 static bool isPSHUFHW_PSHUFLWMask(SDNode *N) {
2593 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2595 if (N->getNumOperands() != 8)
2598 // Lower quadword shuffled.
2599 for (unsigned i = 0; i != 4; ++i) {
2600 SDValue Arg = N->getOperand(i);
2601 if (Arg.getOpcode() == ISD::UNDEF) continue;
2602 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
2603 unsigned Val = cast<ConstantSDNode>(Arg)->getZExtValue();
2608 // Upper quadword shuffled.
2609 for (unsigned i = 4; i != 8; ++i) {
2610 SDValue Arg = N->getOperand(i);
2611 if (Arg.getOpcode() == ISD::UNDEF) continue;
2612 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
2613 unsigned Val = cast<ConstantSDNode>(Arg)->getZExtValue();
2614 if (Val < 4 || Val > 7)
2621 /// CommuteVectorShuffle - Swap vector_shuffle operands as well as
2622 /// values in ther permute mask.
2623 static SDValue CommuteVectorShuffle(SDValue Op, SDValue &V1,
2624 SDValue &V2, SDValue &Mask,
2625 SelectionDAG &DAG) {
2626 MVT VT = Op.getValueType();
2627 MVT MaskVT = Mask.getValueType();
2628 MVT EltVT = MaskVT.getVectorElementType();
2629 unsigned NumElems = Mask.getNumOperands();
2630 SmallVector<SDValue, 8> MaskVec;
2632 for (unsigned i = 0; i != NumElems; ++i) {
2633 SDValue Arg = Mask.getOperand(i);
2634 if (Arg.getOpcode() == ISD::UNDEF) {
2635 MaskVec.push_back(DAG.getNode(ISD::UNDEF, EltVT));
2638 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
2639 unsigned Val = cast<ConstantSDNode>(Arg)->getZExtValue();
2641 MaskVec.push_back(DAG.getConstant(Val + NumElems, EltVT));
2643 MaskVec.push_back(DAG.getConstant(Val - NumElems, EltVT));
2647 Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT, &MaskVec[0], NumElems);
2648 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2, Mask);
2651 /// CommuteVectorShuffleMask - Change values in a shuffle permute mask assuming
2652 /// the two vector operands have swapped position.
2654 SDValue CommuteVectorShuffleMask(SDValue Mask, SelectionDAG &DAG) {
2655 MVT MaskVT = Mask.getValueType();
2656 MVT EltVT = MaskVT.getVectorElementType();
2657 unsigned NumElems = Mask.getNumOperands();
2658 SmallVector<SDValue, 8> MaskVec;
2659 for (unsigned i = 0; i != NumElems; ++i) {
2660 SDValue Arg = Mask.getOperand(i);
2661 if (Arg.getOpcode() == ISD::UNDEF) {
2662 MaskVec.push_back(DAG.getNode(ISD::UNDEF, EltVT));
2665 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
2666 unsigned Val = cast<ConstantSDNode>(Arg)->getZExtValue();
2668 MaskVec.push_back(DAG.getConstant(Val + NumElems, EltVT));
2670 MaskVec.push_back(DAG.getConstant(Val - NumElems, EltVT));
2672 return DAG.getNode(ISD::BUILD_VECTOR, MaskVT, &MaskVec[0], NumElems);
2676 /// ShouldXformToMOVHLPS - Return true if the node should be transformed to
2677 /// match movhlps. The lower half elements should come from upper half of
2678 /// V1 (and in order), and the upper half elements should come from the upper
2679 /// half of V2 (and in order).
2680 static bool ShouldXformToMOVHLPS(SDNode *Mask) {
2681 unsigned NumElems = Mask->getNumOperands();
2684 for (unsigned i = 0, e = 2; i != e; ++i)
2685 if (!isUndefOrEqual(Mask->getOperand(i), i+2))
2687 for (unsigned i = 2; i != 4; ++i)
2688 if (!isUndefOrEqual(Mask->getOperand(i), i+4))
2693 /// isScalarLoadToVector - Returns true if the node is a scalar load that
2694 /// is promoted to a vector. It also returns the LoadSDNode by reference if
2696 static bool isScalarLoadToVector(SDNode *N, LoadSDNode **LD = NULL) {
2697 if (N->getOpcode() == ISD::SCALAR_TO_VECTOR) {
2698 N = N->getOperand(0).getNode();
2699 if (ISD::isNON_EXTLoad(N)) {
2701 *LD = cast<LoadSDNode>(N);
2708 /// ShouldXformToMOVLP{S|D} - Return true if the node should be transformed to
2709 /// match movlp{s|d}. The lower half elements should come from lower half of
2710 /// V1 (and in order), and the upper half elements should come from the upper
2711 /// half of V2 (and in order). And since V1 will become the source of the
2712 /// MOVLP, it must be either a vector load or a scalar load to vector.
2713 static bool ShouldXformToMOVLP(SDNode *V1, SDNode *V2, SDNode *Mask) {
2714 if (!ISD::isNON_EXTLoad(V1) && !isScalarLoadToVector(V1))
2716 // Is V2 is a vector load, don't do this transformation. We will try to use
2717 // load folding shufps op.
2718 if (ISD::isNON_EXTLoad(V2))
2721 unsigned NumElems = Mask->getNumOperands();
2722 if (NumElems != 2 && NumElems != 4)
2724 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
2725 if (!isUndefOrEqual(Mask->getOperand(i), i))
2727 for (unsigned i = NumElems/2; i != NumElems; ++i)
2728 if (!isUndefOrEqual(Mask->getOperand(i), i+NumElems))
2733 /// isSplatVector - Returns true if N is a BUILD_VECTOR node whose elements are
2735 static bool isSplatVector(SDNode *N) {
2736 if (N->getOpcode() != ISD::BUILD_VECTOR)
2739 SDValue SplatValue = N->getOperand(0);
2740 for (unsigned i = 1, e = N->getNumOperands(); i != e; ++i)
2741 if (N->getOperand(i) != SplatValue)
2746 /// isUndefShuffle - Returns true if N is a VECTOR_SHUFFLE that can be resolved
2748 static bool isUndefShuffle(SDNode *N) {
2749 if (N->getOpcode() != ISD::VECTOR_SHUFFLE)
2752 SDValue V1 = N->getOperand(0);
2753 SDValue V2 = N->getOperand(1);
2754 SDValue Mask = N->getOperand(2);
2755 unsigned NumElems = Mask.getNumOperands();
2756 for (unsigned i = 0; i != NumElems; ++i) {
2757 SDValue Arg = Mask.getOperand(i);
2758 if (Arg.getOpcode() != ISD::UNDEF) {
2759 unsigned Val = cast<ConstantSDNode>(Arg)->getZExtValue();
2760 if (Val < NumElems && V1.getOpcode() != ISD::UNDEF)
2762 else if (Val >= NumElems && V2.getOpcode() != ISD::UNDEF)
2769 /// isZeroNode - Returns true if Elt is a constant zero or a floating point
2771 static inline bool isZeroNode(SDValue Elt) {
2772 return ((isa<ConstantSDNode>(Elt) &&
2773 cast<ConstantSDNode>(Elt)->getZExtValue() == 0) ||
2774 (isa<ConstantFPSDNode>(Elt) &&
2775 cast<ConstantFPSDNode>(Elt)->getValueAPF().isPosZero()));
2778 /// isZeroShuffle - Returns true if N is a VECTOR_SHUFFLE that can be resolved
2779 /// to an zero vector.
2780 static bool isZeroShuffle(SDNode *N) {
2781 if (N->getOpcode() != ISD::VECTOR_SHUFFLE)
2784 SDValue V1 = N->getOperand(0);
2785 SDValue V2 = N->getOperand(1);
2786 SDValue Mask = N->getOperand(2);
2787 unsigned NumElems = Mask.getNumOperands();
2788 for (unsigned i = 0; i != NumElems; ++i) {
2789 SDValue Arg = Mask.getOperand(i);
2790 if (Arg.getOpcode() == ISD::UNDEF)
2793 unsigned Idx = cast<ConstantSDNode>(Arg)->getZExtValue();
2794 if (Idx < NumElems) {
2795 unsigned Opc = V1.getNode()->getOpcode();
2796 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V1.getNode()))
2798 if (Opc != ISD::BUILD_VECTOR ||
2799 !isZeroNode(V1.getNode()->getOperand(Idx)))
2801 } else if (Idx >= NumElems) {
2802 unsigned Opc = V2.getNode()->getOpcode();
2803 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V2.getNode()))
2805 if (Opc != ISD::BUILD_VECTOR ||
2806 !isZeroNode(V2.getNode()->getOperand(Idx - NumElems)))
2813 /// getZeroVector - Returns a vector of specified type with all zero elements.
2815 static SDValue getZeroVector(MVT VT, bool HasSSE2, SelectionDAG &DAG) {
2816 assert(VT.isVector() && "Expected a vector type");
2818 // Always build zero vectors as <4 x i32> or <2 x i32> bitcasted to their dest
2819 // type. This ensures they get CSE'd.
2821 if (VT.getSizeInBits() == 64) { // MMX
2822 SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
2823 Vec = DAG.getNode(ISD::BUILD_VECTOR, MVT::v2i32, Cst, Cst);
2824 } else if (HasSSE2) { // SSE2
2825 SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
2826 Vec = DAG.getNode(ISD::BUILD_VECTOR, MVT::v4i32, Cst, Cst, Cst, Cst);
2828 SDValue Cst = DAG.getTargetConstantFP(+0.0, MVT::f32);
2829 Vec = DAG.getNode(ISD::BUILD_VECTOR, MVT::v4f32, Cst, Cst, Cst, Cst);
2831 return DAG.getNode(ISD::BIT_CONVERT, VT, Vec);
2834 /// getOnesVector - Returns a vector of specified type with all bits set.
2836 static SDValue getOnesVector(MVT VT, SelectionDAG &DAG) {
2837 assert(VT.isVector() && "Expected a vector type");
2839 // Always build ones vectors as <4 x i32> or <2 x i32> bitcasted to their dest
2840 // type. This ensures they get CSE'd.
2841 SDValue Cst = DAG.getTargetConstant(~0U, MVT::i32);
2843 if (VT.getSizeInBits() == 64) // MMX
2844 Vec = DAG.getNode(ISD::BUILD_VECTOR, MVT::v2i32, Cst, Cst);
2846 Vec = DAG.getNode(ISD::BUILD_VECTOR, MVT::v4i32, Cst, Cst, Cst, Cst);
2847 return DAG.getNode(ISD::BIT_CONVERT, VT, Vec);
2851 /// NormalizeMask - V2 is a splat, modify the mask (if needed) so all elements
2852 /// that point to V2 points to its first element.
2853 static SDValue NormalizeMask(SDValue Mask, SelectionDAG &DAG) {
2854 assert(Mask.getOpcode() == ISD::BUILD_VECTOR);
2856 bool Changed = false;
2857 SmallVector<SDValue, 8> MaskVec;
2858 unsigned NumElems = Mask.getNumOperands();
2859 for (unsigned i = 0; i != NumElems; ++i) {
2860 SDValue Arg = Mask.getOperand(i);
2861 if (Arg.getOpcode() != ISD::UNDEF) {
2862 unsigned Val = cast<ConstantSDNode>(Arg)->getZExtValue();
2863 if (Val > NumElems) {
2864 Arg = DAG.getConstant(NumElems, Arg.getValueType());
2868 MaskVec.push_back(Arg);
2872 Mask = DAG.getNode(ISD::BUILD_VECTOR, Mask.getValueType(),
2873 &MaskVec[0], MaskVec.size());
2877 /// getMOVLMask - Returns a vector_shuffle mask for an movs{s|d}, movd
2878 /// operation of specified width.
2879 static SDValue getMOVLMask(unsigned NumElems, SelectionDAG &DAG) {
2880 MVT MaskVT = MVT::getIntVectorWithNumElements(NumElems);
2881 MVT BaseVT = MaskVT.getVectorElementType();
2883 SmallVector<SDValue, 8> MaskVec;
2884 MaskVec.push_back(DAG.getConstant(NumElems, BaseVT));
2885 for (unsigned i = 1; i != NumElems; ++i)
2886 MaskVec.push_back(DAG.getConstant(i, BaseVT));
2887 return DAG.getNode(ISD::BUILD_VECTOR, MaskVT, &MaskVec[0], MaskVec.size());
2890 /// getUnpacklMask - Returns a vector_shuffle mask for an unpackl operation
2891 /// of specified width.
2892 static SDValue getUnpacklMask(unsigned NumElems, SelectionDAG &DAG) {
2893 MVT MaskVT = MVT::getIntVectorWithNumElements(NumElems);
2894 MVT BaseVT = MaskVT.getVectorElementType();
2895 SmallVector<SDValue, 8> MaskVec;
2896 for (unsigned i = 0, e = NumElems/2; i != e; ++i) {
2897 MaskVec.push_back(DAG.getConstant(i, BaseVT));
2898 MaskVec.push_back(DAG.getConstant(i + NumElems, BaseVT));
2900 return DAG.getNode(ISD::BUILD_VECTOR, MaskVT, &MaskVec[0], MaskVec.size());
2903 /// getUnpackhMask - Returns a vector_shuffle mask for an unpackh operation
2904 /// of specified width.
2905 static SDValue getUnpackhMask(unsigned NumElems, SelectionDAG &DAG) {
2906 MVT MaskVT = MVT::getIntVectorWithNumElements(NumElems);
2907 MVT BaseVT = MaskVT.getVectorElementType();
2908 unsigned Half = NumElems/2;
2909 SmallVector<SDValue, 8> MaskVec;
2910 for (unsigned i = 0; i != Half; ++i) {
2911 MaskVec.push_back(DAG.getConstant(i + Half, BaseVT));
2912 MaskVec.push_back(DAG.getConstant(i + NumElems + Half, BaseVT));
2914 return DAG.getNode(ISD::BUILD_VECTOR, MaskVT, &MaskVec[0], MaskVec.size());
2917 /// getSwapEltZeroMask - Returns a vector_shuffle mask for a shuffle that swaps
2918 /// element #0 of a vector with the specified index, leaving the rest of the
2919 /// elements in place.
2920 static SDValue getSwapEltZeroMask(unsigned NumElems, unsigned DestElt,
2921 SelectionDAG &DAG) {
2922 MVT MaskVT = MVT::getIntVectorWithNumElements(NumElems);
2923 MVT BaseVT = MaskVT.getVectorElementType();
2924 SmallVector<SDValue, 8> MaskVec;
2925 // Element #0 of the result gets the elt we are replacing.
2926 MaskVec.push_back(DAG.getConstant(DestElt, BaseVT));
2927 for (unsigned i = 1; i != NumElems; ++i)
2928 MaskVec.push_back(DAG.getConstant(i == DestElt ? 0 : i, BaseVT));
2929 return DAG.getNode(ISD::BUILD_VECTOR, MaskVT, &MaskVec[0], MaskVec.size());
2932 /// PromoteSplat - Promote a splat of v4f32, v8i16 or v16i8 to v4i32.
2933 static SDValue PromoteSplat(SDValue Op, SelectionDAG &DAG, bool HasSSE2) {
2934 MVT PVT = HasSSE2 ? MVT::v4i32 : MVT::v4f32;
2935 MVT VT = Op.getValueType();
2938 SDValue V1 = Op.getOperand(0);
2939 SDValue Mask = Op.getOperand(2);
2940 unsigned NumElems = Mask.getNumOperands();
2941 // Special handling of v4f32 -> v4i32.
2942 if (VT != MVT::v4f32) {
2943 Mask = getUnpacklMask(NumElems, DAG);
2944 while (NumElems > 4) {
2945 V1 = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V1, Mask);
2948 Mask = getZeroVector(MVT::v4i32, true, DAG);
2951 V1 = DAG.getNode(ISD::BIT_CONVERT, PVT, V1);
2952 SDValue Shuffle = DAG.getNode(ISD::VECTOR_SHUFFLE, PVT, V1,
2953 DAG.getNode(ISD::UNDEF, PVT), Mask);
2954 return DAG.getNode(ISD::BIT_CONVERT, VT, Shuffle);
2957 /// getShuffleVectorZeroOrUndef - Return a vector_shuffle of the specified
2958 /// vector of zero or undef vector. This produces a shuffle where the low
2959 /// element of V2 is swizzled into the zero/undef vector, landing at element
2960 /// Idx. This produces a shuffle mask like 4,1,2,3 (idx=0) or 0,1,2,4 (idx=3).
2961 static SDValue getShuffleVectorZeroOrUndef(SDValue V2, unsigned Idx,
2962 bool isZero, bool HasSSE2,
2963 SelectionDAG &DAG) {
2964 MVT VT = V2.getValueType();
2966 ? getZeroVector(VT, HasSSE2, DAG) : DAG.getNode(ISD::UNDEF, VT);
2967 unsigned NumElems = V2.getValueType().getVectorNumElements();
2968 MVT MaskVT = MVT::getIntVectorWithNumElements(NumElems);
2969 MVT EVT = MaskVT.getVectorElementType();
2970 SmallVector<SDValue, 16> MaskVec;
2971 for (unsigned i = 0; i != NumElems; ++i)
2972 if (i == Idx) // If this is the insertion idx, put the low elt of V2 here.
2973 MaskVec.push_back(DAG.getConstant(NumElems, EVT));
2975 MaskVec.push_back(DAG.getConstant(i, EVT));
2976 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
2977 &MaskVec[0], MaskVec.size());
2978 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2, Mask);
2981 /// getNumOfConsecutiveZeros - Return the number of elements in a result of
2982 /// a shuffle that is zero.
2984 unsigned getNumOfConsecutiveZeros(SDValue Op, SDValue Mask,
2985 unsigned NumElems, bool Low,
2986 SelectionDAG &DAG) {
2987 unsigned NumZeros = 0;
2988 for (unsigned i = 0; i < NumElems; ++i) {
2989 unsigned Index = Low ? i : NumElems-i-1;
2990 SDValue Idx = Mask.getOperand(Index);
2991 if (Idx.getOpcode() == ISD::UNDEF) {
2995 SDValue Elt = DAG.getShuffleScalarElt(Op.getNode(), Index);
2996 if (Elt.getNode() && isZeroNode(Elt))
3004 /// isVectorShift - Returns true if the shuffle can be implemented as a
3005 /// logical left or right shift of a vector.
3006 static bool isVectorShift(SDValue Op, SDValue Mask, SelectionDAG &DAG,
3007 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
3008 unsigned NumElems = Mask.getNumOperands();
3011 unsigned NumZeros= getNumOfConsecutiveZeros(Op, Mask, NumElems, true, DAG);
3014 NumZeros = getNumOfConsecutiveZeros(Op, Mask, NumElems, false, DAG);
3019 bool SeenV1 = false;
3020 bool SeenV2 = false;
3021 for (unsigned i = NumZeros; i < NumElems; ++i) {
3022 unsigned Val = isLeft ? (i - NumZeros) : i;
3023 SDValue Idx = Mask.getOperand(isLeft ? i : (i - NumZeros));
3024 if (Idx.getOpcode() == ISD::UNDEF)
3026 unsigned Index = cast<ConstantSDNode>(Idx)->getZExtValue();
3027 if (Index < NumElems)
3036 if (SeenV1 && SeenV2)
3039 ShVal = SeenV1 ? Op.getOperand(0) : Op.getOperand(1);
3045 /// LowerBuildVectorv16i8 - Custom lower build_vector of v16i8.
3047 static SDValue LowerBuildVectorv16i8(SDValue Op, unsigned NonZeros,
3048 unsigned NumNonZero, unsigned NumZero,
3049 SelectionDAG &DAG, TargetLowering &TLI) {
3055 for (unsigned i = 0; i < 16; ++i) {
3056 bool ThisIsNonZero = (NonZeros & (1 << i)) != 0;
3057 if (ThisIsNonZero && First) {
3059 V = getZeroVector(MVT::v8i16, true, DAG);
3061 V = DAG.getNode(ISD::UNDEF, MVT::v8i16);
3066 SDValue ThisElt(0, 0), LastElt(0, 0);
3067 bool LastIsNonZero = (NonZeros & (1 << (i-1))) != 0;
3068 if (LastIsNonZero) {
3069 LastElt = DAG.getNode(ISD::ZERO_EXTEND, MVT::i16, Op.getOperand(i-1));
3071 if (ThisIsNonZero) {
3072 ThisElt = DAG.getNode(ISD::ZERO_EXTEND, MVT::i16, Op.getOperand(i));
3073 ThisElt = DAG.getNode(ISD::SHL, MVT::i16,
3074 ThisElt, DAG.getConstant(8, MVT::i8));
3076 ThisElt = DAG.getNode(ISD::OR, MVT::i16, ThisElt, LastElt);
3080 if (ThisElt.getNode())
3081 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, MVT::v8i16, V, ThisElt,
3082 DAG.getIntPtrConstant(i/2));
3086 return DAG.getNode(ISD::BIT_CONVERT, MVT::v16i8, V);
3089 /// LowerBuildVectorv8i16 - Custom lower build_vector of v8i16.
3091 static SDValue LowerBuildVectorv8i16(SDValue Op, unsigned NonZeros,
3092 unsigned NumNonZero, unsigned NumZero,
3093 SelectionDAG &DAG, TargetLowering &TLI) {
3099 for (unsigned i = 0; i < 8; ++i) {
3100 bool isNonZero = (NonZeros & (1 << i)) != 0;
3104 V = getZeroVector(MVT::v8i16, true, DAG);
3106 V = DAG.getNode(ISD::UNDEF, MVT::v8i16);
3109 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, MVT::v8i16, V, Op.getOperand(i),
3110 DAG.getIntPtrConstant(i));
3117 /// getVShift - Return a vector logical shift node.
3119 static SDValue getVShift(bool isLeft, MVT VT, SDValue SrcOp,
3120 unsigned NumBits, SelectionDAG &DAG,
3121 const TargetLowering &TLI) {
3122 bool isMMX = VT.getSizeInBits() == 64;
3123 MVT ShVT = isMMX ? MVT::v1i64 : MVT::v2i64;
3124 unsigned Opc = isLeft ? X86ISD::VSHL : X86ISD::VSRL;
3125 SrcOp = DAG.getNode(ISD::BIT_CONVERT, ShVT, SrcOp);
3126 return DAG.getNode(ISD::BIT_CONVERT, VT,
3127 DAG.getNode(Opc, ShVT, SrcOp,
3128 DAG.getConstant(NumBits, TLI.getShiftAmountTy())));
3132 X86TargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) {
3133 // All zero's are handled with pxor, all one's are handled with pcmpeqd.
3134 if (ISD::isBuildVectorAllZeros(Op.getNode())
3135 || ISD::isBuildVectorAllOnes(Op.getNode())) {
3136 // Canonicalize this to either <4 x i32> or <2 x i32> (SSE vs MMX) to
3137 // 1) ensure the zero vectors are CSE'd, and 2) ensure that i64 scalars are
3138 // eliminated on x86-32 hosts.
3139 if (Op.getValueType() == MVT::v4i32 || Op.getValueType() == MVT::v2i32)
3142 if (ISD::isBuildVectorAllOnes(Op.getNode()))
3143 return getOnesVector(Op.getValueType(), DAG);
3144 return getZeroVector(Op.getValueType(), Subtarget->hasSSE2(), DAG);
3147 MVT VT = Op.getValueType();
3148 MVT EVT = VT.getVectorElementType();
3149 unsigned EVTBits = EVT.getSizeInBits();
3151 unsigned NumElems = Op.getNumOperands();
3152 unsigned NumZero = 0;
3153 unsigned NumNonZero = 0;
3154 unsigned NonZeros = 0;
3155 bool IsAllConstants = true;
3156 SmallSet<SDValue, 8> Values;
3157 for (unsigned i = 0; i < NumElems; ++i) {
3158 SDValue Elt = Op.getOperand(i);
3159 if (Elt.getOpcode() == ISD::UNDEF)
3162 if (Elt.getOpcode() != ISD::Constant &&
3163 Elt.getOpcode() != ISD::ConstantFP)
3164 IsAllConstants = false;
3165 if (isZeroNode(Elt))
3168 NonZeros |= (1 << i);
3173 if (NumNonZero == 0) {
3174 // All undef vector. Return an UNDEF. All zero vectors were handled above.
3175 return DAG.getNode(ISD::UNDEF, VT);
3178 // Special case for single non-zero, non-undef, element.
3179 if (NumNonZero == 1 && NumElems <= 4) {
3180 unsigned Idx = CountTrailingZeros_32(NonZeros);
3181 SDValue Item = Op.getOperand(Idx);
3183 // If this is an insertion of an i64 value on x86-32, and if the top bits of
3184 // the value are obviously zero, truncate the value to i32 and do the
3185 // insertion that way. Only do this if the value is non-constant or if the
3186 // value is a constant being inserted into element 0. It is cheaper to do
3187 // a constant pool load than it is to do a movd + shuffle.
3188 if (EVT == MVT::i64 && !Subtarget->is64Bit() &&
3189 (!IsAllConstants || Idx == 0)) {
3190 if (DAG.MaskedValueIsZero(Item, APInt::getBitsSet(64, 32, 64))) {
3191 // Handle MMX and SSE both.
3192 MVT VecVT = VT == MVT::v2i64 ? MVT::v4i32 : MVT::v2i32;
3193 unsigned VecElts = VT == MVT::v2i64 ? 4 : 2;
3195 // Truncate the value (which may itself be a constant) to i32, and
3196 // convert it to a vector with movd (S2V+shuffle to zero extend).
3197 Item = DAG.getNode(ISD::TRUNCATE, MVT::i32, Item);
3198 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, VecVT, Item);
3199 Item = getShuffleVectorZeroOrUndef(Item, 0, true,
3200 Subtarget->hasSSE2(), DAG);
3202 // Now we have our 32-bit value zero extended in the low element of
3203 // a vector. If Idx != 0, swizzle it into place.
3206 Item, DAG.getNode(ISD::UNDEF, Item.getValueType()),
3207 getSwapEltZeroMask(VecElts, Idx, DAG)
3209 Item = DAG.getNode(ISD::VECTOR_SHUFFLE, VecVT, Ops, 3);
3211 return DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), Item);
3215 // If we have a constant or non-constant insertion into the low element of
3216 // a vector, we can do this with SCALAR_TO_VECTOR + shuffle of zero into
3217 // the rest of the elements. This will be matched as movd/movq/movss/movsd
3218 // depending on what the source datatype is. Because we can only get here
3219 // when NumElems <= 4, this only needs to handle i32/f32/i64/f64.
3221 // Don't do this for i64 values on x86-32.
3222 (EVT != MVT::i64 || Subtarget->is64Bit())) {
3223 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, VT, Item);
3224 // Turn it into a MOVL (i.e. movss, movsd, or movd) to a zero vector.
3225 return getShuffleVectorZeroOrUndef(Item, 0, NumZero > 0,
3226 Subtarget->hasSSE2(), DAG);
3229 // Is it a vector logical left shift?
3230 if (NumElems == 2 && Idx == 1 &&
3231 isZeroNode(Op.getOperand(0)) && !isZeroNode(Op.getOperand(1))) {
3232 unsigned NumBits = VT.getSizeInBits();
3233 return getVShift(true, VT,
3234 DAG.getNode(ISD::SCALAR_TO_VECTOR, VT, Op.getOperand(1)),
3235 NumBits/2, DAG, *this);
3238 if (IsAllConstants) // Otherwise, it's better to do a constpool load.
3241 // Otherwise, if this is a vector with i32 or f32 elements, and the element
3242 // is a non-constant being inserted into an element other than the low one,
3243 // we can't use a constant pool load. Instead, use SCALAR_TO_VECTOR (aka
3244 // movd/movss) to move this into the low element, then shuffle it into
3246 if (EVTBits == 32) {
3247 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, VT, Item);
3249 // Turn it into a shuffle of zero and zero-extended scalar to vector.
3250 Item = getShuffleVectorZeroOrUndef(Item, 0, NumZero > 0,
3251 Subtarget->hasSSE2(), DAG);
3252 MVT MaskVT = MVT::getIntVectorWithNumElements(NumElems);
3253 MVT MaskEVT = MaskVT.getVectorElementType();
3254 SmallVector<SDValue, 8> MaskVec;
3255 for (unsigned i = 0; i < NumElems; i++)
3256 MaskVec.push_back(DAG.getConstant((i == Idx) ? 0 : 1, MaskEVT));
3257 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
3258 &MaskVec[0], MaskVec.size());
3259 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, Item,
3260 DAG.getNode(ISD::UNDEF, VT), Mask);
3264 // Splat is obviously ok. Let legalizer expand it to a shuffle.
3265 if (Values.size() == 1)
3268 // A vector full of immediates; various special cases are already
3269 // handled, so this is best done with a single constant-pool load.
3273 // Let legalizer expand 2-wide build_vectors.
3274 if (EVTBits == 64) {
3275 if (NumNonZero == 1) {
3276 // One half is zero or undef.
3277 unsigned Idx = CountTrailingZeros_32(NonZeros);
3278 SDValue V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, VT,
3279 Op.getOperand(Idx));
3280 return getShuffleVectorZeroOrUndef(V2, Idx, true,
3281 Subtarget->hasSSE2(), DAG);
3286 // If element VT is < 32 bits, convert it to inserts into a zero vector.
3287 if (EVTBits == 8 && NumElems == 16) {
3288 SDValue V = LowerBuildVectorv16i8(Op, NonZeros,NumNonZero,NumZero, DAG,
3290 if (V.getNode()) return V;
3293 if (EVTBits == 16 && NumElems == 8) {
3294 SDValue V = LowerBuildVectorv8i16(Op, NonZeros,NumNonZero,NumZero, DAG,
3296 if (V.getNode()) return V;
3299 // If element VT is == 32 bits, turn it into a number of shuffles.
3300 SmallVector<SDValue, 8> V;
3302 if (NumElems == 4 && NumZero > 0) {
3303 for (unsigned i = 0; i < 4; ++i) {
3304 bool isZero = !(NonZeros & (1 << i));
3306 V[i] = getZeroVector(VT, Subtarget->hasSSE2(), DAG);
3308 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, VT, Op.getOperand(i));
3311 for (unsigned i = 0; i < 2; ++i) {
3312 switch ((NonZeros & (0x3 << i*2)) >> (i*2)) {
3315 V[i] = V[i*2]; // Must be a zero vector.
3318 V[i] = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V[i*2+1], V[i*2],
3319 getMOVLMask(NumElems, DAG));
3322 V[i] = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V[i*2], V[i*2+1],
3323 getMOVLMask(NumElems, DAG));
3326 V[i] = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V[i*2], V[i*2+1],
3327 getUnpacklMask(NumElems, DAG));
3332 MVT MaskVT = MVT::getIntVectorWithNumElements(NumElems);
3333 MVT EVT = MaskVT.getVectorElementType();
3334 SmallVector<SDValue, 8> MaskVec;
3335 bool Reverse = (NonZeros & 0x3) == 2;
3336 for (unsigned i = 0; i < 2; ++i)
3338 MaskVec.push_back(DAG.getConstant(1-i, EVT));
3340 MaskVec.push_back(DAG.getConstant(i, EVT));
3341 Reverse = ((NonZeros & (0x3 << 2)) >> 2) == 2;
3342 for (unsigned i = 0; i < 2; ++i)
3344 MaskVec.push_back(DAG.getConstant(1-i+NumElems, EVT));
3346 MaskVec.push_back(DAG.getConstant(i+NumElems, EVT));
3347 SDValue ShufMask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
3348 &MaskVec[0], MaskVec.size());
3349 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V[0], V[1], ShufMask);
3352 if (Values.size() > 2) {
3353 // Expand into a number of unpckl*.
3355 // Step 1: unpcklps 0, 2 ==> X: <?, ?, 2, 0>
3356 // : unpcklps 1, 3 ==> Y: <?, ?, 3, 1>
3357 // Step 2: unpcklps X, Y ==> <3, 2, 1, 0>
3358 SDValue UnpckMask = getUnpacklMask(NumElems, DAG);
3359 for (unsigned i = 0; i < NumElems; ++i)
3360 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, VT, Op.getOperand(i));
3362 while (NumElems != 0) {
3363 for (unsigned i = 0; i < NumElems; ++i)
3364 V[i] = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V[i], V[i + NumElems],
3375 SDValue LowerVECTOR_SHUFFLEv8i16(SDValue V1, SDValue V2,
3376 SDValue PermMask, SelectionDAG &DAG,
3377 TargetLowering &TLI) {
3379 MVT MaskVT = MVT::getIntVectorWithNumElements(8);
3380 MVT MaskEVT = MaskVT.getVectorElementType();
3381 MVT PtrVT = TLI.getPointerTy();
3382 SmallVector<SDValue, 8> MaskElts(PermMask.getNode()->op_begin(),
3383 PermMask.getNode()->op_end());
3385 // First record which half of which vector the low elements come from.
3386 SmallVector<unsigned, 4> LowQuad(4);
3387 for (unsigned i = 0; i < 4; ++i) {
3388 SDValue Elt = MaskElts[i];
3389 if (Elt.getOpcode() == ISD::UNDEF)
3391 unsigned EltIdx = cast<ConstantSDNode>(Elt)->getZExtValue();
3392 int QuadIdx = EltIdx / 4;
3396 int BestLowQuad = -1;
3397 unsigned MaxQuad = 1;
3398 for (unsigned i = 0; i < 4; ++i) {
3399 if (LowQuad[i] > MaxQuad) {
3401 MaxQuad = LowQuad[i];
3405 // Record which half of which vector the high elements come from.
3406 SmallVector<unsigned, 4> HighQuad(4);
3407 for (unsigned i = 4; i < 8; ++i) {
3408 SDValue Elt = MaskElts[i];
3409 if (Elt.getOpcode() == ISD::UNDEF)
3411 unsigned EltIdx = cast<ConstantSDNode>(Elt)->getZExtValue();
3412 int QuadIdx = EltIdx / 4;
3413 ++HighQuad[QuadIdx];
3416 int BestHighQuad = -1;
3418 for (unsigned i = 0; i < 4; ++i) {
3419 if (HighQuad[i] > MaxQuad) {
3421 MaxQuad = HighQuad[i];
3425 // If it's possible to sort parts of either half with PSHUF{H|L}W, then do it.
3426 if (BestLowQuad != -1 || BestHighQuad != -1) {
3427 // First sort the 4 chunks in order using shufpd.
3428 SmallVector<SDValue, 8> MaskVec;
3430 if (BestLowQuad != -1)
3431 MaskVec.push_back(DAG.getConstant(BestLowQuad, MVT::i32));
3433 MaskVec.push_back(DAG.getConstant(0, MVT::i32));
3435 if (BestHighQuad != -1)
3436 MaskVec.push_back(DAG.getConstant(BestHighQuad, MVT::i32));
3438 MaskVec.push_back(DAG.getConstant(1, MVT::i32));
3440 SDValue Mask= DAG.getNode(ISD::BUILD_VECTOR, MVT::v2i32, &MaskVec[0],2);
3441 NewV = DAG.getNode(ISD::VECTOR_SHUFFLE, MVT::v2i64,
3442 DAG.getNode(ISD::BIT_CONVERT, MVT::v2i64, V1),
3443 DAG.getNode(ISD::BIT_CONVERT, MVT::v2i64, V2), Mask);
3444 NewV = DAG.getNode(ISD::BIT_CONVERT, MVT::v8i16, NewV);
3446 // Now sort high and low parts separately.
3447 BitVector InOrder(8);
3448 if (BestLowQuad != -1) {
3449 // Sort lower half in order using PSHUFLW.
3451 bool AnyOutOrder = false;
3453 for (unsigned i = 0; i != 4; ++i) {
3454 SDValue Elt = MaskElts[i];
3455 if (Elt.getOpcode() == ISD::UNDEF) {
3456 MaskVec.push_back(Elt);
3459 unsigned EltIdx = cast<ConstantSDNode>(Elt)->getZExtValue();
3463 MaskVec.push_back(DAG.getConstant(EltIdx % 4, MaskEVT));
3465 // If this element is in the right place after this shuffle, then
3467 if ((int)(EltIdx / 4) == BestLowQuad)
3472 for (unsigned i = 4; i != 8; ++i)
3473 MaskVec.push_back(DAG.getConstant(i, MaskEVT));
3474 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT, &MaskVec[0], 8);
3475 NewV = DAG.getNode(ISD::VECTOR_SHUFFLE, MVT::v8i16, NewV, NewV, Mask);
3479 if (BestHighQuad != -1) {
3480 // Sort high half in order using PSHUFHW if possible.
3483 for (unsigned i = 0; i != 4; ++i)
3484 MaskVec.push_back(DAG.getConstant(i, MaskEVT));
3486 bool AnyOutOrder = false;
3487 for (unsigned i = 4; i != 8; ++i) {
3488 SDValue Elt = MaskElts[i];
3489 if (Elt.getOpcode() == ISD::UNDEF) {
3490 MaskVec.push_back(Elt);
3493 unsigned EltIdx = cast<ConstantSDNode>(Elt)->getZExtValue();
3497 MaskVec.push_back(DAG.getConstant((EltIdx % 4) + 4, MaskEVT));
3499 // If this element is in the right place after this shuffle, then
3501 if ((int)(EltIdx / 4) == BestHighQuad)
3507 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT, &MaskVec[0], 8);
3508 NewV = DAG.getNode(ISD::VECTOR_SHUFFLE, MVT::v8i16, NewV, NewV, Mask);
3512 // The other elements are put in the right place using pextrw and pinsrw.
3513 for (unsigned i = 0; i != 8; ++i) {
3516 SDValue Elt = MaskElts[i];
3517 if (Elt.getOpcode() == ISD::UNDEF)
3519 unsigned EltIdx = cast<ConstantSDNode>(Elt)->getZExtValue();
3520 SDValue ExtOp = (EltIdx < 8)
3521 ? DAG.getNode(ISD::EXTRACT_VECTOR_ELT, MVT::i16, V1,
3522 DAG.getConstant(EltIdx, PtrVT))
3523 : DAG.getNode(ISD::EXTRACT_VECTOR_ELT, MVT::i16, V2,
3524 DAG.getConstant(EltIdx - 8, PtrVT));
3525 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, MVT::v8i16, NewV, ExtOp,
3526 DAG.getConstant(i, PtrVT));
3532 // PSHUF{H|L}W are not used. Lower into extracts and inserts but try to use as
3533 // few as possible. First, let's find out how many elements are already in the
3535 unsigned V1InOrder = 0;
3536 unsigned V1FromV1 = 0;
3537 unsigned V2InOrder = 0;
3538 unsigned V2FromV2 = 0;
3539 SmallVector<SDValue, 8> V1Elts;
3540 SmallVector<SDValue, 8> V2Elts;
3541 for (unsigned i = 0; i < 8; ++i) {
3542 SDValue Elt = MaskElts[i];
3543 if (Elt.getOpcode() == ISD::UNDEF) {
3544 V1Elts.push_back(Elt);
3545 V2Elts.push_back(Elt);
3550 unsigned EltIdx = cast<ConstantSDNode>(Elt)->getZExtValue();
3552 V1Elts.push_back(Elt);
3553 V2Elts.push_back(DAG.getConstant(i+8, MaskEVT));
3555 } else if (EltIdx == i+8) {
3556 V1Elts.push_back(Elt);
3557 V2Elts.push_back(DAG.getConstant(i, MaskEVT));
3559 } else if (EltIdx < 8) {
3560 V1Elts.push_back(Elt);
3563 V2Elts.push_back(DAG.getConstant(EltIdx-8, MaskEVT));
3568 if (V2InOrder > V1InOrder) {
3569 PermMask = CommuteVectorShuffleMask(PermMask, DAG);
3571 std::swap(V1Elts, V2Elts);
3572 std::swap(V1FromV1, V2FromV2);
3575 if ((V1FromV1 + V1InOrder) != 8) {
3576 // Some elements are from V2.
3578 // If there are elements that are from V1 but out of place,
3579 // then first sort them in place
3580 SmallVector<SDValue, 8> MaskVec;
3581 for (unsigned i = 0; i < 8; ++i) {
3582 SDValue Elt = V1Elts[i];
3583 if (Elt.getOpcode() == ISD::UNDEF) {
3584 MaskVec.push_back(DAG.getNode(ISD::UNDEF, MaskEVT));
3587 unsigned EltIdx = cast<ConstantSDNode>(Elt)->getZExtValue();
3589 MaskVec.push_back(DAG.getNode(ISD::UNDEF, MaskEVT));
3591 MaskVec.push_back(DAG.getConstant(EltIdx, MaskEVT));
3593 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT, &MaskVec[0], 8);
3594 V1 = DAG.getNode(ISD::VECTOR_SHUFFLE, MVT::v8i16, V1, V1, Mask);
3598 for (unsigned i = 0; i < 8; ++i) {
3599 SDValue Elt = V1Elts[i];
3600 if (Elt.getOpcode() == ISD::UNDEF)
3602 unsigned EltIdx = cast<ConstantSDNode>(Elt)->getZExtValue();
3605 SDValue ExtOp = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, MVT::i16, V2,
3606 DAG.getConstant(EltIdx - 8, PtrVT));
3607 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, MVT::v8i16, NewV, ExtOp,
3608 DAG.getConstant(i, PtrVT));
3612 // All elements are from V1.
3614 for (unsigned i = 0; i < 8; ++i) {
3615 SDValue Elt = V1Elts[i];
3616 if (Elt.getOpcode() == ISD::UNDEF)
3618 unsigned EltIdx = cast<ConstantSDNode>(Elt)->getZExtValue();
3619 SDValue ExtOp = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, MVT::i16, V1,
3620 DAG.getConstant(EltIdx, PtrVT));
3621 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, MVT::v8i16, NewV, ExtOp,
3622 DAG.getConstant(i, PtrVT));
3628 /// RewriteAsNarrowerShuffle - Try rewriting v8i16 and v16i8 shuffles as 4 wide
3629 /// ones, or rewriting v4i32 / v2f32 as 2 wide ones if possible. This can be
3630 /// done when every pair / quad of shuffle mask elements point to elements in
3631 /// the right sequence. e.g.
3632 /// vector_shuffle <>, <>, < 3, 4, | 10, 11, | 0, 1, | 14, 15>
3634 SDValue RewriteAsNarrowerShuffle(SDValue V1, SDValue V2,
3636 SDValue PermMask, SelectionDAG &DAG,
3637 TargetLowering &TLI) {
3638 unsigned NumElems = PermMask.getNumOperands();
3639 unsigned NewWidth = (NumElems == 4) ? 2 : 4;
3640 MVT MaskVT = MVT::getIntVectorWithNumElements(NewWidth);
3641 MVT MaskEltVT = MaskVT.getVectorElementType();
3643 switch (VT.getSimpleVT()) {
3644 default: assert(false && "Unexpected!");
3645 case MVT::v4f32: NewVT = MVT::v2f64; break;
3646 case MVT::v4i32: NewVT = MVT::v2i64; break;
3647 case MVT::v8i16: NewVT = MVT::v4i32; break;
3648 case MVT::v16i8: NewVT = MVT::v4i32; break;
3651 if (NewWidth == 2) {
3657 unsigned Scale = NumElems / NewWidth;
3658 SmallVector<SDValue, 8> MaskVec;
3659 for (unsigned i = 0; i < NumElems; i += Scale) {
3660 unsigned StartIdx = ~0U;
3661 for (unsigned j = 0; j < Scale; ++j) {
3662 SDValue Elt = PermMask.getOperand(i+j);
3663 if (Elt.getOpcode() == ISD::UNDEF)
3665 unsigned EltIdx = cast<ConstantSDNode>(Elt)->getZExtValue();
3666 if (StartIdx == ~0U)
3667 StartIdx = EltIdx - (EltIdx % Scale);
3668 if (EltIdx != StartIdx + j)
3671 if (StartIdx == ~0U)
3672 MaskVec.push_back(DAG.getNode(ISD::UNDEF, MaskEltVT));
3674 MaskVec.push_back(DAG.getConstant(StartIdx / Scale, MaskEltVT));
3677 V1 = DAG.getNode(ISD::BIT_CONVERT, NewVT, V1);
3678 V2 = DAG.getNode(ISD::BIT_CONVERT, NewVT, V2);
3679 return DAG.getNode(ISD::VECTOR_SHUFFLE, NewVT, V1, V2,
3680 DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
3681 &MaskVec[0], MaskVec.size()));
3684 /// getVZextMovL - Return a zero-extending vector move low node.
3686 static SDValue getVZextMovL(MVT VT, MVT OpVT,
3687 SDValue SrcOp, SelectionDAG &DAG,
3688 const X86Subtarget *Subtarget) {
3689 if (VT == MVT::v2f64 || VT == MVT::v4f32) {
3690 LoadSDNode *LD = NULL;
3691 if (!isScalarLoadToVector(SrcOp.getNode(), &LD))
3692 LD = dyn_cast<LoadSDNode>(SrcOp);
3694 // movssrr and movsdrr do not clear top bits. Try to use movd, movq
3696 MVT EVT = (OpVT == MVT::v2f64) ? MVT::i64 : MVT::i32;
3697 if ((EVT != MVT::i64 || Subtarget->is64Bit()) &&
3698 SrcOp.getOpcode() == ISD::SCALAR_TO_VECTOR &&
3699 SrcOp.getOperand(0).getOpcode() == ISD::BIT_CONVERT &&
3700 SrcOp.getOperand(0).getOperand(0).getValueType() == EVT) {
3702 OpVT = (OpVT == MVT::v2f64) ? MVT::v2i64 : MVT::v4i32;
3703 return DAG.getNode(ISD::BIT_CONVERT, VT,
3704 DAG.getNode(X86ISD::VZEXT_MOVL, OpVT,
3705 DAG.getNode(ISD::SCALAR_TO_VECTOR, OpVT,
3712 return DAG.getNode(ISD::BIT_CONVERT, VT,
3713 DAG.getNode(X86ISD::VZEXT_MOVL, OpVT,
3714 DAG.getNode(ISD::BIT_CONVERT, OpVT, SrcOp)));
3717 /// LowerVECTOR_SHUFFLE_4wide - Handle all 4 wide cases with a number of
3720 LowerVECTOR_SHUFFLE_4wide(SDValue V1, SDValue V2,
3721 SDValue PermMask, MVT VT, SelectionDAG &DAG) {
3722 MVT MaskVT = PermMask.getValueType();
3723 MVT MaskEVT = MaskVT.getVectorElementType();
3724 SmallVector<std::pair<int, int>, 8> Locs;
3726 SmallVector<SDValue, 8> Mask1(4, DAG.getNode(ISD::UNDEF, MaskEVT));
3729 for (unsigned i = 0; i != 4; ++i) {
3730 SDValue Elt = PermMask.getOperand(i);
3731 if (Elt.getOpcode() == ISD::UNDEF) {
3732 Locs[i] = std::make_pair(-1, -1);
3734 unsigned Val = cast<ConstantSDNode>(Elt)->getZExtValue();
3735 assert(Val < 8 && "Invalid VECTOR_SHUFFLE index!");
3737 Locs[i] = std::make_pair(0, NumLo);
3741 Locs[i] = std::make_pair(1, NumHi);
3743 Mask1[2+NumHi] = Elt;
3749 if (NumLo <= 2 && NumHi <= 2) {
3750 // If no more than two elements come from either vector. This can be
3751 // implemented with two shuffles. First shuffle gather the elements.
3752 // The second shuffle, which takes the first shuffle as both of its
3753 // vector operands, put the elements into the right order.
3754 V1 = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2,
3755 DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
3756 &Mask1[0], Mask1.size()));
3758 SmallVector<SDValue, 8> Mask2(4, DAG.getNode(ISD::UNDEF, MaskEVT));
3759 for (unsigned i = 0; i != 4; ++i) {
3760 if (Locs[i].first == -1)
3763 unsigned Idx = (i < 2) ? 0 : 4;
3764 Idx += Locs[i].first * 2 + Locs[i].second;
3765 Mask2[i] = DAG.getConstant(Idx, MaskEVT);
3769 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V1,
3770 DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
3771 &Mask2[0], Mask2.size()));
3772 } else if (NumLo == 3 || NumHi == 3) {
3773 // Otherwise, we must have three elements from one vector, call it X, and
3774 // one element from the other, call it Y. First, use a shufps to build an
3775 // intermediate vector with the one element from Y and the element from X
3776 // that will be in the same half in the final destination (the indexes don't
3777 // matter). Then, use a shufps to build the final vector, taking the half
3778 // containing the element from Y from the intermediate, and the other half
3781 // Normalize it so the 3 elements come from V1.
3782 PermMask = CommuteVectorShuffleMask(PermMask, DAG);
3786 // Find the element from V2.
3788 for (HiIndex = 0; HiIndex < 3; ++HiIndex) {
3789 SDValue Elt = PermMask.getOperand(HiIndex);
3790 if (Elt.getOpcode() == ISD::UNDEF)
3792 unsigned Val = cast<ConstantSDNode>(Elt)->getZExtValue();
3797 Mask1[0] = PermMask.getOperand(HiIndex);
3798 Mask1[1] = DAG.getNode(ISD::UNDEF, MaskEVT);
3799 Mask1[2] = PermMask.getOperand(HiIndex^1);
3800 Mask1[3] = DAG.getNode(ISD::UNDEF, MaskEVT);
3801 V2 = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2,
3802 DAG.getNode(ISD::BUILD_VECTOR, MaskVT, &Mask1[0], 4));
3805 Mask1[0] = PermMask.getOperand(0);
3806 Mask1[1] = PermMask.getOperand(1);
3807 Mask1[2] = DAG.getConstant(HiIndex & 1 ? 6 : 4, MaskEVT);
3808 Mask1[3] = DAG.getConstant(HiIndex & 1 ? 4 : 6, MaskEVT);
3809 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2,
3810 DAG.getNode(ISD::BUILD_VECTOR, MaskVT, &Mask1[0], 4));
3812 Mask1[0] = DAG.getConstant(HiIndex & 1 ? 2 : 0, MaskEVT);
3813 Mask1[1] = DAG.getConstant(HiIndex & 1 ? 0 : 2, MaskEVT);
3814 Mask1[2] = PermMask.getOperand(2);
3815 Mask1[3] = PermMask.getOperand(3);
3816 if (Mask1[2].getOpcode() != ISD::UNDEF)
3818 DAG.getConstant(cast<ConstantSDNode>(Mask1[2])->getZExtValue()+4,
3820 if (Mask1[3].getOpcode() != ISD::UNDEF)
3822 DAG.getConstant(cast<ConstantSDNode>(Mask1[3])->getZExtValue()+4,
3824 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V2, V1,
3825 DAG.getNode(ISD::BUILD_VECTOR, MaskVT, &Mask1[0], 4));
3829 // Break it into (shuffle shuffle_hi, shuffle_lo).
3831 SmallVector<SDValue,8> LoMask(4, DAG.getNode(ISD::UNDEF, MaskEVT));
3832 SmallVector<SDValue,8> HiMask(4, DAG.getNode(ISD::UNDEF, MaskEVT));
3833 SmallVector<SDValue,8> *MaskPtr = &LoMask;
3834 unsigned MaskIdx = 0;
3837 for (unsigned i = 0; i != 4; ++i) {
3844 SDValue Elt = PermMask.getOperand(i);
3845 if (Elt.getOpcode() == ISD::UNDEF) {
3846 Locs[i] = std::make_pair(-1, -1);
3847 } else if (cast<ConstantSDNode>(Elt)->getZExtValue() < 4) {
3848 Locs[i] = std::make_pair(MaskIdx, LoIdx);
3849 (*MaskPtr)[LoIdx] = Elt;
3852 Locs[i] = std::make_pair(MaskIdx, HiIdx);
3853 (*MaskPtr)[HiIdx] = Elt;
3858 SDValue LoShuffle = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2,
3859 DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
3860 &LoMask[0], LoMask.size()));
3861 SDValue HiShuffle = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2,
3862 DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
3863 &HiMask[0], HiMask.size()));
3864 SmallVector<SDValue, 8> MaskOps;
3865 for (unsigned i = 0; i != 4; ++i) {
3866 if (Locs[i].first == -1) {
3867 MaskOps.push_back(DAG.getNode(ISD::UNDEF, MaskEVT));
3869 unsigned Idx = Locs[i].first * 4 + Locs[i].second;
3870 MaskOps.push_back(DAG.getConstant(Idx, MaskEVT));
3873 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, LoShuffle, HiShuffle,
3874 DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
3875 &MaskOps[0], MaskOps.size()));
3879 X86TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) {
3880 SDValue V1 = Op.getOperand(0);
3881 SDValue V2 = Op.getOperand(1);
3882 SDValue PermMask = Op.getOperand(2);
3883 MVT VT = Op.getValueType();
3884 unsigned NumElems = PermMask.getNumOperands();
3885 bool isMMX = VT.getSizeInBits() == 64;
3886 bool V1IsUndef = V1.getOpcode() == ISD::UNDEF;
3887 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
3888 bool V1IsSplat = false;
3889 bool V2IsSplat = false;
3891 if (isUndefShuffle(Op.getNode()))
3892 return DAG.getNode(ISD::UNDEF, VT);
3894 if (isZeroShuffle(Op.getNode()))
3895 return getZeroVector(VT, Subtarget->hasSSE2(), DAG);
3897 if (isIdentityMask(PermMask.getNode()))
3899 else if (isIdentityMask(PermMask.getNode(), true))
3902 if (isSplatMask(PermMask.getNode())) {
3903 if (isMMX || NumElems < 4) return Op;
3904 // Promote it to a v4{if}32 splat.
3905 return PromoteSplat(Op, DAG, Subtarget->hasSSE2());
3908 // If the shuffle can be profitably rewritten as a narrower shuffle, then
3910 if (VT == MVT::v8i16 || VT == MVT::v16i8) {
3911 SDValue NewOp= RewriteAsNarrowerShuffle(V1, V2, VT, PermMask, DAG, *this);
3912 if (NewOp.getNode())
3913 return DAG.getNode(ISD::BIT_CONVERT, VT, LowerVECTOR_SHUFFLE(NewOp, DAG));
3914 } else if ((VT == MVT::v4i32 || (VT == MVT::v4f32 && Subtarget->hasSSE2()))) {
3915 // FIXME: Figure out a cleaner way to do this.
3916 // Try to make use of movq to zero out the top part.
3917 if (ISD::isBuildVectorAllZeros(V2.getNode())) {
3918 SDValue NewOp = RewriteAsNarrowerShuffle(V1, V2, VT, PermMask,
3920 if (NewOp.getNode()) {
3921 SDValue NewV1 = NewOp.getOperand(0);
3922 SDValue NewV2 = NewOp.getOperand(1);
3923 SDValue NewMask = NewOp.getOperand(2);
3924 if (isCommutedMOVL(NewMask.getNode(), true, false)) {
3925 NewOp = CommuteVectorShuffle(NewOp, NewV1, NewV2, NewMask, DAG);
3926 return getVZextMovL(VT, NewOp.getValueType(), NewV2, DAG, Subtarget);
3929 } else if (ISD::isBuildVectorAllZeros(V1.getNode())) {
3930 SDValue NewOp= RewriteAsNarrowerShuffle(V1, V2, VT, PermMask,
3932 if (NewOp.getNode() && X86::isMOVLMask(NewOp.getOperand(2).getNode()))
3933 return getVZextMovL(VT, NewOp.getValueType(), NewOp.getOperand(1),
3938 // Check if this can be converted into a logical shift.
3939 bool isLeft = false;
3942 bool isShift = isVectorShift(Op, PermMask, DAG, isLeft, ShVal, ShAmt);
3943 if (isShift && ShVal.hasOneUse()) {
3944 // If the shifted value has multiple uses, it may be cheaper to use
3945 // v_set0 + movlhps or movhlps, etc.
3946 MVT EVT = VT.getVectorElementType();
3947 ShAmt *= EVT.getSizeInBits();
3948 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this);
3951 if (X86::isMOVLMask(PermMask.getNode())) {
3954 if (ISD::isBuildVectorAllZeros(V1.getNode()))
3955 return getVZextMovL(VT, VT, V2, DAG, Subtarget);
3960 if (!isMMX && (X86::isMOVSHDUPMask(PermMask.getNode()) ||
3961 X86::isMOVSLDUPMask(PermMask.getNode()) ||
3962 X86::isMOVHLPSMask(PermMask.getNode()) ||
3963 X86::isMOVHPMask(PermMask.getNode()) ||
3964 X86::isMOVLPMask(PermMask.getNode())))
3967 if (ShouldXformToMOVHLPS(PermMask.getNode()) ||
3968 ShouldXformToMOVLP(V1.getNode(), V2.getNode(), PermMask.getNode()))
3969 return CommuteVectorShuffle(Op, V1, V2, PermMask, DAG);
3972 // No better options. Use a vshl / vsrl.
3973 MVT EVT = VT.getVectorElementType();
3974 ShAmt *= EVT.getSizeInBits();
3975 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this);
3978 bool Commuted = false;
3979 // FIXME: This should also accept a bitcast of a splat? Be careful, not
3980 // 1,1,1,1 -> v8i16 though.
3981 V1IsSplat = isSplatVector(V1.getNode());
3982 V2IsSplat = isSplatVector(V2.getNode());
3984 // Canonicalize the splat or undef, if present, to be on the RHS.
3985 if ((V1IsSplat || V1IsUndef) && !(V2IsSplat || V2IsUndef)) {
3986 Op = CommuteVectorShuffle(Op, V1, V2, PermMask, DAG);
3987 std::swap(V1IsSplat, V2IsSplat);
3988 std::swap(V1IsUndef, V2IsUndef);
3992 // FIXME: Figure out a cleaner way to do this.
3993 if (isCommutedMOVL(PermMask.getNode(), V2IsSplat, V2IsUndef)) {
3994 if (V2IsUndef) return V1;
3995 Op = CommuteVectorShuffle(Op, V1, V2, PermMask, DAG);
3997 // V2 is a splat, so the mask may be malformed. That is, it may point
3998 // to any V2 element. The instruction selectior won't like this. Get
3999 // a corrected mask and commute to form a proper MOVS{S|D}.
4000 SDValue NewMask = getMOVLMask(NumElems, DAG);
4001 if (NewMask.getNode() != PermMask.getNode())
4002 Op = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2, NewMask);
4007 if (X86::isUNPCKL_v_undef_Mask(PermMask.getNode()) ||
4008 X86::isUNPCKH_v_undef_Mask(PermMask.getNode()) ||
4009 X86::isUNPCKLMask(PermMask.getNode()) ||
4010 X86::isUNPCKHMask(PermMask.getNode()))
4014 // Normalize mask so all entries that point to V2 points to its first
4015 // element then try to match unpck{h|l} again. If match, return a
4016 // new vector_shuffle with the corrected mask.
4017 SDValue NewMask = NormalizeMask(PermMask, DAG);
4018 if (NewMask.getNode() != PermMask.getNode()) {
4019 if (X86::isUNPCKLMask(PermMask.getNode(), true)) {
4020 SDValue NewMask = getUnpacklMask(NumElems, DAG);
4021 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2, NewMask);
4022 } else if (X86::isUNPCKHMask(PermMask.getNode(), true)) {
4023 SDValue NewMask = getUnpackhMask(NumElems, DAG);
4024 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2, NewMask);
4029 // Normalize the node to match x86 shuffle ops if needed
4030 if (V2.getOpcode() != ISD::UNDEF && isCommutedSHUFP(PermMask.getNode()))
4031 Op = CommuteVectorShuffle(Op, V1, V2, PermMask, DAG);
4034 // Commute is back and try unpck* again.
4035 Op = CommuteVectorShuffle(Op, V1, V2, PermMask, DAG);
4036 if (X86::isUNPCKL_v_undef_Mask(PermMask.getNode()) ||
4037 X86::isUNPCKH_v_undef_Mask(PermMask.getNode()) ||
4038 X86::isUNPCKLMask(PermMask.getNode()) ||
4039 X86::isUNPCKHMask(PermMask.getNode()))
4043 // Try PSHUF* first, then SHUFP*.
4044 // MMX doesn't have PSHUFD but it does have PSHUFW. While it's theoretically
4045 // possible to shuffle a v2i32 using PSHUFW, that's not yet implemented.
4046 if (isMMX && NumElems == 4 && X86::isPSHUFDMask(PermMask.getNode())) {
4047 if (V2.getOpcode() != ISD::UNDEF)
4048 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1,
4049 DAG.getNode(ISD::UNDEF, VT), PermMask);
4054 if (Subtarget->hasSSE2() &&
4055 (X86::isPSHUFDMask(PermMask.getNode()) ||
4056 X86::isPSHUFHWMask(PermMask.getNode()) ||
4057 X86::isPSHUFLWMask(PermMask.getNode()))) {
4059 if (VT == MVT::v4f32) {
4061 Op = DAG.getNode(ISD::VECTOR_SHUFFLE, RVT,
4062 DAG.getNode(ISD::BIT_CONVERT, RVT, V1),
4063 DAG.getNode(ISD::UNDEF, RVT), PermMask);
4064 } else if (V2.getOpcode() != ISD::UNDEF)
4065 Op = DAG.getNode(ISD::VECTOR_SHUFFLE, RVT, V1,
4066 DAG.getNode(ISD::UNDEF, RVT), PermMask);
4068 Op = DAG.getNode(ISD::BIT_CONVERT, VT, Op);
4072 // Binary or unary shufps.
4073 if (X86::isSHUFPMask(PermMask.getNode()) ||
4074 (V2.getOpcode() == ISD::UNDEF && X86::isPSHUFDMask(PermMask.getNode())))
4078 // Handle v8i16 specifically since SSE can do byte extraction and insertion.
4079 if (VT == MVT::v8i16) {
4080 SDValue NewOp = LowerVECTOR_SHUFFLEv8i16(V1, V2, PermMask, DAG, *this);
4081 if (NewOp.getNode())
4085 // Handle all 4 wide cases with a number of shuffles except for MMX.
4086 if (NumElems == 4 && !isMMX)
4087 return LowerVECTOR_SHUFFLE_4wide(V1, V2, PermMask, VT, DAG);
4093 X86TargetLowering::LowerEXTRACT_VECTOR_ELT_SSE4(SDValue Op,
4094 SelectionDAG &DAG) {
4095 MVT VT = Op.getValueType();
4096 if (VT.getSizeInBits() == 8) {
4097 SDValue Extract = DAG.getNode(X86ISD::PEXTRB, MVT::i32,
4098 Op.getOperand(0), Op.getOperand(1));
4099 SDValue Assert = DAG.getNode(ISD::AssertZext, MVT::i32, Extract,
4100 DAG.getValueType(VT));
4101 return DAG.getNode(ISD::TRUNCATE, VT, Assert);
4102 } else if (VT.getSizeInBits() == 16) {
4103 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, MVT::i32,
4104 Op.getOperand(0), Op.getOperand(1));
4105 SDValue Assert = DAG.getNode(ISD::AssertZext, MVT::i32, Extract,
4106 DAG.getValueType(VT));
4107 return DAG.getNode(ISD::TRUNCATE, VT, Assert);
4108 } else if (VT == MVT::f32) {
4109 // EXTRACTPS outputs to a GPR32 register which will require a movd to copy
4110 // the result back to FR32 register. It's only worth matching if the
4111 // result has a single use which is a store or a bitcast to i32.
4112 if (!Op.hasOneUse())
4114 SDNode *User = *Op.getNode()->use_begin();
4115 if (User->getOpcode() != ISD::STORE &&
4116 (User->getOpcode() != ISD::BIT_CONVERT ||
4117 User->getValueType(0) != MVT::i32))
4119 SDValue Extract = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, MVT::i32,
4120 DAG.getNode(ISD::BIT_CONVERT, MVT::v4i32, Op.getOperand(0)),
4122 return DAG.getNode(ISD::BIT_CONVERT, MVT::f32, Extract);
4129 X86TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) {
4130 if (!isa<ConstantSDNode>(Op.getOperand(1)))
4133 if (Subtarget->hasSSE41()) {
4134 SDValue Res = LowerEXTRACT_VECTOR_ELT_SSE4(Op, DAG);
4139 MVT VT = Op.getValueType();
4140 // TODO: handle v16i8.
4141 if (VT.getSizeInBits() == 16) {
4142 SDValue Vec = Op.getOperand(0);
4143 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
4145 return DAG.getNode(ISD::TRUNCATE, MVT::i16,
4146 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, MVT::i32,
4147 DAG.getNode(ISD::BIT_CONVERT, MVT::v4i32, Vec),
4149 // Transform it so it match pextrw which produces a 32-bit result.
4150 MVT EVT = (MVT::SimpleValueType)(VT.getSimpleVT()+1);
4151 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, EVT,
4152 Op.getOperand(0), Op.getOperand(1));
4153 SDValue Assert = DAG.getNode(ISD::AssertZext, EVT, Extract,
4154 DAG.getValueType(VT));
4155 return DAG.getNode(ISD::TRUNCATE, VT, Assert);
4156 } else if (VT.getSizeInBits() == 32) {
4157 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
4160 // SHUFPS the element to the lowest double word, then movss.
4161 MVT MaskVT = MVT::getIntVectorWithNumElements(4);
4162 SmallVector<SDValue, 8> IdxVec;
4164 push_back(DAG.getConstant(Idx, MaskVT.getVectorElementType()));
4166 push_back(DAG.getNode(ISD::UNDEF, MaskVT.getVectorElementType()));
4168 push_back(DAG.getNode(ISD::UNDEF, MaskVT.getVectorElementType()));
4170 push_back(DAG.getNode(ISD::UNDEF, MaskVT.getVectorElementType()));
4171 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
4172 &IdxVec[0], IdxVec.size());
4173 SDValue Vec = Op.getOperand(0);
4174 Vec = DAG.getNode(ISD::VECTOR_SHUFFLE, Vec.getValueType(),
4175 Vec, DAG.getNode(ISD::UNDEF, Vec.getValueType()), Mask);
4176 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, VT, Vec,
4177 DAG.getIntPtrConstant(0));
4178 } else if (VT.getSizeInBits() == 64) {
4179 // FIXME: .td only matches this for <2 x f64>, not <2 x i64> on 32b
4180 // FIXME: seems like this should be unnecessary if mov{h,l}pd were taught
4181 // to match extract_elt for f64.
4182 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
4186 // UNPCKHPD the element to the lowest double word, then movsd.
4187 // Note if the lower 64 bits of the result of the UNPCKHPD is then stored
4188 // to a f64mem, the whole operation is folded into a single MOVHPDmr.
4189 MVT MaskVT = MVT::getIntVectorWithNumElements(2);
4190 SmallVector<SDValue, 8> IdxVec;
4191 IdxVec.push_back(DAG.getConstant(1, MaskVT.getVectorElementType()));
4193 push_back(DAG.getNode(ISD::UNDEF, MaskVT.getVectorElementType()));
4194 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
4195 &IdxVec[0], IdxVec.size());
4196 SDValue Vec = Op.getOperand(0);
4197 Vec = DAG.getNode(ISD::VECTOR_SHUFFLE, Vec.getValueType(),
4198 Vec, DAG.getNode(ISD::UNDEF, Vec.getValueType()), Mask);
4199 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, VT, Vec,
4200 DAG.getIntPtrConstant(0));
4207 X86TargetLowering::LowerINSERT_VECTOR_ELT_SSE4(SDValue Op, SelectionDAG &DAG){
4208 MVT VT = Op.getValueType();
4209 MVT EVT = VT.getVectorElementType();
4211 SDValue N0 = Op.getOperand(0);
4212 SDValue N1 = Op.getOperand(1);
4213 SDValue N2 = Op.getOperand(2);
4215 if ((EVT.getSizeInBits() == 8 || EVT.getSizeInBits() == 16) &&
4216 isa<ConstantSDNode>(N2)) {
4217 unsigned Opc = (EVT.getSizeInBits() == 8) ? X86ISD::PINSRB
4219 // Transform it so it match pinsr{b,w} which expects a GR32 as its second
4221 if (N1.getValueType() != MVT::i32)
4222 N1 = DAG.getNode(ISD::ANY_EXTEND, MVT::i32, N1);
4223 if (N2.getValueType() != MVT::i32)
4224 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue());
4225 return DAG.getNode(Opc, VT, N0, N1, N2);
4226 } else if (EVT == MVT::f32 && isa<ConstantSDNode>(N2)) {
4227 // Bits [7:6] of the constant are the source select. This will always be
4228 // zero here. The DAG Combiner may combine an extract_elt index into these
4229 // bits. For example (insert (extract, 3), 2) could be matched by putting
4230 // the '3' into bits [7:6] of X86ISD::INSERTPS.
4231 // Bits [5:4] of the constant are the destination select. This is the
4232 // value of the incoming immediate.
4233 // Bits [3:0] of the constant are the zero mask. The DAG Combiner may
4234 // combine either bitwise AND or insert of float 0.0 to set these bits.
4235 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue() << 4);
4236 return DAG.getNode(X86ISD::INSERTPS, VT, N0, N1, N2);
4242 X86TargetLowering::LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) {
4243 MVT VT = Op.getValueType();
4244 MVT EVT = VT.getVectorElementType();
4246 if (Subtarget->hasSSE41())
4247 return LowerINSERT_VECTOR_ELT_SSE4(Op, DAG);
4252 SDValue N0 = Op.getOperand(0);
4253 SDValue N1 = Op.getOperand(1);
4254 SDValue N2 = Op.getOperand(2);
4256 if (EVT.getSizeInBits() == 16) {
4257 // Transform it so it match pinsrw which expects a 16-bit value in a GR32
4258 // as its second argument.
4259 if (N1.getValueType() != MVT::i32)
4260 N1 = DAG.getNode(ISD::ANY_EXTEND, MVT::i32, N1);
4261 if (N2.getValueType() != MVT::i32)
4262 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue());
4263 return DAG.getNode(X86ISD::PINSRW, VT, N0, N1, N2);
4269 X86TargetLowering::LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) {
4270 if (Op.getValueType() == MVT::v2f32)
4271 return DAG.getNode(ISD::BIT_CONVERT, MVT::v2f32,
4272 DAG.getNode(ISD::SCALAR_TO_VECTOR, MVT::v2i32,
4273 DAG.getNode(ISD::BIT_CONVERT, MVT::i32,
4274 Op.getOperand(0))));
4276 SDValue AnyExt = DAG.getNode(ISD::ANY_EXTEND, MVT::i32, Op.getOperand(0));
4277 MVT VT = MVT::v2i32;
4278 switch (Op.getValueType().getSimpleVT()) {
4285 return DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(),
4286 DAG.getNode(ISD::SCALAR_TO_VECTOR, VT, AnyExt));
4289 // ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as
4290 // their target countpart wrapped in the X86ISD::Wrapper node. Suppose N is
4291 // one of the above mentioned nodes. It has to be wrapped because otherwise
4292 // Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only
4293 // be used to form addressing mode. These wrapped nodes will be selected
4296 X86TargetLowering::LowerConstantPool(SDValue Op, SelectionDAG &DAG) {
4297 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
4298 SDValue Result = DAG.getTargetConstantPool(CP->getConstVal(),
4300 CP->getAlignment());
4301 Result = DAG.getNode(X86ISD::Wrapper, getPointerTy(), Result);
4302 // With PIC, the address is actually $g + Offset.
4303 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
4304 !Subtarget->isPICStyleRIPRel()) {
4305 Result = DAG.getNode(ISD::ADD, getPointerTy(),
4306 DAG.getNode(X86ISD::GlobalBaseReg, getPointerTy()),
4314 X86TargetLowering::LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) {
4315 GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
4316 SDValue Result = DAG.getTargetGlobalAddress(GV, getPointerTy());
4317 Result = DAG.getNode(X86ISD::Wrapper, getPointerTy(), Result);
4318 // With PIC, the address is actually $g + Offset.
4319 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
4320 !Subtarget->isPICStyleRIPRel()) {
4321 Result = DAG.getNode(ISD::ADD, getPointerTy(),
4322 DAG.getNode(X86ISD::GlobalBaseReg, getPointerTy()),
4326 // For Darwin & Mingw32, external and weak symbols are indirect, so we want to
4327 // load the value at address GV, not the value of GV itself. This means that
4328 // the GlobalAddress must be in the base or index register of the address, not
4329 // the GV offset field. Platform check is inside GVRequiresExtraLoad() call
4330 // The same applies for external symbols during PIC codegen
4331 if (Subtarget->GVRequiresExtraLoad(GV, getTargetMachine(), false))
4332 Result = DAG.getLoad(getPointerTy(), DAG.getEntryNode(), Result,
4333 PseudoSourceValue::getGOT(), 0);
4338 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 32 bit
4340 LowerToTLSGeneralDynamicModel32(GlobalAddressSDNode *GA, SelectionDAG &DAG,
4343 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), X86::EBX,
4344 DAG.getNode(X86ISD::GlobalBaseReg,
4346 InFlag = Chain.getValue(1);
4348 // emit leal symbol@TLSGD(,%ebx,1), %eax
4349 SDVTList NodeTys = DAG.getVTList(PtrVT, MVT::Other, MVT::Flag);
4350 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(),
4351 GA->getValueType(0),
4353 SDValue Ops[] = { Chain, TGA, InFlag };
4354 SDValue Result = DAG.getNode(X86ISD::TLSADDR, NodeTys, Ops, 3);
4355 InFlag = Result.getValue(2);
4356 Chain = Result.getValue(1);
4358 // call ___tls_get_addr. This function receives its argument in
4359 // the register EAX.
4360 Chain = DAG.getCopyToReg(Chain, X86::EAX, Result, InFlag);
4361 InFlag = Chain.getValue(1);
4363 NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
4364 SDValue Ops1[] = { Chain,
4365 DAG.getTargetExternalSymbol("___tls_get_addr",
4367 DAG.getRegister(X86::EAX, PtrVT),
4368 DAG.getRegister(X86::EBX, PtrVT),
4370 Chain = DAG.getNode(X86ISD::CALL, NodeTys, Ops1, 5);
4371 InFlag = Chain.getValue(1);
4373 return DAG.getCopyFromReg(Chain, X86::EAX, PtrVT, InFlag);
4376 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 64 bit
4378 LowerToTLSGeneralDynamicModel64(GlobalAddressSDNode *GA, SelectionDAG &DAG,
4380 SDValue InFlag, Chain;
4382 // emit leaq symbol@TLSGD(%rip), %rdi
4383 SDVTList NodeTys = DAG.getVTList(PtrVT, MVT::Other, MVT::Flag);
4384 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(),
4385 GA->getValueType(0),
4387 SDValue Ops[] = { DAG.getEntryNode(), TGA};
4388 SDValue Result = DAG.getNode(X86ISD::TLSADDR, NodeTys, Ops, 2);
4389 Chain = Result.getValue(1);
4390 InFlag = Result.getValue(2);
4392 // call __tls_get_addr. This function receives its argument in
4393 // the register RDI.
4394 Chain = DAG.getCopyToReg(Chain, X86::RDI, Result, InFlag);
4395 InFlag = Chain.getValue(1);
4397 NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
4398 SDValue Ops1[] = { Chain,
4399 DAG.getTargetExternalSymbol("__tls_get_addr",
4401 DAG.getRegister(X86::RDI, PtrVT),
4403 Chain = DAG.getNode(X86ISD::CALL, NodeTys, Ops1, 4);
4404 InFlag = Chain.getValue(1);
4406 return DAG.getCopyFromReg(Chain, X86::RAX, PtrVT, InFlag);
4409 // Lower ISD::GlobalTLSAddress using the "initial exec" (for no-pic) or
4410 // "local exec" model.
4411 static SDValue LowerToTLSExecModel(GlobalAddressSDNode *GA, SelectionDAG &DAG,
4413 // Get the Thread Pointer
4414 SDValue ThreadPointer = DAG.getNode(X86ISD::THREAD_POINTER, PtrVT);
4415 // emit "addl x@ntpoff,%eax" (local exec) or "addl x@indntpoff,%eax" (initial
4417 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(),
4418 GA->getValueType(0),
4420 SDValue Offset = DAG.getNode(X86ISD::Wrapper, PtrVT, TGA);
4422 if (GA->getGlobal()->isDeclaration()) // initial exec TLS model
4423 Offset = DAG.getLoad(PtrVT, DAG.getEntryNode(), Offset,
4424 PseudoSourceValue::getGOT(), 0);
4426 // The address of the thread local variable is the add of the thread
4427 // pointer with the offset of the variable.
4428 return DAG.getNode(ISD::ADD, PtrVT, ThreadPointer, Offset);
4432 X86TargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) {
4433 // TODO: implement the "local dynamic" model
4434 // TODO: implement the "initial exec"model for pic executables
4435 assert(Subtarget->isTargetELF() &&
4436 "TLS not implemented for non-ELF targets");
4437 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
4438 // If the relocation model is PIC, use the "General Dynamic" TLS Model,
4439 // otherwise use the "Local Exec"TLS Model
4440 if (Subtarget->is64Bit()) {
4441 return LowerToTLSGeneralDynamicModel64(GA, DAG, getPointerTy());
4443 if (getTargetMachine().getRelocationModel() == Reloc::PIC_)
4444 return LowerToTLSGeneralDynamicModel32(GA, DAG, getPointerTy());
4446 return LowerToTLSExecModel(GA, DAG, getPointerTy());
4451 X86TargetLowering::LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) {
4452 const char *Sym = cast<ExternalSymbolSDNode>(Op)->getSymbol();
4453 SDValue Result = DAG.getTargetExternalSymbol(Sym, getPointerTy());
4454 Result = DAG.getNode(X86ISD::Wrapper, getPointerTy(), Result);
4455 // With PIC, the address is actually $g + Offset.
4456 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
4457 !Subtarget->isPICStyleRIPRel()) {
4458 Result = DAG.getNode(ISD::ADD, getPointerTy(),
4459 DAG.getNode(X86ISD::GlobalBaseReg, getPointerTy()),
4466 SDValue X86TargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) {
4467 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
4468 SDValue Result = DAG.getTargetJumpTable(JT->getIndex(), getPointerTy());
4469 Result = DAG.getNode(X86ISD::Wrapper, getPointerTy(), Result);
4470 // With PIC, the address is actually $g + Offset.
4471 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
4472 !Subtarget->isPICStyleRIPRel()) {
4473 Result = DAG.getNode(ISD::ADD, getPointerTy(),
4474 DAG.getNode(X86ISD::GlobalBaseReg, getPointerTy()),
4481 /// LowerShift - Lower SRA_PARTS and friends, which return two i32 values and
4482 /// take a 2 x i32 value to shift plus a shift amount.
4483 SDValue X86TargetLowering::LowerShift(SDValue Op, SelectionDAG &DAG) {
4484 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
4485 MVT VT = Op.getValueType();
4486 unsigned VTBits = VT.getSizeInBits();
4487 bool isSRA = Op.getOpcode() == ISD::SRA_PARTS;
4488 SDValue ShOpLo = Op.getOperand(0);
4489 SDValue ShOpHi = Op.getOperand(1);
4490 SDValue ShAmt = Op.getOperand(2);
4491 SDValue Tmp1 = isSRA ?
4492 DAG.getNode(ISD::SRA, VT, ShOpHi, DAG.getConstant(VTBits - 1, MVT::i8)) :
4493 DAG.getConstant(0, VT);
4496 if (Op.getOpcode() == ISD::SHL_PARTS) {
4497 Tmp2 = DAG.getNode(X86ISD::SHLD, VT, ShOpHi, ShOpLo, ShAmt);
4498 Tmp3 = DAG.getNode(ISD::SHL, VT, ShOpLo, ShAmt);
4500 Tmp2 = DAG.getNode(X86ISD::SHRD, VT, ShOpLo, ShOpHi, ShAmt);
4501 Tmp3 = DAG.getNode(isSRA ? ISD::SRA : ISD::SRL, VT, ShOpHi, ShAmt);
4504 SDValue AndNode = DAG.getNode(ISD::AND, MVT::i8, ShAmt,
4505 DAG.getConstant(VTBits, MVT::i8));
4506 SDValue Cond = DAG.getNode(X86ISD::CMP, VT,
4507 AndNode, DAG.getConstant(0, MVT::i8));
4510 SDValue CC = DAG.getConstant(X86::COND_NE, MVT::i8);
4511 SDValue Ops0[4] = { Tmp2, Tmp3, CC, Cond };
4512 SDValue Ops1[4] = { Tmp3, Tmp1, CC, Cond };
4514 if (Op.getOpcode() == ISD::SHL_PARTS) {
4515 Hi = DAG.getNode(X86ISD::CMOV, VT, Ops0, 4);
4516 Lo = DAG.getNode(X86ISD::CMOV, VT, Ops1, 4);
4518 Lo = DAG.getNode(X86ISD::CMOV, VT, Ops0, 4);
4519 Hi = DAG.getNode(X86ISD::CMOV, VT, Ops1, 4);
4522 SDValue Ops[2] = { Lo, Hi };
4523 return DAG.getMergeValues(Ops, 2);
4526 SDValue X86TargetLowering::LowerSINT_TO_FP(SDValue Op, SelectionDAG &DAG) {
4527 MVT SrcVT = Op.getOperand(0).getValueType();
4528 assert(SrcVT.getSimpleVT() <= MVT::i64 && SrcVT.getSimpleVT() >= MVT::i16 &&
4529 "Unknown SINT_TO_FP to lower!");
4531 // These are really Legal; caller falls through into that case.
4532 if (SrcVT == MVT::i32 && isScalarFPTypeInSSEReg(Op.getValueType()))
4534 if (SrcVT == MVT::i64 && Op.getValueType() != MVT::f80 &&
4535 Subtarget->is64Bit())
4538 unsigned Size = SrcVT.getSizeInBits()/8;
4539 MachineFunction &MF = DAG.getMachineFunction();
4540 int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size);
4541 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
4542 SDValue Chain = DAG.getStore(DAG.getEntryNode(), Op.getOperand(0),
4544 PseudoSourceValue::getFixedStack(SSFI), 0);
4548 bool useSSE = isScalarFPTypeInSSEReg(Op.getValueType());
4550 Tys = DAG.getVTList(MVT::f64, MVT::Other, MVT::Flag);
4552 Tys = DAG.getVTList(Op.getValueType(), MVT::Other);
4553 SmallVector<SDValue, 8> Ops;
4554 Ops.push_back(Chain);
4555 Ops.push_back(StackSlot);
4556 Ops.push_back(DAG.getValueType(SrcVT));
4557 SDValue Result = DAG.getNode(useSSE ? X86ISD::FILD_FLAG : X86ISD::FILD,
4558 Tys, &Ops[0], Ops.size());
4561 Chain = Result.getValue(1);
4562 SDValue InFlag = Result.getValue(2);
4564 // FIXME: Currently the FST is flagged to the FILD_FLAG. This
4565 // shouldn't be necessary except that RFP cannot be live across
4566 // multiple blocks. When stackifier is fixed, they can be uncoupled.
4567 MachineFunction &MF = DAG.getMachineFunction();
4568 int SSFI = MF.getFrameInfo()->CreateStackObject(8, 8);
4569 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
4570 Tys = DAG.getVTList(MVT::Other);
4571 SmallVector<SDValue, 8> Ops;
4572 Ops.push_back(Chain);
4573 Ops.push_back(Result);
4574 Ops.push_back(StackSlot);
4575 Ops.push_back(DAG.getValueType(Op.getValueType()));
4576 Ops.push_back(InFlag);
4577 Chain = DAG.getNode(X86ISD::FST, Tys, &Ops[0], Ops.size());
4578 Result = DAG.getLoad(Op.getValueType(), Chain, StackSlot,
4579 PseudoSourceValue::getFixedStack(SSFI), 0);
4585 std::pair<SDValue,SDValue> X86TargetLowering::
4586 FP_TO_SINTHelper(SDValue Op, SelectionDAG &DAG) {
4587 assert(Op.getValueType().getSimpleVT() <= MVT::i64 &&
4588 Op.getValueType().getSimpleVT() >= MVT::i16 &&
4589 "Unknown FP_TO_SINT to lower!");
4591 // These are really Legal.
4592 if (Op.getValueType() == MVT::i32 &&
4593 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
4594 return std::make_pair(SDValue(), SDValue());
4595 if (Subtarget->is64Bit() &&
4596 Op.getValueType() == MVT::i64 &&
4597 Op.getOperand(0).getValueType() != MVT::f80)
4598 return std::make_pair(SDValue(), SDValue());
4600 // We lower FP->sint64 into FISTP64, followed by a load, all to a temporary
4602 MachineFunction &MF = DAG.getMachineFunction();
4603 unsigned MemSize = Op.getValueType().getSizeInBits()/8;
4604 int SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize);
4605 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
4607 switch (Op.getValueType().getSimpleVT()) {
4608 default: assert(0 && "Invalid FP_TO_SINT to lower!");
4609 case MVT::i16: Opc = X86ISD::FP_TO_INT16_IN_MEM; break;
4610 case MVT::i32: Opc = X86ISD::FP_TO_INT32_IN_MEM; break;
4611 case MVT::i64: Opc = X86ISD::FP_TO_INT64_IN_MEM; break;
4614 SDValue Chain = DAG.getEntryNode();
4615 SDValue Value = Op.getOperand(0);
4616 if (isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType())) {
4617 assert(Op.getValueType() == MVT::i64 && "Invalid FP_TO_SINT to lower!");
4618 Chain = DAG.getStore(Chain, Value, StackSlot,
4619 PseudoSourceValue::getFixedStack(SSFI), 0);
4620 SDVTList Tys = DAG.getVTList(Op.getOperand(0).getValueType(), MVT::Other);
4622 Chain, StackSlot, DAG.getValueType(Op.getOperand(0).getValueType())
4624 Value = DAG.getNode(X86ISD::FLD, Tys, Ops, 3);
4625 Chain = Value.getValue(1);
4626 SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize);
4627 StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
4630 // Build the FP_TO_INT*_IN_MEM
4631 SDValue Ops[] = { Chain, Value, StackSlot };
4632 SDValue FIST = DAG.getNode(Opc, MVT::Other, Ops, 3);
4634 return std::make_pair(FIST, StackSlot);
4637 SDValue X86TargetLowering::LowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG) {
4638 std::pair<SDValue,SDValue> Vals = FP_TO_SINTHelper(Op, DAG);
4639 SDValue FIST = Vals.first, StackSlot = Vals.second;
4640 if (FIST.getNode() == 0) return SDValue();
4643 return DAG.getLoad(Op.getValueType(), FIST, StackSlot, NULL, 0);
4646 SDNode *X86TargetLowering::ExpandFP_TO_SINT(SDNode *N, SelectionDAG &DAG) {
4647 std::pair<SDValue,SDValue> Vals = FP_TO_SINTHelper(SDValue(N, 0), DAG);
4648 SDValue FIST = Vals.first, StackSlot = Vals.second;
4649 if (FIST.getNode() == 0) return 0;
4651 MVT VT = N->getValueType(0);
4653 // Return a load from the stack slot.
4654 SDValue Res = DAG.getLoad(VT, FIST, StackSlot, NULL, 0);
4656 // Use MERGE_VALUES to drop the chain result value and get a node with one
4657 // result. This requires turning off getMergeValues simplification, since
4658 // otherwise it will give us Res back.
4659 return DAG.getMergeValues(&Res, 1, false).getNode();
4662 SDValue X86TargetLowering::LowerFABS(SDValue Op, SelectionDAG &DAG) {
4663 MVT VT = Op.getValueType();
4666 EltVT = VT.getVectorElementType();
4667 std::vector<Constant*> CV;
4668 if (EltVT == MVT::f64) {
4669 Constant *C = ConstantFP::get(APFloat(APInt(64, ~(1ULL << 63))));
4673 Constant *C = ConstantFP::get(APFloat(APInt(32, ~(1U << 31))));
4679 Constant *C = ConstantVector::get(CV);
4680 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 4);
4681 SDValue Mask = DAG.getLoad(VT, DAG.getEntryNode(), CPIdx,
4682 PseudoSourceValue::getConstantPool(), 0,
4684 return DAG.getNode(X86ISD::FAND, VT, Op.getOperand(0), Mask);
4687 SDValue X86TargetLowering::LowerFNEG(SDValue Op, SelectionDAG &DAG) {
4688 MVT VT = Op.getValueType();
4690 unsigned EltNum = 1;
4691 if (VT.isVector()) {
4692 EltVT = VT.getVectorElementType();
4693 EltNum = VT.getVectorNumElements();
4695 std::vector<Constant*> CV;
4696 if (EltVT == MVT::f64) {
4697 Constant *C = ConstantFP::get(APFloat(APInt(64, 1ULL << 63)));
4701 Constant *C = ConstantFP::get(APFloat(APInt(32, 1U << 31)));
4707 Constant *C = ConstantVector::get(CV);
4708 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 4);
4709 SDValue Mask = DAG.getLoad(VT, DAG.getEntryNode(), CPIdx,
4710 PseudoSourceValue::getConstantPool(), 0,
4712 if (VT.isVector()) {
4713 return DAG.getNode(ISD::BIT_CONVERT, VT,
4714 DAG.getNode(ISD::XOR, MVT::v2i64,
4715 DAG.getNode(ISD::BIT_CONVERT, MVT::v2i64, Op.getOperand(0)),
4716 DAG.getNode(ISD::BIT_CONVERT, MVT::v2i64, Mask)));
4718 return DAG.getNode(X86ISD::FXOR, VT, Op.getOperand(0), Mask);
4722 SDValue X86TargetLowering::LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) {
4723 SDValue Op0 = Op.getOperand(0);
4724 SDValue Op1 = Op.getOperand(1);
4725 MVT VT = Op.getValueType();
4726 MVT SrcVT = Op1.getValueType();
4728 // If second operand is smaller, extend it first.
4729 if (SrcVT.bitsLT(VT)) {
4730 Op1 = DAG.getNode(ISD::FP_EXTEND, VT, Op1);
4733 // And if it is bigger, shrink it first.
4734 if (SrcVT.bitsGT(VT)) {
4735 Op1 = DAG.getNode(ISD::FP_ROUND, VT, Op1, DAG.getIntPtrConstant(1));
4739 // At this point the operands and the result should have the same
4740 // type, and that won't be f80 since that is not custom lowered.
4742 // First get the sign bit of second operand.
4743 std::vector<Constant*> CV;
4744 if (SrcVT == MVT::f64) {
4745 CV.push_back(ConstantFP::get(APFloat(APInt(64, 1ULL << 63))));
4746 CV.push_back(ConstantFP::get(APFloat(APInt(64, 0))));
4748 CV.push_back(ConstantFP::get(APFloat(APInt(32, 1U << 31))));
4749 CV.push_back(ConstantFP::get(APFloat(APInt(32, 0))));
4750 CV.push_back(ConstantFP::get(APFloat(APInt(32, 0))));
4751 CV.push_back(ConstantFP::get(APFloat(APInt(32, 0))));
4753 Constant *C = ConstantVector::get(CV);
4754 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 4);
4755 SDValue Mask1 = DAG.getLoad(SrcVT, DAG.getEntryNode(), CPIdx,
4756 PseudoSourceValue::getConstantPool(), 0,
4758 SDValue SignBit = DAG.getNode(X86ISD::FAND, SrcVT, Op1, Mask1);
4760 // Shift sign bit right or left if the two operands have different types.
4761 if (SrcVT.bitsGT(VT)) {
4762 // Op0 is MVT::f32, Op1 is MVT::f64.
4763 SignBit = DAG.getNode(ISD::SCALAR_TO_VECTOR, MVT::v2f64, SignBit);
4764 SignBit = DAG.getNode(X86ISD::FSRL, MVT::v2f64, SignBit,
4765 DAG.getConstant(32, MVT::i32));
4766 SignBit = DAG.getNode(ISD::BIT_CONVERT, MVT::v4f32, SignBit);
4767 SignBit = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, MVT::f32, SignBit,
4768 DAG.getIntPtrConstant(0));
4771 // Clear first operand sign bit.
4773 if (VT == MVT::f64) {
4774 CV.push_back(ConstantFP::get(APFloat(APInt(64, ~(1ULL << 63)))));
4775 CV.push_back(ConstantFP::get(APFloat(APInt(64, 0))));
4777 CV.push_back(ConstantFP::get(APFloat(APInt(32, ~(1U << 31)))));
4778 CV.push_back(ConstantFP::get(APFloat(APInt(32, 0))));
4779 CV.push_back(ConstantFP::get(APFloat(APInt(32, 0))));
4780 CV.push_back(ConstantFP::get(APFloat(APInt(32, 0))));
4782 C = ConstantVector::get(CV);
4783 CPIdx = DAG.getConstantPool(C, getPointerTy(), 4);
4784 SDValue Mask2 = DAG.getLoad(VT, DAG.getEntryNode(), CPIdx,
4785 PseudoSourceValue::getConstantPool(), 0,
4787 SDValue Val = DAG.getNode(X86ISD::FAND, VT, Op0, Mask2);
4789 // Or the value with the sign bit.
4790 return DAG.getNode(X86ISD::FOR, VT, Val, SignBit);
4793 SDValue X86TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) {
4794 assert(Op.getValueType() == MVT::i8 && "SetCC type must be 8-bit integer");
4796 SDValue Op0 = Op.getOperand(0);
4797 SDValue Op1 = Op.getOperand(1);
4798 SDValue CC = Op.getOperand(2);
4799 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
4800 bool isFP = Op.getOperand(1).getValueType().isFloatingPoint();
4803 if (translateX86CC(cast<CondCodeSDNode>(CC)->get(), isFP, X86CC,
4805 Cond = DAG.getNode(X86ISD::CMP, MVT::i32, Op0, Op1);
4806 return DAG.getNode(X86ISD::SETCC, MVT::i8,
4807 DAG.getConstant(X86CC, MVT::i8), Cond);
4810 assert(isFP && "Illegal integer SetCC!");
4812 Cond = DAG.getNode(X86ISD::CMP, MVT::i32, Op0, Op1);
4813 switch (SetCCOpcode) {
4814 default: assert(false && "Illegal floating point SetCC!");
4815 case ISD::SETOEQ: { // !PF & ZF
4816 SDValue Tmp1 = DAG.getNode(X86ISD::SETCC, MVT::i8,
4817 DAG.getConstant(X86::COND_NP, MVT::i8), Cond);
4818 SDValue Tmp2 = DAG.getNode(X86ISD::SETCC, MVT::i8,
4819 DAG.getConstant(X86::COND_E, MVT::i8), Cond);
4820 return DAG.getNode(ISD::AND, MVT::i8, Tmp1, Tmp2);
4822 case ISD::SETUNE: { // PF | !ZF
4823 SDValue Tmp1 = DAG.getNode(X86ISD::SETCC, MVT::i8,
4824 DAG.getConstant(X86::COND_P, MVT::i8), Cond);
4825 SDValue Tmp2 = DAG.getNode(X86ISD::SETCC, MVT::i8,
4826 DAG.getConstant(X86::COND_NE, MVT::i8), Cond);
4827 return DAG.getNode(ISD::OR, MVT::i8, Tmp1, Tmp2);
4832 SDValue X86TargetLowering::LowerVSETCC(SDValue Op, SelectionDAG &DAG) {
4834 SDValue Op0 = Op.getOperand(0);
4835 SDValue Op1 = Op.getOperand(1);
4836 SDValue CC = Op.getOperand(2);
4837 MVT VT = Op.getValueType();
4838 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
4839 bool isFP = Op.getOperand(1).getValueType().isFloatingPoint();
4843 MVT VT0 = Op0.getValueType();
4844 assert(VT0 == MVT::v4f32 || VT0 == MVT::v2f64);
4845 unsigned Opc = VT0 == MVT::v4f32 ? X86ISD::CMPPS : X86ISD::CMPPD;
4848 switch (SetCCOpcode) {
4851 case ISD::SETEQ: SSECC = 0; break;
4853 case ISD::SETGT: Swap = true; // Fallthrough
4855 case ISD::SETOLT: SSECC = 1; break;
4857 case ISD::SETGE: Swap = true; // Fallthrough
4859 case ISD::SETOLE: SSECC = 2; break;
4860 case ISD::SETUO: SSECC = 3; break;
4862 case ISD::SETNE: SSECC = 4; break;
4863 case ISD::SETULE: Swap = true;
4864 case ISD::SETUGE: SSECC = 5; break;
4865 case ISD::SETULT: Swap = true;
4866 case ISD::SETUGT: SSECC = 6; break;
4867 case ISD::SETO: SSECC = 7; break;
4870 std::swap(Op0, Op1);
4872 // In the two special cases we can't handle, emit two comparisons.
4874 if (SetCCOpcode == ISD::SETUEQ) {
4876 UNORD = DAG.getNode(Opc, VT, Op0, Op1, DAG.getConstant(3, MVT::i8));
4877 EQ = DAG.getNode(Opc, VT, Op0, Op1, DAG.getConstant(0, MVT::i8));
4878 return DAG.getNode(ISD::OR, VT, UNORD, EQ);
4880 else if (SetCCOpcode == ISD::SETONE) {
4882 ORD = DAG.getNode(Opc, VT, Op0, Op1, DAG.getConstant(7, MVT::i8));
4883 NEQ = DAG.getNode(Opc, VT, Op0, Op1, DAG.getConstant(4, MVT::i8));
4884 return DAG.getNode(ISD::AND, VT, ORD, NEQ);
4886 assert(0 && "Illegal FP comparison");
4888 // Handle all other FP comparisons here.
4889 return DAG.getNode(Opc, VT, Op0, Op1, DAG.getConstant(SSECC, MVT::i8));
4892 // We are handling one of the integer comparisons here. Since SSE only has
4893 // GT and EQ comparisons for integer, swapping operands and multiple
4894 // operations may be required for some comparisons.
4895 unsigned Opc = 0, EQOpc = 0, GTOpc = 0;
4896 bool Swap = false, Invert = false, FlipSigns = false;
4898 switch (VT.getSimpleVT()) {
4900 case MVT::v16i8: EQOpc = X86ISD::PCMPEQB; GTOpc = X86ISD::PCMPGTB; break;
4901 case MVT::v8i16: EQOpc = X86ISD::PCMPEQW; GTOpc = X86ISD::PCMPGTW; break;
4902 case MVT::v4i32: EQOpc = X86ISD::PCMPEQD; GTOpc = X86ISD::PCMPGTD; break;
4903 case MVT::v2i64: EQOpc = X86ISD::PCMPEQQ; GTOpc = X86ISD::PCMPGTQ; break;
4906 switch (SetCCOpcode) {
4908 case ISD::SETNE: Invert = true;
4909 case ISD::SETEQ: Opc = EQOpc; break;
4910 case ISD::SETLT: Swap = true;
4911 case ISD::SETGT: Opc = GTOpc; break;
4912 case ISD::SETGE: Swap = true;
4913 case ISD::SETLE: Opc = GTOpc; Invert = true; break;
4914 case ISD::SETULT: Swap = true;
4915 case ISD::SETUGT: Opc = GTOpc; FlipSigns = true; break;
4916 case ISD::SETUGE: Swap = true;
4917 case ISD::SETULE: Opc = GTOpc; FlipSigns = true; Invert = true; break;
4920 std::swap(Op0, Op1);
4922 // Since SSE has no unsigned integer comparisons, we need to flip the sign
4923 // bits of the inputs before performing those operations.
4925 MVT EltVT = VT.getVectorElementType();
4926 SDValue SignBit = DAG.getConstant(EltVT.getIntegerVTSignBit(), EltVT);
4927 std::vector<SDValue> SignBits(VT.getVectorNumElements(), SignBit);
4928 SDValue SignVec = DAG.getNode(ISD::BUILD_VECTOR, VT, &SignBits[0],
4930 Op0 = DAG.getNode(ISD::XOR, VT, Op0, SignVec);
4931 Op1 = DAG.getNode(ISD::XOR, VT, Op1, SignVec);
4934 SDValue Result = DAG.getNode(Opc, VT, Op0, Op1);
4936 // If the logical-not of the result is required, perform that now.
4938 MVT EltVT = VT.getVectorElementType();
4939 SDValue NegOne = DAG.getConstant(EltVT.getIntegerVTBitMask(), EltVT);
4940 std::vector<SDValue> NegOnes(VT.getVectorNumElements(), NegOne);
4941 SDValue NegOneV = DAG.getNode(ISD::BUILD_VECTOR, VT, &NegOnes[0],
4943 Result = DAG.getNode(ISD::XOR, VT, Result, NegOneV);
4948 SDValue X86TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) {
4949 bool addTest = true;
4950 SDValue Cond = Op.getOperand(0);
4953 if (Cond.getOpcode() == ISD::SETCC)
4954 Cond = LowerSETCC(Cond, DAG);
4956 // If condition flag is set by a X86ISD::CMP, then use it as the condition
4957 // setting operand in place of the X86ISD::SETCC.
4958 if (Cond.getOpcode() == X86ISD::SETCC) {
4959 CC = Cond.getOperand(0);
4961 SDValue Cmp = Cond.getOperand(1);
4962 unsigned Opc = Cmp.getOpcode();
4963 MVT VT = Op.getValueType();
4965 bool IllegalFPCMov = false;
4966 if (VT.isFloatingPoint() && !VT.isVector() &&
4967 !isScalarFPTypeInSSEReg(VT)) // FPStack?
4968 IllegalFPCMov = !hasFPCMov(cast<ConstantSDNode>(CC)->getSignExtended());
4970 if ((Opc == X86ISD::CMP ||
4971 Opc == X86ISD::COMI ||
4972 Opc == X86ISD::UCOMI) && !IllegalFPCMov) {
4979 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
4980 Cond= DAG.getNode(X86ISD::CMP, MVT::i32, Cond, DAG.getConstant(0, MVT::i8));
4983 const MVT *VTs = DAG.getNodeValueTypes(Op.getValueType(),
4985 SmallVector<SDValue, 4> Ops;
4986 // X86ISD::CMOV means set the result (which is operand 1) to the RHS if
4987 // condition is true.
4988 Ops.push_back(Op.getOperand(2));
4989 Ops.push_back(Op.getOperand(1));
4991 Ops.push_back(Cond);
4992 return DAG.getNode(X86ISD::CMOV, VTs, 2, &Ops[0], Ops.size());
4995 SDValue X86TargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) {
4996 bool addTest = true;
4997 SDValue Chain = Op.getOperand(0);
4998 SDValue Cond = Op.getOperand(1);
4999 SDValue Dest = Op.getOperand(2);
5002 if (Cond.getOpcode() == ISD::SETCC)
5003 Cond = LowerSETCC(Cond, DAG);
5005 // If condition flag is set by a X86ISD::CMP, then use it as the condition
5006 // setting operand in place of the X86ISD::SETCC.
5007 if (Cond.getOpcode() == X86ISD::SETCC) {
5008 CC = Cond.getOperand(0);
5010 SDValue Cmp = Cond.getOperand(1);
5011 unsigned Opc = Cmp.getOpcode();
5012 if (Opc == X86ISD::CMP ||
5013 Opc == X86ISD::COMI ||
5014 Opc == X86ISD::UCOMI) {
5021 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
5022 Cond= DAG.getNode(X86ISD::CMP, MVT::i32, Cond, DAG.getConstant(0, MVT::i8));
5024 return DAG.getNode(X86ISD::BRCOND, Op.getValueType(),
5025 Chain, Op.getOperand(2), CC, Cond);
5029 // Lower dynamic stack allocation to _alloca call for Cygwin/Mingw targets.
5030 // Calls to _alloca is needed to probe the stack when allocating more than 4k
5031 // bytes in one go. Touching the stack at 4K increments is necessary to ensure
5032 // that the guard pages used by the OS virtual memory manager are allocated in
5033 // correct sequence.
5035 X86TargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
5036 SelectionDAG &DAG) {
5037 assert(Subtarget->isTargetCygMing() &&
5038 "This should be used only on Cygwin/Mingw targets");
5041 SDValue Chain = Op.getOperand(0);
5042 SDValue Size = Op.getOperand(1);
5043 // FIXME: Ensure alignment here
5047 MVT IntPtr = getPointerTy();
5048 MVT SPTy = Subtarget->is64Bit() ? MVT::i64 : MVT::i32;
5050 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(0));
5052 Chain = DAG.getCopyToReg(Chain, X86::EAX, Size, Flag);
5053 Flag = Chain.getValue(1);
5055 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
5056 SDValue Ops[] = { Chain,
5057 DAG.getTargetExternalSymbol("_alloca", IntPtr),
5058 DAG.getRegister(X86::EAX, IntPtr),
5059 DAG.getRegister(X86StackPtr, SPTy),
5061 Chain = DAG.getNode(X86ISD::CALL, NodeTys, Ops, 5);
5062 Flag = Chain.getValue(1);
5064 Chain = DAG.getCALLSEQ_END(Chain,
5065 DAG.getIntPtrConstant(0),
5066 DAG.getIntPtrConstant(0),
5069 Chain = DAG.getCopyFromReg(Chain, X86StackPtr, SPTy).getValue(1);
5071 SDValue Ops1[2] = { Chain.getValue(0), Chain };
5072 return DAG.getMergeValues(Ops1, 2);
5076 X86TargetLowering::EmitTargetCodeForMemset(SelectionDAG &DAG,
5078 SDValue Dst, SDValue Src,
5079 SDValue Size, unsigned Align,
5080 const Value *DstSV, uint64_t DstSVOff) {
5081 ConstantSDNode *ConstantSize = dyn_cast<ConstantSDNode>(Size);
5083 /// If not DWORD aligned or size is more than the threshold, call the library.
5084 /// The libc version is likely to be faster for these cases. It can use the
5085 /// address value and run time information about the CPU.
5086 if ((Align & 3) != 0 ||
5088 ConstantSize->getZExtValue() >
5089 getSubtarget()->getMaxInlineSizeThreshold()) {
5090 SDValue InFlag(0, 0);
5092 // Check to see if there is a specialized entry-point for memory zeroing.
5093 ConstantSDNode *V = dyn_cast<ConstantSDNode>(Src);
5094 if (const char *bzeroEntry =
5095 V && V->isNullValue() ? Subtarget->getBZeroEntry() : 0) {
5096 MVT IntPtr = getPointerTy();
5097 const Type *IntPtrTy = TD->getIntPtrType();
5098 TargetLowering::ArgListTy Args;
5099 TargetLowering::ArgListEntry Entry;
5101 Entry.Ty = IntPtrTy;
5102 Args.push_back(Entry);
5104 Args.push_back(Entry);
5105 std::pair<SDValue,SDValue> CallResult =
5106 LowerCallTo(Chain, Type::VoidTy, false, false, false, CallingConv::C,
5107 false, DAG.getExternalSymbol(bzeroEntry, IntPtr),
5109 return CallResult.second;
5112 // Otherwise have the target-independent code call memset.
5116 uint64_t SizeVal = ConstantSize->getZExtValue();
5117 SDValue InFlag(0, 0);
5120 ConstantSDNode *ValC = dyn_cast<ConstantSDNode>(Src);
5121 unsigned BytesLeft = 0;
5122 bool TwoRepStos = false;
5125 uint64_t Val = ValC->getZExtValue() & 255;
5127 // If the value is a constant, then we can potentially use larger sets.
5128 switch (Align & 3) {
5129 case 2: // WORD aligned
5132 Val = (Val << 8) | Val;
5134 case 0: // DWORD aligned
5137 Val = (Val << 8) | Val;
5138 Val = (Val << 16) | Val;
5139 if (Subtarget->is64Bit() && ((Align & 0x7) == 0)) { // QWORD aligned
5142 Val = (Val << 32) | Val;
5145 default: // Byte aligned
5148 Count = DAG.getIntPtrConstant(SizeVal);
5152 if (AVT.bitsGT(MVT::i8)) {
5153 unsigned UBytes = AVT.getSizeInBits() / 8;
5154 Count = DAG.getIntPtrConstant(SizeVal / UBytes);
5155 BytesLeft = SizeVal % UBytes;
5158 Chain = DAG.getCopyToReg(Chain, ValReg, DAG.getConstant(Val, AVT),
5160 InFlag = Chain.getValue(1);
5163 Count = DAG.getIntPtrConstant(SizeVal);
5164 Chain = DAG.getCopyToReg(Chain, X86::AL, Src, InFlag);
5165 InFlag = Chain.getValue(1);
5168 Chain = DAG.getCopyToReg(Chain, Subtarget->is64Bit() ? X86::RCX : X86::ECX,
5170 InFlag = Chain.getValue(1);
5171 Chain = DAG.getCopyToReg(Chain, Subtarget->is64Bit() ? X86::RDI : X86::EDI,
5173 InFlag = Chain.getValue(1);
5175 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
5176 SmallVector<SDValue, 8> Ops;
5177 Ops.push_back(Chain);
5178 Ops.push_back(DAG.getValueType(AVT));
5179 Ops.push_back(InFlag);
5180 Chain = DAG.getNode(X86ISD::REP_STOS, Tys, &Ops[0], Ops.size());
5183 InFlag = Chain.getValue(1);
5185 MVT CVT = Count.getValueType();
5186 SDValue Left = DAG.getNode(ISD::AND, CVT, Count,
5187 DAG.getConstant((AVT == MVT::i64) ? 7 : 3, CVT));
5188 Chain = DAG.getCopyToReg(Chain, (CVT == MVT::i64) ? X86::RCX : X86::ECX,
5190 InFlag = Chain.getValue(1);
5191 Tys = DAG.getVTList(MVT::Other, MVT::Flag);
5193 Ops.push_back(Chain);
5194 Ops.push_back(DAG.getValueType(MVT::i8));
5195 Ops.push_back(InFlag);
5196 Chain = DAG.getNode(X86ISD::REP_STOS, Tys, &Ops[0], Ops.size());
5197 } else if (BytesLeft) {
5198 // Handle the last 1 - 7 bytes.
5199 unsigned Offset = SizeVal - BytesLeft;
5200 MVT AddrVT = Dst.getValueType();
5201 MVT SizeVT = Size.getValueType();
5203 Chain = DAG.getMemset(Chain,
5204 DAG.getNode(ISD::ADD, AddrVT, Dst,
5205 DAG.getConstant(Offset, AddrVT)),
5207 DAG.getConstant(BytesLeft, SizeVT),
5208 Align, DstSV, DstSVOff + Offset);
5211 // TODO: Use a Tokenfactor, as in memcpy, instead of a single chain.
5216 X86TargetLowering::EmitTargetCodeForMemcpy(SelectionDAG &DAG,
5217 SDValue Chain, SDValue Dst, SDValue Src,
5218 SDValue Size, unsigned Align,
5220 const Value *DstSV, uint64_t DstSVOff,
5221 const Value *SrcSV, uint64_t SrcSVOff) {
5222 // This requires the copy size to be a constant, preferrably
5223 // within a subtarget-specific limit.
5224 ConstantSDNode *ConstantSize = dyn_cast<ConstantSDNode>(Size);
5227 uint64_t SizeVal = ConstantSize->getZExtValue();
5228 if (!AlwaysInline && SizeVal > getSubtarget()->getMaxInlineSizeThreshold())
5231 /// If not DWORD aligned, call the library.
5232 if ((Align & 3) != 0)
5237 if (Subtarget->is64Bit() && ((Align & 0x7) == 0)) // QWORD aligned
5240 unsigned UBytes = AVT.getSizeInBits() / 8;
5241 unsigned CountVal = SizeVal / UBytes;
5242 SDValue Count = DAG.getIntPtrConstant(CountVal);
5243 unsigned BytesLeft = SizeVal % UBytes;
5245 SDValue InFlag(0, 0);
5246 Chain = DAG.getCopyToReg(Chain, Subtarget->is64Bit() ? X86::RCX : X86::ECX,
5248 InFlag = Chain.getValue(1);
5249 Chain = DAG.getCopyToReg(Chain, Subtarget->is64Bit() ? X86::RDI : X86::EDI,
5251 InFlag = Chain.getValue(1);
5252 Chain = DAG.getCopyToReg(Chain, Subtarget->is64Bit() ? X86::RSI : X86::ESI,
5254 InFlag = Chain.getValue(1);
5256 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
5257 SmallVector<SDValue, 8> Ops;
5258 Ops.push_back(Chain);
5259 Ops.push_back(DAG.getValueType(AVT));
5260 Ops.push_back(InFlag);
5261 SDValue RepMovs = DAG.getNode(X86ISD::REP_MOVS, Tys, &Ops[0], Ops.size());
5263 SmallVector<SDValue, 4> Results;
5264 Results.push_back(RepMovs);
5266 // Handle the last 1 - 7 bytes.
5267 unsigned Offset = SizeVal - BytesLeft;
5268 MVT DstVT = Dst.getValueType();
5269 MVT SrcVT = Src.getValueType();
5270 MVT SizeVT = Size.getValueType();
5271 Results.push_back(DAG.getMemcpy(Chain,
5272 DAG.getNode(ISD::ADD, DstVT, Dst,
5273 DAG.getConstant(Offset, DstVT)),
5274 DAG.getNode(ISD::ADD, SrcVT, Src,
5275 DAG.getConstant(Offset, SrcVT)),
5276 DAG.getConstant(BytesLeft, SizeVT),
5277 Align, AlwaysInline,
5278 DstSV, DstSVOff + Offset,
5279 SrcSV, SrcSVOff + Offset));
5282 return DAG.getNode(ISD::TokenFactor, MVT::Other, &Results[0], Results.size());
5285 /// Expand the result of: i64,outchain = READCYCLECOUNTER inchain
5286 SDNode *X86TargetLowering::ExpandREADCYCLECOUNTER(SDNode *N, SelectionDAG &DAG){
5287 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
5288 SDValue TheChain = N->getOperand(0);
5289 SDValue rd = DAG.getNode(X86ISD::RDTSC_DAG, Tys, &TheChain, 1);
5290 if (Subtarget->is64Bit()) {
5291 SDValue rax = DAG.getCopyFromReg(rd, X86::RAX, MVT::i64, rd.getValue(1));
5292 SDValue rdx = DAG.getCopyFromReg(rax.getValue(1), X86::RDX,
5293 MVT::i64, rax.getValue(2));
5294 SDValue Tmp = DAG.getNode(ISD::SHL, MVT::i64, rdx,
5295 DAG.getConstant(32, MVT::i8));
5297 DAG.getNode(ISD::OR, MVT::i64, rax, Tmp), rdx.getValue(1)
5300 return DAG.getMergeValues(Ops, 2).getNode();
5303 SDValue eax = DAG.getCopyFromReg(rd, X86::EAX, MVT::i32, rd.getValue(1));
5304 SDValue edx = DAG.getCopyFromReg(eax.getValue(1), X86::EDX,
5305 MVT::i32, eax.getValue(2));
5306 // Use a buildpair to merge the two 32-bit values into a 64-bit one.
5307 SDValue Ops[] = { eax, edx };
5308 Ops[0] = DAG.getNode(ISD::BUILD_PAIR, MVT::i64, Ops, 2);
5310 // Use a MERGE_VALUES to return the value and chain.
5311 Ops[1] = edx.getValue(1);
5312 return DAG.getMergeValues(Ops, 2).getNode();
5315 SDValue X86TargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) {
5316 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
5318 if (!Subtarget->is64Bit()) {
5319 // vastart just stores the address of the VarArgsFrameIndex slot into the
5320 // memory location argument.
5321 SDValue FR = DAG.getFrameIndex(VarArgsFrameIndex, getPointerTy());
5322 return DAG.getStore(Op.getOperand(0), FR,Op.getOperand(1), SV, 0);
5326 // gp_offset (0 - 6 * 8)
5327 // fp_offset (48 - 48 + 8 * 16)
5328 // overflow_arg_area (point to parameters coming in memory).
5330 SmallVector<SDValue, 8> MemOps;
5331 SDValue FIN = Op.getOperand(1);
5333 SDValue Store = DAG.getStore(Op.getOperand(0),
5334 DAG.getConstant(VarArgsGPOffset, MVT::i32),
5336 MemOps.push_back(Store);
5339 FIN = DAG.getNode(ISD::ADD, getPointerTy(), FIN, DAG.getIntPtrConstant(4));
5340 Store = DAG.getStore(Op.getOperand(0),
5341 DAG.getConstant(VarArgsFPOffset, MVT::i32),
5343 MemOps.push_back(Store);
5345 // Store ptr to overflow_arg_area
5346 FIN = DAG.getNode(ISD::ADD, getPointerTy(), FIN, DAG.getIntPtrConstant(4));
5347 SDValue OVFIN = DAG.getFrameIndex(VarArgsFrameIndex, getPointerTy());
5348 Store = DAG.getStore(Op.getOperand(0), OVFIN, FIN, SV, 0);
5349 MemOps.push_back(Store);
5351 // Store ptr to reg_save_area.
5352 FIN = DAG.getNode(ISD::ADD, getPointerTy(), FIN, DAG.getIntPtrConstant(8));
5353 SDValue RSFIN = DAG.getFrameIndex(RegSaveFrameIndex, getPointerTy());
5354 Store = DAG.getStore(Op.getOperand(0), RSFIN, FIN, SV, 0);
5355 MemOps.push_back(Store);
5356 return DAG.getNode(ISD::TokenFactor, MVT::Other, &MemOps[0], MemOps.size());
5359 SDValue X86TargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG) {
5360 // X86-64 va_list is a struct { i32, i32, i8*, i8* }.
5361 assert(Subtarget->is64Bit() && "This code only handles 64-bit va_arg!");
5362 SDValue Chain = Op.getOperand(0);
5363 SDValue SrcPtr = Op.getOperand(1);
5364 SDValue SrcSV = Op.getOperand(2);
5366 assert(0 && "VAArgInst is not yet implemented for x86-64!");
5371 SDValue X86TargetLowering::LowerVACOPY(SDValue Op, SelectionDAG &DAG) {
5372 // X86-64 va_list is a struct { i32, i32, i8*, i8* }.
5373 assert(Subtarget->is64Bit() && "This code only handles 64-bit va_copy!");
5374 SDValue Chain = Op.getOperand(0);
5375 SDValue DstPtr = Op.getOperand(1);
5376 SDValue SrcPtr = Op.getOperand(2);
5377 const Value *DstSV = cast<SrcValueSDNode>(Op.getOperand(3))->getValue();
5378 const Value *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
5380 return DAG.getMemcpy(Chain, DstPtr, SrcPtr,
5381 DAG.getIntPtrConstant(24), 8, false,
5382 DstSV, 0, SrcSV, 0);
5386 X86TargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) {
5387 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
5389 default: return SDValue(); // Don't custom lower most intrinsics.
5390 // Comparison intrinsics.
5391 case Intrinsic::x86_sse_comieq_ss:
5392 case Intrinsic::x86_sse_comilt_ss:
5393 case Intrinsic::x86_sse_comile_ss:
5394 case Intrinsic::x86_sse_comigt_ss:
5395 case Intrinsic::x86_sse_comige_ss:
5396 case Intrinsic::x86_sse_comineq_ss:
5397 case Intrinsic::x86_sse_ucomieq_ss:
5398 case Intrinsic::x86_sse_ucomilt_ss:
5399 case Intrinsic::x86_sse_ucomile_ss:
5400 case Intrinsic::x86_sse_ucomigt_ss:
5401 case Intrinsic::x86_sse_ucomige_ss:
5402 case Intrinsic::x86_sse_ucomineq_ss:
5403 case Intrinsic::x86_sse2_comieq_sd:
5404 case Intrinsic::x86_sse2_comilt_sd:
5405 case Intrinsic::x86_sse2_comile_sd:
5406 case Intrinsic::x86_sse2_comigt_sd:
5407 case Intrinsic::x86_sse2_comige_sd:
5408 case Intrinsic::x86_sse2_comineq_sd:
5409 case Intrinsic::x86_sse2_ucomieq_sd:
5410 case Intrinsic::x86_sse2_ucomilt_sd:
5411 case Intrinsic::x86_sse2_ucomile_sd:
5412 case Intrinsic::x86_sse2_ucomigt_sd:
5413 case Intrinsic::x86_sse2_ucomige_sd:
5414 case Intrinsic::x86_sse2_ucomineq_sd: {
5416 ISD::CondCode CC = ISD::SETCC_INVALID;
5419 case Intrinsic::x86_sse_comieq_ss:
5420 case Intrinsic::x86_sse2_comieq_sd:
5424 case Intrinsic::x86_sse_comilt_ss:
5425 case Intrinsic::x86_sse2_comilt_sd:
5429 case Intrinsic::x86_sse_comile_ss:
5430 case Intrinsic::x86_sse2_comile_sd:
5434 case Intrinsic::x86_sse_comigt_ss:
5435 case Intrinsic::x86_sse2_comigt_sd:
5439 case Intrinsic::x86_sse_comige_ss:
5440 case Intrinsic::x86_sse2_comige_sd:
5444 case Intrinsic::x86_sse_comineq_ss:
5445 case Intrinsic::x86_sse2_comineq_sd:
5449 case Intrinsic::x86_sse_ucomieq_ss:
5450 case Intrinsic::x86_sse2_ucomieq_sd:
5451 Opc = X86ISD::UCOMI;
5454 case Intrinsic::x86_sse_ucomilt_ss:
5455 case Intrinsic::x86_sse2_ucomilt_sd:
5456 Opc = X86ISD::UCOMI;
5459 case Intrinsic::x86_sse_ucomile_ss:
5460 case Intrinsic::x86_sse2_ucomile_sd:
5461 Opc = X86ISD::UCOMI;
5464 case Intrinsic::x86_sse_ucomigt_ss:
5465 case Intrinsic::x86_sse2_ucomigt_sd:
5466 Opc = X86ISD::UCOMI;
5469 case Intrinsic::x86_sse_ucomige_ss:
5470 case Intrinsic::x86_sse2_ucomige_sd:
5471 Opc = X86ISD::UCOMI;
5474 case Intrinsic::x86_sse_ucomineq_ss:
5475 case Intrinsic::x86_sse2_ucomineq_sd:
5476 Opc = X86ISD::UCOMI;
5482 SDValue LHS = Op.getOperand(1);
5483 SDValue RHS = Op.getOperand(2);
5484 translateX86CC(CC, true, X86CC, LHS, RHS, DAG);
5486 SDValue Cond = DAG.getNode(Opc, MVT::i32, LHS, RHS);
5487 SDValue SetCC = DAG.getNode(X86ISD::SETCC, MVT::i8,
5488 DAG.getConstant(X86CC, MVT::i8), Cond);
5489 return DAG.getNode(ISD::ZERO_EXTEND, MVT::i32, SetCC);
5492 // Fix vector shift instructions where the last operand is a non-immediate
5494 case Intrinsic::x86_sse2_pslli_w:
5495 case Intrinsic::x86_sse2_pslli_d:
5496 case Intrinsic::x86_sse2_pslli_q:
5497 case Intrinsic::x86_sse2_psrli_w:
5498 case Intrinsic::x86_sse2_psrli_d:
5499 case Intrinsic::x86_sse2_psrli_q:
5500 case Intrinsic::x86_sse2_psrai_w:
5501 case Intrinsic::x86_sse2_psrai_d:
5502 case Intrinsic::x86_mmx_pslli_w:
5503 case Intrinsic::x86_mmx_pslli_d:
5504 case Intrinsic::x86_mmx_pslli_q:
5505 case Intrinsic::x86_mmx_psrli_w:
5506 case Intrinsic::x86_mmx_psrli_d:
5507 case Intrinsic::x86_mmx_psrli_q:
5508 case Intrinsic::x86_mmx_psrai_w:
5509 case Intrinsic::x86_mmx_psrai_d: {
5510 SDValue ShAmt = Op.getOperand(2);
5511 if (isa<ConstantSDNode>(ShAmt))
5514 unsigned NewIntNo = 0;
5515 MVT ShAmtVT = MVT::v4i32;
5517 case Intrinsic::x86_sse2_pslli_w:
5518 NewIntNo = Intrinsic::x86_sse2_psll_w;
5520 case Intrinsic::x86_sse2_pslli_d:
5521 NewIntNo = Intrinsic::x86_sse2_psll_d;
5523 case Intrinsic::x86_sse2_pslli_q:
5524 NewIntNo = Intrinsic::x86_sse2_psll_q;
5526 case Intrinsic::x86_sse2_psrli_w:
5527 NewIntNo = Intrinsic::x86_sse2_psrl_w;
5529 case Intrinsic::x86_sse2_psrli_d:
5530 NewIntNo = Intrinsic::x86_sse2_psrl_d;
5532 case Intrinsic::x86_sse2_psrli_q:
5533 NewIntNo = Intrinsic::x86_sse2_psrl_q;
5535 case Intrinsic::x86_sse2_psrai_w:
5536 NewIntNo = Intrinsic::x86_sse2_psra_w;
5538 case Intrinsic::x86_sse2_psrai_d:
5539 NewIntNo = Intrinsic::x86_sse2_psra_d;
5542 ShAmtVT = MVT::v2i32;
5544 case Intrinsic::x86_mmx_pslli_w:
5545 NewIntNo = Intrinsic::x86_mmx_psll_w;
5547 case Intrinsic::x86_mmx_pslli_d:
5548 NewIntNo = Intrinsic::x86_mmx_psll_d;
5550 case Intrinsic::x86_mmx_pslli_q:
5551 NewIntNo = Intrinsic::x86_mmx_psll_q;
5553 case Intrinsic::x86_mmx_psrli_w:
5554 NewIntNo = Intrinsic::x86_mmx_psrl_w;
5556 case Intrinsic::x86_mmx_psrli_d:
5557 NewIntNo = Intrinsic::x86_mmx_psrl_d;
5559 case Intrinsic::x86_mmx_psrli_q:
5560 NewIntNo = Intrinsic::x86_mmx_psrl_q;
5562 case Intrinsic::x86_mmx_psrai_w:
5563 NewIntNo = Intrinsic::x86_mmx_psra_w;
5565 case Intrinsic::x86_mmx_psrai_d:
5566 NewIntNo = Intrinsic::x86_mmx_psra_d;
5568 default: abort(); // Can't reach here.
5573 MVT VT = Op.getValueType();
5574 ShAmt = DAG.getNode(ISD::BIT_CONVERT, VT,
5575 DAG.getNode(ISD::SCALAR_TO_VECTOR, ShAmtVT, ShAmt));
5576 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, VT,
5577 DAG.getConstant(NewIntNo, MVT::i32),
5578 Op.getOperand(1), ShAmt);
5583 SDValue X86TargetLowering::LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) {
5584 // Depths > 0 not supported yet!
5585 if (cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue() > 0)
5588 // Just load the return address
5589 SDValue RetAddrFI = getReturnAddressFrameIndex(DAG);
5590 return DAG.getLoad(getPointerTy(), DAG.getEntryNode(), RetAddrFI, NULL, 0);
5593 SDValue X86TargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) {
5594 // Depths > 0 not supported yet!
5595 if (cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue() > 0)
5598 SDValue RetAddrFI = getReturnAddressFrameIndex(DAG);
5599 return DAG.getNode(ISD::SUB, getPointerTy(), RetAddrFI,
5600 DAG.getIntPtrConstant(TD->getPointerSize()));
5603 SDValue X86TargetLowering::LowerFRAME_TO_ARGS_OFFSET(SDValue Op,
5604 SelectionDAG &DAG) {
5605 return DAG.getIntPtrConstant(2*TD->getPointerSize());
5608 SDValue X86TargetLowering::LowerEH_RETURN(SDValue Op, SelectionDAG &DAG)
5610 MachineFunction &MF = DAG.getMachineFunction();
5611 SDValue Chain = Op.getOperand(0);
5612 SDValue Offset = Op.getOperand(1);
5613 SDValue Handler = Op.getOperand(2);
5615 SDValue Frame = DAG.getRegister(Subtarget->is64Bit() ? X86::RBP : X86::EBP,
5617 unsigned StoreAddrReg = (Subtarget->is64Bit() ? X86::RCX : X86::ECX);
5619 SDValue StoreAddr = DAG.getNode(ISD::SUB, getPointerTy(), Frame,
5620 DAG.getIntPtrConstant(-TD->getPointerSize()));
5621 StoreAddr = DAG.getNode(ISD::ADD, getPointerTy(), StoreAddr, Offset);
5622 Chain = DAG.getStore(Chain, Handler, StoreAddr, NULL, 0);
5623 Chain = DAG.getCopyToReg(Chain, StoreAddrReg, StoreAddr);
5624 MF.getRegInfo().addLiveOut(StoreAddrReg);
5626 return DAG.getNode(X86ISD::EH_RETURN,
5628 Chain, DAG.getRegister(StoreAddrReg, getPointerTy()));
5631 SDValue X86TargetLowering::LowerTRAMPOLINE(SDValue Op,
5632 SelectionDAG &DAG) {
5633 SDValue Root = Op.getOperand(0);
5634 SDValue Trmp = Op.getOperand(1); // trampoline
5635 SDValue FPtr = Op.getOperand(2); // nested function
5636 SDValue Nest = Op.getOperand(3); // 'nest' parameter value
5638 const Value *TrmpAddr = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
5640 const X86InstrInfo *TII =
5641 ((X86TargetMachine&)getTargetMachine()).getInstrInfo();
5643 if (Subtarget->is64Bit()) {
5644 SDValue OutChains[6];
5646 // Large code-model.
5648 const unsigned char JMP64r = TII->getBaseOpcodeFor(X86::JMP64r);
5649 const unsigned char MOV64ri = TII->getBaseOpcodeFor(X86::MOV64ri);
5651 const unsigned char N86R10 = RegInfo->getX86RegNum(X86::R10);
5652 const unsigned char N86R11 = RegInfo->getX86RegNum(X86::R11);
5654 const unsigned char REX_WB = 0x40 | 0x08 | 0x01; // REX prefix
5656 // Load the pointer to the nested function into R11.
5657 unsigned OpCode = ((MOV64ri | N86R11) << 8) | REX_WB; // movabsq r11
5658 SDValue Addr = Trmp;
5659 OutChains[0] = DAG.getStore(Root, DAG.getConstant(OpCode, MVT::i16), Addr,
5662 Addr = DAG.getNode(ISD::ADD, MVT::i64, Trmp, DAG.getConstant(2, MVT::i64));
5663 OutChains[1] = DAG.getStore(Root, FPtr, Addr, TrmpAddr, 2, false, 2);
5665 // Load the 'nest' parameter value into R10.
5666 // R10 is specified in X86CallingConv.td
5667 OpCode = ((MOV64ri | N86R10) << 8) | REX_WB; // movabsq r10
5668 Addr = DAG.getNode(ISD::ADD, MVT::i64, Trmp, DAG.getConstant(10, MVT::i64));
5669 OutChains[2] = DAG.getStore(Root, DAG.getConstant(OpCode, MVT::i16), Addr,
5672 Addr = DAG.getNode(ISD::ADD, MVT::i64, Trmp, DAG.getConstant(12, MVT::i64));
5673 OutChains[3] = DAG.getStore(Root, Nest, Addr, TrmpAddr, 12, false, 2);
5675 // Jump to the nested function.
5676 OpCode = (JMP64r << 8) | REX_WB; // jmpq *...
5677 Addr = DAG.getNode(ISD::ADD, MVT::i64, Trmp, DAG.getConstant(20, MVT::i64));
5678 OutChains[4] = DAG.getStore(Root, DAG.getConstant(OpCode, MVT::i16), Addr,
5681 unsigned char ModRM = N86R11 | (4 << 3) | (3 << 6); // ...r11
5682 Addr = DAG.getNode(ISD::ADD, MVT::i64, Trmp, DAG.getConstant(22, MVT::i64));
5683 OutChains[5] = DAG.getStore(Root, DAG.getConstant(ModRM, MVT::i8), Addr,
5687 { Trmp, DAG.getNode(ISD::TokenFactor, MVT::Other, OutChains, 6) };
5688 return DAG.getMergeValues(Ops, 2);
5690 const Function *Func =
5691 cast<Function>(cast<SrcValueSDNode>(Op.getOperand(5))->getValue());
5692 unsigned CC = Func->getCallingConv();
5697 assert(0 && "Unsupported calling convention");
5698 case CallingConv::C:
5699 case CallingConv::X86_StdCall: {
5700 // Pass 'nest' parameter in ECX.
5701 // Must be kept in sync with X86CallingConv.td
5704 // Check that ECX wasn't needed by an 'inreg' parameter.
5705 const FunctionType *FTy = Func->getFunctionType();
5706 const PAListPtr &Attrs = Func->getParamAttrs();
5708 if (!Attrs.isEmpty() && !Func->isVarArg()) {
5709 unsigned InRegCount = 0;
5712 for (FunctionType::param_iterator I = FTy->param_begin(),
5713 E = FTy->param_end(); I != E; ++I, ++Idx)
5714 if (Attrs.paramHasAttr(Idx, ParamAttr::InReg))
5715 // FIXME: should only count parameters that are lowered to integers.
5716 InRegCount += (TD->getTypeSizeInBits(*I) + 31) / 32;
5718 if (InRegCount > 2) {
5719 cerr << "Nest register in use - reduce number of inreg parameters!\n";
5725 case CallingConv::X86_FastCall:
5726 case CallingConv::Fast:
5727 // Pass 'nest' parameter in EAX.
5728 // Must be kept in sync with X86CallingConv.td
5733 SDValue OutChains[4];
5736 Addr = DAG.getNode(ISD::ADD, MVT::i32, Trmp, DAG.getConstant(10, MVT::i32));
5737 Disp = DAG.getNode(ISD::SUB, MVT::i32, FPtr, Addr);
5739 const unsigned char MOV32ri = TII->getBaseOpcodeFor(X86::MOV32ri);
5740 const unsigned char N86Reg = RegInfo->getX86RegNum(NestReg);
5741 OutChains[0] = DAG.getStore(Root, DAG.getConstant(MOV32ri|N86Reg, MVT::i8),
5744 Addr = DAG.getNode(ISD::ADD, MVT::i32, Trmp, DAG.getConstant(1, MVT::i32));
5745 OutChains[1] = DAG.getStore(Root, Nest, Addr, TrmpAddr, 1, false, 1);
5747 const unsigned char JMP = TII->getBaseOpcodeFor(X86::JMP);
5748 Addr = DAG.getNode(ISD::ADD, MVT::i32, Trmp, DAG.getConstant(5, MVT::i32));
5749 OutChains[2] = DAG.getStore(Root, DAG.getConstant(JMP, MVT::i8), Addr,
5750 TrmpAddr, 5, false, 1);
5752 Addr = DAG.getNode(ISD::ADD, MVT::i32, Trmp, DAG.getConstant(6, MVT::i32));
5753 OutChains[3] = DAG.getStore(Root, Disp, Addr, TrmpAddr, 6, false, 1);
5756 { Trmp, DAG.getNode(ISD::TokenFactor, MVT::Other, OutChains, 4) };
5757 return DAG.getMergeValues(Ops, 2);
5761 SDValue X86TargetLowering::LowerFLT_ROUNDS_(SDValue Op, SelectionDAG &DAG) {
5763 The rounding mode is in bits 11:10 of FPSR, and has the following
5770 FLT_ROUNDS, on the other hand, expects the following:
5777 To perform the conversion, we do:
5778 (((((FPSR & 0x800) >> 11) | ((FPSR & 0x400) >> 9)) + 1) & 3)
5781 MachineFunction &MF = DAG.getMachineFunction();
5782 const TargetMachine &TM = MF.getTarget();
5783 const TargetFrameInfo &TFI = *TM.getFrameInfo();
5784 unsigned StackAlignment = TFI.getStackAlignment();
5785 MVT VT = Op.getValueType();
5787 // Save FP Control Word to stack slot
5788 int SSFI = MF.getFrameInfo()->CreateStackObject(2, StackAlignment);
5789 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
5791 SDValue Chain = DAG.getNode(X86ISD::FNSTCW16m, MVT::Other,
5792 DAG.getEntryNode(), StackSlot);
5794 // Load FP Control Word from stack slot
5795 SDValue CWD = DAG.getLoad(MVT::i16, Chain, StackSlot, NULL, 0);
5797 // Transform as necessary
5799 DAG.getNode(ISD::SRL, MVT::i16,
5800 DAG.getNode(ISD::AND, MVT::i16,
5801 CWD, DAG.getConstant(0x800, MVT::i16)),
5802 DAG.getConstant(11, MVT::i8));
5804 DAG.getNode(ISD::SRL, MVT::i16,
5805 DAG.getNode(ISD::AND, MVT::i16,
5806 CWD, DAG.getConstant(0x400, MVT::i16)),
5807 DAG.getConstant(9, MVT::i8));
5810 DAG.getNode(ISD::AND, MVT::i16,
5811 DAG.getNode(ISD::ADD, MVT::i16,
5812 DAG.getNode(ISD::OR, MVT::i16, CWD1, CWD2),
5813 DAG.getConstant(1, MVT::i16)),
5814 DAG.getConstant(3, MVT::i16));
5817 return DAG.getNode((VT.getSizeInBits() < 16 ?
5818 ISD::TRUNCATE : ISD::ZERO_EXTEND), VT, RetVal);
5821 SDValue X86TargetLowering::LowerCTLZ(SDValue Op, SelectionDAG &DAG) {
5822 MVT VT = Op.getValueType();
5824 unsigned NumBits = VT.getSizeInBits();
5826 Op = Op.getOperand(0);
5827 if (VT == MVT::i8) {
5828 // Zero extend to i32 since there is not an i8 bsr.
5830 Op = DAG.getNode(ISD::ZERO_EXTEND, OpVT, Op);
5833 // Issue a bsr (scan bits in reverse) which also sets EFLAGS.
5834 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
5835 Op = DAG.getNode(X86ISD::BSR, VTs, Op);
5837 // If src is zero (i.e. bsr sets ZF), returns NumBits.
5838 SmallVector<SDValue, 4> Ops;
5840 Ops.push_back(DAG.getConstant(NumBits+NumBits-1, OpVT));
5841 Ops.push_back(DAG.getConstant(X86::COND_E, MVT::i8));
5842 Ops.push_back(Op.getValue(1));
5843 Op = DAG.getNode(X86ISD::CMOV, OpVT, &Ops[0], 4);
5845 // Finally xor with NumBits-1.
5846 Op = DAG.getNode(ISD::XOR, OpVT, Op, DAG.getConstant(NumBits-1, OpVT));
5849 Op = DAG.getNode(ISD::TRUNCATE, MVT::i8, Op);
5853 SDValue X86TargetLowering::LowerCTTZ(SDValue Op, SelectionDAG &DAG) {
5854 MVT VT = Op.getValueType();
5856 unsigned NumBits = VT.getSizeInBits();
5858 Op = Op.getOperand(0);
5859 if (VT == MVT::i8) {
5861 Op = DAG.getNode(ISD::ZERO_EXTEND, OpVT, Op);
5864 // Issue a bsf (scan bits forward) which also sets EFLAGS.
5865 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
5866 Op = DAG.getNode(X86ISD::BSF, VTs, Op);
5868 // If src is zero (i.e. bsf sets ZF), returns NumBits.
5869 SmallVector<SDValue, 4> Ops;
5871 Ops.push_back(DAG.getConstant(NumBits, OpVT));
5872 Ops.push_back(DAG.getConstant(X86::COND_E, MVT::i8));
5873 Ops.push_back(Op.getValue(1));
5874 Op = DAG.getNode(X86ISD::CMOV, OpVT, &Ops[0], 4);
5877 Op = DAG.getNode(ISD::TRUNCATE, MVT::i8, Op);
5881 SDValue X86TargetLowering::LowerCMP_SWAP(SDValue Op, SelectionDAG &DAG) {
5882 MVT T = Op.getValueType();
5885 switch(T.getSimpleVT()) {
5887 assert(false && "Invalid value type!");
5888 case MVT::i8: Reg = X86::AL; size = 1; break;
5889 case MVT::i16: Reg = X86::AX; size = 2; break;
5890 case MVT::i32: Reg = X86::EAX; size = 4; break;
5892 if (Subtarget->is64Bit()) {
5893 Reg = X86::RAX; size = 8;
5894 } else //Should go away when LowerType stuff lands
5895 return SDValue(ExpandATOMIC_CMP_SWAP(Op.getNode(), DAG), 0);
5898 SDValue cpIn = DAG.getCopyToReg(Op.getOperand(0), Reg,
5899 Op.getOperand(2), SDValue());
5900 SDValue Ops[] = { cpIn.getValue(0),
5903 DAG.getTargetConstant(size, MVT::i8),
5905 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
5906 SDValue Result = DAG.getNode(X86ISD::LCMPXCHG_DAG, Tys, Ops, 5);
5908 DAG.getCopyFromReg(Result.getValue(0), Reg, T, Result.getValue(1));
5912 SDNode* X86TargetLowering::ExpandATOMIC_CMP_SWAP(SDNode* Op,
5913 SelectionDAG &DAG) {
5914 MVT T = Op->getValueType(0);
5915 assert (T == MVT::i64 && "Only know how to expand i64 Cmp and Swap");
5916 SDValue cpInL, cpInH;
5917 cpInL = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op->getOperand(2),
5918 DAG.getConstant(0, MVT::i32));
5919 cpInH = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op->getOperand(2),
5920 DAG.getConstant(1, MVT::i32));
5921 cpInL = DAG.getCopyToReg(Op->getOperand(0), X86::EAX,
5923 cpInH = DAG.getCopyToReg(cpInL.getValue(0), X86::EDX,
5924 cpInH, cpInL.getValue(1));
5925 SDValue swapInL, swapInH;
5926 swapInL = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op->getOperand(3),
5927 DAG.getConstant(0, MVT::i32));
5928 swapInH = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op->getOperand(3),
5929 DAG.getConstant(1, MVT::i32));
5930 swapInL = DAG.getCopyToReg(cpInH.getValue(0), X86::EBX,
5931 swapInL, cpInH.getValue(1));
5932 swapInH = DAG.getCopyToReg(swapInL.getValue(0), X86::ECX,
5933 swapInH, swapInL.getValue(1));
5934 SDValue Ops[] = { swapInH.getValue(0),
5936 swapInH.getValue(1)};
5937 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
5938 SDValue Result = DAG.getNode(X86ISD::LCMPXCHG8_DAG, Tys, Ops, 3);
5939 SDValue cpOutL = DAG.getCopyFromReg(Result.getValue(0), X86::EAX, MVT::i32,
5940 Result.getValue(1));
5941 SDValue cpOutH = DAG.getCopyFromReg(cpOutL.getValue(1), X86::EDX, MVT::i32,
5942 cpOutL.getValue(2));
5943 SDValue OpsF[] = { cpOutL.getValue(0), cpOutH.getValue(0)};
5944 SDValue ResultVal = DAG.getNode(ISD::BUILD_PAIR, MVT::i64, OpsF, 2);
5945 SDValue Vals[2] = { ResultVal, cpOutH.getValue(1) };
5946 return DAG.getMergeValues(Vals, 2).getNode();
5949 SDNode* X86TargetLowering::ExpandATOMIC_LOAD_SUB(SDNode* Op,
5950 SelectionDAG &DAG) {
5951 MVT T = Op->getValueType(0);
5952 SDValue negOp = DAG.getNode(ISD::SUB, T,
5953 DAG.getConstant(0, T), Op->getOperand(2));
5954 return DAG.getAtomic((T==MVT::i8 ? ISD::ATOMIC_LOAD_ADD_8:
5955 T==MVT::i16 ? ISD::ATOMIC_LOAD_ADD_16:
5956 T==MVT::i32 ? ISD::ATOMIC_LOAD_ADD_32:
5957 T==MVT::i64 ? ISD::ATOMIC_LOAD_ADD_64: 0),
5958 Op->getOperand(0), Op->getOperand(1), negOp,
5959 cast<AtomicSDNode>(Op)->getSrcValue(),
5960 cast<AtomicSDNode>(Op)->getAlignment()).getNode();
5963 /// LowerOperation - Provide custom lowering hooks for some operations.
5965 SDValue X86TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) {
5966 switch (Op.getOpcode()) {
5967 default: assert(0 && "Should not custom lower this!");
5968 case ISD::ATOMIC_CMP_SWAP_8: return LowerCMP_SWAP(Op,DAG);
5969 case ISD::ATOMIC_CMP_SWAP_16: return LowerCMP_SWAP(Op,DAG);
5970 case ISD::ATOMIC_CMP_SWAP_32: return LowerCMP_SWAP(Op,DAG);
5971 case ISD::ATOMIC_CMP_SWAP_64: return LowerCMP_SWAP(Op,DAG);
5972 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
5973 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
5974 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
5975 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG);
5976 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
5977 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
5978 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
5979 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
5980 case ISD::ExternalSymbol: return LowerExternalSymbol(Op, DAG);
5981 case ISD::SHL_PARTS:
5982 case ISD::SRA_PARTS:
5983 case ISD::SRL_PARTS: return LowerShift(Op, DAG);
5984 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG);
5985 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG);
5986 case ISD::FABS: return LowerFABS(Op, DAG);
5987 case ISD::FNEG: return LowerFNEG(Op, DAG);
5988 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG);
5989 case ISD::SETCC: return LowerSETCC(Op, DAG);
5990 case ISD::VSETCC: return LowerVSETCC(Op, DAG);
5991 case ISD::SELECT: return LowerSELECT(Op, DAG);
5992 case ISD::BRCOND: return LowerBRCOND(Op, DAG);
5993 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
5994 case ISD::CALL: return LowerCALL(Op, DAG);
5995 case ISD::RET: return LowerRET(Op, DAG);
5996 case ISD::FORMAL_ARGUMENTS: return LowerFORMAL_ARGUMENTS(Op, DAG);
5997 case ISD::VASTART: return LowerVASTART(Op, DAG);
5998 case ISD::VAARG: return LowerVAARG(Op, DAG);
5999 case ISD::VACOPY: return LowerVACOPY(Op, DAG);
6000 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
6001 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
6002 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
6003 case ISD::FRAME_TO_ARGS_OFFSET:
6004 return LowerFRAME_TO_ARGS_OFFSET(Op, DAG);
6005 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
6006 case ISD::EH_RETURN: return LowerEH_RETURN(Op, DAG);
6007 case ISD::TRAMPOLINE: return LowerTRAMPOLINE(Op, DAG);
6008 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
6009 case ISD::CTLZ: return LowerCTLZ(Op, DAG);
6010 case ISD::CTTZ: return LowerCTTZ(Op, DAG);
6012 // FIXME: REMOVE THIS WHEN LegalizeDAGTypes lands.
6013 case ISD::READCYCLECOUNTER:
6014 return SDValue(ExpandREADCYCLECOUNTER(Op.getNode(), DAG), 0);
6018 /// ReplaceNodeResults - Replace a node with an illegal result type
6019 /// with a new node built out of custom code.
6020 SDNode *X86TargetLowering::ReplaceNodeResults(SDNode *N, SelectionDAG &DAG) {
6021 switch (N->getOpcode()) {
6022 default: assert(0 && "Should not custom lower this!");
6023 case ISD::FP_TO_SINT: return ExpandFP_TO_SINT(N, DAG);
6024 case ISD::READCYCLECOUNTER: return ExpandREADCYCLECOUNTER(N, DAG);
6025 case ISD::ATOMIC_CMP_SWAP_64: return ExpandATOMIC_CMP_SWAP(N, DAG);
6026 case ISD::ATOMIC_LOAD_SUB_8: return ExpandATOMIC_LOAD_SUB(N,DAG);
6027 case ISD::ATOMIC_LOAD_SUB_16: return ExpandATOMIC_LOAD_SUB(N,DAG);
6028 case ISD::ATOMIC_LOAD_SUB_32: return ExpandATOMIC_LOAD_SUB(N,DAG);
6029 case ISD::ATOMIC_LOAD_SUB_64: return ExpandATOMIC_LOAD_SUB(N,DAG);
6033 const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
6035 default: return NULL;
6036 case X86ISD::BSF: return "X86ISD::BSF";
6037 case X86ISD::BSR: return "X86ISD::BSR";
6038 case X86ISD::SHLD: return "X86ISD::SHLD";
6039 case X86ISD::SHRD: return "X86ISD::SHRD";
6040 case X86ISD::FAND: return "X86ISD::FAND";
6041 case X86ISD::FOR: return "X86ISD::FOR";
6042 case X86ISD::FXOR: return "X86ISD::FXOR";
6043 case X86ISD::FSRL: return "X86ISD::FSRL";
6044 case X86ISD::FILD: return "X86ISD::FILD";
6045 case X86ISD::FILD_FLAG: return "X86ISD::FILD_FLAG";
6046 case X86ISD::FP_TO_INT16_IN_MEM: return "X86ISD::FP_TO_INT16_IN_MEM";
6047 case X86ISD::FP_TO_INT32_IN_MEM: return "X86ISD::FP_TO_INT32_IN_MEM";
6048 case X86ISD::FP_TO_INT64_IN_MEM: return "X86ISD::FP_TO_INT64_IN_MEM";
6049 case X86ISD::FLD: return "X86ISD::FLD";
6050 case X86ISD::FST: return "X86ISD::FST";
6051 case X86ISD::CALL: return "X86ISD::CALL";
6052 case X86ISD::TAILCALL: return "X86ISD::TAILCALL";
6053 case X86ISD::RDTSC_DAG: return "X86ISD::RDTSC_DAG";
6054 case X86ISD::CMP: return "X86ISD::CMP";
6055 case X86ISD::COMI: return "X86ISD::COMI";
6056 case X86ISD::UCOMI: return "X86ISD::UCOMI";
6057 case X86ISD::SETCC: return "X86ISD::SETCC";
6058 case X86ISD::CMOV: return "X86ISD::CMOV";
6059 case X86ISD::BRCOND: return "X86ISD::BRCOND";
6060 case X86ISD::RET_FLAG: return "X86ISD::RET_FLAG";
6061 case X86ISD::REP_STOS: return "X86ISD::REP_STOS";
6062 case X86ISD::REP_MOVS: return "X86ISD::REP_MOVS";
6063 case X86ISD::GlobalBaseReg: return "X86ISD::GlobalBaseReg";
6064 case X86ISD::Wrapper: return "X86ISD::Wrapper";
6065 case X86ISD::PEXTRB: return "X86ISD::PEXTRB";
6066 case X86ISD::PEXTRW: return "X86ISD::PEXTRW";
6067 case X86ISD::INSERTPS: return "X86ISD::INSERTPS";
6068 case X86ISD::PINSRB: return "X86ISD::PINSRB";
6069 case X86ISD::PINSRW: return "X86ISD::PINSRW";
6070 case X86ISD::FMAX: return "X86ISD::FMAX";
6071 case X86ISD::FMIN: return "X86ISD::FMIN";
6072 case X86ISD::FRSQRT: return "X86ISD::FRSQRT";
6073 case X86ISD::FRCP: return "X86ISD::FRCP";
6074 case X86ISD::TLSADDR: return "X86ISD::TLSADDR";
6075 case X86ISD::THREAD_POINTER: return "X86ISD::THREAD_POINTER";
6076 case X86ISD::EH_RETURN: return "X86ISD::EH_RETURN";
6077 case X86ISD::TC_RETURN: return "X86ISD::TC_RETURN";
6078 case X86ISD::FNSTCW16m: return "X86ISD::FNSTCW16m";
6079 case X86ISD::LCMPXCHG_DAG: return "X86ISD::LCMPXCHG_DAG";
6080 case X86ISD::LCMPXCHG8_DAG: return "X86ISD::LCMPXCHG8_DAG";
6081 case X86ISD::VZEXT_MOVL: return "X86ISD::VZEXT_MOVL";
6082 case X86ISD::VZEXT_LOAD: return "X86ISD::VZEXT_LOAD";
6083 case X86ISD::VSHL: return "X86ISD::VSHL";
6084 case X86ISD::VSRL: return "X86ISD::VSRL";
6085 case X86ISD::CMPPD: return "X86ISD::CMPPD";
6086 case X86ISD::CMPPS: return "X86ISD::CMPPS";
6087 case X86ISD::PCMPEQB: return "X86ISD::PCMPEQB";
6088 case X86ISD::PCMPEQW: return "X86ISD::PCMPEQW";
6089 case X86ISD::PCMPEQD: return "X86ISD::PCMPEQD";
6090 case X86ISD::PCMPEQQ: return "X86ISD::PCMPEQQ";
6091 case X86ISD::PCMPGTB: return "X86ISD::PCMPGTB";
6092 case X86ISD::PCMPGTW: return "X86ISD::PCMPGTW";
6093 case X86ISD::PCMPGTD: return "X86ISD::PCMPGTD";
6094 case X86ISD::PCMPGTQ: return "X86ISD::PCMPGTQ";
6098 // isLegalAddressingMode - Return true if the addressing mode represented
6099 // by AM is legal for this target, for a load/store of the specified type.
6100 bool X86TargetLowering::isLegalAddressingMode(const AddrMode &AM,
6101 const Type *Ty) const {
6102 // X86 supports extremely general addressing modes.
6104 // X86 allows a sign-extended 32-bit immediate field as a displacement.
6105 if (AM.BaseOffs <= -(1LL << 32) || AM.BaseOffs >= (1LL << 32)-1)
6109 // We can only fold this if we don't need an extra load.
6110 if (Subtarget->GVRequiresExtraLoad(AM.BaseGV, getTargetMachine(), false))
6113 // X86-64 only supports addr of globals in small code model.
6114 if (Subtarget->is64Bit()) {
6115 if (getTargetMachine().getCodeModel() != CodeModel::Small)
6117 // If lower 4G is not available, then we must use rip-relative addressing.
6118 if (AM.BaseOffs || AM.Scale > 1)
6129 // These scales always work.
6134 // These scales are formed with basereg+scalereg. Only accept if there is
6139 default: // Other stuff never works.
6147 bool X86TargetLowering::isTruncateFree(const Type *Ty1, const Type *Ty2) const {
6148 if (!Ty1->isInteger() || !Ty2->isInteger())
6150 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits();
6151 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits();
6152 if (NumBits1 <= NumBits2)
6154 return Subtarget->is64Bit() || NumBits1 < 64;
6157 bool X86TargetLowering::isTruncateFree(MVT VT1, MVT VT2) const {
6158 if (!VT1.isInteger() || !VT2.isInteger())
6160 unsigned NumBits1 = VT1.getSizeInBits();
6161 unsigned NumBits2 = VT2.getSizeInBits();
6162 if (NumBits1 <= NumBits2)
6164 return Subtarget->is64Bit() || NumBits1 < 64;
6167 /// isShuffleMaskLegal - Targets can use this to indicate that they only
6168 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
6169 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
6170 /// are assumed to be legal.
6172 X86TargetLowering::isShuffleMaskLegal(SDValue Mask, MVT VT) const {
6173 // Only do shuffles on 128-bit vector types for now.
6174 if (VT.getSizeInBits() == 64) return false;
6175 return (Mask.getNode()->getNumOperands() <= 4 ||
6176 isIdentityMask(Mask.getNode()) ||
6177 isIdentityMask(Mask.getNode(), true) ||
6178 isSplatMask(Mask.getNode()) ||
6179 isPSHUFHW_PSHUFLWMask(Mask.getNode()) ||
6180 X86::isUNPCKLMask(Mask.getNode()) ||
6181 X86::isUNPCKHMask(Mask.getNode()) ||
6182 X86::isUNPCKL_v_undef_Mask(Mask.getNode()) ||
6183 X86::isUNPCKH_v_undef_Mask(Mask.getNode()));
6187 X86TargetLowering::isVectorClearMaskLegal(const std::vector<SDValue> &BVOps,
6188 MVT EVT, SelectionDAG &DAG) const {
6189 unsigned NumElts = BVOps.size();
6190 // Only do shuffles on 128-bit vector types for now.
6191 if (EVT.getSizeInBits() * NumElts == 64) return false;
6192 if (NumElts == 2) return true;
6194 return (isMOVLMask(&BVOps[0], 4) ||
6195 isCommutedMOVL(&BVOps[0], 4, true) ||
6196 isSHUFPMask(&BVOps[0], 4) ||
6197 isCommutedSHUFP(&BVOps[0], 4));
6202 //===----------------------------------------------------------------------===//
6203 // X86 Scheduler Hooks
6204 //===----------------------------------------------------------------------===//
6206 // private utility function
6208 X86TargetLowering::EmitAtomicBitwiseWithCustomInserter(MachineInstr *bInstr,
6209 MachineBasicBlock *MBB,
6217 TargetRegisterClass *RC,
6219 // For the atomic bitwise operator, we generate
6222 // ld t1 = [bitinstr.addr]
6223 // op t2 = t1, [bitinstr.val]
6225 // lcs dest = [bitinstr.addr], t2 [EAX is implicit]
6227 // fallthrough -->nextMBB
6228 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
6229 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
6230 MachineFunction::iterator MBBIter = MBB;
6233 /// First build the CFG
6234 MachineFunction *F = MBB->getParent();
6235 MachineBasicBlock *thisMBB = MBB;
6236 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB);
6237 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB);
6238 F->insert(MBBIter, newMBB);
6239 F->insert(MBBIter, nextMBB);
6241 // Move all successors to thisMBB to nextMBB
6242 nextMBB->transferSuccessors(thisMBB);
6244 // Update thisMBB to fall through to newMBB
6245 thisMBB->addSuccessor(newMBB);
6247 // newMBB jumps to itself and fall through to nextMBB
6248 newMBB->addSuccessor(nextMBB);
6249 newMBB->addSuccessor(newMBB);
6251 // Insert instructions into newMBB based on incoming instruction
6252 assert(bInstr->getNumOperands() < 8 && "unexpected number of operands");
6253 MachineOperand& destOper = bInstr->getOperand(0);
6254 MachineOperand* argOpers[6];
6255 int numArgs = bInstr->getNumOperands() - 1;
6256 for (int i=0; i < numArgs; ++i)
6257 argOpers[i] = &bInstr->getOperand(i+1);
6259 // x86 address has 4 operands: base, index, scale, and displacement
6260 int lastAddrIndx = 3; // [0,3]
6263 unsigned t1 = F->getRegInfo().createVirtualRegister(RC);
6264 MachineInstrBuilder MIB = BuildMI(newMBB, TII->get(LoadOpc), t1);
6265 for (int i=0; i <= lastAddrIndx; ++i)
6266 (*MIB).addOperand(*argOpers[i]);
6268 unsigned tt = F->getRegInfo().createVirtualRegister(RC);
6270 MIB = BuildMI(newMBB, TII->get(notOpc), tt).addReg(t1);
6275 unsigned t2 = F->getRegInfo().createVirtualRegister(RC);
6276 assert((argOpers[valArgIndx]->isRegister() ||
6277 argOpers[valArgIndx]->isImmediate()) &&
6279 if (argOpers[valArgIndx]->isRegister())
6280 MIB = BuildMI(newMBB, TII->get(regOpc), t2);
6282 MIB = BuildMI(newMBB, TII->get(immOpc), t2);
6284 (*MIB).addOperand(*argOpers[valArgIndx]);
6286 MIB = BuildMI(newMBB, TII->get(copyOpc), EAXreg);
6289 MIB = BuildMI(newMBB, TII->get(CXchgOpc));
6290 for (int i=0; i <= lastAddrIndx; ++i)
6291 (*MIB).addOperand(*argOpers[i]);
6293 assert(bInstr->hasOneMemOperand() && "Unexpected number of memoperand");
6294 (*MIB).addMemOperand(*F, *bInstr->memoperands_begin());
6296 MIB = BuildMI(newMBB, TII->get(copyOpc), destOper.getReg());
6300 BuildMI(newMBB, TII->get(X86::JNE)).addMBB(newMBB);
6302 F->DeleteMachineInstr(bInstr); // The pseudo instruction is gone now.
6306 // private utility function
6308 X86TargetLowering::EmitAtomicMinMaxWithCustomInserter(MachineInstr *mInstr,
6309 MachineBasicBlock *MBB,
6311 // For the atomic min/max operator, we generate
6314 // ld t1 = [min/max.addr]
6315 // mov t2 = [min/max.val]
6317 // cmov[cond] t2 = t1
6319 // lcs dest = [bitinstr.addr], t2 [EAX is implicit]
6321 // fallthrough -->nextMBB
6323 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
6324 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
6325 MachineFunction::iterator MBBIter = MBB;
6328 /// First build the CFG
6329 MachineFunction *F = MBB->getParent();
6330 MachineBasicBlock *thisMBB = MBB;
6331 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB);
6332 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB);
6333 F->insert(MBBIter, newMBB);
6334 F->insert(MBBIter, nextMBB);
6336 // Move all successors to thisMBB to nextMBB
6337 nextMBB->transferSuccessors(thisMBB);
6339 // Update thisMBB to fall through to newMBB
6340 thisMBB->addSuccessor(newMBB);
6342 // newMBB jumps to newMBB and fall through to nextMBB
6343 newMBB->addSuccessor(nextMBB);
6344 newMBB->addSuccessor(newMBB);
6346 // Insert instructions into newMBB based on incoming instruction
6347 assert(mInstr->getNumOperands() < 8 && "unexpected number of operands");
6348 MachineOperand& destOper = mInstr->getOperand(0);
6349 MachineOperand* argOpers[6];
6350 int numArgs = mInstr->getNumOperands() - 1;
6351 for (int i=0; i < numArgs; ++i)
6352 argOpers[i] = &mInstr->getOperand(i+1);
6354 // x86 address has 4 operands: base, index, scale, and displacement
6355 int lastAddrIndx = 3; // [0,3]
6358 unsigned t1 = F->getRegInfo().createVirtualRegister(X86::GR32RegisterClass);
6359 MachineInstrBuilder MIB = BuildMI(newMBB, TII->get(X86::MOV32rm), t1);
6360 for (int i=0; i <= lastAddrIndx; ++i)
6361 (*MIB).addOperand(*argOpers[i]);
6363 // We only support register and immediate values
6364 assert((argOpers[valArgIndx]->isRegister() ||
6365 argOpers[valArgIndx]->isImmediate()) &&
6368 unsigned t2 = F->getRegInfo().createVirtualRegister(X86::GR32RegisterClass);
6369 if (argOpers[valArgIndx]->isRegister())
6370 MIB = BuildMI(newMBB, TII->get(X86::MOV32rr), t2);
6372 MIB = BuildMI(newMBB, TII->get(X86::MOV32rr), t2);
6373 (*MIB).addOperand(*argOpers[valArgIndx]);
6375 MIB = BuildMI(newMBB, TII->get(X86::MOV32rr), X86::EAX);
6378 MIB = BuildMI(newMBB, TII->get(X86::CMP32rr));
6383 unsigned t3 = F->getRegInfo().createVirtualRegister(X86::GR32RegisterClass);
6384 MIB = BuildMI(newMBB, TII->get(cmovOpc),t3);
6388 // Cmp and exchange if none has modified the memory location
6389 MIB = BuildMI(newMBB, TII->get(X86::LCMPXCHG32));
6390 for (int i=0; i <= lastAddrIndx; ++i)
6391 (*MIB).addOperand(*argOpers[i]);
6393 assert(mInstr->hasOneMemOperand() && "Unexpected number of memoperand");
6394 (*MIB).addMemOperand(*F, *mInstr->memoperands_begin());
6396 MIB = BuildMI(newMBB, TII->get(X86::MOV32rr), destOper.getReg());
6397 MIB.addReg(X86::EAX);
6400 BuildMI(newMBB, TII->get(X86::JNE)).addMBB(newMBB);
6402 F->DeleteMachineInstr(mInstr); // The pseudo instruction is gone now.
6408 X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
6409 MachineBasicBlock *BB) {
6410 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
6411 switch (MI->getOpcode()) {
6412 default: assert(false && "Unexpected instr type to insert");
6413 case X86::CMOV_FR32:
6414 case X86::CMOV_FR64:
6415 case X86::CMOV_V4F32:
6416 case X86::CMOV_V2F64:
6417 case X86::CMOV_V2I64: {
6418 // To "insert" a SELECT_CC instruction, we actually have to insert the
6419 // diamond control-flow pattern. The incoming instruction knows the
6420 // destination vreg to set, the condition code register to branch on, the
6421 // true/false values to select between, and a branch opcode to use.
6422 const BasicBlock *LLVM_BB = BB->getBasicBlock();
6423 MachineFunction::iterator It = BB;
6429 // cmpTY ccX, r1, r2
6431 // fallthrough --> copy0MBB
6432 MachineBasicBlock *thisMBB = BB;
6433 MachineFunction *F = BB->getParent();
6434 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
6435 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
6437 X86::GetCondBranchFromCond((X86::CondCode)MI->getOperand(3).getImm());
6438 BuildMI(BB, TII->get(Opc)).addMBB(sinkMBB);
6439 F->insert(It, copy0MBB);
6440 F->insert(It, sinkMBB);
6441 // Update machine-CFG edges by transferring all successors of the current
6442 // block to the new block which will contain the Phi node for the select.
6443 sinkMBB->transferSuccessors(BB);
6445 // Add the true and fallthrough blocks as its successors.
6446 BB->addSuccessor(copy0MBB);
6447 BB->addSuccessor(sinkMBB);
6450 // %FalseValue = ...
6451 // # fallthrough to sinkMBB
6454 // Update machine-CFG edges
6455 BB->addSuccessor(sinkMBB);
6458 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
6461 BuildMI(BB, TII->get(X86::PHI), MI->getOperand(0).getReg())
6462 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB)
6463 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
6465 F->DeleteMachineInstr(MI); // The pseudo instruction is gone now.
6469 case X86::FP32_TO_INT16_IN_MEM:
6470 case X86::FP32_TO_INT32_IN_MEM:
6471 case X86::FP32_TO_INT64_IN_MEM:
6472 case X86::FP64_TO_INT16_IN_MEM:
6473 case X86::FP64_TO_INT32_IN_MEM:
6474 case X86::FP64_TO_INT64_IN_MEM:
6475 case X86::FP80_TO_INT16_IN_MEM:
6476 case X86::FP80_TO_INT32_IN_MEM:
6477 case X86::FP80_TO_INT64_IN_MEM: {
6478 // Change the floating point control register to use "round towards zero"
6479 // mode when truncating to an integer value.
6480 MachineFunction *F = BB->getParent();
6481 int CWFrameIdx = F->getFrameInfo()->CreateStackObject(2, 2);
6482 addFrameReference(BuildMI(BB, TII->get(X86::FNSTCW16m)), CWFrameIdx);
6484 // Load the old value of the high byte of the control word...
6486 F->getRegInfo().createVirtualRegister(X86::GR16RegisterClass);
6487 addFrameReference(BuildMI(BB, TII->get(X86::MOV16rm), OldCW), CWFrameIdx);
6489 // Set the high part to be round to zero...
6490 addFrameReference(BuildMI(BB, TII->get(X86::MOV16mi)), CWFrameIdx)
6493 // Reload the modified control word now...
6494 addFrameReference(BuildMI(BB, TII->get(X86::FLDCW16m)), CWFrameIdx);
6496 // Restore the memory image of control word to original value
6497 addFrameReference(BuildMI(BB, TII->get(X86::MOV16mr)), CWFrameIdx)
6500 // Get the X86 opcode to use.
6502 switch (MI->getOpcode()) {
6503 default: assert(0 && "illegal opcode!");
6504 case X86::FP32_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m32; break;
6505 case X86::FP32_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m32; break;
6506 case X86::FP32_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m32; break;
6507 case X86::FP64_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m64; break;
6508 case X86::FP64_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m64; break;
6509 case X86::FP64_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m64; break;
6510 case X86::FP80_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m80; break;
6511 case X86::FP80_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m80; break;
6512 case X86::FP80_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m80; break;
6516 MachineOperand &Op = MI->getOperand(0);
6517 if (Op.isRegister()) {
6518 AM.BaseType = X86AddressMode::RegBase;
6519 AM.Base.Reg = Op.getReg();
6521 AM.BaseType = X86AddressMode::FrameIndexBase;
6522 AM.Base.FrameIndex = Op.getIndex();
6524 Op = MI->getOperand(1);
6525 if (Op.isImmediate())
6526 AM.Scale = Op.getImm();
6527 Op = MI->getOperand(2);
6528 if (Op.isImmediate())
6529 AM.IndexReg = Op.getImm();
6530 Op = MI->getOperand(3);
6531 if (Op.isGlobalAddress()) {
6532 AM.GV = Op.getGlobal();
6534 AM.Disp = Op.getImm();
6536 addFullAddress(BuildMI(BB, TII->get(Opc)), AM)
6537 .addReg(MI->getOperand(4).getReg());
6539 // Reload the original control word now.
6540 addFrameReference(BuildMI(BB, TII->get(X86::FLDCW16m)), CWFrameIdx);
6542 F->DeleteMachineInstr(MI); // The pseudo instruction is gone now.
6545 case X86::ATOMAND32:
6546 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND32rr,
6547 X86::AND32ri, X86::MOV32rm,
6548 X86::LCMPXCHG32, X86::MOV32rr,
6549 X86::NOT32r, X86::EAX,
6550 X86::GR32RegisterClass);
6552 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR32rr,
6553 X86::OR32ri, X86::MOV32rm,
6554 X86::LCMPXCHG32, X86::MOV32rr,
6555 X86::NOT32r, X86::EAX,
6556 X86::GR32RegisterClass);
6557 case X86::ATOMXOR32:
6558 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR32rr,
6559 X86::XOR32ri, X86::MOV32rm,
6560 X86::LCMPXCHG32, X86::MOV32rr,
6561 X86::NOT32r, X86::EAX,
6562 X86::GR32RegisterClass);
6563 case X86::ATOMNAND32:
6564 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND32rr,
6565 X86::AND32ri, X86::MOV32rm,
6566 X86::LCMPXCHG32, X86::MOV32rr,
6567 X86::NOT32r, X86::EAX,
6568 X86::GR32RegisterClass, true);
6569 case X86::ATOMMIN32:
6570 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL32rr);
6571 case X86::ATOMMAX32:
6572 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG32rr);
6573 case X86::ATOMUMIN32:
6574 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB32rr);
6575 case X86::ATOMUMAX32:
6576 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA32rr);
6578 case X86::ATOMAND16:
6579 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND16rr,
6580 X86::AND16ri, X86::MOV16rm,
6581 X86::LCMPXCHG16, X86::MOV16rr,
6582 X86::NOT16r, X86::AX,
6583 X86::GR16RegisterClass);
6585 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR16rr,
6586 X86::OR16ri, X86::MOV16rm,
6587 X86::LCMPXCHG16, X86::MOV16rr,
6588 X86::NOT16r, X86::AX,
6589 X86::GR16RegisterClass);
6590 case X86::ATOMXOR16:
6591 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR16rr,
6592 X86::XOR16ri, X86::MOV16rm,
6593 X86::LCMPXCHG16, X86::MOV16rr,
6594 X86::NOT16r, X86::AX,
6595 X86::GR16RegisterClass);
6596 case X86::ATOMNAND16:
6597 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND16rr,
6598 X86::AND16ri, X86::MOV16rm,
6599 X86::LCMPXCHG16, X86::MOV16rr,
6600 X86::NOT16r, X86::AX,
6601 X86::GR16RegisterClass, true);
6602 case X86::ATOMMIN16:
6603 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL16rr);
6604 case X86::ATOMMAX16:
6605 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG16rr);
6606 case X86::ATOMUMIN16:
6607 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB16rr);
6608 case X86::ATOMUMAX16:
6609 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA16rr);
6612 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND8rr,
6613 X86::AND8ri, X86::MOV8rm,
6614 X86::LCMPXCHG8, X86::MOV8rr,
6615 X86::NOT8r, X86::AL,
6616 X86::GR8RegisterClass);
6618 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR8rr,
6619 X86::OR8ri, X86::MOV8rm,
6620 X86::LCMPXCHG8, X86::MOV8rr,
6621 X86::NOT8r, X86::AL,
6622 X86::GR8RegisterClass);
6624 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR8rr,
6625 X86::XOR8ri, X86::MOV8rm,
6626 X86::LCMPXCHG8, X86::MOV8rr,
6627 X86::NOT8r, X86::AL,
6628 X86::GR8RegisterClass);
6629 case X86::ATOMNAND8:
6630 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND8rr,
6631 X86::AND8ri, X86::MOV8rm,
6632 X86::LCMPXCHG8, X86::MOV8rr,
6633 X86::NOT8r, X86::AL,
6634 X86::GR8RegisterClass, true);
6635 // FIXME: There are no CMOV8 instructions; MIN/MAX need some other way.
6636 case X86::ATOMAND64:
6637 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND64rr,
6638 X86::AND64ri32, X86::MOV64rm,
6639 X86::LCMPXCHG64, X86::MOV64rr,
6640 X86::NOT64r, X86::RAX,
6641 X86::GR64RegisterClass);
6643 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR64rr,
6644 X86::OR64ri32, X86::MOV64rm,
6645 X86::LCMPXCHG64, X86::MOV64rr,
6646 X86::NOT64r, X86::RAX,
6647 X86::GR64RegisterClass);
6648 case X86::ATOMXOR64:
6649 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR64rr,
6650 X86::XOR64ri32, X86::MOV64rm,
6651 X86::LCMPXCHG64, X86::MOV64rr,
6652 X86::NOT64r, X86::RAX,
6653 X86::GR64RegisterClass);
6654 case X86::ATOMNAND64:
6655 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND64rr,
6656 X86::AND64ri32, X86::MOV64rm,
6657 X86::LCMPXCHG64, X86::MOV64rr,
6658 X86::NOT64r, X86::RAX,
6659 X86::GR64RegisterClass, true);
6660 case X86::ATOMMIN64:
6661 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL64rr);
6662 case X86::ATOMMAX64:
6663 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG64rr);
6664 case X86::ATOMUMIN64:
6665 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB64rr);
6666 case X86::ATOMUMAX64:
6667 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA64rr);
6671 //===----------------------------------------------------------------------===//
6672 // X86 Optimization Hooks
6673 //===----------------------------------------------------------------------===//
6675 void X86TargetLowering::computeMaskedBitsForTargetNode(const SDValue Op,
6679 const SelectionDAG &DAG,
6680 unsigned Depth) const {
6681 unsigned Opc = Op.getOpcode();
6682 assert((Opc >= ISD::BUILTIN_OP_END ||
6683 Opc == ISD::INTRINSIC_WO_CHAIN ||
6684 Opc == ISD::INTRINSIC_W_CHAIN ||
6685 Opc == ISD::INTRINSIC_VOID) &&
6686 "Should use MaskedValueIsZero if you don't know whether Op"
6687 " is a target node!");
6689 KnownZero = KnownOne = APInt(Mask.getBitWidth(), 0); // Don't know anything.
6693 KnownZero |= APInt::getHighBitsSet(Mask.getBitWidth(),
6694 Mask.getBitWidth() - 1);
6699 /// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the
6700 /// node is a GlobalAddress + offset.
6701 bool X86TargetLowering::isGAPlusOffset(SDNode *N,
6702 GlobalValue* &GA, int64_t &Offset) const{
6703 if (N->getOpcode() == X86ISD::Wrapper) {
6704 if (isa<GlobalAddressSDNode>(N->getOperand(0))) {
6705 GA = cast<GlobalAddressSDNode>(N->getOperand(0))->getGlobal();
6709 return TargetLowering::isGAPlusOffset(N, GA, Offset);
6712 static bool isBaseAlignmentOfN(unsigned N, SDNode *Base,
6713 const TargetLowering &TLI) {
6716 if (TLI.isGAPlusOffset(Base, GV, Offset))
6717 return (GV->getAlignment() >= N && (Offset % N) == 0);
6718 // DAG combine handles the stack object case.
6722 static bool EltsFromConsecutiveLoads(SDNode *N, SDValue PermMask,
6723 unsigned NumElems, MVT EVT,
6725 SelectionDAG &DAG, MachineFrameInfo *MFI,
6726 const TargetLowering &TLI) {
6728 for (unsigned i = 0; i < NumElems; ++i) {
6729 SDValue Idx = PermMask.getOperand(i);
6730 if (Idx.getOpcode() == ISD::UNDEF) {
6736 SDValue Elt = DAG.getShuffleScalarElt(N, i);
6737 if (!Elt.getNode() ||
6738 (Elt.getOpcode() != ISD::UNDEF && !ISD::isNON_EXTLoad(Elt.getNode())))
6741 Base = Elt.getNode();
6742 if (Base->getOpcode() == ISD::UNDEF)
6746 if (Elt.getOpcode() == ISD::UNDEF)
6749 if (!TLI.isConsecutiveLoad(Elt.getNode(), Base,
6750 EVT.getSizeInBits()/8, i, MFI))
6756 /// PerformShuffleCombine - Combine a vector_shuffle that is equal to
6757 /// build_vector load1, load2, load3, load4, <0, 1, 2, 3> into a 128-bit load
6758 /// if the load addresses are consecutive, non-overlapping, and in the right
6760 static SDValue PerformShuffleCombine(SDNode *N, SelectionDAG &DAG,
6761 const TargetLowering &TLI) {
6762 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
6763 MVT VT = N->getValueType(0);
6764 MVT EVT = VT.getVectorElementType();
6765 SDValue PermMask = N->getOperand(2);
6766 unsigned NumElems = PermMask.getNumOperands();
6767 SDNode *Base = NULL;
6768 if (!EltsFromConsecutiveLoads(N, PermMask, NumElems, EVT, Base,
6772 LoadSDNode *LD = cast<LoadSDNode>(Base);
6773 if (isBaseAlignmentOfN(16, Base->getOperand(1).getNode(), TLI))
6774 return DAG.getLoad(VT, LD->getChain(), LD->getBasePtr(), LD->getSrcValue(),
6775 LD->getSrcValueOffset(), LD->isVolatile());
6776 return DAG.getLoad(VT, LD->getChain(), LD->getBasePtr(), LD->getSrcValue(),
6777 LD->getSrcValueOffset(), LD->isVolatile(),
6778 LD->getAlignment());
6781 /// PerformBuildVectorCombine - build_vector 0,(load i64 / f64) -> movq / movsd.
6782 static SDValue PerformBuildVectorCombine(SDNode *N, SelectionDAG &DAG,
6783 const X86Subtarget *Subtarget,
6784 const TargetLowering &TLI) {
6785 unsigned NumOps = N->getNumOperands();
6787 // Ignore single operand BUILD_VECTOR.
6791 MVT VT = N->getValueType(0);
6792 MVT EVT = VT.getVectorElementType();
6793 if ((EVT != MVT::i64 && EVT != MVT::f64) || Subtarget->is64Bit())
6794 // We are looking for load i64 and zero extend. We want to transform
6795 // it before legalizer has a chance to expand it. Also look for i64
6796 // BUILD_PAIR bit casted to f64.
6798 // This must be an insertion into a zero vector.
6799 SDValue HighElt = N->getOperand(1);
6800 if (!isZeroNode(HighElt))
6803 // Value must be a load.
6804 SDNode *Base = N->getOperand(0).getNode();
6805 if (!isa<LoadSDNode>(Base)) {
6806 if (Base->getOpcode() != ISD::BIT_CONVERT)
6808 Base = Base->getOperand(0).getNode();
6809 if (!isa<LoadSDNode>(Base))
6813 // Transform it into VZEXT_LOAD addr.
6814 LoadSDNode *LD = cast<LoadSDNode>(Base);
6816 // Load must not be an extload.
6817 if (LD->getExtensionType() != ISD::NON_EXTLOAD)
6820 return DAG.getNode(X86ISD::VZEXT_LOAD, VT, LD->getChain(), LD->getBasePtr());
6823 /// PerformSELECTCombine - Do target-specific dag combines on SELECT nodes.
6824 static SDValue PerformSELECTCombine(SDNode *N, SelectionDAG &DAG,
6825 const X86Subtarget *Subtarget) {
6826 SDValue Cond = N->getOperand(0);
6828 // If we have SSE[12] support, try to form min/max nodes.
6829 if (Subtarget->hasSSE2() &&
6830 (N->getValueType(0) == MVT::f32 || N->getValueType(0) == MVT::f64)) {
6831 if (Cond.getOpcode() == ISD::SETCC) {
6832 // Get the LHS/RHS of the select.
6833 SDValue LHS = N->getOperand(1);
6834 SDValue RHS = N->getOperand(2);
6835 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
6837 unsigned Opcode = 0;
6838 if (LHS == Cond.getOperand(0) && RHS == Cond.getOperand(1)) {
6841 case ISD::SETOLE: // (X <= Y) ? X : Y -> min
6844 if (!UnsafeFPMath) break;
6846 case ISD::SETOLT: // (X olt/lt Y) ? X : Y -> min
6848 Opcode = X86ISD::FMIN;
6851 case ISD::SETOGT: // (X > Y) ? X : Y -> max
6854 if (!UnsafeFPMath) break;
6856 case ISD::SETUGE: // (X uge/ge Y) ? X : Y -> max
6858 Opcode = X86ISD::FMAX;
6861 } else if (LHS == Cond.getOperand(1) && RHS == Cond.getOperand(0)) {
6864 case ISD::SETOGT: // (X > Y) ? Y : X -> min
6867 if (!UnsafeFPMath) break;
6869 case ISD::SETUGE: // (X uge/ge Y) ? Y : X -> min
6871 Opcode = X86ISD::FMIN;
6874 case ISD::SETOLE: // (X <= Y) ? Y : X -> max
6877 if (!UnsafeFPMath) break;
6879 case ISD::SETOLT: // (X olt/lt Y) ? Y : X -> max
6881 Opcode = X86ISD::FMAX;
6887 return DAG.getNode(Opcode, N->getValueType(0), LHS, RHS);
6895 /// PerformSTORECombine - Do target-specific dag combines on STORE nodes.
6896 static SDValue PerformSTORECombine(SDNode *N, SelectionDAG &DAG,
6897 const X86Subtarget *Subtarget) {
6898 // Turn load->store of MMX types into GPR load/stores. This avoids clobbering
6899 // the FP state in cases where an emms may be missing.
6900 // A preferable solution to the general problem is to figure out the right
6901 // places to insert EMMS. This qualifies as a quick hack.
6902 StoreSDNode *St = cast<StoreSDNode>(N);
6903 if (St->getValue().getValueType().isVector() &&
6904 St->getValue().getValueType().getSizeInBits() == 64 &&
6905 isa<LoadSDNode>(St->getValue()) &&
6906 !cast<LoadSDNode>(St->getValue())->isVolatile() &&
6907 St->getChain().hasOneUse() && !St->isVolatile()) {
6908 SDNode* LdVal = St->getValue().getNode();
6910 int TokenFactorIndex = -1;
6911 SmallVector<SDValue, 8> Ops;
6912 SDNode* ChainVal = St->getChain().getNode();
6913 // Must be a store of a load. We currently handle two cases: the load
6914 // is a direct child, and it's under an intervening TokenFactor. It is
6915 // possible to dig deeper under nested TokenFactors.
6916 if (ChainVal == LdVal)
6917 Ld = cast<LoadSDNode>(St->getChain());
6918 else if (St->getValue().hasOneUse() &&
6919 ChainVal->getOpcode() == ISD::TokenFactor) {
6920 for (unsigned i=0, e = ChainVal->getNumOperands(); i != e; ++i) {
6921 if (ChainVal->getOperand(i).getNode() == LdVal) {
6922 TokenFactorIndex = i;
6923 Ld = cast<LoadSDNode>(St->getValue());
6925 Ops.push_back(ChainVal->getOperand(i));
6929 // If we are a 64-bit capable x86, lower to a single movq load/store pair.
6930 if (Subtarget->is64Bit()) {
6931 SDValue NewLd = DAG.getLoad(MVT::i64, Ld->getChain(),
6932 Ld->getBasePtr(), Ld->getSrcValue(),
6933 Ld->getSrcValueOffset(), Ld->isVolatile(),
6934 Ld->getAlignment());
6935 SDValue NewChain = NewLd.getValue(1);
6936 if (TokenFactorIndex != -1) {
6937 Ops.push_back(NewChain);
6938 NewChain = DAG.getNode(ISD::TokenFactor, MVT::Other, &Ops[0],
6941 return DAG.getStore(NewChain, NewLd, St->getBasePtr(),
6942 St->getSrcValue(), St->getSrcValueOffset(),
6943 St->isVolatile(), St->getAlignment());
6946 // Otherwise, lower to two 32-bit copies.
6947 SDValue LoAddr = Ld->getBasePtr();
6948 SDValue HiAddr = DAG.getNode(ISD::ADD, MVT::i32, LoAddr,
6949 DAG.getConstant(4, MVT::i32));
6951 SDValue LoLd = DAG.getLoad(MVT::i32, Ld->getChain(), LoAddr,
6952 Ld->getSrcValue(), Ld->getSrcValueOffset(),
6953 Ld->isVolatile(), Ld->getAlignment());
6954 SDValue HiLd = DAG.getLoad(MVT::i32, Ld->getChain(), HiAddr,
6955 Ld->getSrcValue(), Ld->getSrcValueOffset()+4,
6957 MinAlign(Ld->getAlignment(), 4));
6959 SDValue NewChain = LoLd.getValue(1);
6960 if (TokenFactorIndex != -1) {
6961 Ops.push_back(LoLd);
6962 Ops.push_back(HiLd);
6963 NewChain = DAG.getNode(ISD::TokenFactor, MVT::Other, &Ops[0],
6967 LoAddr = St->getBasePtr();
6968 HiAddr = DAG.getNode(ISD::ADD, MVT::i32, LoAddr,
6969 DAG.getConstant(4, MVT::i32));
6971 SDValue LoSt = DAG.getStore(NewChain, LoLd, LoAddr,
6972 St->getSrcValue(), St->getSrcValueOffset(),
6973 St->isVolatile(), St->getAlignment());
6974 SDValue HiSt = DAG.getStore(NewChain, HiLd, HiAddr,
6976 St->getSrcValueOffset() + 4,
6978 MinAlign(St->getAlignment(), 4));
6979 return DAG.getNode(ISD::TokenFactor, MVT::Other, LoSt, HiSt);
6985 /// PerformFORCombine - Do target-specific dag combines on X86ISD::FOR and
6986 /// X86ISD::FXOR nodes.
6987 static SDValue PerformFORCombine(SDNode *N, SelectionDAG &DAG) {
6988 assert(N->getOpcode() == X86ISD::FOR || N->getOpcode() == X86ISD::FXOR);
6989 // F[X]OR(0.0, x) -> x
6990 // F[X]OR(x, 0.0) -> x
6991 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
6992 if (C->getValueAPF().isPosZero())
6993 return N->getOperand(1);
6994 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
6995 if (C->getValueAPF().isPosZero())
6996 return N->getOperand(0);
7000 /// PerformFANDCombine - Do target-specific dag combines on X86ISD::FAND nodes.
7001 static SDValue PerformFANDCombine(SDNode *N, SelectionDAG &DAG) {
7002 // FAND(0.0, x) -> 0.0
7003 // FAND(x, 0.0) -> 0.0
7004 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
7005 if (C->getValueAPF().isPosZero())
7006 return N->getOperand(0);
7007 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
7008 if (C->getValueAPF().isPosZero())
7009 return N->getOperand(1);
7014 SDValue X86TargetLowering::PerformDAGCombine(SDNode *N,
7015 DAGCombinerInfo &DCI) const {
7016 SelectionDAG &DAG = DCI.DAG;
7017 switch (N->getOpcode()) {
7019 case ISD::VECTOR_SHUFFLE: return PerformShuffleCombine(N, DAG, *this);
7020 case ISD::BUILD_VECTOR:
7021 return PerformBuildVectorCombine(N, DAG, Subtarget, *this);
7022 case ISD::SELECT: return PerformSELECTCombine(N, DAG, Subtarget);
7023 case ISD::STORE: return PerformSTORECombine(N, DAG, Subtarget);
7025 case X86ISD::FOR: return PerformFORCombine(N, DAG);
7026 case X86ISD::FAND: return PerformFANDCombine(N, DAG);
7032 //===----------------------------------------------------------------------===//
7033 // X86 Inline Assembly Support
7034 //===----------------------------------------------------------------------===//
7036 /// getConstraintType - Given a constraint letter, return the type of
7037 /// constraint it is for this target.
7038 X86TargetLowering::ConstraintType
7039 X86TargetLowering::getConstraintType(const std::string &Constraint) const {
7040 if (Constraint.size() == 1) {
7041 switch (Constraint[0]) {
7052 return C_RegisterClass;
7057 return TargetLowering::getConstraintType(Constraint);
7060 /// LowerXConstraint - try to replace an X constraint, which matches anything,
7061 /// with another that has more specific requirements based on the type of the
7062 /// corresponding operand.
7063 const char *X86TargetLowering::
7064 LowerXConstraint(MVT ConstraintVT) const {
7065 // FP X constraints get lowered to SSE1/2 registers if available, otherwise
7066 // 'f' like normal targets.
7067 if (ConstraintVT.isFloatingPoint()) {
7068 if (Subtarget->hasSSE2())
7070 if (Subtarget->hasSSE1())
7074 return TargetLowering::LowerXConstraint(ConstraintVT);
7077 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
7078 /// vector. If it is invalid, don't add anything to Ops.
7079 void X86TargetLowering::LowerAsmOperandForConstraint(SDValue Op,
7081 std::vector<SDValue>&Ops,
7082 SelectionDAG &DAG) const {
7083 SDValue Result(0, 0);
7085 switch (Constraint) {
7088 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
7089 if (C->getZExtValue() <= 31) {
7090 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
7096 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
7097 if (C->getZExtValue() <= 255) {
7098 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
7104 // Literal immediates are always ok.
7105 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op)) {
7106 Result = DAG.getTargetConstant(CST->getZExtValue(), Op.getValueType());
7110 // If we are in non-pic codegen mode, we allow the address of a global (with
7111 // an optional displacement) to be used with 'i'.
7112 GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(Op);
7115 // Match either (GA) or (GA+C)
7117 Offset = GA->getOffset();
7118 } else if (Op.getOpcode() == ISD::ADD) {
7119 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
7120 GA = dyn_cast<GlobalAddressSDNode>(Op.getOperand(0));
7122 Offset = GA->getOffset()+C->getZExtValue();
7124 C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
7125 GA = dyn_cast<GlobalAddressSDNode>(Op.getOperand(0));
7127 Offset = GA->getOffset()+C->getZExtValue();
7134 // If addressing this global requires a load (e.g. in PIC mode), we can't
7136 if (Subtarget->GVRequiresExtraLoad(GA->getGlobal(), getTargetMachine(),
7140 Op = DAG.getTargetGlobalAddress(GA->getGlobal(), GA->getValueType(0),
7146 // Otherwise, not valid for this mode.
7151 if (Result.getNode()) {
7152 Ops.push_back(Result);
7155 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
7158 std::vector<unsigned> X86TargetLowering::
7159 getRegClassForInlineAsmConstraint(const std::string &Constraint,
7161 if (Constraint.size() == 1) {
7162 // FIXME: not handling fp-stack yet!
7163 switch (Constraint[0]) { // GCC X86 Constraint Letters
7164 default: break; // Unknown constraint letter
7165 case 'A': // EAX/EDX
7166 if (VT == MVT::i32 || VT == MVT::i64)
7167 return make_vector<unsigned>(X86::EAX, X86::EDX, 0);
7169 case 'q': // Q_REGS (GENERAL_REGS in 64-bit mode)
7172 return make_vector<unsigned>(X86::EAX, X86::EDX, X86::ECX, X86::EBX, 0);
7173 else if (VT == MVT::i16)
7174 return make_vector<unsigned>(X86::AX, X86::DX, X86::CX, X86::BX, 0);
7175 else if (VT == MVT::i8)
7176 return make_vector<unsigned>(X86::AL, X86::DL, X86::CL, X86::BL, 0);
7177 else if (VT == MVT::i64)
7178 return make_vector<unsigned>(X86::RAX, X86::RDX, X86::RCX, X86::RBX, 0);
7183 return std::vector<unsigned>();
7186 std::pair<unsigned, const TargetRegisterClass*>
7187 X86TargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
7189 // First, see if this is a constraint that directly corresponds to an LLVM
7191 if (Constraint.size() == 1) {
7192 // GCC Constraint Letters
7193 switch (Constraint[0]) {
7195 case 'r': // GENERAL_REGS
7196 case 'R': // LEGACY_REGS
7197 case 'l': // INDEX_REGS
7198 if (VT == MVT::i64 && Subtarget->is64Bit())
7199 return std::make_pair(0U, X86::GR64RegisterClass);
7201 return std::make_pair(0U, X86::GR32RegisterClass);
7202 else if (VT == MVT::i16)
7203 return std::make_pair(0U, X86::GR16RegisterClass);
7204 else if (VT == MVT::i8)
7205 return std::make_pair(0U, X86::GR8RegisterClass);
7207 case 'f': // FP Stack registers.
7208 // If SSE is enabled for this VT, use f80 to ensure the isel moves the
7209 // value to the correct fpstack register class.
7210 if (VT == MVT::f32 && !isScalarFPTypeInSSEReg(VT))
7211 return std::make_pair(0U, X86::RFP32RegisterClass);
7212 if (VT == MVT::f64 && !isScalarFPTypeInSSEReg(VT))
7213 return std::make_pair(0U, X86::RFP64RegisterClass);
7214 return std::make_pair(0U, X86::RFP80RegisterClass);
7215 case 'y': // MMX_REGS if MMX allowed.
7216 if (!Subtarget->hasMMX()) break;
7217 return std::make_pair(0U, X86::VR64RegisterClass);
7219 case 'Y': // SSE_REGS if SSE2 allowed
7220 if (!Subtarget->hasSSE2()) break;
7222 case 'x': // SSE_REGS if SSE1 allowed
7223 if (!Subtarget->hasSSE1()) break;
7225 switch (VT.getSimpleVT()) {
7227 // Scalar SSE types.
7230 return std::make_pair(0U, X86::FR32RegisterClass);
7233 return std::make_pair(0U, X86::FR64RegisterClass);
7241 return std::make_pair(0U, X86::VR128RegisterClass);
7247 // Use the default implementation in TargetLowering to convert the register
7248 // constraint into a member of a register class.
7249 std::pair<unsigned, const TargetRegisterClass*> Res;
7250 Res = TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
7252 // Not found as a standard register?
7253 if (Res.second == 0) {
7254 // GCC calls "st(0)" just plain "st".
7255 if (StringsEqualNoCase("{st}", Constraint)) {
7256 Res.first = X86::ST0;
7257 Res.second = X86::RFP80RegisterClass;
7263 // Otherwise, check to see if this is a register class of the wrong value
7264 // type. For example, we want to map "{ax},i32" -> {eax}, we don't want it to
7265 // turn into {ax},{dx}.
7266 if (Res.second->hasType(VT))
7267 return Res; // Correct type already, nothing to do.
7269 // All of the single-register GCC register classes map their values onto
7270 // 16-bit register pieces "ax","dx","cx","bx","si","di","bp","sp". If we
7271 // really want an 8-bit or 32-bit register, map to the appropriate register
7272 // class and return the appropriate register.
7273 if (Res.second == X86::GR16RegisterClass) {
7274 if (VT == MVT::i8) {
7275 unsigned DestReg = 0;
7276 switch (Res.first) {
7278 case X86::AX: DestReg = X86::AL; break;
7279 case X86::DX: DestReg = X86::DL; break;
7280 case X86::CX: DestReg = X86::CL; break;
7281 case X86::BX: DestReg = X86::BL; break;
7284 Res.first = DestReg;
7285 Res.second = Res.second = X86::GR8RegisterClass;
7287 } else if (VT == MVT::i32) {
7288 unsigned DestReg = 0;
7289 switch (Res.first) {
7291 case X86::AX: DestReg = X86::EAX; break;
7292 case X86::DX: DestReg = X86::EDX; break;
7293 case X86::CX: DestReg = X86::ECX; break;
7294 case X86::BX: DestReg = X86::EBX; break;
7295 case X86::SI: DestReg = X86::ESI; break;
7296 case X86::DI: DestReg = X86::EDI; break;
7297 case X86::BP: DestReg = X86::EBP; break;
7298 case X86::SP: DestReg = X86::ESP; break;
7301 Res.first = DestReg;
7302 Res.second = Res.second = X86::GR32RegisterClass;
7304 } else if (VT == MVT::i64) {
7305 unsigned DestReg = 0;
7306 switch (Res.first) {
7308 case X86::AX: DestReg = X86::RAX; break;
7309 case X86::DX: DestReg = X86::RDX; break;
7310 case X86::CX: DestReg = X86::RCX; break;
7311 case X86::BX: DestReg = X86::RBX; break;
7312 case X86::SI: DestReg = X86::RSI; break;
7313 case X86::DI: DestReg = X86::RDI; break;
7314 case X86::BP: DestReg = X86::RBP; break;
7315 case X86::SP: DestReg = X86::RSP; break;
7318 Res.first = DestReg;
7319 Res.second = Res.second = X86::GR64RegisterClass;
7322 } else if (Res.second == X86::FR32RegisterClass ||
7323 Res.second == X86::FR64RegisterClass ||
7324 Res.second == X86::VR128RegisterClass) {
7325 // Handle references to XMM physical registers that got mapped into the
7326 // wrong class. This can happen with constraints like {xmm0} where the
7327 // target independent register mapper will just pick the first match it can
7328 // find, ignoring the required type.
7330 Res.second = X86::FR32RegisterClass;
7331 else if (VT == MVT::f64)
7332 Res.second = X86::FR64RegisterClass;
7333 else if (X86::VR128RegisterClass->hasType(VT))
7334 Res.second = X86::VR128RegisterClass;